1984_Burr Brown_Product_Data_Book 1984 Burr Brown Product Data Book

User Manual: 1984_Burr-Brown_Product_Data_Book
Open the PDF directly: View PDF .
Page Count: 1260
Download
Open PDF In Browser	View PDF
, m~

II

mlz
@

m

c:

::zJ
::zJ
I

m
::zJ

o
=e

z

"'C

ac.
c
n

...c.
m

Dr
tr
o
o
~

product data book
BURR-BROWN®

I

II

I

MODEL INDEX
Model

Page

ADC10HT ............ 5-3
ADC60 ............. 5-13
ADC71 ............. 5-19
ADC72 ............. 5-27
ADC73 ............. 5-35
ADC76 ............. 5-46
ADC80 ............. 5-54
ADC82 ............. 5-62
ADC84 ............. 5-70
ADC85 ............. 5-70
ADC87/MIL ........ 11-8
ADC100 ............ 5-78
ADC731 . . . . . . . . . . .. 5-35
ADC803 ............ 5-86
DAC10HT ............ 6-5
DAC60 ............. 6-13
DAC63 ............. 6-18
DAC70 ............. 6-26
DAC71 ............. 6-34
DAC72 ............. 6-44
DAC73 ............. 6-54
DACf4 ............. 6-62
DAC80 ............. 6-77
DAC82 ............. 6-87
DAC85 ............. 6-94
DAC87/MIL ....... 11-24
DAC87-CBI-1 ...... 11-36
DAC90 ............ 6-102
DAC700 ........... 6-107
DAC701 ........... 6-107
DAC702 ........... 6-107
DAC703 ........... 6-107
DAC706 ........... 6-115
DAC707 ........... 6-115
DAC708 ........... 6-115
DAC709 ........... 6-115
DAC736. . . . . . . . . . .. 6-54
DAC800 ........... 6-126
DAC811 ........... 6-133
DAC812 ........... 6-141
DAC850 ........... 6-147
DAC851 ........... 6-147
DAC870/MIL ...... 11-48
DIV100 ............... 4-6
INA101 ............... 2-7
INA104 ............. 2-15
INA258/MIL ....... 11-61
IS0100 ............... 3-6
LOG100 ............ 4-14
MCS Series ........ 15-1
MICROMUX II ...... 15-2
MP10 ................ 8-3
MP11 ................ 8-3
MP20 .............. 8-11
MP21 .............. 8-23
MP22BG ........... 8-35
MP32BG ........... 8-43
MP701 ............. 14-4
MP702 ............. 14-4
MP710 ............. 14-6
MP801 ............. 14-8
MP802 ............. 14-8

Model

Page

MP810 ............ 14-10
MP820 ............ 14-12
MP821 ............ 14-12
MP830 ............ 14-13
MP1104 ........... 14-14
MP1216 ........... 14-16
MP2216 ........... 14-19
MP6102 ........... 14-21
MP6202 ........... 14-23
MP6303 ........... 14-24
MP6304 ........... 14-25
MP6305 ........... 14-26
MP6309 ........... 14-27
MP6311 ........... 14-28
M P6394 . . . . . . . . . .. 14-30
MP6421 ........... 14-32
MP7104 ........... 14-33
MP7218 ........... 14-37
MP7408 ........... 14-39
MP7504 ........... 14-41
MP7608 ........... 14-43
M P8304 . . . . . . . . . .. 14-45
MP8316 ........... 14-49
MP8418 ........... 14-51
MP8418-EXP ...... 14-55
MP8418-ISOE ..... 14-57
MP8430 ........... 14-58
MP8450 ........... 14-60
MP8608 ........... 14-69
MPC4D .............. 9-3
MPC8D ............ 9-10
MPC8S .............. 9-3
MPC16S ........... 9-10
MPC800 ............ 9-17
MPC801 ............ 9-24
MPV901 ........... 14-72
MPV904 ........... 14-79
MPV950 ........... 14-84
MPY100 ............ 4-22
OPA11HT ............ 1-9
OPA21 ............. 1-13
OPA27 ............. 1-17
OPA37. ............ 1-17
OPA100 ............ 1-25
OPA101 ............ 1-31
OPA102 ............ 1-31
OPA103 ............ 1-43
OPA104 ............ 1-47
OPA105/MIL ...... 11-74
OPA106/MIL ...... 11-84
OPA111 ............ 1-51
OPA201 ............ 1-61
OPA501 ............ 1-69
OPA600/MIL ...... 11-94
OPA605 ............ 1-77
OPA8780/MIL .... 11-110
PCI-3000 ........... 16-1
PCM51 ............ 6-154
PCM52 ............ 6-162
PCM53 ............ 6-162
PCM75 ............. 5-98
PGA100 ............ 2-26

Model

Page

PGA200 .. .. .. .. .... 2-34
PGA201 ............ 2-34
PSB100 ............ 12-7
PWR70 ............. 12-9
REF10 ............. 4-30
REF101 ............ 4-36
SDM853 ............ 8-59
SDM854 ............ 8-65
SDM856 ............ 8-81
SDM857 ............ 8-81
SDM858 ............ 8-87
SHC80 .........•..... 7-3
SHC85 ............... 7-7
SHC298AM ......... 7-11
SHC803 ............ 7-17
SHC804 ............ 7-17
SHM60.
7-23
TM25 .............. 13-5
TM27 .............. 13-5
TM70 .............. 13-4
TM71 .............. 13-2
TM71B ............. 13-3
TM71110 ........... 13-3
TM71MS ........... 13-3
TM76 .............. 13-4
TM77 .............. 13-2
TM77B ............. 13-3
TM77110 ........... 13-3
TM77MS ........... 13-3
TMC900 ............ 13-8
UAF11 ............. 4-44
UAF21 ............. 4-44
UAF31 ............. 4-52
UAF41 ............. 4-60
VFC32 ............. 10-3
VFC32/MIL ....... 11-120
VFC42 ............ 10-11
VFC52 ............ 10-11
VFC62 ............ 10-17
VFC320 ........... 10-25
XTR100 ............ 2-40
100MS ............. 3-17
546 ................ 12-3
550 ................ 12-3
551 ................ 12-3
552 ................ 12-3
553 ................ 12-3
554 ................ 12-3
556 ................ 12-3
558 ................ 12-3
560 ................ 12-3
561 ................ 12-3
562 ................ 12-3
700 ............... 12-11
710 ............... 12-13
722 ............... 12-17
724 ............... 12-21
3271/25 ............ 1-83
3291 ............... 1-86
3292 ............... 1-86
3293 ............... 1-86
3329/03 .. . .. .. .. ... 1-92

Page

Model

3354 ............... 1-86
3355 ............... 1-86
3356 ............... 1-86
3430 ............... 1-94
3431 ............... 1-94
3450 ............... 3-19
3451 ............... 3-19
3452 ............... 3-19
3455 ............... 3-19
3456 .. .. .. . .. . .. ... 3-27
3500 ............... 1-96
3500MP ........ '" 1-100
3500/MIL ......... 11-132
3501 .............. 1-105
3507J ............. 1-109
3508J ............. 1-113
3510. ..... _. ____ . 1-117
3510VM/MIL. ..... 11-143
3521 .............. 1-123
3522 .............. 1-123
3523 .............. 1-129
3527 .............. 1-133
3528 .............. 1-137
3542 .............. 1-143
3550 .............. 1-147
3551 .............. 1-151
3553 .............. 1-155
3554 .............. 1-159
3571 .............. 1-167
3572 .............. 1-167
3573 .............. 1-173
3580 .............. 1-177
3581 .............. 1-177
3582 .............. 1-177
3583 .............. 1-181
3584 .............. 1-185
3606 ............... 2-52
3626 ............... 2-60
3627 ............... 2-64
3629 ............... 2-68
3630 ............... 2-74
3650 ............... 3-33
3652 ............... 3-33
3656 ............... 3-41
4023/25 . . . . . . . . . . .. 4-72
4085 ............... 4-74
4115/04 ............ 4-80
4127 ............... 4-82
4203 ............... 4-89
4204 ............... 4-91
4205 ............... 4-89
4206 ............... 4-97
4213 .............. 4-103
4213/MIL ......... 11-151
4214 .............. 4-110
4301 .............. 4-114
4302 .............. 4-116
4340 .............. 4-122
4341 .............. 4-126
4423 .............. 4-130
4804 .............. 6-174

A complete price list for these products is located inside the

b~ck

cover.

BURR-BROWN®

International. Airport Industrial Park· P.O. Bex 11400 • TUClGn, Arlzena 85734
Telephone 602·746-1111 • TWX 91l1-li52·1111 . Cable BBRCORP· Telex 66-6491

PRODUCT DATA BOOK

The information in this pUblication has been carefully checked and is believed to be reliable; however, no responsibility is assumed for
possible inaccuracies or omissions. Specifications and prices are subject to change without notice. No patent rights are granted to any
of the circuits described herein.
@1984 Burr-Brown Corporation

LI·300

Printed in U.S.A. July, 1984

Building An Unequalled Reputation, Worldwide,
for Quality, Performance, Reliability
Data acquisition, signal conditioning, and computer I/O components
and systems from Burr-Brown are recognized and used worldwide.
Over the past two decades these'products have'earned a reputation for
superior quality, exceptional, performance,and consiste.,t reliabilityperhaps the pest reputation for; wor,kmanshipin our industry.
Cost effectiveness of our products has been proven in ah,ost of applications: in industrial and process control, te~t instrumentation, aerospace systems, environmental monitoring, medical-clinical, and ana-'
Iytieal instrumentation.
We have built our credibility by being totally responsive to our customers" requirements. Knowing the problems encountered in the real
world, we apply the best, most appropriate, and proven technologies
to achieve practical solutions.
Our components have become ll10re complex, mbre sophisticated as
we continue to combine and vertically integrate multiple functions into
smaller; space-saving packages. When you select these versatile
"mini-systems" your design and assembly time is decreased while
your products' performance and reliability are increased. And today
you pay less, per function, as these microcircuits and subsystems
work more efficiently for you.
At Burr-Brown, quality and reliability are builHn by conservative
deSigns, carefully selected components and manufacturing processes,
by intensive, thorough testing, and stringent quality control.
Customers also give Burr-Brown high marks for service and support,
Our technical literature is among the best in the industry and our
global applications and sales force is factory trained-highly qualified
to help you in product selection and use. Wherever in the world you
contact us, you can be assured of prompt, courteous, efficient serviceand superb product performance.

ii

BURR-BROWN
PRODUCT DATA BOOK
The Burr-Brown Product Data Book contains detailed product data
shee,s for our broad line of precision components for signal processing, data acquisition, and data transmission. In addition, it includes
supplementary data for these components, such as screening programs available, a list of other technical literature that you may order,
accessories, and information on how to interface with Burr-Brown.
To acquaint you with the full breadth of the Burr-Brown product line,
we also include information on the products from our Data Acquisition
And Control Systems Division. Additional detailed manuals are available for most of these products upon request. Contact your local BurrBrown Sales Office listed inside the back cover.
For your convenience the Data Book is separated into 17 major sections: Operational Amplifiers, Instrumentation Amplifiers, Isolation
Amplifiers, Analog Circuit Functions, Analog-to-Digital Converters,
Digital-to-Analog Converters, Sample/Hold Amplifiers, Data Acquisition Subsystems, CMOS Multiplexers, Voltage-to-Frequency Converters, Military Products, Modular Power Supplies, Data Entry and Display Terminals, Microcomputer Input/Output Systems, Data Acquisition and Control Systems, Personal Computer Instru/1lentation, and
Accessories. Each right-hand page has a margin tab on the outer edge
which indicates both product type and part number. The tab index on
page V provides a visual guide to the major sections.
At the beginning of each produ,ct section, you will find explanatory
material and a selection guide to assist you in selecting the product
most suitable for your applications. The selection guide also contains
page numbers for individual product data sheets.
An index of products in this Data Book, listed in alphanumeric order, is
found on the inside of the front cover. A general table of co.ntents
appears on page IV.

iii

TABLE OF CONTENTS
Burr-Brown Orientation ...................................

ii

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . .

iii

Tab Index ...... '.' ........'............... '.' ...... .-. . . . . . .. . . . .

v

Interfacing With Burr-Brown ................ , . . . . . . . . . . . . .

vi

High Reliability Program..................................

viii

Handling Procedures For Microcircuits .................

x

I

.

Burr-Brown Technical Library............................

xi

Section 1: Operational Amplifiers .......................

h1

Section 2: Instrumentation Amplifiers...................

2-1

Section 3: Isolation Amplifiers...........................

3~1

Section 4: Analog Circuit Functions ......... ,..........

4-1

Section 5: Analog-to-Dlgltal Converters................

5-1

Section 6: Dlgltat-to-Analog Converters................

6-1

Section 7: Sample/Hold Amplifiers......................

7-1

Section 8: Data Acquisition Subsystems ...............

8-1

Section 9: CMOS Multiplexers...........................

9-1

Section 10: VOltage-to-Frequency Converters........... 10-1
Section 11: Military Products ............ ;................. 10-1
Section 12: Modular Power Supplies.. . . . . . . . . .. . . . . . . .. . 12-1
Section 13: Data Entry and Display Terminals... . . . . . . . 13-1
Section 14: Microcomputer Input/Output Systems ..... 14-1
Section 15: Data Acquisition and Control Systems..... 15-1
Section 16: Personal Computer Instrumentation........ 16-1
Section 17: Accessories..... ......... .............. ........ 17-1
Burr-Brown Sales Offices Directories ...... inside back cover
iv

TAB INDEX
OPERATIONAL AMPLIFIERS
INSTRUMENTATION AMPLIFIERS
ISOLATION AMPLIFIERS
ANALOG CI'RCUIT FUNCTIONS
ANALOG-TO-DIGITAL CONVERTERS

1
2
3,
4
5

SAMPLE/HOLD AMPLIFIERS

6
7

DATA ACQUISITION SUBSYSTEMS

8'

CMOS MULTIPLEXERS

9

DIGITAL-TO-ANALOG CONVERTERS

VOLTAGE~TO-FREQUENCY CONVERTERS

10

MILITARY PRODUCTS

11

MODULAR POWER SUPPLIES
DATA ENTRY AND DISPLAY TERMINALS
MICROCOMPUTER INPUT/OUTPUT SYSTEMS
DATA ACQUISITION AND CONTROL SYSTEMS
PERSONAL COMPUTER 'INSTRUMENTATION
ACCESSORIES
v

12
13
'14
15
16
17

INTERFACING WITH BURR-BROWN
PLACING AN ORDER
Qrders may be placed via mail, telephone, TWX or TELEX with arw authorized. Burr-Brown field sales.
'office, sales representative, or o.ur headquarters in Tucson. Our offices are listed inside the back cover of
thi.!I Data Book. When placing your order, please provide complete information, including model number'
with all option designations, product description or name, quantity desired, and ship-to and bill.-to
'lad dresses.

TECHNICAL ASSISTANCE
. ' Burr-Brown has a large and competent field sales force; backed-up by an experienced staff of
applications specialists. They will be most happy to assist you in selecting the right product for your
appl ication. This service is available, without charge, from all sales offices ami from our headquarters in
Tucson .

.
~.

,-

'.

DATA SHEETS/LITERATURE
,product data sheets or manuals, similar to tliose inthi!? Data Book but perhaps'containing more recent
. reVisions, are available for most of the products lisfed in this Data Boqk. Application Notes and other
" supporting.iite·rature arealso availabl", on request. If you wish a copy of any of these items simply contact
your nearest Burr-Brown sales office or representative.

PRicES AND TERMS
Prices listed in this catalog, unless otherwise noted, apply only to domestic USA customers; all other
customers should contact their local Burr-Brown representative for price information.
All prices are FOB Tucson, Arizona, USA, in U.S. dollars. ApplicaQle federal, state, and local taxes are
extra. Terms are net 30 days. Prices and specifications are subject to change without notice.

QUOTATIONS
Price quotations made by Burr-Brown or its authorized field sales representatives are valid for 30 days.
Delivery quotations are subject to reconfirmation at the timEl of order placement.

'I"~·

RETURNS AND WARRANTY SERVICE
When returning products for any. reason, it is necessary to contact Burr-Brown, prior to shipping, for
: authorization and shipping instructions. In the U.S.. , contact our Tucson heaqquarters. In other
',cduntries, contact your nearestSurr-Brown field/sales office or representative. Returned units should be
shipped prep.~t(,l·and:must be accompanied by the original purchase order number and date, and an
explanation 6'fthe malfunction. Upon receipt of the returned unit, Burr-Brown will verify the malfunction
 ±10V to ±145V
HIGH VOLTAGE
Offset Voltage
Rated
Outpul
Description

Model l1l

±V
min

±mA
min

FET

3584JM. (0)
3583AM, (0)
3583JM
3582J
3581J
3580J

145
140
140
145
70
30

15
75
75
15
30
60

3571 AM. (0)
3572AM
3573AM

30
30

1A(41
2AIS1

ChopperStabilized

3271/25

At
.25·C
±mV
max

Temp·
Drill
±pVl'C
max

Frequency

Bias

Current
(25'C)
pA
max

Response

Unity

G,in
MHz

Slew
Rate
VI_c

Open
Loop
Gain
dB

Temp
Ran'ge

,.,

Package

120
118
118
118
112
106'

Com
Ind
Com
Com
Com
Com

TO-3
TO-3
TO-3
. TO-3
TO-3
TO-3
TO-3
TO-3
TO-3

1-167
1-167
1-173

Module

1-83

-20
-20
-20
-20
-20
-50

20'3J

~
10

25
25
25
25
25
'30

5

150
30
30
20
20
15

20

40
40
65

-100
-100
40nA

0.5
0.5
1

3
'3
2.6

94

2A1Sl

2
2
10

94

Ind
Ind
Ind

110

20

0.05

1

±80

1

20

140

Ind

3
3
3

:i

5
5
5

5

94

Page
1-185
1-181
1-177 .
1-177
1-177.
1-17i

NOTES: (1) "(0)" Indicates product also availabl~ with screening for increaaed reliability. (2) Com = 0 to +70'C; Ind =-25·C to +85'C;
MIL = -55'C to +125·C. (3) Gain-bandwldth product. (4) 2A peak. (5) 5A peak .. (6) Typical.

1-4

Output currents> ±15mA to ±10A
HIGH CURRENT
Offset Voltage
Rated
Output
±V
min

±mA
min

At
25·C
±mV
max

Temp
Drift
±jJV/·C
max
65
40

Frequency
Response

Bias
CU,rrent
(25· C)
pA
max

Unity
Gain
MHz

Slew
Rate
V/PBec

<2,

Package

Page

1
1
1
1

1.5
1.5
1.5
1.5

94
98
94
98

Ind
Ind
MIL
MIL

TO-3
TO-3
TO-3
TO-3

1-69
1-69
1-69
1-69

Open
Loop
Gain
dB

Temp'
Range

Description

Model 'll

High Power

OPA501AM
OPA501BM
OPA501RM
OPA501SM

20
26
20
26

lOA
lOA
lOA
lOA

10
5
10
5

40

40nA
20nA
40nA
20nA

3573AM
3572AM
3571AM, (0)

20
30
30

2A 1SJ
2A ''s'

10
2
2

65
40
40

40nA
-100
-100

1
0.5
0.5

2.6
3
3

94
94
94

Ind
IndInd

TO-3
TO-3
TO-3

1-113
1-167
1-167

3554AM, (0)
3554BM, (0)
3554SM, (0)

io
10
10

100
100
100

2
1
1

50
15
25

-50
-50
-50

17001'"
1700131
170013.1

1200
1200
1200

100
100
100

Ind
Ind
MIL

TO-3
TO-3
TO-3

1-159
1-169
1-159

3564JM, (0)
3583AM
3583JM
3582J
3581J
3580J

145
140
140
145
70
30

15
75
75
15
30
60

3
3
3
3
3
10

25
25
25
25
25
30

-20
-20
-20
-20
-20
-50

20131

150
30
30
20
20
15

126
118
118
118
112
106

Com
Ind
Com
Com
Com
Com

TO-3
TO-3
TO-3
TO-3
TO-3
TO-3

1-185
1-181
1-181
1-173
1-173
1-173

3553AM, (0)
3329/03

10
10

200

50
50

300101

-200
Bipolar

300
5

2000

NA
NA

Ind
Ind.

TO-3
DIP

.1-155
1-92

Wid.eband

High Voltage,

Booster
(Buffer)

lAI41

100

65

-

5
5
5
5
5

-

NOTES: (1) "(0)" Indicates product also available With screening for increased reliability. (2) Com = 0 to +70·C; Ind = -25·C to +85·C;
MIL = -55·C to +125·C. (3) Gain-bandwidth product. (4) 2A peak. (5) 5A peak. (6) Typical.

LOW BIAS CURRENT
Our many years .of experience in designing, manufacturing and testing FET amplifiers gives us unique abilities
in prDviding IDW and ultra low bias current op amps.
These amplifiers offer bias currents as low as 75fA (75 X

10-15 amps) and low voltage drift as low as 2p.V/°C.
With offset voltage laser-trimmed to as low as 250}.lV,
the need fDr expensive, trim PDt adjustments is eliminated.

o 01pA to InA bias current
LOW BIAS CURRENT
Offset Voltage
Temp
Drift
±/IV/·C
max

Bias
Current
(25· C)
pA
max

Open
Loop
Gain
dB
min

Frequency
Response

Rated
Output

Description

Model lll

At
25·C
±mV
max

Low Drift

OPA103AM
OPA103BM
OPA103CM
OPA103DM

0.50
0.50
0.25
0.25

25
15
5
2

-2
-1
-1
-1

106
106
106
106

1
1
1

Low Noise

OPA101AM
OPA101BM
OPA102AM
OPA102BM

0.50
Q.25
0.50
0.25

10
5
10
5

-15
-10
-15
-10

94
94
94
94

10
10

40
40131

6.5
6.5
14
14

OPAlllAM
OPAlllBM
OPAlllSM

0.5
0.25
0.5

5
1
5

2
1
2

114
120
114

2
2
2

2
2
2

10
10
10

5
5
5

Ind
Ind
MIL

TO-99
TO-99
TD-99

1-51
1-51
1-51

.oPA104AM
OPA104BM
OPA104CM

1.0
0.50
0.50

25
15
10

-0.300
-0.150
-0.075

106
106
106

1
1

2.2
2.2
2.2

10
10
10

5
5
5

Ind
Ind
Ind

TO-99
TO-99
TO-99

1-47
1-47
1-47

3528AM. (a)
3528BM, (a)
3528CM, (a)
3523J. (a)
3523K
3523L, (a)

0.50
0,,25
0.50
1.0
0.50
0.50

15
5
10
50
25
25

-0.300
-0.150
-0.075
-0.50
-0.25
-0,.10

5

Ind
Ind
Ind
Com
Com
Com

TO-99
TO-99
TO-99
TO-99
TO-99
TO-99

1-137
1-137
1-137
1-129
1-129
1-129

Ultra-Low
Bias
Current

,

----

Unity
Gain
MHz

Slew
Rate
V/psoc

±V
min

±mA
min

Temp
Rangel21

Package

Page

1.3
1.3
1.3
1.3

10
10
10
10

5
5
5
5'

Ind
Ind
Ind
Ind

TO-99
TO-99
TC;>-99
TO-99

1-43
1-43
1-43
1-43

12
12
12
12

12
12
12
12

' Ind
Ind
Ind
hid

TO-99
TO-99
TD-99
TO-99

1-31
1-31
1-31
1-31

i

131

.-~.

88
92
90
100
100
100

0.7
0.7
0.7
1
1
1

0.3
0.3
0.3
0.6
0.6
0.6

10
10
10
10
10
10

5
5
10
10
10

Inverting
Only

3430J
3430K

Adjus.
toO

30
10

±0.01
±0.01

100
100

2kHz
2kHz

0.4v/
msec

10
10

5

Com
Com

Module
Module

1-94
1-94

Noninverting
Only

3431J
3431K

AdjuS.
toO

30
10

±O.OI
±0.01

100
100

2kHz
2kHz

O.4VI

10
10

5
5

Com
Com

Module
Module

1-94
1-94

Low Cost

OPAlOOAM
OPAlooBM
OPAlooCM

1
0.5
0.25

15
10
5

±3
±2
±1

94
100
106

1
1
1

2

10
10
10 .

5
5
5

Ind
Ind
Ind

TO-99
TO-99
TO-99

1-25
1-25
1-25

msec
2
2

1-5

5

LOW BIAS CURRENT
Offset Voltage

Description

Modell1 )

At
25°C
±mV
max

' Temp
Drift
±/lV/OC
max

Bias
Current
(25°C)
pA '
max

20
20

50
50

-25
-25

0.1
0.3
1

±50
±50
±loo

3542J
3542S

Open
'LooP
Gain
dB

Frequency
Response
Unity

Rated
Output

MHz

Slew
Rate
V//JSec

min

±mA
min

Temp
Aange f21

Package

Page

88
88

1
1

0.5
0.5

10
10

10
10

Com
MIL

TO-99
TO-99

1-143
1-143

140
140
140

3
3
3

6
6
6

10
10
10

5
5
5

Ind
Ind
Ind

Module
Module
Module

H!6
l-a6
1-86

min

Gain

±V

ChopperStabilized

3291/14
3292/14
3293/14

0.02
0.05
,0.10

3271/25

0.05

1

±BO

140

1

20

110

20

lrid

Module

1-63

Wideband

3554AM, (0)
3554BM, (0)
3554SM, (0)

2
1
1

SO

-50
-50

1000'3)

100013.1

1000
1000
1000

,10
10
'10

100
100

-SO

100
100
100

100

Ind
Ind
MIL

TO-3
To-3
TO-3

1-159
1-159
1-159

Buffer

3553AM, (0)

50

300

-200

. NA

300''''

2000

10

200

Ind

TO-3

1-155

High

3571AM, (0)
3572AM

2
2

40
40

-100
-100

94
94

0.5'
0.5

3
3

30

lA
2A

Ind
Ind

TO-3
TO-3

1-167
1-16!

35BOJ
358,1J
3582J, (0)
3583AM, (0)
3583JM
3554JM, (0)

10
3
3
3
'3
3

30
25
25
25
25
25

-SO

,88

-20
-20
-20
-20

94
100
105
94
100

5
5
5
5
5

15
20
20
30
30
150

70
145
140
140
145

BO
30
15
75
75
15

Com
Com
Com
Ind
Com
Com

TO-3
TO,3
TO-3
TO-3
TO-3
TO-3

1-177
1-177
1-177
1-181
1-181
1-185

3522J
3522K
3522L

1.0
0,50
0.50

50
10
25

-10
-5
-1

0.6
0.6
0.6

10
10
10

10
10
'10

TO-99
TO-91i
TO-99

1-123
1-123
1-123
1-123

Current
High
Voltage

General
Purpose

Ultra-low
Drift

~~

"

-20

1000'"

20'31

30

3522S. (0)

C.W

25

-5

94

1
1
1
i

0.6

1U

1U

Com
Com
Com
MIL

3527AM, (0)
3527BM, (0)
3527CM, (0)

0.50
0,25
0.25

10
5
2

-5
-2
-5

100
100
100

1
1
1

0.6
0.6
0.6

10
10
10

10
10
10

Ind
Ind
Ind

TO-99
TO-99
TO-99

1-133
1-133
1-133

3521H'
3521J, (0)
3521K
3521L
3521R, (0)

0.50
0.25
0.25
0.25
0.25

10'
5
2
1

-20
,-20
-15
-10
-20

94

1.5
1.5
1.5
1.5
1.5

0.6
0.6
0.6
0.6
0.6

10
10
10
10
10

10
10
10
10
10

Com
Com
Com
Com
MIL

TO-99
TO-99
TO-99
TO-99
TO-99

1-123
1-123
1-123

5

54

30

94,
94

94
94
94
94

NOTES: (1) "(0)" indicates product also available with screening for increased reliability.
MIL = -55°C to +125°0. (3) Gain-bandwidth product. (4) -3dB bandwidth.

I

LOW NOISE
Now both PET and bipolar input op amps are offered
with guaranteed low noise specifications. Until now the
designer had to rely on "typical" specs for his demanding

TO~99

1-1~3

1-123

(2) Com = 0 to +70° C; Ind = -25°C to +85° C;

low noise designs, These fully characterized parts allow a
truly complete error budget calculation,

~OW NOISE

Noise
Voltage
nV/ •.jHz
at
10kHz
max

Bias
Current
(25°C)
pA
max

At
25°C
±mV
max

Temp
Drift
±/lV/oC
max

3.8
3:8
3.8
3.8
4.5
4.5
3.8
3.8
3.8
3.8
4.5
4.5

±4Ok
±40k
±55k
±55k
±BOk
±80k
±4Ok
±4Ok
±55k
±55k
±80k
±BOk

0,025
0.025
0.060
0.060
0.100
0.100
0.025
0.025'
0.060
0·060
0.100
0.100

OPA101AM
OPA101BM

8
8

"-15
-10

OPA102AM
OPA102BM

8

8
8
8
8

Description

Model

OPA27 '"
ACL> WIV

OPA27A
OPA37A
OPA27B
OPA37B
OPA27C
OPA37C
OPA27E
OPA37E
OPA27F
OPA37F
OPA27G
OPA37G

OPA37'"

Ac<.>5VN

ACl.>1VN'31

ACl >3VN '31
At;L>

1VN f31

NOTES:

Offset
Voltage

OPAll1AM
OPAlllBM
OPA111SM

,;

Open
Loop

Frequency
Response
Rated
Output

min

GBW
MHz

Slew
Rate
V/JJS9C
min

0.6
0.6
1.3
1.3
1.8
1.8
0.6
0.6
1.3
1.3
1.8
1.8

120
120
120
120
97
97
120
120
120
120
97
'97

8
40
8
40
8
40
8
40
8
40
8
40

1.7
11
,1.7
11
1.7
11
11
1,1
1.7
11
1.7
11

10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0

17.6
17.6
17.6
17.6 .
17.6
17.6
. 17.6
17.6

MIL
MIL
MIL
MIL
MIL
MIL
Ind
Ind
Ina
Ind
Ind
In,d

0.5
0.25

10
5

94

20
20

5
5

12
12

12
12

Ind
Ind

TO-99
TO-99

1-31
1-31

-15
-10

0.5
'0.25

10
5

94
94

40
40

10
10

12
12

12
12

Ind
Ind

To-99
TO-99

1-31
1-31

2
1
2

0.5
0.25
0.5

5
1
5

114
120
114

2
2
2

2
2
2

·10
10
10

5
5
5

Ind
Ind
MIL

TO-99
TO-99
TO-99

1-51
1-51
1-51

(1) Ind = -25°C to +85°C; MIL = -55°C to +125°C.

Gain
dB

94

Temp
Range

±V

±mA

min

min

'"

Package

Page

17.6,
17.6
17.6

TO-991
DIP

1-17
1-17
1-17
1-17
1-17
1-17
1-17
1-17
1-17
1-17
1-17
1-17

'17.6

(2) A, B. C grades available with 1883 screening ..

1-6

(3) FET Input.

UNITY-GAIN BUFFER (Power Booster)
These versatile amplifiers: boost the output current capability of another amplifier; buffer an impedance that
might load a critical circuit; may be used inside the feed-

back loop of another op amp to form a current-boosted,
composite amplifier. Currents as high as ±lOOmA are
available with speeds of 2000V / J.lsec.

UNITY-GAIN BUFFER
Rated
Output
Description

Model

Noninverting

3553AM
3329/03

NOTES:

±v
min

±mA

10
10

200
100

min

Frequency Response
-3dB
MHz

Full Power
BWMHz

Slew Rate
V/_c

Gain
VN

300

32
I

2000

-I
-I

5

-

Open
Loop

Input
Impedance

n
1011
10k

Gain

Temp

dB

Range"'

Package

Page

NA
NA

Ind
Ind

TO-3
DIP

H55
1-92

(I) Ind = -25°C to +85°C.

WIDE BANDWIDTH
Design expertise in wide band circuits combines with our
fully developed hybrid technology to create cost effective
wideband op amps. Hybrid IC performance-in band-

width, settling time and output current-cannot be
duplicated in less expensive monolithic designs.

WIDE BANDWIDTH
'Frequency
Response

Description
Differential

Slew
Rate
VI_c

to

Com-

±a.l%
nsec

pensa-

min

1700,
A=
1000

1000
1000
1000

120 '
120
120

ext.
ext.

3551J
35515, (0)

50, A=10
50,A=10

250
250

400
400

3550J
3550K
35505, (0)

10,A=10
20,A=1
10,A=1

85
100

3508J
3507J, (0)

100, A=100
2O,A=10

Model m
3554AM, (0)
3554BM, (0)
3554SM, (0)

OPA605H
OPA805A
OPA605K
OPA6OSC

OPA101AM
OPA101BM
OPA102AM
OPA102BM

At
Temp
Drift
25°C
±mV ±/IV/oC
max
max

±V
min

±mA

ext.

10
10
10

100
100
100

2
I
I

ext.
ext.

10
10

10
10

I
I

into
hit.
int.

10
10
10

10
10
10

1
1
I

50 /31'
50131

85

400
400
400

20

-

ext.

80

200

ext.

10
10

10
10

5
10

300
300
300

ext.
ext.

300'"

300

ext.

10
10
10
10

30
30

300(31

30

1
I
0.5
0.5

25
25
5
5

8
40
8
40
8
40
8
40
8
40
8
40

1]
II
1.7
II
1.7
II
1.7
II
1.7
II
1.7
II

---

int,I41

10
10
10
10
10
10
10
10
10
10
10
10

16
16
16
16
16
16
16
16
16
16
16
16

0.025
0.025
0.060
0.060
0.100
0.100
0.025
0.025
0.060
0.060'
0.100
0.100

20, A=100
20, A=l00
40, A=100
4O,A=100

5

2.5
2.S
1.5
1.S

int.

5
10
10

int.

12
12
12
12

12
12
12
12

0.5
0:26
0.5
0.25

32

2000

-

-

10

200

12,A=1

4

into

10

15

GBW
MHz

200,
200,
200,
200,

OPA27A
OPA37A
OPA27B
OPA37B
OPA27C
OPA37C
OPA27E
OPA37E
OPA27F
OPA37F
OPA27G
OPA37G
Low Noise

'Offset
Voltage
Rated
Output

Military

OPA600/MIL Saries

Unity-Gain
Buffer

3553AM, (0)

Wide Temp

OPA11HT

A=1ooo
A=1OOO
A=1000
A=1ooo

3OO~'

300131

-

-

tion

ext.

int.'oU
int.'4'
int.''''
int,(4)
int. loU
int.''''

int,14'
int. 141

int'''''
int. I"')

int. I""
into
int.

min

30

Open
Loop
Gain
Temp
dB
Range W

Package

Page

100
100
100

Ind
'Ind
MIL

TO-3
TO-3
TO-3

H59
1-159
1-159

100
100

Com
MIL

TO-99
TO-99

H51
1-151

SOl31

100
100
100

Com
. Com
MIL

TO-99
TO-99
TO-99

H47
1-147
H47

30(3)

103

30131

83

Com
Com

TO-99
TO-99

H13
H09

96
96

Com
Ind
Com
Ind

DIP
DIP
DIP
DIP

1-77
1-77
1-77
1-77

0.6
0.6
1.3
1.3
1.8
1.8
0,6
0.6
1,3
1.3
1.8
1.8

120
120
120
120
97
97
120
120
120
120
97
97

MIL
MIL
MIL
MIL
MIL
MIL
Ind
Ind
Ind
Ind
Ind
Ind

TO-99/
DIP

1-17
1-17
1-17
1-17
H7
1-17
1-17
1-17
H7
1-17
1-17
H1

10
S
10'
5

lOS
lOS'
lOS
lOS

Ind
Ind
Ind
Ind

TO-99
'TO-99
TQ-99
TQ-99

1-31
1-31
1-31
1-31

50

300131

NA

Ind

'TO-3

,.,S5

5131

S

98

+175°C

TO-99

1-9

50
IS
25
50(3 )

50C31

96

96

Sae Military Products

1500

NOTES: (1) "(0)" indicates product also available with screaning for increased reliability.
-55°C to +12So C. (3) Typical. (4) G = 5 min for OPA37.

1-7

(2) Com = 0 to +70°C; Ind = -25°C to +85°C; MIL ""

. GLOSSARY,OF TERMS AND DEFINITIONS I
bperati90al AmpUf'iers
"

•

>

.vii!~geS~

Both Dower supply magnitudes are changed in
the same direction and over the operating voltage, range.

COMMON-MODE INPUT IMPEDANCE
The effecti\re iJllpedance (resistance in parallel with
capacitance) between either input of an amplifier and its
common, or grourid terminal
COMMON-MODE REJECTION (eMR)
When both inputs, of a I\ifferential amplifier experience
the same common-mode voltage (CMV), the output
should, ideally, be unaffected.CMR is the ratio of the
common-mode input voltage change to the differential
input voltage (error voltage) which produces the same
output change.
.CMR (in dB);= ,20 10glOCMV/Error Voltage
ihus a CMR of gOdB means that I V of common-mode
voltage will cause an error of IOOjlV' (referred to input).
COMMON-MObE VOLTAGE (CMV)
That portion of an input signal which is.common to both
inputs of a differential amplifier. Mathematically it is.
defined as the average of the signals at the two inputs:
•
CMV = (e, + e,)/2
COMMON-MODE VOLTAGE GAIN
The ratio of the output signal voltage (ideally lero) to tile
common-mode input signal voltage.
COMMON-MODE VOLTAGE RANGE
The range of' input voltage for linear, nonsaturated
operation.
DIFF,ERENTIAL INPUT IMpEDANCE
The apparent impedance, resistance in paralle) with
capacitance, between the two input terminalS:
FULL POWER FREQUENCY RE$PONSE
The muximum frequency (\t whicli a device. call supply its
peak-ta-peak rated output voltage and current, without
introducing significant distortion.
. GAIN-BANDWIDTH PRODUct
A product of small signal, open-loop gain and frequency
.
"
at that gain,
INPUT BIAS CURRENT,
'
The DC input current required at each inpu~ of an '
amplifrer to provide zero 'output voltage when tlie input
signal and input offset voltage are zero. 'The speGified,
maximum is for each input.
INPUT BIAS CURRENT VS SUPPLY VOLTAGE
The sensitivity of inpilt bias current to the power supply
voltages.
INPUT BIAS CURRENT VS TEMPERATURE
The sensjtivity of input bias current to temperature.
INPUT;CURRENT NOI$E
The input current which 'would produce, at the oUtput of
a noiseless amplifier, the same output as that produced by
the inherent noise generat~ internally. in the amplifier
when the source resistances are large.
INPUT QFFSET CURRENT
The 'difference of the two input bias currents of a '
diffe~em,ial amplifier. .
INPUT O.F.FSET VOLTAGE
The DC input voltage required to provide zero voltage at ,.
the output of an amplifier when the input signal and input
bias currents are zero.

..INPUT OFFSET VOLTAGE VS TEMPERATURE
(DRIFT)
The rate of change of input offset voltage with
. temperature. At Burr-Brown, this is the change in input,
offset voltage from 25°C to the maximum specification
temperature, prus the change in input offset voltage from
25°C to the minimum specification temperature, this
quantity divided by the specification temperature range.

INPUT OFFSET VOLTAGE VS TIME
The sensitivity of input offset voltage to time.
INPUT VOLTAGE NOISE
The differential input voltage which would prOduce, at
the output 'of a noiseless amplifier, the same output as
that produced by the inherent noise generated internally
in' the ampiifier when the source resistances are small.
MAXIMUM SAFE INPUT VOLTAGE
The maximum~ peak value; continuous voltage that may
be applied at, or between, the inputs without damage.
OPEN-LOOP GAIN
The ratio of the output signal voltage to the differential
input' signal voltage.
OPERATING TEMPERATURE RANGE
The temperature range, ambient unless otherwise
indicited, over which the amplifier may be safely
operated:
OUTPUT RESISTANCE
The open-loop output source resistance with respect to
ground. '.
POWER SUPPLY RATED VOLTAGE
The nOrlllal value of power supply voltage at which the
amplifier is designed to operate.
POWER SUPPLY VOLTAGE RANGE
The range. of power supply voltage over which the
amplifier may be safely operated.
QUIESCENT CURRENT
The current required from the power supply to operate
the amplfiier with no load and with the output at zero.
IJATED OUTPUT
The peak output voltage and current which can be
continuously, simultaneously supplied.
SETTLING TIME
The time required, after application of a step input signal,
for the output voltage to settle and remain within a
speCified error hand around. the final"value.
SLEW RATE
The maximum rate of charge of the output voltage when
supplying rated output.
SPECIFICATION TEMPERATURE RANGE
The. temperature range over which the "versus
temperature" 's~cificatio'nsare specified.
STORAGE TEMPERATUR£ RANGE
The temperature range over which the amplifie~ may be
safely stored, unpowered,
UNITY-GAIN FREQUENCY RESPONSE
The frequency at which the open-loop becomes unity.

INPUT OFFSET VOLTAGE VS SUPPLY VOLTAGE'
I/PSRR
The sensitivity of input offset voltage to the power supply

1-8

BURR-BROWN®

OPA11HT

113131

....

-~=

=
Wide Temperalure-Range
General Purpose
OPERATIONAL AMPLIFIER
FEATURES
• -55°C TO +175°C SPECIFICATIONS
.30nA MAX. INPUT BIAS CURRENT AT +175°C
• ±BmV. MAX. INPUT OFFSET VOLTAGE AT +175°C
• ±5pV/oC TYP. INPUT OFFSET VOLTAGE COEFFICIENT
• 12MHz BANDWIDTH:'rYPICAL
• HERMETIC PACKAGE WITH STANDARD PINOUT
(741-TYPEI

DESCRIPTION
These specifications give you a versatile operational
amplifier.that will work in circuits that are subjected
to extremely wide temperature ranges. Typical applications for OPA II HT include general purpose
gain blocks, high-speed pulse amplifiers, audio
amplifiers, high-frequency active filters, high-speed
integrators. and photodiode amplifiers.
You're assured of this product's performance over
the _55°C to +17S"C range because we conduct 100%
screening procedures in accordance with MIL-STD883, method 5004, class B. Burn-in is performed at
200"C. Our sample and inspection procedures include
both destructive and nondestructive bonding wire

pull tests in accordance with Method 2011 of MILSTD-883. The product is assembled in a clean-room
environment.
Model OPAl I HT is internally compensated for
stability at all gains. Pins are available for special
tailoring of the bandwidth compensation. Significant.
advantages in high gain, wide bandwidth, low-bias
current, high output current and high commonmode rejection are provided by OPAl I HT. Inputs
are protected against common-mode voltages up to
the value of the power supplies while the output is
current limited to offer short circuited protection.
TO-99 hermetic package has standard 741-type
pinout arrangement.

Intarnatlonal Airport Industrlat Park- P.O. Box 11400 - TUClon. Arizona 85734 - Tel. (602) 746-1111· Twx: 91(1.952-1111 - Cabla: BBRCORP - Telex: 66-8491

1-9

,i'SPECIFICATIONS
,ELECTRICAL
Specifications at ±15VDC and T A

MECHANICAL

= +175~C .~nllbs otherwise noted
','

OPA11HT

MODEL
CHARACTERISTIC

TYP

94

103
100

dB
dB

Yom
10m

±10
±lS

±12
±23

V
mA

BiNip
SR

50
4

12
75
7

MHz
kHz
V/~sec

.}.5

pSSC

30

nsec

DYNAMIC RESPONSEITA 25°C I
Small-Signal Bandwidth! OqB,

= ±10V

VOUT

Slew Rate

R, = 2kll

MAX

TO-99 PACKAGE

UNI.T

Av

RATED OUTPUT
Voltage, RL 2kll
Current ITA ~ 25°CI

Full-Power Bandwidth}

I

MIN

SYMBOL

OPEN LOOP GAIN, DC, single-ended
No load
RL=2kll

Settling Time (0.1%1
Rise Time 110% to 90%, small-signal)

INPUT OFFSET VOLTAGE
Initial I without ~dj. at 25°C I

s.",",11111
-----I.--PIe,..e

±5

TA = +17SoC
TA = -55°C
Average Via coefficient
Average Via coefficient vs
supply voltage I TA = 25°C I

±6
±7

INPUT BIAS CURRENT
Initial at +25°C

mV
mV

±10

±200

~V/v

±10

±25

nA

±30
±40

nA
nA

lib

±O.l

Ii

±10

DIM

nA

A

±30
±40

INPUT IMPEDANCE ITA - 25°C,
Differential

r;

100

Ci
rt{CMI
ci(CMI

Common Mode

INPUT VOLTAGE RANGE
Common Mode
Differential Mode
Common-Mode Rejection
Over Temperature I-55°C", TA '" +175OC)

nAloe

300
3
1000
3

Mll
pf
Mll
pF
±11

±12
CMR

60

100
100

•c

nA
nA

±C.l

g

N

Pin numbers shown for reference only.
Numben may not b~ ":'larked on package.

nA/OC
±2S

•T

(.2Smm\ R @,MMC "!lIit.~in\l plane.

lio

INPUT DIFFERENCE CURRENT
Initial at +25°C
Over Temperature
TA =+175OC
.:rA=-55'C
Average lio coefficient

1

NOTt::
Leads in tr .... position within .010"

Over Temperature

TA = +175OC
TA = -55OC
Average lib coeffici.ent

1

0

"~l\\

L

~V/oC

±5

FJ

1if
~.

mV

Over Temperature

•

~

~

r;-r!! I!I

Via

±1

rF:=1j

L-

V
V
dB
dB

INCHES
,MAX

MIN

MILLIMETERS

MIN

MAX

.335

.370

8.51

9.40

.305

.335

7.75

.8.51

4.19

4.70

a

.016

.021

0.41

0.53

E

.040

0.25

1.02

.010

.040

0.25

.165

.185

F

.010

G

.200 8A.SIC

H

.028

.034'

0.71

J

'.029

1.02

5.08 BA.SIC
0.86
1.14

.04"

0.74

K

.500

12.7

--

L

2.79

4.06

M

.160
.110
45 0 BA.SIC

N

.09"

.105

2.41

45° BA.SIC
2.67

CONNECTION DIAGRAM

POWER SUPPLYIT,,- 25°C,
Rated Voltage
Voltage Range, derated
Current. quiescent
Over Temperature I-55°C'" TA '" +175OC)
Power Supply Rejection
Ratio, T A = +175OC)

±15.

Vee
±8 to±22
±3
±3

Iq

PSr'r

60

±3.7

100

V
V
mA
mA
dB

BANDWIDTH CONTROL
OFFSET ADJ.

8

1

TEMPERATURE RANGE
Specification
Operating
Storage

-55°C'$ TA $ +175°C
-55°C $ TA$ +200°C
-65°C < TA < +250°C

-IN

-

2

OUT

5

3
+IN

6

+

.,

v+

7

4

OFFSET ADJ.

V-'

\

(TOP VIEW)
PIN 4 IS CONNECTED TO CASE

'1-10

TYPICAL PERFORMANCE CURVES
(at ±15VDC and .T A::;: +25°C unless otherwise specified)

OPEN LOOP FREQUENCY RESPONSE( 11

COMMON MODE VOLTAGE RANGE vs. SUPPLY VOLTAGE

I-

....
f

:c

20

."g>

II:

g"

~

15

'./"

10

::;

c
o
E
E

o

()

100

1k

10k

100k

1M

±10V

120

Jo~

I,F,.. 6ot~ Jv

iii

I .1 .. 1. .1

"...
c

~I~:
·~.·I 9
ega ve

1°11

~

(!)

80

)A +\751c

±iOiSiPI'Y (~rISutP;r

-55.-35f15+512545.65 85

165

205 245

EQUIVALENT INPUT NOISE vs. BANDWIDTH
100

OUTPUT VOLTAGE SWING vs. FREQUENCY

~V:t~~~~~::~~~=f::::=i
10V

'5

±20V

~.

·ig>

125

-" . ..

Temperature (OC)

Time (0.5~sec/divl

;;;

: :

"

100

I"

>

±20V

OPEN LOOP VOLTAGE GAIN vs. TEMPERATURE

~ Positive Going

J.

±15V

Supply Voltage

I 1 1 1

,J"

o
±5V

10M

STEP RESPONSE IN FOLLOWER CONFIGURATION,21

.~

5

CI

V

V

(Hz~

Frequency

.~

~

V

1011--+----+--~~'___l__,,<"--I

1V t----t--~,.~--+-----1

en

"'"

g19

.."

0.1V1---+-..c::::.:..~-~~,---~

'"
Q.

0.01VL-_ _...L_ _ _1.-_ _...L_ _~
10k

100k

1M

10M

0.1 '"""'-......_ - - '_ _- ' - _ - - '_ _..1
100
1k
10k
100k
1M
10M

100M

Upper 3dB Frequency (Hz)
(Lower 3dB Frequency =. 10Hz)

Frequency (Hz ~
INPUT BIAS CURRENT AND DIFFERENCE CURRENT
AS A FUNCTION OF TEMPERATURE
20

EO

"

"tl

il

·c

.'"

::;

OPEN-LOOP FREQUENCY AND PHASE RESPONSE
1~

"1\ I\.

;(

100

I\..

10

I\.

C

~

-:;

c.

E

·0

~ .o..j~;N~/':>

60

f--

.+50

+100

~

I""" I- ••

.'

+150 +200

+250

6()0

"'"

o
-20
10

I()O

I2()o

""

~

0
-50

80
40

"- 1"""100..

"

()

I-- i -

100

1k

10k

100k

1000

~

"'"

1M

I"."

10M 100M

Frequency (Hzl

Temperature °c
1. CapaCitance values shown are compensation from pin 8 to common. Not required for stability. See Figure 1.

HI

14()o

16()0

2. See Figure 3.

.t,.

APPLICATIONS
BANDWIDTH COMPENSATION
The frequencyresponse of the OPAl I HTcan be adjusted
by use of an external compensation capacitor from pin 8
to common as shown in Figure I. The open-loop
frequency response curves illustrate the effect of various
values of capacitance. The OPA II HT is stable at any gain
level without the use of compensation, prov.ided that stray
wiring capacitance and! or load capacitance are not
excessive; and that moderate values of feedback resistance are used (RF8.~ 10k!}). A load capacitance of
=50pF is desirable in all feedback configurations.
STABILITY
Because the OPAl I HT is an extremely-fast amplifier
with high gain. stray wiring capacitance and inductance in
power supply leads can cause circuit oscillation. This can
be prevented by proper circuit layout (all.leads or patterns
as short as possible) and by properly by passing the power
supply lines to common at points close to the amplifier. In
addition. it is recommended that the load be bypassed by
" SupF capaciior. see Figure i.
OFFSET VOLTAGE AND ADJUSTMENT
Although the offset voltage of these amplifiers is only a
few millivolts. it may'in some cases be desirable to null
this offset. This is done by use of a lOOk!} potentiometer
as shown in Figure 2.
TEST CIRCUIT - DYNAMIC RESPONSE
The test circuit of Figure 3 is used for measurement of
. slew rate. settling time. rise time and overshoot. Both rise
time and overshoot are measured for a small output signal
(VOlT = ±100mV). Slew rate and settling time are
measured for a IOV. p-p. square wave.

SUPPLY BYPASS..t

7

1 COMPENSATION
.
.' :L
(OPTIONALI

V+
O.I"F

LOAD
BYPASS
.
SUPPLY

;.:!. ~YPASS

1

50PF

LOAD

-=

FIGURE I. Compensated Amplifier with Supply Load
Bypassing.

~-------------o

\("b~
v+
61
~>1114~--~O
nU!1

FIGURE 2. External Adjustment of Offset Voltage.

FIGURE 3. Dynamic Response Test Circuit.

IIPUT

VOLTAGE REGULATOR AT 200"C
In many applications. a regulated source of ±15V is
needed. A voltage regulator that typically will operate up
to +17S"C is shown in Figure 4. This regulator accepts
+ 16 V to + 30V at its input and provides + 15V at 20mA at
its output. A complementary versio~ may be constructed
to provide -ISV by using theOPAll HT with a 2NI711
transistor. Short-circuit protection should be added if
required.

+11V""

471((1

IiDPF
OUTPUT

+15V11
20lIlA

~ AOJ
VOlTAIE
ADJUST'

IlY88

1.11111

1000F '

C5V8

FIGURE 4. A +ISV Voltage Regulator that will '
Operate at + 175"C.

1-12

BURR-BROWN@)

OPA21

I~~I

=

High-Speed Low-Power Precision
OPERATIONAL AMPLIFIER
FEATURES

DESCRIPTION

• LOW SUPPLY CURRENT
230I'A max at Vee = ±15V

A unique circuit design, state·of·the-art monolithic
processing and advanced laser-trimming techniques
are used to provide a low power amplifier with
outstanding parameters - truly ~instrumentation
grade" performance.
The OPA21 maintains excellent performance fea·
tures over a wide supply voltage range.

• HIGH SLEW RATE
O.2V11'I8c typ
• WIDE SUPPLY RANGE
±2.5V to ±18V .
• LOW OFFSET VOLTAGE
tOOI'V max
• LOW OFFSET VOLTAGE ORIFT
1.OI'V/o e max
• HIGH eMRR AND PSRR
11Od8 typ
• HIGH OPEN·LooP GAIN
l20dB min

-

N

If

A maximum IQ of 230l'A means only 6.9mW of
power consumption at the Vc.c=±15V and I.lmWat
Vee = ±2.5V.
This design also has lower input bias and offset
currents than other low power op amps. This is
particularly important in low power applications
where the high resistor values used can create large
voltage errors due to bias current. The OP A21 is
internally compensated and has'excellent frequency
stability characteristics.

APPLICATIONS
• LOW POWER INSTRUMENTATION
AMPLIFIERS
• ISOLATION AMPLIFIERS
• PORTABLE EQUIPMENT
• BATTERY OPERATION

OFFSET TIIII

International Airport Indatrtlll'lrk· P.O. Sax 11400· TUClDn. Arizona 85734 • T81. 16021 746·1111 • Twx: 911).952·1111 • Clble: BBRCOIIP . T8lex: 66-6491

1-13

SPECIFICATIONS
ELECTRICAL
At T A~ +25°C and +V
- cc= 2 5VDC t0 15VDC un ess oth erwlse .noted .
,,.',

OPA21A, OPA21E
CONDITIONS

PARAMETERS

MIN

I

TVP

I

MAX

OPA21B oPA21F

I

MIN

I

TVplMAX

oioM1G
L
I !lIN I TYP I

I
MAX

I

UNITa

INITIAL OF~SETYOLTAOEI±Vee -15VDCI
Initial Offsetll)

100
200
1.0

150
200
1.0

200

300

500
2.0

500
2.5

500
1000
5.0

p.V
p.V
p.V/oC.
mV

0.3
0.5

1
2

0.8
2.0

2
4

1.2
2

4
6

nA
nA

Initial Bias

7

9

25
40

10
12

40

Over Temperature(2)

15
18

50
75

nA
nA

40

Over Temperature(2)
Average vs Temperature(2)

75
0:5"
+4

Offset Adjustment Range
INPUT OFFSET CURRENT
Initial Offset
Over TemperaturB(2)
INPUT BIAS.CURRENT

INPUT NOISE
Q.1Hzto 10Hz,

Voltage
Voltage Denaity

,

:1,0
'60
20
20
0.7
0.25
0.07

fo =lHz
10 = 10Hz
10 == 100Hz'

to= 1Hz

Current Density

10= 10Hz
fo == 100Hz

60

..

:

.V. p-p
nVl,jHi
nVl%<
nVl%<
pA/,jHi
pAl,jHi
pAl%<

..

INPUT RESISTANCE
Differential

6
10 10 112

Common-Mode'

5

MO

4

011 pF

INPUT VOLTAGE RANGE ',±Vee -15VDC,
Initial Input Voltage

V
V
V
V

-12.5

+14.3
Over Temperature(2)

-12.0

+14.0
CO_ON-MODE RE~ECTIO'" RATIO I±Vee -15VDC. No Load. -12 .. VeM .. +14VI
Initial Reje<;tion Ratio

100

96

110
105

90
86

105
100

84
80

100

Over Temperature(2)

104
100

114
108

100
95

108
104

90

100

85

95

·dB
dB

1000
120
500
114

2000
126
1500
124

500
114
250
108

1500
124
1300
122

500

1000
120
1000
120

VlmV
dB
VlmV
dB

-13.7
+14.0
-13.5
+13.8

-14.2
+14.1

-'3.7
+13.9
-13.5
+13.7

POWER SU~PLY REJECTION RATIO ,±Vee

=2.5V to 18V. No load

Initial Rejection Ratio
Over Temperature(2)

= 15VDC. RL = 1()kll

LAROE SIGNAL VOLTAGE GAIN ,±Vee
Ini~.ial

dB
dB

85

Voltage Gain

Over Temperaturel21

114
250
108

RATED OUTPUT ±Vee '7 15VDC. RL - lOkI!,
Initial Voltage Swing
Over Temperature(2)
Output Resistance

-13.6
+13.8
-13.5
+13.6

V
V
V
V

Open-Loop

500

n

CL - l00pF. RL - 25kll
ACL =: +1. RL = 1QkB

0.2
300

V/lJsec
kHz

DYNAMIC RESPONSE
Slew Rate
Closed-Loop Bandwidth
POWER I\UPPLY
Rated Voltage
Voltage Range
Current. QUiescent
Initial
Over Temperature(21
Power Consumption

:!:15
2.5
No Load
~Vcc :::; 2.5V
-:.Vcc:c lSV
oVee 2.5V
:!:Vcc = 15V
±Vcc "'" 15V. TA::: +2SoC

(3).

13)
13)

0

VDC
VDC

18

(3)

225
250
300
350
7.5

210
230
275
325
6.9

'.

250
275
325
375
8.3

.A
.A

.A
.A
mW

TEMPERATIJRERANGE
Specification

'A.

Operating

A. B.

B.

E. F. G
E. F. G
Storage

"J" and "Z" Packages

-55
-25
-55
-25
-65

+125
+85
+125
+85
+125

'C

.

,

'C
'C
'C

'.c

·Speclfication same as OPA21A. OP'A21E.
NOTES:

1.100% tested. Guaranteed fully warmed-up
2. Over temperature specifications are -55°C ~ TA 'S 1'-125°C for A and B grades and -25°C -:; TA '5 +85°C for E, F. and
G grades
3. See Typical Performance Curves
.

1-14

ABSOLUTE MAXIMUM RATINGS
Supply Voltage ............................ ±18V
Internal Power Dissipation(l) ............. 500mW
Input Voltage
................. Supply Voltage
Differential Input Voltage
±30V
Output Short Circuit Duration .......... Indefinite
Storage Temperature Range .... -65°C to +1500C
Operating Temperature Range
A, B, ............... .' .... -55°C to +125°C
E, F, G .................... -25°C to +85°C
Lead Temperature Range
(Soldering,60sec) ................ +300°C

NOTES:
1. Maximum package power dissipation vs ambient temperature.
Package
Type

Derate Above
Maximum Ambient
Temparature

Maximum Ambient
Temperature lor Rating

TO-99IJI

+80'C

7.1mWf<'C

8-Pin Hermelic DIP IZI

+75°C

6.7mWf<'C

ORDERING INFORMATION
OPA21

Y

==r T

z

Basic Model Number
Performance Grade.Code _ _ _ _ _....J
A,B -55°C to +125°C
E, F, G -25°C to +85°C
PackageCode _ _ _ _ _ _ _ _ _ _ _~

J TO-99
Z a-Pin Hermetic DIP

TO-.
(J SuHlx)

HennellcDIP
(ZSufllx)

OPA21AJ
OPA21BJ
OPA21EJ
OPA21FJ
OPA21GJ

OPA21AZ
OPA21BZ
OPA21EZ
OPA21FZ
OPA21GZ

MECHANICAL

{m?L,I~ro"
fA~

TO~99

.

C
L S

f

p~~~ng II

Leads in true position within 0.01"
(O.25mm) R al MMC al sealing plane.

,F

I

Pin numbers shown for ref.3rence only.
Numbers may nol be marked on package.

K

11--.i

~0

T '", +,,'

yJ

,-~pp'~~·A
i
J

Pin malerial and plaling composilion
conform 10 Melhod 2003lsolderabililYJ
ofMIL-STD-883 (exceplparagraph3.21.
INCHES

OIM

MIN

MAX

.335

370

8.51

9.40

B

.305

.335

7,75

8.51

C

,1-65

.185

41.

4,70

°
,

.016

.021

0.41

0.53

E

.010

.040

0.25

1.02

J

.010

.040

0.25

1.02

G

.200 BASIC

H

.028

.034

0.71

0.86

.029

.045

0.74

1.14

K

.500

L

.110

.160

2.79

M

45° BASIC
.105
.095

/

~

K

~

~J~D

j

J

MLL---I
INCHES

DIM
Pin numbers shown for
reference only. Numbers
may not be marked on
package.

5.08 BASIC

,.

B
C
D
F
G
H

J
K

12.7

L
M
N
R

4.06

45° BASIC
2.41

I Iii

.J-..j.

MAX

A

N

R

L

MILLIMETERS

MIN

Pin material and plating composition
conform to Method 2003 (solderability I
of MIL-STD-883lexcepl paragraph 3.21.

"I'i-

tin plaled.

1

NOTE:
Leads in true position within 0.01"
IO.25mml R al MMC al sealing plane.

j

PI,..

The TO-99 can and leads are bright acid

~
~:
!'
'0
N 1
L

a-PIN HERMETIC DIP
("Z" SUFFIX I

D

'''oW"''''

-;J

E

PACKAGE

2.67

1-15

MILLIMETERS

MIN
MAX
MIN
MAX
8.58 10.28
.871 .40.
a.22
a.8a
.211
.24
.140 .170
S ... 4.12
.021
.01
0.8
0.1
.04. .oao
1.1
1.12
.100 BASIC 2.U BABIC
.08.
2.U
.001 .012
0.2
0.30
.150
3.1
.210 .820
1.1
7.8
O·
11·
o·
15·
.oao
.008
0.28 1.12
.12
.171
8.1
4.4

-

-

-

-

PIN CONFIGURATION
(TOP VIEW)

'OUTPUT

OPTIONAL
TRIM

-Vee

'NO INTERNAL CONNECTION

'NO INTERNAL CONNECTION

TYPICAL PERFORMANCE CURVES
ITA = +25°C, ±Vee = 15VDC unless otherwise noted)

OPEN-LOOP GAIN vs FREQUENCY

160
140

-55°C I
+25°C
250C

,::Si

iii 120

280

bci

,

~

.~ 100
Cl

~

60

0

40

~

"

i

.i!

20

120
60

0.010.1

8.

jI

.!!
 5).
Noise is typically only'3nY/v'HZ at 1kHz with an
exceptionally low llf corner frequency of 2.7Hz.
Peak-to-peak noise is just 80nVin a 0.1 Hz to 10Hz
bandwidth.

APPLICATIONS
• TRANSDUCER AMPLIFIER
, • LOW NOISE INSTRUMENTATION AMPLIFIER
• DATA ACQUISITION PREAMPLIFIER
• PHONO AND TAPE PREAMPLIFIER
• FAST D/A CONVERTER OUTPUT
• WIDE BANDWIDTH INSTRUMENTATION AMPLIFIERS
• PRECISION COMPARATOR

Offset voltage is typically just 10", Y and drift is only
0.2",y/"C. 125dB open-loop gain is matched with
l25dB common-mode rejection ratio. Power consumption is only 3mA.
The same basic op, amp comes in two frequency
compensation versions. The OPA37 is lightly compensated and provides l7Y; ",sec slew rate and
63MHz gain-bandwidth product. The OPA27 is
more heavily compensated for better frequency
stability in low gain applications. It has a 2.SY I ",sec
slew rate and an SMHz unity gain frequency.

OUTPUT

Intemllional Airport IndUltrl., Park· P.O. Box 11400· TuclOR, Arizona 85734· Tel.l&ni) 746-1111 • Twx: 91(1.952·1111· Cable: BBRCORP· Telex: 66-6491

1-17

SPECIFICATIONS'
ELECTRICAL
.AITA = +25°C and +Vcc
= 15VDC unless otherwise noted.
-

I OPA27137A, OPA27mE OPA27mB. OPA27137F1 0PA27mC;OPA27/37G I'
I MIN I TYP MAX I MIN I TYP. I 'MAX I MIN T¥P I MAX UNITII

."

PARAMETERS

CONDITIONS

INITIAL OFFSET VOLTAGE

Initial Offsetl')
Over Temperature
Average vs Temperature

.

• Over Temperature
Average vs Temperature
Long Term Stability(3)
Offset Adjustment Range

.'

TA == +25°C
A, S, C -55°C:5 TA '$ +125°C
A. B, C -55°C:5 TA:5 +125 o C(2)

E, F, G -25°C:5 TA:5 +85OC
E, F, G -25°C:5 TA:5 +85 0 C(2)

10
30
0.2
20
0.2
0.2
±4

25
60
0.6
SO
0.6
1.0

20
SO
0.3
40
0.3
0.3

60
200
1.3
.140
1.3
1.5

30
70
0.4
55
0.4
0.4

100
300
1.8

7
15
10

35
SO
SO'

9
22
14

50
85
85

~10

±40
±60
±60

:t12

±55

±20
:!14

±28
±18

~

0.08
3.5
3.1
3.0
1.7
1.0
0.4

0.18
5.5
4.5
3.8
4.0
2.3
0.6

~V

~V

,sVloq

22

~V

1.8
2.0

lJV/oC
",Virna
mV

12
30
20

75
135
135

nA
nA
nA

±15
±35

±25 .

±SO
±150
±150

nA
nA
nA

0.09
3.8
3.3
3.2

0.25
8.0
5.6
4.5

~V. p-p
nV,,'Hz
nVVHZ
nV JHi:

INPUT OFFSEt CURRENT
Initial Offset

TA - +25°C

Over Temperature

A, B., C -55°C:5 TA:::; +125°C

E. F. G -25°C:5 TA:5 +85°C
INPuT BIAS CURRENT

Initial Bias
Over Te~perature

TA =+25°C
A, B. C-55°CSTAS+12So C

e, F, G -25°C $

TA:5 +85°C

±as

INPUT NOISE

O.lHz to 10Hz(4)(5)
fo = 10Hz(4)

Voltage
Voltage Density

=30Hz(4)
fa = 1oo0Hz(4)
fo

fo = 10Hz(4)(6)
fo = 30Hz{4JlbJ
fo = l000Hz(4)(6)

Current Density

pA\1Hz
pAVHZ
pAv'Hz"

INPUT RESISTANCE
DifferentiaU7)

1.5

6
3

Commo,n-Mode

1.2

5
2.5

0.8

4
2

Mil
Gil

INPUT VOLTAGE RANGE

Initial Input Voltage
Over Temperature

T,,- +25°C
A, B. C ·55°C:5 TA:5 +125°C
E, F, G ·25°C :STA S +85°C

\

±11.0
±10.3
±10.5

±11.5

114
108
110

126
122
124

106
100
102

123
119
121

100'

96

120
116

94

.97

118

96

1000
250
600

1800
1500
700
1200

500

7SO

1500

±12.3

V
V
V

±11.8

COMMON-MODE. REJECTION RATIO

Initial Rejection Ratio
Over Temperature
Over Temperature

. VCM = ±11V
A, S, C ·55°C:::; TA:S:: +125°C

E, F, G -25°C STA:5 +85°C

100
94

96

120
116
118

dB
dB
dB

114.

94
86

118
110

dB
dB

116

90

114

dB

700

1500

1000

200
300

500
800

V/mV
V/mV
'V/mV

700

1300

450

1000

VlmV

POWER SUPPLY REJECTION RATIO

Initial Rejection Ratio
Over Temperature
Over Temperature

±Vcc =4V to 18V
A. B. C -55°C STA S +125°C
·±Vcc'=4.5V to l8V,
E, F..G -25°C :S TA S +86°C
±Vcc

=4.5V,to laV

'

LARGE SIGNAL VOLTAGE GAINI.)

Initial Voltage Gain

RL <= 2kll. Vo - ±10V
Fk ~ lkCl, Vo = ±10V

Over Temperature
Over Temperature

RL ~ 6000. Vo = ±lV, Vee = ± 4V !71
A. S, C -55°C S TA -;:; +125°C

=

AL ~ 2kU. Vo ::!:10V
E, F. G -25'OC ':5 TA:5 +85°C
RL ~ 2kU. Va ±10V

sao

-

V/mV

=

RATED OUTPUT
Initial Voltage Swing

RL ~ 2kn
RL~600n

Over Temperature
Over Temperature
Output Resistance.

A. B. C -55°C' ':5 TA '5 +125°C
RL ~2kn
E, F, G -25°C:5 TA:S +85°C
,RL ;?2kO

±12.0
±10.0

±13.8
±11.5

±11.5

.±13.5

±11.5

±13.5

:tl1.0

±13.2

±10.5

±13.0

V
V
V

±11.7

±13.6

±li.4

±13.5

±11,0

±13.3

V

Open Loop

70

n

2.8
17
8
40

V/psep
V/psec

DYNAMIC RESPONSE
Slew Rate
Gain~8andwjdth

Product

'OPA27
9 PA37
OPA27
OPA37

1.7
11
5

1-18

MHz
MHz

ELECTRICAL (CONT)

I
~I~I~I~I~I~I~I~I~~

LOPA27/37A, OPA27/37E ~ OPA27/37B, OPA27/37F ~ OPA27/37C, OPA27i37G
. CONDITIONS

PARAMETERS

I MIN

POWER SUPPlY .,

VDC
VDC

~15

Rated Voltage .
Voltage Range
Current. QUiescent
Power Consumption

!:22

±4

±4.7
140

"3
90

'.

"3.3
100

mA
mW

::tS.7
170

TEMPERATURE RANGE
Specification

A,'B,C

Operating

A, B. C

e,F. G
Storage

·C
'C
'C
°C
'C

+125
T85

-55
-25
-55
-25
-65

e, F, G

+125

.85
.,..150

·Speclflcatlon same as OPA27/37A and OPA27/37E.

NOTES: (1) The input offset voltage tests are done on automatic test equipment approximately 0.5 seconds after power is applied to the device. The A and E grades
have guaranteed specifications under full warm up conditions. (2) .Offset voltage drift with temperature specification holds for the unnulled condition or when nulled
with R, = 8kClto 20kCl. (3) Long term offset voltage stability is defined by an average, extended time, trend line (Vas YO temp.) after 30 days of initial operation. As
shown in the typical performance curves, Vos ch~nges approximately 2.5pV in the first 30 days excluding the initial hour of operation. (4) Parameter is not 100%
tested; 90% of units meet this speci~ication. (5) See Figures 1 and 2. (6) See Figure 1 for current noise measurement. (7) Parameter is guaranteed by design and is
not tested. (8) Closed-loop gain 2: 5 is required for stability in the OPA37. OPA27 is stable at unity gain.

ABSOLUTE MAXIMUM RATINGS
Supply Voltage. , .. , , , , .... , , , .. , , ......... ±22V
Internal Power Dissipation(l) " " ' , ....... 500mW
Input Voltage(2) ",., ... ,',." .. , ....... ,., ±22V
Output Short Circuit Duration/3 ) , , ••• , ••• Indefinite
Differential Input Voltage (4) " , . , ' , . , " . " ' , ±O,7V
Differential Input Current (4) " •• , . , . , " , •• ,±25mA
Storage Temperature Range"" -65°C to +150°C
Operating Temperature Range
A, B, C .,.,., ............ -65°C to +1500C
E, F, G ..... ,' , , , , .. , ... , .. -25°C to +85°C
Lead Temperature Range
(Soldering,60sec) , .. '.,., .. ".,." ,300°C

NOTES:
1. Maximum package power dissipation vs ambient temperature.

Packege
lYpe

Maximum Ambient
Temperature for Rating

Derate Above
Maximum Ambient
Temperature

TO-99IJI

80'C

7.1mWI'C

s-.Pin Hermetic
DIP(Z)

75°C

6.7mW/'C

2. For supply voltages less than ±22V, the absolute maximum input voltage
is equal to the supply voltage.
3. To common with ±Vcc = 15V.
4: The inputs are protected by back-ta-back diodes. Current limiting
resistors are not used i" order to achieve low noise. If differential input
voltage exceeds ±O.7V, the input current should be limited to 25mA.

ORDERING INFORMATION

Tz

OPAXX
Y
Basic Model Number - _ _::~I-Performance Grade Code
.
A, B, C: -55°C to +125°C
E, F, G: -25°C to +85°C
Package C o d e - - - - - - - - - - - - l
J = TO-99
Z == 8-Pin Hermetic DIP

TO-99 J SUFFIX

a·PIN HERMETIC DIP

OPA27AJ
OPA27BJ
OPA27CJ

OPA27EJ
OPA27FJ
OPA27GJ

OPA27AZ
OPA27BZ
OPA27CZ

OPA27EZ
OPA27FZ
OPA27GZ

OPA37AJ
OPA37BJ
OPA37CJ

OPA37EJ
OPA37FJ
OPA37GJ

OPA37AZ.
OPA37BZ
OPA37CZ

OPA37EZ
OPA37FZ
OPA37GZ

1-19

. .. .
,Il!! ~. EI
120

:>

80

.,

S

22~IFSCOPE
XI

40

·S

z

'"0
11"

RIN= IMn

0

-40

> -80

IIOtn

== =-

,.

--

-~

._.

-

--

!!!!! ,!!!!! l!!

I"l

== 'L" .• ;.;..••
'a4
,

~... ...

-120

NOTE; ALL CAPACITOR VALUES ARE FOR
. NONPOLARllEO CAPACITORS ONLY.

O.IHztO·10Hz Peak-to·Peak Noise'

FIGURE 2. Low Frequc,mcy ,Noise.

FIGURE I. O.IHz to 10Hz Noise Test Circuit.

MECHANICAL
TO·99 PACKAGE

8·PIN HERMETIC DIP
I "z" SUFFIX I

,,~)I '.~'"""
~ •

,

1-

~-

I... IIIII

F

I

IIII

. s.,,,",
Plane

K

.......a.....D

1

4f1
¥J
T·~t~
M

INCHES

DIM

MIN

MAX

0.

MILLIMETERS

MIN

A

.335

.370

8.51

B

.305

.335

775

c

MAX
9.40
851

D

155

185

4.19

470

015

.021

041

053

E

010

040

025

1.02

025

102

F

J

.010

040

G

200 BASIC

H

02.

034

0.71

08.
114

045

0.74

.500

127

L

160
110
45° BASIC

2.79

105

2."41

M

N

095

.0

~~'e

~

..1-..1 I.-~.
G

NOTE:
Leads in true position within
0.10· (0.25mm) R at MMC at
seating plane.

INCHES

DIM

A

•

C
D

Pin numbers shown for
reference only. Numbers may
,not be marked on package.

F

II
H

['08 BASIC

K

.029

A-1
~j

c

'.06

45° BASIC

2.7

J
K

Pin material and plating
composition conform to
Method 2OQ-1. (solderability)
of MIL-STD-883 except
paragraph 3.2).

II
R

MIN

MILLIMETERS

MAX

.... ....

MIN,

MAX

J

M

~-.~

NOTE:

Leads in true position within

0.10" (0.25mm) R at MMC at
1.1' 10.21
. seating plane.

.871 .401
.111
.141
.140 .170
'.11 4.'
0,
.011
.01
. 4
1.1
1
.100 BAIIC I ... A.IC
.0"
'.4
• 01 .1
D••
0.'
.1'0
... 0 .110
'.1
O·
1.·
O·
1'·
D••
1..!.a
. 00' .0'
.17, '.1
.1.
4.4

-

.- •••
r.'

Pi~ m~terial and plating
composition conform to

Method 2003 (solderability I
of MIL·STO-883 except
paragraph 3.21.

PIN CONFIGURATION

OFFSET TRIM

OFFSET TRIM

·IN

+Vce

+IN

OUTPUT
NO INTERNAL
CONNECTION

-Vee

-Vee
ICASEI

8-PIN DIP

ITOPVIEWI

1-20

TYPICAL PERFORMANCE CURVES
(TA

= +25°C, ±Vcc = 15VDC unl_ otherwi.. noted)
O.IHz TO 10Hz, p-p NOISE TESTER
FREQUENCY RESPONSE

100

VOLTAGE NOISE VS
FREQUENCY

A COMPARISON OF OP AMP
VOLTAGE NOISE SPECTRUMS
100

-

~,

90

80

\..

,

~70

r--

i

~80
50

I

I

i

30
0.01

a..
=

,
I/F (orner

JJ

,

LowNoiae

~UdiOOP~~

~

IIfCorner

~DPA27137

Test Time 01 1018C Further Limits
Low Frequency «O.IHz) Gain

"0

C

I!lCorner
2Hz

III Corner = 2.7Hz

I

.....

N

741

"I

....

"

.5

r--

0.1

1.0
10
Frequancy (Hz I

10
100
frequency (Hz I

100

"""'" "'""" " \I'i'"
INPUTWIDEBANDVDLTAGE NOISEVS
BANDWIDTH (0 1Hz TO FREQUENCY INDICATED>
•
100

. ,1,111111. , I ,
r"tlnotrumantation
Range, to DC

i

lllll!.
_I..!J!]
Audio Range
1020kHz

10
100
Frequency I Hz I

1000

,

1000

TOTAL NOISE VS
SOURCE RESISTANCE

5

~
R2

~4

Rs =2Rl

I

%
./

O.

....

I-At lilHz

CI

~kHz

o.01

,V iimrNTrv~

.0
0
Bandwidth I kHz I

0.1

g2

100

1

lk
Source Resistance I U I

VOLTAGE NOISE VS
SUPPLY VOLTAGE

-so

10k

-25

o

25
50
75
Temperature 1°C,

100 125

SUPPLY CURRENT VS
SUPPL Y VOLTAGE

CURRENT NOISE VS
FREQUENCY
5.

5

.....

4

en o
At 10Hz

100.

-

3

«

4.

E

1:
~ 3.

At 1kHz

"

U

>Q.
C>

2

en" 2.

1

1.

TA= -55°C

o

10k

10
20
30
40
Total Supply Voltage I +Vee - -Vee' IV
OFFSET VOLTAGE DRIFT
OF REPRESENTATIVE UNITS

80

OPA27/37C

LONG TERM DRIFT OF
REPESENTA TlVE UNITS

~20

"g>

~

~

<."

~ -20
91
::

0_40
-60

~

.......

--

"

I-Trimming with
rOk Pot does not
change TfVols

-75 -50 -25

J!!'y7/~7A

-"

....... ~P~27/37B
OPA27/37A
I I

./

0

'6

......,~

"..

.......

""

OPA27/37A

J

I I

OPA27137B

I I I

WARM-UP DRIFT

./'k

'"

,.......... .....

--

.....",

.....

-

JPA271J7C & G

""

L

~

~ ..-

"-"

'J

OPA27/37C
0 25 50 75100 125150175
Temperature (0C)

45

6

V'"~1271?7R

r-

35
15
25
Total Supply Voltage 'V

5

6
Time' months

1-21

j

V
I-'

OPA27/37B & F
~

lILV-

r-

.1
OPA27/37A & E

V

1
2
TimeAfterPowerOn minutes

INPUT BIAS CURRENT
iIs TEMPERATURE

OFFSET VOLTAGE CHANGE
DUE TO THERMAL SHOCK .

I
I

I II I I
I I I I,'

Tot= TA'=+700c

r(

25"C

Immel1l8d
I-f- :t~ce
In 7O"C 011 Bath

-

130
110

en

«I

60
Time \l8COl1d81

o

100

\.

...r-.I'o

"

A'I I

Ilf I I I
20

-50 -25

0

,~ ~ t'--. ...

~A2r47~

25

iitti

50

·15 -50 -25 0 25 50 75 100 125
Temperature (OCI
GAIN, PHASE SHIFT
VS FREQUENCY

SLEW RATE. GAIN.BANDWIDTH PRODUCT.
PHASE MARGIN VS TEMPERATURE

25·r.......
-..,1...-MIr-Mr-rn...--r-rT-rTTTnaO
OPA27

I--

,~

-

120 iii
r--"\:lG.t
.,n +++-HIU-IH\--I-+++H+H
I I" 1\
!!

15 \ .

~ 70

~ 10 f--t~+ ~h!~-+
\-t"++I-ti~ l«1l
c
~ Maivln
!
700C
160 ~

50

14

&50

--.

;3

I'\.
'\.

10

OPEN-LOOP GAIN
VS FREQUENCY

rJl

;;;

RL~2k{J

"- \.

OPA37

~ 75

-

;: 70
.~ 65
:::I!
;60

.-- .-

~55

~3O

~.

~ 25
.,20

I\.

o
I

~

\
10 102 103 IOO 106 106 101 106
Frequency (Hzl

15

VRL~kO

- -

-:1.5

~

60 ~rr~--,,-n'mr-rrnnm~

~

40

:::I!
70 ;:

-~
Slaw- r-=

/.: V

fOg IV-

I--f-H~IFI--:=f-++tlflll--+++I-I+IH -120

u

!g3O f-+lrH-HII~-haPhr.a",semqrl+I++HH -140

6OC:

~2O f--+l+'T1IIrt-~mfM1lH+lrH-I+IH -160

65-ilo·

Gain

c

£
55 :!2
;r

10

.

501!

1\ ::;rl'1.'~ \

·i

40
o +25 +50 +75 +100 +125 Cl
Temperature (oC,

Frequency (MHz I

MAXIMUM OUTPUT SWING
VS RESISTIVE LOAD

18

~o~itivl

14

~

~12 ~ing

eg

~

Swing

/.

va

~6
4 '(/

)P. !7

o

1\

0.5

i'" 10
8

2

o
o

10
20
30
40
Total Supply Voltage 'V,

50

o

I

lk

)k

10k
Frequency 1Hz·

1-22

\/I

~M

iii
..

Q.

-10 ~~UU~~~~~~~-2~
0.1
1.0
10
100

16

I

~

r1_~~+W~~~~~~A~VHC~-~5 -160 ~

0

45 III

IOPA3

,

OPA37

r...

"

GBW- I--

210
100

50 ......H"tdiitll-~2.0

-10
-50 -25 0 25 50 75 100 125
Temperature lOCI

SLEW RATE. GAIN BANDWIDTH PRODUCT
PHASE MARGIN VS TEMPERATURE

~60

::

\

-51--+-!~++++I-~..Jo'~~++HI200

-Slew

-75

."

=\

."",

0r--+-+~~~-~r+++~160!

12

10 100 lk 10k lOOk 1M 10M 100M
Fr.,quency (Hz I

r\.

w

a::

-10

1«1

IOPA27

2Of-..,.~~~+++H~~~~~~loo

!!

I

OP~717A

o

75 100 125 150

t:emperature (OCI

OPEN-LOOP GAIN VS
FREQUENCY

~OPA27137B

....

iD 60

,!!
o
>30

-oPA(l7l37C

.1\ 1\

li~"-l
aa"rae

o

h

OPA27137C

fN.1 I

fff-

INF!UT OfFSET CURRENT'
. VS TEMPERATURE
50

50

-2

0.1

1.0
Load ReSistance I kt}'

10

SMALL SIGNAL
TRANSIENT RESPONSE

SMALL SIGNAL OVERSHOOT
VS CAPACITIVE LOAO
l00r---~--'---~---'----'

j~~~--~~~---+---i

I
i

c «I1---ifL---+--!--+-~ o

!

Av=+1

OPA27

AVCL = +1, CL = 15pF

OPA27

AVCL=+1

Time (I'MCI

500

1000

1500

Capacitive Load

2000

SMALL SIGNAL OVERSHOOT
VS CAPACITIVE LOAD

120

I

Time

·2500

I
6PA37

LARGE SIGNAL
TRANSIENT RESPONSE

SMALL SIGNAL
TRANSIENT .RESPONSE

1

f-V1n = 20mV

~

Oscillation

/

/

..--

+50

f~

0

I

~

0-50

II
o

("sec I

(p~ J

o

3

6
OPA37

Av=+5

o

Av = +5

0.4

O.S

CL = 25pF

Time ("leCI

Time (1£S8C I

OPA37
.

500 1000 1500 2000 2500 3000
Capacitive Load (pF J
SHORT CiRCUIT
CURRENT VS TIME

COMMON-MODE INPUT
RANGE VS SUPPLY VOLTAGE

CMRR VS FREOUENCY

16 r---..,.-----r-----~-=~
12\---+~

~

>

120 f-

~S:tJ

ID

iSC(+J

U

" l00f-

~

~

~

8Or-

I
10

4
o
2
3
Time from Output Shorted to Ground! minutes I

~

103

A37

PA2

104

1I

IIIf r\
Ilill

108

1()6

-16!:-0--+---,~--:-~=~

107

Frequency I Hz,

OPEN-LOOP VOLTAGE
GAIN VS LOAD RESISTANCE

PSRR VS FREOUENCY

2.4

160

:> 2.2

~ 1«1
o

"-

~2.0
.~ 1.8

C; 1.6

:; 120

lao I--PO.iti~

.

II:

~1.2

li

.3 1.0

~

~

en 40

0 0 .&

~ 20

~

1.0
10
Load Resistance (kill

o

100

Negative
~SUPPIY

Supply

60

Q.

io.s

0.4
0.1

~

,2 100

5!' 1 4

'15

.--

II:

i/

1

10

~

Frequency Hz·

1-23

~

102 103 104 108 1()6 107 108

APPLICATION INFORMATION
TheOPA27/37'are ideall¥ suited for general pJrposeor
high performance low voltage noise applications where
.input' impedaneesare moderate. These' amplifiers fit,
directly into ~he sockets of tlie 725, OP-05, QP-06; OP~
07; AQ510;,~nd AD517 without changing compensaticjn
or i1uilingcomponents. TyPical 741 nulling' circuitry,
howllver, ~ill require modification (or removal if' not
needed) as shown in'Figure 3.
'
Stable operation is inherently provided with capacitive
loads up to 2000pF at ±IOV output swing, but a series
son decoupling resistor should be used with larger
capacitances.
In high performance low noise applications, it is important to observe proper PC board layout techniques such
as short runs to the input pins and substantial ground
connections converging at a single point. Also, to achieve
the specified drift, careful attention must be pa.id to
minimizing thermoelectric voltages resulting from' dissimilar metals at the pin contacts. Best results can be
obtained by maintaining equal temperatures at both
input contacts which are equaj to the tllmperature of the
package. Also a 5-minute warm-up and minimization of
air currents are'recommended.

4.7kn

lUkU

5-o~_---o

+vcc

OUTPUT

FlGURE4. Offset Nulling Circuit.
UNITY GAIN BUFFER APPLICATIONS-OPA27
Figure 5 shows the output waveform sh~pe when the
feedback resistor, R r, is less than loon and the input
voltage is a fast rising large, signal greater than IV. The
break voltage appears as "feedthrough" and results from

lkn POT

1

+vcc

FIGURE 3, Higher Resolution Nulling Circuit.

OFFSET VOLTAGE ADJUSTMENT
The OPA27/ 37's input offset voltage and drift with
temperature have been precisely trimmed internally at
the time of manufacture, but should a refinement in
trimming be necessary, a potentiometer (see Figure 4)
can be used without degrading t1Vos/ t1temp. A minor
degradation in drift (0.1 to 0.2p.V/°C) will occur, however, if other vaiues from Ikn to IMn are used. Also
trimming a nonzero value will result in ali additional
drift ofVos/300p.V laC. For example, an adjustment of
Vas to lOOp.V will cause a 0.33jJ,V/oC drift change.
Higher resolution in Vos adjustment can be realized by a
smaller potentiometer value plus series resistors as shown
in Figure 3 (+280p.V adjustment range shown).

FIGURE 5. Pulsed, Operation.
the conduction of the input protection diodes which
effectively shorts the output t6 the input. A short circuit
current is then drawn by the input source. When the
feedback is greater than soon, the output is capable of
driving the required current (less than 20mA at 10V) and
the, amplifier remains, in its' linear region producing a
smooth transition.
All op amps have input capac~tance, so the feedback
resistor in combination with this causes a pole to. be
generated which gives an additional phase shift. Greater
than 2kO and 8pF adversely reduces the phase margin,
but this problem can be eliminated with a 20pF to 50pF,
capacitor in parallel with R r.

1-24

BURR-BROWN®

OPA100

IElElI

Low Bias Current JFET Monolithic
OPERATIONAL AMPLIFIER
FEATURES

APPLICATIONS

• LOW INITIAL BIAS CURRENT

• CURRENT-TO-VOLTAGE CONVERSION
• PRECISION VOLTAGE AMPLIFICATION FOR HIGH
INPUT IMPEDANCE APPLICATIONS SUCH AS:

1pA max al +25°C
• LOW BIAS CURRENT VI TEMPERATURE

20pA max al +85° C

pH electrodes
Biological prob./I~'8nsducerl

• HIGH INPUT IMPEOANCE. 10'20
• LOW OFFSET VOLTAGE. 250pV max
• LOW OFFSET VOLTAGE ORIFT. 5pV/oC max

• PHOTO DETECTOR CIRCUITS
• LONG-TERM PRECISION INTEGRATION
• HIGH IMPEDANCE BUFFER
• PRECISION SAMPLE/HOLD

DESCRIPTION
The OPAIOO is a precision monolithic low bias
current operational amplifier. An enhanced bipolar
FET process with JFET input transistors and dielectric isolation is used to achieve low input bias
current. Additionally, bias current compensation
circuitry is used to reduce the bias current even
further. In addition to lowering the bias current at
+25°C, this compensation significantly reduces the
bias current at higher temperatures.
Low offset voltage (250J.! V ml\x) and low voltage
drift (5J.! V /"C) are also guaranteed. This performance
is achieved by active laser-trimming the amplifiers

thin-film resistors.
The amplifier is free from latch-up and is protected
for continuous output shorts to common. Asan added protection feature. either of the trim pins can be accidentally shorted to supply terminals without damage.
The standard pin configuration (741-type) of the,
OPAIOO allows the user drop-in replacement capability. A pin 8 case connection permits thereduction
of noise and leakage by employing guardingtechc
niques.

·III~~----;L,

+IN

Internliional Airport Industrial Park .P.O. Box 11400· Tucson. Arizona 85734· Tel. (602) 746-1111 . Twx: 9111-952·1111· Cable: BBRCORp· Telex: 66-6491

1-25

SPECIFICATIONS
ELECTRICAL
At T. = +2S'C and ±Vcc= 1S\!DC unless otherwlaa noted.
OPA_M

OPA1OOAM
CONDITIONS

PARAMETER

V"",=;l:10V
TA == +25o.C

OPEN-LOOP GAIN. DC
Rated Load. RL ~ 2kO

T,,=:TMINtoTMAx

RATED OUTPUT
Voltage at RL == 2kO

T... ==TMINtoTMAX

Cutrent

TA=TMINtoTM~

Output Impedance
. "Load Capscitance1tl
Short Circuit Current

MIN

TYP

94
88

100
100

;1:10
;1:5

;1:12
;1:10
100
1000
40

500
10

.FIIEQUENCY RESPONSE
Unity Gain, Small Signal
Full Power Response
Stew Rate
Settling Time O.1~
Settling Time 0.01'4

10
0.6
10Vstep

10V step

MAX

MIN

TTP

100
94

106
106

OPA1OOCM
MAX

MIN

TYP

106
100

110
110

MAX

UNiTe

dB
dB
V
mA

n

.-

,

pF
mA

1
32
2
6
10

MHz
kHz
Vlpsec

5

""OC

pSeC
pSeC

Overload "Recovery.
50% overdrlve/ 21

INPUT OFFSET VOLTAGE'"
Initial Offset
Average Drift
Over Temperature

vs Supply

;1:200
;1:3

±100

;1:10

TA = +25°C
TA'= +85°C

;1:1
;1:10

;1:3
;1:100

;1:0.6

T... = +25°(::
T,.,=+85.oC

etO.5·
±10

T,.,=TM1NtoTMAJ(
TA == TMIN to TMAX

INPUT BIAS 'CURRENT'"
Initial Bias Current
Over. Temperature

INPUT OFFSET CURRENT
Initial Difference Current

Over Temperature

';...... 25°C

;1:1000
;1:15
;1:2
;1:100

T~

T,,:..:.TMlNtoTMAX

.1

_.

INPUT IMPEDANCE
Differential
Common-Mode

=
=
=

POWER SUPPLY
Rated Voltage
Voltage Range,
Derated Performance
Curten"!, Quiescent
TEMPERATURE RANGE
Specification
Operating
Storage
fJ Junction-Ambient

;1:50
;1:1

;1:2
;1:40

;1:0.3
;1:5

;1:250
.;1:5
±O.S
;1:25

"VI'C

, ;1:1
;1:20

pA
pA

mV
J-A!N

nil pF
nil pF
nVl,JH7.
nVl,JH7.
nVl,JH7.
nVl,JH7.

60

35
20
20

,

"V.P-P
pA, pop

0!01
0.03
0.6

1AI,JH7.
V
V

pAt nn8

±18
TA= TMINto TMA,x

±10

±12

TA= TMINto TMAJ(

76

82
±V",

88

94

94

100

dB
V

;1:15
±5
1.0

TA = TMIN to TUAJ(

"V

pA
pA

±5

10'· II 6
10'3 11 6 '

INPUT NOISE
Voltage: 10 10Hz
10 100Hz
10 1kHz
fo = 10kHz
f8 = O.lHz to 10Hz
Current: fa =,O.lHz to 10Hz
f8 == 10Hz to 10kHz
fo'= 1kHz
INPUT VOLTAGE RANGE
Differential
Common-Mode
Common-Mode Rejection,
VIN ':"; ±10V
Maximum Safe Input Voltage

;l:SOO
;1:10
±lI;1:1.5
;1:25

VDC
±18
3

2

1.5

VDC
mA

Ambient

-25
-55
-65

+85
+125
+150

'C
'C
'C

'e/W

300

·Speclfication same as for OPAlooAM.
NOTES: (1) Stability guaranteed with load capacitance SSOOpF. (2) Overload recovery is defined as the time required for the output to return from saturation to
linear operation following the removal of a 50% input overdrive. (3) Offset voltage and bias current are guaranteed after 1 minute of operation at TA = +2500. Th,y
are 100% tested. .
L

(

1-26

ABSOLUTE MAXIMUM RATINGS

ORDERING INFORMATION
OPA100

Basic model number ~~~~~--r-~
~
--.J
Performance grade
A. B. C -25°C to +85°C

r-r
X

X

Packagecode-----------------------------J
TO-99 metal can. M

MECHANICAL
TO-99 PACKAGE
NOTE:
l.eads in true position withjnO,010" (O.25mm! A at MMCat
seating plane.
Pin numbers shown for reference only. Numbers may not
be marked on package.
Pin material and plating composition conform to Method
2003 [solderability [ of MIL-STD-BB3 [except paragraph
3.21.

~F:~
l,rllill

.!

=+1

Seating
Plane

111111

N,
m
,-?J
---I~ D

• ---.1 "

L

T

M

DIM

IfIICHes
MIN
~AX
.305

370
.335

10.
.016

18'
.021

E

0'0

F

.010

040
.040

A

•

C
0

G

N

M

0
+ 0
'os iojJ

.335

200 BASIC

f

MILLIMETERS

MIN

MAX

8.51

9,40

'"

8.51

4.19

470

0.41

0.53

0.25

1.02
1.02

0.25

5 08 BASIC

H

.028

.034

071

0.86

J

.029.

.045

0.74

1.14

K

.500
.160
110
45° BAStC
.105
.095

12.7

L

M
N

2.79

4.06

45° BASIC
2.41

2.67

1-27

Supply .......................................... ±1 BVDC
Internal power Disslpatlonl'l ......•.......•..••..• 500mW
Differential I nput Voltagel2) ..•....•..••.••••••••• ±36VDC
Input Voltage Rangel21 ........................... ±1BVDC
Storage Temperature Range .•.......•.•• -65°C to +150oC
Operating Temperature Range ......•...• -55°C to +125°C
Lead Temperature (soldering. 10 seconds I ....... : +3OO°C
Output Short Circuit Duration(3) .............. Continuous
Junction Temperature ......••.........•....•.... +175°C
NOTES:
1. Package must be derated based on: 6JC = 150'CIW or8J. =
300'CIW.
2. For supply voltages less than ±1BVDC the absolute maximum input vOltage is equal to the supply voltage.
3. Short circuit may be to power supply common only. Rating
applies to +25 0 C ambient.

TYPICAL PERFORMANCE CURVES
At TA';' +25'C and ±Vcc = 15VDC unless otherwise' noted.

~ 1000

-+-1--1+45 ~ _+101-+--lr-+t-+

~ 0; +51-+"""'-H

-+-+-, 0

:r. g
'i5

.::

t

01-++1--1-·

0.>

,~--~~~~~~-~ ~; ~0. ~

>

.E -10

z

+-+-+~I-'H-135J!

1

r--r--r--;--;r--,-,1.3
M~

COMMON-MODEI POWER
SUPPLYIREJECTION RATIO

STABILIZATION TIME OF
'INPUT OFFSET VOLTAGE
FROM POWER TURN-ON

P>

80

l;l

'iD

§
E
E

8

~
-.

-t-t+

I

,8

-10

=-rg

0

0.9

~

Frequency IHz I

I BIFET'I,V
(LFI55 TYPE)

-

-

1011

r- V

/

STABILIZATION TIME OF.
INPUT BIAS CURRENT
FROM POWER TURN-ON

E

~400
u"
.gj300
in
~200 r-

r-

Time from Power Turn-on 'tsec)

\

.I

t

~

2

3

--

r~tt ~'j I I I

c3

INPUT BIAS CURRENT
The OP..\100 uses FET input transistors with dielectric
isolation to achieve low input bias currents. Additionally,
bias current compensation circuitry is used to reduce the
bias current even further. In addition to lowering the bias
current at +25°t, this compensation makes significant
reduction in the bias current at higher temperatures.
Figure I shows an improvement of over a decade for
temperatures above +75°C.

JUN~TlOJ ISO~TEII

--+-

5+30 1--+l--+-11---+--+_--I

APPLICATIONS INFORMATION

1000

'1

Temperature (OCI

~ 500

~ +201-+--.l't-+-

20tt ttttj~:: !
-15 -10 ~ d +5 +10 +15
Common-mode Input Voltage IV)

'1'

0·~7L.5-_...I25-+2:':5~+-7"::5~+-:'12::5~+~1::7-:-'5

10k

~ +101-+--+...."......=f--

~"I--+--+-'-+'-+oL..Jl.0 III

CI>

->

~

1.1

0.6

I

10
100
lk
Frequency 1Hz)

120 r--r-..--;-r--r-.,

11--+>_=,

II:

I

10

1

1.2

a; O.B

Time (J'sec)

-J;;.o-+-+-t-"k--t l .q

a:

~

z

~

"-;

i'-. ~

40 50.E

COMMON-MODE REJECTIONI
BIAS CURRENT

,g

>

100

5l

Frequency (Hz)

c:

1.41-+--+-h

i"

'0

°1~~10~I~OO~~~~~~

1.6 r--r.,..--,r--r--r-,

~

.. >

~--+--+--I-45

FREQUENCY
CHARACTERISTICS

INPUT NOISE VOLTAGE
vs FREQUENCY

0

4

Time from Pow~r Turn~on (sec)

The compensation causes the polarity of the bias current
to be indeterminate (note the "±" signs for 18 in the
electrical specifications). This means that the bias.current
may flow into or out of the amplifier inputs.
VOLTAGE NOISE
In mllllY FET amplifier applications the voltage noise is a
critical parameter. The bias current cancellation design
of the OP A 100 allows low noise without sacrificing low
bias current. Figure 2 shows the noise of various types of

V 'I:\
J

~_Opil00
Vr--... / .~
"""
7V ¥r/
,,
~

i
-;. 10

j

.....

DIELECTRIC ISOLA TED
IJFETI\
(HA5180 TYPEI

1

-- -- --

0.1
-15

-50 -25

~~

o

BIAS-CURRENT·
COMPENSATED
DIELECTRIC
ISOLATED JFEl

',. ~OLAR SUPERP BETA.
_1(~M~} 1"!

i--

+25 +50 +15 +100 +125 +150 +115 +200

Tlmpal'l1Ura (OCI
'Rqlllerad trademark 01 Nllional Semiconductor Corp.

FIGURE 2. Noise of Various Low Bias Current Op
Amps. (A) OPAIOO; (B) LFI55 type,
(C) LM I I type, (0) HA 5180 type.

FIGURE I. Absolute Value of Bias Current
vs Temperature.

1-28

"

low bias current operational amplifiers. The noise test
circuit used has a gain of 100kV / V with a I-pole filter at
0.1 Hz and a 5-pole filter at 10Hz.

l00kn recommended
although any
potenHomalllr between IOkIl
and l00kll will work.

GUARDING AND SHIELDING

As in any situation where high impedances are involved,
careful shielding is required to reduce "hum" pickup in
input leads. If large feedback resistors are used, they
should also be shielded along with the external input
circuitry.
Leakage currents across printed circuit boards can easily
exceed the bias current of the OPA 100. To avoid leakage
problems, it is recommended that the signal input lead of
theOPAIOO be wired toa Teflon standoff.lftheOPAIOO
is to be soldered directly into a printed circuit board.
utmost care must be used in planning the board layout. A
"guard" pattern should completely surround the high
impedance input leads and should be connected to a low
impedance point which is at the signal input potential.
The amplifier case should be connected to any input
shield or guard via pin 8. This insures that the amplifier
itself is fully surrounded by guard potential. minimizing
both leakage and noise pickup (see Figure 3).

"L-----Gy.

~------------------------------~
FIGURE 4. External Nulling of Offset Voltage.
APPLICATION CIRCUITS
The OPAIOO is ideally suited for low bias current, high
input impedance applications. Also because the noise
and offset drift errors are low, total high performance can
be achieved. Figures 5 through 8 show a photodiode, pH
probe, isolation, and integrator amplifier.

FIGURE 5. pH Probe Amplifier.

AS LOW AS r-'-___l..,OO"'M"Il_"-~:-1

r-.r::::;:::;~

500pA

,

IIN-

I

I
+
OUTPUT
INPUT----- J
UNITY GAIN BUFFER

80 50mV

R2

·15V

PIN PHOTODIODE

I

I
+
OUTPUT
INPUT -- - - - J
NONIIlVERTING AMPUFIER

\.:::':~9t-SODIUM

*

IODIDE CRYSTAL

Board layout lor Input GUlnltng
with TO-99 PIckage.

FIGURE 3. Connection of Input Guard.
OFFSET VOLTAGE ADJUSTMENT
Although the OPAIOO has a low initial offset voltage
(2501L V), some applications may require external nulling
of this small offset. External offset voltage adjustment
.changes the .drift by approximately 0.31L VrC. for every
IOOIL V of offset adjusted. See Figure 4. .

1-29

FIGURE 6. Computerized Axial Tomography (CAT)
Scanner Channel Amplifier:

:s

<

a..
=

....,.

lKn

TOTAL GAIN = 1000

lMn

lMIl
BIPOLAR:

VOUT
±10Vmaxoul

OUTPUT COMMON
INPUT COMMON

12KIl
BB 722
ISO PIS

V+
<

;-Il~l

FIGURE 7. Low Level High Impedance Isolation Amplifier.

1----.,
I

r- _ _ .J

I I

I I
I I
GUARO--!

+15V

i
I
I

~ - - - - -, t-'cF'--:----"-_--.
I-----~

I
I

I
I
I
lI __

VOUT

FIGURE 8 .. High Accuracy Integrator with Reset_

NON-ISO

I

,

<

.~~

i!iV"+'~V

-

BURR-BROWN,®

OPA1'01
OPA102

IE:lE:lI

-~

CI

CI

Low Noise - Wideband
PRECISION JFET INPUT OPERATIONAL
AMPLIFIER
FEATURES

APPLICATIONS

• GUARANTEED NOISE SPECTRAL DENSITY 100% Tested

• LOW NOISE SIGNAL CONDITIONING
• LIGHT MEASURMENTS
• RADIATION MEASUREMENTS

• LOW VOLTAGE NOISE - 8nV/JRZ max at 10kHz
• LOW VOLTAGE DRIFT - 5MV/OC max (B grade)

• PIN DIODE APPLICATIONS

• LOW, OFFSET VOLTAGE - 250MV max (B grade)
• LOW BIAS CURRENTS -lOpA max at
25°C Ambient (B Grade)

• DENSITOMETERS
• PHOTODIODE/PHOTOMULTlPLIER CIRCUITS

• HIGH SPEED -IOV/Msee min (OPAl 02)

• LOW NOISE DATA ACQUISITION

• GAIN BANDWIDTH PRODUCT - 40MHz (OPA102)

DESCRIPTION
The OPAIOI andOPAI02 are the first FET
operational amplifiers available with noise characteristics (voltage spectral density) guaranteed and
100% tested.
The amplifiers have a complementary set of specifications permitting low errors in signal conditioning
applications; low noise. low bias current. high openloop gain. high common-mode rejection. low offset
voltage. low o'ffset voltage drift. etc.

In addition. the amplifiers have moderately high
speed. The OPAlOl is compensated for unity gain
stability and has a slew rate of 5V I Msec. min. The
OPA 102 is compensated for gains of 3V I V and
above and has a slew rate of IOV! fJsec. min.
Each unit is laser-trimmed for low offset voltage and
low offset voltage drift versus temperature. Bias
currents are specified with the units fully warmed up
. at +25"C ambient temperature.

-Vee

,Vee

* OPA10l ONLY

International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona B5734· Tel. 16021746·1111 . Twx: 910·952·1111 . Cable: BBRCORp· Telex: 66·6491

1-31

·.' SPECIFICATIONS
'"

ELECTRICAL,
Specifications al TA - +25°C and +Vcc = +15VDC unless otherwise noted

"

MODEL
PARA~ETER

,

,

-

CONDITION

,,

MIN

,

OPA10l/102AM
TVP
MAX

OPA10l1102BM "
MIN,
MAX.
TVP"

,,

UNITS

INPUT NOISE
Voltage Noise Density

.'

fc; 111 Corner Frequency
Voltage Noise

Current Noise Density

Current Noise
DYNAMIC RESPONSE
Bandwidth, Unity Gain
OPA10l
OPA102
Gain-Bandwidth Product
OPA10l
OPA102
Full Power Bandwidth
OPlll0l
OPA102
Slew Rate
.OPA10l
OPA102
Settling Time (OPA10ll
.=1%
.=0.1%
.=0.01%
Settling Time (OPA1021
.=1%
.=0.1%
.=0.01%
Small-Signal Overshoot
OPA10l
OPAl 02

Rise Time

.

fo
fo=
fo=
fo =
fo =
fo =

lHz(11
10Hz
100Hz
1kHz
10kHz
100kHz

100
.32
14

9
7
6.5
125
1.3
1.0
2.1
2.0.
38
200

fe = O.IHz to 10HzPI
fe = 10Hz to 10kHz
fe = 10Hz to·lookHz
fo = O.IHz thru 10kHz
f8 = O.IHz to 10Hz
18 = 10Hz to 10kHz

200

80

60

25
11
8
7
6.5
100
1.0
0,8
2.1
1.4
26
140

30
15
8
8
2.6
1.2
2.6

100
30
15
12
8
8
1.3
1,0
2.6

nVIV~

nV/.,fHz
nV/y'RZ
nV/y'RZ
nVly'RZ

nV/y'RZ
Hz
p.V, p-p
p.V, rms
}lV,

rms

fAlvIHz
fA, p-p
IA,rms

Small Signal
10
Note 2

MHz

20
40

MHz
MHz

80
160

100
210

kHz
kHz

5
10

6.5
14

V/llsec
Vlp.sec

2
2.5
10

p.sec

ACL = 100

Vo = 20V, p-p; RL = lkll

Vo = ±10V; RL = lkll
ACL=-1
ACL =.-3
Vo = ±5V; ACL = -1;
RL = lkll

,usee
p.sec

Yo = ±5V; ACL = -3;
RL = lkll

RL = 1 kll; CL = 100pF
ACL =+1
ACL =+3
10% to 90%, Small Signal

1
1.5
8

IAsec

15

%
%

p.sec

,usee

20

nsec
nsec

40

OPA10l
OPA102
Phase Margin
OPA10l
OPA102
Overload Recovery(3)
OPA10l
OPA102

RL = lkll
ACL =+1
ACL =+3

60
45

Degrees

ACL = -1 , 50% overd,ive
ACL = -3, 50% overdrive

1
0.8

p.sec
p.sec

OPEN-LOOP GAIN DC
Full Load
No LQad

Vo - ±10V; RL -lkll
Vo = ±10V; RL;;: 10kll

94
96

105
108

dB
dB

±12
±12

±13
±30
500
±45

V
rnA
II
rnA

50Q
300

pF
pF

RATED OUTPUT.
Voltage
Current
Output Resistance
Short-Circuit Current
Capacitive Load Range
OPA10l
OPA102
INPUT OFFSET VOLTAGE
Initial Offset
vs Temperature
vs Supply Voltage
va Time
Adjustment Range

30

10-±12mA
Vo = ±12V
Open-Loop, f = DC

Phase Margin ~ 250
ACL = +1
~CL = +3

±loo

TA +25°C
-25°C,;; TA';; +85°C
±5VDC,;; I Ycc I ,;; ±20VDC

±6
±10
±10
±1

Circuit in "Connection

Degre~s

±500
±10
±50

±50
±3

±250
±5

p.V
p.V/oC

p.VN
p.Vlmo.
mV

Diagram"
INPUT BIAS CURRENT
Initial Bias
vs Temperat.ure
vs Supply Yoltage

TA - +25°C

-12
Note 4
Note 5

1-32

-15

,

-6

-10

pA

ELECTRICAL (CONT)
MODEL
PARAMETER

l

INPUT DIFFERENCE CURRENT
Initial Difference

CONDITION

I

OPA10lI102AM
TYP
MAX
MINI

J

±6

±3
Note 4
Noie5

TA = +25°C

vs Temperature
vs Supply Voltage

I

OPA10l/102BM
MIN
TVP
±1.5

MAX

UNITS

±4

pA

-c;=
C

Q,.

INPUT IMPEDANCE
Differential

Resistance

1012
1

II
pF

1013
3

II
pF

±< 1Vee 1-3<
105

V
dB

Capacitance

Common-mode
Resistance
Capacitance
INPUT VOLTAGE RANGE
Cammon-mode Voltage Range

Common-mode Rejection
POWER SUPPLY
Rated Voltage
Voltage Range
Current, Quiescent

Linear Operation
fo = DC, VeM =±10V

SO

Derated Performance

±5

±15
5.S

TEMPERATURE RANGE
Specification
Operating
Storage

Derated Performance

-25
-55
-65

NOTES: 'Specifications same as for OPA10l/102AM.
1. Param.eter is untested and is not guaranteed. This specification is
established to a 90% confidence level.
2. Minimum stable gain·for the OPA102 is 3VN.

±20
8

VDC
VDC
mA

+S5
+125
+150

°C
°C
°C

3. Time required for output to return from saturation to linear operation
following the removal of an input overdrive signal.
4. Doubles approximately every B.SoC.
5. See Typical Performance Curves.

MECHANICAL SPECIFICATIONS
DIM

"
C

D

E

ABSOLUTE MAXIMUM RATINGS
Supply
Internaf Power Dissipation(1)
Differential Input Voltage(2)
Input Voltage. Either Inputl')
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 10 seconds)
Output Short-Circuit Duration(3)
Junction Temperature

F

G

±20VDC
750mW
±20VDC
±20VDC
-65°C to +IS00C
-55°C to +12So C
+3000C

INCHES
MIN
MAX

.489
.243
.018
.010
.010

L

.200 B"SIC
.600
.110
.180

5.08 B"SIC
12.7
2.79 i 4.08

M
N

46' B"SIC
.095 L .105

46' B"SIC
2.41 I 2.87

K

--

60 seconds

Pin numbers shown for reference
only. Numbers may not be
marked on package.

1. Package must be derafed according to the details in the
Application Information section.
2. For supply voJtages less than ±20VDC, the absolute maximum
input is equal to the supply voltage.
3. Short-circuit may be to ground only. See discussion of Thermal
Model in the Application Information section.

!

!

C

~

4:

'U~ ~ ~~
.Jl D

Seating K

Pla ..e

~

I

,<)

T

<)1

4

~L

-

N

Weight: 2 grams

Pin material and plating composition
conform to method 2003
,solderability' of MIL-STD-S83
I except paragraph 3.2"

Order Number:
OPA101AM OPA101BM
OPA102AM OPA102ElM

CONNECTION DIAGRAM
PIN CONFIGURATION

POSITIVE SUPPLY
I+Veel

OUTPUT

OUTPUT
I Vour I

+VIN

INVERTING
INPUT
I-V,N'

·Optional to improve
resolution and limit range.

NON INVERTING
INPUT (+V,N'

NOTE: Offset voltage adjustment affects voltage drift vs temperature
by approximately ±0.3~VI"C for each l00~V of offset adjusted.

NEGATIVE SUPPLY I-Veel

1-33

1

~>'
~ ~ o. + 0, S
~
I

Leads in true position within .010"
•
1.25mm I R at MMC at seating plane.

NOTES:

0Wfi-'

L

--

NOTE:

+17So C

rAi

MILLIMETERS
MIN
MAX

.522 12.42 3.28
.307 8.17 .7.80
0.63
0.41
.021
1.02
.040
0.26
1.02
0.25
.040

TYPICAL PERFORMANCE CURVES
ITA =+25°C, ±VpC = ±f,sVDC, unless otherwise noted: Performimce curves apply' to both OPAl 01 and OPA102 unless otherwise noted.)
INPUT NOISE VOLTAGE
TOT,A.LINPUT NOISE VOLTAGE
RMS INPUT NOISE VOLTAGE
VS FREQUENGY .
1000
VS FREQUENCY
1000
VS SOURCE RESISTANCE .

1000

..

,

~~

.
I>
c

100

.~

9!

10 rBM

Z

7'

SQ.

VIIIIIIII

"'

.5

.

10k
lOOk 1M
10
100
lk
. frequency I Hz)
PEAK-TO-PEAK INPUT NOISE VOLTAGE
VS SOURCE RESISTANCE

1

1000

.'"

~

10. 100
lk
10k
Frequency (Hz!.
INPUT NOISE CURRENT
VS FREQUENCY

100

.~

Is=O.1 1010Hz

10

1
103 . 104

I

109

....

§ +50

f

.,

0.1

I l

Time IJ.'S8Cl

\.'

\.

40

10

-J.

o

OP~'02

,." "


§+50

,

~

I~

100

1M

+100

~ -

10

lOOk

,,~

.\..

40

10k

LARGE SIGNAL TRANSIENT RESPQNSE

+45

Rl= lkn

~

Ik

Frequency (Hz)

\.

0

"'"

'I

,08

opl,o,

20

c

100

opl,o,',

IAI

'0;

~

0.1

105
106
107
108
Source Resistance {O 1

100

E

Is'= 10Hz 10. 10kHz

2O.1-~1-~-~---!---!"''''''

OPEN-LOOP FREQUENCY RESPONSE

~

f

80

I

f

'rJI""'"

120

.'"

J.

~"

.5

'0;

f

c

J

~

!!

~c

,"

~ 100 ~~"hod----+--If--+--~

II

100

(;

SQ.

lOOk

I

contribution_ .,-r--- I-:Inc!udes
from sou ret! resistance

>
Z

-

/

I

~ II"'"
103 104 Irf>
107
loll 109
Source ReSistance (II)
COMMON-MODE REJECTION
120 r-_T'""_V:.rS::,.F:.:R.::E,O..,U",E",N:.;Cr:-Y--:--r'_'
I

0.1

~

j

f

>

10

1

>

!!

Z·~

;I

~

I

BM

1

Is = 10Hz 10 100kHz

ig

Rs = loon

~

source resistanCEl
;I

~,OO

.~

'0

~ftom

>

~s~ \ookn

~

t-- ~ In~ludesl conlri~ulion

~

Rs-tMlI-

M

...

.

Rs=10Mn

""'III~

I'

lk 10k lOOk 1M
Frequency (Hz)

10M

-

-

,....-

Rl=lkll
Cl= loopF
Acl. =j3VIV

o

10
Time 1",sec I

1-34

IS·

-

20

25

>.
S

0

~-50
o

,.

Rl = Ikll
Cl = loopF

-100

"""

(Cl=rVIV

o

0.1

0.2

0.3

Time, (psec)

0.4

0.5

FREQUENCY CHARACTERISTICS
VS SUPPLY VOLTAGE

FREQUENCY CHARACTERISTICS
VS AMBIENT TEMPERATURE

1.3,..--r--r--,--,--,----,

1.3

OPA10l
1.21--+--+---+---+---!--____I

1.2

1.11---+--+--+-+--+-""

!l
~
~

1.0

:;;
~

kle';'R~~

I~

1.0

." ~

0.9
0.8

~5--'-'---1-f:0~--'--;1';-5-"""'-~20

0.7

0.7

OP~101'

1.1

0.8 ....~1--l----1--+--+--t

,/

-35

-15

FREQUENCY CHARACTERISTICS
VS SUPPLY VOLTAGE

1.4

~

" 1.1

1.0 Bandwidth

:;
Qj

0::

~

0.8

~

:;

~I""

~

+45

+65

o

+85

r;.... ~

-35

-15

+5

15

lk

op1102

~ I"""""""

Bandwid~

+25

+45

TemperatUN

+65. +85

1

=

--

~

~

~

10
100
Closed-Loop Gain IV/VI

(OC)

QUIESCENT SUPPLY CURRENT
VSSUPPLYVOLTAGE

110

lL

10
100
Closed-Loop Gain IV/VI
OVERLOAD RECOVERY TIME
VS CLOSED-LOOP GAIN

I

'0

O. 7

10
15
20
5
Supply Voltage. (±Vee)
COMMON-MODE REJECTION
VS COMMON-MODE INPUT VOLTAGE

~

.", ~

0.8

VS=I±15V

iii

-'

0:: 0.9

0.4

120

1.0

a;

I-- I-""'s;ew Rar

0.6

c

a..
c

(~C)

Slew~

~"

I,.-

-

c;

OP~W2

1.2

1.2

""
>

,.,..

FREQUENCY CHARACTERISTICS
VS AMBIENT TEMPERATURE

1.3

OPA102

0;

+25

Temperature

OP2101

Bandwidth

7

+5

Supply Voltage (±Vee)

1.6

OVERLOAD RECOVERY TIME
VS CLOSED-LOOP GAIN

15

lk

9~~--~~-.~~~r-~

VOLTAGE GAIN VS SUPPLY VOLTAGE
120,..--r'--,--,--,--,----,

~81---1----+--1--+-+--t

RL = lkfl
1151_-+_-_r-____I--r--+_--i

c:

o

~

~-+--+-_+--1---+_~~~1101_-+_-_r-____I--~-~~~

100

c:

l
-g"
~

§

'0;

I---l--::::!~~~~_..,..=:::;j Cl

90

60

E

8

0

951_-+--+---+---+---!---;

0

150

:;

""'"
S"

g

j
0

o

35L-~--~1~0--~--~1~5--~--~20

5
10
15
Common-mode Input Voltage I±V)

STABILIZATION liME OF INPUT OFFSET
VOLTAGE FROM POWER TURN-ON

S"
g'" 300

100
75
50

.,"'"c:

25

AM

"" 375

AM

'5
Q.
.5
E

Supply Voltage I±VI

THERMAL RESPONSE TIME OF INPUT OFFSET
OUTPUT VOLTAGE VS OUTPUT CURRENT
VOLTAGE FROM HEAT APPLICATION
400
30

:;

125

J'r

f/

,,I

il

5225

f

'5
Q.
.5 150
.5

BM

~

90'~5--~--~'1~0--~----1~5--~--~20

Supply Voltage I±Vecl

"'"c:
"

TA =

~5°C tolTA = 8~OC

'".,

1l.

-

Air Enviror:ment

,,: 20

-

Vee = ±20VDC

.s"'"

-

Vec~I±15VDC

'0

BM

15

>
'5
Q. 10 --:-- Vee ~1±10v6c

~

75

25

8

-

.c:
()

.c:
()

0
0

6

10

Time From Power Turn-on (min)

0
12

4

0

Time From Heat Application (mini

1-35

6

o

o

vee~I±5VDb

I
10

20

J

30.

40

Output Current (rnA 1

50

60

POWER SUPPLY'REJECTION
VS FREQUENCY

.......

120

Di

lOO

~

c:

0

~
'G)

80

OptOl

"~

"",

0.

Co

"

40

0

20

11.

,

~~

o

10

100

lk

10k

Frequen~y

lOOk
I Hz}

1M

30
OPl,Ol

50

"

"" ~

!1:-

;

OUTPUT VOLTAGE VB FREQUENCY

80

a: 80
Ul

SETTLING T'IME
VS CLbsEIHOOP GAIN

0

....

0

POWER SUPPLY REJECTION
VS FREQUENCY

RL

~I,

.1.

5 r - Vee -1+5VD
0
10

lk

I
100

I

RL

"

0
10

1'<1

10k lOOk
lk
Frequency 1Hz,

.~

1M

10M

INPUT BIAS CURRENT VS TEMPERATURE AND
INPUT OFFSET CURRENT VS TEMPERATURE

1060

O,~
5
0

-~
1'111
100

INPUT BIAS CURRENT VS INPUT VOLTAGE
AND INPUT OFFSET CURRENT
VS INPUT VOLTAGE

~

,/

1
1
I

0,00 1
-35

~

V-

-15

l/

~
0

/

+5
+25
Temperatute

,

+4~

+65

+85

-5

f--

Vce-+15VDC

I--

vee=~lOvDb

10

J

Vee

100

I

~~5VDd

I

,..
",~

11,

lOOk
lk
10k
Frequency 1Hz I

M

INPUT BIAS CURRENT VS SUPPLY VOLTAGE
4,0

c;.." 2,51-'----+---+-1----1
'[ 2,0 Without Heat Sink _

,",

E 1,51----+---:;,.+--::;.,,~-1

o

+5

Input Voltage I V I

1-36

+:WVDC

Vee

iii

"'-10

'kO

I

3,5\----I1c-----+--I---l

6
0,4

10M

c~ 3 , 0 1 - - - - + - - - + - . r - - - - j

8

(OCI

0

1M

J

f--

51--

lk

CI~-Lciop Gain ,V/V,

1,6

0

~

"~L.,

lk
10k lOOk
Frequency I Hz,

OPA102

. .J.

d

ta

OUTPUT VOLTAGE
VS FREQUENCY

30

OPA102

0

I

Ot-- Vee = ±10VDC

SETTLING TIME
VS CLOSED-LOOP GAIN

0

=' lkO

5~ Vee =1±15VD6

O':.i ~,

~
1'111
10
100
Closed-Loop Gain IV/V,

10M

I

t - - Ve.e = ±2OVDC

J
h

0

OPA10l

5

LOI----t-:.,'--:__~---t

j

20

+10
Supply Voltage, ±Vee'

APPLICATION INFORMATION
INTRODUCTION
The availability of detailed noise spectral density characteristics for the OPAIOI 1102 amplifiers allows an
accurate noise error analysis in a variety of different
. circuit configurations. The fact that the spectral characteristics are guaranteed maximums allows absolute
noise errors to be truly bounded. Other FET amplifiers
normally use simpler specifications of rms noise in a
given bandwidth (typically 10Hz to 10kHz) and peak-topeak noise (typically specified in the band 0.1 Hz to
10Hz). These specifications do not contain enough
information to allow accurate analysis of noise behavior
in any but the simplest of circuit configurations.

N,m. ~ I IT
n2(t) dt
(I)
where N,m, is the rmsvalue of some random variable net). C I
In the case of amplifier noise. net) represents either en(t) c
a..
or in(t).

v'

,rot

--

CI

The internal noise sources in operational amplifiers are
normally uncorrelated. That is. they are randomly related
to each other in time and there is no systematic phase
relationship. Uncorrelated noise quantities are combined
as root-sum-squares. Thus. if n,(t). n,(t). and n;(t) are
uncorrelated then their combined value is

'NTOTALrm~ = JNI2rms + N22rms + N3 2rms

(2)

The basic approach in noise error calculations then is to
identify the noise sources. segment them into conveniently
handled groups (in terms of the shape of their noise
spectral densities). compute the rms value of each group.
and then combine them by root-sum-squares to get the
total noise.

+

TYPICAL APPLICATION
The circuit in Figure 3 is a common application of a low
noise FET amplifier. It will be used to demonstrate the
above noise calculation method.

FIGURE I. Noise Model ofOPAlOl1 102.
Noise in the OPAIOII 102 can be modeled as shown in
Figure I. This model is the same form as the DC model
for offset voltage (Eos) and bias currents (18). I n fact. if
the voltage en(t) and currents in(1) are thought of as
general instantaneous error sources. then they could
represent either noise or DC offsets. The error equations
for the general instantaneous model are shown in Figure
2 below.

FIGURE 3. Pin Photo Diode Application.
CR I is a PIN photo diode connected in the photovoltaic
model no bias voltage) which produces an output current
i;n when exposed to the light. A.
A more complete circuit is shown in Figure 4. The values
shown for C, and R, are typical for small geometry PIN
diodes with sensitivities in the range of 0.5 A, W. The
value of C, is what would be expected from stray
capacitance with moderately careful layout (O.SpF to
2pF). A larger value of C, would normally be used to
limit the bandwidth and reduce the voltage noise at
higher frequencies.

HZ

,",UlvelBnt circuit for CHI

Cz= IpF

.

--

,-------------------~

FIGURE 2. Circuit With Error Sources.

I

In

If the instantaneous terms represent DC errors (i.e ..
offset voltage and bias currents) the equation is a useful
tool to compute actual errors. It is not. however. useful in
the same direct way to compute noise errors. The basic
problem is that noise cannot be predicted as a function of
time. It is a random variable and must be described in
probabilistic terms. It is normally described by some type
of average - most commonly the rms value.

-----------------I

Note: In+ shorted In this conflgurallon.

FIGURE 4. Noise Model of Photo Diode Applic.ation.

1-37

In Figure 4, eo and io represent ihe amplifier's voltage and
current spectral densities, eo(w) and io(w) respectively.
These are shown in Figure 5.

-

i'"

&a. VOlTAGE NOI.E

0.1

'I

10

100

la=673~

10

\

1+ RzlRI

"

I~

Ik

I~

A~

\

'

,,: 7'1

#

0.0010.01 0.1

,.,.'I

--Ii

,IT .9~HZ,~ ~
11,+ CI/C21 = 28

I

K3 = 1.113 x 10-3 =

10

'~

I~

I

,#

0.01

13=3DHz
~

•

,

,

,

~.

0.1

il*~1'1~1Iff II

I

l'

11/l

I

Frequllley(llzl

,

I

~IOO

'e = 100Hz
~~O~I~~~--~--~~I~k~~I~~~I~~~IM~I=OM

0.01

J.Alw!~

10PAIOII

Ik

I~-I-';t"~!iiiii~iiiiit;;iiiiiiii~iiiliiiii

'

"

I~

~~ loo~~~~--+-~-+~~+-1
10

..

I~

lDOOr---r-~--'---r--r--'---r-~--'

I

,

'

I

~~+~
la
RI

100

Ik I~
Frequency IHzI

I~

1M

10M

FIGURE 7. Noise Voltage Gain.

1M 10M

FnqUincy IHzI

511. CURRENT NOISE

FIGURE S.NoiseVoltage and Curren:t

Sp~ctral

Note that for large loo'p gain (A[3»I)

Density.

Figure 6 shows the desired "gain" of the circuit(tranSimpedance of e,,/ Lo = Z,(s)). It has a single-pole
rolloff at f2 = 1/(211'R,C2) = w2/211'. Output noise is
minimized if f2 is made smaller. N o'rmally R2 is chosen for
the desired DC trans impedance based on the full scale
input current (i;o full scale) and maximum output (eo
max). Then C2 is chosen to make f2 as small as possible
consistent with the necessary signal frequency response.

(4)

F or the circuit in Figure 4 it can be shown that
(5)

This may be rearranged to

loll

~

i
E

!

(Sa)

10·
107

"

12=/
IUk

loB
1050.01

0.1

I

10
100 Ik
Frequency IHzI

10k

[3

,
I~'

(5b)

1M 10M

T, = R,C,

FIGURE6. Transimpedance.

and

Voltage NoIse
Figure 7 shows the noise voltage gai\1 for the circuit iii
Figure 4. It is derived from the equation

Then. t; = 211'T" and f" = 211'T,

eo=eo[ - A
- , ]=eo - r
I + AS
[3,

[ -I -]
I + 1-

I

(5c)

I
-(5d)

For very low frequencies (f«L). s approaches zero and
equation 5 becomes

(3)

(6)

A[3
[3

where:
A == A(w) is the open-loop gain
[3 = [3(w) is the feedback factor. It is the amount of
output voltage feedback to the input of the op amp.
A[3 = A(w) [3(w) is the loop gain. It is the amount of the
output voltage feedback to the input and then
amplified and returned to the output.

For very high frequencies
and equation 5 becomes

(f»t~).

s approa~hes infinity
(7)

1':'38

The noise voltage spectral density at the output is
obtained by mUltiplying the amplifier's noise voltage
spectral density (F;igure Sa) ,times the circuits noise gain
(Figure 7). Since both curves are plotted on log-log scales
the multiplication can be performed by the addition of
the two curves. The result is shown in Figure 8.

I

.L

If. ~ ~
'c = l00Hz'{ J.o

'1 =O.OlHz

I'

,,

I

Lffi

~nB

I'N'
S

j

a

::-

lO~

,

I

I

I

K211 + C, fC2)
rI
I
-

1000

..
~ .....
==. 100

:l:

-.1211 l(31

~".~

R2
KIll + R I

I
I

,

En] rms

I

,

:

\.1

This is the region of increasing noise gain (slope of
+20dB/ decade on the log-log plot) caused by the lead
network formed by the resistance R,II R, and the capacitance(C, + C,). Note that K,. K, is the value oftheeo (w)
function for this segment projected back to I Hz.

--- 208

~

-8.8

•

1M

~

Region 4; f> 15.9kHz

= SnV/

R~

) y'ln(L; f,)

= 80nV/vHZ (I +

~) lin
108

(9)

where Z,(s) = R" II Xc,
100
0.01

( 13a)

This voltage may be obtained by combining the information from figures 5 (b) and 6 together with the open
loop gain curve of Figure 7. The result is shown in Figure'
9 below.

(9a)

m
'>

I
1(r7

~

I

10.8

~80krzrl ,

'3 =
I

10

f"7<"

10'
= 8nV/v'HZ( I + 108 ) y' 673 - 100

(lOa)

,I

J

'2 =15.9kHz-

2.2-1/1

_1.4-

0.1

(10)

®.. I®

CD

Raglon

10.g

) v f,-fc

R~

(12a)

Current Noise

Region 2; f, = 100Hz to f, = 673Hz
R,

VHz (I + 2?) j[i] 380k - IS.9k

The OUtput voltage component due to current noise is
equal to:
( 13)
E" = io x Z,(s)

This region has the characteristic of 1/ f or "pink" noise
'(slope of -IOdB per decade on the log-log plot of eo(w».
The selection of 0.01 Hz is somewhat arbitrary but It can
be shown that for this example there would be only
negligible additional contribution by extending 1', several
decades lower. Note that K,(I + R, R,) is the value of eo
at f= I Hz.

Eo, ,m, = K, (I +

(12)

This is a region of white noise with a single order rolloff at
f, = 380kHz caused by tfie intersection of the 1/ f3 curye
and the open-loop gain curve. The value of 3S0kHz is
obtained from observing the intersection point of Figure
7. The 1T /2 applied to f, is to convert froma 3d B corner
frequency to an effective noise bandwidth.

It is both convenient and informative to calculate the rms
noise using a piecewise approach (region-by-region) for
each of the four regions indicated in Figure 8.
Region I; f, = 0.01 Hz to L = 100Hz

R,

J 1T
+ c,
C,) [2"]f,- f,

E04 'm, = K, (I

10M

(8)

+

, j(IS.9k)' (673)'
8nV/VHZ(I.63 x 10')
-l---]-(lla)

=

FIGURE S. Output Noise Voltage Spectral Density.
The total rms noise at the amplifier's output due to the
amplifier's internal voltage noise is derived from the e.,(w)
function in Figure 8 with the following e)(pression:

K, (I

(II)

!

i.-

,m, =

j --=-f,' _.['.:. .
3
3

K]

,,

Z )," • •
K2 11 +R0.1
_I
Rl •
0.01 0.013 -~K3· K2
0.01 0.1
I
10 100 lk 10k lOOk
F.....u.ncy IHzl

Eo,

= K2·

4 I

I

I
I

I

I~I

Region 3; f. = 673Hz to f, = IS.9kHz

f '2 =15.11kHz
.1.
I '3 = _Hz

!V
Til!'-

88

This is a region of "white" noise which leads to the form
of equation (10).

100

lk
10k
Froquency 1Hz)

\

lOOk 1M

FIGURE 9. Output Voltage Due to Noise Current.
Using the same techniques that were used for the voltage
noise:

= O. 21 /lV

Region I;O.IHzto 10kHz

1-39

is
<
a..

=

(14)

Examination of the results in equation (l6b) together
with the curves in Figure 8 leails to some interesting
conclusions. In this example·84% of the noise comes from
En4. From Figure 8 it is seen that this is the area beyonil
the pole formeil by R2 anil C2.
The En4 contribution eoulil be reduceil several ways. The
most common methoil is to increase C2. This reiluces f2
and the value of K2(l + CI/C2) (see Figure 8). It also
reduces the signal banilwiilth (see Figure 6) anil the final
value of C2 is normally a compromise between noise gain
and necessary signal banilwidth.
.

Region 2; 10kHz to 15.9kHz
-12

En;2 = 1.4 x 10

J

(l5.9k)' (10k)'
--3- - -3-

(l4a)

= (.4/LV

Region 3; f> 15.9kHz
EnB = 2.2

X

10-8

J;

380k - 15.9k

(l4b)

It should be noted that increasing C2 will also affect L
since fa is iletermineil by (C, + C2) (see equation (5b».
Normally C2 is larger than C, anil f2 will.change more
than f. for a given change in C, .
The other means of reducing the noise in region 4
involves changing amplifier parameters. For example,
the use of a slower amplifier would m~ve the open-loop
gain curve to the left anil decreasef,. Of course, reducing
the value of K2,the noise floor, would also reduce the
noise in this region.
The second largest component is the resistor noise EnR
(14% of the total noise). A lower resistor value decreases
resistor noise as a function of v'R:' but it also lowers the
desired signal gain as a direct function of R. Thus,
lowering R reduces the signal-to-noise ratio at the output
which shows that the feedback resistor should be as large
as possible. The noise contribution due to R, can be
decreased by raising the value of C, (lowering f,) but this
reduces signal bandwidth.
It is interesting to note that the current noise of the
amplifier accounted for only I rye of the total En. This is
different than would be expected when comparing the
current and voltage spectral densities with the size of the
feedback resistor. For example, if we define a characteristic value of resistance as
en(W)
.
R'characteristic= in(w) at f= 10kHz
(17)

= 16.8JLV
. En; tolo' = 10-6..J (1.4)2 + (1.4)2 + (16.8)2

(14c)

= 16.9/lV,m,
Resistor Noise

For a complete noise analysis of the circuit in Figure 4,
the noise of the feedback resistor, K2, niust also be
included. The thermal noise of the resistor is giVen by:
ER rm' =
4kTRB
(15)
K = Boltzmann's constant = 1.38 x IO- H
. Joules/"Kelvin
T = Absolute temperature (degrees Kelvin)
R= Resista!lce (ohms)
B = Effective noise bandwidth (Hz) (ideal filter
assumeil)

..J

At 25°C this becomes
ER rms 9! 0.13
ER rms in /LV
RinMO
B in Hz

VRB

For the circuit in Figure 4
R2 = lO'n = iOMO
1T

8nV/v'ifl
1.4fA/ v'1Iz

1T

B=2(f2)=2" 15.9k
Then .
ER rms = (411nV l\/ii7.)
= (4I1nV/v'1i'1)

Conclusions

5.7MO

vB

Thus, in simple transimpedance circuits with feedback
resistors greater than the characteristic value, the
amplifier's current noise would cause more output noise
than the amplifier's voltage noise. Based on this and .the
10Mfl feedback resistor in the example. the amplifier
noise current would be expected to have a higher
contribution than the noise voltage. The reason it does
not in the example of Figure4 is that the noise voltage has
high gain at higher frequencies (Figure 7) and the noise
current does not (Figure 6).
The fourth largest component of tota.! noise comes from
En.' (0.80/,). Decreasing C, will also lower the term K,( 1+
C,.C,). In this case. f, will stay fixed and (, will move to
the right (i.e .. the+20dB/ decade slope segment will move

j T15.9kHz

= 64.9/lV rms
Total Noise

The total noise may now be computeil from
Ent""" = JEn" + En2' + En/ + En4' + EnR2 + En;'

(16)

=J2.67' +0.21' + 15.1' + 158.5' + 64.9' + 16.9'

(16a)

·=..)7.1 +0.04+228+25122+4212+286

(16b)

= I 73/lV rms

140

to the right). This can have a significant reduction on
noise without lowering the signal bandwidth. This points
out the importance of maintaining low capacitance at the
amplifier's input in low noise applications.

used in planning the board layout. A "guard" pattern
should Completely surround the two amplifier input leads
and should be connected to a low impedance point which
is at the signal input potential (see Figure 10). The
amplifier case. pin 8. should also be connected to the
guard. This insures that the entire amplifier circuitry is
fuJly surrounded by the guard potential. This minimizes
the voltage placed across any leakage paths and thus
reduces leakage currents. In addition. noise pickup is also
reduced.
Figures II. 12. and 13 show typkal applications using the
guard and case shielding.
Cleanliness is also a prime concern in low bias current
circuits. It is recommended that after instaJlation is
complete the assembly be washed with a low residue
solvent such as TMC Freon foJlowed by rinsing with
deionized water. The use of some form of high dielectric
conformal coating such as a good two-part urathane
should be considered if the assembly wiJl be used in air
environment which could deposit contaminants on the
low current circuitry.

Shielding and Guarding
The low noise. low bias current and high input impedance
of the OPAIOI/I02 are weJl suited to a number of
precision applications. I n order to fuJly benefit from the
outstanding specifications of this unit. careful layout.
shielding. and guarding are required. Careless signal
wiring or printed circuit board layout can easily degrade
circuit performance several orders of magnitude below
the capability of the OPA 10 1/102.
As in any situation where high impedances are involved.
careful shielding is required to reduce "hum" pickup in
input leads. If large feedback resIstors are used. they
should also be shielded along with the external input
circuitry. The metal Case of the OPA 101 /102 is connected
to pin 8 and is not connected to any internal amplifier
circuitry. Thus it is possible to use the case as a shield to
reduce noise pickup.
Unless care is used. leakage currents across printed circuit
boards can easily exceed the bias current of the OPAIO I /
102. To avoid leakage problems. it is recommended thata
Teflon IC socket be used or that at least the signal input
lead ofthe amplifier be wired to a Teflon standoff. If this
is not done and instead theOPAIOI /102 is to be soldered
directly into a printed circuit board. utmost care must be

R2

OUTPUT

FIGURE 12. Ultra-High Input Impedance Noninverting
Circuit.

(BOTTOM VIEW!

Board layoullor Input Guarding with TO.a9 Pickage.

FIGURE 10. Connection of Case Guard and Input Guard.
C2 =30pF

Shield

FIGURE 13. Low Drift Integrator.

+

Thermal Model
Figure 14 is the thermal model fortheOPAlO1 /102 where:
TJ = Junction temper'iture (output load)
T,* = Junction temperature (no load)
Te = Case temperature
TA = Ambient temperature
iJ eA = Thermal resistance. case-to-ambient

VOUT = .lln x z2

FIGURE II. Ultra-Low Current to Voltage Converter.

1-41

0lf'S.~'yf~cti~e thermal re~istance ofthe),e~t ~ini{
PPQ=Qui~~cenfp()wer di~~ipation'

"

Tj =

'

~' l+Vc~1 I+QU'I,ES<;E~T+I~Vccl LQUIESCENT
PD'I= ,PQwe; 9issipatio~ in the output transisWf..

Of" + PDQ [0,+ (O~s II. Oe~)J" '
+ P IlX [01 +'0, + (OHS /I

OeA)]

{19)

=,(VOUT' VCC)lOUT

(In a ,'complementary output stage only one output
transistor is conducting current at a time.)

Substituting appropriate values yields
T j = 25'; + dov x SmA)[85°QjW + 90°CjW]

INTERNAL POWER DISSIPATION

( 15V)'

+ --

, T/

= 25"C

[75"CjW

,4 x IkO,

'

+ 42"C + 14°C

= TA

+ S5"C;W + 90°C;W]
+ 56"C

,Pox,
= SloC

FIGURE 14. OPAIOIII02 Thermal Model
This'model is obviously not the ~imple one-powe~ s~urce
model used with most linear integrlj.,ted' circuits. It is.
however. a more accurate model for multichip hybrid
integraieil circuits where the quiescent poweris dissfpaieci
in the input stage and the internal power dissipation due
to the load is dissipated in a somewhat physically
separated output stage.
'
The model inFigure 14 must be used in 'conjunction with
the OPAWlj 102's absolute maximum ratings of internal
power'dissipation arid junction temperature to determine
the derated I'?wer dissipation cap'ability ~i thep~ckage:
As an example of how to use this model. consider this
problem: Determine the output transistor junction tem~
perature when the output has its maximum load resistance
and is operated at the worst-case output voltage conditions. Assume Vee = ±15VDC and T" = 25','C.
Maximllm PDx occurs where VOl'T = 1/2Vec.Then

(Ved
PI>X max

=

4Rload

(IS)

The conclusion is that under a worst-case output voltage
condition and,with a I kO I()ad the junction temperature
rise is 56"C above ambient. Thus. under these conditions.
the device could be operated in an ambie,nt up to 119"C
without exceeding the 175"C junction temperature rating.
A similar analysis for conditions, of the output shortcircuited to ground where
(20)
PDX SS =;,: Vee I(OUIPUI limit)
shows that the maximum junction temperature rating of
l75"C ,is exceeded. Thus. the, output should not be
shorted ,to ground for sustained periods of time.

HEAT SINK
The heat sink used on the OPAIO'I/I02 should not be
removed. It has the effect of reducing the package
thermal resistance from 150"C / W to aboUt 90"C per watt.
Removing the heat sink would naturally increase the
junction temperature of the amplifier which would in
. turn raise the input ,bias current. The change in thermal
resistance also affects the noise performance. Removing
the heat sink would increase the noise in the I f region.

1-42

BURR-BROWN®

OPA103

IElElI

Low Drift - Low Bias Current' FET Input
OPERATIONAL AMPLIFIER
FEATURES

APPLICATIONS
• CURRENT TO VOLTAGE CONVERSION

• LOW BIAS CURRENT. 1pA. max

• LONG TERM PRECISION INTEGRATION

• HIGH INPUT IMPEDANCE. 1015 n

• PRECISION VOLTAGE AMPLIFICATION FOR
HIGH INPUT IMPEDANCE APPLICATIONS SUCH' AS:

• ULTRA-LOW DRIFT. 2I-'V/oC. max

• photo current detectors
• pH electrodes
• biological probes/transducers

• LOW OFFSET VOLTAGE. O.25mV. max
• LOW QUIESCENT CURRENT. 1.5mA. max
• HERMETICALLY SEALED TO-99 PACKAGE

DESCRIPTION
The OPAI03 is a precision low bias current operational amplifier. Guaranteed low initial offset voltage
(0.25mV, max) and associated drift versus temperature (21-' Vf"c. max) is achieved by laser-adjusting the
amplifier during manufacturing. This feature, and
guaranteed low bias current (I pA, max), allow
greater system accuracy with no external components.
Quiescent current (1.5mA, max) is unaffected by
changes in ambient temperature or power supply
voltage. Other characteristics of the OPA 103 include
internal compensation for unity-gain stability and

rapid thermal response for quick stabilization after
turn-on or temperature changes.
The amplifier is free from latch-up and isprotected
for continuous output shorts to common. As an
added protection feature, either of the trim pins can
be accidentally shorted to a potential greater than the
negative &upply voltage without damage.
The standard pin configuration (741 type) of the
OPA 103 allows the user drop-in replacement capability. A pin 8 case connection permits the reduction of
noise and leakage by employing guarding techniques.

OFFSET

TRIM

International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734 • Tel. (6021 746·1111 . Twx: 910-952·1111 . Cable: BBRCORP· Telex: 66·6491

1-43

··SPECIFICATIONS
ELECTRICAL

-

-

AlTA = +25"Cand +Vcc = +15VDC unless otherwise rioted

I
I

MODa
OPEN-LOOP GAIN, DC, V OUT + ±10V
Rated Load, RL ;;. 2kO
RL;;'lOkO
TA = -25°C to +85°C, RL;;' 2kO

I OPA103BM I OPA103CM I OPA103DM
I
I MAX I MIN I TVP I MAX I MIN I TVP I MAX I MIN TVP MAX

TVP

100

106
112
100

94

· ··

·
···

RATED OUTPUT
. ±10
±12
±5

Voltage at RL ='2kO, TA = -25°C to +85°C
RL = 10kO, TA = -25?C to +85°C
Current. TA = -25°C to +85°C; Vo =±1OV
. Output Impedance

±t2
±13
±10

3

load Capacitance(1)
FREQUENCY RESPONSE
Unity Gain. Small Signal
Full Power Response
Slew Rate
Settling Time 10.1%1
Settling Time 10.01%1
Overload Recovery(2). 50% overdrive

14
0.9

1
20
1.3
9

20
4

··.
···
··

· ·

15

INPUT OFFSET VOLTAGE
Initial Offset, TA = +25°C
vs .Temperature. TA = -25°C to +85°C

±200
±15

"±20

vs Supply Voltage"T:A =-'5°C to +85°C

·
·
···
··
··

·
···
·

··
··

500. 1000
25 .
10

Short Circuit Current

.

OPA103AM
MIN

±500
±25
±200

±200
±10

··
·
···
···
····
·· ·
±100
±3

±500
±15

·
·
···
··

··

±250
±5

·
··
···
··.
···
·
·· ·
±100
±1

UNITS
dB
dB
dB
V
V
mA
kO
pF
mA
MHz
kHz
VI,.sec
~s.ec
~sec

Iotsec

±250
±2

,.V
,.VI"C
,.VlV

-1

pA
pA

INPUT BIAS CURRENTI3i

Initial elias, TA

= +25°'C

-1

vs Supply Voltage

-1

0.005

INPUT DIFFERENCE CURRENT
Initial Differerice. t A = +25°C

1 ±9.31

1

INPUT IMPEDANCE
Differential
Common-mode
INPUT NOISE

1

··
···

101311~.~

1015111.

Voltage. fo - 10Hz
fo = 100Hz
fo = 1kHz
fo = 10kHz
f8 = O'lHz to 10Hz
Current. f8 = O.lHz to 10Hz
f8 = 10Hz to 10kHz
fo = 1kHz

55
35
30
25
3.0.
0,01
0.003
0.6

··
···

'NPUT VOLTAGE RANGE

Differential
Common-mode. TA = -25°C to +85°C
Common-mode Rejection, VIN := ±10V
Maximum Safe Input Voltage

1 +0.21

±20
±10

76

±12

86
±VCC

POWER SUPPLY

±15

Rated Voltage
Voltage Range. derat~d P!9rformance.
Current quiescent TA = -25°C to +85°C

±5

TEMPERATURE RANGE amblen'
Specification
Oper8:tin g
Storage
8 junction - ambient

-25
-55
-65

1.0

±20
1.5

··· ··
·
· ·· ··

+85
+125
+150

1

±c.21

··
··
···
···

1

1 ±c.21

··
··
··

··
··

··· ··
·
· ·• ·· · ·· ··

·· ·
· ··

pA

°

II pF
011 DF

nVlJ,Hz
nVlJHZ
nVlJHZ

nV/JHZ
,.V'p-p
pA ,pop'
pA. rms

fAlyHi
V
V
dB
V
VDC
VDC
rnA
°C
°C
°C
·C/w

235

tSpecifications same as for OPA103AM.
NOTES:
1. Stability guaranteed with load capacitance:5 500pF.
2. Overload recovery is defined as the time required for the output to return from saturation to linear operation following the removal of a 500/0 input
overdrive si9f'al.
3. Bias current is tested .and guaranteed after 5 minutes of oper~tion at TA = :+-25°C. For higher temperature the bias current doubles every +10°C.

1-44

,

CONNECTION DIAGRAM

MECHANICAL
INCHES

MAX

MILLIMETERS
MIN
MAX

.335
.305

.370

8.51

.336

7.75

,165

.186

4.70

.016

.021

4.19
0.41

.010

.04'
.040

0.25
0.25

1.02

MIN
A

o

.010

-

CC

=
Q,;,

0.53
1.02

5.08 BASIC

.200 BASIC

G

a

9.40
8.51

0.86

.028

.034

0.71

.029

.046

0.74

1.14

12.7

.500
.160

.110
M

45 0 BASIC

N

.095

4.05

2.79

45 0 BASIC

2.67

2.41

.105

Weight: 1 gram

(TOP VIEW)
Pin material and plating composition
conform to Method 2003 I solderability \

Pin numbers shown for reference only.
Numbers may not be marked on package. of MIL-STO·883 I except paragraph 3.21.

TYPICAL PERFORMANCE CURVES
OPEN-LOOP FREQUENCY
RESPONSE

120
~100

~

;:80 1- ~

. r\.

.ij
(!l

60

:

40

g

20

o

1

~ ~
ill

+45

"-

o '"
2:

"-

-45 :::

I

"-

"

c: 11

.ij

110

105

-135m >

100

8.

"0

180

95

10 100 lk 10k lOOk 1M 10M·

Frequency I Hz I

VOLTAGE FOLLOWER
LARGE SIGNAL RESPONSE
RL - 2k!l
~

'"'"
~
0

>

:;
~

10
5
0
-5

I
I
I

"

\

\
\

0-10

~

+10

i

+5

~
>

0

COMMON-MODE REJECTION Iii~
~ 120,-,---,-,--,--,---,
~ 120

.g

801-+-1-+---+-+--1
-8 60 1-+-1-+-1--+-1
0::

~

e

401-~--+-t-+-+~

~ 20 t---t----t--t--t-t---i

~
o

o

5

10

Common-Mode
Input Vonage \±V,

·1 -[

15

:;
o

I I
5

10

15

~1.11-+~~+-1-+-I

+15V

.~ 11---+_+-~_;;';';'-;'~

Vs

+lOV

&! 0.91-+~f---'I

Vs

+5V

1i

'\.

0.8 t---t----f-t---r

......

1

20
Supply Voltage, ±VDC,

~ 1.2

~R

fp =21rV O P

o

O. 7L-...I-...J..--L.~L..-.l.-..J

10 100 lk 10k· lOOk 1M
Frequency, Hz I

-50 -25 0 +25 +50+75+100
Temperature 10 C I

QUIESCENT
SUPPLY CURRENT

MAXIMUM
POWER DISSIPATION

~

,.,"
2:
"
~1

0""""

02

I

lA
V

TA~-25°C

TA - +85°C

00

10

5

I~sec)

~~0
~

H
0..8

60

4Q

20
01

,","
"-

10 100 lk 10k lOOk 1M

Frequency f Hz I

I- TA ~ +25 C.1

~

~ "-

-PSRR

INPUT OFFSET VOLTAGE YS
·THERMAL SHOCK YS TIME

:>

+PSRR

CMRA

~

50
100
150
Ambient Temperature 1°C)

STABILIZATION TIME OF
INPUT OFFSET VOLTAGE FROM
POWER TURN-ON

c:

"'0::
0::
'"
~ 'C
0.0

I"-

15

~ C2 100
80

,

I

Supply Voltage, ±V I

CMRR AND PSRR

5
Ii -" l\.:I"
~

.....

;rA - +25°C

.:;

2
Time

.ii)

110

FREQUENCY
CHARACTERISTICe
1.3·~,--,.-or------,

~L -Ekll

1±2~V- l

15 f\ls

o

020406080
Time I Ilsec I

o

g
TA -+25°C

TAT+8rC

j -5
o" -10

.II2 1oot::+=~+=hil

Vs

1

YS

RL - 2kll, CL - 500pF

1\

If

.

8. 20

TRANSIENT RESPONSE

CL - 500pF

.

l

~ 25

5~Jc

~

30

i

RL;>10kll

I I

o

12

(!l

r-- ,9O~o
I'"

OUTPUT VOLTAGE
FREQUENCY

VOLTAGE GAIN
125

+90

o
~ ±5

i5

:;

±10

ig

/~

i

1/

~±15

i

G

1-45

o

",.

±100

5:; ±200
£±300

I

I

.!;

.!;

8.

0

r- :::0; Tc':' +85°C -

o

10 20 30 40
Time From Power
Turn-On (seCI

50

8.
;

G

o

15 30 45 60 75
Time from Heat
Application (sec I

APPLICATIONS· INFORMATION
'. [':, ,.

offset voltage adjustment changes the laser adjusted"offset
voltage temperature drift slightly. The drift will change
approximately 0.3JtV/"C. for every I00JtV of pffset
adjustment.

THERMAL RESPONSE TIME.
Thermal response tiineisan important parameter in low
drift operational amplifiers like the OPA 103.,A low drift
specification would be of little value if the amplifier took
a longtime to stabilize afterturn-ori or ambient temperature change. The 'r0-99 package and careful Circuit
design provide the necessary quick thermal response.
Typical warm-up drift of the OPA 103 is approximately
20 seconds (see Typical P.erformance Curves).
GUARDING AND SHIELDING
The ultra-low bias current and high input impedance of
the OPAI03 are well-suited io a number of stringent
applications. However. careless signal wiring of printed
circuit board layout can degrade circuit performance
several orders of magnitude below the capability of the
OPAI03.
As in any situation where high impedances are involved.
careful shielding is required to reduce "hum" pickup· in
input leads. If large feedback resistors are used. they
should also be shielded along wIth the external input
circuitry.
Leakage currents acrqss printed circuit boards can easily
exceed the bias current of the OPA 103. To avoid leakage
problems. it is recommended that the signal input lead of
the OPAI03 be wired to aTeflon standoff. Ifthe OPA 103
is to be soldered directly into a printed .circuit board.
utmost care must be used in planning the board hiyout. A
"guard" pattern shoUld· completely surround· the .tWO
amplifier input leads and should be connected to a low
impedance point which is at the. signal input potential.
The amplifier case should be connected to any input
shield or guard via pin 8. This insures that the amplifier
itself is fully surroum!ed by guard potential. minimizing
both leakage and noise pickup. Figure I illustrates the use
of the guard. The resistor R., shown in Figure I is
optional. It may be used to compensate effects of very
large source resistances.·However. note that its use would
also increase the noise due to the thermal noise of R.I.

INVERTING AMPLIFIER

... -~---::'-.,

I

INPUT
FOLLOWER

INPUT
NONINVERTING AMPliFIER
(BOTTOM VIEWI
+Vee t\.
8

°R3 1liiY b. Uled 10 comP.1II111

lar very Ilrg.laurcl .rulllinca..
RI R2/1A 1+ RrI
mUlt baLOW Impedlnce.

Board llyaullor Inpul Guarding

whh TO-99 Plcltag..

- .V7 ~I

OUTPUT""-I·
.
05 ~

04

-Vee

3~

~

GUARO

FIGURE/. Connection of Input Guard.

Any paI.nllomel.r vllu.
between lOklllnd l00lm.

OFFSET VOLTAGE ADJUSTMENT
Although the OPA 103 has a low"" initial offset voltag~
(250Jt V). some applications may require external nulling
of this small offset. Figure 2 shows the recommended
circuit for adjustment of the offset voltage. External

L--~~-{)V_

FIGURE 2. External Nulling of Offset Voltage.

1-46

~

&~
~

BURR-BROWN®

OPA104

IElI3I

Ultra-Low Bias Current Low Drift FET Input
OPERATIONAL AMPLIFIER
FEATURES

APPLICATIONS

• SPECIFICATIONS GUARANTEEO OVER TEMPERATURE

• CURRENT TO VOLTAGE CONVERSION

• ULTRA-LOW BIAS CURRRENT. 751A. max

• LONG TERM PRECISION INTEGRATION
• PRECISION VOLTAGE AMPLIFICATION FOR
HIGH INPUT IMPEDANCE APPLICATIONS SUCH AS:

• HIGH INPUT IMPEDANCE. 1015n
• LOW DRIFT. 10Il V/oC. max

• photo currant datactora
• pH alactroda
• biological proballranaducars

• LOW OFFSET VOLTAGE. O.SmV. max
• LOW QUIESCENT CURRENT. 1.5mA. mix

DESCRIPTION
The OPAI04 is a precision low bias current operational amplifier. Guaranteed low initial offset voltage
(0.5mV. max) and associated drift versus temperature (lOll V "C, max) is achieved by laser-adiusting
the i1mplifier during manutilcturing. The low offset.
in addition to the guaranteed low bias current(75fA.
max). allows greater system accuracy with no extermsl components.
Quiescent current (l.5mA. max) is unaffected by
changes in ambient temperature or power supply
voltage. Other characteristics ofthe OP A 104 include
internal compensation for unity-gain stability and

rapid thermal response for quick stabilization after
turn-on or ambient temperature changes.
The amplifier is free from latch-up and is protected
for continuous output shorts to' common. As an
added protection feature, either of the trim pins can
be accidently shorted to a potential greater than the
negative supply v.()ltage without damage.
The standard pin configuration (741 type) of the
OPA104 allows the user drop-in replacement clipability. A pin 8 case cOhnection permits the reduction
of noise and leakage by employing guarding
techniques.

t -_ _ _-+-_--f'NTERMEOIATE
STAGES
OFFSET
TRIM

OUTPUT STAGE

INPUT STAGE

loteroal/ooll Airport 10dualTl., Park· P.O. Box 1\400· Tucloo. Arlzooa 85734· Til. 1602) 746·1111 . Twx: 911).952·1111· Cabl.: BBRCORP· Telex: 66·6491

1-47

, SPECIFICATIONS
, ELECTRIC~L
At TA

=+2SoC and -+Vee =-+15VDC unl..s otherwise noted
I

MODI!L.

MIN

OPl!N-/.OOP GAIN, DC, YftU'I'. +'O¥
Ratea Load, ,RL .. 21Ul .
RL;;>IOkO
T. = -25°C to +&soC, RI ;" 21lll

::

JU.TI!D

I

OPjU04AM

PARAMlTlljia

TYP

MAX

MIN

OPA'CMBM
TYP

I
MAX

MIN

OPA1IMCM
'TYP

I
MAX

Ulllft

1(111.
112
100

112

dB

dB
..dIL

nu,...UT

vonage al RL = 2Ml. TA = -2SoC to +85°C
RL = 10kO, TA = -2SoC to +&soC
Current T.. = -25"C to +85-0. Vo =±10V
Output Impedance
Load Capacltancel 11
Short Circuit Current

±10
±12

500.
10

mA

'25
1,6

1
35
2,2

V/",S8C

±5

FREOUl!NCY R E _
Unily Gain, Small Signal
Full Power Reopense
Slew Rate
Settling Time '0,1'1101, Av = -1, Vo =0 to±10V
Settling Time '0,01'1101, Av = -1, Vo =0 to :tl0V
Overload Recov~2). ~ overdrive

Ii

±12
±13
:1:10
3
1000
2S

V
mA
kO
p~

MHz
kHz

6

psec
pS8C
pS8C

16

4

15

±200
±1S
±10
+20

±looo
±25
±IOO
±150

INPUT OFFIET VOLTAGE
Initial Ollset, T. = +2SoC

v.• Temperature, T A = -25°C to +85°C
vs Suppiy Vonage, T. = +2SoC
vs Supply Voltage, T. = -25°C to +85°C

±2OO
±10

±500

:t2OO
±S

:tIS

pV

:t500
±10

;NloC
pVN
.VN

INPUT llAl CURRENTCO)
Initie//!Iia., T.I. = +2SOC·
vs Supply Voltage

-300

-75

-'SO

fA
IAN

1

INPUT DIFFI!RENCE CURRENT
Initial Difference. Til. = +25°C

I

I

INPUT IMPI!DANCE
Differential
Common-mode

10 14
10'5

INPUT NOI.
Vo.ltsge,lo - 10Hz
to = 100Hz
'0';' 1kHz
10 = 10kHz
fa = 0, "Hz 1010Hz
Current, fa = O,IHz to 10Hz
fa = 10Hz to 10kHz
fo = lkHi
INPUT VOLTAGE RANGE
Differential
Common..mode. T A = -25°0 to +85°C
Common-mode Rejection at VIN = ±lOV
Maximum Sale Input Voltage
POWER IUPPL Y
Raled Voltage
Vortsge Range. derated performance
Current. quiescent T A = -25°C to +85°C
TEMPERATURE RANGE , _ _I)
~ ~pecl

lcatlon
Operating
Sto,age
8 junction - ambient

I

:t60
Ii

:t80

I

I

±40

I

IA

nil pF
nil pF

0.5
1.0

75

nVlv'~Z

55

nV/JHz
nV/JHz
nV/y'1'tz

35
35
6
3
10
0,25

.V, pop
lA, Pop
fA, rms
IAI.jRZ

:t2O

:tl0
66

I

±12
76
±Vee

60

±15

±20

:t5
1,0
-25
-55
-65

1.5
+85
+125
+ISO

235

go

V
V
dB
V
' VDe
VDe
mA
·e
·e
·e
·eM

·Specification. same . . for OPA104AM,
NOTES:
1, Stability guaranteed with loed capacitance :s 5OOpF,
2: Overload ree"overy is defined as the time required for theQutput to return from saturation to linear operation follo~ing th"e removal of a 50% input overdrive

signal.
,3, Bias current is'lested and guaranleed after 5 minutes 01 operation al TA = +2SoC, For higher temperature the bias current doubles approximately every
+',OOC,

1-48

. CONNECTION DIAGRAM

MECHANICAL

~--------~------------~--~----------------~

TO-99 PACKAGE

INCHES
MIN
MAX

DIM

MILLIMETERS

MIN

MAX

A

.335

.370

8.51

9.40

0

.305

.335

7.]5

8.51

C
0

.166

,185

4.19

4.70

.016
.010

.021

0 .• '
0.25

0.53

.040

.010

.04.

E

.200 BASIC

G

.034
.045

.028

.029

.

1.02
0.86

0.71

1.1 •

0.74
12.7

.500

K

1.02

0.::15

5.08 BASIC

.110

.160

,.095

.105

4.06

2.79

45° BASIC

N

2.41

2.67

Weight: 1 gram
-VCC

'WN~te
H/ '

leads in true position within .010"
1.25mm I R at MMC at seating plane.

Pm material and plating composition

Pin numbers shown for reference only.

conform to Method 2003 ,solderability

ITOPVIEW)

Numbers may not be marked on package. of MIL-STO-883 I except paragraph 3.21,

TYPICAL PERFORMANCE CURVES
OPEN-LOOP FREQUENCY
RESPONSE

120

.......

L__

r\.

~

+-45 ~

:\.

~

~
o '"
~

-45 :

I'\..

:\.
o

o

1

&

.8

~ 100

95

g

~ -180

TA

90 5

VOLTAGE FOLLOWER
LARGE SIGNAL RESPONSE
RL - 2kll

~+10

/
/

f+S
o
>

0

i

-5

1/

.:1

0-10
-15

o

~ +40

\

:I

Time

~ ~R
P 211'" Vop

~

t

"

8109

'\.

+5V

1

~

~

.!t>

~

i5

~ 750
ill 600

; 450

"

~1
c

\

I

1\1

~
.1

2

3

0

5

IIJS8C1

~

+PSRR

=

10
15
20
Supply Voltage \ +V I

STABILIZATION TIME OF
INPUT OFFSET VOLTAGE FROM
POWER TURN·ON

~

"~

i

>

'\...
~

~r-...
~

-PSRR

10 100 1k 10k lOOk 1M
Frequency (Hz)

1-49

.....

50
100
150
Ambient T empsrature \·C)

r--

/

,/

/

I

'5
a.
':-15
.5

U

o

I"'-

f- FTC =+85°C

0

5_10
c:
.c

" ""',

I - TA =+25°C _I

: -5

.
..'"

MAXIMUM
POWER DISSIPATION

INPUT OFFSET VOLTAGE vs
THERMAL SHOCK vs TIME

.. +5

::lio.

1

&300
"iii
} 150

:I

4

~1

~;::-900

82

··-rO'..,~~

-50 -25 0 +25 +50 +75+100
Tempsrature(OC)

c:

~

1--

o? .

10 100 lk 10k lOOk 1M
Frequency 1Hz)

QUIESCENT
SUPPLY CURRENT

.;(

"-~~

Slew Ra\e

...

0.8

........

I
I

~

1

10

+10V

Vs

5 Vs

12

~1.1
.!:

o

CMRR AND PSAR

==
15

RL -2kll

a.
a.

CMRR

10
Common-Mode
Input Voltage I±V)

~10

FREQUENCY
CHARACTERISTICS
1.3

+15V

Vs

>

o

i

o

-

'S 15

+25°C

R~ 1f.kll. fL "1 5OOPF

6~

1--+-+---+-+--+--1

o

+arc

20

~ 60~~-1-1-~-t-~

t8:

.

TA

10
15
20
Supply Voltage \ VDC)

COMMON-MODE REJECTION
~12Or--T--~-T--~-T--;

1

~
&20 v s l J v -

o 0
>
~ -20

10 20 '30 40
Time (,..,secl

:5 l00~:j:=~:j:=;:80 r--'-f-

j

1+

\
\
\

"':2 5

TRANSIENT RESPONSE

CL = 500pF

I I

;;;

I I

Froquency I Hz>

+15

I

30

RL<;!10kll

1

;::- 110
TA - -25°C
'iii
Cl 105

-135~

-90

1

~ 115

10 100 lk 10kl00klM

I

OUTPUT VOLTAGE ••
FREQUENCY

VOLTAGE GAIN
120

+90

.
.

II

.5
0

10 20

30 40

Time From Power
Turn..Qn (sec!

50

,",

c
.c

U

o

15 30

45

Time (secl .

60 75

value of C2 (0.5pF to 2pF) is what would be typically
required. to compensate for the pole generated by 'the
capacitance lit the input node: A larger value of C2 could
be usCll to limit the bandwidth and reduce the' voltage
noise at higher frequencies.

APPL.ICATIONSINFORMATION
THERMAL RESPONSE TIME
. Thermal response time is an important parameter in low
drift operational amplifiers like the OPA 104. A low drift
specification would be oflittle value if the amplifier tooka
long time to stabilize after liun-on. or ambient temperature change. The TO-99" package and careful circuit
design provide the necessary quick thermal response;
Typical warm-up,drift of the·OPAI04 is approximately
20 seconds (see Typical Performance Curves).

-

GUARDING AND SHIELiUNG
The ultra-low bias current and high input impedance of
the OPAI04 are well-suited to a number of stringent
applications. However, careless signal wiring of printed
circuit board layout can degrade circuit performance
several orders of magnitude below the capability of the
OPAI04.
As in any situation where high impedances are involved,
careful shielding is required to reduce "hum" pickup in
input leads .. If large feedback resistors are used, they
should also be shielded along with the external input
circuitry.
Leakage currents across printed circuit boards can easily
exceed the bias current ofthe OPAI04. To avoid leakage
problems, itis recommended that the signal input lead of
the OPAI04 be, wired toa Teflon standoff. If the OPAI04
is to be soldered directly into a p.rinted circuit board.,
utmost care must be used in planning the board layout. A
"guard" pattern should completely surround the two
amplifier input .leads and should be connected to a low
impedance point which is 'at the signal input potential.
The amplifier case should. be connected' to any input
shield or guard via pin 8. This insures that the amplifier
itself is fully surrounded by guard potential, minimizing
both leakage and noise pickUp., Figure I illustrates the use
of the guard.
OFFSET VOLTAGE ADJUSTMENT
Although the OPAI04 has a low initial offset voltage

-55
-65
200

·C
°C/W

NOTES: (1) Sample teated-this p.rameter. is guaranteed. (2) Offset voltage, offset currant, and bias current are measured with the units fully warmed
up. (3) Overfoad recovery is defined as the time req,uired for the Ol,Atput to return from ~turation to linear operation following the removal of a ~ input overdrive.

1-52

ELECTRICAL [FULL TEMPERATURE RANGE SPECIFICATIONS)
At Vee

= ±15VDC and TA =

T MIN to T MAX unless otherwise noted.
OPA111AM

PARAMETER

CONDITIONS

MIN

Ambient temp

-25

TYP

MIN

+85

··25

TYP

-<

OPA111SM

OPA111BM
MAX

MAX

MIN

+85

-55

TYP

MAX

UNITS

+125

·C

1-1500
±5

"VI·C

1:50

"VIV

a..

TEMPERATURE RANGE
Specification Range

=

INPUT
OFFSET VOLTAGE~"
Input Offset Voltage
Average Drift
Supply Rejection

V,.

-

OVDC

t220

+2
86

flooO
i5

100

±110

±10

tSO

100
flO

±300

i500
tl

to.S
90

t.32

12
100
±10

86

"V

dB

BIAS CURRENT' "
Input Bias Current

V,.

OVDC

±50

1250

t30

+130

±820

14100

pA

OFFSET CURRENT'"
Input Offset Current

V,.

OVDC

±30

1200

±15

i

100

±S1Q

13100

pA

VOLTAGE RANGE
Common-Mode Input Range
Common-MOde Rejection

VON

-tlQVDC

il0
86

tl1

100

-t10
90

t-'1
100

110
86

i11
100

V
dB

RL .... 2kQ

110

120

114

120

110

120

dB

R,

110

+11
.,0
40

t 10

±11

±5
10

",0
40

tl0
±5
10

±11
il0
40

mA
mA

OPEN-LOOP GAIN, DC
Open-Loop Voltage Gain
RATED OUTPUT

Voltage Output
Current Output

V.
V.

Short Circuit Current

2kO
tl0VOC
OVDC

+5
10

V

POWER SUPPLY

Current. QU,iescent

NOTES:

10 - OmADC

2.5

3.5

3.5

2.5

mA

3.5

2.5

(1) Offset voltage, offset current. and bias current are measured with th~ units fully warmed up.

ABSOLUTE MAXIMUM RATINGS
Supply ............................................. ±18VDC
Internal Power DiSSipation!1I .•........................ SOOmW
Differential Input Voltage t21 . . . • . . . . . • . . . . . . . . . . . . . . . .. ±36VDC

Input Voltage· Range'"' . . . . . . . . . .. . . . . . . • .. . .. . . . . . . .. ±18VDC
Storage Temperature Range ................. -65°C to +150°C
Operating Temperature Range· ............... -55°C to +125°C

ORDERING INFORMATION

Lead Temperature (soldering. 10 seconds) ............. +300·C

OPA111

Output Short Circuit Duration!3t ...... . . . . . . . . . . . .. Continuous
Junction Temperature. .....
. ....................... +175°C.

=r-

NOTES:
(1) Packages must be derated based on 8Jc::;; 150°C/W or 8JA ;::;::. 200° C/W.

(2) For supply voltages less than ±18VDC the absolute maximum input
voltage is equal 10 the supply voltage.

~ to power supply common only. Rating applies to
+25°C ambient. Observe dissipation limit and T J .

(3) Short circuit may

MECHANICAL

"M" PACKAGE TO-99 (Hermetic)

NOTE:
Leads in true position within .010"

(.25mmR)at MMC at seating plane.

L~;P j I .

CONNECTION DIAGRAM
TOP VIEW

Pin numbers shown for reference
only. Numbers may not be marked
on package.

Pin material and plating composi

SUBSTRATE AND CASE

C Seating
Plan.

F

K

III 'l~

--&--0

C

T

M

1-53

Nr-

•
. ,.'. , N'~-

.,. ,
0

M

tion conform to Method 2003 (solderability) of MIL-STD-883 (except
paragraph 3.2).

+

V

DIM
A

C

0
E

,
G

"

J

K

.

INCHES

MIN

MAX

.33fj

.370

.3"

.335

.166
.185
.021
.016
.010
.010
.200 8ASIC
.034
.•28

........
.... ....
.'00

L

.160
.110
46° BASIC

N

.09'

.,.

MILLIMETERS

MIN

MAX

8.51
9.40
8.61
7.n
4.70
4.19
0.53
0.41
1.02
0.25
0.25
'5.08 BASIC
0.71
0.B6
0.74
1.14

..

12.7

....
--

2:79
45° BASIC
2.67
2.41

.'

TYPICAL PERFORMANCE CURVES

~

T. = +250 C. Vee = ±15VDC unless otherwise noted,
'INPUT CURRENT NOISE SPECTRAL DENSITY

100

i

~

10

~

:i

1

!

.~

I

,

I

E
~

!

~:;;

"

I

;

i

,1/

I

I

"
~'"

i

0.1

100

10

I

lk
10k
Frequency (Hz)'

.~

I....

I

z0

"

~

R,
!

"'"

I

10

0>

II

BM

,

I

trom source. r~~listancel
0.1

10

i

,

*Includes contributi'on

1

I
;

I

I ; I

lk
10k
'Frequency (Hz)

10MO++
*Includes

1M

~~~~~~1~
~

.5

100kCl

9l

'0

z

.JR. lillobn
1

BM

t-

"
~

f~ = 0.1 to 10Hz

j,ooI

10

g

II!I I

"'"

10'"
~

'1,111 I
10k

lOOk

source resistance

~
> 100

! i'l I

100
lk
Frequency (Hz)

...

100

TOTAL' INPUT VOLTAGE NOISE (PEAK-TO-PEAK)
YS SOURCE RESISTANCE'

lk

lOOk

10·

10'

10'

10'

10'

10·

Source Resis~ance (Q)

VOLTAGE AND CURRENT NOISE SPECTRAL
DENSITY YS TEMPERATURE
12

II
10

100

.s

1T

1M

' R,=lMO
_II ;llltt.

i

B

1

lOOk

R.

iIIII..

fA""

r-

I

B~

TOTAL' INPUT VO~TAGE NOISE SPECTRAL
DENSITY vs SOURCE I'lESISTANCE

lk

~:;;

10

>

I

' i

"-'

'0

z

"

I

AM.SM

9l

U

!

100

.s

,

I

z

:

j

iNPUT VOLTAGE NOiSE SPECTRAL DENSITY

lk

TOTAL INPUT VOLTAGE NOISE SPECTRAL DENSITY
AT 1kHz YS SOURCE RESiSTANCE

--

100

1~

-

~:;;

foJlkHz

10

.Jl 10

.s
9l

8

'0

z

"g>

:::
0

6

~~

>

-

~~

V

i"""

~
~~

""""

4
-75 -50

-25

(}
+25
+50
Temperature (OC)

+75

~

~

z

W

~

'0

;;
a

~100

g

Q.

Or\'111 + resistor

z

~
0.1~

Err:

& 10

I~
1
100

"'"

>

'"

10M

100M

8,

c
~
.c

c

BM

~

.c

U

U

0

f

~

g

I

10k
lOOk
1M
Source ReSistance (0)

AM

>
3+75

-; +10

.0>

Resistor noise only
lk

INPUT OFFSET VOLTAGE CHANGE
DUE TO THERMAL SHOCK

INPUT OFFSET VOLTAGE WARM-UP DRIFT
+20

.

BM

II"

....,.

S
>

'0

0.01
+100 +125

i..I!'

Ii'

i

-10

0
T. = 25°C to T' = 85°'C
ir environm nt

-75

5
-20

-150
0

4
5
2
Tim" From Power Turn-on (Min)

6

1-54

-1

o

+3
+4
.+2
+1
Time From Thermai'Shock (Min)

+5

BIAS AND OFFSET CURRENT

BIAS AND OFFSET CURRENT
vs TEMPERATURE

10

10

.L.
100

<'
.e
E
~

"./

=

;;r

~,

10

gj

.

~~

iii

-

I:

E

~
;a
'0

-

~

"",.
/

0.1

<'
.e

10 C"l

-_..

::>
U

!

:

...

ii,

II:
0.1

III

i

C"l

!;

iil

;a
0.1

'0
~

0.1

7"'7

I

III

'Offset Current

!

...-

t:~~~=±;:=:;:!;::=:!;=::::j;:=+;==tO.Q1
-25
0
+25
+50
+75
+100 +125

0.01
-50

0.01

U·

I

-15

o

-5

-10

0.01

+10

+5

+15

Common-Made Voltage (V)

Ambient Temperature (OC)
POWER SU.PPLY REJECTION
vs FREQUENCY

COMMON-MODE REJECTION
vs FREQUENCY

140rTlirr-rTnr~nn-r~~~~~nr~~

140rT~~~~~~~-r~~~~~~~Tn

2Ot-+-++IH--H+r-I-+!+I--+-++#--HH#+++I1~~

Frequency (Hz)

Frequency (Hz)

COMMON-MODE REJECTION
vs INPUT COMMON MODE VOLTAGE

120

CD
~

. 110

I:

0

U
Q)

'ar

II! !
I

100

I
I

I

I

I

I

,!

!I

I

i

!

I

i

120

I

CD 100
~
I:

I

a:

!

I

Q)

0

90

C
E
E
0

!

,

0

I

70

'iii

i

C!l

I

'I

-15

i

I

iI

o

-5

-10

I

Iii
+5

.,..

No.

80

'"

60

>

40

~
a

,

I

Ii

+10

""" .".,.
,

I

I

,~

o

+15

~

'j

.

2·

100

1k

'"

:r

~

.
Lr-- .ei".. ...'."
Jl

£;

(j)

'j

<:

"c.

I

10M

I

2

P'"'

"C
I:

I:

I:

1M

!

l-

N

:e

'"'iii

100k

10k

3

i"

J.

i

Frequency (Hz)

3

"C
I:

~,

-180
10

I

1

C!l

C!l

o-75

-50

-25

o

o
+25

+50

+75

o
o

+100 +125

Ambient Tempereture (·C)

10
Supply Voltage (±Vcc)

1-55

15

g!

=

~
- 135

GAIN-BANDWIDTH AND SLEW RATE
va SUPPLY VOLTAGE

4

N

-65·
I~

1

I
~

Margin

1'OoJ'I1

Common-Mode Voltage (V)

:r

• Phase

I'iori..

"::l

-90

1-1

L

"1'oIJ

'.

,

GAIN-BANDWIDTH AND SLEW RATE
vs TEMPERATURE

4

-::r

¢-r

~

20

!

I

"tJ

.~

,

-45

,.

[

~ 'G~\n'

,

,

i

.".

Q)

I

80

u

I

i'

"C

:;

OPEN-lOOP FREQUENCY RESPONSE

140

I' !! I! I

=
~

0

I+-

I

I

Bias Current

~
u"
iii

II

I

I.

100 0

=BM

-:c

ys INPUT COMMON MODE VOLTAGE

1k

1k

J
20

o

1

TYPICAL PERFORM;AN,CE,. C,VRVI;S:[CONTl
,
. ., ..

T. = +2S'C, Vex: = ±15VOC unl_ otherwise noted.
OPEN-LOOP GAIN
vs TEMPERATURE
140

MAXIMUM UNDISTORTED OUTPUT
. VOLTAGE V8 FREQUENCY

.. 3P

,

00-

-

-

130

~

, .E

,"'

'"

Cl' 120

."

01

'" 110
>
0

I

I

~~

- .......

~
~ 20
"'"

\

!

CD

\;

, "-

,

10

"

'"

.0

-75

-50

-25
0
+25
+50
+75
... Arnbi~nt Temperature'(·C)

o

+100 +125

,

i'-

>

100

I

~.

="
0,
~

'

,

I

1k

10k

" """

~

100k

1M

Frequency (Hz)

SMALL SIGNAL TRANSIENT RESPONSE

:;-

~

g

"

0>

~

"0

>

:;
a.
:;
0

Time (psee)

Time (psee)

SETTLING TIME
vs CLOSED-LOOP GAIN
100

I

iI

i,

j

0

,
0

,

I

:

Ii

,

I/J

,!
I

I.

..

..

20
"

1/

. ,.
0.01%

Z

.,."
,,-

1

I

<
I

;

I

i

'.
10
100
Closed-LoOp Galil (V/V)

,

g

3~--+---+---~---r---+---f---;---1

E

~

I

<3

I

a.
a.

i

,

io"'".¥"'

I

I

0.1%

:

o

"

I

I"

I

4r-__~S=U~PP~L~Y~C~U~RrR~E~N~TrV~.~T~ETM~P~ER~A,T~U~R~E-r__,

I
I 1/

I

' !

I.

0

I

2

~-4--~---r--1---t-~r--t--~

1!-

til

1

I I

, i i
1k

oL-....L_..J.._-'-~~~::---:-::----:--=~
-75 -50
~25
0
+25
+50 +75 +1OQ +125
Ambient Temperature ('C)

APPLICATIONS
INFORMATION
OFFSi:T YOq"AGE ADJUSTMENT
The OPAllI offset voltage is'laser-trimmed and will
require no further trim fOJ; most applicatio/ls. As with
most amplifiers, externally trimming the remaining .offset
can change drift performance 'by about O,3p.V/oC for
.each.IOOp.V of adjusted offset, Note that the tritn (Figure
·1) is similar to ,operational amplifiers such as 741 and
AD547, The OPAUI can replace most other amplifiers
by leaving the external null circuit unconnected ..
INPUt· PROTECTION
Conventional monolithic FET operational amplifiers

8

±IOInV TypiCAl.
TRIM IIAIIGE

. . -Vee

FIGURE 1. Offset Voltage Trim.

'IOKn TO IMn
TRIM POTENTIOMETER
RECOMMENDEDI

"00kn

NOISE: FET VERSUS BIPOLAR
Low noise circuit design requires careful analysis of all
noise sources. External noise sources can dominate in
many cases, so consider the effect of source resistance on
overall operational amplifier noise performance. At iow
source impedances, the lower voltage noise of a bipolar
operational amplifier is superior, but at higher impedances the high current noise of a bipolar amplifier becomes
a serious liability. Above about l5kO the OPAlIl will
have lower total noise than an OP-27 (see Figure 3).

require external current-limiting resistorS to protect their
inputs againkt destructive currents that can flow when
input FET gate-to-substrate isolation diodes are forwardbiased. Most BIFET amplifiers can be destroyed by the
loss of-Vee.
Because of its dielectric isolation, no special protection is
needed on the OPAlll., Of course, the differential and
common-mode voltage limits should be observed.
Static damage can cause subtle changes in amplifier
input characteristics without necessarily destroying the
device. In precision operational amplifiers (both bipolar
and FET types), this may cause a noticeable degradation
of offset voltage and drift.
Static protection is recommended when handling any
precision IC operational amplifier.

GUARDING AND SHIELDING
As in any situation where high impedances are involved,
careful shielding is rquired to reduce "hum" pickup iIi
input leads. If large feedback resistors are used, they.
should also be shielded along with the external input
circuitry.
Leakage currents across printed circuit boards can easily
exceed the bias curent of the OPA\ll. To avoid leakage
problems, it is recommended that the signal input lead of
the OPA\ll be wired to a Teflon standoff. If the OPA\ll
is to be soldered directly into a printed circuit board,
utmost care must be used in planning the board layout.
A "guard" pattern should completely surround the high
impedance input leads and should be connected to a low
impedance point which is at the signal input potential.
The amplifier case should be connected to any input
shield or guard via pin 8. This insures that the amplifier
itself is fully surrounded by guard potential, minimizing
both leakage and noise pickup (see Figure 2).
NON·INVERTING

BUFFER

INVERTING

10-811 BOTTOM VIEW

Source Resistance (R.),

Q

FIGURE 3. Voltage Noise Spectral Density Versus
Source Resistance.
'

BIAS CURRENT CHANGE VERSUS
COMMON-MODE VOLTAGE
The input bias currents of most popular BIFET operational amplifiers are affected by common-mode voltage
(Figure 4). Higher input FET gate-to-drain voltage
causes leakage and ionization (bias) currents to increase.
Due to its cascode input stage, the extremely-low bias
current of the OPA\ll is not compromised by commonmode voltage.

-10

-5
Common-Mode Voltag", (VDC)

OUT

FIGURE 4. Input Bias Current Versus Common-Mode
Voltage.
BOARD LAYOUT
FOR INPUT GUARDING

APPLICATIONS CIRCUITS
Figures 5 through IS are circuit diagrams of various
applications for the OPAlll.

Guard lop and baltom III baard•
.Altern.te: ule Tlllion" atendoH

for sinsltlve Inpul pins.
Teflon" E. I. Du Pont de Nemours & Co.

FIGURE 2. Connection of Input Guard.

1-57

-=
c

a.

9.5ko

+15V

IWoe

OUTPUT

TRIM

'T
"

FIGURE 5. High Imped!Ulce (10140) Amplifier.

OUTPUT

6

PYROELECTRIC
DETECTO;:.R_'-;,_-1-....

OFFSET "

NOTE: PYROELECTRIC DETECTORS, RESPOND
'TO RATE·Of.CHANBE lAC SISNALI ONLY

FIGURE 9. Pyroelectric Infrared Detector.
l00MO

OUTPUT

10 = 50IIV

.iT

5 x IO'V/WATT

CIRCUIT MUSTBE
WELL SHIELDED.

FIGURE 6. Sensitive Photodiode Amplifier.

OFF,SET VOLTABE

=

255pvoe MAXIMUM

WlTiI NO OFF8ET AD.lU8T
INP\IT '

500pf

, 500pf~FO,R

-

FIGURE 10. Computerized Axial Tomography (CAT)
SC¥lner Channel Amplifier.

.
50Hi USE alaMo AND 6.37Mo

FIGURE 7. 60Hz Reject Filter.

PIN DIODE \
< IpF TO PREVENT PEAKING
(SILICON
...-"'"'.:....:...,
DETECTOR CORP.
SD.Q41.n-21.Q111'...-.......~~...........,

\~

..,.a. TO -20118.
RF INPUT

1~

+5VDC

':"

~1pfI

12OO111vDCIpW
VIDEO BANDWIDTH: DC II DHz
I. -

':"

FIGURE 8. Zero-Bias Schottky Diode Square-Law
RF Detector.

":' OVERLOAD - 0.1pW INPUT ':"

FIGURE ll. High Sensitivity (under InW) Fiber Optic
Receiver for 9600 Baud Matlchester Data.

1-58

--

68lkn

r

~
=

IpF

AQ

0 - - -__-:.1
MAGNETIC 47.5kn
CARTRIDGE
INPUT

-.

G= 26dB MIDBAND

LOW fREQUENCY CUTOff =
1I(27TR,C,) = O.l6Hz

-.

IN914

'0 = -AQ/C,

FIGURE l3. Piezoelectric Transducer Charge Amplifier.

FIGURE 12. RIAA Equalized Phono Preamplifier.

IMn

>--4----0
INPUT

0-----..,

OUTPUT

DROOP - 10000V/lec

I.

O.OlpF POLYSTYRENE

* REVERSE POLARITY fOR

NEGATIVE

PEAK DETECTION

FIGURE 14. Low-Droop Positive Peak Detector.

-IN

I. = IpA
GAIN = 100
CMRR - 106dB
R'N = 10130

o--------:=-f

r---------------------,
25kn

5kn

I
I

25kn

15

I
I

lOIn

I

R.

1
5kn

>-i-I-'-OOUTPUT

,6

25kn

,,
__________ J
I

25kn

AMPLIFIER

L _____ _
+IN 0--------'''1

I

DifFERENTIAL VOLTAGE, GAIN =

1 + 2RdR G

FIGURE 15. FET Input Instrumentation Amplifier.

1-59

I

iooo

10Ic0

IGkO

INPUT

!
':"

6

10Ic0

Ay=-IOIO

=

I.9nV/y1Ii TV,. AT 10kHz
BW = 30kHz TVP
SBW = 30.3 MHz TVP
Vos = ±16pV TV,.
AVos! AT = ±lJ.16pV/·C TV,.
I. = 10pA mix
l,N - 10"0 II 30pF

In

10kCl

'THEORETICAL PERFORMANCE
ACHIEVEABLE FROM OPAIIlBM
WlTli UNCORRELATEO RANOOM
DISTRIBUTION OF PARAMETERS.

IOkO

EXAMPLE:

In

=

v(ln.r + (Ina" + (IOJ' + ... + (1nN1

2

IOkO

10kel

OUTPUT

!

I

I
I

..

I
I

.',
I

~-----------~-lI

I

'-

""

'~--------------~

"",

I ",

I

,,'

I

N= 10 OPAIIIBM

FIGURE 16. 'N' Stage Parallel-Input Amplifier.

IpF

375.1kO
IN~

__

~~

__

~

+-________________

____ 187.51cO ____
~~

~

375.1kO
~--.....------~~

I".
. FIGURE 17. O.6Hz Second Order Low-Pass Filter.

1-60

OUT

BURR-BROWN@)

OPA201

113131
PAT. PEND.

Switchable-Input Operational Amplifier
SWOPAMp™
FEATURES

APPLICATIONS

• TWO PRECISION INPUT STAGES
SELECTABLE WITH CONTROL SIGNAL

•
•
•
•
•
•
•
•

• EXCELLENT INPUT SPECIFICATIONS
VoslOOpV max IC Grade)
t:. Yost t:. T lllVloC max IC Grade)
IB 25nA max IC Gradel
• LOW POWER
±Vcc 2.5V to lBV
10501lpA max

AUTO-ZERO SYSTEMS
TWO-CHANNEL MULTIPLEXER WITH GAIN
SELECTABLE-INPUT INSTRUMENTATION AMPLIFIER
SWITCHABLE-GAIN CIRCUITS
SWITCHABLE-BANOWIDTH CIRCUITS
SYNCHRONOUS MODULATOR/DEMODULATOR
ISOLATION CIRCUITS
BATTERY OPERATED SYSTEMS

• EASY TO USE·

DESCRIPTION
The OPA201 is a switchable-input operational amplifier (Swop Amp"'). It contains two independent
differential input stages and one output stage. Either
of the input stages may be connected to the output
stage under the control of the Channel Select digital
input signal which· is TTL-compatible or userprogrammable. The OPA201 is easy to use and
functions as an operational amplifier that can switch
between two sets of inputs.
Each input stage provides excellent input characteristics: low offset voltage (lOOj.!V, max), low offset
voltage drift versus temperature (lj.! V/0 C, max),
and low bias current (2SnA, max).
Additionally, the Swop Amp is a low power device.
It draws less than SOOj.!A (max) over the supply
range ±2.SV to ±18V. It is well suited for portable,
remote, and other battery powered applications.
Also, its low power consumption and excellent
specifications make it well suited for isolation circuit
applications. Burr-Brown's state-of-the-art monolithic design and processing, compatible thin-film

resistors, and active laser trimming produce a truly
unique highly versatile circuit. The unique switchable input stage design allows minimum hardware
and minimum cost solutions to some very demanding analog circuit design problems.

1 OFFSET
TRIM
OFFSET

TR.M

+IN 1

OUTPUT

CHANNEL
STATUS
STATUS
COMMON

CHANNEL
SELECT

CHANNEL
SELECT
THRESHOlD
CONTROL

.ntlrnlilanl' Airport Industrll' Plrk· P.O. Box 11400· Tuclon. ArlzDnl85734 • TII./602I 746-1111 • Twx: 910-952·1111 • Clbla: BBRCORP· Talax: 116·849'

1-61

SPEC.IFICATIONS

ELECTRICAL

At Tit:::;::; +25Q C and ±Vcc = 15VDC unless otherwise noted. Specifications are for either channell or 2 unless otherwise noted.
OPA201AGlRG
PARAMETER

CONDITIONS

OPEN-LOOP GAIN, DC
Rated Load, RL = 10kCl

V OUT

RATED OUTPUT
Voltage at RL ;::::. 10kCl

Current,

VOUT

= ±10V

MIN

TYP
130

MIN

TYP

'OPA201CG
MAli

'MIN

TVP

MAli

UNITS

= ±10V

T,,;: +25°0

114

T,,=TM1NtoTMA)(

11d·

T,.= TMINtoTMAX

±13.5

Output Impedance
Short Circuit Current
INPUT OFFSET VOLTAGE'"
e·ither Channel
InitiaIOffset(2)
Average Drift
Over Temperature(3)
vs Supply

OPA2018G/SG

MAX

dB
dB

120'
114

""

±14
5
0.5
10

V
mA

kll
mA

...
=

TA +25"C
T" = T.MIN to TMjI,JI
TA

±Vee

=

TMIN

to TMAX

120
1.4
150

500
5.0
1000

70
.0.9
100

8
10

32

5

60

6

= ±2.5V to ±18V
T,.,= +25°C

T,,=TMINtoTMAX

200

35

2.0

Q.5

100
1.0

.500

55

200

/lVl"C
/lV

16
32

4

10
16

/lV/V
/lV/V

50
100

/lV
/lV

5

/lV

Match Between
Channels 1 8!1d 2

T,,= +25"C

Initial

500

65

1000

90

15

50
60

13

40
50

12

25
30

nA
nA

1.4

4
6

0.75

2
4

0.7

1
2

nA

150
150

Over Temperature(3J

100
200

25

30

INPUT BIAS CURRENT

T,,:= +25°C,

Initial Bias Current
Over Temperature(31

".

INPUT OFFSET CURRENT

Initial Offset Current

TA

Over Te~perature!31

FREQUENCY RESPONSE
Unity Gain, Small Signal
Full Power Response
Slew· Rate
Settling Time 0.1%
Settling Time O.Ol~

= +25"C

500
4
T" = TMIN toTMAX
10V Step
10VStep

kHz
kHz

0.1

V/psec
49
52

INPUT IMPEDANCE
Differential

IJSOC
IJSOC

-,

6
10'· 112

Common~Mode

INPUT NOl8E
Voltage
Voltage Density

f8 = 0.1 to 10Hz
fo= 1Hz
fo.= 10Hz
fo = 100Hz
to = 1kHz
. f8 = 0.1 to 10Hz
10 = 1Hz
fo= 10Hz
10 = 100Hz
to= 1kHz

Current
Current Density

nA

Mil
1111 pF

1
85
27
27
27
1.5
tooo

/lV,p-p

nV/"fHz
nV/"fHz
nVl"fHz

300

nVl"fHz _
pA, pop
1A/"fHz
1A/"fHz
1A/"fHz
1A/"fHz

.,

100
100

INPUT VOLTAGE RANGE
Common~Mode

T,,=+25°C
T,,=TM1NtoTMAX
T" = +25°C
T,,'= TM'N tOTMAlC

Common~Mode

Common-Mode Rejection',
V'N= +10V
POWER SUPPLY
Rated Voltage
Voltage Range,
derated performance
Current, quiescent

92

I

90
85

98

95·

95

90

425

-Vee

T,,=TMINtoTMAX
VCSEL::: +Vcc
VeSEL = VTC = OV

-Vee
VTc+2,
-Vee
-Vee
<1
25

= CsEL)'"

=

10:. = lmA, Vsc OV
= 15V, Vsc:= OV

Vpulll,lP

500

VDC
/lA

.,

V

+Vee
+Vee
VTc+0.8
VTe + 0.6
50

V
V
V
V
/lA

80

0.4
2.0

dB

+Vcc- 5

'"

-Vee

98
97

V
V
V

VDC
±18

±2.5

'.

I"
Status Common (SC)
Voltage Range
Channel Status
(CSTA
V",V...

94

80

"

+12.5
+12

±15

DIGITAL SI~NALS
Threshold control
(TC) Voltage Rango
Channel Select (CSEL)''''
Voltage Range
V'H (selects C?h. 1)
V'L (selects ch. 2)

hH

-12.5
-12
85

15

1-62

"A
~

V

V
V

ELECTRICAL (CO NT)
OPA201AG/RG
PARAMETER

CONDITIONS

DIGITAL SIGNALS
I"" (OFF)
Switching Time
Between Channels

T"'I,.~TA~TMAI(

CROSSTALK
DC
60HZ

Channel = ±12V

MIN

TYP

-:,

OPA201BG/SG
MAX

MIN

TYP

OPA201CG
MAX

MIN

TYP

MAX

UNITS

20

pA

5'
-100

VaN to OFF

TEMPERATURE RANGE (omblent)
Specification
A, e, C Grades

pSe<;

130
··108

25

120

55

Operating

dB
dB

'20

·85

SGrade
55
65

Storage

,

°C
°C
°C
°C

-125

-125
"'150

NOTES:
1. 100% tested guaranteed fully warmed-up.
2. Without external adjustment. See Offset Adjustment section.
3. Over temperature specifications are -55°C ...

0.20

2.16
•. 30

PIN CONFIGURATION

3."

0.3 BASIC

M

A

.012

.32

2.548ASIC

"0",

H

-. L-

"0
02>

'"

7.628ASIC
0'
0.23
1.52
3.18
'.45

".

OFFSET
ADJUST

NC

-IN,

ORDERING INFORMATION

+IN,

=rT
OPA201

X

G

Basic Model Number
Performance Grade Code _ _ _ _ _ _ _ _ _.J

CHANNEL
SELECT

STATUS
COMMON

THRESI-:fOLD
CONTROL

-Vee

A. B, C -25°C to +85"C
S
-55°C to +125"C
Package Code _ _ _ _ _ _ _ _....;.1
G

+IN.

CHANNEL
STATUS

+V..
OUTPUT

14-pln Hermetic DIP

1-63

TYPICAL PERFORMANCE CURVES

rTA ;" +25° C, iVee ~ 1'5YDC, iiPecifications ai8 for .either chimnei {or 2 unless Qtherwiserioted.
Ao.. VS FREQUENCY
180
160

.700
,/

140
120

100

·-55°C.
+25°C

-+l~OC

80

800
1
'i:

", ,

40

o 0.001

0.1

500

0

400

~
Co

300

'""

r\..

20

!!

"

~

60

.;-

~

:::.--

±5

±15·

c

c'

o

-55°

±10

Gi

1!
o
z

_~o~

-

0

~~
~~

~

~ I"""'"

100

'"

INPUT BIAS AND OFFSET
CURRENT VS TEMPERATURE '

:::

200

lk lOOk

10

Frequency {Hz)

2

SUPPLY CURRENT VS
SUPPLY VOLTAGE

aoo

~

O~~~

-15 -14 -13 -12

±20

Supply Voltage (V)

+12 +13 +14 +15

VIN to OFF Channel (V)

CROSSTALKVS FREQUENCY

±3.2

28

±2.8_

0

±2.4£
'i:
±2.0!!

<,

6

r--..
.......

2

~

4

0
-75

1000

~
~
&:

:ci.6~" .l

.......

50 25

--

.....

I.

-

loa

-

3l
r - ±1.25
r-- ±a.s&.
'.E

±O.4

o

0 +25 +50 +75+100+125
Temperature (OC)

VOLTAGE NOISE VS FREQUENCY

I"'!Io

100

lk

10k

Frequency (Hz)

CURRENT NOISE VS FREQUENCY

LARGE SIGNAL RESPONSE

~o.ooo _ _•

lOOk

~1000._
.~

100

'0

z
8.

Z

~

,g

10

V,N

10

:;
Co

I

'i:
~

6.E:; loo,~~~It~~~tI~~tllll
Co

.E

10L-~~~~~~L-~~WW

1

10

0.1

Time (poec)

100

Frequency (Hz)

0.40

,

SLEW RATE VS TEMPERATURE

90

80

0.35

1

0.30

~ 0.25

i

SETTLING TIME VS TEMPERATURE

1

70

,

0.20 I

~ 0.15

0.10

.-

-

i""'"
~""..,.

""..,. i""'"

0.05 I

~75

~.

r;::::,Tno.OJ"

~.

60

i=

r- ToO.l '11o
50

. .'"
S:

r

~40

~ ......;;:

P===.

30
20

50 25

i
0 +25 +50 +75+100+125

Temperatu;;' (OC)

1-64

1~75-50 -25

0 +25 +50 +75+100+125

Temperature (OC)

so the channel status can be referenced to ground or --V.
The complete circuit functions as a high precision
operational amplifier which can switch between two sets
of inputs under control of'a I-bit logic signal.'

THEORY OF OPERATION
A simplfied schematic of the OPA201 Swap Amp is
shown in Figure I. The circuit has four main parts: (A)
input stage I, (B) input stage 2, (C) active load and
output amplifier, .and (D) channel select circuit. The two
precision differential input stages are identical, with
offset and drift laser-trimmed for very-tight matching.
The input stages share a balanced, high precisioll active
load and external offset adjust pins, so offset trim affects
both channels (see "Using the Swop Amp" section for
independent trim techniques). The input stages also
share a gain stage and complementary output stage. The
biasing circuits for the two input stages are well matched,
so the characteristics of the two amplifiers are very
nearly identical.

~
USING THE SWOP AMP
<
Designing with the Swop Amp is basically the same as a..
CI
designing with any precision operational amplifer, with
the added versatility of switchable inputs. Feedback is
connected from the output to each differential input to
configure each channel as an inverting or noninverting
amplifier, integrator, or other analog circuit function.
The transfer functions for channels I and 2 may be
identicaLto the point of sharing feedback elements, or
they may be completely independent. Feedback resistors
for the off channel are driven by the output as part of

CHANNEl.

STATU$

B
I
A

[CSTAI

STATUS

S
D

COIlllON

llel

.....:.....0

>---0 OUTPUT

VooAD.IUST

FIGURE I. OPA 201 Simplified Schematic.
the load resistance. Error analysisinvo1~ing Eo" IB, 10"
and Vern is the same as for any operational amplifier.
The OFF channel may be modeled as an open circuit in
most applications, with inpUt currents typically under
ISpA for input voltages within the specified commonmode range (see TypicaLPerformance Curves). Although
crosstalk' is specified for OFF channel input voltages
equal to the common-mode illput range extremes, the
same crosstalk characteristics are typically observed for
all input voltages between -Vee and (+Vec -IVDC).
Rejecti9n of signals applied to the OFF channel's inputs
is outstanding, as shown by the -120dB Crosstalk
specifications and Typical Performance Curves for crosstalk versus frequency.

Under control of the channel select circuitry. only one
input stage at a time is active. The selected input stage
controls the. output amplifier, while the unselected input
stage is turned off by deaciivating its bias circuitry. With
no current in the unselected stage, it has negligible input
bias current, and the OFF channe.! cannot send signals
to the output amplifier (see Crosstalk specifications and
Typical Performance Curves).
The channel select circuitry is, simple but versatile, alld
its use is fully described in the "Using the Swop Amp"
section. The trip point for changing channels is set by
the threshold control, pin 10. This provides TTLcompatible levels for the channel select voltage ori pin II
when pin 10 is grounded. An open collector output
transistor provides the logic inverse of the channel select
voltage at the channel status pin. The emitter of this
transistor, status common, is also brought out to a pin

CHANNEL SELECTION
Four pins are involved in the channel select logic,

1-65

providing programmable input logic levels for channel
sele.ct and an output,status indicating which channel has
been selected. Programmabl~ logic levels allow the logic.
to be referenced to grouqd or virtually any voltage,
Referencing the logic to -V is especially useful in
applications whe~e the supply'voltage is low;.f6r example
±3V. The pin-by~pin 'description and recommended
connections describe the versatile but simple' channel
select techniques (refer ·to Figures 2 and 3),
Pin 10 - Threshold Control '
Pin 10 sets the threshold voltage for channel switching,
such that the switching point is two diode drops (""'1.3V)
more positive than the T~reshold COntrol voltage. This
results in TTL 'compatibility when pin 10 is grounded.
Pin 10 must be at least 5V more negative than +Vee, and
should be tied to -Vee when" the minimum supply
voltages are used (±2.5V or +5V), This results in TTL
compatibility for logic referenced to .-Vee.
Pin 11 .. Channel Select
The voltage on pin II determines which input stage is
active. A logic high selects channel I, logic low selects
channel 2. Logic voltages are referenced to the Threshold
Control, pin 10, and are TTL., CMOS-, and open
collector-compatible,
Pin 4 - Channel Status
Channel Status is an open collector output indicating
which channel has been selected, It is the logic inverse of
the Channel Select input referenced to StatusCornmon,
pin 5. This function is not required in many applications,
and pin 4 should be left unconnected if not used. When
using Channel Status, a pullup resistor is connected
between pin 4 and a potential more positive than pin 5
(usually +V or ground). The logic low (indicatibg
channel I selected) will be less than OAV more positive
than pin 5 if the pull up resistor sets a current of ImA or
Ie,s. l.ogic high will be the voltage connected to the
pullup resistor.
Pin 5 - Status Common
Status Common sets the reference point for Channel
Status, and is usually connected to the same potential as
the Threshold Control. Pin 5 must be more negative
than pins 10 and II at all times, and should be connected
to -Vee if the Channel Status function is not used.
Status Common must be at least 5V more negative than.
+Vce.
OFFSET ADJUSTMENT
The iilput offset voltage is laser-trimmed and will not
require user-adjustment for most applications. Pins I
and 7 may be used to adjust the offset of the active
channel to 'zero (see Figure 4). This will also affect the
offset of the inactive chaimel (both offsets move in the
same direction as the pot is adjusted), This technique
may be used to make the offset for each channel equal in
magnitUde and oppo~ite"in polarity, which isdesir:able in
many applications. Besides the complementary 'nature
of the adjusted offsets, their magnitudes ;will now be less
.
than one-half of the Yo, match specification,
An inexpensive CMOSIC, CD4007 (dual-Complemen-

h66

,'.

'Vo..-.
tV"

.......

.... tV"

CHI

. Noll: uV" ... go
CGlllllClpln51D-V...

CMt

SELEetm

2.0~V,,~tV

ClWlllEL

-v"

"::o:';~"'Vcs~~~G.I:=-I-.,-i----l STATUS TIIIUIIOLD

L-_ _..J.._ _.J COIIMOII CONTROL

FIGURE 2, Channel Selection for Ground-Referenced.
Channel Select Signals.

.......

(

)

R,.o.

1110

tV",

CHI

CH2

-V"

FIGURE 3,Channel Selection for -Vee Referenced
Logic Signals.

~
-v" t

II101Ul OffSET ADJUST

FIGURE 4. Basic Offset Adjustment.
tary Pair Plus Inverter), may be used to alternately
connect dual-offset adjust potentiom<:ters (see Figure 5)
allowing independent Yo, adjustment. In this Circuit, the
.channel status output from ·the Swop Amp is used to
drive the CMOS logic, which connects one wiper or the

other to -Vee. Thus R, adjusts the offset of channel I
while R, affects the offset only when channel 2 is
selected.

When the signal channel is selected,
V out

==

Y error

+ AVVosl + AVVIN

Subtracting the "zero" Vo from signal Vo leaves a
corrected output voltage
VOU! = AVVIN + Av (Vo,' - Vo,')
= Av (VIN + AVo,)

a..

Using this technique, system errors may be reduced to
the Vo, match error (50}.! V for CG grade) of. the Swop
Amp. Obviously the channel used for zeroing could
have a voltage reference or AC waveform for gain
calibration for an input, instead of ground.
Auto-zeroing may be free-running, with the Swop Amp
functioning as a chopper, by connecting an oscillator to
the channel select. Figure 6 shows pin 10 grounded,
which allows TTL level interfacing. By programming
this pin with a voltage level, other logic levels can be
accommodated.

-vc:c
11
10

13
14

12

1

CD4G07

v~

0--+----1

SYSTEM-

"- _--"'-' GENERATED
OFFSET
ERROR

v..

-Va:

FIGURE 5. Independent

Dual~Offset

Adjustment..

Note: The CMOS logic requires -Vcc (3V minimum)
and common. The Status Common (pin 5) must be
connected to -Vee.

APPLICATIONS
The OPA201 is ideal for a variety of applications whert
a precision amplifier and switch are needed. Since the
two input stages are contained on the ,same IC and are
precision laser-trimmed, their offsets match very closely.
Therefore, the OPA201 can be used as an auto-zeroing
circuit as well as a dual-channel or switch able-gain
amplifier. It can also be extended to become a low
power 4-channel Swop Amp or dual-channel instrumen, tation amplifier under control of TTL level logic. General purpose and unique applications are only limited by
the user's imagination.
Software auto-zeroing usit:\,g the Swop Amp is easy to
perform (Figure 6). One channel processes signals and
the other channel has the input grounded (both channels
have the same gain). The system generating the error
signal may be a VFC, Iso Amp, ADC, Modulator, etc.
When the zero-input channel is selected,
Vou, = V",o, + Av Vo.'

I

V",o, = system error voltage
V",2 = Channel 2 Vo•
Av = Swop Amp voltage gain
= 1+ (R,/R I )

1-67

~

CC

FIG URE 6. Input Amplifier for Auto-Zeroing Systems.
The OPA201 requires only external resistors, to make a
dual-channel amplifier (2-channel multiplexer with gain).
Gain for either channel may be noninverting (Figure 7)
or inverting (Figure 8) with the usual operational amplifier gain equations applying in each case., In the noninverting case, feedback is connected from the oufput to
each input, with a common feedback resistor for equal
gains. The advantage, in inverting gain circuits, is that
the signal" does not produce a common-mode voltage
which can introduce error or input swing limitations.
This is especially important in low supply voltage applications where common-mode range becomes limited.
Also one channel can be noninverting and the other
inverting, which is particularly useful in absolute value
circuits. Note that in order to achieve the specified openloop gain and maximum output voltage swing, the total
output load including both feedback n.etworks should
not exceed 10kO (see Figures 7 and 8).
Amplifiers with switch able transfer functions 'are designed much like dual-channel amplifiers, except both
inputs are connected in parallel, with each chlftlnel
configured for a different transfer function. Figure 9
shows a circuit that has a gain of 10 for Channel Select
HIGH (channel I selected) and a gain of 1000 for
Channel Select LOW (channel 2 selected). In this case,
the channel select may be thought of as a gain select.

=

digital coiltrol. A wide variety of operational amplifier
function circuits may be ma.de selectable or switchable
usin.gthese techniques.
Figure 10 shows a two-channel differential amplifier.
This concept can be expanded to a full high input
impedance' instrumentation amplifier by adding four
input bUffe~ amplifiers or by using two front end Swop
Amps followed by an operational amp (Figure U).

8
Vour
AL

+~~~.--------y~------------~

A,

Av , =Av 2 = 1 ... R2/A,
A, = A. = (A, R,I
lor balance 01 bill current effects
IRL (A, - A, II ~ 10kQ lor output current raling

FIGURE 7. Selectable Input Amplifier, Noninverting.
VINI

I

~~~----~~--------~
R,

A,
Vour

A.=Ar
Re=A,

R.=A,
A,=R,

SELECT CHANNEL 2: Vo = v.. ""'"

SELECT CIWIIIEI. 1: Vo =V01I1a1R, .

FIGURE 10. Low Power Dual-Channel Differential
Amplifier.
V'1II2

Rs

A.· =-R.IR,
R, = R. R,
A., "-R,/R,
R. = R, R.
ftL lA, - A, I IR; - R,I ? IOtO

·1M2

FIGURE H. Selectable Input Amplifier, Inverting.
Vou,

V..

+1M2

-INI

Av=1+[~J

A, = 10 and 1000

FlG URE 9.

Switchab:~

FIGURE II. Low Power Dual-Channel Instrumentation Amplifier.

Gain Amplifier.

This concept also applies to switch able bandwidth cir-

cuits, where AC coupling (high-pass) or smoothing
(low-pass) characteristics need to be switched in under

1-68

BURR-BROWN®

OPA501

I EEl EEl I

-

«It)=

cr:

a..

«=

High Current - High Power
OPERATIONAL AMPLIFIER
FEATURES

APPLICATIONS

• WIDE SUPPLY RANGE
±1O to ±40 Volts
• HIGH OUTPUT CURRENT
±10 Amp. Peak

• SERVO AMPLIFIER
• MOTOR DRIVER
• ACTUATOR CONTROL
• AUDIO AMPLIFIER
• SYNCRO DRIVER

• HIGH OUTPUT POWER
260 Watts Peak

• POWER SUPPLY REGULATOR

• SMALL SIZE: TO·3 PACKAGE

DESCRIPTION
The OP A50 I is a high power operational amplifier.
Its high current output stage delivers ± IOA yet the
amplifier is unity-gain stable and it can be used in any
operational amplifier configuration. The 260W peak
output capability allows the OPA501 to drive loads
(such as motors) with a greater safety margin.
Safe operating area is fully specified and output
.current limiting is provided to protect both the
amplifier and the load from excessive current.
This hybrid Ie is housed in an 8-pin hermetic TO-3
package. The electrically-isolated package allows
direct mounting to chassis or heat sink without an
insulating washer or spacer which would increase
thermal resistance.
SIMPLIFIED CIRCUIT

Inllrnatlonal Airport Industrial Parlt· P.O. 80x 11400· Tucson. Arizona 85734· TIl. (602) 746-1111· Twx: 911).952·1111· Cable: 88RCORp· Telex: 66-6491.

1-69

SPECIFICATIONS
ELECTRICAL
At Tc =,+25·0 a'nd ±Vcc,. 28VDC (OPAS01AM/AM); ±Vcc = 34VDC (OPAS01SM/BM) unless otherwise.hoted.

OPA501SMIBM

OPA501RM1AM
CONDITIONS

MIN

Output Current, .

AL=2!lIAM/AMI

Continuous(3)

Rc = 2M (SMIBMI

Output Voltage(3)

10= 10A peak

±10
±10
±2O

PARAMElER

MAX

TYP

TYP

MIN

MAl'

,UNITS

RAlED OUTPUTi1H2)

±26

23

±29

DYNAMIC RESPONSE
Bandwidth, Unity Gain
Full Power Bandwidth
SlewAate

Small Signal
Vo = 40Vp-p, AL = 80
AL=50IAM/AM)
AL =6.50 ISMlBM)

10'
1.5
1.5 '

1
16

A
A
V

.

"

MHz
. kHz
Vlpsec.
V/psec

INPUT OFFSET VOLTAGE
I nitial Offset

vs Temperature

±5

-2500 < T< +8500 (AM/BM)
-55·C < T < +125·C (RMlSM)

±10

VB

T calie = +25·C

Supply Voltage

INPUT DIFFERENCE
CURRENT
Initial·
vs Temperature
OPEN-LOOP GAIN, DC

±2

±5

±10

±4O

mV
pVl·C
pVl·C

pVN

±35

vs Supply Voltage

INPUT 81AS CURRENT
Initial
vs Temperature

.,

±10
±65

Tease = +25· C
-2500 < T< +8500 (AM/8M)
-55·C  CASE

BCS
TS .....

>HEAT SINK

BaA
TA~

FiGURE I. Proper Power Supply Connections.
Note that the connections are such that the load curent does
not flow through the wire connecting the signal ground
point to the power supply common. Also, power supply and
load leads should be run physically separated from the
amplifier input and signal leads.
The amplifier should be power-supply-bypassed with
IO"F tantalum capacitors connected as close to pins 3
and 6 as possible. The capacitors should be connected to
the load ground rather than the signal ground.
CURRENT LIMITS

The OPA501 amplifier is designed so that both the positive
and negative load current limits can be set independently
with external resistors R+sc and R-sc respectively. The
approximate value of these resistors is given by the
equation:
Rsc = (0.65 _ 0.0437\ ohms
\; ILIMIT
)
lLlMIT is the desired maximum current in amperes. The
power dissipation of the current limit resistor is:
Pmax = Rsc (ILlMIT)' watts
Rsc is in ohms and ILl MIT is in amperes.
Current limit resistors carry the full amplifier output current
so lead lengths should be minimized. Highly inductive
resistors can cause loop instability. Variation in ILIMIT with
case temperature is shown in the Typical Performance
Curves.
The amplifier should be used with as Iowa current limit as
possible for its particular application. This will minimize the
chance of damaging the amplifier under abnormal load

AMBIENT

FIGURE 2. Simplified Steady-State Heat Flow Model,.
Junction temperature (TI) is found from the equation:
TI = Po ({hc + Ocs + OSA) + T A
Where Po = average amplifier power dissipation (W)
OIC = junction to case thermal resistance \C/W)
Ocs = device mounting thermal resistance
\C/W)
OSA = heat sink thermal resistance \C/ W)
T A = ambient temperature \C)
For most heat sink calculations the quiescent power
dissipation is very low «I watt) and can be disregarded
with only a small error.
The minimum size heat sink can be found from the
equation:
TI -TA
OSA = - - - - Ocs - OIC
Po
Example: Find the maximum thermal resistance (smallest
heat sink) that can be used for an OPA501 with ±Vcc =
28VDC. Output voltage is + IOVDC across a IOn resistor
and ambient temperature is +50"C:
Po

= [(+28VDC) - (+IOVDC)] X

.

200"C - 50°C

0

+IOVDC

Ion

= 18W

•

- 0.1 C/W - 2.2°C/W
18W
OSA= 6.03°C/W maximum
OSA =

As large a heat sink as possible should be used. Ocs depends
on the flatness of the heat sink, the thermal compound used,
and the roughness of the mating surfaces.
Typical values are between 0.1° C/ Wand 0.3° C/ W for a
TO-3 package properly mounted on a heat sink.

1-73

reliability. In this case, Ii lQ~r tVec couId be us,ed to redpce
dissipation.
At lower frequencies, the junction temperature can show
greater modulati'On as the. output power transistor'dissipation increases and decreases with output voltage and
current swing., To ,ensure thl\t the ml\ximum junction
temperature is not exceeded, use the appropriate value of
effective 8JC from Figure,3 .
To illustrate the importance of considering frequency,
consider the· previous example, but with the amplifier
operating at 60Hz:
For a 60Hz output
the effective 8Jc=0.72 X rated 8Jc= I.SsoC/W
TJ =SS.97W( l.5soC/W+ 0.1° C/W +0.4°C/W)+2SoC
TJ=204°C: UNACCEPTABLE

The OPASOI mounting flange is electrically-isolated and
can be mounted directly to a heat sink without insulating
washers or spacers. Screws with Bellville spring washers are
recommended to maintain positive clamping pr,essure on
heat sink mounting surfaces. Long periods of thermal
cycling can loosen mounting screws and increase 8cs.
The Olltput transistor thermal resislilnce (OJe) is a function'
. of output current pulse width, pulse shape, and duty cycle.
Long duration pulses allow the junction temperature
to approach its steady state vallie while shorter pulses cause
lower peak junction temperature due to the junction's
thermal time constant. Heat is conducted rapidly away
from the junction so that as duty cycle deaeases, junction "
temperature decr,eases.
Steady state 8JC is rated at2.2°C/W maximum. In applications where the amplifier's output current alternates
between output transistors-for example, an AC amplifierthe transistor 8JC will depend on frequency as shown in
Figure 3.

a

NOTE: Maximum dissipation does.!!2! occur at .
maximum output.,
SAFE OPERATING AREA (SOA)

In addition to the limits imposed by power dissipation,
the amplifier's output transistorS are also limited by a
second breakdown re8ion. This occurs because of increased emitter current density due to current crowding
at higher operating voltages. Both the dissipation and
second breakdown .limits depend on time and temper-'
ature. Figure 4 shows each output transistor's SOA at a
case temperature of +2S°C.

DUTY CYCLE =0.5 FOR EACH TRANSISTOR
12

1.0

~

0.8

iii

OJ!

,i

OA

§

~

ri""

0.2
10

o
0.1

10

100

Ik

MAXIMUM SPECIFIED I f l\.
"-r.~
CURRENT
,.
l\.
' ~,~

II

10k

8

FREQUENCY IHzl

POWER."- " 01S81~AJr 't...O'
.,

4

FIGURE 3. Effective 8JC for Applications Where Output
Current Alternates Between Output Trans"
istprs.

s:
............z
...
!:;
......

lIr

2

f--- TCASE =+25"C
0.8 f- TJUNCTION =+2OO°C
0.6 f--- 6JC =2.2°C/W

=> 1.0

Example: OPASOISM with '±Vee = 28VDC; heat sink
8SA = O.4°C/W; output = 11.2VAC, rms
400Hz at SA, rms;i Power Factor = 1.0;
assume a mounting resistance of O.J°C/W
and an ambient temperature of +2SoC.
Peak output voltage is: (l1.2V, rms)
= IS.s4v,pk
Peak voltage across each output transisto~ is:
2SV - IS.84V = l2.16V, pk
'"
,
Peak output current is: (SA, rms) JT= 7.07A, pk
Peak power dissipated by each output transistor is:
(12.l6V, pk) (7.07A, pk) (1.0) = 8S.97W, pk
From Figure 3, the effective value of 8JC is 0.60 X rated
thc, therefore,
8JC = l.32°C/W for this example.
The peak junction temperature will be:
TJ = 8S.97W(1.32°C/W + O.\oC/W + O,4°C/W)
+2SoC
.
TJ = IS1.5°C/W
This is below the maximumjunctiQn temperature limits of
+200"C, but a lower TJ will increase the ,amplifier's,

=>
co

K

SE~O~O BREAKDOWN '"
LIMIT It

~~\'~i

~\ "

,

-"

-.l

D.4

0.2

MAXlMU~} RM/AM"

V2

SPECIFIED
VOLTAGE

0.1,
1

2

4

8 8 10

20

' I
8M/BM 1
40 60 60 100

VOLTAGE ACROSS OUTPUT TRAHSISTOR (V)

FIGURE 4. Transistor Safe Operating Area at +2SoC
Case Temperature.

Limits for short pul~e widths are substantially greater
than for steady s~te (DC). At a ca~e temperature of
+ 12SoC the SOA limits are reduced (see Figure S). The
SOA shown in these curves is base~ton a conservative
lineard~rating of both the power dissipation and the
second breakdown region.

1-74

'~t\ MAXIMUM
I "'
B -SPECIFIED
CURRENT

4

"

2

is
~

TCASE = +'25·C
~ 1.0 TJUNCTION = +2OO"C
::::0 0.8 -8JC= UOCIW
u
z

...
...5
5...

I\. ,\!~

'"

Q.2

MAXIMUM
SPECIFIED
VOLTAGE
2

4

I-

iI 8:10

"' l\I'".,
1\~,
\

0.4

1

This set up can also display voltage and current stress
across the OPASO I output transistors as shown in Figure
7. This data can then be compared to the SOA limits.
The amplifier is designed to operate with electromotive- _
force-generating loads such as servomotors, relays, and
actuators. Carefulattenti(Jn must be paid to both the load ~
characteristics and the amplifier's SOA to ensure safe
operation.

'-

:a

\t"'~'" ~\
, l\ ~
~"

0.8

0.1

\

"""~~~~,,~

~

PM/A~~
8M/8M

20

40

=

I

+VCC

~

TEST
SIGNAL o-"N\~
IN

601801100

VOLTAGE ACROSS OUTPUT TRANSISTOR (VI,

FIGURE S. Transistor Safe Operating Area at +125'C
Case Temperat'ure.
Resistive loads are easy to analyze by simply plotting
load lines on the SOA curve. If the curve representing the
load line stays within the OP ASO I output transistor SOA
curve and all other parameters are observed, such as case
temperature, etc., the amplifier will be safe. The load line
can swing through the larger SOA limits if their time
duration constraints are strictly observed.
Reactive loads present a more complex problem since the
output voltage and current are not in phase. This results
in the reactive load line becoming elliptical (when plotted
on linear axes) which requires a larger SOA for safe
operation.
Although detailed analysis is beyond the scope of this
data sheet, the load line can be viewed on an oscilloscope
as shown in Figure 6. The X-V display is driven by the
voltage across the load and by the current into the load.

'BOTH LEADS OF HORIZONTAL
AND VERTICAL INPUTS MUST
FLOAT WITH RESPECT TO EACH OTHER

FIGURE 7. Output Transistor Safe Operating Area
Stress Display.
Figure 8 shows ihe OP ASO I configured as a DC permanent magnet motor driver. The armature current (IA) and
motor voltage (Vm) are monitored within an oscilloscope
in the X-Y mode displaying h and Von respectively.
Slewing the motor with a 4Hz sine wave results in the
motor power ellipse of Figure 9. The input level has been
adjusted to give ±20V, pk, across the motor. An examination of the power ellipse indicates that the instan-'

+VCC

TEST
SIGIIAL o-'-N<.......
III

PMI UI2M4T
SERVOMOTOR

.VCC
'BOTH LEADS OF HORIZONTAL
AND VERTICAL INPUTS MUST
FLOAT WITH RESPECT TO EACH OTHER

·28VDC

FIGURE 6. Loadline Display.

FIGURE 8. Servomotor Amplifier.

1-75

,

"

-II

INSTAN, INSTAfI,
TANEOUS TANEOUI
POWER AMPLIFIER
TO
POWER
AMOTOR OI88IPAnON

Y-A

'v·,
o
811

180
192
193

Inductiveloads should be investigated for high peak
transients generated by a collapsing magnetic field ..
Resistive damping can reducethis problem and although
the amplifiet has substrate diodes as pari of the Darlington
output transistor structure, external diodes are recommell:ded fo~ h'eavy clamping.
Fast diodes such as those normally used as rectifiers in
switching power supplies are suitable.

138
80
32
18

o

+10

+5
A

o
-Ii

FIGURE 9. D.C. Servomotor Load Line,

·10

taneous power delivered to the motor exceeds the
amplifier output transistor's safe operating area at a case
temperature of +250 C. The point at which the motor
shows OV at ·6.9A is a problem. The voltage across the
output transistor is 28V - OV = 28V. Checking the SOA
curve shows that the amplifier can safely withstand this
condition for slightly under 5msec. At 4Hz· this transient
swing outside the DC SOA region is exceeded for much
longer than 5msec.. Continued operation under these
conditions ,will result in failure: Peak junction temperatures should riot exceed +2000 C. Perhaps a motor with a
higher impedance winding should be considered for this
application. Current limiting and lower supply voltage
can also reduce dissipation.
Motors used in servo applications often required a
surprisingly large current to accelerate quickly. Wont
case conditions occur when the motor is operating at full
speed and is suddenly slammed into reverse ("plugging") .
. This condition is illustrated in Figure 10 when a DC
servomotor is driven by a bipolar square wave. As the
motC!r reverses direction a large surge current flows,
causing very high peak power dissipation in the amplifier.
After several time constants (determined by the inertia
moment) the current drops to a lower steady-state value.
Loading the motor increases the motor average power
and amplifier dissipation, SOA curves should be checked
for safe operation under these surge conditions.
The OPA50l current limits may be set to clip the hil!h
surge currents to a, safe level This is ~hown in Figure II.
Note that the current. limit does limit the servo motor
peak acceleration.

+10

·10

"MIUI2M4T MOTOR•.
I " 4Hz. SQ.UAIIE WAVE

±VCC 1!!2SV. 1c=25" '
Av =+10

FIGURE 10. Servomotor Drive - "Plugging"

+5
A 0

+10

v 0
·10

1'1111 UI2M4TMOTOR. NO LOAD
I =4~z. SOUARE WAVE

±VCC = 28VOC. ±RSC= O.l5n
TC =25". ~V =+10

FIGURE lIt Servomotor Drive'withCurrent Limit.

1-76

BURR-BROWN®

OPA605

IElElI

§
C

a..

=

Wideband - Fast Settling
OPERATIONAL AMPLIFIER
FEATURES

APPLICATIONS

• FAST SETTLING - 500nsec max to 0.1%
• WIDE BANDWIDTH -200M Hz Gain -Bandwidth Product

• PULSE AMPLIFIERS

• FAST SLEWING - 300vI /llec slew rate. ACL ;;;. 50

• LINE DRIVERS

• LARGE OUTPUT CURRENT - ±30mA min at ±lOV

• WAVEFORM GENERATORS

• HIGH GAIN - BOdB min at ±30mA output

• HIGH SPEED TEST EQUIPMENT

• FAST.D/A CONVERTERS

• LOW VOLTAGE OFFSET AND DRIFT - 5OO/lV max.
5/lV/oCmax

DESCRIPTION
The OPA605 is designed to offer a well balanced set
of hoth AC and DC specifications. Versatility in fast
settling. wideband and steady state AC applications
is provided by the use of a single external compensation-capacitor. This allows the user to optimize
speed and stability for any particular application.
The full ±30mA guaranteed minimum output current
(at ±IOV) allows the user to realize the high speed
features of the OPA605. Unlike most integrated
circuit wideband amplifiers additional current boost-

er circuitry is not needed for most applications.
The 500nsec max toO.I\:i settling time specification is
guaranteed with a load of 500n and IOOpF. Also the
open-loop gain is guaranteed at the full ±30mA
output.
In addition to the excellent wideband and fast settling
. characteristics. the OPA605 also offers llutstanding
DC performance. Offset voltages are as low as 500/l V
max and offset voltage drift versus temperature of
only 5/lV "c max is available.

International Airpart Industrial Park· P.O. 80x 11400· Tucson. Arizona 85734 . Tel. (6021 746·1111 . Twx: 910·952·1111 . Cable: 88RCORP . Telex: 66·6491

1-77

$PECIFICATIONS
ELECTRICAL

-

-

SpecificaUtins at TA = +25°C and +Vcc = +t5VDC unless'otherwise noted
MODEL

I

PARAMETER

CONDITION

I OPA60SGH(OPA605AMI OPA60SKGiOPA60SCM+
.I.MIN L TVP 1 MAX J MIN I. Tvp.1 MAl(

,'.

...
uNmi'

OPEN-LOOP GAIN, DC
Vo -±10V; RL 33011
Vo = ±10V; RL .. lO! 1.0

....

\~

U

X

Tj=TA+POX 161 +8,2+8CAI

r- 1

..: 40
II

,g

At PARAMETERS
VS TEMPERATURE

POWER DERATING
2.0.---'--,---.,---,--..,

COMMON-MODE REJECTION
VS FREQUENCY

OPEN'LOOP PHASE SHIFT
VS FREQUENCY

Iii

120

~'00

~

8 60
-7 40

!

.....

.......

.~ 60
C)

Cc = 20pF

~

Cc ,0pF

,

5P

c

'J
""-

20

o

, ~\,

o
45

~
.~

120

c

,

C~=OPF

\

Cc

i\.

,2O

,

PF

\

Cc = 20pF

100

180

\

.~

"If"
0

60

c

40

0

U

0

"

,10100 lk 10k. lOOk 1M 10M 100M
~requen..

60

til

i

~

ACL '" +lVIV. Cc = 40pF

,

100

'£
8:

RL = 500n. CL = l00pF

:g

R

.5

~OJ

E

102

~ 103

o

,"

80

E

<:0

/

60

U

T. = +25°C

50
-15 -10
-5
0
5
10
Common-mode Voltage

Common-mqde volt~~e r V I

Gi 60

U

15

20

1:"80

6is po~er lu~n on

I

Ceramic Case

'"
o·

'.'"c"
.r:

Supply Vollag~. ±Vcc 'V,

/.

I=

80

.S 40

10

15

OFFSET VOLTAGE VS TIME

:0:.

6. 5

t

'\

0

>

" 6. 0
.0

+10

,

70

E
E

~

'.~

+5

90

-rl0

(5

TA= +85°C

5

~
~

o

c::"

.

-T.=-25°C

~ 7. 0

V
-5

'iii'

~100

7. 5

+,

/

-10

, ,"-

20

S}

I"'"

0

±Vcc = ±15V

QUIESCENT CURRENT VS
SUPPL Y VOLTAGE

-<§

1. 0

....... -PSR
~ "-

I

O. 1

U

110

.2 100
U

10 100 lk 10k l{)Ok 1M 10M 100M
Frequency r Hz

c
m

'

40

200 400 600 600 1000 1200
Time nse.c

"
c

+PSR

BIAS CURRENT VS
COMMON-MODE VOLTAGE

~

Iii

120

20

./

\

\

I

I
ye\al Case

~~
.'

3

Time (mint

4

APPLICATION INFORMATION
SLEW RATE
This is characterized as I fJ. where fJ is the "feedhack
factor". I fJ is also equal to the gain in noninverting
C
configurations (see I'igures 2 and 3).
a..

§

Slew rate is a large signal output parameter. It is primarily
dependent on the compensation capacitor value (Cd and
has almost no dependence on changes in the closed loop
gain or bandwidth. Typical values of slew rate versus
compensation capacitor value are shown in the Typical
Performance Curves. Decreasing the compensation capacitance increases the slew rate but reduces'the frequency
stability of the closed-loop circuit. Stray circuit capacitances may appear as added compensation to the amplifier. Therefore. stray capacitances should be minimizcd to
avoid limiting slew rate performance.

=

11--"""'---+ Your
1611

BANDWIDTH
The closed-loop bandwidth is a small signal parameter. It
is dependent on the open-loop frequency response of the
op amp (which is determined by the value of the
compensation capacitor. Cd and the external closed-loop
circuitry applied to the amplifier. RC'quirements for
increased bandwidth and more frequency stability result
in opposing constraints on the circuitry and generally the
final selection of circuit value~ represents a compromise
between the two needs.

FIGURE I. Unity Gain Follower.

Hi
lKll

l)-oM....... Vour

SETTLING TIME
Settling time is defined as the total timc required.
measured from the input signal step. for the output to
settle to within the specified error band around the final
value. The error band is expressed as a percent of the full
scale output yoltage (IOV) and the output transition is
from OV to + IOV or OV to -IOV.
Settling time depend$ on slew rate (discussed above) and
the time to reach the final value after the slew portion of
thc transition is complete. The latter is a function of the
closed-loop bandwidth (discussed above) and the closedloop gain. Thus. scttling time is a function of both the
opcn-Ioop frequency compensation (value of C·) and the
particular closed-loop circuit configuration. The best
scttling time is generally obtained at low gains.

lS11

1 H, + A,
-=--=2
iJ
Ai

FIGURE 2. Unity Gain Inverting.
A, = lOOn

A, =900n

1
A,. AI
- =--=10
fl
Hi

COMPENSATION
The OPA605 uses external frequency compensation
which allows the user to optimil.e slew rate. bandwidth
and settling time for a particular application. As mentioned previously. compensation is normally a compromise between the desired speed and the necessary
frequency stability - the higher the speed the lower the
value of C" and the less stable the circuit. Several of the
Typical Performance Curves provide information to aid
in the selection of the correct value of compensation
capacitor. In addition. several typical circuits show
recommended compensation in different applications.

1)-"""'.......

lSn

Your

FIGURE 3. Gain of +IOV.
The OPA605 may be compensated in either one of two
ways. In the primary compensation method. C is connected between pins 10 and 12. Alternately the amplifier
may be compensated with C' betwcen pins 12 and 2 (see
Connection Diagram). Normally the usc of C is recommended. The. use of C e' will give lower output impedance
at higher frequencies. This can be an advantage in some
applications. but the effects are subtle and must be
determined empirically.
Improved stability with larger capacitive loads may be
obtained by connecting a small resistor (a value of 1611 is
recommended) in serics with the output (see figures 2
through 4).

The value of compensation capacitor required for stability
is a function of the amount of negative feedback used in
the particular application.

1-81

Flat high frequency closed-loop frequency response mily
be preserved and any high frequency peaking reduced by
connecting a small capacitor (C, in the examples) in
paralll,1 with the feedback resistor. This capacitor will
compensate for the high frequency c1osed"loop transfer
function zero form~d by the-capacitance at the amplifier's
input and the input and feedback resistors. C, may I)e a
trimmer capacitor, a fixed capacitor or a planned printed
circuit board capacitance: Typical values range from OpF
to 5pF.
.

WIRING PRECAUTIONS
Of all the wiring precautions, grounding is the most
important. A good ground plane and good grounding
practices should be used. The ground plane should
connect all areas of the pattern side of the printed circuit
board that are not otherwise used. The ground plane
provides a low resistance. low inductance common retUrn
path for all signal and power returns.
If point-to-point wiring is used (no ground plane). single
point grounding should be used. The input signal return.
the load signal return ahd the power supply common
should ail ,be connected at the same physical point. This
will eliminate any common current paths or ground loops
which 'coul,d cause signal modulation or unwanted
feedback.
Each power supply lead should be bypassed to ground as
near as possible to the amplifier pins.
All printed circuit board conductors should be wide to
provide low resistance, low inductance connections. and
should be as short as possible. In general. the entirc
physical circuit should be as small as practical. Stray
capacitance should be minimized especially at high
impedance nodes. Pin 4. the inverting input is especially
sensitive to capacitance and all connections to that point
must be short.

Inpllt"and feedhllck resistors should be kept 'as small in
value as practical; values less than 5.6kH are recommended. This will minimize performance limitations
caused by the time constants formed by these resistors
,and circuit capacitances.

Ylew

FIGURE 5. Dynamic Test Circuit Layout.

SHORT CIRCUIT PROTECTION
Short circuit protection to common is provided by
internal current limiting resistors. (Output shorts to either
supply can destroy the device.) The current limits may be
increased by paralleling the internal resistors with external
resistors. REXT connected between, pins 7 and 10 and pins
8 and 10. The short-circuit current is then Is(" 0.05 +
0.6; R,:xT (in amps). The power derating constraints must
be observed when modifying the currenf limits. Details
ate given by tne thermal model.

=

, THERMAL MODEL
Figure 6 is the thermal model for the OPA605where:
= Junction temperature (output load)
;;:: Junction temperature (no load)

TJ
TJ*
Tt

;;::

TA
6( A

Error Signal. "S"
,---.,...- ±5mY for YOUT
R4 Ikll within ±D.I% of lOY.

.

Case temperature

= Ambient temperature
= Thermal resistance, case-lo-ambient

PDQ

= Quiescent power dissipation
I+V('('II+QUIESCENl +1-Vn:!I-QIIIESCENT

Pnx

::::: Power dissipation in the output transistor
::::: (VOl'1 - Vn :) lot:'1

(In a complementary output stage only one output
transistor is conducting current at a time.)

121
R
5

"0"
(31 Y

+YCC ·YCC
NOTES:
I. Fast rac:avery diode•• HP508Z·Z81,.
Z. R5 optional. Impl1lvea frequlnCY stability whln driving large
.c~p"ltlve load•.
3. Resistive laid at YOUT I. 50011 due to IKfeedback realstorl.
4. Not Included on pilnll,d circuit layout.

°CA L..=-':=--!_-'-"-'=:":'--...J
TJ =TA + PDO loZ+8CAI + POX 181'+~ +8CAI

FIGURE 6. Thermal Model.
This 'model yi~lds a Power Derating curve which is a
function of P UQ • See Typical Performance Curves.

FIGURE 4. DynamicTest Circuit.

1-82

3271/25

BURR - BROWN ®

IElElI

High Voltage - Chopper-stabilized
OPERATIO·NAL AMPLIFIERS
response. with low overshoot, and low phase shift,
when the 3271/25 is used as an inverter or summing
amplifier.

FEATURES
• LOW DRIFT
• OPERATES OVER WIDE SUPPLY RANGE

APPLICATIONS

• HIGH OUTPUT VOLTAGE UP TO 110V
• SMALL. ENCAPSULATED PACKAGE
• ALL SollD·STATE DESIGN

DESCRIPTION
The Model 3271/25 is a high voltage, chopper·
, stabilized' operational amplifier in a small,
encapsulated package. The module can be soldered
directly on a circuit board, or may be plugged into a
1500MC connector for chassis mounting. The epoxy
encapsulation insures ruggedness and resistance to
environmental stresses, while the all-solid·state
design, including self-contained MOSFET chopper
and driver, guara'ntees reliable operation.
The amplifier is designed for operation on external
supplies ranging anywhere from ±60VOC to
±120VOC. Output voltage range depends on the
supply. voltages. A low-noise chopping technique
insures ultra-low OC drift as a function of
temperature and time, while eliminating the noise
spikes usually associated with chopper amplifiers.
The 3271/25 has input protection up to the value of
supply voltage. The output stage may be shorted to
common without damage to the amplifier. These
features are particularly desirable when the amplifier
is used in a patchable simulator.

Typical areas of application for the 3271/25 are:
integrators, summing amplifiers, inverters, sample/
hold units, 0/ A converters, precision function
generation, data amplifiers, a ,Id OC preamplifiers.
The wide supply voltage tolerance and stable design
enable the 3271/25 to be used' as a replacement for
vacuum tube amplifiers and older, solid-state
amplifiers in simulators, data acquisition systems,
and other systems where it is desired to increase
reliability and improve performance at modest cost.
Because of the rugged construction techniques and
use of silicon semiconductors, the 3271/25 is not
limited to laboratory applications, but may also be
used in relatively severe environments. Examples are
shipboard, airborne, high vibration industrial, and
remote monitoring stations.

The open-loop gain exhibits a high frequency rolloff
of approximately 6dB/ octave, which insures stability
at all feedback gain levels, or when driving capacitive
loads. At tne same time, the fast slewing rate and
relatively wide bandwidth guarantee fast step

MOOEl3271/25 ENCAPSULATEO PACKAGE

'i.-

1.80'" maJI,

NOTE:

(45.8) ,

Dimen8ion5 in millimeters ~appe~~40 •. W Deep

arc shown in parenthescs.

T:~~" D:::~~e Holc1

PIN CONNECTIONS
Pin I
Pin 2
Pin4

,+,
,-,

Pin 3
Pin S

loverdn, Signal Input
Common

,

Sianal Output
Positive Power
Negative Power
External Zero Control
Overload Signal

MATERIAL
Case - Black Epoxy
Pin~ - Gold-Flashed
Hcader - Alum., Hard Black
Anodized
MatingConneclor
Model 1500MC

InternaliOftal Airport Industrial Park· P.O. Box 11400 - Tucson. Arizona 85734· Tel. 1602) 746·1111· Twx: 910-952·1111· Cable: BBRCORp· Tilex: 66·8491

1-83

SPECIFICATIONS

DC

• See diicudiem of Oulput characterilfticl below,
Operating Temperature Range,-25OC to+8SOC;Storage ·SSOC to+IOOOC.

Performance at 2SOC and + 120 VDC supply unless otherwise noted

MODEL

IANpWlQTH SLEW
RATED
OUTPUT IIA1N
RATE
VO

Volts
min

10

mA
min

Unity
Galn

dB MHz
min" min

. INPUT OFFSET VOLTAGE
Over
At
+25"C Range
·25"C
to
8S"C

full
Power

Venus v......
Tc:;mp.

Versus
.TI~

..,".'

kHz

V/#.

min

min

.V
max

max

.V/Oe
max

30'

20

±SO

:til 0

1.0

#V

Sup~ll

INPUT BIAS CUIIRENT

#V/V·
max:: ~.

INPUT OPEN LOOP
NOISE IMPEDANCES

[<>vet

\;ersus Versus 10/1;£' Input oUtput

·25"C
.
to
85"C

100Iz

.~~ Range

#Vlmo

pA
pA
typ . max max

POWER SUPPLY
QuIe••

Ranp

Temp. Supply 'to

., Current
"

pAj"C
max

pA/V , IlVnns MI1
max max
typ

typ

tlO

2S

kI1

Volo

rnA

max

3271/25 Supply
I,..
tlOV

t,20 140 1.0

+1

1.0

Input Ripple
Supply Ripple

mV

IV j

.

Positive Supply
10

100

2S
0.5
100'yp)

i60totl2(

,.,."

'1;2OmA
(i't12OVllC

•

close as possible'to the amplifier pins. The common lead
shoulc:\ be as short as possible. Heavy gauge bus wire
should be used if long· sl/pply and common leads are
. necessary. The addition of bypass capacitors from the
supply bus to common, at the amplifier pins, will reduce
the equivalent supply irnpedan£e and may be required if
supply leads are long. Figure 2 illustrates the ripple
induced at the amplifier input as a result of supply ripple.

N_~

lK

Ripple Frequency (Hz)
FIGURE 1. Open Loop
Gain VS. Frequency.

1:2

.

OPEN-LOOP RESPONSE
. The DC gain of the amplifier is typically l60dB because
of the additional gain contributed by the DC chopper
channel. This chopper channel gain rolls off at very-low
frequency after which the; amplifier gllin is determined by
the AC channel. The high frequency gain decreases at
very nearly 6dB / octave. Figure I illustrates the openloop gain response of a typical unit.

Frequency (Hz)

:!80 t200

FIGURE 2. Supply Rlpple
Rejection vs. Frequency.

OUTPl,ITCHARACTERISTICS
The output stage of the amplifier is a balanced class B
design which insures Ii minimum of quiescent drain from
the power supply. The·output current rating is +2OmA
and -20mA, regardless ofthe power supply level. Rated
output voltage swing in either direction is IOV less than
the supply voltage ofthe same polarity, whether equal or
unequal values of supply voltage are used. For example,
supply voltages of +75VDC and· -90VDC could
legitimately be used. Tne output voltage rated swing in
the positive direction would be +(75-10) =+65V, while
the negative rated output voltage would be -(90-10) =
-80V. Full power frequency is measured with ±IOOV
swing and ±20mA of output Current, on ±120VDC
supplies.
.
POWER SUPPLY CONSIDERATIONS
The 3271 /25 will operate quite satisfactorily over a range
of power supply voltages froq1 ±60VDC to ±120VDC. In
addition the supplies may have unequal values, so Icing as
each is between 60V and 120V. Amplifier noise and drift
will be minimized if the power supplies are balanced, well
regulated, and have low output ripple. High frequency
performimce will be best, and crosstalk between adjacent
amplifier channels will be least, if the supply impedance
at the amplifier pins is low at all frequencies from DC to
above 100kHz. If the supplies incorporate provisions for
remote voltage .s~ing, the' sense lc:ads shoul!!. be
connected to the positive and negative supply buses ~

1-84

INSTALLATION RECOMMENDATIO'NS
The input iead to theampiifier summing junction shouid
be shielded to avoid pickup of spurious signals;
particularly signals at the .chopper drive. frequency of
100Hz. In integrator application.s, a shielded wire may be
used to connect the feedback or' integrating capacitor to
the amplifier input terminals.. The center conductor
should be connected to the amplifier' input, while the
shield is connected to the amplifier output. The lead
employed should have high insulation resistance to
prevent capacitor discharge.
OFFSET VOLTAGE ZERO CONTROL
The Model 3271/25 operates with low DC input offset
voltage, without the use of a zero control. An optional
external zerO control may be employed to accurately null
the amplifier offset. This control is shown in the package
drawing.
EXTERNAL OVERLOAD INDICATOR
Electrical overload signals may be detected in the
chopper stabilizing channel and applied through pin 5 to
an external overload indit!ating circuit. In the suggested
circuit of Figure 3, D I and D2 are silicon diodes; Q I is all
NPN silicon switching transistor while Q2 isa PNP
silicon switch. Lamp DS I is a IOV, 15mA indicator, O.E.
#01869 or equivalent. The circuit may be adapted for
latching operation by includillg the lOOkfl resistor and
the reset switch shown in dotted lines. The indicator will
then remain lighted, after the amplifier comes out of
satura:tion, until the reset switch is closed.

Commono-----~-+--~--~-J

FIGURE 3. Overload,.Indicating Circuit.

1-85

3291
3292
3293
3354
3355
3356

BURR-BROWN~

IElElI

Chopper-Stabilized
OPERATIONAL AMPLIFIERS

FEATURES
• D!FFERENTIAl INPUT OR SINGLE-ENDED
• VOLTAGE DRIFT AS lOW AS O.1I1V laC

r

• CURRENT DRIFT AS lOW AS O.5pA/oC

I
I
I

I

I~~,7e~ass ":"

'-

C

'

_.

- -CHOPPER CHANNEL
- - - -

FIGURE I. Single-ended Chopper-stablized
Amplifier.

DESCRIPTION
The great strength of the chopper-stabilized
• amplifier is its insensitivity to component changes
due to aging, temperature change, power supply
variation or other environmental factors. Thus it is
usually the best choice where both offset voltage and
bias current must be small over long periods of time,
or under significant environmental changes, and
where external adjustment of offset~ is undersirable
or impossible. Both bias current and offset voltage
can be nulled, if desired, by optional external
controls. Figure I shows a simplified diagram of a
single-ended chopper-stabilized op amp. Since the
chopper channel, including switches and switchdriving oscillator, is built into the amplifier, only the
DC power is supplied externally.

Chopper-stabilized amplifiers achieve their ultra-I!>w
DC offset voltage and bias current by"chopping" the
low frequency comporient of the input signal,
amplifying this chopped signal in an AC amplifier
and then demodulating the output of the AC
amplifier. This output is then further amplified in a
second'stage of DC amplification. High frequency
signals, which are filtered out at the input of the
chopper channel, are coupled directly into the second
stage amplifier. The net result of this technique is to
reduce the DC offsets and drift of the second
amplifier by a factor equal to the gain ofthe chopper
channeJ. The AC amplifier introduces no offsets.
Minor offsets and bias CUrrents exist due to imperfect
chopping, but these are extremely small.

International Alrportlnduslrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. (6021746·1111 . Twx: 911J.952·1111 . Cable: BBRCORp· Telex: 66·6491

1-86

MECHANICAL SPECIFICATIONS
NOTE'
Leads in true position WIthin .015"

NOTE:
Leads in true posrtion within .015"
(.38mm) R @ MMC a~ seeting plane.

(.38mm) A @ MMC at seating plene.

rfB=J

r-A~

JJ

OJ
CI

L ! I
c- JLo
L
r

L-"'dr-"'urTl---'

U

r:;--;;--L J /-G

Pm numbers shown lor referenclli only.
~~

may n~be marked on package.

L_jl+~'~
++

r - '.
G

-';;'1

~~

t2+~-+i'

2 pillees In true position wlth'n .015"

(.38mmlRO>MMC.

o::!'L-J
+v-oL .2 o~'n-tG
-lL ~
.1

INCHES

MAX

MILLIMETERS
MIN
MAX

MIN

MAX

MIN

MAX

2.350

69.69

61,21

A

1.450

1.510

36.83

38.35

1.750

1.810

44.45

45.97

8

1.450

1.510

36.83

38.35

15.49
1.14

C
0

.350

.410

8.89

10.41

.088

.042

0.97

1:D7

.550

610

13.97

0

.035

.045

0.89

.

.300 BASIC

U

","d.no'"m""ngpin.

11

2.410

C

G

L

msy 1'101 be marked on package.

MIN

INCHES

DlM

~

4-40 thread, ,150" (3.81mml min. depth,

L~

-.l

·Pin numbers shown for reference ohlv. Numbers

H iA

.550

.650

.170

.210

.600 BASIC

.550
.650
1.200 BASIC

DIM

G
L

7.62 BASIC

13.97

16.51

4.32

5.33

15.24 BASIC

13.91
16.51
30.48 BASIC

H

.600

.700

K

.170

.350

P
R

1-87

.200 BASIC

.800 BASIC
.100 BASIC
.300
.400

MILLIMETERS

5.08 BASIC
15.24

. 17.78

4.32

8.89

20.32 BASIC
2.54 BASIC
7.62
10.16

ELECTRICAL SPECIFICATIONS
MODELS

RATED
OUTPUT

DC
GAIN

10

Vo

SPEC IFICA TIONS
Typical at 25°C ~:md rated supply

BANDWIDTH
Unity

Full

Gain

Power

SLEW
RATE

INPUT NOISE
Vol"toge

0.01 Hz

unless otherwise noted.

I
I

Current

10 Hz

0.01 Hz

to

to

to

10 kHz

~V

10 kHz
pA

min

pOp

~V
rms

10 Hz
pA
pOp

100

6.0

2

3

10

100

6.0

8

2

30

Volts
min

m,tl.

dB

MHz

kHz

min

min

min

min

±1O

.5

140

±5

140

v/~sec

3291114

Low Cost
I nverting Only

3292/14

3
typ

3293/14

10 Hz

to

10 Hz

rms

!

80

:._-

3354125

Differential InpuT

3355/75

±10

3

3356/25

DIFFERENTIAL INPUT-.:YPES
Until the introudction of Burr-Brown Models 3354/25,
3355/25, and 3356/25, .high performance chopperstabilized operational amplifiers were always singleended. In other words, they could only be used in
inverting circuits. Now, with these units, the same ultralow drift and low offset characteristics can be obtained
for noninverting amplifiers, differential., feedback
amplifiers, sample/hold circuits, peak/hold circuits and
many· other applications where the amplifier must
function with both differential and common-m()de
signals. These amplifiers are ideal for amplification of
low level signals since the low drift and noise result in low
input signal uncertainty. In addition, the gain and
common-mode rejection ratio are very high, insuring
excellent linearity of feedback gain (CMR for commonmode voltage of ±IOV is typically 140dB at DC_and
IOOdB up to 100Hz).
-

When the amplifier is used as a buffer for high impedance
signal sources, the. 10 13n cominon-mode input
impedance results' in negligible loading of the source.
Also, this causes the small DC input bias current to be
virtually independent of input voltage - a very desirable

I

I

400

characteristic for buffering. of the memory capacitor in
sample/hold and peak/hold circuits.
In general, these differential chopper-stabilized units can
. be used anywhere that a differential op amp would
normally be used - but where both voltage and current
drift must be very low. _
LOW COST SINGLE-ENDED TYPES
For most' inverting applications, Models 3291/14,
3292/14, or 3293/ 14 will be found to be the best choice.
These units represent the state-of-the-art in single-ended
chopper-stabilized amplifiers, featuring.the lowest drift,
lowest noise, lowest profile (1.5" x 1.5" x 0.4"), and the
lowest prices available. Frequency response and slew rate
are more than adequate for most applicatiolls.
Typical applications for tliese single-ended amplifiers are
integrators, precision reference so.urces, D / A and A / D
converters of high accuracy, precision comparators,
current to voltage converters and high gain amplifiers for
.
low level, low impedance signal sources.
Where a differential input is not required, these are -the
units to use for those applications where both Jow voltage
drift and low bias current dTift are required.

C

.,

-LOW LEVEL AMPL.fFIER

DIFFERENTIAL AMPLIFIER

FIGURE 2. Typical Applications of Differential'
Chopper-stabilized Amplifiers. .

INTEGRATOR

PRECISION COMPARATOR

FIGURE 3. Typical Applications of Single-ended
Chopper-stabilized Amplifiers.

1-88 .

INPUT OFFSET
VOLTAGE
Over
Range
-25°C
to
+850 C
~V

±20
±50
±100
±30
±50
±100

I
I

Versus
Temp.
-25°C
to
+850 C

Versus
Supply

~V/oC ~V/V

i max

max

INPUT VOLTAGE
DRIFT
Versus
Time

~V/day

max

INPUT BIAS
CURRENT
At
25°C

BIAS CURRENT
DRIFT

max

Over
Versus
Range
Temp.
-25°C -25°C
to
to
+85OC +850 C
pA
pA/oC
max
max
±80
±110
±220

pA

±26
±68
±160

±0.1
±0.3
±1.0

f5

I~Y/mo

±50
±50
±100

±36
±80
±160

±0.1
±0.25
±1.0

±10

IllV/mo

±20
±50
±50

±0.5
±1.0
±2.0

doubles
~

OPEN LOOP
IMPEDANCES

Versus I-_I_np,-u_t---i Output
Supply Difl.
CM

POWER SUPPLY

! Quies.

Nom.
Rated

Range

Volts

Volts

pA/V

1.1

mA

!
±1O

0.5

1.5

±1

Current

max

±15

±12 to ±18

±10

±15

±12 to ±18

±1O

INSTALLATION, OPERATION AND APPLICATIONS INFORMATION
DRIFT CONSIDERATIONS
The best overall drift performance of an amplifier circuit
will be achieved by minimizing impedance levels in the
feedback network. The effect on output offset and drift of
feedback and source impedances is illustrated in Figure 4.
For very large resistances, input bias current becomes the
major contributor to output voltage offset and drift.
Where high input impedance and high gain are needed
simultaneously, it may, therefore, not be feasible to use a
single-ended inverting chopper-stabilized amplifier,
because of this bias current factor. The differential input
·chopper-stabilized amplifier, used in the noninverting
mode, then becomes the best choice. This allows the use
of low impedance feedback networks while still retaining
very high input impedance to prevent source loading.
Note that input bias current doubles (approximately) for
every +lOoC temperature rise for these units.
The circuit of Figure 5 illustrates the effects of offset
voltage and input bias current on integrator
performance. Both parameters cause output errors which
increase at a constant rate as a function of time.
Additional offset voltage and input bias current caused
by temperature drift will cause the output rate errors to
increase with temperature. Note that the output rate
error due to 'bias current diminishes as capacitance, C F ,

increases. Usually, however, there is not much point in
going beyond IO~F because of capacitor dielectric
leakage. Also, as CF is. increased, R, must decrease to
maintain a given R, C F product and there will usually be a
lower limit on desirable values of R" since this represents
the input impedance' of the integrat'or. Also. R,
determines the amount of input and feedback current
flowing for a given input level. The amplifier, and the
signal source, must be capable of supplying this current.
Thus a compromise set of R, and CF can usually be
reached which takes into account these factors.

es

E

1
° = - if;Cf

rid
' 1
es t + Rj C F

J

r
0

.Eo• dt +

·1

CF

J Ib dt'

Eos = input voltage offset
'b = input bios current

FIGURE 5. Integrator Errors Due to Offset Voltage and
Bias Current.
NOISE CONSIDERATIONS
Because of the extremely low DC offset and DC drift
associated with the chopper-stabilized amplifier, noise is
often found to be the remaining limit on signal
resolution. Thus it is desirable to design the feedback
networks and external wiring to minimize the total circuit
noise. This includes the proper grounding and noise
decoupling as described under Wiring
Recommendations. In addition it is desirable to minimize
the levels of feedback impedance as a means of reducing
noise "pickup" arid the effects of amplifier current noise.
When the full bandwidth of the amplifier is not required,
it is recommended that a feedback capacitor be used to

es

Eos = input offset voltage
Ib = input bias current

FIGURE 4. OJltput Drift Components.

1-89

limit the ovetaH bandwidth and 'eliminate as much high
frequenCy noise as possible.
.
When. one of the. differential Input;' chopper-stabilized
amplifiers is used with a high impedance source, the input
current noise' will be the limiting factor on' signal
resolution. For source impedances of I kO or greater it is
recommended that a compensating resistance, Re, be
inserted in series with the inverting input (see Figure 6).
This resistor will' minimize the effect of current' noise at
the chopper frequency.
Shielding of feedback components is desirable aJ;ld may
be necessary in electrically noisy environments. Use of
shielded wire for summing junction leads is also
R .
2

+

.cu~rent ~_
nOise

compensdtion

.

r---

I

R,

Signal I
'Sau,ee .1

: e,

WIRING RECOMMENDATIONS
Models 329i/ 14, 3292/ 14 and 3293/ 14 are designed with
separate pins for power' supply command and signlil
common. The diagram of Figure 7 illustrates the proper
grounding techniques for these amplifiers. It is important
that t~e signal common and power common leads be
connected only at pin 2 of the amplifier. A separate lead is
required from the power supply common to the COM pin
of the amplifier.

-+,
"I

_ I

I

L_' _ _

:-

Load

J

FIGURE 6. Use of a Current. Noise Compensating'
.
Resistor wit~Differential Chopperstabilized Operational Amplifier.
recomlllended in high noise environments. The shield
should then be connected to the output terminal of the
amplifier.
POWER SUPPLY REQUIREMENTS
The amplifiers described in this brochure are specified for
operation on the riltedsupply voltages (±I%): They will
operate with some degradation over the specified range

I,

Supplydrairi current is., specified unde( quiescent
COl'lditiops (nci' output current from the amplifier). When
the amplifier is supplying current tQ a load, this current
must' be ad~d- to the quieScent current of the pr9per
supply to determine total suppiy current. .

Figure: 8 illustrates proper grounding for noninverting
circuits using the differential amplifiers (3354/25,
3355/25, 3356/25).

\

resistor
(Re = R,)

of ~upplyvoltag~,(±12VDC.to ::!;18VDC,for ±lOV
ampJiflefs).' . . , .
...

e,
SIG,
. COM,

Load

-15
+15
. Power Supply

FIGURE 7. Proper Grounding of Models 3291 i 14,
3292/14 and 3293/14.

FIGURE. 8. Proper Grounding of Differential Models
. (Noninverting Mode).

OVERLQAD CHARACTERISTICS
Because the chopper-stabilized amplifier consists of two
amplifying channels, one .fast and the other very slow, the
overload behavior is different from that of nonchopperstabilized op amps.- If the chopper channel becomes
overloaded due to a large error voltage at the sumllling
junction, recovery' may require liS much as a few secoJ;lds.
There are three ways in which such overloads rnay ocCuroutput voltage saturation, output Current limiting, and
transient overload induced when power supply voltages
are applied. The first of these three possible conditions
arises when the amplifier output voltage is driven to its
limits. When the output voltage can no longer follow the
input signal, the summing junction voltage rises from its
virtual ground potential. This relatively large potential is
then ~mplified by the high gain of the chopper channeI to
a level of several volts, a much larger value than is
encountered in the 'chopper channel during normal
, operation. Because of the very large time cOnstants of the
chopper channel filters, decay of thisovervoltage,. and
consequently amplifier recovery, may take several
seconds after removal ofthe overdrive signal. When the

1-90

amplifier reaches one of its output current limits, under
the proper combination of loading and signal, a
condition much like that of voltage saturation occurs.
The output voltage fails to follow the input signal and
chopper channel overload occurs.

The input current of the amplifier may be nulled as in
Figure II (for inverting circuits).

+v

In general, the amplifier will recover quickly from
. transient or short duration overloads since the relatively
slow chopper channel will not become charged to high
levels.
Overloads due to output voltage limiting (not current
limiting) may be prevented by use of a feedback limiter
such as that of Figure 9. Because the amplifier summing
junction is always held at virtual ground, even when the
limiter is active, the chopper .~hannel does not overload
and recovery from limiting is very rapid (I.O~sec or less is
typical). The limits must, of course, be set' below the
output saturation levels of the amplifier itself.

300k
R1
50k ~-iIII/Ir~-'lMr-~---'WIr-...,

-v

4
Ro + R1 + R3
Go i n == --;;-,--;;--'

R2

es

R1

-v
+v

= Rs -

R3 ",
~

R1 + R3
(R 1 + R3) Ro
R1 + R3 + Ro

10~

100 R3 for goin < 10

o-----'Wlr-~

FIGURE 10. Offset Voltage Adjustment for
Noninverting Circuits.

+v
R2

-vo-~M.-J

+v

Ro

'b

-v

FIGURE 9. Feedback Limiter Circuit.

R1

Overloads which occur during the application of DC
power to the amplifier are a result of transient imbalances
within the circuit. Recovery' time from this type of
overload is a fun(;tion of circuit design. Where rapid
recovery from such initial overloads is important, Models
3354/25, 3355/25 and 3356/25 are the best choices. These
amplifiers typically recover to specified operation in less
than one second. They recover equally fast from
extended overload due to signal overdrive conditions for
simple resistive feedback.

FIGURE II. Null Adjustment of Input Current.

DC NULLING TECHNIQUES
The proper connections for nulling of the DC offset
voltage are shown in the Mechanical Specifications. Note
that in all cases these offset controls are optional and
need not be used if the small offset voltage of the
amplifier can be tolerated. The differential chopperstabilized models (3354/25,3355/25 and 3356/25) can be
nulled as shown in Figure 10. However, the inherent
offset voltage of these amplifiers is acceptably low
(typically less than lO~V) for many applications and the
null control may be unnecessary.

INPUT/OUTPUT PROTECTION
The various amplifiers described here are designed such
that any voltage 'up to the value of power supply voltage
may be applied directly to the amplifier input pin without
damage to the amplifier.
Output stages of the amplifiers are current limited to
prevent damage should the output pin be shorted to
common. Permanent damage to the amplifier may occur,
however, if the output pin is connected toa voltage of the
.same order of magnitude as the supply voltages.

es

-::

1-91

BURR-BROWN@

3329/03

IElElI

HYBRID Ie POWER BOOSTER
.
.

FEATURES
• .t.IOOmA OUTPUT
• SHORT CIRCUIT PROTECTED

+vcc

• NO HEAT SINK REQUIRED'
• DUAL-IN-LiNE PACKAGE

DESCRIPTION
The Model 3329/03 is a power booster amplifier
designed for use in cascade with IC or discrete
component· operational amplifiers inside the
feedback loop. Current output cif up to ±IOOmA at
±lOVDC is provided without the need for a heat
sink. The unit is short circuit protected over the full
temperature range or -40°C to +85°C. Output current
is limited to ±ISmA by internal circuitry. No
external components. are required. The high full
power frequency (IMHz) and small signal
bandwidth of SMI:J:z. insure that the unit will not
degrade the frequenCy response of the operational
amplifier used ..
The class B output stage provides high output
.current with a minitnum of quiescent power supply
drain. The low open loop output impedance (IOn)
insures stable operation with large capacitive loads,
and virtually eliininates the closed loOp gain loading
effect of low impedance loads such as son
terminated lines. Because of the 10kn input
impedance of the bposter,the current output requirements of the operational amplifier are minimal.

.International AirpDrllnduSlrial Park.' P.O. 80x114OO· Tucson. Arizona 85734 . Tei: (602) 746-lIIi . Twx: 911H152·l1Ii • Cable: 8BRCORp· Telex: 66-6491

1-92

MECHANICAL SPECIFICATIONS
Dimensions in millimeten;. are shown in parentheses.

PHYSICAL DIMENSIONS

CONNECTION DIAGRAM
(1l0TTOM VIEW)
V+

-n-14+-+
T

•

I

+--+-+1
I

DIMPLE OVER
NO. I PIN POSITION

•

-1--+-+
1
I

•

t-+-+
I

Output
.IS"tYP.(.IL'

=-1f-

"

I

I

·0-10+
1
I

S-nT

Input

+--1--1•
1
I
1""-+7-0- V-

.02

typo
(.51 )

IJin Spacing O. I "
(2.5mm)

Weight: 0.12 0.1.. (.1.40 grams) max.
Material: Black Epoxy

Pins: Tin pl:.lteu nickd
Connel.:tor: Hts an\' l.:ommercial

dual-in.iine con~ector

APPLICATIONS INFORMATION
Power Supply Requirements
The ModeI33~9/03 is designed to operate over a power sup·
ply range of ± 12 VD(, to ± 18 VDC Output voltage swing is
guaranteed to be in excess of ± I a volts a.t full load. when operating on supplies of ± 15 VD(,. For other values of supply
voltage, the output swing varies in proportion.

pedance load (e.g. 50n) is heing driven. a severe loading
effect occurs which greatly reduo:es the effeo:tive open loop
gain and bandwidth. Effeo:tively. the unloaded gain and
bandWidth of the operational amplifier would be multipled
by the loading factor..i!L "" .0:;. if the load is :;on.
\050
When the 3329/03 booster is used. however. the effective
open loop output impedance is Ion. The loading factor now

Gain and Stability

is

The voltage gain of the 33~9/03 is approximately 1.0. The
accuracy of this gain is relativdy unimportant. since the booster is used inside the feedback loop of an operational amplifier. The booster by itself is completely stable under all
conditions of capacitive loading. Because of it's very Inw
output impedance. the 33j9/03 t~nds to isolate the associated operational amplifier from the effects of capacitive load.

Vo

10

Vults

111;\

(min) (min)
t 10

t

100

kllz
(~in)

The input circuitry will withstand overvoltage up to the value
of supply voltage.

Temperature Range
The 33~9/03 will operate over the -400 (, to +85 0 (' temper·
ature range. Storage temperature range may vary from -55°('
to +\OO°C'.
.

1000

3329/03 POWER BOOSTER SPECIFICATIONS
Input
-3dB
Input Signal
Input
Output
Response
Range
Offset Voltage Impedance Impedance
Mill
(min)
S

Volts

mVolt!\

(min)

(max)

tiD

the gain and bandwidth are reduced only

Input and Output Protection

For most general purpose operational amplifiers the dynamic
output impedance is on the order of I kn. When a low im·

Full Power
Response

= .866. and

The output stage of the 3329/03 is current limited to insure
survival of the hooster if the output is shunted to ground.
The unit is safe even under contiilUous short circuit at +85°('.
No heat sink is required.

The input impedance of the booster is approximately equal
to 100 x (load impedance). Thus. for a 100 .ohm load. the
input impedance is approximately 10k ohms. The effective
output" impedance of the booster is approximately equal to
the output impedance. of the operationalamplifier. divided
by 100.
.

Rated
Output

~~

slightly by this loading.

Power Supply Requirements

Range

Quies. Current

k!! (typ.)

!! (typ.)

Volts

Volts

mA (max)

to

10

+.IS

to ± 18

Nom. R

60

OJ

40

..

2

~

,

l

-J;. BOTTOM VIEW
* .. Optional Offset Adjust
- -

~·o.ltI i ..:tr:-!•. ..,(ur)

."

28
2800MC
6 oz.

100 k ....

*-IN.3430
+IN.3431
PI NS - Pin material and plating compositianconform to method 2003 (solderability)
of Mil-Std-883 (except paragraph 3.2).
MATERIAL - Aluminum Case
Aluminum Anodized Header
~ - 6 0% max (170)

*

0" to +700C
- 250 to +85a C
_55 0 to +85OC

~-~-

,.-. meiial:'-"; ~ ;:''';.~ .,-"; ~
.-.·c.......
oi..-).:.-l:·-:i~
.'--.. - .... of
b.--

*

±15V
±(12 to 18)V
+15, -6 mA

TEMPERATURE RANGE
Operating, rated """,ifications
Operoti ng, derated specifications
Storage

20

-

.......
~
~

I\.

"

0
10-3 10< 10- 1 1 10 1 102 103 104

* Specification same as 3430.

** Negative input for Mode;' 3430;

0.1" Grid Spocing

I

POWER SUPPlY
Voltage, rated specification
Voltage, operating
Current I qui escent

IS.MI

.445~
(11.311)

...j

±3ooV
NA
NA

... OIL
",CU21

AIIIMI_ AMi"~
.....'PlII.

~-

3 x 1011 ....

...,(Ull

JIG

±soo ~V/V

INPUT IMPEDANCE
Differential
Inverting input (to common)
Non-inverting input (to common)

MECI:IANICAL
Case style
Mating connector
Weight

..

. ...

11'11'11

NDDreH

±100 ~V/mo.
75 ~V (15 min)

INPUT BIAS CURRENT
Initial bias, 250 C, max
Inverting input
Non-Inverting input
Avg.vI. temp (signal input only)**
vs. supply voltage (signal input only

.

,..

n1l

'''1II11S1r11

2 kHz
7 Hz
0.4 V/ms
10ms

~

.IJI ....

ClJ.D2~

1 ...

FREQUENCY RESPONSE
Unity gain, small signal
Full power response, min
Slewing rate, min

,....

1.15.'I.~

*

100 dB

positive input for Model 3431.

1-95

- - . . Hz

",,:",

3500 SERIES

Low Bias Current
OPERATIONAL AMPLIFIERS
FEATURES
• LOW BIAS CURRENT. ±15nA. max
-LOW DRIFT. ±1IlV/oC. max .
• lOW NOISE. 1.4;uV.p-p
• WIDE SUPPLY RANGE. ±3VOCto ±20VOC
• INTERNAL COMPENSATION
• REPLACES 741 TYPE AMPLIFIERS

APPLICATIONS
• GENERAL PURPOSE AMPLIfiER
• ANALOG COMPUTATION
• PRECISION BUFFER
. • lOW DRIFT INTEGRATOR
• BRIDGE AMPLIFIER
, • STABLE REFERENCE CIRCUITS

DESCRIPTION
The)500 IC op amps are designed ,for low input
current while maihtaining slew rate and bandwiQth
adequate f~r most applications. The low input bihs
current is achieved by a unique bias current cancelling
circuit. This method insures that tlte bias current
remains low over theJul! temperature and commonmode voltage ranges. The same circuitry gives the amplifier,high impedance. both diffetent'ial and commonmode. The amplifier maintains interhal current levels
essentially constant, over the full range of power
supply ivoltages. Thus the offset voltage and drift
remain low for all combinations of supply voltage.
Both military and industrial temperature range versions are offered. Drift selected units are offered at
± I. ±3. ±5. ± 10. and ±20Il V j"C. max. The 3500 is
also a low' nQis~ ICop 'amP. as illustrated by the

Equivalent Circuit Diagram

typical performa~ce curves. Both current and voltage
noise are low. including the low frequency "flicker"
and "popconj" noise which usually prevent the u,se of
IC op amps for low-level signal processing.
The 3500 is internally compensated for unconditional
stabilit\' for all feedback. configurations. even ,with
capacit'ive loads. The slew rate is independent of
s'upply voltage leveL The input stage of the 3500
series exhibits no latch-up when the common-mode
\'oltage range is exce~ded:Tht:,'inpuf impedance
remains high with differential inputs as high as ±30
\'olts. thus the amplifier can be us,ed as a sensitive
comp,irator. The output stage is internally currentlimited to prO\ ide protection lIgainst continuous
short .circuits" The 3500 is' interchaflgeable wit'h 741
type amplifiers but gives greatly improVed performance.

SPECIFICATIONS
ELECTRICAL
Typical at TA

=:

MECHANICAL

+2SOC and ±Vcc = 15VDC unless otherwise noted.

MODEL
3SOOA
·3S00R
OPEN-LOOP GAIN,DC. no load. min

93dB

RATED OUTPUT
Voltage, min
Current, min
Output Impedance
FREQUENCY RESPONSE
Unity Gain. Small Signal
Full Power Sine Wave, min
Slew Rate, min
INPUT OFFSET VOLTAGE
Initial Offset at 25°C, max
Avg. vs Temp. (-25°C to +85°C I max
!-55°C to +125°CI max
vs Supply Voltage

3SOOSERIES
3500B
3500c
$lOOT
3SOOS

:!:10V
±10mA
2kll
1.5MHz
10kHz

O.6V/#oIsec

lOOdS"

.'

lkll

12kHz
O.8V/,usec

15kHz
1.0V/J).sec

:t2mV
±5,uV;oC ,8
:!:10p.v/ o C IS

±lmV±500/J.V
!:3#lVloC ,C
±5IJ.V/oC IT

±20,.NloC IAI
±20,uV/o C I R I

vs Supply Voltage
INPUT DIFFERENCE CURRENT
At 25°C
Avg. vs Temp. I-25°C to +85°C--·

.-55°C to +125°C
ys Supply Voltage

~-

,500.V

Common Mode

±30nA

±1.0nA?C ,A
±1.5nAJOC I A

Order Number"

--

3500A
35006
350OC
3500R
3500S

±51J.V1mo
:!:20nA
:tQ.5nAI"C ,B
!:1.0nAloC ,S

"::!:15nA

:!:SOnA

:to.3nAJOC ,C

!:O.5nAJOC

:to.SnA/ot ,T

--

!"7nA

::t:30nA, max
:!:C.3nA/oC. max

r- ~
~
."~~ 1

±O.2nAIV

,

:t15nA

±O.5nAJOC IA
til.7nA/oC IR
±O.lnA/V

:!:10nA
:tQ.2nAI"C ,B
:±:O.5nA/oC ·S

±O.1nAJOC ·C
:!:O.2nA/oC T

2.0.V

1.4pV

M'

TEMPERATURE
Operating. Rated Specs A, B, C
R,S. T
Storage

yJ
0

D!M

INCHES
MIN
MAX

A

335

3>0

305

.335

•
c
0

,

:!:11V
100dB

±Vcc

POWER SUPPLY
Voltage, rated specification

Current. quiescent, max

;

:t15V

."
7"

'.5
021

041

053

040

025

102

J

040

025

102

G

200 BASIC

H

02.

034

071

0 ••

029

045

074

I 14

M

45° BA.SIC

160

110
095

'508 BASIC

127

500

279

406

45° BASIC
10'

241

PIN CONFIGURATION

ABSOLUTE MAXIMUM RATINGS
Supply
=20VDC
Internal Power Dissipatlon(t) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ SOOmW

+40VOC
.... 20VDC
-65 0 G to + 150° C
-550 C to .... 1250 C
+3000 C
Continuous
+l50°C

NOTES:
1. Package must be derat~d based'on: HJC = 45°C/W or fJJA = 1500C/W
2. Forsupply voltages less than :t20VDC the absolute maximum input VOltage Ise:qual to the supply voltage
3. Short circuit may be to power supply common only. Rating applies to -t-85°C a~blent.

470

'.5
01.

--

• Specifications the same as the 3500A or 3500R
··TYPlcaL
•• "If signal voltage is applied to the Input in the absence of power supply VOltage, series resistance should
be used to limit input curre'nt to 20mA.

9 40
.51

419

010

N

'oifferential Input Voltage(21
Input Voltage Range(2)
Storage T ~mperature Range
Operating Temperature R~nQe'
lead Temperature . Solde~lng, 10 seconds
Output Short Circuit Quration(3)
Junction Temperature

MILLIMETERS
MIN
MAX

010

,

-25°C to +85°C
-55°C to +125°C
-65°C to +150o C

Weight. 1 Q grams

F

K

±3V to ±20V
+3.5mA

,

+.

0,

H

200pA
35pA

INPUT VOLTAGE RANGE
Common-mode Voltage. min
Common-mode Rejection at :tl0V
Maximum Safe Input Voltage·"

~

N

.

T

--

107Uli 3pF
5xl0911',3pF

INPUT NOISE
Voltage. O.OIHz to 10Hz, pop
10Hz to 10kHz, rrns
Current, 0.01 Hz, p-p
10Hz to 10kHz. rms

Operating Range

IIIII . 1

----I.-- 0

Plane"

+l,uVlo C

INPUT IMPEDANCE

Differential

j

±40~NIV

INPUT BIAS CURRENT
At 25°C ! either input 1, max

Avg. vs Temp. I-250C to +85°C max
I-55°C to +125°C max

12kHz
O.8V/~sec

7N!t
rF: 3

Seato no
±5mV

±2JJ.V/day

vsTime

TO-99
3500E

-Vee CASE

'No Internal Connection

2.7

TYPICAL PERFORMANCE CURVES
IAt TA =;+25°C and ±Vcc ~ 15VDC uole.ss otherwise specilied,
• INPUT, BIAS,CURRENT VS
TEMPERATURE
80

;(

E'

c:

40

"
:;

20

~"

f'.

60

.,

U

~

0

Q.

E

!l!'"
0
>

V

ill

'5

IlIls = 10kHz
I-Is

~

II
II

1/

. SOURCE RESISTANCE

.,

>

//

z~

:;

:;

Q.

Q.

E

.E

Is= 100Hz

0.1
Is

I-

10Hz

,

....

Q.

~ ~

~

f=)~' ;bk~Z

'"

.' S

',//

19'

tf'

100

o

1kHz

z ,,;
.:;

~

V

-20

"' , '"'

'10

Q)

;

P~P INPUT NOISE VOLTAGE VS

RMS INeUT NOISEVOLTAGE'VS· ,
SOURCE RESISTANCE .'

~
v~

i0

-

Ir

. liS ~lk,~z
Is

1.,-

, '"'

Is= 10Hz

'"'

-40

-50 -25

0

25 50 75 100 125

10k

Temperature lOCI

Source Resistance

OPEN-LOOP FREQUENCY

m

100

::!

80

~.
.,

60

c:

'"

S
0
>

r---

40

'20

·0

""

:20
,

1

,

-

--

~ -..i.

100

~

"'S..

0

"TA = 850C:::

,

o

4

'"

16

.,
S'"
0

12

:;

8

Q.

>

~

,

.-15
lk

lOOk

10k'

1M

20

.

CL

\

10

r

T1oo
20

30

40

r-...

'1.

.;;

u
ih

ih
~

+L-~ >-"

r....

II

';'-

I

,

12

V"

:;

8

0

4

)I

0

>

,V

~

30

0

/

/

"

V

12
16
4
8
Supply Voltage I±VI
lo..

COMMON-MODE REJECTION VS
FREQUENCY·
'
'120

I - f--'VCM.= 10V, pk - I--

m
::!
a:

:;;
U

COMMON-MODE RANGE VS
SUPPLY VOLTAGE

80

V

8

20

1\

0

-20
1. 10 100 lk 10k lOOk
Frequency I Hz I

WM

'

POWER'SUPPLY REJECTION VS
FREQUENCY

V

2

60
40

20

0

16

100

60

RL=:lkil
16

.,
.
'"'"
~

>-"

15 26- 25
10
5
Output Current I mAl

50

(~sec)

~
U

\

OUTPUT VOLTAGE VS
SUPPLY VOLTAGE

Q.

±Vcc = 10V

0

o

~

,

,

RL='lkil

Time

±Vcc= 15V

4

~

"

20

.,....,. .

±vcc=~rr

8
12
16
Supply Voltsge I±VI

,5
-10

+Vcc -,3oY.

,~

0

TA - '125°C'
'90

:;

0

0

20 +Vcc = 20V

T"A =-55°C'
TA = '25°C ,
TA:" 25°C

Q.

Q.

OUTPUT ilOLTAGE VS
OUTPUT CURRENT

/

.,

±~c!I~~~'

.. 2

o

:s

VOLTAGEGAINVS
SUPPLY VOLTAGE


0

10 100 lk 10k lOOk 1M .10M

110

"

.;;
Q.
,,;,

10k

(n I

.'R'~'= lkil

±V:c'!:~5V

14
.±Vcc = 3V to 20V

""

lk

OUTPUT VOLTAGE VS
FREQUENCY·

RESPONSE
120

1M

tOOk

100Hz

4

o

",V
V
4

8

12

16

Supply Voltsge I±V,

1-98

20

10 1

10

100

lk

10k lOOk 1M

Frequency (Hzl

APPLICATIONS INFORMATION
OFFSET ADJUSTMENT
The input offset voltage of the Model 3500 may be
adjusted to zero by connecting a 50Hl potentiometer
between pins I and 5 with the wiper arm connected to
negative supply (Figure I a). This provides an adjustment
range of approximately ±IOmV. This offset control is
optional and may be omitted if the specified offset is
considered sufficiently Ibw.
Adjustment of the input offset voltage of the 3500 will
affect the voltage drift to some extent. A rough "rule-ofthumb" is ±3/J.V!"C change of drift for each 1.0mY of
offset adjustment. This is true of other IC op amps. such
as the 741, 10 I, etc., but is usually masked by the greater
drift of these units. However, in low drift amplifiers, such
as the 3500C and 3500T, this effect must be considered.
By use of a transistor as in Figure.! the effect of offset
adjustment on drift can be substantially reduced (by
approximately a factor of six).

When opelatmg on a single supply (+V«-), shorting the
output to common is equivalent to a short to supply and
the internal power dissipation is approximately twice
that which occurs for a short to common with'balanced
supplies of± v; •. This dissipation may exceed safe limits
for single supply voltages greater than 20V and must be
prevented by use of a series limiting resistor or other
device, if short circuit protection is desired.

+Vcc

Vo

Vee
=--~
Z

(AZ)
-Al VIN

")"l~'S-L~+ v~
Vl

~

'1lnv,rtlng Ampill/,r

~5

~~.V

..

•1Slmpl, OHset AdJuslm,nl

. bl Orln·C.mp....ted OH... Adlustm,nt

'Opll.n.1 Comp..,nl
bl N.ninv,rting Amplifier

FIGURE I. Offset Adjustment Techniques.

BIAS CURRENT EFFECTS
Input bias current of the ainplifier creates additional
offset voltages by flowing in the impedances of the signal
source and the feedback network. Although the bias
currents of the 3500 are quite small, their effect£ may be
appreciable when these impedances are large. The bias
currents at the two inputs tend to be equal and the difference current smaller than either. Thus equalizing the
resistance from each input to common, as in Figure 2. is
an effective means of reducing DC offset due to bias
current.

FIGURE 3. Operation on a Single Supply.

WIRING PRECAUTIONS
In order to p'revent high frequency oscillations due to
lead inductance the power supply leads should be bypassed.
This should be done by connecting a 10/J.F tantalum
capacitor in parallel with a O.OOI/lF ceramic capacitor
from pins 7 and 4 to the power supply common.
TYPICAL APPLICATIONS

Al

V,N

AZ

<>--N~I

~r
FIGURE 2. Minimization of Bias Current Effects.

Al

AZ

_
2
rN~'

VIN

'3

AZ

Vour= - -VIN
AI

OPERATION ON A SINGLE SUPPLY
Although virtually any op amp can be operated on a
single supply if input and output voltage limitations are
observed, the Model 3500 is particularly suitable for such
use. Its wide supply range of±3VDC to ±20VDC translates to a single supply operating range of 6VDC to
40VDC, plus or minus. Two possible modes of operation
on a single supply are shown in Figure 3. The following
conditions must be,observed to keep the amplifier within
its linear region of operation.
l) +2 < Vo < (Vee -2)
2) +3 < VI~ < (Vee - 3), Figure 3b

'l'lnv'rtlng Amplifier

§Lvour
VIN

3

Vour: VIN
cl Precision Buller Amplil/er

1-99

bl N.ninvertlng Amplifier

6 vour

3500lVlP

BiJRR - BROWN ~

'IElE91

Matched Low Bias CurrentlC
OPERATIONAL AMPLIFIERS
FEATURES
•
•
•
•

TWO MONOLITHIC OP AMPS WITH ...
• MATCHED OFFSET VOLTAGES -.b..Vos = 2DOIIV max
• MATCHED DRIFT. 6.Vos vs Temp. = 1pV/oC max

LOW NOISE. 1.411V pop
lOW BIAS CURRENT. 50nA max
INTERNALCOMPENSATION
WIDe POWER SUPPLY RANGE

APPLICATIONS
• INSTRUMENTATION AMPLIFIERS

• LO~~R:O~S~NGLE-:ENDED AMPLIFIERS WITH

• MULTISTAGE ACTIVE FILTERS WITH LOW
OUTPUT OFFSET

• DUAL CHANNEL AMPLIFIERS WITH MATCHED
DRIFT

DESCRIPTION
Close process control and care(ul grading by BurrBrown make possible a new dimension in IC op.amps
- drift matched pairs. Drifts as low as IJ.I, VI "c may be
obtained using !ile 3500MP op amps. The 3500MP
lC's are selected froin Burr"Brown's 3500 series of op
_ amps, thus all ,the features of the 3500 series are
automatically f~nd in the 3500MP. This enables the
1500MP topro,vide very-low drift (I ",V /"C) with
very~low noise"«(4",V p-p) without sacrificing speed,
(Slew rate 0.8V Iltsec min.)
The 3500 IC op amps are designed for low input
current while. maintaining slew rate and bandwidth
adequate for mq~t applications. The low input bias
current .is· achkved by a unique .bias current
cancelling circuii~ This method insures that the bias
current remains low over the full temperature and
commoncmode voltage. ranges. The same circuitry
gives the amplifier high input, impedance, both
.differential and common-mode.

All units of the 3500Eseries are 100% te~perature
tested for voltage and current drift. The 3500 is also
one of the lowest noise Ie; opamps yet prodUced, as
illustrated by the curves.on page 1-102. Both current'
and . voltage noise' are low, including the low
frequency "flicker" and "popcorn" 'noise which
usually prevent the use of IC op amps for low-level'
·signal processing.
The 3500 is internally compensated for
. unconditional ,stability for all feedback'
configurations, even with capacitive loads. The slew
r Vos = Vosl - Vos21
Initial Offset @ 25°C
Avg. vs. Temp. (-25 to'+8~C) max.

.140 ".
radiUS

o.

30

b) Drift Compensated
Offset Adjustment
*2N3906 or similar.

FIGURE I. Offset Adjustment Techniques.

1-101

TY'PICALPERFORMANCE CURVES
(,y., +250 C on,d ±15 Vdc unless otherwise, specified)
~

RMS INPUT lIIoiSE voI.TAGE
.SOUR~E RESISTANCE

, II
I-

f"B =10k z

Va =,1 kHz

~"

~
0::>:"lOI'-'~-+'CC::O~~~B'=
.... ,- 1kHz
Z..;!.
....

""""
::l
U
5

>

fB~

~

Z

lk

~~~~~~~~~

tvt~;:ttj~J.UlUII
10k
lOOk
FREQUENCY (Hz)

,

U
0
on

!:
0

o

0

0

V
V
o

4
8
12 16 20
SUPPLY VOLTAGE (±V)

~
~

/
/

VOLTAGE GAIN ,VI.

,

SUPPLY VOLTAGE
Cii"

V

/

:s.
Z

~

...0
0...
Z

V

'-

\10

~

",V

0

04
8
12 16 20
SUPPLY VOLTAGE (±V)

VI.

100

o

.

IT= ~2sOC
'
A -T = 250 C
A-r:---:-.

-

~

-.L
I

:L..

, asci,

A=

4
,8
12 16 20
SUPPLY VOLTAGE ,(;tV)

COMMON MODE REJECTION va.
FR~~NCY

120 t---

.

r- WC~ =IIOV, ~okl. '

100

1000

80

)

60

40

100

7

~

~

1'\
10,100 IkIOkIOOk,IM 10M
FREQUENCY (Hz)

I

, FREQUENCY

z
o;:

''\

o
-20

V

POWER SUPPLY REJECTION

\/I.

V

'\

20

RL'=1 k'.A. 1

'4

V

'\

40

,10000

'.I

'\

120

8

5 10 ,15' 20 2S 30
OUTPUT CURRENT (mAl

8

u

,

\

20 30 40 SO
TiMe c.,.s)

on

0<

4

lfpf

6

>'
..;!.

~:s

Lk.A.

= 003 Vto;t20 V

'\

60

20

, ... ~ 16

c).

10

~V.

OUTPUT '«K.TAGE va.
SUPPLY YOirAGE

~'

Zz

1\

-10

::l

20

8i
l;w

.J

2

:!~

~

,100
8C

RL -5 [ k- (
L

....>
::l

I:;'

COMAU)N M9D,E RANGE
SUPPLY VOlTAGE

OPEN LOOP FREQUENCY
. RESPONSE

II

0

0

f

12

0~~-I--+-+-4~~
-20~-+-+-+-+-1-4~

-50 -25 0 25' 50 '75 100 125
TEMPERATURE (0C)

:s.

V. = ,,15V

o

,V

1M

Cii"

5

'"
~~ "
'
"
'
<
4 v.='±st,- iZ"r
V =Oo3v
l"o
o

;>~
w

lOOk

w

I
I
V. = ;tl0V,

..... . /

20~~-+~~-4~~

120

S'.
...

.=Oo2UV

8

~

10k'

10

1M

OUTPUT VOlTAGE .is.
OUTPUT- CURRENT

12

...~

40~~-+-+-+-4~~

VOlTAGE FOLLOWER
STEP RESPONSE

YL

w
C)

16

w

601-I--+-+-4-4~1-~

SOURCE RESISTANCE (A)

:!
...

20

z

I

~

2

..z

W

_40LL~~~~~~~

OUTPUT VOLTAGE
FREQUENCY

4

B

10 kH'

Il.

lk
10k
lOOk
1M
SOURCE RESISTANCE (A 1

....
~
::l
o

F

O~

1.1

i/LI

=

<"
..s

,~loo f- ?TI=

r...... ' 1/

80 ......-.---..-.--.--..-...,.....,
,:,

~ ~

lTTilll

..

"INPUT BlASMREN1 vS.'
TEMPERATURE'
'

poP INPUt NOISE VoLTAGE VI.
, ,sptJRCE RESISTANQI

VI.

20

o

r-,.,

'" ,\

-20

10
I

10 100

Ik 10k lOOk 1M

FREQUENCY (Hz)

1-102

1 10 100 1 k 10k lOOk 1M 10M
FREQUENCY (Hz)

BIAS CURRENT EFFECTS
Input bias current of an omplifier can generate additional small
offset voltages by flowing through the equivalent input source
resistances. Although the bias currents for the 3500MP are
qui te small, the current-generated offset vol tages may be
significant for source resistances greater than 1 k.l>.. When
using the matched 3500MP amplifiers to obtain offset voltage
drifts on the order of 1 flV/oC particular attention must be given
to the input bias currents. Because of the great number of
circuit configurations involving two operational amplifiers,
it is only possible to give some general guidelines for minimizing bias current effects.

/

35038
10mV

x 1 mV

~

35008

a

E

>0
.

100

V

.""

10K

lK

lOOK 1 M.I>.

R.

FIGURE 3. 6 Vas vs. Source Resistance.

II

E

100

:;cP

.;; ">- 10

S:1. 5

>
 125 .....

FIGURE 5. Compasite low Drift Op Amp.

105.n

105 oft.

Eo =

252

oft.

Ei

FIGURE 6. 4 Pole Low Pass B~tterwo~th Filter;fo = 1 kHz.

-2 b.V

. "os

3501

BURR--BROWN®

IE:lE31

Low Bias Current
OPERATIONAL AMPLIFIERS
FEATURES
• LOW BIAS CURRENT. ±3nA. max
• LOW DRIFT. t5pV/oC. max ±30pA/oC. max
• LOW NOISE. O.BpV. POp 30pA. pop
• WIDE SUPPLY RANGE. ±3VDC 10 t20VDC
• INTERNAL COMPENSATION
• REPLACES 10BANO 741 TYPE AMPLIFIERS

DESCR,PTION
The 350 I series is designed to minimize input voltage
drift and input bias current. without resorting to
exotic processing. The low input bias current is
achieved by a current cancellation technique
developed by Burr-Brown's Ie Engin~ering Group.
The same input circuitry gives the 3501 very-high
input impedance, both differential and commonmode. Internal current levels. of the amplifier are
maintained essentially constant over the full range of
supply voltages by relyi,ng rin basic semiconductor
properties and device matching. The result is that
major performance parameters - open-loop gain,
bias current, voltage drift, slew rate and output
current - are affected only slightly by wide variations
of supply voltage. Quiescent power drain is quite low
over the supply voltage range.
The 350 I is internally compensated for
unconditional stability in all feedback
configurations, even with capacitive loads. Thus it is
interchangeable with both 741 and 108 type.
amplifiers (eliminating the external frequency
compensation required of 108 type amplifiers).

Because of the unique input stage design of the 3501,
its common-mode rejection is very-high (I OOdB). The
result is excellent linearity (.01% or better) as a
noninverting buffer. Also the input stage exhibits no
latch-up when the common-mode voltage range is
exceeded. The input impedance remains high for
input voltages up to the value of the supply voltages.
The output stage. is internally current limited to
provide protection against continuous circuits.
All units of the 3501 series are 100% tested to all
min/max specifications - including voltage and
current drift versus temperature. Units are drift
selected with maximum specifications at ±5J'V te,
± IOJ'V te and ±20J'V re. Both military and
industrial temperature range versions are offered.
The 350 I is also a. very-low noise amplifier. Both
current and voltage noise are low, including the low
frequency "flicker" and "popcorn" noise which
usually dictate against the use of utility op amps, such
as the 741, for low-level signal processing.

Inlernatlunal Airport Indualrlal Park· P:O. Box 11400· Tucaon. Arizona 85734· T81.(602) 746-1111· Twx: 9111-952·1111· Cable: BBRCORp· Telex: 66-6491

SPECIFICATIONS
"

"

"

"

",,>\;

.

ELECTRICAL SPECIFICATIONS

TO·99 PACKAGE
Specify 350IA. etc.
Typical at 2SOC and ~15 Vdc unless otherwise noted.

3S0lA
3S0lR

MODEL
OPEN lOOP GAIN·, de: no load

93 d"B,"min

RATED OUTPUT
V~ltoge

:l:IOV, min

Current'

::I:5mA, min

35018,
35015

3SDIC

·
·

·

9m.".~
(9.39)

~.~~'~

(1.02)

2kn

Output Impedance

Unity Gain, Open Loop
Full Power Sine Wave

0.5 MHz
1.6 kHz, min
O. 1 V/~sec, min

'Slew Rate

·

·

fREQUENCY RESPONSf

,

, 'r-

o to 1000 pF

Capocitiv8 Lpod R9nge

.1511"

I

.

,O'I'::)IA.

±S mY, max

.12 mY, max

±20 ~v/oe (A)
±20 "v/oe (R)

±1O"V/oe (B)
±IO "v;oC (s)

±40 ",V/V

±2 "V/day

·
~

INPUT BIAS CURRENT

...
...

@ 25°C
Avg.

Temp. (-25° to +ssec) max
(-550 to +12S°C) max
Supply Voltage

_

250C
Avg. v~. Temp. (-250 to +ss°C)
(_55° to +1250 C
liS.

Supply Voltage

±5 nA

5x 107 ... IfJpF
101OA1I3...f!'

Common Mode

INPUT NOISE
Voltage, .01 Hz to 10 Hz, p-p
10 Hz to 10 kHz, rms
Current, .01 Hz to 10 Hz •. p-p
10 Hz to 10 kHz, rms

2 _V
1." ",V

66pA
12pA

INPUT VOLTAGE RANGE
Common Mode Vol tage
Common Mode Rejection@. ±10V

Max. Safe Input Voltage

±11 V,'min

100 dB

·

Vdltage, rated specification

±15 V
..a.

l/

-3

10kHz

fS

2

~

lK

120

"

60

"m

40

2

~

"-

12

>

10

co

m·
2

~

6

r-...

'5
l!::>

4

~

-20

0

10 100 lK 10K lOOK 1M
Frequency (Hz)

~

a;-

co

....

(!).

j

.."

i
co
2'"

112
108

~104

8

12
16
Supply Vol toge (±V)

-

1--

~"

20

0

IVs

±"LUV

8 -20.1

s

Vs = ±15V

«I

V. = '±IOV

\~

8

'5
l!::>

4 Vs -

0

1
'5

-5

1M

o

o

~

. 1:\

i

.

~
!j:'

'"

2

,,-

I

4
8
12
16
Output Current (mA)

COMMON

MODE RANGE

4

""

"'

1 10 100 lK 10K 1001( 1M
Frequency (Hz)

o

4
8
12
16
Supply Voltage (±V)

1-107

o

4
8
12
16 20
Supply Voltoge - (±V)

107'111111

a

~

104

:103

i,02I• •1

V
o

o

/.

V

~105

V

4

/

/

~ 106~

V

8

/

/

V

POWER SUPPlY REJECTION VI.
FREQUENCY

VL

/

12

/

12

::>

Vcm = 10V, peak

""

RL = 2 K.n.

10

160 200

.16

8

20

80 120
Time (ils)

OUTPUT VOLTAGE VI.
SUPPLY Va..TAGE

20

~

SUPPLY VOLTAGE
16

40

D

.t.

~5V r\2c\ ~

IV. - ±JV

o

\

5++--+-+---f---+l---I

~

o -10~-'+-+--+-'-+-l

±3V

U

... ~., ""\

12

VI.

i

I III

J! l~~

I

1M

~

OUTPUT VOLTAGE va.
OUTPUT CURRENT

16

lOOk

10k

LARGE SIGNAL
STEP RESP.ONSE

11111

20

liT I I lilsllll0,Hz IlIIUll

1k

VI.

lOOK
10K
Frequency (Hz)

'fa = 1kHz

Source Resistance (AI

20

"
40

i

",Vs

o

20

COMMON MODE REJEcnON
FREQUENCY

\

2

~
0

4

.E

Vs = ±15V
V =±10V

\1-'

D

::!!. 116

·0"

\

lK

120

f

'5Q.

DL =2 K~ttlt

-

8

"0

>

~

t- . -

.1

co

....,.

r- -

0

14

"-

D

r-...

20 t-

~

~

la-= 100Hz-

10K
lOOK
1M
Source Resistance (A)

OUTPUT VOLTAGE
FREQUENCY

r .....
a;- 100 I-

;..

·0
Z

'fS =10 Hz
fS 100 Hz

0.1

OPEN LOOP FREQUENCY
. RESPONSE

~

~

10

51

Temperature (0C)

eo

"'"

2

VI.

~

I I

f~ ~1\olH~

..a.

/V
/V

fS = 1 kHz

1111

>100

~

·0
Z

-50 -25 0 25 50 75 100 125

::!!.

I..

/
/

/

8-

;'

L --T

0

10

Q.

P-P INPUT NOISE VOLTAGE
SOURCE RESISTANCE

~

20

10 '

1

10 100 lK 10K lOOK 1M
Frequency (Hz)

5~

OPERJTIQ,N ON A SI~G~£'SU,PPLY

OFFSET ADJUSTMENT
The input' offset' voltllge of the Model 3501 may be adjusted to
zero by: connecting a 50 ,Is A ,potentiometer betWeen pins l.and 5
with the )y;per arm connected, to negative supply (Figure '10). This
provides, on acliusiment' range of approximately ± 10 mV. This
offset, con,rol is optional and may b!, omitted if the specified offset
is considered sufficien>ly low:
Adjustment of the ini>ut offset voltage of the 350) will affect the
voltagedrift to some' extent. A r, fa"clor of six).

Althaughvirtually any op amp can !;ieoperaled on a single suppJy
ifinpul oDd output volt!lge limitations are' observed, the Model
3501 is particularly suitable for such use. It's wide supply range
of ±3 t!" ±20 Vdc translates 10,0 single 'supply operating range of
6 to 40 Vdc, plus or minus. Twa possible modes of operation on a
single supply are shown in i=igu';"3. The following conditions must
be observed to keep the 'amplifier within its 'linear region of
operation.
1) +2 < eo <: (Vs - 2)

2) +3 < e s < (V, - 3), Figure 3b
When operati,ng on 0, single supply (Vs); shO\'ting the ouiput to
common is equivalent ta a short to supply and the internal power
dissipation is approximately twice that which occurs for a short ta
com'1)on with balanced supplies of ± Vs • This dissipation may
~

"

exceed safe limits for single supply voltoges greater than 20 volts
and must bEl prevented by use of a series limiting resistor or other
device, if short circui~ protection is desired.

e,a =

-(~) ei

V
s

T

R2
eL =-

+ eo

Va), Simple Offs.et
Adjustment

Rl

b) Drift

Compens~ted -:

+

Offset Adjustment

LOAD

FIGURE l.Offset Adjustment Techniques,

BIAS CURRENT EFFECTS

0) Inverting Amplifier

Input bias current of the amplifier creates odditional offset voltages
by flowing in the impedances of the signal source and the feedback
network. AlthOugh the bias currents of the 3501 are quite small,
their effectS may be appreciable when these impedances are 'large. ,
The bias currents at the two inputs tend to be equal and the difference <,urrent smdller than either . Thus equalizing the resistance
.. from each' input to common, as in Figure 2, Is on effective mecons
of reducing DC offset due ta bios current.

-,

b) Noninvertlng Amplifier
FIGURE 3. Operation on aSingle Supply.

FIGURE 2. Minlmiz!"tion of Bios Current Effects.

1-108

.e L

e.I

i-=

~

BURR-BROWN®

IElElI

3507J

1\ \ \l

Fast-Slewing
OPERATIONAL AMPLIFIER

FEATURES
• 120V/ ILsec SLEW RATE
• 20MHz GAIN·BANDWIDTH PRODUCT
• INTERCHANGEABLE WITH 741 TYPES

DESCRIPTION
BurroBrown model 3507 J is intendt.:d for use in
circuits requiring fast transient response-pulse amplifiers, D / A converters, comparators, fast followers,
etc. Key parameters such as slew ratc; settling time
and bandwidth are orders of magnitude better than
for most other IC op amps.
The 3507J is compensated to allow faster slewing and
greater band~idth for gains of 3 or more. For gains
greater than 3, the gain rolloff is 6dBi octave. By use
ofa single external20pF compensation capacitor the
350"ZJ can be stabilized at all gains including unity. In
addition, by use of an alternate compensation
technique, it is possible to stabilize the 3507 J at unity
gain without sacrificing its faster slew rate.
The 3507J is pin-compatible with other standard IC
op amps while offeri,ng greater speed and higher
output current. It also is input- and output-protected
to prevent damage if the output is shorted to
common, or the input is shorted to supply voltage.

Inlernational Airporllnduslrial Park· P.O. Box 11400 - Tucson. Arizona 85734 - Tel. (6021746-1111 - Twx: 910-952-1111 - Cable: BBRCORP - Telex: 66-6491

1-109

MECHANICAL

SPECIFICATIONS

TO-99 PACKAGE

.ELECTfUCA'L
TypiCal ar±15VOC .ancl ;'"25°C unless otherwise noted.
MODEL .

3507J

I
OPEN-LOOP GAIN, DC
No Load
2kOLoad
RATED OUTPUT
Voltage 11kO load)
Current

TYPICAL

I

GUARANTEED

=:

77dB

±12V
+2OmA

±10V
±10mA

DYNAMIC RESPONSE
Small Signal Bandwidth (OdB)
Gain-Bandwidth product (ACL = 10)
Full Power Bandwidth
Slew Rate
Settling Time (0.1%)
Ris,Hlme (10:-90%, small signal)
Overshoot

--

20MHz
1.6MHi
120V/I'sec
200nsec
25r1slfC

1.2MHz
SOVll'sec
50nsec

-

-

INPUT OFFSET VOLTAGE
Initial (without adjust) at +25°C
Over Temperature
(avg. OOC to +7OOC)
vs.Supply Voltage
vs Time

±5mV

±IOmV
±14mV

±30I'V/oC
±30I'VN
± 5OI'V/mo

2OOI'VN

+SOnA

+250nA
+500nA

Pin numbers shown for reference only.
Numbers may not be marked on package.

INPUT BIAS CURRENT
Initial at +25°C
Over Temperature
(avg. DoC to. +7OOC)

±O.5n~C

Over Temperature
(avg. DoC to +700 C)

INCHES

DIM.

.

INPUT DIFFERENCE CURRENT

Initial-at +25°C

±20nA

±5OnA
±100nA

to.1nAloC

INPUT IMPEDANCE
l00MO 113pF
l000MO II 3pF

40MO

Comm<;Jn-Mode (linear operation)
.Differential (between inputs I
Absolute Max (either input)

±12V

Common-Mode Rejection

OOdB

:tl0V
±15V
±Supply
74dB

Differential
Common-Mode

NOTE:
Leads in true position within 0.10"
10.25mml.R at MMC at seating· plane.

A

MIN

MAX

.335

.370

MILLIMETERS

MIN

MAX

8.51

9.40

7.75

8.51

.305

.335

C

.165

.185

4.19

4.70

0

. 016

.021 .

0.41

0.53

E

:,;().to

.040

0.26

1.02

F

.010

.040

G

.200 BASIC

H

.028

.034

0.71

.02'

0.25

.04'

0.74

K

.• 00

L'

.110

.160

2.79

N

.09t;i

.. 105

INPUT VOLTAGE RANGE

1.02

5.08 BASIC
0.86
1.14

12.7
4.06

45° BASIC
2.41

2.67

POWER SUPPLY
Rated Voltage
Voltage Range, derated
Current, quiecscent

±15VDC
±SVto ±20V
±4mA

CONNECTION DIAGRAM
±6mA

TEMPERATURE.RANGE
Specifications
, Operating
Storage

OOCto +7ooC
-25°C to +85°C
-65°C to +15OOC

BANDWIDTH CONTROL

OFFSET
ADJUST'

OUT

IN-

-VCC
ITOPVIEWI

1-110

TYPICAL PERFORMANCE CURVES
(At +25°C and ±15VCC, unless otherwise specified)

NORMALIZED AC PARAMETERS
VS TEMPERATURE

OPEN-LOOP FREQUENCY RESONSE·
120

1.1

100
Slew Rate

~

,/1

~

0.

~

8·~
-'

.,

.~

80

40

20

>

o

(;

Bandwidth

r"'';;::
r"';;;

-=

i';

~
L"";;;::
I""'~

300pF ....

IIII

-20
10

I I
I
30pF

60 ' -

oS

0.'"

I I
OpF

100

1oo0pF

100pF

~~

10k
100k
Frequeny (Hz)

1k

'-IJ.

t""';::: I!!oio

10M

1M

100M

·Capacitance values shown are external compensation
from pin 8 to Common.

0.8
75

-50

-25

O·

+25

+50 +75 +100 +125

Temperature (OC)

EQUIVALENT INPUT NOISE
VS BANDWIDTH

OUTPUT VOLTAGE SWING
VS FREQUENCY·
100

-

I-

~

100
Vee ±2OVDC
.
Vee +15VDC

-

10kO Source Resistance

:;

,

- rs;: Vee ±10VDC

.,

EE

.~o'

E>

"

"iii CI>
.~ .~

~

0

,jfZ
"

.,

1.0

10k

100k

1M
10M
Frequency (Hz)

~ ....~V'-oP';;'"
Of
1,\0
",o\""Q

e''''&~

i"'IT I IIIf

0.1
100

100

I:::::

;/rUl

""'"

0.1

~

on Source Resistance

10

1k

10k

100k

1M

Upper 3dB Frequency (Hz)
(Lower3dB Frequency-10Hz)

·With no external compensation
capaci~ance.

NORMALIZED AC PARAMETERS
VS SUPPLY VOLTAGE AT +25°C

OPEN-LOOP PHASE RESPONSE
0

1.1
Bandwidth

.J

~~~

1.1 r-- -

". ~ ~-

'"
~
0.
"

30

.

.<:
0..

~

60

CI>

<"
ill

Slew Rate

,I

:'i!!

f"'o

90

....

120

"-

150
180

\

210
10

100

1k

10k

100k

Frequency (·Hz)
0.8
±10

±15

±20

Supply Voltage (VDC)

1-111

1M

10M

100M

APPLlCAT,IONS
~ANDWIDTH COMPENSATION
Thefrequency response ofthe 3507J can be adjusted by use
of an external compensation capacitor from pin 8 to
common, as shown in Figure I. The open-loop frequency
response curves illustrate the effect of. various 'values of
capacitance. The 3507J is stable for gains of 3 or greater
without external compensation (su'bject to the same limits
on stray and load capacitance and resistance levels). A 20pF
compensation capacitor will stabili;ze the 3507J for all values
of gain, at the sacrifice of bandwidth and slew rate.
The circuit of Figure:1 iHust~ates ano,thee approach to
compensation of the 35Q7J. This method yields unity gaih
stability without sacrificing slew rate.
'

'

-

iL
'

LOAD

~UPPLY
JYPASS

""" D.I"F

±

FIGURE I. Compensated Amplifier with Supply and
Load Bypassing.

IN

STABILITY
Because the 3507J is an extremely fast amplifier with high
gain, stray wiring capacitance and inductance in power
supply leads can cause circuit oscillation. This can be
prevented by proper circuit layout (all leads or patterns as
short as possible) and by properly by-passing the power
supply lines to comnlOn at points close to the amplifier. In
addition, it is recommended that the load be bypassed by a
50pF capacitor; see Figure I.

OUT

21m

FIGURE 2. Alternate Method for Unity - Gain
Compensation of 3507J.

OFFSET VOLTAGE_ADJUSTMENT
Although the offset voltage of this amplifier is only a few
millivolts, it may be desirable in some cases to null this
offset. This is done by use of a'20kO potentiometer as shown
in Figure 3.

FIGURE 3. External AdjustmenlofOffset Voltage.
TEST CIRCUIT -.DYNAM,ICRESPONSE
The test circuits of Figure 4are'usedfor,measurement of
slew rate, settling time, rise 'time and overshoot. Both rise
time and overshoot are measured under small signal
conditions (YOUT = ±200mV). Slew rate and settling time
are measured for a IOV"p-p, squ,are wave.

5pF

8670

1333kn
OUT

FIGURE·4. Dynamic Response Test Circuits.

BURR-BROWN®

3508J

IElElI

Wideband
OPERATIONAL AMPLIFIER

FEATURES
-l00mHz GAIN BANDWIDTH PRODUCT
- 5nA INPUT BIAS CURE NT
-lD3dB OPEN·LOOP GAIN'
- INTERCHANGEABLE WITH 741 TYPES

DESCRIPTION
Burr·Brown model 3508J is a wideband operational
amplifier intended for use in circuits requiring
·extended bandwidth and high gain. Typical examples
of applications are: RF signal amplifiers, fast
recovery voltage references, high speed integrators,
high frequency active filters, and photodiode am·
plifiers.
Model 3508J is internally compensated for stability
at gains greater than five. The 3508J can be externally
compensated by use of a single capacitor, and can
thus be stabilized at any value of gain. By use of an
alternate compensation scheme the 3508J can be
stabilized at unity gain without sacrificing slew rate.
In addition to its wide bandwidth and high gain the
amplifier has a number of other significant advantages oyer other Ie op amps; low bias current,
higQ output current, and high common-mode rejection. Inputs are protected against voltages up to
the value of the power supplies. The output is
current-limited to provide short-circuit protection.

International Airporllndustrlal Parle· P.o. Bax 11400· Tucson, Arizona 85734· Tel. 16021 746·1111 . Twx: 910-952·1111· Cabla: BBRCORp· Telex: 66-6491

1-113

MECHANICAt

SPECIFICATIONS
'ELECTRICAL

TO-9,9 PACKAGE

T.ypicalat =\'t5VDC'a~~+25°C unless otherwise noted.
MODEL

3508J

I
OPEN-LOOP GAIN, DC
No ~oad
2kOLoad

TYPICAL

I ,GUARANTEED

1.06dB
l03dB

9adB

±12V
±18mA

±10V
±10!'1A

RATED OUTPUT
Voltage

Current ,"
DYNAMIC RESPONSE
Small Signal Bandwidth (OdB)
Gain-Bandwidth Product (ACL = 10)
Full Power Bandwidth
Stew Rate
Settling Time (0.1 %)
Ri~.e Time (1.0-90%. sma" siQnal)
Overshoot

-

l00MHz
600kHz
35V/I'S8C

320kHz
. 20Vl"sec

17nsec

45nsec

±3mV

±5mV
±7mV

--

-

--

INPUT OFFSET VOLTAGE
Initial (without adjust) at +25°C
Over Temperature
(avg. OOC to +700 C)
vs Supply Voltage
vs Time

±30ji.V/oC
±30"VN
±50"V/mo

NOTE:
leads ih true position within'O.10'"
(0.2S;"m 1 R at MMC al. ..ating. plane.

200jJVN

, Pin numbers shown far reference only.
may !'lot be marked on package.

Numbers

INPUT BIAS CURRENT
Initial at +25'OC
Over Temperature
(avg. OOC to +700 CI

+15nA

+25nA
+4OnA

±O.5nAfOC
INCHES

INPUT DIFFERENCE CURRENT
Initial at +25°C
Over Temperature
(avg. OOC to +700 CI

±5nA

±25nA
±40nA

"DlM

MIN

MAX

MILLIMETE"RS
MIN
MAX

A'

.335
.305 .

.370

8.&1

9.40

.335
,185

7.75

8.51

±O.2nAfOC
0

INPUT IMPEDANCE

~

Differential
Common-Mode

3OOMO 113pF
l000MO 113pF

40MO

±13V

±11V
±12V
±Supply
74dB

,

F

G

.'"

l00dB

K

L
'M

N

4.70
0.53
1.02
0.25
0.25
1.02
5.08 BASIC

4.19

..." ....
.028

INPUT VOLTAGE RANGE
Common-Mode (linear operation)
Differential-Mode (between inputs I
Absolute Max (either input)
Common-Mode Rejection

.185
.01e
'.040
.010
.010
.040
.200 BASIC
.034

.&00
.110
.160 '
4SoSASIC
.10S
.095

0.41

0.71

POWER SUPPLY
Rated Voltage
,voltage Range. derated
I

Current. quiecscent

±15VDC
±8Vto±2~V

±3mA

±4mA

CONNECTION DIAGRAM

TEMPERATURE RANGE

Specifications
Operating
Storage

.' OOC to +7OOC
-25°C to +85°C
-lIS°C to +15OOC

BANDWIDTH CONTROL

-Vee
(TOPVIEWI

'1-114

0.86

1.1"
0.7"
12.7
2.79
'.06
46° BASIC
2.67
2.'"

TYPICAL PERFORMANCE CURVES
(At +25°C and ±15VDC, unless otherwise specified I

COMMON-MODE VOLTAGE RANGE
VS SUPPLY VOLTAGE

OPEN-LOOP FREOUENCY RESONSE·
120

20

Vee = ±15VDC

~
"
"
a:
""0
::0

100

iii

o.~
0"

.9

'to

i<;

0.0>

0>

60
40

oS

20

>

0

0

.

80

15

10

I:

/

0

E
E

/

V

V

V

/

0

U

o
±15V

±10V

±5V

±20V

Supply Voltage

Frequeny (Hz),

·Capacitance values shown are exte'rnal compensation
from pin 8 to Common.

OUTPUT VOLTAGE SWING
VS FREQUENCY·

1,0

OPEN-LOOP VOLTAGE GAIN
VS TEMPERATURE

1---+----+..,.-3\O~k_--_t

0,1 t---+---+--+---'~~

om ......__......__......___1...._ _...
10k

100k

1M

10M

,100M

-55 -35

-15

Frequency {Hz}

25

85 105 125

120

100 ~------~----~--~----~

iii

~

"
"
S'"

'OJ

Cl

'0

100

0

"""-'1iIo..

80

60

>

40

0
0

20

"

0

", ""'"

0.

-I

Q)

0.

0

10k

65

OPEN-LOOP GAIN AND
PHASE ANGLE VS FREQUENCY

EQUIVALENT INPUr NOISE
VS BANDWIPTH

1k

45

Temperature (OCI

100k

Upper 3dB Frequency (Hz I
(Lower 3dB Fr~quency - 10Hz)

-20
,10

Vee ±15VDC

TA

= +25°C

60
90

""'""

1k

10k

ii
e

iil'

~,
Q)

C>
120

"\.

\

100

150
180
210

100k' 1M 10M 100M

Frequency IHzl

1-115

30

«"

~

'""-

..

STABILlTV",
e,
,
.,
Because t/:l.e 3508J is an e,xtremely fast amplifier with high
gain, stray wiring capacitance'ahd inductarice in power
supply leads can cause circuito.scillation. This can be
prevented by proper circuit layout (all leads or patterns as
short as possible) and by properly bypassing the power
supply lines to common at points close to the amplifier.
In addition, it is recommended that the load be bypassed
by a 50pF capacitor; (see Figure I).
.

APPLICATIONS

JJ:l

l.

COMPENSATION

(aptiO/llII

LOAD
BYPASS
SUPPLY

BYPASS

I50pF

l:. o.M

LOAD

.

FIGURE I. Compensated Amplifier with Supply and
Load Bypassing.
FIGURE 3. External Adjustment of Offset Voltage .

. BANDWIDTH COMPENSATION

The frequency response of the 3508J can be adjusted by
use of an exterrial compensation capacitor from pin 8 to
common as shown iii Figure I. The open-loop frequency
response curves included in the Typical Performance
Curves illustrate the effect of various values of capacitance. The 3508J is stable for gains of 5 or gr.eater
without external compensation (subject' to the same
limits on stray a~d I'olid. capacitance and resistance
levels). A 20pF compensation capacitor will stabilize the
3508J for all values of gain, at the sacrifice of bandwidth
and slew rate.
The circuit of Figure 2 illustrates another approach to
compensation ofthe 3508J. This method yields unity gain
stability wit hout sacrificing slew rate.

IOkn

IN

OFFSET VOLTAGE ADJUSTMENT
Although the offset voltage of this amplifier is only a few
millivolts, it may be desirable in some cases to null this
offset. This is done by use of a lOOk!} potentiometer as
shown in Figure 3.
TEST CIRCUIT - DYNAMIC RESPONSE
The test circuits of Figure 4 are used for measurement of
slew rate, settling time, rise time and overshoot. Both rise
time and overshoot are measured for a small~ outl'ut
signal (Von = ±IOOmV). Slew rate and settling time are
measured for a IOV, p-p. square wave.
'

100en

400n

1Il00 n

OUT
2kn

FIGURE 2. Alternate Method for Unity - Gain
.Compensation of 3508J: -'

FIGURE 4. Dynamic Resl'onse Test Circuits.

1-116

BURR-BROWN@)

3510

I E3IE3I I

Very-Low Drift - Precision
OPERATIONAL AMPLIFIER
FEATURES

circuit accuracy and reliability over temperature
ranges from -25·C to +85·C, surpassing competitive
units rated for only O·C to +70·C.

• VERY-LOW DRIFT· ±O.5I1V/oC max
• VERY-LOW OFFSET • ±6DIIV max

Additional performance features of the 3510 include
high open-loop gain, extremely-low initial offset
voltage, high CMR, very-low thermal feedback, low
input bias current and very-low voltage drift vs
temperature.

• LOW BIAS CURRENT· ±15nA max
• HIGH OPEN-LOOP GAIN· 120dB min
• HIGH CMR • IIOdB min
• VERY-LOW THERMAL FEEDBACK· ±O.IIIV/V

DESCRIPTION
High overall accuracy is offered by Burr-Brown's
3510 Operational Amplifier. It's designed expressly

for use in high gain analog circuits where very-low
drift and high accuracy are essential requirements.
This precision instrumentation grade op amp
provides an economical method to maintain high

Burr-Brown's rigid control of monolithic processing
and its rigid quality control standards result in verylow voltage and current noise in the 3510. It's
specifically designed for use in low level analog signal
processing. Performance specifications are met
exactly by precision trimming at the wafer hivel with
complete testing before shipment. Performance of
the 3510 significantly exceeds that of Burr-Brown's
popular 3500 op amp.

Internallonal Alrpart Industrial Park· P.O. Box 11400· Tucson, Arizona 85734· Tel. 1602) 746·1111· Twx: 910-952·1111 . Cable: BBRCORP· Telex: 66·6491

1-117

ELECT'RICAL SPECIFICATIO'NS
Specifieati~ns '~t::f A = 25"C and -+ISVDC unless otherwise noted Standard specificatil;)ris after warm-up

MODELS

Min

Typ

Min

Max

OPEN LOOP GAIN, DC
2kn Load

120

RATED OUTPUT
±IO
±IO

Voltage

Current
Output Resistance
Load Capacitance

300
I(JOO

"

FREQUENCY.RESPONSE
Uoity Gain. Open Loop. Small Sign" ~~ = ~700pF
Closed-Loop Gain, C = 0, Stabl. Operaiion
Full Power Response. Cc = 0, Ael :::;: 10
.,
Slew Rate, C c = 0, AcL = 10

7
0.5

0.4
;iIO
12
,0.8

INPUT OFFSET VOLTAGE
"
. lnitial Offset. 25"C
vs Temptll - unnulled V...
vs Templll -. nulled V!>,
vs Time
Power Supply Rejection

ISO
2.0
2.5

\

0.2
130
±O.I

110

Thermal Feedback, RI. = 2kn, f = I Hz

INPUl: BIAS CURREN.T
Initial Bias. 2S"C
vs Supply Voltage

,

±20
±0,4

INPUT IMPEDANCE
I II 3
10 II 3

INPUTIIIOISE
Volta'ge;O.1 Hz to' 10Hz

0.8
14
12
12
50
0.8
0.46
0.35

f.= 10Hz
fo= 100Hz
f.= 1kHz

Current. O.IHz to 10Hz
fo= 10Hz
fo= 100Hz
fo = 1kHz

';'.

INPUT VOLTAGE RANGE
Common~mode

Voltage Range. linear operation
Rejection at ±IOV
Maximum Safe Input Voltage

Common~mode

±dV,J-3
110
±V~~

POWER SUPPLY
±I~

Rated Voltage
Voltage Range, derat~ performance
Quiescent Current

'~20

±3
±2.5

±3.5

TEMPERATURE RANGE
, -25

Specification, .(A, B, C)

+85

Operating, derated pellformance,
Storage
8 junction-case
·8 junction~ambient

+l2S
+ISO

-55
-65

40
190

-Specification limits same as 3SlOA
(I) Temperature coefficient specification,s: ~25°C to +85"C for AM. 8M.. CM

-S5'C to +12S"C for SM

1-118

Typ

Max

· ··

±O.4

V
rnA
n
pF
MHz
V/V
kHz

V/"SOC
60

"V

0.5'
0;7

"V/.'C

±IS
±o.25

'

··
'.

·

+12S.

··

··
·
·
··

·
.
··
..
···
··
··
·

"VI"C
IAV/mo

dB
, p.V/V

±15

.'

UNITS
dB

~.

·
··
···
·
···
·

··
·
· ··
·
··
··

-55

, (5)

120
1.0
1.4

·

.±IO

"Min

,

....

3510CM

·
··
·•
·
·· ···

±Z5

±O.I

Differential
Common-mode-

Max

· ···

INPUT DIFFERENCE CURRENT
Initial DifferenCe. 2S"C
vs Temp,l)
vs Supply Voltage

Typ

.'

' ,

·
··
··
·
·· ···

±35
±O.6

vs TempO)'

r"·;

351OBM/351OSM

3SIOAM

±O.is

nA

nA/oC
nArY

±IO·
±O.IS

· ·
· ·
·
·
·· ·

nA

nA;"C
pA/V

Mnll pF
Gn II pF
p.V, p-p
nV IJiii
nV iJiii

nV/Jiii
pAc p-p

pAIJiii
pAIJiii
PAIJiil
V
dB
V -

VDC
VDC
rnA

"C
°C

'C

'CfW
'C/W

TYPICAL PERFORMANCE CURVES
Typical at TA ~ 2S"C and ±ISVDC, unless otherwise noted.

OPEN-LOOP FREQUENCY RESPONSE

,

J

'OIIi

120

'00

\

,

"'lII

40

,

0
2
0.01 0.1

I

,

I

~

('1:"'0

0
\
\

,

'i): ~"''\\

10 00 Ik 10k lOOk IN 10M
frequeney(Hz)

Co:" .0047.uF\

-'''''0.01 0.,

,

,
\

"'lII

60

OUTPUT VOLTAGe VS OUTPllT CURRENT

OP£N-LOOP PHASE RESPONSE
0

J
LLk~±
Vs":tJVco1;.20V
j

-

\,
\

...

>

,
~.

'0 100 Iii. 10k lOOk 1M 10M
FlequencytHIl

Ac

,.

-0_""'......,....->'

_FIGURE 2. Inverting Amplifier.

FIGURE 3. Noninverting Amplifier.

>-"""0 eo

FIGURE 4. Follower Amplifier.

FIGURE 5. Difference Amplifier.

RESOLUTION OF NULLING
POTENTIOMETER

1O,4",V /ppm/"C and must be added to the amplifier's
drift. However, even when using a lOOppm industrial pot,
this figure is ±O.O I", V /"C and can be ignored.

One of the advantages of the 3510 is the ease of nulling the
offset voltage, even with a low cost, single turn
potentiometer. A single turn linear potentiometer can be
used with good resolution. Unlike some competitive, low
offset op amps, the 3510 does not require multiturn pots
or fixed resistors padded with a pot to produce a high
level of trim resolution.
Resolution and range of the offset trim potentiometer at
various resistance values are shown in Table I.
TABLE I. Offset Potentiometer Effects
I

Potentiometer Offset Adjustment Range

Value

10%-90%

0%-100%

Rotation

Rotation

*IOOkfi

±110"V

±2mV

20kfi

±6OO"V

±2mV

IOkfi

±800"V

±2mV

Resolution
at Pot Center

Sensitivity of
,j,V.... /.lT to
Potentiometer
tIIT.C.R.w

IIJ. V I % rotation 1O""Vppm(C

3.S"Vi%
rotJtion

.JO~4J.1V IppmtC

6/AV i% rotation 1O-4IJ.V,' ppm;"C

• Recommended offset adjustment potentiometer.
(I) T.C.R. = temperature coefficient. of resistance

(2) Sensitivity after nulling ±i20",V
value shown. '

or V...: typically the sensitivity is one-half the

POTENTIOMETER
Because the external offset 100kn potentiometer
parallels two internal I kn resistors, the temperature
coefficient of the potentiometer will affect the offset
voltage temperature drift of the 3510 to a very small
degree. In addition, the potentiometer halves have the
same temperature coefficient, therefore the percent
rotation does not drift. Sensitivity of the offset voltage to \
the external potentiometer is very low, only

THERMAL FEEDBACK
Wilen an amplifier achieves the high performance levels
of the 35 10 some effects previously masked by larger error
terms (and now reduced by the 35 IO's high accuracy, high
performance and low error terms) may become
observable. This situation exists with a condition referred
to as thermal feed hack.
Thermal feedback is an error generating condition which
can be caused by the power dissipation and resultant
temperature rise of the amplifier's output stage. This
error is fed back to a previous stage of the amplifier and
alters its usual operation. Normally the input stage is
affected. Tl1\s error is described as a change in input offset
voltage per volt of output voltage change. When the 3510
has a 2kn load the specificatioQ is ±O.I", V / V.
This phenomena is most noticeable at frequencies below a
few hertz and most easily observed on an oscilloscope:
Thermal feedback can add a small error term to the'
"average" temperature effects normaliy described as
input offset voltage drift versus temperature and input
bias current versus temperature.
To minimize the effect of thermal feedback, the 3510
circuits are carefully laid out and thermally balanced to
minimize thermal feedback.

THERMAL RESPONSE TIME
In low drift operational amplifiers like the 3510, thermal
response time is an important performance parameter. In
precision applications the response of the amplifier to
warm-up or environmental change should be considered.

1-121

and

respOnse

FigureS 6
7 show typiciii therina1
of the 3510.
Note that the offset voltllge does not overshoot and that
the response time is very short - less than three minutes.'
Some' competitive lo~ drift operational' amplifiers
require 15 minutes to warm ,up.

>"

18

: = I5

.:a

V-

6

> :; I 2

~~

0';'· 9

~<#=

.&

u

6
3

0

--

Isec I

I

'

'1'

,I

rL--~-_J
Low-_filtei

Following
System

FIGURE 8. High Frequency Filter For Single Stage
,'
'Amplifier.'
,

I

J

=- l
~ 8
1l.
=
'(
'[~

I

>-+~I~h-""""""IV-+-t Part of

Vs - ±15V
3SIOAM

T,=2S:'C

~

-,

",. ___ -,

3jIOBJ.SM

Low-pas~.

r+---iE---.,'=-:'" filter

,"

I

3SIOCM'

2
4
Time (M iOUleS)

I

FIGURE 6. Warm-up Drift.
FIGURE 9. High Frequency Filter For Multistage
Amplifier.

~60

i;!

so I--+~+--If-,--+-+---I

COMPENSATION

"0

>

~

40

o

30H~-:b;;;;;j;-'~-';--"1

!

20

!l,

10

..

=
=
.&

At closed loop gains above lOY/V, the 3510 op amp is
stable without additional frequency compensation. The
amplifier is compensated as shown in Figure 10 for gains
below IOV/V.

u

2

3

4

TiOle(Minutes)

FIGURE 7. Offset Response to an Environmental
, Change.

.~

NOISE
In a high performance amplifier such as the3510, noise
may well, be the, final and limiting criteria fo~ system
accuracy. See specifications and performance curves.
While the 3510 noise is" very acceptable in low and midfrequencies, it is fairly large above 100kHz. Whether or
not this unique characteristic will cause .ser problems
depends on the application of the 3510 and steps.takento
reduce high frequency' noise ,effects.
If circuitry following the 3510 does not respolld to noise
above 100kHz, no corrective steps need to be taken. This
situation is common in applications where a 0.5V/llsec
amplifier is satisfactory., When high frequency noise mus,t
, be reduced, a low-pass filter should be in,stalled in a stage
following the 3510 (filtering at the 3510 itself has little
effect).
Two high frequency.filtering approaches are shown in
Figures 8 and 9.

C c = 4700pF

FIGURE 10. Amplifier Compensation Circuit.
Alternately, the capacitor may be connected between pin
5 and +V" (p,in 7) if the supply is well bypassed to ground.

, SHORT CIRCUIT PROTECTION
The 351Q may be short circuited to ground continuously
without damage. Output shorts' other than to ground
may be tolerated if the "Maximum Power Dissipation vs
Temperature" ratings given in the performance curves are
not exceeded. Power dissipation tan be determined as the
product of (V" - Vou.) X lout. lout undercurrent limit
conditions is specified in the "Output Voltage vs Output
Current" perforQl3nce curve.

1-122

BURR-BROWN®

3521 SERIES
3522 SERIES

113131

Ultra-Low Drift - FET Input
OPERATIONAL AMPLIFIERS
FEATURES
• ULTRA-lOW DRIFT. 11'V/oC max
• LOW INITIAL OFFSET VOLTAGE. 250I'V. max
• LOW BIAS CURRENT. lpA. max
• LOW NOISE
• HIGH COMMON· MODE REJECTION. godB. typ
• WIDE POWER SUPPLY RANGE. ±5VDC to ±20VDC

DESCRIPTION
With input offset voltage drifts as low as II' Vj"C,the
Burr-Brown 3521 IC Operational Amplifier provides
FET input performance combined with drift equal to
the best bipolar Ie's (e.g., BB3500E). The specfacular
performance is achieved through truly state-of-theart hybrid design and manufacturing, including
monolithic FET pairs and active laser-trimming.
The 3521 and 3522 have an exceptionally fast
thermal response. This fast warm-up is achieved
without any heat-sinking.

While low drift and FET input impedance are the
outstanding features of the 3521 and 3522 other
specifications have not been compromised. They are
internally compensated for unity-gain configuration
and the initial voltage offset is guaranteed less than
250/.lV sofor most applications the 3521 is ready to
"plug-in and go." Like other low drift Ie's from
Burr-Brown the 352 I and 3522 have ample speed and
bandwidth for most any application. (Slew rate =
0.6V / I'sec). The high common-mode rejection ratio
(90dB, typ.) enables them to be used as a 0.01%
accurate buffer with low drift and extremely-high
input impedance. The 3521 I 3522 also have very-low
input noise to complement the low drift. The output
is current limited to provide protection for continuous output shorts to common.
The 352113522 are pin-compatible with 741-type
amplifiers, but provide FET input performance
with ultra-low drift while exceeding all other specifications for general purpose operational amplifiers
of the 741-type. BUI r-Brown tests and guarantees all
units to meet all maxI min specifications.

+Vee

OUTPUT

·Vec

International Alrptlrt Induslrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. (6021746·1111· Twx: 91(1.952:11.\1 . Cable: BBRCORP· Telex: 66·6491

1-123

N

~

[;')f:)'~:::~PEC'FICATiONS .
k ...e :::'15'-ECTRICAL

.

MECHANICAL
ITO-99 PACKAGE)

.'V.

,

'.

.'

. Typical at +2S·C. arn:! ;1:15110'& powe¥ slipply cini~
otherwise noted.
'':':
,:,J;' " . "

MODELS
OPEN-LOOP GAlN,:DC ,<
Rated Load, min

~

.;

", .~

."

•.

.

"","

....~21K

3521~

3\i21tt

3521L

3521ft

'~.'~!:fl
.-.;.,.,

;',

RATED OUTPUT

.

+10V
±10mA
1000

FREQUENCY REsPONSE:

,,'-

Unity Gain, Open-Loop

., ,

1.SMHz
lQkHz

.Full Power Response, min

O.6V1i2~

K

.500

M

41'V
21'V
O.3pA·
O.8pA

T

N

\

INCHES
MIN :'MAX

A

:L·

INPUT NOISE
Vo~age"O,OIHz -10Hz, p-p
Voltage, 10Hz - 1kHz; rma
Current, O.OlHz - .10Hz, p-p
Current, 10Hz· 1kHz, rms

~
N

~J

2501'V
±5I'VI·C
±2I'VfOC

±2pA

INPUT IMPED.ANCE

~D

0

INPUT DIFFERENCE CURRENT
Initial differen~: 25·C

FJ

"Lm-

PI.n.

I';

DIM

-20pA

~

~\\
l' ' + IJ

INPUT BIAS CURRENT
Initial Bias, 2S·C, max
(doubles every +l00C)
va Supply Voltage

.

"",,",11111

f

INPUT OFFSET VOLTAGE
Initial Offset, 2S·C, max
va Temp (OOC to +700C), "max
YS Temp (-2S·C to +as·C)
vs Supply Vo~age
vsTlme

'.

re-rl!I!1

94dB

Voltage, min
Curren~, min
O~tput Impedance

.

;,

C···· j

'

:11.0;'

8.51
4.70

0.41

0.53·

1.02
1.02
S·.08 BASIC

0:25
0.25

-

±15VDC

.

.: ~ ,

±5 to±20VDC
±4mA

J

~rc
to +700C
2SOC to +8S·C

·.

TAB

-SSoC to +12S·C
-SS·C to +12S·C

,.as·C to +150·C

i:

0.71

0.86

0.74

1.14

12.7

'.06

2.79

.160

45° B'ASIC
' 2.41
2.67

rTOPVIEWI

TEMPERATURE RANGE
SpeCification .
Operating
Storage

9.40

CONNI;CTION .DIAGRAM

±10V
90dB
±Supply

Current, quiescljtnt

.-

4.19

..."

POWEIi SUPPLY
Rated \/oltage
Voltage Range. derated

~

8.51
1.75

INPUT VOLTAGE RANGE
.Common-mode Voltage
Common-modeJ1ejection
Max. Safe Input Voltage

r
1

MI.LlIMETERS
MIN
MAX

.03"4

45° BASIC
.105
.095

C
i

.'

I

'Speciflcatlon same as for 3S21H.
"-55·C to +12S·C for3S21R.

-Vee

ELECTRICAL (CO NT)
Typical at +2SoC and ±ISVDC power supply unless otherwise noted.
MODELS

3522J

3522K

3522L

3522S

±SOO"V
±10"VloC

±SOO"V
±10"VloC

±500"V

OPEN-LOOP GAIN. DC

Aated Load. min

94dB

RATED OUTPUT
Voltage, min
Current, min

Output Impedance

±10V
±10mA
1000

FREQUENCY RESPONSE

Unity Gain. Open-loop
Ful!l Power Response, min
Slew Rate, min

lMHz
10kHz
0.6V1"sec

INPUT OFFSET VOLTAGE

Initial Offaet. 2SoC. max
vs Temp (COC to +7COCI. max
(-S5°C to +12soCI. max
vs Supply Voltage
vsTime

±1mV
±SO"VfOC

±2S"VloC
±2S"Vlmo
±10"Vlmo

INPUT BIAS CURRENT"
Input Bias, 25°C. max

(doubles every +ICOC,
vs Supply Voltage

-10pA

-SpA

-lpA

-5pA

±lpA

±O.SpA

±lpA

±O.lpAlV

INPUT DIFFERENCE CURRENT
Initial Difference, +25°C

±2pA

INPUT IMPEDANCE
Differential
Common-mode

10110
10120

INPUT NOISE
Voltage. 0.01 Hz to 10Hz. POp
Voltage. 10Hz to 1kHz. rms
Current, 0.01 Hz to 10Hz, p-p
Current. 10Hz to 1kHz. rms

4"V
2"V
0.3pA
0.6pA

INPUT VOLTAGE RANGE
Common-mode Voltage
Co~mon-mode Rejection

Max. Safe Input Voltage

±10V
90dB
±Supply

POWER SUPPLY

Rated Voltage
Voltage Range. derated
Current, quiescent

±ISVDC
±5VDC to ±2OVDC
±4mA

TEMPERATURE RANGE
Specification

Operating
Storage

COC to+7COC
to +85°C
to +15COC

-25~C
~5°C

·Specification same as for 3522J .

•• After Warm-Up.

1-125

-SS~C to +125°C
-55°C to +125°C

TYPICAL PERFORMANCE CURVES
(At +25°C and ±15VDC ~.nle":" .otherwise specified}.

.

"

1000

NORMALIZED INPUT BIAS
CURRENT lis TEMPERATURE

100

:;

./

10

Q...

.: 15
" t:
" :>
,l!!O

g!

V

100

iii

~

~

-so -25

1.0

2.0
1.0

0.5

.0.5

......

80

(!l

,.."'"
0

>

""

80
40
20
0

-

I

iii

J.

~

'J

'iii

Q.

0
0

"-

8

1'\.

"

Q.

lOS

lkO

"

>

0

f

:;
Q.
:;

"ilL

-10

2

11111111
10k
lOOk
Frequency (Hz)

"

-15
1M

I

-

i

16

~

12

I>.

~"

t:-- 1---

0

>

%

4

~
0:

80

0

40

:::;

I
VCM = 10V, Peak

I'..

"

K.

I I

,.o~

]J

1

10 15 20
25
Output Current ( rnA I

>

8

~
o"

4

,

:\.

0
-20
1

12

10 100 lk 10k lOOk 1M 10M
Frequency (Hz)

8

8

4

,

1-126

I'.

,/

12
16
8
Supply Voltage I±V,

20

I::
0

~

~-

l1- ....

~

-_.-.

..

1000 --

Q.

en"
20

r/
II

,.,

Q.

I

If

'0;
0:

/'

12
16
8
Supply Voltage' ±V,

.//

POWER SUPPLY REJECTION VS
FREQUENCY

/

0

0"

50

/

/

o

30

V

E-

I'..

20

2

10,000 r -

0>

E .,
EO:

40

RL = lkO

~

16

1::01
01::

311

6

COMMON-MODE RANGE VS
SU/>PLY VOLTAGE

.."01
~.¥
>-m
"I>.

20

I>.

Vee =±10V

o

20

i

20

iii

10

OUTPUTVOLTAGE VS
SUPPLY VOLTAGE

T A"; +.25°C

Vec =±20V

Vcc =±5V

I

12
16
Supply Voltage I±V,

8

- r......

o

~v

CL;'100pF

0

8

0

'\,

Time(~SeCl

vCY=±15Y

:;

TAj'+85°f-

1\

RL=,lkn,

li

o

1'20

80

f

I

OUTPUT VOLTAGE VS
OUTPUT CLJRRENT

COMMON-MODE REJECTION
VS FREQUENCY

100

'5

0

lOS

VOLTAGE FOLLOWER

:;

" " '\

I::

(!l

.,

~

~
~

TA = -55°C

lOS

107

OUTPUT VOLTAGE VS
FREQUENCY

VOLTAGE GAIN VS
SUPPLY VOLTAGE·

110

~

Source Resistance (01

14

."

lOS

1.OS

Vcc = +5V to ±20V

/

0.2
O. 1

0:1

025 50 75 100 125
Temperature (OCI

/

I

5.0

10Hz-1kHz

2.0

/

..

20
10

O. :2

I::

'iii

/

./

OPEN-LOOP FREQUENCY
RESPONSE
120

100
·so

/

..

5.0

./V
0.00 1

V

20
'10

0.0 1

'poP INPI,J.T I\IOISE VOLTAGE VS
SOURCE RESISTANCE

RMl! INt;'UT NOiSe; Vo!,,. AGE. Vs
SOUR9E R~SISTANCE

50

V

/

0.1

z

V

100

/

100

,.;
10

100 lk 10k lOOk 1M
Frequency (Hz I

APPLICATIONS INFORMATION
THERMAL RESPONSE TIME
Thermal response time is an important parameter in low
drift operational amplifiers like the 3521,3522. A low
drift specification would be of little value if the amplifier
took several hours to stabilize after turn-on or ambient
temperature change. The TO-99 packaging is particularly
well suited for devices requiring fast thermal response.
Figure I shows the typical warm-up drift of the 3521.
Note that the offset voltage has stabilized in less than 4
minutes. Similar warm-up times for some discrete low
drift operational amplifiers range from 7 to 15 minutes.
Offset voltage response to thermal shock can provide
some real sup rises, particularly for amplifiers packaged
in discrete modules. Again the TO-99 package proves
superior. Figure 2 shows that the response to thermal
shock settles very quickly. The. 3521/3522 quickly and
smoothly assumes a new value of offset voltage as
dictated by the drift specification.
BIAS CURRENT EFFECTS
The low bias currents and offset currents of FET input
stages overcome most of the source resistance limitations

50

..:!
50

j:

~powlron

..:!

i

!co

'IS

>

·5

I
I

·10

10

I

"

j

"""-

fI

COMMON-MODE PROPERTIES
The input stage of the 3521 is a monolithic FET pair.
which affords very good matchingbetween the two input
transistors. This close matching makes the 90d Bcommonmode rejection ratio (CMRR) possible. Because of its
excellent common-mode properties the 3521 may be used
as a 0.01% accurate buffer amplifier for inputs between
±IOV. Figure 5 below illustrates typical common-mode
performance of the 3521.
POWER SUPPLIES AND DRIFTS

Note that a power supply change of 40mV will typically
introduce an input offset voltage change of II-' V. Since
power supply drift will have the same effect as offset
voltage drift, the power supply temperature coefficients
of±15V supplies should be about O.I%/"C for optimum
drift performance of the 3521 L.

,

i"-

Time 01 Insertion
Into oven at 7f1<>C

STABILIZED In +25"C
Ambient Air

!:

!

Time Alter Power On Imlnl

Tlmllmln.1

FIGURE I. Typical Warm-up Drift.

FIGURE 2. Effect of Thermal
Shock on Offset Voltage.

:[

IOU
30

_

10
3.0

~

1.0

~

0.1

f.

!

20

:5:

of bipolar operational amplifiers. However, for very
large source resistances or large unbalances in source
resistance (5M!l. and up) the input offset voltage and drift
will be affected as shown in Figures 3 and 4.

~ 300

50

>

/'

30

&

10

i...

./

-

3

~

~
1
:;. 0.3

v

109

105

!

,03

+1

5

~

.5

i

·1

Ii

O. 1
]! 0.03

0.01

~

..i

i

0.03

+2

E

"- 100

.~

-:

104

106

·2
·10

-Ii

+5

+10

Source Resillance fnl

Source Resistance fnl

Input Voitaga fal - VI

FIGURE 3. Typical Effects of
Source Resistance on Initial
Offset Voltage,

FIGURE 4. Typical Effects of Source
Resistance on Equivalent Input
Offset Voltage Drift.

FIGURE 5. Common-Mode
Performance.

1-127

OFF,SI;T. V<>:LTAGE ~o.JUS:r"'.EN;T
The 3521 has a low initial offset (2501-1 V) compatible with
its low drift. However, sqme high accuracy applications
may require external nulling of even this small initial
offset voltage. Virtually any ofrsetvoltage adjustment
method can increase offset voluige drift unless some care
is used.· For example, theinitlal offset. volt~ge of most
monolithic op amps (BB 3500, 741-types, 101, etc.) may
be. nulled using a single pptentiometer, but offset voltage
drift is typically in~reased by about 31-1 V /"C for each m V
of offset voltage adjust. This same relationship will also
hold for the 3521.
.
.

WIRING CONSIDERATIONS (Shielding and
Guarding)
The ultra-low drift, very-low bias current and high input
impedance make the 3521/3522 well suited to.anumber
unique applications. However, careless signal. wiring
C!Pl degrade "system" performance seyeral orders. of
magnitude below the 3521/3522 capability.
'

of

As in any situation where high impedances are involved,
careful shielding is required to reduce "hum" pickup in
input leads. If large value feedback resistors are used,
they should also be shielded along with the ell.ternal input
circuitry.'
.
Leakage curr.ents across printed circuit boa'~ds can easily
exceed the bias current of the units. Perhaps.more
important, unbalanced leakage paths (when is leakage'
ever balanced?) can generate significant input offset
voltages when large source impedances (lOOk!} and up)
are involved. To avoid leakage problems, it is ~ecom- .
mended that the inputs of the 3521 be wired to teflon
standoffs. If the unit must be soldered directly into a
printed circuit board,' utmost care should be used in
designing the board layout. A "guard" pattern should
completely surround the two input leads and be connected
to a low impedance point at the common-mode input
voltage. Figure 6 shows suggested guard connections for
various amplifier feedback configurations. Theamplifier
case should be connected to any input' shield or guard via
pin 8.

INPUTo-.,.,."..,..._---WIr-"

INVERTING AMPLIFIER

8

INPUT

FIGURE 7. Single Potentiometer Adjust at Op Amp
Trim Terminals.
Advantages: .
I. Simplest circuit.
2. Compatible with mostIC 'op·amps.
Disadvantages:
I. Drift increased by circuit about 0.751' V j"C for 3521.
TEMPERATURE COMPENSATED
POTENTIOMETER OFFSf;T VOLTAGE ADJUST
If the circuit in Figure 7 is. replaced with a circuit which
."drifts" with temperature. nulling the offset voltage wilI
not increase the drift .by so large an amount. The circuit
shown .in Figure 8 may be used to null initial offset
voltage and drift will increase only about 0.51' V fOC for
each m V of offset adjust. In the case of the 3521. this
zeroing circuit will typically add at most O. 141' V '''e.

NONINVERTING AMPLIFIER

'Ra MAY BE USED TO COMPENSATE
FOR VERY LARBE SOURCE RESISTANCES
IRS> 6Mn.1 R3 =RS
RR
.
NOTE: - R
I R
2 · MUST BE LOW IMPEDANCE'
2

,+

V+A
oUTPUT_'V7

B20kn

T,-

.54~

v.IJ~..
(BOTTOM VIEWI

GUARo-$

'2N3906 OR SIMILAR,

BOARD LAYOUT FOR INPUT GUARDING
WITH TO-99 PACKAGE.

. FIGURE 6. Connectio)1 of Input Guard ..

FIGURE 8. Temperature Compensated Potentiometer
Null.

1-128

3523 SERIES

BURR -BROWN®

IElElI

Ultra-Low Bias Current FET
OPERATIONAL AMPLIFIERS

FEATURES
• BIAS CURRENT. O.lpA. max
• OFFSET VOLTAGE. 50UpV. max
• VOLTAGE DRIFT. Z5pV/oC. max
• INPUT IMPEDANCE. 1013 0
• NoIse (IOHzl. O.003pA. POp

DESCRIPTION
The Burr-Brown 3523 Series amplifiers are the first
IC operational amplifiers to achieve sub-picoampere
input currents without exhibiting excessive offset
voltage. voltage drift and voltage noise. The high
common-mode rejection. ultra-low bias current, and
10130 input impedance of the 3523 make it the best
choice for a 'variety of buffer and electrometer
applications. These include pH measurement. photocurrent amplification, long term integration, and low
droop sample/hold or track/hold applications.
Because its input offset voltage is laser-trimmed to
less than 500",V, the 3523 can usually be used without
offset nulling. This is a distinct advantage in
applications where it is desired to locate the 3523
near the signal source (e.g., in a signal probe).

The package of the 3523 is designed to preserve its
ability to measure ultra-low currents and to avoid
noise pickUp. The case guard (pin no. 8) may be
connected to a point which is at signal potential. This
minimizes leakage current input from pins to case.
Also. it shields the amplifier's sensitive input
circuitry from power line frequency "hum",
switching transients, and other sources of electrical
noise.
Bias current specifications of the 3523 are guaranteed
after warm-up in ambient air with no heat sink. Thus,
the ultra-low bias current specifications become even
more significant since internal power dissipation can
easily raise case temperature by 20·C in many
applications.
The bias current on many FET amplifiers is a strong
function of applied common-mode voltage. This is
not the case with the 3523. The input stage design of
the 3523 make the input bias current virtually
independent of the common-mode voltage over its
full range.

Inllmlllllllli Airport Induslrlal Park· P.O. Box 11400 . TUCIDD. Arizona 85734 • Tel. (6021 746·) 111 • Twx: 9111·952·1111 . Cable: BBRCORP • Telex: 66·6491

1-129

SPECI FICATIONS
Specifications ty.pic~ ,at .~

f>c and ± 15 V,de Power Supply unless otherwise no~ed.

..MECHANICAL

ELECTRICAL
\

MODELS

l523J

I·

OPEN LOOP GAIN, de no load
I kn, load, min

RATED OUTPUT

T'~99"

J

l5ZlL

10jldB
94 d.B,·.

,

Voltage, min
Current min
. Outpul Imp.danee

l52lK

, ....,,'

1.040")

VS.

tSO "V/OC'

I

±soo ~V

pA

I

-0.25 pA

Time

INPUT BIAS CURRENT
Initial bias. 25°C. max
(double. every + 10°C)
'S. Supply Vollage

-o.~

Initial difference, 25°C

to.2 pA

I

I

1 -0.1 pA

to.1 pA

I

to.05 pA

INPUT IMPEDANCE
10 12 n
10 13 n

Differential
Common Mode

10 Hz - 10 kHz, rms

Current, .01 Hz - 10 Hz, p-p
10 Hz - 10 kHz, rm.

4"V
2 "V
.003 pA
0.01 pA

CASE

Common Mode Vollage
Max. Sare Inpul Voltage

(a

Dimensions in inches are in parentheses.
Pin materiai and plating compo'sition
conform to Method 2003 (solderability)'"
of MiI-Sld·883 [excepl paragraph 3.21.

TOP VIEW

INPUT VOLTAGE RANGE
Common Mode ,Rejection

~.

CONNECTION
DIAGRAM

INPUT NOISE
Vollag'., .01 Hz - 10Hz, p.p

L185~)

tSOO "V
'25 "V!"C

to.OI pA/V

INPUT DIFFERENCE CURRENT

r4.69mm

-1-

BOTTOM VIEW

±H,,,V/oC

't525"V/mo
"V/V

,.370"'dl8.
max.

.48mm
dia.
0:19")
ma",

INPUT OFFSET VOLTAGE
t\ mV

H

mill<.

8.51rt"n

1.27mm
l.OSOH)

"

VMHz
),0 kHz
0.6 V/"see

Inilial Orrsel, HOC, max
vs. T~mp (0° 1.0 70°C), max
vs. Supply Vo~tage

9.39mm
1.310 ld'a

~

FftEQUENCY RESPONSE
Unity Gain, Open Loop"
Full Power Response. min
Slew Rate, min

~

1.02mm

tlO V
HOmA
loon

..

.'

.

10V

'

S

+20

"\

(;

>

~

0

600

0

500

.;;;

0.

400

is

300

~
~
0

200

c

Q.

-20
1

10

FREQUENCY CHARACTERISTICS
os. SUPPL Y VOL TAGE
1.2 ......,-,-,.......,.--,.--,.--,.--,.,....,....,

,

'(ij

>

1\

~

Frequency· (Hz)

H-+-+-d -l-c:.I....~=*---I

1.1
1.0
0.9

0.8

.~

Qi

\.

0.7

a:
0.6

100

o

100 lk 10k lOOk 1M

.,

700

5
.~

"\

.~

Cl

)=+lbv
s 'RL>10Hl f---

"\

+60

.....-..-:... Amp,'ifie; No'jse '

.1 .......-'-...I..:-.......--'-,,.-J-......I,..,...."--'
105
107
109
1011
10 13
tiource Resistance (.n I

800

I

"\

Source Resistance

Johnson Noisel
Amplifier Noise

107
109
1011
1013
Source Resistance (il)

OPEN LOOP FREQUENCY
REPONSE
+100 10-

I

0.5~~~~~~-b~-+-+~

\
25 50 75 100 125 150 175 200
Ambient Temperature (oC)

Supply Voltage (± V)

Small Signal Bandwidth
_ _ _ Slew Rate

OPEN LOOP GAIN os.
SUPPLY VOLTAGE

OUTPUT VOLTAGE os.
OUTPUT CURRENT
20

110

OJ

~

I_I
--

,.~_+1

105

Cl

, - - _~soc

i

95

, - - ~SOC

(;

0.

g

~

:l,

oJ

c

ll.
o

90

>

8

e"
0"
o

12
10

2 4 6 8 10 12 14 16 18 20
. Supply Voltage (±V)

6
4
2
0

""

a;
~
0:

:;;
0

+60
+40
+20
0

I

Vs=±15Vdc
VCM=±10V -

I I ........
5

,

10 15 20 25

T~;~1250C ....

100

:!!
a:

"1\

"

6

5

~

4

>
i5.

3 TA=+25 0 C
"I I I
2

u

I r- "\.
~Jv '\:.

;;~

iii

"

~

I

~±10V

E

=!

'\.

V s -ct.1SV

,0.

- - f - TA;-5r~, - ~ I<:

en

a

30 35 40

COMMON MODE REJECTION
os. SUPPL Y VOL TAGE
110

I

+80

.......

~
2

Output Current (± rnA)

COMMON MODE REJECTION
os. FREQUENCY
+100

~

I I

14

S
~

85
80

VSI=±~OV

16

Q.

100

c

.~

18

""G

ds06

SUPPL Y CURRENT vs.
SUPPLY VOLTAGE

8

:;;

10,000

~A~+250Ic

l" TA=~55bc

~

>
3
c

0

90

"fi

'"
a:
>

80

0

i-

6

8 10 12 14 16 18 20 22
Supply Voltage (± V)

POWER SUPPL Y REJECTION
RATIO vs FREQUENCY
Vs=±15V
TA=+25 0 C

1,000

100

G

0

4

,. I
T r n5

I

/

L.I~

10

i5.
0.

"

en
-20
1

10

100 lk

10k lOOk 1 M

Frequency (Hz)

70 2 4

6

8 10 12 14 16 18 20 22

Supply Voltage (±. V)

1-131

11

10

100

lk

10k lOOk

Frequency (Hz)

· The ultra-low bias current and high input impedance of the
'. 3523 are well siiited to a number of challenging applications.
In order to:fully benefit from the outstanding specific..tions
of this unit careful layout; shielding and guarding is required:
Careless signal wqing or printed circuit board layout can
easily. degrade circuit performance several orde"rs of magni' .
tude below thecap~bilityofthe 3523.

30pF

1000 Mr!

>--6--.V0

As in any situation where hi8h impedances are involved,
careful shielding is required to reduce "hum" pickup in input leads. If large feedback resistors are used, they should
also be shielded along with the external input circuitry; The
metal case of the' 3523 is connected to pin 8 and is not
connected to 'any internal amplifier circuitry. Thus it is
possible to~se the case as. a shield to reduce noise pick~up.

out

~-

Leakage currents across printed circuit 110ards' can easily
exceed the bias current of ·the 3523. To avoid leakage problems;· it is recommended that .a Teflon IC socket be used
or that at leasf the signalinput lead of the 3523 be wired
to a Telfon standoff. . If this is not done and instead the
3523 is to be soldered directly into a printed cin;uit board,
utmost care must be uSed in planning the board layout. A
"guard" pattern should completely surround the two ampli;
fier input leads and should be connected to a low impedance
point which is at the signal input potentia!. (See Figur~ I) .
The amplifier case, pin g, should .also be connected to the
guard. T~s insures that the entire amplifier circuitry is
fully surrounded by the guard potential. This minimizes
the voltage placed across any. leakage paths and thus reduces
leakage currents.

Cleanliness is also a prime concern in ultra low bias. current circuits. It fs recommended that after installation is
complete the assembly be. washed with a low residue solvent
such as TMC Freon followed by rinsing with deionized
water. 'The use of some form of high dielectric conformal
coating such as a good two part urathane should be considered if the assembly will be used in air environment which
could deposit contaminants on the low current circuitry.

v-

FIGURE 2. Ultra Low Current to Voltage Converter.

Guard

V out

+

Case

Vout=Vs

Figures' 2; 3, and 4 show typical applications using the
guard and case shielding.

O~ffi'V~'~

+

(,.+ ~f)
\:

RIO

FIGURE 3. Ultra High Input Impedance Noninverting Circuit.

>-......-<1
+
v

•

out

~"

~-

GpARD .;f

(BOTTOM VIEW)

80ard layout for Input Guarding with Guarded TO-99 Package.

FIGURE 4. Ultra Low Drift Integrator.

FIGURE I. Connection of Case Guard and Input Guard.

1-132

BURR-BROWN®

3527

IElElI

Low Drift"- Low Bias Current FET Input
OPERATIONAL AMPLIFIER
FEATURES

APPLICATIONS

• LOWER PRICED

• CURRENT·TO·VOLTAGE CONVERSION

• ULTRA·LOW DRIFT, 2/.1V/oC, max

• LONG TERM INTEGRATION

• LOW INITIAL OFFSET VOLTAGE, 250/.lV, max

• LOW DROOP SAMPLE/HOLD CIRCUITS

• LOW BIAS CURRENT, 2pA, max

.. PRECISION VOLTAGE AMPLIFICATION

• LOW NOISE

• HIGH INPUT RESISTANCE BUFFER

DESCRIPTION
The Burr-Brown 3527 is a precision operational
amplifier. It offers excellent performance at
moderate cost through the use of hybrid
construction. monolithic lCs. matched FETs. thinfilm resistors. and active laser trimming.
The 3527 low. initial offset voltage (250/.lV max)
allows higher design accuracy at lower installed cost.
Costly pots and external nulling of the offset voltage
are not required for most applications. Also. higher
system reliability is achiev€\d by using fewer parts.
The offset voltage temperature drift of the 3527 is
exceptionally low (2/.1 V!"C max) and is compatible
with the best bipolar amplifiers (BB3500E). It is

achieved by laser adjusting the offset during
manufacture and means that high system accuracy is
maintained over the temperature range.
The low bias current (guaranteed 2pA max) allows
the use oflarger feedback resistor values. and smaller
bias current errors are realizable.
Of course. all the other desirable features of high
quality op amps are engineered into the 3527. It has
low input noise. is free from latch up. is short circuit
protected for continuous output shorts to common.
is internally compensated for unity gain stability. and
is pin compatible with 741 amplifiers. Guarding is
achieved by the pin 8 case connection.
for increased reliability screening. consult BurrBrown.

Internatlonll Airport Indualrlil Park· P.O. Box 11400· Tucson. Arlmna 85734· Tel. 1602) 740-1111 • Twx: 910-952·1111 • Cable: BBRCORP • Telex: 66·6491

SPECIFICATIONS
, ELECTRICAL",

-

Specifications typical at TA = 25°C and +15VDC supplies unless otherwise noted,

.MODELS

I

\

OPEN LOOP GAIN, DC
No Load
RL =2kn

' ~'

"

3527AM
Typ
Min
Max

I

35271M
Min I Typ I Mill<

112
108

100

I Min

3!127CM
Typ I Max

'MECHANICAL to-99.
PACKAGE

Units
dB
dB

'.

Order Number: 3527AM, 3527BM,
3527CM

RATED OUTPUT
Voltage
Current
Output Impedance
Load Cap~citance ,

±10
±10

FREQUENCY RESPONSE
Unity Gain, Open Loop
,Full Power Response ,,'
Slew Rate
Settling Time (0.01%1

±12
±20
600
1000

INPUT OFFSET VOLTAGE
Initial Offset, 25°C
vii" re!T1P, (-25°C to +85OCI
YS. Supply Voltage
vs. Time

"

INPUT liAS CURRENT
, Initial Bias. 25°C
vs. Temp
vs. Supply Voltage

,

".,

-,-

Vlpseo
'.'

±200
±5
±75
±20

±500
,±o10

-2

-5

,,~:.'

.

':

±100 ±250
'±2 '.
±S

±100

I

I

-0.7

-2

"

..

-2

-5

I

I

J

I

1012
,1015

INPUT NOISE
Voltage, f. 10Hz
f." 100Hz
f,,= 1kHz
f. = 10kHz
0.3Hz to 10Hz, pop
10Hz to 10kHz, rms
Current, 0.3Hz to 10Hz, pop
10Hz to 10kHz, rma

NOTE:
Le.ds In''true position within .0'0"
1.25~m).R"

:

N.u~mbers ma~ not be m.~k.d on package.

INCHES

.DIM
A

e
c
0

POWER SUPPLY
Rated Voltage
.
Voltage Range, derated performa""!
. Current, quiescent
.

.,
'SpecIfications same as for 3527AM.

..

G

±15

±5
2.6
-25
-55
-65

+85
+125
+150

°C
°C
°C
°CIW

235
12.25
7.95

16.25
10.65

28.25
19:85

MIN

MAX

.310
.335

8.51
7.75

9.40
8.51

.185
.165
.016
.021
.010
.040
.010
.040
.200 BASIC
.028

.O~

.02'

.04'

M
N

..

.335
.305

MILLIMETERS

MAX

H

L

VDC
VDC
mA

±20
4

MIN

J
K

.1

TEMPERATURE RANGE lambientl
. Specification
Operating
Storage
'8 junction-ambie.~t

F

V
dB
VDC

MMC at seating plane.

Pin numbers shOWn for ref.renee only.

nV/y~

I

.000
.110
. 160
45° BASIC
.105
...0

4.70
4.19
0.41
0.53
0.25
1.02
0.25
1.0~
5.08 BASIC
0.71
0.74

0.86
1.14

....
-

12.7
2.79
45° BASIC
2.41
2.67

Pin matcrial and plating composition
cOll:form to mcthod 2003 (soldcrability)
of MII.-STI>-883 (cxc.:cpt pumgruph 3.2),

$

CONNECTION DIAGRAM

"Doubles every +10'C.

ITOPVI.~)

1-134

t

N

--,-

~J

pA

nVl.JHz
nVlv'Hz
nV/v'Hz
pV
pV
fA
fA

±ilVSIT
76
±Vs

~

+.~Y7

E

INPUT VOLTAGE RANGE
Common"mode Voltage Range
Common,mode Rejection at ±10V
Max. Safe Input Voltage

1

.:r '.
"<~~

n
n

75
35
30
25
2.6
3
15
60

,

I

1

;n.11111

'L~

pA
pAN

±O.31

FJ

Plan., -J...-D

pVN

'.

, Commonwmode

~

•

c;

1

s...

pVlmo,

±5

INPUT IMPEDANCE
Differential

;

pV
±250
±2·· 'IlVlo·C'

±:r

Weight: 1 gram.

,~F:l
r-;-rlll !I

MHz
kHz': ,

"

INPUT DIFFERENCE CURRENT
Initial Difference, 25°C

PRICE
1-24
100-999

,,'

1
14
0.9
'45

10"
0.6

~

,

V
mA
n
pF

TYPICAL PERFORMANCE CURVES
At TA

= +25°C and ±15VDC supplies,

OPEN-LOOP FREQUENCY
RESPONSE

o~

12

100

\
0
0
0

f

11

"

f

1'\

,
1'\

ai

"

90~

.!
'" 105
g

1

100

:

0
5

RL~

1

1

:,.....Slutput
Input

1

0

r
~

.5
80

=

100

iii

1_
=;

10

V

1

-g~

v

-55 -25

20

0.4 0.6
Time I~seci

0.8

o
m

k

~_

100

""-

O. 1
0.0 1
-15

·10

(oCI

0

/
fe

±Vcc

=15VOC

~'r-~~~~~~~--1

~ 60'r--+--+--+--+--+~

~
.§

O. 1

fe

401r--+--+--+--+--+~
20
O"_--'--+--'---;-!;-.J..-~
o
,,~
1!l.
2~
Common-Mode Input Voltage {±Vl

150

'0

z

-~

COMMON-MODE REJECTION
~IOO

o

il.0

1"-

~

8

20
0
10

.......

r-.....

1

........ r-.....

2

100

100 1k 10k 100k 1M
Frequency \Hz\

1-135

~

POWER SUPPLY REJECTION RATIO
~10,OO 0

/

...II
c:
>-

100 ;;;7

8;

./

c1l
RSw.,

o

1

10

100 1k 10k lOOk 1M
Frequency I Hz I

J

QUIESCENT SUPPLY CURRENT

10
1

~600

i

i300

3 T,. "" _55°C-:\TA == +25°C

~ +12~'C
I

I

o 01~~--,~0--~-,~5~~~2O
Supply Voltage (±V I

10

100 lk 10k 100k 1M
Frequency (Hz I

MAXIMUM POWER DISSIPATION

<6
E
E 5f.--f--+--+--+---+----j
e

·1

-5
0
+5 +10 +15
I nput Voltage I V I

-10

.~ 1,000
Rs-1Mn--

50

E 2, T.

1"-

·15

.2

\

c1l

1"-

-3

,i!

8 4 f---f--+--+--+---+----j

.",

g

/

~ 250
.s& 200 l
:g \\

~'20

~40

1
0

0.0 1

1
103 104 105 10& 107 lOB 11)9
Source Resistance (n)

~60

2

/

~ aooTOTAL INPUT NOISE VOLTAGE

=0.3Hz to 10Hz ./
./

l

20

INPUT OFFSET CURRENT

0.00 1
-55 -25 . +5 +35 +65 +95 +125
Temperature lOCI

·5
0
+5 +10 +15
Input Voltage IVI

=10Hz to 10kHz

i'00'r--+--+--+--+--+~

:;

~o
~

.......

./

COMMON-MODE REJECTION

~'20

;

1

~

~

100 lk 10k lOOk 1M
Frequency (HZI

10

E

PEAK.TO-PEAK INPUT
NOISE VOL TAGE-

1
103 104 105 106 ,107 108 tog
SOurce Resistance (n 1
'Includes contribution
from source resistance.

u

~i

~~

/

...-

\

3

V

0

\

1

+5 +35 +65 +95 +125

10

= +10VOC

Vee = +5VOC

0

30

,/

100

\

iii

>

~

Vee

5

INPUT OFFSET CURRENT

1000

§

~

.......

10
15
Supply Voltage (:tV I

INPUT BIAS CURRENT

RMS INPUT NOISE VOLTAGE'

f

1

Vee:: +15VDC

0

1.0

10k

~

100

1

RL -1kn
C = 100pF

0.2

a

_ 1000

~

~

1

Vee = ;20VDC

)

-20

;;;
E

Temperature

5 Vee - ±15VOC

5

0

-1

.~O

0.01
0.00 1

0

1-

i" §" 10

~

1

=1kll

0

-30

100

V

.!::!CJ
'if
O. 1

§
Z

V

15

"\

INPUT BIAS CURRENT

1000

=±20VOC

RL

TRANSIENT RES'PONSE

E

l

20 40 60
Time (j.lSeel

1

+3 0

1

-1 5

1

i

10

>.+20

,

0

5

o V.c

'\

1

OUTPUT VOLTAGE vs
FREQUENCY

30

0

120

+45 Iii

'\

OUTPUT VOLT AGE vs
OUTPUT CURRENT

VOLTAGE GAIN

5

12

RL;;a.10kfl

1\

unless otherwise noted.

(JJA ::

E

235°CIW

§500

~ 400

.

~200

roo

0

"""" "-

""

['\

50
100
150
Ambient Temperature 1°C)

APPLICATIONS
INFORMATION

;; 25
.3

&

~

THERMAL RESPONSE TIME
Thermal response time is an important parameter in low
!lrift operational amplifiers like the 3527. A low drift
specificatiori would be of little value if the amplifier took
several hours to s~bilize after turn~on or ambient
temperature change. The TO-99 packaging is partiCularly
well suited for devices requiring fast thermal response.
Figure I shows the typical warm-up drift of the 3527.
,Note that the offset voltage has stabili~ed in less'.than I
minute. Similar. warm-up times for some low drift
;opera.tional amplifiers ranges from 2 to 15 minutes.

~ 15

!
0

10

a.
E.

5

l/'"
j

:;

.
.

V

.S

C>

0

C

~

.0

-5

Q 15 30 45 60
Time From Power Application (seC.I

FIGURE I. Typical Warmup Drift.
50

Offset voltage respopse to thermal shock can. provide
some real surprises, particularly for amplifiers packaged
in discr~te modules. Again the 3527 TO-99 package
proves superior. Figure 2 shows that the response to
thermal shock settles very quickly. The 3527 quickly and
smoothly assumes a new value of' offset voltl\ge as
dictated by the drift specification.

-L TI=+125 c

V

00 TA
+25°C

0

j

50

00

1

~

0

GUARDING AND SHIELDING
The ultra-low bias current and high input impedance of
the' 3527 . are well-suited ·to a number of stringent
applications. However. careless signal wiring of printed
Circuit board layout can degrade circuit performance
several orders of magnitude below the capability of the
3527 .
. As in any sitUation where high impedances are involved,
careful shielding is' required to reduce "hum" pickUp in
input leads. If large feedback resistors are used. they
should also be shielded along with the' external input
circuitry.

,

50

o 25 50 75 tOO 125
Time From Heat Application Isecl

FIGURE 2. Effect of Thermal Shock on Offset Voltage.

'"A~.R:.
. i . .

Output

.....

Leakage currents across printed circuit boards can easily
exceed the bias current of the 3527. To avoid leakage
problems, it is recommended that the signal input lead of
the 35271?e wired to a Teflon standoff. If the 3527 is to be
soldered dire<:tly into a printed circuit board, utmos\care
must be used in planning the board layout. A "guard"
pattern should completely surround the two amplifier
input leads and should be connected toalow impedanpe
point which is at the signal input potential.
The amplifier case should be connected. to any input
shield or guard via. pin 8. This insures that the amplifier
itself is fully surrounded by guard potential, minimizing
both leakage and noise pickup. Figure 3 illustrates the use
of the guard ..

Input

R3

-

'j~VERTING AMPLIFIER

oL..:;
. . _R_3_:. .;[~__r_j;...'~om._
-

R,

FOLLOWER

NONINVERTING AMPLIFIER
'R3 may be used to compensate
for Very, large $ource" reSistances.
.,
R, R2/(R, + R,I
~ust be LOW impedance.
Board layout for Input Guarding
with TO-99 Package.'

(BOTTOM VIEWI

+\(~9

(\

. Output <::).,.
5

0
-Vc,c

.~8
01

4,

0

'.

Guard

FIGURE 3. Connection of Input Guard.
OFFSET VOLTAGE ADJUSTMENT
Although the 3527 has a low initial offset voltage
(250~ V), some applications may require external rtulling
of this small offset. Figure 4 showstherecommeniled
circuit for adjustment of the offset voltage~ External
offset voltage adJustment changes the laser adjusted
offset voltage tempe.rature drift slightly. For each
microvolt of offset adjusted, an additional drift of
±O.002~ Vi "e is induced.

FIGURE 4. External Nulling of Offset Voltage.

1-136

.

!>.
,.,-3>
,<:-1l

'"

RL = 2kO
RL = 10k
V. = ±IOV
f=DC
RL=OO
Small Signal
R" = 2kll
RL = 2kll
to 1%
to 0.1%
to'O.OI%

±IO
±12
±S

30

T. = 25'C
·25·C .; T, .; +85'C
±Vn ·= 15Vto20V.to5V

Current,Noise ne:nsity

Current Noise

·.'

T. = 2s'C
= 8S"C

-40

at T"

T A ,= 25°C
at T. = ~5'C

'.
, ·300'
-«l

·

·10

··
···
··

··
···
··
··

0.25
0.25
0,25
0,25

f. - 0,3Hz to 10Hz

7
26

Storage

±S

±20
±2

f.-1Hz
f. = 10Hz
f. = 100Hz
f.= 1kHz

TEMPERATURE RANGE (ambient)
Specification
Operating. derated performance

±200

±40

6
4

··

\

±4V..j-3)
74

I

±20
1.5
+85
+125
+150

·25
·55
-65

TABLE I. Electrical Specifications

1-138

±SOO
±IO

±75
·15

MHz
kHz
Vi,....

"s,
"s
tns
pV
pVi"C
pViV

p.Vim o
fA
pA
fAiV
fA
pA

011 pF
011 pF
nVivHz
_VlvHz
_VlvHz
nVlvliz
nVlvHz
pV. pop
IJV. rms

0.15
0.15
0.15
0.15

fAIVH,z
fAlv Hz
fAlvHz
fAIV Hz

5
20

4
15

fA.nns

fA, pop

·

86

·
· ·· ·· · ·· ··
·•
.•.·
·· ··
•
86

'

V
V
rnA
kO
rnA

0.2
0.2
0,2
0,2

·
·

80

±15
±S

'

±4

±V...,

Current. quiescent

±2SO
'±S

~.,.

±SO

f. = 0.3Hz to 10Hz
f. = 10Hz to 10kHz

POWER SUPPLY
Rated Voltage
Voltage Range. derated performance

,,'.,"

...

475
120
55
40
40

66

,

·ISO
·30

·20

10" II 0.8
10" II I

Linear Operation
f= rx;.V<'~ = ±IOV

•

I

f. = 1Hz
f.= 10Hz
f. = 100Hz
f. = 1kHz
f. = 10kHz

"

'

±8

Max. Safe Input Voltage

"

«-.~

±IOO
±2

INPUT VOLTAGE RANGE

"

'

±SOO
±IS
±IOO

±S
±25
20

fn = 10Hz to 10kHz
Common-mode Voltage Range
Common-mode Rejection

I

,"c"-

±200

Common-mode

Voltage Noise

"

II
0,7

;,-

dB

,~

ISO
I

INPUT IMPEDANCE
Differential
INPUT NOISE
Voltage Noise Density

3

, 0..7
5
0.3

·
··

±12

±13
±IO
LS
19

93

·
·
·· ··
··
•· · ·". · ·
·
·
".
. ···
···
··
··
.'· ·
·., ·
90
98

70

· ·

·

V
dB
V
V
V
rnA
·C
·C
·C

TYPICAL PERFORMANCE CURVES
= +25"C, Vl (,

(T \

~IOO

g:r

,

OPEN LOOP TRANSFER
CHARACTERISTICS VS FREQUENCY

120

~

VOLTAGE GAIN VS SUPPLY VOLTAGE

RI.! 2kn

80

~

"'
~

60

\:

§40

r\.

~

oI

10

100

Ik

10k

""
'"'"

0

f\

020

..

+45

*" ,
"
Z

"~

R,"

'2l"

90'"

'"'"
!!J

~25t--+--t-~~-+--~-~

-<

ii

~

:!!.IOO

~20

Z

:;:

"' 95

.....

T, == +8'''('

~

o

80

10k

§:

,

Vn · = +ISVDC

.
~

+I0r--+--r+-+--+_"'--I

I
I

10

100
III:
10k
FREQUENCnHz)

I-

~

::>

~ -5t---~---+--_I----f---~---4

:"'0..

::>

o

..o

lOOk

1M

-IO~-~-+----t
0

10

100

Ik

10k

lOOk

50

1M

FREQUENCY (Hz)
FREQUENCY CHARACTERISTICS
VS AMBIENT TEMPERATURE

~

..

~

OllTPUT
~ ISPliT
~ 0t--+I--+-_I---f--+--4

~

~

I

;+51---;r~-+--~----t---~---i

",

§

TRANSIENT RESPONSE

+100

Ik

~

\.

Vn · =/±5VDC

o

;;

o 100

V,," - +IOVDC

VOLT AGE FOLLOWER
LARGE SIGNAL RESPONSE

\

I-

I

1.3r--T"-""'-""'-""-""'--'

3

1.21--+--+--+--+--I---f

1.2

R,.=2kll
= SOpF
An =+IV"V

c,

100
150
TIME (p~c)

~

:;i

L

>

!;;lI.O

" -s0
::
"o

V-

R." =2k!l

-100

C," = SOpF
An = +IVIV
4

+-+--+--+--;--;

0.• 1-.......

0.8

0·~3.,5,...-_1t,.5--+,I,5,...~+~25,...-+4~5-~+6~5--+~85

O. 7

.
10

6

~O.9

V

STABILIZATION TIME OF INPUT
OFFSET VOLTAGE FROM POWER TURN-ON

300

T,=1 2n,

,

T. =

T,,=

+25'C

+8S DC

J'
/

SO

I(

I/'

;;

>
~

~

1M

l/

.. 100k
Z

o

~

\0 k

/

i;l

...::;'"

k

o

25

SO

75

100

0

o
SO
100
ISO
200
250
TIME FROM HEAT APPLICATION (sec:)

1-139

~

0

/'

J

10""

w

TIME FROM HEAT APPLICATION (.ee)

20

10M

~
.. 100

0

IS

10

POWER SUPPLY REJECTION
RATIO VS FREQUENCY

INPUT OFFSET VOLTAGE VS
THERMAL SHOCK VS TIME

--

~~.\.

SUPPLY VOLTAGE (±Vn )

TEMPERATURE ("C)

TIME ("sec)

SO

200

§ ~ ~~ntwL ~

"I-

00

L

FREQUENCY CHARACTERISTICS
VS SUPPLY VOLTAGE

~I. I

"' +50

so

30

\

;:!:

~

10
IS
20
25
OUTPUT CURRENT (rnA)

OPEN LOOP OUTPUT
RESISTANCE VS FREQUENCY

~

= ±20VDC

20

10
IS
SUPPLY VOLTAGE (±V)

5

OUTPUT VOLTAGE VS FREQUENCY

VeT

~ 10

85

10M

R, ='2kn

~

>

I3S

IM

""';!:IS

I"""
i""""
~
T S"C,__+-_-f
090 t-_+_-+__;,_=...;-2::c

i\

lOOk

2kn

105

"'"~ "
~

-45

In
C":I

30 OUTPUT VOLTAGE VS OUTPUT CURRENT

t10r--T""-T"-""'-""'-""-'"
J

FREQUENCY (Hz)
60

= ±15VDC unless otherwise noted)

10

100

Ik

10k

FREQUENCY (Hz)

lOOk

1M

rNPUT BIAS CURRENT VS INPUT VOLTAGE-

INPUT BIAS CURRENT VS TEMPERATURE

00

1000

I

.~
!

Z
'~IOO

'"

~:S 16
'" I

/

~

V

:;:

~. I ,

'::;
,~

'" ,0

I

~

V

V
00

,

l/

50

~

:100

.15211\M

13

I

If:
"'o

Iii

.

"

~I

.l52!HM

[;l'

~

'JS2JC:'M

SO

0

-10

+85

S

I
0

~
+5

INPUT VOLTAGE (V)

-35

/'

"
+s

-IS

+25

+45.

+65

+85

TEMPERATURE ("C)
PEAK-TO-PEAK INPUT NOISE VOLTAGE
Ik ...._..,..:;VS;;.;S;:;O,.U:;.:R.:;C;,;E;;R.:;E;;:S;;;IS;.;TTA;.;N;;C;;.E"T.:I~..,

'f

75

~,OO~--~---+--~~~~-+--~--~

!-

z

"'
'"'" 'SO

~

;:>

U

t;;

'"

V

~

"'"'0

~ 10

!-

~

;:>

:;:

~

:0I

Z.OO I

+10

10kr-_..,.V_S;.S;.°TU;.;R_C;.;E~R~E;.;S_IS;.;TTA_N,;.CE~'r-"/'7'''

.

~

I

./

/'

~

~

RMS INPUT NOISE VOLTAGE

~

I

I;:>

'

00

+25
+S
+4S
+65
TEMPERATURE ("0'

~

I0

.

"

~

,OIl I
-35

INPUT OFFSET CURRENT VS TEMPERA TURE

"1000

'"

,

2S

~

= 0.3HI -

IOHI

:;:

10ILO',...-'10L,--I.I;o',...-IOL,·;....-'10"''''--IO~'',.....,;.JIO''

II~o'''''-:o!IO~-:"'o'!:o--~IO':'''--IOJ::'''~-I.JO~''--IOJ,,·
SOURCE RESISTANCE (n)

SOURCE RESISTANCE (n)
CoMMON-MODE REJECTION
VS COMMON MODE INPUT VOLTAGE

kC1fAl.INPUT NOISE VOLTAGE VS FREQUENCY

fH
.

• InCludes contribution from
~I-- source resislancc.

COMMQN-MODE REJECTION VS FREQUENCY

120

..

~~~--~---+--~~--+---~--~

~
~

''''

"

"

~

Rs-IOOMO

g

I
. R.:11i.W-

~

~

;;J

'~" M~--~---+--~r---+----r---i
o

lE

"-

~

·RsJ I~n

~

,~

8 701--If--+--t--+-t--'-t
0
I
10
100
FREQUENCY 1Hz)

Ik

10k

S
10
COMMON-MODE INPUT VOLTAGE (±V)

10

100
Ik
10k
FREQUENCY (Hz)

QUIESCENT SUPPLY CURRENT
VS SUPPLY VOLTAGE

-'
«

~IOO~--~---+--~~--+-~~~~

"'

!-

~ O~~~~~~~~~~__~

0~5--'L,--*10~-L,--f.15C-;....L,--1.20

2S

SUPPLY VOLTAGE (±V,,).

1-140

SO

~

lOOk

1M

ex)

N
LO

CO)

7

+VCC

·IN
+IN
OUTPUT
TRIM
TRIM

4

'Vee

FIGURE I. Simplified Schematic

TO-99 PACKAGE
ABSOLUTE MAXIMUM RATINGS
Supply
Internal Power Dissipation (note I)
Differential Input Voltage (note 2)
Input Voltage Range (note 2)
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 10 seconds)
Output Short - Circuit Duration (note 3)
Junction Temperature

±20VDC
500mW
±40VDC
±20VDC
-6SoC to +ISO°C
-S5°C to +12SoC
300°C
Continuous
T; = +I7SoC

NOTES:
I. Package must be derated based on a junction to ambient
.
thermal resistance of 33SoC/W.
2. For supply voltages less than ±20VDC, the absolute
maximum input voltage is equal to the supply voltage.

BOTTOM VIEW

.48mm
dia.
(.019")

~

Dimensions in inches are in parentheses. Pin material and
plating composition conform to Method 2003
(solderability) of MiI·Std·SS3

FIGURE 2. Mechanical Specifications

CONNECTION DIAGRAM
TOP VIEW

CASE

3. Short circuit may be to ground or either supply. Rating
applies to '+IIS"C case temperature or +7SoC.
ambient temperature.
OUTPUT

Drift changes:
"C for each
100", V of offset
adjusted.

O.3~V

(optional)

FIGURE 3. Pin Connections

1-141

APPLICATION CONSIDERATIONS
The ultra-low bias cutrent and high input impedanCe of
the 3528 are well suit~d ,to a' number of challenging
applications. In order to fully benefit from the
putstanding ~pecifications of this unit careful layout,
shielding and guarding is required. Careless signal wiring
or printed circuit board layout can easily degrade circuit
performance several. orders of magnitude below the
capability of the 3528.
As in any situation where high impe'dapces are inVOlved,
careful shielding is required to reduce "hum" pickUp in
input leads. If large feedback resistors are used, they
should also be shielded along with the external input
circuitry. The metal case of the 3528 is connected to pin 8
and is not connected'to any internal amplifier circuitry.
Thus it is possible to useJhe case as a shield to reduce
noise pick-up.
.
,
Leakage currents across printed circuit boards can easily
exceed the bias current of the 3528. To avoid leakage
problems, it is recommended that a Teflon IC socket be
used or that at least the signal input lead of the 3528 be
wired to a Teflon standoff. If this is not done and instead
the 3528 is tO,be soldere4 directly into a printed circuit
board, utmost care must be used ,in planning the board
layollt. A "guard" pattern should completely surround
the two amplifier input leads and should be connected to
a low impedance' point which is at the signal' input
potential (see. Figure 4). The amplifier case, pin 8, should
also be connected to the guard. This insures:that tM entire
amplifier circuitry is f1JJly surrounded by the guard
potentiaJ.'This minimizes the voltage placed across any
leakage paths and thus reduces 'leakagecurrents.
Figures 5, 6, and 7 show typical applications using the
guard and case shielding.
.
Cleanliness is also a prime concern in ultra-low bias
c,urrent circuits. It is recommended that after installation
is complete the assembly be washed with a low residue
solvent such as TMCFreop (ollowed by rinsing with
deionized water. The 'use of someform of high dielectric
conformal .coating such as a good .two part urathane
should be considll1'ed if the assembly ",ill be used in air
environment which could deposit contaminants on the
low current circuitry.

.

+v~

OUTPUT

<0

30 pF

Shield"

1000Mn

6

Vout = Is x 1000Mn

FIGURf 5.Ultra Low Current to Voltage Converter.

Guard

>~6--0Vout
Case

FIGURE 6. Ultra High Input Impedallce Noninverting Circuit.

.
8

c::::;)~'~

.v"04~~?
~

'" '"

20

l
0

"

2

.1 1 I 1

6

...J

.,

90

0

85

80

8

"

I:.

0.

2

,-",101'"

95

o

8
12
16
Supply Vo~age (±V)

o

20

I

I
10

.,

20

c:
a:

16

VCM = 20V, p-p

:
20

o

,'~

"20
1 10 100 lk 10k lOOk 1M 10M
Frequency (Hz)

-"'-

R'L=lkO

['\

~

r\

~

:;;c:

8

E

4

0

V'

10'

~

20

25

o

30

8
12
16
Supply Voltage (±V)

4

20

POWER SUPPLY REJECTION
VS FREQUENCY

,

L

,
,

~

,

~
~

t

~

5
0
0

..L If"

1\
15

0>

>0.

I"-

120 180 200
Time (!'88C)

t--

"

-8>
0-

80

40

~

~12
0 ...

~

~

20

,

II
5

1

...1

i

TA=+2SOC

0>

100

~

I

1

OUTPUT VOLTAGE
VS SUPPLY VOLTAGE

COMMON-MODE RANGE
VS SUPPLY VOLTAGE

..

120

iii 80

o

1M

~

RL= lkO
Cc= l00pF

-10

Output Current (mA)

COMMON-MODE REJECTION
VS FREQUENCY

~

II
Vs=±10V

lL

o

Vs-±5V

4

I:
" ~

1-""
Vs=±15V

~~

0.

10

r---

,Vs-±20V

TA =2So C

108

107

VOLTAGE FOLLOWER
STEP RESPONSE

OUTPUT VOLTAGE
VS OUTPUT CURRENT

~

g

lOS

Source Resistance (0)

lOOk
10k
Frequency (Hz)

0

c: 105
'ii
C!l 100

105

:;
S- -5

I III

lk

VOLTAGE GAIN
VS SUPPLY VOLTAGE
110

0.1

108

V~ I ;5U-\

o

10 100 lk 10k lOOk 1M 10M

115

~
'3

VS=±10~\

> 6
:;
0.
:; 4

I"-

Frequency (Hz)

j

I 1.11\

8

1.;1"

""

2.0
E.:!: 1;0

I
III
RL = lkO

I 11\

.,

-20

5.0

5.:.:

107

Vs =±ISV

:;< 12
0.

~ 10

I'

~ ~

"

0.01 Hz -10Hz

OUTPUT VOLTAGE
VS FREQUENCY

r"

0

iii

lOS

14

40

10

Source Aesist~nce (0)

Vs = ±SV to ±2OV
80

1.

.~

.If
105

120

iii

"

..til

0.1

OPEN-LOOP FREQUENCY
RESPONSE

100

I

./

--

>

./

0.0 1
-50 -25

P-P INPUT NOISE VOLTAGE
VS SOURCE RESISTANCE

100

4

8
12
16
Supply Voltage (±V)

1-145

L

".

100

'"
20

10

100 lk 10k lOOk 1M
Frequency (Hz)

WIRING CONSIDERATIONS

"'" .

SHIELDING AND GUARDING,
The low, bias 'current'and high input impedance of the
3542 are well-suited' to a number of stringent
applications. However;, carele~s~ignlil wirin,g or printed
circuit board 'layout can degrade circuit performance
'several orders of magnitude below the capability of the
"
, , '
3542.

OUTPUT

As in any situation where, lligh Impedances are inv,olved,
careful shielding is requireg to'reduce "hum" pickup in
input leads. If large feedback resistors are used: they
should also be shielded along with the external input
circuitry.
Leakage currents across printed circuit boards can easily.
exceed the bias 'cutrent of the 3542. To avoid leakage
problems, it is recommended that the signal input lead of
the 3542 be wired to a Teflon standoff. If the 3542 is to be;
soldered directly into l!printed circuit board, utmost care
must be used in planning the board layout; A "guard"
pattern should 'completely' surround the two amplifier,
input leads and should be ,connected to a low impedance
point which is at the signal input potential.
The ~mplifier case should be connected to any input
shieldoflluard via pin 8. This'insures thatthe amplifier
itself is fully surrounded by guard potential, minimizing
both leakage and noise pickup. Figure I illustrates the use
of th~ guard for both inverting and noninverting ci'rcuits.
OFFSET VOLTAGE ADJUSTMENT
Although the j'542 has a moderately low initial offset
voltage,(5inY,typ) compatible with its moderate voltage
drift; some applications may reuire external nulling of
this sml!1I offset. Figure 2 shows the recornmended circuit,
for adjustment of the offset voltage..
'

INVERTIII8 CIIl&UIT

OUTPUT
NOIIIIVERTIIG CIRCUIT
V+

OUTPUT

c:g~, ~,.'",
V'O~'b

,

, aUAlIII 1~'
'

lOOe1B

RATED OUTPUT
Voltage. min
Current, min
Open-loop Output Resistance
DYNA~IC RE$PONSE
Bandwidth (odS,'.mall signal)
Full Power Response, min
,Slew Rate. min
Setiling Time (0.01%). ml!X

3550K

N

NOTE
Leads.n true pos.t.on w.thm .010"

f.25rnm) A

±40pA

(d! MMC at seatmg plane.

Pm numbers shown for reference only.

INPUT IMPEDANCE
Differential
Common Mllde

Numbers may not be marked on package

10"01l3pF
10"0 II 3pF

INPUT NOISE
Voltage; O.OIHz -10Hz. p-p
. 10Hz - 10kHz. rms
Currenl. O.OIHz -10Hz. p-p
10Hz -10kHz.• I)1Is

0.2pA
1.5pA

INPUT VOLTAGE RANOE
Common-MOde VOltage
Common-Mode Rejection
Safe Input Voltage. max

±(lV"I,.-S)V
70dB at +5V. -10V
±Supply

POWER SUPPLY
Rated Voltage
Voltage Renge. derated
Current, quieSCef!tC11
tEMPERATURE RANGE
Specification
Operating
Storage

BOTTOM 'VIEW
Qimensions in Inches are in parentheses.

20/lV

Pin materlai and plating composition
conform to ,method 2003 (solderability)
of Mil-Std-863 (except P,8ragraph 3.2)

4tN

tNCRES

.

DIM

±15VDC
±5VDC to ±20VDC
lImA
O·C to +70·C
-55·C to +125·C

MIN

MIN

.335

.!i:70

8.51

9.40

B

.305

.335

7.75

8.51

C

.165'

.185

4.19

4.70

0

.016

.021

0.41

0.53

E

.010

.040

0.25

1.02

F

02S

G

.040
0'0
.20Q·SASIC

H

.028

.034

0.7'1

.029

.04S

0.74

1.14

'27
2.79

406'

M

160
110
45 0 BASIC

NOTES:
1. The use of a finned Ileat sink is recommended.

N

.09~

1.02

5.08 BASIC

.500

L

~S·Cto+I50·C

MAX

A

JK

\-55.C to +125·C
-55·C to +12S·C

MILLIMETERS

MAX

0.86

45° BASIC

,OS

2.41

2.67

. CONNECTION DIAGRAM

TOP VIEW
OFFSET
TRIM

r-I
I

I
I
I

3

I

5 OFFSET

v-

4

.

I

Lo;;.;_~-J
OFFSET ADJUST

1-148

TO V+

TYPICAL PERFORMANCE CURVES
T. = +2SoC ±Vcc = 15VDC unless otherwise Indicated.
SETTLING TIME VS
CLOSED LOOP GAIN

SETTLING TIME VS
CAPACITIVE LOAD

- - =Cc=O.02XC,
O. \~O:---:I-=OO:---I-:000':'::---:I":'O."':'OOO~

O.11':---1:'::O:----:-100:::----:-1000==-'

Capacitive Load (pF)

"'.

i

0

COMMON MODE REJECTION
VS FREQUENCY

m

- - Output
---Input
I
I

+10 A

i/

..,.,•
0

t;

VCM - +5V. -10V

50

\

II:

'"~0

40

1\

c

1\

0

E
E

'"
o 100

20

0

tl

300
500
Time (nsec)

~

o

700

10 100

OUTPUT VOLTAGE
VS FREQUENCY
20

I
V,-rI5VDC

100
10

0.1

l.&

0.01

:;-

~~

:!j,

.,

vee=kv~c. ~ ~

V~=~20vbc
I I I

'5

10

'":I

5

II.

I

I

I

I

10 100 lk

m

"-

~

c

'iii

.,
!I
'"

80

~

40
20

o IL

L
'I

10 100

I

180

I

1I!O
140
120
100

80

"-

50

"lk 10k lOOk 'IM 10M
Frequency (Hz)

I

101-l--::;.....P

i

\

\
,~

I

8~2-4~~6~8-:1~0~12~1~4~16~18~2O~22·

10k lOOk 1M 10M

Supply Voltage (±V)

OPEN LOOP GAIN
VS SUPPLY VOLTAGE

1

"-

Cl

lll-t-t-+---"

Frequency (Hz)

200

"-

80

I

I

OPEN LooP'RESPONSE
100

R,-lkO

Vcc-±5VDC

o

+50
+100
Temperature (OC)

40
20

0

120

..,

.
:;,...
~

.!
'6
.!

il

!!!.

m
c

II

i'"

MAXIMUM
POWER DISSIPATION

800

T.=-55i~

~

100

~

'iii
Cl

20

QUIESCENT CURRENT
VS SUPPLY VOLTAGE

Vee = ±10VDC

%
0

o

10
15
5
Supply Voltage (±V)

V",,=±15VDC

0

>

..I. ~ /
~~ .......Vcc=±5VDC

/

15

I

~~

\

o

lk 10k lOOk 1M 10M
Frequency (Hz)

NORMALIZED INPUT BIAS
CURRENT VS TEMPERATURE
1000

COMMON MODE REJECTION
VS SUPPLY VOLTAGE
80r:;:-~r.::::-r-::::::~=t

c

\

-10

80

~

1\ ~,Jlkd

U

Settling Time (nsec)

Closed Loop Gain (VN)

LARGE SIGNAL VOLTAGE
FOLLOWER PULSE RESPONSE

~
.,

SETTLING TIME VS
OUTPUT VOLTAGE CHANGE

80 r- j
80

~kr<;:;=

S.
c

+12SoC

T.=+2SoC

I

~a.
j

0

i

~

700

800
500
400
300
200

100
40 2 4 6

8 1012141618.20 22
Supply Voltage (±V)

1-149

o

1\
1\
1\

1\
25 50 75 100 125 150 175 200
Ambient Temperature (0 C)

APPLICATIONS
S,ETTLING TIME

Settling time of an amplifier is, defined (see Figilrel) as
the tot~ tirmi required, lifter an input step signai, for the'
output to "settle" within !I specified error band around
the final value. This error band is expt!:ssedas a
percentage of the magnitude of the step trlmsit~on. A
recommended test circuit, for settling time'is shown in
Figure2. The output error signal appears, attenuated:!)y
II' factor of two,at point A and, may be observed at. thi,s
point with, the aid of an oscilloscope. The diodes act as
limiters to prevent overloading the oscilloscope during
,the' fast leading edge of the input signal.' All resistors
, shoUld be 2kO or less 'to eliminate degradation of
performance due 'to stray capac.itance. A typical measurement desired is. the settling time to 0.01% for a
lO-volt step input. This is the time required fot the Slgnal
at point A to decrease to 0.5m V or less and remain below
this level.
INPUT

\

OUT/PUT

ERROR B,AND

-A

__ L __

1/- '1----,-1

,TI/IIE

o
SETTLING TIME

FIGURE 1. Concept of Settling Time.
Settling time for noninverting circuits can also be
measured but requires the use of ultra-fast differential
amplifier test fixtures. For the 3550 settling time is equal
for inverting or noninverting circuits of equal gain.
TO OSCILLOSCOPE

, theo,utputvQltagl!" wayefdrm Witpoutsignificantly
affecting thesIew f.iie. See theSettllng Time versus Load
capaeitance curves f~r typcial impro~~ments in settling
time.'

FIGURE 3. Compensation for Lo84i Capacitance.
W.IRING RECOMMENDATIONS

In order to fully realize the high frequency performance
capaoilities of the 3550, proper atte~tion must be given
, to layout, component selection and grounding. ,All leads
associated with the input and feedback elements should
be as short as possible and all connections should be
made as close to the amplifier termin~s as possible.
Input and feedback resistors should be made as small as
possible consistent with other circuit constraints.
Capacitance from the ouput to noninverting, input can
cause high frequency oscillations, particularly in high
gain circuits operating from large source impedance.
, Careful layout of wiring or,PC board patterns is the only
satisfactory way of preventing such problems.
In order t9 prevent high frequency oscillations due to
lead inductance the power supply leads should be
bypassed. This should be done by connecting a 1OI'F
tarttalum capacitor in parallel with a O.OOlI'F ceramic
capacitor from pins 7 and 4 to the power supply
common.
INPUT AND OUTPUT VO~TAGE RAMGE

Although the 3550 is specified for best operation on
power supply voltage of ±15VDC, it will operate with
minor performance changes over a power supply voltage
, range of ±5VDC to ±20VDC. Many of the curves show
performance of the 3550 when operated from supplies
other than ±15VDC.

FIGURE 2. Settling Time Test Circuit.
Because settling time is affected by bandwidth which in'
turn is dependent upon closed-loop gain,the settling
time of any operational amplifier will be a' function of
closed loop gain. Settling Time' versus Gain curves
illustrate this effect for the 3550 at several levels of
:settling accu~acy.
The 3550 is remarkably tolerant of load capacitance
because of its stable, 6dBfoctave gain rolloff and low
output impedance. Settling Time versus Load Capacitance curves show this characteristic for the, unity~gain
configuration. For larger values of load capacitance, the
compensation technique of Figure 3 may ,be used to
optimi~e the response. The slight negative feedback
provided by Cc tends to reduce any rin~ng at the top of

1-150

BURR-BROWN®

3551 SERIES

IElElI

Wideband and Fast-Settling FET
OPERATIONAL AMPLIFIERS
FEATURES
Ollset

• REDUCES WIDEBAND ERRORS
50MHz Gain-bandwidth product IACL ;;'10)
250V/ps slew rate ICI = 0)

+Vcc

freq.
Compo
8

• VERSATILE
Single compensation capacitor allows
optimum response
True differential input
• PRESERVES DC ACCURACY
Bias current. 1DOpA, max
Laser-trimmed affut voltage

·Vee

DESCRIPTION
The 3551 is designed to off.er the user versatility in
wideband steady state and fast transient
applications. The use of a single external
compensation capacitor allows the user to optimize
frequency response for maximum bandwidth for a
variety of closed loop gains and capacitive loads.
The amplifier is stable at closed loop gains of greater
than IOV I V, with no external compensation and
may be stabilized at all gains with the single IOpF
. compensation capacitor.
In addition to the excellent dynamic response
characteristics, the 3551 also' has good DC
properties. The use of a monolithicFET input stage
gives the 3551 very low input bias and offset currents.

This is in contrast to the high input currents usually
associated with fast amplifiers having bipolar input
stages. Also, the input offset voltage and offset
voltage drift are low as a result of Burr-Brown 's lasertrimming techniques.
Unlike many wideband and fast settling amplifiers,
the 3551 has a true differential input. This means it
can provide its excellent wideband response in the
inverting, noninverting, current-to-voltage and,
difference configurations.
The 3551 is an excellent choice for applications such
as fast DI A and AI D converters, high speed
comparators and fast sampling circuits, to name just
a few.

International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. (6021746:1111 . Twx: 910-952·1111 . Cable: BBRCORp· Telex: 66.fi4111

1-151

"

SPECI,FICATIONS

,
MECH~'CAL TO~99

"

~,,:

~LECTRICAL

F=1

,

"

,"

Specifications typical at 25°C and ±15VDC Power Supply unless otherwise note<;f,

I

MODELS

3SS1J

I

OPEN LOOP GAfN, DC'

,

3ss1S

1-

c,'

Lrl!I~1

100dB
88dB

No Load
1kll, Load min

RATED OUTPUT
Voltage, min
Cl:Irrent, min
Open Loop Output R4sistance

±10V
±10r(IA
10011 at 1MHz

"

-

,I'"
SOMHz
S,OMHz

25dVl~seC

INPUT OFFSET VOLTAGE
Initial Offset, 2SoC, max

,.,

,>,

"

±lmV'

;•

I

F.J

1

So"n.11111
Plane --1.--0

~i'

DYNAMIC RESPONSE
Gain-Bandwidth Product
Gein = 1000
Gain = 10
Slew Rate IC, = 01

,

II

'

,>

r-

N'

~

"1JT~:;}

'.'~1\\

"

~~~J

"

t

N

t

::t50~V/oC

vs. Temp(1)

±SOO~VN

vs,' Supply Voltage

±1oo~V/mo

vs. Time

NOTE:
Lillads in true position within .010"
(.25mm) R Q!)MMC ,at se~ting plane:

INPUT BIAS CURRENT
Initial Bias, 25'OC, max
vs. Temperature
VS, Supply Voltage

-4OOpA I after full warm-up I
doubles every 100C
±1pAlV

Pin numbers shown for f.hmince·o~lv
Numbers--may not be mark.~ on PJlckage

INPUT DIFFERENCE CURRENT
Initial Difference, 25°C

MIN

01'"

"•
c

'8.51

9.40

,305

.335

" 7.75

8.51

.165

.18S

4.19

4.70

0

.016

.021

0.41

0.53

E

.010

,040

20"V

f

.010

,040

0.25
0.25

1.02
1.02

4~V

a

.200 BASIC

O,2pA
l.SpA

J

POWER SUPPLY
Rated Voltage
Voltage Range, derated
Current, qUiescent(1)

.034
.045

0.71

0.86

0.74

'.14

--,

12.7

--

L

,"0

,160

2.79

4,06

M

45° BASIC

N

.095

K

±IIVcc I-SIV
70dB at +SV, ~10V
±Supply
±15VDC
±SIiDC to ±20VDC
11mA

5.08 BASIC

':028
.029
,500

H

INPUT VOL TACOE RANGE
Common-mode Voltage
Common-mode Rejection
Max, Sale Input Voltage

' MlllIMEl~RS
MIN
MAX

,370

I

Voltage, Om,Hz to 10Hz, pop
Voltage: 10Hz to 10kHz, rms
Current, 0,01Hz to 10Hz, p-p
Current, 10Hz to 10kHz: rms

MAX

.335

101111,11 3pF
101111 II 3pF

Differential
Corrimon-mode
INPUT NOISE

INCHES

±40pA

INPUT IMPEDANCE

45° BASIC

.105

2.67

~.41

Pin material and plating com'position"
confo,."'; to method 2003. ttolderabil'ity)
of Mil-Std-883 (except paragraph 3.21

TEMPERATURE RANGE
Specification

Operating
Storage

OOC to +700C
I-SSOCto +125°C
-SS"C to +12SoC
,-ssoC to +125°C
-65°C to +1S00C,
'

CONNECTION DIAGRAM

.--.,j~':"-:"',
I:f

NOTE:
1. The use of a finned heat sink is,recommended.

I Optional

4 -VCCI

IOffset Adjust

'- -

-

-

-'\N'v- - ..J

20kL-to +VCC
The case is electrically isolated.

1;..152

TYPICAL PERFORMANCE CURVES
TA = '25°C
OPEN LOOP RESPONSE
100

I I
-'I \o..'\. I'- Cf = 0 pF I
I
"'~ \\,.. rCf I-10pF
'I

~

80

iii'
~

60

c

.

I\..~

.~

Cl

'0

>

~
I\..~

"
"'"

40

D>

~

Cf = 20 pF

20

o
10100

Vs = ±15 VDC unless otherwise indicated.
RECOMMENOEO VALUES OF FREQUENCY
SLEW RATE vs.
COMPENSATION CAPACITANCE
COMPENSATION CAPACITANCE
vs. CLOSED LOOP GAIN
260

~

~
I\..~
'1~

~

00

= 10 pF

:g,

~

~-----,WIIP '-~I-----,H

1

-r II

"
,/

~Cf

>
-10

V.

I

= :t20 vec

100

~

U

V.

~

.S!

= :tIS vec

10

'c."
~

.1

'C

~

l.& ~ r

~

.01

Z

.001

is

~~

.. ...

100

+50

iii

.

.

60

\

.

+100

40

o

c

~ 91-1-~1-1-1-+-+-+-+-I

.~

8~~~~-L~~~~

10100 lk

2 4

10k lOOk 1M 10M

~

..

Cl

TA = -55°C

l!

60

40
20

--

L-

'0

>

B 10 ;2 141618 20 22

MAXIMUM
POWER DISSIPATION
800

100

80

6

Supply Voltage (:!:.V)

OPEN LOOP GAIN
vs.SUPPLY VOLTAGE
iii

15
5
10
Supply Voltage (:tV)

10

~

120

·c
'ii

0

;;

U

o

TA = -55°C

~
c
° 20
E
E
u°

f

\

COMMON-MODE REJECTION
vs. SUPPLY VOLTAGE

°

11

c

Frequency (Hz)

40

t...

10k lOOk 1 M 10M

~

~

a:

'C

10100 lk



Jio..

Gain (VIV)

-Output

i=

expected values-

~

lk 10k lOOk 1M 10M

1or-----~----

/

40
20

100~----t-----+-----

!

'" , Ra~geOf-~
'"" "
"'" ..... I'iiiO:
~~

!

SETTLING TIME vs.
CLOSED LOOP GAIN
Cf

\

5: 200 \
~ 180
.1. ,
~ 160
140
a: 120
~ 100

Frequency (Hz)

u

\

240

'U 220

j:::" 10'" ....

I~

II

~ I-'" k

L-.-.

TA = +125 0 C

TA:= +2SoC

~

.5
c

°

~

700
600
500

0.

400

is

300

"iii

l;

200
° 100
"~

2 4

6

8 1012141618 2022

Supply Voltage (:tV)

o

r-...

.,

1\

25 50 75 100125150175200
Ambient Temperature (oC)

APPLICATI.ONS

'-f,r\

",

~":

,;,~

•

•

'.

,.~:

•

A

WIRING RECOMMENDATIONS
In order to fully realize the high frequency performance
capabilities ofthe 3551i-proper attention must be given to
layout: component' selection 'and gtounding, All leads associatedwith the input and "(eedback elements should be as shortas possible'and a1I'connectiOlts should be made as close to the
amplifier terminals as possible, Input and feedback resistors
.should be made as small' as possible consistent with other
circuit constraints.. Capacitance.fiom the output 'to non- ,
inverting input can cause high frequency oscillations, particulilfly in high gaih circuits operating from large source impedances. CarefuLlayout of wiring or PC board patterns is
the only satisf~ctory way of preventing such problems.

~readboarding

may indicate that none is needed.

In order to prevent high frequellcy oscillations .due to lead
inductance the power supply lead.s shpuld be bypassed. This
should be done by connecting a. lO Mf tantahu;n capacitor
in parallel with a 0:00 IMf ceramic .capacitor from pins 7 and
•
4 the power supply· common.

-to

INPUt AND OUTPUT VO.L TAGE RANGE
. Although the 355 I is specified for best operation on power
supply voltage of ±IS VDC, it will operate with minor per·
formance changes over' a power supply voltage range of
+5 VDC to +20 VDC. Many of the performance curves show
performanc; of the 355 I when operated from supplies other
than ±15 VOC.

INPUT/OUTPUT PROTECTION
All of the amplifiers listed in the speCification table are de·
Signed to withstand input voltages as high as the supply
voltage, without damage to the amplifier. Thus, inputs may
be subjected to either supply voltage, in any combination,
without damage.

Load

Output stages are internally current limited and will with·
stand short·circuit·to-ground conditions. However, applica- ,
tion of nonzero potential to the outpU1 pin may cause permanent damage and should be prevented' by. t,he proper pre·
cautions.

(8) Inverting Circuits"

SETTLING TIME
Settling time of an amplifier is defined as the total time reo
quired, after an input step signal, for the output to "settle"
within a specified error band around the final value. This
error band is expressed as a percentage of the magnitude of
th~ step transition.

Load

Because settling time is affected by bandwid th which in. turn
is dependent upon closed loop gain, .the settling time qf any
operational amplifier will be a function of closed loop gain.
Settling time vs. gain curves illustrate .this effect for the
355 I at several levels of settling accuracy.

(b) Non-Inver,t~r:ag Circuits

FIGURE '1. 'Proper Grounding Methods.
Provision for phase compensation should always be
made on the PC board even if initial calculations and

1-154

3553

BURR - BROWN ®

IElElI

Wideband - Fast-Slewing
BUFFER AMPLIFIER
FEATURES
• GAIN = .99V/V
• OUTPUT CURRENT. ±200mA
• BANDWIDTH. 3DOMHz
• SLEW RATE. 2000V/lisec
• ElECTRICALLY ISOLATED CASE
• EXTENDS OP AMP DRIVING CAPABILITY WHILE
PRESERVING BANDWIDTH & SETTLING TIME

DESCRIPTION
The 3553 is a unity-gain amplitier designed to be used
either as a signal buffer, or as'the power output stage
for an operational amplifier. Because of its wideband
response (300M Hz, -3dB bandwidth) and fast
slewing capability (2000V I fo.Isec) the 3553 is capable
of following very fast signals. When used inside the
feedback loop of an operational amplifier, theSe high
speed characteristics are essential in order to preserve
the performance and stability of the feedback
amplifier circuit.
With its ±200mA of output current capability, the
3553 is capable of driving a signal of±10V into a 50n
load. This power capability, coupled with its
extremely high speed and wide bandwidth, makes the
3553 ideally suited for line driving applications where
fast pulses or wide band signals are involved.
In addition to its fast I wideband characteristics and
high output current, the 3553 has low input offset
voltage and drift. This, adds to its versatility,
particularly in stand-alone buffer amplifier
applications.
The 3553 is packaged in a reliable hermetically sealed
TO-3 package for environmental ruggedness. The
metal case' is completely electrically isolated. This
simplifies mounting and reduces,cost since the need
for insulating spacers and bushings is eliminated.
International Airporllndustrial Park· P.O. Box 11400· Tucson. Arizona B5734· Tel. (6021746·1111· Twx: YI0-952·1I11· Cable: BBRCORp· Telex: 66-6491

1-155

SPECIFICATIONS
Spe.Cifications ~re typical at +2S o C Case Temperature ~nd ± 1'5 VDC power supply
unless otherwllil> 'noted
,',

,,',

ELECTRICAL

:M,fE.CHANicAL

....

M PA1:KA!lE,(TO-~

,

MODEL

3553AM

,

GAIN, DC
No Load
so n Load, min

4

RATED OUTPUT
'IOV
£200 mA
In

Output Resistance

39'62mm~
max
.
1
ma~ __-+_'-_......
'_

2.54
mm
......
(C).100")
(1.56 )

0.9R V/V
0.92 V/V

Voltage, min
Currerit. min

10.16mm
(0.400")

I

,

,

I

t ..

c

J

n
n nH
UU U U

1 ..

,0.~,6mm--,-t

(0.4") min

DYNAMIC RESPONSE,
Slew Rate, min
Full Power Bandwidth, min
Sm.all Sigqal -3d8 Bandwidth
Settling Time
to 1%
to .01% ,','

2000 V//lsec
, .J2MHz
300 MH~
7.2 nsec
14.S,,,$Oc "

(BOTTOM
VIEW)

12.7mm (.500")dia

INPUT PARAMETERS
Input Voltage, linear range
Input Voltage, absolute"max

Input Impedance
Input Bias Current
(doubles/+ 10°C)

@

+2 SoC

±lOV
±Supply Voltage
lOll n
,200 pA

80°

)

OUTPUT OFFSET Y,OLTAGE
Initial Offset @ +2SoC. max
vs. Temperature (average) -25°C to +8S o C

±SO mV

3.96 to.l 3mm
(0,156 ±0,005")dia

±300 j,lv/oC

'(

POWER SUPPL Y
Rated Voltage
Voltage Range, derated
Current, Quiescent, max
typ

±IS VDC
'.5 VDC to ±21) VDC
"80~A
'
.50 mA

TEMPERATURE RANGE (Case)
Spec,ification
Operation (derate above +120 o C Case) ....
Storage
Ole Thermal Resistance, junction to case

8 JA Thermal ReSistance, junction to ambient

..,2S o C to +8S o C
-5 SoC to + l2SoC
-65°C to + 150°C
6 0 C/W

Pin material and plating composition
conform to Method 2003 (solderability)
of MiI·Std·883 [exC8Dt paragraph 3.2]

33 oC/W'

CONNECTION DIAGRAM
(TOP VIEW)

+Vee
N.C.

*

Input

Output

-VCC
*NO internal connection

-Vee
SIMPLIFIED SCHEMATIC

1-156

CONNECTOR:' OB03MC
HEATSINKS: OB03HS 12 0 C/W
OB04HS 4.2 0 C/W
OBOSHS 3 0 C/W

case is
electrically
isolated

TYPICAL PERFORMANCE CURVES
Typical at 25 0 c and rated supply voltage unless otherwise noted.
SMALL SIGNAL
FREQUENCY RESPONSE
0

2

:;

:>

1.5

€

RLI=5~nl

c

~

:cen

G

il
.c

'\

co

!i

'0

>

.5

10

1k

100k

10M

"-

i"

-50

\

10M

/

5

o

o

lOOk

/

10

>
S
c.
S

-150

1k

1G

o

2

:§

RL

:;

75

:>

1.5 e-

= ~O n

V 1N
f '"

I
I

6

T c::: -5SoC to +125 0 C

4

50

t

25

'0

.5

2

I
I

9 JC

(Casel

I

o

5

10

15

ee )

Supply Voltage (:t. V eel

= 6 o C/W_

~

'>fJ-

o
o

20

I

I
I
r- ~~
'?6~&
r- --;

>

0~~--1~0----1~5--~~

20

15

POWER OISSIPATION
8

= ± Ivs[-5V

2~HZ

10

Supply Voltage (tV

GAIN vs
SUPPLY VOLTAGE

100

Supply Voltage (±. veel

5

Frequency (Hz)

QUIESCENT POWER SUPPLY
CURRENT vs SUPPLY VOLTAGE

/

RLJ50n.
15

t
'0

-200
10

10

20

-100

Frequency (Hz)

;(

OUTPUT VOLTAGE RANGE
vs SUPPLY VOLTAGE

PHASE SHIFT

vs FREQUENCY

i

50

j~
I

- c----

i

I

100

150

200

Temperature (DC)

APPLICATION INFORMATION
BOOSTER AMPLIFIER
One of the primary applications for the 3553 is that of a
current booster for an operational amplifier. The circuit
of Figure I is typical of such applications. Note that the
3553 is used inside the feedback loop and becomes, effectively, the output stage of the composite amplifier. Because the 3553 has unity voltage gain, wideband response,
fast slewing rate, and very little phase delay, the dynamic
response of the operational amplifier is virtually unaffected
by the addition of the booster.

Capacitive loads, often a source ofinstability and oscillations
in operational amplifier circuits, are buffered .by 'the presence of the 3553. In driving heavily capacitive loads the
slew rate of the 3553 will be seen to decrease. This is due
simply to the large currenis required by fast voltage slewing
in a capacitive load,
dV
Ic =Cload dt .
The internal current limit of the 3553 (approximately
600 rnA) places a limit on the slewing rate under such
conditions.

The already low offset voltage of the 3553 is effectively
reduced by a factor equal to the open loop gain of the
operational amplifier and becomes a negligible factor in
total offset error of the circuit.
'
Input impedance of the 3553 is extremely high, thus requiring almost no drive current from the operational amplifier.
On .the other hand, the presence of the 3553 in the circuit
increases the output current capability to ±200 rnA, drastically lowers the output impedance of the loop, and permits
the driving oflow impedance loads such as a terminated son
coaxial line.

..
Composite Amplifier

FIGURE 1. Model 3553 as a power booster.

1-157

BUFFER AMPLIFIER
The 3553 may also be uSed, as shown in Figure 2, as a
unity gain buffer amplifier. No operational amplif\eris
required in this mode of operation. Since the 3553 is then
operated without feedback, it's offset voltage and drift
ate translated to the output. While the gain is not
precisely unity in this mode, the accuracy is adequate for '
many applications.
INPUT/OUT-PUT PROTECTION
The outp).!t stage ,of the 3553 is c,urrent limited at
approximately 6OOmA. This will provide a measure of
output short circuit protection for the amplifier for a
period of time as determined by the heatsinking used, the
amplifier's thermal resistance, the ambient temperature,
etc. Tbe amplifier's output stage transistors should not be
allowed ,to exceed 150°C (175°C absolute max).
The input stage is designed to allow the application of
either supply voltage without damage to the amplifier.

POWER DISSIPATIQN
The power dissipation capability of the 3553 varies with,
ambient temperature and with.the ,type of heat sink used.
A heat sink may be, used to increase tlte dissipation
capability or to aChiev.e a given dissipation capability at
higher temperature. The power deratinj! curve is given in '
the Typical Performance Curves.
.'
WIRING RECOMMENDATIONS
; No special wiring techn'iques are necessary with the 3553.
However, ,it is recommended, as a good engineering
practice, that the power supply lines be bypassed to
',common at' a point ,near the amplifier. (A l.OIlF,
electrolytic in parallel with a IOOOpF ceramic is
recommended.) If the 3553 is used with a wideband
operational amplifier; all leads must be kept as short as
, possible to minimize stray capacitance and unwanted
feedback paths.
'

,FIGURE 2. Model 3553 as a Unity Gain Buffer.

1-158

3554

BURR - BROWN ®

113E11

Wideband - Fast-Settling
OPERATIONAL AMPLIFIER

FEATURES

DESCRIPTION

• SLEW RATE, 1000Vjlsec

The 3554 is a full differential input, wide band operational
amplifier. It is designed specifically for the amplification
or conditioning of wide band data signals and fast pulses.
It featuresan unbeatable combination of gain-bandwidth
product, settling time and slew rate. It uses hybrid
construction. On the beryllia substrate are matched input
FETs, thin-film resistors and high speed silicon dice.
Active laser trimming and eomplete testing. provide
superior performance at a very moderate price.
The 3554 has a slew rate of IOOOV I J..Lsec and will output
±IOV and ±IOOmA. When used as a fast settling
amplifier, the 3554 will settle to ±O.05% of the final value
within 150nsec. A single external compensation capacitor
allows the user to optimize the bandwidth, slew rate or
settling time in the particular application.
The 3554 is reliable and rugged and addresses almost any
application when speed and bandwidth are serious
considerations. It is particularly a good choice for use in
fast settling circuits, fast 01 A converters, multiplexer
buffers. comparators. waveform generators. integrators.
and fast current amplifiers. It is available in several grades
to allow selection of just the performance required.

• FAST SETTLING, 150nsec, max (to ±.05%)
• GAIN-BANDWIDTH PRODUCT, 1.7GHz
• FULL DIFFERENTIAL INPUT

APPLICATIONS
• PULSE AMPLIFIERS
• TEST EQUIPMENT
• WAVEFORM GENERATORS
• FAST DIA CONVERTERS

International Alrporllndustrlal Park· P.O. Box 11400· Tucson. Arizona 85734 . Tel.I602/741i·llll . Twx: 910.952·1111 • Cable: BBRCORP . Telex: 66-6491

1-159

TYPICAL CIRCUITS
5.6kl1

5.6kll
"

\

"." .

2 pF

,

X 1 Inverters

XI Non-Inverter

Error

Signal
56011

S.6kl1
HP 5082-2811
Hot Carrier Diodes

1.2pF*
ei=±lOV'

IpF to 'lSpF

tr =tf = (~)sec

....~-o

~

2711

11000PF
"0:'

+Vcc-V cc
Settling Tillie Test Circuit Schematic

XI0 Inverter

View from Component Side.
Shaded area is the pattern side conductor.

lOon

10kil

X I 00 Inverter

Settling Time Test Circuit Layout
NOTES:
1. These circuits are opti";ized for driving large capacitive loads (to 470pF).

2. The 3554 is stable at gains of greater than 55 (CL .;; 100pF) without any frequency compensation.
3. 45nsec i. optimum. Very fast rise times (1a-20nsec) may saturate the input stage cauaing less than
optimum settling time performance.
'Indicates component that may be eliminated when large capacitive load. are not being driven by the device.

1-160

Amplifier
Output

ELECTRICAL SPECIFICATIONS
At TeAsE

= 2S"C and

±15VOC. unless otherwise noted.
3554AM

PARAMETERS

3554SM

3554BM

CONDITIONS

UNITS
MIN TYP MAX MIN TYP MAX

· · · · · ·
· · · · · ·

OPEN LOOP GAIN,DC
R,. = loon

100
90

lu =±IOOmA
Vo = ±IOV

±IO
;'100

No Load

Rated Load

106
96

RATED OUTPUT
Vollage
Current

Output Resistance. open loop

f= 10MHz

±II

±125
20

Full Power Bandwidth
Slew Rate
10±1%
Settling Time
lo±.I%
10 ±.05%
10±.01%

CF =0
70t
CF = 0, G = 10 V/V
150
C, = 0, G = 100 V/V
425
CF=O,G= 1000V/V
1000
CF=O, V, = 2OVp-p, R, = loon 16
CF=O,V, = 20Vp-p, RL= loon 1000
A=-I
A =-1
A=-I
A=-I

dB
dB
V
mA

n

· · · · · ·

DYNAMIC RESPONSE
Bandwidlh (OdB, small signal)
Gain·bandwidth Product

MIN TYP MAX

90
225
725
1700
19
1200
60
120
140
200

150
250

±o.5
±20

±2
±5O

MHz
MHz
MHz
MHz
MHz

V/l"oc
nsee
osee

nse<;
osee

INPUT OFFsET VqLTAGE

Initial offset. TA = 2S"C
'IS. Temp (T A = _25°C to +SS"C)
Vli. Temp (T. = -55"C to +l25'C)
vs. Supply Voltage

INPUT BIAS CURRENT
Initial bias. 25°C
VI. Temp
vs. Supply Voltage

0

±80

±300

..

-50

-10
±I

INPUT DIFFERENCE CURRENT
Initial difference. 25"C

±2

±IO

INPUT IMPEDANCE
Differential

10" II 2
10" II 2

Common-mode

INPUT NOISE
fa = 1Hz'
f,=IOHz
f, = 100 Hz
f,·= I kHz
f, = 10 kHz
f, = 100 kHz
1.= I MHz
f. = .3 Hz 10 10 Hz
f. = 10 Hz to I MHz
Current. fR = .3 Hz to 10 Hz
f. = 10Hzto I MHz
Voltage.

R,
R,
R,
Rs
Rs
R,
R,
R,
R,
R,
R,

=
=
=
=
=
=
=
=
=
=
=

loon
loon
loon
loon
loon
loon
loon
loon
loon
lOon
loon

125

50
25
15
10
8
7
2

8

450t
160t
90t
50t
35 t
25t
25t

Common-mode Rejection
Max. Safe Input Voltage

±o.2

±I

.±12

±25

· ·
· ·
· · · · · ·
· · · · · ·

·
·
· · · · · ·
f

1t

2

Linear Operation
f = DC, V,·. = +7V, -IOV

44

· · · · · ·

±(lVee",)
78

+Supply
±15
±5
±17

±35

-25

+85
+125
+150

-55
-65
f

±18
±45

· · · · · ·
-25
-55
-65

1,5
45

• Specifications same as for 3SS4AM
•• Doubles every +IO"C
t This parameter is untested and is not guaranteed. This specification is ,established to a 90% confidence level.

1-161

+85
+125
+150
IS
45

mV
~V!,C

25

POWER SUPPI Y
Rated Voltage
Voltage Range. derated performance
Current. quiescent
TEMPERATURE. RANGE (ambient).
Specification
Operating. derated performance
Storage
8 junction.o(:ase
8 junction-ambient

±I
±15

45

INPUT VOLTAGE RANGE
Common.mode Voltage Range

±o.2
±8

-55
-55

+125
+125
+150

-65
IS
45

~V!,C
~V/V

pA
pA/V

pA
nil pF
nil pF
nV/$.
. nV/$.
nV/VHz
nV/VHz
nV/VHz
nV/VHz
nV/.JifZ
"v, p-p
IJ.V.rms
fA, p-p
pA.rms
V
dB
V
VDC
VDC
mA
'C
'C
'C

'C/W
'C/W

TYPICAL
..,

CURVES

at TC :::: +2SoC an,d ± 1 SVDC unle~s otherwise no~~d.
OPEN LOOP RESPONSE

OPEN LOOP RESPONSE

..

VOLTAGE GAIN
Kl)o 10ilu

~

;',,*.257;)'

,

-

\l1···~1B '

~.

~ISVDc

,:

~" ~12vnr

-

i'

II

~~.
50

100

100

-

1$0

OUTPUT CURRENT'(mA)

oum.rr VOLTAGE

OPEN LOOP OUTPUT RESISTANCE VS FRE~
RL -1000
C'f'"OpF

~so

::;

~

~

Ie

,;

~'3
~

Vs .. t,ISVOC

,

0

r
~

\

s· ...

VOLTAe.:

10.
lOOk
1M
FREQUENCY (lUI
FOU..oWE~

10M

100M

·w

"

~

~

·

o

:!S

TIME(nllli~1

":~---+----I----1

'10

_~

;;
~

.a ~
~

7

~r

2~~!~r:::t:l
~
1

1

CLOSED LOOP GAIN (V{V)

INIVr BIAS CURRENT

1'....-...,......;;.;,;.;.=,;.;.;.;;;;;,.;......,...,..,..

100

1-

SO

1S

100

125

I~

~!S

0

~

.l~

fa~

Q~

~ I

i/i/
;, •

;

t:FFECT OF THUMAl SHOCK ON

WAKNUPPRI..,.
TA "

!!o

t· ....

I.

~Sll('

WidlllU'
HUllink

;I . . . . . -+-.I~".-+-+--+---I
!

z

a'l,
-1~of--""''''IIIOI:.-I'''''-~211O:::----:300
0

5E1!LlNG TIMli (nlK)

10

§
~ oV ~
'.1

~o

40

50

60

44IO/-,,/f-t--+-+--i--t
" ....

a
o
10
20
30
40·
natE FROM HEAT APPUCAnON (MIN)

INPUT OFFSEr CURRENT

INPUT OfFSET CURRENT

JO

/

I

/

10

so

§11~1---+-+--4-1---i1
~ 1+-+--1--1--+-+---11

1000

..,

1.1

+S

~

."....

TIME FROM PQWIi.R APPLICATION (MIN)

INPUT liAS CURlfNT

I"'"''',.......,......;;.;,;.;.=,;.;.;.;;;;;,~...,..-.,

WithiN'

j!1 HOCif--,-t--b;o+-+-+-I

~~
I 1~
.
\
'i\
....."....
4-~t--\-\\-~---I---I ~

\ ),'

OfFSt,.VOlTAGE
irA -+125UC

~
t--'
Heallink
~ loooj--.....
-+-+-+-+--I--i
!:i
TA·~+2·SUC

/

i

11---4--+-+--+--1--11
.~ II--f~-+-"""""o!---l
~
V
ffi
l/-'-h0'9--t-+-+--i
~
.lII--I,.---t--+-+-+-il
~ I'I--If--t--+-+-+--I ~
~
'/
"'I---t--+--+--+--+---iI
'I--I--+-+-+--I-~ i ~I---+-+--+--+--i

/

-25

-

I).I!<

~

:i

.~~s.

10
15
SUPPLY VOLTAGI: Ct.VI

Tt.MPt-,RATURl:jll(·)

~Ior--+--+-+-+-+'-f '"

/

30

1.,1-__-+_-,-_-\-__-1

IL"'loon

II
,
f 001---+--+--+--+-"'/'--1
V!~ loot---+--+--+--+--+--i
I

to
IS
20. lS
CF. CAPACITANCE (pF)

,. or-__',;;,••;,;W,;;,.r-·NC_y;,;C,;;,"-',;;,RAIT=T··;;;IS;;,TIC;;,S;..-....,

FRl:OUI:N(,Y C'HARACTt.RISTICS
,.O'r-...,.......;,.,..-....,F.;.;,;.=~.....,

--lftPIII

S

~OuIPUI

!i
;

o

1000

"
~ "'+-+-+--\--t-';;::F-i
-r.H'---t---; ~,

§Sioot---t--~
Ar~
A,""-I L
10

10

GAlNIVM

SEnuNCi TIME Vs.QUTPUT VOLT4CE C'HANGE

SEnUNGTINE

!

100M

TIME 1....:1

1.....- - - , . - - - . , . . - - - . . ,

jI

'"

./ ~
I

v

!<

;!OO)OO400SOO600

100

"-

1M

of/

~~

••
,

·i

I....

I'"

r""'\

.,

RL -loon

.~••

.

;;

CF"SpF
Ik

s

i

\

VOLTAGi; FOLLOWER TRANSif.NT RESfONSt

LARGE SIGNAL RfSPONSI:::

.....npul

:I

r-....
100

-OUtput

•

.~

.~

FREQUENCY (Hz)

",.

'1

\

\

I

,\

?VOC

Ik

100

~I

~

5~ .

V "1.12\11)('

-

rcquiJed for I!lI*itiW loadl.

'"

CFJOpF

!

010

",~"",.J,........
t-----t-..:~ibf"'QJII'Ifelilatiun

~

a

~

Vs'"t.llnlDC'

SLfWRATE

:IS

60

+35

+65

TEMPERAlVRf (OC)

+9S

tllS

.oo·IL--:.I!;;O-~.'!--·'*O-~'~'-:;'I~O--'

.00_55

i

-25

+5

+l5

+65

TEMPERAnJRE (OC)

INPIJI' VOLTAGE (V)

1-162

+95

+125

.OO'.....-.I!::II--l.S!---:\II-~.~S-.~I!:-o--'1
INPUT VOLTAGE (V)

RMS INPUT NOISE VOLT AGF'000

'00

i:

V
fa-I

./

~

z-IM

if

. ,.

,

10

I

10

SOURCE RESISTANCE co·
t'ncludn(OIII,ibulioo rrum

..

COMMON-MQDI; REJE('l10N

.

.

JO

~
\

,

f.

.1':.

~~

,.

A

8

e

E

INCHES
MIN
MAX

'1;110

.,

.-....

1,110
.170

.

.,

F

4tPaA8lc

"H

.IOG,ASIC
1.'" BASIC
.IN.AlIC

J
K
Q

"

.....

....
.'11

.

.04'

.aoo
.111

'.020

tI.12

7.12

,

0 •• 7

10.1 •
1.07

2.03

2 .• 7

4fPaASlc
12.7 BASIC
30.12 BASIC
11.OS BASIC
12.70
10.1'

'.84
24.89

I"-

2
91e

l

tSIl(",IW

"I"-

9J A1"4SOCj

"

.

20

'I'"

'I so

TI-:MI'li.R .... TU ... l'. CUt·)

Offset Potentiometer
(Optionili)

K

•

:-I

-vs

MlUIMETERS
MIN
MAX

38.311

,

~

J

,

r'+7 I
.- ..... .......
D
''tl .... _..~'

,....

Cw

I Amb1C"1 ..

>~ ~

5H~
F

FREQUENCY (Hz)

AMPLIFIER CONNECTIONS

--.1
.J

D-L

(Bottom View)

10 100 It 10k loot III

.

~
" ~

e-

1111

,

MAXJMUM POWER DISSIPATION

SUPPLY VOLTAGE U:.V)

rR·

.01 .1

•

MECHANICAL

Q

-

6

,

,.

.I

QUIESCENT SUPPLY CURRENT

2O~

COMNON-MODE INPUI' VOLTAGE (tV)

S_'" P'o.. - '

....'''''

-lnciudauontribulionflOJll_reemidallce.

./

'"

DIM

,.'

JOU'" ,etill.n~•.

••

,.

"

•. ,t:- r--- .....

,

/'

10'1c--4~-+--Ic-~~.~-+-4

,.'

00

6

~

i

10
.'
SOURCE RESIST ANCIi (PJ
tJncllldr",..mbulJonfrDIIISl.lllreere$b:IIII.:e.

,

\.

I

i

, ,
,'"

,

" 100'1--1-,-.,-•.+,H-,-'-101c",-+-+--/"""J'1

.~

/'
10

TOTAL INPlfI" NOISE VOLTAGE-

PIiA,IC.·TO-PUK INPUT SOlSi' VOLT AGP

/

. Pin material and
plating compoR'

tion conform to

Method 2003
(solderabillty) of
Mil·Std·883
[exGept para·
graph 3.21.

1

4;00

2!5 .• '

NOTE:
Leads in true position within .010·
(.25mm) R @ MMC at seeling plane.
Pin numbers shown for ·referenosonlY.
Numbers may not be merked on ptickage.

1-163

There is no internal case connection.

WIRING PRECAUTIONS
The 3554 is a wideband,high frequency operational
amplifier that has it gain-bandwidth product exceeding I
Gigahertz. The fQll performance capability of this
amplifi,er will be realized by observing a few wiring
precautions and high frequency techniques,
or all the wiring precautions, grounding is the most
important and is described in an individual section. The
mechanical circllit' layout also is very important. All
circuit elementleads should be as short as possible. All
printed circuit board' conductors should be' wide to
provide low r~sistance; low inductance connections and
should be as short as possible. In general, the entire
physical circuit should be as smau as practical. Stray
capacitances should, be minimized especially at high
impedance nodes such as the input terminals of the
amplifier. Pin 5, the inverting input, is especially sensitive
and all associated connections must be short. Stray signal,
coupling from the output to the input or to pin 8 should
be minimized. A recommended printed circuit board
layout is shown with the TYPICAL CIRCUITS. It also
may be used for test purposes as described below.
,When .designing high frequency circuits low resistor
· values shoull! be used; resi,stor values leSs than 5.6kfiare
· recommended. This practice will give the best circuit
'. performance as the time constants formed with the circuit
· capacitances will not limit the performance of the
.
amplifier.

'GROUNDING
As with all high frequency circuits a ground plane and
good grounding techniques should be used. The ground
plane should connect all areas of the pattern side of the
printed. Circuit board that are not otherwise u;~. The
ground plane provides a low resistance,' low inductance
common return path for all signal and power returns. The
ground plane also reduces stray signal pick up. An
example of an adequate ground plane .and good high
frequency techniques is the Settling Time Test Circuit
Layout shown with the TYPICAL CIRCUITS.
Each power supply. lead should be bypassed to ground as
near as possible to the amplifier pins. A combination of a
· II'F tantalum capacitor in parallel with a 470pF ceramic
capacitor is it suitable bypass.
In inverting applications it is recommended that pin 6, the
·non-inverting input, be grounded rather than being
connected to a bias current compensating resistor. This
assures a good signal ground at the non-inverting input.
A slight offset error will result; however, because the
'resistor values normally used in high frequency circuits
are small and the bias CUHent is small, the offset error will
be minimal.

If point to point wiring is used or a ground.plane is not,
single point grounding should be used~, The input signal
retUrn and the load signal return and the power supply
common should all be connected at the 'same physical
point. This will eliminate any common current paths or
ground loops which could cause signal modulation or
unwanted feedback.
. It is recommended that the case of the 3554 not be
grounded during use (it may, if desired). A grounded case
will add a slight capacitance to each pin. To an already
functional circuit gro\lnding the case will probably
require slight, compensation readjustment and tile
compensation capacitor values will be slightly different
from those recommended in the typical performance
curves. There is no internal connection to -the case.
Proper grounding is the single most important aspect of
high frequency circuitry.

GUARDING
The input· terminals of t~e .35~4 may be surrounded by a
guard ring to divert leakage currents from the input
terminals. This technique is particularly important in low
bias current and high input impedan!:e applications. The
guar~, a conductive path tliat completely surrounds the
two amplifier inputs, should be. connected to a low
impedance point which is at the input signal potential. It
blocks unwanted printed circuit board leakage currents
from reaching the input terminals. The guard also win
reduce stray signal couplin~ to' the inp'ut.
In high frequency applications guarding may not be
desirable as it increases the input capacitance and can
degrade performance. The effects of input capacitance,
however, can be compensated by a small capacitor placed
across the feedback resistor. This is described further in
the COMPENSATION section.

COMPENSATION
the 3554 uses external frequ~ncycompenSat!on so that
the user may optimize the bandwidth'or slew 'rate or
settling time for.bis plirticullir application. Several typical
performance curves are provided to aid in the selection of
, the correct compensation capacitance value. In additibn
several typical circuits showr~commended compensation
in different applicatio,ns.
The primary compensation capacitor, CF, is· connected
between pins I and 3. As the periormancecurves show,
larger closed loop gain configurations require less
capacitance and an improve4 gain-bandwidth product
will be realized. Note that no c6mpensationcapacitor is
required for closed loop gains above 55 Y}V and When the
load capacitance IS less than 100 pF.
When driving large capacitive loads, 470 pF an,

"

0

i'--..\.. .

Input ....

,5
~7.5

o

10M

.~

Cl

~

0

~ 60

l'.

0

o

Cc = 1000pF

g> 9 0

'. Cc =OpF

o

~~

Q)

·120

if

150

I--

.·20

::l

1'\

" l'

100
10k
Frequency, Hz

180

0>

~
>

1.5

.'!::

>

.•

0

E •

«

'"

E'

"

1.0

..........

N

I
",V+sc

~

5
()

0.5

,

t\

I I
Cc = OpF,v

I't--...LJ{

t\.

I~ V-

III

I

!

I I

0

I\.

1M

rOCl

.3

100

o"

96

c

--t---

I,

I

Tc = -55°C

I

~ j---

I

Tc=+25~C

c.
o
c.

r-

Tc=+125°C

JJ

92
15

20
25
30
35
40
Supply Voltage, ±VctW,

COMMON-MODE REJECTION
\l.S FRJ;QUENCY
.

r--""'-'T"'-:-.,...--r--,

110
III

±80~--+---+---1-__~--~

";:o

100

"
a:

80

~~

60

~

.~

",.,

i5.

Cl.

'"~"

c:

o
E

+25 +50 +75 +100 +125

Case Temperature,'Tc

~'-1W

lk ~'10k 100 k
Frequen~y Hz

r-- t-

~ 104

Z

o

108

"c

-'
o

-25

'rI

ys' SUPPLY VOLTAGE

()

j'-....

-'
,,>

100

112

QUIESCENT CURRENT
VS SUPPLy'VOLTAGE

±1 001

.'

..........

llJ

10 100 lk 10k lOOk 1M 10M
Frequency I Hz

1M

;,V-sc

"

I

o

25

Cc = l000pF

CURRENT LIMIT VOLTAGE
VS TEMPERATURE
2.0

Pout ~110W

, OPEN-LOOP GAIN

30

-

20

1

io

-

5
10 15
Time I~secl

3

OPEN-LOOP PHASE

1
100 1-0.

0

lLcCc =OpF

S- -2.5

OPEN-LOOP GAIN
VS FREQUENCY

"c

is
t

0

120

III

,/

:;

10k lOOk 1M
Frequency Hz'

~

r--

Cc = 1000pF

+2.5

I

Of--

±Vcc = 35V
ACL '" 10
Cc = WOOpF
Rsc =opo

±Vcc =±35V

0>

'\'1\
\\

> ±20
0

>

I

Cc =OpF

'5'"

:;
Cl.
:;

+5

RL =2511_

:>

0>

. DISTORTION VS FREQUENCY

+7.5
±Vcc =±35V

±40

Output Voltage I V I

VOLTAGE FOLLOWER
PULSE RESPONSE

±50

'"Cl.

t-----'l'---t--+-.,F--+--;
-1.t--I---+-"F-

:; -0.5
c.

Power Supply Voltage, ±Vcc [V,

1-170

g

40

()

20
10

'"
1.00

~

'"

lk
10k lOOk 1M
Frequency iHzl

INSTALLATION AND OPERATING INSTRUCTIONS
R .. = 1.3 (volts) . R .
+s( 1+limiiamps) ·sc

GENERAL PRECAUTIONS
Current Limiting

1.5 (volts)
1.limil(amps)

Iii"''' is the desired maximum (·urrent. The maximum
power dissipation of the resistors is Pm.. , = Rs(' (11"",tl'. The
current limits determined by the equations above arc
accurate to about ±IO";. The variation of I,,,,,,, versus
temperature is shown in the Typical Performance Curves.
Roth +VI"( and -VI"( must he on for the current limits to
function.

It is recommended that during initial amplifier setup.
particularly in breadboarding and when a lack of familiarity with the amplifier exists. that the current limit be set
at about 250mA (Rs(';;" 5.6!l). This will allow verification
of the circuit and will minimize the possibility of damaging
the amplifier. l.ater. when 'the circuit configuration and
connections have been proven. the current limits can bc
raj sed to the desired value.

Minimum Heat Sink
The 3571 AM and 3572AM require a minimum heat sink
of 16"C W or lower in order to insure thermal stability
(mounting on a 3" x 3" x 0.06" piece of Sorii copper-clad
printed circuit board material will be sufficient). ~ ormally,
this will not be a consideration since a larger heat sink will
be used to provide the proper power dissipation as
described if' the Thermal Considerations section which
follows.

To avoid introducing unwanted inductance into the
current limit circuitry. which may introduce oscillations
and permanent damage. both current limit resistors must
he noninductive. Do not usc wire wound resistors.
Carbon composition resistors arc preferred and paralleling them can provide a wide current limit range at the
wa ttage needed.
The maximum value of the negative current limit resistor
is 1511 (IOOmA. min). Exceeding this value. or an open
circuit. could permanently damage the internal 751L
thin-film resistor which parallel R.se.
The amplifier should be used with as Iowa current limit
as possible for the particular application. This will
minimize the chance of damaging the amplifier under
abnormal load conditions and increase reliability by
limiting the internal power dissipation of the amplifier.

Proper Grounding and Power Supply Bypassing
Particular attention should be given to proper grounding
practices because the large output currents can cause
significant grounding-loop errors. Proper connections
are shown in Figure 2.

THERMAL CONSIDERATIONS
The 3571 AM and 3572A M arc rated for 150"C maximum
junction temperature. The thermal resistance fromjunction to case (II,,) is 2.5"C W. The corresponding Power
Derating Curve is giyen in thc Typical Performance
Curycs.
The internal power dissipation ofthc amplifier is giycn by
the c4uation 1'" = P ,)() + Pili where P ,)() is the quiescent
power dissipation and Pili is the power dissipated in the
output stagc.due to.the load. (For±V , I = ±40V. 1',)(, = 80
.\ 0.035 = 2.8W. max). Forthe casc whcre the amplifier is
dri\ing a groundcd load (R, ) with a DC yoltage (±V,,",)
thcmaximumvalucofP", occursat±V"",=±V" 2and
is equal to Pili "'." = (±V,,-)' 4R , . 'Figure 3 shows 1'" as
function of the output yoltagc with thc load resistance as

FIGURE 2. Proper Power Supply Connections.
N ate that the connections are such that the load current
does not flow through the wire connecting the signal
ground point to the power supplv common. Also. power
supply and load leads sho~ld be physically separated.
from the 'amplifier input and signal leads.

ct

running. parameter.

Cl

a.

C

Q

~
"il

The amplifier power supply should be bypassed with 50,., F
tantalum capacitors connected in parallel with O.OI,.,F
ceramic capacitors connected as close to pins 3 and 6 as
possible. The capacitors should be connected to the load
ground rather than the signal ground.

is

~

o
a.

~

2

CURRENT LIMITS

c

The amplifiers are designed so that both the positive and
negative load current limits can be adjusted with external
resistors. R:"se and R.se respectively. The value of the
resistors are given by the following equations:

FIGU RE 3. Internal Power Dissipation vs. Output
Voltage.

1-171

-.....

~

P O [ for any nther value o{V"".~anbecomputed i~om'

POI. = (±V('" - ±V"",). h, = (±V"" _±v"".)'(±~"UI).
"

,

The use of an adequate heat sink is matidato,ry 'llnd
thermalresistanceofthe heat sink (0",) can be determined
from the equation:
8,,, = (T[ - T I'll) - 8[.,

where T.I is the desired amplifier junction temperature
'(+ ISO"C'. max), T, is the ambient te~perature. PIl is the
amplifiers dissipation. PI> = PI>O + PDI.. and 8,. is the
junction to case thermal resistance of the amplifier, Burre
Brown Application l'iote AN-83 entitk'd. "Howto Determine What Heat Sink to lise". i~availllble foradditi'(\nal
infornl

I"

~ 80

,

100

3

0

VOLTAGE FOLLOWER
PULSE RESPONSE

oLk~~put

75

= 120

\

0

10 100 Ik 10k lOOk 1M 10M
Frequency (Hz)

5

""' i\

Phase

~

I

50

5

0

Am litu e /

o
-20

R 1.01d

-30

I", ",I'

25

HARMONIC DISTORTION

OUTPUT VOL TAGE VS FREQUENCV

o

''\. r'\.

0

Case Temperature.Te (OC)

OPEN LOOP FREQUENCV RESPONSE

~

r- I"-

5

tiS

±_O

±25

±30 ±35

Power Supply Voltage (V)

INSTALLATION AND ,OPERATING
INSTRUCTIONS
GENERAL PRECAUTIONS

Rsc

Cl,IRRENT LIMITING
It is recommended, that during initial amplifier setup,

particularly in breadboarding and when a. lack of
familiarity with the amplifier exists, that the current limit
be set at about 250mA (Rsc 55< 2.6!l). This will allow
verification of the circuit and will minimize the possibility
of damaging the .amplifier. Later, when the circuit
configuration and connections have beep provep, the
current limits can be raised to the desired value.
PROPER GROUNDING & POWER SUPPLY
BYPASSING

Particular attention should be given to propergrounding
practices beC<\use the large' output currents can cause
significant ground loop errors. Figure I illustrates proper
connections.

0.65 (volts)
= -::-...:...~~:Iumi,(/!-mps)

hmit is the desired maxim~m current. The maximum
power dissipation of ihe resistors is· Pm.. Rsc (lumi,)2. The
current limits determined by the equations .above are
accurate to about ±lO%. The variation of Ilimi! vs
temperature is shown in the Typical P.efformance Curves.
The amplifier should be used with as Iowa current limit as
possible for the particular application. This will minimize
the chance of damaging the amplifier under abnormal ,
'load conditions and increase reliability by limiting the
internal power dissipation ofihe amplifier. "

=

THERMAL CONSIDERATIONS
The 3573AM is rated for 150°C maximum junction
temperature. The thermal resistance from junction to
case (8jc) is 2.8°C/W per watt. The corresponding Power
Derating Curve is given in the Typical Performance
Curves section.
'
The internal power dissipation of the amplifier is given by
the equation PI> = POQ + POL where POQ is the quiescent
power dissipation and POL is the power dissipated in the
output stage due to the load.
The thermal resistance of the required heat sink (8h.) can
be determined from the equation:

t1!..=

f'IGURE I. Proper Power Supply Connections.
Note that the connections are such thatthe.19ad current
does not flow. through the' wire, connecting the signal
ground point to the power supply common. Also, power
supply and load leads should be rurt physically separated
from the amplifier input and signal leads.
The amplifier should be. power supply bypassed with
50llF tantalum capacitors Connected in parallel with 0.0 I
IlF ceramic capacitors connected as close to pins 3 and 6
as possible. The capacitol'S should be connected to the
load ground rather thl[in the signal ground.

CURRENT LIMITS
The amplifier is designed so that both the 'positive and
negtive load current limits can be adjusted with external
resistors, R+sc and R-sc respectively. The value of the
resistors are given by the following equation:

where TJ is the desi~ed amplifier junction temperature
(+150°C max), TA is the ambient temperature, Po is the
amplifier's dissipation, Po "" POll + POL, and 8jc is the
junction to case thermal resistance of the amplifier.
The electrically isolated case of the 3573AM simplifies
mounting the amplifiers to the heat sink (and the heat
sink to any other assemblies) since there is no need for
electrical insulation. Thermal joint compound and lock
washers should be used to prevent mechanical relaxation
due t6 thermal stresses.
SAFE OPERATING AREA
There are additional constraints on the output voltage
and current other than those just due to the maximum
, internal power dissiphtion of the amplifiers. These are
related to the prevention of secondary breakdown in the
output stage transistors. These restrictions are shown in
the SAFE OPERATING AREA CURVES in the
Typical Performance Curves~

1-176

3580
3581
3582

BURR-BROWN~

IElElI

High Voltage
OPERATIONAL AMPLIFIERS
FEATURES

DESCRIPTION

• HIGH OUTPUT SWINGS, up to ±145V (3582)

The 3580 series is the first family of Integrated
Circuit operational amplifiers which will provide
output voltage swings of up to ± 145V.

• LARGE LOAD CURRENTS, up to ±60mA (3580)
• DIFFICULT TO DAMAGE, automatic thermal shutoff
• REDUCES SOURCE LOADING, 1011 n Input Z
• PRESERVES SYSTEM ACCURACY,
110dB CMR 20pA bias current

The monolithic I-TT input stage has low bias currcnts
(20pA) which minimi/cs the offset \"oltages caused by
thc bias currcnt and the largc rcsistancc normally
associated with high \"(lltage circuits.
The 3580 series is packaged in a TO-3 package which
will dissipate over 3W of power without a heat sink
and 4.5W with a suitable heat sink.
The input stage is protected against overvoltages and
the output stage is protected against short-circuitsto-ground. A special thermal sensing circuit prevents
damage to the amplifier by automatically shutting
the amplifier down when too much power is being
dissipated.
.

OFFSET TRIM
3r-"""'-f

+IN

Inl8rnlllllllll Airport Induslrlal Park· P.O. Box

11400· Tucsan. ArlzlIIII 85734· TIl. 1BD2I 746·1111

1-177

. Twx: 910-952·1111 . Cabll: BBRCORP· Tlllx: 66-6491

THEORY OF OPERATION
advantages not normally available'in mand ±Vcc max unless otherwise noted.

OUTPUT VOL TAG" VS
FREQUENCY

SLEW RATE VS SUPPLY'
VOLTAGE AT FULL LOAD

CURRENt LIMiT VS
TEMPERATURE

+30

><

'"
1l.

1.0 t--+,--+--j~+-+--7--1

1251--+HttH1,~

~:

>

~ 100~++1~~~r+++HHt-4-i

rr

~
g

iii.
."0

~.

~ 50~++4+H~~~;+HHt-4-i

:;

~:l

(ij

E

~

~

cij

'? 80

"

'0;

e

.s"

I'
~

40

"0

I\.
10k lOOk 1M 10M

50

60 70 80' 90 100 110
power Supply I % of max 1

NORMALIZED INPUT BIAS'
CURRENT VS TEMPERATURE

C 1000

V

100

...,.11'

~

0

:;

1

V

~

'a o. 1
0,0 1

0.00 1
-50

25 50 75 100 125

'-

10'1---+---+---1---+--+---1
10

100

lk

10k lOOk 1M

Frequency, Hz

100

125

150

104

Amplifier
Shot Noise

150

105

1
106

107 106

N'251--~r+Hflff--t~~~--f-ti
'

I

~1001--~~~ff--+~~~--f-ti

-g
~

o

 20

o~

,

OPEN-LOOP GAIN vs SUPPLY
VOLTAGE AT MAX LOAQ
+1r--r--~~~--~-r-'

~82
358.1

60

(!l

""

-30

-60 -25

Power Supply' % of max'

OPEN-LOOP FREQUENCY
RESPONSE-FULL LOAD

100

-20

-40

100

r

~

0

~

.!:!

Frequency I kHz'

120

~

() -1 0

,

~ 08

25~~~~~U

o

'"

1:

~0.9~-+_+--+

.75F*,*~~'Ys"';;1

~ +20

'E

:::i +1 0

f = O,OlHz to 10Hz

106
107
108
Source Resistance (!ll

POWER SUPPLY REJECTiON
VS FREQUENCY

3581

&3~82

~110 ~ i"'Both Supplies
0
':g"
"
rr,.,
'ij)

90

.h

70

......

3580
Ci 50
c.
Positive Supply
:l
. ---=.oOnly

'"~
0
D..

r---

-J.~
Neg. Supply

"

30

~

10
10

100

lk

10k

lOOk

Frequency (Hzl

1M

BURR-BROWN®

3583

I ESIESI I

High Voltage - High Current
OPERATIONAL AMPLIFIER
FEATURES

APPLICATIONS

• HIGH OUTPUT SWINGS. Up to ±140V

• PROGRAMMABLE POWER SUPPLY
OUTPUT AMPLIFIER

• LARGE LOAD CURRENTS. ±75mA
• PROTECTED OUTPUT STAGE. Automatic Thermal Shutoff

• HIGH VOLTAGE CURRENT SOURCE
• POWER BOOSTER

• REDUCES SOURCE LOADING. lOll n Input Z

• HIGH VOLTAGE INTEGRATOR

• PRESERVES SYSTEM ACCURACY.
"OdB CMR 20pA Bias Current

• DIFFERENTIAL AMPLIFIER FOR HIGH
COMMON·MODE VOLTAGE CIRCUITS

DESCRIPTION
The 3583 is the first integrated circuit operational
amplifier to provide output voltage swings of±140V
with c.urrents as high as ±75mA.
The amplifier operates over a wide supply range
(±50VDC to ±150VDC) and has excellent input
characteristics (I10dB CMR. 3mV Yos. 25!-'Y "c
.l Vos' .IT).
The monolithic FET input stage has low bias current
(20pA) which minimizes the offset voltages caused by
the bias current and the large resistances normally
associated with high voltage circuits.
The input stage is protected against overvoltages and
the output stage is protected against short-circuits to
ground for supply voltages below ±IOOVDC. A
special thermal sensing circuit prevents damage to
the amplifier by automatically shutting the amplifier
down when too much power is being dissipated.
Two temperature ranges are available: O"C to +70"C
(3583JM) and -25°C to +85"C (3583AM).

Intemllional Airport Industrial Park - P.O. Box 11400 - Tucson. Arizona 85734 - Tel. 1602) 746-1111 - TWI: 910-952·1111 - Cable: BBRCORP - Telex: 66-6491

1-181

SPECIFICATIONS

~,

."

'"

Elf;CTRICA,l
Specifications typi~1 at TeASE = +25°C and ±Vee = lsOVDC unless otherwise noted.

I

MODELS

3583AM

I

~----~~~~~~~~~~

~83JM

POWER SUPPLY
±50VDC to ±150VDC
,
8.5mf' '

Voltage, ±Vcc
Quiescent Current, max

,,'

RATED OUTPUT
Voltage. ±, I,Vee!-10'VDC. min
Cu~rent.

±40VDC to ±140VDC
±75mA
±100mA
'. ", ·,,~.1OnF
'~'" ',.

min

Current, Short Circuit
Load Capaci.tance. max,

','."

OPEN'LOOP GAIN

.

,.118dl3 ,
94dB, ;"'ih; i05dB. Iyp

~"

No Load. DC
Rated Load. DC
FREQUENCY RESPONSE

".

. ,',.,

...

,:
'5MHz

Unity Gain Bandwidth, Small Signal
Fulll?ower Bandwidth. R, =.10~1l
Slew Rate
Settling Time. 0.1%

_~

1

,,6p~Hz

30Vl.u sec

12J.1.sec

,

INPUT OFFSET VOLTAGE' T,,';+25°C
Initial at 25°C, max
Drift vs Te,mp, max

±3mV

.,-

Lead. iri'1ru8 position'withln :010"
R IP MMC lit seating plana.

±20~VIV

(.2~,:"m)

±50~V/mo
PI" "umb.rll shown ~or re~.'.nce o"ly.

..

INPUT BIAS CURRENT
Initial at 25°C, max
Drift vs Temp
Drift vs Supply Voltage

, NOTE'

'±23~/oC

f',

Drift vs Supply Voltage
l)rift vs Time

~I:'m~rs ma,V

i

-20pA
doubles every 10°C
;'.
0.2pAIV

,

OROeR NlJMBER,:
3583AM
3583JM
WEIGHT:
. ,15,IGrams

INPUT OFFSET CURRENT
±20pA
doubles every 10°C
0.2pAIV

Initial at 250 (:
Dri'ft vs Temp
Drift vs Supply Voltage

MATING CONNECTOR:
0803MC

INPUT IMPEDANCE

..

1.510
.745

1.550

0

'c

,300

~400

5~V

0

.030

.042

1.7~V

E

.08.

.105

INPUT NOISE
Voltage 0:01 Hz to 10Hz. pep
10Hz to 1kHz, rmS
Current 0.01 Hz to 10Hz. p-p

INeMes
MIN
MAX

OIM

10111l1110pF
101111

Differential
Common-mode

·0.3pA

H'

TEMPE,RATURE RANGE (Casei
Specification
Operating
Storage

'+Vee+I-Vee! '
+Vee to -Vee

--25°C to

38.35
18.92

39.31
1Ui6

7.62
0.97

10.16
1.07

2.67
2.03
40° BASIC
12.7 BASIC
30:12 BASIC

.583 aASIC
.400
.600

15.0& BASIC
10.1S
12.70

Q

.151
.980

3.84
24.89

.161
1.020,

4.09
26.91

CONNECTION DIAGRAM

+85~C 10°C to 700C
-55°.c to +125°C
-~5°C to +125°C

NOTES:
1.The inputs may b~ damaged by pulses at pins 5 or 6 with dV/dt;>-1V/nsec.
Any possible damage can be eliminated by limiting the input current to
150mA with external resistors in series with those pins. No external protection
is needed for slOwer 'voltage changes.
.

MIU,IMETERS .
MIN
MAX

J,

R

±,! Vee!-tO,V
110dB :'

.770

40b BASIc'
.500 RASle
1.186 BASIC

F
r.

INPUT VOLTAGE RANGE
Max Safe .oiffe~ential Voltage(1')
Max Safe Common-mode Voltage
Common-mode Voltage, Llnear
Operation
Common-mode Rejection

not- be ~.rk,.d 0." pack.,•.

Optional
Offset Adjust
:

TO'
+Vee

ITop View I
.,

r-'" --,

<'00k!,1

-~L

4 '

Offset Trim
-IN

• No internal connection.
The metal case is electrically isolated.
lt is recommended that the case be
grounded during use.

1-182

TYPICAL PERFORMANCE CURVES
Typical at TeASE = +25°C and ±Vcc

OUTPUT VOLTAGE vs
FREQUENCY

150

""

125

!:'

100

Q.

.,;

-

Jsll\~~

SLEW RATEvs
SUPPLY VOLTAGE

_

~ +20
E +10

II:

:J

?

C
!!

0

()
t:l

-10

.!>!
'OJ

-20

~

~

II:
~

50

.!!

\

25

0

o

10

en

20

100
1000
Frequency IkHzl

IXl

80

'""

'OJ



'"

l!!
'0

5Q. -50
5

TOTAL LOW FREQUENCY INPUT
NOISE vs SOURCE RESISTANCE
10,000r---.,...--..,..--....,
10001------1:---+---1

5Q.

J--I~-I''-+-1'''---t---;

Thermal Notse

100
1001-----+--

II:
'0
z

10
10 Noise_+-_---,::...I~'--__I

5.0
1.7
1

..E

t

~

I-

106 10'
Source Resistance (n I

Output Voltage ,VI

150
Vee

'"

150

+150V
,

I"iIo.

'-

::;: 70
()

125

-

111111
linear Operation
I

50

~
E

8

iii

110

~

90

'tJ
"

11111111

Vee = ±150V

>-

is.

50

en"

30

~

10

Q.

50

~

25
lOOk
1M
Frequency (Hz)

1-183

nI

"-

'm 70

75

10k

106
I

r-..

"-

II:

10
100 lk 10k lOOk 1M
Frequency (Hz)

106
10'
Source Resistance

POWER SUPPLY REJECTION
vs FREQUENCY

g 100

~
=ii

30

10

105

106

COMMON-MODE
VOLTAGE vs FREQUENCY

COMMON-MODE REJECTION
vs FREQUENCY

90

i

75 100 125

Case Temperature. Tc (oC·

~

". 1000

II:

50

Q)

5O .....~-1~~

>

iii

25

2.5

~

100

110

0

--~

'OJ

TOTAL INPUT NOISE VOLTAGE
vs SOURCE RESISTANCE
~ 10,000 r - - r - - r - - T " " - " - - "

130

..... r--.,.I

10.0

~

150 r--r--,-,....:,.~,.......,

-100

-.--

I"

, RECOMMENDED
POWER DERATING

c

~
E
1;

"-

Case Temperature (oC i



RL =2kO

75

5Q.
5

150VDC unless otherwise noted.

50

Q)

~'"
>

=::

3M

10

"-

"
100

lk
10k lOOk
Frequency (Hz)

1M

, APPLrCATIONS INFORMATlON
The 3583 is a high voltage, high output current integrated
circuit operational amplifier. Its ease of use. compact size:
and excellent input and. output specifications makes it
well suited for a wide varIety of high voltage applications.
The equivalent circuif fo'r the 3583 is shown in Figure I.
The design uses a monolithic FET input stage for high
input impedance. low bias current, and low voltage drift
versus temperature. The offset voltage at 25"C and the
drift versus temperature are compensated by state-of-the'art laser-trimming techniques. They are low enough so
that user-trimming will noi be required in mo~t applicaions. The high input' impedance provides negligible
source impedance loading errors when the noninverting
circuit configuration is used., The low bias currents
minimize offset errors when large values of source and
feedback resistors are used.

FIGURE I. 3583 Equivalent Circuit.
A true cascade input stage is used together with considerableprotection circuitry. There are voltage liJl1iting
transistors to prevent damage due to reverse bias
breakdown of the input pair and current limiting resistors
to limit the input current to I rnA with the inputs at ±150,
Hllt" The unit> arc conservatively rated (and 100'ii'
tested) at full rated diffcr.ential voltage (+150V and
-150V) but typically will withstand a 50'; ovc';'voltage
without damage.
.

The unit operates over a wide supply range (±50V to
± 150V) with outstanding common-mode rejection (II Od B).
.It also has another feature which is important in many
high voltage applications:' The input bias current is
virtually independent of applied commoncmode voltage.
The output circuit has a unique,protection ieature which
is only practical iii iritegrated-circuit amplifiers - sclfcoritained automatic thermal sensing and.·shutoff circuitry which ,automatically turns the amplifier off when
the internal temperature reaches. approximately 150"C.
T!)is is accomplished by sensing the substrate temperature
and ,deactivating the amplifier's biasing network when
the. temperature reaches 150"C. As this happens, the
output load current limits at a safe value and the
amplifier's quiescent current decreases. The output
current will remain at a low value or oscillate between
two values depending on the amount of power being
dissipated and the heat sink conditions seen by the
arnplifier. In either case, the amplifier will not sustain
internal damage and will return to normal operation
. wit~in a few seconds after the abnormal load condition is
reinoved.
Thii internal thermal prolection removes some of the
,constraints of power derating for abnormal operating
conditions. The amplifier will protect itself for many
co"ditions of ex<;ess power dissipation (see the Power
Derating Curve). This allows the lise of a smaller heat
sink to protect against abnormal output conditions since
the all)plifier has its own internal protection for many
conditions of excess 'power dissipation. The output
constraints of the Recommended Safe Operating Area
curves must still be observed.
Th'e 3583 has several other features that improve its
utility. 'For instance, the rrietal case of the unit is
completely electrically isolated. (This can be contrasted
to most power semiconductors where the case is connected
to the collector of the device.) This simplifies mounting
and reduces cost since the need for insulating spacers and
bushings is eliminated. The hermetically sealed package
improves reliability and will more easily withstand severe
environments than do discrete component amplifiers.
The small package size reduces weight and makes
mounting more convenient.

1-184

Burr-Brown offers three heat sinks as accessories;
0803HS with a thermal resistance of J 2°C; watt,
0804HS at 4.2"C; watt, and·0805HS at 3°C; watt.
A convenient mating connector, 0803 MC is also available.

3584

BURR-BROWN®

IElElI

High Voltage
OPERATIONAL AMPLIFIER
FEATURES
•
•
•
•
•
•

TYPICAL GAIN·BANDWIDTH. 50MHz
OUTPUT. +145V
PROTECTED OUTPUT. automatic thermal shutoff
BIAS CURRENT. ·20pA
CMR. 110dB
SLEW RATE. 150V/usec

APPLICATIONS
•
•
•
•

ANALOG SIMULATORS
DlGITALLY·CONTROLLED POWER SUPPLIES
CRT DEFLECTION
ELECTROSTATIC TRANSDUCERS

DESCRIPTION
The 3584 is a high voltage. integrated circuit operational
amplifier that will provide up to ±145V output.
The amplifier will provide a gain-bandwidth product of
20MHz. minimum, 50MHz typical. The amplifier uses
external frequency compensation (one R and one C) so
that the user may optimize the bandwidth and slew rate
for his particular application.
The amplifier operates over a wide supply range
(±70VDC to ±150VDC) and has excellent input
characteristiC$ (IIOdB CMR. 3mV Eo.. and 25p.V j"C Eo<
Drift). The input stage is a FET. The low -20pA bias
current minimizes the offset errors caused by the large
value resistors normally used in high voltage circuits.
The input stage is protected against overvoltages and the
output stage is protected against short circuits to ground.
A special thermai sensing circuit helps to prevent damage
to the amplifier by automatically shutting the amplifier
down when too much power is being dissipated.
Intarnatlonal Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734 • Tel. 1602) 746·1111 . Twx: 910-952·1111 . Cable: 8BRCORP . Telex: 66·6491

1-185

DISCUSSION
The 3584 is a high voltage, integrated circuit operatiQnal
amplifier. Its ease of use, 'compact size, and, e"Jelbhlt
input and output specifications makes it well suited for a
wide variety of high voltage and high speea applications:
,
The design uses a monolithic 'FET input stage for high
input impedance, low bia, current, and low voltage drift
, versus temperature. The offset. voltage and the drift are
, laser trimmed. They are low enough so that user trimming
will not be required in most applications.
To achieve the high common-mode voltage capability
and rejection a true cascode input stage is used together
with considerable protection circuitry. There are voltage
limiting diodes to prevent damage due to reverse bias
breakdown' of the input pair and current limiting resistors
to limit the steady state input 'current to ImA with the
inputs at ±ISO volts. The units are conservatively rated(and 100% tested) at full rated differential voltage (+ISO
and -ISOV) but typically will withstand a 50%
overvoltage without damage.

OPERATION 'FROM A$INGLESUPPLY
It may be desirable in some applications to operate the
,amplifiers from a single supply. ,The ci~cuit in Figure I
illustrates a typical application. Note that there are
restrictions on the input and output voltages (e, and eo)
which are necessary in order to keep the amplifier circuits
operating in a linear manner.
It should be noted that when the amplifier is operated

from a single supply, the Output stage, which is still short
circuit current limited and thermally protected, is not
protected for short circuits -to gr'ound under all operating
conditions. Consult the safe operating area curve.

+JOOV

·0

RO+ RI
(--R-- )
1

+IOV .. ej" +290V
+sv

It also has another feature which is important in many
high voltage applications. The input bias current is
virtually independent of applied common-mode voltage.
This is a benefit of the true cascode input stage which
keeps the drain to source voltage of the input trans~tors
,'constant as the common-mode voltage changes.
, Theamplifi,ercontains automatic thermal sensing and
shut-off circuitry which automatically turns the amplifier
off when the internal (substrate) temperature reaches
approximately ISO'C. This is accomplished by sensing
the substrate temperature and deactivating all current
sources when the temperature reaches a critical level. As
this happens, the output current gradually decreases to
zero. The output current may remain at a low value '9r
oscillate between 2 values depending on'the amount of
power being dissipated and the heat sink conditions seen
by the amplifier. In either case, the amplifier will not
sustain internal damage and will return to normal
operation within a few seconds after the abnormal
condition is removed.

= ej

"'0" + 290V
+

'0

FIGURE I. Operation from a single supply.

+!30VDC to +28SVDC
HVDC

+1 SVDC

(1)

13

22
IS

It

DAC80-CBJ.I

21

12

The incorporation of thermal sensing and shut-off in the
amplifier will require a smaller heat sink than normal.
This is due to the fact that the amplifier will protect itself
and does not require a massive heat sirik for protection
under abnormally high power dissipation.

-lSVDC

NOTES:

The 3584 has several other features that improve its
utility. The metal case of the unit is completely electrically
isolated. This simplifies mounting and reduces cost since
the need for insulating spacers is eliminated. The
hermetically sealed package improves reliability and will
withstand severe environments better. And the smaU
package size reduces weight and makes mounting more
'
convenient.

1. May be connected to + lSVDC.
2. Use for DAC gain adjust. Vout = (I DAC OUT)(Rt).
3. Optional offset adjust.

FIGURE 2. High Speed, High Voltage OAt.

1-186

V out

SPECIFICATIONS
ELECTRICAL

MECHANICAL

Typical at 25"C and ±V« max unless ptherwisc nOled.

MOOELS

3S84.iM
2.54
mm"

POWER SUPPLY
Voltage. ±Vee
Quiescent Current. max

±70 to ±ISO VDC
±6.SmA

(o.l

rr

l)

I

TO·3

r1
,-1----'--

IO.16mm

J9.62mm
(1.56")

I

(0.40")
max

I

RATED OUTPUT
Vollagc. ± ( I V-J -S)VDC. min

±6S to ±14S VO<'

('urrent. min

±ISmA
±2SmA
10 nF

Current. Short Circuit
toad Capacitance. max

OPEN LOOP GAIN
No Load. DC

120 dB
1000B

Rated Load. DC. min

FREQUENCY RESPONSE
Unity Gain BandM'idth. Small Signal
Gain-bandwidth Product. (= I kHl. G =100

TMHz
20 MHz, min

Full Power Bandwidth. G = 100
SlewRate.G= 100,
Setlling 1 imc. O.Il',f.• G = 100

INPUT OFFSET VOLTAGE
zSOc. max

InitIal.

Drift V) T cmp. max
Drif! vs Supply VollallC
Drift vs Time

135 kHz
150 V/~s

3.96mm +0.13

1210's

(0.156 !0.005")
dia

3 mV
25 ~VrC
20 ~V/V
50 II-V/mo

INPUT BIAS CURRENT
Initial @ 2SoC. max
Drift VI Temp
Drift .. Supply Volt...,

Pin material and plating composition
conform to Method 2003 (solderability)

·lOpA
doubles every IO"C
0.2 pA/V

of MiI·Std·88J I except paragraph ·3.21

INPUT OFFSET CURRENT
Initial@ 2S"C
Drift VI Temp
Drift VI Supply Vol....

CONNECTION
DIAGRAM

±20 pA
double, every IO"C
0.2 pA/V.

(TOP VIEW)

INPUT IMPEDANCE
Differential
Common Mode

Optional
10"

n II

Offset

10 pF

Adjust

lO" 0

INPUT NOI,§E
Voltase 0.01 Hz to 10 Hz p-p
10 Hz to 1 kHz rms
Current 0.01 Hz to 10 Hz p-p

Off.et

r-

100kO!

To

5 ~V
1.7 ~V
0.3 pA

--...~

+Vcc

L

Offset

Trim

INPUT VOLTAGE RANGE
Max Safe Differential Voltage!!1
MaX. Safe Common Mode Voltage
Common Mode Voltage. Linear
Operation
Common Mode Rejection

·IN

±( I V" I -IO)V

IIOdB

TEMPERATURE RANGE (Case)
SpecifICation;

Operating
Storase

Compensation

(+V ... +I-V .... ')
+Vu to -VI;#.

Connector: 080JMC
ODC to 70P C
-SS"C to +12S"C

Healsinks: 0803HS. 0804HS. or 0805HS

-'S·C to -+ISO"C

Compensation
Gain

20011

10 nF
(I) The inputs may be damaged by pulses at pins !i or 6 with dV , dt ~ I V! ns Any possible damage
can be eliminated by limiting the input current to 150mA with external resistors in series With those
pins. No external pr~tion is need~ for !dower voltage chan,es.

10
100
1000

SOOF

2kn
20kn

SO pF
not required

"'or mtermediate \lalues of gain. R and C values may be
interpolated.
.
I he case IS electrically isolated. It is. recommended that the
case be grounded during use.

1-187

Typical at 2s0C;,8·nd".tV cc max un'less'othetwise'noted:'
OUTPUT VOLTAGE VI FRE'IiUENCY

SLEW RATE VI SUPPLY VOLTAGf. FULL LOAD

IS 0

Co~pensation :

~

\

~
~

~
.8
:!!

~

1\

.7

0

Z

0

10k

10M

io"

V
0

I

I

40

.

0

SO
60
'70
80 90
Power Supply (% of Max)

Frequen~ (Hz) .

r-

./

V

.s

lOOk

./'~

1/

160

./

'oC.s-j./
,0"'" ./
r- r-~}Z~"-~
.g"-

.6

:os:

0

and .ol.pF

I

.9

"0

'SLEW RATE VI COMP,ENsATlOil

I

CompensatiOn:, loo

1.0

200n and :OlpF'
kO and 500 pF
20k.{l JD~ 5,0 pF

,

0

I .

I

HIIIII I I

100

200
2k
20k
External Co~pensation 'lmpeda~ce (n)

OPEN LOOP GAIN VI SUPPLY
VOLTAGE iii MAX LOAO

OPEN LOOP FREDUENCY RESPONSE FULL LOAr
120

,

,

PQWER

DISSI~ATlON

........

,1'-

100

.,

80

~ 60
c

~

~

40

>

20

-5

" ""
'" ." \

o

r-- ~,c.s-~s...-~

Compensation:
200n and .01pF I-'\.
2k.{l and 500 p
20!tn and 50 pF

'/

,~
~,

..

·5

\\.

·20
10

100 Ik

10k lOOk 1M

J

10M

SAFE OPERATING AREA (Soc......., Bnakd....)

V

/.::

0

/
V

~

o

·20

/

1/

~

~ pO

o

20

100

~

10

,

.....

'§+IO

~

0

"

~-1O

i--+---ti-F

100

i-

125'

150

108

o

·25

-r-.

;::J::s:'.~~~,F-

III

~

120

II

II

25

-

1'1..

2000 and ,Ol,u:F

10k

"
lOOk
Frequency (Hz)

1-188

75

100

,.

"

~

"

~

,.

50

POWER SUPPLY REJECTION

JlJ

Compensaticm:

1M

""

Case Temperature (OC)

MAXIMUM COMMON·MODE
VDLTAGE VI FREQUENCY

100 Ik
19k lOOk
Frequency (Hz)

I........

Amplifier Noise

Source Resistance (n)

,

"

20
o
Z-30

o
10

75

CURRENT LIMIT .. TEMPERATURE

r--j--+---+-,

~

0
I

50

NOISE .. SOURCE RESiSTAN,CE

+50 +100 +150

"-

40

""

100

Temperature (OC)

120

80

90

;::;

COMMON-MODE REJECTION

.,

80

Power Supply (% of Max)

Output Voltage

,

70

~+20

~

1

P
Smsec

·30
·150 ·100 ·50

100

~

o
60

1:

Intemal cu!ent Limit

;;
:HO

9JA :::'!2 0CfW

I

-=? 1000 t--+---j--+---t--..-H

1/

~

~

>

I

e
=
0

;~

§

5msec

O~

,

1\

~t>",)

~-r-

50

Frequency (Hi)

30

"1

,- c...,
V~
,

\

1

8IC·12.C/W

.~.g7 ""1/ I-"""

"."
"

0

(C~)

~
~ POSitive Supp Y

-,

Negative Supply

I

o
1M

3M

10

100

~

"

Ik
10k lOOk
Frequency (Hz)

INSTRUMENTATION
AMPLIFIERS

WHAT IS AN INSTRUMENTATION AMPLIFIER?
An instrumentation amplifier is a closed-loop, differential input gain block. It
is a committed circuit with the primary function of accurately amplifying the
voltage applied to its inputs.
Ideally, the 'instrumentation amplifier responds only to the difference
between the two 'input signals and exhibits extremely-high impedances
between the two input terminals, and from each terminal to ground. The
output voltage is developed single-ended with respect to ground and is equal
to the product of amplifier gain and the difference of the two input voltages
(see Figure 1).

FIGURE 1. Idealized Model of an Instrumentation Amplifier.
The amplifier gain G is normally set by the user with a single external
resistor. The properties of this model may be summarized as infinite input
impedance, zero output impepance, the output voltage proportional to only
the difference voltage (e2" e1), a precisely known gain constant (implying no
nonlinearity), and unlimited bandwidth. This amplifier would completely'
reject signal components common to both inputs ( common-mode rejection}
and would exhibit no DC offset voltage or drift.

2-1

CHARAC'TERISTU::S: Qf\ ;,{,,' . '.
INSTROMENTATlONAIViF!LJF.IERS
.~,

I

It is desirable to achieve, as close as possible, the characteristics of the ideal
instrumentation amplifier. The following paragraphs are a discussion of the,
other-than-ideal, characteristics of the instrumentation amplifiers.
Input Impedance - A simple model of rea!i~tic instrumentation amplifier is
shown in Figure '2: The in'lp~dance Zid.tepresents the differential input
impedance. The common-mode input impeqance Zicm is represented as t,wo

+.

FIGURE 2. Simple Model of an Instrumentation Amplifier Shown in
..
··a Typical Application Configuration.
.
equal compol)ents, 2Zicm,. from each input to ground. These finite resistances
contribute an effective gain error due to loading of the source resistance.
The instrumentation amplifier provides a load on the source of Zi =Zid II Zicm.
If source impedance isRs = Rs 1+ Rs2. the gain error caused by this loading
is:
Gain Error = 1-

~=~",RSifZ.> R

Zj + Rs

Zj + ,Rs

Zi

1

S

If Rs is 10kO and Zi is 10MO,

108103
Gain Error;;;: - - - : : : 0.1%
10 x 10 6
.

The DC comm~m-mode input impedance Zicm will be independent of gain.
The DC differential input impedance Zid may vary as a function of gain.
Specifications give the worst-case value. The nonzero output impedance of
the amplifier will also create a gain error, thevalue of which depends on the
load resistance.
Nonlinearity - The linearity of gain is possibly of more importance than the
gain accuracy, sincethevalueofthegain can be adjusted to compensate for
simple gain errors. The nonlinearity is specified to bethe peak deviation from
a "best fit" straightline, expressed as a perc~nt of peak-to-peak full scale
output.
Common-mode heJection - As illustrated in Figure 2. the output voltage has
twO components. One .component is proportional to the differential input
voltage ed c= (e2 - e1). The seCond component is proportional to the commonmode input voltage. The common-mode voltag.e which appears at. the
amplifier's input terminals is defined as Ecm = e2 + e1/2. Thj"s may consist of
some common-mode voltage in the source itself, eem, (such as bridge
excitation) plus any noise voltage, en. between the source common and the
amplifier common. As shown in Figure 2, the constant G represents the

2-2

differential amplifier gain factor (fixed by the external gain-setting resistor).
The constant (G/CMRR) represents the commo-mode signal gain of the
amplifier. The CMRR (common-mode rejection ratio) is the ratio of differentia! gain to common-mode gain. Thus CMRR is proportional to the
differential gain and CMRR increases as the differential (gain G) increased:
Hence, CMRR is usually specified forthe maximum and the minimum values
of gain of the amplifier. The common-mode rejection may be expressed in
dB as - CMRR (dB) = 20 log10 CMRR.
For an ideal instrumentation amplifier the output voltage component due to
common-mode voltage should be zero. For a realistic instrumentation
amplifier, the CMRR though very high, is still not infinite and so will cause an
error voltage of Ecm/CMRR x G to appear at the output.
Source Impedance Unbalance - If the source impedances are unbalanced
the source voltages (ecm + en) are divided unequally upon the commonmode impedances and a differential signal is developed at the amplifier's
input. This error signal cannot be separated from the desired signal. In the
circuit in Figure2 ifRs2=O, Rs1 =1kn, ecm +en =10V, and.Zcm = 100Mn, then
the effect of unbalance is to generate a voltage.
e 2 -el

= 10V -

t0 8
10V 10 8 + 10 3

= 10V

10 3
10V
)08 + 10 3 ~-;-;;s= O.lmV

If ed full scale is 1OmVthen this error is:
O.lmV
Error :;::--::: 1% of full scale.
IOmV

Offset Voltage and Drift - Most instrumentation amplifiers are two stage
devices - they have a variable gain input stage and a fixed gain output stage.
If Vi and Vo are the offset voltages of the input and output stages respectively,
then the amplifiers total offset voltage referred tothe input (RTI) =Vi + Vo/G
where G is the amplifier's gain. [Note that Eos (RTI) x G.]
The initial offset voltage is usually adjustable to zero and therefore, the
voltage drift is the more significant term since it cannot be nulled. The offset
voltage drift also has two components - one due to the input stage of the
amplifier and the other due to the output stage. When the amplifier is
operated at high gain, the drift of the input stage predominates. At low values
of gain, the drift of the output stage will be the major component of drift.
When the total output c;lrift is referred to the input, the effective input voltage
drift is largest for low values of gain. Output voltage drift will always be
lowest at low gains. If ~Vi/~T = 2p.V/oC and ~Vo//),.T = 500p.VjOC and the
amplifier in a gain of 1000VN is nulled at 25°C, then at 650C the offset
voltage will be:
Eos (RTl} 650 = 40°(' 121'V/oc + (5001'V IOC/I OOOV IV) I
40°C (2.5P.V/°C) 100l'V O.lmV

=

=

=

If the full scale input is 10mV then the error due to voltage drift is:
Error = 0.1 mV 11 OmV = 1% of full scale.
Input Bias and Offset Currents - The input bias currents are the currents that
flow out of (or into) either of the two inputs of the amplifier. They are the base
currents for bipolar input stages and the JFET leakage cljrrents for FET input
stage. Offset currents are the difference of the two bias currents.
The bias currents flowing into the source resistances will generate offset
voltages of Eos2 = 182 X Rs2 and Eos1 = 181 X Rs1. If Rs1 = Rs2 = Rs/2 the offset
voltage at the input is Eos2 - Eos1 = los x R x/2. This input referred offset error
may be compared directly with the input voltage to compute percent error.
INote that the source must be returned to power supply common or Rs will be
infinite and the'amplifier will saturate.)

2-3

. APPLICATIONS OF INSTRUMENTATION
. AMPLIFIERS
In·strumentation amplifiers are generally used in applications where extracting and ·accurately amplifying lowleilel differential Signals riding on
high common~mode voltages (±10V)is very important. Such applications
require high input impedance, high CMRR, low inp.ut noise, and excellent
DC levels stability (low offset voltage drift).
·Instrumentation amplifiers are used as transducer amplifiersforvarious
types of transducers such as strain gage bridges, load cells, thermistor
networks, thermocouples, c.urrent shunts, biological probes, weather
gauges and so forth. Other applications il")clude recorder preamplifiers,
multiplexer buffers, servo error amplifiers, current sensors, signal condition-ers in process .control and data acquisition systems, and in geni:lral
measurements of small differential signals riding on ·common-mode.
voltages.
The small size, low cost, and high performance of these amplifiers offer an
attractive approach for data acquisition applications, that is, assigning a
fixed-gain amplifier to each transducer and locating the amplifier physically
near the transducer. This approach largely eliminates common-mode·noise .
pickup problems since a high level signal (rather than a low level transducer
signal) is then retransmitted to the data gathering station. The result is a
higher signal/nOise ratio at the output.. Using one amplifier per point may
well. be more economical, a~ well as offering better peformance and
flexibility, than the approach of using low level multiplexers.

2-4

SELECTION GUIDE
INSTRUMENTATION AMPLIFIERS
Input Parameters

Gain

Description

Model

Very-High

INA104HP
INA104JP
INA104KP
INA104AM
INA104BM
INA104CM
INA104SM

Accuracy

INA101AM
INA101CM
INA101SM
INA101AG
INA1()lCG
INA101SG

General
Purpose

Gain
Range

'_100012l
'_100012l
1-1000 121

'_1000121
'_1000121
'-1000(2)
'_l000l2J

,_l000llill
1-1000121
'_1000121

l-100012f
1-1000 121

'_1000121

vs Temp
max I.J,tVlOC)

G=loo
±3dBBW
(kHz)

Temp
Range

Unbal ... min

'"

Package

Page

96dB
96dB
96dB
96dB
96dB
96dB
.96dB

±(2±2O/G)
±(0.25 ± 101G)
±(0.75 ± 101G)
±(2± 2OIG)
±(0.75 ± 101G)
±(0.25 ± 101G)
±(0.75 ± 10/G)

25
25
25
25
25
25
25

Com
Com
Com
Ind
Ind
Ind
MIL

DIP
DIP
DIP
DIP
DIP
DIP
DIP

2-15
2-15
2-15
2-15
2-15
2-15
2-15

±0.007
±0.004
±0.004
±0.007
±0.003
±O.OO3

96dB
96dB
96dB
96dB
96dB
96dB

±(2 + 20/G)
±(0.25 + 10/G)
±(0.25 + 10/G)
±(2+2O/G)
±(0.25 + 101G)
±(0.25 + 101G)

25
25
25
25
25
25

Ind
Ind
MIL
Ind
Ind
MIL

To-loo
TO-loo
To-loo
DIP
DIP
DIP

2-7
2-7
2-7
2-7
2-7
2-7

96dB
96dB
96dB
96dB

±(2+ 2O/G)
±(0.75 + 10/G)
±(0.25 + 10/G)
±(0.75 + 101G)

25
25
25
25

Ind
Ind
Ind
Ind

DIP
DIP
DIP
DIP

2-74
2-74

125

±O.007
±O.OO3
±O.003
±0.003

74dB
60dB
60dB

±(6+ 10/G)
±(3+ 5/G)
±(1 +5/G)

14
14
14

Ind
Ind
Ind

DIP
DIP
DIP

2-60
2-60
2-60

±(3+ 10/G)
±(3+ 10/G)
±(1.5 + 7.5/G)

30
30
30
30
30
30
30

Ind
Ind
Ind
Ind
Ind
Ind
Ind

DIP
DIP
DIP
DIP
DIP
DIP
DIP

2-66
2-66
2-68
2-88
2-68
. 2-68
2-68

8OO'~

Ind
Ind

To-99
'TO-99

2-64
2-64

Gain

Non-

G=100.
25"C
max

Drift
G=loo
ppm1"C

Linearity

0.15
0.15
0.15
0.15
0.15
0.15
0.15

22
22
22
22151
22151
22151
22151 .

±0.007
±0.003
±O.OO3
±0.007
±0.003
±0.003
±0.003

0.03
0.03
0.03
0.03
0.03
0.03

2213•
22131
2213•
2215l
22151
221151
125 131
125 131
125131

G=loo
max %

3630AM
3630BM
3630CM
3630SM

'-1000121
'_1000121
1-1000121

0.1
0.05
0.05
0.05

3626AP
3626BP
3626CP

5_10001.21
5_1000121
5-1000121 .

0.5
0.5
0.5

35'"
35'"
35131

±0.05
±O.04
±0.04

3629AM
3629AP
3629BM
3629BP .
3626CM
3629CP
3629SM

5-1000121
5-1000(21
5-1000121
5_1000121

45131

45'·

±0.007
±O.007
±0.004
±O.OO4
±O.OO4
±O.OO4
±0.004

106dB14•

5-1000C21
5_1000121

0.1
0.1
0.1
0.1
0.1
0.1
0.1

1VN. fixed
lVN.llxed

0.01
0.01

5
5

±O.OOll$j
±O.OO1151

90dB
l00dB

Gain set

0.05
0.02

10
10

±O.Ol
±0.005

0.05
0.02

20

10

0.05
0.05
0.02
0.02

10
10
10
10

Buffer,
Unity-Gain
Differential

3627AM
3627BM

Noninverting

PGA100AG
PGAlooBG

'_1ooo

GIII

5-1000'"

Dynamic
Response

CMR. OCto
60Hz. G=10
lkO

Accuracy

45131

45131
45131
45'"
45131

Offset
Voltage

,

106dB""

106dB'4.
106dS'4.I
106<:18 1..
106dS(4)

±(1.5+7·5IG)

±(0.75 + 5/G)
±(0.75 + 5/G)
±(1.5 + 7.5IG)

106dB"'1

30

2-74

2-74

20

800-'

NA
NA

6'"'
6'"'

5MHz
5MHz

.od
Ind

DIP
DIP

2-26
2-26

±O.007
±0.003

96dB
96dB

2(G =100)
0.4(G =100

30
30

Ind
Ind

DIP
DIP

2-34
2-34

0.004
0.004
0.004
0.004

9OdB. G = 1
SOdB. G = 1
9OdB. G = 1
SOdB.G= 1

±(3 + SO/G)
±(3 + SO/G)
±(1 +2OIG)
±(1 +201G)

40
40
40
40

Ind
Ind
Ind
Ind

DIP
DIP
DIP
DIP

2-52
2-52
2-52
2-52

PROGRAMMABLE GAIN AMPLIFIERS
Multiplexed

with4-~lt

word (2,
4.8 .... 128

Input
Instrumentatian
Amplifier
Input

PGA200AG
PGA200BG

Differential
Input

3606AG
3606AM
3606BG
3606BM

Gain set
with2-bit
word 1,10,

100.1000
Gain set
with3-bit

word 1, 2,4
8 ... 1024

PRECISION TWO-WIRE TRANSMITTER

Model
XTRlooAM
XTR100AP
XTR100BM
XTR100BP

Output Parameters

Input Parameters

Span
Untrimmed
Error
max

NonLinearity
max

Temp
Drift
ppm'llo/"C

-3%
-3%
-3%
-3%

0.01%
0.01%
0.01%
0.01%

±100
±100
±IOO
±IOO

min

Currant
Range
mA

Olf!l8t
Current
Error
!lA. max

90dB
90dB
90dB
90dB

4-20
4-20
4-20
4-20

±4
±4
±4
±4

Ollaet
Voltage
max

Off!l8t
Voltagevs
Temp max
I'V/"C

CMR
DC,

±5OpV
±5OpV
±25jJV
±25jJV

±I
±I
±0.5
±0.5

NOTES: (I) Com = Oto +70"C; Ind= -25"C to +85"C; MIL = -SS"C to +125"C.
(4) DC only. (5) Unity-gain. (6) Typical.

FS Output
. Temp
Current
Error
Range
pA,max
±20
±20
±20
±2O

(2) Sel with external resistor.

2-5

'"

Package

Page.

Ind
Ind
Ind
Ind

DIP
DIP
DIP
DIP

2-40
2-40
2-40
2-40

(3) With zero TCextemal resiator.

GLOSSARY .OF -TeRMS & DEFINITIONS
Instrumentation Am'pllfiers

COMMON"MODE INj)UT IMPEDANCE
The effective impedance (resistance in parallel with
Capacitance) between: either input of an amplifier and its
common, or ground, terminal.
COMMON-MODE REJECTION (CMR)
When both inputs of a.differential amplifier experience
the same common-mode voltage (CMV), the output
should, ideally, be unaffected. CMR is the ratio of the
common-mode input voltage change to the differential
input voltage (error Voltage) which produces the same
output change.
CMR (in dB) = 20 10glO CMV/Error Voltage
Thus a CMR. of SOdB means that I V of common-mode
voltage will cause an error of JOOI-'V (referred to inp~t).

INPUT BIAS CURRENT DRIFT
The rate of change of input bias j:urrent wit\:! temperature
or time.
INPUT GUARDING
The use of an 'input shield that is sometimes driven to
follow the voltage levelof the input.signal and, thereby, .
remove leakage and loss-inducing voltage differences
between the input signal path and surrounding stray
conduction paths.
.
INPUT OFFSET CURRENT
The difference ()f the two input bias currents in a
, differential amplifier.
INPUT OFFSET VOLTAGE
The DC input Voltage required to provide zero voltage at
the output of an amplifier when the input signal and input
bias' currents are zero.

COMMON-MODE REJECTION RATIO (CMRR)
The ratio of the differential voltage gain of an amplifier to
its common-mode voltage gain.
COMMON-MODE VOLTAGE (CMV)
That portion of an input signal.which is common to both
inputs of a differential amplifier. Mathematically it is
defined as the average of the signals at the two inputs:
CMV = e, + e2/2

INPUT PROTECTION
A means of protecting an input ofa device from damage'
due to the application of excessive input voltage.
INSTRUMENTATION AMPLIFIER
A closed-loop differential input gain block exhibiting

1=EEDBACK
The return of a portion of the output signal from a device
to the input of the device.

high input impedance and high common-mode rejection.
Its primary function is to accurately amplify the voltage
applied to its inputs.

FULL POWER FREQUENCY RESPONSE
The maximum sinllwave frequency at which a device can
supply its peak-to-peak rated output voltage and current,
without introducing significant distortion.

NONLINEARITY
The peak deviation from ,a best straightline (curve fitting
, on input-output graph) expressed as a percent of peakctopeak full scale output.

GAIN
The ratio of the output signal to the associated input .
signal of a device.

OVERLOAD RECOVERY TIME
Tile timelequiredfor the output of an amplifier to return
from saturation to linear operation, ,following the
removal of an input overdrive signal.

GAIN ERROR
The differe~ce. be~ween the actual gain of, an amplifier
and the one predicted by the ideal gain expression.

SETTLING TIME
The time required; after application of a step inP!ltsignal,
for the output voltage to settle and remain within a
specified error band around the final value.

INPUT BIAS CURRENT
The DC input current required at. each input of an
amplifier to provide zero output voltage when the input
signal and input offset voltage are zero. The specified
maximum is for each input..
.

SLEW RATE
The maximum rate of change of an output voltage when
supplying the rated output.

2-6

BURR-BROWN@

INA101

IElElI

=
c:!:

Very-High Accuracy
INSTRUMENTATION AMPLIFIER
FEATURES

APPLICATIONS

• ULTRA-lO\y VOLTAGE DRIFT - o.25JLV/oC
• LOW OFFSET VOLTAGE - 25JLV
• LOW NONLINEARITY - 0.002%
• LOW NOISE - 13nV/iVHz at 10 = 1kHz
• HIGH CMR - 106dB at 60Ifz
• HIGH INPUT IMPEDANCE - 1010n
• LOW COST

• AMPLIFICATION OF SIGNALS
FROM SOURCES SUCH AS:

Strain Gages
Thermocouples
RTDs'
• REMOTE TRANSDUCERS
• LOW LEVEL SIGNALS
• MEDICAL I,NSTRUMENTATION

DESCRIPTION
The INAIOI is a high accuracy, multistage, integrated-circuit instrumentation amplifier designed for
signal conditioning requirements where very-high
performance is desired. All circuits, including the
interconnected laser-trimmed thin-film resistors, are
integrated on a single monolithic substrate.

A m ultiam plifier design is used to provide the highest
performance and maximum versatility with monolithic construction for low cost. The input stage uses
Hurr-Brown's ultra-low drift, low noise techqology
to provide exceptional input characteristics.

OFFSET ADJUST

OFFSET AOJUST

GAIN SET 1 1 ~>-::-:~---............~
BAINSET2

4H"'::;~---~"'-";

+Vcc -VCC A2 OUTPUT

COMMON

M Package

G Package

International Airport Indllltriat Park· P.O. Box 11400· Tucson. Ariziml 85734 • Tel. (602( 746- jIll • Twx: 910-952·1111 . Cable: BBRCORP . Telex: 66-6491

2-7

SPECIFICATIONS

ELECTRICAL

At'+25°C WI'th -.
+I5VDC power supp y and'In ClrcUI't 0 fF"Igure 2 un ass 0 th elWlse not ed .
INA10l~AG

MODEL
.

.,. ~IN

MIN

.''>''''

TYP

'.

~10ICMtC.G

INA101SM/SG
MAX

MIN

TYP

MIN

MAX

'TYP
"

1000

I

Range of Garn
Gain Equation
Error From Equation, OCI1II21

G = 1+ (40k/RGI
±(0.04±0.OOOl6G
-0.02/G,

±(0.I±O.OO3G .'
-0.05/GI

2
20
22
22
±,O.002 +10'5<3,

5
100
110
110.
±,O.005+2X l05GI

MAX'·

,.

--c:c

"

'.

UNITS

V/V
V/V
%ofFS

!3ain Temp. Coefficients(3)

G
G
·G
G

= I
=10
= tOO
",IOOQ

Nonlinearity, DC (21

±io.ool
+ 1O- 5Gi

±10.C02
+ lO-5GI

2
10
II
.1)
±IO.OOI
+ lO-5G,

"

5
50
55
55
±10.002
+IO-5GI

ppm/oC
ppm/oC
ppm/oC
ppmrc
% of pop FS

.: '.

RATED OUTPUT

±IO
±5

Voltage
Current

Output Impedance

±.I2.5
±.IO
0.2

V.
mA

'.

n

INPUT OFFSET VOLTAGE

±25+200/G .

Initial Offset at +25' Clm'

±IO±IOO/G . ±25±200/G
±O.75±IO/G

':!'50±400/G'
±2±20/G

vs. Temperaturel2l

:tlO±IOO/O' ±25±200/G
±O.25±10/G

±,I+20/GI
±II +20/GI

vs. Supply
VS. Time

p.V
p.vrc
p.V/v
p.V/mo

INPUT BIAS CURRENT
Initial Bias Current
(each input)

±15

12.1

±IO

±30

-±30

±5

"

vs. Suppiy

±0.2
±O.I

Initial Offset Current (2j

±15

vs. Temperature

+0.5

vs. Temperature

.'
'"

±30

±IO

is

±30

INPUT IMPEDANCE

Differential

nA

INPUT NOISE
Input Voitage Noise
fil:, O.D1!:iz to·IOHz
Density, G = 1000
fo = 10Hz
fo = 100Hz
fo=IkHz

.'

nArC
nAN
nA
nAloe

nil pF
nil pF
V

±IO

DC to 60Hz, G = I'.,
80
96
DC to 60Hz, G = 10
DC to 6OHz,"G = 100 to 1000 106

'±20

,

1010 113
1010 113

Common-mode
.INPUT VOLTAGE RANGE
Range, Linear Response
CMR with 1kO Source Imbal.

±20

..

;

90
106
110

dB
dB
dB

,
p.V,p-p

0.8
....

18
15
13

nV/,jHz
nVl,jHz
nV/,jHz

Input Current NOise

fs = 0.01 Hz to 10Hz
Density

fo = 10Hz
fo = 100Hz
fo = 1kHz

50 ,

pA, pop

0.8
0.46
0.35

pA/y'Hz
pA/,jHz
pA/,jHz

,

DYNAMIC RESPONSE

Small Signal, ±3dB Flatness
G=I'
G=IO
G = 100
G = 1000
Small Signal, ±I% Flatness
G=I
G=IO
G=IOO
G = 1000
Full Power, G = I to .100
Slew Rate, G = I to 100'"
Settling Time (0.1%1
G=I
G=IOO
G=IOOO
Settling Time (0.01%
G=I
G=IOO
G=IOOO.

-

0.2

300
140
25
2.5

kHz
kHz
kHz
kHz

,.

kHz
kHz
kHz
Hz
kHz
Vlp.sec

20
10
I
200
6.4
0.4
30
40 '
350

40
55
470

30
50
500

45
70
650

~sec

p.sec
p.S8C
"

.
2-8

p.sec
p.sec
p.sec

ELECTRICAL
MODEL
POWER SUPPLY
Raled Vollage
Vollage Range

±20
±8.5

±5

Quiescent-

±6.7

-55

+85

+125

+125
+150

ABSOLUTE MAXIMUM RATINGS

NOTES:
1. "TYPically the tolerance of Rewlll be the major eouroe of geln error.
2. Speclfally teeted for 1883.
3. Nof Including the TCR of Re.
4. Adjueleble 10 zero at eny one geln.

±20V

Supply
Internal Power Dissipation
Input Voltage Range
Operating Temperature Range
Storage Temperature Range
Lead Temperature (soldering 10 seconds)
Output Short·Circuit Duration

600mW

±Vcc
-S5'C 10 +12S'C
-65'C to +IS0'C
+300'C
Continuous to ground

ORDERING INFORMATION
INA10l C

T

G

Basic Model Number--=:::rPerformance Grade Code
S: -55'C to +125'C
A, C: -25' C to +85' C
Package Code ~--------'
M: TO-100
G: 14-Pin Hermetic DIP

TO-l00

DIP
(GSufflx)
INA101AG
INA101CG
INA101SG
Hermellc

(M Suffix)
INA101AM
INA101CM
INA101SM

MECHANICAL
M Package

rr=

~
LA~C

LF::'1 ~ :-:.:::::=:
NOTE:

A ---

Z

F

J

..... t.-o

J

.,

Numb... may not be ma ..ed on package.

j r--r-=-~=o
INCHES

OIM
A

0
F

G
H

MIN

.370
.1335

8.51

9.40

7.75

8.51

.185

4.19

4.70

.016
.010

. 021
.040

0.41
0.25

0.53
1.02

0.25

1.02

. 010
.040
.230 BASIC
.02.
.034
.04'

.160
36° BASIC
.110
.120

M3i
f(mr
trJG~"::

MilLIMETERS
MIN
MAX

.165

.120

N

MAX

.335
.305

.029
.500
M

GPackage

Hermetic DIP

Plane

5.84 BASIC

0.71

0.86

0.74

1.14

-A

12.70
3:05'
4."
36° BASIC
2.79
3.05

l~~V

BOTTOM VIEW

2-9

Leads in true position within
0.01" (0.2Smml R at MMC at
seating plane.
Pin numbers shown for reference only. Numbers may not
be marked on package.

INCHES

. ....

DIM

MIN

••70

C

0

.015

MAX
.710
.110
. 021

MILLIMETERS
MIN
MAX
17.02
1.85
Q.3•

1.' •

18.03
4.32
0.53

F

.04•

G

.tOO8ASIC

2.'154 BASIC

H

.02•

.010

0 ....

1.78

.012
.240

0.20

3."

0.30
6.10

J

.ooe

K

.120

. 080

L

.3OQ8ASIC

M

--

10

N

.000

.080

1.52

7.82 BASIC

to
0.23

1.52

.'

PIN CONFIGURATION

,",

COMMON
-Vee

+ INPUT

OFFSET
ADJUST 2

GAIN SENSE 2
7 COMMON'

GAINSET2
A20UTPUT

+IN
Al0UTPUT

TOP VIEW
TOP VIEW

TYPICAL PERFORMANCE CURVES
At +25°,C and in circuit of Figure 2 unle~s otherwjs~ noted.
TOTAL OFFSET VOLTAGE
CMR VS SOURCE IMBALANCE

3200 ...._ _...;;D;;,R;.;,IFT....;..V.;.,S;.,G,;.;.A;,.IN;..._ _......

'~

t o.o03 .....

~

---i-----..I~-~'-f

Max

~

:i.5
15

z

Typ
0.0011-....;~-"""~~-I-,..,---''-I

"

60 .....- - i - - - - i - - - - 1 - - ' - f
60Hz ..:...DC ~ ••••

'iii
Cl

O'OO03 ...._ _....,j_ _ _ _. . . ._ _ _...
10

100
GainlVNI

1000

40~1---3~.2--~1~0--~32~--1...
00
Source Resistance Imbalance IkO>

Gain (VN{

CMR VS FREQUENCY

GAIN ERROR VS FREQUENCY

GAIN VS FREQUENCY
120
G= 1000

60

iii 40
'!!

G=l00

~"

G=1 10

20

o!

\

100

"\'
\

100

'

h%Err r"'\

lk

~

G=l

.\

I

10

"

G=10

~
I

G=ll

G= 100,1000

Balanced
Source

~

60

\.

10k

lOOk

1M'

10

Frequency IHzl
WARM-UP OAIFT VS TIME
10

>

..''"!:

8

~
0

>

~

6

0

:;

c. 4

.5.
.!:

'".."
Q)

2

.J:;

()

0

100
.1k
Frequency (HZI,

10k

G=19
0.01% ....- -....--'----t.,..-......
10
100
lk
10k
lOOk
Frequency (Hz.)
STEP RESPONSE

QUIESCENT CURRENT VS SUPPLY
±9

I

~

"~
G!,
A:"lJ

+10

\

8'

\

7

'""

'-

3

Time jMinules}

4.

5

/

±5

V

/

1\'

±10

±15

2-10

±20

'"

J

-10

Supply Voltage, (Volts)

,

o

100

200 300 400
Time (I'sec)

t--

500

600

TYPICAL,PERFORMANCE CURVES (CONT)
SETTLING TIME VS GAIN

10c0~--~~~~~~~~--.

RL = 2kll
CL = looopF

looo~-----r------~------'

~

i.3 320 J----I-----f----4

~100

.

"
E
(5

E

;::

C>

>

,!;

~

INPUT NOISE VOLTAGE
, VS FREQUENCY 100 <; GAIN <; 1000,

'OUTPUT NOISE VS GAIN
30r-----~------~----...

100

t----f---~_,_.".__HJH

10
Gain {VNI

1000
Gain {VNI

10
100
Frequency (HZI

1000

DISCUSSION OF PERFORMANCE
INSTRUMENTATION AMPLIFIERS
Instrumentation amplifiers are differential input closedloop gain blocks whose committed circuit accurately
amplifies the voltage appliec;l to their inputs. They
respond only to the difference between the two input
signals and exhibit extremely-high .input impedance,
both differentially and common-mode. Feedback networks are packaged within the amplifier module. Only
one external gain setting resistor must be added. An
,operational amplifier, on the other hand, is an open-loop,
uncommitted device that requires external networks to
close the loop. While op amps can be used to achieve the
same basic function as instrumentation ampiifiers, it is
very difficult to reach the same level of performance.
Using op amps Often leads to design trade-offs when it is
necessary to amplify low level signals in the presence of '
common-mode voltages while maintaining high input
impedances. Figure I shows a simplified model of an
instrumentation amplifier that eliminates most of the
problems.

ID=I.+'b
II =Glez '111= BId
G(IIz + 1,112 GICM
'II = ---ciiiiI = CMRR

heM
'o=GItI+ CMRR

THE INA101
Simplified schematics of the INAIOI are shown on the
first page. I t is a three-amplifier device which provides all
the desirable characteristics of a premium performance
instrumentation amplifier. I n addition, it has features not
normally found in integrated circuit instrumentation
amplifiers.
The input section (AI and A2) incorporates high performance, low drift amplifier circuitry. The amplifiers are
connected in the noninverting configuration to provide
the high input impedance (1O IO n) desirable in the instrumentation amplifier function. The offset voltage and
offset voltage versus temperature is low due to the
monolithic design and improved even further by the
state-of-the-art laser-trimming techniques.
The output section (A3) is connected in a unity-gain
difference amplifier configuration, A critical part of this
stage is the matching of the four IOkn resistors which
provide the difference function. These resistors must be
initially well matched and the matching must be maintained over temperature and time in order to retain
excellent common-mode rejection. (The 106dB minimum
at 60Hz for gains greater than IOOV i V is a significant
improvement compared to most other integrated circuit
instrumentation amplifiers.)
All of the internal resistors are compatible thin-film
nichrome formed with the integrated circuit. The critical
resistors are laser-trimmed to provide the desired high
gain accuracy and common-mode rejection. Nichrome'
ensures . long-term stability of trimmed resistors and
simultaneous achievement of excellent TCR and TCR
tracking. This provides gain accuracy and commonmode rejection when the INAIOI is operated over wide
temperature ranges.
USING THE INA101
Fi.gure 2 shows the simplest configuration ofthe IN A 10 I.
The gain is set by the external resistor, RG with a gain
equation ofG= I +(40KI RG). The reference and TCR of
RG contribute directly to the gain accuracy and drift.

. For INAIOI G=, + O/RS
where RG II the gain Ilttlng rellBlor.

FIGURE I. Model of an Instrumentation Amplifier.

2-11

F~r gains greater than unity. resistor Rd, is ,eopnected
externally between pins I and 4. At high gains where the
value orR" becomes ,small. additional resistance (i.e ..
relays. sockets) inthe Ro circuit will contribute to a gain
error. Care should be taken to minimize this effect .
. The optional offset null capability is shown in Figure 2.
The adjustment affects only the input stage component of
. the offs,et voltage. Thus. the null condition will be
disturbed when the gain is changed. Also. the input drift
will be affected by approximately 0.31 ~.iY /"C per 100101 V
of input offset,voltage that is trimmed; Therefore, care
should be taken when considering use of the control for
removal of other sources of offset. Output offsetting can
be accomplished in Figure '3 by applying a voltage to
Common (pin 7) through a buffer amplifier. This limits
the resistance in series with pin 7 to minimize CMR error.
Resistance above O.l!l will cause the common-m'ode
rejection to fall below I06dB. Be certain to keep this
resistance low.

It is important to not exceed the input amplifiers'
dynamic range. The amplified differential input signal
and its associated common-mode voltage should not
cause the output of Al or A, to exceed approximately
±IOV or nonlinear operation will result.
'1

Thla ~In:ull may be und la a repllcllI1IIDt
lor Ibe single poI8ntiolllll8r. tt will ,adlult
: onlll.Ad leava drill unchanged.
'
I

+VCC

I

I
L

_______ ,

+VCC
,...----

OPTIONAL 1
OFFSET I 0.3 .. 1
ADJUST 'I
1M'
:

I

I

,

:~",

:0
CD "'- __
L...; _____

:',,',<>PTIONALOFFSETADJUSTMENTPROCEDURE
, It is frequeritl~ de~irabl~ to nul; the input compo~e~t of
, offset (Figure 2) and occasionally fhat of the output
(Figure 3). The quality of the potentiometer will affect the

+15VDC

, 1~11ODkO
RI

EXTERNAL
AMPLIFIER

R3

~ Ikll
~ R2 ·15VDC

FIGURE 3. Optional Output Offset Nulling or
Offsetting Using External Amplifier (Low
Impedance to Pin 7).
results. therefore, choose one with good temperature and
mechanical-resistance stability. The procedure is as'
follows:
I. Set EI -=Ei = OV (be sure a good ground return path
exists'to the input);
2. Set the gain to the desired value by choosing R".
3. Adjust to lOOk!} potentiometer in Figure 2 until the
output reads OV ±lmV or desired setting. Note that
the offset will change when the gain is changed. If the
'Output component of offset is to be removed or if it.is
desired t~ establish an intentional offset, adjust the
lOOk!} potentiometer in Figure 3 until the output
, readsOV '±I mV or desired setting. Note that the offset'
will not change with gain, but be sure to use a stable
extermil amplifier with good DC characteristics. The
range of adjustment is ±15mV as shown. For larger
ranges change the ratio of RI to R2.

TYPICAL ApPLICATIONS
Many applications of instrumentation amplifiers involve
the amplification of low level differential signals from
bridges and transd ucers s!Jch a$ strain gages, thermocouples" and KID's. Some of the ilJlPortant parameters
include common-mode rejection (differential cancellation
of COin'mon·mode offset and noise, see Figure I), input
impedance, offset voltage and drift, gain accuracy.
linearity, and noise. The INAlOI accomplishes all of
these with high precision.
Figures 4 through 9 show some typical applications
circuits.

FIGURE 2. Basic Circuit Connection for the INAJOI
Including Optional Input Offset Null
Potentiometer.

BASIC CIRCUIT CONNECTION
The basic circuit connection for the INAJOI is shown in
Figure 2. The output voltage .is a function of the
differential input voltage times the gain.

2-12

+Vcc
V
R A__R
TRANSDUCER
ORSENSDR-El RESISTANCE
BRIDGE
. E2
i'R

,

,..~---,......

I

r

\

I

",E'N I
I
I

1

\

I

,

I

\

s

-

: RS~

c:
~

I
I

I

\

,

I

I
I I
I I
I

\

I

I
-~

SHIE~

FIGURE4. Amplification ofa Differential Voltage from a Resistance Bridge.
+vcc

_oc(j

NOllllllOHz HUMI

, .... ---,.......
I

.\

I

\

,

I

I
I I

\

I

I

I
I I

AllALDl818NAL

I

\

\

I

I

I

TRANSfORMER
NOISE 110Hz HUMI

~

°Galn IInll will minimize
gain error dUlID addilional
reallllnca In IlI8 RS Glreuh.

FIGURE 5. Amplification of a Transformer Coupled Analog Signal.

FIGURE 6. Output Offsetting Used to Introduce a DC Voltage for Use with a Voltage-to-Frequency Converter.

2-13

"+illvoc ,from 1IOI18on pow.r supply)

FIGURE 7. ECG Amplifier or Recorder Preamp for Biological Signals.

'O~S 1I0T REQUIRE

EXTERNAL ISOLATION POWER SUPPLY

ISOLATION AMPLIFIER

EOUT

+l5VOC
INPUT
COMMON

ISOLATIOII POWER SUPPLY

+15VOC

OUTPUT
COMMON

722

FIGURE 8. Precisionlsolatedlnstrumentation Amplifier.
CHANNEL SELECT
GAIN SELECT
CONTROL LOGIC

CP

fr

EOUT

'VREF AND GROUND
MAYBE USED FOR
ERROR CORRECTION

FIGURE 9. Multiple Channel Precision Instrumentation Amplifi"r.

2-14

BURR-BROWN®

INA104

IElElI

Very-High Accuracy
INSTRUMENTATION AMPLIFIER
FEATURES

APPLICATIONS

• VERSATILE FOUR-OP AMP DESIGN
• ULTRA-LOW VOLTAGE DRIFT - O,25/lV/oC, max
• LOW OFFSET VOLTAGE - 25/lV, max
• LOW NO"L1NEARITY - 0.002%, max
• LOW NOISE - 13nV/.Jjfz" at 10 = 1kHz
• HIGH CMR - 106118 at 60Hz, min
• HIGH INPUT IMPEDANCE - 1010n
• LOW COST

• AMPLIFICATION OF SIGNALS
FROM SOURCES SUCH AS:
Strain Gages

DESCRIPTION
The INAI04 is a high accuracy; multistage, integrated-circuit instrumentation amplifier designed for
signal comfitioning requirements where very-high'
performance is desired.
A multiamplifier, monolithic design, which uses
Burr-Brown's ultra-low drift, low noise technology,
provides the highest performance with maximum
versatility at the lowest cost and this makes the
INAI04 ideal for even high volume applications.

______________________

CMY SENSE

RTDs
• REMOTE TRANSDUCER AMPLIFIER
• LOW LEVEL SIGNAL CONDITIONER
• MEDICAL INSTRUMENTATION

Burr-Brown's compatible thin-film resistors and
state-of-the-art wafer level laser-trimming techniques
are used for minimizing offset voltage and temperature drift. This advanced technique also maximized
common-mode rejection and gain accuracy.
The INAI04 also contains a fourth operational
amplifier, specified separately, which can conveniently be used for some important applications such
as single capacitor active low-pass filtering, easy
output level shifting, Common-mode voltage active:
guard drive, and increased gain (x 10,000 and greater).

~~~!~l

A4
SUMMING
JUNCTION
llItO
LAI''''-+-_''''''~-(II FEEDBACK
I RESISTOR

GAIN
GAIN SENSE

Thermocouples

100en
4} - - - - - - - \

10

GAIN·
GAIN SENSE

I

I .....- - - 1

5kO

A4
OUTPUT

I
I

I
I

I

---@----@---B -------OFF~ ADJUST
+Vce
NOTE: +111 AND -IN ARE WITH RESPECT
OUTPUT.
IF A. IS USED INVERTING. +IN AIID -IN ARE REVERSED.

TO"

'Yee

COMMON

7 ________

J

A4· NONINVERTING INPUT

International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734 . Tel. (602) 746-1111 . Twx: 9111-952·1111 • Cable: BBReORp· Telex: 66-6491

SPECIFICATIONS
ELECTRICAL
At TA = +2SOC with ±15VDC power ~upply and In circuit of Floure 1 unless otherwise noted .

.L
,;i6;i\> ..

..•. .' Range of Gain

G'= 1 + 14OklRoi
±10.08 - O.05/GI

Gain Equation

. Error From Equation, DC(1)
Gain Temp. Coefficient(2)
G=l
G=10
0=100
G= 1000
Nonlinearity, DC

Output 'Impedance

UNITS

:...
V/V
%'Of FS

±10.15-0,i/GI

10
11
11
±IO.OOI
+10-501

11.0

+11.5, ":12.5"
+11.5, -12:5
0.2

1

VN

100

±10.002 + I;r;GI

±10
±5

:iJ'.",:"'!:>

5

2
20
22
22

RATED OUTPUT
Current

MIN

,c 'INl!7A!lMEI\It"tIONAMPLI~ER

':,;,,., 'GAIN'

Voltage

·1

INA104AM/HP.
TVP
" .. MAX

. MIN

110
±10.OO5 + 2 x 10-5GI

±IO.OOI
+ 10""G1

±10.002
+10-5GI

50
~

55
±(Q.002
+10-5GI

b"

ppmfOC
ppmfOC
ppmfOC
ppmfOC
%01 pop FS

V
mA

n

INPUT OFF.SET VOLTAGE
Initial Offset at +25°CI31

'I

±10 ±IOO1G

±5O±400/G

±25.±200/G

±25 ±2OO/G
±O,75 ±10/G· '

±2±20/G

vs Temperature
v.Supply

I..

ysTime

"

±10 ±100/G

,

±25 ±2OO/G
±O.25 ±10/G

~V
~VfOC

~VN

±(1 + 50/GI
±ll+20/GI

~Vlmo

, ,

INPUT 81AS CURRENT
Initial Bias Current

±3Q

±15

±io

±2O

±5

nA

leach input I

vs Temperature

nAlOC

±0:2'
±0.1
±5

vsSupply
In itlal Offset Current

I

±2

±30

±2

.' ±O.5

vs Temperature

I

±2O

nAIV
nA

nAlOC

INPUT IMPEDANCE'
1010 113.
1010 1(:1'

Differential

Common-mode

011
011

•

INPUT VOLTAGE RANGE
Range, Linear Response
±10
CMF! with lk.O Source Imbal.
DC to 80Hz. G = 1
80
DCt060Hz,G=10
'96
DC to 80Hz, G = 100 to 1000 106

pF
pF

v
90
106

dB
dB
dB

I.

.-

110

INPUT NOISE
Input Voltage Noise
ia = O.IHz tO,10Hz
DenSity, G'= 1000
fo= 10Hz
fo= 100Hz
fo = 1kHz
Input Current Noise
fa = 0.01 Hz to 10Hi
Density
10= 10Hz
fo= 100Hz
fo = 1kHz

0.8

~V:p-p

18

nV/v'Hi

nV/v'Hi
nV/,;tHZ

15
13

....

50

pA, pop

0.8

pAlVHZ
pAlVHZ

0.46."
0..35

pAly'Ri

DYNAMIC RESPONSE
Small Signal, ±3dB Flatne.••

G=1
13=10
G=I00
G= 1000
Small Signal, ±1% Flatnes.
G=1
G=10
G=I00
G= 1000
Full Power, G = 1 - 100
Slew Rate, G = 1 - 100
Sel\llng Time (0.1%1
G=1
G=100
G= 1000
Settling Time (0.01%1
G=1
G=I00
,G.= 1000

kHz '
kHz
kHz
kHz

300

'., 140
25
2.5
"20

kHZ
kHz
kHz
Hz
kHz

10
1

200.
0.2

6.4
0.4

VI~sec

40 .

~aec

55
470
'30
50
500

~sec

~c

45

~sec

70
650

~aec
0'

2-16

usee

ELECTRICAL (CONT)
IMINI

~ GAIN.VO = ±10(1
Rated Load RL '" 2kO
RL" 10kll

115
125

10

+13. -14.5
+13. -14.5
7.5
2

5

Current
Output Impedance

-Load capacitance (unity~gain
inverting)
Short Circuit Current

0.35

1

INPUT OFFSET VOLTAGE
Initial, TA '= +25°C
YS TAm

TYP

I~~

RATED OUTPUT
Voltage at RL = 2kll
RL = lOkI!

FREQUENCY ResPONSE
Unity Gain, Small Signal
Full Power
Slew Rate
Settling Time (unity gain)
0.1%
0.01%

I

I

I

I MODEL

".

INPUT alAS CURRENT
INPUT IMPEDANCE
Differential

MAX
IMINI
OUTPUT ...."i·

TYP

I

MAX

IMINI

TYP

I
I

UNITS'

.A.
dB
dB

.

V
V
mA
kll

2000
10

pF
mA

1
9
0.55

MHz
kHz
V/~sec

37

,",sec

40

.usee

:tl
+5

:t2

+55

+150

.-';

mV
/J.V/oC
nA
kll

50<1
100

Common~Mode

MAX

Mil

RESISTORS. 10kO
0.5

Accuracy
Drifl
Ratio Match
Dri!t

30
0.06
5

INPUT VOLTAGE NOISE
F. = O.IHz to 10Hz
Density
fo = 10Hz
fo = 100Hz
fo = 1kHz
POWER SUPPLY. TOTAL
Rated VOltage
Voltage Range

5
50
0.12

.'

1.5

~V.p·p

35

nVJHz
nVyHZ
nVJHz

33
32

V
V
mA

±15
±5

Current, Quiescent

%
ppm/oC
%
ppmfOC

±S.l

±20
±9.6

TEMPERATURE RANGE

Specification
INA104HP/JP/KP
INA104AM/BM/CM
INA104SM
Operation
INA104HP/JP/KP
INA104AM/BM/CM/SM
Storage
INA104HP/JP/KP
INA104AM/BM/CM/SM
6J_C
6J-A

°C
°C

+70
+85
+125

0
-25
-55

-40

'C

·C
·C

+85
+85

-55
-40
-65

'C

.+85
+150

'C
OOC/W
OOC/W

lIS
350

'Specifications same as for INA104HP.
NOTES:
1. Typically the tolerance of RG will be the major source of gain error. 2. Not including the TeA of RG. 3. Adjustable to zero at anyone gain.

2-17

IIIC

!:

MECHANICAL

I

MET'AL HERMETIC DIP'

.",,'

I·, '

PLASTI.C DIP
M LIMHE"S
MIN
MA~L
21\'IllI

O'M

I';

'214.3.

M"

'''90

'co

NICN..
MI'Le''''',"'
210
• •3
533'
S10', ~

o:h

n

25C

~
0
SQ.

4

".'"c

~ ±9

1\
\

E
~

<'3 ±8
E

i\.

0

3

"'"

U

,~"

"' """-

6
9
Time (Minutesi

o ±7

12

-

V

±6

SETILING TIME VS GAIN

OUTPUT NOISE VS GAIN

~ 320

"E
;::
:i'"

~

Gl,

,~

10

1000

o

±20

I 00

~OO

300

400

500

600

Time (lotseCj

INPUT NOISE VOLTAGE
VS FREQUENCY [100 5 GAIN 510001
1000

5°ot-::::=E==t:===1
1=

i

50~~;::1======:t======:j

o

10

t---~~::::J
I----:':"',-

.:
0

100
Gain [VNJ

"- i'o-..

~

~

0

10

1\

"
~

0-5

~

S
32

;:; 0

i

>-

z

g

~ 1001----1----+----1

S"
'"
'0
100

/cf=loJ,

~ +5

~

~

,,:
§ 20

'OOk

STEP RESPONSE

-10

30
RL =2kn
CL = looopF

:g

V

v

±5
±10
±15
Supply Voltage [Volts 1

15

1000

u

lk
10k
Frequency I HZJ

+10

2

.:

10k

±10

i

~

Ik
100
Frequency {Hz)

QUIESCENT CURRENT VS SUPPLY

10
~

~

60

FreQuency (Hz)

>

III

"

\

I
10

"ii

\

\

o

III

\~

G=',0

20

"-f'\.:

G-10
100

~

GAIN ERROR VS FREQUENCY

G-l00.1000

1

DISCUSSION
OF PERFORMANCE
. INSTRUMENTATION AMPLIFIERS
Instrumentation amplifiers are closed~loop gain blocks
whose committed Circuitry accurately amplifies the
voltage applied to their inputs. They respond only to the
difference between the two input signals and exhibit
extremely-high input impedance, both differentially and
common-mode. Feedback networks are packaged within
the amplifier module. Only one external gain setting
resistor must be added. An operational amplifier, on the
other hand, is an open-loop, uncommitted device that
requires external networks to close the loop. While
operational amplifiers can be used to achieve the same
basic function as instrumentation amplifiers, it is difficult

GainlVNJ

10
100
Frequency [Hz)

1000

to reach the same level of performance. Using operational
amplifiers often leads to design trade-offs when it is
necessary to am plify low level signals in the presence of
common-moc;le voltages while maintaining high input
impedances .

THE INA104
A simplified schematic o'the INAl04 is shown on the
first page of this data sheet. It is a three-amplifier device
which provides all the desirable characteristics of a
premium performance instrumentation amplifier. In ad~
dition', it has features nc;>t normally found on integrated
.circuit instrumentation amplifiers.
The input section (AI and A2) incorporates high performance,low drift amplifier circuitry. The amplifiers are
connected in the noninverting configuration to provide

2-19

the /tigh input impedimce (JOIOO) desirable in the instrumentation a,mplifier fqnction. The offset voltage and
offset..voltage . versus temperature is low due to the
monolithic design and improved even further by the
state-of~the-art laser-trimming techniques.
•

OPTiONAl.OFFSET ADJUSTMENT PR0C:;:EDURE
It is freq'ilently desirable tonull the input component of
offset (Figure I) and oC(;lisionally that of the output
.

The output section (A3) is conqected in a unity-gain
difference amplifier configuration. A critical part of this
stage is the matching of the four 10k!! resistors which
provide the difference function. These resistors must be
initially well matched and the matching must be main.tained over temperature and time in order to retain'
excellent common-mode rejection. (The I06dB minimum
at 60Hz for gains greater than lOOY IY is a significant
improvement compared to most other integrated circuit
instrumentation amplifiers.)

-Vee

I

Thlulrcult miy.be 0.111 u I1Ipl."lnllar.
the Ilngl. pDl8nllom8llr.lt wlllidjuat allllt
I .nd IIIVI drill unchl~lII.

I

.

I _ _ _ _ _ _ _ .,
• 1...

I

I

+Vee

I

I
I
I

:~
: 18

15

:L _________ '

All of the internal r~sistors are compatible thin-film
nichrome formed with the integrated circuit~ The critical
resistors are laser-trimmed to provide the desired high
gain accuracy and common~mode rejection. Nichrome
ensures long·term stability of trimmed resistors and
. simultaneous achievement of excellent TCR and TCR
tracking. This "provides gain accuracy and commonmode rejection when the INAI04 is operated over wide
temperature ranges.

8

foUT

The fourth op-amp (A4) of the INA 104 adds a great deal
of versatility and convenience to the amplifier. Its use
allows easy implementation of active low-pass filtering,
•. '::_--"':_-c,.

_ u _ _ _ ......... ouu........

6uu.I lS,",U,",lAL1VU.

lUC

pin "connections make the use of this stage optional and
the "speCifications appear separately in the tabje of
Electrical Specifications.
USIN~

THE INA104

Figure I shows the simplest configuration of the IN Al 04.
The gain is set by the external resistor, Ra, with a.gain
equation ofG = I + (40KI Ra). The reference and TCR of
Racontribute directly to the gain acCuracy and drift.
For gains greater than unity, resistor Ra is connected
externally between pins 5 and 14. At high gains where the
value of RG becomes small, additional resistance (i.e.,
relays, sockets) in the RG circuit will contribute to a gain
error. Care should be taken to. minimi.ze this effect.
However, this error can be virtually eliminated with the
INA 104 by using the ,gain sense circuit connection.
Pins 1,5, 14, and 18 are accessible so that a four-terminal
connection can be made to R,;. (Pins I and 18 are the
voltage sense terminals since no signal current flows into
the operational amplifiers' inputs.) This may be useful at
high gains where the value of Ra becomes smaiL
The optional offset adjust capability is shown in Figure
I. The adjustment affects only the input stage component
of the offset voltage. Thus, the null condition will be
disturb.ed (if input offset is not adjusted to zero) when
the gain is changed. Also, the input drift will be.affected
by appro~imately O.31IlVjOC per lOOIlV of input offset
voltage that is trimmed. Therefore, care should be taken
when considering use of the control' for removal of .other
sources of offset.,

V

I~F-'

TANTALUM~

·CoMaci plii 7 to CommUII
IIId pin 10 to pin 11 whln Inllrn.'
Amp A4 '. not uslll.

FIGURE I. Basic Circuit Connection for the INAI04
Including Optional Input Offset Null
Potentiometer.
(Figure 2). The quality of the potentiometer will affect the
results, therefore, choose one with good temperature and
mechanical-resistance stability. The procedure is as
follows: .
1. Set EI = E2 = OY (be sure a good ground return path
exists to the input).
"
2. Se~ the 'gain to the desired value (greater than I) by
choosing Ra .
3. Adjust the lOOkO potentiometer in Figil(e I until the
output reads OY ±l mY or desired setting. Note that
the offset will change when the gain is changed. If the
output component of offset is to be removed or if it is
desired to establish all intentional offset, adjust the
IOOkO potentiometer in Fig\lre 2 until the output
reads.OY ±I mY or desired setting. Note that the offset
will not change with gain, but be sure to use a stable
amplifier with good DC characteristics. The range of
adjustment "is ±15mV as shown. For larger ranges
change -the ratio of RI to R •. The op amp is used to
maintain a low resista,nce «0.10) from pin 6 to
Common to avoid CMR degradation.

BASIC CIRC.uIT CONNECTION
The basic circuit connection for the INAI04 is shown in
Figure I. The output voltage is a function of the
differential input voltage times the gain.

2-20 .

-VC C

-VCC

g

:c

10

EOUT

EOUT =IE I . E2111 - 14IIIt/ROlllRF" IIItII

",

REFERENCE
·Vee

R2

Ikn

'NOTE: A4 1nVlrll the output 01 dlalnotrumanllUon Amplllior.
pin Bto pin 10. Thareloro theaquaUon for foUT thowl
EI • E21nstlld 01 E2' EI'

·15VOC

• ~.INTERNAl TO THE INAID4. EXTERNAL AMP
IOPA27 DR EQUIV.I MAY ALSO BE USED.

FIGURE 3. Additional Gain From Output Stage.
FIGURE 2. Optional Output Offset NuHing or
Offsetting Using an Amplifier(Lowlmpedance toPin 6).
with most other IC instrumentation amplifiers as shown
in Figure 4. The use of the extra internal op amp. A•.
means that CM R ofthe instrument amp is not disturbed.
and that a convenient value of variable resistor can be
used. The circuit shown in Figure 2 can also be used to
achieve the desired offsetting by scaling the resistors R,
and R,. A low impedance path from pin 6 to Common
should be provided to achieve the high CM R specified.
Resistance above 0.10 will cause the CM R 10 fall below
106dB.

Figure I does not include additional internal op amp A•.
Power supply bypassing with a I/-IF tantalum capacitor
or equivalent is always recommended.
I n applications which do not use the fourth internal
amplifier (A. - pins 7. 9. 10. II. and 12). pin 7 should be
corinected to Common and pins 10 and II should be
connected together. This will prevent the output of A.
from saturating("locking-up") and affecting the offset of
the instrumentation amplifier. A,. A,. and A).

TYPICAL APPLICATIONS
Many applications of iristrumentation amplifiers involve
the amplification of low-level differential signals from
bridges and transducer~ such as strain gages: thermocouples. and RTD·s. Some of the important parameters
include common-mode rejection (differential cancellation
of common-mode offset and noise). input impedance.
offset voltage and drift. gain accuracy. linearity. and
noise. The INAI04 accomplishes all of these with high
precision.

10

EOUT

Figures 3 through 13 show some typical applications
circuits.
Figure 3 shows how the output stage may be used to
provide additional gain. If gains greater than IOOOV; V
(10.000 up to 100.000 and greater) are desired it is better
to place some gain in the output amplifier rather than the
input stage dueto the low values of RG required (R(; <
400 for (I + 40kj RG ) > 1000). Note. however. that
accuracy can degrade due to very-high amplification of
offset, drift. and noise errors.

·Vcc~+Vcc

R

R= a convenient valul
1

ill
\~

.. "
CHAN~.EL,TO-CHANNEL
,CROSStALIS VS FREQUENCY'

INPUT NOIS,E
cuRRENTVSFREQUENCY

INPUT NOISE
1000 r-_T"V..
O..
LT..;ATG;.E;.V.;.S,...FR..,;E;.Q;;;U;.;E;..N;.;C.,Y_..,

1/'

I---I'-:--t-+-:-+---t---I

10

&"

.5

lOOk 1M

,10

c~

c

(.)

~
0

t;

"
,...

:: 1.2

iii

'is'

II:

5

60

~ 1.0

Q.
::>

rn 40

«i

a;

~

z

20

~~O-~--~lk~~I~O~k~I~OO~k~~~~

~ -1 125

7"--

a 100 - >

~
5

~

i

-

75-i--

r--l·---I

+ .. - - .~.--

50t---~~~--~---+--~--~
25 • / ' "

«
§.

+25

+45

+65

OUTPUT VOLTAGE
VS OUTPUT CURRENT

30

-f
~

o
5
g-

:s

~

225
150
75

(.)

o

.-

/

300

--

V

t

1.3

--~--

TA

..

I

)

,

Vee '= .±1 BVDC

=25°C to TA =B5°C
Air Environment ' --

(---

--

Vee;" ±15VDC

_-

.. ..

~

I
2
3
4
5
Time From Heal Application (min I

5

18

Vee

L±~vdc

1J

o

6

QUIESCENT SUPPLY
CURRENT VS TEMPERATURE

r
2

-

.

-

1._

I

t...-

I

J

.

I

I

4
6
8
10
Output Current (mAl

.~

~

1.1

~.

1:,1.0
Q.

i '·

0

Q.

/

i'-.... i'o..

",Digital.

0.9

.11: 0.9

0.8

0.8

........

Anallog

0.7
5

10
15
Supply Voltage (±Vee)

0.7
-35

/
/"

) .......... --.. .

Qi

12

ANALOG INPUT
OVERVOLTAGE CHARACTERISTICS

1.2

~ 1.1

+85

(OC)

"

::>

,~

+5

Temperature

.. 375

1.2

C

'"
~

V

. . .v

:;

ANALOG SUPPLY CURRENT
VS SUPPLY VOLTAGE

(.)

rn::>

-15

THERMAL RESPONSETIMEOF INPUT
OFFSET VOLTAGE fROM HEAT APPLICATION

Time From Power Turn-on (min)

1.3

1
0.00~5

\

400

."

""

1

20

V

y

I

10
15
Supply Vollage 1.±Veel

5

f-. ·-f--f---+--I ~

B 0"-~2--+4---.~6--~8-~'0~~'2
I

0

1/

0.4

STABILIZATION. TIME OF INPUT OFFSET
VOLTAGE FROM POWER TURN-ON

1~r-~~~---r--~--~-'

V

1M

INPUT BIAS CURRENT
VS TEMPERATURE

1000

.L

O. 6

Frequency (Hz I

~

/

~ 0.8
§

Q.

lOOk

,

1.4

"

80

100
Ik
f:reqlJency(Hz)

I~

lOOk

INPUT BIAS CURRENT
VS SUPPLY~OLTAGE

1.6

iii 100

100
lk
10k
Frequency (Hz)

V

V

V

/
/

-15

+5

+25

+45

Temperature (OCi-.

2-30

+65

+65

oIS

18

212427303336
Analog Input Overvollage (±VIN)

DISCUSSION OF
PERFORMANCE
The PGAIOO is ~'self-contained programmable-gain
amplifier whose gain can' be changed in 8 binarily
weighted steps from I to 128 or as scaled externally
through the gain scale/ adjust pin. The gain control is
accomplished by the gain switch (break-before-make)
whose position is detllrmined by the 3-bit TTL addtess,
A" A., and As. When selected, I of8 positions connects
the thin-film resistor network to the feedback loop of the
op amp. This establishes the desired gain. (See Installation and Operating Instructions for gain scaling.)
Similarly, the 8 analog input channels are switched by the
input multiplexer (break-before-make) whose position is
determined by the 3-bit TTL address, Ao. A" and A2.
Gain and channel selection appear in Table \. 64-channel/
~ain combinations are possible.

GAIN SELECT

rr

r
A4

Aa

I

-+

A2

8

:c
CD

I

ICL.

SELECT

AD~

r-

_DISABLEDU
CE ENABLER

CP

The digital inputs are latched by the positive transition of
the clock pulse. pin 18. when the clock enable. pin 19. is
low. The relative set up and holding times specified in the
Electrical Specifications are shown in Figure I. The
·internallatch is similar to the industry standard 74LS378.
Figure 2 shows a timing diagram for selected addresses
indicating: the enable function. changing channel and
gain. changing channell constant gain, and constant
channell changing gain.

PosITIVE
EDGE
TRIBGER

,,

,,

,,
,

,,
,

CHANNEL CHOSEN I",

INo
,

INI
,

1~7
I

I

GAil CHOSEN G~ I

G~ I

G~2

G~2

G='128

,,

,,

,,

IN7

FIGURE 2. Timing Diagram for Selected Addresses.

INSTALLATION AND
OPERATING INSTRUCTIONS

TABLE I. Gain and Channt"l Select Truth Table.

POWER SUPPLY AND SIGNAL CONNECTIONS
GAIN SELECT
A.
As
A3

GAIN
1
2

0
0
0
0

0
0

0

1
1

0

4

1

1
1
1
1

0
0

0

1
1

0

8
16
32
64
128

1

1
1

CHANNEL SELECT
Al
A2
Ao

CHANNEL

0
0
0
0

0
0

0

1
1

0
1

IN~

1
1
1
1

0
0

0

1
1

0

IN4
IN5
IN6
IN7

1

1
1

INO
IN1
.IN2

DATA
ADDRESS

CP

FIGURE 3. Basic Power Supply, Ground, and
Signal Connections.
Figure 3 shows the proper analog and digital power
supply connections. The supplies should be decoupJed
with I",F tantalum and l()()()pF ceramic capacitors as
close to the amplifier as possible. To avoid gain errors
connect grounds as indicated being sure to minimize
ground resistance. Note that a resistance of greater than

FIGURE I. Data Address and Clock Enable Setup and
Hold Times.
.

2-31

.0.0050 in series with the analog common will degrade the
. specified gainacc!lracy. IMPORTANT: Normally the
. digital ground is brought in from the digital power supply
on. a separate line. However, the analog a,!d digital
commons must be.connected together soniewhere in the
system.

128

32

!
'0

2

I

'

. ,

/;'
,

v. ,'

,V ,
--

on

V,
,

,0'

,

,

,

IIAlNAOJUST -"--MOVES LINE

Ai SHr-

j?~
I.
'

000 001 010

.100. 101

DIg1t.llnpUl (Air A4• Aa)

0

-

110

III

FIGURE 5. Effect of Gain Adjustment.
gain. If RJ is made smaller,output offsetting can be
accomplished. This can be used to introduce an intentional DC voltage at the output, The external amplifier
used will add to the input noise, therefore, use one with a
noise level of at least three times lower than that specified
.
for the PGA 10.0.'
LAYOUT CONSIDERATIONS
Proper attention to layout is necessary to achieve. the
specified performance of the PGAI.o.o. Major goals are to
reduce crosstalk, noise pickup, noise coupled from the
power supply, and gain errors.
.,

+5YDC

RI

r1!1rm-'~1 OCIcn

TeR
.. IOOppm/'1:

IMn
R3

"~~

8
4

'r

'\':, :%

s
!! III

OPTIONAL GAI.N SCALE/ADJUST
The gain scale/ adjust pin is shown in Figure 4. When no
connection is made, gains appear as in Table I. At least
two functions can be performed. First, the gain range can
be scaled to gains ot.her than I. to 128, for example, I to
10.0 or I to 1024. Gain steps, however, retain binary
weighting, Some examples are: (I, I, 2, 4, 8, 16, 32, 64
with pins II and 12 cQ,nnected together), (I, 1.5625,3.125,
6.25,12.5,25,5.0,1.0.0), (1,12.5,25,5.0,100,200,400,8.0.0),
and (I, 16, 32, 64, 128, 256,,512, (024). Scaling is
accomplished by using a potentiometer, RI, shown in
Figure 4. Be certain to use a potentiometer of good
mechanical and thermal stability. Additional gain drift
with temperature should be minimal since it depends on
the thermal tracking of the resistance ratio, RA to RH, set
by the potentiometer.

RA

"

:

'OElt'"

84

" .

"

Be certain to separate analog and digital mns to avoid
coupling of digital transients. To reduce gain errors,
connect analog grounds with a ground plane or a low
resistance star configuration as shown in Figure 3.
Analog and digitaicOinmo~s ~ beconnected at some
point in the system to insure proper operation.
GAIN INACCURACY AND NONLINEARITY
As shown in Figure 3, connect pins 5 and 211 directly
together at the unit and use pin 2.0 as the primary analog
common. Ground resistance in series with pin 2.0 also
, appears in series with the internal gain-setting resistors
and will decrease the magnitude of all gains except unity.
The resulting accuracy error varies nonlinearly with the
gain selected and therefore cannot be externally adjusted·
to zero for more than one gain at a time. Gain linearity is
not affected by external ground 'resistance (see Performance Curves.)

RZ

OFFSE't
R4 ADJUST

Iko 511cn
·15VOC

FIGURE 4. External Gain and Offset Adjustment.

Secon~, the. gain inaccuracy,' remaining after laser trimming at the fact.ory, can be adjusted to zero at any gain
other than Ilnity.· To improve resolution and limit
adjustment range, a resistor may be added in series with
the wiper of the potentiometer and pin 12. This' will,
however, increase gain drift. Figure 5 shows the effect of
gain adjustment. RI does n61 affect gain linearity.
OPTIONAL OFFSET ADJUSTMENT
Figure 4 also iilustiates a technique for offset adjustment.
This adjustment has no effect at unity gain .. R2 will trim
the offset to zero and have neglible effect on the gain
accuracy. For best results, trim the offset at the highest

CROSSTALK
Crosstalk is the amount of signal feedthrough from all
OFF channels that'appears at the output of the input
multiplexer. It is expressed as a percent of the input signal
applied to all OFF channels. For example, the .0 ..0.03%
specification indicates that .o.6mY, p-p, out ofa 2.oy, p-p,
I kHz sine wave (applied to 7 OFF channels) will appear
at the noninverting input of the internal op amp. Note
that crosstalk increases with high frequencies due to the
capacitive coupling between ON and OFF channels. It
also increases with greater source resiStance. However,
because both' the input signal and crosstalk noise are
amplified equally, the resulting output signal-to-noise
0

2-32

ratio is independent of gain. Unused input channels
should be g"rounded in order to reduce crosstalk and
extraneous noise pickup. (See Performance Curves.)

applications of the PGAIOO separately and in a data
acq uisition system.
Figure 7 shows a Data Acquisition System. In this system
the PGA I 00 allows the user to deal with signals of wide
dynamic range while maintaining high system resolution.
For example: When used with a 12-bit AI D converter in
a "floating point" system, the 27 gain range of the
PGAIOO plus the 2'2 range of the converter produces a
total system resolution of 2'9 (524,000 to I).
c:
Also the user can modify and reprogram gain values for ~
different analog input channels merely by changing the
software computer program. Since· different dedicated
amplifiers are not required for various input channels,
the PGAIOO also saves space and overall system costs.
Software correction virtually eliminates system offset
and gain errors over both time and temperature.

SETTLING TIME
Settling time is the time required, after application of a
step input signal, for the output voltage to settle and
remain within a specified error band around the final
value. It is a very important consideration since this will
be the limiting parameter in determining the maximum
channel scanning or throughput rate. The PGAloo"
specification includes the effects of both the multiplexer
and amplifier. Note that settling time increases with
increasing source resistance and gain. Minimum settling
time is achieved by choosing a low "source resistance, for
example. Rs';;; IOkfl and gains';;; 16. (See Performance
Curves.l
INPUT OVERVOLTAGE PROTECTION .
The PGAIOO provides input overvoltage protection of
20V in excess of either power supply voltage expressed as
±( IVee 1+20). This is achieved in the dielectrically
isolated analog multiplexer which will withstand overvoltage even when the power supplies are off. As a
consequence the PGAlOO is protected against high input
levels and brief transient spikes of up to several hundred
volts that can result from signals originating from outside
the system. (See Performance Curves.)

TYPICAL APPLICATIONS
The PGAIOO is ideal for a variety of applications,
especially where low channel-to-channel crosstalk is
required. In many applications the PGAIOO will not
require trimming of offset and gain errors. However,
these can be minimized utilizing hardware or software
error correction techniques. Figures 6" and 7 show

FIGURE 6. Digitally Selectable Function Amplifier.

CRT DISPLAY

.~h> {~~~t-_______

D_AT_A_B_US_-,

BOARD

V-

'-- ~--"'-r---""'"

I

ADDRESS BUS

I---------.~

1'---------------1
~
CDNTHUlIUS

CP

~.':'

&ANALOG INPUT

J

ADORES. DECDD£I AID
~
CDIITRDl lDI1C

I----...t--l

I

CHAIINElS{~~~~~~~~P8AIOO~C; :IH...AII_._El_S_E_lE_CT_ _-I~a::.
=:

FOR OFFSET ANO GAIN I VREF
CORRECTION
1

V

,~

_

7'

AID
CONVERTER

AOC8D

'--___. .

'FIGURE 7. Use of PGAIOO in a Data Acquisition System with Software Auto-zero and Gain Calibration.

2-33

BURR-8ROWN®

PGA200/201

IElElI

Digitally-Controlled Programmable-Gain
INSTRUMENTATION AMPLIFIER
FEATURES

Ap·PLICATIONS

• DIGITALLY-PROGRAMMABLE GAIN
- Dellade Model - PGA200 .
Gains of 1, 10, 100,1000
- BlnarY'Model - PGA201
Gains of 1, B, 64, 512

• DATA;ACQUI$ITION SYSTEMAMPUFIER
• DIGITALLY-CONTROLLED AUTORANGING SYSTEM
• SYSTEM' DY~AMIC RANGE EXPANSION
• REMOTE INSTRUMENTATION SYSTEM

.. EXCELLENT GAIN ACCURACY (0.02%, max)
• LOW GAIN NONLINEARITY (0.012%, max;G = 1000)
• LOW GAIN DRIFT 11Oppm/o C, max; G
.

= 1000)
.

• 2-BIT LATCHED TTL-COMPATIBLE GAIN CONTROL
• LOW OFFSET VOLTAGEI25pV

~TI,

• TEST EQUIPMENT

max;G

= 1000)

• LOW OFFSET VOLTAGE DRifT 10.3o,.,V/oC, 'max;
G== 1000)'
.
,

The PGA200 is a hybrid Ie instrumentation amplifierwith 4igitally-controlled decade gain steps of 1,
10, 100, and. 1000. The PGA201 differs oniy by
providing binary steps of I, 8,64, and 512. Both have
TTL-comp!ltible latched inputs· for microprocessor
interface. The logic section has high input impedance and functions without a separate logic power
supply. Precision laser-trimmed offset and gain
permits use without external adjustments. High
perfprmance thin-film resistors with excellent tracking assure low gain drift and excellent stability.

lOkO

lOkO

201<0 .

2Ok0

+--"""'......-+-----{ 4

~~~:::_MOOE

>--+~I\M--'--......,0.....
kO--l8 g~~:N

InlernatlonllAlrparllnduslrlal Park· P.O. Box 11400· lucian. Arizona 85734 . Tal,(602) 746-lH,1 . Twx: 910-952-1111 . Cabla: 88RCORP.- Talax:66-6491

2-'34

SPECIFICATIONS
ELECTRICAL
At +25°C with ±15VOC power supply unless otherwise noted.
MODEL(')

PGA200/201AG

PARAMETER

CONDITIONS

GAIN
InaccuracyC21 G

MIN

=1

G=10
G=loo
G = 1000
Nonlinearity, G

=1

G=10
G=100
G = 1000
Drift vs Temperature, G;::: 1

G=10
G =100
G = 1000
Stability V5 Time

PGA200/201BG

TYP

MAX

0.02
0.02
0.02
0.02
0.002
0.002
0.003
0.012
10
10
10
10
0.D1

0.05
0.05
0.05
0.05
0.005
0.005
0.007
0.025
20
20
20
20

MIN

TYP

MAX

UNITS

0.01
0.01
0.01
0.01
0.001
0.001
0.002
0.011
5
5
5
5

0.02
0.02
0.02
0.02
0.002
0.002
0.003
0.012
10
10
10
10

%
%
%
%
%
%
%
%

ppmrc
ppmrc
ppm/oC
ppm/oC
%l1khr

RATED OUTPUT
VOltage

lo=5mA

Curr€!nt
Impedance

Vo=10V

10
5

12.5
10.0
0.3

V
mA
0

ANALOG INPUT CHARACTERISTICS

Common-Mode Range
Absolute Maximum Vortage

10
No Damage

V
V
011 pF
011 pF

Vee
10'0 II 3
10" 113

Impedance, Differential

Common-Mode
OFFSET VOLTAGE [RTI)

Initial Offset, max C31 , G = 1

G=10
G =100
G = 1000,
vs Temperature, G = 1
G=10
G=100
G = 1000
vs Time
vs Supply

225
45
27
25
10
2
1
1

450
90
54
50
22
4
2
2

110
20
11
10.
5
0.75
0.20
0.15

225
45
27
25
10
1.5
0.40
0.30

30

5

20

30

5

20

1 + (20/G)
1 + (20/G)

10 < Vee < lSV

pV
pV
pV
pV
pvre
pVloe
pv/oe
pyre
pVlmo
pVN

INPUT BIAS CURRENT

Initial at 25° C
vs Temperature

10
0.2
0.1
10
0.5

Each input

vs Supply
Offset Current
vs Temperature

nA
nAloe
nAN
nA
nAloC

COMMON-MODE REJECTION

G=1
G = 10
G =100
G = 1000

OCto 60Hz,
lkO Source

Imbalance

SO
96
106
106

95
110
120
120

.

dB
dB
dB
dB

INPUT NOISE'"

Input Voltage Noise, I. = O.IHz to 10Hz

0.8
18
15
13
50
0.8
. 0.46
0.35

Density, fa = 10Hz

1o = 100Hz
to=lkHz
Input C'urrent Noise, 18 = O.1Hz to 10Hz
Density. 10::: 10Hz

10= 100Hz

fo::: 1kHz

pV, pop
NV/"tHz
NVI"tHz
NV/"tHz
pA, pop
pA/"tHz
pAl"tHz
pAl"tHz

DVNAMIC RESPONSE

±3dB Flatness
G=1
G=10
G =100
G = 1000

Small signal

±1% Flatness

Small signal

G=1
G=10
G= 100
G = 1000

500
150
30
2.4

kHz
kHz
kHz
kHz

50
25
3
300

kHz
kHz
kHz
Hz

2,..35

ELECTRICAL [CONT]

,

'MODEL

PGA2OOI2OIAG
CONDITIONS

Full Power
Slew Rote
Settling Time (0,1%), G = 1
G=tO
G=l00
G=looo
Settling Time (0,01%), G = 1
G=10
G=l00
G=looo'"
Overload Recovery Time
G = 110100
G = 1000

G=ltol00
G'=l to 100

/

.MIN
0,2

TYP

PGA2OOI2OIBG
MIN

MAX

MAX

TVP

UNITS

,

6.4
0.4
35
35
50

kHz
VllJS8c
JlSec.
JlSec
"sec
JlSec
JlSec
"sec

,

480
40
40
80
670

IJS8C
JlSec

50% overdrive
12
22

DIGITAL INPUT CHARACTERISTICS
Input Low Threshold
Input Low Curren!
Input High Threahold I
Input High Current
T _, Write Pulse Width
T., Data SetuP Time
Th , Data Hold Time

-

,

$Isee
JlSec

0,8

V

30

"A
V

30

"A
nsec
nsec

2.4
300
180
30

POWER SUPPLY
Rated Voltage
Voltage Range
Quiescent Current

nsec.
±15

10
±10

TEMPERATURE RANGE
Specification
Operating
Storege

-40
-55

·18
±12
+85
+125
+150

-55

V
V
mA

,.

'C
'C
'C

,

'Specifications same as for PGA200/201AG,
NOTES: (1) All specifications pertain to both PGA200 and PGA201, Values for gains 01 10, 100, and 1000 for the PGA200 are the same lor gains 018,64 and
512. for the PGA201. (2) Measured with alOkO load.· (3) Adjustable to zero. This offset is the total offset Including both input and output components
referred to'the input. (4) Noise due to the Input stage. There Is also an output comppnent which becomes significant In low gain (see Typical Performance
Curves). (5) Settling time of the averege value of the output waveform since the nOise floor in a gain of 1000 is on the order of 0.01% of lull scale.

ABSOLUTE MAXIMUM RATINGS

MECHANICAL

Supply ................. , ......... , .. , ......... , .... ±18VDC
Internal Power Dissipation, ........ , ......... , .. ,...... 600mW
Analog And Digital Inputs .............................. ±Vcc
Operating Temperature Range ......•....... -55'C to +125'C
Storage Temperature Range ••• , .••.....•..• -55'C to +15O'C
Lead Temperature (Soldering 10 S"9onds) ••........•. +300' C
Output Short-.Circuit Duration .•....... Continuous To Ground
Junction Temperature .................................. 175'C

NOTE: Leads in true position within .010"
(.25mm) R at MMC at seating plane.

PIN DESIGNATIONS

INCHES

,OIM

1.
2.
3.
4.
5.

AO

Analog Common
WR
9. Output
-Voc
10. Offset Trim
Common-Mode Voltage 11. Offset Trim
NC
12. +Vcc
6. +IN
13. Digital Common
7. -IN
14. Al
8.

'0

PGA200 or PGA201

.B
Grade: A,

X

MAX

MIN

MAX

.170

.al0

19".56

20.51

.480-

.500

12:19

12.70

,155

.215

3.94

5.46

.016

020

.41

100 BASIC

'8

ORDERING INFORMATION
G

'-~T
.
.

14-pin DIP, G package

2-36

L'

MILLIMEtERS

MIN

.oeo

110

.009

012

.23

.150

..210

3.8'·

.300 BASIC
.015,

. 035

.•.

2.54 BASIC

2.03
.30
5.33

7.62 BASIC
.3.

..

.

TYPICAL PERFORMANCE CURVES
Til. = +25 0 C. ±Vcc

= 15VDC,

unless otherwise noted.

CMR VS FREQUENCY
120

G ='100,1000
G = 10

100
G=1

al

III

" 8 0 1 - - - - + - - - + - - - "....,..---1
ci:
::;

"

a: 80

::;

()

Balanced
Source

()

----1---

60

601------~----~---_4----~

40L-__~____~____~__--J

3.2

10

32

10

100

GJooo

y..

G=1100

III 40

\

"c
GJo

'"



;::

:;
0.
:;

Ol

.5

~

o

100

(f)

'\

-5

Z

c

32
0.0003
•
100
Gain (VN)

OUTPUT NOISE VS GAIN
30~--~-r--~--~----.,

§

1000

·-20
o

100

200

300' 400

500

600

Time 'psec·

INPUT NOISE VOLTAGE
VS FREQUENCY 100' GAIN 1000
1000

11r-_ _~I~Q;.V;.;S;.S;.,U;.p_p~~;.y_~_--,

l~

,;

">

.,

E 201-----+----+---1-1

%1001-----+----4---~

to

~

o

>

>

ill

~ 10 l-----t----+-J'==--l

:;
0.

:;

a

100
10
Gain IVNI

1000

'\ .....

I

-10

'iii
f"

FIGURE 2. Timing Di·agrams.

~Jc

GUARD DRIVE
Use of the guard drive connection in Figure 4 can
improve 'system common-mode iejection when the
distributed capacitance of the input lines is significant.

r---------,
I THIS CIRCUIT MAY BE USED AS A I

I REPLACEMENT FOR THE SINGLE I
I
I POTENnOMETER.

I ~F~~: ::~UL~VE '

OPTIONAL
INPUT
+Vcc OFFSET
ADJUST

I DRIFT UNCHANGED.

I
I

lOOkO

I
I

I

I

R,:
11

I
+Vcc

:
lOOkO 10MO

LI!.._!!. _____

I

J

FIGURE 3. Optional Input/Output Offset Adjust.
and changes with gain. The output component is due to
the offset of the second stage amplifier and is constant.
R\ may be used to null the input offset. Its quality will
affect the results; therefore, choose a potentiometer with
good temperature and mechanical resistance stability.
The wiper should be connected to +Vcc at a point as
close as possible to the + Vcc terminal of the instrumentation amplifier. Null the offset as follows:
I. Set E\ = E, = 0 (be sure a good ground return path
exists to the inputs).
2. Set the gain to 1000 (or 512 for PGA201).
3. Adjust R\ until the output reaches OV ±lmV or
desired value.
Input offset adjustment will affect the offset drift by
approximately 3.lp.V/oC/mV of offset that is,trimmed.
This effect can be greatly reduced by using the alternate
offset adjust circuit shown inside the dashed line.
The output offset may be nulled or, alternately, the
output can be level shifted with R •. R, and R3'divide the
wiper voltage of R. down for increased sensitivity. Their
ratio may be changed in order to increase the range of
adjustment if desired. The buffer amplifier is required in

FIGURE 4. Guard Drive.
The common-mode voltage which appears on pin 4 is
resistively derived from the output of the first stage
amplifiers and has the value (E\ - E2)/2. This voltage is
used to drive the shield which preferably should extend
up to and around the input pir;ts 6 and 7. This
configuration Improves common-mode rejection by
reducing the common-mode current flow. The buffer
amplifier is used in order to supply more current than
the internal 20kfl resistors can provide so that the guard
can accurately track the actual common-mode voltage.

TYPICAL APPLICATIONS
The PGA200 and PGA201 are ideal for computercontrolled data acquisition systems as shown in Figure 5.

FIGURE 5. Multiple Input Data Acquisition System
With Various Input Ranges.

2-39

BURR-BROWN®

X'TR100

IElI5II

"

.Precision, ;Low Drrft
4mA to 20m A
TWO-WIRE TRANSMITTER
FEATURES

APPLICATIONS

• INSTRUMENTATION AMPLIFIER INPUT
Low Offset Voltage. 25~ V mIx
.
low Voltage Drift. O,5~V/oC max
Low Nonlinearity. 0,01% max

• INDUSTRIAL PROCESS CONTROL
, Pressure Transmitters
Temperature TrsrismlHers
MIllivolt TransmlHers

• TRUE TWO-WIRE OPERATION
Power and Signal online Wire Pair
. Current Mode Signal Tra'nsmlsslon
High Noise Immunity
• DUAL MATCHED C.URRENT S,OURCES
• WIDE SUPPLY RANGE. 1t6V to 40V
• -4Q°C TO +85°C S~ECIFICATIONRANGE
• SMALL 14-PIN OIP PACKAGE

• RESISTANCE BRIDGE INPUTS
• THERMOCOUPLE INPUTS
• RTOINPUTS
• CURRENT SHUNT (mV) INPUTS'
• AUTOMATED MANUFACTURING
• POWER PLANTIENERGY SYSTEM MONITORING

DESCRIPTION
The XTR 100 is a microcircuit, 4mA to 20mA, twowire transmitter containing a high accuracy instrumentation amplifier(IA), a voltage controlled output
current source, and dual~n\atched precision current
references. This combination is ideally suited for
remote signal conditioning of a wide, variety of
transducers such as thermocouples, RTD's, thermistors, and strain gauge bridges. State-of-the art
design and laser-trimming, wide temperature range
operation and small size make it very suitable for'
industrial prOcess control applications.
The two-wire transmitter allows signal and power to
be supplied on a single wire-pair by mod!llating the
power supply current With the input signal source.
The tral)smitter is immune to voltage drops from
long runs and noise from motors,. relays, actuators,
switches, transformers, and industrialequipment. It
can be used by OEMs prOducing transmitter modules·

or by data acquisition system manufacturers. Also.
the XTRIOO is generally very useful for low noise.
current-mode signal transmission.

e,

~--~B +VCC

3

SPAN {

12131214
OPTIONALIANOWIDTH ~
CONTROL '

-r::-

. 'OPTIONAL OFFSETNUlL

Intlmallon.1 AIrport Indllllrlil Park. 1':0. Bax 11400 - TUClon.Arlzona 85734· TII.IIMizt 74&-1111 . Twx: 910-1152-1111 . cable: 88RCORp· Tllex: 6608491

2-40

SPECIFICATIONS
ELECTRICAL
At TA = +25"C. +Vee = 24VDC. RL = 1000 unle.s otherwise noted.

I
PARAMETER

CONDITIONSlDESIGNAnON

MIN

XTR100AM1AP
TVP
MAX

I

XTR100BMIBP
MIN
TVP
MAX

I
UNITS

OUTPUT AND LOAD CHARACTERISTICS
Current
Current

Current Limit
Offset Current Error
Offset Current Error vs Temp.
Full Scale Output Current Error
Power Supply Rejection
Power Supply Voltage
Load Resistance

Linear Operating Region
Derated Performance
10 min
lOS. 10 4mA
.:I.los/.:I.T
Full Scale 20mA

4
3.8
28
±1.5

=
=

±5

Vee. pins 7 & 8. complianc" ' )
At Vee +24V. 10 = 20mA
At Vee = +40V. 10 20mA

=

20

110
+11.6

22
38

·

·

±4
±10
±20

135

,

+40
800

=

1400

mA
mA
mA
"A
ppm. FSI"C
p.A
dB
VDC
0
0

SPAN

Equation
Untrimmed Error(2)
Nonlinearity
Hysteresis
Dead Band
Temperature Effects

Rs in 0, 8, and 82 in V
-5

ESPAN
ENONLINEARITY

io = 4mA + [0.016U+ (40/Rs)) (e. - e,)
-2.5
0
0.01
0
0
±100
30

%
%
%
%
ppm%I"C

INPUT CHARACTERISTICS
Impedance

Differential
Common-Mode
Voltage Range. Full Scale
Offset Voltage

vs Temperature
.Bias Current
vs Temperature
Offset Current
vs Temperature
Common-Mode Rejectlon(4)
Common-Mode Range

0.411 0.047
1011180
.:I.e

=182 - '" )1 3)

0

Vos
.:I.Vos/.:I.T
IB
.:I.IB/t.T
losl
.:I.losl/.:I.T
DC
81 and 62 with respect to pin 7

±D.7

80

90
4

0.30
10
0.1
100

1
±50
±1
150
1
±30
0.3

·

·
±0.25

±25
±D.5

±2O

'.

GOIlp.F
GO II pF
V
p.V
p.VI"C
nA
nAl"C
nA
nAl"C
dB

V

6

CURRENT SOURCES

1

Magnitude

Accuracy
vs Temperature
vsTime
Ratio Match
Accuracy
vs Temperature
vsTime
Output Impedance

Vee = 24V. V.,N 8 - V.,N 10. 11
19V. R.= 5kCl. Fig. 3

mA

=
±0.03

Tracking
1 -IREFI/1REF2

±D.OO6
10

±0.02
±15

±1
20

±D.05

-40

-55
-40
-55
-40

10

·

TEMPERATURE RANGE
Specification
Operating lAM. BMI
lAP. BPI
Storage IAM.BM)
lAP. BPI

±D.015

±D.l
±30

±8

+85
+125
+85
+165
+85

·

·

%
ppml"C
ppm/mo.
%
ppml"C
ppm/mo.
MO

°C
°C
°C
°C
°C

'Same as XTR100AM/AP.
NOTES:
1. See TYPiC~1erlormance CUrvBB.
2. Span afro hown is untrimmed and may be adjust~ to zero.
'
3. '" and e2
signals on the -INand +IJII terminals with respec1totheoutput. pin 7. While the maximum permissible.:l.e islV. it is primarily intended
lor much I wer input signal levels. e.g .. 10mV or50mV lull scale lor the XTR100A and XTR100B grades respectively. 2mV-FS is also posalblewlth
the B grade; but accuracy will degrade due to possible errors in the low value span rBBlslance and very high amplillcation 01 offset. drift. and noise.
4. Ollset voltage is trimmed with the application 01 a 5V common-mode voltage. Thus the associated common-mode error Is removed. See
Application Information section.

2-41

ABSOLUTE MAXIMUM RATINGS
ZEROADJU~T.

Power Supply, Vee
InputVoltage,EI1,Or82
Storage Temperature Range, metat
Storage Temperature'Rarige; plastic
Lead Temperature (soldering 10 seconds I
Output Short-circuit Duration
Junction Temperature
'

l
f

40v
"Vour,:S +Vee
-SS°C to +1S50C

-400 C

to +85~C

BANDWIDTH
CONTROL

IREf2

+300OC

Continuous to -ground
+1S5°C

IREF!

MAKE NO
CONNECTION
+Vce

MECHANICAL
XTR100AM/BM
(Metal)

XTR100AP/BP
'(Plastic)

rD
l-U
C

NOTE: Leads in true position within
0.10- I 0.25mm, R at MMC
at seating plane.

NOTE: Leads in true position within
0,10" rO,25mm' R at MMC
at seating plane.

Denotes
Pinl

INCHES

OIM

MIN

MAX

MILliMETERS
MIN
MAX

.880

21,84

22,35

.510

,12.45

12.95

.170

.250

4.32

6.35

0

.016

.021

0.41

0.53

G'

.100 BASIC

,155

2.92

3.94

.150

.300

3.81

7:62

7.62 BASIC

.080

2.03

120

Pin numbers shown for
reference only.
Numbers are not marked
on package.

.790

.,0

20.07

20.57

,490

.510

12.45

12.95

.190

.210

<\.83

5.G3.

[Rl[H

:~~~BAS'i~

0.46

0.53

r-t~ OOOOO!l
•
loooooo~

~

r:JL-Lo

2.54 BASIC

.115

.300 BASIC

~

K

.860
.490

3.05

jJL
"

MATING CONNECTOR:
0145MC

'

.

L

~:: BAS1~15

2,54 BAS.lC

2.03

2.92

3.30

7.62

7.62 BASIC"

2.03

Prn numbers shown for
reference only.
Numbers are not marked
on package.

TYPICAL PERFORMANCE CURVES
(TA = +25°C, +Vec = 24VDC unless 'otherwis~ noted I

.,

SPAN VS FREQUENCY
80

RS -1000

Rs=~O
RS=2kO
Rs-"

STEP RESPONSE
25

Cc=O

Rs =25A

."""

~

.'.~

IRsJ

<
g

_ 0.6 1----+--~..JE=---_4l---__t

Rs=250

~

~

10k
lOOk
Frequency (HZI

1M

" 10

(.)

I

:;

Co

:;
0

o

~

~

~

!

~

-

)

\~

~= 0.4' I--~~~--:-,i----t----I .9. 04 al=s

~

o
lk

20

~ 15

.~

100

FULL SCALE INPUT VOLTAGE VS Rs
RS(OI .
o
100
200
300
~8r----r----,.~~~--~

~

0.2

0.02 <1

____.-L____
200

400
600
Time (posee)

800

1000

2

~

__- L__

4
Rs (kOI

6

~O

8

COMMON-MODE REJECTION
VS FREQUENCY

POWER SUPPLY
REJECTION VS FREQUENCY

140

120
100

r-

""

80

iii
"0

ri:
::;;
tl

60
40
20

o
10

0.1

100

""

100

1k

"

."

40

Z

!
I
I

---1--1---_._-

0,

10

100

lk

100 ~--~-if--1I1or~~~,---I

c::

,

~ 10~--~~f-~---111or~~~

0.1 I....----'L----L__--'-_--'--_..I-----'
10
100 lk
10k lOOk 1M

10k lOOk 1M 10M

Frequency (Hz)

Bandwidth Control, Cc ipFI

INPUT CURRENT NOISE
DENSITY VS FREQUENCY

4

'5

3

,

0
100

lk

10k

lOOk 1M

o

1

4

f

>

-.~-.

3

1\
\

,

m

~
'5

~

'5
Q.
E.

5

;{
.os

"

\

m

'0

~

"

~\

z

E.

OUTPUT NOISE CURRENT
DENSITY VS ..FREQUENCY

6

tl

'[ 10

10

5

!1:
l'

\,

~--~~~~~~~-+--~

""",

I

~

0>

>
.~0 20

""'",

lk

6

50

30

~
:;

',,-

,

20

"

">

'5

10k

40

60

~

"" '",

a:
~ 60

10k lOOk

Frequency (Hz)

3>

I

iii 60

INPUT VOLTAGE NOISE
DENSITY VS FREQUENCY

l~

r-....

120

BANDWIDTH VS
PHASE COMPENSATION

10

......
100

Frequency (Hz)

2

%1

o
lk

10k

lOOk

1M

o

Frequency (Hz)

1

Rs=.o

"

10

100

.......
lk

10k

lOOk 1M

Frequency 1Hz!

THEORY OF OPERATION
A simplified schematic of the XTR I 00 is shown in Figure
l. Basically the amplifiers, AI and A2, act as an instrumentation amplifier controlling a current source, A3 and
QI. Operation is determined by an internal feedback
loop. el applied to pin 3 will also appear at pin 5 and
similarly C2 will appear at pin 6. Therefore the current in
Rs. the span setting resistor, will be Is = (C2 - el)/ Rs =
els; Rs. This current combines with the current, h. to
form II. The circuit is configured such that h is 19 times
II. From this point the derivation of the transfer function
is straightforward but lengthy. The result is shown in
Figure l.
Examination of the transfer function shows that 10 has a
lower range-limit of 4mA when elN = e2 - el = OV, This
4mA is composed of 2m A quiescent current exiting pin 7
plus 2mA from the current sources. The upper range limit
of 10 is set to 20mA by the proper selection of Rs based on
the upper range limit of e,,,. Specifically Rs is chosen for a
16mA output current span for the givenfull scale input
voltage span; i.e,. (0.016U + 40/ RS)(eIN full scale)
= 16mA, Note that since 10 is unipolar e2 must be kept
larger than el; i.e., ez ;;;. e, or eIN ;;;. 0, Also note that in
order not to exceed the output upper . range limit of
20m A. e'N must be kept less than I V when Rs = ~ and
proportionately less as Rs is reduced,

R3
1.25kn

R4
125kn

10 = 4mA + [0.01 BtJ+ 4O/R.I"" a",. = Is "-

'1

FIGURE I. Simplified Schematic of the XTRIOO.

2-43

I NSTAL,LATI ON AND
.....
OPE'RATJNG INSTRUCTIONS

Solving for Rs;
40

Rs=

(I)

AIo/Ae - 0.01.6U
Major points to ·consider· when designing with the
XTRIOO:
I. The lea:ds to Rs should be kept as short as possible to
reduce noise pick-up and parasitic resistance..
.
2. +Vcc. should be bypassed with a O.OIIlF capacitor as
close to the unit at possible (pin 8 to 7).
3. Always keep the input voltages within their range of
linear operation
.
+4V~el ~+6V

+4V~e2o;;;+6V

(el and e2 measured with respect to pin 7).
4. The maximum input sign~llevel (eIN FS ) is I V with
Rs = ~ and proportionally less as Rs decreases.
5. Always return the current references (pins 10 and II)
to the output (pin 7) through an appropriate resistor.
If the references are not used for biasing or excitation
connect them together and through a I kO resistor to
pin 7. Each reference must have between +1 V and
+(Vc.c -4V) with respect to pin 7. Filter with one
O.OIIlF or two 0.00471lF capacitors.
6. Always choose RI. (including line resistance) so that
the voltage between 'pins7 'and 8 (+Vcd remains
within thell.6V to 40V range as the output changes
between the 4mA to 20mA range (see Figure 2).
7. It is recommended that a reverse polarity protection
diode (0., in Figure I) be used. This will prevent
damage to the XTRIOO caused by momentary (e.g.,
transient) or long term application of the wrong
'polarity of voltage between pins 7 and 8.

For example, if AelN Fs = 100mV for Al oFS = 16mA
.40
Rs == ~(~16:-m-A~/:-:-IOO=-m-:V-:::-)

40
0.16-0.016

==~==2780
0.144

See Typical Performance Curves for a plot of Rs vs
..le,,,FS' Note that in order not to exceed the 20mA upper
range limit elN must be less than I V when Rs == ~ and
proportionately smaller as Rs decreases.

BIASING THE INPUTS
The internal circuitry of the XTR 100 is such that both e,
ande2 must be kept approximately 5V above the voltage
at pin 7. This is easily done by using one or both current
sources and an external resistor R2. Figure 3 shows the
simplest case - a floating voltage source e'2. The 2mA
from the current sources flows through the 2.5kO value
of R2 and both e, and e2 are raised by the required 5V with
respect to pin 7. For linear operation the constraint is
+4V
+4V

~el ~+6V
~e2~+6V

8. When the XTRI 00 is in high gain, use a compensation
capacitor, pins 12 and 13, and consider PC board
layout which minimizes parasitic capacitance.

tmA

!-

1500
1250

-

R2=2.5kn

250

tmA

+5V-'

O~~I~O·

~

alN =82'

l1li

PlWjlr Suppl, VaIIIge, Vps (wnll.

FIGURE 2.Power,Supply Operating Range.

40
,,=4IIA+I\UIIIU + IiSlelN

FIGURE 3. Basic Connection for Floating Voltage
Source.

SELECTING RS
- RSPAN is chosen so that a given fuli scale input span.elN FS
will result in the desired full scale output span of AloFs,
[(0.016U) + (40/RsJl AelN = Ala = 16mA.

Figure 4 shows a similar connection for a resIstive
transd ucer. The transducer could be excited eit her by one
(as shown) or both current sources.

2-44

lmA

~

O~.

________________________

~

RIl.tlvl liN tv!

,

,
(
\

,

.:.-,

FIGURE 5. Elevation and Suppression Graph.

',!--........,.."---"..."",...----'

C:::~;:~::CUITRY
SHOWN IN FIGURE 6

'0 = 4mA + (G.01BO

+

~ "'in

·IN=.z=lmAXRT

I

,,,

.•,
I

I.

FIGURE 4. Basic Connection for Resistive Source.

+

e2

I

I

".......... ...__ .. - ... ~JI'.,' --... 2mA

CMVANDCMR
Thus the XTR 100 is designed to operate with a nominal
5V common-mode voltage at the input and will function
properly with either input operating over the range of 4V
to 6V with respect to pin 7. The error caused by the 5V
CMV is already included in the accuracy specifications.
If the inputs arebiased at some other CMV then an input'
offset error term is (CMV- 5)/CMRR; CMR is in dB,
'CMRR is in V/V.

.,N = "'2' V""

a'N = [12 + V4'

V4 = lmA x R4
8'2 = ImAx RT
[II Elevlflld Zero Rangl

V4=lmAxR4
"2= lmAx RT
[bl Suppreaed Zero Ringe

,-

.'+
,/V4

SIGNAL SUPPRESSION AND ELEVATION

In some applications it is desired to have suppressed zero
range (input signal elevation) or elevated zero range
(input signal suppression). This is easily accomplished
with the XTR 100 by using the current sources to create
the suppression/ elevation voltage. The basic concept is
shown in Figures 5 and 6(a). In this example the sensor
voltage is derived from RT (a thermistor, RTD or other
variable resistance element) excited by one of the ImA
current sources. The other current source is used to create
the elevated zero range voltage. Figures 6(b), (c) and (d)
show some of the possible circuit variations. These
circuits have the desirable feature of noninteractive span
and suppression/ elevation adjustments. Note: It is 'not
recommended to use the optional offset voltage null (pins
I, 2, and 14) for elevation/suppression. This trim
capability is used only to null the amplifier's input offset
voltage. In many applications the already low offset
voltage (typically 201l V) will not need to be nulled at all.
Adjusting the offset voltage to nonzero values will
disturb the voltage drift by ±0.31l V/"C per IOOIL V of
induced offset.

'

,,
\
,

.....

\,
:/
,,/ -"2mA

.......... _-_ ....;'
'IN = [82' V""

'IN =[.'2 + V4'

V4=2mAxR4
.[el Elevilld Zero Rangl

V4 =2mAx R4
[dl Suppreaed Z.ra Rlflge

FIGURE 6. Elevation and Suppression Circuits.

APPLICATION INFORMATION
The small size, low offset voltage and drift, excellent
linearity, and internal precision current sources, make
the XT R 100 ideal for a variety of two-wire transmitter
applications. It can be used by OEM's producing different
types. of transducer transmitter modules and by data
acquisition systems manufacturers who gather transducer
data. Current mode transmission greatly reduces noise

2-45

interference. The two-wire nature of the device allows
economical signal conditioning at the transducer. Thus
the XlR I00 i~, in general; very suitable f~r individualized
and special purpose applications.
EXAMPLE I - RTD Transducer shown in Figure 7.
Given a process with temperature limits of +25°C and
+1 50°C, configure the XTRlOO to measure the temperature with a platinum RTD which produces 1000 at O°C
and 2000 at +266"C (obtained from standard RTD
tables). Transmii 4mA for +25°C and 20mA for + 150°e.
Computing Rs.
The sensitivity of the RTD is .lRj.lT = 1000j266"e.
. When excited with a I rnA current source for a 25"C to
150c.C range (i.e., 125°C span) the span of elN is I rnA x
(lOOOj266cC) x 125°C = 47mV = AeIN.
From equation I, Rs =

°1

40

-'-----~-

Alo

L\ein -

0.016U

== 0.:0244

Rs =' . . 40
. 16mA _ 0016U
47mV
.

= 123.30

Span adjustment (calibration) is accomplished by trimming Rs.
Computing R4:
At 25°C, e'2 = ImA x [1000 +

(~:.~

x 25"C)]

= ImA x 109.40
= 109.4mV
In order to make the lower range limit of2SoC correspond
to the output lower range limit of 4mA the input circuitry
shown in Figure 7 is used.
elN is made 0 at 25 cC
or e;2S'C - V. = 0
thus, V,.= e22S'C = 109.4mV
V,
109.4mV
R. = ImA =
ImA

= 109.40

,Computing R2 arid checking CMV:
At 2ScC, ez = 109.4mV
At ISOoC,'e2 = ImA x [1000 +

(;:c~

x ISO°C)]

FIGURE 1. Circuit for Example I.
EXAMPLE 2 - Thermocouple Transducer shown in
.Figure 8. Given a process with temperature (TI) limits of
O"Cand +1000"C. configure the XTR 100 to measure the
temperature with a type J thermocouple that produces a
58mV change for 1000°C change. Use a semiconductor
diode for a cold junction compensation to make the
measurement relative to Oce. This is accomplished by
supplying a compensating voltage, VR., equal to that
normally produced by the thermocouple with its "cold
junction" (T2) at ambient. At a typical ambient of+25"C
this is 1.28rilV (obtained from standard thermocouple
tables with reference junction ofO"C). Transmit 4mA for
TI =O°C and 20mA forTl=+IOOOce. Note:eIN=e2 -el
indicates that TI is relative to T 2.
Establishing Rs :'
The input full scale span is S8mV (Ae'N Fs = 58mV).
Rs is found from equation (I)
40

Rs = -.l-:--:"h-,....;'----

= IS6.4mV

- - - 0.016U
delN

Since both ej and V4 are small relative to the desired SV
common-moae voltage they may be ignored in computing
R2 as long as theCMV is met.
R2 = SV j2mA = 2.SkO
e2 min=sv+0.109.4Vj
e2 max = SV + O.IS64V

el= SV + 0.1094V
.,'

40
16mA _ 0.016U
S8mV

The +4V to +6V CMV
requirement is met.

Rs = 153.9q

.

2-46

40
= 0.2599

Selecting R.,:
R. is chosen to make the output 4mA at TTe = O"C (VT<:' =
-1.28mV) and Tn = 2SoC (Vo = 0.6V). A circuit is shown
in Figure 8.
VTe will be -1.28mV when TTC = O°C and the reference
juntion is at +2S"C. e, must be computed for the
condition of T" = +25°C to make elN = OV.
V"25'T
el 2S'c
elN
withelN
V.
ImA x R.
R.

The diode voltage has the form
KT
q

0

IOIOI)E
ISAT

VI)=--~n---

Typically at T2 = 2SoC, Vp = 0.6V and tJ.Vo/tJ.T =
-2m V j"c. Rs and R" form a voltage divider for the diode
voltage VD. The divider values are selected so that the
gradient tJ. Vo/ tJ. T equals the gradient of the thermocouple at the reference temperature. At 25°C this is
approximately S2p. V j"C (obtained from standard thermocouple table) therefore,

= 600mV.
= 600mV x SI/ 20S1 = 14.9mV
= e2 - el = + VTC + V. - e,
=OandVrc =-1.28mV
= e'l + eIN - VTC = 14.9mV + OV -(-1.28mV)
= 16.18mV
= 16.180

(2)

52 V/"C = 2000 V "'C (
R.
p.
P. I
Rs + R.
Rs is chosen as 2kO to be much larger than the resistance
of the diode. Solving for R. yields 510.
THERMOCOUPLE BURN-OUT INDICATION
In process control applications it is desirable to detect
when a thermocouple has burned out. This is typically
done by forcing the two-wire transmitter current to either
limit when the thermocouple impedance goes very high.
The circuits of Figures 14 and IS inherently have down
scale indication. When the impedance of the thermocouple gets very large (open) the bias current flowing into
the +input (large impedance) will cause In to go to its
lower range limit value (about 3.8mA). If up scale
indication is desired the circuit of Figure 16 should be
used. When the TC opens the output will go to its upper
range limit value (about 2SmA or higher).

FIGURE 8. Thermocouple Input Circuit with Two
Temperature Regions and Diode (D)
Cold Junction Compensation.

OPTIONAL INPUT OFFSET VOLTAGE TRIM
The XTR 100 has provisions for nulling the input offset
voltage associated with the input amplifiers. In many
applications the already low offset voltage (2Sp. V max for
the B grade, SOp. V max for the A grade) will not need to
be nulled at,all. The null adjustment can be done with a
potentiometer at pins 1,2, and 14 as shown in Figures 3
and 4. Either of these two circuits may be used. NOTE: It
is not recommended to use this input offset voltage
nulling capability for elevation or suppression. See the
Signal Suppression and Elevation section for the proper
techniques.

Cold Junction Compensation:
The temperature reference circuit is shown in Figure 9.

l~lmA
+

RS
+

Vo

-

Vs

-

0
+

R6

V6

OPTIONAL BANDWIDTH CONTROL
Low-pass filtering is recommmended where possible and
can be done by either one of two techniques shown in
Figure 10. C2 connect to pins 3 and 4 will reduce the
bandwidth with a cutofffrequency given by,

-

f

fco
FIGURE 9. Cold Junction Compensation Circuit.

2-47

1.59 x 10
=------""'-'-------(R,'+ R2 + R3 + R.)(C, + 0.047p.F)

8
=
tc

with feo in Hz, all Rs in nand C, in JJ. F. Thi~ method has
the disadvantage of having feo vary with R" R" R3, R.,
and it may require large values of R3 and R•. The other
method, using C,· will use smaller values of capacitance
and is not a functiCln of the input resistors. It is however,
more subject to nonlinear distortion caused by slew tate
liini,ting. This is normally not a problem with the slow
signals associated with most process control transducers.
The relationship between' C, and feo is shown in the
, Typical Performance Curves.

FIGURE 13. Bridge Input, Curre'nt Excitation.

ImAJ
R3'

ImA~
RI

RZ

~

THE CIRCUIT HAS
DOWN SCALE BURN-OUT
INDICATION

114'
15!!

'Ra AND R4 SHOULD BE MADE EQUAL IF USED.
Inllrlllily 'nil.. RTI =

Je2lnput ilia. +[11II1put llaae ] 2
Iiii1

FIGURE 10. Optional Filtering.
FIGURE 14. Thermocouple Input with RTD
Cold Junction Compens~tion.

APPLICATION CIRCUITS

~lmA

THE CIRCUIT HAS
DOWN SCALE BURN-OUT
INDICATION

ISOLATOR

FIGURE II. XTRIOO with Lo~p-powered Isolation.

FIGURE 15. Thermocouple Input with
Diode Cold Junction Compensation.

THIS CIRCIIT HAS UP
SCALE BURN·OUT INDICATION

LMl28
6.9V
WLTAGE
REF

FIGURE 12. Bridge Input, Voltage Excitation.

FIGURE 16. Thermocouple Input with RTD
Cold Junction Compensation.

2-48

V+~--~---------------------------.

MCI403A

VOLTAGE
REFERENCE

HI
VR
10' =(I + Rillo
=12510- 4mA

ii2

* 1 '(0. 20mAI

OTHER COI(VERSIONS ARE READILY ACHIEVABLE BY
CHANGING THE REFERENCE AND RATIO OF Rlto At.

0

FIGURE 17. OmA to 20mA Output Converter.

DETAILED ERROR ANALYSIS

The term in brackets maybe written in terms of offset
current and resistor mismatches as 10, j.R + los' R4.

The ideal output current is
• (3)
in 11)1'\1. = 4mA + K e""
K is the span (gain) term, (0.016mA/ mY) + (40/ Rs)

V,lSI* = input offset voltage

18" * 102* = input bias current
los,* = input offset current
IlR = RT - R4 = mismatch in resistor
j. Vec = change supply voltage between pins 7 and
8 away from 24V nomimal
PSRR* = power supply rejection ratio
CMRR* = common-mode rejection ratio

The nature of the XTR 100 circuit is, such that there are
three major components of error,
ao = error associated witH the output stage.
as = errors associated wit h span adjustment.
a, = errors associated with input stage.
The transfer function including these,err~rs is
10 Aen'AL = (4mA + ao) + K (I + as)(e'N -J.. ad

as =

(4)

When this expression is expanded, second order terms (as
a,) dropped, and terms collected, the result is

io ACTlJAL = (4mA + ao) + K e'N "Ka, + Kas e'N

Given the circuit in Figure 7 with the XTR 100B specifica'tions and the following conditions: RT = 109.40 at
25°C, RT = 156.40 at 150~C, 10 = 4mA at 25°C, 10 = 20mA
at 150°C, Rs =,123,30, R4 = 1090, RI. = 2500. RUNE =
1000, VD' = 0.6V, Vps = 24V ±0.5%. Determine the %
error at the upper and lower range values.

(6)

This is a general error expression. The composition of
each component of error depends on the circuitry inside
the XTR 100 and the particular circuit in which it is
applied. The circuit of Figure 7will be used to illustrate
the principles.
ao = 10sRTO
(7)

A. At the lower range value (T = 25°C).
ao = 10SRTO = ±4/-LA
IlVcc
a, = VOSI + [IBI j.R + losl R4]+ PSRR
+

10sRTO* = the output offset error current.
F or the circuit of Figure 7,

a, = VOSI + [IB' RT - IB2 R,] +

+

(e,

~;~~

+ fSPAN

EXAMPLE 3

(5)

The error in the output current is io ACTlJAL - io IDEAL and
'can be found by subtracting equations (5) and (3).
io ERROR = ao + Kas + K as ell'

ENONLfN

ENONUN* = span nonlinearity
ESPAN* = span equation error. Untrimmed error
= 3% max, May be trimmed to zero.
*Items marked with an asterisk (*) can be found in the
Electrical Specifications.

(el + e2)/2 - 5
CMRR
IlR = RT2S0C - R4 = 109.4 - 109 = 0

Il Vcc = 24 x 0.005 + 4mA (2500 + 1000) + 0.6V
= 120mV + 1400mV + 600mV =2120mV
el = (2mA x 2.5kO) + (I mA x 1090) = 5.109V
e2 =(2mAx2.5kO) + (lmA x 109.40) =5.1094V
(el +e2)/2-5=0
PSRR = \3.16 x lOs for llOdB
CMRR = 31.6 x 103 for 90dB

(8)

+ e,)/2 - 5V
CMRR

2-49

(1(

= 25pV + (l50nA x 0 + 30nA x 1090)
+

.2120mV +
3.16xlOs

(9)

31.6 ~ 103

= 25pV + 3.27pV + 6.7pV + 0
= 34.97
Os = ENONLlN + ESPAN
= 0.0001 + 0 (as~umestrim of Rs)
io error = 00 + K 01 + K Os elN
K=0.016+

40

R';

'
40
=0.016t 123.30 =0.34IU

A NOTE FOR HIGH, GAIN APPLICATIONS

elN = e2-V. = IREFI RTZ5T-IREF2 R.
since Rr 2S'C = R.
elN = (lREFI-IREF2) R. = O.lpA x 1090 = 1O.9pV
Since the maximum mismatch of the current references is
O.OI%of ImA=O.lpA
io error =4pA + (0.34Ux 34.97) + (0.341 x 0.0001)
x 10.9pV =4pA + II.S9pA + O.OOO4pA = 15.S9pA
15.S9
'
% error = - - - x 100% = 0.4 at lower range value.
4mA

B. At the upper range value ( T = ISO"C)

= Rr ISG'C " R. =

7720mV
+
, 3.16 x lOs

+----:;X

10'

= 2SpV + 1O.33pV'" 24pV FO = S9-33pV
Os =0.0001
elN = ej - V. = IREFI 'Rr ISG'C - IREF2 R.
= (ImA X 156.40) - (hilA - 1(90)
= 47mV.
'
io ERROR

= 00 + K 01 + K Os x elN
= 4pA + 0.341U x 59.33pV + 0.341Ux
0.9001 x 47000pV
= 4 x 20.23 + 1.6 = 2S.S3pA

25.S3pA
% error = 20mA: x 100%

= 0.13% at upper

This is the thermal resistance from output transistor
to ambient. It is used for normal power dissipaiion
considerations (see Figure IS).

Thermal Resistance: OJ! = 600 CjW
Input Stage Temperature Rise:
at 20mA output: 700mW X 60°CjW = 42"C
at 4mA output: IS6mW X 60"CjW = 9.4"C

0

31.6

In applications where €liD full scale is small «SOm V) and
R,pan is small «-ISOo.), caution should betaken to consider errors from the external sPlin circuit plus high
amplification of offset ~rift and noise.
In such applications, be sure to include the effect of the
normal thermal feedback within the XTRIOO package.
Small additional errors, occur from a change in input
offset voltage and current due to a change in chip temperature resulting from a change in output current (4mA up
to ~OmA).
The XTRIOO has two thermal resistance specifications:
(hA= IIS"C

OJ! = 6O"CjW
This is the therm3J. resistance which describes the
effect of outPllt stage power dissipation in input stage
temperature rise.
As an example of how OJ! would be applied, we will
calcuhi.te the limits with Vps = 40V and RL = 2S00.
Power Dissipatio/l:
at 20mA output: 20mA [40V-(20mA X2S00)] = 700mW
at 4mA output: 4mA [40V-(4mA X 2S00)] - IS6mW

IS6.4 - 109.4 = 470
~ Vel' = 24 x O.OOS + 20mA (2S00 + 1000) + 0.6
= 7720mV
el '" 5.109V
e2 =(2mA x2.5kO)+(ImA x IS6.40) =S.IS6V
(el e2)j 2 - SV ""0
~R = -Rr, Isac + R. = IS6.4 - 109 = 470
on= 4pA
01 = 2SpV + (IS0nA x 470 + 30nA x 1090)
'~R

CONCLUSIONS
From ~quation (9) it is observed that the predominant,
error term is the input offset voltage (2Sp V for the B
grade). This is of little consequence in many applications.
Vos RTI can, however. be nulled using the pot shown in
Figures 3 and 4. From equation (10). the predominant
errors are los RTI (4pA), Vos Ru(2S/i V), and Io (\SOnA),
max, B gmde.
'

(10)

Thus under these conditions when the output changes
from 4mA to20mA the input stage temperature changes
42"C - 9.4"C = 32.6"C. The maximum input stage offset
change will depend on the particular grade specification:
A Grade (lpVj"C max) 32.6pV
B Grade (O.SpV JOC max) = 16.31iV

=

The amount of error that this offset voltage represents
depends on how large'the full scale input voltage is. It is
worse, of course, for small input voltages. Table I shows
the error as a percentage of full scale and in terms of
output current (% FS,error X 16mA FS output span).

range value or % of FS.

2-50

TABLE I. Maximum Errors Due to Thermal Feedback
Vps = 40V, RL = 250ft
A Grade

- B-Grade

10mV FS

100mV FS

WFS

0.326%
(52.2pA)

0.0326%
(5.22pA)

0.0033%
(0.522pA)

0.163%
(26.1I'A)

0.0163%
(2.61I'A)

0.0016%
(0.261I'A)

HOW TO REDUCE ERRORS
Lower Vps
The errors can be reduced by lowering the voltage at the
XTRIOO line terminals. The errors in the example above
represent a fairly demanding condition of maximum voltage (V PS = 40V) and minimum resistance (RL = 2500). If
the voltage is lowered to 24V, then a 4mA to 20mA
output change causes a change in input stage temperature of 17.3°C and the errors in Table I are reduced by a
factor of 17.3°Cj 32.6°C = 0.53. (Note that this is different than the decrease in the voltage itself: 24/40 = 0.6.)
Raise Resistance
If the load or line resistance is raised the output power
dissipation will also be reduced. If RL = 4000 (400/250
= \.6), the change in output temperature is 29.2°C as the
output changes from 4mA to 20rnA (still with Vps =
40V) and the errors in Table I are reduced by a factor of
29.2OC/32.6°C = 0.9.
Heat Sink
Heat sinking the package will reduce both OJA and OJ!.
The following is information on small-finned heat sinks
that are attached with an epoxy heat sink adhesive
(AHAM-985). The three models are 0.75" X 0.4" X 0.21".
Model 141
Models 141 and 142
. AHAM
Heat Sink Plus
27901 Front St.
28715 Via Montezuma
Rancho, CA 92390
Temecula, CA 92390
(714) 676-4151
(714) 676-3031

1430
1400
1300
_ 1200

~

1100

i

1000

is

700

_

600
500

XTR100 POWER DERATING CURVE

"

-~

'""

900
1
'il 800

J
'iii

j

'"'" "-

-8

..-115°C/W

"

400
300
200

ex:

lX

'"

100

o

25

50
100
125
75
Ambient Temperl:!ture (oG)

150

17

FIGURE 18. Power Derating Curve.

GENERAL RECOMMENDATIONS HANDLING
PROCEDURES FOR INTEGRATED CIRCUITS ,
All semiconductor devices are vulnerable, in varying
degrees, to damage from the discharge of electrostatic
energy. Such damage can cause performance degradation
or failure, either immediate or latent. As a general
practice we recommend the following handling procedures to reduce the risk of cilectrostatic damage.
1. Remove the static-generating materials, such as
untreated plastics, from all areas that handle microcircuits.
2. Ground all operators, equipment, and work stations.
3. Transport and ship microcircuits, or products in~
corporating microcircuits, in ,static-free, shielded
containers.
4: Connect togethe~ all leads of each device by means of a
conductive material, when the device is not connected
into a circuit.
5. Control r~lative humidity to as high a value as practical (50% is recommended).

2-51

BURR-BROWN®

3606

'.IElElI

Digitally Controlled

Programmable Gain
INSTRUMENTATION'AMPLIFIER.
FEATURES
-11 BINARY GAINS -I. 2. 4. 8.16.32.
64.128. 256. 512.1024V/V
- 4-BIT TTL GAIN 'CONTROL
- EXCELLENT GAIN NONLINEARITY
0.01% max at G= 1024V/V
- LOW GAIN ERRORS - 0.02% max
- LOW GAINORIFT - 10ppm/oC max

- LOW VOLTAGE DRIFT
l~V/oC max RTI. G= 1024V/V
-HIGHCMR -110dBmln. G= I024V/V
- HIGH INPUT IMPEDANCE - 10 x J09n
-LOW OFFSET VOLTAGE
22.uV max Rn G= 1024V/V
2mV max RTI. G= IV/V

r-------------------------------------,

I

I

I

I

I

I

I

I

I
I
I

I

I
I

I
I
I

t

I

I

t

9--------\
L ____________________ _

I
I
I

_ _ _ _ _ _ _ -1I

Inlernatlonal Alrporllnduslrlat Park - P.O. Box 11400 ~ Tucson. Arizona 85734 - T81. 16021 746-1111 - Twx: 910-952-1111 - Cable: 8BRCORP - Telex: 66-6491

2-52

DESCRIPTION
The 3606 is a self-contained, Programmable Gain
Instrumentation Amplifier (PGIA) whose gain can be
changed in II binary weighted steps from I to 1024V i V.
The gain control is accomplished through a 4-bit TTL
input.

plus laser trimming minimized this change to a maximum
of±25m V with no external adjustments. With two simple
offset adjustments the change can be limited to less than
2mV (ImV typ) at the output over the entire IV/V to
1024V/V gain range.

The PGIA function allows the user to deal with wide
dynamic range sigrials while maintaining high ~ystem
resolution. For example: when used with a 10-bit A to D
converter in a "floating point" system. the 2'0 gain range
of the 3606, plus the 2'0 range of the converter produces a
total system resolution of 2'0 (II I ,OOO.OOQ: I).

A simplified schematic of the 3606 is shown in Figure I.
The circuit consists of a variable gain high input imped- _-"
ance voltage follower input stage (A I and A2) followed
by a unity gain difference amplifier (A3) with a variable
gain output stage (A4).
Common-mode voltage is derived for active guard drive
to improve system common-mode rejection. Two-pole.
low-pass filtering can easily be implemented on the
output stage to r<'duce noise bandwidth and improve
system signal-to-noise operation. A latch function is
provided to inhibit gain changes while the digital gain
control input is changed.

Desirable characteristics of a high performance instrumentation amplifier are offered by the 3606: high input
impedance (IOGn), excellent gain nonlinearity (0.0 Iri
max, G = 1024V/ V; 0.02'.:; max. G = I VI V). high
common-mode rejection (IOOdB min, G;:' 4V.'V). low
gain error (0.02';; max with no trimming required). low
gain temperature coefficient (IOpprn, "C max), and low
offset voltage drift vs temperature (Ill V, "c max. RTI. G
= 1024).

Burr- Brown's instrumentation grade monolithic operational amplifiers. high stahility precision thiI:t-film resistor
networks and advanced laser-trimming techniques are
used hy the 3606 to achieve a performance, size and cost
combinatioll never hefore achieved in a PG IA. It is
availahlc in a 32-pin dual-in-line package in either.
ceramic or metal (hermetic) configurations.

Added to these outstanding instrumentation amplifier
characteristics is the ability to change 3606's gain under
control of a 4-bit TTL input word. An important
characteristic of the 3606 PGIA is its low change in offset

+5 .

~

DIGITAL
+5

,
DIG
GND

DIGITAL
GROUND

+v

ANA
GND

~

~

ANALOG
+15V

ANALOG
GROUND

·v

cp

'ANALOG
-15V

20kn

10kn
IOkU

GAIN (

l

@}

101m

20
kn

10PTIONALiOFFSET

TRiMl
10kn

+ I N O - - -....

@
SAL

ICMVl

FIGURE I. Simplified Schematic.

2-53

14

TO SWITCHES

i

'SPECIFICATIONS
ELECTRICAL

Typical at +25~C. unless othe"rwise noted.

PARAMETER

CONOITIONS

MIN

"Am1
1

,.

TYP

MAX

±0.02
0.001
0.003
0.005
±5
±O.01

0.002
. 0.004
0.01
±10

I

' '36oea'"
MIN

I

ITYP

MAX

UNITS

GAIN,OI2J

Inaccuracy
Nonlinearity'S)

Drift vs Temperatwe
'IS Time

G =1 to 1024.10 = lmA
G = 1 to 16
G = 32 to 128
G = 256 to 1024
G = 1 to 1024
G = 1 to 1024

±a.05

±0.01

±a.02 .

%
%(5)

%
%
ppm/oC
%/1000 hr.

RATED OUTPUT

Voltage

10 =±SmA
Vo = ±10V

Current
Impedance

±12
±10
0·05

±10
±5

V
mA

' .

II

.'

INPUT CHARACTERISTICS

Absolute Max Voltage
Common-Mode Voltage Range

No damage

±Vcc

±10 .

Linear operation

±10.5

Differential Impedance

'011.3

Common·Mode Impedance

10113

..

V
V
lOOn !I pF
100!lll pF

±,O.OlG

. mV

OFFSET VOLTAGE, RTO'"

±'0.02G· ±,O.04G
+1,
+2,
.,±0.OO15G '±O.003G
;to.iJ3G2 1 ±O.OSG2'
.±O.OOlG
±0.01G2'
,±0.002G
±O.04G2'
±1
±2

Initial at +25°C Il51

'IS Temperature

-25°C to +85'C

vs Time

vs Supply

"sGain!81

With

mVl'C
mV/mo

mVN

,

trjmm~ng

INPUT BIAS CURRENT
Initial
'IS Temperature

±.O.02G
+21
,±0.0005G ,±O.OOlG
±0.01G2' ±O.02G2'
:+-11

mV

'.e,

.,

+25'C
-25'C to +85'C

±15
±O.3
±0.1

±50

±S

±20

nA
"Aloe
nAN

+25'C
-25'C io +85'C

±15
±O.S
±0.1

±50

±S

±20.

nA
nAI'C
nAN

vs Supply Voltage
INPUT DIFFERENCE CURRENT
Initial
VB Temperature

vs Supply Voltage
INPUT NOISE

-

Voltage
O.OlHz to 10Hz
10Hz to 1kHz

RSOURCE S 5kU

1.4
.1.0

G ,,1024

p.V. p-p
IJ.V,rms

Current

70

O.OlHz to 10Hz
10Hz to 1kHz

pA, pop
pA, rms

20

COMMON-MODE REJECTION

DC; lk!l Source Imbalance
G=1.2
G=4't06
G =32 to'1024
60Hz, lkll Source Imbalance
G=I,Z
G=4to16
G = 32 to 1024

80

90
100
114

80
90
100

86
96
106

90

100
1,0
114

90

100
110

dB
dB.
dB
dB
dB
dB

"

,

DYNAMIC RESPONSE

±3dB Response
G;=1
G =32 to 128
G = 256 to 1024
±1% Response
G=1
G =32 to 128
G =.256 to 1024
Slew Rate
Settling"Time
t01%
to 0.1%
toO.Ol%

100

kHz
kHz
kHz
kHz

Small Signal
100
40
10
SmaUSignal

G=1
G=128

0.2

40
8
3
0.5
75
100
200

2-54

,

,

'

.

.

kHz
kHz
kHz
V/p.sec
~sec

,usee
p.sec

ELECTRICAL (CO NT)
Typical at +25°C, unless otherwise noted.

I

PARAMETER
LOGIC VOLTAGES

I
I

CONDITIONS

"0" level'71

I

"1" Level l7l
Absolute Max
ANALOG SUPPLY
Rated Voltage
Voltage Range. Derated Performance
Current. quiescent
DIGITAL SUPPLY
Rated Voltage
Voltage Range
Current. quiescent
TEMPERATURE RANGE
Specification
Storage

I

No damage

3608A1t1
TYP

MIN

I

+2.4

I

I

0

+5.0

I
I

MAX

31068(1)
MIN

I

TYP

+0.4

I

I

+7

.'

I

1 I ml

I

J

I

MAX

I

I

L

I

I

+4.5

I

I

-25
-40

±10

I
I

+5

I

10

I

I

±20

I
I

+5.5

+85
+100

I

I

I

I
I

I

I

VDC
VDC
mA

VDC
VDC
mA

l

*Speciflcatlons S8me as 3606A.
NOTES:
1. Specify 3606AG or 3606BG for ceramic package and 3606AM or 3606BM for metal package-see below.
~G-~X.
.
3. Nonlinearity is the maximum peak deviation from the best straight·line as a percent 01 full scale
peak-te-peak output.

V
V
V

I

±t5

±8

UNITS

°C
·C

5. May be adjusted to zero.
6. Trimmed according to Figure 8.
7. All digital inputs are 1 TTL unit load.

4. RTO = Referred To Output. May be referred to input by dividing by gain G.

MECHANICAL
"G"PACKAGE

"M"PACKAGE

rr-'~
INCHES

DIM

MIN

MILLIMETERS

MIN

MAl(

·4.32
0.4&

5.84
0.53

~

,

2.54 BASIC
2.79

3.30

51TH B11111111111
)
-10-

-.I I.L --1 1-"
c

Loads',. !'"epos'!'O"W,!h,,, 0'0"

1 25rnrnl Rl!'MMCa'MI""op!lnl

OIM

INCHES
MAX
1.160

".

D

.."·
,
L ·············
R

MILLIMETERS
MIN
MAX

G

2.;;~

1008AS!C

-f- ~-~. ~~h-*L

.9008ASIC

22.868A.SIC

6.35

31oooooooooo • •

LEADS IN TAU!; POSITION WITHIN
.010" 1.25rnm1A II> MMe AT SEATING PLA.NE

o.~

P,nnumba •• ohown'Q ••• f.'ancao"lv.

m,v nO. t>e markad on pack.""

PIN DESIGNATIONS
PIN NO.

OESIG.

3
4
5
6
7

-V
-IN
J,
I None)
IJ
(None)
F
J2
R1

8
9
10
11
12
13
14
15
16

FUNCTION

-15V Analog SuPply
Inverting Input
Output of Ao
Optional A4 Offset Trim
Summing Junction of A4
Optional A4 Offset Trim
Low-Pass Filter Pin
Input toA.
Output Reference
0
Output
SenseG -1
S1
Sense G-4
S2
SenseG =2
S3
Output Reference
R2
ANAGND Analog Ground
INone)
No Internal Connection

2-55

PIN NO.

DESIG.

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

Do
0,
G
DIGGND
02

03
+5
INonel
(None)
Gain
Gain
(None)
+IN
+V
BAL}
BAL

FUNCTION
Digital Input, LSB
Digital Input, next LSB
Latch
Digital Ground
Digital Input, next MSB
Digital Input, MSB
+5 Digital Supply
No Internal Connection
No Internal Connection
Optional External Gain
Optional External Gain
Input CMV
Noninverting Input
+15V Analog Supply
Optional I nput Stage
Offset Null

TYPICAL PERFORMANCE; CURVES
Typical

a~

+25°C unless qtherwise noted.

SMALL SIGNAL
FREQUENCY RESPONSE

G l1024

60

Gl128

Iii

40

"c

100

,,

\1%
\

Gll

o
10

I

100

G=1

,-"

20

C)

~

'"

60

\

40

10k
lOOk
lk
Frequency (Hz I

1M

1

OUTPUT OFF$ET VOLTAGE
DRIFT VS GAIN

100

"l"-

G-16

\1\

G~16

'iii

COMMON-MODE REJECTION VS
SOURCE flESISTNACE IMBALANCE
120 DC (j • 32 to 1024

COMMON-MODE REJECTION
VS FREQUENCY
120 (j. 32t01024

10

100

~

"

100
lk
Frequency I Hz I

-_, 60HzG~32"... "1' to 1024: .........

.

60;;;"G-:;S"",
DC G ~
SOHz'G-!':;---- "":""'"

_

a: 80 r~-+---+--.::..t:_---i
~
' ...... "
.60r.---1---t---+---t

40~1--~3~.2~~-1~0~~~3~2~--~1~00

10k

Source Resistanc.e Imbalance I kO I

WARM-UP RESPONSE

OUTPUT OFFSET VOLTAGE GAIN

50

10

I

./
3606A

1

~ V-- ~

",--

t:/

3606B
INIJlAL""
" : ' T j USEi

o

0.001

1

16
64
Gain IV/V)

4

256

1024

TR~

16

.1

64

\
\-G=1024VIV
POWER
\
TURN-ON

--

256

GainlVNl

OUTPUT STAGE GAIN ERROR

I
/
I

G=1V~ "...;.

o

1024

I\..

o

'"

10
Timelminl

~

15

20

256

1024

OUTPUT STAGE GAIN NONLINEARITY

0.02 ...._-=V.:;:S~O;;.:U::.T:.:P~.U:.rT..;C::;U::;R.;;R.;;E~N.;.T;..._.,

0.Q1 ,.._...;.V;;S..;;O;.;U;.;T.;.P..;;U;.;T..;C;;.;U;;.;R.;;R.;;E;;N;.;T~_...

0.0151---+---11---1---1

#.
f:'
W

0.011---~+_--+_--......,

c
'iii
C)

0.005tiiiil==a:=::::~--i=--1
0

7.5
2.5
Output Current {mAl

0

10

WIDEBAND
• OUTPUT NOISE VS GAIN

10

30

2.5
7.5
Output Current (mAl

10

OUTPUT NOISE BANDWIDTH

4

S2

0

z

~

.1l.

s

(;

'0

z

~
:;

'.5

o

>

4

64
16
Gain (VIVI

256

1024

0

'.5

S

10

0_ 10

0
1

G=256.1000

,I
_+10

ill

ill

64
("/VI

STEP RESPONSE

~ 20

'0

16
Gain

RL =2kO
CL = 1000pF

~

E

~6

4

1

G=1024·
;; 8

"INCLUDES GAIN
SWITCHING TIME.

0

100
lk
Bandwidth (HZI

2-56

10k

0

20

60
Time III-sec)-

100 .

140

INSTALLATION AND
OPERATING INSTRUCTIONS
POWER SUPPLY CONNECTIONS
Figure 2 shows the proper analog and digital power
supply connections. The analog supplies should be
decoupled with I~F tantalum and 1000pF ceramic
capacitors as close to the amplifier as possible. Because
the amplifier is direct-coupled it must have a ground
return path for the bias currents associated with ihe
amplifier inputs at pins 2 and 29. If the ground return
path is not inherent in the signal source (tloating source)
it must be provided externally. The ground return
resistance (R(;R) should be kept as low as practical. An
upper limit of approximately 50M!l is established by the
input bias currents of the amplifier and its commonmode voltage.

ANAL06

COMMON

FIGURE 2. Power Supply and Ground Connections.

common-mode rejection ratio [CM R (in dB) = 20 log
CM RR(in V / V)]. Common-mode voltage shown as ECM
is actually the average of the two voltages appearing at
the two inputs (pins 29 and 2) with respect to pin 15 (V,
and V,).

GAIN SETTING
Gain is determined by a 4-bit digital word applied to the cc
input Do through·DJ (see Figure I). Pin 19 provides a
.Iatch function for the inputs. When pin 19 is a logic O. w'"
changes on the Do through D., inputs are inhibited. Pin 19
should be at +5V if the latch is not used.
A gain state truth table is shown in Table I. Gains are
determined by the resistor networks shown in Figure I.
For thc state OJ, 0, = 0, O. the input stage gain is a
function of the gain setting resistor R" connected between
pins 26 and 27. It: gains of I. 2 and 4 are desired. no
connection should be made to pins 26 and 27 and the
resistance across these pins should be kept high with
respect to 40k!l (> 400M!l).
Gain accuracy is established by laser-trimming the thimfilm resistor networks during assembly. No external. user
trimming is required.

i

OUTPUT OFFSET
Output offset may be varied by either of two methods
shown in Figure 4. Sources at pin 9 and pin 14 apply
voltages to the noninverting inputs of A. and A, respectively (see Figure I). Since the output stage gain occurs
after these points. the output voltage bias established
with VR , and VR , will vary with the output gain, G,.
Sources connected at pins 9 and 14 must have resistances
low with respect to 10k!} in order not to disturb gain
accuracy and common-mode rejection.

SIGNAL CONNECTIONS
Basic signal connections are shown in Figure 3. The
. connection to pin 14 completes the difference amplifier of
A, (see Figure I). The 3 to 8 jumper connects the output
stage. The pin 9 connection provides a divide-by-two
attenuator for the A. stage. This is necessary to limit the
signal on th~ output stage switches to maintain signal
linearity. The pin II. 12 and 13 connections to pin 10
close the feedback loop around A•.

FIGURE 4. Output Offsetting.

FIGURE 3. Basic Signal Connections.

LOW-PASS FILTER
For low frequency signals. system performance may be
improved by reducing noise bandwidth in the amplifier.
This may be accomplished with the addition of one or
two external 'capacitors as shown in Figure 5. C2 is
connected to a 10k/10k attenuator and C, is connected as
a feedback element across A4 (see Figures I and 5). The
transfer function is:

In the equation shown in Figure 3. G, is the input stage
gain and G, is the output stage gain. CM RR is. the

vo
V;:,

LOAD

2-57

[
=

10, 10'
1[
10 x 10'
]
IOOxlO"S(C,+330xI0'12')+20xIO'J 1+ lOx J(}'R,SC,+R,

TABLE I. Gain State Truth Table.
Digital' Inputs
(G~)
'(G,)
0, D, D"
0 ,0
0
0
0
0
0
I
0
0
I
0
I
I
0
0
I
0
0
0
0
i
0 ' I
,0
I
I
0
0
I
I
I
I
0
0
0
I
0
0
I
I
I
0
0
I
I
I
0
I
I
0
0
I
I
I
0
/,
I
I
0
I'
I
I
I
0,

,

G,
(A, and A,)
(Pins 2 & 29 to 3)
I

+ 40k

R,.

',4

G,
G,' G,

I'A.)

(Pin 8 to Pin 10)
I
2
4
4
I
2
4
4
I

32

256

2,
4
4
I
2
4
4

(R(,.

= 00)

I
2
4
4
.4
8
16
16
32
64
128
128
256
512
1024
1024

G, . G~
(R,.· "',;.,)
i(1 +40k,R,.)
2( I + 4Ok. R,.)
4(1 + 40k Rh)
4( I + 40k R,.)
4
8
16
16
32
64
128
128
256
512
/024
1024

*Rq connected between pins 26 and 27.

The first term is a first order filter. The second term is
morc complex, RI varies with the output stage gain-I.4k
for G, = 4 (see Figure I), The "I + ... " nature of the
transfer function prevents a true first order filter rolloff.
For most applications; the first order low-pass filter
obtained by C, provides sufficient filtering, The value C,
required for a desired cutoff frequency, (f, in Hz) is
obtained by the equation shown in Figure S.

Brown's 3329 will provide ±100mA output while Burr~
Brown's 3553 will supply ±200mA, When either booster
is placed inside the feedback loop as shown, the booster's
offset voltage produces no significant errors since it is
divided by the open-loop gain of the output stage.
GUARD DRIVE CONNECTIONS
Use of the guard drive connection shown in Figure 7 can
improve system common-mode rejection when the distributed capacitance of the input lines is significant. The

FIGURE S. Low-Pass Filter Connections.
LARGER OUTPUT CURRENT
The output current rating of the 3606 is a minimum of
±SmA. The linearity' of the gain is affected by output
current. See Typical Performance Curves. Optimum
linearity 'is achieved with In ,,;; ImA, 10 ,,;; SmA is
acceptable, Above SmA it may be desirable to use a
power or current booster as shown in Figure 6. Burr-

-

±l00mA TO

±2OOmA

FIGURE 6, Output Current Booster.

FIGURE 7. Guard Drive Connections.
common-mode voltage which appears,on the input lines
and on pins 29 and 2 is computed by the 3606 [(VI +
V2). 2] and appears at pin 28. It is. then fed back to the
shield so that the voltage across the distributed capacitances is minimized. This reduces the common-mode
current and i!TIproves common-mode rejection. The
operational amplifier in the voltage follower configuration is used III supply more current than can be
obtained from the 20k resistors conilec~ed internally to
pin 28 (see Figure I).
OFFSET TRIM
Offset.voltages of the 3606 are reduced by laser-trimming
during assembly. This reduces the initial offset voltage
and the offset voltage change with gain change to levels
that are acceptable for most applications. For more
critical applications the offset voltages can be externally

2-58

nulled to I.Cro. The following steps should be followed
(see Figure 8).

APPLICATIONS
A typical application of 3606 in a microcomputer based
data a~quisition system is'shown in the block diagram
below.
The purpose.of this system is to be able to acquire data
from a specific analog input channel. suitably condition it
(amplify it and convert it to digital form) and store it or
transmit it for further processing.
Initially the Microcomputer loads the RAM (random
access memory) with the required coding for various
desired gains via Data Bus. The coding associates the
gain state truth table for 3606 with eorresl'onding address
locations in the computer memory. So when the computer
puts out an instruction to multiplex a specific analog
input channel through the multiplexer via the Address
Bus, the RAM also receives the same address information
and puts out corresponding gain code to the PGIA 3606.
The 3606 amplifies the multiplexed signal by the programmed gain value, and outputs it to S, H (sample and
hold). The S, H holds the output value when,it receives
the control signal from the computer and the A D
converts it and outputs it to the computer via the Data
Bus under computer control.

OUTPUT
STAGE
TRIM

FIGURE 8. Optional Offset Trim.
I.
2.
3.
4.
5.

Adjust both R, and R, to mid-range.
Set the gain to minimum (I V V).
Adjust R, to make VOl'" eyual zero.
Set the gain to maximum (1024V V).
Adjust R, to make VOl I eyual/ero.

By using this techniyue, the change in output of.Tset
voltage caused by a gain change of I V V to 1024V V
rimy be reduced to. typically ImV instead of 10mV with
no external trimming. Trimming may cause the offset
\oltage drift \s temperature to' increase slightly.

The PGIA 3606 allows the system user to modily and
reprogram gain values for different analog input channels
merely by changing the software computer program.
Since different dedicated instruments are not required for
various input channels, the PGIA also saves space and
overall system costs.

DATA BUS
MICROCOMPUTER

r---

I

ADDRESS BUS

,---

I

~.---

r---"
ADDRESS

f----

CONTROL BUS

I

,
ANALOG INPUT
CHANNELS

'nr
RAM

~.

CONTROL
LOGIC

I

LATCH
ANALOG
MULTIPLEXER
MPC4D
MPCBS

,

~--'--

"

..... ....
I

/

PGIA " .......

FIGURE 9. Use of 3606 in Data Acquisition System.

2-59

~
SHC298

AID
CONVERTER
ADCBO

, BURR-BROWN®

3626

IESIElI

Low Drift
INSTRUMENTATION AMPLIFIER
FEATURES
- LOW VOLTAGE DRIFT @ LOW GAIN
2/lV/oC @ G= 5 (3626CP)
- LOW NOISE - 2/lV. pop

- HI.GH CMR - > BOdB @ G= 1000
-LOW COST
- ,SMALL SIZE - DIp· Package

DESCRIPTION
The 3626 is an integrated circuit instrumentation
amplifier designed for amplifying low level signals in
the presence of high common-mode voltages, Its low
drift. high input impedance (5 x IOYU). easy gain
adjustment (5V i V to 1000 V I V) and high commonmode rejection eliminate the problems and
compromises associated with using operational
amplifiers to realize the same'gain function.

The 3626 offers many benefits to the user for his
instrumentatio'n applications:

Compared to other integrated circuit instrumentation amplifiers it has the uriique feature of having low
vohage drift versus temperature ai low gains.

Small. dual-in-line package conserves board

L,ow voltage reduces temperature errors,
High common-mode rejection preserves system
accuracy.
High input impedance prevents errors due to
source loading and source impedance imbalance.

Laser-trim'med o'ffset requires no nUlling.

GAIN
, GAIN
REF

+IN

Inlernaliooal Airport Industrial Park· P.O. B.ox 11400· Tucson. Arizona 85734· Tel. 16021 746·1111· Twx: 910-952·1111 • Cable: BBRCORp· Telex: 66-8491

2-60

DISCUSSION

A simplified circuit diagram of the 3626 is shown in
Figure I. The circuit uses Burr-Brown's high
performance bipolar integrated circuit amplifiers and a
laser-trimmed thin-film resistor network. The excellent
initial matching and temperature tracking of these
components provide a level of performance difficult to
obtain with even expensive discrete amplifiers and
resistors. The gain accuracy. linearity. and temperature
coefficient are particularly attractive.

An instrumentation amplifier is basically a closed-loop
gain block that exhibits high input impedance and high
common-mode rejection. Instrumentation amplifiers are
committed devices with differential inputs and accurately
predictable input-to-output relationships - all necessary
feedback networks are contained in the circuit package.
These characteristics distinguish instrumentation
amplifiers from operational amplifiers - open-loop
devices whose closed-loop performance depends 1,1 pon
the external networks supplied by the user.

One of the most outstanding features of the 3626 is its low
voltage drift. especially at low and medium gains. Figure
2 shows the drift performance of the 3626 series
compared to monolithic integrated circuit
instrumentation amplifiers. The guaranteed voltage drift

[n instrumentation amplifiers. parameters such as input
and output impedances. frequency response. offset
voltage drift. and common-mode rejection are specified
for the closed-loop. committed configuration. One of the
few parameters that the user can vary is gain (by choosing
the external gain-setting resistor value). Another
important difference between an operational amplifier
and instrumentation amplifier is that the instrumentation
amplifier has no summingjunction available; you cannot
make a summing amplifier or integrator out of 'an
instrumentation amplifier.
[n the past f~w years. choices in instrumentation
amplifier designs have grown from a number of discrete
modular units to include monolithic and hybrid
integrated circuit versions which offer high performance
at lower cost - and in smaller packages. Monolithic
Integrated Circuits ([e's) were the first to break the price
and performance barrier. Hybrid IC's, such as the 3626.
are more expensive than monolithic [C's but they give
better performance for the money.

GAIN (VNI

FIGURE 2. Input Offset Drift vs Gain.
performance is almost two orders of magnitude better at
low gains.
The design of the 3626 is such that output biasing is easily
accomplished: See Figure 3 for proper connections. The
impedance of the reference source should be low
compared to 5kU. A current booster such as the 3329
(IOOmA) or 3553 (200mA) can conveniently be used with
the 3626 to increase its output current driving capability.
An application note. "Instrumentation Amplifiers"
(AN-75) is available which has information on the use of
instrumentation amplifiers. Contact your nearest sales
office or our factory in Tucson to obtain a copy.

Instrumentation amplifiers normally require at least one
extern'al resistor - the gain-setting resistor R".
Monolithic units usually require two additional - the
output feedback resistor and a resistor between feedback
common and ground. Since temperature coefficient
differences between these two resistors will cause output
offset voltage drift. they must be matched to meet the
desired drift specification. Hybrid units. such as the 3626.
have the advantage that all resistors except the gainsetting R" can be included in the package.
GAIN

1.25k

5kll

n

F[GURE I. Simplified Circuit Diagram.

FIGURE 3. Output Offsetting and Power Boosting.

2-61

SPECIFICATIONS

MECHANICAL
NOTE:

Lead,'in true position" within .010" {.26mm).R@MMC
at seating plane.
.
\

ELECTRteAL . , ' ,,' "

",Aj

• Sp~c.ific:ations typical at .25°C and ±15VOq. unless othe~wise n()it~Q.

I

MODELS

36268P

"

GAIN

3628CP

I

Gain Equation
Error from'
l
R~nge of Gain, min
Gain Temp'. Coefficient:
G=5
G= 10
G = 100
G = 1000
Nonlinearity, max 1%)12)

I

G = /; + j'10kIllRG)
1±0:25 - d:003GI%
5 to 1000

Equatiool l

2ppm/~C

±10,02 + 0,0003G)

OUTPUT
Rated Output, min
Output Impedance" G =100

I

25ppm/oC
, 35ppm/oC,
5Oppm/oC
±Io.ol + O,OOO3G)

I +10,01 +o.o003GI

~~".,
~noJl
["1'
[H

Pin numbe's shown tor reference only.
Numbers are no't markea on 'package.

........

H----,

±10V@±5mA
20

1 1 3

~

j

e I

14 13 12 II 10 $

INPUT OFFSET VOLTA\1E
Initial Offse,t. max(1)
VS. Temperature, 'max
v., Supply
VS. Time

68dB
74dB

A

74dB
SOdB

±IO',2 + IO,2iGllmV
±Il + (5/GiI~VloC

40~VIV

±50nA ! either input 1
±O.7nA/~C

±O,1nA/V
2~V, p-p
2J.AV, rms
,I,50pA, p-p
liOpA, rms

DYNAMIC RESPONSE
Small Signal, ±3dB Flatne.s:
G=5
G = 10

0
G

INCHES
MIN
MAX

MILLIMETERS
MIN

MAX

.790

.S10

20.07

20.67

.490

.510

1'2.45

12.95

.190

.260

.018

.021

.100 BASIC
.115',
,OSO
.130

.300

4,,!!;3
6.80
'0.63
0,'"
2.54 SASIC
2.03
2.92
3.30
·7.62

.,300 BA:SIC

7.62 SASIC

,OSO

2.03

.116

2.92

Row Spacing: 7.Smm 10.300"1
Weight: 3.4 grams 10012 oz,'
Connector: 0145MC 114-pin DIP,
Pin material and plating composition'
ct;:)nform to Method 2003 I solderability 1'
of MIL-STD-8S3,

PIN CONNECTIONS
t. GAIN
12, GAIN
~, I NO INToERNAL
13, -IN
3, f CONNECTION
14, +IN
4, Vos
5, Vos
6, -Vee
7, REF
8,'SENSE
9, OUT
10, +Vce
tl, NO INTERNAL CONNECTION'

400kl-\z
160kHz
14kHz
1.4kHz

G = 100
G '" 1000
Small Signal, ±1% Flatne.s:

TEMPERATURE 'RANGE
Specification~, min
Operation
'
Storage

±10,2 + (O,21GllmV
±13 + 15IG>I~V/oC

DIM

3~V/mo,

INPUT NOISE
Voltage, p-p, O,OIHz to 10Hz
rms, 10Hz to 10kHz
Current, p-p, 0,01 Hz to 10Hz
rms, 10Hz to 10kHz

POWER SUPPLY
Rated Voltage
Voltage Range
Quiescent Supply Current

5 x 1090113pF
±10V
with 1kU source unbalance
74dB
60dB

±10.4 + 10,41GilmV
±16 + 110/GiI~VloC

INPUT BIAS CURRENTS
Initial Bias Cuirent. max
vs. Temperature, max
VS, SupplY

G=5
G = 10
G = 100
G = 1000
Full Power, G = 5 to 100
Slew Rate, G = 5 to 100
Settling Time 10,1%>:
G =5
G= 10.
G= 100
G'·- 1000

~

.0 •• 0 ••

INPUT
Input Impedance, Dill, & CM,
Input Voltage Range. ""in "CMR, DC to 60Hz
G =5, min
G =10 to 1000, min

76kl-\z
27kHz
201kHz
250Hz
19kHz
1)IVI~sec

,

CONNECTION DIAGRAM

20~ ..c
30J,tsec
100}1sec
12ms'

±15VDC
±5VDC to ±20VDC
±7mAi max
-25°C to +85°C
-55°C to +125°C
-65°(; to +150°C

NOTES:
1. May be trimmed to zero.
2. Nonlinearity is the maximum peak deviation from the best stralgh.tline as a percent of ft,lll scale
. peak-to-peak output.
TRIM

2-62

TYPICAL PERFORMANCE CURVES
Typical @2SoCand:!:.15VDCpowersuppliesunlessotherwisenoted.

COMMON·MODE REJECTION
VS.FREaUENCY

CMR VS.SOURCE

IMPEDANCE UNBALANCE

100

G = 100.10001

16

&
Ii

I[

I

J

m 80

12

3!
I[

:;

8

G=5

' - G( 10

60
40

4

1k

~

'0

_.200

11

50

20
10

-fe

L10 J. ,Jo'kJ'f

0.

::

10

100

1k

"

~
;;

>

~

1k
10k lOOk
Source Resistance ISl)

',,~

f-rp°t"

Locus of +1%

..-

r-

~

:;
~

0

110;
10k 100k 1M
Frequency (Hz)

10M

0
-5

-10

tf
o

10

~-

..::'

-J:

"'1'"--..11

±.5V

r---.
5

1M

i 10 V

10

15

20

Output Current (mA)

SUPPLY CURRENT
VS COMMON-MODE INPUT

\

1/

N'

;;

>

f---

100

I

.

~=i1~\

10

STEP RESPONSE

~

LJ

-'..!.--k

15

0

100

v

20

&

~

./'
1
10

SATURATED OUTPUT VOLTAGE
VS OUTPUT CURRENT

10

V, ~
0.1

(n)

/

~

(n)

10
100
1k
10k lOOk
.. Common-mode Input Frequency (Hz)

100k

/

,

10

FREQUENCY RESPONSE
1000

1.0

32k

~e = , IOH. r~ fOk~Z1

::
a:

10k lOOk 1M·

Source Resistance

~100 ~ 50
Z

./

:;

--

.~ 2 0
o

/

z

I
10k

PEAK-TO·PEAK INPUT NOISE
VOLTAGE VS.SQURCE RESISTANCE

RMS INPUT NOISE VOLTAGE
VS SOU RCE RESISTANCE

E
,;

I
3.2k

Source Impedance Un?alance

Supply Vo!tage

=-

fCM "" 60Hz

_.

20 I-

Iii 100

--

I

tJ

\

G =5to 100
A L ' 2ka
_

CL

= 1.000pF
20

\

30
40
Time (,usec)

t2

50

_.-

---+--+--+--1

o

12
:1:4
16
±8
.!:10
Common-mode Voltage (V)

INSTALLATION AND OPERATING INSTRUCTIONS
SETTING THE GAIN
Figure 3 shows the normal operating connections for the
3626. The differential gain. G, is determined accordingto
the equation:

impedances), the circuit in Figure 4 may be used. In this
circuit, R, is added to intentionally imbalance the
inverting and noninverting gains of the amplifier. Rl is
then used to rebalance them, which overcomes the effects
of any residual CMR degradation due to source
impedance imbalance, etc. An iinprovement of
approximately 6 to'IOdB can be typically realized at low
gains.

where Ro is the resistor shown in Figure 4. This gain
equation is typically accurate to 0.25%. The temperature
coefficient of R" will directly affect the stability of G. For
high gains, R,; will be quite small (R" = Ion for G =
1000); thUS, the wiring impedance between pins 12 and 1
should be kept as low as possible. (Trimming of Ro will
eliminate the effects of wiring impedances so long as this
impedance is constant.) Also, note that V",. source needs
to be low impedance so as not to significantly affect the
gain equation.

COMMON-MODE REJECTION TRIM
The 3626 meets its C M R specifications without
additional trimming; however, for improved CMR 'in
special situations (such as imbalanced source

FIGURE 4. C0'!lmon-mode Rejection Trim.

2-63

BURFf-BROWN®

3627

IElElI

High Accuracy Unity-Gain
DIFFERENTIAL AMPLIFIER
FEATURES
• LOW COST
• EASY TO USE
• COMPLETELY SELF·CONTAINED
• HIGH ACCURACY
Gain Error. 0.005%
Nonlinearity. 0.0005%
CMR. 106118
• NO TRIMMING REQUIRED

DESCRIPTION
The 3627 is a high accuracy committed-gain differential amplifier. It consists of a ,high quality
monolithic operation amplifier. a low drift thin-film
re~istor network and laser-trimmed offset circuitry all inside a single integrated circuit package.
The fa,ct that the 3627 is completely self-contained in
a TO-99 package has several us\!r be~efits:
'The total performance is guaranteed as a single
component.
No gain adjustments are required.
No offset trimming is required.
The whole circuit, including the gain setting
resistors and offset trim circuitry, is protected by ,
the environmentally rugged hermetically sealed
package;
.
The total amplifier. function is very small in size
(0.108 square inches of a rea and 0.025 cubic inc/les
of volume).;
The 3627 is offered in two grades; the 3627 AM and
the 3627BM. They differ only in common-mode
rejection (94dB typ~ vs I06dB typ.) and offset voltage
, drift (15/0;' V1°C typo vs 1Oj.! V j"C typ.)
The 3627 Offers excellent total performance with no
fuss and a very-low total installed cost.
IntBrnatl!lllalAlrporllndualrlal Park - P.O. Box 11400· TucIDR. Arizona 85734 - Tel. (602) 746-1111- Twx: 910-952·1111 - Cable: BBHCOHP - Telex: 66-8491

2-64

DISCUSSION
OF PERFORMANCE
The 3627 is a new and unique approach to a widely
occurring problem - how to get excellent performance at a
low cost in a unity-gain differential amplifier circuit.
Burr-Brown's solution to this problem uses its wide range
of integrated circuit expertise; a high quality monolithic
amplifier, low drift high stability thin-film re'sistor
network and state-of-the-art laser-trimming techniques.
The result is a completely self-contained amplifier with
total guaranteed 25°C accuracy of less than ±O.O 15% .
(gain error, nonlinearity, offsets and common-mode
rejection).
The simplicity of the unity-gain differential amplifier
circuit may be deceiving when one considers an error
analysis. Consider, for example, gain and common-mode
rejection errors. The gain is determined by the ratio of R I
and R2 and the ratio of R3 and R4. The common-mode
rejection of the total circuit is a function of the CM R of
the operational amplifier and the matching of the resistors
R I to R3 and R2 to R4. Even if the operational amplifier
is perfect (infinite CMR), in order to guarantee 100dB
common-mode rejection would require resistor match of
approximately 0.0005% (5ppm).
This matching (and especially maintaining the match
over temperature) can be difficult and expensive to
achieve. Packaged matched and tracking resistor networks are available but they are fairly expensive
compared to the cost of the complete 3627 amplifier. Of
course, matching can be obtained by trimming or padding
some of the resistors, but this is difficult to do since each
resistor affects both gain accuracy and common-mode
rejection simultaneously. Unless care is used in choosing
UNITY·GAIN DIFFERENCE AMPliFIER

the trimming sequence a frustrating iterative trimming
process can be encountered.
With the 3627 these problems no longer exist for the user.
They are solved inside the package by Burr-Brown and
the user has a completely self-contained plug-in-and-go
amplifier to use. The excellent gain accuracy and
. common-mode rejection is obtained by using lasertrimming of a thin-film resistor network (R I through, ......
R4). The outstanding gain and common-mode rejection ~
temperature coefficients are a result ofthe excellent TCR CO)
tracking properties inherent in Burr-Brown's thin-film
resistor networks.
The offset voltage is also laser-trimmed to a very low
250!-'V, max., value (lOO!-,V, typical). This low value of
offset eliminates the need for external offset adjust
potentiometers which reduces cost and improves reliability.
The basic approach of the 3627 as a completely selfcontained amplifier has several cost saving implications.
It reduces design, purchasing and inventory cost. It
reduces labor costs because the gain setting resistors do
not require installation and adjustment. Also, no
potentiometers are required.
SENSE

,------fir"1 +VCC

>---_.fi'I

OUT

,.............

' - - - - - - . f i ' I 'Vee
REF

FIGURE I. Simplified Circuit Diagram.
VARIABLE·GAIN DIFFERENTIAL AMPLIFIER

AI25k1l1

2likn ±O.D2%

HIGH. INPUT IMPEDANCE. VARIABLE·GAIN,INSTRUMENTATION AMPLIFIER

282

eo =II + 1'j J 1'2' III

DIFFERENTIAL IN • DIFFERENTIAL OUT AMPLIFIER

lin = lOMe

2-65

SPECIFICATIONS
ELECTRICAL
'Specifications at TA '" +2SoC

MECt;lANICAL
~nd

~DELS,'<

GA1N
Gain Equation
Gain Error
Gain Nonlin"arity(2)
Gain Temp. Coefficient, max
Gain Temp. CQefficient, typ
OUTPUT
Rated Output, min
Rated Output, typ
Output Impedance

3627AM

'I

DYNAMIC RESPONSE
Small Signal, ±1% Flatness
Sma" Signal, ±3dB Flatness
Full Power Bandwidth
Slew Aate
Settling Time, 0.1% 1±10mV,
Settling Time, 0:01% 1±1mVi'
POWER SUPPLY,
Rated'Voltage
Voltage Range
Quiescent supply Current

,',

<

±10Vat±SmA
±12Vat±10mA
0.0111
,I
SOkll
50kll

Common~mode

Input Voltage Range,
Differential
Common-mode
Common-mode Rejection, DC to 60Hz
CMR. at2S0C
CMR. -25°C to +8SoC

:i627eM

G :-1VIV(1)
±O,01%, max 1±O.ooS% typ,
±O.o01%, max 1±O.OOOS% tYPI
±O.ooOS%IOC ISppm/oC,
±O.0002%IOC 12ppmfOC,

INPUT
Input Impedance
DifferEmUsl

OFFSET AND NOISE
Offset Voltage, RTOI4I1S)
at2S0C
vs Temperature, IlV/oC
vs Supply
vs Time
Noise Voltage, RTOI4I1S)
0.01 Hz to 10Hi
10HZ to 100Hz

TO.~99

±1SVDC' power supply unless otherwise noted,

I
±20V
±20V
90dB, min I 94dB, typ,
8OdB, min ,godB, typ,

I

l00dB', min, 106dB. tYPI '
86dB. min '94dB, typ"

"NO'TE
leads l'n. true POSition .... 'tt'lm 0·10"
@I MMC at sea tong plane

,

I.'

2SOpV, mal< (100pV, typ)
30. max 11S, typ,
I 20, max 110, typ'
20"VlV

(.251"(lmf A

".JNct~ES: •.

OIM

MAX

MIN

.335 .

.31'0

8.51.

9.40

8

.305

.;3;35"

7,75' .

8.s1

,C

,165
.016
.. 0;0

,185,

.021

4·19
0.41

4.70
0.53

,040
,040

0.25
0.25

" 02

A

20"V/mo

I
2"V. p-p
1,S"V, rms

0
E

.010
G

.200 BA'SIC

SkHz min 18kHz. typ'
0.8MHz,min ,1.2MHz. tYPI
14kHz min 118kHz, typ'
0.6V1"secmin IW/"sec, typ,

J'

20~sec

M

'4!.1° BASIC

SO"sec

N

'.095

±1SVDC
±5VOC to ±18VOC
±2mA

MILLIMETERS

MIN

1.02

5.08 BASIC

.028

,034

0.71

.02g.

.045

0.74

,160

2.79

.SOO

:,,0

MAX

0.86
1.14

12.7

.10S'

4,08

45° BASIC
2.41

2.67

Pin matenal ana platmg"compostion conform to
method 2003 ,solderability' of MIL-STO-883
'except paragraph 3.21. '

TEMPERA~RERANGE
I specifications, !T1in

Operation
Storage

'

-2S°(; to +85°(;
-55°C to +12SoC
-65°C to +lSOoC

CONNECTION DIAGRAM

NOTES:
1. Connected as unity~gain amplifier. Several other cOnfigurations are Rossible. See t~e
figures in Discussion and Typical Applications .
. 2. Nonlinearity is the maximum peak devi~tion from the best. str~jghtline as a percent
of full scale peak-to-p~k output.
'
3. With zero source impedance unbalance.
4. Referred to ou,put in unity ..gain d,ifference configuration. Notethatthis circuit has a
gain of 2 for the operational amplifiers offset voltage and noise voltage.
S. Includes effects of amplifiers' input bias currents.
6.,lncludes effects of ~rflpliflers' input current noise.

'ITOPVIEWI
TAB

,-IN

-Vee

See Figure 1 for circuit diagram,

2-66

TYPICAL PERFORMANCE CURVES
Specifications at TA

= +25°C and ±15VDC pow~r supply unless otherwise noted.

INPUT RANGE FOR
LINEAR RESPONSE

GAIN ERROR
VS FREQUENCY

-110
3dB

>
~

151----+--+-

"5
Q.
E.

10

e

w

II:

1%

.~ 0.1%

(!l

0.01%

°O~-5~--1~0~~15~~2~O--~
Supply Voltage

I

V

::;
()

100 2001k

,V,

.,

!!10

+5

Cl

>
:;
B~

0

I

/

0
-5

-10

\

/
o

/
10

cii

"."

\

'

(!l

10k

lOOk

1M

30

40

I\BM

\ \

-80

AM

100

1\'

lk

'""'-10k

lOOk

Frequency / Hz I

Frequency i Hz I

SMALL SIGNAL GAIN VS FREQUENCY

MAXIMUM OUTPUT VOLTAGE
VS OUTPUT CURRENT

3dB

20

0
-2
-4

~

.,

0>

S
>

~

'0

-8
-10

:;
B~

0

,,,-

20

~

-60
10

10M

~

Time

-90

........

-70

1%
.+10

Oi

"
II:

V
0.001%

STEP RESPONSE

~

-100

V

'I'

.

io---

.",-

10%

COMMON-MOOE REJECTION
VS FREQUENCY

-2~00L---1J..k---l-!:Ok,----1",0""Ok,----:IJ.,M,-L...J
l OM

50

(~seci

Frequency I Hz I

TYPICAL APPLICATIONS
HIGH ACCURACY, lOW DRIFllOW OFFSET· UNIT GAIN INVERTER

'0

= 18Z· 011

ACCURACY 0.01%
LINEARITY 0.001%
OFFSn < 250~V
AT OUTPUT
OFFSET DRIFT
< 2O~V/·C AT
OUTPUT

at 10V and lOOmA with 3329
atlOVand ZOOmA with 3553

NONINVERTING SUMMER

2-67

BURR-BROWN ®

3629

':1 ElE5I 1

Low Drift
I-NSTRUMENTATION AMPLIFIER
FEATURES

APPLICATIONS

• VERY-LOW VOLTAGE DRIFT
o.75!"V/oC

• SIGNAL CONDITIONING FOR PROCESS
CONTROL AND DATA ACQUISITION

• HIGH CMR - BBdB at 60Hz
• LOW NOISE - 1.2!"V. POp

• TRANSDUCER AMPLIFIERS FOR:
Thermocouples
Load Cells
Strain Gage Bridges

• SMALL SIZE - DIP Package

• MULTIPLEXER BUFFERS

• LOW BII\S CURRENT - 20mA

DESCRIPTION
Offering very-low voltage drift versus temperaiure
even at low gaihs. the 3629 meets critical
instrumentation requirements when amplifying lowlevel signals in the presence of high common-mode
voltages. This precision integrated circuit instrumentation amplifier offers low bias current and high
input impedance (IO'''n). A single resis\.or sets gain
from 5V V to IOOOV V.

Low voltage drift to rt!duce temperature errors
High common-mode rejection to preserve .syste,m
accuracy
High input impedance to minimi/e errors caused
by source loading and source impedance
imbalance
Small. dual-in-line plastic or hermetically scaled
• nietul package to conserve board space
Laser-trimmed offset to eliminate nulling

The 3629 exceeds the performance of other Ie
instrumentation amplifiers and offers many benefits
for instrum.::ntation applications:

Usc the 3629 to eliminate probkms and compromises
that arise when attempting to use operational
amplifiers to achieve the same gain function.

84
83
'--.......VI4,."..--t-----'V'~-QSENSE

82
8EFo--J~""'-""'----~N_--'

> - - - " " " 0 OUT

4No-------\

+INo----------------------....
International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734 - Tel. 16021 746-1111 - Twx: 910-952-1111 - Cable: BBRCORP - Talex: 66-8491

2-68

SPECIFICATIONS
ELECTRICAL
Specifications tYPIcal at 25°C with :t15VDC

po~er supply unless otherwise noted.

MODEL

I

Min

3629AP, 3629AM
Typ

I

Max

'2OkIR~'

1000

I

I

3629BP, 3629BM, 3629SM
Typ
Max

Min

I

I

Min

3629CP, 3629CM
Typ

I

I

UNITS
Max

III

~~~--------------~--------~-------L------~--------L-------~-------L------~--------L-------~--w-v---I
~
GAIN
Range of Gam
Gam Equation
Error From Equation, DC
Gam Temp. CoeffiCient
G~ 5
G;"' 10

J:

5+

G '" 100
G '- 1000
Nonlinearity. DC
t

RATED OUTPUT
Voltage
Current
0L!tput Impedance G = ,00

VIV

1"

12
20
25

25
45
50

t 0.002
10-5G

+ 2 x 10-5G.

ppmloe
ppmloe
ppmloe
ppmloe

±,O.OOS

tlO.OOl
1'10-sG

1,0003

::tIO.OCt

T 10-5Q,

+ to-sG,

:>::10

+12.5

V

~10

tt25
0.01

mA
11

INPUT OFFSET VOLTAGE
10001al Offset at 25°C
vs Temperature
vs Supply
vsTime

:tID :t, l00/G . :t25 :t. 200/G I

.!25 .!: 200/G· z:50 ±,4QOJG·

:!:1.5 ±,7.S/G,

.t3 :1:·10/G

±10 ±, 100/G, ±25 ±,200/G,
:to.75 ±15/G

10

:rO.4

INPUT BIAS CURRENT
Initial Bias Current, each input
vs Temperature
\IS Supply
Imtlal Offset Current
vs Temperature

:tIS
,030

:to.t
:!15
::to.6

INPUT IMPEDANCE
Differential
Commonwmode
INPUT VOLTAGE RANGE
Range
Ct.tR w/lkH Source Imbalance
DC,G::. 5
G:. 10
G '" 100 to 1000
60Hz All Gains

±35
.:to.60

:to.2
'SO

"tID

±25

'5

,20

::tl0

~30

"

:t20

:tl.2

jJ.V
jJ.V/oC
IJ,VIV
IJ.V/mo
nA
nAloe
nAIV
nA
nAtoe

10 'I 3
10 Ii 3

GU II pF
Gn lI·pF

=10

V

100
106
110

10'
110
120
92

dB
dB
dB
dB

1.2
1.0
70
20

p.V, p.p
IJ,V, rrns
pA, pop
pA,.rms

88

INPUT NOISE
Vo!tage, pwp, 0.01 Hz to 10Hz
rms. 10Hz to 1.0kHz
Current, pwp, O.OlHz to 10Hz
rms. 10Hz to 1.0kHz
DYNAMIC RESPONSE
SmaU Signa!, ::t3dB Flatness,
G .~ 5

G

~

1000

Small SignaL
G ~ 5'

~1%

I

90
60
30
3.5

G '" 10
G:o lOa

kHz
kHz
kHz
kOiz

Flatness.

G:. 10
'0'-' 100
0"" 1000
Full Power. G :. 5 to 100
Slew Rate. G '" 5 to 100
Settftng Time 01%10.01%
G" 5
G "" 100
G· 1000
POWER SUPPLY
Rated Voltage
Voltage Range
Current, QUiescent

0.2

I

TEMPERATURE RANGE
Specification l2J,
Operation
Storage

k~z

72
3.8
0.33
30
7.5
0.45

kHz
kHz
Hz
kHz
VllJ,sec

35/40

jJsec

85/120

.sec

350/400

.1:'S8C

±15

"
-25
-55
-65

,5

~
CO)

~~~

±20
,7

mA

+85
+125
+150

·C
·C
·C

·Speciflcations same as for 3629AP, AM.
NOTES:
1. See Typical Performance Curves.
2. ·55°C to +12S"'C for 3629SM.

2-69

MECHANICAL

r-i= J'

METAL CAN PACKAGE

g

Order Number:
3629AP
3629E1P
362QCP

3629AM
3629BM
3629CM
'3629SM

A

L

PLASTIC PACKAGE

Order Number:

WEIGHT: 4,1 grams
MATING CONNECTOR: 0145MC

IT ~.;:,:::;;::
. . "'"'-.
..

OO"""p," ,

8L'~I:"

INCHES

DIM

•

LJ r"
• II 0

it

0 • 0:

~ ~ .; 0 (.
.

a:

t ~OW"

MIN

MAX

~

.880

,"90
.170

',510

.016

12.45

INCHES
MIN
MAX
.810

20.07

.4"

.610

12>4!S"

Plnnl,lmberS
:lhownfO'

2.54 BASIC

2.92

3.94

N ... mber~.,e

.150

.300

3.81

7.62

nOl marked

.lOO 8ASIC

T.62.8ASIC

On package

,06.

2.03

referlll'lc:eonty .

not marked
on pack a"".

3.05

CONNECTION DIAGRAM
+vcc

.()21
.018
,100 BASIC

.06 •
. 115
,300
.130
.300 BASIC

2,03
2.92
3.30
1.82
1.62 BASIC

,080

2.03

INSTALLATION AND
OPERATING INSTRUCTIONS
OFFSET VOLTAGE ADJUSTMENT
I nitial offset of the 3629 is trimmed to a very-low value
during production, In most applications further nulling
will not be required, If it is necessary to null offset to the
lowest possible value, a low cost single turn potentiometer can be connected between pins 4 and 5 as shown in
the Connection Diagram, Drift changes 0.33/lV ('C for
each 100/l V of offset voltage nulled, Due to second order'
effects, the point of minimum offset drift does nOt occur
at the point of zero offset voltage in approximately 25%
of the cases, I n these instances nulling the offset voltage
may cause a slight increase in voltage drift.
A following stage should be used if large system offsets
must be nulled, This method results in the lowest possible

.HS

2.92

drift, In the circuit shown in Figure L the offset
component of VOl' due toV, is (V,R,) R" Resistors R,
through R, are selected to provide system scaling and to
make the offset component of Vo ,", due to V, cancel the
component of VOlt due to VI,

FIGURE L Multistage Amplifier For Offset :\ull and
High Frequency Filtering,

·Optional
Olfset Trim

-Vcc

R'

~.57

t2.95
4.83
5.33
.,46
0.53
2.54 BASIC

.210

0.53

.021
,155

MILL.IMETERS
MIN
MAX

.790

6.35

.115

reference onl y

DIM

22.35

.250

.100 BASIC
'"

MIL.LlMETERS
MIN
MAX

NOISE
The 3629 offers very-low noise at low and midfrequencies, See specifications and performance curves, .
At frequencies above 100kHz. noise increases and may
cause errors if the following circuitry responds to higher
frequencies, When high fre,quency noise must be reduced,
a low-pass filter .should be installed in a stage following
the 3629, Figures I and 2 illustrate two high frequency
filtering lipproaches~

-I -

>....,I-"N'It-.-""~....

-::"

~,

Following
Part 01

System

Low~pas~ Filter

FIGURE 2, High Frequency Filter For Single Stage
Amplifier.

2-70

TYPICAL PERFORMANCE CURVES

!1l

32

1000

c.
.2

~

II

."

~

II:

'0 10.0 - _ .. -_ ..

z

~
g

i

E
E

3.2

8
1.0!;:=±=:::::~~~~~
100
1k
1M
Source Resistance,

',L--~~~--_'~OO~--~~--~'Ok
Source Resistance Imbalance

(1,

In.

Gain IVIV,

FREQUENCY RESPONSE

-'.5,-,.-,----,;---,---,
,ool==~,

601--""""1-,

~
II:

:;

---rr----

g

w

c
~ -0.5

80

~

()

I

--t+
I

'K

20

=

Error from Gain Equation
-0.00075G tIO.OS :to.OOO25G,

 Vout

Load

FIGU RE 7. 3629 Used in a Transducer Application.

2-73

3630

BURR -BROWN@

IElElI

Very High Accuracy
INSTRUMENTATION AMPLIFIER
FEATURES

APPLICATIONS

• ULTRA LOW VOLTAGE DRIFT· 0.25uV/OC

• AMPLIFICATION OF SIGNALS
FROM SOURCES SUCH AS:

• LOW BIAS CURRENT· 20nA
• LOW NOISE . 1.2ull p.p

Strain Gages
Thermocouples
RTDs

• HIGH INPUT IMPEDANCE· 10 x 109 0
• HIGH CMh • 106dB @ 60Hz

• REMOTE TRANSDUCERS

• LOW OFFSET VOLTAGE· 25J1V

• LOW LEVEL SIGNALS

• LOW NONLINEARITY· p.002%

DESCRIPTION
The 3630 is a high accuracy, multi-stage, integrated
circuit instrumentation amplifier designed for signal
conditioning requirements where very high
performance is desired.
A multi-stage design is used to provide excellent
\ specific1;ltions and maximum versatility at reasonable
cost. The input stage uses Purr-Brown's ultra-low
drift low noise monolithic operational amplifiers to
provide :outstanding input characteristics ..
All resistors are on a single network of Nichrome
deposited on silicon. This provides high initial
accuracy low TCR (temperature coefficient of
resistance) and TCR matching, and outstanding
stability as a function of time.

Stat~of-the-art laser-trimming techniques are used
for reduction of offset voltage, offset voltage drift
versus temperature, and for maximizing commonmode rejection.
In addition to providing an outstanding set of
specifications, the 3630 offers convenience and ease
of use in providing the following features: single
capacitor active low pass filtering; easy output
biasing (zero suppression and elevation); commonmode voltage generation for active guard drive;
conveniently increased output current capability.
The unit is packaged in an 18-prn metal hermetic
dual-in-line p~ckage which provides shielding, ease
of installation, and environmental ruggedness.

Inllrnllional Airport Industrial Park - P.O. Box 11400 ~ Tucaon. Arizona 85734· Tel. (602174&-1111 - Twx: 910-952-1111· Cable: BBReORp· Telex: 66·6491

2-74

DISCUSSION

INSTRUMENTATION AMPLIFIERS
Instrumentation amplifiers are closed loop gain blocks
whose committed circuitry accurately amplifies the
voltage applied to their inputs. They respond only to the
difference between the two input signals and exhibit
extremely high input impedance. both differentially and
common-mode. Feedback networks are packaged within
the amplifier module. Only one external gain setting
resistor must be added. An operational amplifier, on the
other hand, is an open loop, uncommitted device that
requires external networks to close the loop. While op
amps can be used to achieve the same basic function as
instrumentation amplifiers, it is difficult to reach the
same level of performance. Using op amps often leads ~o
design trade-otIs when it is necessary to amplify low-level
signals in the presence of common-mode voltages while
maintaining high input impedances.
THE 3630
A simplified schematic of the 3630 is shown in Figure I. It
is a three-stage device which provides all the desirable
characteristics of a premium performance
instrumentation amplifier. In addition, it has features not
normally found on integrated circuit instrumentation
amplifiers.
The input stage (AI and A2) consists of two of BurrBrown's premium grade high accuracy bipolar
operational amplifiers. They are connected in the
noninverting configuration to provide the high input
impedance (10 x 109(1) desirable in the instrumentation

amplifier function. The inherent low offset voltage and
low offset voltage drift versus temperature of these
amplifiers is improved even further by the state-of-the-art
laser-trimming techniques.
The second stage (A3) consists of a high quality
operational amplifier connected in a unity gain difference
",mplifier configuration. A critical part of this stage is the
matching of the four 10k ohm resistors which provide the
difference function. These resistors must be initially
well matched and the matching must be maintained over
temperature and time in order to maintain excellent
common-mode rejection. (The I06dB minimum at 60Hz
for gains greater than IOOV / V is a significant
improvement compared to most other integrated circuit
instrumentation amplifiers.)
A II of the resistors shown in Figure I are part of a singie
thin-film network of Nichrome deposited on a passivated
silicon substrate. The critical resistors are laser-trimmed
to provide the desired high gain accuracy and commonmode rejection. The single network approach provides
the excellent TCR (temperature coefficient of resistance)·
and TCR tracking desirable to provide gain accuracy and
common-mode rejection when the 3630 is operated over
wide temperature ranges.
The third stage (A4) of the 3630 adds a great deal of
versatility and convenience to the amplifier. Its use allows
easy implementation of active low pass filtering, output
offsetting, and additional ,gain generation. The pin
connections make the use of this stage optional but the
effects are included in electrical specifications.

r - - - -20kn - - - - - - - - - - - - - - - -:- -

----------,

Gain

10k 0

IOkll

IOkO

+IN
CMVSense

4 )------_-~__.

Output
Gain

Gain Sense

1 }-----.,

:

Offs"; Trim

+r .•'

SkO

I

L---@----4---~---0------ -FIGURE I. Simplified Schematic

2-75

I
6 _ _ _ _ _ _ _ ,. ________ JI

U,SING THE 3630
Figure 2 shows the simplest configuration of the ,3630:
The gain is set by the external resistor Ro with a gain
equation G = I + 40kj Ro. A low TCR resistor should be
used for Ro since it contributes directly to th~ gain
accuracy.
Pins '1,5, 14 arid 18 are accessible so that a four terminal
connection can be made to RG. (Pins I and 18 are the
. voltage sense terminals since no signal current flows into
the operational amplifiers' inputs;)This may be useful at
high gains where the value of Ro becomes small.

Figure 8 shows how the output stage may be used to
provide additional gain. If gains greater than looOV IV
are desired.ji is better to obtain them from the output
stage than the input stage due to the low values of Ro
requirt:d .(Ro~< 400 for (I + 40kl Ro) > 1000).

MECHANICAL

Ir

The optional offset null capability is shown in Figure 4,
The adjustment affects only theinput stage component of
the offset voltage. Thus, the Dull' condition will. be
disturbed when the gain is changed. Also; the input drift
will be effected by approximately O.33/LV
per lOO/LV
of input offset voltage nulled.
.
Output offsetting .('·~ero suppression" or "zero
elevation") may be more .easily accomplished with the
3630 than with most other IC instrumentation amplifiers.

27.2mm
(1.071

~

rC

~

12.6mm
(0.50

11-1

t==l'
TT,(0.

4.Smm

191

--ito- 0.46mm
(0.0IS1

Pin material and plating composition conform to Method 2003
(solderability) of Mil-Std-S83 (except paragraph 3.2).

+vcc

FIGURE 3. Mechanical Specifications

VOl"l

PIN DESIGNATIONS
I.
2.
3.
4.
5.
6.

FIGURE 2. Basic Connections

Gain Sense
Inverting Input
Negative Supply
Common-mode Voltage Sense
vain
Ground

7. Reference

8. Output of Al
9. Input to "10. Output
II. Sense
12. Summing J unction of ""

Figure. 5 shows how this is done. The use of the
noninverting input of the output stage means that CMR
of the second stage is hot disturbed and that any
convenient value of variable resistor can be used.
The output stage also allows active low pass filtering to be
implemented conveniently with a single capacitor. The
effect .this filtering has on rioise reduction can be seen in
the Typical Performancf" Curves.

13.
14.
I S.
16.

Positive Supply
Gain
Offset Trim
Offset Trim:
17. Noninvenil)8 Input
IS. Gain Sense

The input stage contains extra resistors for the
computation of input common-mode voltage. Figure 7
shows how this voltage, available at pin 4, can be used to
drive the shield of the input cable. Since the cable isdriveri
at the common-mode voltage the effects of distributed
capacitance is reduced and the AC system common-mode
. rejection may be improved. Amplifier A I is a buffet to
supply larger currents than can be supplied by the 20kO
resistors internally connected to pin 4.

2-76

ELECTRICAL S.PECIFICATIONS
Specifications typi,:al at 2S"C with -+15VDC power supply and in circuit of Figure 2 unless otherwise noted.

MODEL

3630AM

.
GAIN
Range of Gam
- Gain Equation
Error From Equation, DC

I
G

Gain Temp. Coefficient 411
G=I
G = 10
G = 100
G = 1000
Nonlinearity, DC

= I +40k/RG

1000

(±O.OS
±O.oooIG)

(±O.I
±O.0002G)

8

20
115
125.
'125

45
50

:I~~~)
~SO

CUrrent

Output Impedance
INPUT OFFSET VOLTAGE
Initial Offset at 25"C w
vs. Temperature
vs. Supply
vs. Time

Bias Current (each

IN~:r

10 x 10'
lOx 10'
±IO

±12

~.

106
110

106

IN~~~g~.O~~~ O.OlHz _ 10Hz
DYNAMIC
Small Signal, ±3dB Flatness.
G= I
G= 10
G = 100
G = 1000
Small Signal, ±I% Flatness,
G.=I
G=IO
G = 100
G = 1000
Full Power, G = I - 100
Slew Rate. G = I - 100
Settling Time (0. 1%)
G= I
G = 100
G = 1000
Settling Time (.01%)
G=S
G = 100
G = 1000

• C_MI"",_"I\ r.U~,E

~io:.~!on
NOTES;
I. With Ro TCR = 0 ppmj"C
·Specifications same as for 3630AM

··
··
·
··

I~S7~1~

±IO ±)ooIG

~'~/~

±30

±S

±20

·
···

20
10
I
200
7.5
O.S

·
···
··

··
···
·
·
···
··
··
·
·
··
··

·
. ±20
+14

+8S
+12S
+150

,. Trimmable to zero at anyone gain.

..

·
··
·

.

··
·

·· ·
·· ··
· ·

3. -SS"C to +12S"C for 3630SM.

2-77

~V

~Vj"C

nA
nAj"C
nAIV
nA
nA/"C

V

dB
dB
dB
~V

p-p "

pV rms

pA p-p
J'Arms

kHz
kHz
kHz
kHz

.

·

%ofp..p FS

~ II pF

·
··
·

·
···
··
··
·
·
··
·
·

ppm/"C
ppmj"C
ppm/"C
ppmj"C

IlV/V
IJ.V/mo

±IO

I 33

V/V
V/V
%

V
rnA
1I

±50

100
ISO
1000

:;~

··

!(~o09~)

±20

60
100
SOO

I
1-65

+i<.°·~~G)

···
·

±S

25
2.5

±8

··

···
·
·
··
··
··
·
··
·
··
·
··
·

±30

90

±S

··

·

(±O.OS
±o.oooIG)

±SO

±IS

RANGE

±IO ±loolG

90

p~~~: :O~~:'LY

~~~~~. ~;i~cent

··
·

ISO

! 0.2

:tri:::G)

·

(±O.02
±o.OOOOSG)

±IO

1.2
1.0
70
20

rms, 10Hz - I.OkHz
Current. P-P. O.OIHz - 10Hz
. r.ms-,- 10".-- LOkHz

· ·

+~.~.I'G). !(~OO!!~L

··

±12.S
±12.S
0.01

±IS
±0.3
±o.1
±IS
±O.S

vs. Temperature
vs. Supply
Initial Offset Current
vs .•.•mpera.ure

INPUT VOLTAGE RANGE
Range, Linear Response
CMR w/ Ikll Source Imbal.
DC to 60Hz. G = I
DC to 60Hz. G = 10
DC to 6OH':, G = 100 to 1000

···
·

±2S ±2oo1G ±SO ±400IG
±2 ±20jG
±(I + 20/G)
±(I + 20/G)

IN.PUT.B~AS ~URRENT input)
1001iai

·

(±O.O2
±o.OOOOSG)

'+J.°·I~~G)

R~TED

OUTPUT
Voltage

·

Units

3630CM

3630BM. 3630SM

kHz
kHz
kHz
Hz
kHz'
V/~sec
~sec

psec
~sec

~sec
~sec

iJSCC .

··
··
·

V
V
rnA
"C
"C
"C

I

=

fa

C")

TVPICALPERFORMANCE CURVES
, ..:\t 2.5"C and

','f>

'@:
...
C.

~
=
I
12'01a~!~~r~~T--l

0.01 r----.,..---.,.---~

00.-1

ti'

~

in circuit of Figure".2 unfess otherwise not~.

6OHzG=~

' .......
100
1

..--,-+__.....,¥-_---,~-I

O.0031-__

,

" "

100 - 1000_,-........
"""c--~
.............

6OHzG=~

'"'"«z

6OHzG-1

::;
~ 0.0011-...,;;:.:;;._. .~~~'--_ __I
6O~--~--~-~--~

z

<:

"

,o.00031:-_ _~-~~~_-~.
10
100
1000
GAIN (V/V)
GAIN NONLINEARITY ,VS GAIN

12.0

iii

~

z

,

<:

"

G-IO

GJI~'" ,~
J I%Error":\

4t)

G=IO

'

20

100
G= I

~
\

\

Gt

\

~

~

8.0
Balana:d
Source

u

'""'

1.0%

iii

100

Ik

10k

lOOk

60

1M

~

~

\

I

10

iii
'"
:!!

GAIN (V/V)
OUTPUT OFFSET DRIFT VS GAIN

G= 100, 1000

GJooo

60

E!::~=-~~~~--.J
10
100
1000

1.oL.. .
I

I
3.2
1.0
32
100
SOURCE RESISTANCE IMBALANCE (kO)
CMR VS SOURCE IMBLANCE

'"
'''"""
z
0

'"

<:

"
..01%'--.....1._ _....___1-_....

10
100
Ik
FREQUENCY (Hz)
CMR VS FREQUENCY

FREQUENCY (Hz)
GAIN VS fREQUENCY

1%

1.0

I.ok

100
Ik
l.ok
FREQUENCY (Hz)
GAIN ERROR '<;S FREQUENCY

lOOk

:;-

~

...l

~
!;;

!e

'"0

..
I:0

~
~

'"~

G= I

T" = 25"C

"'"~
6

4

/

I

\

\

J

............

«

..............

±8

:c
u
TIME (Minutes)
WARM-UP DRIFT VS TIME

+10

V

/

V

/

V

.0

c:

C,=.o

0-

>

'" '"

...l

'"0

'"
o
Z

fIl

CIl

..
GAIN (V/V). .
S.ETTLING TIME VS GAIN

g ..!!!!~!!~~~~~~~~J
R,=.o

10

100

1000

GAIN (V/V)
OUTPUT NOISE VS GAIN

2-78

15.0
25.0
TIME
STEP RESPONSE

350

.~

~
~

.~
~

~

~

:0
0I:0

~
~

0

5.0

"2t----t---'-----.Il/"'--'----I2'O "'"

z

5.0 I-

I:0

.0 I

...:::

!

!

'"

100 0

1000

I' \

G = 100

~

>

~~I'O~----r----r-~~--- ">~

100

d=IOOOI

-10 ~

!I5~---~_ _~-~--- 15.0

10

CI. - 10000f
R; = 2kO

I

.0
±S
±IO
±IS
±2.o
SUPPLY VOLTAGE. (Volts)
QUIESCENT CURRENT VS SUPPLY

~

~l

~.

I

10

~

~

S

0.0

0

10

100
Ik
FREQUENCY (Hz)
OUTPUT NOISE VS 3dB FREQUENCY

APPLICATIONS
+Vn

Optional Offset Null

-Vn

R = any convenient value

FIGURE 4. Optional Offset Null
I
Fp= - - - H,
2" CI' 104

+v{'("

FIGURE 5. Output Offsetting

Cr in farads

Shield

\
,-,--.,.-,

,

"

VOI"r(f)

VOl'" = (V, • V,)(I

+ 4Ok/R,,)[I/(1 + 2m 10' x Cd)

FIGURE 6. Active Low Pass Filtering

FIGURE 7. Use of Guard Drive

V,

>@'....-Vn("l

-V('('

You,

= (V, - Y,)(I'+ (40k/R•• l][lk + (R,/IOklj

FIGURE 9. Output Power Boosting

FIGURE 8. Additional Gain From Output Stage

2-79

VUI'T

2-80

ISOLATION AMPLIFIERS

WHAT IS AN ISOLATION AMPLIFIER?
An isolation amplifier is a device with the primary function of providing
ohmic isolation (break the ohmic continuity of electrical signal) between the
input signal/circuitry and the output of-the amplifiers. It usually consists of
an input operational amplifier or instrumentation amplifier followed by a
unity-gain isolation stage. The sole purpose ofthe unity-gain isolation stage
is to completely isolate the input from the output of the device. Ideally, the
ohmic continuity of the input signal is broken (at the isolation barrier) yet
accurate signal transfer without any attenuation is achieved across the
unity-gain isolation stage. An important feature of an isolation amplifier is
that it has a completely floating input which helps eliminate cumbersome
connections to source ground in several applications.
Figures 1 and 2 show typical isolation amplifier applications. The isolationmode voltage Viso is the voltage which exists across the isolation barrier. The
contribution bftheoutput referred error caused byViso is (Viso/IMRR) it Gain
where IMRR is the Isolation Mode Rejection Ratio. Vsig is the differential
input signal and Vem is the common-mode voltage. The "Leakage Current" is
the current which flows across the isolation barrier with some specified
isolation voltage applied between the input and the output.

CHARACTERISTICS ,OF
ISOLATION AMPLIFIERS
The folloWing is a discussion of some ofthe characteristics and terms unique
to isolation amplifiers.
Common-mode Voltage and Isolation Voltage - Some manufacturers (other
than Burr-Brown) treat common-mode voltage and isolation voltages
synonymously in describing the use and/or specifications of isolation
amplifiers. It is important to understand the significance of these terms and
the difference between them.
.
When the input common is grounded, the input signal Vd (see Figure 1) can
be floated by the amQunt Vem above the input ground. Vem is the common-

. 3-1

mode JOlt'age(GMV\"anq i~genera"y ±1 O'{li;;'i~ed b1ij,~ CMV ~a!irig of the
input stage amplifier. In applications involving' higher systems commonmode voltages, input common terminal is not grounded and the com~on
mode voltages are referenced across the isolation barrier to the output
common terminal.

ISOLATION'
VeM
BA~RIER
_
ERROR
,~

10

Ii;

veM ERROR VISO ERROR'
eMRR
IMRII"
.

I
I
I I +
Va =IV sls ' VeM ± VISO I Glln
eMRR
IMRR

Va =IISIS ± vIsa IMRIIl Rf
INPUT
COMMOI
"IMRR IN AMPS/VOLT

"IMRR IN VOLTS/VOLT

FIGURE 2. Typical Isolation Amplifier, Voltage
(Input) Mode,.

FIGURE'1. Typical Isolation Amplifier, CUrrent
(Input) Mode.

The isolation voltage Vise as shown in Figure 1 is the potential difference
between the input common and the output common terminals. The isolation
voltage rating describes the amount of voltage that the isolation barrier can
withstand without breakdown. This feature of the isolation amplifier allows
two distinct ground connections to be made when necessary. It allows tt'Je
isolation amplifier to be used in applications involving very-high commonmode voltages and in applications of breaking ground loops.
Many applications involve a large "system common;'lilode volfage." In such
.applications, the isolation amplifier's input common terminal is not connected toany,ground but the output common terminal is connected to the
system ground. In such a ease, the te.rm Vern shown in Figurf3s 1 and 2
becomes negligible and. Viso determines the safe limit for the system
common-mode voltflge.ln this manner, the isolation amplifier can accommodate common-mode voltages of 2000V or more.
Common-mode Rejection and Isolation Rejection - Isolation-mode rejection
(I M R) is another term which some other manufacturers refer to as commonmode rejection (CMR). The above discussion on the common-mode voltage,
and isolation voltage helps recognize the difference between CMR and the
IMR. The CMR is the measure of the input stage amplifier's ability to reject
common-mode input signals (common-mode with reference to the output
common) while transmitting the differential slg.nal across the isolat!.on
barrier. The isolation-mode rejection ratio (I MRR) is defined by the equation
shown in Figures 1 and 2. Thus, understanding the IMR capability.of
isolation amplifiers allows their meaningful use in applications requiring
very high common-mode rejection ratios such as100dB to140dB.
Isolation Voltage Ratings, Test Voltage -It 'is important to understand the
significance of the conti nuo'us derated isolation voltage specification and its
relationship to the actual test voltage applied to thlil unit. Since a "continuous" test is impractical in a product manufacturirigsitujition (implies
infinite test duration) it is generally accepted practice to perform a production test at a higher voltage (higher than the continuous rating) for some
shorter length of time.
.

3-2

The important consideration is then "what is the relationship between actual
test conditions and the continuous derated minimum specification?" There
are several rules of thumb used throughout the industry to establish this
relationship. For most isolation amplifiers, Burr-Brown has chosen a very
conservative one: Vtest = (2 x Vcontinuous rating) + 1000V. This relationship is
appropriate for c'onditions where the system transient voltages are not well
. defined: Where the real voltages are well defined or where the isolation
voltage is not continuous the user may chose to Lise a less conservative
derating to establish a specification from the test Voltage.

APPLICATIONS OF ISOLATION AMPLIFIERS
When one or more of the following conditions/requirements are present in
an application, an isolation amplifier would generally be the right choice as a
signal conditioning device: .
•

When ohmic isolation between the signal source and the output is a
requirement (isolation impedance between the input and the output>
10MO).

•

When excellent common-mode noise and voltage rejection is a requirement (CMR > 100dB).

•

When it is necessary to process signals in the presence of, or riding on,
high common-mode voitages (CMV ~ 10V).

In general, most applications can be broadly categorized into the following
four types:
•

Amplifying and measuring low level signals in the presence of high
common-mode Voltages.

•

Breaking ground loops and/or eliminating source ground connections.
The isolation amplifier provides full floating input, eliminating the need
for connections to source ground, and thus allows two-wire hook-up to
the signal sources.

•

Providing an interface between medical patient monitoring equipment
and the transducer/devices which may be in physical contact with the
patients. Such applications require high isolation voltage levels and verylow leakage currents.

•

Providing isolation protection to electronic instruments/equipment.
Large common-mode voltages occasionally cause hazardous electronic
faults. Low leakage c.urrents and high isolation voltage capability of
isolation amplifiers help protect instruments against damage caused by
such faults.

Isolation amplifier performance requirements vary significantly, depending
on the type of requirement. In applica1ionswhere bandwidth and speed of
response are more important than gain accuracy and linearity, the opticallycoupled amplifiers will be the best choice. For applications where gain
accuracy and linearity are key parameters, Burr-Brown's family of· transformer-coupled amplifiers are the suitable choice.

"Reference National Electrical Manufacturers Association (NEMA) Standards Parts
ICS 1-109 and ICS 1-1 n.

3-3

SELECTION' GU1DE
,

OMcripteon
LowOrift'"
LowB...

FET

-:M51

:M52

:M55

True3~wire

TRAN.SFORMER COUPl,.ED AMPLIFIERS
IsOlation

I.a.le'ion

Voltage (V)

-.Rojoction,min.

........

Pu_

Contin·

LHkage
Current
8fT...

-

l.alation

Olin

Impe-

Nonlinearity

.

Highest

Current
Input

IIIII.need .
FET Input
Low Drifl
Wide
88nc:lWldth

F.....

£xtIirMl
11O'_ion

T....p.
RInge

PNk

peek

(dB)

(dB)

(pI')

n

pF

Pockage

180

120

I

10"

I.

i"O.OO5 ·±0.0015

lOll

U

No

Com

Module

3-19

±500
,.2000

±2000
,.5000

120
120
120

I
1

10"

i"O.OO5
to.OO5
to.OOS .

lOll
lOll
lOll

No~

20pA

2.5
2.5
2.5

No'·

Com
Com
Com

_Ie

10"
10"

to.025
i"O.025
i"O.025

No

.,,"

16
16
I.

2SpA

.•.

180
180
180

3-19
3-19
3-1.

2+
(15OIGo)
1+
(7s/Go)

SOnA

2.5

No

Com

_ute

3-27

SOnA

2.5'

No

Com

lOOnA

30

No

Ind

----

Poge

±2000

sanA

'"

±500

DIP

3-41

1_

30

No

Ind

DIP

3-41

'"

:M58A

±2000

,.5000

180

130

2~

10"

14

1"0.02

to.Ol

34568

t2000

,.5000

180

130

25

10"

I.

to.06

i"O.03

_G

±3500

±8OOO

180

125

0.5

10"

6

±O.l

i"O.03

36568G

t3500

t8000

180

125

0.5

10"

8

to.OS

to.03

385IIHG

t3500

t8000

180

125

0.5

101.

8

to.15

to.03

3858JG

t3500

t8000

180

125

0.5

10"

8

to.l

i"O.03

3858KG

't3500

t8000

180

125

0.5

lO'l

•

i"O.1

to.03

3II5OHG
3880JG
3IIOKG
3850MG

t2000
t2000
t2000
t2000

t5000
t5OOO·
t5000
t5000

140
140
140
140

120
. 120
120
120

0.25'"
0.25'"
0.25'111
0.25'"

10"
10"
10"
10"

1.8
1.8

3882HG
3882JG
3882MG

t2000
±2000
t2000

t5000
t5000
t5000

140
140
140

120
120
120

0.25'"

10'1

0.25·'

to"

750
750
750

2500
2500
2500

,I....
1....

101'"
106"
'06"

ISO'OOAP
ISOtOO8P
ISOlOOCP

±3dB

_t

Vol",

±pYfOC

25+
(5OOIG,)
5+
(IOOOIG.)
200+
(IOOOIGo)
50+
(7501Go)
10+
(38OiG.)

OPTICALLY COUPLED AMPLIFIERS
llllIoneed

Cur-

80Hz

lsot.lion
Voltage

....

-.... -.

DC

typ .
('110)

In.trumen·
tation
Amplillef

voltage
Dri"n

T....

!NIX.
( )

....

kHz

10pA

,_

30

No

Com

DIP

3-41

lOOnA

30

No

Com

DIP

3-41

30

No

Com

DIP

3-41

15
IS
IS
15

Yoo
Y.
YOI
Y.
Y.
Y.
Y.
V.
Y.
Y.

Ind
Ind
Ind
Ind

DIP
DIP
DIP
DIP

3-33
3-311
3-33
3-33

Ind
Ind
Ind

DIP
DIP
DIP

3-33
3-33
3-33

Ind
Ind
Ind

DIP
DIP
DIP

3-8
3-8
3-8

,_
lDnA

1.8

i"O.OS
i"O.03
i"O.02
i"O.06

25.
10
5
100

i"O.2
to.l
i"O.2

to.OS.

50

25

SOiiA
SOnA

0.25'"

1.8
1.8
1.'

tOM

10"

i"O.OS

lOll

50nA

IS
IS
IS

0.3
0.3
0.3

10"
10"
10"

2.5
2.5
2.5

D.•
0:1
0.07

0.1
0.01
0.02

10'"

IDnA
lanA
lanA

80
80
80

......

3-27

lOOnA

i"O.2
i"O.1
i"O.OS
i"O.2

I .•

Aequi~

IDnA
lanA

NOTES: (1) Com = O·C tD +70·C; Ind = -25°C to +85·C. (2) Bipolar. (3) Isolation voltage tested at 25OOV. rma. 60Hz; leakage current
tested for 2pA max at 240V. rml. 60Hz. (4) ±15V at ±15mA isolated power available to power external circuitry. (5) At 24OVI6OHz. (6) RON
=; 10k. Gain =100.
•

3-4

GLOSSARY OF TERMS & DEFINITIONS
Isolation Amplifiers
barrier. It is the voltage or current that must be applied
to the input to force the output to zero when Visa is
present.
For voltage input mode:

ISOLATION AMPLIFIER
A device which provides ohmic isolation (breaks ohmic
continuity of an electric signal) between the input and
the output of the device. Method of coupling may be
thermal, magnetic, optical, or any means other than
,direct ohmic coupling. Such a device allows the input
circuit to be referenced separately and independent of
the output circuitry.

IMRR = Va e',,:o/G with Va = 0
For current input mode:
IMRR ,;"

ISOLATION BARRIER

A barrier or region between the input and the output
stage of an isolatiom amplifier, where the signal transfer
is achieved between the input and the output.

with Va

= 0 (10 = 0)

ISOLATION IMPEDANCE

ISOLATION VOLTAGE
The potential difference between the input stage common and output stage common terminals of an isolation
.
amplifier.

The effective impedance between the input common
terminal and the output common terminal. It is the
impedance of the isolation barrier. (It is usually specified
as a typical parameter. Leakage current is related to
isolation impedance and is usually specified with a maximum limit.)

ISOLATION VOLTAGE RATING
The amount of voltage that can be impressed between
the input common and the output common terminals
(across the isolation barriet) without resulting in breakdown.
LEAKAGE CURRENT

ISOLATION-MODE REJECTION (IMR)
The IMR is the measure of an isolation amplifier's ability to reject common-mode input signals (commonmode with reference to the output common), while
transmitting the differential signal across the isolation

The current that flows between the input common terminal and the output common terminal (across the isolation barrier) with a specified voltage applied across it. (It
is usually 100% tested and specified with a maximum
limit.)

3-5

BURR-BROWN@)

lS0100

IElElI

Miniature
Low Drift ··Wide Bandwidth
ISOLATION AMPLIFIER
FEATURES

APPLICATIONS

• EASY TO USE, SIMILAR TO AN OP AMP
VOUTIIIN '= RF, Current Input. .
VOUT/VII~ = RF/RIN" Voltage Input

• INDUSTRIAL PROCESS CONTROL
Transducer sensing
(thermocouple, RTD, pressure bridges)
4mA to 20mA loops
Motor and SCR control
Ground loop elimination

• 100% TESTED FOR BREAKDOWN
750V Continuous Isolation Voltage
• ULTRA-LOW LEAKAGE, D.3pA, max, at 240V/60Hz

• BIOMEDICAL MEASUREMENTS

• WIDE BANDWIDTH, 60kHz

• TEST EQUIPMENT

• LOW COST
.1B-PIN DIP PACKAGE

• DATA ACQUISITION
I'

DESCRIPTION
The ISO I00 is a miniature low cost optically-coupled
isolation amplifier. High accuracy, ,linearity, and
time-temperature stability are achieved by coupling
light from an LED back to the input (negative
feedback) as well as forward to the output. Optical
components are carefully matched and the amplifier
is actively laser-trimmed to assure excellent tracking
and low offset errors.
The circuit acts as a current-to-voltage converter
with a minimum of 750V (2500V test) between input
and output terminals. It also effectively breaks the
galvanic connection between input and output
commons as indicated by the ultra-low 60Hz leakage
current ofO.3/LA at 240V. Voltage input operation is
easily achieved by using one external resistor.

Designs using the ISOIOO are easily accomplished
with relatively few external components. Since V,,!'.,.
of the ISOI()() is simply liN ROUT, gains can be
. changed by altering one resistor value. I n addition,
the 150100 has sufficient- bandwidth (DC to 60kHz)
to amplify most industrial and test equipment signals.
IREFI a~CE

Versatility along with· outstanding DC and AC
performance provide excellent solutions to a variety
of challenging isolation probl~ms. For el!;ample, the
ISOIOO is capable of operating in many modes,
including: noninverting (unipolar and bipolar) and
inverting (unipolar and bipolar) configurations. Two
precision current sources are provided to accomplish
bipolar operation. Since these are not required for
unipolar operation, they are available for external
use (see Applications section).

·Vee -vee

RF

INPUT
COMMON

IRER B~CE

OUTPUT
COMMON

·Vce -Vee

Internallonal Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734- Tel. (602) 748·1111 . Twx: 91(J.952·111t • Cable: BBRCORp· Telex: 66-6491

3-6

SPECIFICATIONS
ELECTRICAL

-

At TA = +25°C and +Vcc = 15VDC unless otherwise noted
PARAMETER

I

I

CONDITIONS

MIN

IS0100AP
TYP
MAX

I

IS0100BP
MAX

I MIN I TYP

IS0100CP

I MINI TYPT MAXI UNITS

ISOLATION
. Voltage,
Ratad Continuous, AC peak or DC'"
TilSt Breakdown, AC peak or DC
Rejectionl') DC
AC
Impadance
Leakage Current

750

V
V
pAN
dB
pAN
dB
n iipF
",A,rms

2500

1Osee

5
146
400
108

R'N =10kl!., Gain = 100
60Hz, 480V, RF = 1Mil
R'N = 10kll, Gain = 100

;0'2 112.5

1

240V, rms, 60Hz

0.3

!i!a

OFFSET VOLTAGE (RTI)
Input Stage IVosll
Initial Offset
vs Temperature
vs Input Power Supplies

500
5
105

300
2

200

300
2

200
2

300

150

2

1

vs Time
Output Stage IVOSO)
Initial Offset
vs Temperature
vs Output Power Supplies
vs Time
Common-Mode Rejection Ratlo(2)

500
5
105
1
3

60Hz, RF = lMn
R'N = 10kll, Gain = 100

90
±10

Common-Mode Range

/lV
/lVioC
dB
/lVlkHr
/lV
/lVioC
dB
/lVIkI,ir
nAN
dB
V

REFERENCE CURRENT SOURCES
Magnitude
Nominal
vs Temperature
vs Power Supplies
Matching
Nominal
vs Temperature
vs Power Supplies
Compliance Voltage
Output Resistance

10.5

12
0.3

12.5
300
3

nA
ppm/oC
nAN
V

50
150
0.3
+15

-10

/lA
ppm/oC
nAN

2 x 1()9

II

60
5
0.31
100

kHz
kHz
VI/lsec
/lsec

FREQUENCY RESPONSE
Small Signal Bandwidth
Full Power Bandwidth
Slew Rate
Settling Time

Gain = WI/lA
Gain = lVi/lA, Vo = ±10V
0.22
0.1%

TEMPERATURE RANGE
-25
-40
-55

Specification
Operating
Storage

+85
+100
+100

°C
°C
°C

UNIPOLAR OPERATION.
GENERAL PARAMETERS
Input Current Range
Linear Operation
Without Damage
Input Impedance
Output Voltage Swing
Output Impedance
GAIN
Initial Error, AdjustableToZero

,
-0.02
+1

-20
-1

/lA
mA

0

0.1
RL = 2kll, RF = lMO
DC, open-loop

-10

V
n

0
1200

Vo = RF IIIN)

vs Temperature
vsTime ,
Nonllnearityl31
CURRENT NOISE
O.OIHz to 10Hz
10Hz
100Hz
1kHz

-=

8

2
0.03
0.05

5
0.07

1
0.01

2
0.05

1
0.005

2
0.03

0 .1

0.4

0.03

0.1

0.02

0.07

1

%FS
%fOC
%/kHr
%

I'N=0.2/lA
pA, p-p
pAly'Hz
pA/y'Hz
pAly'Hz

20
1
0.7
0.65

INPUT OFFSET CURRENT (lOS)
Initial Offset
vs Temperature
vSPower Supplies

1
0.05
0.1
100

vs Time

3-7

10

nA
nAlOC
nAN
pA/kHr

ELECTRICAL (CONT)
"

PARAMETER

IS0100AP
TVP
MAl!
~IN

CONDInONS

POWER SU"....IES
", Input:Stage ,
Voltage (rated performance I
Voltage (derated performance,
Supply Current
'

IS0100BP
,MIN TVP M~

ISOfOOCP

-:MDT

-m- -.oor

,UNI1S

"

±15
±7
IIN=-0,02I'A
hN'=-2OI'A

butput Stage
Voltage (rated performance I
Voltage (derated performance I
Supply Current
Short Circuit current Limit

,..

.

±18
±1.1

±2

+8.-1.1 +13.,-2

.

"

'V
V
mA
mA

±40

V
V
mA
mA

+10
+1

mA

±15
±7

±18
±1.1

Vo=O

±2

BIPOLAR OPERATION
GENEAALPAAAMETERS
Input Current Range
Lil"!e8r Operation
Without Damage
Input Impedance
Output Vo~age Swing
Output Impedance
GAIN
Initial Errc;:>r (Adjustable

-10
-1

~

.

0.1

RL = 2k": RF = 1MO

+10

-10

"

V
0

1200
VO=RF

To Zero I

jhN~

2
0,03
0-05
0,1

vs Temperature
vs Time
Nonlinearity (31
CURRENT NOISE
0,01Hz to 10Hz
10Hz
100Hz
1kHz

5
0.07

1
0,01

2
0,05

1
0,005

2
0.03

0.4

~.03

0.1

0.02'

0.07

ItN=0.2I'A

nA. pop
pA/v'Hz

1,5
17
7

40

20

200
3
0.7

vs Temperature
vs Power Supp!ies
YB Time

pM/Hz

.'

6

INPUT OFFSET CURRENT Ilos. bipolar/("'
Ini.!lal Offset

pA/v'Hz
10

70
2

35
1

250

POWER SUPPLIE,S
Input Stage
Vo~age (rated performance'
Vo~age (derated performance I
Supply Current

±15
±7
+2.-1'.1
+8. -1,1

liN = +1OI'A
hN =-10"A

'Output Stage
Vo~age (rated performance I
Vo~age (derated performancel
Supply Current
Short Circuit Current Limit

±1.1

Vo =0

nA
nAl"C
nAN
pA/kHr

V
-V
mA
mA

..

±Hi
+3.-2
+13.-2

.,

±1S
±7

%OfFS
%I"C
%lkHr
%

±18
±2
±40

,.

V
V
mA
mA

• Same as IS01ooAP.
NOTES:
1. See Typical Performance Curves for temperature effecta.
2. See Theory of Operation section for definitions. For dB see Ex. 2, eM and HV errors.
3:'Nonlin~arity is the peak deviation from a "best flt'~ straight line exp~essed as a percent of full scale output,
4. Bipolar offset current includes'effects of ~eference current mismatch and unipOlar offset current.

MECHANICAL

.

"N .,
INCHES

D

j,L

PIN CONFIGURATION

~~~----~~~~~--------~--~

MlLLItv1Et~RS

INPUT COMMON "
"U

'l.9S

,'~

".13

.01'
,OO.""C

'"

2.501'010$1(:

'"

UtI

:lOO.MIC

?~ilAII'e

'"

,~

t

NC·

2

+VCCA.

3

VOUT

4

-VCCA2

2.lr.I

,,,

, BAL

NOTE
Leads i" true poSl110n wIthin

o 111' O.255mm R al
seating plane

.

I.

Pin numbers shown for
reler&nceonly.
Numbers not marked
on package

.

+VccA,
OUTPUT COMMON
'NO INTERNAL CONNECTION

3..8

ABSOLUTE MAXIMUM RATINGS
±18V

Supply Voltages
Isolation Voltage
Input Current
.~torage Temperature Range.
Lead Temperature {s~ldering'''10 secondSl
Output Short-circuit Duration

2500V
±1mA

_,55°C to +10ooC
+3000C
Continuous to ground

TYPICAL PERFORMANCE CURVES
ITA = +25°C, ±Vcc = 15VDC unless otherwise notedl

BIPOLAR OUTPUT
SWING VSRF

SMALL SIGNAL
FREQUENCY RESPONSE

20

+10

+;Jvee

10

>

Q)

'it"

-10

«

-20

1'i
E

I

±15

Iii

""E

BIPOLAR INPUT STAGE
SUPPLY CURRENT VS INPUT CURRENT

±20

&"- 't.

rn ±10

"5

B-

6

±5

"':;'

...

~~I
"'if

±7~ee

B~

c:

~
u
~

'"

1'i

a.

C;
~

+Vee
-Vee

~

'"

VO = (l2pAHRF)
IVeol ~ tV max

-30

~

±ldvee

~~
'" '--±lolee-

C>

" "'



C>

"

Q)

'~

c:l

'""5a.

III 1800
.c;

'"

-10

0

\

270°

E

±13Vee

\

-15



c:

i!'

5
u

RECOMMENDED
OPERATING
REGION -I----+-+H-HI

Q)

E
.

750

g
§ 500

RECOMMENDED
OPERATING
REGION -----I--I+:f-I

~

g

Q)

u« 250r-~-------r------t---f171

...J

u'

«

O~~

+65 +85 +125
I.solation Voltage I kV I

Temperature (OC)

3-9

____

~~

__

~~~

-25
Temperature 1°C)

=
=

GAIN ERROR VS TEMPERATURE

RATE OF GAIN ERROR SHIFT
VS ISOLATION VOLTAGE
1.5,....-......,--...,..--.,..-.....,

3.0 ,..._.;.A...
N..
O_IS'i-0_L_A..;,T_IO...
.N_V..,0r-L_T_A_G_E........,

o

Short1erm shift (10 hrs)

2.5~~--+---'---+----;

gs~.2.0

1----j---'F;t----1

~ ~ 1.51----t--...,-,:b!"'-V'M, ±Ios) R" "" -(-I,,,) RF = I,,,R,,. (I).
where. losis the difference between AI and A2 bias
currents. For input voltage operation I'N can be replaced
'by a voltage source (V's) and series resistor (R,s)since
the summing node ofthe op amp is essentially at ground.
Thus. lIs = V's I R,!,.
Unipolar operation does have some constraints, however.
In this mode the input current must be negative so as to
produce a positive output voltage from AI to turn the
LED on. A current more negative than 20nA is necessary
to keep tbe LED turned on and the loop stabilized. When
this condition is not met the output Qlay be indeterminant.
Many sensors generate unidirectional signals; e.g.,
photoconductive and photodiode devices, as well as some
applications of thermocouples. However, other applications do require bipolar operation of the ISOIOO.

BIPOLAR OPERATION
To activate the bipolar mode. reference currents as
shown in Figure I. are attached to the input nodes of the
op amps. The input stage stabilizes just as it did in
unipolar operation. Assuming liN = O. the photodiode
has to supply all the IREFI current. Again. due to
symmetry. 1", = 1,)2. Since the two references are
matched. the current generated by D2 will equal IREF'.
This results in no current flow in R F • and the output
voltage will be zero. When I", either adds or substracts
current from the input node. the current DI will adjust to
satisfy IIlI = liN + lREFI. Because IREFI equals lREF' and IIlI
equals I",. a current equal to liN will flow in RI'. The
output voltage is then Vo: I,NR F. The range of allowable
liN is limited. Positive (,N can be as large as IREFI (1O.5J-1A.
min).At this point. DI supplies rio current and the loop
opens. Negative (,N can be as large as that generated by
DI with maximum LED output (recommended 10J-lA.
max).
DC ERRORS
Errors in the ISO 100 take the form of offset currents and
voltages plus their drifts with temperature. These are
shown in Figure 2.

'USE IMII OR GREATER TO ACHIEVE AFULL SCALE OUTPUT OF lOY.

FIGURE 2. Circuit Model for DC Errors in the ISO 100.
Al and A2:
are assumed to be ideal amplifiers.
Voso and VOSI: are the input offset voltages of the output
and input stage. respectively. Voso
appears directly at the output. but. VOSI
appears at the output as

is the gain error.
A. : I Ideal gain/ Actual gain I -I
The output then becomes:
V,N±VOS,
-IREFI ±Ios)(l + A.)+ IREF2]±Voso
VOI ' T: RF[(
R'N

A.:

(2)

The total input referred offset voltage of the ISO 100 can
be simplified by assuming that Ae: 0 and Y,N '" 0:
+VOSI
VOlr r "" RF [~±Ios ±.lIREF] ±Voso
(3)
R'N
where • .lIREF : IREFI - IREn.
This voltage is then referred back to the input by dividing
by RF R
Letting .lIR"F - los: los hip"''''
VosIRTII: (±VOSl ) ±R,N(lOS hi""''') + Voso / (R,,/ R'N) (4)
Example 1: (Refer to Figure 2 and Electrical Specifications Table)
R'N = 100kO. R,,: I MO (gain =10).
Given:
VOSI = +200J-lV.
los hip"'''' = +35nA, Voso: +200J-lV
Find:
The total offset voltage error referred to the
iriput and output when V'N = OV
Vos total RTI = ±VOSI ±R'N (los bipo,ar).
±VOSO/(RF/ R,N )
= +200!lV + lOOkO (35nA)
+200J-l V I( I Mn/ lOOk!})
= O.2mV + 3,5mV + 0.02mV
= 3.72mV

,s.

Vostotal RTO= Vos total RTI x RF/RIN
= 3.72mV x 10
= 37.2mV
(Note: This error is dominated by los bipo'ar
This calculation does not include gain error.
For total output offset see equation 2).

COMMON-MODE AND .UGH VOLTAGE ERRORS
Figure 3 shows a model of the ISOIOO that· can be used to
analyze common-mode and high voltage behavior.

VOSI...&'

R ,s

see equation.(2).
is the offset current. This is the currerit at
the input necessary to make the output
zero. It is equal to the combined effect of
the difference between the bias currents
of A I and A2 and the matching errors in
the optical components. in the unipolar
mode.
IREFI and IREF2 : are the reference currents that. when
-- - connected to the inputs. enable bipolar
operation. The two currents are trimmed. in the bipolar mode. to minimize
the los nipol" error.
!E.! and 11>2: are the currents generated by each photodiode in response to the light from the
LED.

3-11

FIGURE 3. High Voltage Error Model.

8

i

Definitions of CMR and,IMR,

'as

los is defined tHe'input cUfn!nl required to make the
ISOIOO's output zero. CMRRandlMRR in the ISOIOO
lire expressed asconductal1ceS; CMRR defines the
relationsllip 'between a change in the appli~d cotnmonmode voltage (VCM ) and the change in los required to
maintain the amplifier's output at zero:
CMRR (I-mode) ='Alos/~ VCM in nA/V
(5)
""":[AI6s'1' ""Av~h~M'
(6)
CM '
RR (V-mode)=. AVc,t'jRIN'='AVCM ' mV/V
IMRR defines the relationship between a change in the
applied isolation mode voltage (VIM) and, the change in
los required to maintain the amplifier's output at zero:
~Ios , .."
., '
.IMRR (I-mode) = ~VCM In pA/V
(7)
] R" =
[
1M RR (V-mode) =~Ios

(8)

~ VERR 1M in V V
. ~VIM,
CMRR & IMRR iriV/V area. function of RIN.
V1M is the voltage between .input ccimtnori and output
common.
VCM is the common~modevoltage(noise that is present
on both input lines,"typically 60Hz).
VERR is the'equivalenterrorsignal, applied in series with
--the input voltage; which produces an output error
identical to th!lt'produceq by applit::iltion of V'M
and V,M.
•
'.
CM R R and 1M RR are the common-lTIode and isolationmode rejection ratios, respectively.
~V",

TOTAL ,CAPACITANCE (C, and C2) is distributed
along the isolation' .barrier. Most of the capacitance is
coupled to'low impedance or noncritical nodes and
affects only the leakage current. Only a small capacitance
(C 2) couples to thejnput of the second stage, and
contributes to IMRR.

CM R = 20 LOG (0.3m VI Vi= .Y70dB at 60Hz
'"
iMRRin V/VF , , '
. .' ,
, JM R R (lcmode)(RIN) =.5pA/ V( 10,OkO}= 0.5J.1. v I v
IMR = 20 LOG (0.5 x IO-6V/V) =-126dBat DC
t.

Example 3:
.
In Example 2, VIM is an ~(,"!;igna\ at 60Hz and
IMRR=,400pA.

, v

VERR.RTI =
=
=
VERR RTO =

VERR CM + V ERR 1M
0.3mV + 200V (400pA;,V)(lOOk!l)
8.3mV
83mV (with AC IMRR)

Example 4:
Given:
Find:

Total error RTO from Examples I lind 3 as
120.2mV (with AC IMRRl
Percent error of + lOY full scale output
% Eiror VER R total x 100"
VI'S
= 120.2mV x 100
10V
= 1.2% '.

NOISE ERRORS
Noise' errors in the unipolar mode are due primarily to
the optical cavity. When the full 60kHz bandwidth is not
needed, the output noise oflhe ISOIOo'can be limited.by
either a capacitor, C", in the feedback loop or by a
low~pass filter following the output. This is shown in,
-Figure 4. Noise in the bipolar mode is due primarily to the
reference current sources, and can. be reduced bv the
.
low-pass filters shown in Figure 5.

Example. 2: Refer to Figure 3 and Electrical
: Specifrcation Table)
Given:

Find:

VCM = rVACpeak at 60Hz, VIM = 200VDC,
CMRR =3nA/V, IMRR = 5pA/V,
R;~'''='fiJom,RF= I MO ' .
{Gain = 10),
The error voltage referred to the iriput and
output whel). VIR = OV
VERR RTI = (VcM)(CMRR)(R ,N ) + (V",)
(lMRR)(RIN)
=1 V (~nA/V) (lOOk!l) + 200V
. .(5pA/V)(IOOkfl}·
=0.3mV+0.lmV
=O.4mV

"N
.f =_1_

o hliC

FIG U R E 4. Two Circuit Techniques for Reducing
Noise in the Unipolar Mode.
l00kn

lMI! .

V~RR RT.6 = VERR RTI (RF/ RI~)
= O.4mV (10)
; =4mV(with DC IMRR)
(No~.: This error is dominated by the CMR R
term)
' .. ' .. .
.
For purposesof comparingdvlRR and rMRR directly
with dB specificatio'ns, the following calcuIations can be
'.,
performed:
CMRR iri V/V = C'MRR (I-mode)(RIN)
= 3nA/V (lOOk) =Q.3tnV IV

3-12

FIGURE 5. Circuit Technique fqf Reducing Noisdrom
The Current Sources in the Bipolar-Mode.

OPTIONAL ADJUSTMENTS
The offset voltage of the input and output amplifiers
generally need no adjustment. However, VOSI and Voso
can be adjusted independently using external potentiometers. Anexample is shown in Figure 15. Notethat Voso
(500j.LV, max) appears directly at the output, but VOSI
appears at the output multiplied by gain (RF/ R,N). In
general, one pot, usually at the input, is sufficient.
Adjustment Procedures: In the bipolar mode, set V,N to 0
and adjust the offset potentiometer for a zero output
voltage. In the unipolar mode, set 1r~ to' the lowest
expected input current, for example 20nA, and adjust the
offset potentiometer for an output voltage equal to l,s x
R, .

FIGURE 9. Bipolar Inverting.

BASIC CIRCUIT CONNECTIONS

APPLICATION INFORMATION
The small size. low offset and drift, wide bandwidth.
ultra-low leakage, and low cost, make the ISOIOO ideal
for a variety of isolation applications. The b.asic mode of
operation of the ISO 100 will be determined by the type of
signal and application.
Major points to consider when designing circuits with the
ISOIOO.
I. Input Common (pin 18) and -IN (pin 17) should be

grounded through separate lines. The Input Common
can carry a large DC current and may cause feedback
to the signal input
2. lise shielded or twisted pair cable at the input, for long
lines.

FIGURE 6. Unipolar Noninverting.

3. Care should be taken to minimize external capacitance
across the isolation barrier.
4. The distance across the isolation barrier, between
external components, and conductor patterns. should
be maximized to reduce leakage and arcing.

or
VOUT = V,N (RF/R'NI

5. Although not an absolute requirement. the use of
conformally-coated printed circuit boards is recommended.

FIGURE 7. Bipolar Noninverting.

6. When in the unipolar mode, the reference 'currents
(pins 8 and 16) must be terminated.
7. The noise contribution of the reference currents will
cause the bipolar mode to be noisier than the unipolar
mode.
8. The maximum output voltage swing is determined by
l,N and R F .
VSWINO

=

IIN max X RF

9. A capac'itor (about 3pF) can be connected across R"
to compensate for peaking in the frequency response.
The peaking is caused by the pole generated by RF and
the capacitance at the input of the output amplifier.

·USE POSITIVE INPUT VOLlAGE ONLY
V,N »10#A x RSOURCE

FIGURE 8. Unipolar Inverting.

Figures 10 through'I6 show applications of the ISO 100.

3-13

. CF MAY BEUIED TO .
IMPROVE FREQUENCY
RESPONSE II1lIuC8 Pelklng)

CF MAY BE USED TO '
IMPROVE FREQUENCY " 10 =I /2 .. RFCF
RESPONSE {~C8'paaklnQI,

I...
v·t---.--"

I..-"...-...J.-_ _ _- - '

COLD JUNCTION
COMPENSATION
NOT SHOWN

R3 AND liz ARE REQUIRED TO MAINTAIN
A3mA. MIN. LOAD TO THE 722

FIGURE 10. Two-Port· Isolation Photodiode Amplifier
,
, (Unipolar).
.

R3 AND R2 ARE REQUIRED TO MAINTAIN
A3mA. MIN, LDAD TO THE 722

FIGURE II. Three-Port Isolation Thermocouple
Amplifier (Bipolar).

~--+-,--------,---,----:---'----,-'

+15V III ·t5V
(I) FOR ISOLATED SUPPLIES SEE FIGURES 10 AND II.

(2) IN THIS EXAMPLE THE INTERNAL PRECISION CURRENT REFERENCE. IREf
PROVIDES BRIDGE EXCITATION.
(3) PIN'S OF THE INAIOI MUST 8E MORE NEGATIVE THAN ·~v FOR LINEAR
OPERATION OF THE ISOIOD WITH RI = lOOkH.

FIGURE 12. Precision Bridge Isolation Amplifier (Unipolar).

3-14

ilUTPUT
COMMON

TOTAL GAIN =I ODD

OFFSET
AOJ

~ALlBRATION

PROCEDURE:

I. SET VIN =DV

2. ADJUST ~ FOR lOUT = 20mA

a SET VIN =-5V

,VISOLATEO

4. ADJUST RIN FOR lOUT =4mA

FOR ISOLATEO SUPPLIES SEE FIGURES 10 AND II

FIGURE 13. Isolated 4mA to 20mA Transmitter (Example of an isolated voltage controlled current source).

GAIN = +1010 +1000
APPROXIMATE INPUT OFFSETTING = 0 10 ±7.5~A
FOR ISOLATED SUPPLIES SEE FIGURES 10 and 11

FIGURE 14. Isolated Test Equipment Amplifier
(Unipolar with Offsetting).

NOTE: Offset Adjust on pins 5 and 6 are for nulling the 500~V
V080 only. To adjust overall offset, including bias current
effects, use nuiling (offset) scheme shown in either Figure
J3 or Figure 14. Reference current offset will give the best
performance.

3-15

-8=
~

VOUT

±VCC's
TO INPUT STAGES
OF AMPLIFIERS
2
3

724 ISOLATED
POWER SUPPLY

'NO ADOITIONAL CONNECTIONS TO OUTPUT AMPLIFIERS
NOTE THAT A VARIETY OF INPUT/GAIN CONFIGURATIONS CAN BE USEO

FIGURE 15. Four-Port Isolated Summing Amplifier (Unipolar).

CHANNEL SELECT

INPUT
CHANNELS

·15V

OUTPUT _
COMMON T
*FDR ISOLATEO POWER SUPPLIES SEE FIGURES 10 ANO II.

FIGURE 16. Multiple Channel Isolation Amplifier (Bipolar) with Programmable Gain (Useful in Data AcquisitIOn
Systems).

3-16

BURR-BROWN@

100MS

113131

EMI SHIELD
DESCRIPTION
The lOOMS is an epoxy encapsulated electromagnetic electrostatic interference (EMI) shield for use
with circuits where s,nsitivity to EMI is critical. It
was designed to attenu~te EM I by converting electromagnetic field energy into heat that is absorbed by
the shield and by shunting electrostatic fields to
comlT!on. The lOOMS may be used in applications to
either confine or exclude EM I. Its cavity was designed
for 28.45mm x 28.45mm x 7.24mm. 20-pin hybrid
packages. The shields in the cover and base plate are
in two separate halves to maintain the electrical
isolation between the adjacent rows of pins of the
module it encloses. Because of the spacing between
the shield halves and the epoxy flow holes. the
lOOMS provides a partial. but adequate low reluctam;e
path for electromagnetic flux. The' lOOMS' is well
sui.ted for use with isolation modules such as the
Burr-Brown )(,5(,. 722. and 724.

the output common. Figure 2 illustrates the assembly
of the lOOMS.

Connection to
Output Common

Connection to

I nput Common
VIsa:; Isolation Voltage

FIGURE I. Crnss-Sectional Side View of lOOMS.

Cover

ASSEMBLY INSTRUCTIONS

Shield Solder Tab

Assemble the base plate to the module by pushing the
pins of the module through the beveled holes in the
base plate until the base plate and bottom of the
module are in contact with each other. Place the
cover over the module so the tabs are aligned and fit
into the slots in the base plate. Bend the four wide
shield soldering tabs protruding from the cover to
make contact with the bare metal on the base plate.
Solder these four tabs to insure the integrity of their
connection to the base plate.
The lOOMS and the module it contains are mounted
and secured to a printed circuit board (PCB) by
soldering the two narrow PCB solder tabs to the
appropriate common. The PCB solder tab closest to
the input side of the module sl:lOuld be soldered to the
input common. The other tab..should be soldered to

:

I

:~~ ~BasePlate

ct-.-.-·j'.':.~
•. '
~.'

FIGURE 2. Assembly Diagram.

InternatiMal Airport Industrial Park - P.O. Box 11400 - Tucson. Arizona 85734 - Tel. 1602) 746-1111 - Twx: 910-952-1111 - Cable: BBRCORp· Telex: 66-6491

·3-17

SPECIF'ICATIONS'
ELECTRICAL -Specification~ apply between solder tabs.
PARAMETER

• C;:ONDITIQNS

NOTE:

T~mperature

changes

TYP

MIN

"uii,IITS

MAX

'"

Isolation Voltage
.Rated Continuot.ls. DC
Rated Continuous. AC
Test
Capacitance
Resistance
Leakage Current

~.'

3500
2000
8000

.

10 s.cori!!S

VDC

V, rrns

~ T fj,t,

VDC
pF
II

1010
0.23

120V.60Hz
I

",

I'A

greater than 1°C per minute be~ow OOC and long term storage above 100°C are not recommended;

MECtiANlq,AL
NOTE:
1. E'nelosed module lead length minus 0.060"
to 0.80· ,I,52mm'to 2.03mm •.
2. Pin diameter determined by enclosed
module.
Order Number: lOOMS
Weight: 1'7.5 'granis

DIM

INCHES
MIN
MAX

MILLIMETERS
MIN
MAX

A

1.320

1'.380

33.53

35.05

II

1.320

1.380

33.53

35.05

C

.350
.040
.60b

.450,
.060

8.89
1.02
15.24

11.43
1.52

L

.015
'1.180

0.38
29.97

N,

.150

.025
1.280
.250

3.81

0.64
32.51
6.35

p

.150

.250

3.81

6.35

R

.015
.130

.055
.230

0.38
3.30

1.40
5.B4

.080

.08Q

'1.52

2.03

0

H
J .

T
S

.700

APPLICATIONS INFORMATION
MULTIPLE DEVICE ORIENTATION

20kll

2Mll

20kll

2MIl

A typical application for the lOOMS is shown in Figure 3.
, Using multiple devices within 30mm of each other can
cause them to interact by forming beat frequency interference outputs. The lOOMS can reduce this interference
by as much as a factor 0[200: I depending on the distance
between the devices and their relative orientation.
_Minimum EMI results when the gaps of both shields are
paralleled as in Figure 3a.

.

Gap.in Shield

,J

Gap in Shield

Ia I

Optimum PCB I:-ayout.

(bllsolated Data -":equisition Input Glieuit,y.

FIGURE J. Orientation for Minimum EM!.

3-18

C =0.47I'F

17.78

3450
3451
3452
3455

BURR-,BROWN@!

113131

~------------------------------------------------------------------------~~
Precision Linear
ISO.LATION AMPLIFIERS
FEATURES

APPLICATIONS

• 2000V ISOLATION (3452)

• GROUND·LOOP ELIMINATION

• 160dB ISOLATlON·MODE REJECTION

• OFF·GROUND SIGNAL MEASUREMENTS

• DIFFERENTIAL INPUT

• MEDICAL INSTRUMENTATION

• 0.005% GUARANTEED GAIN LINEARITY (3450)

• PATIENT MONITORING

·lI"V/oC INPUT VOLTAGE DRIFT(34501

• INDUSTRIAL PROCESS CONTROL'

• 20pA INPUT BIAS CURRENT (3452)

• DATA ACQUISITION

• PRECISION WIRE·WOUND RESISTORS FOR
LONG TERM STABILITY

• HIGH VOLTAGE MEASUREMENTS
• FAULT PROTECTION

• LOW INTERFERENCE PICKUP· PW MODULATION

they can be connected in all of the common opamp
feedback circuits such as summing. inverting. differ. entiating. etc.

The models 3450. 3451. and 3452 are operatioAal
amplifiers with the unique feature of having the out·
put completely isolated from the input. This is
accomplished by a high accuracy modulation de·
modulation stage which isolates the input from the
output by 10'~n in parallel with 12p.f' of coupling
capacitance and provides gain linearity and stability
far superior to that offered bv ordinary isolation
."
amplifiers.

The 3452 differs from the 3450 and 3451 in that it has
higher isolation voltage (2000V vs 500V) and has
isolated ± 15VDC power available at the input.

These devices differ from other isolation amplifiers
in several respects. They are true differential input
operational amplifiers whereas other commercially
available isolation amplifiers are simple unityCgain
isolators or are capable ofa few fixed gains. Thus

The 3450 and 3451 differ from each other primarily
in their input stage characteristics. The 3450 has a
low drift (II" V "C) bipolar transistor input stage
while the 3451 has a low bias current (25pA)FET
transistor input stage. The 3455 is identical to the
3452 except for additional isolation specifications
more well suited for medical applications.

r ;::::::::::::: _-:::::: :::::: :::-:_-_._-.-.-_:,- ----.- -- --,
FOBK

I
I

·IN

PULSE WIDTH
MODULATOR

+IN

+V
liP COM
-vtBAL

OUTPUT
DIP COM

·15VOC
C>+,.----!...,...;I-+-----1r--:c=-T-"l----~--_HS +15VOC

>+--:-.,......,..---JL--l_.J:::~.:....--.JrotiiiCCiiNvEiRrtn--t<:J PWR COM

International Alrporllnduslrlal Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. 16021 746·1111 • Twx: 910·952·1111· Cable: BBRCORp· T818.,66·6491

3-19

SPECIFICATIONS
ELECTRICAL

"

i., . """

TYJj>ical at 25°C and ±15VDC unless otherwise no~-; '..

...,'.'

.','

I
Op~n-{.QOP

a_in,

min
Input 9ffset Voltage at 25°CI31. inax
T.emp~rature, max
vs, Supply
VS. Time
Input Bias Current at 25°C, max
, vs Temperature; max
vs.Suppl';'
Input uffset ,",urrent at 25°,",
vs Temperature max
vs. Supply
Input Impedance
Differential
Common-model')
Input Noise
.
Voltage; 0.01 Hz f(,1OHz
10Hz to 1kHz
Current, 0.01 Hz t.o 10Hz
10Hz·to 1kHz
I nput Voltage Range
Common-mode(4) (operating), min
Differential Iw/o daplage), min
Common-inode Rejection(4) at 10V
so atea ower Aval 80le
Voltage
Current. max
Ripple at 100kHz

. vs

'94';',;·,,:

.88

±O:~~, •

. . $4':

.:

*2p.
" ':.i5O" ,.'

!~ :
:;:,0'"

•.

.+0.30

.±S.O

:±50

±25
+100
-0.02
-0.025 •• ~
. doublesll00C
+0.001
±0.002
doubles/l00C,

±50
±0.5

±0.2
±30;-max
'to.3
+O.t
'"

dB
mV
~VfOC
~VN

~V/rrio

nA
n~~C

nAN

±O.OOOS

...

107
5·x.l09 1110

.n

lOll
10"1110

0.8
1.2
30
50

2
3
0.3
0.6

100

±10
±15
80

IlllpF
4
2
0.3
0.6

I

90

~V. p-p
rms
pA. p-p
pA, rms

IJ,V,

NOTE:

Le.d. in tr .... position within .015"
(.38mm) A" MMC at ,..tlng plane.

--

±15 +0. -10%

--

'tl0

--

100

V
mA
mV;,,-p

ISOLATION
Gain (without trimming). max(3)WN
±0.1
±0.5
vs Temperature, max
:1;:10
±50
Nonlinearity(5) at +10V. maxflyp
, +:005/+0.0015 ±0.025/+.005 ±O.025/+.005
Frequency Response, -3d5 Isee ~ig. 8)
1.5
2.5
Seltling Time
~Q~%

5

~~%

1

Isolation I mpedancelS)
Isolation Leakage Current
240V/60Hz. max
Isolation-mode Reject)on!")

1012

a'

I

±500
+2000

A

2.250

2.310

0

3:480
3.510
.7,10
.650
.038
.042
.200 8ASIC

89.15
87.63
16.51
18.03
0.97
1.07
5,08 BASIC

0
G
H

J

dB
dB
±2000
+5000

MAX

ppm/oC
%
kHz

II 16

MILLIMETERS
MIN
MAX

MIN

C

msec
msei:

160
120

DIM

%

2.5161

DC. min
60Hz. min
Isolation Vo)tageIS)
Rated. continuous, min
Test Voltage(7)'

4-40 thread, .10" f2.S4mml min, depth, 2 plec:e,'
, in tfue POIitio.n within .015" (.38fT1ml R (II MMC

V
V
dB

$7.15

58.157

,200
.300
.525 BASIC

5.08
7.62
13.34'BASIC

.170
.360
2,700 SAS1C

4.32
B.89
68.58 BASIC

,450
,350
1.350 BASIC
.7,50 SA'SIC

34.29 BASIC
19.05 BASIC

8.89

,- 11.43

MATERIAL: Black Plastic
WEIGHT: l00g '3.50'"
MATING CONNECTOR: 4400MC

V. pk
V. pkl·"

OUTPUT
"Output, Voltage. min,
Output Current. min
Output Impedance. DC
Output Noise
·0.01 Hz to .10Hz
10Hz to 1kHz
Outp,ut Offset Voltage at 2.$°C(31. max
vs Temperature, max
YS. Supply
vs. Time
Input Power,.Req4irements
Voltage
. Current. quiescent. max
Current. full load. max

±2 .

:tl0
±5

V
mA

0.2

!\

7
25
±5'
±100
±500
±100

I

~V.

I

±5

p.V/oC
~VN'

",V/mo

±14 to 116

+30/-5
+35/-10

I

+55/-10

TEMPERATURE RANGE
Specification
Storage
Operating

p-p
V rms
mV

'-2510 +85
-55 to.. +125
-25 to +85

3-20

VDC
mA
mAla,

NOTES:
1. The 3455 is identical to the 3452 except for two
additional specifications. ·each unll is tested to
withstand a 2500V, r:ms •. 6OHz sine wave isolation
voltage IRef. Dielectric Withstand Voltage.
paragraph 3~'J 1 of UL5441. Each unit is specified
at a maximum leakage current of 2~A with 240V.
rms, 80Hz. Isolation voltage I Ref. Leakage
Current •. paragraph 27.5 of UL544).
2. For 3450 and 3451 current drawn from FDBK pin
must be'; SmA. For 3452 the sum of the current
drawn.f(om FDBK pin and either "-il/Bal" or "+V"
pino I I.e .• + or - isolated currerill must be ';11 mAo
3. ertors may be trimmed to zero.
'4. Common-mode par.meters are measured at the
+)N and -IN pins with respect to the liP COM pin.
5. Npnlinearlty is specified to be the peak deviation
from a best strsightline expressed as a percent of
peak-to-peak full scale output.
S.lsolation-mode 'Parameters are measured at the
liP COM pin with respect to the PWR COM pin
and O/PCOM pin.
7. All ,units 100% tested for 1~A max leakage current
at test voltage.
8. Includes fullY loaded Input power.

PIN CONNECTIONS


• BAL
• -ViBAL

+15V.
-1SV.
OFFSET.
GAIN.

• -IN

O/P COM.

• FDBK

O/PCOM·.

OUTPUT.

• +v

OUTPUT.

=

~'

MODELS 3452 & 34S5

MODELS 3450 & 3451

CIRCUIT DESCRIPTION
The 3450. 3451. and 3452 operate on the same principle.
basically that of an operational amplifier followed by a
high accuracy isolation stage (Figure la). The high
accuracy of the isolation stage is achieved by use of a
proprietary feedback technique in combination with
high-stability components.
Isolated DC power for the input amplifier is provided by
a~ internal DC~to-DC converter which derives its power
from the external +15VDC supply.
Althougli a DC-to-DC. converter and modulation
techniques are used. the output noise is typically less than
I mV (peak) as a result of careful design. internal filtering.
and a shielded package. The frequency of this noise is
approximately 100kHz which makes it insignificant for
many applications. Pulse width modulation minimizes
pickup from adjacent units. The symbol shown in Figure
I b is used to represent the complete isolated operational
amplifier.

I DIP COM
(I)

I

I

I
I

_.J
-V/Bal (I)
(a) Simplified Bloel! Diagram

PWR
COM

(bl Symbol

The OJ P COM pin must be connected tothe PWR COM
pin. Figure lOa shows the power supply connections and
the optional offset and gain trims.

(110113452 only

FIGURE I. Block Diagram and Symbol.

APPLICATIONS
For signal sources of millivolt levels and low internal
impedance. the 3450 will usually be the best choice.
Signal sources of this type include thermocouples.
thermistors. etc. The 3451 will generally be the best
choice for signal sources having large values of internal
impedance. The pH cell is an example of this type of
signal source.

The isolation amplifiers may be used in the same manner
as any operational amplifier except that the feed back
signal is taken from the FDBK pin rather than from the
output pin. No connection is required orwould normally
be made from input common (1/ P COM) to either the
power common (PWR COM) or output signal ground
pins. Some typical circuit applications are shown in the
following paragraphs.

'See Nola 2 In
Electrical
SpaclHcaHOIIs.

NONINVERTING CIRCUITS
Two useful applications of these amplifiers are
impedance buffering and pre-amplification of low-level
signals. Such signals may be "riding" on several hundred
volts of common-mode potential or they may simply
have a significant amount of common-mode noise
(power line "pickup"; etc.).

Output

Source
Ground

Figure 2 illustrates the correct signal and feedback
connections for such noninverting circuits.

Load Ground

FIGURE 2. Noninverting Amplifier'Circuit.

3-21

""
"CURRENT AMPLIFIER
INVERTING CIRCUITS
As \\(iJh nonisQla.te!i.. o;>pera~ionaL!lJ~plifiers. the isolation
The isolation amplifiei"s can be'used' for,a.,variety ·,of
amplifiers 'can be used to conveh current source or
inverting circuit applications. Figure 3. illust.ra.tes. the
convert current sigl\al~ t~ :iillqlut vQltage. However. with
proper circuit connections forSUlllfning' a number of
these amplifiers;the:i'nput signal may have a large voltage'
sign,\ls which are all iit the same coni.mon~mode level. Ail
associated with it whi"h can he.cpmpletely isolated from
example of the use' of such an amplifier is the
output ground,· The drcuit in Figure 5 illustrates this
computation of a weighted a\erage of several
technique, '.
temperature inputs.

FIGURE 3. SumhIingAmplifier (or Weighted 'Averager).
DIFFERENTIAL IN~UT CIRCUIT
. The isolated operational all1plifier can be' operated in a
fully differenti.al mode as shown in Figure 4. The input
impedance of the differential·amplifier circuit is 2R, and
may cause underslrabIe loading 'of. the signal source
unless R', is: much 'greater than the. impedance of the
sign.aI sources.

FIGI,JRE 4. Isolated

D~fferential

BRIDGE AMPLIFIER
The circuit in Figure 6 illustrates a method of amplifying
a signal from a balanced bridge which cannot be
conveniently used wlth.3 nonisolated amplifier. The
circllit shown provides a high input impedance so that the
bridge is not loaded. The common"mode rejection of the
bridge excitation voltage.is not degraded by the external
gain setting . resistors as it would. be, with a difference
amplifier. The gain can be changed conveni~ntly. by
adjusting a single resistor (R,) ..·Also. the whole bridge
circuit may be floated with respect to the output by a
voltage equal to the isolation mode'voltage specification
without creating troublesome ground-loop current. .

Amplifier.

. OlItpuJ."

r---'~+

·Brldge excitation can bIi suPPlied bV 3452.

FIGURE 6. Bridge Circuit with Floating Input.

ISOLATION AMPLIFIER USED IN MEDICAL
APPLICATIONS
When isolation amplifiers are used in patient monitoring
medical application the considerations of I) patient
safety and 2) protection of ,the amplifier against
defibrillator voltages require the use of additional
circuitry.
The input resistors must be kept large in order to limit the
leakage current in the event of a component failure in the
input stage of the amplifier. The I.2Mn resistors will
limit the current to 12.S/lA (Figure 7).

The amplifier must be protected in two areas against
possible damage from defibrillator overvoltages. Diodes
DI through D. protect the input stage from excessive
voltages and currents. The gas-filled surge voltage
protection (SVP in Figure 7) will protect the isolation
barrier of the amplifier from breakdown. A Siemens part
number B2-8470 will limit the voltage across the
isolation barrier to 470V and has high isolation resistance
and low leakage capacitance characteristics.

1.2M!!

"\
2:.

.5

1.2Mu

Output

CommOll

101m
2W
+15V

Shield

FIGURE 7. High Performance ECG Amplifier Gain = 20V V.

PERFORMANCE
OFFSET VOLTAGE AND NOISE
The total error, at the output of the isolation amplifiers
may be computed by treating it as two amplifier stages in
cascade. One stage (the input stage) has variable gain (G I)
and the other stage (the isolation stage) has a fixed gain of
IV/V.
When this concept is applied to the circuit in Figure 2 as a
typical example we see that the total DC offset voltage
error at the isolation amplifier output is given by
Vo, = Vo,1 X G I IHRI X G I + V,,,,
where:; Vo< = total offset voltage. referred to output
(RTO)
Vo
EQUIVALENT CIRCUIT

(BI

(AI
,
'I
R2
• = CI + --!!!!L
+ --!!..) -

CMR =21i IOU10 CMRR

o

I

CMRR

IIiRR

RI

IMR =20 IOD1D'IMRR

FIGURE 8. Common-mode

andlsolatiori~mode

Voltage Errors.

al Open Loopl'reqilsncy Re.ponse of Input Amplifier

>iiI Frequency Response of Output Stage

fOO

BO

60
iD'

:la'

40

r\

\

"\

......

",

20

I!oo.

't'
;,

100

It

10k

·20

-450

""'"

c;;
:la

~

Phase ' /

Gain
.1

........

'~ , / Gain

;'\

, ,--... ......
"(Dalay-l OO~S~I

.goo

~

lOOk

~

,Ph:~ "

-40

.,

\.

'\

,

.6Q

~

1M

Ik

2k

FIGU RE 9. Frequency Response of Input and Output Stages.'

-J. 24

'

.

120"

""-\
"'-........

lDk

4k

lHzl

(Hzl

.'

\

......,\..
20k

INSTALLATION AND OPERATING INSTRUCTIONS
MOUNTING
The isolation amplifiers are plastic cased modules
suitable for soldering directly o'n to a printed circuit
board. Alternatively they may be plugged into the
4400MC mating connector which may be mounted on a
.
panel or chassis.
Gain of the isolation amplifiers is determined primarily
by the operational amplifier input stage. This alIows a
wide range of possible gains with the accuracy
determined primarily by the feedback networks and the
open-loop gain of the operational amplifiers. R,. ;;;: 10k!!
is' recommended for best linearity. The gain of the
isolation stage is nominalIy unity but may be trimmed
over a limited range to alIow easy calibration.
Offset voltages of both input and output stages are
adjustable by use of external components.
Figure 10 ilIustrates a typical amplifier circuit where gain
and offset voltages are adjusted. Proper calibration
procedure for this circuit would normalIy be as folIows:
POWER SUPPLY REQUIREMENTS
The isolation amplifiers have no unusual power supply
requirements. A standard low-cost power supply such as
the Burr-Brown 551 is recommended. The necessary

Feedback Network
FOBK

Input

O--~)-Mh..JOIl8etAdj.

isolated power for the input stage of the amplifier is
derived internally by a DC-to-DC converter operating
from the externalIy applied +ISVDC power.

CALIBRATION ADJUSTMENTS
ISOLATION STAGE OFFSET VOLTAGE NULL
Set input signal to zero (connect +IN to '1/ P COM)
connect 1/ P COM to 0/ P COM and measure the voltage
between the FDBK and OUTPUT pins with a floating
DVM. NulI this voltage by adjusting R4. Remove the
connection between I/P COM and OIP COM.
INPUT STAGE OFFSET VOLTAGE NULL
With the input signal set to zero, adjust RS such that the
voltage between the FDBK and I, P COM pins is zero.
(This is best done at a high gain value, i.e .. R(; + RF! R(;=
1000).
OVERALL GAIN ACCURACY
With R ... and R(; at the proper values to pr'oduce the
desired gain G = R" + R ... R(;. apply a known calibration
voltage VR as the input signal. Adjust R 3 for the desired
output Vo = VR X G.
If it is unnecessary to' adjust the offset voltage of the
output stage, R, and R. may be omitted. Ifnoadjustment
of input stage offset voltage is desi~ed, omit R, and R•. If
the specified gain accuracy (see spec table) is adequate
without further adjustment, both R, and R.l may be
omitted. The OUTPUT pin must then be connected to
the GAIN pin for an output stage gain of unity. Omit R, if
R, through R. is omitted.
For alI applications other than unity-gain noninverting,
R, is unnecessary and only R.l is needed to trim the gain.
However. it is then necessary.to set the first stage gain
slightly below the desired overall value and then use R,
for the gain calibration.
For fixed-gain applications it may be unnecessary to nul'
offset voltage for both input and output stages. The offset
voltage of the output stage, for instance. may be used to
compensate for the input stage offset. thus giving an
overalI null. However. if gain is to be varied over a wide
range it will usually be necessary to nulI both offset
voltages.

·15V

10MO (34IiOJ

75Ok0 (34&1)
Note: All external adjustments
IOMO 134521
are optional.
"This termlnallabeted "·VIBal" on Model 3452

FIGU RE lOa. External Connections for 3450, 3451
and 3452.

Appr'opriate safety precautions should be taken when
adjusting input stage offset voltage or gain. These points
will be '''floating'' at the isolation-mode voltage and
appropriate precautions must be taken if this is a high
voltage. In particular, any adjustment potentiometers
used for input stage adjustment should hilVe insulated
shafts with voltage ratings in excess of any expected
common-mode potential.
The.output stage can be adapted to drive capacitive load
of up to 10,000pF without sacrificing DC gain accuracy.
Add R, = lOon as shown in Figure lOb, otherwise,
R8 =on.

IOOkll

Oemod Source

FIGURE lOb. Equivalent Circuit of OJ P Stage.

3-25

=
~

....

WIRING S,HIEL.DINGANIr'
ISOLATION-MOOE REJECTION
The capacitive coupling from input common (I( P CO M)
to outpuicommon (OJ P, COM) for the isolation "
amplifiers is extremely low. This is essentiiil element in
achieving the isolation-mode rejection ~pecifications.
'Therefore. it is essential that care be used in wiring and
ptintedcirc~'lt 'card layo~itominlmiz,e st~ayi:llpacitance
between input and output circuits. .
Proper shielding of input'1eads is also essential in
preserving isolation-mode rejection. When shielded cable
is used the shield should be .connected to thecomm,on.mode potential. at the signal source ..
Isolation-mode rejection at high frequencies wilt be
degraded by resistance in series between the signal source
and the I; P COM pin (e.g .. wire resistance). Figure II
illustrates the mechanism by which. such degradation
occurs. The isolation-mode voltage :'divides".across R.
and C creating an 'isolation-mode error voltage ~eIS() .
which appears as an unwanted differential input voltage
adding to e,. Note that this. error occurs even if R" and Rw
are equal because the stray capadtance C . exists only
from the l. P COM pin t.()O P CClM.lfthisdegradation
of the isolation-mode rejection ~ecornes significant (for
R. = IkU and f = 60Hz. the CMR is still in excess of

97d'B) a <:&pacitill'lct,fr\>m thef1N:pin tp:Q/ P COM will
. compensate the effect. A capacitor used in this man,ner
must withstand whatever isolation-mOde potentialt;xi~ts:

ail

elso

IMRR=-681so

FIGU RE II. Degradation of Isolation-mode Rejection
, Due to Wiring Impedance and Coupling
Capacitance.

l-26
\

BURR-BROWN®

3456

IElElI

~--------------------------------------------------------~ ~
ISOLATED INSTRUMENTATION AMPLIFIER
FEATURES
• TRUE 3-WIRE INSTRUMENTATION AMPLIFIER INPUT
• TRUE INSTRUMENTATION GRADE ISOLATION AMPLIFIER
• IJ/V/oC INPUT VOLTAGE DRIFT
• ADJUSTABLE GAIN. I to 1000
• LOW NONLINEARITY. 0.02% max
• ISOLATION VOLTAGE. 2000V PEAK RATED CONTINUOUS
• l60dB ISOLATlON·MODE REJECTION
• ±20mA. VOLTAGE OR CURRENT PROGRAMMABLE OUTPUT
• 2.5kHz FREQUENCY RESPONSE
• LOW INTERFERENCE PICKUp·PW. MODULATION
• FULLY SELF·CONTAINED

APPLICATIONS
• ISOLATED THUMOCOUPLE AND RTD SENSING
• INDUSTRIAL PROCESS CONTROL
• TEST EQUIPMENT AND INSTRUMENTS
• HIGH VOLTAGE INSTRUMENTATION AMPLIFIER
• CURRENT SHUNT MEASUREMENTS
• GROUND· LOOP ELIMINATION
• BIOMEDICAL PATIENT MONITORING

International Airport Induslrlal Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. (6021 746·1111 . Twx: 910-952·1111 . Cable: BBRCORP . Telex: 66-6491

3-27

OESC-RIPT10N'
mOdula;~~/iti~~~~iOh

Mod~j; ~4~A'-and

The
34568 are high performance
instrumentation amplifiers which have their out~Ws
cqmpletely isolated from the input. The front end-oC,the
unit is a high performance, DC dlffererttia!~inpu~
irlstrumentation amplifier stage. designe4' foraa~a' .'
;::acquisition and instru~entation use. The 10w'dtif(lbw '
'noise and high CMR make it possible to accura:t'ely
,amplify microvolt-level signals with gains of up to 1000.
The input stage is followed by a high accuracy unity gain,

pulse'width
isolati<;>n stage.
This isolation stage isolAtes' ijfiriputJront',~he output by
lp1201f,14 pF impedani£The 3456Aana 34568 differ
,,frpmother isolation amplifiers in several respects. They
'ar¢ ,true instrumentation, amplifiers as opposed to
; differential input op amps or fixed gain isolators. They
"Offer both, the single resistor programmable gain range as
well ~s the true 3 wire instrumentation amplifier input.

THEORY OF OPERATION
<~""

"

•• •

;~'.

Figure I shows block diagram of 3456. The true 3 wire
instrume9tationamplifjer inpllt section Shown needs, only
one resistor to set the required gain level. It has high input
impedance, high CMR and low bias current and allows
the use of inverting, non-inverting afld differential input
configurations. The input offset adjustmenJ shown is"
optional.
ISolated DC power for the input stage is provided' by an'
internal DC / DC converter which derives its power from

"~I

.'

the external +15 VDC supply. The isolated power is also
made, available (9n +V and,-V p~ns>Jorexternal us~.
The modulation/ demodulation stage isolates the input
from ,the output by 10 12 0 in parallel with 14 pF of
coupling capacitance. 'Pulse width modulation technique
is' used to mininiize, pickUp from adjacent units. This
technique ,combined with the use of wirewound and laser
trimmed thin-film resistors provides high overall
accuracy and excellent dI:ift characteristics.

- Output

isolation Stage

Input Stage

--,
SENSE

12.Sk

r------t-.......-{) COMP

> .....-:-~OUT

Pul~e

R

Width
Modulator

O/PCOM

t,
'I '

+IN

+v

I/PCOM~--~----t----------r-r----~~

~---------t-----+-'O + lSY

PWR

ReCtifier

r----------+------~~COM

'-------:--0 - i SV

-v
1\

,'--BAL

,

~

G
R

BAL'
I

...

SOk

I

-~--

____ J

FiGURE.! .3456 BLOCK DIAGRAM

3-28

=Gain
=Gain Setting Resistor

SPECIFICATIONS
Typical at 2S"C and ±15VDC supply, voltage' unless otherwise noted.

ELECTRICAL
MpDEL

MECHANICAL
1

3456A

GAIN
Gain Equation

(BOTTOM VIEW)

3456.8

ct.

G = 1+ 2s:n

Range of Gain
Gain Nonlinearity at G ~ 100
';1000
Gain Accuracy at G t6; ·100
G'; 1000
Gain vs Temperature at G ~ 100
at G = 1000

INPUT
Input Impedance - Differential
Common-mode
Input Voltage Range!1I
A bsolute max
Common-mode Rejection,. DC-100Hz
at G = I. SkO source un bal.
at G = 100.
balanced source
Input Bias Current. I nilial
vs Temperature
vs Supply
Input Noise
Voltage. O.OIHz - 10 Hz
10Hz - 1.0kHz
Current. 0.01 Hz - 10Hz
10Hz - 1.0kHz

on

1-1000
±0.01% typ .. ±O.02% max
±O.03% typ .• ±O.08% max
±o.2% max
±O.S% typ.
10 ppm/"C
SO ppm/"C

~
•

58.4mm
(2.a")

(liP COM); .

,i.

(BAL)..

.:--1_'-

deep 2 Holes -Qc-----,(""BA"l"'")
~.

.;(+15V)
~; ·1.iS:v) ..................

2S4mm

; (SENSEI

(0.10·')
Iy,

; (CaMPI

0,

•

.1.

(GAIN);

191mm
(O.750··)

7······· . . ·• •·..·.. -+-+I:V);:~ ... +-

_.6.

(+IN);_
(-IN) I)

-

IGAIN)!

(alP COMI

o (OUTPUT)

I+V)~

-

,

t----- 68.6mm 12.7·', - - - - - I

8OdB. min
IIOdB
±SOnA •. max
0.3nA/"C typo 0.6nA/"C. max
±0.2nA/V
1.5~ pop
J.4j.tV rms
200pA pop
50pA rms

#4·40 Thread
5.1m. m{0.2")

~

lo'n II 3 pF
5 x lo'n II 3 pF
±IOV
±lsolated Supply

(PWA COM)

-

I

~f----17.8mm
(0.7")

I

I

88.9mm
(3.5")

•

I

I

~~-rrU'---'-.02-m-m---------------'r-~
(0.040")

5 1 mm

(0.2'·)

ISOLATED POWER
Voltage - No load
Voltage - ±IOmA
Current
Ripple at 100kHz

MATERIAL: Black Plastic
WEIGHT: 100 grams (3.5 oz.)
PINS: Pin material and plating composition
meet method 2003 (solderability) of
Mil-Std-883 (except ·paragraph 3.2)
MATING CONNECTOR: 44ooMC.

±J5.3V. max
±13.SV, mil)
±IOmA. max
100mV. pop

J

TOTAL OFFSET VOLTAGE
Initial 11f
vs Temperature
v. Supply
vs Time

±(0.5 + S/G)mV max
±(0.25 + 2/G)mV max
±(2·+ 150/G)~V rc max ±(I + 75/G)~V rC max
±(30 + 5OO/G)~V/V
±(3 + 100/G)~V Imo

PIN CONNECTIONS

ISOLATION
Isolation Impedance1lf
Isolation Mode Rejection. DC
,60Hz
Isolation Voltage. Rated Continuous
Test Volt.age!41

lO"n II 14 pF
+ liP Gain (dB)
1300B + liP Gain (dB). min
±2000V Peak
±SOOOV Peak
I~OdB

(TOP VIEW)
BURR~BROWN PWR COM.

FREQUENCY RESPONSE
-3dB Response at G ~ 400
-3dB Response for 400 ~ G
Setting Time to 0.01%
toO.I%

~

1000

• lIP COM

:::~

2.SkHz
2.SkHz to 1kHz
Smsec
lmsec

• GAIN
•

OUTPUT
Output Voltage
Output Impedance. DC
Short Circuit Current. Duration
Output Noise. O.OIHz - 10Hz
1Hz - 1kHz

--"I

.

• +IN

: ~:N
..,

± IOV at ±20mA, min
O.04n
4OmA. unlimited
15~V pop
25~V rms

I E!I E!l1

D'"
V

+15V·.

ISOLATED
-15• •
INSTRUMENTATION SENSE.

AMPLIFIER

3456A

O/;~;~

:

OUT •

POWER SUPPLY
Voltage
Current. Quiescent
Full Load(~1

+40/-8mA,. max
+8S/-30mA. max

TEMPERATURE RANGE
Specification
Operating
Storage

-25"C to +85"C
-2S"C to +85"C
-55"C to + 125"C

±14 to ±16VDC

NOTES:
I. The ±IOV input range is subject to the limitation that
I Vcommon mode I + I Gain x Vd,ff/21 :E:;; lOY.
2. Both the components (input and output) of the offset voltage may
be trimmed to zero.
3. Isolation mode parameters are measured at the liP COM pin with
respect to the PWR COM pin.
4, All units are .100% tested for 2Sj.tA maximum leaka~e at test
voltage.
I
5. Includes full iSOlated pOwer supply·,

'3-29

VOLTAGE' OUTPUT CONFIGURATION' "

2:

The 3456, when connected as show~in 'Figure
will
provide output signal Cl\pable of driving up to ±20mA
load.' Refertp lhe block diagl<\ln shawn in Figute 2.
Notice that the dembduh.!.ted signal is referenced to the
alP COM pin. The O/PCOM pin is connected to the
output ground (PWR COM)' for voltage output
configuration as is shown in Figure 2. So with this
configuration, the demodulated voltage signal is fully
applied across the, load impedance Zl..
If roll-off ata lower frequency (lower than 2.5kHz) is
desired, an optional cqmpensation capacitor Cc may be
connected as shown between the CaMP pin and the OUT
pin. See Figure 4 for the selection ofCc. The output offset
controls shown in Figure 2 and Figure 3 are optional.
They provide approximately ±15mV offset control at the
output.

The SENSE and COMP pins are subject to electrostatic
noise pick-up via stray capacitance. To 'minimize this
noise pick-up these pins and connected circuits should be
shielded. If these controls are not used, we recommend
the unused pins be cut off flush to the 3456 surface. This
would help minimize the degradation of Isolation Mode
Rejection.
- Optional
Offset Control

IJ..d-

O.IIl'·

'"

('~

n.nllll·
I(lOOp/-

IOOpl'
HipI-"
H.I

iU

100
11,

JOOO

,FIGURE4. -3dB Frequency Vs Cc (Voltage Output).
ALTERNATE GAIN ADJUSTMENT
'The gain adjustments are normally made by varying the
gain setting resistor at the input. Since voltages at high
potential may be present at the input side of the isolation
barrier, some applications may require that gain
adjustments or gain trimming be done at the output side
of the isolation amplifier. For the voltage output
configuration. such gain trimming can be done at the
output. Figure 5 shows a recommended gain adjustment
method, This method would provide a ±l% gain trim at
the output.
.

9+ ISV

r-___

SENSE 100Mn

..!:

I-<>-~~lOOkn

6-'lsv
*cc

COMP ___ ~

J(iMn

'"
<'

OUT

~

2Skn

".

'"

--.

RL

011' COM

O/PCOM

soon

FIGURE 5. Alternate Gain Adjustment Method For
Voltage Output Configuration.

HS6

CURRENT OUTPUT
FIGURE 2. Voltage Output Configuration With
Simplified Block Diagram.
'

SENSE 100kn

,

100kn

~-,-

f

-¥IY--

1100!!

+ISV

10kn'

-I

sv

FIGURE 3. Alternate a i P Offset Control For Voltage
Output Configuration.
.

CONFIGU~ATlON

Current output configuration is a configuration which
gives an output current proportional to the input signal.
The 3456 should be connected as shown in Figure 6 for
current output configuration. In this configuration, the
alP COM pin is not connected to the output ground
(PWR COM). Thea I P COM pin is connected toRe. The
demodulated signal (voltage between the OUT pili and
OIP,COM pin) is thus applied across Rs. With Ii given
demodulated signal and known feedback for the output
amplifier, the voltage across Rs, can be calculated. With
known valJle of this voltage, the value of Rs can' be fixed
to give the desired output current,to the load resistor Rl..
The output current is thus programmed by Rs.It does not
change with changes in the load resistor RI.. The feedback
resistor R~ paralleled with the internal IOOk!l resistor (see
Figure 6) helps achieve the required voltage rescaling at
the output (the OUT pin).

3-30

the demodulated signal -reference from output ground to
the voltage developed across RL. Hence, as discussed
earlier, consistent with the requirements of desired
application, it is best to keep the RL to as minimum a
value as is possible. Figure 7 shows the maximum
additional peak nonlinearity errors in the current output
configuration expressed as a percent of full scale peak to
peak output (40mA) vs RL/Rs.
RS

The values of Rs and RF as calculated above, would
program the unit for the desired full scale output current
I. when the gain of 3456 is scaled for ±IOV full scale
ouptut. With these values of Rs and RF the unit would
comply with the performance curves shown in Figures 7,
8 and 9. Deviation from this selection procedure could
result in degraded performance.
FIGURE 6. Current Output Configuration With
Simplified Block Diagram

Due to the output amplifier bias currents and the
demodulator currents, we recommend that the full scale
output current vahle be ±lmA or higher (up to ±20mA).

PROGRAMMING FOR CURRENT OUTPUT
The selection criteria discussed below is based on 3456
being gain programmed for ±IOV full scale signal at the
OUT pin (the signal as referenced to the PWR COM pin).
With ±IOV" full scale signal, best overall accuracy is
achieved.
RL is defined as the maximum load impedance in ohms
and 10 as the maximum peak output current in amperes.
The common-mode voltage (an error producing term) is
directly proportional to RL. So, it is desirable to keep RL
to as minimum a value as is consistent with desired
application's requirements.
Determine first the value of 10 and RL suitable for the
desired application. The values of Rs and RF in ohms can
be obtained by the expressions,
10 - I. RL
Rs=---and
·R F

=-------

I

0:

V

o. I

0

0:
0:

:.:.:
f-

z:

t
'"

0: 0.0 1

fI/

".

0.

0.00 I V ,
0.1

10

100

FIGURE 7. Maximum Additional Peak Nonlinearity
Errors in Current Output Configuration Expressed as
Percent of pop Output Current Vs RL/Rs.

105 - 10 Rs . 10' + Rs
Cc, expressed in pF, can be calculated by the expression
220.10 5

Cc

where RF is in ohms.
The above calculated value of Cc would maintain the
-3dB frequency response at 2.5kHz. Roll-off at a
frequency lower than 2.5kHz can, be achieved by
increasing the value of Ce .
The maximum allowable voltage across Rs + RL to
maintain the specified accuracy, also known as
"compliance" is limited to ±IOV by the output swing
capability of the output amplifier.
The current output configuration contains all error
elements of the voltage output configuration plus
additional common-mode errors introduced by raising

>

E

O.I~_

FIGURE 8. Typical Additional Offset in Current Output
Configuration Vs RL/Rs.

3-31

CC)

~

configuration. Gain nonlinearity would 'not'exceed,the
voltage output specification by more than the value:
indicateq iriF.gtire 7.

fOO'._"'II
IOIlE. .

Current'output offset and teIJ1perature drift·are specified
'as a voltage quantity.,appearing across Rs. 'These' .
parameters each containlwo terms. The firs,t termis the ;'
total offset voltage RTI (referred to input) specification'
for voltage outPllt mode multiplied by the input g~in

,._-

setting, multiplied by

./

•

.',

~ .' The second t~rm is the;
L+~'
.

value found from Figure 8 for the offset voltage and fTom '
Figure 9 for (he offset voltage drift. Adding these two·
terms would give the offset voltage and the offset voltage
drift values appearing across the scaling resistor Rs. To
obtain these paramete~s in t~r,ms of the offset current and.
the offset current drift, they have to be divided by Rs. In
short,

FIGURE 9. Typical Additional Temperature Drift in
Current Output Configuration Vs R,JRs.
SPECIFICATIONS FOR CURRENT OUTPUT
When the above 'discussed current output configuration
procedure is followed for selection o(R F , Rs, Cc and RI.,
the following performance st,mdards would be met by the
cpnfiguratiort.
'
Gain accuracy would be maintained within a maximum
. of 0.1 % above that specified fot voltage output.

( voltag, Output

M~dC) ,(Input)
(--!L)+(
Value from .\
Gain
Rs + RL
f:ig. 8 or Fig. 9)

Specification

_ (current Ou~put Mo~e)
-

Specification

To qbtain the ~ffset or drift i~ units of ~urrent, divide the
above .equation by Rs.

].:.32

BURR-BROWN® .

3650
3652

IElElI

~------------------------------------------------------------------------~ ~
~

Optically-Coupled Linear
ISOLATION AMPLIFIERS

FEATURES

APPLICATIONS

• BALANCED INPUT

• INDUSTRIAL PROCESS CONTROL

• LARGE COMMON-MODE VOLTAGES
±2000V Continuous
140dB Rejection

• DATA ACQUISITION
• INTERFACE ELEMENT
• BIOMEDICAL MEASUREMENTS

• ULTRA LOW LEAKAGE
0.35J.1A max at 240V160Hz

• PATIENT MONITORING

I.BpF Leakage Capacitance

• TEST EQUIPMENT

• EXCELLENT GAIN ACCURACY
0.05% linearity
0.05%/l000Hours Stability

• CURRENT SHUNT MEASUREMENT
• GROUND-LOOP ELIMINATION

• WIDE BANDWIDTH
15kHz ±3dB
1.2VI !,sec Slew Rate

• SCR CONTROLS

DESCRIPTION
The 3650 and 3652 are optically coupled integrated
circuit isolation amplifiers. Prior to their introduction commercially available isolation amplifiers had
l:>een modular or rack mounted devices using transformer coupled modulation demodulation techniques.
Compared to these earlier isolation amplifiers the
3650 .and 3652 have the advantage of smaller size.

lower cost. wider bandwidth and 'integrated circuit
reliability. Also. because they lise a DC analog
modulation technique as opposed to a carrier type
technique; they avoid the problems of electromagnetic
interference (both transmitted and received) that
most of the modular isolation amplifiers exhibit;

'--~
Light
Ftux

~.

~4

'.

1 - - - - - Common to 3650 & 3652 --,----1.1
International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona B5734· Tel. 1602) 746·1111 . Twx: 910-952·1111· Cable: BBRCORp· Telex: 66·6491

3-33

ELECTRlqAL

-

T yp'ca
. I at2S0C an'C!+15YDCs uppi yvo Itag'
esune

1

MODEL
ISOLATION

..

e

365OMGIHChi '

,

Isolation Voltage
Rated Continuous, ~ min)
:"Test Voltage, Iminl 10sec duration

.-

S no

,....;:.

"

1

.1

·:.365OJG

3650KG

1

' 3652MO/KG;;\

1,\

,~: 36WG

";','
,,'

~;::: ,

.'.

I

:!OOOVp or VDC
SOOOVp

..

!solation-Mode Aejection, G -10
DC
" 60Hz, SOOOl! source unbaiance
:Leakage Current, 240Vl6QHz
Isolalion Impedance

l40dB
120dB
0;35,.A, max
1.8pF
10'21!

Capacitance

Resistance
GAIN
Gain Equation
for current sources

for volt~ge.sources
Input Resistance. RIN. max
Buffer Output Impedance, Ro
Gain Equation Errs,. maxiS)
Gain Nonlinearity
Gain vs Temperature
Gain vsTime

G,

=l09Volt/Amp

=

'106

=1.ooS7 x lOSVoltlAmp'"

RG1

+ RG2 + RIN

VN

I

I

I

Frequency Respon~e
Slew Rats
±3dB Frequency
Sellling Time,
to±O.Ol%
I

G,

.1()6'
VN
RG' + AG2 + A'N + Ro
2SI!
2S11
Not applicable
901I±3011
1.S%<4'
0.5%141
1.S%
O.S%·
O.S%
±O.OS% typo ±O.2% max. ±0.03% typo ±O.l% max ±0.02% typ. ±0.05% max ±O.OS% typo ±0.2% max ±O.05% typo ±0.1% max
3OOppmfOC
.
100ppml"C
SOppmfOC
~OOppmfOCl41
2OOppmI"C<4·
±Q.OS%ll000hrs.
±0.05%11000hrs.
Gv

0.7V1psec min, 1.2V1psec typ.
15kHz
4oo"s""
200psec

to±O.1%

INPUT STAGE'"
Input Offset Voltage
at 25°C. maxGU

vs Temperature. max
VliSupply

vs Time
Input Bias. Current
at2S0C
vs Temperature
vsSupply
Input Offset Current
vs Temperature
vs Supply
Input Impedance
Differenlial
Common·mode
Input Noise
Voltage, O.05Hz to 100tlz
10Hz to 10kHz

±SmV
±2S"VfOC

I

I

±1mV

±10"VfOC

l00"VN

±O.SmV
. ±5"VfOC

±SmV

±2mV
:!:25pVfOC

±5O~VfOC

lJVN

SOpVll000 hrs.

loopVll0oo hrs.

10nA typ, 40nA max
0.3nAl"C
.0.2nAN

1OpA typ, SOpA max
doubles e¥ery +l00C
1pAN

effects included
in output offset

10pA.
doubles every 10°C
lpAN

=2511 max
109/1

101111
101111

8pV, pop
4"V, rms

4", pop
5"V, rms

"R'N"

,

Input Voltage Range
Common·mode. linear operation.
wlo damage, at +,at+I,-1
at+IA, -IA

±II VI-SIV
±V
Not applicable ...
Not applicable'"

Differential, wlo damage, at +, Differential: wlo damage, at +1,-1
Differential, wlo damage, at +IA, -IA

±V
Not appllcabl.e
Not applicable

±V
±600V for 10msscI7I
±60OOV for 10msec'"

Common-mode Rejection, 60Hz

90dS at 80Hz, Ska imb"ance

80dB at 80Hz, Skll imbalahce

Power Supply ,Input Stage Only,
Voltage' at "+V" and "-V"

±8V to±18V

±8V to±18V

:t1.2mA'"
+6.SmA or -a.5mA, typ
+1'2mA or -12mA, max

+8.5mA or -8.SmA, typ
+16mA or -16mA, max'

.,

±il VI-51
±V
±300V for 10msec l7l
±3000V for 10msec '71

Current
Quiescent
with ±10V output'71

±3mAIII

..

3-34

ELf:CTAICAL (coni)
3IIOIIGIHG 111

MOOEL

3I52MGIHG·C11

3I52JG

OUTPUT STAGE
Output Voltage. min
Output Current. min
Output Offset Voltage
at 25°C maxQI

±lOV

t10V
··,·,..-±5mA···

±25mV
±900,uVfOC

vs Temperature. max

±10mV
±450J'V/oC
iSOOpVN
±1 mVll000hrs

vs Supply

vsTime
Output NoiseVoltage
O.OSHz to 100Hz
10Hz to 1kHz

±5mA

±25mV
±900,.NloC

±10mV
±3OOpVI"C

±lmVI1000hrs

SOpV. pop

SOpV. pop
65IJV. rms

65,N. rrns

Power Supply, Output Stage Only I
Voltage I "+Vcc" and "-Vee",
Current
Quiescent
with ±5mA output. max

±10mV
±450iIlVloC

±500,NN

±8V to ±18V
±2.3mA typ, ±6mA max
±11mA

TEMPERATURE ...
Specification
Operating
Storage

O"C to 85°C
-4O"C to +1OOOC
~55°C

to +125°C

1. All electrical and mechanical speciflcationa of the 3650MG and 3852MG are identical to the 3650HG and 3652HG. respectively. except that the following
specifications applv to the 3850MG and 3852MG: (a) Isolation teat yoltage duration IncrllQd from 10sec minimum to 60eec minimum; (b) Input offset yoltage at
25·C max: ±1OmV; va temp. max: ±100,tVrC; (e) Output offset voltage at 25·C max: ±SOmV; .. temp. max: ±1.8mVrC.
2. If used 8S 36S0, see Installation and Operating Instructions.
3. Trimmab1. to zero.
4. Gain error terms specified tor inputs applied through buffer a",plifi8n (i.e., ±1 or ±IR pins).
5. Input stag. specifications at +1 and -1 Input" tor 3852 unless othei'WJse noted.
8. Maximum eate Input current at erther input i8 1OmA.
7. Continu~u. rating is 1/3 pula retlng.
8. Load current·il drawn from on8 supply lead at 8 time; other supply current at quiescent krlel. For 3852 add O.2mA/V of positive CMV.
9. dTJdt> 1°C/mlnute below O·C, and long-term storage above1000C is not recommended. Also limit the repeated thermal cycles to be within the 0·0 to +85·C
temperature range.

n .......

PIN .CONNECTIONS

MECHANICAL

.,--------:10<' "+" denotes missing
32

~.i'~~
1

for reference only
Numbers may not be

B

~

pins.

Pin numbers shown
marked on package.

t
L
l Fr-j II-~-'l--' .r=~1
:

••••••••••••• :

•

_

NOTE:

Leads in true position
within 0.010"
IO.25mmIR3IMMCat
seating plane.

I-I

.J0

DIM'

INCHES
MIN
MAX
1.701
1.120
.170

•

,Mitt

....

4$.1.

...0

4.:12

....,.
.....
MAX

....

.....,.. .... ....
., .
.... ..., I."....
1.21
:II.MIUIC
2.7'

AS'C

H

.. MILLIMETERS

1.710
1.1eo

,

F

.110

. '10

.lCIDaASlC

N

..

,

.010

• 110

.

....

22.11 IAlIC
0.21
:1.1 •

3."

LLJ

·ORDER NUMBER:
3850MG 3852MG
3852HG
3850HG
3852JG
3850JG
3850KG
MATERIAL: Alumina
(ceramic!
WEIGHT: 14 grams
10.50Z)

MATING CONNECTOR:
2302MC I set 01 two.
16-pin striPs I

3-,15

'T:VPICAL PERFQRMANCE! 'CURVES
Typical at 25°C and ±15VDC power supplies unless otherwise noted.

It-IPUT STAGE SUPPLY CURRENT
VS,oUTPuiVOLTAGE
,
, 12r-:..,rr-,r--r-;rr-,

.(

NORMALIZED LINEARITY
VS. TEMPERATURE
1.5

ISOLATION LEAKAGE CURRENT
VS.ISOLATION VOLTAGE

u

_ 0 5 f-+--ir--'--t--+-t----l

E

~ 10).
U:sethefollowing procedure If it is desired to null both
input and output components (for example. if the gain of
the amplifier is to be switched). The input stage offset is
first nulled (50k!} adjustment) with the appropriate.input
signal pins connected to input common and the amplifier
set at its maximum gain. The gain is then set to its-

Figure 6a shows the 3650 connected as a transconductance
amplifier with input current sources. Voltage sources are
shown in Figure 6b. I n this case the voltages ar,e
converted to currents by R';I and Ru ,. As shown by the
equations. they perform as ga,in setting resistors in the
voltage transfer function. When a single voltage source is,
used.it is recommended (but not essential) that the gain
setting resistor, remain split into two equal halves in order
to minimize errors due to bias currents and common"mode rejection (see Typical Performance Curves).
Figure 6c'illustrates the connections for the 3652w'hen
the FET buffer amplifiers A, and A, are used. This
configuration provides an isolation amplifier with high
input impe~an'ce'(both common-mode and differential)
and good common-made,and isolation-mode rejection.
It is a true isolated instrumentation amplifier which oas
many benefits for noise rejection when source impedance
i\1lbalances are present.
,In ,the 3652 the voltage gain of the buffer amplifiers 'is
slightly less than unity, but the iainof the output stage
has been raised to compensate for this so that the overall
transfer function from the ±I or±! R inputs to .the output
,is correCt. It should be noted that AI and A2 are buffer
amplifiers. No summing can be done at the ,±l or ±I R
inputs. Figure6c shows the +1 and -I inputs used. Ifmore
input voltage protection is desired, then the +1 Rand - 1R
inputs should be used. This will increase the input noise
due to the contribution from the I .6M!} resistors, but will
provIde additional differential and common-mode protection (IOmsec rating of 3kV).
.

A" and A" the input and output stage amplifiers. are
considered to be ideal. Separate external generators are
used to model the offset voltages and bias currents. Roo is
assumed to be small relative to R'il and R'02 and is
therefore omitted from the gain equation. The feedback
configuration, optics and component matching are such
that I, = I, = 1.1 = I•. A simple circuit analysis gives the
following expression for the total output error voltage
due to offset voltages and bias currents.
10"
(I
Y"",.,,,,,,, = R (j I + R (i~ [E"" + (1111 R'il -Ill, R,;,~+
!J E"",

Your =('I • '21 x IrAti + v,so xIMRR*
FI~URE

6a. 3650 With Differential Current Sources.

f5

Offset current is defined as the difference between the
two bias currents 1111 and J,,,. If 1111 = III and Ill, = III + I"" ~

.

IP"·I,.,

then. (or R'il = R(;,. Y,,,,, -Ill = -2This comporient of error is not a function of gain and is
therefore included as a part of E,,,,, specifications. The
output errors due to the output stage bias current are also
included in E."".This results in a very simple equation for
the total error:
,

V,HU-to,t;LI

FIGURE 6b. 3650 With Differential Voltage Source.

I' R(it -- R(i~ ) •
= 10"E""
2R(d + E·1'>0 (or

(2)

In summary it should be noted that equation (2) should
be used only when R';I = R,;,. When Rid ¥ R,;,.
'equation (I) applies.
The effects of temperature may be analyzed by replacing'
the offset terms with their corresponding temperature
gradient terms:
V",,,-6 y"", 6T, E"" -6E,,,, 6T, etc.
For a complete analysis of the effects of temperature.
gain variations must also be considered.

FI G U R E 6c. 365I with Differential Voltage Source.
"'IMRR here is in pA V. typically SpA Vat 60Hr and IpA Vat DC.

OUTPUT NOISE

··The offset adjustment circuitry and power supply connection!'l have been
omitted for simplicity. Refer to Figure 5 for details.

The total output noise is given by
E,,(RMS) = V(En, G)'

+ (Enoi

where E" (RMS) = total output noise
E", = RMS noise of the input stage
E"" = RMS noise of the output stage
G = H)" (R';I + R,d

ERROR ANALYSIS
A model of the 3650 suitable for DC error analysis of
offset voltage. voltage drift versus temperature. bias
current. etc., is shown in Figure 7.

E"" includes the noise contribution due to the optics and
the noise currents of the output stage. Errors created by
the noise current of the input stage are insignificant
compared to other noise sources and are therefore
omitted.

COMMON-MODE and ISOLATION-MODE
REJECTION
The expression for the output error due to commonmode and isolation mode voltage is:
V,'m
V"" ]
V,,,,, = G [ CMRR + IMRR

FIGURE 7. DC Error Analysis Model for 3650.

3-39

GUARDING 8t PROTeCTION

1. . . .

1ICJUC·c:.Mrt.r.

·...·.... ,22

To preserve fhe excellent inhererit isolation characteristics
of these amplifiers, the fol1owing re'commended practice
should be noted:
'
I, Use shielded, twisted pair of cable at the input as
with any instrumentation amplifier:
, 2. Care sould be taken ~o minimize external capacitance. A symmetrical layout of external components
to achieve balanced capacitance from the input
terminals to output common will preserve high IMR;
3. External components and conductor patterns should
be at a distance equal to or greater than the d'istance
between the input and output terminals, to prevent
HV breakdown.
4, Though not an absolute requirement, the use of
laminated or conforinally coated printed circuit
boards is recommended. '

APPLICATIONS
Figure 8 shows a system wht;re i~olation amplifiers (3650)
'are used to measure the' armature current and the
armature voltage of,a motor.

FIGURE 9, 3652 Used in Patient Monitoring
Application (ECG, VCG,.·EMG Amplifier).,
The 3652 is ideally suited for patient monitoring applications as shown in Figure 9; The fact that it is a true
balanced input instrumentation amplifier with very high
differential and common-mode 'inpedance mcans that it
can greatly reduce thecOmmon~mode lioise pick up due
to-imbalance in lead impedance's that often appear in
patient monitoring situations, The 3kV and 6kV shown
in Figure 9 are the 10msec pulse ratings of the +IR and
-I R, inputs for the common-mode a'nd differential input
voltages with respectto input common. The rating of.the
isolation b<\rrier is 2000V, pk continuous. The nonrecurrent pulse rating of the isolation barrier is 5000V, pk
since e-<\ch uriit is' factory tested at 5000V, pk.lf the
isdlinion barrier isto'be subjected to higher voltages a gas"
filied surge voltage protection device can be used, For
multichanneLoperation, two 3562's can be powered by'
'one Model 722 isolated DC: DC converter. The total
leakage current for both channels at 240V / 60Hz would
still be less than 2J.lA.
'
The block diagram in Figure 10 shows the use of isolation
amplifiers in SCR control application.

FIGURE 8, Is.olated Armature Current and Voltage
Sensor.
The armature 'current of the inotor 'is converted to a
voltage by the calibrated shunt 'R, and then amplifier
(adjustable gain) and isolated by the 3650,'
The armature voltage is sensed by the voltage divider
(adjustable) shown and then amplified and isolated by
the,3650,
The 3650' provides the advantage of accurate curren!
measurement i,n the 'presence of high: common-mode
voltage, Both 3650's provide the advantage of isolating
the motor ground from the control system ground.
Isolated power is provided by ari isolated DC:DC
converter (BB Model 722 or equivalent).

FIGURE 10. 3-PhaseBidirectional SCRC,ontrol with
Voltage Feedback.

340

BURR-BROWN®

3656

IElElI

Integrated Circuit - Transformer Coupled
ISOLATION AMPLIFIER
FEATURES

APPLICATIONS

• INTERNAL ISOLATED POWER

• MEDICAL

Patient monitoring and dlagnoatlc
Inltrumaritatlon

.8000V ISOLATION TEST VOLTAGE
• O.5IlA MAX LEAKAGE AT 120V, 80Hz

• INDUSTRIAL

Ground loop elimination and off-ground
slgnll mellurement

.3-PORlISOLATION
• 125dB REJECTION AT 60Hz

• NUCLEAR

• 1" xl" x 0.25" CERAMIC PACKAGE

Input/output/power Isolation

DESCRIPTION
The 3656 is the .first amplifier to provide a total
isolation function ." both signal and power isolation
". in integrated circuit form. This remarkable advancement in analog signal processing capabiiity is
accomplished by use of a patented modulat.ion
technique and minature hybrid transformer.
Versatility and performance are outstanding features
of the 3656. It is capable of operating with three

completely independent grounds (three-port isolation). In addition. the isolated power generated is
ayailable to power external circuitry at either the
input or output. The uncommitted op amps at the
input and the output allow a wide variety of c;losedloop configurations to match the requirements of
many different types of isolation applications.

I

I
I

I

____ .-J

ThiS product IS covered by the following United States patents: 4.066.974; 4.103.267; 4. 082.908, Other patents pending may also apply upon the
allowance and issuance of patents thereon. The product may also be covered in other countries by one or more international patents
corresponding to the above-identified U.S. patents.

International Airporllnduslrial Park - P.O. Box 11400· Tucson. Arizona 85734· Tel. 16021 746-1111 . Twx: 911).952·1111 . Cable: BBRCORP'· Telex: 66·6491

3-41

,

..

\

THEORY OF OPERATION
. Details of t6c;:3656 a~e shown in Figure ·1. The external
connections shown, place it in its simplest gain
configuration ~ unity gain, noninvertihg. ~everahoth'er'
amplifier gain configurations and power \s~la:tion .
configuratiohs are possible. See Installation,: and.
Operating Instructions and Applications sectiops; for . .
details.
.
, "
.

in Figure 'I) 'to equal th~,iriRl,Itslgn~1 voltage applied at
pin 7. Since the input an~ til¢' ri\\tput delpodulators are
m.atclied and produce ,i4,enticilJ output' voltages, the
vOltage at pin 11 (referenced to pin 17, the output
comm<)n)'is eq ual to the voltage at pin 10 (referenced to
pitj,,3,'the input common). In the, output stage, output
ampiifier A2 is connected as a tinity gain buffer, thus the
output voltage at pin 15 equals the output demodulator
voltage at pin II. The end result is an isolated output
voltage at pin 15 equal to the input voltage at pin 7 with
no gaivilnil; coniiectiOll between them.
Several amplifier and power' conne(,:tion variations are
'.' .
, .
possible:

ISolation of both signal and power is accomplished with a
single miniature toroid transformer with multiple
windings. A pl!l~e generator operating atapprOld,mately
750kHz provides a two~part voltage waveform to
transformer TI . .one part of the waveform is r~ctifieq. by
, diodes DI through D. to provide'the Isolated power to'the
input and otitpui stages (+V, -v and\l+,.V-).1;tje,p,ther
part of the waveform is 'modulated" with input' s'ignal·
information by' the modulator operating in~o the V 2
winding 'of the transformer.
"
The modulated signal is coupled by windings W6 and W7
to two matched demodulators - one in. the input stage and
one in the outputstajle - whicltgenerlite ide1Jti£~(voltages
at their outputs, pins 10 and II (yolt,ages i~il.ticalwith
respect to their respective common~, pins 3 aiid 17). In the
irlput stage the input amplifier AI, the modulatbr and the
input demodulator are connected' in a negative feedback
loop. This forces the ~oltage atp!n,:6;(.connect as shown

,I. The input stage may be connected in various operational amplifier gain configurations.
2 .. Jhe output stage may be operated at gains above unity.
3. The interllally generated isolated. voltages which
provide power to AI and A2 may be overridden and
external supply voltages used ·instead.
Versatility and its three independent isolated grounds
allow simple ,solutions to demanding analog signal
conditioning problems; See the Installation and
Operating Instructions and Applications sections for
details.

P+

+

VO UT

O.47p F
' Co

i

.------------'--(17'r-r-----'-'O

,FIGURE I. Block Diagiam.

342

SPECIFICATIONS
ELECTRICAL
At +2SOC, V± = 1SVDC and 1SVDC between P+ and po, unless otherwise noted.
PARAMETER

CONDITIONS

I
I

3656AG, BG, HG, JG, KG
MIN

TYP

-I

MAX

I
1

UNITS

ISOLATION
Voltage
Rated Continuous(1), DC
Rate Continuous(2), AC
Test. 1Osec(l)
Rejection
DC
60Hz, < loon in liP Coml 2)
60Hz, 5kU in I/P Coml2)
3656HG
3656AG, BG, JG, KG
Capacitance(1)
Resistance(1)
Leakag~

Current

3500 ,1000,
2000 17001
8000 ,3000,
G,

OFFSET VOLTAGEIS)
InitiaIl3).3656HG
3656AG. JG
3656BG. KG
vs. Temperature. 3656HG
3656JG
3656AG
3656KG
3656BG
vs. Supply Voltage
3656HG
3656AG, BG. JG. KG
VS. Curren~(6)

VDC

= 10VIV
160
125

dB
dB

6.0 ,6.3,
10'2 110 '2 ,
0.28

dB
dB
pF
!l
pA

108
112

120V, 60Hz

0.5

-

GAIN

Equations
Accuracy of Equations
Initiall3) 3656HG
3656AG, JG, KG
3656BG
vs. Temperature 3656HG
3656AG. JG
3656BG. KG
vs. Time
Nonlinearity
External Supplies used at
pins 12 and 16, 3656HG
3656AG, JG. KG
3656BG
I nlernal Supplies used lor
Output Stage

VDC

V,rms

See Text
G< 100VIV

1.5
1.0
0.3
460
120
60

%
%
%
ppml"C
ppml"C
ppml"C
%

±0.15
±D.l
±O.05

%
%
%

0.02 ,1 + log khrs. '
RA + RF

= Rs;" 2Mn

Unipolar or Bipolar Output

Bipolar Output Voltage
Swing. Full Loadl')

±D.15

%

RTI
1SVp between P+ and P-

±14 + 40/G, , 1
±12 + ,20/G,. 1
±Il +,10/G,'1
±1200 +, 1000/G"1
±150 + ,750/G" 1
±125 + )500/G1I1
±ll0 + .3S0/G, 'I
±15 + .350/G,·1

pVI"C
pV/oC

±I 0.6 + •3.5/G, ·1
±10.3 + ,2.1/G, 'I
±IO.2 + ,2O/G,)1

mVIV
mVIV
mVlmA

±IO.l

+ ,10/G, ,I

±i 10 + 1100/G1Ij X
,1 + log khrs .•

Input Voltage Rangel e)
Linear Operation
Without Damage
Output Current

;N/oC

Supply between P+ and P-

vs. Time
AMPLIFIER PARAMETERS
Bias Current(7)
Initial
VS. Temperature
vs. Supply
Offset Currentl7)
Impedance
Input Noise Voltage

mV
mV
mV
pV/oC
pVI"C

pV

Apply to A I and A2

20

nA
nAI"C
nAIV
nA
Mil II pF
pV, pop
IJ,V, rms

±S
Supply-SV
±8
Supply

V
V
V
V

100
0.5
0.2
5
lOa 115
5
5

Common-mode
Ie = O.OSHz to 100Hz
fa = 10Hz to 10kHz
Internal Supply
External Supply
I nternal Supply
External Supply
VOUT =±SV
±15V External Supply
I nternal Supply
VOUT= ±10V
±15V External Supply
VOUT = ±2V. Vp" p_ = B.5V
Internal Supply

±5
±2.5

mA
mA

±2.S

mA
±1
ISO

Quiescent Current

3-43

450

mA
pA

ELECTRICAL (CONT)

,

At +25°C. Vf;: = 15VDC and 15VDC between P+ and po. unl!>ss otherwise noted.

I

. T.VPc'C

MI.N.

FREQUENCY RESPONSE

:!:3dB Resp6nse

'.

-'

1.3

Direction measured at o'utput
toO.05!\'o

~

"30

"

':Srriall'Slgnal
",.

I

.~

~

UNITS'

"."-

"

~ldl 'Pow,er
Slew Rate
Settling Time

.. :/'.,'

>,;.

3656AG, BG;HG, JG, KG

CONDITIONS

PARAMETER

."

kHz
kHz

"

+0.1. -0.04
500

V/~sec

L

J,tsec

,.-.',

OUTPUT
Noise Voltage IRTII

fB 0.05Hz to 100Hz
fB = 10Hz t.o 10kHz

~sld~al Ripple(9}

),5. 2 + ,22/G, ,2
,jI5 12 +111/Gl,2

,

~V. pop
~V.

POWER SUPPLY IN

rms •

mV, pop

5
aiP+. p-

Rated Performance

15

Voltage, Range(10)
Ripple Current(9)

Derated Performance

8.5
10
14
0.7

,

Average
vS.·Currents from +V. -V, V+, vat +V. -Y. V+. V- pins! 131'

Quiescent Current(11)
Current VS. Load Current(12)
ISOLATED POWER OUT
Voltage, no load

8.5
7.0

15Vbetween p+ and P±5mA 11OmAsumllOad(121
VS. Supply between P+ and P-

Voltage. full load
Voltage VS. Power Supply
Ripple Volta'gel91
No load
Full load

9.0
8.0
0.66
40
80

±SmA load

16
25
18

VDC
VDC
mA.p-p
rnA. DC

mAlmA
9.5
9.0

V
V
VN

200

mY. pop
mY. pop

+85
+70
+100
1-125

°C
°C
°C
°C

TEMPERATURE RANGE
Specification 3656AG. BG·
3656HG. JG."KG
.

-25
0
-55
-65

Operation(10)

Storage! "1
NOTES:
1. Ratingsio parenthesis and between p. (pin 201 and OIP Com (pin 171.
Other isolation ratings are between liP Com and O/P Com or liP Com
and P-

2. May be improved with proper shieiding. Sea,performance Curves.
" ."
"". If output s.wing.is unipolar, or if the oot'put is not loaded, specific_tion
same as if external supply were used.
,
5. Includes effects ·of A1 and·A2 offset voltages and bias currents if
recommended resistors used.
6. Versus the sum of all external currents drawn from V+, V·, +V, ·V

3. Mi\ly.be trimmed t9 z~.~o.

1=1501.
7. Effects of Al and A2. bias currents and offset currents a~e included' in
Offset Voltage specifications.
8. With respect to liP Corn I pin 3.1 for Al and with respect to O/P Com I pin
171 for A2. CMR for A1 and A2 is loodB. typic«1.
9. In configuration of Figure 3. Ripple frequency approximately 750kHz.
Measurement pandwidth is 30kHz.
10. Decreases lineafly from 16VDC at 85°C to 12VDC at 1000t.
11. Instantaneous peak current required from pins 19 and 20 at turn-on is
100mA for slow rising voltages (5OmsecJ ,and 300mA for fast rises

MECHANICAL
CASE. CeramiC

1 ~~~ro'''''O''M'
,

B

WEIGHT. 10 grams 10.35 oz

R

~

t · :J

C

1

10

••

H

[

I

PINS Pin matenal and plating
comnOSltlon to conform to
method 20031solderab,lrtyl of
MIL-STD-883Iexcept
paragraph 3 2 J.

ISOJ,lsecl.
12: Load current is sum drawn from +V. -V. V+. V- 1= hsol.
13. Maximum vp.I~B:ge rating at pins 1 and 4,is ±J.eVDC; maximur:n ,voltage
rating at pins 12 and 16 is ±18VOC.
14. Isolatio·n ratings may degrade if exposed to 125°C for more thEin 1000
hours or 900C for more thanSO,OQO hOUrs.

A

~, ,.JLD
~Fi
,L,J
INCHES
'OIM
A

B

D
C

MILLIMETERS

MI.

MAX

M"

MAX

1.0ao

1.120

2743

28.45

1080

1.1:<'0

73!)'

27.43
5:97

'"

.021

0.46

0.!)3

.050

0.S9

1.77

F

'3;

G

100 SASIC

2.64 BASIC

"

. 1008ASIC

7.54 BASIC

K

,

.150

3.81"

N

.002

A

.100 BASIC

900 BASIC
.010

+V
MOD INPUT
INPUT OEMOD COM
-V.
BALANCE'
A, INVERTING:INPUT
A1 NONINVERTING INPUT
BALANCE
A,0UTPUT·
INPUTDEMOD

6.
1.
8.

S.89

9.

22.86 BASIC
0.05

1.

2.
3.
4.
5.

28.45

.OJS

.350

PIN DESIGNATIONS

0.2!)

10.

254 BASIC

3-44

11. OUTPUT DEMOO
12. V13. A2 NON INVERTING INPUT
14. A2 INVERTING INPUT
15. A20UTPUT
16. V+
17. OUTPUT DEMOO COM :
18. NOPIN
19. P+
20. P-

TYPICAL PERFORMANCE CURVES
All specifications typical at +25°C unless otherwise noted.
PHASE RESPONSE·

SMALL SIGNAL FREQUENCY RESPONSE

nl

+5

iii

0

.

·5

Cl.

I
a:

l..

Jr'

·10

~",;!,~,

r- ~~2=limmvl;i

:60

~

f.

111111111

o~+~v.=~j

lOOk

;
i"

5

:;

4

'">0

~

0

Outpui ~'Wing

6

•••

I"

• • ~.

I,

II

G=looo

.

8

I~~~rtlon

7

2

5

,~

JJlI.o'[
100

'5:

I•
G-l
1k

10k

2.2

1ii
C 1.8

~

c3

'E

j"

o

~
/ ~

1.6
1.4

Z

iJ.

,/

~ 1.0

I

~

/

1.2

>

S
I!

-~

0.8
0.6
-55

·25

llso I see note 12 of electrical specs ~

-55 -25

Jl/:

0
+25 +50 +70+85+100
Temperature rOCI

E 8

,iii 160
~

:5

160

C IS

i140
~ 120

=!!

c 100

i

80

-

~d~

~

..;~

'"

'"

~c"

~

t'

10 100· ·1k
Frequency Hz

il
11
~

4

E 3

".

....- I

\l

I

a: 2

E
E II
.i1

.

:"&.

±V at hsa ~ max

~

-

/

" .~ ~5

+ atl 0-0

--

:;
t--+--t---t-+'~~5f"7~-I8 :;
"':'

-25

~"-: 2.0

,

Z

1

50~

I

Outpu;ttt

1100

·0

2

I

"''''

QUIESCENT CURRENT VS TEMPERATURE

.

~

>

1:

..

II;

,

0;
co

-0

~O
2 Iii
3

Frequenpy (Hz)

1.

~

u"

.~

NOISE VOLTAGE VS FREQUENCY

~'k

7

&6

.!!> 5

..J.II

. ,

Power Supply Voltage P± 'V,

10k

4° 3'c ~4

IWt-l~

38~~~'~0~'~'~~~~~~~'6

8

~ it

8.§

G=loo

4

9

IUM
.AlII'

3

"

OUTPUT VOLTAGE SWING VS TEMPERATURE
AND ISOLATED SUPPLY LOAD

I
11111 I

11111

11111111 I

",

rnto Oo

III
"lMIIi

"

1

1:::::,

90
G,-1 )00"
120
15
0"180
p-l V
21
V
~
24o Vour:= 3OOmV, rms
,JQIJJ
270
100 200 500 1k 2k 5k 10k 20k 50k lOOk
FrequencyrHzl

OUTPUT SWING AND DISTORTION
VS FREQUENCY

8

G,-1

0
"'30 """!iii

lk
3k
10k 30k
Frequency 1Hz>

300

G, -10

~

1\

·20 '-Vp=ISV
V+, V· = +15V,
I I ·15V I I
·25
-30
100

~

=100

~

·15

10

IJ,I}_1

"1i-l \

~

~

.s

OUTPUT SWING VS SUPPLY VOLTAGE

l1r-..,..-r-.,..."T"-"-""'~""

III~

~,I=lio

lOOk

o

2k

4k
6k
8k
Isolation Voltage IVPI

o

10k

" . 'I$'OLATI;Dpp\\(~R eo,NF'~lIR.TIONS

INSTALLATION AND
.OPERATING INSTRUCTIONS
The 3656 is averY versatile device capable of being used in
a variety of isolation. and amplification configurations.
There aTe. se.ver.al fundamental considerahons that
determine configuration and component value constraints:
L Consideration mustbegiven to .the load placed on the
resistance (pin 10 and pin II) by external circuitry.
T~eir output.resistance is IOOkO and a lo~d resistor of
2MO or greater is recommended to prevent"v~ltage
divider loading effect in excess of 5%.
2. Demodulator loa&ngs should be ciosely.matched so
be equal. (Unequal detheir output voltages.
modulator output voltages will produce a gain error.)
At the 2MO level, a matching error of 5% will cause.an
additional gain I;:rrorofO.25%.
3. Voltage swings at demodulator outputs should be
limited to 5V. The output maibe distorted ihhis limit
is exceeded. This constrains .the maximum allowed
gains of the input and output stages.· Note that the
voltage swings at demodulator outputs'are tested with
2MOload fora minimumof5V.
'
4. Total current Mawn from the internal isolated supplies
must be limited to less than ±5mA per supply and
limited to t total of 10mA. In other words, the
combination of external and internal current drawn
from the internal circuitry which feeds tl),e +V, -V, V+
and V-pins should be limited to 5mA per supply (total
current to +V, -V, V+ and V-limited to IOmA). The
internal filter capacitors for ±V are O.OIIJF. If more
than O,lmA is drawn to provide isolated power for
external circuitry (see Figure 12), additional capacitors
are required to provide adequate filtering. A minimum
ofQ.IIJF/mA is recommended.
5.. The input voltage at pin 7 (noninverting input to AI)
must not exceed the voltage at pin 4 (negative supply
voltage. for A,)in order to prevent a possible lockup
condition. A low leakage diode connected between
. pins 7 and 4, as shown in Figure 2, can be used to limit
this input voltage swing,
'
6. Impedances seen by each amplifier's + and - input
.terminals should' be matched to minimize offset
voltages caused by amplifier input bias ciJrrent~:Since
the demodulators have a IOOkO output resistance, the
amplifier input nOl connected to the demodulator
should also see 10011:0.
7. All external filter capacitors .should be, mounted as .
close to the respective supply pins as is possible in
order to prevent excessive ripple voltages on the
supplies or at the output. (Optimum spacing is less tha'n
0.5". Ceramic capacitors recommendeQ.)

will

POWE.R AND SIGNAL
CONFIGURATIONS
NOTE: Figures 2, 3 and 4 are used to illustrate both
signal and power connection configurations. In the
circuits shown, the power and signal configurations ate
independent so that any power configuration could be
used with any signal configuration.

The 3656 is designed with isolation between the input, the
output, and the, power cO.nnect.ions.The internally
generated isolated voltages suppliedt() Aland Azmay be
overridden with external voltages' greater than the
internal supply voltages. Thesb,.twO features of 3656
prOVide a great deaf of versatilit§ ill p'6~sj~le :isolation and
power supply hook-ups;· When ' external' supplies are
.apPlied;the rectifying diodes (OJ through D.) are reverse
bil\sed .and the internal voltage sources are decoupled
from the amplifiers (see Figure\). N.ote, that when
extermil supplies are us~d, they must never be lower thall
, the. internal supply voltage.
Three-Port
The power supply connections in Figure 2 show the full
three-port isolation configuratioll. The system has three
separate grounds with no galvanic connections between
them. The two external 0.471JF capacitors at' pins 12 and
16 filter the rectified isolated voltage at the output stage.
Filtering on the input stage is provided by. internal
capacitors. In this configuration continuous isolation
voltage Tlltings are: 3500V between 'pins 3 and 17;3500V
between pins 3 and 19; I000Vbetween pins 17 and 19:

FIG UR E 2. Power: Three-port Isolation;
Signal: Unity-gain, Noninverting.
Two-Port - BIpolar Supply
Figure 3 shows two-port isolation which uses aft external
bipolar supply with its common connected to the: output
sta,ge ground (pin 17). One of. the supplies (either+ or ,could be used) provides power to the pul~e generator
(pins 19 and 20). The same sort of configuration is
possible with the external supplies connected totlie input
stage. With theconneotion'sllOwn, filtering at pins 12 and
16 is not required. In this, configuration continuous
isolation voltage rating is: 3500VDC between pitis 3 and
17; not applicable between pins 17 and 19; 3500VDC
between pins 3 and 19.

3-46

SIGNAL CONFIGURATIONS
Unity Gal", Nonlnvertlng
The signal path portion of Figure 2 shows the 3656 in its
simplest gain configuration: unity gain noninverting.
The two IOOkO resistors provide balanced resistances to
the inverting and noninverting inputs of the amplifiers.
The diode prevents latch up in case the input voltage goes
more negative than the voltage at pin 4.
Nonlnvertlng With Gain
The signal path portion of Figure 3 demonstrates two cc
additional gain configurations: gain in the otuput stage ~
'and noninverting gain in the input stage. The following CO)
equations apply:
Total amplifier gain:
G= GI.G,=VO~T/VIN
Input Stage:

FIGURE 3. Power: Two-port. Dual Supply;
Signal: Noninverting Gain.

0)

G, = I + (R F/ RA) (Select G, to be less than
5V/full sCale'VIn to limit demodulator output
to 5V)

(2)

RA + RF ~ 2MO (Select to load input
demodulator with at least 2MO)

(3)

Rc = RA

II

(RF + lOOkO) =

Two-Port Single Supply

RA (RF + lOOkO)
RA + RF + 100kO

Figure 4 demonstrates two-port isolation using a single
polarity supply connected to the output common (pin
17). The other polarity of supply for A2 is internally
generated (thus the filtering at pin 12). This isolated
power configuration could be used at the input stage as
well and either polarity of supply could be employed. In
this configuration continuous isolation voltage rating is:
3500V between pins 3 and 17; 3500V between pins 3 and
19; not applicable between pins 17 and 19.

(Balance impedances seen by the + and - inputs
of A, to reduce input offset caused by bias
current)

(4)

Output Stage:
G, = I + (Rx/ RK) (Select ratio to obtain VOl'T
between 5V and IOV full scale with VIN at its,
maximum)

(5)

Rx II RK = IOOkO (Balance impedances seen
by the + and - inputs of A2 to reduce effect
of bias current on the output offset)

(6)

R. = RA + RF (Load output demodulator
equal to input demodulator)

(7)

Inverting Gain, Voltage or Current Input
The signal portion of Figure 4 shows two possible
inverting input stage configurations: current and input
and voltage input.
Input Stage:
For the voltage input case:
G, = -RF/ Rs (Select G, to be less than
5V/full scale VIN to limit the demodulator
output voltage to 5V)
RF = 2MO (Select to load the demodulator
with at least 2MO
Rc = Rs
FIGURE 4. Power: Two-port. Single Supply;
Signal: Inverting Gains.'

II

(9)

(RF + 100kO) = : : tR~F++I~~~~ri

(Balance the impedances seen by the + and
- inputs of A,).

3-47

(8)

(10)

For the current'input case:,

So we willcalcuiate'd; for !OV'outputand 125% of the
maximum input voltage.
:. VOUT = (1.25 x O.I)(GI)(G,)
i.e., 10V = 0.125 x 40 X G,'
:. G,= IOV/5V=2V/V

"(l1)

YOl""!' = -lIN RF - G,

Rc'''' RF

(12)

R~ maybe made larger than 2Mn jfdesited. The rOpF
capacitors, ~re
fdcompensate for the input
'capacitance of Al and tQ insur~ ftequency s,tability.

used

Output Stag~:
The output stage is the same as shown in equations (5),
(6), and (7).
.,

ILiustrati~e Calculati~~s:
.,

Step 6
G, =1 + (Rx/ RK) '7 2;0
:." Rx/ R~ = 1.0
:;, Rx = RK

,

(15)

Step 7
'-,-,

The resistance seen by the + input terminal of the output
s'tage amplifier A, (pin 13) is the output resistance 100kO
of the output Qemodulator. The resistanc,e seen by, thci
(-)inputtermiit,al of A,(pinI4)should ~e matched to the
resistance seen by ihe + inpJlt terminal.

The maximulTl,illput voltage is 100m V. It is desired to
amplify the input signal for maximum accuracy, Noninverting output is desired.
'
Input Stage:
Step I '

The resistance seen by pin '14 is the parallel combination
of Rx and R~.
.:. Rx II RK = JookO
i.e,.(R x - RK/(R x + RK) = 100kO
i.e., R,,/[I + (~K/Rx)] = 100kO
(16)

GI max = 5V j Max Input Signal = 5V/0.IV =50VjY
With the above gain of 50V iV, if the, input ever exceeds
100mV, it would drive the output 'to saturation. Therefore, it is good practic~ to allow reasonable input
Qverrange.
1
,
, So, to allow for 25yc input overrange without saturation
at the output, select; ,
"
G I =40Y;V
'
G t = I + (RF + R,,) = 40
( 13)
:. RF/'R:" = 39

Step 8
Solving equations ('15) and (16) RK = 20k!} and
Rx = 200kO.
Step 9

Step 2
,
R" + R"'forms a voltage divider with the 100kO output
resistance of the demodulator. To limit the voltage
R"
divider loading effect to no more than 5%, R"
should, be chosen to be at least 2MO. For most
applications, the 2 MO should be sufficiently,large for R"
+ R". Resistances greater than 2MOmayhelp decrease the loading effect, but would increase the offset voltage'
d r i f t . -

+

The voltage divider with R" + RF = 2MO is 2MOjt2MO
+ IOOkO) = 2,)(2+ 0.1) =95.2%; i.e., the-percent loading
is 4.8%.
Choose R" + Rr = 2MO
Step 3

(14)

'The otuput demodulator must be loaded equal to the
input demodulator;
:. Rs = R'" +RF = 2Mh
(See equatioil(f4) above in Step 2)

'.

'

Use the resistor values obtained in Steps 3,4, 8and 9, and
connect.the 3656 as shown in Figure 3. '

,OFFSET,TRIMMING
Figure 5 shows an optional offset voltage trim circuit. It is
important that R" + RF = Ro.
CASE I: Input and output stages in low gain,use
output potentiometer (:R,) Ot:lly, Input potentiometer (Rt! may be disconnected. For
example; unity gain could be obta,ined by
setting R" Ro= 20MO, Rc = 100kH, R" =0,
Rx,= 100kO,and RK = x.

=

Solving equatl'ons ('13) and' (14)
RA = 50kO a'nd R" = 1.95MO
Step 4

CASE 2:

Input stage in high gain ,and output stage in
low gain, useinjlut potentiometer (RI) only.
Output potentiometer (R,) may be discon,nected. For example, GT = 100' could be
obtained by setting RF= 2MO: Ro= 2MO
returned to pin 17, RA = 20kO; Rx = 100kO,
andRK=x.

CASE 3:

When it is necessary to perform a two-stage
precision trim (to maintain a very small offset
change under conditions of changing temperature and changing gain in Al and A,), use
step I to adjust the input stage and step 2 for
the outputstage. Carbon compo~ition n:sisc
~ors are acceptable but potentiometers should
be. stable .

The resistances seen by the + and - input terminals otthe
input amplifier Al should be closely matched in 6rder to
minimize offset voltage due to bias currents:
:. Rc = RA II'(RF + IOOW)
= 50kO II (1.95MO +Iook!lj
=!49kO
'
Output Stage:
Step 5
V OUT, ~ Vi" MAX -G I - G,
As discussed in Step I, it is good pra.ctice,to provide 25% '
.input overrange.

3-48

APPLICATIONS
ECG AMPLIFIER
Although the features of the circuit shown in Figu.re 6 are
important in patient monitoring applications. they may
also be useful in other applications. The input circuitry
uses an external. low quiescent current op amp (OPA21
type) powered by the isolated power of the input stage to
form a high impedance instrumentation amplifier input
(true three-wire input). RJ and R, give the input stage
amplifier of the 3656 a noninverting gain of 10 and an
inverting gain of -9. RI and R2 give the external amplifier ~
a noninverting gain of I + 1/9. The inputs are applied to ~
the nqninverting inputs of the two amplifiers and the
composite input stage amplifier has a gain of 10.

FIGURE 5. Optional Offset Voltage Trim.
Step I:

I nput stage trim (R A = Rc = 20k!}. R" = R" =
20M!}. Rx= lOOk!}. RK =~. R2disconnected);
AI high. A210w gain. Adjust RI forOV ±5mV
or desired setting at VOUT, pin 15.

Step 2:

Output stage trim (R A = Ro = 2OM!l. R('
lOOk!}. RF =0. Rx = lOOk!}. RK =~. RI and
R2 connected); AI low. A210w gain. Adjust R2
forOV ±lmV or desired setting at VOUT, pin 15
(±llOmV approximate total range).
Other circuit component values can be used
with valid results:

Note:

The 330kO. I W. carbon resistors and diodes DI - D4
provide protection for the input amplifiers from defibrillation pulses.
The output stage in Figure 6 is configured to provide a
bandpass filter with a gain of 22.7 (68M!}/ 3M!}). The
high-pass section (0.05 Hz cutoff) is formed by the l!l F
capacitor and 2M!} resistor which are connected in series
between the output demodulator and the inverting input
of the output stage amplifier. The 'Iow-pass section
(100Hz cutoff) is formed by the 68M!l resistor and 22pf
capacitor located in the feedback loop of the output
stage. The diodes provide for quick recovery of the highpass filter to overvoltages at the input. The lOOk!! pot
and the 100M!} resistor allow the output voltage to be
trimmed to compensate for increased offset voltage
caused by unbalanced impedances seen by the inputs of
the output stage amplifier.
In many modern electrocardiographic systems. the

3Mn

R2
IlQcu

Z2pF

LA

looMn
141
HIGH

330lul

I.

RA

33111cu

...

0,

Dr

03

04

LOW

IW

r-~----------------~_~~5wre
NOTES:
I. BAltDPASS o.05Hz TO 100Hz.
.
2. ADJUSTABLE RESISTOR MAY BE USED TO ACHIEVE MAX COMMON-MODE REJECTION BETWEEN LA/RA AND RL.
3. NEGATIVE 15V SUPPLY MAY BE CONNECTED IN PLACE OF D.47pF CAPACITOR IF AVAILABLE.
4. SEE OFFSET TRIMMING SECTION.

FIGURE 6. ECG Amplifier.

3-49

AI = At = Aa"111'21

+11

,111= O,"IIa=D4= IIMIiII

LA

,

an
"

\

i

atn
HI

an
BlooT

:+v

?

HA
33IIIn

R4

IIVIIC

FIGURE 7. Driven Right,Leg ECG Amplifier.
patient is not grounded. Instead, the right-ieg electrode is
connect.ed to the output of an auxiliary operational
amplifier as shown in Figure 7. In this circuit, the
common-mode voltage. on the body is sensed by the two
averaging resistors RI and R2, inverted, amplified, and
fed back to the right-leg through resistor R•. This
negative feedback drives the common-mode voltage to a
low va·lue. Th~ body's displacement current id does not
flow to ground, but rather to the output circuit of A3.
This reduces the pickup as far as the ECG amplifier is
concerned and effectively grounds the patient.

G=louT/Vls = I +
.

RF
. R2
x
A (R 1 + R2 )

~R

•

Rs

lol'T .;;; ±2.5mA
VI. ';;;±4V (compliance)
RI.';;; L6k!l
RF + RA = RI + R2';;; 2M!l
CURRENT OUTPUT - LARGER UNIPOLAR
CURRENTS
A more practical version of the current output function is
shown in Figure 9. If the circuit is powered from a source
greater than 15V as shown,a three-terminal regulator
should be. used to provide 15V for the pulse generator
(pins 19 and 20). The input stage is configured as Ii unity
gain buffer, although other configurations such as current
input could be used. The circuit uses the isolation feature
between the output stage and the primary power supply'
to generate the output current configuration that can
work .·into a .. grounded load. Note that the output
transistors can only drive positive CUTrent into the load:
Bipolar current output would require.a second transistor
and dual supply.

The value of R. should be as ll\rge as practical to isolate
the patient from ground. The resistors R3 and R. may be
selected by these equations:
R3 = (R 1 ,'2) (V". Vo ,) and R. = (Vo, - V~,)/id
(-lOV .;;; V,,';;; +IOV and -IOV';;; VCM ';;; +IOV) .
where V" is the output voltage of A3 and VCM is.the
common-mode voltage between the inputs LA and RA
and the input common at pin 3 of the 3656.
This circuit . has the added benefit of having higher
common-mode rejection than .the circuit in Figure 6
(approximately IOdB improvement).
I

BIPOLAR CURRENT OUTPUT
The'three-port capability ~f the 3656 can be used to .
implement a current output isolation amplifierfuilction,
usually difficult to implement when grounded loads are'
involved. The circuit is shown in Figure 8 and the
following equations apply:

ISOLATED 4mA·TQ 20mA OUTPUT
Figure 10 shows the circuit of a'n expandedversion of the
isolated current output function. It allows any input
voltage range to generate the 4mA to 20m.A output
excursion and is also capable of zero suppression. The
"span"(gain). is adjusted by·Rz and the "zero" (~mA
output for minimum input) is se~ by the 200k!l pot in the
output stage. A threc"terminalSV reference is. ,used to
provide a stable 4mA operating point. The ,reference is

3-50

FIGURE 8. Bipolar Current Output.
connected to insert an adjustable bias between the
demodulator output and the non inverting input of the
output stage.
DIFFERENTIAL INPUT
Figure II shows the proper connections for differential
input configuration. The 3656 is capable of operating in
this input configuration only for floating loads (i.e., the
source YiN has no connection to the ground reference
established at pin 3). For this configuration the usual
2MO resistor used in the input stage is split into two
halves, RF and RF-. The demodulator load (seen by pin
10 with respect to pin 3) is still2MO for the floating load
as shown. Notice pin 19 is common in Figure II whereas
pin 20 is common in previous figures.
SERIES STRING SOURCE
Figure 12 shows a situation where a small voltage, which
is part of a series string of other voltages, must be

FIGURE 9. Isolated I to 5YIN/4 to 20mA lou'.
measured. The basic problem is that the small voltage to
be measured is 500V above the system ground (i.e., a
system common-mode voltage of 500V exists). The
circuit converts this system CMV to an amplifier isolation
mode voltage. Thus, the isolation voltage ratings and
isolation-mode rejection specifications apply.
IMPROVED INPUT CHARACTERISTICS
In situations where it is desired to have better DC input
amplifier characteristics than the 3656 normally provides
it is possible to add a precision operational amplifier as
shown in Figure 13. Here the instrumentation grade
Burr-Brown 3510 is supplied from the isolated power of
the input stage. The 3656 is configured as a unity-gain
buffer. The gain of the 3510 stage must be chosen to limit
its full scale output voltage to 5Y and avoid overdriving
the 3656's demodulators. Since the 3656 draws a

}~
}.,

RI·
~

Ra

lie
+

V,.

'OUT

.RL
7

FIGURE 10. Isolated 4mA to 20mA lOUT.

3-51

Vour =[VIN + I5OOVI1MRIII + (RF/RAII
RA +Rp 2Mn

FIGURE I I. Differential Input, Floating'Source. '

,FIGURE '12. Series Source.

significant amount of supply current, extra filtering for
the input supply is required as shown (2.x 0.47/lF).

between the 3656 and sensitive components may not give
sufficient attenuation by itself. In these applications the
, use of an electromagnetic shield is a must. A shield,
Burr-Brown lOOMS, is specially designed for use with
the 3656 package. Note that the offset voltage appearing
at pin 15 may change by 4m V to 12mV with use of the
shield; however, this can be trimmed (see Offset Trimming section).

ELECTROMAGNETIC RADIATION

The transformer coupling used in the 3656 for isolation
makes the J656 a source of electromagnetic radiation
unless it is properly shielded. Physical, separation

+
Vour

+
-

-:;:-

~IGURE 1'3. Isolator for. Low-Level Signals.

3...;52

-,15V

ANALOG CIRCUIT FUNCTIONS

Analog circuits act as building .blocks with which to perform a variety of
instrumentation, computation, and control functions. They provide a broad
range of versatile, proven, and ready to use computational function circuits
for the designer to use in developing simple or complex systems. The analog
circuit functions include multjplers, dividers, multifunction converters, true
rms-to-DC converters, logarithmic amplifiers, voltage and window comparators, peak detectors, precision oscillators, and filters. The multifunction
converter also provide multiply, divide, square root, exponentiate, roots,
sine, cosIne, arctangent, vector magnitude RMS-to-DC and logarithmic
amplifier functions.
The availability of these relatively complex functions as precise, versatile,
easy-to-use,low-cost building blocks has broadened the scope of practical
analog circuit systems and greatly simplified analog circuit designs. The
names of most analog ci rcu it functions are self-explanatory and descri be the
main functions they perform.
The functions are used mostly for processing (handing) and/or conditioning
of analog signals; and usually (though not always) for simulation of
algebraic and/or trigonometrically expressed analog computations. The
variety of applications'these functions are effectively used for, are limited
only by the designer's creative imagination. Some of the interesting
appl ications where analog circuit functions have found wide acceptance are
listed in the table on the following page.

4-1

Types of Applications
...Recommended Analog Circuit Function
M'uhiplier, Diyider, Multifunction
Analog simulation.
Algebraic and trigonometric computations. Converter, Logarithmic Amplifier,
Oscillator.
Power series approximation, function
. fitting and lil'learizing
Analog wave shaping.
Multiplier, Divider.
VC0and AGC applications.
Multifunction Converter, Multipli.er.
Vector computation.
:Muitiplier, RMS-to-DC Converter.
Power and energy measurements.
Multiplier, Divider.
Moduation and demodulation.
Logarithmic Amplifier.
Signal compression:
Lqgarithmic Amplifier.
Log-antilog-log ratio computations.
Light-related measurements.
Logarithmic Amplifier.
All circuit functions.
Analog signal conditioning.
Instrumentation and control systems.
All circuit functions.
All circuit functions.
Variety of test equipment.
Osdllator.
Transducer excitation
Signal reference.
Oscill'i\,t,pr.
Alarm circuits.
Voltage' and Window Comparators.
Bang-bang control applications.
Voltage and Window Comparators.
Control of limit stops.
Voltage and Window Comparators.
Analog memory and peak detection.
Peak Detection.
,

.'

.

4-2

SELECTION GUIDE
MULTIPLIERS/DIVIDERS

You can select, accuracy from 0.25% to 2% max from
this complete line of integrated circuit multipliers. Most
provide full four-quadrant mUltiplication. All are laser-

trimmed for accuracy-no trim pots are needed to meet
specified performance. These compact models bring the
cost of high performance down to acceptable levels.

MULTlPLIERS/DIVIDERS

Model 11 )

Error
max
at 25'C
'4. max

Tra,nsfer Function

Coefficient
%/'C

Feedthrough
mV

Offset
Voltage
mV

2
1
1

0,04
0,04
0,04

50
50
'50

20
20
20

Temperature

1%
Bandwidth
kHz

'"

Package

Page

Com
Com
MIL

TO-lOO
TO-l00

TO-l00

4-89
4-89
4-89

Ind
Ind
MIL

DIP
DIP
DIP

4-91
4-91
4-91

40

Com
,Com
MIL

TO-l00
TO-l00
TO-l00

4-89
4-89
4-89

15
5

33
33

Com
Com

DIP
DIP

4-97
4-97

10
7
7

70
70
70

Ind
Ind
MIL

TO-l00
TO-l00
TO-l00

4-103
,4-103
4-103

50
10
7
7

70
70
70
70

Ind
Ind
Ind
MIL

TO-l00
TO-l00
TO-l00
TO-l00

4-22
4-22
4-22
4-22

10
7
10
7

70
70
70
70

Ind
Ind
Ind
Ind

DIP
DIP
DIP
DIP

4-110
4-110
4-110
4-110

4203J
4203K
4203S, (a)

XV/l0

4204J
4204K
42048, (a)

XV/l0

..

0,5
0,5
0,25

0.Q1
0,01
0,02

,10
5
5

15
5
5

32

4205J
4205K
4205S, (Q)

(X, - X.)(V, - V.)/l0

2
1
1

0,04
0,04
0.04

50

20
20
20

40
40

50

XV/l0

0,5
0,25

0,01
0.Q1

10
5

[(X, - X.)(V, - V.)/l0) + Z

1
0,5
0,5

0.008,
0,008
0,008

30

420SJ
4208K
4213AM, (a)
4213BM
4213SM

50

30
30

Temp

Range

40
40,
40

33
33

Sse Military Products

42131MIL Series
MPV100A
MPV100B
MPV100C
MPV100S

[(X, - X.)(V, - V.)/l0) + Z.

±2
±1
±0,5
±0,5

0,017
0,008
0,P08
0,025

4214AP
4214BP
4214RM
4214SM

[(X, - X.)(V, - V.)/l0) + Z

1
0,5
1
0,5

0,02
0,02
0,02
0,02

100
30
30

30
30
30
30

30

"Same as model above.
NOTES: (1) "(a)" indicates product also available with screening for Increased reliability,
+85'C; MIL =-55'C to +125'C,

(2) Com = O'C to +70'C; Ind = -25'C to

SPECIAL FUNCTIONS

This group of models offers many different functions
that are the quick, easy way to solve a wide variety of

analog computational problems. Most are in integrated
circuit packages and are laser-trimmed for excellent
accuracy.

SPECIAL FUNCTIONS

Function

Model

Multifunction
Converter

Logarithmic
Amplifier

j

+,r

Temp
Range

Description

Comments

'"

Package

Page

4301
4302

V(ZlX)m
This f,unction may be used to multiply, divide, raise to powers, take roots
and form sine and cosine functions.

4301 Is hermetically sseled and
shielded in a metal package, 4302 is in
a plastic package, Both units are
pin-for-pin compatible,

Ind
Ind

DIP
DIP

4-114
4-116

LOG100JP

K Log (1,/1.)

Optimized for log ratio of current
inputs, Spacifled over six decades of
input (lnA to lmA), 55mV total error,
0,25% log conformity,

Com

DIP

4-114

4127JG
4127KP

K Log (1,/1 ....)

A more versatile part which contains
an internal reference and a current
inverter, 1% and 0,5% accuracy,

Com
Com

DIP
DIP

4-82
4-82

4340

True rms-to-DC conversion based on
a log-antilog computational
approach,

Laser-trimmed, requires no external
trimming for rated accuracy. Hermeti·
cally sealed 'in a metal package,

Ind

DIP

4-122

EIN'(t)dt

4-3

SPECIAL FUNCTIONS

,j

Temp
Range

Model

Function

4341

+

.tEoN·.(I)dl

Peak,jIlll!5BM
Delm:IOr
4ll85l.'~

Teni'p'

(V)

(rnA)

Range(11

Package

Page'

+13.5/35 .
'+13.5/35 ..
. +1~.5(35.
.. +13.5/35

4.5
4.5
4.5
4.5

Com
Com
MIl.
MIL

TO-99
TO-99

4-30
4-30

+13,S/35
·+13.5/35
+13.5/35·
+13.5/35 .

4.5
4.5.
4.5
4.5

Gam
.,C9m.
. MIL,
MIL

(1) Com = 0 10 +70·C; MIL = -55·Clo +12S·C.

4-4

,~g~::
TO-99

.

.,to,gg·
TO-99

rd:'9s

4,~30', "
4-30 '. :

4-36
4~~,6 J
4-36,
4-36 "

GLOSSARY OF TERMS & DEFINITIONS
Analog Circuit Functions
positive feedback and resulting in different trip points for
the two directions of output transition.

ABSOLUTE-VALUE CIRCUIT
A circuit that produces a unipolar output signal equal to
the magnitude or absolute value of a bipolar input signal.

LOGARITHMIC AMPLIFIER
An amplifier which develops an output voltage that is
proportional to the logarithm of t"e input signal.

ACCURACY
The deviation from the ideal output voltage defined as a
percent of full seale output voltage.

OUTPUT OFFSEt
The output voltage when the inputs are grounded.

COMPARATOR
A device with two stable output states which signal if an
input current or voltage has crossed a threshold. The
threshold may be set by one or more other currents or
voltages, either fixed or variable. .

RMS
The root-mean-square value ofa time-varying signal E(t)
over a time period of T is
Enns = .,jl-.I""/T=->!....
; =[E:-:-(t:-::')P'd:-t

CREST FACTOR
The ratio of the peak value of a time-varying signal to its
rms value.

RMS CONVERTER
A circuit that develops a DC output voltage equal in rms
value to an input signal of arbitrary waveform.

CURRENT LIMITING
Limiting the output current supplied by a circuit for •
protection purposes.

SETTLING TIME
The time required for the output to respond to a step •
input and to settle within some specified error band
around the output final value.

FEEDBACK
The return of a portion of the output signal from a device
to the input of the device.

SLEW RATE
The maximum rate of change of an output voltage when
supplying the rated output.

FEEDTHROUGH
The input offset parameter applicable to multipliers. It is
the output voltage when voltage is applied to one input of
the niultiplier and the other input is at zero.

SMAU SCALE FREQUENCY RESPONSE
The -3d8 output frequency for a small AC signal
(normally IV, pop) input. For mUltipliers, one input may
be held at +IOVDC or -I OVDC and the other input held
at small AC signal.

FULL POWER FREQUENCY RESPONSE
The maximum frequency at which the output will swing
full scale peak-ta-peak voltage into a rated load without
significant distortion of the output.
HYSTERESIS
The transfer response lag of comparators controlled by .

WINDOW COMPARATOR
. A compartor that detects levels within a set range or
window rather than simply distinguishing between levels
above and below a set point.

4-5

,

BURR-BROWN®

DIV100

I~~I

,.'

,

ANALOG DIVIDER
FEATURES

APPLICATIONS

- HIGH ACCURACY

- DIVISION

- TWIJ·QUAORANT OPERATION

• SQUARE ROOT
• RATIOMHRIC MEASUREMENT

-EASYTO USE

• PERCENTAGE COMPUTATION
.TRANSDUCER AND BRIDGE LINEARIZATION'

0.25% maximum error, 40:1 denominator range

Dedicated log~antilog technique
Laser-trimmed to specified accuracy -no
external resistors needed

, -lOw'COST
- DIP pACKAGE

DESCRIPTION
The DIY I 00 is!! precision two-qul/drantanalog
divider Offering superior performance over' a wide
range of denominator inp'ut. Its accuracy is nea'rIy
tWo orders oj' magnitUde better than multipljers used
fordivision. It consists ciffpur operational amplifiers
and logging transistors integrated into a-single
monolithic circuit and a laser-trimmed.' thin-film
resistor network. The electrical charactetisticsof
these, devices offer th~,user gMaranteedaccuracy
without the need for external adjustment - the
DIY I 00 is a complete. single package analog divider.

- AUTOMATIC LEVEL - AND GAIN - CONTROL
• VOLTAGE CONTROLLED AMPLIFIERS
• ANALOG SIMULATION
For those applications requiring higher accuracy
than the DIY 100 specifies the capability for optional
adjustment is provided. These adjustrnents allow the
user to set scale factor. feedthrough. arid output~
referred offsets for the lowest total divider error. ,The DIY 100 also gives the user aprecision. temperature-compensated reference voltage for external
use,
Desigriers of industrial process control systems.
analytical instruments. or biomedicalinstrumenta- '
tion will find the DIY 100 easy to use and also a low
cost. but highly accurate solution to their. analog
divider applications,

VREF

output

Output
NInput

13}----------1>-------~-----'--..,....-'

International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734 - Tel. (6021746-1111 - Twx: 910-952-1111 - Cable: BBRCORP: Telex: 86-6491

SPECIFICATIONS
ELECTRICAL

-

Specifications at TA = +25°C and +Vcc

= 15VOC unless otherwise noted

MODEL

DIV100HP

PARAMETER

CONDITIONS

vs. Supply
Warm·up ti,me to rated performance

AC PERFORMANCE
Small-Signal Bandwidth
0.5% Amplitude Error
0.57° Vector Error
Full-Power Bandwidth
Slew Rate
Settling Time
Overload Recovery

DIV100JP
MAX

MIN

TYP

I

Vo = 10N/O

TRANSFER FUNCTIO'N
ACCURACY
Total Error
Initial
vs. Temperature

TVP

MIN

DIV100KP
MAX

MIN

TVP.

MAX

UNITS

I

RL;;' 10kll
O.25V ~ 0 ~ 1OV, N ~ 10 I
lV';; 0';; 10V. N.;;I 01
O.25V<; 0<; lV. N.;;I 01
0.25V';; 0';; 10V. N.;;I 01

0.7
0.02
0.06
0.15
5

0·· +10V
-3dB
Small-Signal
Small-Signa)
Vo = ±10V. 10 = ±5mA
Vo = ±10V. 10 = ±5mA
,= 1%. .J,Vo = 20V
50% Output Overload

INPUT CHARACTERISTICS
Input Voltage Range
Numerator
Denominator
Input Resistance

N<;IOI
o ;;'+250mV
Either Input

1.0
0.0512,
0.212}

0.3

0.5

0.2

0.25

% FS(11)
% FSOI"C
% FSOI"C
% FSOI%

Minutes

350
15
1000
30
2
15

kHz
kHz
Hz
kHz

V/"sec
J.tsec

4

",sec

25

V'
V
kll

±10
+10

-

>
E

OUTPUT CHARACTERISTICS
Full-Scale Output 1FSO I

Rated Output
Voltage
Current
Current Limit
Positive
Negative

10 =±5mA
Vo =±10V

V
mA
2()(2)
2312)

mA
mA

N =OV

,

370
1

REFERENCE VOLTAGE CHARACTERISTICS RL;;' 10M!!
Output Voltage
Initial
At +25°C
... Supply
Temperature Coefficient
Output Resistance

AMBIENT TEMPERATURE RANGE
Specification
Operating Range
Storage

V

±10
±5
15
19

OUTPUT NOISE VOLTAGE
fa 10Hz to 10kHz
0=+10V
o =+250mV

POWER SUPPLY REQUIREMENTS
Rated Voltage
Operati ng Range
Quiescent Current
Positive Supply
Negative Supply

±10

6.312)

6.6
±25
±50
3

6.912)

±20

VOC
VOC

i12)
10(2)

mA
mA

0
-25

+70
+85

-40

+85

°c
°c
°C

±12 \
5
8

Derated Performance

V

"VN
ppm/DC
kll

'±15

Derated Performance

IJV, rms
rnV, rms

·Same as 01Vl00H.

ABSOLUTE MAXIMUM RATINGS
Supply _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ +20VOC

Internal Power pissipation(3)
Input Voltage Rangel 4)
Storage Temperature Range
Operating Temperature Range
Lead Temperature I soldering, 10 seconds I
Output Short-Circuit Duration(3)(5)
Junction Temperature
~

600mW
+20VOC
-55°C to +125°C
-25°C to +85°C
+300°C
Continuous
175°C

NOTES:
1. FSO is the abbreviation for Full Scale Output.
2. This parameter is untested and is not guaranteed. This specification is established
to a 90% confidence level.
3. See General Information section for discussion.
4. For supply voltages less than ±20VDC. the absolute maximum input voltage is equal
to the supply voltage.
5. Sho·rt-~ircuit may be to ground only. Rating applies to an ambient temperature of
+380 (; at rated supply voltage.

4-7

TYPICAL. PERFORMANCE CURVES
ITA.= +25°C. Vee = ±15VDC unless otherwise noted. I
TOTAl. EARClR va
DENOIomlATOR VOI.-TAGE

TOTAL ERROR va AMBIENT T&MPERATURE

FREQUENCY RESPONSE VS
,DENOMINATOR ~LTAGE

10TAL ERROR va OUTPUT CURRENT

•

1M·

O•

..

~.

~

-

"# 0.4

L.3
~

~.

.... 0.2
.0.

O·010Lc.,.....J...J..J..1.llJ.J,".o-L....L..u.llLII,O·

-'jOUj

,
2

Denominator Volhlg8 'V,

0.10

~

\l

..

~~
'"
~!'.

NOHt.IJ\lEARITY VS
NUMERATOR FREQUENCY

L.

J -,,

J
100

0.01

'.1

tOOk

tOk"

Numerator Frequency 1Hz,

DENOMINATOR FEEOTHAOUGH VS

+,0

If

+,.

"

Numeraloi Frequency HI

Ct.-2OpF
RL~2kO

TRANSIENT RESPONSE

+100

.

0-+10V-

\

10
Denominator Vottage : V

LARGE SIGNAL STEP RESPONSE

LAROe SIGNAL STEP RESPONSe

DENOMINATOR FREQUENCV

i

'\

002

O.O, ......"""U-I....J,..l.JJJL..J....l..J..............
1M

,.~

0.04

·t

\

10k
100tc
Frequency (Hz I

N=Oalnwt
~!I.=2rlOHr:
VcuT '" 10-sinwl

0.00

~,.

,.

(v·

NONLINEARITY va
0.00

Il~~

,..

Denominator Vottage

DENOMINATOR VOLTAGE

AMPLITUDE ERROR VS
NUMERAT~ FREQUENCY

N-2Y,p-p

1

,.

••
Output Current 'mA

SMALL-8IOHAL FREQUENCY RESPONSE

,~
~
!

O-=+25OmV

/

D"'+tOY

Ct.-2OpF

CI.",·2OPF

~+50

",-2"'-

Ii-oo
0

20

+,00
+I!O

II

,\

-10

eo

40

1\

-10

50

80

Frequency 1Hz,

Time ',aNC'

TAANSIENTRESPONSE

OUTPUT NOISE VI DENOMINATOR VOLTAGE

100

0

10

200

I

i ....

1i "~~~~~~~++~

O=+25QmV

Ct.-2o,.F

at

\.

!t
!! •
Ii

100

160

J .un:I+m~~

ri'

200

8

,

1
10
Denomlnetor VOlt. IV·

Timetl'teCl

PIN CONFIGURATION

Denominator voUage ,V

MECHANICAL
ORDER NUMBER

1. Gain Error Adjust
2.0ut"ut
3.-Vee
4. 0 Input Offset Adjust
5. Internally Connected to Pin 1
6. Internally Connected to Pin 14
7. Internally Connected to Pin 8
8. Reference Voltage
9. Denominator IO} Input
10. Common
. 11. N Input Offset Adjust
12. Output OffSet Adjust
13. Numerato'IN} Input
14. +Vee

0"
0"
012
0"
0'·
O.
.0.

40

OUleSCENT CURRENT VS
AMBIENT TeMPERATURE

"'! .
50

30

12rT"~rTTO;rrr~'

1

-100

20

Tlmel,.aecl

'0

II

~

-'00
150

'0
20
·0
'0
50

eo
'0

I Bottom View}

!

DIV100HP
DIV100JP
DlV100KP

CASE: Epoxy
WEIGHT: 2.7 Grams
CONNECTOR: 0145MC

D~M
A

•
0
G
H

.......

INCHES
MIN
MAX

.,

.-

....

20.$1

12.45

12.15

.300

K

.130

L

.3008A8IC

"

....

MIlLIMETERS
MIN
MAX
20.07

.115

.115

•..... .
3.3. ,...

0.53
2.M.ASIC
2.03
2.82
7.62 BASIC

2-0.

..

~.:!!~';n

lrue position within
0010·,0.25mm' RatMMCat
seating plane.

Denotes Pin 1

.1510

.02'

r~Al
IJ

Ambient TemperaluN ,oC

c

.81.

.110
.018
.1008 .... 1<:

"

2.9:Z

~.n
~rH

Pin ··numbers shown.for
reference only. Numbers are
not marked on package .

DEFINITIONS
output amplifier. Individual errors are not specified
because it is their sum that affects the user's application.

TRANSFER FUNCTION
The ideal transfer function for the DIV 100 is:
V""' = 10 N/D
where: N = Numerator input voltage
D = Denominator input voltage
10 = Ir.ternal scale factor
Figure I shows the operating region over the specified
numerator and denominater ranges. Note that below the
minimum denominator voltage (250mV) operation is
undefined.
+10

SMALL-SIGNAL BANDWIDTH
Small-sigr.al bandwidth is the frequency the output drops
to 70% (-3dB) of its DC value. The input signal must be
low enough in amplitude to keep the divider's output
from becoming slew-rate limited. A rule-of-thumb is to
make the output voltage 100mV. p-p. when testing this
parameter. Small-signal bandwidth is directly proportional to denominator magnitude as described in the
Typical Performance Curves.

Vout := +tOV

+8

.

0.5% AMPLITUDE ERROR
At high frequencies the input-to-output relationship is a
complex function that produc!,!s both a magnitude and
vector error. The 0.5% amplitude error is the frequency at
which the magnitude of the output drops 0.5% from its
DC value.

+8

iE:

i

+2

VOul= +4V
VClU1

=+2V

Vout=-tCV

i

VIIII=..zV

I

VOUI =4V

-II

'out "·611

·8

vout=·av

·10

Vtu1 =-I3V

0.570 VECTOR ERROR
The 0.57" vector error is the frequency at which a phase
error of 0.0 I radians occurs. This is the most sensitive
measure of dynamic error of a divider.

FIGURE I. Operating Region.
ACCURACY
Accuracy is specified as a percentage of full-scale output
(FSO). It is derived from the total error specification.

LINEARITY
Defining linearity for a nonlinear device may seem
unnecessary; however. by keeping one input constant the
output becomes a linear function of the remaining input.
The denominator is the input that is held fixed with a
divider. Nonlinearities in a divider "dd harmonic distor.tion to the output in the amount of:
Percent Distortion Percent Nonlinearity

TOTALERROA
Total error is the deviation of the actual output from the
ideal quotient 10N/ Dexpressed in percent of FSO(lOV);
e.g., for the DIV lOOK:
Vout (lIcUmll = Vout (ideal) ± total error.
where: Total error = 0.25% FSO = 25mV.
It represe.nts the sum of all error terms normally associated
with a divider: numerator nonlinearity, denomimator
nonlinearity, scale-factor error. output-referred numerator and denominator offsets. and the offset due to the

=

v'l

FEEDTHROUGH
Feedthrough is the signal at the output for any value of
denominator within its rated range, when the numerator
input is zero. Ideally the output should be zero under this
condition.

GENERAL INFORMATION
WIRING PRECAUTIONS
In order to prevent frequency instability due to lead
inductance of the power supply lines, each power supply
should be bypassed. This should be done by connecting a
IO/oIF tantalum capacitOr in parallel with a lOOOpF
ceramic capacitor from the +Vee and -Vee pins to the
power supply common. The connection of these capacitors should be as close to the DIVlOO as practical.

OVERLOAD PROTECTION
The D I V I00 can be pmteeted against accidental power,
supply reversal by putting a diode( I N400 I. type) in series
with each power supply line as shown in Figure 2. This
precaution is necessary only in power systems that
momentarily reverse polarity during turn-on or turn-off.
If this protection circuit is used, the accuracy of the
DIV 100 will be degraded by the power supply sensitivity
specification. No other overload protection circuit is
necessary. Inputs are internally protected against overvoltages and they are current-limited by at least a IOk!1
series resistor. The output i~ protected against short
circuits to power supply common only.

CAPACITiVE LOADS
Stable operation is maintained with capacitive loads of
up to 1000pF, typically. Higher capacitive loads can be
driven if a 22!1 carbon resistor is connected in series with
the DIVIOO's output.

4-9

TJ= Junction Temperature (output loaded)
TJ* = Junction Temperature (n9)oad)
Tc = Case Temperature
"
T A = Ainblent Temperature
(J = Thermal Resistance
rhis model is obviously not the simple one power source
model that most linear device, rnl!nufacturers give. It is.
however, a more accurate model for a multi device
monolithic or hybrid integrated circuit.

FIGURE 2. Overload Protection Circuit.'

STATIC SENSITIVITY
N~lSpecial

handling isrcquired. The DIV 100 does not use
transistors. Furthermore. all external leads
are protected by resistors against low energy electrostatic
discharge (ESD).
MOS~tvpe

INTERNAL P~WER DISSIPATION

The model in Figure 3 .must be used in conjunction with '
the DIV 100's absolute maximum ratings of internal
, po~er
"

VI> Rx R!'

(2)

In the DIV 100 VR11 = 6.6V. R,,= R, = R".and Rx issuch
that the transfer function is:
(3)
Vo = 10:\ D
where: N = Numerator Voltage
D = Denominator Voltage
Figure 5 is a more detailed circuit diagram for the
DIV 100. In addition to the circuitry included in Figure 3,
it also shows the resistors (R3, R4 , Rg , R., and RIO) used
for level-shifting. This converts the DIV 100 to a twoquadrant divider.
'

Note that the reference voltage is broUght out to pins 7
and 8. This gives the user a precision. temperaturecompensated reference for external use. Its open-circuit
voltage is +6.6VDC, ±0.075V. typically. Its Thevenin
equivalent resistance is Jk!l. Since the output resistance
is a relatively high value. an operational amplifier is
necessary to buffer this source as shown in Figure 6. The
external amplifier is necessary because current drawn
through the 3kO resistor will effect the DIVIOO scale
factor.

The implementation of the transfer function is equation
(3) is done using devices with real limitations. For

example, the value of the D input must always be
positive. If it isn't, Q3 will no longer conduct, A3 will
become open loop. and its output and the DIV 100 output
will saturate. This limitation is further restricted in that if
the D input is less than +250mV the errors will become
substantial. It will still function, but its accuracy will be
less.

t,-J

..._DI_VI_OO_....

Still another limitation" i,s the value of the N input must
always be equal to or less than the absolute value of the D
input. From equation (3) it can be seen that if this

FIGURE 6. Buffered Precision Voltage Reference.

OPTIONAL ADJUSTMENTS
Figure 7 shows the connections to make to adjust the
DIV 100 for significantly better accuracy over its 4O-to-1
, denominator range.
The adjustment procedure is:
I. Begin with RI, R2, and R3 set to their mid-position.
2. With INI = D = IO.OOOV, ±lmV, adjust RI for
Vo +lO.OOOV, ±lmV. This sets the scale factor.
"3. Set D to the minimum expected denominator voltage.
With N
D, adjust R2 for Vo ~IO.OOOV. This adjusts the output referred offset errors.
4. With D still at its minimum expected value, make
N == D. Adjust R3 for Vo = 1O.OOOV. This adjusts the
, output referred offset errors.
5. Repeat steps 2-4 until the best accuracy is obtained.

oo-_ _-6:r'---=~-=li:H__-OV.=101110

=

=

=

4-11

+Vcc

IOkO

FIGURE 7. Connection Diagram for Optional
Adjustments.
.

. TYPICAL AP'PLICATI()~S
CONNECTION DIAGRAM
Figure 8 is applicable to each application discussed in this·
section, except the square' root mode.
.
.

Rsource

<: IOn

· FIGURE 8. Connection Diagram - .Divide Mode:
RATIO METRIC MEASUREMENT
The DIVIOO is useful for ratio metric measurements such
· as efficiency, elasticity, stress. strain, percent distortion,
impedance magnitude, and fractiQ"nalloss or gain, These
ratios may be made fnr instantanenus, average, RMS, nr
peak values ..
· The advantage of using the DIVIOO can be illustrated
froin the example shnwn in Figure 9.

.

FIGURE 10. Ratio, Control nf Water to, Hydrnchlnric
Gas

PERCENTAGE COMPUTATION
A variation of the direct ratiometric measureinents
previnusly discussed is the need fnr percentage cnmputatinn, In' Figure II the' DIV 100 nutput varies as the
percentdeviatinn nfthe measured variable to the standard.

FIGURE 9. Weighing System - Fractinnal Loss.
· The LVDT (Linear Variable Differential Transformer)
weigh ~ell measures the fnrce exerted nn it by the weight
nLthe material in the container. Its nut put is a voltage
proportional to,:
. Fg
W=-·
a

FIGURE II. Percentage Cnmputatinn,
TIME AVERAGING
The circuit in Figure 12 nvercnmes the fixed averaging
interval and crude apprnximatlon nf mnre cnnventional
time averaging sche~es,

where: W = Weight .nf mat!!rial
F= Fnrce
g = Acceleration due to gravity
a = Acceleratinn (acting on body of weight W)

x

In a fractinnalloss weighing system the initial value nfthe
material can be determined by the vnlume ofthe cnntainer
and the density of the material. If this value is then held
·on the D-inputto the DIV 100 fnrSnme time interval; the
· DIVIOO nut put will be a measure of the instantanenus
, fractional Inss:
Loss (L) "" WINSTANTANEOl'S/WINiTiAI.
Nnte that by using. the DivlOO in this applicatinn the
common physical parameters of g and a have been
eliminated from the measurement, thus eliminating the!
need fnr precise system calibration.
The nut put from a ratinmetric measuring· system may
, also, be used as a feedback signal in an adaptive prncess
cnntrnl system. A common application in the chemical
industry is in the ratio cnntrol nf a gas and liquid flow as
illustrated in Figure 10.
'

"
OIVIOO.

T

- If

VOUI=X="T

xdl

0

0

FIGURE 12. Time Averagipg Computation Circuit. '
BRIDGE LINEARIZATION
. The bridge .circuit in Figure 13 is. fundamental to,
pressure, force, strain and electrical measurements. It can
have nne or mnre active ·arms whose resistance is a
runctionof the physical quantity, property, nr cnndition
thaUs being measured; e.g., forc~, of cnmpressiqn. For
the sake nf explanatinn the bridge'in Figure 13 has nnly
one active. arm.

4-12

sends a control signal to the denom[nator input to
maintain a constant output. thus compensating for input
voltage changes.

VEX = excitation

Voltage

FIGURE 13. Bridge Circuit.
The differential output voltage \'" \ is:
VII,' = VII _ V \

-VI.So.

m+o)

a l1ol1lil1~ar func-tiol1 of the resistanc-e c-hange in the
active arm. This nonlinearitylimits the useful span of the
bridge to perhaps ± I 0(;( variation in the measured
parameter.

.PosHlve DC Relerence Voltags
FIGURE IS. Automatic Gain Control Circuit.

Bridge linearization is accomplished using the circuit in
Figure 14. The instrumentation amplifier. converts the
differential output to a single-ended voltage needed
to drive the divider. The voltage-divider string makes the
numerator and denominator voltages:

~=

-\',s6R"
+ 3R",)(2

(2R,

2 V, s K,,,

D=
(2R,

+ 0)

+ 3R,,,)(2 + 0)

VOLTAGE-CONTROLLED FILTER
Figure 16 shows how to use the DIV 100 in the feedback
loqp of an integrator to form a voltage-controlled filter.
The transfer function is:
VOl/liSt _
K
V InC... 1

.and.

TS + I

-

where: K = -R', 'R,

. respecvively.

T

=

'10 R, C
VCIl'IR(o)]

where: R" = DIV 100 numerator input resistance
R,1l = DIV 100 denominator input resistance
Applying these voltages to the [)IV 100 transfer function
gives:
\'
10'>; J) = (2R, + 3R",)(R,,<'») 10

This circuit may be used as a single-pole low-pass active
filter whose cutoff frequency is linearily proportional to
the circuit's control voltage.

which reduces to:
V" = -So
if the divider's input resistances are equal.

Vcontrolo----t

t - -.....- - - Voutls)
82

The nonlinearitv of the bridge has been eliminated and
the circuit output is independent of variations in the
excitation voltage.

Vcontrol;:' +250mV

FIGURE 16. Voltage - Controlled Filter.

SQUARE ROOT
Vout = .JiiiN
81 = Ikll

13

N;:. +IODmV

FIGURE 14. Bridge Linearization Circuit.

AUTOMATIC GAIN CONTROL
. A simple AGC circuit using the DIV 100 'is shown in
Figure I S. The numerator voltage may vary both posi~ive
and negative. The divider's output is half-wave rectified
and filtered by D,. R,. andC,. It is then compared to the
DC reference voltage. I f a difference exists the integrator

FIGURE 17. Connection Diagram for Square Root Mode.

4-13

BURR-BROWNe

LOG100

IElElI

Precision

/LOGARITHMIC AND LOG RATIO~AMPLIFIER
FEATURES

APPLICATIONS

• HIGH ACCURACY
OJ7% FSO max Total Error
over 5 decadas
• GOOD LINEARITY
0.1 %max log Conformity
over 5 deelllas ' \
.EASYTOUSE
PIn-selectable Gains
Internal Laser·trlmmed Raslston
• WIDE INPUT DYNAMIC RANGE
6 Deeldas. 1nA to 1mA

• LOG. LOG RATIO AND ANTILOG
COMPUTATIONS
• ABSORBANCE MEASUREMENTS
• DATA COMPRESSION .
• OPTICAL DENSITY MEASUREMENTS
• DATA LINEARIZATION
• CURRENT ANO VOLTAGE INPUTS

VOUT = KLOG

I,

,.--'II""------4--+--i. z :~R
TRIM

i2

RESlSTOII VALUES NOMINAL ONLY,
LASER-TRIMMED FOR PRECISION \lAIN.

DESCRIPTION
The LOG I00 uses advanced integrated circuit technologies to achieve high accuracy, eaSe of use, low cost,
and small size .. It is the logical' choice for your
logarithinic-type computations. The amplifier has
guaranteed maximum error specifications over the
full six-decade input range (I nA to I mAl and for all
possible combinations of II and h. Total error is
guaranteed so that inv,olved error computatio~s are
not necessary.
The circuit uses a specially designed compatible thinfilm monolithic' integrated circuit which contains
amplifiers, logging transistors, and low drift thinfilm resistors. The resistors are laser-trimmed for

maximum precision. FET inP!lt transistors are used
for the amplifiers whose low bias currents (IpA
typical) permit signal currents as low as InA while
maintaining giJaranteed total errors of 0.37% FSO
maximum.
Because scaling resistors are self-contained, scale
factors of IV, 3V or SVper decade are obtained
simply by pin selections. No 'other resistors are
required for log ratio applications. The LOG 100 will
meet its guaranteed accuracy with no user trimming.
Provisions are made for. simple adjustments of scale·
factor, offset voltage, and bias current if enhanced
performance.is desired.

1nl8nlllllllal Airport Induslrlll Parte· P.D.Box 11400· Tuclon. Arizona 857:!4 - T.I.I61121 746-1/11 -Twx: 910-952-1111 - Cable: BBRCDRP -Telex: 66-8491

SPECIFICATIONS

ELECTRICAL

Specifications at TA == +25°C and ±Vcc = ±15V unless otherwise noted,
PARAMETER

Initial

Over Temperature

.TYP

MIN

MAX

UNITS

0.1
0.25

%
%
%/oC
%/OC
Vldecade
%
%fOC

±55
±30
±25
±20
±25
±30
±37

mV
'mV
mV
mV
mV
mV
mV

VOUT = K Log 11,/121

TRANSFER FUNCTION
Log Conformity Erron')

I

LOG100JP

CONDITIONS

Either h or 12
InA to 100~A ,5 decades I
InA to lmA /6 decades I
1nA to 1OO~A /5 decades)
InA to lmA 16 decades>

0.04 .
.0.15
0.002
0.001
1.3.5
0.3
0.03

K Range/2)

Accuracy
Temperature Coefficient
ACCURACY
Total Error/3)
Initial

K = 1,(4) Current Input Operation
1,.12=lmA
h. 12 = loo~A
I,. ~2 = 10~A
h. 12=I~A
h. 12 = loonA
h. 12 = 10nA
h.12=lnA

vs Temperature

h.12=lmA
h. 12 = loo~A
I,. 12= 10~A
h. 12= I~A
h. 12 = loonA
h. 12 = 10nA
h. 12= InA

±a.20
±0.37
±0.28
±a.033
±a.28
±a.51
±1.26

mV/OC
mV/oC
mV/oC
mV/oC
mV/oC
mV/oC
mV/oC

vs Supply

h.12=lmA
1,.12 = lOO~A
I,. 12= 10~A
h. 12= l/
OffSet Voltage
Initial

±0.7
±80

±5

1
doubles every l00C
3
0.5

5(5)

VB Temperature
Bias Current

Initial

vs Temperature
Voltage Noise
·Current Noise

10Hz to 10kHz. RT!
10Hz to 10kHz. RTI

I

I

mV
~V/OC

pA
IAV, rms

I

pA,rms

AC PERFORMANCE
3dB ResponsaCe). 12 = 1O~A
InA
I~A
lO~A

lmA
Step Response(6)
Increasing

=4500pF
=150pF
=150pF

Cc
Cc
Cc
Cc =

50pF

kHz
kHz
kHz
kHz

11
7
110

~sec

4.5
20
550

Ilsac

Cc = 150pF

I~AtolmA

loonA to IliA
10nA to 100nA
Decreasing
lmA to I~A
I~A to loonA
1oonA to 1bnA

0.11
38
27
45

~sac

#lsec

Cc = 150pF
~.ac

I'sec

OUTPUT CHARACTERISTICS
Full Scale Output I FSO'
Rated Output
Voltage

Current
Current limit

lOUT = ±5mA
VOUT= ±10V

±10

V

±10

V
mA

±5
12.5
15
0.05

Positive
Negative
Impedance

mA
mA

0

POWER SUPPLY REQUIREMENTS
Rated Voltage
Operating Range
Quiescent Current

±15

Derated Performance

±12
±7

4-15

±18
±9

I

VDC
VDC
mA

ELECTRICAL.(CONTD}

..

Spec.'ficatlon$atTA= 425°C and ±Vec = ±1511Ilnless'0IhelWise noled.

I

:PARAMETER

COND,TIONS

I

MIN

I

-40
-40

I

TYP

I

MAX

,f

.+70

I

UNITS'

AMBIENT TEMPERATURE RANGE
Specification
. Operating Range
.Storage

0
Derated Pertormance

I

I

+85
+85

I

°C.
°C
°C

NOTES:
1. Log Conformity Error is the p.eak deviation from the best-fit straight line of the VOUT vs Jog liN curve expressed as a percent of peak-ta-peak full
scale output.
2. May be trimmed to other values. See Applications section.
a,'The worst-case Total Error for any ratio of 11/12 is the largest of the two errors when hand 12 are considered separately.
4. Total Error at other values of K rs K ti mes Total Error for K = 1,
5. Guaranteed by design, Not directly measurable due to amplifier's committed configuration.
6. 3dB and Iransient response ara a function of both ttie compensation capacitor and the level of input current. See Performance Curves.

'ABSOLUTE MAXIMUM RATINGS
Supply
±18V
Internal Power Dissipation
600mV
lOrnA
Input Current
±18V
Input Voltage Range
. Storage Temperature Range
-55°C to +125°C
Lead Temperature (soldering 10 seconds!
+3000C
Output Short-.circuit Duration
Continuous to ground
175°C
Junction Temperature

PIN CONFIGURATION
1.I,INPUT
2. SCALE FACTOR TRIM
3. K= 1
4. K=3
5. K=5
6. +Vec
7. OUTPUT
8. NO INTERNAL CONNECTION
9. -Vee
10. COMMON
11. NO INTERNAL. CONNECTION
12. NO INTERNAL CONNECTION
13. NO INTERNAL CONNECTION
14.I,INPUT

SCALE FACTOR PIN CONNECTIONS
K. Vldecade

Connections
5to 7
4t07
4 and 5to 7
3 t07
3and5t07
3 and 4 to 7
3 and 4 and 5 to 7 .

1.9
1
0.85

0.77
0.68

ORDER NUMBER: LOG100JP
CASE: Epoxy
WEIGHT: 2.7 grams
CONNECTOR: 0145MC
NOTE:
Leads in true position within

0.010" rO.25mm I Rat MMC at
seating plane.

o
G

10
2°
30
4°
5°

09

60

o 8

7'

I

Bottom View I

FREQUENCY'-COMPENSATION
.

MECHANICAL

A

014
013
012
011
010

.790

:810

20.07

20.57

.490
.190

.510
.260

12.45

.01a

.02'

0.46

12.95
6.60
'0.53

4.83

.100 BASIC

2.54 BASIC

.080
.130

2.03
3.30

.115
.300

2.92
7.62

.300 BASIC

7.62 BASIC

.080

2.03

.115

Ce

2.92

Pin numbers shown tor
reference only. Numbers ar~
not marked on package.

4-16

I'

PERFORMANCE CURVES
I Typical at TA = +25°C. Vee

NORMALIZED TRANSFER
FUNCTION

= ±15VOC unless otherwise noted.]

ONE CYCLE OF NORMALIZED
TRANSFER FUNCTION

TOTAL ERROR VS
INPUT CURRE'NT

11K I
-

>

31K

I,

VOUT = K

~ 2lK
~
~ 11K

Log

:;
~

0

o

~ M11K I

~ -21K

V

/

~ -31K I

/

i;

L

V

±75

;;; 0.9(K 1

i

/

~

O.SIK I

/

'6 0.7IK
~

O.6IK

/

Cl

:; 0.51K

o

0.31K

E

(; O.2IK I

z
10

0.001 0.01 0.1

O..lIK

o/

100 1000
I,

/

IL

/

1M

.1. .1

~ +20

:;

il
~

0

~

-10

/

1mA

,.........,r---r-.......-..,...-.,---,

lOOk ~-+---t-;""""+'-r--+--+--"I:''' ~:::

br~~--7'1~""~'~lm",AlmA

e-IOOkl--'--r---f--'-;--+-+''''''-I

40(5
~10k~~~~~~r-~~~~-i

I

I

30t
N

11

0+10

I

l00nA
1OI'A
Input Current (h or 12)

50U:

I
I

-

I

3dB FREQUENCY RESPONSE
MINIMUM VALUE OF
COMPENSATION CAPACITOR

Gain Error ~nd
+50 r-Offset Error Trimmed

+40

lnA

Current Ratio, i;

'2

g+30
w

6.0 S.O 10

3.0 4.0
I,

TRIMMED OUTPUT ERROR
VS INPUT CURRENT

~

I

o
2.0

1.0

.

Current Ratio,-

taZero.

-- ...... ...... ..... ......

/

~ O.4IK
~

/

-20~

lkl--'~-r-~1--~~~£-~~~

~

10

~

a

V

Jl 100r-+:-~-t-:.~"bo~-7"~'-if--I
ll!

~

+105 10
(.)

-20

lnA

+20

l00nA
10"A
1mA
Input Current (I, or 121

lnA

10nA 100nA l"A lOIlA tOOIlA ImA
Input Current. 12

THEORY OF OPERATION
I

The base-emitter voltage of a bipolar transistor is
YIlE

= YT fu t
I

where:

YOlJ/ = VI' I!n ..J and since

(5)

Qn X = 2.3 loglO X

(6)

I
Yom! = n VI' log ~

(7)

I~

VI' = KT
q

K = Boltzman's constant = 1:381 x 10-23
T = Absolute temperature in degrees Kelvin
q = Electron charge = 1.602 x 10- 19 Coulombs

where

I, = Collector current

R,

\, = Reverse saturation current

R,

(3)

If the transistor~ are matched and isothermal and VI'I
YT2 , then (3) becomes
I,

(9)

I-

I

n YT log ~

(10)

or

Substituting (I) into (2) yields

II

+ R~

= --R-

(2)

Yotrr '= YT[Qn- -Qn[-]
Is
$

+ R~

Y OUT = Yom! ~-R-,-

From the circuit in Figure I, we see that
YewI" = YaE, - YaE~

(8)

n = 2.3

also

'i'

(4)

4-17

I

YOUT = K log::l
.
12

(,II)

It should be noted that the temperature dependance
associated with YT= KT jq is compensated by making RI
a temperature sensitive resistor with the required positive
temperature coefficient.

,

:TOTAt.;ERAOR
The total error is the deviation (expres~ed in mY) of the
actual output from the 'ideal output of Von' = K log
(II/h). Thus, ,'",
' " .. '
' ,
VOl''!' (AtT!'ALI = VOlT (IilEALI ± Total Error.
It represents the sum of all the individual components of
error normally associated' with the log amp when pperated
in the current input mode. The worst-case error for any
given ratio of II /h is the largest oethe two errors when I,
and h are considered separately.

,II

VOUT = K LOG Ii

FIGU'RE I. Simplified Model of Log Amplifier.
',,;.

D~FINITION

Example
I, varies over a range of! OnA to I/-IA and b varies
from WOnA to IO/-IA. What is the maximum error?
Table I 'shows themaxiinum errors for each decade
combination of I, and h.

OF TERMS

TRANSFER
FUNCTION
,
I
The idea,l transfer function is VOIrI' = K log ~
, where
K

= the scale factor with units of volts/ decade

II

= numerator input current

TABLE I.

I,/I~

and Maximum Errors.
II
1max error)·

10
12
max error!*

'8

8

l00nA
l25mV,

120mV'

l00nA
125mV,

0.1
!30mv)

1
125mV,

10
125mV,

l~A

0.01
130mVI

0.1
125mvl

l20mVl

0.001
130mV,

0.01
125mV,'

"0.1
,25mV,

i!:. 2
'8

I 25mV ,

InA

.2

~

.6

10,.A

__._--_.-IOO~A

Since the largest value of I I / h is 10 and the smallest is,

ImA

(1.001, K is set at 3V per decade so the output will range

~

from +3V to -9V. The maximum total error occurS'\\lhen
I, = IOnA and is equal to K x 30mV. This represents a
0.75% of peak-to-peak FSO error (3 x 1°2°30 ) x I00% ~

VOUT =K log i2

·8

12=I~A

·1 U

Fixe VIIut DlIz

0.7Y;i wh~re the full s~ale output is 12V(from +3V to
-9V).

FIGURE 2. Transfer Function with Varying K and II.

ERRORS RTO AND RTI
As with any transfer function. errors generated by the
function itself may be Referred-to-Output (RTO) or
Referred-to-Input (RTI). In this respect log amps have a
unique property:
Given some error voltage at the log amp's output, that
error corresponds'to a constant per-cent of the input
regardless of the actual input level.'

III
8
8
4

i

2

II

~II+---~~~~~~~~--~--~~~-:::>
~-2

~

-6
-8
·10

1

·Maxlmum errors are In parenthesIs.

IDnA

o+----.--~~--._~~~~~

:>

(20mV,
10~A

4

l~A

lOnA
(30mV,

12 = denominator input current.

II
VOUT=Klog ~

Refer to: Yu Jen Wong and William E. Ott, '~Function
Circuits: Design & Applications"; McGraw-Hili Book,
1976.

K=3
Find VII.. 01 K

FIGURE 3. Transfer Functi()n with Varying 12 and I,.
ACCURACY
Accuracy considerations for a I\>g ratio amplifier are
somewhat more complicated than for other amplifiers.
The reason is that the transfer function is nonlinear and
has two inputs, each of which can vaty 6ver a wide
dynamic range. The accuracy for any combln~tion of
inputs is determined from the total error specification.

4--18

LOG CONFORMITY
Log conformity corresponds to linearity when You'!' is
plotted versus II/ I~ on a semilog scale. In many applications log conformity is the most important specification.
This is true beca~se bias current errors, are negligible
(I pA compared to input currents of InA anda,bove) and
the scale factor and, offset errors may be trimmed to zero
,or removed by system calibration. This leaves log conformity as the major source of error.

The frequency response curves are shown for constant
DC I, and h with a small signal AC current on' one of
them.

Log conformity error is defined as the peak deviation
from the best-fit straight line ofthe VOUT versus 10g(I,/ 12)
curve. This is expressed as a percent of peak-to-peak full
scale output. Thus, the nonlinearity error expressed in
volts over mdecades is
VOI'T (NON!.lIq = K 2Nm volts
where N is the log conformity error, in percent.

The transient response of the LOG 100 is different for
increasing and decreasing signals. This is due to the fact
that a log amp is a nonlinear gain element and has
different gains at different levels of input signals. Frequency response decreases as the gairi increases.

(12)

INDIVIDUAL ERROR COMPONENTS
The ideal transfer function with current input is
Von' = K Log !.t
I,

GENERAL INFORMATION
(13)

INPUT CURRENT RANGE
The stated input range of I nA to I rnA is the range for
specified accuracy. Smaller or larger input currents may
be applied with decreased accuracy. Currents larger than CD
I rnA result in increased nonlinearity. The 10m,A absolute
maximum is a conservative value to limit the power
dissipation in the oUtput stage of A, and the logging
transistor. Currents below I nA will result in increased
errors due to the input bias currenls of A, and A, (I pA
typical). These errors maybe nulled. See Optional
Adjustments_ section.

!

The actual transfer function with the major components
of error is

=:

\

I, - III
Vwr = K( I ± ~K) log ~I
I ±K 2Nm ± Vos
.:! -

Ii,

011'1'

(14)

The individual component of error is
.lK = scale factor error (0.3%. typ)
1o , = bias current of A, (lpA. typ)
Is, = bias current of A, (lpA, typ)
N = log conformity error (0.05%. 0.1%. typ)

FREQUENCY COMPENSATION
Frequency compensation for the LOG 100 is obtained by
connecting a capacitor between pins 7 and 14. The size of
the capacitor is a function ofthe input currents as shown
in the Performance Curves. For any given application the
smallest value of the capacitor which may be used is
determined by the maximum value at J, and the minimum
value of It. Larger values of C(' will make the LOG 100
more stable. but will reduce the frequency response.

VOS OUT = output offset voltage (I m V, typ)
m = no. ,of decades over which N is specified:
0.05% for m = 5. 0.1% for m = 6
Example: what is the error with K = 3 when
I, = lilA and h = lOOnA

10-6 - 10- 12
'
V,wr=3(1±0.003)log _,
_I' ±3(2)(0.000,5)S±lmV
"
10 - 10 (15)
10-6
(16)
"" 3.009 log 10-' + 0.015 + 0.00 I
= 3.009 (l) + 0.015 + 0.001
= 3.025 volts

SETTING THE REFERENCE CURRENT
When the LOG 100 is used as a straight log amplifier 1, is
constant and becomes the reference current in the
expression

(17)

(IS)

I,
V'WI' = K log 1 REI"

Since the ideal output is 3.000V the error'as a percent of
reading is
0.025
% error = -3- x 100%= 0.S3%

IREI' can be derived from an external current source (such
as shown in Figure 4) or it may be derived from a voltage
source with one or more resistors.

(19)

For the case of voltage inputs. the actual transfer
function is
V'_I
R
H,
VOlT = K( I ± .lK) log"
~_I
R, H,

(21)

IREF

r-----------~~r--~----

+ ~
ttl
, +K 2Nm ±Vos 01''1'
+ Eos,
- R,
(20)

6V
+15V----. .-filh

3.11110
, . . -...-...".....-- ·15V

IN834

FIGURE 4. Temperature-Compensated Current
Reference.

FREQUENCY RESPONSE
The 3dB frequency response of the LOG 100 is a function
of the magnitude of the input current levels and of the
value of the frequency compensation capacitor. See
Performance Curves for details.

When a single resistor is used the value may be quite large
when IREF is small. If IREF is IOnA and +15V is used

4-19

A voltage dividermay be used to reduce the value of the.
resistor. When this is do~e one rnustbe aware o{possible
errOrs caused by the amplifier's input offservoltage. This
is shown In Figure 5.

FIGURE 5. "T" Network for Reference Current.

FIGURE 7. Output Offset NUlling.

I n this case the voltage a~ pin I~ is not exactly zero, but is
equal to the value ,of the input offset voltage of Al which
ranges from zerQ to ±5mV. Vr must be kept much larger
than 5mV in order to make this effect negligible. This
concept also applies to pin I.

ADJUSTMENTS OF SCALE FACTOR K
The value of K may be changed by increasing or
decreasing the voltage divider resistor normally connected to the output, pin 7, To increase K put resistance
in series between pin 7 and' the appropriate scaling
resistor pin (3, 4 or 5). To de<;rease K. place a parallel
resistor between pin 2 and either pin 3, 4 or 5.

OPTIONAL ADJUSTMENTS
TheLOG I00 will meet its specified accuracy with no user
adjustments. If improved performance' is' desired the
following optional adjustments may be made.

APPLICATION INFORMATION
WIRING PRECAUTIONS
In order to prevent frequency instability due to lead
inductance of the power sup'ply lines, each power supply
should be bypassed. This should be done by connecting a
IOILF tantalum capacitor in parallel with a 1000pF
ceramic capacitor from the +Vee and -Vee pins to the
power supply common. The connection of these capacitors sho'uld be as close t<;> the LOG I00 as praciicai.

INPUT BIAS CURRENT
The circuit in Figure 6 may be,used to compensate for the
input bias currents of Al and A,. Since the amplifiers
have FET inputs with the' characteristic bias current
doubling every 10"C this nulling teChnique is. practical
only where the temperature is fairly stable.

.Vee

CAPACITIVE LOADS
Stable operation is maintained with capacitive loads of
up to 100pF, .typically. Higher capacitive loads can be
driven if a 220 carbon resistor is connected in series with
the LOG IOO's output. This resistor will, of course, form a
voltage divider with other resistive loads.

lkMll nllllOr available from

Burr·Brown. Order part
IIjImber RF-500.

'

CIRCUIT PROTECTION
The LOG I00 can be protected against accidental power
supply reversal by puttingadiode(l N4001 type) in series'
with each power supply line as shown in Figure 8. This
precaution is necessary only in power' systems that
momentarily reverse polarity d tiring turn-on or turn-off.
If this protection circuit is used, the accuracy of the
LOG I00 will be degraded slightly by the voltage drops
across the diodes as determined by the power supply
sensitivity specification.

FIGURE 6. Bias,Current Nulling.
OUTPUT OFFSET
,
The output offset may be nulled with the circuit in Figure
7; II andb are set equal at some convcn,ient value in the
range of IOOnA to 100ILA RI is then adjusted for zero
output voltage.
,

The LOGIOO uses small ,geometry FET transistors to
. achieve the low input bias currents. Normal FET handling technIques should be used to avoid damage caused
by low energy electrostatic'discharge (ESO),

4-20

b

OPT

=

K oPT =
LOG1OO

J

I, MAX

X

(26)

I, M'N

~

(27)

1 I'MAX
og b OPT

Since K is selectable in discrete steps. use the largest value
of K available which does not exceed KOPT.
NEGATIVE INPUT CURRENTS
The LOG 100 will function only with pOSItive input
currents (conventional current flow into pins I and 14).
Some current sources (such as photomultiplier tubes)
provide negative input currents. In such situations the
circuit in Figure 10 may be used_

FIGURE 8. Reverse Polarity Protection.

LOG RATIO
One of the more common uses of log ratio amplifiers is to
measure absorbance. A typical application is shown in
Figure 9.
Absorbance of the sample is: A = log
If A2

)"

X;

(22)
National
LM394

I,

= A, and D, and D2 are matched A ex: K log 1;' (23)
-Vee

-lOUT

FIGURE 10. Current Inverter.
VOLTAGE INPUTS·
The LOGIOO gives the best performance with current
inputs. Voltage inputs may be handled directly with series
resistors, but the dynamic· input range is limited to
approximately three decades 'of input voltage by voltage
noise and offsets. The transfer function of equation (20)
applies to this configuration.

FIGURE 9. Absorbance Measurement.
DATA COMPRESSION

ANTILOG CONFIGURATION (an implicit technique)

In many applications the compressive effects of the
logarithmic transfer function is useful. For example, a
L.OG 100 preceding an 8-bit analog-to-digital converter
can replace a more expensive 20-bitconverter.

-Vee

SELECTING OPTIMUM VALUES OF 12 AND K
In straight log applications (as opposed to log ratio) both
K and b are selected by the designer. In order to minimize
errors due to output offset and noise it is normally best to
scale the log amp t~ use as much of the ±IOV output
range as possible. Thus. with the range ofl, from I, MIN to
I, MAX:

For II MAX
For I,M,,,

VIN----------..J

+IOV = K log I, MAxlh

(24)

= K log I, MINI \,

(25)

-IOV

+

vOUl =IREF RAnIIlog [- V~NJ

K= 1 whln VIN CDnnlfllBd 10 pin 3
K=3wheft VIN cDIHIllCI8d 10 pin 4
K= 5 whlll VIN clltlIIllCI8d 10 pin 5

FIGURE 11. Connections for Antilog Function.

Addition of these two equations and solving for b shows
that its optimum value. \, (W,. is the geometric mean of
I, MAX and I'M'''.

4-21

MpV100

BURR-BROWN~.

IElElI

MULTIPlJER-DIVIDER'
APPLICATION'S

FEATURES
•
•
•
•
•
•
'.
•
•

• LOW COST
• DIFFERENTIAL INPUT
• ACCURACY 100% TESTED AND
, GUARANTEED
• NO EXTERNAL TRIM,.,ING REQUIRED
• LOW NOISE
9O/JV. rms. 10Hz to 10kHz
• HIGHLY RELIABLEONE·CHIP DESIGN
• DIP OR TO-l00 TYPE PACKAGE
• WIDE TEMPERATURE OPERATION

MULTIPLICATION
DIVISION
SQUARING
SQUARE ROOT
LINEARIZATION
POWER COMPUTATION
ANALOG SIGNAL PROCESSING
ALGEBRAIC COMPUTATION
TRUE RMS·TO-DC CONVERSION

DESCRIPTION
The MPYIOO multiplier-divider is a low cost
precision device designed for general putpose
'application. In addition to four-quadrant
multiplication, it also performs analog square root
and division without the bother of external
amplifiers or potentiometers. Laser-trimmed one-

chip design offers the most in highly reliable
operation with guaranteed accuracies. Because of the
internal reference and pretrimmed accuracies the
MPYlOO does not have the restrictions of other low
cost multipliers. It is available in both TO-IOO and
DIP ceramic packages.

Multiplier Cort

OUT

2,

Al\llllllItIr

2t

MPYIOO,FUNCTIONALBUJCI( DIA8RAM
Internatianal Airport Indultrlal Park, P.O. Box 11400· Tuc.on. Arizona 85734· Tel. (602) 746-1111 . Twx: 9HJ.952·11II • Cable: BBRCORp· Tellx:~-64Q1

4-22

SPECIFICATIONS
ELECTRICAL

-

-

Specifications at TA .::::: +25°C and +Vs - 15VDC unless otherwise noted

CONI)ITIONS

PARAMETER

M LTIPLIER PERFORMANCE
Transfer Function

MIN

TVP

MAX

I

MPV100B/C
MIN

(X, ~ X2~~V' - Y2' + Z2

TVP

I

MPV1DOS
TVP

MAX

UNITS

±0.5
±0.025

±0.05

% FSR
% FSR/oC
% FSR/oC
% FSR/%

±7

±50mV

:to.3

±O.7

MIN

MAX

or

-10V';; X. y,;; 10V

Total Error
Initial
VS. Temperature
vs. Temperature
VS.

I

MPV100A

MOOEL

TA =. +25°C
-25°C ~ T A ~ +85°C
-55°C

~

TA

~

±0.017

±1.0/0.5
to.008/0,008 ±0.02/0.02

±2.0
±D.05

+125°C

'r

±0.05

Supply("

Individual Errors

Output Offset

TA = +25°C

Initial
VS. Temperature
vs. Temperature
vs. Supply(1)
Scale Factor Error
Initial
vs. Temperature
vs. Temperature

±50
±0.7

-25°C ~ TA ~ +85°C
-55°C ~ TA ~ +125°C
TA = +25°C
-25°C ~ TA ~ +85°C
-55°C,;; TA';; +125°C

vs. Supply'"
Nonlinearity

X Input
Y Input
Feedthrough
X Input
Y Input
Temperature
vs. Temperature
VS.

VS.

=

X = 20V. pop; V ±10VDC
Y = 20V. pop; X = ±10VDC
I = 50Hz
X 20V. pop; Y = 0
Y =20V. pop; X =0
-25°C"; T A ,;; +85°C
-55°C"; TA"; +125°C

=

X,

±0.25

'r

±0.12
±0.D08

'r
'r

±0.05

'r

±O.OS
±D.08

'r

100
6
0.1

30/30

0.15

-/'

> X2

SQUARER PERFORMANCE
Transfer Function

I

-10V ,,; X,;; +10V

mV
mV/oC
mV/oC
mV/%
% FSR
% FSR/oC
% FSR/oC
% FSR/%
% FSR
% FSR

30

'I'
'/'

mY. pop
mY. pop
mY. p-p/oC
mY. p-p/oC
mY. p-p/%

'r

IXl - X2'·

Total.Err,!r

:to.D08

'I'

10 !Z2 - Z" + y,

X = 10V
-10V';; Z ';;+10V
X = tv
-tv '" Z,;; +1V
+0.2V';; X ,;; +10it
-10V';; Z ,;; +10V

Totsl Error· with
external adjustments

±50/25
±2.0/±0.7

0.1

Supply'"

DIVIDER PERFORMANCE
Transfer Function

±10/7
±0.7/0.3

±100
±2.0

±1.S

±0.75/0.35

±0.35

% FSR

±4.0

±2.0/1.0

±1.0

% FSR

±S.O

±2.5/1.0

±1.0

% FSR

±D.6/0.3

±0.3

% FSR

'f'
±1/0.S

±0.5

%FSR

IX'1t212+ Z2
±1.2
I

'f'

SQUARE-ROOTER PERFORMANCE

Z, < Z2
tv,,;Z,;; 10V

Transfer Function
Total Error

+Jl0,Z2 - Z, , + X2

I

±21

AC PERFORMANCE

Small-Signal Bandwidth
1% Amplitude Error

1% ,0.57° Vector Error
Full Power Bandwidth
Slew Rate
Settling Time
Overload Recovery

IV~
IV~
~

550
70
5
320
20
2
0.2

Small-Signal
Small-Signal
= 10V. RL = 2kll
= 10V. RL = 2kll

= ±1%, ~Vo = 20V

50% Oulput Overload

'f'
'I'
'/'
'/'
'/'
'/'
'/'

kHz
kHz
kHz
kHz

-

V/,",sec
,",sec
.usee

INPUT CHARACTERISTICS

Input Voltage Range
±10

Rated Operation
Absolute Maximum
Input Resistance
Input Bias Current

'I'

V
V
M!!

'f'

±Vcc

X. Y. Z(2)
X. Y. Z

10
1.4

'I'
'/'

~A

OUTPUT CHARACTERISTICS
.

Rated Output
Voltage

= ±SmA
Vo = ::!::10V

10

Current
Output Resistance

±10
±5

1= DC

V

'f'
'/'
1.5

'/'

6.2
0.6
110
60
1.3

'/'
-/'
'/'
'/'
'/'

mA
II

X-Y-O

OUTPUT NOISE VOLTAGE

1Hz
= 1kHz
1/1 Corner Frequency
Is = 5Hz to 10kHz
Is 5Hz to SMHz

10

'0

=

~V/v,HZ

~V/.JHz
Hz
,",V, rms
mV, rms

POWER SUPPLY REQUIREMENTS

Rated Voltage
Operating Range
Quiescent Current

\

'/'

±15
Derated Performance

±S.5

±20
±5.5

'I'

'/'

4-23

VDC
VDC

'/'

'/'

mA

1-=
>-

Q,.

::IE

ELECTRICAL SPECIFICATIONS (CONT)
MODEL
CONDITION!\
TEMPER TURE RANGE IAmblentl"
Specification
Operating, Range
Storage
NOTES:
,. Includes effects of recommended null pots. "
2, Z2 input resistance is 10MIl, typical, with Vas pin open .. "
If Vas pin is grounded Or used 10r optional offset adjust~ent.
the Z2 input resistance may be as low as 25ktl.
~Same as MPY100A specification.

•I' means B/C grades same as MPV100A specification.

Va

IX,-X211V, ·V21
10

MECHANICAL

-15VDC
CERAMIC DUAL-IN·LlNE PACKAGE

METAL CAN PACKAGE

Order Number:
MPV100AG, MPY100BG
MPV100CG, MPV100sG

Order Number. .
MPV100AM, MPV100BM
MPV100cM, MPV100SM,
Pon

PIN CONFIGURATION
GPACKAGE

rE, :~

L-Ir-

•

i..,,~

I

9-=t-i
Plane

....:... ~o

NOTES:
,. Vos adjustment optional not normally recommended. Vas
pin may be left open or grounded.
2. Ail unused Input pi~s should be grounded.

SIMPUFI,ED SCHEMATIC
NOTE' leads 10 true position wlthm
,0:010 O.25mm. A at MMC ~t
sealmg plane.
INCHES

DIM
A
.C

0

,
G,

MIN
.670

710 •

.170

" MILLIMETERS

MIN

MAX

17.02

18.03
4.32
1.52

.015

,021

1.65
0.3S

.045

.060

1,14

,06'

0.53

.100 BAStC

2.54 BASIC

.025

.070

0.64

,008

.012

0.2Q

,120
L

MAX

10°
,060

0.23

.240

.009

A

8

e
D

1.52

INCHES
MIN
MAX
.335
.305
.165
.016
.010

1.78

0.30
3.05
6.10
7.62 BAStC
10"

.300 BASIC

M

DIM

G
H

.370
'.335

B.51
7.75

9.40
8.51

.185
.021
.040

4.1.
0.41
0.25

4.70
0.53
1.02

.010
.04.
.230 SASIC
.034

.•2~

.029

.045

K

.500

M

.120
.1eo
36° BASIC
.110'
.120

N

MILLIMETERS
MIN
MAX

1.02
0.26
5.B4 BASIC
0.71
0.86
0.74
1.14
12,70
3.05
4."
36° BASIC
2,79
3.05

4-24

TYPICAL PERFORMANCE CURVES
TOTAL ERROR VS
AMBIENT TEMPERATURE

~

10

#

5

e

2

'0

Ul

a
c5

InpJt Slgn!1

~

/

0.5

'i

0.1

/

~0.Q1

o SO 100 150
-50
Ambient Temperature 1°C I

0.00 1
10

~
~
~

'"

Q.

E:


.r;

"'"e

100k

"'"
~

~X

0

>

Y~'

\
10M

~

"

IV"

5

-5

0

r--

\

&.

1.0

OUTPUT VOLTAGE VS
OUTPUT CURRENT

80
!Il

~

50

~

40

I

~

I \

X = 12V. p-p
Y=±1OVDC

Y-12V,p-p
X~±1OVDC -

E

4.0

1k

14
10

t,~

~-r"
,,'

, ,"i/

6

0

. S.O

,,-

f..,

I

iJ
2

4 6

8 10 12 14 16 18 20

Power Supply Voltage I ±Vcc 1
SUPPLY CURRENT VS
AMBIENT TEMPERATURE
16

+25°C

__ -55·C

14
SmA Load

- -

E 10

~>-

8:

'""

\

20
100

Positive Common~mode

~ 12

\
10

-r=F="

4

\\

30

10k 100k 1M 10M

INPUT VOLTAGE FOR
LINEAR RESPONSE

2

Frequency 1Hz!

r

1k

:; 8
Q.

I

COMMON-MODE REJECTION
VS FREQUENCY

II
II

100

&
12
c

CL =1150PF

o

"/

• Differential
16 r'P - Negative common-:~

'~

~~L~2kn _1\

-10

I

vFe1thrO~~ I

10

20
18

80
70

20

rt

F~thr~UghI
1

10

---jlnput
,-Output

I

0

III

Frequency (Hzl

2.0
3.0
Time ("secl

100k

X

~

j~

1 I

50

1M

I

10
~

1M

10k

, -, f

100

~
al
u.

1k

Inp~t Sig~al ~ l20v, ~p

LARGE SIGNAL RESPONSE

Small Signal

-5

~

200

Frequency I Hz>

OUTPUT AMPLITUDE VS
FREQUENCY

o

100

500

'""0

~ O.OS

:;'0.02
~ -100

~

~

/

"

,!;

c:

o.

~

'/V
1\

~

"

~ 0.2
'0 1

~ 20J, p-p
/

~

FEEDTHROUGH VS FREQUENCY

1000

10

'0

V

"iii

~

NONLINEARITY VS FREQUENCY
100

16

10k 100k 1M 10M

Frequency I Hz I

Output Current' ±mA I

8

Quiescent f -

6

-

2

o

-100

-50

o

SO

100

150

Ambient Temperature fOCI

ABSOLUTE MAXIMUM RATINGS
Supply
Internal Power Dissipation(1)

Differential Input Voltage(21
Input Voltage Range(21
Storage Temperature Range
Operating Temperature Range
Lead Tempsrature !soldering ..~O seconds.
Output Short-circuit Duration(3}

Junction Temperature

±2OVDC
500mW
±40VDC
±20VDC
-65·C to +1SOOC
-55'C to +12S'C
+3OO"C
Continuous
+1SOOC

NOTES:
1. Package must be derated onBJC = 1S'CIW and BJA = 16SOCIW for the metal package and 9Jc = 3S'CIW and BJA = 22O'CIW for the ceramic package.
2. For supply vonage.. les. than ±2OVDC the absolute maximum input voltage i. equal to the supply voltage.
3. Short-circuit may be to ground only. Ratl'ng applie. to +8SoC ambient for the metal package and +SSOC for the ceramic package.

4-25

APPLICATIO'NS INFORMATION··:~i~.
THEORY OF OPERATION
The MPYlOO is a variable transconductance multiplier
consist:ing ot t)tree·diff~ren.tial voltage:to~llurrent
converters, a multiplier core and an output differential
.
amplifier as illustrat'i:din Figu~e I.

"t

I

"'f",J'

which shows the output voltage to be the product of the
two input voltages, V, and. V •..
Var·iations in I., du.e to' '" cauSti a large common-mode
voltage swing inthe circuh. The errors assoCiated with
this common-mo!ievoltage tan be eliminated by using
two differeiiiial sta'ges in parallel arid cross-coupling their
0lltputs as shown irtFigure.3.

h
~------o~o-------~

+

+o---{
V2

FIGURE I. MPYlOO Functional Block Diagram.

FIGURE 3. Cross-co~pled Differential Stages as Ii
Variable-transconductance Multiplier.

.

The ba~ic principle of the transconductan£e multiplier
can be. demonstrated by the (jifferential stage in Figure 2.
.

,

:

I

.

An analysis of the. Circuit in Figure 3 shows it to have the
same 'overall tranliferfunctl.on as before: .
V" = V,V, (R, V,R,). '
For input voltages larger than V,the.v(lltage-to-current
transfer characteristics of the differential pair Q,. Q, or
Q, and Q4 are no,' iong~r)i.near. ·Instead.their collector
currents are relat~d t()tlle appli~d voltage V, as

"

,----_--
D..

1% AMPLITUDE ERROR

·OPTIONAL BALANCE
POTENTIOMETER

:IE

, -, '1" +VC,C
4701ta
IiOkn .._-_Jo"N'....--~1'" TO THE
IkO-::-',

~

APPROPRIATE

IIIPUT'

'Vee

TERMIIIAl

FIGURE 6. Optional Trimming Configuration.
terminal, as well as the X and Y input ter!l1inlj.ls, should
be grounded, All inputs should be refereneed to power
supply common.
'
Figure 7 shows how to achieve a scale fa~tor larger than
the nominal 1/10. In this case, the scale factor is unity
which makes the transfer function
K,=~,I +'(R" R:~
,L' 10 :J
Vo = KVxVy K(X 1 - X2 )(Y 1 - Y2).'

=

Itis 6~vious from this err()r 'equation that divider error
bec()ines'excessively large for smaJi values of XI - X2• A
IO-!o-I denominator rimge is u5uaily the practicaJ'Iimit,
If more accurate division is required over a wide range of
denominator voltages. an' externally generated voltage
maY be applied to the unused X-input (seeOptionalTrim
Configuration). TO' trim; apply a ramp 'of +IOOmV to
+ I V at 100Hz to both Xl arid Zlif X2 is used for offset
adjustment, otherwise reverse the signal poIa:rity, and
adjustthe trim voltage to minimize the variation in the
output. An alternative to this procedure would be to use
the Burr-Brown DIVlOO, a precis~on log-antilog diVider.
SQUARING

XI

0,1," K"I

X2
MPYlOO
o-"'--7--IYI
~x
Y2
±IOV. FS
_ _ _ _ _ _J

10ka

MPYlOO

V.. ±IOV. FS
OPTIONAL
SUMMING
INPUT.
±IOV. Fa

FIGURE 9, Squarer Connection.

FIGURE 7. Connection For Unity Scale Factor.
This circuit has the disadvantage of increasing the output
offset voltage by a factor of 10 which may require ihe use
, of the optional balance control as in Figure I for some
applications. In addition, this connection reduces the
small signal bandwidth to about 50kHz.

SQUARE ROOT
Figure 10 shows the connection for taking the square root
of the voltage Vz. The diode prevents a latching condition
which could occur if the input momentarily changed
polarity: This latching condition is not a design t1aw in
the MPYlOO, bot occurs when a multiplier is connected
in the feedback loop of an operatioJUlI amplifier to
perform square root functions.

DIVISION
Figure 8 shows the basic connection for two-quadrant
division, This configuration is a multiplier-inverted
analog 'divider, i.e., a mUltiplier connected in the
feedback loop of an operational amplifier. In the case of
the MPYIOO this operational amplifier is the output
amplifier shown in Figure I.

Vo = +
OPTIONAl
SUMMING
INPUT~
±IOV. FS

""--1 X2XI

0-41-'l'.......~-f YI

v10(Z!,ZII +~

MPYIOO

~ ~---fY2

(II CIRCUIT FOR POSITIVE Vz'

+O.2V .. (Z2' Zll ",+IOV

Vx
DENOMINATOR
+O.2VTO
+IOV. Fa
OPTIONAL
SUMMINS
'NPUT.
~
±IOV.FS

VO' ±IOV. FS

OPTIONAL
SUMMING
INPUT. '
±IOV. FS

MPYlOO

""---1 Xi

Vz

x2

L..-r-lYI
Y2

NUMERATOR
±IOV.FS

MPYlOO

(bl CIRCUIT FI\R NE,GAnVE VZ'

FIGURE 8~ Divider Connection.

FIGURE 10. Square Root Connection.

The divider error with a multiplier-inverted analog
divider is approximately
Edi~der"; 10 Emultipli.r! (Xl - X2)

The load resistance Rl. must be in the r\lnge of 10k!}";; R;
,.;; I Mn. This resistance must be in the circuit as it
provides the current necessary to operate, the diode.

4-28

BRIDGE LINEARIZATION

The circuit of Figure 13 has a sensitivity of IV / % and is
capable of measuring 10% deviations. Wider deviation
can be measured by decreasing the ratio of R2/R,.
SINE FUNCTION .GENERAT.OR
71.548kll

Vo = 1001n9V1
5.715kll

;

NOTE: VIhluld b••llarDl II poaslble II minimize divider Irran.
:~ I~: MJ~~:~RlIlD kllII V2 within IhellllJlll vDllIDI

IOkn

FIGURE II. Bridge Linearization.
The use of the MPYIOO to linearize the output from a
bridge circuit makes the output Vo independent of the
bridge supply voltage.

I·IOV., VI ., +IOV ••nd IV =gOI

FIGURE 14. Sine Function Generator.
The circuit in Figure 14 uses implicit feedback to
implement the following sine function approximation:

TRUE RMS·TO·DC CONVERSIONMATCHED TO O.ll25%
RI
R2

V., '" (1.5715V, - O.004317V,'1 (I
'" 10 sin (9Vd.

+ O.OOI398V,')

SINGLE·PHASE POW.ER MEASUREMENT

'" =R5/ 1R.c + Rs!
l' =I-RI Ral/At
INSTANTANEOUS
POWER

FIGURE 12. True RMS-to-DC Conversion.
The rms-to-DC conversion circuit of Figure .12 gives
greater accuracy and bandwidth but with less dynamic
range than most rms-to-DC converters.

'*

FIGURE IS. Single-Phase Instantaneous and Real
Power Measurement.

PERCENTAGE COMPUTATION
IV2,VII
Vo = -V-I-100
VI

MORE CIRCUITS

The theory and procedures for developing virtually any
function generator or linearization circuit can be found in
the Burr-Brown McGraw Hill book "FUNCTION
CIRCUITS - Design and Applications."

I%PERVOLT

+O.2V .. VI ., +IOV

'::"

XI
X2
YI
Y2

REAL POWER

1"'1'1l0nElrmIILrml CDl81

MPYlOO

atn

Ikll

Figure 13. Percentage Computation.

4-29

BURR-IRIj@

'REF10

1~'E3

Precision
VOLTAGE REFERENCE
FEATURES

APPLICATIONS

•
•
•
•
•
•

•
•
•
•
•
•
•

+10.00V OUTPUT
HIGH AC,CURACY, ±O.005V
VERY-LOW DRIFT, 1ppm/o C Rlax
EXCELLENT STABILITY, 25ppml100Dhrs.
LOW ,NOISE,' IiltV p-p; O.lHz to lOH:t
WIDE SUPPLY RANGE, up III 35V

PRECISION CALIBRATED VOLTAGE STANDARD.
TRANSDUCEftEXCITATION
DIA AND ,AID CONVERTER REFERENCE
PRECISION CU~RENT REFERENCE
ACCURATE COMPARATOR THRESHOLD REFERENCE
DIGITAL VOLTMETERS
TEST EQUIPMENT

DESCRIPTION
The REFIO is a precision voltage reference whic'h
provides a +1O.00V output. The drift i~ laser-trimmed
to Ippm/oC max (KM grade) over the ful.1 specification range. This is in contrast to some references
which guarantee drift ov~r a liz:nited portion of their
specification temperature range. The REFIO achieves
its precision without a heater. This results in low
quiescent current, fast warm-up, excellent stability,
and low ,noise.
The output 'can be adjusted with minimal effect on
drift or stability. Single supply operation over 13.5V
to 35V supply 'range and excellent overall specifications make the REFIO an Ideal choice for the most
demanding applications such as precision system
standards, D/ A a.i)d, A/D, references, transducer
excitation, etc.

156kO

COMMON

Inllrnlllllllil Airport IndUllrlal Park, P.O. Box 11400· Tucson. Arlmna 85734· Tel: (6021746-1111 . Twx: 911J.85Z·1111 • Clble,: BBRCORp· Telex: 1I1!"6491

4-30

SPECIFICATIONS
ELECTRICAL
MECHANICAL

At TAo = +25°C,and +15VDC power supply unless otherwise noted,

REF10JM/KM/RM/SM
PARAMETER

CONDITION

MIN

TYP

MAX

UNITS

TAo = +25°C

9.995
-0.100

10.000

10.005
+0.250
1
3

V
V
ppm/·C
ppm/·C
ppml"C
ppml"C

'TO-99 PACKAG):

OUTPUT VOLTAGE
Initial
Trim Range'"

vs Temperature'!': KM
JM
SM
RM
vs Supply (line regulation)
vs Output Current

(load regulation)
vs Time

NOISE
OUTPUT CURRENT

O·C to +70·C·
O·C to +70·C
-55·C to +125·C
-55·C to +125'C
Vee = 13.5 to 35V

0.001

Ic=Oto ±10mA
T.= +25·C

0.001
50

0.002

%/mA
ppm/l000 hrs

6

25

/.IVp-p

3

O.IHz to 10Hz
Source or Sink

INPUT VOLTAGE RANGE

6
0.002

mA

±10
13.5

35

QUIESCENT CURRENT

lour = 0

4.5

WARM-UP TIME

To 0.1%

10

TEMPERATURE· RANGE
Specification: JM,KM'"
RM,SM'
Operating: JM,KM
RM,SM
Storage

%N

'6

V
mA
J,l5eC

0
-55
-25
-55
-65

+70
+125·
+85
+125
+125

·C
·C
·C
·C
·C

NOTES:
1. Trimming the offset voltage will affect the drift slightly. See Installation arid Operating Instructions for
details.
2. The "box method" is used to specify output voltage drift vs temperature. See the Discussion of
Performance section.

NOTE:
Leads in true position w'ithin 0.010"

(0.25mm) R at MMC at seating piane.
Pin numbers shown for reference or.ly.
Numbers not marked on package ..
Pin material and plating compcsition

conform to Method 2003 (solderability)
of MILcSTD-883. (except paragraph 3.2).
il'lCHES . ',.
OiM • MIl'l ~A)f;
.305

.370
.335

C

,,165

.1B!)"

0

'.018"

A.

E

.F
G·
H

ORDERING INFORMATION

,.~

.021
.010
.040
',040'
;010
.200 BASIC

',028

X

M

~T

Performance
Grade Code
- - -=:r_._.
_____
Basic Model Nu_m_b_e_r
J, K:
O°C to +70°C
R, S: -55°C to +125°C
Package Code
TO-99

1r,.1HERS

MIN

MAX

a.S1

9.40

, 7.75

8.51

4.19'

;. 4.70

0,41,'.
0.:25
0,26

0.53
' 1.02
1,Q2 •

5.08 SASIC

.03'

0.71

0.86

.04'

0.74

1.14

J'

.029 .

K

.500:

M

45° BASIC

45 0 BASIC

N

.09"

2.41

.11Q

REF10

t;l1~

12.7

.160
.105

2.79

4.06
2.67

.. WEIGHT: 1 gram

-

PIN CONFIGURATION
. TOP VIEW

ABSOLUTE MAXIMUM RATINGS
Input Voltage ..................... , ........ :. 40V
Power Dissipation at +25° C .. :........... 200mW
Operating Temperature Range
REF10JM/KM , ............. , ... -25°C to +85°C
REF10RM/SM ................. -55°C to +125°C
Storage Temperature Range ..... -65°C to +125°C
Lead Temperature (soldering, 10sec) ...... +300°C
Short-Circuit Protection at +25°C
to Common or +15VDC .. , ........... Continuous

4-31

'Pin 3 Is an unbuffered 6.3V output. Any load wili affect the output
voltage and drift. A load of II'A on pin 3 will typically change the
output voltage by 51JjN and the drift by 0.1 ppm/· C.

TYPICAL PERFORMANCE CURVES
','

~

;:i

;;

~

E

e

,,"'

g

w

POWER SUPPLY REJECTION
.100

RESPONSE TO THERMAL SHOCK
+400

Iii 90
~

+15
+10

c

200

o~

+5
0
-6
-10
-15

,
-200

a:

~~

~ fluorinert bat~1
-400 ~TA=+70"C
0'

"

70

::0
(/)

50

I

40

0

','

15
10
Time (sect

S

80

"'\

80
~
Q.

Device immersed in +7o-C

_

-20

I

VS FREQUENCY

I ' I~ [i

\

,

t\.

"30
20

100

lk

lOtc

Frequency 1HZ!

QUIESCENT CURRENT VS TEMPERATURE

5



0

SD.
S

-50 -25

o +25 +50 +75 +100 +125
TemperaturelOC)

Output Current t mAl

TYPICAL REF10 NOISE

5D.

TYPICAL HEATED ZENER NOISE

RSIOI

5

Q.

S

S

g

g

~

j

.,

~

SII
t;

II

I>

I.~
( _ Nol.. Test Circuit)

0

:

'(5

z

Z

o
IAII z l00v1V
'• • 0.1Hz IIId 1011z
NOISE TEST CIRCUIT

4-32

1_ Noiae Test Circuit)

l00tc

THEORY OF OPERATION
The following discussion refers to the diagram on the
first page'.
In operation, approximately 6.3V is applied to the
noninverting input of op amp AI by zener diode DZI.
This voltage is amplified by Al to produce the 1O.00V
output. The gain is determined by R, and R,: G= (R, +
R,)/ R,. R, and R, are actively laser-trimmed to produce
an exact 1O.00V output. The zener operating current is
derived from the regulated output voltage through R3.
This feedback arrangement provides closely regulated
zener current. R3 is actively laser-trimmed to set the
zener current to a level which results in low drift at the
output of AI. R. allows user-trimming of the output
voltage by providing for a small external adjustment of
amplifier gain. Since the TCR of R. closely matches the
TCR of the gain setting resistors, the voltage trim has
minimal effect on the drift of the reference.

l

VUpPfIr BowId

+10.0007 , - - - - - - - - - - - - - - - - - - ,
I

t
,g

I

I

I

I

I

I

I

I

I

V,r-----------------------~h
Vnomlnlti

+10.0oool----"71''---""7'"7---..---t

J

700pV

Worst-case
AVoul
for

REF10KM

~~------------------------y
I
I

r-----I

I

+9.9993

o

~

VlsJ_
n

JI

r 80URd
___

-

n

___

I

70

2S

(T... )

(T_)

Temperature (OC)

DISCUSSION OF
PERFORMANCE
The REFIO is designed for applil;ations requlflng a
precision voltage reference where both the initial value at
room temperature and the drift over temperature are of
importance to the user. Two basic methods of specifying
voltage reference drift versus temperature are in common
usage in the industry--the "butterfly method" and the
"box method." The REFIO is specified with the, m!)[e
commonly used box method. The "box" is formed by the
high and low specification temperatures and a diagonal.
the, slope of which is equal to the maximum specifi~d
drift.
'
For the REFIO each J and K 'unit is tested at temperatures of O°C, +25°C, +50°C, and +70°C and each R
and S unit is tested at -55°C, -25°C, O°C, +25°C,
+50°C, +75°C, +100°C and +125°C. The minimum
and maximum test voltages must meet this condition:

[

(VOUT mox- VOUT min)/IOV]
Thigh -

FIGURE I. REFIOKM Output Voltage Drift.

INSTALLATION AND
OPERATING INSTRUCTIONS
BASIC CIRCUIT CONNECTION
Figure 2 shows the proper connection of the REFIO. To
achieve the specified performance, pay careful attention
to layout. A low resistance star configuration will reduce
voltage errors, noise pickUp, and noise coupled from the
power s\,\pply. Commons should be connected as indicated being sure to minimize interconnection resistances.
OPTIONAL OUTPUT VOLTAGE ADJUSTMENT
, Optiqoal output voltage adjustment circuits are shown
in Figure 3 and 4. Trimming the output voltage will
change the voltage drift by. approximately O.OIppm/oC

111

X 106 ::5 drift specification

T tow

This assures the user that the variations of output
voltage that occur as the temperature changes within the
specification range T,ow to Thigh will be contained within a
box 'whose diagonal has a slope equal to the maximum
specified drift. Since the shape of the actual drift CUrve is
not known, the vertical position of the box is not exactly
known either. [t is, however, bounded by Vupp" Bound and
VLow" Bound (see Figure I).
Figure I uses the REFIOKM as an example. It has a drift
specification of Ippm/oC maximum and a specification
temperature range of O°C to +70°C. The "box" height
(Vito V,) is 700p.V and upper bound and lower bound
voltages are a maximum of 700p. V away from the
voltage at +25 0 C.

Vee

+

-,..

REFIO

lid'
TANTAlUM

R..

Ru

R...

NOTES:
I. l ..d millanc.. hire a/ up 18 a lew oItlDl ~IVI negllglbll eII1ICI .. parlurllanca.
2. Amlll,nca If 0.10 In .Irla wlttl \ben IIIdi will CIUlla IIiV mar whlll IlIe
lad currenllill Ita mlxlmum allOmA. TIIII raulta In , D.Ol% arrar IIIIOV.

FIGURE 2. REFIO Installation.

per m Vof trUnI,D:ed voltage,. In the.circuit,iG,l'igure 3 any
mismatch in TCR betw~n the, two sections of·tne
,potentiometer will also affeCt drift but the effect of the .
-iTCR is reduced by a 'factor of 40 by the internal
resistor divider. A high quality potentiometer,with good
mechanical stability, such a,s a cermet, should be used.
The circuit in Figure 3, has a range of approximately
; +250mV to:':'IOOmV. The circuit in Figure4 has less
ranl!e bu~ provides higher resolution. The mismatch in
TCR between Rs and:the internal resistors can introduce
some sliglit drift. This effect is ritinimized if Rs is kept
significantly larger than the 156kO internal resistor. A
TCR of IOOppm/oC is norm!llly suffiCiertt.

APP~I~ATI()~J~F'.QRMA,TI:,9N
High accuracy, extremely-low drift, and small size make
t.heREflO i4eal for demanding ins,tnlmentiltion and
system voltage, reference applications. ,Since no heater ,is
required, low power supply current designs are readily
achievable. Also the REFlO has lower output noise and
m~ch faster warm-up times,' than heatc;d refer~nces,
per.mitting high precision without extra powe~ or additi9nal supplies. It should be ,considered that operating
any integrated, circuit at an elevated' temperature will
reduce it~MTTF.
A variety of application circuits are shown in Figu~es 5
'
through ,11.

+Vcc
+V';"

VOUT

t-""6----t--------_D

REFIO

2OkO
OUTPUT
VOLTAGE
ADJUST

REFIO
+Vcc

+IOV

Maximum range 1+2.5%. -1.0%) I,nd minimeidegradation 01 drift

'----,
FIGURE 3. REFIO Optional OutputVoltage Adjust.
,.,.IOV
SEE INFORMATION IN
TYPICAL PERFORMANCE CURVES
IpF
TANTALUM

Tbe,TCR 01 Rs can aflecl VOUT
drill II Rs Is made sIRllt

VOUT
REFIO

6

FIGURE 6. ±IOV Reference.

VTAIM .
5 ~

+IOV

2OkO
OUTPUT
VOLTAGE
ADJUST

Rs·

+Vcc

"lis lypic.,'Y 4Mo

FIGURE 4. REFIO Optional Output Voltage Fine
Adjust.
REFIO

:+vcc

REFIO

Vom=+IOV

Ito

*
C

,

,oo,.,F

10V
''''''=-R- .R~lkO

""

"

,

I"" =-'='1.1Iltz
2>rRC "

fIGURE 7. Positive Precision Current Sourc~.

FIGURE 5. Precision Reference with Filtering.

4-34

35V TD55V

1

REFlD

+Vcc

6

+IOV

+~

REFlD
+Vcc

4

2

REFID

+20V

6

4

FIGURE 10. +5V and +IOV Reference.
12

REF10

~

+Vcc = 24V

+1~

6

2

NOTES:
I. REFID's can be stlcked 10 oblaln voll_gea In
mulllpill of IDV.
2. The supply vollage Ihauld be betwlln IOn +5
and IOn +25 where n Islhe numlier 01 REFlO's.
3. Dulpul currenl of nch REF10 liliiii lUll exead III
rated oulpul currenl II ±IOmA. This Includllihe
current delivered 10 Ihe lower REFID.

REFlO

+IOV
I11III0

AV
FIGURE 8. Stacked References.
I11III0

+Vcc

AI 10.oV. Ihe I1\1III1 brldgl requires IB.7mA. An 8200 resistor cllllll8Cl8d dlrlClly
lrom Ihe bridge 10 Ihe POliti'" supply prlvldea Ihl bulk of Ihe brldgl current.
The REF10 need only IUJIPly sn .ror current 18 knp Ihe bridge 1I1O.DV. Sinci
lhe REFlD can sink or sourca up \0 IOIIIA. Ilia circulllhown un IOlar... IUPply
varllllDlll of up 10 24V. ±BV. or bridge realatanca drift Iram 4lIIIO 10 14lIII0.

+5V
REFID
+Vcc

FIGURE II. +IOV Reference with Output Current
Boost Using a Resistor to Drive
a 6000 Bridge.
-5V

FIGURE 9. ±5V Reference.

4-35

BURR-BROWN®

REF101

11::3E11

Precision
VOLTAGE REFERENCE
FEATURES

APPL.ICATIONS

.+IO.OOV OUTPUT

• PRECISION CALIBRATED VOLTAGE STANDARD

• HIGH ACCURACY. ±O.OO5V
• VERY LOW DIlIFT. I ppm/oC max

• TRANSDUCER EXCITATION
• DIA AND AID CONVERTER REFERENCE

.• EXCELLENT STABILITY. 25ppm/lOOOhrs.

• PRECISION CURRENT REFERENCE

• LOW NOISE. 61' V. POp typo 0.1 Hz to 10Hz

• ACCURATE COMPARATOR THRESHOLD REFERENCE

• WIDE SUPPLY RANGE. up to 35V

• DIGITAL VOLTMETERS

• LOW QUIESCENT CURRENT, 6mA max

• TEST EQUIPMENT

• USEFUL MATCHED RESISTOR PAIR INCLUDED

DESCRIPTION
The REFIOI is a precision· voltage reference which
provides a + IQ.OOV output. The drift is laser-trimmed
to I ppmj"C max (K M grade) over the full specification rarige. This is in contrast to some references
which guarantee drift over a limited portion of their
specification temperature range. The REFIOI'
achieves its precision without a heater. This resuJts in
low quiescent current (4.5mA typ), fast warm-up
(Imsec to O.l%),excellent stability (2Sppm/ IOOOhrs
typ), and low noise (251' V, p-prrtax, 0.1 Hz to 10Hz).
The output can be adjusted with minimal effect on
drift or stability. Additionally, the.REFIOI contains
a matched pair of user-accessible precision 20kfl
resistors which are useful in a variety of applicatioris.
Single supply operation over l3.5V to 3SV .supply
range and excellent overall specifications make the
REFIOI an ideal choice fOT the most demanding
applications such as precision system standards,
·DI A and AI D references, transd.ucer excitation etc.

R4

VTRIM 2 1-"""......
lB5kn

81

VOUT
FEEDBACK

COMMON

RB

International Airport Industrial Park· P.O. Box 11400· TUcson. Arizona 85734· Tal. 1602) 746-1111 . Twx: 911).952·1111· Cable: BBRCORP.· Telex: 66·8491

4-36

SPECIFICATIONS
ELECTRJCAL

At TA::= +25°C and +15VDC power sUpply unless otherwise noted

MECHANICAL

REF101JM/KM/RM/SM
PARAMETER

CONDITION

MIN

TYP

MAX

UNITS

TA = +25°C

9.995
-0.100

10.000

10.005
+0.250

V
V

1
2
3

ppm!OC
ppm/DC
ppm!OC
ppm!OC
%!V

OUTPUT VOLTAGE
Initial
Trim Range(1)
vs T emperature(2)

KM
JM
SM
RM
vs Supply I line regulation I
vs Output Current
Iload regulation I

DOC to+700C
OOC to +700C
-55°C to +12SOC
-55°C to +125°C
Vee = 13.5 to 35V

6

IL "" 0 to ±10mA

vsTirne

TA = +25°C

NOISE

O,IHz to 10Hz

OUTPUT CURRENT

Source or Sink

INPUT VOLTAGE RANGE

0.00025

0.002

0.00025 131
0.001141

0.0021.'

'%/mA
%!mA
ppm!1000 h rs

25

pVp-p

25
6
±10
35

QUIESCENT CURRENT

lOUT =0

4.5

WARM-UP TIME

To 0.1%·

10

TEMPERATURE RANGE
Specification
JM.KM
RM,SM
Operating
JM,KM
RM,SM
Storage

Plan"

mA

0
-55

+70
+125

-25
-55
-65

-u=..

I'

1.1.1

ICC

.
Leads·i~ true position within 0,010"
10.25mml R at MMC,at seating plane.
Pin numbers shown for reference only.

Numbers not marked on package.
Pin material and plating composition
conform to Method 2003 (solderability I
of MIL-STD-863 lexcept paragraph 3.21
:DIM.

°C
°C

+85
+125
+125

--

1

......£..-lJ

NOTE:

kfl
%
ppm!OC
ppm!OC

±D.05

I

,J

/~
- 'Y'

psec

20
±O.OI
50
2

•

~

j

"., "' IIIII

V

6

TO-99 PACKAGE

Lrl!!!1

mA

13.5

UNCOMMlnED RESISTORS
Resistance
Match
TCR
TCR Tracking

rF:~
LJ

,

A

C

°C
°C
°C

,

0

'"

.'"
His

"

18!1

...

",
0"

4S0SAS1C

N

.095

.,
".
'"

MAX

/1[,

'"

""

O!IJ

0<. ."

M

".

M'N
B!>l

,
"
,
,

'00

MILLIMETERS

310

.040
0>'
0>'
,200BAStC
0,"
.03.
.029

H

NOTES: (1) Trimming the offset voltage will affect the drift slightly, See Installation and Operating
Instructions for details. (2) The "box method" is used to specify output voltage drift vs temperature. See
the Discussion of Performance section. (3) Sourcing current. (4) Sinking current.

INCHES
M,"
.MAX

8!>1

."

'0'
o 2~,
'0'
'108 6ASIC

.".,.
1;/7

'"
'"

...

'"
4s"'aASIC
'"

'"

WEIGHT: 1 gram
ORDER: REF101JM, REF101KM
REF101RM, REF101SM

ORDERING INFORMATION

REF101 X M
Basic Model Number--------I,
Performance Grade Code----------'
J K -25°C to +85°C
R', S -550C to +125°C

PIN CONFIGURATION

T

PackageCode----------------------~

(TOPYIEWJ

TO-99

ABSOLUTE MAXIMUM RATINGS
Input Voltage ............................... 40V
Power Dissipation at +25°C .............. 200mW
Operating Temperature Range
REF101 JM/KM ................ -25°C to +85°C
REF101 RM/SM ............... -55°C to +1250 C
Storage Temperature Range ..... -65°C to +125°C
Lead Temperature (soldering, 10sec) ..... +300"C
Short-Circuit Protection at +25°C
To Common or +15VDC ........... Continuous

4-37

I
I
I
I

+~

I
I

I

COMMON'

___

~_~

IL..____ ________20kO

OPTIONAL
VOLTAGE
TRIM

tbi TeR II AS ~n'eiltcl
VOUT drift II RS II wilde
1II1II1..

os. OuljlUt Valllge AdjUllment va RS CUrve.
NOISE TEST CIRCUIT

OPTIONAL OUTPUT VOLTA8£ FINE ADJUSTMENT CIRCUIT.

TYPICAL PEAFORMA"CE CURVeS
-

TVPICAL HEATED ZENER NOISE

'5

.'

"

TVPICAL BANDGAP REFERENCE NOISE

.

l+6"y
S. +4~V

l +2"V
~

j

f

.~
z

I

Low Frequency Noise
lsee Noise Test Circuit)
RESPONSE TO THERMAL SHOCK

POWER SUPPLY REJECTION VS FREQUENCV

100

+400

Iii

~

c

200

o~
-200
~

-400

t4

<

i
c
o

i

1
~

LOAD REGVI,ATION VS
'TEMPERATURE

+3

;c

\
\.

50
40

"

Il.

"-

30

o

5

10

15

20

100

1k

10k

100k

Time(seC)

Frequency/(Hzl

QUIESCENT CURRENT VS TEMPERATURE

OUTPUT VOLTAGE ADJUSTMENT vs Rs

""
~

~ 2

-2

0

-3
-4
'-75

:>

~ 4
C
t::
:>
3
0
C

,

-1

'"'"
Ul

~

<

I

o

--

f'..

"\

';; 70
a:
~ 60

5

~

+2
+1

,

~

90

80

-so -25

-50 -25 0 +25 +50 +75+100 +125
Temperature I'C)

0,+25+50+75+100+125

Temperature I'C)

1oor-~~~~~~~--,

in~

80

I----I~_+~"'+':....

e~ ~i 80 I---+--f-"""",
L __ _
~;4!lI---::.~_P"""""'o:::..

§g
~<

..,

o

2

8

Out~ut

Current I mAl

4.:38

10

100k

1M
RSIOi

10M

100M

ification temperature range of O°C to +70°C. The "box"
height (V, to Y2) is 700~V and upper bound and lower
bound voltages are a maximum of 700~ V away from the
voltage at +25"C.

THEORY OF OPERATION
Thefollowing discussion refers to the diagram on the first
page.
In operation. approximately 6.3V is applied to the
noninverting input of op amp A, by zener diode DZ,.
This voltage is amplified by A, to produce the IO.OOV
output. The gain is determined by R, and R2: G = (R, +
R2)/ R,. R, and R2 are actively laser-trimmed to produce
an exact IO.OOV output. The zener operating current is
derived from the regulated output voltage through R3•
This feedback arrangement provides closely regulated
zener current. R.i is actively laser-trimmed to set the zener
current to a level which results in low drift at the output of
A,. The adjustment of output voltage and zener current is
interactive and several iterations may be used to achieve
the desired results. R. allows user-trimming of the output
voltage by providing for a small external adjustment of
amplifier gain. Since the TCR of R. closely matches the
TCR of the gain setting resistors. the voltage trim has
minimal effect on the drift of the reference.

+1D.0007~---- ___V!!'p~~ao.!.n~ __ ...: ___ ,

Thigh -

X

I

Vneml RlI L------::;~--7""'--"""_t '1OO~V
Wont_

+10.0000·

e:

..Wiut
lor
REF10lKM

I
I

V2~--------------------__Y
I
I
I
I
+9.D9113l---- - - - - - - - - - - _____ J

I

IVLoweraound

o

I

25

(Tlow)

Temperature (OC)

70
(Thigh)

FIGURE I. REF)O)KM Output Voltage Drift.

The REFIOI is designed for applications requmng a
precision voltage reference where both the initial value at
room temperature and the drift over temperature are of
importance to the user. Two basic methods of specifying
voltage reference drift versus temperature are in common
usage in the industry - the "butterfly methodffand the
"box method". Neither of these methods is entirely
. satisfactory in cases where the drift versus temperature is
relatively nonlinear as is the case with most voltage
references. The REFIOI is specified with the more
commonly used box method. The "box" is formed by the
high and low specification temperatures and a diagonal.
the slope of which is equal to the maximum specified
drift.
For the REFIOI each J and K unit is tested at temperatures of O"c, +25"C, +50"C, and +70°C and each R
and S unit is tested at -55"C. _25°C. O°C. +25°C. +50°C.
+75°C. + 100°C and + 125"C. The minimum and maximum
test voltages must meet this condition.
r(Vot·.,. m" - Von' min); lOY]

I

I
:
I

Vlr---------------------~

DISCUSSION OF
PERFORMANCE

L

I

I
I
I

I

INSTALLATION AND
OPERATING INSTRUCTIONS
BASIC CIRCUIT CONNECTION
Figure 2 shows the proper connection of the REFIO I. To
achieve the specified performance, pay careful attention
to layout. A low resistance star configuration will reduce
voltage errors. noise pickUp. and nO.ise coupled from the
power supply. Commons should be connected as indicated being sure to minimize interconnection resistances.'

+
I~F

TANTALUM
(I)

10":;;;; drift specification

T 10w

This assures the user that the variations of output voltage
that occur as the temperature changes within the specification range T,o.. to Thigh will be contained within a box
whose diagonal has a slope equal to the maximum
specified drift. Since the shape of-the actual drift curve is
not known. the vertical position of the box is not exactly
known either. It is, however. bounded by VUppe, Bound and
VLo.." Bound (see Figure I).
Figure I uses the REFIOI KM as an example. It has a
drift specification of I ppm/"C maximum and a spec-

(I)

NOTES,
1. laid mlsllJICII hire II up to Illw ohml hivelllfliialbli aIIlCIDft parlDrllllIlCl.
2. AmaUvely CIIIIIInt IIUITlnllf Ippru. 2mA atlillppm/OC IIawa In 1II1s 1IId.
I n In 11111 Iud WlUld Intrlduuuaut211V emr (1d1u1flblllD ZInI) willi ablUl
0.1 ppm/OC drill at lIIe aulptd.
a ArnllflllCl II 0.1 n In Itrlllwltfllhtliltadl will elu" I I mV mor wilen 1111
load cu~l1ftIllatlllllaxlmum IIIOmA. Thll reaulllin I o.ol'le Irror If IOV. .

FIGURE 2. REFIOI Basic Circuit Connection.

4-39

,". '

OPTIONAL OUTPUT VOLTAGE ADJUSTMENT
,Optional output voltage adjustment circuits are shown in
Figures Jand 4. Trimming the output voltage will change
the voltage drift by approximately 0.01 ppin/"C permV
of trimmed voltage .. In th,e circuit. in Figure 3. any
mismatch in TCR between the two ,sections of the
, potentiometer will also affect ddft but the effe.ct of the
~ TCR is n;duced by a factor of 40 'by the internal resistor
divider. A high quality potentiometer, with good. mechanical stability, such as a cermet, should be used. The
circuit in Figure 3 has a range of approximately+250mV
to -IOOmV. The circuit in Figl,lre 4 has less range but
provides higher resolution. The mismatch. in TCR
between Rs and the internal resistors can introduce some
slight drift. This effect' is minimized if Rs is kept
significantly larger than the l65kO internal n;sistor. A
TCR .of 100ppm/"C is normally sufficient.

APPLICATION:lNFo.,RMATlQN
Highaccur~cy, extremely-low drift: and smaiIsize mak~
the REFIOI ideal for demanding instrumentation and
system voltage reference applications., Since no heater is
required, low power supply current design,s are readily
~chievable. Also the REFIO ( has lower output noise and
much faster warm-up times (ImsectoO.1 %) than heated
r~ferences, permitting high precision without extra power
from additional supplies. It should be considered that
operljting any integrated circuit at an elevated temperature willTeduce its MTTE
. A variety of application circuits are shown in Figures 5'
through 19.

+VCC
.Vi:c
+
I~F

VOUT =+10V

.,.. TANTALUM

V

20kn
OUTPUT
VOLTAGE
ADJUST

+IOV

1
Ico = 2" RC

=1.6Hz

,FIGURE 5. Precision Referencewith Filtering.

\l
MlXlmum rangl (+2.5%. ·1.0%) and minimal dagradlllion 01, drift,

FIGURE 3'. REFIOi Optional O~tput Voltage Adjust.
+Vcc =15V

°RS typically 4Mn.

+Vcc
......- - - - - , +

V

The TCR 01 RScan alflet VOUT
drill If RS Is madJ amall,

I~F

TANTALUM

FEEDBACK
H O + - - - - - o VOUT2 =+IOV

nil

+IOV

OUTPUT
r""'_-S VOLTAGE
ADJUST

SEE INFORMATION IN .
TYPICAL PERFORMANCE CURVES.
Higher !'IlDfutioa. !'Iduced range.

FIGURE 4: REFIOI Optional Output Voltage
FineAdjust. •

FIGURE 6. ±IOV Reference.

,4-40

VOUT I ; +5V

LOGIC

0
I

....> - - - - - - - - 0 VOUT 2; +IOV

VOUT
+IOV
·IOY

.....,-----0

+IOV
AUXILIARY
OUTPUT

FIGURE 7. +IOV and +5V Reference.

FIGURE 9. Digitally-Controlled Bipolar Precision
Reference.

+VCC ; 55V to BOV
.--------?O--o+VCC = ,I5V to 35V

. .----~----40VOUT5;+5OV

'----4~_;._oV'OUT = +IOY
lOUT = 0 to +IOOmA

VOUT4=+4OV

~~==::::;~===-OVOUT 3; +3OV

FIGURE 10. +IOV Reference with Boosted Output
Current to 100mA.

VOUT 2 = +2OY

).J.-~==:::::jt::===-OVOUT I = +IOV

REFIOI

}-----.....----.o VOUT = +IOY

FIGURE II. +IOV Reference with Input Voltage Boost
for 48V Operation.

FIGURE 8. Stacked References.

4-41

+Vcc =15V

Ladder resistor tolerances:

AtllOkno.02%
Alt 10ul%

4Mn

10111<0

OlaV
Ian
25kn
lOUT = 10V/R
where R= RI Ii'R2'

50u

t

·15V

lOUT

~

lOUT may be railed up to lamA
by using Bxlarnll resistors.

IOkn
5V

IOn
IOkn

IOkn
2V

2011

Ian

FIGURE 12. Positive Precision ImA Current Source.

20kn

10kn

~""'r-"N"-1o-(J

50u

1V

IOn
+15V

I

lOUT
4mAto

25tn
50n

,2OmA

+15V

SILICONIX

.RI
V
5ku
IN
Oto lOY A~~~T

VNBDAB

20kn IOkn
t-''Mr-''N'-"1>-O 0.1 V
50n
Ian

·15V

R2
416.7n

+Vcc =15V

25kn

50n

SPAN
ADJUST

IOn
IOkn

+IOY
20n

FIGURE 13. 4mA to 20mA Precision Current
Transmitter.

0.02V

Ian
IOku

50kn

IOkn

~'!Y'-"N"-1~

20n

NOTE: Tie all commons
to one point

IOkn

r-w...-'w..-+-o o.05V

.15V

IOkn
o.OIV

FIGURE 14. Precision Voltage Calibrator.

4-42

+Vcc =24V

+$V

OUT

~----~--------Q~
80011

800n

FIGURE 17. ±5V Reference.

4

.!>V

BOOn

IIOOn

+20V

At lo.oV. thl IIOOn bridge requlrel 18. 7mA. An 820n rellllllr conn.clld directly
lram tlte bridge to the poeRlvelupply provldel the bulk oIdi. brldgl curranl The
REFIOI ....d only lupply In errar currant to klep thl brldgl.t ID.OV. Sinn lIIe
REFIOI can sink or laurn up to IOmA. thl circuit lhown can totor.1I supply
varlltlons 01 up to 24V. ±8V. or brhlga reslltlnn drift lram 400n to l400n.

'FIGURE 15. +IOV Reference with Output Current
Boost Using a Resistor to Drive
a 600n Bridge.

>--+------0 +IDV

R

r----~,

+Vcc

v

_.!>AxRG

OUT -

2iiiiiR

"Taml Transducer Bridge Errors with Op·AmtI
Feedback Contral. EON. May 28. 1D82. Jlrald Graeme.

FIGURE 16. Linear Bridge Circuit Using Internal
Precision Resistors of the REFIOI as the
Bridge Completion Network.

FIGURE 19. Bipolar Input Voltage to Frequency
Converter.

4-43

+ISV

UAF11
UAF21

BURR-BROWN®

,IElIEII

UNIVERSAL ACTIVE FILTERS
FEATURES

APPLICATIONS

• SAVES DESIGN TIME
User·tuneable frequllncy, Q·factor, gain
Calculate only three resistance values
Design directly from this data sheet
Compl~tely chara,cterlzed parameters

• FilTER CONFIGURATIONS
Butterworth
Bessel
Chebyschev
• FilTER FUNCTIONS
low pass
High pass
Bandpass
Band reject

, • IMPROVED PERFORMANCE
Wida frequency ranges
UAFll • 0.001 Hz to 20kHz
UAF21 • 0.001 Hz to 200kHz
1% frequency accuracy
Qrange of 0.5 to 500
Reliable hybrid construction
NPO capacitors and thln~fII'm resistors

DESCRIPTION
The UAFll's and UAF21's are low cost universal
active filters. These versatile units can easily be
tailored to any active filter application, using the
extensive information provided in this data sheet.
UAF's are excellent choices for use in communications equipment, test equipment (engine analyzers.
aircraft and automotive test, medical test. etc.), servo
systems, process control equipment, sonar and many
others.
The UAFll's and UAF21's are complete two-pole
active filters with the addition of four external
resistors that provide the' user easy control of the

Q-factor. resonant frequency and gain. Any complex
, filter response can be obtained by cascading these
units. Three separate outputs provide low-pass. highpass. and bandpass transfer functions. A band-reject
(notch) transfer function may be realized simply by
summing the high-pass and low-pass outputs.
Since these UAF's are so vers,atile and flexible, they
can be stocked by the user, in quantity for use as
building blocks whenever the requirement ari~es.
This means instant availability and the UAF purchases may be made in volume to take advantage of
quantity price discounts. '

Input t
Input 2
Inpul3

oAdJust
International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. (602) 746-1111 . Twx: 911).852·1111 . Cable: BBRCORp· Telex: 66-6491

4-44

SPECIFICATIONS
ELECTRICAL
Typical at +25°C and with rated supply unless otherwise noted.
MODEL

MECHANICAL

UAF11

UAF21(1)

UNITS

±IOO
±IO
lOOk

±15·
±IO
lOOk

nA
V

0.001 to 20k
±I
±O.005
0.5 to 500

0.001 to 200k
±I

Hz
%
%/OC

0,5 to 500

--

±0.025
±O.I
0.1 to 50

±D.OI

%/"C

±D.025
0.1 to 50

%/"C

0.6

6.0

V/jJ,sec

20
10
2

20
20
20

V
V
V

±IO
2
200
10

±IO
10
200
10

IlV, rms
rnA

EPOXY PACKAGE
NOTE:

INPUT
Input Bias Current
Input Voltage Range
Input Resistance

leads in true position within

O.10~

O.2Smm A at MMC at seatrng plane

n

TRANSFER CHARACTERISTICS
Frequency Range I fo I
to Accuracy(2)
fa Stability(3) (over temp. range)
Q Rangel")
Q StabilitylS)
at fo Q ~104
at fo Q ';;105
Gain Range

±O.OO5

--

OUTPUT
Slew Rate

Pin numbers shown for
reference only
Numbers may not be
marked on package.

Peak-tc;>-Peak Output SWing(S)
fo';; 10kHz
fo';; 20kHz
fo~ 100kHz
OUlput Offset
I at low-pass output with unity gain I
Output Impedance

Noise(7)
Output CurrentcB)

rnV

II

POWER SUPPLIES
Rated Power Supplies
Power Supply Rangel O)
Supply Current at ±15V (Quiescent!

±15
±5 to±18
±12. max

±15

±5 to ±18
±12. max

V
V
rnA

TEMPERATURE RANGE
-25 to -1-85·
-40 to +85

Specification: Epoxy
Storage: Epoxy

-25 to +85
-40 to +85

NOTES
1. The UAF21 includes two internal O.002J..1F power supply capacitors.
2. Repeatibility of fo using 0.1% frequency determining resistors.
3. T.e.A. of external frequency determining resistors must be added to this figure.
4. Derated 50% from maximum - see Typical Performance Curves.
5. Q stability varies with both the value of Q and the resonant frequency fo.
6. low-pass output - see Typical Performance Curves.
7. Measured at the bandpass output with
= 50 over DC to 50kHz.
8. The current required to drive RF1 and RF2 (external) as well as C1 and C2 must come from
this current.
9. For supplies below ±10V, Q max will decrease slightly; filters will operate below ±5V.

a

PIN CONNECTIONS
Pin I.
Pin 2.
Pin 3.
Pin 4.
Pin 5.
Pin 6.
Pin 7.

High-Pass Output
Optional Pin
Bandpass Output
Q Adjust Point
Common
+Supply
low-Pass Output

Pin 8. Frequency Adjust
Pin·9. -Supply
Pin 10. Frequency Adjust
Pin 11. Optional Pin
Pin 12. Input I
Pin 13. Input 2
Pin 14. Input 3

4-45

Note 1: Pin
presence optronal

'C
'C

DIM
A

•

C
0
G
H

INCHES
MIN
MAX
.790
.490

MILLIMETERS
MIN
MAX

.810
.510

20.07
12.45

.190
.26.
.018
.021
.100SASIC

4.83

6.60
0.46
0.53
2.54 BASIC

.080
.115
.130
.300
.300 SASIC
.080

2.03
2.92
3.30
7.62
7.62 BASIC
2.03

20.57
'2.95

2.92

TYPICAL PERFORMANCE CURVES

"',

I

Q MAX, VS, RESONANT FREQUENCY'

FULL POWER RESPONSE
1000

100
80
6(j

'50

~

40

30

?-

25

g

15

~

10

100

~20

;;

.8

'"

~

~ ,
'f'

LOWwpass
~

Bandpass'

8
6

~

5
4

10

3

High-Pass

,

2,5

, 2

I"-

1,5

'"

~
2

3

4 5 6 78 10

15 20

30 40

60 80 100

1
100

lk

UAFll
10

20

30 40

60 80100

~

10k

lOOk

lOOk

1M

UAFll
200 300 400 600

1000

lk

10k
UAF21

UAF21 ,
Frequency I ~Hz I

Resonant Frequency. Hz

APPLICATIONS INFORMATION
T ABLE I. Useful References.

TRANSFER FUNCTION

1, Tobey. Gene. etal. Qp!!ratlonal Amplifiers: ~g!!..!!!!!.t"p~1i6ation ••
Chapter 8. McGraw-Hili Book Company. 1971,

The UAF21 uses the state variable techniql1e to produce a
basic second order transfer function. The equation
describing the three outputs available are:
T(Low-Pass) =
T(Bandpass) =

S1

+ (w"/Q) s + w,,~

s!

+ (w,,/Q) s + w}

2, Wong. Yu ,Jen. and William Ott: Function Circuits: Q!!igQ '!!l!!
.l!p~licatlons. Chapter 6. McGraw-Hili Book Company. 1976,

3. Daniels. Richard W.: ~pproximation Methods for Electronic

AHP(w,,/Q)s
AMP

T(High-Pass) =

4, Zyerev. Anatol I.: Handbook of Filter Synthesis. John Wiley and Sons.

1967.
5. Temes •. GaborC .• and Sanjit K. Mitra: Modern FillerTheoryand De.ig~.
John WiI~y and Sons. 1973.

s~

where w" = 271"f".

Burr-Brown also manufactures a line of completely selfcontained active filters called the ATF76 series. These are
available in most popular transfer functions with from
2- to B-pole responses. They contain aU necessary components and do not require any user design effort.

To obtain band reject characteristics the low, pass and
high-pass outputs are summed to form a pair of jw axis
zeros:
T(Band-Reject) -

,
s-

E!!l!!

Quigt!. McGraw-Hili Book C!>mpany. 1974.

DESIGN STEPS

+ (w,,/ Q) s + w,,-'

I. Choose the type of function (low-pass. bandpass. etc.).
type of response (Butterworth. Bessel. etc.). number of
poles. and cutoff frequency based on the particular
application.

where ALP = AHP = A.
The state variable approach uses two op amp integrators
and a summing amplifier to provide simultaneous lowpass. bandpass and high-pass responses. One UAF is
required for each two poles of low-pass or high-pass
filters and for each pole-pair of "and pass or band-reject
filters.
'

Ifth~ transfer function is band-reject see Band-Reject
Transfer Function before proceeding to step 2.
2. 'oetermine the normalizea low-pass filter parameters
(fn and Q) based on the type of response and number of
poles selected in step I. See Normalized Low-Pass
Parameters.
3. If the actual response desired is low-pass go to step 4.
For other responses a transformation of variables
must' be made (low-pass to bandpass or low-pass to
high-pass). See Low-Pass Transformation.

DESIGN PROCEDURE SUMMARY
These procedures give the design steps for the proper
application ofa UAF and for the selection of the external
components. More detailed information on filter theory
pertinent to some of the steps can be found in the
reference sources listed in Table I.

4-46

4. Determine the actual (denortnalized) cutofffrequency,
fn, by mUltiplying fo by the actual desired cutoff
frequency. See Denormalization of Parameters.
5. Pick the desired UAF configuration (noninverting,
inverting or bi-quad). See Configuration Selection
Guide and UAF Configurations and Design Equations.
6. Decide whether to use design equations" A" or "8".
See Design Equations "A" and "8". 7. Calculate R.., and RF1. See Natural Frequency and
UAF Configurations and Design Equations.
8. Determine Qp. See Qp Procedure.
9. Select the desired gain for each UAF and calculate the
corresponding R,; and RQ • See Gain (A) and UAF
Configurations and Design Equations.

T ABLE If. Low-Pass Filter Parameters.
Besae!
Numbe Butterworth
n(l)
of Pol
Q
Q
0'1
1.0 0.70711
1.2742
0.57735
2
3
4

1.0
1.0 1.0

--

1,00.54118

1.0 1.3065

--

1.0

5

6

8

BAND-REJECT TRANSFER FUNCTION
The band-reject is achieved by summing the high-pass
and low-pass UAI" outputs. Either of the configurations
in Figures 2 and 3 can be used to provide the band-reject
function if they are used as shown in Figure I.

1.23134

,,,

U

0.86372

-

Q

0.907227 1.1288

_.

1.32475
, .44993

0.69104

0.826456
1.068S53 1.7002

0.368911
Q.941326 2.551S

1.43241
1.60594

0.52193
0.80554

0.597002 0.70511
1.031270 2.9406

0.470711 0.9294
0.963678 4.59388

0.362320
0.690483 1.1778
1.017735 4.5450

0.216308
0.627017 1.77509
0.97579 7.23228

0.396229 0.68364
0.766121 1.8104
1.011446 6.5128

0.31611 a.S01.
0.730027 2.84426
0.982828 10.461e

1.0 0.61805

1.50470
1.55876

1-.0 1,61812

1,75812

1.0 0.51763
1.0 0.7.0711
1.0 1.93349

1.60653
1.69186
1.90782

--

7

.-

Chebysev
dB Ripple
0.5 dB Ripple
fnf21

0.56354
0.91652
0.51032

0.61120
1.0233

--

-

1.0
f.O 0.55497
1.0 0.80192
1.0 2.2472

1.68713
1.71911
1.82539
2.05279

0.53235
0.66083

1.0 .50980
1.0 .60134
1.0 0.89998
1.0 2.5629

1.78143
1.85314
1.95645
2.19237

0.50599 .0.296736
0.55961
0.598874
0.71085 0.861007
1.2257
1.005984

1,1263

-

0.256170
0.503863 1.0916
0.822729 2.5755
1.008022 8.8418
0.67658
1.6107
3.4657
11.5308

-

0.155410
0.460853 1.64642
0.797114 4."501
0.967228 14.2802
0.237699
0.571925
0.842486
0.990142

0.69236
2.5327
5.58354
18.e873

1. -3dB frequency.
2. Frequency atwhich amplitude response passe~throug~1 the ripple band,

TABLE Ill. Low-Pass Chebyschev Program.

The 15kn resistor is adjusted for maximum rejection.
The circuit in Figure 3 is applicable when using design
equations "A" (Au' = AHI,). When design equations "B"
are used (Au' = IOAHP). the resistor at pin 7 must be 10
times the resistor at pin I to obtaineq'ual pass-band gains
above and below fo.
In either case, the four external U AF resistors (Ro, R,!.
RFI and RF1) should be calculated for f., andQ of the
band-reject filter desired and for AI p to equal the desired
pass-band gain. An input constraint is that the input
voltage times A"pmust not exceed the rated peak-lo-peak
voltage of the bandpass output. or clipping will result.

PI=3.1415925536
COMPLEX r·'(101
READ 5, N, i1

5 FOf1MAT "2.1'8.6
A=SQRTI EXf', H/4.34.9443 '-1. I
B=1.IA

AN=-=ALOG (8+SQR·r, £:1 **2.1. II
."'N=AN/PLOATINI
J=MOD(N,
DO

10K~I.

2~+N/2

J

RP"SINH, AN 'SIN. FI';'LOAT, 2'K-l ,!cLOAT ,2-N.
X1P=COSH,AN ,'COS, PI'FLOATI2'K-11IFLOATI2'NII
WN=SQRTIRP"2+XIP"21
Q=-WNI12'RPI
PIK,=CMPLXiWN,QI'

10kn

IFIMODIN,2I.NE.0.AND K.EQ.JIGO TO 15

UAF with Four
Extsrnal Rsslstors

PRINT 20, PIK,

10k!!

GO TO 10

NOTE: Language variations betw:en
computers may require modification
of this program.

15 F=REALlPd()I

Input
Signal

PRINT 30. F
10 CONTINUE
20 FORMAT

2X'FN~ "E20.8"Q~"E20.8

30 FORMAT '2X"FN

~

"E20.8

STOP
END

FIGU RE I. Band-Reject Configuration.

Note that for bandpass and high-pass filters complex
conjugate pole pairs in the actual filter correspond to
single poles in the normalized low-pass model. Thus four
poles in Table II would correspond to four-pole pairs in a
bandpass or high-pass filter.
Filters with an odd number of poles show one fn with no
corresponding Q value. This represents a simple RC
network that is required for odd pole filters. This RC
network with a cutoff frequency equal to fn times the
overall filter cutoff frequc,ncy should be placed in series
with the first UAI" two-pole section. An external op amp
and RC network can be used for this purpose.

NORMALIZED LOW-pASS PARAMETERS
Usual active filter design procedure involves using normalized low-pass parameters. Table II is provided to assist in
this step for the more common filter responses. Table III
is a FORTRAN program which allows fo and Q to be
calculated for any desired ripple and number of poles for
the Chebyschev response. Program inputs are the number
of poles (N) .and the peak-to-peak ripple (R). Program
outputs are fo and Q, which are used exactly as the values
taken from Table II.

4-47

The cutoff frequellcy determined:\wthl: Tab:feU filter
parameters is(l)the-3dB frequency oftheButterWorth
resp.~nseand ofthe Bessel response and (2) tbe frequency
at~hichJhea:inplitude response of theChebyschev !liters
passes thrQugh the maximum ripple band (to enter the.
stop band).
.
LOW~PASS TRANSFORMATION
Low-P.SS 10 High-Pass
Thefollowing simple transformation may be used for
high-pass filters:
I
;:-:-:-.:..--Cn (high;pass) = fn (low-pass)
Q (high-pass) = Q (low-pass)
low-Pass to Bandpass
The IQw-pass to bandpass frl\nsformation to generate fn
(bandpass) and Q (bandpass) is much more complicated.
It is tedious to do by hand but can be accomplished wi~h
the FO RTR AN program given in Table IV. This program
automates the tranformation
s = p/2 ± J(p/2)2 - I.

COMPLEX P,S,U,
READ 5, FN, 0, OBP
5 FORMAT ,3F12.5,

UAF CONFIGURATIONS AND
DESIGN EQUATIONS
Noninverting Configuration
For applications requiring a bandpass gain of I V I V. the
internal resistor R:r-maybe used (input at pin 14) as the
gain resistor R,;: thus: only three external resistors are
needed to configure the filter.
To use equations "B" connect an II kH resistor between
pins 12 and I. Use equations "B" for frequencies above
8 kHz or when RQ from eq uations" A" becomes a negative
value.

Y=FWSORT,1.-1,.I,O'2.,,·'2,
X=-FN/O'2.'
P=CMPLX, X,y,
U=CONJG,P,
00301=1,2
S=P/,2'OBP,
P=S"2-1.
T=ATAN2'AIMAG,P',REAL'P,,
IF 'T.GE.O. ·GO TO 10
T=2.'3.14159+T

10 T=T/2.
A=SORTICABS, p, ,'COS, T,

SIMPLIFIED DESIGN EQUATIONIi "A"

B=SORT'CABS,P,"SIN,T,

1:.< 5kHz (l'AFI t) or 50kHl WAF211

S=S+CMPLX, A.B'

I.

FN=CABS,S,

= R1 : =

IO~ w" =- 1.59 x let f..

3. Ro = 10' (2Q, - A", I)

PRINT 20,FN,0

4. RCI = (2QI' ~

20 FORMAT '2X"FN="F12.5"0="F12.5.
IFI AIMAG, U I.EO.O.,GO TO 40

END

RI I

2. ARt' ::;: QAI J> ::;: OAIII'

0~FN/'2.'REAL'S, ,

40 STOP

DENORMALIZATION OF PAR~ME:rE~S
Table II shows filter parameters for many 2- to 8-pole
normalized \ow"pass filters. TheQ and the normalized
unqamped natural frequency, fn for each two-pole section
are shown. The Q values do not have to be denormalized
and may be used directly as desc.tibed in the Design.
Procedure Summary. fn must be denormalized by multiplying it by the desired cutoff frequency of the actual
overall filter to obtain'the required frequency. f., for the
design formulas. As an example. consider a 4-pole lowpass Bessel filter with a cutoff frequency of 1000Hz. The
first stage would be designed to an f"of 1432.41 Hz and a
Q of 0.52193 while the second stage would have an fo of
1605.94Hz andQofO.80554. To .combine the tWO stages
into the composite filter the low-pass output of the first
.stage (pin 9) would be connected to the input resistors
(R,i),ofthe second stage.
CONFIGURATION SELECTION GUIDE
It is possible to configure the UAF three different ways.
Each configuration produces features that mayor may
not \>e desirable for a specific application. The selection
guide in Table V is given.to assist in determining the most
advantageous configuration for a particular application.

TABLE IV. Low-Pass to Bandpass Transformation
Program.

30 P=U

wouk! result in.the pole ft0~itions for a.three:-polepair
bandpils~ fitter requiring three U~F stages.
..

Alt,• +I)

10' AliI'

SIMPLIFIED DESIGN EQUATIONS "B"
f,,> 5kHz. (UAFI i) or SOkH,(UAF21)

NOTE: Language variations between
computers may require modification
of this program.

I.RH=RI:=3.16xlO" w,,=5.03xI01 f"
2. AliI'::;: Q 3.16·Al.p = 3.16Q Alii>

3. Ro = 10' (3.48Q, - A" - I)

Program Inputs

4. Rti = (3.48QI', • AliI' +·1) IO~

I. fn - From Table II for the low-pass filter of interest
2. Q - From Table II
3. QBP ~ Desired Q of the bandpass filter

A,,,•.

Inverting CQnfiguration
SIMPLIFIED DESIGN EQUATIONS "A"

F or filters with an odd number of poles a Q of 0.5 should
be used where Q is not given in Table I I. Enter 10~ for Q
when transforming zeros on the Imaginary axis. .

2.A HP =QAu.=Q Alii'

The program transforms each low-pass pole into a
bandpass pole pair. Thus a three-pole low-pass input.

4. RfJ ::;: 2 x IO~ (2QI' + AliI' ~ I)

f,,< 5kHz (UAFII) or 50kHz (UAF21)
I. R",

= R", = 10' w,,= 1.59 x 10' r..

3. Rq ::;: IO~ Qp AliI'

4-48

NONINVERTING INPUT

INVERTING INPUT

BI-OUAD

Oulputs Available

BP, LPand HP

BP, LPand HP

BPand LP

Inverted Outputs

BP

HPand LP

SPand LP
No

o & Gain Independent of
Frequency Resistors?

Yes

Yes

Type of 0 Variation
With Changes in RF

Constant 0

Constant 0

Other Advantages

May be used with only three external

Parameter limitations

20. - ABP > 1 {f. < 8kHz}
3.480. - ABP > 1 '{ fO> 8kHz I

Constant bandwidth
RG and Ra are small at
high frequencies

resistors I use internal R3 as RG I
20.+ABP>1 {f.<8kHzl
3,480. + ABP > 1 {fO> 8kHz I

None

Summary: The BI-Ouad filter is particularly usefulasa bandpass filter ilthefilter bandwidth must be kept constant asthecenterfrequency is varied, "
Q must be kept constant (l.e .. constant of a bandpass or maintaining constant response of a to~pass or high-pass I one 01 the other two
configurations should be used, The Bi-Ouad also has the advantage that RG and Ra are smaller than RG and Ro of the other two
configurations {this is especially useful at high frequencies I. The non Inverting input configuration has the advantage that for ABP = 1, RG =
l00kO; therefore As iinternall may be ~.ed so that only three external resistors are needed {RF1. RF2, Ral.

a

II
I .L.

r-----------------~--------------~~

n
12

RS" 12
Inpul Signal

Input
Signal RS "13
Me l00kn

14

Ie
FIGURE 2. Noninvertin'g Configuration.

FIGURE 3. Inverting Configuration.

SIMPLIFIED DESIGN EQUATIONS "B"
r.. > 5kHdUAFIli or 50kHz (UAF211
I. Rn = Rr~ = 3.16 x lO"

(U"

= 5.03

X

107

r..

2. ABP=Op/3.16=3.160p AHP

3. Rc. ,= 3.16 x 10" Q .. AnI'

= 2 X Io"~ (3.48Q.. + AMI'· I)
BI-QUAD Configuration
SIMPLIFIED DESIGN EQUATIONS "A"
f.. < jkHI (l'AFIIi or 50kH, (l'AF211
I, Rr = RI : = 10"
= 1.59 x IO~ f..

.4. RI)

!

FIGURE 4. Bi-Quad Configuration.

(u"

2.QArl'=AHI'

.l

R~)

= Q,.R, f

SIMPLIFIED DESIGN EQUATIONS "B"
"> ~J..H/I\':\I--II) nr 50kHI (L\J-:!II

I. R,., ~ RI"~ = 3.16

X

lOll cu.. = 5.03 x 10"

r..

2. Q A'I"= AMI"

.1. Rv = 3.16 Q" R,

I

4. Re,. = RQ ARI'

Design Equations "A" and "B"
I. Farf" below 8kHz. either ofequations"A"or"B" may
be used.
2. For f" above 8kHz. equations "B" must be used.'1f
equations "A" were used above 8kHz. the filter could
become unstable.
3. Equations" A" are for the UAF as it is supplied. When
using equations "B". a II kO resistor must be placed in
parallel with R~ (between pins' 12 and I).

4. The values of RFI and RI'~ calculated with equations
"B" are approximately one-third of those calculated
with equations "A". Thus there may be an advantage
in using equations "B" at low frequencies. Using
equations "B" would require use of one more resistor.
but that would not alter or affect filter performance in
any manner..
. 5. Using the negative gain values for Al.p or AHP or Asp
could result in the negative values for resistors Ro and
RQ • So the absolute value of the gain should always be
used in the equatiolls.
6. Under some circumstances the value of RQ using
equations "A" will be negative. If this occurs. use
design equations "B".

4-49

Natural Frequency (10)
I. fo for each one pole-pair bandpass filter is the center
frequency (fc). fc is defined as fc= -.,IfJ; where fl is the
lower -3dB point and f2 is the upper -3dB point of the
pole-pair response.

.2. ,:1:0" obtain..f", below ,I 00 Hz, using "practical resistor . , .
". yalues, capacitors may be parahele~i Wi,h:CI' and C2 JO
reduce thesize of RFI and Rn.If capacitors are added
inpai-allel. "
"
"
. "F"
'
,
.
,lOoop .
RFI (new) = RF1 (new) = RFI (old) -'--"--, ,
"
"C: + IQOOpF
where RF (new) 'is the 'new lower value frequency
r,esistor, C is the'value oUhe two external capacitors
placed across CI and C2 (between pins 10 and 3 and
pins8and 7 and RFI (old) is the vaIiiecaIcuiated inthe "
~ilnpilfied design e(juations.'
,

".A~p ~ for,.high,pass output·,,,gainachigh frequepcies .
,2. Refer ld.the'Typiea) Per-formanceCurves for fuji
power resporise. WheiLs~lel;ting thegl;1In.insu(e the
limit~ ,of the curve ar¢'n!-'>t l;xceeqeq for the.,desired
voltage range.
'
DETAIL.ED TRANSFERFUHCtIONEQUAfION$
The foJlowing .eqillitions show !/ie action, of all the
irHernalanil external UAF filter components. They are
notrequlred for the -regular design procedure but could
be usedifa detailed.analysis is required.
,NONINYERTING INPUT CONfiGURATION
I. Im/,r'~ {R) 'Rli CL ·R,,~C.:i)

Q-Factor
("
,J.:For bandpass filters Q,,:, 3dB bandwidth
.2. WhelL ,designing low-pass JiIters",oL more ,than two
poles. best results, \ViII be obtai l1 ed if the two pole
sections with lower Q art: followed by the sections with
higherQ; This will eliminate,anypossibilityofclipping
due to high gai~ ripple in high Qsections.
1 '

Z:" Q=,'

2~r'"'"

"

,
,

1-.

'9
8
7

7

6

6
5

8

5
.:iI4

,)~y

4

3

3

2

2

105

10'

.l.

.,

'"s.,"':R r = I

;
10'

.~.

+ I R:+ I RIJ

-=..

AliI';::; Rq R"

Offset Error Adjustment
DC offset errors will be minimized by grounding pin 5
throug/:! a resistor equal to I;' 2 the value of RFI or RF2 .
The DC offset adjustment shown nere may' pe used if
required.
Offset errors will increase with increases in Re,

lOOk!)

~P _IY-TO-P-In-8-f~o~" aS-S-du-tP-u-t- ~

f·4S... .

••

To pin 10 for low-pass or high-pass output.

-- t-t-

.Supply

'"

2

3

4, 5 6 7 ,89105

' 2

3

2

3

4

e 7, Ii 9106

2

3

WAF21

Rl

Q At t' hu.. RI ·C!)

..ttl'!.

/. ~

5

Rc.

2.Q= R()('~w"

"May be adjusted' for best sensitivity,

Design Example
It is desired to design a 5-pole Bessel, Low-Pass Filter
with f" '" 3.3kHz and ALP = I. We will use the UAFII to
implement this filter.
From Table II, the foHowing :values of fn ,and
obtained.

WAF11

105

.

~

BI-QUAD CONFIGURATION

V

'v~~q;'

(f{ ,R I .(",

QAll':: () RJ AF,U'" .R,",= ~HPJRIRI:!.CJ, (~2RI:':C::d.

I":

<,

RI)

R1R 1 , ( ·

4. AIIP=JR1R:R1.:C: (R11c;.'1) Q'R"

,

, J,;'

"

I. w,,~·= R~ (R I Rile l R/"~C~)
2, Q=, R, (I + 2 x i(i R"~rnR--;,,C"",7n(Jl.-;;,RD,R--;"C~'1

"

.

10'11:,,1,' R,"R",C,.'

INVERTING INPUT CONFIGURATION

!

,105
9
8

106

'.~

Rt+'R:'

5. A ul' ='.10' 12 + 10'

,
I·. If the "I'" times Q" product is greater th,an 10" (or 10'
for the UAF21). it is possiblefor the measured filter Q
to be diffe'rent from the calculated value of Q. This
effect is 'the ' result of nbriideal characteristics of
operational amplifiers. It can'be 'compensated for by
introducing thel'arameter Qp into theclesigne'quatioris.
2. Calculate the f" Q product for the,filter~ Ifthe.product
is lIbove 10'Hz(or 10' for the UAF21). lotah:' the
corresponding f"Qp product 011, the'c~rve in Figure 5.
Divide'f"Qp by f" to obtain Qp: Use Qpas indicated in
the design equaiions. For, LQ products below 10'Hz
(or 1,O'for the UAF21). Qi'= Q.. .
2

(I

Rio

I,

Qp Procedure

~.

+(_,R,')'( ,Rf"l," +

= 10',+ 10' R,) (IO~' + Ri;;' .
4. Q AI ;:"=: 5kHz. equations "8" would again be used. and
an II kO resistor would be connected between pins 12 and
I of the second UAF stage.

Using the above shown values of fn and Q. we now will
proceed to design the three stages of filter separately.
Anyone of the three configurations can be used. We will
select inverting configuration.
'.

7
X 10
- R1 "-- 5.03
R 1'15802

For Stage I.
fn - 3.3kHz x fn = 3.3kHz x 1.55876 = 5144Hz

t:.Q= 5802 x 0.91652 = 5.32 x 10"

Since fu >5kHz. equation~ "8" would be used. thus an
II kO resistor must be connected between pins 12 andl.
5.03 x 107 '
Rn = RI" = 5144
= 9778B

fnQ<10 4 •
A

fnQ<10 4 • :.Qp = Q = 0.56354.

3.J6 X 104 x 0.56354 = 99 85kB
0.17834
.

2 x 10'<
RQ = 3.48Qp + ARP-I
. 175.52kn

= 0.91652

= 2!.. A = 0.91652 x 1=0.29004
RP 3.16 LP
3.16

For Stage 3.
f = 3.3kHz x fn = 3.3kHz x 1.50470 = 4966Hz

2 x 10'<
3.48 x 0.56354 + 0.17834 -I

For the simple pole.
I
I
,
10-'
RC = 21Tf = 21T x 4966 _'.2049 x
3300pF (or any convenient value)

For Stage 2.

L = 3.3kHz x fn = 3.3kHz x 1.75812 = 5802Hz

R = 3.2049 x 10:'= 9.71 k!l
3300 x 10- 1-

977811

Input

Qp = Q

2 x 10'<
2 x 10'
RQ = (3.48 Qp + A RP-I) - (3.48 x 0.91652 + 0.29004 -I) '"
80.66k!l

ARP = Qp ALP = 0.56354 x I == 0.17834
3.16
3.16
AuI'

:.

R,; = 3.16 x 10' Qp= 3.16 X 104 xO.91652 = 99.86kH
AD.
0.29004

f.,Q = 5i44 x 0.56354 = 2.9 x 10"

R,,=J.16x 10"QI'

8669!1

977811

RG

LP 7r----.....,

99.85kn

·15V +15V
866911

866911

9.71kll
Out

FIGURE 6. Overall Circllit.

4-51

UAF31

BURR-BROWN@"

IElElI

UNIVERSAL ACTIVE FILTER
High Pass

Band I'ass

(}u,put

Output

2

II

('1 1000 pF

tuw IJ ass

(~U~pUI,

."

C21000pt'

Input I

130-----<1'-#
Input 2

Ilo----.-\

Input J

I.

FEATURES
• LOW COST
• SAVES QESIGN TIME
,Calculate only three resistance values'
Dnlgndlrectly from this data sheet. ,'
Completely characterized parameters
• IMPRBVED PERFORMANCE
1% frequency accuracy·
UncommlHed op amp included
Q range of 0.5 to 50D
Reliable hybrid construction
NPO capacitors and thln·fllm resistors

InI8mlllollll Airport IndUllrlal Patt • P.O. Box 11400, TumiA. Arlzenl 85734 • T81. (6021 746-1111 • Twx: 911).952·1111 • Cable: 88RCORP - T118II: fll!-6491

4-52

DESCRIPTION
to take advantage of quantity price discounts.
Three separate outputs provide low pass, high pass, and
band pass transfer functions. A band reject (potch) transfer
function may be realized simply by summing the high pass
and low pass outputs, The UAF31 also includes an uncommitted op amp that may be used as an input or output
buffer or to add an additional one-pole response to the
filter.

The UAF31 is a versatile 2-pole active filter which, with the
addition of three or four external resistors, provides the
user easy control of the Q-factor, resonant frequency and
gain. Any complex filter response can be obtained by
cascading units. The UAF31 is an ideal building block that
can be purchased and stocked in quantity to be used whenever the requirement for a filter arises. In this way filters
are, available immediately and may be purchased in volume

TRANSFER FUNCTION
To obtain band reject characteristics the low pass and high C;;
pass outputs are summed to form a pair of jw axis zeros:.
~

The UAF31 uses the state variable technique to produce a
basic second order ·transfer function. The equations describing the three outputs available are:
T(Low Pass)

A(s2+wo2)
T(Band Reject) = 2
--2- where ALP=AHP=A,
s +(wo/Q) s + Wo

ALpw02
s2 + (wo/Q) s + w0 2

The state variable approach uses two op amp integrators
(#2 and #3 in the simplified schematic below) and a summing amplifier (#1) to provide simultaneous low pass, band
pass and high pass responses. One UAF31 is required for
each two poles of low pass or high pass filters and for each
pole-pair of band pass or .band reject filters.

ABp(wo/Q)s
T(Band Pass) = --:--------:;:
s2 + (wo/Q) s + w0 2
T(High Pass) =

AHps2
s2 + (wo/Q) s + wo2

High Pass

Band Pass

Low Pass

Output

Output
2

Output

II

6

RI lOOk

CI 1000 pF

C2 1000 pF

Input 3
14

L-_ _ _ _ _ _ _ _~------------_<)J

FIGURE 1. UAF31 Schematic.

4-53

::::»

SPECIFICATIO••
ELECTRICAL
Ty:pical at 2 SOC.

MECHANICAL

~d with rated supply ,~nless othe~ise n'oted.

MODEL

,

UAFJ1·

INPUT

nf

Input Bias Current
;Input Volt.age Range
In put Resistance

±40nA

±IO V
100 kn"

TRANSFER CHARACTERISTICS
Frequency Range (fo)
f~ Accuracy(t), max
fo Stability(2) ..
Q Range(3)
Q Stahility(4)
@fQQ ';;;10 4
@fo Q';;;10 5
Q Repeatability
Gain RanEe

dot over
pin 1 -

±0.002%/oC

0.5-500

Output Current(7)

h

12.7mm
(0.50")
........



E

.

300

~ 20

.e

.

400

X

~100._
50

o

Band Pass

6
5
4

80
60

40

3
2.5
2
1.5

30
25~-r-+-r+444+H~HH--~-r~r+++HK4H~

High Pass

:1

1
1

2

3

'I

4 567810

20~-r-+-r+444+H~HH--~-r~~++HK4H~

"'!...

~

1520

15~-r-+-r+444+H~HH--~-r~~~HK4H~

3040

10~1--~~2~~3~4~5~6~7~8~10~~~2~0~3~0·4~0~~60~8~0~1~00

6080100

Frequency (kHz)

Resonant Frequency (kHz)

FIGURE 2. Full Power Response

FIGURE 3. Q Max. vs. Resonant Frequency

,ACTIVE FILTER DESIGN PROCEDURE 4. CalculateQpasshow~intheQfa~tordesignnotesto
compensate for amplifier phase shift errors.
5. Determine the filter configuration that will be used
(see configuration selection guide on the opposite
page for recommendations).
6. Calculate the resistance values required using the design equations for the filter configuration selected.

To design filters using the circuits shown on the following
pages, these six design steps should be followed:
I. Determine fo , the natural frequency of the pole pair.
2. Determine A, the gain of the filter section (V/v).
3. Determine the Q factor.

NATURAL FREQUENCY (fo) DESIGN NOTES
fo values for many low pass and high pass filters are
given in the filter parameter table on page 5-107.

The equivalent resistance if inserted between pins I and
11 or pins 2 and 8 is

fo for each one pole-pair band pass filter is the center
frequency (fc). fc is defined as fc = v'fli2 when f 1
is the lower 3 dB point and f2 is the upper 3 dB point
of the filter.

R = Ra Rb + Ra + Rb
Rc
Capacitors may also be paralleled with C I and C2 to
reduce the size ofRFI and RF2' If capacitors are added
in parallel,

To use the UAF31 with fo above 8 kHz, an II kfl
resistor must be placed in parallel with R2 (between
pins 13 and 11). For the higher frequencies where
an 11 kfl resistor is required, use simplified design
equations "B". For operation below these frequencies;
use simplified design equations "A" or "B".

1000pF
RFl(new)=RF2(new) =RFl(old) C+ lOOOpF
where RF(new) are the new lower value frequency resistors,
C is the value of the two external capacitors placed across
Cl and C2 (between pins 1 and 2 and pins 8 and 9), RFI
(old) is the value calculated in the simplified design equations.

To obtain fo below 100 Hz using practical resistor
values, T-networks may be used for the frequency
determining resistors (RF 1and RF2)'

GAIN (A) DESIGN NOTES
The gain (VIV) of the filter section is:
ALP - for low pass output - gain at DC.
ABP - for band pass output - gain  I (fo < 8·kHz)
3.48 Q p - ABP > I(fo > 8 kHz)

Summary:

RG and RQ are small
at high frequencies

2 Qp + ABP'> 1 (fo < 8 kHz)
3.48 Qp + ABP'> 1 (fo > 8 kHz),

,NONE

The Bi-Quad filter .i.s particularly useful as a bandpass filter if the filter bandwidth must be kept con~tant as the center frequency
is varie~.. If Q must· be kept constant (i.e., constan~ .Q of a band pass or m~intaining .a. c«?ll,stant response of ':llowpass or ~ighpasS)
one·ofthe other two configurations should be used. ·The Bi-Quad also has the advantage that RG and RQ ·are smaUer than RG
and RQ of the. ot~.er ~ configurations (this.is espeCially useful.at high frequencies). The noninverting input configu.ation has
the advantage that for ABP = 1, RG = 100 k therefore R3 (internal) may be used so that only three ex.ternal resistors are needed
(RF!. RF7' RQ).
.
.
'
"

4-56

NONINVERTING INPUT CONFIGURATION
For applications requirin3 a band pass gain
of I (V/V). the internal resistor R3 may be
used (input at pin 14) as the gain resistor
RGo Thus only three external resistors are
needed to configure the filter.

• To use equations "B;' connect an 11 k resistor between pins 11 and 13. Equations
"B". are also valid for frequencies below 8 kHz.

SIMPLIFIED DESIGN EQUATIONS "A"
<8

fo

109
1. RFJ ;;; RF2 =~

11

kHz

100 k RI

1.592 x J0 8

=- - - ' 0 - -

2. A DP ::; Q ALP == Q AHP
10 5 Q
3.RG =A Sp Qp
4. RQ=

10'
AOpQp
2Q> - - . , - - - I

SIMPLIFIED DESIGN EQUATIONS "B"
fo; QP/Q - I

Resistors

INVERTING INPUT
CONFIGURATION
SIMPLIFIED DESIGN EQUATIONS "A"
2. A BP = Qp ALP
J. R

11

< 8.kHz

fa

,
109
I. Rfo'l = RF2 =~

=-

1.592 x 10 8
---'-0---

9

=Op AHP

L.P.

_ IDS Op

G-ASP
10'

. 4. RQ

=2Qp + ASp _ I

SIMPLIFIED DESIGN EQUATIONS "B"
f o >8kHz

I. Rio" = R F2 ::;
2. ASp=

ViOl( 108

-;;;;- =

5.033 x 10'
--'0--

~6 ALP= 3.16 Qp AHP

* External

=3,16.104 Qp

3. R
G

Resistors

ADP

"',,:OS~_-:-_ _

4.
RQ

3.48 Qp + ADP _ 1

BI-QUAD
CONFIGURATION
SIMPLIFIED DESIGN EQUATIONS "A"
f o <8kHz

I. Rn = RF2

=~ =

1.592 x tOR

Input
Signal

fo

Wo

2. AUp= Q ALP

8

J. RQ=Qp RFI
4.

RG=~

A DP

SIMPLIFIED DEsiGN EQUATIONS "B"
f o >8kHz

t. RFt = R F2 :::: Vilrx 10 8
Wo

3

=

5.033 x 10'

fo

~------------~---~

2. ADP = 3.16 Q AU;
3. RQ = 3.16 Qp R FJ

* External

4. RG=!lL
AU>

4-57

Resistors

The baiIdreject confJgUratiort is achieved by summing'the
high pass,and low pass UAF outputs. The circuits shown
in Figures 5 and 6 can be used to provide the band. reject
function if they are connected as'shown in Figure 8. The
Figure 8 circuit is applicajJle when using simplified design
equations "A" (ALP = AHP), but when operating with an
1'1 kn resistor between pins 13 and 11 (ALP =10 AHP),
the resistor ~t pin 9 must be 10 times the resistor at pin 11
to obtain equal passband gains above and below fo . '

passband gain. An input constraint: the input voltage times
ABpmust not exceed the rated peak-to-peak output voltage
of the band pass output, or clipping and distortiun will result.

In .either case, the four ext~rnal UAF resistors (RG, RO,
RF I and RF2) Should be calculated for fo' and Q of the
band reject filter desired and for ALP to equal the desired

Uncommitted Amp

HP
10 kf!

11
UAF with
rL~P~::>.:.9-1 External
Band Reject 0 utput

5

10kf!

FIGURE 8. Band Reject Output

FILTER PARAMETERS
LOW PASS AND HIGH PASS
Table I shows filter parameters for many 2 to 8 pole low
pass filters. The Q and the normalized undamped natural
frequency, fn, for each two-pole section are shown. The Q
values should be used with Figure 4 and in the design
formulas Of! page 5-106 and fn must be multiplied by the
desired cutofffrequency ofthe overall filter to obtain the
required frequency, f., for the design formulas. As an
example, consider a 4-pole low pass Bessel filter with Ii
cutoff frequency of 1000Hz. The first stage would be
designed to an f. of 1432.41 Hz and aQ of 0.52193 while
the second stage would have an f. of 1605.94Hz and a Q
of 0.80554. The low pass output of the first stage (pin 9)
should be conne,cted to the input resistor (Ro) of the
second stage.
Filters with an odd number of poles show one fn with no
corresponding Q value. This represents the simple RC network that is required for odd pole filters. This RC network
with a cutoff frequency equal to fn times the .overall filter
cutoff frequency should be placed in series with the first

UAF two-pole section. The uncommitted internal op amp
should be used as a buffer to isolate the RC network so that
the UAF input resistor will not affect the cutoff frequency
of the RC network.
The cutoff frequency determined by the Table I ,filter parametersis(l) the 3 dB frequency of the Butterworth response
and of the Bessel response and (2) the. frequency at which
the amplitude response of the Chebyschev filters passes
through the maximum ripple band and enters the stop band.
To obtain high pass pole positions, the low pass to high pass
, transformation may be used: fn (high pass) = f""n""('"'IJL.
w- p-a-ss"')
Q (high pass) = Q (low pass)

The lOW pass to band pass transformation is much more complicated, but it can be done using the low pass to band pass
conversion program (Table III).

CHEBXSCHEV
NUMBER
OF POLES

BUTTERWORTH
Q

fn

BESSEL
fn

Q

0.5 dB RIPPLE
fn

Q

2 dB RIPPLE
fn

Q

2

1.0

0.7071'1

1.2742

0,57735

1.23134

0.B6372

0.907227

1.12B6

3

1.0
1.0

----------

1.32475
1,44993

-----.-----

1.0

0,69104

0.626456
1.068B53

------------1.7062

0.368911
0.941326

2.5516

4

1.0
1.0

0.54118
1.3065

1.43241
1.60594

0.52193
0.80554'

0.597002
1.031270

0.70511
2,9406

0.470711
0.963678

0.9294
4.59388

1.0
1.0
1.0

------------

0.56354
0.91652

0.362320
0.690483
1.017735

--."---------

0.61805
1.61812

1,50470
1.55876
1.75812

--.--.".----.

5

1.1778
4.5450

C,218308
0.627017
0.97579

1.77509
7.23228

6

1.0
1.0
1.0

0.51763
0.70711
1.93349

1.60653
1.69186
1.90782

0.51032
0.61120
1.0233

0.396229
0.7611121
1.011446

0.68364
1.8104
6.5128

0,31611
0.730027
0.982828

0.9016
2.84426
10.41;16

1.0
1.0
1.0
1.0

"------------

1.68713
1.71911
1,82539
2.05279

0.53235
0.66083
1.1263

0.256170
0.503863
0.822729
1.008022

-------.-----

0.55497
0.80192
2.2472

-----------

7

1.0916
2.5755
8.8418

0.155410
0.460853
0.797114
0.987226

1.64642
4.11507
14.2802

8

1.0
1.0
1.0
1,0

0.50980
0.60134
0.89998
2.5629

;.78143
1,83514
1.95645
. 2.19237

0.50599
0.55961
0.71085
1.2257

0.296736
0.598874
0.061007
1.005984

0.67657
1.6107
3.4657
11 ,5305

0.237699
0.571925
0.842486
0.990142

0.89236
2.5327
5.58354
18.6873

TABLE 1. Low Pass Filter Parameters

4-58

------.---

--------.-

-----------

COMPLEX P,S,U
READ 5, FN, Q, QBP
FORMAT (3FI2.5)
Y=FN°SQRT(I.-(I./(Qo2.W02)
X=-FN/(Qo2.)
P=CMPLX(X,Y)
U=CONJG(P)
DO 30 1=1,2
S=P/(2.oQBP)
P=soo2-1.
T=ATAN2(AIMAG(P),REAL(P»
IF(T.GE.O.) GO TO 10

LOW PASS CHEBYSCHEV
Table II details a FORTRAN program to determine fn
and Q for a Chebyschev low pass filter. The only inputs
required are the number of poles and the peak to peak
ripple (dB) of the desired filter. The 'program output. are
treated exactly as the values on the pole positioJ:l table
(Table I).
'

BAND PASS
Table III details a FORTRAN program that may be used
to transform low pass pole positions into the equivalent
band pass pole positions.

TABLE 111. Low Pass to Band Pass Transformation Program

Program Inputs:
1. ~n-From Table I for the low pass filter of interest.
2.

Q From Table I.

3.

QBP-Desired Q of the band pass filter.

T=2.o3.14159+T
10 T=T/2.
A=SQRT(CABS(P))*COS(T)
B=SQRT(CABS(P»*SIN(T)
S=S+CMPl.X(A,B)
FN=CABS(S)
Q=-FN/(2.oREAL(S»
PRINT 20,FN,Q
20 FORMAT (2X"FN = "FI2.S" Q = "FI2.S)
IF(AIMAG(U).EQ.O.) GO TO 40
30 P=U
40 STOP
END

For filters with an odd number of poles a Q of .S should
be used where Q is not given in Table I. The program
transforms each low pass pole into a band pass pole ·pair.
That is. using the two~pole low pass pole positions would
result in the pole positions for a two pole pair. band pass
filter, requiring two UAF stages. Enter 10 6 for Q when
transforming zeros on the imaginary axis. This program
alitomates the transformation s = p/2 ± (p/2)LI.

DETAILED TRANSFER FONCTlDN EQUATIONS
The following equations show the action of all the internal and external
UAF31 filter components. They should be used if a detailed analysis,
not covered in the simplified equations, is required.
, NONINVERTING 'NPUT CON~IUURATION
I. Wo 2

= Rl

AFt ::2 Cl C2

1 + Jt4 (RG + RQ)

---.ra~(R2 RFI CI) l\
I+R
1G"~

2. Q.

f,

R2

RG(

Je; +k+.J;)
J

, .... - "2
.

A

'-iii

6. Aap'"

::! ~~)~

+!L

1

4. ALP '"

PI=3.1415926536
COMPLEX P(IO)
READ 5,N,R
5 FORMAT(12,FS.6)
A=SQR'f(EXP(R/4.3429448)-I.)
B=I./A
AN=ALOG(B+SQRT(BO °2+ I.»
AN=AN/FLOAT(N)
J=MOD(N,2)+N/2
DO 10 K=I,J
RP=SINH(AN)OSIN(PIOFLOAT(2°K-I)/FLOAT(2°N»
XIP=COSH(AN)OCOS(PIOFLOAT(2°K-I)/FLOAT(2°N»
WN=SQRT(RPo'2+XIP**2)
Q=-WN/(2. o RP)
P(K)=CMPLX(WN,Q)
"IF(MOD(N,2).NE.O .AND.K.EQ.J) GO TO 15
PRINT 20,P(K)
GO TO 10
15 F= REAL(P(K»
PRINT 30,F
,10 CONTINUE
20 FORMAT(2X"FN="E20.S" Q = "E20.S)
30 FORMAT(2X"FN="E20.8)
STOP
END

(~) .. Asp E:~

3. Q ALP'" Q AHP

-

+ R2
'Rj'

L'-RG(~+to+~)

~

'NVERnNa 'NPUT CONFlaURATlON
I. Wg2 '" RJ iF! ::2 Cl C2
2. Q" (I +

Rot)(

ltQ

3. Q ALP = Q AMp
4. ALP =
S.

~

,I

+

~+

(~) '"

) (

RFJ CI
RF2

Jo R.J
E:! ::! ~!)li
RI

Y,

c,)

Aap

~

AHP"'~ALP"'~

6. ABP '" (t + ~Q)

.

I

RGfJG+J;+~)

II·DUAD CONFI8URATION
I.

Wo 2 .. RI

2. Q =

Rq

3. ADP '"

OFFSET ERROR ADJUSTMENT

RFI~~ RnC2

C 2 ....

wJaA~P':.2 = ~
+ Supply

DC offset errors will be minimized by grounding pill 3
through a resistor equal to 1/2 the value of RPI or RP2.
100 k

The DC offset adjustment shown here may be used if
requited.
Offset errors will increase with increases in Rp.

Supply

4-59

to pin 8 for bane pass output
to pin 1 for low pass or high pass
output.
-May be adjusted for best sensitivity.

BURtil-BROWN~

'UAF4t

IElEI,1

UNIVERSAL ACTIVE FILTER
FEATURES

BENEFITS

• LOW COST
• SMALL SIZE
Single wide DIP package
• FULLY CHARACTERIZED PARAMETERS
• HYBRID CONSTRUCTION
• IMPROVED PERFORMANCE
1% frequency accuracy
Q range of 0.5 to 500
.NPO capacitors and thin·fiIm resistors
Uncommitted op amp includ!ld

• SAVES PRINTED CIRCUIT BOARD SPACE
• SAVES DESIGN TIME
Calculate only four resistance values
, Design directly from Ihis dala sheel
Versalile building block for filter design
• HIGH RELIABILITY
• HIGH STABILITY

High-Pin

Blndp..1

LoW,PIII

Ouqwt

Output

Output

Input 3

International Airport IndUltrlal Park· P.O. Box 1I41io· Tucson. Arizona 85734· Tal. (6112) 746·1111· Twx: 910-952·1111 . Cabla: BBRCORp· ~elex: 66-6491

'4-60

DESCRIPTION
The UAF41 is a versatile two-pole active filter. It uses a
three operational amplifier double integrator feedback
loop to generate a complex pole pair (two conjugate
poles). The location of the poles in the complex plane
(and thus the natural frequency and Q) are determined by
external, user supplied resistors. Either three or four
resistors are used depending on the particular
configuration chosen.
The UAF41 produces three transfer functions
simultaneously - low-pass, high-pass, and bandpass which are available at three separate outputs. The fourth
basic transfer function - the band-reject or notch - can be
obtained simply by summing the high-pass and low-pass
outputs using the uncommitted amplifier (A4) contained
in the UAF41. The uncommitted op amp can also be used
to add a single-pole response for complex filters requiring
an odd number of poles.

More complex higher-order filters can readily be
obtained by cascading UAF's. This is easily done with the
UAF41 since the high input impedance and low output
impedance associated with the operational amplifiers
used prevents the series connected stages from interacting
(e.g., no frequency pull due to following stage loading).
This data sheet contains the design procedures for an easy
selection of resistor values for the stagger tuning of
cascaded stages.
The versatility of the UAF41 makes it a general purpose
building block for a wide variety of active filter
applications. Its universal nature, ease of use, small size,
and low cost allows the user the convenience of keeping
units on hand for immediate use whenever a filter
req uirement arises.

TRANSFER FUNCTION
The U AF41 uses the state variable technique to produce a
basic second order transfer function. The equations
describing the three outputs available are:
T(Low-Pass) =

T(8andpass) =

T(High-Pass) =

s'

+ (wo/Q) s + wo'

s'

+ (wo/Q) s + wo2

s'

+ (w,,/Q) s + w o'

high-pass outputs are summed to form a pair of jw axis
zeros:
A (s' + wo')
T(8and-Reject) = ,
,
s· + (wo/Q) s + wo'
where ALP

ADP (w o / Q)s

The state variable approach uses two op amp integrators
(A2 and A3 in the simplified schematic below) and a
summing amplifier (AI) to provide simultaneous lowpass, bandpass, and high-pass responses. One UAF41 is
required for each two poles of low-pass or high-pass
filters and for each pole-pair of bandpass or band-reject
filters.
.

To obtain band-reject characteristics the low-pass and

HIGH·PASS
OUTPUT

= AHP = A.

LOW·PASS
OUTPUT

BANDPASS
OUTPUT

13

14

5Dl
e calculated for any desired ripple and number of poles
for the Chebyschev response. Consult the references on
last page for other information.

I

Note. that for bandpass and high-pass filters complex
conjugate pole pairs in the actual filter correspond to
single poles in the normalized low-pass model. Thus four
poles i~ Table I would correspond to four-pole pairs in a
bandpass or high-pass filter.

II

Q

4-63

Filters with. an odd number of poles ~h'ow one fn with no
correspondIng Q val!!e; This represe'lts a simple RC
network that is required for odd pole filters. This RC
'network· with a cutoffJrequency equal to fn times the
overall filte( cutoff freque!lcy should be placed in series
with the first UAF two-pole section. The. uncommitted
internal op amp with'an extern,lI RC network can be used

for this purpose.
The cutoff frequency deteriniti~d by the Table.I filter
parameters is (I) the -3d B frc;ql1ency of the Butterworth'
response and of the Bessel response and (2) the frequency
at which' the amplitude response ofthe Chebyschev filters
passes through the maximum ripple band .(to enter the
stoP band).

TABLE I. Low-Pass Filter Parameters.
CHEBYSCHEV
NUMBER
OF POLES

2
3

4

5

6

7

8

BUTTERWORTH
fn( I)
Q

BESSEL
fn(1 )

1.0

0.70711

1.2742

O.5dB RIPPLE
Q

fnC!)

0.57735

1.231J4

Q

2dB RIPPLE
fn(2)
Q

0.86372

0.907227

1.1286

1.0

,

1.32475

----

0.626456

--- -

0.368911

----

1.0

1.0

1.44993

0.69104

1.0681l53

1.7063

0.941326

2.5516

1.0

0.541 III

1.43241

0.52193

0.597002

0.70511

1306.5

1.60594

0.H0554

1.031 :270

2.9406

0.470711
0.963678

0.9294

1.0
1.0

----

1.50470

----

0.362320

----

0.218301l

----

1.0

0.611l05

1.55H76

0.56354

0.690483

1.1778

0.627017

1.77509

1.0

1.61 Il 12

1.75H12

0.91652

1.017735

4.5450

0.97579

7.23~28

1.0

0'.51763

1.60653

0.51032

0.396229

0.68364

0.31611

0.9016

1.0

0.7071 I

1.69186

0.61120

0.768121

I.RI04

0.730027

2.84426

1.0

1.93349

1.907H2

1.0233

1.011446 6.5128

0.982828

10.4616

1.0

----

1.6X713

----

0.256170.·

----

0.155410

----

1.0

0.55497

1.719 I I

05.~,235

0.503863

1.0916

0.460853

1.64642

1.0

0.H0192

1.82539

0.660H3

0.1l22729

2.5755

0.797114

4.11507

1.0

2.2472

2.05279

1.1263

1.00H022

H.H4IH

' 0.987226

14.2H02

1.0

0.5091l0

1.7~143

0.50599

0.296736

0.67657

0.237699

0.H9236

r.O

0.60134

1.83514

0.55%1

0.598874

1.6107

0.571925

2.5327

1.0

0.H9998

1.95645

0.71085

0.861007

3.4657

0.842486

5.58354

1.0

2.5629

2. I 9237

1.2257

/..005984

11.5305

0.990142

11l.6873

.

4.59388

-

( I) -.1 dB, FrClIUenf,;Y.
(2) Frequency at which amplitude resp·onsc passes th'roll~h the ripple hand.

NORMALIZED LOW-PASS CHEBYSCHEV

and low-pass UAF outputs. Either of the configurations
in Figures 3 and 4 can be used to provide the band-reject
function if they are used as shown in Figure 2 .
The 15k!} resistor is adjusted for maximum rejection.
The .circuit in Figure 2 is applicable when lising design
equations"A" (ALP = AHP). When design equations ".8"
are used (ALP = IOAHP), the resistor at pin I must be 10
times the resistor at pin 13 to obtain equal pass-band
gains above andbelowfn.
In either crase, the four external UAF resistors (Ro, RQ ,
RFI and RF2) should be calculated for fo and· Q of the

Table'lI gives a FORTRAN' program for the determin. ation of fn and Q for a general normalized Chebyschev
low-pass filter of any ripple and number of poles.
Program inputs are thenlimber of poles (N) and the
peak-to-peak ripple (R). Program outputs are fn and Q,
which are used exactly as the"valuestaken,from Table I..
BAND-REJECT TRANSFER FUNCTION

The band-reject is achieved by summing the high-pass

4-64

OFFSET ERROR ADJUSTMENT
DC offset errors will be minimized by grounding pin 3
through a resistor equal to 1/2 the value of RFI or R F2.
The DC offset adjustment shown here may be used if
required.
Offset errors will increase with increases in RF.

band-reject filter desired and for ALP to equal the desired
pass-band gain. An input constraint is that the input
voltage times ABP must not exceed the rated peak-to-peak
voltage of the bandpass output. or clipping will result.

T ABLE II. Low-Pass Chebyschev Program.

+

Supply

lMn·
lOOkn

~'''''''-----''''''''''Ir.-----..j''to pin 14 for bandpass output
to pin 8 for .low·pass or high-pass output.

PI = 3.1415926536
COMPLEX PI101
READ 5. N, R
5 FORMAT 112, FS, 61
A [ SORT I EXPI R/4.342944S)-11
B= 1.1A
AN = ALOGIB+SORTIB"2+1.11
AN = AN/FLOATINI
J = MODIN,21+N/2
D010K=l,J '
RP=SINHIAN1'SINIPI'FLOATi2'K-11/FLOATI2'NII
XIP = COSHIANI'COSIPI'FLOATI2'K-11/FLOATi2'NII
WN= SORTIRP"2+XIP"21
0= -WNli2.'RPI
PIKI = CMPLXIWN,OI
IFIMODIN,2I,NE.0 AND.K.E.O.J.1GO TO 15
PRINT 20, PIKI
GO TO 10
15 F = REALIPIKII
PRINT 30, F
10 CONTINUE
20 FORMATI2X"FN="E20,S"E20,SI
30 FORMATI2X"FN="E20.SI
STOP
END

*May be adjusted for best sensitivity.

Supply

LOW-PASS
TRANSFORMATION
LOW·PASS TO HIGH·PASS
The following simple transformation may be used for
high-pass filters:
fn (high-pass) =

fn (low-pass)

Q (high-pass) = Q (low-pass)
LOW·PASS TO BANDPASS
The low-pass to bandpass transformation to generate fn
(bandpass) and Q (bandpass) is much more complicated. _
It is tedious 10 do by hand but can be accomplished with
the FORTRAN program given in Table III. This
T ABLE III. Low-Pass to Bandpass Transformation
Program.

13
HP
F-----(:)

COMPLEX P, S, U
READ 5, FN, 0, OBP
5 FORMAT 13F12.51
V=FN'SORTI1.-ll.110'2.11"21
X=-FN/IO'21
P=CMPLXI X, V)
U=CONJGiPl
DO 30 1=1, 2
S=P/12.'OBP)
P=S"2-1.
T=ATAN2IAIMAGIP),REALIP))
IFIT,GE.O) GO TO 10
T=2.'3.1459+T

r-------,
UAF with
, Exl.rnal R.II.....

IOkn

Uncommlnad Amp

Blnd·Rel.ct
Output

10 T=T/2
A=SORTICABSIP))'COSIT)
B=SORTICABSIP))'SINIT)
S=S+CMPLXIA,B)
FN=CABS(SI
. O=-FN/(2.'REAL(S))
PRINT 20, FN, 0
20 FORMAT (2X'FN =·F12.5"O ="2.5)
IFIAIMAGIU).EO.O) GO TO 40
30P=U
40 STOP
END

lUkn

FIGURE 2. Band-Reject Configuration.

4-65

A.p - for bandpass output~gain at fo
AHP ; for,high-pass 'output - gain at high frequencies.
2. Refer to Performa'nce Curves for full power response.
'When selecting the gain, insure tliat the limits of the
curve are not exceeded for the desired voltage range.

program automates the tranform.ation
s = p/2 ± J(p/2)2 - I.
.
PROGRAM, INPUTS:
I. fn -From Table I for the low-pass filter of interest
2. Q - From Table I '
3. QBP - Desired Q of the bandpass filter
For filters with an odd number of poles a Q of 0:5 should
be used where Q is not given in Table I. Enter 10' for Q
when transforming zeros on the, imaginary axis.

NATURAL FREQU!NCY.(fo)
I. fo for each one pole-pair band pass filter is the center
frequency (fe). fe is defined as fe = ,ffJ; where f. is the
lower -3dB point and f2 is the upper -3dB point ofthe
pole pair response.
.

The program transforms each low-pass pole into a
bandpass pole pair. Thus a thiee-pole low-pass input.
would result in the pole positions for a three-pole pair
bandpass filter requiring three U AF stages.
DENORM~LIZATION OF PARAMETERS
Table I'shows filter parameters for many 2- to 8-pole
normalized low-pass filters. The Q and the normalized
undamped natural frequency. fn for each two-pole section
are shown. The Q values do not have to be denormalized
and may be used directly as described ill the Design
Procedure Summary. fn must be, denormalized by
multiplying it by the desired cutoff frequency of the
actual overall filter to obtain the required frequency. fo
for the design formulas. As an example. consider 1\ 4-pole
low-pass Bessel filter with a cutoff frequency of 1000Hz.
The first stage would be designed to an'foof 1432.41 Hz
and a Q of 0.52193 while the second stage would have an
fo of l605.94Hz and aQ of 0.80554. To combine the two
stages into the composite filter the low-pass output of the
, first stage (pin I) would be connected to the input
resistors (Ro) of the second stage.

DESIGN EQUATIONS "A" AND "S"
I. Forfo below 8kHz. eitherofequations"A"or"B"may
be used.

2. For fo above 8kHz; equations "B" must be used. If
equations "A" were used above 8kHz. the filter could
become unstable.
3. Equations" A" are for the U AF as It is supplied. When
using equations'''B", a 5.49kO resistor inust be placed
in parallel with R2 (between pins 12 and 13).
4. The values of RF. and RF2 calculated with equations
"B" are approximately one-third of those calculated
with equations "A". Thus there may be an advantage
in using equation "B" at low frequencies. Using
equation "B" would require use of one. more resistor,
-but that would not aher or affect filter performance in
any m.anner.
5. Using the negative gain values for ALP or AHP or ABP
could result in the negative values for resistors RG and
R Q • So the absolute value of the gain should always be
used in the equations.

2. To obtain fo below 100Hz using practical resistor
values, capacitors may be paralleled with C 1 and C2 to
reduce the size of RF• and Rnlf capacitors are added
in parallel,
, I~OpF
RF• (new) = RF2 (new) = RFI (old) C + lO00pF
where RF (new) is the new lower value frequency
resistor, C is the value of the two external capacitors
placed across CI and C2 (between pins 7 and 8 and
pins I and 14 and RF. (old) is the value calculated in
the simplified design equations.
Q-FACTOR

fo
I. For bandpass filters Q = 3dB bandwidth

,

2. When designing low-pass filters of more than two
poles, best results will be obtained if the two p~le
sections with lower Q are followed by the sections with
higher Q. This will eliminate any possibility of clipping
due to high gain ripple in high Q sections.
3. Q repeatability (Q change from unit-to-unit) is
typically· ±5% for foQ products less than 104 • The Q
repeatability error increases as the foQ product
increases to approximately ±IO% for foQ products
near 10'.
QpPROCEDURE
I. If the "fo times Q",product is greater than 10'. it is
possible for the measured filter Q to be different from
the calculated' value of Q: This effect is the result of
non-ideal characteristics of operational amplifiers. It
can be compensated for by introducing the parameter
Qp into th~ design equations.
2. Calculate the foQ product for the filter. If the product
is above IO'Hz, loc~te the corresponding foQp product
in the Performance Curves. Divide foQp by fo to obtain
QP. Use Qp as indicated in the design equations. For
foQ products below 105 Hz, Qp = Q.
'

GAIN (A)

I. ,The gain (V / V) of each filter section is:
ALP - for low-pass output - gain !It DC

4-66

CONFIGURATION SELECTION GUIDE
It is possible to configure the UAF4l three different ways. Each configuration

produces features that mayor may not be desirable for a specific application.
This'selection guide is given to assist in determining the most advantageous
configuration for a particular application.
NONINVI:RTI~(;

INl'llT

INVERTIN(; IlI:l'liT

BI QlIAD

Outputs Availahk'

Ill'. 1.1' and III'

Ill'. 1.1' .",d III'

HI' and LI'

OUIPUIS Inv~rlc'd wilh rcslwc'l
10 th~ Inpul

Ill'

III' and 1.1'

HI' and 1.1'

Fr('qU('ll~Y R('sist~lrs?

Yes

Ycs

~o

Typc "I' Q Variali"n
Wilh (,han~~s in RF

('onsl."'1 Q

('onsl.1Il1 Q

('onslanl
B.",dwiulh

Q & Cain Indcpcndcnl or

Advanla~~s

Olhcr

Ro

May eliminale one exll'rnal

R(; and
arc small al high
rrequencies

resistor (usc inlcflwl R3:.1s R(j)

Par~lInct('r

~ Q p ' ABI' > I (Eqns. "A")
JAX Q p . ABI' > I (Eqns. "B")

Limitations

~ Q p + AIll' > I (Eqns. "A")
"AX Q p + AIll' > I (Eqns. "Il")

No III'
Output

Summary: The Bi·Quad nller is partkularly useful as a hand pass !iller if Ihe filler handwidth must he kept constant as
the center rrequency is varied. If Q musl he kept constanl (i.e .. constant Q or a handpass or maintaining a
consiant response of a low-pass or high-pass) one of the other two configurations should be used. The Bi·Quad
also has the advantage that RC; and RQ arc smaller than with the oiher two configilrations (this is especially
useful at high frequencies). The noninverting input configuration has the advantage that for ABI' = I.
Re; =50kH: thererore R" (internal) may be used so that only three external resistors arc needed (RFI. RF2. RQ).

UAF41 CONFIGURATIONS AND DESIGN EQUATIONS
NON INVERTING INPUT CONFIGURATION
SIMPLIFIED DESIGN EQUATIONS "A"
109

I. RFI '" RF:z

50lUl

1.592 x 108

"'-W;"'--'o--

13

RI

S.Ox 104 Q
3. KG = AepQp
5.0 x 104
A
Q

4.R Q =

2Qp-

B; '-1

SIMPLIfiED DESIGN EQUATI'aNS "8"

t

Input
SIDnl1

> 8kHz
..j'iOx 10 8 . 5.033 x 107
Rn =-:;--"'-'-0--

MUll be used for fo
J.

RFI

=

Q
2. ABP=-ALP'" 3.16QAHP
3.16

S.Ox I04Q
J. RG "'-A-.-p-Q-p•. , RQ =

--...:;;:;=-=-AB~

N/e

5.0x 104

3,48Qp _

Qp _ 1

FIGURE 3. Noninverting Input Configuration.

4-67

14

INV~RTIN~ INPUT, CQf\lFI~Ut:tArIOf\l
SIMPLIFIED DESIGN EQUATIONS

"A~'

10' 1.5'2 lI. 108
I. RFI '" RF2

=W;'" --'.--

2. Asp '" Qp ALP"" Qp AHP

.

l. R G " 5.0"lI. 104 Qp

4.R;~
2o,+"B,-1

Q

SIMPLIFIED DESIGN EQUATIONS "B" t
Must'be IIHd for

'0

)18kHz'

.Jiij. 108 _ 5.033l1. 107
I. RFI "Rn =~ - - , - . - Qp
2. A ap='3.i6"LP" 3.16Qp"HP

3. RG '" 1.51. 104 Op
ABP
5.0.104

FIGURE 4. Inverting Input Configuration.

BI-QUAD CONFIGURATION
SIMPLIFIED DESIGN EQUATIONS "A"
10' 1.592.x 10'
I. RF,=RF2"~=-,-.,--

l. RQ " Qp RFI
RQ
4. R O " A BP

SIMPLIFIED DESIGN EQUATIONS

"a"

t

MUlt be uled for fo .. 8kHz

I. R· ... I

Z

Rn = "lOx 10'
Wo

2. Aap

=~
fo

=3.16 Q ALP
'External Rlliitara

FIGURE 5. Bi-Quad Configuration.
t To use equaHons "S~ connect a S.49kO resistor between pins 12 and 13.
~quations "S" are also: valid for frequencies below 8kHz.

DETAILED TRANSFER FUNCTION EQUATIONS
The following equations show the action of all the internal and external UAF41
filter components. They are not required for the regular. design procedure but could
be used if a detailed analysis is required.
NONINVERTING INPUT CON,FIGURATION
K .. l{n I{F2'("

('2

I I 1(4 (K(: IRQ)

K(: Kl.)

("'2 "'FI ('1 r'h
K J KF2 ('2

3. 0 ALP'" Q AUp

(~

2

1+

!!.

"

6.

AUp=~.

G

) '" A tW (: I : ... 1
2

F2

~~ I)V!
2

INVERTING INPUT CONFIGURATION

BI·UUAO CONFIGURATION

ACTIVE FILTER DESIGN EXAMPLES USING THE DESIGN
PROCEDURE OUTLINED IN DESIGN STEPS SECTION.
Example I.

Step~.

It is desired to design a three-pole, 0.5dB ripple,
Chebyschev High-Pass Filter; the cutoff frequency Co =

f. Q = 1871.2 x 1.7062 = 3.19 x 103
:. fo Q < 10'
:. Qp = Q = 1.7062

2kHz, Gain AHP = +1.
Step-.J.
The type of transfer function (high-pass), the type of
response (Chebyschev), number of poles (3), and the Cllt
off frequency (f,) are chosen depending upon the
particular application and are stated in the example.

~-.2.

ADP = Qp
R . = 5.0

X
X

AHP = 1.7062 x I = 1.7062
104 x 1.7062 = 29 3kfl
.

I. 7062 x 1. 7062

(,

5.0 x 104
RQ = 2 x 1.7062 _ 1.7062 _ I = 70.8kfl

Step-.l,.
Normalized low-pass filter parameters fn and Q are
obtained from Table I (or from program shown in Table

The above obtained resistor-values are for the complex
pole pair of the first stage of the required active filter. The
simple pole obtained as outlined below, using the
uncommitted op amp in the UAF41 makes the second
stage of the required filter.

II).

Complex Poles:
fn = 1.068853 ]
Q = 1.7062 .
Simple Pole:
fn = 0.626456

For the simple pole fn was obtained in step 3.

Step.J.
Now, since the actual response desired is high-pass, the
low-pass to high-pass transformation must be made as
previously discussed in Low-Pass Transformation.

The actual (denormalized) frequency = ( x fn

fn (high-pass) = f

1_
Now f= __
,
21TRC

n (low-pass)

f n = 1.59628 I

= 2kHz x 1.596281 = 3192.6Hz

' QHP = QLP

:. For Complex Poles:
fn = 1.068853

I'
21Tf

:. RC = -

4.9851 x 10-'

21T x 3192.6

0.935582
Choosing C = 2200pF (or any convenient value),

and Q = 1.7062
4.9851 x 10-'
R = 2200 x 10-"

For Simple Pole: fn = 0.6;6456 = 1.596281

22.66kH

Note:

Stel14.
Now, determine the actual (denormalized) frequency.
f" = f, x fn = 2kHz x 0.935582 = 1871.2Hz

R and! or C may be chosen in any convenient manner to
obtain the desired RC product.
The overall circuit for the required filter is shown below:

't.,p~.

-fer to the Configuration Selection Guide. Since the
required is positive, the H P output is not inverted
with respect to the input. Therefore, the noninverting
input configuration must be selected. Note that the HP
output is not available with the Bi-Quad configuration.
~ain

85.l18kn

-15V +15V

85.08tn

14

10

Step....§..
Since f.

1...----19

< 8kHz,

In Rs

Equations" A" would be used.

1\

Step~.

I
IZ200PF

13!-t~_~
I

I

!B.3kn

For the Complex Poles Stage of the filter, using the
equations "A".
1.592

X 108

1871.2

HI)

22.lIIIkn
71A3kn

=

85.08kfl
FIGURE 6. Overall Circuit - Example 1.

4-69

ExamPle 2.

..

.

It is desired to design a 4-pole Butterwor~h, Bandpass
Filter, withQ = 25, t = 19kHz and A,;'; = I . '

.Example 3.
It is dcsi~ed' to design ~ 5-pole
. with L;=-BkHi a.nd ALP \=.1."

2.6118kO

Since f. > lOS, locate the corresponding f.. Qp fromthe
Performance Curves.
Divide f.Qp by f. to obtain QP.
Thus Qp = 48.76
5.0

X

104 x 35.36541
I x 48.78

104
48.78
3.48 x 47.78 - 35.37 -I

R _.
Q -

5.0

X

For Stag!:..!.
f. = 3.3kHz x fn = 3.3kHz x 1.55876 = 5144Hz
~ince fo > 8kHz, equations "A" would be used.
1.592 x 108
R~I = RF2 =
5144
30.95kO
foQ = 5144 x 0.56354 = 2.9 X 103
foQ> lOS, :. Qp = Q = 0.56354
ABP = Qp .ALP = 0.56354 x I = 0.56354

36.25kO

R -

298.70

0-

5 x 104 x 0.56354
= 50kO
0.56354

5 ~ 10'
RQ = 2 x 0.56354 + 0.56354 _ 1.

. For Stage 2.
Following the same procedure as shown for Stage
above, the values shown below are obtained.

72.4kO

For Stag~.
fo = 3.3kHz x fn = 3.3kHz x 1.75812 = 5802Hz
Since fo > 8kHz, equations "A" would be used.

f.'Q = 6.624 x 10', using the Performance Curves,
Qp = 48.04
RFI = RF2 = 2.6867kO
Ro = 36.8kn
and RQ = 303.40
The overall circuit for the required filter is shown below.

1.592 x 10'
5802

27.44kO

foQ = 5802 x 0.91652 = 5.32 x 103
foQ> 10', :. Qp =Q = 0.91652
ABP = Qp ALP = 0.91652 x I =0.91652

·15V +15V

·15V +15V

.

Using the above shown values of fn and Q, we now will
proceed to design the three stages of filter separately.
Anyone of the three configurations can be used. We will
select inverting configuration.

f.Q = 19270.6 x 35.36541 = 6.815136 x 10'

Ro =

5
Ro =
RQ

X

io' x 0.91652
0.91652

50kO

5 x 10'
2 x 0.91652. + 0.91652 - 1

= ~8.58kO·

,

For Stag!:..1.
f = 3.3kHz x fn = 3.3kHz x 1.50470 = 4966Hz

For the simple pole,
298.70

Filter

fn = 1.55F6 ]
Q = 0.56354
fn = 1.75812 ]
Q = 0.91652
Simple Pole:
fn = 1.50470

For Stag!:...!.
f.. = 19kHz x fn = 19kHz x 1.0142435 = 19270.6Hz
Since fo > 8kHz, equations "B" would be used ..
- R - 5.033 X 10'
FI - F2 - 19270.6

'. ,

From Table 1 the following values of f. and Q are
obtained.
Complex Poles:

Using the computer program shown in Table 111, the
following values of fn and Q are obtained.
fn = 1.0142435, Q = 35.36541
and
fn = 0.9859565, Q = 35.35886
Using the above shown values of Q and fn, we now will
proceed to design the two stages of filter separately.
Anyone of the three configurations shown in the
Configuration Selection Guide can be used, We ,will
select the non inverting input configuration.

R

Bis~el: Low-Pas~

303.40

llt'

RC =

2~ =

271' xl4966 = 3.2049 x IO- s

3300pF (or any convenient value)

FIGURE 7. Overall Circuit - Example 2.

4-70

3.2049 x 10-'
R = 3300 x 10-"

USEFUL REFERENCES

9.71kH

I. G.E. Tobey, J.G. Graeme and LP. Huelsman,
Operational Amplifiers: Design and Applications,
(Chapter 8) McGraw Hill Book Co., 1971.
2. Yu Jen Wong, William E. Ott, Function Circuits:
Design and Applications, (Chapter 6)' McGraw Hill
Book Co., 1976.
3. Richard W. Daniels, Approximation Methods for
Electronic Filter Design, McGraw Hill Book Co.,
1974.
4. Anatoll. Zverev, Handbook of Filter Synthesis, John
Wiley and Sons Inc., New York, N.Y., 1967
5. Gabor C. Ternes, Sanjit K. Mitra. Modern Filter
Theory and Design, John Wiley and Sons, New York,
N.Y., 1973

The overall circuit is shown below.

5t
C
=

~

FIGURE 8. Overall Circuit - Example 3.

4-71

BURR - BROWN ®

IElEI'.

PRECISION OSCILLATOR

Opllonal exlllrnal components for varying fl'1quency.
. Use Iwo matched capacitors or two matched resistors.

FEATURES

. F+15VDC

------- --I
I.

\

• FIXED FREQUENCY - 10Hz to 20kHz

Wien Bridge Oscillator

• STABLE AMPLITUDE

.---...

• SINE WAVE OUTPUT

r- X

• LOW DISTORTION

I

T

+15VDC

.

I

Cz

I

RZ

I
I

;- 3

DESCRIPTION
Model 4023(25 is an all solid-state, ultra-stable sinewave oscillator. Both "output amplitude and
frequency are constant, and the stability of both with
time and temperature variations is excellent. Internal
high-performance Burr-Brown Ie operational
amplifiers are used to form a Wien bridge oscillator
circuit and to regulate the output amplitude. The
frequency of oscillation is within ±I% of the
customer-specified value. If desired, external
components may be· added to trim the frequency to
an exact value. Adding two external resistors will
raise the output frequency and adding two external
capacitors will lower the output frequency. With its
small size, low distortion, and excellent freql,lency
and amplitude stability, the Model 4023(25 is ideal
for use as a reference oscillator in airborne or mobile
equipment, specia!"purpose test equipment, and in
telemetry systems. To order, specify Model4023 (25
and frequency.

~

,J,~

+~

I RI
L_L 2
Common -= I
I
I

I
CI

I...

I
I

Inverter

:~rn

Gain .
Control
Network

IDlljJF

I
I
I
I
I

I
I
II
.Precision
I
. . , . - - -...... Reference Voltage I

I

I

Integrator

t

__ l'~J

,

I

'----11-----'

~.15VDC

\.. Optional external component
for minimizing distortion.

.

.

International Airport Industrial Park· P.O. Bax 11400· Tucson. Arizona 85734· Tel. 16021 748·1111 . Twx: 91(1.952·1111 . Cable: BBRCORP . Telex: 66·6491

4-72

ELECTRICAL
SPECIFICATIONS

may be lowered by externally paralleling the internal
capacitors C, and C,; and the frequency may be raised by
paralleling the internal resistors R, and R,. The nominal
values of C, and C, will be as follows:
C, and C,
Frequency fn
10Hz to 100Hz
O.I",F.
101 Hz to 1000Hz
O.OI",F
O.OOI",F
1001Hz to 20kHz

Typ iccl performance at 25°C and
with rated supply unless otherwise noted

FREQUENCY
Range (1)

Customer specified, may be any
value From 10 Hz to 20 kHz.
± 1%, (May be trimmed by the user
to less than ± l%f
0.04%/oC (max.)

Accuracy
Stability vs. Temperature

OUTPUT (3)
Ampl itude - Output A
- Output B
Amplitude Accuracy

6Vrms
3 Vrm. (with 600

~

It is important to pad both R, and R, or C, and C, by an'
amount to keep distortion within specifications.

~qual

If the frequency is lowered by a significant amount, it
may be necessary to externally parallel the integrator
capacitor C, to lower distortion of the output.

load)

±2%

Impedance - Output A

1~

- Output B
Rated Load - Output A
- Output B
Dist~rtion (max.)

600~

The range of frequency adjustment is approximately 2
decades (within 10kHz and 20kHz). For example, a 10Hz
unit may be trimmed for a frequency of up to I kHz or a
10kHz unit may be varied down to 100Hz. However, the
distortion and amplitude stability specifications are
guaranteed and tested only for the nominal frequency of
oscillation. In general, the degradation in distortion and
amplitude stability as the frequency is varied over a wide
range is very small.

1.2 k ~
600 ~
0.1%

AMPLITUDE STABILITY
vs. Temperature (max.)
Noise and Jitter (max.)

0.02%/oC
0.02%
0.1%

. Long Term (max.)

TEMPERATURE RANGE
Operating,
Rated Specifications

-250C. to +85O C
- 55°C to + lOOOC'

Storage

POWER REQUIREMENTS
Rated Supply
Voltage Range at 25°C (2)
Supply Drain ·(max.)

INSTALLATION

±15 Vdc
±12 Vdc to ±18 Vdc
±40 rnA

(1) To order, speciFy Model 4023/25 and Frequency.
(2) The p6sitive and negotivesuppl ies must.be balanced
within 2% of each other.
(3) The output may be taken from either Output A or
Output B (not both).

MECHANICAL SPECIFICATIONS
f
!

~:~"(45.'}

.

~:s

'"

G! j;
~J>+

r-

"-

'~

'f~b"

10

0.1

"
<"

'4

~.,

I
I

0.Q1

1/'

~
<'$",v

'"

~O.25mm)

~O..,QttI'Pi"'

1.385

2.54 BASIC

.100 BASIC

12"";

LD

[f

MIN

ci .....

~A=:J'

RT~A~

1.310

0 ••

"

..

- ~ r-...

'E"

r....

l;

t"""

lk
100
Input Frequency (Hz, Sine Wave)

<::

',I
D.Ol

0.001
100

10k

4-76

'/

lk
10k
Input Frequency (Hz, Sine Wave)

lOOk

THEORY OF OPERATION
in the capacitor even though the input voltage may
become larger thim the peak voltage. In the Reset Mode
(S I open. S2 open). the voltage on the capacitor will
charge to whatever voltage is applied to the reference
voltage input. If both S I and S2 are closed at the same
time. the output of AI will be connected to the reference
voltage input through a low impedance.. This represents
an illegal mode of operation. but will cause no damage to
the unit.

In the Peak Detect Mode(SI closed. S2 open). the analog
output tracks the analog input until a peak value is
reached. When, the input voltage falls below the magnitude of the peak voltage. CR I becomes revc:rsed biased.
and the feedback loop between Al and A2 is broken. At
this point. the status output transistor turns on and the
magnitude of the peak voltage is held on the analog
output I n the Hold Mode (S I open. S2 open). the current
charging path from the output of Al to the capacitor is
opened. The output voltage is equal to the voltage stored

NC

NC

Cammen

(II

StalUB
Rlturn

'NC

SlIIUI

NC

Oulpul
17

Hi:

NC

Reference (21
Vollage
13

S2

Inpul

-

6
NC

on.1I

NC

G)
logic
IIIfIUI

AdJull

NC

Logic
Power
Supply

Nol81:
1. Pin 21 Inlemally clllln.- 10 CUI on 40858M and 4085SM.
2. Pin 13 mUll bl cOMIICIId to Iithir powlr supply'common or I user-speciliad raterlflC8 voll.... Refer 10 Application Bectlon lor details.
3. External capacllor: UBI polystyrene (up 10 .as·CI. palYPl1lplene, or leflllll.

Optional
External (31
Capacllor

FIGURE 1. 4085 Functio~al Diagram ~nd'Pin Configuration.

ANALOG
INPUT
(dottedl

~---7

ANALOG
OUTPUT
(1Dl1dl

"

.....

, ,,

. ,.,

"
I

,

"\
,

I

..

... ..

I

"

, ...

,

""

",,"

",:""
.
,

OV
"I"

LOGIG
INPUT
LOGIC
INPUT
STATUS
TRANS·
SISTOR

''0''

A

I

I

- - -....-11.... . - - - - - - - hold - - - - - - : - -..'+1....- - - relli - -

i- reall
"I"

"0"

""•

I

on
On

1

n

I

FIGURE 2. Timing Diagram For Peak-Detect Operation.

4-77

I

I

OPERATING I NSTRUCl'IONS> ,
QFFSET VOLTAGE ;ADJUSTMENT
The ±2mYillPut of(set voltage ,of the 4085 may be n~lled
to zero by using the circuit shown in Figure f .With the
408~ in the Peak Detec(,M,ode (logic input A '7 "I", logic
input B.= "0;1 apply zerovolls to.pin .1. Adjust the
potentiometer until the 'putput voltage is zero v,olts.
Disconnect pin 12 after adjustment is made.
·15VOC

JDkn

.t

~

!

"N.onirive'rting'" Ineans logic" I" = peak has been detected.
"
.'

t).....:.-.......- - - To TTL\lan....t = 10)

(Remove 2.Okn
reslaIDr lor, 15VOC .
CMOS logic.)
.

Pin 2
21m ID 101m

FIGURE 5. Inverting ITL(CM05) Status Output.'

.f IDDp~m/OC,..;
560kn.
IOMQ.
~

Pin 3
Pin 12

2iiiA

+5vilc

IOkn

FIGURE 3. Offset Adjust·Circuit:

j)-_-:--~

POWER SUPPLY CONSIDERATIONS
The 4085 will operate as specified with power supplies
from ±8VDC to ±18VDC. To minimize npise pickUp, the
supply inputs should .be decoupled with I~F tantalum
capacitors located physically close to the unit.

To TTL

FIGURE 6. Noninverting TTL.Status Output.

DIGITAL INPUTS AND LOGIC SUPPLY
The digital inputs may be driven with TTL or CMOS
logic. Pin 8 should be tied to the logic supply. The)ogic
supply voltage (Vd may also be provided by connecting
pin 8 through a resistor of yalue R (kO) = 1.67 (Vee
-Vd/VI. to the +Vee (Vee; ;;;. Vd'. The logic threshold
voltage is equal to O.4VI. - O.7V.

FIGURE 7. Noninverting CMOS Status Output.
INPUT FREQUENCY 'BANDWIDTH LIMITING
DESIGNING .INHYSTERESIS
It may b¢ desirable in Some situations to have hysteresis
in the circuit such that small peaks will not he detected,
eliminating jitter' in the Status output. This is possible
through external components connected as shown in
Figure 8. After a peak is detected, the input voltage must
be slightly greater (determined by' R 1/ R2) 'than the
previous peak to cause the output to resume tracking the
input. This hysteresis voltage is expressed by:

It is recommended that the input bandwidth he limited as
much as possible by an RC section such as that shown in
Figure 4. This is to limit noise spikes at the input thll! may
cause erroneous readings. If detecting large pulse heights,
a 5~sec time constant should be used, This will not
degrade acquisition time or trac\<:ing a~curacy for frequencies up to 500Hi. For input frequencies greaterthan
500Hz, a smaller time constant may be used.

.vln Q---I'>N.'-'-~:L_---10
Ikll

~

Pin I

V _ (V;n - VE -0.9V) R(
11RI + R2

47DDpF

FIOURJ":4.\1nput Bandwidth Limiting.
STATUS OUT~UT CHARACTERISTICS
The openccollector, open-emitter. output transistor is a '
small signal, medium speed switching transistor similar
to a 2N2222. To facilitate driving a variety of devices, the
configuration of the status output has ,been left to the
user's discretion.
'. '
.

. The erriitter voltage of the status transistor should be tied
to a voltage sufficiently lower than the lowest expected
peak to allow proper operation.

The internal comparator shown in the block diagram
(Figure I) has an output characteristic as follows. Input
signal track: Zou, --0; peak hold: You, = +Vcc - O.5V.
Several configurations a~e illustrated in Figure~ 5, and
7. "Inverting" means logic "0" = peak has been detected.

6;

RI

HGURE 8. Hysteresis.

4-78

APPLICATIONS
PEAK CATCHER
This circuit detects and holds the first peak it encounters.
After the first peak is detected, it automatically is
switched to the Hold M ode. To reset the circuit for
catching another peak, a lOf.Lsec or longer positive logic
pulse should occur at the Release Input. This wilt reset
the peak detector to the desired voltage and put itin the
peak-detect mode.

220n

FIGURE 9. Peak Catcher.

Olgltll
Output
AOCBO
End
of Convert

FIGURE 1.1. AI D Converter Interface.
PEAK-TO-PEAK DETECTOR
Figure 12 shows a circuit that will display the peak-topeak voltage of an input waveform. The Status Output
indicates that both positive and negative peaks have been
detected and that the output is valid. The resistors around
A3 should be matched to insure good common-mode
rejection.

NO-RIPPLE, FAST-SETTLING RMS-DC
CONVERTER
If a waveform is known, the rms value of the signal may
be computed from the peak value. In this circuit, the rms
value is computed by the output amplifier from the peak
value held by the 4085. The output in the circuit shown is
updated manually. It may be updated automatically by
replacing the switch circuit with an oscillator plus timing
logic.

Vlno---_~
A
B

FIGURE 12. Peak-to-Peak Detector.
REFERENCE VOLTAGE
In the Reset Mode the voltage applied. to pin 13 places an
initial charge on the holding capacitor at the input to A2
(see Figure I). This threshold voltage may be any value
between positive and negative 10 volts. For most applications pin 13 will be tied.to power supply common. This
sets VRer to 0 volts. The 4085 will then capture peaks
greater than 0 volts.
Pin 13 must be connected to either power supply
common or to a user-specified reference voltage. If this
connection is not made the 4085 will appear to have
excessive droop.

FIGURE 10. RMS-DC Converter.
INTERFACING TO AID CONVERTER
Interfacing to an AI D converter is straightforward. The
gating of the AI D converter command allows a conversion only if a peak has been detected and permits
completion of each conversion. If a peak occurs while the
AI D is converting, it will not be detected.

4-79

4115/0-4

BURR -BROWN@

::IElel·
I·:

WINDOW COMPARATOR
FEATURES

ApPLICATIONS

• ADJUSTABLE LIMITS FOR "HIGH", "LOW", AND "GO"

• PRODUCTION LINE TESTING

• UP :rO 200mA LOAD CAPABILITY (each output)

• TEMPERATURE CONTROLS

• INPUT PROTECTION

• INDUSTRIAL ALARMS
• LEVELDETECTORS/CDNTROLS

DESCRIPTION
Model 41 15/04 is a hybrid IC window comparator in
a double width DIP .. The unit h~ three inputs - one
for a ·voltage that sc;ts the upper limit, another for a
voltage that sets the lower limit, and a signal input.
There are three mutually c:xclusiveoutputs - HIGH,
LOW and GO. When an output is ON it will sink up
to 200mA of current. This input diode protected
device is designed to work with input voltages of up
to ±IOV, and willnot.be harmed by voltages to±15V.
The 4115/04 will drive a variety of loads including
lamps, relays, MOS circuitry, and high noise
immunity logic as well as DTL .and TTL devices.

Typkal Luad

r-----4-;-;S;4---··--'HIGH
:

Windt!w ('umparawr

~~iP:~r l-:u 0-2 ~I"""'r1..-.r.=--

Input

Input
"iiltnal

I
I
)1
F
I
'10+'1
1 MA........
I

1

Luw\!'r. 51
limit l-·LO-;-.,.,.................V
Input

I

I8

1L ____________":'
-11
Eu1
3
o to +30

Mll
1I
V

+200

mA

+400

mA

Go .............. +.J.~ ..
Common ... 8-.+.++ .. 7 Low

0.7

V

II- ,600"

-25 to +85
~40 to +85
-55 to +100

~12

±15
to ±18
±15

(Bottom View)

r

(

A dimple appears

-ISV .14 -t + 1" 'il
over pin space I
+ J SV ... J.
-t + + -+ Eu
tt2·t + ... ·... 3+ EI

-+

+.'+--1"-+ +4--+

High tlO' T

~

++ .. 5 ~

.760"

...J I
~

EL

0.1" (2.54) Grid

"C
"C
"C

WEIGHT: 0.24 0'. (6.80 gram,)
MATERIAL: Black Exoxy
PIN: Pin material and plating composition. conform to
Method 2003 (solderability) of Mil~Std-K83 (except
paragraph 3.2).
CONNECTOR: Fits any commercial dual·in-linecorinector.

VDC
VDC
mA

To achieve best results use stable quiet reference sources and drive signal input from low
impedance source. Noise and drift in input sources readily masks the inherently high
resolution of the device.

4-81

BURR-BROWN ®

4127

IElElI

LOGARITHMIC AMPLIFIER
FEATURES
-ACCEPTS INPUT VOLTAGES DR CURRENTS OF
EITHER POLARITY

functions accurately for up to six decades of input
current and four decades of input voltage, In
addition. a newly developed current inverter and a
precise internal reference allow pin programming of
the 4127 as a logarithmic. log ratio. or antilog
amplifier.
.

- WIDE INPUT DYNAMIC RANGE
6 Decades of currant
4 Decades of voltage
-VERSATILE
Log. antilog. and log ratio capability

To further increase its versatility and reduce your
system cost. the 4127 has an uncommitted
operational amplifier in its package that can be used
as' a buffer. inverter. filter. or gain element.

-SMALL SIZE
Double wide DIP

The 4127 is available with initial accuracies (log
conformity) of 0,5% and 1,0%. and operates over an
ambient temperature range of
to +70°C.
'

-LOW COST,

-Ire

With its versatility and high performance. the 4127,
has many applications in signal compression.
transducer linearization. and phototube buffering,
Manufacturers of medical equipment. analytical
instruments. and process control instrumentation
will find the 4127 a low cost solution to many signal
'processing problems,

DESCRIPTION
Packaged in a ceramic double wide DIP. the4127 is
the first hybrid logarithmic amplifier that accepts
signals of either polarity from current or voltage
sources, A' special purpose monolithic chip.
developed specifically for logarithmic conversions.

I

r------------- - -'-- - -- -- -- - ---- - ----,

..: i
I

:
I

lit> Xl

I
I
I

y~ tt> i ::1
yo

LO-+-:- -____
:

C?

Ny

I !

--L

~

w.

'f

~

C?

b-: ;o;---------- - __ -'

L---------

1

~

L~
+15VOC

InternaUanal Alrpartlnduslrlal hrk - P.O_ Box 11400 - T~on. Arizona 85734 - Tal. 1602l 746-1111 - Twx: 910-952-1111 - Cable: BBRCORP - Telex: 66-6491

4-82

SPECIFICATIONS
ELECTRICAL
Typical specifications at+25°C with rated supplies unless otherwise noted
MODEL
ACCURACY!l). % of FSR
Current Source Input: lnA to lmA
Voltage Input: 1 mV to 10V
INPUT
Current Source Input. Pin 4

CLlrrent Source Input. Pin 7
Reference Current Input, Pin 2
Absolute Maximum Inputs

4127KG

I

4127JG

0.5% max
0.5% max

I

1% max
1% max

-lnAto-lmA
+lpA to +lmA
±10mA or ±Supply Volts
±10V
±5mA

FREQUENCY RESPONSE
-3dB Small Signal at Current Input
of 100~A .
of 10pA
of lpA
of 100nA
of 10nA
Step Response to within ±",% of
Final Value liR = lpA. A = 5)

90kHz
50kHz
5kHz
250Hz
80Hz

STABILITY
Scale Factor Drift (.loA/oe}
Reference Current Drift (~IRJoC\

Input Offset Current Drift (.lls/oe)
Input Offset Voltage Drift
Accuracy VB. Supply Variation
Reference Current
Input Off.et Voltage
Input Noise - Current Input
Input Noise - Voltage Input
UNCOMMITTED OP AMP CHARACTERISTICS
Input Oll.et Voltage
Input Bias Current
Input Impedance
Large Signal Voltage Gain
Output Current
TEMPERATURE RANGE
specification
Operating
Storage
POWER SUPPLY REQUIREMENTS
Rated Supply Voltage.
Supply Voltage Range
Supply Current Drain
at Quiescent, max
at Full Load, max

t::d

r
- - ..................
I
B

+lnA to +lmA

OUTPUT
Voltage
Current
Impedance

MECHANICAL

j

t-

24

13

! .......... ~2

R~A---J

rL.-----.,
nr KGJ~~ In(
IF A
LLJ

F""'"

Ion

Seating Plane

NOTE:
Leads in true position withon .0tO"
(.2Smm) R .. MMC at saating plana.

INCHES

DIM

10msec

~

1 p.A

MAX

MIN

MAX

1.310

•. 360
.810

33.27

34.54

.19.56

20.57

C

.150

3.81

5.33

0

.018

.021

0.46

0.53

.035

.050

0.89

±0.003 Ift/°C for 400nA < IR < 1pA
10pA at +25°C. Double. Every 100C
±10pV/oC

5mV
40nA
lMn
85dB
SmA
coe to +60o e
-10 o e to +70°C
-55°C to +125°C

±15VDC
±14VDC to ±16VDC

±20mA
±26mA

NOTE:
1. Log conformity at 25°C.

.770

.100 BASIC
.110
• K

±O.OOliRIV
±300pVIV
1pA, rms, 10Hz to 10kHz
10pV. rm •• 10Hz to 10kHz

MILLIMETERS

MIN

A

•

±O.OO05A1°C

±O.OOl IRloC for IA

Pln numbers shown
for reference only
Numbers may not be
marked on package

.150

.130

.250

..600 BASIC

.002

"

.08'

.010
.105

2.79

3.30

3.Bl

6.35

15.24 BASIC

0.05

0.25

2.16

2.67

CASE: Ceramic
MATING CONNECTOR: 245MC
WEIGHT: 56 grams (2 oz.)
ORDER NUMBER: 4127KG
4127JG

PIN CONNECTIONS
1. IREF OUTPUT
2. IREF INPUT
3. NO PI N PRESENT
4. +I INPUT •
5.·CURRENT INVER"fER OUTPUT'
6. NO PIN PRESENT
7. CURRENT INVERTER INPUT
8. NO PIN PRESENT
9. OP AMP +INPUT
10. OP AMP -INPUT
11. OP AMP OUTPUT
12. NO PIN PRESENT
13. MAKE NO CONNECTION
14. NEGATIVE SUPPLY
15. NO PIN PRESENT
18. NO PIN PRESENT
17. NO PIN PRESENT
18. LOG OUTPUT
19. GAIN ADJUST
20. NO PIN PRESENT
21. COMMON
22. POSITIVE SUPPLY
23. IREFBIAS
24. NO PIN PRESENT

*Pins 4 and 5 are internally
connected.

4-83

1.27

2.54 BASIC

TYPICAL PERFORMANCE CURVES
RELATIONSHIP OF REFERENCE CURRENT 'R

RELATIONSHIP OF SCALE FACTOR"A,"
TO GAIN-SETTING RESISTOR R2

ANO'EXTERNALRESISTOR R,
100llA

e

"-

10llA

K

,~

9V

BV

~

0

1lc

lilA

i

II:

100nA

"

7V

I,,

10kf!

6V

~

./

3V

~

2V

IV

'R

o

lMf!

10Mf!

V
o

100Mf!

/
20kf!

40kf!

60kf!

BOkf!

Resistance

LOG RELATIONSHIP OF l!.§lAND OUTPUT

RELATIONSHIP OF

'R
VOLTAGE IN TERMS OF "AU

"~I

'
TO OUTPUT VOLTAGE

FOR 'R = lilA AND A = 5V AND 10V

Output

Output

Voltage

Voltage

+10V

4V

,+5V

2V

0_0010,01

E =AIOgM
o
lilA
A= 10V

Input
Current

IS'

Input

'R

= -A 109101IS [_ I-I
'R

Eo

I

Resistance

2V

V

j

4V

I

IOOkf!

'/

5V

E'o=-AI0910~
10nA

,

10V
i

1000

-5V

'R

,IR

-10V

DISCUSSION OF SPECIFICATIONS
ACCURACY
The deviation from the ideal output voltage defined as a per'
cent of the full scale output voltage.
INPUT/OUTPUT RANGE

The log relationships of ,~Alog

-:S
R

and ;'A log IESR are sub'

R

ject to the constraints'specified. The 4127 can be operated
witl! inputs lower than those given, but the accuracy will be
degraded.
FREQUENCY RESPONSE
The small-signal frequency response varies considerably with'
signal level and scaling, so the frequency response is specified
under several different operating conditions.
4~84

STAEJILITY
The use of a monolithic transistor quad and low-drift op
amps mininrizes drift, but some drift remains in the scalefactor, reference current, and input offset. Input offset consists of a bias current plus the op amp input voltage offset
divided by the signal source resistance. Also, there is some
slight drift in conformity to the log function and in output
amplifier offset, but this is generally negligible,

Ie =Collector 'Current

THEORY OF OPERATION
The. 4127 is a complete logarithmic amplifier that can be
pin-programmed to accept input currents or voltages of
either polarity. By making use of the internal current
inverter. reference current generator. log ratio element.
and uncommitted op amp. you can generate a variety of
logarithmic functions. including the log ratio of two
signals. the logarithm of an input signal. or the antilog of
an input signal. The unique FET-input current-inverting
element removes the polarity limitations present in most
conventional log amplifiers.
Utilizing the inherent exponential characteristics of
transistor functions. the 4127 calculates accurate log
functions for input currents from I nA to I rnA. or input
voltages from I mV to I OV. Carefully matched
monolithic quad transistors and temperature sensitive
gain elements are used to produce a [og amplifier with
excellent temperature characteristics.
A functional diagram of the 4127 circuit is shown in
Figure l. In addition to the basic log amplifier. the4127
contains a separate internal current source. a current
inverter. and an uncommitted operational amplifier. The
current inverter accurately converts negative input
current to a positive current of equal magnitude.
The 4127 is capable of accurately logging input current
over a 120dB range but to use this full range. good
shielding practice must be followed. A current source
input is. by definition. a high impedance ·source and is
therefore subject to electrostatic pickups.
The input op amps A, and A3 have FET input stages for
low noise and very-low input bias current. The op amp A,
will make the collector current of Q, equal to the signal
input current Is. and the collector current ofQ2 will be the
referenee input current IR •
From the semiconductor junction characteristics. the
base-to-emitter voltage will be

I L =Reverse saturation current
q, m, K =C6nstants
T = Absoiute temperature

If the transistors Q, and Q2 are at the'same temperature
and have matched characteristics then

The output op amp A, provides a voltage gain of
approximately (RT + R,)/ RT• and the value of (mKT)/ q
is about 26mV at room temperature. Since resistor RT
varies with temperature to compensate for gain drift. the
output voltage Eo expressed as a log will be
Eo = -A 10giO IS
IR
where A"" RT + R2 (26 mV) O.l34 ' RT "" 520n
RT
The external resistor R, sets the reference current IR and
resistor R, sets the scale-factor "A". R, and R, must be
trimmed to the desired values. but the approximate
relationships are shown in Typical Performance Curves.
The relationship between the input current Is and the
output voltage Eo in terms of the externally adjusted
parameters IR and "A" is illustrated in Typical
Performance Curves. This relationship is. of course.
restricted to values of Is between I nA and I rnA and
output voltages of less than ±IOV.

-52On Tharmlster
r-~~--~----------------~119

E
A4
+

i

®i'r;th

Irellnpul IR
2

-.

saln
_-' H2
Log Outpul
OOPAIIP
·Input
II Op Amp
Output
9 OpAmp
+tnpul

>Eo..;..____--C
SOmV.,p-p
20mV. pop
2mV. p-pfOC

L

,

,.

ORDER NUMBER:
4203J. 420SJ
'4203K. 420SK
4203S.4205S
WEIGHT:
.
1 gram

, + '.. 1'----~

\. M.s.;

., '

\?"~~ -::----.JG
~H

2SV/~sec

IMHz
40kHz
10kHz

DIM

1p.sec

J

INCHES
MAX
MIN

MAX

.370
.335

8.51
7.75

9.40
a.S1

c

,185

,02'

4.19
0.41
0.2&

4.70
0.53
1.02

E

3mV, rrns

F

.010

6OO~V. rms

G

0

H

J

K

±IOV
±15V
IOMO
10MO
36kO

MIN

.336
.305
,165
.016
.010

3",sec

MILLIMETERS

A
B

L

M
N

,040

.040
.230 BASIC
.oze
.034
.029
,500

,04"

--

.120
.160
36° BASIC
.110
.120

0.25
1.02
5.84 BASIC
0.71
0.86
0.74
12.70
3,06

1.14

-4,,,"

36° BASIC
2.79
3.05

u
:

CONNECTION DIAGRAM
±IOVat ±5mA
10
±ISVDC
±12VDC to ±18VDC
±4.SmA

.l

OOC to+700C

V+

-SsoC to
+12SoC

-65°C to +ISOOC

'N, '

~o

•

• COM

'Xo

ZtN'

OUT

ZO:

'-
«l

.....
."'"

'~

~

+5

1,00k

-5
'-10

<

"'"

::;1

-60

~

.
0

f!l

~

10

,

Z
0

J

lOOk,

:I:

FREQUENCY (Hz)

FIGURE 4. Small Sit!nal Frequency
Response

~

~

100

~

~

~

0

..:

0.1

:I:

l:i«l

:<
:I:
~

10M

1000

->

,..:

1M

,

FIGURE 3. Small Signal Frequency
Response

!

1.0

::;1

I'

-ISO

lOOk
1M
FREQUENCY (Hz)

0.

Q

-120

10k

,

~
10k

Do

!:!

~

Ik

-IS
-20
-25

400

FIGURE 2. Step Response

..:

-90

~

TIME (jlSec)

g

«l

...:I:

200,

0

1M

z

irn

-10

...!:::

0

~

0

-30

~

1"

Q

0

FIGURE 1. Large Signal Freq uency
Response

!;:

-5

«l

FREQUENCY (Hz)

€:

'"'

S

«l'

\

~
~

....

+10

IJ

10

'«l

'to.

0.01
100

Ik

10k

I

lOOk

100

FREQUENCY (Hz)

FIGURE 5. Output Distortion

vs. FrellJlency

Ik

10k

lOOk

FREQUENCY (Hz)

FIGURE 6. AC Feedthrough
vs. Frequency

DISCUSSION OF PERFORMANCE CURVES
LARGE SIGNAL FREQUENCY RESPON~

OUTPUT DISTORTION,

This response curve describes the output voltage capability of
the 4204 asa function of frequency. The measurement is made
with one input at +I 0 or -10 VDC, and with a sine wave applied
at the other input. An output distortion of 0.5% is allowed.

The' output distortion of th~ 4204 is of most interest in
modulator applications. The curve of Figure 5 characterizes
this distortion with one input of the 4204 held at +I 0 or-I 0
VDC. A sine wave is applied to the other input. The sine wave
amplitude is held constant at 20 volts pop while frequency is
varied.

STEP RESPONSE
Step response is measured with one input at +I 0 or -IOVDC and
with a 20 volt pop Square wave applied at the other input.

SMALL SIGNAL FREQUENCY RESPONSE
These curves care the amplitude and phase response of the 4204's
transfer function, when one input is held at + 10 or -10 VDC. A
sine wave signal 1s applied to the other input. Small signal
response requires that the amplitude of the input sine wave be
adjusted so that the outP~t signal does not reach the slew rate
limitation.
'

4-94

ACFEEDTHROUGH
The variation of feed through as a function of frequency is
illustrated by Figure 6. One of the inputs is a zero while a 20
volt pop sine wave is applied at the other input. The output
feedthrough ge'nerally has substantial harmonic content and
is measured in millivolts, peak-to-peak.

OPERATING MODES
DIVIDE MODE

MULTIPLY MODE

SQUARE ROOT MODE

,....

-z

0

Ez
Fy
0

014

lO-

-"

0
0
0
0
08

II

0
0
0
0

Eout

,..

-

0
0
0
0
08

7

Ex

L~14

E

1-

Eout

;..

0
0
0
0

r--

~

,..,

-

0
0
0
0

0
0
0
08

7

Eout

lO,., t-

014

.....

70- t--

Ex
,..

,....
.....

-

ExFy

Eout =

-----w-

IOEz

lr

Eout=~

.J 10 Ez

Eout = -IOV';;; Ex';;; -O.lV
-IOV';;; Ez ';;; +IOV

--=-

OV';;; Ez ';;;+ lOY

ADJUSTMENTS
Although the 4204 will achieve speCified performance in the
multiply mode with no external trimming, optimized perfor- '
mance can be achieved with external adjustments. The proper
connections and the trim procedures are explained below.
The 4204 will operate within specification with any combination of input signals. The b.est performance, however, will be
obtained in the 2nd, 3rd and 4th quadrants. That is if four
quadrant operations are not needed, the performance of the
4204 can be optimized by constraining operation to quadrants 2, 3 and 4 rather than I.

Eout
2

4204

IM!l
1M!}

MULTIPLICATION

1M!}

+15,

-15

+15

Ey~

MULTIPLICATION TRIM PROCEDURE (FIG. 7)

20k
R3

20k
RI

I) Set Ex = 0 and apply a 10 volt peak-peak sine wave
(SO Hz) to Ey: Adjust RI for minimum output.
2) Set Ev = 0 and apply a 10 volt peak-to-peak sine wave
(SO llz) to Ex: Adjust R2for minimum output.
3) Set Ex = Ey = 0: Adjust R3 for Eout = 0.000 V.
4) Set Ex = Ey =+10.000 V ±.I mY: Adjust R4 for
Eout =+10.000 V ±.2 mY.
'

-15

~

~
20k
-15

+15

R2

FIGURE 7. Multiplication Trim Procedure.

4-95

2) Set Ez = 0 volt. Ex'" ~1'1)\t.adjustR~ such thatE() ==
O.OOOV ±2mV.
3) Set Ex = E, =+= -1O:000VD<:":!:2mV. adjust R, such that
Eo='+IO.OOOVDC :!:2mV.
.
4) Set Ex = Ez= minimum value required by application.
adjust R, such that Eo= +IO.OOOVDC ±5mV.
5) Repeat steps.(2) through (4) if necessary.

DIVISION
The 4204 may be used as a tw~.quadrarit divider without
the need for an external operational amplifier. It should.
however. be. PQted. that the maximum output error;is
approximately given by;
divider error'" IOEm
Ex
where tm is the total error specification for the multiply
mode. Obviously. divider error· becomes excessively largl:
for small values of Ex. A 10: I denominator range is
usually the practical limit. I F accurate division is required
over a wide dynamic range of denominator voltage, the
Burr-Brown DIVIOO is recommended (0.25%, max over
a 40: I range).

-IS +IS

-IS

~0'Nv-0
Rio 20k

Rz.20k

DIVISION TRIM PROCEDURE (FIG. 8)
FIGURE 8. Division Trim Procedure.

I) Set all potentiometers at about mid-scale.

SQUARE ROOT

SQUARE ROOT TRIM PROCEDURE (FIG. 9)
I) Set E/ = + 10;000VDC ±2mV. adjust R: such that E" =
-1O.000VDC ±2mV.
2) Set E, = minimum value required by application ("',,)
adjust R, such E" =+= -~ ±2mV.
3) Repeat steps (I) and (2) if necessary.

The pin eonnectionsfor the Square Root mode of
operation are similarto those for division. exee.pt that the
denominator input is connected to the output node.
Errors in the Square Root mode of operation become
troublesome for small values of E,. However. the output
error does not increase so rapidly as in the divide mode.
The actual output for small values of E, is given
appr~ximately, by;
E""I = V 10E/ + lOt"
where tmis the total error specified for Multiply mode.
This equation can be used to determine the feasibility of
using the 4204 as a square rooter for a given application.
For operation over a much wider dynamic range. with
improved accuracy. the Model 4302 multifunction
converter is recommended.

FIGURE 9. Square Root Trim Procedure.

4-96

BURR-BROWN@

4206

IElElI

ANALOG MULTIPLIER-DIVIDER
FEATURES
• HIGH TOTAL ACCURACY
0.25% and 0.5% max. no external trims
0.1% and 0.2% typo with external trims
• lOW TEMPERATURE DRIFT
100ppm/oC Irom DoC to +700C
• SMALL PACKAGE
Dual-in-line saves board space
• LOW COST

,.-----(.2

International Airport Industrial Park· P.O. 80x 11400· Tucson. Arizona 85734· Tel.l6021746·ltl1· Twx: 91(1.952·111t· Cable: 88RCORp· Telex: 66·649t

4-97

DESCRIPTION
The 4206 is a four-quadrant an~logmllltipii¢r offering high accuracy,low ndise,'i1ildrrioderate
bandwidthat low cost. It use~~ldg/antildg techriique and is internally laser-trimmed and
multiply mode accuracies"or9.2'5.%andO,5% max, ate guaranteed with no external components.
By folJowing the external trim procedure' described in Multiplication secti,on, accuracies can be
improved to 0.1 % and 0.2% typo Accuracy specifications are verified at Burr-Brown by an
automatic tester which scans the X-Yplarie. ,Maximum error at any points in the plane is
required to be less than the specified values.
The 4206 also,perforn;Is the divide function in two quadrants and the square root function in
, one quadrant with no external components required. Detailed instructions for these operations
are given on the last page:

THEORY OF OPERATION
,

The 4206's log-antilog multiplication technique is based
upon the logarithmic voltage-current relationship in a semiconductor junction. This action is shown by the simplified "
equation:

,

I

extremely temperature sensitive. The 4206, however, has excellent temperature characteristics because the log and antilog circuitry have equal and opposite temperature drifts
which cancel to a first order approximation. The log and
antilog circuits will compensate each other to the extent that
the various logging transistors are matched to each other. In
the' 4206 these transistors are 'placed adjacently on a monolithic chip to obtain the best possible matching and so the
be'st possible performance.

KT

Vbe = (-)(1n Ic - In IJ
q
,
where Vbe is the transistor's emitter-base voltage, Ic is the
transistor collector current, Is is the collector saturation
current, K is Bolzmann's constant, q is the charge of one'
electron and T is the absolute temperature in degrees Kelvin.
As can be seen from the equatiori, the logarithmic function is

4·)---------------....,
,..----------(12

+ISV

11}---------------------~

4-98

SPECIFICATIONS
Typical performance at +2S o C with rated power supplies unless otherwise noted.
Per cent specifications refer to % of full scale (1 OV).

ELECTRICAL
MODel

4206J

OUTPUT FUNCTION
TOTAL ERROR( Multiply Mode)"
Internal trim, max t
External trim, typ
vs. Temperature
vs. Supply

INDIVIDUAL ERRORS (Multiply Mode)
Output Offset X=Y=O
Scale Factor Error
Non-Linearity
X = 20 V, p.p Y = -IOVDC}
Y = 20 V, p.p X=-IOVDC
X = 20 V, pop
Y = 20 V, pop
Feedlhrough (ill 50 Hz
X = 20 V, pop Y = 0
Y = 20 V, pop X = 0

~ ~ ::~ ~g~}

0.5% max
0.2%
o.OI%/oC
0.02%1%
15 mV
0.2%

1% Vector Error (0.57° phase shift)
,Power Response

f;o~ull

I V/iJ.sec
250 kHz
33 kHz
2.5 kHz
20 kHz
300 iJ.V rms

Inpul Voltage
:!c10 V
:!cSupply
2SkH/2SkH/I00kH

OUTPUT CHARACTERISTICS
Rated Outpuf
Voltage, min

Current, min
Output Impedance

:!c10 V

is

IH

lOuiescent Current

:!cIS VDC

·

·
·

·
·

+IS rnA, -8.5 rnA
O"C to +7O"C
-25"Cto +85"C
-40"Cto +85"C

·

* Same 8S for 4206J

* * Total

t

marked on package.

DIM

0

G

INCHES
MAX
MIN

MILLIMETERS

MIN

MAX

.790

.B10

20.07

20.57

.490

.510

.190
.018

.260
.021

'2.45
4.83
0.46

12.95
6.60
0.53

.100 BASIC
.115
.080

2.54 BAS1C
2.03

2.92

.130

3.30

7.62

.300

.300 BAStC

7.62 BASIC

.080

2.03

."5

2.92

PIN SPACING: 2.5mm (0.1") ROW
SPACING: 7.6mm (0.300") WEIGHT:
3.4 grams (0.12 oz.) CONNECTOR:
l4-pin DIP 0145MC Price: $3.75 ea.
Pin material and plating composition conform to Method 208 (solderability) of MilStd-202.

±.14 to ±16 V

TEMPERATURE RANGE
Specification
Operating
Storage

Pin numbers shown
for reference only.
N umbers are not

rnA

POWER SUPPL V REQUIREMENTS
Rated Supply
Operating Range

5 mV
0.1%

5 mV pop
S· mV pop

INPUT CHARACTERISTICS
Maximum for Rated Specifications X,Y,Z
Maximum Safe Level X,Y,Z
Input Impedance X/Y IZ

0.1%

10 mV pop
10 mV pop

OUTPUT NOISE X = V = O.OV
DC to 10 kHZ

0.25% max

·,

AC PERFORMANCE
Slew Rate
-3 dB Small Signal Bandwidth
I % Am plitude Error

.
..

0.05%

0.005%

~OTE: Leads in
true position within
.01O"(.25mm) R at
MMC at seating

4206K

EXEy
10

error is a tested maximum and does not represent a sum of the maximum
individual errors as the maximum individual errors do not occur at the same X,
Y operating point.
With output loading of 10kn or less:

PIN CONNECTIONS
Ez
Output
-Vs
4 Feedthrough Adj.
5 Make No Connection
6 Make No Conne~tion
Ex
8 Internal Reference
9 Make No Connection
10 Ground
II Feedthrough Adj.
12 Offset Adj.
13 Ey
14 +Vs

,,~:t. ·~~f;.· 'f.'i:·~:'~>~;;ti:'··_: ,~,::,,:<,

I

,,;

.;:....

TYPICAL'PERFORMANOE CURVES
Typical Performance @25 0 C and
'.

Q:

~
"'5
~

D.
CIl

;.

....
0

20

C!l
Z

'i.

' 10

'"

;>
0..

;>

0

0
Ik

10k

+5

>
Ol

0

Q
;>

;.

;>

-5

'";>

-10

....

;.

;.

:::;

",.

::E

..:

1M

-30

;.

~

..:'"

-90

'"

-.120

::

10

0

'"
Q

,

,

U

Z

~

0

:;;

'>
!

1.0

::
0::

::
;.

lOOk

1M

*

FREQUENCY (Hz)

FIGURE 4. Small Signal Frequency
Response

t.

10

~

Ii

:
.'

Q

..:

10k

,

C!l

0

Ol
Ol

::
Ik

/

100

;>

0.1

0::

-ISO

10M

1000

D.

J

I

FIGURE 3. Small Signal Frequency
Response

Q:

Q

~

lOOk
1M
FREQUENCY (Hz)

10k

FI.GURE 2. Step Response

;.
0::

-60

,

~

-20

TIME (/'Sec)

0

Ol

"

-IS

400

200

0

z

'"

~

-10

-25

lOOk

FIGURE 1. Large Signal Frequency
Response

i'"

r"1\.

-5

0

FREQUENCY !Hz)

;.

0

Ol

Ol

\ r--

;.
;.

I
+10

$'
S

....

1\

~
'.

± 15 VDC

0.01
100

Ik

10k

lOOk

'"

I

FREQUENCY (Hz)

FIGURE 5. Output Distortion
n. Frequency

100

Ik

10k

lOOk

FREQUENCY (Hz)

FIGURE 6. AC Feedthrough
lIS. Frequency

DISC.USSION OF PERFORMANCE CURVES
LARGE SIGNAL FREQUENCY RESPONSE

OUTPUT DISTORTION

This respon~e curve de~cribes the output voltage capability of
the 4206 as a function of frequency. The measurement is made
with one input at + I Oor -10 VDC. and with a sine wave applied
at the other input. An output distortion of 0.5% is alloYfed ..

STEP RESPONSE
Step response ismeasiJred with one input at +I 0 or -I OVDC and
.
with a 20 volt p.p square wave applied at the other input.

'. The output- distortion of the 4206 is of most interest in
modul~tor applications. The curve of Figure 5 characterizes'
this distortion with one input of the 4206 held at + 1Oor .-1 0
VDC. A sine wave is applied to the other input. The sine'wave
amplitude is held consta~t at 20 volts p:p while frequency i~
varied.

SMALL SIGNAL FREQUENCY RESPONSE
These curves are the amplitude:and phase respbnse of the 4206's
tr.ansfer function, when one input is held at +1 0 or -10 VDC. A
sine wave signal is applied to the other input. Small signal
. response requires that the amplitUde of the input sine wave be
adjusted so that the output signal does not reach the slew rate
limitation..
.

AC FEEDTHROUGH
The variation of feed through as a function of frequency is
illustrated by Figure 6. One of the inputs is a zero,while a 20
volt p.p sine wave is applied at the other input. The output
feedthrough generally has substantial harmonic content and
is measured in millivolts, peak.to·peak.

4-100,

OPERATING MODES
DIVIDE MODE

MULTIPLY MOOE

SQUARE ROOT MODE

"..,

Ez
Ey
,...

014
0
0
0
0
08

lO-

II

fout

014

,....

~

0
0
0
0

0

"

0
0
0
08

7~

Ex

~

fo~t
,....

I"

014

o
o
o
o

0
0
0
0

08

7~

Ex
,....

JOEz

fout= ~-IOV ~ Ex ~ -O.lV
-IOV ~ Ez ~ +IOV

OV~Ez~+

IOV

.ADJUSTMENTS
Although the 4206 will achieve specified performance in the
multiply mode with no external trimming, optimized performance can be achieved with external adjustments. The proper
connections and the trim procedures are explained below.
The 4206 will operate within specification with any combination of input signals. The best performance,however, will be
obtained in the 2nd, 3rd and 4th quadrants. That is if four
quadrant operations are not needed, the performance of the
4206 can be optimized by constraining operation to quadrants 2, 3 and 4 rather than I.

Eout

4206

20k

IM!1
IM!1

MULTIPLICATION
+15

-IS

Ey~

MULTIPLICATION TRIM PROCEDURE (FIG_ 7)

20k
RI

I) Set Ex = 0 and apply a 10 volt peak-peak sine wave
(SO Hz) to Ey: Adjust RI for minimum output.
2) Set Ev = 0 and apply a 10 volt peak-to-peak sine wave
(SO Kz) to Ex: Adjust R2for minimum output.
3) Set Ex = Ey = 0: Adjust R3 for Eout = 0.000 V.
4) Set Ex = Ey = +10.000 V ±.I mY: Adjust R4 for
Eout = +10.000 V ±.2 mY.

~
20k
-IS

+15

R2

FIGURE 7 Multiplication Trim Procedure

4-101

2) Set Ez = 0 volt, Ex ~'":W:'¥, \lidjust R2S\;1ch that Eo =
0.000 V±2 mV. ", . ' . : "
. .•...
.;, .

DIVISION
The 4206 may be'lised as a twooquadtant divider without
the need for an external operational ~plifier. It should,
however, be noted that' the maximum output error 'is
approximately given by

3) Set Ex = Ez = -lO.OOOVDC ±2 mY, adjust R3 such that
. Eo= +to.OOOVDC±2mV.
4) Set Ex' = Ez '" minimum value required by application,
. '" adjust Rl such that Eo = +IO.OOOVDC ±5 mV.
5) Repeat steps (2) through (4) if necessary.

divider error '" I Oem
Ex
where em :~ the total error specification for the multiply
. ,,' mode. Obviously, divider error becomes, excessively large for
small values of Ex. A 10: I denominator range is usually the
practical limit. If accurate division is required QVera wide'
dynamic range of denominator voI'tage, the Burr-Brown
Model 4291 is recommended (0.5%,' max., over a 100: I
range).

DIVISION TRIM PROCEDURE (FIG. 8)
FIGURE 8 Division Trim Procedure

I) Set all potentiometers near mid-scale.

SQUARE ROOT TRIM PROCEDURE (FIG, 9)
I) Set Ez '; +lO.OOOVDC ±2 mY, adjust R2 such that Eo =
+ 1O.000VDC±2 mY.
2) Set Ez '" minimum value required by application (Ezm)
adjust RI such that Eo = - ",110 Ezm ±2 mY.
3) Repeat steps (I) and (2) necessary.

SQUARE ROOT
The pin connections for the Square Root mode of operation
are similar to those for diviSion, except that the denominator
iIlPut is connected to the output node. Errors in the Square
Root mode of operation bec01:ne troublesome for small
values of Ez . However,the output error does·not increase so
rapidly as in the divide mode. The actual output for small
values ofEz is given approximately by
.----Eout '" -V lOEz + lOem
where em is the total error specified for Multiply mode. This
equation can 'be used to determine the feasibility of using the
4206 as a square rooter for a given application. For operation
.over a much wider dynamic range, with improved accuracy,
.the Model 4302 multifunction converter is recommended.

it:

FIGURE 9Square Roo,t Trim Procedure

4-102

BURR-BROWN®

4213

IElElI·

MUL TIPLIER-DIVIDER
FEATURES

APPLICATIONS

• LOW COST

• MULTIPLICATION

• DIFFERENTIAL INPUT

• DIVISION

• ACCURACY 100% TESTED AND GUARANTEED

• SQUARING

• LOW NDISE
120ilV. rms. 10Hz to 10kHz

• SQUARE ROOT

• SELF-CONTAINED
No additional amplifiers

• POWER COMPUTATION

• SMALL SIZE
Hermetic TO-IOO package

• ALGEBRAIC COMPUTATION

• WIDE TEMPERATURE OPERATION

• TRUE RMS-TO-OC CONVERSION

• LINEARIZATION
• ANALOG SIGNAL PROCESSING

DESCRIPTION
The 4213 multiplier-d i\ider is a 10\\ cost precision
de\ice designed for general purpose application. In
addition to four-quadrant multiplication. it also
performs ;\llalog squarc root and division without
the bother of externa I amplifiers. The 421 J is lasertrimmed to guarantee its ratcd accuracy with no

e.'ternal components. The internal zener regulated
references make the 4213 much Ie" sensiti\e to
supply variation than earlier Ie multipliers. Hermetic
TO-IOO package. wide operating temperature range.
low output noise. and low cost arc some of the
desirahle features of this \wsatile device.

4213 FUNCTIONAL DIAGRAM

Multiplier Core
OUT

Atlenuator

International Airport Industrial Park· P.O. 80x 11400 • Tucson. Arizona 85734 • Tel. (6021 746·1111 • Twx: 91IJ.952·11I1 • Cable: 88RCORP - Telex: 66·6491

4-lO3

SPEciFICATIONS
ELECTRiCAL

SP~:ifications"at

TA'; +25°C and+Vcc=
15VOC un'less otherwise noted
-

I

MODEL
CONDITIONS

PARAMETER

4213AM
MIN

-25°C ~ TA :s;;; +~oC
-55°C:S;; TA ~ +125°C

TA = +2Soe
-2Soe .;; TA .;; +ssoe
-ssoe.;; TA';; +12Soe

±1O
to.?

-±0.25

vs Supply

-25°C :s;; TA ::;;; +85°C
-55°C

~

X = 20V. POP; Y = tl0VDe
Y = 20V. pop; II = tl0VDe
1= SOHz
X = 20V. pop; Y =
Y = 20V. pop; X =
-2Soe .;; l'A .;; +85°e
-S5°e.;; TA';; +12Soe

°°

±a.s

±SO

±7·
±0.3

±25
to.?

--

I

x,>4213SM
TYP

MAX

UNITS

--

-±0.02S

±a.s

% FSR
% FSR/oe
% FSR/oe
% FSR/%

t2S

--

mV/OC

±O.7

mV/oC
mV/%

to.OS
to.OS
to.Ol

% FSR
% FSR

--

--

--

X, > X2

..1Q:..Z,-Z2 " +'y

X =-10V
-10V';; Z ';;+10V
X=-1V
-w.;; z';; +w
-10V';; X,;; -0.2V
-10V .;; Z';; +10V'

·mV

±?
to.3

--

--

-±O.OS

% FSR
% FSR/oe
% FSR/oe
% FSR/%

X, - X2'

to.COS.

--

--

0.1

mY. pop
mY. pop
mY. p-p/oe
mY. p-p/oe
mY. p-p/%

2

±0.75

to.3S

to.35

% FSR

t2.0

±1.0

tl.0

% FSR

:j:S.O

±1.0

.:!:1.0

% FSR

I

±0.3

to.3

% FSR

+~
tl

to.S

±0.5

% FSR

SQUARER PERFORMANCE
Transfer Function
Total Error

I
I ,MIN

0.1S

DIVIDER PERFORMANCE
Transfer Function

external adjustments,

MAX

±2.0

30
6
0.1

.vs Supply

Total Error, with

I

--

--

TA '!f; +125°C

Io VS Supply(
Nonlinearity

Temperature

TYP

--

±a.12
to.OOS

TA = +25°e .

vs Temperature

V$

--

--

±O.OS

Scale Factor Error
Initial
vs Temperature

Y Input

±1.0
±0:02

·±o.ooa

vs Supply
Individual Errors
Output Offset
Initial
vs Temperature
vs Temperatl!re

MIN

IX, - X2~~Yl - Y2 1 + Z2
-10V';; X. Y';; 10V
TA = +2Soe

Total Error
Initial
vs Temperature
vs Temperature

Feedthrough
X Input
Y Input
V5 Temperature

MAX

.

MULTIPLIER·PERFORMAN :E
Transfer Function

X Input

4213BM

TYP

,X, 10X2 .2+ Z2

I

-10V';; X .;; +10V

±0.6

SQUARE-ROOTER PERFORMANj::E

Z, < Z2
lV';; Z';; 10V

Transfer Function
Total Error
AC PERFORMANCE
Small·Signal Bandwidth
1% Amplitude Error
1% 10.57°. Vector Error
Full Power Bandwidth
Slew Rate
Settling Time
Overload Recovery

I

::t1%,

~Vo =:

kH~

550
70
5
320
20
2
0.2

::!::3dB

Small Signal
Small Signal
IVd = 10V. RL = 2kll
IVd = 10V. RL = 2kll
t =:

I

20V

50% Output Overload

kHz
kHz
kHz
V/p.sec
p'sec
p'sec

INPUT CHARACTERISTICS

Input Voltage Range
Rated Operation
AbSolute Maximum
Input Resistance
Input Bias Current

V
V
Mil
"A

±10
±Vcc

1O
1.4

X. Y. ZI1'
X. Y. Z

OUTPUT CHARACTERISTICS

Rated Output
Voltage

10

=:

±SmA

Current
Output Resistance

Vo = ±10V

OUTPUT NOISE VOLTAGE

X-Y-O

±10

fo 1Hz
fo = 10kHz
111 Corner Frequency

fs = 10Hz to 10kHz
Is = 10Hz to lOMHz
POWER SUPPLY REQUIREMENTS
Rated Voltage
Operating Range
Derated Performance
Quiescent Current

;

tS

f= DC

V
mA

'1.5

II

40
1.0
1060
125
3

"VI, Hz
"VI,1}il
Hz
·p.V, rms
mY, rms

±15

±S.S

±20
±S.S

4-104

VDe
VDe
mA

ELECTRICAL (CO NT)

I

MOOEL
PARAMETER
TEMPERATURE RANGE !Ambient!
Specification
Operating Range
Storage

I

CONDITIONS

I

Derated Performance

I

I

4213AM
MIN

I

TYP

1

MAX

J

4213BM
MIN

j

TYP

1

I
MAXJ

I

4213SM
MIN

J

TYP

I

MAX

I

I I I I I I I I I I
+85
+125
+150

-25
~~

-:5

.1:25

UNITS

°C
°C
°C

NOTES:
1. Z2 input resistance is 10MU. typical. with Pin 9 open. If Pin 9 is grounded ~r used for optional offset adjustment, the Z2 input resistance may be as low as 25kU.

·Same as 4213AM specification.

CONNECTION DIAGRAM

MECHANICAL

L-F:

NOTE:

·Optional component

. .'".."'. .

-15VDC

PIN CONFIGURATION

Leads rn true position within .010"

~~

Y2

z~ I
-.1100--0

ORDER NUMBER.
4213AM
4213BM
4213SM
WEIGHT:
1 gram

NOTES:
1. Vas adjustment optional not normally recommended. Vas
pin may be left open or grounded.
2. Arr unused input pins should be grounded.
3. Pin 5 IS connected to the case.

SIMPLIFIED SCHEMATIC
INCHES
DIM

MIN

MAX

MILLIMETERS
MIN

MAX

A

.335

.370

8.51

B

.305

. 335

7.75

8.51 .

C

.165

.185

4.19

4.70

9.40

0

.016

.021

0.41

0.53

E

.010

.040

0.25

1.02

F

.010

.040

0.25

1.02

G

.230 BAStC

5.84 BASIC

H

.028

.. 034

0.71"

0.86

J

.029

.045

0.74

1.14

K

.500

.. -

L

.120

.160

M

36° BASIC

N

.110

I .120

12.70

--

3.05

4.06

36° BASI.C
2.79

1 3 .05

4-lO5

TYPICAL PE~FORMANCE CURVES
TOTAL ERROR VS
AMBIENT TEMPERATURE

cr

,~

10

NONLINEARITY VS FREQUENCY
100

'0
~
cr

g

:;

,3'"
S

~

0.2

~

O. I

.~

m 0.1

,SO

"

~ 00 I

'0

'"
'c

'"

'"

X-F~edth~ou9~

50

e'"
~

20

J::

10

i5

lk
10k lOOk
Frequency I Hz,

10

1M

100

~

:;

'"

-5

-10

;3'" -15

I

I

~

Y~
\

~

'" -5 -

'S

1M

. CL

-10

-20
lOOk

VCRL~ 2kll

o

1~

10M

70

I

'0

SO

X ~ 12V. p-p
Y ~ ±10VDC

!\

~

1\
\

I

I
~O

40

.s'"

"

,.~

....,.. ..
/, ..'
~

,.

6

4~

50

'/ "'- rlI..

'2

..'I

~
2

4

6

I

8 10 12 14 16 18 20

Power Sl:Ipply Vo1tag~ I ±Vcc

SUPPLY CURRENT VS
AMBIENT TEMPERATURE
16

Y 12V. p-p
,\X~±10VDC ~

14

~ 12
C 10

SmA Load

--: po.-

-

IL

1!
:; 8
()

\

30

14

10
:; 8

150 P

20

Positive Common-mode
Differential
Negative common-mo~,

~ 12

\

c:

~

>

l"'o..

I
I. I

60
III

r=-F-"-'

:\

OUTPUT VOLTAGE VS
OUTPUT CURRENT

COMMON-MODE REJECTION
VS FREQUENCY

I

r=F
16

Time ljJ.sec

Frequency' Hz

80

I

10k lOOk 1M 10M

INPUT VOLTAGE FOR
LINEAR RESPONSE

18

~

>

lk

Frequency I Hz'

LARGE SIGNAL RESPONSE
10

:e0.~

"j

Y_Fe~dthroIUg!. /

20

0

~

'/

J::

""

100

Ambient T~mperature °C·

'0

1/

LL

10

OUTPUT AMPLITUDE VS
FREQUENCY

III

~ fV. ~-p ~

I I

g" 100
'0

0.00 I

-

-75-50 25 0 25 50 75100125

Inprt Si 9 }al

.200

>

0.05

~.

500

!:

./

'/ /
V 'v

~

""

'"0..
:>

/

/

~

V

0.5

10

~
'0

v

w

FEEDTHROUGH VS FREQUENCY
1000

1~plut Si9'~al ~ 2JV. p-p

,.,

Quiescent

0.

§' 4

\

(f)

20
10

100

lk

o

-1oo-7S·S0 -25 0 25 SO 7S 100 12S ISO

10k lOOk 1M 10M

Ambient Temperature 1°C

Frequency Hz

ABSOLUTE MAXIMUM RATINGS
Supply
Internal Power Dissipatio{l(1)
Differential Input Vc;>ltage(2)
Input Voltage Rangel'''
Storage Temperature Range
, Operating Tempera~ure Range

±20V,DC
500mW

±40VDC

Lead Temperature Isoldering, 10 seconds I
Output Short-circuit Duration(3)
Junction Temperature

NOTES:
1. Package must be derated based on: OJC ::: 55°C/Wand (JjA

±20VDC
-65°C to +1S0°C
-5SoC to +12SoC
+3000C
Continuous

+1S0°C

= 1'65°CIW.
2. For supply voltages less than ±20VDC the absolute maximum input voltage is equal to the supplY'voltage.
3, Short-circuit may be to ground only. Rating applies to +85°C ambient.

4-106

DEFINITIONS
TOTAL ERROR (Accuracy)
Total error is the actual departure of the multiplier
output voltage from the ideal product of its input
voltages. It incI'udes the sum of the effects of input' and
output DC offsets. gain error and nonlinearity.
OUTPUT OFFSET
Output offset is the output voltage when both inputs V,
and Y yare zero volts.
SCALE FACTOR ERROR
Scale factor error is the difference between the actual
scale factor and the ideal scale f:lctOr.
NONLINEARITY
:\onlinearit)' is the maximum deviation from a best
straightline (curve fitting on input-output graph) expressed as a percent of peak-to-peak full scale output.

FEEDTHROUGH
Feedthrough is the signal at the output for any value of
V, or V, within the rated range. when the other input is
zero.
SMALL SIGNAL BANDWIDTH
Small signal bandwidth is the frequency at which the
output is down 3d B from its low frequency value for a
nominal output amplitude of 10(:; of full scale.
1% AMPLITUDE ERROR
The I I; amplitude error is the frequency the output
amplitude is,in error hy II;. measured with an output
amplitude of !O"; of full scale.
1% VECTOR ERROR
The I "; vector error is the frequency at which a phase
error of 0.0 I radians (0.57") occurs. This is the most
sensitive measure of dynamic error of a multiplier.

APPLICATIONS INFORMATION
MULTIPLICATION
Figure I shows the basic connection for four-quadrant
multiplication.
The 4213 meets all of its specifications without trimming.
Accuracy can, however, be improved over a limited
range by nulling the output offset voltage using the
lOOkQ optional balance potentiometer shown in Figure l.
i\C feedthrough may be reduced to a minimum by
applying an external voltage to the X or Y input as shown
in Figure 2.

terminal. as well as the X and Y input terminals. should
be grounded. All inputs should be referenced to power
supply common.
Figure 3 shows how to achieve a scale factor larger than
the nominal 0.1. I n this case. the scale factor is unity
which makes the transfer function
V" = KV,V, = K(X, - X,)(Y, - V,)
K = [I + (R, R,)j 10
0.1:;:;; K:;:;; I

Z,. the optional summing input. may be used to sum a
voltage into the output of the 4213. If not used. this

10kn

4213

·15VDC

to

+15VDC

FIGURE 3. Connection For Unity Scale Factor.

·t5VDC

+t5VOC

This circuit has the disadvantage of increasing the output
offset voltage by a factor of 10 which may require the usc
of the optional balance control for some applications. In
addition, this. connection reduces the' small signal
bandwidth to about 50kHz.
.

'Optlonal nu11lng
potentiometer.

FIGURE I. Multiplier Connection.

f----.,..,.----1........
+15VOC

50kll

470fm

lkl~

DIVISION
Figure 4 shows the basic connection for two-quadrant
divisio.n. This configuration is a multiplier-inverted analog divider. i.e .. a multiplier connected in the feedback
loop of an operational amplifier. In the case of the 4213
this operational amplifier is the output amplifier of the
multiplier itself.

To the
appropriate
Input Terminal

·15VDC

FIGURE 2. Optional Trimming Configuration.

4-107

+15VOC

'.:,\I~·
·t5VDC

"Optlonal
Nulling
L-=~:,-_ _~==-~~l!-...J ComponenlS

+15VDC

'.::l~

FIGURE 4. Divider Connection.
The divider error with a multiplier-iriverted analog
di\ ider is approximately
,
tdllldc'l = 10 f:lllllItII'JI\'1 (X 1,- X~).

·15VDC
.15VDC +15VOC
'Optlonal NullingComponenlS

It is obvious from this error equation that divider error

becomes excessively large for small values of Xl - X~. A
10-to-1 denominator range is usually the practical limit.
If more accurate division is required over a wide range of
denominator voltages. an externally generated .voltage
may be applied to the unused X-input (see Optional Trim
Configuration). To trim. apply a ramp of + 100m V to
+ I V at 100Hz to both Xl and Zl if X~ is used for offset
adjustment. otherwise reverse the signal polarity. and
adjust the trim voltage to minimize the variation in the
output. An alternative to this procedure would be to use
the Burr-Brown DIY 100. a preCision log-antilog divider.

Z2
+O.2V.; \ZI·ZZI.;:+IOV

FIGURE 6. Square Root Connection.
This' will improve the square root mode accuracy to
about that of the multiply mode.

BRIDGE LINEARIZATION
4k!!

SQUARING

VII" ±10V. FS

Vx
±IOV. FS
'Optlonal Nulling
Component
·15VDC

Optional
Summing
Input.
:tIOV. FS

FIGURE 5. Squarer Connection.

SQUARE ROOT
Figure 6 shows the connection for taking the square root
of the voltage V,. The diode pre\'ents a latching condition
which could occur if the input momentai"ily changed
polarity.This latching coildition is not a design flaY;' in
the 4213. but (lcCUr, when a multiplier is connected in the
feedback loop of an operational amplifier to perform
square root functions.

FIGURE 7. Bridge Linearization.
The use of the 4213 and ,the instrumentation amplifier to
linearize the output from a bridge circuit makes the
output Y" independent of the bridge supply \'(lltage.

TRUE

RMS~TO-DC

CONVERSION
Matched to 0.025%

ZOkn

The\oad resistance Rl must bcintherangeoflOkn~ Rl
:;;;; I M!l. This resistance must be in the circuit as it
provides the curren! necessary to operate the diode.

RI

Mode

Switch

The output offset should be nulled for optiinum pe,rf~finance by allowing the inputto be its small~st expected
value and adjusting Rl for the proper output voltage.
FIGURE 8. True RMS-to-DC Cpnversion.

4-108

RZ

The RMS-to-DC conversion circuit of Figure 8 gives
greater accuracy and bandwidth but with less dynamic
range than most rms-to-DC converters,

WIRING PRECAUTIONS
In ordcr to prevent frequency instability due to lead
inductance of the powcr supply lines. each power supply
should bc bypassed, This should be done by connecting a
101l1-' tantalum capacitor in parallel with a IOOOpF
ceramic capacitor from the +Vn and -V,(' pins of the
421 J to the power supply common. The connection of
these capacitors should be as close to the 4213 as
practical.

PERCENTAGE COMPUTATION
IV2- VII
'Vo = -YI - 100
1% per volt
o-~_-IXI

+O,2Y"; YI ,; +IOY

x2
YI

4213

CAPACITIVE LOADS

Y2
Ukll

Stable opcration is maintained with capacitive loads to
IOOOpF in all modes typically. cxccpt the square root
mode for which SOpF is a safe upper limit. Higher
capl~citi\'e loads. can be driwn if a lOon resistor is
connccted in series with the 421 J"s output.

Y2
Ikll

FIGURE 9, Percentage Computation,
The circuit of Figure 9 has a sensitivity of I V I % and is
capable of measuring loci de\'iation', Wider deviation
can be mcasured by decreasing the ratio of R, R"

SINE FUNCTION GENERATOR

MORE CIRCUITS
. The theory and procedures for,developing virtually any
function generator or lincari/ation circuit can be found in
the Burr-Brown McGraw Hill book "I-T:\("TIO:\ C1R("l'ITS - Design and Applications."'

71.548kll

Vo = 10 sin 9V,
5.715k!!

10k!!

I-lOY'; VI'; +IOV, and IV = gol

FIGURE 10, Sine Function Generator,
The circuit in Figure 10 uses implicit feedback to
implement the following sine function approximation:
V.. =(1.5715V,-(J.004317\',') (I +0,001391(\',.')
= 10 sin (9\' d.

SINGLE-PHASE POWER MEASUREMENT
eill/ = .j2 Elrms sin wi
ILIt( = v'2\rms sin Iwl + 01

R4

Real Power
~ Icry/10llElrmslLrms cosol

FIGURE II. Single-Phase Instantaneous and Real
Power Measurement.

4-109

51

BURR-BRoWN®

4214

IE3IElII

MULTIPliER - DIVIDER

APPLICATIONS'

FEATURES
-DIFFERENTIAL INPUTS

- MULTIPLICATION

- LASER-TRIMMED

- DIVISION

. - GUARANTEED ACCURACY

- SQUARING
- SQUARE ROOTING
• ADAPTIVE CONTROl

0.5% and 1Ufo
- SELF-CONTAINED

No additional parts required

- ALGEBRAIC COMPUTATION

-lOW NOISE
120JJV rms,10Hz - 111kHz

- POWER COMPUTATION

- DIP PACKAGES

DESCRIPT10N
.The 4214 family of mUltipliers are low cost integrated
circuit multiplier/dividers designed for general
purpose usage. In addition to four quadrant
multiplication, they also perform division and square
rooting of analog signals. They do not require use of
additional amplifiers to perform these functions. The
4214 is laser-trimmed prior to finai packaging and is
guaranteed to its rated accuracy with no external
components - a distinct advantage from standpoints
of cost and reliability.
4214 contains its own zener regulated references and,

as a result is much less sensitive to supply voltage
variation than were earlier Ie multipliers. The
multipliers' output noise is only 120l'V rniS ina 10Hz
to 10kHz bandwidth.
The unit is available in two 14 pin DIP packages. The
plastic version ("P" package) is offered for minimum
cost as is speCified ovet the -2S'e to +8S'e range. The
.hermetic metal package ("MOO package option)
provides operation over the full -ss'e to +12S'e
temperature range.

hIIInUIIIIIII Al/plrlllldullrllll'lrll • P.D. ItIlI 11400· Tucun. ArlZ1II11 85734 • TIl. (602) 74&.1111 • TWI; 910-952·1 in. Cable: BBRCORP • rlllx; 811-8491

4-110

ELECTRICAL.SPECIFICATIONS
Typical performance at +25OC with rated power supplies unless otherwise nOled.

MODEL

(X,-X,)(y,-Y,)
10

OUTPUT FUNCTION
TOTAL ERROR(I)

MECHANICAL

4214BP/SM

4214AP/RM

4214AP.42i4BP
Weight: 2.9 grams (0.10 oz.)

+z,

S.lmm

Without Trimmin.

1% max

Error .. Temperature (-2S"C to +85"C). (AP and BP)
(-5S"C to +125"C). (RM and SM)

0.OO8%/"C typ.• 0.02%/"C max
0.025%i"C typ .• 0.05%, "C max

0.5% max

i

INDIVIDUAL ERRORS
OutputOffsel
VI

VI

Temperature
Supply

?mV Iyp

25mV max

0.7mVI"C typ

O.3mV;"C typ

2mVtC max

O.7mV;oC max

VI Supply
Nonlinearity
X(X = lOV p.P. Y = ±IOVDC)
Y(Y = lOV p.P. X = ±IOVDC)
Feedthroulh at SO Hz
X=lOVp.P.Y=0
Y=lOV p.p.X =0

Pin I

4214RM.4214SM
Weight: 3.9 grams (0. I3 oz.)

±O.08%
±O.OI%

·4.Smm
_12.6mm-j (0.19")

.. Supply

1

Small Siplal ±3dB Flatn...
Small Siplal ;!:I% Flatness
Small Si...1 ±I% Vettor Error (0.57" Phase Shift)
FuU Power Bandwidth

S","R ...
Sellli. . Time to 1% (20V step)

OUTPUT NOISE IX

(0.50")

0.46mm_lI__

AC PERFORMANCE

10 Hz to 10 kHz
10 Hz to 10MHz

,I-L-

n-r

30mV POp
6mV pop
O.lmV p-pt"C
0.15mV p-p,%

Temperature

(iTo")

1-.£

~os~~~"'n-

0.25mVI%
. 0.12%
O.OO8%!"C
0.05%1%

Scak Factor Error
VI Temperature

VI

IOmV lyp

SOmV mu:

(0.50,,)

~T

0.05%1%

Error VI Supply

12.7mm

610 kHz
90 kHz
7.S kHz
330 kHz
23V;"s

1.7,,5

=Y =OJ

120"V rms
700"V rms

INPUT CHARACTERISTICS
Input Volta.. Ran..
Rated Operation, min.

±IOV
tV.
10M!!
1.4"A

Absolute m~x

Input Impedance. X. Y. Zm
Input Bias Current, X. Y. Z

OUTPUT CHARACTERISTICS

(0.018")

7.6mm
(0.30,,)
Pin 14

0000000

Connector: Ol45MC (l4-pin DIP)
Pin material and plating composition
conform to method 2003 (solderability)
of Mil-Std-883 (except paragraph 3.2)

CONNECTION
DIAGRAM

±IOV at ±SmA min

Rated Output
Output Impedance

u!!

POWER SUPPLY REQUIREMENTS
±15V
±8.SVDC to ±20VDC
±5.5mA

Rated Volta..
Operating Range'
Quiescent Current

TEMPERATURE RANGE
Rated Performance (specification)

Operation
Sto,...

APand BP
RMandSM
AP·and BP
RMandSM

-2S'C to +8S'C
-S5'C to +12S'C
-55'C to + 12S'C
-4O'C to +8S'C
-6S'C to +ISO'C

I. T olal error is the maximum allowed value of the sum of the individual errors.

No inl~rnal
connections on
Pins 4, S, 6 and 8.

2. Z2 input impedance is 10 MO typ with Pin II open circuit. If Pin II is grounded or used
for optional offset adjustment the Z2 input impedance may become as low as 25kU.
NOTE: Vos adjustment optiunal. nol nurmall~ recommended.,'
Pin II may be left open or grounded.

4-111

70 II'

I

II

60

S.

~
1>:'

::..
u

I

·x =

l'\.

I

12V pop.
SO ~=.!,!.Q-YDC
4Q

y", 12V pop.
\X=.±IOVDC-

\

~

j
-51--+~

\

20

-10'~~~

10 100 Ik 10k 'OOk ,M
Common·mode 'input ·Freq~ency (Hz)
FIGURE 1. Common·mode Rejection vs.
FrequeQcy.

~
:'.
c
~

0:

~

:;
Q.
.5

Frequency (Hz)
FIGURE 3. Smal1.B;g~al Frequency

.S
'2
o

o. I

/

"7V

0.0 I

Q.

>",/

"

500

.

~ 200

!l" 100
"0

..e

50

.;;

10

>
.c

'v

/

Z

_1000

Inp~t Sig~al=20~~-P

10
I

4

-20'-~~--'"""'l~--_.~.

5.0

Response.

i!'

.~

t -10t---+----+-...,.r"~_t
:;
8 -151---+___,-----+--......-'--\-:1

Time (1")
FiGURE 2. Step Response.

,

12
10

-St--+------3i,I:,-'--,.-"---I

Q.

__~__-+__-+~~

o

18
16
14

~"
'0.

>

1\

30

Ot--+-....:".-.,.;...,.-t--'-"-'+"';"-f

~

"0

\

S

~

.c

20

"

~
10k I Ok 1M
100
Ik
Frequency (Hz)
FIGURE S. Nonlinearity vs. Fre,quency.

10
FIGURE 4. Input Range for Linear
Response.

10 100 I~ '10k 100 I
Input Frequency (Hz)
FIGURE 6.Fee2<>3<>-

X Input
Output
-15 VDC
Make No Conn.
X Offset Adj.

6~
7~

rnA

tt:

Z Input

(BOTTOM VIEW)

4302 FUNCTIONAL OIAGRAM

General specifications for the Model
4302 Multifunction Converter are pre- .
sented on this page. These specifications characterize fhe 4302 as a versatile
fhree input multifunction converter.
The following pages are applications
oriented to help you apply the 4302
to your particular circuit function need.
These pages contain dedicated circuit
configurations in order to produce the
functions of: multiplication. division.
exponentiation, square rooting, squaring; sine, cosine, arctangent, and vector
algebra.
It is the purpose of this. product data
sheet to enable you to apply the 4302
to your analog conversion needs quickly
and efficiently.

Vy~-4~~~~~

Vxo---------~~HiI~il----__,
Vzo---------~~

POWERS

ROOTS
(0.2';;

m<

1)

(1

< rn';;

5)

(m~

1)

~ ~.
":"

Many of the folloWing circuit ·configurations using the 4302 require .a reference voltage for scaling purposes. The reference
voltage is shown to be +15 VDC (+15 VDC REF.) since in
most cases the +15VDC power source for the 4302 has sufficient time and tempera·ture related stability to achieve the
specified typical accuracies.

4-117

If the particular supplies which are available for powering the
4302 do not have the necess~y .stability for the required conversion accuracy, an additional + 1 S VDC precision supply may
be required.

MULTIPLIER/DIVIDEIFUNCTIONS
MULTIPLIER-~-------.....:--.
,

In multiplier applic~tions the 4302 provides high accuracy
at a low cost. The 4302 accepts inputs up to + 10 VDC and
provides Ii typical accuracy of ±0.2S% of full scale.

E;fE Z
Eo = + ' - - ,
10,

Transfer Function

ACCURACY,
Total Errors

FIGURE 1

Typical at +25 o C,
Maximum "at +2S~C

{

(for input range)
vs. Temperature
Offset Errors (EI'=EJ, = 0)
Output Offset (at 25 C)
, 'VS. Temperature
+15 VDC
REF

>25 mV
<50 mV
10.03V<:E I <: 10. V
0.01 V<:EZ <: Io.V
0.2 mV/oC

NOISE'(1o.'Hz to I kHz)

10.0 /IV rms

BANDWIDTH (El' E 2 )
Small Signal ( -3 dB)
Full Output

5110 kHz
60 kHz

(I) Set RI so that with Ej = EZ '" +10.00 VDC, Eo = +10.00 VDC.

DIVIDER
As a divider, the 4302 outperforms many of the multiplierl
dividers on the market at a much lower cost. In the divider
configuration the 4302 boasts a typical conversion accuracy
of ±0.2S% ot: full scale.
+15VDC
,REF U-"...,..,.....IV""
Eo = +10 (E I /E 3 )

Transfer Function

~3O-----\!~~"'t"""':~~

I", ACCURACY
Total Errors
Typical at +2S0 C
Maximum at +2S o C
(for EI <:

~3

*

ani! input range)

vs. l'emperature
Offset Errors (E I = 0., E3 = + I 0 V)
Output Offset (at 25°C)'
VS. Temperature

NOISE (10. Hz to I kHz)
E3=+lo.V
E3=+0.1 V
BANDWIDTH (El' E 3)
Small Signal (-3 dB)
Full Output
(E3 = +10. V)

±25 mV
±50mV
{ 0.03V <:E I <: 10V
0.1 V<:E 3 <:lo.V
2 m VDC
±2,5m VDC
±15 mVDC
0..2<: m<: 5
0. to +10. VDC
0. to +10. VDC

FIGURE 4

_

E

1

Use these connections
when taking roots of
small input levels.

_

Exponentiator Transfer Characteristics

NOTES:
(1) Connect a 100 n potentiometer as shown in Figure 4 for either
roots (0.2':;; m < 1) or powers (1 < m':;; 5).
(2) Set Rl so that with EI ~ +10.00 VDC, Eo ~ +10.00 VDC.
(3) Select a + DC voltage level (E 1) such that the output voltage
(Eo), as acted upon by the desired exponent, will not exceed
+ 1 0,00 VDC. A level which is mid-range for input values of
interest is. an appropriate one to use~ Set R2 so that the out-

(4) Repeat steps (2) through (4) as necessary.

*

put vo1tage (Eo) is the value expected for the chosen values of

input (E 1) and exponent (m).

SQUARE

When taking roots of smaller input levels. a modified transfer
equation (Eo::; (IOE])rn] will provide improved conversion
accuracy. To achieve this transfer function: 1) apply a +1.5 VDC
REF in place of the +15 VDC REF shown in Figure 4., 2) make
R3 a 1.40 Mn resistor, and rearrange R J and R3 as 1.5VDC REF
and 3) follow all notes except in note (2) apply +0.1 ovne to pin
7 to set R 1 to Eo ~ + 1.00VDC.
.

ROOT----~-----

As a Square Rooter (m = 0.5), the 4302 provides a typical
total conversion accuracy of ±0.07%. Refer to Figure 5 and
notes for connections and adjustments respectively.
Transfer Function

Total Conversioil Error (Typical)
0.5 VDC < EI .; 10 VDC
0.02 VDC < EI .:;; 0.5 VDC
Input Voltage Range
Output Voltage Range

Eo~IO~
10
±7mV
±SS mV
o to +10 VDC
Oto+IOVDC

NOTES:
(1) Connect pins 12,11, and 6 together. Set Rl such that with

EI ~ +10.00 VDC; Eo ~ +10.00 VDC.
(2) Connect 100 n resistors as shown in Figure 5.
(3) For greater conversion accuracy. R2 & R3 may be replaced by
a potentiometer as shown in Figure 4.

SQUARE -,.---.---------~
Configured as a Square Function Converter (m = 2), the
4302 produces high conversion accuracies of typically 0.03%.
Please refer to Figure 6 and accompanying notes.
Transfer Function
Total Conversion Error (typical)
0.1 VDC':;; EI .:;; 10 VDC
Input Voltage Range
Output Voltage Range

Eo

~

10

(~~) 2

±3mV
VDC
o to +10 VDC

o to +10

NOTES:
(I) Set Rl such that with EI ~ +10.00 VDC, Eo ~ +10.00 VDC.
(2) ~onne,ct 100 n resistors as shown in Figure 6.
(3) For greater conversion accuracy R2 & R3 may be replaced by
a potentiometer as shown in Figure 4.

4..,119

TRIGONOMETRIC FUNCTIONS
SINE------,------'------,---~-Sine functions can be accurately generated from input voltage levels representing angular displacement from 0 to 900 .
Model 4302 configured as in Figure 7 will produce the sine
power series approximations with modified coefficients to
typically better than ±0.5% of full scale. In this circuit, the
4302 is scaled so that when e =0, Eo =0 vnc, and when
=90, Eo = laVnC.

e

NOTES:
(I) Adjust R4.if needed so that EI < I rn VDC when Eo = O.
(2) Adjust R2 so that EI = +0.8045 VDC when EiJ = +5.00 VDC.
(3) Adjus\ R3 so that EI = +~. 709 VDC wh,m EO = + I 0.00 VDC.
(4~ Repeat steps (2) .nd (3) as necessary.

Eo =10 Sin 9E o

Transfer Func.tion

Power S~ries Approximation
Eo = !.5708E o -LS924

~6.366
EO y.S27

Total Conversion Error (typical)

±50mV

Input Voltage Range (0 .. 0 .. 90°)

Oto+lO VDC

Output Voltage Range (0 ..sin 0 .. I)

o to +10

VDC

FIGURE,7
10kf!
+15 Vdc
REF

137 kf!

845 kf!

36.6 kf!

_

COSINE
Connected as in F igure 2, the Model 4302 will generate a
cosine furiction of the input voltage. Typical accuracies of
±0.8% can be expe cted froin this'configuration.
NOTES:
(I) Adjust RI so tha t lio = +10.00 VDC when EO:' O.
(2) Adjust R2 so tha tEo = 0 when Eo = +10.00 VDC.

Eo = 10 cos 9E o

Transfer Fl-Inction

Power Series Approximation
Eo = 10 + 0.3652 EO

_0.427~E!'504
±80rnV

Total Conversion Error (typical)
Input V ott.go Range (0 .. 0 .. 90°)

o VDC to +10 VDC

Output V ott age Range (I .. cos 8 .. 0)

+10 VDC to 0 VDC.

FIGURE 8.

+15 VDC REF

20.5 ill
14.0 kf!
+15 VDC'
REF

+15 VDC

10.0 ill

Eo

~15

-

37.4 kf!

-

EO

4-120

"C"

VDC

ARCTANGEN-T
Model 4302 and the associated circuitry shown below will
produce the inverse tangent of a ratio. This application is
particularly well suited to conversion from rectangular
coordinates to polar coordinates where
E
EO =tan- 1 ~

Transfer Function

Eo = tan

[E21

(900)

(Ell Y_21Z5
1+ - [Ezl

Ex

NOTE:

iE;T

( [EIJ)1.2125
Eo =

.Power Series Approximation

The accuracy of conversion depends upon the levels of the
input signals. Please refer to table at right.
(I) Set R) so that with E1

7IGEII.)

Total Conversion Error

Z < E 1 • E 2 .. 10 VDC
0.1 < EI. E2" 2 VDC
0.03 < E1. EZ .. 0.1 VDC
Input Voltage Range (EI' E2)
Output Voltage Range 0 . ;;;;: En .s;;: 90°

= E2 =+10.00VDC. Eo; +4.500 VDC

±I mVDC.

±55 m VDC
±65 m VDC
±340 m VDC
+0.01 VDC to +10 VDC
o VDC to +9 VDC

E,
E,

+ISVDC

VECTOR MAGNITUDE FUNCTION
The model 4302 will produce the square root ofthe sum of
the squares of two inputs. This function is companion to the
arctangent of a ratio for the conversion of rectangular to
polar coordinates.

(refer to notes 1 and 2)

Output Voltage Range

o to +10VDC

NOTES:

Conversion Error

±1mVDC

Transfer Function
Input Voltage Range E 1
E2

o to +IOVDC
-IOVDC to + 10VDC

1. Figure to shows one practical way to implement the transfer function Eo=JEli+E/
using 4302. It shows use of model 350JA op
amp. Model 3501'5 rated output is ±IOV.
This limits the range of El and E2. such that

the conditions E,:s;;;y' 100 - E2 and
I-Ed.;; (5 - E,'/20) and
v'E7+E7 ~ 10 are always satisfied.
(a) The above conditions imply,
OV ~ El :;;; JOV and -5V ~ E~ ~ 5V.
(b) The a.hove conditions also imply that for
applications where El =j E~I the range would
be limited to 4.142V max.
2: Use of model 3627 as shown in Figure JI
would directly substitute the eight IOk!1 resistors and the two model 350JA op amps.
This would reduce the number of
components needed to implement vector
magnitude function and reduce overall cost.,

IN4154
or oquiv.

E'CF------------------------______-'

4-121

BURR-BROWN®

4340

1_131

TRUE RMS-TO-OC CONVERTER
FEATURES
• LOW COST
• HIGH ACCURACY
±D.3mV ±O.t % Reading
• HIGH INPUT IMPEDANCE· 5ku
• HERMETIC METAL PACKAGE

DESCRIPTION
output impedance of I U. This product will supply ~p
to SmA of output current at a voltage of +IOYDC.
The input is fully protected for conditions of
overvoltage up to the supply voltage. The output will
withstand short-circuit to power supply common for
an indefinite period of time.
The specified unadjusted performance characteristics of the. 4340 are shown in the Electrical
Specifications. Provision for the external adjustment
of gain, voltage offset, DC reversal error, and
frequency response performance allow the user to
improve upon the specified conversion accuracies to
the degree required by the user's application .

The Burr-,Brown Model 4340 is a true rms"to,DC
converter featuring high performance, low cost, and
a small hermetiC package. The 4340 will compute the
true rms value of a variety of signals applied to the
input. The input signal may consist of complex AC
waveforms as well as a DC voltage level. The output
of the 4340 is a DC voltage, the amplitude of which is
equal to the rms value of the input voltage.
The 4340 will acc,ept input voltages from 0 to ± lOy'
over a wide input frequency range. The conversion
accuracy of the 4340 is specified in terms of error in
millivolts plus a percent of reading, as a function of
.input signal level over an input frequency range.
The 4340 has an input impedance of SkU and an

IAvaraglng)

r - - - - - - - - - - - - -- - - - - - - - -. - - - - - ,
I

I

I
I Eo

, X2

El I
I

I
I

.I

Ringing ClIlUII

I _______________________ J
L

International Airport Industrial Park· P.O. Box 11400· Tucso~. ArlzlHII 85734· Tel. (602) 746-1111 . Twx: 910-952·1111 . Cabla: BBRCORP . Telex: 66-6491

4-122

SPECIFICATIONS
MECHANICAL
NOTE:
Leads in true position withIn .010" (.25mm) A
at seatmg plane.

ELECTRICAL
Typical at 25°C with rated power supplies unless otherwise noted.
MODEL

@

MMC

4340

Eo{DCI=~

TRANSFER FUNCTION
INPUT
Peak Voltage
Absolute Maximum Voltage
Impedance

±10VDC
±Supply
5kl)

OUTPUT
Voltage
Current, min
Impedance

°

CONVERSION,ACCURACY
Total Unadjusted Error, max
Input: 10mV. rrns to 7V, rrns
Input: 100Hz to 10kHz sine wave·
Total Adjusted Error"
Input: 10mV, rms to 7V, rms
Input: 50Hz to 20kHz·
STABILITY
Accuracy vs Temperature

to +10VDC
+5mA
HI

±2mV ±O.2% Reading

±O.3mV

::to. 1% Reading

±O,001% of FSR plus
±O.01% of reading per °C
±O,001% of FSR plus
±O.01% of reading per %~V

Accuracy vs Supply

DIM

TEMPERATURE RANGE
Operating
Storage

-25°C to +85°C
-55°C to +125°C

POWER REQUIREMENTS
Rated Voltage
Voltage Range
Quiescent Current

±15VDC
±14VDC to ±16VDC
±12mA

"Model 4340 will convert DC inputs. Lowerfrequency AC input signals will require the addition of
external capacitors to preserve the accuracy.
"Performance with external trims and CL ~ 3",F and 20pF ~ CH ~ 100pF.

INCHES
MIN
MAX

MILLIMETERS
MIN
MAX

A

.860

.S80

21.84

22.35

B

.490

.510

12.45

12.95

C

.170

.250

4.32

6.35

0

.016

.021

0.41

0.53

G

.100 BASIC

H

.115

K

.150

2.54 BASIC

.155

2.92

1,300
.300 BASIC

3.81

L

A

,080

2,03

3.94

I

7.62

7.62 BASIC

1,120

_I

3.05

Pin material and plating composition meet
method 2003 (solderability) of MIL-STD-883
(except for paragraph 3.2.1).

PIN CONNECTIONS
Averaging

Square
Rooting

--..

@

@

@

@

@

@

@

-'Pinl

>-t--IFx
I
I
I

I

L

Pin 8

I

@

@

@\,

I

I

L-f.____

~

Ra_n_IP_·n_g_c_ir_C_U_it_ _ _. .

- -

J

COMMON

:

_ _ _ _ .-J

(BOTTOM VIEW)

FIGURE I. Functional Block Diagram of Model 4340.

4-123

.INST~L~ATION ANDO'PERATION INSTRUCTIONS

_......._---0----.
. . . ---

+I5VDC

"15VDC Eo*

o

FIGURE 2. Model 4340 RMS Converter" Connected to Produce Specified Unadjusted Accuracy.

OPTIONAL EXTERNAL ADJUSTMENTS
Although the unadjusted performance of the 4340 is quite'
high for most 

u

1.

0:

"~

0.
a

E

i=

a:
o
e-o

~

c
o

"
It
~

o

10Hz

30Hz

70Hz 100Hz

300Hz

700Hz 1 kHz

1.00V RMS Sine Wave Input Frequency
Averaging Capacitor Value

FIGURE 2. Output Ripple Magnitude vs. Input Signal
Frequency.

FIGURE 3. Response Time vs. Vallie of Averaging
Capacitor.

EXPANDED TRIM PROCEDURE FOR GREATER ACCURACY
If the 4341 is used in applications to measure complex
waveforms, the following expanded trim procedure is
recommended. (Refer to Figure 4).
First set all potentiometers at mid turn position.
I. DC Reversal Error - Apply +1O.000V ±lmV and

-1O.OOOV ±lmV to E'n alternatively, adjust R5 such
that Eo readirigs are the same ±2mV.
2. Gain Adjustment - Apply E'n = + IO.OOOVDC
±lmV, adjust RI such that Eo =+IO.OOOVDC ±lmV.
3. Input Offset - Apply +1O.OmV ±O.lmV and -1O.OmV
±O.I m V to E'n, adjust R4 such that Eo readings are the
same ±O.lmV.
4. Offset - Ground Em, adjust R3 such that
Eo = 0 ±O.I m V. Repeat Step (3).
5. Low Level Accuracy - Apply Em =+IO.OmV ±o.lmV,
adjust R2 such that Eo == +1O.OmV ±o.lmV.

1%

C Averaging
Capacitor

+15VDC

~

R4
10kn ~

-15VDC

··15VDC

FIGURE 4. Expanded Trim Procedure (High Accuracy
Applications).

NONUNITY GAINS
Gain values greater than unity can be achieved by inserting resistor R. between pin 5 and pin 6. R. "'" (A 2 - I) x 10k + 2k
where A is the desired value of gain (I < A ,,;; 10). (R. is in ohms).

4-129

BURR~BROWN®

4423

IIEIElI

PRECISION QUADRATURE OSCILLATOR
FEATURES

DESCRIPTION

• SINE AND COSINE OUTPUTS

The Model 4423 is a precision quadrature oscillator.
It has two outputs 90 degrees out of phase with each
other, thus providing sine and cosine wave outputs
available at the same time. The 4423 is resistor pro·
grammable and is easy to use. It has low distortion
(0..2% max up to 5kHz) and excellent frequency and
amplitude stability.
The Model 4423 ,also includes an uncommitted
operational amplifier which may be used. as a buffer,
a level sllifter, or as an independent operational
amplifier. The 4423 is packaged in a versatile, small,
low-cost DIP package.

• RESISTOR·PROGRAMMABLE FREQUENCY
• WIDE FREQUENCY RANGE: 0.802Hz to 20kHz
• LOW DISTORTION: 0.2% max up to 5kHz
• EASY ADJUSTMENTS
• SMALL SIZE
• LOW COST

Inlernational Airport Induatrial Park· P,O. 80x 11400· Tucson. Arizona 85734· Tel. (602174&·1111 . Twx: 910-952·1111· Cable: 88RCORp· Telex: 66-8491

4~130

SPECIFICATIONS
Prices and SpecifICations
subject to change without notice

Specifications typical at 25"C and ±15VDC
Power Supply Unless Otherwise Noted

ELECTRICAL
MIN

TYP

MAX

UNITS

20.0k
2k
,0,002

20.5

21.0k
20k
20k
±5
±IOO

Hz
Hz
Hz

MECHANICAL

FREQUENCY
Initial Frequency (no adjustments)
Frequency Range (using 2 R's only)
Frequency Range (using 2 R's and 2 es)
Accuracy of Frequency EquationStability vs Temperature
Quadrature Phase Error

±I
±50
±O.I

-t J 1
Dotove'-tJ~/
12.7mm

20.3mm
(0.80")'

%
ppmj"C
degree

DISTORTION

Pin

Sine Output (pin 1)
0.002Hz to 5kHz
5kHz to 20kHz

0.2
0.5

Cosine Output (pin 7)
0,002Hz to 5kHz
5kHz to 20kHz
Distortion vs Temperature

6,5

0.2
0.8

%
%

0.015

%:"C

1.5

7.5

7
0.05
0.4
5

~

/"/7
1 n'_~
Pin'

~~~

n0

---r

u

?O~2~~
- P i n 14
(0.020")

Vrms

%/"C
V/V

Pin material and plating composition
conform to method 2003 (solderability)·

mA
il

I

of MIL·STO-883 (except paragraph 3.2).
mV
nA
Mil

1.5
275
1

dB

90
5

mA

POWER SUPPLY
Rated Supply Voltage
Supply Voltage Range
Quiescent Current

±18
±18

VDC
VOC
mA

+70
+85
+125

"C
"C
"C

±15
±12
±9

+

TEMPERATURE RANGE
0
-25
-55

Specifications
Operation
Storage

~
5

A4

-

6

- May be trimmed for better accuracy.

PIN CONNECTIONS
1. E 1, Sine Output

8. Frequency Adjustment

2. Frequency Adjustment

9. -V cc- -15VDC

3.
4.
6.
6.
7.

frequency Adjustment
+In, Uncommitted Op Amp
-In, Uncommitted Op Amp
Output, Uncommitted Op Amp
E2, Cosine Output

.

JLo.51mm

ROW SPACING· 7,6 (0.300")
WEIGHT - 3.4 gms (0.12 Ol)
CONNECTOR· 14 pin DIP connector

UNCOMMITTED OP AMP
Input Offset Voltaic
Input Bias Current
Input Impedance
Open Loop Gain
Output Current

1

%
%

OUTPUT
Amplitude (Sine)
At 20 kHz
vs Temperature
vs Supply
Output Current
Output impedance

;o6,;;:r;

(0,50")

10.
11.
12.
13.
14.

+V cc. +15VOC
Common
F req uen cy Adj ustmant
Frequency Adjustment
Frequency Adjustment

FIGURE I. Equivalent Circuit.

4-131

TVPICALPERFORMANC'E CURVES
+5%

r\,
\
"

t-..... .......

'"
"

K
\

-5%

-5%

'10Hz

100Hz

Frequency

FIGURE 2,

,1kHz
10kHz
Frequency-

-so

100kHz

FIGURE 3.

EXTERNAL CONNECTIONS

0
+50
+100
. Temperature °c

+150

FIGURE 4.
TI" frequency f can be expressed by:

I. 20 kHz Quadrature Oscillator
The 4423 does not require any external component to
obtain a 20 kHz quadrature oscillator. The connection
diagram is as shown in Figure S.

El~

42.0S R
f

= (C + 0.001) (3.78S +2R)

where, f is in Hz ,
C is in ~F
and R is in kfl

10 sin 27r(20klt

4423
El~

10 sin 211ft

FIGURES.
2. Resistor Programmable Quadrature Oscillator
For resistor programmable frequencies in the 2 kHz to
20 ,kHz frequency range, the connection diagram is
shown in Figure 6. Note that only two resistors of equal
value are required. The resistor Rcan be expressed by,
, R in kfl
R =3.78Sf
42.0S - 2f
f in kHz

FIGURE 7.
For best results, the capacitor values shown in Table I
should be selected with respect to their frequency ranges.
20 kHz

f

e

E,= 10sin 2'1J'ft

20 Hz

FIGURE 6.
; 3. Quadrature Oscillator Programmable to 0.002 Hz
For oscillator frequencies below 2000' Hz, use of two
capacitors of equal value and two resistors of equal value
as shown in Figure 7' is recommended. Connections
shown in Figure 7 can be used to get oscillator frequency
in the 0.002 Hz to 20 kHz range. '

4-132

2 kHz

200Hz

to

to

2 kHz

2,00 Hz

0

O.OI/iF

O.I/IF

0.2 Hz

0.02 Hz

2 Hz

to

to
20 Hz

to

to

2 Hz

0.2 Hz

0.02 Hz,

0.002 Hz

to

IpF

IO/iF

100j.F

1000/iF

TABLE I.
After selecting the capacitor for a particular frequency
the value of the required resistor can be obtained by using
the resistor selection' curve shown in Figure 8 or by the
expression:
3.78Sf (C + 0.001)
~here,
R = 42.0S _ 2f (C + 0.001)
Risinkfl
fisinHz
and C is in ~F

DISSIPATION FACTOR (OF)
A capacitor can be modeled by an ideal capacitor in
parallel with an internal resistor whose value depends on
its dissipation factor (DF). Mathematically, the internal
resistor R is given by,

10k!1

0:

I k!1

J

J

..J

..:

~

lOon

oJ

....

><
,~

Ion

~

," r-,~
,v ~-9,,:r-~~
," r-~
~'9". ~v"

"

1!1
O.OOIHz O.OIHz O.IHz

1Hz

10Hz

100Hz

R=

1kHz

10kHz IOOkH,

FRFQlIENCY

FIGURE 8.
The curves shown in Figure 8 are provided only as a
nomographic design aid. The selection of capacitor
values is not limited to t1~e values shown in Figure 8. Any
suitable combination of Rand C values which satisfies
the expression relating R, F and C as shown above, would
work satisfactorily with the 4423.
NOTES ON TYPES OF CAPACITORS TO USE:
There are various kinds of capacitors available for use.
There are polarized, also known as DC capacitors and
non-polarized, also known as AC capacitors available. Of
these two types, the polarized capacitors cannot be used
with 4423 to set the frequencies.
Commonly available non-polarized capacitors inclpde
NPO ceramic, silver mica, teflon, polystyrene,
polycarbonate, mylar, ceramic disc etc. A comparison is
shown in Table II.
Capacitance
Range (pF)

NPO Ceramic
Silver Mica
Teflon
Polystyrene
Polycarbonate
Metalized Teflon

SpF - 0.1 pF
SpF - 0.047 pF
0.001 - 100 pF
0.001 - 500 pF
0.001 - 1000 pF
0.001 - 100 pF

Temperature
Coefficients
ppm/'C

Dissipation
Factor (%)

30

0.05
0.05
0.01
0.03
0.08
0.1

60

200
100
90

Metalized Mylar
Ceramic Disc

0.001 - 1000 pF
0.001 - 1000 pF
0.001 - 2000 pF
SpF - 0.5 pF

60

10
700
700
10,000

where R is in ll, f is the Hz, and C is in farads.
For example, 'the DF of ceramic disc capacitors is of the
order of 3%, which for a 0.01 /-IF capacitor would look
like having an internal resistor of 530kll at I kHz. The
530 k!l value resistor is small enough to stop the 4423
oscillator from osCillating.
Some capacitor manufacturers use the terms "Power
Factor" (PF) or "Q Factor" (Q) instead of the term
"Dissipation Factor". These terms are similar in meaning
and are mathematically related by,
(DF)
(PF)

I

Q=(DF)

OSCILLATION AMPLITUDE
It takes a finite time to build up the amplitude of the
oscillation to its final full scale value. There is a
relationship between the amplitude build-up time and the
frequency. The lower the frequency, the longer the
amplitude build-up time. For example, typically it takes
250 seconds at I Hz, 30 seconds at 10Hz, 4 seconds at 100
Hz, 400 milliseconds at' I kHz, and 40 milliseconds at 10
kHz oscillator frequencies.
There are two methods available to shorten this normal
amplitude build-up time. But there is also a relationship
between the amplitude build-up time and distortion at
final amplitude value. When the amplitude build-up time
is shortened, the distortion can get worse.
One method to shorten the amplitude build-up time is to
connect a resistor between pin 3 and pin 14. The lower this
resistor is the shorter will be the time to build up
amplitude of the oscillation, and worse will be the
distortion of the output waveform. For example, a lookll
resistor would shorten the amplitude build up time from
15 seconds to I second at 20 Hz frequency, but, the
distortion could be degraded from'tpically 0.05% to 0.5%.
The other method is to momentarily insert a I kll resistor
via a reset switch betwen pin 3 and pin 14. The amplitude
of oscillation is built· up instantaneously when the reset
switch is pushed. There will be no degradation of
distortion with this method since the Ik!l resistor does
not remain in the circuit continuously.

Metalized
Polycarbonate
Mylar

I

271'f C(DF)

0.4
0.7
I

3

TABLE II.

For use with the 4423 oscillator, the choice of capacitors
depends mainly on the user's application, error budget
and cost budget. Note that the specifications of 4423 do
not include the error contribution of the external
components. The errors sourced by external components
normally have to be added to the 4423 specifications.
As a general selection criteria we'recommend the use of
the above table. Start from the top of the list in the above
table. If the capacitor is found unsuitable due to it being
too large in size, too expensive, or is not easily available,
then move down in the list for the next best selection. In
any case do not choose or use any capacitors with
dissipation factors greater than 1%. Such a' capacitor
would stop 4423 oscillation.

4-133

4-134

ANALOG-TO-DIGITAL
CONVERTERS

The Burr-Brown analog-to-digital converter product line has a broad
range of devices that enable the user to select the performance and
price range ideally suited for the application. The high-performance
12-bit ADC80, whic.h converts to 12-bit accuracy in 25psec, was originated by Burr-Brown in 1975 and has become an industry standard.
The recently introduced ADC803 is a 12-bit, 1.5psec conversion time
AID converter that multiplies your system's throughput capabilities at
the best price/performance ratio available. A high-resolution converter, the ADC76, converts 16 bits to ±O.003% absolute accuracy in only
15psec and is packaged in a 32-pin triple-wide dual-in-line package.
Other performance categories are high-temperature (up to +200°C),
and total harmonic distortion for digital recording of audio.
All devices are totally complete and fully specified, and have a track
record of high reliability proven both in the field as well as in internal
qualification testing.

5-1

SELECTION GUIDE
ANALOG-TO-DIGITAL CONVERTERS .
3~sec,

and low cost 12~bit designs that convert in 25~sec .
High resolution 16-bit converters in· small DIL packages
give conversions to 0.003% accuracy ir: 15~sec at a very
reasonable price; Harsh temperature environments can
be handled as well with 12-bit converters that operate to
+200°C.

These designs will meet your most demanding applica.tions. We employ monolithic technology to support the
high performance offered. The successive-approximation
design approach produces ADC's that give 12-bit conversion in as low as 1.5~sec, 8-bit conversion in less than

ANALOG-TO-OIGITAL CONVERTERS

Conver·
sion Time,

Bipolar, max

max (psec)

(ppm FSRI" C)

Accy. Drift

Input
Range
(V)

Rangel2l

Temp
Package

Page

LowC.osl

ADCSOAG-IO·31
ADC80AG-12'"

)0
·12

±0.048
±O.012

21
25

±23
±23

±2.5,±5,
±IO, +5,+10

Ind
Ind

CeramiC
o 32-pin
Dip

5-54
5-54

Low Coal,
High Speed

ADC82AG-IO
ADC82AM, (0) .

8
8

±0.2
±O.2

2.8
2.8

±60

±2i5. ±5, ±IO,
+5,+10,+20

Ind
·Ind

24-pin
DIP

5-62
5-62

ADC84KG·IO
ADC84KG-12

10
12

±O.048
:±0.012

6

#1·
±2i

:±2.5,. ±5,. ±IO,

10

+5,+10

qom
Com

32-pln
DIP

5-70
5-70

Lowprlft,
High Speed

AD85C-IO
ADC85-IO
ADC85C-12,'(0)
ADC85-12, (0)

10
10.
12
12

±O.048
±0.048
±O.012
±0.012

·6
6
10
10

±26
±16
±19
±13

±2:S, ±5, ±10,
+5;+10

Com
Ind·
Com
Ind.

Metal
Hermetic
32-pln
DIP

5-70
5-70
5-70
5-70

Very High
Speed

ADC603BM
ADC603CM

12
12

±0.02O
±0.015

1.5
1.5

±23
±23

±5, ±10,-10
±5, ±IO, -10

Ind
Ind

Metal
Hermetic
32Cpin
DIP

5-86
5-86

High
High
Accuracy

ADC73J
ADC73K
ADC731J
ADC73IK·

16
16
16
16

±0.DOI5
±0.0D075
±0.DOI5
±0.0D075

170
170
170
170

±9
±9
±9
±9

±5,±10,
+10,+20

Com
Com
Com
Com

Module
Module
Module
Module

5-35
5-35
·5-35
5-35

High
Resolution

ADC71JG·
ADC71KG

16
16

±O.OO6
±O.OO3

50
50

±15
±15

±2.5, ±S, :tl0,
010+5,
010+10,
Oto+2O

Com
Com

Ceramic
32-pin
DIP

5-19
.5-19

ADC72AM
ADC72BM
ADC72JM
ADC72KM

16
16
16
16

±O.OO6
±O.OO3
±O.OO6
±O.OO3

50
50
50
50

±12
±12·
±17
±17

±2.5, ±5, ±10,
010+5,
010+10,
010+20

Ind
Ind
Com
Com

Metal
Hermetic
32-pln
DIP

5-27
5-27
5-27
5-27

ADC76JG
ADC76KG

16
16

±O.OO6.
±O.OO3

15
15

±15
:t15

±2.5, ±5, ±10,
010+5,
010+10,
0·10+20

Com
Com

Ceramic
32-pln
DIP

5-46
5-46

Very-Wide
Temp Range

ADC10HT
ADC10HT-l

12
12

±O.012
±O.048

50
50

±34
±63

±5,±10
±5,±10

-55'Clo
+2OO'C

Ceramic
28-pln
DIP

5-3
5-3

High Speed

AOC60-08
ADCeo.l0
ADCeo.12

B
10
12

±O.195
±O.0488
±O.0244

0.88
1.88
3.50

±2O
±20
±15

±2.5, ±5
±IO, +5
+10,+20

Com
Com
Com

Module
Module
Module

5-13
5-13
5-13

Mililary

ADC87/MIL Seriaa

High

ADCI()(J.SMD

4dlgll
+ sign

±O.OO5

30maec

±5

Com

Module

5-78

Description

.

Resolu- Linearity
Error max
tion
(Bils) (%ofFSR)

Resqlution,

Model lll

Resolution

..

±60
'"\

.

Sea Military Products
±10

NOTES: (1) "0" indicates produci alao available wilh screening for Increased reliability. See 0 Program.
!nd -25'Cto+85'C; MIL -55'C 10 +125'C. (3) "Z" models operale from ±12VDC supply.

=

=

(2) Com = 0 to +70'C;

PCM ANALOG-TO-DIGITAL CONVERTERS FOR AUDIO
Total Harmonic

Model

(Bits)

Distortion
(max)

PCM75KG
PCM75JG

16
14(·11

0.02% at -15dB
·0.05% at -15dB

Resolution

Description
PCM-Audio A(O·Converte .....
NOTES: (1) Com = 0 10 +70~C.

Conversion
Time
(max)
17psecc2I
15psec f21

Input Range
(V)

Temp
Range (1 )

Dynamic

Range

Page

±2.5, ±5, ±10
±2.5, ±5, ±IO

Com
Com

SOdB
SOdB

5-98
5-98

(2) Cen be redu","" to 8/.IS8C. (3) InternallB-bit DAC available 10 uear.

(4) Can be operated at 16 bits.

BURR-BROWN®

ADC10HT

IElElI

Wide Temperature R.ange
General Purpose 12-Bit
ANALOG-TO-DIGITAL CONVERTE.R
I-

=
=
c,:,
=
c

-

FEATURES
• -55°C to +2000C SPECIFICATIONS
• FULL 12-BIT RESOLUTION
• 50IlSBe MAX CONVERSION TIME
• NO MISSING CODES OVER FULL TEMPERATURE
RANGE
• COMPLETE WITH INTERNAL CLOCK AND ftEFERENCE
VOLTAGE
• SERIAL OUTPUT DATA AVAILABLE
• TTL AND +5V CMOS COMPATIBLE
• OUAL-WIOTH HERMETIC CERAMIC PACKAGE
• LOW POWER OPERATION WITH EXTERNAL
REFERE.NCE (250m WI

DESCRIPTION
You'l find this general purpose, 12-bit, successive
approximation AI D converter ideally qualified for
circuits that must operate over wide temperature
ranges. The ADC IOHT incorporates state-of-the-art
IC and laser-trimmed thin-film components. It is
complete with an internal clock and reference voltage.
Internal scaling resistors allow bipolar input voltage
ranges of±5V and ±IOV. A pin is provided for serial
output data. The ADCIOHT is contained in a
compact, dual width, 28-pin ceramic DIL package.
To assure consistent performance, 100% screening
procedures are conducted on the ADCIOHT at key
points during its manufacture. Burn-in and tempe'rature cycling ijre examples. A clean-.room environment is maintained for assembly operations.

~fI===~I/PIIIlMDFFIlT
J:
",,11

".!lAUEL
••ITAl

OIl"UT

....-~-ol ....'

IIIAIIlSELECT

..= ..

'-------oCllllftRTCII. ." ..

-----0

"""ou,

'-----~----oITATU.

'-----------0

""".UT

International Airport Industrial Park· P,O, Box 11400· Tucson, Arizona 85734 • Tel. [6021 746·1111 • Twx: 911).952·1111 • Cable: BBRCORP • Telex: 66·6491

5-3

SPECIFICATIONS
ELECTRICAL

-

Speclfications.at rated power supply voltages and TA - +25"C unless otherwise noted

MODEL
MIN
RESOLUTION
INPUTANALOG

12

AOC111HT
I TVP -\' MAX

I

.'

,

TVP

I
I

ADC1OHT~1

I
I

MIN
12

I
I

MAX'

I
I

UNITS
Bits
I

I

Voltage Ranges
Unipolar
Bipolar
Impedance Idlrect·input'
Oto+1OV. ±SV
.0 to +2OV. ±lOV

DlGlTAU1,
Convert Command Logic Loading

o to +10. nto +20
±S.±10.

V
V

2
4.

kll
'k'il'

1

CMOS Load

.

2
4

I

I

I

o to +10. 0 to +20
±S.±10

1

TRANSFER CHARACTERISTICS
ACCURACY
Gain Erron2l
Offset Erron2l
Unipolar
Bipolar
Linearity Error
Inherent Quantization Error
Differential Linearity Error
Total Unadjusted Erro(4)
+25°C
-SsoC to +2000C
Total Adjusted Erron5'
+25°C
-55°C to +2000C
Total Unadjusted Erron6'
E,clusive of Reference
+2SoC
-55"C 10 +2000C
T oIal Adjusted Erron7)
E,cluslve of Reference
I
+2SoC
-55"C 10 +2000C

±D.05

±0.2

±D.OS

±0.2

%

±O.OS
±D.OS

±0.2
±0.2
±D.012

±O.OS
±O.OS

:to.2
:to.2
:to.048

±112
·-±a.012

±O.024

±O.048

±O.096

% of FSR.31
%ofFSR
%of FSR
LSB
% of FSR

±D.l0
±D.3D

±0.40
±t.OO

:to.1S
±0.80

±0.40
,±1.50

%ofFSR
% of FSR

±D.OO6
±D.20

±D.012

±O.ad

±D.024
±O.SO

±O.048
±1.10

% of FSR
%ofFSR

±D.l0
±0.20

±0.40
:to.SO

±O.IS
±0.50

±0.45

:tl.l0

%of FSR
% of FSR

±D.OO6
±O.15

±0.012
±D.40

±D.024
:to.40

±0.048

:to.75

% of FSR
%ofFSR

3D

50

30

50

~sec

±15
±5

±35
±10

±25
:tID

:tl00
:t2O

ppm/oC
ppmfOC

CONVERSION TIME
DRIFT 1-55°C .. TA .. +2OOOC,
Gain
With Intamal Reference
E,cluslve of Reference
Offset
Unipolar
Bipolar
With Inlernal Reference
E,cluslve of Reference
Linearity
No Missing Codes ITemp. Range
-55"C to +2OO°C

'±112

±1

±2

±2

:tl0

ppm Of FSR/OC

±10
±4
±D.5

±35
:tl0
:tl

±25
±8
±1

±100
:t20
:t3

'ppm of FSR/oC
ppm of FSR/oC
ppm of FSRloC
Bits

10

12

OUTPUT

DIGITAL DATA
Parallel
OutpUI Codesl 61
Unipolar
Blpolan9i
Oulpul Drive
Serial Data Code I NRZ I - SB. OB
Oulpul Drive
Status
Slatus Outpul Drive
Internal ClPck
Oulput Drive
Frequency

I.
1

SB
OB.TC

I
SB.OB

1

I

I

I
I
I

Logic "1" During Conver~jon

1

1

400

5-4

SB.OB

I
I

LSTTL Loads

I

LSTTL Loads

1
Logic "1" During ConverSion
1
1

1

I
I

SB
OB.TC

I

400

LSTTL Loads
LSTTL Loads
kHz

SPECIFICATIONS
MODEL
POWER SUPPLIES AND REFEIII:NCI:

I

MIN

ADC10HT
TYP

I

±t4.5
+4.75

Rated VoHage. Analog
Digital
Supply Drain. +15VDC(10)
-15VDC(10)
+5VDC
Power Supply Sensitivity
±15VDC
+5VDC
Internal Relerence Voltage
Max External Current with
no Degradation 01 Specs
Temperature Coefficient

9.990

±15
+5
+15
-30
+16
0.01
0.01
10.0

I
MAX

I

ADC10HT-l
TYP

L

MIN

±15.5
+5.25

±14.5
+4.75

10.010

9.990

I

±15
+5
+15
-30
+16
0.01
0.01
10.0

2
±10

MAX

I

UNITS

±15.5
+5.25

-.

VDC
VDC
mA
mA
mA
%01 FSRI%Vs
%01 FSR/%Vs
V

10.010

mA
ppml"C

2
±10

TEMPERATURE RANGE
Specification
Operating
Storage

-55

+200
+200
+210

-55
-65

-55
-55

+200
+200
+2'0

~5

°C
°C
°C

NOTES:
1. +5V CMOS compatible. Input current (low to high state I = l#J,A max. Use pull·up resistor when driving convert command from TTL.
2. Adjustable to zero (see Table II and Figures 5 and 61,
3. FSR means Full Scale Range. For example. unit cpnnected lor ±'OV has a 20V FSR.
4. Includes Gain, Offset. and Linearity Errors tBipolar Model.
5. Gain and Offset Errors removed at +25°C I Bipolar Mode,.
6. Includes Gain, Offset, and Linearity Errors with external +10.DV ±lmV reference. does not include Reference Drift Bipolar Mode.
7. Gain and Offset Errors removed at t25°C with external +10.0V ±lmV reference, d~s not include Reference Drift, Bipolar Mode.
8. See Table I. SB - Straight Binary. OB - Offset Binary. TC - Two's Complement.
9. TCcoding obtained by using MSB Ipin 131 instead ofM~B Ipin 12,.
10. May be reduced. See Low Power Operation. pages 5-11 and 5-'2.

MECHANICAL

I

•

I

NOTES:
1.,--*lntruepclllllonwlltMnO.010"
10.25mm, A III MMC at ....... plant.

'P

[

2.Plnnu,,"*,nawnkM'~onty.

N.",.,. ""Y' not be marked on pacQge.

,.~

.

. ,. . ..

..,

INCHES

00..

r.~~
~ H.
LL-J

••
c

·•
D

G
H

L

K

N

MILLIMETERS

....... ...
...

T.OPVIEW

Bil11

, -_ _ _ _ _ _{28) SERIAL OUT

l2}----,

-1SYDC SUPPL V

Bit 10

+15 VOC SUPPLY

Bit 9~.

REF OUT ,+1OV

I

Bit 8

ANALOG COMMON

Bil7~11

f:N4Mii.(23) 20Y RANGE

Bit 6

Bit 5

10V RANGE

It--'">:;;...-!r.;)

BIPOLAR OFFSET

Bit 4

CONVERT COMMA~D

Bit 3

STATUS

Bit 2

CLOCK OUT

·MSB·Bit 1

MSB Bit1

~::-~::~~J~~E:f¥~~~~
~

OIGITAL COMMON

REF IN RATE
CLOCK
+SYOC SUPPL V

5-5

..

.

1::::.. , 8A~~il

CONNECTION DIAGRAM

LSBBit12

MA,

1 .• "
1.• '1 31 ••• 17.21
.1108Aa1C 11.48 8AaiC
•1ao .201
1.21
.011 .01'
.01S
1••0
.0.1
1.14
.1008A81C
2.14 8A81C
.0&1 .0'5
1.40
2 .• '
.001 .0'1'
.155 .1'5
.'00 BASIC
.020 .010
.71

TYPICAL PERFORMANCE CURVES
POWER SUPPLY REJECtiON VS
POWER SUI;>PLYRIPPLE FRE\QUENCY

LINEARITY ERROR VS CONVERSION l!jPEEO

p.200

-f--

0.175

g
to

-- -- 1i2Lks,;i; SBit. 7 1--, --

~1:-

'1c:

I~~~~~~m~~~~I~

0.04

t+++++++++-+1-+1rl-H-H-t++t-+-hI -15V

0.02

H-t+t+-H-H-H-H'-t-H-H-Hl'l-t1-H

0.008

~lllllllmllllm

0.002

t+++++++++-+1-HI+I-IIH-t++++-hI +5V

'0

p.l50

#- ~

&~

UI

~ 0.125

0.08
0.1
0.06

~ Bit 01"'rat:on

o~

f--l0 Bit Operation

0.100

I ,

0.075

12 Sit

O~~ratlon

~'&

,

\\ ~,

1/2LSB
"or 10 Bits_~

~i
_t: .c
c: . 0.006
0.01
00
0.004

=

-- I~ ~ ~ - -:-- i- tsel'or:~Bl~
-....
-~'
~I
o

::; 0.050

112

0.025

~

o

5

ro

~

~

~

~

~

$

~

~

±15V

I

#-

Oc0010~.I.I..I.I.l~O.l.l..I.I.l..100..l.l"""ll.kI.I.l.I.l0~kll:l.~100k

50

frequency (Hz]

Conversion Time {"sec l

DISCUSSION OF PERFORMANCE
The accuracy of a successive approximation AI D
converter is described by the transfer function shown in
Figure I. All successive approximation AI D converters
have an inherent Quantization Error of ±1/2LSB. The
remaining erro~ in the AI D converter are combinations
of analog errors due to the linear circuitry, matching and
tracking properties of the ladder.and scaling networks,
power supply rejection, and'reference errors. In summary.
these errors consist of initial errors including Gain.
. Offset. Linearity. Differential Linearity. and Power
Supply Sensitivity . .Initial Gain and Offset errors may be
adjusted 'to zero. Gain drift dver temperature rotates the
line (Figure I ) about the aero or,minus full scale point (all
bits Off) and Offset drift shiftS'the line left or right over
the operating temperature range. Linearity error is
unadjustable and is the most meaningful indicator of
AI D converter accuracy. Linearity error is the deviation
of an actual bit transiti~n from the ideal transition value
at any level over the range of the AI D converter. A
Differential Linearity error of ± 1/2LSB means that the
width of each bit step over range of the AI D converter is
ILSB.±1/2LSB.
The ADCIOHT is also Monotonic. assuring that the
oUtput digital code either increases or remains the same
for increasing analog input' signals. Burr-Brown also
specifies that this converter wi'll have no missing codes
over the fuil operating temperature range:,

1111... 1111
1111 •. 1110

l

;!
5

i....

1100_1100
1100..•0010

looo...1lIJOO
0111 ... 1111

h

'f-----;.-r.l:r--it-H-I

t

Offset

i::::':: j{AIIB~
I'~
11IIOO.••1lIJOO

.FSR"

Analog Input
'ElnOFF
'See Table I for digital code definitions.

2"

I

:
+~SR
T

ElnON:

FIGURE I. Input vs Output for an Ideal Bipolar
AI D Converter.

5-6

·ILSB

TIMING CONSIDERATIONS
The timing diagram (Figure 2) assumes an analog input
such that the positive true digital word 0110 0 III 0110
exists.

CIIIV.-tI"
C'-lIlnd
1li\liiii1

ClICk

...

...... (£001

BIt 2

---~"'"

BIt 3

== =J

IH4

185
BIt 8
BH7
IH8

BIt I
BIt '0
BIt 11

LSI
...11131

0111
Out

===J~

L-j","
IT __________________
______
~~

~~

r-=:=~J________~~~==============~
__
1''0''

~-=-

__ J

U"'"
~=~J~--------------~U"'"

U"'"

===J__
==

IT

J~--------------------~

r--

L--.l"'"
==
=J
=~=J~.--------------------------~
L--.l"'"
Tr-1
===J
4
11 ~m&
3
8
'0
LU
=-=- -= wMLiJ
"I"
"I"
'V'
'V'
''0''
T
"II"

"'"

"'" "'" ","

"'"

NOTES: ('I The clock In lhe ADCIOHT II running contlnuoully. The convBrt command mUll go law II
lust BOnm balol'1llhe riling adge af any clack puilita InlUlIe 8 canvel'llon. Ind mUll
relurn 10 the high stile II ImlBOnnc belare the succeeding low·ta-hlgh clock Iransilion.
121 ~c Jar 12 bill.
.
(31 Usa lralllng adge al clock Ia slrobe serial autput

FIGURE 2. ADCIOHT Timing Diagram.

DEFINITION OF DIGITAL CODES
PARALLEL DATA
Two binary codes are available on the ADC IOHT parallel
output; they are straight binary (SB) for unipolar input
signal ranges and offset binary (OB) for bipolar input
signal ranges. Two's complement (TC) may be obtained
by using MSB (pin 13) ..
Table I shows the LSB. transition values, and code
definitions for each possible analog input signal range for
8-, 10- and 12-bit resolutions. Figure 3 shows the
connections for 12-bit resolution. parallel data output.
with ±IOV input.

SERIAL DATA
. Two straight binary codes are avaihible on the serial
output line; they are SB and OB. The serial data is
available only during conversion and appears with the
MSB occurring first. The serial data is ~ynchronous with
the internal clock as shown in the timing diagram of
Figure 2. The LSB and transition values shown in Table I
also apply to the serial data output except for the TC
code.

5-7.

I-

:c

=
c::;
=
<

_Itr. .

.......... ri_mi.

ir·.. _

II
...
_
_ n ..

"_II1II,-

· _ -............ _

.. IIirIIII ...._··

SERIAL OUT
·15V
+15V

ANAUI8GND
ANALOG INPUT

ADCIOIIT

(·IOV III +IOVJ .

CONVERT
COMMAIIO
STATUS

-.....--- - .........
+5V

...
_""_.-.ID
_

AIICIIIIT IprI/IrIMy""-"",) ......... ...
O'I.F .......
_IIIITI. 184K).

DIGITAL GROUIIO

FIGURE 3. ADC(OHT Connections for ±IOV Analog Input. 12-Bit Resolution. and Serial or Parallel Data Outpl,lt.
TABLE I. Input Voltages, Transition Values, LSB Values and Code Definitions.
INPUT VOLTAGE RANGE AND LSB VALUES

Binary I BIN I Output
Analog Input Voltage Range
Code Designation
One Least Significant Bit ILSB.)

Transition Values
MSB LSB
11k1111'1
100... 000
000...001

+10V

+5V

Oto+10V

06(11'orTC<2)

06(1) or TC(2)

56(31

Defined As:

Oto +20V
SB(3)

10V12n

10Vl2 n

2OV12 n

n=8
n=10
n=12

78.13mV
19.53mV
4.88mV

39.06mV
9.77mV
2.44mV

39.06mV
9.77rriV
2.44mV

78.13mV
19.53mV
4.88mV

+Full Scale
Mid Scale
-Full Scale

+10V - 3/2LSB
0
-10V + 1/2LSB

+5V-3/2L,SB
0
-5V+ 1/2LSB

+10V - 3/2LSB
+5V
0+ 1/2LSB

+20V - 3/2LSB
+10V
0+ 1/2LSB

2OVl2n .

F5R12 n

NOTES:
(110B = Offset Binary
(2ITC = Two's Complement - obtained by inverting the most significant bit.
(3)SB = Straight Binary
('IVoltages given are the nominal value for tranaillon to the code specified

MSEi I pin 13,

DISCUSSION OF SPECIFICATIONS
The ADCIOHT is specified to provide critical perform- .
ance criteria fora wide variety of applications. The most
critical specifications for an AI D converter are linearity,
drift, gain and offset errors, and conversion-speed effects
on accuracy. This ADC is factory trimmed and tested for
al\ critical key specifications.

POWER SUPPLY SENSITIVITY

Changes in the DC power supplies will affect acc.uracy.
The ADCIOHT power supply sensitivity is specified for
±O.OI% of FSR I %Vs for±15V supplies and ±O.OI% of
FSR / %Vs for +5V supplies. Normally. reguiated power
supplies with 1% or less ripple are recommended for use
with this ADC. See Layout Precautions, Power Supply
Decoupling and Figure 4.'

GAIN AND OFFSET ERROR
Initial Gain and Offset errors are factory trimmed to
typically ±O.05Y( of FSR at 25"C. These errors may be
trimmed to zero as shown in Figures 6 and 7.

5-8

LAYOUT AND OPERATING INSTRUCTIONS
LAYOUT PRECAUTIONS

INPUT SCALING

Analog and digital common are not connected interrially
in the ADCIOHT but should be connected together as
close to the unit as possible, preferably to a large plane
under the ADC. If these grounds must be run separately,
use wide conductor pattern and a O.oI~F to O.I~F
non polarized bypass capacitor between analog and digital
commons at the unit. Low impedance analog and digital
common returns are essential for low noise performance..
Coupling between analog inputs and digital lines should
be minimized by careful layout.

The analog input should be scaled as close to the
maximum input signal range as possible in order to utilize
the maximum signal resolution of the AI D converter.
Connect the input signal as shown in Table II. See Figure
5 for circuit details.
TABLE II. ADCIOHT Input Sca1ing Connections.

Signal
Range

Output
Code

Pin 21
To Pin

Connect
Pin 23
To

Connect
Input
Signal
ToP;n

±10V
±5V
o to +10V
o to +20V

OBorTC'
OB orTC'
SB
SB

25"
25"
Open
Open

Input Sig.
Open
Open
Input 5ig.

23
22
22
23

Connect

Input

POWER SUPPLY DECOUPLING
The power supplies should be bypassed with high
temperature mica or teflon capacitors as shown in Figure
4 to obtain noise free operation. These capacitors should
be located close to ihe ADC.

..
.

1

®

Io.I"F

DIGITAL COMMON

®

®
®

..
1
..

REF

·15VDC

0.1"],:

OU~25 VREF

RS = 25n ±D.I %If glln Idlult II not used.

RG

ANALOG
COMMON

REF

IN

o.l"F~

@)

-==

~'-0-bt-a-in-ed-b-Y~U~S-in-g~M~5~B~'-Pi-n~1-3----~------~--------~ ~
··11 optional offset adjustment is not used-connect a 25U ±O.1% resistor
from pin 21 to pin 25 to obtain specified gain and offset errors.

+5VDC

I-

17

TO D/A
CONVERTER

~

~

+15VDC
BIPOLAR
OFFSET

FIGURE 5. ADCIOHT Input Scaling Circuit.

FIGURE 4. Recommended Power Supply Decoupling.

OPTIONAL EXTERNAL GAIN AND OFFSET ADJUSTMENTS
A connection diagram for the ADCIOHT in the ±IOV
input bipolar mode of operation is shown in Figure 3. The
gain and offset adjustment resistors (R I and R2) should
be selected discrete metal,film or wirewound resistors and
noi potentiometers if optimum performance is required
under high shock and vibration levels. The internal gam
and offset errors are laser trimmed to within a maximum
error of ±0.2o/c with 25fl. 0.1 'ii resistors in place of R I
and R2. Another possible approach in many applications
is to simply remove the offset and gain errors with digital
techniques after the AI D conversion has taken place.This
approach can \'inually eliminate the need for initial gain
and offset adjustment·and even the effects of gain and
offset drift with time and temperature can often be
removed. In some cases it may be desirable to use
potentiometers.

recommended for minimum drift over temperature and
time. These pots may be any value from 10kfl to 100k!l.

.ADJUSTMENT PROCEDURE
OFFSET, Connect the Offset potentiometer or resistance
substitution boxes as shown in Figure 6. Sweep the input
through the end point transition voltage that sh.ould cause.
an output transition to all bits off E ()II~'.
Adjust the Offset potentiometer or resistor substitution
boxes until the actual end point transition voltage occurs
at E(),~r. The ideal transition voltage values of the input
are given in Table I.
GAIN ' Connect the Gain adjust potentiometer or
resistor substitution boxes as shown in Figure 7. Sweep
the input through the end point transition voltage that
should cause an output transition to all bits on (E\)~).
Adjust the Gain potentiometer until the. actual end point
transition voltage occurs at E'r'~.

Gain and Offset errors may be trimmed to zero using
external gain and offset trim potentiometers connected to
the ADC as shown in Figures 6 and 7. Multiturn
potentiometers with 100ppm/"C or better TCR's are

5-9

C

Table I details the tr~nsition voltage levels required.··
It is also possible to make the adjustm~~ts just described
with potentiometers and then replace the resistive arms
with discrete metal film or wire-wound resistors in order
to make a system more rugged before subjecting it to
harsh environments.
+15VOC

III

t;;\
IMn·
~----"""r----"_
BIPOlAR
OFFSET

Figurc~ .shQwsthe effect of c.lock. rate· control resistor
(R('R) on 'clock frequency. Figure 9 is ba'Sed on a typical
initial clock frequency of about 400kHz (conversion time
of 30,",sec for 12 bits). To determine the required clock
frequency:

fd •d = Bit Re~oluti~n
ConversIon TIme
For example. if the ADC)(IHT is short cycled to IO-bit
operation an(,i a conversion time of 20,",sec is required.
then
10
(,,"" =20,", sec = 500k Hz

101m III lOIIen

R

UNIPOLAR OFFSET
ADJUST
·15VOC

from Figure 9 a clock rate resistor (R cR ) of about 40kn is
required.
2.SM

Ibl

BIPOLAR~

OFFSET .2.1

.

50n

RI

BIPOLAR OFFSET
ADJUST

REF OUT 25

2.0M

~

~

,ll'1.0M

g

"

(3

~

SOOk

REF
OUT
SAIN
ADJUST

REF

o

IN

o

10k

20k

30k

40k

50k

60k

70k

60k

9Ok'1 OOk

Clock Adjust Resislor Ill,

FIGURE 7. Optional Gain Adjust with ±0.4% Range
of Adjustment.
CLOCK RATE CONTROL (OfTIONAl)
Faster Conversion

If adjustment of the clock rate is desired for faster
conversion times. a resistor may be connected between
Clock Rate (pin 16) and Clock Out (pin 181 as shown in
Figure 8.

CLOCK
RATE

:

FiGURE 9, Cloc,k Frequency vs Clock Rate Control
Resistor (R cR ).
Slower Conversion

The conversion time can be decreased by connecting a
capacitor from the Clock Rate pin to Digital Common
(see Figure 10) ..

,1. '

CLOCK ®I-----:--~_....;....,
RATE

-

.}

. RCR
CLOCK, IB
OUT

CLOCK
FREQUENCY
ADJUST

FIGURE 8. Optional Clock Rate Adjust for Fa~ter
Conversion Times.

DIGITAL

. _ _ _ _ _ _ _T...J ...CCR

Ii4\-

COMMON~

_

. FIGURE 10. Optional Clock Rate Adjust for Slower
Conversion Times.

5-10

Figure II shows the effect of the clock rate control
capacitor on the clock frequency.

54COOQUAD
2-INPUT NAND GATE

1M

.;, lOOK

SHORT
CYCLE CONNECT TO n + I BIT
CONVERT 20 L -_ _ _ _ _ _ _ _ _ _ _----'
COMMAND
,

1\

J:

~

FIGURE 12. Short-Cycle Circuit which· Provides for
. Lower Resolutions than 12 Bits with
Faster Conversion Times and Continuous
Conversions.

\

:>

~

u.

\.

'"£

tJ

Table III indicates where' to connect the short cycle input
for 8-bit and 10-bit resolution and gives possible
conversion time(s) obtainable by using this feature along
with the clock rate pin.

~

10K

-o

2

6

10

12

14

-

TABLE III. Short Cycle Connections and Specifications cQ.:t
for 8 to 12 Bit Resolutions.
C
Resolution I Bits I

lK

.....
=

Q

16

16

20

Connect SHORT CYCLE to:

22

Conversion Time

Clock Adjust Capacitor I nF I

i#sec1{1}

Nonlinearity at +25°C ADC10HT

FIGURE II. Clock Frequency vs. Clock Rate
Control Capacitor (C(,R).

,'!bofFSR,

10
Pin 2

8
Pin4

24

10

6

±0.012
±O.048

±O.048
±O.048

±O.l
±O.l

NOTE: 111 Adjust Conversion Time with Clock Rate Control resistor as
shown in Figures 8 and 9.

The serial output data (pin 28) is synchronous with the
internal clock. In some applications the clock frequency
must be lowered to 3kHz or 4kHz so that the data can be
transmitted over long distances. If 12-bit resolution is
required. the conversion time for 4kHz is

For 12-bit operation and continuous conversion. simply
connect status (pin 19) directly to convert command (pin
20) ..

OUTPUT DRIVE
Normally the ADCIOHT logic outputs will drive two low
power TTL loads or one LSTTL load. If long digital lines
must be driven. external logic buffers are recommended.
The digital outputs are connected directly to the internal
CMOS successive-approximation-register and can drive
+5V CMOS without the need for pull-up resistors.

.
12 bits
conversion time = 4kHz = 3msec
From Figure I I. a clock rate control capacitor. CCR. of
approximately 16nF is required.
In applications requiring such a slow conversion time. a
low-pass filter should be used at the analog input to the
ADCIOHT.

SHORT-CYCLE AND CONTINUOUS
CONVERSION OPERATION.
The ADCIOHT may be operated at faster speeds for
resolutions less than 12 bits by using the clock rate control
feature. The conversion time can be further increased by
using the short cycle circuit shown in Figure 12. Without
this circuit. the status signal (pin 19) will always remain
high for 13 clock pulses even if only 8 bits are being used.
By connecting the short cycle input of the NAND gate to
the n + I bit (connect to bit 9 for 8-bit operation. for
example) the conversion will be completed and the status
signal will go low after n + I clock pulses (9 pulses for 8-bit
operation). It should be noted that with the circuit shown
in Figure 12. the ADCIOHT will operate in a continuous
conversion mode, i.e .. a new conversion will start on the n
+ 2 clock pulse without the need for an external convert
command.

ADC10HT-l

12
N/A

HEAT DISSIPATION
The ADC fOHT dissipastes approximately 750mWand
the package has a case-to-case ambient thermal resistance
(8 L d of 35"C W. For optimum performance at +200"C,
8" should be lowered by a heat sink or by forced air over
the surface of the package. If the converter is mounted on
a PC card. improved thermal contact with the copper
ground plane under the package can be achieved by using
a silicone heat-sink compound.
LOW POWER OPERATION
. The typical supply cu;rents required by the ADCfOHT
under normal operating conditions are 15mA (+15V).
30mA (-15V). and 16mA (+5V). The average power
required (PI» is therefore

5-11

PI> = 115mA x 15Vi + 130mA x -15vl + 116mA x 5Vi
755mW.

Under certain operating conditions this power consumptioncan be reduced to as little as 250mW.
The ADC'IOHT is c~mpletely self-contained with an
internal + IOV reference voltage. The+ 15V supply is used
only to,'supply power for the op amp current source and
zener diode used in this reference: Ifan external reference
is available. tl'\e+15V supply is not required and·it can be.
removed. This reduces the PI) by 15mA x 15V =;!25mW.
The average PI) for the ADC'IOHT is therefore·reduced to
530mW.
The major contributor to the power consumption is the
-15V supply. As longas a +IOV reference is used, the Vsupply voltage must be between -13V and -16V. If.
however, a lower voltage reference is used, this V- supply
voltage can be reduced considerably which greatly reduces
the power corisumption. Loweringthe reference voltage
will, of course,' lower the full scale input voltage by a
proportional amount. For example, if the reference
,voltage is +SV, the full scale input voltage for the IOV
range input (pin 22) will be +5V, instead of + I OV with a
+ IOV reference, in the unipolar mode of operation. Table
IV indicates the minimum supply voltages and the typical
power consumption obtained when using these supply
voltages for various values of VRI'F.
TABLE IV. Minimum Power Supply Voltages and,
Typical Power C'onsumption for Operation
with External VRf.f. (Note: +15V is not.
required if internal VRH is not used.)
External

+VLOGIC

VREF

rPin 151

rMinimuml

,Typical.

+10V

+5V

-13V

470mW

+6.3V

+5V

-10V

300mW

+5V

+5V

-8V

250mW

~Vs

IPin 271

Total Power Consumption

LOW-POWER EXTERNAL REFERENCE
A simple external reference voltage can be made with a
single resistor and a zener diode as shown in Figure 13.
The power consumed by the reference is only about
75mW with +Vs = +IOV. The power supply sensitivity of
this reference is approximately ±O.02% of FSR/%Vs.

The· point Where the two: curves cross is the zerotemperature-coefficient .bias; current. +VS, and! or R"
should then be adjusted accordingly for. this optimum
operating current..

, IZ = IV, • Vzl/Ra

'~Vs."
RB
.
.

Izi

IZ
.'

z

V

"

Vz

VZERO T.C.

FIGURE 14. Simple Techniques for Obtaining a Low
'
Drift Reference Voltage.
This procedure is, also discussed in a Burr-Brown
Application Note: "Squeeze High Performance out of
Low-Cost Hybrid Data Converters, AN~86.
Other Application Notes
Burr-Brown also has other Application Notes of interest
to the converter user. In particular:~
"What. Designers Should Know About Data Converter
Drift." AN-89.
"C'orrecting ErrorsDigitally in Data Acquisition
and Control," AN-IOI.

OPERATION WITH EXTER~AL CLOCK
Figure 15 shows the internal clock circuit of the
ADC'IOHT. 10 operate with an external clock. first
connect the Clock Rate Control (pin 16) to ground. This
will shut off the internal clock and also turn off the open
collector output transistor of the LM 119 comparator.
The Clock Out (pin 18)will then be ina "high"state(+5V)
because of the 2kH pull-up resistor to +5V. Now simply
use the Clock Out pin for the external clock input. Note
that the external clock must have the capability of sinking
2.5mA when it is in the low state due to the 2kH pull-up
resistor.

9+V,
490nINOMINALI
.....-~--<.I"o.o +I.3V
CD825 ICOMPENSA TED DEVICESI
, -

~

±2Oppm/o c

- IB:3kn

FIGURE 13. Simple +6.3V External Reference That
Requires Only 75mW.

5kn

A very simple procedure can be used to obtain the lowest
possible drift with this reference. First; vary the zener
current from about 4mA to II mA by changing either the
bias voltage, +Vs, or bias resistor, R", and plot V, versus
Vas shown in Figure 14. Next, heat the zener (the exact
temperature is not important. but it should be near the
desired operating temperature). and repeat the proc~dure.

lOkI!

5kn

TO SAR

FIGURE 15. ADC'IOHT Internal Clock.

5-12

BURR-BROWN®

ADC60

IElElI

High Speed
ANALOG-TO-DIGITAL CONVERTER
FEATURES

DESCRIPTION

• FAST CONVERSION SPEED:
12-blts - 3.5Ilsec. max
10-bits - 1.88ILsac. max
8-bits - 0.88Il1ec. max
Throughput sampling rates from 250kHz (12-bits)
to 1MHz 18-blts) can be attained
• PIN-PROGRAMMABLE UNIPOLAR OR BIPOLAR
• ANALOG SIGNALS
• SERIALAND PARALLEL DATA OUTPUTS
• SELF-CONTAINED WITH INTERNAL CLOCK &
REFERENCE
Simplifies system design and reduces cost
• ±l12LSB LINEARITY
Provides accurate conversion
• NO MISSING CODES
Gain Adj.
Siy.Com
R2
Rt

BP OHIII
Camp. In
Rei. Out
Au Com
·ISVOC
+ISVOC
+SVOC
Olg. Com

Bit 1
IMSBI
Bit 2

Al!.I.

The Model ADC60 is a very high speed, successive
approximation AI D converter than is designed for
applications requiring system throughput sampling
rates from 250kHz to I M Hz. The fast conversion
speed is accomplished with proprietary fast settling
circuits which preserve linearity and drift while
permitting conversion speeds up to 100nseci bit.
Available in 8-, 10-, and l2-bit resolutions the
ADC60 contains an internal reference and clock.
Internal components are provided for pinprogrammable analog input signal ranges of±2.5V,
±5V, ±IOV, 0 to +5V, 0 to +IOV and 0 to +20V.
Digital data is available in both serial and parallel,
binary form with corresponding timing signals. All
. digital input and output signals are DTL/TTLcompatible.
The ADC60 operates from ±15VDC and +5VDC
power, and is housed,in a 2" x 4" xO.75" module with
screened-on pin function identification.

(MSBI
Bit 3
BI14
Bit 5
Bit6
Bit 7
Bit B
Blt9
Bit 10
Bit II
Bit 12
Short

fIE!!
St,...

Serial Out
StatuI
Conv.Com
Clock Out
International Airport Industrial Park - P.O. Box 11400 - Tucson. Arizona 85734 - Tel. (6021 746·1111 • Twx: 910-952-1111 - Cable: BBRCORP - Telex: 66-6491

5-13

THEORY OF 'O'PERATION
TIMING CONSIDERATIONS
Upon receipt "tlf an external Convert Command;ttie:
previ'ous data sample' is cleared from the outpu(registe'r:
"Pata is available in both sl!.riala~d parallel fo(m,jiming
Each bit is 'then successively compared agliinsJ"thl:
signals are available for the, tra;nsfer"o[data,to external'
amplitude of the input signal. and is either held as a"~':or,
devices, For parallel data transfer. Status and, its
turned on as a "I" until all bits have been triecl.'The
'compliment Status indicate when the conversion is
parallel 'data output is not available for transfer: ,to
,:c9'mpiete. For serial data transfer. the Clock Out signal'
external devices until the Status output changes from ':,',,:1t,;lrls on the trailing edge of the Convert Command; and
logic "I" to logic " 0 " . . .
sedal data is valid before the positive going edge of the
CIQckOut signal, The Clock ceases operation when the'
Serial data is only available during conversion. and must
be transferred to external devices with the Clock and'
conversion is complete. There will be one more clock,
pulse thar! the number of bits converted (ft:solution).
Statu's signals beginning with the first clock pulse
following a change in Status from logic "0" to logic "I".
Figure 1. shows the timing details of the ADC60.

:.::CCH .,.

Convert

I

gl~t

--fl:

Status

-,

1

I

-

IT11-

'.

I

LT=-"'----l'

-t ... DlY

I ...
I
I

I

Bit 1 (MSB[ : _ -

,I'

I
I

I

I

-..I

....... "2

11I
I

r-Tcw

n ~I---~

~T3H

'

I
I
: - - T SET
I I
If-l-~,------;
T3l-l ~
I
'------

T CT

'

Bit 1

I

~.~-U- _
I
,u
I

I

1

I

---------~-t.1

III

n ..
n
: ~t----j I

,I

.f _-_-,1']
I

:

I

-!

TCP'---'

I

I

T::: =::::::::.:. :.:.:. -:1
I

,81t3

I

I

hi.

:n
I

'II
I

Serial Out

Bit2

T CCl

~ ..." ".'

Command

I

:-_- ~t!:!.-:;!..- _Ji

Bit N

I

I

I

I

::.: +:: ~~!O';-----""I,..,---cl ..f---:-:.....,,------:-----

==

BitN(lSBC:

~-:.:: ~.J
I

~ ..I---;I;------"iT':-"T:''-:--I
~L.-T4
~'~I~:--"':".---

I
'I

I'

=,::. -::. ::':1

I '

,n---ii:_..:.._____

FIGURE L ADC60 Timing Diagram.
J'ABLE I. Switching Characteristics.
PARAMETER
SYMBOL
TCT

DESCRIPTION
Conversion,1.'ime • 12,B\t
10 Bit
8 Bit

MIN.
2.50
1.20
0.80

TYP.
3.45
1.83
0.84

MAX.
3.50
1.88
0.88

UNITS

TCCH

Width of Convert Comrtuind Pulse

30

---

---

nsee

TCCL

Intemal Between Convert Command Pulses
(TCT + TI + T DLy)

T1

D.lay From Trailing Edge of Conv. Command
To Leading Edg. of Clock Out

,30

41

60

....c

T2

D~lay

from Conv. Command To R.set

:16'

40

68

nsec

T3H

Delay From Valid High Output To Trailing'
Edge of Clock Out

22

43

70

osee

T3L

Delay From Valid Low Output To Trailing
Edg. of Clock Out

30

51

72

nsec

T4
T DLy

D.lay From Valid Data 'to STATUS LOW

12

18

37

nsec

Delay From Clock Out to S-TATUS HIGH

22

44

60

nsec

60

nsec
osec

TSET
TCW

Setup Tlnle from Status to Conv. Command" (2)

TCp

Clock Ont Period· (3)

Clock Out Width
12 Bit
10 Bit
8 Bit

NOTES: 1. ADC60 internal clock may be inhibited !>y returning the

convert command to "I". By this technique, the converter
may be cycled through an entire convenion one clock pulse
at a time. This technique allows the conversion time to be extended ,to' Virtually any conversion- time.
-

5~14

",""C

lASec
lASec

(I)

0

--

40

50

192
104
88

265
165
9S

"

270

risec

171

osec
_c

98

2. The convert· command may rise as soon as the
lut clock out pulse riSes.
; ,,,
3. Th. clock period for ADC60 ia riot n.c_arily

constll:ntthroughout the ~nvenion time.

SPECIFICATIONS
ELECTRICAL

MECHANICAL
NOTE:
Lead, in true position Within .015"
L38mm) R @MMC at teating plane.

Typic:al at 250 (; and rated power supplies unless otherwise "9ted.

I
I

MODEL
RESOLUTION

ADC80-08
8

I
I

ADC60-10
10

I
I

ADC811-12
12

I
I

UNITS

Bits

r-

INPUT
ANALOG INPUTS
±2.S, :!:5, ±10
o to +5, 0 to +10, 0 to +20
0.2

V
V
kilN FSR

Positive Pulse 30nsec wide min. Trailing
edge ·"1" to "0" initiates conversion.
2

TTL Loads

Voltage Ranges, Bipolar
Voltage Ranges, Unipolar
Impedance

Logic Loeding ..
ERROR(2)

Differential linearity Error. max
Monotonicity

.:to.2
:to.2
:to. 195
:to.19
:to.27

No Missing CQ

TYPICAL
INPUT SIGNAL SYSTEM THROUGHPUT
SYSTEM ACCURACY
RANGE (volts)
SAMPLING RATE (max)
*RSS

•

t10
Oto+10
.±10
o to +10
:!:.10
to +10

o

200kHz
22(lkHz
325kHz
370kHz
530kHz
625kHz

:!:.0.04%
:!:.0.04%
:!:.0.125%
:!:.O,125%
:!:.0.25%
:!:.0.25%

-

... RSS - Root Sum Squared. ,

5-18

BURR-BROWN@

ADC71

IE'lE'lI

16-Bit Hybrid
ANALOG-TO-DIGITAL CONVERTER
FEATURES:

DESCRIPTION

• 16-BIT RESOLUTION

The ADC71 is a low cost. high quality. 16-bit s.uccessive approximation analog-to-digital converter. The
ADC71 uses state-of-the-art IC and laser-trimmed
thin-film components and is packaged in a convenient 32-pin dual-in-line package. The converter is
complete with internal reference. short cycling capabilities. and thin-film scaling resistors. which allows
selection of analog input ranges of ±2.5V. ±5.0V.
±IO.OY.O to +5.0V. 0 to +IOY and 0 to +20\1.

• LINEARITY ERROR ±D.003%
• COMPACT DESIGN
32-Pin Ceramic Package
• FAST CONVERSION SPEED
• LOW COST

Data is available in parallel form with corresponding
clock and status output. All digital input and outputs
are DTL/TTL compatible.
Power supply voltages are ±15YDC and +5VDC.

,----0 SHORT CYCLE
PARALLEL
DIGITAL
OUTPUT

,----0 CONVERT COMMAND

} INPUT
RANGE SELECT

t - - -.....-t----OCOMPARATOR IN
' - - - - - 0 REF OUT 1+6.3V)
1 - - - - - - - - 0 CLOCK OUT

' - - - - - - - - - - - - - - - 0 STATUS

. International Airport Industrial Park· P.O. Box 11400· Tucaan. Arizona 85734· Tel. (602) 746·1111 • Twx: 910-952·1111 • Cable: BBRCORP· Telex: 66-6491

5-19

SPECIFICATIONS
ELECTRICAL

..

Typical at +2SOC and rated power supplies unless otherwise noted'

I

MODEL

ADC71KG

1 MIN I

I

RESOLUTION

UP

I

r

MAX

I

16.

I
I

,

ADC;7~JG

~·,·.I.

MIN

1

.,

::, . r

MAX
16'

I
,I

.. ,'UNITS

Bits

~.'

ANALOG INPUTS
'.

Voltage Ranges

Impedance I Direct Input

,.

,:, .. ,

±2.5, ±5, ±10
o to +5, 0 to +IQ,
p to +20

Bipolar
Unipolar

±2.5, ±5, ±10

.V

Oto +20

V

2.5
5

kll
, kn~:.
kll

o to +5. 0 to +10,

I

o to +5V, ±2.5V
o to +10V, ±5.0V.
o to +20V, ±10V

2.5
5
10

'io

DIGITAL INPUTS(1)
Convert Command

POSirve pulse SOnsee jide I min 1 triiHng edge,
1

Logic Loading

"I" t~ "0" initiates conversion
. '

I

TTL Load

1

TRANSFER CHARACTERISTICS
ACCURACY
±O.1(2)

Gain Error

±:O.1(2)

±0.2

±0.2

Offset
±O.05(2)
±0.112)

Unipolar

Bipolar

±0.05(2)

±0.1
±0.2
±0.003

linearity Error
±0.003

±112
±O.003

0.003
0.001

0.003
0.001

±1/2

Inherent Quantization Error
Differential Linearity Error

±0.1.
±0.2
±0.006

±O.1(2)

%
I ..

% of FSR(3,
%of FSR
%of FSR
LSB
%of FSR

POWER 'SUPPLY SENSITIVITY
±15VDC
+5VDC

CONVERSION TIME('). 14 Bits·

%olFSRI'IIIVcc
%01 FSRI'IIIVcc
50

50

WARM-UP TIME

,usee
min

5

5

DRIFT
±15

Gain

::15

ppmfOC

Offset
±2

Unipolar
Bipolar
Linearity
No Missing Codes Temp Range
KG , 14·bit
JG , 13·bit

±4
±10
±3

±2
+10

=2

=4
±10

~2

+40

=3
~

50

0

ppm of FSRfOC
ppm of FSRfOC
ppm of FSRfOC
°C
°C

OUTPUT
DIGITAL DATA
All codes compleme~tary
Parallel
Output CodesiS)

I

I

Unipolar

I

I

jB
COB, CTC(6)
2
Logic "1" during conversion
2

Bipolar
Output Driv,
Status
Status Output Drive

TTL Loads
2

TTL Loads

2

TTL Loads
kHz

6.6

V

±200
:tl0

ppmfOC

Internal Clock

Clock Output Drive
Frequency

2
280

INTERNAL REFERENCE VOLTAGE

6.0

6.3

280
6.6

6.0

6.3

Max External Current
±2oo
±10

with No Degradation of Specs
Temp Coefficient

~A

POWER SUPPLY REQUIREMEN:rS
Power C,onsumption
Rated Voltage, Analog
Rated Voltage, Digital
Supply Drain +15VDC
Supply Drain '15VDC
Supply Drain +5VDC

±14.5
+4.75

TEMPERATURE RANGE.,
Specification
Operating I derated specs
Storage

,

0
·25
'55

1.55
±15
+5
+45
·35
+70

±15.5
+5.25

±14.5
+4.75

+70
+85
+125

0
·25
·55

5-20

1.55
±15
:\'5
+45
·35
+70

W
±15.5
+5.25

+70
'+Q5
'. ;1-125

VDC
VDC
mA
mA
mA
°C
°C
9C

NOTES:
1. DTlITTl compatible, i.e., logic "0" =0.8V, max. logic "1" = 2.0V, min for inputs. For digital outputs logic "0" = +0.4V, max. logic "1"'; 2.4V, min.
2. Adjustable to zero.
,
.
3. FSR means Full Scale Range. For example, unit con~ected for ±10V range has 20V FSR.
4. Conversion time may be shortened with "Short Cycle" set for lower resolution, see ~'Additional Connections Required" section.
5. See Table I. CSB - Complementary Straight Binary. COB - Complementary Offset Binary. CTC - Complementary Two's Complement.
6. CTC coding obtained by inverting MSB ,Pin 1 •.

MECHANICAL

DIM

C

INCHES
MIN

MILLIMETEAS

1120

1.160

.110

.23

r

i

-"-

L
~

0.89
127
2.MeASIC
2.79

3.81
,gOOI!lASIC

.002

,

.010

CASE: Ceramic

................

MATING CONNECTOR:
2302MC
WEIGHT: 13 crams 0.46 oz.

P,n '''''''''e'' ilhown 10' ,.Ie ••"".o,,'v
N""'t>e,.,,,.vnO'''.''''a.ke,tonpuk.ge

r:==r;j~1L

' . . . . . . . . . . . . . ::

!---:l

~~;~-j:U"OS~"ON:';J Nt--L-GJL"~"

22.86 eASIC
0.0&

.130

010" I

2Smm'"

~MMC

AT SEATING PtAII,IF

,

CONNECTION DIAGRAM
TOP ViEW
SHORT CYCLE

,MSB, Bit 1

CONVERT COMMAND·

Bit2
Bit3

+5VDC SUPPLY

Bit4

GAIN ADJUST

Bit5

+15VDC SUPPLY

Bit6

COMPARATOR IN

Bit7

BIPOLAR OFFSET

BitS

'10V

Bit 9

20V

Bit 10

REF OUT 6.3V

Bit"

ANALOG COMMON

Bit 12

-15VDC SUPPLY

,lSB for 13 bits, Bit 13

CLOCK OUT

,lSB for 14 bits, Bit 14

DIGITAL COMMON

Bit 15

STATUS

Bit 16

NC

·If an external clock is used. connect the clock to pin 31 CONVERT COMMAND.

TYPICAL PERFORMANCE CURVES
GAIN DRIFT ERROR, % FSR VS
TEMPERATURE

POWER SUPPLY REJECTiON VS
POWER RIPPLE FREQUENCY

,

0.1

/

0.06
-15VDC

0.04

Y

0.02
0.0 1

~

~ 0.006
~

0.004

ffi

0.002

'0
i'

0.001

u.

_250

o

+700

+250
Temperature

rOC

+850

/
~

V

10

100

5VDC

1k

Frequency! Hz I

I

5-21

J

I

t
1

J

+15VDC

V

10k

100k

DISCUSSION OF
PERFORMANCE

0000...0000
0000...0001

The accuracy of a successive approximation AI D converter is described by the transfer function shown in
Figure I. All successive approximation A/ D converters
have an inherent Quantization Error of ± 1/2 LSB. The
remaining errors in the Ai D converter are combinations
of analog errors due to the linear circuitry, matching and
tracking properties of the ladder and scaling networks,
power supply rejection, and reference errors. In summary,.these errors consist of initial errors including Gain,
Offset, Linearity, D.ifferential Linearity, and Power
Supply Sensitivity. Initial Gain and Offset errors may be
adjusted to zero. Gain drift over temperature rotates the
line (Figure I) about the zero or minus full scale point (all
bits Off) and Offset drift shifts the line left or right over
the operating temperature range. Linearity error is unadjustable and is the most meaningful indicator of AI D
converter accuracy. Linearity error is the deviation of an
actual bit transition from the ideal transition value at any
··Ievel over the range of the A. D converter. A Differential
Linearity error of± I 2LSB means that the width of each
bit step over the range of the A D converter is I LS B,
±I 2LSB.

0111...1101
0111...1110
011 Ll111

h

t---....;...j.'J~---l!~+-I

1000... 0000
1000...0001
1111...1ItO
ltll ... 1lll

Ollset

:
I

;?:Erro\

f Eo

I

~~ EinON:

+~SR ·tLSB

.FSR ' \

Analog Input
ElnOFF
'See Table I lor digital code dellnltlons.

T

2"

FIGURE I. Inp~t vs Output for an Ideal Bipolar Ai D
Converter.
antees that this converter will have no missing. codes over
a specified temperature range when short cycled for 14bit operation.

TIMING CONSIDERATIONS
The timing diagram (Figure 2) assumes an analog input
such that the positive true digital word 1001 1000 1001
0110 exists. The output will be complementary as shown
in Figure 2 (0110 011101101001 is the digital output).

The ADC71 is also Monotonic. assuring that the output
digital code either increases or remains the same for
increasing analog input signals. Burr-Brown also guar- .

Convert
Command lll
Internal Clock
Status IEOC)
MSB
Bit 2

===J

Bit 3

~'T

Bit 4
Bit 5

-- ~J __~__-=I"O="~----------~----------------~~,

Bit 6
Bit 7
Bit 8

=__ J

--]

~

1"0"

~"1"

___ ..,.J-----'------,~"I"

=-=--=-J

LJ"I"

___ J~----------------~I·=·O"~~================~~

Bit 9

==-=J=r--___________--=LJ==;"I"

Bit 10
Bit 11
Bit 12

===J

LJ"I"
I

---J

Bit 13
Bit t4
Bit t5

~~t~o6nal
External
Clock

"0"

___ J
LJ"I"
___
J~--------------------------------~I"O="~~~~~
=-=-_-J
1"0"
~
=-:::=- -I
l..!:!!J
--I[-l i---' ;-1 r-l r-l r-l r-1 r--, r-l r-l r-l r-l i-l r-i'r~l r-l r-j r-~ t

lO0nsec. max -.j

I-J

1_

!,.,..

LJ

I...J

\...J

l-l

L...l

L.J

L..J

L.J

L..J

,--J

LJ

t~1

NOTES:
1. The convert command must be at least 50nsec wide and must remain low during a
conversion. The conversion is initiated by the "trailing edge" 01 the convert command.
2. 57 "sec lor 16 bits.

FIGURE 2. ADC71 Timing Diagram.

5-22.

1_1

~LJ

I..J

DEFINITION OF DIGITAL CODES
PARALLEL DATA
Two binary codes are available on the ADC71 parallel
output; they are complementary (logic "0" is true)
straight binary (CSB) for unipolar input signal ranges
and complementary offset binary (COB) Jor bipolar
input signal ranges. Complementary two's complement
(CTC) may be obtained by inverting MSB (Pin I).

Table I shows the LSB. transition values. and code definitions for each possible analog input signal range for
12-. 13- and 14-bit resolutions. Figure 3 shows the connections for 14-bit resolution. parallel data output. with
±IOV input.

: Boned iinis-a~e- - - : extarnal connections.

,,,

;::::

+SyoC

~

,
,,

CI

+15VoC

I

10k!! 10
IOOkn

r--

,

GAIN
ADJUST

10k!! 10
lOOk!!
I"F

OFFSET
ADJUST

ADCII

r---

I"F

I

I

I

."

ANALOG
COMMON
·15YOC

I"F

I

DIGITAL
COMMON

'--_ _ _ _- STATUS OUTPUT 10
r
CONTROL LOGIC

• Capacllor should be connected even If external glln adlust Is not used.

FIGURE 3. ADC71 Connections For: ±IOV Analog Input. 14-Bit Resolution (Short-Cycled). Parallel Data Output.
TABLE I. Input Voltages. Transition Values. LSB Values. and Code Definitions.
Binary I BIN,
Output
Analog Input
Voltage Range

INPUT VOLTAGE RANGE AND LSB VALUES

One Least
Significant
Bit ILSBI

±'OV

±SV

±2.5V

o to +'ov

·Oto+5V

Oto +20V

COS'
orCTC"

COS'
orCTC"

COS'
orCTC"

CSS'"

CSS'"

CSS'"

20V

'OV

5V

'OV

2"
'.22mV
6'0"V
305"V

Tn"

Tn

2.44mV
'.22mV
6'0"V

2.44mV
'.22mV
6'0"V

'.22mV
6'0"V
305"V

Defined As:

Code
Designation
FSR

2"

2"

n= '2
n ='3
n ='4

4.BBmV
2.44mV
'.22mV

20

SV'

~
2"
4.88mV
2.44mV
'.22mV

Transition Values
MSS LSS
000 .. 000 ....
0'1...'"
"1..."0

+Full Scale
Mid Scale
-Full Scale

+'OV ·3/2LSS +5V ·3/2LSS +2.SV ·3/2LSE 'OV ·3/2LSS +SV ·3/2LSS +20V ·3/2LSS
0
+5V
0
a
+2.5V
+'OV
0+ '/2LSS 0+ '/2LSS
-tOY +'/2LSS -5V +'/2LSS -2.5V +'/2LSS 0+ '/2LSS

'COS = Complementary Offset Sinary
"eTC = Comp!ementary Two's Comp.lement - obtained by
inverting the most significant bit. MSB I Pin 11

,·"CSB = Complementary Straight Binary
.... Voltages given are the nOl'l1inal value
for transition to the code specified.

5:-23

cc:

DISCUSSION OF SPECifiCATIONS·
connecting external trim potentiometers. as shown in
Figures 6 and 7.
POWER SUPPLY SENSITIVITY
'Changes in the DC powersupplies·will affect accuracy.
'The ADC71 power supply sensitivity is specified' for
±o.OO3%ofFSR/%Vcc, for±15V supplies and ±o.OOI 5%
of FSR/%Vcc for +5V supplies. Normally, regulated
powet supplies with 1% or less ripple are recommended
for use with this ADC. See layout Precautions. Power
Supply Decoupling and Figure 4 .

The ADC71 is specified to provide critical performance
criteria for a wide variety of applications. The most critical.specific;ltions for. an AI Dconverter are linearity.
drift; gain and offset errors. and conversion speed effects
on accur/lcy .This ADC is factory trimmed and tested for
alIcritical key specifications.
GAIN AND OFFSET ERROR
Initial Gain and Offset errors are factory trimmed to
typically ±O.l% of'FSR (typically ±0.05% for unipolar
. ' offset) at 25"C. These errors may be trimmed to zero by

LAYOUT AND OPERATING INSTRUCTIONS
LAYOUT PRE~AUTIONS
Analog and digital c.ommon are not conpected internally.
in the ADC71 but should be connected together as close
to the unit as possible. preferably to a large pfane under
the ADC. If these grounds must be run separately. use
wide conductor pattern and a 0.0 1f.l F to 0.1 f.l F ~onpolai
ized bypass capacitor between analog and digital commons at the unit. low impedance anaiog and digital
common returns are essential for low noise performance.
Coupling between analog inputs and digital lines should
be minimize.dby c[lreful layout. The comparator input
(Pin 27) is extremely sensitive to noise. Any con.nection to
this point should be as short as possible and shielded by
Analog Common or ±15VDC supply patterns.

. ize the converter after power is applied.

INPUT SCALING
The analog input should be scaled as close to the maximum input.signal range as possible in order to utilize the
maximum signal resolution of the AI D converter. Connect the inp.ut signal as shown in Table II. See Figure 5 for
circuit details.
T A!JLE II. ADC7l Input Scaling ConnectiQns.
Connect
Input·.
Signal
Range
±1OV
±5V
±2.5V
Oto+5V
o to +10V
to +20V

POWER SUPPLY DECOUPLING

The power supplies should be bypassed with tantalum
. capacitors as shown in Figure 4 to obtain noise free
operation. These capacitors should be located close to the
ADC.

o

Connect
Output
Code
• COB or CTC'
COB or eTC'
COB or CTC'
CSB'
CSB
CSB

Pin 26
To Pin

Connect
Pin 24
To

Input
Signal
ToPin

27
27
27
22
22
22

Input Sig .
Open
Pin 27
·Pin27
Open
InputSig.

24
25
25
25
25
24

Obtamed by Inverting MSB •Pm t '.

·15VDC

+5VDC

It·-@
I
~~.----~--~----~~
~

1.F

DIGITAL COMMON

..

@~-+!-{.;\

I

1.F

+.

ANALOG
COMMON

DIRECT
INPUT

..

~---+-----<~

1+

1.F

~

..

®------...--+-15-V~DC

COMPo ":'
IN 27'}------1----~

~

FIGURE 4. RecoJ"flmended Power Supply Decoupiing.

BIP~~.R
+VREF
OFFSET

CONVERTER INITIALIZATION
On power-up, the state of the ADC internal circuitry is
indeterminate. One conversion cycle is required to inltial-

FIGURE 5. ADC71 Input Scaling Circuit.

OPTIONAL EXTERNAL GAIN AND OFFSET ADJUSTMENTS
Gain and Offset errors may be trimmed to zero using
external gain and offset trim.potentiometers connected to
the ADC as shown in Figures 6 and 7. M ultiturn potentiometers with 100ppm "c or better TCR's are recommended for minimum drift over temperature and time; ;
Thesepots may be any value from 10kUto fOOkH. All
resistors should be 201/( carbon or better. Pin 29 (Gain

5-24

Adjust) and Pin 27 (Offset Adjust) may be left open if no
external adjustment is required.
ADJUSTMENT PROCEDURE
OFFSET - Connect the Offset. potentiometer (make sure
'R, is as clQse to pin 27 as pos$ible) as shown in Figure 6.
Sweep the input through the end point transition voltage

that should cause an output transition to all bits off
(E'\I~").

Adjust the Offset potentiometer until the actual end point
transition voltage occurs at E'\\". The ideal transition
voltage values of the input are given in Table I.
fal

+15VDC

®

I.8Mn

..,..,...

IDkn to 100kU

~

COMP.IN
OFFSET ADJUST

used. The external clock pulse must be a negative going
pulse with a width between 100nsec and 200nsec as shown
in Figure 2. and must be at a lower fre4uency than
the internal clock.

ADDITIONAL CONNECTIONS REQUIRED
The ADC71 may be operated at faster speeds for resolutions less than 14 or 13 bits. depending on the model
selected. by connecting the Short Cycle.lnput. pin 32. as
shown in Table III. Conversion speeds. linearity, and
resolutions are shown for reference.
TABLE III. Short Cycle Connections and Specifications
for 12- to 14-Bit Resolutions.

·15VDC
+15VDC

fbi

Resolution (Bits)

16

14

13

12

Connect Pin 32 to

Open

Pin 15

Pin 14

Pin 13

Maximum Conversion
l~sec){l)

57

50

46.5

43

ax mum on near y
al2S0C I%of FSR)

0.()()3(2)

0.00312)

0.006(3)

0.00613)

Speed

18Dkn

27

ISOkn
IDkulo IDDkn

CDMP.IN

NOTES:
1. Max. conversion time to maintain specified nonlinearity error.
2. ADC71 KG only.
3. ADC71 KG or ADC71JG.

22kn
OFFSET ADJUST
·15VOC

-=.E:-

FIGURE 6. Two Methods of Connecting Optional
Offset Adjust.

GAIN - Connect the Gain adjust potentiometer as shown
in Figure 7. Sweep the input through the end point transition voltage that should cause an output transition to all
bits on (E?:~). Adjust the Gain potentiometer until the
actual end point transition voltage occurs at E't~.
Table I details the transition voltage levels re4uired.

+15VDC

!

f

27Dk!!
10k!l to
~'100k!l

GAIN ADJUST

..,.. 0.01 ~F
ANALOG COMMON

@J

OUTPUT DRIVE
Normally all ADC71 logic outputs will drive two standard
TTL loads: however, if long digital lines must be driven.
external logic buffers are recommended.
HEAT DISSIPATION
The ADC7l dissipates approximately 1.55 watts (typical)
and the packages have a case-to-ambient thermal resistance (01.\) of 25"C W. For operation above 70"C. OL\
should be lowered by a heat sink or by forced air over the
surface of the package. See Figure 8 for 0, \ re4uirement
above 70"('. If the converter is mounted on a PC card.
improved thermal contact with the copper ground plane
under the case can be achieved using a silicone heat sink
compound. On a 0.062" thick PC card with a f6 s4uare
inch (min.) area. this techni4ue will allow operation to
85'"C.

GAIN AOJUST
.15VOC

25+----""""'"

FIGURE 7. Connecting Optional Gain Adjust.
60

EXTERNAL CLOCK
If an external clock is used. connect the external clock to
convert command. pin 31. The convert command shown
in Figure 2 is not used. After each conversion is completed. a new conversion cycle will automatically start on
the first falling edge of the external clock following the
completion of conversion. The clock out signal will
remain as shown in Figure 2 even if an external clock is

70
80
90
Amblenl Temperature lOCI

FIGURE 8. Oe.\ Re4uirement Above 70"('.

5-25

qRDERINGINFORMATION
MODEL
ADC71KG
ADC7IJG.

TEMPERATURE
O"C to +70"C'
O"C to +70"C

PACKAGE
Ceramic
<;'eramic

BURR-BROWN®

ADC72

IElElI

16-Bit Hybrid
ANALOG-TO-DIGITAL CONVERTER
FEATURES:

DESCRIPTION

• 16·BIT RESOLUTION

The ADC72 is a low cost. high quality. 16-bit
successive approximation analog-to-digital converter. It uses state-of-the-art IC and laser-trimmed thinfilm components and is packaged in a compact 32-pin
metal dual-in"line package. The converter is complete
with internal reference. clock. comparator. and thinfilm scaling resistors. which allow selection of analog
input ranges of ±2.5V, ±5V, ±IOV; 0 to +5V, 0 to
+ IOV and 0 to +20V .
Data is available in parallel form with corresponding
click and status output. All digital input and outputs
are DTL/TTL compatible.
Power suply voltages are ±15VDC and +5VDC.

• ±D.OO3% MAXIMUM NONLINEARITY
• COMPACT DESIGN
32-Pln Hermetic Matal Package
• FAST CONVERSION SPEED
5O~ai: Maximum
• LOW COST

, - - - 0 SHORT CYCLE
PARAllEL
DIGITAL
OUTPUT

',...---0 CONVERT COMMAND

} INPUT
RANGE SELECT

t - - -.....-r----OCOMPARATOR IN
' - - - - - 0 REF OUT 1+6.3VI
1 - - - - - - - - , . . _ 0 CLOCK OUT

' - - - - - - - - - - - - - - - 0 STATUS

International Airport Indullrlal Part . P.O. Baxl,l400 ••Tut;IDn. Arizona 85734· Tel.l602J 746·1111 • Twx: 9111-952·1111 . Cable: BBRCORp· Telex: 66-6491

5-27

SPECIFICATIONS'
E~EC;TRI9~~

.,

,TYPiCal ~t":25'9 arm,~a/8d power supplies unless otherwise noted.
' !lDC72JM.KM

MOolL

I

MIN

I MAli

'/)'p ....

t

':

RES9!-UTIO!'l

t-.:,:"

INPUT'

?~

ADC72AM.".
MIN

I

TVP

16

.16

ANALOG

I

MAX'

.,

..:~1·
> ..(

,'.:

i

UNITS
Bits

j

Voltage Ranges
Bipolar
Unipolar

:'2.5; ±5. ±10
o to +5.0 to +10.
Oto +20

Impedance, Direct Input'
o to +5V. ±2.5V
.0 to +10V. ±5.0V
o to +20V. ±10V

.'

,

2.5
5

V

±2.5. ±5. ±10
o to +5. 0 to +10.
.oto.+20

V
kll
. kll
kll

2.5
5
10

.

10

f·· '.

DIGITALII)
Convert Command
Logic Loading ~

PoSiti~~ pulse 50neee wide, min trailing edge, "1" to ;'0" initiates conversion

ACCURACY
Gain error(2)
Offset Gain(2)
Unipolar
Bipolar
Linearity Error

!

KM.BM
JM.AM
Inherent Quantization Error
Differential L!nearity Error

±O.1

±0.2

±0.1

:!:0.2.

%

±O.05
:to'. 1

±O.1
±0.2
±0.003

±0.05
±0.1

±0.1
±0.2·
±O.OO3

% of FSR(3)
% of FSR
%ofFSR
1(, of FSR
LSB
.%ofFSR

%0.008

±1/2
±0.003

±O.003
±O.OOI

CONVIRSION TIME(4).14 Bits

50

DRtFT
Gain
Offset
Unipplar
Bipolar
Linearity
No Missing Codes Temp Range
JM. AM .13 bits'
KM. BM)14 bits.

±o.OO6

±O:OO3
±0.001

'.
50

10

10

WARM-UP TIME

..

"

±1/2
:!:0.003

POWER SUPPLY SENSITIVITY
±15VDC
+5VDC

TTL Load

1

1
".

TRANSFER CHARACTERISTICS

% of FSR!%') Vs
% of FSRt'IIt.1Vs
~sec

min

±10

±2O

±7

±15

ppmi"C

±2
±8
±2

±4
±10
±3

±5

±2
±10
±2

ppm of FSRloC
ppm of FSRi"C
ppm of FSRloC

+50
+40

°C
°C

2

TTL Loads

2

TTL Loads
kHz

6.6

V

±200
±5

ppmloC

+50
+40

0
+10

0
+10

OUTP!1T
DIGITAL DATA
. All codes complementary
Parallel
OutPvt CodeslS)
Unipolar
Bipolar
Output Drive
Status
Status Output Drive
Internal Clock
Clock Output Drive
Frequency

CSB
COB. CTC(S)
2
Logic "1 ,; during conversion

TTL Loads

2
2
280

280

INTERNAL REF!!RENCE .VOLTAGE
Max External·Current
with No Degradation of Specs
T emp Coe"i~ient
POWIiiR SUI'PLY RIiiQUIREMENTS
Pow~r Consumption
Rated Voltage. Analog
Rated Voltage. Digital
Supply Drain +15VDC
Supply Drain -15VDC
Supply Drain +5VDC
TEMPERATURE RANGE
Specification
Operating I derated specs
Storage

6.0

6.3

. '6.6.

6.0

6.3

,
±200
+10
1.3
±14.5
+4.75.

0
-25
-55

:t15
+5
+45.
-35
+70

±15.5
+5.25

+70
+85
+.125

.,

5:-28 .

±14.5·
+4.75

-25
-55
-55...

1.3
±IS
+5
+45
-35
+70

~A

W
±15.5
+5.25

+85
+85
+.125

VDC
VDC
rnA
mA
mA

~C
°C

.' .o.c

NOTES:
1. DTLJTTL compatible. i.e" Logic "0" = 0.8V, max. Logic "1"= 2.0V, min for inputs. For digital outputs Logic "0" = +0.4V, max. Logic "1" = 2.4V, min.
2. Adjustable to zero.
:i. FSR means Full Scale Range. For example, unit connected for ±10V range.has 20V FSR.
4. Conversion time may be shortened with "Short Cycle" set for lower resolution, see "Additional Connections Required" section.
S. See Table I. CSB - Complementary Straight Binary. COB - Complementary Offset Binary. CTC - Complementary Two's Complement.
6. CTC coding obtained by invartlng MSB I Pin 1 I.

MECHANICAL
NOTE:'

I---A--;
A

1.720

1.160

43.89

44.70

B
C

1.120
.110

1,180
.2&0

28.45
4.32

29.46
8.35

D

.018

.021

0.41

0.53

G

.100 BASIC
.100
.140

2.64 BASIC
2.54
3.68

,150
.300
.tOO BASIC

3.81
7.52
22.86 BASIC

. 100

,1.-0

2.54

I

leads in true position withtn .010"
.255mm' R at MMC at seating plane.

~~H

,
..
l,, ...............

f'in numb.'llhown for ref.rence onlV.
Number. mav not be marked on pllCk ....

CASE: Nickel-plated kovar
MATING CONNECTOR, 2302MC
WEIGHT: 13 gramIIO.46 OZ.l

)

(

Contrasting glass seal or
square corner denotes pin 1.

i1.--,
. -'

3.55

CONNECTION DIAGRAM
TOP VIEW
SHORT CYCLE

MSB Bill

CONVERT COMMAND'

Bi12
Bit3

+5VDC SUPPL Y

Bit4

GAIN ADJUST

Bit5

+15VDCSUPPLY

Bit6

COMPARATOR IN

Bit7

BIPOLAR OFFSET

Bit8

10V

Bit9

20V

Bit 10

REF OUT 6.3V

Bitll

ANALOG COMMON,

Bit 12

-15VDC SUPPLY

LSB for 13 bits Bit 13

lSB

fo~

CLOCK OUT

14 bits Bit 14

DIGITAL COMMON

Bit 15

STATUS

Bit 16

NC

'If an external clock is used. connect the clock to pin 31 CONVERT COMMAND.

TYPICAL PERFORMANCE CURVES
POWER SUPPLY REJECTION VS
POWER RIPPLE FREQUENCY

GAIN DRIFT ERROR ('III OF FSR)
VS TEMPERATURE

0.1

+0.10,....----,......-----....:.--------,---,

~+O.06

u..

/

0.06

-15V.!;C

+O·04I~~~~~illii~~iilllllll~~~1
-0.04

0.02

!!:+O.02

g

0

'0 -0.02
...

~

i

V

0.04

fl.f1:f::JIJ../o=--.,;=---+---....::",..~~~!:!oQ:~I+M'+Hf

-O.IOO·~--------_+----------~----------~~~~~--~~

~ -o.08~--------+_------~------------~~----~

-0.10 ' - - - - . . . : . . - - - - ' - - - - - - - - - ' - - - -....
c2SOQ
Mii"'O
'r""peralure (O'er

0.0 1

8.

/

0.006

/

~ 0.004

~
'0

If.

I

+15VDC

r-/

~

0.002

+SVDC
0.001
1

5-29

/

L

10

100
lk
Frequency 1Hz,

V

10k

lOOk

DISCUSSION OF
PERFORMANCE

01)00...0000

0000...0001

! : : ;: :.: ht----T.~.----;~ff+--1
fF

The accuracy of a successive approximation AI b converter is described by the transfer function shown in
Figure I. All successive approximation AI D converters
'have an inherent Quantization Error of±1/2 LSB:thi"
'remaining errors in the AI D converter are combinations
of analog errors due'to the linear circuitry. matching and
tracking properties of tAe ladder and scaling networks.
.' power supply rejection. and reference errors. In summary;
; these' errors consist of initial errors including Gail?
Offset. Linearity. Differential Linearity. and Power
Supply Sensitivity. Initial Gain and Offset errors may be
adjusted to zero. Gain drift over temperature rotates the
line (Figure I) about the zero or minus full scale point (all
bits Off) and Offset drift shifts the line left or right over
the operating temperature range. Linearity error is
unadj,ustable ,and is the most meaningful indicl\tor of
AI D converter accuracy. Linearity error is the deviation
of an actual bit transition from the ideal transition value
at any level over the range of the AI D converter. A
Differential Lint!arity error of ± Ii 2LSB means that the
width of each bit step overthe range of the AI D'converter
is ILSB. ±1;2LSB.
The ADC72 is also monotonic. assuring that the output
digital code either increases or remains the same for
increasing analog input signals. Burr-Brown also guar-

~
i§:

~

is

1000...0000

1000...0001
1111...1110

1111 ...1111

I

Offset

I

Erro
\

I
I

~

~~ ElnON!

·FSR "\
Analog Inpul
2
~Off
'See Table I for digital code detlnilloni.

~ .1 LSB
2

FIGURE I. Input vs Output for an Ideal Bipolar A D
,Converter.

.'

.

.

TIMING CONSIDERATIONS
The timing diagram (Figure 2) assumes an analog input
such that the positive ,true digital word 1001 1000 1001
0110 e,xists. The output will be complementary as'shown
in Figure 2 (OlIO 01110110 1001 is the digital output).

Convert
Command l11
Internal Clock
Statui IEOCI
MSB
Bit 2
Bit 3

___ J

L-j"I"

~J _______:=I"O="~~~--~77~----------------~rr-- -'J
1"0"
r---~--~---='
~~~====~===============~
===J
Lj"'I"

Bit 4
Bit 5
Bit 6
Bit 7
BitS

==='J----------------.~r. I~
=__ J
L_h"
r----~-------.:::::..2'-,-..:::;t:,':;--'r::::::::::::::=:::::::===::::::::::===:::!"-~
==_J
;
.
Lj"l"
=__
.
.. - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Bit 9

]

Bit to
Bit II
Bit 12

"

1"0"

~J~--------------~--~------~L_JrI~
.. ------~-----------

===J~

===J
-- J

Bit 13
Bit 14',
Bit 15

____~--------__----__--~==~~
. o·~'========~r---U"I"
1"0"

r--

--- ~---.."..---~-~----.:..-----,.-='::::::;:;:-----;'
1"0"
r__ ' '

=~_-J

, BII16
Optional EKlemal
Clock

l...!!!j"I"
,
===JltJ-1J-Lf~1f-lr·~1r-lr~lf-~Lf~1r:·~·lr-:lr~lf-lf~..,-r-·l~r~lJ-1t.-'
'" ,.
,' '
, .."
,
'
--

II

.

.

antees, that these converters will have no missing codes
over a specified temperature range when short-cycled for
14-bit operation.
'

.

"

.

200nsec. max - _ I i _ N O T E S : '
,'~,", ,
1. The IlIIIIvert command mUll bnt'latst 5OilaIC'wide and mUll remain low during a
convirslen. the conversion is Inlliated bv lhe, '1ralling edge" of Ihe convert command.
2.57,.aec lor 16 bill.
3. Use trailing edge of clock to: stl1!be aerial oulput

FIGURE 2. ADcn Timing Diagr.am.,

5-30

DEFINITION OF DIGITAL CODES
PARALLEL DATA
Two binary codes are available on the ADen parallel
output; they are complementary (logic "0" is true) straight
binary (CSB) for unipolar input signal ranges and
complementary offset binary (COB) for bipolar input
signal ranges. Complementary two's complement (CTC)
may be obtained by inverting MSB (Pin I).

Table I shows the LSB. transition values. and code
definitions for each possible analog input signal range for
12-. 13- and 14-bit resolutions. Figure 3 shows the
connections for 14-bit resolution. parallel data output.
with ±IOV output.

: o;u.d Hnn-aie- --,, .eX1ernal connllCllans.

>-+---,,,,.,..._________

,,,

-~--_<

+5VDC

,

}------I---~t_--+_----_-~t_----<+15.VDC

101m to

r--

lOOkll
GAIN
L--_~S ADJUST

I

1...---

IDklllo

L-_ _,--_+__-+____~~IOOkn
OFFSET
ADJUST

ADcn

r--I

I
I

ANALOG

}---------~--+--~----~-I~I'~F~---,~·COMMON

r------------+----.. . .

~----'---< ·15VDC

I

DIGITAL
'--_ _ _ _- STATUS OUTPUT to
r
CONTROL LOGIC

NC

~"

1.6

. COMMON

_ _ _ _ _J'../

• Capacitor should be connllCled lVen II external gain adlusl is not used.

FIGURE 3. ADCn Connections For: ±IOV Analog Input. 14-Bit Resolution

(Short-C~c\ed).

Parallel Data Output.'

TABLE I. Input Voltages. Transition Values. LSB Values. and Code Definitions.
Binary ,BIN
Output

Analog Input
Voltage Range

INPUT VOLTAGE RANGE AND LSB VALUES

Defined As:

Code
Designation
One Least
Significant
Bit rLSBI

FSR

±10V

±5V

±2.5V

Oto+l0V

o to+5V

Oto +20V

COBlt,
or CTCI21

COBlt,
orCTCI2,

COBI'I
orCTCI2,

CSBI3,

CSBI31

eSB(3,

20V

10V
2n
2.44mV
1.22mV
610l'V

5V
2n
1.22mV
61Ol'V
3051'V

10V

5V

Tn"'"

Tn

n'" 12
n '" 13
n'" 14

4.88mV
2.44mV
1.22mV

2"

Tn

2.44mV
1.22mV
61Ol'V

1.22mV
61Ol'V
3051'V

~

2n
4.88mV
2.44mV
1.22mV

Transition Values
MSB LSB
000 ... 00014'
011...111
111...110

+Full Scale
Mid Scale
-Full Scale

+ 1OV -3/2LSB +SV -3/2LSB +2.SV -3/2LSe 10V -3/2LSB +SV -3/2LSB +20V -312LSE
0
0
+SV
+10V
0
+2.SV
-10V +1/2LSB -SV +1/2LSB -2.5V +1/2LSB 0+ 1/2LSB 0+ 1I2LSB 0+ 1/2LSB

=

(1'COB Complementary Offset Binary
121 CTC '" Complementary Two's Complement - obtained by
inverting the most significant bit. MSB (Pin 11

5-31

13, CSB '" Complementary Straight Binary
(4) Voltages given are the nominal value
for transition to the code specified,

DISCUSSION OF
SPECIFICATIONS

:qONVERTEfll,UTIALlZATION,... .
'. <'
On' power-up,tlie state ~tthe'ADb internal~lrcui61' is'
indeterminate. One conversion cycle is required to initialize the converter after power is applied.

The ADC72 is specified to provide critical performance
criteria for a wide variety of applications. The most
critical specifications f~r an AI D converter are linearity,
dr'ift,gaiil and offset errors, and conversion speed effects
on ac;curacy. This ADCis factory~triirimed and tested for
.all critical key specifications.

INPUT SCALING
The analog input shoUld be' scaled as close to the
maximum ihput'signal range as possible in. order to utilize
the maximum signal resolution'· of the AI D converter.
Connect the input signal as shown in Table il. See Figure
S for circuit details.

GAIN AND OFFSET ERROR
I nitial Gain and Offset errors are factory-trimmed. to
typicalfy :to. I % ofFS R (typically ±O.OS% for unipolar
offset) at 2S"C. These errors may be trimmed to zero by
connecting external trim potentiometers as shown in
.
Figures 6 and 7.

TABLE II. ADC72 Input Scaling Connections.
Input
Signal
Range

POWER SUPPLY SENSITIVITY
. Changes in the DC power supplies will affect accuracy.
The ADCn- power supply sensitivity is specified for
±O.OQ3% of FSR/%.1 Vs for ±ISV supplies and ±O.OOI%
of FSRi%.1Vs for '+SV supplies. Normally, regulated
power supplies with 1% or less ripple are recommended
for use with this ADC. See Layout Precautions, Power
Supply Decoupling and Figure 4. .

±10V
±5V
±2.5V
o to +5V
oto +10V
Oto +20V

Output·
Code
COB or CTC'
COBorCTC'
COBorCTC'

cse
cse··

CSB

InputSig.
Open
Pin 27
Pin 27

Open
Input Sig.

24
25
25
25
25
24

COMP.!
IN

~.

BIP:O:-~!1
OFFSET

OPTIONAL EXTERNAL GAIN
AND ,OFFSET ADJUSTMENTS

The power supplies should be bypasged with tantalum
capacitors as shown in Figure 4 to obtain noise free
operation. Thesl; capacitors should be located close to the: .
ADC.

.

·15VDC

@)....,-~1~IMF ANALOG

@--'I'4'~+__CD~~~MQN
IMF

•
@)r-.----+1-5...VDC~

+VREF

FIGURE.S. ADC72 Input Scaling Circuit.

POWERSUPPL Y DECOUPLING

e-

27
27
27
22
22
22

'Connect
Input
Signal."
TO Pin

DIRECT
INPUT

LAYOUT PRECAUTIONS
Analog and digital common are .not connected internally
.in the ADC72 blltShould be connected together as close
to the unit as possible. preferably to a larg~ plane under'
the ADClf ih~se g{oUn~S, mus.t be run sel'arately, use
wide conductor pattern and a O:OI~F to O.I~F nonpolarized bypass capacitor between analog and digital
~.orn.mons at the unit.. Low impedance analog al)d digital
common returns are essential for low. noise performance.
Coupling between analog inputs and digital lines should
be minimized by careful layout. The comparator input
(Pin 27) is extremely sensitive to noise. Any connection to
this point should be as short as possible and shielded by
Analog Common or ±ISVDC supply patterns.

:p

Connect
Pin 24
To

Obtained by inverting MSB ' Pin 1 .

LAYOUT AND,OPERATING
INSTRUCTIONS

-t6VDC

Connect.
Pin 26
T';Pin

Gain and Offset errors may be t~iinmed to zero using
externa:i gain and offset trim potentiometers connected to
the ADC as shown in Figures 6 and 7. Multiturn
potentiometers with lOOppm/"C or better TCR's are
recomin.ended for minimum drift over1emperature and
time. These pots may be any value from IOkO to lOOkO.
All resistors should be 20% carbon or better. Pin 29 (Gain
Adjust) and Pin 27 (Offset Adjust) may be left open if no
external adjustment is req~ired.

ADJUSTMENT PROCEDURE
OFFSET - Connect the Offset potentiometer (inake sure
R, is as close to pin 27 as possible) as shown in Figure 6.
Sweep theinl)Ut through the.cmd point transition voltage
that should cause an output transition to all bits Ofr
(Eo,":).
.

FIGURE 4. Recommended Power Supply Decoupling.

5-32

Adjust the Offset potentiometer until the actual end point
transition voltage occurs at E()\·~'. The ideal transition
voltage values of the input are given in Table I.

The external clock pulse must be a negative-going pulse
with a width between 100nsec and 200nsec as shown in
Figure 2, and must be at a lower frequency than the
internal clock.

+15VDC

lal

ADDITIONAL CONNECTIONS REQUIRED

®

..

1.8MIl

"NY

IOk!lIO IDDIJ,

INSTR {
AMP IN

.

I
I

+

_

L- _
___ _
ADCT310NLY

I
,I
,

International Airport Industrial Park - P.O. 80x 11400 - TUClon. Arizona 85734 - Tel. 1602) 746-1111 - Twx: 910-952-1111 - Cabie: BBRCORP • 'Telex: 66-6491

5-35

SPECIFICATIONS'
ELECTRICAL
At T A = +25°C 'and rated power supplies unless otherwise noted.
MODEL

,

:

ADC73.!·, ADC731J
MIN

,-.

I

ADC73K, APC731K"
MAX

n'P

I

RESOLUTION

16

MIN

I:::~:'

I

MAX

'J

.is

"NITS
Bits

INPUT CHARACTERISTICS
ANALOG

J J

Voltage Ranges

Bipolar
Unipolar(1)

±5.±10
o to +10. 0 to +20·

V
V

5
10

kll

Input Impedance. Direct Input
o to. to. :t5V
o to +20V. :tlOV
Differential Amplifier ,ADC731 only'

Inp'ut Impedance, Differential

kll

1010 II 3

Com~on·mod~

5 x.1091\

Common-mode Voltage(2)
CMRR :tl0V input (3)

U il pF
nil pF
V.

~

±IIVccl-31
76

dB

DIGITAL (Convert Command)
Pulse Width
Logic "1" Voltage
Current
-Logic "0" Voltage
Current

200
2.0

nsec
V
20
0.8
0.4

"A
V
mA

±D.0015

+35

%
%01 FSR
%oIFSR
% 01 FSR
% 01 FSR
%oIFSR
°C

300

LSB/mV
LSB/mV
LSBimV
LSB/mV
~V. pop

±D.0005

%oIFSR/%~V

TRANSFER CHARACTERISTICS
ACCURACY
Gain Error!41
Offset Error(4), Unipolar

:to.OOl
:to.OOl
:to.OOl

Bipolar
Linearity Errorc5)
Differentia.1 Linearity ErrortS)
Quantization Error
No Missing Codes Temperature Range
Differential Ground Potential Erron61
Gain
Offset

Linearity
Differential Linearity

±D.0015

±0.003

±D.00075
+15
0.01
0.02

om
0.02
150

30 Noise, Full Scale,(7)

±O.00075

:to.00075
:to.0015
±D.00075

POWER SUPPLY SENSI11VITY
Olfset. +15VOC
-15VOC
+5VOC
Gain. +15VOC .
-15VOC
+5VOC
CONVERSION TIMEIS)

±o.OOOI

%oIFSR/%~V

±0.0007
±D.00035
±0.0012

%oIFSR/%~V

±o.OOO4

%oIFSR/%~V

170

150

WARM-UP TIME (To rated accuracy)

15

%oIFSR/%~V
%oIFSR/%~V

"sec
minutes

TEMPERATURE DRIFT
(Including Internal Relerence)
Gain
Olfse\. Unipola(
Bipolar
Lineanty
Differential Linearity

±10
±2
±5
±2
±2

±O.5
±0.5

ppmJOC
ppm 01 FSR/oC
ppm 01 FSR/oC
ppm 01 FSRJOC
ppm 01 FSR/oC

LONG TERM STABILITY
Gain, Exclusive of Reference
Offset. Exclusive of Reference, Bipolar
Unipolar

±30
±30
±5

l,inearity

±3.7

Reference

±50·

±7.5

5-36

ppm/103 hr
ppm 01 FSRI
103hr
ppm 01 FSRI
103hr
ppm 01 FSRI
103 hr
ppm/103hr

ELECTRICAL (CONT)

Data Codes 1Positive True Logic I
Parallel(9)
Serial I NRZ 1(9)
Status
Internal Clock
Frequency
Clock Adjust Range
Logic Levels
Logic "1" Voltage

USB. BOB. BTC
USB. BOB
Logic "1" During Conversion

113

kHz
%

±20

2.4

Current

0.4

V
mA

Logic "0" Voltage
. Current

0.4
3.2

mA

V

+6.0012
±5

+14.5
-14.5
+4.75

+15
-15

+15.
-15.5

~5

~5.25

V
V
V
mA
mA
mA

60
65
.130

+70
+100
NOTES:
1. Maximum input voltage of AOC731 differential buffer input is ~10V,
2. Vee is value of supply voltage connected to +15V and -15V power supply pins.
3. See CMRR versus frequency performance curve.
4. Adjustable to zero with internal potentiometers. FSR = Full Scale Ran'ge.
5. As adjusted at the factory. Periodic recalibration is performed by following the adjustment procedure in the Installation and Operatmg Instructions.
6. Effect on output of DC voltage differential being present between analog and digital grounds. Measured with 10V Full Scale Range Input and up to
175mVOC between grounds.
7. For20V FSR input voltage. Noise is directly proportional to user-selected FSR.
8. Conversion time can be reduced to 120~sec. See Typical Performance Curves for accuracy versus conversion time. Conversion time and resolution
may also be reduced by"short-cycling" See Installation and Operating Instructions.
9. BOB = Bipolar Offset Binary. USB = Unipolar Straight Binary. BTC = Bipolar Two's Complement.

MECHANICAL

J:r:Z:J /"......,

w~
I

.

I
I

CJ.:cii·

.~ ~:aE"'
!

'-1
y-l

~!

INCHES

MILLIMETERS

DIM

MIN

MAX

MIN

MAX

A

4590

4810

11659

11709

B

2990

3010

7595

7645

C

380

400

965

1016

D

022

028

056

071

E

290

310

737

787

i3
H
L

M

P

100 BASIC
540

I

560

100 BASIC
290
146

310
154

1372

I

1422

254 BAStC
737'

787

3708

3911
508

A

180

200

457

S

090

.110

229

279

7493

7544

.

T

295

297

u

3990

" 010

10135

10185

V

065

085

165

216

I

W

140

160

356

406

y

235

255

597

648

Z

2285

2305

5804

5855

u-----.;

I

254 BASIC

,

5-37

PIN DESIGNATIONS
.'.

::t15V Return(1)
-15V Supply
+15V Supply
'INI
m2
IN3
NC(2)
+6V Ret Out
Analog GndP)
NC
NC

NC

18'
28'
38
48
58
68
78
88
98
108
116
128

tT
2T
3T

'41'

i ST

L6I
7T
aT
9T
lOT
ItT
12T

±15V Returnl'1)
·lSV Supply
+15V Supp't.
:TnStr Amp InpUil
I nstr Amp Output I ADC731 only(3)

illl!t!....A!!!p.ln~!J
NC(2)
+6V Ret Out
Analog GndP)'
NC
'
'NC
Clock Control

Bit IS
8it13 ,
8itll
8it 9
8it 7
8it 5
8it 3
8itl,MS8·
Serial Out
Status Out
ShorlCycle
+5V Return

258"
,268,
.278
288
298
308
318
328
338
348
358
368

NOTES:
1. :t15V Return I Pins 1T, 1B is internally connected to

Analog Gnd ,Pins 9T, 98 in ADC731,

2. Internally connected to Pins 8T, 86.

3, Not internally connected on ADC73 models,

PC BOARD MOUNTING DETAILS
(component side)

5-38

'25T
26T
27T
28T
29T
30T
3tT
32T
33T
34T
35T
36T

IiIit16iLS81
8it14
"
8it12
8Ul0
8it 8
Bit 6,
Bit 4
Bit 2
Bitl1MS8,
Clock Out'
Convert Command

+5V,Supply,

CONNECTION DIAGRAM

±1SV Rtn"
-1SV Supply
+15V Supply

e:

+5V Supply
35B Short Cycle

l6-BIT

~

R>_t.:==:t==lSUCCESSIVE APPROXIMA nON
..
REGISTER

g: ~

-Instr Amp In

4T

o--+--+t--,

Voltage INI

4B

0--+--++--1-'

'nstr Amp Out
Voltage IN2

ST
SB

+Instr Amp In
Voltage IN3

6T
6B

+6V Ref Out

+5V Rtn

{~: gJ r"-M......W-"..-'-t

3ST Convert Command
34B Status
34T Clock Out
33B Serial Data Out
33T Bitl,MSB,
32B Bitl,MSB,

0--+--++--+--------,

32T Bit2

16-BIT
DIA
CONVERTER

Go-I-+'

31B Bit3
3H Bit4
lOB BitS

l~

JOT Bit6
29B Bit7
29T Bit8

8B
9T
Analog Gnd" { 9B
NC lOT
NC lOB

28B Bit9
28T Bit 10

0
0
0

,...
U

CO)

27B Bitll
Bit 12

~'rr

NC lH
NC l1BO
Clock Control 12T

0-----"1.____..1

NC 12BO

c:II
C

26B Bit 13
26T Bit 14
25B BitlS
2ST Bit16 LSB

•

"'::t15V Rtn r pins 1T, 18 is internally connected
to Analog Gnd ,pins 9T, 9B in the ADC 731.

TYPICAL PERFORMANCE CURVES
LINEARITY AND DIFFERENTIAL
LINEARITY ERROR VS CONVERSION TIME
GAIN DRIFTVS AMBIENT TEMPERATURE

±0.0030 ....- . , . . . - . , . . - . . , . - _ -...

Oia:

±0.002S

COMMON-MODE REJECTION
OF DIFFERENTIAL INPUT
BUFFER VS FREQUENCY
-110

+0. IS I---+-t-+-I~+---I-~

I--+--+---f---+---I

.-100

a: +0. I 0 I----I-+-.-!---+"--+--" ----I

:e~

~ '0 ±O.0020 1--+--+--+---+---1

'$

~ ~ ±O.0015

'ID

o

e

~

-0.10

a:
::;

u

I---+-+--+-+--+-+--f

170

+25

I

-80
-70

-0.15 I--+-I-+-I-+---I-~

o
160

\

-90

'0

w
-0.05 I---+-+--+-+--+--j=
c

~ ~ ±O.0010
" ill
:J :5 ±O.OOO751-~Ct~~~~;;~;3
±O.OOOS
ISO

I

'0 +0.05

i§~

140

~

~

10

100

lk

Bits

+15

,

\

100

110

POWER SUPPLY REJECTION
±0.1

,

5~

::'$

""- '"

120 130

±O.Ol

-1SV§

w-

~~

'5'0

oil:

r--...

140 ISO

Conversion Time

±0.001

.....

+15V
+SV

±O.OOOI
100

160

II
lk

10k

lOOk

Power Supp!y Ripple Frequency I Hz I

IJ,.I.SeC 1

5-39

10k

Frequency Hz

Ambient Temperaure ,oC

CLOCK RATE CONTROL VOLTAGE
VS CONVERSION TIME

"

-60

+70

Conversion Time I J,.I.sec,

* Short-cycled to 15

\

100k

1M

input range of the A: Dcorlverter is ILSB±I J2LSRThe
ADC73 and ADC73 rare also guaranteed to have' no
missing codes from + 15~C to +35"C.
'

DISCUSSION OF
SPECifiCATIONS AND
PERFORMANCE

TI,MING CONSIDERATIONS
ACCURACY
The ,accuracy of a successive ,Ipproximation A D converter is descrihed hy the transfer funciion shown in
Figure I. All successive approximlltion A Dc()nverters
have 

I-

::>

'"
-'
==
co
is

0000 ... 0000
ANALOG INPUT
TRAN~ITION

+FSR'~ILSB
2

VOLTAGE
·SEE TABLE I FOR DIGITAL CODE

FIGlJ.RE I. Input

v~Output

for an Ideal Bipolar AjD'Converter.

5-40

14-----'--------CONVERSION TIME (21 _ _ _ _ _ _ _ _ _.....,
CONVERT
COMMAND ('I
INTERNAL CLOCK
. STATUS
MSB

B,T2
alT 3
alT4
alT 5
BIT6
al17
81T8
BIT 9
a,T ,0
alT II
BIT 12
BIT ,3
BIT ,4
alT 15

___ J

:::J
:::TL.....J . ,.
L-j","
:::J
:::J.., ____ .
"0"

~_~

:::J
:::J
::_J
:::J
:::J
:::J
:::J
:::J
:::J
:::J
:::J

~I'~=~~

\"0"

______________________ ____
~

LJ"I"

~r--

r

.

L-J~~I.. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

LJ"I"
1"0"

L-j",,,

L_h"
1"0"

LJ"l"

~

______________________________~I=
. a'=h~----~r--

r--

,....,,....,.-=-..,

BIT '6
Msa
,
2
SERIAL131 DATA OUT:: -I--L.";,"a,,J,
.. , ..

.. ,..

4

I

"a'

5

6

I

7

.., ...., ..

"0"

NOTES:
I. The clllvart command musl ball 11111 2IlOnuc wide, Th, conversion Is
Inl!lalad by lhe "leading adga" ollhl clllvert command,

I

"I"

2, 170,..sec maximum for 16 bIll.
1 Usa trailing (high lD lowl edge 01 clock lD stroba Blch sarial output bil

FIGURE 2. AD03 731 Timing Diagram.

TABLE I. Input Vultages, Transition Values. LSB Value
,
and Code Definitions,
INPUT VOLTAGE· RANGE AND LSB VALUES
Analog Input
Voltage Rang.

I

Code
Designation
One Least
Significant
Bit ,LSB

Transition
Values(4)
LSB
MSB
1111 ... 1111
1000 ... 0000
0000 ... 0000

"!:.5V
BOBI1I
orBTC(2)

USB(3)

20V

10V

l0V

2"

2"

2"

2"

1.22mV

61O~V

61O~V

l.22mV

61O~V

305~V

305~V

610~V

305~V

l53~V

l53~V

305~V

FSR

2"
n
n
n

~

~

~

14
15
16

+Full Scale
Mid Scale
-Full Scale

o

to~10V

-10V
BOB'"
orBTC(2)

o to +20V
USB(3)
20V

+10V-3/2LSB +5V-312LSB +10V-312LSB +20·3/2LSB
+5V",lI2LSB +10",1/2LSB
0:!:1I2LSB
O:!:lI2LSB
0+l/2LSB
0+1/2LSB
-l0V+l/2LSB -5V+1/2LSB

1. BOB ~ Bipolar Offset Binary
2. BTC ~ Binary Two's Complement
3. USB = Unipolar Straight
Binary

4. Nominal voltages for
transition to code specified.

5-41

INSTALLATION AND
OPERATING INSTRUCTIO~S
MOUNTING'
Mounting on a, printect ,circuit board-isaccomplisheci
using the female printed circuit connectors s~pplied with
each A, D converter. Mount theA D converter with two
#4 external tooth lockwashers and two' #4-40 machine
screws, Refer to themou'nting instructions. Be sure to
leave clearance for screwdriver adjustment of the trim
potentiometers.

, be taken to prevent other'printed circuit conductors from
making electrical contact with ,the case. In oider to avoid
ground loop paths, the caSe itself should not be cbrinected
to any o.ther·local power supply returns.

PC LA YOUT CONSIDE~ATIONS

The metal case (ADC73 and ADC731) is connected
internally to the±15V Rtn pins (I Band IT)_ Care must,

Coupling between digital signal paths and the analog
iI1Puts, INI, IN2, IN3 and +Amp In and-Amp In
(ADC731) should be minimized' by careful layout
separatiQn and or ground plane shielding.
In addition to the power supply cQnnectiQns, other
, connections to' the A D converter shQuld be limited to'
digital inputs and outputs with a single digital commQn
return path and the analog input.

+

+
ADC731

OPTIONAL

=

__________....

~m~~OR +--+--++--""':':::":=-j~!!t:::
~---~--I+5V,

ri~-+--~--------iCOM

'----------I+15V
l-~------------------iCOM

SVSTEM

'---------------1 ·15V

aROUND

FIGURE 3. ,A DC73I PQwer Supply ConnectiQns.

542

+5V
POWER
SUPPLY

±15V
POWER
SUPPlY

POWER SUPPLY CONNECTIONS

Power supply decoupling capacitors should be used as
shown in Figure 3 and located as close as possible to the
pins. Use Ij.lF tantalum or electrolytic capacitors.'
Parallel electrolytic capacitors with O.OI/.lF ceramic
capacitors for be'St high frequency decoupling.

ADC731
AnalogGnd (pins 9B. 9T)and ±15V Rtn (pins lB. IT)are
connected together internally. ±15V Rtn and +5V Rtn
(pin 36B) are not connected internally. These supply
return lines should be connected together as close to the
unit as possible. If±15V Rtnand +5V Rtn are connected
together ata system common point a significant distance
from the pins. usc a 0.01 /.IF to O.I/.IF non polarized bypass
capacitor between these pins as close to the pins as
possible. Refer to Differential Ground Potential Error in
Electrical Specification table.

ADC73
Analog Gnd and ± 15V Rtn pins are not connected
internally on this model to permit a separate analog input
signal return sense connection. Input signal connections
arc described in a following section.
Comments made for ADC731 power supply connections
also apply to the ADC73. Refer to Figure 4.

+

+

OPTIONAL ::;:
BYPASS
+----1f----+~----<...,:.:...::.:.::.(:
CAPACITOR

COM

+5V
POWER
SUPPLY

+15V
COM
·15V

:!:15V
POWER
SUPPLY

+5V

FIGURE 4. ADC73 Power Supply Connections.

5-43

CALIBRATION
The relative accuracy of ADC73 and ADC73 I is adjusted
to within specification at the factory. Offset and Gain
may need to be' adjusted after the AI D ,converter is
installed and,afterextended periods of time , ~ecalibration
will be necessary.
'

SEPARAT,E POWER SUPPI-IES
Because the effectiveness of high resolution AI D converters can be reduced ,by small anipunts of noise,
separate fl()ating supplies may ,be needed for applications
in environments with high electrical noise. These supplies
and their return paths should be connected to the AI D
converter only.' Some'experimentation with extra,shielding and alternative return configuraiions may be necessary
in extreme circumstances.
INPUT CONNECTIONS
ADC73
Analog input signals to ADC73 are connected directly to
low impedance inputs (5kU and IOkn). The user may
select unipolar or bipolar, IOV or 20V full scale ranges as
illustrated in Figure 5.
A DC73 I
ADC731 has a precision high impedance differential
input buffer. The user may select a unipolar range of 0 to
+ IOV or bipolar ranges of±5V or ± IOV as illustrated in
Figure 6. Note that signal input voltage VIS plus the
common-mode voltage is limited to ± IOV for the bipolar
connection and + IOV for the unipolar connections.

FROMD/A
+----,C:::ON::;,VERTER

} ±15V lIETURN

'II BIPOLAR. ±IOV III' ±5V INPUT'.

FROM Oil

FROM Oil
CONVERTER

~---,C;,:;ON;;,;.V~RTER

'II BIPOLAR. ±IOVDr ±5V INPUT.

I±15VRETURN
1111 UNIPOLAR. Ola +IOV INPUT (InI,~

FIGURE 6. Signal Input Connections for ADC73!.
FROMO/A
CONVERTER

1111 UNIPOLAR. 0 Ia +IOV Dr 0 Ia 20V INPUT.

FIG~RE

Six potentiometers are b'ulltinto ,the ADC73 'and
ADC73 I for adjusting Offset (I potentiometer); Gain (I
potentiometer), and Linearity (4 potentiometers). Lin,earity is adjusted in the first 4MSB's by adjusting the
currents in bits I(MSB), 2, 3, and 4. Refer to Table 1\ for
the transition voltages to be applied to the input
appropriate to the input range being used. All input
voitages should be set within ±IO"V of the ideal voltage.

5: Signal Input Connections for ADC73.

5-44

Procedure for full calibration (Offset. Linearity. and
Gain):
I. Set the input voltage to the transition voltage for oll"set
calibration. Adjust the Offset potentiometer until the
transition to 000 I,. from 0000,. occurs SO% of the time
with repeated conversions.
2. Set the input to the transition voltage for the Gain, Cal
adjustment listed in Table II. Adjust the Gain
potentiometer until the transition to OFFF,. from
OFFE,. occurs 50~:; of the time with repeated conversions. If bit 4 should turn on such that the codes
I FFF,. and I FFE,. occur. adjust potentiometer
labeled bit 4 so that bit 4 (pin 31T) does not turn on.
3. Set the input to the bit 4 transition \"Oltage of Table II.
Adjust the potentiometer labeled bit 4 until thetransit ion to 1001,. from 1000,. occurs SO+~~--------t----'--C i5VDC

I
I

I

......-_:_t_----<+15VDC

}-___- - - f - - -.....---+-~-IOkuta
lOOku GAIN

r-I
~--

-

IOkuta

_-_-.:_-_e:_S+-A_DJ-'U_ST-f~.,.....--.~IOOkU

L..-_...

OfFSET
ADJUST

AOC78

r-I

1 .... - -

I

ANALOG
}---------+--'--+---..,.--I----I~.."F-+-......... COMMON

}-.,_------.....--r-"-----...,....;;.......-...;;...--< ·15VDC

I
I

"

DIGITAL
COMMON

L .... ,..... _

}----e·"'·' STATUS OUTPUT TO
.CONTROLLOBIC

'CAPACITOR SHOULD 8E CONNECTED EVEN IF EXTERNAL GAIN ADJUST.IS NOT USED.

, FIGURE 3. ADC76 C(Jnnections For: ±IOV Analog Input. 14-BitResolution (Short-Cycled). Parallel Data Output. .

TABLE I. Input Voltages. Transition Values.LSB Values. and Code Definitions.
Binary I BIN I
OutDut
Analog Input
Voltage Range.

INPUT VOLTAGE RANGE AND lSB VALUES

Defined As:

Code
Dsalgnation
One least.
Significant
B~ IlSBI

±lOV..

±5V

±2.5V

'0 to +10V

Oto +5V

Oto+20V

COBI'I
orCTC\21

COBIII
orCTC(2)

COBI'I
orCTC(2)

CSB(3)

CSBI3)

CSBI3)

W!n

1IDl

~
2n
1.22mV

1IDl

~
2n.
1.22mV

f§!!

~

2n
n=12
n=13
.A.=14

2
4.88mV
2.44mV
1.22mV

2n
2.44mV
1.22mV

610~V

an
2.44mV
1.22mV

610~V

305~V

610~V

610~V
305~V

4.88mV
2.44mV
1,22mV

+FilllScale
MidScale
-Full Scale

+lOV ·3/2LSB
0
-10V'+1/2lSB

+5V ·3/2lSB
0
-5V+l/2lSB

+2.5V -3/2lSB
0
-2.5V +ll2lSB

+lOV -3/2lSB
+5V
0+ 112LSB

+5V -3I2lSB
+2.5V
0+ 1/2lSB

+2OV -3/2lSB
+10V
0+ 112lSB

Transitlon'Values
MSB lSB
000 ...000(4)
011 ... 111
111...110

.

.'

('ICOB = Complementary Offset Binary

(3)CSB = COmplementary Straight Binary

(2)CTC = Complementary Two's Complement - obtained by
,
inverting the most significant bit. MSB Ipin 11.

1')Voltages given are the nominal value
for transition to the code specified.

.

?-48

.

SPECIFICATIONS
ELECTRICAL
At +25"C and rated power supplies unless otherwise noted
MODEL

ADC7tKG
MIN

ADC7IJO

TYP

MAX

RESOLUTION

MIN

TYP

I

'16

MAX

UNITS

16

Bits

ANALOG INPUTS
Voltage Ranges
Bipolar
Unipolar

±2,5. ±5. ±IO

±2,5. ±5. ±IO

V

oto +5. 0 to +10.
o to +20

o to +5. 0 to +10.
Oto+2O

V

2,5
5
'10

2.5
5
10

kll
kll
kll

Impedance I Direct Input I
o to +5V. ±2.5V
o t6 +IOV. ±5.0V
o to +2OV. ±IOV
DIGITAL INPUTS(')
Convert Command
Logic Loading
External Clock

Positive pulse SOnsec wide (min) trailing edge! "1" to "0" initiates conversion I
I
I
I
I
I
I
Negative pulse l00-200nsec wide. Frequency < internal clock(2)

I

TTL Load

±C.2

'Ib

TRANSFER CHARACTERISTICS

Q

±O.I

±C.2

±C.I

±C.OS
±C.I

Inherent Quantization Error
Differential linearity Error
Noise 130. p·pl

±C.I
±C.2
±C.OO3

±0.003
±0,003

±112
±C,003
±C.OO3

POWER SUPPLY SENSITIVITY
±15VDC
+5VDC

0.003
0.001

0.003
0.001.

'lbol FSR/'lbVs
'lbol FSR/'lbVs

Linearity Error

±C.OS
±C.I

±1/2

CONVERSION TIME(S) 114 B~.)

±O.I
±C.2
±C.OO6

15

IS

I'sec

min

5

5

DRIFT
Gain
Offset
Unipolar
Bipolar

±15
±4
±IO
±3

±2

Linear~

No Missing Codes Temp Range
KG II4-bitl
JG II3-bit)

±2

±2
±2

±15

ppmfOC

±4
±IO
±3

ppm 01 'FSR/oC
ppm 01 FSRfOC
ppm 01 FSR/oC

50

°C
·C

+40

+10

0

OUTPUT
DIGITAL DATA
(All codes complementary I
Output Codes(B)
Unipolar
Bipolar
Output Drive
Status
Status Output Drive
Internal Clock
Clock Output Drive
FrequencytB)
POWER SUPPLY REQUIREMENTS
Power Consumption
Rated Vo"age. Analog
Rated Vo"age. Digital
Supply Drain +15VDC
Supply Drain -15VDC
Supply Drain +5VDC
TEMPERATURE RANGE
Spacilication
Operating 'I derated specs I
Storage

~,

C
'Ib01 FSRI4}
'Ib 01 FSR
'lboIFSR
LSB
'lbofFSR
'Ib of FSR

WARM-UP TIME

II
.....

ACCURACY
Gain Error(3)
Oflset Error
Unipolari:\)
Bipola(3)

I

I

I

CSB
COB.CTC(7)

I

I

2

CSB
COB.CTC(7)

2

2933

±14.5
+4.75

1.55
±15
+5
+45

1400

933

±15.5
+5.25

±14.5
+4.75

+70
+65
+125

0
-25
-55

-35
+70
0
-25
-55

5-49

2

TTL Loads

Logic "1" during conversion

Logic "I" during converiion

1.55
±15
+5
+45,
-35
+70

2

,TTL Loads

2
1400

TTL Loads
kHz

±15.5
+5.25

VDC
VDC
mA
mA
mA

W

+70
+85
+125

I

·C
°C
·C

NOTES: ,
'
,
"
"
" ,"
" DTLITTL compalible, i,e .. Logic "0" = 0,8V, max, Logic "I" = 2,OV, min lor inputs, For digital outputs Logic "0" ='0,411, max, Logic "I" = 2.4)/, inin,
.
. ,: ~., ~,
2. See External Clock operating instructions.
3, Adjustment to zero, See "Optional External Gain and Ollset Adjustment" section,
FSR ineans'Fu'ii sCale Range, For example, unii conneCted lor ±10V range h.... 20V FSR,
'
,
,
5, Conversion time may be shortened wilh "Short Cycle" eet lor lower resolution and with use 01 ,Clock Rate Control, See "Optional Conversion'Time
',. Adjustment" sectiqn, The, CI"!'k Ra... .control I pin 231 should be cC\ilnected to Di,gi!al Common for specified conversion time, Short Cycle I pin 32 I
should be left o~n lor 16-bit rasol ution or connecfed to the n + 1 digital'outputlor n-bit 're...ilution, For example, connect Short Cycle to Sk15 I Pin 1~, (or'
14-bit resolution, For resolUlions less than 16 Ms, pin 32 should also be tied to+5V througha 2kll resistor:
'
"
6. See Table L CSB,- Complementary St,$ight Binary, COB - Complementary Ollset Binary, CTC - yomplementary Twq's Complement.
7. CTC coding obtained by inverting MSB (pin 1 t,
'
8, Adjustable with Clock Rate,controllrom approximately 933kHz to 1,4MHz, See Figures 12 and 13 and Table III,

;4:

I
,',

MECHANICAL
INCHES
MIN
MAX

~

MILLIMETERS
MIN

1-

'!>JJ

", , "

D'

i

2302MC
WE!G~T:

,j

T

N
"

NOTE:
' '
Leads in true position w,ithin,
0,0,10· lO,25mm, Rat MMC at sealing plane,

13 grams'.O.46 oz.

HERMETtqtTY:
Conform~to method ~014
condition. C step 1 ,fluoro-carbon of MIL-STO..aB3

"i J.tI2 F8' Lr;-L-=:J r
Jl1I.H.J
~-~-N~1Im~
to .Jl.o l~TNI

'"
2286"BAS'C

CASE: C~r~mic
MATtNG CONNECTOR:

Pm. numbers shown for retereneeonly.
Numbers may not be marked on package.

gross leak.

UUU

PlA'"

CONNECTION DIAGRAM
TOP VIEW

IMSB,Bitl

r;:t=====:;----;:=======tl2)

Bit2

SHORT CYCLE,
'CONVERT COMMAND'

Bit3

+5VDC SUPPLY

Bit4

GAIN ADJUST

Bit5

+15VDC SUPPLY

Bit6

COMPARATOR IN

Bit 7

BIPOLAR OFFSET

Bit 8

10V

Bit9

20V

Bit 10

CLOCK RATE CONTROL
ANALOG COMMON

Bit12

-15VDC SUPPLY

ILSB for 13 bits, Bit 13

CLOCK OUT

ILSB for 14 bits, Bit 14

DIGITAL COMMON'

Bit 15

~~~~~~~~~~~~~~~::::~)i~

Bit 16 ~

STATUS
.NC

, ;,'If an external.clock is used, connect the clock to pin 31 I CONVERT COMMAND"

TYPICAL PERFORMANCE CURVES
GAIN DRIFt ERROR','III OF FSR,
\Is TEMPERATURE
+0, '8 r---....;-......;..-..;.....;...-....,.
+0,'61-------------1
IX:

..
>

~

+0,12

~ +0,08

g

w

~
c

'iij
Cl

~

0.06

,S

0,04

/
-15VDC

V

~

c

15

a:

POWER SUPPLY REJECTION VS
SUPPLY. RIPPLE FREQUENCY

0.1

+0,04

u"

0

i'

0.02

V.
/

~

15

-0.04

0,01

8.

0,006

(5

0.00'\

-0,12

~

0.002

-0,16
-0,18

15

-0,08

it
i'

0

+250
Temperature °C

+700

I

+15VDC

/
./

J

l\./.".

+5VD~

0,001

1

5.,.50

IE ,.:

10

100
lk
Frequency (Hz I

10k

lOOk

DISCUSSION OF
SPECIFICATIONS
The ADC76 is specified to meet critical performance
criteria for a wide variety of applications. The most
crit-icalspecifications for an AI D converter are linearity.
drift. gain and offset errors. and conversion speed effects
on accuracy. This ADC is factory-trimmed and tesied for
all critical key sp,!:cifications.

GAIN AND OFFSET ERROR
Initial Gain and Offset errors are factory-trimmed to
typically ±O.I% of FSR (±0.05% for unipolar offset) at
2S"C. These errors may be trimmed to zero by connecting
external trim potentiometers as shown in Figures 7 and 8.
POWER SUPPLY SENSITIVITY
Changes in the DC power supply voltages will affect
accuracy. The ADC76 power supply sensitivity is specified at ±0.OO3% of FSR/%V s for the ±15V supplies and
±0.0015% of FSR/%V s for the +5V supply. Normally.
regulated power supplies with 1% or less ripple are
recommended for use with this A DC. See Layout Precautions. Power Supply Decoupling. and Figure 5.

LINEARITY ERROR
Linearity error is not adjustable and is the most meaningfu) indicator orAl D converter accuracy. Linearity is the
deviation of an actual bit transition .from the ideal
transition value at any level over the range of the AI D
converter.
Differential linearity describes the step size between
transition values. A differential linearity error of±0.003%
of FSR indicates that the size of any step may not vary
from the ideal step size by more than 0.003% of Full Scale
Range.

ACCURACY VERSUS SPEED

..

'"
e::.

0.1

ut-

...==
IE
c

\\f

:::;

0.01

E
...

D.OO3

::;

0.001

:i.
....
~
!!:

to the unit as possible. preferably to a large plane under
the ADC. If these grounds must be run separlltely. use
wide conductor pattern and a O.OIIlF to 0.11l F n'onpolarized bypass eapacitor between analog and digital commons at the unit. Low impedance analog and digital
common returns are essential for low 'noise performance.
Coupling between analog inputs and digital lines should
be minimized by careful layout. The comparator input
(pin 27) is extremely sensitive to noise. Any connection to
this point should be as short as possible and shielded by
Analog Common or ±15VDC supply patterns.

POWER SUPPLY DECOUPLING
The power supplies should be bypassed with tantalum or
electrolytic capacitors as shown in Figure 5 to obtain
noise free operation. These capacitors should be located
close to the ADC.

@

-

-

®
1+
I I~F

@)

®

DIGITAL COMMON

.

·15VDC

1
I~F

@)

ANALOG
COMMON

..

1+

I+I~F

...

+15VDC

INPUT SCALING

TABLE II. ADC76 Input Scaling Connections.

SHORT CYCLED TO 12 BITS
SHORT CYCLED TO 1'3 BITS
f8HORT CYCLED TO BITS

i.

Input.

112LSB 12·BIT

\~

D.IIDII
Ii!
c

-

Analog and digital common are not connected internally
jll the ADC76. but should be connected together as close

The analog input should be scaled as close to thc
maximum input signal range as possible in order to utili/c
the maximum signal resolution of the A () converter.
Connect the input signal as shown in Table II. See Figurc
6 for circuit details.
.

Iii"

Ie

II!

LAYOUT PRECAUTIONS

FIGURE 5. Recommended Power Supply.Decoupling.

I n successive approximation AI D converters. the conver-

-..

LAYOUT AND OPERATING
INSTRUCTIONS

+5VOC

DIFFERENTIAL LINEARITY ERROR

...
...'"
....

sionspeed affects linearity and differential Iinea-rity
errors. Conversion speed and its effect on linearity and
differential linearity errors for the ADC76 are shown 'in
Figure 4.

~~

5

I12LSB IS-BIT

15
10
CONVERSION TIME l"ucl

FIGURE 4. Linearity and Differential Linearity
Versus Conversion Time.

Output
Code

±10V

COB or CTC'
COBorCTC'
COBorCTC'
CSB
CSB
CSB

±5V
±2.5V
o to +5V

o to +10V
o to +20V

1I2LSB 14·BIT

:5

Signal
Range

To· Pin

Connect
Pin 24
To

Connect
Input
Signal
ToPin

27
27
27
22
22
22

InputSig.
Open
Pin 27
Pin 27
Open
Input Sig.

24
25
25
25
25
24

Connect
Pin 26

Obtamed by Inverting MSB I pm 11.

20

OUTPUT DRIVE
Normally all ADC76 logic outputs will drive tWo standard
TTL loads; however. if long digital lines must be driven.
external logic buffers are recommended.

~

~
C

Table I details the transitiPtlNoltage
leveisteqliired.
,
,

DIRECT
INPUT

[II

..

..,..,..

1.8M!1

@

"

+15VDC " "
IUknl., IDOku
OFFSET ADJUST
i
·I&VDC

'COMP.IN
'.'

[bl

"

.~
COMP.IN

,221m' "
"'='"

FIGURE 6. ADC76 Input Scaling Circuit:
INPUT IMPEDANCE
The input signal to the; ADC76 should be a low impedance, such as the output of an'op amp to avoid,any errors
due to the relatively lowinputimpedance of the ADC76.
If this impedance is not low, a buffer amplifier should be
added between the input signal and the direct input to the
ADC76 as shown in Figure 7.

'"

+15VDC
101m ta IDOkn
OFFSET ADJUST"
·15VOC

",

."'.

FIGURE 8. Two MethodsofConnectingOptioi!.a1
Offset Adjust.
"
'
+1,5VDC

~."...,..,....-~

ANALOG COMMON

(§)T

o.ol~F

IOknta

IDOIen

GAIN ADJUST
·15VDC

FIGURE 9. C()nnectingOptional Gain Adjust.
AllAlDB INPUT Sl8NAL
883107J

FIGURE 7. Source Impedance Buffering.
OPTIONAL EXTERNAL GAIN AND
OFFS"'T ADJUSTMENTS
, Gain and Offset errors may be trimmed to zero using
external gai,n and offset trim potentiometers connected to
the ADC as shown in Figures 8 and 9. Multiturn
potentiometers with, 100ppmj"C Or better TCR's are
reco'mmended for minimum drift over temperatl!re and
time. These pots may be any value from I.OkU to lOOk!!.
All resistors should be 20% carbon or better. Pin 29 (Gain
Adjust) and pin 27 (Offset Adjust) may be left open i(no
external adjustment is required.
ADJUSTMENT PROCEDURE
Offset - Connect t'he Offset potentiometer (m~ke sure R,
is as close to. pin 2iaspossible) as shc;>wn in Figure 8.
Sweep the input through the end point transiti(lO voltage
that should cause an output transition to all bits off
(WI'"

I'

(E,l' ).

Adjust the Offset potentiometer until the actual end poilU
transition voltage occurs at E"','L The ideal ,transitio~
voltage values of the input are given Table I.

in

Gain - Connect the Gain adjust potentiometer as shown in
Figure 9. Sweep the input through the end point transition
voltage that should cause ,an output transition to all bits
on (E(:~). Adjust the Gain potentiometer until the actual
, end point transiti()nvoltageoccursat E(:~.
.CONVERTER INITIALIZATION
On power-up. the state of the ADC internal circlI,itry is
indeterminate. One conversion cycle is required to initialize the converter after power is applie:d.

EXTERNAL CLOCK
If an external clock is used, connect the external clock to
Convert Command,.pin 3 L The convert command shown
in Figure 2 is not used. After each conversion is completed, a new conversion cycle will automatically start on
the first falling edge of the externa.l clock follow.ing the
completion of conversion. The clock, out si1lnal will
remain as sho'wn in Figure 2 even if an'external clock is
used. The external clock pulse must be a negative going
pulse with a width between IOOnsec and 200nsec as shown
inFigure 2, and must be at a lower frequency than the
internal clock. The circuit ion Figure 10 shows a simple
technique for generating a clock signal with the required
duty cy<;le from an ,external clock with an arbitrary duty
cycle. The external clock must operate at a lower
frequency than the internal clock for proper operation.
This should not present a problem since the frequency of
the internal clock can be increased to any desired vallie by
using the Clock Rate Control, pin 23. Figure II sh()ws a
conversion using a continuous external clock.
OPTIONAL CONVERSION TIME ADJUSTMENT
The ADC76 may'be operated with faster conversion times
for resolutions less than [4 bits by ,connecting the Clock
Rate Control (pin 23) and the Short Cycle (pin 32) as
"shown in Table III. Typical conversion times for the
r~solution and connections are indicated.
TABLE III. Short Cycle and'Ci~k Rate Control
Connections for.l2- to 16-Bit Resolutions.,

,
",

ae~Qlutiqn

I Bits I

Connect Pin 32', to
Connect Pin 23 to
Typical Conversion Time

16

15

Open

Pin 16

'14

Hi

,13

' 12,

Pin 14

Pin13

Pin 19,' Pin 19 Pin 19 Pin 30
16,,88C ,1~""G "10,,sec

Pin 30

17~sec

Pin

~~sec

For resolutions less than 16 bits also connect a 2kll r.eslstor from +5V 10
pin 32,

5:"52

+6VOC

Ikll

ADcn
COlVERT
COMMAND
EXTERIIAL CLOCK

~

If a more precise adj ustment of conversion time is desired
than can be obtained by simply connecting the Clock
Rate Control (pin 23) to Digital Common or +5V, as
indicated in Table III, the Clock Rate Control may be
connected to an external multiturn trim potentiometer
with a TCR of±IOOppml"C orlessas shown in Figure 12.
The typical conversion time versus the Clock Rate
Control voltage is shown in Figure 13 .. The effect of
+15VOC

~
@___....<5k1l

CLOCK

-*:::1 RATE

+6VIIC

INTERNAL CLOCK
FREQUENCY ADJUST

CLOCK RATE CDJlTROL

COITROL

EXTERIAL
CLOCK

FIGURE 12. Clock Rate Control, Optional Fine Adjust.
30
~-+-~~r--r-+-'TYPICAL

125 t--t--l-+--+-t--+--IH

OICI
ITO PIli 31)
~ ~ 200nuc TYPICAL
STATUS - - - - - . . ,

EIIO OF PREVIOUS

!20t--t-+-t--ir--+-+-H

115~~~+-++

COJIVERS~Ui'fiifOF NEXT CONVERSIOII.

ul:~;t~~~E§~::!§~~~

111l1li AOC78Iarpnp"8IIIFIIIIn. TIIIIntImII clICk I,......, II 1133kHz willi
1111 Click Rill Clllllrlllpin 23) _I11III ID Dlallli CaII..n. II. higher
......... cllCIc 1/IqUInc, II IIIIIIlrId. 11II11IIImI1 CIDat Il'IIIuencr CIn III

Incrulld br can_na pin 23. +6V.
EXIIrIIII claak DIn hlVlln, dulrld dutr cr.cli.

o

2

4

8

8

10

12

14 15

COJITROL VOLTAGE ON PIN 23

FIGURE 13. Conversion Time vs Clock Rate Control
Voltage.

FIGURE 10. Continuous Conversion Using .External
Clock With Arbitrary Duty Cycle.

varying the conversion time and the resolution on Linearity Error and Differential Linearity Error is shown in
Figure 4.

+6VOC
Ikll

HEAT DISSIPATION
ADcn
1-i-'----{:31 . CONVERT
COMMAND
EXTERNAL CLOCK
CLOCK

-@ ~~~ROL

COlVERT COMMANO

'------{:18 STATUS

The ADC76 dissipates approximately 1.8 watts (typical)
and the packages have a case-to-ambient thermal resistance (Bn) of 25"C/W. For operation above 70"C, B('"
should be lowered by a heat sink or by-forced air. over the
surface of the package. See Figure 14 forB(,A requirement
above 70"C. If the converter is mounted on a PC card,
improved thermal contact with the copper ground plane
under the case can be achieved using a silicone heat sink
compound. On a 0.062" thick PC card with a 16 square
inch (minimum) area, this technique will allow operation
to +85"C.

EXTERIAL
CLOCK

1
T," .~

QICI--......,
(TO PIN 311

_II-- 2IJOnuc ITYPICAL)

80

STATUS _ _......I
1IDtI:
Th. CIIIVlrt _lIInd .ad 1111 ........1clack mUll III high 111IItI11I_1, 10
InlUIIIUOIIvtrllln. TIl. DllllVlflian wllllllrt en IhIrlllftg ItIglallllllXllfnel
clack. An, aonvtrI CeQladllhil Dccur during. cenvmlln will III lallll'lld.

FIGURE

)1.

70
80
90
100
AMBIENT TEMPERATURE rC)

FIGURE 14. 6(,A Requirement Above 70"C.

Conversion Initiated by Convert Command
Using Continuous External Clock.

5-53

=
C

i

* TIl.........1cIoat n.aency liliiii1111_111.. IIIlnt.,...1 cItcIc lrIqueftC,

co
,....

U

110

h

BUR,R-BROWN®

,'1',<.1

I Hl\

ADC80

t~~n

IElElI

,

ADr- •.riA' ,I \}:

t

•

/\>l

(IN\\'R\f fl,

m.im

f .. OCeop.<:'i
•

~

it)
~

• ><

Ie AN:ALOG- TO-DIGITAL CONVERTERS
FEATURES

DESCRI'PTION

• COMPACT DESIGN - Self-contllned with Internal clock.
comparaJo~. an~ reference
",'.
32-pln ceramic package
,

"

'

• FAST CONVERSION SPEEDS
Provide'ast ,lIlgnal sampling r,tes
12-blts - 25Jlsec. la-bits - 21 Jlsec
Faster conversion speeds obtainable with
"Short:Cyclino" 'and optional external clock
• LOWCOST

Complete,with internal reference. the ADC80 offers
versatility and performance formerly offered only in
" larger modular or racl<-inount packages.
Thin-film internal scaling resistors are provided
for the selection of analog input signal ranges of
±2.5V. ±5V. ±IOV. 0 to +5V orO to +IOV.
Gain and offset errors:maybe externally trimmed to
'zero. offering initial accuracies of·better than
±0.0122~ii (;±:I 2LSB).The model ADC80 is specified
'
for ~25"C to +S5"C operatio'n.

• WIDE SUPPLY RANGE - Will operate with
±11.4V to ±16V supplies IZ modeli) ,

'FUNCTIONAL DIAGRAM

iii'f1
LOGIC SUPPLY
'DIGITAL COMMON
COMPARATOR IN aY..!:99=~:-t
INPUT RANGE{
SELECT
ANALOG COMMON
GAIN, ADJUST

The Model ADCSOAG-IOand ADCSOAG-12 are
,10:.andJ2-bit su~es~iveapp~oxin:ulii-___ To
SAR

FIGURE 4. ADC80 Input Scaling Circuit.
TABLE II. ADC80 Input Scaling Connections.
Connect
Input

'~
+ .

+5V
Dig. Com.

!

€),...,.-~:t~-...

4

€)

Signal
Range

·15V
I~F
1·121Y
@I"---:r:~-"'." Ana. Com.

1+

9

I~F

"'1:

~

Ij';'
v.:J

"-10V
tSV
t,2.5V
o to +5V
o to +10V

I~F

•

Sku

Bipolar
Offset
Ana. Com.

POWER SUPPLY DECOUPLING,
The power supplies should be bypassed with tantalum or
electrolytic type capacitors as shown in Figure 3 to obtain
noise free operation. These capacitors should be located
close to the ADC80. II'F electrolytic type capacitors
should be bypassed with O.OII'F ceramic capacitors for
improved high frequency performance.

RI

Compln

+ 15V
(+12VI

Connect

Connect

Input

Pin 12
To Pin

Pin 14

Signal

To

To

Output

Code

CSB
CSB

14
13
13
13
13

Input Signal

11
11
11
15
15

COB or eTC
COB or eTC
COB or eTC

Open
. Pin 11
Pin 11
Open

FIGURE 3. Recommended Power Supply Decoupling.

OPTIONAL EXTERNAL GAIN AND
OFFSET ADJUSTMENTS
Gain and Offset errors may be trimmed to zero using
external gain and offset trim potentiometers connected to
the ADC80 as shown in Figures 5 and 6. Multiturn
potentiometers with 100ppm "c or better TCR's are
recommended for maximum drift over temperature and
time, These pots may be any value from 10kH to 100kH.
All resistors should be 20e ; carbon or better. Pin 16(Gain
Adjust) may he left open if no external adjustment is
required.
.

voltage that should cause an output transition to all ones.
Adjust the Offset potentiometer until the actual end
point transition voltage occurs at E'.'~·'·. The ideal
transition voltage values of the input are given in Table I.

GAIN • Connecf the Gain adjust potentiometer as
shown in Figure 6. Sweep the input through the end point
transition voltage that should cause an output transition
to all zeros .

ADJUSTMENT PROCEDURE
OFFSET· Connect the Offset potentiometer as shown in

Adjust the Gain potentiometer until the actual end point
transition voltage occurs at E~):. '

Figure 5. Sweep the input through the end point transition

Tablti I details the transition voltage levels required.

(bl

III

CL!!~~f
~"''''~

Comp.l"

·15V
1·12V]
·1.5Mu for Zmodels
··28Im for Zmodels

IUkU:O
lOOkn
Offset

Adjust

Ibl

lal

+15Vf>12V]-

+15VI+12V]

+15V 1+12VI

Ic.\ 180Icn
I~

Comp
IN

f~Olm

I80kn

'1221111" '
-=-

Gain Adlusl

~

lOOkn
Offset

FIGURE 5. Two Methods of Connecting Optional Offset
Adjust with a O.4YC of FSR Range Adjustment.

t.

.L __. _ ;

F
,.... T 0.01 ~·IIlV
\!9-'

~dlU8t

·15V 1·12VI

IlIMn'

10ku to

~ lOOkn

Ana. Com,

+15V (+I2VJ

11'::\

Gain I~
Adjust

1·12V]
·8.2Mn for Zmodels
'.9.lkn for Zmodels

270k

'I'
@1
15

f

'
271lkn

n

0.01 F
~
"

Ukn"

1:-

IUku
10
looko
Gain

Adjuet
·15V H2VJ

FIGURE 6. Two Methods of Connecting Optional Gain
Adjust with a 0.6% Range of Adjustment.

5-59

CLOCK OPTIONS
The ADCSOis extremely versatile in that it. can be.
operated in several different modes with either internal or
external clock. Most ofthe~e options can be implemented

with nothing more than an i.nexpensive quad 2-input
NAND gate (7400) as shown in .Figures 7 through 10.

~------~----~----~----------~

1L1lS1..\

10.81t

+, Operation

; External _
I Clock·

I

12·81t

I IOpmtlon
- .... +5V

I

I

+5V

JL
Convert

Dlgltll
Comman

I

I Commend

FIGURE 7. Internal Clock- Normal
Operating Mode. (Conversion
initiated by the rising edge of the
convert command. The internal
clock runs only during
conversion.)

FIGURE 9. Continuous External Clock. (Conversion initiated by rising
edge .of convert command. The convert command must be'
synchronil.ed with clock.)

470pF

.Il.Jl.JL
External
Clock

FIGURE S. Continuous Conversion with
External Clock. (Conversion is
initiated by 14th clock pulse.
Clock runs continuously.)

FIGURE IO.Continuous Conversion with Internal Clock. (Conversion
is initiated by the 14th'~lock pulse. Clock runs
continuously. The oscillator formed by gates 2 and 3
ins.ures that th'e conversion process will start when logic
power is first turned on.)

SHORT CYCLE FEATURE
The ADCSO may be ope~ated at faster speeds for
resolutions. less than 10 or 12 bits. depending on the modi:l
selected. by connecting the short cycle pin. pin 21. a~

shown in Table Ill. Conversion speeds. linearity. and
resolutions are· shown for reference.,

TABLE Ill. Short Cycle Connections and Resolutions for S- to 12-bit Resofutions ADCSO.
RESOLUTION (BITS)

8

12

10

Pin 9

Pin 28

Maximum Conversion Time( 1).
Internal Clock (~sec)
External Clock (Ilsac)

25
23

22
12

18
6

Maximum Nonlir.:-earity
At +25 0 C (% of FSR)

0,012(2)

0.048(3)

0.20(3)

Connect Pin 21

NOTE~:

i

to

Pin 30

(1) Max conversion time to maintain ±%LSB !"onlinearity error.
(2) 12 Bit Models onlY.

(3) 10 or 12 Bit M6dels.

OUTPUT DRIVE
Normally all ADCSO logic outputs will drive. 2 standard
TTL loads; however. '

Hold

FIGURE 12. Zero Droop Infinite Hold Sample/ Hold using ADCSO and a Few External Components.

ORDERING INFORMATION

xx

ADC80AG
A D Converter family
A = -25"C to +S5"C
G = Ceramic Package

T
Blank - ±14.0V to ±16.0V Supply range
Z -±II.4V to ±16.0V supply range

5-61

Resolution (No. of Bits)
10 = 10 Bits
12 = 12 Bits

,

BURR-BROWN nversion
and appears with the most significant bit (MSB) occurring
first. The serial data is synchronous with the internal
c1o<;k asshown in the timing diagram of Figure 2. The
LSB and transition values shown in Table I also apply to
the serial data output except for the CTD code.

TABLE I. InpHt Voltages. Transition Values. LSB Values. ~nd Code.oefinitions.
Binary rBIN r
Output
Analog Input
Voltage Ranges

INPUT VOLTAGE RANGE AND LSB VALUES

Defined As:

Code

COB
orCTC'

Designation

One Le..t
Significant
Bit(LSBr

±10V

FSR

±2.5V

±5V
COB "
orCTC'

Oto+l0V

COB
orCTC'

CSB"

5V

10V

Oto+5V

Oto +20V

, CSB"

CSB"

211

20V

2""

10V

5V

21f

211

2""

2"

2""

20V

n";8

78.13mV

39.08mV'

19.53ri1V

39.06mV

'19.53mV

78.13mV

+FuliScale
MidScale
-FUll Scale

. +10V -3/2LSB

+5V -3/2LSB
0
-5V+1/2LSB

+5V-3/2LSB
+2.5V·
a,+ 1/2LSB

+20V -3/2LSB
+10V
0+ 1/2LSB

Transition Values
MSB
LSB
000 ", 000'"
011 ".111
111." 110

0
-10V +lI2LSB

+2.5 -3I2LSB +10V -3I2LSB
+5V
'0
-2.5V +lI2LSB
0+ 1/2LSB

'COB = Complementary ofise! Binary 'CTC = Complementary Two's complement- obtained
"CSB = Complementary Straight
' _ _ by using the complement of the mostwsignificant bit
Binary
(MSBr. MSB is avaliable o,n pin-12.

'''0' is the Transition

BII.
Voltages given are the
nominal value for transition

to the code specified.

5-66

DISCUSSION OF
SPECIFICATIONS
The ADC82 is specified to provide critical performance
criteria for a wide variety of applications. The most
critical specifications for an AI D converter are linearity,
drift, gain and offset errors, and conversion speed effects
on accuracy. The ADC82 is factory trimmed and tested
for all critical key specifications.
GAIN AND OFFSET ERROR
Initial gain and offset errors are factory trimmed to
±O.OS% ofFSR at +25"C for both theO to+IOand ± IOV
ranges. No external adjustment is required to obtain
initial absolute accuracies of±1 LSB. When using one of
the other input signal ranges or when even greater initial
accuracy is desired these errors may be trimmed to zero
by connecting external potentiometers as shown in
Figures 9 and 10.
ACCURACY DRIFT VS TEMPERATURE
Three major drift parameters degrade AI D converter
accuracy over temperature; they are gain, offset and
linearity drift. The worst-case accuracy drift is the
summation of all three drift errors over temperature.
Statistically, these errors do not add algebraically, but
are random variables which behave as root-sum squared
(RSS) or la errors as follows:
RSS = J E/ + E,,' + E/
Where Eg = gain drift error (ppm/"C)
E" = offset drift error (ppm of FSR/"C)
E, = Linearity error (ppm of FSR/"C)
For unipolar operation, the total RSS drift is ±49.0ppml
"c and for bipolar operation, the total RSS drift is ±56.8
. ppmj"c.
ACCURACY VS SPEED
In successive approximation AI D converters, the conversion speed affects linearity and differential linearity
errors. Conversion speed and its effect on linearity and
differential linearity errors for the ADC82 are shown in
Typical Performance Curves:
The ADC82 conversion speeds are specified for a
maximum linearity error of±1 12LSB and a differential
linearity error of± I I 2LSB with the internal clock. Faster
conversion speeds are possible with an external clock (see
Figures 6 and 7.
POWER SUPPLY SENSITIVITY
Changes in the DC power supplies will affect the
accuracy of the ADC82. The ADC82 power supply
sensitivity is speCified for±O.006% ofFSR/%Vs for-15V
and +5V supplies and ±O.02% of FSR/%Vs for +ISV
supplies. Normally, regulated power supplies with 1% or
less ripple are recommended for use with the ADC82. See
layout precautions a.nd power supply decoupling below.

to the unit as possible, preferably to a large ground plane
under the ADC82. If these grounds must be run separately, use. wide conductor pattern and aO.OI~FtoO.I~F
non polarized bypass capacitor between analog and digital
commons at the unit. Low impedance analog and digital
common returns are essential for low noise performance.
Coupling between analog inputs and digital lines should
be minimized by careful layout.
POWER SUPPLY DECOUPLING

The power supplies should be bypassed with tantalum or
electrolytic type capacitors as shown in Figure 3 to obtain
noise free operation. These capacitors should be located
close to the ADC82. I~F electrolytic type capacitors
should by bypassed with O.OI~F ceramic capacitors for
improved high frequency performance.

@)
+5V

OIG.
COM.

® --I
BIPOLAR t;;:\

OFFSET
AN'A. COM.

\!!I

hlSAR

7.Bkll

'N.. +

®----.J..

VREF

FIGURE 4. ADC82 Input Scaling Circuit.
TABLE II. ADC82 Input Scaling Connection.
Input
Signal

LAYOUT AND
OPERATING INSTRUCTIONS
LAYOUT PRECAUTIONS

Analog and digital commons are not connected internally
in the ADC82 but should be connected together as close

5-67

Output

Range

Code

±10V
±5V
±2.5V
01o+5V
o to+l0V
Oto+20V

COBo,CTC
COBo,CTC
COBo,.CTC
CSB
CSB
CSB

Connect
Pin 16
To Pin

Connect
Pin 15
To

Connect
Input
Signal To

18
18
18
17
17

Input Signal
Open
Pin 18
Pin 18
Open
Input Signal

15
14
14
14
14
15

17

~
~

CI

c

CONV~RTER

INITIALIZATION
On po'\Ver,~p • .the ~tate of the "ADC internal circUitry is
indeterminate. One conversion cycle is required to initialize the. converter after power is applied.

CONVERT
COMMAND

Jl

23

CONVERT
COMMAND

.
.. 3
CLOCK OPTIONS
The ADC82 is extremely versatile in . that .it can "e.
. operated in several different modes with either internal or
external clock, Most ofthese options can be·implemented
with ·nothing more than an inexpensive quad 2"input
,NAND Gate (7400) as shownirt Figure 5 through 8.
~.

.~

exTERNAL
::LOCK

CLOCK
IN

~,

CLOCK
OUT

CONVERSION INITIATED BY
FAUINS EDGE OF THE CONVERT
COMMAND. THE INTERNAL·
CLOCK RUNS ONLY
DURING CONVERSION.

CONVERSION IS INITIATED
BY 10TH CLOCK PULSE.
CLOCK RUNS CONTINUOUSLY.

FIGURE 6. Continuous Conversion with External Clock.

FIGURE 5. Internal Clock-Normal Operating Mode.

n

~NVERT
1~COMMAND

Jum,O----:-----"11'o---=L!J

CLOCK
IN

EXTERNAL
CLOCK

CONVERT
COMMAND·
NO
CONNECTION

CONVERSION INITIATED BY RISING EDGE OF
CONVERT COMMAND. THE CONVERT COMMAND MUST
BE SYNCHRONIZED WITH CLOCK. CONVERT
COMMAND MUST BE LOW DURING CONVERSION.

FIGURE 7. Continuous External Clock.
470F

~
880kli

.

470pF

·3

CONVERT
COMMAND

CONVERSION IS INmATED BY THE 10TH
CUICK PULSE. CLOCK RUNS CONTINUOUSLY.
THE OSCILLATOR FORMED BY GATES 2 AND 3
INSURE THAT THE CONVERSION PROCESS WILL
START WHEN LOGIC POWER IS FIRST TURNED
ON. (THESE VALUES GIVE,. 2IIOnuc CO.VERT
COMMANDI.

FIG URE 8. Continuous Conversion with Internal Clock.

5-68

OPTIONAL EXTERNAL GAIN
AND OFFSET ADJUSTMENTS

III

!

Ib)

+15V

Gain and offset errors may be trimmed to zero using
external gain and offset trim potentiometers connected to
the ADC82
shown in F1gures 9 and 10. Multit~rn
potentiometers with 100ppml"C or better TCR's are
recommended for minimum drift o~er temperature and
time. These pots may be any value from 10k!} to lOOk!}.
All resistors should be 20% carbon or better. Pin 13 (Gain
Adjust) 'may be left open if no external adjustment is
required.

as

ADJUSTMENT PROCEDURE
Offset - Connect the Offset potentiometer as shown in
Figure 9.. Sweep the input through the end point
transition voltage that should cause an output transition
to all bits off (E().'~'').

IMIl
10blTO
~IOOI(/l
CaMP
IN .

OFFSET
ADJUST

+15V

Itr.\. IOkIl

10kllTO
lDOkll
OFFSET
ADJUST

IOku

COMP.
lOOkIl ~
1~'111
IN

-=

·15V

..

·15V

FIGURE 9. Two methods of Connecting Optional
Offset Adjust with a ±I.O% of
FSR Range of Adjustment.
(bl

(I)

+15V

Adjust the Offset potentiometer until the actual end point
transition voltage occurs at E(),'~F. The ideal transition
voltage values of the input are given in Table I.

+15V

IOknTO
lOOku
GAIN
ADJUST

10kn TO
100ku
GAIN
ADJUST

Gain - Connect the Gain adjust potentiometer as shown
in Figure 10. Sweep the input through the end point
transition voltage that should cause output transitions to
all bits on (E7~). Adjust the Gain potentiometer until the
actual end point transition voltage occurs at EW::.

·15V

Table I details the transition voltage levels required.

·15V

FIGURE 10. Two Methods of Connecting Optional
Gain Adjust with a ±IO% Range of
Adjustment.

ORDERING INFORMATION
ADC82A

x

--~=---- ~
G Ceramic Package

AI D Converter Family
A = +25"C to +85"C

=

M = Metal Hermetic Package

5-69

'

.. '.':

ADC'84
AD'C85

'BURR-BROWN@)

IElElI
'"",'.

IC ANALOG-TO-OIGITAL CONVERTERS
FEATURES
• COM PACT DESIGN -Self-contained with Internal clock.
comp.arator. reference. and input buffer amplifier' '
32-pln car_mlc or hermetic matal package
• FAST CONVERSION SPEEDS
Provide Fast Sigilal Sampling Rates
12-blts - IOllsec. 10-bits, 61lsec
,
Faster conversion speeds obtainable with
"Short-Cycling" and adJustable clock rate
• LOW COST - AOC84KG-12

DESCRIPTIQN
The ADC84 and ADC85 families of 10- and 12-bit
analog-to-digital converters utilize state-of-the-art
IC and laser-trimmed thin-film components, and are
packaged in ~,.compa(;t ~2,p.in duaHn-line packages.
Complete with internai r~ference ihd input buffer
amplifier, they offer versatility and performance
formerly offered only in larger modular or rackmount packages. "
'
Thin-film internal scaling resistors are provided for
'the selection of analog input signal ranges' of±2.5V,
±5V",±IOV,Oto+5VorO to+IOV. Gain and offset
errors may be exteplally trimlTle~1 to zero, o,ffering
initial accuracies of better than ±O.O 12% (±l j 2LSB).
The fast conversion speeds of lOll sec for 12-bit and
61lsec for IO-bit resolution make these ADC's
excellent for a wide range of applications where
system throughput sampling rates from 100kHz to
120kHz are required. In addition, they may be short
cycled and the clock rate control may be used to
obtain faster conversion speeds at low resolutions.
Data is available in parallel and serial form with
corresponding clock and status signals. All digital
input and output signals are DTLj TTL-compatible.
Power supply voltages are ±15VDC and +5VDC.
Inllmilianal AlfIIOrIlnllUBtrlal Park· P.O. Box 11400· TUClGn, Arizona 85734· Tel.1602l 746-1111 . Twx: 911).952·1111 • Cable: BBRCORP· Telex: 66-6491

5-70

the same for increasing analog input signals. Burr-Brown
also guarantees that these converters will have no missing
codes over a specified terilperture range.

DISCUSSION OF
PERFORMANCE
The accuracy of a successive approximation AI D
converter is described by the transfer function shown in
Figure I. All successive approximation AI D converters
have an inherent Quantization Error of±1/2LSB. The
remaining errors in the AI D converter are combinations
of a nalog errors due to the linear circuitry. matching and
tracking properties of the ladder and scaling networks,
powersupply rejection. and reference errors. In summary.
these errors consist of initial errors including Gain.
Offset. Linearity. Differential Linearity and Power
Supply Sensitivity. Initial Gain and Offset errors may be
adjusted to zero. Gain drift over temperature rotates the
line (Figure I) about the zero or minus full scale point (all
bits OFF) and Offset drift shifts the line left or right over
the operating temperature range. Linearity error is
. unadjustable and is the most meaningful indicator of
AI D converter accuracy. Linearity error is the deviation
of an actual bit transition from the ideal transition value
at any level over the range of the AI D converter. A
Differential Linearity error of ± I I 2LSB means that the
width of each bit step overt he range ofthe AI D converter
is ILSB±1/2LSB.
The ADC84 and ADC85 are also monotonic, assuring
that the output digital code either increases or remains

000 ... 000

.....

Eo;

000 ... 001

co
co

011 ... 101

co
!:!.

011 ... 110

.....

........=
=
....

011 ... III

co

100 ... 000

;!:

100 ... 001

!!!
co

III ... 110
III ... III

~~

tl=L

I

ON
EIN

.FSR ' \
ANALOG INPUT
2
EIN OFF
OSEE TABLE I FOR DIGITAL CODE DEFINITIONS.

+FSR ·ILSB
2

FIGURE I. Input vs Output for an Ideal Bipolar AI D
Converter.

TIMING CONSIDERATIONS
The timing diagram of the ADC's (see Figure 2) assumes
an analog input such that the positive true digital word
10011000100 I exists. The output will be complementary
as shown in Figure 2 (0 1100 1110 110 is the digital output)..
MAXIMUM THROUGHPUT TlME(2)

CONVERTII!
COMMAND
INTERNAL
CLOCK
STATUS IEOC)
MSB
BIU

BIT3
BIT 4
BITS
BIT 6

BIT7
BIT 8
BITD
BIT 10

BIT II

"0,,1

LSB
SERIAL(3)
DATA
OUT

r-i

OPTIONAL
"---1 j--:
r-1
~-l
;--i ;-- •• - - 1 r-j:---EXTERNAL
L'
L..,
.. ..I
L..!
LJ
L.J
L...
L~
LJ
L..J
LJ
U
LJ
LJ
CLOCK
I I NOTES:
1188 pg. ~oonsec mix
I I. The cllllverl _mimi mUll bill 1l1li 50nsec wIde and milstl'1lmaln low "rIng I conversion. The _lrslDn II Inhlllld by the 'fllllng
,
~ adg," of Ihe canver! cammlnd. 2.10.5.... lar 12·blhland 6A~lec 'er lO-blhl. a Ulllrllllng edge of cloct \0 strabismal outpul

:--1 r-ll"--:

-I

FIGURE 2. ADC84 and ADC85 Timing Diagram.

r-" r-1

SPECIFICATIONS
ELECTRICAL
T yplca
. I at+25°C and rated power'supplles otherwise noted ,
MODEL'
ADC85

RESC)umON

10

12

10

INPUT
ANALOG'INPUTS
Voltages Ranges.
Bipolar
Unipolar
Imped~nce I Direct In,?u!1
to +5V. ±2.5V
o to HOY. ±SV
·±IOY.
Buffer Amplifier

ADC84KG
10'
12

I

UNITS
BITS

±2.S. ±S. ±10
o.to +S. 0 to +10

V
V

2.S
S
10

kll
kll
kll

100
SO

Mil
nA

2

~sec

o

Imped~nce,

I

ADC85C.

I

12

.,

min

Bias Current
Settling "ime
to 0.01% for 20V steplll
~IGITAL INPUtSI2I

'Convert Command
Logic Loading
External Clock
I "AN""ER CHARACTERISTICS
ERROR
Gain Error
Offset Error
Unipolar
. Bipolar
Linearity Error. max(4)

Positive pulse 50nsec wide, min. Trailing Edge
"1" to "0" initiates conversion·
1
Sea External Clock paragraph

I

±O.O12

Inherent Quantization Error

:t1/2

Differential Linearity Error
Nco Missing Codes
Power Supply Sensitivity
±lSVDC
+SVDC
DRIFT
Specification Temperature Range

±1/2

Gain, max

Offset
Unipolar
Bipolar
Linearity, max
Monotonlclty
CONVERSION SPEED. I max ;15!161
OUTPUT
DIGITAL DATA
All codes complementary
Parallel
Oulpul Codesl71
Unipolar
Bipolar
Oulpul Drive
Serial Dilta Codes I NRZ,

-2Sto +85

I

o to +70

I

o to +70

,.'
-25 to +8S
±15
±20
±3
±10
±3

±3
±7
±2

.6

10

..

POWER REQUIREMENTS
Raled Vollllges
Range for Rated Accuracy
Supply Drain +15VDC
-15VDC
+5VDC
TEMPER,ATURE RANGE
Specification
Operati~g rderated specs)
Siorage

(see

PACKAGE
Mechanical
. Speclfi.catlo~s) ..

.
±O.048

I o to +70

I

I·Oto+70

"

Oto "'70
±25

+3
±12
±3
±3
Guaranteed
6
I 10

±30

±3

=3

::20

::15

±3

I

I

6

°C
ppm/OC

+3
+15
±3

ppm 01 FSR/oC
ppm 01 FSR/oC
ppm 01 FSR 1°C

10

~sec

TTL Loads
TTL Loads

Logic "1 ". during conversion
2

TTL Loads

I

1:35

I

1.9

±5

I

±5

I

±10

2
I
6.3

1.35

I

1.9

I

1.35

TTL Loads
MHz
V

tl0

I

±20

I

':20

ppm/oC

~A

200
I·

±15. +5
4.75105.25 and ±14.510 ±15.5
+45
:35
+120

I

-5510 +125

0(;

2

1.9

-2510 +85

%01 FSRI31
%ofFSR
%olFSR
%ofFSR
LSB
LSB

% 01 FSR1%Vs
%olFSR/%Vs

o to +70
±40

I ±0.012

CSB
COB.CTC.
2
CSB.COB

Slat us
Slatus Oulpul Drive
Inlernal Clock
Clock Oulpul Drive

INTERNAL REF. VOLTAGE
Max External Current With no
degradation of Specifications
-Tempco of Drift. max

Oto+70

±O.O04
±0.001

Output Drive

Frequenc:yl6~

%

±O.1 I Adjustable to zero I
to zero
,.
±O.OS
±0.1
±0.012 I
I ±O.048
.A~justable

±O.048

TTL Load

010170
-5510 +85, 110°C case Temp.
-S510 +125

.,Metal r'Hermeti'C-i

5-72

.

"

+45
-35
+70
010 +70
-S510 +125
Ceramic

V
V
mA
mA
mA

oC
°C
°C

4. Error shown Is the same as ±1I2LSB max linearity error In % of FSR.
'5. Oon....lon time may be shortened with ''short cycle" set for lower
resolution, See Table III.
6. Internal Clock Is externally adjustable.
7. See Table II. CSB - Complementary Straight Binary. COBComplementary Offset Binary. CTC - Complementary Two'.
Complement.

NOTES:
1. Thissetlling time adds to conversion spaed when buffer is connected to
input.
2. DTL/TTL compatible; i.e., Logic "0" =0.8V max, Logic"1" =2.011, min for
inputs. Fordigital outputs, Logic "0" = +0.4V max, Logic "I" = 2.4V, min.
3. FSR means Full Scale Range - for example, unit connected for ±10V
range has 20V FSR.

CONNECTION DIAGRAM
(TOPVIEWI
Serial Out

Bit 12 (LSB for
12 bitSI
Bitll

-15VDC Supply
Buffer!n

Bit 10 (LSB for
10 bits)
Bit 9

Buffer Out

BitS

+15VDC Supply

Bit7

Gain Adjust

Bit 6

Analog Common

Blt5

R220V Range

Bit4

R, 10V Range

Bit3

Bipolar Offset

Bit 2

C?mparator In

i§

Bitl (MSBI

Convert Commandt

C

B1i1 iMSBI

Status

Short Cycle

=

Clock Out

Dig. Common·

Ref. Out (+6.3VI

+5VDC SUpply

Clock Rate Control

·Dlgital Common is Internally connected to case. (ADC85 and ADC85C onlyl
t If an external clock Is used, connect the clock to Pin·21 (conv. command.,
ISee Figure 2 and External Clock paragraphl.

TYPICAL PERFORMANCE CURVES
0.20
0,175
i:

~

~

g

w

:E..
"e:
:::;

LINEARITY ERROR VS CONVERSION SPEED

1" 1
,;i~SB I II :1'8·Bit Operation

Ir

,

For8Blts

0.150

\

0.125
0.10
0.075 ,,;..
0.05
0.025

-

--

~

-

0.20
0.175

1o-blt
°reration

1I2LSB For

_'21Its_l~

DIFFERENTIAL LINEARITY VS CONVERSION SPEED

lI~sBfr

I

,

'"-

g

0.1SO

w
l:-

.

0.125

e:

\

0.10



~

~

>

..

8.;t
e iil

+0.10

g

0.01

~

0.006

-0.05

0.004

-0.10

0.002

-0.15

0.001

/
~

V

o

+25

+70

+S5

Temperature (OCI

5-73

10

r,

~
J

+15VDC

~J

-I
I+5VDC

·25

10

Co,:,version Time (JtSec)

0.1

fe

-

-

).

4

10

12-Blt
,Operation

100
lk
Frequency (Hzl

b/

10k

lOOk

DEFINITION' OF DIGIT'AL:'C()DES
PARALLEL DATA

SERtAL DATA

Three binary codes are ~vaiiable onthe.ADC84 and
ADC85 parallel output; they are cornplernentary(logic
"0" is true) straight binary (CSB) for unipoiar input
signal ranges and cornplernentary two's complernent
. (CTC) and cornplernentary offset binary ,(COB) for'
bipolar input singal ranges.
.
Table I describes the LSB,transition values 'and code
definitions for each possible analog input signal ningll for
8-, 10-, and l2-bit resolutions.

.

Twostraighi'binary·.'~ompiel"ent&s shpwn in the tirning diagrarn of Figure 2. The
LS~and transition values shown in Table I also apply to
the serial data output e~cept for the CTC code.

TABLE!. Input Voltages, Trans'ition Values, LSB Values, and Code Definitions .
. Binary I BIN I
Output

.If:'1PUT VOL TAG.E RANGE AND LSB VALUES

:

Analog Input
Voltage Range.

Defil\ed A~::

Code

~.

,-

..

±10V
COB'
orCTC'"

Designation
One Least
Significant

Bit ILSBI

±5V

±2.5V·

COS' .'
or'eTC'"

COB'
.orCTC"·

10V

FSR
2n
n=8

20V
2n
78.13mV

39.08mV

5V
2n
19.53mV

n= 10
n= 12

19.53mV
4.88mV ,

9.77mV
2.44mV

4.88mV
1.22mV

. 2"

oto +10V

Oto+5V

CSB"

CSB"

10V
2n
39.06mV

5V
2n
19.53mV

9.77mV·
2.44mV

4.88mV
1.22mV

Transition Values

MSB

LSB

000 ... 000 ..••
011 ... 111
111 ... 110
. 'COB ~ Complementary Offset Binary
"CSB = Complementary Straight
Binary

+FuIiScale'
MIL Scale
-Full Scale

+10V'-3i2LSB.
0
-10V +1/2LSB

+5V-3/2LSB
0
-5V + 112LSB '

+2.5 -3/2LSB
0
-2,5V+1/2LSB

"'CTC ~. Complementary Two'.' complement· obtained

+10V -3I2LSB
+5V
0+ 1/2LSB

+5V-3/2LSB
+2.5V
0+ 1/2LSB

**uVoltages given are the

by using th~ complement of tf:1e most-S!gn!ficaot

no'mfnal value for tra'nsition

bit IMSElI: MSB is availa!!le on pin-13.

19 the code speciiied.

:

DISCUSSION
,OF SPECIFICATIONS
,
'
The ADC8~ and ADC85 are spe~ified to pr~vide critical
perforrnance criteria for a wide variety of applications.
The rnost critical specifications for an AI D converter are
linearity, drift, gain and offset errors arid conversion
speed effects on accuracy. These ADC's are factorytri~rned and tested for all critical key specifications.
GAIN AND OFFSET ERROR
Initial Gain and Offset:errors are factory-trirnrned to
±O.l %. of FSR (±0.05% for unipolar offset) at 25"C.
T1ieseel'rors may be trirnrned to zero by connecting
external trirn' pbtentiorneters as shown on next page.

For the ADC85-12 operating in the ,uni'polar rnode the' .
total RSS drift is ±15.42pprni"C and for bipolar operation the total RSS drift is ±:16.7pprn/"C.
ACCURACY VS SPEED
·In successive approxirnati-on AI D converters, the conversion speed affects linearity and differential li'nearity
errors. Conversion speed and its effect on linearity and
differential linearity errors 'for the ADC84 and ADC85
,are sho~n in Typical PerformanC7 ~\Irv~s.
The conversion speeds are specifii:d for a rnaxirnurn
linearity error of ± 1I 2LS B with the internal clock. Faster
conversion speeds are possible (see Clock Rate Control
Alternate Connections).

ACCURACY DRIFT VS TEMPERATURE
Three rnajor drift pararneters' degrade AI D converter
accuracy over temperature; they are gain, offset and
linearity drift. The worst-case acc\lracy drift is the
surnrnation of all three drift errors. OVer tern perature.
Statistically, these errors do not add 'algebraically, but
are randorn variables which behave as·root"Surn-squared
(RSS) or 10 errors as follows:
. RSS = J El + E02 + Ee2
where eg = 'gain drift error (pprnj"C)
. EO == offset drift error (pprnofFSRj"C)
EC = linearity error (pprn of FSRj"C)

POWE~. SUPPLY SENSmVITY

Chariges in the DC power supplies will affect accuracy.
The ADC84 and theADC85 power supply sensitivity is
specifiedf9r :to.003% of FS R/ %V,for ±lSVDC supplies
an~±0.00l5%ofFSJy%Vsfor,.+5NDC supplies.
N orrnal!y, regulated power supplies with I% or less ripple
,are rt!coriunended for use with these AD.C;:'s. See Layout
Preca'utionsand Power Supply Decouplingon next page.

5-74

LAYOUT AND OPERATING INSTRUCTIONS
LAYOUT PRECAUTIONS
Analog and digital commons are not connected internally
in the ADC84 and ADC85, but should be connected
together as close to the unit as possibfe, preferably to a
large ground plane underthe ADC. Ifthese grounds must
be run separately, use wide conductor patte'rn and a
0.0 IIlF to O. IIlFnonpolarized bypass capacitor between
analog and digital commons-at the unit. Low impedance
analog and digital common returns are essential for low
noise performance. Coupling between analog inputs and
digital lines should be minimized by careful layout.

INPUT SCALING
The analog input should be scaled as close to the
maximum input signal range as possible in order to
utilize the maximum signal, resolution of the A/ D
converter. Connect the input signal as shown in Table II.
See Figure 4 for circuit details.
'

BUFFER
INPUT

CDMP.

POWER SUPPLY DECOUPLING
The power supplies should be bypassed with tantahim or
electrolytic type capacitors as shown in Figure 3 to
obtain noise free operation. These capacitors should be
located close to the ADC. III F electrolytic type capacitors
should be bypassed with O.OIIlF ceramic capacitors for
improved high frequency performance.

IN

BIPOLAR

OFFSET

FI G U R E 4. I nput Scaling Circuit - ADC84 and ADC85.
For
Bunered
Inpur

,
+SVDC ..
DIG.
COM.

•

:::tf

I

U

@)
@

®
@
@

or: ..

~

TABLE II ADC84andADC85 Input ScalingCcinnections.~

Input
Signel

Connect Connect
Pin 23
Pin 25
To Pin
To
'Input
±10V
COB or CTC
Signal'·
22
COB or CTC
±5V
22
Open
±2,5V
22
Pin 22
COB or CTC
Pin 22
Oto+5V
CSB
26
,Open
Oto +10V
CSB
26

·15VDC

Rang.

l"F
I+
• COM.
ANA.
',,,F
I+, .. +15VDC

FIGURE 3. Recommended Power Supply Decoupling.

Output
Code

For
Direct Input
(••• note)
Connect
Connect
Input
Pin 29
Slgn.1
To Pin
To Pin
25
24
24
24

25
24
24
24
24

2'4

"Connect to Pm 29 or mput signal as shown In next two columns.
··The. input signal Is connected to Pin 30 if the buffer amplifier is used.
NOTE,: lIthe buner amplifier is not used, the input Pin 30 must begrounded
IPin,26),

OPTIONAL EXTERNAL GAIN AND OFFSET ADJUSTMENTS

Gain and Offseterro~s may be trimmed to zero using
external gain and offset trim potentiometers connected to
the ADC as shown in Figures 5 and 6. Multiturn
potentiometers with IOOppm/"C or better TCR's are
recommended for minimum drift over temperature and
time. These pots may be any value from 10ko. to IOOko..
All resistors should be 20% carbon or better. Pin 27 (Gain
Adjust) and Pin 22 (Offset Adjust) may be left open if no
external adjustment. is required.

(I)

+15VDC

'-"-----.!.!~~

~yy.....---

COMP IN
.

~

(bl

10lul
TO

"+15VOC

I-AIIrv-.-J\I8DN-kl....l _ f f£::l
OFFSET
22kn
ADJUST

lookn
' OFFSET ,
ADJUST

·15VOC

ADJUSTMENT PROCEDURE
Offset - Connect the Offset potentiometer as shown in
Figure 5. Sweep the input through the end point transition
voltage that should cause an output transition to all bits
off (E(V~».

·15VOC

FIGURE 5. Two Methods of Connecting Optional
Offset Adjust with a 0.4% of FSR Range
of Adjustment.
(b)

(I)

+15VDC

Adjust the Offset potentiometer until the actual end point
transition voltage occurs at E(~~F. The ideal transition
voltage values of the input are given in Table I.

f

IOkn
TO
(i:i......~ lOOk!!
'C'..L 0.01 F
BAIN
I'
ADJUST

GAIN
ADJUST,

Gain - Con~~ct the Gain adjust potentiometer as shown

IOMn

®1"

in Figure 6. Sweep the input through the end point
transition voltage that should cause an output transition
voltage to all bits ori (E?~). Adjust the Gain potentiometer until the actual end point transition voltage occurs
at E?~.
Table I details the transition voltage levels required.

ANA.
COM.'

·15VOC

270kn +15VO;:n,'

270kn

27}..,-~V"I~M-

6.Bkn

f

lookn

~~~UST

·15VOC

FIGURE 6. Two Methods of Connecting Optional
Gain Adjust with a 0:6% Range
of Adjustrrient.
'

5-75

C

CLOCK RATE; CONTROL
• ';)U)DITIONAL .COftiNECTIONSREQUIRED:
ALTERNATE CONNECTIONS
The ADC84 andADC8S may be operated 'at faster
If adjustment of the Clock ~~te is desired ~or faster
sl?~s fo~resolutionslen thall 12 bitsb¥.,connecting the
conversion spe~ps,' the Clock' Rate Control may be
Sport Cycle input, pin 1,4; as shown in Table III. C9nverconnected to aJ;l externaI'multiturri trim pote!1tiometer
sion speeds, linearity 8Jld resoMi9nare shown for referwith TCR of ±IOOppm/oC or less as shown in Figures
ence. ,Specifications, for IO-bit units assume connections
as shown below.
.
,
7 Aarid 7B.lfthe potentiometerisconne~tedto-15VDC,
,conversion time oan be increased as shown in Figure 8. If
TABLE III. Short Cycle Corinectionsand Specifications
these adJustments are used, dele:te the connections shown
for 8- to 12-Bit Resolution.
in Table III for pin 17. See Typical Performance CUrves
8
12
10
for nonlinearity. error vs. clock frequency, and Figure 8
. RESOLUTION (BIts)
Connect Pin 17 to (1)
Pin15
Pin16
Pin 28
for the effect of the control voltage on clock speed.
Connect Pin 14 to
Pin16
Pin2 , Pin4
, Operation With Clock Rate Control voltage of less than
Maximum Conversion
-IVDC is not recommended.
Speed 1~8eCI(2)
10
6
4
"

Manimum Nonlinearity
at25°C 1% ofFSR,

"

0,012(3)

0.048(4) ,

0.2014)

..5VOCI·

CLOCK ' t::\
RATE
\!!,ICONTROL

-- - _

"'

2kn
_
-

NOTES:

CLOCK
FREQUENCY
ADJUST
112-BIT RESOLUTIONI
RANGE OF ADJUSTMENT IS
10,..ac to 6.8~88C

t

FIGURE 7A. 12-Bit Clock Rate Control Optional Fine
" . Adjust.
'

CLOCK
RATE
CONTROL

+5VOC

CLOCK
lilcn
FREQUENCY
, .
ADJUST
.
, 18- OR III-BIT RESOLUTIOrq
RAIIIIE OF ADJUSTMENT IS
....
8.014ac to 4.O~1IC lor 10-4111 llId
3.6_ FOR B-BIT RESOLUTIONS.

0-----

,

..

FIGURE 7B. 8~Bit Clock·RateCont,rol Optional Fine
'Adjust."
"

.4
8
12
CONTROL VOLTAlIE ON PIN 17

1. Cpnnect on,ly if clock rate control is not used.
2. Max. conversion speeds to maintain ±1I2LSB nonlinearity error.
3, 12-bit mOdels only.
, 4,10- or 12-bit models.'

CONVERTER INITIALIZATION
'On power-up, the state .of the ADC internal circuitry is
indeterminate. One conversion cycle is required to initialize the converter after power is applied.
.OUTPUT D,RIVE
Normally all ADC84 and ADC85 logic outputswill drive
2 standard TTL-loads; however, if long digital lines must
be driven, external logic buffers are recommended.
HEAT DISSIPATION
The ADC8:4 and ADC8,5 dissipate apprpximatelY'1 ;2W
and the packages have a case-to-ambient thermal resiS:talice «ok·, should be lowered by a heat-siilk or by forced
air over the surface of the package). See Figure 9£or flt'A
requirement above 70n e. If the converter is mounted on a
PC card, improved thermal contact with the copper
ground plane under the case can be achieved using a
silicone heat-sink compound. On a O.062-inch thick PC
card with 16 square-inch minimum area. this technique
will allow operation to 85"e.
,',
'

14 15

FIGURE 8. Conversion Time vs Clock Speed Control
VoltaJ!:e.
EXTERNAL CLOCK
lEan external clock is used, cO,linect the external clock to
convert commaQd, pin 21. The convert command shown
in Figure 2 is' not used. After each' conversion is
completed, a ni!w conversion cycle will automatically
start of the first falling' edge of the external clock
following the completion of conversion. The clock-out
signal w\ll remain as shown in Figure 2 even if an external
clock is used. The external clock pulse must be a negative
,going pulse ~ith.a width between IOOnsec and 200nsec as
shown in Figure 2.

25?----1Ioi..

10
O~I~~+-+-+-+-+-+-~~~~_

BD

.10

BD

100

AMBIENT TEMmATURE lOCI

FIGURE 9. 8CA Requirement Above 7ane.

5-76

110,

HIGH RELIABILITY AID CONVERTERS.
Each of the ADC85 models are available screened to the
requirements of the Burr-Brown Q-Program. which
consists of a sequence of thermal and mechanical stress

procedures. plus a verific~tion of package hermeticity.
The diagram below illustrates the screening sequence
wh;ich is applied to 100% of the Q-Screened AI D
converters .

High Temp.
Storage
(MIL-STD-883)

Temperature
Cycling
(MIL-STD-883)

. Hermetlclly
GroolLeok
(MIL-STD-883)

Hermltlelly
Fine Leak
(MIL-STD-883)

Method 1008
Condition B
+125°C
24 Hours

Method 1010
Condition B
-55 to +25°C
10 Cycles

Method 1014
Condition C
Step 1
Fluorocarbon

Method 1014
Condition A
Helium
5 x H)"7 cc/sec

Bum-In
(MIL-STD-883)

Centrifuge
(UIL-STD-883)

Method 1015
Condition 0
168 Hours
+700C IADC85C,
+85°C I ADC85,

Method 2001
2.000 G

Y, Axis

MECHANICAL

(J L+:t:. . . . .

~"'''''''''''',~

J

AD.C84

ADC8S, ADC85C

1

"

~

--.l

1 "---.,.,
CJ

A~

(
•

,

G

• ... r--

c- ,

H

CI
C

rn

\
•

..J I!!.IIIIIIII ~ ~

NOTE:
Leads in true position
within 0.D10-(0.255mm,
R at MMC at seating plane .

..

r-!* ••••••••••••••
Pin 1 identified on
bottom by contrasting
color of gl... or

A

NOTE:
leads in true position
within 0.01O-,O.255inml
R at MMC al sealing plane.
INCHES
DIM

.

MIN

MAX

,.,...

1.1"

1.700
.170
,01'

f

0
H
K
L

N

"

1.710

"ID.AlIC
.110
.'10
.800 IIAIIC
.010
.110

....

MILLIMETERS
MIN
MAX

..... a_
...., ....
........ ....
.'00
..., '.30
....

... .-.-

A

C
n

.'30

43.1.

....70

11.13

1.27
2.MIlASIC
2.7'
0.311
22._AlIC

...

2.7.

square corner.

..........•.....

32

PINS: Pin material and plating
composition conform to method
2003 (solderability, of MILSTD-8a3 (e~cePt paragraph 3.21
CASE: Ceramic
MATING CONNECTOR: 2302MC
Set of two 16-pin strips
WEIGHT: 13 grams (0.46 OZ. 1

17

Pin numbers shown for reference only.
Numbers may not be marked on p~kage.
PINS: Pin materia( and plating
composition conform to method
INCHES
MlUJM£:TERS

~~~':;~:~:~~~~~~;!~~3.21
~
,~:
CASE: Kovar, Nickel plated
•
MATING CONNECTOR: 2302MC

c

Set of two 16-pin strips
WEIGHT: 13 grams (0.46 OZ.I

G
H

I)

K

0.. .

1.120
'.170
.01'

ORDERING INFORMATION
ADCXX

XX

~
Grade:

ADC85
ADC84

:.:'

1.1eo
.210
.021

• .411
2 .....
'.32
... .
0.41
0.53
2.MIASIC
2.M
3.N
3081
7.82

.100 Mile
.100
.140
.1110

Blank (-25"C. +85"CXADC85 only)
C (O"C. +70"CXA DC85 only)
KG iO"c. +70"C)(ADC84 only)

5-77

Resolut·ion:
10= 10 bits

12= 12 bits

~

::':

.3DD

.800I,uIC
.100
.10t0

'.30

CQ

c.:»

a

L

..

3.M

3."

BURR-BROWN@

·AOC100·

1&:1&:11

High Resolution - Integrating
ANALOG-TO-OIGITAL CONVERTER'
FEATURES
-16·BIT RESOLUTION
-SELF·CONTAINED MODULAR PACKAGE
-LOW DRIfT
-USER·ADJUSTABLE LINEARITY
- EXPANDABLE TO 5·OIG11 BCD RESOLUTION

DESCRIPTION
The Burr-Brown Model AOClOO AID Conyerteris
.ari integrating AID Converter that utilizes the delta

sigma modulation principle. The digital equivalent of
analog signals is developed by counting a number of
pulses whost: average repetition rate is proportional
to tlie amplitude of the input signal over a fixed
lntegration period. The internal clock is externally~
adjustable to provide integration periods which are
integral rriultiples of 50Hz or 60Hz periods for
maximum powerJine noise. rejection. The· closed
conversion tOQP assures linear performance of
'±O.005% ±I count that is indeperident of clock
frequency deviations over the specified temperature
.
range of O"C to.±70':C.
The ADCIOO'is housed in a 2" x4"x 0.4" module and
operates from ±15VDC and +5VDC power. All'
digital input and output signals are TTL-compatible.
Four basic models are offered: Unipolar 4-digit BCD,
4-digit plus sign BCD, unipolar and bipolar 16-bit
binary. The binary units· are pin-programrriable for
12-, 14-, or l6-b.it resolution ..
The ADCIOO is excellent for applications which
require good accuracy and high resolution, but where
speed is not too important. Conversion speeds range
from 12msec for 12-bit binary to 30msec for 4-digit
.
plus sign BCD codes.
'

.

Digital Output Code

Inl8rnallllllll Airporllnduslrlal Park· P.O. Box 11400· Tucson, ArIzona 85734 . Tel. (602) 746-1111 . Twx: 910-952·1111 . Cable: BBRCORp· Telex: 66-6491

5-78

SPECIFICATIONS
Typical at 25°C and rated power supply unless otherwise noted.

ELECTRICAL

""""

LeecIIin.,... .................01S..
!. _ _lR.MMC . . . . ,..,..

MODEL
ADC100
RESOLUTION

DECIMAL

BINARY
. Unipolar lBipolar
USB
BOB
SMO

BCD
4 digits

4 digits 14 or
16 bits

+ sign

UNITS

14 or
16 bits

INPUT
ANALOG INPUT

Voltage Range
Maximum Safe Input Signal
Input Hias ('urrent typ max
Impedance
IJuffered
Unbuffered

o to +10 1:10 . Oto+l0 '±IO
i2SVor supply voltage, whiche~ris I.~ss
20
200
200
10(1)

200
10

200
10

200
25

v
nA
nA
Mil
kll

................... ...,,...... ...... N........

Settling Time (to 0.003%)
FSR(2) step

Buffered, max
Unbuffered, max

I DIGITAL INPUT
Convert Comma'nd

r·.·· . . . ··............ ··

25

SO
25
SO
JJsec
I
I
1
1
,",sec
TTL/UTL Compatible Logical
for
at leastck)

u."

External Clock

~ ................................... t ••• ; .......... 7

'. ". ." o.na. ........ pinL

See "Clock Operation"

TRANSFER CHARACTERISTICS

I INCHES
MIN
MAX

DIM

.05
.02
±0.005

.05
.05
.02
.D2
±0.005 ±0.005
.± I count'

.05
.05
±11.005

±5

±IO

%ofFSR
%of FSR
% of FSR(2)

4.010

100.53

101.85

1.950

2.010

49.53

51.05

9.9.

0

.019

.410
.021

G

. 100 RA IC
.150
.250

2.54 ELASIC.
6.35
3.81

.250
.350
1.800 BASIC

6.35
8.89
45.72 BASIC

A,CCURACY DRIFT
Temperature Coefficient (max)

±IO

t10

.200 BASIC

ppm of FSRLoC

.050

POWER SUPPLY SENSITIVITY
Power Supply Sensitivity, max
±15VDC
+5VDC

±0.007
±0.002

±0.004 ±0.0002 ±0.0002 % of FSR/% of
P.S. Voitage(J SV)
±0.001 ±0.002
±O.OOI % of FSR/% 0(;
P.S. Voltag';(SV)

CONVERSION TIME
(maximum with Internal ('lock)

30

30

For 12 bits - 12.5
14 bits - SO
16 bits - 200

msec

OUTPUT
DIGITAL OUTPUTS

End of Conversion

5.0B BASIC
3.81
1.27

NOTE
LeadS in trye position WIth'" 015"
'(.38lnml R @ MMC ill 5f1ltlng plane

1--1·- A

"I

CJJ
E

Pin numbe.sshOwn for referenceonl\

L

mav ~of.be mark ad on package

+.......... +............................. ..

1

36

o to +70
-25 to +85
-55 to +100

····.·.·.·+··.,.·t·.·.

72

POWER SUPPL Y
Supply Drain
+15VDC
-15VDC
+5VDC

0.53

p

TEMPERATURE

Rated Voltage
Range (max)

.150

0.48

~~r-nr-III-II-II-Il-ln-hlll-hl-I-IIII-,11 ~
I 0:::11.--J l.- --1.-0 L , -.J

TTL/DTL Compatible
All digital outputs-will drive 6 TTL
loads except the sign bit (for SMD
units) which will drive 4 TTL loads
"0" during conversion

Specification
Operating (reduced specs)
Storage

MILLIMETERS
MIN
MAX

3.9S0

ACCURACy(3)
Gain Error
Offst;!t Error
Linea'l:ity Error, max(4)'
Quantizing Error

"'"not ..........on ........

t ...................

v

37
·+·o+·· .. •.... •• .....

...

. Denoles miSSing I»nli

V

rnA
rnA
rnA

Case:
Pins:

~Y connecting the input directly to unhuffered inputs.
For SMIJ units this connection hypasses the sign magnitude circuitry and results in a
unipolar BCD unit.
2) F S R is Full"S'calc Range; IOV for unipolar. 20V for bipolar converters.
J) Gain and Offset Error may he externally adjusted to zero.
4) Linearity is factory adjusted for 4 digit or 14 hit operation and is user adjustahle to
typically 0.002%·.

t) The internal buffer may he bypassed

5-79

Diallyl Phthalate shell
Pin material and plating composition
conform to Method 2003 (solderability) of
MiI·Std·883 I except paragraph 3.2 ) .
Weight: 4 oz (114 grams)
Ac~ual pin assignments not shown on this
diagram.
Mating Connectors: 2400MC - P.e. Card with
solder terminals or 24» I Me . Set of 4 - ·18 pin
connector strips

Method of Conversion
DELTA-SIGMA MODULATION
The Burr-Brown Model AD(' 100 AID Converter utilizes the
delta-sigma conversion-technique which produces a train of
pulses whose rate is proportional to the amplitude 'of the
input analog signal. For a given internal clock frequency
(400 kHz) the delta-sigma modulator output isa train of
pulses whose average frequency varies from zero to 400 kHz.

The width of these pulses 'are constant, but the number of
pulses varies in relation to input signalam~lliud~.. These •
pulses' are coimteej :in ;a' binary:( or BCOrcounler o\l~r: the.
integration ..interval resulting in a direct digital outp'ut that
is' ~quiyalellt to the analog inpu t. The ADC I 00 'timing
diagram is shown, in Figure ·1.-

I

I
I

~~_____:__________~____________~JC~r~________~________________~____~_
CONVERT
I
I

I

END OF
CONVERT

-'~__~~~:__________________~r~r________~
I
SJ
I

~~

~~?~;~~ATOR

OUTPUT
PARALLEL
DIGITAL
OUTPUT
(LSB)

.,

I

CURRENT

______

LJ
'n

~.

~

LJ
n

,

_________________-'. _________

~

~

I

,

____

~~~r

n ____________________________

~

...,

~

I

I

I
I

I

____~I

~______~£~r__~rl--------'---------------'-.1
I--IllGITALOUTPUTCHANGING------~jjf-r--....+I....--IlIGITALIlATASTABLE , : , ' "

DISCUSSION OF SPECIFICATIONS
ANALOG INPUT SETTLING TIME is the time required
after a F.S.R. input step for the ,converter's input circuitry
to settle to specified accuracy. The CONVERT COMMAND
should be delayed, by this period of time after any large
input voltage change to preserve the converter~s accuracy.
ACCURACY - The basic accuracy ~f the ADC' 100 is defined by linearity and quantizing errors .. When gain and
offset err()rs are adjusted -as shown in Figures 3 and 4 and
Table I, the accuracy of the ADCIOOis 0.005% tl count.
LINEARITY ERROR is a measure of the deviation of the
converter's actual transfer characteristic from the ideal. It
is definec! as the maximum deviation of the actual converter transfer function from the best fit straight line
through it. If the linearity error is also adjusted, the acCjlJacy will typically be 0.002% tl count.
QUANTIZING ERROR is inherent in any AID converter,
simply because a converter's analog input is continuous
digital output must be discrete codes. The ADC
while
100 is designed such .that increaSed resolution may be
obtained by interpolation of several successive conversions
of the same input voltage. For example, if the output
codl', is zero for three conversions and one LSB for one,
conversion, the actual input voltage is one quarter of an
LSB.

its

ACCURACY DRIFT is the 'maximum change with temper, atureof any

~oint

on the converter's transfer characteristic.

OFFSET ERROR is the deviation from the ideal input
required to produce an output of all logical ,zeroes (all
bits OFF). GAIN ERROR is the deviation from the ideal
input required to produce an output of all logical ones
(all bits ON) with the offset error adjusted to zero.

SERIAL OUTPUT'
The serial output of the ADC I 00 may be used to transmit
data remotely over a single line. Details for implemen'ting
this method of data transmission are discussed In"Appiica:

tions."

DIGITAL OUTPUT CODES
. For unipolar analog input signals, 4-digit BCD or '16-bit
straight binary (USB) digitaL output codes are offered; for
bipolar analog input signal;; 4-digit plus sign BCD (SMD)
or I 6.. bit offset binary (BOB) digital Qutput codes are
offered. The LSB & full scale analog values and equivalent
digital codes are shown 'in Table I.

S~O

'.

ORDERING INFORMATION
The ADt' 100 may

b~

ofliered hy using the ordering code below.

.!1fK:

A Of I 00 -

converter
Family

OUTPUT CODE
BCD - Binary Coded Decimal
SMD . Sign Magnitude BCD
USB - Unipolar Straight Binary
BOB - Bipolar Offset Binary

INSTALLATION and OPERATING INSTRUCTIONS
EXTERNAL CLOCK

CLOCK OPERATION

An external clock may be used by leaving CLOCK OUT,
pin 26, open and connecting the external clock to CLOCK
IN, pin 28. The duty cycle of the external clock should
be 80% to 90% as shown in Figure 3.

The ADClOO may be operated from the internal clock,
or from a user supplied external clock.
A clock period faster than 2.5 /lseconds or slower than
25/lseconds will degrade the performance onlle ADC I 00.
50 Hz or 60 Hz rejection may be achieved by adjusting the
clock frequency such that the CONVERT COMPLETE
pulse is an integral nUmber of 50 or 60 Hz periods (i.e.,
a multiple of 16.67 msfor 60 Hz rejection or 20.00 ms
for 50 Hz' rej~ction). For example, SMD or BCD units
convert in 30 millisec with a clock period of 3 /lsec.
The closest multiple for 60 Hz rejection is 3333 ms
integration time.

INTERNAL CLOCK
.If the internal clock is used, CLOCK OUT. pin 26, and
CLOCK IN, pin 28, must be connected together.
The approximate period of the internal clock is 3/lseconds.
The internal clOck frequency may be adjusted using the
circuit shown in Figure 5 over a range of approximately
2.5 /lsec to 25 /lsec. If the clock frequency is not adjusted,
pin 21 should simply be left open.

'CONNECTION DIAGRAMS·

Dig.
Cum

NOTE I. See Figure 3. for detaUs of clock.

NOTE I. See figure 3 for details of clock. ·To pins 60. 69 and 70

FIGURE 2a. BCD and SMD Models.

fIGURE 2b. USB and BOB Models.

5-81

,ANALOG COMMON, pins 3 and 23, are connected
'together internally as are DIGITAL C~MMOJ)lt, piri~$b;";
40 and 41. Digital and Analog C~mmon arenot~<'lIi
nected internally; but they should be tied together' at
some point in the system a$ close as possible to the
ADC I 00 to prevent any difference voltage betweeri them, '
All units have available a spare inverter (SN7404) whose,
input is pin 22 and output is pin 24. '
USB andjJOB ,units aremar~ed as shown in f'igure 3;the
BOB ul)lts '!l!!!xwiU have a connection for BiPOLAR
OFFSET, pin 19. The BOB units must have pin 19 ex~
ternaUy connected by the user to SUMMING JUNCTION,
pin 20.
For USB ..and BOB units, either 16-BIT TERM[NATE,
pin 69, 14-B[T TERMINATE,' pin 70, or 12-B'T
TERMINATE, pin 60, must be connected to TERM-

INATE lN, pin 42. The LSB will.always be O.n pin 44,
f6r'16,bitsis'on pin 72, for f4.bits is on pin 67,
.for 12 bits is on 'pin 63.
th~M~B

BCD a~d SMD units are marked as shown in Figure 4,
the SMD units only' will have connections for ADJ, pin I
and pin 5, and SIGN OUT! pin 9.
For BCD and SMD units, TERMINATE OUT, pin 69,
should be conriected to TERMINATE IN, pin 42, for
4-digit operation (see "Applications" for increased resol"
,
ution).
NOTE:For SMD units, the output sign bit operates continuously. That is, the sign bit output wjll change' with
the input voltage' polarity even though the end of con'
version output is "high". Therefore an output flip flop
(such as the 7474 IC shown on next page) may be used to
store the sign bit at the end of conversion. (The PC
mount option includes this flip-flop).

CONNECTIONS FOR INPUT SIGNAL, EXTERNAL GAIN and OFFSET TRIM
GAIN
10Mn

TRIM

..,VI"",.C IOPc!'.{).
I M'{)'

CLOCK

Lrlf1f"
-+l 1"s!.-ll
~
3.usec

100

to

200 "sec

FIGURE 3.GAIN and OFF,SET Adjustments

for all Converters.

The connectiqns shown 'in Figure 3 illustrate various input and.
trim connection options; it is not nece~a'ry' to iqclu,de switches
or jump~rs as indicated unless that level of flexibility is desired.
If linearity is .~ot externally adjusted, the transfer.' characteristic
of the ADC100 can be adjusted for minimum errors USing'. only
the GAIN and OFFSET adjustn:tents, TabJe I sh·ows the input
v.oltage and respective output cod~s for the~ adjus(meQts.

BCD and USB MODELS

of

Adjust to t.I;le proper output code with an .in-put
+2.5000 valts
using the OFFSET aqju'stment; then adjust to .the. p.roper output
code with +7.5000 volts input .using the GAIN, ·adjustment (see
Figure 3 for circuitry and Table I for·input/output-:values:). Repeat
until both·' ate opti~UIl1.

SMDMODELS
Adjust,tothe proper output codes as described above for·SCD and
USB models at 2.500 and +7.500 voUs; then use the negative OFFSET adjustment (as shown in Figure 4) to provide the proper·output
code with -10 mV input and the negative GAIN adjustment (also
in Figure 4) to provide the proper o~tpurcode w!th ~9.99,OO vQlts
input (see Table I).

SMD.SIGN BIT STORAGE

FIGURE 4. Additional NEGATIVE GAIN and OFFSET
Adjustments required for SMD Converters.
,
BOB MODELS,
Using"the OFFSET adjustment! adju!!!t to the output code of 0100
. ... 00 with an"input of -5.0000 volts; then· find' the input voltage,

(near +5.00 volts), that causes an output code of 1-100 . .,. 000. Set
the input voltage to
point halfway between e. and 5.0000 volts.
Use the GAIN adjustment to p~ovide an output of. 1100 ..• 000.
Repeat the OFFSET adjustment at ~5.0000 volts and check to see
that an input of +5.00000 volts produces <:tn .Qutput cede of 1100
..• 00.0. (See Table I). Repeat until both are optinlum.

a

WiRING PRECAUTIONS
All con,nections between the ADC i 00 and ext.ernal components
should be as short ·as possible to minimize coupling effects and
noise pickup. The +5V logic :supply must be bypa~"d with a 100
to 200 pF tantalum capacitor to digital common to preserve ADC 100
linearity, particularly near mid~scale. Experimenting by se:~ting full
scale and zero. exactly correct and checking at· or near' mid~scale
while varying the PQwer supply. decoupling will demonstrate. the
qua~ity of the bypassing. This should be done' first withqut any of
the clock and/or linearity adjust circuitry. and then with the circuftry if it is to be used.

To Pin 9

+-----<

(Sign Out)

UNUSED ADJUSTMENTS
To Pin 39 End of Cpnv.

AlI'unused adjustments should bo left'open except OFFSET adjust
which should be grounded. , "
.

TABLE I. GAIN and OFFSET Adjustments without LINEARITY TRIM.
1/4 Scale OFFSET Adjusl

One
CODE

USB

.SMD

LSB
(mV)
1.00

+2.5000

12 hits
14 hits
16 hits

2.44
0.61
0.15

+2.5000
+2.5000
+2.5000

Positive
Negative

1.00

+2.5000
-0.0100

12 hits
14 hits

3/4 Scale GAIN Adjust

Input
Voltage

OI1TI'UT COilE

Voltage

BCD
4 digit

4.KK
1.22
16 hits
0.31
NOTE: Negative full scale is O.OOOV for

BOB

Input

MSB
LSB
0010010100000000
010000000000
01000000000000
0100000000000000
10010010100000000
0000

o 0000 0000 000 I

+7.5000
+7.5000
+7.5000
+7.50000
+7.5000
-9.9900

OUTPUT CODE
MSB
LSB
0111010100000000
I I 0000000000
I 1000000000000
I 100000000000000
10111010100000000
01001 1001 10010000

I I 0000000000
.+5.0000
-5.0000
010000000000
I 1000000000000
+5.0000
-5.0000
01000000000000
I 100000000000000
+5.00000
-5.00000
o I 00000000000000
unipolar a~d -I O.OOOV for hipolar models. Positive full scale is + I O.OOOV - t l.SD.

'CLOCK and LINEARITY ADJUSTMENTS

-

U
CII

C

CLOCK ADJUST
It may be necessary to adjust the clock frequency if optimum
noise rejection to 50 or 60 Hz power line frequency is
'desired, or else a specific conversion period is desired.
Otherwise, an external clock adjustment is not required.
The CLOCK ADJUST trim circuitry shown in Figure 5
may affect linearity, particularly where there is already
.a bypassing problem with the 5 volt logic supply. If clock
trim is employed, it may also be necessary to perform the
linearity' adjustment described below. The external wiring
at pin 21 should be as short as possible to minimize this
problem.
NOTE I. Use tantalum capacitor.

NOTE: The 400 kHz clock frequency will vary up to
J'If per degree Centigrade. This will have a very small
affect on the accuracy of the ADC J00, but it can cause
problems in some systems applications since the total
conversion time will vary inversely with this frequency.

FIGURE 5. CLOCK ADJUST Circuit.

LINEARITY ADJUSTMENT
Linearity errors can typically be adjusted to less than 0.002%
with the ·circuitry shown in Figure 6. This adjustment can
be done only when th~ internal clock is used .
.If the LINEARITY adjust circuitry is used, the OFFSET
adjustment should be made near negative full scale, the
GAIN adjustment should be made near positive full scale,
and linearity adjusted ne.ar mid-scale .. See Table II for the
proper input voltages and output codes.
NOTES:
I. This wire should be as short as possible
2. This connection required only when external clock is used.

With GAIN and OFFSET adjusted per above, the linearity
error should be adjusted to zero near mid-scale. Supply the
ADC 100 input with the mid-scale voltage shown in Table II
and adjust the linearity potentiometer to obtain the output
code also specified in Table II.

FIGURE 6. LINEARITY Adjustment Circuit.

5-83

TABLE II. GAIN and OFFSET Adjustments with UNEARITYTrim.

..

OFFSET Adjustment
CODE

Input
, Voltage,

Output Code

BCD

Mid·S~.le

GAIN Adjustment
Input
Voltage

MSB

Output Code
MSB

LSB

LINEARITY Adjust

Input
Voltage

"
Output ~ode

MSB

LSB

LSB

+0.0100

0000 0000 0001 0000

+9.9900

1001 100,1 1001 0000

+5.01(j

0101000000010000

16 bits

+0.00976
+0.00976
+0.0097,6

000000000 I 00
000000000 HlOOO
000000000 I 000000

+9.9378
+9.9896
+9,99'01

111111111011
11111111101111
1111111110111111

+'5.00488
+5.00488
+5.00488

1000000000 I 0
1000000000 I 000
1000000000100000

SMD
Positve
Negative

+0.0100
-0.01,00

I 0000 0000 000 I 0000

+9,9900
-9.9900

1 1001 1001 1'001,0000
1001 10010000

+5,010

1010100000001 0000

4 digit

USB
12 hits
14 hits

BOB
12 bits
14 hits
16 bits

o 0000 0000 0001

0000

0000000000 I 0
0000000000 I 000'
0000000000 I 0000

~9,99024

-9.99024
-9.99024

-

o 1001

+9,9854
+9,9890

1000000000 I 0
1000000000 I 000
1000000000 I 00000

+0.00976
, +0.00976
<0.00976

111111111101
11111111110111
1111111111011111

+9.9898

--

-

,APPLICATIONS
VOLTAGE TO FREQUENCY CONVERTER
The CURRENT output. pin 32, and the C'i:OC'i< output. pin 34. may be used
to provide a continuous serial output pulse train whose average repetition rate
is proportionalte the ,analog input Voltage. This circuitry is shown in solid
lroes in Figure 8. The END OF CONVERSION output. pin 39, can be gated
with the serial.output using the additional circuitry shown with dotted lines, The
gated output pulse train is available only during conversion and the number of
pulses in' that period, is proportional to the input voltage, as shown in Figure 7.'

w.,

CURRENT

"

,

32

39

ENIlOF
CONVERT

.LJ"
,
,

I

r1-'

~
...

I

1.._'"

b--

I' ,

I

I

r---,-J

,
I

: 1/47400

L-r-,
SERIAL

.,.._ _ _~nL

01'TPI',.

St.·rial
()Ulput Rate

- l' ~

I

______....nL____

~'~i.!' __ ~her~ ('
\' full :'Iol'all!'

0-.

- - - -I-,'Gated
Serial
Output

- -

l·hu.;k l're4uenl.·~
"'" ··wn kH ....

FIGURE 8. Voltage to Frequency Converter.

FI(jllRE 7, Typical OUlput Waveforms,

5 DIGIT ADC100
The resolutioil of BCD and SMD models may be expanded
to 4·1/2 or5 digits with'a minimum of external circuitry.
Expansion H)4.1/2 digits will double the conversion time to
about60 milliseconds WhileS digit conversion will require
300 milliseconds. Figure '9 shows the application of two
SN 7490 decade counters tv provide an eXIra digit output.

term in 42

term out

6~

Linearity
Correction
Network

If the ADC(OO is use'd' till five digit operation, it is recommended< th,ai !'J\e,)i;;earityadjust'ment circuitry shown in
Figure 6 be, ,u~d' to provide accuracy consistent with the
resolution. With five digit operation, the positive full scale
input voltage 'is ':tlf99990 volts while the negative full scale
input is, 0.00060 volts (BCD) or -9.99990 (SMD). A good
mid-scale input' voltage to use for the linearity adjustment
is 5.00500 volts (output code 0101 00000000 01010000).
The ADC 100 maybe used as the heat of a 5 digit DPM with
accuracy much better than that of any moderately priced
digital panel meters at a lower cost.
The components ,required in addition 'to tlie AD('J 00 are:
(I) Two decade counters (such as Tl's SN7490)

36
35

MSB 72

FIGURE 9. Extending ADC lOa to 5 Digits.
(2)
(3)

5-84

Five BCD to seven segment de,coders (such at Tl's
SN7447A)
A display (such as RCA's DR2100 Numitron series)

(.l)

Pow~r

Supplies. ±15 volts and +5 volts (such as Burr·
Brown's Model 551 and Model 5(2).

1 ppm/or offset drift while contributing only 0.00:!'i!
linearity errors.

ADC100 PREAMPLIFIER
-tN

An instrumentaiion amplifier may be used as the input to
the AD('j 00. An input instrumentation amplifier such as
Burr·Brown's 3625 will provide differential inputs with
common mode rejection as well as gain. The circuitry shown
below will provide a gain of 10 (Le .. I volt instead of 10
volt input range) and 74 dB rMR.
The orrset aujustm~nt or the AIK 100 has enough range to
compensate rll' Ihe small output offset of the 3h2~ ami liS'
g:lin adjustment can compensate for Ihe gain errors of the
3625
The

.~625B

will add no more.than 10 ppm/oe gain drift and

Adjustml!nt Circuitry

.... 1(jURI: 10. Differential Input ADC IOU.

5-85

BURR-BROWN®

l'ElElI

High-Speed
ANALOG-TO-DIGITAL CONVERTER
FEATURES
• 12·BIT RESOLUTION
• ±0.012% UNEARITY AND DIFFERENTIAL UNEARITY
ERROR MAXIMUM IC GRADE)
• NO MISSING CODES -25°C TO +85°C
• 32·PIN METAL PACKAGE
• CONVERSION TIME: 5OOnI8c. 8 bits
67Onsec. 10 bits
·1.5,Aec. 12 bits

DESCRIPTION
The ADC803 is a high speed successive approximation analog-to-cligital converter utilizing state-ofthe-art IC and laser-trimmed thin film components.

It is complete with internal reference, clock, and
comparator and is packaged in a 32-pin metal
package. Conversion time is set at the factory to
1.5l'sec.
With user-adjusted conversion time set at ll'sec,
±ILSB accuracy can be achieved. The gain and
offset errors may be externally-trimmed to zero.
I nternal scaling resistors are provided for the selection of analog signal input ranges ofOV to -IOV, ±5V.
and ±IOV.
Output data is available in a serial or parallel format.
Output codes available are complementary binary
for unipolar inputs and bipolar offset binary for
bipolar inputs.
All digita1 inputs and outputs are TTL-compatible.
Power supply requirements are ±15V and +5V.

PARAllEL
DIGITAL
OUTPUT

COlVERT COM MAID

~'I'r---O)

IIPUT
RARE SElECT
COMPARATOR II

CLOCK RATE COITROI.
CLOCK OUT
STATUS
SERIAL OUT

Inllrlllll....1Alrplll1lndualrlal Park· p.o. BDX 11400· Tucaon. Ariz.... 85734· Til. 1602) 746-1111 • Twx: 910-952·1111 • Cabl.: BBRCORP· Talex: 66-6491

5-86

SPECIFICATIONS
ELECTRICAL
At +250 C rated power supplies 1 Slolsec conversion time and after 6·minute warm·up unless otherwise noted
ADC803CM

MODEL
MIN

I

ADC8038M

I

TVP

MAX

RESOLUTION

I

MIN

TYP

'2

I
I

MAX

UNITS

'2

Blta

INPUTS
ANALOG
Voltage Ranges
Bipolar
Unipolar

Impedance
-'OV to OV, ±SV
±'OV
DIGITAL
Convert Command
Loglc'Loading

±S,±'O
Oto-'O

V
V

'.4
2.4

kO
kO

Negative pulse 50nsec wide Imin} trailing edge (0 to 1) initiates conversion

I

I

4

I

II'

TIL Loads

TRANSFER CHARACTERISTICS
ACCURACY
Gain Erronl)
Offset Errorll)
Unipolar
Bipolar

Linearity Error
1.5p.sec Conversion Time
1.0,...sec Conversion Time
Differential Linearity Error
1.S,.,.sec Conversion Time
1.0J,lS8C Conversion Time
Inherent Quantizatio,:, Error
POWER SUPPLY SENSITIVITY
Gain and Olfset
+'SVDC
-, VDC
+5VDC

Conversion Time
+'SVDC
-'5VDC
+5VDC
CONVERSION TIME!
Factory Set
Range of Adjustmentl31

±O.'

±O.oa

±O.2

%

±O.OS
±O.02

±0.2
±O.,

±O.07

±O.3
±O.2

%01 FSRI21
%ofFSR

±O.OO9
±O.O'S

±O.0'2
±0.020

±O.O2O
±O.020

%oIFSR
%oIFSR

±0.0'2

±O.O'S
±0.024

±0.020
±0.024

112

%oIFSR
%oIFSR
LSB

±O.OO36
±O.OOOS
±O.OO'

% of FSR/%Vcc
% of FSR/%Vcc
% 01 FSR/% VDD

±O.7

%/%Vcc
%/%Vee
%/%VDD

None
±o.a
'.3
0.8

DRIFT
Gain
Offset
Unipolar
. Bipolar
Linearity Error, ·25°C to +85°C

1.5p.sec Conversion Time
1.01o'8ec Conversion Time
Dillerential Linearity Error, -2S'C to +8S'C
1.5",58C COnversion Time
1.0psec Conversion Time
Conversion Time
No Missing Code Temp. Range
1.5~sec Conversion Time

±O.04

'.5
2.2

"sec

Poec

±'O

±30

±'5

ppm of FSR/' C

±2

±7
±'O

±3
±S

ppm of FSR/' C
ppm of FSR/' C

±3
±O.0'2
±O.O'S

±o.o,a

±0.0'2
±O.O'S
±O.'

±o.o,a

±0.024

%ofFSR
%ofFSR

±O.024

%ofFSR
%ofFSR

±O.O20

±O.024

%I'C

-2S

+85

'C

OUTPUT

I

DIGITAL DATA

Parallel
Output Codes
Unipolar
Bipolar
Output Drive
Serial Data Codes (NRZI
Output Drive
Status
Status Output Drive
Internal Clock
Clock Output Drive
. Frequency (without
external clock adjustment)

I

I

Complementary Straight Binary
Bipolar Ollset Bi,!ary

6

TTL Loads
Same as Parallel (MSB first)

6

TIL Loads

Logic "1" during Conversion

6

.

3
a

TIL Loads
TIL Loads
MHz

5-87

ELECTRICAL (CONT)

-"".,'

~.

I

MODEL

t

~
~

ADC803CM

I

MIN

TVI'

MAX

±15.0
+5.0
+27

±15.75
+5.25
+32
-55
+210

ADC8038M

-.l

MIN

TVI'

-.l

MAX

POWER SU"PLY' REQUIREMENTS
Power Consumption.
Rated voltage, Analog I±Vccl
DigitallVool
Supply Drain, +15V
-.15V·
+5V

±14.25
+4.75

-38
+180

J
-.l

UNI'tS

.

.'

VDC
'VOC'
mA
mA
'r,;A

.

TEMPERATURI,! RANGE (AMBIENT)
-25
-55

Specification
Storage

.

+85
+125

NOTES:
1. Adjustable to zero. See Optional Gain and Offset Adjustment section.
2. FSR means Full' Scale Range. For example, unit connected for ±10V has 20V FSR.
3. See Optional Clock Rate Control section. For faster conversion time at less resolution, see section on External Shor:t pycle.

!

CONNECTION DIAGRAM

ABSOLUTE MAXIMUM
RATINGS

(MSBI BIT I. I . . , . - - - - ,

ANALOG COMMON

Analog Supply
Voltage To
Analog Common ••• ±18V

31

ANALOG COMMON
BIT6 B
+5VDC (Vool SUPPLY
DIGITAL COMMOII
SERIAL OUT

Digital Controls
Inputs ••••••••••• +5.5V
Analog Inputs ••••• ±15V
Operating
TemperatI,Jre
Am bient ••••••• +85° C
Case ••••••••• +125°C
Storage
Temperature •••• +125°C

SENSE
COMPARATOR IN
10V

7
B

20V
·15VDC SUPPLY (-Veel
+5VDC SUPPLY (VDoI
21 DIGITAL COMMDII
+15VDC SUPPLY (+Vcel

BIT 10

18

t==:~~~~~=::::=j17

,

MECHANICAL
A

I

L=:t

~

C(

J--H
0000000000000000

16

1

~1e!lllllllillll

1

0-001.-

!

LL

1

j

CLOCK RATE CONTROL
CONVERT COMMAND
CLDCKOUT

PINS: Pin material and plating composition
conform to method 2003 (80ldarablllty) of
MIL-8TD-883 (except paragraph 3,2)
CASE: Kovar, Nickel plated
HERMETICITV: Groee Leek Teet
MATING CONNECTOR: 2302MC Set
two 16-pin strips
WEIGHT: 13 grams (0,46 oz.) ,

0'

0000000000000000
'C32
17

" - - - Denotes pin 1

G-J

+15VDC SUPPLY l+Veel
·15VDC SUPPLY (·VceI .
BIPOLAR OFFSET

Digital Supply
Voltage To
Digital Common •••• +7V

U

·C
·C

-

..
'Speclflcation same as for ADC803CM

Pin numbers shown for reference·only.
Numbers may nol be marked on package,

0'

Pin 1 can be Identified from bottom
unit
by either a contraatl'ng color of glass seal
or a square corner.
Is tied to Digital
,·Common.
NOTE: Leads in true position within 0.10·
(O.25mm) R at MMC at seating plane. Pin 8
connected to case,

case

5-88

DIM

INCHES
MIN
MAX

MILLIMETERS
MIN
MAX

A

1.720

1.760

43.69

44.70

B

1.120
.170

1.160
.250

28.45
4.32

29.46

c

.016

.02'

6.3.5

G

.100 BASIC

H

.'00

.,..,

0.41
0.53
2.54 BASIC
2.54
3.56

K
L

.300
.150
.900 BASIC

3.81
7:62
22.86 BASIC

R

.'00

0

.140

2.54

3.56

THEORY OF OPERATION
The accuracy of a successive approximationanalog-todigital converter is described by ihe transfer function
shown in Figure I. All· successjve approximation AI D
converters 'have an inherent· Quantization Error of
±1/2LSB. The remaining errors in the AI D converter
are combinations of analog errors due to the linear
circuitry matching and tracking. properties of the ladder
and scaling networks, power supply rejection, reference
errors and the dynamic errors of the DAC and comparator. In summary, these errors consist of initial errors
including Gain, Offset, Linearity, Differential Linearity,
and Power Supply Sensitivity; I.nitial Gain and Offset
errors may be adjusted to zero. Gain drift over temperature rotates the transfer function (Figure I) about the
zero point and Offset drift shifts the transfer function
left or right over the operating temperature range.
Linearity error is unadjustable and is the most meaningful
indicator of AID converter accuracy. Linearity error is
the deviation of an actual bit transition from the ideal
transition value at any level over the range of the AI D
converter. A Differential Linearity error of ±1/2LSB
means that the width of each bit step over the range of
the AID converter is ILSB, ±1/2LSB. The ADC803 is
guaranteed to have no missing codes over the specified
temperature range.
.

81T10_

8ITI'~
8lT'2~

S:'r~DATAIIIVAlJDmttili@i{W4JraiM:.UiMi~

.

000 ... 000

50

40
125

lew

17

25

lao

10

to

10

...

10
10

38
38
38
38.

I

OFFSET

ERn.

I

f .f!

I
I

~

FIGURE 2. ADC803 Timing Diagram.

~~ finONI
.FSR"

-

Nominal
"'Without extarnal adjustment

f--......;i-+'+--~h-I--I

'2

Ic:o

100

100"'010~
100 ... 001
011 ... 110
000 ... 001

Max·
(nsec)

15
tc.••. . 100

111 ... 110

011 ... 111

Min·
(nsec)

leo

III ... III

100 ... 000

Time
Period

AULOS llPUT
EIIOFF

.FSR

T

·ILSS

·IIfE TABLE I FOR DISITAl CODE DEFINlnO.1.

FIGURE I. Input versus Output for an Ideal Bipolar
AI D Converter.
TIMING CONSIDERATIONS
The timing diagram (Figure 2) shows the relationship
between the convert command, clock and outputs. The
digital output word is positive true logic for bipolar
operation and complementary logic for unipolar operation.
The following are some important notes on the ADC803
timing. The times given are typical unless otherwise
noted. Nominal maximum and minimum times are also
given in Figure 2.
I. When power is first applied, the status ofthe ADC803
will be undetermined. A CONVERT COMMAND
must be applied to initialize the ADC803.

2. The CONVERT COMMAND must be low at least
SOnsec prior to the ·~O" to "1" edge that starts a
conversion.
3. The clock runs continuously when the initial CONVERT COMMAND goes high and whenever the
CONVERT COMMAND is high thereafter. It does
not run when CONVERT COMMAND is low. It
may be beneficial to keep CONVERT COMMAND
low except during conversions to 'limit the digital
noise induced in the ground and power supply lines.
4. ,The clock starts 2Snsec after the "0" to "I" transition
of the CONVERT COMMAND.
S. Parallel Output Data: The Successive Approximation
Register (SAR) is reset 26nsec after the leading edge
of the first clock period in the conversion cycle. The
MSB is set to logic "0" .and all other bits are set to
logic "I". The bits ate determined in succession
starting with the MSB, Bit I, as shown in Figure 2.
Each bit ~ill be valid 26nsec after its corresponding
clock pulse.
The falling edge ohM STATUS signal should not be
used to strobe parallel data out of the ADCS03

5-89

;' '''directly; The table in Figure 2 indicates that the fal-'
;. ling edge of STATUS may occur prior to bit 12 data'
: becoming valid.
. ..
6) Serial Output Uata: The serial output isindeterl minate until Bit lis valid; which occurs 26nsecafter
: the leading edge of the second 'clock pulse. The
. remaining bits (Bits 2 through 12) are valid in:successiQni6r one clock period each beginning 26nsec after
the leading edge of .each .clock pulse. \
STATUS goes high 26nsecaftet the leading edge of
- the first clock' .pulse and goes low I!!nsec after the
leadi~ edg~ of the last clock pulse.
S. Bit 12 will' become valid at about the same time
STATUS goes low and a new conversion can be
, initia,tedat anytime after the output data has been
read~'
'.
. .

7:

'c~~ Tbe·c,onv·~rter may be restarted duri~g a"c·onversion.
..

When CONVERT COMMAND makes a "0" to "I"
transition after the minimum set-up time, the 'SAR
will bc.:'reset and a neW conversion will start regardless
. of the state of the converter prior to the CONVERT
COMMAND being received.
Figures 3, 4, and 5 are photographs 'of the actual pulse
shapes and relationships.

FIGURE 5. Photo of (a) .Bit-12 Pata (Parallel).
(b) Clock, and (c) Status (20nsec/div).
DIGITAL CODES
Parallel .Data

Two binary codes are available on the ADCS03 parallel
output; they are complementary straight binary (Logic
"0" true) for unipolar input signal ranges and bipolar
offset binary (Logic "I" true) for bipolar input signal
ranges. Binary two's complement may be obtained for
bipolar input ranges by inverting the MSB. It should be
noted that for unipolar input ranges -10 volts is full scale.
Table I ~hows the LSB, transition values, and code
definitions for each possible' analog signal range.
TABLE I. Input Voltages. Transition Values, LSB
Values and-Code Definitions
Analog Input
Voltage Range
Code
Designa~ion

:tl0V

:t5V

Oto-IOV

BOBI'}
orBl'C}2}

BOB
orBTC

CSBI3}

4.88mV

2.44mV

2.44mV

-10V + 112LSB

--5V +'112LSB

-JOY + 312LSB

One Least
Significant

Bit,lSa.,

FIGURE 3. Photo of (a) Convert Command. (b) Clock.
and (c) Status (200nsecl djv)~

TransitioliValues

MSB LSal4}

::::~::>
~~:::~~
~~~:::~~~:>

.fIV +112LSa

-l12LSa

-lI2LSB

+lOV - 312LSa

+5V-3I2LSa

..

,

-1I2LSa

.'

NOTES/I. BOB = Bipolar'Oftset Binary.
2: BTC = Binary Two's Complement IObtained by inverting the
~ost signif.fcant bit Lpin 11.
3. CSB .=. Complementary Stralght Binary.
4. Voltages given are the nominal value forthe transition from the
next lower code.
;

Serial Data (NRZ)

FIGURE 4. Photo of (a) Convert Command; (b) Serial
.:
Out; arid (c) Glock (50nsecj div).

Two binary codes are available on the serial output lilie;
they are'complementary straight binary (CSB) for unipolar input ranges and bipolar offset binary (BOB) for
bipolar input signal ranges. The serial data is available

5-90

only during conversion and appears with the MSB first.
See the timing diagram and discussion under "timing
considerations" for more detailed information.

€)

The LSB and transition values shown in Table I. also
apply to the seri'al data output, except serial output does
not have a BTC code.

DISCUSSION OF
SPECIFICATIONS
The ADC803 is specified to meet critical performance
criteria for a wide variety of applications. The most
critical specifications for an AI D converter are Linearity,
Drift, Gain and Offset errors, and Conversion speed
effects on accuracy. This ADC is factory-trimmed and
tested for all.critical key specifications.

@

@)

@)

@)

@).

0

@)

CD

€)

+15VOC

I

11~F

.A:oa COMMON

II~F

--

-15VOC
+5VOC

11~F

I·

.O:TAl COIliMON

FIGURE 7. Recommended Power Supply Decoupling.

GAIN AND OFFSET ERROR

Initial Gain and Offset errors are factory-trimmed to
typically ±O.05% of FSR at 25"C. These errors may be
trimmed to zero by connecting external trim potentiometers as shown in Figures.lO, II, and 12.

LINEARITY ERROR

Linearity error is not adjustable by the user and is the
most meaningful indicator of AI D converter accuracy.
Linearity is the deviation of an actual bit transition from
the ideal transition value at any level over the range of the
AI D converter.

ACCURACY VERSUS CONVERSION TIME

In successive approximation AI D converters, the con. version time affects Linearity and Differential Linearity
errors. Conyersion time and its effect on Linearity and
Differential Linearity errors for the ADCS03 are shown
in-Figure 6.

DIFFERENTIAL LINEARITY ERROR

Differential Linearity describes the step size between
transition values. A Differential Linearity error of
±I I 2LSB indicates that the size of any step may not vary
from ILSB by more than ±1/2LSB.

~

~,
a:

&? ±2,O

LAYOUT AND OPERATING
INSTRUCTIONS

a:
w

~

+85'C

~±1.S
w

Z

LAYOUT PRECAUTIONS

-'

The ADC803 is a high speed analog-to-digital converter
which requires more layout precautions than general
purpose products.

::;

~±1.0
zw

a:
~

-2S'C

i5±O.s
~

~z

:;

0

The ADC803 has two pins for analog cOlp.m~n, two pins
for digital common, and two pins for each power supply
input. Each pair ofthese pins must be connected together
eX,ternally. The connection between the digital supply
pins and the connection between the digital common pins
must be as short as possible. The analog and digital
commons are not connected together internally in the
ADC803, but should be connected together externally to
a ground plane.

L-_-+--:+--t--i---+--0

0.8

1.0

1.2

1,4

1,6

CONVERSION TIME (p8ec)

FIGURE 6. Linearity and Differential Linearity Error
versus Conversion Time.

Connecting all commons to a ground plane at the
ADCS03 is the best 'method to minimize noise and
dissipate heat. Pin 8 (Digital Common) is internally
connected ,to the case.

POWER SUPPLY SENSITIVITY

Changes in the' DC power supply voltages will affect
accuracy. Normally, regulated power supplies with I% or
less ripple are recommended for use with this ADC. See
Layout Precautions, Power Supply Decoupling, and
Figure 7_

The ADC803 also has an analog common Sense input
(pin 27) for the analog input. This se-nse pin must be

5-91

connected to analog common lts.dose to -the input signal
.source as possible or connected to the ground plane. Low
impedance analog and digital common retuf'lsare essential for low noise performance. Coupling between analog
inputs and digital lines .should be minimized by careful
layout. Special attention shoqld be taken to .ensure that
the clock noise on the +5V supply liile does not couple
. into the analog inputs. ,
The Comparator input (pin,26) is extremely sensitive to
noise. Any connection to this point should be as short as
possible and shielded by analog common or ±15VDC
supply patterns. The Clock Output (pin 17) is sensitive to
stray capacitance; capacitance, on this pin could alter the
clock wave shape.
.
/'

OUTPUT DRIVE
All ADC803 outputs except the clock witt drive six ITL
loads; the clock will drive three TTL loads. If long digital
lines must be driven. external logic buffers are required
particularly for the clock which is sensitive io capacitive
loading.
INPUT IMPEDANCE
The source impedance to the ADCS03 should below.
such as the output of an op amp. to avoid any errors due
to the relatively low input irnpeqance of the·ADCS03~

If this impedance is not low. a buffer amplifier should be
added between the input.signal and the ADCS03 input as
shown.,in Figure 9.

POWER SUPPLY DECOUPLING

The power supplies should be bypassed with l/lF tantalum
capacitors as shown in Figure S to obtain noise-free
·operation. These capacitors should be located close to the
.
ADC.

ANAL080~IN~PU~T_-..,_LI':_-l
l_---~.thc; ADC dep~cJng
proper analog and digital grounding. 'Several analog and
digitat ground pins have been provided to allow for
optimizing the iritermiIliyotit of the ADC.As will be
explained iri more dbtaillater;aiialog and digital grounds
should be connected together imly at 'one point by an
extremely low resistive and inductive connection' (a
ground plane is ideal). A special analog .ground called
'~sense"has been .provided to eliminate the voltage drpp
that would otherwise be in the ground return of the R-2R
ladder. MeaSuring ,the input signal ,with respect. to the
sense terminal, makes ..:the measurement independent of
the impedance that is. developed in. the connectjQn
between the sense terminal and the analog ground, pin
28.
. ,., ,
-

,ANALOG-To-DIGITAL CONVERTER
TEST TECHNIQUE

A very effective way of determining the DC performanc~
of an ADC is by using the "servo loop meJhod." The
block cl,iagramof this technique is shown ~n Figure 18;
This meaSurement system automatically locates the analog voltage that causes the digital output to alternate.
between the desired code and the adjacent code. The
·computer is programmed to place the desired code on the
I/O bus which is one set of inputs to the digital
comparator. The other set of inputs to Olis comparator is
the digital output of the ADC. Depending upon the
result of this comparison, t1te integrator is directed to
, change its output until an equilibrium state is achieved.
Once in equilibrium, the DVM measures the analog input
to the ADC and transmits the information to the
computer via the IEEE-488 bus. The test program checks
all the desired code combinations, verifying the performance of the A DC. Test time ~iIl range from 10 seconds
to several minutes dependi'pg. on the ,speed of the test
program, settling time ofthe DV¥, and number of codes
to be checked.
GROUND LOOPS

Figure 19 illustrates the interaction that occurs between
the analog and digital grounds when an ADC is c.onnected
into a test circuit. This interaction is created by ground
loops. The circuit in Figure 19 shows how ground loops
.are created when the ,ADC te.s.ter. combines digital and
· analog portions of the circuit together-in this case, the
test signal generator (analog) and the digital circuitry that
detects the ADCcode which corresponds to the analog
signal (digital). The ground loop exists When the digital
ground connection between the ADC and the tester is
in parallel with the analog grounds that cqnnect the tester
with the ADC. When the connection. is made in this
manner some of the digital current is diverted into the
analog signal' return, which creates a code-dependent
,error signal due to the resistance in the analog signal
· return. This error distorts the linearity measurement and
ind\lC,cs hysterisis. The ~rrpr canbes\lpstantilllly redl.lc.ed
if the anaLog and digital grQunds are isolate4 from each
other in theA-DC tester.

2110
ANALOG
INPUT

PIN2S

-

ptNM

lKII

TEST SIGNAL
SOURCE

SENSE

PIN 27

fi;c
PIN 2G

FIGURE 17. Simplified Model of ADC803 Depicting Proper Analog and Digital Ground.

DVM

IEEE... BUS

COMPUTER

110 BUS

DIGITAL
ANAL08. OUTPUT
---II.PUT

DIGITAL
COMPARATOR

>-,..........

FIGURE 18. Servo Loop Analog-to-Digital Tester.

5-95

DIGITAl GROUID CURREIT

•

t--1~--t--..;, /\.'--.....- - -......- - - - - - - - - - - - - - - ,
'v'

D11ITAL
8R8UID
REIISTIIICE
PC CARD

BROuilD

TE8T8Y8TEM

ItIIIUI.

AriALoa
!lRDUn
.. CUIREIT
L-_~_ _ _ _+_---li\\ ,'''\ ~""'_I-_--I
v

AIAlD8
8ROU11D
RElI8TUCE

TEaTSyaTEM

FIGURE 19. Ground Loop Interaction Between Analog and Digital Grounds When ADC Is Connected
Into Test Circuit.
BEAT FREQUENCY TEST

A "beat frequency tesf~ applied to an ADC803 with a
companion sample/hold illustrates both an effective
means of testing the high frequency performance of such
a system and demonstrating that the ADC803 with its
associated sample/hold is capable of digitizing high
frequency signals cleanly. A sample/ hold must be used
when performing this test to hold the input of the
ADC803 constant during the conversion time. Figure 20
is a block diagram of the beat frequency test set up.
The beat frequency test is useful for being able to rapidly
determine whether there are any serious problems with
the ADC. In this test the input frequency is set at slightly
less than one-half the sampling rate. The Slight difference
is selected to allow the sample point to vary by I LSB, or

TEKTRIIIIIX
8111lWAVE
OSCIllATOR
88603

less, on successive samples. The d~ta is clocked into a 19W
frequency reconstruction DAC at one-half the sampling
rate'to enable viewing on an oscilloscope. Figure 21 is a
photograph of the response to a full scale input sine
wave centered around 'the MSB and Figure 22 is a
photograph of the response of a small signal sine wave
centered around the MSB. For comparison, a photograph (Figure 23) is included which shows the response
of the ADC803 to a 125Hz input signal which is the
same as the beat frequency.
Figure 24 is the PC card layout that was used for the, beat
frequency 'test. This layout demonstrates some of the
layout practices that must be followed when using a high
speed ADC like the ADC803.

H·P
PUL8E
BE.ERAtOR

m-ECL

, TIIAIIII.ATOR

KI0124

11138

1=..,

COlVERT COMMAII

f=37..-z
TEKTRONIX
liNE WAVE
O8CILLATOiI

881103

SAMPLEI
HOLD
,BURR·
I.OWI
8HC803

ADC8D3

TTL-ECL
TRANSLATOR
MCIDI24

FIGURE 20. Block Diagram of Beat FrequencyTest Circuit.

·5-96

08CJI.l.0.
SCOPE

>

I
1msec/~iv

1msec/diy

lmsec/div

FIGURE 21. Beat Frequency Test
Response of Full Scale

FIGURE 22. Beat Frequency Test
Response of Small Signal

FIGURE 23. Response of Small Signal
125Hz Sine Wave Input.

r-______;o::S:i:ne::w:a:v:e:I:n:p:u:t:·:::::::::::o::::::::S:in:e:w::a:v:e:l:n:p:ut:·:::::o::::::::::::::::::::::::::o~____- ' .
STAAT CONYERT

.-

i

(Q)··oa~

C

---- -- -C) '(QJ
--- ------ i hi
~~
@ ..•
~

-m:Je>

~~

~
z

..

...

J2

-=
_

~

~

HH!

.- Meg)

.~

+

---=

M

+

u

--G!:J-!

DIGITIZED OUTPUT

STATUS

o

JlI

o

V97-2 REV A

(a) Top View

(b) Bottom View

FIGURE 24. PC Board Layout for Beat Frequency Test Fixture.

5-97

o

o

. ':"., i" ,_<>r"')

,,;:"\:'~:RbMi5:

c

DE~J;~~~ti<

Bit 3

>;<

Bit 4

~

BitS>;C

~.

Bit 6
Bit 7 (7
Bit 8
Bit 9
Bitl0
Bitll

~

...-----------1:'32
r-----------I'~
Reference
~

~

__

~

8

>;<
~

<

1'111

Bi'12~_ _ _ _ _--,Ir;:
'Iff
ILSB for 14 bitsl Bit 14 ~J------lil

III

Bit 16

I:
II

II
l
G§:iI-------.J
~

-t

;

~

~
com~

16-BitSAR

ILSBfor13bits,Bit1313-

Bit lS

CONVERT COMMAND'
+5VDC SUPPLY

r--I-------I.~l GAIN ADJUST

II
-.III
,I'

~If---...J·III

SHORT CYCLE

".,1_

Clock

~ +1SVDCSUPPLY

~

r+-.-=6"-=.3'"'kn::----.....

CqMPARATOR IN

~N~---.f:~ BIPOLAR OFFSET

.--:=----125 10V}
hS'Ikn,-i· Connect the Gain adjust'potentiometeras shown
in Figure' (I. Sweep the input through the end point
transition \'oltage that should cause an o)Jtput transition
to all bits on (E(:~). Adjust the Gain potentiometer until
the actual end p;,int transition voltage occurs at E(~~.

I...

!

Table I details the transition voltage levels required.

20

I

I
1'N'.-. j

.15VDC

GAIN ADJUST

@

AUDIO COMMON ~

510kn

D.OI"F
.

4

10

12

14

15

CONTROL VOLTAGE ON PIN 23

IOknlo lOOk!!
GAIN ADJUST
·15VDC

FIGURE 13. Conversion Time vs Clock Rate Control
Voltage.

FIGURE 11. Connecting Optional Gain Adjust.
1.0

OUTPUT DRIVE
all PCM75 logic outputs will drive two stan·
dard TTL loads: howe\·e·r. if long digital lines must be
driven. external logic huffers arc recommended.

0.4 16-8IT.:".;.;.;;..;..~;;;.-;j;;;;-+-. _

Connect Pin 32 to
Connect Pin 23 to
Conversion Time
I Typi~11 . ,.i.sec

. 15

'J

Open
Pin 19
17

Pin 16
Pin 1q

l<

P,,, 14

Din

Pill 1Q

15

P'r" In
10'

Pr" 30

16

p.,

-~'.",~'

0,01

... .--+--

l :~:!~§~].r-"..--i--1

14-81t
. 0.004 IfI.8lT

C

12

13

~~~--+-~--r---~

15

e

If a more precise adiustment of conversion time is desired
than can be obtal~ed by simply connecting the Clock
Rate (pin 23) to Digital Common or+5V, as indicated in

_} ..3Dd8

0.1 IfI.8IT·-------!"~~__-~~

The PCM75 may be operated with faster conversion
times for resolutions less thllll 14 bits, if a higher TH Dis
acceptable, by connecting the Clock Rate (pin 23)and the
Short Cycle (pin 32) as shown in Table III. Typical
conversion times for the resolution and connections arc
indicated.
TABLE III. Short C\cle and Clock Rate Control
Connections for 12- to 16-Bit Resolutions.
16

-t----1

..- --"----=--ir=- ."-.------l......-/
14-81T

ADDITIONAL OPTIONAL CONNECTIONS

'3

,

14-8IT·i,;;,.~~d~~~C~;E=

~ormally

Resolution ,Bits

.•

II

7

CONVERSlOII TIME 1...111
0118 =:!:5¥OC =FS

FIG U R E14. Total Harmonic Distortion vs Conversion
T;me.

5-105

CONVERT
.COMMANO
PCM75,'

to
EXTERNAl CLOCK WAVEFORM,
APPLIED TO PIN 31.

0.4

....
..•..

.,._,-,-;

r--i-'lI~.--4--;:~~-'-' .• -.--~

l

'FIGURE 16. ContinuousConversion Using an External
Clock.

co

;::'
~

'¥l~

0.1

!2

co

.

..

So!

~+--r--+-...j

co

+5VDC

...
;ll

',\
,

.....==co

220pF

Ikll
"

, . M!ct=:::d

0.01

1~~

fCMT5

+5VDC

__ _

,B"sec- - •.~

15plec'-EXTERNAl.:.,---;;;--7;;;'~
CLOCK -

V,N IdB)

FIGURE 15. Total Harm(lnicDistortion vs Input
Voltage l.evel.

EXTERNAL CLOCK
If an external clock is used. connect it to the Convert
Command. pin 31. The convert command waveform as
shown in Figure 2 is then not used on pin 31. The internal
clock signal will still appear <10 pin 20 and its waveform
can vary from that shown in Figure 2. The external clock
pulse. as applied to pin 31. must he a negative-going pulse
with a width hetween IOOnsec and 200nsec as shown in
Figure 2 and in Figures 16. 17. and 18.

'The external clock lrequency must be lower than the Internal clock
frequency or'the PCM75.

FIG U RE 17, Continuous Cbnversion lising an External
Clock That Has an Arhitrary Duty Cycle.
IC I =1I274lSf23

OR EQUIVALENT

IC2 = 1/474\.832
OR EQUIVALENT

Figure 16 shows continuous conversion using,an external
clock waveform. with the correct duty cycle applied
directly to pin 31. A new conversion will automatically he.
initiated hy the (n + 2) clock pulse where n is ttie
resolution of the PCM75.
Figure 17 shows how to shape the waveform to apply to
pin 31 when using an external clock that has an arhitrary
duty cycle.
Figure 18 showsh,ow to obtain continuous externa,1
clock convers,ion initiated by the'rising edge of an
e~ternal clock pulse only when an ad{Jitional convert
command pulse is high.
In all cases when usingari external clock. the frequency of
the external clock must be lowerthan thefrequency of the
internal clock. The internal clock normally runs at
933kHz when the Clock RateControl. pi~23. is connected
to digital common. Higher internal clock frequencies can
- be obtained by'connecting the Clock Rate Control. pin
23. to positive voltages; +5V is often cOl)venient to use.
See Figure 13 for relative increases.

Note:
The convert command and the external clock must be high slmultaneoully to
Inltlale a conversion. T1Ie conversion wlll.stlrt on the rising edge 01 the
external clock. Any further convert commands that occur during a conversion
will be Ignored until the conversion Is compillflld.
'.

FIGURE 18. Con,tinuous Conversion Initiated hy the
Rising Edge of an External Clock Pulse.
Onl\' When an Additional Co'nvert
Co~mand Signai is High.

5-106

DESCRIPTION OF AID - DIA OPERATION
The PCM75 was designed ~o that the internal D! A
converter can be made available to the user as shown in
Figure 19. The D A converter portion of the PCM75
requires only ±15VDC supplies and analog common for
operation. Therefore. floating the +5VDC supply pin
~pin 30) turns off the internal clock. successive approximation register (SA R). and comparator without affecting
the operation of the DACo Note that the +5VDC line
nust appear as a high impedance to the PCM75 or

damage may result to the SAR digital outputs when they
are used as digital inputs for operation of the Dj A
converter.
This circuit provides a low cost alternative to using a
separate Ai D and DI A converter in applications where
the operation of only one device is required at any given
time. The current settling time of the Dj A portion of the
PCM75 is about IlJsec to within ±0.003% of the final
value. The voltage settling time is dependent upon the
characteristics of the output amplifier (A,).

DAC
ADC
OPEN
CLOSE
OPEN
CLOSE
OPEN
CLOSE
CLOSE
S4
OPEN
OPEN
S5
C LOSE
CLOSE
55
0 PEN
CLOSE
S7
0 PEN
BUFFER CONTROL DI SABLE ENABLE
SWITCH

DAC11IPUT

MSB

''''''"
rn H '"
TRI·STATE BUffER

I
Msa

74LS244 x2

11
1

LSB
BUFFER OUTPUT CONTROL

~
~
~
~
~
~
~
~9

~
~

+15VDC

sa

~
PCM75

~

~
~22

~

~

~

~
18

S2

ADC INPUT 1:!"5VDCI

S4

I
-:F
2.7kn
S7

I ~3

•,J.,

A.k
LF356

....

- s:5

>m

FIGURE 19. PCM75 Used Both as an A D Converter and as a D A Converter.

5-107

• +5VUC

81°

~

;n}-

~

COlVERT COMMAND

~

~
>i1
~

LSB

~
~

DIGITAL COMMON
AUDIO COMMON
OAC OUTPUT I '5VOCI

STATUS OUTPUT
·15VDC

,

I

/

/
5-108

DIGITAL-TO-ANALOG
CONVERTERS

The Burr-Brown digital-to-analog converter product line contains a
broad variety of products designed to simplify your task of converting
digital information to analog form. The available, products provide
resolutions ranging from 8 bits to 16 bits, and encompass a variety of
performance features and package types engineered to meet your
needs for accuracy and reliability at low cost.
These products are designed to ease the task of application. Most
units are complete, requiring no external components to aChieve the
desired function. All the D/A converters listed in this section include an
internal reference and most have an output voltage amplifier,although
the line also includes current output versions carefully designed for
applications requiring current outputs, such as driving displays.
For low-cost general-purpose applications, consider the pin-compatible DAC800 and DAC80. If you require high resolution and accuracy,
such as in test equipment and high performance instrumentation, the
DAC700 and DAC70 families provide a variety of alternatives. Need
high speed? Try the ECl-compatible DAC63 or TTL-compatible
DAC812. The PCM52 and PCM53 have been optimized to provide 16bit resolution with very low total harmonic distortion, required in audio
and acoustic applications. Recent additions to the line include
DAC708n09 and DAC811, designed for complete microprocessor
compatibility. Refer to the Selection Guide in this section for a complete listing of available products.
Whether your system requires low cost, high resolution, high speed,
wide temperature range, or low drift, consider Burr-Brown-a world
leader in D/A converters.

6-1

,SELECTION GtnOE
DIGITAL-TO-ANALOG CONVERTERS
Our DAC80 is a standard in 12-bit perfonnance.,DAC800

-a monolithic IC-continues this proven product offering the same pinout, functions and improved, perfor' ", ,"
mance at a lower price.
16-bit designs from Burr-Brown have also Set industry
standards: DAC71 is the industry stahdard}ow:::¢ost 16-

Description
High
Resolution
Monolithic

High
Resolution
Mlcroprocessor
Compatible

Monolithic'·11
12-Blt

Mod.ln!

bit D / A; DAC701 and DAC703 are complete 16-bit
monolithics with op amps an.d voltage reference on the
chip.
EClrcompatible DAC63employs new technology and
higher levels ,of mtegration to achieve 35nsec (typ to
±o.OI2%) settling time and excellent temperature and
timestl:\bilitY,atlow cost. '

,
DIGITAL:TQ-ANALOG 'CONVERTERS
Accy, Drift
Resolu- i Linearity
Settling
Error. max ~Ipoiar, max
tlon
TI,me(FSR,
D\IIP'!t,
(Bits)
Raf!lles '
('!IooIFS~) (ppmFSRrC)
±lI2LSB)
'Oto-2mA
Oto-2mA
Oto+l0V
!lto+1OV
±1mA
±;MA'
±1OV
±10V

DAC700KH
DAC700BH
DAC701KH
DAC701BH
DAC702KH
DAC702BH
DAC703KH
DAC703BH

16
,6
16,
16
16
16
16
16

±o.o03
±a,003
±a,0q3
±a.OO3
±o,OO3
±a.OO3
±a.OO3
±a,003

DAC706KH
DAC706BH
DAC707KH
DAC707BH

16
16
16
16

±a,003
±a.OO3
±a,003
±a,003

±25
±25
±25
±25

Oto-2mA
±1mA
±5V,±10V
Oto+l0V

DAC706KH
DAC706BH
DAC709KH
DAC709BH

16
16
16
16

' ±a.OO3
±a,003
±a,003
±a.OO3

±25
±25
±25
,', ±25

Oto-2mA
±lmA
Oto+1OV
Oto+10V

DACIIOO-CBI-I
DAC800-CBI-V

12
12

±O.O12
±a.012

±2Sf4J
±25

±1,-2mA
±2,5, ±5, ±10,
+S,+10V

3OOnsac'

DAC800PCBI-V

12

±a,012

±25

DACS50-CBI-1
DACS50-CBI-V

12
12

±a,012

±17141

±O,O12

DAC651-CBI-1
DAC651-CBI-V

12
12

±a,012
±a.012

DAC611AH "
DAC611BH
DAC811 Kt,f
DAC811SH

12
12,
12
12

DAC80-CBI-I'"
DAC80-CBI_V'"!
DAC80-CCD-I'"'
DAC80-CCD-V'"

±28
±2B
±28

±28.uP
±25'"
±2S
±25
±25

350naec
350naec

.c,.aac

~
360naec
350naeC

.c,.aac
4jiaec

.c,.aac
.c,.aac
.c,.aac
.c,.aac
.c,.aac
.c,.aac

Temp
Range
III

Com
Ind
Com
Ind
Com
Ind
Com
Ind

LowCoeI

Low Drift

DAC85-CBH.

Ceramic
Hermetic
26-pln'
DIP

6-115
6-11S
6-11S
6-115

Com
Ind
Com
Ind

Ceramic
Hermetic
24-pln
DIP

6-115
6-115
6-115
6-115

a,.sac

Com
Com

Ceramic
24-pln
DIP

6-128
6-126

±2,S, ±S, ±10,
+S.+10V

a,.sac

Com

Plastic

6-126

±1.-2mA
±2.S. ±S. ±10,
+5.+10V

000n8ac

±17

Ind
Ind

Ceramic
Hermetic
24-pln
'DIP

,6-147
6-147

±30f41
±30

, ±1.-2mA
±2,S. ±5, ±10.
+S,+1OV

3OOn_

MIL
MIL

Ceramic
Harmetlc
24-pln
DIP

6·147
6-147

'±a.012
±a,006
±a,012
±a;006

±30
±20

±5,
±S,
±S.
±S,

Ind
Ind
Ind
Ind

Ceramic
'24-pin
DIP

6-133
6-133,
, 6-133
6-133

12
12

±a.012
±a.012

!l:::2S!"

3 digits
3 digits

±a.025
±a.025

±25'"
±25

12

±O,O12

'±20'"

±1.0.-2mA

12

±0,012

±20

12

±a.Q,12

±30'B'

±2.S. ±S. ±10;
+S,+1OV
±1,O.-2mA

12

±a.012

±30

12

±a.012

±30
±20
±25,

±10, +lOV
±10. +10V
±10; HOV
±10. +lOV

±l,O.-2mA
±2,S, ±S, ±10.
+S.+10V
Oto-2mA
Oto+l0V

(0)

DAC85-CBI-V.
(0)

DAC65C-CBI-I.
(0)

DAC65C-CBI-V,
(0)

DAC65LD-CBI-V

Ceramic
' 24-pln
'DIP

Page
6-107
, 6-107
6-,07
6-107
6-107
6-107
6-107
6-107

Com
Ind
, Com
Ind

4jIaac
4jIaac

a,.sac

a,.aac

"

Microprocessor
Compatible

Package

±S

±2,S, ±5. ±10,
+5.+1OV
±2,S, ±S. ±10,
+5,+10V

.c,.aac,
~

4jIaac
4jIaac

OOOnaec

a,.aac

Com
Com

300naec

Com

Ceramic
24-pln
DIP

,,6-77
6-77

Com

6-77
6-77

'3QOnaaC

Ind

6-94

a,.sac

Ind

a,.sac

OOOnsac

Com

a,.aac

Com

3I.t8ec

Ind

6-94 '
Metal'
HermetiC
, 24-pln "
DIP

6-94
6-94
'6-94

DIGITAL-TO-ANALOG CONVERTERS

Accy. Drift
Bipolar, max
(ppm FSRI"C)

Output
Ranges

Settling
Time (FSR,
±lI2LSB)

Temp
Range

(Bits)

Linearity
Error max
('11001 FSR)

DAC7G-CSB-1
DAC7G-COB:-I,
(a)

16
16

±0.003
±O.OO3

±i8.1
±7'81

Oto-2mA
±lmA

50jMc
50peec

Ind
Ind

DAC71-CSB-1
DAC71-COB-1
DAC71-CCD-1
DAC71-CSB-V
DAC71-COB-V
DAC71-CCD-V

16
16
4dlglta
16
16
4 digits

±O.OO3
±O.OO3
±O.OO5
±O.OO3
±O.OO3
±O:OO5

±1SC81
±1S18t
±1S111

Oto-2mA
±lmA
Oto-2mA
Oto+l0V
±lOV
Oto+1OV

1,...:
1,...:
1,...:
lo,-c
lo,-c
lo,-c

Com
Com
Com
Com
Com
Com

DAC72-CSB-1
DAC72-COB-1
DAC72-CCD-1
DAC72-CSB-V
DAC72-COB-V
DAC72'CCD-V

16
16
4 digits
16
16
4 digits

±O.OO3
±O.OO3
±O.OO5
±O.OO3
±O.OO3
±O.OO5

±19
±19
• ±19

Oto.-2mA
±lmA
Oto-2mA
Oto+l0V
±lOV
Oto+l0V

1,...:
1,...:
1,...:
lo,-c
lo,-c
lo,-c

Ind
100
Ind
Ind
Ind
Ind

Metal
Hermetic
24-pin
DIP

DAC73J
DAC73K
DAC736J
DAC736K

16
16
16
16

±0.O15
±O.OOO75
±0.0015
±O.OOO75

±22
±22
±22
±22

oto -2, ±lmA,
±2.5, ±5, ±10,
+5,+10V

50jMc
50peec
50peec
50jMc

Com
Com
Com
Com

Module
Module
Module
Module

6-54
6-54
6-54
6-54

Very-Wide
temperature
Range

DAC10HT
DAC10HT-l

12
12

±O.012
±0.048

±20
±50

±2.5, ±5, ±10,
+S,+10V

200naec
200naec

-55'C
to
+2OO'C

Ceramic
24-pin
DIP

6-5
6-S

Very-High
Speed

DAC60-10
DAC60-12

10
12

±0.048
±0.012

±1SC81
±1S 181

Oto-5,
±2.SmA

40naec
l50naec

Com
Com

Module
Module

6-13
6-13

Ultra-High
Speed

DAC63BG
DAC63CG

12
12

±O.012
±0.012

±21
±16

±5,-IOmA
±S,-10mA

35naec
3Snaec

Ind
Ind

DAC63BM
DAC63CM
DAC63SM
DAC63TM

12
12
12
12

±0.012
±O.012
±O.018
±O.018

±21
±16
±21
±16

±S,-IOmA
±5,-IOmA
±S,-10mA
±5,-10mA

3Snsec
40nsec
40nsec
40nsec

Ind
Ind
MIL
MIL

Ceramic I
24-pin
DIP
Metal
Hermetic I
24-pln
DIP

DAC812BM
DAC812CM

12
12

±O.018
±0.012

±47
±25

±S,-10mA
±S,-IOmA

65nsec
80naec

Ind
Ind

Hermetic

Resolution

Description
High
Resolution

HighResolution

Highly
Accurate

Model '11

±15
±15
±15

±19 1e.1
±19~'

±19 161

...

Package

Page

Metal
Hermetic
24-pin
DIP

6-26
6-26

6-34
6-34
6-34
'6-34
6-34
6-34

Ceramic
24-pin
DIP

6-44

6-44
6-44 .

6-44
6-44

6-44

I
I

Metal

6-18
6-18
6-18
6-18
6-18
6-18
6-141
6-141

24-pln
DIP
Military

DAC87/MIL Series

Low Cost

DAC82KG

Monolithic
80Bit

DAC90BG, (a)
DACBOSG, (a)

See Military Products
8

8
8

±0.16

±0.2
±0.2

. ±50

±7S''''
±7S ItIl

±2.S, ±S, ±10
+5, +10, ±O.8,
Oto-l.6mA

2.5j.tsec

±1,-2mA
±1,-2mA

200nsec
200nsec

Com

Ceramic

6-87'

18 pin
DIP
Ind
MIL

Ceramic
Hermetic
16-pin DIF

6-102
6-102

a

NOTES: (1) "(0)" indicates product also available with screening lor Increased reliability. See Program. (2) Com = 0 to +70'C; Ind =
-25'C to +8S'C; MIL = -55'C to +12S'C. (3) Connected internally lor unipolar operation. (4) In -V models the output op amp is on a
second chip. (5) "Z" mod$ls operate from ±12VDC supply. (6) When used with an external op amp which uses the internal feedback

resistor.

PCM DIGITAL-TO-ANALOG CONVERTERS FOR AUDIO

Model

(Bits)

Total Harmonic
Distortion
(max)

PCMS1JG
PCM52JG-V
PCM53JG-V
PCM53JG-1
PCM53JP-V

16
16
16
16
16

0.04% at -15dB
0.002'110 at F.S.
0.002'110 at F.S.
O.OO2'IfoatF.S.
0.002'110 at F.S.

Resolution

Description
PCM-Audio D/A Converter

-

Settling

Time

Output
Range

Range'"

Dynamic
Range

Page

5j.tsec
3psec
. 3psec
350nsec
3psec

±10,±5V
±SV
±10V
±lmA
±10V

Com
Com
Com
Com
Com·

96dB
96dB
96dB
96dB
96dB

6-154
6-162
6-162
6-162
6-162

NOTES: (1)Com=Oto+70'C.

6-3

Temp

·

.

. .,

'SELF-CALIBRATING, ..,IGH, PRE,CiSION D/A CONVERTER

This unique 16-bit Df A converter is actuaily ~ instru~
ment. The heart isa highly accurate 16-bit D/ A converter with a heated, temperature compensated precision
reference. Wrapped around this D f A are mi(~,rocomputer-

controlled measurement and calibration Circuits' that
automatically null out gain" offset and linearity errors
caused by shifts with time and temperature when initiated by one negative-going TTL-pulse provided by the '
user.

SELF-CALIBRATING D/A CONVERTER
Descrlpllon

Model

Reeolutlon

Total Error
+15 to +45°C

Precision,
High-Resolution

DAC74

16bilS

±0,00f5'11o, max

"",

Outpul
RanQ88 ,

Calibration TI\TIe

Package

Page

Oto+10V
±10V

2;5aec, initiated by 15peac
nagatlva TTL pulse

7" x 5" x 0,600"
metal

6-62

6-4

BURR--BROWN®

DAC10HT

lEila.

Wide Temperature Range
General Purpose 12-Bit
DIGITAL-TO-ANALOG CONVERTER
FEATURES
• -55°C to +2000C SPECIFICATIONS
• FULL 12-BIT RESOLUTION
• 200nsec SETTLING TIME. TYPICAL
• MONOTONIC OVER FULL TEMPERATURE
RANGE
• TTL ANO CMOS COMPATIBLE
• HERMETIC OUAL-WIDTH CERAMIC
PACKAGE

DESCRIPTION
Designed for use in circuits that operate over a wide
temperature range. DACIOHT is a general purpose.
12-bit. D/A converter. The design uses state-of-theart integrated circuit and laser-trimmed thin-film
techniques for maximum accuracy. Compatible with
TTL and CMOS logic. DACIOHT is monotonic
over the full -55"C to· +200"C temperture range.
Special design techniques minimize output glitches.
The package is compact. dual-width. 24-pin ceramic
DIL.
100% screening operations are conducted at key
manufacturing steps. Burn-in and temperature cycling are exaniples. and the product is assembled in ~
dean-room environment.

GAIN
SETTLING
RESISTOR

12·BIT
LADDER
RESISTOR
NETWORK
AND
CURRENT
SWITCHES

BIPOLAR
OFFSET
RESISTOR

)
'.

EXTERNAL
OUTPUT
AMPLIFIER

C

REFERENCE
CONTROL
CIRCUIT

EXTERNAL
} "REFERENCE

Inlernational Airport Induslrlal Park· P.O. Box 114110· Tucson. Arizona 85734 . Tel. 16021 746·1111 . Twx: 91 ()'952· II 1I . Cable: BBRCORP . Telex: 66·6491

6-5

SPECIf'ICATIONS
ELECTRICAL
Speciflcalions al Vee = +15VDC VEE

=-15VDC Refef8nce =+1OVDC
I

MIN

I TYP I

and TA

MAX

=+25'C unless Olherwise noled

I

MIN

I

TV',,'

I

MAX

'J

IN"'"

DIGITAL INIIUTS

RaaoIution
TTL-Logic "I" all00na, max
Logic ~'O" at -100pA, max
Logic :'0" al-l00pA, max at +200'C
CMOSI1l-Logic "I" all00nA, max
logic ','0" al-l00,.A, max

12
2.0

12
2.0

Bils
V
O.B
0.6

O.B
0.6

V

~Vee

70'lI0 Vee

V

~VCC

30'lIo Vee

V

±1/4

±112

LSB
LSB

0.05
0.05

±2
0.2
0.2
0.2

TRANIFIER CHARACftIIIITICS
.ACCURACY
Li....rity Error al +25'C.
12-BII
10-841
at -ssoC to +2OO"C
12-841
10-811
Gain Error(2)
Bipola.r Of18t Erro.r IlnpulaU 0'1/(2)
Unipolar Ollaat Error I Input all O'S,(2)
Monotonic Temperature Range
12-BII
100BII
Differenllal LI....rity Error
12-841
100Bil
Totel Unadjusted Error(3)
+25'C
-55"C 10 +2OO"C
Total Adjuated Error(4)
+25'C
-55'C 10 +2OO"C

±1/4'

±112"

±2
0.05
0.05

LSB

0.2.
0.2
0.2

LSB
'!Io
. '!IootFSR.
'!loot FSR

+200
+200
±1/2

LSB

±1

±112

±1

LSB

±O.1
±O.3

±O.4
±O.B

±O.15
±O.90

±O.45
±1.30

'!Io0l FSR
'lIIof FSR

±O.OO6
±O.015

±O.012
±O.40

0,024
±O.40

±O.048
±O.90

'!Ioof fSR
'!IooIFSR

CONVERSION Il'EED
Sellllng Time to 112LSB ,+FS change ,(5)
Major Carry Glilch Duration
I to 8O'Ift complete)

200

200

nsec

35

35

nsec

DRIPT 1-5!5'C to +2OO"C,
Gain I excluelve 01 reference drift'
Bipolar Oliset
Unipolar Offset
Differential Linearity

±2
±2
±O.5

±2

±5
±5
±2
±3

±10
±10
±1
±3

±25
±25
±5
±4

ppml'C
ppm of FSRI'C
ppm of FSAtoC
ppm of FSR/oC

OUTPUT
Current - Unipolar ,±10'II0,
Current - Bipolar 1±101Mt!
Selectable Rangesl8)
Resistance
Capacitance
Compliance VoUage

~2.~:!2.5'

oto +5, 0 to +10, -2.5 to +2.5,
-5 to1 +5,~0 1°1+ 10
-3

+10

~2.~:~

;2.5',
010 +5, 0 to +10, -2.5 to +2.5
-5 to1+5.~0

10t
I

-3

O.
+10

mA
mA
V'
kll
pF

V

EXTERNAL ADJUSTMENTS
Gain Adjust Range
Bipolar Offset Adjust Range
Unipolar offsei Adjust Range

±O.25
±O.25
±O.25

NOIII! 10.IHz 1010Hz, all "I".,
MULTIP\.YINO MODE PERfORMANCE
Number of Quadrants(7)
Reference Voltage Range
. Accuracy(8)
Feedlhroughi.)
Outpul Slew RalePO)
.Outpul Settling Time 110 0.01'!lo of FS 1(10)
Control Amplifier BW ,smail-signal,
closed-loop,

30

2

o

%olFSR
'!Iool FSR
'!Io of FSR

±O.25
±O.25
±O.25
30

+10.24

±O.05

~V.

pop

2

o

+10.24

±O.05
±O,02

±O.02

6
3

6
3

10 .

10

V
'lII of FSR
%01 FSR
mA/Jolsec
~sec

MHz

POWER IUl'I'LlEl AND REFERENCE
Reference Input Impedance
Reference Voltage Range
Power Supply, Voltage - Vee
Voltage - Vee
Current - Vee
Current - VEE
Power Supply Sensitivity
Vee'al +5VDC
VEE al-15VDC

8±10'110

o
+4.75
-13.5

8±10%

o

-15
+9
-28.

+10.24
+15.0
-16.5
+15.0
-<40.0

1
3

5

I

10

3

+4.75
-13.5

-15

+10.24
+15.0
-16.5

+9

-28
,5.'
10

kll
V
VDC
VDC
mA
mA
ppml'!lo6V
ppml'lll6V

SPECIFICATIONS
MODEL

I

DAC10HT
TYP
I

I

MIN

MAX

I

MIN

DAC1OHT-l
TYP

1

J

MAX

I

UNITS

+200
+200
+210

.,

°C
°C
°C

TEMPERATURE RANGE

,

Specification
Qperating
Storage

1

-55
-55
-65

+200
+200
+210

-55
-55
-65

I ! I I

NOTES:
1. +4.75V < Vee < +15.0V and pin 2 tied to pin 1.
2. Adjustable to zero I see Figures 4' and 51.
3.lneludes Gain, Offset, and Linearity Errors with external +10.0V ±lmV
reference. Does not include Reference Drift.
4. Gain and O.lIset Errors removed at +25°C with external +10.OV ±1 mV
refere:nce. Does not include Reference Drift.
5. Current settling' into short circuit.
6. Using intemalscaling·resiSlors and OPAllHT output op amp.
7. Bipolar operation at digital inputs only.
8. For.1VDC reference vohege I see Figure 21. Full Scale Range = IV.
9. Voltage at reference input'O to +1OV. 2kHz sine wave (see Figure 31,
10. All "l"s. 10V step on reference input.

PIN DESIGNATIONS
1
+Vcc
LOGIC THRESHOLD
2
VREF INPUT, LO,
3
4
N/C
VRE~ INPUT, HI·
S
-VEE
6
BIPOLAR OFFSET
7
BIPOLAR OFFSET
8
CURRENT OUTPUT
9
10VRANGE 10·
20VRANGE 11
COMMON 12

24
23
22
21
20
19
18
17
16
·15
14
13

BIT lIMSB,
BIT2
BIT 3
BIT4
BITS
BIT6
BIT7
BIT8
BIT9
BIT 10
BIT 11
BIT 12 ,LSB'

MECHANICAL

24

01

l

o
A

13

12

Jmmmm~Jj
L+ --i

I i

0

F--llj

G

l-

INCHES

DIM

MIN

H

MIN

1.215

30.10

:105

.110
.021

2.67
0.38

.035
G

MILllMETEAS

1.185
0

"Seating Plane

MAX

.060

. lOa BASIC
.030
.. ODS

Pin numbers shown for reference o~Jy.
Numbers may not be marked on package.

.120

NOTE:
Leads in true position within 0.010"
I 0.25mm ,R at MMC at seating plane,

.025

.070
.012
.240

.600 BASIC

0.89

30.86
4.32
0.53
1.52

2.!>4 BASIC
0.76

11.

,0.20

0.30

3.05

6.10

15.24·BASIC
~

10° •

.060

MAX

0.64

0°

1.52

CASE: Ceramic with hermetic seal

CONNECTION. DIAGRAM· UNIPOLAR

CONNECTION DIAGRAM· BIPOLAR

Bill
Bit 12
(MSB) BIU Bit 3 BlI 4 BIt5 Bft B Bft 1 Bit B Bit 9 Bft 10 Bit II LSB)

Bill
Bit 12
(MSI) III 2 Blt:i BII 4 Bit 5 Bft 8 Bft 7 Bit B BII 9 BIlIO Bit II ILSB,

13

+5/+15VDC

-15Voe

+15VDC

·In high temperature environmentS'with high levels of shock and vibration it is recommended that discrete wirewound .or metal film resistors be used
instead of potentiometers.

6-7

I-

=

-

c::t

U

~

DI~CUSSION

OF SPECIFICATIONS

DIGITAL INPUT CODE$,:
DAC I0 liT 'accepts a positive-true straight binary (BIN)
input code. Offset-binary code is created by offsetting the'
output amplifier' with the DAC reference. Two's complement Code is obtained from-6ffset binary by inverting
bit I (the most significam. bit) ej(ternally. See Table I.

...

:,.

..

":";"

'

"

DACIOHT.
Leakage Current is measured at the converter 61,itput with
logic 0 on all digital inputs. It appears a·~. ~art of offset
error, both at room' temperature an~'over the specified
temperature range. In the unipolar configuration,
virtually all offset error is d.ueto leakage current.

,

ACCURAcy
Linearity of the DAC IOHT is guaranteed tobe within the
specification over 'its. temperature range. This is the
measure of the devia~ion of the actual transfer curve from
the ideal transfer cu~ve expressed graphically as, a straight
line dra}Vn !)etwt<~nthe end~pojnt .values. For the
DACIOHT the maximum deviation is'±1)2LSB at 2S·C
and ± I LSB over the full specification temperature range
ftom -SS"C to +200"C.
Differential Linearity error is the deviation from an ideal
JLSB output voltage change from one adjacent state to
the next. An error specification of ±I /2LSB indicates
that outP\lt voltage step size; can range from 1/ 2LSB to
3/ 2LSB betweell adjacent states. .~
Monotonicity is. an important .property for a 0/ A.
:converter, especially one .used in. a.closed control loop. A
converter is monotonic if tlte output signal increases or
remains the same for an increase in digital input. A
converter'sdlfferentild linearity determines whether or
not it is monotonic: If differential linearity is <± I LSB,
'the converter will'be monotonic.· Monotonicity is guar.(anteed over the entire' spedfied temperature range for the

DRrFT
. Gain Drift is a measure of the· change iil the full scale
range output' due to: a: challge in ,temperature and is
expressed in.parts pc;r miliion per ",C (ppml"c). It is
calculated by 'determining the fuUscale range value at
high temperature, then at low temperature. The difference
the two values is divided by the difference in the two
temperatures.
Offset Drift is a measure of the actual change in output
. over the specified temperature range with.iogic oori all
digital inputs. It is calculated by measuring offset voltage
at the temperature extremes .. The ma)(imuql change
referred to the offset voltage at +2S·C is divided by the
temperature excursion from +2S°C. Offset drift is
expressed in parts per million of full scale range per ·C
(ppm of FSRI"c).
.
Differential Linearity Drift (the change in differential
linearity over the specified temperature range) is cah
'culated in a manner similar touffset drift.and is expressed
in ppm of FSRI"C.

j'n

T ABLE I. Digital Input Codes.
, DIGITAL INPUT CODES
ANALOG OUTPUT
VOLTAGE'

LOGIC INPUTS
Binary
If1Hlflllll
100009000000
Ott.lttlllll1
000000000000

CURRENT

o to +tOV

-IOV 10 +IOV

Oto -2mA

··+9.9978V .
+5.0000V
+4.9978V
O.OOOOV

+9.9951V
O.oootiv
-0.00491/ ."
-10.0000V

·-I._1nK
-I,OOOOm".
-O.9995mA
O.OOOOmA

',.

-1·mA to +1 InA.
-O.9995mA·
Q.O!IOOmA
+O.OOOSmA
+1.0000mA

Binary two's Complement··

01111tt11111
t111111111.11
I~

IlS!! (BINI
'To obtain valu•• for other binary rang. .:
to +5V range: divide O-to'+IOV'rangevalues'by 2:'
±SV range: dl~id. ±1.0V rang~ values by 2.

o

-o._mA
O.OOOOmA
+O.OOO5mA
+l.OOOOmA

+9.9951i1
O.OOOOV
-O.0049V
-IO.OOOV

OOOOOOOOOOOO

!4.88mV

O.488pA

±2.5V range: divide :tl OV range value. by 4.
"MSB must be inverted externally lor'thls code:

CONVERSION SPEED
Settling Time is tbe time reqUired for the output to enter,
lind re'main within an error.. band of 'the final value:
ineasured from the time the digital input is chang~d.
The settling time for a I LSSchange at the il)Pii.t is
naturally less than for a full scale change. It is greatest at
the major carry point (the point at which. all of the bits
change states) due to nonuniform switching times of the

internal current switches. For a I LS~ ,,~ange at the major
c~rry point~ settlipg time to within O.OI;%wHltypically be,

200nsec;

."

,.

,

.

COMPLIANCE VOt~~GE
'This is themax.imum voltage which can be impressed on
t.he.currenl output npde and still remain withi," the
specified accuracy. These voltages are -3.0Vand+IOV.

6-8

Feedthrough of the DACIOHT is theamount of reference
signal that appears at the output when all digital inputs
are logic O. Expressed in % of FSR, it increases with
increasing reference frequency (see Figure 3).

POWER SUPPLY SENSITIVITY

This measure of the effect of a power supply voltage
change on the Dj A converter output is defined as a
percent of FSRjpercent of change in either the +5V,
+ 15V or -15V power supplies about the nominal supply
voltages. 'Figure I shows power supply rejection vs
frequency.

0,08
0.07

1000

0.08

~'0

+15-

'>
..,

/

100

i

II.

'0

/

i

~

0.05

~

g. 0.04

./

e

/

~ 0.03

i
0.02
0,01

10

-15

o
10

FIGURE 1.

100

lK
10K
Frequency (Hz-)

-

J

/

10

100

lK

l'OK

lOOK

1M

Frequency IHzl

FIGURE 3. Feedthrough Voltage vs Power-Supply
Ripple Frequency (Unipolar Mode).

lOOK

Power~Supply Rejection vs
Power-Supply Ripple Frequency.

OPERATING INSTRUCTIONS
MULTIPLYING MODE PERFORMANCE

INPUT LOGIC LEVELS
Inputs of the DACIOHT are either TTL or CMOS logic
compatible. For TTL, connect +5V to pin I (pin 2 open).
For +5V CMOS, connect +5V to pins I and 2. For + 15V
CMOS compatibility, connect +15Vto pins.! JlDd 2.

The output of the DACIOHT is the product of the
reference input and digital input values. The reference
may be an AC signal and can vary from 0 to + 10 volts.
This is useful in applications where digitally programmed
attenuation of a signal is desired. Bcause the reference
voltage input must be positive, the DACIOHT muitiplies
in two quadrants only. For highest accuracy the input
reference voltage should be as high as possible (see
Figure 2).
0.10

In circuits where pin 2 is used to determine the digital
threshold level, the following application tip may be
helpful. If ,the analog system ground (to which the
DACIOHT is referred) is separate from the digital driving
logic ground, the threshold voltage input.(at pin 2) may be
driven from an external voltage source to keep the
threshold at proper value. Threshold voltage will always
beat one-half the voltage applied to pin 2 (+1.4V < pin 2
<+15V).

I

0.09

I

ffi 0.08

II.

~ 0.07

i

'0

0.06

~ 0,05

g0,04
:::I

~c:

'ii

POWER SUPPLIES
Each power supply should be bypassed to ground with a
O.I#,F capacitor as shown in the Connection Diagrams.
Locate the capacitors as close as possible to the
DACIOHT.

i

:::I

0.03

\

\

~

Cl 0.02
0.01
0,00
2

GAIN AND OFFSET ADJUSTMENTS

~

........

......

(Voltage Output Configuration)
Initial gain and offset errors of the DACIOHT circuit may
be trimmed out using the following procedures.
Unipolar configuration - input all O's and nun offset error
by adjusting R3 until output voltage equals zero. Input all
I's and adjust RI until the output voltage is +FS -I LSB
(see Table I and Connection Diagram).

r---.. 100..

3
4
5
6
7
Reference Input (Volts)

8

9

10

FIGURE 2. Gain Accuracy vs Reference Voltage.

6-9

I-

-=

C)
~

cC)

Bipolar con(ig\lrlltion.~ inpllt·llll.Q's and null offset error

LOW POWER OPER.ATIOIII
Tht;typical,supply cu~rent~ r~qui;'c:d by'the 6ACIOHT
under. normal operating coriditions are 9mA (Vi.;dand
28mA(V EE). The average power required (PI» islherefore
PJ1,;=IVcc x9mAj'+lvE E x 28mAj
.. , .
. = 555mW (+Vs = 15V,-Vs = 15V), or .
= 46SmW (+Vs ~ SV, -Vs = 15V). .

b~ adjusting R~;until outputvol~g"eq\lals ~FS.lnput ~ll

I's lind adjust RJ Il.nti!. the output vQU,l!.geis+FS - I LSB
(see Table I and Conm~chonDjagram).
'.
To obtain specified gain and offset errors, replace the SOH
potentiotneters(Ri and Ri) shown· in the Connection
. Diagrams with 25H 0.1 % fixed resistors.
.

SELECTING AN EXTERNAL REFERENCE
DACIOHr is configured to use a +IOV reference. An
internal8kH resistor in series with an external SOH adjust
potentiometer sets the current into the reference input at .
1.25mA (see Figure 4).
Temperature drift of the reference increases drift of the
entire circuit. In unipolar configurations the drift
specification adds directly to the total circuit drift. In the
bipolar configuration some· drift cancelling effects take
plllce. One~half of tl)e reference drift added to the total'
DAC drift will give total circuit drift.

4

I.25InA

. Ito.

Under certain operating conditions this power consumption can be reduced to as little as 245m W.
. The major contributor to the power consumption is the
-15V supply. As long as a +IOV reference.is used, Vn
must be between -13.5V and -16.5V; If, however, a lower
reference voltage'is used, VEE can be reduced considerably
and' this greatly reduces the power consumption. Lowering the reference voltage will, of course, lower the full
scale. output voltage by a proportional amount. For
.example, .if the reference voltage is +5V, the full scale
output voltage when using the IOV range. pin (pin 10) will
be +5V instead of + I OV With a + IOV reference in the
unipolar mode of operation. Table II indicates the
miitimumsupply voltages an.d the. power consumption
obtained when using these supply voltages for various
valuesofVREF. See also page IOfora discussion of how to
build a'low power voltage reference circuit .
TABLE II. Minimum Power Supply Voltages and
Typical Power Consumptio!1 for Operation
with Various Values of VREF•

+

FIGURE 4. Using a +IOV Re'ferenc~.

SELECTING AN EXTERNAL REFERENCE

Building .An Exte,nal +10Y 2CJOOC Reterence
The DAClOHT requires an external +lOV reference for
normal operation. A circuit for obtaining this reference
voltage that will operate at +200°C is shown in Figure
5. The value of RJ or R2 should be adjusted to provide
a reference voltage of 10V ±lmV due to the tolerance
of the zener voltage. With no adjustment to the zener
current for optimum zeroT.C. point (see page 10), this
reference will have an average temperature coefficient
of about ±20ppmjOC over-55OC to +200OC.

External

+Vcc

,

,

-VEE

Total Power

VREF

(Pin 11

(Pln6,

. c<>nsumption .I TYllical,

+lOV

+5V.

-13V

409mW

+6.3V

+5.V

-10V

275mW

+5V

+5V

-8V

235mW

SELECTING AN OUTPUT AMPLIFIER
The most important characteristics of the outp'utamplifier
are input offset voltage drift. input bias (or difference)
current drift. and settling time. Specifications overtlie full
operating temperature range are very important. Initial
input offset voltage and bias current effects will be
trimmed out. but bias errors will be introduced as these
parameters drift with temperature changes. Errors
introduced will appear as offset in the 0'1 A circuit output.
Table III provides the equations used to convert these
amplifier errors to OJ A output errors.
TABLE III. Compliting DAC Error Contributed by
External Amplifier.
PARAMETER

UNIPOLAR
CONFIGURATION

18 x RF
(Bias

+IOV

~------------~~v~

-=

VOl ( 1

C0825
(COMI'BIUTED
DEVICEII

VOl

x 100

TsR

RF)
+ -:.-

lkl!

FSR

.

x 100

BIPOLAR
CONFIGURATION

~)(100
FSR

RF
Vos ( 1 +-'.)
·O.Skl!
x 100
FSR

FSR = full scale range r-2.5V to +2.5V is a 5V FSR, etc. '. Results
are in % of FSR; tO'get ppm 01 FSR, multiply by 104.
RF is the vall,le of the feedback resistor.
RF1 and RF2 are options s~own in Figure 7:

FIGURE 5. +lOVReference That Will Operate At
+200°C.

6-10

Example:
If V", drift and Ihl'" drift of the output amplifier are
10MV!"C and 0.5nAj"C, respectively. in aD Aconverter
with -IOV to + IOV output. the output drift due to these
effects would be computed in this manner.
(

v...:

(10. 10") I

connecting the internal resistors as shown in figure 7:
Output voltage range of this circuit is approximately
±2.25V.

....---------,11

10kll)

!tn

+ 4.iikii

x 100

20

= 0.00018%

10

of FSR "C'

or 1.8ppm of FSR;"C
I.... ; O.S. 10:0, (10k/}) • 100

~ 0.00003% of FSR

""C

orO.Jppm of FSRI"C
Total error contribution of amplifier = 1.8 + 0.3 = 2.lppm of FSR "c

Effects of input bias current drift may be reduced
approximately by a factor of 5 by placing a resistor in
series with the positive input lead of the amplifier as
shown in Figure 6.

--------,7

~5011

,-----lb----'h---FROM v rei

Uku
2kn

RFI

/

10

2kJl RF2

Gain and offset adjustments arc made as described
previously except the "+FS" and "-FS" are intercl1anged
and "-FS + II.SB substituted for +FS -II.SB.
Unipolar and other bipolar ranges may be selected by
using an external load resistor as long as the compliance voltage limits, -3.0V to +IOV, are observed. To
minimize temperature drift when using an external
CI
load resistor, (R2 in Figure 8), an external referencec:.:t
current-setting resistor should also be used. These two C
CI
resistors should track over temperature as explained in
the section on selecting an external reference on the
previous page.

....

----,
11-';'

FIGURE 7. Bipolar Current Output Operation
Utilizing Internal Resistors.

=

-

I
I
I
I

I
I
I

Ikn
12

FIGURE 6. Equivalent Output Circuit.
This balances the offset created by bias currents and the
error is reduced to the difference in bias currents in the
positive and negative inputs. (Substitute 1..""., in equations
in Table Ill).
The value of this resistor is shown in Table IV for different
output ranges.

MULTIPLYING MODE OPERATION
DAC IOHT can he used as a two-quadrant multiplying
D A converter hy applying the analog signal to be
processed through a lOon potentiometer to the reference
YOlta.ge input. pin 5. The analog signal must he hetween 0
and +IOV. The output will be an analog signal equal to
the product of the input analog signal and the input
digital code. DC error of the output signal is less than

TABLE IV. RE Values.
Output
Range

±2.5V

±5V

±10V

0 to +SV

0 to +10V

Re
Value

470n

6lsn

7271l

SOOIl

80011

FIGURE 8. Using an External Load Resistor.
Settling time of the DAC IOHT is less than 400nsec for an
FSR change to within 0.0 Ifii of final value. The output
amplifier's dynamic characteristics should be compatible
with this performance. Burr-Brown's OPAI2HT fastsettling amplifier is recommended for use' up to 175"C.
The OPA II HT is recommended for operation at + 200"C.
CURRENT OUTPUT OPERATION

DAC IOHT can be connected to produce a bipolanoltage
output without the use of external components by

0.05% for a reference voltage range of +1 V to +IOV. For
voltages near zero. the error can be quite large (see Figure

2).

HE~rp!SSIP~TI()!II, ,,",
The DACIOHT dissipates appro~imately 430mW (with
+5V and -15V power supplies) and the package has a
: case-to-ambient ihermal resistance (iJ(,A) of34"C; W. For
. optimum perfo~mance at +200"C. (k~should be lowered
,by a heat sink~or, by forced air over the surface of the
package. If 'the converter is mounted on a Pc card.
improved thermal contact with the copper ground plane
under the package can be achieved by using a silicone
'
.
heat-sink compound'.

",,"

".

6-12

BURR-BROWN@)

DAC60

IEJEJI

Ultra-high Speed
DIGITAL-TO-ANALOG CONVERTER
FEATURES
• 40nsec SETTLING TIME
• 10- AND 12-BITS
• LOW COST
• MONOTONIC
• 1/2LSB DIFFERENTIAL LINEARITY

DESCRIPTION'
The DAC60 is a high speed digital-to-analog'
converter designed for high speed display
applications, for use in high speed AID converters,
and for use as a high speed, precision waveform
generator. The DAC60 is available in 10- and 12-bit
accuracy. The extremely high speed of the DAC60 is
accomplished with low impedance current switching
techniques. The typical settling time to 0.05% for an
. LSB step is 25nsec. The maximum settling time for
the major carry or for a full scale transition is only
40nsec to 0.05%. (The major carry is the LSB
transition from 011 ... II to 100 ... 00).
The DAC60 produces a current output proportional
to the digital input. The most significant bit (MSB)
produces an output of -2.5mA. The DAC60 is pinprogrammable to obtain unipolar or bipolar output
signals. The current output may be fed directly into
the summing junction of an external high speed
operational amplifier, or onto an external summing
resistor. An internal 2kO feedback resistor' is
included. in the DAC60 for use with an external
operational amplifier. This resistor provides voltage
output ranges of 0 to +IOV or ±5V and compensates
for temperature drift of the DAC60.

Intamlllllllli All1JIII1lndUllril1 Part· P.O. Box 11400· Tuaon. Arizona 85734· Tel. [6021 746-1111 . Twx: 91(1.952·1111 . Cable: BBRCORP· Telex: 86-6491

6-13

,'S:I':E,ClflCATIONS
~

,·f. ':": ,.,"'::"

Specifications typical at 25°C and with rated supply unle~"oth,e~ise

noted.

.

~":,

."

ELECTRICAL
MODEL
. DIGIT ~L,INPIJT.S
Data Input Codes

DAC60
10 Bits and 12 Bits
TTL/DTL Compatible
Complell1:entary Logic

TRANSFER CHARACTER,ISTICS
ACCURACY
Linearity Error
Differential Linearity Error (max)
Gain Error

(adjustable to zero)
Offset Error
(adjustable to zero)
Unipolar
Bipolar

"±1/2 tSB
±1/2 LSB

±~.05% of FSR (3)
±O.OOI % of FSR
±0.05% of FSR

Simplified OAC60 Schematic.

ACCURACY DRIFT
Voltage Oulpul{l)
Current Output
Differential Linearity Error
(0° 10 +70°C)
10 bits
'
12 bits
Monotonicity (00 to +70o C)

±15 ppmloC
±30 ppmloC

MECHANICAL

Oimfmsions in parentheses are in inches.
±1/2 LSB

±I LSB
Guaranteed

CONVERSION SPEED
Settling Time for I LSB Change(2)
\00.05%
100.0125%
for full scale change or major
carry change
10 0.05% (max)
,1o 0.0125%

25 os
40 os

~O

ns
150 ns

. POWER SUPPL Y SENSlTIVlTy(4)
±I 5 Volt Supply

±0.002 %/% P.S. Change

OUTPUT'
Unipolar Output Range(5)
Compliance
Output Impedance
Bipolar Output Range(5)
Compliance
Output Impedance

o to -5 mA,

3.2 V
650n
±2.S rnA
0.70 V
516 n

5.1 mm
(.20")

POWER SUPPl Y REQUIREMENTS
Rated Power Supplies
Power Supply Range
Supply Drain (max)

±15 V
±l4.5 to ±15.5 V

+ ___..1 BOTTOM VIEW

L.-_ _ _

+45 rnA, -35 rnA

It.

TEMPERATURE RANGE
Specification
Operating (reduced specs)

Storage

Material
Case - Diallyl Phtalate Shell
uPin I'!laterial and plating composition conform
to Method 2003 (solderability) of MiI-Sld-883
(exce"pt p~ragraph 3.2).u
.
'Conne.tor'- 230lMC
or - 2302MC

0° to +700 C
"--25°C to +85 0 C
-55°C to +iOOoC

('1) When in the voltage output mode using an external op amp

a·~d·the internal feedback resistor as shown in figure

1.

(2) For any data change not involving the four most significant bits.
(3) FSR is Full Scale Range (5 rnA).

(4) The percent change in the output level with a one percent change in power supply voltage."
(5) The unipolar output may be fed into a: resistive load providing a 3.2 volt or less-·swing. It is'recommended that the bipolar
output he fed into the summingjunction of an op amp or a resistive load low enough to limit the swing to less than 100 mY.

6-14 _

DEFINITION OF SPECIFICATIONS
DIFFERENTIAL LlNEARITV ERROR

MONOTONICITV

The differential linearity of the DAC60 is ±1/2 LSB. This
means that any I LSB digital input change will produce an
output change of I LSB ±1/2 LSB (1/2 LSB to 3/2 LSB).
This specification is especially important in CRT display
systems because the eye is sensitive to differential linearity
errors greater than ±I/:? LSB.

The DAC60 is guaranteed to be monotonic over 0 to 700 C.
This means that the output will never decrease for an in·
crease in the digital input.

COMPLIANCE
The compliance voltage of the DAC60 is the maximum voltage swing allowed on the current output node in order to
maintain the specified accuracy; it is 0.70 volts for the
bipolar current 'range of ±2.S rnA and is 3.6 volts for the
unipolar current range of 0 to -5 rnA. The· maximum safe
voltage swing allowed with no damage to the DAC60 output
is ±S volts.

LlNEARITV ERROR
Linearity error is the deviatio'~ .,. 3:1~, output state from an
ideal straight line drawn between the end points (all bits ON
and all bits OFF)
.

DEFINITION OF DIGITAL INPUT CODES.
The DAC60 is available
witli complementary binary
coding. The user may pin
strap the output for bipolar complementary offset binary ot unipolar complementary straight binary.

MSB

OUTPUT
VOLTAGE(2)

OUTPUT
CURRENT(I)

INPUT

BIPOLAR

LSB

111 ... III
Oil ... III
000 ... 000

+2.5 rnA
OmA
-(2.5 rnA -I LSB)

One LSB
10 bits
12 bits

UNIPOLAR
OmA
·2.5 rnA
-(5 rnA -I LSB)

4.88IlA·

4.881lA

1.221'A

1.221'A

lllPOLAR
·5.0 V
0.0 V
+S.OV -I LSB
9.76 mV
2.44 mV

OUTPUT
VOLTAGE(3)
when driving 50 n

UNIPOLAR
0.0 V
+5.0 V
+IO.OV.-I LSB

UNIPOLAR
0.00 mV
-1l6.07 mV
-(232.14 mV -I LSB)

9.76 mV
2.44 mV

0.227 mV
0.057 mV

(I) Sh()rt circuit current
(2) Op-Amp output when driving summing junction and using the internal R}i (see Figure I)
(3) See Figures 2 and 3.

INSTALLATION AND OPERATING INSTRUCTIONS
+15V
Optional
Gain Adjust

-...AJ'Ir-+-~IOkn

-15V
, - - - - - . Output
+15V

--4--""",-.c I Okn
TOP VIEW
Optional GAIN and OFFSET Adjustments

•

BIPOLAR OFFSET, pin 17, should be connected to' I
OUTPUT, pin IS, for bipolar operation or to POWER
COMMON, pin 22, for unipolar operation.

•

GAIN Adjustment Range: ±O.IS%ofFSR

•

Offset Adjustment Range: ±O.IS% of FSR

•

If the GAIN ADJUST is not used, leave pin 27 open_

•

REF OUT, pin 21 may be used to. provide a low drift
(5 ppm/DC) reference for external circuitry as long :as
less than ±IOO IJA. is drawn from it.

•

Internal 4.7 IlF bypass capacitors between the ±Is Vdc
power inputs and ground are included so that the DAC60
does not require external bypass capacitors.

Optional

Offset Adjust

-15V

• Both the DAC60'10 and DAC60-12 provide 12 digital
inputs. Digital inputs that are not used should be tied
to "I" (+5 volts). (Bits 11 and 12 on the DAC60-1O
should be tied to +5 V if not used.)

INTERNAL FEEDBACK RESISTOR
Burr-Brown includes a 2 kn feedback 'resistor in the high
speed resistor network (pin 18). The feedback resistor's
temperature coefficient of resistance (TCR) is matched with
that of the resist.or network. Since the. TCR of the resistor
network contributes much of the current output drift of
the DAC60, use of the feedback resistor with an external
op amp reduces the effective drift of the voltage output.
This is why the voltage output drift in the electrical
specifications table is significantly better than the current
output drift.

6-15

'OPTIONALOPERATING .GOIFIGURATIONS
DRIVING AN DP AMP SUMMING JUNCTION
The DAC60 will drive til.e summing junction of an op amp
(op amp b'eing used as a current to voltage converter) to
.
produce an output voltage:
VOUT =-(lour) (RF)
where lOUT is the .PAC60 shorf circuit output current and
RF is. the op amp feedback resistor. Use, of the internal
feedback resistor (pin 18) will result in a 0 to + 10 volt or
±5. volt Olltput range. A 16 kn feedback resistor would
produce output r~nges of 0 to +50 volts or ±25 volts.
Use of the internal 2 kn feedback resistor will result in
output voltage d!"iftsas indicated in the specification table
because theintemal' RF:drift is matched to that ~f the
current sources. When using external feedback resistors,
their temperature coefficient of resistance (TCR) should be
directly added to the current output drift of the· DAC60 to
obtain'the drift of the voltage output.

* Burr-Brown's 3400, 3401

and 3402 may also be used.

FIGURE'I. Driving an op amp summingjunctlon.

DRIVING A RESISTIVE LOAD

When driving a resistive load, the voltage output of the
DAC60 is the short circuit output current times the eqUivalent load resistance.' The DAC6Q output impedance is
approximately 650 ohms (in parallel with the load resistance,
Rr). The output voltage Is:

v .

our

=(1

our

)(RLX650n)·
RL + 650 n

With an RC of 100 kn or. higher, the full scale output
Voltage will' be' approximately .3.2 volts. An RL of 300
ohms will provide a full seale. output voltage of approximately I volt. ,.;
NOTE: For bipolai: use, the. OlltPUt voltage should be less
.than 700 mV fOi-acceptable output accuracy.

Power
Common

FIGURE 2. Driving a resistive load.

DRIVING A CABLE
The DAC60 can drive long hmgths of cable with a.circuit
as. shown in Figure 3. With just the 93 ohm terminating
resistor used, the full scale 0t\tput will be approximately
500 mY. The 120 ohm resistor across pins IS and 1.6 will
minimize output re-reflections dye to mismatches between
the characteristic impedance of the cable and the output
impedance of the DAC60. The reflection factor of a c.able

of

to is ,.the characteristic
impedance the
Zo+Zt
.
cable and Zt is the termination resistance. A 1% mismatch
between Zo and Zt will reflect back I % of the output voltage to the cable input where the termination' resistance
normally seen 'is the 650 ohm 'output impedance of the
DAC60. The reflection factor at the cable input would
then be .75 .. The 120 ohm resistor reduces this reflection
factor to 0.06 and significantly reduces glitches cauSed by

is Zo - It where

reflections. Of course the 120 ohm resistor will reduce the
full scale output voltage to about 250 mY.

FIGURE 3. Driving a cable.

6-16

APPLICATIONS
DEGLITCHED VOLTAGE OUTPUT
Output transients when SWitching from one state to
another are always a problem with high speed D/ A
converters. These transients, sometimes called glitches, are the result of unequal turn on and turn off
times of the digital and analog components. A
major contributor to glitch amplitude for the DAC
60 is the data skew of the digital inputs. Data
skew is the time difference between the time one
bit input changes state to the time other bit inputs
change state. With data skew of less than 2 nanoseconds the DAC60 glitch area will typically be
25 picoamp seconds.
If a high speed amplifier, such as BB Model 3550 is
used on the DAC60 output, a bridge clamping circuit on the summing junction will reduce the glitch
amplitude. The deglitching bridge and bridge driver
should be connected as shown in Figure 4. A high

·FIGURE 4: DegUtcher on DAC60 Output.
speed Schottky digital storage buffer should be used to reduce skew to
2 nanoseconds or less.
The deglitcher performance depends on the SWitching speed and'
of the bridge diodes. The bridge essentially clamps the .w.........oJ
near ground, preventing voltage glitches from appearing at the
output. This technique can essentially eliminate or significantly
glitch amplitudes to 5 LSB or less at the output.

5!1
~

c

WAVEFORM GENERATORS

CI

~--------------------------------------------~.

The DAC60 may be used asa high
speed, preCision signal generator with
the help of a programmable· read-only
memory.

DAC60

The counter updates the PROM addresses once each clock cycle. The
delay provides a strobe pulse for the
shift register when the PROM outputs
have settled to a new word. This circuitry may be programmed to provide
almost any complex, high speed waveform with up to 0.01% accuracy.

Vout

CRT DISPLAY CHARACTER G.ENERATOR

x Position

t
DAC60

Character J
Information 1
Y Position

i ---,.,

Character

t

A CRT display can be implemented
Information
using two DAC60's. The six most
significant bits (bit 1-6) are used to position the beam while
the less significant bits (bits 7-12) provide the character generation.

6-17

Ultra;;.High Speed
DIGITAL-TO-ANALOG CONVERTER
.,

FEATURES
.• 12-BIT RESOLUTION AND ACCURACY

• ADJUSTABLE LOGIC THRESHOLD FOR IDEAL
, SWITCHING

• 3Dnl8c SETTLING TIME (MAJOR CARRY)

• INTERNALLY-BYPASSED SUPPLY LINES TO
MINIMIZE SETTLING TIME

• ECL-COMPATIBLE INPUTS
• LOW GLITCH ENERGY

• INTERHALFEEDBACK RESISTOR FOR EXCELLENT
THERMAL TRACKING

• ±30ppm/o C MAX GAIN DRIFT
• LINEARITY ERROR LESS THAN ±1I2LSB OVER
SPEciFIED TEMP RANGE
.

• INDUSTRIAL AND MILITARY GRADES
• HIGH RELIABILITY SCREENING AVAILABLE

DESCRIPTION
The DAC63 is an ultra-fast-settling l2-bit current
output D/A converter in a 24-pin dual-in~line pack:
age. The inputs are ECL-compatible and the output
settles in 30nsec, typ (40nsec, max for C and T
grades) to within ±O.OI2% of Full Scale Range for
an MSB change. The DAC63 utilizes a monolithic
12-bit switch chip and a stable thin-film-on-sapphire
resistor network to achieve fast settling time and
excellent stabilit~ over temperature and time. Bec
cause of the close thermal tracking of the currentswitching transistors (all on one monolithic chip),
the possibility of thermal-tail settling time problems
are eliminated. An internal applications resistor for
~se with an exter~al output op amp is 'included to
convert the output current to insure excellent tracking and therefore lower drift. The linearity is guaranteed to be within ±1/2LSB over the specified temperature range of :-:25°C to +85°C for theCG, CM,
+125°C for SM
BG, and BM grades and .,...5S oC
and TM grades. Gllin drift 1s ±30ppm/oC max and
bipolar offset drift is ±10ppmoLFSR/oC max (high
grades). Also included internally.js Ii +6.2V refer."
ence: An output·voltage compliance range of +2.0V
to -O.5V allows the generation of an outjmtvoltage

. witholjt using an external output amplifier. The
device is available in both metal and ceramic bottombrazed ~a.~kages.
FUNCTIONAL DIAGRAM.

,Vee

i-"l_._. ._

DIGITAL
INPUTS

to

International Airport Industrial Park· P.O'.Box 114.00.:

Tucso~. Ariz~nl85734: 1el.l6021746·1I11 . Twx; 910-952·1 ill

6-18

-Vec

. LOGIC
THRESHOLD
SELECT
BIPOLAR
OFFSET
ECL
BIPOLAR
CURRENT.
OFFSET
SWITCHES .---r----IP lOUT
AND
RESISTOR
LADDER
RFEEDBACK
NETWORK
GND
GND
GND
GND
BND

: Cable: BBRCORP' Telex: 66·64!11

SPECIFICATIONS
ELECTRICAL
At "f-2S"C and rated supplies unless otherwise specified.
MOOEL

DAC63CG/CMITM

PARAMETER

MIN

TYP

DAC638G/IM/SM
MAX

MIN

TYP

MAX

UNITS

INPUT
DIGITAL INPUT
Resolution
~ogic Inputs")
Logic "1"; VOltage
Current
Logic "0": Voltage
Current
Logic Threshold: Voltage

-0.78
6.0
-1.62
-1.20

Eel-compatible
-0.90
-1.75
10.0
-1.33

Current

12

Bits

-0.96
33.0
·-1.85

V
pA
V
nA
V
rnA

-1.40
0.25

TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error
Differential Linearity Error
Gain Errorl21
Offset Errorl~lI: Unipolar
Bipolar
MonOlo.nicity Temp. Range (min)
CG. CM. BG. BM
TM.SM

±0.02
±0.01
±0.02
-25
-55

SETTLING TIME (Into lSOn)
lLSB Change
Settl·jng to :to.012% of FSA
CM/TM. BM/SM
CG.SG
Full Scale Change
Settling 10 ±l% of FSR
±O.l%ot FSR
±0.024% ot FSR
CM/TM. BM/SM
CG.BG
±0.012% ot FSR
CM/TM. BM. SM
CG.BG
Glitch Energy ,.,

%ofF$AISI
%01 FSR
%
%ot FSR
%ot FSR

±0.012
±O.012
±0.1
±0.D4
±O.l

·C
·C

+85
+125

30
30

40
40

40
35

17
30
55
35

20

65

65
40

50

±15
±0.3

nsec
nsec
nsec
nsec

75
55

80

70
40
250

DRIFT (over specified temp. range)
GaIn
Offset Unipolar
Bipolar
Linearity Error
(over speCified temp. range)
Differential Linearity Error
(over specified temp. range)

SO
45

nsec
nsec
nsec
nsec

lSB/nsec
±40
±1
±15

ppm/oC

±0.012

±O.025

%otFSR

±0.025

±O.O5

%ofFSR

±3O
±0.6
±10

±20
±O.S

pprn/'C
ppm/DC

OUTPUT
ANALOG OUTPUT
Output Current
Output Voltage Ranges
with External Op Amp
witi"tout External Op Amp'5,
Output Impedance withOut
External Op Amp
Unipolar:. POSitive
.. Nega[ive
Bipolar
Campllanc'e Voltage

a to -10, ±5

rnA

o to +10. ±5
o to "1""1.5, ±O.5

V
V

150
200
170

0

·cO.5

n
n
V

+2.0

POWER SUPPLIES AND REFERENCE
Internal Reference Voltage
Internal Refer~{1ce Drift
Power Supply Voltages
Pow:er Supply Current: -t-15V
-15V
Power Supply Sensitivity: -15V
-15V
Power Dissipation

+6.2
='3

:±1.5
±15
26
38
:to.OO35

±O.OOO4
960

V

ppm/oC
±18
31
46

"60·

6-19

\

V
rnA
rnA
'IoI%AV
'IoI%AV
rnW

ELECTRICAL (CONT)
MODEL

DAC83CG/CMITM

PA~~TER

"

PHYSICAL CtWlACTERISTICS
TEMPlRATURE RANGE' ,
~pecilication: CG. CM. BG. BM
TM.SM
Storage

DAC83BGlBMlSM

TVP

MIN

MAX

r

MIN

TVP

MAX

,

,
-25
-55

UNITS

~C'

+85
+125
+150

-65

PACKAGE
CG.BG
CM. TM. BM. SM

·C
'·C

24'-pin DIP bottom-brazed ceramic
24'-pin DIP metal

·Specillcation same as lor DAC63CG/CMITM,
NOTES: (1) Logit Input voltages and currents are dependent on the logic threShold voltage. The logic input val~es given in each column are correct for the logic
thrf'Shold voltage given in that column. ,(2) When used with an external output op amp or when the internal impedancea!resistors are used as 'the load. (3) FSR is
Full Scale Range. which is 10mA for both the DAC63BG and DAC83CG. (4) Reier to Output Glitch section. (5) ReIer to Figures ,8, and 9.

MECHANICAL

,...

.

A

\

IL~D
W

~"i'

r'

Im~.IGl..I~
~-r ~ M~~ IJ4
--I

1l.

LEAilNGPLANE

INCHES

DIM

A

•

MIN

MAX

1.'10 1 •• ,0
.7.0 •• 00

.11.

C

•207

MILLIMETERS·

MIN

.....

11."

10.81
1 .• 1

K
L

.001 .ou
.••
.200 .210 1.01
.100 IAIIC 11.14 I

.0'

N

.oa.

.8.

NOTES
WIT~IN 010'
(25MMl A@MMC AT SEATING PLANE

1 LEADS IN TRUE:. POSITION

.

e

.
L1
,
"
. ...........
H

.'1.
.170

.....

tMfTE"S
MAX

..."

.• OO ..... IC
,000

20.'7

..

,

7·.2
1S.2e'A'le

'-'.

0

•

.......... .';

~

INCHES
MAX

.01'
.100.AlIC

f=-,

i-:-:i
III i11i i
G~E

I
'01

at.11 aa.17

2.1" IAIIC
2.21 1 •• '

~

~L

MAX

.s.
r-+- • ..0"• •
1.14 1.40
r-f-

f...!!J

I

ce!!t

.

DIM

Pi" n.\4mCIII" ..nOW" lor r.I~'"c.
,"iIIV not 1M ...... ~.., on p.ck,VI.

O"IV

NOTE'

I._I'" !r.... po.ition "'''thIn .010"
1.25"''''1 JII • MMC It
pl.nl.

_t,",

•. aa
.11

PIN ASSIGNMENTS
PinNa.
1
2
3
4
5
6
7

8

9
10
11
'12
13
14
15
16
17
18
19
20
,21
22
23
24

DISCUSSION OF
SPECIFICATIONS

Function
BilllMSB,
Bit 2
Bit 3
Bil4
Bil5
Bil6
Bit 7
Bil8
Bit 9
Bill0
Bill1
Bil121LSB,
GND
GND
GND
GND
GND
Feedback Resistor cOnneclion
Current Oulput
Bipolar Offset
BipQlar Offset
Logic Threshold
+15VDC
-15VDC

ACCURACY
Linearity of aD/ P,. converter is one of the true measures
of ~ts performance. The linearity error of the DAC63 is
specified over its entire temperatur~. range. The analog
output'will not vary by more than ±1/2LSB from an
ideal straight line drawn between the end points (inputs
all "I"s and all "O"s) over the specified temperature
range.
Differential linearity error of aD/ A' converter is the
deviation from an ideal ILSB vol~age change from one
adjacent output state to the next. A differential linearity
.error specification of ±1/2LSB means that .the output
voltage step sizes can range from 1/2LSB to 3/2LSB
when the input changes from one adjaceilt inplit state to
the next.

6-20

Monotonicity over the specified temperature range is
guaranteed to insure that the analog output will increase
or remain the same for increasing input digital codes.
DRIFT

Gain Drift is a measure of the chang~ in the full scale
range output over temperature expressed in parts per
million per °c (ppm/°C). Gain drift is established by: I)
testing the end point differences for the DAC63 at tm;n,
+25°C, and ·tmax; 2) calculating the gain error with
respect to the +25°C value and; 3) dividing by the
temperature change. This figure is expressed in ppm/DC
and is given in the electrical specifications (includes
internal re~~rence).
Offset Drift is a measure of the actual change in output
.around zero over the specified temperature range. The
offset is measured at tm;n, +25°C, and tm... The maximum
change in Offset is referenced to the Offset at+25°C and
is divided by the temperature. range. This drift is expressed in parts per million of full scale range per °C
(ppm of FSR/oq.

DIGITAL INTERFACE, LOGIC THRESHOLD,
AND NOISE IMMUNITY

The DAC63 is compatibl~ with convention~ ECL logic
families such as ECL 10,000. The circuit diagram shows
that the equivalent circuit of each DAC63 digital input is
the base of one side of a differential amplifier. The logic I
input voltage is -0.85V with a typical input current of
8j.tA. The logic 0 input voltage is -1.75V with an input
current of less than 8nA.
'
The Logic Threshold funGtion of the DAC63 is very
important in dealing with noise in the ECL input-u,?-d. plane to connect common ground
points.
.
'3. Remove"the ground, plane, frQm underneath Signal
lines where.it would add capa~it~nce .
4. Separate analog and digital signal'leads to avoid coupling oCthe digital signal into the analog paths.
5. Bring the source of the digital driving signal as close
to the inputs of the DAC63 as possible. If the digital
inputs are not· clean it will be necessary to reshape
them using registers or line drivers. Figure 6 shows
how to interface the DAC63 to an input register. It is
recommended that the logic power line be bypassed
near' the digital logic cireuitry as a further measure to
achieve clean signals.
6. If possible, the DAC63 should be solde,red directly
into the printed circuit board since connector lead
length will cause ringing, in the output.
OUTPUT GLITCH
"Glitch" is defined as the difference in the waveforms at
the output of the DA~ if there is data skew and if there is
not, The measurement o(glitch is accomplished by
measuring the area between these two waveforms.
An output glitch of less than 250LSB-nsec is achievable
with the DAC63 because 'it einploys ECL Circuitry with
current switches that have virtually identical delay times
for logic signals making either positive or negative transitions. A glitch results when the digital data changes
from one code to the next and the bits do not all switch
at the same time. The delay time between the earliest and
latest switching bits is called skew time. Typicillly during
the skew time of the digital data, which includes the
DAC switching, the digital code is undefined and the,
DAC output can go to any voltage between the full scale
extremes. The glitch creates a noisy output which can be
troublesome in some' applications such as precision displays and compJe'x waveform generation. Figure 5 is a '
photograph of a scope trace of the, DAC output with a
glitch occurring at the inajor carry transition.
The DAC63 design has been optimized for low glitch
energy. However, it further reduction in the output 'glitch
can be achievedby adjusting the skew of ththigher order
bits of the driving circuitry and by adjusting 'the logic
threshold. This cail' be done by connecting a variable
capacitor from the data lines to ground on each of the
.. first three significant bits (more than. three lines inay be
,adjusted if desired). Refer to Figure 6. It will be, neces, sary to create a driving digital code pattern' that .causes a
, major carry transition around these bits. It..is convenient
to use a digital ramp from a counter for, this purpose.
Initially set the logic threilhold exactly half-way between
logic 1 and a iogic O. This will be about ":'L3V. then

.6-22

OUTPUT CONFIGURATIONS
AND APPLICATIONS
INFORMATION
The DAC63 contains two 1.24kO resistors for generating
the bipolar offset current and a IkO resistor which is
primarily used as the feedback resistor when used with
an external op amp. This' thin-film network is constructed on sapphire to provide excellent temperature
tracking capability inherent in thin-film networks. These
internal resistors along with other internal resistors
cause the DAC63 output, in any mode, to be a ratiometric product of the reference; The feedback resistor has
very low power sensitivity so that linearity is maintained
independent of digital code changes. Because this resistor is constructed on a sapphire network, it is possible to
have both superior tracking and low capacitance. Figure
7 shows the DAC63 connected to an external op amp in
unipolar and bipolar modes. With the Burr-Brown model
OPA600 it is possible to achieve settling times to ±O.OI%
accuracy in l50nsec. Many of the output accuracy and
linearity specifications are given when connected to an fa
external op amp.
~
For highest speed operation, the DAC63 should be used CI
without an external op amp. Figures 8 and 9 show how
to connect the DAC63 for bipolar and positive unipolar

FIGURE 5. Typical Glitch Repsonse of DAC63 at
Major Carry Transition with a 1.6V Full
Scale Range.,
examine the major carry transition associated with bit 3
and adjust the capacitor for minimum glitch. Make the
same adjustment to bit 2 and then to bit I. If done in this
order, interactions will be minimized. Finally, fine tune
the response by adjusting the logic threshold voltage (pin
22) for minimum glitch. It may be necessary to repeat
this procedure once or twice for complete optimization.

r-5.2V .
(MSBIBITIBIT281T3BIT481T581T6-

-

BIT7BIT8BIT 9BIT 10BIT 11- ILS8)8IT 12- rDATA STROBE

MCI0178

CI

I

?"

?~

I
81T IIMS8l
2
BIT2
3
BIT3
BI14
BITS
BIT 8

C2

C*

-=-

CLOCK

IiJ

OAC83

7
81T7
B 81T8
9
BIT 9
10
81T 10
II
81T II
12
BIT 12

MCIOI16

-5.2V

CLOCK

~

330n
lOOn

MCI0118

!-5.2V
NOTES:
I. Pull-ilown r8liliOrt Ire all 51 On,
2. CI• C2' C3 adlualed between 0 and 50pF lor minimum glllCh.
3. Power and ground connecllons are no! shown.

200n

iaL
-5.ZV

FIGURE 6. DAC63 Interface to Input Latches Including Glitch-Adjust Circuitry.

6.-23

lOOn

330n

LOGIC THRESHOLD

22

I~F

:::r:+
.... TANTALUM

Fi~re 10 jlh,ISfrateS h9w to' cO!lnectthe
DAC63toconstr~ct afast,~/D con:-erter,~ Tb~ ADC

operatiQn,;

attempts to create

'a

null a(the DAC 'In 2U ,
Connection

+15V

.",

..

'

"P,OOQQV

"'5,OoOOY

" :',5,0000Y
,0,OoOOv '

9 99?SY

ill,99l6V, ,

14711

, "C;On'hect

',open,

to Pin 19

OFFSET ADJUST

~100kll
'15V~

OAC63

110 Relationships with

FIGURE 7. Bipolar and Unipolar Output Connections when Used with Externa,l Op Amp.

20

1.24kll

.~~2V

rt9

l!

1.5Mn

OFFSET
ADJUST
l00kn

1.24kn

~212V

CD

~

200n

010 IOniA

""='='

17

-15V

-+

19
lkn

300n

L:

r/.I

1,24kn

VOUT
Ikll

OfFSET ADJUST

20

+15V

(~I:A

GAIN
ADJUST
500n

200n

18

r

,.!7 L
,

.

+
J-,

5DOn

"2

R5

'"

16

DAC63

\

~4

13

15

!

1/0 Relationships for Voltage Output
Configuration without External Op Amp

14
DAC83

-15V

GAIN ADJUST VDUT

16

,-:,;:-

.'~!

-=-

Output Vo~lage

13

-::::.,?-

I)'glta
Input Code

Positive
Unipolar

000000000000
011111111111
111111111111

O.OOOOV
'0,7500V
1,4996V

Bipolar
-0,500V
O,OOOV
O:SOOV

..

, FIGURE 8. Bipolar Voltage Output Without External
OpAmp.
'

FIGURE 9. POSitive Umpolar Voltage Output
External Op Amp.
'

6-24

Wltho~t

I#F
TANTALUM
+ -=-¥ H
~

+

4
23
22

BIT I

I~F

TANTALUM
Ikll

=¥ I.F TANTALUM

4.12kll

-=-

* I

I
I

....
=
........

..

=

I

....

I

·15V
19

5

I

~
~

8

I
I
BIT 12

12·BIT .
LADDER
RESISTOR
NETWORK
AND
CURRENT
SWITCHES

Ikn
18
17

9

16

10

15

11

14

12

13

+5V

ANALOG
INPUT

-=

=
'"c:
C")

Ikn
Ikn
·15V

2.74kn

"T
Ikll

Ikn

=

BIT I

;

I
I

1
1
1

2504 SAR

BIT 12

2.74kn

CLOCK

·15V

FIGURE 10. DAC63 Used in a Fast AID Converter.

6-25

"DAC63 Bits 2 through 11 are also connected
10 &AR InpUII 81t 2lhrlllDh Bit II ruplCllVlly.

BURR.BROWN~ .

DAC70

I~E:JI.

High .Resolution
DIGITAL-TO-ANALOG CONVERTER
FEATURES
PROVIDES ACCURATE ANALOG SIGNALS
EXCELLENT FOR CALIBRATION STANDARD AND
HIGH RESOLUTION APPLICATIONS

SMALL SIZE.SAVES SPACE AND WEIGHT

Hermetic Dual-in-iine Package
Low Cost

IS-bit resolution
Laser-trimmed to tiI.OO3% maximum nonlinearity
Ultra-low drift, :t.4ppm/oC. max

DESCRIPTION

FUNCTIONAL DIAGRAM

The DAC70 is a high quality 16-bit hybrid IC D/A
converter in a 24-pin DIP-compatible hermet.ic metal
package. Constructed with laser-trimmed and driftmatched thin-film resistor riet~orkand fast-settling
bipolar IC current switches, the DAC70 settles in
50~sec to a maximum nonlinearity of±o.003% offull
scaie range (FSR) and has a very low maximum gain
drift of ±4ppm/"C .over 15"C to 50°C. Three basic
models accept complementary unipolar or bipolar
16-bit binary or complementary 4-digit BCD TTL. compatible input codes. Each model is available in
two grades of drift, linearity and operating
temperature range. The Model DAC 70 (-25"C to
+85"C) offers ±0.003% of FSR maximum
nonlin~arity and ±7ppmj"C maximum· gain drift.
The Model DAC70C (OUC to + 70"C) offers ±o.OO5%
of FSR maximum nonlinearity and ±14ppnlj"C
maximum gain drift.
These units provide output current signals of±lmA
or 0 to -2mA, and contain the scaling resistors for
connecting an external amplifier to provide 0 to
+IOV (CSB, CCD) or ±IOV (COB) output voltage
ranges. Input ,Power is ±15VDC and +5VDC.
Excellent stability, long life and quality product
performance is assured because· each DAC70 is
·burned-in for 96 hours at + 100°C. Calibration
equipment used to test the DAC70 is traceable to the
National Bureau of Standards.

Inllmllianal AlrpDrt Industrial Park· P.O. Box 11400· Tul:lOll. Arimo 85734· Tel. (Il02l i4fi.1111 • Twx: 91~·111\ . Cable: BBRCORp· Tellx: 1f6.6491

6-26

$PECIFICATIONS
MECHANICAL

iA=J

ELECTRICAL
(Typical at lSoC with rated power supplies unless otherwise noted.)

MODEL
INPUT
DIGITAlllilPUTS
Data Input Codes
Logi<: Levels (I)
Logic "I"
Logic "0"

I

DAC70

I

DAC70C

I

L[~l
b

UNITS

TTL Compalible
Complementary: 16 bil BinaryI
4digil BCD
+2.4 < c, < S.S at 4O"A Source
o< C4 < +0.4 max. at 1.6mA sink

D,no'".;n'

V
V

TRANSFER CHARACTERISTICS
AcCURACY (25°C)
Linearity Error (max)
Gain Error. (max)(3)
Offset Error I (max)(3)
Monotonicity Guaranteed (lOoC to 40 0 q

DRIFT(O)
Gain (max) (DoC to +70o C)
(max) (_25°C to +8S o C)
(max) (+1SoC to SO°C)
Offset
Unipolar

Bipolar (max)
Linearity (max)

SETTlIlIIG TIME (4)
(10 O.OOJ% FSR)
Voltqc OutputCS) (max) 20 V step
.6 mV step
Current Output
2 mA step
Output Switching Transient
Slew Rate

:1:0.003

tol..

±O.OOS

±O.O5

10

13

--to
t2

-t8

r

OUTPUT

tolD

, 2

J,oIsec
osee
",ec
mV
V/JJSec

100
50
50
500
I

IIilTERNAl REFEREILICE VOLTAGE (V,)
Maximum External CUrRnt(7)

TEMPERATURE RANGE
Specification
Operating (Double above drift specs)
Storage

,

'2

2'

'3

.00000 ••••••

.016
.021
.100 BASIC
.150
.125
.150 I .300
.6008ASIC
.110
.080

I

H
ppm of FSR/%
ppm of FSR/%

K

14
!I

ppm ofFSR/%
ppm of FSR/%

R

L

ppm/%
ppm/%

tlO

"
Oto+lO
tiD
5
0.05
0.003

V
V
mA
Il
\'bF8R

Oto -2

mA
mA
V

tI

±2.5

kll
kll
V

4.4

15
6.3
200

oA

U5 and +5
t14.5 to ±IS.5 &. +4.75 to +5.25.

V
V

JO
25

mA
mA

I

°c
°c
°c

-25 to +85
o to +70
-25 to +85
-55 to +100
-55 to +125

(I) It is recommended that the digital input lines to tbe DAC70 be drawn from TTL devices (inverten
or tegisten) that drive only the DAC to obtain the specif"led accuracy.
(2) FSR means full idle'range and is 20V for flOV range, lOY for 0 to +10V range, etc.
(3) Gain and offaet are externally adjustable to zero (see l'igures 4 and S).
(4) Worse case con~itions measured a~ the worst case major carry (mid-scale).
(5) With external Burr·Brown Model 3S00C op amp or equivalent, using internal feedback resistors.
(6) The cunont output should be connected to th;e Yirtual ,round of an amplifier summing junction to.
obtain specified accuracy.
(7) With no desredation of specifications.

1.385
.810
.250

.790
.170

0

to.1

INCHES
MIN
MAX
1.365

A
8
C

"

POWER SUPPl Y REQUIREMENTS
Rated Voltage
Ran..
Supply Orain
t 1 5 V (including 5 rnA load)
+5 V

Ol¥

G

ANALOG OUTPUT
Voltage Mode(5)
esa and eeD Models
COB Model
Output Current (min)
Output Impedance (DC)
RMS Noise (10 Hzto 10 kHz)
Current Mode
eSB and CCD Models
eOBModel
Compliance(b)
Output Impedance (OC)
Bipolar
Unipolar

1I'lIiit

000000000000

ppm of FSRjUC
ppm of FSR/oC
ppm of FSR/oC

POWER SUPPl Y SENSITIVITY
Unipolar Offset
±IS V
+5 V
Bipolar Offset
:1:15 V
+5 V
Gain
HSV
+5 V

r;;-

ppm/DC
ppmr'C
ppm/DC

"4

t7
.4

fL:1~H
j I!!

%0' FSR(2)
%
%of FSR
bits

I

MILLIMETERS
MIN
MAX
34.67

35.18

20.07
20.57
4.32
6.35
0.41
0.53
2.548ASIC
3.81
3.18
3.81 I 7.62
15.248ASIC
2.79
2.03

I

I

CASE: .Kovar
Mating Connector 24SMC.
PIN: Pin material and plating composition
conform to method 2003 (solderabiltiy)
of Mil-Std-S83 (except paragraph 3.2).
WEIGHT: 9 grams (.32 oz)

CONNECTION DIAGRAM
(MSB) G:
b +6.3 V
Bit I I
Bit 3

G.:
G:

Bi14

@:

Bit 5

G:

Bit 6

C1:

B;t 2

Bit.S

G::


.1

0

.08
.06
.04

~

.02

0::&
C

06
~"li

+s"v Supply":

:8Aa

/

II)

u.

~

K::

"0

.01

~

~

.006
.004

/'
10

t

w

//

.,/
1

+15V Supply

. / 1/

./

.002
".001

U
0::

/

'-/

- <
w·U. m

;;

-15V Supply

II)

II)

0.1

<

~

./

100

.0010"1:.1---~~---"":":~-_....a~
10k

Ik

Settling Time fl'Sec)

lOOk

Power Supply Ripple Frequencv (Hz)

FIGURE Z. Power supply rejection vs. power supply ripple frequency.

FIGURE 3. Full scale range settling time vs. accuracy.

/...1-

+ Full Scale

'"/

~/" ~T

/'.//

~

~/"

~

~:''''

~

1
rn

~

R

f"

Z:~~:j.l

Offset Adj.
Translates
the line

~

All bits

OFF

/

f{ang~ of

"

Gain Adj.

/.;4~~

~~

~ -,

~

Gain Adj.
rotates
the line

All bils
ON

I

~..

w=..+-+-I--l-+--+f~""'+-+-+-+-I
Digital Input

FIGURE 4. Relationship of OFFSET and GAIN adjustments
for a UNIPOLAR O/A converter.

FIGURE 5. Relationship of OFFSET and GAIN adjustments
for a 81PO LAR 0/A converter.
UTPUT

0

VOLTAGE

DIGITAL INPUT CODE

URRENT

1681t RnoJution 1A Bit R-.olutlon 16 Bit RMDlution 4 8it RlIaOlution

DIGITAL INPUT
AND ANALOG
OUTPUT
RELATIONSHIPS

Complement.,y Unlpol.,.
Stra.lght Binary (CSS)
Oto +10Vor-Oto.-2mA
One LSS
All Bits ott
All Bits on

+16311V
+9.99986V

+6101AV
+9.99939

O.031mA
-1.99997mA
zero

O.122p'A
-1.99988mA
Zero

Qne LSB
All Bluoff
AIISltlOn'

+306j",V
+9.99969V
-10.000DV

+l.22mV
+9.98878V
-10.0000V

D.031101-A
-D.99997mA
+1.0000mA

0.122101-A
-O.99988mA
+l.0000mA

ComPlementary Binary
Coded Decimal (ceDI
Ota +10V or 0 to -1.2SmA
ane LSB
F.S. Bits off
All Bits on

4 Digit
Resolution

20,.

20,.

Complementary Bipolar
OffMt BirI.,y (COB)
tl0Vor UmA

+l.OmV
+9.999V

401glt
R8IOIutCon
N/A

z...o

TABLE II. Ideal output voltage and current.

6-29

.O.126",A
-1.249S7mA

z.'"

N/A

OPERATIN'GAND INSTALLATION INSTRUCTIONS
Figure 6. The lead and CQntact resistance,Zi' is reduced by
the loop gain to al;:ceptablevalues.

.INSTALLATION CONSIDERATIONS
The DAC70 is laser trimmed to 14 b.it linearity. The design
of the device makes the 16 bit resolution available on binary
units. If 16 bit resolution is not required, bit 15 (pin 15) and .
bit 16 (pin 16) should be connected to +5 V through a single
I k n resistor.

The DAC70 and the wiring to its Clinnector should be located
so as to provide optimum isolation from sOurces Of RFI and
EMI. The key word in elimination of RF radiation or pickup is loop area. Therefore, signal leads and their return conductors should be kept close together. This reduces the
external magnetic field aloilgwith any radiation. Also, if a
signal lead and its return conductor are wired close together
they present a small flux-capture cross section for any external field. This reduces radiation pick-up in the circuit.
··The metal case of the unit is internally connected to the common pin to further minimize pick-up. The DAC70 case is
made of gold. plated Kovar which also provides some electromagnetic shielding.

Due to the extremely high resolution and linearity of the
DAC70, system design problems such as grounding and contact resistance become~ery important. For a 16 ~it converter
with a +10 volt full scale range, one LSB is 15~~V. With a
load current of 5 mA and series wiring and connector resistance of only 30 mn, the output will be in error by I LSB.
To understand what this means in terms of a system layout,
the impedance of #18 wire is about 0.064 nlft. Neglecting contact resistance, less than 6 inches of wire will produce
a I LSB e{ror in the analog output yoltage! Although the
problems involved seem enormous, care in the installation
planning·can minimize the potential causes of error.

NOTE:

It is recommended that the digital input lines of the OAC10 be driven
from inverters of TTL input registers to obtain specified accurecy.

The output can be made essentially independent of lead resistance by sensing the output at the load itself as shown in

"-

OAC70
6.3k
+ (COB
only)

~~

IOkSl (COB)
5kSl (CSB)

".A

~

. 1

~ut

8kSl (CCD)

15kSl
< p /2mA
o

L21

~

20

)

.A

'AI

~+

Common

/

T

Feedback Current
(I "dependent of Loed I

RB

..

i!2

..... BB3500C
or equiv.

,.." . ~",)

,
~~ RLoad
~

i!3

Bias Current

To Pin 23

To Pin 19

To Pin 18

+V

l' JaF: :+

COM

1 "F:

:'t-

-V

i "F:I

t

,

+V
COM

(NegIi9ib~

i!4
±16V
Supply

+5V
Supply

*RB should be equal to the output
impedance at Pin 21 to compensate
for the bias current drift of A 1• Use
standard 10%, 118 in carbon composition or equivale~t "resistors.
RB ~.3k (COB) ... 10k II 15k II 6.3k·
RB = 3.9k (eSSI .. 5k II 15k
RS a 5.1k (eCO) .. 8k II 15k

FIGURE 6. Output CIR~UlT for making LOAD VOLTAGE essentially independent of LEAD RESISTANCE.

SUPPLYOECOUPLING
For best performance and noise rejection, power supply decoupling capacitors should be connected as
shown in Figure 6. These capacitors should be located close to the DAC70.

6-30

EXTERNAL OFFSET AND GAIN ADJ.
Offset and gain may be trimmed by the user with externally
connected offset and gain potentiometers. Connection of
these potentiometers and the method of adjustment is out·
lined below. In each case a simplified schematic of the DAC
70 as seen from the adjustment point is given to assist the
user in designing his own adjustment networks. Adjust offset first and then gain to avoid interaction (see Figures 4 and 5).

GAIN ADJUSTMENT
For either unipolar (CSB, CCD) or bipolar (COB) models,
apply the digital input that should give the maximum posi·
tive current or voltage output. Adjust the gain potentiometer for this full scale value. The positive full scale voltage
and currents for the DAC70 are given in Table II.

,----------I

I

Output

I

6.3V

OFFSET ADJUSTMENT
For unipolar (CS8, CCD) D/A converters, apply the digital
input code that should give zero volts output and adjust the
offset potentiometer for zero volts output. For bipolar
(COB) D/ A converters, apply the digital input code that
should give minus full scale (-:-10 volts) and adjust the offset
potentiometer for an output voltage of -10 volts. Two methods of offset adjustment are shown in Figures 7 & 8.

24

+15VDC

R

* lOkn to

l00kn ~'-~51~O~kvn---2~2a-~~·

+15VDC

r-____~3~.9~M~n~~~Oknw

..,5V

I

Reference

-15VDC

DAC70

-

L- _ _ _ _

.

FIGURE 9. Gain adjustment circuit.

100kn

Figure 9 shows how the gain adjust works on the DAC70.
The gain of the DAC70 is determined by the reference current
Iref. Due to the high gain and low bias current of A I, the
voltage at the positive input of A I is approximately equal
to the voltage at the gain adjust pin VG. Therefore, the reference, current is
. 6 3V _V
IREF= .
G
.
SOk
Since VG is approximately equal to zero initially, a simple
formula for determining the voltage range necessary at the
gain adjust pin for a given percentage change in gain is
FIGURE 7. Offset adjustment, DAC70-CSB-I with
external op amp.
In some applications the use of such a large offset adjustment
resistor might be undesirable. An alternative method of offset adjustment is shown in Figure 8:

db

~VG = % Gai~ hange x 6.3 volts
The full scale output voltage of the DAC70 with an external
output amplifier and internal feedback resistor is laser trimmed to less than ±O.OS% of FSR.

REFERENCE SUPPLY

·10kn
+15VDC

-15VDC

6.2kn

All DAC70 and DAC70C models are supplied with an internal +6.3V reference voltage supply. This reference voltage
(pin 24) has a tolerance of ±S% and is connected internally
for specified operation.· The zener is selected for a gain drift
of typically ±3 ppm/oC and is burned in for a total of 160
hours for guaranteed reliability.
This reference may also be used externally but the current
drain is limited to 200 J.l.A. An external buffer amplifier is
recommended if the DAC70 internal reference will be used
externally in order to supply a constant load to the reference
supply output.

FIGURE 8. Alternative method of offset adjustment for
. DAC70-CSB-I with external op amp.

NOTE: An external reference cannot be used. The DAC70
internal reference must be used.

* High quality multi-turn (10 turns if possible) potentiometers with less than lOOppm/oC, T.C.R. should be used.
6-31

APPUCATION:$' .'
DRIVING AN EXTERNAL OP AMP
The DAC7(l'is a curre~t ou'tput device and wiJl drive the summing jUnction of a~ op amp to produce an outputvoltage
(see Figure,tO). The op amp ou'tput voltage'is:' '

The DAC70 can be scliled for any desired voltage range with
an external feedback resistor; bUlat the expense (}f ,increased
drifts 'Of up· to±2S ppm/oC. :Theresistors in'the DAC70 are
chosen: far ratio traCking of· ± I ppm/oC and not absolute
T.C.R. (which may be as high as ±2S ppm/Qr).

'Ii out:' -lout Rf
Where 10llt is the PAC70Qutput current a~d Rf is the feed·
back resistor/Use of the internal feedback .resistor (pin 17)
is required itQ Jobtain, specified gain accuracy and low gain
drift.

An alternative method of scaling the output voltage of the
DAC70 and preserving the low gain drift is shown in Figri~e
II. ".
'
,

5kn

Oto

15kn

2mA

FIGURE 10., External op amp

u~ing

internal feedback resistors.
.

~~.

Vout

15kn

FIGURE

ll. External OIl amp using internal and external feedback resistors io maintain low gain drift.

OUTPUTS LARGER THAN 20VOL T RANGE
For output voltage ranges larger than±lO volts, a high voltage op amp may be employed with an extermil feedback
resistor. Uile lout values of ±l' rnA for bipolar voltage
ranges and;'2 rnA for unipolar voltage ranges(see,Figure 12).
Use protection diodes when a high voltage op amp is used.

FIGURE 12. Exteil\al ~p amp using exter~~feedback
resistors.

6-32

ORDER INFORMATION
DAC70 X
XXX - X
.Output
L~L~~I-__""':~~":;::::~~-"" I =Current Output
16 Bit DtA
Convert8r Family
Blank = -250C to +850C
C = 00 to + 700C

Complementary Striight Binary
COB =16 Bit
Complementary Offset Binary
CCD = 4 digit Complementary BCD

6-33

'BURR-BROWN@

DAC71

IElElI'

"'High Resolution
16-BIT DIGITAL-TO-ANALOG CONVE.RTER
FEATURES

DESCRIPTION

• 16-BIT. 4-DlGlT RESOLUTION

The OAC71 is a high quality 16-bit hybrid IC 0/ A
converter available in a 24-pin dual-in-line ceramic
package,

• ±D.003% MAXIMUM NONLINEARITY
• LOW DRIFT±7ppm/"C. (TYPICAL)
• CURRENT AND VOLTAGE MODELS
• LOW COST

The OAC71 with ,internal reference and optional
output amplifier offers a maximum linearity error of
±O,003o/c- of FSR at room temperature and a
maximum gain drift of ±20ppm/oC over a temperature range ofO°C to +70°C.
Three basic models accept complementary 16-bit
binary or complementary 4-digit BCO TTL-.
compatible input codes,

VOLTAGE MaDEL
6.3V REF, OUT
+15VDC
GAIN ADJUST
SUMMING JUNCTION

Packaged within the OAC71 are fast-settling switches
and stable laser-trimmed thin-film resistors that let
you select output voltages 0 to + IOV (CSB and CCO)
or±IOV (COB)and output currents ol:tl rnA orO to
-2mA. Input power is ±15VOC and +5VOC.

COMMON
,15VDC
+5VDC
V OUT

L..._ _ _ _ _ _, , - }

1.~r l

Internationll Alrporllnduslrial Park, P,O, Box 114011· Tucson, Arizona 85734 . T81.(602) 746-1111 . Twx: 910-952·1111 . Cable: BBRCORp· Telex: 66-6491'

·6,.34

SPECIFICATIONS
ELECTRICAL

TypiNI"TA~2S"C

-

_ _ _ ouppIleo ..._ _ _

IIOIIIL
~

IIIQIT"~

"-ulian. CCD
CSB.COB
Logic LeveIo ,TTl-Com.,.,ible,(1)
Logical .. ,,, tat +4OpA I
Logic:III·'O· '"t-I.8mA,

D&e7,
.,.,..

IIAII

4
16

UNITI

Bi,.
+5.5
+0.4

VDC
VDC

:to.OO5

-'ofFSRc21"
'IIooIFSR

TUIIINIII~'
li.-Hy Error .. 2S"C. CCD

COS.cse

:to.OO3
±O.l
:to.25
±2
±5
±I
±5
+50

±0.01
:to.OS
±O.l

0

±15

±7
:t15

±5O
:to.083
:to.071
:to.23
:to.23
±20

±to

a-

VoI,-. Unipollr
llipolo, .'
Current. Unipollr
BipoII,
Di_lalll_riIy ...... Temperlture
lI_ty Error ...., T!I'"peroture

±I

±2
±10

±I
±40
±2
±2

IITTUIIII""

V,,"- _ . ,10 :to.Q031Io·ol FSR·
Output: 'lIN SlOp
ILSBSIep(II
Slew ReIO
Current_. ,to :to._ 01 FSR
Output: 2mA IIOp lOll to 10011 LOid
IklilOid
Switching Tran"'"

10
5

5
3
20

I
3

'110
'110

mV
mV
_A
_A
·C

NOTE: Leads
in true position.
within 0.10"

O.2Smm A at
MMCat
seating plane

-,....
u

&:I

ppm 01 FSI\JOC
ppm 01 FSAI'IC
ppm 01 FSIIJOC
ppm 01 FSIIJOC
ppmofFSI\I"C
ppm 01 FSI\I"C

----_--

VI __

DIM
A

B
r

N

010+10
±10

V
V

O.OS

mA
II

I

Indefinite to Common

Short Circuit Duration

Current_.
Re_ - CSB. ceo
COB
Outpullmpodlnce - Unipola,
Bipola,

010-2
±I
15
4.4
±2.5

Compliance

mA
mA

kll
kll .

V
6.6

V

MIIximum Extern., Currenl(1)

±200

T....,."..ure CoefIicienl 01 D,ill

±10

_A
PPml"C

8.0

6.3

6-35

INCHES
MIN
M""
1.310
.770
.150
.018.

Mlll..lMETEAS
MIN"
MAX

1.360

·,33.27

34.54

.810
.210

19.56
3.81

.02'

~O:46

20.57
5.33
·0.53

....

.035
.100BA.SIC

. I:.

±5

,Pin numbers--_J
shown for
reference only.
Numbers may
nol be marked
on ·package

'IIooIFSR
'110 01 FSR
110 01 FSR
'IIooIFSR
ppml"C
ppml"C

MALOQ 0U1'NI'

....-a._VOLT_

lj=-1£":ji

mV

500

'3

ppm 01 FSIIJOC
ppm 01 FSRJOC

0U1'NI'
V,,"-_
Re_ - cse. CCD
COB
0uIpu' Current
Outpul Impodlnce , DC

1>'

B

..

+U
0

a-

.

Digiti

ACCUUCY
G1in Error.l31 V,,"C_I
Error.131 V,,"-. UnipoIa,
VOIIIge. Bipoll,
Current. Uni~l.r
Currenl.lIiJJoi.,
Mo_icily Tem_ura Renge .14 big·
- , - ,_opociliod IOmp. ,"nge.
Total Bipollr Drill' incl_ gain.
<>"-'. Ind li_,ity drill· .141 VolYga
Current
T'*' erro< ...... TMlperalure RengetSi
V,,"-. UnipoIor
Bipollr
Current, Unipolar
Bipoli.
Olin. V,,"C-t

MECHANICAL

.110
.130
.150
.250
.500 BASIC
.002
.010
.• 00
0.85

1.27
0.89
2.54 BASIC
2.79
3.30
,6.35
3.81
15.24 BASIC
0.05
0.26
2.16
2.67

CASE: Ceramic
MATING CONNECTOR: 245MC
WEIGHT: 8.4 grams, 0.3 oz.
. HERMETICITY: Conlo,ms to
method 1014 condition C step 1
I fluorocarbon' of. MllwSTO..a83
I gross leak,.

MODEL

A 71
TYP

MIN
POWER SUPPLY SENSITIVITY
'\;Inipolar Offset "
±15VDC
+15VDC
Bipolar Offset
±15VDC
"
+5VDC
~. '

:to.oool
.

MAX

"

"i\

UNITS

.

"

..... '

"

~O.OOOI

%01 FSR/%Vs
. % 01 FSR/%Vs

±0.0004
±O.Oool

%01 FSRI%Vs
% of FSR/%Vs

±O.OOl
±O.OOOS

%ofFSR/%Vs
%01 FSRI%Vs

Gain

±15VDC
+5VDC

;

POWER SUPPLY I!EQUIREMENTS
Voltage
S~pply Drain. ±15"DC ,no load,
+5VDC , logic supply,
TEMPERATURE RANGE
Specification
.
Operating' double above Drift Specs,
Storage
'

±14.5, +4,75

±15, +5
±25

+20
0
-25
-55

±15.5. +5.25
±35
+35

VDC
mA
mA

+70
+S5
+100

°C
°C
°C

NOTES:

C·

-\"'.

1. Adding external CMOS hex buffers CD4oo9A will provide 15VDC CMOS'input compatibility. The percent
change in ouiput(.1 Vo 'as 10picO varies from O.OV to+0.4V and logic 1 changes from +2,4V to +5.0V on all inputs
is less than 0.006% 01 FSR.
2. FSR'means Full Scale Range and is 20V lor ±I OV range: 10V for ±5V range. etc.
3. Adjustable to zero with external trim potentiometer.
4. See "Computing Total Accuracy over Temperature".
5. With gain and offset errors adjusted to zero at 25°C.
6. LSB is for 14-bit resolution.
7. Maximum with no degradation of specifications.

CONNECTION DIAGRAM'

PIN ASSIGNMENTS
1.0~F~

I Models
,MSB, Bit I
Bit2
Bit 3
Bit4
Bn5
Bit 6
Bit7
BitS
Bit 9
Bitl0
Bitl1
Bit12
Bitl3
Bit14
Bit 15
,LSB, Bit 16
RF
+5VDC
-15VDC
COMMON
lOUT
GAIN ADJUST
+15VDC
6.3V REF, OUT

+Vs
10kll

L-----~------'O+Vl

Current Model does not

'RF=5~11

,CSB,.IOkll ,COB,. SkI! ,CCD,.

6-36

Pin
No.
1
2
3'
4
5
6
7
6
9
10
II
12
13
,14
15
16
17
18
19

20
21
22
23
24

V Models
Bitl,MSB,
Bit 2
Bit3
Bit4
Bit5
Blt6
'BIH
BitS
Bit9
Bit 10
Bitll
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16,lSB,
VOUT
+5VDC
-15VDC
COMMON
SUMMING JUNCTION'
GAIN ADJUST
+15VOC
6.3V REF. OUT

DISCUSSION OF SPECIFICATIONS
DIGITAL INPUT CODES

+O.08r---------,

the DAC71 accepts complementary digital input codes in
either binary (CS B. CO B) or decimal (CCD) format. The
COB .model may be connected by the user for either
complementary offset binary (COB) or complementary
two's complement (CTC) codes (see Table I).

+O.06t--------~,.

TABLE I. Digital Input Codes.
DIGITAL INPUT CODES
CSB

..,!l0w

..
8
2

MSB

AllbitsON

ai MidScale
~ Allbi1S0FF

LSB

&00 . 00&
0111 ... 111
1111 ... 111

100(1...000

COB

Campi .
Straight
Binary

Campi:

+Full Scale
+1/2 Full Scale
Zero
Mid Scale -ti.. 58

+Full Scale
Zero
-Full Scale
-'lS~

Oflsel

BInary

CCD

~
w

Complementary Coded
Decimal 4 DigitS

0

0
2
0
0

o

F.S. bits ON
AIIBit~OFF

0110 ... 0110

'+Full SCale

',11.,,111,'

Zero

CTC'
,Compl.
Two's
Complemenl

-0.08 0!---+-2~5~----"';+~70

-1LSB

Temperature

Characteristic

jOe t

-Full Scale

Zero
+Full Scale
·Invert the

MSBofthe
COB code
with an
external
inverter to
ebtainCTC
cexle.

FIGURE I. Gain Drift Error (%)vs Temperature.
The maximum change in offset is referenced to the offset
at +25"C and is divided by the temperature range. This
drift is expressed in parts per million offull scale range per
"c (ppm of F~R!"C).·
.

SETTLING TIME

ACCURACY
LINEARITY
This s~cification describes one of the truest measures of
0/ A converter accuracy. As defined it means that the
analog output will not vary by more than ±O.OO3% max
(CSB. COB) or±O.005% max (CCD) from a straight line
drawn through the end points (all bits ON and all bits
OFF) at +25"C.
DIFFERENTIAL LINEARITY
Differential linearity error of a 0/ A converter is the
deviation from an ideal I LSB voltage change from one
adjacent output state to the next; A differential linearity
error specification of ±1/2LSB means that the output
voltage step sizes can be anywhere from 1/ 2LSB io
3/2LSB when the input changes from one adjacent input
stage to the next.
MONOTONICITY
Monotonicity over O"C to +50"C is guaranteed. This
insures that the analog output will increase or remain the
same for increasing 14-bit input digital codes.

DRIFT
Gain Drift is a measure of the change in the full scale
range output over temperature expressed in parts per
million per"C(see Figure I). Gain Drift is established by:
I )testing the end point differences for each DAC71 model
at +25"C and the appropriate specification temperature
extremes; 2) calculating the gain error with respect to the
+25"C value; and 3) dividing by the temperature change.
This is expressed in ppm/"C..
Offset Drift is a measure of the actual change in output
with all "I"s on the input over the specified temperature
range.

6-37

Settling time for each DAC71 model is the total time
(including slew time) required for the output to settle
within an error band around its final value after a change
in input (see Figure 2).

j1

~

8.
c:
G.

0.1

~.!

;~

~~

'0

FIGURE 2. Full Scale Range Settling Time vs
Accuracy ..
VOLTAGE OUTPUT MODELS
Settling times are specified to ±O.OOJ% of FSR; one for
maximum full scale range changes of 20V and one for a
I LSB change. The I LSB change is measured at the major
carry (0111 ... 11 to 1000 ...00), the' point at which the
worst-case settling time occurs.
CURRENT OUTPUT MODELS
Two settling time are specified to ±O.003% of FS R. Each
is given for current models connected with two diffc;rent
resistive loads: Ion to loon and looon.
COMPLIANCE '
Compliance voltage is the maximum voltage swing

-

......
U

C
CI

allowed on the output 0.1'. ~th~.,ciJ~r~~r.::!'l16q~IS:-\Yhi1e"
maintaining specified accuracy. The typical compliance
voltagct of aU current output" models is ,:t2.5V and
maximumsate'vtllnrgt'swi'tl'g permitted without damage
';'. ','
'
is±5V.
POWER$UPfJLY SENSIT,iVITY
; Power supplysehsiiiV,ieyis a meli~u~ of tile effect of a
power supply change on the D.: A,converter putput. It is
defined asa 'Percento.f;FS1f.~per'percent of change in
, either the positive. negative. or logic supplies abo.ut th¢
, nominal pow~r,s!lpply'voltages (see Figllre 3).
"

~

"

,5

0,04

.."'"

0,02

Cfl

>
c

~

't;;

0.

g.
UJ

a:

Cfl

LL

0
~

"

3.9Mn
~

·15V,Supply

/'

'~

J::

'u
0

should be lOOppm/"C or less. The 3.9MO and 270kO
resistors (200/( carbono,1i ~tter) sl\o.uld, be located c)oseto
ihe DAC71 to preveniiibi~e pickup. I fit is not:donvenieht
to use Hiese high-vitfue resistors. an equivalent''T''
'~etwork. as shown in Flg;"re' 4;' may be substitUted in
"-place 'of the 3.9Mll. A"O:OOIIlF to O.OI,.'F 'cetamic
. capacitor should be'connected from Gain Adj'usl'(pin 22)
to common to "re~ent noise pickup. Ref'e'r to Figures 5
and 6 for relationship of offset and gain adjustmc;nts to.
unipolar and bipolar D A"converters:

"

0,1
0,08
0,06

0.
0.

";'~justa.s il~s'i,tib!id below" TCR of the potentiometers

0,01
0,008, ,
0,006

,,'"

,

+5~ SUPPlY,;;

~V

0,004

18Ok1l

IlIOkn

~.~

/
Equival~nt

FIQIJRE 4.

Resistances.

..L

+iSV Supply

./

0,002

../

0,001
1

I

/' /

"/

'

..':"

lk
10k
100
10
Power Supply -Ripple FreqjJency I Hz,

"
,'"

+full Scale

,,":":"'T

ILSB
lOOk

"'~

co

i

:f

C

Range ot
,Olfset

All DAt1 f models are supplied with im internal +6.3\1
reference voltage supply, This reference voltage (pin 2~)
has a to.lerance, of ±5(ii and is co.nnected internally for
specified operation. The zeni:r is'selected for a Gain Drift
of typically ±3pPI11 "(:' find, is burned-infor a total of 168
hours fo.r guaranteed rdiability. This reference may also.
be used, externally b,ut the current drain is limited to
200IlA. An externl\lb,uffer amplifier is reco.mmended:,if
the DAC71 internal reference is, used .ex,ternally in order
to provide a consta'ntfoad to the reference supply output.

.-,!;"
,~/~f

All bllS
.:;,;0"
logic I ~r--

AlII'ljt

REFERENCE SUPPLY

,~

Ranga ot
8al,n

AlI .

Gain Adl.

rOlatas

All bill
Log~c 0

tha lime

OI'set All;.
Tranllat.. ~

Digital Input

I

the line

'

~~' '"
.JI!

m

i

FIGURE 3, PowerSupply,Rejectionvs Power Supply
Ripple Frequency,

/"" 0'/

~
&!

FIGURE5. Relationship of Offset and Gain Adjust~
ments for a Unipolar D; A Converter.

'.:L

ILSB

L

/~ Rangaot
+full Scale ,,;,; Gain Ad;.

r....f_·~·,.T
S'

All blls
logic I

OPERATING INSTRUCTIONS
s

POWER SUPPLY CONNECTIONS

~

F'or optimum performance and noise, rejection. power
supply dccoupling capadio'rs ;hoUld be added as sh()wn
in the (;' shows a simplified circuit diagram cia
DAC7i~cOB-V with all bits 'ofC The current switch
leak~ge current is negligible. SO
V-I't'I,1, SCAU' = (-Rd RRPo)' VRH
= (-!QkQ/6.3kO). 6,3V = -IOV

+Vcc

.

.

- I of

~

/

:'V+FS ~ ':'W_ Fa

~

." /IIIn DrIft· :'V+FS ':'V.f8
~2:.V+FS'·

I ... ',

=~11:! ....-,

III

1"""''''''1""'1..........
j
---.lI..l...L...&....I..L_

\111

IfIlII

·3

FIGURE 17, (a) Effecto( a Positive Ref'erence Drift on
the Ideal D, A Transfer Function: (b) Error
Distribution Due to Reference Voltage
Drift in a DAC71.

. , VOUT =·IOV

'.

FIGURE 16. Simplified Diagram of DAc71-COB-V
,
with "All Biis Off'(±IOY Range).
This equation shows that ifYKH ,increases, the Qutput
voltage will decrease"and vice veisa.lf·the VRIT drift'is
+ IOppmj"C,this equiyalenn'o (t IOPPrnl"C) x I +6:3V)""
+63,.,. V j"C. This will result,in a voltage drift at. the
amplifier output of
.'

a V-Fs/olT = -CR,/ RHPo )' (a VREF/'.l T)
==

~IOknj6.3kn). (63,.,.V!,'9 = -IOO,.,.V('C.

"

Using this relationship. the worst-case accuracy drift for \\
DAC71-C08-V can be computed. The maximum TCR
. of the zener reference is ±!Oppm "(.The gain drift due to
the reference then is also ± IOppin "c. The full sca,le drift
. and bipolar offset drift are each half that ;,a:!nount or
±5ppm "c. The maximum. gain and offset drifts of the
: DAC71.exciusive of (he reference. are±5and ±3ppm "G"
respectively. Adding this to the full scale drift due to the
reference .plus the linearity drift of ±2p.pm, "C gives a
worst-case total accuracy drift oft 15pph1 "~Co (Rando~
drifts, which these are,can be irith~ same direction.so they
'add directly.) This is muchiess than~tlie t6,.11 drift
obtained by simply adding the maximum gain. bipolar
offset; and linearity drifts (±27ppm"C).The ~aximum

6-42

zero point drift is equal to one-half of the gain drift
exclusive of the ~eference plus the offset drift exclusive of
the reference; or ±5.5ppm of FSR/"C.
The DAC71 is specified over a O"C to +70"C temperature
range giving a maximum excursion from room temperature (+2S"C) of 45"C. Assuming that gain and offset
errors have been adjusted to zero at room tempetature.
total worst-case accuracy error
= Linearity error + Accuracy drift x ~ T
= ±0.OO3% + ±ISppm/"C (45") (100)
=±0.07%
total worstccase bipotar zero point error
= Bipolar zero drift x ~T
= ±5.5ppm of FSR% (4S"C) (100)
= ±0.02S%

ORDERING INFORMATION
MODEL

-.....

INPUT CODE

c.,)

CC
CI

CURRENT MODELS
DAC71-COB-1
DAC71-CSB-1
DAC71-CCD-1

Complementary Offset Binary
Complementary Straight Binary
Complementary Coded Decimal

VOLTAGE MODELS
DAC71-COB-V
DAC71-CSB-V
DAC71-CCD-V

Complementary Offset Binary
Complementary Straight Binary
Complementary Coded Decimal

643

BURR-BROWNe

OAC72

I ElEEI I

High Resolution
16-BIT DIGITAL-TO-ANALOG CONVERTER
FEATURES

DESCRIPTION

• IS-BIT. 4-DlGIT RESOLUTION

The DAC72 is a high quality 16-bit hybrid IC Di A
converter in a 24-pin dual-in-line metal package.

• ±O.OO3% MAXIMUM NONLINEARITY
• LOW DRIFT ±5ppm/oC. TYPICAL
• AVAILABLE IN TWO TEMPERATURE RANGES:
II"C to +700C
-25?C to +B5°C .
• CURRENT AND VOLTAGE MODELS
• LOW COST
• METAL HERMETIC PACKAGE
VOLTASE MODEL
6.3V REF. OUT
+15VDC
GAIN ADJUST

DAC72 with internal reference and optional output
amplifier 'offers a maximum linearity error of
·±O.OO3% of FSR at room temperature and a maximum gain drift of ±20ppm"/OC over a temperature'
·range ofOoC to +70OC. DAC72 offers a maximum
linearity error of ±O.OO3% of FSR at room temperature and a gain drift of ±20ppm/oC from -2Sd C to
+8SoC.
Three basic models accept complementary 16-bit
binary or complementary 4-digit BCD TTLconipatible input codes.
Packaged within the DAC72are fast-settling switches
and stable laser-trimmed thin-film resistors that let
you select output voltages 0 to +IOV (CSB and CCD)
or±IOV (COB)and output currents of±1 rnA orO to
-2mA. Input power is ±IS.VDC and +5VDC.
'

SUMMING JUNCTION

I!'.!

~
!!i

·15VOC

~

+5VOC

...

!!!

V OUT

}-~
INPUTS

Inlemllllllil AlrpDrt Indualrlll Park· P.O. Box

11~.

TuClan. Arlzonl85734· Tel. 16021 74&-1111 • Twx: 9111-952·1111 • Cable: BBRCORp· Telex: 66-6491

6-44

SPECIFICATIONS
ELECTRICAL

-

Typical at TA - +25°C and rated power supplies unless otherwise noted
DAC72C

MODEL
MIN

I

TYP

I

DAC72

I

MAX

MIN

I

TYP

I

MAX

I

UNITS

INPUT
DIGITAL INPUT
Resolution,

ceo

4
16

CSB, COB
Logic Levels, TTL-Compatible ,11)

logical "'''1' at+40~A'
L'ogica' "0" ,at -1.6mA'

+5,5
+{).4

+2.4
0

Digits
Bits

4
16

+5.5
+0.4

+2.4
0

VOC
VOC

TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error at 25°C,

ceo

COB,CSB
Gain Error(3l, Voltage
Current
Offset Erron 3 l, Voltage, Unipolar
Voltage, Bipolar
Current, Unipejlar
Current, Bipolar
Monotonicity Temp, Range' 14-bits I

!0,OO5

::to.OS
±O.l

0

±O.lS
±0,25
±2
::t.10
±1
±5
+50

%01 FSR(21

:tQ.OO5
:tQ,Q03

±O.OO3
±0,Q5

%0' FSR

:tQ,Q5

::to.1S

:to.OS

±0,25
±2
±10
±1
±5
+70

%
%
mV
mV
.A
.A
°C

±11/±19
±4O

ppm of FSR/oC
ppm of'FSR/oC

±0.1

0

DRIFT, Over specified temp. range

Total Bipolar Drift, includes gain. offset.
and linearity drift 1(4', Voltage' hot/cold ,(51
Current
Total Error over Temp. Range(B)
Voltage. Unipolar I hoVcold .(5)
Bipolar' hoVcold ·(5)
Current. Unipolar

±7
:::15

±15
±50

~5

±10

;:0,083
±O.O71
±O.23
±O,23

Bi'p~lar

Gain. Voltage', hot/coldl(5j
Current
Offset
Voltage. Unipolar
Bipolar
Current. Unipolar
Bipolar
Differential Linearity over Temperature
Linearity Error over Temperature

:tQ,072/±O.10
:tQ.072/:tQ,10
!0.24

%0' FSR
%0' FSR
% 0' FSR

±0.24

%
FSR
'ppmfOC

"±5

±2O

±eo

0'

±2O
±47

±1

±2
±10
±1
±4O
±2
±2

:':1

±2
±8
±1
±35
±1
±1

5
3
20'

10
5

5
3
20

10

ppm/oC
ppm
ppm
ppm
ppm
ppm
ppm

of FSR/oC
of FSR/oC
01 FSRfOC
of FSR/oC
of FSR/oC
of FSR/oC

SETTLING TIME
Voltage'Models ito ±O.OO3% of FSR
Output: 20V Step
lLSB Slepl7l
Slew Rate
Current Models to ±0.003% of FSR
Output: 2mA step lOU to lOOn Load
lkU Load
Switching Transient

1
3

.sec

5

~sec

VllJ.sec
1
3

500

J..I.~.C
~sec

500

mV

Oto+10
±10

V
V
mA
II

OUTPUT
ANALOG OUTPUT
Voltage Models
Range. - eSB, eco
COB
Output Current
Output Impedance DC·
Short Circuit Duration
Current Models
Ranges - CSB, CCO
COB
Output Impedance ~ Unipolar
Bipolar
Compliance
INTERNAL REFERENCE VOLTAGE

N
.....

Co)

o to +10
±10
±5

6.0

:':5
0.05
Indefinite to Common

0,05
Indefinite to Common

o to ~2
±1
15
4.4
±2.S

Ot~-2

6.3

Maximum External CurrenHSI
Temp, Coeff. of Drift

6,6

±200
±10

6-45

mA
mA

±1
15
4,4
±2.5
6,0

8,3

kll
kll
V
6,6

V

±200

.A
ppm/oC

±S

-

C

=

MODEL
MIN
POWER SUPPLY SENSITIVITY
Unipolar Offset
;l:l,~VDC

.

DIIC72C"
TYP

','

",

MAX

DAC72
TVP

"MIN

UNITS

MAX

I
:to.COOl
±0.0001

+15VDC
Bipolar Offset
±15VDC
+SVDC

±O.OOOl
±O.OOOl

% of FSRI%Vs
% of FSR/'lli Vs

±O.OO04
±O.OOOl

±0.0004
±O.OOOl

% of FSRI%Vs
% of FSRI% Vs

±0.001
±O.OOOS

±0.001
±0.0005

% of FSRI% Vs \
%ofFSRI%Vs

""

Gain
±15VDC
+5VDC

POWEll SUPPLY REQUIREMENTS
Voltage
Sopply Drain, ±15VDC I no load)
+5VDC I logic supply)

±14.5. +4.75

±15, +5
±25
+20

±15.5, +5.25
±35
+35

±14.5, +4.75

+70
+85
+100

-25
-55
-55

±15,+5
' ;1:25
±20

±15,5, +5.25
±35
+35

VDC
mA
mA

+85
+100
+110

·C
·C
·C

TEMPERATURE RANGE
0
-25

Specification

Operating) double above Drift Specs I
Storage

-55

'NOTES:
.~, i

1. Adding external CMOS hex buffers CD400QA will provide 15VDC CMOS input compatibility. The percent change in output ,..I Vo'
aslogicOvariesfromO.OVtoO.4Vand Ilogic 1 changes from +2.4V to +5.0V on an inputs is less than 0.006% of FSR.
2. FSR means Full Scale Range arid is 20V for ±10V range, 10V for ±5V range. etc,
3. Adjustable to-zero with external trim potentiometer.
4. See "Computing Total Accuracy over Temperature".
5. Hot .. +2SOC to +850 C; Cold'" -25°C to +25°C for DAC72.
6. With gain and offset errors adjustvd to zero at 25°C.
7. LSB is for 14-blt resolution.
8. Maximum with no degradation of specifications.

MECHANICAL

-~'=:1

1
L

CONNECTION DIAGRAM
1.0~F~

NOTE:
Leads in true

D

+Vs

position within .010'"

10kU
to
IOOkll ..

1.25mm, R at MMCat
seating plane.

·V.

" - Oenotes pi" 1

b
~IUJIIIII!t R
l.G
.-l~1H
--,

C==

0 ••••

° •• ° • •• "

1

,;..

2'

13

10kU
'to
'l00kll

+Vs

L-I

b

FI ! '

~+-''NI~---..~

r - -.....-o-Vs

Pin numbers shown
for reference only.
Numbers may not be
m~trked on package.

~--r-----o+VL

000000000000

INCHES

DIM

MILLIMETERS

MIN

MAX

MIN

MAX

1.365

1.386

34.67

35.18

.790

20.07

C

.170

.810
.250

4.32

20.57
6.35

0'

.016
.021
.tOO BASIC

0.41

0.53

A

•
G
H
K

L
R

.126
.150
.150
.300
• .eooRASIC

.08.

.110

Current Model does not contain.A 1.

2.54 BASIC

3.18
3.81

3.81

7.62

15.24 BASIC
2.03

2.79

°RF = 5kU (CSBI.10kU (COBI, 8kU ICCDI.

CASE: Nickel Plated Steel
MATING CONNECTOR:245MC
WEIGHT: 8.4 grams (0.3 oz. I
HERMETICITY: Conforms to method 1014 Condition C
Step 1 (fluorocarbonl of MIL-STD-883 Igross leek).

6-46

DIFFERENTIAL LINEARITY
Differential linearity error of a D/ A converter is the
deviation from an ideal I LSB voltage change from one
adjacent output state to the next. A differential linearity
error specification of ±1/2LSB means that the output
voltage step sizes can be anywhere from 1/2LSB to
3/2LSB when the input changes from one adjacent input
stage to the next.

PIN ASSIGNMENTS
Pin

I Models
IMSB,Bill
Bil2
Bil3
Bil4
Bit 5
Bil6
Bil7
Bil8
Bil9
Bill0
Billl
Bit12
Bil13
Bil14
BII15
ILSBI Bil16
RF
+5VDC
-15VDC
COMMON
lOUT
GAIN ADJUST
+15VDC
6.3V REF. OUT

No.
1

V Models
BllllMSBI
Bil2
Bil3
Bil4
Bil5
Bil6
Bil7
Bil8
Bil9
Bill0
Billl
BII12
Bil13
Bil14
BillS
Bil161LSBI
VOUT
+5VDC
-15VDC
COMMON
SUMMING JUNCTION
GAIN ADJUST
+15VDC
6.3V REF. OUT

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

MONOTONICITY
M onotonicity over O"C to +50"C (DAC72C) and O"C to
+70"C (DAC72) is guaranteed. This insures that the
analog output will increase or remain the same .for
increasing 14-bit input digital codes.

DRIFT
Gain Drift IS a measure of the change in the 'full scale
range output .over temperature expressed in parts per
million per"C(see Figure I). Gain Drift is established by:
I) testing the end point differences for each DAC72 model
at +25"C and the appropriate specification temperature
extremes: 2) calculating the gain error with respect to the eN
+25"C value: and 3) dividing by the temperature change. Co:»
C
This is expressed in ppmj"c.

....
=

DISCUSSION OF
SPECIFICATIONS
Ii

DIGITAL INPUT CODES
The DAC72 accepts complementary digital input codes in
either binary(CSB, COB) or decimal (CCD) format. The
COB model may be connected by the user for either
complementary offset binary (COB) or complementary'
two's complement (CTC) codes (see Table I).
T ABLE I. Digital Input Codes.
DIGITAL INPUT CODES
CSB

~

Compl.

~

MSB LSB
0000 ... 000

Iti Mid Scale
~ All biisOFF

0111 .. 111

8 All biisON

1111...111

1000 •.. 000

COB
CompL

Straight

Offset

Binary

Binary

+Full Scale
+1/2 Full Scale
Zero
Mid Scale -1LSB

+Full Scale
Zero
-Full Scale
·1LSB

CCD

'"~

Complementary Coded
Decimal 4 Digits

o
::z

8

F .5. bits ON

o

All Bits OFF

0110 ...0110
1111...1111

+Full Scale

Zero

."""0

...
c

C)

+0.04
+0.02
0
-0.02
-0.04
-0.06
-0.06
-25

~

III

~
UJ

Temperature (OCl

CTC'
Compl.
Two's
Complement

FIGURE I. Gain Drift Error (%) vs Temperature.

·1lSB
-Full Scale
Zero
+Full Scale

Offset Drift is a measure of the actual change in output
with all "I "s on the input over the specified temperature
range.
The maximum change in offset is referenced to the offset
at +25"C and is divided by the temperaiure range. This
drift is expressed in parts per million offull scale range per
"C (ppm Of FSRj"C).
.

'Invert the
MSBofthe
COB code
with an
external
inverter to
obtain eTC
code.

SETTLING TIME
ACCURACY
LINEARITY
This specification describes one of the truest measures of
D/ A converter accuracy. As defined it means that the
analog output will not vary by more than ±O.003% max
(CSB, COB) or ±O.005% max (CCD) from a straight line
drawn through the end points (all bits ON and all bits
OFF) at +25"C.

6-47

Settling time for each DAC72 model is the total time
(including slew time) required for the output to settle
within an error band around its final value after a change
in input (see Figure 2).
VOLTAGE OUTPUT MODELS
Settling times are specified to ±O.003% of FSR: one for
maximum full scale range changes of 20V and one for a

.referenc~·voltage supply. This' reference voltage (pin 24)"
has a tolerance df±5%.abdis comietled internally for
.specified operation. The zener is selected for a Gain D~ift
of typically ±3ppml"C and is burned-in for a total of 168
hours for guaranteed reliability. This reference may also.
be used externally. but the current drain is limited to
'.200IlA. An external buffer amplifier is recommended if
'the DAC72 internal rereren¢e is used externally in order
to provide a constant load to the reft:rence supply output;

~

.'"
.

0.1

~~

p.Ol

c

a:
~-I
~ cl!' 0.03

"0
E

.

!!

OPERATING INSTRUCTIONS

"

Q.

POWER SUPPLY CONNECTIONS '

Settling Time (#AseC)

FIGURE 2. Full Scale Range Settling Time vs Accuracy.

I :

~.

'llSBchange: The I LSBchange is measured at the major
carry (0111...11 to 1000 ...00), the point at which the
worst-case settling time occurs.

. CURRENT OUTPUT MODELS
Two settling times are specified to±0.003% ofFSR. Each
'is given for current models connected with two different
resistive loads: Ion to loon and 1000n.

. For optimum performance and .noise rejection, power
supply decoupling capacitors should be added as-shown
in the Connection Diagram. These capacitors (Illf
tantalum or electrolytic recommended) should be located
close to the DAc'72. Electrolytic' capacitors. if used,
should be paral.leled with O,OIIlF ceramic capacitors for
best high frequency performance .

COMPLIANCE
Compliance voltage is the maximum voltage swing
allowe.d on the output of the current models while
maint~iningspecified accuracy. :The typi"cal compliance
voltage of 'all current output models is ±2.5V and
maximum'Slife'voltage swing permitted without damage
is±5V.
.
POWER SUPPLY SENSITIVITY
Power supply sensitivity is a measure of··tpe effect of a
.power supply change on the Dj A converter output. It is.
defined as a percent of FSR per percent of change in
either the positive, negative, or logic supplies about the
nominal power supply volta,ges (see Figure 3) .

,:ag.

.

...

-15V Supply

~

~ 0.02

.r:

~

+5V Supply./
0:01

~ 0.008
~

.

~

0.006
0.004

~

0.002

"0

0.001' .
1

'"a:"~

Offset and gain may be trimmed by installing external
,offset and gain potentiometers, Connect these poten-'
tiometers as shown in" tlie Conn.ection Diagram and
adjust as described below. TCR of the potentiometers
should be IOOppm/"C or less. The 3.9MO and ,270\cO
resistors (20% carbon or better) should be located close to
the DAC72 to prevent noise pickup.lfit is not convenient
to us'e these high-value resistors, an equivalent "T"
network, as shown .in Figure 4, may be substituied in
place of the 3.9tVtn. A O.OOIIlF to O.OIIlF ceramic

FIGURE 4. Equivalent Resistances.

0.1

0.08
'" 0.06
>
0.04
.5

EXTERNAL OFFSET AND GAIN
ADJUSTMENT

.L

/

~

V

/

"
~""

+Full SClla
lLSB
"

I

+15V Supply

./

/j

/: :/

I

10
100
lk
10k·
Power Supply Ripple Frequency (HZI

lOOk

FIGURE.3. Power Supply Rejection vs Power Supply
Ripple Frequency.

R naa DI

I

~

"';.*..,

i

All bltl .~;r
logic 1 • ~

..
...

~tll'AdJ'll

""'''-''''"T
II

"fI',,'"/ "

/

,~"

""

,

RangaDl
Gain AdJ.

Glln AdJ .
rotatas

All bill

Ibatlma

LOglcll

011111 AdJ: .

nlnal.... . - thallna
I'"

R~FERENCE

SUPpLY
All -DAC72 models are supplied with an internal +6.3V

6-48

1I1gltattnput

FIGURE 5. Relationship of Offset and Gain Adjust.
ments fo'r a Unipolar D/ A Converter.

GAIN ADJUSTMENT
For either unipolar or bipolar configurations. apply the
digital input that should give the maximum positive
output voltage. Adjust the gain potentiometer for this
positive full scale voltage. See Table II for positive full
scale voltages and the Connection Diagram for gain
adjustment connections.

capacitor should he connected from Gain Adjust (pin 22)
to common to prevent noise pickup. Refer to Figures S
and 6 for relationship of offset and gain adjustments to
unipolar and bipolar 0/ A converters.
If the full (absolute) accuracy capability of the DAC72 is
required. recalibra,tion of gain and offset every 2 months
is recommended.

rr-

ILSB

L

0:
S

All bill
logic I

"

;f

/"

+Full

~

Sa~ / ;

-*-

INSTALLATION
CONSIDERATIONS

T

Range 01
I•

1}
'\~ GaIn
AlII.
.,
rotate.

/~,/

The DAC72 is laser-trimmed to 14-bit linearity. The
design of the device r:nakes the 16-bit resolution available
on binary units. If 16-bit resolution is not required. bit 15
(pin IS) and bit 16 (pin (6) should be connected to
+SVDC through a single I kn resistor.

thallne

~~~~~~/~~~.~~~ All bill

"'i. -:.,
II

Bipolar V
~/..
0If1ll
'.& ~
Ringe 01
0If1ll Adj.1.
fIIllIIAdl • ..L
Trlnala... --rthallnl
..

logic 0

~.

MSB ON
all others
OFF

''I'

/ ~-'-t~v"

Due to the extremely-high resolutIOn and linearity of the
DAC72. system design problems such as grounding and
contact resistance become very important. For a 16-bit
converter with a +IOV full scale range. I LSB is IS3/lV.
With a load current of SmA. series wiring and connector
resistance of only 30mn. the output will be in error by
I LSB. To understand what this means in terms of a
system layout. the impedance of #23 wire is abo.ut
0.02In/ft. Neglecting contact resistance. less than 6
inches of wire will produce a I LSB error in the analog
output Voltage! Although the problems involved seem
enormous. care in the installation planning can minimize
the potential causes of error.
Figure 7 shows the connection diagram for a voltage output
DAC72. Lead and contact resistances are represented by

011111

Scale

DlgltellnpUl

FIGURE 6. Relationship of Offset and Gain Adjustments for a Bipolar 0/ A Converter.
OFFSET ADJUSTMENT
For unipolar (CSB. CCD) configurations. apply the
digital input code that should produce zero potential
output and adjust the offset potentiometer for zero
'output.
For bipolar (COB. CTC) configurations. apply the digital
input code that should produce the maximum negative
output voltage. The COB model is internally connected
for a 20V FSR range where the maximum negative output
voltage is -IOV. See Table II for corresponding codes and
the Conneciion Diagram for offset adjustment connections. Offset adjust should be made prior to gain adjust.

DAC72·CSB·V

N]

VOUT R2

TABLE II. Digital Irlput and Analog Output
Relationships.

17

RL

OUTPUT CODE
DIGITAL INPUT CODE

VOLTAGE

16-Bit
Resolution

~--------~r---------~

CURRENT

14-8il
Resolution

16-Bit
Resolution

14-8il

R4~

Resolution

Complementary Unipolar

Straight Binary, csa,
o to +tOVor Oto -2mA"
One LSB
All Bits ON ,'00 ...00
All BisOFF '11 ... 11

+1531'V

+6101lV

a.0311lA

+9.99985V
Zero

"'9.99939V
Zero

-1,99997mA
Zero

O.I22#1A
-1.99988mA
Zero

+3OS~Y

+1.22mV
+9.99878V
·1O.0000V

O.031J,tA

O.I22J.1A

-o.99997mA
+l.0000mA

-o.99988mA
+1.0000mA

to Pin 23 _T"--J.---':"--~+!Vr---'
COM ±I5VOC
l~F
SUpply
To Pin 19 --.4--"-1----------.V~
~

Complementary BipOlar
Offset Binary I COB

____

±IQVor±lmA'
One LSB
All Bits ON '00 ...00
All Bits OFF I 11 ... 11'
Complementary Binary
Coded Decimal.
o to +10V or 0 to -1.25mA
OneLSB
Full Scale .0110 ...0110
All Bits OFF -1111 ... 1111

ceo

3
SanIIOUI/I:t

+9.99969V
-10.0000V
4-Digit
Resolution

N/A

+1.0mV
+9.999V
Zero

To Pin IB __r--+-----::+V~---l
COM +5VOC
SUpply

4-Digit,
Resolution
N/A
0.125~A

*RB =31m ICOBI
RB =3.9knlCSBI
RB = 5.1 knlCCOI

-1.24987mA
Zero

• To obtain values for other binary -CBI- ranges: 0 to +5V range, divide 0 to
+10V range by 2: ±5V range, divide ±10V range by 2; ±2.5V range, divid~±10V
range by 4 ..

FIGURE 7. Output Circuit for Voltage Models.

6-49

RI through Rs. As long as the ,load iresista:n~e (Rt) is
constant,R2 simply introduces again error that can ,be
removed during initial calibration. R3 is,part of RL if the
output voltage is sensed at Common (pin, 20) .and
therefore introduces no error. If RL is variable then R2
should be less than I LSB. For example, if RLmin is Sk!1
then R, should be less thanO.OS!1. RL should'be located as
cl~se as possible to the DAC72 for optimum performanct;.
Figures Sand 9 show two methods of connecting current
model DAC72's with external precision output op amps.
By sensing the output voltage at the load resistor (i.e., by
connecting R" to the output of A I at Rd the effect of RI
and R, is greatly reduced, RI will cause a gain error but it
is independent of the value of RI. and can be eliminated
during initial calibration. The effect of R, is, negligible
because it is inside the feedback loop of the output op amp
and is therefore greatly reduced by the loop gain. If the
output cannot be sensed at Common (pin 20), then the
differential output circuit shown in Figure 9 is recommended. In this circuit the outputvoltlige is sensed at the
load common and not at the DA'C common as in the
previous curcuits." The value of R. and R, must be
adjusted for maximum common-mode rejecti'on at RI..
Note that if R3 is negligible the circuit of Figure 9 can be
reduced to the one shown in Figure S because RR '" (R, +
R~) 1/ R•. In all three circuits the effect of R. is negligible.

RZ

R5 +R7 = RF + RI
R6=ROAC

To Pin 23-,.-.-+

To Pin 18

·v

To Pin 19

+V

+

I~F

COM

COM ±15VDC
·V ' SUpply

+V

+ I';F

COM

~5VDC'
SUpply

FIGURE 9. DiffereniialSensing Output Op
Amp Configuration.
The DAC72 and the wiring to its connectors should be
located to provide optimum isolation from sources of
RFI and EMI. The key word in elimination 'of RF
radiation or pickUp is loop area. Therefore. signal leads
and their return conductors should be kept close together.
This reduces t~e external magnetic field along with any
radiation. Also. if a signal lead and its return conductqr
are wire(! close together they present asmall flux~apture
cross section for any external field. This reduces radiation
pickUp in the circuit'. The metal case, of the'DAC72is
internally connected to the common, pin, to further
minimize pickUp. The DAC72 is made of nickel plated
steel which also provides so~e electromagnetic shielding.
NOTE: It is recommended that the digital input lines of
the DAC72 be driven from inverters or buffers of TTL
input registers to obtain specifiedaccur~cy.'

"

COM

R3

R4
'+V

I~F

To Pin 19

+V

To Pin 23

TePin 18

DAC7Z.C88-1

±15VOC
SUpply

DRIVING A RESISTIVE LOAD UNIPOLAR
A load resistance. RI.. with the current output model
connect as shown 'in Figure 10. will gener~te a voltage
range. Vewl'. determiried by:
Vewl' = -2mA[(ISk!1x RI.}f(I Sk!1 + Rd]
Where RI. max = 1.36k!l
'
and Vewl' max = -2.SV

+5VDC
Supply

·Ra lbould be eqillllD the output
Impedance II Pin ZI ID campannte
lor III, bill currenl drtll 01 AI. U.e
.tendlrd 10%. 1I4W carbon cllll!pGlltion
or equivalent ra.llIOra.

Add an e'xternallow T.e. «lOppm/"C) resistor (Rd as
shown in Figure II to'obtain a 0 to -2V full scale output
voltage range, for CCD input codes.

Ra = 3Itn (COal
Ra =Ukn (CSDI
Ra = 5.lkll (CCD)

VOl"! = 1.2SmA [( IS.6kH x Rd/( 15.6kH + Rd]
Where RI, max =, 1.79k!1
and Vorl' max = -2.0 I V

FIGURE'S. Preferred ExternalOp Amp Configuration.

6-50

APPLICATIONS

\i

DRIVING AN EXTERNAL OP AMP WITH CURRENT
OUTPUTDAC
The DAC72-(CSB. COB. CCD)~I are current output
devices and will drive the summingjunction of an op amp
to produce an output voltage (see Figure 13). The op amp
output voltage is:

Current cantrallad
by dlgllllinpul

15Icri

VOl"'" = -I",· ... RF

FIGURE 10. Equivalent Circuit DAC72-CSB-1
Connected for Unipolar Voltage Output
with Resistive Load.

\r

N

Current contnJllad
by d'g't."nput

L -__________________

~

____________

+

FIGURE 13. External Op Amp Using Internal
Feedback Resistors.

15.8kn

FIGURE II. DAC72-CCD-1 Connected for Voltage
Output with Resistive Load.
DRIVING A RESISTIVE LOAD BIPOLAR
The equivalent output circuit for a bipolar output voltage
range is shown in Figure 12. Von is determined by:
V", .... = ±lmA [(4.44k!l x R,)/(4.44k!l + RI.)]
Where RI. max = 5.72kH
and Vo,'''' max = ±2.5V

Where 1m .... is the DAC72 output Current and RF is the
feedback resistor. Use of the internal feedback resistor
(pin 17) is required to obtain specified gain accuracy and
low gain drift.
The DAC72 "can be scaled for any desired voltage range
with an external feedback resistor. but at the expense of
increased drifts of up to ±2Sppmj"C. The resistors in the
DAC72 are chosen for ratio tracking of±lppmj"C and
not absolute TCR (which may be as high at ±25ppmj"C.)
An alternative method of scaling the output voltage ofthe
DAC72 and preserving the low gain drift is ~hown in
Figure 14.

Current contnJUad

\i

by dlglhllnput

"

±lmA

+

Ukn

FIGURE 14. External Op Amp Using Internal and
External Feedback Resistors to Maintain
Low Gain Drift.

FIGURE 12. DAC72-COB-1 Connected for Bipo.lar
Output Voltage with Resistive Load.

6-51

'""

~~

In the bipolar mod~the rnajor portion ofgain drift is d'u~.
, to the zener reference. The gilin and offset drifts caused by
reference drift are always in opposite directions .
Therefore, the accuracy drift will be the difference rather
.
than the sum of these'drifts.

OUTPUTS LARGER TH~N 2O·~QLT: R"~GE
For output voltage ranges larger than ±IOV. a high
.' vottage<1p ,amp may beC:mployed with .an exte{Qal
feedback resistor. Use lm't values of ±I mA for bipolar
,voltage rlj.nges and -2mA for unipolar voltage ranges (see
FigJlre i5).Use pro\ectlon diodes when a high voltage op
,amp is us~d, '
.

First. conside~ the effect of refer~nce variations on qffset
. drift. Figure 16 shows a simplified circuit diagram of a
DACnC-COB-V with all bits ofLThe current switch
kakage ciirrent is negli,gible, so

.....- - - _ 1 7

V-FI'I.I. S(',\I.I' = (-RF! RIlI·R). VREI'
=(-IOkU,6.3k!l) • 6.3V = -IOV

+Vcc

101m

VOUT

VOUT,·lav

'FIGURE IS. External Op Amp Using External
Feedback Resistors.'

FIGURE 16. Simplified Diagram of DACnC-C08-V
·with "All Bits Off"(±IOV Range),
.

COMPUTING TOTAL
ACCURACY OVER
TEMPERATURE
The accuracy driftwith temperature of a DACn consists
of three primary components: gain drift, unipolar or
bipolar offset drift, .and linearity drift., To. obtain the
· worst-case accuracy drift, most users would assume that
all· drift errors .are rand<;>m and w(,mld simply add them
algebraically. However. the worst-case accuracy drift for a
DACn operating in the bipolar mode is about one-half
of the algebraic sum of the individual drift errors.
.
· To explain this fact, it is necessary to consider the
unipolar and bipolar modes of operation separately. The
following analysis is for the DAcnc although it applies
to both models by simply substituting,th~ proper temperature coefficients from the electrical specifications ..
In the unipolar mode of operation. qffset drift (±l ppm
, "C) is due primarily to voltage offset drift of the output·op
.amp and. to a lesser extent, to theleakage current through
: the. quad cutrent sw'it~hes. Gain drift consists of several
co'mponents: I) ±Sppmj"C due to ratio drift of current
switch V HE to the reference transistor. 2) ± IOppm/ "c due
· to the zener reference and. 3) ±2ppmj."C·linearity drift
due to ratio drift of current weighting r~~istors and VIll' of
the quad current switches. The sum of these three
components. ±17ppmj"C, is the maximum gain drift.
Because the parameters described could all drift in ttie
same direction. the worst-case accuracy drift in the
.ulIipolarmode is simply the sum of the components, or
±18ppmj"C,

This equation shows that if VRI'I' increases. the output
voltage will decrease and vice versa. If the VREI· drift is
+IOppm "C. this is equivalent to(+IOppm "C) x (+6.3V)
= +63V "c. This will result in a voltage drift at the
amplifier output of
~V-FS ~T= -(RF RIlPo) .(~VREF ~T)
=~ 10k!! 6:3k!l). (63/lV "C) = -100J.lV "C.
Since the DAcnC-COB-V is operating in the ±IOV
range this is equivaleni to (-IOO/lV "C):';' (20V range) =
-Sppm of FSR "c.
Now consider the effect of reference changes on gain drift.
When all of the bits are turned on it can be shown that:
~ V+I''!'LL S('ALI'. ~T = +(RF, RIlPo). (~VREF' ~T)
= +( IOk!l,6.3k!l). (63/lV "C) = + IOO/l V "c
and (+100/lV."C)20V Range = +Sppm, "c of FSR.
This result indicates that the drift of the minus fuB scale
voltage will be equal in magnitude to, and in the
oppposite direction of. the drift of the phis full scale
voltage and that zener reference variations have virtually
n.o effect on the zero point (see Figure 17): This equation
also indicates that th.e gain drift is equal to the VRI'I drift
in ppm. "c, and the magnitude of the minus fuJI scale drift
and plus full scale drift is equal to one-half of the VREF
drift.
) Using this relationship, the'wprst-caseaccuracydrift for a
DACnC-COB-V can be computed. The maximum TCR
oflhe zener reference is±IOppm, ':C .. The gain drift dueto
the reference then is also ±IOppm "C. The full scale drift
and bipolar offset drift are' each half that amount or

6-52

~

,. t

I
go

J

I'

~

/;

I~~-

,

~".
Referancl drtft

I'

dOli not B"act
,~ zero point.

lal
Digital Input (bll

,,~

..

.
" ..

!

I

,

I'~

1'1'
~

;'

Gain Ortft =.1V+fS.-.1V,FS

/.

-,2.1V+FS·

I

I'

(LSBI
Error. ~l'
(bl

- 1lnlnnj"T1
JH,l""'

III

"T"'.....................................

,3,

FIGURE 17. (a) Effect ofa Positive Reference Drift on
the Ideal D/ A Transfer Function: (b) Error
Distribution Due to Reference Voltage
Drift in a DAC72.

±5ppm/"C. The maximum gain and offset drifts of the
DAC72C. exclusive of the reference. are ±5 and
±3ppmj"C respectively. Adding this to the full scale drift
due to the reference plus t~e linearity drift of±2ppmj"C
gives a worst-case total accuracy drift of ±15ppmj"C.
(Random drifts. which t;h~se· are carl be in the same
direction. so they add directly·.)'This is much less than the
total drift obtained by simply adding the maximum gain.
bipolar offset. and linearity drifts (±27ppmj"C). The
maximum 7.ero point drift is eljual to one-half of the gain
drift exclusive of the reference plus the offset drift
exclusive of the reference. or ±5.5ppm of FSRj"C.
The DACnC is specified over a O"C to +70"Ctemperature
range giving a maximum excursion from room tem. perature (+25"C) of 45"C. Assuming that gain and offset
errors have been adjusted to 7.ero at'room temperature.
total worst-case accuracy error
= Linearity error + Accuracy drift x ..l T
= ±0.0030i + ±15ppm. "C (45") (100)
= ±0.07o/r
total worst-case bipolar 7.ero point error
Bipolar 7.ero drift x ..l T
= ±5ppm of FSRyc (4S"C) (100)
= ±0.025(ii

ORDERING INFORMATION
MODEL
CURRENT MODELS
DAC720-COB-1
DAC72C-CSB-1
DAC72C-CCD-I
DAC72-COB-1
DAC72-CSB-1
DAC72-CCD-1
VOLTAGE MODELS
DAC72C-COB-V
DAC72C-CSB-V
DAC72C-CCD-V
DAC72-COB-V
DAC72-CSB-V
DAC72-CCD-V

TEMP RANGES

PKG

DoC to +70°C
COC to HO°C
DoC to +70°C
-25°C to +85°C
-25°C to+85°C
-25°C to +85°C

Metal
Metal
Metal
Metal
Metal
Metal

Compl. Offset Binary
CampI Straight Binary
Com pI. Coded Decimal
Com pI. Offset Binary
Comp\. Straight Binary
Compl. Coded Decimal

DoC to H00C
DoC to +70°C
DoC to +70°C
-25°C to +85°C
-25°C to +85°C
-25°C to +85°C

Metal
Metal
Metal
Metal
Metal
Metal

Compl.
Com pI.
Compl.
Compl.
Compl.
Compl.

6-53

fNPUTCODE

Offset Binary
Straight Binary
Coded Decimal
Offset Binary
Straight Binary
Coded Decimal

BURR-:BROWN®

OAC73
OAC736

I EI,EI I

High Resolution 16-8it
DIGITAL- TO~ANALOG CONVERTER
FEATURES

:-------_ ... _-----------------.--:

-16·BIT RESOLUTION

IV Rafarence

- ±1I2lSB MAXIMUM NONLINEARITY
- LOW DRIFT
- CURRENT DR VOLTAGE OUTPUT
-'INTERNAL GAIN. OFFSET. AND
LINEARITY ADJUSTMENT

Outpul

t----4 Ground

-LATCHED INPUTS IDAC731

Sense

-lOW COST

Hybrid '

DESCRIPTION
The; DAC73 is a 16-bit modular high performance
digital-to-analog converter in a 2", x 4" x 0.4"
(50.8mm x 101.6mm x 10.2mm) package. The low
drift and ultra-high linearity of theDAC73 provide
voltage or current output signals that are accurate'to
±0.OOO75% of full scale input range at 25"C ambi.ent.
The critical components including the curren!
steering switches. the temperature-compensaied
zener reference. and the precision laser-trimmed bit
resistor network are contained in a single ceramic
hybrid package.
The feedback and reference resistors are laid out for
maximum stability with low current density and
±IOppmj"C maximum temperature coefficient with

± I ppm "c tracking. This insures' very-low
superposition errors and low temperature coefficient
of gain.
The inputs are TTL-compatible CMOS and contain
level triggered latches in an 8-bii format 'for
microp'rocessor !lata bus ~ompatibility. No external
components ,are required to achieve full 16-bit
accuracy. Gain and offset potentiometers are also
included in the DAC73.
The DAC736 has electrical specifications identical to
the DAC73. but it is pin-compatible with the
AD1136. The input latches. bit adjust pins. ground
sense pin. and internal offset adjust pot are not
included.

Inlernatlonal AIIlIIirt Industrial Park, P,O. II1Ix 11400· Tucson; Arizona 85734· T81.1602I746-1111 ,Twx: 91(1.952·1111 . Cable: BBRCORP· T81ax: 66·6491,

'6-54

$PECIFICATIONS
ELECTRICAL
TA = +25"C and rated power supplies unless otherwise noted.

I

I

MODEL

I
TVP

MIN

I

MAX

J

MIN

I

TVP

I

MAX

I
I

UNITS

INPUT
DIGITAL INPUT
Resolution - CSB. COB
Logic Levels. ,TTL-Compatible CMOS,
Logical "1" 18t +1.0~A\
logical "0" lat -C.5mA I

16

Bits

+5.5
+1.5

VDC
VDC

±O.DOO75
±0.D2
±O.OS
±0.25
::to.S
±10
±1
±5
+35

% 01 FSRII)
%
%
%
mV
mV

:t24
:':22

ppm 01 FSR/oC
ppm 01 FSR/oC

~0.009

:':0.10S
:':0.099
:':0.024
:':0.022

:t4·

±10

%01 FSR
%01 FSR
%·01 FSR
%'01 FSR
ppm/DC

::0.5
:':2
:':1
:':1

:':2
:':5
:':2
:':2

16
+3.5
-0.5

+5.5
+1.5

+3.5 .
-0.5

,~R~NIIF!R_CI-\""""'_""'"''''''
ACCURACY
linearity Error at 25°C
Gain Error.I') Voltage CSB
COB
Current
Offset error,(2) Voltage. Unipolar
Bipolar
Current. Unipolar
Bipolar
Monotonicity Temp. Range 16 Bits lor K. 15 Bits for J

±0.005
±O.OI
±0.05

±0.0015
±0.02
±0.05
±0.25
±O.S
±10
±1
±5

±0.005
±0.01
±0.05

+5

±15

DRIFT lOver specified temp" ra~ge I
Total Drift I includes gain, offset. and linearity drift I
CSB
COB

Total Error over Temp. Range<3}
Voltage. Unipolar 'ooC to 700 e
Bipolar
Voltage. Unipolar 15°C to 35°C
Bipolar

:':9:5
:':9

:':24
:':22

:':0.043
:':0.010
:':0.009
:':4

±0.10S
±0.099
:':0.024
:;'0.022
±10

:':0.5
:':2
::1
:':1

:':2
:':5
:':2
:':2

±O.O40

Gain Exclusive of reference drift
Offset' Exclusive of reference drift,
Unipolar
Bipolar
Differential Linearity over Temperature
I

Linearity Error over Temperature,
SETTLING TIME
Voltage ,to ±O.DOO75% 01 FSR,
Output: 20V Step
1 LSB Step(4)
Slew Rate
Current ,to ±O.00075% 01 FSR •
Oulput: 2mA Step
COB Switching Transient Magnitude

±9.5

:':9
±0.043

'to.040
":0.010

50
6
IS

10

6
18

6

~A

°C

ppm
ppm
ppm
ppm

01
01
01
01

FSR/oC
FSRloC
FSRJOC
FSRJOC

jJ.sec
.usee
V/~sec

",sec
mV
V-",sec

6
800
0.45

SOO
0.45

COB Switching Transient Energy

50
10

~A

OU]'PUT
ANALOG OUTPUT

Voltage Output
Ranges - CSB
COB
Output Current -

o

o
o

to +5
010 +10
. :':IC
+4,
:':2

Unj~olar

Bipolar
Output Impedance. DC
Short Circuit Duration
Current Output
Ranges - CSB
COB
Output Impedance.-. Unipolar
Bipolar.
Compliance
: INTERNAL REFERENCE VOLTAGE

Maximum External Curren,tfSJ
Temp. Coelf.
OUTPUT _N_OISE
Current. COB
0.1Hz 1010Hz
10Hz to 100kHz
Voltage. COB. :':10V Range
O.IHz to 10Hz
10Hz to 100kHz

I

O'O~cominon 0.05

o to-2

0.03
Inc elinite

..

:':1
15
4.4
-1.5to+l0
5.990

+4
:':2

V
V
V
mA
rnA

O.OS

II

to +5
to +10
±2.5, ±5. ±10

:t25.

6.000

6.010

±4

:':10

5.996 .

o to-2

mA
mA

±1
'15
·4,4
..
-1.5to+l0
6.000

+4

kll
kll
V
6.010

+4
:':4

±tp

V
mA
ppm/DC

'1
4

1
4

nA. p-p
nA, rr'ns

10
70

10
70

"V. p-p
IAV, rms

6-55

I.
,....

CW)

c.:a

C

CI

ELECTRICAL (CO NT)
MODEL

DAC73J/DAC736J
TYP

MIN

STAB!LlTY. LONG TERM
pain r-Exelusivtt of· reference .•~ "-',"
,Offset COB I Exclusive of r~'!i'l'n~.~!,

. 'eSB

',"Reference

i:

.U.NI!S.

.

'ppm/103hr

±30

pI>;" of FSFI!

:1:5

:1:5

pp';~~h;SRj

+0.25

:1:0.25
±10

,103hr
lSBI103hr..
ppm/l03h r·

:1:20

. ±0.0001
0:0.0001

±0.0001
'!:O.OOOI

·>.b.of .FSR/'lI.Vs
'%offSR/%Vs

. ±0.0004
!0.0001

±0.0004
±O.OOOI

. % of FSR/% Vs
% of FSR/% Vs

!0.001
!0.0005

0:0.001
!0.0005

"

±15VDC
+5VDC

POWER SUPPLY REQUtREMENTS
: Rated Voltage
'Range
Supply Drain, ±15VDC no load'" ,
+5VOC logic supply

:~'

.·:!;3a~"

~10

.:POWER SUPPLY SENSITIVITY
~'Unipolar Offset
, ±15VOC
~. +5VOC
. Bipolar Offset
±15VOC
+5VDC

·.i'·.·

DAC73KmAC13SK
TYP
MAX

..

±3O

:t30

1\",,:

"linearity

'Gain

MIN

MAX

::15. +5

!15, :+5
=14,5, +-4.75

::15.1-5
+35 .. -45

.

+5.25
-1;50, -60

~15.5,

!14.5, +4.75

'!:,15.5,. +p.25
+50, -60

!:1S, +~
. +35, -45

9

% of FSR/% Vs
% of FSR/% Vs
VDC
VDC

rnA
·mA

9

TEMPERATURE RANGE
+-;0
: Spetification0
'70
°C
Storage
-55
·100
-.55
.c
,.100
".,'N~O~T~E~S~,- .....----...;;.._ _ _ _~-.L---'!"""..,..;L.i..--...1.----1-.....---II...;--...1....;;.---I-~---'
~1. FSR means Full Scale F.lang~ and is 20V for !10V range, 10V'f,or :!:5V range, etc.
2. A~just~ble to zero with inter.nal ~nm DotEm~iometer ,offset adjust'ment external on OAC736 •.
3, With gain and offset errors adjusted to zero at +25°C,

4. "LSB is for 1S-bit r.esolution.
5. Maximum with no degradation of specifications.

;I\4ECHANICAL
.DAC73

DAC736 ...
".:,.:

'"

-,

~IJ

NOTE.

leads

L..--

I

In

.NOTE
leads In tfL!e.
pOSition Within
:015" 38mm R
al,MMC at
seating plane

true

pOSition Wlthm
015'" .38mrn A
at MMC at
seating plane

2=1 ........... ,'1

i--umu mU IUIIIIUUUUUDU
T '.

"..JI..:.

"..J k- .

~r-H
. ; ..
C
;..................

!

:\1,

,
~.

"

......•

."

INCHES

'OIM

MIN

MAX

0"

.019

L

" ....

'I

Mitt
49.53

51.05
10.41

":021

DIM

.250

.350

rO.48'
0.53
2.54 BASIC
3.81

6.35

6.35

8.89

1.800 BASIC

46.72' BASIC"

.200 BASIC

,5.08 BASIC

.. ...

INCHES

MAX

·8.89

.250

0.50

""

~llLiMETERS

.410

.150

I

I

Pin numbers shown for
reference only Numbers
may not be marked on
package.

2:0~O

.;00 BASIC
K

I"

1.-, --l

.10033

3.950

1.950
.350 •

1

i

--lH

0

"

"

MIN

MAX

3.950

4.010

1.950
.350

2.010
.410

'~O1-9

·~.021·

MAX
101.85

49.53 . '51.05
8.89
0.48

. 0.53

2.548ASIC
3.81
6.:)5

.250
.350
1.800 BASIC

6.35
8.89
45.701 BASIC

0.50

6-56

MIN

.1008AS1C
150
.250

.200 8ASIC

3.81

MILLIMETERS
100.33

.150

5.08 BASIC
1.27

3.81

.~

,

PIN ASSIGNMENTS

CONNECTION DIAGRAMS

.n,

_IV!

'h'o

(Unipolar 0 to +10Y)·

0

,Nt

_lin

..

0
"13

w

a

,Hot

."'T"M"
.un
.UT3

• I lIT ,,111111

enIT2

• 3ItT 3
eUIT4

IOMu

eUIT4

• 'LATCH

."1T5
.,OllTe
.,UIT"

• 'lin

.'0I1U
• 11 lilt

5ku

.,1IIH

.

.,UllI

5kU

lIT 4AD,I5Ie

'"'"

• II liT II

DAC73

Precision
Hybrid

....{::

enl'Tl3
eUII"4

-.I,T,.
_2II1IT15

22MU
22Mn
22 u

• n"Tl0
·1111'"

."lItI!

II(~:U~=:

.ZllATeIl

16·BII OAC

.'UITt

ttT3ADJ'1 •
1111.11.1&1.
IIT'AIJ55 •

Il~:~:~

-nl,T'5

"".44e

.n~'

e .....

e •• llW

llIDUlOlllSEoe

-nllTli

A'POIIU'.

III'DUIIIIFF.'''.

g" ....

e".15.
e3l·'9

e3l-lIV

22Mu

.Alli::

e13I1T'3

eUIIT,.

."OIlU,.

IlI'OLA .. lfFlfT4II.

e"_

.34....

UIIjT ;FfSETAlIJUST

UIflr-WST

18 R d ' iL _'_8__-'-__- _ _ J
'inlemailinarily Adlustmenl Potll1llom.....

12kU

DISCUSSION OF
SPECIFICATIONS

t

r----+-~--J

+5VOC

VOUI

+

SkU

+15VOC

DIGITAL INPUT CODES
The DAC73 736 accepts complementary digital input
codes in CSB or COB format. The COB model may be
connected by the user for either complementary offset
binary (COB) or complementary two's complement
(CTC) codes (see Table I).

·15VOC

Common U .....- -..

To Pin 34

TABLE L Digital Input Codes.

(Blpolar±10Y)

DIGITAL INPUT CODES

+15VOC

~.....I..........,

.....,.,.,~_--1t7b-~::~~I!:O

'--+--~!D-.,- -15VOC
5kn

'"0
Q

..8
::!J

5kn

..;
til

U

Precision
Hybrid

CSB

....til

DAC736

Compl.
Straight
Binary

MSB LS'B

j

I

COB

CTC'

Compl.
Offset
Binary

Compl.
Two's
Complement

+Full Scale
-LFull Scale
-lLSB
All bits ON 0000 .. ,,000
Zero
0111..
'1/2 Full Scale
-Full Scale
Mid Scale
-Full
Scale
Zero
Zero
"'II Bits OFF
.. " I
'" I
-lLSB
1000
.. 000 Mid Scale-l LSB
'Full Scale

",

·In\"erl the !\iSH of the ('OK code with an external inverter to obtain cre I.'ode.

16-BIIOAC

INPUTS
Each bit input of the DAC73 consists of a buffered
CMOS D,type latch (see Figure 1). Bits I (MSB) through
8 are latched by a low level on pin 6_ Bits 9 through 16
(LSB) are latched by a low level on pin 21. The· latch
Inputs may be left open for transparent transfer of data_

l2kn

+5VDC

OAC73

6kn

10~ll

VOUI
Input

COmmon-I-++-H-+-/
OIgltll Input

FIGURE IO.Relationship of Offset and Gain Adjustments for a Unipolar D/ A Converter.

6-59

LINEARITY ADJUSTMENT
Internal
If it becomes necessary to adjust the linearity of the
DAC73 or DAC736 after an extended tirrie period oHor
operation under temperature extremes. the 4MSB's may
be user,adjusted. For optimum operation the unit should
be calibr~ted in its c;>perating environment. Calibration
is performed by a differential linearity adjustment at tbe
first four major carries. This method of calibration is
possible since the .DAC73 and DAC736 have .almost no
superposition error. The calibration procedure including
gain. offset. and linearity adjustll)ent is outlined' in Table
III. Steps, I and 10. may be omitted for linearity
adjustment only.

OUTPUT RANGE CONNECTIONS
Internal ~caling resist'o~s in the DAC73/736 provide
wide range of output voltage range connections. These
internai resisto'rs may be connected to provide"three
bipolar output voltage'ranges of±IOV. ±5V. or±2.5V or,
two unipolar voltage ranges ·of 0 to +5V or 0 to + IOV \
Since the internal scaling resistors are an integral part of
the DAC73 i 736. g!lin lind offset drift are minimized by
. their use .. Connections for DAC73 736 are shown in
Table II. Figure· II ~s a connection diagram.

a

TABLE II. Output Range Connections.
Digital
Co:nnect
Input Codes Pin 47 to

Output
Range
.!o10V
±5V
±2.5V
to +10V
to +5V

o
o

COB
COB·
COB
CSB
CSB

Connect
Pin 46 to

Connect
Pin 44 to

Connect
Pin 68 to

44

69
69
69
69
69

47
NC
69
NC
69

68
70
70
70
70

44
44
NC
NC

!;xternal(DAC730nlyj
The ,linearity adjustment of the first 4MSB's of the.
DAC73 may. ,bti accomplisned externally either with
potentiometers or with D/'A converters. Using a DAc to
adjust linearity will allow com'puter controlled accuracy
adjustments of the DAC thus giving the capability of
maintaining 16-bit' accuracy over all environmental
variations. Gain ami offset may also be adjusted in this
manner.
Eight~bit bipolar voltage output DAC's can be used for
all of the adjustments. Each circuit is shown in Figure 12.

In all cases pins 52 and 53 and pins 48 and 49 should be
shorted together with low. resistance capacitance
connections.

53

6tn .

0

w.----~:

"'No1r'4'-----O

,INSTALLATION CONSIDERATIONS
Tomaintain the extremely-high accuracy of the DAC73 .
and DAC736 when installed in a system environment.
careful attention must be paid to grounding .and to
connection resistances. Figures 13 and 14 are examples of
correct connection con-figurations to yield maximum
acc.uracy. The effectstif various wiring and conta,t
resistances. Rio R:. R '. and R, arc reduced or eliminated
as follows.
R, appears in series with the feedback resistance and
therefore introduces only a gain error that can he nulled
during calibration.
.

46

FIGU R E II. Output Amplifier Voltage Range Scaling
Circuit.

R:'is inside the output amplifier feedback loop and its
.
effect will be reduced h~' the loop gain.
In Figure.I3'forthe DAC736. R., is in series with the load

T ABLE III Calibration Procedure
DVM READING

STEP

HEX
INPUT
CODE

ADJUST
POTENTIOMETER'"

UNIPOLAR
MODE

'10VOLT
BIPOLAR MODE

DESCRIPTION

1

FFFF

RVs'2I

O.OV

·10.00OOV

Null Offset

2

FooO

N/A

V4

V4

Read Output Voltage

3

EFFF

RV4

V4 + 153,N

V4 + 305.V

Adjust RV4 until DVM reads V4 + 1LSB

4

EOOO

N/A

V3

V3

Read Output Voltage

5

DFFF

RV3

V3 + 305~V

Adjust RV3 until DVM reads V3 + 1LSB

S

COCO

N/A

V2

V2

Read Output Voltage

7

BF.FF

RV2

V2 :- 153~V

V2 + 305.V

Adjust RV2 until DVM reads V2 + 1LSB

V3 +

153~V

8

8000

N/A

9

7FFF

RV1

V1 +

V1

10

0600

RV5

+9.999~47V ,

153~V

V1

Read Output Voltage

V1 + 305.V

Adjust RV1 until DVM reads V1 + 1LSB

·+9.999695V ",

NOTES:.1. For potentIometer 10cI.tlon see Pin ASSIgnments. 2. Exte~nll offset adjustment on OAC736.

6-60

Adjust Gain

resistor and will cause an error in the voltage· across RI..
One-half LSB error would result at full load for R, =
O.0211. Therefore. if possible. sense the output voltage to
include R,.
Rll1!Ie: ±O.5mV Adjuslmenl Resolullon:

":4~V

Figure 14 illustrates the optimum connection made
possible by the ground sense pin on the DAC'73.1 n the
configuration shown R;, = R ,. and R;, II R" = R".-\{, II
R"l'o. This causes any signal developed across R., to be
rejected as a common-mode inpuI. and R .• will not affect
the voltage across RI.. This configuration will also reject
noise present on the system common.
R" is negligible in both circuits when ground connections
are made as shown.

(BIpolar Made)

GAIN ADJUST (Manual coarse adjusl.
requIred).
Range: +2fjLSB. -4LSB Resolullon: ±D. I LSB

~

~IOV

Sense
Outpul

>~------I®

Ral1!le

LINEARITY ADJUST IRepeallor each oIl11e bil adjusllnpuls).

FIGURE 12. External Accuracy Adjustment.

¢-~ ----- -- - --.Q-~- -- ----~

r

~f~

:I
I
I

cD

ii
I

:

kU
~

ROAC

'-----.

-

h

-

-

h_

--- -

RZ

!

15k!!
RB

'-

:~7

~>---rlU---''''''r-''

15ku

;

:-

-

;

34

~

+V

~

R4

h

--

lI

FIGURE 14. DAC'73 - ±IOV Bipolar Mode.

RL

~e~:eJoulPul ~

The DAC73i736 and the wiring to their connectors
should be located to provide optimum isolation from
sources of RFI and EML The'key word in elimination of
RF radiation or pickup is loop area. Therefore. signal
leads and their return conductors should be kept close
together. This reduces the external magnetic field along
with any radiation. Also. if a signal lead and its return
conductor are wired close together they present a small.
flux-capture cross section for any external field.

VL
~=-=::-I

~ 15VOC Supply I-T_OP_I_.-:30,..........._ _T_o_p_ln_Z_8-I+5VDC Supply

·v

~.,.

FIGURE 13. DAC'736- Unipolar Mode.

6-61

BU'RR-EIROWN® ,

'DAC74

IElElI

Self-Calibrating High Resolution True 16-81t
DIGITAL-TO-ANALOG CONVERTER

FEATURES

DESCRIPTION'

• 18-BIT RESOLUTION
• SELF·CALIBRATION MAINTAINS ACCURACY OF
±1/2LSB NONLINEARITY }
±O.OOO35% GAIN ERROR ' +15"& TO +45°C
±40~V OFFSET
• UNIPOLAR OR BIPOLAR VOLTAGE OUTPUT
• DOUBLE BUFFERED FOR AN II- OR 18-BITBUS

The DAC74 is a self-coniained true ,16-bit Digital-toAnalog converter designed for applications requiring
high resolution and accuracy such as displays.
frequency synthesizers. automated test equipment.
anaiytical instruments. and high resolution con'trollers. Furthermore, in applications where equipment
is inaccessible or frequent calibration is impractical
the DAC74 is ideal because the self-calibration
accuracy depends only on the long term stability of a
heated zener reference diode.
Using self-calibration circuits. the DAC74 maintains
typically ± I LSB total error oyer + 15"C to +45"C!
Compare this with other high resolution.converters
which can only maintain this accuracy over a ±2"C or
±3"C range. A patented microprocessor-controlled
differential measurement technique is the key contributor to the DAC74's drift performance: This technique allows use of low cost hybri!J and monolithic
circuiis to remove linearity. gain; and offset errors
resulting from ambient temperature varia\ions. component aging; and varying load conditions:'

DI8ITAl
IIIPUT

MEASUREMEIIT
CIRCUIT

This product is covered by Unit~ States patents4.222.I07 and 4.272.760. Other patents pendin!! may aJsoapply upun theallu".lI1cc illld i!\!_~==D~A~C~V~O~LT~AG~E~O~U~T~PU~Tt::t.:",g:t::R~Lh

"

A~.

0

Rva

0

C. _
~

UNIPOLAA ATN SENSE

RTN
RTN
..

~

'?'

·;OVR.F

,.'

.

~

"

1

...

CMRTRIM

+1OV REF

7

ATN

BIPOLAR OFr::
CURAENT OUTPut

20

23" A. DIS ill the MSB. l.ogic I is a high input logic level.

II

fNMSB

Enable fnrthedata input latches. Controls the MSB hyte latch and th.: 2nd latch in Ihcduublc-huffcrcd I.SD hylc.l.c\cI
triggered on high level.

12

DIGITAl. COMMON

IJ

RUN

('At

+SV supply return.
Control input. l.ow input for SEI.F-CAI.IBRATION mode, High input fur SERVICE. Ihl.' manual calibratiun mude.

14

MPU Off

Controls micrtlprocessor oscillator. Low ~ ON. High - OFF. Must he 10" fur SOm~cc ~fun:

15

RFS

Control input. Resets the DAC74 controller and suhse4ucntly cau!rIe:lo the RAM t'o.hc cleared and "calihratiun" ur
':service" to begin. Input is a logic 0 (low) pulse with 14",sl.'C minimum \\idth.

ii'"ES i!rl;'lsscrted.

16.17.18.19

DIGITAl. COMMON

+SV supply return.

20

CAr

Status OUlput. Inrorms the user if calibration failed. l.ogic 10\\ mcan!rl calihratiun !rIuL'ce!rlsful.

21

iRQ
RUN

Status Output. This i!l. high during the time the calibration controller has control of the main D At'ol1\erh:r.

23

KEY

This pin may be used to key the module to protect against incorrect plulo'-in alignment.

24

ENLSB

Enable input ror lSB byte latch. l.evel triggered on high lewi.

22

25 through 32 D14. D12. 010. 08.
06. 04. D2. DO

An internal microprocessor control input. Not used by user.

Data input to the main D A. DO is the l.SB. Logic I is high logic 'le\lcI.

3J

DIGITAl. COMMON

+SV supply return.

34

+SVI~

+sv supply input.

CONNECTOR P3 (Analog Connec:tor)
~.
1.2

NC

No connection.

3

-ISV1)Io,

-ISV supply input. Connected internally to pin 38.

4

+HV1)Io,

+ISV supply input.

5.6

ANAI.OG COMMON

Return ror ±ISV supply. Connected internally to pins 35 and 36.

7.8

RTN

A.n~log

UNIPOI.AR RTN
SENSE

Unipolar Return Sense. Analog load sense for unipolar output configuration.

10

BIPOI.AR RTN
SENSE

BipOlar· Return Sense. Analog load sense for bipolar output configuration.

II

CAL SENSE

Calibration Sense. A connection to sense the D A output at the load and prm ide an input 10 the error mea!rlurement.
circuit.

12
13

CURRENT OUTPUT
BIPOI.AR GA:IN

14

NC

No connection.

15

UNIPOI.AR OFFSET
TRIM (OFFSET DAC)

Connects an internal trim network to pin 16 for unipolar operation. This network is factory sel.·

16

OFFSET TRIM
(OfFSET DAC)

Offset trim input connection to the pedestal offset D, A converter.

17

UNIPOLAR GAIN
TRIM (OFFSET DAC)

Gain trim input connection to the pedestal offset D A converter for unipolar operation.

18

UNIPOLAR CAl.

A digital option line selt:Clina the soflware routine calibrating the main D A com'erter for the hipolar or unipolar
confisuration.

19

VOLTAGE OUT
(OFFSET DAC)

Analog output of the pedestal offset 0, A converter.

20

UNIPOLAR GAIN
(OFFSET DAC)

Connects the pedestal offset D A COR\o'ener for 0 to + 10V output range. Connect to pin 19.

21

BIPOI.AR GAIN
(OFfSET [)AC)

Connects the'pedestal offset D A convener for -IOV to +IOV OUIPUI Jangel Cmtnect to pin 19.

22

-lOV ..... OUT

-IOV precision rererence output.

23

-F.S. REF
(ALI. BITS OFFI
BIPOI.AR GAIN

Minu.s ~ull Scale input to analog switch of error measuremeittcircuit. Connect to pins 7, 8. 33.34 for unipolar. Connect
to pin 22 for bipolar.

DeSignation

~

Connect~

internally to pin 37.

return ror the analog output. Connected internall)' to pins 33 and 34.

A connection to the current output of the bit switches. Used to connl.'Ct Bipolar Offset, pin 29.
Connection to scale the output amplifier for bipolar output range (-10 to +IOV}and 10 provide a sense input lrom the

load.

24

Gain tri'm input connection to the pedestal offset 0 A

6·69

cO~\'ener

for bipolar o~ration. ('onnccr to

~in

2S.

Conru.-ction to provide preci~i(~n ,+ !~y 'rcfcren,~~ ~~o ,t~~
+IOV precision reterem.'c O U l p l ; l . < . "

!~.' ~ ",>un,\ ~rt,t.:r d~~uit~: <. 'nn~~'~:~,~t~ pin ~~:

25

+IOV RII IN

26

+IOV MH OUT

27

AIX' VOLTAGE IN
(TESTI

The analog output of the diftercm;e amplifier in the error mCI.I!\un.'l11cnt circuit.

28

UNIPOLAR GAIN

C~l~lleClion to scale. th.e.o~lpul an:tpljfi~r for .u~~p~)la.r tlI,ltput nU1~'C W to

load,"

,

"

:; ':

."

",

t 10,\') .and,lo pnnidc 11 !t\cn~c. inpullrumlhl'
,

.

. '

29

BIPOLAR OffSET

COnnCl.1s the bipolar on"ct current source to the currcnl output of the Illilin I) A l'UlI\crh.'" hi pnl\ ide hirwhtr nlhl.'t.
Connect to, pins 7. 8. ,U. 34 for unipolar. ('onncc~ I~ pin .12 fur hipul.u.

)0

J)AC VOLTAGE
OUTPUT

Analog voltage output of the main I> A conwrter.

31

+f.S. REI'
I AU. BITS ON I
CRM ·fRIM

Plus Full Scale input to analog switches of the error mea"Ufl!ml!rH circuit.
Connt.'Ct ~l pin 25.

32
33.34

Common-modI! rejl!(.1ion trim for the uutput amplific-r for bipular upl!fl.Iliun
('onnl.'Ct to pin.s 7.~. ,D . .14 for unipular. C,)nnl.'Ct h) pin 12 fur bipular.

unl~.

RTN
ANALOG C()MM(lN

Analog return for the analog output. Also conocl.1ed internall} to pin:'l 7 and H.

35.36
37

+ISV ....

+ISV supply input. ("unru:c..1ed internally 10 pin 4.

~ISVI'

-ISV supply input. ("unnected internally tn pin 3.

38

Return fur ± I SV supplic!'l.· ("onnt.-ctcd internally

39

. +12V·TEST

Test pin for internal +12YU(',

40

·12V TEST

Test pin for internal-12VUC

Itl

·pin:'l 5 a.ild 6.

INSTALLATION
The three connectors described in the previous section
have three. separate functions: analog interface. digital
interface. and the terminal interface. The terminal interface is used only for factory lest, Connectiol) to a printed
circuit board can be made using female printed-circuitmounted connectors supplied with the DAC74. They
should be positioned relative to the. fou{ internallythreaded mqunting holes at the corners of the DAC74 as
shown in Figure 4. Mount the DAC74 with four #6
external tooth lock,washers and four #6-32 screws using
0.156" diameter holes. Be sure to leave clearance for
screwdriver adjustment of the trim potentiometers.
Alternatively. the DAC74 can be mounted on a chassis
with the connectors facing upward using two #6 lock-

washers and two #6-32 sc·rews· by means of ·the two
internally-threaded holes near the center of the DAC74 as
shown in. Figure 4. In this orientation,. connection to
ribbon cable can be made with mass terminated. female.
flat cable connectors (3M. 3421-0000. 3414-0000. 34170000). Ind·ividual wires may also be connected to the
DAC74 in this orientation using female wire-app,.Iied
connectors (AMP 1-87456-6.3-87456-0.3-87456-6 housings plus appropriate crimp snap-in pins), In either case.
the jumpers for the unipolar or the bipolar. configuration
should be made right at the analog connector P2 as
described i~th; fOUowingparagraph. The potential drops
due to long jumpers cause a degradation in the accuracy
of the calibration circuit.

7.0lI0'
U75' _ _ _ _ _1;.. 17-:-7._"'.;;...1~
. .....' .
(111.93I11III1
.4.150"
------·101.4111111

2.837'
(72.11IIIIIIII1

s.1IOII"
(127·0IIH1

5.375'·
(138.53IIIml
.L.....-I--'---"'-~ -$-_fI.32tllrlld (lhrul
(2 PLI

,...;.-----==----,---,--'--'--,rr-----I+----....." . .

fl.32111r1ld
11.188' min dlplh

(4PlI

11.438-

(11.13111111

FIGURE 4. DAC74 Package Mounting Hole Locations.

·6-70

POWER SUPPLY CONNECTIONS
A typical configuration is shown in Figure 5. Regard less
of the local grounding. bring two separate return lines
from the common near the power supplies to the DAC74.
Connect one to Digital Common and the other to Analog
Common. The load return line should be connected only
to RTN (pins 7. 8. 33. 34) on P3 as shown in the unipolar
and bipolar Connection Diagrams. Other connections to
local grounds should be made with caution as they may
cause ground loops which induce undesirable voltages at
the common return points. The case is tied internally to
Analog Common. Normally it should not be connected to
any local grounds. Besides the power supply connections.
other connections to the DAC74 should be limited to the
digital inputs with a single digital current return and the
5-wire connection to the load. The external connections
should be made so as to minimize theconduction paths to
external noise sources. Internal bypass. capacitors are
included in the DAC74; no other bypass is needed nor
recommended.

Precautions
I. Provide all three grounds before applying \olutge
to either the power supply inputs or the signal inputs.
2. Avoid static discharge during handling and installation.
Store the DAC74 i.n a conductive package.
.
3. Usc short pairs of wire close together to mini mile
electromagnetic pickUp.
In very noisy environments. separate floating supplies
may be needed to power the DAC74. These supplies and
their common returns should be connected only to the
DAC74. Some experimentation with extra shielding and
alternative return configurations may be necessary in
'extreme circumstances.

OUTPUT CONNECTION
The output connection for unipolar and bipolar operation
are shown in the Connection Diagrams. For either
unipolar or bipolar. it is very important to provide both a
current-carrying wire and a sense wire to both sides of the
load in order to minimize the errors caused by induced
potentials and losses in the wiring to the load. The·fifth
wire. CAL SENSE. returns the output voltage at the load
to the error measurement circuit. In a noisy environment
these wires should be enclosed in a shield that is connected
only to the RTN pins ofthe DAC74. The return line from
the load to the RTN pin of the DAC74 must be separate
from other grounds in order to avoid potential drops due
to shared current paths. The resistance of this path must
be low so that the voltage drop is less than 20j.lV. For
example. at SmA one foot of 16-guage copper wire
(4!l/ lO00ft.) produces a 20j.lV drop.

The power supply voltages may be se4uenced on or otT in
any order provided that the power supply inputs haw no
transient voltages of polarity opposite to the normal DC
input with respect 10 Analog or Digital Common.
The power supply re4uiremel1ls arc listed bCto",. During
power-up. an initial surge of 400mA is re4uired by the
+15V supply input.
Input Voltage

+5V

+15V

-15V

Current, max
typ

800m...
SOOm...

200m...
150m...

200m ...
150m...

TO PIli 131BlPOLAR BAIl)
OR PIli 281U1IPOLAR SAil)

TO PIli II !CAL SElBE)

VOLTAGE OUTPUT

DIIITAL
COMMOII

TO PIli 10 IBIPOLAR R11I BEII3E)
OR PIli 91UIIIPOLAR RTII SEIISE)

TO PlN4

+15VOC---------.

COM

TO PIII3

·15VDC

TO PIli I

+5VOC

±15VIIC

SUPPLY

+5VDC
SUPPLY

COM

FIGURE 5. Power Supply and Common Connections.

6-q}

5

:i

Unipolar Connection. T~e o~tput c?nnection~ and'jumper~ are listed .below. Th.e plr)n~nl'?~.r.'"reli:r to the ani,llog,
connector pJ. The first five connectIOns constitute the 5-wlre connectIOn to the load.' .
"
.
"
Connection
30 to load (top)
28 to

loa~

(top)

7 to load (bottom)

9 to. load (bottom)
II to load (top)
33 to 6

23 to 34
29 to 34
. , 1

26 to 25 .
15 to 1(1
17t025
',' 19 to,20

Purpose
DAC VOLT AG E OUTPUT
Output connection to the ioad.
UNIF'OLAR GAIN
Output sense to 'the inverting input of the outp!ltamplifier. 'Sets unipolar riln:g~,
RTN , .
'
'.'
Current return from the load. This retqrn impedance must be low,- equivalent of
16-gauge wire.
UNIF'OLAR RETURN SENSE' ,
Return sens'e to the ~oninverting input of the tlUtput amplifier.
CAL SEN,sE
, I npl\l tC!the error measurement circuit from the load.
RTN TO ANALOG COMMON
Connect com!]1on returns. Thisjumper is esscntialto prcvcnt dam.ige to the internal
reference.
-F.S.REF (ALL BITS OFF)
Set minus full ~cale to 0 volts. Keep as short as possible.
BIF'OLAR OFFSET TO RTN
Maintain the same current drain on the + I0' volt refercnce as' bipolar connection .
+I0V REFOUT TO +IOV REF IN
Keep as short as possible.
UNIF'OLAR OFFSET TRIM TO OFFSET TRIM
Connect offset trilil to offset adjust input of the pedestal offset () A con\'erter.,
UNfF'OLAR.GAiN TRIM (OFFSET DAC) to +10 VOLl'REF
Connect the full scale gain reference of pedestal offset D A converter..
VOL. TAGE OUT (OFFSET DAC) output to UNIF'OLAR GAIN (OFFSET PAC')
Return sense to.inverting input of the pedestal offset D A converter:

18 to digital common

UNIF'OLAR CAL to DIGITAL COMMON
Set software to unipolar mode.

31 to 25

+F.S. REF to +IOV REF IN.

Bipolar Connection: The output connections and jumpers for bipolar operation are listed below. The pin numbers
refer to the analog connector 1"3. The first five connections constitute the 5-wire connection to thc load.
Connection
Purpose ,.
30 to load (top)
13 to load (top)
7 to load (bottom)

10 to load (bottom)

DAC VOLTAGE OUTF'UT
Output conne!=tion to the load.
BIF'OLAR GAIN
Sense to the inverting input of the output amplifier. Sets bipoiar range.
RTN
, Current return from the 19ad.This return impedance must be low - equivalcnt of I foot
, 16-guage,wire for 5mA output.
BIPOLAR RETURN SENSE
, Return sense to the noninverting input of the output amplificr.

I J to load (top)

CAL SENSE
Input to the error measuring circuit from the load.

32 to 7

CMR toRTN
Match the equivalent impedance to RTN for both inputs of output amplificr for the
bipolar configuration.

7,8,33,34

RTN
Tied togethe~ internally.
RTN to ANALOG COMMON
Connect common returns. This juniper is essential to prevent damage to the internal
references

33 to 6

Connection
23 to 22
29 to 12
26 to 25
16 to 25
24 to 25
19 to 21
31 to 25

Purpose
-F.S. REF(ALL BITS OFF) to -IOV REF OUT
Set minus Full Scale to -10 volts. Keep as short as possible.
BIPOLAR OFFSET to CURRENT OUTPUT
Bipolar offset for output amplifier.
+IOV REF OUT to +IOV REF IN
Keep as short as possible.
OFFSET TRIM (OFFSET DAC) to +IOV REFERENCE IN
Connect bipolar offset of the pedestal offset D; A converter to + IOV REF.
BIPOLAR GAIN TRIM (OFFSET DAC) to +IOV REF
Connect the Full Scale gain reference of the pedestal offset D, A converter.
VOLTAGE OUTPUT (OFFSET DAC) to BIPOLAR GAIN (OFFSET DAC)
Return sense to inverting input of the pedestal offset D, A converter.
+F.S. REF to +IOV REF IN.

Internally Connected Pins. The following pins are connected internally:
Function
Pin No.
DIGITAL C;OMMON2, 12, 16. 17, 18,19.33
1,34
+5Vn,
ANALOG COMMON
5.6.35.36
+15Vls
4.37
-15V1s
3.38
RTN
7.8.33.34
plGITAL INPUTS
Data inputs DO - DI5 and enable inputs. ENMSB and
ENLSB. are low power Schottky (74LS373). Control
inputs REs: RUN/CAL and UNIPOLAR CAL are
standard TTL inputs. M PUOFF is a standard TTL input
with a 10k!! pullup resistor connected to +5V volts.
. Timing specifications on the digital inputs are listed in the
Specifications table and discussed· in the Operation
section.

OPERATION
DAC74 data inputs. control signals. and status lines are
usually be tied to
shown in Figure 6. MPUOFF
DIGITAL COMMON permitting the internal crystal
ocsillator to run continuously. However. one may wish to
control the oscillator to remove all possible sources of
noise during D/ A converter operation. MPUOFF must
be asserted low SOmsec before the REs pulse is asserted.
The
line resets the calibration controller and starts
controller operation when it returns high after being
asserted low for at least 14",sec.
RUN/CAL isamodecontrolline. When high. RUN/CAL
enables the controller to set up the SERVICE mode. In
. this mode, the user performs a coarse m!!!!!!1 adjustment
of the D/A converter. When RUN/CAL is low. the
controller is ,informed to set up the SELF-CALIBRATION mode. the normal mode of ~peration. .
Data input latches are level-triggered by ENSMB and
ENLSB. These are used to strobe-in data from an 8-bit
bus with DO through D7 connected to D8 through DI5

will

respectively. For l6-bit bus operationENLSB can be
permanently connected to +5V. Since all three latches are
octal transparent latches (74LS373). their inputs may be
transferred directly to their outputs by setting their
respective enable inputs high. The table below indicates
four common interfaces. A high input refers to a logic I
input (2V to 3.5V) and a low input refers to a logic 0 input
(OV to O.8V).

Mode

ENMSB

ENlSB

Description

Transparent

High

High

I(>obit

Positive

Hish

Inputs are transferred directly to the
MAIN DI A convener.
All 16 bits are latched at the end of the

interface
8~hll

Pul..
low

interface
B-bit

interface

Positive
\ Pulse

ENMSB pulse.

Positive
Pulse

Capture 8lSB's from the data "bus in
low byte buffer.
"Transfer 8MSB) from the data bus and
transfer latched BlSB's to the MAIN
D. A converer at the end of the pulse.

m

6-73

The three-state output in the second rank of latches is
disabled by R'UN. a status output signal. during the time
the calibration controller has control of the main D/ A
converter.
INITIAL SETUP
It is necessary to trim the +IOV and -IOV reference as
close to IOV as possible using the potentiometers located
at the edge of the module. The procedure is described in
Manual Calibration section.

It should not be necessary to manually adjust OFFSET.
GAIN, and LINEARITY on units received frotn the,
factory. However. after a year or mor~of operation it may
be necessary to adjust these parameters ;to within the
range which can be trimmed by the self-calibration
circuits. The manual adjustment procedure is described in
the Manual Calibration section. It is important that either
the load be connected or that a d,ummy load be switched
in during calibration or adjustment.
"

Self-Calibration Mode
After power-up; a 1/2-hour warm-up period must be
allowed. This permitsihe heated zener reference and
other critical circuits to stabilize.
The next step is to initiate the SELF-CALIBRATION
routine. Self-calibration is initiated by providing a pulse
(low. 14Jlsec min) from the host equipment to the RES
line. Self-calibration typically takes 2-1/2 seconds. CAL
and RUN inform the user on the internal status of the
calibration controller. The operation of these is best
explained by a timing diagram. Figure 7.
Upon application of the reset pulse. CAL goes (or
remains) low and goes high about IOOJlsec after RE'S is
returned high. CAL remains high for 500Jlsec maximum.,
If it remains high. self-calibration has failed. If it goes low.
self-calibration will be successful. The fact that calibration
has failed means that either a noise transient has interferred with system operation or that the maximum
correction factors have, been used and that the main 0; A

converter connot be corrected to within speCificailon.
Howevei. tHe converter will still operate. It will be
necessary to perforin in.anu~1 adjustments described in
the Manual Calibration section.
R UN,goes high about IOOJlsec after the RES pulse returns
high and remains high until all calibration controlh;r
operations are complete and control of the main D, A
convertt;r is returned to the digital data inputs, It is
important to be aware \>ftwo facts during self-calibration:
(I) the main D, A converter is being exercised. its output
is moving and changing the voltage on the load; and (2)
the three-state output enable of the main D A converter
input bitches IS held high by R1JN thereby disconnecting
the data inputs from the main D A converter.

Service Mode
Before one can manually adjust the GAIN. OFFSETand
LINEARITY of the DAC74. it must be put in a mode
called the SER".!f], mode. This is accomplished by
~hing RUN/CAL high and asserting a pulse on the
RES line. The 'result of going i'1to this mode, is that all
corrections in the RAM ,are set to zero before control is
returned to the user data input lines.
The timing is illustrated in Figure 7. CAL does not return
low as it did in the SELF-CALIBRATION mode but
remains high. Ri:iN returns low indicating that control
has been returned to the data inputs. RUN time is ab~ut
300msec. Manual calibration may proceed as described in
the Manual Calibration section.

--

015(1881

I---

I

I

LATCN 74lS373

I
I
I

D8

".

or

EN

~

E.I..
flUB

MAIN BIA CONVERTER
~

07
I
I
I
I,

DD(L88l

,-

I

I

EN

DE

LA TeN 74lS373

i:-

or

EN

LATCH 74lS373 ,

I---

f---

RUN/CAL

IES

.

'

lPUOfF
RUN
CAL

FIGURE 6. OAC74 Inputs:.

1

+5V
1111111

--

I
~----~\

lr -------------------------------------

HI

I

I--:-:-'RES

--l ___

14~1IC.lllft

,

'do .
I..".... I"

I

,
,1

RUI

-,,

'cAL

1iIIIi~ ...

I
I

I

,,

"'I
:--IIIInIIC.IYP

I

I

,I

_I

RUIJCiL...

l ..

~,.
-I

'RUN
311c.1IIl

M'UOFfID.

FIGURE 7. Self-Calibration Mode Timing.

REI

)r

I

I

~--------~~

.---'REa~
14~1IlI

RUliCAib\glJ
MPUOFfIaw

FIGURE 8. Service Mode Timing.

I

MPUOFF
I
~c..:--____"'"'\~

--J~~---------~--------------~------------------~--~------

iii

-

I

IiOIIAc. ilia

,
I

~---------------\

{

~IR£I
~
14...... 111.
,

,.

,1
.-.I
; - 1iIIII.......... ,

i,
FIGURE 9. Control Timing Diagram.

6-75

'\,......-----------------------

,Full Automatic Control
If the user wishes to automatically control the total
operation of the DAC74 including the SERVICE,mode.,
as well as the SELF-CALIBRATION mode, additional
, timing considerations apply. An additional timing diagram is shown in Figure S. Note that the M PUOFF must
is asserted and the
be asserted low SOmsec before
RUN/CAt. must be asserted within 500l'sec'ofthetirtle
that the RES pulse returns high.

rn

MANUAL CALIBRATION
Manual adjustment of the DAC74 is accomplished by
eight potentiometers located at one end of the package.
Space for screwdriver access must be provided on the
mounting surface. A label marked "REFER TO MANUAL BEFORE REMOVING LABFl. "must be removed
from the end,ofthe Pllckage to access the potentio~(!ters.

, p,~\ the l)AC74 ilJtQ lhc..SEI{YJCE mnd..: u,s,d ..:s,'rined,in
,the Service Mode section.
Adjustments will be made in the follllwiqg order: OFFSET, preliminary GAIN. 4MS8's (LI!'I:EARlTY). and
final GAIN. Output voltage readings will be different fill'
bipolar and ,unipolar cilOtigurations. Table I shows the
data word to be strobed into DAC74. the potentluOlet.:,.
to be adjusted. and the output reading tp b.: alt,iined Ii),.
unipolar and bipolaT configurati()ns. ' "
, Afte~ these adjustments are made, put the DAC74 in the
SELF-CALIBRATlON mode as described in the SelfCalibration Mode section. The DAC74 is now ready for
normal operation:
TABLE I. Calibration Voltages.
Dilta Input

10V Reference Adjustment
After the DAC74 has been installed, the load connected,
and a 1/2-hour warm-up period has elapsed, the references may be adjusted. The reference voltages should be
set to IOV, ±IOpV.

Step

A 6-1/2 digit yo It meter, which has been calibrated as
accurately as possible may be used to adjust the reference
and coarse calibrate the D/ A converter.

Adjust

Word Ihex! . Poteniometer

1
2
3
4
5

0000
0800

6

8000

7

FFFf

1000

2000
4000

OFFSET
GAIN
012
013
014
015
GAIN

01 A Output Reading'
Unipolar"

Bipolar

O,OOOOV,±50~V

-10,OOOOV,±I00~V

O,3125V.±50~V

-9.3750V,±100~V

O,6250V,±50~V

-8,7500V,±100~V

1,2500V ,±50~V

77,5000V,:t.l00~V

2,5000V,±50~V

-5,OOOOV,±I00~V

5,OOOOV.±50~V

O,OOOOV.±I00~V

9,99985V,±50~V

'-9,9$97V,±I00~V

OPERATIONAL CHECKLIST

ADJUSTMENT PROCEDURE
I. Connect the voltmeter between the +IOV REF OUT
pin (26) and anANALOG COMMON pin(S,6,3S:36).
Adjust the +IOV REF potentiometer to obtain a
reading of 10.OOOOOV, ±IOI'V.
2. Connect the voltmeter to 'the -IOV REF OUT
pin (22) and adjust the -IOV REF potentiometer to
read -IO.OOOOOV, ±IOI'V, Needed for bipolar only.
Note: If these reference voltages are to be used to provide
references to vther circuits, those loads must be connected
before the above adjustments are made. External reference loads must remain constant for accurate operation
of the DAC74.
Coarse Calibration of the Main D/A Converter.

The self-calibration controller can correct main D/ A
errors within a limited rarige.lfthe gain, offset or linearity
shift due to initial installation environment, such as load
return wire voltage drops, power supply voltage line
regulation, or component aging, a manual coarse adjustment will be necessary. These six adjustments are made
using potentiometers at the edge of the DAC74 package.
Coarse adjustments bring the errors of the DAC74 to
within the operating range of the self-calibration circuit.
It is sufficient to adjust the DAC74 output to within
norminal values.
'
..
ADJUSTMENT PROCED'URE
After the DAC74 had been installed, the load connected.
a 1/2-hour warm-up period has elapsed" and thie reference
voltages have be'en set, manual calibration may proceed.

I. Be sure that all pins and jumpers arc connected properly as discussed and illustrated in the Installation
section'. Carefulillyout and shielding is necessary ttl
keep digital noise ().ut of the analog circuits.
2. The load return line from the load to RTN ('pin 7.1'.1)
must have less than 201' V voltage drop across its
length for proper operation. See Installation section.
3.se sure and wait about I 2-hour for warm,up.
4. Check power supply voltages at the module pins.
+ISV and -15V, ±O.SV
+5V, ±0.25V
S. Check +12V and -12V voltages generated internally.
+12V. ±0.6V pin 39.1'.1
.
-12V, ±0.6V pin 40.1)3
6. Check +IOV and -IOV references. The D A converter
accuracy is directly dependent on fhese voltages. See
Adjustment Procedure in the Manual Calibration
section.
+1O.00000V, ±IOI'V pin 26,1'3
-IO.OOOOOV, ±IOI'V pin 22,P3
7. Check MPUOFF (pin 14, P3) to be sure it is low. It
'.must be low for at least 50msec before attempting'
self-calibration.
S. Be sure ~U~N~I;:PO~L"":'A~R~C~A~L (pin IS.P3) is high for
bipolar operation or low for unipolar operation.
9. ~pulse must be at least l4/,secwide.
10. IfC AL status does not return low during an automatic
'" self-calibration;the D / A converter may be out of
tolerance. Adjust it using the procedure in the Manual
Calibration section. An unsucc,essful self-calibration
can result from a voltage or current transient in the
D / Acc;>nverter systein, Au~mpt a second, selfcalibration.

DAC80

BURR-BROWN®

IE:lElI

Integrated Circuit
DIGITAL-TO-ANALOG CONVERTER

FEATURES:

DESCRIPTION

• WIDE POWER SUPPLY RANGE MODELS
AVAILABLE IZ MODELS)
• 12-BIT. 3-DIGIT RESOLUTION
• ±II2LSB MAXIMUM NONLINEARITY
• COMPLETE WITH INTERNAL REFERENCE
AND OUTPUT AMPLIFIER IV MODELS)
• FAST SETTLING :.3oonsec to ±o.ol%
(I MODELS)
• CERAMIC DUAL-IN-LiNE PACKAGE
• LOW COST

Use this popular 12-bit digital-to-analog converter
for low cost precision performance applications.
DAC80. with internal reference and optional output
amplifier. offers a maximum nonlinearity error of
±O.OI2%. ±30ppmj"C maximum gain drift. and
monotonicity - all over a onc to 70"C operating
range. In the bipolar configuration. total accuracy
drift is guaranteed to be less than ±25ppm("C. Select
TTL compatible complementary 12-bit binary (CBI)
or 3~digii BCD (CCD) input codes.
Packaged within DAC80's 24-pin duaHn-line
ceramic case are fast-settling switches and stable.
laser-trimmed thin-film resistors that let you select
output voltage ranges of ±2.5. ±5. ± 10. 0 to +5. 0 to
+10 volts (V models) or output current ranges of .
± I rnA or 0 to -2mA (.I models). Voltage output
models settle to ±0.OI0e. of FSR in 31'sec fora lOY
step change.

VOLTAGE MODEL
6.3V REF OUT
GAIN ADJUST
+VI

.....
!;
i!

;

COMMON

By specifying the DAC80Z 'model with a supply
range of ±ll.4V to ±16.0V, you can use this proven
D/A converter in microprocessor and semiconductor memory systems.

SUMMING JUNCTION
20V RANGE
IOV RANGE
BIPOLAR OFFSET
REF INPUT
Voul
-VI

LOGIC SUPPLY

Inlernatlooal Alrporl Industrial Park - P.O. Box 11400 - TUClon. ArizlJna 85734 - Tel. 1602) 746-1111 - Twx: 91M52-1111 • Cable: ,BReORP - Telex: 66-8491

6-77

SPECIFICATIONS
Typical at 25°C and rated power supplies unless otherwise noted

ELECTRICAL

.....,.. :
OACSOCBI

MODEL
MIN

OAC80CCQ.
MAX

TYP··.

DIGITAL INPUT
Resolution

MIN

TYP

MAX

UNITS

3

Bits
Digits

12

Logic Levels ITTUCompatible)(ll
Logic "1" 1+40~A max at +5.0V,
Logic "0" (1.6mA max at +0.4VI
ACCURACY
Linearity Error at 25°C
Differential Linearity Error
Gain Error(2)
Offset Error(2)
Monotonicity Temp. Range. min

+5.0

+2.4

o

+0.4
±1!4
±1/2
±0.1
±0.05

±0.08
±O.08
±15

LSB

±1/4
±1/2
±0.3

±a.05

±a.15

LSB
'!Io
'!Io of FSA(31

+70

·C

±25

ppm of FSA/·C

±a.15
±a.12

% of FSA
'!Ioof FSA
ppm!·C
ppm!·C
ppm' of FSAJOC
ppm of FSA/·C
LSB'
(SB

o

±0.15
±0.12
±30
±10
±3
±15
+1. -7/8
±1!2

±1
±7
±1!2

±0.08

±a.os
±15
±1
±7
±1/2

5
3

5
3

1.5

1.5
20

~O

10

10

300

300

1

1

±2.5. :1:5. ±10. 0 to +5, 0 to +10
±5
±5
0.05
Indefinite to Common

'I

I

±1. Oto-2
4.4
15

w

~sec

nsec
,",sec
Volts
mV
ohms

0.05

±2.5

±200
±20

±10

Volts
~A'

±;W

ppm/·C
'!Io of FSAI% Vs
% of FSAI% Vs

±a.OO2

±15, +5
±12. +5

±16, +16
±16. +16

±25
+20

±35
±3O

o

+70
+85
+100

-25

-55

±14, +4.75
±11.4, +4.75

mA
kO:
kO
Volts

±200

±a.02

:1:0.02
±0.OO2

NOTES:
1. Adding external CMOS hex boffers CD 4oo9A will provide CMOS Input
compatibility.
2. Adjustable to zero-with external trim potentiometer.
3. FSA means"F~II Scale 'Range" and is 20V for ±10V range, 10V for ±5V
range. etc.
4. To maintain drift spec internal feedback, reSistors must be used for
current output models.

~ec

VI~sec

+6.3

±10

:!:14. +4.75
±11.4, +4.75

psec

OtO·+l0

±2.5

POWER SUPPLY SENSITIVITY
+15V Supply
-15V and +5V Supplies

±3O
±10
±3
±15
+1, -7/8
. ±1/2

Oto-2
4.4
.15

+6.3

tNTERNAL REFERENCE V.OLTAGE
Maximum External Current(8)
Tempco of Drift. max

TEMPERATURE RANGE
Specification
Operating I double above specs I
Storage
.

VDC
VOC

±1/8
±1/4
±0.1

±25

ANALOG OUTPUTII model.
RBn,ges
Output Impedance - Bipolar
Output Impedance Unipolar
Compliance

POWER SUPPLY REQUIREMENTS
DACao
DACaoZ(7)
Supply Drain
±15V/±12V (including 5mA load I
+5V (logic supply I

±a:15

+0.4

.

CONVERSION SPEEDII mode,s - of FSA
Sen/ing Time to ±0.01'!1o
For FSA Change
100 to 1000 Load
lkO Load
ANALOG OUTPUTIV models
Aanges(7)
Output Current
Output Impedance lOCI
Short Circuit Duration

±q.3
+70

DRIFT(" (O·C to + 70·C I
Total bipolar drift. max I includes gain.
offset, and linearity driftsl(S)
Total error ovet OOC to +700 C(8)·.
Unipolar
Bipolar
Gain
Exclusive of internal reference
Unipolar Offset
Bipolar Offset
Differential Linearity O°C to +70°C
Linearity Error OOC to +700 e
CONVERSION SPEEDIV models
Settling Time to ±O.o1'!1o of FSA
For FSA Change
with 10kO Feedback
with 5kO Feedback
For lLSB change
Slew Aate '

o

±1/2
+1"-3/4

o

+5.0

+2.4

±15, +5.
±12. +5

:t16. +16
±16. +16

±25
'+20

±3O

±35

o

. +70

-25

+85

-55

+100.

: VDC
VDC
mA
mA

·C.
·C
·C

5. See "Computing Total Accuracy Over Temperature."
6. With gain and offset errors adjusted to zero at 25°C. ~ee discussion on
last page.
7. DAC80Z supply range is ±12.0V min to ±16.01l mill' for 0 to +10V and
±10V outputs.
.8. Maximum with no degradation of specifications.

6-78

CONNECTION DIAGRAMS
VOLTAGE MODEL

CURRENT MODEL

10k!!
to

lOOkl2
-Vs

10k!!
to

lOOk!!

+Vs

. MECHANICAL

NOTES:
1. 3kO for CCO modols, SkO for CBI modols.
2.11 connected to+Vs.which is permissible,power dissipation increases 2OOmW.
3. CBI model, 2kO;
model. on and pin 20 has no internal connection.
4. 6.3ktl reSistor internally grounded on ceo models.
S. ReSistor required only for Z models. see "Operating Instructions".
Make no connection to power supply on non-Z models.

ceo

000000000000

,4

Pin numbers shown
tor reference only.
Numbers may not be
marked on package.

n

PIN ASSIGNMENTS
I Models

Pin
No.

(MSBI Bit 1
Bit 2
Blt3

Bit 4
BitS
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
(LSB) Bit 12
LOGIC SUPPLY
-Vs
lour
REF. INPUT
BIPOLAR OFFSET
SCALING NETWORK
SCALING NETWORK
SCALING NETWORK
COMMON
+Vs
GAIN ADJUST
a.3V REF. OUT

V Models
Bit 1 (MSBI
Bit2

3
4
5'
a
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

81t,3

NOTE:
Leads in true position within .OlO~ 1.25mmlR at MMC at aBating plane.

Bit4
BitS
Bit a
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12 (LSBI
LOGIC SUPPLY
-Vs
Vour
REF. INPUT
BIPOLAR OFfSET
10V RANGE
20V RANGE
SUMMING JUNCTION
COMMON
+Vs
GAIN ADJUST
6.3V REF. OUT

INCHES

DIM
A'

c
0
F

G

MAX

MIN

MAX

1.310

1.360

33.27

34.54

.710
.150
.018

.810

19.56

20.57

.210
.021

3.81

5.33

0.46

0.53

.035
.060
.100 BASIC
.110

.150

I·

.130
·.250

.600 BASIC
N

MILLIMETERS

MIN

1.27
2.54 BASIC

0.89

2.79

3.30

3.81
6.35
15.24 BASIC

.002

.010

0.05

D••

.105

2.16

0.25
2.67

CASE: Ceramic
MATING CONNECTOR: 245MC
PIN: Pin material and plating composition conform to
method 2003 (solderability) of MIL-STD-683 (except
paragraph 3.2).
WEIGHT: 8.4 gram. (0.3 oz.)
HERMETICITY: Conforms to mothod 1014 condition C
step 1 (fluorocarbon) of MIL-STD-883 (gross leakl.

6-79

, DIGITAL INPUT CODES
The OAC80 accepts complemenfary digital input codes
, in either binary (CBI) or decimal (CCO) format. The CBI
model may be connected by the user,for anyone of"three
cpmplementary codes: ;CSB, CTC or COB.

TABLE'I Oigitallnp~t Codes
DIGITAL INPUT

0

a;

MSB

LSB

0

000000000000'
011111111111
100000000000
111111111111

..,.!!.

MSB

."

0

:;;

iii

0,

ANALOG OUTOUT

LSB

COB
,Compl.
Offset
Binary

CSB
Compl.
Straight
Binary

+FuilScele,
,Zero
-lLSB
Mid-scale :lLSB
-Full Scale,
Zero
+FuliScale .

'+1/2 Full Scale

C;TC'
':Campl.
Two's
Compl.

al 2SoC and "is divided·by the temperature.. range. This
drift is expressed, i;n.' plI.rt,s, per million of full scale range
per °c (ppm of FSR/"C).
SETTLING TIME
Settling t,ime for ea!;h ;0';\<:86 rno.del is the total time
(including slew time) require4for the output' to settle
within an errOr band a-rpund its finalvafiie after,a change
in input (see Figure 1'),'
'
,

-LSB
-Full Scal~
-Full Scal.
Zero

CCD
Complementary Coded Decimal - 3 Di!!it•

:;;
0

0
0

011001100110
111111111111
• Imert the MSB of the

+Pull Scale
Zer9
~B

code with an external inverter to obtain

(" I C code.

0.01 RL =
10nID
lOOn

ACCURACY,
,
'
Linearity ,of a O,/A converter is the true measure of its
performance. The lineaiityerror, of tM OAC80 is
specified over its entire temperature range. This ·means
that the analog output ~iIl not vary by more than
±1/2LSB, maximum, from an ideal straight line drawn
between the end points (inputs all "I"s and all "O"s) over
the specified temperature range of O°C to +70°C.
Oifferential linearity error of a 0/ A converter is the
deviation from an ideal I LSB voltage change from one
adjacent output state to the next.' A differential linearity
error specification of ±1/2LSB means that the output
voltage step sizes ,can range from 1/2LSB to 3/2LSB
when the input changes from one adjacent input state 10
the next.
'

Monotonicity over a O°C to +70°C range is guaranteed in
the OAC80 to insure that the analog output will increase
or remain the same for incre~sing input digital codes.

~L=
lDODntl
IUln '

0.003
0.001
0.1
F~ G U R,E

I. Full Scale Range Settling Time vs Accuracy

Voltage0utput Models: Three settling times are
specified to ±0.01% of full 'scale range (FSR); two for
maximum full scale range changes of 20V, lOY and one
fora I LSBchange. The I LSB chliiige'is'measured althe
major carry (0111... U to: 1000 ...00), the point at which
the worst case settling time occurs.
Current Output M()dels: Two settling times are specifi~d
to ±O.OI% of FSR .. Each is given for current models
connected with two different re~istiveloads: 100 to 1000
and 10000 to 187S0. Internal resistors are provided for
connecting nomi!1al load resistances of approximately
10000 to 18000 for output voltage range of±1 V andOto
-2V. ,See Table IV.
'

DRIFT
Gain Orift is a measure, of the change in the full scale
range output over temperature expressed in parts per
million per °c (ppm/°C). Gaill drift is established by: I)
testing the end point differences for each OAC80 model
at O°C, +2S·C and +70°C; 2) calculating the gain error
with respect, to the 2SoC ~alue and; 3) dividing by the
temperature change. This figure is expressed, in ppmrC
and is given in the electrical specifications both with and
without internal reference,

COMPLIANCE
Compliance yoJtage is the maximum voltage swing
allowed on the current output node in order to maintain
specified accuracy. The maximhm compliance voltage of
all current output, models is ±2.SV. Maximum safe
voltage swing permitted without damage,to the OAC80 is
±SV.'
,

Offset Orift is a measure of the actual change'in output
with all "I"s on the input over the specified temperature
range. The offset is measured at O°C, +2,SoC and +70·C.
The maximum change in. Off$¢tis referenced to the Offset

POWER SUPPLY SENSITIVITY
Power supply s~nsitivity is a;measure of the effect of a
power supply change on the 0/ A c'onverter output. It is
defined 'as 'a' percent of FSR :I'erpercent of-change in

either the positive, negative, or logic supplies about the
nominal power supply voltages (see Figure 2).

EXTERNAL OFFSET AND GAIN ADJUSTMENT
Offset and gain may be trimmed by installing external
Offset and Gain potentiometers. Connect these
potentiometers as shown in the connection diagrams and
adjust as described below. TCR of the potentiometers
s\lould be IOOppm/·C or less. The 3.9MO and 33MO
resistors (20% carbon or better) should be located close to
the DAC80 to prevent noise pickup.lfit is not convenient
to use these high ,value resistors, an equivalent "T"
network, as shown in Figure 3, may be substituted in each
case. The Gain Adjust (pin 23) is a high impedance point
and a O.OOI,..F to O.OI,..F ceramic capacitor should be
connected from this pin to Common (pin 21) to prevent
noise pickup. Refer to Figures 4 and 5 for relationship of
Offset. and Gain adjustments to unipolar and bipolar
D j A converters.
Offset Adjustment: For unipolar (CSB, CCD)
configurations, apply the digital input code that should
produce zero potential output and adjust the Offset
potentiometer for zero output.

'1---t--~-

r- +Supply (+V&I'

I
.supply (,vs/'
I

,~

/

,.,..,

\....

~~t~
l

10

100

Ik

10k

lOOk

FIGURE 2. Power Supply Rejection vs Power Supply
Ripple.
REFERENCE SUPPLY

All DAC80 models are supplied with an internal 6.3 volt
reference voltage supply. This voltage (pin 24) has a
tolerance of ±S% and must be connected to the Reference
Input (pin 16) for specified operation. This reference may
be used externally also, but· external current drain is
limited to 200,..A. An external buffer amplifier is
recommended if this reference will be used to drive other
system components.

270kn

270kn

~
llItn - Ian

~
FIGURE 3. Equivalent Resistance.

OPERATING INSTRUCTIONS
For bipolar (COB, CTC) configurations, apply the
digital input code that should ·produce the. maximum
negative output voltage. Example: If the Full Scale
Range is connected for 20V, the maximum negative
outp"t Voltage is -IOV. See Table II for corresponding
codes and the Connection Diagrams for offset
adjustment connections.

±12 VOLT SUPPLY OPERATION
The Z models will operate with supply voltages as low as
±11.4V. For operation with supplies less than ±14V an
external resistor must be connected between the positive
supply and pin 24. This provides additional current
required by the intemal reference. The required ~esistor
value for supply voltages of ±11.4V to ±12.6V is 2.0kO
and for s':ipplies of ±12.6V to ±14V is 3.9kO.
It is recommended that output voltage ranges -IOV to
+ IOV and 0 to + IOV not be used with the Z model ifthe
supply voltages are ever less than the recommended
±12V. The output amplifier may saturate if 1V'DPpl~ -I V.D,
maxi < 2.0V. This applies to units with both CBI and
CCD input c9des. Except for operation at lower supply
voltages, the DAC80Z and DACHO operation is identical.

.1..

"

+Full SClle

~./"

"
/'
.
/"
";E.,, ~

ILSa

I

¥\

J

D.e
~
i

.li!

IJ
~

...

Rlllge of

ORIII Adj.

POWER SUPPLY CONNECTIONS
. Decoupling: For optirnum performance and noise
.rejection, power supply decoupling capacitors should be
added as shown in the Connection Diagrams. These
capacit,ors(l,..F tantalum or electrolytic recommended)
should be located close to the DAC80. Electrolytic
capacitors, if used, should be paralleled with O.OI,..F
ceramic capacitors for best high frequency performance.

"o'''<''./"T'

o'".t'/

o'/~(

An bUa
Lagle I

/

.~;o"

7ii'

,1~e"

~

,

Rlllge of

GI1nAd~

Glln Ad~
l'1iliiii
IlIIllme

ORIII Adj.
~H-+-+--+--tU--+-H-+-+-(
Tlln.I... . - OlgUlllnplll
lhlllne
I

FIGURE 4. Relationship of Offset and Gain
Adjustments for a Unipolar
OJ A Converter.

6-81

AD bU.
LiItIlc'V'

~

U
C

=

. T ABJ:.E H. Oigitalinput/ Analog Output.
<
ANALOG OUTPUT

.

+10V

+9.9976V
+5.OOO0V
+4.9976V
O.OOOOV
2.44ml/.

+9,9951V

•

. 000000000000
011111111111
. HJO.oOoooOOoo
111111111111"
One LSB

o·

"

J!J

"

~

g,
(,)

CURRENT
. ..
+1mA
Oto<2mA

Oto+l0V
12-Bit"Resolution
LSB
MSB

a;
~
:::;;
iii

:::;;

...

VOLTAGE'

DIG1TAL INPUT

,3-Digital Resolutio(1
LSB
MSB
011001100110
011001101111
011011111111
111111111111
One LSB

-1.9995mA
-1.oooomA, ..
-o.9995mA ~
O.OooomA

O.OOOOV
-0.0049V
-10.0000v
4.66mV

<0.9995mA
O.oOoomA
+O.OOO5mA.
+1.ooomA
0.4.66~A

O.466~A

.

..'
+9.990V"
·+9.900V·
+9.OOO\<
O.OOOV
10.00mV

,.

N/A
N/A'
N/A
N/A
WA

-1.249mA,
-1.238mA.
-1.125mA
O.OOOmA

'.'

N/A
NlA
N/A
NJA
N/A

1.25~A

.-

'To obtain values for other binary I CBII ranges: 0 to +5V railge: divide 0 to +1 OV range values by 2.
±5V range: divide ±10V range values by 2.
±2.5V range: divide ±IOV range values by 4.
uNormal Full Scale R~nge with correct codes; output can go higher if illegal codes are appli~d.

Gain Adjustment: For either unipolar.or bipolar
configurations. 'apply the digital input that should give
the maximum positive voltage output. Adjust the Gail)
potentiometer for. this positive full scale voltage. See
Table II for positive full scale voltages and the
Connection Diagrams for gain adjustment connections.

ILSB

L

a- 12' T
_
All bill
'Loglcl
'"

i
&

/

TarBl.
contrOl ckl

16
?REF.INPUT

. 18

-

,...l.-

3IcnICCDI

,

oi!i.

~ /~:/

·Pln 17 not cf!lll1!lCl8d lar CCO.
modals. Thatr:3kn r8sllbir.ls
IntJrnally cannactod to cammon.

T

;)f {f.:GrotllatenAld~

_0

OUTPUT

>-------UI5

Rlllgaol
-tfull Sella I' / ' ; Glln Adj.

.~',.

Un

w...

•

FIGURE 6. Output Amp,li.(ier Voltage Range Scaling
"
.
Circuit.

thalln.
H-+-§+Z+- .
ForFSR .......
1010 loon load
,Itn load

n
J

.L:::tJ-"

0

2.5
2.0
0.'
20

,
"

'

CONVERSION 'SPEED
VOI.... OUlpcl
Setllina lime 10 ±G.2% of FSR
For FSR .ban..
2OVR ....

":' .-

R.-MMC. ,

.g

DIM

±20

:

'

~;!=::1

,L8

Resolution

.' '.,

.qU)·.·J.. ~I~1

at ...tin, pl~.

0

r

~"I

..

(lnl.)

~ ri4)Common
~

"='

@)-15V

@1••,t(Ext.)

r

(iDSi1I1 LSB)
@)Bi17

,

DISCUSSION OF SPECIFICATIONS

DIGITAL INPUT CODES

DRIFT

The DAC82 accepts digital inputs in complementary
binary (CBI) format '. and may be connected for
complementary straight binary (CSB) or complementary
offset binary (COB) operation. By using one external
inverter, the user can operate the DAC82 in the
complementary two's complement (CTC) mode.

DIGITAL
INPUT
CODES
MSB

GAIN DRIFT
GAIN DRIFT is a measure of the change in the analog
output over, temperature expressed in parts per million
per °C (ppm/°C). The GAIN DRIFT is determined by
testing the end point differences at the high and low
temperature extremes and at 25°C for each 'model,
calculating the GAIN ERROR with respect to the 25°C
value, and dividing by the.temperature change.

OUTPUT RANGE
VOLTAGE010 +IOV

±IOV

+9.961 V
+s.ooov
+4.961 V
O.OOOV
39.06mV

+9.922V
O.OOOV
-78.12mV
-IO.OOOV
78.12mV

'OFFSET DRIFT

CURRENT

OFFSET DRIFT' is a measure of the actual change in
output voltage at zero volts output over the specified
temperature range. The offset voltage is measured at the
temperature extremes, and the maximum change
referenced to 25°C is divided by the temperature range.
This drift is expressed in parts per million of full scale
range per'C (ppm of FSR/"C).
C

Ol01.6mA ±O.8mA

LSB

00000000
o I I I I I I I
10000000
I I I I I I I I

one LSB
• To obtain

val~

-1.594mA

~.794mA

~.800mA

O.OOOmA

~.792mA

+6.248~A

O.OOOmA

+O.800mA

6.248~A

6.248~A

B
CI

for other binary (CBI) ranges:

SETTLING TIME

o to +SV ranae: divide 0 to +IOV range values by 2.
±5V ra.,.: divide ±IOV ran.., values by 2.
±2.SV range: divide ±IOV range values by 4.

Settling time is the time required for the output to enter
and remain in an error band equal to ±o.2% of full scale
range measured from the time the digital input is
changed. Typical settling time values for full scale
changes are a function ofthe load resistor and are shown
in the figure below.
.

TABLE I. Digital Input and Analog Output
Relationship.

300n5

ACCURACY

~~

'"
i='O

e"'"
..

LINEARITY
The LINEARITY of a D / A converter is the true measure
of its performance: The DAC82 analog output will not
vary by more than ±I /2 LSB from an ideal.straight line
drawn between the end points (aliI's and all O's) over the
specified temperature range.

200ns ...... ~

~~
ii;i

'" S

lOOns

1000

IkO

lOW
Load Resistor

100kO

DIFFERENTIAL LINEARITY
FIGURE 1. Settling Time for FSR Change vs Load.

The DIFFERENTIAL LINEARITY error of a D / A
converter is the deviation from an ideal I LSB voltage
change from one adjacent output state to the next. A
DIFFERENTIAL LINEARITY error specification of
±1/2 LSB means that the output voltage can change
anywhere from 1/2 LSB to 3/2 LSB when the input
changes from one adjacent digital state to the next.

COMPLIANCE
The COMPLIANCE VOLTAGE of th. DAC82 is the
maximum voltage swing allowed on the current output in
order to maintain the specified accuracy. It is -4.0 to +4.0
volts for the unipolar and bipolar current ranges.

6-89

, POWER SUPPLY
SENSITIVITY

,

.

'/~

:

,"

"

;'.

/

~06

.04

t!1

POWER SUPPLY SENSITIVITY is a measure of the
effect of a power supply voltage change on the'Dl A;
converter output. It is defined as a percent Of
FSR/percent of change in either the +15 volti)r~ISvolt"
powenupplies about the nominal power supply voltages. '
. Figure 2 shows 'Power Supply Rejection vs Frequency..

8.

.
t

~>

g .5

... , v
",..~

rc~
u
'O~

/../

+ISV Supply ......
.02
.01

.006

·001

I ./

t!1

'.-ISV Supply

!',

V"

,002
.001

100'

.10

I

Ik

.10k

lOOk

Power Supply Ripple Frequency (Hz)

.......

FIGURE 2.PQwer S\lpply Rejection vs. Power Supply
Ripple Frequency.

OPERAT,ING INSTRUCTIONS
POWER SUPPLY
CONNECTIONS

)-,o~~----' T" +ISVDC
S~pply

DECOUPLlNG' '

DAC82

For best performance and noise rejection" power supply
decoupling capacitors should be connected as shownjn
Figure 3. These capacitors should be located c.!ose to the
DAC82 and should be tantalum or electrolytic types.
bypassed with a 0.01 foLF ceramic capacitor for best high
frequency performance. . .
'

)-,o~~-,---_Common

)-,o~I-_,.--

' -_ _ _""'.-

_ _ To -ISVDC
Supply

FIGURE 3. Recommended Power Supply Decoupling.

OPERATION IN TtiE
,
CURRENT OUTPUT MODE
On the current output pin, ..theDAC82 provides a
unipolar output current of 0 to -L6mA and a bipolar
9utput current of ±o.8mA. Refer to Figtlre4 and Table I(
for proper connections. In applications requiring the use"
of theDAC82 in the current output mode, such as an;
A/D converter, the, internal sealing resistors should be
used to generate currents corresponding to analog input
voltages.

OUTPUT RANGE

CONNECT P~I'I I TO:

o lo-1.6mA

N.t.

±O.8mA

Pi~ 18

·TABLE II. Connections for Current Output Mode.

FIGURE 4. Current Output Mode Connection Diagram.

6-90

DRIVING AN EXTERNAL OP AMP
UNIPOLAR OR BIPOLAR UP TO 20V OUTPUT RANGE
The DAC82 will drive the summing junction of an op
amp (the op amp being used as a current to voltage
converter) to produce an output \IGITAL INPUT

and +70 0 C or +85°C'. The maximum change in,OFFSET
is referenced to the OFFSI;lT at 25°C divided by the temperature ran·ge. This drift is expressed iii' part!; per million
offull scale range per °C. (ppm of FSR/OC),

ANALOG OUTPUT
. COD
CTC·
Compt
Compt
Two's
Siraisht
Offset
Binary
Binary
Compt
-L,)D
+Full Scale
+Full Scale
Zero
-Full Scale
+li2 FuU Scale
Mid Scale· -I LSD
-II,SD
+Full Scale
CS.8
Compt

MSD

i

,;
;0
;"

LSD

OOOOOOOOOOOO
011111111111
100000000000
111111111111

~
.,;

e

MSD
LSD
OlIO 0110 0110
1111 1111 1111

• Invert the MSB
ere co(le.

Zero

;-Full !leale

SETTLING TIME
The settling time for each model DAC85 is ·the total time
(including slew time) for the output to settle to within an
error band about its final value after a change in· the input.

vOLtAGE OUTPUT MODELS

Zero

Three settling times are specified to ±O.OI%.of full scale
range (FSR); two for maximum full scale range. changes of
20V and 10V and also for a I LSB change. The I LSB
change is measured at the major carry (0111 ... II to
1000 ... 00) since this is the point where· the worst case
settling time occurs.

CCD
Complementary Coded Decimal - J Dilil>
+ UII·~ca e
Zero

or the COB co(ie with an ~xternal

inverter to 9btain

TABLE I. DigitallnputCodes.

CURRENT OUTPUT MODELS
Two settling times are specified for current output mOdels;
each specified settling time to ±0.01 % of FSR: is given for
the DAC85 current models connected with two different
resistive loads -. i.e., 10 to 100 ohms and 1000 to 1875
ohms. Internal resistors are provided for connecting nOminal
load resistances of approximately \000 ohms to 1800 ohms
for output voltage ranges of ±I volt and 0 to-2 volts. (See
.
Table 4)

ACCURACY
LINEARITY
The linearity of a 0/ A converter is the true measure of its
performance.' The linearity error of the DAf'85 and DAC85C is specified over the entire specification·· temperature
ranges. The definition ot' this specification means that the·
analog output will not vary by more than ±i/2LSB from an
ideal straight line drawn befween theenli puints (all bits ON
and all bits OFF) oyer· the specified operating temperature
range,

COMPLlAN,CE
The compliance voltage of the DAC85 is the maximum voltage swing allowed on the current output mode in order to
maintain the specified accuracy; it is ±2.5 volts for the bipolar current range of ±1.0 rnA apdis -2,5 volts for the hnipolar current range of 0 to -2 rnA. The maximum safe, voltage swing allowed with no damage to theDAC850ufput is
±5 volts for current output mQqels.

DIFFERENTIAL LINEARITY·
Differential linearity error of a D/ A.converter is the deviationfrom an ideal I LSB vq!tage ch~nge from one adjacent
output state to the next. A differeniiallinearity error specification of rl/2 LSB means that the output ·voltage can
change anywhere from 1/2LSB ·to. 3/2 LSB when the
input changes from· one adjacent input state to the next.

DRIFT
GAIN DRIFT
GAIN DRIFT is'it measure of thecpange in the full scale
range analog output over temperature expressed in parts per
million per °C (ppm/oC). The GAIN DRIFT is determined
by testing the.end point differences at ';259(, or OOC; +25 0 C
and +70°C or +85OC for each model and calculating the
GAIN ERRdR with respect to the 25°C value and dividing
by the temperature change. This specification is expressed
in ppm/oC.

FIGURE 1. Full Scale Range Settling Time vs. Accuracy.

6-96

POWER S'UPPLY SENSITI'VITY

.1

~'" .06

POWER SUPPLY SENSITIVITY is a measure of the
effect of a power supply voltage change on the D/ A con·
verter output. It is defined as a percent of FSR per
percent of change in either the + 1S volt or -1 S volt and +S
power supplies about the nominal power supply voltages ..
Figure 2 shows Power Supply rejection vs. frequency.

tc.

.04

~~

.02

Q,Q,

~.=

=::

~

g:;

j +ISV

I/'

.oJ

.006
.004

~

... .c
o~

~'O

.002
.001

I

10

./

Supply

-

~

./
I'. -ISV Supply

+SV Supply"

I

Ik
10k
100
Power Supply Ripple Frequency (Hz)

-

lOOk

FIGURE 2. Power Supply Rejection vs. Power Supply Ripple
Frequency.

REFERENCE SUPPLY
All DAC8S models are supplied with an internal 6.3 volt
reference voltage supply. This reference voltage (pin 24)
has a tolerance of ±5%, and must be connected to the
Reference Input (pin 16) for specified operation.

This reference may also be used externally, but the current
drain is limited. to 200 /lA. An external buffer amplifier is
recommended if the DAC8.5 internal reference will be externally
used in order to provide a constant load to the reference supply
output.

ORDERING INFORMATION
DAC85 xx xxx - X
_ _~=-T
12·Bit D/A Converter
Family
Example: DAC85-CBI·V
DAC85 with voltage output,
Binary code and -25 0 C to
+85OC temp. range.

C = 0 to +700 C Model
LD = Low drift -2SoC to
+85 0 C Model
Leave blank for-25 0 C
to +85 0 C Model

~------==

INPUT CODE
OUTPUT
CBI = Complementary
V Voltage
l2-bit binary
I = Current
CCD =Complementary
(not available
3-digit BCD (not available
for LD model)
for DAC85LD

OPERATING INSTRUCTIONS
DIGITAL INPUT AND
ANALOG OUTPUT RELATIONSHIP
Output Range
Oigitallnput
Codes

Voltage *
Oto+10V :t:10V

Current

oto-2mA

.:!:1mA

Binary (CBI)
12 bit resolution
+2.44mV 4.88mV
One LSB
O.488jlA
0.488jlA
+9.9976V +9.99SIV -1.999SmA -0.999SmA
All bits ON
All bits OFF
IO.OOOV
Zero
Zero
+1.0000mA
Decimal (CCD)
3 digit resolution
One LSB
IOmV
+ FS bits ON
+9.99Vt
All bits OFF
Zero

POWER SUPPLY CONNECTIONS DECOUPLING
For best performance and noise rejection, power supply
decoupling capacitors should be connected as shown in
Figure 3. These capacitor's should be located close to the
DAC85 . and should be tantalum or electrolytic types by·
passed with a 0.01 /IF ceramic capacitor for best high fre·
quency performance.

,..:_ _ _ _....;.2;:4 Internal Reference

N/A

l.2SjlA
-1.249mA

r------ Connect to Pin 16'
J-~~,.------ To +15 Vdc

N/A

Supply

Zero

r4~-""--. Common

OAC8S

TABLF 2. Ideal Output Voltage and Current.

~-t_-J'f\---_ To -15 Vdc

tNormal full scale range with correct codes; output can go to + 12
volts if illegal codes are ap.pJied.
*To obtain val~es.for othe~ binary (CBI) ra~~es:

~~

o to +5V range:

Supply
_ _. ._ _ _ _ _ To+SV
Supply

divide 0 to +lOV range values by 2.
±SV range: divide ±lOV range values by 2.,
t2.5V range: divide ±lOV range values by 4.

FIGURE 3. Recommended Power Supply Decoupling.

6-97

EXTERNAL· OFFSET and GAIN, ADJUSTMENT
Offset and gain may be trimmed externally by the user with externally connected
OFFSET lind GAIN potentiometers. If gain and offset adjust circuits are riot used,
pins 15:20, and 23 should be connected as described in other sections herein. (Do not
ground.) Connection of the potentiometers and the methods of adjutments is as
outlined below. Potentiometer resistance' values indicated are range of values.
Potentiometers should have TCR of lOOppmj"C or less.' The 3.9M!} and 18M!}
resistors ,can be 20% carbon composition or better. These two resistors should be
located close to the DAC85 to prevent signal pickup..

OFFSET ADJUSTMENT

GAIN ADJUSTMENT

for unipolar (CSB, CCD) Df A converters, apply the digital
inppt code that should give zero volts output and adjust the
OFfSET potentiometer for zero volts output. For bipolar
(COB, CTC) DfA converters, apply the digital input code that
should give the maximum negative voltage output. Example:
If the FULL SCALE RANGE is connected for 20 volts,
then the maximum negative voltage output is·IO volts. See
Table 2 for corresponding codes.

for either unipolar or bipolar Df A converters, apply the
digital input that should .give the. maxirnU!:n positive'voltage' '
output. Adjust the GAIN potentiometer for this positive
full scale voltage. The positive full scale voltages for the
DAC85 are given in Table 2.
+15 Vdc

Offset

+15 Vdc
10 kn

(~: ~~ ~~~ i :::,~~s.

)------------J3.~9~M~n~----t---~~ :gokn

10kn
Gain
Adj.

z,;:.::....----------~y..,...--t_..;.,.< to

.001 1'1'
~ ~ to
21l.)'"
.011'F

Common

1.8

Mn

100 kn
.15Vdc

Range of-Adjustment: ±O.3% of FSR

·15 Vdc

Range of Offset Adjustment, ±0.2% of FSR

/.1..
~/'

/.?!J('"
f.
Range of

1

~~". A d i

~,~:~a~e;'

AU bit.

OFF

G,'.
& 1-'l'''
~
P

All bill
OFF

/." "T

......../-'
?,:.- ~

"'H4~~'Ii+-4'-+-1Jo++-4

Range. of

G,I. Adj.

Adj.
rotates;

the line

All hilS

1C.o~-+-+-+-III-+++-+-I-I,1
/.

the l i n e ' -

......... AlIbi.,
ON

ON

T.........

Oilitalln'put

DlJItailftpu.t

the line

FIGURE 4. Relationship of OffSET and GAIN Adjl,lstments
for a UNIPOLAR Df A Converter.

fiGURE 5. Relationship of OffSET and GAIN Adjustments
for a BIPOLAR Df A Converter.

VOLTAGE OUTPUT MODELS
OUTPUT RANGE CONNECTIONS
Internal scaling resistors are provided in the DAC85 to provide a wide range of output voltage range connections.
These internal resistors rnay be connected to provide three
bipolar output voltage ranges of ±IO, ±5 or ±2.5 volts or
two unipolar output voltage ranges of 0 to +5 or 0 to + I 0
To Reference 16

Ref.
Input

6.3 kn

17

Control Ckt.
From Weighted
Resistor
Network

-

{)21
~Com

18

5 kn (CBI)

":I"

19

3 kn (CCO)
15
Output

fIGURE 6. Output Amplifier Voltage Range 'Scaling Circuit.
*pin 17 not connected for t'CD models. The 6.3 kn resistor is
internally connected to common.

volts .. Since these internal scaling resistors are an integrat
part of the DAC85, gain and offset drift is minimized.·
Connections for DAC85 output voltage ranges are shown
in Table 3.
.
.
Settling time for these voltage ranges is specified for a fulf
scale range change, and is 5· microseconds for 8 kn or \0 kn
and 3 microseconds for a 5 kn feedback resistor.
Output
Range

Digital
Connect Connect Connect Connect
Input .Codes Pin 15 to Pin 17 to Pin 19 to Pin 16 to

±JO

COB or eTC

19

20

IS

24

±5

COBor·CTC

1·8

20

N.C.

24

±2.SV

COB or CTC

20

24

CSB

18
'18

20

o to +IOV
o to +5V
o to +IOV

21

N.C.

24

CSB

18

21

20'

24

CCO

19

N.C.

IS

24

TABLE 3. Output Voltage Range Connections'Model DAC85.

Voltag~

CURRENT OUTPUT MODELS
Internal resistors are provided either for scaling an external
op amp to the same voltage ranges as the voltage model
DAC85 or for configuring a resistive load to provide two
output voltage ranges of ± I volt or 0 to -2 volts. These
internal resistors (RU) are an integral part of the DAC85
design, and are required to maintain the gain and bipolar
offset drift specifications of the DAC85. If the internal
resistors are not used, external RL or RF resistors should
have ±25 ppm/oC or less. temperature coefficient to minimize drift.

Instructions for using the DAC85-xxx-1 with either a resistive
load or an external op amp are on the following pages.
External RLS or RLP resistors are required to give exactly
o to -2V or ± I V output range. These resistors should have
a TCR of ±I 00 ppm/oC or less. If these exact output ranges
are not required, RLS (or RLP) need no' be used as discussed below.

r:- Toref.cORlrolclu.

Ref. In
16

The current model DAC85 equivalent output circuit and
resistive scaling network is different from the voltage model
DAC8S, and is shown in Figure 7 and 8 for reference.

0

i-- 'N'1r.-------017

I :-----0:

'"~'"' Y$

---0

H A ) DAC8S·CBI-1

r= Rd.

Ref. In

6.3kU

.----"'U 17 Bipolar Off...

,------...------L)IS

Internally

-----l..,":'licd to Common

160~~~---"N,,".

.nn

ISUl

-_--¥.rv--------O 19

IBO
....

---

~5kn

150---3

010
2mA

020N.C.

(B) DAC8S-CCD-1

lUll"!

OI7N.C.

L-~============~~=-

FIGURE 7. Internal Scaling Resistors.

______

FIGURE 8. DAC85 Current Model Equivalent Output Circuit.

Vol"tage Output Using' Resistive Load
UNIPOLAR
BINARY INPUT CODE (CSB)
A load resistance RL connected to the output as shown in
Figure 9, will generate a voltage range, VOUT, determined
by:

VOUT =-2 rnA

(15kXRL)
15 k + RL

V ew ,
RI.s

where RL max = 1.36 kn
and VOUT max =-2.5 volts

FIGURE 9. Equivalent Circuit DAC85-CBI-I connected for
Unipolar Voltage Output with Resistive Load.

For minimum drift as specified, the internal scaling resistor
(RU) should be connected as shown in Table 4 for the CSB
code with a series connected external metal film full scale
trim resistor (RLS) to provide a full scale output voltage
range of 0 to -2 volts. With RLS = 0, VOUT = -1.1l2V.

,.---,~\
by digital input

t:~

I1CD INPUT CODE (CCD)

• OlO

Connect the internal scaling resistors as shown in Table 4,
and add an external parallel connected metal film resistor
(RLP) as shown in Figure 10 to obtain a 0 10 -2 volt full
scale output voltage range for CCD input codes. With RLP
=00, VOUT = -2.08V.

1.2SmA

RI.I

'7

1.5

+

RI.,

VOUT

21

-

~'om

FIGURE 10. DAC85-CCD-I Connected for Voltage Output
with Resistive Load.
~.

Output
Input
Code . Voltage
Range

Internal
Resistance
RU

1% Metal Film
External Resistor
RLS
RLP

CSB

o to-2V

0.968 kl1

10511

CCD

o to-2V

1.875 kl1

N/A

COB or
CTC

±IV

1.2kl1

90.911

~

~~

N/A·
36:5 kl1
N/A

RU Connections
Connect
Connect Connect
Pin 15to Pin 18to Pin 20 to

Reference
Connect Connect
Pin 16 to Pin 17 to

20

19 & R LS

15

24

21
(Com)

19

21
(Com)

N.C.

24

N.C.

18

19

R LS

24

15

TABLE 4. DAC85X - XXX - I Resistiye Load Conne.ctions.

6-99

Bipolar Offset
RLS
Between' pin
18 & 2.\
N/A
Between pin
20 & 21

RLP
NJA

Between pin
IS & 21
N/A

BIPOLAR
COB and CTC,INPUT COpES
The equivalent output circuit for a bipolar output voltage
range is shown in Figure II. , VOUT is determined by:
.
(RLX4.44k)
VOUT=±1 rnA x
. '
,
. RL + 4.44k

2kl!

-

r--

Bit6~

lout

-=

Bj't1
§I(MSB)

2mA

O.5mA

~

..

5kl!
~

c:

B

lout

~10V
Range

5kSl

~;

L--.
7.6~lnt

Scommon

Ref.

~20V
Range

Bit 8
(LSB)1

<2: r- ~'~u

~8iPol8r

-15V

G:

~Gain
Adj.

Offset

•

4. Connect to ground if gain adjust circuit is not used.

6-103

DISClJ$SI.;ON
",
,

QF~SPECIFIC~T'IONS

'\

DIGITAL INPUT CODES
The DAC90 accepts digital inputs in compfementary
binary (CBI) format and may be connected for complementary straight binary (CSB) or comprementary
offset binary (COB) operation (see Table I). By using one
e,xterJlal inverter, the user canoperate the DAC90 in the
complementary two's complement (CTC) mode.

Offset Drift

OFFSET DRIFT is a measure of the actual change in
output voltage (using an external amplifier) at zero volts
output over the specified temperature range. The offset
voltage is measured atthe temperature. extremes, and the
maximum change referenced to 25"C is divided by the
temperature range. This drift is expressed in parts per
million of full scale range per"C (ppm of FSRj"C).

l'ABLE'!. Digital Input and ,Analog Output
'

Relationship ,
DIGITAL
INPUT
CODES
MSB

OUTPUT RANGE
VOLTAGE*
CURRENT
oto +10it ±1i1V Oto-2mA ±1mA

SETTLING TIME
SfTTl.I:'\G TIM f is the time rcquired for thC(llnput to
enter and remain in an error hand equal to ±O.1' i of full
scale range measured from the time the digital input is
changed. Typical settling time \alues for full scale
changes arc a function of the, load resistor and lire shown
in the figure below.

LSB'

00000000

+9.961V +9.922V

-1.992mA -0.992mA

01111111

+5.000V. O.OOOV,

-1.000mA O.OOOOmA

10000000

+4.961 V

_7B.12mV -0.99mA

+7.Bl1'A

, 1 1 1 1 11 1

O.OOOV

-10.000V

O.OOOmA

+1.000mA

one LSB

39.06mV 78.12mV

7.81/lA

7.811'A

* Requires external 8(nplifier. To Obtain val ues for other ..bi~ary
(C~I) ranges; 0 to +5V range: divide 0 to +10V range values by 2

.

t5V range: divide t10V range values by 2.
±2.5V range: divide ±10V range values bV 4.

300

,

U

iR

ACCURACY
LinearIty
The LINEARITY ofa Dj A converter is the true measure
of its performance. The DAC90 anaiog output will not
vary by more than ±lj2LSB from an ideal straight line'
drawn between the end points (alii's and all O's) over the
specified temperat\lre range.

._"E a:e::~'"
Cl"e:::: 0
=#
~~

'i'I

E

200

..

I",.oo~

100

100

lk

Load Resistor

Differential Linearity

DIFFERENTIAL LINEARITY error of a Dj A converter is the deviation from·an ideal I LSB voltage change
,from one adjacent output state'to the next. A DIFFERENTIAL LINEARITY error specification of ±I j2LSB
means that the output voltage can change anywhere from
Ij2LSB to 3j2LSB when the inpilt changes from one
adjacent digital state to the next.

10k

lOOk

In,

FIGURE I. Settling Time for FSR .Change.vs Load.

Compliance

The COMPLIANCE VOLTAGE of the DAC90 is the
maximum voltage swing allowed onthe c,urrent output in
order to maintain the specified accuracy; it is -4.0V to
+4.0V for the unipolar and bipolar current ranges. The
maximum safe voltage swing allowed with no damage to
the DAC90 output is -4.0B to +15.0V

. DRIFT
GalnDrlfl..

GAIN DRIFT is a measure of the change in the analog
output over temperature expressed in parts per million
per '"C (pp:mj"c). The GAIN ORIFT is determined by
testing the end point differences' at the high and low
temperature. J::xtfemes and' at 25"C' for each model,
calculating. the GAIN ERROR with respect to the 25"C
: value, and dividing'by the temperature change.

6-104

POWER SUPPLY SENSITIVITY
POWER SUPPLY SENSITIVITY is a measure of the
effect of a power supply \'oltag~ change on the () A
converter output. It is defined as a percent of FSR/.
percent of change in either the +15VDC or -15VDC
pgwer supplies about the nominal power supply voltages.
Figure 2 shows power supply rejection vs frequency.

0.1

,f

0.06
0.04
+15VDC Supply ......

0.02

~

0.01

~

g

w
a:

f:2

'0

;j1

0.006

0.004

0.002
0.00 1

V

V

./

L

.... -15VDC Supply

1
100

10

/

L

lk

10k

lOOk

Power Supply Ripple Frequency I Hz I

FIGURE 2. Power Supply Rejection vs. Power Supply
Ripple Frequency.

OPERATING INSTRUCTIONS
POWER SUPPLY CONNECTIONS
Decoupling
; ) - -....- - - -... To +15VDC

For best performance and noise rejection. power supply
decoupling capacitors should be connected as shown in
Figure 3.These capacitors should be located close to the
DAC90 and should be tantalum or electrolytic types
bypassed with a O.OIj.tF ceramic capacitor for best high
frequency performance.

Supply

DAC90

L____

Common

-f!)-~~-------1PTO-15VOC

Supply

FIGURE 3. Recommended Power Supply Decoupling

OPERATION IN THE CURRENT OUTPUT MODE
In the current output mode. the DAC90 provides a
unipolar output current of 0 to -2mA and a bipolar
output current of±1 rnA. Refer to Figure 4 and Table"
for proper connections. I n applications requiring the use
of the DAC90 in the current output mode. such as an
A D converter. the internal scaling resistors should be
used to generate currents corresponding to analog input
voltages.

0'0
-2mA

TABLE II. Connections for Current Output Mode.
Output Range

o to

-2mA

±1mA

Connect Pin@to:
N.C.
Pin 10

FIG U R E 4. Current Output M ode Connection Diagram.

6-105

VOLTAGE OUTPUT using an eXTERNALOP,AMP
UNIPOLAR OR BIPOLAR,OPERATION
The OAC90 wiildrive the summing junction of an op
amp (the op amp ,bei'ng used as a, current-to~voltage
converter) to produce and output voltage,
,

,

VOl'''' = -I X RF
where ImT is the OAC90 output current and RF iphe
feedback resistor. Refer to Table III and Figure 5.

TABLE III. Voltage Ranges of Current Output DAC90
with External Op Amp.
Output
Range

Digital
Input Codes

tl0V

FIGURE 5. External Op Amp Using Internal
Feed,back Resistors.

Connect
to

®

Connect
Pin@to

COB

11

10

±5V

COB

12

10

±2.5V

10,11

COB

12

Oto+10V

CSB

12

N.C.

o to +5V

CS,B

12

11

EXTERNAL OFFSET and GAIN ADJUSTMENT
Initial offset and gain errors may be trimmed by the, user
with externally connected OFFSET and GAIN potentiometers and an operational amplifier. Refer to Figures
5 and 6 for proper connections. The adjustment
procedures are described below. Potentiometer resistances are shown as a range of values and should have a
temperature drift coefficient of IOOppm, "c or less. The
trimming networks should be located as 'close to the
OAC90 as possible to minimize noise pickup. The
ceramic capacitor shown in Figure 6 will further reduce
noise pickUp at the gain adjust point.
OFFSET ADJUSTMENT

Offset adjustment should be made prior to gain adjustment. Connect the unit as shown in Figure 5 for the
desired output range and add the offset adjust network
shown in Figure 6., Offset adjustment is the same
procedure for either bipolar or unipolar operation.
Apply the digital input code which should give zero volts
output and adJust the offset potentiometer for zero volts
output. See Table I for the corresponding codes.

ri
.

13

100k,'

Gain

n

"';<
0"/

lLSB

~
.s~,
Range

Jo"

~,
~
u

~~

~
"3

Offset Ad).

All

ll"" I

Offset Ad.::....t...

Tnmslates
the line

Adjust

Adjust

10kH to
l00kH

,

R = lk!1 to
10k!1 '

-15VDC

7R

-15VDC

FIGURE 6. Connections for OFFSET and GAIN
Adjustment.
GAIN ADJUSTMENT
The gain adjust procedure is the same for either bipolar
or unipolar operation. An external amplifier should be
connected as shown in Figure 5. Connect the unit for the
desired output range and add the ga,in adjust network
shown i~ Figure 6. Apply the digital input code which
should give the maximum positive output voltage and
adjust the gain potentiometer for the cOrrect output.
Refer to Table I for the corresponding codes.

+Full
Scale

~

+Full Scale

......

7R

°llset,

L
5c.

+15VOC

+15VDC

"s
~t.

; ~y

~:!~/
'l~-{

r

5

e
0

Range of
Gain Adj

...
0

~~ ..

~9../

~

Gam Adj.
rotates
the lone

h,q
/.W

0

~

AIIO's
'

/
--r-IC-HH-i--i---IjIH-++++-I
I

AII1's

Adjust

/."//
/,//

;'

Digital Input

/

//

-FLII

Scale
Oi

FIGURE 7. Relationship of OFFSET and GAIN
Adjustment for a UNIPOLAR 0/ A
Converter.

Offset,

ita'

In ut

FIGURE 8. Reiationship.ofOFFSET and GAIN
Adjustments for BIPOLAR 0 A
Converter.

6-106

BURR-BROWN®

DAC700/702
DAC701/703

I EEl EEl I

Monolithic 16-Bit
DIGITAL-TO-ANALOG CONVERTERS
FEATURES
• MONOLITHIC CONSTRUCTION
• VOUT AND louT MODELS
• HIGH ACCURACY:
linearity Error: ±0.003% of FSR max
ISH. KH models)
Differential linearity Error: ±0.OO6% of FSR max
ISH. KH models)
• MONOTONIC lat 14 bits) OVER FULL SPEC
TEMPERATURE RANGE IBH. KH models)
• PIN-COMPATIBLE WITHDAC70. DAC71. DAC72
• LOW COST

DESCRIPTION
This is another industry first from Burr-Brown-a
complete l6-bit digital-to-analog converter that includes a precision buried-zent;:r voltage reference

and a low-noise, fast-settling output operational
amplifier (DAC701f703), all on one small monolithic
chip. A combination of current-switch design techniques accomplishes not only l4-bit monotonicity
over the entire specified temperature range (BH and
KH grades) but also a maximum end-point linearity
error of ±O.OO3% of Full Scale Range (BH and KH
grades). Total full scale gain drift is limited to
±15ppm/oC maximum (BHgrade).
Digital inputs are complementary binary coded and
are TTL-, LSTTL-, 54f74C- and 54f74HC-compatible over the entire temperature range. Outputs are 0
to +IOV (DAC701), ±IOV (DAC703), 0 to -2mA
(DAC700) and ±lmA (DAC702).
This D/ A family is pin-compatible with the voltage
and current output DAC71 and DAC72 model
families. The DAC700 and DAC702 are also pincompatible with the DAC70 model family. These
D / A converters are packaged in 24-pin ceramic sidebrazed packages that are hermetically sealed.

8.3V REF OUT
+Vcc

GAIN ADJUST
SUMMING JUNCTION
COMMON
-Vee

Voo

International Alrporllnduslrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. 18021 746·1111· Twx: 91IJ.952·1111· Cable: B8RCORP· Telex: 66-84111

6-107

SPECIFICATIONS
ELECTRICAL
AI TA = +25' Cand ,allld po""" supplie8 unl,ess ~Iherwise noled,
DA~kH'

DAC700170117021703BH

MODEL

,

PARAMETER

~' . ,

.

,', :'.1'"

TVP

MIN

MAX

:": TVP

"

,,' MAX'"

J
UNITS

INPUT

,

DIGITAL INPUT
Resolution
Dlgit4llnputsl1l : VIH
VIL

I'H,

-0.35

16
+Vcc
+0.8
+40
-0.5

±0.0015
±0.003

±O.OO3
±O.OO6

±a.001S

'±0.003
±0.10
±0.1

+2,4
-1,0
VI:::::;

+2.7V

IlL, V, = +0.4V

·

Bils
V
V
pA
rnA

TRANSFER CHARACTERISTICS
ACCURACY'"
Linearity Erro"'"
Dlffensntlal Llneartty Error'''
Differential Linearity Errorf41
al Bipolar Zero (DAC702l703)
Gain Errorfsi
ZerO' Error,suet "
Monolonicity Over Spec. Temp. Range

±0.05
±0.05
14

'"

0/0 of FSR
%olFS~

14

,

DRIFT'''
(over specification temperature range)'
Tolal Error Over Temp. Range (all mOdelS)'
Tolal Full Scale Drift:, DAC700/701
DAC7021703
Gain Drift (all models)
Zero Drift: DAC700n91
DAC7021703,
Dlffensntlal Llneailty Over Temp.'"
Linearity Error Over Temp.'"

±O.05
±8,5
±7
±7
±1.5
±4

SETTLING TIME (10 ±0.0030/0 pI FSR)'"
DAC701n03 (VOUT models)
Full Scale Slep, 2kn load
lLSB Step al Worsl Case Code'"
Slew Rale
DAC7001702 (lOUT Models)
Full Scale Slep (2mA), 100 10 loon load
lkn load

4

8

2.5
10

4

±0.10
±18
±15
±15
±3
±10
+0.009, -0.008
±0.006

±0.003
±0.07

±O,OO6
±0.15

0/0 01 FSR
0/0
%olFSR
Bits

±0.08
±10
±10
±10
±2.5
'±5

±0.15
±3O
±25
±25
±5
±12

%olFSR
ppm 01 FSRI' C
ppm 01 FSRI' C
ppm/'C
ppm 01 FSRI' C
ppm 01 FSRI' C
%olFSR
%olFSR

.'

.'

pSec
psec
V/psec

·

nsec

350
1

pSec

OUTPUT
VOLTAGE OUTPUT MODELS
DAC701 (CSB Code)
DAC703 (COB Code)
Output Current
Outpullmpedance
Short Circuit to Common Duration
CURRENT OUTPUT MODELS
DAC700 (CSB COde)""
Oulpul Impedance""
DAC702 (COB Code)"·'
Output fmpedante f101
Compliance Voltage
REFERENCE VOLTAGE
Voltage
,Source Current Available
for External Loads
Temperalure Coefficienl
Short Circuli 10 Common Duration

010+10
±10
0,15
Indefinlle

.

010-2
4,0
±1
2.45
'±2.5
+6,24

+6,30

+1,5

+2.5
±10
Indefinite

13,5
13.5
+4,5

15
15
,"'5
+10
~13

+4
+16
..,18

+4

·
·

+6.36

+6.0

±15"

POWER SUPPLY REQUIREMENTS
Voltage: +Vcc
-Vee
Voo
Currenl (no load)
DAC700n02 (lOUT models): +Vee
-Vee
Voo
DAC701I703 (VOUT models): +Vcc
-Vee
Voo

V
V
mA
n

.

±5

16,5
16,5
' +16.5
+25
-25
+8
+30

-30
+8

6-108

+6,6

V

·

±25

mA
ppm/'C

·

·

+6,3

.,

·

:

mA
kn
mA
kn
V

·
··
~

V
V
V
mA
mA
mA
mA
mA
mA

ELECTRICAL [CaNT)
DAC7GOI7011702170311H

MODEL
PARAMETER

MIN

DAC7G01701I7021703KH

TVP

MAX

365

630
780
±a.003
±0.003
±O.OOI

MIN

TVP

MAX

J
1

UNITS

POWER SUPPLY REQUIREMENTs (CONT]
Power Dissipation (Voo = +5.0V)"1>
OAC7001702
OAC7011703
Power Supply Rejection: +Veo
-Veo
Voo

530

±a.OOl5
±0.OOl5

±a.OOOI

790
940
±0.006
±0.006

mW
mW
'!40 01 FSRI%Vcc
'!40 01 FSRI%Vcc
'Mt 01 FSR/%Voo

+70

·C
·C

TEMPERATURE RANGE
Specification
Storage

-25

-60

+85
+150

0

..
·SpeClflCstion same 88 model to the left .
NOTES:
I. Digital Inputs are TTL, LSTTL, 54174C, 54174HC and 54174HTC compatible over the operating voltage range of Voo = +5V to +I5V and over the specified
temperature range. The Input switching threshold remains at the TTL threshold 01 I.4V over the supply range of Voo = +5V to +I5V. As logic "0" and logic "I"
Inputs vary over OV to +C.8V and +2.4V to +IOV respectively, the change In the O/A converter output voltage will not exceed ±0.003% of FSR for the BH grade and
±0.008% of FSR for the KH grede.
2. OAC700 and OAC702 (current-output models) are specified and lested with an external output operational amplifier connected using the internal leedback
resistor in all parameters except settling time.
3. FSR means Full Scale Range and Is 20V for the ±IOV range (OAC703), lOV lor the 0 to +10V range (OAC701). FSR is 2mA lorthe ±lmArange (OAC700) and the 0
to +2mA range (OAC702).
4. ±0.OOt5'11o 01 Full Scale Range Is equivalent to lLSB In 16-bit resolution. ±0.003% 01 Full Scale Range is equivalent to lLSB In IS-bit resolution. ±a.006'!40 01 Full '
Scale Range ia equivalent to lLSB In 14-blt resolution.
5. Adjustable to zero with external trim potentiometer. Adj ....ing the, gain potentiometer rotates the transfer lunctlon around the zero point.
6. Error at input code FFFFH lor OAC700 and OAC701, 7FFFH for OAC702 and OAC703.
'
7. With gain and zero errors adjusted to zero at +25°C.
c.:t
8. Maximum represents the 30' limit. Not l00'!4. tested for this parameter.
C
Ct
9. At the major carry, 7FFFH to 8000. and sooo. to 7FFFH.
10. Tolerance on output impedance and output current is ±30%.
11. Pow~r dissipation is an additional40mW when VDO is operated at +15V.

8....

rM~E~C~H~A~N~IC~A~L~____________--,'rC~O~N~N~E~C~TI~O~N~D~IA~G~R~A~M~________________________-,

l~~]O~I~J ~~

DAC70I, DAC703
+Vcc

27IIIc!l

'ing plane.

!}-----;;-;;;-;:":!=-~'N' ___~ C3)

.. :;];C2)

"::::t: C2)

Voo

111

NO'l'ES:
1. Can be tied to +Vcc Instead of
having separate Veo supply.
2. Oecoupling capacitors are O.lpF to
1.0pF.
3. Potentiometers are lOkOto lOOkO.
4. 5kO (OAC700, OAC70l), lOkO
(OAC702, OAC703). .
5. Amplifier in DAC701, OAC703 only.

CASE: CeramiC, hermetic
MATING CONNECTOR:
0245MC
WEIGHT: 9.2 grams
(0.32 oz.)

6-109

. PIN ASSIGNMENTS
Pin
# .•..

1

2
3
4

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21'
22
23
24

.

.'

DAC7011703

DAC700I7Q?
B~ 1 (MSB)
BWl!
Bit 3
Bit'4
Bit 5
. Bit6
.Bif7
Bit8
Bit9
Bit 10
Bit 11
Bil'12
Bit 13,
Bit 14
Bit 15
Bit 16 (LSB)

Bit 1 (MSB)
Bit 2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9
Bit 10
Bitll
Bit 1·2
Bit 13
BII.14
Bit 15
Bit 16 (LSB)

Dlfferentia.1 Linearity E;rror
Differential Linearity Error (DLE) of a Dj A converter is
the deviation from an ideal ILSB change in the output
:from one adjacent output state to the next. A differential
linearity error specification of ±1{2LSB. means that the
output step sizes can be between Ij2LSB and 3j2LSB
when the input changes from one adjacent input state to
the next. A negative DLEspecification of no more than
-I LSB (-0.006% for 14-bit resolution) ensures monotonicity.
'

VOUT

RFEEDBACK

Voo

-Vee
Common
lour
Gain Adjust
+Vcc
+6.3V Reference Output

Voo
-Vee
Common
-Summing 'Junction (~ero'Adiust)
Gain Adjust
+Vcc
+6.3V Reference Output

Monotonicity
Monotonicity assures that the analog outputWilllltcrease
or remain the same for increasing input digital codes.
The DAC700j701j702j703 are specified to be monotonic
to 14 bits overthe entire specification temperature range.

ABSOLUTE MAXIMUM RATINGS*

av.

Voo to Common .......................................
+18V ,+Vcc to Common,,,.,,,,,,,,,, .. ,, ... ,,,,.,, .. ,,,, .. ,, OV, +18V
-Vee to Common. " " " .. " " , .. " ... " " . " . " . " , ." OV, -18V
Digital Data Inputs (pins 1-16) to Common",.", .. "" -tV, +18V
Reference Out (pin 24) to Common. " Indefinite Short to Common
External Voltage Applied to R, (pin 21, DAC7001702) . " " " . ±18V
External Voltage Applied to D/A Output
(pin 17, DAC7011703) .. , .. , , " .•... , .. , " .... , . " .• -SV to +SV
Vour (pin 17, DAC7011703)." ... , .. " Indefinite Short to Common
Power Dissipation ................................... ~ .. 1000mW
Storage Temperature .......................... -6(}°C to +150°C

·Stresses above those listed under "Absolute Maxlmur:n RatlOg$'" may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.

DISCUSSION OF
SPECIFICATIONS
DIGITAL INPUT CODE.S
The DAC7ooj70lj 7021703 accept complementary digital
input codes in either binary format (CSB, Unipolar or
COB, Bipolar). The COB models DAC702j703 may be
connected by theu.ser for .either. complementary offset
binary (COB) or comple'mentary two's complement
(CTC) codes (see Table I).

.,~CCURA~Y

"Linearity' .
This ~pecification. describes' one of the most important
measures of performance of a Dj A converter. Linearity·
error is the deviati~n of the analog putput from a'
straight line drawn through the end points (all bits ON
point and all bits OFF point).

.'

DRIFT
Gain Drift
Gain drift is a measure of the change in the fuJI-scale
range output over temperature expressed in parts per
million per degree centigrade. Gain drift is established
by: (I) testing the end point differences for each D j A at
tm;n, +25° C and tm,,; (2) calculating the gain error with
respect to the +25°C value; and (3) dividing by the
temperature change.
Zero Drift,
Zero. drift is a measure of the change in the output with
FFFFH (DAC700 and DAC701) applied to thedigitid
inputs over the spedfied temperature range. For the
bipolar models, zero is. measured at 7FFFH (bipolar
zero) applied to the digital inputs. This code corresponds
to zero volts (DAC703) or zero milliamps (DAC702) at
the analog output. The maximum change in offset at tniin
or t max is referenced to the zero error at +25°C and is
divided by the'temperature change. This drift is expressed
iIi parts per million' ()f fuJI scale range per degree
centigrade (ppm of FS.Rj°C).

TABLE [ Digital Input Codes.
Analog Output
Digital
Input
Code.

DAC7001701
Complementary
Straight Binary
(CSB)

DAC702/703
Complementary
Offset Binary ,
(COB)

. DAC7021703
Complementary
Two's Complement
(CTC)'

OOOCh<

+ Full Scale

7FFFH
8000H

+112 Full Scale
+112 Full Scale

+ Full Scale
Bipolar Zero
-ILSB

-ILSB
- Full Scale
+ Full Scale

FFFFH

-ILSB
Zero

- Full Scale

Bipolar Zero

"'Invert the MSB of the COB code with an external Inverter to obtain eTC
code.
'

SETTLING TIME
Settling time of the D j A is the total time required for the
analog output to settle within an error band around its
final value after a change in digital input. Refer ,to Figure
.
I for typical values for this family of products.
Voltage Output
Settling times are specified to ±O,003% of FSR (±Ij 2LSB
for 14 bits) for two input conditions: a fuJI-scale range
change of 20V (DAC703) or 10V (DAC701) and a ILSB
change. at the "major carry,» the point at which the

6-110

0.030

1.0 ....--'T"-"T"~r---.,..r----.,

i

~

;

'0

-g,,~

0.025

ID .,

~ 0.020

..

i!- 0.015

Iii

1I

Q.

~ ~ O.OII------\+---~-t--_;+_--__t

u:'O

e
Ui

c

rn

0.010

0:

~

LL

~
0.001 ..._ _ _ _~--...-""'":~---~~
0.01
10.0

ill

!I

II: II

I II
I
I
I

I

i

0.005

..

1

0
1

Settling Time (p••c)

ill I

'j

'0

.,.92

i:

:1'
1'1

0

""
~~

:!

ii

II

.c:

is ~

~ "
Uilt:

II II i
"~ I ' i '

I

' j

oS

0.11----+-+--+-_-+-\+---;

I ill!

-1 I

:,' I',
,

i

!I I
!
..,15V Supply

,

Iii
I1

:!

I

1.1'

iil
10

I

;! I! I I II
; i'l 1 ,' '

I

ll
100

11
I~ I
Iii

IJ
+15V.
~ Supply

,...

U
Ik

~v
u~

10k

lOOk

Power Supply Ripple Frequency (Hz)

FIGURE 1. Final-Value Error Band Versus Full-Scale
Range Settling Time.

FIGURE 2. Power Supply Rejection Versus Power
/ Supply Ripple Frequency.

worst-case settling time occurs. (This is the worst-case
point since all of the input bits change when going from
one code to the next.)

external load should remain constant.
If a varying load is to be driven by the reference supply,
an external buffer amplifier is recommended to drive the
load in order to isolate the Bipolar Offset (connected
internally to the reference) from load variations:

Current Output
Settling times are specified to ±O.003% of FSR for a
full-scale range change for two output load conditions:
one for 100 to 1000 and one for 10000. It is specified
this way because the output RC time constant becomes
the dominant factor· in determining settling time for
large resistive loads.
COMPLIANCE VOLTAGE
Compliance voltage applies only to current o.utput
models. It is the maximum voltage swing allowed on the
output current pin with the DAC still being able to
maintain specified accuracy.
POWER SUPPLY SENSITIVITY

Power supply sensitivity is a measure of the effect of a
power supply change on the D / A converter output. It is
defined as a percent of FSR change in the output per
percent of change in either the positive supply (+Vce),
negative supply (-Vee) or logic supply (Von) about the
nominal power supply voltages .(see Figure 2). It is
specified for DC or low frequency changes. The typical
performance curve in Figure 2 shows the effect of high
frequency changes in power supply voltages.

OPERATING INSTRUCTIONS
POWER SUPPLY CONNECTIONS

For optimu~ performance and noise rejection, power
supply decotipling capacito~s should be added as shown
in the Connection Diagram. IJ.lF tantalum capacitors
should be located close to the D / A converter.
.
EXTERNAL ZERO GAIN AND ADJUSTMENT
Zero and gain may be trimmed by installing . external
zero and gain potentiometers. Connect these potentiometers as shown in the Connection Diagram and adjust
as described below. TCR of the potentiometers should
be IOOppm/oC or less. The 3.9MO and 270kO resistors
(±20% carbon or better) should be located close to the
D / A converter to prevent noise pickup .. If it is not
convenient to use these high-value resistors, an equivalent
"T" network, as·shown in Figure 3, may be substituted in
place of the 3.9MO part. A O.OOI,..F to O.OIJ.lF ceramic
capacitor should be connected from GAIN ADJUST
(pin 22) to COMMON to prevent noise pickup. Refer to
Figures 4 and 5 for the relationship of zero and gain
adjustments to unipolar and bipolar D/ A converters.

REFERENCE SUPPLY

All models have an internal low-noise +6.3V reference
voltage derived from an on-chip buried zener diode. This
reference voltage, available at pin 24, has a tolerance of
±5% (KH models) and ±I% (BH models). A minimum
of 1.5mA is' available for external loads. Since the output
iropedance. of the reference output is typically 10, the

FIGURE 3. Equivalent Resistances.

6-111

g

t;
C§

+FULL
SCALE

/

ILSB

~

5

~'" '"

:'
i

c

RANGE OF
ZERO ADJ.

,

/"'/ '"/ '

I!:

,

,,,..1/.,/~
,,, "'T

~.-'
ajAr'

::I INPUT = 0'. ?""
ir FFFFH e ~

11 I

.¥~"

BAIN ADJ.
ROTATES
THE LINE

RANGE OF
flAlN ADJ.

RANSE AND
OFFSET

INPUT = OOOOH

ADJUST'

, ZERO ADJ.
' ,~H-+-+_._t-I-+-+--r
" TRANSLATES,-DI8ITAL INPUT
THE LINE
I
-FULL SCALE
DIGITAL IN'UT

FIGURE 4. Relationship of Zero and Gain Adjustments for Unipolar D/A Converters,
'DAC700 and DAC701.
"

FIGURE S. Relationship of Zero and Gain
Adjustments for Bipolar D / A coriverters;
DAC702 and DAC703.
',

Zero Adjustment
For unipolar (CSB) configurations, apply the digital
input code that produces zero vpltage or zero current
output and adjust the zero potentiometer for zero output. .
For bipolar (COB, CTC) configurations, apply the digital
input code that produt:es zero output voltage or current.
See Table II for corresponding cQdes and the Connection
Diagram for zero adjustment circuit connections. Zero
calibration should be made before gain calibration.

Gain Adju~tment

bit IS-

SYSTEM GROUND POINT

independent of the value of RL and can be eliminated by
initial calibration adjustments. The effect of R2 is negligible because it is inside the feedback loop of the output
op amp and is therefore greatly reduced by the loop gain.
If the output cannot be sensed at COMMON (pin 20), or
the system ground point as mentioned above, the differential output circuit shown in Figure 8 is recommended. In this circuit the output voltage is sensed at the
load common and not at the D/A converter common as
in the previous circuits. The value of R6 and R7 must be

±15VIIC
SUPPLY

TO PIN IB_--:-?----l--+-V-t
+ \jIF
COM

+5VOC
SUPPLY

FIGURE 8; Differential Sensing Output Op Amp
Configuration.

6-113

.adjusted for maximum comiii(lIHnode rejection at R L •
Note that if R3 is negligible, the circuit of Figure 8 can be
reduced to the one shown in Figure 7. Again the effect of
R. is negligible..
The DjA converter and the wiring to its connectors
should be located to provide optimum isolation from
, sources of RFI and EMI. The key concept in elimination
of RF radiation or pickup is loop area; therefore, signal
leads and their return conductors shOllld be kept clOSe
together. This reduces the external magnetic field along
. with any radiation. Also, if a signal lead and its return
conductor are Wired close together, they prese!J,t ~ small
flux-capture cross section for. any external field. This
reduces radiation pickUp in the circuit. .
.

'. ·R.. R,. TeR < '±IOppm/o e

FIGURE 10. External Op Amp .. UsingInternal and.
External Feedback. Resistors' to Maintain
Low Gain Drift .

.APPLICATIONS
DRIVING AN EXTERNAL OP AMP WITH
CURRENT OUTPUT D/A's
DAC700 and DAC702 are current output devices and
will drive the summing junction of an op amp to produce
an output voltage as shown in Figure 9. Use of the
internal feedback resistor (pin 17) is required to obtain
specified gain accuracy and low gili:n drift. .

VOUT

FIGURE 11. External Op Amp Using External
Feedback Resistors.

ORDERING INFORMAtiON
MODEL
DAC700KH
FIGURE 9. External Op Amp Using Internal
Feedback Resistors.

.

DAC700 or DAC702 can be scaled for any desired
'voltage range with an external feedback resistor, but at
the expense of increased drifts of up to ±50ppm/oC. The
resistors in the DAC700 and DAC702 ·ratio track to
±lppm/oC but their absolute TCR may be as high as'
±50ppm/oC.
An alternative method of scaling the output voltage of
·the D/A converter.and preserving the low gain drift is
shown in Figure 10.
OUTPUTS LARGER THAN ao-VOLT RANGE
For output voltage ranges larger than ±IOV, a high
voltage op amp may be employed with an external
:feedback resistor. Use lOUT valueS of ±lmA for bipolar
voltage ranges and -2mA for unipolar voltage ranges
(see Figure 11). Use protection diodes as shown when a
high voltage op amp is used.
'
,

DAC700BH
DAC70lKH
DAC7(llBH
DAC702KH
DAC702BH
DAC703KH
DAC7!l3BIt

6-11.4

DESCRIPTION
Current Output, 0 to "':'2mA,
OOC to +70°C
Current Output, 0 to ~2mA,
-25°C to +85°C
Voltage Output, 0 to +19V;
O°C to +70°C
Voltage Output, 0 to +lOV,
"':'25°C to +85°C
Current Output, ±lmA,
O°C to +70°C
Current Output, ±lmA:
-25°C to +85°C
Voltage' Output, ±lOV,
O°C to+700C
Voltage Output, ±10V,
-25°C to +85°C

BURR-BROWN®

DAC70en07
DAC70an09

IElElI

Microprocessor-Compatible
16-BIT DIGITAL-TO-ANALOG CONVERTERS
FEATURES
• TWO·CHIP CONSTRUCTION
• HIGH·SPEED 111-BIT PARAllEL. B·BIT (BYTE)
PARAllEL. ANO SERIAL INPUT MODES
• OOUBlE·BUFFEREO INPUT REGISTER
CONFIGURATION
• VOUT AND lOUT MODELS

• HIGH ACCURACY:
linearity Error ±O.D03% of FSR max
Differential linearity Error ±O.OO6'I0 of FSR max
• MONOTONIC (TO 14 BITS) OVER SPECIFIED
TEMPERATURE RANGE
• HERMETICAllY SEALED

DESCRIPTION
The DAC708 arid DAC709 are l6·bit D/A converters designed to interface to an 8-bit microprocessor
bus .. l6-bit data is loaded in two successive 8-bit
bytes into parallel 8-bit latches before being transferred into the D/A latch. The DAC708 and DAC709
have current and voltage outputs respectively and
are in 24-pin dual.-wide hermetic DIPs. Output codingis Binary Two's Complement (bipolar) or Unipolar Straight Binary (unipolar, when an external logic
inverter is used to invert the MSB). In addition, the
DAC708f709 can be loaded serially (MSB first).
The DAC706 and DAC707 are designed to interface
to a l6-bit bus. Data is written into a l6-bit input

latch and subsequently the D / A latch. The DAC706
and DAC707 have current and voltage outputs
respectively and are in 28-pin dual-wide hermetic
DIPs. Outputs are bipolar only (±lmAand ±IOV
respectively) and have BTC input coding.
All models have Chip Select, Write and Clear controllines as well as input latch enable lines. In bipolar mode, the Clear input sets the D / A latch to give
zero voltage or current output. These converters are
l4-bit accurate and I!re complete with reference and,
for the DAC709 and DAC707, a voltage outpUt
amplifier.

1.m:1IE~'\
CLEAR
WRITE
CHIP SELECT

DAC708f709 Block Diagram

ClIIITIIGL
LOGIC

DAC706/707 Block Diagram

International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85134· Tel. 16021 141H 111 • Twx, 91Q.Q52·1 III "Cabla: BBRCORP . Talax: 66-6491

6-115

SPECIFI'CATIONS
ELECTRICAL
At T. = +25°C, rated power supplies, and allar a 10 minute warm-up unl.... otherwise noted.

I

MODEL

DAC7OII707~

1

MIN

/

MIN

TVP

MAX

UNITS

,

INPUT

c~mpllnt

DIGITAL INPUT
Resolution
Bipolar Input Code
Unipolar Input Code'" (DAC7061709 only)

logic Levels'":

I,
1

DAC7GII707I7G11701iot

MAX

TVP

+2.0
-1.0

VIH

V'L
I," (V, = +2.7V)
I.. (V, = +O.•V)

·

+5.5
+0.8

J
1

,

TRANSFER CHARACTERISTICS

ACCURACY'"
Linearity Error
Differenlial Lln8llrily Error'"
Differential Linearity Error at Bipolar Zero.....
Gain Error'''
Zero Error'?!
Monotoniclty Over Spec Temp. Range
Power Supply Sensitivity: +Vcc
-Vee
V..

16

sinL Two's
Unipolar Straight Binary

.

··
·
···

±a.0015

±a.OO3

::1;0.003

±a.OO6

±a.0015

±a,003

. ±a.OO3

±a.os
±Ii:os '

±a.l0
±a.'1

±a.07,

±a.0015
±a.0015
±a,oool

±a.OO3
±a.OO3

14
,

±a,001

D"IFT (over specification

·

BilO

·
··

V
V
/lA
/lA

±a.OO6
±a.15

'11101 FSR'"
'III of FSR
'IIIoIFSR
'III
'IIIoIFSR
BIIO
'IIIoIFSR~Vcc

±a,.006
±a,006

'III of FSRI'IIIVcc
'11101 FSRI'IIIVDD

tempei'atu~ rangel~ ,

Gain Drill
Zero Drill: Unipolar (DAC7061709 only)
Bipolar
Differential Linearity Over Temp'"

±7
±1,5
±4

Linearity Error Over Temp'"
SETTLING TtME (to ±0.003'III of FSR)'"
Voltege Output Models
Full Scale Step (2kO load)
lLSB Step at Worst Case COde""
Slew Rate
Current Output Models
Full Scale Step (2mA)
10 to 1000 load
lkO load

±15
±3
±10
+0.009,
-0.008
±a.OO6

4

,

350
1

CURRENT OUTPUT MODELS
Output Current Range
DAC708 Unipolar (USB Code)""
Bipolar (BTC Code)""
DAC706 Bipolar (BTC Code)""
Unipolar Output Impedance""
Bipolar Output Impedance"·'
Compliance Voltage

010-2
±1
±1
4.0
2,46
±2,5

+13,5
-13,5
+4,5

··

+16.5
-16,5
+5.5

+10
-13
+5
+16
-18
+5
370

+25
-25
+10
+30

-30

+10

640
790

535

6-116

ppml"C
ppm 01 FSRI"C
ppm 01 FSRI"C
'IIIoIFSR

··
·

·
··

··
··
·

/l88C
/l8ee
'VI/l88C

naee

V
V
V
mA
0

mA
mA
mA
kO
kO
V

···

+15
-15
+5

i

/IfI8C

·

POWER SUPPLY REQUIREMENTS

Voltage: +Vcc
-Vee
Voo
Current (No Load)
Current Output Models: +Vcc
-Vee
Voo
Voltage Output Models: +Vcc
-Vee
Voc
Power Dissipetion: Current Output Model.
Voltage Output Models

·

··
·

±5

0.15
Indefinite

±5

·

Oto+l0
±5,±10
±10

Short Circuit to Common Duration

±12

·

8

OUTPUT
VOLTAGE OUTPUT MODELS
Output Voltage Range
DAC709 Unipolar (USB Code)
Bipolar (BTC Code)
DAC707 Bipolar (BTC Code)
Output Current
O~tput Impedance

±25'

±5

''IIIoIFSR

•

2,5

10

±10
±2.5

·

·
···
··
·
··

V
V
V
rnA
mA
mA
mA
mA
mA
mW
mW

I

MODEL

I

DAC7OII707I7081701BH

I

MIN

I

I

-25
-85

I

TV...

DAC7C1117D7I7C111701KH

I

MAX

I

MIN

I

I

+85
+150

I

0

I

TVP

I

MAX

I

+70

I
I

UNITS

TEMPERATURE RANGE
Specification
Storage

.

I

~C

'C

'Speciflcation same ea for DAC706170717081708BH.
NOTES: (1) MSB mull be inverted externally prior to DAC7081709 input. (2) Digital inputs are TTL. LSTTL. 54174C. 54174HC and 54174HTC competlble over the
specified temperatura range. (3) DAC706 and DAC708 (current"output models) are specified and tested with an exlernal oulpUI operational amplifier connected
using Ihe internal feedback resl810r In alll.sts. (4) FSR means Full Scal. Rang•. For example. for ±10V OUlput. FSR = 20V. (5) ±a.0015% of Full Scale Range is
equal to.l LSB In III-bit resolution. ±O.OO3% of Full Scale Range Is equal 10 1 LSa in 15-bit resolulion. ±a.OO8% of Full Scale Range is equal to 1 LSB in 14-blt
" resolution. (8) Error at input code oooOH. (For unipolar connecllon on DAC708l709lhe MSa musl be Inverted exlernally prior to D/A inpul.) (7) Adjustable 10 zero
with exlernallrlm pOlenllometer. Adjusting the gain potentiometer rotates thelransfer fucntion around the bipolar zero point. (8) Maximum represents the 30' limit.
Not 100% tested for this paremeter. (9) The bipolar worst-case code change is FFFFH to ooooH and OOOOH to FFFFH. For unipolar (DAC7081709 only) II is 7FFFH 1,0
8000H and 8000H to 7FFFH. (10) Tolerance on outpul impedance and outpul currenl is ±30%.

CONNECTION DIAGRAMS
DAC708/709
(2J

::x:

+

VOD

...

NOTES,
1._111l1li01010lIl<0,
2, DtclujlIIIIII CIIIICi..... If' 0.1"" 1I'1,Q,d',
-Woe

DATA
INPUTS

DAC7061707
NOTES, I. PaIOnulNlotirs .ro 10kO to 10lIl<0,
Z. Dlcaupllnl clpacltlrl Ire O.lpF 10 l.Opf.

VOUl

Woo

01

caM
3,9MO

&I
IA

GAIN AOJ,

D4

+Voe

-v
DIGITAL
INPUTS

\ClR
CONTROl LINES .

Wi

la

OIA
LArCH

DB
DID

\ A,

I

1-

LATCH ENABlE LINES) A,

\(IIII)DI5

DIGITAl. INPUTS)
(

014

-,------------------~-

J

OESCRtPl'ION OF "PIN FUNCTIONS
DAC708I7tI7

'"

Designator

,

Peacrlption

DAC708I7OI

,. Pin
#

Designator

Voltage output for OAC707 or an Intarnal feedback
resistor for use with an external output op amp for the
OAC706.

1·

Aa

Latch enable for O/A latch (Active low)

Voo,

,logic supply (+5V)

2

A:;;

Latch.!nable..!or "Iowbyta" Input (Active low). When
both A" and AT ana logic "0", the serial input mode is
selected and the serial Input Is enabled,

COM

Common

3

A,

latch enBble for "high byte" Input (Active lOw). When
both A;; and A; are logic "0", the serlillinput mode Is
select~and the sertallnpui Is enabled.

SJ (OAC707)
lauT (OAC706)

Summing Junction of the internal output op amp for the
OAC707, or the currant output for the OAC706, Offset
adjust circuit Is connected to the summing junction of
the output amplifier. Reier to Connection ~iagram,

4

07(015)

Input for data bit 7 if enabling low byta (LB) latch or
data bit 15 if enabling the high byte (HB) latch.

GA

Gain Adjust pin. Refer to Connection Diagram lor gain
adjust circuit.

5

06(014)

Input lor data bit 6 il enabling LB latch or data bit 1411
enabling the HB latch,

+Vee

Positive supply voltage (+15V)

6

05 (013)

Data bit 5 (LB) or data bit t3 (HB)

-Vee

Negative supply voltage (-15V)

7

04(012)

Data bit 4 (LB) or data bit 12 (HB)

CUi

Clear line. SetS the input latch to zero and seta the O/A
latch to the input code that gi_ bipolar zero on the
O/A output (Active low)

8

03(011)

Data bit 3 (LB) or data bit 11 (HB)

WR

Write control line (Active low)

Cs

Chip select control line (Active low)

A,

Enable lor OIA converter latch (Active low)

Ao

Enable lor input latch (Active low)

12

OCOM

015 (MSB)

Data bit 15 (Most Si~nlflfa~t Bit)

13

RN

014

Data bit 14

14

VOIJT
AFT (OAC708)

013

Data bit 13

15

ACOM

Analog common

012

Data bit 12

16

SJ (OAC709)

Summing junction of the internal output op amp for the
OAC709, or the current output for the OAC708, Reier to
Connection Diagram lor connection 01 external op amp
toDAC708.

'.

,

Desc;rlptlOn

VOUT (OAC7071
RF(OAC706)

,

;

9

02(010)

Data bit 2 (LB) or clata bit 10 (HB)

10

01(09)

Data bit 1 (LB) or data bit 9 (HB)

11

00(08)/51

Data bit 0 (LB) or data bit. 8 (HB), Serial input when serial
mode is selected.

lauT (OAC708)

011

Data bit 11

17

Digital Common
, Feedback resistor. lor lnternal or extarn.1 operational
amplifier. Connect to pin 14 when a 10V output range is
desired. Lasve'open for a lOV output range,
Voltage output lor OAC709 or feedback resistor lor use
with an external output op amp for the OAC708. Refer to
Connection Diagram fo, connection of external op amp
toDAC708,

,BPO

Bipolar offset. Connect to pin 16 when operating in the
bipolar mode. Las.. open lor uni~lar mode.
Gain Adjust pin

010

Data bit 10

18

GA

09

Data bit 9

19

+Vee

Positive supply voltage (+15V)

08

Data bit 8

20

-Vee

Negative supply voltage (-15V)

07

Data bit 7

21

CLR

Clasr line. Seta the high and low byte input reglstera to
zero and, for bipolar operation, seta the O/A register to
the input code that gl_ bipolar Zero on the OIA oulput~
(In t~e unipolar mode, Invert the MSB prior to the O/A.)

06

Oatabit6

22

WR

Wrlta controiline

05

Data bit5

23

Cs

Chip select control line

04

Data bit 4

24

VQO

Logic supply (+5V)

03

Data bit 3

25.

No pin

02

Data bit 2

26

'No pin

01

Data bit 1

27

No pin

DO (LSB)

Data bit 0 (Lasst Significant BII)

28

No pin

6-118

(The OACT08 and DAC709 are in 24-pin peCkages)

MECHANICAL

DAC7061707
DAC70S/709

I: ~

.

M

gl

LDJJ r : ]J

Pin 1

2

"

I

12

INCHES

I

DIM

; DIM

.81

A
8

C.J

C

0
F
G
H

J
K
L

N

N

MI'

MAX

MILLIMETERS
MI.
MAX

1.435 1.415 38.45 37.21

16.41 BASIC
4.08 . 5.21
.48
.38
1.14
1.40
2.154 BASIC
2.41
.08S
1.40
.23
.30
.012
.185
3.84
4.86
SASIC 15.24 BASIC
.030
.78

.810 BASIC

.110 .205
.015
.Ote
.056
.0415
.100 BASIC
.0156
.009
.1155
.800
.020

."

TABLE I. Digital Input Codes.

ABSOLUTE MAXIMUM RATINGS

Analog Output

Voo to COMMON ........................................ OV, +1SV
+Vcc to COMMON ...................................... OV, +1SV
-VcctoCOMMON ...................................... OV,-1SV
Digital Data Inputs to COMMON. . • • • . • • • . . • . . • • •. -o.SV, Voo +O.S
DC Current any Input .................................... ±10mA
Reference Out to COMMON. . . . • • . •. Indefinite Short to COMMON
External Voltage Applied to R.
(pin 1, DAC708; pin 13 or 14, DAC708) .............. , .. .... ±1SV
External Voltage Applied to D/A Output
(pin 1; DAC707; pin 14, DAC709) ........................... ±SV
VOUT (DAC707, DAC709) • • • . • . • . • . . .• Indefinite Short to COMMON
Power Dissipation. • • • . . • • • • • • . • • • • • . • . • • . • . . . • . • • • . • . ... 1000mW
Storage Temperature .. . • • • . .. . • . .. .. • . • . • • • . • • .. -60"C to +1S0'C

Digital
Input
Codes

Unipolar Streight Blnaiy'u
(DAC7081709 only; connected for Unipolar operation)

Binary Two's Complement
(Bipolar operation;
all models)

7FFFH
oooOH
FFFFH
8000H

+112 Full Scale -1 LSB'"

+Full Scale
Zero
-1LSB
-Full Scale

Zero
+Full Seele
+112 Fuli Scale

(1) MSB must be inverted externally.

(2) Assumes MSB Is Inverted

externally.

Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. Exposure to abaolute maximum conditions for extended perlod8 may affect devlca reliability.

ACCURACY

DISCUSSION OF
SPECIFICATIONS
DIGITAL INPUT CODES

For bipolar operation, the OAC706/707/708/709 accept
positive-true binary two's complement inpJlt code. For
unipolar operation (OAC708/709 only) the iIiput code is
positive-true straight-binary provided that the MSB
input is inverted with an external inverter. See Table I.

Linearity
This specification describes one of the most important
measures of performance of a D/A converter. Linearity
error is the deviation of the analog output from a
straight line drawn through the end points (-Full Scale
point and +Full Scale point).
Differential Linearity Error
Differential Line-arity Error (OLE) of a 0/ A converter is
the deviation from an ideal ILSB change in the output
when the input changes from one adjacent code to the
next. A differential linearity error specification of
±1/2LSB means that the output step size can be between
1/2LSB and 3/2 LSB when the input changes between

6-119

. adjacent codes. A negative·PLE specification of -ILSB
maximum (-0.006% for 14-bit resolution) insures mono, t~nicity.
Monotonicity

Monotonicity assures that the analog outPUt will increase
or remain the same for increasi!lginput digit!!,1 codes.
The DAC706/70717081709 are specified to be monotonic to 14 bits over the entire specification temperature
range.
DRIFT

Voltage Output

· Settling times are specified to ±0.003% of FSR (±1/2LSB
, for 14 bits) for two input conditions: a full-scale range
change of 20V for bipolar or 10V for unipolar and 'a
· ILSB change at the "major carry", the point at which the
· worst-case settling time occurs. (This is the wprst-case
: point since all of the input bits change when going from
· one code to the next.)
,
Current Output

Gain Drift

.,.'

final value. after a changein.digital input: R~i~ to.:~l'e
I for typical values fpr this .family' of products.

Gain drift is a measure of the change in the full-scale
range output over temperature expressed in parts per
million per degree centigrade (ppm/°C). Gain drift is
established by: (1) testing ~he end point differences at tml.,
+25°C and t max; (2) calculating the gain error with
respect to the +25 9 C value; and (3) dividing . by the
. temperature change:'
Zero Drift

Zero drift is a measure of the change in the output with
OOOOH I!:pplied to he D I A converter inputs over the specifiedtemperature range. (For the DAC7081709 in unipolar mode, the MSB must be inverted.) This code corresponds to ze~o volts (DAC707 and DAC709) or zero milliamps (DAC706and ·DAC708) at the analog output.
The maximum change in offset at tml. or tm" is referenced
to the zero error at +25°C and is divided by the temperature change. Thisdrift is expressed in FSR/oC.
SETTLING TIME
Settling time of the D I A is the total time required for the
analog output to settle within an error .band around its

Settling times' are specified to ±0.003% of FSR fora
full-scale range change for two output load conditions:
one for IOn to lOon a!ld one for looon. It is specified
this way because the ouput RC time constant becomes
· the dominant factor in determining settling time for
large resistive loads.
COMPLIANCE VOLTAGE
Compliance voltage applies only to current output models. It is the maximum voltage swing allowed 'on the
output current pin while still being able to maintain specified accuracy.
POWER SUPPLY SENSITIVITY

Power supply sensitivity is a meaSure of tht; effect of a
change in a power supply voltage. on the D'tA co.nverter
output. It is defined.as a pertent of FSR change in the output per percent of change in either the positive suppiy
(+Vee), negative supply (-Vee) or logic supply (Voo)
about the nominal power supply voltages (see Figure 2).
It is specified for DC otlow frequency changes. The
typical performance curve in Figure 2 shows the effect of
high frequency changes in power supply v6ltages.

0.030 r-T'"T"nT~"""''''''''''''''''--''''''"nTrm-...,...,....ri'm''--''''''''''''';'

---.,...-.,......,1"'---..,.,...----,

. ! : ill,

1.0 .....

~

it

;

15

.E

-'"

~[

III "

o c

aE~

#

I'lill

"

, :ii"

illl

i.l'l

~

:t~
~ &. 0.01 t-----+t----t--~t__\r+---_I

o

II

a:

!

15

:'(

~

I'

f

i

~ II

" II

I

'

I

'II

I
j" ~l~V
:1 '
l
Supply
# 0.005 t-t-+ttttttr----r--'+H+Hl--+--t+
!1+ti!l--+-++l+~~-;-rtmMlI
: Ii,. I
'J
'11'
i
~
~

~

" '(

iii

°1t;~~~10~~~~100;:~~~1~k:tlt~10~k~ft~100~kl

...._~
10.0

0.OO1~_---~--il-~~--

Settling ')me iPSeC)'

po';'er Supply Ripple

FIGURE 1. Fin8I-Value Error B;md Versus Fuil-Scale
Range' Settling Time:
.

!

'Iii, [':1 iii
0.Q15I-Httttttt-4-++HHt-t+ttttttt-+++H++lt-H1-l+1lII
I

~W0.0101-t+ttttttt---+--+t-H++lt-t++t+Ittt-+++H++lt--llttttllll
:11
: " fill,:
I!
II !I

".!!

:i ~

0.01

, :Iii
,I'I

1+1:t - !

~ 0.020 t-t-+ttttttr-+T+I+ti!t--+--t-++tH!t--l--t+H+Hl--PIooll+lllI
!l!
I !I
i !
I
11"'1

~ ~ 01 t-~--+--+--t---~~--,---I

u:::

III!!I! II:ii[I.,. 'lil,I!'!

+.~t+tl!"'it-'+.-t+HliI'II+-I.~.......,·''ri! ~'t'tfi1+!1
I I II' Ii. :, !Iil
: ~l~J ~~pp~,YI

i ,:

{ 0.025

FreqU8n~y

(I-Iz)

FIGURE 2. Power Supply Rejection Ve'rsus Power
Supply Ripple Frequency. . .' ,

. 6-120

OPERATING INSTRUCTIONS
POWER SUPPLY CONNECTIONS
For optimum performance and noise rejection, power
supply decoupling capacitors should be added as shown
in the Connection Diagram. II'F tantalum capacitors
should be located close to the D/A converter.

+FULL
SCALE

'---0

3.9MO

= <>-------'"lSOkO,

.L

• -"

ILSB

J.,

~

~

:=
RANGE OF

4

• .-' -"

~

!!

EXTERNAL ZERO AND GAIN ADJUSTMENT
Zero and gain may be trimmed by' installing external
zero and gain potentiometers. Connect these potentiometers as shown in the Connection Diagram and adjust
as described below. TCR of the potentiometers should
be lOOppm/oC or less. The 3.9MO and 270kO resistors
(±20% carbon or better) should be located close to the
D / A converter to prevent noise pickup. If it is not convenient to use these high-value resistors, an equivalent"T" network, as shown in Figure 3, may be substitued in place of the 3.9MO resistor. A O.OOII'F to
O.OII'F ceramic capacitor should be connected from
GAIN ADJUST (pin 22) to COMMON to prevent noise
pickup. Refer to Figures 4 and 5 for the relationship of
zero and gain adjustments to unipolar and bipolar D / A
converters.

0-------"'

_lJT -

"''*RANGEDF

,¢::'

GAIN AOJ,

./!~~\

::

INPUT =
OOOOH j

ir

ZERO ADJ'll / ..
ZERO ADJ.
",.
TRANSLATES.-THE LINE
I

¥

.;.-

GAIN ADJ.
ROTATES

~

INPUT = FFFFH

THE LINE

J

I
DIGITAL INPUT
I

I

I

I

t

FIGURE 4. Relationship of Zero and Gain Adjustments for Unipolar D/A Converters,
DAC708 and DAC709.

.r----.I..----.J·"~

lSOkO

IOkol
FIGURE 3. Equivalent Resistances.
RANGe AND
OFFSET
ADJUST

Zero Adjustment
For unipohir (USB) configurations, apply the digital
input code that produces zero voltage or zero current
output and adjust the zero potentiometer for zero output.
For bipolar (BTC) configurations, apply the digital
input code that produces zero output voltage or current.
See Table II for corresponding codes and connection
diagrams for zero adjustment circuit connections. Zero
calibration should be made before gain calibration.

FIGURE 5. Relationship of Zero and Gain Adjustments for Bipolar D/A Converters,
DAC7061707 and DAC7081709.

TABLE II. Digital Input And Analog Output Voltage/Current

Relationship~.

VOLTAGE OUTPUT MODELS
Analog Oulpul
Digital

Inpul
Code
One LSB
FFFFH
.OOOOH

Analog Oulput
Digilal

'Unipolar (DAC709)

Input

16·Bil

15-Bil

14-Bil

Units

153
+9.99985
0

305
+9.99969
0

610
+9.99939
0

pV
V
V

Code
One LSB
7FFFH

6000..

Bipolar (DAC707 'and DAC709)
16-Bil

15·Bil

14-Bil

305
+9.99960
-10.0000

610
+9.99939
-10.0000

1224
+9,99978
-10.0000

Units

pV _
V
V

CURRENT OUTPUT MODELS
Analog Output
Digital
Input
CodeOne LSB
FFFFH
OOOOH

Analog Output
Digital
Inpul
Coda

'Unipolar (DAC706)
16-Bit
0.031
-1.99997 .
0

15-Bit

14·Bit

Units

0.081
-1.99994
0

'0.122
-1.99988
0

pA

rnA
rnA

.One-LSB
7FFFH
8~

·MSB assumed to be Inverted externally.

6-121

Bipolar (DAC708 and DAC708)
16-Blt

15·Bit

14-Bit

Units

0.031
-0.99997
+1.00000

0.081
-0.99994
+1.00000

0.122
-0.99988
+1.00000

pA
rnA
rnA

Gain Ad'uitment .

The maximum <:io<:k rate of the latc.hes is 10MH;z:. The
minimum time betwe~n write (WR) pulses for successive
enables is 20nsec. In the serial input mode (DAC708 and
DAC709), the maximum rate at. which data ,can be
clocked.into the input sbift register is 10M Hz.
The timing oCthe contro.! signals is given in Figure 6.

Apply the digital input that gives the maximum positive
output voltage. Adjust the gafn potentiometer for this
positive full-scale voltage. See Table II for positive fullscale voltages and the Connection Diagram for gain
adjustment circuit connections.
, INTERFACE LOGIC AND TIMING
DAC70an09

DAC706n07

The DAC706P07, interface timing is the same as that
described above except instead of two 8-bit separatelyenabled input latches, it has a single l6-bit input latch
enabled byAo. The D1A latch is enabled by A.. Also,
there is no serial-input mode.

The signals CHIP SELECT (CS), WRITE (WR), register, enables (Ao, A;, and A;), and CLEAR (CLR),pro~
vide the control functions for the microprocessor inter~
face. They are all active in the "low" or logic "0" state.
CS must be low to aceessany of the registers. Ao' and. A;
steer the input 8-bit data byte to the low- or high-byte
input latch respectively. A; gates the contents of the two
input latches through to the D/A latch in parallel. The
contents are then applied to the iilput of the D 1A converter. When WR goes low, data is strobed into the latch
or latches which have been enabled.
The serial input mode is activated when both Ao and A;
are logic "0" simultaneously. The DO (D8)1 SI input data
line accepts the serial data MSB first. Each bit is clocked
in by a WR pulse. Data is strobed through to the D/A
latch by Az going to logic "0" the same as in the parallel
input mode.
Each of the latches can be made "transparent" by maintaining.its enable signal at-iogic "0;'. However, autated
above, whenbothAo and,A; are logic "0" at the same
time, the serial mode is seleCted.
LOGIC TIMING· Parallel II' Serial Dill Input

t.w

lew

Iwp

IoH

TIMING DIAGRAM

DatI valid" end aI Viii
Ci valid" end of Wii
iii. Ai. Ai valid \0 IIId II Wii
Wrlll pulu width
DatI blld after end 0/
~

~

DAC708 AND DAC709

Om T••penlUra
1IIIC.1l1n.

low

INSTALLATION
CONSIDERATIONS

IIIIC. ...II.

80
80
80
80

o

Wii

.~

I/ r - - ~~_Ft.w--l

Ci - -......

AiI,AI, A!

':

lew

t:

DO-D1~5.=-::SI~-~--""*

'.

,,.-__

I~

low-l

I )(

~
. . I-10H-1
IwP:j

. W i i - - - -...'t'"~,~

7":--:--~

FIGURE 6. Logic Timing Diagram.'
The CLR line resets both inplit latches to all zeros and
sets the D1A latch to 8000". This is the binary code that
gives a null, or zero, at the output of the D 1A· in the
bipolar mode. In the unipolar mode"activitating CLR
will cause the output to go to one-half of full scale:

Due to the extremely-high accuracy of the D 1A converter, system design problems such as grounding 'and contact resistance become very important. For a l6-bit converter with a +I.OV full-scale range,lLSB is 153"V. With
a load current of SmA, series wiring and connector
resistance of only 30mO will cause the output to be in
error by ILSB. To understand what this means in terms
of a system layout, the resistance of typical I ounCe
copper-clad printed circuit board material is approximately 1/2mO per square. In the example above, a 10
. milliinch-wide conductor 60 milliinches long would cause
a lLSB error.
In Figures 7 and 8, lead and contact resistances are
represented by Rl through Rs. As long as the load resistance RL is constant, R2 simply introduces a gain error
and can be removed with gain calibration. R3 is part of
RL if the output voltage is sense,d at COMMON (pin 15).
Figures 8 and 9 show two methods of connecting the
,current output.mdoel (DAC708) with an external precision output op amp. By sensing the output voltage at the
load resistor (connecting RF to the output oCthe amplifier at RL) the effect of Rl and R2 is greatly redu~d. Rl
will cause a gain error but is independent of the value of
RL and can be eliminated by initial calibration' adjust, ments., The effect of R2 is negligible because it is inside
the feedbaCk loop of the output op amp and is therefore
greatly reduced by the loop gain.
In many applications it is impractical to sense the output
voltage at ANALOG COMMON" pin 15. Sensing the
output voltage at the system ground ,point is permissible
with the DAC708 and DAC709 becausetbey have
separate analog and digital common lines and the return
current is a near-constant 2mA and varies by only IO"A
to20"A over the, entire input code range. ~ can be liS
large as 30 without adversely affecting the linearity of
the D/A converter. The voltage drop across ~ is constant and appears as a zero error ihat can be nulled with
the zero calibration adjustment.
Another approach senses the outpUt at the load as
shown in Figure 9. In this circuit the,output voltage is

6-122

DAC7lJ6 OR DAC708

FIGURE 9. Alternate Connection for Ground
Sensing at the Load (Current Output
Models).
sources of RFI and EMI. The key to elimination of RF
radiation or pickup is small loop area. Signal leads and
their return conductors should be kept close together
such that they present a small flux-capture cross section
for any external field.

FIGURE 7. DAC709 Bipolar Output Circuit (Voltage
Out).

DAC706 AND DAC707
The above considerations are all applicable to the
DAC706 and DAC707 except there is only one COMMON pin (pin 3). Refer to Figures 9, 10, and II. The
ground currents in the ANALOG COMMON of the

1lAC7118

12 MITAL
COMMON

"R.
+w",
+
~I" ANAl06

+W"
ANAl06
COMMON

/"

±Vcc
SUPPLY

/"

-Woo

SYSTEM
UOUND

±Vcc
SUPPLY

DIGITAL

~ COMMON
Woo
SUPPlY

+

COMMON

-Woo

SYSUM
GROUNO

MilA(
COMMON

IJIf

+
.~

'l

Woo

Woo
SUPPLY

v••

FIGURE S. DAC70S Bipolar Output Circuit (with
External Op Amp).

FIGURE 10. DAC707 Output Circuit (Voltage,
Bipolar).

sensed at the load common and not at the D/ A converter
common as in the previous circuits. The value of R6 and
R7 must be adjusted for maximum common-mode rejection across RL. The effect of R. is negligible as explained
previously.

DAC70S!709 are also present in the COMMON pin of
the DAC706!707. There is also an additional codedependent ground current from the digital interface circuitry that flows through pin 3. Again, the effects of this
component of the ground current can be minimized by
using pin 3 as the sense point.

The D/A converter and the wiring to its conneCtors
should be located to provide optimum isolation from

6-123

APPLICATIONS
LOADING THE DAC709 SERIALLY ACROSS AN
ISOLATION BARRIER
A very useful applicatiOtl of, the DAC709" is in achieving
low-cost isolation that preserve~, high: accuracy. Using
the serial input feature of the input register pair; only
three signal lines need to be isolated. The data is applied
to pin II in a serial,bit'Stream, MSB first. The WRinput
is used as a data strobe, 'clocking in' each data bit. A
R~SET signal is provided for system startup and reset.
These three signals are each optically isolated. Once the
16 bits of serial data have been strobed into the input
.register pair, the data is strobed through to the D / A
,register by the "carry" signal out of a 4-bit binary synchronous counter that has counted the 16 WR pulses
used to clock in the data. The circuit diagram is given in
Figure 13.
SYIlCtlIIOIIOUS BINARY COUNTER

FIGURE II. DAC706 Output Circuit (Bipolar, with
External Op Amp).

DAC706J1Ol

3 CDMMON
TO LDAD COMMON

FIGURE 12. Kelvin Connection Grounding for
DAC706j707.
.
In situations where this is not possible, the output signal
may be sensed at the system ground point by either
maintaining the return Ic:;ad resistance below O.04sJ (tp
keep the error from this source to ±O'.003% of FSR max)
or by using Kelvin sensing as shown in Figure 12. An
operational amplifier connected as a unity-gain follower
is used to reference the D/A common to the system
ground. Iri addition, the varying ground current is
"soaked up" by'the op amp, eliminating the ground drop
'problems that would result in runnirtg the ground cur- '
rent throughR4. The input offset and offset drift of the
amplifier will add directly to the zero error and iero drift
of the D/ A converter.

+
POWER

sumy "
VJI).TABE
I

L _ ISIILATIOII BARRIER
DATA STROpE
SERIAL INPUT

i2

~

... --v-v-vr-

,'"

,I,.·

,~... ~

, 'LI

ANALOS
OUTPUT

~-----'---"'"""-'fVV--

FIGURE 13. Serial Loading of Electrically Isolated,
, DAC708/709.

CONNECTING MULTIPLE DAC707'S TO A 16-BIT
MICROPROCESSOR BUS

Figure 14 illustrates the method of connecting multiple
OAC707's to a l6-bit microprocessor bus. The cir-cuit
shown has two OAC707's and uses only one address line
to select either the input register or the Of A register. An
external address decoder selects the desired converter.

FIGURE 14. Connecting Multiple OAC707's to a 16Bit Microprocessor.

ORDERING INFORMATION
MOdel
DAC706BH
DAC706KH
DAC707BH
DAC707KH
DAC70SBH
DAC70SKH
DAC709BH
DAC709KH

Temperature Range
. -25 to +85"0
o to +70"0
-25 to +85"C
o to +70"C
-25 to +85"C
Oto+70"C
-25 to +85"C
Oto+7O"C

6-125

Input Configuration

Output Configuration

l6-bit Port
l6-bltPort
l6-bH Port
l6-bHPort
6-blt PortlSerial Input
6-bit PortlSeriallnput
8-bit PorUSeriallnput
8-bit PorUSerial Input

Current Out
Current Out
Voltage Out
Vo~ageOut

Current Out
Current Out
Voltage Out
Voltage Out

BURR-BROWN®

DAC800
DAC800P

I ElEiI I

Integrated Circuit
DIGITAL-TO-ANALOG, CONVERTER
FEATURES
• LOW COST HIGH RELIABILITY SINGLE·CHIP
REPLACEMENT FOR INDUSTRY STANDARD DACBD
• 12·B11 RESOLUTION
• ±1I2LSB MAXIMUM NONLINEARITY, DoC to +7o°C
• GUARANTEED MoNOToNICITY, DoC to +7o°C
• DUAL·IN·L1NE PACKAGE WITH INDUSTRY STANDARD
(DACBOI PINOUT.

imum gain drift and guaranteed monotonicity, all
over O"C to + 70"C. In the. bipolar configuration, total
·drift is guaranteed to be less than-25ppm of FSR I "c.
The DAC800 is in a 24-pin d ual-in-line package with
the popular DAC80 pinout. Two package options
are ·available:a hermetic ceramic side-brazed package and a low-cost molded plastic package (voltage
out only).
For designs that require a wide temperature range,
see Burr-Brown models DAC850 and DAC85I.

• HERMETIC PACKAGE (optional I
VOLTAGE MODEL

• TWO PACKAGE OPTIONS: hermetic side·brazed and
molded plastic

8.3V REF OUT

• GUARANTEED SPECIFICATIONS WITH ±12V AND
±15V SUPPLIES

GAIN ADJUST

DESCRIPTION

COMMON

The DAC800 is a third·generation monolithic
Integrated Circuit that is a pin-for-pln equivalent to
the industry-standard DAC80 first introduced by
Burr,-Brown, It has all of the functions of its
predecessor plus faster settling time and enhanced
reliability because of its monolithic construction,
The current output model ofthe DAC800 is a singlechip integrated circuit ~ontaining a subsurface zener
reference diode, high speed current switches, .and
laser-trimmed thin-film resistors, The DAC800
provides output voltage ranges of ±2.5V, ±5V,
±IOV,O to +5V, 0 to +IOV (V models) or output
current ranges of±I:175mA or 0 to -2.35mA (I
model).
This high accuracy converter offers a maximum
nonlinearity error of ±lj2LSB, ;t30ppmj"C max-

SUMMING JUNCTION

+VCC

20VRANGE
10VRANGE
BIPOLAR OFFSET
REF INPUT
'OUT
'Vee
lOGIC SUPPLY

Patents pending may apply upon the allowance and issuance of patents
thereon. The product may also be covered in other countries by one or
more international patents.

Iniernatiooal Airport Industrial Park· P.O. Box 11400· TuC$OO. Arizona 85734· Tel. \6021 746·111t • Twx: 9,10·952:1111 • Cable: BBRCORP· Telex: 66·6491

6-126

SPECIFICATIONS
ELECTRICAL
TYPical at +25°C and ±Vcc

MECHANICAL

= 12\1 or 15V unless otherwise noted.

,

PARAMETER

MIN

TYP

MAX

UNITS

"

bib;

16.5

+0.8

VDC
VDC

+20
-0.36

.A
mA

DIGITAL INPUT
Resolution

L.ogiC Levels

(over spec. temp ,ange)'"
V/tf (Logic ",")
V,~ (Logic "0")
I," (VIN '" 1-2.4VI

+.
0

= +O.4V)

ACCURACY
Linearity Error at 25° C

.,12

LSB
LSB

±1l4
±1/2
±0.1

+1, -3/4
±O.3

±O.06

±O.15

~o'FSR':IJ

POWER SUPPLY IENlmvlTY
+15V and +5V Supplies

±O.OOO1
±O.OO3

±0.001
>0.006

'of FSRI16.Vcc;

-15V Supply

D.fferent.al Linearity Error
Gain e"o,-l"
Offwt Error'lI

.

~ofFSR/~Vcc;

lor the bipolar connection)
Total."or over DoC to +70"C' 51

"

DIM
A

1.185

C

.105

F
G

>0.06
±0.05
.,0
±1
.7

1:0.15

"01 FSR

J

±O.12

'lSofFSR
ppmioC

K
L

ppmot FSRrc

M

..

N

.00S

1.S
1S

VI....,

REFERENCE VOLTAGE OUTPUT
Current (for external loadS). Source
rampeo 01 Drift

1:2.S, :tS. ±10, 0 to +5,0 to +10
±5
0.05
Indefinite

±0.88
010 1.76

±1.175
010 -2.35
3.1

±1.47
010 -'2.94

...-6.23
1.S

n

mA
mA

+2.5

V

'"

T«IIPERATURI RANGE
Specification
Operating'"
SIOIage

0.20

0.30
8.10
1S.24 BASIC
10"
0 ....
1.52

10.15 oz. I

3.0.

-

10"
.060

DAC800P

'r

O·
_

... 4.5

2S

-60

1 (0.25mm)

R at

MMC at seating

plane.

Sealing

·d:~--L----

0

..

t..,
... , .....
"'
"" 1.21a
31.32 32.al
•B 1.233
.638 .6715 13.87 14."
I~'

"' ...

-+ ~!~
F

G
H

J

+6.37

V
mA

•

.30

ppm/DC

M

,1S
+5.0

H6.S
+16.5

VDC
VDC

.8. 20

+12. -25
+10

mA
mA

+70
+85
+100

·C
·C
·C

+7

NOTE
Lear.ts :in true poei·
tion within 0.010"

Plane

N
~11.4

V..
Supply Dram
+15V, -15V (no load)
85V (lOgic supply)

CASE: Ceramic
MATING CONNECTOR:
0245MC
WEIGHT: 4.1 gram.

'N
£=?\
~

+6.30
2.S
"t"10

POWER SUPPLY REQUIREIiENTS
±V~

4.32

0.53
0.89
1.52
2,$4 BASIC
0.76
1.78

.800 BASIC

G

mA

kO
kO

7.'
2.S

-Ol-

MAX

0.38

O

_-

....,

300

c

30.86

Pin 1

{DACaoo only)
Settling Time to ±O.O1'" of FSA
For FSR Change
100 to 100n load
1kO load

ANALOG OUTPUT, I mode'
(DAC800 only)
Ranges: Bipotar
Unipolar
Output Impedance: BipOlar
Unipolar
Compliance

MIN
30.10
2.87

o .

CONVERSION "'ED. I model

Output Current
Output Impedance (DC)
Short Circuit to Common. Duration

•

·C

....,
....,

2.'

10

PJ)mot fSRr'C
LSB
LSB

pack.ge.

MILLIMETERS

1.215
.170
.015
.021
.060
.005
.100SASIC
.030
.070
.012
.008
.120
.240

ppmot FSRrC

"12

Dlfferent,allinea,ity DoC to HOoe
Linftanty ErrorO°C to +70oC
Monotonicity Temp. Range. min

ANALOG OUTPUT. V models
Ranges {±Vcc =15V)el

INCHES
MIN
MAX

±25

±3
.,S
+1, -7/8
±1I2
+70

.

reference only. Numbefa
may not be martted on

J~D~G~ I nt=;;,

±10

.30

NOTE:
Leads in true pOSition
within 0.010'" IO.25mml
R at MMC ., _ling plane ..

Pin numbers IIhown for

"

L--A~

H

Unipolar
Bipolar
Gain
Un, polar Offset
Bipolar OllS8t

CONVERSION SPIED', V models
Settling Time to ±D.D1" of FSR
For FSR Change
20V ,ange. 2kn load
10V range. 2kO load
For 1LSB Change, Major Carry,
2kO loa~
Slew Rate. 2kO load

.'

D

DRIPT'''(O°C to +1O°C)
Bipolar Drift (±Iull scale drift

13

0

D"CIOO,D"~

MODEL

I'L (V ,N

DACIOO

,.

...

.21"

.023
.04' .012
.100 BASIC
.030 .010
.008 .016
.1001 .13
.&00 IASIC
O·
16·
.018 .022

Mll.IM!

4 •• 1

o.

'fH~

I."

0 ••8

1.01 1.57
2.a48ASh:

O.7:t--w.
0.20

0.3'

2.'4

3,36

. CASE: Plastic
MATING CONNECTOR:
0245MC
WEIGHT: 3.7 g08m.
(0.13 OZ. I

11:.~.pt;~

o.• ~~

NOTES:
(1) Aeter to Logic Input COmpatibility section.
(2) Adjustable to zero with external trim potentiometer.
(3) FSR means "Full Scale Aange" and is 20V for ±10V range, 10V for ±SV
range, etc.
(4) To maintain drift spec internal feedback resistors must be used for
current output models.
(5) Includes the effects of gain, offset and linearity drift. Gain and offset
ar'rors are adjusted to zero at +25° C.
(6) A minimum of ±13V supply is required for ±10V and 0 to 10V ranges.
All other ranges accept ±12V supplies,
(7) Power diSSipation is an additionall00mW, max, when Voo is operated

at+15V.
(8) Max operating temperature for DACSOOP-CBI-V is +70°C.

6-127

CONNECTION DIAGRAMS

Voltage Mod'elS'

Current Model

9 -Vee
11110MUl

-Vee

~OI '
OFFSET ADJ, ~ll
OFFSET A~J.
'
TRANSLATES
..-,"+-++-+-+.....++-~
THE LINE
I
DIGITAL INPUT

ALL BITS
LOGIC 0

FI G UR E 4. Relationship of 'Offset and Gain Adjustments
for a Unipolar Dj A Converter.
ILSB

L

ft:

,+FULL
L
'
SCALE,...; RANGE Of
"'~/T GAINADJ.

FULLSCALE~1}\_
GAIN ADJ.
RANGE ~./
ROTATES

ALL BITS'
LOGIC I '''-,..'......1t+J......+!I.~""~-+..._.....,......
BIPOLAR V ,%
RANGE OF
OFFSET.:J>:lOFFSET ADJ'l
' I
OFFSET ADJ.
,/...
TRANSLATES
'.
THE LINE
'T '
DIGITALINPUT

THE LINE
ALL BITS
LOGIC 0
OFFSET

FIGURE 5. Relationship of'Offset and Gain Adjustments
for a Bipolar Dj A Converter.

6-130

components. Connections for various output voltage
ranges are shown in Table III. Settling time for a full scale
range change is specified as 3/Lsec for the 20-volt range
and 2.5/Lsec for the IO-volt range.

For bipolar (COB. CTC) configurations. apply the
digital input code that should produce the maximum
negative output voltage and adjust the Offset potentiometer for minus full scale voltage. Example: Iftlie Full
Scale Range is connected for 20V. the maximum negative
output voltage is -lOY. See Table II for corresponding
codes and the Connection Diagrams for offset adjustment
connections. Offset should be adjusted prior to gain.

CURRENT OUTPUT MODEL
The resistive scaling network and eq uivalent output
circuit of the current model differ from the voltage model
and are shown in Figures" and 8.

Gain Adjustment: For either unipolar or bipolar configurations. apply tf:\e digital input that should give the
maximum positive voltage output. Adjust the Gain
potentiometer for this positive full scale voltage. See
Table II for positive full scale voltages and the Connection Diagrams for gain adjustment connections.

~__~~kn______fri\

REF.I.PUT~Y~
2.55k1!

18 .
1.
~
4.261Cll
® Rutstor
':25%
@

TABLE II. Digital Input/ Analog Output.

IDlnneR

Analog Output
Current

o to -2mA

lSB

o to +IDV

tlDV

000000000000
01111'11111,'
100000000000
111111111111
One LSB

+9.9976V
+5.0000V
-t-4.9976V
O.OODOV

-rS.9951V

2.44mV

4.6BmV

I

I

FIGURE 7. Internal Scaling Resistors.

Voltage'

Digital Input

MSB

1.71kl!

O.COODV
-O.OO49V
10.0000V

I nternal scaling resistors (Figure 7) are provided to scale
an external op amp or to configure load resistors for a
voltage output. These connections are described in the
following sections.

±1.~A

·1.9995mA
-1.0000mA
··-O.9995mA

O.OOOOmA
o.4SBpA

-O.9995mA

O.OOOOmA
+O.OOOSmA
+l.0000mA
O.48BpA

If the internal resistors are not used for voltage scaling.
external Rl. (or Rd resistors should have a TCR of

*To obtaLn values for other binary ranges:
o to +5V range: divid,e 0 to +10V range values by 2.
±5V range: divide ±10V range values by 2.
±2.5V range: divide ±10V range values by 4.

5.36kn
REF. INPUT I'j'i\r----..-,'H-r._______@17BIPOlAR
\:;J
OFFSET

..

~

COMMON

OUTPUT

RESISTOR TOLERANCES !25'10

oTO
2.35mA
±25'10
FIGURE 8. Current Output Model Equivalent
Output Circuit.
±25ppm/"C or less to minimize drift. This will typically
add ±50ppmjOC plus the TCR of Rl. (or RF) to the total
drift.
Driving a Resistive Load Unipolar
A load resistance. Rl. = RI.I + Rl. s• connected as shown in
Figure 9 will generate a voltage range. VOt:T. determined
by:
RI. x 7.2kO)
VO\'! = -2.35mA ( RI. + 7.2kfl

FIGURE 6. Output Amplifier Voltage Range Scaling
Circuit.
TABI.E III. Output Voltage Range ConnectionsVoltage Model DAC800.
Output
R'lnge

Digital
Input Codes

Connect
Pin 15 to

Connect
Pin 17 to

COB ur.('T('

19
1M
18
18
18

20
20

Con'neet Connect
Pin ~9 tu' Pin 16 to
i)---~+

±IO
±5
±2.5'v
0'0 +IOV
Ot()+5V

C08or CTC
C08or crc
CSB
CSB

=
ICC

VOLTAGE OUTPUT MODELS
Output Range Connections
I nternal scaling resistors provided in the DAC800 may be
connected to produce bipolar output voltage ranges of
± IOV. ±5V or ±2.5V or unipolar output voltage ranges of
o to +5V or 0 to + IOV. See Figure 6.

FROM WEIGHTED
RESISTOR
NETWORK

Iu

15

20

20

21
21

NC

24
24
24
'24

20

24

NC

Gain and offset drift are minimized because of the
thermal iracking of the scaling resistors with other device

FIGURE 9. Current Output Model Equivalent Circuit
. Connected for Unipolar Voltage. Output
with Resistive Load.

6-131

To achieve' specified drift. connect the internal scaling
r~sistor (RI.I) as ~hown to an external metal film trim
resistor ( RLS ) to'provide full scale output voltage range of
oto -2V. If the internal resistors are not used. externaJ'RL
(or Rd resistors should have a TCR of ±25ppll'l/"C or
less to minimize drift. This will typically add ±50ppm/"C
plus the TCR of RL (or Rd to the tbtal drift. Tolerances
on internal equivalent resistors are wide. R,.s will have to
be selected for each unit.

VelD.,.': IOI"l',x Rf
where IOU-I" is the DAC800 output current and RF istl!e
feedback resist()r. Using the internal feedback resist,?rs Of
the current output model DAC800 provides output
voltage ranges the same as the voltage model DAC800.
To obtain the 'desired put PUt voltage range when
connecting an external' op amp, refer to Table IV.

TABLE IV. Voltage Range of Current Output DAC800.

Driving a Resistive Load Bipolar

. The equiyalent output circuit for a bipolar out.put voltage
range is s,hown in Figure 10. RL : Ru + Rl.s. Vewl" is
determined by:
'
V ,.: + I 175mA( RI. x 3.07k!l)
0\ ,
_.
RI. + 3.07kO
To achieve specified drift. connect 1.71kO and 2.55kO
internal scaling resistors in parallel (Ru) and add an
external metal film resistor (Rl.s) in series to obtain a full

OUlpul
Range

Digilal
Inpul Codes

±10V
±5V
±2.5V
010 +10V
O10+5V

COB or CTC
COB or' eTC
COBorCTC
CBB
CSB'

®necI Connect Connect Connect
A 10
Pin 1710 Pin 1910 Pin 1610
19
18
18
18
18'

15
15
15
21
21

0NC
15
NC
15'

24
24
24,
24
24

Output Larger Than 20V Range

For output voltage ranges larger,than ±IOV. a high
voltage op amp may be employed with an ,external
feedback resistor. Use 11'1," values of±I.175mA ±25('i for
bipolar voltage ranges and -2.35mA ±25fii for unipolar
voltage ranges. See Figure 12. Use protection diodes
when a high voltage op amp is used.

i}-_ _ _-Q+

VOUT

FIGURE 10. Current Output Model·Connected for
Bipolar Output Voltage with Resistive
Load.
'FOR OUTPUT VOlTAGE SWINGS UP TO l40V PlI.

scale output range of ± I V. The tolerances on the
internal equivalent resistors are wide. RLS will h!lve to be
selected for each unit.
'
Driving An External Op Amp

The ,current output model DAC800 will drive the
summing junction of an op amp used as a current to
voltage converter to produce an output voltage. See'
Figure II..

FIGURE 12. External Op Amp - Using External
Feedback ..Resistors.
The feedback resistor. Rf. should have a temperature
coefficient as low as possible. Using an external feedback
resistor. overall 'drift of the cin;uit increases due to the
lack of temperature tracking betweenRF and the internal
, scaling resistor netwock. This will typically add 50
. ppin/"C'+ RF drift to total drift.
LOGIC INPUT COMPATIBILITY

i
OlD

2.36mA

VOUT

DAC800 digital inputs are TTL. LSTTL and 54 74HC
., CMOS compatible over the operating range of V"". +5
to +15V. The input switching threshold remains at the
TTL threshold over supply range of VDD• +5V to +15V.
Logic "0" input current over temperature is low enough
to permit driving DACSOO directly from outputs 'of'
4000B and 54!74C CMOS devices over the logic power
supply range Of+5V to +15V.

FIGURE II. External Op Amp - Using,lnternal
Feedback Resistors.
.

6-132

BURR-BROWN@

DAC811

I E5IE5I I

Microprocessor-Compatible
12-BIT D/A CONVERTER
FEATURES

DESCRIPTION

• SINGLE INTEGRATED CIRCUIT CHIP
• MICROCOMPUTER INTERFACE: DOUBLE-BUFFERED
LATCH
• VOLTAGE OUTPUT: ±10V, ±5V, +10V
• MONOTONICITY GUARANTEED OVER TEMPERATURE
• ±IIZLSB MAXIMUM NONLINEARITY OVER
TEMPERATURE
• GUARANTEED SPECIFICATIONS AT ±12V AND ±15V
SUPPLIES
• TTL/5VCMOS-COMPATIBLE LOGIC INPUTS

The OAC811 is a complete single-chip integrated
circuit microcomputer-compatible 12-bit digital-toanalog converter, The chip includes a precision
voltage reference, microcomputer interface logic,
double-buffered latch, and a l2-bit 0/ A converter
with a voltage output amplifier, Fast current switches
and a laser-trimmed thin-film resistor network
provide a highly accurate and fast D/A converter,
Microcomputer interfacing is facilitated by a doublebuffered latch, The input latch is divided intQ three
4-bit nybbles to permit interfacing to 4-. 8-, 12- or
16-bit buses and to handle right- or left-justified
data. The 12-bit data in the input latches is transferred to the D/A latch to hold the output value.
Input gating logic is designed so that loading the last
nybble or byte of data can be accomplished simultaneously with the transfer of data (previously stored in
adjacent latches) from adjacent input latches to the
D/A latch. This feature avoids spurious analog
output values while using an interface technique that
saves computer instructions.
The DAC811 is laser trimmed at the wafer level and
is specified to ±1/4LSB maximum linearity error (B
and S grades) at 25°C and ±1/2LSB maximum over
the temperature range. All grades are guarantc;ed
monotonic over the specification temperature range.
The OAC811 is available in four performance grades.
The DAC811AH and BH are specified over the
-25°C to +8So C; the DAC811RH and SH are
specified over -55°C to +12S o C. All models are
packaged in a 28-pin.O.6-inch wide dual-in-line
hermetically-sealed ceramic side-braze package.

4-18B',

4-1I8',

Inllrllllional Airport IndUllrlal Park· P.O. Bex 11400· Tucaon, Arizona 85734 • Tel. 1602) 746-1111 • Twx: 910-962·1111 • Clbla: BBRCORP . Talax: 66-6481

6-133

SPECIFICATIONS
ELECTRICAL
TA = +25°C ±Vcc = 12Vor 15V unless otherwise noted.

I

MODEL

1

DAC811AH

1

' DAC811BH

1MIN 1 TYP 1 MAX I

PARAMETER

'iotIN,

'.1 tvp·1

MAX

I

DAC811RH

,DAc;at!.~ .

,";~J

1MIN 1 TYP I MAx I· . . .lIt 1 tyP '1 IIAle 'I

UNITS

INI'UT
DIGITAL INPUT
Resolution .

,LeiBal.·

Cottes!lI
Digital Inputs Over Temperature Range121

V,"
Y"
',", VI
'lL. VI

12

+2.0
0.0

= +2.7V
= +O.4V

Digital Interface Timing OverTElmf)6rature Range
, twp, WI!f pulse width
tAW', Nx and ~ valid to end of ~
tow. data valid to ehd of WR
.
tOHI data valid hold time

I ..

Bits

.,"..
,

+15
+0.8
±10
±20

VDC
VDC
pA
pA

'':

.

50
50
80
0

nsec
nsec
nsec
nsec

+10

TRANSFER CHARACTERISTICS

'J •

.

.•

.'.

ACCURACY

Linj!8rityError
Differentlal"llnearlty Error:"

±1/4
±112
±O.l
±0.06

Gain Error'"
,Offset Errorl3~
Monotonlcity
Power Supply Sensitivity. +Vcc

±112
±3/4
±O,2
±O.15

H/8
±1/4

±1I4
±112

±1!4
";/2

±112
±3/4

±1/8
±1/4"

±1I4
±1/2(

LSB
.. ··LSB
'110

%ofFSR''''

Guaranteed ,

lib of FSRflMtVoc

±o.oOl
±O.OO3
±O.OO2
±O.OO8
±O.OOO5 ±O.0015

-Ycc
V••

"ofFSR~Vcc

iI)b of

FSRI%VDD

DRIFT (Ovef specification temperature range)

Gain

±10'
±5
±5

'Unipolar Offset
Bipolar Zero
Linearity Error Over Temperature Range
Monotonicity Over Temperature Range

±1/2

±3D
±10
±10
'±3/4

±10
±5
±5

±114

±20
±7
±7
;""2

±15
±5
±5
;1;112

±3D
±10
±1O
±3/4

Gua~anteed

±15
±5
±5
±1/4

;

±20
±7
±7
±1/2

ppm/DC
ppm of FSRrC
ppm of FSRI"C
LSB

CO.NVERSION SPEED

I .

SEnLlNG.TIMEIeI (to.within ±O.O1% of FSR of
final value; 2kn load)
Fo~ Full Scale Range Change, 20V Range
10V Range
For 1LSB Change at Major Carryf71
Slew Rate'"

_0

""""

1

""""

Vlpsec

12

OUTPUT
ANALOG OUTPUT
Voltage Range (±Vcc

= 15V)~, Unipolar

Bipolar
Output Current
Output Impedance (at DC)
Short Circuit to COmmon Duration
REFERENCE VOLTAGE
Voitage
Source Current Available for External Loads
Temperature Coefficient
Sh9rt Circuit to Common Duration

V

010+10
±5.±10

V
"lA

.

±5
0.2

"

Indefinite

+6.0
+2.0

I.

+6.6
+6-3.J
±10

±3D

±10

±20

±10

±30

±10

±20

V
mA
; ppm/DC

Indefinite

PO,WER SUPPLY REQUIREMENTS

Voltage. +Vcc
-y""

+11.4
-11.4

V..

+4.5

+15
-15
+5
+16
-23
+8

Current (n~ load~. +Vcc
'-Vcb

V••
Potential at DeOM with Respect
Power Dissipation

t~ ACOMItI)

VDC
VDC
VDC
mA
mA
mA
V
mW

+16.5

-16.5
+5.5
+25

-35
+15
±O.5

625

800

TEMPERATURE RANGE

.Speciflcatlon
Storage

+85
+150

-25
-65

-55

+125

·C·
·C

PACKAGE

Type

2&-pin side braze
wide dual~in~line

O.6~inch

Ma,eria'
Seal
Weight

ICe"'ml~

Hard solder (himetiC)

1

Grams

6

·Same as specification to immediate left.

6-134

.

.

NOTES; (1) USB = Unipolar Straight Binary; BOB = Bipolar Offset Binary. (2) Refer to Logic Input Compatibility section. (3) Adjustable to zero with external
. trim potentiometer. (4) Error at Input code 000,. for both unipolar and bipolar ranges.' (5) FSA means Full Scale Range and is 20V for the ±10V range. (6) Maximum represents the 30' limit. Not 100% tested for this parameter. (7) At the major carry. 7FF,. to soo,. and soo,. to 7FF,e. CS) Minimum supply voltage required for
±10V output swing is ±13.5V. Output swing for ±11.4V supplies is at least -8V 10 +8V. (9) The maximum voltage at which ACOM and DeOM may be separated
without affecting accuracy specifications.

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

+Vcc ................................ O to +18V
-VcctoACOM ......... : ............ Oto-18V
VDD to DCOM ........................ 0 to +7V
VDO to ACOM ............................ ±7V
ACOM to DCOM ......................... ±7V
Digital Inputs (pins 2-14, 16-19)
to DCOM ..................... -O.4V to +18V
External Voltage Applied
to lOY Range Resistor ................... ±12V
REF OUT ............ Indefinite short to ACOM
External Voltage Applied
to DAC Output. . . . . . . . . . . . . . . . .. -5V to +5V
Power Dissipation. . . . . . . . . . . . . . . . . . . .. lOOOm W
Operating Temperature:
AH, BH .................... -25°C to +85°C
RH, SH .................... -55°C to +125°C
Storage Temperature ............ -65°C to +150°C

DB" -III.:

Write Cycle #1

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability:

ORDERING INFORMATION
Linearity Error,
rna. (+25'C)
±1I2LSB
-25' C to +S5' C
-25' C to +S5' C
±'/4LSB
±1I2LSB
-55'C to +'25'C
-55' C to +,25' C
±1I4LSB
Temperature

Range

Model

Package

DACS"AH
DACS"BH
DACS"RH
DACS"SH

Hermetic Ceramic
Hermetic Ceramic
Hermetic Ceramic
Hermetic Ceramic

MECHANICAL

[:0:]
I

A

j

NOTE
Leads In true POSition Within 010·
(25mm)R@MMC at seating plane

MiN

M...X

35.20

35.92

D

.108
.015

.166
.021

0.38

F

.035

.060

0.89

G
H
J
K

.038
.008

C
numbers shown for reference only
Numbers may not be marked on package

L

M
N

6-135

MILLIMETERS

1.414

....

Lr~PIn

F.

INCHES
M...X

MIN
1.386

DIM

.1OQBASIC

4.22
0.53
1.52

2.74.

2.54 BASIC
1.63

.064

0.91

.012

0.20

0.30

.240
.120
,800 BASIC

3.05

8.10

.025

I

10'

15.24S"'SIC
10'

'.060

0.84

-

I

1.52

-

co

c:,:)

c

=

PIN NOMENC~TURE
PIN NAME

Line~rity Errar as used in ri /A cqnyerter, specifications
by Burr-Brown is the deviation of the analog output
(rom a straight line drawn between, the end ;p~ints
(inputs all "I's" and all ·'O'sj. The DAC811 linearity
error is specified at ±1/4LSB (max) at +2S o C for B and
S grades and ±1/2LSB (max) for the A and Rgrades.

, Losilc Supply, +5V

Voo

,

LINEARITY ERROR
,',

FUNCTION

WR

WRlfE, command signal to load latches. Logic
low load. latcl)as.

3

Li5AC

LOAD D/A CONVERTER, ana_ WR to load the
D/A latch. Logic ,Iow'enables.
,

4'

N;

NYBBLE A, enables WR to I;"d Input latch A (the
moat significant nybble. Logic low enables.

S

N;

NYBBLE B, enables WR to load Input,latch B.
Logic loW enables.

6

No

NYBBLE C, enables WR to load Input latch C (the
least significant nybble). Logic low enable•.

7

0"
0,.

DATA, Bit 12, MSB. positive true.

8
9

D.

DATA,BiHO

10

D.

DATA. Bit 9

11

07

DATA, BitS

12

D.

DATA, Bit 7

13

D.

DATA,BitS

14

D.

DATA, Bit 5

15

DCOM

DIGITAL COMMON, VDD supply return

DIFFERENTIAL L1NEARITYERR,OR

Differential Linearity Error (DLE) is the deviation from
a lLSB output change from one adjacent state to th"
next. A DLE specification of 1/2LSB means that the
output step size can range from 1/2LSB to 3/2LSB when '
the input changes from one state to the next. Monotonicity requires that DLE be less than lLSB '(jver the
temperature range of interest.
'

DATA,BIt11

MONOTONICITY
A D/ A converter is monotonic if the output either

increases or remains the same for increasing digital
inputs. All grades of DAC811 are monotonic over their
sl?ecification temperature range.

16

Do

DATA, Bit I, LSB

17

0,

DATA, Bit 2

18

0.

DATA, Bit 3

DRIFT

'9
20

D.

DATA,Blt4

+VCC

Analog Supply Input, +15V or +12V

Gain drift is a measure of tile change in the full scale
range output over the specification temperature range.
Drift is expressed in pans per million per degree centigrade (ppm/DC). Gain drift is established by testing the
full scale range value (e.g., +FS minus -'-FS) at high
temperature, +25 DC, and low temperature; calculating
the error with respect to the +25°C vahie and dividing
by the temperature change.
Unipolar offset drift is a measure of the change in output
with all O's on the input over the specification temperature range. Offset is measured at high temperature,
+25°C, and low temperature. The maximum change in
offset referred to the +25°Cvalue divided by the temperature change is the offset drift. It is c:xpressed in parts per
million of full scale range per degree centigrllde (ppm ,of
FSR{" C).
Bipolar zero drift is measured at a digital input of 80016,
the code that gives zero volts output for bipolar operation.'

21

-V""

Analog Supply Input, -15V or -12V

22

GAINADJ

To externally adjust gain

23

ACO~

ANALOG COMMON, ±Vcc supply return

24

V...

D/A converter voltage oulput

25

10V RA1'IGE

Connect to pin 24 for 10V' Range ,

26

SJ

SUMMING JUNCTION of output limpllfler

27

BPO

BIPOLAR OFFSET. Connect to pin 26 for Bipolar
Operatton

26

REF OUT

6.3V rafarance output

DISCUSSION OF
SPECIFICATIONS
INPUT CODES
The DAC811 accepts positive true binary input codes.
DAC811 may be connected by the user for anyone of the
following codes: USB (unipolar straight binary), BOB
(bipolar ,offset binary) or, using an external inverter on
the MSB'line, BTe (binary two's complement). See
Table I.
'
TABLE.!. Digital Input Codes.
DIGITAL INPU

MSB

ANALOG OUTPUT
USB
Unipolar
Straight
Binary

LSB

BOB
Bipolar
Offaet
Binary

BTC'
Binary

T",Il'.
Complement

+
+
1111'1111111

+Full Scale

+Full Scale

'00000000000

+112 Full Scale

Zero

-Full Scale

0'11'111111'

112 Full Scale -, LSB

-, LSB

+Full Scale

-Full Seale

Zero

OOOOOOOOOOOO Zero

SETTLING TIME

Settling Time is the total time (including slew time) for
the output to settle within an error band around its fm&J.
value after, a change in input. Three settling times are
, specified to ±0.01% of Full Scale Range (FSR): two for
maximum full scale range changes of 20V and lOY, and
one for a lL~B change. The lLSlJ change is measured at
the major carry (7FF16 to 80016 and 80016 to 7FFI6), the
, input transition at which worst-case settling time occurs.
REFERENCE SUPPLY

, LSB

DAC811 contains an on-chip 6.3V reference. This voltage
(pin 28) has a tolerance o( ±0.3V. The reference output
may be used to drive external loads, sourcing at least
2.0mA. This current should be constant for best performance of the D/A converter.
.

'Invart the MSB of the BOB code with external invarter to obtain BTC
code.

6-136

POWER SUPPLY SENSITIVITY
Power Supply Sensitivity is a measure of the effect of a
power supply change on the D 1A con~erter output. It is
defined as a percent of fSR output change per percent
of change in either the positive, negative, or logic supply
voltages about the nominal voltages. Fig\lre I shows
typical power supply rejection versus power supply
ripple frequency.

the D/A register. This double-buffered organization
prevents the generation of spurious analog output values.
Each register is independently addressable.
These input latches are controlled by N;:, Ni, Nc and
WR. NA, NB, and Nc are internally NORed with WR. so
that the input latches transmit data when both N;; (or
Ni, Nc) and WR. are at logic "0". When either N;; (orlira',
Nc) or WR go to logic "1", the input data is latched into
the i1iput registers and held until both NA (or NB, Nc)
and WR go to logic "0".

1.0

The DI A latch is controlled by LDAC and Wit LDAC
and WR are internally NORed so that the latches
transmit data to the DI A switches when both LDAC
and WR are at logic "0". When either ~ or WR are
at logic "I", the data is latched in the D 1A latch and held
until LDAC and WR go' to logic "0':

./~~

~t

..L

~g 0.1

l~
.Q.

!.ril

~I
00.0.G1
'Co

U

o.l!
0

0.001

~~

0.000\0

-

100

..,..

L

~

~
lK

10K

All latches are level-triggered. Data present when the
control signals are logic "0" will enter the latch. Whe,ll
anyone of the control signals .returns to logic "1", the
data is latched. A truth table for all latches is given in
Table II.

12

V

fx\;C

lOOK

TABLE II. DACSIl Interface Logic Truth Table.

1M

Frequency (Hz)

FIGURE 1. Power Supply Rejection versus Power
Supply Ripple Frequency.

WR

N.

N.

1

'x

X

x

X

No Operation

0

0

1

1

1

Enables Input Latch 4MSB's

0

1

0

1

1

Enables Input Latch 4 Middle Bits

0

1

1

0

1

Enables Input Latch 4 LSB'.

0

1

1

1

0

Loads D/A Latch From Input Latches

·0

0

0

0

0

All Latches Transparent

Don~

care.

" X" -

OPERATION
DACSll is a complete single IC chip 12-bit DI A converter. The chip contains a 12-bit D/A converter, voltage
reference,output amplifier, and microcomputer-compatible input logic as shown in Fig\lre 2. .

OPERATION

NcLDAC

GAIN AND OFFSET ADJUSTMENTS
Figures 3 and 4 illustrate the relationship of Offset and
Gain adjustments to unipolar and bipolar D 1A converter
output.
OFFSET ADJUSTMENT
For unipolar (USB) config\lrations, apply the digital
input code that should produce zero voltage output and
adjust the Offset potentiometer for zero output. For
bipolar (BOB, BTC) config\lrations, apply the digital
input code that should produce the maximum negative
output voltage and adjust the Offset potentiometer for
minus full scale voltage. Ex.ample: If the Full Scale
Range is connected for 20V, the maximum negative
output voltage is -lOY. See Table III for corresponding
codes.

G.AIN ADJUSTMENT

fIGURE 2.DACSll Bloc\c Diagram.

For either unipolar or bipolar configurations, apply the
digital input that should give the maximum positive
voltage output. Adjust the Gain potentiometer for this
positive full scale voltage. See Table III fQrpositive full
.
scale voltages.

INTERFACE LOGIC
Input latches A, B, and C hold data temporarily while a
complete 12-bit word is assembled before loading into

±12V OPERATION
The DACSIl is fully specified for operation on ±12V
power supplies. However, in order for the output to

6-137

-

;;
u

c

CI

. ,~;L

'"
~/:":;-T

f"~

~

',rf,"-/

&AI

ALLBln ~"
L08le II ...;Jr:~\
7' IAIII ADJ.
C
OFFSET ADJ'lj
Jf
ROTATES
OFFSET ADJ.
'
THE LlIlE
TRANSLATES
..THE LlIlE
I
1I161TAL IIiPUT

.'!9 ,

.1I RAIIIE OF

These capacitors (l"Ptanthlum recommended) should
be loCated close to the DAC811.
.

.. ~"EIIF
••iil ADJ;

~i
.... :1
iI!

/

I.'

. Ali ilTS
.LOGIC 1

FIGURE 3. Relationship.of Offset and Gain' Adjustments
for a Unipolar D / A Converter

. 'ij
T

!

ALL elTs
LOGIC 0 "

I

'.L

+fULL

~LE /;

IL.~
~"
FULL sCALE . '~t"-':'-IAIiAIIoI.
'RAUE .. :;:.
IITATU .
, ~ ..:
.
TIlE U.

-..

llPO!.AR V ,.t'
RAUE OF
OFFSET J,"
OFFSET ADJ.}
, I .
OFFSET ADJ.
/.
TRANSLATES
THE LlIlE
T
DI81TALIIIPUT

C

RAUEOF

'//T' GAlli ADJ.

.

The DAC811 features seplirate digital and analog power
supply returns to pernik optimum connections for low
noish and hi~ speett performance: the Anillog Common
(pin 23) and Digital Common (pin l~) should be conneeted together at one' point. Separate returns minimize
current flow in low level signal paths if properlyconnected~Logic retUrn currents are not added into the analog
signal return path. A ±O.5V difference between ACOM
and DCOM is pennitted for spec:ified operation. High
frequency noise on DCOM with respect to ACOM may
pe~mit noise to be coupled titrough to the analog output,
theiefore, some caution is required in applying these
.
common connections..
The Analog Common is the high quality return for the
D/ A converter and should be connected directly to the
analog reference point of the system. The load driven by
the output amplifier should be returned to the Analog
Common.
.

All BITS
L08IC I

OFFSET

FIGURE 4. Relationship of Offset and Gain Adjustments
for a Bipolar D/A Converter.
TABLE III. Digital Input/Analog Output, ±Vcc = ±15V,
ANALOG. OUTPUT YOLTAGE,
DIGITAL INPUT

010 +10V

±5Y

+9.9976Y
+5,QOOOY
+4,9976Y
O.OOOOV
2.44mV

+4.9976Y
O,OOOOY
-o,0024V
-5,QOOOV
2.44mV

12-BII Resolullon
LSB
MSB

I

I

I

111111111111
10ooooQ!lOOOO
011111111111
000000000000
lLSB

±10Y

+9,9951V
O,OQOOY
-o,0049V
-10.OOOOV
4,88mV

swing to ±IOV, ·the power supplies must be ±13.5V or
greater. When operating with ±12V supplies, the output
swing should be restricted to ±8V in order to meet
. specifications.
LOGIC INPUT COMPATIBILITY

The DAC811 digital inputs are TTL, LSTTL, and
54j7411C CMOS-compatible over the operating range of
VDD. The input switching threshold remains at the TTL
threshold over the supply range.
•
'
The logic input current over temperature is low enough to
permit d~ving theDAC811 directly from the.outputS of
4000B and 54/14C CMOS devices.

INSTALLATION
POWER SUPPLY CONNECTIONS
Decoupling: For optimum performance and noise tejection, power 'siipply decoupling capacitors should be
added as shown in the Connection Diagram, Figure 5.

6-138

FIGURE 5. Power Supply, Gain, and Offset
Potentiometer Connections.
EXTERNAL OFFSET AND GAIN ADJUSTMENT
Offset and Gain may be trimmed by installing external
Offset and Gain potentiometers. CoilDect these potentiometers as shown in Figure 5. TCR of the potentiometers.should be 100 ppm/oC odes's. The 1.0MO and
3;9MO resistors (20% carbon or better) should be located
close to the DAC81l taprevent noise pickUp. If it is not
convenient to use these high va11le resistprs, an equivalent
"T" network, as shownin'Plgure 6, may be substituted in
each case. The Gain Adjtist (pin 22) is a higit impedance
point and a O.OOI"F to O.OI"F .ceramic capacitor should
be connected from this pin to .Analog Common to
reduce noise pickUp in all applications, including those
not employing external,gain adjustment.

strobed into the D/A latch of all D/A's simultaneously
updating all analog outputs. All the interface schemes
shown below use a base address decoder. If blocks of
memory are unused, the" base address decoder can be
simplified or eliminated altogether. For instance if half
the memory space is unused, address line A,s of the
microcomputer can be used as the chip select control.

~'=~'IOOkO
I.oMO·

,IOOko
.

12kO.

_~18Ok0'""!'"18Oi0 .

~=
a.po

.

.

10110

FIGURE 6. Equivalent Resistances.
OUTPUT RANGE CONNECTIONS
Internal scaling resistors provided in the DACSII may be
connected to produce bipolar output voltage ranges of
±IOV and ±5V or unipolar output voltage range of 0 to
+iov. The 20V range (±IOV bipolar range) is internally
connected. Refer to Figure 7. Connections for the output
ranges are listed in Table IV.

4-BIT INTERFACE
An interface to a 4-bit microcomputer is shown in Figure
S. Each DACSI1 occupies four address locations.
A 74LS139 provides the two to four decoder and selects
these with the base address. Memory Write (WR) of the
microcomputer is connected directly to the WR pin of
the DACSII. A S205 decoder is an alternative device to
use instead of the 74LS139.

0801-------+-t1
FROM
VOLTAGE REFERENCE

5.38lt0

®

'V\I'

RoPO

BIPOLAR
OFFSET
SUMMING
JUNCTION

...
...'"
...•...
•
~

IOV RANGE

4.2IIk0

-

CO

081

OAC811

Q

!;;!

<
CI

D82

Q

FROM OIA
CONVERTER

c.:I

083

Wi
A,"

A,
RESISTOR TOLERANCES ±25%
A,

FIGURE 7. Output Amplifier "oltage Range Scaling
Circuit.

Ao

Table IV. Output Range Connections.
Output
Range

Digital
Input Codes

Connect
Pin 25 To

Connect
Pin 27 To

24

23

Oto+l0V

USB

±5V

BOB or BTC

24

26

±10V

BOBorBTC

NC

26

FIGURE S. Addressing and Control for 4-Bit
Microcomputer Interface.

I, 1·.1, 1,10,,10101091 OBI 1011 OBI 051 041 031021011001
• R'ghl-JIISflIIed

APPLICATIONS
MICROCOMPUTER BUS INTERFACING
The DACSII interface logic allows easy interface microcomputer bus structures. The control signal WR is
derived from external device select logic and the 1/0
Write o~ Memory Write (depending upon the system
design) signals from the microcomputer.
The latch enable lines NA, NB, Nc and LDAC determine
which of the latches are enabled, It is permissible to
enable two or more latches simultaneously as shown in
some of the following examples.
The double-buffered latch permits data to be loaded
into the input latches of several DACSlI's and later

FIGURE 9. 12-Bit Data Formats for ii-Bit Systems.
8-BIT INTERFACE
The control ,logic of DACSII permits interfacing to
right- or left.:justified data formats illustrated in Figure
9. When fl12~bit D I A converter is loaded from an S-bit
bus, two bytes of data are required. Figures 10 and II
show an addressing scheme for right-justified and leftjustified data respectively. The base address is decoded
froIn the high-order address bits. Ao and A, address the
approptiate latches. Note that adjaCent addresses are

6-139

~sed;' For th~ righ~"ju~tified case XI()1610~s the 8 LSD;s
and XOI/61Qads'the 4MSB's and simultaneously transfers
ipputlatch data to the Dl A latch. Addresses XOO16 and
XlII6 are not used.
Left-justified data is handled in a similar manl).er, shown
in Figure 11. The DACHli still occupies two adjacent
locations in the microcomputer's memory map. -

INTERFACING MULTIPLEDAC811's
.IN 8-BITSYSTEMS ,
Many applications require that th~ outputs of several
.0 f A converters be updated simultaneously such as
'automatic test systems. The interface shown in Figure 12
'uses a 74LSI38 decoder to decode a set of eight adjacent
'addresses to load the input latches of four DACBll's.
The example shows a right"justified data format.
A ninth address using A3. causes all DAC811's to be
updated simultaneously. If a particular DAC81I is
always loaded last, for instance, D f A #4, A3 is' not
needed, thus saving 8, address spaces for other uses.
Incorporate A3 into the Base Address Decoder, remove
the inverter, connect the common LDAC line to Nc of
Df A #4, and connect Gl ofthe 74LSI38 to+SV.

FIGURE 10. Right-Justified Data Bus Interface.

OPERATION

_DA~81,1

FIGURE 12. Interfacing Multipl~ DAC 8il's to
an 8-Bit Bus.
12- AND 16-BIT MICROCOMPUTER INTERFACE
For this application the input I~tch enable lines, NA, Ns,
Nc are tied low, causing the latches to be iranspatent.
The Df A latch, and therefore DAC 8Il, is selected by the
address decoder and strobed by WR.
,
FIGURE)I. Left-Justified Data Bus Interface.
,

6-140

DAC812

BURR-BROWN®

IElElI

Ultra-High Speed
DIGITAL-TO-ANALOG CONVERTER
FEATURES

DESCRIPTION

• 12-BIT RESOLUTION AND ACCURACY

The DACSl2 is an ultra-fast-settling 12-bit currentoutput D / A converter with TTL-compatible inputs
packaged in a 24-pin dual-wide dual-in-Iine hermetic
metal package.
The current output settles to ±O.OI2% of full scale
range in 55nsec, typical (65nsec, max., C grade;
80nsec, max., B grade).
The DACSl2 utilizes a monolithic 12-bit switch chip
with stable, compatible thin-film resistors to achieve
fast settiing time and excellent stability over temperature and time. An internal applications resistor for
use with an external op amp is included to convert
the output current into a voltage for OV to +IOV or
-5V to +5V ranges.
An output voltage compliance range of +4V to -4V
allows the generation of an output voltage without
using an external output amplifier.
The DACSl2 comes in two drift grades. The linearity error of the C grade is guaranteed to be within
±1/2LSB over the temperature range of -25°C to
+S5°C. Gain drift of the C grade is ±20ppm/oC
(max) and bipolar offset drift is ±IOppm of FSR/oC
(max). The B grade has a linearity error of ±ILSB
over the temperature range and a maximum gain
drift and bipolar offset drift of ±40ppm/oC and
±15ppm/oC, respectively.

• 55ns8c CURRENT OUTPUT SETTLING TIME
• TTL-COMPATIBLE INPUTS
• MONOTONIC OVER ENTIRE TEMPERATURE RANGE
• LINEARITY ERROR LESS THAN ±1I2LSB OVER
TEMPERATURE RANGE IC GRADE)
• HERMETIC METAL PACKAGE
+Vee
-Vee
BIPOLAR OFFSET

D/A
SWITCHES

AIID
RESISTOR
LADDER
NETWORK

lout

V••
ANAL06 COMMON
ANALOS COMMON
ANAL06 COMMON

_-------

.....

ANALOS COMMON
DISITAL COMMON

Intematlonat Airport Industrial Park· P.O. Box 114DO· Tucson. Arizona 85734· Tel. (6021746·1111· Twx: 910·952·1111 . Cable: BBRCORp· Telex: 66·6491

6:"141

N

;;
c,.,
C

CI

SPECIFICATIONS
ELECTRICAL
At T. = +25'C rated power suppll.. and after 5-mlnute warm-up unleee otIIMwI.. noted.
MODEL-

-

DACIIICM" :.
MI"

TYP

I

DACI1-

!lAX

MIN

UI'

MAX

I,J.NITS

··
···

Bita
V
V
pA
pA

±O.018
±O.018

'IIoofFSR'"
'IIoofFSR

INPUT
DIGITAL INPUT
Resolution; CSB, COB
Logic InpulS: VIM
VII.
IIH, VI = +2.7V
IlL, V, = +O.4V

,-

.

12
+5.25
'+0.8
+20
-800

. +2.0
0.0

··

TRANlI'lIt'ClWIACTIRIITlCII

,
ACCURACY
Linearity Error
Differential Linearity Error
Gain Erro....
0IfaaI Erro....: Unipolar
Bipolar
MonotonlcllY Temp. Range (min)

.:to.OO8
±D.03
.±D.02
±D.03
.,.25

CONVERSION IPiED
Settling Time to ±II2LSB Into 1500
For FSR Change
For lLSB ChangeDRIFT
Gain
0IfaaI: Unipolar

Bipolar
Linearity Error
Dlllerential Linearity Error

±O.Q12
±O.012
±D.I
±D.04
±D.I
+85

55
25

65

±IO
±D.25

±20

±O.5
±IO
±O.012 over Temp. Range (max)
±D.025 over Temp Range (max)

±O.OO8

..

·

··
··

··
·

'110
'110 of FSR
'110 of FSR

'C

n_
n_

80

±40
±1
±15
±O.025 over Temp. Range (max)
±D.04 over Temp. Range (max)

±20
±D.5

ppm"C

,

ppm of FSRrC
ppm 01 FSRrC
'110 of FSR
'110 of FSR

OUTPUT
ANALOG OUTPUT
Output Current: Unipolar
Bipolar
Output Voltage Ranges
with Extemal Op Amp: Unipolar
Bipolar
ouiput Impedance: Unipolar
Bipolar
Output Compliance

Oto-IQ
-5 to +5

mA
mA

Oto+l0
-5 to +5
170
150

··

+4

-4

V
V

n

n
V

POWER IUPPLIES
Power Supply Sensitivity: +Vcc
-Voc
V""
Power Supply Voltagea: +Vee
-Vee
VDD
Power Supply Current: +VCC
-Vee
Voo
Power Dioaipation

+14
-18
+4.5

+15
-15
+5
+30
-40
+25
1.2

±O.DD4
±O.OOI
±O.OOO2
+18
-14
+5.5
+40
-50
+40
1.8

··

·

PHYIICAL CHARACTERIITICI
TEMPERATURE RANGE
Specification
Storage
PACKAGE

-25
-55

+65
+150

··

24-pin Hermetic Metal
-O.6~Pin Row Spacing

SpecifIcatIon the some as lor DAC812CM.
NOTES: (1) FSR Is lull ocala range. (2) Adjustable to zero with axtemal poIentlOl1'8ler.

6-142

··

'IIoFSR/'IIoVcc
'IIoFSR/'IIoVcc
'IIoFSR/'IIoVoo
V
V
V
mol
mol
mol
W

··
·

·
··
··

'C
'C

·
.

PIN ASSIGNMENTS

MECHANICAL

Pin
1
2
3

iA=:j

.
__
J
~IIIIIIII~ ~

~
G....I

NOTE
Leads In true posItion within
.010" (25mm) R at MMC at
seating plane

I.-

ui"
C- -

0

•• 00000.0.00

I

2'

12

13

0.0000000000

Pin numbers shown for referenC8 only. Numbers may not
be marked on package.

4
5

6
7
S
9
10
11
12
13

I- --l
L

INCHES
MIN
MAX

DIM

MAX

1.365

1.385

J4.~7

35.18

•

.790

.810

20.01

C

.170

.250

4.32

20.57
6.35

0

.016

.021

0.41

0.53

G

.100 BA$IC

....eo..

"
K

>2'
15.

.150

.300

L

.600 BASIC

"

.08.

.110

Pin

Function

14

Digital Common
(VDO Common)
Analog Common
(±Vcc Common)
Analog Common
Analog Common
Analog Common
Voo (Logic Supply)
lOUT (Current Output)
R, (Application ReSistor)
BPO (Bipolar Offset)
-VO:'L"''
--1--:-

-- --

!\ \

"

0

8"
«

±1J2I.SB.
----

20

;30

40

50

60

2
1
0

-I l-

-1

-2

-

±o,OO5
10

±2LSB

-3
20
70

60

90

100

40

60

60

Settling Time. (nsec)

Settling Time (nsec)

FIGURE 2.DAC8l2 Typical Settling Time vs. Accuracy

6-144

FIGURE 4. TypicalPositive-to-Negative Full-Scale
Output Characteristic.

S. Bring the source of the digital driving signal as close
to the inputs of the DAC8l2 as possible. If the digital
inputs are not clean it wilJ be necessary to reshape
them using registers or line drivers. It is recommended
that the logic power line be bypassed near the digital
logic circuitry as a further measure to achieve clean
signals.
6. If possible, the DAC8l2 should be soldered directly
into the printed circuit board since connector lead
length will cause ringing in the output:

metric product of the reference. The feedback resistor
has 'very low power sensitivity so that linearity is maintained independent of digital code changes. Because this
resistor is constructed on a sapphire network, it is possible to have both superior tracking and low capacitance.
Figure 5 shows the DAC8l2 connected to an external op
amp in unipolar and bipolar modes. When the op amp is
a Burr-Brown model OPA600 it is possible to aChieve
settling times to ±O.l% accuracy in l50nsec. Many ofthe
output accuracy and linearity specifications are given
when connected to an external op amp.
For highest speed operation, the DAC8l2 should be used
without an external op amp. Figure 6 shows how to
connect the DAC8l2 for bipolar and unipolar operation.
Figure 7 illustrates how to connect the DAC8l2 to construct a fast AID converter.

OUTPUT CONFIGURATIONS
AND APPLICATIONS
INFORMATION
The DAC812 contains a 1.24kO resistor for generating
the bipolar offset current and a IkO resistor which is
primarily used as the feedback resistor when used with
an external op amp. This thin-film network is constructed on sapphire to provide excellent temperature
tracking capability inherent in thin-film networks. These
internal resistors along with other internal resistors
cause the DAC8l2 output, in any mode, to be a ratio-

Q------------,
22
I
!- CONNECT FOR BIPOLAR OPERATION
I

6~1.2~0
6.2V

r.:-

Oil
10mA

!

'"21

¥1i

DACBI2

GAIN ADJUST

.r

I
I

-'»!

I

1
I
I
I

""
20

500

t

VOUT

~ Ro

18
17

>ecovercd in other countries by one or
more international patents.

Iniemlliunal Alrporl Industrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. 1602) 746·1111 . Twx: 910-952·1111· Cable: 8BRCORp· Telex: 66-8491

6-147

SPECIFICATIONS
ELECTRICAL
At'25'C and ±Vcc = 12V or l~V unless otherwise noted.

.

"f"'(

t,

INPUT

DAC850-CBI

"

.

'

MODEL

MIN

TXi>

MIN

,

<•

MAX

".r

;OJ

'a.

DIGITAL INPUT

I

DAC851-CJ51
. MAX

TYP

UNITS
,,'

,

"

12

Resolution

Logic Levels {LSTTL Compatible)'"
Logic "I" (at +2OpA)
Logic "0" (at O.36mA)

I

+2
0

TRANSFER CHARACTERISTICS

+5.5
+0.8

+2
0

12

Bits

+5.5
+0.8

VDC
VDC

ACCURACY

Linearity Error
Differential Linearity Error

Gain Errorl2!
Offset Errorl21
Power Supply Sensitivity

.

+15V and +5V Sup~lies
-15VSupply
DRIFT'" (over spec. temp r.nge)·
Bipolar Drift
(± full scale drift for the bipolar connection)

Total Errorl15l : Unipolar
Bi~lar

Gain
Offset: Unipolar
Bipolar

Differential Linearity (over spec. temp range)
Linearity Error (over spec. temp. range)
Monotonicity Temp. Range," min

±1I4
±1/2
±O.I
±0.05

±1I2
+1,-3/4
±O.2
±0.15

±1I4
±1I2
±O.I
±0.05

±1I2
+1,'-314
±O.2
±0.15

LSB
LSB
%
%01 FSA'"

±O.OOOI
±0.003

±O.OOI
±0.006

±O.OOOI
±0.OO3

±o.oOI
±0.006

% 01 FSRI%Vcc
% Of FSRI%Vi:c

±5
±O.I
±0.06
±IO
±1
±5
±1I2

±17
±0.20
±0.12
±20
±3
±10
±1
±1I2
+85

±15'
±0.15
·±0.15
±10
±1
±5
±1I2

±30
±0.30
±0.30
±25
±3
±15
±1
±1/2
+125

ppm 01 FS.R/' C
% 01 FSA
%01 FSR
ppml'C
ppm 01 FSR/' C
ppm of FSR!' C
LSB
LSB
'C

3.
2.5
1.5
15

5
4

psec
psec
poec
V/psec

-25

-55

CONVERSION SPEED

V Model (settling time to ±0.01% of FSA)
For FSR Change: 20V Range, 2kO Load
10V Range; 2kO Load
For lLSB Change, Major Carry, 2kO Load
Slew Rate, 2kO Load
I Model (settling time to ±O.OI% of FSR)
For FSR Change: 100 to 1000 Load
lkO Load

5
4

3
2.5
1.5
·15

10

10

300
1

nsec
psec

300
1

OUTPUT

I

ANALOG DUTPUT

V Model
Ranges (±Vcc = 15V)'·'

I

I

±2.5, ±5, ±10, 0 to +5, 0 'to +10
±5
0.05

Output Current

Output Impedance (DC)
Short Circuit to Common, Duration

I

I

Indefinite

I

I

±2.5, ±5, ±10, 0 to +5, 0 to +10
±5
0.05

I

~ndefjnite

I

V
mA
0

I Model
Ranges'
Output Impedance: Bipolar
Unipolar
Compliance

±0.a8,
o to -1.76
2.5
5.8
-2.5

±1.175,
Oto -2.35
3.1
7.2

±1.47,
Oto -2.94
3.7
8.6
+2.5

+6.23
1.5

, +6.3
2.5
±IO
±15
+5
+8, -20

+6.37

±O.as,
Oto-I.76
2.5
5.8
-2.5

±1.175,
Oto -2.35
3.1
7.2

±1.47"
Oto -2.94
3.7
8.6
+2.5

+6.3.
2.5
±10
±15
+5
+8, -20

+6.37

mA
kO
kO
V

POWER SUPPLIES AND REFERENCE

Reference Voltage Output
Current (for external loads). Source
Tem'perature Coefficient of Drift
Power Supply Requirements: ±Vcc
m

VDD

±11.4
+4.5

P,?wer Supply Drain: ±Vcc ( no load)

VDD (logic supply)

+7

±20
±16.5
+16.5
+12, -25
+10

+6.23 .
1.5
±11.4
+4.5

+7

±25
±IS.5
+16.5
+12, -25
+10

V
mA
ppml'C
VDC
:VDC
mA
mA

+125
+150

'C
'C

PHYSICAL CHARACTERISTICS
TEMPERATURE RANGE
Specification

Storage
PACKAGE

-25
-65

+85
+150

-55
-65

24-pin hermetic DIP side-brazed ceramic

6-148

NOTES:
1. Adding external CMOS hex buffers CD 4049A/4050Awili provide CMOS
input compatibility. Refer to Logic Input Compatibility section.
2. Adjustable to zero with external trim potentiometer.
3. FSR means "Full Scale Range" and is 20V for ±10V range. 10V for ±5V
range, etc.
4. To maintain drift spec internal feedback resistors must be used for
current output models.

MECHANICAL
'3

.'

"

0
L--.
A

'INCHES

_F_-:~
N=t-{

MAX

MILLIMETERS

MIN

A

1.185

1.215

30.10

c

.os

.170

2.67

0

015

.021

F

.035

J

.030

H

K
L

M

N

.060

.100 SASIC
.008
120

.070
.012

-

0.89

MAX
30.86
0.53

1.52

2,54 BASIC

0.76

• IS

0.20

0.30

3.05

6.10

.0·

15.24 BASIC

.060

IMSBI BIT 1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT 7
B·IT 8
BIT9
BIT 10
BIT 11
,LSBI BIT 12
LOGIC SUPPLY, Voo
-Vee
lOUT
REF. INPUT
BIPOLAR OFFSET
SCALING NETWORK
SCALING NETWORK
SCALING NETWORK
COMMON
+Vee
GAIN ADJUST
6.3V REF. OUT

1J

~

I

I,

...

I

...

L

~

.1 M

NOTE:
Metal Cap connected
to -Vee internally.

4.32

.240

600 BASIC

.025

0.38

PIN
I MODELS NO. V MODELS

Pin numbers shown tor
reference only. Numbers
may not be marked on package.

Seating Plane

G

.

+m~

NOTE:
Leads in true position
within 0.010" 10.25mml
R at MMC at seating plane.

~f1
..JL-+-0JGL
MIN

7. Power dissipation is an additional100mW, max, when Voo is operated at

PIN ASSIGNMENTS

2.

OIM

. 5. Includes the effects of gain, offset and linearity drift. Gain and offset
errors are adjusted to zero at +25.oC.
'
6. A minimum of ±13V supplies is required for±10V and Oto +10V ranges.
All other ranges accept ±12V supplies.

CASE: Ceramic
MATING CONNECTOR:
0245MC
WEIGHT: 8.4 grams
10.30z.·

10°
0.64

6
8
9
10

"

12
13
14
15
16
17
18
19
20
21
22
23
24

BIT 11MSBI
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
BIT8
BIT9
BIT 10
BIT11
BIT 12 ILSBI
LOGIC SUPPLY, Voo
-Vee
VOUT
REF. INPUT
BIPOLAR OFFSET
10V RANGE
20V RANGE
SUMMING JUNCTION
COMMON
+Vee
GAIN ADJUST
6.3V REF. OUT

1.52

CONNECTION DIAGRAMS
Vonage Model

Current Model

NOTES:
I. OAC850/851 use I 10M n rellll1lr. Than modals can rep/Relhe OAC85 which USII
an 18Mn rellal8r a,",lhe OAC87 which una .33Mn rellll1lr.
2. Pin 1601 DAC850/851 II uled only 10 connect Iha bipolar onlll rlllll8r.
An external refarance vaKllla may not be Uled wllh DAC850/85I.

3.11 connacl8d 18 +VCC' which II permissible, power dissipation Incr888as 75mW typ.,
lOOmW max.
.
4. For flltut 881ll1ng lima conntct pins 19. 18. and 1518ge1her.
5. Values shown ara for ±15V supplill. For supplies below ±13.5V use 2.7Mn In plica
of 3.9Mn and 7.5Mn In placa of IOMn.

6-149

=
=

in

=

c.,)

C

SETTLING TIME
Settling time' is the total· time (including slew time)
required for the 'output to seitle within an error band
around its final value after a changein input (see Figure I).

DISCUSSION OF
SPECIFICATIONS
DIGITAL INPUT CODES
The DAC850 and DAC85 I accept complementary binary
digital input codes. They may be connected by the user
for anyone of three complementary codes; CSB, CTC, or
COB (see Table I).

3

~
.

TABLE I. Digital Input Codes.
DIGITAL INPUT

MSB

LSB

~
~
OOOOOOOOOOOO

011111111111
100000000000
111111111111

+FuliScale
+1/2 Full Scale
Midscale -1 LSB
Zero

COB
Campi.
) Offset
Binary
+Full Scale
Zero

g.;

I

0.3

M':del~

"i

\

I'

0.1

a::~

ANALOG .OUTPUT
CSB
Campi.
Siraighl
Binary

-g&
~~

\IV~~I'.'

:.=

~ ~ 0.03

CTC'
Campi.
Two's
.CampI.

-lLSB

-LSB
-Full Scale
+Full Scale

"Full Scale

Zero

~5k(,JJdUL
~.

\', ~ciJ~1I ~ ~ ,

~~B 0.01
l

u..

0.003
RL

= lOll

to 10011
0.001
0.1

'Invert the MSB of the COB code with an external inverter to obtain
CTCc0d8.

II

10kiIIF.J.db~cll
'i'Ti'"i-j'l

~ ..... ""

~ .......
~
10

100

Settling Time ("sec)

ACCURACY
Linearity of a D! A con,verter is the true measure of its
performance. The linearity error is specified over its
entire temperature range. This means that the analog
output will not vary by more than ±I/ 2LSB, maximum,
from an ideal straight line drawn between the end points
(inputs all "I "s and .all "O"s) over the specified temperature range.

Differential linearity error of a D/ A converter is the
deviation from an ideal I LSB voltage change from one
adjacent output state to the next. A differential linearity
error specification of ±1/2LSB means that the output
voltage step sizes can range from I! 2LSB to 3/2LSB
when the input changes from one adjacent input state to
the next.
M onotonicity over the specification temperature range is
guaranteed to insure that the analog output will increase
or remain the same for increasing input digital codes.
DRIFT

FIGURE I. Full Scale Range Settling Time vs Final
Value Error Band.
Voltage Output Models: Three settling times are specified
to ±0.01% of full scale range (FSR): two forl1Jaximum
full scale rangechangtls of 20V and 10V, and one for a
I LSB change. The I LSB change is measured at the major
carry (0111...11 to 1000 ... 00), the point at which the
worst-case settling time occurs.
Current Output Models: Two settling times are specified
to ±0.01% of FSR. Each is given for current models
connected with two different resistive loads: IOn to lOon
and looon. I nternal resistors are provided for connecting
a nominal load resistance of approximately 1000n for
output voltage ranges of ±I Vand 0 to -2V.
COMPLIANCE

Compliance voltage is the maximum voltage swing
allowed on the current output node in ordeno maintain
specified accuracy. The maximum <;ompliance. voltage of
all current output models is +2.5V to -2.5V.

Gain drift is a measure of the change in.the full scale range
output over temperature expressed in parts per million
per "C (ppm "C). Gain drift is established. by: I) testing
the endpoint differences at -25"C. +25"C. and +85"C for
the DAC850 and.at -55"C. +25"C. and +Q5"C for the
DAC85 I; 2) calculating the gain error with respect to the
+25"C value and; 3) dividing by the temperature c.hange.
This is expressed in ppm "C.
.

POWER SUPPLY SENSITIVITY .
Power supply sensitivity is a measu~e of the effect of a
power supply change on the D/ A converter output. It is
defined as a p'ercent of FS R per percent of change in
either the positive, negative. or logic supplies about the
nominal power supply voltages (see Figure 2).

Offset drift is a me·asure of the actual change hi output
with all "I "s on the input over the specification temperature range. The offset is measured at -25"('. +25"C. and
+85"C for the DAC850 and at-55"C. +25"C, and + 125"C
for the DAC851. The maximum change in offset is
referenced to the offset at +25"C and is d,ivided by the
temperature change. This drift is expressedi n parts per
million of full scale range per "c (ppm of FSR "c).

REFERENCE SUPPlY
All models are supplied with an internal 6.3V reference
. voltage supply. This voltage (pin 24) has a tolerance of
±I% and must be connected to the Referenc.e Input (pin
16) for specified operation. This reference may be used
externally also. The exte.rnal current drain is limited to
sourcing 2.5mA up to +85°C and ImA up to.;f-125°C not
including current required by the bipolar offs~ circuit.

6-150

An external buffer amplifier is recommended if this
reference will be used to drive other system components
because variations in a'load driven from the reference will
result in bipolar offset variations of the DJ A converter.
Gain and bipolar offset adjustments should be made
under constant load cO(lditions.

convenient to use these high value resistors, an equivalent "T" network, as shown in Figure 3, may be substituted in each case. Figures 4 and 5 illustrate the relationship of offset and main adjustments to unipolar and
bipolar D JA converter output.
270kn

~

u

~

180JUl

.S

~

"g

.

U

'0

FIGURE 3. Equivalent Resistances.

~

~

.

+FUll SCALE

Co

g

w

~

~

:;

~

...._ _...~.....~_J....._...J..._ _J....._.J

1

1M

10M

~
cw

FIGURE 2. Power Supply Rejection vs Power Supply
Ripple.

RANGE OF

A~J.

.~ ~

Offset and gain may be trimmed by installing external
offset and gain potentiometers. Connect these potentiometers as shown in the Connection Diagrams and adjust
as described below. TCR of the potentiometers should be
100ppmj"C orieSs. The3.9MOand IOMO resistors (20%
carbon or better) should be located close to the case to
prevent noise pickup. For operation with supplies of less
than ±13.5V, use 2.7MO and 7.5MO resistors in place of
the 3.9MO and IOMO resistors, respectively. If it is not

,~/~/

ROTATES
THE LINE

t,..k'

~

I

All81TS
lOGIC 0

DIGITAL INPUT

FIGURE 4. Relationship of Offset and Gain
Adjustments fora Unipolar D A Converter.
+FUll

.L,... SCALE ,/;

~

;

All BITS
lOGIC I "

T·

1,,f'

. , ".?, T'

BIPOLAR V
!'MSB 011
RANGE OF
OFFSET .J,l
All OTHERS
OFFSET AOJ'l
' I
OFF
OFFSET ADJ.
/~
;FUll SCALE
TRAIISLA TES
•
THE LINE
T
OIGITAlllIPUT

C

.L

RANGE OF
GAIN ADJ.
ILSB- I
~
FUll SCALE
,1l'\~ BAINADJ.
RANRE .. ' /
ROTATES
~;'
THE lift
T

S

POWER SUPPLY CONNECTIONS
For optimum performance and noise rejection. power
supply decoupling capacitors should bea.dded as shown
in the Connection Diagrams. These capacitors (I~F
tantalum or electrolytic recommended) should be located
close to the case. Electrolytic capacitors. if used. should
be paralleled with O.OI"F ceramic capacitors for best
high frequency performance. The metal cap on the top of
the package is connected internally to -Vee.

EXTERNAL OFFSET AND GAIN ADJUSTMENT

RANGE OF
GAIN ADJ.

~~
1h'
lOGIC I .;:7 GAIN ADJ.

""11' ¥'~

INSTALLATION AND
OPERATING INSTRUCTIONS

±12 VOLT OPERATION
The DAC850 and DAC851 are fully specified for operation on ±12V power supplies; however, to use the ±IOV
and 0 to + IOV ranges of the voltage output models. the
power supplies must be ±13V or greater. All other voltage output ranges and all current output ranges provide
satisfactory operation with ±llAV supplies. The supplies should be balanced to obtain optimum performance.

,'; 1...

,':~:---T

~!i All BITS

OFFSET
OFFSET A~J.
TRANSLATES
THE LINE

C

Frequency' Hz I

~

1lS~.~-T

~
:=

'2 O.OOO1 ..._

~

IIlf1m

~

2.7Mn or 3.9Mn

.c

,Iii

2701cn

~
-=-

7.5Mn or IOMn

L

All BITS
lOGIC 0
OFFSET

FIGl 'R F 5. Relationship of Offset and Gain
Adjustments for a Bipolar D A Converter.
Offset Adjustment: For unipolar (CSB) configurations.
apply the digital input code that should produce zero
potential output and adjust the offset potentiometer for
zero output.
For bipolar (COB. CTC) configurations. apply the
digital input code that should produce the maxi'mum
negative output voltage and adjust the Offset potentiometer for minus full scale voltage. Example: If the Full
Scale Range is connected for 20V. the maximum negative
output voltage is -lOY. See Table II for correspondi'ng
codes and the Connection Diagrams for offset adjustment
connections.
Gain Adjustment: For either unipolar or bipolar configurations. apply the digital input that should give the
maximum positive voltage outPJlt. Adjust the gain
potentiometer for this positive full scale voltage .. See
Table II for positive fuJI scale voltages and the Connection Diagrams for gain adjustment connections.

6-151

Ii.

u

c

=

.

,'IA6U;: II. Digitallnp,ut/Analog Output,
.'

"

·
"

LSB'

.. ~OoooooooooA .
011111111111"
100000000000
111111111111
One LSB

VOLTAGE'

o to +IOV
·'·+9,9976V
, +S.OOOOV
·+4.9976V
O.OOOOV
2.44mV

Oto-2mA

~,-8~_-,-,!~__11_ _ _ _f,';\ BIPOLAR
& OFFSET
H'r"

FIGURE 6. Output Amplifier Voltage Range Scaling
Circuit.
.
Gain and offset drift are minimized because of the
thermal tracking ofthe scaling resistors with other device
components. Connections for various output voltage
· ranges are shown in Table III. SeUling time fora full scale
range change is specified as 3/Lsec for the 20 volt range
and 2.5/Lsec for the 10 volt range.
TABLE III. Output Voltage Range Connections Voltage Model. .

,...
¥
4.281U1
'
'.
Rlllator I1IInncaa ±2S'Io

15

'1. '
211

lOUT

I

oTO

2.35mA

±25%

FIGURE 8. Current Output Model Equivalent
Output Current,

.

.

Internal scaling resistors (Figure 7) are provided to scale
an external op amp or to configure load resistors for a
low drift direct voltage output. These connections are
described in the following sections.
If the .internal resistors are not used for voltage scaling.
external RL (or R F ) resistors should have a TCR of
±25ppmj"C or less to minimize drift. This will typically
add ±50ppm/"C plus the TCR of RL (or RF) to the'total
drift.

Driving a Resistive Load Unipolar
A load resistance, RL= RLI + RLS. connected as shown in
Figure 9 will generate a voltage range, VOUT. determined
by:'
VOUT = -2.35mA

(RLx7.2kn)
RL + 7.2kn.

Digital
Connect Connect Connect Connect
Input Codes Pin 15to Pin17to Pin 19to Pln'16 to

COBor.CTC
COBorCTC
COBorCTC
Oto+1OV
CSB
CSB
Oto+SV

±5

..." 'S!

II

ately in magnitude. That is: if the scaling resistors are
high by 10%. the internal impedance is high 'by about 8%.
OUTPUT

±10

"

~ ... I

@COMMOII

FROM WEIGHTED
RESISTOR
NETWORK

'6.38k'

REF.'.PUT~

• FIGURE 7. InternalScaling Resis~ors.

-

VOLT~GE OUTPUT MODELS
Output Range Connections
· Internal scaling resistors provided in the DAC850 may be
., , .', connected to produce bipolar output voltage ranges of
. ± 10V, ±5V or ±2.5V or unipolar output voltage ranges of
• 0 to +5V or 0 to + IOV. See Figure 6.

±2.SY

. ,

+1mA

+9.99S1V -1,999SmA -o.9995mA
O.OOOOV -1.0000mA O.OOOOmA
-0.0049V -{l.999SmA +O.OOOSmA
-10.0000V O.OooomA +1.000mA
4.66mV
O.466"A
O.46S"A

o

Output
Range

.'

CURRENT

+1OV

*To obtain values for other binary ranges:
to +SV r,nge diviele 0 to +10V range values by 2.
. ±5V range: divide ±1OV range values by 2.
:t2.5V range: divide ±10V range values by 4.

REF. INPUT

.

ANALOG OUTPUT

DIGITAL INPUT
MSB

' .

(7.2kn u,!-ipolar, 3.07k!l bil?olar) ,tracks thcrtolerance of
: the scaling resistors,in sign and appr!)xiJWltely proportion-

19
18
18
18
18

20
20

15
NC

20
2"
21

20'
NC
20

24
24
24
24
24

CURRENT OUTPUT MODELS
The resistive scaling network and equivalent output
circuit ofthe current-model differ from the voltage model
and are shown in Figures 7 and-8. It is important 10 !Iote
that there is a relationship between the tolerances {)f the
current source and the scaling resistors. The magnitude
of the tolerance tracks very Closely but with opposite sign.
The tolerance of ttie internal resistance of the converter

FIGURE 9. Current Output Model Equivalent Circuit
Connected for Unipolar Voltage; Output
with Resistive Load.
.

To achieve specified drift. connect the internal scaling
resistor (RI.I) as shown to an external metal film trim
resistor (RLs) to provide full scale output voltage range of
o to -2V. Tolerances on internal equivalent resistors are
wide. RI.s will have to be selected for each unit.

Driving a Resistive Load Bipolar
The equivalent output circuit for a bipolar output voltage
range is shown in Figure 10. RL = RI.I + RLs. VOUT is
determined by:
Vo' = ±1.I7SmA(RL x 3.17kO)
ur
RI . + 3.17kO

)-----0+

TABLE IV. Voltage Range of Current Output D/ A
Converter.
Output
Range

Digital
Input Codes

®nect

Pin 17 to

±10V
±5V
±2.5V
Oto +10V
Oto +5V

COBorCTC
COBorCTC
COBorCTC
CSB
CSB

19
18
18
18
18

,15
15
15
21
21

A

to

Connect

Connect
Pin 19to

@
NC
15
NC
15

Connect

Pin 16to
24
2424
24
24

Output Larger Than.20V Range
For output voltage ranges larger than ±IOV. a high
voltage op amp' may be employed with an external
feedback resistor. Use Im'T values of ± 1.17SmA for
bipolar voltage ranges and -2.35mA for unipolar voltage
ranges (see Figure 12). Use protection diodes when a high
voltage op amp is used.
The feedback resistor. RF• should have a temperature
coefficient as low as possible. Using an external feedback
resistor. overall drift of the circuit increases due to the
lack of temperature tracking between RF and the internal
scaling resistor network. This will typically add SOppm. "c
+ RF drift to total drift.
~

=

~------------------------------,~

=

FIGURE 10. Current Output Model Connected for
Bipolar Output Voltage with Resistive
Load.
To achieve specified drift. connect the 1.71kO and
2.55kO internal scaling resistors in parallel (RI.I) and add
an external metal film resistor (RLs) in series to obtain a
full scale output range of ± I V. The tolerances on the
equivalent internal resistors are wide. R'$ will have to be
selected for each unit.
Driving An External Op Amp
The current output model will drive the summingjunction
of an op amp used as a current-to-voltage converter to
produce an output voltage (see Figure II).

4.281C1l

426ku

WOUT

I

all
2.35mA

WOUT

*F.. DUtpuI vII.... Iwt",1 up tD l40V P-/I.

FIGURE 12. External Op Amp- Using External
Feedback Resistors.

LOGIC INPUT COMPATIBILITY
DAC8S0 and DAC8S1 digital inputs are TTL. LSTTL.
S4/74HC CMOS compatible as shown in the specification table when VDO is operated over 4.5 to 16.S volts.
Figure 13 illustrates using CMOS hex buffers with
DAC8S0 to provide CMOS input compatibility. This
combination will operate together over a wide range of
logic power supply voltages.

Df

II OPAl105HG
'f.. fllllIItI.... allli.

FIGURE II. External.Op Amp - Using Internal
Fe,edback Resistors.
VOUT = lOUT X RF
where lOUT is the output current and .RF is the feedback
resistor. USing the internal feedback resistors of the
current output model provides output voltage ranges the
same as the voltage model. To obtain the desired output
voltage range when connecting an external op amp. refer
to Table IV.

6-153

FIGURE 13. Using DAC8S0 851 with CMOS Hex
Buffers Over a Wide Range of Logic Power
Supply Voltages.

BURR-BROWN®

PCM51JG

IElElI

DESIGNED FOR AUDIO

16-Bit
DIGITAL-TO-ANALOG CONVERTER
.,.'
",

""

FEATURES

DESCRIPTION

• 16-BlT RESOLUTION
• 350nsec SETTLING TIME. typ (I Model)
• 5/lsec SETTLING TIME. typ (V Model)
• 0.006% OF FSR MAX DIFFERENTIAL LINEARITY
ERROR (0.0025% typ)
• 0.0025% THO (FS Input, 16 Bits). typ
• 0.012"/0 THO (-I5dB. 16 Bits). typ
• 96dB DYNAMIC RANGE .
• EIAJ STC-007 COMPATIBLE
• PIN COMPATIBLE - OACn & PCM50

The PCM51 is designed for PCM audio applications
and is compatible with ElA] STC"()07 specifications.
The PCM51 may be operated as either a 16-bit or a
14-bit converter, It features wide dynamic range, low
differential linearity error, low distortion. and has a
very-fast settling time.
The PCM 51 contains an internal voltage reference,. It
uses state-of-the-art IC and laser-trimmed thin-film
components. The converter combines high quality
and high performance with low cost.

• LOW COST
BOTH VOLTAGE·OUTPUT fPCM51JG·YI
ANO CURRENT·OUTPUT fPCM51JG-l)
MODELS ARE AVAI,LABLE.
I
PCM51JG~ ODES NOT CONTAIN OUTPUT
OPERATIONAL AMPLIFIER.

REFERENCE
VOLTAGE

RF

PARALLEL
DIGITAL
INPUT

18·81T LADDER
RESISTOR NETWORK

AND

AUDIO OUTPUT

CURRENT SWITCHES

International Airport:lndustrial Park .P;O. Box 11400 • TUCIDO. Arizona 85734 • Tel: 16D2) 746·1111 • Twx: 9l0-952·1I1.1·'Cable: BBRCORP • Telex: 66-6491

6-154

I

MECHANICAL

SPECIFICATIONS
ELECTRICAL
ITA = +25°C and rated power supplies unless otherwise noted.)
MODEL

L

I

PCM51JG
TYP

MIN

UNITS

MAX

INPUT
DIGITAL INPUT
Resolution
Dynamic Range
Logic Levels ITTL-Compatiblel1 1 1
Logic "1" at +40"A
Logic "0" at -1.6mA

I

16

I

VDC
VDC

±10

±a.5
±100

%
mV

0.0025

0.006

% of FSR(31

0.004
0.0025

0.005

%
%

0.023
0.012

0.06
0.04

%
%

±0.1

Gain Error
Bipolar Zero Error(2)
Differential Linearity Error
at Bipolar Zero
TOTAL HARMONIC DISTORTIONI'I
Vo = ±FS at f = 400Hz
14-Bit Resolution
16-Bit Resolution
Vo = -15dB alf = 400Hz
14~Bit Resolution
16-Bit Resolution
Vo = -20dB at f = 400Hz
14-8it Resolution
16-Bit Resolution
Vo = -60dB at f = 400Hz
14~Bit Resolution
16~Bit Resolution

0.025

%
%

4.2
1.9

%
%

0.04

DRIFT lOver Specified TemperatureRangel
Total Bipolar Drift (includes gain,
offset. and linearity drift I

±25

13

11 ~\"" ......... ~'

ATtA~

NL

CASE: Black Ceramic
MATING CONNECTOR: 245MC
WEIGHT: 8.4 grams 10.3 oz. ,
HERMETICITY: Conforms to
method 1014 condition C step 1
,fluorocarbon. of MIL-STD-883
(gross leak!.

ppm of FSRfOC;

±50

DIM
5
3
20

~sec

,.,.sec.:
V/"sec

350
350

•c

Indefre

Range

MIN

MAX

33.21

34.54

.110

.810

19.56

20.51

.150

.210

3.81

5.33

.018

.021

0.46

0.53

F

.035

nsec

G
H

. 110

K

'50
.600 BASIC

,

A

±10
.±5I')
±5
0.1

MAX
1.360

a

N

ANALOG OUTPUT
Voltage Model. PCM51JG-V
Ranges

MILLIMETERS

MIN
1.310

nsec
Min

1

A

050
.100 BASIC

.oUTPUT

Output Current
Output Impedance I DC I
Short-Circuit Duration
Current Model. PCM51JG-1

f

INCHES

SETTLING TIME I To ±0.006% of FSR,
Voltage Model. PCM51JG-V
Output: 20V Step
1LSB Step(S)
Slew Rate
Current Model. PCM51 JG-I
Output: 1 mA Step
Ion to 100n load
1kll Load(S)
WARM-UP TIME

Bits
dB

+5.5
+0.4

TRANSFER CHARACTERISTICS

Pin numbers
shown for
reference only.
Numbers may
not be marked
on package.

plane.'

I

96
+2.4
0

NOTE: Leads
in true position,
Within 0.10·
(0.25mml R at
MMC at seating

'30
250

00'

0'0

0 ••

'0'

.

o B.

'"

254 BASIC

,,

3.30

3.Bl

6.35

1524 BASIC

005

2>.

0.25
2.61

V
V
mA
n

~: CT mon

mA
kll

Output Impedance
POWER SUPPLY
SENSITIVITY
-15VDC
+15VDC
POWER SUPPLY REQUIRMENTS
Voltage. Vs
Supply Drain, +15VDC I no load·
-15VDC

%01 FSRI%Vs
%of FSR/% Vs

±0.02
±0.002.
±14.5.

±15
±25
-40

±15.5

VDC
mA
mA

+70
+85
+85

·C
·C
·C

TEMPERATURE RANGE
Specification
Operating' derated specs
Storage

0
-25
-55

NOTES:
Adding external CMOS hex buffers CD4009A will provide 15VDC CMOS
input compatibility. The percent change in output t VOl asJogicO varies
fromO.OV to +O.4V and logic 1 changes from +2.4V to +5.0V on all inputs
is less than 0.006% of FSR.
. .
2. Adjustable to zero with external trim potentiometer.
3. FSR means Full Scale Range and is 20V for ±10V range and 10Y for
±5V range.
4. The measurement of total harmonic distortion is highly dependent on'
the characteristics of the measurement circuit. A block diagram of a

measurement circuit is shown in Figure 3. Burr-Brown calculates THO
from the measured linearity errors using equation (2) in the secti~n on
"Total Harmonic Distortion", and specifies that the maximum THO
measured with the circuit shown in Figure 3 will be less than the limits
indicated.
5. LSB is lor \.4-bit resolution.
6, Measured with an active clamp, as shown in Figure 10. to provide a low
impedance for approximately 200nsec.
7. Connect pin 24 to pin 17 to obtain ±5V range.

6-155

in
:IE
c.:»
a..

CONNECTION DIAGRAM,

,.. ,

PIN ASSIGNMENTS

:'!'

,PiA

!:!2:
l'
2
3

+V.

4
5
6
7

8
9
10
11
12
13
14
15
16
17
18
19
20
21

-V.

22
23
24

THEORY OF OPERATION
The accuracy of a DJ A converter is described by the
transfer function shown in Figure I. The errors in the
D J A converter are combinations of analog errors due to
the linear circuitry, matching and tracking properties of
the ladder and scaling networks, power supply rejection,
. and reference errors. In sU\TImary, these errors consist of
initial errors inCluding Gain, Offset, Linearity, Differential Linearity, and Power Supply Sensitivity. Initial
Offset or Bipolar zero errors may be 'adjusted to zero.
Gain drift over temperature rotates the,line (Figure I)
about the minus full scale point (all bits oro, and Offset
drift shifts the line left or right over the operating
temperature range. Most of the offset and gain drift with
temperature or time is due to the drift of the, internal
reference zener diode. The converter is designed so that
ALLBITSON,
SAIN
ERROR"

0000...0000

•
.
•

0000...0001

..
...

:::>

5

~

I

0111 ...1101
0111 ...1110
0111 ...1111
1000...0000
1000_.0001
1111 ... 1110
111 L.11I 1

~
ERROR
\

'\

•

•

AlIALOG OUTPUT

"SEE TABLE I FOR DIGITAL CODE DEFINITIONS.

FIGURE I. Input vs Output for an Ideal
Bipolar D/.A Converter.

'1
2
3
4

5
6'
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21
22

23
24

Bit 1 {MSBI
Bit 2
Bit 3
Bit4
Bit 5
,Bil6
Bit7
Bit8
Blt9
Bitl0
Bitll
Bit 12
Bit13
Bit14
BitlS
Bit lS
CODE

9421
94113
9'535
9'5A'5
9603
964E
9687
96AD
96ce
96(0
96AD
9697
-:.o64E
9610;:
95A'5
953'5

','I

'~4B'3

",~

':'421
937[1
92(9

;'3
~,

4-

:'5

9';::05

':'6
<:'7
':'8
':'9
Hllo
11)1

9133
',,0'52
8F63
8E68
8D60
8C4D
81130
8A0A
8eDil
El7A'S

10';:
10:::

I.H

,.5
,.,
107
J08

,.9
11.

B669

8527
El.3El
8297
B14(

IDEAlDAC
DC' V,)115

'DEAl SINE
VAlUE VOll5

QUANTIZING
ERROR 11"115

-1.572876
-1.617432
-1.6'5711214
-1.691284
-1.719971
-1. 742a~9
-1.76103.254
-1.771:351
-1.777649
-1.777049
-1.771851
-1.760.254
-1.742359
-1. 719971
-1.69128"
-1.657104
-1.61 ?432
-I. '572376
-1. ~228.o:;,
-1.467896
-1.4€1SO'el
-1.343':'94
-1.27'53,,121
-1.2002393
-1.125793
-1.04'5227
-.961304
-.87432'"
-.784697
-.692139
-.59:'534
-. '50109~
-.492832
-.30334'5
-.202637
-.101624

-1. 5727b~
-1.617580.
-1.6'57115
-1.691244
-1.7198'57
-1.742861
-1.7601 :'9
-1.7717'56
-1.777554
-1.777'554
-1.7717'56
-1.761211;'9
-1.742861
-1.719&'57
-1. 691244
-1. 6S7J:'5
-1.6175813
-1. '572769
-1.5228;:8
-1.467920
-J. """122';'
-1.3439"3"
-1.U'5.r::t.'1
-1.202428
-1.1256:'3
-1.045240
-.96141(1
-.67443-;'
-. ;'84614
-.6922;-1

.0'110107
-.000149
-.880018
.000.849
.890113
- .000902
.000875
• 0000'H
.0000.9'5
.1210809'5
.000094
.001210:''5
-.0121121002
.000113
.000040
-.000010
-.009148
.00010i
-.0130001
-.1390024
-.131211314'<:
· 000~60
'.0090159
-.1309035
• 0001~0
-.01019019
-.130010;'
-.000110
-.121000007
-.00121092
-.1300056
· 000099
.0008'57
.00010'51
-.000072
.00121184

-.537'59~

-.'5ge99'"
-.4e277'5
-. 39323~,
-.202709
-.101'520

PCM52JG-V

BURR-BROWN®

,IElElI

PCM~3JG-V

PCM53JP-V
'PCM53JG-1

DESIGNED FOR AUDIO

16-Bit Monolithic'
DIGITAL-TO-ANALOG CONVERTER
F.EATURES

DESCRIPTION

• LOW COST
• NO EXTERNAL COMPONENTS REQUIRED
• IS-BIT RESOLUTION
.16·BIT MONOTONICITY. typ ,

The PCM52 andPCM53 are state-of-the-art, fully
monolithic, qigital-to-analog conveiters that are
designed and specified for digital audio applications.
These devices employ a· segmented architecture and
ultra-stable, nichrome (NiCr), thin-film, wellmatched resistors to provide monotonicity, low
distortion, and low differential linearity error (especially around bipolar zero) over long periods of time
,
and over the full operating ,temperature range.
The PCM52-V and PCM53-V are completely selfcontained with stable, low noise; internal, zener
voltage reference; high speed current switches;
resistor ladder network; and fast-settling; low noise.
output operational amplifier all on a single monolithic chip. A special: open-loop reference 'circuit
helps provide the fast-settling time required for
critical audio' applications., The converters can be
operated using two power supplies (± 15V) instead of
three separate supplies. Fe~ external components
are necessary for operation, and all critical specifications are JOO%tested.l'his helps to assure the:userof
high system renability and outstanding overall system.
p~formance.
'
,
The PCM53JG-I is simil~r to thePCM53JG-V
except it' provides a current o,utput that settles to
within ±O.OO6% of FSR'of its final value in typically
350nsec in re'sponselo a full-scale change. in thi:
digital input code.
'
The letters JG and JP after the number (PCM53JG
ot PCM53JP) refer to the package'type: the JG
refers to a ceramic DIP package and JP refers to a
plastic molded package. The letters -V and -I
(PCM53JG-V and PCM53JG-I) refer to the voltageoutput and current-output models respectively. These
models are currently available: PCM52J,G-V,
PCM53JG-V, PCM53JP-V, PCM53JG-1. Other
family members may become available later.

•o.run %OF FSR, TYP DIFFERENTIAL
LINEARITY ERROR
.0.002% THO (FSlnput. 16 Bltll. typ
.0.02% THO (·20dB.16 Bltsl. typ
• 3/llec SETTLING TIME. typ
• 96dB DYNAMIC RANGE
• ±10V (PCM531 AND ±5V (PCM521 AUDIO _
OUTPUT AVAILABLE
• EIAJ STC'{)07COMPATIBLE
• INDUSTRY·STANDARD PIN OUT
• COMPACT. 24-PIN. DlL PACKAGE

.15V

-15V

R,I

PARAUEL
DIGITAL
INPUT

Intematlanal Airport Industrial Park· p.o. Box 11400· Tucson. Arizona 85734· Tel. 1602) 748·1111 . Twx: 910-952·1111 . Cable: BBRCORp· Telex: 66-6491

6-162

SPECIFICATIONS
ELECTRICAL
TA

= +25°C rated power supplies unless otherwise noted.

I

MODEL

I

PCM52/PCM53
TYP

MIN

MAX

UNITS

+Vee
+0.8

dB
VDC
VDC

INPUT
DIGITAL INPUT
Resolution
Dynamic Range
Logic Levels (TTL/CMOS Compatible): Logic "1" at +401lA
Logic "0" at -0.5mA

Bits

16
96
I

+2.4
0

TRANSFER CHARACTERISTICS
ACCURACY
Gain Error
Bipolar Zero Error( 1 )
Differential Lil"!earity Error at Bipolar Zero
Noise (rms)(20Hz to 20kHz) at Bipolar Zero: PCM52-V'"
PCM53·V 131

±0.1
±10
0.001
15
30

±1.0
±50
0.005

%
mV
%ofFSR I2J

30

J.IV
J.IV

TOTAL HARMONIC DISTORTION'" (l6-Bit Resolution)
Vo ±FS at f 420Hz
Vo -20dB at f 420Hz
Vo -60dB at f 420Hz

0.002
0.02
1.9

0.004
0.04

=
=
=

=

=
=

60

4.0

DRIFT (0· C to +70· C)
Total Bipolar Drift (includes gain, offset, and linearity drift)

±25
±0.1
±0.01
±4

Bipolar Zero Drift
SETTLING TIME (to ±0.006% of FSR)
Voltage Models (PCM52-V, f'CM53-V) Output: 10V Step
lLSB Step
Current Model (PCM53-I) Output (lmA Step): 100 to 1000 Load

3
1
350
350
2.5
10

1kO load m
Deglitcher Delay (THO Test)tSI
Slew Rate

±150
±0.68
±0.06
±20

ppm- of FSRI" C
%of FSR
dB
ppm of FSR/· C

psec
/-Isec

4.0

naee
nsec
lISee
V/J.lsee

1

WARM-UP TIME

%
%

Bits

16

MONOTONICITY

%

.

Min

OUTPUT
ANALOG OUTPUT
Voltage Models
Ranges: PCM53-V
PCM52-V
Output Current
Output Impedance
Short-Circuit Duration
Current Model
Range, PCMS3-1 (±3O%)
Output Impedance (±30%)

±10
±5

±9.8
±4.9
±5

±10.2
±5.1

V
V

mA

o

0.1

I

indefinit::o commlon
2.4.

mA
kO

±0.001
±0.001
±0.001

% of FSR/%Vcc
% of FSR/%Vee
% of FSR/%Vee

POWER SUPPLY
SENSITIVITY

+Vee
-Vee
.vpo
POWER SUPPLY REQUIREMENTS
Voltage: ±VCC'8/

±14.25
+4.75

VOD IS )

(Voo may be connected to +Vcc supply voltage. Result is slightly
increased total power dis~ipation of approximately 40mW).
'
SU[ilply Drain (no load): +Vee 181

-Vee 'tll
VOO ISI

±15
+5

±15.75
+15.75

VDC
VDC

+18
·-18
+4

+30
-30
+10

mA
mA
mA

+70
+85

·C
·C

TEMPERATURE RANGE
Specification
Operating

NOTES: 1. Adjustable to zero With external potentiometer.

o
-25

2. FSR means Full Scale Range and IS 20V for ±10V (PCM53-V) and 10V for ±5V range

(PCM52~V). 3. Characterization units show at least two sigma units to meet this specjfication. Not 100% final tested. 4. The measurement
of total harmonic distortion is highly dependent on the characteristics of the measurement circuit. A block diagram of a measurement circuit
is shown in Figure 2. Burr-Brown may calculate THO from the measured linearity errors using equation (2) in the section on "Total Harmonic
Distortion," but specifies that the maximum THO measured with the circuit shown in Figure 2 will be less than the limits indicated.
5. Oeglitcher or Sample/Hold delay used in THO measurement test circuit. See Figures 2 and 3. 6. See Connection. Diagram and Pin
Assignments. 7. Measured with an active clamp to provide a low impedance for approximately 200nS8C.

6-163

MECHANICAL

CONN~CTION

r

DIAGRAM

JPPACKAGE

PCM53JII-l_
not CIIIIIln A.I.

(TOP VIEW)

24

; +vee

!
1

·Vee
.•

OfM

AI

•
C
F
G
H

N

INCHES
MIN
MAlt

1.'"

....
.1"

MilliMETERS
MIN
MAlt

1 .••• 3t.1t .1 .• 1

.111 .... 17 14."
" .• 1 '.70
I.
.04
.01 •. 1.01 t. 7
.1001.I.C 1.1 .. 8"1',C
.0'0 .010 0.71 " , •
•00
.0"
0.10 0 .• '
.t
.1
2.1" ....
. 100 I. I , ..... I"I'C
o· ".
O.
, .e
.0,. .022 0:'"
0."

.'1

.11.

0."

NOTE:

Leads in true position
within 0.10" (0.25mm Rat
MMC at seating plane.

[~[]~]l
c-- . -. -

AUDIO OUTPUT
±&V'RANSE IPCM52·VI
±IOV RANIE (PCM53-Vj

*R. = 5kCl (PCM52)
= IOkClIPCM53)

JGPACKAGE
. (TOPVIEWI

PIN ASSIGNMENTS

:.J

PIN
NO.
1
2
3
4
5
6
7
8
9
10

NOTE:
Leads In true position within 0.Q10"
(0.25mml R at MMC at seeting plane.

11
12
13
14
15
16
17
18
19
20
21
22
23
24

Actual package, such' as cover appearance,
may vary slightly from unit to unit. Pin
spacing will not change ..

ABSOLUTE MAXIMUM RATINGS
DC Supply Voltages
Input Logic Voltage
Storage Temperature
Lead Temperature
During Soldering

±18VDC
-1V to +Supply Voltage
-55°C to+100oC .
10sec at +300oC

6-164

PCM52/53-V
Bit 1 (MSB)
Bit 2
Bit3
Bit4
Bit5
Bit 6
Bil7
Bit8
.Bit9
Blll0
Bit 11
Bil12
Bit 13
Bit 14
Bit 15
Bit 16 (LSB)
±5V AUDIO OUT (PCM52-V)
±10V AUDIO OUT (PCM53-V)
Veo
-Vet;
COMMON
SUMMING JUNCTION
TEST POINT
+Vcc
REFERENCE OUT (+6.3V)

PIN
NO.

PCM53-1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

Bit 1 (MSB)
BI12
Bil3
BI14
Bit5
-Bit 6
Bit 7
Bit 8
Bit9
Bitl0
Bil11
Bit 12
Bit 13
BII14
Bit 15
Bit16 (LSB)
R. (10kCl ±30%)

18
19
20
21

VDD
-Vo<>
COMMON
lOUT. ±lmA ±30% '
(AUDIO OUTPUT)
TEST POINT
+Voc
REFERENCE OUT
(+6.3V)

22
23
24

THEORY OF OPERATION
AND AUDIO SPECIFICATIONS

DYNAMIC RANGE
The Dynamic Range is a measure of the ratio of the
. smallest signals the converter can produce to the fullscale range and is usually expressed in decibels (dB). The
theoretical dynamic range of a converter is approximately 6 X n, or about 96dB for a l6-bit converter. The
actual, or useful, dynamic range is limited by noise and
linearity errors and is therefore somewhat less than the
theoretical limit. However, this does .point out that a
resolution of at least 16 bits is required to obtain a 90dB
minimum dynamic range, regardless of the accuracy of
the converter. Another specification that is useful for
audio applications is Total Harmonic Distortion (THD).

The transfer function of an ideal binary Dj A converter is
a set of discrete output levels that lie on a straight line as
shown in Figure I. The number of possible discrete
output levels, or resolution, is equal to 2" where n is the
number of digital inputs or "bits". The PCM52j 53 has 2'"
or 65,536 possible output levels. Another method of
expressing resolution that is useful in audio applications
is Dynamic Range.

' '-' ' b

mm ...

~

0000 ... 0001

l:0

a..

!!

....

i

!

.1

TOTAL HARMONIC DISTORTION
ALL BITS ON ,
GAIN

.

."

,ORIFT"

•

0111 •.. 1110

THD is useful in audio applications and is a measure of
the magnitude and distribution of the Linearity Error,
Differential Linearity Error, and Noise, as well as
Quantization Error. To. be useful, THD should be
specified for both high level and low level input signals.
This error in unadjustable and is the most meaningful
indicator of DJ A converter accuracy for audio appli- &.I
cations.
:E

•

0111 ..• 1\11

1000 ••• ~
1000 _II1II1

IfII .•• 1110
1111 •• 1111

OFFSET

L·
DRIFT~

•

•

U

I

•

I.'

·FSR/2

, BIPOLAR ZERO

ANALOG OUTPUT

I

The TH D is defined as the ratio of the square root ofthe D..
sum of the squares of the values of the harmonics to the
value of the fundamental input frequency and is expressed
in percent or dB. A block diagram of the test circuit used
to measure the THD of the PCM52J 53 is shown in Figure
2. A timing diagram for the control logic is shown in
Figure 3.

(+FSRI2I·1 LSB

"SEE TABLE I FOR DIGITAL CODE DEFINITIONS.

FIGURE I. Input vs Output for an Ideal Bipolar
Dj A Converter.

BB3560K
ANALOG SWITCH
OR EQUIVALENT
(MP7512 OR EQUIVALENT]

r---'I ' 101m.

. , . _......L

1-1-..J
SIMPLIFIEDSCH~ ~
+

I

[

OF DEGUTCHER

2X
74LSI81
BINARY
. COUNTER

..

2X
2716
PROM'S

VOUT

•
5pF

~

"-

OEGLITCHER
CONTROL
4X
LATCH
74LS75

USE 400Hz HIGH·PASS
FILTER AND 30kHz
LOW·PASS ALTER.

"-

DISTORTION
METER

SHIBASOKU
MODEL 725
OR EQUIVALENT

.......
"-

OUT
(PCM52/531

"-

"-

DEGLITCHER

LOW·PASS
FILTER

TOKO
MODEL 1·231-38-11
OR PCMII OR
EQUIVALENT

DEGLITCHER CONTROL

0_,....,-........,....,
TIMING
CONTROL
LOGIC

-20.f-+-~~~

SEE CONTROL LOGIC TIMING (Figure 3~

i

-40 '-+-+-+--+4--1

!CD,-8011-++-+-I-I--l
.aof-+-~HI+-l

·IQQ '--J.,-J.,-.J....~IP
LOW·PASS FILTER
CHARACTERISTIC

FIGURE 2. Block Diagram of Distortion Test Circuit.

6-165

1 tOl 102 103 104 105
FREQ. (Hz(

• : LATCII ENA8LE
C: DESLITC\tER
CONTROL

is 420Hz and tlie aIl1pli~ude, of the. input. signalis OdB •
.
Figure 4 shows thetypic~THD-as ~. function of output
voltage.
Figure 5 shows typical TlfDas a function of frequency.

nL..__~nL..--"_..,.j~

-tJ11 I"IiOIIftuc

-20d~. and -60dB down from. full scale:

u

1lJ'. ..

-1,- 2.5!<11C
1: CLlICK

i!

. FrGURE 3. Control Logic Timing for PCM52/53
Distortion Test Circuit.

iD.02r+~~+H~-r~~H

1~~~~~~j!lIlI!I~j!lI!lII~~t
!~~Jttmml-~~~~-FHn~~

If we assume that the error due to the test circuit is

ii

negligible. then the. rms value of the PCM52/53 error
referred to the input'can be shown to be

0.01

1·2OdB!.;

~iJ.D05

Q

E,m.

= I{ Q [ELCi) + EQ(i)l' ..

I

(I)

frtlJlllncy

where n is the number of samples in one cycle of any given
sine wave. EI.{i) is the linearity error of the PCM52/ 53 at
each sampling.point. and EQ(i) is the quantization ertor
at each sam piing point. The TH D can then, be expressed
as

I+. ,=1Q[EI.(i) + EQ(i)]' x 100%

THD =~ =
_ Erms '

Erms

DIGITAL INPUT CODES
The PCM52/53 accepts complementary digital input
codes in binary format. It may be connected by the user
for either complementary offset binary (COB) or complementary two's complement (eTC) codes. See Table I.

. TABLE I. Digital Input Codes.

This expression indicates that. in general there is a
correlation between the THD and the square root of the
sum of the squares of the linearity errors at each digital
word of interest. However. this expression does not mean
that the worst-case linearity error of the D / A is directly
correlated to the TH D.
For the PCM52/53 the test period was chosen to be
22.7psec (44.lkHz) which is compatible with the EIAJ
STC-007 specification for PCM audio. The test frequency

2.0

I.D

",

.0.4
D.2
0.1

.... ~\

rY

Q.04

D.02
0.01
0.004
0.002

.0.001

DIGITAL INPUT CODES

MSB LSB
All bits 01\1
Mid Scale
All bits.OFF

I

~

0000 ... 000
0111 ... 111
1111 ... 111
1000 .. ,000

COB

CTC'

Complementary
Offset Binary

Complementary
Two's Complement

+Full Scale
Zero
-Fu·II.Scale
-1LSB

-JLSB
-Full Scale
Zero
+Full Scale

• A TTL inverter must be connected between the MSB input signal
and bit 1 I pin I ,. to obtain CTC input cod~.

DETAILED THEORY OF
OPERATION

10.0
4.D

IHzl

FIGURE 5; Total Harmomc DistortIOn (THD)
vs Frequency.

(2)

where En.. is the rms signal-voltage level. .

rllll karl

0.00l~~"~~IOO~~--~~I~k----~~~l.~~~

i=1

.eo -50 -40
0dB ItJUlllfall sail RllltJllfSR)

14-8111

,,\ ~

~
l(alll

~

-30 ·20 ·10
VOUT (d.1 .

0

FIGURE 4. Total Harmonic Distortion (THD) vs VOUT.

6-166

In the basic design, the three functions represented by
the ,complete D / A converter-th.e voltage reference, the
output amplifier, and the converter-are distnbuted
among six major circuit blocks (Figure 6). Three
blocks---:the open loop reference, the current-offset
circuit, and the reference output amplifier-perform the
reference functions., The D/A conversion is performed
by two circuits called ihe upper converter and the lower
converter, which are cQmbined into the voltage output
by the on-chip output op amp.
The prime requirements for a D/A converter circuit
designed for PCM audio applications are that it have
low differential linearity error and monotonicity and
that it stay that way over a useful temperature range. To
obtain this performance at 14 to 16 bits, the converter
combines,segmentation with multiple R-2R networks.

Vo""

lmA

MSB
alll alT 2 alT 3

i1

m

10""7(

131

(

'DA'"

~aIT~
4"

+Vee

+Vcc

-Vee

TT

~

I......

~ R...

SYSTEM
6RDUND

+VLogIC

LSa
BIT 16

-(ill

---------8ITS 5-15-- - - - - - - - -

v..
MODifiED
2R R·2R LADDER R

0,

•

•

..
2R

2R

1 ..
R

L-______~~~~~--~~--~~Vr~~~~~~~~~~ ..

-

1"

9"0'1
-....J

• 1 • 1

1"

2R

SECONDARY
LADDER

,I

.1

...

2R
R

alTs
9·16

all 6

all 7

. ..
Yli(

I

'CURRENT
OFFSET
I....-- DPEN.LooP REfERENCE ~ I

mJ

-Vee
UPPER CONVERTER
. (aITS 1-3)

.J L

'-----

.

..

..

alT 5
BIT a
alT 4
._____ LOWER COIVERTEI _ _ _ _ _ _ _ _ _.J
(aITS 4-16)

FIGURE 6. Simplified Circuit Diagram of the PCM52/53 16-bit Digital-to-Analog Converter.

PCM52

The upper' converter, which, generates' the three most'
significant bits, is made up 'of seven equal curren~
sources (Ql REI through Ql RE7), each providing 0.~5mA.
Together the sources form the upper converter current,
IOAcu.
\ The three binary-coded MSBs (bits I, 2, and 3) are
decoded by a three-to-seven-line circuit, which sequentially selects the equiil current sources as the 'binary code
formed by the bits changes through the eight values (000
to Ill). Thus, as the code ranges through its values, IOAcu
changes from 0 to I. 75mA. This scheme ensures monotonicity, reduces initial matching and tracking requirements, and cuts the tracking errors that occur with
temperature and time.
Averaging Transistor and Resistor ShiHs
To further improve the tolerance of the upper converter
to time and temperature change, the seven equal currents
are turned on in the following order: Q., Q2, Q7, Qs, Ql,
Q6, Q3. This sequence, which produces the zero-to-fullscale output, averages the shifts that occur in transistor
parameters and in the value of theemittet resistors;'
The 13 least significant bits \ire produced by the lower
converter, which uses nine more equal-current sources
for the nine middle bits and emitter area rationing for
the 4LSBs. However, rather than being summed directly'
by the current of the upper converter (which would have
required 2 16 -1 equal current sources) the current
sources are further divided binarily by a pair of R-2R
networks, called the modified R-2R ladder and the
secondary ladder. By diverting the LSB currents through
the modified ladder, the lower converter produces IOACL.
This current consists of 213 -1 discrete, 30nA steps for
each 0.25mA segment of the upper converter. IOAcu and
IOAcL are added at the summing junction, SJ, to form the
IOAc, which has a range that varies between 0 and
1.99997mA.
The modified R-2Rladder IS superior t~ a conventional
R-2R ladder because its output can be increased or
decreased by laser-trimming of its' output resistors (Rx
and Ry). Such trimming does not change the binary
current division in the hidder. The gain of the lower
converter can then be trimmed relative to the gain of the
upper converter without interacting or in any way
affecting the linearity of the lower converter.
The initial values oEthe 16 current sources are determined
by the voltage at the output of the reference (the emitter'
of Q23), but the sources are set to the same value when
the emitter resistors (Rl-RI6) are laset~trimmed. The
sources 'are turned on and off by a differential switch
, pair (such as QSA-QSB) driven by the low-power Schottky
TIL-compatible input circuit (typical of Os, Rs, Qs, Zs).
The input circuit provides the level translation.

Constant Power
To maintain 16-bit performance, the on-chip power
'dissipation-and therefore the chip temperature-'-must
be kept constant during code changes. Therefore the

curren't from both the ON side (QlB) and the OFF side
(Q1A) of each 'differential switch pair in' the uppe(
converter should come from + Vcc, rather than one from
+Vcc and one fromgrounl!; The ON'side currents (when
the bits are on) come from +Vcc and flow 'through A2
and the feedback resistor, Ro" to the summing junction
to form IOAcu. Transistor Q22 is used to provide the
OFF side current with a similar path to +Vcc. In the
lower converter, the secondary R-2R>ladder, which is
connected between the OFF side of the differential
switches and Q22, provides the same function by keeping
the +Vcc current and the analog ground current
constant with code changes.
The secondary ladder also significantly reduces linearity
errors that would otherwise be caused by external
ground wiring. Indeed, the secondary ladder makes
possible the use of a single ground ,pin, which is the only
way to make all the connections in a 24-pin package.
Most converters use a closed-loop op amp for precision
DC biasing of their current sources. However, switching
transients can cause excessive settling time in the op
amp. To ensure minimum settling time, the PCM52/S3
uses an open-loop reference circuit, which incidentally
does not require space-consuming capacitors for frequency compensation or suppression' of switching
,transients.
The reference voltage is generated, by a Kelvin-sensed
buried zener diode. Kelvin sens'ing is used because the
elements of the buried zener, RA and RB, have a large
and nonlinear temperature coefficient. The Kelvin,sensed connection removes from the reference path the
large voltage drop, RBlz, caused by the IrnA zener
current h, Instead it substitutes the voltage drop
produced across RA by'the base current of QB.
Since this base current is only I~A, the drop is negligible,
and the true zener breakdown, Vz is sensed. In addition
great care W\iS taken to ensure that all temperaturesensitive parts of the open-loop reference were laid out
along lines of thermal equilibrium, to prevent thermal
,settling tails.
High-Speed Output Amplifier
The converter's output amplifier, A2, which sums all of
the output currents and converts them into the output
voltage, VOAC, must be just as accurate as the reference
and current sources and just as fast as the switching
circuits.
The amplifier is very fast, and it is well behaved when
driving a capacitive load. It slews at lOY / ~sec and
typically settles to 0.003% of final value in less than
4~sec for a 20V step. ,For a step of ILSB at the major
carry, it settles in 1.5~sec. The thermal tails caused by
temperature gradients and resistor self-heating are less
than 0.001% of full scale.
Thermal tails occur when thermal gradients across the
chip change as signal levels change. For example, when
driving a load the output stage of the amplifier and its
feedback resistor generate more heat at the full-scale
output voltage than at zero. Therefore the temperature-

6-168

sensitive differential input stage, which is close by on the
chip, uses cross-coupled transistors and resistors to
equalize thermal gradients.
To achieve a ±IOV output swing when operating from
±15V, the output stage of the amplifier uses two
transistor pairs connected in series. This scheme is
necessary because the breakdown voltage of the npn
transistors is limited to 20V by the semiconductor
process.
In addition, the output stage is biased in a class AB
condition, so that current is always flowing. Continuous
current flow is essential to ensure that the open-loop
gain, Ao, and closed-loop output impedance, Ro, remain
constant for both positive and negative full-scale output
swings at 103dB and 0.030, respectively. With lesser
performance, errors would occur. If, for example, Ao
changed from 94dB to 100dB for an output swing of
-lOY to +IOV respectively, the output error would
change by iOOj.lV, and the change would be nonlinear.
Likewise a nonlinear error approaching 2ooj.l V would
occur if Ro changed from 0.040 to O.OSO.

DISCUSSION OF
SPECIFICATIONS
The PCM52/53 is specified to provide critical performance criteria for a wide variety of applications. The
most critical specifications for a 01 A converter in audio
ap plications are Total Harmonic Distortion, Differential
Linearity. Error, Bipolar Zero Error, parameter shifts
with time and temperature, and settling time effects on
accuracy. The PCM52/53 is factory-trimmed and tested
for all critical key specifications.
The accuracy 01 a 01 A converter is described by the
transfer function shown in Figure I. The errors in the
01 A converter are combinations of analog errors due to
the linear circuitry, matching and tracking properties of
the ladder and scaling networks, power supply rejection,
and reference errors. I n summary, these errors consist of
initial errors including Gain, Offset, Linearity, Differential Linearity, and Power Supply Sensitivity. Initial
Offset or Bipolar zero errors may be adjusted to zero.
Gain drift over temperature rotates the line (Figure I)
about the bipolar zero point and Offset drift shifts the line
left or right over the operating temperature range. Most
of the Offset and .Gain drift with temperature or time is
due to the drift of the internal reference zener diode. The
converter is designed so that these drifts are in opposite
directions. This way the Bipolar Zero voltage is virtually
unaffected by variations in the reference voltage.

DIFFERENTIAL LINEARITY ERROR
Differential Linearity Error (OLE) is the deviation from
an ideal I LSB change from one adjacent output state to
the next. OLE is important in audio applications because
excessive OLE at Bipolar Zero (at the "major carry") can
result in audible crossover distortion for low level output
signals. Initial OLE on the PCM52/53 is factory-trimmed
to typically ±0.001% of FSR.
STABILITY WITH TIME AND TEMPERATURE
The parameters of a 01 A converter designed for audio
applications should be stable over a relatively wide
t.emperature range and over long periods oftime to avoid
undesirable periodic readjustment. The most important
parameters are Bipolar Zero Error, Differential Linearity
Error, and Total Harmonic Distortion. Most of the
Offset and Gain drift with temperature or time is due to
the drift of the internal reference zener diode. The
PCM52/53 is designed so that these drifts are in opposite
directions so that the Bipolar Zero voltage is virtually
unaffected by variations in the reference voltage. Both
OLE and THO are dependent upon the matching. and
tracking of resistor ratios and upon VHE and hH of the
current-source transistors. The PCM52/53 was designed
so that any absolute shift in these components has
virtually no effect on OLE or THO. The resistors are
made of identical links of ultra-stable nichrome thin-film.
The currerit density in these resistors is very low to further
enhance their stability.
POWER SUPPLY SENSITIVITY
Changes in the DC power supplies will affect accuracy.
The PCM52/53 power supply sensitivity is specified for
±0.001% of FSR/%Vcc for all supplies. Normally.
regulated power supplies with 1% or less ripple are
recommended for use with the DAC. See also Power
Supply Connections paragraph in the Installation and
Operating Instructions section.
SETTLING TIME

Settling time is the total time (including slew time) required for the output to settle within an error band around
its final value after a change in input (see Figure 7).

u

BIPOLAR ZERO ERROR

Initial bipolar zero error (Bit I "ON" and all other bits
"OFF") is the deviation from zero volts out and is
factory-trimmed to typically ± 10m Vat +25°C. This error
may be trimmed to zero by connecting the external trim
potentiometer shown in FigureS.

O.ooID.O\O.,
1.0
Sattllng TIm. (!'Iacl

FIGURE 7. Full Scale Range Settling Time vs Accuracy.

6-169

Settling times are specified to ±O.006%of'fSR; orie for a
large output voltageci:).angeof IOV and one for a I,",SB
change. The I LSBchange is measured at the major carry
(0111...11 to 1000 ... 00), the point at which the worst-case
settling time occurs.

ILSI

.1

•

I &NALOGOUTPUT .

Tf -+FULL SCALE •

... .
•

,

. .. .. .

ALL BITS
LOGIC I

INSTALLATION "AND
OPERATING INSTRUCTIONS

t

"
....
,- .... .

POWER SUPPLY CONNECTIONS
For optimum performance and noise rejection, power
supply decoupling capacitors should be added as shown
in the Connection Diagram': These capacitors (l/LF
tantalum or electrolytic recommended) should be located
close to (he PCM52/53.

DIGITAL INPUT·BIPOLAR
ZERO
(MSB ON AND
ALL OTHER BITS OFF)

RA/IGEOF
BIPOLAR ZERO
. ADJUST
,

.-

•

ALL BITS

t LOGIC 0

.

-FULL SCALE

BIP~AR ZERO ADJUST

TRANSLATES THE LINE

EXTERNAL BIPOLAR ZERO ADJUST (OPTIONAL)
In some applications the Bipolar Zero Error (offset) may
require adjustment. This error may be adjusted to zero by
installing an external potentiometer as shown in Figure 8.

~ . . l}i~p'

I

~H~_

-Vee

FIGURE 9. Effect of Bipolar Zero Adjustment on a
Bipolar D/ A Converter Transfer Function.
TABLE II. Digital Input and Analog Output
Relationship.
OUTPUT

IUkn
TO
.10000n

DIGITAL
INPUT CODE

BIPOLAR
ZERO
ADJUST

Volt_Model

Current Model

16-811
14-811
ReooluUon ·R.'oluUon

16-811
14-811
ReooluHon, ReooIullon

Complementary
Bipolar Offset
Binary (COB)
±10V (PCM53)
O.031pA
+1.22mV
+305pV
One LSB
O.122/AA
All Bits On
+9.99969V +9.99678V -O.99997mA -O.99968mA
00... 00
All Bits Off
-10.00000V -10.00000V -i.OOOOOmA +1.00000mA
11...11
±5V (PCM52)
One LSB
+152/AV
+61OpV
All Bits On
+4.999848V +4.99939V
00... 00
All Bits Off
11 ... 11
·-5.00000V -S.OOOOOV

-Vee
FIGURE 8. Optional External Bipolar Zero Adjust.
The potentiometer should have adequate resolution, at
least 10 turns for full-scale resistance.
The TCR of the potentiometer should be 100ppmj"C or
less. The 1.5MO resistor(20% carbon or better) should be
located close to the PCM52! 53 to prevent noise pickup.
Refer to Figure 9 for the relationship of Bipolar·Zero
adjust on the D/A converter transfer function.
ADJUSTMENT PROCEDURE
Apply the digital input code that should produce zero
volts output (bit I or MSB "ON and ail other bits
"OFF''). Adjust the bipolar zero potentiometer until zero
volts is obtained.
Table II shows the ideal plus and minus full scale voltages
and LSB'valuesfor both 14- and 16-bit resolution and
±IOV and ±5V output ranges.
H

J2
R3

SENSE OUTPUT
+Vec

INSTALLATION CONSIDERATIONS
If 14-bit resolution is desired, bit 15 (pin 15) and bit 16
(pin 16) should be .connected to Voo through a IkO
resistor to insure that these bits remain off.
Figure lO shows the connection diagram for a PCM52/
53-V. Figures II and.}2 show connection diagrams for
PCM53-I models.

I/'F

COM

I/'F

-Vec

±15VDC
SUPPLY

II. = litll(PCM52-V)
= IOkll(PCM53-V)

FIGURE 10_ Output Circuit for PCM52/ 53-V.

6-170

PCM53-1

RI~

The PCM52/53 is not normally sensitive to electrostatic
discharge (ESD). Figures II and 12 show connection
diagrams for PCM53-I models.

1000n (PCM&31

APPLICATIONS

+V,.....--...
TO PIN 23-":t+~-:--::--+--'~
-:-l,,-::F_ _+-,-CO.:.;M~ ±15VDC
TO PIN 19_+--I_I,,_F_ _-!-_....:V~

SUPPLY

FIGURE II. Preferred External Op Amp Configuration
Using PCM53-1.
Lead and contact resistances are represented' by R,
through R;. As long as the load resistance (Rd is
constant, R, simply introduces a gain error. R, is part of'
Rl. if the output voltage is sensed at Common (pin 20) and
therefore introduces no error. If RI. is variable, then R,
should be less than RLm;n/2'6 to reduce voltage drops due
to wiring to less than I LSB. RL should be located as close
. as possible to the PCM52! 53 for optimum performance.
The PCM52/53 and the wiring to its connectors should
be located to provide optimum isolation from sources of
RFI and EMI. The key word in elimination of RF
radiation or pickUp is loop area; therefore, signal leads·
.and their return conductors should be kept close together.
This reduces the external magnetic field along with any
radiation. Also, if a signal lead and its return cQnductor
are wired close together they present a small flux-capture
cross section for any external field. This reduces radiation
pickUp in the circuit.
Rf = IOkO. PCM53-1

IPAC
CURRENT
CONTROLLED

Hf

BY
DIGITAL
INPUT

Uto
~----------~COM

IpAc VARIES FROM -lmA 10 +lmA (TOLERANCE = ±30'lo1

The equivalent lU\fIut clrcaR far I currant_ut IllldelII Ihown aboVe.
V." " dlllrlllMtf by:
VOUT '" ±IIlA
fl2.4kn III000n x Hell
.
U2.4lcn III000n + It.lJ

FIGURE 12.Driving a Resistive Load With PCM53-1.

6-171

Figures 13 and 14 show a circuit diagram and timing
diagram of a single PCM52/53-V used to obtain both left
and right channel audio output in a typical digital audio
system. The Sony CX-7934 and associated LSI logic
contain all of the required circuitry for error detection,
correction, and formatting of the digital data obtained
from the Compact-Disc priorto sending this information
to the D/ A converter. The CX-7934 is used in a parallel
output mode where the left and right channel parallel data
are time-shared. Since the digital inputs of the PCM52/53
are TTL-compatible, they can be connected directly to
the parallel outputs oftheCX-7934. Only a single inverter
is required (Bit I) to convert the two's complement
output code of the CX-7934 to offset binary. The audio
output of the PCM52/53-V is alternately time-shared
between the left and right channels. The design isgreatJy
simplified because the PCM52/53-V is a complete D/ A
converter.
A sample/hold amplifier, or "deglitcher", is required at
the output of the D/ A converter for both the left and right
channel, as shown in Figure 15. The S/H amplifier for the
left channel is composed of Al, SW" and associated
circuitry. A, is used as an integrator to hold the <\nalog
voltage in C,. Since the source and drain of the. FET
switch operates a't a virtual ground when "C"and "B"are
closed in the sample mode, there is no increase in
distortion caused by the modulation effect of Ron by the
audio signal.
Figure 16 shows the deglitcher control signals for both
the left and right channels which are produced by the
timing control logic. A delay of2.5l'sec (tw) is provided
to .eliminate the glitch and allow the output of the
PCM52/53-V to settle within a small error band around
its final value before connecting it to the channel output.
Due to the fast settling time of the PCM52/53-V, it is
possible to minimize the· delay between the left channel
and right channel outputs when using a single D/ A
converter for both channelS. This is important because
the left and right channel data is recorded in phase and
use of a slower D/ A converter would result in significant
phase error at the higher audio frequencies.
A low-pass filter is required at the S/ H output to remove
all unwanted frequency components caused by the sampling frequency as well as the discrete nature of the D/ A
converter output. The filter must have a flat amplitude
response over the entire audio band (0 to 20kHz) and a
very-high attenuation above 20kHz. Most previous digital audio circuits used a high-order (9-13 pole) analog'
filter. However, the. phase response of an analog filter
with these amplitude characteristics is nonlinear and can
disturb the pulse-shapedcbaracteristics of the transients
contained in music.

IN
~
c.,:,
G-

2_2kn

2.21w

LEFT CHANNEl
OUTPUT TO LPF

>-........-

2.2110
R3

"....

,~~'

.

~LJ

CX-7934
(SONY)

2Ic x BR~M
"

2.2110

r- i:1
RIGHT CHANNEL
OUTPUT TO LPF

9

W2

MP7512
(MICRO POWER)

CX-7933
(SONY)

TIMING
CONTROL
LOGIC

LEFT CUANNEL
OEGLlTCltER
CONTROL
RIGHT CHANNEL
' - - - " " DEGLITCHER CONTROL

CX-7935
(SONy)

TO USE PCM53. ADD BUFFER
AMPL!FIERS SUCH AS Al AND A3
SHOWN IN FIGURE 15.

FIGURE 13. A Single PCM52/ 53 Used to Obtain Both Left and Right Channel Output in a Typical Digital Audio System.
SECOND-GENERATION SYSTEMS

One method of avoiding this problem and obtaining a
linear phase response is to use an oversampling digital
filter technique asshown in Figure 17. The Yamaha YM3511 and YM~2201 LSI chips provide all of the functions
described for the Sony chip set and, in addition, contain
an onboard digital oversalI!pling filter which effectively
.multiplies the sampling frequency py a factor of two and
sends the parallel data at a rate ofB8.2kHz to the 0/ A
converter. Since the offset binary parallel data is directly
available from the YM-2201, no external inverter is
required. Furthermore, since the deglitcher control signal
is also. available from the YM-2201, no external timing

RIGHT CHANNEL
OEGLITCHER CONTROL
A"LOW" SIGNAL ON THE OEGLITCHER
CONTROL CLOSES SWITCH "A" WHILE A
"HIGH" SIGNAL CLOSES SWITCH "B".

,,

I

LReK 1.1-:_ _ _-'

,,

DATd.........R::-::18=HT.---Xr--~LE;::;FT:---'\X

RIGHT

,

X . LEFT

l(

FIGURE IS. A Sample/ Hold Amplifier (Deglitcher) is
Required at the Digital-to-Analog Output
for Both Left and Right Channels.

UP••"';

control logic is required for most applications. The
timing diagram for this circuit is shown in Figure 18.

!

RIGHT CII4I111EL
DEGLITCHER I 25pHc' :-..a.3plIC...1
CONTROL I
.
-,I
LEFT CHANNEL -f'----'-'.
I
DEGLITCHER
CONTROL

I

'

r---L

FIGURE 14. Timing Diagram for the Digital Audio
.
System using PCM52/53 and Sony LSI
Logic.

6-172

This circuitreq.uir.es a very fast 0/ A converter since the
sampling frequency is multiplied by a factor of two or
more. This techriiqueresults in intermodulation products
being created, by mixing the sampling frequency and
componentS of the li.ildio frequency, that are far outside
the audioband of 0 to 20kHz. These unwanted frequencies

I
t+-•. _-

IIIT~ FOADAt

RI6MT

.x

.._-

44-1kHz -

,
--In~l.

,
-----t

IIIIIITClllIlELIIA"N.4. LEFTCK."LlIA'"

I
X_t_ELIAU'.j(LEfTcu-.U,TlI.IX

n

DI~~:~ ';---'---!j ~,_ _ _ _ _ _---l......----·1
CtJITROl

cHA::I

DEBLITCHER
CHTIIDl

:

~

1-"

: : In'-_____~---'~
I

- : : - DILAY BITWlIMlIFT AIID RIBIIT CIlAIIIIL

THI IIIBUTCHIR CDITRDL BIIMALJ ARE BIIEllAlID IY TME lIMIMI
CDITROL LDlIC. TIll FAIT SEmIM. TIMI OF TIlE PCMR/A uKESIT
POIIIII.E TO MlIiMllE THE DELAY BITWEEM LIFT AMI RIBIIT CIIA_LS
TO ABOUT U ..... WIIICH RIDUCIS PllAII I_R AT TIll HIIMII AIIIID
FRIQUlIICIEt

FIGURE 16. Timing Diagram for the Deglitcher Control
Signals.
are easily removed by a low-order linear-phase analog
filter following the deglitcher circuit since a sharp
amplitude response is not required. A singlePCM52f53-V
can be used for both the left and right channel lIS long as
the oversampling rate of the digital filter is two. An
oversampling rate of four can be used if a separate
PCM52f 53 is used for each channel. This would reduce
the complexities of the analog filter required even further
(at the expense of an additional Df A converter).
Another factor to consider when choosing a Df A
converter for digital audio applications is that the
linearity of the total harmonic distortion versus output
signal should be good since a change in the background

noise level can be audible. The design of the PCM52/53
ensures that the hneanty of the total harmonic distortion
versus output signal level is very good over the full range
of amplitude and frequencies. Also, no special grounding
or shielding techniques 'are required to obtain good
.. signal-to-noise ratio with the PCM52/53. Some converters require a high frequency clock which can couple to
the analog output of the D/ A converter through the
output wiring and ground circuitry.
The PCM52 and PCM53 Df A converters provide a
complete solution to one of the most critical portions of a
digital audio system. Since the sound of the system can be
affected by the D/ A converter more than any other single
component, the selection of which converter to use'
should be made with care.
,

I

1---Il2IIIIz-----j
X UfTCIAIIEI. ..,U

DATAFOIDICl.. .uTaIAIIElllt.1U

=,..: :...=..: ..: ,::-.:\'"Xr:u~".....
=::::.::::,,::::.·-:\,X./

'J..!-b...

IDATUELlCTDI I

COIfT.:lr.. ..t--"~
CHAlIEL '

'--_ _ _ _....

DH~:I
r'"A
CHAlIEL.71---~:-'

IL

'--_ _ _ _ _

DESUTCllER
COITlIOl

... =fll_
I.

=2.78pa.c

FIGURE 18. Timing Diagram for Digital Oversampling
Technique when using Yamaha LSI.

2.2111l

2.21U1

LEFT CHANNEL
OUTPUT TO
LINEAR PHASE
ANALOG
LOW·PASS
FILTER

Ukl!

TO USE PCM53. ADO BUFFER
AMPLlFIfRS SUCH AS Al AND
SHOWN IN FIGURE 15.

FIGURE 17. Oversampling Digital-Filter Technique Using Yamaha LSI.

6-173

RIGHT CHANNEL
OUTPUT TO
LINEAR PHASE
ANALOG
LOW·PASS
FILTER

Aa

BURR-BROWN@

4804

IElElI

Low Cost
12-81T POWER CAC
FEATURES
• DlGITALLV PROGRAMMABLEyOLTAGE SOURCE
±30VDC. 1AConlinuous Output
• RESISTOR·PROGRAMMED VOLTAGE RANGE AND
CURRENT LIMIT
• LOW COST
• INPUT STORAGE REGISTER
• ,±.lI2LSB MAXIMUM NONLINEARITY

DESCRIPTION
The 4804 Power DAC offers versatility and low cost
in automatic test equipment and prOCess control
applications. The output range is ±30VDC at IA
with built in current limiting at ±1.2A. By adding one
external resistor, you can select any full scale OUtput
range less than ±30VDC and still maintain 12·bit
resolution, Also, the current limiting can be varied by
changing the value of twO, easily accessible resistors.
The package was designed for mounting on a PC
card and can dissipate up to 20W internally in free air
with no external heat sinking required.

/

Intern"IGIIII AlrparllndUllrlal Part· P.O. 8ox.114OO· TUCIan. Arlzana 85734· Tel. (1i02J 74&-1111 • Twx: 9111-1152·1111 • Cable: 88RCORp· Tatex: ~I

6-174

DETAILED DESCRIPTION
GENERAL

To reduce gain and offset errors below the specified values,
OFFSET ADJUST and GAIN ADJUST trim points are provided.
Follow the procedure shown on page 6-178.

The 4804 consists of al2-bit storage register with strobed
inputs, a 12-bit digital-to-analog converter, and a power
output stage. By changing the input code according to Table
I, the output voltage may be varied between ±30V with output currents up to 2A continuous. The maximum internal
power dissipation for various output conditions is described
in Figure 3 and 5. Care must be taken not to exceed the
power dissipation limits for "the thermal environments described in the figures.

POWER AMPLIFIER
The power amp stage buffers the D/ A converter signal and
provides the power output capability. Connecting the ±30V
RANGE pin to the output will preset the full scale range to
±30V, giving the transfer function described in Table I; Le.
I LSB = 14.65mV. RF and RS were selected for optimum
temperature stability to minimize gain drift errors, and the offset of the Power Amplifier has been nulled at the factory. By
connecting a resistor between the Vour RANGE ADJUST pin
and the output, a variety of full scale ranges can be selected
while maintaining 12-bit resolution.

No external adjustments or components are required to
achieve the specified accuracy. If improved performance is
required, two adjustments will null the offset and gain errors.
The procedures for adjusting these parameters are described
on page 6-178.
To minimize noise levels in the 4804 the analog and digital
signal returns are not internally connected. For proper operation, these two grounds must be· externally connected
together.

For optimum stability, the external resistor should have a T.C.
which is less than ±IOppm/°C. The ±35V inputs to the power
amplifier may be reduced if full scale ranges less than ±30V are
desired. To maintain the best accuracy, these supplies should ca
not be reduced below ±15V. Since the 4804 output current is ~
derived from the ±35V power inputs, the current-carrying capability of these power supply connecting leads should be
considered.

g

STORAGE REGISTER
The storage register consists of 12 integrated-circuit, positiveedge-triggered flip-flops utilizing TTL circuitry. The logic
levels at the register inputs are transferred to the D/ A converter on the positive-going edge of the strobe pulse. Strobing
, occurs at a particular voltage level and is not directly related
to the transition time of the positive-going pulse. When the
strobe input is at either the high or low level, the inputs to
the register have no effect on the D/ A converter inputs. The.
strobe and register are fully compatible with most TTL or
DTL circuits.

Rp and RM determine the output positive and negative current limits, respectively," of the output. They have been
preselected for current limiting of ± 1.2A, typo The current
limiting can be changed by replacing Rp and RM with other
values according to the following formula:
1.2V
R=---Icurrent limit

DIGITAL-TO-ANALOG CONVERTER

It is not necessary that Rp and RM be the same value. Since the

The D/ A converter stage accepts the digital output from the
storage register and converts it into a bjpolar analog signal
according to Table I.

output current of the 4804 flows through these resistors, the
power dissipation of Rp and RM should be considered. Both
resistors are stud mounted for easy accessibility.

Gain

~~~j.-

-- ....,
I

30k

9T

±30V RANGE

RF
BIT

1

2
3 "-,,....,.---,

4
5
6
7

'-""","--OW



RS

z

V OUT RANGE ADJ.

V OUT

0
0

: )H;-!JC=:::J
10 <:Il!:8>---I
LSB

lOT

w

«

0

""isr--L__....I
"II'"

STROBE <:!..!1.!!>----.....

L---4+-

__

@-_-®-_-®-~

SB,ST

NO Connecti on

-15VDC +15VDC

FIGURE I. Block Diagram

6-175

___

lS,lT

-35VDC

3B;3T

+35VDC

I

J

,S~ECIFICAJIONS
,
!;
.':,', . . ,: ' '. :. ",:; .
,1

~ . ,_

.~.

Typical at 25°C. rated power supplies, and V out range:::: f30

.....--...;.......;;.----...;...-------------...;...-.

unless otherwise noted.

MECHANICAL

ELECTRICAL

..

INPUT
Kesolutlon

Logic levels

(TTL/CMO~

12 bits
Compatible)
±2V < ein < +5.5V @';;+O.lmA
OV < ein < +0.8V @';;-0',36mA

Logical HI"
Logical "0"
Dig.i~al ~nput

offset binary (see Table I.)

Coding

TRANSFER CHARACTERISTICS
TOTAL ACCURACY
V out Ra~ge :;:: ±30V

53mm

Drift (OoC to +70°C)

6.038"j
max

±50ppm/o Cmax
"OIlV /oC max
±2ppm/oC

Gain

Output Offset Voltage
Differential Linearity

.~~!"'::~.-e-

T

(5.7''')
max'

±Y1LSB max,
±Y,LSB max
±3mV"inax

Output Offset Voltage

C1~
145mm

±O.OS% of reading

Individual Error Contributors
Linearity Error' (OoC tQ +70o C)
Differential Linearity Error

..

10185mm
(4·.010").max

~
a: a:

97.2mm
( 3..83",


';;

.=0~
-30~--~--~--~---+--~--~

OC:~~~~~~~~

-3S~--~0--~2~5--~S~0--~7~5~~10~0~~

±l 0

Time U.s)

±20
t30
±40
Output Voltage (Volts)

FIGURE 5. Output Amplifier Power
Dissipation vs. Output Voltage.

FIGURE 4. Pulse Response.

DIGITAL INPUT CODES VS. VOUT'.

INPUT CODE
LSB
MSB

NOMINAL OUTPUT VOLTAGE

±lOV RANGE

VARIABLE RANGE

I

Illl lllli III

+30.000V

+io.oooro V
10k

1111 Illl IllO

+29.98SV

+9.995(RO ) V
10k

1000 00000 000

+i4.6SmV

+4.8S( RO) mV
10k

o Illllllllil

O.OOOV

O.OOOV

o IUIlIlll 10

-14.6SmV

-4.88( RO ) mV
10k

000000000000 I

-29.97IV

-9.990(

~O~)

V

000000000000

-29.98SV

-9.995(:~kl

V

TABLE I.

6-177

OFFSET AND GAIN ADJUSTMENT
, The offset and gain of the D/A converter stage may be trimmed using externally connected
OFFSET ADJUST and GAIN ADJUST potentiometers. The adjustment procedure is ,outlined below. Since the GAIN ADJUST is connected to a high impedance point in the D/ A
converter, a ceramiC capacitor connected between this point and analog common is recommencled to minimize noise pickup. The offset error should always be nulled before adjusting
the gain error potentiometer.

OFFSET ADJUST PROCEDURE

GAIN ADJUST PROCEDURE

Apply the digital code which could give the maximum positive voltage output and adjust the OFFSET ADJUST potentiometer for the proper output voltage~ For example,.if the
4804 is connected for Ii full scale range of ±30V, apply all
ones to the input and adjust the potentiometer for an output of+30.00OV.

Apply the digital code which should give the maximum negative voltage output, and adjust the GAIN ADJUST potentiometer for the proper output voltage. For example, if the
4804 is connected for a full scale range of ±30V, apply all
zeros and adjust the potentiometer for an output of
-29.985V.

liT
Pin

i

1-'-----.""
jiI\

.OO1jLF

Analog

"'1"' .OI!~

Common

Range

Adjust
Translates tlie
Line Vertically)

-15V

ApJU$T

Input
HI-+-+-.g....+-I.,.+>~~+-I~H-+-+-I Input
AliI's"
"
.... All 0'8

~~nB o--,--------tJ ,:~::DC

!

+ Full Scale Output

(Offset

• lOOk

GAIN

,6

Offset--X
Anj.

+15V

MSB= 0

All others = 1

-15VDC

"'''t.

~f:>J

'~~b

-Full Scale _
'\
Adj.
L...._O_u..;tP:..u_t==-:';=,.-r-_ _ _'~ Range
(Gain Adjust
Rotates the
Line about x

t

OFFSET ADJUST

FIGURE 6.

FIGURE 7.

DISCUSSION OF SPECIFICATIONS
DIGITAL INPUT CODES
The 4804 accepts TTL and CMOS compatible input codes',
in binary format. Table I shows the output voltage for
selected iiIputs.
'

ACCURACY
Total Accuracy is the maximum deviation from the ideal
output over the full output range. It is tested at 25 0 C and
represents the maximum allowed value of the sum of the
individual errors. The total accuracy is specified as a maximum with the 4804 in the ±30V range configuration. If
an output range less than ±30V is selected, the accuracy
will improve as the power amplifier gain is reduced.

6a78

Lineary Error for the 4804 is specified as a maximum over
the temperature range of OOC to +700 C. This means that
the analog output will not vary by more than ±~ LSB
maximum from an ideal straight line drawn between the
"all bits ON" and "all bits OFF" end points.
Differential Linearity is the deviation from an ideal 1 LSB
voltage change from one adjacent output state to the next.
A differential linearity error spec of ±~ LSB means that
the output voltage step sizes can be anywhere from ~ LSB
to 3/2 LSB when the input changes from one adjacent
input state to theriextMonotonicity over OOC to +700 C is gu~anteed in the
4804. This insures that the analog output will increase or ,
remain the same for increasing input digital codes.-

The maximum change in OFFSET is referenced to the OFFSET at 25 0 C divided by the temperature range. This drift is
expressed in parts per million of full scale ranges per °c (ppm
of FSR/°C).

DRIFT
Gain Drift is measure of the change in the full scale range
analog output over temperature. The GAIN DRIFT is determined by testing the end point differences at OOC, +2S oC
and +700 C, calculating the GAIN ERROR with respect to
the 25°C value, and dividing by the temperature change.
This specification is expressed in ppm/°C.

POWER SUPPL Y SENSITIVITY
Power Supply Sensitivity is a measure of the effect of a
power supply voltage variation on the 4804 output. It is
defined as a change in output voltage per change in supply
voltage with the ±30Voutput range. Power supply rejection
is improved if a full scale range less than ±30V is selected.

qffset Drift is a measure of the actual change i.n the output
with all bits OFF (all O's) over the specified temperature
range, and is measured at OOC, +2S oC and +700 C.

OPERATING INSTRUCTIONS
REMOTE SENSING
In applications requiring that the load be located some distance from the Power DAC, the line resistance from the 4804
to the load can cause significant error, especially during operation at high currents. To minimize this problem, connect
the circuit with the line resistance inside the feedback lool!
of the output amplifier, as shown in Figure 8. This ·technique effectively divides the line resistance by the open loop
gain of the output amplifier (94 dB min, with RLOAD S.Q).
To minimize noise pickup, the external feedback resistor
should be located as close as possible to the 4804.

load voltage will be reduced by approximately I LOAD x
RUNE. Proper grounding of the 4804, load, and digital
stimulus will also reduce errors caused by ground loops.

THERMAL CONSIDERATIONS
The absolute maximum internal power dissipation of the
output amplifier is 20 watts in free air at 2S oC. Derate by
O.2W/oC above 2S oC. Thermal resistance from amplifier
junction to ambient is 6 0 C/waU. Figure 5 shows internal
power dissipation as a function of otuput voltage and load
resistance with ±3SV supply voltages.

Since the amplifier must still overcome. the voltage drop in
the line inside the feedback loop, the dynamic range of the
V out Range
Adjust

External Feedback Resistor

Digital

Stimulus

Ra
RUne

>---~'N"""------i V 10ad =
"out

Com.

~

--'~;;::::~l ~
Pin

Digital

L - - -_ _poo---

Power Supply

FIGURE 8. Grounding Scheme With Remote Sensing

6-179

V out - i load x R Line

6-180

SAMPLE/HOLD AMPLIFIERS

II
For any application requiring use of a sample/hold amplifier, consider
the variety of products listed in the Selection Guide in this section. The
products range from SHC298, a low cost solution for your mediumspeed 12-bit system, to SHC803 and SHC804, high speed sample/
holds optimized for your high bandwidth requirements.
If your. needs include high performance and small size over either
industrial or military temperature ranges, turn to SHC80 and SHC85.
These popular products are fully self-contained, including holding
capacitor.
Use of a carefullY selected sample/hold can increase the sampling
bandwidth of an analog-to-digital converter by up to four orders of
magnitude, while insuring that an accurate value of the signal is captured at a specific point in time. In many applications not viewed as
requiring high bandwidth data acquisition, optimum performance and
cost may still be achieved by use of combinations of very high speed
multiplexers, sample/holds, and AID converters.
Sample/hold amplifiers-another part ofthe complete data acquisition
solution.

7-1

'SELECTION.,GUIBE.'
SAMPLE/HOLD CIRCUITS

,

.

'

Proven technologies applied' to these Circuits achieve,' '
very high speed and accuracy for demlUlding applications. SHC298AM is a low post nion<;>litilic.Designed JO

be perfonnance compatible to Burr-Brown AI D and
D I A conyerters, the application of all of these S I H cirCU:it~ is quick and ellSy.

"

.

SAMPLEtHOLD CIRCUITS.
Gain/Offs.t

Charge

,

Droop "
Rate'
(mV/maec),:,

,

Acquisition

TeiJI"""
, (ppm!>1

, Error

0fIs8t

(%)(mV)

(mV)

SHC80KP

±a.Ol, :t2 max

:t2 max

0'.5 inax

3

. 10, mali '

DIP

7-3

High Speed,
Complete

SHC85, (0)
SHC85ET, (0)

±a.01, ±2inax
±0.01, ±2 max

±2max

0.5 max
0.5 max

3

±2max

4.5 max
,4.5 max

DIP'"
I)IP'"

7-7
7-7

LowCo.t,
Monolithic

SHC298AM

±a.Ol, ±7 max

±2Smax

10max~

TQ-ggl3I

7-11

Very-High
Speed

SHM60

Module

7-23

Ultra-High
Speed

SHC603BM
SHC603CM
SHC804BM
SHC604CM

DIP
DIP
DIP
DIP

7-17
7-17
7-17
7-17

Description

Modelli1

Low Coat,
Complet.

. Time:.
, (paso)'"

2OVI~P)

3

4
';

.j"

±0.01, ±l.S

±l.S

S

2

±O.l,±5max
±O.1.±3."ax
±a.l.:t5 max
±0.1, :t3 max

±10max
±Smax
:tl0max
:tSmax

±5max
±Smax
:tS max
:t5max

±lO'max '
±S'max
.±lo'max,
±Smax

,.

10 mali
1 max

3OOriseCm.x ,
.,3OOnaeC max

309nMC~ax
300niec max"

Package

,',

Page

NOTES: (1) "(0)" Indicates product also availabl. with SCneening lor Increased reliability. See 0 Progrem .• , (2) lOY step to 0.01% ollinal value.
(3) Hermetic. (4) With l000pF external holding' capacitor.

BURR-BROWN

1E3E31

SHeBO

®

Fast Ie
SAMPLE/HOLD AMPLIFIERS
FEATURES
• 14-PIN DIP PACKAGE
• 10)lsec ACQUISITION TIME
• COMPLETE WITH HOLDING CAPACITOR
• :to.01 % ACCURACY
• -25°C TO +85°C TEMPERATURE RANGE (SHC80BM)

DESCRIPTION
Ultra-linear performance and fast acquisition speeds
- that's the combination that makes the SHC80
models ideal for your demanding data acquisition
and ·control applications.

t¥ht
OI!!!!d/. +15VDC N/C

The SHC80 acquires and holds up to ±IOY analog
signals to an accuracy of ±O.O I(·i of full scale.
Acquisition time is 12!-,sec for a 20Y step or IO!-,sec
for a lOY step. High performance results from the use
of internally compensated circuits normally found
only in larger. more expensive sample holds.
Two models give you a choice of operating
temperature range: the SHC80KP (O"C 10 -t70"C) in
an epoxy package. also the SHC80BM (-25T to
+85"C) in a hermeiic metal case. These units are well·
suited for:
+In

·15VDC

Mlda
An.
Centrol Com.

N/C

Data Acquisition Systems
Data Distribution Systems
Analog Delay Circuits
Puls.e Amplitude Modulation Circuits
Waveform Amplitude Measurement

C Ou\jlul
Ex\.

InllmlilOftal Airport Induatrlall'lrk· P.O. Box 11400· Tucson. Arimna 85734· Tal. 1602) 746-1111· Twx: 916-952·1111 . Cable: BBRCORP· Talex: 88-6491

7-3

SPECIFICATIONS
., MECHANICAL,

ELECTRICAL
, Typle81 at 25°C with

rat~d supply and

l000pF Internal capacitor unless otherwise noted.

I

MODI!LS

SHCIOKP

INPUT

I

SHCIOBM

I

,-.EPOXY,PACKAG.E -

r l""

UNITS

,"

A

ANALOG INPUT
Voltage Range
Maximum Safe Input Signal
Impedance
Bias Currant
DIGITAL INPUT
ITTL/MOS Compatible I
Mode Control
':Sample" - Logic "1"
"Hold" - Logic "0"

±10
:t15'
lOS 11-5'
400

±10
±15
lOB II 5
400

Logic Supply
Voltege+5V

Logic Supply
Voltage +15V

2 throughput nonlinearity. droop.
thermal transients and feedthrough; in short. all errors
that cannot be adjusted to zero for a IOV input change
after a lOll sec acquisition time and a I msec hold time.
Offset errors may be adjusted to zero by the offset
control. but gain errors 'must be removed by a gain
adjustment elsewhere in the system. (Gain adjust not
included in SHC80.)

:

Sample-ta-Hold Switching

I

Transient & Charge Offset

i -I~

\\
,

'FeedthrOUgh
.
, (Change in solid line 1

AcquisitiOn

.... ..-..- ...",.....

\

Time

FIGURE I. Example of Specifications.

t~1

GAIN ACCURACY
The difference due to amplifier gain errors between Input
and Output voltage when in the "sample" mode.

;'~r

a-

DROOP RATE
The voltage decay at the output during the "hold" mode
due to storage capacitor. FET switch leakage currents.
'
and output amplifier bias current.

I I T4J
4

6
8
10
Typi cal Acq uisition Ti me
10V Steps (plOel

12

FIGU RE 2. Acquisition Time. vs Full Scale Range Error.

OPERATING INSTRUCTIONS
FEEDTHROUGH
The amount I>f input vl>ltage change that appears at the
output when the amplifier is in the "hold" mode ..

OPTIONAL EXTERNAL CAPACITOR SELECTION
The value of the external capacitor determines the droop.
charge offset. and acquisition time of the sample/ hold;
Both droop and charge offset will vary linearly with
capacitance from the values given in the specification
table.
Figure 3 shows the behavior of acquisition time with
added external capacitance. The behavior of droop with
external C is determined by:

THROUGHPUT - NONLINEARITY
The total charge offset and gain nonlinearity. i.e .. the
inaccuracy due to these two errors that cannot be
corrected by gain and offset adjustments. Throughput nonlinearity is specified over the 20V input range.

7-5

gain circuitry in data acquisitiori'systems. When it is
'combined with Burr-Brown's 16"cnannel M PC-16S
Analog Multiplexer and ADC80 AI D Converter, you
have a compllet 16-enannel data acquisition system with
25kHzihroilghput· sampling, rates apd ±0.02% (RSS)
accuracy. ,

dv I
0.5 X 10'-9 \
.mY
Droop =d't"1000pF-i- C,:,pF) msec
Capacitors with high insulation resistance 'arid low
dielectric absorption •. such as teflon or polystyrene
should be used as storage elements (polystyrene should
not be used above,+85"C). Care should be taken in the
printed cireuit layout to minimize leakage currents from
the capacitor to minimize droop errors.

SIMULTANEOUS SAMPLE/HOLD
Time correlation of, sampled data signals' may be
implemented by using OM samplel hold for each analog
signal 'prlor to input to an analog multiplexer. The
SHC80's low aperture time of40nsec, practically

OFFSET ADJUSTMENT
Connect a 2kH to 5k!l multiturn potentiometer with a
max TCR or 150ppm'''C as shown. in the Connection
Diagram. and adjust the offset with the input grounded.
During the adjustment. the samplel hold should be
switching continuously between the "sample" and the
"hold" mode. Adjust the error to zero when the unh is in
the "hold" mode. This procedure insures that charge
offset as well as amplifier offset error will be removed.
160

u

so

~

40

.

r--- JOV 'Input
Stop,

S

E

j:

20

~

c
0

.~

:i!,
8'
«

10

eliminates channel-to:-channe.l tj~iie sl~w. The throughput

sampling rate lind the number of data chanels will
determine the maximum "hold" time and 'hence, the
worst-case droop error of the sample/ hold in the la~t
channel to be sampled prior to the next ~refresh" or
samplej hold command. This droop error may be
minimized by adding external capacitance to the SHC80
as shown in Figure 3.
The droop error is computed by:
Max Droop. Error (Channel' N) = (T x n)(Droop rate)

/. V

/.V
~ ~ 10V Input Step
~

Where T = II System Sample Rate and
n = number of multiplexer data channels.
Example:
For a IO-bit. 32-chann~lsyStem with throughput sample
rate of 25kHz, assuming no el!(ternal capacitance. the
droop error of channel N is:
Droop Error (E,,) = (I I 25kH)32 x (500 x 10-.1) = 640IlV.
For ±IOV input signal range and IO-bit resolution. the
resolution of ±I /2LSB is ±9.77mV. This droop error is
less than 0.032LSB (negligible). and no external C is
needed to reduce the droop of the SHC80.

5

, ..
0.000

O.OOB

0.002

0.032

0.12S

External Capacitor (",F)

FIGURE 3. ,Acquisition Time vs External Capacitor.
LOGIC THRESHOLD PROGRAMMING
Pin to is.,normally connected to the logic return and pin 9
to a' positive logic supply. The logic threshold is
determined by the4,3k!l and 10kH resistors shown in the
connection diagram. The threshold is 1.5V for logIC
operated on a' +5V supp,ly and 4.5V for'a '+15V logic
supply. If it is not convenient to connect a logic return
and supply to the S H C80. pin 10 may be connected to the
analog return and pin9 to+15V for 15V logic orto+15V.
throllgh a 27kH resistor for 5V logic. Thelnode contr,ol
switching transistors have sufficie'nt current gain to allow
the mode control pin to be driven from MOS logic. l)e
mode control polarity may be reversed by connecting an
extermilly-derived threshold voltage to pin 3 and by
copnecting pins 9 and 10 to the mode control source.

Clock
ADCSO

AID
Converter

-Par~Hel

Digital Date

Programmer
"Logic

APPLICATIONS

Channel Address

DATA ACQUISInON SYSTEM
The SHC'80 'i"hakesan excellent device for reducing
aperture time arid eliminating conversion noise from high

or
Computer 1/0

ANALOG DATA ACQUISITION SYSTEM

7-6

Serial
D ....

BURR-BROWN®

SHC85
SHC85ET

IElElI

Fast Ie
SAMPLE/HOLD AMPLIFIERS
FEATURES
• 14-PIN DIP PACKAGE
• 5pS8C ACQUISITION TIME
• COMPLETE WITH HOLDING CAPACITOR
• ±0.01% ACCURACY
• -55°C TO +125°C TEMPERATURE RANGE (SHCB5ET)

DESCRIPTION

.

The SHC85 is designed to acquire and hold up to
±IOVDC analog signals to an accuracy of±o.OI% of
full scale range in 5psec for a ,20 -volt step. or
4.5/Lsec for a IOVDC step. Featuring internally
compensated circuits normally found only in more
expensive and larger samplej holds, the SHC85
offers ultra-liner performance and fast acquisition
speeds for the most demanding data acquisition and
control applications.
Two models are available: the SHC85 is specified for
O°C to 70°C operation, and the SHC85ET is specified
for -55°C to +125"C operation.
The SHC85jSHC85ET are well suited for use in:
Data Acquisition Systems
Data Distribution Systems
Analog Delay Circuits
Pulse Amplitude Modulation Circuits
Waveform Amplitude Measurement

1- - - - - '+15VOC

:I

~
, Ollset I
I Adjust I

~

I
I

N/C

N/C

N/C

N/C

_J) __O ___O_O _ 0_.,
I
I
I

I
I

I
I
I

--6- J
Analog
In

·15VOC

Modi
Control

Analog
Common

N/C

Ext C

Output

International Airport Industrial Park· P,O. Box 11400· Tucson. Arizona B5734 . Tel. (6021 746·1111 • Twx: 91lJ.952·1111 . Cable: BBRCORp· Telex: 66·6491

7-7

SPECIFICATIONS
Typical

~t~50C wi~hrated supplY-and a

lOOOpF Internal capacitor unless otherwise noted

rlQ
L

MECHANICAL

ELECTRICAL
MODELS

I

SHC85

I

I

SCHISET

r-A=J

UNITS

INPUT
ANALOG INPUT
Voltage Range
Maximum Safe Input Signal

±IO
±15

Resistance

lOS

Bias Current

50

±IO
±15
108
50

Voltage
+2.0V < e <+8V
.OV '

-5

o. 8

o. 6

; o.4

>0

o. 2

'"

0

::§

-0. 2

::l
C

I

Sample Mode

"

r--...

z-o. 4

>-0.
. 1000

i"".

6

I

-15

-10

I. 8
6

§

I.4

-5

10

15

.

-

............

"

...

~

o. 8

........ .....
l; ••'S
~

o

'0.6 -

f- TI = - 2 1 '

$"

-0. 8

100

0;

b
i""'o..

2

.. "~
o

r......

lOOk

10k

CHARGE OFFSET

:e

T, -25"c1
RL - 10k!!

lk

F requency (Hz)

GAIN ERROR
I

'"

100

Hold Capacitor (}.tF)

DYNAMIC SAMPLING ERROR

10

10

IIIII

I. 2
I

~ o.4

e'" o. 2
0

-15

I
I
-10

-5

T J "=+1S50C

""'....... .
........

I
0

5

10

Input Voltage (V)

Input Slew Rate (V/msec)

7-13

15

POWER SUPPLY REJECTION

=-

lJ

160r:;TTI1mrTT'rmnr-TT1Tm.-.,.,.TTTmI
T, = zsoc.
140 V+:~ ~~:~ IsvttffflHfflilHf-+Httfffl

:;- 120 I
';:i

j9~~,7110Vttttttflt-+HttHII-t+ftttlll

lOO"~;;;ffI'tHllIIllIdI+ttItlll-+++tHlH+Hll!lI

~== ~O~
Negative
:§

60

Supply

Positive

5

......

0

40

~

~.119

TJ=:!SU('

:*",ootl~~t,;~I~~~d

I '1'0.

~ ·90

.s,

8

,-8Q .

-;9 .70t+t11t+-ffit+tffi-l'-ttttttttt+tft-l

S

~

:!Q

M
.,30.",rr-rTTn'........",..,....,..,ITV'"'"."'"="'y....="',"SV

:;:'.120Hilt+Htt-ttl-tt++HtviN= 10V p.p
c:
Hold Mode

0

<.>

;f

=-

S

0

S

~uppIY

FEEDTHROUGH REJECTION
. (HOLD MODE)

INPUT BIAS CURRENT

"" . -6ot+t1It+-ffit+tffi-l'-tttt+tttt+ttIH
~

·1 0

[J.,

0
100

Ik

10k

·1 S
lOOk

!M

Frequency (Hz)

~

~

0

~

~

~

1m

!~

.SOL,LIIL,I,J.J~,JJ-LL+.-u..u,l""OkJ..LII"i,o-"lOkJJY.r~'1

!~

. Junction Temperature ("C)

Frequency (Hz)

DISCUSSION OF SPECIFICATIONS
THROUGHPUT NONLINEARITY

CHARGE OFFSET
Charge Offset is the offset that results from the charge
coupled through the gate capacitance of the switching
FET. This charge is coupled into the storage capacitor
when the FET is switched to the "hold" mode.

Throug~put

nonlinearity is defined as total Hold mode.
nonadjustable. input to output error caused by charge
offset. gain nonlinearity. I msec of droop. feedthrough.
and" thermal transients. It is the inaccuracy due to these
errors which carinot be corrected by offset and gain
adjustments. Throughput nonlinearity is tested with a
IOOOpF holding capacitor. 10V input changes. 10j.lsec
acquisition time. and I msec Hold lime (see Figure I).

CONTROL
SIGNAL

GAIN ACCURACY
Gain Accuracy is the difference between Input and
Output voltage (when in the Sample mode) due to
amplifier gain errors.

SAMPLE
I

. . . . l - - - - - - -.....-----....lL_.TIME
INPUT
VOLTAGE

DROOP RATE
Droop Rate is the voltage decay at the output when in the
Hold mode due to storage capacitor. FET switCh leakage
currents. and output amplifier bias current.
FEEDTHROUGH
Feedthroughis the amount of the input voltage change
that appears at the output when the amplifier is in ·the
Hold mode.

OUTPUT
VOLTAGE

APERTURE TIME
Aperture Time is the time required to switch from
Sample to Hold. The time is measured from the 50%
point of. the mode contro1.transition to the time at which
the output stops tracking the input.
.
ACQUISITION T.IME
Acquisition Time is the time required for the sample/ hold
output to settle within a given error band of its final value
when the mode control is switched from Hold to Sample.
FIGURE I. Sample/Hold-Errors.

7-14

OPERATING INSTRUCTIONS
PAM Output

EXTERNAL CAPACITOR SELECTION
Capacitors with high insulation resistance and low
dielectric absorption. such as teflon. polystyrene or
polypropylene units. should be used as storage elements
(polystyrene should not be used above +85"C). Care
should be taken in the printed circuit layout to minimize
AC and DC leakage currents from the capacitor to
reduce chage offset and droop errors.
The value of the external capacitor determines the droop.
charge offset and acquisition time of the Sample/ Hold.
Both droop and charge offse,t will vary linearly with
capacitance from the values given in the specification
table for a O.OOlj.lF capacitor. With a capacitor ofO.Olj.lF
the droop will reduce to approximately 2.5j.1V /msec and
the charge offset to approximately 1.5m V. The behavior
of acquisition time with changes in external capacitance
is shown in Typical Performance Curves.
OFFSET ADJUSTMENT
The offset should be adjusted with the input grounded.
During the adjustment. the sample/hold should be
switching continuously between the Sample and the Hold
mode. The error should then be adjusted to zero when the
unit is in the Hold mode. In this way. charge offset as well
as amplifier offset will be adjusted. When a O.OOlj.lF
capacitor is used. it will not be possible to adjust the full
offset error at the sample/ hold. It should be adjusted
elsewhere in the system.

,Analog Input /

_ -,

\ __ ..,/ ~i
~j "
n

n. . __---'

Mode Control Hold--.I1L-_ _..J L _ _ _..J

FIGURE 3. PAM Output.
DATA DISTRIBUTION
The SHC298AM may be used to hold the output of a
digital-to-analog converter whose digital inputs are
multiplexed (see Figure 4).
TEST SYSTEMS
The SHC298AM is also well suited for use in test systems
to acquire and hold data transients for human operators
or for other parts of the test system such as comparators.
digital voltmeters. etc.

Stonte
Capacitor

Analot
Outpu.

P---t-

Channell

O.lpF

~

APPLICATIONS
DATA ACQUISITION
The SHC298AM may be used to hold data for
conversion with an analog-to-digital converter or used to
provide Pulse Amplitude Modulation (PAM) data
output (see Figures 2 and 3).

Diaital
Inputs
Chan ..12

-ISVDC
toAjD

Analog
Inputs

Converter

r---,

PAM Output
Analog

Multiplexer

CbaaneI N

Ol~
Diaital

+ISVDC

Input.

FIGURE 2. Data Acquisition.

'FIGURE 4. Data Distribution.

7-15

Witli it 0 .• IlF storage capacitor: the output may be'held
10sec with less than 0.1% error. With a I~F storage
capacitor. the output may beheld more than 15 minutes
with less, than IW error.

be conn!;l::ted to the'sample/ hold i~put$: The~ettl.itlg tilne
of the multiplexer. instrumentation amplifier. and sample/
hold can be eliminated from the channel conversio,n time
'
as before.

CAPACITIVE LOADING
SHC298 is sensitive to capacitive loading on the output
and may oscillate. When driving long lines. a buffer
'should be used.
Digital
. -_ _.,OJ.1IPut

HIGH SPEED DATA ACQUISITION
The minimum sample time for one channel in a data
acquisitiori system is usually cc"nsidered .to be the acquisition time ofthe sample/ hold plus the conversion time of
the analog-to-digital converter. If two or more sample;
holds are used with a high speed multiplexer. theacquisition time of the sample/ hold can be virtually eliminated.
While the first channel is in hold and switched on to the
ADC, the multiplexer may be addressed to the next
channel. The second sample/ hold will have acquired this
data by the time the conversion ,is complete. Then, the
sample/ holds reverse roles and another channel is addressed (see Figure 5). For low level systems. an instrumentation amplifier and double-ended multiplexer may

Analo!HO

BI
02

~Dig.itl.\l

Converter
1(0)

:\

High
Speed
Switch

FIGURE 5. "Ping-Pong" Sample Holds.

7-16

BI2

BURR-BROWN@

SHC803BM, CM
SHC804BM, CM

IElElI

Ultra-High Speed
SAMPLE/HOLD AMPLIFIER
FEATURES

DESCRIPTION

• 350nsec max ACQUISITION TIME

The SHC803 and SHC804 are high speed sample/
hold amplifiers designed for use in fast 12-bit data
acquisition systems and signal processing systems.
The SHC803 contains a fast-settling unity-gain amplifier for buffering high impedance sources or for
use with CMOS multiplexers.

• ±O.O1% THROUGHPUT NONLINEARITY
• 150nsec max SAMPLE-TO-HOLO SETTLING TIME
• INPUT BUFFER (SHCB03)
• 24-PIN HERMETICALLY-SEALED METAL PACKAGE

SAMPLE/HOLD
ANALOG INPUT

HOLD HOLD

ANALOG

COMMON

The SHC804 acquires a lOY signal change in less
than 350nsec to ±1/2LSB at 12 bits. Throughput
nonlinearity error is guaranteed to be within
±1/2LSB for 12-bit systems. Stability over temperature is excellent, with only ±5ppm/oC of gain drift
and ±4ppm of FSR·/oC of charge offset drift ov!!r
the -25 to +85OC temperature range.
The ±25psec maximum aperture uncertainty of
SHC803 and SHC804 permits sampling (to ±O.OI%
of Full Scale Range) of signals with rates of change
of up to IOOV / JLsec. These sample/holds have been
optimized for use with Burr-Brown's high speed 12bit analog-to-digital converter, model ADC803. Together these components are capable of accurately
digitizing fast changing signals at sample rates as
high as 500k samples per second.
The digital inputs (HOLD and HOLD) are TTLcompatible. Power supply requirements are ±15V
and +5V and the specification temperature range is
-25°C to +85°C. The SHC803 and SHC804 are
packaged in a 24-pin dual-in-line hermetic metal·
package. SHC804 is pin-compatible with other
sample/holds on the market with similar performance characteristics.
.

International Airport Industrial Park· P.O. 80x 11400 . Tucson. Arizona 85734 . Tel. 1602) 746·1111 . Twx: 911).952·1111 . Cable: 88RCORP . Telex: 66·6491

7-17

SPECIFICATIONS
ELECTRICAL
At +25' C, rated power supplies and a lkO .outputload unle~s otherwise specified.
MODEL

SHC803I804CM·

SHCIICi3ISHC804BM

PARAMETER

MIN

I

SAMPLEIHOLD INPUTS [wt1ho11tlnput buffer]
ANALOG
Voltage Range

±10.25

TYP

MAX

-

TYP

MI\X

.

±11
1.00

R'N
DIGITAL [HOLD, HOLD]

MIN

V
kO
V
V
pA
mA

+2.0

V'H
VOL

+0.8

,,~, VIN:;::

+60

IlL.

-1.2

VIN

+2.7V
== +O.4V

UNITS

SAMPLE/HOLD TRANSFER CHARACTERISTICS [_out Input buller]
ACCURACY
Sample Mode
Gain
Gain Error
TemperatlJre Coefficient
Linearity Error
Zero Offset .
Temperature Coefficient
Hold Mode
Charge Offset
Tem~rature Cbefficient
Droop Rate: at +25' C
+85'C
Throughput Nonlinearity
Power Supply Sensitivityl21; ±Vcc
Voo

±0.1
±10
±0.005
±5
±2.5

±3
±0.001
±1
±1

±10
±10
±5
±0.5
±0.01
±0.002
±0.003

±2
±3
±0.5.

DYNAMIC CHARACTERISTICS
Acquisition Time (with 10V step)
to within: ±0.1% (±10mV)
±O.OI% (±lmV)
Sample-to-Hold Settling Time
to within ±0.01% (±lrnV)
Sample-to-Hold TranSient Amplitude
Aperture Delay Time l31

Aperture

VlV
.%

-1

220
250

Unce~ainty

±0.03

±5
±3
±1.5

±1
±2

±5
±4
±0.1

ppm/'C
%ofFSR'lI
mV
ppm of FSR/' C
mV
ppm 01 FSRI' C
pVlpsec
mVipsec·
%ofFSR
%01 FSR/%V""
% of FSRI%Voo

"sec
nsec

350

100
80
15
±10
180
1
16

Sample Mode: Output Slew Rate
Full Power Bandwidt~
Small Signal Bandwidth
Hold Mode Feedthrough Rejection
(lOV square wave Input)

±1
±O.5
±0.5

150
150
25
±25

-

nsec

mVpeak
nsec

psec
Vlpsec
MHz
MHz

±0.005

%

SAMPLE/HOLD OUTPUT
Voltage Range
Output Current
Short Circuit Protection
Output Impedance (at DC)

±10.25
±50

i.

V
mA

±111

Indtini.t~~~1Com

mar

0.1

0

±5
±2.5
±25

mV
ppm of FSR/' C
nA
OllpF
V

INPUT BUFFER CHARACTERISTICS [SHCS03 only]
INPUT
Offset Voltage
vs Temperature
Bias Current
Impedance
VIN Range

,

I
±10.25

DYNA!o'IIC CHARACTERISTICS
Full.Power Bandwidth
Slew Rate C41
Sellling Time'" to ±2mV for 10V Step
OUTPUT
VOUT Range
Output Current

±112
±1.5
,0'115
±11
320
10
2.5

.

±10.25
±10.25

kHz
Vlpsec
psec
V
mA

7-18

ELECTRICAL [CO NT]
MODEL

SHC803I804CM

SHC803ISHC804BM

PARAMETER

I

MIN

TYP

MAX

±13.5
+4.75

±15
+5.00

±16.5
+5.25

30

35
20
10
40
25
10
875
1100

MIN

TYP

I

POWER SUPPLY REQUIREMENTS
Rated Voltage: ±Vcc
V••
Quiescent Current (no load)
SHC604: +Vee
-Vee
V••
SHC603: +Vcc
-Vee
VDD
Power Dissipation: SHC804
SHC603

15
5
33
18
5
700
790

MAX·

UNITS

.

'V'
V
mA
mA
'mA·',
mA
mA
mA
mW
mW

;

TEMPERATURE RANGE
Specification
Storage

-25
-55

.·C
'C

+85
+125

'Specification same as SHC603/SHC804BM.
NOTES: (1) FSR 'means Full Scale Range and is 20V for SHC603 and SHC804. (2) Sensitivity of Offset plus Charge Offset.
HOLD add 5nsec typical: (4) With buffer connected to the sample/hold amplifier.

(3) With respect 10

HOt'P.. For

MECHANICAL

~

CASE: Nickel-plated steel
MATING CONNECTOR: 245MC
WEIGHT: 8;4 grams (O.30z)
HERMETICITY: Conforms to method 1014
Condition C Step 1
(fluorocarbon) of
MIL-STD-883 (gross leak)
OlHlotflPin '.

L-.f
.. )
~IIIIII " II--L-o
Ii
I

DIM

34.67

35.18

B

.790

.810

20.57

c:

.110

.250

20.07
4.32

0

.016

.021

0.41

0.53

G

.100 BASIC

2.54 BASIC

H

.125

.150

3,1S

3.81

K

.150

.300

3.81

1.62

A

.600 BASIC

Pin numbers shown for reference only.
Numbers may not be marked on package.

MILLIMETERS
MIN
MAX

1.385

G --' ' -

• ~r+-_H-:--_--.

INCHES
MIN
MAX
1.3615

R

.080

.110

6.35

15.24 BASIC

2.03

2.79

R

NOTE: Leads in true pOSition within .010"
(.25mm) R at MMC at seating plane.

CONNECTION DIAGRAMS
VOUTO----(

COM ANALOG
POWER
-15V SUPPLY

7-19

COM ANALOG
. :POWER
- 15V SUPPlY

Aperture Delay Time is the time re/ilpired to sw;itl:ll from

ABSOLUTE MAXIMUM RATINGS

... ,.

,SlImPl," tQ ijpJ!i. Th~ . t\mt: is rn~4s~r~d' ,r!lm ihe.,50%

Input Ovc;rvoltage., ,.,,::".':,;~ .. ;, ..... ,. ±15V
-fV/!c to Vee ~OMMON .. : ......... Oto+i8V
':"'Vecto V~e COMMON ............ 0 to -18V
V~ttiigei:ib Digitallnputs
~pins 11 ;and 12) ... ; ........... -O.5V to -I: 7V
Power Dissipation ............. '..... 1500mW
V:~D to DCOM ' ..... ; .................. -O:5V
A;il~log Output: .... Indefil?-ite Short to Vee COM
NOTE: S:tressesabove those listed under "Abso,lute Maximum' Ratings" may cause perman,ent
d~mage to the device. ;Exposure to absolute maximum conditions for extended periods may affect
d~~icereliability,
"

'pdi'llHlfthe Hold mode control transition to the time at
which the output sto-ps tracking the input.
'
Aperture Uncertainty Time is;,thenonrepeatibility of
I\perture delay time. -,-,--,
.
,

"

~

..

. 'PfN"''ASSIGNMENTS

PI'1' '
2

Description

.J':II~m~

Analog voltage output
Not connected
Not connected' ,
Not connected
Not connected

Sample/Hold Output
NC

3 . NC
4

5
6
7
8
g

10
11
12
13

NC
NC;,
NG
NC, '
NC'
Voo
beOM
HOLD

','

HciiJ5 :
~/ti).;

~,uffe,: oui, SHC,SP3 only

COM,
NC

Not connected
Not connected
Signal Common
, -15V supply" '
Analog power common, connected

'::"Vcc

Vee COM

• "to'C8se" .~.

.

_I

Logic supply"
Logic su'pply common
'Logic "1" ~ HOLD
Logic "0" " HOLD
SHC804 input; for SHC803 connect
,pin 13 to' pin 14
Not conriect~d for SHC804
Signal' cornmpn
Not connected for SHC804
Not connected

+15V supply, .
,

lflis'cbsSI'dN OF'

ISPlfql~,ICATIONS

'Throug!!Jl'ut Nonlfn~irity is defined as~ota! Hold mode,
nonadjustable, inpllho output error tlilised by charge
offset, gain inonlineifity, droop, feedtprough, and thermal transients. It, iS',lhe inaccuracy 9ue to these errors
which cann'Dt becor,rected by Offset :and Gain adjust'
,,:",
': ',:
.'.ments.
Gain Error ;is the difference between 'th~ inpUt and outR~~':vQltagemagnitu.~e,(in the Sample\triode) d.ue to the
amplifier gain errors. .
, :
Dr06p.'Rat~ is the voltage decay at.tlle output wh~n iii
the Hold mode due to storage capar;itoran;d FET switch
leakage current and theinput bias cummtof the output
amplifier.
.
Feedthroug!! is the amount of output voltage change
caused by an input voltage change when the sample/
hold is in the Hold mode.

v,~....

##1
## I
#'
I
/
I
,
I

N~t conn'ecte~

. Not'cOnnected

Buffer In, SHC803 only

NC
NC
NC
COM

. ",24,,' .+Voc

'v

Not.,connecte:d
Not oonnected

i

14
15
16
17
18
19
20
21
22
23

Acquisition Time is the time requiredfor the sample(
ilold output to settle to within a given error band.qf:its
final value when the sample/hold is .switched from Hold
to Sample.
Charge Offset (Pedestal); is the output voltage change
that results from charge coupled into the Hold cl!pacitor
through the gate capacitance of the switching field effect
transistor. This charge appears as' an offset at the output,
Sample-to-Hold Switching Transient is the switching
transient which appears on the 01;ltput when the sample/
hold is switched froin SalJlple to Hold. Both the magnitude alld the Settling time of the transient are specified.

Vout

:.

'

I'
I

./SAMPLE·T,O·HOlO
TRANSIENT "
••~

I

:

"

"!

--------- ---_ .

I
"
I_ACQUISITION·
I
TIME
I

t

DROOP

I
I,

SAMPLE
HOLD,

FlGURE I. Definition of Acquisiti,on Time, Droop
and Sample-to-Hold Transient. '.

OPERATION
A simplified circuit diagramofSHC8Q3J804 is shown p,n
page I. The SHC803 includes ii noniilVertiilg unity-gain
op amp to serve as "a source:impe,dal)c,e,buffer whc:n the
sample/hold is used with CMOS analog multiplexers.
The SHC804aitd SHC803 are identical except for this
buffer."
.
In the 'Sample (track) mode the circuit acts as a unitygain in'lerting amplifier. In the Hold mode, the capjicitor, CH, holds the ~alue of the output at'the'time the unit
was switched to' the Hold mode. Additional' circuits
compensate for switching transients;md provide switch
leakage current: clj,ncellation. The amplifier provides
high current driv~iindlow output impedance to external
loads."
.'
GAIN, OFFSU; CHARGE OFFSET'
SHC803 imdSltC804~ave bee~ 'inte~~ally-trimmed to
eliminate the need for ex;ternaUrittl' potentiometers for
Gain, Offset (in Sample,mode) and Charge Offset (Pedestal).' System Gain and Offset errors cartbe"adjllsted
elsewhere in the system, at an input amplifier preceding
the sample/hold, or at an analog-to-digital converter following the sample/hold.

7-20

ouput impedance oUhe signal source should be low and
remain low over a wide bandwidth. A small capacitor at
the driving source may help to improve the charge offset
errors that are affected by dynamic source impedance.

INSTALLATION
GROUNDING AND BYPASSING
SHC803 and SHC804 have four COMMbN pins (pins
10, 15, 21, and 23) and all must be tied together and
connected to the system analog common (VccCOM) as
close to the package as possible. It is preferable to have a
large ground plane surrounding the sample/hold and
have all four common pins soldered directly to it. Note
that the metal case is internally connected to pin 23;
therefore, care must be taken to avoid a ground loop if
the case is allowed to contact the ground plane.
Most digital return currents pass through pin 10. Noise
from the switch-drive circuit may couple directly into the
main op amp summing junction, a very noise-sensitive
node. Care must be taken to insure that no voltage differences occur between pin 10 ,and the other common
pins. This is the reason pin 10 must be connected directly
to the ground plane.
For the same reason, the logic supply should be kept as
free of noise as possible. ±Vcc supply lines (pins 24 and
22) are internally bypassed to common with O.OI,~F
capacitors. It is recommended that the user install additional external O.l~F to I~F tantalum bypass capacitors
at each supply pin.

SHC803 BUFFER AMPLIFIER
The buffer amplifier incorporated in the SHC803 provides appropriate drive characteristics to the sample/
hold amplifier. Again a 20pF to 50pF capacitor added to
the output of the buffer amplifier may improve charge
offset performance.
The buffer amplifier is optimized for fast settling with
IOV pop signals. However, for step input signals greater
than IOV, a protection network (Figure 2) is required to
prevent the buffer from overload, resulting in excessive
settling time.
The data sheet for the Burr-Brown model ADC803
analog-to-digital converter contains a sample printed
circuit board layout incorporating many of the above
considerations.

2kO

SAMPLE/HOLD CONTROL

A TTL logic "0" at pin II (or a logic "I" at pin 12)
switches the SHC803/ 804 into the Sample (track) mode.
In this mode, the device acts as a unity-gain inverting
amplifier, the output following the inverse of the input.
A logic "I" at pin II (or a logic "0" at pin 12) will switch
theSHC803/804 into the Hold mode. The output voltages will be held constant at the value present when the
Hold command is given.
If pin II is used, pin 12 must be connected to the DCOM
(pin 10). If pin 12 is used, pin II must be tied to V1)1).
Using the HOLD and fIOi]) inputs as a logic function
may adversely affect the charge offset (pedestal). A clean
digital signal (no overshoot) at the HOLD or HOLD
inputs will also reduce charge offset errors. Pins II and
12 present less than one standard TTL load (two LSTTL
loads) to the digital drive circuit.
OUTPUT LOADING

FIGURE 2. SHC803 Buffer Amplifier Protection For
Input Steps Greater Than IOV.

APPLICATIONS
SIGNAL DIGITIZATION

Sample/hold amplifiers are commonly used to hold
input voltages to an A/ D converter constant during
conversion. Digitizing errors result 'if the analog signal
being digitized varies excessively during conversion.
For example, the Burr-Brown ADC803 is a l2-bit successive-approximation converter with a 1.5~sec conversion
time. To insure the accuracy of the output data, the
analog input signal to the A/ D converter must not
change more than 1/2LSB during the conversion.
The maximum rate of change for sine wave inputs is
dv/dt (max) == 2n-Af(V/sec). If one allows a 1/2LSB
change (2.44mV) for a ±IOV input swing to the A/D
converter, the allowable input rate-of-change limit would
be 2.44m V /1.5~sec == 1.63mV / ~sec. Thus the sampled
sinusoidal signal frequency limit is

Care must be taken when loading the output of the
SHC803/804 to avoid possible oscillations, current limiting and performance variations over temperature.
The maximum capacitive load to avoid oscillations is
about 300pF. Recommended resistive load is 5000 or
more, although values as low as 2500 may be used.
Acquisition and sample-to-hold settling times are relatively unaffected' by resistive loads down to 2500 in
parallel with capacitive loads up to 100pF. Higher capacitances will affect acquisition and settling times.

f == (1.63 X 103)/2trA == 259/ A(Hz)
where A is the amplitude of the sine wave. For a ±IOV
sine wave this corresponds to a frequency of 26Hz.
A sample/hold in front of the A/D converter "freezes"
the converter's input signal whenever it is necessary to
make a conversion. The rate-of-change limitation calculated above no lon!!er exists. If a sample/hold has
acquired an input signal and is tracking it, the sample/
hold can be commanded to hold at any instant. There is

ANALOG SIGNAL SOURCE CONSIDERATIONS
The output impedance of the signal source driving .the
SHC804 will affect the accuracy of the sample and hold
operation both statically (at DC) and dynamically. The

7-21

short, delay between the time the hold command is
asserted." and the time the circILi! actually holds. This
delay is'called aperture delay. The hold command signal
can' usually be advanced in time to cause the amplifier to
hold when one wants it to hold.

'11

.

"

o-----{13

.

The uncertainty in aperture 'delay, ~;alled apertu~e jitter,
is 'a key consideration. For the SHC803/804 there is a
2Spsec maximum period duririg which the input signal
should not change, for example, more than '1/2LSB for
12-bit systems. For a±IOV input range (l/2LSB =
2.44mV), the input signal rate of change limitation is
2.44m V / 2Spsec = 97 .6V / Msec. The equivalent input sine
wave frequency is

START CONVERSION

FIGURE,), SHC804 and ADC803 Provide$ampling
'Rates OVer SOOk Samples Per Second.

f=97 ..6X 106/2rrA= IS.S/A(MHz),

CH 1

60,000 times higher than using the A/ D alone.
However, there are imensio.ns in parentheses are in inches.

TRANSFER CHARACTERISTICS
ACCURACY al Gain of I V/V3
Dynamic Nonline'ari~y4

±0;01
±0.01

'0.005
'0.005
3
I
±0.005
100

Gain Error

Throughpul Offsel (Adj. 10 Zero)5
Droop Rate
Dielectrt.c Absorption 4
Noise
Common Mode Rejection Ratio

b . .l5mm
(.25")

DIGITAL INPUT (Mode Conlrol)2

+ 15V Supply Vollage Ra;'ge
-15V Supply Voltage Range
Quiescent C~rrent
+ 15V Supply - Sample Mode
-Hold Mode
-15V Supply - Sample Mode
-Hold Mold

10.lbmm
(0.40'')

I

%of20V
% of 20V
mV
/lVIp.,ec
%uf()'V

5

~V

10-4

Power Supply Rejeclion

10

fms

V/V
ppm/%

30

WEIGHT; . 56.7 grams (2 liZ)
MATING CONNECTORS;
2.100 - P.{'. Card and Terminals
2301 - Set of 2 - 16 Pin Connector Strips
PINS: IJin material and platin~ composition
conform to method 2003 (solderahility) of
MII·Std·883 I.xcepl paragraph 3.21.

ACCURACY DRIFT (OoC 10 +70°C)
Throughput Drift
Droop Rale

ppm of 20Y/oC

±2
doubles every 10,oC

DYNAMIC CHARACTERISTICS
Bandwidth (Full Power)
.Oulput Slew Rale
Acquisition Time (to .0.01%)
IOV Slep
20V Step

400
25

kHz
V/IlstJC

0.8
1.2
12

. Aperture'Time

Sample-to-Hold Transient
Peak Amplitude
Seltling 10 .01%
Feedlhrough in Hold Mode

I
1.5

",sec
",sec

Dsec

50
200
±0.005

mV
nsec
% of Step
Change at input

OUTPUT
Voltage Range
Current Range
Impedance (SlIorl Circuil Prolecled)

±IO
±20
1.0

TEMPERATURE
Specification
Storage

NOTES:
1. Inpul should never.exceed supply by
more than 0.6 volts.
2. Sholtky TTL compatible.
3. Gain is user selectable.

..

V
mA
11

°c

010 +70
-55 to +125

°c

4. For I p.sec SAMPLE and
IS p..ec HOLD times.
S. Includes voltage and charge offsets.

7-24

CONNECTION DIAGRAM
(To'P VIEW)

DISOUSSION OF SPECIFICATIONS

ACCURACY

All SHM60 sample/hold units are tested for accuracy and are factory trimmed to assure that all units meet critical specifications.

DYNAMIC NONLINEARITY
This is the unadjustable throughput error from input to output
for a I microsecond SAMPLE period and a 15 microsecond
HOLD Reriod. Errors included in this specification are through·
put nonlinearity, dielectric absorption, droop, thermal transients and feed through. Offset errors must be adjusted to zero
with an offset trim control and gain errors must be adjusted
to zero with a gain trim control elsewhere in the system.

SAMPLE-TO-HOLD SWITCHING TRANSIENT
When the mode control is changed from SAMPLE -to- HOLD,
the switching transient that appears on the output is the
sample-to-hold switching transient.

v
Yin,*> ",""

,

,

V OUI

/

,

I

. / Sample·lo-Hold
T~n~n~ _ _

I
I
I

1. __

Droop

--,

ACCURACY - UNITY GAIN OPERATION
The initial accuracy of the SHM60 is ±0.01 % maximum of full
scale range when operated as a unity gain voltage follower.

GAIN and OFFSET ERRORS - GAINS OTHER THAN UNITY
The SHM60 should be treated in the same manner as an operational amplifier when gains other than unity are employed. The
gain setting resistor parameters such as absolute accuracy and
tracking ratio must be considered when computing error effects
for gains other than unity.
THROUGHPUT DRIFT
The Jnput to output accuracy drift over a ooe to +7,OOC
temperature range is the throughput drift - it is ±2 ppm/oe or
±0.OOO2% of 20 volts.

THROUGHPUT OFFSET
The output offset voltage encountered in the HOLD mode
after sampling a grounded input is throughput offset. This
error includes charge offset at zero volts input as well as amplifier d.c. voltage offsets. ,

ACQUISITION TIME
The acquisition time of the SHM60 is defined as shown in
Figure I. This is the time required for the SHM60 to turn on,
slew and settle to 0.01 % of the input voltage when the mode
is changed from HOLD ,to SAMPLE.

Hold

FIGURE 2. Definition of Acquisition Time Droop and
Sample-to-Hold Transient.

DROOP RATE
Droop in a sample/hold is the voltage decay at the output
due to output amplifier bias curre'lt when operating in the
HOLD mode. To determine the effects of droop on system
accuracy, the droop rate is multiplied by the HOLD period.

FEEDTHROUGH
The amount of input voltage change seen at the output when
the sample/hold is in the HOLD mode is feedthrough error.
The low feed through error of 0 .00S%preserves the accuracy of
the sampled signal and can be used to increase the throughput
sample rate, especially in time multiplexed applications.

APERTURE TIME
Aperture time is the delay between the time the sample/hold
is given the command to HOLD the input signal and the time
that this actllally occurs. The SHM60 aperture time of 12
nanoseconds is sufficiently 'small to make aperture errors
negligible for most applications.

v
100

= mV
E

;,;.;

10

I
L.,.:.....Aperture

mV

I
Sample

Time

I

,I

.Hold

Acquisition Time (/Jsec)

FIGURE I. Error vs. Acquisition Time (Unity Gain Follower).

SYSTEM
ERROR
CONSIDERATIONS

FIGURE 3. Aperture Error.

The I J.Lsec acquisition time ,and 12 nanoseconds aperture
window of the SHM60 offer an excellent way of
reducing system gampling error at high throughput rates
for sinusoidal data. Taking the maximum slope of a
sine wave at the zero crossing where maximum samRling
error occurs, the error voltage as a percentage of full
scale is proportional to the product of frequency and
aperture time (ll t):

7-25

% Aperture Error ~
II \' x 100 = 21ffllt x 100
V

where II V ~ Aperture error
V =Peak signal amplitude
f ~ Maxim~m signal frequency
II t = Aperture time

INSTALLATIOM'"a:ndOPE:RA1INGINSTRUCTIONS
OPTIONAi. VOLTAGE and CHA'RGE OFFSET ADJUSTMENTS
Throughput OFFSET error'maytlOrmally be adjusted to
zero with a single external VOLTAGE OFFSET adjust
control, as shown in Figure 4., ,A small CHARGE OFFSET error of I mV to 3 mV 'in the HOLD mode may
occur. This CHARGE OFFSET error may also be adjusted to zero with an optional external CHARGE OFFSET adjustment as shoWn in Figure 4_
I

Note!

+o-oIf'-Analog
Input,? __

l
,.

.

NOTES:
I. The analog input signal should not be run under
Of 'over the module as this may degrade feed~
through in. the HOLD' mode.
2.. Potentiometers shQuld have a TCR of 100 ppm/
°c or less.

•

Care must be taken tlJ provide a good .Jow imped.
ance common as ,there'is an appreciable amount
of current returned to the power supplies.

•

Power supply hypas~ capacitors are provided in
the module, hut· additional hypassing may he
required' if excessive noise is present on the
power supply lines.

.

FIGURE 4_ Optional CHARGE and VOLTAGE OFFSET
Adjustment Connections.

CONNECTIONS FOR GAINS OTHER THAN UNITY
Output

RI'

= 10k!! max

Although optimum performance is at unity gain, the
SHM60 may be operated to provide gains ranging from
±I to ±IOOO as shown in Figures 5 and 6. For these
configurations, the unit may be treated as aM operational amplifier. Acquisition time will get longer as
gain increases, approximately 2.5 flsec settling· to
±O.O I % for a gain of 5 and 4 flsec for a gain of 10 for
10 volt output steps_ Voltage drift can be computed as
with an op amp using 10 flV/oC as the input drift.

FIGURE 5. SHM60 Connections for Inverting GAIN.

NOTES:
• Gain accuracy and drin is depen(J.ent on the
absoiute accuracy and thermat tracking properties of the gain setting .resistors R I and
RF- MetB:1 film 'or better qu~lity low drift
res.istors are recommended.
•

FIGURE 6. SHM 60 Connections for Non-Inverting GAIN.

7-26

Charge offset is independent of gain, and is
referred to the o~tput.

DATA ACQUISITION
SUBSYSTEMS

If your system requires data acquisition and conversion, you may want
to consider one of our system data modules (80M) or microprocessor
compatible modules (MP). Each contains a multiplexer, A/D converter,
and timing and control logic, with instrumentation amplifiers and
sample/hold circuits also available in some modules for use in capturing low-level and high-frequency signals. The microprocessor compatible modules (MPs) are 8DMs which contain address decoding and
specialized control log ic, making them compatible with most available
microprocessors. These subsystems, fully tested at the factory, have a
proven record of reliability.
Modules of this type are very popular in applications requiring rapid
design turn-around, and also where the user lacks the necessary skill
and experience in performing fully optimized analog circuit layouts
and component performance matching. Typical applications include
industrial measurement and control (such as process monitoring), test
equipment, and any other application requiring total guaranteed performance with a minimum of utilized space.
As with all Burr-Brown conversion products, these units are designed
to provide a total solution.

8-1

SELECTION GUIDE
DATA ACQUISITION SYSTEMS

Designed for high performance general purpose applica~
tions, these systems provide a complete data acquisition
function in one small package. You can devote your
design efforts to other tasks because the totally selfcontained system includes input mUltiplexer, instrumen-

tation amplifier (in some models), sample-and-hold amplifier and 12-bit AID converter. Timing and control
logic, clock and reference are all internal. A host of
features-even tri-state outputs for microprocessor
buses~make this .system practical, even in high volume
,buys •.

DATA ACQUISITION SYSTEMS
Throughput Accuracy

Throughput
Rate (kHz)

Package

Page

30111

Module

8-59

aUl

Module

8-87

40
29

QIP
QIP

8-65
8-65

;to.048
;to.024

33
25

QIP
QIP

8-81
8-81

;to.048
;to.024

25
18

QIP
QIP

8-81
8-81

('II>ol~SR)

Description

Model

Modular

SDM853

16.lng......nded,
8 dillerentlal

12

±0.025

Low Level

SOM858·

16 SlrigllHmded';
8 differential

12

±O.025'"

Hybrid
.±10V Input

SDM854AG
SDM854BG

16 .ingl~nded,
8 dillerentlal

12
. 12

±0,048 .'
;to.024

Hybrid

SDM856JG
SDMs56KG

16 singl......nded, .
.8 dillaranliai

12

SDM857JG
SDM857KG

16 sing......nded,
. 8 dillarentlal

12

Hybrid
Low Level
NOTES:

Channel.

Resolution
(Bits)

12
12

(1) Can be increased il short-cycled to 8- or IO-bitresolution.

,

(2) At gain = 100.

MICROPROCESSOR' INTERFACED
ANALOG INPUT AND OUTPUT SYSTEMS

These data acquisition and ,analog data distribution systems are complete-totally interfaced to the micropro~
cessor bus with no. external interfacing components
required. They provide an·instant solution by preserving
your valuable engineering design resources.

16-channel analog input systems and two-channel analog
output systems talk directly to popular buses under control of the microprocessor. They are truly design-in-andforget solutions to analog interface problems.

MICROPROCESSOR INTERFACED ANALOG INPUT SYSTEMS
Re.olutlon
(Bit.)

Accuracy
('II> 01 FSR) max

Package

Page

16 .ingl......nded,
8 dillerential

8

;to.8,high
±O.4, low

±4O

QIP

8-11

MP21

16 .ingl...... nded,
8 differential

8

;to.8,high
±0.4, low

;t4O

QIP

'8-23

Universal

MP22BG

16 .ingl......nded,
8 dillarential

12

;to.4,high
;to.l,low

±2S'11

QIP

- 8-35

High-

MP32BG
MP32CG

16 .ingl......nded,
8 dillarential

12
12

;to.OS
±0.025

;tOO

QIP
QIP

8-43
8-43

Ceramic

8-3

Description

Model

Channel.

8080-, SC/MPCompetible

MP20

6800-, 8502Compatible

Accuracy

Tempco
(ppm/· C) max

±eo

MICROPROCESSOR INTERFACED ANALOG OUTPUT SYSTEMS
8080-, SC/MPCompatible

MP10

6800-, 6502-

MPII

2

8

±O.4

±80

32-pln OIP
2

8

;to.4

;tOO

Ceramic
32-pin DIP

Compatible
NOTES: ·(1) Unipolar, excluding IA.

8-2

8-3

BURR-BROWN ®

MP10
MP11

IElElI

~ ANAl.

dU,etJ 1
H<, ....... N

<.)1.->

Nlf" 1
't;

-

~~--

Microprocessor-I nterfaced
a-BIT ANALOG OUTPUT SYSTEM
MP10. MP11 BLOCK DIAGRAM
ADDRESS

DB~1ER~I::r~~~01

t\

All

{

...u
:!
ffi
....

t

AD
Al
R/W
.
pin triple-wide dual-in-Iine packages. They. (Xlntain two
~-~it D/ A converters which are internally ti'immCd for .,
gam and offset so that no external trimming is required.
AI) .,IlcCfs,&aI'Y jlne!fa<;~•.. tiPli!1g aQd a2 (MPl1)

...

. foUllECOOER
and
Write Control
Logic

JSTRO~E

STROBE

Q

cc
II.
CI

...cc
iii

I~

~7

rv

~6
.'

.

L
A
O/A
T
C . CONVERTER
H'

."

"t
~

Y

L
A
T
C
H

.....
ANALOG
OUTPUTS

IIIIID
D/A
CONVERTER
".•

8-4

I

ELECTRICAL SPECIFICATIONS
(Typical at 2S"C and rated supplies unless otherwise noted.)

MPIO/MPll

MPIO/MPll

ANALOG OUTPUT

DIGITAL INPUTlOUT PUT
2

Number of analog outputs
Output voltage range
Output impedance
Output settling time

All signals compatible with
the microprocessor bus
An analog output channel selected by:
Input data bits read by:

.

±IOV

2510
.._

AO
00-D7

POWER REQUIREMENTS
HVDe ±S% at 90 mA
+ISV ±3% at 30 mA
-ISV ±3% at 30 mA

TRANSfER
CHARACTERISTICS
Resolution

One LSB
Throughput accuracy (max)
Throughput accuracy (typical)
Temperature coefflCient
of accuracy

TEMPERATURE RANGE

8 bit binaty
(complcmenlary binary)
1B.lmV
±o'4% FSRU,2t

IfC to 71fC
-sS'C to +8S'C

Operating temperature range

Storage temperature range

±O.25% FSR
±O.OO8% FSR/'C

I. FSR is Full Scale R.... = lOV.
2. Accur.cy components ar.: Linearity Error = ±O.2% FSR; Gain Error = ±O.I% FSR, Offset Error = ±O.I% FSR.

MECHANICAL SPECIFICATIONS
Pm .... umbers shown tor raferance only.

INCHES

Numbers may not be m.r .... d on packa9lt

r

• • • • • • • 00 • • • • • • •

2

17

B

NOTE'

~-{C:"'A'~

LEADS IN TRUE POSITION WITHIN
.010" (.25.mm)FI @lMMC AT SEATING PLANE.

1

ffi

DIM

MAX

MIN

MAX

A

1.700

1.760

'&3,18

44.70

•

1.120

1.160

29.48
0.53

.230

28.45
4.32

D

.01 •

.021

0."

F

.03'

.050

0.89

G

.100 BASIC

2.54 BASIC

H

.110

.130

2.79

1(

.150

.250

-C

L

[C

L LK oJL"~1I1,

jl

I

LL J

1

MILLIMETERS

MIN

.170

.900 BASIC

5."
1.27
3.30

3.B1

6.35

22.86 BASIC

N

.002

.0.10

0.05

>0.25

"

.110

.130

2.79

3.30

MATERIAL: Ceramic'"
WEIGI:IT: 14 grams (0.5 oz)

PI.NS: Pin material and plating composition
conform to Method 2003 (solderability)
of Mil-Std-883 (except paragraph 3.2).
MA TING CONNECTOR: 2302MC (Set of two. Ir.-pin stripsl

PIN CONNECTIONS
8080 Pin
Connections
I
2
3
4
5
6
7
8
9

IO
12
18
26
25

-

I AIO
2 Common
3D4
4 05
5 D6
607
703
8 02
MPIO
9 01
10 00
II Reset
12 RtW
13 AI
14 AO
15 +ISVDC
16 -ISVDC

....

All 32
AI3 31.
AI2 30
A9 29
A 8 28
A 7 27
A6 26
A 5 25
A4 24
A 3 23
A 2 22
B 2 21
B 3 20
+5V 19
Out I 18
Out 2 17

8080 Pin
Connections
40
.38
37
35
34
33
32
31
30
29
27

6800 Pin
Connections

--

--8
37
9
IO
II
12
13
14
15
16

-

-

17

18
19
20

20

-~,

8-5

6800 Pin
Connections
1 Output I

2
3
4
5
6
7
8
9
10
11

12
13
14
15
16

-ISVDC 32
+ISVDC 31
Output 2
+SVDC
R/W 30
---Enable
Reset 29
AO
00 28
Al
01 27
A2
02 26
A3
03 25
MPll
A4
D4 24
AS
05 23
A6
D6 22
A7
07 21
A8
Common 20
B2 19
A9
AIO
AI3 18
All
AI2 17

....

-

-34
40
33
32
31
30
29
28
27
26
21

-23

22

·~TWp.~
RtW

J

,

_TWO~

_TOW--!
07

.)

DO

•

TAW

TWA
I

Address A 13 . A9

,.

.,

N

INTERNAL
TO MPIO_

C·

I

TCW

TWC

I.

\----TAC

TAC_

I

OUTPUT INTERNAL TO MPIO

)

1

I'
Symbol

Min

TWp
TOW
TWO
TAW
TWA
TWO
TWC
TWD
TAO
TAC

430
100
6S
620
35
30
3S

Max

ns
ns
ns
ns
ns
ns
ns
ns

-635

-16

25
600

-,

I'

Units

---

TWD

:

ANALOG OUTPUT

TAO (analog otuput data stable)

>et=

~

FOR THE 8080 ITSELF

liS

TAW

~

2tey - t03 - tR42 - 140ns

TAW

~

670no Min

ns

FIGURE 1. MPIO Timing Diagram.

Enable

~

112

--./
TAEW.

Addre.s A13·

A~

,,":!E~
1VS~+ 204;

--.

---.l

OAV

I+-

-

2AV

0.4V
TWE_

Read/Write

Data

Bu~

f4-

\

1-

~

DO· 07

2AV

I

0.8V

Peripheral Data· INTERNAL Tb'MPII

OAV

I-THW

k:ov
0.2V ~

TpOWI~

2AV

0.4V

i-- r--

2.4V

X

O.4V

I

ANALOG OUTPUT
TAO (analog otuput data stable)
Symbol
TE

Min

Max

Unit

0.450

25

liS

TAEW

180

-

ns

TOSU

300

'-

ns

TWF.

130

THW

10

TPOW
TAO

17

-

ns

1.0

,..

-

2S

I-

"

ns

,..

FIGURE 2, MPII TimIng Diagram,

8-6 ,

,.

.,.~

PROGRAMMING

MVI M, DATA;

DATA = 80

Loads initialization data (80,.)'
to initialization address
.

These units are easily programmed since all are treated as
memory locations. They use any memory reference
instruction that can write data from internal registers or
the accumulator. A single instruction l1an be used to write
data to one or both channels. When the M P lOis used
'with an IlOilO, a single SH LD instruction referenced to the
lower of the two addresses will automatically transfer the
data in the H register to DACI and the da!a in the L
register to DAc2. An ST A instruction wiil transfer the
data in the accumulator to either DAC When the M P II
is used with a 6800, a single STX instruction referenced to
the lower of the two addresses will automatically transfer
the eight upper bits of the index register to DAC I and the
eight lower bits to DAC2. An STAA instruction will
transfer the contents of the accumulator to either DAC
Of course, if direct addressing is not desired, MOV
instructions may be used to transfer data from internal
registers to a specific DAC memory location. As with any
programmable peripheral. the M P 10 and M P II must be
initialized.

The initialization sequence assigns internal registers to'
function as input registers for the Di A converters. Now"
data can be written into the M P 10. This is accomplished'
by outputting the correct MPIO address:

-

a

a

()

0

User
Defined

OUTPUT I

--

a

a

()

User
Defined

OUTPUT 2

The B~ and B, inputs determine the address to which the
M P I() will respond. The four memory locations which are
possible are outlined below:

MP10IN.ITIALlZATION
The RESET input controls the siatus of the control
register of the M P 10. An active high on this line will reset
the control register to all "zeros".
The M P 10 will require initialization every time RESET is
activated. If RESET is connected to ground, the MPIO
must be initialized only orice before output of the data.

B~

B,

A~

A,

0

0

0

0

O.

I

()

I

I

0

I

0

I

I

I

I

.~

Q

a:::

At the time that the address appears on the address bUS,"
data will appear on the data bus and a R I W pulse will be: :IE
generated by the microprocessor. After 25J.1sec, the analog::
voltage will be stable at the selected output. Timing:
requirements shown in Figure I must be satisfied in order'
for the MPIO. to be initialized and operate correctly.~
These timing requirements are completely compatible.
with the 8080.
.

MPIO INITIALIZATION SEQUENCE:
I. Load initialization address

2. Load initialization data
MPIO INITIALIZATION ADDRESS:

MP11 INITIALIZATION
The RESE'f input controls the status of the cO.ntrol an~
peripheral registers of the M P II. The initialization
s~quence will differ if RESET is connected lo'a master
reset line of a microprocessor or if it is hard-wired to V".
The MPII will require initialization every time the
RESET line is activated low. If the RESET line isihard
wired to V", the MPII· must be initialized on~y 'once
before output of the data is attempted.

--

x X I

a a
User,
Ddined
X = don't care, notconm:cted tei MPIO
I = True

MPIO INITIALIZATION DATA
DJ

D.

D,

D.

D.i

I

o

o

o

'0

D~

D,

o

o

MPII ADDRESS STRUCTURE

D"

A" A,. Au A" All A,,, A. Ak A, A. A~ A. A, A; A, An
XX
,10a,YY

For 8080 the sequence may look as follows: .
LXI H, ADDR;

ADDR

.-:::::

A", A,. - don't care, not connected to M P II
A~ - Address is user selectable
A", A, - Addresses control the initialization seq~e'rii:e ' .

= Initialization address

Loads H & L registers with
.
initialization address

8-7

,,:,,' Initiali·zation sequence when RESET is hard wired to V"':
I. Load accumulator with "zeros"
2. Store, accumulator at memory locations:

'x

'X

I I

I I

'I

lOa

I 0

Address. of Control register A

A"A 14 A"A"Aj',A II,A. A. A,A. A, A. Al A, AI: A"
X X 'I I I I I I
I I lOa I I

Address of Cont,rol register B

3. Load accumulator with "ones"
4. Store accumulator at memory locations:
A"A'4AIlA"A II A IO A. A. A, A. A, A, Al A~ AI A"
XX
10aOO
XX
I
OaOI
XXI
I
OalO
X X'I
'lOa I I

Address
Address
Address
Address

For·the 6800 this sequence can be written as follows:
LOAA'
"zeros"
STAA
Address of control register A
ST AA
Address of control register B
LOAA
"ones"
STAA
Addres,s of peripheral register A
STAA
Address of peripheral register 8
STAA
Address of control register A
STAA
Address of control register 8

Loads
Stores
Stores
Loads
Stores
Stores
Stores
Stores

Or !is: LOX
STX _
LOX
STX
STX

# $0000
$ Address control register A
# $1111
$ Address peripheral register A
$ Address control register A

Initialization sequence when RESET line is connected to
maSter reseqcontrol registers A and 8 are always set to
iero after master reset and only ones need to be stored in
the re~sters): .
.
LDAA
STAA
STAA
STAA
'STA'A'

LOXX

Zeros in accumulator
zero's in CR.A. '
zero's in,~.R. B
one's in accumulator
one's in P.R.A
onc's in P.R~B.
one's in CR:A
one's in CR.B

Loads zero's in index register
Stores zero's in CR. A and B
Loads one;s in index register
Stores one's in P.R. A and B'
Stores one's in CR. A and B

x

X

I

I

I

I

I

I

I

I

I

I

II

iI

()

II

Ol'II'I'I I

X

X

I

I

I

I

I

I

,

I

I

I

()

iI

II

I

Ol'(Pt'( :!

At the time that the address appears on the address bus,
data will appear on the data bus, and if the RjW and
Enable puIses!lre COIJectIy timed, 2SJL~ec from the true
address the analog VOltage will be stable at the selected
output.
Timing requirements shown in Figure I must be satisfied
for the MJ?II to be initialized and opeiate correctly. All
timing requirements are completely compatible with 6800
microprocessors. User definable address line A1 used in
conjunction withthe 8, input all!?\Vs tn~,user ,\Pj>lace,~he
MPII in t~o different memory locations or use two
different M P II's in order to expandthe,analog system'to
four, outputs. When 8~ is wired to logical), the M P II
responds to an A, addr(,!ss of 0 and when8~ is wired to a
logical 0, the MPII'responds to an A, address of I.

"ones"
Address, Peripheral- register A
Address Peripheral register 8
Address Control register A
Address Control register 8 ,

or as:
STX
STX

of Peripheral register A
of Peripheral register B
of Control register A
of Control register B .

#$111>1
$ Address Peripheral register A
$ Address Control register A

N ow da~a C!ln be written int~ MP! I. This is accomplished
by outputting the correct MPlI addreSs:
"

8'-8

Store the following codes .in memory beginning with
location ADJ?R X:
ADDR X
- FF
ADDR X + 1- BF
ADDR X + 2 -7F
ADDR X +3 - 3F
ADDR X +4 - 00
ADDR 2 is the address of output I, ADDR 3 is the address
of output 2:

TeST PROGRAMS
The test circuit and test programs following allow the user
to test the operation of the MP 10 or MP II. The test may
be conducted by setting up the MPIO/MPII as shown in
Figure 3. The microprocessor system should have a
teletype/CRT terminal interface. The programs will step
through several output voltage levels for each DAC
output (see Figure 4). Notice how the software is different
for the two test programs to illustrate two software
approaches.

,....--<;.... . .

MPll Test Program

LOX
STX
JSR
LOX
STX
JSR
LOX
STX
JSR
LOX
STX
JSR
LOX
STX
JSR
LDAA

DAC)
OUTPUT

pP

MP10/
MP11

System

DVM

UAC2
L....-......-..J OUTPUT

FIGURE 3. Test Circuit for MPIO/MPII.
INP

MPIO Test Program

LOOP I

LOOP 2

# $ FFFF;
ADDR I;
INP
# $ BFBF;
ADDR I;
INP
# $ 7F7F;
ADDR I;
INP
# $ 3F3F;
ADDR I;
INP
# $ 0000;
ADDR I;
INP
ADDR X

Bit A #01
BEQ INP
LOA A ADDR X + I

Initialize MP 10
LXI H ADDR X
Address ofthe first
byte of data.
MOV A, M
Load ACC with first byte
of data.
STA ADDR2 Output to MPIO DACI
INX H
Increment ADDRI
CALL CI
Call Input routine
CPI
Wait for any character
80
except carriage return
JNZ LOOPI
. LXI ADDR X

Initialize MPII
Load index register
Store FF in each DAC
Load index register
Store BF in each DAC
Load index register
Store 7F in each DAC
Load index register
Store 3F in each DAC
Load index register
Store 00 in each DAC
Load Statusl w·, f
of ACIA
TT~ or
input

.-......a:::
Q

:E

Load
From Data}
ACIA

CMP A
80
BNE Back
JMP Return
BACK RTS

Jump back
to test

program or
return to
main program

The MPII test program will output -IOV from both DACI
and DAC2 then wait for an input from the TTY. Any
character except CR will advance both DACs ofthe MPI I
to the n!:xt value as defined in Figure 4. CR terminates test
program by jumping to RETURN.
ADDR I is the address of output I, ADDR X is the·address
of the ACIA.

[~~VA~~3

Output to MPIO DAC2
INX H
Increment ADDRI
CALL CI
~
CPI
Wait for any character
80
except carriage return
JNZ LOOP2
RET

Step
I

The MP I0 test program will output five different voltages
from DACI andthen from DAC2 (see Figure 4). DACI
will initially output -IOV. To step through the other
values for DACI enter any character other than carriage
return (CR). To transfer control to DAC2, enter CR.
DAC2 will output -IOV. To step through the other values
for DAC2 enter any character except CR. To exit the test
program, enter CR.

Ideal Output
-IOV

Actual Output Limits
-9.922V to -1O.078V

2

-5.0V

-4.922 to -5.078

3

O.OOOV

-0.078 to +0.0711

4

+5.0V

+-4.972 to +5.078

5

+9.922V

+9.844 to +10.000

FIGURE 4. Output Voltages for Test Programs.

8-9

Reprinted

A'PPLICATIONS

fr0r t-:1C'm.m,,:.I. ~u[~.~. }~1H. ~'oro:r~g~:.~ ~c ~~r~w~~ill. 'Inc .. 197K.

FLOWCHART USING 8080 and MP10

ANALOG INPUT AND ANALOG OUTPUT
Allhough the M PIO and M P II are analog output peripherals. the)' can he easily
adapted to provide both analog inputs"and outputs.
With the addition of a few external components; these units' ca"n each provide one
analog input and one analog output for.. your system as shown.bdo.w:

MP10 ANALOG INPUT/OUTPUT

....J

ADDRESS BUS

11

--lJ

8080

8255

System

PPA

II

r-

('

MP10 I>"l"~
l)ut

nAn
0

nUl

I I

I

DATA BUS
+lSVDS:~

Analog
Output

rr-

J

-lSVDC

~

LMlll
Comparator

A

liokll

)

Analog
Input

10kH

MPll ANALOG INPUT/OUTPUT

Analog
, 6800
System

PIA

MPtl DACi

FLOWCHART USING 6800 and MP11

Output

Out
1).<\Cl

+ISVDC~

-ISVDC
LMlll
Comparator

1-.....1'I0'lkfl'''''......OAnalo g

IOkll

Input

These systems use the microcomputer system to perform the logic o(a ~ucl'('ssive
approxim"tion A D converter .. usi~g one chann~1 of the MPIO or ~PII to
'provide the () A con\'crter reference function required. In a, successive
approximation converter. the analog input is compared to known outputs of a
D, A converter. Firsl.. the microcomputer turns the MSB on, waits for the settling
, time 'of the MPIO or MPII. and the switching time ohhe comparah>'r, then read!!
the status. If the comparator indicates that the MSB voltage is smaller than the
analog input. the MSB input to the MPIOi M.PI J SUlYS "on" and "the next most
significant bit "is turn~ on. If the comparator indicates that the MSB 'value is
larger than t"e analog inpu~. the m;crocompute~ will turn the MSB "off' and turn
"on" the next most significant bit. In this way all 8 bits ofthe 0, A converter ~re
tested. Whe.n the conversion is complete, the input'of the D/ A converter will be a
digital representation of the analog input. ThiS value will'also be stored in the
microprocessor's accumulator (complementary binary).

The A/O conversion will require approximately 900· microseconds .when
perfor~d in this manner. Burr-Brown will shortly have available a detailed
application note describing this process includmg all software required.

. Low
'... Enl~r if MIJIO/MPII anrJ
system J.lPAtpIA
wl!re initiali7.~rJ previo~slY

BURR-BROWN@

MP20

IElElI

8-BIT MICROPROCESSOR-INTERFACED
DATA ACQUISITION SYSTEM
FEATURES
COMPATIBLE WITH:
BOBDA
8085
8008
8048
Z-80
SCIMP

EASY TO USE,
Completely compatible with 80BOA microprocessors
PPAis not needed
No external logic needed
No external adjustments
Low or high level analog inputs
Unlimited expansion

EASY TO PROGRAM
Choice of ways to interface:
Memory-mapped or lID mapped
Only one instruction to acquire data

COMPLETELY SELF-CONTAINED

Addr Dec

~P

Addrlll

Bua

"

LOW COST
SAVES DEVELOPMENT TIME AND MONEY

Mux EXimple 2 Mux Example 1

rSln/DIl

~IOgln~

Mux
Addrall LJlch

Multiplexer

,

I
} OUTPUTS

-V
Addrn. Decoder

3$
6$
~P

Data Bus

} INPUTS

I

Control Logic

I

'\y/

} GAIN ADJUST .
OUTPUT

Delay
Control Logic

t--

I

I

I

T
8-8lt Analog-ID-Dlgltal Convartar

Trl-Stata Output

AOC IN I
ADC IN 2
COMP IN

~ BIPOLAR OFFSET

'II

0
Output Balaet

Dalay Adjust

International Airport Industrial Pari: - : _0_ Box 11400 - TUlllon, Arizona 85734 - Tel. (602) 746-1111 - Twx: 910-952-1111 - Cable: 88RCORP - Talex: 66-6491

8-11

.

.

.

DES'CRIPTiON
The M P20 is.acomplete analog input syst~mpackagedjn'
an 80,pin qila~"iti-line package. It; .is" completely
compatible with 8080A and 8008 microprocessQrs. his
also compatible with SC; M P and with. the Z-80. The.
. MP20 contains a high speed 8-bit A, D converter. an .
instrumentation amplifier. an input multipleXer tliat pan
accept up to 16 single-ended signals or 8 differential
signals as well as interface. timing and address decoding
logic. The gain and offset are internally laser trimmed so
that no external adjustments are required on the ±5V orO
to +5Vinput range io obtain an absolute accuracy of
better than ±O.4'1c (I LSB). The system can digitize low
level or high level analog signals. The gain.of the internal
instrumentation amplifier can be programmed with a
single external resisto,f'to allow input signal ranges as low
as ±IOmV. This means that the MP20 can be connected
to low level sensors'such as thermocouples and strain
gauges without external signal amplification.
The address lines AO through AI5 are low power
Schottky ril compatible and can be connected directly

to the address bus o( an 8080A or.8oo8. Alraigitalinput
lines rt\qiJire standard lSTIL ,voltages. . .

'When;pr<1g~;i,mming these periphel'al~:the' user treats
th\!ih' as memory. Each analog input channel occupies'
oJ)el1\lImj'lry location. Any memory reference instruction
can beilsed. Since most microprocessors have been
optimiied for memory usage. memory reference
instructions are the most powerful instructions in a
microprocessor's repertoire. The M P20 is treated as
memory to simplify software and allow an almost
unlimited number of systems to be conne'eted to .i'~ihgie
processor. P\ns A1 to A 14 are made available so that the
microperip'heral address can be hardwired for almost any
possible memory lo<;ation. Since these units are treated as
memory. a single instruction is all that's needed to read an
input channel. For instance, when the M P20 is used with
an'HOHOA. a single instruciion;LHLD. can be used to
input data to the Hand l registersJrom two consecutive
analog inputs. Likewise. a single lDA or MOV
instruction will input data from one channel to the CPU.
·\NAI.l>lO INl'l'TS

MP20 BLOCK DIAGRAM

0- N
~

i

r- -

N

~~

!! ~ !

,

or, ..::: .....
- ~

~

-N

.....

'It or,

--

-

-

~ ~ ~~ i i i
o

-. ..,. .,.. oC ....

0-

'"'I..,.
r-I"""

00 '" -

~ ~ ~!!~! ~ ~

-

:!:

.
c

-\0

."

ts;('hannel

·\2

I.aldl

Analog
MultiplexC!r

·\3

-

8-('hannel
Analog
MultiplexC!r

..\4-

f
f

77

-\5
Ab
.\7

"

\11 IX onl HI
AdJrCIl"

.\"

AIO

7•

,.

A"
.\ 13

"

-\1

11\ IN III

Cuntrul
Lt)~il

~

r

M

A!

M
A7
AS
A9
AT1i

}'' SclCl'1

.lll

ill
AU
114
\fRIT,

{wm
IlBI~

6.

a0
C

(,~'\IN

IA OliT

c

"

66

~0

a.2Sk

r.-

('untrul

I.Uftil'

.7
63

AI)(' IN I

Aile IN.2

COMP IN

Statu!>

1'0

I{

" .

.-\,IlJlJS·1

~

0-

R"WIT 0
H.L:\U'r

"-

IAIN(O

Ilc\:odl..'r

All

"-

~

MI.X Olr) LO

At{

6S

III
112

8-Bit
Analog-to·digita'
ConvC!rter

iH
Ilo
DS
1M
117

8-J2

8110

SPECIFICATIONS

MECHANICAL
LEAOS IN TRUE POSITION WITHIN
.015" !.38mmIR lei MMC AT SEATING PLANE

ELECTRICAL

P,nnumbe,"Shownfo•• afatanceonlv
Numbe" mav not be m~r~ad on p&clr.age.

-&-:-:-::-::-:-::-:-----.,
8 bits binary
16 single-ended!8 differential
40",sec/channel
AOC gain ranges

Amplifier gain range
Amplifier gain equation
Ma)( input voltage without damage(3)
Max input voltage for multiplexer

operation
Input impedance
Bias current 25°C
Bias current O°C to 700

e

0-5V, O-IOV, ±2.5V, ±5V, ±IOV
2 to 250
G = 2 + •50kn/REXT .(2(
±20V

±6V
5 x losn II lOpF - OFF channel
5 x l09n II lOOpF - ON channel
lOOnA
200nA

Amplifier output noise

Gain = 100, Rs = soon
Amplifier input offset yoltage. max
Amplifier offset voltage drift
Amplifier settling time ,to 0.1% FSR
G = 2
G = 10
G = 50
G = 100
G = 200
CMRR ,for dill.rential
G = 2

400,.,.V, rms ·10Hz to 10kHz

:tlmV
~16

.

~.~~ ~-i
1 R~' .................
.......

~

t[~~T=!-;:;:;~;:;:;~)"J
DIM

lOO~sec

MILLIMETERS

MIN

MAX

MIN

MAX

2.'20
1.670

2.180
1.720

53.B5

55.37

....

.230

200lo'sec
70dB DC to 60Hz

.01B

0.46

. 100 BASIC
.100 BASIC
.150
.250
1.500 BASIC
.010

:to.4% of FSR(51
:to.4% of FSR
±O.8% of FSR
±0.8% of FSR
·±0.2% of FSR
-±0.2% of FSR
±I/2LSB
:to.1%
±O.I% of FSR

Quantizing efror

.~

INCHES

20~sec

Gain errOr(4)
Offset error( 4 )
Power supply sensitivity
±I5V

.100 BASIC
.200 BASIC
t.looBASIC

2.54 BASIC
6.35
38.1 BASIC
0.25

MATERIAL: Ceramic
WEIGHT: 32 grams. 1.2 OZ
PINS: Pin material and plating
composition conform to
method 2003, solderability
of MIL-STO-883 except
paragraph 3.2
MATING CONNECTOR'
2350MC ,set of four 20~pin
strips

2.54 BASIC
5.08 8ASIC
27.94 BASIC

PIN- CONNECTIONS

±0.02%/%.l Vee
IJin I

IA (iA)\. ADJl"SI
IA 1\ HI
IA (iAI,\ AllIl"SI
~l X OJ I UI
1\7
1\ f>

I\" 5

5 TTL loads or 20 LSTTL loads
AO - A3
DO - 07

44
45
4.

.,

'" "(
"

1\0
\11 X I \'..\HII I
\11 X I·\·\HII

5:!

"",

·\0

/'

.\(

71MSn)

n.
1)5

114

D.'
J)~

1)(

DO 11.S8)
-15\"
-15\

1>4
115

('()!\W 1\
,\\..\ ('O!\t
HI'()

AM

M

i·\OII

Ai<

""

Ah

A7

A7
M

~

AIO

AiO

••

I\" c.J RFI I

""

I' 10 IoU I

7.l

_14

All

J5

AiT
All

.17
JM
J9
40

ill

77

AD

"1.

AOOR DECODE O!' I

I:"'; K RI·I 0

70

J.

m

R,
R(

74

75

7.

M"

.::!

1\ II HI I .1
1:,,\ I~ KI· I -I
1\ IJ HI I .:\
1\ I~ KI· I n
1:,,\ 15 KFI 7
Ml'XOlIIO
Ot-:fSET !'IWII
IA 1:,,\ 1.0
OfFSE"l !'iliLI.

PIN FUNCTIONS
IAGAIN
ADJUST

(Optional). Pin I and Pin 3. By connectirg
a resistor between pin I and 3 the gain of
the internal instrumentation amplifier can
be varied as follows:
Gain = 2 + (50knl R)
where R is the gain setting resistor. The IA
is factory adjusted for a gain of 2 without
any external resistor.
I mportant: If a gain greater than IO is
required an external capacitor must be
connected frolll "DELAY" (pin 49) to
+5V. This increases an internal delay to
allow for the increased settling time of the
instrument\ition arnplifier;
lAIN HI
Pin 2. This is the positive 'input of the
internal instrumentation amplifier. This
should beconnected to pin 4 (MUX OUT
HI) for normal operation.
MUX
Pin 4. This is the high output of the analog
OUT HI
input mUltiplexer. This is connected to pin
2 (IA IN HI) for differential operation. It is
connected to pin 77 (MUX OUT LO) and
pin 2 for single-ended input operation.
IN7 - INO
Pins 5 - 12. The first 8 (of 16) analog inputs
for single-ended operation or the 8 positive
inputs for 8 channel differential input
operation.
MUX
Pin 13. Leave open for single-ended input
ENABLE I operation. Connect to pin 14 (MUX
EN ABLE 2) for differential input
operation.
Pin 14. Connect to pin 15 (SIN/DIF) for
MUX
ENABLE 2 single-ended input operation. Connect to
pin 13 (MUX ENABL,E I) for differential
input operation.
SINjDIF
Pin IS. Single/ Differential input operation
connect to pin 14 (MUX ENABLE 2) for
single-ended operation. Leave open for
differential input operation.
AO- A3
Pin 16 - 19. Address lines that select one of
16 analog input signals (INO - INIS). 0000
selects channel 0 and IIII selects channel
IS when the correct address is presented to
the MP20. Connect A3 to ground for 8
channel differential operation.
A4 - AI5

Address lines. Pins 20, 22, 24, 26,2830,32,
34, 36, 38, 41, and 43. When the proper
address is presented to the MP20 in
addition to the MEMR (pin 44) pulse, the
conversion is initiated.
Address select lines. Pin 21, 23, 25, 27,29,
31,33, 3S, 37, 39 and 42. By connecting
these lines to DIG COM or +S volts
(through a I k!l resistor) almost any
address can be assigned to the MP20. For

example if A4 is connected to GND., the
correct (valid) address for A4 is' a "I"
(> + 2.0).
ADDR DEC Pin 40. A positive pulse will appear when a
valid address appears on the MP20 address
lines and MEMR (pin 44) is low. The rising
edge of this pulse strobes.the input channel
select information (AO - A3) into a latch. It
can also be used for external purposes.

DBIN
ENABLE
RESET

Pin 44. Memory read. A "Low" pulse on
this line along with a correct address will
enable DO - D7 (data lines). Also used to
initiate a conversion.
Pin 4S. Connect to DBIN on 8080.
Pin 46. Enables MP20 output. Connect to
ground for normal operation (see figure 7).

Pin 47. A "Low" on this line is required to
RESET the MP20. Connect to RESIN
input of the system's 8224 or invert 8080's
RESET input.
Pin 48. When the MP20 is "Read" by the
READY
microprocessor, the READY line will go
"Low" until conversion is complete. If the
READY line is used to halt the CPU, the
8080 will enter a "Wait" state (Tw) until the
mUltiplexer, instrument amp, and A/ D
converter have completed converting the
analog data to a binary 8-bit code (40J.Lsec)
with gain";; I0). The READY line will then
return to its "High" state which releases the
processor from the Tw state. The output
data appears.on the data bus (DO - D7)
, during the T3 state.
DELAY ADJ Pin 49. When the MP20 is addressed, an
internal delay of approximately 35J.Lsec is
initiated to allow for multipiel(er and
instrumentation amplifier settling time.
When the IA is operated with gain> 10 this
delay must be increased (see Figure 4 and
Figure 5) to allow forthe increased settling
time of the IA.
Pin 50. +5V at 140mA maximum, 90mA
+SV
typical,
Pin SI. Digital common. This pin should
DIG COM
be connected to analog common (pin 64) as
close to the MP20 as possible for optimum
perforinance.
OUTPUT
Pin 52. This pin should be connected to
SELECT
DIG COM to obtain binary data at DO D7. To obtain two's complement data
(bipolar mode) connect pin 52 to +5V
through a lkn resistor.
D7 - DO
Pin ?3 - 60. 8-bit data bus. Tri-state low
power Schottky TTL compatible.

8-14

-ISV
+ISV
COMP IN

ANA COM

BPO

R2

Pin 61. -15 volt at 30mA typical.
Pin 62. + 15 volt at 30mA typical.
Pin 63 .. Comparator input of 8-bit AI D
converter (successive-approximation).
Leave open for unipolar operation or
connect to "BPO" (pin 65) for bipolar
operation.
NOTE: This point is extremely sensitive to
noise. Any connection to this line should
be as short as possible and shielded by
ANA COM or ±15 volt supply patterns.
Pin 64. Analog common should be
connected to digital common (pin 51) as
close to the M P20 as possible for optimum
performance.
Pin 6S. AI D converter bipolar offset. It
should be connected to ANA COM (pin
64) for unipolar operation of COMP IN
(pin 63) for bipolar operation.
.
Pin 66. A () converter input resistor.
Connect to IA OUT (pin (8) for 0 to +5V
input unipolar operation or ±2.5V input
bipolar operation. Leave open for ±5V
input bipolar operation.

11 320n80c
TI

Pin 67. AI D converter input resistor.
Connect to IA OUT for±5 volt operation.
Leave open for other input ranges.
Pin 6S. Instrumentation amplifier output.
IAOUT
Connect to R I (pin 67) or R2 (pin 66) for
normal operation.
IN8 - IN 15 Pin 69 - 76. Analog inputs S through IS for
R ETO- R ET7 single-ended operation or analog returns 0
through 7 for differential input operation.
Pin 77. Multiplexer output for
MUX
OUT LO
INS - INI5
RETO-RET7
Connect to "MUX OUT HI" (pin 4) and
"IA IN HI" (pin 2) for single-ended input
operation or connect to "IA IN LO" (pin
79) for differential input operation.
RI

OFFSET
NULL
IA IN LO

Pin 78, 80. Optional instrumentation
amplifier offset adjust (see figure I).
Pin 79. Negative input of instrumentation
amplifier. Connect to ANA COM (pin 64)
for single-ended input operation or"MUX
OUT LO" (pin 77) for differential input
operation.

M4 Machine Cycle
_,_

T2

~.

I

I

Tw - - - - - - - - - \ .

T3

- ii

AIS·AO _____--'
07·00

y

MEMR

----------1

ADDRESS
DECODE..:.R'--_-'-_ _ _ _ _+...JJ
_ _ _ _ _ _ _ _-+~~t,AD

tADJL-

--~~~===~~-fl------....;,\\..------

READY
DBIN

tENABLE
- - - - - - tREADY-

All waveforms shown are for an 8080A - 1 microprocessor operating at:
CLOCK PERIOD (tCY) ~ 320nsec
INSTRUCTION CYCLE ~1.3"8ec
,. and '2 clock signals are shown for reference only. They are not required for operation of MP20.

MP20 Timing Diagram Normal Operation (LOA Instruction using READY to stop microprocessor during conversion).

8-15

M4

Machine CYcle
I

I'

-----07 - DO

STsB

-X~T~'LU~ ,..

- -- .... _---DATA OUT

__

J~ SYMBOL
tAD

V

tMR

\

MEMR'
ADDRESS
DECODER

to READY

\
I

ODIN

MIN

MAX UNIT
25

.. nsee

100

nsee

90

nsec

40

nsee

40

,usee

and correct address

/

I

PARAMETER
Delay from MEMR
to AD DR. DEC.
Delay from MEMR

\

tRS

Delay from

tENABLE

READY to 1112
Output Data Stable
from DB IN

tREAOY

Conversion time

READY low

The LOA Instruction will READ the data from the previous conversion and start a new
conversion. The new data can be read in 40JJSec (max).
CAUTION: Do not read the MP20 while a conversion is in progress or an.enoneous
output may result.

MP20 Timing Diagram (LDA Instruction without stopping microprocessor during conversion).

OPERATING INSTRUCTIONS
PROGRAMMING
The MP20 is easily programmed since it is treated as
memory. It uses any memory reference instruction that
can read data. A single instruction can read data from one
channel (LOA) or two adjacent channels (LHLD).
Example: MP20 used with an 8080. MP20 base address FF70; acquire data from channelsFF70 through
FF72. Normal operation.
LHLD FF70

Acquires data and transfers channel 0
(FF70) data to L register and channell
(FF71) data to H register.

LOA FF72

Acquire. data from channel 2 (FF72) and
transfers to the accumulator.

LOA FF70

Starts conversion of channel 0 (FF70).
m~.croseconds of software here to
insure that conversion is complete.

{ At least 40
LOA FF71

Transfers conversion data from channel 0
(FF70) to accumulator and starts conversion
of channell (FF71).
At le ..t 40 microseconds of software.

LOA FF72

Transfers conversion data from channell
(FF71) to accumulator and starts conversion

of channel.2 (FF72).
At least 40 microseconds of soft~are.
LOS FF7X

The MP20 may ,be opetated in several programming
modes. The minimum software approach (i.e., one
instruction to acquire data as described above) is to halt
the CPU during conversion (40 ~sec). This mode of
operation is effected by cortnecting the READY line (pin
48) of the MP20 to the 8080's READY input. TheMP20
may also be operated without halting the CPU: In this
mode ·of operation conversion may be initiated by a
memory read instruction referenced to the prOper
channel. When the conversion is complete, the data value
may be acquired by another read instruction. The second
read instruction can be referenced to any channel address
of the MP20. This instruction should be addressed to the
next channel to be acquired since it will start a conversion
. cycle.
Example: MP20 used with an 8080. MP20 base addressFF70; acquire data from channels FF70 through
FF72. Do not halt CPU.

8-16

Transfers conversion data from channel 2
(FF72) to accumulator and starts conversion
of any other channel of data.

The time required for conversion may be between40~sec
and 200~sec depending upon the gain of the internal
instrumentation amplifier. Therefore, the 40~sec time
between LOA instructions shown above could be as long
as 200~sec for a system used in the highest gain mode. If
desired. the READY line may be polled to determine that
conversion is complete and the data output· valid. Of
course. if' direct addressing is not desired. MOV
instructions may also be used.
Example: MP20 used with an 8080: MP20 base address
Ff70. Normal Operation. Re.ad and Print the
;yalue of all 16 input channels and then stop.
CROUT
NMOUT
BEG 1:

EQU 0lF3H (OIEEH)
EQU 02C2H (02C3H)
LXI SP 3FFF H (l3EDH)
LXI H OFF70 H
:Address for channel zero
MOV 0, M.
:Read data from board
CA·LL CROUT
:Print CR & LF
MOVA,D
.
CALL NMOUT
:Print data

:N ex t channel

INXH
MOV A.L
CPt!Q

8~- - - 0

R,

:Have all 16 channels
been read'?

78

IMP BEG!
WHOA:

HLT

This program assumes' 'that the system is under the
control of the SBC80/1O prototype package monitor
(M80P, version 1.0, March I, 1976). The locatio{ls in
parenthesis are used with the MCS~80system design kit.

SINGLE ENDED VS. DIFFERENTIAL INPUTS
The MP20 analog inputs may be connected as singleended. differential or pseudo-differential. Single-ended
operation may be used for high level (over one volt full
scale) signals in low noise environments (Figure 3).
Differential operation will reject common,mode noise
appearing on both inputs (Figure 2). It should be used in
noisy environments or with any low level signal (less than
one volt). In the pseudo-differential mode. the MP20 is
connected as for the single-ended mode in Figure 3 except
the I.A. low input. pin 79. is not grounded. Pin 79 is
connected to an external ground that is common to all of
the analpg inputs. In cases with a noisy ~emote ground
where little noise will be picked up between sensor and
MP20. the pseudo-differential mode may be used.

ANALOG. INPUT RANGE SELECTION

TABLE I. Analog Input Range Pin Connections.

~5V

ADC Range

Pin Connection!>

:tIOV

65 to 63: 66 open; 67 to 6K

±2.5V

±SV

!J.25V

±2.5V

65"

o to 5V

o to IOV
o to 5V

65 to 64; 66 to 68; 67 open

o to 2.SV

(hJ

FIGURE I. (a) MP20 Gain Adjust: (b) Offset Adjust.

The MP20 may be set for any range between ±5V and
±IO mY. Table I shows the pin connections for the
various high level ranges available.

Gain

G == 2 + ·50kU
R! + R2
R2 is fine adjust

(aJ

The base address of the MP20 is set by inputs A4 through
A14. Address lines A4 through AI4 respond to the
inverse of inputs A4 through A14. For instance. if A6 is
grounded. A6 will respond to a "high" input. AI5 is
internally connected to respond to a "high" input.

MillO Input
Range

-15VDC

IOOkH

MP20

JZWHOA

65 to 63: 66 to 6K: 67 open
(0

63: 66 to 6K; 63 to 67

The M P20 is set for single-ended operation when wired as
shown in Figure 3. The microprocessor address lines are
connected as indicated in the Pin Connections table on
page 3. Differential operation occurs when the unit is
connected as in Figure 2. However. address line A3 (Pin
19) should be grounded and A3 on the microprocessor
connected to A4 on the MP20. The remainder of the
higher ordered microprocessor address bits should be
connected to the next higher bit on the MP20.

65 to 64; 66 [(l6~; 63 10 67

The M P20 may be set to output da.ta with straight binary
coding (pin 52 grounded) or two's complement coding
(pin 52 to +5VDC through a I kO resistor). Straight
binary coding is typically used with unipolar input ranges
and two's complement coding with bipolar input ranges.
Table II describes the coding.
Th~

internal instrumentation amplifier is factory set for a
gain of 2. This gain can be increased to 250 by adding an
external resistance (R,.,,) between pins I and 3. R,,, should
be a stable resistor (10 ppm "C) since this temperature
drift will add to the accuracy temperature coefficient. The
gain of the amplifier can be determined by this formula:

Analug

Input:>.

MP20

+

~-dannl..·1

+0----1-1

,
Pin

Gain = 2 + 50kO With pins I and 3 open. the gain is 2.
R~'\I .

('Untll'l'lum:.

150('11.'11
l.llO ,-'

Since the amplifier input offset will be multiplied by the
amplifier gain. lin offset adjust may be required (see figure
Ib).

differential
analuJ:!,
multipkx.cr

+

1
.l·bi! Channel Sc,'lel..'!

T'to 7'l

. FIGURE 2. Differential Input Connections.

TABLE II. Ana'iog Input Values.
DIGITAL OUTPUT
Straigh1

8inar~

ANALOG INPUT

Code

:t5V

o ttl +5V

±lOmV

+9.92mV

IIII IIII Wh.,)

0111 IIII Ph.)

+Full Sl.:ulc

+4.9bl\'

+4.9KOV

11100 IXXIO IMO,,)

IXXX) OIXXI (lXI ... 1

Mid-Scale

O.lXK!I·

2.5(NJ\'

O.IXXI\'

IXXIO OIXXI (lXI,.).

IIKKIOOOOI"O".)

-I-ull SL'aic

·5.lKm·

O.IXX)\'

-1O.lKlml'

J9m\'

19.5mV

7M.\,

Onl' I

sa

8-17

The only external factor. other than glli ll •that effects the
,MP20 settling time is the impedimce of the source
connected to a channel. Figure 6 shows' a circuit model of
an "ON" channel.

"\n.tlli/,!
l!lrul~
16~channd
single~cndcl,!

0-- ,

The signal at the output ofthe rrniltiplieJ' must be allowed
to settle ,to ±O.I % (six time constants) to maintain the full
a~curacy of the ~·ystem. The m~Itiplrxer' time constant
can be calculaied"wit.h the equation:'T d (Rs + RON)C,•.
For Rs = I.k!! and,'C, 7' SOpF./ =(I.S + I)k!! x SOpF =
12Snsec. Thus 0.7S~sec is needed to settle to ±O.l%. For
high input impedances requiring mo're than lO~sec for
mu!tiple"xer settlin"g tl1!ae. the required dcla"y titne :inay

~naklg

multiplcxcr
Pill

111:

('llnnc~:tHlns

15111"14
1-'()~'1I
"'7 hi

4

F!GURE 3 .. Sin';;le-ended" Input Connections.

DELAY TIMING
A delay time between channel, selection and start of
conversion is built into the MP20 to allllw the analog
multiplexer and instrumentation amplifier (I.A.) time to
settle before starting the A '0 converter. As the gain of
the amplifier is increased. the settling time required
increaseS. The factory set delay time (3S}Lsec) is sufficient
for gains of up to 10. At higher gains. a capacitor must be
lidded fro'm pin 49 to the +S VOC supply to increase the
delay time. Figure 4 shows the settling time .of the M P20
vs. gain. Figure S shows the value of capacitance required
to increase the delay.
250

;;

3"

1

I

IsoH
IIX)

50

()
()

/

,/

c.:-=

SOpt-" fOr'~inglc~ended" mode
C. == 12.SpFfurdifferentialmode
Rn ... • == () for singk~C"ndcd m()d ...'

FIGURE 6. "ON" Channel Circuit Model.

I.()(}

15(}

21M)

.250

IA Settling Time (~sec)

FIGURE 4. TypicallASettling Time vs Gain
(Output Settling to ±O.I%J.
,11N )

I

~

/

V

/

/

100
K(}

so

.19

35

~

"/

'f:, ,

co
o :c:::::"

1000

1 jl.;.il

R" ... •

~V

so

i:;'

Sourcc"
Rc~i~tancc

'/

V

-g
\!

T mu, is the settling time 'of the multiplexer and Tl,\ is the
settling time of the instrumentation amplifier as shown in
Figure 4. If-the source bandwidth can be limited. high
impedance sources may be accurately handled by placing
a' large' capacitance across the, multiplexer input. An
analysis of such a circuit shows that a capacitor of O;S}LF
is sufficient. For such a capacitance the multiplexer time
constant becomes 80nsec.
'

/

I /

I.
I

I

~(N).

;,.

I

I

be calculated with thi~ fo~mula: T,,';"JT1mu, + T 1'A. where

20()O

"lO()()

4(K)()

soon

Capacitor Value (pF)

FIGURE 5. l\pical Delay Time \'s CapacitOt Value.

INPUT OVERVOlTAGE PR9TECTION
As shown in Figure 6. the analog inputs have reverse
biased diode circuits w.hich protect from, damage by
overvoltage (such as static). It is still reasonable to take
precautions against static discharge. The same circuitry
protects the inputs from steady-state overvoltage damage
during operation; The MP20)s. overvoltage protection
can be increased by adding series resistors at each input.
The input resistance must limit the current flowing
through the input protection diodes to 10~A. For
instance. if ISk!! resisto~sare added to each input: the
protection is increased to 16SV (16.5((0 x IOrilA).
I ncreased input resistance will. of course. increase the
amount of time necessary for the multiplexer to settle as
'.
described in the previous section.
OUTPUT EN,ABlE
The circuitry used to enable the tristate output lines (0700) on the MP26can be connected in such a way as to
meet· a wide variety oftimlng requirements. The output ,is
enabled only when the address decoder output (pin 40) is
high. OBIN (pin 4S) is high. and ENABLE (pin46) is low.
Any other combination of digital signals on these lines
will result in 07 - DO being in a high impedance state (see
'Figure 7).

8-18

To ADDR. DEC.

ADDR. DEC.o-:,:---L.--""--'"

07-DO ENABLE

DBIN

°lilg~100

FIGURE 7. Output Enable Circuitry.
The combination of a correct address and a memory read
(MEMR - pin 44) command will cause the address
decoder output to go high. If ENADLE is not used it
should be connected to DIG COM. IfDDIN is not used it
should be connected to +5V through a I k!l resistor. Most
applications will only require the use of one of these lines.
lines.

RESET
It is important to reset the MP20 on start up with a low
pulse on the RESET line (pin 47) if the READY line (pin
48) is being used to halt the processor. The reset pulse
simply clears an internal flip-flop and guarantees that on
start up the READY line will go high thereby not halting
CPU.
If the MP20 conversion cycle is being timed out by
software control, a reset pulse is not necessary. If the
RESET line is not used it should be connected to +5V.

CONVERTER INITIALIZATION
On power-up, the state of the ADC internal circuitry is
indeterminate. One conversion cycle is required to initialize the converter after power is applied.

HIGHER SPEED OPERATION

300

400

500

FIGURE 8. Typical Resistor Value to decrease
Delay Time.

CALIBRATION
The MP20 is laser trimmed at the factory to ±o.4%
accuracy when using the ±5V or 0 to +5V ranges. If one of
these ranges is used, no adjustments are required. If the
±2.5V, ±1.25V or 0 to +2.5V ranges are used, an offset
adjust only is required. For other ranges, both the gain
and offset must be adjusted. Figure I shows the
adjustment connections. The gain adjustment should be
made such that the transition to a full scale output (1111
1110 to III I llll for straight binary) occurs with an
input of positive full scale less 3; 2LSB. One least
significant bit (LSD) is the full scale range (FSR) divided
by 2" where n is the number of bits oftheAjD converter.
For the MP20, one LSD is FSRj2 8 = FSRj256. The
offset adjustment should be made such that the transition
to minus full scale output (0000 0001 to 0000 0000 for
straight binary) occurs with an input of negative full scale
plus 1,2LSB. For a range of ±50mV, ILSB =
100mV 256 = O.39mV. The gain adjustment should be
made at +50mV - (1.5)(O.39mV) = +49.42mV. The offset
adjustment should be made at -50mV + (0.5)(0.39mV) =
49.80mV. Table III shows offset and gain calibration
values for typical ranges.
Table III. Calibration Values.

The M P20's internal instrumentation amplifier requires
35J.Lsec to allow for settling time. If this internal amplifier
is not used, substantial improvements in throughput rate
can be obtained. This is easily done since neither the
inputs nor the output of the instrument amplifier are
internally connected. For instance, Burr-Brown's 3507J
high speed op amp (for single-ended inputs) may be used,
with a settling time ofO.2J.Lsec for gains of up to 100. The
total delay time necessary may be calculated by this
formula:
Tn

200

MP20

Instrument

Input Range

Amp Gain

±SV
o to +SV
±2.SV
o to +2.SV
±J.2SV
0- SOmV
±2SmV
0- 2SmV

= JT'MI:X + T"A'

2
2
2
2
2
100
100

200

ADC Range
±IOV
o to +IOV
±SV
o to +SV
±2.SV
o to +SV
±2.SV
to +SV

o

Calibration Values
Offset

Gain

-4.980V
+9.8mV
-2.490V
+4.9mV
-J.24SV
+98,soV
-24.9mV
+49,.V

+4.941 V
+4.971 V
+2.471 V

+2.48SY
+J.23S
+49.7mV
+24.7mV
+24.9mV

The following program may be used to adjust gain and
offset.

where T MI'X is the settling time of the multiplexer
(750nsec) and T'A is the settling time of the instrument
amplifier. For a TIA of O.2J.Lsec we have Tn = O.78J.Lsec.
Using 3/Lsec for the delay time to allow for unit to unit
variation, the total throughput time will. be 8/Lsec
(including 5J.Lsec for ADCconversion time) or 125kHz. A
resistor between pin 49 and +5VDC will reduce the delay
time from the factory set value of 35J.Lsec (see Figure 8).

REF

EQU OOH

Offset Ref =OOH
Full Scale Ref = FFH

CO

EQU 0IE8H(OlE3H)

Monitor routines

CROUT EQU OlF3H(OlEEH)

8-19

NMOl!T EQU

BEGI:
BEG~:

CLP:

ORG

3C50H

LXI
LXI
MVI
LXI
MOV

H,OFF7.eJH
fnitialize
SP,3FFFH(J 3EOH)
E,IOH
B,O
A,M
:Read data from
board
REF
:Increment data
count if data =
REF
NEQ
B
C
:Have 100
conversions
been made?
A,64H
C
CLP
A,B
:Yes, Print data
count
NMOUT
C,20H
:Print a space
CO
E
:Fulliine been
printed?
BEG2
CROUT
:Yes, Print CR
& LF
BEGI

SUI

NEQ:

Oi('2H(02C3H)

JNZ
INR
INR

MVI
SUB
JNZ
MOV
CALL
MVI
CALL
OCR
JNZ
CALL
JMP
£NO

This program assumes that the system is under the
control of the SBC80/10 prototype package monitor
(M80P, version 1.0, March I, 1976). The locations in
parenthesis are used to allow the program to work with
the MCS-80 system design kit. It may be used for both
offset and gain calibration. The system offset should be
adjusted first, followed by the gain adjustment.
The address of channel zero is assumed to be FF70'.1 f it is
not. the LXI H instruction should reflect that change. The
[efe'rence values on the first line assume straight binary
coding. For offset binary coding. Offset Ref= 80 and Full
Scale Ref = 7F.
A G3C50 monitor command will begin program
execution. After 100 conversions have been made, the
value (in hex) oflhe B register will be printed. This value
represents the number of times the data read from the
board was e4ual to "REF" (00 for' offset: FF for gain).
Calibration is performed by connecting a voltage source
capable of 0.01"; accuracy to input channel zero (this
could also be a DC voltage source of less absolute
accuracy whose, output is monitored by a 0.0 I ,; DVM):
'rhe offset adjustment is made first by using the
appropriate offset calibration \'oltagc. Run the
calibration program and adjust the' on board offset
potentiometer until the B register contains a \ aluc
between I E It, and 46", (30,,, and 70,,,).

To perform the gain adjusiment dlimge the data fabeIed
"REF" in the calibration program from 00 to FF, set the
input voltage to the, correct value as shown in Figure 8
and adjust the on board gg's Z-80.

ADDRESS BUS

INO
IlIlIN

I
AN ..-d.l> (.;

INPUl

j

I

-

MifMR
MI'20
REAllY
IN 15

AO

All

AO

AIS
'-'-10

45

Out I

18Iootion:l)

LOBIN

'~2 R/W

RES'E'f .J..7
8080

or

RESIN

8224

2

4

23

I

12

9080A
READY
RESET

-

L

f1!ANALOG
OUTPU T

I
. . RESET

44

Out 2

f11.-

MPIO

MEMW

8228

MEMR
124

-

DATA BUS

FIGURE 10. MPIO and MP20 Us'ed With the 8080.
r--1>-t-O+SVDC

ADDRESS IIUS

All

AI330
31
SC/MP

m

An

NWDS

OUT

12
MPIO

48 NHO

, AI4

PACI

DAC 1
OUT

DAC2

DAC2

OUT

OUT

DATA IIUS

FIGURE II. MPIO.and MP20 Used With theSe MP.

DATA BUS

FIGURE 12 MPIO and MP20 Used With the Z-80.

8-22 .

BURR-BROWN®

MP21

IElEI·1

Microprocessor-I nterfaced
8-BIT ANALOG INPUT SYSTEM
"N"" 0(, IN .. U

,.. .... ., . . .

.

rs

____ or_

0 _ .... -.
.c""""~

~~ ~ ~ ~~!:!: ~~~~~! ~

o

(.jlh:h

.<•

...
.... ~

M~'X

"
.'"
.A'. '0

I.... IN 1.0

All

All
AU

AI<

01' I III

MI'X Ill!"! III

14---+---1

.... IS

lAIN HI

CUlltrol
I.UI,I.i.:

~
~

~

_ _ _",J.o}

.t.===='~'~..
~

ill

i{R~~A ~--~-H--'

80

(;AIN AllJllST

) onS!'T "mUST
IAOUl

1t2<"II('IN II

6.151r.

HAll

iN'f"
StatuI

,,0

1:::

II a.1
Analu,.tu.lligilal

III

'14

"
"
"

I~I

( .... Ul·1N 2)

('OMI'.IN

Ui>O

I..·ODverter

'"
"'
'"

FEATURES
-EASY TO USE
PIA is not needed
No external logic needed
No external adjustments
Low or high level analog inputs
Unlimited expansion

- COMPATIBLE WITH:

6800
650X

F·8
- EASY TO PROGRAM
Choice of ways to interface:
Memory·mapped
Interrupt capability

-COMPLETELY SELF·CONTAINED
-LOW COST

- SAVES DEVELOPMENT TIME AND MONEY
International Airport Industrial Part· P.O. Box114OO· TunaR. Arizona 85734- Tel. (602) 746-11" . Twx: 9111-952-11 II . Cable: BBRCORp· Telex: 66-6491

8-23

gauges without external signal amplification.·
All control liiles are fully compatible with the
microprocessor bus and operate.at·low power Sehottky
TTL levels. The M P21 inptidinesp're,~ent 0lle LS TTL
load while li.n outputs cail.:drive up to 201$ TrL loads.

DESCRIPTION

The ~ P~L is a complete analog input sy~tem packaged in
. a 8o.-pin .' quad-in-line package. It is c9rnpletely
. compatible with 6800 microprocessors;', Ii is also
compatible with the6So.X and with the F-S. Th,e MPZl.
contains a high speed 8-bit Ai D'. cQn~erter, !l.ll
.... . . . '
i instrumentation amplifier, an input multiplex/;rthat call
accept up to 16 single-ended signals or8 diffei:ential
signals as well as interface, timing and address' decoding , . : Wheil programming these peripherals, the user treats
logic. The gain and offset are internally laser trimmed so
them as memory. Each analog input channel occupies one
memory location. Any memory reference instruction can
that no external adjustments are required on the ±5V or 0.
be used. Pins A4 to' A!-3 are made available so that the
to +5V input range to' obtain an absolute accuracy of
microperipheral address can be hardwired for any of \024
better than ±o.4% (I LSB). The system can digitize low
level or high level analog signals. The gain of the internal>
possiQle memory\ocation bands. Since these units are
treated as m~mory, a minimum of instructions are needed
instrumentation amplifier can be programmed with a
single external resistorto allow il1put sigrial ranges as low' fo read ,an input .channel. The M P21's versatile memory
mapped operation allows it to be used with or without
as ±Io. mY. This means that the MP21 can be connected
halting' the CPU or in the interrupt mode.
to low "level' sensors' such as thermocouples 'and strain

PROG RAM MIN G

MP~

ANALO(i INPUTS

I BLOCK DIAGRAM

:.&.;:...,

..J..J

0 _ N "" .. .." oD;:
t::t:titt:
tt
o:.cr:::o::,xCl:I¥ 1:.:;:':

"'=

"'''' =
••

zz,.;.,

')()(:::'

."

AO
AI
A2
Al

::>
'"
'"'"'"
;:"''"

;;
'i

ii~

C I - N " " I ..

..".c ....

coo-----0-""1'"\ ..

II'!

!:!: ~ ~ ~!:!:!:'~~~!:!:!:.!~

:!Latch·

A4

A5

77

K6
A7
A8
A9
AIO
All
AI2

Add~ess

7.

Decoder

m

lAIN HI
Control

Control

0-1

to

IA IN La

And

'All
AI.
AI5

MUX OUT
MUX OUT

logic

Logic

(~AIN

~J~~

ADJUST

78

Add....

so_I

'8~

I

,

OHSF.J AIlJUST
I" OUT

R2 (AIlC IN I)

6.2Sk

. 67

RI (AIlC IN 2)

63

COMP.IN

65

OPO

Status

i{
'"

.."

DO
III
D2

8 Bit
Analog.to·llilital
Converter

Dl

D4
05
Db
07

8

'"

8-24

SPECIFICATIONS
Typical at 2SoC unless

otherwi~

MECHANICAL

noted.

ii'

ELECTRICAL

Pin

r +10

'

numbers

:e~n!eor

TRANSFER CHARACTERISTICS
Resolution
Number' of channels
Throughput rate(ll (max)

Bias current 2S"C
0- 70"C
Amplifier output noise
Gain = 100. Rs = soon
Amplifier input offset voltage (max)
Amplifier offset voltage drift
,Amplifier settling time (to .1% FSR)
G ~2
G= 10
G = 50
G = 100
G = 200
CMRR (for differential inputs)(G = 2)

5 ~ lo~n II 10 pF - OFF channel
5 x lo'n II 100 pF - ON channel
100 nA
200 nA
400ILV rms (10 H1. to
±lmV

I()

+

"C

:!(6

50·G)~V.

D'M

±O.4% of FSRI~)
±o.4% of FSR
±o.8% of FSR
±o.8% of FSR
±O.2c;( of FSR

r

I

1IIIIIIIIIIIIIUIIIIIIUUlllillIOIII'

-Lo

MAX

M'N

MAX

2.120

2.180

53.85

55.37

B

1.670

1.720

42.42

43.69

c

.170

.230

4,32

5,84

0

.018

.021

0.46

0.53

F

.035

.050

0.89

1.27

G

.100 BASIC

2.54 BASIC

H

.100 BASIC

2.54 BASIC

K

.150

3.B1

.250

1.500 BASIC

,N

,050 BASIC

.002

.010

NOTE: LEADS IN
TRUE POSITION
WITHIN .OW
(.38mm) R AT
MMCAT
SEATING
PLANE.

MILLIMETERS

M'N

A

L

±0.2% of FSR
±I '2 LSB
±O.lo/c
±O.I% of FSR

MATERIAL:
Ceramic
WEIGHT: 32grams
(1.2 oz) PINS: Pin
material and plating
composition
conform to Method
2003 (solderability)
of M il-Std-883
(except paragraph
3.2) MATING
CONNECfOR:
2350MC (Set of
four 20 pin strips)

6.35

38.1 BASIC
0.05

0.25

127 BASIC

R

_TOO BASIC

2.54 BASIC

T

.200 BASIC

5.088ASIC

u

1.100 BASIC

27.94 BASIC

±O.02%:%.l.V((
±O.002%!%.l.V n

PIN CONNECTIONS

±40 ppm"('
±20 ppm,"C
Guaranteed

!!.!!.

,,,

.
,

Binary or Binary two's complement
All digital inputs are one LSTTL load
S TTL loads or 20 LSTfL loads
AO- A3
DO - D7

POWER REQUIREMENTS

TEMPERATURE RANGE

I

INCHES

200~s

70 dB (DC to 60 Hz)

DIGITAL INPUT/OUTPUT

Rated voltages .
Range for rated accuracy
Supply drain ±15V
+5V

-1~:O'O"'''=

c

.-tt~JJ

All signals are compatible with
. Microprocessor bus
Output coding
.
logic loading
Output drive (DO - D7)
An analog input channel is selected by:
The output data'bus are read into:

41

tt '
N +--K-Gj L
[

20IL s
2Sj...s
SOILS
100""s

STABILITY OVER TEMPERATURE
System accuracy drift!'" (max)
Linearity (max)
Monotonicity (O"C to +70"C)

42

kHl.)

ACCURACY
Throughput accuracy
±5V. ±2.5V. ±1.25V range (maxi·)
O-SV. 0-2.SV range (max)(4)
±so mY range (max)(!»
0-50 mV range (max)tM
Linearity (max)!·)
. Differential, linearity(4)
Quantizing e~ror
Gain error (max )1-11
Offset error(max)I~1
Power s,:!pply sensitivity
±15V
+5V

0 0 00111 III III III III III 0 III III III III III III III

19

i~~ ,. . . . ... ~

()'5V, ()'IOV, ±2.5V, ±5V, ±IOV
2 to 250
G :::: 2 + SOkOl Ru/~)
±23 volts

±6 volts

iBO!

only.
Nllmben

8 bits binary
16 single-ended/8 differential
401LseC/ channel

ANALOG INPUTS
ADC gain ranges
Amplifier gain ran&e
Amplifier gain equation
Max input voltage without damagefl)
Max input voltage for multiplexer
operation
Input impedance

-...

±15V, +5V
4.75 to 5.25 and ±14.5 to ±IS.5V
±30mA
+90mA
O·C to +70·C

,

(2) Ru, is an external resistor connected between pins I and 3.
(3) With power applied.
(4) With no external adjustments.
(5) FSR is Full Scale Range (FSR is IOV for ±5V range).
(6) Gain = 100 with external gain and offset trim.
(7) Includes gain drift. offset drift and linearity-drift.

,,-

1-';"

'"

'"
'"
'" "'"~
"" \11 \. I '''lSI I ,
" \.11 \. I',\HII ,
1'0'

"
"""
""
.."
""
"
""
"
"""
"
~o

25

(I) Includes 3S""sec for mux and amplifier time and 5ILec for ADC conversion time.

~
1,\ (,,\1'1;' -\D.ll ~ I
lA" HI
111.(",\1' "I>Jl "
\11"\ 01 I HI

.15

"1'1111'

'"
"""
U
"
,-"

·\4'

~

"

~

."
'"
'"

"Wi

·\10

'"

W

AI~

"" m
'"
.,"'" Ali

",I)DR IlI("OIli m I

8-25

'"
... ,
"'.' ••
"

~

~

.,."
"
"
"'"

~

...·\,.1'\

"

"ii"hil
ii"!\il
1lI1·\\ 'Ill
.~\

~~.

1)1(,«(1\1
OlIl'II"'HI("t

q

11"(\(<''')

.""'"

'*

.,""

"

""....
,."""
...
.,"
'",

.,
.,

Il~

'"
'"
1l~

,><

nU!I "Rl

'"

j I ~\
("O\1"I'

...," CO\1
tWO
R: (-\1)(" 1,\ II

R11·\lX·I':1
Io\ot I
"~IO I I)
"

Rli 7

~l"'

m-!-""

II
N
CL.

:::!iE

PIN FUNCTfO'N'S
(Optional). Pin I and Pin 3. By connecting
a resistor between pin I and 3 the gain of
the intc;rnal instrumentation amplifi~rcan
be set as follows:
Gain = 2 + SOkO/R",.
. Where ReX! is the gain setting resistor. The
IA is factory adjusted for a gain of 2
without any external resistor.
Important: If a gain. greater than 10 is
required an external capacitor must be
connected from "DELAY" (pin 49) to
+5V. This increases an internal delay to
allow fill' the increased settling time of the
instrumentation amplifier. (See'page 6-224)
Pin 2. This is the positive input of the.
IA IN HI
internal instrumentation amplifier. This
should be connected to pin 4 (MUX OUT
HI) for normal operation.
Pin 4. This is the output' of the analog
MUX
input multiplexer. This is connectec:J to pin
OUT HI
2 (IA IN HI) for differential operation; It is
connected to pin 77 (MUX OUT ~O) and
pin 2 for single-ended input operation.
IN7 -INO
Pins S - 12. The first 8 (of 16) analog inputs
for single-ended operation or the 8 positive
inputs for 8 channel differential input
operation.
Pin \3. Leave open for single-ended input
MUX
ENABLE I operation. Connect to pin 14 (MUX
ENABLE 2) for differential input
operation.
MUX
Pin 14. Connect to pin IS (SIN/DlF) for
ENABLE 2 single-ended 'input operation. Connect to
. pin 13 (MUX ENABLE I) for differential
input operation.
SIN/DIF
Pin IS. Single/ Differentialinput operation
connect to pin 14 (MlJX FNA.BLE 2) for
single-ended operation. Leave open for
'
differential input operation.
AO- A3
Pin 16 - 19. Addfess lines that select one of
16 analog input signals (INO - INIS). 0000
selects channel 0 and nli selects. channel
IS when the correct address is pres~nted to
the MP21. Note: A3 should be connected
to DIG COM for 8 channel differential
input' operation.
A4 - AIS
Address lines. Pins 20, 22, 24,26, Z8, 30, 32,
34,36,38,41, and 43. Connect to A4 -AIS
of the 6800.
Address select lines. Pin 21,23,25,27,29,
31,33,35,37, and 39. By connecting these
lines to DIG COM or +S volts (throu.gh a
IkO resistor) any of 1024 address bands
ca!.!.E.e assigned to the MP21. For example,
if A4 is connected to GND., the corre<;t
(valid) address for A4 is a "I" (> + 2.4V).
IA GAIN
ADJUST

ADDR
DEC

R./W

VMA
~2

RESET

OEtAY
ADJ

+5V
pIG COM

8~26

OUTPUT
SELECT

Pin 40, A,positive PQlse Willl!-ppear When a
valid address appears on the MP21 address
lines and when R(W (pin 42), andff2 (pin
46) andVMA (pin'45) are high. The rising
edge of this pulse strobes the input channel
select information (AO - A3)into a latch. It
can also be used, for external purposes.
Pin 42. Read/Write control line. Connect
to R/W, of 6800.
Pin 44. interrupt output. Connect to IRQ
or NMi of the 6800 if interrupt operation is
desired. When conversion has been
completed. a lO~secpulse (negative) is
generated on thisJine. (Not an open
,collector output.)
Pin 45. Connect to VMA on 6800.
Pin 46. Connect to "2 on 6800.
Pin.47. A "Low" on this line is required to
reset the MP21. Connect to the RESET
input of the 6800.
Pin 48. When the MP21 is "Read" by the
microprocessor via any memory reference
instruction tpe HALT line, will go ......ow..
until conver$ion is complete. If the 1IA['f
line is used to halt the CPU, the 6800 will
halt upon coinpletion of the next
instruction. When the mUltiplexer,
instrument amp, and A/D converter have
completed converting the analog data to a
binary 8 bit code (40~sec with gain';;;; 10)
. the IIAri' line will then return to its'
"High;' state which releases the processor.
The output data can then be read with a
second memory reference instruction .
(Not an open collector output.)
Pin 49. When the MP2! is addret;~ed, ~n
internal delay of approximately 3S~sec is
initiated to allow for multiplexer and
instrumentation amplifier settling time.
When the IA is operated with gain> 10 this
delay must be increased (see Figure 4) to
allow for the increased settling time. of the
IA. This is done by adding a capacitor
between pin 49 and +5V. (See Figure 5;
Pin SO~ +Svolt at 140 rnA maximum,
90 rnA typical.
Pin S1. Digital common. This pin should
be connected to analog common (pin 64) as
close to the MP21 as possible for optimum
performance.
Pin 52. This pin should be connected to
DIG COM to obtain binary data at Do 07. To obtain two's complement data
(bipol~r mode) co/mect pin S2 to +5V
through a I kO resistor.

07- DO
-15V
+15V
COMP
IN

Pin 53 - 60. 8 bit data bus. 3-state low
power Schottky TTL compatible.
Pin 61. -15 volt at 30 mA typical.
Pin 62. + 15 volt at 30 mA typical.

bipolar operation. Leave open for ±5V
input bipolar operation.

Pin 63. Comparator input of 8 bit AID
converter (successive-approximation).
Leave open for unipolar operation or
connect to "BPO" (pin 65) for bipolar
operation.
NOTE: This point is extremely sensitive to
noise. Any connection to this line should
be as short as possible and shielded by
ANA COM or ±15 volt supply patterns.
ANA COM Pin 64. Analog common should be
connected to digital common (pin 51) as
close to the MP21 as possible for optimum
performance.
BPO

Pin 65. AID converter bipolar offset. It
should be connected to ANA COM (pin
64) for unipolar operation or COMP IN
(pin 63) for bipolar operation.

R2

Pin 66. AID converter input resistor.
Connect to IA out (pin 68) for 0 to +5V
input unipolar operation or ±2.5V input

RI

Pin 67. AID converter input resistor.
Connect to IA out for ±5 volt operation.
Connect to Pin 63 for 0 to +2.SV and
±1.25V ranges.

IA OllT

Pin 68. Instrumentation amplifier output.
Connect to RI (pin 67) or R2 (pin 66) for
normal operation.

INS-IN IS
Pin 69-76. Analog inputs S through IS for
RETO-RET7 single-ended operation or analog returns 0
through 7 for differential input operation.
Pin 77. Multiplexer output for
MUX
INS-INI5 or RETO-RET7.
OUTLO
Connect to "MUX OUT HI" (pin 4) and
"IA IN HI" (pin 2) for single-ended input
operation or connect to "IA IN LO" (pin
79) for differen~ial input operation.
Pin 78. 80. Optional instrumentation
OFFSET
amplifier offset adjust (see Figure I).
NULL
IA IN LO

Pin 79. Negative input of instrumentation
amplifier. Connect to ANA COM (pin 64)
for single-ended, input operation or
"MUX OUT LO" (pin 77) for differential
input operation.

4th cycle
LOA

"1

~
~

"2

R~----------t-----------t---~;i=~

__~~-1I~------

VMA
Add
Bus

Data

~New

Bus

~Data

Clock frecj. = I Mhz
!HT = 200ns min before fldling edge of,,1.
tHAL T = 40_c (max)
tON = 70nsec (max)
tAD = 30nsec (max)

MP21 Timing Diagram (usiqg HALT to stop microprocessor during conversion).

8-27

, ,II
R/W'

--------'--111' ",-'...:.----"---'-

VMA

, OP. Code +2

Add
BUI

X_~X

Datil
Bus

I'Per, Add

>q, X
I

QpCode

>C

~~=><"rer.Add

~New

~

~l

~'Data

Add
Dec

MP21 Timing Diagram (without stopping microprocessor during conversion).
'13

Last
cycle

1st cycle

1st cycle

[NT

LDA

Data
Bus

~
Data

Add

--------------ll~l---------foll~--~

Dec

tpcs = 200ns min before falling edge of next to last "2 clock pulse of i~structio~

tiNT; 121'sec (max)

MP21 Timing Diagram (using Interrupt).

OPERATING INSTRUCTIONS
PROGRAMMING
The MP21 is easily programmed since it is treated as
memory. It uses any memory reference instruction that
can read data.
The MP21 can be operated in four modes:
I) Start data conversion, halting the microprocessor for
the 4Ollsec* conversion time. This is the simplest
approach. It should be used if 40Ilsec of software time is
av~ilable. (MP21's iiAIT line, pin 48, connected to the
6800's HALT input, pin 2.)
Example:

LOA XXXX starts conversion of channel at
location XXXX
NOP
CPU halts at the end of this
instruction
LOA XXXX transfers data from channel at
location XXXX to accumulator

2} Start data conversion, then go to a different part of the
program. When 4Ollsec* or more have passed, come back

to the MP21. to read the converted data. This mode uses
the least amount of time; it should be used when software
time is at a minimum. (MP2I's HALT line, pin 48, is
open.)
Example:

LOA XXXX starts conversion of the channel
at location XXXX
:

{at least 40llsec* of software here

LOA XXXX transfers data from channel at
location XXXX to accumulator :
* The conversion time of the MP21 may be between 40
and 200 microseconds depending upon the gain of the
internal instrumentation amplifier. See Figure 4.
3} Start data conversion, then go to a 'different part of the
program. Periodically, check the MP21 's HALT li\le (pin
48) to deteCt if conversion is complete. This mode should

8-28

ADDRESS SELECTION

be used if a positive check of a complete conversion is
needed. (MP2I's HAi:Tline, pin 48, could be interfaced
to a 6820 PIA for instance.)

Example:

The base address of the MP21 is set by inputs A4through
ATJ. Address lines A4 through A 13 respond to the
inverse of inputs A4 through Al3. For instance, if A6 is
grounded, A6 will respond to a "High" input. AI4 and
A 15 are internally connected to respond to a"High"input.

LOA $XXXX starts conversion of channel at
location XXXX
:

{other software

ANALOG INPUT RANGE SELECTION
The MP21 may be set for any range between ±5V and
±IO mY. Table I shows the pin connections for the
various high level ranges available.

lOA $YYYY1lOOP to determine if conversion
is complete
AA ANOA $ZZ YYYY is location of 6820 PIA
with HALT informa tion
ZZ is mask used for determining if end of conversion bit
is set
BEQAA
LOA $XXXX transfers data from channel at
location XXXX to ac.cumulator

MP21 Input
Range

±5V
±2.5V
±1.25V
0- 5V
0- 2.5V

4) Start conversion, then go to a different part of the
program. The MP21 will interrupt at the end of
conversion. The interrupt mode is very useful when the
MP2l is at high gains with convers':m times longer than
4O!-,sec, see Figure 4.(MP2I's INT line, pin 44, connected
to the 6800's IRQ line, pin 4.)
Example:

0100
0100 CE 92EO
0103 5F
0104 A600
0106 0101
0107 A600
0109 FF 0137
010C F70139
OIOF B7013B
0112 CE 013B
0115 BD EOBI'
0118 860D
OIIA BDEIDI
01lD860A
0111' BDEIDI
0122 1'60139
0125 FE 0137
0128 5C
0129 CI,IO

NAM
MP21
OUT2H EQU
$EOBF
OUTEn: EQU
$E 1111
INEEE
EQU
$EIAC
ORC
$100
START LlJX
#$92EO
CLR B
CONY
LlJA A.X
NOP
LDA A,'X
STX
STREI
STA B STRE2
STA A STRE3
LDX
#STRE3
JSR
OUT2H
LDA A #$OD
JSR
OUTEEE
LDAA #$OA
JSR
OUTEEE
l.DA B STRE2
l.DX
STREI
INC II
CMPll #$10

2
2
2
2
2

±IOV
±5V
±2.5V
0- 10V
0- 5V

Pin Connections
65 to 63; 66 open; 67 to 68
67 open
63 to 67
67 open
63 to 67

65 10 63; 66 to 68;
65 to 63; 66 to 68;
65 to 64; 66 to 68;
65 to 64; 66 to 68;

The internal instrumentation amplifier is factory set for a
gain of 2. This gain can be increased to 250 by adding an N
external resistor (R",) between pins I and 3. R"t should a...
be a stable resistor (10 ppmtc) since this temperature :liE
drift will add to the accuracy temperature coefficient. The
gain of the amplifier can be determined by this formula:
Gain = 2 + 50kO . With pins I and 3 open, the gain is 2.
R ext

Base address for MP21

Since the amplifier input offset will be multiplied by the
amplifier gain, an offset adjust may be required at high
gains (see Figure Ib).

Clear Counter
Initia~e

Conversion

Read Data
Store Index Reg.
Store Counter
Store Data

-ISVDC

Print Data
MP21

Next Channel
Have 16 channels been
read?

2704
08
7E 0104
BDEIAC STOP

BEQ
INX
JMP
JSR

STOP

Yes

CONY
INEEE

Do another conversion

0134
0137
0139
013A

7E 0100
0002
0001,
0001

JMP
RMB
RMB
RMB
END

START
2
I
I

Input character
to begin again

This program assumes that the system is under the
control of the MIK BUG monitor, Revision ~. To read
and print the value of all 16 channels again, input any
character from the keyboard.

(a)

SOkn
C=2+--R J + R2
R2 is fine adjust

(b)

FIGURE J. (a) MP21 Gain Adjust; (b) Offset Adjust

0128
012D
012E
0131

STREI
STRE2
STRE3

ADC Range

Table l. Analog Input Range Pin Connections
The M P21 may be set to output data with straight binary
coding (pin 52 grounded) or two's complement coding
(pin 52 to +5VDC through a I kO resistor). Straight
binary coding is typically used with unipolar input ranges
and two's complement coding with bipolar input ranges.
Table II describes the coding.

MP21 used with a 6800. MP2l base address
92EO. Processor halted operation. Read and
Pdn t the value of all 16 input channels and
then stop.

EOBF
1'101
EIAC

Gain

SINGLE-ENDED VS. DIFFERENTIAL INPUTS
The MP21 analog inputs may be connected as single. ended, differential or pseudo-differential. Single-ended
operation may be used for high level (over one volt full
scale) signals in low noise environments (Figure 3).
Differential operation will reject common-mode noise
appearing on both inputs (Figure 2). It should be used in
noisy environments or with any low level signal (less ~han
one volt). In the pseudo-differential mode, the MP21 is

8-29

,
ANALOQ'INPUT
o to +SV

DIGITAL OUTPUT
Straight Binary Code

Two's Complement Code

±SV

11111111 (FF,,)

01 U 1111

1000 0000 (80,,)

0000 0000 (00,,)

Mid..scale

0000 0000 (00,,)

1000 0000 (80,,)

(7F,~)

y

±IOmV

+4.961 V

+4.980V

+9.92mV

O.OOOV.

2.500V

O.OOOV

-Full Scale

-S.OOOV

O.OOOV

-1O.00mV

One LSB

39mV

19.5mV

7K"V

+Full Scale

,

.

TABLE II. Analog Input Values
connected as for the single-ended mode in Figure 3 except
the IA low input, pin 79, is not grounded. Pin 79 is
connected to an external ground that is common to all of
the analog inputs. In cases with a noisy remote ground
where little noise will be picked up between sensor and
MP21, the pseudo-differential mode may be used.
Analog
Inputs'
+

time 'constant can be calculated with the formula: T = (R,
+ Ron + Ron*)Co. ForR,=lkfiandCo=SOpF, T=(I.S+ I)
kfi x SOpF = 12Sns(single-ended operation). ThusO.7S#,s
is needed to settle to ±o.!%. For high input impedances
requiring more than 10 microseconds for multiplexer
settling time,' the required delay time may be calculated
with this formula: T ~ ='/T2 mux + T\A, where T mux is the
settling time of the multiplexer and T. A is the settling time
of the instrumentation amplifier as shown in Figure 4. If
the source bandwidth can be limited, high impedance
sources may be accurately handled by placing a large
capacitance across the multiplexer input. An analysis of
such a circuit shows that a capacitor ofO.S#,F is sufficient.
For such a capacitance the mUltiplexer time constant
becomes SOns.

MP21

I! Channel
Differential
Analog
Multiplexer

,
Pin Connections
IS Open
13 to 14
4 to 2
77 to 79
19 to DIG COM

4

2

!

Z

I---'o---o.:....t
77 79

3 Bit Channel Select

250

FIGURE 2. Differential Input Connections
~

.;

Analog
Inputs

~

200

~

0

MP21

II"

"

•
Pin Connections
IS to 14
13 Open
77 to' 4
4 Bit Channel Select
4to 2
79 to ANA COM

I

150

::;

10

1>1

~

lL '"

1=

i5

......
'"'"
:s

FIGURE 3. Single-ended Input Connections

V

/

0
-l

V

5:V

100

50

0

200

ISO

250

GAIN (V/V)

DELAY TIMING
A delay time between channel selection and start of
conversion is built into the MP21 to allow the analog
multiplexer and instrumentation amplifier (I A) time to
settle before starting the AI D converter. As the gain of
the amplifier is increased, the settling time required
increases. The factory set delay time (3S#,sec) is sufficient
for gains of up to 10. At higher gains, a Capacitor must be
added from pin 49 to the +S VDC supply to increase the
delay time. Figure 4 shows the settling time of the MP21
vs. gain. Figure S shows the value of capacitance required
to increase. the delay.
The only external factor, other than .gain, that affects the
MP21 settling time is the impedance of the source
connected to a channel. Figure 6 shows a circuit model of
an "ON" channel.
The signal at the output of the multiplexer must be
allowed to settle to ±o.I% (six time constants) to
maintain the full accuracy of the system. The multiplexer

FiGURE 4. Typicai iA Settiing Time vs. Gain
(Output Settling to ±o.1 %).
300

,.....

L

~

0

II"

200

/'"

2

.>1

!

>-

<

-l

1>1

Q

100
80
50
39
35

V

-/

/

(i

o 0"0

on"
-..,

1000 2000 3000

4000

5000

CAPACITOR VALUE (Picofarads)

, FIGURE S. Typical Delay Time vs. Capacitor Value.

8-30

,

source~

Source
Resistance

RS

described. Applications using the M P21 with other
processors are shown in Figure 10 and II.

+suppiy

MP21

I.Skll

~

1('

RON
~~
SUPPlY
I SkU
RON

r

.

(

o

'Supply

Co = SOpF for single·ended mode
Co:: 12.SpF for differential mode
RON* ';:;: 0 for single-ended' mode

FIGURE 6. "ON" Channel Circuit Model.

INPUT OVERVOLTAGE PROTECTION
As shown in Figure 6, the analog inputs have reverse
biased diode circuits which protect from damage by
overvoltage (such as static). It is still advisable to take
precautions against static discharge. The same circuitry
protects the inputs from steady-state overvoltage damage
during operation. The MP2J's o\c!'\oltage protection
can be increased by adding series resistors at each input.
The input resistance must limit the current flowing
through the input protection diodes to lOrnA. For
instance, if 15k!} resistors are added to each input, the
protection is increased· to 165V (16.5kn x lOrnA).
Increased input resistance will, of course. increase the
amount of time necessary for the multiplexer to settle as
described in the previous section and increase the offset
voltage by the drop caused when the bias current passes
through this resistance.
.
.

RESET
It is important to reset the MP2l on startup with a low
pulse on the REm line (pin 47). The reset pulse clears
an internal flip-flop and guarantees that the next read
instruction to the unit will.start a conversion. Thereafter,
every other read instruction will initiate a conversion as
previously descri bed.

CONVERTER INITIALIZATION
On power-up, the state of the ADC internal circuitry is
indeterminate. One conversion cycle is requireq to initialize the converter after power is applied.

HIGHER SPEED OPERATION
The MP21's iniernal instrumentation amplifier requires
35 microseconds to allow for settling time. Ifthis internal
amplifier is not used., substantial improvements in
throughput rate can be obtained. This is easily done since
neither the inputs nor the (lutput of the instrument
amplifier are internally connected. For instance, BurrBrown's 3622 high speed instrument amplifier (for
differential inputs) or 3505J high speed op amp (for
single-ended inpuh) may ne used. with a 'ettling time (If
I"'t" ror gains or up to 100. rhe total delay time
neec"ary may ne .:akulated ny this lormula:

NON 6800 OPERATION
The circuitry used to enable the 3-state output lines (D7DO) and begin conversion on the M P21 can ne connected
in such a way as to meet a wide \anety oj timing
requirements. The outpui is enabled only when a valid
address appears on the addre~s input> and when VMA
(pin 45), R,W (pin ,.2). and 02 (pin 46) are high. Any
other combination of digital signals on these lines will
result in 01 - DO neing in a high i.mpedance state (sec
Figure 7).
All that is required to use the MP21 with a system other
than a 6800. is that these signals be brought to their active
levels. When this occurs. operation begins as previously

where T Ml'X is the settling time of the multiplexer (750ns)
and T'A is the settling time of the instrument amplifier:
For a TI.' of l/Lsec we have TI" = 1.3/Lsec. Using 3"sec for
tht' delav time to allow for unit to unit variation, the total
throu'gh-put iime will be 8/Lsec (including 5 microseconds
for ADC conversion time) or 125 kHz. A resistor between
pin 49 and +5 VDC will reduce the delay time from the
factory set value of 35 microseconds (see Figure 8).

2S
To ADDR DEC

ADDR DEC

40

~.

'""

l.()~·ic

tl7·DO

8 20

ENA8l~,

~

5 15

E

,.

RtW

«

..J

~
VMA

10

I

~

V

~

~I
,II

O~~1

00

200

300

400

SOO

REStSTOR VALUE (kilohm,)

FIGURE 7. Output Enable Circuitry

FIGURE 8. Typical Resistor Value to Decrease Delay
Time.

8-31

CALIBRATION
, Tl1is prQgrama~sumes th~t the pr9gram is ,,[\!Jet: control
; of the M1>torola EXORciser, EXbug monitor_ If the
ine' MP21 is ' laser trimmed at t,he factory to ±o.4%
; Mikbug monitor is aVllilable, th,e following printout
accuracy when using the ±SV, ±2.SV, ±1.2SV, Oto+2.SV
, software may be added by, using it to replace all codes
or 0 to +SV ranges. If one of these ranges is used, no
starting from location OilS. hi addition the references
adjustments are required. For other ranges (G';' 2),both
count at 0104 and OilS must ~ replaced wi~h2E. '
the gain and 'offset must be adjusted. Figure I shows the
adjustment connections. The offset adjustment should be
made such that the transition to minus full scale output
OUT 2H EQU SEO BF
, OUT EEE'EQU SEt 01
(0000 0001 to 0000 0000 for' straight binary) occurs with
an input of negative full scale plus 1/2 LSB. One least
0118 F7
STA B STRO
significant bit (LSB) is equal to the fUI~scale range (FSR)
01
2E
divided by X' where n is the number of bits ofthe AID
CE
OIlB
LOX #STRO
converter. For the MP21, I LSBis FSR/2' FSR/2S6.
01
The gain adjustment should be made such that the ,
2E
OIlE
BD JSR OUT2H 'Print no. of true,conversions.
transition to a full scale output (1111 III 0 to 1111 fill
EjO
for straight binary) occurs' with ,an input of positive full
BF
scale less 112 LSB.'Since 12S states are used for negative
0121
86
LDAA #00
00
inputs and one state is ,used for zero, only 127 states are
BD
JSR
OUTEEE
0123
available for the remaining' positive range. Thus the
EI
positive full scale voltage is I LSB less than nominal full
'01
012E
RMB I
COUNT
scale. Fora range of ±SO mV,I LSB= IOOmV/2S6=0.39
012F
RMB 1
STRO
mY. The gain adjustment should be made at +49.6ImV*
END
-(0.5)(0.39 mV) = +49.42 mY. The offset adjustment
This 'program may be used for .both offset and gain
should be made at -SOmV + (0.S)(0.39mV) = -49.S0 mY.
calibration. The system offset should be adjusted first,
Table III shows offset and gain calibration values for
fQllowed by the gain adjustment .
typical ranges.
• (SOmV ~ I LSB = 49.6ImV)

to

=

MP21

Instrument

IDputR.....

AmpO.in

AOC RanI!"

±SV
010 +SV
±2.SV
010 +2.SV
±1.2SV
0- SOmv
±2SmV
O'2SmV

2
2
2
2
2
100
100
200

±IOV
Uta +IOV
±SV
o to+SV
±2.SV
o to+SV
±2.SV
Oto+SV

Calibration Values
Offset
Gain
-4.9SOV,
+9,8mV
-2.490V
+4.9mV
-1.24SV
+98I'V
-24.9mV
'+491'V

+4.941 V
+4.97 IV
+2.471 V
+2.48SV
+1.23S
+49.7mV
+7.4.7mV'
+24.9mV

Table III. Calibration Values.
rhe following program may be used to adjust gai~ and
offset.
ORG $100
LDAA #$64
86
START 0100
0102

CONV

0105
0106
0107
OIOA
OIOB
OIOE
0110

AA

0112
0113

64

B7
01
lA
4F
SF
B6

92
EO
01
B6
92
EO
81
REF
26
01
SC
7A

STA A COUNT
Clear Accumulators.
CLRA
CLRB
LOA A $92 EO Begin Conversion.

NOP
LDAA $92 EO Read Data.
CMPA#REF

IS Data = REF?

BNEAA

No. Do not count.

INCB
DEC COUNT

Yes. 00 count.
Hav:e 100 conversions
been done.

0116
0118
COUNT OllA

01
lA
26
EF
20
E6

BNE CONY

No. Do another.

BRA START

Y.s. Begin neKt run.

RMB
END

The address of channel zero is assumed to be 92EO. If it is
not, the LDA instructions should reflect that change. The
reference valueS for Ref assume straight binary coding,
Offset Ref == 00 and Gain Full Scale Ref FE For two's
complement binary coding, OffsetRCC;'" SO and Gain Full
Scale Ref = 7E

=

A 100;0 command to Exbug will begin program
exe\:Ution. For Mikbug the ,user's stack. must be loaded
with "11ft and then a G command executed to begin
program execution. For those applications not using
the printer portion of the program insert a breakPoint
via a IIS;V command. After 100 convenionshave been
made, the value (in hex) of the B accUmulator will be
printed if using Mikbug program. This value rl:pr~ents
the number of times the'data read from the board was
"4ulli to "REF" (00 ior onset; FF for gain). '
Calibration is performed by connecting a voltage source
capable of 0.01% accuracy to input channel zero (this
could also be a DC voltage source of less absolute
accuracy whose ~utput is monitored by a 0.0 I % DVM).
The offset adjustment is made first by using the
appropriate offset calibration voltage and REF value.
Run the calibration program and adjust the offset
potentiometer until the B 'register cOntains a value
between IEI6 and'4616 (3010 and 7010).
To perform the gain adjustment, change the data labeled
~REF' ,in the calibration program to its correct gain
value. Set the input voltage to the correct value as shown
in Figure S and adjust the gain potentiometer,in the same
manner as described for offset.

If EXbug is used the program will halt and the B
, accumulator can be examined from the program register
display produced by the breakpoint.
"

8-32

THERMOCOUPLE TEMPERATURE
ACQUISITION

remote sensor should be earth grounded to prevent
common-mode voltages from exceeding the ±5 volt range
I)f the multiplexer. If the sensor is earth grounded, the
I MO resistors are not required. The I MO resistors do
not enter into an error calculation for input errors
because the low resistance of the sensor shorts any
differential voltage that might be caused by the offset
(difference current) of the amplifier. Offset or difference
current is merely the difference between the bias current
of each input. See the overvoltage protection section for a
discussion of the effects of the IOkO resistors in the input
filter. The I MO resistors could have been put on the
output side of the mUltiplexer eliminating the need for
repeating them for each input; however, this would have
loaded the IOkO resistors of the filter causing a possi ble
I% error for static conditions.
To complete a thermocouple system it is necessary to
terminate all th~rmocouple wire pairs at an isothermal
box or connector strip of some type. An ordinary barrier
strip may be monitored to allow the observed
thermocouple emf to be cold junction compensated.
Figure 9 shows an excellent circuit for this purpose. Its
output is connected to one of the input channels to supply
ambient temperature data to the system computer. Its
output sensitivity is approximately 2 mY j"c.

Thermocouples are often used as temperature sensors for
process control systems. Thermocouples are
characterized by temperature coefficients of 10 to
70", Y
and operating ranges of minus hundreds to plus
thousands of degrees centrigrade. When the MP21 is
operated with an instrumentation amplifier gain of 100 or
more, it may be connected directly to these devices.
The wire runs from thermocouple to measuring device
often pick up large common-mode noise signals of 60 Hz
or higher frequencies. When the M P21 is used as an eight
channel differential input' system, the high commonmode rejection of the instrument amplifier will reject
common-mode noise. To minimize differential mode
noise, the signal wire should be twisted and if possible
shielded. As a rule, an unshielded twisted pair is better
than a coax, and a shielded, twisted pair is still better. In
applications where these wiring practices cannot always
be observed, a differential RC filter may be used. Figure 9
shows such a system.
The 10 kO resistors and IO",F capacitor provide low pass
filtering (f, = 0.8 Hz) while the optional I MO resistors
supply bias current to the instrumentation amplifier. The

rC

MP21
10k

CHN

IO"F

r--H-.....t-<)-o--I

10k

CHN RTN

...

IMS1

.

Cable Run

'sothermal
Barrier Strip

___ -, "

.,

Optional --'-H...Z....L-O-W-...
Bias Current
Pass Filter
Supply Resistors
+15
+15
20k

200k
BB3500B

-Rd

Rc

E

Ra

kT

="RC""+"Rd (I + Rb) q In 10

E { dE
Rd
Ra K
(d'f)=-Rc+Rd (I+"Rb)qln 10

ilS V

Rd
-

T = OK. k/q = 8.67 x 10- 5

Dual monolithic transistor pair (National toM 114)
Mounted Near 'sothermal
Barrier Strip -

FIGURE 9. Thermocouple Input System Using MP21. -

8-33

+SV

-15

+5

PIN CONNECTION. SUMMARY,
.,
Sing)e-ended
Multiplel'er .
Differential
Multiplexer
Amplifier

Input Range
±5V
±2.5V
±1.25V
0-5V
0- 2.5V

. JUMPER
4 to Z; 4 to 77; 79 to 64;
Address Bus (AO- A15)
15 to 14; 13 open
4 to 2; 77 to 79;13 to 14;
Address Select (A4 - A 13)
15 open '
Control Bus
I and 3 open for G = 2;
R;" between I, and 3 for G '12,

65
66
65
65
65

to
to
to
to
to

63;
63;
63;
64;
64;

66
66
66
66
66

open; 67
to 68; 67
to 68; 63
to 68; 67
to 68; 63

to 68
open
to 67
open
to 67

52 to 51 for binary; 52 to 50*
for two's complement.
* Through a I kH resistor.
.'

Output Coding

Data Bus (DO

~

D7)

JUMPE~

Connect to 6800'saddress bus
AO - AI5
;
Connect to +5V* or Ground
"

42 to 6800's R/W (pin 39)
44 optionally to 6800'5 IRQ
(pin 4)
45 .to 61100's VMA (pin 5)
46 to 6800's gz (pin 37)
47 to 6800's RESET (pin 40)
,48 to 6800'sHi\['f(pin2) open
for operation without
halting CPU.
Connect to 6800'5 data bus.

MICROPROCESSOR INTERCONNECTION
The following diagrams show interconnections of the MP21 {described in this data sheet) and
also of Burr-Brown's MPIO and MPII analog output ,microperipherals' (PDS-363) with
Motorola's 6800, MOS Technology's 650X, and FairchHd's F-8. Although Burr-Brown's
analog m.icroperipherals are optimized for 8 bit microproCessors. with the addition of a few
external component,s, they can be used with any 4 through 16 bit microprocessors.

CPU Read
Steps~

,'RAM WRITE

For Operation of MP21.with F·8

I. Start conversion by addressing and reading MP21.
2. Initialize Timer

3. Use timer initialized interrupt to read data.

FIGURE 10. MP21 and MPII Used With the 6800
or 650X.

FIGURE I L MP21 and MPIO Used With the F-8.

8-34

BURR-BROWN

MP22BG

IElElI

Microprocessor-I nterfaced
12-BIT DATA ACQUISITION SYSTEM
FEATURES

DESCRIPTION

• INTERFACES WITH 8080A. 8048. Z·80. SC/MP
MICROPROCESSOR WITHOUT ADDITIONAL
COMPONENTS

A complete analog input system. the M P22BG
interfaces to many microprocessors without
additional external components. Contained in an 80·
pin quad·in·line package. it includes a 12·hit CMOS
A D converter. instrumentation amplifier. input
multiplexer that accepts up to 16 single·ended signals
or 8 differential signals. an address decoder. and
control logic. Logic to generate interrupt. halt. and
direct memory access request signals is also included.

• INTERFACES WITH 6800. 650X. F8. 8085
MICROPROCESSORS WITH MINIMAL
EXTERNAL LOGIC
• COMPATIBLE WITH PDP·8. PDP·ll. NOVA. ECLlPS.E
MINICOMPUTERS
• EASY TO PROGRAM

The system can digitize low-level or high·level analog
signals. Gain of the internal instrumentation
amplifier can be programmed with a single external
resistor allowing input ranges as low as ±IOmV.

One Instruction acquires data as a memory mapped
device
Two instructions acquire data as an accumulator I/O
device

MULTIPLEXER
SINGLE-ENDED/
DIFFERENTIAL

pP
ADDRESS
BUS
GAIN
~--oADJUST

JlP CONTROL BUS

A/D
CONVERTER

liP DATA BUS

International Airport Industrial Park - P.O. 80x 11400 - Tucson. Arizona 85734, Tel. (602) 746-1111 - Twx: 910-952-1111 - Cable: 88RCORP - Telex: 66-6491

8-35

ANALOG MULTIPLEXERS
Two !I-channel CMOS alJalog multiplexers are used on
the input which permits s¢lection of 16 single-ended or 8
differential inputs. A pseudo 16 channel differential mode
of operation can also be achieved by connecting the ..
amplifier's inverting input to a common,'remote signal
ground. Channels are addressed by the ad(lress decod,er
which is connected directly to the microprocessor address'
bus. The number of input channels can be. expanded
without limit using external multiplexers.

The MP22's address decOder is nllide up of exclusive-or
gates which have open c,onector outputs so that the
.outputs of several gates may be ~onnel:ted together
,through a single pull-up resistor... The .. address of the
. M,P22 is determined by wifing the address s.elect .lines tl)
either ground or +S volts. Only when all of the address
lim,S (A inputs) are in opposite states of their respective
address select lines (A inputs) will the address decoder
output go high.
DELAVTIMER
A time delay between channel selection and start of
.conversion is built into the MP22. This allows th~ analog
multiplexer and the instrumentation amplifier time to
settle before starting the A/D converter. As amplifier
gain increases, settling time increases. See Figure 8.
Factory set delay time( IS~sec)is suffiCient for gains from
'unity to SO. At higher gains a capacitor must be added
between pins 49 and SO to increase delay. Figure 7
indicates the capacitance required to increase delay time.

INSTRUMENTATION AMPLIFIER
The instrumentation amplifier is a low drift. differential
amplifier featuring high speed at gains above unity and
gain programming with an external resistor. Gain may be
selected from unity to SOO.
ANALOG-TO-DIGITAL CONVERTER
The l2-bit AID converter is a CMOS, successive
approximation device with 4S~sec conversion time and
three-state outputs. Laser-trimmed, compatible thin-film
networks are used to assure linearity and stability over
wide temperature ranges.

CONTROL LOGIC
The control logic generates signals to halt or interrupt the
CPU while conversion takes place and to signal the CPU
when conversion is complete and data can be read.
Enable signals are also generated to gate the data onto the
data bus.

ADDRESS DECODER
Typical microprocessor systems have several thousand
. memory locations, teletype or CRT terminals, and
possibly several MP22s. By using 12 address· lines the
microprocessor can communicate with as many as 2'2. or
4096 memory locations or peripheral devices, with each
having its own unique address.

~

!!!

4420

I

:::
1.721

Q

~

~::

" lA'cue."

I

Ai ..

I

021
Xi 31

m ••
m ..

!!!~
Ii

~

g

.

Q.

~

......

Logic

I

~~
~~
~

J

1

Control

..........

,..

8 Ch.nnel
A.....
Mul",..••r

An.log
Muiliplex.r

r---C--

Add .....

Decoder

...

~~~

a Channa'

A1134

Aia
,.,..,

~

.....

.. f:~:

..

~

REFERENCE
The internal voltage reference of the .MP22 has been
optimized for stable outputs with respect to temperature.
Output current up to 2mA can be drawn externally from
the reference outputs.

"I,.,~

~

1_

~

46
lmIR44

RiiET39

,

"0

AO,16

Amp

I

liS

DRQ43

..

r~ n~~

~

Control
Logic

D8IN"
INT ..
READY 4'

~

-

•
To

FIGURE I. Block Diagram

.,0

.......

DELAY

0

.7

AQCI~

8-36

-0 50 LOGIC SUPPLY
51, DIGITAL COM

-0 t4 ANALOG COM

88IA OUT

71 IA IN LO

52 STAAT CONY

An.1og

.,

37 +MUX SUP OUT

38 • MUX SUP OUT

4. DELAY OUT·
CONVERT COMMAND

ADC

•

+R.t

Dlglta.
Comert.,

D'R1I7iii'fA

~Ycc

12 +Vcc

77 MUX OUT LOW
2 IA IN HltMUX OUT HI
1 IA GAIN SELECT
3 IA GAIN SELECT
71 OFFSET NULL

} Add_.
DoIoy

61

QAINAD.lUST

..

0

NIC

..
0

REF OUT

..
0

8.0

MICROPROCESSOR CONNECTION DIAGRAMS
A"

} Address
Select

CS

D"

ReSet

Reset

Au;

A"

MP22

D,

D"F===D;:;=:ata:=;;B:=u",s·:===::1

Ready

Au

A7i

A,

A;;MP22
X;

D - t - - - - - - - -....

+5V

A,
A;

Aw

~1

Data Bus·

8080A

A.
A,

A,

Address Bus

1;0 Select

t'R",E:;;S",I;.;N_... rre;e;

SOMOA t-_R_e_ad-,Y-t

~==-tReady

Reset

RDYIN

DBIN

MEMR

System
Reset

LHLD

Will initialize conve~sion and
store data in HL registers

MP22 Base Address;

• 10k pull down resistors required.

MP22 Base Address;

IN

FIGURE 2. MP22 Used with 8080 Halt Mode
Memory Mapped

AO ; 0 A 1·- A4 channel select
AS - A7 1/0 select initializes
conversion and reads 8 LSD's
Store 8 LSB's in REG C
AO ; I AS - A7 I/O select
reads 4 MS8's

MOVC,A
IN
MP22 Base Address;
• 10k pull down resistors required.

MEMW
CS;t-----IVMA

R/W

FIGURE 4. MP22 Used with 8080 Halt Mode
Accumulator I/O

6800

Address Bus
Au

All

Iirnm"

CS
MP22
Ready QEMW

Z-80
WAIT
On

Data

AI!

Optional
4 Bit Address
Decoder
74LSI36

Do

..._ _ _ _....D....
7
Bus. 07

OBIN

Program to READ and STORE 16 channels of data using Block
Transfer Instruction.
AO; I
DO; 0

STAA
Destination Address
NOP
LDA

Destination Address

LO HL, NN
NN points t6 channel 0 MP22
LO DE, MM
MM pOints to the first location of the destination
LD BC, OIOOH byte counter (2 bytes/channel x 16); 32 10
LOI
Load and increment
Total Execution Time with tcy = .41J.8 and conversion rate 40~s is
T = 3 (41'S) + 16 (6..4 + 40I's); 754.4",.

Starts cQnversion
Halt

AO; 0

8 LS B 's, Resets M P2 2

AO; I

4 MSB's

LDA

Destination Address

• 10k pull down resistors required.

• 10k pull down resistors required .

FIGURE 3. MP22 Used with 6800

FIGURE 5. MP22 Used with Z-80 (Halt Mode)

DELAY TIME COMPONENT
SELECTION CURVES

TYPICAL PERFORMANCE
CURVES

2

r:

1

1/~

FIGURE 6. Typical Resistor S
6
Value to Decrease Delay. Time.~

;:4 I
:s 211
'"Q

V

FIGURE S. Differential

Amplifier Settling Time
vsGain

II

0 0 33 66 100 133 166 200
RESISTOR VALUE (kilohms)

120
,",100

0

FIGURE 7. Typical Dela}
Time vs Capacitor Value

l/

lw
):'40

:s
'"c

. /I '

/
FIGURE 9. Differential
Amplifier Common-mode
Rejection vs Gain

/

010'"

o
0.0017 .0033 .005 .0067.0083.01
CAPACITOR VALUE (microfarads)

8-37

ELECTRICAL SPECIFICATtONS , :'
MP22BO

'"

,MODEL

Min

, '.:

TRANSFER CHARACTERISTICS

12

Reso,lutionlll

Number of Channels
Throughput Rate'll atG =
ANALOG INPUTS
ADC Gain Ranges
Bipohir(·ll
Unipolar'''
Amplifier Gain Range
(jaj~

I

,

40

, Typ

J

'I

I
12
16 Single;Ended/8 Differential
45

Max

Units

12

Bits

55

ps/Channel

,-

(I

Equation

Input Voltage Without Damage
Input Voltage for Multiplexer Operation
Input Impedance
Off Channel
On Channel
Bias Current
25"C
O"C to +70"C
Aml'lifierOutl'ut :-'oly the offset
(pifference current) of the amplifier. Offset or difference
current is merely the difference between the bias currents
of the two inputs. The I MO resistors could have been put
on the output side of the multiplexer eliminating the need
for repeating them for each input; however, this would
have loaded the IOkO resistors of the filter causing a
possible I % error for static conditions.

Thermocouples are often used as temperature sensors for
process control systems. Thermocouples are
characterized by' temperature coeffiCients of '10 to
70p. V/"C'ana Operating rangeS 'of minus hundreds,to plus
thousands of degrees centrigrade. When the MP22 is
operated with an instrumentation amplifiergain of 100 or
more;'it may be conIiected directly to fhese·devices.
The wire runs from thermocouple to measuring device
often pick up large common-mode noise signals of 60 Hz
or higher frequencies. When ~he MP22 is used as an eight
channel diffe'r~nfiai input' system, the high commonmode· rejection' (jf the instrument amplifier will reject
common~mode noise. To minimize differential mode
noise; 'the' signal· wire should be twisted and if possible
shielded; As Ii rule, an unshielded twisted Pllir is better
than a coax,anda shielded, twisted pair is still better; In
applications where these wiring practices cannot always
be.obsetved,:,a differential RCfilter may be used. Figure
H'shows such'a system.
The 10 ItO reglstors and IOp.F capacitor provide low pass
,_fit~$!ting (ff:::'. O"~ H,z) while the ~ptio~al I MO resistory
: supply bias current to the instrumentation amplifier. The

To complete a thermocouple system it is necessary to·
terminate all thermocouple wire pairs at an isothermal
box or connector strip of some type. An ordinary barrier
strip may be monitored to allow the observed
thermocouple emf to be cold junction compensated.
Figure II shows an.excellent circuit for this purpose. Its
out put is connected to one of the input channels to supply
ambient temperature data to the system computer. Its
output'Sensiti'!ity is approximately 2 rh V

rC.

CHN

'Ok

..

",

..

Cable Run

.'sothermal
Barrie{ Stdp

..,;;..,-~

-~

_ _ _ _..
,

Op~ional
Bias Ourrent
Supply':Resistors

,

;1"

lH; Low

his F'Uter

j'

+IS~

--1-15

10k

200k
BB3S00B

Rc:-

Rd

Ra

E

dE

Rd

.  ), .."iI ln 10 . ,

·IS
~

n

+S

BURR-BROWN@

MP32

IElElI

Microprocessor-I nterfaced
12-BIT DATA ACQUISITION SYSTEM
FEATURES

DESCRIPTION

The M P32 is a complete analog input system and
interfaces to many microprocessors without additional external components. Contained in an 80-pin
quad-in-line package. it includes a 12-bit CMOS
A / D converter. instrumentation amplifier.
input multiplexer that accepts up to 16 single-ended
signals or 8 differential signals, an addess decoder.
and control logic. Logic to generate interrupt. halt.
and direct memory access request signals is also
included. The system can digitize low level or high
level analog signals. Gain of the internal instrumenOne instruction acquires data as a memory-mapped tation
amplifier can be programmed with a single
device
resistor allowing input ranges as low as
Two instructions acquire data as an accumulator 1/0 external
±IOmV.

-INTERFACES WITH 8080A. 8048. Z-BO. SCIMP
MICROPROCESSOR WITHOUT ADDITIONAL
COMPONENTS
- INTERFACES WITH 6800. 650X. F8. 8085
MICROPROCESSORS WITH MINIMAL
EXTERN,AL LOGIC
- COMPATIBLE WITH PDP-8. PDP-II. NOVA. ECLIPSE
MINICOMPUTERS
- EASY TO PROGRAM

device

MULTIPLEXER
SINGLE·ENDED/
DIFFERENTIAL

liP
ADDRESS
BUS
GAIN

r.---o ADJUST
pP CONTROL BUS

A/D
CONVERTER

liP DATA BUS

International Airport Induslrlal Park· P.O. Box 11400· Tucson. Arlzena 85734 . TeJ. 1602) 746-1111 • Twx: 910-952·1111 . Cabla: BBRCORP . Telex: 66-6491

8-43

DESCRIPTION (CONT)
ANALOG MULTIPLEXERS

ANALOG-TO-DIGITAL CONVERTER

Two 8-channel CMOS analog multiplexers are used 011
'the input which permits selection of 16 single-ended 8
differential inputs. A l6-channel·pseudo-differential mode
of operation can also be achieved by connecting the
amplifier's inverting input to a common, remote signal
ground. Channels are addressed by the address decoder
which is connected directly to the microprocessor address
bus. The number of input channels can be expanded
without limit u~ing external multiplexers.
.
,

The 12cbit AID converter is a CMOS, successive
approximation device with 40ILSeC conversion time and
three-state .outputs. Laser-trimmed, compatible thin-film
.networks ate used to assure linearity and stability over
wide temperature ranges.
ADDRESS DECODER
The l2-bit address decoder has been included in the
MP32 so the device can be uniquely specified within 4k
bands ofthe address field. iffunher decoding is required,
the chip select (CS) pin can provide a 13th bit or the
output of an external decoder can be connected to the
internal address decoder output "wired-AND" node.

or

INSTRUMENTATION AMPLIFIER
The instrumentation amplifier is a low drift, differential
amplifier featuring higb speed at gains above unity and
gain programming with an external resistor. Gain may be
selected from unity to 500.

a~
g~

~(J

~

0

.

II
~

r"~

;;

Address
Decoder

I

A1134

CS 36
.0\523
Ai 25

} Add'...
S~lect

rl

{-- ..
m3S

"m
~

~~"

R

.

~

tNT 42
Af"AOY 4R

\

"co
~

c

I-

~

::I.

ORO 43

0
0

C"~
DO 60

~

WWa:a: a: a: a: a:

z

~

1-1-1-1-1-1-

I-I-wwwwww

O.... NM..,...,<.D""~~~~~~:~
~~~~;~~;;;~~~~~~
N ....

O~~""<.D..,mO_NM..,...,<.D

..........

I

Delay

Control
Logic

IDI'- .... ,...,...,....,....""

~
>--

---

~

Analog
Multiplexer

-C

>-- 0

-

i

~I
HI.

61 -15VDC

62 +15VDC
37 NC
38NC

~

0

50 +SYDC

.,r

0

64 ANA COM

51 DIG COM

I-------

r
I

a-Channel

I ,.,I,..,

I

Control
Logic

8-Channel
Analog
Mulliplell;er

i

77 MUX OUT LO
2 IA IN HIIMUX OUT HI
1 IA GAIN SELECT
3 IA GAIN SELECT
78 OFFSET NULL

~

68 IA OUT

~7

I

RESET 39
OBIN 4S

Z

ffi

~

~

::?

NM..,...,<,DI'-

·0 ....

- -n

A726

Ai! 2'
Al31
AilI33

;;;

~

~

"

m

Latch.

A522
A624

Al27

s ffi s

~

~

A2"18
A319
A420

A828
A930
Al032

.1i

(J~

oW
00

iil"
"i3

~

W

ciw

00
00

791A IN LO

49 DELAY OUTPUT
::::(:~:.::::;:~ =~~.~~.~;.~~::;

S2 START CONY

t

I

0159
0258

12~BiI

0654
0753

0
41
DACK/INTA

0
47
DELAY
ADJUST

.70

..
0

ADe IN

Ne

FIGURE I. Svstem Block Diagram.

8-44

-

+Rel

AID Converter

g!
~~
05 S5

0

0

63

65

REF TEST

BIPOLAR

POINT

OFFSET

-0

4 ADC GAIN ADJUST

DELAY TIMER
A time delay between channel selection and start of
conversion is built into the MP32 and is described in
. detail in the Analog Input COIifiguration section.

Enable signals are also generated to gate the data onto the
data bus.
REFERENCE
The internal voltage reference of the MP32 has been
optimized for stable outputs with respect to temperature.
Output current up to 2mA can be drawn externally from
the reference outputs.

CONTROL LOGIC
The control logic generates signals to halt or interrupt the
CPU while conversion takes place and to signal the CPU
when conversion is complete and data can be read.

SPECIFICATIONS
ELECTRICAL
Typical at +25°C and rated supplies unless otherwise noted.
MP328G AND MP32CG
MODEL

I

MIN

TRANSFER CHARACTERISTICS

Resolution(lj
Number of Channels
Throughput Rate(1) at G = 1

12
50

I

I

TYP

't Single-end;~/8

MAX

I

UNITS

t2

Bits

80

",sec/Channel

Differenti:.1

ANALOG INPUT/OUTPUT

ADC Voltage Input Rangesl2)
Bipolarl3)
Unipolar(1)
Amplifier Gain Range
Gain Equation
Input Voltage Without Damage

±10
Oto+10
1 to 500
1 + 125kO/RexT i

Input Voltage for Multiplexer Operation

Input Impedance
011 Channel
On Channel
Bias Current
+25°C
OOCto+700C
Amplifier Output Noise G = loo .. Rs = 1500n

1.5

1.2
7.0
±0.5
±17 + [OO/G) I

Amplifier Input Offset
Amplifier Input Offset Drift (Asource = 1.SkO maxI
Amplifier Gain Drift. (ReXT'; 10ppmfOCI
G=1
G=10
G=loo
G=5oo

V
V

VN
±35
±10

V
V

1018
1.8

0
kO

300
400

nA
nA
mV, rms
mY. p-p
mV

±7.0
±126 + [1OO/GII

~V/oC

±10
±110
±120
±120

ppmfOC
ppm/oC
ppmfOC
ppm/oC

15

",sec
",sec
,",sec
,usee
dB

11 + (2/GillQ-4

% FSR/%:'V

Amplifier Settling Time to ±O.01% of FSR

G=1I1)
G=10
G=loo
G =500
CMRR for Dillerentiallnputs DC to 60Hz
Instrumentation Amplifier
Power Supply Sensitivity

20
25
100
SO

84

ACCURACY

,

System RSS Accuracy(') at 25kHz Throughput
G=I.BG
CG
Linearity. BG
CG
Differential Linearity. BG
CG
Gain Error
Offset Error
System RSSAccuracy at 1kHz Throughput
G=500
ADC Accuracy Drift

±a.05
±0.025
±0.025
±0.0125
±O.025
±a.0125
Adjustable to Zero
Adjustable to Zero

linearity
Gain
Reference Drift
Ref Out (Pin 63)
Bipolar Offset (Pin 65)
System Accuracy' Drift (Excluding IA)
Unipolar
Bipolar
No Missing Codes (-25°C to +S5°C)(Bits 1 thru 12)CG
(Bits 1 thru IIIBG

Guaranteed
Guaranteed

8-45

%FSR
%FSR
%FSR
%FSR

±a.39

%FSR

±3
±10

ppmfOC
ppmfO

±15
±25

ppmfOC
ppmfOC

±25
±60

ppmfOC
ppmfOC

1'-

EJ.,ECT~I~AL (CO~T)

': ",'
MP32BG'AND MP32CG

MODEL
MIN

MAX

TYP

Power Supply Sensitivity IExcluding IAI
±15VDC
'
+5VDC

UNITS

±o.OO8
±0.OOO2

% FSFlI%..W
% FSR/%.lV

DIGITAL INPUT/OUTPUT
Bipolar Ollset Binary.
Unipolar Straight Blnal)'

Blopolar Code
Unipolar Code
Logic Loading Pin 1211
Logic Loading Pin 1601
All Other Digital Inputs
Output Drive
Analog Input Channels Selected By:
Output Data

3LSTTL
2LSTTL
1LSTTL

..

lTTLLoad
Al-A4
00-07

POWER REQUIREMENTS

!

Rated Power Supply Voltages"!
Pow."r Su pp/y Ranges lor Rated Accuracy
Power Supply Operating Range 1±15VDC only'
Supply Drain
+15VDC
-15VDC
+5VDC
Power Dissipation lat rated supplies'

1.

±18

VDC
VDC
VDC

20
20
160
1300

mA
mA
mA
mW

+85
+100
+125

·C
·C

±15. +5
+4.75 to +5.25 and ±1'.4 to ±15.Z5

:!oIO
10
15
60
700

TEMPERATURE RANGE
-25
-40
-55

Specification
Operating
Storage

·C

NOTES:
1. These parameters are 100% tested. 2. Inputvoltage must be kept 2V below supply voltage. 3. External amplifier required. 4. Gain and offset adjust to zero.

MECHANICAL

,r

PIN ASSIGNMENTS

p

IA GAIN SELECT
IA IN HIIMUX OUT HI

•

~..
-(t:·········· .... '~I
,

r

3,

r

T

C

..

,.

.1

A

E E. .~'
INCHES

DIM

MILLIMET~RS

MIN

MAX

""N

2,120

2180

53.85

55.37

1.670

1720

42.42

4369

C

.170

.230

4.32

5.84

0

,

0'.
035

0"
050

0"
0.'

0.53

G

.100 BASIC

254 BASIC

H

.100 BASIC

2548ASIC

,

.150

3,81

'.500 BASIC

A

•

K

N

.002

250
0'0

,-tL~JJ

"'AX

,"

0.05

.050 BASIC

127 BAStC

.100 BASIC

2.54 BASIC

T

.200 BASIC

15.08 BASIC

u

1.100 BASIC

2794 BASIC

Ail

24
25

A1

26

21
28
As 29
All 30
Ail 3'
A'O 32
A11i 33
A11 3.
3S
CHIP SELECT CS 36
NC 37
NC 38
RESET 39
ADDR DECODE 40

LEADS IN TRUE POSITION
0.015" O.38mm A@

~ITHIN

MMC AT SEATING PLANE .

020

R

23

A5

A7

NOTE:

.35

p

As

AB

38.1 BASIC

2
3
4
5
6
1
8
9
'0
11
'2
'3

IA GAIN SELECT
ADC GAIN ADJUST
IN1
INS
11'45
1N4
IN3
IN2
IN'
INO
MUX ENABLE'
MUX ENABLE 2
SIN/DIF '5
AD '6
A' 11
A2 '8
A3 '9
A4 20
lOGIC INPUT 2'
AS 22

4'

~9

i

,

Pin

~Jr""""""""'~

i

m

Pin numbers shown for
reference only. Nuinbers may
not be marked on !'ackage.

MATERIAL: Ceramic
WEIGHT: 32 grams' 1.2 oz. I
MATING CONNECTOR: 2350MC Iset 01 lour 20 pin strips •
.

8-46

No.
·4'
42
43
44
45
46
41
48
49
50
5'
52
63
64
55
56
51
58
59
60
8'
62
63
64
65
66
61

i5Acis

Input/Output Addressing
Input/ output addressing is accomplished by considering
the MP32 as an input! output ,or peripheral device. Thus
the I/O control signals are used to operate the unit. The
addressing scheme is the same as that described in the
Memory-Mapped Addressing section. The user may be
forced to use I/O addressing if all ·of the available
memory addresses have been taken up w·ith memory or
other inemory"mapped devices.
Addr..s ExpanBlon
The 8-bit MP32 base address (A5 through A II and CS)
enables one of 256 bands oflocations in the address field.
The top 3 bits of th·e 16-bit microprocessor address bus

.'\4 .'\J ,"2 AI An
1

0

0

1

===::::=

0

Channel Select

MP32 used with 8080; read MP32 base address:
IF72H channel 9.
LHD.l F72H acquires and transfers data to CPU from.
channel 9.
The 8LSB~s(at location IF72H) are transferred to
register L and the 4MSB's (at location IF73H) are
transferred to register H.
Total time: 16tcy + 50Jlsec = 57.8I'sec(for tcy = 488nsec
8080 A)
Interrupt Mode
To use the MP32 in the Interrupt Mode connect the INT
and DACKjINTA lines to the 8080's INT input and

8-48

cycled repeatedly by inserting the desired memory starting
address and the terminal count into the program.

INTA output respectively (see Figure 16). Conversion is
initiated by writing DO = into the MP32. When the
conversion is complete the M P32 generates an INT signal
which will remain low until INT A is received from the
8080.
Example: MP32.base address I F72H
MV\ A.OIl

OOH

STA

1 F72H

START

Programming For DMA Operation

L:onVl!r~iun

Continlle \ ...·jth

pro~ral1l.

INT will

arrive SO,usec after start of conversion.
IN T arrives
Us~r

h~rc

will generatl.! RST instruction

(usu~llIy

dOllt.' \·.... ith an X227) whil,.'h

will provide the address uf an
interrupt handljn~ routine and store
program l"ounkr.
INTEHRUPT Handler:

PUSH PSW
PliSH H
PUSH Il
PUSH B

~

EI
LllLIl 1 F72H

POP B
POP Il
POP H

f

POP PSW

Store ace. and flags

IStartl converllon whln
'-_-,-_--' DMA Inabledl

StuTe fe-g. if Ilel.:cs:-.ary

En':lhle interrupt
REAl) l>A') A from

MI'.~~

Channel 10 L," KLSB\
H "4MSB\
Pr(H:ess data

Restore registers and flags
Restore program counter

ENTER:

RET

MVI A. XX

:load Channel 2 with DMA Slarting Address'

OUT X4H
MVI A. YY
OUT X4H

Polled Mode
The electrical connections for the Polled Mode are the
same as that for the Halt Mode, except that the MP32
READY line is not connected.

MVI A. XX

:load Channel 3 with DMA Slarting Address

OUT X6H

MVI A. YY
OUT X6H

MVI A. XX

;load Channel 3 wilh Terminal Coont

OUT X7H
MVI A. 0
OUTX7H

Programming in the Polled M ode is also similar to that of
the Halt Mode except that after starting the conversion
with a memory reference instruction, the program continues to run. After sufficient time has elapsed for the
completion of the conversion, the most significant data
byte is read. If the MSB is set, the conversion is still in
progress. When .it has been determined that the conversion has been completed. the least significant, and then
the most significant dat.a bytes are read. Reading of the
data will begin a new conversion which may either be
ignored or it can access the next analog channel of
interest. In either case, the data from the first conversion
will not be affected·.

MVI A. 0

;load Channel 2 wilh 0 Terminal Counl

OUT X5H

MVI A. 0
OUT X5H

MVI A. 84H

;Sel Mode Reg. for Auto!lIlId and enable Channel 2

OUT X8H

The interface is designed to always start on analog input
channel O. The interface requires one pass through all
channels to intialize. The data put in memory through
this initial pass will most likely be erroneous and should
be dis~egarded.
OPERATIONAL MODES (Input/Output)
Each memory-mapped operational mode can also be
used on the 1/0 bus. When used with the 1/0 bus. the
appropriate address lines and timing signals (i.e., IIOR
instead ofMEMR) must be applied. In addition, the
appropriate READ and WRITE instructions must be
used. For the 8080 this would mean substituting the
following sequence for LHLD XXXXH:
INXXH
MOV L,.A
IN XX+lH
MOVH,A

Direct Memory Access Mode
Data from the MP32 can be updated automatically and
stored in a dedicated part of system memory by using the
Direct Memory Access (DMA) mode of operation.
Figure 3 illustrates the DMA connection for an 8080
microprocessor. Since the· MP32 address decoder is not
needed for this mode of operation it can be used to
provide address selection for the DMA controller (model
8257). This interface is designed to operate on the 1/0
bus.
The following program can be used to operate the DMA
interface. Any number of adjacent M P32 channels can be

8-49

8080 S,lI8m

18080. 8224.
and 82281

07

07

DATA BUS

00
A7
A6

DO
CS
All

ADDRESS BUS

AD

A5

1I0R
RESET BUSEN
MP32

RESET iiiSEi
1 - - - ; ~:~~
TC 1 - - - 1 - - - - 1 - - - - - 1 - - - - - - 1 ADDR
CS
DECODE
DACK2
MEMW
8257
MEMR
DR02 ~--I-------i

.~----t

READY
RESET

F.IGURE 3. MP32, 8080 Conne<:lion for DMA Operation (I 0 Mapped).

TIMING
The internal timing diagram and timing constraints of the
MP32 are shown in Figure 4 and Table l. The MP32 is
compatible with any digital system that can operate
within the timing constraints shown,

CONFIGURATION
UNIPOLAR AND BIPOLAR OPERATION

The M P32 will convert either unipolar or bipolar voltage
inputs, Unipolar input ranges vary from + 10mV to + IOV
(full~cale). Bipolar ranges are from ±IOmV to±IOV. For
bipolar input signal ranges from ±5V to ::tW\" ail
external amplifier is used to divide the input signal by 2
and an offset is introduced to give a 0 to +5V input to the
ADC. Use the connection diagram shown in Figure 5.
For bipolar input signal ranges of±5V down to ±lOmV,
the external amplifier is not used. Use the connection
diagram shown in Figure 6.
TABLE I. MP32BG/CG Timing Diagram Parameters.
Parameter

Min

Ma.

Unit

Delay· Valid Addr. to Addr. Oecoder"Out

30

nsec

128

nsec

tT

Delay· MEMW to DELAV Out
Delay· ti.lEQR to DELAV Out.

98

nsec

td,lay

Analog Settling Time

1000

Io'sec

tfi

Delay· DELAV to REAOV Out

tad
IT

lconverslon Total-Channel Conversion Time

1

45

52

nsec

55

t-Isec

to

Delay· End of Conversion to ORO

25

nsec

tl

Delay. End of Conversion to INT

70

tOa'

Delay·

80

nsec
nsec

tis

Delay - DACK/INTA to INT Out

75

nsec

rnI0R711i1T1i to oFlo Out

TI\BI.E II. Analog Input Configurations.
Input Range
±10V
±7:5V
!:5V
±1.0V
"1;:100mV

ANALOG INPUT

Symbol

The unipolar input connection diagram is shown in
Figure 7. Table II gives a summary of circuit configurations for several input ranges.

8-50

IAGain

~20mV

1
1.33
1
5
25
250

o to +10V
o to +5V
Oto +20mV

500

1

2

Circuit,
Configuration
Figure 5
Figure 5
Figure 6
Fig'ure 6
Figure 6
Figure 6

Delay Adjust
Required
No
No
No
No
No
Ves

Figure 7
Figure 7
Figure 7

No
No
Ves

INSTRUMENTATION AMPLIFIER GAIN SELECTION

The internal instrumentation amp,iifiet gain may b~ set to
any value between I and 500 by connecting an external
gain resistor between pins I and 3. With the pins open the
gain is I ±0.02%. The gain ofthe amplifier is determined
by: G = I + '(25kO, Rut), where Re.. is the gain resistor
value. The external resistor should be stable (lOppm/"C
or beter) since its drift will add to the. gain temperature
coefficient.
.
SINGLE-ENDED VERSUS DIFFERENTIAL INPUTS

The MP32 analog inputs may be connected in singleended, differential, or pseudo-differential configurations.
Single-ended operation may be used fOT high level (over
I V full scale) signals in low noise environments (see
Figure 8). Differential operation will rej~ct commonmode noise that appears on both inputs (see Figure 9) .. 11 .
should be used in noisy environments or with any low
level signal (less than I V). In the pseudo-differential
mode, the MP32 is connected.the same as single-ended

AlJ.AI1

=:;-""\
~~ !~~~D~~~ ________________________________ ~~

ADDRESS

.....

~~~DDER

,

=-

'ad

.

'~.-________

MEMW
MEMR

lad _

l.-

.

•

j,

1"-------"Y
IT" ..
1-_ ___________--.
DELAY

____~i!

~~----------------

.....- - - - - - I d a l a y - - - - - -..ij

IR~

READY

\.0-

------.\

lCOIIvalllon--------",7":Jc----------

I----------------------------J
lOll

ORO

I"

____________________________
II"';

INT

loa_
....

\r---

~t

DACK/INTA

FIGURE4. MP32 Timing Diagram.
Sat gain of Intarnal amplifier to
glva ±IDV ranga aliA OUT.

For clarily. only cannacllons
slgnilicanl to ttla analog
Inpul conllguration all shown.

4.7~FTantalum

-

0.01 ~F C8ll1mlc
51

r------=0~~~==}
88 IA OUT
83
BIPOLAR AOC IN
OFFSET
ADJUST
87

MPaZ

ADllog
Inpuls

60
51
58
55
54

NOTES:
1. R.alslor network· 10kn pull down
IBourns 4116R-001-l04 or Allen
Bradley 316BI.
2. IN914 o[ equivalent.
3. Carmat potentiomatar and Ihin-lilm
resistors wllh 10Oppm/"C TCR or lass.

0111

Bus

III

FIGURE 5. Connection Diagram for Bipolar Input Ranges Between ±5V and ±IOV.

r

+5VD

~~

~ I-

Sat gain 01 Inlemal amplillar to
glva ±5V rangeal IA OUT.

51

+15VDC

r1-

:15VBC

~.,:;~..:<- 4.7~FTanlalum

For clarlly. only COIInmiDns
signilicant 10 ttle analog
inpul conl/gurallon ara shown.

(21 >-J t·+-jH - - - 0.01 ~F Ceramic

50~

64

61

r~I;A;OU;T--:~~1=:;:===} Analog

p8

L.!!

Blpallr
Offsal (31
.Adlusl

Inpula

60

37.4kU

Z5Dll~~
81poar
I r F~5O'kU

NOTES:
Gain (31
1. Raslstor network - lDku puil down
AdJuSI
IBourns4116R.oDl-l04 or Ailen
Bradley 3168~
2.IN914 or equlvalenl
3. Cermet patanliomatar and Ihin-lilm
nIIlstors wlttllDDppm/OC TCR or I..s.

ABC IN
MPaZ
OFFSET NUU

65
BIPOLAR OFFSET

~ REF TEST POINT
ABC GAIN ADJUST

lMn

FIGURE 6. Connection Diagram for Bipolar Input Ranges of±5V or Less_

.8-51

I

Dlla
Bus

_ A5VDC
-

For clarity. only connections;: '
significant to the anaiog
input configuration are shown..

~ 4.7 ~F

Tanglum
~14.-l ~....."......=,O,OI ~F Ceramic
Set gain of internal amplifier to
liive 0 to 10Vrlnge atIAOUT.

51

61

68 iA OUT
Unipolar
011881
Adiusl

67 ADC IN

MP32

I-_~___

}

Analog
inputs

r-_---ata == Low Ref

SC

'n.lm,:I\.'II1I,.'l1ll'lllint

20
01
4C
7A
01
21

YC1>: Increment count
Han.' 1,.'()I1\I.'r!liUllloo rcw.;h~d IOU'!

8NE CONV

26

'n. Do .anuther l,.'tlIlwl"Siun

8RA START

FO
20
DF

Yes. Begin next run

COUNT
END
AI>:
AC:

AA:
A8:

ORG

IOff

LXI
LffLI>
MOV
SUI

SO

I ~l{)fI
\, I.
.\XX,\,

;1" Data =

1.0\0\-

AA

I~R

('

;\u. Incrt.!l11cnt count

JMP

AB
8
A.B

;Yes. Increment count

MOV

The program assumes that the MP32 is sei for channel
located at IF70'6 and IF71'6. If the MP32 has been
reprogrammed tor some other address this value should
be reflected in the program's STX instructions that refer
to the MP32.
.
After assembling and loading, insert a breakpoint at
location II C via a "V" command.
Calibration is performed by connecting
precision
voltage source capable of 0.005% accuracy to CHO. (This
could also be a DC voltage source of less absolute
accuracy whose output is monitored by a 0.005% DVM.)
The offset adjustment is made first by using the
appropriate offset calibration voltage. The calibration
program is then run and after 100 conversions will halt at
the breakpoint. Control will return to the 'monitor which
will then print the contents of all of the program registers
at the time of the breakpoint. The contents of each
accumulator should be compared for approximately
equal values. If a difference of more than 10,6 is present,
slightly readjust the offset control and restart the program
with a ;Pcommand. Repeat this procedure until the
accumulators' contents are within 10,6 of each other.

Ret'!

JZ
I~R

"xxxx is 0000 fur off!let. OFFI-" for gain.

:Clear Band C Reg. pair
:Rcud data fwm

:U;t\C IUO,l'uO\C'r!ooHIO!'>

been nUHh.·

AE:

ADD
('PI
JNZ
JMP
eND

C
64ff
A("
AD

a

:Yes. 8egin program again

*xxxx i!o> 0000 for offset. 0 ............ for gnin.

The program assumes that the M P32 is wired for channel

o located at.1 F70H. If the MP32 is wired for a different

address, the address associated with the LHLD instruction AC must reflect this change.
After assembling and loading the program, set a break.point at AE. The program is then started using aGIO
Command. After 100 conversions, the breakpoint will be
reached and control will return to the monitor. The Band
C registers are then examined for an approximately equal
count (within 10,6 of each other). Both the Offset and

8-54

T ABLE IV. Calibration Input Voltages.
Input Voltage
Range(')

Full Scale

Range

LSB Value

o to +IOV
o to +5V
o to+1V

IOV
5V
IV

2.44mV
1.22mV

-lOY to +IOV
-5V to'+5V
-IVto+1V

20V
lOV
2V

V, tOV2

V2- V,

Unipolar

Bipolar

General
Equation

Vm for Offset
Adjustment

Vm for Gain
Adjustment

244"V

+1.22mV
+O.6lOmV
+O.122mV

9.99634
4.99617
+O.99963V

4.88mV
2.44mV
488"V

-9.99756
-4.9988
-O.99976V

9.99268
4.99834
+O.99927V

V.2 - v,l21
- 2n--

V, + 1!2LSB

V2 - 312LSB

NOTES:
1. For other ranges, compute the proper mput voltages using the general equation.
2. n = resolution 112 bits for MP32BG/CG

The gain adjustment is made in much the same manner.
However, the data associated with·the CPX instruction in
the calibration program must be changed from 0000)6 to
OFFF'6.
CALIBRATION WHEN USED WITH
OTHER MICROPROCESSORS
The same technique used in calibrating the MP32 with
the 8080 and 6800 can be used with any processor.
Repetitive conversions are made around the "edge" of an
output digital step or transition (the lowest for offset, the
highest for gain), and then look for 50% of the conversions
to be on each side of the edge. The program should be
written to convert with the input at the transition voltage
a large n urn ber of times and record in two registers the

number of conversions that fall on each side of the
transition voltage. When the numbers are approximately'
equal (within 10,6), the converter is calibrated. This must
be done for offset first, then gain. Refer to Table IV for
th~ high and low transition voltages.
Again, the unit should be allowed to warm up for 15
minutes wi~h power applied prior to calibration.
INTERFACE CONNEC1'I.ON DIAGRAMS
The M P32 is designed to easily interface with most
micoprocessors. The following pages illustrate the use of
the MP32 with several different CPU's. The basic
software to operate the units is also shown except where
previously discussed in the text.

~

r-----------------------------------------------------------~&

8080

READY
SYNC

2

RESET
READY
SYNC

2

8224
11-------'
STSTBD---~-~----_q

nST8

iiSii

MEMwK>--------------~

NOTE: For clarity. anly IIIau ,laRllI required to canlllClthl MP321D till_ Iphlm hive blllllhllwn.
All other connactians are made as explalnad .Isewhere In this manual or In tIIa 8080 literature.

FIGURE 15. MP32 Used With 8080 in Halt Mode.

8-55

., .

. '

..

All
e
e
e

8080

AU
OBiN
INT

07

p..H:l

. lIESET
RESET
READY f--- READY
SYNC I--- SYNC
<1>2 I--- 

z

50

e,

E :;:

.!;

c0

~

5

ADC Ampli·
Range fier
Gain

20V

±10V

1

lV

o to 10V

10
100

U.1V

Oto 10V

10mV

Oto 10V 1000

Reso·
lution
4.88mV

Delay for Delay for Delay for
Settling Settling Settling
to ±CI.2% to ±CI.OS" to 0.01%
(~ec)
(/.ISI!c)
(/.ISI!c)

2441' V

7
10

24.41lV

20

2.44IlV*

60

8

9

15

18

25
70

30

-

TABLE II. This table shows the delay timer setting required
to .allow for the settling time of the instrumentation ampli·
fier to tl1e accuracies specified, Add the 24~sec conversion
time of tl1e AID converter to the above delay times to obtain
channel conversion times. * Depends on desired SIN ratio.

TABLE I. Throughput Rate vs. Gain for Normal and
Overlap Modes.

8-61

ELECTRICAL SPECIFICATIONS
Typical at '25°C and rated

'pow~r'~upplies

unless otherwise noted

I

MODEL

SDM8S3

TRANSFER CHARACTERISTICS
Throughput Rate. min
Resolution

30kHz, 33,.sec/channel
12 Bits
16 single-ended/8 differential

Number of Channels

ANALOG INPUTS
o-SV, o-IOV, ±2.5V, ±SV, ±IOV
I tp 1000
G = I + 2Okfl/REX,
±16V
±1O.24V
100Mfl, IOpF OFF channel
100Mn, I(j()pF ON channel

ADC gain ranges
Amplifier gain range
Amplifier gain equa\ion
Max. input voltage without damage
Max. input voltagc fur m~ltiplC!At:1 upcralion
Input impedance
Bias current
2S"C
O"C tp 70"C
Dif(erential Bias Current (25"C)
Differential Bias Current Drift
Amplifier output noise (Gain = 100. R.
Amplifier input offset voltage. max
Amplifier voltage offset drift

,,,

,
= 5(00)

20nA
SOnA
IOnA
O.lnAtC
1.2mV. rms; 7mV. p-p
4OO,.V
2 + 20/G,.V!"C

ACCURACY'''
System RSS accuracy at 2S"C (Gain
Linearity (Gain = I)
Differential linearity (Gain = I)
Quantizing error
Gain error
Offset error
Power supply sensitivity

= I)

±O.02S% FSR'" at 30kHz throughput
±1/2LSB, at 30kHz throughput
± 1/2LSB, at 30kHz throughput
±1/2LSB
Adjustable to zero
Adjustable to zero
±O.OOS% FSR/% change of supply voltage

STABILITY OVER TEMPERATURE
Sy.stem accuracy drift, max
Linearity ,drift

±30ppm/"C of reading
±3ppm of FSR/"C

DYNAMIC ACCURACY
• Sample & Hold aperture time
Aperture time uncertainty
Error for full scale transition between
successively addressed channels
Differential amplifier CMRR (Gain = I)
. Channel cross talk
Sample & Hold feedthrough
Sample & H'old decay rate

30nsec
±5nsec
I LSB at 30kHz
74dB at I kHz 6SdB at 3kHz (I00dB at 60Hz Gain = 1000)
80dS down at 2kHz, for OFF channel to ON channel
80dB down at 5kHz
IO,.V,..ec

OUTPUT
Output Coding (Complementary)
. Gain trim'~1
Offset trim t41
Ai D Conversion Time
Delay

Unipolar Straight Binary, Bipolar Offset, Binary Two's Complement
Adjustable to zero error
A..iju:Sl8oie to zero errOr
24psec
9#lse~ nominal. externally adjustable from 5.51'sec to 14I'sec'~f

POWER REQUIREMENTS

±ISVDC ±3% at +5OmA, SmV, nns, ripple
-ISVDC ±3% at -7SmA, SmV, rms, ripple
+SVDC ±S% at +300mA, 2SmV, nos, ripple

ENVIRONMENTAL
Operating temperature

O'C to 70'C
-2S'C to +8S'C
95% noncondensing

Storag~·temperature

Relatixe humidity
I.
2.
3.
4.
5.

With REX' between pins 26 and 27.
No missing codes guaranteed.
FSR means Full Scale Range.
Gain and Offset controls are located in the m'odule. The adjustment ranges are ±O.I% FSR for Oain and ±O.I% FSR for Offset.
Adjustable to 10 seconds witb external cap3:;citor.

8-62

DIGITAL INPUT SPECIFICATIONS
Address inputs

One standard ITL load. positive true
4-bil binary
One standard TTL load. 'negative true. address loaded with strobe inputs.
One standard TTL load. negative true, address loaded with strobe inputs ..
One stal1dard TTL load. STROBE and ~ edge trigger the delay timer and clock the address
coumer. STROBE must be high to enable STJfOlJE and ~ must be low to enable STROBE.
Two standard TTL loads. positive true. logic "0" allows the Strobe inputs to trigger the delay timer. but
prevents the MUX address counter from being clocked.
One standard TTL load. a positive going edge at TRIG initiates conversion. a negative going edge at 'TRIG
initiates conversion; TJrrn' musLbe '"0" to enable TRIG; TRIG must be •. ," to enable T"IUIT.
One standard TTL load~ logical J for 12-bit resolution. connected to the N + I bit output for N bit
resolution.

~

Clear Enable
Strobe & 'S'i"roIie
Count Enable
ADC trigger
Short cycle
Multiplexer Enable
Multiplexer Enable
S/ D select

Two stand~rd TTL loads. logical I enable multiplexer output and logical 0 turns off all channels.
Two standard TTL loads. logical I enables 16-channel single-ended operation and logicalOenabJe8-channel
differential operation.

DIGITAL OUTPUT SPECIFICATIONS.
~ata outputs
Parallel BI. BI , , . BI2
Serial out
Address outputs
Delay out (Delay Out)
Clock
Status

2 Standatd TTL loads. negative true.
2 Standard TTL loads. negative true. time serial data output beginning with 81. (sec timin,g diagram),

5 Standard Tn: loads. positive true. 4-bit

binary code. internal 2kH pull-up resistors.
5 Standard TfL loads high (low) during the delay period. triggered by Strobe E-::-_~_-_-Ch~ne~ add==."iid_--_-------_-~~-;~el ~',;;d::5 ~d~
FQjJsec::;J

-----I

~==================~

_ _ _ _-4-_~(S~a::m::p~l~in::;g~).J...- - - - - 24.usec conversion - Ch n ------ti._~(S~a:m~p:':in~g~)~

DATA BIT 1
(B1) - MSB
B2

--r,-'- __
---_

~
-"""T"'\.- - - - - - _ _ _ I- _ _ ..J 1'..1:;::;:=================~.

-

-

r
'"-"I

-1---"

-- - - r - - -

c

~

0

____

r- - - - - - - - - -

,,-_-_-_

-1'--"
- _1...
r--"\-_·11 _ -_ -_~!
_ '-.2....J~...,..----------------."'j'~ _
_ _
_ _ _r......-../
\__ _ _ 1_ ·1
I I
!!.?al.a-:!I~

B3
B12(LSB)

-- --

SERIAL DATA
OUT

S/H OUT

.

I

----'-------

-""T~IT-,-,-T" :-T_-t-{:LS~

---1I

-

--

YiJ":'L81.9__:.:.ol~~2.J __________ _

4

- - - ~8 jJ";""

Serial data valid

..

I

+FS
-FS

FIGURE 4. Timing Diagram for Sequential Addressing Normal Programming Mode.
TRIG (START)

(Runs while high -stops when low)

STROBE

24.usec Convert~,-_ _S_a_m_p_'e_ _""

STATUS
DELAY OUT

~~~

ADDRESS

OUTPUT
DATA VALID
DIFF.
AMP.
OUT

+FS
-FS
+FS

S/H
OUT

-FS

,(See Table I,)
___

-=--_~;;,~~~_-_-_-~=

Channel-n -1

\

I

~

-=

-=--:

Channel n

/

Sample

Convert

X~a~el n~-=- =--=--="

-=- -=--_-_-=

'-___________.11

\

Channel n

-'

/

FIGURE 5. Timing Diagram for Sequential Overlap Programming Mode. (Delay must be adjusted to status pulse.)

8-63

+,

PACKAGE AND PIN CONFIGURATION
SDM853 CONNECTOR PIN DIAGRAM
+15VDC
ANA.GND.
C.H 0 IN
CH liN
CH 21N
CH 31N.
.CH4IN
CH.5IN
CH 61N
CH7 IN
MUX OUT HI
LOAD ENB
COUNT ENB
A80UT
A40UT
A20UT
Al0UT
DLV.
STROBE
ADCTRIG
DLV. ADJ. 1
Rl
NEG REF OUT
POS. REF dUT
AMP IN HI
G2
Gl
·AMP IN LD
AMP OUT
STATUS
Bl MSB
B3
B5
B7
B9
Bll
SER OUT
+5

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

l'

18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

34
35
36

37
38

76
75
74
73

-15VDC
siD ENB
CH8.1N·(ORTN),
CH 9 IN (1 RTN)

72
71
70
69
68
67
66
66
64
63
62
61
60
59
58
57
56
·55

CH 10 IN (2 RTN)
CH 11 IN (3 RTN)
CH 12 IN (4 RTN)
CH 131N (5 RTN)
CH 14 IN (6 RTN)
CH 15 IN (7 RTN)
MUXOUT LO
CLR ENB
MUX ENB
A8 IN
A4 IN
A21N
AllN
OLV.
STROBE
AD.C TRIG
·DLV.ADJ.2
R2
BPO
COMP IN
GAIN ADJ.
5tH IN
5tH OUT
SHo'. CVC.
5tH CONTROL

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39

1(~~6~':})m~

t+~~:~;.~ ------i
/1 . ((i'~':});~~TTOM
I

S.1mm
(0.20")

5 6

:.. ~==: ==:··::::1 ,I
~

*

25.8mm
'1.015")

7.6mm
(0.30:')

"Tapped Screw Hoie~

•

use 4-40 x 3/16"
Hardware

smm...f

101.6mm
(4.00")

(~I

-r-1

ro~;;~)

1IIU1U.

l ,...

-

SOM863

(3.00j·)

-L

_1111 I I'

(EDGE VIEW)

J .'

t- 7 .6mm

8.4mm
(0.33")

CASE MATERIAL: Insulated Steel
CONNECTOR PINS: Gold Flashed·
WEIGHT: 146 grams (5 oz.)

MOUNTING INSTRUCTIONS:

B2
B4
B6
B8
Bl0
B12 LSB
CLK.OUT
DIG RTN

MOUNTING FLUSH ON PC CARD
1. Use strip connectors or two 14-pin and three 16--pin low

profile Ie sockets (shipped with each unit).
2. Use 4-40. x 3/16" (4.8mm) LG Pan HD Hardware to
secure the SDM853 to PC Card.

I

Model

16 Channel Single-ended or
8 Channel Differential Data

I

Description

MPC1SS

16 Channel Single-ended
CMOS Multiplexer in 28

546

t5V to t15VDCtOC

pin DIP

Acquisition System
MPC8D

J

76mm

(0.30")typ

Bf

Description

(0.65")

-4>-

-~

ORDERING INFORMATION
Model

16.5mm

VIEW)

7

,

8 Channel Differential CMOS
Multiplexer in 28 pin DIP

Converter

8-64

SDM854

BUR-R-BROWN@

IElElI

HYBRID DATA ACQUISITION SYSTEM

DESCRIPTION

FEATURES
- MINIATURE SIZE
- LOW COST
-12-BIT. ±D.012% LINEARITY ERROR
-INPUTS UP TO ±10 VOLTS
- WIDE TEMPERATURE RANGE
- SELECTABLE 16 SINGL~. 8 DIFFERENTIAL INPUTS
- THREE-STATE OUTPUT BUFFERS

Outputs

The SDM854 is a complete data acquisition system
contained in a miniature 2.2" x 1.7" x 0.22" (55,9mm
x 43.2mm x 5.6mm) ceramic package. This system
offers all the functions available in large modular
data acquisition systems. Inputs up to ±IOV can be
accepted and low-level inputs can be accommodated
by connecting an external instrumentation amplifier
to the output of the multiplexer and to the input of
the sample hold amplifier. Digital resolution is 12
bits with accuracy of±0.0249i at a throughput rate of
27kHz.

SIH

'~

Input

Serial
,---------0 Dall
SlIlul

1 - - - - - - - 0 and

Control

Digital
Outputs

}

Output

L-===~ Enable
LInes

Clack
Rata Adl ..

Clock
Out

International Alrparllnduatri.1 Park· P.O. Box 11400· Tucson. Arizona 85734 - Tel. (6021746-1111 • Twx: gI0-952·1I11 • Clble: BBRCORP - Telex: 66-6491

8-65

:,SYSTEM

O"ESCRiPTION

TheSDM854,oC~ntait;lS"all compon,nts n~,e.ssary to

multiplex and convert analog signals up~o HOY in-to
equivalent digital outputs. Throughp.uisampliiig dte's",
are from 27kHz ( 12-bit resolution)::'to, 70kHz. (~-bit,
resolution) in the overlap mode of operation. The SDM854 can be configured to accept either8-channel
differential or 16-channel sini.de-ended signals and can be '
expanded almost without limit with external multiplexers. Three-state outputs are provided for easy
interface to microprocessor and other bus-structure
systems. The systeni components are illustrated in Figure
I and described in the following paragraphs.

THREE-STATE OUTPUT BUFFERS
Digital outputs of the ADC are internally buffered by
LSTTL three-state bllllers .. Thre~ separate enable lines
"ilre brougtll out for easy iillel'facingt04-. 8~6(, 16-bit data
buse~\ ~.SB and BUSY are also bulTered ,'~y separale
three~stil~e devices. ea~h with its -own enable tine.

ADDRESS LATCH
Outputs of the 4-bit TTL register latch are connected to
thl( address inputs of the multiplexer. This latch serves as'
a'n address storage register' for the sdccit:o '~riaio!(rnput.
It may be loaded through 4 address inputs. Other inputs
are LOAD and CLEAR. The 3 least significant bits are
used for 8-cha'nnel differential mode addressing,

ANALOG MULTIPLEXER
Theanalog multiplexer consists of two CMOS integrated
circuits. Pin interconnects are used to select 16-channel
single~nded or8o{;hannelditlerential operation.lnsingl~nded
operation the multiplexer can lie used in \I pseudodifferential mode by connecting a~ external amplifier's
inverting input to common remote signal ground. Channel selection is made by an internaily latched 3c or 4-bit
'binary word. for differential or single-ended operation
respectively.

DELAY TIMER
A delay timer allows settling time for the multiplexer and
sample, hold circuits before conversion begins. The delay
is adjustable over a wide range -by use of an external
resistor or capacitor. This allows for longer settling time
if an external -instrumentation .amplifier is u~ed and is
operating at high gains. or shorter settling time for lower
resolution operation.
'

SAMPLE/HOLD
A complete stand-alone circuit. the sample hold amplifier features buffered output. 'IOJisec acquisition time.
and IOOnsec'apertllre time.
'
Input. output. and mode control lines are brought out to
separate pins. This allows maximum system flexibility
for performing functions. 'such as automatic gain ranging. with no loss of aperture time.

CHANNEL EXPANSION
The number of analog input channels of!:he S DM854 can
.be easily increased . by using Burr-Brown's MPC8D (8chan~el differential) and MPCI6S (I6-channel singleended) multiplexers. These are latch-free devices which
contain internal binary decoding at TTL or MOS levels
and may be integrated into a system with minimal externallogic.

SYSTEM PERFORMANCE
The SDM854 is Gonfigured for random channel selection. With the addition of an external counter they can.be

ANALOG-TO-DIGITAL CONVERTER
The ADC is a 12-bit. 25Jisec converter with O.OI~i
linearity error. Its features inclu'de. positive and negative
reference voltage outputs. external gain and offset adjl!st"ments. straight binary or two'S coniplement output. serial
data and clock outputs. stat \IS output. a short cycle
feature. and a clock rate control for higher throughput
rates at lower resolution o,r accuracy ..

',8-66

IlUXIMUX
001 001

,~

LO

SlIt

SlIt

IJfIIfI

S/H

S/H

r~ T- j-

IUSY

EIIIII.!

SapIoIlllld

~

EIABU I

l_~===::f-""""""U.l=fi;;';EEE DID09
Oil

DB
-:=-"'-- ENABLE 2

~--1----"-"~07

011

C""RETo
C119/RETI
CIIIO/REn
CHII/RET3
CHI2IRET4
CHI3/RETS
CHI4/RET6
CHIS/RETIl
A30UT
MUXENULE
/02 OUT
II
AI OUT
AU OUT

05

-- -L.._--,--04
03
D2

01
DO

EiiULn

~§~M~~~@Wfil

ll1~~~~~~~m

iiTlmllI

-B,4V
SERIAL OUT
SHOAT CYCLE

AD II

AIIN

27

/0211,
A3111

~ll~S:-~J~~:'

51
LOAD CLEAR

MUX
ENABLE 2

SINI DELAY STROBE
OIF ADJUST

CLOCX CLOCK
RATE OUT
ADJUST

DELAY TRIG
OUT

FIGl'RF I, SDMX54 Hlock Diagram,
configured to continuously se4uence through all analog
channels or se4uence through all analog channels on
command from an external trigger.

DIGITAL INPUT SPECIFICATIONS
One

Addn:!\:o. Coding

4-hit bin •.Ir)
One ... t.lIldan! I.S I 'II load. Iw ... itl\l;' true. 'Ilklre ... ~ hmdcd un
pu ... iti\L· edge.
()ne ,1.lnJard I S I'll IlIad. nt'.!!iltl\l' true. 111\\ k'\t'll,:lcur ...

lOA I>

With the appropriate 4-hit (single-ended) or 3-hit (differentiall channel address on the latdl inpuh, and DELAY
01'1( pin 45) tied to the LOA J) input (pin 23), a negati\e
going edge is applied to the STROHE input (pin 4X), This
starts the delay timer. latches the multiplexer address,
and allows the input signal to pass through the multiplexcr,
and sample hold hefore starting the A J) elll1\ersion,
The DEI,A Y 01'1' signal (pin 45) is also connected to the
TRIG input (pin 46) and the A D col1\ersion is initiated
on the negati\e-going edge, 'I he S H COYIROI. input
(pin 661 is l'Ollllccted to iIT'S'i' (pin 24) so that the
sample hold is in the HOI.D modc' during the A D

~tandard

Addrc:o.!'o Inpul!<>
lAO· All

('II'AR

addrcs~

I.S I II Imld.

PO:-.i[jH.' trUt'

latd

One ..landarll I II Illild. 1\I~h-h'-I(l\\ tran,llh)/l In!:!.!!l'r ...
tht'dd.l) tmll.'r.
Ont' ~tand.lrd III [null. a nega!l\c .!!llmg edgc 111I1I<1Il· ... thc

SHOR 1(")'('11'

:\ J) COl1\t'r'llIn.
Ollt' ... lundal'd I S I II Iliad. Illglt' I 1m I ~-hit rt· ... lliuliull.
('nnnl.·I,:t 10 "X-hn" or "IO-hl1" IlH' X- \11' W·hit r.,.'!'ollhllillil.

i'ITtiiTi.

RAiii1'1.
RAiiin.

Oil\.'

j)jj

.'-~talC

mm·

HI'S)' F>';,~HI.F
S H ('0>';1 ROI

\.'011\ ~r~ion.

~tandard

I S I II load. a 10\\ lc\el

en ~-151.

DIGITAL OUTPUT SPECIFICATIONS
Paralld I>aw

B~

using o\erlap programming the settling time cJlccts of
thc analog multiplexer and external instrumentation
amplifier (if used) can hc reduced. extending throughput
sampling rates up to 27k HI for 12-hit and 70kHz for II-bit
resolution (ADC short-cycled), This mode of operation is
most useful when converting low-level inputs to accommodate the increased settling time of the external instrumentation amplifier. Overlap programming is accomplished
by connecting imSY to STROBE and S H CO~TROI.:
DEI.A Y OUT to LOAD and TR IG, In this mode of
operation the address of the next channel to be com'erted
is latched and the output of the external instrumentation
amplifier allowed to settle to a new \'alue during the
prescnt convcrsion.

OutPUh
Saial Output

iiTI

ii'RY
HI'S)'

CI.OCKOl"l
Addrcs~

()utpuh

2 ~tandard TTl.luudll. pUlIiti\c trUt'. 'RZ. timc ~cri.11 data
output beginning y,ith 1>11 (lICt' riming Diagram).
5 ~tandard TTl. loads. pUSiliw true. J-1Itatc.

5 ~tandard rn. load1l. loy, during A I> con\'Cr~inn.
5 standard TTl. loads. high during A () comer...ion. 3-~tute
511landard I'lL. load~. fur synchroni/ing scriulllut data
(see Timing Diagram).
5 LSTfL or 2 standard TTL loads. positive true

IAO-AJ)

DELAY Ot'T
,S».;

8-67

I>I~

5

~tandard

TTl, Inad!V

100

nsec
J,lsec
mV

DYNAMIC ACCURACY
Sample/Hold Charactertstics
Aperture Time
Acquisition Time
Feedthrough 10V step

10
:1::1.4

OUTPUTS
Digital Output Coding
Serial Output Coding
ADC Conversion Time(3)
Clock Frequency(3)
Delay(4)

NC
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CHO
MUX ENABLE 2
MUX ENABLE IfA3 OUT
SIN/DIF
A20UT
A10UT
AD OUT

CLEAR
±0.024
±0.012

Binary, Offset Binary,
Two's Complement
Nonrer

~5zel·N3~Z'

J,tsec

520

kHz

15

J,lsec

mA
mA
mA
mW

'C

'0.
'C

NOTES:
1. FSA means Full Scale Range FSR is 20V for :!10V r~nge .
2. Adjustable to zero.
3. Conversion time' and clock frequency can be externally adjusted from
13l-tseC fdock:::: 1.0MHz to 11 Op,sec . fclock :.: 118kHz Conv. times are
for 12-bit resolution.' See Figure 9.
4. Can be externally adjusted from 3,usec to 300.usec.

II
kU
nA

-35

Specification Temperature Range
Operating Temperature Range
Storage Temperature Range

V
V

0.02

+10

V
1:/

' ±lS.5

TEMPERATURE STABILITY

Positive Output
Positive Output Drift
Negative Output
Negative Output Drift

UNITS

ENVIRONMENTAL

ANALOG INPUTS
ADC Input Voltage Ranges
Mux Input Voltage Range
Absolute max without damage
For linear operatton
Mux Input Impedance. OFF Channel
Mux Input Impedance. ON Channel
I nput Leakage, OFF Channel
Output Leakage. AJI
Channels Disabled
Output Leakage with
Input Overvoltage of
·35V
-35V

PARAMETER
POWER REQUIREMENTS

TRANSFER CHARACTERISTICS

8-68

AOIN
AllN
A21N
A31N
LOAD
BUSY
DIG COM
SHORT CYCLE
1O-BIT RESOLUTION
8-BIT RESOLUTION
DO LSB
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
Dll MSB

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1B
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

80
79
78
77

76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

NC
NC
MUX OUT LO
CH15/RET7
CH14/RET6
CH13/RET5
CH12/RET4
CH111RET3
CH10/RET2
CH9/RETl
CH8fRETO
NC'
5/H IN
SfH OfFSET ADJUST
S/H CONTROL
-15VDC
-15VDC
ANA COM
SfH OUT
-6.4V REF OUT
10V RANGE
BIPOLAR OFFSET
20V RANGE
·2.5V REF IN

E"NiiilLE2
• 25V. REF OUT
ENABLE 1
ENABLE 3
SERIAL OUT
CLOCK OUT
CLOCK RATE ADJUST
+5VDC
STROBE
DELAY ADJUST

TRiG
DELAY OUT

D1i

BUSY
BUSY ENABLE
5fj ENAliLE

MECHANICAL

n
.

-=:1L_'

NOTE:

J!"·:···············:,
79

Pin numbers
shown for
reference
only .

41

Leads in true position
within 0.015" O.38mm R
at MMC at seating plane.
INCHES

I r"' .................~ r
~~:······A..~

t [t .
N+--K-oJL
I

I

. .,.
."'
DIM
A

538&

5537

1670

4242

4369

170

. 230

'"
0.'

..

G

100 BASIC

H

,00 BASIC

2 !i4BA$'C

0:..0

2 &4 BASIC

..'", .,.".

,
,
,

WEIGHT: 32 grams 1.20z
MATING
CONNECTOR:
2350MC set of four

20-pm strips or
0422MC assembled unit

",

'"

381 BASIC

1 500 BASIC

N

-LD

,

." ."
'"

."

,D
K

1II11111111111dllilAIIIIIIIIRAdlli

MATERIAL: Ceramic

MAX
2190
, 720

C

I

MILLIMETERS
MiN
MAX

MIN

2120

.0>

o 2~

050 BASIC

127 BASIC

H

lOa BASIC

~

.200 BASIC

508 BAS'C

U

1100 BASIC

2194 SA5'C

54 BASIC

TYPICAL PERFORMANCE CURVES

POWER SUPPLY REJECTION
VS POWER SUPPLY
RIPPLE FREQUENCY
0.2

8

>

1

0.1

;

0.04

~
iii

0.02

II
I

(/J

"-0.004

-'-

0.002

J L

0.001

o

~

';5VDC

Vl

100
lk
10k
Frequency' Hz

'"
tj -5

e

iii

lOOk

1M

-

10

0

eo

30

40

50

~

.....
60

i5

u

'"

-0.05
-0.1
'0.15
Temperature °C

Conversion Time }Jsec . 12-Bit Resolution

V

ArD CONVERTER LINEARITY ERROR
VS CONVERSION TIME

~

'0

'. 30

if-

e

w
,.,

,

O.~

1/2LSb
0.195 B-Bit

~

- -- -- -

a:

"-

'0

if-

g

0,2 1/2LJB
0.195 8-Bit

--

8-Bit

0,15

w

Z.

10-Bit

O. 1

0.05 1/2LSB

\ 1\

30.048 5 - - 1 :~
10-Blt 1/2L~.~
0.012 2
112-Bi1
20

AID CONVERTER DIFFERENTIAL
LINEARITY ERROR VS
CONVERSION TIME

(/J

8-Bit

0.15

.~

15

u

o

a:

10
Time ,min'

>-

" r---.....

(5

CASE TEMPERATURE VS TIME WITH
NO HEAT SINK OR AIR FLOW

U 40

~ .0.05

J!!
a:

-10

-0.1

(/J

I'.

I

10

a:

~\

I
-15vDC

V V

if-

0,0004

l\..

1+15vDc

a: 0.Q1

SYSTEM ACCURACY DRIFT

AID CONVERSION TIME VS CLOCK RATE
CONTROL VOLTAGE, 12-BIT RESOLUTION
15

5

12-Bit

15

Conversion Time' }Jsec

8-69

o. 1

3

10-Bit

1\

0,05

_~1/2L~Jl

20

12-Bit

-1/2LSB \
::\
'i' 0.0485 =lO-Bit
~ 0.012 2
1Z-Bit
::=
10
15
is
(' llI" Itl user It)p.ic ein.:uitr~.

AO" - A.1"

Addre~~ linc!'l th.11 !ooCh,t one of 16 .analup. input !l.iglUtl!oo (('HO-CH l!il. ()U(}() !o.Cicl.'t!oo chunncl () mul IIII !l.eh't!oo
dlil 11 l1el 15. ('ul1ncct 1\.1 III !!Hlund fur H-chi!,!itall'ommon. Connect to A:\A COM (pin 6.1) as dose In the SI>MH54 as possiblc:

Pin 26

SHORT CYCI.E

This pin allows short cycling thc A '.l> convcrter for lower rcsolutions then:b~ ubtaining faster cnnwrsinn time!l..
Connect to +5Vl)C (pin 49) for n-bit resolution. (pin 27) for 10-bit resolution, or (pin 28) fur 8-bit resoluti(ln.

IO-BIT RESOl.lJTIO'

To sh~)rt cycle to 10-bit resolution ctlnnt."'Ct

S-BIT RESOI.l!TlO,

To short cycle

10

~o

20, 21. 22).
i~

ioy,.

pin 26. Otherwise. make no .l·onnel,'tion.

8·bit resolution. connect to pin 26. Otherwise, makc no connectiun.

Pin!\' 1') thru40

1l0-1l11

12-:-hit dutll hus, .l-SUItC In\\ pO\\"l'r Schuttky TTI.'"l'mnpiltihk'.

Pin "'I

i5ii (pin 44) is cnabtcd "hen WI

Pin"':!

iiii RAiiiT
81'SI' RA'iiiT

Pin .tJ

III'SY

.l-!'otutl'llutpll.1 Ihlll \\ill he hig.h unl~ y,hill''''' A l)c\unl',""i(Hl i!o. in pn\l.·c:-O'... Output until i!'lnut \,did \\hik'lhb!'lil!mll
i!oo high.

Pin~

iiii

MSii. l'se in!o.tclld of DII Y,hl'l1 tYou'!oo cllmpienlL'llt tlutput i!oo l'CljUirl'd.

Pin .a5

IlI'I.AY 01

Thi!l. pulsL' is u!ool'd tn del", the heg.inl1in!,! of the A D cumcl'!ooiull ttl aUo" for the sl.·ttling 01 the l11ultipk':\cr ilnd
!I.'lmple huld.

E~A81J: i!l. 1m\.

8('SY tpin.4.11 j!l. cmtbk'd when Ol'SY

F:\A8~.1:

i!oo 10".

Pin -'1'1

nm;

A ncW-tthl' TTL cd!,!c

Pin 47

IlHAY A/J.lI'SI

Whcn thc SI)M854 i!o ilddre~!l.cd. illl intl.'rnal dclu~ ot appr(lxil1latd~ IS",scc j" initiuted to allo\\ for multiplcxcr :.lIIcJ
!l.anlplc hold !oI:tliing lime. The dela} can he !oohurtl.'ncd fur hIMC!" Im\l.'l"-rc!I.(l!utiun. ()pl'mtiull.

Pin-l)l

STR(18F

A

Pin ...9

-5\'Il('

+5VDC at 200mA maximum, t 70mA typical.

Pin 50

(,l.ot'K R ..\ I F AIl.ll'S'I

\'.Iryiny the \oltn!,!e:.u thi!l. pin chullI.!.I.'!oo Ihc duck. frcl!uency antt Iht'rt'h~ .'h~.,,~!.... ~h·: ~~,~'.~~;~~:-: :.p::c:.! ,~f ~h.: /'" D
conn'rter. (\mllC"ct to DIG ('OM (pin 25) for 12-hil upemtion (25J,t!ooel.' A I> c(lIl\crsion timel. Cunnect tu
+5\,1>(, for IO-hit uJll'ratiun a~d .cunnect t~) +15\'1">(' fur H~bit operatiun (~t.'e page II I.

Pin :'1

('/ ()(,K (WI

:\' I) I.·umertcr clOCK output. Output is fWe!ool:nt only dur.in,g 1\ I> c()n~crsion. :\ + ITTI.
5.:'!01o;HI rate "hen.':'\ i!oo Ihe rc!ooulution. .

l'in :'1

SHU,\I

Seri'll uutput d.tta in ~RZ format i!oo!ooynchronuu!oo with (·I.O(·K Ol' J (pin 51 )sit!l1ul.l'!ooc I1l'gmi\"C ed.!:-'t.' uf('I.O('j(
Ol' r to ~trohc euch hit.

()l

I'X ..\81I,.1 '
"'ADI." I
"'A8!.1' j
I~ili

55

-2.5\' RHOI'

1ll'~ati\I.'

011

r IT cdgc tlll

thi!l. pin initiutc!I. thc A D e(lmcn.ioll. Conncd

In

DI:I.AY Ol' r (pin 45),

thi!oo pin initiutc!l. thc I>EI.AY Ol'j" pul!I.C.

pul~I.':4: E:,\ABl.f 3 (pin 5.') enuhles D.l - DO. A Iny, on thc emlblc line cnable!oo
·uutPUh.

1..11.11.1

Pmitl\c \ultage referencc uutput. ('unnect tu REF 1:\ (pin 57) (through SOU) for unip()lur or bipular opcratiun
(unlc!oo!oo an ~xternal rcfcrcnl.·c·is used). AI!'Io connect tu BP9 (pin 59) (t~rou!,!h 25U) for hipolar operation,

lOon pot) or u!ooc

Pin 57

Relerence \uhage input. Connect hi +2.5V REF OUT (pin 551 (through SOU resistor or
extern,,1 +2.5V reference (+2.5V ±IOmV "I O.·5mA required).

Pin ;1'(

AI D convener input resistor. Leave open unless an external IA with a sain greater than 2 is used, (Input
multiplexers are limited to ±IOV maximum input voltage.)

Pin 59

~

BIPOI.AR Of+SI' I

/\ D comerter hipolur oIIM!t. ('unnect tu KEF Ol 'T 'pin 55) through u 25J1 rcsi!'ltor or a 5O{1.p01 for bipolar
operation. I.emc open fur unipulnr uper..ltion.
•

Pjn fotl

10\ R,\\(iI'

.'\ I) l'(f!l\I.'rtcr input rl'!ooi!ootur. l·!l.ing withnut 11'\: l·onnl.'l.·t to SHOt "1' (pin 62)

Pin til

-0,4\ 11IT 0(' I

,"eg!,.' Itl thl' SI )\11<5'" :1."

Pin 1l.J

-1~\'Il("

-15\ 1)(' al JOnll\ t)pil·al.

l'inM

+I~\'I)('

!'il1M

S II

Pill ('7

s 1I00'I'Sri AIl,Il Sl

Olhd illiju:o.l luI' :-.amph.· hold hel: I-ig.un: XI.

Pin tiX

S 111\

Input

PlIllllj

Pill' 70 thrLl 77

t

("o~

I KOI

'"

, '!lX-('II"
RI In - KI'I7

15\'1)('

,II

rll,~ihh.·.

.lOrnA I)pil,.d.

A 10\\ !-----~~~--------~I~~l-!f~=:

-

/v
--'-

-15voe

"

+15voe

.~lk!l

1lOO8 11012 ,1l016
elpacllDr Valullllll

1

fine OIlset
Adluslloptlonall

24k!!

IlO2I1

or

FIGURE 6, Typical Capacitor Value to Increase Delay
Time·
30
25

1 20
>i 15
.],

10
5

0

L

,.....

100

-200

f.-- I--

300

400

I--

500

6110

Resis!O, Valuelkl!1

FIGliRE 7, Typical Resistor Value to Decrease Delay'
Time,*
"'("l.Ipal"itnf ur n:!>i~tor i~ L'OlUll'L'h:d frum J'lin 4710 +.5\' :-.upply.

CALIBRATION PROCEDURE
GAIN AND OFFSET ADJUSTMENT
External gain and ofTset adjustment potentiometers arc
~h(p",'n in Figure H. Ccrmt:'t p:'1t:; \\'ith " T.C. R. of
± 100ppm "C or less should he used, The adjustments
shown each h(nc a' range of ±O,JI'; of the Full Scale
Range,
If adjustment of gain and offset is nO\Teljuired iH and R2
should he replaced with 25l! (Illd 50l! rcsist!lrs respectively, These resistors should he low T,e «±100ppm "C)
-metal film or eljuiqllent.
The SHOFFSET ADJl'ST (pin fl7) may he used as a
fine offset adjustment.,
The easiest way to'calihrate the dc\'ice is to connect a
\Olhl!.!e source io multiplexer input CHO (either differ~n
tial Ill' single-ended input opemtion may he used),
Channel zero will be addressed by simply connecting
CI.EAR to DIG COM,

FIGURE 8, External Gain and Offset Adjustment.

adjust the offset potentiometer until all output bits are
logic 0 with bit DO ,dithering between logic 0 and I,
Change the source voltage to the most positive value of
the input range minus~, 2LSB. Adjust the gain potentiometer until all output bits are logic I with bit DO dithering
between logic I andO. When a resoll.!.t,ion less than 12 bits
is used,. the LSB voltage is given by the formula in Table
II where :'II is the number of output bits, Onc's climplement coding is obtained by shifting the previous adjustments up by I 21.SB using the offset potentiometer.
TABLE II. I.SB Values, for 12-Bit Resolut'ion.
LSB Yolts
Range

After the CHO \'Illtage source has heen addresse-

... ... +

1

Simply adding an external counter will allow.sequentii!l
addressing of all 16 input channels (see Figure 13).
i

.

'

,

FIGURE 13. Sequential Addressing.

MULTIPLEXER ,CIRC;:UIT OPERATION
At the address and enahJc inputs a \oltage is interpreted
as a logic "1" if it is greater than 2.4 \olts; and "0" if less
than 0.8 \OIls.

3kll
"i

When 'an ·input .channel has been· selected the "on
resislitnce" fnim inpul 10 output is 3k!t The input
capacitance'for each channel is approximately 7pF. while
the output capacitance is approximately 25pF for each
8-channclmultip!exer. A circuit model of an ON channel
is shown in Figure 14.

~·~-1~"~~~~·~~l~·--·~

I

7PF

:to
-=-

I25pF

.

lEach 8·channel muiliplexerl

FIGURE 14. ON Channel Circuit Model.

8-76

This model is very important when high speed switching
of high output impedance sources is required. For
example. if the full accuracy and resolution of the systcm
is required. the signal at the output of the multiplexer
must be allowed to settle to about 0.01",. If the source
impedance is I kll. the 7pF can be neglected and the
multiplexer has a time constant of 2.Xkl! x 50pF =
140nsec. It requires approximately 9 time constants to
settle to 0.0 V,: 1.26j1sec is well within the 15j1sec of the
SDM854 delay timer. However. if the source impedance
had been 10kl!. the 0.01", settling time would have
approached 6j1sec. For high speed multiplexing of higher
impedance sources. it will usually hc desirable to parallel
the 7pF input capacitor with a large capacitor: howeser.
this could limit the source bandwidth. In am' case there is
no point i'n making it any larger than 10" tin~es the output
capacitance. or 0.5j1 F. When this sile storage capacitor is
used. t he out put time consta nt is 1.8 kl! x SOp F = 90nsec.
This means that the system settling time is essentially'
determined by the settling time of a differential amplifier
and sample hold circuit. For switching of large signals it
must be remembered that the 0 ' resistance is the
channel resistance ofa FET. and. as such. it is a nonlinear
function of the applied \oltages. An~ ITT will current
limit at its Ill" ",tlue. As a result. the pres ious calculations
arc only an approximation derived from a lineariled
model. The settling time to 0.01' i for a 10V step is
approximately 4.0j1sec for source impedance less than
Iklt.

USING AN INSTRUMENTATION AMPLIFIER
WITH THE SDM854
When low-le\el signals are being con\wted. such as with
thermocouples. strain gauges. etc.. it will be necessary to
usc an instrumentation amplifier (IA) \\ ith theSDM854
10 utilile the full dynamic range of a 12-bit systcm. This
can be done by connecting the IA bet\\een the multiple,xer
and sample hold amplifier because the output of the
multiplexer and the input of the sample hold amplifier
arc both brought out separately on the SDM854.
There arc two ways an external IA can be connected to
increase the \ersatility of the system. The most accurate
way is to 1I~l: the amplificr in it true differential mode a~
shown in hgure 16. \\ here a Burr-Bro\\ n 3630 is connected

Gain

140k !!IRgl

TWISTED
lEAD
INPUT

The analog and digital inputs have re\erse biased diode
circuits which prevent damage from discharge of static
electricity. Ho\\e\er. it is still wise to take reasonable
prc((1ution against static discharge.

l'I(i[' R Flo. InstruJllcntation Amplifier ('onncl·tion lor
I rue IJiflcrential Input.
to the SDMX54 for dilfcrential opera lion. I his configuration is ideal \\here the inpul lines run OIer a long
distance or through noiss em ironments. I'or best re,ull,
the input linb ,hould be in t\\ i,tcd ,hielded pair' \\ ith the
shield grounded alone end to present ground loop

BINARY SCALING
Binary scaling, of the A D comerter provides I.SB
\,oltages of 2.5m V. 2.5mV. and 5.0m V for \ oltage ranges
01'0 to 1O.24V. -5.12V to +5.12V. and -10.24V to ± 10.24
respectively. These may be obtained b, adding external
resistors in series \\ith input n:sistors of the A D
conserter. Metal film resistors \\ ith teinperature coefficients of less than IOOppm "C arc recommended. This is
shown in Figure 15.

r

=I +

curn:nt~

from forming.

A ,eeond \\a, to usc an IA is in the p,eudo-dillerential
mode as sho\\ n in Figure 17. '(hi, method i, idea I il ~"I 01
SDM854

+V

Gain =1 + 140k!!lRgI
Input Range

lOV Range
20V --'''''''--different input signals versus only 8 inputs
in the true differential operation.

THERMOCOUPLE TEMPERATURE
ACQUISITION
Thermocouples arc oi'ten used as temperature sens(irs for
process control systems: Thermocouples are ch'aracterized
by temperature coefficients of 1011 V "c to 7011 V"C and
operating ranges of minus hundreds to plus thousands of
degrees centigrade. When the S{)M854 is operated with,
an external instrumentation amplifier gain of 100 to
1000. it may be connected directly to these devices.
However. electronic instrumentation is usually mounted
in a temperature controlled environment with Ipng runs
of thermocouple wire to the actual point of tempeptlire
measurement. These long wire runs often pick up large
common-mode noise signals of60HI or higher freljuencics.
When the SDM854 is used as an 8-channel differential
input system. the high common-mode rejection of the
external instrumentation amplifier will reject commonmode noise. To minimize differential mode noise. signal
wires should be twisted and possibly shielded. As a rule.
an open twisteD pair is better than a coax. and a shielded,
twisted pair better still. In applications where these
wiring practices cannot always be observed. a differential
RC filter may be used (see Figure 18).

In both the true differential and pseudo-differential
operation care shpuld be taken in choosing the correct IA
to maintain the high accuracy ~lI1d linearity of the system.
Some or the importa'nt characteristics arc:
I. I.inearity error':;; 0.0 l2fi at all gains
2. Offset current drift, ~ I 2I.SB (Gain)( R,,,,,,,,,,)..l.T
(,MRR > (,M,,,,,.,, I 2I.SB
4. Offset voltage drift < I 2I.SB (GAI:\)..l.T
5. High input impedance> R,,,,,,,, x 10'

J:

The importance of initial offsets arc s()mewhat minimi/ed
by the capability to cancel out offset at se\'eral points in
the system. The Burr-13rown 3f>30 was chosen for this
ttpplication because of its high linearity. good drift spec
and CM RR characteristics. Someofthe accuracy calculations for the Burr-Brown 3f>30 are as follows:
Nonlinearity = ±0.002 + 10 < (Gain) Ii FS at G':;; 100
nonliilearity is':;; O.OO.Vi FS
Input impedance = 10"!!
source impedance up to
lOOk!! can be used.
Voltage offset drift at (jain = 100
O.251lV "C.:;; 1.22m\' IOO..l.T so..l.T':;; 49"C
for errors':;; I 21_SH.
CMf{R at (jain = 100 is IIOdB
eM range = W\' ,l.nmV = 7gdH.

S;,

The 10k!! resistors and a lOll F capacitor pnnide lowpass filter-ing 0: = O.KH/) "hile the I Mil resistors supply
hias current to the instrumentation amplifier. The remote
sensor should be earth grounded to pre,'ent commonmode Hlltages from <',\ceeding the ± IS\' range of the
multiplexer. This will'tlsually supply hia, current: 110\\ever. the resistors pnnide a back up. It is 110t obvious
what resistance the bias currents orthe amplifiers \\ ill sec.
The I Mn resistors do not enter into an error calculation
for input drift because the low resistunce or the sehsor
shorts any differential current of the amplifier. Ollset or
difference current is merely the difference hetween the
bia~ currents of each input. See page 15 for a worst-case
error analysis of the input filter ror multiplexed data
aCljuisition systems. The I Mil resistors could have heen
put on the output side of the multiplexer eliminating the

RG = 40n

Thermocouple

~

,,

'-:---v----'
long Cable Run

B25!l
1I10IRa" Rbi
•
27k!l1

O.I_F

_

Rc
~

"-v-' """--v----'

1

·t5VDC .". Dual MDnoil~ic
Transistor Pair
Mounted Near
•• Rc+RII
--!!L'H .!!
Ii!! " " } Isothermal
All.
{
..!!. _...J!L It + B!I!.~ 10
Barrier Strip
Hc+Ad

Ab q

T: IK,lt!q = 1.17 II

IT

to- 5

FIGURE 18. Ambient Temperature
Sensor

I

SOMB54

I

Optianal IHz low·Pass :
:
Bias Current
Filter
L __=_~1.!!.:15__ !l!
Supply Resistors

~Ra 4O.2I--.
~

~~

80M854

ENABm
ENABLE 3

XACKI

BUSY

AORII
AOR21
AOR31
AOR41
OATyl

AD IN
AI IN
A21N
' A31N
00
01
02

OAT I

I

:, I

I,

FIGl'RE 23. SDM854 Interfaced to SBC80 Multibus.

WAIT

Processor Enters WaiiSlale
Qulpul P20 = I Prevents 8tsrt of Anolher Conversion
22Msec + Wall Inllialize P21 . P24 As Inpuls
,--"-"'Output P27 = IOP26. P25 = I
Typ.
Inpul P21 . P24 Read 4,IIlSB's
'Oulpul P26 = 10 P21. P25 = I
Inpul P21 • P24 Read 4 Mid Bits
Output P25 = 10 P27. P26 = 01
Inpul P21 . P24 Read 4 LSB's
Insulllclenlinio on Z8 to do beHer program or diagram.

Hi

I,

'BIlSY
£1
E2
E3

STB2
P20
P21
P22
P23
P24
Z8
P25
P26
!»2?

Initialize Port 2 P20 . P27.As Oulputs
Oulput P20 =0 P2 . P24 Channel Oal8 .'
Starts C!llIverskm

ENABLE I

Ilb~
8if'~

N

~II.U

STlIOB£

t-2..

,--

,--

FIGURE 25. SDM854 Interfaced to Z8.

8-80

SDM856
SDM857

BURR-BROWN

IElElI

HYBRID DATA ACQUISITION SYSTEM
FEATURES

DESCRIPTION
The SDM856 and SDM857 are complete data
acquisition systems contained in a miniature 2.r x·
1. r x O.2r ceramic package. These systems offer all
the functions available in large modular data
acquisition systems and are available with an
optional internal instrumentation amplifier
(SDM857). Inputs as low as ±lOmV can be accepted
by the SDM857; thermocouples, strain gages, and
other low level signal sensors don't require external
signal conditioning. Both models are fully
expandable from the basic 16 channel single-ended
or 8 channel differential input capability. Digital
resolution is 12 bits with accuracy of ±o.024% at a
throughput rate of 29kHz (SDM856KG).

• MINIATURE SIZE
• LOW COST
• 12-BIT. :tD.012% LINEARITY ERROR
• INSTRUMENT AMP OPTION
. • LOW LEVEL INPUTS ISOM8571
• SELECTABLE 16 SINGLE. 8 DIFFERENTIAL INPUTS
• THREE-STATE OUTPUT BUFFERS
• THROUGHPUT RATES (SOM857 Overlap Model
B-Bit Accuracy: 70kHz
100BII Accuracy: 32kHz
12-BII Accuracy: 29kHz
Outpuls

SIH
Input Control Output

,

Irn~pm&--OUt~~I: ~

I
I
I
I

+
IA.
-

I
I
I
I

Input

Serial

r-----------~;;I
Contnll

SIH

L_SO~~~~ _J

-=

Digital
Outputa

Output
}
L--===~ Enable

linea

81mbl

Chick

Rate Adj.

,!nl8rnlllanal Airport Industria.' Park· P.O.

Bo~

Clock
Out

.-.-Rll8l111cl
Outpma

11400· Tucson. Arizona 85734 . TIl. (602) 746·1111 . Twx: 910-952·1111 . Cable: BBRCORP· Telex: 66·6491

8-81

DISClJSSION OF PERFORMANCE
INTRODUCTiON
SDM857 ~()~iai~s~1l components necessary to multiplex
and c6nvert analog. signals low as d:1O\nV and as high
as ±5V into equivalent digital output~, "Throughput
sampling rates are from 29kHz (I2-bit resollition) to
70kHz (8-bit resolution) in the ()Verlap mode of
operation. A complete low drift instrumentation
amplifier allows selection of gains from 2 to 500 with one
,external resistor. SDM856 is identical to SDM857, but
'doe§ not include the instrumentation amplifier. This
provides the option of ailding an external instrumentation amplifier for specific requirements such as high
speed, digital programming, etc. Both models, can b.e
configured to accept either 8-chanriel differential or 16channehingle-ended signals and can be expanded almost
without limit with external multiplexers. Three-state
. outputs are p'rovided for easy interface to micro'processor
and other bus-structured systems. Figure I illustrates all
system cor;nponents which are described in the following
paragraphs.
ANALOG MULTIPLEXER
The analog multiplexer consists of two CMOS integrated
, circuits. Pin interconnects are used to select 16 channel
single-ended or 8 .channel differential, operation. In
single-ended operation the multiplexer can be used in a
pseudo-differential mode. by connecting the amjllifier
inverting input to common remote, signal ground.
, Channel selecti9n is made by an internally latched 3 or 4

bit binary word, for4iffer~nti~i' or
operation respectively.

as

,

SDM8S7

<;l:!ly

MJx~~~Goln -~ S/H
lin In" Adjust Out lin

Muc
Out . Out

HI2

7~ :~l ~t

~ingle-ended
',

INSTRUMENTATION AMPLIFIER (SDM857 only)
Offering low' drift and high accuracy, the internal
instrumentation amplifier may be programmed by a
single external resistor fot gains from 2 to 500. With gain
programming pins open, the gain is 2.

SAMPLE AND HOLD
A complete stand .alone circuit, the sample and hold
amplifier features bufferell' outpUt, IO",sec acquisition
time, and 100nsec aperture time.
Input,output, and mode control lines are brought out to
separate pins. This allows nlaXimurrtsystem flexibility
for performing functions, such as automatic gain
ranging, with no loss of aperture time.
ANALOG TO DIGITAL CONVERTE,R
The ADC is a 12-bit, 25",sec converter with 0.01%
linearity error. Its feat~res include positive and negative
reference voltage outputs, el(ternal gain, and offset
adjustments, straight binary or two's' complement
output, serial data and clock outputs, Status output, a
short cycle feature, and a clock rate control for .higher
throughput rates at lower resolution.

,
Off.t 51H
Adl. Control

s/H!!!!x

Alta

Dla.7.f1V

Out Enabl. BusylUiY

Com

Com Range

i1 1 :t"2~"
1
U--:::,
62

6

I ~ I
. L - - - - .J

I",

.. '

43,

'i~1631~ft
+15

IOV

"+2:5V.

Ratve .f Ref

-IS <5

7.:T.t1e/

,---JL-JLW-,
DII
DID

InstNmentation

Ampliflor.

D9
D8

D7
D6

EnabEe'2
D5
D4
D3
D2

DI
DO
£noblo 3

1m
tm£noble
-6.4V
Serial Out
ShartCycle

Out.~t~~~~~~~fr

fnab 1 A2 Out
M.lJe /P3
AIOut
AD Out

1081'
8 Bit

AO-In
AI In

A2 In

A31n

21

:tl"

51

Mux

sirV

Delay

Enab 2

Dlff

(M

Clod< Clod<

"'to

Adl'"

FIGURE I. SDM856/SDM857"Furiction Diagram.

8-82

Out

DISCUSSION OF PERFORMANCE (CONTINUED)
THREE-STATE OUTPUT BUFFERS

SYSTEM PERFORMANCE

Digital' outputs of the ADC are internally buffered by
LSTIL three-state buffers. Three separate enable lines
are brought out for easy interfacing to 4-, S- or l6-bit data
buses. MSB and BUSY are also buffered by separate
three7state devices, each with its own enable line.

SDMS56 and SDMS57 are configured for random
channel selection. With the addi\ion of an external
counter they can be configured to continuously sequence
through all analog channels or sequence through all
analog channels on command from an external trigger.
With the appropriate 4-bit (single-ended) or 3-bit
(differential) channel address on the latch inputs, and
DELA Y OUT (pin 45) tied to the LOAD input (pin 23), Ii
negative going edge is applied to the STROBE input (pin
4S). This starts the delay timer, latches the multiplexer
address, and allows the input signal to pass through the
multiplexer, instrumentation amplifier and sample/ hold
and settle to its final value before starting the A/D
conversion. The DELAY OUT signal (pin 45) is also
connected to the TRIG input (pin 46) and the A/D
conversion is initiated on the negative-going edge. The
S/H CONTROL input (pin 66) is connested to BUSY
(pin 24) so that the sample/hold is in the HOLD mode
during the A/D conversion.

ADDRESS LATCH
Outputs of the 4-bit LSTTL register latch are connected
to the address inputs of the multiplexer. This latch serves as
an address storage register for the selected analog input.
It may be loaded through 4 address inputs. Other inputs
are LOAD and CLEAR. The 3 least significant bits are
used for S channel differential mode addressing.
DELAY TIMER
A delay timer allows settling time for the mUltiplexer,
amplifier and sample/hold circuits before conversion
begins. The delay is adjustable over a wide range by use of
an external resistor or capacitor. This allows for longer
settling time of the instrumentation amplifier when
operating at high gains, or shorter settling time for lower
resolution operation.

By using overlap programming the settling time effects of
the analog multiplexer and instrumentation amplifier
can be reduced, extending throughput sampling rates up
to 29kHz for l2-bit and 70kHz forS-bit resolution (A DC
short-cycled). This mode of operation is most useful
when converting low level inputs to accommodate the
increased settling time of the instrumentation amplifier.
Overlap programming is accomplished by connecting
BUSY to STROBE and S / H CONTROL; DELA Y OUT
to LOAD and TRIG. In this mode of operation the
address of the next channel to be converted is latched and
the output of the instrumentation amplifier allowed to
settle to a new value during the present conversion.

CHANNEL EXPANSION
The number of analog input channels of the SDMS56
and SDMS57 can be easily increased by using ~urr
Brown's MPCSD (S channel differential) and MPCI6S
(16 channel single-ended) multiplexers. These are latcbfree devices which contain internal binary decoding at
TIL or MOS levels and may be integrated into a system
with minimal external logic.

SYSTEM TIMING DIAGRAMS
OUTPUT

INPUT

STROBF

---u

u

MUX

ADDRESS

OUT

LOAD

DELAY

OUT

TRiG

BUSY

S H
CONTROL

011 (MSB)

(sampling)

-

-

I

---"----'"

I

25~sec conversion - Ch n

---l- --""7""'\."O -

-

----~-

-

(sampling)

Ll_ _ _ __

----h----

-

"

"I

.... _ - -

===C--'::-l/ .~.!. - - - - - - - - - - --.+-r':::':
_ _ _ L- __
LJ".--

010

~'
I

D9

I

01 {LSDI

1

1

- - - -"""'-,

1

I

-

-

-

-1- -

--1- 1

liiil

l-tO~~i

+FS

_ _-,-IoJ/

SHOUT
·FS

-

~

I

,..

''--

I

-~SB
0 I I I
'

---1:---

SERIAL OUT

r----- --- -~ch;;(jatavaild! ;.-;----,

I ' I

---:----

1/
1
LSB
-""'T~M_-,-,-.,... :-r-..,.-lT- 2' 3 , 4'
' 7 ' 8 , 9 ' IO.L II I 12 ,
-...L--'- ......U... -.I,..; ...... ;...,I-

.

Serial data valid

: • I

:
I

ENAiil'E
1.2.3
DATA OUT

FIGURE 2. Normal Operation

8-83

'------

- ----

---t-------' -_ _ _ _ __

SPECIFICATIONS

DYNAMIC ACCURACY

ELECTRICAL

Sample/Hold Characteristics
Aperture Time
Acquisition Time
Feadthrough (10V step)
Amplifier Charecteristics
(SMD857 only)
Amplifier CMRR at 60Hz. G = 2
G=500
Amplifier Overload Recovery Time

Typical at TA = +25°C and rated power supplies unle~s otherwise opted.
MOOEL

SDM856/SDM857

TRANSFER CHARACTERISTICS

MIN

Resol\.ltion
Number of Analog Channels
Throughput Rate (Normal Mode)
SDM858JG
SDM858KG
SDM857JG
SDM857KG
Throughput Rate (Overlap mode)
SDM856JG
SDM856KG
SDM857JG
SDM857KG

12

TYP

MAX

1~IN/8D.'F

UNITS
Bits

33

35

25
22
18

27
24
20

kHz
kHz
kHz
. kHz

38
27
38
27

40
29
40
29

kHz
kHz
kHz
kHz

·0 to +10 •.±5•. ±10

V

0~Cto+70'C

Offset Current at +25'C
O'Cto+70'C
Input Offsel Voltage
Input Offset Voltage Drift (G tOO)
Output Noise (10Hz - 10kHz)
G = 100. Rs - 500n
Common-mode Rejection (DC)
G=2
G = 1000
Sample/Hold DC Characteristics
Input Impedance
Bias Current
Output Offset Voltage

.n~~

90
95

dB
dB

200

/lS8C

Binary. Offset Binary.
Two's Cpmplement
Non-return to zero (NRZ)
30
25.
520 .

I'S8C
kHz

Digital Output Coding
Serial Output Coding
ADO Conversion Timel"l
Clock FrequencyHiI
Del aye11: SOM856
SOM857

±20
±6

118001171
5 X 10'113
2
500
G = 2 + (2OkQ/REXT''')
±50
±1.1
±20

I

.I

±O.6
±0.1
±4

>

±6

V
V
QllpF
QllpF

nA
nAl'C
nA
nArC
mV

90
97

dB
dB

10'°113
50
7

QllpF.
nA
mV

+2.500
-6.4
±5

+2.510
-6.8
±10'

V
V
ppm/'C

Quantizing Siroi
System Gain Error-141
System Offset Errorl41
Power Supply Sensitivity:

JG
KG

Linearity Drift

±0.1
±0.1
±0.0007
±0.0007
±o.OOl

+15V
-15V
+5V

TEMPERATURE STABILITY
System Accuracy oriftl15l :

±0.024
±0.012

Unipolar
. Bipolar

MIN

TYP

±0.08
±0.024
±0.012
±0.048
±0.024
±0.012
±0.3
±0.3

%ofFSR
% of FSR
% of FSR
%ofFSR
%of'FSR
%OfFSR
%
%ofFSR
%I%AV
%I%AV
%/%AV

MAX

UNITS

±25
±20
±2

ppm/'C

+70
+100

'C
'C

-40
+120
1300
1400

25-99

100:249

174
219
194
242

145
164
154
192

125
158
130
162

~

INPUT

8llSY

STiOiE

~~TROI.
fRiO

I)ElAY

1.0AI>

MlJX

ADDRESS mil
1>11 eMS81

oco

'"
'1O
SERIAI.OUl
+t:s

f~A8I.E

1.2..1

UAIAOl"

pi>m/~C

ppm of
FSR/'C

mA
mA
mA
mA
mA
rnA
mW
mW

1-24

OllT

o

+20
-50
+140
+25
-55
+140
1750 .
1900

PRICES

±0.048 % of.FSR I31
±0.024 %ofFSR
%ofFSR

+10
-35
+120
+15

SDM856JG
SDM856KG
SDM857JG
SOM857KG

""

±0.11

±15.5
+5.25

0
-55

I'A

o
o
o

±15
+5

Specification Temperature Range
Storage Temperature Range

ACCURACY
Throughput Accuracy
to +5V. ±5V ranges JG
to +5V. ±5V ranges KG
io +20mV. ±10mV JG
(SDM857 only)
to +2OmV. ±10mV KG
(SDM857 only)
linearity (G = 1): JG
KG
Differential Linearity (G = 1):

/lSec

V·
V

$
$
$
$

NOTES:
1. RexT is the external gain~se'tting resistor. (Connect· between pins 1 and 80.)
2. External loading of the +2.5V reference output is not recommended.
3. FSR means Full Scale Range. e.g .. FSR is 10V for ±5V range.
4. Adjustable to zero.
5. Includes gain. offset, and linearity drifts.
6. Conversion 1ime and clock frequency can be externally adjusted from 13psec
(fClock = 1.0MHz) to 110psec (fc1ock = 118kHz). Conversion times are for 12-bit
resolution.
7. Can be externally adjusted from 3/lSec to 300IJSec.

REFERENCE VOLTAGES
Output Voltage: Positive
+2.490
-6.0
Negative
Temperature Coefficient
(each oulput)
Current Available for External Loads
r'usiti.a f21
0
-200
NeQstive

/lS8C

ENVIRONMENTAL

I'V/'C
I'V.rms

±14.5
+4.75

Quiescent Current
SDM856. +15VDC
SDM856. -15VOC
SOM856. +5VDC
SDM857. +15VDC
SDM857.-15VDC
SDM857. +5VDC
Power Dissipation: SDM856
SDM857

QllpF

400

15
30

POWER REQUIREMENTS
Rated Voltage for Specified Accuracy

1
1
5X 10'1110

/lSec
mV

OUTP.UTS

ANALOG INPUTS
ADC I nput Voltage Ranges
Mux Input Voltage Range
Absolute max without damage
For linear operation
Mux Input Impedance. OFF Channel
Muxlnput Impedance. ON Channel
Amplifier Characteristics
(SOM857 only)
Input Impedance
Gain Range
Gain Equation
Input Bias 'Current at +25'C

.100
10
±1.4

FIGURE-3.0verlap Operation

8-:84

DIGITAL INPUT SPECIFICATIONS

DIGITAL OUTPUT SPECIFICATIONS

Address Inputs
(AO- Al)

One standard LSlTL load. positive true

P~r~lIel

Address Coding

4-bit binary
One standard LSTTL load. positive true. address loaded on

5 standard TTL loads. positive true. 3-s1atc.

Data

Outputs

Load

2 standard TTL loads. positive true. N RZ. time serial data
output beginning with DII (see Timing Diagram).

Serial Output

positive edge.

Clear

One standard LSTIL load .. negative true,

lo~

5 standard TTL loads. J10sitive true. 3-statc.
5 standard Tn. loads. low during A, D conversion.

level clears

latch.

One standard LSTTL load. high-to-low transition triggers
the delay timer.
TRIG

One standard LSTTL load. a negative going edge initiates the
A 0 conversion.

Short Cycle

One standard I.STIl. load. logical I for 12-bit resolution
connect to 

Ji

'[

5
z: o.os 1------\------,.tfII£:....---j,jI~""7=-_f 100 g

!

t«

0.021------::;o~I!!!::---::::I~"--+_----_f 50
0.01

.....~.....~~.........~

c:::..==c::::~_
I

10

Gain

20
1000

100

~

~

'"c
'"
~

821-----------+-----~

~
«
I

I0

Gain

100

1000

FIGURE 5_ Output Noise vs_ Amplifier Gain

FIGURE 4. Nonlinearity and Settling Time
vs. Amplifier Gain

THROUGHPUT ACCURACY AND TIMING RELATIONSHIPS
System
Gain
V\'
~56

10
100
500

onh,
H57 only
N570nlv
~57 only
N57 only

Systcm
Accurac

rhroughpul Rate (mIni
(Channels scc)
Overlap
J(i
KG
KG

Surmal

KG

J(j

Hi

+0.024(';
+1.).024';
+0.035(";
+O.mw;

+O.04W;
±O.04W"(
+0.06(';
to. I I";

::0.1"';

±O.IY·;

.Uk
22k
22k
10k
2.5k

25k
INk
INk
9k
2.4k

3Nk
JNk
JNk
Ilk
2.6k

27k
27k
27k
Ilk
2.6k

Delay rime (psec)
Ovcrlap

~urmal

J(i and KG

.1(;

KG

15
.\0
.1"

""
"

.15
JS
.l5

."

J90

90
:WO

TABLE IL Throughput rate and delay time vs gain for normal and overlap modes.
Full Scale Input
Range

10V
IV
O.IV
20mV

ADC
Range

Amplifier
Gain

-10 10 +10
010+10
oto +10
o IQ,+IO

2
10
100
SOO

Amplifie'r/ Multiplexer
Settling Time (",sec)

Resolution

2.44mV
244~V
24.4~V
4.88~V

To ±o.2%
8
12
6S
320

To ±o.OS%
10
14
80
390

To ±o.OI%
20
24
90
4S0

TAL .E- IlL This table shows the delay timer setting required to allow for the settling time of the
instrumentation amplifier to the accuracies specified.
In overlap, when the amplifier/multiplexer settling time
is less than the ADC conversion time, set the delay timer
for the- ADC conversion time plus the sample/hold
acquisition time (30 ",sec plus lO",sec). When the

amplifier/multiplexer settling time exceeds the ADC
conversion time plus the S / H acquisition time, set the
delay timer for the amplifier/multiplexer settling time.

,8-85

CONN'ECTIONDIAGRAM "

..

• •
2

0
0
0

o I
0
0

79

·· ·
···

800
0

+I5VDC
0
0
0

··"'64·'·
··
r·•
·
•
•
· o· . . ..· ·•
0

0
0

Ii;F O~cf i

0

.;

CeramIC

0

0
0
0

0
0

0

0

25 :

65
63

•

59
57
55

0

I

0

4P

0

E

18MO

IOkO

15VDC
Unipolar

Bipolar
Gain

0

~

+5VDC
+15VDC

1001l!OO

0

0

0

lPF

0

0

0

0

15VDC

it

• •
• 0
0

Offset

Offset

0

0

0

• 39

0

40

41

42

0

NOTE:
Multiturn potentiometers with IOOppm "C or better TCR's are recom mended for minimum drift
over time and temperature .

FIGURE 6. Connection Diagram for power supply decoupling and gain and offset a4justment.

PIN DESIGNATIONS

n"'·

MECHANICAL

'f,','

IA GAIN ADJUST
MUX OUT HI
,
,IA IN HI
CH7
C.H6
CH5
CH4
CH3
CH2
CHI
CHO
MUX ENABLE 2
MUX ENABLE II A3 OUT
SIN DlI-'
A20UT
AI OUT
MOUT

ffiAR
AO IN

'I
2
'3
4
5
6
7

'80
'7.
78

8

73
72
71
70

9
10
II
12
13
14
15
16
17
18
I.
20

AI IN

.,

A31N
LOAD

2l
2)
24
25
26
27
28

BUSi
DIG COM
SHORT CYCLE
IO.. BIT RESOLUTION
g.. 81T RESOLUTION
DO (LSB)
,
'01
D2

03
04

05
06
D7

08
D9
010

011 (MSB)

2.
30
31
32
JJ
34
35
36
37
.18
3.
40

77
76
75

{4'

'69
68
67
66

65
64
63
62
61
~

59
58
57
56
55
54
53
52
51
50
4.

..

47
46
45
44
43
,42
41

,

IA GAIN ADJUST ,
IA IN LO
MUX OUT LO
CHIS:RET 7
CHI4IRE:r6
CHI3; RETS
CHI2, RET4
CHII iRET.1
CHIO,RET2
CH., RETI
CH8; R,ETO
I AOUT
S,H IN
S, H OFFSET ADJUST
S/H CONTROL
+ISVDC
·15VDC
ANA COM
SHOUT
-6.4V REF OUT
leV R,;:-. I
100M!!. IOpF OFF channel
Input Impedance
100M!!. 100pF ON channel '"
Bias Current
±IOnA. Iyp; ±30nA. max
+2S"C
±20nA. typ; ±6OnA. max
O'C to +70'C
±IOnA. typ; ±30nA. max
Differential Bias Currenl
±O.4nA "C typ; ±1.0nA;"C. max
Differential Bias Current Drift
±2S ±(200 G),.V
Amplifier I nput Offset Voltage. max
±O.75 ±(l0 G),.V "c
Amplifier Voltage Offset Drift. max
±2 ±(200 G)I'V V
vs Supply. max
±2 ±(40 G),.V mo
vs Time
Amplifier Input Noise
Voltage
I.2,.V. pop
O.OIHz to 10Hz
1.0,.V. rms
10Hz to 1kHz
Current
70pA. pop
0.01 Hz 1010Hz
20pA. rms
10Hz to 1kHz
Amplifier Output Noise (G = 100. Rs = SOOn)
0.12mV. pop
0.01 Hz to 10Hz
0.J2mV. rm.
10Hz 1010kHz
O.I~V Vln,"'1
Thermal Feedhack'"
±S,.V
Channel-to-Channel Input Voltage Error'"

8-89

.....
ACCURACY'"
'.
System Accuracy. max (Gain- 1(0)
Linearity
.
'Differ¢ntial Li~earitn(Jain =: 1(0)
.
Quantizing Error

±o.025% FSR'6J al 2kHz Ihroughpul rale
±I112 +. (G/2400)] LSB
±1/2LSB al2kHz)hroughput rate
. ±1{2L.SB
Adjustable .to zero
Adjustable to zero.
:±o.OOS% FSR/%change of supply voltage

G~inError

Offsel Error 1,
Power Supply Sensitivity
STABILITY OVER TEMPERATURE
Syslem Offsel. Drift. max (ZIN .. 400(1)
G.= I
G=IO
"G = 100
G = 1000.
G = 2000
System Gain Drift,!1l max
G=I
G = 10
G =.100
G = 2000
ADC Offset Drift (Unipolar)
ADC Offset Drift (Bipolar)
ADC Linearity Drift

±Sppm of'FSR /"C
±7ppm of FSRj"C
±30ppm of FSR/"C
±300ppm' of FSR!"C
: ±600ppm of FSR,"C
±35ppm of readingj'C
±80ppm of reading/"C
±85ppm of readingj'C
i85ppm of reading/"C
±3ppm of FSRl"C
±ISppm of FSR/"C
±3ppm of FSRj"C

DYNAMIC ACCURACY
Sample/Hold Aperture iime
Sample/Hold Acquisition Time (to 0.025%)
Error for Full Scale Transilion Between
Successively Addressed Channels'
G= I
G = 100
G = 1000
G = 2000
Amplifier CMRR. min; IkO Source Imbalance
G = I. f=6OHz
G = I. f=.lkHz
G = 10. f = 60Hz
G;;' 100. f= 60Hz
Channel Cross Talk
Sampie/ Hold Feedthrough
Sample/Hold Decay Rate. (+70"C)

..

125nsec. Iyp; 200nsec. max
26"sec. Iyp; ·52"seo. max

±ILSB at 8kHz
±ILSB al 2kHz
i2LsB al 1kHz
±4LSB at 500Hz

,.' .'

86dB
70dB
96dB
1000B
-8OdB al 2kHz. OFF channel 10 ON channel
±0.OO7% of 20V
I"V/"sec.IYp; IO~Vi"sec .. ina,,'

OUTPUT
Outpul Coding (Complemenlary)

Unipolar slraig]!t bin.ary. bipolar offset binary.
binary two·s· complement
Adjustable to zero

'Gain Error!!U
Offset Error'"
A/D Conversion Time
Delay
POWER REQUIREMENTS

ArljustAhlp to

7P'f't')

24"sec typo 30"sec max
470"sec nominal. externally adjuslable'"
+ISVDC ±3% at +65mA:ripple < 5.mV. rm&
-ISVDC ±3% at -75mA. ripple < SmV. rms
+5VDC ±5% at 300mA. ripple< 25mV ..rms

ENVIRONMENTAL
Operating Temperature
Storage Temperature
Relative Humidity

O"C 10 70"C
-25"C to +85"C'
95", noncondeosing .

l - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - : : - -....."-

NOTES:
1. With RUT

2.
3.
4.
S.
6.
7.
8.
9.

betw~n pins 26 and 27.
With multiplexer output conn~ted to IA input.
Drift due to internal heating.
Error due to thermoelectric effects of dissimilar metal junctions.
No missing codes guaranteed.
FSR means full scale range.
Exclusive of gain resistor drift.
Gain and offset contro~ are located in the module. The adjustment ranges are ±O.J% FSR for gain and ±o.I% FS,R for offset.
Adjustable to 10 seconds with extern~1 capacitor. to 50psec with an external resistor.
. '

8'-90

DIGITAL INPUT
Address inputs

One standard TIL load. positive true
'One standard TIL load. negative true. address loaded with strobe in Dub.
One standard TIL load, negative true, address cleared with strobe inputs.

LOAD ESABLE
CLEAR ESABI.E
STROBE It. STROBE

One standard TTL load. STROBE and m
counter. STROBE must be hi/!h to enahle ~ and ~ must he low
cnable STR08E.
Two standard TTL loads. po!roilive true, logic "0" allo\\o'S the Strom inpuh to trigger Ihe delay timer. but

to

COUST ESABI.E

prevents the MllX address counter (rom hein, clot.:ked.
AOCTRIOOER

One standard TTL load. a positive Boing edge at fRIG initiates c(ln\'cr!oiun. a ncpti\"c goinB-cdgeat iRi'('i
initiates conversion; T1fTU must be ''0'' 1«.1 cnable TRIG: I"RIG mU!lt be .,'- to cnable ~

SHORT eynE

One standard TIL load. logic ..... for
.
resolution.

Ml!I.T1PI.EXER ESABI.E
Ml'LTIPLEXER ESABLE
S I> SELECT

12~bit

resolution. connected to the N + I bit output for N bit

Two standard TIL loads. logic 10. 00 enables multiplexer output and logic "0" turns off all channels.
Two Slandard TIL loads. logic "I" enables l6-channel sinBIe-ended operation and logic'"O" enables
8"'Channel differential operation.

DIGITAL OUTPUT
~ata

outputs

2 Standard Tn. loads. nctlali\'c truc.
2 Standard r'·I. loads. ne~ati\'e true. time serial data uutput hCBinnin,t!. with 81.

Parallel BI. BI ... 812
SERIAI.Orl

Address outputs

on

DELAY
and DELAY
('LOCKOrT
STATl"S

on

5 Standard TTL loads. positi\'e true.

4~bit binar~

ctlde. internal 2kll pull-up resistoB.

5 Standard TTL loads high (low) durinl.l. the delay periud. trI~en.-d hy S" ROBF and S I ROBt-· input!..

S Standard rn. loads (or synchroniling serial oul dala.
5 St~ndard TTL loads. high durintt tile A () com·cri!\on.

PIN
DESIGNATIONS

MECHANICAL
If\lCI-~ES

DIM

lw
WI

&!

. .,

MILLIMETERS

MAo)!

&',

116.33
75.69

c

A

o
10.61

+ISVOC
ANA COM
CHOIN
CHI IN
CH21N
CH31N
CH41N
CHSIN
CH61N
CH71N
MUXOUT HI

LuAu £"N'A'ilE

COUNT ENABLE
A80UT
MOUT
A20UT
AI OUT

DEi:AYOiiT
STROBE
AOCTRIG
DELAY ADJUST I
RI
NEG REF OUT
POS REF OUT
lAIN HI
G2
01
lAIN LO
IAOUT
STATUS
81 MSB
B3
BS
B7

89
BII

SERIAL OUT
+SVDC

I
2
3
4
5
6
1
8

•

10
II
12

13
14
15
16
11
18
I.

20
21
22
23

76
75
14

13
12
11
10
69
68
61

66
65
64
63
62
61

60
59

SS
51
56
55

·15VOC
S,DSELECT
CH8 IN (RTNO)
CH'IN(RTNI)
CHI0(RTN2)
CH II IN (RTN3)
CH 12 IN (RTN4)
CH 13 IN (RTNl)
CH 14 IS (RTN6)
CH 15 IN (RTNlI
MUX OUT LO
CLEAR ENABLE
MUX ESABLE
A81N
MIN
A2lN
AI IN
DELAY OUT

54

8PO

53
52
51
SO
4.

48
41

Hi IMSii

..

B2

32

45

B4

4.1
42
41
40

B6
B8
BIO
BI2 LSB
CLOCK OUT
DIG COM

26
21

28
29

33
3~

3S
36
31
38

.
39

.270

.330

....

12.19

7.&28"'51(:
6.85
8.38

1.".0
Q

.130

U

.110
3.980

.no

'"

5.81

'.24

•. 32

6.80

Pin numbers' shown for

reference only. Numbe.rs may
nol be marked on package.
NOTE:

Leads in true position within .0 I S"
(.J8mm)R at MMC at seating plane.

AOCTRiG
DELAY ADJUSTZ
R2

30
31

25

loll

ffiiOiiE

COMP IN
GAIN AI>JUST
SHIN
SHOUT
SHORT CYCLE
S HCOSTROl

24

.3OO8A$IC

.."

7671

4-40 thread. 190" (4.83mmi
min. depth. 2 places.

- - I M I o - - - - U - - -....

CASE MATERIAL: Insulated Steel
CONNECTOR PINS: Gold Flashed
WEIGHT: 145 grams (5 oz.)

I

MOUNTING INSTRUCTIONS:
(Mounting flush on PC Card.)

I 1. Use strip connectors or two 14-pin
i

and three 16-pin low profile Ie
sockets (shipped with each unit).

2. Use 4-40 x 3/16" (4.8mm) LG Pan
HD Hardware to secure the SDM858
I to PC Card.

i

8-91

TYPfCAl

PEIlFOFlM~NCECURV'ES'

AMPLIFIER COMMON-MODE REJECTION
VS SOURCE IMPEDANCE IMBALANCE

AMPLIFIER COMMON-MODE REJECTiON
VSSOURCE IMPEDANCE IMBALANCE

,

120

=

r=60Hz

~

E

Q

t;

U),

"'C

Z

ioo

,",

~,

'"'c'"

G=I

,

'.

'

r::oc

:=I~
.~

z

'~ 100t=~~~~---+~~------~
~

G-IOO,

5'

•

G=I

0

::E

Z 80

80~--------~-4~--~-'----4

~

::E

U

u'

0

.~

~

60

60 ..I - - - - - - . . I I O.....-----~IOO

100

10

I

SOURCE IMBALANCE (kn)

SOURCE1MBALANCE(kO)

SYSTEM NOISEVS AMPLIFIER GAIN

AMPLIFIER SETTliNG TIME VS GAIN

100r-------~------~-------T..,

1000 r-~--,----T"""-~-'r""

R, = soon
Bandwidth = 30kHz

i

;;
! 10

;: 320 ~-"--_'_!---~+--,f_.",..._1

"''"(3

::E

i=
z
:::;

z

'0

~
,.."'

~ 100~------~--~~~~~--~~~

'.J

0

Ill,

>

32~

I

_______
,10

...

1...-----.........

0.1 ...___........_ - - -__
'I
10
100

------*-------~

100
GAIN (V'V)

AMPLIFIER'OUTPUT OFFSET
VOLTAGE DRIFT VS GAIN

AMPLIFIER NONLINEARITY VS GAIN

0.01

1000 2000

AMPLIFIER GAIN (V V)

ro----..----...,.--'"""lr-..,...,.

100r-------~-------r------~~

Rli = Source tmpeda~', ,

0.0003 ..
1 - - - - .-::10!:----":'100~----:,1::!000:::-:2000~

10

GAIN (V'V)

100
GAIN (V V)

8-92

1000 2000

MULTIPLEXERS

Burr-Brown multiplexers allow for a very low cost-per-channel figure
in multiple-channel data conversion or data distribution systems. Twc
types are offered-a low-cost, high quality family of dev!ces that range
from 4 to 16 channels and can accommodate either single-ended or
differential signals and a very-fast-switching family, again 'Singleended or differential, for high throughput rate applications. All are
TTL-and CMOS-compatible, have input protection in excess of the
maximum power supply voltages, and can be operated singly or in
multitiered matrices.

9-1

MULTIPLEXERS
,.'

,

..

,..'

Models MPC4, MPCS and MPCJ60ffer over-voltage
protected inputs that can withstand up to 20 voltS
greater than either supply-:-especiaUy important ~hen
input signals are present and MUX power is off. Models
.~,

..

i,l'nput
Deacrtptlon

Model

Protected
Inpula

MPCSS
MPC4D
MPCl6S
MPCSD

1I.•I!,g~i",
4dift8ient141
111.lngle
8 differential .

MPCIIooKG
MPCilOOSG
MPCS01KG
MPC801SG

18.ingle,or
8 dillerentlal
8.lngl8 or
4, dillerential

High
Speed

Channel.

Ranga,
(Ii)

,

±15
:1:15
:1:15

:tIS

!:is,
:!:15
:1:15
:1:;5

I'

MPCgOO and MPC80.1 provide fast settling time for high
throughput rate systems. All models have internal chan,nel selection decoding and IQw leakage current to be
" compaiible with higher accuracy sys~ms.

"oMllI':TIPLSl(~RS '
On :., I
",CroaStalk
R~.(lC8", "("'oIOFF
i\uIX.,,;
Channel Signsl)
Mid}:'.'.
: ,1.81<0
1.8kn,
1.8kO

'0.005
0.005

7500
"7500
7500
7500

',0,004
0.004
0.004
0.004

5/1880
' '5/1880', '

O.OOlf,
0,005

Settling
Time

(100.01'M1)

;~}
, ';'"

" lAftO..

aOo.,...",
aqj)n~
800".'
8OOn...,
;> • ~'

9-2

"

Package

Page

DIP
PIP
,DIP,
;, "DIP

9-3
9-3
9-10
9-10

DIP
DIP
DIP
DIP

9-17
(1-17
9-24
,9-24

BURR-BROWN@

MPC4D
·MPC8S

IElElI

CMOS ANALOG MULTIPLEXERS

FEATURES
• LOW POWER CONSUMPTION
CMOS analog switches
15mW at 100kHz
• PROTECTS SIGNAL SOURCES
Break-before-make switching
• HIGH THROUGHPUT RATE
• RELIABLE MONOLITHIC CONSTRUCTION

DESCRIPTION
The MPC8S is a single-ended monolithic 8-channel
analog multiplexer and the MPC4D is a monolithic
4-channel differential input output multiplexer. The
digital and analog inputs are protected from
overvoltage inputs that exceed either power supply.
These CMOS devices feature self-contained binary
channel address decoding and are compatible with
DTL. TTL. or CMOS input levels. Channel
interaction is eliminated during overvoltage
conditions and also in theevent of a power loss. They
are packaged in a 16-pin DIP and dissipate typically
7.5mW.

International Airport Industrial Park· P.O. Box 11400· Tucson. Arlznna 85734· Tel. (6021746·1111 . Twx: 9tO·952·1111 . Cable: 88RCORP· Telex: 66·6491

9-3

DESCRIPTION"
Digital and analog \rp~ts;a~efa:ilui~ proti:cted from
overvoltages tn.~t ~xceed' the pow~rsupplies pr
" from the loss of power:
'

The ~PC8Sis',asirtgle+ended monolithic 8-channel
analog multiplexer arid the M PC4D is a monolithic
differehtial"inpl1t/optPu(channel analog multiplexer
constriltte"d with faifute-protected CMOS devices.
Transfer accuracies of better than 0.01% canbc: a~!V¢ved"
at sampling rates up to 200kHz from signalsQui'<;es of up.'
to ± 10 volts amplitude.
These DTl/TTl/CMOS compatible devices feature
self-contained binary channel address decoding. An
ENABLE Iin~., i~ also made available ~.hich,lillows tlw
.user to individually enable an 8-channel group (MPC8S)
or a4-channel group (MPC4D) facilitating channel
expansion in either single~triode or multiJiered matrix
configurations.
'

ei~her

High quality, processing is employed to produce CMOS
FET analog channel switches' which have low leakage
current, high OFF resistance, low feedthrough
capacitance and fast settling time,'
T'hese devic~s are housed in compact 16-pi~duai-in-line
packages, and are specified for operation over a O°C to
+'75°C temperature, range, They are pin and package
c'ampatible with the'S08jS09 series.

,. - - - +v- - - - - - - -,

CH
.----'--OB

j'n

I

:f'l;:- ,

,

J,{

':

+-4------l0 Analog
Output

';;

c

.. <

:c,!!,

'"

I

11

I~-="v

A

I

Channel {A
Select
A0
Address
I O"=="-------\.

Select

b+v

Addr~ss

b-v

Enable

or--_-_-_-_-_-_-_-_-_-_--'___ ..:

Ao

x

X

L

L

L

11

2

I(MSB)

v (iN Il

Decoder

FUNCTIONAL'BLOCK DIAGRAM - MPC8S

None

I

TRUTH TABLE -MPC4D

On
Switch

A2

AI

AO

x

X

X

L

,L
L

L
L

L

Il'

I

11

H
H
11
11
11
H
11

2

1.

H

I

L
11
11
H
H

11
L
L
H
11

11
L
H
L
H

EN

None

3

4
5
6
7
8

TRUTH TABLE - MPC8S

AO

-

I

16

-

AI

AO

16

AI

EN

-

2

IS

-

GNn

EN

IS

A2

-v,up .;...

3

14

-

+Vsup

-Vsup

INIA

-

4

13

-

INIB

INI

IN2A

-

5

12' -

IN2B

IN2

IN3A

-

6

II

IN3B

IN3

IN4A

-,.

7

10

8

9

OUTA -

~

IN4B

IN4

OUTB

OUT

MPC4D,PIN DIAGRAM

MPC8S PIN DIAGRAM

94

b+v
I

_ _ _ _ _ _ _ _ _ _ _ _ .Jp - V
til~c=-::,-::-=-::o-:~r:-:-:~

~

"On"
Switch
:Pair

EN

.....

AI g;:;:;:;;:;;=====1

Enable

FUNCTIONAL BLOCK DIAGRAM - MPC4D

AI

LSB)

"Channel { A 0

OGNn

0;,""'*------1

4

6

8

14

GND

13

+V~uP

12

INS

11

IN6

10

IN7

9

IN8

Typical for following: conditions: V

+ = +ISV,

SPECIFICATIONS
n.

V • = -.!iV, R.... . ~ ~ 1000

T" = 2SoC unless otherw~ noted.

~M~P~C~4D~AN~D~M~P~C~8~S--~----------'

ELECTRICAL
MODELS
!INPUT
ANALOG INPUT

Units

Voltagc Range
Maximum Overvoltage

±Is
+v supply +20
-v supply -20

v

±18

mA

16 Pin Ceramic Lead Frame

TOP VIEW

16

9

V

V

8

Cu.rrent at Maximum Overvollage
per channell II

Number of Input Channels
Single-ended
Differential
ON Characteristics

5.0Smm
(0.200") Index Notch, Pin 1

ON Resjstancc (Rm.)

Typical
Maximum
Ro~ Drift VI. T emperat.ure
(ifC to, +75°C)
,
RullO Mismatch
Channel-to-channel
Differential

1,5
1,8

kll
kll

0.2S

%/"C

50

50
50

N/A

Input leakage (II)

0.1
See Figure 9

Input Leakage Drift
OFF Characteristics
OFF Resistance

II
II
nA

lOll

II

0.2
0.02
See Figure 9

nA
nA

(All channels disabled)
Input Leakagct61
Leakage Drift
Output Leakage with Input
Overvoltage

of +35V
of -3SV
-v supply ~ VI. < 0.8 at I nA
+4V .. VH . . + V supply at I nA
3 bit binary
2 bit binary

logic"O" (Vd'U!'
LOlie "I" (VH)IIIW

Channel Select

code - one of

I

L6.350mm_1

!

v

v

Supply Drain
At I MHz Switching Speed
AT 100 kHz Switching Speed
Typical Power Consumption
DC to 10 kHz

±IS

v

+IOto±20
-10 to -~O

V
V

+4. -2

rnA

±o.s

mA

7.5

mW

DYNAMIC CHARACTERISTICS
Gain Error (20 Mflload) maximum
Crosstalk!'!
Settling Time~4!
To ±2mV ±(0.01%)
1"0 ±20mV ±(O.IO%)
Common-mode Rejection (minimum)
Switching Time
Turn ON
Turn OFF
Recovery Time from Inpui Overvoltage
Pulse of 3sV for 100 .....
To 0.01%
To 0.10%

0.01

%

% of OFF
channel signal

O.OOS

N/A

120
0.5
0.3

ISO
IS

OUTPUT
Voltage Range
Capacitance to Ground

Mismatch

V

±15

25

It"'

pF

N/A

±IO

%

TEMPERATURE
Specification
Storage

o to +75
-65 to +150

9.S2mm

+(~~~~.~
.j

+.002
-.002

7.62mrn
(0.300") min

code - one of

POWER REQUIREMENTS

1"(0.250") .,

~ (0.375")max

eight
four
logic "0" (low) disables all channels.
Logic "1'- (high) enableS channel select to
tUTn on selected cha,nnel.

':taled Power Supply Voltages
Supply Range
'+Supply
-Supply

~apacitance

~ ro?;;;,':1~

nA
/'A

DIGITAL INPUTS

Ensble

min.

NOr,lcCUMULATIVE

Output leakage

"C
"C

NOTES:

I. Total power dissipation due to input

overvoltage current flowing in the input
protection circuitry must be limited to
0.75 watt for both (a) normal operation
with power supplies turned on or (b)
during a fault condition when the
supplies are shorted to ground.
2: Maximum overvoJtage is ±Vsupply ±4
volts at ±lS mA_
3_ 20 volt peilk-to-peak 1000 liz sinewave;
RSOURCE = 10000., same signal on all
unused channels.
4. For 20 volts between switched channels,
RSOURCE = 1000R SI;e Figure 5 for
settling time vs_ source impedance (Rs).·
5_ From each side of MPC4D to ground_
6. Leakage measurement made with all
OFF channel inputs fed in parallel to
+20 volts_

DISCUSSION OF"RERFORMANGE
.,$tatic Jr~nsf~r Accu'racy"', .
" ." ,
impedance unbalance. common7mcide irnpedll:l1ce, lo~d;
.bias current mismatch, load differential I impedance
mismatch, and common-mode impedance of the·, load all
contribute errors to the multiplexer. The multiplexer ON
resistance'rriismatch, leakage current mismatch ~nd ON
resistance also contribute to differential errors.
.
The effects of these errors can be minimized by following
the general guidelines described in this section, especially
for low level mUltiplexing applications. R~fer to Figure 2.
LOAD (OUTPUT DEVICE) CHARACTERISTICS
• Use devices with very low bias current. Generaly. FET
input amplifiers should be used for low level signals less
than 50mV RSR. L9w bias current bipolar input
amplifiers are acceptable for signal ranges higher than,
50mV FSR. Bias current matching will determine the
input offset.
• The system DC common-mode rejection (CMR) can
never be be'tter than the combined CMR of .the
multiplexer and driven load. System CMR will be less
than the device which has the lower CMRfigure.
• Load impedances, differential and common-mode,
should be lOW ohms or higher.
SOURCE CHARACTERISTICS
• The source impedance unbalance will produce offset,
common-mode and channel-to-channel gain-scatter
errors. Use sources which do not have large impedance
unbalances if at all possible.
• Keep source impedances as low as possible to' minimize
resistive loading errors.
•. Millimize ground loops. If signal lines are shielded.
ground all shields to a common point at the system
, analog common.
If the M PC4D is used for mUltiplexing high-level signals
of ±I volt to. ±IO volts full scale ranges. the foregoing
precautions should still be taken. but the parameters are
not as critical as for low-level signal applications.

The static or DC transfetaccuracyof transmitting the
multiplexc;r input v.olt,agc; t9 the output .depends .on, the;
channel ON resistance (RpN), the 10ild imped!lnce,the
source" impedance, the iOlld bias current and the
multiplexer leakage current.

SINGLE·ENDED MULTIPLEXER STATIC ACCURACY
The :major contributors to static transfer accuracy for
single-~nded multiplexers. art::
'
Souree resistariceloading error
Multiplexer ON resistance error
DC offset error caused by both load bias current and
multiplexer leakage current,
Rc:sistive .Loading Errors
The ~ource and load impedances wil~ determine the input
resistive loading errOrs, To minimize these errOrs:
• Keep loading impedance as hi~h as possible, This minimizes the resistive loadmg effects of the source 'resistance ,and multiplexer ON resistance. As a guideline,
load impedances of 108 ohms or greater will keep
resistive loading errors to 0.002% or less for 1000 ohm
source impedances. A 106 ohm load impedance will
increase source loading ,er,ror to 0.2% or more.
• Use sources with impedances as low as possible. A 1000
ohm soutce resIStance WID present less than 0.001%
loading error and 10,000 ohin source resistance will
increase source l~ading error to 0.01% with a ro8 ohm
load impedance.
Input resistive loading errors are determined by the
, following relationship: (see Figure I)
Sour~ and Multiplexer Resistive Loading Error
.... ,
E (Rs

,

RS + RON

+ RONl= RS+ RON + R[; x 100%

where RS : : . source resistance
RL = load resistance
.RON,= multiplexer ON resistance

INPUT OFFSET VOLTAGE
Bias current )i;enerates 'ah input' OFFSFT volti'ge as
result of the IR drop across the multiplexer ON resistance
and source resistance.' A load bias current of 10
nanoamperes will generate an offset voltage of20/.N if a
1000 ohm source is used, and 200jL V if a 10,000 ohm
source is used. In general. for the MPC8S;the OFFSET
voltage at the output is determined by:

FIGURE I :MJ'C8S Static Accuracy Equivalent Circuit.

,vOFFSET = (Ib + ILl (RON + Rsl
where [h : : . Bias ~urrent ~f device mUltipl.exer is
IL = Multiplexer. leakage current
RON = Multiplexer ON resista~ce'

~rivin-g

Z load

I

\ RSOURCE;:: Sour~e res~t~~ce ~

DIFFERENTIAL MULTIfLEXER STATIC ACCURACY
Static accuracy errors in a differential multiplexer are'
difficult to control, especially when it is used for
multiplexing low-level signals with full scale ranges of 10
to i 00 millivolts.
.'

J.Io>l>-

iii
a;
c
c

.

Source Resistance (Rs)
(k.l1)

0.1

FIGURE 5. Settling time vs source
resistence for 20 volt step change.

'"u.

u,
u.

0

CiJRVES

"iii

"'

~ 1OO't-----~-'~+;:_--'''''----~

0.01

u

'0
~

'"

;;;

i

° 0.0001"""L._.....~~..L._ _..L._ _..1
U
1

100

lk

60~1----~----~~--~~~~

140r----~--~~---,-----,

10k

. Frequency (Hz)

Signal Frequency (.Hz)

FiGURE 7. CMR vs frequency for
Mililel3660 IA and MPC40 (G = 1000).

FIGURE 6. Crosstalk vs
signal frequency.
"iii
~·100~----~-.~~--~~----~
:;;
u

80~--~----_+~~~--__i

Frequency (HZ)

1::(111111111111

FIGURE 8. Combined CMR vs
frequen~y for Model 3670 IA
(G = 1000) and MPC40.

E 0.6

j:

0.5

~

0.4

~

'0.3

"

~,
"

0.2
3

1.5
Temperature (oC)

FIGURE 9. Leakage current
vs temperature.

~

1.4

Jl'l

1.3

>
~I

-g.!3 •~

1.2

~:~ ~

,1.1

.~ ,!!! iii

• 1.,..

~

~

k ''01.0
o

10

V H (High) Logic U&vel (Volts)

"\.

,,

~

ooc "

T A " 75°C

~

': li:i
ti 0.9
!>;

0.8
i5

5'

tl0"

"

±15,

Supply Voltage (Volts)

FIGURE 11. Normalized "ON" resistance vs supply voltege:

FIGURE 10. Access time vs
.Iogic I,vel, {high!.
'

15

OPERATION & INSTALLATION INSTRUCTIONS
The ENABLE input, pin 2. is included for expansion of
the number of channels on a single node as illustrated in
Figure i2. With ENABLE line at a logic I. the channel is
selected by the 2 bit (M PC4D) or 3 bit (M POlS) Channel
Select Address (shown in the Truth Tables on page 9-4) If
ENABLE is at logic 0, all channels are turned OFF; even
if the Channel Address lines are active. If the ENABLE
line is not to be used, simply tie it to +V supply.
If the + IS volt and; or -15 volt supply voltage is absent or
shorted to ground, the MPC4D and MPC8S
multiplexers will not be damaged; however, some signal
fecdthrough to the output will o~cur. Total package
power dissipation must not be exceeded (see Footn'otel,
page 9-5).

Single vs. Multi-Tiered Channel ~xpansion '
In addition to reducing programming cQm.Ple

To O!h:, ":;PCBS Ch

0

TWO TIER EXPANSION
Using a 4 x 4 2-tier structure for expansion to 16 channels,
the programming is simplified A 4-bit counter outp'ut
does not require a I of 8 decoder. The 2 LSB's of the
counter drive the A" and AI inputs of the four first tier
multiplexers and the 2 MSB's of the counter are applied
to the All and AI inputs of the second tier multiplexer.

Out

8

MPC8S

111

c;
«.

SINGLE NODE EXPANSION
The 32 x I configuration is simply eight M PC4D units
tied to a single node. Programming is accomplished with
a.S bit counter, using the.2 LSB's of the counter to control
Channel Address inputs A" and AI and the 3 MSB's of the .
counter to drive a I of 8 decoder. The I of 8 decoder then
is used to drive the ENABLE inputs (pin 2) of the
MPC4D multiplexers.

IN3

8

Ou

En

2J:
on
+

1.3

DOC'; T A'; 75°C

..,

!I

~.~ ~

~~ a:= ~°

1.2

1.

1

\

~!z ~ 1.0

o

~

~

: a:t

5

10

V H (High) Logic Level (Volts)

~
"0 1.4

~
"C C

0.2

0.9
O.B

+7

+10
Supply Voltage (volts)

9-15

+15

15

INSTALLATION & O,PERATINGINSTRUCTIQNS
The ENABLE input, pin 18, is .included for expansion of
the number of channels on a single-node as illustrated i~'
Figure 5. With the ENABLE line at a logic I, the
channel is selected by the 3-bit (MPC80) or 4-bit
(MPCI6S) Channel Select Address (shown in the Truth
Tables). If ENABLE is at logic 0, all channels are turned
OFF, even if the Channel Address Lines are active. If the
ENABLE 'line is not tobe used, simply tie it to+V supply.
If the +15V and/or -15V supply voltage is absent or.
shorted to ground, the MPC80 and MPCI6S
multiplexers will not be damaged; however, some signal
feedthrough to the output will occur. Total package
power dissipation must not be exceeded (see :\ote I of
Electrical Specifications).

ar~

applied to the Au, A" and A, inputs of the second tier
muliiprexer.

Single vs Multitiered Channel Expansion
In addition to reducing programming complexity, twotier configuration offers the added advantages over
single-node expansion of reduced OFF channel current
leakage (reduced Offset), better CMR, and a more
reliable configuration if a <;hannel should fail in the ON
condition (short). Should a channel fail ON in the single'node configuration, data cannot be taken from any
channel, whereas only one channel group is failed (8 or
16) in the multitiered configuration.

For best settling speed, the input wiring and interconnec~
tions between multiplexer output and driven devices
should be kept as short as possible. When driving the
digital inputs from TTL. open collector output with pullup resistors are recommended (see Typical Performance
Curves, access time).

t{1
:i
;;

TWO-TIER EXPANSION
Using an 8 x 8 two-tier structure for expansion to 64
channels, the programming is simplified. The 6-bit
counter output does not require an 8 of I decoder. The
3L5B of the counter drive the All, A" and A, inputs of the
eight first tier multiplexers and the 3MSB of the counter

Chl '1618~G~r~0~UP~1_ _- ,
IN16
I~na~e
A3A:2A1Ao

Multiplex~r
output

Direct

To
I I
.
Group,
,-- --,
2
I I,........
I

To

I{I
~

«

SINGLE-NODE EXPANSION
The 64 x I configuration is simply eight M PC80 units
tied to a single~node. Programming is accomplished with
a 6-bit counter, using the 3LSB of the counter to control
Channel Address inputs Au. A, and A, and the 3MSB of
the counter to drive an 8 of I decoder. The 8 of I decoder
then is used to drive the ENABLE inputs (pin 18) of the
M PC8D multiplexers.

Group 1

I

CHANNEL EXPANSION

DIFFERENTIAL MULTIPLEXER (MPC8D)
Single or multi-tiered configurations can he IISNI· !'.'
expand multiplexer channel capacity up to 64 channels
using a 64 x I or 8· x 8 configuration.

28t-0~u_t_ _ _ _ _ _-.

MPC16S

I

'"

To preserve common-mode rejection of the M PC80. use
twisted-shielded pair wire for signal lines and inter-tier
connections and. or multiplexer output lines. This will
help common-mode capacitance balance and reduce
stray signal pickup. If shields are used, all shields should
be connected as close as possible to system analog
common or to the common-mode guard driver.

SINGLE-ENDED MULTIPLEXER (MPC16S)
Up to 64 channels (4 multiplexers) can be connected to a
single-node, or up to 256 channels using 17 M PC 16S
multiplexers on a two-tiered structure as shown in
Figures 5 and 6.

IN2
IN3

I
I

'"

I ~':.: ~ ;;-1_-0
I
\...... Buffered
I BB 3550 or 3607J
I

G'guPI

AaA:2A1Ao

Group 4
18 Enable

I

I

MPC16S

I

Group,4

Ch49·64 281'0::;u::t'--'--_ _--::-:-:-::-'
Settling titne to 0.01% for A E;;; 10on.
-Two MPC168 units in parar'el: 10,usec
.... Four MPC8D units in parallel: 12,usec

FIGURE 5. 32 to 64 Channel, Single-Tier Expansion.
. ~

,0 INl

!~t~
o~

;;~

~~\o

IN2
IN3

28 Out

MPC16S
IN16

18

~n

Multi plexer

+V

AoA1A:2A

lil

To

·1

I

Ir

ot~e~ M'p616 Ch

~~

g;

'i(!!i

~ 0 '()

"'-

IN::!

MPC16S

I

I

:,.. __ .,
II,"' ....

28

Enl'" -

18~L.""+""

IN16
. AoAl A:2Aa

INl
IN2

Direct

28 Out

:

Enable Inputs

lOtlO-

Outputs

INl

+V

y Bufforod

BB 3560 or 3607J

lout

MPC1.6S
IN16

18

. AoA1A:2Aa

~.
+v

lI
Settling ti me to

I

0.01 % is 2011sec with
Rs S 10011

I

1
4MSB
4LSB
a-Bit Channel
Address Gen.

J

FIGURE 6. Channel ExpanSIOn up to 256 Channels
Using 16 x 16 Two-Tiered Expansion.

9-16

I

.... ,&.0

BURR .. BROWN®

MPC800

I EEl 13 I

High Speed
CMOS ANALOG MULTIPLEXER
FEATURES

DESCRIPTION

• HIGH SPEED
l00nsec accass time
BOOnsec settling 10 0.01 %
250nsec settling to 0.1 %
• USER-PROGRAMMABLE
16-channel single-ended or
8-channel differential
• SELECTABLE TTL or CMOS COMPATIBILITY
• WILL NOT SHORT SIGNAL SOURCES
Break-before-make switching
• SELF-CONTAINED WITH INTERNAL
CHANNEL ADDRESS DECODER
• 28-PIN HERMETIC DUAL-IN-L1NE PACKAGE

The MPC800 is a high speed multiplexer that is
user-programmable for l6-channel single-ended
operation or 8-channel differential operation and for
TTL or CMOS compatibility.
The M PC800 features a self-contained binary address
decoder. It also has an enable line which allows the.
user to inhibit the entire multiplexer thereby facilitating channel expansion by adding additional
multiplexers.
High quality processing is employed to produce
CMOS FETanalog channel switches which have low
leakage current, low ON resistance, high OFF
resistance, low feedthrough capacitance, and fast
settling time ..
Two models are available, the MPC800KG for
operation from O"C to +75"C and the MPC800SG
for operation from -55"C to +125°C.

A DECODER

As
v·

0

ij

r---...f-0

1~.,10·

ra.97

"

'.01""

.021

c:i.38

0,:53

,.00Q

rO?,O

0.76

,1.l8

5.59

.220
"F

G

.1008ASIC

2.54 BASIC

H.

.030

.095

0.76

.007
.1QO·,

.Q13

.L

.600 BA,SI<:
1.0

M

.020

.090

0.18 '

2:41
0.33

2".64
15.24 BASIC
'-15
0.51

2.29

PIN CONFIGURATION

I

mA
mA

DYNAMIC CHARACTERIST~c::S
Gain'Error
Cross Tal«7)
T OPEN (Break belore make delay I
Access Time at f?5°C
Over!emperature Range
Settling Time(8)
to 0.1% (20mVI
toO.Ol%12mVI
Common~Mode Rejection (Differential I
DC
60.Hz
Channel Input CapaCitance. Cs. (offl
Channel QU!PIJ\ CapaCitance, Co loffl
Inpui Output CapaCitance, CDS 10111

..

Pin numbers snOWI"!. for raferenee only.

INCHES

DIGITAL INPUTS
Over Temperatu're Range
TTLt41
Logic "0" I VAll
Logic "1" (VAH)

'~~

'"

•

V

,.':,?,'j,

OFF Channel Output Leakage Drift
Output Leakage I All
channels disabled 1(31
Output Leakage with Overvoltage
+16V Input
'16V Input

to

CE;';?·t:"E"

1;.;,:ti~iTs

M~'"'"

TYP

••

Maximum Overvoltage
.Number 01 Input Channels
Differential
Single-Ended
Reference Voltage Range(1)
ON Ch~r~~leristics(~1
ON Aesistance I AON I +isoc
Over Temperature Range
RON Drift vs Temperature
RON Mismatch
ON Channel Leakage
Over Temperature Range
ON Channel Leakage Drift
. .,.Qf.F qh~,acteri~tics
OFF Isolation
.OF.F Chamiel Input Leakage
Over Temperature Range
OFF Channel Input Leakage Drilt
OFF Channel Output Leakage

I

MPC800KG, MPCSOOSG .

'

, <0.0003"
See Typical Performance Curves
20
100
ISO
120
200

,

250

%
nsec
nsec
r:lsec:
nsec
nsec

BOO
> 125
>75
2.5

dB
dB
pF
pF
pF

·16

0.02

9-t:8

TOP'"EW
+Vce
OUTB
NC
IN16/8B
IN15nB
IN14/6B
IN13/5B
IN12/4B
INll/3B
IN10/2B'
~N9/1B

GND
VREF

A3

1
2
3
4
5

6
7
8
9
10
11
12
13
14

28
,27
26
25
24
23
22
21
20
19
18
'17

16
15

OUT' A
-Vee
IN 8/8A
IN7nA
INS/6A
INS/SA
IN4/4A
IN3/3A
IN2/2A
IN1/1A
ENABLj;
Ao
A,
A2

MODEL

MPC800KG, MPC800SG

PARAMETER

MIN

TYP

TEMPERA11JRE
Specification

Specification

Storage

UNITS

1. Reference voltage controls noise immunity, normally left open for

TTL compatibility and cO'lnected to'Voo for CMOS compatibility.
2. V,N = ±10V, lOUT = 100"A.

.

MPC800KG
Storage
MPC800SG

NOTES:

MAX

3. Single·ended mode .

0
-65

+75
+t50

°C
°C

-55
-65

+125
+t50

°C
°C

4. Logic levels specified for VREF {pin 13) open.
5. For ,single--ended operation, connect output A I pin 28) to output B
I pin 21 and use A3 (pin 141 as an address line. For differential operation

connect Aa to -Vee
6, Derate 8mWfOC above TA = +75°C.
7. 10V, p-p, sine wave on all un'used channels. See Typical Performance
Curves.
8. For 20V step input to ON channel, into 1k!l load.

TYPICAL PERFORMANCE CURVES
CROSS TALK VS SIGNAL FREQUENCY

OJ

COMBINED CMR VS FREQUENCY
FOR MODEL 3630 AND MPCSOO

LEAKAGE CURRENTS
VS TEMPERATURE

1000

1

c

Ol

iii
1D

0.1

~

()

O.Ot

o

0.001

.><

~

0.0001

l.

I
1: 10 -"OOFF"OUTPUT
~

~

.
.

()

Ol

J:!

-'

/

() 0.00001
100

"ON" CHANNEL

~

/

;l!

~

.;(

V

u..
u..

'0

100

/

c
c

0.1

O.ot

lk

10k

lOOk

1M

10M

-

25

P
35

'"

45

if.

65

-

300

~
c
"E

600

~ 400

200

~

100

..

35

45

55

65

75

Temperature.(OC)

9-19

SETILING TIME VS SOURCE RESISTANCE rl0V STEP CHANGE, RL = lkll

800

i=

0
25

lOOk

75
Frequency (Hz)

1000

i§
z

55

RON DRIFT VS TEMPERATURE

400

S

pl.l'"

Temperature (OC)

Signal Frequency (Hz I

500

-'

f'~ ~

-

I

,10 0.0 \'10 1

I

0\'10'

200

o

~

I

'i

\"'~

/'

V

0.01
0.1
10
Source Resistance I klli

100

1M

DISCUSSION OF
.:PERFORMANCE
STATIC TRANSFER ACCURACY
The static orDc,tr~nsfer accu~cy of transmitting the
multiplexer inpuholtageto the output depends on the
channel ON resistance (RON). the load impedance. the
·source impedance •. the load bias current. and the
multiplexer leakage current.

Single-Ended Multiplexer Static Accuracy
The major contributors to stlltic transfer accuracy for
single-ended multiplexers are:
Source resistance· loading error
Multiplexer ON resistance error
DC offset error caused by both load bias current and
multiplexer le~kage current.
RESISTIVE. LOADING ERRORS
The source andloa+-~-----I----.+-H
Al >7----t+H-l

........-+"-< IN 4A

At

DE·
CODER

...I·-+......... OUTB

........-++< IN 48
1

1
1
1 _____ ,:
L ___________ L
INPUT BUFFER AND DECODERS
MULTIPLEXER
SWITCHES
Internlllonal Alrporllndustrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. 1602) 746-1111 • Twx: 910-952·1111 • Cable: BBRCDRP· Telex: 66-6491

SPECIFICATIONS

ELECTRICAL
At TA = +25°C and ±Vee = 15VDC unless otherwise noted
MODEL

MPCl01KG, MPC801SG

PARAMETER

MIN

TYP

I

MECHANICAL

MAX

UNITS

-15
-Vee -2

+15
+Vee +2

V

4
8
6

10

V

750

n
n

(TOP VIEW)

INPUT
ANALOG INPUT

Voltage Range
Maximum Overvoltage
Number of Input Channels
Differential
Single-Ended
Reference Voltage Range(1)

ON Characteristics(2)
ON Resistance (RON I at +25°C
Over Temperature Range
RON Drift vs Temperature
RON Mismatch
ON Channel leakage

500
700
See TYPica11

OFF Characteristics

OFF Isolatiiin
OFF Channel Input ~eakage
Over Temperature Range'
OFF Channel Input leakage Drift
OFF Channel Output leakage
Over Temperat.u~e Range'
OFF Channel Output leakage Drift
Output leakage (All
channels disabledl@

1000

p"::I~~malnce Curves

~.~

Over Temperature Range

ONChanriei leakage Drift

V

n
nA
nA

50

-~T~T:I

dB
nA
nA

0900.015 _ _ _ _...

,r"~,----,".hD...',
•.

.

. ,

"\ D.'.. ..,...

t

14· OI

I~~~:h
rj'l' "
J', ):".~O;::,
f--0.aoTVP

O.1.8:!:0.003

O.100TYP

11.521

IO.4'!i7 ± 0.0781

12..5-41

See Typical Periorr:nance Curves

I

0.1
0.30

nA
nA

50

See Typical Performance Curves

0.02

nA

<0.35
<0.65

mA
mA

Output leakage wit.h Overvoltage

+16V Inpul
-16V Input
DIGITAL INPUTS

.

Over Temperature, Range
TTlI4)
logic "0" (VAL I
Logic "1." (VAH I

IAH
IAL
TTL Input Overvoltage
CMOS
logic "0" (VAll
logic "I" (VAHI
CMOS Input Overvoltage
Address A20vervoltage

Digital Input Capecitance
Channel Seleell S)
Singl ....Ended
Differential

Enable
POWER REQUIREMENTS
Over Temperature Range
Rated Supply Voltage
Maximum Voltage Between Supply Pins
Total Power Dissipation
Allowable Total Power Dissipation(6)
Supply Drain I +25°C I
At lMHz Switching Speed
At 100kHz Switching Speed

0.6

V
V

1
20
6

~A

0.3VREF

V
V
V
V
pF

2.4
0.05
4
-6

0.7 VREF
-2
-Vee -2

+Vee +2
+Vee +2
5

3-bit binary code one of 8

2-bit binary code on 014
Logic "0" inhibits all channels

~A

V

I

TOPVIEW

I

+Vee [

Cross Talk(7I
TOPEN (Break belore make delay I
Access Time at 25°C
Over Temperature Range

Settling Timet")
toO.l%(20mVI
,to 0.01% (2mVI

18 OOUT A
17 b-vee

V
V
mW
mW

IN8/4B[ 3

16DIN4/4A

IN7/3B[ 4

15DIN3/3A

+14. -12.5
+12.5.-12.5

mA
mA

INS/2B[ 5

14DIN2/2A

IN5/IB! 6

13 b1Nl/1A

J 125
>75
1.9
10
0.02

dB
dB
pF
pF
pF

Common-Mode Rejection I Differential)

DC
60Hz
OFF Channel Input Capacitance. Cs I off I
OFF Channel Output Capacitance. Co ,offl
OFF Input to Output Capacitance. Cos lolf,

1

OUTB[ 2

D,YNAMIC CHARACTERISTICS
Gain Error

:IE

PIN CONFIGURATION

9:..25

GND[ 7

12 b ENABLE

VAEF[ 8

11

A2[

9

10

b
b

Ao

A,

ELECTRICAL (CONT)
MPC801KG, MPC80.1SG

MODEL
;

J

..PARAME:rER

:ryP

MIN

1II0TES:.:

,.MAX

UNITS

TEMPERATURE
MPC801KG
Specification

Sioragll
MPC801SG
Specificati0r:t

Siorage

0

+75

-65

+150

·C
DC

-55
-65

+125
+150

°C
°C

1. Reference

.

voltage .controls nOise tmmunity. normally teft open for

.TTL. compatibility and connected to Voo for ~""Qs ~!!fO~ibility. '
2, VIN = :tl0V, lOUT = 100~A,
.
3, Single-ended mode.
4, Logic levelsspecified forVAEF (pin81 open.
5. For single~ended operation. connect output A (pin 18) to output B
pin 2 and use A2 ~pin 9) 'as an address line. For differential'operation
connect A2 to -Vee,
S. Derale 8mWI"C above TA = +75°C.

Y

7. 10V, p.p. sine wave on all unu.sed channels. See TYPical Performance
Curves.
8, For20V slep inpullo ON channe,j, inlO lkU load.

TYPICAL PERFORMANCE CURVES
CROSS TALK VS SIGNAL FREOUENCY

LEAKAGE CURRENTS
VS TEMPERATURE

1000

COMBINED CMR VS. FREQUENCY
FOR MODEL 383Q AND MPC801
140,...---.----.----,---...,.----i

G = 000
0,1

1
o

/

0.01

0.00 1

0.000 1

lk

"OF

,--

8.
IV

......

...J

10k
lOOk
1M
Signal Frequency Hz

1000

OU~PUT

::l

V

0 0 ,00001
100

C 10
~
0

/

~

~
:::
e

"QN" CHANNEL

c

V

u..
u.

o

'0

100

..:

f"~ ~

0.1

~

0,01
25

10M

~
35

601--+-~

55
45
Temperature °c

SETTi.'ING TIME VS SOURCE RESIS- '
TANCE,120V STEP CHANGE I Ri. = lkfl

I. ,

,

I

I

,~.
c

'1iOtl

~

g'400

!

200

75

~LO---l~00~--~--~10~k----lOO~k--~IM
Frequency Hz

500 .

RON DRIFT VS TEMPERATURE

-

400

800

". ,

65

-

-

°

iO G.O''''

-'

=:

~

,/
\o~

~

.~ 200

a:

V

100

,
0.01

0.1

300

'1

10

°

100

25

Source Resistance kn

9-26

35

55
45
Temperature ,oC

65

75

Differential MuHlplexer Static Accuracy

DISCUSSION OF
, PERFORMANCE

Static accuracy errors in a differential multiplexer are
difficult to control. especially when it is used for multiplexing low level signals with full scaleranges of 10m V to
lOOmV.
The matching properties of the multiplexer, source and
outpuf load playa very important part in determining the
transfer accuracy of the multiplexer. The source impedance unbalance. common-mode impedance, load bias
current mismatch. load differential impedance mismatch,
and common-mode impedance ofthe load all contribute
errors to the multiplexer. The multiplexer ON resistance
mismatch, leakage current mismatch and ON resistance
also contribute to differentia.l errors .

STATIC TRANSFER ACCURACY
The static or DC transfer accuracy of transmitting the
multiplexer input voltage to the output depends on the
channel ON resistance (RON), the load impedance, the
source impedance, the load bias current, and the
multiplexer leakage current.

Single-Ended Multiplexer Static Accuracy
The major contributors to static transfer accuracy for
.single-ended multiplexers are:
Source resistance loading error
Multiplexer ON resistance error
DC offset error caused by both load bias current and
multiplexer leakage current.

Referring to Figure 2, the effects of these errors 'can bl::
minimized by following the general guidelines described
in this section, especially for low level, multiplexing
applications.

RESISTIVE LOADING ERRORS

Load (Output Device) Characteristics

The source and load impedances will determine the ON
resistance loading errors. To minimize these errors:

• Use devices wit h very low bias current. Generally. FET
input amplifiers should be used for low level signals
less than 50mV FSR. Low bias current bipolar input
amplifiers are acceptable for signal ranges higher than
50mVFSR. Bias current matching will determine the
input offset.

• Keep loading impedance as high as possible. This
minimizes the resistive loading effects of the source
resistance and multiplexer ON resistance. As a guideline, load impedances of lOin or greater will keep
resistive loading errors to 0.002% or less for 1000n
source impedances. A 106n load impedance will
increase source loading error to 0.2% or more.

• 'The system DC cOrnmon-mode rejection (CM R) can
never be better than the combmed CMR of the
multiplexer and driven load. System CM R will be less
,than the device which has the lower CMR figure.

• Use sources with impedances as low as possible. A
looon source resistance will present less than 0.002%
loading error and IOkn sour~e resistance will increase
source loading error 0.02% with a 108n load
impedance.

• Load impedances, differential and common-mode.
should be 10IOn or higher.
RSI

Input resistive loading errors are determined by the
following relationship (see Figure I):

_IBIAS

RoN

(Rs + RON) =

Rs =
Rl.
RON

;=

=

,MfASUREO
VOLTAGE

,
I

RSB

Rs + Ros
x 100% where
Rs+ RON + Rl.

~!:!l~

ROFF

Vm

I
I

I

I
I

Source and MUltiplexer Resistive Loading Error
E

-,

r--

ILl

I
I
I

_..J

R.sour~(

Load resistance
Multiplexer ON resistance.

FIGURE I. MPC801 Static Accuracy Equivalent Circuit
(Single-ended Operation).

Input Offset Voltage
Bias and leakage currents generate an input Offset
voltage as a result of the IR drop across the multiplexer
ON resistance and'source resistance. A load bias current
of 10nA, a leakage current of I nA. and an ON resistance
of 700n will ~enerate an offset voltage of 19J.L V if a
1000n source IS used, and 118J.LV if a 10kn is used. In
general, for the MPC801 the Offset voltage at the output
is determined by:
.'
VOFFSET = (18 + Id(RoN

RSIA

RoNIA

'BIASA

r"'~~y.........--==-o.:.-:.;-~-:..;-

'loA)

: COI2

--

ROI2

,
,COI2

I~BI

,

-

zwol
,
I
I
CC. :
I

IL,- _ _ _ _ _,
___
-'

+ R.... ",) where

18
= Bias Current of device multiplexer is driving
IL
= Multiplexer leakage current
RON = Multiplexer ON resistance
R,o"", = Source resistance.

9-'1.7

FI G U RE 2. M PC80 I Static Accuracy Equivalent Circuit
(Differential Operation).

':'~:.'."'.

: ~

H~£"

,""
.~:.",~.
;'~i
, " , "'"
',,,

,.,.• ,'" ...:.)t,/

Source Ch.raderlltlcti , " "

n

• ,Thlsouic~ impedance unbalance'will produce offset,'
'commori-mode and chanrieJ"to-chil'illiel gain scatter
erro'rs. Use sources'whiCh do notha ve large impedance
unbalances if at all possible.
',. ,"
• Keep source impedances'as' low-as possi ble to minimize
'resistive loading'errors, :'"
• Miniinizeground loops,: If signal lines are shielded.
g'round all 'shields to a common point at'the, system
analog corilrriori.
If ~he M PC'SO I is~sed j-or mUltiplexing higlilevelsignals
on V to,lQY full ,scale ranges, the foregoing precautions
should siilfbe taken, but' the paralnt!ters are not as critical
as for low level signal appliCiltions
SETTLING TIME
Settling time is the timnequired for the multiplexer to
reach and maintain an output 'within a specifi.ed error
band of its final value in response to a step i'op lit , The
settling time of Ihe MPCSOI is primarily due 10 the
channel capacitance and a combination :,of resistances
' "
which include the source and load resistan~es,
If (,he parai\eI combination of.lh,e ~ou~ce and I~ad
resistance times the totlJ,1 channe,l capaci,ianceis kept
small, then the seHli~g 1ime, is, 'primarily ;lffected by
internal RC"s, For the M P(80 I the internal capacitance
is approximately 10pF differential or 20pF single-ended.

I:'

-

1

FIGURE 3, Settling Time Effects (Singi'e..,ended).

·<,'Y ~/.~ {> ~.,~~'::~~;1

"~ ..,', ":' f'-;,

( ..

With external capacitance neglected, th.e tmle cO.nstiHitof
source resistance in parallel w\;h,:I~a'd }~§i$l~n~ehriihbe:
internal capacitance should be k,ept!~ss th,lln 40psec, This,
means the source resistance 'shOUld be Rept to less "than
4kH (assume high load resistance) to maintain fast
settling tim~s,
ACCESS TIME
This is the time rt!quirt:d for the CMOS FET,io turnON
after a new digital code has been applied to the Channel
Address inputs, It is measured from the 50 percent point
of the addressinpu! signal to the90perbent ,point of the
analog signal seen at,the output for a lOY signalchange
between channels.
'

CROSSTALK
Crosstalk is the'amount of signal fe~dthrough from the 3
differential or 7 single-ended OFF channels appearing at
the multiplexer output. Crosstalk is caused by the voltage
di~ider effect of the OFF channel, OFF resistance,
and junction capacitances in series with the RilN and
R,o"", i'mpedances ,of the ON channel. Crosstalk is
measured with a'2QV, pk-pk, 1000Hz sine wave applied to
all OFF channels.The crosstalk for these multiplexers is
shown in' the Typical Performance Curves.

COMMON-MODE REJECTION (DIFFERENTIAL
MODE ONLY)
The rriatching properties of the load; ~ultiph:xer and
sO'urce affect the 'common-mode rejection (CM R)
capability ofa differentially'multiplexed'system. CMR is
the ability of the multiplexer and input amplifier to reject
signals that are common to both inputs, and to pa~s on
only the signal difference to .the output, ,Protection is
provided for common-mode signals of ±2Y, above the
power supply voltages with no damage to the analog
switches,

The CMR of the MPCSOI and Burr-Brown's model 3630
Instrumentation Amplifier is 120dB at DC to 10Hz wit,h a
6dB/ octave rollofftoSOdB'at 1000Hz, This measurement
of CM R is shown in the Typical P~rforrn'ance Curves and
is made with a Burr-Brown modeI.3630instrumeritation
amplifier connected foria gain-of 1000 and with source
,unbalance of IOkfl, I kO and no unbalance,
Factors whicli will degrade multiplexer and system DC
CMRare:
'
~ Amplifier bias 'current and differential impedance
misl1)at~h,

'

,

• Load impedance mismatch.
"
'
• Multiplexer impedanceandleaka~e cl,lrrent mismatch.
FIGURE 4. Settling and Common"Mode Effects
( Differential),

9-28

TRUTH TABLES
MPCSOI llsed as8-channel single-ended multiplexer or
4-channel dual multiplexer.

• Load and source common-mode impedance ..
AC CMR rolloff is determined by the amount of
common-mode capacitances ·(absolute and mismatch)
from each signal line to ground. Larger capacitances will
limit CMR at higher frequencies; thus, if good CMR is
desired at higher frequencies, the common-mode capacitances and unbalance of signal lines and multiplexer to
amplifier wiring must be minimized. Use twisted-shielded
pair signal lines wherever possible.

USE A2 AS DIGITAL
ADDRESS INPUT

INSTALLATION & OPERATING
INSTRUCTIONS
The ENABLE input, pin 12, is included for expansion of
the number of channels on a single-node as illustrated in
Figure 5. With the EN ABLE line at a logic I, the channel
is selected by the Channel Select Address (shown in the
Truth Tables). [f ENABLE is at logic 0, aU channels are
turned OFF, even if the Channel Address Lines are
. active. If the ENABLE line is not to be used, simply tie it
to logic I.
For the best settling time, the input wiring and interconnections between multipl~xer output and driven
devices should be kept as short as possible. When driving
the digital inputs fr.om TTL, open collector output with
pullup resistors are recommended.
To preserve common-mode rejection of the M PCSO I use
twisted-shielded pair wire for signal lines and inter-tier
connections andlor multiplexer output lines. This will
help common-mode capacitance balance and reduce
stray signal pickup. [f shields are used, all shields should
be connected as close as possible' to system analog
common or to the common-mode guard driver.

"ON" CHANNEL TO

~

A1

Act

" OUT A

X

X

X

NONE

NONE

H

L

L

L

IA

NONE

H

L

L

H

2A

NONE

H

L

H

L

3A

NONE

H

L

H

H

4A

NONE

H

H

L

L

NONE

)B

H

H

L

H

NONE

2B

H

H

H

L

NONE

3B

H

H

H

H

NONE

4B

ENABLE
L

OUTB

For a-channel single-en.ded function. tie "out A" to "out 8", for
dual 4-channel function use the A2 address pin to select between
MUX A and MUX B. where MUX A is selected with A2 low.

MPC801 used as 4-channel differential multiph;xer.
A2 CONNECT TO .VCC
ENABLE

.~

.

"ON" CHANNEL TO

Act

OUT A

OUTB

X

NONE

NONE

l

lA

IB

H

2.0. .

2B

L

X

H

L

H

L

H

H

L

3A

3B

H

H

H

4A'

4B

I

CHANNEL EXPANSION

LOGIC LEVELS
The logic level is user-programmable as either TTLcompatible by leaving the VREF (pin S) open or CMOScompatible by connecting the VREF to VI>I> (CMOS
supply voltage).

Single-tier Expansion
Up to eight M PCSOI 's can be connected to a single node
to form a 64-channel single-ended multiplexer or up to
eight M PCSOI 's can be connected to two nodes to form a
32-channel differential multiplexer. Programming is
accomplished with a 6-bit address and a I of 8 decoder
(Figure 5). The decoder drives the enable inputs of the
M PC80 I, turning on only one multiplexer at a time.

8-CHANNEL SINGLE-ENDED OPERATION
To use the MPCSOI as an S-channel single-ended multiplexer, output A (pin IS) is connected to output B (pin 2)
to form a single output, then all three address lines (Ao,
A" and A,) are used to address the correct channel.
The MPC801 can also be used as a dual channel singleendeCl multiplexer by not connecting output A and B, but
then only one channel in one of the multiplexers can be
addressed at a time.

Two-tier ExpansIon
Up to nine MPC801's can be connected in a two-tier
structure to form a 64-channel single-ended multiplexer
(Figure 6) or up to five M PC80 I 's can be connected in a
two-tier structure to form a 16-channel differential
multiplexer. Programming is accomplished with a 6-bit
address.
SINGLE VS MULTITIERED CHANNEL EXPANSION
[n addition to reducing programming complexity, twotier configuration offers the added advantages over
single-node expansion of reduced OFF channel current
leakage (reduced Offset), better CMR, and a more
reliable configuration if a channel should fail in the ON
condition (short). Should a channel fail ON in the single-

4-CHANNEL DIFFERENTIAL OPERATION
To use the MPCSOI as an 4-channel differential multiplexer, connect address line A2 to -Vee then use the
remaining two address lines (Ao and Ad to address the
correct channel. The differential inputs are the pairs of A,
and B" A2 and B" etc.

9-29

node configuration, data cannot b¢ ~,tak~n 'fr()m any .
channel, whereas only one channel groupis'fliiJetl( 4hr 8)
in the multi tiered configuration.

I

i{
...

8-BIT CHANNEL
ADDRESS GENERATOR

II
At! At

:::

IN1
AI
IN2
0- IN3 MPCBDI

~

0- IN8

ENABLE
OUlA
OUTB ,.J

I

ill
IGl8
DECODER

I

MULTIPLEXER
\'

OUTPUT
IN8

,.'

;i{
...""

~ IN2

II

INI AO AI A2

MULTIPLEXER
OUTPUT

I

0- 1M3 MPCBDI

0- IN8

ENABLE
DUTA
OUT B ,.J

~

TO MULTIPLEXERS 3 • 8

FIGURE 6. 64-channel. Two:Tier. Single~Ended
Expansion.

~

TO MULTIPlEXERS 3 • 8

FIGURE 5. 64-Channel, Single-Tier. Single-Ended
.
Expansion.

9-30

VOLTAGE TO FREQUENCY
CONVERTERS',

VFC's provide a simple, low cost way of converting analog signals into
digital form. They provide an important alternative to other analog to
digital conversion techniques. Their integrating input properties make
them an appropriate choice when operating in noisy environments.
The combination of high accuracy and linearity, low temperature drift,
and monotonicity often provide performance characteristics unattainable with other techniques.
Since an analog quantity represented as a freqI,Jency is inherently
serial data, it is easily handled in large multi-channel systems. Frequency information' can be transmitted over long lines with excellent
noise immunity using loW cost digital line transmitters and receivers.
Isolation can be accomplished with optical or transformer couplers
without loss in accuracy. Outputs from multiple VFC's can be gated to
common counter circuitry with simple digital logic.
Burr-Brown monolithic VFC's include the VFC32, VFC62, and VFC320
which provide industry standard performance and reliability in such
applications as preciSion test and measurement equipment, data
acquisition systems, and communications equipment.

10-1

IE

,

,,) ",,:'

,"

.':; ,."

;,

,'"

Description

ModelUl

Low Cost,
Monolithic

VFC32KP
VFC32BM, (0)
VFC32SM, (0)

Military
Hybrid,
Complete

High

Performance,
MonolithiC

Frequency
Range
(kHz)

VIN
Range
(V}

User"
selected,
5OOkl'lz, max

Usar.'
selected

Oto 10
01010
Oto 100
Oto 100

Oto+l0
Oto+l0
Oto+l0
Oto+l0

",

.

VFC62BG
VFC62BM
VFC62SM
VFC62CG
VFC62CM
VFC320BG
VFC320BM
VFC32OSM,
VFC320CG
VFC320CM

"

..,~ ,"'.II)M,","

,~,

~"

(.

Linearity
('!Io of.FSR) max

Tempeo
(ppm of FSRI"C)
max

Temp'
Range«lt

Packig,e

Page

±C:Ol 'at 10kHz .
:;1:0,05 at .'.OOkHz
'±C,2 at 500kHz

75typ
::;1:100
:;1:150

Com
tnd
MIL

DIP
TO-'l00
TO-l00

1().3
10-3
1().3

Ind
,MIL
}\nd ',"

DIP
DIP
DIP

10-11
10-11
10-11
10-11

:DIP
TO-l00
T0100
DIP
To-l00
DIP
To-l00
TO-t\lO
DIP
'TO-l00

10:17
10-17
10-17
10-17
10-17
10-25
10-25
10-25
10-25
10-25

, VFC32IMIL series
VFC42BP
VFC42SM
VFC52BP.
VFC52SM

.
;';"

vlfidtlNVEATERS ':

See 'M,lIItary ProcIucta

'
Usar" .:
selected,
1MHz max

Userselected,
lMHz max

",' ~

User-

~ed

-,:, ,''':

Usersalected

±a,01

"

±C,01.'
:;1:0,05
±C,0Jj
±O,OO5 at 10kHz
±C.OO5 at 10kHz

:;I:O.~at'I\k~· ;'
±C.oozat:~~ :
:;1:0.002 at: 10kHz
:;I:O.OO5:at, 10kHz
:;1:0,005 at 10kHz
:;1:0.005 at 10kHz
0-:;1:0.002 at 10kHz
,*0.()Q2 al,10k!lz
'c

*;100
'''±100,
:;1:150
:;1:'150·

Mit',;,"

:;1:50'
:;1:50
'*50
:;1:20
:;1:20
:;1:50
:;1:50
':;1:50
:;1:20
:;1:20

"

NOTES: (1) "(0)" indicates product also available with screen~g,lori~ree.ed reliability. See 0 Program.
-25"C to+65"C; MIL = -55"C to +125"C.
'.
, ..

1'0-2

, lnd
Ind
:MtL
Ind
Ind
I,nd
hid
MIL
Ind
Ind
(2) Com

DII~

r

=°to +70"C; Ind =

BURR-BROWNI!!l

IElElI

••

VFC32

VOltage-to-Frequency
and Frequency-to-Voltage
CONVERTER
FEATURES

APPLICATIONS

• RELIABLE MONOLITHIC CONSTRUCTION
• HIGH LINEARITY
±O.01%max at 10kHz FS
±O.05% max at 100kHz FS
• V/F OR F/V CONVERSION
• 6-DECADE DYNAMIC RANGE
• VOLTAGE OR CURRENT INPUT
• OUTPUT DTL/TTL/CMOS COMPATIBLE

• INEXPENSIVE A/D AND D/A CONVERTER
• DIGITAL PANEL METERS
• TWO-WIRE DIGITAL TRANSMISSION WITH NOISE IMMUNITY
• FM MOD/DEMOD OF TRANSDUCER SIGNALS
• PRECISION LONG TERM INTEGRATOR
• HIGH RESOLUTION OPTICAL LINK
• AC LINE FREQUENCY MONITOR
• MOTOR SPEED MONITOR AND CONTROL

DESCRIPTION
The VFC32 monolithic voltage-to-frequency and
frequency-to-voltage converter provides a simple
low cost method of converting analog signals into
digital pulses. The digital output is an open collector
and the digital pulse train repetition rate is proportional to the amplitude of the analog input
voltage. Output pulses are compatible with DTL
TTL. and CMOS logic families.
The converter requIres two externai resistors and two
external capacitors to operate. Full scale frequency
and input voltage are determined by one resistor (in

series with -IN) and two capacitors (one-shot timing
and input amplifier integration). High linearity is
achieved with relatively few external components,
c.g .. :to.OI"; at IOkHt. The ot'lcr rcsistor is ~ nOI1critical open collector pull-up (f,wl' to+Vcd.
The VFC32 is available in three models and two
package configurations. The TO-IOO versions are
hermetically sealed, and specified for the -25"C to
+85"C and -55"C to + 125"C ranges, and the 'epoxy
dual-in-line unit is specified from O"C to +70"c'

'OUT

International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734 . Tel. (6021746·1111 • Twx: 9t1).952·t 111 . Cable: 8BRCORP • Telex: 66·6491

10-3

SPE.CIFICATIONS
EI:-E(:TRICAL
At TA = +2S·C and +ISVDC power supply unless otherwise noted
.'

I

',",

CONDITIONS

CHARACTERISTICS
INPUT (V/F CONVERTER)

I

YfC32KP .

I

MAX

TYP

MIN

FOUT =VIN 17.S R,C" Figure 6

Voltage Rangel')
Positive Input

.20
3001110

1
650 1110

300 113

500 II 3'

501110

.~

TYP

UNITS

lpo

,

:.

,

"

,

.'

MOil pF

,

"

,

-0.05

,

150klF~A)

0,1.

.

nA
nA
mV
kllil pF

,

.j

15011 io
+1:0

V
rnA

,

,',
"

VOUT = 7.5 R,C, FlN,Figure 9

Logic "1"
Logie "0"
Pulse-width Range

r

'V

250 "

100

Impedanc~

I

WC32BM

'+MI~

"

+D.25mA,
xR,
-10
+0.25

>0
>0

INPUT (FlY CONVERTER)

MAX

TYP

'J

>0

Negative Input
Current Rangel')
Bias Current
Inverting Input
Nonlnverting Input
Ollset Voltage(2)
Dillerentiallmpedance
Common-mode
Impadance

I

YfC32BM
MIN

.

kllll pF

,

V
!,sec

V

ACCURACY

Linearity Erro~'

0.01 Hz Soper
freqSl0kHz
O.IHz:s oper
Ireq :S, 100kHz
0.5Hzs oper
Ireq S 5OO.~Hz

±0.005
±0.025

.

±O.OS

,

.

±O.OS

Ollset Error Input
Offset Voltage(2)
Ollset Drift(6)

I

'Ib 01 FSR
,

'Ib 01 FSR

4

mV'
ppmolFSRfOC

±3

Gain Error(2)
Gain Dr)II(S)
Full Scale Drift
'ollset drift &
gain drift,ISI(7)

:

'lbof FSRI5)

±0.01014)

1= 10kHz

S
±7?

±50

±100

±70

±IS0

''Ib of FSR
ppmfOC

1= 10kHz

±75

±50

±IOO

±70

f150

ppm of FSRfOC

f = DC, ±Vcc = 12VDC
to 18VDC

J'P'I'erSupply
• Sensitivity

'Ib01 FSR/'Ib

±o.o15

OUTPUT (V/F CONVERTER) (open colleclo; out"'!')
Voltage, Logic "0"
Leakage Current,
'Logic "1"
Voltage, Logic "1"
Pulse Width
Fall Time

ISINK ""-SmA

0

Vo = ISV
External pull-up resistor
required! see Figure 4 I
For Best Linearity
loUT = SmA, c..OAD = 500pF

0.2

0.4

0.01

1.0

.
.

,

Vpu
0.2S/FMAX
400

"

,.

'

;,'

10 S. 7mA
Vo S 7VDC
Closed100p
Without oscillation

V
sec

nsec'

)

OUTPUT (FlY CONVERTER) VOUT
Voltage
Current
Impedance
Capacitive Load

V
I'A

V
rnA'

Oto+l0
+10 :

II

1
100,

pF

DYNAMIC RESPONSE
Full Scale Frequency
Dynamic Range
Settling Time
Overload Recovery

5001S)

kHz'
decades

6
,VlF, to spacilied linearity
lor a lull scale Input step
< 5Q'Ib ove,rload

19'
19'

I

POWER SUPPLY
Rated Voltage
Voltage Range
Quiescent Current

±15
±11

±6.0

V
V
rnA

.

.,

TEMPERATURERA"GE
Specification
Operating
Storage

.

±20
±5.is

O·
-25

-25

+70

-2~

+85
+85

-55
'65

'Specification the .ame as VFC32KP

10-4

+85
+125
+150

-55
.-55

-85

. +125
+125
+150

·C

·C
·C

NOTES:
1. A 25% duty cycle (O.25mA input current) is recommended·where possible to achieve best linearity.
2. Adjustable to zero. See Offset and Gain Adjustment section.
3. Linearity error is specified at any operating frequency from the straight line intersecting 90% of full
scalefrequencyandO.1% of full scalefrequ'ency. See Discussion of Specifications section.
Above 200kHz. it is 'M:llmrll~nded a" grades be operated below +8S o C.
4. ±O.01S% of FSR for negative inputs shown in Figure 7. Positive in.,utS are shown in Figure 6.
5. FSR = Full Scale Range (corresponds to full scale frequency and tull scale input voltage I.
6. Exclustve of external components' drift.
7. Positive drift is defined to be increasing frequency with increasing temperature.
8. For operation above 200kHz up to 500kHz, see Discussion of Specifications and Installation and Operation sections.
g. One pulse of new frequency plus 1/lsec.

ABSOLUTE MAXIMUM RATINGS
±22
SOmA
+20mA
±Supply
±Supply
±Supply

Supply Voltages
Output Sink Current (FOUT)
Output Current (Vo",)
Input Voltage. -Input
Input Voltage. +Input
Comparator Input
Storage Temperatura Range
VFC32BM, SM
VFC32KP

-6S'C to +1&0'C
-2S'0 to +85'C

MECHANICAL ,
VFC32KP
EPOXY DUAL-IN-LiNE

VFC32BM, VFC32SM
TO-100 PACKAGE

rF~~

NOTE:
Leads in true position within
0.10" 10.2Smm, R at MMC at
seating plane.
Pin numbers shown for
reference only,
Numbers may not be
marked on package.
INCHES

MIN

MAX

N

Plane

~D

INCHES

DIM

.370

.305

.335

7.75

9.40
8.51

A

.165
.016
.010

.185

4.19

4.70

B

.021

0.41

0.53

C

.04.

0.25

1.02

J>4O
.230 BASIC
.034
.028

...--"

M

z.~

.335

.010
G

.029
.500
. 120
.160
36° BASIC
.110
.120

8.51

NOTE:
Leads in true position within
0.10" '0.2Smm. Rat MMC at
seating plane.

N

0.25
1.02
5.84 BASIC

MIN

MAX

660

.785

16.76

19.94

.220

5.59

,D

.015

.2BO
.200
.023

03.

070

G

.100SASIC

2.54 BASIC
0.76
0.20

0.71

0.86

H

0.74
12.70
3.05

1.14

J

.030
.008

K

.100

L

.300 BASIC

....

M

36° BASIC
2.79
3.05

MILLIMETERS

MAX

MIN

N

.20

.095
.015

7.11
5.08

0.38
0.76

0.58
1.78
2.41
0.38

2.54
15°

762 BASIC
15°

.050

0.51

1.27

PIN CONFIGURATIONS
VFC32BM. VFC32SM
TO-HlQ PACKAGE

-Vee

VFC32KP
EPOXY DUAL-IN-LiNE PACKAGE
-IN

+IN

NC

VOUT

NC

+Vee

COMMON

ICASEI

-Vee

COMMON

ONE-SHOT
CAPACITOR

COMPARATOR
INPUT

NC

NC

(TOPVIEWI'
NC
NC = NO INTERNAL CONNECTION.
EXTERNAL CONNECTION PERMITTED.

ITOPVIEWI

10-5

DISCUSSION OF
SPECIFICATIONS
LINEARITY
Linearity is the maximum deviation of the actual transfer
function from a straight line drawn .between the end
points (90% of full scale input or frequen,cy and 0.1% of
full scale called zero). Linearity is the true measure of
voltage-to-frequency converter's performance, and is a
function of the full scale frequency. Refer to Figure I to
determine typical linearity error' for your application.
For a given full 'scale frequency. the linearity error
decreases with decreasing operating frequency as shown
in Figure 2. Also. best linearity is achieved at lower gains
(.lFol"l/.l VIS) with operation as close to the chosen full
scale frequency as possible,
.
The high linearity of the VFC32 makes the device an
excellent choice for use as the front end of A/ D
converters with 8- to 12-bit resolution, and for highly
accurate transfer of analog data over long lines in noisy
environments (2-wire serial data transmission).

range per "C. As shown in Figure 3, the. drift increases
'above 100kHz, and this should be taken into account for
specific applications ... To determine the total accuracy
drift over temperature, the· drift coefficients· of external
components (especially RI and CI.} must be addedto the
'drift ofthe VFC32. Above 200kHZ, it is recommended all
grades be operated below +85"C. Higher dUlY cycie (up to
50%) and higher output transistor collector current (up to
ISmA) will be required. Linea~ity will. however, be
degraded
I .
.
.
c~

:

..

100II

c

..

;ij:
:....~

a1VZOO
~

P"

"

.!leiOO I;:::::::yyp SM.KP)

!';;
.l&i,

~a 4G I-- I-TYP IBM)

II

20

III

10

0.10

Ik

2k

4k

II.. 200k 4OIl\J I.oM
IIlII
Full lelll FriQUIRCY 1Hz)

0.D4

.

FIGURE 3. Full Scale Drift vs Full Scale Frequency.
(25% Duty CYcle)
RESPONSE
.

Ii"

Ie 0.02

.::

~

~ 0.01

~

~0.004

0.002

-

Typlul TA=+25"C

111111

0.001
It

10k 20k 40k
lOOk 200II 40IIk I.OM
Full Scali Frwqlllncy IHzl

4k

2k

FIGURE I. Lmeanty Error vs Full Scale Frequency.
(25% Duty Cycle)
+1.0

IFULL SCALE =10kHZ
Typical I
TA =+25°C

+0.5

g

!

l!:

--

0

~

~

r-I

-0.5

--

·1.0
0

Ik

2tJ

3k

I
I

I

I

,,/

--4II
5k
ak 7t
OPlrlllng FrwqulIicy IHzl

",

ak . 9k 10k

FIGURE 2. Linearity Error vs Operating Frequency.
(25% Duty Cycle)
FREQUENCY STABILITY vs TEMPERATURE
The full scale 'frequency drift ,of··the VFC32 versus
temperature is expressed as parts pet. millj on (jffull scale

Response ofthe VFC32to changes in'input signal level is,
specified for a full scale step. and is I. microsecond plus I
pulse of the new frequency. For a 10 volt input signal,step
with the VFC32 operating at 100kHz full scale. the
settling time to within ±0.01% of full scale is II
microseconds.
'

THEORY OF OPERATION
The VFC32 monolithic voltage-to-frequency converter
provides a digital pulse train output whose repetition rate
is directly proportional to the analog input voltage in
Ffgure 4.
Essentially. the input amplifier acts as an integrator that
produces a 2-part ramp. The first part is a function, ofthe
input voltage. and the second part dependent '.Qnthe
current sink. When a positive input voltage is applied at
VIN. a constant' current will flow through the input
resistor. causing the voltage at fiN to ramp down toward
zero, accordingto.dV/dt = VIN/ RIC,. During this time,
'the constant current sink is disabled by the switch. Note,
this period is only dependent on VII" and integrating
components. When the ramp reaches a voltage close to
zero, the comparator will cause the one-shot to fire.'The
one-shot period is determined by an internal 7.5V
reference and C,. The f(wl' signal will then change logic
states. going from a "0" to a .. I ". and the switch will close,
enabli'ng the constant current sink. The ramp voltage will
then change direction and begin to ramp up. Since
Vis/ RI is always set up to be less than I rnA, the current in
the integrating capacitor will flow toward the summing
,junction. and ,the ramp voltage rate change will be;

of

10-6

+VPUll·UP
15V TO 15V TYPICAlly!
INTEGRATING CAPACITOR
INPUT RESISTOR
RI
VIN o-.""".......-+---1~;

VOUT
PUU·UP
RESISTOR A2

.r

CI
ONE·SHOT

~ CAPACITOR

FIGURE 4. Functional Bloc·k Diagram of the VFC32.
Y,N -lmA

The equations reduce to:

R,

( _
0-

Before the ramp voltage can saturate the input amplifier,
the one-shot will reset, disabling the current sink,
changing the output state back to logic "0", and restarting
the cycle. Since the integrating capacitor C2 affects both
the rising and falling. segments of the ramp voltage, its
tolerance and temperature coefficient do not affect the
output frequency. It should, however, have a leakage
current that is small compared to V'N/ R" since this
parameter will add directly to the gain error of the VFC.
C" which controls the one-shot period, should be very
precise since its tolerance and temperature coefficient
add directly to the errors in the transfer function.
To operate the VFC32 as a highly linear frequency-tovoltage converter, open the connection between VO\"T and
f'N, and connect VIN to VOlT. The input frequency should
be coupled through a capacitor to f'N, and a positive
output voltage proportional to fIN will be generated at the
VOUT connection. For details see Installation and Operating Instructions.
The total VFC period is determined by the following
equations, which is shown graphically in Figure 5.

I

~

!jlt===:L-.!:H==,-rL...!::::::'

L-____________________________________

DUTY CYCLE
The duty cycle (D) ofthe VFC is the ratio ofthe one-shot
period (t2)or pulse width, PW, to the total VFC period (tl
+ t2). It is measured at the full scale input voltage, which
gives the full scale output frequency, FFS.

o=

h

t, + t2 = PW

FFs

PW=-'L
FFS

t = t, + hand i = c dv/dt

Duty cycle is related to the maximum input current and
the ImA (nominal) current sink. By reducing the equations for t2 and fo:

and:

o = _V.:;IN;...·m=a;...x;.../(:...R...:'.:....)
-.l VOUTtl = +.l YouTh

t2=CI~
ImA

X

ImA

hN max
ImA

A 25% duty cycle or less is recommended to achieve the
best linearity. This corresponds to a maximum input

10-7

~

-J~

FIGURE 5. Integrator and VFC Output Timing.

fo=+
C2
C2
t=.lVouTtr VIN/(R,) + .lVoUTt2 V'N/(RIl-lmA

V's
7.5(R ,) C,

current of 'O.25mA. Ho\lleve1'~ fot' frequencies' ab'ove
, 200kHza higher duty cycle (up to 50%) will provide more
: stable high temperature operation at a sacrifice in
, linearity.
In generaf.1designs·with the VFC32 include: (I) Choosing
. F MAX • (2) Choosing the duty cycle ( D=.0.25 typically). (3)
Determining the ol1e-shot, PW. an4 (4) Calculating C,.
: C~. R,. R~. and R;.
'

INSTALLATION AND
OPERATING INSTRUCTI,ONS
: The VFC32 can be conriected to operafe as a V/ F,
converter that will accept either positive or negative input
voltages. oran input current. Refer to F(gl.lr~s 6 l!.nd 7.
C2

INTEGRATOR CAP.

adjustrifentpot (R31.IMtheoffset adjusthetwOtk (R4\
R5) can be omitted if input offset voltages of I m V to 4m"
can be tolerated. R2 is an output pull up resistor and its
value depends On ,the phil up voltage ,and output drive
requirements .
EXTERNAL COf,1PONENTSELECTION CRITERIA
One-shot Capacitor,CI. This capacitor determines the
duration of the output pulse, and is a function of the full
scale frequency. accordingto this equation:
CI(pF) =33 x 106 /fMA x - 30
Aboye 425kHz use 47pF
Select the closest standard yalue to the capacitance given
l>Y the equation. The"ini,tial tolerance of this capacitor is
not critical since R3 will be adjusted to remove initial gairi
errors. The temperature drift is critical. since it will add
directly to the errors in the transfer function. An N PO
ceramic type is recommended. Every effort should be
made, to, minimize tbe parasitic capacitance at this
connection to the, VFC32 and CI should ,be mounted as
close as 'possible. Figure 8 shows pulse width and FS
,frequency for various values of C I.

1000

'v+

~

'ILOAO

"BYPASS
WITH O.D1~F

i.3

PIN NUM,BERS IN SQUARES,REFER TO DIP

100

10

~

.;

£:

-

10

~

0.001
Capacllance Cl

FIGURE

(
~.'

iii

FIGURE 6. Connection Diagram for VI F Conversion.
Positive Input Voltages.

O!!.

0.01
I~.FI

8. Output Pulse Width (0 = 0.25) and Full
Scale FreqUency vs External One-shot
Capacitance.

PIN NUMBERS IN SQUARES REFER 'TO DIP

FIGURE 7. Connection Diagram for V/FConversion.
Negative Inpilt Voltages.
Differential inputs are also possible (in Figure' 7 lift
ground on R;, and drive R, and pin 14 differentially).
Note, no CMRwill be present.
The full scale freq uency and full scale input voltage
(current) are established by the selection of values for R I.
C2. and CI. Most applications will require a gain

Input Resistor RI and, R3. R I and R3 deiermine the
magnitude' of the current w.hich charges :theintegrator
capacitor. It is a function of the full scale input voltage,
according to this equation for 25% duty cycle.
R I (kO) [90% - %tolerance CI] x VIN max/0.25mA
R I is scaled down by [I-(initial CI tolerance + 0.1)] to
allow the addition of a series gain adjusting pot. R3.
R3 (kO) = VIN mait/0.25r;nA - R,
R I should'have a very low temperature coefficient since
this drift adds directly to the errors in the transfer
function. If the input signal is a current rather than a
voltage, R I and R3 should be ,replaced with a short
circuit. and the full scale input current should be 0.25mA
(250/0' duty cycle). Removal of gain error then requires
adjustment of C I.

10..8

Integrating Capacitor C2: C2 isa function of the full scale
frequency, according to this equation:
C'(ILF) = 102/fMAX below 100kHz
O.OOIILF min above 100kHz
Select the closest standard value to the capacitance given
by the equation. The initial tolerance and temperature
stability are not critical since these errors do no affect the
transfer function. Since the leakage current of the
capacitor introduces a gain error, select a capacitor with
leakage that is small compared to the full scale input
current e.g., 0.2SmA. A mylar type is recommended.

Trimming Components R3, R4, RS,
RS nulls the offset voltage of the input amplifier. [t
should have a series resistance between 10kO and lOOk!!
and a temperature coefficient less than 100ppmi"c. R4
can be a 200/< carbon composition resistor with a value of
10Mfl.
R3 nulls the gain errors of the converter and compensates
for initial tolerances of R I and C I. Its total resistance
should be at least 20% of R I, if R [ is selected 10%'low (see
R I equation). Its temperature coefficient should be no
greater than five times that of R I, to maintain a low drift
of the R3 - R I series combination.

Output Pull Up Resistor R2. The open collector output
can sink up to 8mA and still be TTL-compatible. Select
R2 according to this equation:
R2 min (0) = VPl:I.I.l'p/(8mA - h.OAIl)
A 10% carbon composition resistor is suitable fq~ use as
R2.
.

OFFSET AND GAIN ADJUSTMENT PROCEDURES
To null errors to zero, follow this procedure:
I. Apply an input voltage that should produce an output
frequency 0[,0.001 X full scale.
2. Adjust R5 for proper output.
3, Apply the full scale input voltage.
4, Adjust R3 for proper output.
S. Repeat steps I through 4.
[f nulling is unnecessary forthe application, delete R. and
R;, and replace R3 with, a short circuit.

Operation above 200kHz up to SOOkHz requires higher
duty cycles up to 50% (hN = O.SmA)and a,pull-up resistor
that permits 15mA to flow in the output transistor. At
ihis speed, capacitive loading should be minimized ,to
100pF or less to allow the output voltage time to rise to
logic one. Due to the large collector current, the logic
zero may rise above+O.4V. This may require an interface
circuit such as diode clamp or voltage comparator for
coupling to TTL inputs, Note, that linearity will degrade.
Also, it is recommended to stay below +85"C at high
frequencies.
'
FREQUENCY· TO-VOLTAGE CONVERSION
To operate the VFC32 as a frequency-to-voltage converter, connect the unit as shown in Figure 9, To interface
with TTL-logic, the input should be coupled through a
capacitor, and the input to pin 10 biased near+2.5V,,The
cOl)verter will detect the falling edges of the input pulse
train as the voltage at pin 10 crosses -O.6V. Choose C3 for
appropriate value of t (see Figure 9). For input signals
with amplitudes less than 5V, pin 10 should be biased
closer to zero, to insure that the input signal at pi'n 10
crosses the -0.6V threshold. Errors are nulled following
the procedure given on this page, using 0.00 I X ful·1 scale
frequency to null offset, and full scale frequency to null
the gain error. Use equations from V/ F calculations"to
find RI, R3, R., R" CI and' C2.
POWERSUPPLY CONSIDERATIONS
The power su'pply rejection ratio of the VFC32 isO.O 150(
.of FSR I 'i; max. To maintain±0.015'1r conversion,
power supplies which' are stable to within ±I'i; are
recommended. These supplies should be bypassed as
close as possible to the converter with 0.0 III F c, J,j' : ~

I

CONDITIONS

CHARACTERISnCS

.....

, .. ,.:",..,
VF~,·.,J.
.'~

'VF~~/BM/SM

'.

MIN

TVP

MAX

I

MIN

I

1">'TYP, .. r

VlF CONVERTER lOUT - VIN/7.S R,C', , Figure 4
>0
<0
+0.25

Fig. 4 wilh 82 = 0
Fig. 4 with e, = 0
liN =V,N/R,N

Voltage Range(')
Current Rangel')

-

I

".
UI\II!iS

.

.

!NPUT TO OP AMP

"MAX,

NOle2
-10
+750

V
V

,.A

Bias Cl:Jrrent
Inverting Input

4
.. ·10,

,

Noninverting Input

..

Ollset Voltagel3)
Offset Voltage Drill

:

300115

Differential Impedance
Common-mode
Impedance

' ..

300113

±5
650 II 5

,

'.

Ollset Error
OllsetDrilll7)

Qain Error(3)

.

mV

., ~

I'V/oC

,.

,

500 113

±O.Q0'4:

±O.OOIS·

±O.005
±O.O3

±O.OOS
±O.I

±O.002

±IS

..

.

.~

kO

II

kO

II pF

pF

,

Fig. 4 with 82 + = '0(6)
" 0:01 Hz ,;; lour :;; 10kHz
0.1 Hz S; foUT S; 100kHz
1Hz,;; four';; IMHz
Input Offset VOllagel3)

Gain Orilll7)
Full Scale Drill
"Iollset drift&
gain dilfll7J1BII9)
Power Supply' Sensitivity

QA

±O.I~

ACCURACY
Linearity Errort'"415)

nA

8
30

±O.S
±5

±,IO

'

50
50

1= 10kHz
1= tOkHz

'

..
20
1,,20

,

%of FSR/%

±O.015·

±Vee = 14VOC to 18VDC

%ofFSR'"
%ofFSR
%ofFSR
ppm olFSR
ppm 01 FSR/oC
'!frof,FS!!
ppmolFSRrC
ppm of FSR/oC

DYNAMiC RESPONSE
Full Scale Frequency
Dynamic Range"
Settling Time
Overload

Flecovery

6
IViF" to specifiea linearity
for a full scale input step
< 50% overload

ACTIVE PULL-UP OUTPUT
Voltage, Logic "0"
ISINK = 8mA, max
Voltage. 'L:o~ii: "I" : .
For Best Linearity
Duty Cycle at FS
Fall Time
lOUT = SmA. ClOAO = SOOpF

i:ri! CONVERTER VOUT = 7.5 A,C,

MHz
deCaaes

I

ClOAO,;;50pF

Note 10
Note 10

'

..

..

0.4
Vpu

Vpu - 2.6

V
V
%
nsec

25
100

F,N. Figure 9

INPUT TO COMPARATOR
501110
+1.0
-Vee
0.25

Impedance
Logic "I",
Logic "0"
Pulse-width Range

"

ISO 1110

kO

II pF
V
V

+Vee
-0:05

#lsec

OUTPUT FROMOP AMP
Voltage
Current
Impedance

Capacitive Load

V
rnA

010 +10
+10

10 = 7inA
. Vo =7VDC
, Closed-loop

Without oscillatio~

n

0.1
100

pF

±20
+Vee
±S.7

V
V
V
rnA

POWER SUPPLY
±15

Rated Voltage
Voltage Range. Vee
Pull-up Voltage
Quiescent Current

±13
+3.5 "
not including load current

±S

.

TEMPERATURE RANGE'
Specification
B and C Grades
S Grade
Operating
B and C Grades
S Grade
Storage

:25
,

"

'

tl

"

+85

:.

,25.to+85'
-55 tO +1:25
'65
+150

I

-65

'Speciflcatlon the same as'for VFC62BG/BMISM.

10... 18

°c
°C

-55 'r125

°c

,.'

;'"150

°C
°C

;",

NOTES:
1. A 25% duty cycle at full scale (O.25mA input current) is recommended where possible to achieve best linearity.
2. Oetermined by RIN and full s.cale current range constraints.
'

3. Adjustable

io zero. See Offset and Gain Adjustment section.

4. Linearity error at any operating frequency is defined as the deviation from a straight line drawn between the full scale frequency and
0.1% of full scale frequency. See Discussion of Specifications section.
5. When offset and gain errors are nulled, at an operating temperature. the linearity error determines the final accuracy.

= 0 typical linearity errors are 0.01% at 10kHz, 0.2% at 100kHz.
7. Exclusive of external components drift.
8. FSR = Full Scale Range (corresponds to full scale frequency and full scale input voltage).
9. Positive' drift is defined to be increasing frequency with increasing temperature.
10. One pulse of new frequency plus 50nsec typical.
6. For e,

ABSOLUTE MAXIMUM RATINGS
Supply Voltages
Output Sink Current at fOUT
Outp~t Current .t VOUT
Input Voltage, -Input
lriput Voltage, +Input

±20V
50mA
+20mA

Storage Temperature Range
Lead Temperature (soldering. 10 seconds I

±Vcc
±Vcc
-65°C to +15O"C
+3000C

VFC62BG/CG
CERAMIC DUAL-IN-liNE

-

VFC62BM, CM/SM
TO-100 PACKAGE

~!!~~

CJ·

6 --1
l--li
~
I

in true position Within
0.10"1025mm1RatMMCat

. '-Pin.'

Seating
Plane
INCHES
MIN
MAX
.335

.370

8.51

.335

7.75

9.40
8.51

.165

'.185

4.19

4.70

.016

.021

0.41

0.53

.010

.040

0.25

q)2

.010

.040

0.25

1.02

.230 BASIC

5.8"48ASIC

.028

.034

0.71

.029

.045

.120

··A'.~P - l'

1

:i

-.II--~

!

I

/116

R

J~

36° BASIC

36° BASIC

N

.110

2.79

D
F

•
H

K

L
M

4.06

M

•

c

J

1.14

3.05

·
N

3.05

.

___ D

DIM

0.86

0.74

.120

it'·:
!.G~

12.10
.160

U

MILLIMETERS
MIN
MAX,

.305

.500

..... , ....

T=~'-~_N
'. - ' .. -f---T

~--,:
seating plane
Pin numbers shown for reference only
E
F .J
Numbers may not be marked on package

OIM

.

NOTES: ,. Leads in true position within 0.01"
,0.25rnml R.t ...ting plane.'

MECHANICAL

....,.,.

..,
'.. . ,
.... ....".
• ,N

".

.01&

-,...
.... .....
..N
1t.1'

..,. ....'.32,...
..." ....- 3._.

.. .

. "4

'OO8ASIC

-

"0

't.41

3."

U41ASIC
2.1'
0.30

UBA8IC
1.5-

7.a8ASIC

,..

,...
....,,. .... ....
,'" s." ....
0-

0"

PIN CONFIGURATIONS
ITOPVIEWI'

MPACKAGE
ITO-l001

GPACKAGE
IDUAL-IN -LINEI
-IN

ITOPVIEWI

NC
NC
-Vee ICASEI

3

8 COMMON

-Vee
ONE-SHOT
CAPACITOR

ONE-SHOT
CAPACITOR
VPU
fOUT
NC = NO ',NTERNAL CONNECTION.
EXTERNAL CONNECTION "'ERMITTED.

10-19

COMPARATOR
INPUT'

Vpu

NC

fOUT

t=~~~~NC

DISCUSSION OF
SPECIFICATIONS'

(especially RI and CI) must be added to the drift of the
VFC62.
. . . .
1000

LINEARITY
Linearity is the maximUln deviation of the actual transfer
function from a straight line drawn .between the end
points ( 100% full scale input or frequencY and 0.1 % of full
scale called zero). Linearity is the most demanding
measure of voltage-to-frequency converter performance,
and is a function of the full scale frequency. Refer to
Figure I to determine typical linearity error for your
application. Once the full scale frequency is chosen, the
linearity is a function of operating frequency as it varies
between zero and full scale. Examples for 10kHz full
scale are shown in Figure 2. Best linearity is achiev~d at
lower gains (..lfoL'T/ 8 VIN) with operation as close to the
.chosen full scale frequency as possible.
The high linearity of the VFC62 makes the device an
excellent choice for use as the front end of A/ D
converters with 12- to 14-bit resolution, and for highly
accurate transfer of an!llog data over long lines in noisy
environments (2-wire'digital"transmission).

"~

8 AND 8 GRADES
C"S..10E

IIIk

FIGURE 3. Full Scale Drift vs Full Scale Frequency.
RESPONSE
Response of the VFC62 to changes in input signal level is
specified for a full scale step, and is SOnsec plus I pulse of
the new frequency. For a IOV input signal step with the
VFC62 operating at 100kHz full scale, the settling time to
within ±O.O I% offull scale is IOJtsec.

ftlft

0JI4

THEORY OF OPERATION
The VFC62 monolithic voltage-to-frequency converter
provides a digital pulsetrain output whose repetition rate
is directly proportional to the analog input voltage: The
circuit shown in Figure 4 is. composed of an input
amplifier. two comparators and a flip-flop (forming a
one-shot), two switched current sinks, and an active pullup output transistor stage. Essentially the input amplifier
acts as.an integrator that produces a two~part ramp. The
first part is afunction ofthe input voltage, anti the second
part is dependent en the input voltage and current sink.
When a positive input voltage is applied at VIN, a current
will flow through the input resistor, causing the voltage at
Your to ramp down toward zero, according to dV /dt =
VIN/ RIC,. During this time the constant current sink is
disabled by the switch. Note, this period is only dependent
on VIN and the integrating components.

;J
0.01

I

0JI04

-'A =

.OFsttf

O.lll2
ft,..·

Ik

2k

IIIk 2!IIt 4IJk

It

2D _

lOOk

iM

Full SclI, Fnqu.., (Hz1

FIGURE \. Linearity Error vs Full Scale Frequency.

..

~.0D3

!

+9.001

if
it

€
":II

V

...
.
-o~ ...
-" -./

. ,;.?

.........

CGRAM

"

~

:!!i

-0.001

....

.0.002

",1:
-=

.. -- -_. -- - "

• GRA-'~.G02

.......

r--.....

-0.003

0

n

2k

- -..

........ r-..

.~

.-1
--- .- .--/
,,/

5k 8k 7k
:lit 4k
0pInI1ng FI'lllIIItICY (Hzl

8k

11IIIIc2OOk _1M

fullS.lt fl1QutnC,IHZJ

Ok IIIk

FIGURE 2. LIIleanty Error Vs Oper!ltIllg Frequency.
FREQUEMCY STABILITY \Is TEMPERATURE
The fuil scalefr.equency drift of the VFC62 versus
temperature is expressed as parts per million of full scale
range per 0c. As shown in Figure 3, the drift increases
above 10kHi. To determine the total accuracy drift over
temperatu~e, t~e drift coefficients of external components

When the ramp reaches' a voltage close to zero,
comparator A sets the flip-fldp. This closes the current
sink switches as well as changingfoUT from logic 0 to logic
. \. The ramp now begins to ramp up, and ImA charges
through C, until Vq = ~7.SV. Note this ramp period is
dependent on the ImA current. sink, connected to the
negative input of the op amp,. as "well as the input voltage.
At this -7 .SV threshold comparator Bresets the flip-flop,
and the ramp voltage bellins to ramp down again before
the input ampl\fier has a cilanceto saturate. In effect the
comparators and flip-flop form a one-shot whose period
is determined by the internal reference and a I rnA current
sink plus the. external ~apacitor, ,CI. After the. one-shot
resets, fOUT changes back to. logic 0 and the cycle begins
again.'

10-20

The transfer functiqll for the YFC62 is derived as follows

INPUT IlEIIITOR

R,

fOUT~
V,N,

V,N
'OUT' 7.5R,C,
FOR POSITIVE INPUT VOLTAGES '--------i::----...;...+.----------:1r~
USE 8" SHORT Iz'
COMMON
FOR NEGATIVE INPUT VOlTAGES
USE 12- SHORT I"
C'I·E-IHOT
FOR DIFFERENTIAL INPUT VOLTAGES
~ CAPACITOR
PIN NUMBERS SHOWN FOR ;'M" PACKAGE (TO·lOO)
USE IIId Iz'

I,

FIGURE 4. Functional Block Diagram

ohh~

VFC62.
,

for the circuit shown in Figure 4. Detailed waveforms are
shown in Figure 5,
fouT = t, ~ t,
(I)
In the time t, + t" the integrator capacitorC, charges and
disc~arges but the net voltage change is zero.
Thus aQ = 0 = hN t,

+ (hN - IA) 12

(2)

So that I'N (t, + t,) = IA t,
.
V'N
But Since
t, + 12 = -,I- an d IIN =-R
lOUT

fOUT=

(3)
(4), (5)

'

Since the integrating capacitor, <\ affects both the rising
and falling segments of the,' ramp voltage, its tolerance
and temperature coefficient do not affect the output
frequency. It should, however, have a leakage current
that is small compared to I'N. s,ince this parameter will
add directly to the gain error of the VFC. C" which
controls the one-shot period, should be very precise since
its tolerance and temperature coefficient add directly to
the errors in the transfer function.

1

~

(6)

IAR'h

OV

·7.5V

The operation of the VFC62 as a highly linear frequencyto-voltage converter, follows the same theory of operation as the voltage-to-frequency converter. e,' and e, are
shorted and F'N is disconnected from V(Wl. F'N is then
driven with a signal which is sufficient to trigger
comparator A. The one-shot period will then be ~
determined by C,' as before, !lut the cycle repetition ""
~
frequency will be dictated by the digital input at F'N.
:>

DUTY CYCLE
The duty cycle (D) of the VFC is the ratio of the one-shot
period (12) or pulse width, PW, to the total VFC period (t,
+ t,). For the VFC62, t, is fixed and t, + t, varies as the
input voltage. Thus the duty cycle is a function of the
input voltage.' Of particular interest is the duty cycle at
full scale frequency. DFS, which occurs at full scale input.
DFs is a user-determined parameter which affects ,lin«;larity.

-rL
I

I

DF~ = t,

FIGURE 5. Integrator and VFC Output Timing.
In the time t" 18 charges the one-shot capacitor C, until
its voltage reaches -7.5V and trips comparator B.
C,7.5
Thus 12 = - (7)
.
. 18 .
VIN
18
U~mg (7) 10 (6) Yields fO~T=7.5 R,C XI;
(8)
Smce IA ,= 18 the result IS
VIN •
fOUT = 7.5 R,C,
(9)

10-21

1,

+ 1,

= PW

X

fFs

Best linearity is achieved when DFs is 25%. By reducing
equations (7) and (9) it can be shown that
D

_ V'N max / R,
FS-

ImA

hN max

IiiiA

Thus D FS = 0.25 corresponds to I'N max = 0.25mA.

. '1'; j~ifs ~lookHz,

~dPFt=

(13)

.

.. ;OI; if;16~k.lf.i.O005 fps;>sMkH[

'rtinthing C6~~efils
s
Rs nullSthe of($~fvoltage tfftHeinptit Ilmplifler. I.t should
have a series ie&!l!fllhOe lJ~tweefiIO~O and loom and a
teibj:reYaturec Package). Current
flowing into the fOUTpin (logic sink current) will also
contribute to ihi~ cutrent. It is advisable to separate this
common lead ground from the analog ground associated
with the integrator input to avoid errOrs produced by
these currents flowing through any grotirid return impedance.
.

PIN NUMBERS IN SOUARES REFER TO OIP PACKAGE

2.2kn

DESIGN EXAMPLI

Given a full scalt! i~put of +JOY; select the values of R I,
R 2, R3, C 1, a'n~ C2for a 25%:duty cycle at 100kHz
maximum operation irlt.o one ttl-load .. See. Figure 6.
Sellicting ~ (D".I<= 0.'25)
C; =[(33 x I06)/fMAx] -l~
[(66 x 106)/fMAx] -15
if D~s = 0.5
= [(33 X 106)1 lO:OkHz~ -15
=315pF
.,.,
ChoOse a 300pF NipOce'l"l1niic capacitor with I % to 10%
tolerance.
'
SelectingR, ami /(, (DFs 4,0.25)
Rl + R3 =VIN fl'illX/0.25 ttl A·

= IOV Ill.251M
== 4OkO

VIN max/O.5mA
ifD Fs = 0.5

FFS =100kHz

'FIGURE 9. Connection Diagram for F/V Conversion.

TYPICAL APPLICATIONS
Excellent linearity, wide dynamic range, and compatible
TTL, DTL. ~nd CMOS digital output make the VFC62
ideal for a variety of VFC applications. High accuracy
allows the VFC6'2 to be used where absolute or exact
readings must be made. It is also suitable for systems
requiring high resolution up to 14 bits.
Figures 10 - 14 show typical applications of the VFC62.

wput Resistors Rl .and R~_
;,
The inPJlt resis~ance (RI II,nd R3 inFiguf":s ~;i\ni'7) is
ca~lOulll(ed to set the desired i!lpllt c\li:~9Jiiffpl1~~)e
input voltage. This isnQrlnally p;~~m~.t,9J!roy.l!.le a)5,%
duty Cycle at full sc~le iQ!l\l;t andoutP!,!t.Va,I~":~ oWer
than QFS =0.25 may be IISM jQtlineari\ywi!1 bellff~e4.'
Tbe.!lQminal vallle.Qf.Rd" ., .
..
,
R 1 == VIN IlUI·J
( 1,4)
.'. 0.25mA.
. ..
If gain t~'mmiQ.8.i§to l>e gplle,
no.mjmil :Yflueis
..i'·.~·
redl!ccdby thetQ.ler!\Rce.of~II\!i9t:1w4'ls. ired.'." tr!I11.T~
RI shQuld have a yery-I()~tempcratui'e.l(~fficlent ~rP<;e
its driftadds directly to the errors iltthetransfer fv~ct10n..

INSTALLATION AND
OPERATING INSTRUCTIONS
VOLTAGE-TO-FREQUENCY CONVERSION
The VFC62 can be connected, to operate as a VIF
converter that will accept either positive or negative input
voltages, or an input current. Refer to Figures 6 and 7.

*

C2' INTEGRATOR CAP,

GAIN ADJ,

~,

..

One-Shot Capacitor, C 1
'.
This ~pacItor·det~~miQei.tbe dIlTltif the~.AA-s.hot
pulse. From equation (9) ihe nominaly~lue is . " ,"
""YiN

....

.'

C1 .om "f,r'S'R, fO\J'f
, ( I J.)
For the usul,\!)5% dutY.lI,t fMAlI == VII)/ R1 Q.25mA. tbllre
is approximately 15p Fof re.ic\uai ~Pll(;:iti\lJi'Qe '~b t.~~~ the::
design value is
,"
~',
';'
3Jx 19'·
C.(pF) =~ - 1$
"
(I~)
where fps is the full scale output frequency, in ,H,~. The
temperature drift of CI is critical since it wjll add dirt:!=t1y
to the errors of the transfer fun(;:tiQn. An NPO"ceramic
type is recommended. Every effort s~\!ld be inat,le to
minimize stray capacitance associatedwiih C 1• ~ sh~1d
be mounted as close to theYFC62as po~sible,Figu"e, 8
shows pulse wic;lth and full S\!lI.le freq\le~cy for v'!-riQ\ls
. value~:ofCI at DFs = 25%.
. .
,,'

=

·BYPASS WITH O.oI~F

PIN NUMBERS IN SQUARES REFER TO DIP ~ACKA&E

FIGURE 6. Connection Diagram for VI F Conver~ion, ,
Positive Input Voltages.
GAIN ADJ .

C2

INTEGRATOR CAP.

• BYPASS WITH 0.01 F
~ PIN NUMBERS IN SQUARES REFER TO DIP PACKAGE

FIGURE 7. Connection Diagram for VI F Conversion,
I
Negative Input Voltages.

EXTERNAL COMPONENT SELECTION
I n general the design sequence consists of: (I) choosing
fMAX , (2) choosing the duty cycle at full scale (DFS = 0.25
typically), (3) determining the input resistor, RI (Figure
4), (4) calculating the one-shot capacitor, .Ct, and (5)
selecting the integrator capacitor C,.

FIGURE 8. Output Pulse
" =0.25) and Full
Scale Frequency vs External One~sbot
Capacitance.
Integrating Capacitor, C,
Since C, does not occur in the VI F transfer functi(l!l
equation (9), its tolerance and temperaturestl\bilityare
not important; however. leakage current in C, cllyses II
gain error. A ceramic type 'is 'sufficieQt for' most
applications. The value of C, determines,the amp!itllde of
VO\JT. Input amplifier saluration. noise ievels for t\'le
comparators and &lew rate limiting Q( the integr.xor

10-23

.~~..

"",

PARALLEL
'DATA

FIGURE .10. Inexpensive A/D"with Two-Wire Digital Transmission Over Twisted Pair.

BCD

DIFFERENTIAL -.:--'--t
INPUT

cauNTER
DRIVER/DISPLAY

FIGURE 11.Inex~SiVe'Bigital Panel Meter.,

PRECISION
DC LEVELS
DOWN TO llilirV
FULlBCAlE

FIGURE 12.

0.005'10 LINEARITY

Remot~T~ansducer

Readout via Fiber Optic Link (analog and digital output).

+IOVTO -IOV
INPUT
l---I--"~

20kn
SlGN 8ITo---,.,
OUT
Ukll

+VCC

-15V

HGURE 13. Bipolar input is accomplished by.offsetting
the input to the VF(: with a reference
voltage.' Accurately matched resistors in
the REFlOl provide a stable half-scale
'oiltputftcquency at zero vOltsinp~t. ,

r.'

...

, FIGURE 14. Absoiutevalue circuit with the VFC62. Op
, amp, Dl and Ql (its base-emitter junction
functioning as a diode) provide full-wave
rectification of bipolar input voltages. VFC
output frequency' is proportional to led.
The sign bit output provides indication of
the input polarity.

\ '~

;,:.

1""

VF~BG/BM/SM
MAX

; Tv,.;

MIN

I:,~xl

.,... ,,-

,

~N!r,

VlF.CONVeRTER FOUT - VINn.5 R,C" Figure 4
INPUT· TO OP AMP
Fig. 4 with 82 = 0
Fig.4 with e, = 0
liN' .; \TINiRIN

Voltage Range(1)

Curre~t Rangel')

Note 2
-10
'+750

>0
<0

+o.2!>.

Bias Current
4
10

Inverting Input
. Noninverting Input

V
V
I'A

"

e·

Common-mode

,

±5
659115 .

300115

nA
nA
mV
I'VloC
killl pF

~O

±a.IS

Offset Voltage(3)
Offset VoltaQe Drift
Differential Impedance

300113 '"5001l~"

impecianos

ACCURACY

.Fig.4 with 82 = I)(si
0.01 Hz S loUT S 10kHz
0: I Hz S fOUT S 100kHz
1Hz S lOUT S lMHz

Linearity Error(1)(4)(5)

kn II pF

±a.OO4

±a.005

±0.OO8
+0.1

±a.03O

±0.OOI5

Offset Error Input

,

±15

Ol~tV(»tageI3)

±0.5
±5

OffsetDrii«7) .
Gain Errort3),
Gain Driftl7)
Full Scale Drift
,offset drift &
gain drift),7),8)(9)
Power Supply Sensitivity

f= 10kHz
f = 10kHz

±10
50
50

±Vee = 14VO.C; to 18VDC

±a.015

%01 FSR
%olFSR
% 01 FSR

±O.OO2

ppm of FSR
ppm of FSR/oC
%ofFSR
ppm of FSR/' C
ppm 01 FSRlOC

20
20

% of FSR/%

,"

DYNAMIC RESPONSE
MHz
decades

I

CLOAOS50pF

Full Scale Frequency
Dynamic Range
Settling Time

6
!V/F) to spepified linearity .
Note 10
Note 10

for a full sc'ale input step

Overload Recovery

<:

50% overload

OPEN COLLECTOR OUTPUT
Voltage, Logic "0"
Leakage;Current, '
Logic "1"
Voltage, Logic "I"

ISINK

= SmA, max
0.01

Vo = 15V

0.4

V

1,0

p.,A

External pull-up resistor

YPu

required I see Figure 4)
For Best Linearity
lou.r,= SmA, CLOAO = 500pF

, 'Duty Cycle at .FS
Fa" Time

FlY CONVERT.ER VOUT - 7.5 R,C, F,N, ,Figure 9

V
%

25
100

nsec

"

INPUT TO COMPARATOR
I!"pedance.
Logic "1"
Logic'''O''

501110
+1.0
-Vee
Q.?5

<-

,.

Pulse·width ~ange

,

kn II pF
V
V
I'sec

150 1110
+Vee
-0,05

.

OUTPUT FROM OP AMP
Voltage
Current

Impedance
Gapacitive Load

lo=7mA
Vo=7VDC

V
mA
n
pF

Oto+l0
+10

Clos8d~looP

0.1
"1~

Without oscillation

POWER SUPPLY
Raied Voltage
Voltage Range .'
Quiescent Current

V
V
mA

±15
±13'

±20

±S

,.

·±S.7,

TEMPERATURE RANGE
Specification
B 8hd C Grades
S Grade
Opel'llting
Band C Grades
S Grade
Storage

...

,

"

~25

+85
+125

°c
°C

-55

+85
+125

:-55.

-1:150

°C
°C
°C

-55
~25

'Specification the same as for VFC320BG!BMlSM.

10.:.26

..

NOTES:
1. A 25% duty cycle at full scale (0.25mA input current) is recommended where possible to achieve best linearity.
2. Determined by RIN anq full scale current range 'Constraints.
3. Adjustable to zero. See Offset and Gain Adjustment section.
4. Linearity error at any operating frequency tSdefined as the deviation from a straight line drawn between the full scale frequency and 0.1%
of full scala frequency.,See Discussion of Specifications section.
5. When offset and ga'in errors are nulled, at an operating temperature, the linearity error determines ~he final accuracy.
6. Fore, = 0 typical linearity errors are: 0.01% at 10kHz, 0.2% at lOQkHz, 0.1% at lMHz.
7: Exclusive of external components' drift.
'
8, FSR = Full Scale Range I corresponds to fuli scale and full scale input voltage.
9. Positive drift is defined to be increasing frequency with increasing temperature.
10. One pulse of new frequency plus SOnsectypical.

ABSOLUTE MAXIMUM RATINGS
±20V

Supply Voltages
Output Sink Current at fOUT
Output Current at VOUT
Input Voltage, -Input
Input Voltage, +Input
Storage Temperature Range
Lead Temperature Isoldering, 10 seconds I

SOmA
+20mA

±Vcc
±Vcc
-65°C to +150°C

+300o C

-

VFC320BM/CM/SM
TO-100 PACKAGE

NOTE
Leads," true POSition Within

~~~;~~'~~a~:'
"'m

E

MIN

MAX

.335

370

MILLIMETERS
MIN
MAX
8.51

9.40

.305

.335

".75

8.51

C

.165

:185

4.19

4.70

o

.016

.021

0.41

0.53

'- PI~""

:-; F-

F
K

Seating
Plane
INCHES

"1

~l

Rat MMC at

~:::: :].

fS--Jr

1

numbers shown for reference only
Numbers may not be marked on package

DIM

.

NOTES: 1. Leads in true position within 0.0'"
I O.25mm I R at seating plane.

MECHANICAL

--u.-c ;--

j

I'

,.
,+
l

~

~o~

If'

INCHES

MOO

V~'(ct-....!~

I-'E:.....-f..::.O
"""O_I-'.04:;:O:o......+'O:::..2"'5:.....-t-"c:.O
:'!2-l ' - H

MIN

MAX

MIN

A

,..

767

19.13

.H'

'.22
3."

G

,..

.015

F

""

.DOII

""
".

.012

.1)10

.040

0.25

1.02

H

.028

.034

0.71

0.86

J

.029

.045

0.74,

1.14

K

K

G

.120

.160

3.05

L

M

36° BASIC

36° BASIC

N

.110

2.79

.1.120

M

4.06

N

R

3.05

.," ..,.

....

.53

•.,.
-

3."
7.R8Mle

.

O.3BA IC

.,,.

•.,.
.,.
2.16

'.20

.... ...
'

MAX
1'...,

1.14'
'.52
2.548ASIC

.1008A8IC

H

12.70

.500

..,

D

F

~~G~=~j.2~3~O~.;AS~I~C:~=~=5~.8~.~8~A~S~,C~:=~

753

C

B

~

MILLIMETERS

DIM

".

'.23
3.18

'"

...
'0·

t.52

PIN CONFIGURATIONS·
MPACKAGE
(TO-1OQ)

.GPACKAGE
( DUA~-IN-~INE)
-IN

ITOPVIEW)

NC

{TOP VIEW)
+IN
VOUT
+Vee

-Vee ICASE)

ONE-SHOT
CAPACITOR

3

8

-Vee

COMMON

ONE-SHOT
CAPACITOR

COMPARATOR
INPUT

NC 5
fOUT
NC = NO INTERNA~ CONNECTION.
EXTERNA~ CONNECTION PERMITTED.

10-27

COMMON
COMPARATOR INPUT

NC

NC

fOUT.

NC

temperature, the drift coefficients of external compollents
(especially R, and C,l must be added lot he driffofihe
VFC320.
'

DISCQS810N, OF
SPECIFICATIONS
LINEARITY
Linearity is the maximum deviation of the actual transfer
function from a straight line drawn between the end
points( 100% full scale inpui or frequency andO.I%offull
scale called zero). Linearity is the inost demanding
measure of voltage-to-frequency converter performance, '
and is a function of the full scale frequency. Refer to
Figure I to determine typical linearity error for your
application. Once the full scale frequency is chosen, the
linearity is a function of operating frequency as it varies
between zero and full scale. Examples, for 10kHz full
scale are shown in Figure 2. Best linearity is achieved at
lower gains (.l.fot:T/.l. V,,,) with operation as close to the
chosen full scale frequency as possible.
The high linearity of the VFC320 makes the device an
excellent choice for use as the front end' of AID
converters 'with 12- to 14-bit resolution, and for highly
accurate transfer of analog data over long lines in noisy
environments (2-wire digital transmission).
0.10

I

I~

.T~ 't2f~

,0.1102

0.001
It

OfS iOf;

10k 2110k 4IIOk

IIIe 20k 40k

2t ,4k

Full Seale Frequency 1Hz)

FIGURE I. Linearity Error vs Full Scale Frequency.

,

1

Typlcal. TA=+25"1: -

"' :J.::::r

+0.003 'FULL SCALE =10kHz

'

/v' BI:R~L. ..

...........

- -- "\-..
r"::.::. '-.
. -.. _.. -- .... -1
......
r--......
/
~ ..- -"-

~

-~CGRAD£

~~.

'"

'

..........

o

lk

2Ic

at

:..,.....-

I'..

4k

SIc

8k

7k

8k

E' '

400

o!s

'i¥
........ ZOO·

~

ie 1110
DO . .

~I

40 -BANIIS8RADES

!

20 -caRADE

1!-

10

Ik

2k

FIGURE 3. Full

III

,

1111
4k'
10k

lOOk ZOOk 400k 1M
Full Saall Frequencv 1Hz) ,

~cale

Drift vs Full Scale Frequency.

RESPONSE,'
Response of the VFC320 to changes in input signal level
is specified for a full sca~e step, and is SOnsec plus I pulse
ofthe new frequency. For a 10V input signal step with the
VFC320 operating at 100kHz full scale, the settling time
to within ±o.O I% of full scale is 1Oil sec.

THEORY OF OPERATION

Ii

!~

1Il00

ak

10k

Op.rlling Frllluency 1Hz)

FIGURE 2. Linearity Error vs Operating Frequency.
FREQUENCY STABILITY VS TEMPERATURE
, The full scale frequency ,drift of the VFC320· versus
;' temperature is expressed as parts per million of full scale
range per 0c. As shown in Figure 3, the: drift increases
a~ove' 10kHz. To determine the totalaccuraey drift over

The VFC320 monolithic voltage-to-frequency converter
provides ildigital pulse train outputwhose repetition rate
is directly propc;>rtional to the analog,input voltage. The
circuit shown in Figure 4 is composed of an input
amplifier, two comparators and a flip-flop (forming a
one-shot), two switched current sinks, and an open
collector outPl,lt transistor stage. Essentially the input
amplifier acts as an integrator that produces a two-illut
ramp. The first part is a function of the input voltage, and
the second part is dependent on the input voltage and
current sink. When a positive inpqt voltage is applied at
VIN, a current will flow through the input resistor,
causing the voltage at VOUT to ramp down toward zero, ,.
according to dV/dt = V,N/R,C,. During this time the
constant current sink is disabled by the switch. Note, this
period is only dependent on VIN and the integrating
components. '
When the ramp reaches a voltage close to zero,
comparator A sets the flip-flop. This closes the current
sink switches as well as changing fOUT(rom 10gic.0 to logic
I. The ramp now begins to ramp up. and ImA charges
through C, until Vel = ,-7.SV. Note this ramp period is
dependent on the ImA current sink, connected to the
negative input of the op amp; as well as the input voltage.
At this -7.SV threshold point at C,. comparator B resets
the flip-flop, and the ramp voltage begins to ramp down
again before the input amplifier has a chance to saturate.
In effect the' comparators and flip-flop form a one-shot
whose period'is determined by the internal reference and
a I rnA cllrren~ sink plus the external capacitor,C,. After '
the one-shot resets, fouT changes back to logic 0 and the
cycle begins again.- "
.',
The transfe~
ftinction f~r the, VFC320 is derived for the
',.,.

10-28

+VpULL.UP IVpul
15V TO 15V TYPICALLVI

INTEGRATINS CAPACITOR

INPUT RESISTOR

II

•

VOUT

R,

I
PULL·UP ~ R
R!SISTOR 2

-

1

"N

'OUT~
V,N
lOUT = 7.5 RICI
DNE-8HOT

VIN'
FOR POSITIVE INPUT VOLTAGES
USE II' SHORT 12'
~-----t-:-----t-4---------'--t-_..J
FOR NEGATIVE INPUT VOLTAGES
B
COMMON
USE 12' SHORT II'
.VCC
CI
IINE.SHOT
FOR DIFFERENTIAL INPUT VOLTAGES
":" CAPACITOR
PIN NUMBERS SHOWN. FOR "M" PACKAGE ITO·IOOI
USE I, Ind 12.

I.

FIGURE 4. Functional Block Diagram of the VFC320.
the circuit shown in Figure 4. Detailed waveforms are
shown in Figure 5.
I

foul' = t I + t,
(I)
In the time t:. + t I the integrator capacitor C~ charges
and discharges but the net voltage change is zero.
(2)
Thus ~Q = 0 = I,~ t I + (liN - IA) t,
So that lIN (t, + t,) = IA t,
and liN
. But since t I + t, =

(3)

"..L

(4), (5)

Since the integrating capacitor, C" affects both the rising
and falling segments of the ramp voltage, its tolerance
and temperature coefficient do not affect the output
frequency. It should, however, have a leakage current
that is small compared to liN. since .this parameter will
add directly to the. gain error of the VFC. CI, which
controls the one-shot period, should be very precise since
its tolerance and temperature coefficient add directly to
the errors in the transfer function.

10LT

[OUT

=

(6)

V IN

The operation oftheVFC320 as a highly linear frequencyio-voltage converter, follows the same theory of operation as the voltage-ta-frequency converter. el and e, are
shorted and FI" is disconnected from VOl'T. FI~ is then
driven with a signal which is sufficient to trigger
comparator A. The one-shot period will then be
determined by C I as before, but the cycle repetition
frequency will be dictated by the digital input at Fis.

IARlt2

OV

·7.5V

I-n
I

I I

DUTY CYCLE
The duty cycle (D) of the V FC is the ratio of the one-shot
period (t,) or pulse width, pW, to the total YFC period (tl
+ 12). For the VFC320, t, is fixed and tl + t2 varies as the
input voltage. Thus the duty cycle, D, is a function of the
input voitage. Of particular· interest is the duty cycle at
full scale frequency, DFS, wliich occurs at full scale input.
DFS is a user determined parameter which affects linearity.

12

I.I

-rL

D FS =

FIGURE 5. Integrator and VFC Output Timing.

Using (7) in (6) yield fouT=
Since IA = 18 the result is
VIN
fOUT = 7.5 RICI

7,~;'C, x

::

(8)

= PW x f Fs

Best linearity is achieved when DFS is 25%. By reducing
equations (7) and (9) it can be shown that
D . - YIN max I RI _ lIN max
FSImA
- ~

t,.

In the time
18 charges the one-shot capacitor C , until
its voltage reaches -7.5V and trips comparator B.
C 1 7.5
Thus t 2-- --1(7)

_t,_
tl + t2

Thus DFs = 0.25 corresponds te liN max

(9)

10-29

= 0.25mA.

>-

,

, 'fNSTALLATICN AND
OPERATING INSTRUCTIONS,
VOLTAGE~TO-FREQUENCY CONVERSION

The. VFC320 .can be .connected to operate as a V/F
converter that will ac~ept either positive or negative input
voltages, or an inpu~ current. Refer to F~ures 6 and 7.

caIcuhi'ted to set the desi'red input current at full scale
input voltage. This is normally 0.25mA to provide a 2S%
duty cycle at full scale input and output. Values other
than DFS = 0.25 may b'e used but linearity will be affected.
The nominal value is Rr is
V'Nmax
(10)
R, = . 0.2StnA
If gain trimmi't1g is to be done, the nominal .value is
reduced by the toleranceofC, and the desired trim range.
Rl.should hav~a very-low temperature coefficient since
its drifi adds directly to the errors in the transfer function.
One-Shot Capacitor,C,

lOUT
"BYPASS WITH 0.01 "F PIN NUMBERS IN SQUARES REFER TO Dip PACKAGE

FI.GURE 6. Connection Diagram fo'r V /.f Conversion,
Positive Input Voltages.
.

This capacitor determines tht; duration' of the onecshot
pulse. From equation (9) the nominal·value is
C, nom =
YIN
(II)
7.S R, fOUT
For the usual2S%duty at fMAX = V'NI R, =0.2SmAthere
is approximately ISpF of residual capacitance so that the
design value is
6
C ,(pF)= 33 x 10 _ IS
(12)
f Fs
where fFs is the full scale output frequency in Hz. The
temperature drift ofC is critical since it will add directly
to the errors of the transfer function. An N PO ceramic
type is recommended. I;':very effort should be made to
minimize stray capacitance associated with Ct. It shollid
be mounted as close to the VFC320 as possible. Figure 8
shows pulse width and full scale frequency for various
values of t, at D FS = 2S%.

INTEGRATOR CAP.

~--~----~-----r----~I~

I

i~

~ 100 I---+----t--'~-.,.--__t 104

£:

I

I

..~

I

~

101---!---711-~--t-~--t

'OUT
"BYPASS WITH 0.01 "F PIN NUMBERS IN SQUARES REFER TO DIP PACKAGE

,FIG U RE 7. Conn.ection Diagram for V I F Conversion,
Negative Input Voltages.

EXTERNAL COMPONENT SELECTION
I n general the design sequence consists of: (I) choosing
fMAX, (2) choosing the duty cycle at full scale (DFS = 0.25
typically), (3) determining the input resistor, l!" (Figure
4), (4) calculating the one-shot capacitor, C" (5) selecting
the integrator capacitor Cz, and (6) selecting the ~utput
'pull-up resistor, Rz.
!Ellut Resistors R, and R,
The input resistance (R, and R, in Figures 6 and 7) is

FIGURE 8. Output Pulse Width (D FS = 0.2S) and Full
Scale Frequency vs EXlermil One-shot
Capacitance.

Integratin~llacitor. Cz
Since C2 does not occur in theV/F transfer function
equation (9). its tol.era,nce and. temperature stability are
. '!ot important; however. leakage current in C2 causes a
gain error. A. ceramic type is sufficient for most
applications. The value ofCzdetermines the amplitude of
VOUT. Input amplifier saturation. Iioise-Ievels for the
.comparators and slew rate limiting of the integrator

I

determine a range of acceptable values,
IOO/[FS; if fFs';;;; 100kHz

Cd,uF) =

~ng

(13)

0.001; if 100kHz < [FS';;;; 500kHz
0.0005; if fFs > 500kHz

<2!!!put Pull Up Resistor Rz.
The open collector output can sink up to 8mA and still be
TTL-compatible. SelectRz according to this equation:
Rz min (0) = VPIJJ.J.IJP/(8mA - iu1AD)
A 10% carbon film resistor is suitable for use as Rz.
Trimming~ponents R" R., R,
R, nulls the offset voltage of the input amplifier. It should
have a series resistance between IOkO and 100kO and a
temperature coefficient less than 100ppm/"C. R. can be a
10% carbon film resistor with a value of IOMO.
RJ nulls the gain errors ofthe converter and compensates
for intitial tol.erances of R,and C,. Its total resistance
should be at least 20119 ofR" if R, is selected 10% low. Its
temperature coefficient should be no greater than five
times that of R" to maintain a low drift of the R.I - R,
series combination.
OFFSET AND GAIN ADJUSTMENT PROCEDURES
To null errors to zero, follow this procedure:
I. Apply an input voltage that should produce an output
frequency of 0.001 x full scale.
2. Adjust R, for proper output.
3. Apply the full scale input voltage.
4. Adjust R, for proper output.
5. Repeat steps I through 4.

If nulling is unnecessary for the application, delete R. and
R" and replace RJ with a short circuit.'
POWER SUPPLY CONSIDERATIONS
The power supply rejection ratio of the VFC320 is
0.015% of FSR/% max. To maintain ±0.015% conversion, power supplies which are stable to within ±I%
are recommeded. These supplies should be bypassed as
close as possible to the converter with O.OI,uF capacitors.
Internal. circuitry causes some current to flow in the
common connection (pin II on DIP package). Current
flowing into the fouT pin (logic sink current) will also
contribute to this current. It is advisable to separate this
common lead ground from the analog ground associated
with the integrator input to avoid errors produced by
these currents flowing through any ground return impedance.
DESIGN EXAMPLE
Given a full scale input of +IOV, select the values of R"
Rz, RJ, C" and Cz for a 25% duty cycle at 100kHz
maximum operation into one TTL load. See Figure 6.
Selecting C, (OFS = 0.25)
C, =[(33 :-106 )/fMAx] -15
[(66 x 10·)/fMAx] -15
ifDFs = 0.5
= [(33 X 106)/ 100kHz] -15

= 31SpF
Choose a 300pF N PO ceramic capacitor with I% to 10%
tolerance.

R, and RJ (DFs = 0.2S)

R, + RJ = VIN max/0.2SmA

VIN max/O.SmA
if DFS = O.S

= IOV/0.2SmA
=40kO
Choose 32.4kO metal film resistor with I% tolerance and
R, = 10kO cermet potentiometer.
Selecting C,
C, = 10' I Fm..
= 10' jlOOkHz
= O,OOI,uF
Choose a O.OOI,uF capacitor with ±SC1i tolerance.
Selecting R,
~!,;-:;:;:p/(8mA - h.(lAll)
= SV / (8mA - 1.6mA), one TTL-load = 1.6mA
= 7810
Choose a 7S00 1/4-watt carbon compensation resistor
with ±5% tolerance.
FREQUENCY-TO-VOLTAGE CONVERSION
To operate the VFC320 as a frequency-to-voltage
converter, connect the unit as shown in Figure 9. To
interface with TTL-logic, the input should be coupled
through a capacitor, and the input to pin 10 biased near
+2.5V. The converter will detect the falling edges of the
input pulse train as the voltage at pin 10 crosses zero.
Choose C, to make t = O.lt (see Figure 9), For input
signals with amplitudes less than SV, pin 10 should be
biased closer to zero, to insure that the input signal at pin
10 crosses the zero threshold. Errors are nulled following
the procedure given on this page, using 0.00 I x full scale
frequency to null offset, and full scale frequency to null
the gain error. Use equations from V / F calculations to
find R" R" R., R" C, andC,.
PIN NUMBERS IN SQUARES REFER TO DIP

R,

~~

T""

r-~J..},f'<--""""-N------ _~~v

Ukn

"BYPASS WITH O.oI"F

FIGURE 9. Connection Diagram for FlY Conversion.

lO-31

.

" ,

TYPICAL APPLICATION.S
Excellent'linearity, wide dynamic range, and compatible
TTL, DTL, and CM OS digital output make the VFC320
ideal for a variety of VFC applications. High accuracy
allows the VFC320 to be used where absol\lteor exact

I

SENSOR.

~

readings must be made. It is also suitable for systems
requiring high resolutioJ:l,upto 14 bit~.
I;igures 10 - 14 show typical applications of the VFC320.

COUNTER

VFC320

PARALLEL
DATA
COMPUTER

FIG URE 10. Inexpensive AI D with Two-Wire Digital Transmission Ovet Twisted Pair:
81
DIFFERENTIAL
INPUT

VIN

'2

J

L'OUT

VFC320

.

I

I

CLOCK

,

I

J

BCD
COUNTER

I

DRIVER/DISPLAY

.

J

FIGURE I L lnexpensive Digital Panel Meter.

0.005% LINEARITY

FIGURE 12.RemoteTransducer Readout via Fiber Optic Link (analog and digital output).
+15V

GAIN ADJUST
+10V TO -10V
INPUT
10
20kO

20kO

REF101.

VFC320

2kO

13

11

7

14

5

SIGN BITo---(1
. OUT

o TO
10kHz
OUTPUT

3300pF

-15V

. FIGURE 13 .. Bipolar input is accomplished by offsetting
the input to the VFC with a refen;nce
voltage. Accurately matched resistors in
the REFIOI provide a stable half-scale
output frequency at zero volts·input.

FIGURE 14. Absolute value circuit with the VFC320.
.
Op amp, D, and Q, (itsj)ase-emitter junction functioning as a diode) provide fullwave rectification of bipolar .input voltages. VFC output frequency is proportionalto led.The sign:bit output provides
indication of the input polarity.

10-32

MILITARY PRODUCTS GROUP

Wafer Processing

High quality products for demanding military and industrial applications are
produced by our Military Products Group in a totally separate facility within
Burr-Brown's complex.
.
Reliability is designed and manufactured-into our MilitaryProducts under
the guidance of MIL-M-3851 O.
Allprqduct fami lies are fully specified from -55° C to +125°C with up to th ree
performance ,grades al'ld two product assurance levels (/883B and IMIL).
The 1883B models are 100% screened to M IL-STD-88~, level B, method 5004
or 500S.The IMIL models have additional requirements of 10% PDA and QCI
consisting of groups A and B on each inspection lot.
How stringently our Military Products group controls and documents the
assembly and testing of its products is described in the product flowsection
that follows.
All materials used by the Mi!it~ry Products group have unique component
specifications to assure their conformity to MIL-STD-883, methods 201 0 and
2017.
.
Environmental control in our clean room areas meets and often exceeds
Federal Standard 209B requiremelnts fOJ particle count. ESD (electrostatic
discharge) procedures are fully Doserved through every stage of matenal
handling, product assembly, testing, storage and shipment. Operator
training, certification and re-certification conform to MIL-M-38510.
MTTF data is based on actual product performance, not just calculated
valu.es. Qualification reports. and test data are available. All data sheets
follow military slash sheetforl'l1at and, because of their completeness, can be
transferred directly to YOiJt drawings with minimal modification. This
standard QPL slash sheet format simplifies your requests to government
agencies for non-standard parts approval.

11-1

m

A CONTROLLED PJlANUFACTURI:NGi.FACIUTYrDED1CATED
EXCLUSIVELY TOM"ILrrARY" QlJAlIl'Y PRODUCtlbN ','
•

PERSONNEL -Allproductioll and quality control
personnel directlyinv.olved with' fabrication,
inspection, testing and handling perform their
functions according, to appropriate MIL specs.

• 'TRAINING - Operator training and certification
programs providehained personnefqualified to
assembleaQ-d test'the' PrOducts\! Certification
requires classroom training and Written examinations for initial certification. Periodic written
exams must be passed to maintain certification.
•

WORK-IN-PROCESS ENVIRONMENT - All work~
in-process is s~ored in a nitrogen environment.
Critical assembly processes; die visual, die ,attach, wirebol")d andallinspectidnsare performed
under laminar flow hbods -equipped with ion
grids - in a class 100 environment

•

ENVIRONMENTA1. CONTROL - Clean room
procedures, which confoi-m to FederalStandard
209B, provide class 10,000 clean air exceeding
the class of 100,000 requirementofMIL-STD-883.

•

MATERIAL CONTROL - Each product has a
complete and current flow chart apd flow sheet
to assure accurate processing through assembly
and test. Each manufacturing lot contains the lot
numbers of its components listed by the quality
control inspection identification (QCID number)
all traceable back to, the incoming vendor's lot
number.

•

Wlrebond (Gold)

MANUFACTURING LOT CONTROL - Each lot
has a unique flow sheet which documents lot
number, parts list, operation, quantity, date of
operation and operator's identification.

• , EQUIPMENT CALIBRATION - Performed under
the guidance of MIL-STD-45662,
•

•

•

QUALIFICATION - All IMIL models are initially
qualified per MIL-STD-883, method 5004 or5008,
groups A, B, C and D as described in "the
products' detailed specification.

Wlrebond (Aluminum)

STATIC CONTROL ~-To minimize static (ESD)
damage, antistatic smocks, stainless steel table
tops, stainless steel work-in-process trays,
ground straps, ion' grids under laminar flow
, hoods and anti~static shipping:, materials - are
used.
RECORD RETENTION - All flow sheets containing process data and inspection records are
'
retained for three years.

Die Attach

11-2

.'

.,

.

DieShea~

,

PRODUCT FLOW
INCOMING
QUALITY CONTROL
INSPECTIQN

MATERIALS

ASSEMBLY LOT
FORMATION

•

ASSEMBLY· MIL·STO-883
CONDITION B
• QC LOT FORMATION GATE
• KIT INSPECTION
• DIE ATTACH
• IPQC DIE SHEAR
• INTERNAL LEAD WIRES
• IPQC WIRE PULL GATE
• PRE·CAP VISUAL INSP.

:IE

~

Assures that all materials meet requirements of the
applicable component specification. Usage tests
are performed and vendor lot ~racEiability begins.

All material is maintained in a bonded stockroom to
assure traceability.
Orgination of manufacturing flow sheets, bill of
material, materials and lot traceability records.

•

QC Lot Formation Gate - matches flow sheet bill
of materials and traceability records with materials issued from the stockroom

•

Kit InsRection - piece parts and die are 100%
visually inspected to meth6ds2010 and 2017.

•

Die Attach - eutectic (providing low ohmic
contact) and non-conductive epoxy (cured at
25°C above storage temperature in nitrogen).

•

In Process DieShearGate- performed to method
2019 on each manufacturing lot. Assures the
integrity of the die attach method.

•

Internal Lead Wi res - Wi res are of the same metal
as the die metalization. Aluminum ultrasonic
wirebond machines are mounted on shock tables
to insure quality bonds. Gold-ta-go/d wirebonds
are performed with thermosonic 'wirebond machines.

•

In Process Wire Pull Gates - bonding operations
are monitored at the beginning of each shift,
every fou r hours, witl) a new lot, new operator or
a machine adjustm~nt. Both destruct and nondestruct tests are performed and the length and
width of each wirebond is measured to verify
conformance to method 2010 or 2017 .

•

Pre-Cal' Visual InSRection - Although not required by MIL-STD-883 it is performed by BurrBrown to method 2010 or 2017.

..........
...
a:
....
...
a::

c

z:

5

a::

l-

e>

z:
~

...
CI

e>

:IE

....

4!

PRE·CAP
FUNCTIONAL
TEST

,

POWER
STABILIZATION

Performed on all products that require laser trimming.

All products that require laser-trimming receive a
72-hour burn-in, in nitrogen, at +125°C.

00
11-3

-~~.....-~ ..

FINAL VISUAL
- PRE-CAP "8" VISUAL INSP.
-IPOC OC CSI/GSI

Resistor networks are I~ser-trimmed to meet ap.plicable specifications.
.

• .,Pre-Cap "8" Visual Inspection - a 1000f0lIisual
inspection,to method 2010 or 20.17.
•

In Process QC Pre-Cap "8" Visual Gate performed to method '2010 'or 2017. (Sburce
Inspectionperfotmed if required,) ,

Following a vacuum bake at +125°C (to meet
method 5004 or 5008 moisture content requirements) products are welded, gold/tin o~ glass
sealed.
.
.
Marking is in accordance with MiL-M-3851 0 and
consists of;
•
•
•
•
•

Part number
Seal date code
Manufacturer's identification (~®)
Manufacturer's designating symbol (CE8S)
Country of origin

A 24-hQurminimum bake at +150o C per MIL-STD-

, 883, method 1008, condition C.

Ten cycles, from-65°C to +150°C per MIL-STD883, method 1010, condition C.

Performed to MIL-STD-883, method 2001, in the Y1
axis only.

Product performance is compared to the specified<
DC parameters at 25°C.
.

Total burn-in time is 160 hours minimum at an
ambient temperature of +125°C per MIL-STD-883,
methpd 1015.
Product performance is compared to the specified
DC parameters at 25°C. Ail 25°C parameters
specified inthe data sheets are read and r~corded.,

11-4

/8838 MODELS

The assembly lot PDA (percent defective allowable)
cannot exceed 10%.
All drift parameters as speciiiedin the data sheet are
100% tested at -SsoC, -2SoC, +2SoC, +8SoC and
+12SoC.
100% test to M I L-STD-883, method 1014, test
condition A.
100% test to MIL-STD-883, method 1014, condition C.

FINAL
VISUAL
-IPQC GATE

/

FINAL
VISUAL
-IPQC GATE

QUALITY
, CONFORMANCE
INSPECTION

80NDED
FINISHED GOODS
STOCK ROOM

Bond Measurement

100% external visual inspection to MIL-STD-883,
method 2009.
•

Final Visual Quality Control Gate - to MILSTD-883, method 2009.

Groups Aand B inspection of MIL-STD-883, method
SOOS or S008 are performed on each inSpection lOt.
Groups C and D inspections are performed when
agreed. to by contract. A report of the most recent
Groups C and D inspections is available from BurrBrown at a nominal charge.
This product flow illustrates major operations only.
Space does not allow a complete description of the,
. numerous details of all operations. Processes and
flows may change to· conform to latestrevisions or
to improved product performance and quality.

Wire Pull

11-5

SELECTION GUIDE
ANAlOG-TO-DIGITAl CONI/ERTERS
Resolution
Model

ADC87/Mll
ADC871883B
ADC87
ADC87U/883B
ADC87U

Bits

llnearny
±lSB, max

12
12
12
12
12

112
112
1/2
1/2
112

Conversion
Time

Gain Drift

' Input

~.max

±ppmrC,max

.Ra,nv.ev.

Operating
Temperature
Rangel1l

8

15'
15
15
15
15

±2.5,
±S,
±10,
010+5,
010+10

Mil
Mil
Mil
.Mll
Mil

'8
8
8
8

{

Package
{ 32·pin
DIP

Page
11-.
11-8
11-8
11-8
11-8

DIGITAl-TO-ANALOG CONVERTERS
Settling
Resolution

Time

Gain Drift

Lif'Jearity

max' ,

Output
Ranges'

Bits

±lSB,max

Monotonlclty

±ppm'oC. max

DAC87-CBI-VlMll
DAC87-CBI-v/B
DAC87-CBI-V
DAC87U-CBI-VlB
DAC87U-CBI-V
DAC87-CBI-I/B
DAC87-CBI-1
DAC87U-CBI-I/B
DAC87U-CBI-I

12
12
12
12
·12
12
12
12
12

1/2
1/2
1/2
1/2
1/2
112
1/2
1/2
1/2

-SS·CI+125·C

20
20
20
20
20
20
20
.20
20

7_c
7_c
7_c
7_c
400naec

{ ±2.5,
±5,
±10,
+5,
. +10

400nsec
.400nsec
400nsec

'{O10 2mA,

DAC870VlMll
DAC870Vl883B
DAC870V
DAC870U/883B
DAC870U
DAC870VLlMIl
DAC870VLl883B
DAC870Vl
DACB70ULI883B
DAC870Ul

12
12
12
12
12
12
12
12
12
12

1/2
1/2
112
1/2
1/2
1/2
1/2
1/2
112
112

25
,25
25
20
20
25
25
25
20
20

7psec
7psec
7psec
7psec
7psec
7psec
7_c
7psec
7Jaoc
7psec

Mqdel

-5soCl+125°C
-55°Cl+125°C
-25· CJ+85· C
-25· C/+85· C
-SS·C/+125·C
-55· C/+125· C
-25°01+85°C

-25°C/+85°C
-55° CI+125° C
-55·CI+~25·C

-SS·C/+I25·C

-25°01+85°C
-2S·CJ+85·C
-SS·C/+I25·C
-55.C/+125°C
-55·C/+I25·C
-2S·CJ+85·C
-25°CH-85°C

7psec

±1mA

{ ±2.S,
. '±5,±10,
010+5,
010+10

Operating
Temperature
Rsnge t.lI

Package

Page

Mil
Mil
Mil
Mil
MIL
Mil
Mil
Mil
Mil

24-pin DIP
24-pin DIP
24-pin DIP
24-pinDIP
24-pln DIP
24-pln DIP
24-pin DIP
24-pin DIP
24-pin DIP

11-24
11-24
11-24
11-24
11-24
11-:18
11-38
11-38
11-38

Mil
Mil
Mil
Mil
Mil
Mil
Mil
Mil
Mil
Mil

{ 24-pln
DIP
ceramic
28{ terminal
leadl...
chip
carrier

11-48
11-48
11-48
11-48
11-48
11-48
11-48
11-48
11-48
11-48

VOlTAGE-TO-FREQUENCY CONVERTERS

M,qdel

,~

"i

VFC32WM1883B
VFC32WM . .
VFC32VMlMll
V.FC32VMI883B
VFC32VM
VFC32UM/883B
VFC32UM

~inearity.

VINRange

FOUT Ringe

V

kHz, max

'I!oFSR,.max

Full Seale Drift
ppm FSRr C, max

±10
±10
±10
±10
±10
±10
±10

200
200
200
200
200
200

±o.OO8 all0kHz
±o.OO8 al 10kHz
±o.OI at 10kHz
±o.OI all0kHz
±o.OI at 10kHz

±loo al 10kHz
±loo allOkHz
-400, +150 al 200kHz
-400, +150 al 200kHz
-400, +150 al 200kHz

±O.01 at 10kHz

±150 at 10kHz

200

±O.o1allOkHz

±150 allOkHz

Operating
Temperature

- Rangel11

Package

Page

Mil
Mil
Mil
Mil
Mil
Mil
Mil

TO-loo
TO-loo
TO-loo
TO-loo
TO-loo
TO-loo
TO-loo

11-120
11-120
11-120
11-120
11-120
11-120
11-120

Operating
Temperature
Range ltl

Package

MULTIPLIERS
Accuracy at 25" C
±.... max '

Model
4213WMI883B
4213WM
4213VM/Mll
4213VM/883B

:§l~~~/~B
4213UM
NOTES:

112
1/2
.1
1
1

Accuracy at 125 C
±%. max
0

4
4
4
4
4

1

2111

1

2'"

Feodlhrough

OUlpul Offsel

±mV. max

±mV, max

Output
V, mA,min

50
50
100
100
100
100
100

25
25
30
30
50
50
50

±10,±5
±10,±5
±10,±5
'±10, ±5
±10, ±5
±10,±5
±10,±S

Mil
Mil

MIL ~

Mil
MIL
Mil
Mil

(1) U grade specifIed lemp;".',lure range Is -2S· C to +85. C, all others specified over MILlemp range.

11-6

(~)

TO-l00',
TO-loo
TO'loo"
T0-100
TO.loo·
TO-l00
TO-l00'
At +85. c,

Page

1",51
11-151
.11'151
11,.111,1
11-151
11-151
11-151

OPERATIONAL AMPLIFIERS
Offset Voltage
DescrIptIon
Wideband

General
Purpose
Bipolar

Model

Bias

at 25°C

drift

tmV, max

±pVloC max

Currenl
nA,max

Bandwidth
Unity Gain
MHz; min

QPA600VM/MIL
OPA.600VM/883B
QPA600VM
OPA600UM/883B
OPA600UM

2'
2
2
5
5

20
20
20
80
80

-100pA
·-100pA
-100pA
-100pA
"l00pA

3500R/MIL

5
5
5

20
20

±3O
±3O
±3O

1

3500R/883B
3SOOUl883B

20131

~

O.ll.
0,12

2
2

±25

0.25

±25

0.25

.250
.250
250
250
250
250
250
.250

2
2
2
5
5
5

-tpA
-lpA

1
1
1
1
1
1
1
1

OPA106WM/MIL
OPA106WM/883B
QPAt06WM
OPA106I1M/Mll
OPA106VM/8838
OPA106VM
OPA1OOUMJ883B
OPA106UM

.250

5
5
5

l00tA
lOOIA
lOOIA
lSOIA
'SOIA
lSOIA
-3OOIA
--3OOfA

Power

OPA8780VM/Mll
OPA8780IIM/883B
OPA8780VM
OPA8780UM/883B
OPA8780UM

.250
.250

.250
.250

10
10
10
10
10

lpA
-'pA

-lpA
lpA
lpA
-lpA

10

10
10
20'3.

20,3.

-."

30
30

--.05

'.05

30
50

- .05

-."

50

PaCkage

Page

125
125
125
150
150

external
external
external
external
external

:tID, :t200
:ttC, ±2oo
ttC, :t200
:1::10.1:200
:ttO. :1::200

MIL
MIL
MIL
MIL
MIL

{'6-Pln

11-94
11-94
11-94

0.6
0.•

--

internal
internal
internal

:rIO, :tl0
.rIO, :tID
:rIO, rtO

MIL
MIL
MIL

TO-99
TO-99
TO-99

11-132
11-132
11-132

0.5
05

-

-

internal
internal

:rIO, ttC
rtO, :1:10

MIL
MIL

TO-99
TO-99

11-143
11-143

0.'
0.'
0.'

-

internal
Internal
internal
Internal
Internal
tnternal
rnterna'
tntema'

tlO,
t:l0,
:'"10,
.t"'O,
rtO,
:tID.
rtO,
:rIO,

1:10
:tl0
±10
±10
±10
1:10
rIO
±10

MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL

TO-gg
TO-gg
TO-gg
TO-99
TO-99
TO-99
TO-99

11-74
"-74
11-74
11-74
11-74
11-74
11-74
1'-74

:tS
t:5
1:5
±S
±5
±S
±5
:t5

MIL
MIL

I

3510VM/MIL
3510VM/883B

.250
.250

mm

400
400
400
400

1

OPA1OSWM/MIl
OPA l05WMl8838
OPA10$WM
OPA l05VM/Mll
OPA 105VM/883B
OPA105VM
OPA 105UM/8838
OPA105UM

.250

satron

Temp;
Rangedl

"""
0.6

Precision
Bipolar

Ultra Low
BIas
Current

n,

1000

Low-Drift,
Low Bias

IS,al
1S,a,

I,
:1::0.01%

{ 5000. '"
A

Operating

Slew
Rate
VIps, min

0.'

-

0.'
0.'
0.'
0.'
12
12
12
12
12
1.2
1.2
1.2

,
,
I
1
,,

1

1
5
5
5
5
5

--

-

15
15
15

-

-

15
15

Output
Compen-

mternal
mternal
mlernal
loternal
mternal
mlernal
Internal
mternal
mternal
internal
Internal
internal
internal

V,mA,

:t'0,
±10,
:tID,
1:10,
1:10,
:tID,
tID.
:tl0.

±3O, ±60
:t:3O, ±SO
±30. ±SO

±30, ±SO
±30, ±SO

INSTRUMENTATION AMPLIFIERS

Description

Model

Very
High
Accuracy

INA258WGlMIL
INA258WGl883B
INA258WG
INA258VG/MIL
INA258V~B

INA258VG
INA258UG/883B
INA258UG
INA258WLlMIL
INA258WLl883B
INA258WL
INA258VLlMIL
INA258VLl883B
IN~VL

INA258ULl883B
INA2S8UL

Range HI

NonLinearity
('110),
25"C,
G=100
max

CMR,DC
G=tO
1kn,
Unbal. •. min
T.

V",,"'T
(pltrC)
max
G=1ooo

1-1000
1-1000
1-1000
1-1000
1-1000
1-1000
1-1000
1-1000

0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1

0.007
0.007
0.007
0.007
0.007
0.007
0.007
0.007

96dB
'96dB
96dB
96dB
96dB
96dB
96dB
96dB

0.5
0.5
0.5
1.0
1.0
1.0

1-1000
1-1000
1-1000
1-1000
1-1000
1-1000
1-1000
1-1000

0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1

0.007
0.007
0.007
0.007
0.007
0.007
0.007
0.007

96dB
96dB
96dB
96dB
96dB
96dB
96dB
96dB

to 60Hz,

1.8'31
1.8'31
0.5
0.5
0.5
1.0
1.0
1.0
1.8'~

1.8'"

-

11-94

11-94

TO-99

MIL,

MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL

NOTES: (1) U grade specified temperature range is -25°C to +85°C; all others specified over MIL temp range.
product. (3) -2S·C/+85·C.
.

Gain
Error
('IIoFS)
25·C
G=100,
max

DIP.

Rate
(VI/A8C)
25"C
G=.100
Rc=2kO

Operoting
Temp.
Flange'"

0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2

MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL

0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2

MIL
MIL
MIL
MIL
MIL
MIL
MIL
MIL

TO-99
TO-99
TO-99
TO-99
TO-99

TO-99
TO-99
TO-99
T0-3
T0-3
TO-3,
TO-3
TO-3

11-84

11-84
11-84
11-84
11-84
11-84
11-84
11-84

lHl0
11-110

1Hl0
11-110
11-110

(2) Gain-bandwidth

Package

{DIP

{~~
LCC

Page

11-111
lHll
11-61
11-61
11-61
11-61
11-61
11-61
11-61
11-61
11-61
11-61
11-61
11-61
11-61
11-61

NOTES: (1) Set with external resistor. (2) MIL = -55·C to +12S·C; U grade specified temperature i.·-2S·C to +85·C; 811 others specified over
MIL tempereture renge. (3) -25·C to +85·C.

11-7

BURR-BROWN®

.'ElElI

'ADC87/MIL SERI'ES
MODEL NUMBERS:
ADC87/MIL
ADC87Ul883B
ADC87/883B ADC87U
ADC87
REViSiON A
DECEMBER, 19~2

12-BIT -55°C to +125°C Military
ANALOG-TO-DIGITAL CONVERTER
FEATURES
• HI·REL MANUFACTURE

• -55°C TO +125°C OPERATION

• ACCURATE
±lI2LSB max Linearity Error
±O.1 % FSR max Full Scale Absolute Accuracy
±15ppm max Gain Drift

• COMPLETE
Internal Reference
Internal Buffer.
Internal Clock

• B~sec MAX CONVERSION TIME

• MIL·STD·B83 SCREENING

DESCRIPTION
The ADC87. MIL Series is a high performanc!,!,
analog-to-digital converter. It features±1 2LSB
linearity, ±O.I% full scale accuracy, ±ISppm drift.
8~sec conversion time, -SS"C to + I2S"Coperation
and optional M I L-STD-883 screening.

I

The ADC87 uses suc~essive approximation. It
resolves the most' significant bit first, then the second
bit, then the third, etc. Successive approximation is
the most popular·high performance design as it is fast
and accurate.
The ADC87 is a hybrid microcircuit. It is complete.
with an internal reference, an input buffer amplifier
and an internal clock. The converter ma¥ be short
cycled to provide faster conversions to less resolution.
Five analog input ranges, ±2.5V, ±SV, ±IOV, 0 to
+IOV and 0 to +20V, are available, and the digital
output data is availabl~ in parallel and serial format.
All digital outputs and inputs are TTL compatible.
Standard power supply voltages, ±ISVDC and
+5VDC, are required.
Two electrical performance grades are available. The
premium grade operates from -S5"C to + 12S"C and is
designed for military, aerospace, and demanding
industrial applications. The U grade has specifications from -2S"C to +8S"C and from -SSoC to + I 25"C.
Applications include test equipment, shipboard, and

ground support equipment where operation is
normally. between -2S"C and +8S"C and full temp- .
erature range operation must be assured.
The ADC87 MIL Series is manufactured on a
separate Hi-Rei manufaciuring line with impeccable
clean room conditiqns which assures inherent quality
and provides for long product life. The ADC87 is
hermetically sealed in a metal. welded, dual-in-line
package.
Three product assurance levels are available: Standard, 883B and MIL The Stil.ndard product
assurance level 'offers Hi-Rei manufacturing where
many MIL-STD-883 screens are performed routinely. The 883B proQuct assuI'anc~ level, 883B.
s'uffix, offers Hi-Rei manufactl!ring plus IOO%screen- .
ing per MIL-STD-883 method S008 (class B). The
MIL product assurance level, i MIL suffix, offers
Hi-Rei manufacturing, 100% screening pcr MILSTD-883B method 5008 and 109i PDA. Quality
assurance further processes, MIL devices, by performing group A and B inspections on each inspection lot and group C and D inspections periodically
and when specified on the customer;s purchase order.
A report containing the most recent gr'oup A. B, C.
and D tests is available for a nominal charge.

International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734 . Tel. (6021 746·1111 • Twx: 910-952·1111 Cable: 88RCORP . Telex:·66-6491

11-8

DETAILED SPECIFICATION
MICROCIRCUITS, LINEAR
ANALOG-TO-DIGITAL CONVERTER
HYBRID, SILICON
I. SCOPE

1.1 Scop..£: This specification covers the detailed requirements for a precision 12-bit, integrated circuit, analog-to-digital
cnnverter.
1.2 Part number. The complete part number is as shown below.
ADC87

;MIL

I

I

Basic model
number

Grade
. (see 1.2.1)

T

Hi-Rei product
designator
(see 1.2.2)

1.2.1 Device typ..£: The device is a single, 12-bit, analog-to-digital converter.
There are two electrical performance grades. The premium grade has no grade designation in the part number and
features specifications and tests from -5'5"C to + 125"C The U grade has a U grade designation in the part number and
features specifications and tests from -25"(' to +85"C and specifications from -55"C to + 125"C
Electrical specifications are shown in Table I. Electrical tests are shown in Tables II and Ill.
1.2.2 Device dass. The device class is similar to the hybrid class (class B) product assurance level, as defined in
M I L-M-3851 O. The H i-Rei product designator portion of the part number distinquishes the product assurance levels as
follows:
Hi-Rei Product
Designator
Requirements
MIl.
Standard model. plus 100l(c MIL-STD-883 hybrid class screening with
10l1c PDA, plus quality conformance inspection (QCI) consisting of
Groups A and B performed on each inspection lot, plus Groups C and D
performed initially and periodically thereafter.
883B
(none)

Standard model, plus 100W M IL-STD-883 hybrid class screening.
Standard model including lOOt;( electrical testing.

1.2.3 Case outline. The case outline is as defined in Figure· I. The case is metal and is conductive.
1.2.4 Absolute maximum ratingi
Supply voltage, Vel'
Supply voltage, V""
Analog inputs (pins 24 and 25)
Buffer input
Digital inputs
Storage temperature range
l.ead temperature (soldering, 6Osec)
J unction temperature

±18VDC
+7VDC
±25VDC
±18VDC
+5.5VDC
-65"C to + 150"C
+300"C
TJ = 175"C

1.2.5 Recommended operating conditions.
Vel': ±14.5VDC to ±15.5VDC
Vim: +4.75VDC to +5.25VDC
-55"C to + 125"C

Supply voltage range
Case

t~mperature

range

1.2.6 Power and thermal characteristics.

32-lead can

Case outline

Maximum allowable
power dissipation

Maximum
8J-C

Maximum
8C-A

Maximum
8J-A

figure I

1500mW at TA = 125"C

7°Cj W

25"Cj W

32°Cj W

11-9

2. APPLICABLE DOCUMENTS
2.1 The following documents form a pa,rt of this specificl!,tipn to;tjle,eJ,!.tent specified herein.
SPECIFICATION
"
,"',
'.'
.
·1
MILITARY
M I L-M-385I 0 - M icrocij.cuit~, General Specificatfon for.
STANDARD
MILITARY
M IL-STD-883- Test Methods and Procedures for Microcircuits.
~'.

3,REQUIREM ENTS
3.1 General. Burr-Brown uses production and test facilities and a quality andreliability assurance program adequate to
assu~ssful compliance with this sp.ecification.
'
3.1.1 Detail sJlecifications. The individual item requirements are specified herein. In the event of conflicting
requirements, the order of precedence will be the purchase order, this specification, and then the reference documents.
3.1.2 Country of manufacture. These microcircuits are manufactured, assembled, and tested within the United States of
Amer~
". "
.
.
3.2 Design, construction, and pJ1ysical dimensions.
3.2.1 Package, metals, and other materials. The package is in accordance with paragraph 3.5.l.of M IL-M-38510, except
that organic and polymeric materials may be used for substrat,e and die attach. Th~exterior metahurfaces are corrosion
resistant. The other materials are nonnutrient to fungus as specified in MIL-M-38510.
3.2.2 Design documentation. The design documentation is in accordance with M IL-M-3851 O.
3.2.3 Internal conductors and internal lead wires. The internal conductors and internal lead wires are in accordance with
M I L-STD-385I O.
3.2.4 Lead mate'rial and finish. The lead material is kovar type (type A). The lead finish .is gold plate with nickel
underplating. The lead material and finish is in accordance with MIL-M-385.10 and is solderable per MIL-STD-883.
method 2003:
3.2.5 Glassivation. All dice utilized are glassivated.
3.2.6 Die thickness. The die thickness is in accordance with MIL-M-38510.
3.2.7 ~ysi~al dimensions. The physic~1 dimensions are in accord~nce with paragraph 1.2.3 herein.
3.2.8 Circuit diagram 'and terminal connection. The circuit diagram and terminal connections are shown in Figure 2.
3.3 Electrical performance characteristics. The electrical performance characteristics areas specified in Table I and
apply over the full operating case temperature range of -55"C to + 125"C unless otherwise specified.
3.3.1 !!Jllut Rang~ The ana!og input range is as specified in Table V when externally connected as shown therein.
3.3.2 OUlj:mt Code. Coding is complementary binary. The digital output codes corresponding to analog input voltages
.
are shown in Table VI.

NOTE:
'Leads in true position within 0.010"
,O.25mm' R al MMC al sealing plane. '

)

(

'-- ,:]

I

DIM

INCHES
MIN
MAX
1.760

1.720

1.120
0000000000000000

1

,.

Pin numbers shown for reference only.
Numbers may not be marked on package.

D

Weight ,25 grams max.

3~o

.170,

1.160
.250

.016

.02\

FIGURE

29.46
6.35

0.41

0.53'

2.'14 BASIC

2.54

14D

I·

100

r. Case Outline (Triple-Wide DIP Configuration).
II-I{}

MAX
44.70

. lOa BASIC

.150
A'

MIN
28.45
4.32

.100

.300

.900 BASIC
00·0 00 0 0 0000 o."i·

MILLIMETERS
43.69

.140'

3.81

3.56
7.62'

'2'2.86 BASIC

2."

3.56

SERIAL OUTPUT

BIT 12 (LSB)

·VCC

BIT 11

BUFFER IN

BIT 10

BUFFER OUT

BIT 9

+VCC

BITa

GAIN ADJUST

BIT7

ANALOG COMMON

BIT6

20V RANGE

BITS

10V RANGE

BIT 4

BIPOLAR OFFSET

BIT3

COMPARATOR INPUT

BIT2

START CONVERT

BIT I (MSB)

STATUS

BIT I (MSB)

CLOCK OUTPUT

SHORT CYCLE
DIGITAL COMMON Y

REFERENCE OUTPUT (6.3V)
CLOCK RATE

VDD

Y

PIn 15 Is connected to the GaBe.

FIGURE 2. Circuit Diagram and Terminal Connections (Bottom View).
3.3.3 Transfer Function. An A, D converter represents an analog input voltage in a digital output format. The converter
resolves the analog input into 12 bits of resolution, or 2", or 4096 voltage segments. For each voltage segment there is a
unique digital output code.
The ideal transfer curve. as shown in Figure 3, is a "stair-case"connecting the extremes of the analog input range. Minus
full scale(-FS) corresponds to digital III I ! IIII I II, the first transition occurs at -FS + I j2LSB, each bit is I LSB wide,
and +FS -I LSB corresponds to digital 0000 0000 0000. An ideal straight line connects each end point and the center of
each bit. A best fit straight line is parallel to the ideal straight line and biased to minimize linearity errors. Note, the
coding is complementary.
0000 0000'0000
0000 0000 0001

1

011111111110

;

c3 01111111 1111 +-------..;-,~!-------f
.ll!
~ 100000000000

...

~

111111111101

'+
ff

111111111110

+

...

1111 II 111111 .....-----?~---'-----N---·FS

OV

+FS

AfIlIlog Input IBlpolar OperaUOIl)

FIGURE 3. Ideal AI D Conyerter Transfer Function.

11-11

The 'basic' converter is unipolar in design; that is, OVDC analog input produces one digital extreme and plus full scale
VDC produces the other digital extreme. There are two unipolar input ranges. For bipolar operation, a bias (bipolar
offset) is introduced into the inptJtsuch that OVDC analog inpurproduces midscale digital output. This allows plus and
, minus analog inputs (see Figure 3). There are three bipolar input ranges.

,

The errors from the best fit transfc;r function are specified in Table I. Linearity and Differential Linearity are the most
meaningfulADC87 accuracy indicators, as they are not externally adjustable. They are factory laser-trimmed. Zero error
and gain error are laser~trimmed and may be externally nulled if necessary for the application. The inherent quantization
uncertainty due to resolving or quantizing the analog input into bits is ± I /2LSB.
,
3:3.4 Timing Considerations. The timing diagram is shown in Figure 4. A start convert, positive going pulse, initiates a
conversion. The most significant bit (MSB) is determined during the second clock pulse,'and each successive bit is
determined during the next II clock pulses. When conversion is complete, Status output drops to LogicO. Digital output
data is available in parallel or serialformat. Serial output data may be strobed out bit-by-bit, during the clock period
after the bit is determined. If desired, an external clock may be used. Further information is available in Applications
Information, paragraph 7.

- - - - - ' - - - - - - - - - THROUGHPUT TIME
START
CONVERT
INTERNAL
CLOCK
STATUS
BIT II.~SBI
BIT2

~"I"

== =J
===J
---J

BIT 3
BI14
BIT 5

LJ'T'
1"0"

rr

1"0"

---~------~.~~~==============~
~-=-~JLJ"'"

BIT 6

===-Ji-'---------,LJ"I"

BIT7

=~=J
==~J

BIT 8
BIT9

LJ:'I"

BIT 11
BIT 12/LUI
SERIAL
DATA
OUTPUT

~~~~~ ~

===J
=-=-

r

1"0"

== =J'--,----------,.-.,.----------,L-j
=J
LJ"I",
=:=

BIT 10

CLOCK

"0"
___

-:::w.&.iJ
''0''

..,..

''1''

4
"0"

5
''0''

8
"I"

"I"'

''I''

W''0''

"I"

1

LSB

10

11

"1"

",."

12
"0"

··O··r
~

-- - -tJ--Lr -lr-1f-1J-1I-~f-lr-l.r -If-lf-lr--LJ--lf -1J
I I

loo,.secID2OOnIec-llI. Slirt Convert mull be II1aall50nuc wlda and mUlt remlln low during converelon. Converelon Islnltllted by the Slirl Convert trilling edge. Onca I convaralon hie begun, a aacond
slln pulse will not rnat the convanar.
.
\ 2. PlrellBi dall wIll be v.,1d I40nuc Iltar IIItUlI gall low Ind remain. vilid until another converelon I. Initiated,
, 3, Serial dill will be valid t40nuc liter an Internll clock rlBlng edgelnd 200naec altar an external clock .Ill11ng edge.
4. When ullng In aXl8rnl1 clock, COIIvlralol1lllnltlll8d by thelllllng Idge 01 the Drat clock pul.e lollowlng sllws going low. The convener will continuously convert.

FIGURE 4, Till)ing Diagram.

11-12

3.3.5 Zero error and gain error adjustment. Zero error and gain error may be externally nulled using the circuits shown in
Figure 6. See /\pplications Information. paragraph 7.4.
3.3.6 Rcyuired external connections. For specified accuracy and speed. connect Clock Rate. pin 17. to OVDC. pin 15.
For a 12-bit conversion cycle. connect Short Cycle. pin 14. to Logic I. pin 16. See Applications I nformation. paragraph 7.
for additional information.
.
3.4 Electrical test re<.juirements. Electrical test requirements are as specified in Table II. The subgroups of Table III and
'Iimits of Table IV. which constitute the minimum electrical test requirements for screening. qualification. and quality
conformance. are specified in Table II.
3.5 Marking. Marking is in accordance with M IL-M-38510. The following marking is placed on each microcircuit as a
minimum.
a. Index point
b. Part number (see paragraph 1.2)
c. Inspection lot identification code.if
d. Manufacturer's identification (iI!IIi')
c. Manufacturer's designating symbol (CEBS)
f. Country of origin (U.S.A.)
3.6 Workmanship..: These microcircuits are manufactured, processed. and tested in a careful and workmanlike manner.
Workmanship is in accordance with good engineering practices. workmanship instructions. inspection and test
procedures. and training. prepared in fulfillment of Burr-Brown's product assurance program.
3.6.1 Rework l'rovisions. Rework provisions. including rebonding for the MIl. H i-Rei product designation. are in
accordance witl] MIL-M-38510.
3.7 Traceabilit},:, Traceability.' for MIL. is in accordance with M IL-M-3851O. Each microcircuit is traceable to the
production lot and to the componentvendor's component 101. Reworked or repaircd microcircuits maintain traceability.
3.8 Product and l'rocess chang!O: Burr-Brown will not implement any major change to the design. materials.
construction. configuration. or manufacturing process which may affect the performance. quality. reliability or
interchangeability of the microcircuit without full or partial requalification.
3.9 Screening. Screening. for MIL and 883B Hi-Rei product designations. is in accordance with MIL-STD-883.
method 5008. hybrid class. except as modified in paragraph 4.3 herein.
Screening for the standard model. includes Burr-Brown QC4118 internal visual inspection and stabilization bake, fine
leak. gross leak. hum-in (72 hours performed preseal). constant acceleration (condition A). and external. visual
inspection per MII.-STD-883. method 5008. hybrid class.
.
For the MI'L Hi-Rei product designation. all microcircuits will have passed .the screening requirements prior to
yualification or quality conformance inspection.
3.10 9ualification. Qualification is not required. See paragraph 4.2 herein.
3.11 9ualit)' conformance inspection. Quality conformance inspection. for the MIL Hi-Rei product designation. is in
accordance with MIL-M-J8510. except as modified in paragraph 4.4 herein. The microcircuit inspection lot will have
.
passed quality conformance inspection prior to microcircuit delivery.

JJ

A 4-digii date code, indicating year and week of seal. is marked on ,. 8838 and (none) Hi-Rei product designations.

11-13

T ABtE I.

Electri~al

Performance Characteristics.

ire ',,:',55°C to+125~C, S'upply liol\~ges ±1!lVDC j\nd +5VDC"u"i"s. ~!Ii~.wi$8
,,' specified"

'.

"ADC87/~iL "
AQC;;81/~B'

CONDITIO"'S

~IN

12 '
,

ADQ87\1/II\I~

ADC87U

1

MAX

"\' '"

I TV!'
IIIAX
',,: . ' 1 1 · '
MiN,

t;'

UNITS

Bits

"

• 1i1P~t Voltage Flanges: Unipolar
,
- ~ipqlar,
.
OireGt ,fn.puJ Impedance: 0
+5V,,±2.5V
to +10V, ±5V
±10V'
Suffer'Amplifi.er: Gain Acqur;acy

Oto +5, Oto +10
±2.5. ±s. ±10
2.5
5
10
±C.01
50
100
2
2

to

,

ADC87
TYP

°

Input Impedance
Input Bias Current
Offset Voltage
Settling Time

Tc = +25°C
Tc = +25°C
Tc = +25°C
20V step to ±0,01 % FSR

V

V
kll
kB
kll
%
Mll
nA
mV
}Jsec

5

DIGITAL INPUTS

Start Convert Command: 21
Positive PU,lse Width
Logic Loading'
."
Short Cycle Logit Loadin'g'
Logic Levels: Logic '" ,.,
Logic "0"
All Digital Inputs

nsec
TTL LoadY
TTL Load
V
V

50

O·e

I

DIGITAL OUTPUTS

Parallel D~t. Coding, !y
Unipolar ,Ranges
Bipolar Ranges
Output Drive
Serial Data COding', NRZ,!y
Output Drive

CSB
COB. CTC
TIL Loads
CSB. COB

"

tTL Loads

Status Bit Coding
Output Dri~e
Internal CrOCk'Output Dri~e"
Logic Levels: Logic "1"
Logic "0"
,All oJtputs", '
'
,,'/.' ..;,

':'~\;'~":';":,

Zero Error, Bipolar..1l

(B~polar M~j.or Tr,"~~~tion,~.rror,

Full Scale Absolute Accuracy Error . ..1I
Bipolar §!
'Gain Error"y

Zero'Error. Unipolar..1l

Full Scale Absolute Accuracy Error, ~
Unipolar
Linearity Error

Inherent Quantization Uncertainty
Differential Linearity Error

No Missing Codes
Monotonicity
Zero Adjustment Range
Gain Adjustment Range

Logic 1 Dunng Conversioll

TIL Loads
TIL Loaos
V
V

2.4

004

+25°C
-25°C to +85°C
-55°C to '+1'25°C
+25°C
-25°C to +85,oC
-55°C to ..... 125°C '
+25°C
Drift V
+25°C
-25°C to -r85°C
-55°C to +125°C

±C,02'

±0,05

±0.05
±0,05

,0,1
'0,1

'±0.02
±0,05

tO,05
±O.1

+0,05

+25°C

:to.1

'0,2

±O,05
±10
+0,10

:!:0,1
715
1'0,15'

±C,15

:!:0:2
!:O.2

±O.l

-25°C to +85'C
. -55°C to +125PC', '
+25°C
-25°C to +85°C
-55°C to +125°C
Drift

+0.2
±1/4

to.05
.:t10

+0,05

+0.10
±C,15
±0.1
±0,2

+0.3

±1/2
±1/4

+25°C
-25°C to +85°C
·55°C to +125°C
Drift

"!:O.3

:!:0.6
±0.25
±OA
+0.9,

!1/2
±1/2

"!:1/2

'0.07
"0,15
'0,3
:!:0,15
,0,25
:!:0.6
'to,1 '
:!:15
+0,2

!1
,2

±1
±4

t1/2
±1
±3

±1
±2
-55
-55
0,3
0,5

0.4
0,55

1,5

7.5
1,6

+125
+125

-25
-25

+85
+85

% FSR§!
%FSR
%FSR
%FSR
%FSR
%FSR
%
ppml"C
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
LSB§!
LSB
LSB
ppm of Fi?R/oC
LSB
LSB
LSB
LSB
ppm of FSR/oC
°c
°C
%FSR
%FSR

DYNAMIC CHARACTERISTICS·

Conversion Time §!
Internal Clock Frequency,#

'*Transfer and dynar:nic characteristics are specified without the optional buffer amplifiers.,

11-14

8

~sec

MHz

TABLE I. Electrical Performance Characteristics (cont).
Tc = -55'0 to +125'C, Supply Voltages ±15VDC and +5VDC, unless otherwise specified. I
LIMITS

CHARACTERISTICS
REFERENCE
Internal Reference: Voltage
Drift
External Current
POWER SUPPLY
Power Supply Range: ±15V Supply
+5V Supply
Quiescent Current: +15V
-15V
+5V
Power Consumption
Power Supply Rejection: +15VDC
-1SVDC
+5VDC
THERMAL CHARACTERISTICS
Operating Temperature Range
Storage Temperature Range
Thermal Impedance: Case to Ambient. DCA
Junction to Case, 8JC

CONDITIONS

MIN

A.DC87/MIL
ADC87/883B
ADC87
TYP

I

6.0

+6.3

Quiescent

Ambient
Ambient

MAX

I

MIN

±15
+5
35
35
40
1300
±0.002
±0.OO2
±0.001

~A

.

±15.5
+5.25
45
45
50
1500

,
.'
-

-55
-65

UNITS

MAX

V
pprnfOC

6.6
+5
200

-55°C to +125°C

±14.5
+4.75

I

. AOC87U/883B
ADC87U'
TYP

+125

-1-150

-55
-65

V
V
rnA
rnA
rnA
rnW
% FSR/%Vcc
% FSR/%Vcc
% FSRI%Vcc

+125
+150

'c

NOTES:

jJ Trailing edge dogic 1 to logic O. initiates conversion.
11 A TTL Load is defined as 40~A max at VIN = 2.4VDC dogie 1" and -1.6mA max at VIN

= O.4VDC dogie a"
J/ esa = Complementary Straight Binary; COB =Complementary Offset Binary; CTC =Complementary Two's Complement. Serial and parallel output data
is in Nonreturn to Zero INRZ, format See Output Coding and Timing Diagram.

jJ Externally adjustable to zero. This specification is without external adjustment.
FSR = Full Scale Range. The ±10V analog input range is a 20V FSR. The ±5V or 0 to 10V input range is a 10V FSR.
Applies to +Full Scale and to -Full Scale.

11 Gain drift is defined as the absolute,value of the change from +25°C to the hot temperature, plus the absolutevalueofthe change from +25°C to the cold

'!Y
.!l/

temperature, and that quantity divided by the tempefature span. This is a 3-point drift. The hot temperature change is usually greate'r than the cold
temperature change.
.
±1 LSB = ±0.024% FSR.
.
Conversion time is defined as the width of the status pulse. It is specified using the internal Clock, with Clock Rate, pin 17, connected to OVOC and Short
Cycle, pin 14, connected to logic 1.

TABLE II. Electrical Test Requirements.
,The individual tests within the subgroups appear in Table HII

~

ADC87/MIL

MIL-STD-883 TEST IIEQUIIIEMENTS (HYBIIID CLASS)

ADC871883B
ADC87

ADC87U/883B
ADC87U

Subgroups I see Table '" I

Interim electrical parameters, preburn-in' (method 5008,
Final electrical test parameters, method 50081
Group A test requirements method 50081
Group C end point electrical parameters' method 5008.
·PDA applies to subgroup 1 ,see 4.3.d

11-15

'C

'elW

20
5

·Specifications the same as ADC87/MIL.

21
.21

'c

1

1

1',2,.3,4,6,7

1,2,3,4,6,7

1,2,3,4,6,7

--

--

Table IV delta
limits and limits

--

--

1
1,

2U, 3U, 4, 6, 7

TABLE Ill. Group A Inspection.
LIMITS

"
ADC87/MIL
ADC87/883B
ADC87
SUBGROUP

PARI\METERS

'CONDITIONS Jj

I
Zero error, biPolari!
Tc =+25°C' Full scale error, 'FS bipolar y
Full scale error, +.FS bipolar y
Gainerrory
Linearity error
Differential linearity error .1/
~o missing codes
Internal reference voltage
Zero error, unipolar :#
Full scate error, unipolar 1/
Gain error. unipolar :y

±IDV range;y
±IDV range ;y
±I DV range ;y
±IDV range

Zero error, bipolar
2
Tc =+1~5°C Full scale error. -FS bipolar 1/
Full scale error, +FS bipolar 1/
Gain drift
linearity error
Differential Linearity error
No missing codes

±IOV range ;y
±IDV range,W
±IOV range ,W
See su bgroup 3

Zero errpr, bipolar 1/
2U
Tc = +85°C Full scale error, -FS bipolar y
Full scale error, +FS bipolar 1/
Gaindrilt
linearity error
Differential linearity error
No missing codes
3
Tc

= -55°C

Zero error, bipolar 1/
Full scale error, -FS bipolar 1/
Full scale error, +FS bipolar 1/
Gain drift
Linearity error

MIN

MIN

±ID
±2D
±2D
±2D
±1/2
±1I2

D to +IDV range;y
D to +IDV range;y
oto +IDV range

Pass
+1l.D
+5

~.6

+15
±20
±ID

MAX

UNITS

±14

mV
mV
mV
mV
LSB
LSB

±30
±30
±20
±1/2
±1I2
Pass
+6.0
+5.

Pass/fail

+15
, ±20
±10

±2D
±4D
'NO

mV
mV
mV

±1
±1

LSB
LSB
Passlfail

.-

±10V range,W
±10V range ;y
±IOV range,W
See subgroup 3U

±30
±50
±50

mV
mV
mV

±I
:tl

LSB
LSB
Pass/fail

Pass
:t2D

±IOV range ;y
:tl0V range ;y
±10Vrange ;y
§J

mV
mV
mV
mV
LSB
LSB
Passlfail

±4Q

±40

±54
:tl
±1

Differential linearity errot

V
mV
mV
mV

~.6

Pass

Pass

No missing codes

Zero error, bipolar 11
3U
Tc = -25°(:; Full scale error, -FS bipolar JJ
Full scale error, +FS bipolar y
Gain drift
Linearity error
Differential linearity error

MAX

ADC87U1883B
ADC87U

±10V range ;y
±10V range;y
:tl0V range;y
§I

mV
mV
mV
mV
LSB
LSB

:t30
:t50

:t50
±33
:!:1
:!:I
Pass

No missing codes

Pass/fail

4
Te=+25°C Conversion time

8

8

,Usee

5
TC = +1 25°C Conversion time

8

8

J.tsee

8

8

~sec

45
45
50
1500

45
45
50
1500

mA
mA
mA
mW
mV
mV
Passlfail
Pass/fail

6
TC = -55°C Conversion time
7
Quiescent current
+Vec
Tc =+25°C
-Vee
Vee
Power consu!nption

Zero

8~just",ent

range

Gain adjustment range
MSB inverted output
Serial output

No load, all bits logic 1

Quiescent
:!:IOV range
±IOVrange

±60
:!:100
Pass
Pass

:!:60
±IOO
Pass
Pass

NOTES:

'.JJ :!:Vee = 15VDC, Voo = 5VDC, no load,withoutthe optional buffer amplifier, unlessotherwise specified. The internal clock is used. Clock Rate. pin 17. is connected
.

-to OVDC. Short Cycle, pin 14, is connected to logic I.
Without external adjustment.
.1J For the :tIOV range: bipolar +FS is ideally at +9.995117VDC; bipolar zero i. ideally at O.OOOVDC; bipolar -FS is ideally at -10.000VDC.
For the 0 to +10V range: unipolar +FS is ideally at +9.997559VDC; unipolar zero is ideally at O.OOOVDC. Refer to Figure 3 and Table VI.
..1/ Monotonicity Is assured by differential linearity :5:tILSB.
.
2 The absolute value olthe gain change from+25°C to+125°C, is added to the absolute valueolthegain change from +25°C to -55°C. This provides a
3-point drift.
2/ The absolute value olthe gain change from +250C to+850C, is added to the absolute value olthe gain change from +25°C to -55°C. This provides a
3-point d r i f t . '
.
~

11-16

TABLE IV. Group C. End Point Electrical Parameters.
'Tc

= +2S0 C. ±Vcc = lSVDC. Voo = +SVDC,
LIMIT

DELTA

Zero error, bipolar

TEST

20mV

10mV

+Full scale error, bipolar

30mV

10mV

·Full scale error, bipolar

30mV

lOmV

Gain error, bipolar

30mV

10mV

Linearity

lLSB

1/2LSB

Differential linearity

lLSB

1/2LSB

TABLE V. Analog Input Range Selection Connections.
DIRECT INPUT

BUFFERED INPUT

Inpul Signal
toPln

Inpul
Impedance

:t2.SV

24

2.Skfl

301026

29 open

23 to 22

:tSV

24

Skfl

30 to 26

29 open

23 to 22

:tl0V

25

10kfl

30 to 26

29 open

23 to 22

o to +SV
o to +10V

24

2.Skll

30 to 26

29 open

23 to 26

24

5kll

30 to 26

29 open

23 to 26

Input Range

Inpul
Impedance

Inpul Signal

to Pin

Required Exlemal Pin Connections

22 to 2S

22 to 25

Required Exlernal
Pin Connections

30

SOMfl

29 to 24

23 to 22

30

SOMfl

29 to 24

23 to 22

30

SOMfl

29 to 2S

23 to 22

30

50MlI

29 to 24

23 to 26

30

50Mll

29 to 24

23 to 26

TABLE VI. Ideal Analog Input Voltage vs Digital Output Code.
DIGITAL OUTPUT CODE
LSB

MSB
Inpul Range

-2.SV

MSB

LSB

MSB

LSB

111111111111

011111111111

0000 0000 0000

lLSB

-2.S00V

OV

+2.498779V

1.2207mV

":5V

-S.OOOV

OV

+4.997559V

2.4414mV

,,10V

-10.000V

OV

+9.995ll7V

4.8828mV

o to -I-5V

OV

+2.S00V

+4.998779V

1.2207mV

o to +10V

OV

+5.000V

+9.997559V

2.4414mV

NOTE:
Analog voltages are the center of the bit rang~. Transitions occur 1/2LSB before and 1/2LSB
after the bit center.

11-17

22 t02S

22 to 25

4. PRODUCT ASSURANCE PROVISIONS
4.1 SamQlingand insQection. Sampling and inspection procedures are.in accordance with MIL-M-38510 and MILSTD-883,-;:;;-ethod 5008, except as modified herein.'
4.2 Qualification. Qualification is not required unle.ss sp~cified by contract or purchase order. When so required.
qualification will be in accordance witht)J~inspection.fouti~e of MIL-M-3851O, paragraph 4.4.2.1 :The inspections to be
performed are those specified herein for groups A, B, C, and 0 inspections (see paragraphs 4.4. I ,4.4.2,4.4.3. and 4.4.4).
Burr-Brown has performed and successfully completed qualification inspection as described above. The qualification
report is available from Burr-Brown.
4.3 Screening. Screening, for, MIL and /·883B Hi-Rei product designations. is in accordance with MIL-STD-883.
method 5008. hybrid c1ass,,·and is conducted on all devices. The following additional crit~ria apply:
a. Constant acceleration test (MIL-STD-883. method 2001) is test condition.A. YI axis only.
b. Interim and final electrical test parameters are specified in Table II. The interim electrical parameters test prior to
burn-in is optiona) at the discretion of the manufacturer.
.
c. Burn-in test (M IL-STD-883. method 1015) conditions:
(I) Test condition B
(2) Test circuit is Figure 5 herein
(3) T A = I 25"C minimum
(4) Test duration is 160 hours minimum
d. Percent defective allowable (PDA). The PDA. for the MIL Hi-Rei product designation only. is 10 percent and
includes both parametric and catastrophic failures. It is based on failures from group A. subgroup I test after
cool-down as final electrical test in accordance with MIL-STD-883. method 5008. and with no intervening
electrical measiJrements. If interim electrical parameter tests are performed priorto burn-in, failures resulting from
preburn-in screening may be excluded from the PDA. If interim eleCtrical parameter tests prior to burn-in are
omitted. all screening failures shall be included in the PDA. The verified failures of group A. subgroup I after
burn~'in in that lot areusedto determine the percent defective for that lot. and the lot is accepted or rejected based
on the PDA.
e. External visual inspection need not include measurement 'orcase and lead dimensions.

+15VDC

+5VDC

FIGURE 5.!est Circuit. Burn-in and Operating LifeT,est.

4.4 Quality conformance insQection. Groups A and B inspections of MIL-STD-883.method 5008. are performed on
each inspection lot. Group D. subgroup I, seal test, of MIL-STD-883, method 5008. is performed on each lot of packages
procured. Groups C and D inspections (except for subgroup I, seal test) ofM IL-STD-883. method 5008. are not required
unless specified by contract or purchase order.
Burr-Brown periodicaly performs groups C and D inspections of MIL-STD-883. method 5008. A report of the most
rec;ent groups C and D inspections is available from Burr-Brown.

11-18

4.4.1 Group A insfledion. Group A inspection consists of the test subgroups and LTPD values shown in M I L-STD-883.
method 5008. and as specified in Table II herein.
4.4.2 Group B inspection. Group B inspection consists of the test subgroups and LTPD values shown in M IL-STD-883.
method 500s.-- - - .

.

4.4.3 Groufl C inspection. Group C inspection consists of the test subgroups and LTPD values shown in M II.-STD-883.
method S008. and as follows:
a. Operating life test (M I L-STD-883. method 100S) conditions:
( I ) Test cond ition B
(2) Test circuit is Figure S herein
(3) T \ = 12S"C minimum
(4)Test duration is 1000 hours minimum
b. End point electrical parameters are specified in Table II herein.
c. Additional electrical subgroups are specified in Table II herein.
4.4.4 Group D inspection. Group D inspection consists of the test subgroups and LTPD values shown in M I L-STD-883.
.
method S008.
4.S Methods of examination and tes·t. Methods of examination and test are specified in the appropriate tables. Electrical
test circuits are as prescribed herein or in the referenced test methods of M I L-STD-883.
4.S.1 Yoltage and current. All voltage values given are referenced to the external zero reference level of the supply
voltage. Currents given are conventional current and positive when flowing into the referenced terminal.
4.6 I nSflection of flrel'aration for deliver)!. Inspection of preparation for delivery is in accordance with M I L-M-38SI0.
except that the rough handling test does not apply.

S. PREPARATION FOR DELIYERY
ii.1 Preservation-flackagi.!!.g and packing. Microcircuits are prepared for delivery in accordance with M II.-M-38SIO.

6. :'IIOTES
6.1 :-\otes. The notes specified in M IL-M-38SI0 are applicable to this specification.
6.2 Intended use. Microcircuits conforming to this specification are intended for use in applications where the use of
screened parts is desirable.
6.3 Ordering data. The contract or order should specify the following:
.
a. Complete part number (see paragraph 1.2).
b. Requirements for certificate of compliance. if desired.
6.4 Definitions.
Full Scale Absolute Accuracy Error. Full scale absolute accuracy error i~ the difference between the ideal and the actual.
unadjusted .. analog input \oltage at the full scale points. It applies to unipolar plus full scale. bipolar minus full scale. and
bipolar plus full scale. Absolute accuracy includes lero. gain. linearity. and noise errors and. when specified over
temperature. includes tht' drifts of thes.e errors. It is measured at the first or last transition .. as appropriate. The error is
expressed in I.SBs or 'i of FSR.
!!il'olar Zero Error. Bipolar zero error is the.difference between the ideal and the actual analog input voltage for the
digital output code 0 III IIII 1111. It is measured at the 100000000000 toO III IIII IIII transition which ideally occurs
at OYDC -I 2LSB.
Bipolar zero error is also km)wn as bipolar major transition error.
LJ niJlolar Zero Error. LJ nipolar zero error is the difference between the ideal and the actual analog input voltage for the
digital output code IIII II II IIII (unipolar). It is measured at the IIII 1111.1111 to IIII IIII 1110 transition which
ideally occurs at OYDC +1 2LSB.

Gain Error. Gain error is the difference between the ideal and the actual analog input voltage span. It applies to both
unipolar and bipolar input ranges. It is measured between the firSt transition and the last transition which is ideally FS R
-2LSB.
Gain error in some literature describes What is defined herein to be unipolar full scale error and bipolar plus full scale

11-19

Offset Error.This term'is not used ~ith the A DC8.7. Offset error in some literature describes what is defined herein to be
unipolar zero errorand/ or bipolar minus full sc~le error.
' '
.
'

Linearity Error. Linearity error is the difference between the ideal and the actual bit tran~i~ion when zero error a,nd gain
errorequ~.
,
'
Differential Linearity-.Error. Differential linearity error is the difference between the ideal and the actual bit step width.
Zero differential linearity error means each bit step width is I LSB.A maximum differential linearity error of± I' 2LSB
'
means a bit step width may be between I,' 2LSB and 3 2LSB.

Monotonicity. Monotonicity is the condition where the digital output code remains the same or increases for an
increasing an;;-Iog input signal.
'
Quaniization Uncertainty. Quantization uncertainty is the inherent uncertainty of being able to determine the analog
~oltage which produces a digitai code. Because the analog input voltage is divided or quantized into a finite number of
bits. each digital code represents an analog voltage span equal to .I LSB. Qu,tntization uncertainty is, ±I 2LSB. Its
magnitude may be reduced only by using a higher resolution converter.
6.5 Microcircuit group assignment. These microcircuits are Technology Group F as defined in M I L-,M-38SI O. Appendix

E.

----

6.6 Electrostatic sensitivity. These microcircuits may' be damaged by electrostatic discharge. Electrostatic,sensitive
. '
precautions should be obser-ved at all times.
7. APPLICATIONS INFORMATION
7.1 ~yout. To produce ~Iean. noise-free. accurate conversions. high frequency layout techniques should be used. Wide.
low inductance conductor patterns. short and direct external component leads. power supply decoupling. and a ground
plane are recommended. Long runs should be avoided, Coupling and runs. which mightcause inpiJt-to-output coupling.
should be avoided. High impedance points should be given special consideration. The input to the buffer. the comparator
input (particularly sensitive) and the external adjustment pins are sensitive. Shielding by Analog Common or ± 15VDC
supply patterns my be helpful.
7.2 Grounding. A ground plane under the ADC87 is recommended.
Analog Common (pin 26) and Digital Common (pin 15) must be connected to¥ether and to the analog system ground.
Preferably. connect both commons directly to the ground plane under the ADC87. If these commons must be run
separately. use wide conductor patterns and connect a O.OIJ.LF ceramic capacitor between the commons at the unit. The
case is connected to Digital Common. pin 15.
7.3 Power Supply Decoulliing. For optimum performan'ce and noise rejection. each power supply should he decoupled
by connecting a IJ.LF tantalum capacitor and a O.OIJ.LF ceramic capacitor from each power supply to the groun,d plane.
Locate the capacitors close to the c O , n v e r t e r . ·
'
7.4 Qlltional External Zero and Gain Adjustments. The ADC87 zero error and gain error are factory laser-trimmed to
position the staircase transfer function within Ta~le I specifications. Optionally. two adjustments ,null zero error and
gain error (see Figure 6).
Zero adjustment moves the entire staircase left-to-right. For unipolar ranges. -FS. OV DC. is nulled. For; bipolar ranges.
midscale. qVDC. is nulled. (Alternately. bipolar -FS may he nulled.)
Gain adjustment adjusts the span of the staircase. Adjustmenteffectively rotates the.staircase about -FS. For unipolar
and bi'polar ranges. zero adjustment should be made first. then +FS error is nulled.
'
Adjustments should be made after a 10 minute warm-up. Fixed. selccted resistors may be substituted. for the
potentiometers after the adjustments have been determined. if desired. If adjustments are not used. pin 22 (zero adjust)
should only be connected as required for analog input rangeselectioil and pin'27 (gain adjust) should be eithergrounded
(recommended) or.open.
7.4.1 Zero Adjustment Procedure. For the selected unipolar range. apply the analog input voltage at which the IIII 1111
IIII to IIII IIII 1110 transition ideally occurs. OVDC +1, 2LSB, While continuously converting. adjust the zero
potentiometer until the transition "flic,kers".
For the selected bipolarrange~ apply the analog input voltage at which the 10000000 0000 to 0111 1111 IIII transition
ideally occurs. OVDC -lj2LSB. While continuously converting. adjust the zero potentiometer until the transit-ion
"flickers". 7.4.2 Gai,n Adjustment Procedure. Make zero adjustment first. For all input ranges. apply the analog input voltage at
which the 0000 0000 0001 to 0000 0000 0000 transition ideally occurs. +FS -3 2LSB. While continuously converting.
adjust the gain potentiometer until the transition "flickers", For bipolar ranges. re'peat 7,cro and gain adjustments as they
" are interactive.

11-20

y
~
YY

Pln22

l.BMn

+15VOC

+15VOC

+15VOC

f ·

IOkn to
tookn

YY
I BOkn

Y
I~}n

i

Pin 22

·15VDC

10kn to
1DOW

PinYY
27

IOMn

~

y

~IOknto

O.O~ Y

1000n

22kn
·15VDC

+15VDC

Pin 26

.15VOC

Adjustment Range =0.4% FSR 1±0.2% FSRI

§j

Pin 27

1/Y
270kn

270kn .

.
~
6.8kn

O.O~ 1/

Pin 21!

-=

f

3!

IDkJlto

l00kn

.15VlIC

Adjustment Rango =0.55% FSR 1±D.27% FSRI
Ibl Gain Adlustment

lal Zoro Adjustment
Notes:

1/ Locate as close as possible to the converter to minimize noise pickup.

y

5% carbon composition or beHer.

~

An attentuator network may bo substituted lor the series resistor lor lower Impedance and lower noise susceptibility.

Y Use multlturn potemlometera with lDOppm/'C TCR or less to minimize drift wHh temperature.
FIGURE 6. Optional External Zero and Gain Adjustment Circuits.

7.5 Start Convert and Status. To start a conversion. a positive pulse with a minimum pulse width of 50nsec must he.
applied to the Start Convert terminal, pin 21. The trailing edge (falling edge) resets the converter. starts the internal clock
and initiates a conversion. The start convert input must remain logic 0 during conversion. as the internal clock is stopped
by logic I and the output will be erroneous. Another start convert pulse during a conversion does not reset and re"Start a
conversion: it may momentarily stop the internal clock and produce an erroneous output.
Status output. pin 20. is logic I during conversion. When a conversion is complete. Status drops to logic 0 and the
internal clock is turned off. Refer to the timing diagram. Figure 4.
7.6 Continuous Conversion. The ADC87 will continuously convert, commencing a new conversion immediatciy after
the last conversion. when wired to accept an external clock. See paragraph 7.8 and Timing Considerations. paragraph
3.3.4. Alternately. the internal clock may be used with a new start convert common every 8.7J.Lsec or slower.
7.7 Internal Clock and Clock Rate. The ADC87 is specified and tested using the internal clock. The internal clock is
factory adjusted to 1.6M Hz with Clock Rate. pin 17. connected to OVDC (Digital Common). U nderthese conditions. the
ADC87 will meet all the conversion speed and accuracy specifications.
The internal clock frequency may be increased or decreased by applying a positive or negative voltage to Clock Rate. pin
17 (see Figure 7). The circuits shown in Figure 8 may be used. Increasing the clock frequency decreases the conversion
time: however. linearity errors increase as shown in Figures 9 and 10. Decreasing the clock frequency is accomplished hy
using a negative voltage or using an external clock (see paragraph 7.8).

15

~

.............

r=::::::r--

12·m
10·BIT

o
·5

+5
Control Voltage IVUCI

+10

+15

FIGURE 7. Clock Rate Control Voltage.

11-21

+5VOCJj

+15VOC

__.1.~:r

1M
12kll

_-C-_ _ _,
Pin 17y

Pin 17'y

II) Flnl Ad)ustmlnt Rlngl

Ib) COIIII AdlllllmMlt Ringe

Notu:

Jj USI nagaOvl supply III dlcreall the clock frequailcy. '
.y Pin 17 Is not connected to DYOC when using clock 1111 adlustment potentlomel8r.
.'Y Multlblrn pDI1ntIDm8l8r wHh lDDppm/oC TCR or IllS.

FIGURE 8. Clock Rate Adjustment. Optional.

0.150

0.150

=

~ 0.125

o.t25

o.1

lO·81T

~

0.05

0.025

o

J81T

\ \
\

!!

.::; 0.075

~

.::.
~

-

€
~
::::;

"- ~

- ~.'

co

-- -

t2·81T LIMIT

8 .

2

10·BIT LIMIT

\ l\.

0.025

-- ~

--

12·81T LIMIT
10

2
Convlrslon Tlmel"slc)

Convmlon Time I"sec)

FIGURE 9. I.inearity vs (onversion Timc.

0.00

o

10

12!8rr

\\
\\

0.075

J

11).81T LIMIT

10·81T

D. t

FIGl.'RE 10. Differential Linearity \'s Convcrsion Timc.

7.8 External Clock. An external clock may be uscd with the ADC87 for synchronization orspecial timing applications.
The external clock frequency must be lower than,the internal clock frequency, However. the internal clock frequency
may be increased: see parag~aph 7.7.
The external clock is corinected to the Start Convert terminaL pin 21. The normal. start convert positive pulse signal is
not required. The external clock must bc a negative-going pulse. IOOnsec to'200nsec wide. at a frequency lower than the
'internal clock. The falling edge (leadipg edge) ofthe external clock statts the internal clock. The internal clock completes
one cycle. then ceases as the Start Convert terminal. pin 21. is logic I at that time. The next external clock falling edge
turns on the internal clock again. for one cycle. The Clock Output signal. pin 19. displays the internal clock synchronized
to the lower,. external clock frequency. A conversion is complete and Status output drops to logic 0 after. 13 clock pulses.
The converter will provide continuous conversions as long as the external clock signal is present. A conversion is
. complete when Status outpUt drops to 10gicO. Status remains logicO for one external clock period. The next conversion
starts on the next falling edge of the external clock following conversion completion. Conversio'ns cease when Start
Convert input is logic I.
'
A circuit to generate an external clock signal from a clock with an arbitrary duty cycle is shown in Figure II. A circuit to
generate an external clock signal from a convert command is shown in Figure 12.

11-22

+SVDC
5.llIm
+SVBC

S.Okn
I

i
:4

t-i-"----~

I

i
:4

t-r---~

ABC87
START
CONVERT.
Pin 21

1.-_ _ _ _ _

EXTERNAL
CLOCK

~

ADC87
START
CONVERT.
Pln2i'

ADC87
STATUS.
Pin 20

OICI
(TO PIN 211
~

-

STATUS
END OF PREVIOUS

'OICI----,,.--.,,..---,...--....,,-(TO PIN 211

l50nncTYPICAL
.

CONVERS~Uii OF NEXT CONVERSION.

-11--150nIBCTYPICAL

Note:
The axternal clock frequancy musl ba lowar Ihan Iha Intamll clock frequancy.
Exlarnal clock can hava any deilred duty cycla.

STATUS _ _--'
Note:
Start Convert and Ihl external clock mUli be high Ilmuhaneously to Inlllite a
convarslon. The convlralon wlllslirt on Ihe riling edge 01 theldlrnal clock.
Any coovert commands Ihal occur during I COllVBrlmn will ba Ignored.

FIGURE 12. Conversion Initiated by Convert Command
Using Continuous External Clock.

FIGURE I I. Continuous Conversion Using External
Clock with Arbitrary Duty Cycle.

7.9 Short Cycle. The ADC87 conversion cycle may be stopped prior to converting all 12 bits. This provides faster
conversions tOless resolution. For conversions to n bits. connect the n + I bit output to Short Cycle. pin 14. The
remaining bits are truncated.
.
Figure 13 shows a complete cycle and a short cycle to 10 bits. For 10 bits the internal clock frequency has been increased
to provide the minimum conversion time. See Clock Rate. paragraph 7.7.

RlsoluHon (bltsl
Clock Rlla connect pin 17 to pin
Short Cycle connect pin 1410 pin
Conversion Speed paIC. max '

12
15
16

8

10
10
2
5

• FIGURE 13. Short Cycle Connections.

11-23

BURR-BROWN@

DAC87/MIL SERIES

IElElI

MODEL NUMBERS:
DAC87-CBI-VlMIL .. DAC87U-CBI-VlB
DAC87-CBI-VlB
DAC87U-CBI-V
Jj .
DAC87-CBI-V

. , .. '

REVislDN D .
~PRIL. 1984

12-Bit ';55~e to f125°C Military'
DIGITAL-TO-ANALOG.CONVE.RTER
,
. .

. '
,~

,

.'

FEATURES
• HI·REL MANUFACTURE
.• COMPLETELY SPECIFIED; ·55°C to +125°C .
• ACCURATE
±1/2LSB max Linearity. over temperature .
±2Oppm/"C maxGlln Drift
±D.2% Total Error. over'temperature
Monotonic. over temperatura .

• OPTIONAL MIL.STD:883 SCREENING
• DAC85 PIN·COMPATIBLE
• COMPLETE • INTERNAL REFERENCE
AND OUTPUTAMPLIRER

DESCRIPTION
The DAC87! MIL Series is a high performance. 12bit. TlL-compatible. ·55"Cto +125"C digital-to~
analog converter in a metal. welded. hermetically
sealed package .. and it is manufactured on a separate
hi-re( production line. It is pin-compatible with
DAC85 converters and has five user-selected .output
ranges. Each DAC is a complete device with an
internal output amplifier and an ultra-stable reference.
The DAC87! MIL Series is designed for high accur.acy. wide temperature applicatio·ns. The total accuracy without external trim adjustments is ±O.I% of
FSR, decreasing to only±0.3% of FSR over -55"C to
+125"C. With ~xternai. offset and gain trim adjustments at +25"C. the total accuracy is less than ±0.2%
of FSR over -55"C to + 125"C. Gain drift is less than
20ppm/"C. Linearity error. contributed mostly by
the internal current switches and resistive ladder, is
reduced by laser trimming to less than ±1!2LSB over
temperature. Differential linearity is less than ± I LSB
over temperature thereby guaranteeing monotonicity
from -55"C to +125"C.

J1

There are two electrical performance grades and
· three product assurance levels allowing a wide
application! bud.get choice. The. DAC87-CBI-V model grade features excellent performance from -55"('
to + I 25"C and finds wide military, aerospace. and
industrial applications. The DAC87U-CBI-V model,
grade features excellent performance from -25"C to
+85"C. andg'Uarantees specifications from -55"C to
+ I 25"C. Applications include test equipment. shipboard. ground support. and shirt-sleeve environments
where operation is between -25"C and +85"C but full
temperature operation must be assured.
The three product assurance levels available are:
standard; ! B (100% screened per M IL-STD·883
method 5008. hybrid class. Class B); and! MIL (100%
screened. plus PDA = 10%. plus Groups A and B
testing on each inspection lot. plus Groups C and D
performed initially. periodically. and when specified
on the customer's purchase order). See paragraph
1.2.2 for more details. Each device is manufactured in
a hi-reI environment with Clean room conditions
which assures "built-in" quality.

Current output models are also available. Contact Burr-Brown.

Iniernatlonal Alrpo~t Industrial Park· P.O. 80x t t400 • Tucson. Arizona 85734 . Tel. (6021 746·1111 . Twx: 910-952·1111 . Cable: 88RCORP . Telex: 66·6491

11-24

DETAILED SPECIFICATION
MICROCIRCUITS, LINEAR
DIGITAL-TO-ANALOG CONVERTER
HYBRID, SILICON

I. SCOPE

1.1 Scope. This specification covers the detail requirements for a 12-bit. TTL-compatible. integrated circuit'. digital-toanalog converter.
1.2 Part Number. The complete· part number is as shown below.
MIL
v
DAC87
CBI

I.l

Basic model
number

Grade
(see 1.2.1)

T

l

Voltage
output JJ

T

Hi-Rei product
designator
(see 1.2.2)
1.2.1 Device type. The device is a single. 12-bit. digital-to-analog converter. The input coding is complementary binary.
Thedevice may be externally pin-connected foreitherComplementary Straight Binary (CSB) or Complementary Offset
Binary (COB) coding (see Tables V and VI).
There are two electrical performance grades. The premium grade has no grade designation in the part number and
features specifications and tests from -55"C to + I 25"C. The U grade has a U grade designation in the part number and
features specifications and tests from -25"C to +85"C, and specifications froin -5'5"C to + I 25"C, .
Input coding
(Complementary Binary)

Electrical specifications are shown in Table I; electrical tests are shown in Tables II and III.
1.2.2 Device class. The device class is similar to the hybrid class (class B) product assurancc Icvel. as defincd in
M I L-M-38510. The Hi-Rei product designator portion of the part number distinguishes the pr,)duct .issurancc Ic\'cls as
follows:
Hi-Rei Product
Designator
MIL

B

(none)

Requirements
Standard model, plus 100% MIL-STD-883 Class B screening, with 10%
PDA, plus quality conformance inspection (QCI) consisting of Groups A
and B on each inspection lot, plus Groups C and D performed initially
and periodically thereafter.
Additional electrical testing is performed in / MIL models.
Standard model, plus 100% MIL-STD-883 Class B screening.
Standard model including 100% electrical testing.

1.2.3 Case outline. The case outline is as defined in Figure I. The case is metal and is conductive.
1.2.4 Absolute maximum ratings.
Supply voltage. V'T
Supply voltage. VI)I>
Data input voltage
Output short circuit duration
Storage temperature range
I.ead temperature (soldering. 6Osec)
JunctiQri temperature

.JJ
.JJ

±18VDC
OVDC to +18VDC
-I VDC to +7VDC
Unlimited lJ
-65"C to +150"C
+300"C
TJ = 175"C

Current output mode!!>. are also a\allable. Contact Burr-Bro~n .
Short CIrcuit may be to ground (lnJ~. Rating applies to IIS"C case temperature or 65"(' ambient temperature.

11-25

:::!

::IE
......
,...
CICI

c,:)

C
CI

1.2.5 Recommended operating conditions.·' .,
Supply voltage range
,J Vi·c: :;!:14.sVI:)Cto ±IS.5VDC
, ,Vnn: +:4.7SVB€ to+5.25VDC
Ambient temperature range'-S5"Cto +12S';C ,
1.2.6 Power and thermal characteristics.
Maximum allowable
power dissipation
Package
Case outline
Figure I

24"lead can

Maximum

Maximum

1350mW at T" - 12S"C

8 J-C

8 J-A

7"C/W Jj

37"C!W

2. APPLICABLE DOCUMENTS
. 2.1 The following documents form a part of this specification to the extent specified herein.
SPECIFICATION
MILITARY
M 1l--M-38510 - Microcir,::uits. General Specification for.
STANDARD
MILITARY
MIL-SJD-883 - Test Methods and Proceduresfor Microcircuits.
3. REQUIREMENTS
3. J General.. Burr-Brown uses.production and test fac,ilities and a quality and reliability assurance program adequate to
assu~ssful comp'lia~ce with thIS specification.
3.1.1. Detail specifications. The, individual item requirements are specified ~erein. In the event of conflicting
r,equirements. the order of precedence will be the purchase order. this specification. (lnd then the reference documents,
3,.1.2 Country of manufacture. These microcircflits are manufactured. assembled. and tested with'in the 1I nited States of
America.
3.2 Design. construction, and physical dimensions.
3.2.1 Package. metals. and other materials. The package is in accordance with paragraph 3,5, I of M II.-M-38SIO except
.organic and polymeric ,materials may be used for substrate and die attach. The eXlerior metal surfaces are cilrrosion
resistan,t. The other materials are nonnutrient to. fungus as specified in M II.-M-38SIO,

iA=:j

D[ .. tm,.
'--

" - - - Denotes pin 1

f=r)
f

G

d

J UlIIIIII ~L·
H
000000000000'

1

12

24

13

DIM

leads in true position with'in 0.010"
.Q,25mm' R at MMC at seating plane.

INCHES
MIN
MAX

MILLIMETERS
MIN
MAX

A

1.365,

1.385

34.67

35.. 18

B

.810

20.07

20.57

C

.790
,)70

.250

4.32

6.35

0

.016

.021

0.41

0.53

G

.100 BASIC

I

.150

3.18

.300

3.81

K

.125
,.150

L

,.600 ,BASIC

R

.080·

H

L

2.54 BASIC

.110

3,81

I

7.62

15.24 BASIC
2.03

I

2,79

0

Pin numbers shown for.reference only.
Numbers may not be marked OA packa,ge.

R

000000000000

Weight 15 grams max.

FIGURE I. Case Outline (Double-Wide DIP Configuration).

JJ

Rating applies to normal device operation. For the output short circuit condition. the maximum 8J·C of the output die of IOO"C W must be applied to the output
short circuit current.

11-26

3.2.2 Design documentation. The design documentation is in accordance with MIL-M-38510.
3.2.3 Internal conductors and internal lead wires. The internal conductors and internal lead wires are in accordance with
MIL-M-38SI0.
3.2.4 Lead material and firiish. The lead material is kovar type (type A). The lead finish is gold plate with nickel
underplating. The lead material and finish is in accordance with MIL-M-38510 and is solderable per MIL-STD-883.
method 2003.
3.2.5 Die thickness. The die thickness is in accordance with MIL-M-3851O,
3.2.6 Physical dimensions. The physical dimensions are in accordance with paragraph 1.2.3 herein.
3.2.7 Circuit diagram and terminal connections. The circuit diagram and terminal connections are shown in Figure 2.
3.2.8 Glassivation. All dice utilized are glassivated.
3.3 Electrical performancecharacteristtcs. The electrical performance characteristics are as specified in Table I and apply
over the full operattng ambIent temperature range of -55"C to +li5"C. unless otherwise specified.
3.3; I Offset and gain error adjustment. The DAC is capable of being externally adjusted to zero offset error and to zero
gain error using the circuits in Figure 3. See applications information. paragraph 7.3.
3.3.2 Input coding. The input coding is complementary binary. The digital input code to yield the corresponding output
voltage(or the output ranges is specified in Table V.
3.3.3 Output range. The output range is specified in Table VI when ~xternally connected as shown therein.
3.4 Electrical test requirements. Electrical test requirements are specified in Table II. The subgroups of Table III and
limits of Table IV which constitute the minimum electrical test requirements for screening. qualification. and quality
conformance. are specified in Table II.

6.3V
REFERENCE
OUTPUT

IMSI, BIT I
IITZ

GAIN ADJUST

BIT3

+VCC

BIU

COMMONY

81T5
8118
BI17
81TS

12·BIT
LADDER
RESISTOR
NETWORK
AND
CURRENT
SWITCHES

+15VDC

+15VOC

SUMMING
JUNCTION

OFFSET
ADJUSTMENT

Y

ZOV RANGE

y

~

lOY RANGE

100cuID
IODkll

SUMMING
JUNCtiON

1118

REFERENCE INPUT
OUTPUT

BIT 11

,Vce

(lSBIBITI2

VOO

y
}------~ltl!~
D.O'I1~F ta
O.o1~f

BIPOlAR OFFSET

81T1D

GAIN ADJUSTMENT

·15VDC

·15VOC

1/ ';IODppm/OC.

Y

±ZO% clrban_pOlIUon or beUer.loCIII cia.. \0 Ihl OAtB7
\0 prevenlllOlll pickup.

'U Clrlmlc.

y Pin 21 II canMelld ID the CIII.
FIGURE 2. Terminal Connections.

FIGURE 3. Offset and Gain Error Adjustment Circuits.

11-27

TABLE I. Electrical Performance Characteristics.

I

CHARACTERISTICS

CONDITIONS

JI

RPOLUTION
DIGITAL INPUTS
Input voltage
Loglc"I"

TA = +25°C
-5SOC';;TA';;+125OC
TA = +25°.C
-55°C';; Til. ';;+125°C

Logic "0"
Input Current
Logic "1"
Logic "0"

Y,N =2.4V
V'N=Q.4V,

ACCURACY
Total error, untrimmed ~
Unipolar

Linearity

Differential linearity error .§J

Monotoniclty temperature range §/
Offset error .§I
Unipolar y

Bipolar

-1.6

+40
0

rnA

~A

.

±D.l0

±D.25
±0.30
±0.10
±D.25
±D.30

y

.

±D.0122

±0.50
±0.50
±3
±0.75
±1,Q
+3.

LSB
LSB
LSB

±D.20
±D.0122

±D.OOO

±0:15
±D.20
±D.25

±D.SO

±D.50

±D.75

±0.25

±D.SO
±D.50

o·

.'

'.

+1.0
+125
to.02

±0.05 .

±D.02

±D.08
±a.05

-25

'

..

%ofFSR
%ofFSR
%olFSR
%.ofFSR
%01 FSR
%ofFSR
%ofFSR
%olFSR
%ofFSR
%ofFSR
%ofFSR
%ofFSR
LSB
LSB
LSB

±G.15

-55

+85

°C

±0.02

±0.05
±0.OO8

±0.02

±0.05.
±0.10

%OfFSR
%ofFSR
%ofFSR
%ofFSR
%ofFSR
%ofFSR

±D.l0

Y

Unipolar

-25°C to +85°0

Bipolar

, -55°C to +1 25°C
-25°C to +85°C:
-55°C to +125°C

Offset adjustment range

',·,±1
±5
±0.15

Gain error §/ J/
Unipolar'y

TA = +25°C
-25°C';; TA .;; +85°C
TA = +25°C
-25°C';; TA .;; +85°C
-55°C';; TA';; +125°C

±3
±10
.' ±3.0·

±10

ppm
ppm
ppm
ppm

of FSR/oC
of FSR/oC
of FSR/oC
of FSR/oC

%ofFSR
±D.l0

±D.OS

±0.10
±D.20

±D.05

±0.25
±O.10

±D.05

±O.10
±D.20

±10

±20

ppmJOC
ppmJOC

±10

±20

ppm/'OC

±D.25

,

-25°C to +85°C
-55°C t6 +12SOC
-25°C to +85°C
.-55°C to +125°C

Gain adjustment range

±l:.
±3

±0.05

y

Bipolar

I

±D.2

-55°CE:;; TA ~ +125°C

!J

Gain temperature sensitivity
Unipolar

±D.006

TA = +25°C
-25°C';; TA .;; +85°C
-55°C ';;·TA';; +125"C
TA = +25°C
-25°C';; TA .;; +85°C
-55°C';;TA';;+125°C

Offset temperature sensitivity

Bipolar

V
V
V
V

TA = +25°C
-25°C';; TA .;; +85°C
-55°C';; TA';; +125°C .
TA = +25°C
-25°C';; TA .;; +85°C
-55°C';; TA';; +125°C
TA- +25°C
-25°C';; TA .;; +85°C
-55°C';; TA';; +125°C
TA +25OC
-25°C';; TA';; +85°C
-55°C';;TA';;+125OC

~rror

Bits·

5.5
5.5
0.&
0.4

Y

Bipolar

UNITS ..21

2.0
2.4
0
0

TA - +25OC
-25°C .. TA .. +85°C
-55°C .. TA';; +125°C
TA = +25°C
-25°C';; TA .. +85°C
-55°C'; TA" +125°C

Bipolar

Total ,error. trimmed §I
Uni.polar

LIMITS
DAC&7-CBI-VlMIL .'
DAC87-CBI-VlB .
OAC&7U-CBI-VIB
DAC87U-CBI-V
DAC&7-CBI-V
.MIN
MAX
TYP
MIN
TYP
MAX
12
12 .' I
I
I
I

±l0
+10
±D.2

±D.3

10

20

±20
±20

±60

%of FSR
%ofFSR
%ofFSR
%ofFSR
%ofFSR
%ofFSR

oomJOC
%ofFSR

DYNAMIC CHARACTERISTICS
Slew rate
Settling time

~Vo

-2OV to ±II2LSB
~Vo = IOV to ±1I2LSB
~Vo = lLSB to +1I2LSB

5
3
1.5

V/~ec

..

7

6
3

"sec

ANALOG OUTPUT
Output voltage range §/'
Output current IN
Output resistance, DC
Output short circuit current

..

±10
±5
0.05
TA = +25°C

±5

11-28

0.2
±40

~sec

"sec

.

V
mA

n
mA

T ABLE I. Electrical Performance Characteristics (cont).
LIMITS
DACB7-CBI-VlMIL
DACB7-CBI-V/B
DACB7-CBI-V
CHARACTERISTICS

CONDITIONS

l/

.1

MIN

TYP

.1

MAX

DACB7U-CBI-V/B
DACB7U-CBI-V
MIN

~

TYP ~

MAX

±S

±10
±30

UNITS

Y

INTERNAL REFERENCE
Internal reference voltage ,VR
Internal reference temperature sensitivity

±6.0
-25°C to +BSoC
-55°C to +12SoC
for specified VR

Output current from internal reference

±6.3

±B.6

±5

±10
200

V
ppm of VR/oC
ppm of VRJOC
"A

POWER SUPPLY
Power supply range
+Vee
-Vee
Voo

+14.0
-14.0
+4.75

+15
-15
+5

+16.0
-16.0
+15.5

V
V
V

±Vec = ISV ±O.SV
Voo = 5V ±0.2SV

±O.002
±O.OOI

±O.004
±O.002

% of FSRI%Vde
% of FSR/%Voo

TA = +25°C

±20

±30
±30
25
25

mA
mA
mA
mA

+125
+150

°C
°C

Power supply sensitivity

±Vcc
Voo
Power supply current (quieSc8t:ltl

±Vcc

·55°C E;; TA ~ +125°C
TA = +25°C
-55°C <;; TA <;; +125°C

Voo

20

TEMPERATURE RANGE
Operating
Storage

-55
-65

'Specification same as DACB7-CBI-V
NOTES:
'1J±Vec = 15V, Voo =SV,-SsoC<;;TA<;;+12SoC, unless otherwise specified.
Y FSR = Full Scale Range (Example: The FSR is 20V for ±IOV range, IOV
for±SV range, and IOV forOto+IOV range. I LSB= Least Significant Bit.
~ Total error includes all errors at any fixed power supply voltage within
the recommended supply voltage range, including the internal
reference. linearity error. offset error, and gain error.
~ Offset and gain externally trimmed to zero error at TA = +2SoC.
§I Monotonicity is assured by testing differential linearity to ±lLS8
maximum.

§J Externally adjustable to zero.

!J The reference error is Included.
.§! The offset error is specified separately and is not included herein.
~

The output voltage range is determined by external conditions (see
Table Vil.

!!¥ Limit is assured by testing output resistance where RLOAO = 2kO.

TABLE II. Electrical Test Requirements
{The individual tests within the subgroups appear in Table III,

MODELS

DAC87-CBI-VlMIL ,

MIL-STO-883 te.t requlremento (hybrid cl...)

Interim electrical parameters [ preburn~in I I method 50081
Final electrical test parameters I method 5008 I

Group A test requirements I method sa081
Group C end point electrical parameters I method 5008)

Additional electrical subgroups performed prior to Group C inspections

DAC87-CBI-V/B
DAC87U-CBI-VlB
DAC87-C81-V
DACB7U-CBI-V
~ubgroups"1 see able Iii,

1

1

1

1',2,3,4

1,2,3

1,2U,3U

1,2,3,4

--

--

Table IV delt.
limits and limits

--

--

2C, 3C, 5, 6

--

--

PDA applies to subgroup 1 I see 4.3.d I

3.5 Marking. Marking is in accordance with M IL-M-38510. The following marking IS placed on each microcircuit as a
minimum.
a. Index point
b. Part number (see paragraph 1.2)
c. Inspection lot identification code .11
d. Manufacturer's identification (lEi"")
e, Manufactuer's designating symbol (CEBS)
f. Country of origin (U.S.A.)
3:6 Workmanship. These microcircuits are manufactured. processed, and tested in a careful and workmanlike manner.
Workmanship is in accordance with good engineering practices. workmanship instructions. inspection and test
procedures, and trainings. prepared. in fulfillment of Burr-Brown's product assurance program.
3.6.1 Rework provisions. Rework provisions. including rebonding •. for the MIL Hi-Rei product designation are in
accordance with MIL-M-38510.
!.

A 4-digit date code, indicating year and week of seal, and a 4- or 5-digit lot,identifier is marked on each l:Init.

11-29

3.7 Traceability. Traceability isin accordance with MIL-M~385JO. Each microcircuit is traceable to the production lot
and to the component vendor's component lot. Reworked or ~paired microcircuits maintain traceability.
3.8 Productand proceSs change. Burr.Orown·wil(not implement a'ny major change to the design. materials. construction.'
configuration, or manufacturmg· process which may affect the performance. lJuality.reliability or interchangeability of
the microcircuit without full or partial relJualification.
3.9 Screening; Screening, for I MIL andl B Hi-Rei product designations, is in accordance with MIL-STD-883, method
5008, Class B, exCept as modified in paragraph 4.3 herein.
,Screening for the standard model, (none) Hi-Rei product designation, includes Burr-Brown QC4118 internal visual
inspection and. stabilization bake, fine leak, gross leak, bum-in (72 hours performed preseal), temperature cyple,
constant acceleration (condition D), and external visual inspection per MIL-STD-883, method 5008, Class B.
For the./ MIL Hi-ReI product designation. all microcircuits will have passed the screening relJuirements prior to
lJualification or quality conformance inspection.
3.10 Qualification. Qualification IS not required. See paragraph 4.2 herein.
3.11 Quality conformance inspection. Quality conformance inspection. for the MIL Hi-ReI product designation. is in
accordance with MIL-M-38510. except as modified in paragraph 4.4 hetein. The microcircuit inspection lot will have
passed lJuality conformance inspection prior to microcircuit delivery.
TABLE III. Group A Inspection.
LIMITS
DAC87~BI-V/MIL

SUBGROUP
I
TA =+?5°C

PARAMETERS
Offset error. bipolar
Gain error, bipolar .
Linearity error. bipolar

Diflerenliallinearity err~r, bipolar
Total error. untrimmed, bipolar
Total error, trimmed. bipolar

Internal reference voltage
Input voltage

4
4

4

4
4
§/
4

-

CONDITIONS JJ

¥

+6.0

4
4
4

Output resistance

4

Ro=

Output short Circuit current
Power supply sensitivity

-4

Power sl,Ipply current

-

Total error, untrimmed, unipolar

4

Offset error. bipolar {VOE'
Gain error, bipolar IGE I
Offset temperature sensitivity.
Bipolar

4
4

±10V range ,id.al value = -IO.OOOV,
±10V range lideal value" +9.9951 17V,

-

'.lVOE
±10V range'll

'Glin temperature sensitl~ity,
Bipolar

-

.lGE
±10V range, ~ =

Llnearlly error, bipolar

4

Dlfleranliallinearity error, bipolar
Total error, untrimmed, bipolar

4
4

3

3
4
4

-1,6

IVo no loadt'.. /Vo2kll load I *
5mA

R'oad = 10, Vo = +FS and -FS
±10V range, V;';, +FS.-.lVee = +0.5V
and -O.5V
±10V range, Vo = +FS • .l Voo = +O.25V
and -O.25V
±10V range
±IOVrange
o to +IOV range I ideal value = O.OOV,
o to +IOV range lideal
value '<+9.997559V
o to +tOY range

Offset adjustment range
Gain adjustment range
Offset error, unipolar
Gain error, unipolar

MIN

±IOV range' ideal value = ,IO.OOOV,
±IOV range lideal value = +9.995117V'1I
±IOV range
~
For + bit errors
For - bit errors
±IOV range ~ ~

Logic "I". all inputs. Yin = 5.0VDC to
2.0VDC, measure .lVo
'Loglc "0", all Inputs. Yin = OVDC to
O.8VDC, measure .lVo
Logic "I", each input, Yin = +2.4VDC
Logic "0", each input, Y'n = +O.4VDC
No load+Vee
No load-Vee
No load Voo

Input current

2
TA=+125°C

DAC87-CBI-v/B
DAC87,CBI-V '

TEST
CIRCUIT,
FIGURE

I

±10V range, Wjj
For + bit error.
For - bit errors
±10V range jj21
±10Vrange

'Vo = +full scale

11-30

VOE'2t1 • VOE25
lOOOC
GEI25 - GE25
l000C

±IO
±20

mV
mV

+2.44
'2.44
±3.66
±20

+2.44
'2.44
±3.88
±20

mV
mV
mV
mV

--

+8.6

,-

+6.6

V

±4

±4.8

mV

±4
+40
0
30
30
25

±4.8
+40
0
30
30
25

mV
I'A
mA
mA
mA
mA

+6.0

'1.6

0.2

II

±40

mA

.±2.6

±2.6

mV

±2.0

±2.0

±40

±5

±5

±/i

mV
mV
mV
mV

±10
±10

±IO
±10

mV
mV

±30
±40

y

UNITS

±to
±20

0.2
±5

'11

=

MAX

DAC87U-CBI-v/B
DAC87U-CBI-V
MIN
MAX

±30
±40

±20
±50

mV
mV

±O.20

mY/DC

to.40

mV/oC

.+2.44
±2.44
±4.88
±60

mV
mV
mV
mV

TABLE III. Group A Inspection (cont).
LIMITS

SUBGROUP

PARAMETERS

3

= -55°C

--=.----

4
4
4

No load +Vcc
No load -Vee
No load VOD

Offset error, bipolar VOE '
Gain error, bipolar, GE

4
4

t10V range ideal value:.:: -lO.OOOV
±10V range' ideal
value o. +9.995117V 11

Offset temperature sensitiVIty.
Bipolar

-

±lOV range

Gain temperature sensitivity,
Bipolar

-

-<:10V range,

linearity error, bipolar

4

Differential linearity error. bipolar
Total error, untrimmed, bipolar
Total error, trimmed, bipolar
Internal reference voltage
fnternat reference
temperature sensitivity

4
4
4

±10V range. '# Y
For + bit errors
For - bit errors
,10V range ~ '21
±10V range
:!:10V range !.J

-

Offset error, bipolar
Gain error, bipolar

4
4

I

'60
.iVA
.iT

3C

T.

= -25°C

3U

VAllS - VR2~

±63

.iVOE
.iT
,,\VGE

-:rr

6O"C

=

GE8S - GE25

--sooc

±lOV range Kieal value
:!::10V range Ideal
value ~~ +9.995117V

+lOV range. - - =

Linearity error, bIpolar

4

--.n

-10000V

11

.lVOE

V0E25 - VOE-55
BOoC

.iGE

Ge25 - Ge-55

..IT

80°C

± 10V range:y jJ
For +- bit errors
For - bit errors
± 10V range ~.2/
±lOV range
±10V range 7J
'60
.iVR

VR25 - VR 55

±10V range (ideal value:= -lO.aOeVI
±:lOV range I ideal
value:-:: +9.995117V

-

+

~VOE

:t10V range.

:.GE
--sr
= GE'S - Ge-25
50°C

Differentia! linearity error, bipolar
Total error, untrimmed bipolar
Total error, trimmed bipolar
Internal reference voltage
Internal reference
temperature sensItivIty

4
4
4
4

mV,'C

+244
-244
-488
. 50
-30
'66

mV
mV
mV
mV
mV
V

p.V/oC

-20

mV

' 50

m'.

'020

mV/oC

-040

mV/oC

,< 44
-244
. 488
'60
'40
'66

mV
mV
mV
mV
mV
V

p.V/oC

30
25

_10Vrange,~=

-20

VOE2S - Voe-,s
50°C

mV

'40

mV

'020

mV 

o. 1
0.06
0.04

15~

0.02

ffi

0.0 1

O::w

~

-'

L

~ ~ 0.006

... () 0.004

~~

;f'.

0.002
0.001

~

±15V Supplies

10

100

lk

"'~,.

"

~

oQ'c
V

10k

lOOk

POWER SUPPlY RIPPlE FREQUENCY (Hz)

FIGURE 9. Typical Power Supply Sensitivity vs Power Supply Ripple.

"'-

7.3 External offset and gain error adjustment. The untrimmed accuracy of the DAC87/ MIL Series is very good and is
adequate for many applications. However, when the initial offset and gain errors are greater than what can be allowed
in the application, the circuits shown in Figure 3 may be connected and the offset and gain errors may be adjusted to
zero.
7.3.1 Offset adjustment. Apply the digital input code, 1111 1111 1111, which should produce zero volts output for the
unipolar ranges, or minus full scale for the bipolar ranges. Adjust the offset potentiometer until the output, for the
output range ~ing used, is exactly as depicted in Table V.
7.3.2 Gain adjustment. Apply the digital input code, 0000 0000 0000, which should produce positive full scale. Adjust
the gain potentiometer until the output, for the output range being used, is exactly as depicted in Table V.

11-47

BURR-BROWN®

IElElI

DAC870/MIL SERIES
MODEL NUMBERS:
DAC870VlMIL
DAC870U/883B
DAC870VLlMIL
DAC870UL/883B
DAC870U
DAC870V/883B
DAC870VLl883B
DAC870UL
D.AC870V
REVISION N9NE
DAC87OVL·
OCTOBER, 1983

12-Bit ~55° C to- +125° C Military
DIGITAL-TO-ANALOG CONVERTER
FEATURES
• HI·~EL MANUFACTURE
• COMPLETELY SPECIFI.EO. -55° Cto +125° C
• ACCURATE
±1I2LSB max Linearity. over temperature
±25ppm/o Cmax Gain Drift
±O.3% Total Error. over temperature
Monotonic. over temperature

.MIL·STD·883 SCREENING
• DACB7 PIN·COMPATIBLE
• COMPLETE-INTERNAL REFERENCE AND OUTPUT
AMPLIFIER
..

DESCRIPTION
The DAC870 Series is a high performance, l2-bit,
TTL-:compaiible, -55° C to + 125° C digital-to-analog
converte~ in either a 24-pin ceramic side-brazed
package or a 28-terminalltiadless chip carrier, and it
is· manufactured on a separate Hi-ReI production
line. It is pin-compatible with DAC87 converters
and has five user-selected output ranges. Each DAC
is a complete device with an internal output amplifier
and an ultra-stable reference.
The DAC870 Series is designed for high accuracy,
wide temperature applications. The total accuracy
without external trim adjustments is ±0.25% of
FSR, decreasing to only ±0.4% of FSR over -55° C
to + 125° C. With external offset and gain trim
adjustments at +25° C, the total accuracy is less than
±O.3% of FSR ovet -'-SsoC to +I25°C. Gain ~rift is
less than 25ppm/oC. Linearity error, contributed
mostly by the internal current switches and resistive
ladder, is reduced by laser trimming to less than
±1/2LSB over temperature. Differential linearity is
less than ±ILSB over temperature, thereby guaranteeing monotonicity from -55°C to +125°C.

There are two electrical performance grades and
three product assurance levels, allowing a wide
application/budget choice. The DAC870V model/
grade features excellent performance from -55°C to
+125°C and findS wide military, aerospace, and
industrial applications. The DAC870U model/ grade
features excellent performance from -25°C to
+85°C, and guarantees specifications fro.m -55°C
to +125°C. Applications include test equipment,
shipboard, ground support, anti shirt-sleeve environ- .
ments whete operation is between -25° C and +85° C
but .full temperature operation must be assured. .
The three product assurance levels available are:
standard; /883B (100% screened per MIL-STD-883
method 5008, class B); and / MIL (100% screened,
plus PDA =10%, plus Groups A and B testing on
each inspection lot, plus Groups C and D performed
initially, periodically, and when specified on the
customer's purchase order). See paragraph 1.2.2 for
more details. Each device is manufactured in a HiReI environment with clean room conditions which
assures "built-in" quality.

Internalional Alrportlnduslrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tei. (6021746·1111· Twx: 910-952·1111 . Cable: BBRCORp· Telex: 66·6491

11-48

DETAILED SPECIFICATION
MICROCIRCUITS, LINEAR
DIGITAL-TO-ANALOG CONVERTER
HYBRID, SILICON
I. SCOPE
1.1 ScoJie. This specification covers the detail requirements for a 12-bit voltage output digital-to-analog converter

hybrid microcircuit.
1.2 Part Number. The complete part number is as shown below.
DAC870
V

=r

Basic model
number

lGrade
(see 1.2.1)

L

~

Package
(see 1.2.3)

/MIL

T
Hi-Rei product
designator (see 1.2.2)

1.2.1 Device typ~. The device is a single, 12-bit, voltage output digital-to-analog converter. The input coding is
complementary binary. The device may be externally pin-connected for either Complementary Straight Binary (CSB)
or Complementary Offset Binary (COB) coding (see Tables V and VI).
There are two electrical performance grades. The V grade designation is the premium grade and features specifications
and tests from -55°C to +125°C. The U grade designation features specifications and tests from -25°C to +85°C and
operation from -55°C to + I 2 5 ° C . '
Electrical specifications are shown in Table I; electrical tests are shown in Tables II and III.
1.2.2 Device class. The Hi-ReI product designator portion of the part number distinguishes the product assurance
levels available as follows:
Hi-Rei product
designator
Requirements
Standard model plus 100% MIL-STD-883 class B screening, with 10% PDA, plus quality
/MIL
conformance inspection (QCI) consisting of Groups A and B performed on each inspection
lot, plus Groups C and D performed initially and periodically thereafter.
Standard model, plus 100% MIL-STD-883 Class B screening.
/883B
(NONE)
Standard model including 100% electrical testing.
1.2.3 Case outline. Two case outlines are available.
1.2.3.1 24-pin ceramic side-brazed (DIP). No package identifier is utilized to specify the 24-pin ceramic side-brazed
package, which is MIL-M-38510, Appendix C, designator D-3, configuration 3. Figure I depicts the case outline for this
package type.
1.2.3.2 28-terminalleadless chip' carrier (LCC). The "L" package identifier is utilized to specify the 28-terminal square
lead less chip carrier package, which is MIL-M-38510, Appendix C, designator C-4. Figure I depicts the case outline for
this configuration.
1.2.4 Absolute maximum rating~.
Supply voltage, Vee
±20VDC
Supply voltage, Voo
OVDC to +18VDC
Data input voltage
-IVDC to +7VDC
Output short circuit duration
Continuous to ground
Storage temperature range
-65°C to +165°C
Lead temperature (soldering, IOsec)
+300°C
Junction temperature
1.2.5 Recommended operating conditions.
Supply voltage range
Vee: ±14.5VDC to ±15.5VDC
Voo: ±4.75VDC to +5.25VDC
Ambient temperature range
-55°C to +I25°C
1.2.6 Power and thermal characteristics.
Maximum allowable
Maximum
Case outline
power dissipation
OJ-C,
Packag~
24-lead DIP
Figure I
850mW
48°C/W
28-terminal LCC
Figure I
950mW
42°C/W

11-49

2. APPLICABLE DOCUMENTS
2.1 The following documents form a part ofthiiisp~cificationtothe extent specified herein.
SPECIFICATION
MILITARY
MIL-M-38SI0 " Microcircuits, General Specification for.
STANDARD
,MILITARY
MIL-STD-883 - Test Methods and Procedures for Micr.ocircuits.
3. REQUIREMENTS
3.1 General. Burr-Brown uses production and test facilities and a quality and reliability assurance program adequate to
assure successful compliance with this specification.
3.1.1 Detail specifications. The individual item requirements are specified' herein. In the event of conflicting
requi~the order of precedence will be the purchase order, this specification, and then the reference documents.
3.1.2 Country of manufacture~ These microcircuits are manufactured, assembled, and tested 'within the United States
of America.'
3.2 ~gn, construction, and PEysical dimensions.
3.2.1 Package, metals. and other materials. The packages, metal surfaces, and other materials are in accordance with
MIL-M-38SI0.'
.
.
NOTE

[](][]
L

'A

Lead5 In true PQlmon wllhm ,010"
t.25rnm)f'I GIl MMC af seatlr'lg plane

-+---

-,dbJ

OIM

I

, INCHES
MIN
MAX

MilLIMETERS

MIN

MAX

A

1.18$

1.215

30.10

30.86

C

.105
.015
.035

.170
.021
,06.

2.67
0.38

0.53

0.,9

1.52

0
G

.lOO·BASIC

.03.
.•08
.120

...
N

0.76

17.

.012

0.20
3.05

8,10

.240

A
B
C

0.30

10°

F
G

1.52

H

15.24 BASIC

1.°

.08.

OIM

2.54 BASIC

.070

.600 BASIC

.025

4.32

0.64

(a) 24-pin side braze; package 10: (none)

INCHES
MIN
MAX

MILLlMETFRS

MIN

MAX

.442

0458 11.23 11.83
A58
11.23 11.83
.442
.100
1.83
~084
2.64
0.71
.022
.028
0.68
, 1.27 BASIC
.060 BASIC
.008R TYP.
O.20R TYP.

(b) 28-terminal LCC; package 10: "L"

FIGURE I. Case Outlines.
3.2.2 Design documentation. The design documentation is in accordance with MIL-M-38SIO.
3.2.3 Inter~al conductors and internal lead wires. The internal conductors and' internal: lead wires ,are in accordance
with MIL-M-38SIO.
3.2.4 Lead material and finish. The lead material and finish is in accorqance with MIL-M-38SIO and is solderable per
MIL-STD-883, method 2003.
3.2.5 Die thickness. The die thickness is in accordance with MIL-M-38SIO.

11-50

3.2.6 Physical dimensions. The physical dimensions are in accordance with paragraph 1.2.3 herein.
3.2.7 Circuit diagram and terminal connections. The circuit diagram and terminal connections for the ceramic sidebrazed package are shown in Figure 2 and the circuit diagram and terminal connections for the leadless chip carrier
package are shown in Figure 3.
3.2.8 Glassivation. The microcircuit dice are glassivated.
3.3 Electrical l'erformance characteristics. The electrical performance characteristics are specified in Table I and apply
over the full operating ambient temperature range of -55°C to +125°C unless otherwise specified.
3.3.1 Offset and gain error adjustment. The DAC is capable of being externally adjusted to zero offset error and to zero
gain error using the circuits in Figure 4. See applications information paragraph 7.3.
3.3.2 !!!l'ut coding. The input coding is complementary binary. The digital input code to yield the corresponding
output voltage for the various output ranges is specified in Table V.
3.3.3 Output rang~. The output range is specified in Table VI when externally connected as shown therein,
3.4 Electrical test requirements. Electrical test requirements are shown in Table II. The subgroups of Table III and
limits of Table IV, which constitute the minimum electrical test requirements for screening, qualification, and quality
conformance, are specified in Table II.

8.3V
REFERENCE
OUTPUT

IMSB) BIT I
BIT!

6AIN ADJUST

BIT 3

+Vcc

BIT4

COMMON

BIT5

SUMMING
JUNCTION

BIT6

20V RANGE

BIT7

IOV RANGE

BITB

BIPOLAR OFFSET

BIT9

REFERENCE INPUT

BIT 10

OUTPUT

BIT 11

-Vee

CI

VOD

CO
c.:I
C
CI

-I

ILSBI BIT 12

FIGURE 2. Terminal Connections (24-pin Ceramic Side Braze).

11-51

:i
........
"'""

6.3V
NC

BIT3

REFERENCE GAIN
OUTPUT ADJUST

+Vce

28
BI14

COMMON

BIT 5

SUMMING
JUNCTION

BI16

20V RANGE

NC

NC

8117

10V RANGE
BIPOLAR
OFFSET
REFERENCE
INPUT

16
BITIO

BITII

BITI~

LOGU:

-Vee

VOUT

SUPPLY.
Voo

FIGURE 3. Terminal Connections

+15VDC

+15VoC

OFFSET
ADJUSTMENT

~

IOknfo
IlIOkri

SUMMING
JUNCTION

OFFSET
AOJUSTMENT

11
Jj
)-..Jo.J"I'...____-llnIID

PARAMETERS

Offset error, bipolar
TA::;: +25°C Gain error, bipolar
Linearity error, bipolar
1

Differential linearity error, bipolar
Total error, untrimmed, bipolar
Total error, trimmed, bipolar
Internal reference voltage
Input vOltage,!J

DAC870
'V"Grade

TEST
CIRCUIT
FIGURE
5
5
5

5
5

CONDITIONS.!>

MIN

±10V range (ideal value; -10.000V)
±10V range (ideal value; +9.995117V).i'
±10V rangeJi ~
For + bit errors
For - bjt errors
±10V range..!'!!

+6.23

Gain adjustment range
Offset error, unipolar
Gain error, unipolar

5

Total error, untrimmed, unipolar

5
5
5

±10V range (ideal value =-10.000V)
±10V range (ideal value; +9,995117V).i'

-

±10V range.

Gain temperature sensitivity.
Bipolar

-

±10V range.

Linearity error, bipolar

5

Differential linearity erro.r, b!polar
Total error, untrimmed, bipolar
Total error, trimmed, bipolar
Internal reference voltage
Internal reference
tempe~ature sensitivity

5

±10V range,l1 ~
For + bit errors
For - bit errors
±10V range~.li
±10V range
±10V range.!!

-

Power supply current

-

5
5
5

Output resistance

5

Output short Circuit CLJrrent
Power SLJpply sensitivity

-5

Offset error, bipolar (Voe)
T.; +125·C Gain error, bipolar (Ge)
Offset temperature sensitivity,
Bipolar

4
5

5
5
5

-

--b.VOE

±5

Voe1as - V0Ea5
100·C

GE125-

GE25

;

t.T

100·C

t.V.

VR12S -

VA25

;

t.T

11-55

100·C

UNITS

+2.44
-2.44
±3.66
±50

mV
mV
mV
mV

+6,37

-

V

±4

'±4.8

mV

±4
+40
0
12
25
10

±4,8

mV
pA
mA
mA
mA
mA

0,2

0

±40

mA

±2,6

mV

±2,0
±10

mV
mV
mV

±15
±25

mV
mV

±30

±SO

mV
mV

±O.30

mVrC

±O,SO

mVrC

+2.44
-2,44
±4.88
±60
+6,37

mV
mV
mV
mV
mV
V

±157

pVl·C

±80
+6.23

MAX'

mV
mV

±30

;

t.T

t.G.

-1.6

.MIN

±20
±30

5

-

Logic ",", aU inputs, VIn ::;: 5.0VDC to
2:0VDC. measure INa
Logic "0", all inputs. V1n ::;: OVOC-to
O.aVDC. measure 6.Vo
Logic "1", each input, Yin = +2.4VDC
Logic "0". each input. V," ; +0,4VDC
No load +Vcc
No load -Vee
No load Voo
(Va no load) - (Vo 2kO load)'
Ao· ;
5mA
A..... ; 10. Vo ; +FS and -FS
±10V range. Vo; +FS, t.Vcc ; +0.5V
and -0.5V
±10V range, Vo = +FS, tNDD:::= +O.25V
and -0,25V
±10V range
o to +10V range (ideal value; O.OOV)
o 10 +10V range (ideal
value; +9,997559V).!I
o to +10V range

Input current

MAX.

DAC870

"U"Grade

TABLE III, Group A Inspection (cont),

SUBGROUP

PARAMETERS

.

TEST
CIRCUIT
FIGURE

LIMITS
DAC870
"v.. G.....

CONDITIONS.Y

MIN

PoWer supply current
2e
T. = +125°e

5
5
5

NO load +Vcc
NO load -Vee
No load Voo

Offaat error, bipolar (Voo)
2U
T.=+65°e Gain error, bipolar (Ge)
Offset temperalure sensitivity,
Bipolar

5
5

:tl0V range (Ideal value =-10.000V)
±10V range (ideal value = +9.995117V).!i

-

'l±10V range,

Gain temperature sensitivitY.
Bipolar
Linearity error, bipolar

MAX

DAC870
"U·G ......
MIN

IJ.Voe
'"'AT"

=

VOE80 - V0E25
60°C

Geao -

IJ.VG.

-

±10V range,

5

±10V range •.lf .$

"t:T =

Offsel error, bipolar
3
T.= -55°C Gain error, bipolar
Offset temperature sensitivity.
Bipolar

3e
T.=-25°e

5.
5
5
5

,

GEe

60°C

-

For - bit errors
±10V range.!'.!!
±10V range
±10V range Zl
+6.23
IJ.V.

-IJ.T

=

VR8& - VR25
---60°C

5
5

±10V range (ideal value =-10.000V)
±10V range (ideal value = +9.995117V).!i

-

±10V range,

Gain temperature sensitivity,
Bipolar

-

±10V range,

Linearity error, bipolar

5

±10V range, Jj ~

Differential linearity error, bipolar
Total error, untrimmed, bipolar
Total error, trimmed, bipolar
Internal reference Yoltage
In~ernal reference
temperature sensit,ivity

5
5
5
5

Power supply current

3U
Offsel error, bipolar
T.= -55°C Gain error, bipolar
Offset temperature sensitivity,
Bipolar
Gain temperature sensitivity;
Bipolar
Linearity error, bipolar

Differential linearity, error, bipolar
Total error, untrimmed, bipolar
Total error, trimmed, bipolar
Internal reference voltage"
Internal reference
temperature sensitivity

-

-6VoE
IJ.T

IJ.G.
IJ.T

=

VCle215 -

VOE-56

60°C

GE2S -

=

Ge-515

80°C

For + bit"errors
For - bit errors
±10V range.!!.!!
±10V range
±10V range Zl
IJ.V.
-IJ.T

=

6Qoe

5
5
5

No load +Vee
No load -Vee
\\,0 load Veo

5
5

±10V range (ideal value =-10.000V)
±10V range (ideal value = +9.995117V)!'

-

±10V range,

-

±10V range,

5

±10V range. 3J $

5

For + bil errors
For - bit errors
±10V range.!!.!1
±10Y.range
±10V range Zl

5
5
5

-

IJ.VQE
-IJ.T

=

--

=

IJ.G.
IJ.T

±0.40

mV/oC

+2.44
-2.44
±4.66
±50
±30
+6.37

mV
mV
mV
mV
mV
V

±126

pVloe

mVloe

±0.50

mVloe

mV
mV
mV
mV
mV
V

±157

"V/oe

12
25
10

mA
mA
mA

50°C

IJ.T

50°C

±30
±40

mV
mV

±0.30

mVre

±O.40

mV/oe

+2.44
±4.66
±50
±30
+6.37

mV
mV
mV
mV
mV
V

±126

pV/oe

-2.44

+6.23

VA26 - VA-26

6

To ±1/2LSB, IJ.Vo = 20V
IJ.Vo = 2OV, 10% 10 90%

10

Settling Time
5
T.= +125°e Slew Rate

6
6

To ±1/2LSB, IJ.Vo = 20V
IJ.Vo = 20V, 10% to 90%

10

Settling Time
6
T.= -55°C. Slew Rale

6

T 6 ±1I2LSB, IJ.Vo '" 20V
IJ.Vo = 2OV; 10% to 90%

10

11-56

mV/oC

±0.30

GE25 - Ge-25

6

6

±D.15

mV
mV

VOE$ - VOE-2S

Settling Time
Slew Rale

4
T.= +25°e

mV
mV

±30
±50

50°C

IJ.VR

-- '"

±30
±40

+2.44
-2.44
±4.66
±60
±60
+6.23 ' +6.37

VR25 - VA-55

U~ITS

mA
mA
mA

For + bit errors
Differential linearity error, bipolar
Total error, untrimmed, bipolar
Total error, trimmed, bipolar
Internal reference voltage
Internal reference
temperature sensitivity

MAX

12
25
10

7
7

psec
V/psee

psec
V/paee

7

.-

psec
Vlpsec

NOTES:
jJ ±Vcc = 15VDC, VDD = 5VDC, Logic 1 = 4V, Logic 0 = 0.2V, no load, unless olherwlse specified.

lJ Offset error corrected to zero.
~

The individual bit errors that are positive are switched on and compared to 1I2LSB. The individual bit errors that are negative are switched on and compared to
1/2LSB. This guarantees ±1/2LSB maximum linearity error.
~ Offset error and gain error correction factors for the Device Under Test (OUT). if any, are applied to the OUT output voltage before comparing the OUT output
voltage to the ideal output voltage. This is the basis for linearity error and differential linearity error relative to a straight line through the end points of the transfer
function.
~ Differential linearity error is tested at all combinations of the four most significant bits.
§J Total error, trimmed, (bipolar) is the same as linearity error, bipolar.
11 Offset and gain errors adjusted to zero at TA := +25°,C.

TABLE IV. Group C, End Point Electrical Paramters.
(TA= +2SoC, ±Vcc= lSVDC, VDD= +SVDC)
Limit

Della

±0.25% of FSR
±0.5LSB
±0.75LSB
Yes
±0.10% of FSR
±0.15% of FSR

-.

Tell
Total error, untrimmed, bipolar
lineari.t~·_ error, bipolar
Differential linearity error, bipolar
Monotonicity
Offset error, bipolar
Gain error, bipolar

*OeltB limits to be finalized upon completion of qualification.

TABLE V. Ideal Output Voltage vs Digital Input Code.
Digital Input Code\Complemenlary 12-BII BINl'l)
Oulpul Range

111111111111

011111111111

001100000110110

-2.5V Ie> +2.5V
-5V 10 +5V ,
-10V 10 +10V
010 +5V
010 +10V

-2.500V
-5.000V
-10.000V
0
0

0
0
0
+2.500V
+5.000V

+2.498779V
+4.997559V
+9.995117V
+4,998779V
+9.997559V

NOTES:
1. One LSB = 1.2207mV for a 5-voll full scale range. One LSB =2.4414mV
for a 10-voll full scale range. One LSB = 4.8828mV for a 20-volt full scale
range.
2. Digital input codes are shown with the MSB listed first.

TABLE VI. Output Range Selection.
24-pln Side Braze Package
Output Range
-2.5V 10 +2.5V
-5V 10+5V
-10Vlo +10V
010 +5V
010 +10V

Required External Pin Connections
151018
151018
151019
151018
151018

171020
171020
17 10 20
171021
171021

191020
19NC
191015
191020
19NC

161024
161024
161024
161024
161024

28-Termlnal LCC Package
Output Range
-2.5V 10 +2.5V
-SVIO +5V
-10V10 +10V
OIl' +5V
010 +10V

Required Exlamel Pin Connection.
181021
181021
181023
181021
181021

20 to 24
201024
201024
201025
20 10 25

11-57

231024
23NC
231018
231024
23NC

191028
191028
191028
191028
191028

Voo +Vcc
+10Vnc

--<>

r"'"
,,,}"
I
IL./
I

II

____

I

:"

OIGITAL
VOLTMETER

I,,"L../

Vo (SLEW RATE)

'BIT INPUT

FIGURE 6. Slew Rate and Settling Time Test Circuit.

FIGURE S. Test Circuit-Simplified.

4. PRODUCT ASSURANCE PROVISIONS
4.1 Sampling and inspection. Sampling and inspection procedures ar,;: in accordance with MIL-M-38510 and MIL'
STD-883, method 5008, except as modified herein.
4.2 Qualification. Qualification is not required unless specifically required by contract or purchase order. When so
required, qualification will be in accordan~e with the inspection rOQtii)e of MIL-M-38510, paragraph 4.4.2.1. The
inspections to be performed are those specified herein for groups A, B, C and D inspections (see paragraphs 4.4.1, 4.4.2,

.

«~~«4

'-

Burr-Brown has performed and successfully completed qualification inspection as described above. The most recent
'
report is available from Burr-Brown.
4.3 Screening. Screening for the /MIL and /883B Hi-Rei product designations is in accordance with MIL-STD-883,
method 5008, class B, and is conducted on all devices. The following criteria apply:
a. Interim and final test parameters are specified in Table II.
b. Burn-in test (MIL-STD-883, method lOIS) conditions:
(I) Test condition D
(2) Test circuit is Figure 7 herein
(3) TA = +125°C minimum
(4) Test duration is 160 hours minimum

+5V
OV

~ , '12J~

2kn
'--';""I;'"'?"or':"""-'"'?"<

1~lkHz

DUTY CYCLE
'="-50'10
(bl zs.TERMINAL LCC

(a) 24-PIN SIDE BRAZE

FIGURE 7. Test Circuit-Bum-in and Operating Life Test.

11-58,

c. Percent defective allowable (PDA). The PDA, for I MIL product designation only, is 10 percent and includes both
parametric and catastrophic fallures. It is based on failures from group A, subgroup I test, aftercool-down as final
electrical test in accordance with MIL-STD-883, method S008, and with no intervening electriCid measurements. If '
interim electrical parameter tests are performed prior to burn-in, failures resulting from preburn~in screening
failures may be excluded from the PDA. If interim electrical parameter tests are omitted, all screening failures shall
be included in the PDA. The verified failures of group A, subgroup I, after ,burn-in are used to determine the
percent defective for each manufacturing lot, and the lot is accepted or rejected based on the PDA.
d. External visual inspection need not include measurement of case and lead dimensions.
4.4 9uality conformance inspection. Groups A and B inspections of MIL-STD-883, method S008, class B, is
performed on each inspection lot. Groups C and D inspections of MIL-STD-883, method 5008, class B are not required
unless specified by contract or purchase order.
Burr-Brown periodically performs groups C and D inspections of MIL-STD-883, method S008, class B. A report of the
most recent group C and D inspections is available from Burr-Brown.
4.4.1 Group A inspection. Group A inspection consists of the test subgroups and LTPD values shown in MIL-STD883, method 5008, and as specified in Table II herein.
4.4.2 Group B inspection. Group B inspection consists of the test subgroups and LTPD values shown in MIL-STD883, method S008 (class B).
.
4.4.3 Group C inspection. Group C inspection consists of the test subgroups and LTPD values shown in MIL-STD883, method 5008 (class B), and as follows:
a. Operating life test (MIL-STD-883, method lOOS) conditions:
(I) Test condition D
(2) Test circuit is Figure S herein
(3) TA = +12SoC minimum .
(4) Test duration is 1000 hours minimum
b. End point electrical parameters are specified in Table II herein.
4.4.4 Group D inspection. Group D inspection consists of the test subgroups and LTPD values shown in MIL-STD883, method 5008 (class B) and as follows:
a. End point electrical parameters are specified in Table IV herein.
4.4.S Inspection of packag!!!g. Inspection of packaging shall be in accordanc~ with MIL-M-38510.
4.5 Methods of examination and test. Methods of examination and test are specified in the appropriate tables.
Electrical test circuits are as prescribed herein or in the referenced test methods of MIL-STD-883 .
.4.5.1 Voltage and current. All voltage values given, except the input offset voltage (or differential voltage) are
referenced to the external zero reference level of the supply voltage. Currents given are conventional current and
positive when flowing into the referenced terminal.
S. PACKAGING
S.1 Packagi!!g re'luirements. The requirements for packaging shall be in accordance with MIL-M-38SIO.
6. NOTES
6.1 Notes. The notes specified in MIL-M-38SIO are applicable to this specification.
6.2 Intended use. Microcircuits conforming to this specification are intended for use in applications where the use of
screened parts is required or desirable.
6.3 Ordering data. The contract or purchase order should specify the follo\Ving:
a. Complete part number (see paragraph 1.2).
b. Requirement for certificate of compliance, if desired.
6.4 Definitions.
Offset error. Offset error is the difference between the ideal analog output voltage and the actual output voltage, when
ail the input bits are off (digital input code: llli Illl Illl).
Gain error. Gain error is the difference between the ideal analog output voltage span and the output voltage span,
between when all the input bits are off (digital input code: llllllll Illl) and when all the input bits are on (digital input
code: 0000 0000 0000).
Linearity ~rror. Linearity error is the difference between the ideal analog output vol,age and the actual output voltage,
when the offset error and the gain error are equal to zero.

11-59

Differential linearity. Differential linearity is the difference between the ideal (ILSB) analog output voltage change, fot
a l-bit9hange indigital input code and ~he~tualoutput voltage change. A 
.~

_._ .

<
g ±8

10'M0

iii

E
~

~

'"

100
lk
Frequency I Hz I

g 1'Mo

()

c


r!!!!!!!!IIiiii~=----.J
10
100
1000
GainlVNI

6

\

1\

!

6-5

i'-.

o

500

INPUT NOISE VOLTAGE
I/SFREQUENCY 1100SGAINS1000,

600

\
i\......

"

-10

32

8

S.

:: 0

100

WARM-UP DRIFT VS TIME

STEP RESPONSE

1«or-----~----_T~~__,

o

3

'-

6

9

12

Time IMlnutesl

OUTPUT NOISE VS GAIN

30~----'------r--~~

1000

~

:>

§20~-----+------1-----~

i
g
~ 10~-----+------1-+.;;-::-::-t

z
'[
'5

o
100
10
Frequency 1Hz,

1000

oL._...II;;_iilliiiiil!!!!l
1

10

100
GalnlVNI

1000

S. APPLICATION INFORMATION
S.I Description. The IN A25S is a three-ampHfier device which provides all the desirable characteristics of a premium
performance instrumentation amplifier. In addition, it has features not normally found in integrated circuit instrumentation amplifiers. See simpljfied schematics in Figures 2 and 3.
The input section (AI and A2) incorporates high performance, low drift amplifier circuitry. The amplifiers'are connected in the noninverting configuration to provide the high input impedance (101°0) desirable in the instrumentation
amplifier function. The offset. voltage and offset voltage versUs temperature are low due to the monolithic desigit, and
are improved even further by state-of-the-art laser-trimming techniques.
The output section (A3) is connected in a unity-gain difference amplifier configuration. A critical part of this stage is
the matching of the four 10kO resistors whieh provide the difference function. These resistors must be initially well
matched and ~he matching must be maintained over temperature and time in order to retain excellent common-mode
rejection. (The l06dB minimum at 60Hz for gains greater than lOOV / V is a significant improvement compared to most
other integrated circuit instrumentation amplifiers.) .
.All of the internal resistors are compatible: thin-film nichrome formed with the integrated circuit. The critical resistors
are laser~trimmed to provide the desired high gain accuracy and common-mode rejection. Nichrome ensures long-term
stability of trimmed resistors and simuitaneous achievement of excellent TCR and TCR tracking. This provides gain
accuracy and common-mode rejection when the INA258 is operated over wide temperature ranges.
The fourth op-amp (A4) ofthe INA25S adds a great deal of versatility and convenience to the amplifier. Its use allows
easy implementation of active loW-pass filtering, output offsetting, and additioJ!.al gain generation. The pin connections
make the use of this stage optional and the specifications appear separately in the table of Electrical Specifications.
S.2 Using the INA25S. Figure 4 shows the simplest configuration of the INA25S. The gain is set by the external
resistor, Ro,with a gain equation of G = I + (40K/Ro). The reference and TCR of Ro contribute directly to the gain
accuracy and drift.
For gains greater than unity, resistor Ro is connected externally. At high gains, where the value of Ito becomes small,
additional resistance (i.e., relays, sockets) in the Ro circuit will contribute to a gain error. Care should be taken to
minimize this effect.

11-70

TABLE III. Group A Inspection (cont).
LIMITS

SUBGROUP

SYMBOL

MILSTD-883
METHOD or
equivalent

3
T. = -55°C

V~

4001

b.V~/b.T

4001

3U

V~

4001

b.V.. Ib.T

4001

T,,= -25°C

"

EA.

T. = 25·C

VOP
SR
NLJi

4004
Figure 4

INA258WG/MIL,!!
INA258WLlMIL,!!
INA258WG/883B
INA258WLI883B
INA258WG
INA258WL

CONDITIONS
(±VCC:= 15VDC
unless otherwise specified)
A.=l
A. = 1000
A.=l
[V~ (25°C) A. = 1000
[V" (25° C) -

V~

(-55°C)J

+ 80

V~

(-55°C)]

+ 80

A.=l
Av= 1000
A.=l
[V.. (25°C) - V.. (-25°C)J
A.= 1000'
[V,. (25· C) - V.. (-25·C)J

MIN

INA258VG/MIL!I
INA258VLlMILJi
INA258VG/883B
INA258VLl883B
INA258VG
INA258VL

MAX

UNITS

1050
90
10

1450
150
15

5250
450
45

pV
pV
pvrc

1.5

1.0

3.0

pV/oC

1380
135

pV
pV
pvrc

MAX

MIN

MAX

INA258UGI883B
INA258ULl883B
INA258UG
INA258UL
MIN

20

+ 50
1.B

/lV/oc

0.05
0.10
0.10
0.40

%FS
%FS
%FS
%FS
V
V/psec
%
%
%
%

+5

Gain Equation Error Av = 1
A.= 10
Av = 100
Av= 1000
RL=2kO
RL= 2kO
A.=l
A.,=10
A. = 100
Av= 1000

0.05
0.10
0.10
0.40

0.05
0.10
0.10
0.40
±10
0.2

±10
0.2
0.005
0.005
0.007
0.025

NOTES: j j IMIL models available third quarter 1984.
~ Fourth op amp.
~ E1 ;::: OV and E2 Is varied to enable nonlinearity error to be measured by sampling 21 pOints between -10V :$.
deYiati~n from straight line connecting these end points at each gain setting.

±10
0.2
0.005
0.005
0.007
0.025

0.005
0.005
0.007
0.025

EouT S +10V and determining worst case

TABLE IV. Group C, End Point Electrical Parameters.
(TA= +25·C, ±VCC= 15VDC, v ... = OV)
TEST
VIO(A.=l)
VIO (A. = 1(00)
I..

LIMIT
±25Op\I
±5OpV
±20nA

DELTA

.

·Delta limit. to be finalized upon completion 01 qualification.

3.11 Quality conformance inspection. Quality conformance inspection, for the / MIL product designation, is in accordance with MIL-M-38SI0, except as modified in paragraph 4.4 herein. The microcircuit inspection lot will have passed
quality conformance inspection prior to microcircuit delivery.
4. PRODUCT ASSURANCE PROVISIONS
4.1 Sampling and inspection. Sampling and inspection procedures are in accordance with MIL-M-38SIO and MILSTD-883, method SOOS, except as modified herein.
.
4.2 Qualification. Qualification is not required unless specifically required by contract or purchase order. When so
required, qualification will be in accordance with the inspection routine of MIL-M-385IO, 4.4.2.1. The inspections to be
performed are those specified herein for groups A, B, C, and D inspections (see paragraphs 4.4.1, 4.4.2, 4.4.3, and 4.4.4).
Burr-Brown has performed and successfully completed qualification inspection as described above. The most recent
report is available from Burr-Brown.
\ 4.3 Screening. Screening for the / MIL and /883 Hi-ReI product designations is in accordance with MIL-STD-883,
method 5004, class B, and is conducted on all devices. The following criteria apply:
a. Interim and final test parameters are specified in Table II.
b. Burn-in test (MIL-STD-883, method 1015) conditions:
(1) Test condition B
(2) Test circuit is Figure 5 herein
(3) T A = +1250 C minimum
(4) Test duration is 160 hours minimum

11-71

S.3 Basic circuit connection. Thc.bilSic circuit connection fot thtrINA2S8 is shoWn in Figure 4; The output voltagt is a
function of the differential input 'voltage times the gain.
Figure 4 does not include additional internal op amp A4. Power supply bypassing with a I#lF tantalum capacitor or
equivalent is always recommended.
.
In application~\Vhich do not. use the fourth intern~ amplifier, insure the A4'+Vee is not connected to Vee, the A4 +
inputis connected to common imd A4·sense is connected to A4 output.
.
8.4· 1Ypical applications. Many applications of instrumentation amplit'iersJnvolve the amplification of low-level differential SignalS from bridges and transducers such as strain gauges, thermocouples, and RTD's. Some of the important
parameters include common-mode rejection (differential cancellation. of common-mode offset and noise), input impedance, offset voltage and drift, gain accuracy, linearity, and noise. The INA2SS accomplishes all of these with high
'
. .
precision.
Figures 6, 7, andS show some typical applications circuits.
Figure 6 shows how the output stage may be used to provide ,dditional gain. If gains greater than 1000V/ V (10,000 up
to 100,000 and greater) are desired, it is better to place some gain in the output amplifier rather than the input stage, due
to the low values of Ro required (Ro < 400 for [I + 4Ok/ Ro] > 1000). Note, however, that accuracy cali degrade due to
very high amplification of offset, drift, and noise errors.
Output offsetting ("zero suppression" or "zero elevation j may be more easily accomplished with the IN A258 than with
most other Ie instrumentation amplifiers, as shown in Figure 7. The use of the extra internal op amp, A4, means that
CMR of the instrumelit amp is not disturbed, and that a convenient value of variable resistor can be used.
Amplifier A4 also allows active. low-pass filtering to be implemented convenientlywith'a single capacitor. Filtering can
be used for noise reduction or band-limiting of the output signal as shown in Figure S.

+Vee

+Vee

R.

-Vee
°NOTE: A4 Invtlll 1111 IIdpuI III thl IlIIInnnInIIItIn .....IIIIr.
PIli 2 10 pin 16. ThIrIIInIltII llqllllan ,.. four IIIIWi
E, - E. Inllllll III Eo - E,.

°NOTE: A4 Invtlllltll ........ 1II1t111~ • .,IIIIor,
pin 8 '10 pia 19. TIIInfIn ltIIequ..... ,.. four IhIwI
E, - E,lnIIIId III E. - E,.

, (II iNA258 "8".

(blllA258 "LN.

FIGURE 6. Additional Gain From Output Stage.

11-72

+vcc

=

+vcc

R I IIGIIVlnl1lll VII., 1<1l111cn IypllllllYI
EouT = IE, - E.I (1 + la'IIoII + ZV.I •
·IIOTE: A4 IIIVIrII,
Fllllfl ..

I.

EoUl = IE, - E,III + [a/IIoII + ZV.".
·NOTE: A4 1Mi'll... Fllllfl ..

1IIINA258 "(I".

IbIINA258 "L"

R = I ClllVllllIIII nil, 1<1l111cn IyplilllYI

FIGURE 7. Output Offsetting.
+vcc

+vcc

I. = 11I2"c, x 1000Hz
C, In Iarld, UIItI wfth A4

EOUT = IE, - Eol (1 + [a/IIoIlII/[\
"NOTE: A4 IIIVII'II. •• Flaufl 6.

+ 27ff x

f. = .11I2"c, x 100IHz
C. In farld, and willi A4

EouT = (E, - E.I (I + (a'R.II (11(1
·NOTE: A4 InVlI'II. .11 Figufl ..

10' x C.II

(bIINA258 "L".

l'IINA258 "S"

FIGURE 8. Active Low-Pass Filtering.

11-73

+ 2'" x

10' x C,II

BURR-BROWN®

IElElI

OPA10S/MIL SERIES
M9DEL NUMBERS:
OPA105VM/MIL
OPA105VM/883B
OPA105VM
OPA105UM/883B
OPA105UM

OPA105WM/MIL
OPA105WM/883B,
OPA10SWM
REVISION A
MARCH, 1983

FET Input Military
OPERATIONAL AMPLIFIER
FEATURES

APPLICATIONS

• LOW BIAS CURRENT. 1pA. max
• HIGH INPUT IMPEDANCE. 10130

• CURRENT-TO-VOLTAGE CONVERSION

• ULTRA-LOW DRIFT. 2/lV/oC. max

• PRECISION VOLTAGE AMPLIFICATION FOR
HIGH INPUT IMPEDANCE APPLICATIONS

• LONG TERM PRECISION INTEGRATION

• LOW OFFSET VOLTAGE 25D/lV. max
• LOW QUIESCENT CURRENT. 1.5mA. max
• HERMETICALLY SEALED TO·99 PACKAGE

D,ESCRIPTION
The OPAIOS/MIL Series is a low bias current
operational amplifier. Guaranteed low initial offset
voltage (2S0/lV. max) and associated drift versus
temperature (2/lV;"C. max) is achieved by laseradjusting the amplifier during manufacturing: This
feature. and guaranteed low bias current (lpA. max). '
allow greater system accuracy with no external
components.
Quiescent current (I.SmA. max) is unaffected by
changes in ambient temperature or power supply
voltage. Other characteristics of the OPA lOS; MIL
·Series.include internal compensation for unity-gain

stability and rapid th,ermal response for quick stabilization after tUrn-on or temperature changes.
The amplifier is 'free from latch-up and is protected
for continuous output shorts to common. As an
added protection feature. either ofthetrim pins can
be accidentally shorted to a potential greater than the
negative supply voltage without damage.
THe standard pin configuration (741 type) of the
o PAlOS, MIL Series allows the, user drop-in replacement capability. A pin 8 case connection permits
the reduction of noise: and leakage by employing
guarding techniques.

International Airport Indlll1rlal Park· P.O. Box 11400 • Tucson. Arizona 85734 • Tel. 1602) 748·1111 . Twx: 910-952·1111 . Cable: BBRCORP . Telex: 66-6491

11-74

DETAILED SPECIFICATION
MICROCIRCUITS, LINEAR
OPERATIONAL AMPLIFIER
HYBRID, SILICON
I. SCOPE
1.1 Scop~ This specification covers thedetail requirements for a FET input. low bias curreht.low drift. integrated circuit
operational amplifier.
1:2 Part Number. The complete part number is as shown below.

V

OPAIOS

I

Basic model
number

,MIL

M

T

lGrade

.
l
Metal

(see 1.2.1)

package

Hi-Rei product
designator
(see 1.2.2)

1.2.1 Device typ..£: The device is a single operational amplifier. Three electrical performance grades are provided. The W
grade features ±21l V/"C drift (-5S"C to +12S"C). The V grade features ±51lV i"C drift (-5S"C to +12S"C). The U grade
features excellent performance (±15IlV j"C) from -25"C to +85"C and guarantees performance from -55"C to +1 25"C.
Electrical specifications are shown in Table I. Electrical tests are shown in Tables II and Ill.
1.2.2 Device class. The device class is similar to the hybrid class (class B) product assurance level. as defined in
M IL-M-38510. The Hi-ReI product designator portion of the part number distinguishes the product assurance levels as
follows:
Hi-ReI product
Requirements
desig~
'MIL
Standard model. plus 100% MIL-STD-883 hybrid class screening. with 10% PDA.
plus quality conformance inspection (QCI) consisting of Groups A and B on each
inspection lot. plus Groups C a,nd D performed initially and periodically thereafter.
Additional electrical testing is performed on / MIL models.
/883B
Standard model. plus 100% MIL-STD~883 hybrid class screening.
Standard model including' 100% electrical testing.
(none)
1.2.3 Case outline. The case outline is A-I (8-lead can. TO-99) as defined in M IL-M-38SIO. Appendix C.Thecase is metal
and is conductive.
1.2.4 Absolute maximum rating~
Supply voltage range
Input voltage range
Differential input voltage range
Storage temperature range
Output short-circuit duration
Lead temperature (soldering. 6Osec)
Junction temperature
1.2.5 Recommended oRerating conditions.
Supply voltage range
Ambient temperature range'
1.2.6 Power and thermal characteristics.
Package
8-lead can
1
1.

Case outline
Figure I

±20VDC
±20VDC.!.
±40VDC.!.
-65''C to + 150"C
Unlimited 3.
300"C
TJ = 175"C

±5VDC to ±20VDC
-S5"C to + 125°C

Maximum allowable
power dissipation
225mW at TA -125"C

Maximum
oJ-A

220"CjW

The ahsolute maximum input ,"oltage is equal In the supply vultage.
Short circuit may he ttl ground only. Rating apples 10 +135"( ca!

OPEN-LOOP FREQUENCY
RESPONSE

,--

"0

~

+45'"

r\..

1\10,.

~

r

~

20

I'\.

-

o

~

C/)

'"

-45 ?o
90~

"

135~

-

10 100 Ik 10k lOOkiM lUM'80
Frequency (Hz 1

OUTPUT VOLTAGE vs
FREQUENCY

30

+90

iii
"0

1201-'-+--+~+

""

Q.

:>

~

+40

RL = 2kll
~ 10'I

25

~=t~~~20
'is

>
~
'5

o

15

g

10

'5
Q. -5
'5

"

5
:--:;~,'-

°1

'"

+20
0
-20

"

-40

J!l
'0

0

0

0_ 10

10 100 lk 10k lOOk 1M

020406080
Time (#-,secJ

QUIESCENT
SUPPLy'CURRENT

aiCOMMON MODE REJECTION

TAr:.::::25~C

TA-~OC

1\
\
1

II

Frequency (Hz I

1\

CL = 500pF

~

~120

c:

0100

t;

Q)

>
'5
,g.

I
I

:g, 5

III

STEP RESPONSE

;;

VOLTAGE FULLOWER
LARGE SIGNAL RESPONSE

RL - 2kn

Z

TA = +85°C

TAL~5OC

_.. _---

~.,

.~ 80

a:

I,

~

60

'1c:'

40

o

..-

!

-~~t-

~ 20

RL = 2kll. CL = 50: F
o 1 2 3
Time I~Secl

o

E
0

5

10

15

20 II

Power Supply Voltage (±V 1

0

5

10

15

Common-Mode Input Voltage I ±V I

8. APPLICATION INFORMATION
8.1 Offset voltag!: !!#justment. Although the OPAI05! MIL Series has a low intital offset voltage (250M V), some
applications may require external nulling of this small offset. Figure 4 shows the recommended circuit for adjustment of
the offset voltage. External offset voltage adjustment changes the laser adjusted offset voltage temperature d r-ift slightly.
The drift will change approximately O.3M V!"C for every 100M V of offset adjustment.
8.2 Guarding and shielding. The ultra-low bias current and high input impedance of the OPAI05j MIL Series are
well-suited to a number of stringent applications, however, careless signal wiring of printed circuit board layout can
degrade circuit performance several orders of magnitude below the capability of the OPA lOS! MIL Series.
As in any situation where high impedances are involved, careful shielding is required to reduce "hum" pickup in input
leads. If large feedback resistors are used, they should also be shielded along with the external input circuitry.
Lea kage currents across printed circuit boards can easily exceed the amplifier's bias current of the OPA 105j MIL Series.
To avoid leakage problems, it is recommended that the signal input lead of the OPAIOSj MIL Series be wired to a Teflon
standoff. If the OPA lOS! MIL Series is to be soldered directly into a printed circuit board, utmost care must be used in
planning the board layout. A "guard" pattern should completely surround the two amplifier input leads and should be
connected to a low input impedance point which is at the signal input potential.
The amplifier case should be connected to any input shield or guard via pin 8. This insures that the amplifier itself is fully
surrounded by guard pptential, minimizing both leakage and noise, pickup. Figure 6 illustrates the use ofthe guard. The
resistor R3 shown in Figure 6 is optional. It may be used to compensate effects of very large source resistances. However,
note that its use would also increase the noise due to the thermal noise of R,1.
8.3 Thermal ~ponse time. Thermal response time is an important parameter in low drift operational amplifiers like
the OPA lOS! MIL Series. A low drift specification would be of little value if the amplifier took a long time to stabilize
after turn-on or ambient temperature change. The TO-99 package and careful circuit design provide the necessary quick
thermal response. Typical warm-u'p drift of the OPA 105j MIL Series is 20 seconds.

R,
INPUT

RZ

O--....,...'I.-;f"T-=~=~~~1
GUARD

,

R3

OUTPUT

I

. +

OUTPUT
INPUT

·INVE~TiNiiAMPi.jFIER

o-----J.L-_.-.-..-.~-14
FOLLOWER

RZ

,

+VCC(\.7~'
~v
01

OUTPUT

.vf?4 ~~~
05

OUTPUT
INPUT

0-----."".-.-..-_-.+-\
.
NoNINVERTING AMPLIFIER

'R3 may be used to compensate

lor very large source resistances.

GUARO

R, RZ/IR , + Rzl
muat b., low Impedance.

Bmd layout lor Inpul guarding
with To.g9 Package.

FIGURE 6. Connection of InputGuard.

11-83

32

~

BURR-BROWN@)

IElElI·

OPA 106/MILSERIES
MODEL NUMBERS:
·OPA106WM/MIL
OPA106WM/883B
OPA106WM
OPA 106UM/883B
OPA106UM

OPA106VM/MIL
OPA106VM/883B
OPA106VM

REVISION A
MARCH, 1984

FET Input Military
OPERATIONAL AMPLIFIER

FEATURES

APPLICATIONS

• LOW BIAS CURRENT. 100fA. max

• CURRENT-TO-VOLTAGE CONVERSION

• HIGH INPUT IMPEDANCE. 10130

• LONG TERM PRECISION INTEGRATION

• LOW DRIFT. 5/lV/oC. max

• PRECISION VOLTAGE AMPLIFICATION FOR
HIGH INPUT IMPEDANCE APP.LlCATIONS

• LOW OFFSET VOLTAGE 250/lV. max
. • LOW QUIESCENT CURRENT. I.5mA. max
• HERMETICALLY SEALED TO-99 PACKAGE

DESCRIPTION
The 0 P AI06 / MIL Series is a low bias current
100fA. max) operational amplifier. Guaranteed low
initial offset voltage (250/lV, max) and associated
drift versUs temperature (5/lV ('C, max) is achieved
by hiser-adjusting the amplifier during manufacturing. This feature, and guaranteed low bias current
allow greater system accuracy with no external
components.
Quiescent current (1.5mA, max) is unaffected by
changes in ambient temperature or power supply
,>:oitage. Other characteristics of the OPA 106/ MIL
Series include internal compensation for. unity-gain
I

stability and rapid thermal response for quick
stabilization after turn-on or temperature changes.
The amplifier is free from latch-up and is protected
for continuous output shorts to common. As an
added protection feature, either of the trim pins can
be accidentally shorted to a potential greater than the
negative supply voltage without damage.
The standard pin configuration (741 type) of the
OPAI06/MIL Series. allows the user drop-in replacement capability. A pin 8 case connection
permits. the reduction of noise and leakage by
employing guarding It:chniques.

•

Intarnilional Airport Industrial Parte· P.O. Box 11400· Tucson. Arizona 85734· Tal. 16021 741H 11 1 • Twx: 911J.9S2·1I11 . Cable: BBRCoRp· Telex: 66·6491

11--84

DETAILED SPECIFICATION
MICROCIRCUITS, LINEAR
OPERATIONAL AMPLIFIER
HYBRID, SILICON

I. SCOPE

1.1 ~.l!. This specification covers the detail requirements for a FET input, low bias current, low drift, integrated circuit
operational amplifier.
1.2 Part Number. The complete part number is as shown below.
jMIL

OPAI06

V

M

I

.l

..L

I

I

Hi-Rei product
designator
(see 1.2.2)
1.2.1 Device typ~. The device is a single operational amplifier. Threeelectrical performance grades are provided. The W
grade features ±51L VJOC drift (-55°C to + 125~C). The V grade features ±IOIL VJOC drift (-55"C to + 125°C). The U grade
features ±20/LV jnC drift from -25°C to +85°C and guarantees performance from -55"C to +125"C.
Electrical specifications are shown in Table I. Electrical tests are shown in Tables II and III.
1.2.2 Device class. The device class is similar to the hybrid Class (class B) product assurance level, as defined in
M I L-M -3851 O. The Hi-Rei product designator portion of the part number distinguishes the product assurance levels as
follows:
Basic model
number

Grade
(see 1.2.1)

Metal
package

Hi-Rei product
desig~

Reguirements

IMIL

Standard model, plus 100% MIL-STD-883 hybrid class screening, with 10% PDA,
plus quality conformance inspection (QCI) consisting of Groups A and B on each
inspection lot, plus Groups C and D performed initially and periodically thereafter.
Additional electrical testing is performed on / MIL models.

/883B
(none)

Standard model, plus 100% MIL-STD-883 hybrid class screening.
Standard model including 100% electrical testing.

1.2.3 Case outline. The case outline is A-I (8-lead can, TO-99) as defined in MIL-M-38510, Appendix C. The case is
metal and is conductive.
1.2.4 Absolute maximum

rating~

Supply voltage range
I nput voltage range
Differential input voltage range
Storage temperature range
Output short-circuit duration
Lead temperature (solderins, 6Osec)
Junction temperature

±20VDC
±20VDC I
±40VDC.i
-65"C to +150°C
Unlimited l.
300"C
TJ =+175°C

1.2.5 Recommended operating conditions.
Supply voltage range
Ambient temperature range

±5VDC to ±20VDC
_55°C to + 125"C

1.2.6 Power and thermal characteristics.

Package
8-lead ca; .

Case outline
Figure I

Maximum allowable
power dissipation
225mW at TA - +125°C

Maximum
11 J-C
220°CjW

1 The absolute maximum input voltage is ellual to the supply voltage.
1 Short circuit may be to grou?d only. Rating applies to +135"C case temperature or +SO"C ambient temperature at ±15VDC supply voltage.

11-85

2. APPLICABLE DOCUMENTS
2.1 The following documents form a part'of this specification to the extent specified herein.
I
.....
SPECIFICATION
MILITARY
,
'MIL-M-38510 - Microcircuits. general specification for.
STANDARD
MILITARY
MIL-STD-883 - Test methods and procedures for microcircuits.
3. REQUIREMENTS
3.1 General. Burr-Brown uses production and test facilities and a quality and reliability assurance program adequate to
assure successful compliance with this specification.
3.1.1 Detail specifications. The individual item requirements are specified herein. In the event of conflicting
requirements the order of precedence will be the purchase order, this specification, and then the reference documents.
3.1.2 Country of manufacture. The~e microcircuits are manufactured, assembled, and tested within the United States of
Amer~'
. .
3.2 Design, construction, and p,hysical dimensions,
3.2.1 Package, metals, and other materials. The package is in accordance with paragraph 35.1 of M IL-M-38510. The
exterior metal surfaces are corrosion resistant. The other materials are nonnutrient to fungus as specified in
MIL-M-38510. See Figure I for the case outline.

.Note:
leads in true position within O.010
fO.2Smm I R at MMC at seating plane.
H

Pin numbers shown for reference only.

Numbers may not be marked on package.

DIM

INCHES
MIN
MO\X

MILLIMETERS
MIN
MAX
9.40

A

.335

.370

8.51

B

.305

.335

7.75

C

.165

,185

4.19

0

.016

.021

0.41

0.53

.010

'.040

0.25

1.02

.010

.040

0.25

8.&1
I

470

1.02

G

.200 eASIC

5.08 BASIC

H

.028

.034

0.71

.029

.045

0.74

K

.500

12.7
2.79

M

160
110
45° BASIC

N

.095

lOS

0.86
1 "
4.06

45° BASIC
2.41

267

FIGURE I. Case Outline (TO-99) Package Configuration.

,

3.2.2 pesign documentation. The design documentation is in accordance with MIL-M-3851O.
3.2.3 Internal conductors' and internal lead wires. The internal conductors and internal lead wires are in accordance with
M IL-M-3851O.
3.2.4 Lead material and finish. The lead material is kovar type (type A). The lead finish is gold plate with nickel
underplating. The lead material and finish is in accordance with M IL-M-38510 and is solderable per M IL-STD-883,
method 2003.
'
3.2.5 Die thickness. The die thickness is in accordance with MIL-M-38510.
3.2.6 ~ysical dimensions. The physical dimensions are in accQrdance with paragraph 1.2.3 herein.
3.2.7 Circuit diagram and terminal connections. The circuit diagram and terminal connections are shown in Figure 2.
3.2.8 G1assivation. All dice utilized are glassivated.
3.2.9 Schematic Circuit. The schematic circuit is shown in Figure 3.

11-86

OUTPUT

·VCC
8HAO CAN fTOP VIEWf

FIGU RE 2. Circuit Diagram and Terminal Connections.

OUTPUT

OFFSET

TRIM

FIGURE 3. Simplified Schematic Circuit.

3.3 Electrical Qerformance characteristics. The electrical performance characteristics are as specified in Table I and
apply over the full operating ambient temperature range of _55°C to +125°C unless otherwise specified.
3.3.1 Additional electrical Qerformance characteristics. Electrical performance curves are shown in paragraph 7.
3.3.2 Offset null. The amplifier is capable of being nulled to zero offset voltage using the circuit in Figure 4. If nulling is
unnecessary for the application, delete the potentiometer and make no connections.

11-87

---0 OUTPUT

:-::.:=

OFFSET NUll

·Vee
FIGURE 4. Offset Null Circuit.

3.3.3 Freq~y com~nsation. No frequency compensation is required. The amplifier is free of oscillation when
.
operated at any gain and when operated in any test condition specified herein.
3.4 Electrical tests. Electrical tests are shown inTable II. The subgroups of Table III and limits of Table IV, which
constitute the minimum electrical tests for screening, qua:Iification, and quality conformance, are shown in Table II.
3.5 Marking. Marking is in accordance with M IL-M-38510. The following marking is placed on each microcircuit as a
minimum.
a. Part number (see paragraph 1.2)
b. Inspection lot identification code 1
d. Manufacturer's identification (rlii'B'fj
e. Manufacturer's designating symbol (CEBS)
f. Country of origin (U.S.A)
3.6 Workmanship": These microcircuits are manufactured, processed, and tested in a careful and workmanlike manner.
Workmanship is in accordance with good engineering practices, workmanship instructions, inspection and test
procedures, and training, prepared in fulfillment of Burr-Brown's product assurance program.
3.6.1 Rework provisions. Rework provisions, including rebonding for the i MIL product designation, are in accordance
.
with MiL:=M-385 10.
3.7 Traceability. Traceability for / MIL product designation is in accordance with MIL-M-38510. Each microcircuit is
trac~able to the production lot and to the component vendor's component lot. Reworked or repaired microcircuits
maintain traceability.
3.8 Product and process chang~. Burr-Brown wili not implement any major change to the design, materials,
construction, configuration, or manufacturing process which may affect the performance, quality or interchangeability
of the microcircuit without full or partial requali(ication.

JJ

A 4--digit date code. indicating year and week of seal. is marked on /8838 and (none) Hi-Rei product designations.

11-88

TABLE I. Electrical Performance Characteristics.
All characteristics at -55°C'; TA:S +125OC, ±Vce = 15VDC, unless otherwise specified.

SYM
BOL

CHARACTERISTIC
GAIN
Open-Loop
Voltage Gain

Avs

OPA108WM/MIL
OPAloeWM/883B
OPA108WM
MIN I TVP I MAX

CONDITIONS
RL 2kll
Vo = ±10V, F = OHz

103
93

TA +25°C
-55°C'; TA:S +125°C

OPA108VM/MIL
OPA108VM/8838
OPA108VM
MIN TVP I MAX

OPA108UM1883B
OPA108UM
MIN I TVP I MAX

UNITS

109
101

dB
dB

500
10

3
1000
25

V
mA
kll
pF
mA

19
1.2

1
28
1.8

RATED OUTPUT
Voltage
Current
Impedance

Load Capacitance
Short Circuit Current

R,=lkO

±10
±10

Vo
10
Zo
CL
los

To Ground

BW
BW
SR
Ts
Ts
T,

Unity Gain-Small. Signal t A = +25°C
Full Power
TA = +25°C
RL =2kll.
TA = +25°C
TA= +25°C
TA = +25°C
TA =+25°C

TA = +25°C
TA = +25°C

DYNAMIC RESPONSE
Bandwidth
Bandwidth
Slew Rate
Settling Time 10.1%1
Settling Time 10.01%1
Overload Recovery Y

MHz
kHz
VI~sec

6

~sec

18

~sec

4

15

~8ec

±250

~V

INPUT OFFSET VOLTAGE
Initial Offset
Temperature Sensitivity

VIO
DV,O

TA = +25°C
V,o (TA) - V,o (+25°C)

.n

±5

-55°C" TA" +125°C
~ +85°C
Vee = ±5, Vee = ±2OVDC

±10

-25°C:$ TA

vs Power Supply

PSRR

50
±20

~V/"C

-300

fA
fAN

#V/"C
dB

±80

INPUT BIAS CURRENT

Initial Bias
vs Supply Voltage

I"

TA - +25°C
TA = +25"C

1'0

TA =+25°C

··100

-150

1

INPUT OFFSET CURRENT1I
Initial Offset

I

I

I

±40

I

I

Differential
Common-Mode

Z,o

1013 11
0.8
1015 11
'1.6

TA == +oC

,

ZICM

Current

±80

I

I

1±80

i

fA

II

,

INPUT NOISE
Voltage

I
:

INPUT IMPEDANCE

en

in

fo = 10Hz
fo= 100Hz'
fo = 1kHz
fo = 10kHz
fa = O.lHz to 10Hz
fa = O.lHz to 10Hz
fa = 10Hz to 10kHz
fo = 1kHz

= +25"C
=+25°C
= +25°C
= +25°C
= +25°C
TA = +25°C
TA = +25OC
TA = +25°C

pF

011 pF

nVl$.
nVl$.
.nVl$.
nVI$.
iNI, p-p

75
55
35
35

TA
TA
TA
TA
TA

II

6

fA. pop

3
10
0.25

fA/VHz

±12
86

V
V
dB

fA,rms

INPUT VOLTAGE RANGE

Differential
Common-Mode
C9mmon-Mode Reject!on

V~

CMRR

V,N = ±10V

TA = +25°C
TA = +25OC
TA=+25°C

±20
±10
76

POWER SUPPLY
Rated Voltage
Voltage Range
.Quiescent Current

±15

±V~

±5

10

1.0

±20
1.5

VDC
VDC
mA

+125
+150

°C
°C

TEMPERATURE RANGE (ambient)
-55
-65

Operating
Storage
'Same as OPA106W Grade

NOTES:
1I Overload recovery is defined as the time required for the output to return from saturation to linear operation following.the removal of a 50% input overdrive signal.
21 Bias cum;nl islesled and guaranteed al T. = +25· C. For higher lemperature the bias current doubles every +10· C.

11-89

•
....

ii

8

~
=

3.9 Screening. Screening, for jMIL and /883B Hi-ReI product designations, isin accordance with MIL-STD-883,
method .500k, hybrid class, except modified .in paragraph 4.3 herein. ,.' . .
S~reening for the standard model includes BUrr,Brown QC4118 internal visual inspection and stabilization bake, fine
leak, gross leak, burn-in (72: hours performed preseal), temperature cycle (condition C), constant acceleration
. (condition .8), and eid:ernalvisuill inspection pet MIL-STD-883, inethod 5008, hybrid class. ".
.
For the / MIL product designation, all microcircuits will have passed the screening requirements prior to qualification or
quality conformance inspection.
.'
\
'
3.10 Qllalification. Qualification. is not required. ,See paragraph 4.2 herein.
3.11 Qualit:\' conformance inspection. Quality conformance inspection, for I MIL prod uct designation, is,in accordal)ce
with MIL-M-3851O, except as modified in paragraph 4.4 herein. The microcircuit inspection lot will have passed quality
conformance inspection prior to microcircuit delivery.

as

T ABLE II. Electrical Test Requirements.
(The individual tests within the subgroups appear in Table Ill)

MIL-STD-883~
REQUIREMENTS

(hybrid""'••)
Interim electrical

OPA106WM/883B
OPA106WM/MIL OPA106WM

OPA106VM/883B OPA106UM/883B
OPA106UM
OPA108VM/MIL OPA106VM

paramet~rs

I pre burn-in 1I method 50081

1,4

1,4

t,4

Final electrical test parameters
I method 50081

1',2,3,4

1,2,3,4

1'.2,3,4-

1,2,.3,4

I··

1,2,3,4

---

Table IV limits
and delta Limits

---

5.61/

Group A te*t requirements
I method 50081
Group C end point electrical
parameters I method 50081

Talile IV limits
and delta limits

Additional electrical subgroups
for Group C inspections

5.6JJ

-

1,4

1,4

1,2,3,4

1, 2U, 3U, 4

---

---

-----

-----

POA applies to subgroups 1 - 4 Isee4.3.dl

JI LTPO for these additional tests is 15%,

TABLE Ill. Group A Inspection.
LIMITS

SUBGROUP

SYMBOL
V,O

hB
1
TA=+25"C

Vo
IQ
CMRR
PSRR

MIL,STD-883
CONDITIONS
METHOD OR
±VCC= 15VDC
EQUIVALENT unless otherwls. specified

OPA106WM/MIL
OPA106WM/883B
OPA106WM
MIN
MAX

OPA106VMlMIL
OPA108VM/883B
OPA106WM
MIN
MAX

±250
±loo

4001
4001
AL =2kU

±10

VeM ±10V
Vee = ±5V, Vee = ±20V

76
80

±250'
±150
±10

±250
±3oo
±10

1.5

1.5
4003

OPA106UM/883B
OPA106UM
MIN
MAX

1.5

76

76

80

80

UNITS
~V

IA
V
rnA
dB
dB

2
TA=+125°C

OV,O

4001

V,a (125) -VIO (25)
100

2U
TA=+85°C

OV,O

4001

Via (85) -Via (25)

3
TA = -55°C

OVIO

4001

Via (25)

3U
TA = -25°C

OVIO

4001

Via (25) -Via (-25)
. 50

4
TA '=+25°C

AvS
SR

4004
4002

I-OHz, RL -2kU
RL'= 2kO Vo = ±10V

5
TA=+125°C

Avs

4004

I=OHz, RL=2kO

93

93

dB

Ii

AvS

4004

'1 = OHz,. RL = 2kO

93 ..

93

. dB

~V/oC

10

5

20

,.,.v/oC

'60
Via (-55)
80

~VloC

10

5

20
.103
1.2

. ".

TA = -55°C

11-90

103
1.2

103
1.2

I'V/oC
dB
V/p.sec

TABLE IV. Group C, End Point Electrical Parameters.
ITA

~

+25°C. ±Vcc ~ 15VDC, Voo

~

+5VDCI

4. PRODUCT ASSURANCE PROVISIONS
4.1 SampJ.!.!!g and inspection. Sampling and inspection procedures are in accordance with M IL-M-38510 and
MIL-STD-883. method 5008. except as modified herein.
4.2 Qualification. Qualification is not required unless specifically required by contract or purchase order. When so
required. qualification will be in accordance with the inspection routine of M IL-M-38510. paragraph 4.4.2.1. The
inspections to be performed are those specified herein for groups A. B. C and D inspections (see paragraphs 4.4.1. 4.4.2.
4.4.3. and 4.4.4).
Burr-Brown has performed and successfully completed qualification inspection as described above. The most recent
report is available from Burr-Brown.
4.3 Screening. Screening. for i MIL and /883 H i-Rei prod uct designations, is in accordance with M IL-STD-883. method
5008, hybrid class, and is conducted on all devices. The following additional criteria apply:
a, Constant acceleration test (MIL-STD-883, method 2001) is test condition B, VI axis only.
b. I nterim and final test parameters are specified in Table I I, The interim electrical parameters test prior to burn-in is
optional at the discretion of the manufacturer.
B c. Burn-in test (M IL-STD-883. method 1015) conditions:
(I) Test condition B
(2) Test circuit is Figure 5 herein
(3) TA = +125"C minimum
(4) Test duration is 160 hours minimum
d, Percent defective allowable (PDA). The PDA. fori MIL product designation only, is 10 percent and includes
both parametric and catastrophic failures. It is based on failures from group A. subgroup I test, after
cool-down as final electrical test in accordance with MIL-STD-883, method 5008, and with no intervening
electrical measurements. If interim electrical parameter tests are performed prior to burn-in, failures resulting from
preburn-in screening failures may be excluded from the PDA. If interim electrical parameter tests prior to burn-in
are omitted, all screening failures shall be included in the PDA. The verified failures of group A, subgroup 1, after
burn-in in that lot are used to determine the percent defective for that lot, and the lot is accepted Ilr rejected based
on the PDA.
·e. External visual inspection need not include measurement of case and lead dimensions.

FIGURE 5, Test Circuit, Burn-in and Operating Life Test;
4.4 Quality conformance inspection. G1'OUpS A and B inspections of M IL-STD-883, method 5008, is performed on each
lot. Groups C and 0 inspections of MIL-STD-883, method 5008, are not required unless specified by contract or
purchase order.
Burr-Brown periodically performs groups C and D inspections of MIL-STD-883. method 5008. A report of the most
recent groups C and D inspections is available from Burr-Brown~
4.4.1 Group A inspection. Group A inspection consists of the test subgroups and LTPD values shown in MIL-STD-883,
method 5008. Table X, and as specified in Table II herein.

11-91

4.4.2 Group B inspection. Group B inspection consists of the test subgroups and LTPD values shown in M IL-STD-883,
method 5008, Table XI.
4.4.3 Group C insp'ection. Group C inspection consists of the test subgroups and LTPD values shown in M IL-STD-883,
,
method 5008, Table XII, and as follows:
a. Operating life test (MIL-STD-883, method 1005) conditions:
(I) Test condition D
(2) Test circuit is Figure 5 herein
(3) TA = +125"C minimum.
'(4) Test duration is 1000 hours minimum
b. End point electrical parameters are specified in Table II herein.
c. Additional electrical subgroups are specified in Table II herein.
4.4.4 Group D insp'ection. Group D insPection consists of the test subgroups and LTPD values shown in M IL-STD-883,
method 5008, Table V.
'
4.5 Methods of examination and test. Methods of examination and test are specified in the appropri'ate tables. Electrical
test circuits are as prescribed herein or in the referenced test methods of M I L-STD-883.
4.5.1 Voltage and current. All voltage values given, except the input offset voltage (or differential Voltage) are referenced
to the-;;:ternal zero reference level of the supply voltage. Currents given are conventional current and positive' when
flowing into the referenced terminal.
4.6 Inspection of p'reparation for delivery..:. Inspection of pr~par'ation for delivery is in accordance with MIL-M-38510,
except that the rough handling test does not apply.
5. PREPARATION FOR DELIVERY
5.1 Preservation-packagillg and p'acking~ Microcircuits are prepared for delivery in accordance with M IL-M-385 10.
6. NOTES
6.1 Notes. The notes specified in MIL-M-38510 are applicable to this specification.
6.2 Intended use. Microcircuits conforming to this specification are intended for use in applications where the use Of
screened parts is desirable.
'
6.3 Ordering~ Tqe contract or order should speCify the following:
a. Complete part number (see paragraph 1.2)
b. Requirement fO,t certificate of compliance, if desired.
6.4 Microcircuit group assignment. These microcircuits are assigned to Technology Group F as defined in MIL-M38510, Appendix E:- - - - - 6.5 Electrostatic sensitivity. These microcircuits may be damaged by electrostatic discharge. Electrostatic sensitive
precautions should be observed at all times.
7. ELECTRICAL PERFORMANCE CURVES.
(Typical at TA = +25"C and ±V('c = 15VDC unless otherwise specified).
120

·90
1l

-..45 ~



.40

C>

-20

>

0

:;""

-20

-40

~ 20

'"is

>
~
:;

100

0
90 5

!
I

\

RL =2kll, L=sO:F
o 1 2 3
Time ,",sec.

5

!~~~~~~l.] ~

0120 ...--.-:c.;;;,=c,-;.::"""';';""r-,

O~,~~~~~~~~

-5

I
I
II

--~ I--

\
\

r

0

10

20 30 40

Time

m

r

~sec,

COMMON-MODE REJECTION

=;';~~loo
~80
-8o
=!'

I

60
40

ho

5

st,--~1"'0-'--'-"-5-""""'2:.!0 u
Power Supply Voltage' ±V

11-92

CL =500pF

,,120

c

~ ~o 20~4--+~~~~~

I 8~

~

°-10
5

~ ~ 6Of=+::!!1:~~~-+----l 8 1
" leo
"
.~
a: ,;,
~ '8 40 ~1--+-I---"'Ik"'Ik1-~

11.

0

10 100 lk 10k lOOk 1M
Frequency r Hz
QUIESCENT
SUPPLY CURRENT

~

g

:;

ttl "

~ .~100

T

10

0,

gt

T

15

RL =2kll

> 10 --- -

:!



>

10

~

0

:!0

-1353

20

"""" 25 r-1--+-+--r-4--4

115

= ~"C> 105

.

STEP RESPONSE

:;

;r
0

0,

.'"
'is

(fl

-90 ~

'is

>

.

'0

VOLTAGE FOLLOWER
LARGE SIGNAL RESPONSE

OUTPUT VOLTAGE vs
FREQUENCY

30

120

0

5

10

15

Common-Mode Input Voltage' ±V,

8. APPLICATION INFORMATION
8.1 Offset voltage adj~. Although the OPAI06/MIL Series has a low initial offset voltage (250I-'V). some
applications may require external nulling of this small offset. Figure 4 shows the recommended circuit for adjustment of
the offset voltage. External offset voltage adjustment changes the laser adjusted offset voltage temperature drift slightly.
The drift will change approximately 0.31-' V1°C for every 1001-' V of offset adjustment.
8.2 Guarding and shielding, The ultra-low bias current and high impedance of the OPAI06/ M IL Series are
well-suited to a number of stringent applications. however. ~areless signal wiring of printed circuit board layout can
degrade circuit performance several orders of magnitude below the capaoility of the OPA 106/ MIL Series.
-:\s in any situation where high impedances are involved. careful shielding is required to reduce "hum" pickup in input
leads. If large feedback resistors are used. they should also be shielded along with the external input circuitry.
Leakage currents across printed circuit boards can easily exceed the bi~s current of the OPA 106/ MIL Series. To avoid
leakage problems, it is recommended that the signal input lead of the OPA 106/ MIL Series be wired to a Teflon standoff.
If the OPA 106/ MIL Series is to be soldered directly into a printed circuit board. utmost care must be used in planning the
board layout. A "guard" pattern should completely surround the two amplifier input leads and should be connected to a
low input impedance point which is at the signal input potential.
The amplifier case should be connected to any input shield or guard via pin 8. This insures that the amplifier itself is fully
surrounded by guard potential, minimizing both leakage and noise pickup. Figure 6 illustrates the. use ofthe guard. The
resistor R, shown in Figure 6 is optional. It may be used to compensate effects of very large source resistances. However,
note that its use would also increase the noise due to the thermal noise of R,.
8.3 Thermal response time. Thermal response time is an important parameter in low drift operational amplifiers like the
OPAI06/ MIL Series. A low drift specification would be of little value if the amplifier took a long time to stabilize after
turn-on or ambient temperature change. The TO-99 package and careful circuit design provide the necessary quick
thermal response. Typical warm-up drift of the OPAI06j MIL Series is approximately 20 seconds.

RI

INPUT

o--"H.,....~r-T-=::;::::;~::;-I
GUARD

,

OUTPUT

OUTPUT

I

.

+

INPUT

O------+L-__-.-..-.•+-\
FOLLOWER

+VCCC\)l~

OUTPUF=>
OUTPUT
INPUT

o----......... 9.~"
GUARD

RI R2/IRI+ R21

must be LOW impedance.

FIGURE 6. Connection of Input Guard.

11-93

32

~

BaattllayaUl lor Input guanll",
with TO-llll plcklgl.

BORR-BROWN@

IElEaI

OPA600/MIL SERIES,
MODEL NUMBERS:
OPA600VM/MIL OPA600UM/8838
.OPA600VM/883B OPA600UM
OPA600VM
REVISIONC'
. JULV,1883

Fast Settling -Wideband
OPERATIONAL AMPLIFIER
FEATURES

APPLICATIONS

• FAST SETTLING
BOnlac 10±D.l %.
115nlac 10 ±O.O1%

• VOLTAGE CONTROLLED OSCILLATOR DRIVER

• FULL DIFFERENTIAL FEr INPUT
• -55"C TO +1 25°C OPERATION

• LARGE SIGNAL. WIDEBAND DRIVERS
• HIGH SPEED DAC OUTPUT AMPLIFIER
• VIDEO PULSE AMPLIFIER

• LARGE OUTPUT
±lOV. ±2OOmA (50n)
• GAIN-BANDWIDTH PRODUCT - 5GHz

DESCRIPTION
The OP A600 is a wideband operational amplifier
specifically designed for fast settling to ±O.OI%
accuracy. It is stable, easy to use, has good phase
margin with minimum overshoot, and it has excellent
DC performance. It utilizes a FET input stage to give
low input bias current in contrast to the higher
currents usually associated with very-fast amplifie.rs.
Its DC stability with temperature is outstanding. Its
-3dB bandwidth of·lOOMHz is available at a closed
loop gain of 10. The slew rate exceeds400V / j.lsec. All
of this combines to form an outstanding amplifier for
large and small signals.
Settiing time is the best measure of this amplifier's
total dynamic capability. High accuracy with fast
settling is achieved by the large open-loop gain,
which provides the accuracy at the upper frequencies.
The thermally balanced design maintains this accuracy without droop or thermal tail. External
compensation allows the user to optimize the settling
time in his application.
The OP A600 is built to be reliable and is ~esigned to
operate from TA = -SS·C to +12S·C. It is a hybrid
microcircuit in a welded, hermetic, metal package

and is available with MIL-STD-883 screening. The
circuit is built on an alumina substrate which has a
metallic attach to the package for good thermal
transfer and reliable high temperature operation.
The metal package provides electrostatic shielding.
The circuit uses thin-film resistors and all glassivated,
high speed silicon die. The gold or aluminum wirebonds utilized produce a monometallic system
wherever possible, eliminating metal migration, a
time-temperature reliability problem. The amplifier
is actively laser-trimmed and is thoroughly tested.
Reliability is emphasized during each phase of
manufacture.
The OP A600 is useful in a broad range of video, high
speed, and ECM applications. It is particularly well
suited to operate as a voltage controlled oscillator
(VCO) driver. It makes an excellent digital-to-analog
converter output amplifier. It is a workhorse in test
equipment where fast pulses, large signals, and son
drive are important. It is a good choice for sample/
holds, integrators, fast waveform generators, and
multiplexers.

'Inllmllional Airport Ind.-trial Park· P.O. Box 11400· Tucl8II. Arlzuna 85734· Tel.1602l 746·1111 . Twx: 910-952·1111 • Cable: BBHCORp· Telex: 66.f1491

'11-94

DETAILED SPECIFICATION
MICROCIRCUITS, LINEAR
OPERATIONAL AMPLIFIER
HYBRID, SILICON
I. SCOPE
1.1 Sco~. This specification covers the detail requirements for a hybrid. fast settling, integrated circuit operational
amplifier.
1.2 Part Number. The complete part number is as shown below.

V

OPA600

T

8asic model
number

l

M

/MIL

Metal
package

Hi-ReI product
designator
(see 1.2.2)

l

Grade
(see 1.2.1)

I

1.2.1 Device typ,l;.. The device is a single, operational amplifier. Two electrical performance grades are provided, the U
grade and the V grade. The V grade offers the higher performance. Electrical specifications are shown in Table I.
Electrical tests are shown in Tables II and Ill.
1.2.2 Device class. The Hi-ReI product designator portion of the part number distinguishes the product assurance levels
as follows:
Hi-ReI product
designator
Re!luirements
/MIL
Standard model, plus 100% MIL-STD-883, method 5008, class 8 screening, with 10%
PDA, plus quality conformance inspection (QCI) consisting of Groups A and 8 on each
inspection lot, plus Groups C and D performed initially and periodically thereafter.
Additional electrical testing is performed in / MIL models.
/8838
Standard Model, plus 100% MIL-STD-883, method 5008, class 8 screening.
(none)
Standard model including 100% electrical testing.
1.2.3 Case outline. The case outline (16-lead can) is as defined in Figure 6. The case is metal and is conductive.
1.2.4 Absolute max~mum rating§..
±17VDC
±17VDC.!.
±25VDC.!..
-65°C to +150·C
A few seconds 11
300"C
TJ = 175°C

Supply voltage range
Input voltage range
Differential input voltage range
Storage temperature range
Output short-circuit duration
Lead temperature (soldering, 6Osec)
Junction temperature
1.2.5 Recommended o!,!rating conditions.
Supply voltage range
Ambient temperature range
1.2.6 Power and thermal characteristics.

Packag!e
16-lead,can

Case outline
Figure 4

±9VDC to ±16VDC
-55"C to +125°C

Maximum allowable
Maximum
8 J-C
Rower dissip'ation
2.6W at TCAsE = See Applications
+125°C
I'llformation

I; The absolute maximum input voltage is equal to the supply voltage.
Duration is limited by device heat sinking (thermal resistance). Short circuit may be

"i;

to

11-95

ground only.

Maximum
8C-A
35°CfW

2. APPLICABLE DOCUMENTS
2.1 The following documents form a part ofthls specification to 'th~ ,extent specified herein.
SPECIFICATION
'
"
"
;,'
MILITARY
MIL-M-38510 - Microcircuits; general specifipationfor.
STANDARD
MILITARY
MIL-STD-883 - Test methods and procedures for microcircuits.
3. REQUIREMENTS
3.1 General. Burr-Brown uses production and test facilities and a ql,lality and reliability assurance program adequate to
assure successful compliance with this specification.
3.1.1 Detail specifications. The individual item requ,irements are, specified herein. In the event of conflicting
requirements. the order of precedence will be the purchase order, this specification, and then the reference documents.
3.1.2 Country of manufacture. These microcircuits are manufactured, assembled, and tested within the United States of
America.
3.2, Design, construction. and physical dimensions.
3.2.1 Package, metals, and other materials. The package is in accordance with paragraph 3,5.1 of M I L-M-385I 0, except
that organic and polymeric materials (epoxy) are used for attach of some of the die. The' exterior metal surfaces are,
corrosion resistant. The other materials are non nutrient to fungus as specified in MIL-M-3851O.
3.2.2 Design documentatiori. The design documentation is in accordance with MIL-M-38510.
3.2.3 Internal conductors and internal lead wires. The internal conductors and internal lead wires are in accordance with
MIL-M-38510.
3.2.4 Lead material and finish. The lead finish.is gold plate with nickel underplating. The lead material and finish is in
accordance with MIL-M-38510 and is solderable per MIL-STD-883, method 2003.
3.2.5 Die thickness. The die thickness is in accordance with MIL-M.38510.
3.2.6 Physical dimensions. The phYsical dimensions are in accordance ~;ih paragraph' 1.2.3 herein.
3.2.7 Circuit diagram and terminal connections. The circuit diagram and terminal cO!lnections are shown in Figure I.
3.2.8 Glassivation. Glassivation is in accordance with MIL-M-38510.

OFFSET ERROR NULL 100011onal)

'-Vee '

COMMON
(Clse)

JJ Rller to Figure 4 lor recommended lrequlncv companut~.

11 Cenneet pin 9 to pin 121nd connect pin 710 pin 8 for,maxlmum IHllput curranl.See

:v

~

There I. no Internal connecllon. An axtam.1 connection mlV ba madL

§I Ilia recommended Ihallba amplifier be _ntad wllh lhe casa In contacl whh •

AppllcaUon Inlormdlon lor further Inlormatlon.
Bypaaa lid! poWir lupplV IIId II clou 18 pollibleto lilt ampllflar pins. AIp.F
eS11 lanlllu.. capaclfllr la _ ..ended.

gnlund plane lor good lhermal trlnllar and optimum AC perlormal1GL

FI G U RE I. Circuit Diagram and Terminal Corinections.

11-96

3.2.9 Schematic Circuit. The schematic circuit is shown in Figure 2.
OFFSET

OFFSET

FREQUENCY
COMPENSATION

FREQUENCY
COMPENSATION
12 +VCC

COMMON

lcala,

!

FREQUENCY
COMPENSATION

R7
R13
50n

CI

D.01"F

CURRENT
BOOST

~~-4----{9

~------------~Q8

RII
R8
·INPUT

R4

R3

CURRENT
BOOST

3r---------~----------~

~--~---l7

01
RIO
R9

.Vee

RI6
5O1l

C2
O.OI"F

COMMON

FIGURE 2. Simplified Schematic Circuit.
3.3 Electrical ~erformance characteristics. The electrical performance characteristics are as specified in Table I and
apply over the full operating ambient temperature range of -55~C to +125°C unless otherwise specified.
3.3.1 Additional electrical ~erformance characteristics. Electrical performance characteristic curves are shown in
paragraph 7.
3.3.2 Offset error null. The amplifier is capable of being nulled to zero offset voltage using the circuit in Figure 3. If
nulling is unnecessary for the application, delete the three components and make no connections.
• +vCC

::!
:IE
.......

§
C

a..

1:1

INPUTS

FIGURE 3. Offset Null Circuit.
3.3.3 Freql!ro..cy compensation. The amplifier must be externally frequency compensated. See Figure 4.
3.4 Electricahests. Electrical tests are shown in Table II. The subgroups ,of Table III and limits of Table IV, which
constitute the minimum electrical tests for screening, qualification, and quality confQrmance, are shown in Table II.

11-97

3.5 Marking. Marking is in accordance with M I L-M-385 10. The following marking is placed .on each microcircuit as a
minimum.
- a. Index point
b. Part number (see paragraph 1.2)
c. Inspection lot identification code.!l
d. Manufacturer's identification
e. Manufacturer's designating symbol (CEBS)
f. Count!")' of origin (USA)

(IIiWl@)

3.6 Workmanship. These microcircuits are manufactured, processed, and tested in a careful and workmanlike manner.
Workmanship is in accordance with good engineering practices, workmanship instructions, inspection and test
procedures, and training, prepared in fulfillment of Burr-Brown's product assurance program.
3.6.1 Rework p'rovisions. Rework provisions, including rebonding, for the / MIL H i-Rei product designation, are in
accordance with MIL-M-3851O.
.
3.7 Traceability. Traceability for IMIL Hi-Rei product designation is in accordance with MIL-M-38SI0. Each
microcircuit is tr7tceable to the production lot and to the component vendor's component lot. Reworked or repaired
microcircuits maintain traceability.
3.8 Product and p'rocess chang!:; Burr-Brown will not implement any major change to the design, ml\terials,
construction, configuration, or manufacturing process which may affect the performance, quality, reliability or
interchangeability of the microcircuit without full or partial requalification.
3.9 Screening. Screening, for 1 MIL and 1883B Hi-Rei product designations, is in accordance with MIL-STD-883,
method 5008, dass B, except as modified in paragraph 4.3 herein.
Screening for the standard model, includes Burr-Brown QC4118 internal visual inspection, stabilization bake, fine leak,
gross leak, burn-in (72 hours performed preseal), temperature cycle, constant acceleration (condition B), and external
visual inspection per MIL-STD-883, method 5008, class B.
For the /MIL Hi-Rei product designation, all microcircuits will have passed the screening requirements prior to
qualification or quality conformance inspection.
3.10 Qualification. Qualification is not required~ See paragraph 4~2 herein.
3.11 Quality conformance insp'ection. Quality conformance inspectiOn, for 1M IL Hi-Rei product designation, is in
accordance with MIL-M-38510, expect as modified in paragraph 4.4 herein. The microcircuit inspection lorwill have
passed quality conformance inspection prior to microcircuit delivery.
.

R1

R3

R4

C1 ·C2

short

open

6.8

620

short

open

3.3

lk

short

open

3.3k

3.3k

3.2k

3.3k

3.3k

116

+1

open

R2
100

-1

620
100
100
100

c3

,

I I A ~igit date code. indicatina year and week of seal, and a 4- or Soodigit lot indentifier is marked on each unit.

11-98

RS

4.7

56

2.2

100
100

0

Note: Resistance is in ohms. capaeJlan"" is in pF.
gain is volts/voll.
.

FIGURE 4. Recommended Amplifier Circuits and Frequency Compensation.

c4

4.7

100

T ABLE I. Electrical Performance Characteristics
All characters frolT'-55°C" TA" +12SOC, ±Vee = 15VDC, unless otherwise noted.

OPAIOOVM/MIL
OPAtlOOVM/883B
OPMOOVM
CHARACTERISTICS

CONDITIONS

MIN

TYP

OPMOOUM/883B
OPMOOUM

MAX

MIN

TYP

MAX

UNITS

OUTPUT
Voltage IVol
Current (10)
Currenl, pulse (I",,)
Resistance (Ro)
Short Clrcuil Currenl (los).

±10
±9
±180
±I80

RL=2kll
RL =501l J/
RL =50IlJ/
RL = 50n'y
Open-loop, DC

V
V
mA
mA

±11
±10

±200
±200
75
250

150
300

115

125

.TA =+25°C

125
105
80
80
55

140
130
105
105
75

t = 1",sec to 500msec

0.5

I

To ground only,

n
mA

IMAX = l.ec1/

DYNAMIC RESPONSE
Settling Time, ±0.01 %
11,1

S

±0.1%
±I%
Post Settling Time
Stability IIs+1 EI

.1Vo = 10V

.1Vo
.1Vo
.1Vo
.1Vo

=
=
=
=

TA = 25°C
TA = -25°C to +85°C
TA = -55°C to +125°C
TA = +25°C
TA = +25°C
TA = +25°C

201{
10V
20V
5V

±0.01%

Gain-Bandwidlh Product
10pen-looPIIGBP,

G=IVN

I

I
I

Ce =OpF,

G=I000VN
Ce =OpF,

Y

nsec
nsef:
nsec
nsec
nsec
nsec
nsec
mV

TA = +25°C

150

MHz

TA = +25°C

500

MHz

TA = +25°C

1.5

GHz

TA = +25°C

5

GHz

G= 10,OOOVN

TA = +25°C

G=+1VN
G=-WN
G=-IVN

TA =
TA =
TA =
TA =
TA =
TA =
TA =

G=-IOVN
G=-IOVN
G=-I00VN
G=-IOOOVN
Full Power Bandwidlh
IBWFPI

Vo =±5V, }
G=-WN
Cc =3.3pF,
RL = l001!

Slew Rate ISR I

Vo =±5V,
G=IOOOVN
Ce =OpF,
RL = lOOn
Vo= ±5V,
G =-niN

~
Phase Margin

150
165
175

Ce = OPF'1
Cc =OpF,
G= 10VN
Cc =OpF, }
G= l00VN

Bandwidth IBWI
-3dB, small signal

125
135

G=-WN,
Ce = 3.3pF

+25°C
+25°C
-55°C 10 +125°C
+25°C
-55°C to +125°C
+25°C
+25°C

TA=+25°C

10

GHz

100
75
70

125
90

80
70
15
5

95
95
20
6

MHz
MHz
MHz
MHz
MHz
MHz
MHz

13

16

MHz

500

V/J,lsec

TA =+25°C
AVo=10V

}

TA = +25°C
AVo=IOV
TA = -55°C to+125°C

400

90

135
135

V/",sec

440

V/,usec

350

TA = +25°C

40

Degrees

94

dB
dB

GAIN
Open-Loop Voltage Gain
IAvsl

f=D.C"
RL =2kl!

TA = +25°C

TA = -55°C to +125°C

86
74

INPUT
Offset Voltage IV,OI])

TA = +25°C
TA = -25°C to .S5°C
TA = -55°C to +125°C

Offset Voltage vs

TA = -25°C to +25°C
TA +25°C to +85°C
TA = -55°C to +25°C
TA =+25°Cto+125°C

Temperature

(OV,OI
Bias Currenl (hB I

TA = +25°C
TA = +250 Cto +125°C

Offset Cumint 11101

TA = +25°C
TA = -55°C to +1 25°C

1

4

2

5
10
15

mV
mV
mV

50
25

80
80

~VfOC

100
100

~VfOC

6

0
0

11-99

~VfOC

10
10

20

-20
-20

-100
-100

pA
nA

20
20

50
50

pA
nA

20

~VfOC

,
&
.......
g

=
~

=

TABLE I. Electrical. Performance Characteristics (cont)
All characteristics from -95 0 0 S TA S"+1'2So C, ±Vcc = 15VDC, unless otherwise noted.

CHARACTERISTICS

MIN

CONDITIONS
Vee - ±15V. ±1V TA = +25°C

Po;.o:roSWI~~~ejecli""
Common-Mode
Voltage Range (CMV)
Common-Mode Rejection
Ratio (CMRR)
Impedance (ZIN)

TA = +25°C

-10

VeM = -{)V to +5V T A = +2Soc

60

.. OPA6OOUM/883B
OPA600UM

np

MAX

200

500

MIN

TYP

MAX

UNITS
~VN

,

+7

V
,.\.

80

dB

Common~mode

TA = +25°C
TA = +25°C

1011 II 2
1011 112

nil pF
nil pF

I = 10kHz

TA=+25°C

20

Differential

Voltage Noise (en)

.,

nVI\I'HZ
..

POWER SUPPI,Y
Rated (Yee)
Operating Range (Vee I
Quiescent Current (10)

±15

:t9

VDC
VDC
mA

:!:16
±38

±30

TEMPERATURE RANGE
(ambient)
Operating
Storage
8JC (junction to case I
(JCA I case

-

OPA600YM/MIL
OPA600YMl663B
QPA600YM

..

-55
-65

+125
+150

-55
-65

+125
+150

°C
°C

. See applications information

to ambientl

35

°C/W

..

flSpeclflcatlons the same as V grade.
NOTES:
jJ Pin 9 connected tl:? +Vcc, pin 7 connected to -Vee. Observe power dissipatjo~ ratings.
Pin 9 and pin 7 open. Single pulse t = 100nsec. 'Observe power disSipation ratings.
2/ Pin 9 and pin 7 open. See paragraph 8.B.
jJ G = -1VN. Optimum eeltling time and slew rate achieved by individually compensating each device. Reier to paragraph 8.3.
§I Post settling time stability is a measure of the pulse droop. or thermal tail. after the output has settled.
!}J Compensation per paragraph 8.311 Adjustable to zero.

11

lDr--DA~

~

t-

I
nn

..L-DO

I ..

!! ~ ~ i ~ l

Seating Plane

-Lo

I I

~G·

. -

NOTES:
1. Leads in true position within 0.010"
(0.25mml R at MMC at seating plane .
2. Pin

H

io

I0

K

.280

~

.100. BASIC

R

.085

I)

16

G

9

GOOvOCllO€l

L,~

MAX

H

C

t

MIN

.883 .880
.7eo .805
.175 .180
.,014 .022
.100 BA81C
.135 .155

8

Denotes Pi n 1

I

shown f~r reference only.

INCHES

DIM

A

-.L

numbe~

I

MILLIMETERS

MIN

-270

I

.116'

MAX

24AI 14.88
18.30 20A5
4.45 4.83
0.3e 0.a8
2.U BASIC
U3J 3.84
5 .• '"

8.80

15.24 BASIC
2.41
2.82

FIGURE 5. Case'Outline.
TABLE II. Electrical Test Requirements.
(The individual tests within the subgroups appear in Table III)

~
elu')

MIL·STD·883 TEST REQUIREMENT (hybrid

Interim electrical parameters (pre burn·in)(method 5008)

Final electrical test parameters (methqcf5008)
Group A test reqUirements (method 5008)
Group Cend point electrical parameters (method 5008)

...

Additional electrical su~groups performed· prior to Group C inspections
.~.

-

PDAappl!eS 10 subgrpup 1 (see 4.3.d)

OPA60OYM/6638
OPA600YM

OPA600YM/MIL

OPA600UM/8838 '
OPA600UM

Subgroups (eee Table·1I11
1

1

'''2,3.4..7,9,10,''

1,2,3,4,7.9

i. 2, 3, 4, 7, 9
Tab~ek~ W~ii':.ano

..

_.

-

.-

.... None

-.

1.
1,2, 2U. 3, 3U, 4, 7. 9

-

TABLE III. Group A Inspection.
LlMlni
OPA600VMJMIL
OPA600VM/883B
OPA&OOUM/883B
OPA600YM
OPA&OOUM
MIN
MAX
MIN
MAX

MIL-STD-883
METHOD OR
EQUIVALENT

CONDITIONS
±VCC =lSV.
unl_ otherwise opeclfled

+PSRR
-PSRR
CMR
10

4001
4001
4003
4003
4003
4005

VeM=O
VeM=O
+Vee = 15V. ±1V, -Vee = 15V
+Vee = 15V, -Vee = 15V, ±1V
VeM = -5V to +5V

2
TA = +125°C

Via
OV,a

4001
4001

2U
TA=+85°C

Via
OV,a

4001
4001

3
TA = -55°C

Via
.OV,O

4001
4001

3U
TA = -25°C

OV,a

4001

4
TA = +25.°C

Va
10
Avs

4004
4004
4004

RL =2kn
RL = 50n, pin 9 to +Vee, pin 7 to -Vee
RL = 2k!l, I = OHz, Va = ±10V

±10
±160
86

±10
±180
86

V
mA
dB

7
TA = +25°C

Va
Va

4004
4004

RL = 2kn, ±Vec = 16VOC
RL = 2kll, ±Vee = 12VOC

±11
±?

±11

V
V

9
TA = +25°C

ts

Y

4002

To ±O.Ol%, Figure 10
final value at t = 1.usec

SR

y

4002

G = -1, Va = ±5V, Figure 10
10% to 90%

J/Y

4002

To ±O.Ol%, Figure 10
G=-1,Vo.;=±5V

140

nsec

tsyy

4002

To ±O.Ol%, Figure 10
G=-l, Vo =±5V·

140.

nsec

SUBGROUP

SYMBOL

1
TA=+25°C

V,O

10
TA = +125°C
11
TA= -55°C

liB

-4

+4

0
-500
-500
60

-100
+500
+500

Via I +25°C I - Via (+125°CI
l00"C

-6

-Hi

-20

+20

Via 1+25°CI - Via (+85°C)
600C

-6

+6
+20

-20

Via 1+25°CI - VIO 1-55°CI
800C
VIC I +25°C, - VIC r-25°CI

38
-15
-100

+15V
+100

mV
pV/"C

-10
-80

+10
+80

mV
pV/"C

-13
-100

+13
+100

mV
pV/"C

-9
-80

+9
+80

mV
pV/oC

-500
60

+5
-100
+500
+500

±7
125

400

UNITS
mV
pA
pVIV
pVIV
dB
mA

-500

38

500C

ts

-5
0

150
400

nsec
V/psee

NOTE:
11 This test required lor IM.IL suffix only. Sample test per MIL-STO-l05 level II, 4.0% AOL, normal inspection.
21 G :::::: -1V/V. Optimum settling time and slew rate achieved by individually compensating each device. Refer to paragraph 8.3.

TABLE IV, Group C. End Point Electrical Parameters.
(TA = +25°C, ±Vcc = 15VOCI
TEST
Input Offset Voltage
Open-Loop Voltage Gain
Settling Time
(to 0.01%, AVo = 10V, G = -1 I

LIMIT

DELTA

4mV
B6dB

3mV
6dB

12Snsec

-

4. PRODUCT ASSURANCE PROVISIONS
4.1 Samp'ling and inspection. Sampling and inspection procedures are in accordance with M IL-M-38510 and
MIL-STD-883. method 5008. except as modified herein.
4.2 Qualification. Qualification is not required unless specified by contract or purchase order. When so required,
qualification will be in accordance with the inspection routine ofMIL-M-38510, paragraph 4.4,2, I. The inspections to be
performed are those specified herein for groups A, B. C and D-inspections (see paragraphs 4.4. 1,4.4.2,4.4.3, and 4.4.4).
Burr-Brown has performed and successfully completed qualification inspection as described above. The qualification
report is available from Burr-Brown.
4.3 Screening. Screening. for / MIL and /883 Hi-Rei product designations, is in accordance with MU.-STD-883, method
5008, class B. and is conducted on all devices, The following additional criteria apply:
.
a, Constant acceleration test (MIL-STD-883, method 2001) is test condition B, Y, axis only.
b. Interim and final test parameters are specified in Table II. The interim electrical parameters test prior to burn-in is
optional at the discretion of the manufacturer.
.

11-101

, C. Burn-in test (M I L~STD"S83, method 10 I 5) conditions:
(I) Test condition B
.
(2) Test circuit is Figure 6 hereip
(3) T A = +125"C minimum
'(4) Test duration is 160 'hours minimum
d. Percent defective allowable (PDA). The PDA, for / MIL Hi-Rei product designation only, is 10 percent and
includes both parametric and catastropic failures. It is based on failures from group A, subgroup I test after
cool-down as final electrical test in accordance with MIL-STD"S83, method 5008, and with no intervening
electrical measurements. If interim electrical parameter tests are performed prior to burn-in, failures resulting from
preburn-in screening failures may be excluded from the PDA. If interim electricaJ parameter tests prior to burn-in
are omitted, all screening failures shall be included in the PDA. The verified failures of group A, subgroup I after
burn-in in that lot are used to determine the percent defective for that lot, and the lot is accepted or rejected based
on the PDA.
e. External visual inspection need not include measurement of case and lead dimensions.

FIGURE 6. Test Circuit Burn-in and Operating Life TeSt.
4.4 Quality conformance inspection. Groups A and B inspections of MIL-STD"S83, method 5008, are performed on
each inspection lot. Groups C and D inspections of MIL-STD-883, method 5008, are not required unless specified by
contract or purchase order.
Burr-Brown periodically performs groups C and D inspections of M lL-STD-883, method 5008. A report of the most
recent groups C and D inspections is available from Burr-Brown.
4.4.1 Group A inspection. Group A inspection consists of the test subgroups and LTPD values shown in MIL-STD-883,
method 5008, and as specified in Table II herein.
4.4.2 Group B inspection. Group B inspection consistsofthe test subgroups and LTPD values shown in MIL-STD-883,
method 5008.
4.4.3 Group C inspection. Group C inspec'tion consists of the test subgroups and LTPD values shown in M IL-STD-883,
method 5008, and 8S1'ollows:
a. Operating life test (MIL-STD-883, method 1005) conditions:
(I) Test condition B
(2) Test circuit is Figure 6 herein
(3) T A = 125°C minimum
(4) Test duration is 1000 hours minimum ,
b. End point electrical parameters are specified in Table 11 herein.
c. Additional electrical subgroups are specified in Table II herein.

11-102

4.4.4 Group D inspection. Group D inspection consists of the test subgroups and LTPD values shown in M IL-STD-883,
method 5008.
4.5 Methods of examination and test. Methods of examination and test are specified in the appropriate tables. Electrical
test circuits are as prescribed herein or in the referenced test methods of MIL-STD-883.
~.5.1 Voltage and current. All voltage values given, except the input offset voltage (or differential voltage) are referenced
to the external zero reference level of the supply voltage. Currents given are conventional current and positive when
flowing into the referenced terminal.
4.6 Inspection of packagi!!g. Inspection of packaging shall be as specified in MIL-M-385 10.
5. PREPARATION FOR DELIVERY
5.1 Preservation-packagl.!lg and packing. Microcircuits are prepared for delivery in accordance with MIL-M-38510.
6. NOTES
6.1 Notes. The notes specified in MIL-M-38510 are applicable to this specification.
6.2 Intended use. Microcircuits conforming to this specification are intended for use in applications where the use of
screened parts is desirable.
6.3 Ordering data. The contract or order should specify the following:
a. Complete part number (see paragraph 1.2)
b. Requirement for certificate of compliance, if desired.
6.4 Microcircuit g!:Q!!p assig~. These mircocircuits are assigned to Technology Group F as defined in MIL-M38510, Appendix E.
6.5 Electrostatic sensitivity. These microcircuits may be damaged by electrostatic discharge. Electrostatic sensitive
precautions should be observed at all times.

7. ELECTRICAL PERFORMANCE CURVES

(Typical atTA = +25°C and ±Vcc = 15VDC. unless otherwise specified I.
BODE PLOT

100
90

III

r-c;: <:illli .......
i"""ooo.

~60
50

c=3.3pF

~40

r--.. ""
r--..

8" 30

..J

e.

20

8- 10

Cc ,{PF

o I-CFt= 3.3r~1

""""

600

CC

lOOk

SETTLING TIME VS GAIN

3001r--~~";;"~--.,..---.,

..\

~ c:
+1004

l""1::!

,g

~

+501

o

~

J

3fP

II .Ll
1M
10M
Frequency (Hz)

1\

"

~
010

if

lpF

.i!!

i'~ 6

'"'1-.E~

Cc

-20
-40
10k

~8
8c:

"",,,,

-10
-30

700

lo-~c=OpF

80 l"o

_ 70

·i

COMPENSATION AND SLEW RATE VS GAIN
10

II

100M

-50
100

-

0.

~

SLEW RATE

,

.J( ...II!'"

8.

""-

5

0 2

COMPENSATION

-150
loo0M

SETTLING TIME
2oor-__V~S~O~UrT~P~U~T~V~O~L~T~AG~E~C~HrA~N~G~E--,

01

---r-+-IJl
10
Closed-loop Gain (VNI = 1 + RF/RIN
SETTLING TIME AND
SLEW RATE VS TEMPERATURE

1.2

G=1VN
1.1

j200~----~----~~--~~
~ 150~---+.:J!:;",,--:;;;""~~E:,

.~

Is

~

lO.D1~1

~ .....

go

~ looE:=~;'~:;;"'~:t----I
50r_--__. .~-+---r_---i

0.9

0 ....--.,5!--~1:!:0:--~1~5--~20
Output Voltage Change (VI

0'~75

...

Is/
~

~~ ~

~

50~~--~~----~------~

0"1.......----~10!"'""--~1~OO!"'""----1~OOO
Closed-loop Gain (VN I = 1 + RF/RIN

11-103

-SO -25

o +25 +50 +75 +100+125
Temperature (CCI

30 OUTPUT VOLTAGE VS OUTPUT CURRENT

1.

2

OPEN,LOOP GAIN AND QUIESCENT
CURRENT VS TEMPERATURE

'0

i

1.2

.1

:;

> 15
01

-

.0

-'

O~ Vee = 15
5

o

G=-10VN

','

25

"20
E

BANDWIDTH·

1.4

Vee-±12

50

100

150

200

250

10

10

~

r"AV~

o.9
.8

300 0 -75 -50

Output Current (mA I

~

0

"'-

+25 +50 +75 +100 +125

Temperature I·C I

"""'- ~

~

~

-25

'.

~

~

~

:0.8

0'~75

-50

-25

0

""'

+25, +50, H5 +100 +125

TamperBture (·C I

8. APPLICATIONS INFORMATION
8.1 Wiring_precautions. The OPA600 is a wideband, high frequency operational amplifier with a gain-bandwidth
product exceeding 5GHz. This capability can be realized by observing a few wiring precautions and using high frequency
layout techniques. Of all the wiring precautions, grounding is the most important and is described in detail in the next
section.
In general, all printed circuit board conductors should be wide to provide low resistance, low impedance signal paths and
should be as short as possible. The entire physical circuit should be as small as is practical. S~raycapacitances should be
minimized, especially at high impedanc,e nodes, such as the input terminals bfthe amplifier and compensation pins. Stray
signal coupling from the output to the inputshould be minimized. All circuit element/eads should be as short as possible
and low values of resistance should be used. This will give the best circuit performance: as it will minimize the time
constants formed with the circuit.capacitances and will eliminate stray, unwamed tuned circuits.
8.2 Grounding. Grounding is the most important applications consideration for the OPA600, as it i,s with all high
frequency 'circuits. Ultra-high frequency transisters are used in the design of the OPA600 and oscillations at
frequencies of 500M Hz and above can be stimulated if good grounding techniques are not used. A ground plane is highly
,recommended. It should connect all areas of the pattern side of the printed circuit that are not otherwise used. The
ground plane provides a low resistance, low inductance common return path for all signal and power returns. The ground
plane also reduces stray signal pickUp. It eliminates parasitic circuits from what would otherwise be long, component
leads.
'.
.
,
,
Point-to-point wiring is not recommended. However, if poil\t-to-point wiririg is used, a single-point ground should be
used. The input signal return, the load signal return and the power supply cominon should all be connected at the same
physical point. This eliminates common current paths or ground loops which can cause unwaQted fe,edback.
Each power supply lead should be bypassed to ground as near as p()ssible to the amplifier pins. A I~F CSI3 tantalum
capacitor is recommended. A parallel 0.0 I~ F ceramic may be added if desired. This is especially important When driving
high current loads. Properly bypassed and modulation free power supply lines allow full amplifier output and optimum
settling time performance.
'
OPA600 circuit common is conn,ected to pins I and'13; these pins should be connected to the ground plane. The input
signal return, load return, and power supply common should also be connected to the ground plane.
The case of the OP A600 is internally 'Connected to circuit common, and as indicated above, pins I and 13 should be
connected to the ground plane. Ideally ,the case should be mechanically connected to the ground plane for good thermal
transfer but becailse this is, difficult in,practice, the OP A600 should be fully i,nserted into the printed circuit board with
the case very close to the ground' plane to make the best possible thermal conriection. If the case and ground plane are
physically connected or are in close thermal proximity, the ground plane will provide heat sinking which will reduce the
case temperature rise. The minimum 01>..\600 pin length will minimize lead inductance, thereby maximizing
performance.
'
To repeat, proper grounding is the single most important aspect of high.frequency circuitry.
8.3 Compensation. The OPA600 uses ,externalfrequency compensation so that the user may optimize the bandwidth or
settling time for his particular application. Sevt:ral performance curves aid in the selection ofthe correct compensations
capacitance value. The Bode plot shows amplitude and phase versus frequency for several values of compensation. A

11-104

related curve shows the recommended compensation capacitance versus closed-loop gain.
Figure 4 shows a recommended circuit schematic. Component values and compensation for amplifiers with several
different closed-loop gains are shown. This circuit will yield the specified settling time. Because each device is unique and
slightly different, as is each user's circuit, optimum settli'ng time will be achieved by individually compensating each
device in its own circuit, if desired. A 10% to 20% improvement in settling time has been experienced from the values
'
indicated in TableI . '
The primary compensation capacitors are C, and C, (see Figure 4). They are connected between pins 4 and S and between
pins II and 14. Both C, and C2 should be the same value. As Figure 4 and the performance curves show, larger
closed-loop configurations require'lesscapacitance and improved gain-bandwidth product can be realized. Note that no
compensation capacitor is required for closed-loop gains equal to or above 100V / V. If upon initial application the user's
circuit is unstable, and remains so after checking for proper bypassing, grounding, etc., it may be necessary to increase
the compensation slightly to eliminate oscillations. Do not over compensate. It should not be necessary to increase C,
and C, beyond 10pF to ISpF. It m~y also be necessary to individually optimize C, and C, for improved performance.
The flat high frequency response of the OPA600 is preserved and high frequency peaking is minimized by connecting a
small capacitor in parallel with the feedback resistor (see Figure 4). This capacitor compensates for the closed-loop, high
frequency, transfer function zero that results from the time constant formed by the input capacitance of the amplifier,
typically 2pF, and the input and feedback resistors. The selected compensation capacitor may be a trimmer, a fixed
capacitor or a planned PC board capacitance. The capacitance value is strongly dependent on circuit layout and
closed-loop gain. It will typically be 2pF for a clean layout using low resistances (I kO) and up to IOpFfor circuits using
larger resistances. Using small resistor values will preserve the phase margin and avoid peaking by keeping the break
frequency of this zero sufficiently high. When high closed-loop gains are required, a three-resistorattenuator is
recommended to avoid using a large value resistor with its long time constant.
For heavy capacitive.ioads, greater than SOpF, refer to the section on capacitive loads, paragraph 8.6. For particularly
difficult applications where the wiring layout may not be the best or where there may be 1000pF loads, parasitics, strays,
long lead lengths, changing capacitive loads, etc., doublet compensation is recommended. This is discussed in paragraph
8.12 and is shown in Figure 9. This circuit offers increased stability at the expense of increasing the settling time by
approximately SO%. Also, this circuit is especially useful for functional testing at low frequency and incoming inspection.
8.4 Settling time. Settling time is defined as the total time required, from the input signal step, for the output to settle to
within the specified error band around the final value. This error band is expressed as a percentage of the magnitude of
the output transition.
Settling time is a complete dynamic measure of the OPA600's total performance. It includes the slew rate time, a large
signal dynamic parameter, and the time to accurately reach the final value, a small signal parameter that is a function of
bandwidth and open-loop gain. Performance curves show the OPA600 settling time to ± I%, ±O.I %. and ±O.O I%. The
best settling time is achieved in low closed-loop gain circuits.
Settling time is dependent upon compensation. Under-compensation will result in small phase margin, overshoot or
instability. Over-compensation will result in poor settling time. Refer to paragraph 8.3.
Figure 4 shows the recommended compensation to yield the specifiel:l settling tine. Improved or optimum settling time
may be achieved by individually compensating each device in the user's circuit since individual devices vary slightly from
one to another as do user's circuits.
8.S Slew rate. Slew rate is primarily an output, large signal parameter. It has virtually no-dependence upon the
closed-loop gain or the small signal bandwidth. Slew rate'is dependent upon compensation and decreasing the
compensation capacitor value will increase the available slew rate as shown in the performance curve.
8.6 Capacitive loads. The OPA600 will drive large capacitive loads (up to 100pF) when properly compensated and
settling times of under ISOnsec are achievable. The effect of a capacitive load is to decrease the phase margin of the
amplifier which may cause high frequency peaking or oscillations. A solution is to increase the compensation
capacitance, somewhat slowing the amplifier's ability to respond. The recommended compensation capacitance value as
a function of load capacitance is shown in Figure 7. (Use two capacitors, each with the value indicated.} Alternately,
without increasing the OPA600's compensation capacitance, the capacitive load may be buffered by connecting a small
'
resistance, usually sn to son, in series with the Output, pin 8.
For very-large capacitive loads, greater than IOOpF, it will be necessary to use doublet compensation. Refer to Figure 9
and paragraph 8.12. This places the dominant pole at the input stage. Settling time will be approximately SO% slower;
slew rate should increase. Load capacitance should be minimized for optimum high frequency performance.
Because of its large output capllbility, the OPA600 is particularly well suited for driving loads via coaxial cables. Note
that the capacitance of coaxial cable (29pF / foot of length-for RG-S8) will not load the amplifier when the coaxial-cable
or transmission line is terminated in its characteristic impedance.

11-105

125r----r----r----.---,----'2~

150

Ii

;::
1---+-==..:.+--II~l-+--I1100 .~
.

~

1---+---t-#---'i--+-'---l150

,Compensation Capacitance (pF)

FIGURE 7. Capaciliv~ Load Compensation and Response;
8.7 Offset voltage adjustment. The offset voltage of the OPA600 may be adjusted to zero by connecting a SkU resistor in
series with a IOk!l linear potentiometer in sc(ies with another SkU resistor between pins 2 and 15, as shown in Figure~. It
is important that o,ne end of each of t~e two resistors be located very cl.ose to pins 2 and 15, to isolate and avoid loading
these sensitive terminals. The potentiometer should be ,a small, noninductive type with the wiper conriected to the
positive supply. The leads connecting these \:ompom:nts should be,short, no longer than 0.5-inch, to avoid stray
capacitance and stray signal pick-up. If the potentiometer must be located away from the immediate vicinity or'the
OPA600, extrell1;e care must be observedwith t~e sensitive leads. Locate the two 5kn resistors verycIose to pins 2 and 15.
Never connect +Vcc directly to pin2 or IS, Do not attempt to elimini\te the 5kn resistors because at extreme rotation,
,the potentiometer will directly connect +Vccto pin 2 or pin 15 and permanent damage will result.
Offset voltage adjustment is optional. The potentiometer and two resistors are omitted when the offset voltage is
considered sufficiehtly low for the particular application. For each microvolt of offset voltage adjusted, the offset voltage
temperature ~ensitivity will change by ±O.004j.1 V j"c.
8.8 Current boost. External' ability to bypass the internal current limiting resistors has been provided inthe OPA600.
This is referred to as current boost. Current boost enables the OPA600 to deliver large curren.ts into heavy loads
(±700mA at ±,IOV). To bypass the resistors and ac~ivate the current boost, connect pin 7 to-Vec.at pin 6 with a short lead
to,minimize lead ,iOl:juctance and connect pin 9 to +Vcc at pin 1.2 with a short lead.
CA UTION -' Activating current boost by bypassing the iriternal current limiting resistors can permanently damage the
OPA600 under fault conditions. See paragraph 8.9.
Not activating,current bOOst is especially useful for initial breadboarding. The son (±5%) current limiting resistor in the
collector circuit of each of tne' output transistors, causes the output transistors to saturate; this limits the power
dissipation in the outPllt stage incase of a [a u 1,1. Operating with the current boost not activated may also be desirable with
small-signal outputs (i.e.±1 V) or When the load current is sl,Ilall.
Each resistor IS internally capacitively-bypassed (O.Olj.lF, ±20%) to allow the amplifier to deliver large pulses of current,
such as to !;hargf! diodf:junctions or circuit capacitances and still respond quickly. The length of timethanhe OPA600
can deliver these, CUHent pulses is limited by the RCtime constant.
'
'
The internal voltage drops, output voltage available, power dissipation, and maximum output current can be determined
for the,user's' application by knowing the load resi~tance and computing:
,

RLOAD

,
VOliJ=14(SO+R
)
, "
.
LOAD
This'applies for RLOAh less than loon and the current boost not aCtivated. When R WAJ) is large, the peltk output voltage
istypicalfy ±i IV, which is determined by otherfactors within the OPA600.
. .

, 8:9Short,circuit p'rotection. The QPA600 is a sho~-circ~it-protected for momentllTy short to common «5sec), typical
ofthose encountered when probing a circuit during experimental breadboarding or troubleshooting. This is true only if
pins 7 and 9 are open (current boostnot activated). An inter~al50n resistor is in series with the coUel;tor'of each of the
output transistors whicH under fault coiidftiohs will cause the output transistors to saturate' aild iimit the power
dissipation irithe Qutput stage. Extended application Man output short can damage the amplifier due to excessive power'
dissipation. _ . .
. ',
.
The OPA600 is'nOt short-circuit-protected when the current boost is activated. The large output current capability of the
OP A 600 wili'cause excessive powerdissipatiol1 arid permanentdama~e will result even for momentary shorts to ground.
Output shorts to either supply will generally destroy th~ OP A600 whether the current boost is activated 'or not.
:

,

\

8.10 Heat sinking and power dissipation. The OPA600 is intended as a printed Circuit board mounted device and assuch,
does not require a heat sink. It is specified for ambient temperature operation from -55"C to + I25"C. However, the power
dissipation must be kept within safe limits. At extreme temperature and under full load conditions, some formof heat
sinking will be necessary. The use of a hea~ sink, or other heat dissipating means such as proximity to the ground plane,
will result in cooler operating temperatures, better temperature performance, and improved reliability.
The thermal model used to describe the OP'A600 is more complete than is usual for operational amplifiers. The thermal
resistances for the output stages have been separated frpm the thermal resistrance for the balance of the OPA600. For
most monolithic op amps and hybrids, thermal properties are usually represented by one thermal resistance,OJC; and in
general, that is fairly accurate because the total power dissipation is low and the heat that is generated is in one area. For
packaged power transistors, thermal properties are also accurately represented by one thermal resistance, OJC; all the
power is dissipated in one point source. The OPA600 op amp however, has a large power handling capability and large
power dissipations occur in different locations within the amplifier under differing load conditions,
The total power dissipation within the OPA600 is the sum of all the individual sources of dissipation. By making some
simplifying assumptions and neglecting second order effects, the dissipations are grouped into three sources - quiescent
power, NPN output transistor power, and PN P,output transistor power. Using the thermal model shown in Figure 8 and
the absolute maximum junction temperature rating (derate the maximum, if desired) and solving the Thevenin
equivalent simultaneous equations that result, the user can determine junction. internal substrate, and case
temperatures. It will be apparent that the output stages contribute significantly to the thermal rise. Under light loading.
the requirements to dissipate the generated heat are much less than the requirements to dissipate heat under full load
conditions at a maximum temperature, Using this expanded thermal information allows the user to safely apply the
OPA600.
.

TJN

r~
I
1

TJp

Be =35DC/W

85=I.7DC/W

84 = IZOC/W

, 81 = 32°C/W

~:~r.
TJO

I

~

II 1I
TA

TC

TJN = Junction temperature of NPN output transistor.
TIp' = Junction temperature of PNP output transistor.
TIQ = Worst case temperature of any device in the
balance of the amplifier.
Tc = Case'temperature.
TA = Ambient temperature.
OJ, 0, = Thermal resistance, output transistors.
03,04 = Thermal resistance, substrate.
0,
= Thermal resistance, substrate attach and package.
06
= Thermal resistance, case to ambient.
PN = Worst case power dissipation in the NPN output
transistor.
Pp
= Worst case power dissipation in the PNP output
transistor.
PQ
= Quiescent power dissipation.
FIGURE 8. OPA600 Thermal ,Model.

Below are two examples of using the thermal model.
I. Find the worst case internal junction temperature rise above ambient.
PQ = I W
Conditions:
PN= Pp=O.1 W
no heatsink

11-107

:::!
:IE

§c

a..
=

TiN == 80.7PN+ 48.7Pp + 36.7PQ + TA
TIN - T A= 49.6°C
as PN:, Pp
TIP - T A= 49.6°C
T'Q= 49.6PQ + 36.7PN + 36.7Pp + TA
TIQ - TA = 57"C
Answer:
57°C
2. Find the maximum output stage power dissipation allowed with a maximum case temperature of +125"C and not
exceeding the ma,ximum junction temperature of + I 75"C.
Conditions:
PQ = I Watt
PN= Pp
Solution:

32

Solution:

+115"C

Answer:.

1.7,

y.t;j)
T
l

Checking T'Q:

12

1

N

17501
+

TIN = PN 32 + (PN+ Pp)12 + (PN + Pp) 1.7 + PQ 1.7 + Tc
175 = 59.4 PN + 1.7 + 125
PN=0.813W
T'Q'= (I) 12.9 + (2x 0.813 + I) I. 7 + 125
TIQ = 142°C (i.e. < 175°C)
0.813W may be dissipated in each output transistor.

It may be necessary to physically connect the OP A600 to the printed circuit board ground plane, attach fins, tabs, etc" to
dissipate the generated heat. Because ofthe wide viuiety qfpossibilities, this task is left to the user. For all applications it
is recommended that the OPA600 be fully inserted into the printed circuit board and that the pin length be short. Heat
will be dissipated through the ground plane and the AC performance will be. its best. See paragraphs 8.1 and 8.2
8.11 Testing. For static and low frequency dynamic measurements, the OPA600 may be tested in conventional
operational 'amplifier test circuits, provided proper grounding techniques are observed, excessive lead lengths are
avoided, and care is maintained to avoid parasitic oscillations. See the above sections, especially paragraphs 8.lan9 8.2.
The circuit in Figure 9 is recommended for low frequency functional testing, incoming inspection, etc. This circuit is less
susceptible to stray capacitance, excessive lead length, parasitic tuned circuits, changing capacitive loads, etc. It does not
yield optimum settling time. We recommend placing a resistor (approximately 3000) in series with each piece of test
equipment, such as a DVM, to isolate loading effects on the OPA600.
To realize the full performance capabilities of the OPA600, high frequency techniques must be employed and the test
fixture must not limit the amplifier. Settling time is tht; most critical dynamic test and Figure IO shows a recommended
OPA600 settling time test circuit schematic. Good grounding, truly square drive signals, minimum stray coupling, and
small physical size are important.
The input pulse generator must have a flat topped, fast settling pulse to measure the true settling time of the amplifier. A
circuit that generates a ±5V flat topped pulse is shown in Figure II.
Every OPA600 is thoroughly tested prior to shipment assuring the user that all parameters equal or exceed their
specifications.

FIGURE 9. Amplifier Circuit for Increased Stability.

11-108

1.21 HP2835

+ISVDC

~
..L

'61911

+ ,Blgn

...

INPUT = "SV
OUTPUT = "SV
ERROR OUTPUT ·ll.5mV I .0.01 '!oJ
61911
'0.0211 MATCHEO
"WIlli C. + C. = 3.3pF typical, C, opUmlzad IIII'
clrculll.youL and RL = 500. Is < 160nIIC.

·15VDC

FIGURE 10. Settling Time and Slew Rate Test Circuit.
+15VDC

~#~
+ISVDC ~.
B4011

INPUT =TTL
OUTPUT = rliV

'ALHN39GB
2N2907

10#F

..r::-1'::"

100

~

15f!

~-

+15VOC

=

·15VDC

FIGURE II. Flat Top Pulse Generator.
8.12 Increased Slew Rate. The OPA600 slew rate may be increased by using an alternate compensation shown in Figure
9. The slew rate will increase between 700 and 800V i!-,sec typical with 0.0 I% settling time increasing to between 175and
190nsec typical and 0.1 % settling time increasing to between I IO and 120nsec typical.
For alternate doublet compensation refer to Figure 9. For a closed-loop gain equal-I. delete C I and C2 and add a series
RC circuit (R =220, C =O.OOI!-,F) between pins 14 and 4. Make no connections to pins II and 5. Absolutely minimize
the capacitance to these pins. If a connector is used for the OPA600, it is recommended that sockets for pins II and 5 be
removed. For a PC board mount, it is recommend'ed that the PC board holes be overdrilled for pins II and 5 and adjacent
ground plane copper be removed. Effectively this compensation places the dominant pole at the input stage, allowing the
output stage to have no compensation and to slew as fast as possible. Bandwidth and settling time are impaired only
slightly. For closed-loop gains other than -I, different values of Rand C may be required.
I

11-109

BURR-BROWN®

·IElI5II

OPA8780/MIL SERIES
MODEL NUMBERS:
OPA8780VM/MIL *
OPA8780VM/883B
OPA8780VM

OPA8780UM/883B
OPA8780UM
REVISIO"" NONE
DECEMBER, 1983

High Voltage
OPERATIONAL AMPLIFIER

FEATURES

APPLICATIONS

• HIGH OUTPUT SWING. ±30V

• LARGE SIGNAL DRIVERS

• LARGE LOAD CURRENT. ±60mA

• HIGH POWER AUDIO AMPLIFIER

• DIFFICULT TO DAMAGE. automatic thermal shutoff
• REDUCES SOURCE LOADING. 100Gn input Impedance
• PRESERVES SYSTEM ACCURACY;l06db CMR.
20pA bias current
'
• FAST SLEWING. 15V/J.!Sec

DESCRIPTION
The OPA8780 is the first lI).ilitary version integrated
circuit operational amplifier that provides high output swings up to ±30V. The monolithic FET input
stage has low bias current (20pA) which minimizes
the offset voltage caused by the bias current and the
large resistance normally associated with high voltage
circuits.
The OPA8780 is packaged in a TO-3 package which

will dissipate over 3W of power without a heat sink
and 4.5W with a 'suitable heat s·ink.
The input stage is protected against overvoltage and
the output stage is protected against short-circuits to
ground. A special thermal sensing circuit prevents
damage to the amplifier by automatically shutting
the amplifier down when too much power is \>eing
dissipated.

*Available 3rd quarter 1984

Intemltlonll Airport Industrial Park· P.O. Box 11400· Tucaon. Arizona 85734· Tel. (602) 74fi.l111 . Twx: 910-952·1111 • Cable: BBRCORp· Talax: 66.fi49t

11-110

DETAILED SPECIFICATION
MICROCIRCUITS, LINEAR
OPERATIONAL AMPLIFIER
MONOLITHIC, SILICON
I. SCOPE
1.1 Scope. This specification covers the detail requirements for a very-high accuracy, operational amplifier.
1.2 Part number. The complete part number is as shown below.

OPA8780

I
Basic model
number

v

M

IMIL

l
Grade

--L
Package

(see 1.2.1)

(see 1.2.3)

T

Hi-ReI product
designator (see 1.2.2)

1.2.1 Device type. The device is a single operational amplifier. Two electrical performance grades are provided: the V
grade (-55°C to +125°C) and U grade (-25°C to +85°C). The electrical performance characteristics are shown in
Table I.
1.2.2 Device class. The device class is similar to the class B product assurance level as defined in MIL-M-38510. The
Hi-ReI product designator portion of the part number distinguishes the product assurance levels available as follows:
Hi-ReI Product
Designator

1MIL
1883B
(none)

Requirements
Standard model plus 100% MIL-STD-883 class B screening, with 10% PDA, plus quality
conformance inspection (QCI) consisting of Groups A and B performed on each inspection lot,
plus Groups C and D performed initially and periodically thereafter.
Standard model, plus 100% MIL-STD-883 Class B screening.
Standard model including 100% electrical testing.

1.2.3 Case outline; The case outline is an 8-pin TO-3 package. Figure I depicts the case outline for the package.
1.2.4 Absolute maximum ratings.
Supply voltage range
Input voltage range
Internal power dissipation
Case storage temperature range
-Lead temperature (soldering, 60 sec.)

±35VDC
[±(Vcc)-5]
4.5W with heat sink
-55°C to +150o C
300°C

1.2.5 Recommended operating conditions.
Suppiy voltage range
Case temperature range

±15VDC to ±35VDC
-55°C to +125°C

1.2.6 Power and thermal characteristics.
Case
outline

Maximum allowable
power dissipation

Maximum

Package
8-lead CAN

Figure I

4.SW with heat sink
at Tc +25°C

IO°CjW
with heat sink

11-111

OJ-C

2. APP,LICABLE DOCUMENTS
2.1 The following documents form a part .of this specification to the extent specified herein.
SPECIFICATION
MILITARY
MIL-M-38510-Microcircuits, general specification for.
STANDARD
MILITARY
MIL-STD-883-Test methods and procedures for microcircuits.
3. REQUIREMENTS
,3.1. General. Burr-Brown uses production and test facilities and a quality and reliability assurance program adequate
to ass\lre successful compliance with this specification.
3.1.1 Detail specifications. The, individual item requirements are specified herein. In the event of conflicting
,requirements the order of precedence will be the purchase order, this specification, and then the reference documents.
3.1.2 Country of manufacture. These microcircuits are manufactured, assembled, and tested within the United States
of America.
3.2 Design, construction, and physical dimensions.
3.2.1 Package, metals, and other materials. The packages, metal surfaces, and other materials are in accordance with
MIL~M-38510.

NOTE,
Le.ds in true position within .010"
, (.25mm) R 0 MMC .~ seating plane.
Pin numb,rs shown for reference only.
Numbers may nO~.be marked on package.

INCHES
DIM

Q

MILLIMETERS

MIN

MAX

MIN

MAX

A

1.510

1.550

38.35

39.37

B

.745

.770

lB.92

19.56

C

.300

.400

7.62

10.16

0

.03B

.042

0.97

1.07

E

.080

.105

2.03

2.67

F

40° BASIC

400 BASIC

G

.500 BASIC
1.186 BASIC

12.7 BASIC
30.12 BASIC

J

.583 BASIC

15.06 BASIC

K

.400

Q

.151

R

.980

H

I
I

.500

10.16

.161

3.84

I
I

1.020

24.89

I

12.70
4.09
25.91

FIGURE 1. Case Outline (TO-3) Package Configuration.

3.2.2 Design documentation. The design documentation is in accordance with MIL-M-38510.
3.2.3 Internal conductors and internal lead wires. The internal conductors and internal lead wires are in accordimce
with MIL-M-38510.
3.2.4 Lead material and finish. The lead material and finish is in accordance with MIL-M-38510and is solderable per
MIL-STD-883, method 2003.
3.2.5 Die thickness. The die thickness is in accordance with MIL-M-38510.
3.2.6 Physical dimensions. The physical dimensions are in accordance with paragrpah 1.2.3 herein.
3.2.7 Circuit diagram and terminal connections. The circuit diagram and terminal connections for the TO-3 package
are shown in Figure 2.
3.2.8 Glassivation. The microcircuit die is glassivated;
3.2.9 Schematics circuit. A simplified schematic circuit is shown in Figure 3.

1l-.tl2

OPTIONAL OFFSET
ADJUST

1------'
OFFSET
I
I TRIM
I

TO +Vcc

--...f an
I
IL _ _

OFFSET
TRIM

-Vee
(TOP VIEW)

FIGURE 2. Connection Diagram.

+vcc
OFFSET
TRIM
OFFSET
TRIM

-IN
+IN

-Vee

7}---------~--~--4---~~--~~------------------~----~----------~

FIGURE 3. Simplified Schematic.

3.3 Electrical performance characteristics. The electrical performance characteristics are specified in Table I and apply
over the full operating ambient temperature range of -550 C to +1250 C unless otherwise specified.
3.3.1 Additional electrical performance characteristics. Additional electrical performance curves are shown in
paragraph 7.
3.3.2 Offset null. The amplifier is .capable of being nulled to zero offset voltage using the circuit in Figure 2. If nulling
is unnecessary delete the potentiometer and m~e no connections.

11-113

TABLE 1. Electrical Performance Characteristics.

- -

All characteristics from -SS·C < Tc < +125·C ±Vee = 35VDC unless otherwise noted
'OPA8780VM/MIL
OPA8780VM/883B
OPA8780VM

.'

CHARACTERISTICS

CONDITIONS

TYP

MIN

OPA8780UM/883B
OPA8780UM
MAX

POWER SUPPLY

Voltage ±Vcc
Quiescent Current

±IS
Tc= +2S·C

±35
±10

"

RATED OUTPUT

Voltage (Vo)
Current
Current, Short Circuit

Tc= +25°C
Tc:= +25°C

±10
±80
'±70

±30

MIN

TYP

MAX

.

V
mA

.

V
mA
mA
nF

±200
10

Load Capacitance

UNITS

OPEN LOOP GAIN

No Load, DC
Rated Load, DC

106
Tc = +2S·C

90

Smail Signal

5

dB
dB

FREQUENCY RESPONSE

Unity Gain Bandwidth
Full Power Bandwidth
SlewRate

Settling Time

MHz
kHz
V/iJSeC
V/ps.c
V/JJSec
V/JJSec
V/JJSec
JJSec

100
Tc= +25·C
Tc= -25·C
Tc = -55·C
Tc= +85·C
Tc= +12S·C
0.1%

15
10

20

12
12
12
6
12

9
10

4

·

INPUT OFFSET VOLTAGE

Initial

±1

Tc= +2S·C
Tc= -55·Cto +125·C
Tc=-25·Cto+85·C

Drift vs Temperature
Drift .s Supply Voltage

±10
±15
±IS
~

·

100
100

Drift vs Time

50

mV
mV
mV
pV/·C
pVN
pV/mo

INPUT BIAS CURRENT

Initial

Tc=+25·C

Drift va Temperature
Drift va Supply Voltage

.I.

pA

,). ±20
±50
Dou1bles every It" C
0.5

PA!.V

INPUT OFFSET CURRENT
Initial

·

L

.L

Tc:;:;. +25°C

±20
Dou1bles every I o'·C
0.5

Drift VB Temperature
Drift .s Supply Voltage

l

pA
pAN

. INPUT IMPEDANCE
100
100

Differential

Common Mode

GO
GO

INPUT NOISE
Voltage
Current

O.OIHz to 10Hz p-p
10Hz to 1000Hz rms
0.1 Hz to 10Hz p-p

·

5
1
1

pV
pV
pA

INPUT VOLTAGE RANGE

Max Safe Differential Voltage

+Vcc + I-Veel

V

Max Safe Common-Mode Voltage

+Vcc:to-Vcc

V

1±(IV:~'-8)1

Common-Mode Voltage. Linear Operation

Common-Mode Releetion

V
dB

TEMPERATURE RANGE [CASE]

Operating
Storage
Specification

-55
-55
-55

11-114

+125
+150
+125

.
-25

.
+85

·C
·C
·C

TABLE II. Electrical Test Requirements.
(The individual tests within the subgroups appear in Table III).

MIL·STD-883 TEST REQUIREMENTS (Hybrid Class)

OPA8780VM/MIL

Interim electrical parameters (preburn~in) (method 5008)
Final electrical test parameters (method 5008)
Group A test requirements (method 5008)
Group C end pOint electrical parameters (method 5008)

OPA8780VM/883B
OPA8780VM

OPA8780UM/883B
OPA8780UM

1
1,2,3.4
1,2.3.4

1
1. 2U, 3U. 4
1,'2U, 3U, 4

1
1,2.3,4
1'.2,3,4
Table IV limits

-

-

and delta limits

'PDA applies to subgroup 1 (see 4.3.c)

TABLE III. Group A Inspection.
LIMITS
OPA8780VM/MIL
OPA8780VM/883B
OPA8780VM
SUBGROUP
4
2

PARAMETERS

15

Initial Input Offset Voltage

To :+125'C
T,: +125'C, R,: 5000

4

Slew Rate

Tc = +85°C
Tc = +85°C, Rl:;;: 5000

10

3

Initial Inpui Offset Voltage
Slew Rate

To: -55'C
T, = -55'C, R, = 500n

9

3U

Initial Input Offset Voltage

T c =-25°C
T, = +25'C, R, = 5000

10

Initial Input Offset Voltage

Slew Rate

1

"Initial Input Offset Voltage
Quiescent Current
Initial Bias Current

Open'Loop Gain
Slew Rate
Short-Circuit Current

MAX

MIN

To: +25'C
T,: +25'C, R,: SOOO

Slew Rate

2U

CONDITIONS

Initial Input Offset Voltage
Slew Rate

Tc=+25°C
To: +25'C
To= +25'C
T, = +25'C, R, = 5000
T, = +25'C. R, = 5000
To = +25'C, Rae = 100

OPA8780UM/883B
OPA8780UM

90
15
±70

MIN

MAX

UNITS

±10

mV
V/ps.c

±15

mV
Vlps.c

±15

mV
Vlps.c

±15

mV
Vlpsec

±15

mV
VIllsec

±10
±10
±50

mV
mA
pA
dB
Vlpsec
mA

±200

..

·Speclflcatlon IS the same as for the V 9r899.

TABLE IV: Group C, End Point Electrical Parameters
(Tc

= +25°C, ±Vcc = ±35VDC)

TEST
Quiescent Current

Input Offset Voltage
Slew Rate
Open~Loop Gain
Short Circuit Curren~
Bias Current

LIMIT

DELTA

±10
±10
15
90
±200
-50

±3
±5
±5
±10
±25
±25

UNITS
mA
mV

Vlps"c
dB
mA
pA

.

3.3.3 Frequency compensation: No frequency compensation is required. The amplifier is free of oscillation when
'
operated iIi any gain and when operated in ariy test condition specified herein.
3.4 Electrical tests. Electrical tests are shown in Table II. The subgroups of Table III and limits of Table IV, which
constitute the minimum electrical tests for screening, qualification, and quality conformance, are shown in Table II.
3.5 Marking. Marking is in accordance with MIL-M-385IO. The following marking is placed on each microcircuit as a
minimum.
a. Part number (see paragraph 1.2)
.b. Inspectio'ri lot identification code li,
•
aURR·BROWNe
c. Manufacturer's identification (I e:.e:. I)
d. Manufacturer's designating symbol (CEBS)
e. Country of origin (U.S.A.)
3.6 Workmanship. These microcircuits are manufactured, processed, and tested in a workmanlike. manner. Workmanship is in accordance with good engineering practices, workmanlike instructions, inspection and test procedures, and
training, prepared in fulfillment.of Burr-Brown's product assurance program.
11 A 4-digit date code, indicating year and week of seal. and a 4- or 5-digit lot identifier is marked on each unit.

11-115

3.6.1 Rework provIsions. Rework provisions, including, rebonding for the !MIL prOduct designation, are in
accordance with MIL-M-38510.
3.7 Traceability. Traceability for the! MIL product desigtlation is in accordance with MIL-M-38!i10. Each microcircuit
is traceable to the producti\>n lot and to the component vendor's component lot.< '
3.8 Product, and process change. Burr-Brown will not Implement any major change, to the desigtl, materials,
construction, or manufacturing process which may affect the performance, quality or interchangeability of the
microcircuit without full or partial requalification.
3.9 Screening. Screening for !MIL and/883B Hi-Rei product designations is in accordance with MIL-STD-883,
method 5008, class B, except as modified in paragraph 4.3 herein.
Screening for the standard model includes QC4118 internal visual inspection, stabilization bake, fine leak, gross leak,
burn~in (72 hours performed preseal), constant acceleration (condition A), temperature cycle (condition C), and
external visual per MIL-STD-883,methOd 2009.
For the! MIL product designations, all microcircuits will have passed the screening requirements prior to qualification
or quality conformance inspection.
3.10 Qualification. :Qualification is not required. See paragraph 4.2 herein.
3.11 Quality conformance inspection. Quality conformance inspection, for the !MIL product designation, is in
accordance with MIL-M-3851O, except as modified in paragraph 4.4 herein. The microcircuit inspection lot will have
passed quality conformance inspection prior to microcircuit delivery.
4. PRODUCT ASSURANCE PROVISIONS
4.1 Sampling and inspection. Sampling and inspection procedures are in accordance with MIL-M-38510 and MILSTD-883, method 5008, except as modified herein.
4.2 Qualification. Qualification is not required unle,ss specifically required by contract or purchase order. When so
required, qualification will be in accordance with the inspection routine of MIL-M-38510, paragraph 4.4.2. The
inspections to ):)e performed are those specified herein for groups A, B, C and D inspections (see paragraphs 4.4.1, 4.4.2,
4.4.3, and 4.4.4).
Burr-Brown has perf,ormed and successfully completed qualification inspection as described above. The most recent
report is available from Burr-Brown.
4.3 Screening. Screening for the! MIL and! 883B Hi-Rei product designations is in accordance with MIL-STD-883,
method 5008, class B, and is conducted on all devices. The following criteria apply:
a. Interim and final test parameters are specified in Table II.
b. Burn-in test (MIL-STD-883, method 1015) 'conditions:
(I) Test condition B
'
(2) Test circuit is Figure 4 herein
(3) TA = +125°C minimum
(4) Test duration is 160 hours minimum
c. Percent defective allowable (PDA). The PDA, for !MIL product designation only, is 10 percent and includes
both parametric and catastrophic failures. It is' based on failutes from group A, subgroup I test, after
cool-down as final electrical test in accordance with MIL-STD-883, method 5008, and with no intervening
electrical measurements. If interim electrical parameteI: tests are performed prior to burn-in, failures
resulting from preburn-in screening failures may be excluded from the PDA. If interim electrical parameter
tests are omitted, all screening failures shaH be included in the PDA: The verified failures of group A,
subgroup I,after burn-in are used to determine the percent defective for each manufacturing lot, and the lot
is accepted or rejected based on the PDA.
d. External visual inspection need not include measurement of case and lead dimensions.
4.4 Quality conformance inspection. Groups A and B inspections of MIL-STD-883, method 5008, are perfor,niedon
each inspection lot. Groups C and D inspections of MIL-STD-883, method 50(}8, are not required unless,specified by
contract or purchase order.
' "
'
,

,

Burr-Brown periodically performs groups C and D inspections of MIL-STD-883, method 5008. A report of the most
recent groups C and D inspections is available form Burr-Brown.
'
4.4.1 Group A inspection. Group A inspection consists of.the test subgroups and LTPD values shown in MIL-STD883, method 5008, and as specified in Table II herein.
.
4.4.2 Group B inspection. Group B jnspection consists of the test subgroups and LTPD vlilues shown in MIL-STD883, method 5008 (class B).

+v

0.01""

FIGURE 4. Burn-In Circuit.

4.4.3 Group C inspection. Group C inspection consists of the test subgroups and LTPD values shown in MIL-STD883,/Ilethod 5008 (class B), and as follows:
a. Operating life test (MIL-STD-883, method 1005) conditions:
(I) Test condition B
(2) Test circuit is Figure 4 herein
(3) TA = +125°C minimum
(4) Test duration is 1000 hours minimum
b. End point electrical parameters are specified in Table II herein.
4.4.4 Group D inspection. Group D inspection consists of the test subgroups and LTPD values shown in MIL-STD883, method 5008 (class B) and as follows:
a. End point electrical parameters are specified in Table IV herein.
4.4.5 Inspection of packaging. Inspection of packaging shall be in accordance with MIL-M-38510.
4.5 Methods of examination and test. Methods of examination and test are specified in the appropriate tables.
Electrical test circuits are as prescribed herein or in the referenced test methods of MIL-STD-883.
4.5.1 Voltage and current. All voltage values given, except the input offset voltage (or differential voltage), are
referenced to the external zero reference level of the supply voltage. Currents given are conventit;mal current and
positive when flowing into the referenced terminal.
4.6 Inspe~tion of preparation for delivery. Inspection of preparation for delivery is in accordance with MIL-M-3g510,
except that the rough handling test does not apply.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-M-38510.
6. NOTES
6.1 ~ The notes specified in MIL-M-3851O are applicable to this specification.
6.2 Intended use. Microcircuits conforming to this specification are intended for use in applications where the use of
screened parts is required or desirable.
6.3 Ordering data. The. contract or purc'hase order should specify the following:
a. Complete part number (see paragraph 1.2).
b. Requirement for certificate of compliance, if desired.
6.4 Microcircuit group assignment. These microcircuits are assigned to Technology Group H as defined in MIL-M38510, Appendix E.
6.5 Electrostatic sensitivity. CAUTION-these microcircuits may be damaged by electrostatic discharge. Precautions
should be observed at all times.

11-117

7. ELECTRICAL PERFORMANCE CURVES
TCASE = +25° C and ±Vcc max unless otherwise noted.
OUTPUT VOLTAGE VS
FREQUENCY

CURRENT LIMIT VS
TEMPERATURE

SLEW RATE VS SUPPLY
AT FULL LOAD

VOLTA~E

+30
1.01-+-+-+-+-+--:.I--f

!
cr.

-

~·0.9t--+-+-.,..I:~ :"~~--1--I

Vcc= ±35V

......

o

0;

j

c

-40
-50 -25

f:

OPEN-LOOP GAIN VS SUPPLY
VOLTAGE AT MAX LOAD

i

iii'

:!!. -1

""',,-

~

!\.

I

1:1000

~

100

~~

10

:;
Q.

.5

1

)_

O. 1

Z~

~

v

/

)~

0.0I

.

E
~ 1000 1 - - r - - r - - 1 r - - 1 r - - t

-25

Q.

.5

Q.

:e{!.

.5

I
Amplifier
ShotN6ise

10

t

iii'110

:!!.
c

'1

:a

lOl=:j:::j::=t::::t=t=l
10

100 Ik 10k lOOk 1M
Frequency (Hz)

10'
10'
10'
Source Resistance (0)

:--...

90

cr"

'iD 70

30

~
50
Q.

"~

VJ

5
0
10k

..

•;0
'1

~±~V
lOOk
1M
Frequency (Hz)

11-118

3M

-

POWER SUPPLY REJECTION
\is FREQUENCY

VOLTAGE VS FREOUENCV

5

y

1 = 0.01 Hz.tQ 10Hz

MAXIMUM COMMON-MODE

;r90

150

Thermal Noise
of Source Resistor

100

10'

~"0
70
Vcc ±35V
150IIlIl!:I!!I!I!lIIII!II
50

75
100 125
Temperature (OC)

1

150

......

I

50

:;

COMMON-MODE REJECTION
VS FREQUENCY

~

~(I

I

Z

0 25 50 75 100 125
Temperature (OC)

130

~"'6

I 1000
.g

:;

\
\

~

.~
~

\

TOTAL LOW FREQUENCY INPUT
NOISE VS SOURCE RESISTANCE

TOTAL INPUT NOISE VOLTAGE
VS SOURCE RESISTANCE

,

75 100 125

I

BJAt 10jC/w

25

{!.

-50

1.0 I-

o

50 eo 70 eo 90 100 110
Power Supply ('II> 01 max)

!

0.001

"

:5 0.5

10 100 Ik 10k lOOk 1M 10M
FrequencY.(Hz)

NORMALIZED INPUT BIAS
CURRENT VS TEMPERATURE

d
.1III

r- 9~ = 10!C/w

4.0

.!!- 3.5
~ 3.0
.~
~ 2.5
~ 2.0
0m 1.5

"-

o

50

(Case)

c:

-20

25

MAXIMUM POWER DISSIPATION
-5.0
!4.5

"

0

Case Temperature (0 C)

"-

~60

,
~

Power Supply (% 01 max)

- -,

iii'

......

~-30

120

:!!. 80

I.......

E

~

OPEN-LOOP FREQUENCY
RESPONSE-FULL LOAD
100

8-10

~-20

100
1000
Frequency (kHz)

10

".... .......

:::; +10
1:
I!! 0
'0

~ 0.8

S-

l+2O
~

"""-

Negative Supply

P~sltl.e SUPPI;"'

'"

30

.......

10
10

100

lk
10k lOOk
Frequency (Hz)

1M

8. APPLICATION INFORMATION
8.1 Offset voltage adjustment. If offset adjustment is necessary this may be done as indicated in Figure 2, by adding a
lOOkO potentiometer between pins 3 and 4 with the center tap connected to +Vcc.
8.2 Case connection. The case is electrically isolated. It is recommended that the case be grounded during use.
8.3 Single supply operation. It may be desirable in some applications to operate the amplifiers from a single supply.
The circuit In Figure 5 illustrates a typical application.
Note that there are restrictions on the input and output voltages (el and eo) which are necessary in order to keep the
amplifier circuits operating in a linear manner.
It should also be noted that the OPA8780 is short-circuit limited, thermally protected, and protected from short circuits
to ground.

+7DV

...._--0+

FIGURE 5. Operation From a Single Supply.

11-119

+lOV s e, s +7DV

+ 5vslos+7UV

VFC32/MIL SERIES'

BURR-BROWN®

IElElI

MODEL NUMeERS:
VFC32WM/8838
VFC32VMIMIL
VFC32WM.
VFC32VM/8838
VFC32VM
VFC32UM/8838
VFC32UM
REVISION C
APRIL,1984

VOL TAGE-TO-FREQUENCY CONVERTER
FEATURES
• HIGH LINEARITY
±0.OO6% max (13 bits) and ±O.Ol% max
(12 bits) at 10kHz FS
±0.05% max al 100kHz FS
±O.1% max al 200kHz FS

• HI-REL MANUFACTURE
• 6-0ECADE DYNAMIC RANGE
• OUTPUT OTl/TTl/CMOS COMPATIBLE
• V/f OR F/V CONVERSION

DESCRIPTION
The VFC32 monolithic voltage-to-frequency and
frequency-to-voltageconverter provides a simple.
low cost method of converting analog signals into
digital pulses. The digital output is an open·collector
and the digital pulse train repetition rate is proportional to the amplitude of the analog input
voltage. Output pulses are compatible with ·DTL.
TTL. and CMOS logic families.
The converter requires two external resistors and two
external capacitors to operate. One external resistor
and one external capacitor set up the full scale
frequency, with a guaranteed nonlinearity of±O.I%
maximum at 200kHz. The other capacitor is the oneshot capacitor; for best performance it should 'have a
low temperature coefficient. The other resistor is a
noncritical open collector pull~upresistor.
The VFC321 MIL Series converter is available in
three electrical performance grades. The V grade has
200kHz specifications and tests. The W grade has
premium linearity, ±O.006% of FSR, and premium
full scale accuracy temperature coefficient of
100ppmj"C. The U grade is specified from -25°C to
+85°C and from _55°C to + 125°C. It is primarily for
high performance test equipment, shipboard, ground

support and industrial applications, where operation
is normally between -25°C and +85°C and full
temperature operation must be assured. All are
packaged in welded, hermetically-sealed, TO-I 00 ,
cans.
All devices are manufactured on a separate Hi-Rei
manufacturing line with impeccable cle.an room
conditions to assure "built-in" quality.
Three product assurance levels are available: standard, 1883B, and I MIL. The standard models have
many MIL-STD-883 screens performed routinely.
The 1883 suffixed devices are 100% screened per
MIL-STD-883 method 5004 class B and each/MIL
suffixed device is Hi-Rei manufactured, 100%
screened per MIL-STD-883 method 5004 class B,
and has 5% PDA..
.Quality assurance further processes / MIL devices,
performing group A and B inspections on each
inspection lot and group C and D inspections
periodically and when specified on the customer's
purchase order. A report containing the most recent
group A, B, C, and D tests is available for a nominal
charge.

International Airport Industrial Park· P.O. Box 11400· TUClon. Arlzonl B5734· Tel. (602) 746-1111 - Twx: 910-952·1111 - Cable: BBRCORP - Telex: 66-6491

11-120

DETAILED SPECIFICATION
MICROCIRCUITS, LINEAR
VOL TAGE-TO-FREQUENCY CONVERTER
MONOLITHIC, SILICON

I. SCOPE
1.1 Scop~ This specification covers the detail requirements for a very linear. voltage-to-frequency converter. For the
description of operation see paragraph 3.3.3.
1.2 Part Number. The com'plete part number is as shown below.
V

VFC32

T

~

Grade
(see 1.2.1)

Basic model
number

M

IMI\'

Metal
package

Hi-Rei product
designator
(see 1.2.2)

T

l

1.2.1 Device typ'e. The device is a single. voltage-to-frequency converter; it will also function as a single. frequencv-tovoltag~rte-;::- Three electrical performance grades are provided. The V grade features specifications and te;ts at
200kHz. The W grade features premium linearity (13 bits) and premium full scale accuracy. The U grade features
specified and tested performance from -25°C to +8SoC and maintains -~5°C to + 125°C operation.
Electrical specifications .are shown in Table I. Electrical tests are shown in Tables II and III.
1.2.2 Device class. The device class is similar to the product assurance level class B. as defined in M IL-M-38SI O. The
Hi-Rei product designator portion of the part number distinguishes the product assurance level as follows:
Hi-ReI Product
Designator
jMIL

/883B
(none)

Re~uirements

Standard model, plus 100% MIL-STD-883 class B screening, with 10%
PDA, plus quality conformance inspection (QCI) consisting of Groups A
and B performed on each inspection lot, plus Groups C and D performed
initially and periodically thereafter.
Standard model, plus 100% MIL-STD-883 class B screening.
Standard model including 100% electrical testing.

::!
1.2.3. Case outline. The case outline is A~2 (lO-lead can, TO-100) as defined in MIL-M-38SI0, Appendix C. The case is
metal and is conductive.
1.2.4 Absolute maximum rating~
Supply voltage range
Input voltage range. +input. pin I
Input voltage range. -input. pin 2
Output pull-up supply voltage (VPlI)
Output sink current, pin 6
Comparator input voltage
Output current pin 10
Storage temperature range
Lead temperature (soldering, 6Osec)
Junction temperature

.JJ

The absolute maximum input voltage is equal to the supply ....oltage.

:§ Vpt" is the supply voltage connected to pin 6 via

R~.

set:' Figure 2.

11-121

±22VDC
±22VDClf
±22VDCll
±22VDCJj 11
16mA
±22VDCJj
±20mA
-6S"C to +ISO°C
3OO"C
TJ = 17S"C

2:

~

CW)

=-f:e

1.2.S Recommended o~rating conditions.
Supply voltage range
Output pull-up supply (Vpd
Input voltage ~ange. ('vIN)
Input current range. pin 2
Full scale frequency
Ambient iemperature range

'±IIVDC to,±20VDC
, +4.5VDClb +20VDC
, OVDCto+[O.OOO2Sx (R, +'R,)]VDC.!loll
-IOVDC to OVPC 11
OmA to +O.2SmA
OmA to +0.50mA 11
100kHz !J
-SS"C to + 12S"C

1.2.6 Power and thermal characteristics.
Maximum allowable
Maximum
Maximum
Maximum
Package
Case outline
power dissipation
6 J-C
6 C-A
6.1-A
I()-Iead can
ISO"C. W
A-2
22SmW at T" == 12S"C
70"C/W
220"C W
(TO-100)
2. APPLICABLE DOCUMENTS
2.1 The following documents form a part of this specification to the extent specified herein.
SPECIFICATION
MILITARY
MIL-M-38SI0 - Microcircuits. general specification for.
STANDARD
MILITARY
MIL-STD-883 - Test methods and procedures for microcircuits.
3. REQUIREMENTS
3.1 General. Burr-Brown uses production and test facilities and a qUality and reliability assurance program adequate to
assure successful compliance with this specification.
3.1.1. Detail sJlecifications. The individual item requirements are specified herein. In the event of connicting
requirements. the order of precedence will be the purchase order. this specification. and then the reference documents.
3.1.2 Countr)' of manufacture. These microcircuits are manufactured. assembled. and tested within the ,United States of
America.
3.2 Design. construction. and p..!!},sical dimensions.
3.2.1 Package. metals. and other materials. The package is in accordance with paragraph 3,S.1 of M I I.-M-J85 10, The
exterior metal surfaces are corrosion resistant. The other materials. are nonnutrient to fungus as specified in
MIL-M-38S10.
3.2.2 Design documentation. The design documentation isin accordance with M II.-M-38SI0.
3.2.3 Internal conductors and internal lead wires. The internal conductors and internal lead wires arc in accordance with
MIL-M-38SIO.
3.2.4. Lead material and finish. The lead material is kovar type (type A). The lead finish is gold plate with nickel
underplating. The lead material and finish is in accordance with MIL-M-38SI0 andis'solderable per MIL-STD-883.
method 2003.
3.2.S Glassivation: The microcircuit die iii glassivated.
3.2.6 Die thickness. The die thickness is in accordance with MIL-M-385IO.
3.2.7 e!.t},sical dimensions. The physica~ dimensions are in accordance with paragraph 1.2.3 herein.
3.2.8 Circuit diagram and terminal connections. The circuit diagram and terminal connections are shown in Figure I.
3.2.9 Schematic circuit. The functional schematic circuit is shown in Figure I.
3.3 Electricaillerformancecharacteristics. The electrical performance characteristics are as specified in Table I and apply
over the full operating ambient temperature range of -SS"C to +.l'2S"c. unless otherwise speCified.
3.3.1 Additional electrical performance characteristics. Electrical performance curves are shown within paragraph 7.
3.3.2 Connection diagram. The connection diagrams for voltage-to~frequency operation are shown in Figures 2 and 3.
The connection diagram for frequency-to-voltage operation is shown in Figure 4.
'
Jj For positive input voltqes (see Fiau", 2).

11
11

!J

For frequencies 100kHz to 200kHz 50% duty cycle is recommended (ICC paragraph 3,3.3,1).
For negative input volt_ (see Fiaure 3),
For best line linearity.

ll-U2

'II-LEAO CAN (TOP VlEWI
.Vcc (CASEI 3

8 COMMON
7 COMPARATOR 'NPUT
NC = NO 'NTERNAL CONNEcnON.
EXTERNAL CONNEcnON PERM mEG.

FIGURE I. Terminal Connections and Functional Schematic Circuit.
3.3.3. Description of Operation. The inpui amplifier of the VFC is connected as an integrator (sec Figure 2). When a
positive input voltage is applied at V,~. a constant current. V,~, (R, + Rd. will flow through the input resistor. (R, + R,).
charging capacitor C1. At this time the current sink is disabled as the switch is open and the VFC output. pin 6. is logic "0".
The voltage at the amplifier output (comparator input) will ramp down from a positive voltage toward zero. according tn
dv dt = V,~ [(R, + R,) C1]. When the ramp reaches a voltage close to zero(= -O.6V). thecomparatorehanges state. and
tires the one shot. Note. this period of time is a function of the input voltage. V's.
As the one-shot fires. the VFC output. pin 6. changesfrom logic "0" to 10gic"I". and the switch closesenahling the I rnA
current sink. The length of time the one shot fires is determined hya reference (7.5V) within the one shot and the external
one shot capacitor C,. Note. this period of time is not a function of the input voltage. For good over temperature
performance C, must have a low temperature coefficient. When the current sink is enabled. the current in the integrating
capacitor. C1. revers(s direction and flows toward the summingjunction. This occurs hecause the constant input current.
V,s:(R, + R,). is set up to always be less than the ImA current sink. The voltage at the amplifier output ramps up
according to dv dt = [(V's '(R, + R.,) - (I rnA)]! C1. Before the ramp voltage saturates the amplifier. the one shot resets.
When the one shot resets. the switch opens. the current sink is disahled. the VFC output changes hack to logic "O"and the
cycle repeats.
Thc total VFC period is determined hy the following equations:

I·

I

"=T
C'
t = .lV",·, t, V's' (R',

+ R.,)+ .lV"n 12

C1
V,si(R,

+ R,) -lmA

and:

The equations reduce to:
f =
..
7.5 (R, + R,) C,

V,,,

Note, the outputirequency is not dependent upon C2, and the temperature coefficients ofR" R3, and C, are critical to the
VFC's over-temperature performance. These temperature coefficient effects must be added to the drift specifications of
the integrated circuit itself.
3.3.3.1 Dutysycle. The duty cycle(D) of the VFC is the percent the one-shot period (t1) is of the total VFCperiod (t,
It is measured at the full scale input voltage. which is theJull scale frequency.

D

=

+ t11.

~

t,

+t,

Duty cycle is related to the maximum input current and the I rnA (nominal) current sink. By reducing the equations for t1
and f..:
VIN maxi (R,+ IR 3)
I" max
D
!rnA
ImA

11-123

TRANSFER FUNCTION
'a=

V'N
7.5(RI +IIaICI

Vee = ±15VDC
Vpu BVoe
V'n = OVOC II +IOVoe

=

V'n

~ f_c_c

'a ==4IIz III1000Hz
_"JR,,4or-.....

EXTERNAL COMPONENTi

,

,

RI =Do

L----.- .~!

·VCC

'Vee (CASEI

~=1.21c1l

fIJ=2OIc1l
R4 = 10MII

As =50Icn
C, = 3300pF (0 = 0.251
~ = o.OI~F

COMMON

FIGURE 2. Connection Diagram. Voltage-to-Frequency Operation. Positivc Input.
TRANSFER FUNCTION
, _
,VIN
a-7.5(RI +R3IC,
Vee = ±15VDC
Vpu = 5VDC
Vln = ·IOVOC II +OVOC

'a ==4IIz til IDleHz

EXTERNAL COMPONENTS .

,Vee

11:

RI

,

,
,

fIJ=2OIc1l
R4= 10MIl

I

,---------yp.ass cap'acitors. Each power supply should be bypassed to ground as close as possible to the converter
with 0.0 III F capacitors.
3.3.5. Offset and gl!in error null. The VFC is capable of being nulled to zero offset and zero gain error using the circuits
shown In Figures 2. 3. and 4. R~ effects zero offset error; Ri effects zero gain error.
The offset and gain error null adjustment procedure is:
a. Apply an input voltage that should produce an output frequency of 0.001 of full scale.
b. Adjust Rs for 0.001 of full scale frequency.
c. Apply full scale input voltage. JJ
d. Adjust R3 for full scale frequency.
e. Repeat steps a through e.
If nulling is unnecessary for the application, delete R. and R~. and replace R3 with a ~hort circuit.
3.4 Electrical Tests. Electrical test requirements are as specified in Table II. The subgroups of Table III and limits of
Table, IV. which constitute the minimum electrical tests fOf screening. qualification. and quality conformance. are shown
in Table II.
3.5 Marking, Marking is in accordance with MIL-M-38510. The following marking is placed on each microcircuit as a
minimum.
a. Part number (see paragraph 1.2).
b. I nspection lot identification code ..1/
c. Manufacturer's identification ( ~).
d. Manufacturer's designating symbol (CEBS).
e. Country of origin (U.S.A.).,
3.6 Workmanshil'. These microcircuits are manufactured. processed. and tested in a careful and workmanlike manner.
Workmanship is in accordance with good engineering practices. workmanship instructions. inspection and test
procedures. and training. prepared in fulfillment of Burr-Brown's product assurance program.
3.6.1 Rework I'rovisions. Rework provisions for / MIL and! 883B Hi-Rei product designations. including rebonding. are
in accordance with MIL-M-38510.
3.7 Traceability. Traceability is in accordance with MII.-M-38510. Each microcircuit is traceable to the production lot
and to the component vendor's component lot. Reworked,or repaired microcircuits maintain traceability,
3.8 Product and llrocess change. Burr-Brown will not implement any major change to the design. materials. construction.
configuration, or manufacturi;;-g process which may affect the performance. quality. reliability or interchangeahility,of
the microcircuit without full or partial requali(ication.
3.9 Screening~ Screening, for / MIL and 883B Hi-Rei product designations. is in accordance with M II.-STD-KK.l.
method 5004. class B. except as modified in paragraph 4.3.
For the standard model, Hi-ReI product designation (none), routine manufacturing processing includes Burr-Brown
internal visual inspection, stabilization bake, fine leak, gross leak, constant acceleration, and external visual inspection
per MIL-STD-883, method 5004, class B.
For the jMIL Hi-ReI product designation. all microcircuits will have passed the screening requirements prior to
qualification or quality conformance inspection.
3.10 Qualification. Qualification is not required. See paragraph 4.2 herein.
3.1 I Quality conformance insllection. Quality conformance inspection, for the / MIL Hi-Rei product designation. is in
accordance with MIL-M-385 10. except as modified in paragraph 4.4 herein. The microcircuit inspection lot will have
passed quality conformance inspection prior to mireocircuit delivery.
NOTE:

.1
1.

For optimum linearity it is recommended that gain error nullin!! be performed at 90("; of full scale frequcncy rather than at IW", of full
A rour-digit date code, indicating year and week of'seul. is marked on 8838 and (none) Hi~ReI pnl: = 8mA

PinS

JJ

MIN

nA

Pin6

Linearity error
WULL SCALE = 200kHz

MAX
4

VFC32
UGRADE

40

Output logic "0"

Gain error, unadjusted
Linearity error
fFULL SCALE = 10kHz

MIN

,

Input offsel vollage
Input bias current
(inverting input)
Input bias current
Inoninverting input)
Output logic "0"
Output leakage currenl
!logic 11
Quiescent current

LIMITS
VFC32
WGRADE

VFC32
V GRADE

+25°Cto+125°C
+25°Clo+125°C

-3.0

+100

0

+60

-55°C to +25°C

-eo

0

-25°C to +25°C

-50

0

11-128

Hz
Hz
Hz
Hz
Hz
Hz
kHz
Hz

-30

+90

0

Hz
kHz

°Llmllslhe same as V grade.
NOTE:
Linearity error Is adjustad or normalized. to zero at 90'111 offull scale frequency an.d at 0.1'111 of full scale frequency.
Sublracl the frequency al the colder lemperature from Ihe frequency al the hotter temperetur•.

11
y

±1

±I
±1

+3.0
0

-8.4

'I

±I
±I

Hz
Hz
Hz
Hz
Hz
Hz
Hz
kHz

Hz
-75

+25

Hz

TABLE IV. Groups C and D. End Point Electrical Parameters (TA= +2S"C, ±V" = ISVDC).
LIMITS
VFC32VM/MIL

TEST
Input Offset Voltage
Input Bias Current (-)
Input Bias Current (+;
Full Scale Drift

4mV
40nA
l00nA
±3kHz (Hotl
-a.4kHz, OHz (Cold;

4. PRODUCT ASSURANCE PROVISIONS
4.1 Sam(>ling and ins(>ection. Sampling and inspection procedures are in accordance with MIL-M-38SIO and
MIL-STD-883. method SOOS except as modified herein.
4,2 Qualification. Qualification is not required unless specifically required by contract or purchase order.
Whenso required. qualification will be in accordance with the inspection routine of M IL-M-38SI0. paragraph 4.4.2.1.
The inspections to be performed are those specified herein for groups A. B. C, and D inspections (see paragraphs 4.4.1.
4.4.2.4.4.3. and 4.4.4).
Burr-Brown has performed and successfully completed qualification inspection as described above. The qualification
report is available from Burr-Brown.
4.3 Screening, Screening. for IMIL and /883B Hi-Rei product designations. is in accordance with MIL-STD-883.
method SOO4. class B. and is conducted on all devices. The following additional criteria apply:
a. Interim and final test parameters are specified in Table II. The interim electrical parameters test prior to burn-in is
optional at the discretion of the manufacturer.
b. Burn-in test (MIL-STD-883. method lOIS) conditions:
(I) Test condition B
(2) Test circuit is Figure S herein
(3) TA = +12S"C minimum
(4) Test duration is 160 hours minimum
c. Percent defective allowable (PDA). The PDA, for MIL Hi-Rei Product designations only, is S percent based on
failures from group A, subgroup I test after cool-down as final electrical test in accordance with MIL-STD-883,
method SOO4. and with no intervening electrical measurements. If interim electrical parameter tests are performed
prior to burn-in. failures resulting from preburn-in screening failures may be excluded from the PDA. If interim
electrical parameter test prior to burn-in are omitted. all screening failures shall be included in the PDA. The
verified failures of group A. subgroup I after burn-in in that lot are used to determine the percent defective for that
lot. and the lot is accepted or rejected based on the PDA.
d. External visual inspection need not include measurement of case and lead dimensions.

+lOV

FIGURE S. Test Circuit. Burn-in and Operating Life Test.

11-129

4.4 Quality' conformance insl!ection. Groups A and B inspections of M I L-STD-883. method 5005. are performed on each
inspection lot. Groups C and D inspections of M IL-STD-883. method 5005. are not required unless specified by contract
or purchase order.
Burr-Brown periodically performs groups C and D inspections of MIL-STD-883. method 5005. A report of the most
recent groups C and D inspections is available from Burr-Brown.
4.4.1 Group A insl!ection. Group A inspection consists of the test subgroups and LTPD values shown in M IL-STD-883,
method 5005, Table I and as specified in Table II herein.
4.4.2 Groul! B ins~ction. Group B inspection consists of the test subgroups and LTPD values shown in M II.-STD-88J.
method 5005. Table II (class B).
4.4.3 Groul! C insl!ection. Group C inspection consists ofthe test subgroups and LTPD values shown in M II.-STD-I!I!J.
method 5005, Table III, and as follows:
a. Operating life test (MIL-STD-883, method 1005) conditions:
(I) Test condition B
(2) Test circuit is Figure 5 herein
(3) TA = +125"C minimum
(4) Test duration is 1000 hours minimum
b. End point electrical parameters are specified in Table II herein.
4.4.4. Group D insl!ection. Group D inspection consists of the test subgroups and LTPD values shown in MIL-STD-883,
method 5005, Table IV, and as follows:
a. End point electrical parameters are specified in Table IV herein.
4.5 Methods of examination and test. Methods of examination and testare specified in the appropriatc tablcs. Elcctril'al
test circuits are as prescribed herein or in the referenced test methods of MIL-STD-88J.
4.5.1 Voltage and current. All voltage values given, except the input offset voltage (or differential voltage) are refcrclH:ed
to the externallero reference level of the supply voltage. Currents given are conventional current and positivc when
flowing into the referenced terminal.
4.6 Insl!ection of p.!!l!aration for deliver~ Inspection of preparation for delivery is in accordance with M IL-M-J8SI O.
except that the rough handling test does not apply.
5. PREPARATION FOR DELIVERY
5.1 Preservation-packagl!!g and I!ackins; Microcircuits are prepared for delivery in accordance with M II.-M -J85 IO.
6. 'NOTES
6.1 Notes. The notes specified in M IL-M-38510 are applicable to this specification.
6.2 Intended use. Microcircuits conforming to Ihis specification are intended for use in applications where the lise of
screened parts is desirable.
6.3 Ordering data. The contract or order should specify the following:
a. Complete part number (see paragraph 1.2).
b. Requirement for certificate of complial)ce, if desired.
6.4 Microcircuit groul! assignment. These microcircuits are assigned to Technology Group D as defined in MIL-M38510, Appendix E.
6.5 Electrostatic sensitivity-, Caution - these microcircuits may be damaged by electrostatic discharge. Precautions
should be observed alaH times.

11-130

7.

DISCUSSION OF SPECIFICATIONS.

7.1 Linearity..: Linearity is the maximum deviation of the actual transfer function from the straight line intersecting 9()//r of
the full scale frequency (90% of full scale input) and 0.1 % of the full scale frequency (= zero input). Linearity is the true
measure ofa VFC's performance. Linearity error is a function ofthe full scale frequency as shown in Figure 6. For a given
full scale frequency the linearity error decreases with decreasing operating frequency as shown in Figure 7. To allow the
user to benefit with improved linearity at lower frequencies. linearity error is specified in bands of operating frequency
(see Table I).
7.2 FreQuency' stability' versus temJ!!;rature. The full scale frequency drift of the VFC32 versus temperature is shown in
FigureS. The temperature coefficient effects of the external components (especially RI and CI) must be added to the drift
of the converter.

0.10

+\.D

0.04

.

!

+0.5
N

;:

0.02

i!.

:5

0.004
0.D02

-

!z:

1.;1

J 0.01
iII

'FULL SCALE =10kHz
TyplCll
TA =2S"C

"""- r-

"t:

~

-

0.00 I
Ik

III
4k

:/

-O.Ii

Typlcll TA=25"C,

2k

~

,."

10Ie 20Ic 4IIk
10IIIe 200Ic 4IIIk
Full Salt Fn~.nc, (Hzl

.\.D

1.II1II

FIGURE 6. Linearity Error vs Full Scale Frequency.

o

Ik

2k

3k

4k
5Ic
at 1k
Oparalfng Fral\Ulncy (Hz(

ak

9k

10Ie

FIGURE 7. Linearity 'Error vs Operating Frequency.

1000
Anngl f1Ir MOil Onlc.. (... Tlble 1\

..,.IG

TA =-lili"C hi +12S"C

~

IIIII
TA=-2Ii"C II +86"C

::::!

TJIIIcII TA=-2Ii"C III .a5"C

::E

......
N

IIIIIII

C'I)

IIIII

c."

u..

10Ie
10IIIe 200Ic 400k
Full Sail FI1....., (HzI

FIGURE S. Full Scale Drift ys Full Scale Frequency.

11-131

I.DM

=-

,

BURR-BROWN®

3500/MIL SERIES

IElElI

MODEL NUMBERS:
3S00R/MIL
3S00R1883B
3S00U/883B
REVISION A
OCTOBER,1981

General Purpose - Military
OPERATIONAL AMPLIFIER
FEATURES

APPLICATIONS

• LOW BIAS CURRENT. ±3OnA. MAX
• LOW DRIFT. ±2D~V/oC. MAX
• LOW NOISE. 1.4~V. rms
• WIDE SUPPLY RANGE. ±3VOC to ±2OVOC
• INTERNAL COMPENSATION
• HI-REL MANUFACTURE

• GENERAL PURPOSE AMPLIFIER
• ANALOG COMPUTATIDN
• PRECISION BUFFER
• LOW DRIFT INTEGRATOR
• BRIDGE AMPLIFIER
• STABLE REFERENCE CIRCUITS

DESCRIPTION
The 3500 IC op amps are designed for low input
current while maintaining slew rate and bandwidth
adequate for most applications. The low input bias
current is achieved by a unique bias current cancelling
circuit. This method insures that the bias current
remains low over the full temperature and commonmode voltage ranges. The same circuitry gives the
amplifier higli impedance, both differential and
common-mode.
The 3S00 is also a low noise IC op amp. Both current
and voltage noise are low, including the low frequency
"flicker" and "popcorn" noise which usually prevent
the use of IC op amps for low-level signal processing.
The 3500 is internally compensated for unconditional
stability for all feedback configurations. even with
capacitive loads. The slew rate is independent of
supply voltage level. The input stage of the 3500 series
exhibits no latch-up when the common-mode voltage
range is exceeded. The input impedance remains high
with differential inputs as high as ±30 volts, thus the
amplifier can be used as a sensitive comparator. The
output stage is internally current-limited to provide
protection against continuous short circuits. The

3500 is interchangeable with 741 type amplifiers but
gives greatly improved performance.

These devices are manufactured in a hi-reI environment with clean room conditions which assures
"built-in" quality. Each device is 100% internally
visually inspected per MIL-STD-883 method 2010
and after the cap is welded on, the balance of the
MIL-STD-883 method S004 class B screening is
completed.
The,' MIL suffixed devices are processed further by
Quality Assurance. performing groups A and B
inspections on each inspection lot and groups C and
D inspections when specified on the customer's
purchase order. A report containing the most recent
groups A. B. C, and D tests is available for a nominal
charge.
The R grade devices offer the best performance over
the ambient temperature range of -SS"C to +I 25"C,
However. if the operating ambient temperature range
will not exceed -2S"C to +8S"C, such as wil h test
.:quipment. the U grade device provides full performance at lower cost.

IntemaliOlllI Airport Induslrlll Park· P.O. Box 11400· TuC8oo. Arlzanl 85734· Tal. 1602) 746-1111 . Twx: 9111-952·1111· Clble: BBRCORp· Talax: 66.6491

11-132

DETAILED SPECIFICATION
MICROCIRCUITS, LINEAR
OPERATIONAL AMPLIFIER
~ MONOLITHIC, SILICON

I. SCOPE
1.1 Scop£.: This specification covers the detail requirements for a monolithic. integrated circuit operationlll
amplifier.
1.2 Part Number. The complete part number is as shown below ..

3500

T

Basic model
number

l

R

,MIL

T

Grade
(see 1.2.1)

Hi-ReI product
designator
(see 1.2.2)
1.2.1 Device typ£.: The device is a single. operational amplifier. Two electrical performance grades lIrc
provided. the R grade and the U grade. with the R grade offering the higher electriclIl performllnce.
1.2.2 Device class. The device class' is similar to the product assurance level class 8. liS defined in
MIL-M-38510.
The Hi-Rei product designator portion of the part number distinquishes the product assura-ncc level liS
follows.
Hi-ReI product
designator

Requirements

IMII.

Basic model, plus 100% MIL-STD-883 class B screening with 5% PDA, plus
quality conformance inspection (QCI) consisting of Groups A and B on each
inspection lot, plus Groups C and D performed initially and periodically
thereafter.
18838
Basic model. plus loocii. MIL-STD-883 class 8 screening.
1.2.3 Case outline. The case outline (8-lead can) is as defined in Figure 4. The case is mctlll lind is Clllldu.:t i\ e.
1.2.4 Absolute maximum rating!!:
Supply voltage range
I nput voltage range
Differential input voltage range
Storage temperature range
Output short-circuit duration
Lead temperature (soldering. 60sec)
Junction temperature

±20VDC
±20VDC .LI
±40VDCJj
-65"C to + 150"C
Unlimitcd.Y
300"C
1'., = 175"C

1.2.5 Recommended oRerating conditions.
Supply voltage range _ _ _ _ _ _ _ _ ±3VDC to ±20VDC
Ambient temperature range
-55"C to +125:'C
1.2.6 Power and thermal characteristics.

JJ

Package

Case outline

Maximum allowable
power dissipation

8-lead can

FlGURE4

225mW at T, = 125"C

Maximum
II J-C
70"C W

Maximum
II ('-1\

220T W

The absolute ma.'(imum input \ulli.lgc j" L'4Uilltu Ihe :-,uflpl) wlttlgc.

]J Short circuit rna} be tn ground IInl}. Rating apr1ic:-. tu + 1.1~··("

l'il:o.C Il'mpcrilturl'

11-133

or

~5()"C



:;

"

'0

1kHz

".f

-40
25

lk

50 75 100 125

10k

I

OPEN-LOOP FREQUENCY

cii

~

c:
'n;

.

100

Cl

60

C>

40

~
0

>

20
0

a

:>

-20
1

110

100

.

90

o

I

.

10

C>

J!!

J

(;

>

"

\

~

:;
£l-

,

II

~

-5

0

-10

,

\

RL = lkll
CLrl0r

lOOk

o

1M

10

20

30

40

50

VOLTAGE GAIN vs.

OUTPUT VOLTAGE vs

OUTPUT VOLTAGE vs.

SUPPLY VOLTAGE

OUTPUT CURRENT
20

J
.><

Co

-

:>

I'\TA= SSOC==

0.

I
12

"

0>

>

:;

r-.

16

I

Vee .-= 10V

1"

8

:;

4

.

!Vcc'- 5V

10

/

0

>.

:;
Co
:;

15

20

25

> 0.
,,>
o -

12

;; ~
~~

40

E
0
0

1\

-20
10M

8
4

0

16

20

POWER SUPPLY REJECTION vs.
FREQUENCY
10.000

r-16

12

8

Supply Voltage I ±V,

20

"
~

/

,V
o

30

V

.L

/

/'

/

0

SUPPLY VOLTAGE

60

Frequency I Hz I

....

COMMON-MODE RANGE vs.

...

10 100 lk 10k lOOk

~-

12

Output Current, mA,

80

0

16

......

:>

:>

/

o,i

20

...
'"

C>

0
i},

I.~ ..." ......

o

20

I
I
RL = lkll

~

0
i},
~

I

±Vcc·3~

16

a

±Vcc:::; 15V

12

60

SUPPL Y VOLTAGE
20

-rVcc - 20V

..,......

J!!
0

0

TA = 125°C

100

1

n

Time l~sec l

120 ~ r--VCM = 10V, pk -

0

15

L'R",:'= lkll

10k

FREQUENCY

'2

1M
I

-15

COMMQN-MODE REJECTION vs.

~
II:

lOOk

VOLTAGE FOLLOWER
STEP RESPONSE

1111111

lk

Supply Vo~age I:tV I

cii

10k

I III

Freqoency I Hz I

"'"

Co

0

lk

+Vcc - 3V

~

I III
I

Frequency 1Hz I

..J

C

" 1 III
fe 100Hz

'Source ReSistance

~~c~I~~5~

4

10 100 lk 10k lOOk 1M 10M

r-=--'"
:::- i--L

Cl

I

0

TA - 25°C

c:
'n;

0.
0
0

"

"

V fe =lkHZ

fe = 10Hz

In·

'V,:'~I~V

>
:;

= -55"C I
TA = -25°C
/

~

10

"

£l-

~

,
I

1111111

J!!
0

TA

cii

12

0>

""

IV

I

./
......:~

.f

1M

lOOk

~V,~'~'~V

14
±Vcc = 3V to 20V

""

80

C.
.~ ~ 10
0
z >~
:;

OUTPUT VOLTAGE vs.
FREQUENCY

RESPONSE

r....

I

I~ ~ lbk~Z

I III

Source Resistance

120

III

100

g

fe = 100Hz
fe - 10Hz

I0

II>
0>

J!!

Co

0.1

·50 ·25

L

1/

,l'V
/V

z :>

/

·20

~

/'

III

rDe= 10kHz
I-.fe

5:

I

III

10

0>

20

0

.

60

~

V

I

c:
.S!

1000

.2:-

100

i

/

/

Co

0.

"

L

V,

2

3

6

Vou',

V,N

VOll'l" = Vn..

dl Diffen:nce Ampliroer

crPrecision Buffer Amplifier

11-142

BURR-BROWN®

3510VM/MIL

IElElI

REVISION A
MARCH,1984

DETAILED SPECIFICATION
MICROCIRCUITS, LINEAR
OPERATIONAL AMPLIFIER
MONOLITHIC, SILICON
I. SCOPE
1.1 Scop£: This specification covers the detail requirements for a monolithic, low offset voltage drift, integrated
circuit operational amplifier.
1.2 Part number. The complete part number is as shown below.
V
3510

T

Basic model
number
1.2.1

~yp.!.

l

M

(MIL

Metal
package

Hi-Rei product
designator

l

Grade

I

The device is a single, operational amplifier.

1.2.2 Device class. The device class is similar to the product assurance level class B, as defined in

MIL-M-3851O~

1.2.3 Case outline. The case outline (8-lead can) is as defined in Figure 5. The case is metal and is
conductive.
1.2.4 Absolute maximum rating~
Supply voltage range
Input voltage range
Differential input voltage range
Storage temperature range
Output short-circuit duration
Lead temperature (soldering, 6Osec)
Junction temperature

±20VDC
±20VDC 1;
±40VDCli
-65°C to +150°C
Unlimited1J
300°C
TJ = I75°C

1/ The absolute maximum input voltage is equal to the supply voltage.
2{ Short circuit may be to ground only. Rating applies to +135OC case temperature or +50OC ambient temperature at
±ISVDC supply voltage.

Inllmlllonil Alrporllndullrlll Plrk·

P.o. BOll 11400· TucsOll. ArizOlll85734· Tal.l802J 7411-1111 . Twx: 91(1.952·1111 • Cabla: BBRCORp· ralax: 66-6491

11-143

1.2.5 Recommended operating conditions.
Supply voltage range ____ ~ ____________ ±3VDC to ±20VDC
Ambient temperature range ____________ ~55°C to+125°C
1.2.6 Power and thermal characteristics.
Package
Case outline
8-lead can
Figure 5
2. APPLICABLE DOCUMENTS

Maximum allowable
power dissipation
225mWat TA -125°C

Maximum
8 J-C
70°CfW

Maximum
8 J-A

220°CfW

2.1 The following documents form a part of this specification to the extent specified herein.
SPECIFICATION
MILITARY
MIL-M-385io - Microcircuits, general specification for.
STANDARD
MILITARY
MIL-STD-883 - Test methods and procedures for microcircuits.
3. REQUIREMENTS
3.1 General. Burr-Brown uses production and test facilities and a quality and reliability assurance program
adequate to assure successful compliance with this specification.
3.1.1 Detail sp'ecifications. The individual item requirements are specified herein. In the event of conflicting
requirements, the order of precedence will be the purchase order, this specification, and then the reference
documents.
3.1.2 CountrY. of manufacture. These microcircuits are manufactured, assembled, and tested within the United
States of America.
3.2

Desig~,

construction,

!!ill! PEy'sical dimensions.

3.2.1 ~&£.~. and other materials. The package is in accordance with paragraph 3.5.1 of MIL-M-38510.
The exterior metal surfaces are corrosion resistant. The other materials are nonnutrient to fungus as specified in
MIL-M-38510.
3.2.2 Design documentation. The design documentation is in accordance with MIL-M-3851O.
3.2.3 Internal conductors and internal lead wireit. The internal conductors and internal lead wires are in
accordance with MIL-M-3851O.
3.2.4 Lead material and finish. The lead finish is gold plate. The lead material and finish is solderable per
MIL-STD-883, method 2003.
3.2.5 Glassivation. All die are glassivated.
3.2.6 Die thickness. The die thickneS"s is in accordance with MIL-M-38SI0.
3.2.7 Physical dimensions. The physical dimensions are in accordance with paragraph 1.2.3 herein.
3.2.8 Circuit diagram and terminal connections~ The circuit diagram and terminal connections are shown in
Figure I.

OUTPUT

8-Lead Can (lop View)
:'\OTF.: ·\'1 ( is connected to the

l'aM~>

FIGURE I. Terminal Connections.

11~144

3.2.9 Schematic circuit. The schematic circuit is shown in Figure 2.
V+Q79'~'~I-'~----~----~--------~-R-~--------------~--'
Ikll

Iktl

••

2.94kfl
V'''4~

.9

.IS

UlkU

lIII011

'10

.KWn

IU7
Jkll

H.lts
1411

________- L__- L____________

NOTE: All resistance and capacitance values are nomlltal.

FIGURE 2. Schematic Circuit.
3.3 Electrical p'erformance characteristics. The electrical performance characteristics are as specified in Table I and
apply over the full operating ambient temperature range of -55°C to + 125°C, unless otherwise specified.
3.3.1 Offset and gain error null. The amplifier is capable of being nulled to zero offset voltage using the circuit in
Figure 3.

INPUTS~

0-----

H;':::=== OFFSET NULL
OUTPUT

-Vee

FIGURE 3. Offset Null Circuit.
3.3.2 FreQuency comp'ensation. The amplifier is free of oscillation when operated at a gain of 10 or greater with no
external compensation and a source resistance of ~lOk.n and when operated in any test condition specified herein.
3.4 Electrical tests. Electrical tests are shown in Table III. The subgroups of Table III and limits of Table IV, which
constitute the minimum electrical tests for screening, qualification, and quality conformance, are shown in
Table II.
3.5 Marking. Marking is in accordance with MIL-M-38510. The following marking is placed on each microcircuit
as a minimum.
a. Part number (see paragraph 1.2)
b. Inspection lot identification code
c. Manufacturer's identification
d. Manufacturer's designating symbol
e. Country of origin

11-145

TABLE I. Electrical Perlormance Characteristics.
Characteristics

Input

off~

voltage

Inpul offset voltage
temperature sensitivity
(unnuDed V,ol

Input offset current
Input offset current
temperature sensitivity
Input bias current
Input bias current
~emperalure sensitivity
Power supply
rejection ratio
Power sup~ly
. rejection ratio
Inpul voltage
cornmon--mode rejection
Adjustment for
input offset voltage
Output short circuit current
(for positive output)

Output short circuit current
(for negative OU'put)

DC power dissipation
(qui....nl)
Single-ended input impedance
(noninverting input)

Conditions
(+V,,· = ISV. unless olherwise specifted)

Symbol
V,O

4

VIO

-rr

T. = 2S"C
·SS·C';; T • .;; +12S"C

4 TA from aSS"C to +2SoC
4 T. from +2S"C 10 +J2S"C

1,0
4110

AT

TI

.-

4 T. from -SS·C 10 +2S"C
4 T. from +2S C 10 +12S C

T. - 2S·C
-SS"C';; T.';; +l2S·C
4 T A from -SSoC to +2SoC
4 T. from +2S"C 10 +l2S·C
+Vct·

Units

Max

,

·SS"C';; T.';; +12S·C

III
.6 II.

Limits
MIn

±120

uV

±JSO

",V

+2
±2

uV ·C
"V!"C

±IS
±SS

nA
nA

±O.4
±O.4

nA/·C
nA/"C

+2S
±8S

nA

±O.6
±O.6

nA ·C
nA!"C

nA

= IOV

+PSRR

-Vcr: = -ISV,

T. = 2S·C

3

"V/V

-PSRR

+Vcr: = ISV
-Vcr:=-IOV

T. = 2S"C

3

",V/V

CMR

V50

COMMON-MODE REJECTION
VS FREQUENCY

d
[I

X= 12V, Pop
Y=±10VDC

40

r\,

20
100

lk

10

~

5

gi

0

:;
Q.

:; ·5

o

i\

I

-

-10

o

16

I
2.0
Time

~ 8
.5 6
4

2

I
3.0

4.0

o

5.0

~sec

OUTPUT VOLTAGE VS
OUTPUT CURRENT

100

lk

10k lOOk 1M 10M

INPUT VOLTAGE FOR
LINEAR RESPONSE

Positive Common-mode

r=~ Differential

r r Negative Common-moc:;,
,~

~

~

'/

'"
~

.'

n.·

..•

..'

.'

I

2 4 6 8 10 12 14 16 18 20
Power Supply Voltage ~Vcc
SUPPLY CURRENT VS
AMBIENT TEMPERATURE

16
14

"
()

,

5mA Load -::~-

8

.ag- 6

Quiescent

4

'"

10k lOOk 1M 10M

Frequency I Hz

y.fjd\t"~~ I

& 12
~ 10

V'~j'~ \
1.0

rt

-j

> 14

:\

I

C

Frequency. Hz

20
18

('

X'F~th~U9~

10

1M

~ 12

\

30

10

I
lOOk

I l"\. Y - 12V. POp
I 1_\X=±10VDC-

0:

~

20

.c::

LARGE SIGNAL RESPONSE
10

.n

Y

10k

Inpft

'"

Frequency I Hz I

OUTPUT AMPLITUDE VS
FREQUENCY

:>

r:
f

.L

t/'

/

€
. ill 0.1
.5
g
Z 0.0 1

. Sig~al
-1 = kav.
I !.p 1 I
III

tsoo

.,;
§200

V

/

'0

'5 O. I

~'"

Sig~al = ~V. pop

10

l2

FEEDTHROUGH VS FREQUENCY
1000

16
Output Current ±mA

o

-100-75-50-250 255075100125150
Ambient Temperature °C

8. APPLICATIONS INFORMATION
8.1 Power suppl}' decoupling, For optimum performance and to prevent frequency instability due to power supply lead
inductance, each power supply should be decoupled by connecting a IpF tantalum capacitor from each power supply pin
to ground (power supply common).
8.2 9ipacitive loads. Stable operation is maintained with capacitive loads up to 1OOOpF, except for the square root mode
which is limited to SOpF. Higher capacitive loads can be driven if a lOon resistor is connected in series with the output for
isolation.
8.3 Iypical Applications.
8.3.1 Multiplication. The basic connection for four-quadrant mUltiplication is shown in Figures 2a and 2b. Optional
offset nullling is shown in Figure 3. Feedthrough may be minimized by applying an external nulling voltage to the X andl
or·Y input, as appropriate. Usually, the nulling voltage is applied to X2 or Y2. If Z2 input is not used, it should be
grounded.

11-160

Figure 6 shows how to achieve a scale factor larger than 0.1 (i.e., a denominator less than 10). A larger scale factor is
electrically advantageous in some applications, but this has the disadvantage of proportionately increasing the output
offset voltage. Note, the offset may be nulled as shown in Figure 3. Also, the small signal bandwidth is reduced to about
50kHz.
IlIIn

4213

K= [1 + IA,/A2)]l10
0.1 ,.;;K,.;;I
·15VDC

+15VDC

FIGURE 6. Connection for Unity Scale Factor.
8.3.2 Division. The basic connection for two-quadrant division is shown in Figure 2c.
Divider error is approximately
.
Edivider

10Emultiplier
I 2

X

=

X

Note, the divider error will become very large for small values of (XI - X2). A 10 to I denominator range is a practical
limit.
8.3.3 §..quaring~ The basic connection is shown in Figure 7.
X,
x2

>--+'--0"

4213

V,o-.......I--fY,

t:Y2~--r--.,._/"---r: 12

v2

.,;..
IDDkn
·15VDC

+15VDC

FIGURE 7. Squaring Connection.
8.3.4 Square Root. Figure 8 shows the connection for taking the square root of the voltage VZI - VZ2. The diode prevents a
latching condition which could occur if the input momentarily cJll~nged polarity. The'load resistance RL must be in the
range of IOkO';;;; RL';;;; I MO to provide the current necessary to operate the diode. The output offset should be nulled for
optimum performance; allow the input to be its smallest expected value and adjust RI for the proper output voltage. The
square mot mode accuracy is then approximately that of the mUltiply mode.

v.=
~

lit.

+15VDC

Al
lOOk!!

I, ':"

I,

·15VDC
·15VDC
·Opdllllli Nulling camponanll

+15VDC

12

0:-

+O.2V,.;; Il, • 12)";; +IOV

+O.2V ,.;; Il, • 121 ,.;; +IOV
·15VDC

FIGURE 8. Square Root'Connection.

11-161

·15VDC

+15VDC

It

8.3.5 Percent. The circuit of Figure 9 has.a sensitivity of I V /% and is capable of measuring 1'0% deviations. Wider
deviation can be measured by d,ecreasing the ratio of R2/R,.

4213

FIGURE 9. Percentage Computation.
8.3.6 Sine Function Generator. The circuit in Figure 10 uses implicit feedback to implement the following sine function
approximation: Vo = (1.5715V, - 0.004317V,3)/(l + 0.001398V,2) = 10 sine (9V,).

71.548kO
XI
"--"""""~--+-IX2

YI

Vo =10 Iln.9VI
4213

5.7I5kO

Y2

10kn

HOV,;;VI,;;+IOY.IAdIV=go)

FIGURE 10. Sine Function Generator.
8.3:7 Singk-[lhase Power Measurement. Figure II shows a circuit for measurement of single-phase instantaneous and
real power.

0:=R5 /IR4+RsI
,,= I-R I Ral/R2
InliaotalllOUl

Power
R.al Power

f

10:,,11 O)IElrmIILrmlC818)

FIGURE II. Single-Phase Instantaneous and Real Power Measurement.

11-162

MODULAR POWER SUPPLIES

Well-regulated DC power is usually required to power modern electronic
circuits. Overthe years electronic circuits have changed in terms of size and
performal)ce. Packaged in small integrated circuit packages or in hybrid
modules, more. and more electronic circuits now provide significantly
improved performance .. Burr-Brown encapsulated power supplies have kept
up with changing times. We provide a broad line of reliable, self-contained,
ready to use power supplies, at low cost, to meet OEM and design engineers'
power supply requirements.
Burr-Brown standard series AC/DC power supplies and DC/DC converters
provide maximum flexibility in systems design. They are particularly useful
for powering analog interface circuitry involving operational amplifiers, A/D
and D/A converters, instrumentation and isolation amplifiers, analog circuit
functions, and so forth, in digital and analog systems. A wide range of output
voltage and current ratings are available; international input voltage ratings
are also available.
The AC/DC supplies are available in both the PC board-mountable and
chassis-mountable versions. The chassis mount type provides the same
reliable performance as the PC board mount type, but the input and output
connections are made on a terminal strip via screw terminals rather than
pins. They are useful in applications where use of PC boards or sockets is
either undesirable or impractical.
The DC/DC converters are available in small encapsulated PC boardmountable packages. They provide high input-output isolation, making
them suitable in computer interface applications where, if necessary, the
analog circuitry can be "floated" completely independent of digital ground.
Specially designed DC/DC converters are available for use with opticallycoupled isolation amplifiers and for applications where isolation voltage
ratings of 3000 volts and more are required.
AI!' Burr-Brown power supplies are extensively tested before and after
encapsulation to ensure reliable operation. Computerized automatic testing
equipment is used to implement stringent quality control. Years of linear and
digital engineering expertise have gone into the design and manufacture of
Burr-Brown products. Most of these power supplies are available from stock
in both small and large quantities.

12-1

SELECTION GUIDE
AC/DC CONVERTERS
Rated
Output

Regulation
Overrated
Line Voltage

Output'"
Noise

Package

Page

±0.1%
±0.05%
±0.05%
±O.05%

2mV
O.5mV
O.5mV
O.5mV
O.5mV

Module
Module
Module
Module
Module

12-3
12-3
12-3
12-3
12-3

Ripple/

Description

Model

Dual±1f;VDC
Supply
P.C.B. Mount

f;50
551
552
553
554

±15V, ±2f;mA
±15V, ±50mA
±15V, ±100mA
±15V, ±2oomA
±15V, ±350mA

±O.O~%

±O:05%
±O.O5%
±0.O5%
±O.Of;%
±O.O2%

Dual ±15VDC
Supply
Chassis Mount

556

±15V, ±200mA

105VAC to 125VAC,
50Hz to 400Hz

±O.O5%

±O.05%

lmV

Module

12-3

558

±15V, ±500mA

121(3)141

±O.O5%

±O.O5%

lmV

Module

12-3

5VDC Supply
P.C.B. Mounl

560
561
562

5V fs " ±250mA

±O.I%
±O.I%
±O.I%

±O.05%
±0.05%
±O.O5%

lmV
lmV
lmV

Module
Module
Module

12-3
12-3
12-3

5V''', ±500mA
5V'S',

Rated Input

Regulation
No Load
to Full Load

105VAC to 125VAC,
WHz to 400Hz
121131141

105VAC to 125VAC,
50Hz to 400Hz
121131141

±1000mA

DC/DC CONVERTERS

Description

Model

Regulated

546

Isolated

Input

Output

Isolation

Leakage
Current

Package

Page

4.5VDC to 5.5VDC
400mA

Single-Bipolar
±15V,120mA

300V

Not Specified

Module

12-3

PWR70

10VDC to 18VDC

±1%VDC, ±1oomA

2000VDC

max

Module

12-9

700

10VDC to 18VDC
89mA

±10VDC to ±18VDC
(±1V tolerance)
at 60mA total

1500Vp

11lA, max

Module

12-11

700U '5.1

10VDC to 18VDC
89mA

±10VDC to ±18VDC
(±1V tolerance)
at 60mA total

2000Vp

11:'A, max

Module

12-11

710161

10VDC to 18VDC
100mA

Four sets of outputs
each set:
±10VDC to ±18VDC
(±1V tolerance)
at 76mA total
all outputs

1000Vp

1pA. max

Module

12-13

722
722BG

5VDC to 16VDC
120mA

Two-Bipolar
±15V,64mA

3500VtSI

lilA at
240V, 60Hz

DIP

12-17

800QV ffll

724

5VDC to 16VDC
125mA

Four-Bipolar
±8V

lilA at
240V, 60Hz

DIP

12-24

3000V ClJl

1000Vt5J

1/JA,

NOTES: (1) At full load, .rms (max): (2) 205VAC, 50Hz to 400Hz option available. (3) 90VAC to 110VAC, WHz to 400Hz option available. (4) 220VAC to 260VAC, 50Hz to 400Hz option available. (5) Models 700 and 700M have separate Internal Input and output shields.
Models 700U and 700UM have no Internal shields. Model 700M and 700UM are Similar to Models 700l7OOU but, In addition, they are 100%
screened to patient-connected circuit requirements for the leakage current (par. 27.5) and withstand voltage (par. 31.11) of UL544. Additional
per unit charge for 700M or 7ooUM. See Product Data Sheat for complete specifications. (6) Model 710 provides 4 channels (sets) of Isolated
outputs. See Product Data Sheat for com~lete specifications.
REGULATED BATTERY-BACKED POWER SUPPLY
Model

Rated Output

PSBloo

+5VDC, 1'.2A
+12VDC, 1.2 A
-12VDC, 1.2 A
-5VDC.loomA

Output Ripple
lWmV,
360mV,
360mV,
40mV.

p-p
p-p
p-p
p-p

Current Limit

12.0A ±5%
1.5A ±5%
1.5A±5%
None

Rated Input
{ lOO-I30VAC
or
200-260VAC

12-2

Features

Page

Designed for,use with microcomputer systems
such as Multibus?· system.
Provides signals for line power loss. or low
internal battery.

12-7

BURR-BROWN@

IElElI

MODULAR AC/DC AND
DC/DC POWER SUPPLIES

FEATURES
• PC BOARD-COMPATIBLE
• CHASSIS MOUNTABLE
• HIGH RElIABILITY, FULLY TESTED
• LOW INSTALLED COST
• COMPLETElY SELF·CONTAINED

DESCRIPTION
Burr-Brown standard series power supplies and
DC/DC converters provide maximum flexibility in
systems design. They are particularly useful for
powering analog interface circuitry in digital and
analog systems and have a wide range of output
voltage and current ratings. They are completely selfcontained. ready to use encapsulated units. For most
OEM users they eliminate engineering startup/documentation costs and manufacturing delays
at prices generally far below internal manufacturing
costs.
The AC! DC power supplies have a current limiting
circuit in the output stage. designed to withstand
output short-circuit-to-common or substantial
overload conditions for long periods of time. without
causing damage to the power supply.
In applications where isolation between input and
output is an essential requirement (such as powering
isolation amplifier input and output stages) the BurrBrown isolated DC/DC converters provide up to
l500VDC of isolation protection.

International Airport Industrial Park· P.O. Box 11400 . Tucson. Arizona 85734 . Tel.1602J 746-1111 . Twx: 9tO·952·111 t . Cable: BBRCORP . Telex: 66·6491

12-3

MODULAR AC/DC POWER sUPPLIes
• PC BOARD/CHASSIS MOUNT TYPE
• ±15VDC DUAL OUTPUTS, +5VDC SINGLE OUTPUT
• 25mA TO l000mA CURRENT CAPABILITY
• CURRENT·LlMITED OUTPUTS FOR SHORT CIRCUIT PROTECTION
• INTERNATIONAL AC INPUT VOLTAGE OPTIONS AVAILABLE·

SPECIFICATIONS COMMON TO ALL ACIDC
POWER SUPPLIES
Input Voltage: lOSVAC to 12SVAC. SOHz to 400Hz. For international
AC input voltages see options E. F. and H.
Input Isolation: SOMfl
Breakdown Voltage: SOOV; min.
Output Voltage: Error. ±I%; temperature coefficient. ±O.02%/"C
Output Protection: Current limiting protection for output to withstand
overloads and direct short circuits to ground to prevent excessive
temperature within the unit.
Rated Operating Temperature: -2SoC to +71 °C. May be operated at higher
temperatures with proper derating.
Storage Temperature: -2SoC to +8SoC.

DCI DC CONVERTERS, ±15VDC OUTPUT
• REGULATED ±15VDC FROM UNREGULATED DC INPUT
.' DIFFERENT DC INPUT VOLTAGE RANGES AVAILABLE
• HIGH CURRENT CAPABILITY WITH CURRENT LIMIT PROTECTION
• ISOLATED DC/DC CONVERTERS. 75% EFFICIENCY AT FULL LOAD
• LOW COUPLING CAPACITANCE (8pF)

ISO be/bc COl(v

• HIGH ISOLATION VOLTAGE (1500VDC)
• LOW EMI. SHIELDED AND UNSHIELDED UNITS
• UP TO FOUR FULLY ISOLATED OUTPUT CHANNELS (Model 710)
• SMALL SIZE

~
. ~. ~~':Ja~.·':'
~U~

,100/j

.''{.~;.

12-4

AC/DC CONVERTERS
5VOC Logic Supplies

Dual ±15VDC Supplies
PC Board Mount
Model

m

550

552

Chassis Mount

554

553

556

558

PC Board Mount

561

560

562

RATED OUTPUT
±15V
±ISV
±I~V
5Vo,
±ISV
±15V
±lSV
±ISV
±25mA ±SOmA ±IOOmA ±200mA ±350mA ±2oomA ±500mA 250mA

Voltage (nom)
Current (max)

SV/lH~t

Sv/llr~)

SOOmA 1000mA

RATED INPUT
Voltage

105 - 125VAC, 50 - 4ooH7

105 - 125VAC
50 - 4OOH,
E,F,H

E, F, H

Options!'·

105 - 125VAC, SO - 4ooH,
E, F, H

REGULATION
No load to full load (max)
Over rated line voltage (max)

±O. I fii ±O.OSIf( ±O.05f',f, ±O.OSW· ±O.02o/r ±O.OS% ±O.OS% ±O,I% ±O.I% ±O,I%
±a.OSI/(, ±O.OSr:; ±O.OSt;( ±O.05e.:!. ±O.02<;t ±0.05% ±0.05% ±O.05% ±O,OS% ±O.05%

OUTPUT RIPPLE AND NOISE
At full load. rms (max)

2mV

0.5mV

0.5mV

0.5mV

O.5mV

ImV

ImV

ImV

ImV

ImV

DC/DC CONVERTERS :l1SVDC Output
MODEL
RATED INPUT
Voltage

Current. Quiescent
Current. full load

Low Profile
546

4.5VDC to 5,SVDC
400mA. max
!'SA. max

Isolated/fll
700/700U'·1

7101\1

IOVDC to ISVDC
20rnA at ±3mA load
89mA max at ±30mA load

IOVDC to ISVDC
4OR'!A at total output of 24mA
1000A at total output of 76mA

RATED OUTPUT
±ISV
120mA. max

±V.:. w: IV tolerance

4 sets of ±V'IN wI IV tolerance

Current

total 6OmA. max.

Shorl circuit current

180mA. max

120mA. max

total 76mA max; any single
output -60mA. max
l20mA. max

0.1%. max
0.02Q typo 0.1% max

35mV/mA

75mV/mA

max

±ISmV peak at ±3mA
load; ±8OmV peak. max.
at ±30mA load

±2SmV peak at ±3mA
load; ±80mV peak; max.
at ±9.SmA load

300VDC
10"0 II 50pF

42ooVp/SOOOVp
ISOOVpj2000Vp
1O'''1l II 5pF /10'''0 II 3pF

2200V. rms
6OOV. rms, IOOOVp

Voltage (no load)

REGULATION
line at rull load
load. zero to full load

OUTPUT VOLTAGE TEMP. COEFFICIENT
OUTPUT RIPPLE

±3mV:"C

JOmV peak, typ; 20mV
pea.k. max; O.8mV. rms

-

-

-

INPUT-OUTPUT ISOLATION
Test voltage. Ssec at 60Hz
Voltage. continuous. derated
Impedance
leakage current at 240V,' 60Hz. tested

IO'''ll II SpF

IliA. max

IliA. max

-2S"C 10 +SS"C
-SS"C to +12S"C

-2S"C 10 +S5"C
-SST 10 +IIO"C

TEMPERATURE RANGE
Operaling
Storage

OT to 71T
-SST to +IOO"C

I. The output may be connected as +SV or -SV.
2. These 5V supplies have over-voltage protection which limits the output voltage to 7V (max) in a fault condition.
3. International input voltage rating available. Specify: E option - 20SV AC to 240VAC. 50Hz to 400Hz.

F oplion - 90VAC 10 1I0VAC, 50Hz to 400Hz.
H option - 220V AC to 260V AC, SOH, to 400Hz.
4. Models 700 and 700M have separate internal input and output shields. Models 700U and 700lJM have no internal shields. Mode1700M and 700UM are similar to
Models 700, 700U but. in addition. they are lOOCk screened to patient connected circuit requirements for the leaka"geeurrent (par. 27.5) and dielectric withstand
voltage (par. 31.11) of UL544. S;~ Product Data Sheet for complete specifications.
S. Model 710 provides 4 channels (sets) of isolated output~. See Product Data Sheet for complete specifications.
6. For newerdesign~. the models 722 and 724 (hybrid isolated OCt DC converters) which are smaller in size and better in performance are recommended. Please refer to
models 722 and 724 product data s.heets.

12-5

PACKABE DRAW/NBS
DRAWING ND. 1

DRAWING NO, 2

68.6mm
(2.7")

,

12.7
mm
(0.5"')

--------!

l~hmlI

'AC

63.5mm
(2.5")

lCiOfI~~ii5lI~~ii5lI~iII-.l.. 10.2mm

r"
r'

Pin Diameter 1.02mm (0.04")

101.6rnm

• No Connection for Models 560, 561, 562.
For Models 550, 551, 560 - A = 22.2mm (0.875")
Weight: 340 grams (12 oz)
For Models 552, 553, 561, 562 - A
Walght: 425 grams (15 oz)

THREADED INSERTS (4)
#4-40 = 3.3mm (0.13") deep

= 32mm (1.25")

For Model 554 - A c 4.1cm (1.62")
Weight: ~50 grams (26 oz)

~OTTOM V IEW -11-- 2.54mm (0.1 ")
For Model 556 - A

DRAWING ND. 3 Model 546

= 36.6mm

(1.44")

For Model 558 - A = 50.8mm (2.00")

10.2
mm
(0.4")

DRAWING NO, 5 Model 710

2.54
mm

(0.1")11--+_1-+-".1

WEIGHT -

T

BOTTOM VIEW

50 grams (1.7 oz)

IO.2mm

(0.401

DRAWING NO.4 Model 700
28.7mm...""
t.!1.13").

h;

28.7
mm

1/

(1.13 .. ) ....

/1'

10.2mm
(0.40")

.
dia.

It.
20.32mm---...
(0.80")

.

Input ShIeld

Weight: 22.67 gm
(O.800z) max
Grid: 2.50mm (0.10")
NOTE: Input and Output
circuits have

separate shields.

Input
Common

I--I.

+t+++ttt+ot
Output
++H+++ Common
ltiUt~.t+i! _

~~++t ... +

+VIN
10.2mm
(0.40")

+ V OUT

to

+!iiHiii;:

++i++++'"
I.tt
....++~OutPut
I I
Shield

C4 -V04 +VII4

OUT

t

--J

Bottom View

- V

r--

12-6

Weight: 25 grams (0.9 oz.)

Grid: 5.0Smm (.201

BURR-BROWN®

PSB100

IElElI

REGULATED DC POWER SUPPLY
WITH BATTERY BACK-UP

DESCRIPTION
REGULATOR SOARD

Customers building critical control systems can now
purchase a power supply with a self-contained battery
back-up, eliminating the need for separate, expensive
UPS systems.

RL

-S CSl-t-----""""

1!lJ-12 ADJ

-12
-12

:=~i ~L.!~----'

PS B I 00 supplies all common voltages used in microcomputer systems, such as the M ultibus™ system.
The supply unit includes an internal 24V battery
pack and charger, three TTL outputs and LED
indicators that indicate power system status. Signals
are provided for line power loss, low battery, and
very low battery. Internal batteries provide a minimum of 30 minutes back-up at full load. An external
24VDC battery pack can be added to extend back-up
time.

I!l!

+12
ADJ

+12
+12
h.c.

\9

~~i ~fl~----'
+S

-S &-11--+----,

A 6ASS
I:l FUSE

RET
RET

:;~r_~~~~~
+5 ADJ

I!l!

INPtlT
Line Voltage
Battery f Internal)

12) 18-24 VAC 2.SAHR

Une Fuse

1.SASB-115VACI.75ASB-230VAC

(1)

(tI100-130VAC/200-260 VAC

Operation above 130/260VAC may damage unit.
115/230VAC operation is switch selectable.

(2) An external 24VDC lead s'cid battery may be connected. No fuse
protection is provided for the external battery.

OUTPUTS
+SVDC
+12VDC
-12VDC
-5VDC

±S%
±S%
±S%
±1%

RIPPLE (MAX) CURRENT CURRENT LIMIT
1S0mV p-p
11.2A
12.0A ±S%
360mV p-p
1.2A
1.5A ±S%
360mV p-p
1.2A
1.SA±5%
40mV
100mA
NONE

OPERATION
I. Insure proper line and load .connection to unit.
2. Insure.proper line voltage selection, liS! 230V AC.

3. Place AC switch in ON position; the AC indicator
should light. The unit is now operating.
4. Place BATTER Y switch in ON position. Battery
back-up of supply is now operational. Note that
the supply is not battery-startable.
5. To turn unit off once started, both the AC switch
and the BATTERY switch must be in the OFF
position.

MultibusTII - Intel Corp.

Internalional Alrporllndustrlal Park· P.O. Box 11400 . Tucson. Arizona 85734 . Tel. (6021 746·1111 ··Twx: 910·952·1111 • Cable: BBRCORP . Telex: 66·6491

12-7

BATTERY BACK-UP
PSBIOO contains a 24VDC 2.5 AHR lead acid
battery pack. The battery is charged and maintained
by an internal battery charger. Upon loss of AC
power, the battery will maintain operation of a full
load for 30 minutes minimum if fully charged. An
external 24 VDC rechargeable battery may be connected if desired. If an external battery is installed, the
internal battery should be disconnected (remove
battery fuse).,The internal charger will supply 24VDC
at SOOmA to charge or maintain external batteries.

T
7.2"

l~~
1"".------13.S"------...f.1

BATTERY CHARGER
24VDC at 500mA
Low battery (LB) indication 2.1 VDC
Very low battery (VLB) indication 19.5VDC'

LB and VLB indication are operational only during
battery discharge cycle.
Three TTL compatible outputs are provided on the'
charger circuit board for low battery (LB), very low
battery (VLB) and line loss (LN). All three outputs
are active low.

tf.¥=I;;

.0"-11
5.750"~
~

BATTERY CHARGER

0
0
@

+24 ADJ

iJj ADJ
GND

~

ijiJi }
rn

.<;.

;;:

@
@

iJj

TTL
OUT

24VAC INPUT
24VAC

12-8

;1

~
13.750"

BURR-BROWN®

PWR70

IElElI

ISOLATED DC/DC CONVERTER
Low Cost-Unregulated Outputs
OUTPUT POWER TO 3 WATTS
FEATURES

APPLICATIONS

• OUTPUT POWER TO 3 WATTS

• SPOT REGULATOR

• HIGH ISOLATION VOLTAGE
2000VDC

• POWER FOR DATA ACQUISITION.
OP AMPS. ETC.

• SIX-SIDED SHIELDING

• PROCESS CONTROL

• INPUT AND OUTPUT FILTERING

• PORTABLE EQUIPMENT

• LOW PROFILE PACKAGE
0.4" HIGH

• TEST EQUIPMENT

DESCRIPTION

Six-sided shielding suppresses electromagnetic radiation which could disturb sensitive analog measurements or interfere with system timing signals. Input
filtering minimizes reflected ripple current. Output
ripple voltage and switching transients are reduced
by filtering the PWR 70 outputs.
Momentarily connecting an output pin to the output
common will riot damage the PWR70. Short circuit
protection is accomplished by using power
MOSFETs in the PWR70's input circuitry.

The PWR 70 is a single-channel. dual-output DCI DC
converter designed for general purpose power conversion applications where high efficiency is more
important than load regulation.
The PWR70 provides a plus and minus output
voltage approximately equal to the input voltage
magnitude. It operates over an input voltage range of
IOVDC to 18VDC. Isolation voltage is a minimum
of2000VDC.
SIMPLIFIED CIRCUIT DIAGRAM

.--------------------::::J

r-'-'-'-'-'- -.-.- -.- -'-'-'
I

RECTIFIERS

.

OUTPUT
COMMON
CONTROL CIRCUITRY
'Your
'YIM

____________

_:::J

International Airporllnduslrlal Park· P.O. BOll 11400· TuCS1lll. Ariz1lna 85734· Tet (fII2J 746-1111 • Twx: 91Q.!152·1l11 . Cable: BBRCORP ·Telex: 116-&191

12-9

SPECIFICATIONS
ELECTRICAL

MECHANICAL

At TA "+25'C, +V'N = 15VeC, and lOUT" ±15mA unless otherwise noted.

PARAMETER

CONDITIONS

INPUT
Rated Voltage
Voltage Range
Input Current

MIN

MAX

TVP

UNITS

±10
±10

vec
vec
mA
mA
mA,pk
rT)A, pk

10G
6

vec
I!
pF

15
18

10
'OUT =± 3mA
lOUT" ±33inA
lOUT" ± 3mA
lOUT" ±33mA

Ripple Current

25
100

ISOLATION
Rated Voltage
Resistance

2000

Capacitance
Leakage Current

V'SO

OUTPUT
Rated Voltage
Voltage Accuracy
Rated Current
Current Range
line Regulation
Load Regulation
Ripple Voltage

=240VAC, 60Hz

~A

1
±15

±80

vec
%
mA
mA
VIV
mVlmA
mV. pk
mV. pk

+85
+125
+150

'c
'c
°c

3
±15
±1oo

0
10VeC c, V,N ;;, 16VeC
±3MA j:; 'OUT ;:>- ±33mA
'OUT
±3mA
'OUT
±33mA

1.08
35
±10

=
=

Pin numbers shown
for reference only.

Ltjf:"-::{

~G ~l!+IN + v~~

G

"+" denotes

TEMPERATURE
Specification
Operating
Storage

-25
-55

-65

L -

j..

~

miSSing pin.

NOTE: Input and output circuits have
separate shields.

OIM

l

~
"iii

"iii

E
0

'E

Z

z

E

E

c

c

0

e

e

u.

u.

c

c
.2
1ii

0

:;
'>

-2

"

0

I-

"

0

0

.~

0

>

G

I-

0

>

-35
Output Current (mA)

-5

25

55

65

115

Ambient Temperature (Oe)

fIGURE I. I.oad Regulation.

27.31

1.015

1.135

27.31

28.83

.350
.038

.410

8.89

10.41

.042

0.97

1.07

.:200 BASIC

5.08 BASIC

.212

.312

5.38

7.92

.170

.350

4.32

8.89

.SOO BASIC

20.32 BASIC

.100BASIC

2.54 BASIC

212

145

CONNECTION DIAGRAM
BOTTOM VIEW

FIGURE 2. Temperature Drift.

V+

-VIN

ABSOLUTE MAXIMUM RATINGS

Input Voltage ....
Output Current. ..
Output Sh"ort-Circult Duration.

5.38

2.84

Material: Black Epoxy
Weight: 22.67 gm (0.80 oz.)
Grid: 2.50mm (O.'O~)

"

-4

1135

.112

-1

MILLIMETERS
MIN
MAX
28.83

INCHES
MIN
MAX
1.075

+VIN

..................... t8VeC
.. ........... ±150mA
. .......... Momentary

COM
.... IN
V
+IN

+VO~

OUTPUT

COMMO

--

-VOUT

NOTE: Inpul and oulpUl circa", have sep.rate "'laid&. Inpullhleltlls connlCl8d
to -V ,N• Oulpullhleld II connected to
oUlpul common.

12-10

BURR-BROWN®

,so

IElElI

700/700U

DC DC (I)NV

~
iCG

ISOLATED DC-TO-DC CONVERTER
FEATURES

APPLICATIONS

•
•
•
•

• INDUSTRIAL PROCESS CONTROL
• MEDICAL INSTRUMENTATION
• TEST EQUIPMENT
• DATA ACQUISITION SYSTEMS

HIGH BREAKDOWN VOLTAGE 5000V PEAK
LOW LEAKAGE CAPACITANCE = 3pF
SHIELDED AND UNSHIELDED UNITS
COMPLETELY SPECIFIED

BENEFITS

DESCRIPTION

• HIGH VOLTAGE RATING PROTECTS
EXPENSIVE INSTRUMENTATION
• LOW LEAKAGE CURRENT PROTECTS HUMAN LIFE
• EXCELLENT ISOLATION CMR IMPROVES
SYSTEM PERFORMANCE
• SHIELDING PREVENTS ELECTROSTACTIC AND
EMI PROBLEMS

The Model 700 converts a 10VDC to 18VDC input to
a dual output of the same value as the input voltage.
The internal hybrid integrated circuit reduces size
and cost. A self-contained frequency stable 130kHz
oscillator drives switching circuitry which is designed
to minimize the common problem of spiking due to
transformer saturation. Regulation and short circuit
protection. if desired. can easily be added (see Figure
3). Models 700 and 700M have separate internal
input and output shields. Models 700U and 700UM
have no internal shields.

+IN

V+

x

o
Inpal

OIclllllor

Recllflera and Fillera

I+VOUTl
COM
V-

Shield
(-VOUTl

(Outpul Shield)
Madel 700 CirculI Ollgram

Inlarnatlanal Alrporllndustrlal Park· P.O. Box 11400· Tucson. Arizona 85734· Tal. (602) 746·1111· Twx: 910-952·1111 • Cable: BBRCORp· Telex: 66·6491

12-11

SPECIFICATIONS

MECHANICAL

ELECTRICAL
Typical at 25°C with 1SVDC supply unless otharwlse noted.

7OOI700M

MODEL

I

700UnoGUM

INPUT
Voltage Rangell )
Current at ·±3mA Load
Current at ±30mA Load
Ripple 'Currant at ±3mA Load
Ripple Currant al ±30mA Load

10V to laV
20mA
±100mA.max
±3mA.peak
±100mA. peak

NOTE;

L.adl In tru. position within .015"
{'3Brnml R • MMC et seetinD plene.

ISOLATlON(2)
-

4200V. p
. 1500V. p
10Gllil SpF
1~A. max

Voltage. Tesl. Ssec al SOHz
Voltage. Continuous. deraled
Impedance
Leakage Currant at 240VlSOHz

Pm numbers shown
for reference only

SOOOV. P
2OOOV. P
10GIIIi 3pF
1p.A, max

OUTPUT
Your al ±3mA to ±3OmA Load
Operating Current total 01 both outputa
Sa.. Nondestructive Current at 25°C
Sensitivity 10,Input Voltage
Load Regulation
Ripple Voltage at ±3mA Load
Ripple Voltage at ±30mA Load
Balance 01 +V and -Vat +1 = -I

±VIN with ±1V tolerance
SOmA. max
120mA. max

p.n

~ -

1.08VN

l

-.-j

INCHES
MIN
MAX

35mVlmA
±15mV. peak
±80mV. peak max
±2OmV

A

1.075

1.135

27.31

28.B3

1.07.

1.13&
.410

27.31

28.83

B.89
0.97

10.41
1.07

c

TEMPERATURE RANGE
Operating
Storage

-............. .. denoles mISSing

I

-25°C to +85°C
-55°C to +125OC

NOTES:
1. Derate to 16V max between +VIN and -Y,N 'above 700C.
2. A medical grade unit Is available which is 100'110 screened to Patient Connected
Circuit requirements lor Ihe leakagecurrenl I par. 27.51 and dielectric withstand
Yoltage I par. 31.11' 01 UL544. Specify 700M or 700UM.

D

.350
.038

G

.200 BASIC

H

.212

.04.
.312

5.08 BASIC
5.38
7.92

.170
.350
.800 BASIC
.100 BASIC
.112
.212

4.32
8.89
20.32 BASIC
2.54 BASIC
2.84
5.38

Me.riel: Bleck EPOII';'
Weight: 22.67 11m 10.BO oz.1
Grid: 2.S0mm 10.10'"

_pare.

NOTE: Input end Output circuits h • ..,.

~ 3\

!

\ ~""-~

!i
j

I.'

~~

-

,

.1-21
>j.-3
-4
-S

2n

EQual Load far ±V

.'\..

21

Varying'
Output'

"'"

Mil SlIe:
Load' -

10

I

I

I

I

1
±3mA Load, .....

Fixed Output'
~

~

"-.;

......J.
........ .........

-"

20

shields.

~

30· 40'
OUtput CurnnllmAl .

501

FIGURE 1. Load Regulation.

1
-2

..~ """
~

JI'

l= ::
fOOn

roti

oa,

-55, -35 -15 +5 +25 +55 +76

Amblll1l TI..perature lOCI

FIGURE 2. Temperature Drift.

+

. FIGURE 3. Short Circuit Protection.

·For one output with constant 1SmA
load and varying current on other output.
rA minimum load of 3mA is recommended for each output t.

USE WITH ISOLATION AMPLIFIERS:
When the ModeI700/700U is used with isolation ampli.fiers such as the Burr-Brown 3650 and 3652 special'
attention should be given to current ratings to avoid over
designing. Since the isolation amplifiers do not draw
maximum current simultaneously from the V + and V-

Model 700 (700 U terminals, it is possible to drive more
isolation amplifiers per ModeI700(700U than one might
initially expect. The Model 700(700U is capable of
providing a total output current of 60mA balanced or
unbalanced between the two outputs. A minimum load of
3mA' is recommended for each output.

12-12

BURR-BROWN®

710

113131

QUAD-ISOLATED DC-TO-DC CONVERTER
FEATURES
• FOUR ISOLATED 110VDC to 11BVDC OUTPUTS
• DRIVES FOUR 3650/3652 ISOLATION AMPS
• HIGH BREAKDOWN VOLTAGE. 2200VDC TEST
• LOW LEAKAGE CAPACITANCE. BpF
• LOW LEAKAGE CURRENT. IpA @ 240V/60Hz
• LOW COST PER ISOLATED CHANNEL

APPLICATIONS
• INDUSTRIAL PROCESS CONTROL
• TEST EQUIPMENT
• DATA ACQUISITION SYSTEMS

DESCRIPTION
The Model710 converts a single 10VDC to 18VDC input
into four dual isolated outputs of the same value as the
input voltage. The converter is capable of providing a
total of 76mA at rated output voltage accuracy and can
provide isolated power to four independently isolated
3650/3652 optically coupled isolation amplifiers with the
entire assembly mounted on one 5" x 7" card.
Extensive use is made of hybrid integrated circuits to
reduce size and cost. A self-contained frequency stable
130 kHz oscillator drives switching circuitry which is
designed to minimize the common problem of spiking
due to transformer saturation.

International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. (6021 746-1111 . Twx: 911).952·1111 • Cable: BBRCORp· Telex: 66-6491

12-13

DESCRIPTION
OUTPUT CURRENT RATINGS

ISOLATION VOLTAGE RATINGS

The Model710 is capable of providing a total of76mA of
output current divided among its eight outputs. The
maximum current available from anyone output is
shown in Figure 9. A minimum average current oOmA is
recommended for each output in order to maintain
output voltage accuracy. Thus, the current may be
balanced (such as +9.5mA and -9.5mA) or unbalanced
(such as +16mA and -3mA). The best output voltage
accuracy will be obtained under balanced conditions.
Channels may be connected in series or parallel for higher
voltage or current. For parallel operation connection of
channel I to 2 or channel 3 to 4 will result in lowest ripple.
In some cases the 710 may drive larger loads than would
be apparent from a cursory examination of the
specifications. For example, see"Figures I and 2. The
most total current drawn from the pair of +Vo and -Yo
output is 1m" + IQ (not 2 x 1m,,). For the 3650 this is a
lJIaximum of 12mA +1.2mA = 13.2mA (instead of
24mA).

It is important that the user understand the significance of
-l he

continuous derated isolation voltage specification
and its relationship to the actual test voltage applied to
the unit. Since a "continuous" test is impractical in a
product manufacturing situation (implies infinite test
duration) it is generally accepted practice to perform a
production test at a higher voltage (i.e., higher than the
continuous rating) for some shorte.r length of time.
The important consideration is then "what is the
relationship between actual test conditions and the
continuous derated minimum specification?" There are
several rules of thumb used throughout the industry to
establish this "relationship. Burr-Brown has chosen a very
conservative one: V"" =(2 X Veontinuou, "tin.) + 1000 V. This
relationship is approp"riate for conditions where the
system transient voltages are not well defined. • Where the
real voltages are well defined or where the isolation
voltage is not continuous the user may choose to use a less
conservative derating to establish a specification from the
test voltage.

*

Reference National Electrical Manufacturers
Association (NEMA) Standards Parts ICS 1-109 and
ICS I-III.

Yin

Vo

SHORT CIRCUIT PROTECTION
The circuit in Figure 3 may be added to the input of the
710 in order to protect it from damage in situations where
too much current is demanded from the outputs - such as
a short circuit from an output to its common. The circuit
limits the input current to approximately 100 rnA for an
input voltage of 15 VDC (for{3 of 2N2219 of 50) .

. FIGURE I. Typical Connection
Vin~

'J

<0:7
Voul

tI""\ /
V

20

IOUI~

I

I

'-T .1
l+~max
+lQ

2N2219

IN4148.l...~
1000

t

.......

3.6k

-IQ
1-

•

I

FIGURE 3. Short Circuit Protection

FIGURE 2. Waveforms

12-14

-VII..
+VIN

710

SPECIFICATIONS
Typical at 2SoC with I SV supply unless otherwise noted.

ELECTRICAL
MODEL
INPUT

MECHANICAL
710

lIull

Voltage Range
Current at lotal Output Current of 24mA
Current at Total Output Current of 76mA
Ripple at Total Output Current of 24mA
Ripple at Total Output Current of 76mA

10Vto ISV
40mA
10000,max
ISmA, peak
4OmA,peak

T

10.2mm
(0.40")

ISOLATION'"
Yoltage Accuruyf'l
Current for Rated Aceurac;:y: Total of all currents
Maximum Current: Anyone output
Leakage Current at 240V /60 Hz

2200V, rms at 60Hz
6OOV, rms AC. IOOOVOC
lOGO II 8pF
lilA, max

OUTPUT

Voltage Accuracy~ ~I
Current for Rated Accutacy: Total of all currents
Anyone output
Total Safe Nondestructive Current at 2S"C
Sensitivity 10 Input Voltalt!
Load Regulation 'ft,
Ripple Vollage at ±3mA load
Ripple Voltage at ±9.5mA Load
Balance of +V and ~V at +1 = -I
6V""1 vs Temperature -25"C to +85"("

See Figure S
76mA. max
6OI,DA,max
12OmA, max '
I.OSV/V
7SmV/mA
±2SmV. peak
±80mV. peak max
±20mV
3.0%

TEMPERATURE RANGE
Operating
Storage

Material: Black Epoay
Weight: 2S grams (0.9 OL)
Grid: S.OSmm (.20")
Pin: Material and 'plating composition
conform to Method 2003 (solderability) of
MIL-STD-883 (except paragraph 3.2).

-2S"C to +SS"C
-SS"C to +IIO"C

Derate to 16V max between +VI~ and ~VI~ above 70"C.
Operation down to SV is possible with reduced output current and accuracy.
Isolation specifications are applicable to input to output isolation as well as channel to channel isolation.
See disCussion on previous paae; 22OOV. rms = 3000V peak.
S. A minimum output current of ±3mA per channel is recommended to maintain output voltage accuracy.
6. Load regulation for one channel with other channels at ±9.SmA load.

NOTES: I.
2.
3.
4.

C

c

FIGURE 5. Typical Connection with Four 3650
Isolation Amplifiers.

FIGURE 4. Functional Diagram

12-15

TYPICAL PERFORMANCE CURVES

-,l'\.

4
...I

0_
>I t!'~
-;

\.

"cH

>

+
.;

e

0

> :8c
:; .!!
:;'" Q~

-I

H ,g

0

Test Condition 2
4

RF chosen for IF:::; ±9.SmA

r-.... ,V
~

~

0

z

'0

Test Condition I
RF chosen for IF::: 3mA

I/

-2

at i:±i";trxe~~7"

1

.........

"'-

1

\..

........
/V -r-+-L

I" ........
Lat terminals with variable Ri:" .......
i'

-3 RF chasin for IF = ±9.SmA

'1

-4

1 I 'I

1 1

-4

-5

-5

o

4

6

8

Output

10 12

Curre~t.

14

16

18

20

o

4

IL+ = IL_ (rnA)

10

6

60

16

~

40

0

20

't"

Maximum output current for

/

anyone output

14
:0

fr

fr
:0

:0

0

./

so

.:;:

:;

18

70

20~--~--~----~--~--~----'

>

14 16

FIGURE 7. LOAD REGULATION - unbalanced.load

FIGURE 6. LOAD REGULATION - balanced load

:l,

12

Output Current (rnA) IL+

0

Maximum balanced load
current per channel

o

12

20
10

10

o
10

12

Input Voltage
FIGURE 8. OUTPUT VOLTAGE ACCURACY VS
INPUT VOLTAGE

14

12

C ....- - . - - - ,

+VIN

16

18

Input Voltage
FIGURE 9. OUTPUT CURRENT ~ATlNGS TO MAINTAIN
OUTPUT VOL TAGE TOLERANCE

+VO

+VIN

+Vo

+VOL

-VIN

-VIN

-+-t---.

+Vo

710

710

C

L+

-VOL
C

+VO

C

FIGURE 10. Test Condition I: Balanced Load

-Vo

+Vo

FIGURE II. Test Condition 2: Unbalanced Load

12-16

722

BURR-BROWN®

11131131

DUAL ISOLATED DC/DC CONVERTER
FEATURES

APPLICATIONS

• DUAL ISOLATED ±5V TO ±IBV OUTPUTS
• HIGH BREAKDOWN VOLTAGE. BOOOV TEST
• LOW LEAKAGE CURRENT. <1!'A AT 240V/BOHz
• LOW COST PER ISOLATED CHANNEL
• SMALL SIZE. 27.9mm x 27.9mm x 7.Bmm
(IY x 1.1" x0.3")

• MEDICAL EQUIPMENT
• INDUSTRIAL PROCESS CONTROL
• TEST EQUIPMENT
• DATA ACQUISITION SYSTEMS
• NUCLEAR INSTRUMENTATION

r---~-----------------,
I

p+~------------------~

I

V+o-----.

+VOl

I

Cl

I

-VOl

I

I

E

I
I
I

+V02

-?C2
V_o----4----~

I

-V02

I

~-------------------------~

DESCRIPTION
The 722 converts a single 5VDC to l6VDC input into
a pair of bipolar output voltages of the ~ame value as
the input voltage. The convt;rter is capable of
providing a total output current of 64mA at rated
voltage accuracy and up to 250mA without damage.
The two output channels are isolated from the input
and from each other. They may be connected
independently, in series for higher output voltage or
in parallel for higher output current, as a single
channel isolated DC/DC converter.

Integrated circuit construction of the 722 reduces size
and cost. High isolation breakdown voltages and low
leakage currents are assured by special design and
construction which includes use of a high dielectric
strength, low leakage coating used on the internal
assembly.
A self-contained 900kHz oscillator drives switching
circuitry which is designed to eliminate the common
problem of input current spiking due to transformer
saturation or crossover switching.

Intemliional Alrporllndustrlal Park· P.O. Box 11400 - Tucson. Arizona 85734 - Tel. (602) 746-1111 • Twx: 910-852-1111 • Cable: 88RCORP - Telex: 66·8491

12-17

DISCUSSION
OUTPUT CURRENT RATINGS
At rated output voltage accuracy, the 722 is capable of
providing 64mA divided among its four outputs!l). A
. minimum average output current of 3mA is
recommended at each output to maintain voltage
accuracy.
Output channels(2) may be connected in,series or parallel
for higher output voltage or cun:ent.
ISOLATION CONFIGURATIONS
The fact that the two outputs of the 722 are isolated from
the input and from each other allows both two-port and
three-port isolation connections.
Figure I shows Burr-Brown's 3650 Optically Coupled
Isolation Amplifier connected in three-port
configuration. One of the 722 channels provides power to
the 3650's input. The other channel supplies power to the
3650's output. The amplifier's input and output are
isolated from each other and the system's power supply
common. In this configuration the 722's channel-tochannel isolation specification applies to the amplifier
input-to-output voltage.

Figure 3 illustrates how the 722 may provide isolated
input power to the input stage of two 3650's connected in
the two-port configuration. Power for the output stage is
provided by the system +I5V and -15V supplies. Input
stages are isolated from each other and from the system
supply. In this situation the 722's input-to-output
isolation specification applies to the amplifiers' input-tooutput voltages while the channel-lo-channel 722
specification applies to the voltage existing between "1/ P
Com I" and "lIP Com # 2."

*

MECHANICAL

~
••••••• ••
I

B

J l..
I
i.=- A ----I

L

Pin numbers shown for
reference only
Numbers may not be
marked on package.

NOTE:
Leads in true position within
0.Q10" (0.25mm) R 8t MMC
at seating plane.

[~ -,:::7.~ :::-::::

284,

Seating Plane

9

D

021
.035
.05•
.100 8ASIC
.tOO BASIC

g,

7.24

048

053

'0.89

1.:27

2.54 BASIC
2.54 BASIC

.3150
.900 BASIC

.010
.tOO BASIC

0.25
2.54 BASIC

SHORT CIRCUIT PROTECTION
The circuit in Figure 2 may be added to the input of the
722' to protect it from damage. in' situations where too
much current is demanded from the outputs - such as a
short circuit from an output to its common. The circuit
limits input current to approximately 150mA for an input
voltage of 15VDC (for fJ of 2N2219 of 50).
p+

+VOI
C,

+
v+
V'N

E
IN4148

v-

N
N

-VOl

r- +VOl
C,

-VOl

'(I) "output" denotes.liqle output terminal (+V or.~V) and: its associated eommon
(2) "chnneI'" denoteIa pair of outputs (+V and ~V) and their _ociated common

FIGURE 2. Short Circuit Protection
+ISV -ISV

I

Power Supply Common

FIPURE I. Three-Port Isolation

FIGURE 3. Two-Port Isolation with two 3650's.

12-18

ELECTRICAL SPECIFICATIONS
Specifications at TA = +25°C V,N = 15VDC C

= 0 47JJF

PARAMETER

CONDITIONS

R1 Selected per Typical Performance Curve

I
MIN

722
TYP

I
MAX

MIN

7228G
TYP MAX

I
MIN

722MG
TYP MAX

I

u-IIIiTs

INPUT
Rated Input Voltage
Input Voltage Rangel I)
Input Current

Inpul Ripple(2)

15

Total output current = 12mA
Total output current = 64mA
Total output current = 64mA
alTA ~ +85°C
Total output current = l60mA
Total output current = 12mA
Total output current = 64mA
Total output current = l60mA

VDC
VDC
mA
mA

16

5
50
105

120

120

-

-

225

275

3
6

-

-

-

-

12

mA
mA
mAo pk
mAo pk
mAo pk

ISOLATION
Test Voltages!O)

Rated Voltage(3)
Isolation Impedance
Leakage Current(4)
OUTPUT
Rated Output Voltage!S)

Output Current
Load Regulation
Ripple Voltage

Tracking Error Between
Dual Outputs
Sensitivity to Input
Voltage Changes
Output Voltage Temperafure
Coefficient

Input-te-output, 5 seconds. min
Input-ta-output. 1 minute. min
Channel-to-channel, 5 seconds, min
Input-ta-output. continuous
Channel-to-channel, continuous
Input-ta-output
Input-to-output. 240V. 60Hz

10116
1
15.4
t4.3

16.0
15.3

3

200
100
Note 5
15
35

14.2

100

50
±lOO

TSpec,flcatlon Range

V, rrns
V. pk
V
V
GlIllpF
pA

~g~
13.7

ILoad = 3mA per output
ILoad = l6mA per output
ILoad = 40mA per output
Balanced loads

=:.

•.

2500
5000
3500
2000

Iload 3mA per output
ILoad = 16mA per output
Iload = 40mA per output
Total of all outputs
Anyone output(6)

TA

V. pk

8000

15.0

VDC
mA
mA
mV. pk
mV. pk
mV. pk
mVDC

1.13

VIV

±0.02

%/oC

TEMPERATURE
Specification

ILt)ad ~ 16mA per output
Iload ~ 40mA per output

-25
-25
-55

Storage
Junction Temperature

T85
+60
+125
+125

°C
°C
°C
°C

Specifications same as 722.
NOTES:
1. For ambient temperature above 700C the Input voltage is 12.SV max. The
input voltage remains l6V max if case temperature· IS kept below 85°C.
2. External capacitor across "P+" to "V~" pins and 12H of #24 wire to VIN.
3. Relationship between test and rated is V.... = (V_ X 2) +1000V.

INSTALLATION AND
OPERATING INSTRUCTIONS
Typical application connections for the 722 are shown in
Figures I and 3. Primary power (VIN) is applied at the
"P+~ and "V-" terminals. The common or ground for VIN
may be connected to either "P+" or "V-"; the only
requirement is that "P+" and "V+" must be positive with
respect to "V-.~
Power for the internal oscillator and switch drivers is
derived from the primary power by a voltage dropping
resistor RI. The value ofRI as a function OfVIN is shown
in the TYPICAL PERFORMANCE CURVES section.
Alternately, voltage for the "V+~ terminal may be
obtained from a separate source. "V+" should be +5V to
+7.5V positive with respect to "V-~. If a separate source is
used, tlie V+ input must be applied before the "P+" input
to avoid possible damage to the unit. P+ and V+ must

4. Reference UL544, paragraph 27.5, Leakage Current.
5. See "Typical Performance Curves".
6. A minimum output current of 3mA at each output is recommended to
maintain output voltage accuracy.

remain positive with respect to V-at all times (including
transients). If necessary, diode clamps should be put
across these inputs.
The "E" pin enables the converter when connected to
"V+" and disables it when connected to "V-."
An external capacitor, "C", (O.47/LF ceramic) is used to
reduce input ripple. It should be connected as close to the
"P+" and "V-" pins as practical. Input leads to these
terminals should also be kept as short as possible. Since
the 722 is not internally shielded, external shielding may
be appropriate in applications where RFI at the 900kHz
nominal oscillator frequency is a problem.
Each output is filtered with an internal O.22/LF capacitor.
Output ripple voltage can be reduced below the specified
value by adding external capacitors up to IO/LF between
.each output and its common.

12-19

TYPICAL PERFORMANCE CURVES
Specifications at

-r. = +25°C. Y,N = t5VDC: C =0.47J.1F. R, salectad per typl~al pe-;"o~mance curve.
MAXIMUM SAFE OPERATING
TEMPERATURE VS TOTAL
OUTPUT CURRENT

SELECTION OF R, OR EXTERNAL
VOLTAGE V+ FOR MINIMUM INTERNAL
POWER DISSIPATION

Maximum Output Current
From Any Single Output

<16mA

>13

:>

II

" 139
F
10
'0

>
S

0.

.so

II

I~
9

-<8

V+EXT

16mA to
~OmA

82011

StOll

82011

51011

20011

51011

200ll

Oll

200ll

Oll

6.5V

~

~

~

§
Q >13r ---;----+----t--:c.

~

~75

E

75~&
~ ~

,i50

50~~

~

~

E

7.5V

~

25~

125

-

g

C <58 ......--_t--.......,h£:

~

Oll

18

~ 100 ~----_t---'''''''.......''''''---+------lloo §

.>30mA

1.3kll

OUTPUT VOL TAGE VS INPUT VOL T AGE

125 r-----"'T"'-----,.----.----,25

~

0

9.0V

o

SINGLE-CHANNEL LOAD REGULATION

3~4----L---~8~--~--~12~--L---~'6

150
100
50
Total Output Current(2) . mA·

Inpul Vottage V

CHANNEL-TO-CHANNEL INTERACTION

SINGLE OUTPUT LOAD REGULATION

>
z

>

~

Jll

.~
0.

o
13~0----~20~---4~0~---6~O~--~8~O--~1~00'

'3~0----2~Q~--~4~0--~6~0~--~~~--~'00

Output Load Current. I ILl mA.

Output load Current, IL ! rnA I

Output Load Current, IlL I rnA

PARALLEL OUTPUT UNBALANCED
LOAD REGULATION

PARALLEL OUTPUT BALANCED
LOAD REGULATION

OUTPUT-TO-OUTPUT INTERACTION

>

;;;
0'

~

~15~----~--~~----+-----+-----~

~

f

>

~ 14

3_ 141---+--'

l1!
'0

~

'0

~

0.

S

S

o

o

80
·mA

100

'3~O-----4~0----~8~O~--~1~20~---'~6~O--~2~OO'
Output Load Current,! IL I rnA

Notes:
,1, Using a 104mm )( 19mm x 1.6mm aluminum strip mounted to the bottom of the case with heat sink compound:
·2 Total output current is the sum of the currents for each individual au,tput.
.

12-20

130~----~40-----8~0~--~12~0~--~16~O--~2~00
Output Load Current. IL

rnA

724

BURR-BROWN@

IE:lE:lI

QUAD ISOLATED DC/DC CONVERTER
FEATURES

APPLICATIONS

• QUAD ISOLATED ±8V OUTPUTS

• MEDICAL EQUIPMENT

• HIGH BREAKDOWN VOLTAGE. 3OO0V TEST

• INDUSTRIAL PROCESS CONTROL

• LOW LEAKAGE CURRENT. 1

~

~
~

~

~

14

~12

~

ri

10

r=

~

-:I: lour = 24mA

.A~
= l28mA
~ I'{':I:(I.loUT=±16mA)
~
i I I

(1.=±3mA)

6

514
2

o
o

5
10
IS
INPUT VOLTAGE (V)

w

~ I.OJ-----+--+~?!iI_+--__1
OIl

t~ O.sl---t--""fI---I---I

~

O~O--~S~~~I~O--~I~S--~W
INPUT VOLTAGE, V,N (V)

~ 8.'

j

+

TEST CONDITION I
(Balanced Load)

I
IF =3mA

~

8

~

IF

IT
=!6mA

.. 7.S

-=-

~

~

V,N

7

o

o

Test Condition 2
(dual output, unbalanced load)

m

w

~

~.

~ 8t-~~~-4~~~~~--I

.~

~

OUTPUT CURRENT, 1.+ (mA)

12-24

_=_I6mA
-t_---I__..

7.S t-R_F_C_hosenl-_I_O'-tI_F

~

5 7t--+--4--t--~--I

§

LOAD REGULATION·
(lnterclwmel with unbalanced load)

9

~ 8.S .....<::-+-~.,--~:-+-:--I

Test condition 1

(dual output, balanced load)

w

40
10
~
~
OUTPUT CURRENT 1.+= I.· (mA)

TEST CONDITION 2
(Unbalanced Load)

DATA ENTRY AND DISPLAY TERMINALS
MICROTERMINALTM

• Operates on factory floor, on the production line,
in labs, computer room or office.

Pioneering New Concepts
In Data Collection

Easy To Interface
• Serial ASCII communications.
• EIA RS-232-C/CCITT V.24, 20mA current loop or
RS-422.
• 110 to 19,200 baud.
• Up to 63 Microterminal control panels per serial
interface.
• Digital I/O available.
• Buffered data entry to reduce on-line time, or
data transmission on keystroke for conversational
mode.

If your system's data entry/control/display requirements are sophisticated but limited in volume, you
don't need to buy big, expensive and fragile CRTs
or printing terminals to do the job efficiently.
"MicroterminaI T. " terminals-uniquely flexible in application versatility-are designed expressly to fill
the human interface demands of widely dispersed
control and communications networks-in machine
and process control, energy management systems,
inventory control and factory floor data collection,
and information processing systems. MicroterminalsT. , because of their interface flexibility, appearance, size, durability, and easy installation,function
equally well as consoles and control centers for
instruments and small systems. They also perform
as I/O terminals in diagnostic applications.

Easy To Use
•
•
•
•

Bar code reader models available.
Magnetic stripe readers available.
Full alphanumeric and simple numeric keyboards.
One stroke function keys enter complex preprogrammed data strings.
• Function indicators to confirm those instructions.
• Indicators to report operational status and steps.
• Tactile touch key feedback that confirms data.
entry.

Rugged And Reliable
• Tough-100% solid state (no video tubes, no moving parts).
• 0 to +60°C operating temperature range.
• Dust proof/water resistant front panel protects
display, indicators, keys.

Practically Priced
•
•
•
•
•

Easy To Design In
• Very compact (8.5" X 4.5"), mounts on flat surface.

Low cost terminal functions.
One-year warranty.
Complete-no add-ons or interface.
Simple system integration.
Special operator training not required.

MICROTERMINAL SELECTION GUIDE
General Purpose

Low Cost

Model Number

Oigltall/O
TM71

TM77

-300-XX

TM27

TM70

TM76

TM71

TU77

-110

-I/O

TM71M

TM71B
-XX

TM77B
-XX

AlN

TM25

Display TypelU

BarCode
Readerl7l

Mil
Spec

Mag Stripe
Readerl 71
TU71MS TM71MS
-xx
-XX

HEX

HEX

AlN

AlN

AlN

AlN

AlN

AlN

AlN

A/N

AlN

8

8

12

12

16

16

16

16

16

,.

AIN

Number of Characters in Display

16

16

16

Internal Buffer Size (Input and output)

6

6

36

36

60

60

60

60

60

60

60

60

60

Keypad TypelU

HEX &
NUM

HEX or

AlN

NUM

AlN

NUM

AlN

NUM

AlN

AlN

NUM

AlN

NUM

Data Transmlssion l2l
(Nonpolled Mode)

Block

m

Echo

Echo

Block

Block

Block

Block

Block

Block

Block

Block

Blook

Communication InterfaceQ/

RS232

RS422

RS232

RS232

RS232

samBas

same as

same as

RS232

&Cll

&Cll

&CIl

&CIl

TM71

TM71

TM71

or RS422

Multidrop Capacity

6

63

,.

,.

RS232
or ell

Function Keysi4I

7

6

6

6

Baud Rate

300

300'0
4800111

300&
1200

300&
1200

Digital Inputs

No

3

No

No

Digital Outputs w/LEO's

No

•

2

User EPROM

No

No

8~Bit

110 Port

I Output w/LED's
I Bidirectional

NUM

TU71B

same .. same as same as
TM718

TM71B

orRSW

,.

63

,.

63

63

16

16

16

110to
19.200

110to

110to
19.200

110to

110to

9600

110to
19.200

19.200

19.200

NO"

No"

No

No

No

No

No

2

2"

~

2

2

2

2

2

Ves

Yes

Yes
Yes
Yes

V..
V..
V..

No

No

No

No

No

150r83

1501'63

,.

15 or 83

,.

15 or 63

19.200

11010
19.200

110to
19.200

No

No

2

2

No

No

"
110to

Nt

No

No

No

No

No

No

No

No

No

No

No

13-1

"

N/A

63

No

No

No

No

No

No

Yes

Veo

V..

Yes

, MICROTERMINAL SELECTION GUIDE
General Purpose

Low Cost
Power Supply

15VDC

8-12VOC
voltage
regulator

5VDC

5VDC

5VDC

Digital 110

5VDC

5VDC

5VDC

MIL

BarCode

Spec

Rea

0,

• Runged, Compacl.Panel·Mount Case
• Tough, Water and Dust Resistant
Front Panel
• Mounts with Four Screws on Any
Flat Surlace
• 0 to +60' COperating Temperature Range

SYSTEM INTERFACE
• RS·232·C and 20mA Current loop or R8-422
Connection on Rear Panel
• Polled: Ito 15 Terminals on a Single
Serial Interlace
• Power and Signal Through a Single
Connector
• 110 to 19,200 8aud
• Optional EPROM for User·deflned Function Keys
• 10 TTL Outputs Controlled by Host CPU
• 8·line TTllnpul/Output Port Controlled
by Host CPU

Host CPU Programmable
Keyboard lockout

SPECIFICATIONS
Common To All
MICROTERMINAL ™ Products
ENVIRONMENTAL
OOC to +60o C·
95% Relative Humidity,
Non-condensing
MECHANICAL DIMENSIONS
Width: 21Smm (8,5")
Height: 114mm (4,5",
Thickness: lSmrT) (0,6"); 35mm (1.35")
for TM71 Band TM77B;
22mm (0.85"; for TM71M
KEYBOARD
Sealed
Tactile feedback
·O"C 10 +50"C on "8" models.

OPT·05: Po_red Desk-Top Stend.

COMMUNICATIONS
PROTOCOL SUMMARY

Provides a 15 degree mounting base for
all "70" Series Microterminal products
except TM71 Band TM77B. Provides +5V
supply for operation.

HOlt SYltem to
MICROTERMINAL ™

DTP-D5E designed for 240VAC input
supply:

Input message
Request transmit buffer
Clear all"
Clear input buffer·
Define function message
Delete function message
Delete all function messages
OutputtoAl
Output to A2
Scroll display
Flash display·
Blank display·
Keyboard lockout
Set turnaround time·
Re-transmit last message
Remote Enter (to test com lines I·
Read Port A, ASCII or Decimal·
Output to Port A, ASCII or Decimal·
Port A input/output continuous ASCII
or Decimal·
Halt continuous 110·
Output to Port B·
Auto/manual wand·
Extend control mode·
Audible alarm control·

PSX·24: Plug-in transformer provides
24VAC supply for TM71 Band TM77B'
operation. PSX-24E for 240VAC input
supply.

ORDERING
INFORMATION
TM25-300HT
TM25-300NT
TM27
TM71M
TM71
TM71-IIO
TM77
TM77-'IO
TM70
TM76
TM71B-12
TM71B-22
TMnB-12
TM77B-22
DTP-OS (E)*

nonpolled, hex keyboard
non polled, numeric
keyboard

complete model number
all options inCluded

RS-232-C
RS-422
RS-232-C
RS-422
Desk-Top Stand and
Power Supply
Plug-in 24VAC Supply
PSX-24 (Er
(Bar Code Readers 1
·240VAC input supply

MICROTERMINAL ™

to HOlt SYltem
Output message
Output already polled
Port A data·
Acknowledge·
Negative acknowledge·
* Not available on all models

Mating Connectors
Communications (and power) connector all
models except TM27: DB-2SP. Burr-Brown
2525MC connector kit includes a DB-25P.
2525MC not included in baSic model above;
must be ordered separately if needed.
110 connector for TM71-1/0 and TM77-1I0
required in addition to communications
connector. 110 connector is 20 Dins - two
parallel rows of 0.025" (O.64mm) square posts
on 0.100" (2.S4mm) spacing. BERG 489-005
and 65 489-007 are ribbon cable connectors.
Burr-Brown part number 2020MC is a BERG
65489-007.
TM27 connector: 26-oins, 2 parallel rows of
0.025" (O.64mm) square posts on 0.100'
(2.54mm) spacing.

Model TM25 Only
HOlt System to
MICROTERMINAL ™
Input message
Clear
MICROTERMINAL ™

to HOlt SYltem
Output message

13-7

yMC9DD

a communications processor for .

..

FACTORY FLOOR DATA COLLECTION SYSTEMS
.•• using Microterminals ..•
You can feed up to 128
Microterminals into one
host pprt using-

TMC9DD
HOST

TMC900 - a communications processor
- offers an integrated, off-the-shelf data
collection system. It controls, collects,
and processes data from dozens of Microterminals and provides an economical
solution to many problems associated
with factory floor data collection systems.

---------- -ACCIIIIm

1m

......

_IT.TIII. lit I

IIIE1l1111'--.

_1IIIPECTlIII

QCBIIIII

...... '''llIIIIlIIl.l

~._.'.

TIGl...

IIIIIfEIUU

WIIIISTlTIDlIIU

terminalaper
c;lla.nnel - for a total

input capability of 128
Microterminala

......

TMC900 interlaces as many as 128 Microterminals to a single communications port
in the host computer. In addition, it also
performs such essential tasks as terminal
polling, local validation, error recovery
and basic transaction processing. Definitions of as many as 100 transactions can
be down-loaded to the TMC900. Each of
these. can have up to 10 prompt/reply
editing specifications. Unless specific
validation by the host is specified, the
host will receive only the variable data for
the transaction - tagged and time stamped
- when the inputs are complete.

TMC900 t1ARDWARE SPECIFICATIONS
CenlralP_
- 8088 microprocessor at 5MHz
- 2 serial 110 paris for asynchronous communication
• Host Computer RS-232 or R8-422 to 19.2K baud
• Local Console RS-232 to 19.2K baud
• TMC-TMC Link for redundant operation
• High speed, interrupt-driven parallel interface to
Peripheral Processors
- 128;( bytes of RAM
- 128K bytes of ROM
. - Realtime, Multitasking Operating System
- Time of Day Clock
- S.A.S.I. Hard disk interface

.....p".ral Proceseor(a]
(Terminal 110 Processors, max 2 Per System)

Optional Power SUpply

-Z80A microprocessor at 3.7MHz
- 2 or 4 Terminal Line! - RS-422 or 20mA current loop
- Up to 16 Microterminals per line
- 8K bytes of RAM
- 16K bytes of ROM
- Realtime, Multitasking Operating System

- Battery Backup
-115VAC or 24 VAC
-- Integral sealed dry lead-aCid batteries
- External Battery (24VDC) Connection
- Provides full system operation
• 30 minutes nominal
• 60 minutes maximum on full charge

Front Panel Status Indicators

Dllk Storage Syllem (optional)

- Nine diagnostic LEOs
• Host Port TX, RX
• Console Port TX, RX
• Link Port TX, RX
.Run (CPU)
• Poll (indicates active polling of Network)
• Power

- 5-114" Winchester Type
- 5Mb unformatted storage capacity
-19" Rack Mount

13-8

MICROCOMPUTER 1/0 SYSTEMS
This full line of ",C compatible I/O .~oards is available
off-the-shelf. Design features let you put your microcomputer-based system together fast, using these analog
and digital I/O's that offer: simple software requirements; memory-mapped designs; up to 64 input channels

per board; analog inputs and outputs on the same board;
9- or 12-bit resolutions; software programmable gains;
relay outputs; isolated digital 1/ O. Plug compatible with
Int~l; DEC, National, Motorola. Rockwell, Zilog, Synertek, AMC and others.

SELECTION GUIDE
MULTI BUS· ANALOG 1/0
Inputs
Model
MP8304
MP8305
MP8316-V
MP8316-1
MP8418
MP8418-AO
MP8416-PGA
MP8416-PGA-AO
".1P8416-EXP
MP8418-ISOE
MP8430
MP8450
MP8608
MP8606-AO
MP8616
MP8616-AO
MP8832
MP8832-AO

Analog
Input

Analog
Output

High
Level

•
•
•
•

•
•
•
•
•
•

•
•
•
•
•
•
•

111
111

•
•
•
•

•
•
•
•

•
•
•

Low
Level

•
•
•
•

'"
111

111

•
•
•
•
•
•
•
•

•

'"

•
•
•
•
•
•
•

Number
Channels

Analog
Reaolutlon
(bits)

Input

12
12
12
12
12
12
12
12

Price
Output
4

4
18
18
15DIF131 SE
15DIF131 SE
15 DIF131 SE
15DIF131 SE
48 DIFI96SE
16DIF
16DIF
16DIF
8DIF·
8DIF
16SE
18SE
32 DIF/84SE
32 DIF/84SE

'"

III

12
12
8
8
8

8
8
8

2
2

Features
Individual D/A converters
MP8304 without cable
Low cost per channel
4 to 20mA Inputs
Realstor progrsmmable gain
Resistor programmable gain
Software programmable gain
Software programmable gain
Analog Input expander
400V 18Olation

Exc;:itatJon resistor compensation

2
2
2

l000V transformer 180lated
Low cost
Low cost
Low cost
Lowco.t
Low cost
Low cost

($)
1-49
725
590

550
850
675
850

n5
835
485
750

850
1495
550

695
550
695
850

850

Page
14-45
14-45
14-49
1_
14-51
14-51
14-51
14-51
14-55
14-57
14-58
14-60
14-69
14-69
14-119
14-69
14-69
14-69

MULTlBUS· DISCRETE 1/0
Digital
Input

Model
MP801
MP802
MP810
MP81D-NS
MP81D-LV
MP81D-AC
MP810-DB
MP820-05
MP82D-15
MP821-Q5
MP821-15
MP830-72

•
•
•
•
•
•
•
•

Number
Channels

•
•

16
32
24
24
24
24
24
5
15
5
15
72

180lated

Features

•
•
•
•
•
•
•
•
•
•
•

Relay output
Relay output
Contact closure input
Voltage Input
Low voltage Inputa
AC senae Inputs

Debounce circuit
Count to 65,536
Count to 65,536

Time measurement

Time measurement

Prlce($}
1-49

Page

350

1'4-8

575
450
375
375
475
460
425
700
425
750
450

14-8
14-10
14-10
14-10
14-10
14-10
14-12
14-12
14-12
14-12
14-13

~

Output read back
_.. ...
(I) Must be used WIth MP8418, MP8418-AO, MP8416-PGA or MP8416-PGA-AO which govern MP8416-EXP or MP841a-ISOE performance.
..

NOTES:

••

Digital
Output

14-1

D

..

MOTOROLA MICROMODUlES ANALOG 1/0
Inputs

Model
MP71 04
MP720a
MP7216
MP721 a
MP7408
MP740a-NS
MP7408-AO
MP7408-NS-AO
MP7432
MP7432-NS
MP7432-AO
MP7432-N5-AO
MP7504
MP760a
MP760S-1

Analog
Input

Analog
OutP~t

•

•
•

•

•

•
•

•
•

level

•
•
•
•

•
•
•
•

•
•

•
•

•
•

•
•
•

•
•

low

•
•
•
•
•
•

•
•

•
•

High
Level

•

•
•

•

•

•

Analog
Resolution
(bits)
12
12
12
12
a
a

Number
Channels
Input

General purpose"
General purpose
General purpose
Low cost
LoweDst

4
a DIF/16SE
a DIF/1IiSE
16SE
a DIF/16SE
a DIF/16SE
a DIF/16.SE
a DIF/16SE
32 DIF/64 SE
32 DIF/64 SE
32 DIF/64 SE
32 DIF/64 SE

8
8
a
a
a

8
a
12
12

Features

Output

LoweDst
Low cost

2
2

LoweDst
LoweDst
Law cost
Law cost
Low cost
Isolated-fused outputs
200VDC protection
Fused inputs

2
2
4

aDIF
aDIF

Page
14-33
14-33
14-33
14-37
14-39
,.4-39
14-39
14-39
14-39
14-39
14-39
14-39
14-41
14-43
14-43

MOTOROLA MICROMODUlES DIGITAL 1/0
Model
MP701
MP702
MP710
MP71Q-NS

Digital
Input

Digital
Output

Number
Channels

•

16
32
24
24

•

•
•

Isolated

"Features

' Page

•
•

Reed relays
Reed relays
Dry contact closures

14-4
14-4
14-6
14-6

•
•

Wet contact closures

DEC Q-BUS ANALOG 1/0
Inputs
Model
MP1104
MP1216
MPI216-PGA

Analog
Input

Analog
Output

•

•

High
level

low
Level

•

•
•

•

•

Analog
Resolution
(bits)
12
12
12

Number
Channels
Input.

Output

Features

Page

4

Individual CIA converters
Resistor programmable gain
Software programmable gain

14-14
14-16
14-16

32SE
32SE

ZllOG MCB ANALOG 1/0
Inputs
Model
MP2216
MP2216-AO

Analog
Input

Analog
Output

•
•

•

High
Level

low
level

•

•

•

•

Analog
Resolution
(bits)
12
12

Number
Channels
Input
32SE
32SE

Output

Features

Page

2

Resistor programmable gain
Resistor progrltmmable gain

14-19
14-19

STD BU::' BOARDS
Model

Function

MP6102-0
MP6102-1
MP6202-{)
MP6202-1
MP6202-2
MP6303-8

CPU
CPU
Memory
Memory
Memory
Analog Input

MP6303-16

Analog Input

MP6303-24

Analog Input

MP6303-32

Analog Input

MP6304
MP6305-4

Parallel 1/0
Analog
Output
Analog
Output
Power Supply
Power Supply
IEEE-46a
Parallel 1/0
EPROM

Description

Page

ZaOA Single board computer. memory to 8k bytes. 24-bit TTL 1/0. RS-232-C port. 2.5MHz.
Z60A single board computer. memory to ak bytes. 24-bit TTL 1/0. RS-232-C port. 4.0MHz.
EPROM/RAM memory board for up to 32k bytes EPROM or 16k bytes RAM supplied with 2716 EPROMS.
EPROM/RAM memory board for up to 32k bytes EPROM or 16k bytes RAM without memory devices.
EPROM/RAM memory board for up to 32k bytes EPROM or 16k bytes RAM supplied with 2016 RAMs.
8-channel differential analog input. fixed gain. 12-bil. Requires MP6309 ±15VDC power supply or
"equivalent.
18-channel differential analog input. fixed gain. 12-bil. Requires MP6309 ±15VDC power supply or
equivalent.
24-channel differential analog input. fixed gain. 12-bil. Requires MP6309 ±15VDC power supply or

14-21
14-21
14-23
14-23
14-23
14-24
14-24
14-24

equivalent.

MP6305-a
MP6309-{)
MP6309-1
MP6311
MP6394-0
MP6421

32-channel differential analog input. fixed gain. 12-blt. Requires MP6309 ±15VDC power supply or
equivalent.
48-channel parallel 1/0 board.
4-channel analog output. ±10V. a-bit. Requires MP6309 ±15VDC power supply or equivalenl.

14-24

a-channel analog output. ±10V. 8-bit. Requires MP6309 ±15VDC power supply or equivalent.

14-26

DC/DC power supply. +5VDC input. ±15VDC output at 3OOmA.
DCIDC power supply. +5VDC input. ±15VDC output at 150mA.
IEEE-486 controller.
4O-Channel· intelligent parallel 1/0 board with Z60 CPU. 2k bytes EPROM and lk byte RAM.
EPROM programmer board for JEDEC EPROMs with optional peraonality modules.

14-27
14-27
14-28
14-30
14-32

14-25
14-26

Programmer
..

14-2

VMEbus ANALOG I/O
Inputs

Channels
Model
MPV901
MPV901A
MPV901P
MPV904I"'
MPV904V"'
MPV950D'"
MPV950S'"

Inputs
16DIF/32SE
16DIF/32SE
16DIF/32SE

asel21
16SE

Outputs
2
2
16
16

High
Level

Low
Level

Resolution
(bits)

•
•
•

•
•

12
12
12
12
12
12
12

•
•

•

Throughput
Time
(psec)

F8{ltures

Page

60
60

Resistor programmable gain
Resistor programmable gain

75

Software programmable gain
Current Output

14-72
14-72
14-72
14-79
14-79
14-64
14-64

3
3

Voltage output
High speed
High speed

NOTES: (1) Preliminary Data Sheet. (2) The MPV950D has 8 SE channels plus 8 channels which can be configured for differential operation,
Single ended operation, and current inputs.

14-3

BURR-BROWN@)

MP701
MP702

11511511

1\7ITC'ROCOMPUTER DIGITAL OUTPUT SYSTEMS
DESCRIPTION
The MP701 and MP702 are digital output,
micro peripheral boards designed to be used with
Motorola 6800 microcomputer systems. The
microperipheral boards are electrically and
mechanically compatible with Motorola's
Micromodule and EXORciser development system.
The MP701 has 16 digital output channels, and the
MP702 has 32 digital output channels. Each digital
output channel is implemented with a protected reed
relay.
Relays are used to provide low "on-impedance", high
output current and output isolation. Each output is
isolated from the computer bus up to 600VDC and
from charinel to channel up to 300VDC. This means
that the computer is protected from voltage
transients and malfunctions. In addition, since each

channel is isolated, the voltage switched by each line
is not critical, and ground loops are avoided. The
varistors protect each relay contact by suppressing
high voltage transients such as those encountered in
inductive circuits.
These boards appear as memory locations to the
user. Data written on the data bus controls the status
of each output. A "I" will close an output, a "0" will
open an output. Any memory write command may
be'used. Each write command controls the status of
eight channels. Address bits AO and A I on the
M P702 and AO on the M P70 I select which set of
eight outputs are controlled. The remainder of the
address lines are used to select the board itself.
Because the address block occupied by each board is
user selectable, it can be placed anywhere in memory.

'15

"
vu.
v...
RNi

S~====~~==~~~

InlBnllllanll AirpDrllndllllrial Park· P.O. BDx 11400· TUCIDO. Arizona 85734· Tel. 16021 748·1111· Twx: 911J.952·1111 • Cable: BBRCORp· Telex: 66-6491

14-4 '

OPERATING
INSTRUCTIONS

SPECIFICATIONS
ELECTRICAL

PROGRAMMING

Typical at +25°C and rated supplies unless otherwise noted.

Each digital output channel appears as one bit of memory
to the microcomputer. The channels are selected in
groups of eight by AO on the M P70 I and by A I-AO on the
MP702. Writing a I to an output channel closes the
output contact; writing a 0 to an output channel opens the
output contact. Once an output is defined, it will remain
in that state until redefined by another write to that byte.
For example, to open channels 0, 2, 6, and close channels
I, 3,4, 5, 7 with an MP702 as shipped from the factory
execute:

NUMBER OF CHANNELS

16

MP701
MP702

32

DIGITAL OUTPUT
Watts DC ~ resistive load I max
Amps t resistive load I max
Voltage t resistive load I max
Life I resistive load I min
Initial contact resistance max
Actuate Time
De-Actuate Time
Bounce Time

lOW
0.5A
28V. rms
106 operations
0.211
250~sec
250~sec

LDA #$BA
STA $9IFC
where BA (1011 1010) is the data written tothe board and
91 FC is the address of channels (}"7. Refer to Table I for a
description of which data and address lines control which
output channels.

150#t sec

TRANSIENT PROTECTION
Continuous Power Rating
Discharge Capacity

250mW
30 watt·seconds

COMPUTER !!IUS
All signals compatible with Motorola
EXORciser and Micromodules system
Logic Loading

Output Coding

TABLE I. Data - Address - Channel Relationship.
o = open, I = close.

I LSTTL
o Open Contact
I Close Contact

Data
Bus
D7
D6
D5
D4
D3

ADDRESS LINES (AI, AO)
01
10
II
15
23
31
14
22
30
13
21
29
12
20
28
II
19
27
10
18
26
Di
17
9
25
DO
8
16
24
Channel Number
The M P70 I and M P702 arc passive during a read to their
memory locations. Therefore, other memory or I/O
devices may be placed at the same address without
interfering with the microperipheral's activities.

POWER REQUI"EMENTS
Voltage
Supply Drain max, MP701
Supply Drain max, MP702

5VDC, ±5% V
0.4A
0.7A

ISOLATION VOLTAGE
Between Microcomputer Bus and Outputs
Between Outputs
OPERATING TEM!'ERIITI.IRE
STORAGE TEMPER.o.TURIO

m

600VDC
300VDC
O°C to +70oC
-55°C to +125°C

MECHANICAL

00
7
6
5
4
3
2
I
0

DIGITAL OUTPUT CHANNEL

Compatible with Micromodules and EXORciser® card
spacing.
Minimum card spacing: 12.7mm (0.5''),
Microcomputer bus connector required: 86-pin PC edge
connector with 0.156 contact centers (SAE-43D/ 1-2).
50-pin output edge connector on board.
A mating connector is available from Burr-Brown:
2250MC (Viking '# 3VH25/ IJN5, solder tab). A
Scotchflex connector is available from 3M: 3415-0001.
H

Each output is capable of switching an inductive load.
Transient suppressors are used across each output switch
to protect the output relay from damage due to surges
when the contact is opened. A typical output circuit and
the load circuit that it might drive are shown in the figure
below.
-+~

~.

I

Top
lo,--+-"",,-tl_'onnector

"*

Transient Suppressor

14-5

C I'

~ ==
-~-

M1'701J702

-.....
a..

BURR-BROWN @)

MP710

119191

MICROCOMPUTER DIGITAL INPUT SYSTEM
A 24-CHANNEL ISOLATED DIGITAL INPUT SYSTEM COMPATIBLE
WITH MOTOROLA MICROMODULE/EXORciser@ AND
ROCKWELL SYSTEM 65
-12VOC

A1S-4----...J\1
A2~--t.;.;.AD;;.;;D.;.;.RE;;.;;S.;:..SB;;.;;U.;:..S..,/1

0+----...

t-----t-O~

ADDRESS

OPTICAL
ISOLATOR

INPUT I---t-O;!
CIRCUITRY

--

DECODER

VUA

Typical of 24 channels

.2·o+-----:--~r::~:1

AI 0 - + - - - - - - - 1

AO'ot-------IL..""T'"...J~

___
r-;ii'lA-rEii'
ISOLATED
DC/DC
CHANNELS 0 -7

-----++~12VDC

DATA BUS

CONVERTER
(Optional)

-12VDC

1--_ _- -....+,;;;12VDC
CHANNE'LS 8 -15

-12VDC

+12VDC
t-:C:-::H~AN::::N:::El~S-::I&:-.2::::3....-~12VDC

FEATURES
• ISOLATED FROM COMPUTER BUS
AND CHANNEL TO CHANNEL
• CONTACT CLOSURE OR VOLTAGE INPUTS
• REDUCES SYSTEM DEVELOPMENT TIME
System engineered and specified
Plug compatible '
Easy to program
Operates ,from computer power supply
• 70°C BURN·IN

Intamatlonal Airport Industrial Park· P.O. Box 11400· TUGson. Arizona 85734· Tal. (6021 746·1111 • Twx: 910-952·1111 . Cabla: BBRCORP· Talex: 66-6491

14-6

DESCRIPTION

SPECIFICATIONS

This microperipheral board provides 24 digital input
channels that interface electrically and mechanically with
Motorola Micromodule® and EXORciser® microcomputers. It is contained on a single printed circuit
board that operates from the computer's +5VDC power
supply. Digital inputs enter through a card edge
connector located opposite the bus connector.

ELECTRICAL
Typical at +25°C and rated supplies unless otherwise noted
INPUT CHARACTERISTICS

24
15kll

Number of Channels
Input Impedance
Input Delay Times
Open to closed
Closed to open

The MP710 operates with dry relay contacts M P71O-NS operates with voltage inputs (wet relay
contacts). The M P710 may be modified by jumper
selection to operate with voltage or contact closure
inputs, or a mixture of both. Inputs are arranged in
groups of eight. Each group is isolated from other groups
and from the computer bus up to 600VDC. Isolation
between inputs is 300VDC (MP71O-NS). Isolation
protects the computer _from voltage transients and
malfunctions. In addition, since each input is isolated, the
voltage switched by each line is not critical and ground
loops are avoided.
M P71O's are programmed as memory locations. Each
input is one memory bit and any read command may be
used. When the board is read. logic 0 represents an open
contact (low voltage): logic I. a closed contact (high
voltage). Each read command inputs the status of eight
channels. Address bits AO and A I select the set of inputs
~o be read. The remainder of the address lines arc used to
select the board itself. The address block occupied by
each board is selectable and can be located a'nywhere in
memory.

25JA.sec, max
100Jolsec. max

VOLTAGE SENSE

MP710-NS
17V
4V

Minimum voltage to detect a logic 1
Maximum voltage to detect a logic 0
CONTACT CLOSURE SENSE
RCL.OSED

MP710 10n·board ±12V supply!

6kll. max

MP710-NS

at 24V across contacts
at 48V across contacts

6kU,

max

30kll. max
42kll, max

at 60V across contacts
ROPEN

MP710 lon-board ±12V supply I
MP710-NS

8OkU. min
80kll, min
175kll, min
235kll, min

at 24V across contacts
at 48V across contacts
.at 60V across contacts
Maximum voltage IVSt across input
without damage

MP710

120VAC, rms, max

MP710-NS

60VDC, max
168VAC, rms, max
84VDC, max

ISOLATION VOLTAGE
Between microcomputer bus and inputs
Between inputs iMP71q-NS only'
Between groups Of 8 inputs

600VDC
300VDC
600VDC

POWER REQUIREMENTS

®Motorola

MP710

INSTALLATION

MP710-NS

These units are shipped from the factory ready for
immediate use. Installation requires only plugging the
card into any empty slot in the computer and wiring the
input connector.
MECHANICAL

{ +5VDC ±5% at 400mA
+12VDC ±5% at 100mA
+5VDC ±5% a1 400mA

COMPUTER BUS
All signals compatible with Motorola
Micromodule and EXORciser systems
Logic loading
Input coding

1LSTTL Load
Logic 0: op~n contact
logic 1: closed contact

TEMPERATURE RANGE

Compatible with Micromodule and EXORciser card
spacing.
Minimum card Sl'acing: 12.7mm (0.5").

O°C to +70°C

Operating
Storage

-55°C 10 + 125°C

Microcomputer bus connector required: 86 pin PC edge
connector with 0.156" contact centers (SAE-43Dj 1-2).
Two 50-in output edge connectors on board.
A mating connector is available from Burr-Hrown:
2250MC (Viking # 3VH25 IJN5, solder tab). A
Sc~tcht1ex connector is available from 3M: 3415-0001.

DEFINITION OF SPECIFICATIONS
INPUT DELAY TIME

OPES TO CLOSED - Th~ delay
switching from open 10 closed.

r~quir~d to d~tec~

an input contact closure

Cl.OSED TO OPE:\ - The delay required to detect an input contact closure
switching from closed to open.
CONTACT CLOSURE IMPEDANCES
R(W~I!I - The impedance of an input contact closure when c1ost'd. RetlIM · n
specifications are the maximum impedam"'e
. allowed to reliably detect a closure.

RIII'I· .... - '\"he impedance of an input contact ci(n,ure when open. Rill·,· .... specification
i!> the lowest impedance allowed to reliably detect'an 'open contact.

14-7

MP801
MP802

BURR-BROWN@

IElElI

MICROCOMPUTER DIGITAL OUTPUT SYSTEMS
A 16- OR 32-CHANNEL RELAY OUTPUT SYSTEM COMPATIBLE
WITH INTEL SBC80 AND INTELLEC MDS MICROCOMPUTERS

ADRF
ADR2

ADDRESS
DECODER

TRANSIENT
PROTECTION

XACK

-.,-.-

MWTC

TYPICAL OF 32 OUTPUTS
CONTROL
LOGIC

ADR1
ADRO

iiii
D7

DATA BUS
INTERFACE

FEATURES
-ISOLATED FROM COMPUTER BUS
AND CHANNEL TO CHANNEL
- TRANSIENT PROTECTION
- EASY TO PROGRAM AND USE
- MEMORY·MAPPED
- BURNED·IN

Internllional ,Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734 . Tel. 16021 746·1111 • Twx: 910-852·1111 . Cable: BBRCORp· Telex: 88-6491

14-8

DESCRIPTION

MECHANICAL

The MP801 and MP802 are digital output (contact
closure) microperiphcral boards that arc electrically and
mechanically compatible with Intel's SBC80 and Intellec
MDS microcomputer systems. The MP801 offers 16
digital output channels and the MP802, 32 digital output
channels.
Each channel is implemented by a protected reed relay
and can handle up to to watts. Relays provide low "onimpedance" and high output current and isolate output
channels from the computer hus and from channel to
channel. Isolation insures that ground loop problems are
avoidt:d. The computer is protected from component
failures caused by voltage transients and malfunctions
occurring in the outside world.
M PSO I and MP802 appear as memory locations and data
written on the data bus controls the status of each .output.
A logic I will close an output. A logic 0 will open an
output. Any memory write instruction may be used.

SPECIFICATIONS
Typical at +25"C and rated supplies unless otherwise noted
-O~-

•

ELECTRICAL
NUMBER OF CHANNelS
16
32

MP801
MP802

DIGITAL OUTPUT
Watts DC (resistive load) max
Amps (resistive load) max
Voltage (resistive load) max
Life (resistive load) min
Initial contact resistance max
Actuate Time
De-Actuate time
Bounce time

10 watts
0.5 amps
28 Vrms
IO~ operations
0.3 ohms

ImSec
250jJsec

150J.l,sec

TRANSIENT PROTECTION
Continuous power rating
Discharge capacity
Leakage current through transient
suppressor at 28V

Bus

00

D7

7

SmA

D6

6

05
54

S
4
3
2
I
0

00
ill
51
i'i1i

I LsrrL

o Open Contact

IS
14
13
12
II
10
9
8

23
22
21
20
19
18
17
16

II

31
30
29
28
27
26
25
24

te

600VDC
JOOVDC

o to

ADDRESS LINES (AI. AO)
01
10

TABLE II. Data - Address - Channel Relationship.
Logic 0 = open, Logic I = close.
The MP801 and MP802 are passive during a read to their
memory locations. Therefore, other memory or I/O I:)
devices may be placed at the same address without
interfering with the microperipheral's activities.
:IE

SVDC. ±S%
0.3 amp
O.S amp

ISOLATION VOLTAGE

OPERATING TEMPERATURE

Each digital output channel appears as one bit of memory
to the microcomputer. The channels are selected in
groups of eight by ADRO on the MP801 arid by ADRIADRO on the MP802. The remainder of the address lines
are used to select the board itself. Because the address
block occupied by each board is user selectable, it can be
placed anywhere in memory. Writing a logic I to an
output channel closes the output contact; writing a logic 0
to an output channel opens the output contact. Once an
output is defined, it will remain in that state until
redefined by another write to that byte. For example, to
open channels 0, 2, 6, and close channels I, 3, 4, 5, 7 with
an MP802 as shipped from the factory execute:
MVI A, BAH
STA F700H
where BA (lOll 1010) is the data written tothe board and
F700 is the address of channels 0-7. Refer to Table II fora
description of which data and address lines control which
output channels.
Data

J Close Contact

Between microcomputer bus and outputs
Between outputs

PROGRAMMING

2S0mW

POWER REQUIREMENTS
Voltage
Supply Drain max, MPSOI
Supply Drain max, MP802

OPERATING
INSTRUCTIONS

30 wattwseconds

COMPUTER BUS
All signals compatible with Intel SSC 80
and MOS Systems
Logic Loading
Output Coding

Compatible with SBC 80 and Intellec MDS card
spacing.
Minimum card spacing: 12.7mm (0.5'').
Microcomputer bus connector required: 86 pin PC edge
connector with 0.156" contact centers (SAE-43D /1-2).
Two 50 pin output edge connectors on board. One is used
for MP801, both are used for MP802.
A mating connector is available from Burr-Brown:
2250MC (Viking # 3VH25/ IJN5, solder tab). A
Scotchflex connector is available from 3M: 3415-0001.

+70"('

TABLE I. Electrical Specifications

14-9

MP810
MP810-DB
MP810-NS
MP810-LV
MP810-AC

BURR-BROWN@

IEJEJI

MICROCOMPUTER DIGITAL INPUT SYSTEM
A 24-CHANNEL ISOLATED DIGITAL INPUT SYSTEM
COMPATIBLE WITHIEEE-796 {MULTIBUSTM}
+12VDC9 9-12VDC
j.

F
2

ADDRESS BUS

I/'

irE3=

ADDRESS
DECODER

I
C

I

r

W

<
D7"

DATA BUS

+12VD C

DPTlCAL
ISDLATDR

INPUT
CIRCUITRY

B ---

Typic" of 24 channels

CONTROL

LOGIC

oA

II

DATA
BUS
INTERFACE

A

~

..

"

+12 VDC
ISDLATED
DC/DC
CDNVERTER
(Optional)
[WETTING]
CURRENT
SUPPLY

-:!:-

CHANNELS 0 . 7

-12 VDC
+12 VDC

CHANNELS 8 ·15

-12 VDC
+12 VDC

CHANNELS 16·23

-12 VDC

FEATURES
Mulilbul" -

Intel Corp.

•
•
•
•
•
•
•
•
•

ISOLATION· FIELD TO COMPUTER
ISOLATION· CHANNEL TO CHANNEL
CONTACT CLOSURE
CONTACT WETTING CURRENT
VOLTAGE INPUTS DCIAC
DEBOUNCE
TTL·COMPATIBLE INPUTS
20·BIT ADDRESSABLE
+711"C BURN·IN

Intarnatlonal Alrport'indullrlal Park· P.O. Box 11400 • Tucson. Arizona 85734 • Tel. (6021 746-1111 . Twx: 910-952·1111 . Cable: BBRCORP· 'Telex: 66·6491

14-10

DESCRIPTION
The MP810 series provides 24 optically-isolated discrete
inputs for Multibus (lEEE-796) based microcomputer
systems. Input signal types include I) dry contactc1osures,
2) wetted contact closures, 3) DC voltages, and 4) AC
voltages. Isolation protects the computer from input
voltage transients and malfunctions of field inputs. In
addition, channel-to-channel isolation minimizes channel
interaction and avoids ground loop problems.
Full hardware integration allows cards to be inserted
directly into the system back panel. Power for the card is

provided by the system bus; therefore, no external power
supplies are required.
The MP810 is memory-mapped. Data is acquired through
any memory read operation. Each input is I bit of an 8-bit
word. An open contact (low voltage) is represented by a
logic 0 and a closed contact (high voltage) is represented
by logic I.
Contact debounce is available on some models. This
prevents erroneous data that could be caused by relay
contact bounce. The hardware approach unburdens the
processor and reduces system overhead normally required
to deb ounce contact closures.

SPECIFICATIONS
Electrical
Typical at +250 C and rated supplies unless otherwise noted.
MODEL
INPUT CHARACTERISTICS
Number of Inputs
Input Resistor
Delay Times
Open-to-Closed(1)
Closed-to-Open(2)
VOLTAGE SENSE
LogicO
Logic 1
MAXIMUM VOLTAGE (Vs) ACROSS
INPUT WITHOUT DAMAGE
VDC. max
VAC. max
VOLTAGE SOURCE
(contact wetting I
ISOLATION VOLTAGE
System-to-Field
Channel-to-Channel
Input BlockslSI
POWER REQUIREMENTS

MP810

MP810-DB

MP810-NS

MP810-LV

MP810-AC

UNITS

24

15K.1/2W

24
15K.1/2W

24
15K.1/2W

24
1.5K.1/2W

24
56K.1/2W

n

0.025
0.100

6513)
65(3)

0.025
0.100

0.025
0.100

1(3)
80(3)

msec
msec

Open(4)
Closed(4)

Open( 4)
Closedl41

4VDC
17VDC

lOV rms(6)
48V rmsl61

V, max
V, min

60
120

60
120

168

20
40

120
250

VDC
VAC. rms

±12V

±12V

None

None

None

600
171
600

600

600

(7)

600

300
600

600
300
600

300
600

+5/+12
400/100

+51+12
400/100

+5
400

+5
400

400

BUS INTERFACE

84

2VDC
3.5VDC

600

+5

Meets electrical and mechanical specifications of IEEE-796 (Multibus)

ENVIRONMENT
Operating Temperature
Storage Temperature
Relative Humidity

o -+70·C
-55·C to +125·C
95% noncondensing

NOTES:
I. OPEN-TO-CLOSED: The delay required to detect an input contact closure switching from open-ta-closed.
2. CLOSED-TO-OPEN: The delay required to detect an input contact closure switching from closed-to-open.
3. Contact debounce time.
4. Contact state.
5. The on-board OC-to-OC converter provides three isolated voltages. Each voltage services one block of eight input channels.
6. This is for a 60Hz signal.
7. Common power supplies used for contact wetting degrades channel-ta-channel isolation.

MECHANICAL SPECIFICATIONS
Compatible with IEEE-796 (Multibus) specifications
Minimum card spacing: 0.6'" (15.2mm}
Board Thickness: 0.062" (1.57mm)
Bus connector: PI: 43/86 pin on 0.156"13.9mml centers
P2: auxiliary: -30/60 pin on 0.10" (2.5mml centers
1/0 connectors: P3/P4: 25/50 pin on 0.10' (2.5mm) centers

14-11

VDC
VDC
VDC
VDC
mA

BURR-BROWN@

MP820-05
MP820-15
MP821-0'5
MP821-15

1 &:lEI 1

MICROCOMPUTER DIGITAL INPUT SYSTEM

5- or 15-Channel Isolated Pulse Counter/Measurement
System Compatible with IEEE-796 (Multibus™)

FEATURES
• 5 OR 15 CHANNELS
• 16·BIT COUNTER
• SINGLE OR OOUBLE PRECISION
• REGISTER TRANSFER
• MEMORY OR I/O MAPPED
• OPTICALLY·ISOLATED INPUTS
.DEBOUNCE

•
•
•
•
•
•

FREQUENCY (MPB21 ONLYI
PULSE DURATION (MPB21 ONLYI
MULTIBUS'" COMPATIBLE
2D·BIT ADDRESS BUS
16-BIT DATA BUS
BURNED·IN

OSCILLATOR

I--.-...r-----,
CHI
5-CHANNEL
PROGRAMMABLE
COUNTER

CH5

CHB
5-CHANNEL
PROGRAMMABLE
COUNTER

CHIO

CHII
5-CHANNEL
PROGRAMMABLE
. COUNTER

OF

iiii

CHI5

Multibus'· - Intel Corp.

International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734· TIl. (802) 746-1111 • Twx: 911).952·1111 • Cable: BBRCORp· Tlllx: 66-8491

14-12

BURR-BROWN®

MP830-72

1E3E31

MICROCOMPUTER TTL INPUT/OUTPUT SYSTEM

72-Channel TTL Input/Output Systems Compatible with IEEE-796 (Multibus™)

FEATURES
•
•
•
•
•

•
•
•
•

72 CHANNELS
INIOUT BLOCKS OF B
SOCKETED liD TERMINATIONS
OUTPUT READ BACK
LATCHED OUTPUTS

NO POWER·UP GLITCH
MEMORY (1/01 MAPPED
MULTIBUS'" COMPATIBLE
BURNED·IN

iii
A4

iii/A3---.r---l~.,

PORT I
CHI-8

BHEN -;:::=~~
INH XACK - - - - - I
MEM R/IWW===:1
I/ORW-

. . . --r-,..

DATA
BUS
INTERFACE

..
PORT 9
CHII5-72

MultibusTil - Intel Corp.

Inlernatlonal Airport Induslrlal Park· P.O. Box 11400· Tucson. Arizona 85734 . Tel. (6021 746·1111· Twx: 910-952·1111 . Cable: 88RCORp· Telex: 66·6491

14-13

MP1104

BURR-BROWN@

IElElI

MICROCOMPUTER ANALOG OUTPUT SYSTEM
A 4-CHANNEL ANALOG OUTPUT SYSTEM COMPATIBLE WITH
DIGITAL EQUIPMENT CORP. LSI-11, LSI-11/2, LSI-11/23, PDP-11/03, AND
PDP-11/23 MICROCOMPUTERS

DESCRIPTION
The MPII04 analog output peripheral is electrically
and mechanically compatible with and interfaces
directly to DEC's Q bus.
The MPII04 consists of four 12-bit Dj A converters

with address decoding and control logic. It also
includes a DC! DC converter for operation from the
computer's SVDC supply. The MPII04 is burned-in
before shipment.

ADDRESS SELECT
AND CONTROL
LOGIC

DATA BUS

...... ,

""""'CO...

~

GND~~_____________~

D/A CONVERTER
DAC3

MP1104 BLOCK DIAGRAM

Inl8matllllllll Airport Indualrllll'lrk • P.O. Box 11400 • Tucson. Arizona 85734 • Tal. (602) 746-1111 • Twx: 910-952-1 III • Cabla: BBRCORP • Telex: 66-6491

SPECIFICATIONS

PROGRAMMING
The MPl104 is programmed as memory locations and
any memory write instruction can be used. The 0/ A
converter input'occupies the 12 least significant bits of a
word. The address block occupied by the M P II 04 is userselectable and can be placed anywhere in the upper 4k of
memory.
M P II 04 's are jumpered at the factory with a base address
of 170440 (channel 0). Channel one is at location 170442,
channel two is at location 170444, and channel three is at
location 170446 (see Table I).

.ELECTRICAL
Typical at 25°C and rated power supplies unless otherwise ~oted
ANALOG OUTPUT
OUTPUT CHARACTERISTICS
Number of Channels
Output Voltage Range.
(Jumper SelectableJ{ll
Output Impedance
Short Circuit Protection
TRANSFER CHARACTERISTICS
Resolution
Output Settling Time. max(2)

MP1104

4
±10V. 0 to 10V. ±5V. 0 to SV.
±2.SV at SmA
0.010
Ve.
12 bits
1O#olsec

TABLE I. OJ A Converter Data Assignments.
WRITE DATA

ACCURACY
Output Accuracy. maxl31
Temperature Coefficient of
Accuracy Dri1l15)

±30ppm 01 FSR/De

POWER REQUIREMENTS
MPll04

+SV ±S% at 1.2SA

ENVIRONMENTAL
Operating Temperature

Relative Humidity

±O.02S% FSRI4)

DIS 014 013 012 011 010 09 DB 07 Db OS D4 03 02 01
X X X
X BII BIO B9 B8 B7 B6 BS B4 B3 B2 BI

BO

MEMORV MAP

Channel 0
Channell

Base Address
Base Address +2

Channel 2

Base Address +4
Base Address +6

Channel 3

oDe to +700e

ADDRESS MODIFICATION

95% of noncondensing

NOTES:
1. Factory set lor ±10V range.
2. Settling to ±0.01% 01 FSR lor a lull scale change.
3. Includes linearity errors with gain and offset errors adjusted
4. FSR means Full Scale Range.
5. Includes offset drift. gain drift and linearity drift.

DO

The base address of a board can be set to any 4-word
boundry by properly jumpering (with push-on sockets)
its address selector. The base address set at the factory is
170440. To change the sense of a bit simply remove the
present jumper and insert the jumper for that bit (see
Tables II and UI).

to zero.

TABLE II. Base Address Jumpers.
ADDRESS
LINES
AI2

FACTORY
SET
VALUE

JUMPER
MATRIX
LAYOUT
0
I
12
Ii

Ali

MECHANICAL

10

FACTORY SET
VALUES
0 I
12
Ii
10

AIO
9
K

A9

.compatible with DEC LSI-II, LSI-II/2, LSI-II /23,
PDP-I 1/03, and PDP-I 1/23 card spacing.
Minimum card spacing: 12.7mm (0.5").
Analog Output Connector: one 20-pin PC edge
connector on top edge of board.
Analog Output Mating Connector:

A8
A7

o

AS
A4

Mating connector available from Burr-Brown:
2220MC (Viking #3VHIO/ IJN5, solder tab)

AJ

A flat cable connector is available from Berg:
65764-001

I

ADDR/~

o I
.:J.1
ADDR

Jumper inserted
Jumper inserted
between these two between these two
pins for logic O.
pins for logic l.

ANALOG OUTPUT RANGE SELECTION
Each 0/ A converter is wire wrap jumpered at the factory
for ±IOV operation with two's complement coding. It is
a..
possible, however, to alter jumpers on the board for other :IE
output voltages and coding. When making a change, just
remove those jumpers indicated for the present range and
replace them with the jumpers required for the desired
range.

-g

OPERATING INSTRUCTIONS
INSTALLATION
MPII04 is shipped from the factory calibrated and ready
to use. Installation consists of plugging the card into any
empty slot in the computer and wiring the analog
connector.

14-15

MP1216
MP1216-PGA

BURR-BROWN®

IElElI

MICROCOMPUTER ANALOG INPUT SYSTEMS
A 32-CHANNEL ANALOG INPUT SYSTEM COMPATIBLE WITH
DIGITAL EQUIPMENT CORPORATION LSI-11, LSI-11/2, LSI-11/23,
.
PDP-11/03 AND PDP-11/23 MICROCOMPUTERS'

FEATURES:

. DATA
AC.QUISITION
MODULE

• HIGH AND LOW LEVEL INPUTS
- SOFTWARE PROGRAMMABLE GAIN
n to 1024) AMPLIFIER OPTION
- EASILY PROGRAMMED
-BURN-IN

DESCRIPTION
The M P 1216 analog input peripherals are electrically
and mechanically compatible with and interface
directly to DEC's LSI-II/2 family. The boards use
one dual-wide card slot.
The MPI216 includes: over-voltage protection to
26VDC; an analog multiplexer; resistor
programmed instrumentation amplifier (MPI216),
or a software programmable amplifier with gains of I
to 1024 (MPI216-PGA); samplej hold amplifier and;
a 12-bit AI D <.:unverter.

These units are 16-channel differential (user
strapable ~s 32-channel single-ended) analog input
systems.
Gains of I to 1024 are software selectable for the
programmable amplifier version (MPI216-PGA),
and the gain for each channel is stored in an on-board
RAM. The proper gain for each channel is then
selected automatically by the MPI216-PGA.
The MPI216-PGA is particularly recommended for
iow-ievel inputs.

Inlernallonal Airp0rllnduSlrlal Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. 16021 74fi·lll1 . Twx: 91()'952·1111 • Cable: BBRCORp· Telex: 66-6491

14-16

MECHANICAL

SPECIFICATIONS
ELECTRICAL

Compatible with LSI-II, LSI-II/2, LSI-II /23,
PDP-llr03 and PDP-I 1/23 card spacing.

Typical at 25·C and ratad power supplies unless otherwise notad

ANALOG INPUT SECTION

I

INPUT CHARACTERISTICS
Number of Channels

MP12181MP1211-PGA

Minimum card spacing: 12.7mm (0.5").
Analog Input Connector: One 40-pin analog edge
connector on board for analog inputs.
Analog Input Mating Connector:
Mating connector available from Burr-Brown:
2240MC (Viking #3VH20/ lJNS solder tab); a flat
cable connector is available from Berg: 65764-007.

32 slngle-ended or
16 differential
±10V.0-l0V

ADC Gain Ranges (jumper selectablell'l
Amplifier Gain Ranges
ReSistor Programmablel21 IMP12161
Software Programmable IMP1216-PGAI
Maximum Input Voltage without Damagel31
Input Impadance
l00Mn.
l00Mn.

1 to 1000
1 to 1024
±26V .
10pF OFF Channel
lOOpF ON Channel

Bias Current

Resistor Programmable
Software Programmable
Amplifier I nput Offset Voltage
Resistor Programmable
Software Programmable
Amplifier Input Offset Voltage Drift
Resistor Programmable
Software Programm.ble
TRANSFER CHARACTERISTICS
Resolution
Conversion Time. max G 1
ReSistor Programmable''')
Software Programmable
Conversion Time. max G 1024
Resistor Program"UIble
Software Programmable

=

=

±20nA
±15nA

OPERATING INSTRUCTIONS

±400"V
±40"V

INSTALLATION
MPI216 is shipped from the factory calibrated and ready
to use. Installation consists of plugging the card into any
empty slot in the computer and wiring the analog
connector. See Figure I for the block diagram.

±2"VfOC
±0.5"VfOC
12t!118
40"sec
375,.sec
l00,.sec
375"sec

ACCURACY
:system Accuracy at +25·(;. maxlSI G - 1
±Q.025'111 FSRI"I
System Accuracy at +25·C. max G = 1024
Resistor Programmable
±Q.l'111 FSR
Software Programmable
±Q.05'111 FSR
System Output Noise G =1. rms
Resistor Programmable
1mV
Software Programmable
1mV
System Output Noise G =1024. rms
15mV
Resistor Programmable
Software Programmable
2mV
Linearity
±1I2LSB
Differential Linearity
±1/2LSB
. Quantizing Error
±1I2LSB
Adjustable 10 zerol71
Gain Error
Adjustable
to zero
Offset Error
Monotonicltyl81
Guaranteed O·C to +70·C
STABILITY OYER TEMPERATURE Binolar 191
System Accuracy Drift. max G - 1
±45ppm of FSRfOC
System Accuracy Drift. max G = 1024
Resistor Programmable
±200ppm of FSR/·C
Software Programmable
+l00ppm of FSR/·C
DYNAMIC ACCURACY
Sample/Hold Aperture Time
125nsec
Aperture Time Uncertainty
±5nsec
74dB IDC to lkHzl
Differential Amplifier CMRR G = 1
Channel Crosstalk
80dB down at 1kHz. for

'~~NC~~~~~~,
POWER REQUIREMENTS
MP12161MP1216-PGA
ENYIRONMENTAL
Operating Temperature
Relative Humidity

+5V +5'111 at 1.0A

PROGRAMMING
This peripheral is programmed as memory locations; any
memory reference instruction can be used. Two 16-bit
memory locations are used. One for the Read/ Write data
register; the other for the Control Status register (see
Figure 2). The addresses occupied by each MPI216 are
user selectable and can be placed anywhere in the upper
4K of memory.
On MPI216-PGA's (with software programmable gain
amplifiers) an on-board random access memory (RAM)
is used to store the gain for each channel.
When the Gain Control bit (D8) of the Write Data
Register is a logic I, the data contained in bits D9-D12 of
the same register are written to the on-board RAM to
control the gain for the channel also written in the same
word (bits 00-D4). On subsequent operations if the Gain
Control bit is a logic 0, the programmable gain amplifier
will use the gain already stored in on-board RAM for that
channel.
these boards are factory set with Data Register at
location 170402 and the Status/ Control Register at
location 170400.

OOC to +70·C
95'111 noncondenslng

NOTES:
1. Factory set for ±10V range.
2. Factory set for Gain = 1.
3. With power off 1±36 volts with power onl.
4. With delay inhlbiiad. 22"sec.
5. Includes linearity errors with gain and offset errors adjusted to zero.
6. FSR means Full Scale Range.
7. When any' one gain range is adjusted to zero gain erro" the gain
error for any other range is less than ±O.O2% wnen using the software

A conversion is started by writing the channel number to
bits DO-D4 of the data register. This write operation
selects the proper analog multiplexer channel and starts a
delay one-shot which allows time for the multiplexer,
instrument amplifier and sample/ hold amplifier to settle
to the new channel's value. At the end of the delay time,
the sample/hold amplifier is switched to the hold mode
and the A/ D converter starts its conversion.

programmable amplifier.

8. No missing codes guaranteed.
g. Includes offset drift. gain drift. and. linearity drift.

When the conversion is. complete, the board can be
operated in one of two modes:

14-17

CHO

.....•.. ~~~':. ~~?~~~~I?!I.~?~~~~ ~ .•.i

!

+5VDC
DCIDC CONVERTER

GND
·15YDC

FIGlJR . 1. Block Diagram.
Interrupt Mode

In the Interrupt Mode, when the conversion is complete,
the MPI216 asserts the bus interrupt request line
(BIRO). When the LSI·II responds with a bus interrupt
acknowledgement (BIAKI), the MPI216 asserts the bus
. reply line (BRPY) and gates an interrupt "vector" onto
the bus. The vector address is selected by jumpers on the
board. The Interrupt Mode is enabled by wr.iting a logic I
to bit D6 of the Control Register.

Polling Mode

In the Polling Mode, the CPU must periodically scan bit
D7 of the .ST ATUS Register to determine if the
conversion is complete. A logic I indicates that
conversion is complete. A read of the Data Register will
then produce the data word. The board is in the Polling
Mode if the !nterr'upt !\1cde is disabled by writing a logic
o to bit D6 of the Control Register.

14-18

MP2216

BURR-BROWN®

I E1IE1I I

MICROPERIPHERAL
ANALOG INPUT/OUTPUT SYSTEM
A 12-BIT 32 CHANNEL ANALOG INPUT /2 CHANNEL
ANALOG OUTPUT SYSTEM COMPATIBLE WITH ZILOG
MICROCOMPUTERS

FEATURES
• ANALOG lID ON THE SAME BOARD
• OPERATES FROM COMPUTER POWER SUPPLY
• HIGH LEVEL OR LOW LEVEL INPUTS
• BURNED-IN

DESCRIPTION
Completely compatible with Zilog's Z-XO MCB'"' and
Z-80 MCS series of microcomputers. MP2216
provides a single board l2-bit resolution analog
input, output system. The input section accepts 16
differential or 32 single-ended channels. Inputs
ranging from millivolts to volts can be digitized
because of M P22l6's variable gain instrumentation
amplifier.
Two optional channels of analog voltage are
provided in the output section of the M P22l6. The
input data for each digital-to-analog converter is
double buffered to minimize output glitches during a
data update. Several output ranges and bipolar or
unipolar operation are selected by on-board
programming.

Conlrol{
Bus

:...~--

_

---

Data
Bus

Power {
Supply -

-.---r;;;::;:r--o
+
--~_

The MP2216 is mechanically. electrically and
logically compatible with the Zilog systems. Power is
derived from the +5V logic supply. Logic levels and
drive capacity are matched to the system bus.
Interfacing is accomplished primarily through a Z-80
PIO contained within the system.

Inlernalional Airporllnduslrial Park· P.O. Box 11400· Tucson. Arizona 85734 - Tel. 16021 746·1111 . Twx: 910-952·1111 . Cable: B8RCORP . Telex: 66-6491

14-19

THEORY OF OPERATION
The M P2216 interfaces with the Z-80 I/O bus occupying
10 locations for the complete input/ output system. The
first four locations are required for the PIO. The next two
locations transfer input channel address and board
status. The remaining locations are used to \lass data to
the two digital-to-analog converters.
Data can be acquired from the analog inputs in either the
POLLING or INTERRUPT mode:
POLLING MODE - A conversion is initiated by writing
the analog channel address to the address register. The
program must then periodically test the conversion bit in
the status register to determine when the conversion is
completed. During initialization of the MP2216's PIO,
the interrupt enable must be reset (both ports) to prevent
generation of interrupts.
The following program may be used to input a channel of
data to the Be register pair:

ELECTRICAL SPECIFICATIONS
Typical at 2S"C and rated power supplies unlm othCI"Wisc noted.

ANALOG INPUT SECTION
INPUT CHARACTERISTICS
Number of Channels
ADC aain Ran... (Jumpet Selectable)
Amplifier Gain Ranaes (resistor programrr.able)
Maximum Input Volta. Without Damage
Inpul Impedance

32 .in&k--AO

+SV ±S% al 1.6 amp

ENVIRONMENTAL
Operating Temperature
Relative Humidity

O"c. 10 +70"C
95% noncondensing

TABLE I. Electrical Specifications
:.;orES:
I. I ndudes offset errors. gain errors. linearity errors.
2. FSR means Full Scale Range.
.l :'IIlo missing codes guarant('Cd.
4. Indudes off!.Cl drill. gail! drift dnd linearity drift.

SYSTEM CONFIGURATIONS
The MP2216 microperiphcral board is available in two "er~ions.
MP2216-AO: All features of the MP2216 system are included in this
confiRUration.
MP2i16: Provides all features except the t~o digital-to-analogconverters.
MP8004;

Cable assembly - two required.

14-20

BURR-BROWN®

MP6102

IElElI

STD BUS
SINGLE BOARD COMPUTER
FEATURES
.ZSOA
•
•
•
•
•
•
•
•

MEMORY CAPACITY TO 8k BYTES
PROGRAMMABLE 24-BIT PARALLEL I/O
RS-232-C SERIAL I/O
SELECTABLE POWER ON/RESET JUMP ADDRESS
ONBOARD COUNTER/TIMER
MULTILEVEL INTERRUPT CONTROLLER
SOFTWARE-PROGRAMMABLE BAUD RATE
ONBOARD MONITOR/BIOS SOFTWARE IN EPROM

DESCRIPTION
The MP6102 is a Z80-based computer which generates all STD-Z80 signals. A great degree of flexibility is built into the MP6102 through the use of
fuse-link PROMs for memory and I/O control
allowing the user to modify functional control to
suit a specific application.
Interrupt control is performed by an AM9519 Universal Interrupt Controller, which provides management and priority resolution for up to eight
maskable interrupt inputs. Parallel I/O is provided
by an 8255A Peripheral Interface, supplying 24 bits
of mu.ltiple mode input or output.

The onboard Z80A-CTC provides three channels of
user-definable counter/timer functions. One of the
channels is software-programmable as the time base
for the RS-232-C port. This serial I/O port, programmable to 9600 baud, is based upon the I825lA
USART, and afford the user a number of communications protocols from which to choose. All I/O
connectors are on the user edge of the card on 0.100"
grid centers.
The EPROM-resident Monitor program provides
for keyboard functions and the basic I/O software
(BIOS) for CP/M® compatible disk and terminal
I/O.
CPI M is a registered trademark of Digital Research

International Airport tndustrial Park· P.O. Box 11400· Tucson. Arizona 85734 • Tal. 16DZ1 746·l11t . Twx: 9t(J.952·1111 . Cable: BBRCORP· Talex: 66·6491

14-21

SPECIFICATIONS
ADDRESS AND I/O INFORMATION

OPTIONS AND SPECIAL FEATURES

ADDRESS SELECTION

On board memory may be deactivated using the. PHANTOM line and
the lower EPROM may be unconditionally asserted using PROM 1
requeat.

The MP6102 can occupy as much as one 8k byte page in memory.
As shipped, the two EPFIOM sockets occupy the third and lourth 2k
byte blocks, conligured lor 2716 EPROMs, while the byte-wide
RAM occuplea the second 2k byte block lor a tolal of 6k bytea 01
resident onboard memory. The lirat 2k. byte block is considered to
be ollboard.
The board is shipped with memory paged to locations EBOO to FFFF
with the Monitor/BIOS EPROM occupying FOOO to F7FF (EPROM 1).
FOOO is also the power-on jump address.
I/O ADDRESSING

Sixteen 110 ports are occupied by on board functions, as follows:
Port
USART data ................................................ 0, 2
USART control/status ...................................... " 3
Zao-CTC ............................................... 4, 5, 6, 7
Interrupt data ...•..•.................•.•......•.•...••••... S, A
Interrupl control ............................................ 9, B
PIO channels A, B, C .................................... C, D, E
PIO control .................................................. F

Special memory or I/O decoder PROMs are available lrom the
factory.
MEMEXP and 10EXP l\1ay be programmable using an onboard
parallel port bit.
EPROMs can be of 2716 or 2732 type, within the confines 01 the
selected Sk page. (Standard shipping configuration is 2716 for each
EPROM socket.)

The user interface allows for cascading interrupt controllers,
bringing onboard three external control functions and providing the
selected baud clock for external use.

ORDERING INFORMATION
When ordering the MP6102, please specify desired
configurations as shown below:
MP6102-O
MP6102-1

Any other references cause data transfers to occur from the bus.

14-22

2.5MHz
4.0MHz

BURR-BROWN®

MP6202

IElElI

STD BUS
EPROM/RAM MEMORY CARD
MEMORY ORGANIZATION
Selectable, depending upon memory type installed; addressable on
the minimum logical boundary, 8S defined by the memory type in

FEATURES
• SOCKETED FOR 32K EPROM
• ALTERNATE 16K RAM
• EPROM AND RAM MIX
• SELECTABLE MEMORY ADDRESS
.IK MEMORY BOUNDARIES
• MEMEX SUPPORT
• MINIMUM MEMORY SPACE CONFIGURABLE

use.
IC MEMORY TYPES

2508 I ntallTl
2516 (2716) IntallTl
2732 Intel
4016TI

4801 Mostak
BUS LOADING
1LSTIL load
BUS DRIVE
24mA sink, 15mA source

DESCRIPTION

CARD DIMENSIONS

The MP6202 EPROM/ RAM Memory Card has
been designed to meet the varied requirements of
STD bus system designs which call for a mix of
EPROM and RAM.
System memory may be mapped in the smallest
logical increments, relieving the requirement for
allocating entire 8k or 16k blocks to EPROM/ RAM
which only use a portion of that block. The MP6202
memory may be configured from Ik byte to 4k byte .
blocks; however, the memory type selected for both
EPROM and RAM must be of the same family
type.
Through jumper options, any logical memory
address boundary may be occupied. Depending
upon the application, the' card may be populated
with only as many memory chips as required;
therefore, only memory space in use is allocated.
User-selectable options allow the MP6202 to be
enabled upon either the occurrence of a low active
or a high active MEMEX signal. Thus, two banks of
memory are easily implemented.

4.5" x 6.5"
VOLTAGE REQUIREMENTS
+SVDC at 250mA (not including memory chips)
OPERATING TEMPERATURE RANGE

aoe to 55°C

STD BUS COMPATIBILITY
All 8-bit microprocessors

ORDERING INFORMATION
The MP6202 is available in the following configurations. To order, please specify as shown below:
MP6202-O EPROM/ RAM Memory
Card, supplied with eight
Intel 2716 EPROMs or
equivalent
MP6202-1 EPROM/RAM Memory
Card, supplied without
EPROMs
MP6202-2 EPROM/RAM Memory
Card, supplied with
TMM2016 RAM or
equivalent

SPECIFICATIONS
SYSTEM CLOCK RATE,
4.0MHz

ma.

MEMORY SUPPORT CAPABILITY

32k bytes. max

Inlernalional Alrporllndustrlal Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. 16021746·.1111 . Twx: 9tlJ.952·1111 . Cable: BBRCORp· Telex: 66·6491

14-23

BURR-BROWN®

MP6303

IElElI

STD BUS
ANALOG INPUT BOARD
FEATURES

SPECIFICATIONS
(Typical al +2SoC and rslad power'unless olherwise naiad)

• 32·CHANNEl
• DIFFERENTIAL INPUTS
• 12·BIT RESOLUTION
• SELECTABLE INPUT RANGES
• USER·CONFIGURABLE INPUT CONDITIONING
• VARIABLE RESISTOR·SELECTABLE GAINS
• SAMPLE/HOLD
• HALT MODE OPERATION
.1/0 MAPPED
• REGISTER TRANSFER OF DATA

NUMBER OF CHANNELS .......................... 32 dlffersnlial
RESOLUTION ............................................ 12·blt
THROUGHPUT TIME [G = 51 ........................... 16psec
INPUT SIGNAL RANGE .. : ..................... ±2.SmV to ±10V
ADC RANGE .................. O 10 SV, 010 10V, ±2.5V, ±5V, ±10V
AMPLIFIER GAIN RANGE'" , ..•..•.••......•.•••••...•. I to 1000
INPUT IMPEDANCE ...................................... lOGO
BIAS CURRENT .................... ,.", •• , •..••••..••.... 35nA
CMRR .................................................... 90dB
AMPLIFIER INPUT OFFSET ...•. , •.••.•...••.•••••....•... 1.SmV
AMPLIFIER INPUT OFFSET DRIFT •••••• " .•.•••.•....•• SmVrC
BUS LOADING .............................. lLSTTL load per line
POWER •••••• , ........... , .•• +SVDC al l00mA, ±1SVDC alSOmA
OPERATING TEMPERATURE •••••••• , ............... O"C 10 5SoC
STD BUS COMPATIBILITY ••••. .STD-ZSO, STD-8080, STD-8085,
STD-8800, STD-6502

,DESCRIPTION

NOTE:

The MP6303 is a' 32-channel, 12-bit differential
input analog-to-digital converter for data acquisition
in the STD bus microsystem environment.
The converter can be configured to operate with
input signals in the range of ±2.SVDC, ±SVDC,
±IOVDC, 0 to SVDC or 0 to IOVDC. The MP6303,
can perform a conversion in lO",sec, plus filter and
multiplexer settling time.
The A/ D converter contains a high performance
instrumentation amplifier with a gain setting from
IV/V to lOOOV/V, to accommodate low level sensors
such as strain gauges and thermocouples, and high
level signals such as power supply outputs,

1. Potenllometer adjuslmenllactory 8ello XS.

POWER SUPPLY OPTION, .. MP6309 Exlernal ±15VDC
Power Supply Cerd

ORDERING INFORMATION
The MP6303 is available in 8-channel increments,
up to 32 channels. To order, specify number of
channels as shown.
MP6303-08
8 Analog Input Channels
MP6303-16
16 Analog Input Channels
MP6303-24
24 Analog Input Channels
MP6303-32
32 Analog Input Channels

Inlamatlonal Airport Induslrlal Park - P.O, Box 11400 - Tucson, Arizona 85734· Tal. 18021 746-1111 • Twx: 9111·952-1111 - Cabla: BBRCORP - Talax: 66-6491

14-24

BURR-BROWN@>

MP6304

I ESIESI I

STD BUS
PARALLEL INPUT/OUTPUT
INTERFACE LEVELS
All I/O lines are buffered with inverting or noninverting buffers of
the user'S choice.

FEATURES
•
•
•
•

I/O ADDRESSING
SELECTABLE INTERFACE LEVELS
COMMON FAMILY LOGIC ELEMENTS
MULTIMODE PROGRAMMABILITY

OPERATING RANGE
O·C to SS·C
CARD DIMENSIONS
4.S" x 6.S"
CARD FORMAT
STD bus

DESCRIPTION
The MP6304 is a versatile, programmable parallel
TTL input/ output card designed for the STD bus
microsystem environment. The flexibility of the card
allows it to be used in practically all STD bus
environments, including STD-Z80, STD-8080, and
others.
A number of user-selectable options are provided so
that the card may be configured for a wide variety of
application requirements.
Addressing is switch-selectable so that the card may
be located in any contiguous 8-location group
throughout the entire I/O range. All I/O lines are
buffered with invening or noninverting buffers of
the users' choice.
Provision is made for common family logic elements
in the input and output buffer areas. The onboard
Intel 82SSA peripheral interface circuits may be
programmed to operate as either input, output,
bidirectional and bit set/ reset, latched or strobed or
a combination thereof.

VOLTAGE REQUIREMENTS
+SVDC at 400mA
I/O CIRCUIT TYPE
Intel 82S5A
STD BUS COMPATIBILITY
STD-Z80, STD-8080, STD-BOBS, STD-6800, STD-6502

USER SELECTABLE OPTIONS
The following information describes the jumper and switch options
provided as standard features with each MP6304.
SWITCH GROUP US
Switch
1
2
3

4
S

I/O Address Line
A7
A6
AS
A4
A3

A switch placed to the ON position conditions the card-select

decoder to expect a low condition on the input address lines to
produce the select signal: To set the card to occupy addresses DOH
through 07H. therefore. all switches are set to the ON position.
82S5A PORT C BUFFER ELEMENTS
Jumper Groups A and B are provided for the 82SSA Port C functions
so that the driver/receiver elements may be configured on a bit-wise
basis, compatible with the function of Port C.
8255A PORT A AND B BUFFER ELEMENTS

SPECIFICATIONS
SYSTEM CLOCK RATE, ""'"
4.0MHz
I/O ORGANIZATION
8 consecutive 110 ports; 48 bits, 32 definable as Input or output in
8-bll groups, 16 definable as Input or output on a bit-far-bit b.si •.

110 ADDRESSING
SwitCh-selectable

The rows of octal TTL elements U8 through U1' and U12 through
U1S are provided so that the S255A Ports A and B may be configured
as Input or Output. If a port will be programmed to be OUTPUT. the
logic element (Element A) is Installed in the US row and becomes a
driver. If that port will be programmed to be an INPUT. the logic
element is installed in the U12 row and becomes a receiver.
Note that In both the Element A and Element B positions, provision
has been made for "generic" or equivalent circuit usage, where pins
1 and 19 of each of the elements are left definable by the user.

Inlernllional Airport Induatrla) Park· P.O. Box 11400· Tucson. Arizona 85134 - Tel. 16021 746-1111 - Twx: 910-952-1111 - Cable: BBRCORP • Telex: 66-6491

14-25

BURR..,BROWN®

I E::iEl I

STD BUS
8-CHANNEL DIGITAL-TO-ANALOG CONVERTER
FEATURES
•
•
•
•
•
•
•

SPECIFICATIONS

VOLTAGE OR CURRENT MODE
B-BIT RESOLUTION
FAST SETTLING TIME
SELECTABLE OUTPUT RANGE
SELECTABLE ADDRESSING
MULTIMODE OPERATION
SELECTABLE POWER SOURCE

OUTPUT RANGE
o to 10VDC at 10mA volt~ge mode unipolar
-5VDC to +5VDC at 10mA voltage mode bipolar
4mA to 20mA current mode (typical)

{may require external curre~t source)"
D/A CONVERTER ACCURACY
0.1'!41
., D/A CONVERTER SETTLING TIME
2.3jIsec, max (all bits high to low)
SYSTEM CLOCK RATE,"'"
4.0MHz

DESCRIPTION
Designed with a full array of features, the MP63!)S is
an 8-channel digital-to-analog converter for data
conversion applications in the STD bus microsystem
environment.
With each channel independently configurable, the
MP630S can operate in either the current or voltage
mode. In the current mode, the current source may
be provided onboard or offboard. If jumpers are
installe5YDC
GRD

'j

UDD
DCIDC
CONVERTER
MODEL·54B

111

z
INPUT
MUX
3-STATE
OUT

~
~

I'r

Y1n'~
.
I I

2~

~~

'"

TATION
AMPLIFIER

SAMPLEi
HOLD·

1SELECTION

uA

(1D-o
'j

t----

.: ·
-·

f

I

AO= 0

• LSI'S

AO-l

4MSI'5

IlBIT
AID CONVERTER

-IIVDC ':"IIVDC

In!ernalional Alrporllnduslrial Park· P.O. Box 11400 - Tucson. Arizona B5734 - Tol. 16021 746-1111 - Twx: 910-952·1111 - Cable: BBRCORp· Telex: 66-6491

14-33

, DESCRIPTION

contains the 546 DC/DC converter to assure'operation
on +SVDC power. The input of the D / A converters. are
douple buffered so that a complete 12 bit word' can be
litrobed into a D / A converter's input register to minimize
Qutput glitches.
' ,
.

These microcomputer peripherals provid,e two much
needed functions· that interface directly t9 Motorola's
. Micromodule and EXORciser microcomputers. The
•functions are.: I)Analog Data Acqui~itionand2) Analog
Output. The devices. are electrically and mechanicallY
compatible with Motorola micro~omputets. I;ach
analog system is contained on a single printed circuit
board that is treated as memory input and output by ihe
CPU. The cards will mate to any memory or I/O slot. The
analog interface for each system is at a flat cable
connector at the opposite edge of the board ftom the bus
, connector.

'THEORY OF OPERATION
. When programming with these peripherals, they' are
,treated as memory locations, Both the A / D converter
output and the D/A converter input are 12 bit words &0
two 8 bit memory locations are needed for each channel.
But, because the address block occupied by each
peripheral is switch selectable, it can be placed anywhere
in memory. Since these units are treated as memory, a
single instruction is all that's needed to set the input of a
b / A converter. For instance, the STX (write) instruction
followed by the proper address is used to write data from
the, index register to the MP7104. The fQur most
significant bits are written first followed by the eight least
significant bits. Through double buffering in the M P71 04
only one 12 bit data transfer is made to the DAC to
minimize glitching.
All of these systems are jumpered at the factory with the
first channel at 'address EFOO,. (that's 1110 1111 0000
0000 in binary). Each subsequent channel is two memory
locations past the start .of the last channel so that the
second channel is at location EF02'6 (1110 1111 0000
0010).

The Data Acquisition Systems consist of the MP7208, an
8 channel differential input system; and the MP7216, a 16
channel single-ended input system. Burr-Brown's
SDM853 modular data acquisition system is used to
implement these systems. The data acquisition systems
include an input multiplexer, high gain instrumentation
amplifier, sample/hold and 12 bit A/D converter along
with all the necessary timing, decoding and control logic.
The model 546 DC / DC converter (+5V to ± ISV) is also
used so that only the microcomputer's +5VDC power
supply is required.
The MP7104, an analog output system, provides four
analog output channels' (using four of Burr-Brown's
hybrid 12 bit DAC80 D / A converters). This board also

ALL SYSTEMS ARE ELECTRICALLY
AND MEC'HANICALL Y COMPATIBLE
WITH MICROMOOULE AND
EXORCISER MICROCOMPUTERS.

14-34

ANALOG INPUT SYSTEM - MP720S/7216
M
I
C
R

o
C
o

SDM853 DATA ACQUISITION MODULE

haeu

-\
11

}

AI·A4

M

P

ANALOG
MULTIPLEXER

U

T
E
R

to

A
)

A5·A15

B VMARfW ~

U

S

!'

I

~

ADDRESS
DECOOER

·112
AU

A

1SELECTION

A

<'4 DO-iff]'4

ENABLE
2

.ElEI.

+5VDC

INPUT
MUX

DCIDC
CONVERTER
MODEL·54I

GRII

3-STATE
OUT

111

Vi
~

~

I

I

--:I»

YrRU.E~

-

CONTROL AND
TIMING LOGIC

GIH

•• ••
• •

Zz
~~

;;10

'"

TATION
AMPLIFIER

SAMPLEI
HOLD

t

I

I

AU=U

8 LSB'S

AU= I

4MSB'S

12 BIT
AID

CO~VERTER

-15VDC ":'+15VDC

ANALOG OUTPUT SYSTEM - MP7104
+5VDC

'ElEI'

GRO

DC - DC
CONVERTER
MODEL 546

VMA
RfW

.~

M

I

A2
AI

R

o
C
o
E

--..

AD
112

~

B

I(

U

.:--..,.
7

V'

r·

~

:---v

L
A
T
C
H

~L
'-

r
OAC I STROBE
OAC 2 STROBE

I OF 4
DECODER
AND WRITE
CONTROL
LOGIC

~

DAC 3 STROBE
DAC 4 STROBE
STROBE

DO
J

r---

ADDRESS
DECODER

I

R

S

r

~

n-

I

H V .

C

M
p
U
T

~

f---+ +15VDC
f---+ -15VDC

\/

I(

I~

t

•

8 BIT LATCH
8 lSB'S

4 MSB'S

14-35

'-

r

~

IV

A
T
C
H

~~
r---v'~

:

~tA

'-

~
r-v

T
C
H

'ElElI
D/A.
CONVERTER
DACaO
1

IEaI~1
DIA
CONVERTER
DACaO
2

...
...

A
N

A
L

o
G

o

11:3&:11
DIA
CONVERTER
OACaO
3

U

T
p

r+ U

T ~
S r:::

a..

'ElElI
DIA
CONVERTER
DAC80
4

-f+

==

OPERAttNG
INSTRUCTIONS

·SPECIF'CATIONS

All specifications typical at 2S"C unless otherwise noted '

ANALOG INPUT
Num'~er of analo'g inputs

MP7208
MP7216
±IOmV to ±IOV
4-20mA. IQ-SOmA

8 Ithanne1 differential
1,6 channel single-cnded
Input voltage rangelll
Input· ,current loop ranges
(resistor programmable)
ADC gain" ra.~ges
{stJ:ap selecta.ble)
Amplifier gain range
(resistor programmable)
Amp!ifier gain equation
(resistor programmable)

±IOV. 0 to IOV, 0 to

~V

±5. ±2.5V
I to 1000 V V
G = I + 20"kU R,xI .
±15V
100 megohms

Input overvoltage protection
Input impedance
Bias current

INSTALLATION
The MP7104, MP7208 and the MP7216 are shipped from
the factory calibrated' and ready fQr immediate use.
Installation requires only plugging the card into any
empty slot in the EXORciser or with a Micromodule and
routing the board's mating I/O cable to the back panel.
The cable supplied with each board is shielded and. in
the case of the MP7104. provided with the proper
terminations.

'
20nA
SOnA
1.2mV. rms; 7mV. p-p

2S"C

o to 70"C
Amplifier output noise
(Gain = 100 R, = SOOIl)
Amplifier input offset voltage (max)(·)

4OO~V

Amplifie~

2~~JlV"C

input offset voltage drift (max)

PROGRAMMING

TRANSFER CHARACTERISTICS
Rl!solulion

12 bits binarv

Thrqughpul accuracy. ±IOV range (max)
±WmV range
Temperature coefficient of accuracy
±IOV range (max)
±lOmV range
Conversion time ±IOV range
±IOmV range
CMRR (for differential inputs)
Sample hold aperture time

±O.025l;( FS,R'!t
±O.ISi FSR
±O.003('( FSR T
±O.Olci FSR T
33 microsecond!>'
100 microsccond~
74 dB 11K to 20()() H,)
30n~

DIGITAL INPUT/OUTPUT
All signals are compatible, wit.h
computer bus
Output coding

Micro~

A n analog input channel is selected by:
Th~ output data bits are read into:,1 1

POWER REQUI.R-EMENTS
MP7208. MP7216
MP72I7-NS. Mpn09-NS

Bipolar. Two's Complement:
unipolar. straight binary
.:ll through 6i
DO through D7
+SVDC ±S9C at I amp. 2SmV ripple
{ +SVDC ±S0i· at +SOOmA. 2SmV ripple
+tSVDC±3~r at +50mA. 5mV ripple
-lSVDC ±3C:i at -75mA. SmV ripple

TEMPERATURE RANGETemperature

o to 70"('

ANALOG OUTPUT
Number of analog 'outputs: 4
O.utput voltage rang~llt
Output impedance
Output settling 'time

,MP7104
±IOV. 0 to IOV. ±SV. 0 to SV. ±2.SV
at SmA (strap selectahle)
III
< 10 microseconds

TRANSFER CHARACTERISTICS
Resolution
Throughput aCcuracy (max)
Temperature coefficient of accuracy
Unipolar
Bipolar',

12 bit\ binary
±O.O 12S','i FS R

±O.OO3'ic FSR: "C
±O.004S% FSRt"C

'.

DIGITAL INPUT/OUTPUT
All signals are compatible with M icrocomputer bus
An analog o~tput channel is selected by:
The input data bi~$ are read by:

Programming of these analog I/O. boards is easily
accomplished since all are treat<;d as memory locations.
The M P71 04 uses any memory reference instruction that
can write data from the index and stack point registers or
the accumulators. In a similar manner a channel in the
MP7208 or MP7216 can be read by any memory
reference instruction that can read data into the index and
stack pointer registers or the accumulators.
The voltage data for theSe boards is represented by a 12
bit two's complement binary number. Each bit has a value
of 4.SSmV. with the polarity of the voltage indicated by
the sign ·of the binary number. Since the index. stack
pointer and A and B accumulator pair registers are 16 bits
long and the data word is 12, bits. the MP720S and
M P7216 set these unused bits to the same value as the
most significant bit of the data. This assures the proper
representation of the data's sign.
Each board is set lj.t the factory for a block of addresses
beginning at EFOO. Any analog data channel requires two
memory locations since the digital data is 12 bits. The
most significant 4 bits of data are always located in an
even location while the remaining S bits are located in the
next higher location. Thus. the first analog channel is
located at EFOO and EFOI while the second analog
channel is located at EF02 and EF03. When moving data.
all boards require that the most significant bits (even
addresses) be referenced first. In addition. the M P7208
and MP7216 systems require: the most significant data to
be read followed by a NOP instruction for proper starting
of the ·conversion process. This can be illustrated as
shown below:

I\IandA2

iTo through m

LDAA
NOP

EFOO

LDX

EFOO

POWER REQUIREMENTS
MP7104

+SVDC ±S% at +1 amp. 2SmV ripple

{ +SVDC ±S% at +500 mA ±SmV ripple
MP710S-NS

TEMPERATURE RANGE
T~mperature

Starts conversion of CHO
Allows processor to halt
during conversion
Reads data as soon as
conversion is complete

+ISVDC±3r;f at +1·OOmA. SmV ripple
·15.VDC ±3(;( at -IOOmA. 5mV ripple

o to 70"C

14-36

± IOV range.
(2) FSR is Full Scale Range (i.e .• 20V for ±IOV range, IOV for 0 to +IOV range).
(3) The 4 MSB's when conversion is complete, followed by the M LSB's.
(4) Adjustable to zero.

(l) Conriected at the factory for

BURR - BROWN ®

IElElI

MICROCOMPUTER ANALOG INPUT SYSTEM
A LOW-COST 12-BIT. 16-CHANNEL ANALOG INPUT SYSTEM COMPATIBLE WITH
MOTOROLA MICROMODULE AND EXORciser® MICROCOMPUTERS

A1

ADDRESS BUS

A4

A5
A15

VMA

1\

LATCH

-V

R/W

vi

OECOOER
AND
CONTROL
LOGIC

ANALOG
INPUTS

ANALOG
MULTIPLEXER

••
•

CH1 5

Y·STRU."TATI..
AMPLIFIER

~

STATUS

,+
~

CONTROL
LOGIC

~

I-C

=2
we(
>::!l
2::!l

12 BIT
AID CONVERTER

Cc

'"''"'

~

0 - ~->-.
0 - f.6-~
0-

I

f-Co.

7

CHB

16 CHANNEl

+ +

ADDRESS BUt AOORESS

,8'2

AD

---l\

""-.7
TRI-STATE
OUTPUT

DATA BUS

D

FEATURES
• 700C BURN-IN
• OPERATES FROM COMPUTER'S ±12VDC,
+5VDC PDWER SUPPLY
• ACCEPTS LOW LEVEL INPUTS
• EASY TO PROGRAM

Intornatlonal Airport Industrial Park· P.O. Box 11400· Tucson. Arizona B5734 . Tel. (602) 746·1111 . Twx: 910-952·1111· Cable: BBRCORP . Tolex: 66-6491

14-37

DESCRIPTION
The MP7218 is all analog input micr.operipheral board
desigriedto be used with Motorola's Micro(llodule aDd
EXORciser@microcomputersystems. It is eleetficallyalid
mechanically compatible with these systems. The analog
system is contained on a single printed circuit board that
.is treated as memory by the CPlJ. The analog interface is
at a connector on the opposite edge oftheboardfromthe
bus connector.
This data acquisition system includes 25V input
overvoltage protection, an analog multiplexer, high gain
instrumentation' amplifier, and 12 bit A/O' converter
along with all the necessary timing, decoding and control
logic. The unit. operates from the microcomputer's
+5VOC and ±12VOC power supplies. The MP7218 is
capable of interfacinB ±lOmV to ±5V signal levels.
When programming with this peripheral, it is treated as
memory. The A/Oconverter output is Ii 12 bit word so
two 8 bit memory locations are needed for each channel.
Address bits A15-A5 select the'boafd and A4-AI select
the analog input channel to be digitized. To start a
conversion the board is written to using an STA or similar
instruction. After convc;rsion data remains in the output
latches waiting to be read until another conversion is
initiated. This unit may be used with or without halting
, the CPU or in the interrupt mode.

SPECIFICATIONS
All specificatiQDS typical at 2SoC unless otherwise noted.

ANALOG INPUT

MP7218

'.

8 differental{16 singie-ended('1

NUlJ!.ber: of.~nalog inputs

± IOmV to ±SVw

Input ian'ge
ADC gain ranges "

°

("r~p,selecta~le)

Amplifier gain range
Factory set ,gain
Amplifier gain equation
(resistor programmable)
Input overvoltage protection

G

=

\

±2SV

100 megohms

Input impedance. DC
Bias current
2S"C
to 70"C
Amplifier output noise
100 R, SOOn)
(Gain
Amplifier input offset voltage, max
Amplifier input offset voltage
drift. max

20nA
SOnA
>.1{2mV. r01S;"7mV. p-p

°

=

to SV
±5V, ±2,SV
I to 1000
I
I + 20kOiR ....·

=

400"V
,(2 + 20,G)"V!"C

TRANSFER CHARACTERISTICS
ResQlution
Throughput accuracy, (±5V range, max,)
±IOmV range
Temperature coefficient of accuracy range, max
±SV
±IOmV range
Conversion time ±SV range
±JOmV range
eM RR (for. differential inputs)

I

12 bits binary
±O.02S% FS R(.11
±O.I% FSR
±0.004% FSR!"C
±O,OI% FSR!"C
50 microseconds
100 microseconds
90dB (DC to 60 Hz)

DIGITAL INPUT/OUTPUT

The MP7218 is jumpered at the factory with the first
channel Ilt address 93E016, the second at 93E216, etc. By
changing jumpers, the boards may be placed anywhere in
memory.

AlilOignaJs are compatible with
"M icrocomputer bus
Output coding
Logic loading (all input!!o)
Data bu~tput drive
HAI.T. IRQ. NMI nutpul driw

Bipola~ two's complement(~1
One LSTTL load
20 TTL loads
10 TTL loads

POWER REQUIREMENTS
Power supply voltages

Range for rated accuracy

+SVDC at 100mA.
+12VDCapOmA
-12VDC at 7SmA
4.75V to S.2SV and
±I k4V to ±12,6V

TEMPERATURE RANGE
Temperature
(I)
(2)
(3)
(4)

O"Cto 70"C

Connected at the factory as 8 channels differential.
Connected at the factory for ±5V range.
FSR is Full Scale Range (i.e .• IOV for ±5V range. SV for 0 to +SV range),
Straight binary jumper selectable. (W80. W81)

MECHANICAL CFlARACTERISTICS
Compatible with EXORciser and Micromodule card
spacing.
Minimum card spacing: 12.7mm (OS')
Microcomputer bus connector required: 86 pin PC edge
connector with 0.156" contact centers (SAE-430/ 1-2).
Analog connector: 50 pin PC edge connector with 0.100"
contact centers. Burr-Brown part number: 2250MC
(Viking # 3VH25/ IJNS - solder tab). Scotchflex cable
connector also available from 3M (#3415-0001).

14-38

,MP7408
MP7432

BURR- BROWN@

IElElI

MICROCOMPUTER ANALOG 1/0 SYSTEM
A LOW-COST 64-CHANNEL ANALOG INPUT12 CHANNEL ANALOG OUTPUT
SYSTEM COMPATIBLE WITH MOTOROLA MICROMODULE AND EXORciser® SYSTEMS
8 TO 64 ANALOG INPUTS

t---------'-1\

,----l\ LATCH
1\
A15
ADDRESS
Ai
OECODER
ASO
L...CONTROL AND
ASI ~
~1:r--t-_====~+_-+_-l--.~TI~M~IN::G;l:OG::I:.C
VMAIVUA
HAlTIIRO

Y

~

--.J

...
tt / ' L~,
H2 ~:t::::::::::::::::::::::::::::::::::::::::::::::::t::::t=::::::::::::1~::::~~LLE~N::AB~LIE
~

, OATA D7<;A
'-.-_++_...Jt..
BUS
.J\
DO r - + - - - - - - - - - - + - 1 I - - - - , V

lA--

OATA
BUS
INTERFACE ~

~

READ/WRITE
CONTROL LOGIC

-V

~

l
+5VDC
GRD

...

:

~

iV'~r.--:.~~~~~~~~~~~~-VLM=U~LT;IP~lE=X=ERJ:==t=.~~

...

AD
Al
RiW

7:
ANALOG

OC/OC
CONVERTER
(OPTIONAL)

OAC 1 STROBE
OAC 2 STROBE
1--+15VDC
~-15VDC

~

"

~
V

INSTRUMENTATION
AMPLIFIER

8 BIT
AID CONVERTER

~==:::::
L
D/A
A
T CONVERTER
C (OPTIONAL) 1
H

L
A
T
C
H

D/A
CONVERTER
(OPTIONAL) 2

FEATURES
• EASY TO PROGRAM
Systems are treated as memory
• REDUCES SYSTEM DEVELOPMENT TIME
• EASY TO USE
8 to 64 Input channels on one board
Analog input and output on one board
High level or low level inputs
• 70°C BURN-IN
Inlernational Airport Induslrlal Park - P.O, Box 11400 - Tw:son. Arizona 85734· Tal. 16021 746·1111 . Twx: 910-952-1111 • Cabla: BBRCORP - Telax: 66-6491

14-39

D~ESCRIPTION
This micrqcoIIlPuier peripheral prov~des two functjon~,
that interface directly to Motorola's,Mii:romoduk and
EXORciser" microcomPuterS. The !,'functions are: (I)
Analog Data AcqU:isition' and (2) Analo~Output.Both
analog input and output systems~F. CQntained olHI,slngle
printed circuit board that is treated as memory input or
output by the CPU. The analog interface is atconnect'QrS
on the opposite edge of the board from the bus connector;

SPECIFICATIONS
specifications
All

typical at 25"C unless otherwise noted.

ANALO.G INPUT/OUTPUT SYSTEM
ANALOG. INPUT
Number Of an~log inputs

,

.,

. 8 rliffetenli"al (16 signal-endedf1
32 dif~\enl.ial.(64 singie-.ended)16)
lr"put

MP7408
MP7432

v~[tage r~nge!ll

±5mV to ±5V

AD~ ~n rangesnt

±IOV. 0 to lOY 0 to SV
±SV, ±2.SV
1 to 1000

(strap selectabfe)
AmpliflCt.)gain rangel11
. (rcsisto'r programmable)

The Data Acquisition System is availabIewith up to 32
channels differential (64 channels single-ended) on one
board. It includes an input multiplexer, high gain
instrumentation amplifier, 8-bit AID converter along
with all the necessary timing, decoding and control logic.
This system can digitize low level or high level analog
signals. The gain of the internal instrumentation
amplifier can be programmed with a single external
resistor to allow input signal ranges as low as ±2.SmV.
This means that the MP7400 can. be connected to low
level sensors such as thermocouples and strain gauges
without external signal amplification. A DC! DC
converter (+SV to ± ISV) is also available so that only the
computer's power supply is required. The 'nata
Acquisition System is available with two optional 8-bit
D I A converters to provide analog output in addition to
input on the same board.

G

Amplifier gain equation
Input o\-ervoltage protection

±ISV
100 megohms

Input impedance
Rias current
2S,,{, (max)
O"{' to 70"C

+300nA
-2nA "C:

±(S +

Amplifier input offset voltage drift

When programming these penpherals, they are treated as
memory locations. Any memory reference instruction
can be used. Two memory locations are used by the
analog input system. One location is used to seleCt the
channel and start conversion. The same location provides
status informatipn when read. The other location
contains the converted data. The analog output system
also uses two memory locations, one for each channel.
Because these units are treated as memory, a minimum of
instructions are needed to read an input channel or to set
the output of a DI A converter. The MP7400's versatile
memory mapped operation allows it to be used with or
\Vithout' halting the CPU or in the interrupt mode.
."All of these units are jumpered at the factory for address
95FO through 9SF3.

I~) ~Vi"C

ANALOG INPUT TRANSFER CHARACTERISTICS
8 bit binary
±O.4% FSR'"
±O.5% FSR

Resolution
Throughput accuracy ±5V range (ma~)
Throughput accuracy ±IOmV range
Temperature coefficient of accuracy
±SV range (max)
±IOmV range
Conversion time ±5V range (max)
Conversion time ±IOmV range (max)
CMRR {for differential inputst11 ,

±0.02% FS R !,'C
±O.07% FS R I tIC

44 microseconds
84 microseocnds
66 dB (Gain 2)
86' dB (Gain
100)

=
=

ANALOG OUTPUT
N umber of analog outputs
Output, oJtage range l ",)

THEORY OF OPERATION

= lOOk!}, Rtxl

2
.cIOV. 0 to 10V. ±SV. 0 10 SV. ±2.SV
at SmA (strap selectable)
I!l
< S microseconds

Output impedance
Output settling time (max)

ANALOG OUTPUT TRANSFER CHARACTERISTICS'
8 bit binary

Resolutiun
rhroughput af,;f,;uracy (max)
remperaturt· coefficient of accuracy
Unipolar
Bipolar

±O.4{,il FSR

±O,OOS';j FSR i "c
±O.D I{i; FS R "C

DIGITAL INPUT/OUTPUT
All signals are compatible with Motorola
Microcomputer Bus
Output coding
An an~log input channel is selected by:
An 'analog output channel 'is selected by:
rhe input, output data bits are read through:

Bipolar, two's complement;
Unipolar. straight binary
' DO Ihrough DS
AO
DO Ihrough 57

POWEA REQUIREMENTS
M P74011. M P74J2

+SVDC +S% at J amp

MP74011-NS. MP7432-NS

{

+SVDC ±S% at SOOmA
+ISVDC ±S% at 40mA
-(5VDC ±S% at 40rhA

{

+5VDC' ±5% at 500mA
+ISVDC ±Sq at IOOmA
-15VDC ±S/'(.at IOOmA

With analog output
MP7408'AO. MP7432-AO

MP74011-NS-AO. MP7432-NS-AO

TEMPERATURE RANGE

'14-40

+5VDC ±5% at 2 amp

O"C: 10 70"C:

MP7504

BURR - BROWN ®

11:31:31

MICROCOMPUTER ANALOG OUTPUT SYSTEM
A 4-CHANNEL. 8-BIT ISOLATED ANALOG OUTPUT SYSTEM COMPATIBLE WITH
MOTOROLA MICROMODULE AND EXORciser® MICROCOMPUTERS

VUA
VMA
R/iV'

:'-~~-lr.!:::;::~r--i.-,J

112 0-1----.1
G/H

CHANNEL { AI
SELECT AD e>-jt----i.-r--J- ~1--_---I

07-+----'

OPTICAL
ISOLATORS

iiII-+-==-=:'::'J

+5VOC o--1f-------I
GROUND~I-----

OCIOC
CONVERTER

FEATURES
-OUTPUT ISOLATION/OUTPUT PROTECTION - MOTOROLA MICROMODULE AND EXORciser
COMPATIBLE
- REDUCES SYSTEM DEVELOPMENT TIME
System engineered and specified
- 4-CHANNEL ANALOG OUTPUT SYSTEM
Plug compatible
- 4mA TO 20mA OUTPUT
Operates from computer POWer supply
Easy to program
- 70°C BURN-IN
- COMPATIBLE WITH ROCKWELL SYSTEM 65

InlernatiOlll1 Alrporllnduslrlal Park - P.O. Box 11400 - Tucson. Arizona 85734 . Tel. (6021.746-1111 • Twx: 91(1.952·1111 . Cable: BBRCDRP - Telex: 66-6491

14-41

DESCRIPTION
This niicrocomputer peripheral, burned in at,70·C to
inqease. reliability' and reduce aging shift, provides four'
optically-isolated 8-I;it fused analog outpu~s that interface ..
directly with Motorola's Micromodule and EXORciser
microcomputers. The MP7S04, 

·· ··

I:

4 MSS'S

12 BIT
AID CDNVERTER

I

'I

!Ii

"5ttLc

InternaliOlial Airport Induslrlal Park, P,O, Box 11400· Tucson, ArizoRl 85734 . T81.(602] 746-1111 • Twx: 910-952·1111 • Clbla: BBRCORP· Talax: 66·6491

14-45

DESCRIPTION

~

I

These microcomputer peripherals provide two much
needed "functions t,/tat interface directly to Intel's
SBC80/1O ' and, ,Intellec MDS microcomputers. The
functions are: I) Analog Ditta Acquisition and 2) Analog'
Output. The devices are electrically and mechanically
compatible with any SBC80j

... ~DRF/~
~
...

en
en
en
::>

...

...

a:
Q
Q

~DR3/y

a: oct
I-

::>

a.
:Ii

ADR2I
ADRI/

....a:

ADRIf/

co
....
co
~

MWTCI

...
~

XACK/
I

Dl~
...oct DAT41
en
::>

I

I-

oct
Q

~AT31 r
I

I

DATil
I

V

~~

f---+ +15VDC
f---+ -15VDC

DC/DC
CONVERTER
. MODEL 546

r-

IV
~

ADDRESS
DECODER
"-

J

rDAC 1 STROBE

1 OF 4
DECODER
AND WRITE
.CDNTRDL
LOGIC

DAC 2 STROBE
DAC 3STROBE
DAC 4 STROBE

I

STROBE

.~
/

r

...

J
t

a BIT LATCH

I~

a LSB'S

4 MSB'S

14-47

'--

-

~
III

L
A
T
C

H
L
A
T
C
H

~j

-,/ H

=x:
--v'

D/A
CONVERTER
DAcao
1

f+

IElElI
D/A
CONVERTER
DAcao
2

~

A
N
A
L

o
G

---1\~A

-

IElElI

T
C
H

IElElI
D/A
CONVERTER
DAcao
3

I EI!5! I
D/A
CONVERTER
DAC80
4

o

... ~I
Too::I"

.r+

S~
co
a..
:IE.

OPERATING INSTRUCTIONS

SPECIFICATIONS'

All specifica~ions typical at '25"C uril~~ ~the~ise noted ..

ANALOG INPUT SYSTEMS
ANALOG INPUT

I.NSTALLATION

MP8408/MP8416

The MP8304, MP8408 and the MP8416 are shipped from
the factorS' calibrated and ready for immediate use.
Installation requires only plugging the card into any
empty slot in the computer and routing the board's
mating I/O cable, Cable placement is shown on page
1O~30. The cable supplied with each board is shielded
and, in the case !lfthe M P8304, provided with the proper
termination.

Number of analog inputs

8 differential

'-16 single...ended
"Input voltage rangell !
I nput current loop ranges
(resistor programmable)
ADC gain ranges
(strap selectable)
Amplifier gain range
(resistor programmable)
Amplifier gain equation
Input ovcr\!oltage protection
Input impcdance
Bias current

2S"C

MP8408
MP8416
±lOmV to ±J.OV

ItolOOOVV
G = I + 20 kU Rio:",
(resistor programmable)

±ISV
100 megohms

PROGRAMMING

Amplifier output noj~

20nA
SOnA
1.2mV. "rms; ?mV. p-p

(Gain 100 R, Sooll)
..
Amplifier input offset voitagt! {max)I~1

4OO~V

Amplifier input offset voltage drift

2+

oue to 7Q"e

=

=

:.

4·20mA la-SOmA. ClC.
·±IOV. 0 to IOV. 0 to 5V
±SV. ±2.5V

~ ~V

Programming of these analog I/O boards .is easily
accomplished since all are treated as memory locations.
The MP8304 uses a single SHLD instruction to load any
of its four digital to analog converters from the Hand L
registers: In a similar manner a channel in the M P8408 or
MP84.16 is read by a single LHLD instruction.

"C

TRANSFER CI:IARACTERISTICS
Resolution

12 bits binary

Throughput accuracy ±IOV range.(max)

±O.02sc:i

±IOmV range
Temperature coefficient of accuracy
±IOV range (max:
:tlOmV range
Conversion time ±IOV range
±IOmV range
eM RR (for differential inputs)
Sample hold aperture time

±O.lf;; FSR

FSRI~!

The voltage data for these boards is represented by a 12
~it two's complement binary number. Each bit has a value
of 4.88m V, with the polarity of the voltage indicated by
the sign of the binary number. Since the Hand L register
pair is 16 bits long and the data word is 12 bits, the
MP8408 and MP8416 set these unused bits to the same
value as the most significant bit of the data. This assures
prop.:r representation of the data's sign.

±O.003 fi; FSR "c
±O.Olc;; FSR "c
33 microseconds
100 microse(!'onds
74 dB (DC 10 2000 Hz)
30ns

OIGITAL INPUT/OUTPUT
All signals are compatible with
Microcomputer bus
Output coding
An analog input channel is selected by:
The output data bits are read into:' II

POWER REQUIREMENTS
MP8408. MP8416
MP8417·NS, MP8409-NS

Bipolar. Two's Complement;
unipOlar. straight binary
ADRI Ihrough ADR4
DATO, Ihrough DAT7

Each board is set at the factory for a block of addresses
beginning at F720. Any analog data channel requires two
memory locations since the digital data is 12 bits. The
least significant 8 bits of data are always located in an
even location while the remaining 4 bits are located in the
next higher location. Thus, the first analog channel is.
located at F720 and F721 while the second analog
channel is located at F722 and F723. These boards can
occupy the same address space as· memory ·since they
inhibit memory whenever they become active.

+SVDC ±SyC at I amp. 25mV ripple
{+SVDC ±S0i al +SOOmA, 2SmV ripple
+ISVDC ±3tJi at +SOmA. SmV ripple
·ISVDC ±3% al ·7SmA. SmV ripple

TEMPERATURE RANGE
Temperature range

O"C to 70"C

ANALOG OUTPUT SYSTEMS

MP8304

ANALOG· OUTPUT
Number of analog outputs
Output ,voltage .rangerll
Output impedance
Output settling time

4
±IOV. 0 10 IOV. ±SV. 0 10 SV. ±2.5V
at SmA (strap selectablef

III

< J0 microseconds

MECHANICAL CHARACTERISTICS

TRANSFER CHARACTERISTICS·
Resolution
Throughput accuracy (max)
Temperature coefficient of accuracy
Unipolar
Bipolar

·12 bits binary
±O.OI2S% FSR

. Compatible with lntellec MDS and SBC-604/614 card
spacing.
Minimum card spacing: 12.7mm (0.5")
Microcomputer bus connector required: 86 pin PC edge
connector with 0.156" contact centers,
40 pin analog connector (3M -3432) provided on board.
Mating connector (for OEM versions) is 3M - 3417.
Recommended cable also by 3M; 3476/40.

±O.003% FS R!"C
£o.OO4S% FSRi"C

DIGITAL INPUT/OUTPUT
All signals are compatible with
~ icrocomputer bU;s .
.; An analog'Qutput channel is selected by:
. The input data bits are read by:

'POWER REQUI.REMENTS
MP8304
MP830S·~S

ADR I i and ADR2,
DATO, Ihrough DAT7;
, +SVD·C ±S% at +1 ~mp. 25mV ripple
{+SVDC ±S% al +1 amp. 2SmV ripple
. +15VDC ±311c
+i.oOmA. 5mV ripple
·ISVDC ±39, al·loomA, SmV ripple

at

Temperature range

(I) Connected at the factory for ±IOV range.
•(2) FSR is Fun Scale Range (i.e.. 20V for ±IOV range, 10V forO to+IOV range).

TEMPERATURE RANGE

(3) The 4 MSB's when conversion is complete, followed by the 8 LSB's.
(4) Adjustable to zero.

O"C 10 70"C

1448

BURR-BROWNII

MP8316-1
MP8316-V

IElElI

MICROCOMPUTER ANALOG OUTPUT SYSTEM
FEATURES
• 16 CHANNELS
.0- 24.57mA or ±IOV OUTPUTS
• SINGLE GAIN AND OFFSET ADJUSTMENT
• MEMORY MAPPED or I/O OPERATION
• UP TO 2O-81T ADDRESS BUS
• 12-BIT RESOLUTION
• MULTlBUSTM COMPATIBLE

MuIUIIuI TM. Intli Corp.

DESCRIPTION
Dynamic analog outputs allow the M P8316 to provide
high channel density on a single board. This approach
frees system space for other peripherals and minimizes
per channel power requirement. An on-board DC-to-DC
converter powers the MP8316 from the system +5VDC
supply. Channel data is stored in an on-board RAM and
used by the refresh circuit to update outputs. Each
channel is factory-adjusted to allow system calibration to
be accomplished with a single gain and offset adjustment.
Memory mapped or liD operation is a jumper-programmable option on the board.
Two models of the MP8316 are available. Both models
have 16 analog outputs and 12-bit resolution. The current
output model (MP8316-1) will sink up to 24.57mA .on
each channel and is well suited for 4mA to 20mA
operation. The voltage output model (M'P83 16-V) can be
jumpered for bipolar or unipolar operation. Both units
conform to Intel's M ultibus"I"M specification.

DATA

BUS

I

I
I

CHI5

I
I

L.I __ __ JI
~

DC·TO-DC

r:

+5VDC

GND

"'-----"

Inflnllllenil Airport IndtillrIll Park· P.O. Box 11400· TUGI8/I. ArlzDIII 85734· Til. 1602) 748·1111 : Twx: 910-952·1111 . Clble: BBRCORp· Telex: 86-6491

14-49

SPECIFICATIONS
ELECTRIC~L

"

,

,'"

Typical ai 2s00' and raled pel,"e, supPlies unless 9therwiSe specifi.K! ..
MODEL

MP8316-1

'MP8316-V

Current sink
16
12-bit
to 24.S7,mA
10Vmi n
SOV max
,lWmax

'voltage
16
'12-bit "
±lQV, ±sV;, ±2.5V

OUTPUtS
Type
Num ber of Channels
Resolution
Aange

o

ACCURACY
Total Accuracy{ 1i max
Offset Error
Linearity

Gain Error
Crosstalk
Temperature Coefficient

, ,
Qto+10V
" 0 to +sv,at SmA max
±0.07% FSA
±1I2LSB (0.012%)
±1/2LSB '
O.OS% FSA
,.'±lI2LSB
±30ppm/oC

INH2I

Prevents ROM from responding.

84,5~sec

845~sec

MWTCI

M~m.ory

46.2~sec

46.2~sec

IOWCI

1/0 write command.

8.Smsec
11msec

3.Smsec
5msec

XACKI

Slave acknowledge to host CPU that data has
been taken from data bu~ forwfite operatton or that
valid data has been placed on the bus for read
operation.

BPANI

BUS PRIORITY IN - indicates that no higher

BPAOI

BUS PFUORITY OUT - passed to BPANI input of the
next lower .prior.ity module.

Refresh Scan Time
Charge Time per Scan
Settling Time
to 0.1% of FSR
to 1/2LSB
DATA HOLD TIME ON BUS

Multibus TM

I

Multibus™

I

1.SA

I

1.SA

Description

INITI

T~is

INH11

pie~ents RAM from respondfng.

signal resets the system.

prio~ity

ENVIRONMENT
Operating' Temperature
Reiative Humidity

Control Line

200nsec

200nsec

I

POWER
+5V ±5'111 (system bus)

TABLE I. Description of Control Lines,

±o.1% FSA(2)
±1/2LSB (0.012%)
±1/2LSB
0.1% FSR
±1I2LSB
±50ppml"C

TIMING

BUS CONFIGURATION

a write operation t'o the appropriate channel. When this
occurs, the refresh circuit disables ihe multiplexer to
prevent output glitches and to 8;UoW the CPU to change
the RAM data:
" ,
Table I des~ribes the Mul~ibti~l"1 controi ~ignii1S';used by
the MP8316. The pinout of the bus connector (PI)
conforms to the M ultibus™ specifications. Control lines
BPRN! a:r'Ki:SPRO/ are connected so that the MP8316
" will not interfere with mUltiple processor operation when
the seria'!' priority technique is used. The auxiliary
connector (P2) is not used.

write command.

module is requesting the b~s.

ooC to +7000
9S% noncondensing

'NOTES:
1. With gain and offset error calibnited as described under Calibration,
includes linearity error, channel·to-channel offset error, channel-to-

channel gain error and crosstalk.
2. FSR is full scale range.

. OPERATING INSTRUCTIONS
INSTALLATION
The MP8316 comes factory-adjusted and ready for use.
Analog outputs are available onco~nector P3. Current
outputs require an external current source (see Figure I).

P3
r---'

MECHANICAL

I

Compatible with Intellec MDS and iSBC-604/614 card spacing.
Minimum card spacing: 1S.2mm (0.6").
Microcomputer bus connector require9: 86-pin PC edge connector with

1+

:

~------------~--~

I
I

0.156" contact centers.

I
CH14 :
I

5O-pin analog edge connector on boerd for analog outputs,
0.100" contact centers.
Mating connectors:
"
Burr-Brown 2250MC (Viking ~3VH2S/1JNS, solder tab).
3M Corporation 341S-0001 (Scothflex, for flat cable I.

THEORY OF OPERATION
The dynamic output approach uses a single digital-toanalog converter (DAC) to drive all 16 outputs. Digital
data for each channel is stored in anon-board RAM and
analog output data for each channel is stored in separate
sample/ hold circuits. The refresh circuit contains a
channel counter that selects the appropriate DAC input
from RAM for the channel being updated and multiplexes the DAC output, to, the appropriate channel
sample/ hold. Thus, the output data is updated, independent of the Itost CP·U. TheCPU c~angesdata in' RAM by

4

CH15:

I
MP8316-1

P3
r-:--,

:0:'i

1+ I

.. !
I

I

47

iL __ .....:

MP8316-V

FIGURE l. Connections for Current and Voltage
Outputs. '.

14-50

BURR - BROWN ®

MP8418

113131

MICROCOMPUTER ANALOG 1/0 SYSTEMS
A 31-CHANNEL ANALOG INPUT. 2-CHANNEL OUTPUT SYSTEM
COMPATIBLE WITH INTEL SBC80. INTELLEC® MDS AND
NATIONAL BLC-80 MICROCOMPUTERS

FEATURES

'DESCRIPTION

• HIGH AND LOW LEVEL INPUTS
• SOFTWARE PROGRAMMABLE GAIN (1 10 10241
AMPLIFIER OPTION
• ANALOG INPUT AND OUTPUT ON ONE BOARD
• EASILY PROGRAMMED
• MEMORY MAPPED
• LOW COST
• BURN-IN

The MP8418 series of analog I/O peripherals are
electrically and mechanically 'compatible with and
interface directly to Intel's MULTIBUS® and other
microcomputers of similar configuration. These analog
systems are treated as memory by the CPU.
The analog input portion of the M P8418 includes: overvoltage protection to 26VDC; provision for up to eight
4mA to 20mA inputs; an analog multiplexer; resistor
programmed instrument amplifier Of, a software
programmable amplifier (gain of I to 1024); sample/ hold
amplifier and; a 12-bit A/D converter. An' optional
analog output system is included on the same board. It
consists of two 12-bit D / A converters with double
buffered inputs to minimize glitches, and control logic.

u.._~5:=~F.'=

M P8418 is a IS-channel differential (user strapable as 31
channel single-ended) analog input system. With one
expander board the system can be expanded to 63
differential channels (strapable as 127 single-ended
channels). Another input channel is grounded on the
board so that it may be used as ground reference for
automatic calibration.
Gains of I to 1024 are software selectable for the
programmable amplifiers and the gain for each channel
(up to 127 channels) may be stored in an on-board RAM
if desired. The proper gain for each channel is then
selected automatically by the MP8418.

International Airport Induslrial Park· P.O. Box 11400· Tucson. Arizona 85134· Tal. (602)146-1111· Twx: 910·952·1111 . Cable: BBRCORP· Talex: 66·6491

14-51

ITF~:::-i~-----

1------

+5voc----li:::-.:-1

OUT I
AO RETI

Analog

6RO----I

Outputs

...._ _,1---0 ·15VOC

1------ OUT2

L:.J.:.:;,;;;:::.::.t------ AO RET2'

BLOCK DIAGRAM- MPB41B-AO

A/O converter output and 01 A converter input are 12bit words. therefore. two memory locations are needed
for each channel. The address, block occupied by each
M P8418 is user selectable and can be placed anywhere in
memory.

MECHANICAL
SPECIFICATIONS
Compatible with Il)tellec MDS and SBC-604/614 card
spacing.
, Minimum card spacing: IS.2mm (0.6").
Microcomputer bus connector required: 86-pin PC edge
connector with 0.IS6" contact centers.
One SO-pin analog edge connector on board for analog
inputs.
Mating connector available from Burr-Brown:
22S0MC. (Viking IHVH2S, IJN5. solder tab);
from 3M: 3415-0001 (Scotchl1ex),
Two 20-pin analog edge connectors on board for analog
outputs and analog input expansion.
Mating connector available from Burr-Brown:
2220MC. (Viking lt3VH 10, IJN5).

OPERATING INSTRUCTIONS
INSTALLATION
MPS41S is ship,ped from the factory calibrated and ready
to use. Installation requires only plugging the card into
any empty slot in the computer ,and wiring the analog
connector.
PROGRAMMING
This peripheral is programmed as a memory location and
any memory reference instruction can be used. ,Both the

Because these peripherals are treated as memory. a
Il;linimum of instructions are needed to read an input
channel, or to set the input oCa 01 A converter. For
example: when the MP.s4IS is conneCted in the HALT
mode, the LHLO (load) instruction followed by the
proper address can be used to read data from an analog
input channel. It will automatieally select, the desired
channel, ,initiate conversion and when conversion is
complete, transfer the A/O converter output' to the
S080's Hand L registers. The eight least significant bits
(LSB's) of the data wc,>rd are transferred to the CPU first
followed by the four most significant bits (MSB's). The
four MSB's are in data buspositionsO-3. A singleSHLO
instruction can be used to write data to one analog output
channel. The eight LSB's are written first, followed by the
four MSB's(in 00-03). When the four MSB's are written
to the board, all twelve bits of, the' data word are
transferred simultaneously to the 01 A converter input.
ADC/DAC Bit Placement

Low Byte
High By'"

1>7

1>6

1>5

D4

D3

02

[)I

•

~

•

&

•

•

•

[)O
~

X

X

X

X

B'J

Bin

By

BM

On MPS4IS's, with the software programmable gain
,amplifier,an Qn-board random access memory (RAM)
may, be used, to store the gain for each channel. In this

14'::52

mode, (Control Register D4 = I). lh~ proper
gain is automatically selected from the RAM
when a channel is converted. If the RAM is not
used (Control Register D4 = 0). the amplifier
gain must be written to an on-board register
(Control Register DO-D3).
All these systems are jumpered at the factory
with a base address of F700,o. Each subsequent
channel is two memory locations past the start of
the last channel, consequently channel one is at
location F702,o, channel two is at location
F704,o, etc.
The input system operates in several modes:
INTERRUPT MODE: A read instruction tothe
board (ADRO = 0) starts the conversion. An
interrupt is generated at the end of the
conversion. The interrupt can be connected to
any of eight vector locations and may also be
disabled by software. Control Register D6 = I
enables interrupt for interrupt mode.
POLLING MODE: A read to the board starts
the conversion. The interrupt is disabled by
software and the CPU may then read the status
word to determine when conversion is complete.
Control Register D6 = 0 disables interrupt for
polling mode.
HALT MODE: a read instruction to the board
starts the conversion. The M P8418 halts the
CPU until conversion is complete, at which
point the data is transferred to the CPU. Only
one instruction is needed to start conversion and
to transfer data to the CPU (an LHLD or POP
referenced to the channel's LSB's can be used).
CONTINUOUS MODE: A read instruction to
the board starts the conversion. The CPU is not
halted, but reads the status of the MP84I8 to
determine when conversion is complete (Control
Register D6 = 0) - or the CPU waits for an
interrupt (Control Register D6 = I). When
conversion is complete, the CPU reads the data.
The read instruction is addressed to the next
channel to be converted. The data from the last
conversion is thus transferred to the CPU and
conversion is started for the next channel.
EXTERNAL TRIGGER: This mode allows a
conversion to be started independent of the
CPU. A read instruction is required to set the
proper channel. Once the board· has been set, a
low to high transition of the EXTERNAL
TRIGGER input (P5, pin 20) will start
conversion. End of conversion can be detected
by polling or interrupt technique. Data is
obtained by any read command. The external
trigger will start conversion independent of
other board functions. The busy input (P5, pin
19) goes high at the start of conversion and goes
low when the MSB ofthe converted data is read
by CPU.

ELECTRICAL SPECIFICATIONS
Typical at 2S"C and rated power supplies unless otherwillt noted

ANALOG INPUT SECTION
INPUT CHARACTERISTICS

MP8418

Number of Channels

3J si!lgle-ended l IS differential

A~ Gain Ranges (Jumper Selectable)!!!

010

Amplifier Gain Ranges
Resistor Programmable!~11 Software Programmable

SV.

0 10

10V. ±2.SV. ±SV. ±IOV

I 10 1000,1

Maximum Input Voltage Without Damage!·')

10

1024

±26 volts

100Mll. IOpF OFF Channel
100Mll. 100pF ON Channel
±20nA
±SOnA
±IOnA

Input Impedance

Bias Currenl (2S"q
Bias Current (0 to 70"C)

Differential Bias Current
Amplifier Input Offset Voltage G = 1000
Resistor ProgrammablejSoftware Programmable
Amplifier Input Offset Voltage Drift G = 1000
Resistor Programmable/Software Programmable
TRANSFER CHARACTERISTICS
Resolution
Throughput Tlme (max) G = I
Resistor Programmable, Software Programmable
Throughpul Time G = 1024
Resistor Programmable l Software Programmable
ACCURACY
System Accuracy at +25"C (max)'~1 G = I
System Accuracy at +25"C~' G = 1024
Resistor Programmable, Software Programmable
Linearity
Differential Linearity
Quantizing Error
Gain Error
Offset Error

±400",V/±4",V
±2",V,"C,±I",V,"C
12 Bits
38",sec, 350J,lsec
IOOJA5eC,3SO",sec
±O.032S% FSR'"
±O.I<;( FSR. ±O.OS<;( FSR (max)
±1.2LSB
±I 2LSB
±I 2LSB
Adjustable to Zero''''
Adjustable to Zero
Guaranteed o"e to + 70"C

Monotonicity'~'

STABILITY OVER TEMPERATURE (BipOlar)'"
System Accuracy Drift (max) G - I
±4Sppm of FSR "c
±IOOppm of FSR."C
System Accuracy Drift G = 1024
DYNAMIC ACCURACY
Sample, Hold Aperture Time
I 25nsec
Aperture Time Uncertainty
86dB (DC 1060Hz)
Differenlial Amplifier CMRR. G = I
Channel Crosstalk
SOdB down at I kHz. for OFF Channel to
I
ON Channel
ANALOG OUTPUT, SECTION (AO oplion)
OUTPUT CHARACTERISTICS
Number of Channels
Output Voltage Ranges (Strap Seie<:table)
±1,ov.OIO
alSmA
III
Output Impedan~
Short Cin::uit Protection
Yes
TRANSFER CHARACTERISTICS
12 bits
Resolution
Output Senlipg Time (max)
IOl'sec
ACCURACY
±O.OI2S<;( FSR
Output Accuracy
±30ppm of FSR "c
Temperature Coefficient of Accuracy
POWER REQUIREMENTS
+5V ±5'RY MODE CONNECTIONS
fACTORY SET'MODE
HALT
HALT
POLl.I~(j INtERRLJi)'",'

POI.I,Ii"(; IN'TERRlIPP
Note:. Any model can be c«;mnected in any mode.
·'nl I ra'-'1.0ry Set

JUMPERS REQUIRED FOR
INTERRUPT VECTOR

TABLE I. PrQgramming Mode Connections.

INTO,
INTI,
INn;
INn,
INn,
INT5
INT6,
INT?,

JUMPER REQUIRED
JPI7. JP29. JPJO. JP81
JPI7. JP29. JP81
JPI7.)P31. JP82

Halt Mode
Polling and Interrupt Mode
Continuous Mode

External Trigger Mode

JPI6. JP29. JP81

TABLE III. Interrupt Selection.'

TABLE II. Mode Selection Jumpers.

Factory
ADR7 ... ADRO
Set
00000000
F700
00000001
F701
0000 0010
F702
0000 0011
F703

MEMORY MAP
CHO
IN
CHI
IN

WRITE

READ
8LSB's of offset
STATUS

NLA
CONTROL

LSB
MSB
LSB
MSB
LSB
MSB

00000100
0000 0101

CH2
IN

F706
F707
F708
F709

0000 0110
0000 01 II
0000 1000
0000 1001

Clf3
IN
CH4
IN

F71E
F71F

0001 1110
0001 1111

CHIS
IN

~

LSB
MSB

F710

00010000
00010001

CHI6
IN

I

LSB
MSB

I

NLA

LSB
MSB

F704
F705

f711

JP70
JP71
JP72
JP73
JP74
JP75
JP76
JP77

GAIN 0*
GAIN 1*

N\A

CHO OUT
or GAIN

LSB

CHI OUT
or GAIN

LSB

.... ,,-

GAIN 2*

MSB

..... ", GAIN 3*
MSB

NLA ______

GAIN 4*

N/A

NLA ____ GAIN 15·
N/A
NLA ____ GAIN 16*
NLA
N/A - Not used.

"Used only on PGA versions when RAM gain storage is used.

A read instruction (other than a STATUS REGISTER read) should not be made to the board during a conversion.
Contact factory for more ,details.
STATUS REGISTER
D4
D3
D2
DI
DO
, --------GAIN X*---------------Interrupt
ConVert
Write*
RAM*
Complete
Enable
Enable
Enable
·Used only on versions with software programmable amplifier.
D7

D6

D5

Convert Complete - The bit is low during conversion. It
goes high on completion of conversion and remains high
until the MSB of a data word is ,read.
Interrupt enable: status of interrupt enable
Write enable: ,~tatus of write enable
RAM enable: status of RAM enable
GAIN X: cuttent value stored in PGAGAIN control
register.

BURR - BROWN@

IElElI

MICROCOMPUTER ANALOG INPUT EXPANDER
FOR MP8418

FEATURES

DESCRIPTION

• 48 DIFFERENTIAL CHANNELS/
96 SINGLE·ENDED CHANNELS

MPS418-EX·P is a bank of multiplexers that expand
the analog input channel capacity of the MP841S
series microperipheral. Differential input capability
is expanded from 15 channels t063 channels. Singleended capability is expanded from 31 channels to 127
channels. Control signals and power are passed to
the expander from the MPS418. The analog input
signal is passed to the MPS4lS from the expander.
Multiplexer channel addresses are latched on the
expander board'. The expander occupies the memory
space immediately above the MPS4IS. Gain, data
conversion, and bus interface are performed by the
MP8418_ Channel gains can be stored in a RAM on
the PGA versions.

• SOLID STATE MULTIPLEXING
• 26V OVERVOLTAGE PROTECTION WITH DIODE CLAMPS
• MULTlBusrl COMPATIBLE

MulUbusTI_ Inlll Corp_

CHI8

ANALOG
SlSNAL

INPUT
CONDITIONINS

MUX

TO
MP8418

CONTROL
FROM
MP8418
ICI..

><

CONTROL

CH63

INPUT
CONDITION INS

Y.I

-

=
ooc:r
=
ICI..
ADDRESS
IUS

International Airport Induslrial Park - P.O. Box 11400 - Tucson. Arizona 85734 - Til. 1602) 746-1111 - Twx: 910-952-1111 -,Cable: BBRCORP - Telex: 66-6491

14-55

:IE

"SPECIFICATIONS
ELECTRICAL
Inputs

46 differential, '
96 sin91~::end~d

Input Protection

26V

Power

110mA (from system bus)
30mA (from MP8418)
20mA (from MP8418)

+5V
+15V
-15V

::"

,

See MP8418 Specifications for all other input
characteristics.

FIGU~E

I. System Interface.

TABLE I. Ju~perRequirements for Differential
,
Operation.
"

Install

MECHANICAL
Compatible with Intellec MDS and iSBC-604/614
card spacing.
Minimum card spacing: IS.2mm (0.6").
Microcomputer bus connector required: 86-P!n PC edge
connector with 0.IS6" contact centers.
Two SO-pin analog edge connectors on board for
analog' inputs.
Mating connectors:
Burr-Brown 2250MC (Viking#VH2S/ IJNS) ,solder tab;
3M Corporation: 341S-0001 (Scotchflex).
Interface Cable: 20-conductor ribbon cable with a card
edge connector mass terminated on each
end, available from Burr-Brown:
MP800S, I" long
SMSOI23-00I,9.5" long
INTERFACE CONNECTOR
Bottom
+15VDC
AnalogGND
-15VDO
DigGND
Dig GND
Dig GND
AnalogGND
AnalogGND
AnalogGND
AnalogGND

P5
1
3
5
7
9
11
13
15
17
19

2
4
6
8
10
12
14
16
18
20

!£I!

+15VDC
Analog GND
-15VDC
Addr, Out
EXP/
DigGND
Analog GND
AnalogGND
IAINIAIN+

Remove

'MP8418
JP4{ 45
JP33,36
JP66,67,
JP3, 4, 7'
JP42,39
JP2,5

JP3
JP1

TABLE II. Jumper Requirements for Single-ended
Operation.
Install

Remove

MP8418
JP44
JP33,37
JP66,67,68
JP2,5
JP39, 42, 43,
36,45
JP3, 4, 7

MP8418-EXP
JP1

JP2
JP3

INPUT NETWORK

The input network is shown in Figure 2. The switch
shown represents two CMOS multiplexers in series.
Input protection is provided by the series resistors and
diode clamps. The Clamps prevent the ntu1tiplexer inputs
from exceeding the supply voltages. An optional resistor
(R) allows the .user to convert current inputs to voltage
that can be detected by the MP8418. The optional
capacitor (C) in combination with the input resistors
form a low-pass filter. Low-leakage high-quality capacitors should be used to minimize errors. The optional
resistor and capacitor are only useful for differential
operation.

'INSTALLATION
If possible, adjacent slots in the system should be used for
the MP8418 and MP8418-EXP. This ,is particularly
important for low level operation where Ionger cables
introduce noise and offset errors. Analog inputs connect
to P3 and P4. Connector PS on the MP8418-EXP
connects to P4 on the M P8418 to interface the two units
(see Figure I). Tables I and II show jumper c()nfigurations
for the expander and additional jumper changes required
on the MP8418.

MP8418-EXP.
JP2

FIGURE2. Analog Input Circuit.

BURR-BROWN®

IElElI

MICROCOMPUTER ISOLATED
ANALOG INPUT EXPANDER FOR MP8418
FEATURES

DESCRIPTION

• 400V ISOLATION
.16 CHANNEL FLYING CAPACITOR MULTIPLEXER

The MP8418-ISOE expands the analog input capability of the MP84.18 family of microcomputer
boards from 15 channels to 31.47 or 63 channels by
using one. two or three MP8418-ISOE's. (Note: Only
expander channels are .isolated. The 15 channels on
the MP8418 are standard CMOS multiplexed
inputs.) A flying capacitor technique is used to
provide 400V input and channel-to-channel isolation ..
Low thermal EMF relays minimize errors for low
level operation. A low-pass inpu't filter on each input
provides 60Hz normal-mode rejection.
System interface. signal amplification. and data
conversion are provided by the M P8418. Software
options and analog signal ranges on the M P8418 are
applicable to the M P8418-ISOE. Both boards
conform to Intel's Multibus™ specifications.

• 8Hz LOW-PASS FILTER
• MUL nBusTM
• LOW THERMAL EMF RELAYS

Multihw,IM ~ Intt:l Corp.

'"l

eN 0

0>---0---.------

ANALOG
TO
MP8418

;r

"15V
CONTROL
FROM
MP8418

0----'--CN 16

l

J

=
!e
1.1.1

CO

;;:

CO

a...

:::IE
OPEN CIRCUIT
DETECTION

ADDRESS
BUS

Inler.JIatiwl Airport Induslrlal Park· P.O. 80x 11400· Tucson. Arizona 85734 • Tel. 16021746·1111 • Twx: 910·952·1111 • Cable: 88RCORP • Telex: 66·6491

14-57

MP8430

MICROCOMPUTER RTD INPUT SYSTEM
DESCRIPTION

FEATURES
.16 THREE-WIRE RTo INPUT CHANNELS
• SOLID-STATE MULTIPLEXING
• PROGRAMMABLE GAIN INSTRUMENT AMPLIFIER
• MUL TlBUSTM COMPATIBLE (lEEE-796)
• MEMORY OR liD MAPPED
• LINE LENGTH COMPENSATED
MulUbulTM_ lnlel Corpol'lllion

The M P8430 is a mUltiplexed l6-channel RTD input
digitizer. Each channel is line length compensated by
an exciter circuit which may be calibrated to the
device with balance and span adjustments. This
circuit produces a voltage. proportional to the
temperature ·of the RTD. which is filtered, multiplexed, amplified. and presented to a l2-bit analogto-digital converter circuit. The converter in turn is
interfaced to the microcomputer bus, thus providing
a digital representation of the RTD temperature to
the computer.

CHI
AID
CONVERTER·

INPUT
MULTIPLEXER

DATA BUS

RESISTOR
PROGRAMMABLE
AMPLIFIER

DECODE
AND
CONTROL
LOGIC

CMUI

ADDRESS
BUS

CONTROL
BUS

International Airport Industrial Park· P.O. Bux 11400· Tucson. Arizona 85734· Tal.

14-58

16021 746·1111 • Twx: 91(1.952·1111 • Cabla: BBRCORp· Talex: 66-6491

INSTALLATION

SPECIFICATIONS
ELECTRICAL
TYPical specifications at TA
otherwise noted.

= +25°C and

rated power supplies unless

MP8430

MODEL
INPUT
Type

3-wire resistive temperature
device! RTO I
12-bit (one-part in 40961

Resolution
Zero I balance I
Setting
Range 125-turnJ
Excitation Current
Setting I nominal I
Range
Gains Fixed
Gain Equation
user set gain,
ADC Input Range
Maximum Line Resistance
1/2-loop resistance·
One-Pole Input Filter

100n
Oil to 20011
0.7546mA
0.73mA to 0.78mA
.31 .• 100
R107 + 25kll
R107
-5VDC to +5VDC
4000n
0.33Hz

ACCURACY
System Accuracy at +25°C
Temperature Drift

±0.10n
100ppm/oC

THROUGHPUT
Throughput Time
Settling Time
Conversion Time

85,."sec
60~sec
25~sec

BUS STRUCTURE

Multibus™ IIEEE-79GI

POWER REQUIREMENTS
;-5VDC. ±5%
;-12VDC. ±5%
-12VDC. :t5%

0.35 amp
0.35 amp
0.14 amp

ENVIRONMENTAL
Operating Temperature
Storage Temperature
Relative Humidity

OOC to+700C
-25°C to +85°C
95% noncondensing

M P8430 is shipped from the factory ready for use.
I nstallation consists of setting the . correct address,
plugging the card into any empty slot in the Multibus
computer, and wiring the RTD connector.
ADDRESSING

M P8430 may be operated either memory-mapped or
I; O-mapped (jumper selected). The board occupies four
bytes of address space and can be placed on any four byte
boundary. Eight, 12, 16, or 20-bit memory or 1;0
mapping are selectable.
PROGRAMMING
M P8430 is programmed in either the polled-mode or
interrupt-mode, the difference being that the status
register must be read in the polled-mode to determine.
completion of a conversion, whereas the interrupt-mode
signals completion of a conversion by setting an interrupt
to the processor.
Interrupt-mode is enabled by writing a "I" to bit 'D6' in
the Status register (base address + I). The appropriate
interrupt jumper (W31-W38) must also be installed on
the board.
A conversion is initiated by writing a channel number to
the Control register (base address). The channel number
is a hexidecimal 0 through F to select o,ne of 16-channels.
During conversion,bit "D?"oftheStatus register will be a
'I '. Whe'n the conversion is completed. this bit will return
to '0' indicating that valid data is in the data registers.
Data is typically read first from the Data Low register
(base address + 2), then from the Data High register (base
address + 3). This can be done with a single "LHLD"
instruction. Writing a 'I 'to bit 'D4' of the Status register
will clear the interrupt if operating in the interrupt-mode.

MUX

CHANNEL
SELECT
LATCH

CHI6

ADDRESS
DECODE
AND
CONTROL
LOGIC

STATUS
AND
CONTROL
REGISTERS

FIGURE I. Block Diagram;

14-59

BURR-BROWN@

MP8450

1EaE51 I·

MICROCOMPUTER ANALOG INPUT SYSTEMS

l6-Channel Analog Input System Compatible with IEEE-796 (MultlbusTIII

FEATURE.S
• TRANSFORMER-ISOLATED INPUTS
• IOOOV ISOLATION INPUT TO BUS
• 700V CHANNEl-TO-CHANNEl
• INPUT FilTER
• OPEN CIRCUIT DETECTION
• RESISTOR-PROGRAMMABLE-GAIN PER CHANNEL
• MEMORY OR liD MAPPED
• REGISTER TRANSFER OF DATA
• 2O-BIT ADDRESSABLE
• BuIiNED-IN

~C~~~~~~~~:N:TR:OL.J
INK

XACK
MEM R/W
I/OR/W

LOGIC

AMPLIFIER

INT

iif

CPU

Do

Multibus'" ~ Intel Corp.

Internatlooal Airport Industrial Park - P.O. Box 11400 - Tucson. Artzona 85134 - Tel. 160ZI 146-1111 - Twx: 910-952·1111 • Cable: BBRCORP . Telex: 86-6491

14-60

THIS PAGE INTENTIONALLY LEFT BLANK

14-61

THIS PAGE INTENTIONALLY LEFT BLANK

14-62

THIS PAGE INTENTIONALLY LEFT BLANK

14-63

THIS PAGE INTENTIONALLY LEFT BLANK

THIS PAGE INTENTIONALLY LEFT BLANK

14-65

THIS PAGE INtENTIONALLY LEFT BLANK

14-66

THIS PAGE INTENTIONALLY LEFT BLANK

14-67

· THIS PAGE INTENTIONALLY LEFT BLANK

14-68.

MP8608
MP8616
MP8632

BURR-BROWN@

IElElI

MICROCOMPUTER ANALOG 1/0 SYSTEMS

FEATURES
•
•
•
•

INTEL-SBCBO and INTELLEC MoS COMPATIBLE
NATIONAL-BLCBo COMPATIBLE
LOW cost
70°C BURN-IN

• EASY TO PROGRAM
Systems are treated as memory
• REDUCES SYSTEM DEVELOPMENT TIME
System engineered and specified
Operates from computer's +5VoC
power supply if desired
• EASY TO USE
Bto 64 input channels on one board
Analog input and output on one board

Internllianal AlrporllndUllrlal Park· P.O. Box 11400· TUClon. Arizona 85734· Tel. (802) 746·1111· Twx: 910-952·1111 . Cable: B8RCORp· Telex: 66-6491

14-69

DESCRIPTION
These mictOcomputer pei'ipherals provide two functions'
that interface directly toIntel's SBC80 and Intellec MDS
microcomputers. The functions are: (I) Analog Data
Acquisition and (2) Analog Output. The devices are
electrically and mechanically compatible with.any SBC80
and IntelU:c MDS. Both analog input and output systems
are contained on a single printed circuit board that is
. treated as memory input or output by the CPU. The cards.
will mate to any memory orl/O slot. They are compatible
. with the 0.6" spaCing of the SBC80 or the O. 7S" spacing of'
the Intellec MDS. The analog interface for each system is
a connector at the opposite edge of the board from the bus
connector.
>

The Data Acquisition syst~mis available with up to 64
channels single-ended on one board. It includes an input
mUltiplexer, high gain instrumentation· amplifier, 8-bit
A/D converter along with all the necessary timing,
decoding and control logic. A DC / DC converter ("t 5 V to
±ISV) is also available so that only the computer's power
supply is required. The Data Acquisition System is
available with two optional 8-bit D/ A converters to
provide analog input and output on the same board.

, THEORY OF OPERATION
ANALOG INPUT /
OUTPUT SYSTEM
r-----------------------------------, '.M

When programming with these peripherals, they are
treated as memory locations. Any memory reference
instruction can be used. Both the A/D converter output
and the D/ A converter input are 8-bit words so one
memory location is needed for each channel. Because the
address block occupied by each peripheral is user
selectable, it can be placed anywhere in memory.

AIIAlOG

Because these units are treated as memory, a minimum of
instructions are needed to read an input channel or to set
the input of aD/ A converter. For instance, the LHLD
(load) instruction followed by the proper address can be
'used to read data from two successive analog input
channels. It will automatically select the desired channel,
initiate conversion an4,:when conversion is complete,
transfer the A/ D converter output for the first channel to
the 8080's L register 'and the second channel to the H
register. Likewise a single LDA instruction can be used to
read one analog input chann!:l.
All of these systems are jumpered at the factory with the
first channel at address F70016. Each subsequ~nt channel
is one memory location past the start of the last channel
so that the second channel is at location F70b6.

14-70

SPECIFICATIONS
All specifications typical at 25"C unless otherwise noted. i

OPERATING INSTRUCTIONS
PROGRAMMING

ANALOG INPUT/OUTPUT S,YSTEM
ANALOG INPUT
Number of analog inputs
8 differential
16 single-ended
32 differel}tial or 64 smgle-ended

Programming of this analog I/O board is easily
accomplished since all channels are treated as memory
locations. Any memory refer;nce instruction can be used.
A single ST A instruction may be used to load the
accumulator contents to one of the D / A converters.
Likewise a single LDA instruction can be used to read an
analog input channel.
Single instructions can also be used to set the inputs of
both D / A converters and read two adjacent analog input
channels. An SHLD instruction referenced to DAC I will
load the contents of the L register into DAC I and the
contents of the H register into DAC 2. An LHLD
instruction will read the channel addressed and the next
higher channel. The channel addressed will be transferred
to the L register and the next higher channel to the H
register. Of course, any MOV instruction may also be
used if direct addressing is not desired.

MP8608·
MP8616
MP8632

(~I

Input voltage range(l)
ADC gain ranges(l)
(strap selectable)
Amplifier gain rangel II
(resistor programmable)
Am'plilier gain" equation
Input overvoltage protection
Input iml"edance

±IOmV to ±5V
±IOV.O to IOV. 0 to 5V
±5V. ±2.5V
Ito IOOOV/V
G

= 100kll/ R,,,
±ISV
100 megohms

Bias current
25"C (max)
0"(- to 70"C

+.100nA
-2nA "c

Amplifier inp,ut ~ffset voltage

±2mV
±15+~)

Amplifier input offset voltage drift

#V"C

G

ANALOG INPUT TRANSFER CHARACTERISTICS
Resolution
Throughput accuracy ±5V range (max)
±IOmV range
Temperature coefficient of acc;uracy

±5V range

The normal operation of this board halts the CPU during
the conversion time of the analog input system. This is
because the software in this mode is simpler than in any
other (i.e., only one instruction required!). If the halt
feature is not desirable, it may be disabled.

,

8 bit binary
±O.4('( FSR ':'
±O.51!; FSR

(~ax)

±D.02e, FSR "C
±O.07r;·( FSR "C
44 microseconds
84 microsr.conds
66 dB (Gain = 2)
86 dB (Gain = 100)

±IOmV range
Con'version time ±5V range
±IOmVrange
CMRR (for differential inputs)'"

ANALOG OUTPUT
Number of analog outputs
Output .. ultage rangcl41

2
±IOV. 0 to IOV, ±5V. 0 to 5V, ±2.5V
at SmA (strap selectable)
III
< 5 microseconds

Output impedance
Output settling time (max)

The voltage data for these boards is represented by an 8bit two's complement binary number. With a ±5V range,
each bit has a value of 39.1 m V, with the polarity of the
voltage indicated by the sign of the binary number.

ANALOG OUTPUT TRANSFER CHARACTERISTICS
I

Resolution
Throughput accuracy (max)
Temperature coefficient of accuracy
Unipolar
Bipolar

8 bits binary
±0.4% FSR
±0.005% FSR!"C
±0.01% FSR/"C

Each board is set at the factory for a block of addresses
beginning at F700. Any analog data channel requires one
memory location. Thus the first analog channel is located
at F700 while the second anaI'og channel is located at
F701.

DIG/TAL INPUT/OUTPUT
All signals are compatible with
Microcomputer Bus
Output coding

Bipolar, two's complement;
Unipolar. straight binary
ADRO/ through ADR5,
ADRO/
DATO/ through DAT 7/

An analog. input channel is selected by:
An analog output channel is selected by:
The input/ output data bits are read through:

MECHANICAL CHARACTERISTICS

POWER REQUIREMENTS
M P8608. M P8616. M P8632.
With analog output
MP8608-AO. MP8616-AO. MP8632-AO

+5VDC ±5% at I amp, 25m V r.ipple
+5VDC ±5% at 2 amD .. 25mV ripple

TEMPERATURE RANGE
O"C to 70"C
(I) Connected at the factory for ±5V range (ADC range

For op,eration without halting the CPU, the conversion
should be started by using a single ~hannel memor)(
reference instruction (LDA or MOV). Then the CPU
should execute a routine which will take longer than the
conversion time (44 to 84 microseconds). When the CPU
now uses an LDA or MOV referenced to the same
memory location, the converted data will be transferred
to the CPU.

Compatible with Intellec MDS and SBC-604/614 card
spacing.
Minimum card spacing: 12.7mm (0.5'').
Microcomputer bus connector required: 86 pin PC edge
connector with 0.156" contact centers.
50 pin analog edge connector on board.

= ±IOV. Gain = 2).

Mating connector available from Burr-Brown:
2250MC (Viking #0 3VH25/ IJN5, solder tab);
from 3M: 3415-0001 (Scotchflex).

(2) FSR is Full Scale Range (i.e .. IOV for ±5V range).
(3) DC to 6OH1. with I kU source unbalance.
(4) Connected at the factory for ±IOV range.

(5) Connected at the factory as 32 differential.

14-71

BURR-BROWN®

MPV901
MPV901A
MPV901P

IElElI

MICROCOMPUTER ANALOG I/O SYSTEMS
32-CHANNEL ANALOG INPUT, 2-CHANNEL OUTPUT SYSTEMS
WITH VMEbus COMPATIBILITY

FEATURES
• HIGH AND lOW lEVEL INPUTS I±IOV 10 ±IOmV)
• SOFTWARE-PROGRAMMABLE-GAIN II 10 1000)
AMPLIFIER OPTION IMPV901P)
• 32 ANALOG INPUTS AND 2 OUTPUTS ON ONE BOARD
• AMPLIFIER GAIN INDIVIOUAllY PROGRAMMABLE
FOR EACH CHANNEL USING ON-BOARD RAM
• ADDRESS SELECTABLE IN WHOLE 16MBYTE
MEMORY SPACE
• 12-BIT RESOLUTION

DESCRIPTION
, The MPV901 series of analog I/O boards are electrically and mechanically compatible with, and interface directly to, the VMEbus.
The analog input section of the MPV901 includes:

an analog multiplexer suitable for 32 single-ended or
16 differential channels, resistor-programmed instrumentation amplifier (MPV901, MPV90IA) or a software-programmable ampJifier (MPV90IP, gain of I
to 1000), sample/hold amplifier and 12-bit A/D
converter. An optional analog ouput system is included on the MPV90lA and MPV90IP, consisting of
two 12-bit D/A converters and associated control
logic.
The PGA gain setting and channel selection are
dynamically-monitored and the settling time of the
PGA calculated to allow maximum data throughput
rates.
Gains of I to 1000 are software-selectable for the
PGA and the gain for each channel may be stored in
an on-board RAM if desired. The proper gain for
each channel is then selected automatically by the
MPV901.

'$'I~'16V

QV~-I5'i

Inlernatlonal Airport Induslrial Park· P.O. Box 11400 . Tucson. Arizona B5734 . Tal. 16021 746·1111 . Twx: 911).952·1111 . Cable: BBRCORP . Telex: 66·6491

14-72

SPECIFICATIONS
ELECTRICAL
Typical at +25'C and rated power supplies (as defined in VMEbus specification) unless otherwise stated.

NOTES: (1) Factory set for±10V operation. (2) Factory set for Gain =
1, (3) Adjustable to zero. (4) Includes linearity errors with gain and
offset errors adjustable to zero. (5) FSR means Full Scale Range. (6) No
missing codes guaranteed.

MECHANICAL

ANALOG INPUT SECTION
INPUT CHARACTERISTICS
Number of Channels
ADe Gain Ranges (Jumper-5electable)11I
Amplifier Gain Ranges
Resistor-Programmablel2l (MPV901,
MPV901A)
Software-Programmable (MPV901 P)
Maximum Input Voltage Without Damage

Input Impedance

Bias Current (+25"C). max
(O.. C to +70"C). max
Differential Bias Current

1 to 1000
, to 1000 (steps of 1. 10, 100. 1000)
±25V (Power Oft),
±35V (Power On)

>1(lOMCl. 5pF OFF Channel
>100MO, 50pF ON Channel
±3SnA
±60nA
±35nA

Amplifier Input Offset Voltagel:tl: MPV901P

±32OpV

MPV901, A
Amplifier Input Offset Voltage Drift

±160pV

Resistor-Programmable (MPV901,
MPV901A)
Software-Programmable (MPV901P)

±1OpW'C
±1OpVfOC

TRANSFER CHARACTERISTICS
Resolution
Throughput Time, G 1:
Resistor-Programmable (MPyeo1,
MPV901A)
Software-Programmable (MPV901 P)
Throl!ghput Time, G 1000:
Resistor-Programmable (MPV901 ,
MPV901 Al
Software-Programmable (MPV901 P)

12 bits

=

100psec, max
100psec, max

=

72Opsec, max
7201JS8C, max

ACCURACY
System Error at +25° C, maxl.llll
MPV901P: G 1, G 1000
MPV901, A: G 1, G 1000
System Linearity
A/D Converter
LInearity
Differential linearity
Quantizing Error
Gain Error
'Offset Error
Monotonicityltll

±II2LSB
±1I2LSB
±1/2LSB
Adjustable to Zero
Adjustable to Zero
Guaranteed O°C to +70°C

STABILITY OVER TEMPERATURE
System Accuracy Drift
MPV901P: G = I, G = 1000
MPV901, A: G
G 1000

50ppm, 50ppm Of FSRJoC
40ppm, 100ppm of FSR/" C

= =
= =

=" =

DYNAMIC ACCURACY
Sample/Hold Aperture Time
Aperture Time Uncertainty
Differential Amplifier CMRR, G = 1:
MPV901P
MPV901,A
Channel Crosstalk

±O.05%, ±O.075% FSR '1I1
±O.05%, ±O.4% FSR
±O.025% FSR

125nsec
±5nsec
90dS (DC to 60Hz)
BOdS (DC to 60Hz)
75dS down at 1kHz for OFF
Channel to ON Channel

ANALDG OUTPUT SECTION [MPV901A. MPV901P)
OUTPUT CHARACTERISTICS
Number of Channels
Output Voltage Ranges (Switch-Selectable)
Output Impedance (at DC)
Short Circuit Protection, Duration
TRANSFER CHARACTERISTICS
Resolution
Output Settling Time, max
ACCURACY
Output Error, max
Temperature Coefficient ~f Accuracy

2
o to +5V, 0 to +10V
±2.5V, ±5V, ±10V, at 5mA
0.05D
Indefinite to Common
12 bits

Spsec
+0.15% FSR
'!-25 ppm of FSR/o,C

POWER REQUIREMENTS
MPV901
MPV901P
MPV901A

+5V ±5% at 1.5A max
+5V ±5% at 2.0A max
+5V ±5% at 2.0A max

ENVIRONMENTAL
Operllting Temperature
Storage Temperature
Relative Humidity

Compatible with double-height VMEbus card-racking systems,
Minimum card spacing 20.34mm (O.S") [VMEbus specificationcompatible]. One 37-pin '0' type analog connector on board for
analog. inputs/outputs. Use Cannon '0' type connector part nurn·
ber DC37P/1A1N or equivalent.

32 single-endedl16 differential

o to 5V. 0 to lOV, ±2.SV, ±5V, ±10V

DoC to +70°C
-25° C to +B5° C
90% noncondensing

OPERATING INSTRUCTIONS
INSTALLATION
The MPV901 is shipped from the factory calibrated and
ready to use. Installation only requires plugging the card
into an empty slot in the VMEbus card cage and wiring
the analog connector.
PROGRAMMING
The board is programmed as 64 successive memory'locations (word locations), switch-selectable in the whole
16M byte address range. Both the AID converter output
and DI A converter inputs are l2-bit words, therefore
data word accesses are required for each channel.
A minimum of instructions are needed to read an input
channel or to set the input of a DI A converter. For
example, a read instruction, addressed to the next channel to be converted, will acquire the converted data of
the current channel and upon completion of the data
transfer, initiate a conversion at the new channel address
just selected.
'
On the MPV90lP version the on-board RAM may be
used to store a gain value for each channel. In the case
where the RAM is not used (Control Register 012 = 0),
or is not available (MPV901, A), the gain must be written to an on-boatd register (Control Registers D08 and
D09). All boards are jumpered at the factory with a base
address of FFF780H. Each subsequent channel is two
memory locations past the start of the last channel, consequently channel 0 is at location FFF780H. channell is
at location FFF782H.
The input system operates in the following modes:
Interrup't Mode. A read instruction to the board starts
the conversion. An interrupt is generated at the end of
the conversion. The interrupt can be connected to any
one of seven interrupt request lines and may also be

~~~a:~:~:ro:o:!:::~p~c~~~;.\ Register DI4 =

I enables

i

:>
Polling Mode. A read instruction to the board starts the CI..

~rsion. The interrupt is disabled either by software :IE
or by setting all switches on the interrupt request lines to
the OFF position. The CPU determines the end of conversion by reading the Status Register. (Control Register
DI4 = 0 disables interrupt for Polling Mode.) When
conversion is complete, the CPU reads the data. The
read instruction is addressed to the next channel to be

14-73

converted. The. data from the ,hist conversion is thus
transferre~ to the CPU and convers~on is start~ for the
next channel.
During the Interrupt Mode of operation, the. MPV901
supplies, the interrupt vector on data, lines 000-007
when requested by the CPU. The vector is user-definable
as illustrated in Table I. The MPV901 can also be
selected to interrupt on any oile of seven interrupt
request lines as shown in Table II. Interrupt capability
can .be c;Iisabled either by software (Control Register
014 = 0) or by hardware (no switches selected). .
.

INTEN
R;WEN

RAM EN

SHORT CYCLE
T ABLE I. Interrupt Vector Selection
SWITCH POSITION FOR
"1"
"0"
SW4psn 1 ON
SW4 psn 1 OFF
2 OFF
20N
30FF
30N
40N
4 OFF
50N
50FF
60N
6 OFF
70N
7 OFF
BON
80FF

OATALINE
000
001
002
003
004
005
D06
007

, Gl, GO

TABLE II. Interrupt Line Selection.
REOUESTINTERRUPT
ON LINE
IR01' ,
IR02'
IR03'
IR04'
IROS'
IR06'
IRO?'

- AH.irtables ihterrupt.aOdisabies
interrupt.
- A O,enables the CPU to write the
gain for, each channel to RAM. A
1 prevents the CPt) from writing
to RAM.
- AOdisables the interhal RAM and
the CPU must write a gain (Gl.
GO) into the Control Register. A I
enables the RAM to supply gains
as stored.
'
A 0 enables lO-bit conversion to
ta"e place (for increased speed and
reduced accuracy operation), A I
disables short cycle and allows full
12-bit operation.
- If the RAM is not used to store
gain information the. gain may be
written on GI and GO. The gain
remains as written until a new
value overwrites the old value.
MEMORY MAP

SWITCH SELECTED
(ONE ONLY)
SW1 psn 10.3.2 ON
9,3,1 ON
ON
8,3
7.2,1 ON
,ON
6,2
5,1
ON
ON
4

SINGLE-ENDED OPERATIO!'li
FACTORY SET
ADDRESS

READ

WRITE

FFF 780
FFF 782
FFF 784

SW4 is used to set the interrupt vector while SWI selects the
interrupt line on which the request is to be made. (Note that
switch SW I should be set t'O select interrupt capability on
ONE line only.)

FFF 'BE

FFF 7CO

FFF 7EO

STATUS REGISTER

FFF 7E2
FFF 7FE
FACTORY SET
ADDRESS
FFF 7AO

CON V COMP

INTEN
R/W EN
RAM EN
SHORT CYCLE
GI,G9

- This bit is low during conversion.
It goe's high on completion of
conversion.
- Status of inter~upt enable.
- Status of write enable.
- Status of RAM enable.
- Status of short cycle.
- Gain Control- current value of
gain stored in control register.

FFF ?BE

FFF 7CO
FFF 7EO

FFF 7E2
FFF7FF.

ADDRESS MODIFICATION

CONTROL REGISTER

The base address of a board can be seUo any value by
properly setting its address selectors. The base' address
set at the factory is FFF780 H. To change the sense of a bit
simply change the position of the switch setting for that
bit (address line A07 is factory set to a '''I'').

14-74

TABLE III. Address Switch Selection.
ADDRESS
LINE
A07
AOB
A09
Ala
All
A12
A13
A14
A1S
A16
A17
A1B
A19
A20
A21
A22
A23

FACTORY
SET
1
1
1
1
a
1
1
1
1
1
1
1
1
1
1
1
1

SWITCH POSITION FOR
"0"
"1"
MPV901A, P

SW2 psn 1 ON SW2 psn 1 OFF
20N
20FF
30N
3 OFF
40N
4 OFF
SON
S OFF
60N
60FF
70FF
70N
BON
BOFF
SW3 psn B ON SW3 psnB OFF
70N
7 OFF
60N
60FF
SON
S OFF
40N
40FF
30N
3 OFF
20N
2 OFF
ION
10FF

ANALOG OUTPUT RANGE SELECTION
Each DAC isjumpered at the factory for± IOV operation
(complementary offset binary coding). It is possible,
however, to alter jumpers on the board for other output
voltages and coding (see Table IV). When making a
change, first set all switch positions on SW6 to the OFF
position and then set to the ON position those switches
required for the desired range.
.
TABLE IV. Analog Output Range Selection.
RANGE
±10V
±SV
±2.SV
a to +SV
a to +10V

OUTO
SW6 psn 2,3 ON
1,3 ON
1,3,SON
1,4,SON
1,4 ON

OUTI
SW6 psn 7,B
6,B
6,B,10
6,9,10
6,9

ON
ON
ON
ON
ON

BASEAOD:
OUT.QADD:
OUT1ADD:
STEP'

lOOP

DATA
WORD
(X) FFF
Xl 000

RANGE
+2.SV

+S.OV

+10.0V

-2,SOOOV

-S,OOOV

-10,000V

Oto +SV a to +1'OV
O,OOOOV

I"SET FRED. AND NO. STEPS '/

MOVE W
MQVeW
Move.w
ADD I
JMP

$0000.00:
DO, OUTOAOD:
DO,OUT1ADD;
STEP,DO:
LOOP::

I'STARTING VALUE (FOR FULL SCALE) ':

BASEAOO+$60:
BASEADO+$62;

Start calibration by loading both DACs with data that
will produce the most negative ouput, which for complementary straight binary operation is FFFH. The
DACs should then be set by their offset control (R V6 for
OUT 0 and RV8 for OUT I) to the appropriate voltage
value shown in Table VI. The gain control (RV5 for OUT
o and RV7 for OUT I) is adjusted in a similar manner
after setting the DACs to their most positive output which
for straight binary is OOOH. The gain control is used to
set the DAC output to the HIGH voltage value indicated
in Table VI.
TABLE VI. DAC Calibration Values,
RANGE
±10V
±SV
±2,SV
a to +SV
a to +10V

,LOW
-10.000V
-5.000V
-2.500V
O,OOOV
O,OOOV

HIGH
' +9.9951V
+4,9976V
+2.496BV
+4.9988V
+9.9976V

1 LSB
4,BBmV
2.44mV
1.22mV
1,22mV
2.44mV

ANALOG INPUT RANGE SELECTION
Software-Programmable Amplifier (M PV90 I P)
The analog input system as shipped from the factory !:an be
software-set for input ranges of ±IOV to ±IOmV, Table
VII gives the input ranges for each gain value.
TABLE VII. Software-Programmable Amplifier Input
Ranges,
GAIN SETTING

(X) IndIcates don't care states
The following Motorola 6800Q assembly language program performs a simple dynamic check of the two
analog outputs, A ramp (sawtooth) waveform with
amplitude plus and minus full scale and frequency
approximately L25kHz will be produced at each output.
NOTE: The constant "STEP" in the program can be
altered to give different frequencies and number
of steps in the output waveform, (e,g" changing
STEP to 63H will give an output frequency of
,205kHz)

. :1

#$0031.

O,OOOOV

+2,49BBV +4,9976V +9,99SIV +4,99BBV +9,9976V

.186983.

I'BOARD BASE ADDRESS '/
rDACO ADDRESS'/
I"DAC1 ADDRESS'!

The analog outputs can be calibrated as follOWS, Install
the board in a VMEbus racking system and allow it to
reach thermal equilibrium (about 15 minutes under
power) before starting the procedure.

ANALOG OUTPUT CHECKOUT

TABLE V. DAC Full Scale Values.

@$FFF7BO;

ANALOG OUTPUT CALIBRATION

NOTE: The analog outputs default, on power-up, to the
most positive value in the selected range.

It is simple to perform static checks of the two anairg
outputs by loading the D A locations with an output data
word. The base addresses of the analog outputs are
factory set to values of FFF7EOH and FFF7E2H. The
ideal values for plus and minus full scale are shown in
Table V.

DYNAMIC CAe CHECK.

Eau
Eau
EOU
EOU

00
01
10
11

AMPLIFIER
GAIN
1
10
100
1000

INPUT RANGE"

LSBVALUE

±10V
±1V
±100mV
±10mV

4.88mV
0,488mV
48.8pV
4.88pV

*Assumes A! D converter range of±IOV.
Resistor-Programmable Amplifier (M PV90 I.M PV90 I A)
The analog input system can be set for any range between
±IOV and ±lOmV. It is set for ±IOV (complementary offset
binary coding) at the factory.
There are two gain-determining elements in this system-the AID converter and the instrumentation amplifier. The

14-75

is
en
::alE

A/D converter is factory-set for·a ±IOV 'range and the
amplifierfor a gain of I. The A/ D converter can be set for
other ranges by, simply changing the jumper links as shown
in Table VIII (before adding new jumpers, remove those
indicated for the present r~nge).
TABLE VIII. A/ D Converter Range-Setting Jumpers.
RANGE
INSERT J,UMPERS
±10V
J7, J9
;;!5V
J6, J9
:12.5
J6, J8, J9
Oto+5V
J6, J8, J10
Oto +10V
J6 J10

±IOV or 0 to +1()V ranges: with the amplifier j1roviding
all the system gain.
'
Single-Ended/ Differential Operation
All boards are'connected at the factory for 32' Channels
single-endedoperation but can be converted to 16
channels differential operation by simply changing a few
board jumperS/switches. Table XI indicates those jumpers/switchesthat must be present for a given mode of
operation.
TABLE Xl Channel Conversion
JUMPER/SWITCH SETTJNGS REQUIRED FOR
SINGLE-ENDED
DIFFERENTIAL
32 channels
16 channels
SW5 psn 2 ON, psn 1 OFF
SW5 psn 1 ON, psn 2 OFF
J1, J3 IN; J2 OUT
'
J2 IN; J1. J3, OUT

MPV901 is factory-set for complementary offset binary
coding with switch SWS positiol) 4 ON and position 3 OFF.
For operation in the complementary two's complement
mode, switch SWS position 3 is ON and position 4 is OFF.
Table IX shows the output codes for the analog input
section.
TABLE IX. Output Codes for Analog Input Section.
COMPLEMENTARY TWO'S COMPLEMENT
(XXXX)' 011111111111
(X) 7FFH Negative Full Scale
(XXXX)" 111111111111
(X) FFFH Midscale
,
iXXXX)" 1000 0000 0000
(XI,800H Positive Full Scale
"Four MSB's are unused and set to 1111
COMPLEMENTARY STRAIGHT BINARY
(XXXX)"111111111111
(X) FFFH Negative Full Scale
(XXXX)" 011111111111
(X) 7FFH Midscale
(X) OOOH Positive Full Scale
jXXXXl" 0000 0000 0000
"Four MSB's are unused and set to 1111

I

I

I

I

ANALOG INPUT LOW LEVEL OPERATION
Resistor-Programmable Amplifier (MPV90I, MPV90IA)
Bi!)ding posts for the external gain setting resistor are
provided in order that the instrumentation amplifier can be
user set for gains up to 1000. Use the following formula to
calculate the value of the resistor, Rg.

In noisy environments the differential mode of operation is
recommended for use with low level analog signals which
are more prone to common-mode noise interference.
ANALOG INPUT CALIBRATION
If the input range of the resistor-programmable amplifier is
to be changed, use the following procedure to adjust gain
and offset. The gain and offset errors ofthe M PV90 I may be
optimized for anyone range by calibrating the unit on that
range. The board is factory-calibrated on the ±IOV range.

Calibration is performed by connecting a voltage source
capable of 0.002% accuracy to any input channel (this could
also be a DC voltage source ofless absolute accuracy whose
output is monitored by a DVM capable of 0.002% accuracy). Offset and gain adjustments are made while
applying the voltages listed in Table XII.
TABLE XII. Analog Input Calibration Values.
RANGE
o to +5V
o to +10V
±5V
±10V

. Gain = I + (40jRg)
where Rg is the gain setting resistor, (value in kO).
A stable resistor (with temperature coefficient of resistance 5ppmjOC or better) should be used in this application. As shipped from the factory, gain is set to I.
Settling time of the amplifier increases as gain increases. A
delay of 50l"sec is set at the factory to allow for multiplexer
and amplifier settling times. This delay time is sufficient for
amplifier gains up to 50. For gains larger than SO a longer
delay time is required. The appropriate delay for a selected
, value of gain can be set by inserting the jumper links at
position IC4-3 as shown in Table X.
TABLE X. Amplifier Settling Time Jumpers.
GAIN
RANGE
1-10
11-100
101-1000

SETTLING TIME
REQUIRED
451'sec max
70l'sec max
650l'sec max

CONNECT PINS
ON IC43
Pin 6-7
Pins 2-3, 6e7, 14-15
Pins 2-3, 6-7,
10-11,,14-15

OFFSET
+0.610mV
+1.221mV
-4.9988V
-9.9976V

GAIN
+4.9982 V
+9.9963 V
+4.9963 V
+9.9972 V

For other ranges, offset voltage adjustment is made at
the most negative value of the range, plus 1/2LSB. An
LSB is equal to the full-scale range divided by 4096 (for
12-bit resolution). Gain adjustment is made at the most
positive value of the range less 3j2LSB. Thus for a range
of ±50mV, ILSB is IOOmV/4096 = 24.4JlV. The offset
adjustment is ma10Mn
>10MO
dependent upon
amplifier
configuration
±3OnA
±3OnA
±eOnA

30iN

O.4jNrc
12 bits

3iISeC
2.2p8ec
2p8ec

±O.~FSR''''
±O.~FSR
±O.~FSR
±O.~
±O.~

±O.025'111
Adjultable 10 zero
Adjuatablelo zero
Guaranteed OOC 10

+7O"C
STABILITY OVIR TlllPUATURE
Syatam AcCuracy Drill
·MPV850S
MPV9500
DYNAMIC ACCURACY
Sample/Hold Aperture Time. max
Aperture Time Uncertslnty
Channel Croaaf'alk

±5Oppm of FSRrc
±55ppm of FSRrc

An

20naec
±100paec
75dB down ai 1kHz
for OFF channel
to ON channel

POWER REQUIRIIIIINT8
MPV950S
MPV9500'

..

+5V ~ at 2.DA max
+5V ~ at 2.DA max

ENVIRONMENTAL
Operating Temperature
Storage Tempereture
Relative Humidity

PROGRAMMING
The board is programmed as 64 successive memory locations (word locations), switch-selectable in the whole
16M byte address range. The AID converter output is a
12-bit word, therefore a data word access is required to
read the converted data for each channel.
A minimum of instructions are needed to read an input
channel. For example, a read instruction addressed to
the next channel to. be converted will acquire the converted data of the current channel, and upon completion
of the data transfer, initiate a conversion at the new
channel address just selected (if CPU triggering is selected) or await an external trigger input before conversion
at the new address (if external triggering is selected).
All boards are jumpered at the factory with a base
address of FFF780H. Each subsequent channel is two
memory locations past the start of the last channel; consequently channel 0 is at location FFF780H, channell is
at location FFF782H.
The input system operates in the following modes:
Interrupt Mode-A read instruction or an external
trigger to the board starts a conversion.
interrupt is
generated at the end of the conversion. The interrupt can
be ·connected to anyone of seven interrupt request lines
but may be disabled l?y software (Control Register
009=1 enables the board for Interrupt Mode).
Polling Mode-A read instruction or an external trigger
to the board starts the conversion. The interrupt is disabled either by software or by setting all switches on the
interrupt request lines to the OFF position. The CPU
determines the end of conversion by reading the Status
Register (Control Register D09=:=O disables the interrupt
for Polling Mode). When conversion is complete, the
CPU reads the data. The read instruction is addressed to ~
the next channel to be converted. The data from the last ~
conversion is thus transferred to the CPU and either a...
conversion is started for the next channel (CPU trigger
selected), or an external trigger is awaited (external
trigger selected).
During the Interrupt Mode of operation, the MPV950
supplies the interrupt vector on data lines 000-007
when requested by the CPU. The vector is user-definable
as listed in Table I. The MPV950 can alsQ be selected to

OOC 10 +8O"C
-25OC to +86OC
IlO'IIo noncondenalng

NOTES: (1) Factory eat for 0 to HOV operation. (2) Factory eat for
singie-andad mode and ,Gain = 1. (3) IncJud_linearity errore with gain
and oftaet errore edjuatable to zero. (4) FSR means Full Scale Range.
(5) No mlaalng codea guaranteed.

==

14-85

interrupt on anyone of Seven interrupt request lines ,as
shown in TableIL Interrupt,capability can ,be disal,led
either by 'software' (Control Register D09=O) or by
hardW{lre (l).o'switches selected).
TABLE -I.-, Interrupt Vector Selection
,

Switch Position For

,

Data Line

"0"

DOO

SW4psn ION,
20N
30N
40N
SON
6 ON,
70N
80N

001
002
003
D04
005
D06
007

"1"
SW4psn 1 OFF
20FF
30FF
40FF
SOFF
60FF
70FF
80FF

TABLE II. Interrupt Line Selection
Request Interrupt On Line

Switch Combination (one only)

IR01'
IR02'
IR03'
IR04"
IROS'
IR06'
IR07"

SW1 psn 10.3,2 ON
9,3,10N
,8,3 ON
7,2,10N
6,2 ON
5.1 ON
ON
4

CONTROl; ii1EGISTER
015
N/A,

Read
011

012

N/A

N/A

, N/A

,

'

,',:':.':"

011

010

,009

WA

N/A

Int
Er

.

DoS,
Ext
'Trig

ADDRESS MODIFICATION
The,base address of a board can be set to any,value by
properly setting its address selectors. The base address
set at the factory is FFF780H. To chal1ge the sense of a
bit simply change the position of the switch setting for
that bit', (address line A07 is factory-set to a "I'')--'-:see
Table III.
'

TABLE III. Address Switch Selection.
Address

Line
A07
A08
A09
Al0
A11
A12
A13
A14
A15
A16
A17
AlB
A19
A20
A21
A22
A23

MEMORY MAP

015

013

hit En -A I enables interrupt, a 0 disablc:s,interrupt.
Ext Trig-A 0 enables external triggering, a I dis'
ables external'triggering.

SW4 is used to set the interrupt vector while SWI selects
the interrupt line on which the request is to be made
(Note that switch SWI should beset to select interrupt
capability on ONE line only).

Factory-Set
AddresS

"

014

Write

Factory
Set

1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
l'

'1

Switch:Position Fer

SW2psn 1 ON
,20N
301',1
40N
50N
60N
70N
80N
SW3psn 80N
70N
60N
SON
40N
30N
20N
10N

;~.

"1"

"0"

SW2 psn 1 OFF
20FF
30FF
40FF
5 OFF'
' '60FF
70FF
80FF
SW3psn 80FF
..
' 70FF
'IrOFF
' 50FF
40FF
,,30FF
2 OFF' ;
1 OFF

FFF780
FFF782,

ANALOG INPUT RANGESELECTl()N, "
MPVg50S
The analog input system can be set for either ±5¥or 0 to
+IOV full scale. It is setforHO to +IOV at the., factory
(complementary straight binary coding). To set the inputs
for the ±5Y range, select the jumper links as'shown in
Table IV (before adding new jumpers, remove those
indicated for the present range).
TABLE IV. Input Range Setting Jumpers.

FFF784

FFF79E
FFF7CO,
FFF7FE
"Channels 4 to 7 and 12 to 15 have amplifiers in
MPV9500 version,'
,

S,ATUS REGISTER
015

' 014

(013

OVer'
Samp

Over
Samp

Over
Samp

012
Over
Samp

011
"N/A

010

009'

008

Cony
Comp

Int
En

Ext
Trig

Over Samp, -These bits are. normally high. They go
low when the exte;rnal (or internal)
trigger rate, ex~s, the maximum permissible, rate.
Conv Comp -This bit is low during conversion. It
goes, high ,UpO!l, completion of conversio.~.,

Int En
Ext Trig

-Status offnterrupt enable.
-Status of external trigger enable.

Range

Insert Jumpers

Oto+l0V
±5Y

J6,
J7 ..

The MPV950S1s factorycset for complementary straight
, binary coding. Table V shows the output 'codes for the
analog il;lput se~tion.
'
. ,','
TABLE V. Output Codes for Analog Input Section.
,COMPLEMENTARY STRAIGHT BiNARY
XXXX11.1111111111
XXXX011111111111
XXXX 100000000000

Negative Full Scale
Midscale

Positive Full Scale

Four MSB's are unusad and selto 1111,

MPV950D
The analog input system can be set for any range,
between ±500mV to ±5VorOto +IV orOto +10V.1t is

14-86

set for 0 to +lOV at the factory (complementary straight
binary coding). There are two gain determining elements
in this system: the Ai D converter and the amplifier associated with a channel. The Ai D converter is factory set
for a 0 to +IOV range and the amplifiers for a gain of I.
The Ai D bonverter can be set for other ranges by simply
changing the jumper links as shown in Table IV. (Before
adding new jumpers, remove those indicated for the
present range).
The amplifiers can be set to provide any gain value in the
range I to 10 inclusive. The "uncommitted" amplifier
configuration is shown in Figure I.
C

RETURN
.

TO

r-->-'i-' 0--0--1
I

I

I

I

INPUT:

jl-<~l---4

..;.A

MUX
INPUT

>--i-:---f

I

I

L_J
'D' TYPE
CONNECTOR

FIGURE I. "Uncommitted" Amplifier Configuration.
TABLE VI. Circuit Components At Each Channel.
Component
A·
B
C·

o·
E

CH7

CH6

CH5

CH4

J9
R33
R34
R35
R36

Jl0
R37
R38
R39
R40

Jll
R41
R42
R43
R44

J12
R45
R46
R47
R48

CH15
J13
R49
R50
R51
R52·

CH14

CH13

CH12

J14
R5S
R54
R55
R58

J15
R57
R58
R59
R60

J16
R61
R62
R63
R64

-Factocy-fitted link for single-ended. input and gain = 1. For other
amplifier information, see data sheet on ttie OPA27 amplifier (POS-486).

The above arrangement allows the amplifiers to be user
connected in many of the standard operational amplifier
configurations.
ANALOG INPUT CALIBRATION
If the input range of the Ai D converter is to be changed,
the following procedure can 'be used to adjust gain arid
offset errors. (MPV9SO series boards are factory-calibrated on the 0 to +10V range).
Calibration is performed by connecting a voltage source
capable of 0.002% accuracy to Channel O. (This could
also be a DC voltage source of less absolute accuracy
whose output is monitored by a DVM capable of 0.002%
accuracy). Offset and gain adjustments are made while
applying the input voltages listed in Table VII.

TABLE VII. Analog Input Calibration Values.
Range

Offset Adjust

Gain Adjust

Oto+l0V
±5V.

1.221mV
-4.9988V

+9.9963V
+4.9963V

2. a. For 0 to +IOV range: Adjust the on-board offset
potentiometer (R V2) until the output code reads
FFFEH.
b. Adjust the offset potentiometer until the position
. where the output code makes the transition from
FFFEH to FFFFH.
3. a. For ±5V range: Adjust the on-board offset potentiometer (RV2) until the output code reads F7FFH.
b. Adjust the offset potentiometer until the position
where the output code makes the transition from
F7FFH to F8ooH.
To perform the gain adjustment, perform the following
procedure:
I. Set input voltage to appropriate value.
2. Adjust the on-board gain potentiometer (RVI) until
the output code reads FOOIH.
3. Adjust the gain potentiometer until the position where
the output code makes the transition from FooIH to
FOOOH.
Calibration is now complete.
FREQUENCY RESPONSE
The ability of the MPV950 series to respond to an input
signal of a given frequency is determined by the rate at
which the system can acquire and convert signals and by
the frequency response of the input amplifiers (MPV950D):
For 12-bit operation using all 16 channels simultaneously, maximum recommended input frequency is 10kHz.
Care should be taken to ensure that the input signal does
not contain frequencies of a significant amplitude beyond
this value.
For lO-bit resolution and 16-channel operlltion, the maximum recommended input frequency is 15kHz.
For 8-bit resolution and 16-channel operation, the maximum recommended iriput frequency is 16kHz.
If the number of channels used at anyone time is
reduced, then the input signal frequency can be increased
accordingly. For example, for 12-bit operation but using
only 8 channels, the maximum input frequency can be
.
increased to 20kHz.
The input signal frequency and number of channels (for
12-bit operation) are related as shown below.
Max input signal frequency (kHz) = Ain
where A = 160 for 12-bit operation
= 240 for lO-bit operation
= 256 for 8-bit operation
n = number of channels in use
~
An external trigger input is provided. Details of the §:
trigger signal are shown in Figure 2. A TTL compatible
input signal can be used to trigger the board.
The maximum trigger signal repetition rate must not
exceed the rate at which an input can be acquired and
converted. For 12-bit operation, the maximum trigger
frequency is typically 320kHz (not including CPU laten<,:y time); for JO-bit operation it is typically 480kHz,
and for 8-bit operation it is typically 512kHz.

IE

Before making the adjustments, allow the MPV950 to
reach thermal equilibrium (about 20 minutes under
power). The offset adjustment is made first by using the
offset calibration voltage and the following procedure:
1. Set calibratio!l voltage to appropriate value.

14-87

L

.,

'

Iw

OPEIilATION SUMMARY

"

~

I

V.

\ Vl/L
Y.

Ma.

Min

O.5V
+25V

-10.OV
+3.5V
Oneac

NlA

100nMC

t."

OV'o

V.r

~

t.

on...

FIGURE 2. External Trigger Signal.
Should the trigger frequency eKceed the maximum permissible rate, the fro!!t panel LED wili illuminate. If this
occurs, the trigger fre~uency should be reduqed until the
LED is e,xtiriguis!ted., Exceeding the maxirnum trigger
ratc will also cause data bits DIS, D14, .DB, Dl2 (which
are normaiIy at a high level), to be driven to low level,
thus indicating the, oversampling condition to the CPU.

a

SHORT CYCLE
If less than 12 bit! of resolution is required, the cycle time
of the AI D converter can be shortened to give the equivalent of a lO-bit converter with 670nsec conversion time
or an 8-bit converter with 500ilsec conversion time.
The procedure for obtaining short cycle performance is
as follows:
I. Connect~ frequency counter or oSCilloscope probe to
test point TP6.
2: Remove jUmpers Jl and J5.
3. Insert jumpers J8, J4, and J3 for lO-bit operation or
insert jumpers J8, J4, andJ2 for 8-bit operation.
4. Adjust potentiometer R V3 until the pulse width at
test point TP6· is 670nsec for IO-bit resolution or
500nsec for8-bit resolution (see Figure 3).
5. Insert jumper 11.
'

All boards are shipped from the factory ready for immediate use, however they do have a number of userselectable 6ptions. These options, which have already
been described, are sU,mmarized below.
• I. Programming Mode
Units are factory set to the non-interrupt mode and
default, on power-up, to the polling mode. Selection of
the interrupt mode and, interrupt vector is made as out4
lined earlier. T;lble I describes the selection of one of
seven, interrupt vectors.
2. Addressl Address Modifier
The units are factory~set for a base address oc'FFF780H
and to respond to short 110 addressing with no address
modifier decoding. Table III describes the jumpers which
allow the, user to configure'the units for any address.
Address modifier code response can be altered by programining the PROM to suit user requirements (consult
factory for details). Addressl Address Modifier decoding
options are shown in Table VIII.
TABLE VUI. Address and Address Modifier Decoding
, Options'.
J21

J20
itlnsert
Insert
Rem~ve

Insert

Remove
Remove

AM COdes

Address becoding

N/A
N/A
30.39

A01-A2~

A01-A15
A01-A23

'Factory-set option.

3. An~og Input Range
Two input systems are available with ·the units-16
unconditioned inputs (MPV950S), and 8 unconditioned
plus 8 conditioned inputs (MPV950D). in both cases the
AI D converter may be set to one' of two ranges. The
.
amplifiers may be user-set as defined earlier.
4. Triggering
The unit defaults on power-up to the external triggering
mode. Selection of internal triggering is liS defined earlier (see Control Register).

FIGURE 3. Waveform at TP6.

14-88

P3(A)

7
RR

6
.8R

5
RR

4
RR

RR
43 41
R R

RR
47 45
R R

mJJ9MJJIolm~m
RR
RR
35 33
39 37
R R . R iI

~nil~~fOOruF4~m
RR
63 61

RR
69 57

RR
55 53

15

14

13

I J21

RR
51 49
1.2

JJJ

RV3

~

MPV950D
USER·PROGRAMMABLE
AMPLIFfER
CHANNELS

IJ8

D
SW4

IJ20

23154

OCO

1111 !
RVI

IJ7
IJB

SWI

RV2

PI

P2

FIGURE 4. MPV950 Series Switch and Jumper Positions.

ORDERING INFORMATION

CONNECTOR PINOUT ("0" TYPE)
Pin
No:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

HI

The following options are available when ordering
MPV950 series boards.

Pin

Description
IN15
IN07
IN14
IN06
IN13
IN05
IN12
. IN04
OV (ANALOG COMMON)
IN11
IN03
iN10
IN02
IN09
IN01
INOS
INCO
TRIGGER RETURN
TRIGGER RETURN

No.

Description

20
21
22

RET15
RET07
RET14
RET06
RET13
RET05
RET12
RET04
OV (ANALOG COMMON)
RET11
RET03
RET10
RET02
RET09
RET01
RETOS
RETCO
EXTERNAL TRIGGER

23
24
25

26
27
28
29
30
31
32
33
34

35
36
37

NOTE: Unused analog inputs '!.hould be connected to OV (Analog
Common)

14-89

Description

Model

16 channels single-ended. analog input
8 channels with user-programmable amplifiers

MPV950S
MPV950D

THIS PAGE INTENTIONALLY LEFT BLANK

14-90

DATA ACQUISITION
AND
CONTROL SYSTEMS
REMOTE TERMINAL UNITS
Remote Terminal Units (RTUs) are microprocessor-based data acquisition and control packages that provide measurement signal conditioning, local control, and .intelligence for complex production processes. These products are geographically distributed throughout the
plant facility and communicate the data from many sensors to a central computer over a single cable, thus eliminating large bundles of
costly wiring.

MCS Series
The MCS Series are competitively priced data acquisition and control
systems RTU. MCS modularity allows purchase of a system configured for today's needs and assures e)(pandability later with minimum
problems and cost. This versatile system provides analog and digital
signal conditioning while maintaining accruacy over ambient temperature ranges from -10°C to +60°C. A full range of analog and digital 110
functions are available. A variety of standard packages are available
including rack mount chassis with card cage and NEMA enclosures.

15-1

Micromux II .
Low base cost makes this system ideal for low point count Supervisory
Control and Data Acquisition (SCADA) applications. Multidrop expandability allows the system to grow as' needs increase. Modern
CMOS technology dramatically reduces' power consumption while
providing a wide -40°C to +60°C operating temperature range.
Analog and digital 110 options are combined with CPU intelligence on
a single board. Each Micromu,x " board accommodates up to four 1/0
modules in any combination. 110 modules are available for high level
analog input isolation, TIC and RTD linearization, analog outputs, digitalllO, and pulse accumulation. Communications are over a serial
line. An onboard modem is optional. NEMAenclosure options protect
Micromux " from harsh environments.

15-2

PERSONAL COMPUTER
INSTRUMENTATION

INTELLIGENT INSTRUMENTATION TURNS PCs INTO LOW COST
INDUSTRIAL OR LABORATORY CONTROL CENTERS
The new PCI-3000 System from Burr-Brown lets small personal computers perform test, measurement, data acquisition, signal processing,
and control functions formerly requiring much larger and more expensive minicomputers and dedicated systems.
PCI-3000 acts as a front-end processor interfacing a variety of analog
and digital data to the PC from industrial and laboratory transducers
and signal sources. Compatible host computers include IBM PC and
XT, Apple, Compaq, DEC, and HP, plus many minicomputers and
mainframes.
Modular design and a very wide selection of analog, digital, and
special-function input/ouput (I/O) boards permit great flexibility in
configuring systems to initial requirements and expansion to accommodate system growth and diversification. Added flexibility is provided
by extensive internal firmware which accepts simple high level commands.
A basic PCI-3000'system consists of a master unit containing a power
supply, Z80A microcomputer with up to 32k of user memory and up to
three I/O boards selected for the application. As many as 192 analog or
digital I/O points are available to the user from a single master unit.
With expansion enclosures, a single master unit can provide up to 1024
I/O pOints, using 16 I/O boards. Thermocouple, frequency measurement, counting, and pulse-generating functions are also supported.

16-1

IE

A family o~ termination R,~n~lsare avajlabl~. i.n the :PCI-3000 system.
These panels provide convenient screw-terminal connections for both
signal inputs andOutplJts from't~e real wOrld: ;Two types of panel
enclosures are provided. One panel enclosure is'designed for industrial environments. Its panels contain mountin~ ,fixtures for auxiliary
p,~Sive"~Jgnalconditipning;devlces such ,as iriputJilters', dtopp.iI)g
reaistors;' protecti6" diodes, andc vpltage divlders.;:.A"~econdpanel
en(llosui:~ adapts the PCI-3000 to the unique requi~ments,ofthe
I~!>oratory. "Its panel ,features 64 ¢/'lannels ()f analog input,64digltaIIlO
. p~ints( .4ana109 outpl,l~, 7 cQunters, 2 PIJshbottqriSwitches,and 4
. optically.,coupled outputs.
,...

16-2

PCI-3000
f

INTELLIGENT INSTRUMENTATION
for Industry an~ Laboratory

CONFIGURATION GUIDE
AND
DATA BOOK

BURR-BROWN®

IElElI

~

~--------------------------------~~
16-3

TABLE OF CONT~NTS

Introduction. . • . . . . . . . . . • . . . . . . . . • . • • . . . . . • . . . . . • . . . . . . . . • . .. 16-5
CONFIGURING A PCI-3000 SySTEM ........•...........•... 16-7
PCI-3000 MASTER AND EXPANSION ENCLOSURES ........ 16-7
INPUT/OUTPUT BOARDS AND DATA SHEETS ....•.•...... 16-9
Digital Input/Output Boards, PCI-3302 ..•..............•... 16-10
Combination Boards, PCI-3301 •....•........ ; ........•.•.. 16-10
Analog Input Boards, PCI-3303 ..•.....•...•••............. 16-10
Analog Output Boards, PCI-3304 ...•..• ~ .....•......••..... 16-10
Counter/Pulser Board; PCI-3305 •• ~ .•. ; ••.................. 16-10
Thermocouple Input Board, PCI-3306 •...................... 16-10
SYSTEM FIRMWARE .........................•........•.... 16-17
TERMINATION PANELS AND HARDWARE ................. 16-19
Digital Termination Panels ...............•......•......•... 16-20
Optically-Isolated Termination Panel and Isolat~rs ............ 16~20
Analog Termination Panels .........•...•.....•..........•. 16-20
Thermocouple Termination Panels ......•................... 16-20
COMMUNICATIONS PRODUCTS •..•....•...•....•...•...•. 16-21

16-4

INTRODUCTION
The PCI-3000 is an intelligent instrumentation front end
designed to turn any personal computer into a powerful
system for data acquisition, test, measurement and control. It interfaces to personal computers such as the IBM
PC, IBM XT, DEC, HP, Compaq, Apple, and others.
Communications with these computers (or with any
other host) takes place through serial (RS-232 or RS422) channels, or' optionally, via IEEE-488.
The PCI-3000 is a very flexible system that offers extensive expansion capabilities. The basic or master unit is
housed in a rugged, yet attractive, compact enclosure
designed for either rack mounting or for tabletop integration with a personal computer. The master enclosure
contains power supplies and a single-board microcomputer. Additionally, up to three I/O boards may be
added within the master enclosure. This type of modular
construction provides great flexibility in configuring a
system. A very basic system could consist of the master
enclosure (power supply and lI}icrocomputer) with only
one I/O board added inside.
System capability can be expanded in the following two
directions as shown in Figure I:
I. A variety of 1/ 0 boards may be added along the PC 13000 Interface Bus under master system control.
Expansion-enclosure boxes are available to house
four additional 1/0 boards each. By using mUltiple
expansion chassis, systems of up to 16 1/0 boards
and over 1000 points may be controlled from a single
master unit. The PCI-3000 Bus is designed to allow
reliable communications between the expansion enclosures and the master enclosure at distanCes up to 10
meters (approximately 30 feet).
2. Up to 31 master systems may be networked together
along a multidrop communications bus from a single
host using RS-422, or IEEE-488 protocols. For applications where sensors or output devices are widely
distributed, RS-422 communications can be used for
direct wire connections over distances up to 1200
meters (approximately 4000 feet). For longer distances, modems may be used to communicate over
various communications links.
The flexibility of the PCI-3000 System is a result of the
internal firmware operating system. Stored in EPROM,
the operating system is normally transparent to users
who rely on the standard command functions. However,
the operating system can be modified by those who want
to create their own command functions or stand-alone
programs for individualized applications. The choice to
use these featu~es is up to each user, but is facilitated by
these internal PCI-3000 utilities:
Task scheduler
Allows regular or timed execution of user tasks
Drivers
Buffered access to all communications ports
Access to all inputloutput boards
Clock handling

Debug
Through the on-line debugger
System Library Routines for
Code conversions
Buffer handling
Number system conversion
Thermocouple linearization

The unique PCI-3000 firmware allows the user to access
the system without modification or to tailor it to meet
special needs. PCI-3000 systems can be programmed as
complete data acquisition and control systems. Terminals and printers can be connected to meet individual
system needs. User EPROM space is available so programs may be permanently added to PCI-3000 systems.
In addition to its sophisticated architecture and easy-touse software, the PCI-3000 System offers a reliable and
practical set of termination panels which provide a conTABLE I. PCI-3000 System Specifications.
(Read/write speeds correspond to 9600 baud communications.)
COmmunl""Uona
Local Multidrop
Remote

Two asynchronous serial channels, 300-9600
baud. RS-232-C signals on both chen nels.
RS-422 signals on Channel A. (2-wire. halfduplex. Up to 4000 feet.) IEEE-488
(optional), controlled by host.

Memory

8k byte. of u.er RAM Installed.
Expandable to 32k bytes, RAM or EPROM.

Tempa,8Iure
R_nge

O'C to +50'C (I/O boards and enclosures).
-25'C to +70'C (passive termination panels).

Mach_nl",,1

Master or
expansion

2.4 x 17 X 19 inches (H, W, 0)

Termination panel

rack
Lab panel
Expand_bilK,

5 X 19 X 2.5 inches (H. W, 0)
15.8 X 19 X 2.5 inches (H, W, 0)
Up to 192 I/O channels per master enclosure.
Up to 1024 channels using expansio~ enclo-lUres.

Up 10 31 masters can be networked together on
an RS-422 multidrop communications line
supporting up to 31744 1/0 channels.
AMlog Inpub

Si!1gle-.ended or
Differential

±10mV to ±10V direct inputs (higher with
attenuation added to termination panel).
Convertible to current input. 0.1% full scale
accuracy. 12-blt resolution. 2000 readings/
sec (into internal memory). Up to 30 readings/sec returned to host. Programmable
gain (1 to 1000). Thermocouple inputs (J. K
or T), O.B'C repeatability.

A....ogOutput
Voltage or current

±10V or 4 to 20mA. 12-bit resolution. 0.1% full

Counte,.

Maximum input frequency: 8MHz. Accumulation. gateable. Direct frequency measurements. 16-blt resolution. 0.005% stability.

Pube Output

Programmable pulse width, period and number
of pul.... Frequency range: 61Hz to l!MHz.
125nsec resolution. 0.005% stability.

Digital

TTL compatible. 24mA current sink, 15mA cur-

Input and output

Read/set bits. bytes or words at the rate of
30/sec. High voltage isolation (4000V
OC/AC) and 3A switch capability with opto-

P_SUppl,

85VAC to 13OVAC, 50Hz to 60Hz or 200VAC to
280VAC. 50Hz to 60Hz. 8OW.

TennlnllIIon
p-

Provides screw terminal connections and pro-

scale accuracy. Write time, 2Omsec.

rent source.

Isolation panels.

16-5

visions for user-defined signal conditioning.

II
~

C3
a..

PERSONAL
COMPUTER

To other
mast~r systems
(up to 31 total)

IEEE-488/RS-232-C/RS-422

MASTER SYSTEM
ENCLOSURE #1

MASTER SYSTEM
ENCLOSURE #n
(n ~31)

Termination Panels
as needed

Termination Panels
as needed

II>

:::l

III
CD

u

~
$

.!:

~.

U
11.

EXPANSION
ENCLOSURE #1

Termination. Panels
as needed

To Expansion Enclosures
as needed (maximum bus load
is 16 boards and/or
256 addresses)

A basic system consists of one master enclosure. plus one
one I/O board. System capability can be·expanded in two
directions;
·1) multiple I/O boards on the PC!-3000.1nterface Bus.
controlled by a master enclosure. and
2) by networking multiple master enclosures together
using a choice of RS-422. or IEEE-488 standard
communication buses.

To Expansion Enclosures
as needed (maximum. bus load
is 16 boards and/or
256 addresses) ,

System may be expanded both vertically and horizontally.

, FIGURE I. PCI-3000 System EXI'ansion Capability.

16-6

venient means of connecting to sensors or to output
devices. Two different termination panel enclosures are
offered to provide an inexpensive and convenient method
for housing the termination panels and the wiring leading from the real world into the system:
I. An industrial termination panel enclosure can house
one of a number of different termination-panel
options. Termination panels provide a neat, accessible method to interface between field wiring .and
cables leading to master or expansion enclosures.
Each of the optional termination panels is designed
for optimum interfacing with specific types of input/
output devices (digital I/O, analog I/O, thermocouples, etc.)
2. A laboratory termination panel enclosure accepts 64
channels of analog input, 64 digital I/O points, four
analog outputs, seven counters, two push-button
switches, and provides four optically-coupled inputs.
Both ±ISV and +SV are brought to its panel along
with a variable voltage source (±IO V).
Table I ~ives the PCI-3000 system specifications.

CONFIGURING A
PCI-3000 SYSTEM
This section is an aid in configuring a system for a specific application. More detailed information about each
specific product area appears in later sections of this
brochure.
Starting with the Master System Enclosure with its
power supply and microcomputer, there are three additional elements to consider in configuring a PCI-3000
System:
-the input/ output boards for a specific application
-the termination panels for the I/O boards
-the; Expansion Enclosures, if required.
The first step in configuring a system is to select the
appropriate input/ output boards and termination panels
to meet the requirements of a given application. The
function of a termination panel is to connect the application signals to the input/ output boards. The function of
an input/ output board is to provide the necessary interfacing circuitry to convert real-world signals tq a compatible digital format for signal processing.
The termination panel family includes a wide variety of
analog, digital, combination analog/ digital, thermocouple, laboratory, and' optically-isolated terminations.
If desired, the termination panels can be housed in ·a
Burr-Brown Termination Panel Enclosure, or in other
enclosures such as NEMA boxes for harsh-environment
operation.
Input/ output boards include digital input/ outputs, analog input/ outputs, thermocouple inputs, pulse inputs/
outputs, as well as combination units.
After selecting the appropriate input/ output boards and
termination panels, the Master System Enclosure and
Expansion Enclosures can be selected. Three input/
output boards fit in one Master Enclosure. Each expan-

sion enclosure can hold four input/ oufput boards. Master Systems are listed under the PCI-3000 Series. Expansion Enclosures are needed only if more than three
input/ output boards are required in your a~plication.
Figure 2 is a convenient diagram to aid in selecting the
various I/O boards and termination panels in order to
configure a system for any given application. Figure 2
carries the information in Figure I to the next lower
level, showing which I/O boards will properly interface
with termination panels in order to bring signals to and
from the real world.

PCI-3000 MASTER AND
EXPANSION ENCLOSURES
PCI-3000 Systems are housed in one or more slim-line
enclosures that are equally attractive in either tabletop
or rack-mounted applications. Each such enclosure
houses power supplies and up to four printed-circuit
boards. The heart of the PCI-3000 system, a singleboard Z80A-based microcomputer, resides in'the master
enclosure along with as many as three I/O boards.
Expansion enclosures accommodate ·up to four I/O
boards. A system of up to 1024 points can be configured
with one master enclosure and four expansion enclosures. Systems of up to 31,744 points can be constructed
by networking 31 masters together on the RS-422 port.
MuIti~enclosure systems may be configured by stacking
enclosures on top of one another, or by rack mounting
the enclosures, using optional slides.
Interconnections between I/O boards and between enclosures are achieved via mass-terminated ribbon cables.
Since each expansion enclosure contains its own power
supplies, power requirements are automatically met as
the system is expanded. Input/ output cables exit the rear
of the enclosure through a strain-relief slot and plug into
screw terminal panels that may also be tabletop or rack
mounted in termination panel enclosures.
The unique design of the enclosures allows cooling to
occur by a combination of radiation from its metal skin
and convection through vent holes. The power supply
pod is separated from the printed-circuit boards by a
metal thermal barrier. No fans are necessary. This fact
considerably improves overall system reliability.
For very harsh environments, PCI-3000 systems can be
mounted in NEMA enclosures that provides waterproofing and protection from dust and oil.
FEATURES AND CAPABILITIES
Some of the features and capabilities of the PCI"3000
System that reside in the Master Enclosure are summarized below.

Microprocessor
The PCI-3000 uses the Z80A microprocessor. It operates
at a 4MHz rate.
Memory
The microcomputer board is equipped with eight memory sockets which allow a full memory expansion of 64k
byt~s. The bottom bank of four sockets is dedicated to

16-7

MASTER SYSJEM ENCLOSURE,
PCI-3001-1
'Options:
PCI-3001-2
PCI-3001-1 Except 200-260VAO
PCI-3903-1
'
IEEE-488 I/O Port lor PCI-3001 leries
PCI-3905-1
Rack Mount Slide
PCI-I200 Seriel Cebles

USER-DEFINED
I/O OPTIONS
ANALOG'INPUT BOARQS
PCI-3303-2
64 Channels, Single Ended
PCI-3303-4
32 Cl1annels, Dillerential

.

J{

TERMINATION
PANELS

TERMINATION
PANEL OPTIONS

PCI_3702

PCI-3907-1

16/8 Channe,Is. Analog

PCI-3703
32/16 Channels. Analog
PCI-3705
Laboratory
PCI-3707
8 Channels. Bridge

THERMOCOUPLE INPUT BOARQ
PCI-3306-1
----,
32· Channels, Differential

Base Rack Mount
PCI-3908-1

Cover

(PCI-3704
16 Channels. Thermocouple

--FL

I
I
I
IL_--,I __ I

L ______ _

EXPANSION
ENCLOSURE

I
I

I

I

t __ I

~_~

I
I

L_~

__________ _

ANALOG OUTPUT BOIIRDS
PCI-3304-1
B Chen nels, ±10V
PCI-3304-2
,8 Chantiels, 4-20mA
PCI-3304-3
4 Channels, ±10V
PCI-3304-4
4 Channels, 4-20mA
PC 1-3304-5
2 Channels, ±10V
PCI'3304-6
2 Channels, 4-20mA

PCI-3702
16/8 Channels, Analog
PCI-3703
32/16 Ch,nnels, Analog
PCI-3705
Laboratory

PCI-3701
16 Channel., 01/00
PCI-3702
1618 Channels, Analog
PCI-3703
32/16 Channels. Analog
PCI-3705
Laboratory
PCI-3706
16 Channela, ISO
PCI-3707
8 Channels, Bridge

ANALOG INPUT AND
DIGITAL 1/0 BOARDS
PCI-3301-2
32 01100, TTL & 16 Channel., SE
PCI-3301-3
32 01100, TTL & 8 Channels Oil

=r[

PCI_3701

EXPANSION ENCLOSURE

DIGITAL 1/0 BOARD
PCI-3302-1
64 01100, TTL 24mA Sink

PCI-3909-1
OpHonl:
PCI-3909-2
PCI~3909-1 Except 200.. 260VAC
PCI-3905-1 '
Rack Mount Slide

FIGURE 2,

PCI~3000

PUlSE"IO AND ANALOG
OUTPUT BOARDS
PCI-3305-1
4 Channel Analog Output
& 7 Counters/Pulsers
PCI-3305-2
7 Counters/Pulsers

System Component Configuration Guide,

16-8

,

16 Channels, 01,/00
PCI-3705
Laboratory
PCI-3706
16-Channelsl,SO

POI-3701
18 Channela, 01100
PCI-3702
1618 Channel., Analog
PCI-3703
32118 Channels, Analog
PCI-3705
LabOralory
PCI-3706
16 Channel. ISO

DIGITAL
ISOLATION
PCI-1101
PCI-l102
PCI-1103
PCI-1104

firmware and system RAM. This leaves the top four
sockets for RAM expansion or for user EPROM to
accommodate special commands or programs. Each
I socket may be strapped to accept either a RAM or
EPROM chip of the BYTEWIDE format. (32K bytes
maximum.)
Watchdog TImer
This circuit ensures that the microcomputer will be reinitialized in the event that the processor halts or becomes
caught in an infinite loop. A software routine "hits" the
Watchdog timer (WDT) periodically. If this routine fails
to run, the WDT times out and restarts the processor.
Switch Regl.ter
Sixteen on"board switches allow baud rate and mode
selection for serial communications channels A and B, as
well as unit identification for use in multidrop systems.
Indicators
Eight LED indicators are provided which are used as
processor status indicators for both normal operation
and during the-execution of internal diagnostics.
INPUT/OUTPUT COMMUNICATIONS PORTS
The following descriptions provide a~ overview of the
characteristics of each of the PCI-3000 input/ output
communications ports.
Channel A
Channel A is a serial, asynchronous, RS-232/422 channel for communication to a host computer or to 11 terminal. Line speeds of 300 baud to 9600 baud may be
selected. When RS-232 is selected, modem control signals are provided. RS-422 drivers and receivers are
available to provide two-wire, half-duplex communications. This technique permits reliable data transmission
at high data rates without a modem over longer distances than are possible with RS-232 (up to 4000 feet). In
addition, RS-422 supports multidrop capability of up to
31 master systems.
Channel B
Channel B provides only RS-232 communications.
PCI-3000 Bu.
This bus is designed for simple and reliable interconnection of inputj output boards. The PCI-3000 Bus is
equipped with special line-transceivers that make it possible for the bus to extend through multiple expansion
enclosures while maintaining reliable operation.
GPIB
This optional communications port is the IEEE-488
standard bus for instrument interconnection. It allows
the host computer to communicate with both the PCI3000 and to other" instruments plugged into the GPIB.
SYSTEM ENCLOSURE OPTIONS
The following options for PCI-3000 Systems relate to
the system enclosures.
PCI-3001-1 Ma.ter Enclosure
This enclosure contains the microcomputer, power supply, and cables necessary to begin using the PCI-3000
System with a personal computer equipped with an RS-

422 or with RS-232-Ccommunications port. Not included are the I/O interface boards or the termination panels required for a specific application. The PCI-3001-1
Base Unit operates on 85 to 130VAC, 50 to 60Hz.
PCI-3OO1-2 Muter Enclosure
This system has the same features as the PCI-3001-1
except that the power supply operates on 200 to 260
VAC, 50 to 60 Hz.
PC-3909-1 Expan.lon Enclo.ure
This enclosure contains power supplies, cables, and
mounting space for four I/O boards. Power supplies
operate on 85 to 130 VAC, 50 to 60 Hz.
PCI-3909-2 Expan.lon Enclo....re
Same as PCI-3909-1 except power supplies operate on
200 to 260 VAC, 50 to 60 Hz.
The following options are not necessary for the basic
operation of the PCI-3OO1 and PCI-3909 series, but they
may be purchased separately for spares, mounting, or
for expansion of basic capability of the system.
PCI-3905-1 Rack-Mount Slides
For the PCI-3OO1 and PCI-3909 Series.
PCI-3903-1 IEEE-488 Port
Converts the PCI-3001 Series to provide lEEE-488
(GPIB) communications.
PCI-3901-1 Microcomputer Board
This board is supplied as part .of a PCI-3001 Series
Enclosure. This item is a separate listing for those who
desire spares. Firmware EPROMs and RAM not" included (see below).
PCI-3901-2 Microcomputer Board
This board is the same as the PCI-3901-1, except it does
contain the latest revision of PCI-3000 System firmware
(EPROMs and RAM).
PCI-3902-1 Firmware Integrated Circuits
The latest revision of PCI-3000 System firmware.
Includes EPROMs and system RAM integrated circuits.

INPUT/OUTPUT BOARDS
AND DATA SHEETS
Interfacing to real-world signals takes place through the
various I/O boards that are available for the PCI-3000
System. Up to three ofthese I/O boards may be plugged
into a Master Enclosure (PCI-3001 Series). This allows
systems of up to 192 points to be configured in a single
enclosure. For larger systems, Expausion Enclosures
(PCI-3909 Series) may be used. Each Expansion Enclosure will accommodate up to four I/O boards, which
allows interfacing as many as 256 additional points per
expansion enclosure. See Table I for a summary of board
specifications.
A list of I/O boards with brief summary descriptions' ~
follows. More detail is given in the data sheets at the end U
of this section.
~

8

16-9

DIGITAL INPUT/OUTPUT BOARD
PCI"33Q2-1
64: digital inp.ut/ output lines, TIL-levels, 24mA sink current
COMBINATION INPUT/OUTPUT'BOARDS
PCI-33Ql-2
32 digital input/ outputs and 16 single-ended analog
inputs, 12-bit resolution

PCI-3301-3
32 digit~ input/ outputs andS differential analog inputs,
.
,
12-bit resolution
PCI-3305-1, Counter/ Pulser / Analog Output Board
7 digital registers and 4 analog outputs
ANALOG INPUT BOARDS

ANALOG OUTPUT BOARDS
PCI.3304-1, 'S-Channel AnalogV'oliage Output Board
±IOV analog outputs, 12-bit resolution.

PCI-3304-2, S-Channel Analog Current Out~utBoard
4 to 20mA, analog outputs, 12-bit resolution
PCI-3304-3, 4-channel Analog Voltage Output Board
±IOV analog outputs, 12-bit resolution
PCI-3304-4, 4-channel Analog Current Out~ut Board
4 to 2OmA, analog outputs, 12-bit resolution
PCI-3304-5, 2-Channel Analo$ Voltage Output Board
±IOV analog outputs, 12-bit resolution
PCI-3304-6, 2-Channel Analog Current Out~ut Board
4 to. lOmA, anaiog outputs, 12-bit resolution
COUNTER INPUT/PULSER OUTPUT BOARDS

PCI-3303-2
64 single-ended analog inputs, programmable gain, l2-bit
resolution
PCI-3303-4·
32 differential analog inputs, programmable gain, l2-bit
'
.
resolution

PCI-3305-1, Counter/Pulser/ Analog Output Board
7 digital registers. and 4 analog outputs
PCI~3305-2, Counter/Pulser Board
7 digital registers

THERMOCOUPLE INPUT BOARD
PCI-3306-1
32 channels for J, K, or 'f, type thermocouple inputs,
A/D conversion, ,12-bit resolution, zero-point compensation,' and linearization.

16-10

BURR-BROWN®

PCI-3301 Series

IElElI

32-POINT DIGITAL INPUT/OUTPUT,
16-CHANNEL ANALOG INPUT BOARDS
FEATURES

• 0.1% full-scale accuracy
• CMRR = 80dB at 60Hz

plGITAL I/O SYSTEM

• 32 TIL level input/ output points.
• Four 8-bit digital I/O registers each jumper configured for input or output.
• Contents of output registers may be read back.
• Input or output configuration may be read by
software.
• Output registers provide 24mA of sink current
and 15mA of source current
• Up to 30 read/ writes per sec
• Compatible with both isolated and non-isolated
termination panels
ANALOG INPUT SYSTEM

• 16 channels of single-ended input or 8 channels of
differential input.
•
•
•
•

12-bit resolution.
Up to 2000 readings per second (internal storage)
Up to 30 readings per second (returned to host)
Gain selection by installing precision resistor
(G=I to 250)

• Zin = 109 0
• Ibia. = 25nA
• Crosstalk;::: -IOOdB

DESCRIPTION
The PCI-3301 series of I/O boards provides a mixture of digital input/ output points and analog input
channels for PCI-3000 systems.
The 32 digital points may be jumper-strapped for
input or output on a byte basis. The standard signal
levels are TTL input and buffered TIL driver outputs. Input/ output cables mate directly to digital
isolation panels for handling high voltage AC or DC
discrete signals.
Two versions ofthe PCI-3301 series are offered. The
PCI-3301-2 has 16 single-ended analog inputs. The
3301-3 has 8 differential analog inputs. The input
gain may be user-selected by insertion of a precision
resistor.

lUI DRlVEII
AID IIECEJVUI

SI&llAL CABLE

__ '-..r--DII-IOARO
COllECTORS

.FIItIII AI AIALII&
mMIIATlIIII PAiEL
_Al CAlLES TO/FROM
IIItIITAL TERMIIATIOI PAIE~

52
~

L-__________________________________________________________________
~~
International Airport IndUltrlal Part· P.O. Box 11400· TUClDa. Arizona 85734· T81.1802) 746-1I11 • Twx:911J.952·11l1 . Cab!" BBRCORp· lllll: 66.fi491
U

16-11

BURR-BROWN~

IElElI

64-POINT DIGITAL I NPUT/OUTPUT BOARD
FEATURES

DESCRIPTION

• 64 TTL level input/ output points.
• Eight 8-bit digital I/O registers, each jumper configured for input or output.
• Contents of output register may be read back.
• Input or Output configuration may be. read by
software.
'

The PCI-3302-1 is an I/O board for the PCI-3000
System that provides 64 buffered TTL level digital
inputs or outputs. These bits are organized into
eight, 8-bit wide registers, each of which is jumperselectable as an input or an output byte. However,
higher voltage signals and high voltage isolation
may be obtained by iJsingexternal termination panels, such as the PCI-3706-1, along with the PCI-IIOO
Series Optoisolators.

• Output registers provide 24mA of sink current
~nd 15mA of source current.
• Compatible with PCI~3701 signal conditioning/
, screw termination panels.
• Compatible with PCJ-3706 high voltage/ high current isolated signal conditioning panels.
• Read or set bits, bytes, or words at the rate of up
to 30 per second.

REGISTERS

DRIVERS AIID
RECEIVERS

ON.8IJARD
COIIIIECTORS

SIGNAL CABLES'TO/fROM
DIGITAL TERMIIIATION PANELS
Inlernallanal Alrporllndualrlal Park· P.O. Box 11400· Tuclon. Arizona 85734· TIl. (602) 748-1111 • Twx: 911J.952·1ill • Cable: 88RCORp· T,II.: 68-6481

16-12

BURR-BROWN®

PCI-3303 'Series

I ElE:I I

64-CHANNEL ANALOG INPUT BOARD
FEATURES
• 64 Channels of single-ended input or 32 channels
of differential input.
• 12-bit resolution.
• System accuracy of 0.1% full scale.

~

• Zin = 101°n
• hia.= 10nA
• 4 programmable gains-I, 10, 100, 1000
(can be configured for other gains)
• Converter input range is ±IOV.
• May be user jumpered for ±5V or 0 to IOV.
• Can be configured for current input
• Up to 2000 readings per second into internal
memory
• Up to 30 readings per second returned to host
• Connects through cables to analog signal conditioning/ screw termination panels. These panels
provide capability for installation of signal filtering, current loop input, voltage division and
surge suppression components.

PCI·3000 BUS ''-------...

IZ·BIT
ANALOG·TO·
DIGITAL
CONVERTER

DESCRIPTION
ON·BOARD
CONNECTORS

The PCI-3303Series of I/O boards for the PCI3000 System provide up to 64 channeis of singleended or 32 channels of differential analog input.
Analog input is obtained by selecting one of the
input channels using an analog multiplexer and
. converting the voltage to a digital value with a
l2-bit, successive-approximation, analog-to-digital converter. One of four amplifier gains may be
selected for each conversion, allowing a full scale
input range of±IOmV to ±IOV.

~

SI8IIAL CAlLES FIIIIM

AIIALOII TERMIllATIIII !'AIElI

~

_____________________________________________________________________________________
InlBrnllianal Airport Industrial Parle· P.O. Box 11400· TUCIDA. ArfzlN1I85734 . T.1. (602) 746-1111 • Tw,x: 910-952·1111 • Cable: BBRCORP· Talax: 66-6491
c::;
~a.

16-13

BURR-BROWN®

PCI-3304Series

IElElI

.

,,",

..~.'

,

8-,4.., AND·2-CHANNEL
DIGITAL-TO-ANALOGCONVERTER BOARDS·

•
•
•
•

FEATURES

DESCRIPTION

12-bitdigital-to-analog converter.
0.1% full-scale accuracy.
Output write time as short as 20msec.
Two versions of output available-voltage (±I OV)
or~urrent (4mA to 20mA).

The PCI-3304 series Of digital-to-analog converter
boards provide up to eight channels of analog output for PCI-3000 Systems. Each output is directly
proportional to a corresponding value loaded· into
the 12-bit digital register on the interface bus. In
addition, the board is available in two, four and
eight channel versions.
PCI-3304-I, 8-Channel Voltage Output
PCI-3304-2, 8-Channel Current Output
PCI-3304-3, 4-Ch.annel Voltage Output
PCI-3304-4, 4-Channel Current Output
PCI-3304-5, 2-Channel Voltage Output·
PCI-3304-6, 2-Channe1 Current Output

• Voltage versions may be user-jumpered for ±5V,
o to 5V, ±2.5V or 0 to IOV.
• Both output versions available in 2, 4 or 8
chimnels.

ON·BOARO
CONNECTOR

SISNAL CABLE

t-~- fROM AUNALoa

. YERMINATION PANEL

•
•

•

•

•
•

II

•

Inl8rnallDIIII Airport Ind"trlal Park· P.O. Box 11400· TUClan. ArlzDIII85734· Tel. (602) 74&-1111 . Twx: 910-952·1111 • Cable: BBRCORP· TIIil: 1IIH491

16:..t4

BURR-BROWN®

PCI-3305 Serie$

1E3E31

COUNTER/PULSER OUTPUT
ANALOG OUTPUT
•
•
•
•
•
•

FEATURES

DESCRIPTION

Seven 16-bit counters.
8MHz input pulse rate.
2MHz pulse-generation rate.
125nsec resolution.
±0.OO5% stability.
Four of seven counters may be set up to count
events, measure frequency, output pulse streams.

The PCI-3305 series of 1/0 boards provide a
mixture of pulse or event counting, frequency
measurement, pulse output and analog output,
for PCI-3000 Systems.
All boa'rds in this series include seven 16-bit
counter blocks. Three of these counters are used
exclusively as event counters. The other four
counters may be set up. through software commands, as counters to measure frequency, or as
pulse output blocks (either finite or continuous
pulse streams).
The PCI-3305-1 board includes four digital-toanalog converters, which provide four channels
of analog output voltages.
This board requires 32 addresses. This limits a
single master system to 56 counters if entirely
configured with PCI-3305 series boards. (Note
that 32 x 8 :: 256 addresses.)

• Four 12-bit digital-to-analog converters (PCI3305-1 only).
• Counter functions are compatible with PCI-3706I high voltage 1high current isolated signal conditioning/screw termination panels.

TO
FIELD

COUNTER
CONNECTOR
TO
FIE,Lo

ANALOG
OUT
CONNECTOR

International Airport Industrial Park· P.O. Box 11400· Tuclon. Ari,zona 85734 • Tel. 16021 746-1111 • Twx: 91(1.852·1111 • Cable: BBRCoRP • Telex: 66·6491
L -____________

~~

~---------------------------------------------------------------------------------------------~D16-15

BURR-BROwN®

PCI-3306-1

I E:iEl I

.32-CHANNEL
DIRECT THERMOCOUPLE INPUT BOARD
FEATURES
• 32 channels of direct thermocouple input.
• Zero point referencing for J, K, and T types of
thermocouples.
• Gain = I and 10, noncompensated, input
available for non,thermocouple channels.
• ±O.8°C repeatability.

•
•
•
•

~

PCI·3000 BUS ' - - _.....

lb... = ±IOnA

IZ·BIT
ANALOG· TO·
DIGITAL
CONVERTER

Crosst~lk 2:: -1I0dB
CMRR = 92dB at 60Hz
12-bit analog-to-digital converter used to obtain
reading.

ZERO·POINT
REFERENCE
COMPENSATION

• Firmware can provide linearized results in degrees centigrade.

DESCRIPTION
The PCI-3306-1 is a PCI-3000 System board which
provides 32 channels of direct thermocouple inputs.
The PCI-3306-1 in conjunction with the PCl c3704-1
!ermination panel includes a solid state junction
compensation network which provides an output
that is zero point referenced. Thermocouple types J,
K, and T are supported. The PCI-3306-1 must be
used with a PCI-3704-1 screw termination panel,
which provides the screw terminals for the thermocouples as well as a terminal temperature sensor for
the compensation network. The firmware has the
capability 9f returning the values read from the PCI3306-1 directly in degrees centigrade.

O·N·BOARO
CONNECTORS

SUIL CAllES FRa
AIIALO. TERMIIATIOII PAIW

Internatlolllli Ai.rpoi1'lnduslrlal Park· P.O, Box 11400· Tucson; Arizona 85734 • Tal. (6OiJ 7~111 1 • Twx: 910-952·1111 • Cable: BBRC,ORP· Talex:6&-8491

16-i6

PCI-3000 SYSTEM FIRMWARE
Command messages are sent to the PCI-3000 from its
host computer through any of its three communications
ports. 'These commands are interpreted by decoding
programs within the PCI-3000 firmware. A decoded
function command causes one of a number (If data '
acquisition or control function programs to execute
under the operating system. Each different function
returns results to the host computer through the receiving communications port. A standard set of functions
within the firmware allows reading or' setting of all signal
1/0. For most users, all that will ever be needed are the
standard functions included in the PCI-3000 firmware.
Simply send a command string with a high level statement like PRINT from BASIC and receive a data string
back with an INPUT statement.
.
Since the internal firmware is indeed a small operating
system, a user may write his own special-purpose functions that may be down-line loaded and become extensions to the standard firmware. Special functions may
also be set up to run continually, or on a timed basis.

the BASIC language. However, the principles shown
apply equally to any programming language that you
may prefer to use.
Let's start by reading the value of a particular digital
input port on the PCI-3OO0. The following BASIC program steps would achieve that result:
10
20
30
40

OPEN "COM:96~" AS #1
PRINT #1, "SAI',I,RD BT (1',7)"
LINE INPUT #I,AS
PRINT AS

Let's look at each of these commands in detail.
10

OPEN COM AS #1

STATEMENT 10 is a typical command to open a communications channel at 9600 baud and designate it as # I.
Some operating systems include terms to define parity,
etc.
20

PRINT #1, "SAI',I,RD BT (1',7)"

STATEMENT 20 causes the message

Other features of the PCI-3OO0 firmware include:

$AI',I,RD BT (1',7) 

-On-line and off-line diagnostics for system troubleshooting.

to be sent to the PCI-3000 as an ASCII character string,
through com port #1. Let's examine each character
segment:

-A Console Emulator program which allows direct
interaction with the PCI-3000 at the machine level for
debugging user programs.

Tells the PCI-3000 that a new message is
starting.

$

-A set of internal system utilities to allow easy programming of user functions.

Tells the PCI-3000 that the message is in th~
ASCII format, with no error checking.

AI'

The following describes how to work with the PCI-3000
Operating System.
.

Defines the PCI-3000 id number, which
allows a number of PCI-3000s to be connected in a network. (This number could be
1-31).

HOW TO WORK WITH A PCI-3000

In the simplest mode of operation, there are basically
two steps in using the PCI-3000 to acquire data or generate control signals. The first step is to tell the PCI-3000
what it is you want it to do, the second is to receive the
desired data or command acknowledgement back from
the PCI-3000. The PCI-3000 accepts command messages
and returns data as a string of ASCII alpha-numeric
characters. This is very convenient, since most personal
and other computers have software that supports transmission and reception of ASCII characters through their
communications ports. Once a PCI-3OOOis plugged into
an RS-232 or RS-422 communications port on your
computer, you are ready to send commands and receive
data. GPIB (IEEE-488) is a PCI-3000communications
option.

RD

Tells the PCI-3OO0 that this function command is from the READ group of commands
(RD is the abbreviation for ReaD).

BT

Tells the PCI-3000 that only one bit is to be.
read (BT is the abbreviation for BiT).

(1',7)

Tells the PCI-3000 that the bit to be read is
bit number 7 at address number 1'. (More
about addresses later.)

 , This character, which is the same as "Carriage
Return" or "Enter", is automatically transmitted by your computer. It tells the PCI-3000
that the message has ended and it should now
execute the command it received.

Probably the easiest method of learning how to program
your personal computer to communicate with tbe PCI3000 is by looking at some specific examples. Once you
have worked through these examples, you can begin
using the other PCI-3000 function commands summarized in Table II. The following examples are written in

30

LINE INPUT /f1,AS

STATEMENT 30 captures the response from the PC 13000 by using the LINE INPUT command. The actual
response from,the PCI-3000 might be:

=,

!

~
16-17

TABLE II. Standard

PCI~3000 Firmware Functions (Version 13.5) "

eommend(Pa_)

','

Function

,

.

Read Group
RD BY (A)

ReeD BYIl! at Pdi-3000 Bus Addreaa A.

RD BT (A. bit n)
RDWD(A)

Read BIT of SYte at PCI-3000 Bus Addra.. A.
Read WorD at PCI-3000 Bus Addreaa A (I.e., PCI-3OOO Addreaa A Is low byte and Addr888 A+l Is high byte).

RD AN (A, channel nJ

R8jld ANalog Channel n at PCI-3000 Bus Addreaa A.

RDID(A)

Read ragister IDentification of PCI-3OOO Bus AddrassA
Reed' raglster Identification of eight PCI-3000 Bus Addra.... starting at A.

I

n

RDCF [A]
RDTJ

Reed Thermocouple Channel n at PCI-3000 Bus Addra.. A.

(A, channel n)

Thermocouple types-J, K, or T ara read by entering T J, TK or TT respectively.

Write Group
WR BY (A, byte)

WRite BYte int~ PCI-3000 bus addre.. A.

WR BS (A, bit n)
WR BC (A, bit n)

,Set Bit n of byte at PCI-3000 Bus Addraas A.
Clear Bit n of byte at PCI-3000 Bus Addrass A.

WR WD, (A, word)
WR AN (A, byte)

write WorD into PCI-3000 Bus Address A (low byte) and Addra.. A+l (high byte).
Write Byte Into PCI-3000 DAC at 'bus addreaa A,

Downline Load Group
LB BL (START, END,
-xx, xx, .,'.)
LD FN (CODE1, CODE2,
0, START, END, xx, xx, .. ,)

Downline LoaD BLock of data from memory addra.. START to memory addrass END, xx ara data bytes being
loaded.
Downline LoaD new FuNction, CODEI and CODE2 ara ASCII codes of fUnction command letters. Data bytes (xx)
will be loaded In memory from START address to END address.

Continuous Function
Control Group
AC (xx, xx, ... )
CCEN

Add to Continuous function buffer. xx ara arguments and parameters required by function being sdded.
ENable Continuous Function execulion.

CCDS

DISable Continuous Function execution.

CCCL

CLear Continuous Function execution buffer.

CC RP (ENTRY)

RePort on the next continuous function rasults sterting from ENTRY

~umber.

Diagnostic Group
DR AN port (A, START
CHANNEL, No. CHANNELS)

Dump a Diagnostic Report of ANalog channels on "port". These channels ara at PCI':ioOO'Bus Add ...... A beginning
with START CHANNEL and continuing for No. CHANNELS)

DR BY port (A, NUMBER)

Dump a Diagnoetic Report of digital BYtes on "port" starting with PCI-3OOO Bus Addrass A and continuing for
NUMBER bytes.

DL TB (OUT, IN)

Do a Digital Loop Back Test from OUT byte Addreaa to IN byte Addrass. '

High Speed S\:an Group
AS [CL] (A. STARr
CHANNEL, No. CHANNEL
(G.COMP,))

Set up for high spaad scan. Add No. CHANNEL of consecutive channels beginning with START CHANNEL at
Addrass A to Cycle Table. If so specified, conversions will be done with a gain of G and cold junction compen..tion
specified by COMPo If the argument CL Is Included, the Cycle Table will be clesred befora adding any channels,

TS (A, CHANNEL n, TRIG)

Set up a trigger for high~Spaad scan. A Is the addreaa for the TRIGger, CHANNEL n 18 a bit number or analog channel number. Analog channels will trigger on a change graater than TRIG, For digital channels .TRIG defines a level
or trsnsl~lon.

AR [NU] (No. of '
Channels)

,Used to retrieve analog data stored in memory by the analog acquisition scan (M), function, Data Is ratrieved using
this function successively. No. of channels defines the num.ber of analog channels to be returned. I! NU Is specified
results will not be returned in engineering units.

M [port] (CYCLE COUNT,
DELAY [TRIG])

This will execute an analog acquisition scan of all channels in the Cycle Tabie defined by the AS command. CYCLE
COUNT defines the number of such acans desired while delay defines the time.,..in ~illlseconds-between acan8. I!
TRIG Is prasent, the acen will take place only after the trigger '(as defined by TS function) h~ occurred .. I! port is
specified, data Is dumpad out on the port, otherwise data i8 saved in memory.

Counter Module Support
EV EN (A, COUNTER n)

ENable EVent ,counting at COUNTER n at PCI-3000 Bus AddresS A:

EV RD [CL] (A,
COUNTERn)

ReaD EVent COUNTER n at PCI-3000 Bus Address A, If Gl I. p""",nllhen clear the counter after the
.)\

reac:'

FR [NW] (A,
COUNTER n, exp [m])

Re,ad FRequencY"lIt COUNTER n at PCI-3OOO Bus Add. p;" exp is a pOwer of ten and alo~g with M defineS the
units (If fr;equency desired: I! Nw Is praeent, the frequency meesurament will be Inltleted by the function will not walt
for completion.

FR RD [NW] (A,
COUNTERn)

ReeD prevlou81y initiated FRequency at COUNTER n afPCI-3000 Bus Addreaa A. if NW Is prasent the f,unctlon will
not wall for the rsading to complete.

PG FL (A, COUNTER n.
WIDTH, PERIOD number)

Output a fini", number of puleas from COUNTER n at PCI-3000 BUll,Addreaa A. WIDTH defines pules wldih;
PERIOD pulee period, numbardefines number of puleas:'

PG ~T (A, COUNTER n,
WIDTH" PERIOD)

Output a continuous Pulee Straem from COUNTERn at PCI-3000 Bus Addreaa A. Width defines pulee width,
PERIODpulesperiOll,·
.
,
,
. ' . •...
.
Stoi? j>ul.. strae,",from COUNTER n at PCI-3000 Bus ~"dl'8SJl A.

PG SP (A, COUNTER n)

..

16-18

TABLE II. Standard PCI~3000 Firmware Functions (Version L35)(Cont)
Miscella"oou. Co"lrol

SIC

Puis port into console mode.

X

Removes port from console mode.
(Conlole mode enables echo. and run. PCI-3000 on-line debug program 10 examine/change memory. etc.

IN

Inlliallzes all modules on the PCI-3000 bus.

You've now seen how to receive both digital and analog
inputs from the PCI-3000 into your personal computer.
How about the other direction-writing analog and digital data to the PCI-3000's output ports. Writing a byte
of data out to a digital output would be accomplished
with the following sequence:

!7,0,1 
where:
Marks the beginning of a return message.
Means that the response came from master
number I.
0,

Means that the function executed OK (if an
error had occurred, an "E" would have been
transmitted along with a.n error code).

PRINT #1 "$AO,7,WR BY (1,255)"
LINE INPUT #1 AS

Means that the status of the digital line in the
PCI-3000 that is being interrogated is low
(where a "I" means low and a "~" means
high).

40

The command sets all the bits (255 is the decimal equivalent of all l's) at the PCI-3000 address I.

Message terminator.
PRINT AS

In STATEMENT 40, the command PRINT AS will
cause the returned data, to be displayed on the personal
computer CRT.
Let's look at another example. We'll make a couple of
assumptions to simplify things a little bit. First, assume
that the communications channel is already open. Second,
assume that the input to the analog input is half of the
full-scale value' in the positive direction. A command
sequence to read an analog channel would be as follows:

PRINT #1 "SAO,7,RD AN (4,15)"
LINE INPUT #1 AS

The data string held in AS contains the value of the
output byte that the PCI-3000 has read back after executing the output byte function. This read back provides
a check that the data was sent correctly.
As you can probably see, it is very easy to manipulate
PCI-3000 inputs and outputs from any high level language without the need of special drivers or software
extensions from your computer. It's possible to communicate with the PCI-3000 from any computer or terminal equipped with an RS-232, RS-422 or GPIB communications port.
If you want to write personal computer programs in an
Assembler language in order to significantly improve
system performance, the PCI-3000 also offers a BINARY
protocol. The BINARY protocol is more efficient than
the ASCII protocol used in the above examples, but
does require a more detailed understanding of the operation of the PCI-3000 and the personal computer. All the
function commands available in the ASCII protocol are
also available in the BINARY protocol.

The actual response string might be:
!7,0,+1024
The decimal number +1024 represents the analog signal
level. The actual value of the response could have been
any number in the range -2048 to +2047 which represents the plus and minus full-scale swing of a 12-bit
analo~-to-digital converter.
The (4,15) in the print statement tells the PCI-3000 that
the reading should be taken on channel 15 of the analogto-digital converter whose control register is at address 4.

TERMINATION PANELS
AND HARDWARE
All 110 boards connect to input signals or to output devices
through ribbon cable connectors. A famiiy of termination
panels is offered to assure reliable, rugged, and convenient
connection to the outside world. These termination panels
connect directly to the (included) ribbon cables through
compatible connectors. Also, these panels provide mounting

16-19

, facilities for the am
45') WP

L·

j

9999.7-

-.'C\
1575mm
(0.'62")
Teflon /
Insulator

17-2

Material: Aluminum

--1I

Finish: Hard Black
43.1B,/!,m
(1.70 )

13.21mm
(0.52")

~

r

Anodize

• Idemical to 1200MC

except for mounting
holes.

MATING CONNECTORS
Material: Aluminum
Finish: Hard Black Anodize

1500MC

2250MC

3.4Smm 10.136") dis
5.84mm (0.23") dis x 82° nom.

7S.1mm

I

e'sink (2 holes)

(3.OS") - - - -

6.4mm
(.25")

SS.7mm

1 - - - - - - - ( 3 . 3 8 " ) -----~I
26.67mm

(LOS")

___- -_ _ 70.Smm _ _ __

I

dia
2 Holes

-

(2.7S")

•

11.1mm

6.3Smm
(.250") ±.015

(.44")

2302MC
I.r-

40.64mm
(1.60")

10 0 0 0 0 [

-Lt---·~~nrrr------~nt~~

------1,I

TOP VIEW

2800MC

4.45mm

DO DO lJ 1 (0.175")

_____________ t
SIDE VIEW
IL
TI
~~

S.46mm
(0.215")

I I I I I I I I I I I I 1I I 1_t
-.J

1 r'l ['JC] 6 r'l 1.1

4.06mm
(0.160")

I

44.4Smm

_(1.7S")

~

A sat of two 16·pin connector
strips for PC board rnaunting.·

-t

3.17mm
10.125")

2.S4mm
(0.10")

~t

-l (O';~") I-

dia hole
(6 each)

9.14

3.17mm
(0.12S")
.

I
\I-~-----rJ.f~)----~·~· -.L

2401MC

~

Identical to 2302MC
except each connector
strip length is 45.72mm (LBO")

I@J

-i

+---~-

6.35
mm
(0.25")

'l)m

22 . 6
(0.S9 )

-

t-@--~---t

@
~

A set of four 18-pin connector
strips for PC board mounting.

4400MC

IF=

4800MC

1~.~;.~mm=fl
68.58mm

12.70")

S.OBmm
(0.20") typ

@~E'-

@

3.25mmdis@
(0.12S")
C'sink 82°
x
37mm (0.29") .........
dia
.........

.0
"' '":

@

- -

roiE
72.14mm

(2.84")

~o~~~~+-~____~@~~
3.25mm

- (0.12S")

C'Slnd~8820x
7.37mm (0.29")
dis

Clearance for
4-40 screw on

Clearance

19.0Smm (0.75")

for

center

4-40
Screw

3.17mm (0.12S")l.1..

Q IT

•

11.94mm (0.47")

17-3

'I ~
7.

I

tl
'_-:~..

~

177 8mm

I

I,

@

@
3.18mm (0.125:JJ..L
I
12.19mm
(0.48")

MATING CONNECTORS'
2201MC

rr=='

62.87mm

1 - - - - - - (2.47S")±0.10 - - - - - - - - 1
58.42mm

I

'(2.300,"l±0.01S'
,
S3.34mm
'~_ _~
'(2.100")±0.OOS

A

1" 2 3 4

-

---.H-- _

__

-~

--

-:\rc---

I I 2.S4mm
--l f- fO.10")typ

(.OS4" - .071")
Accommodates Thick Circuit Board

O

':JL
B 12 3 4

1.37mm -1.80mm

I

-

1.40mm
(O.OSS")typ

JL'

IT

8.38mm
(0.33"l±0.00S

~

1;S2mm
'\..(O.OS")WP

(Non-accumulative)

.79mm

78.11mm
1----""'7"'D..,-447'm,.-m-----(3.07S")±0.01S
.
(2.77S")±0.00S

(0.031")

JL

6.10mm 0.64mm
(0.24") ± (0.02S") Pierced
Accommodate
3-26 AWG Wire

2350MC
50.80mm
1----------(2.00
0")
2 .54mm
(0.10") 19 places

1t

I

------------1
..

~.S4mm

~r~r(@lr~r~r~r~r~r~r~r~r~r~rC®lC®l~I~1~1~1~J==fO.1°·:~9mm
((0.031")

f ttt t' ttttf ttttttttt~'71mm
,

~
___

(0.028")

"" I

2.S4mm
(0.1, O")typ
48.26mm

1-----------(1.900")

---------1

17-4

#70 drill size

HEAT SINKS
0804HS 4.2°C/W ATT (See notes)

080JHS 12°C/WATT

TOP VIEW

(See notes)
TOP VIEW
G.

1_

2.5.4m m

1(1.0",

--l"

See

t

"mmmum-rSIDE VIEW

(0.09'"

19mm
(0.75'"

.1

~

.

~

T

Material: Aluminum
Finish: Black Anodized

2.3mm
"
(SIDE VIEW, (0.09",--1

Material: Aluminum
Finish; Black Anodized

0805HS JOC/WATT

3.55mm
(0.14'"
(2 Holes)

TOP VIEW

@---Ir---

o

-@

See
Oetaill

o

,

,

o

.......
................-::-:-::---"'~.,

0 -t---~--

I

1

-t--t---

~

00

+~
o 0

---f---t--.-

I

o

-0--1---1
BOTTOM VIEW

END VIEW

.-

--0

64.3mm
(2.53")

17.5mm

(0.69'"

'NOTES

6-32 Thread
(4 Holes)

o
101.35mm
(3.99")

o

f---

Detail 1

1. Thermal resistance specified are for natural connection. Heatsinks
0803HS and OS04HS are mounted on 6" x 6" x 1/16" G-l0 PC board.

3.86mm
(0.152'"
dia.
(2 Holes)

2. A thin-film of heatsink compound(Dow Corning 340 or equivalent)
between the heat~ink and the TO-3 device is recommended,

Hole
Pattern

17-5

0-11----'----'--

Material: Aluminum
Finish: Black Anodized

·INTERNATIONAL SALES DIRECTORY
BURR-BROWN OFFices.
Burr-B_I........-O".....

M.......... eorp.
ClIIIIoburr _

N_,.
AUSTRIA

0eIemIch

Burr-Brown R _ GeIm.b.H.

11118_"-

~11

W_WD11EA
HerttOnlohlro. E.........

A-11oo_
..-.. 0222/82 13 71
TeIe.13477

'M (OI23J 48751
ToIex_
Burr-Brown I n " " " " " Publl....._ _ D I _ C o .

UNITED KINGDOM
Burr-8rownIn_ Lid.
C........."H_

...., 1-oho1ne, AkaIakII

11m_R.....

M.......... ToIIJo 107

BENELUX
Burr-Brown InIemaIIoneI a. V.

p.o.ao.na

P.O. BOx 77.
1117 ZL ScIIlphol

1117 ZL Schlpllol. HoIIend
..-.. 0211-470lI80

TlleN'-"-'.020470SIO

..-.•• 13024

Te... 13024

FRANCE
Burr-Brownlnte....1Ion8I S.A.

aurr-8rownLId.
(ScoIIIInd -..utecIurl,.'lICIlllyJ
Slm_ P• .....,. KlrIdon Cemp...
Llvlngeton. WHI LoIhIen
EH5478G
Tel. [OSOIJ 414 445

18A_Dule_
F-7815O LeChHney
..-..(01J_
TeIe. 8II8372F

TeIe. 727484

JAPAN'
au.....rown ........ Ltd.
5FI_ . . . . . . ......

"-'.[II3J_41
TeIe. 78121S11
O_:'M (08J ___7

-

SWEDEN
Burr-Brown , _ AS

........,

184 81 UpplendS VII.,
Tel. 1J7IO.1II010
SW~LAND

W-..JWD11EA
HerIIonIIhlro.

E,.-

TeL (OI23J 33IS7

~
WUTGERMANY
Burr-Brown Inlern8llonel GmbH
HeupIaItz -

Leger:

WIIcIecher.- 28
D-7024~1 [.............J

"-'.0711170 10 as
ToIex 7255310

Burr-Brown AG
W.......rlenalr••
CH_ R_IIkonIZUrIeh

BUro B_:..-.. CM2t12S 38 31

..-.. (01J724-OII2I

BUro E........: 'M 081S1I4Z72I

Te... _

BUro D_'M021S4184 48

BUro _ r t TeL O8081ln584
ITALY
Burr-Brown Inte....._
Via Zente. 14 .

BUro M.......hen: 'M oetII1 77 37

S.r.L

20138 Mlleno
Tel. (02J _ 52 21
Te... 31t248

SALES REPRESENTATIVES
AUSTRALIA
Kenelee (AUST) Ply. Ltd.
48 Henderson Road. Clayton
Victoria, 3168
Tel. (03) 5601011
Telex 35703
BELGIUM
Luc Ruelle
Wolvestrast NBR6
3078 Everberg
CANADA
(Components)
Allan Crawford Associates
6503 Northam Drive
Misslssauga. Ontario 14V lJ2
Tel. 416/678-1500
Telex 06 966769
(Data Acquls. & Control Systems)
Webster Instruments Ltd
1134 Aerowood Drive
Mississauga. Ontario L4W 1Y5
Tel. 416/625~
Telex 06 960412
DENMARK
MER-ELAIS
Ved Klaedebo 18,
/:!K-2970 Hoersholm
Tel. (02) 57 10 00
Telex 37360
FINLAND
PerelOy
Kehiikuja 6
SF05830 Hyuinkaa 3
Tel. 14-21800
Telex 15117 PEREL SF

"'--

..'>,

GREECE
Macedonlan Electronics, Inc.
Thessalonlka-Hellas
Pontou 16-Charilaou
PO.B 240
Tel. 308800
Telex 417584

REPUBLIC OF KOREA
Oyang Corporation
CPO Box 3285
126-6 Sangandong
Chongroku. Seoul
Tel. 725-8991
Telex 22879

HONG KONG
Schmidt & Co. (HK) Ltd.
18th Floor, Great Eagle Centre
23 Harbour RClad, Wanchal
Tel. 5-8330222
Telex 74166 SCMCHX

NEW ZEALAND
McLean Inlo Teeh Ltd.
P. O. Box 9484, Newmarket
Auckland 1
Tel. 501801
Telex 21570

HUNGARY
Siex Elektronlkelemente GmbH
Karlstrasse 10
Postlach 1365
0-8250 Zirndorl
Tel. 60 71 78
Telex 623486

NORWAY
H.C.A. Melbye AlS
Postboks 8 Haugenstua

INDIA
Oriole Services & Consultants
PVTLtd.
P.B. No. 9275
4. Kul'la Inuusiriai Estate
Ghatkopar. Bombay 400 086
Tel 5122973-74-75
Telex 1171022
ISRAEL
Racom Electronics Co. Ltd.
P: O. Box 21120
Tel-Aviv 61210
Tel. 03 491922
Telex 33808

N~SL09

Tel. (02) 1080 50
Telex 71880
PORTUGAL
Telectra
P.O. Box 2531
Lisbon 1
Tel. 688072
RUMANIAIBULGARIA
Empexion. Ltd.
Falcon House. Lll1lers Close
Colliers Wood
.
London SW19 2RE
,Tel. 01~911
Telex 928472

SOUTH AFRICA
A. R. Adams Trading (PTY) Ltd
POB44048
Linden 2104
Tel. (011) 78205448
Telex 425184
SPAIN
Unltronlcs. S.A.
Torre de Madrid
(Plante 12. Ollclna 9)
Madrid
Tel. 242-5204
Telex 22596
TAIWAN
Alpha Precision Instr. Corp.
12th Floor. Express Bldg.
56 Nan King East Road. See. 4
Taipei. R.O.C.
Tel. (02) 773 2121
Telex2S138
TURKEY
Bure Ticaret Co.
P:O. Box 39
Bakanlikar, Ankara
·Tel. 1745171250300
Telex 43430 Sago TR
YUGOSLAVIA
Elektrotehna Ljubljana
TOZD Elzas
Tltova81
Ljubljana 61001
Tel. 061 329745
Telex 31767

BURR-BROWN@

BURR-BROWN CORPORATION
P.O. Box 11400 e Tucson. Arizona 85734
Telephone: (602) 746-1111 e TWX: 910-952-1111 e Telex: 66-6491

113131

Page 1

CUSTOMER PRICE LIST
Prices in U.S. dollars.
Model
Number

F.O.B. Tucson. Arizona
19

1024

25-

99

0025MK

1.00

1.00

1.00

0100MS

11.80

11.80

11.BO

0145MC

4.65

4.10

3.60

0432MC

8.00

8.00

6.00

98.50

9B.50

0546
0548MC

26.00

26.00

98.50
26.00

0549

62.00

62.00

62.00

0550

67.50

67.50

67.50

0551

69.50

69.50

69.50

0552

75.50

75.50

75.50

0553

97.38

97.38

97.38

0554

122.25

122.25

122.25

0556

155.00

155.00

155.00

0560

68.75

68.75

68.75

0561

75.10

75.10

75.10

0562

97.38

97.38

97.38

0700

57.50
60.00
50.00
57.50

57.50
60.00
50.00
57.50

57.50
60.00
50.00
57.50

M
U
UM

Quantity discounts available.
100249

Model
Number

9.85
5.20

0710

64.25

64.25

64.25

0722

49.95
60.35
54.35

49.95
60.35
54.35

37.75
49.20
43.55

66.65

66.65

52.65

.

48.55

3.30
4.95

3.30
4.95

3.00
4.10

2.70
4.10
4.00

BG
MG
0724
0803HS
MC
0804HS

4.B5

4.85

4.00

0805HS

16.50

16.50

16.50

0806MC

19.00

19.00

19.00

15.00

2014MC

15.00

2020MC

8.00

B.OO

2026MC

25.00

25.00

2201MC

2B.00

28.00

2220MC

B.oo

8.00

B.OO

2240MC

15.00

15.00

15.00

2250MC

18.00

lB.OO

18.00

2302MC

7.75

7.75

7.75

2350MC

13.00

13.00

13.00

2360MC

9.00

9.00

9.00

34.50
44.85
38.80

28.00

2525MC

25.50

25.50

3271/25

195.00

195.00

195.00

3291114

113.00

113.00

113.00
113.00

3292/14

113.00

113.00

3293/14

99.00

99.00

99.00

3329/03

38.60

3B.60

33.00

3354/25

155.00

155.00

3355/25

118.00

l1B.00

155.00
118.00

3356/25

101.00

101.00

101.00

3430J
K

123.00
123.00

123.00
123.00

123.00
123.00

3450

229.00

229.00

229.00

Effecllve September 1, 1984

3451

19
217.00

217.00

217.00

3452

217.00

217.00

217.00

3455

217.00

217.00

217.00

10.30
17.60
22.45
36.25
36.25
21.25
20.00
30.00
27.50
33.00
44.50
53.25
71.00
15.00

10.30
17.60
22.45
36.25
36.25
21.25
20.00
30.00
27.50
33.00
44.50
53.25
71.00
15.00

8.15
14.45
18.65
28.00
28.00
16.60
18.00
24.00
22.50
25.25
34.70
41.00
56.60
13.00

6.40
10.85
14.20
22.25
22.25
12.50
17.00
23.00
18.00
21.20
29.50
33.60
48.00
12.00

3501A
AQ
B
BQ
C
CQ
R
S

5.95
9.25
12.20
15.75
15.95
20.60
17.50
25.50

5.95
9.25
12.20
15.75
15.95
20.60
17.50
25.50

4.85
7.30
10.10
13.40
13.25
17.50
15.60
20.75

3.85
6.10
7.95
11.10
11.20
14.45
11.70
16.95

3507J
JQ

12.95
17.35

12.95
17.35

10.75
13.95

9.25
12.35

3508J
3510AM
BM
CM
SM
VM/883B
VM/MIL

10.75

10.75
9.35
11.85
18.25
18.25
25.00
35.00

8.65
7.50
9.40
14.25
14.25
21.00
29.00

7.75

9.35
11.85
lB.25
18.25
30.00
45.00

5.95
7.45
11.60
11.60
16.00
22.00

3521H
J
JQ
K
L
R
RQ

23.95
34.25
45.15
51.40
72.40
84.25
110.00

23.95
34.25
45.15
51.40
72.40
84.25
110.00

19.45
25.90
34.65
38.85
55.25
68.80
95.00

15.70
21.25
29.40
34.2B
47.00
55.70
82.65

3522J
K
L
S
SQ

17.85
23.50
32.75
46.30
61.65

17.85
23.50
32.75
46.30
61.65

14.35
19.40
25.25
37.30
51.95

11.75
16.00
21.10
29.85
43.65

3523J
JQ
K
L
LQ
3527AM
AMQ
BM
BMQ
CM

33.35
44.00
39.70
47.60
64.00
16.25
21.80
21.75
26.75
33.15

33.35
44.00
39.70
47.60
64.00

26.25
37.00
32.95
37.80
54.50
12.70
17.15
16.50
22.05
26.75

21.65
31.50
27.55
31.80
48.95

3500A
B
C
E
MP
R
R/883B
R/MIL
RQ
S
SQ
T
TQ
Ul883B

*

t

1024

16.25
21.80
21.75
26.75
33.15

2599

24.00

* Prices for the 3500MP are for matched pairs.

t Qualification reports $40 each.
All prices subject to change without notice.
Minimum order $75.

100249

10.95
14.85
14.65
19.25
23.30

CUSTOMER PRICE LIST

Page 2.
Prices in U.S. dollars.
Model
Number

3528AM
AMQ
BM
BMQ
CM
CMQ
3542J
JQ
S
SQ
3550J
K
S
SQ
355tJ
S
SQ
3553AM
AMO
3554AM
AMO
BM
BMO
SM
SMO
3571AM
AMO
3572AM
3573AM
3580J
3581J
3582J
JQ
3583AM
AMO
JM
3584JM
JMO
3606AG
AM
BG
BM
3626AP
BP
CP
3627AM
BM
3629AM
AP
BM
BP
CM
CP
SM
3630AM
BM
CM
SM
3650HG
JG
KG
MG
3652HG
JG
MG

F.O.B. Tucson, Arizona
19

20.25
27.05
24.85
33.00
30.25
40.95
9.75
15.00
15.80
22.45
31.20
39.75
57.80
78.00
31.80
56.15
70.00
36.00
57.00
73.20
90.00
83.80
105.00
97.60
130.00
72.45
98.00
63.00
36.00
62.00
93.45
101.50
135.00
100.00
140.00
95.00
94.50
129.50
105.00
121.00
137.00
167.00
33.60
35.91
41.35
12.50
16.75
32.65
29.25
39.60
37.30
46.35
41.40
46.35
44.00
62.25
95.00
95.00
56.25
73.15
88.90
50.40
73.15
88.90
57.25

10~

24

20.25
27.05
24.85
33.00
30.25
40.95
9.7.5
15.00
15.80
22.45
31.20
39.75
57.80
78.00
31.80
56.15
70.00
36.00
57.00
73.20
90.00
83.80
105.00
97.60
130.00
72.45
98.00
83.00
36.00
62.00
93.45
101.50
135.00
100.00
140.00
95.00
94.50
129.50
105.00
121.00
137.00
167.00
33.80
35.91
41.35
12.50
16.75
32.65
29.25
39.60
37.30
46.35
41.40
46.35
44.00
62.25
95.00
95.00
56.25
73.15
88.90
50AO
73.15
88.90
57.25

Quantity discounts available.

2599

100249

15.85
21.55
19.35
25.95
24.15
33.65
8.50
13.00
14.00
18.75
25.00
31.25
46.85
64.50
25.25
46.25
60.00
28.90
50.00
57.70
74.00
69.30
90.00
78.80
110.00
54.00
79.00
64.00
26.50
47.50
69.85
87AO
119.00
85.00
118.00
80.00
72.50
109.00
95.00
110.00
126.50
153.65
24.30
27.20
34.20
9.85
12.60
26.15
·24.20
31.00
26.50
36.75
34.20
36.75
34.00
48.70
72.25
72.25
42.80
55.15
73.35
36.60
57.35
69.70
47.25

12.95
17.45
17.55
23.60
21.90
29.00
6.50
11.00
12.65
17.50
21.45
25.50
35.70
51.00
21.45
35.70
49.00
22.45
44.00
47.70
65.00
56.15
77.00
66.30
94.50
48.00
69.00
54.50
25.00
41.00
61.00
71.00
104.00
70.00
103.00
65.00
65.50
98.00
87.00
98.50
113.85
137.00
20.85
22.65
27.85
9.15
11.25
23.05
21.45
26.35
24.80
30.60
27.85
30.60
28.00
41.15
64.50
64.50
33.75
46.70
65.00
32.00
46.70
64.00
42.80

Model
Number

3656AG
SG
HG
JG
KG
4084/25
4085BM
KG
SM
4115/04
4127JG
KG
4203J
K
S
SQ
4204J
K
S
SQ
4205J
K
S
SO
4206J
K
4213AM
AMO
BM
SM
UM
UM/883S
VM
VM/883B
VM/Mll
WM
WM/883B
4214AP
BP
RM
SM
4301
4302
4340
4341
4423
ADC10HT
HT-l
ADC60-12
ADC71JG
KG
ADC72AM
BM
JM
KM
ADC731J
K
ADC73J
K
ADC76JG
KG

t

Effective September " 1984
19

t

86.35
106.75
76.25
81.30
99.95
167.00
82.00
71.00
103.00
66.30
50.75
58.45
36.25
49.65
77.00
102.50
68.00
88.75
101.00
134.00
31.95
46.50
66.45
88.35
48.45
68.80
29.35
36.70
42.50
55.00
31.00
43.00
45.00
60.00
65.00
60.00
75.00
25.25
37.45
30.50
49.40
90.75
52.55
90.75
29.20
24.20
495.00
385.00
337.00
129.00
161.00
207.00
258.00
173.00
216.00
556.00
654.00
456.00
543.00
229.00
265.00

1024

86.35
106.75
76.25
81.30
99.95
167.00
82.00
71.00
103.00
66.30
50.75
58.45
36.25
49.65
77.00
102.50
68.00
88.75
101.00
134.00
31.95
46.50
66.45
'88.35
48.45
68.80
29.35
36.70
42.50
55.00
31.00
43.00
45.00
60.00
65.00
60.00
75.00
25.25
37.45
30.50
49.40
90.75
52.55
90.75
29.20
24.20
495.00
385.00
337.00
129.00
161.00
207.00
258.00
173.00
216.00
556.00
654.00
456.00
543.00
229.00
265.00

Qualification reports $40 each.
All prices subject to change without notice.
Minimum order $75.

2598

69.00
85.35
61.00
65.00
79.95
167.00
73.50
60.65
94.50
52.50
39.40
49.45
26.00
42.75
59.00
82.00
59.95
79.55
94.00
129.00
26.00
37.85
52.00
71.85
39.95
56.65
23.45
30.60
33.40
46.90
26.00
37.00
39.00
49.00
53.00
49.00
62.00
21.25
31.20
24.95
42.00
74.50
39.70
71AO
24.05
19.50
455.00
345.00
337.00
121.00
151.00
194.00
242.00
162.00
202.00
556.00
654.00
456.00
543.00
215.00
244.00

100249

57.85
77.85
51.00
54.50 '
66.95
59.00
49.50
75.50
48.75
34.40
43.90
19.60
34.80
53.00
74.00
51.00
64.50
82.00
116.00
19.95
30.25
40.00
56.65
30.25
42.25
18.90
25.50
28.30
37.75
23.00
29.00
29.00
38.00
42.00
38.00
48.00
16.80
27.00
23.35
36.75
64.70
32.15
64.20
17.95
16.65

93.00
116.00
149.00
186.00
125.00
155.00

165.00
199.00

CUSTOMER PRICE LIST
Prices in U.S. dollars.
Model
Number
ADC803BM
CM
ADC80AG-l0
AG-12
AGZ-12
ADC82AG
AM
AMQ
ADC84KG-l0
KG-12
ADC85-10
-12
C-12
CQ-12
Q-l0
Q-12
ADC87

F.O.B. Tucson, Arizona
1-

10-

9

24

2599

Quantity discounts available.
100-

249

259.00
239.00
214.00
175.00
299.00
278.00
249.00
199.00
85.00
85.00
68.00
46.00
87.00
87.00
69.00
48.00
87.00
87.00
69.00
48.00
65.00
65.00
44.00
52.00
94.00
94.00
75.00
63.00
127.00
127.00
110.00
105.00
105.00
70.00
84.00
115.00
115.00
92.00
77.00
143.00
143.00
115.00
150.00
150.00
120.00
132.00
132.00
106.00
193.00
193.00
159.00
172.00
172.00
139.00
206.00
206.00
165.00
240.00
240.00
225.00
216.00
1883B
335.00
335.00
294.00
270.00
IMIL
415.00
415.00
415.00
390.00
172.00
172.00
160.00
150.00
U
206.00
206.00
U/883B
190.00
180.00
ADC87V
220.00
220.00
205.00
195.00
270.00
270.00
250.00
230.00
Vl883B
V/MIL
385.00
385.00
385.00
345.00
t
BOOK-Ol
33.50
Operational Amplifiers-Design and Applications
BOOK-02
33.50
Applications of Operational Amplifiers-Third
Generation Techniques
BOOK-03
29.50
Function Circuits-Theory and Applications
BOOK-04
29.50
Designing With Operational Amplifiers-Applications
Alternatives
295.00
230.00
DAC10HT
295.00
HT-l
218.00
218.00
170.00
DAC60-10
147.00
147.00
147.00
-12
157.00
157.00
157.00
DAC63BG
108.00
108.00
83.00
89.00
126.00
126.00
97.00
107.00
BM
119.00
119.00
92.00
99.00
CG
139.00
CM
139.00
119.00
107.00
SM
209.00
209.00
182.00
166.00
TM
229.00
229.00
203.00
184.00
DAC70-COB-1
186.00
129.00
186.00
154.00
-CSB-I
186.00
186.00
154.00
129.00
DAC700BH
39.00
58.00
58.00
46.00
32.00
KH
48.00
48.00
38.00
DAC701BH
58.00
58.00
46.00
39.00
48.00
48.00
32.00
38.00
KH
DAC702BH
58.00
58.00
46.00
39.00
48.00
48.00
38.00
32.00
KH
39.00
DAC703BH
58.00
58.00
46.00
48.00
48.00
38.00
32.00
KH
73.00
54.00
DAC706BH
73.00
69.00
44.00
63.00
63.00
51.00
KH
DAC707BH
73.00
69.00
54.00
73.00
44.00
KH
63.00
63.00
51.00
DAC708BH
73.00
69.00
54.00
73.00
44.00
KH
63.00
63.00
51.00
54.00
DAC709BH
73.00
73.00
69.00
63.00
63.00
51.00
44.00
KH

Model
1Number
9
DAC71-CCD-1
55.00
-CCD-V
58.00
-COB-I
55.00
-COB-V
58.00
-CSB-I
55.00
-CSB-V
58.00
DAC72-CCD-V
91.00
-COB-I
79.00
-COB-V
91.00
-CSB-I
79.00
-CSB-V
91.00
C-COB-V
77.00
DAC736J
357.00
420.00
K
357.00
DAC73J
420.00
K
DAC80-CBI-1
34.50
-CBI-V
36.50
-CCD-I
34.50
-CCD-V
36.50
DAC800-CBH
23.00
-CBI-V
25.00
P-CBI-V
22.00
DAC80Z-CBH
34.50
Z-CBI-V
36.50
Z-CCD-V
36.50
DAC811AH
22.50
28.50
BH
79.00
RH
130.00
SH
DAC812BM
119.00
159.00
CM
DAC82KG
34.00
DAC85-CBI-1
75.00
-CBI-V
78.00
DAC850-CBI-1
33.00
-CBI-V
35.00
DAC851-CBI-1
49.00
-CBI-V
53.00
DAC85C-CBI-V
76.00
LD-CBI-V
145.00
Q-CBI-I
136.00
Q-CBI-V
141.00
DAC87-CBI-1
115.00
-CBH/B
125.00
-CBI-V
120.00
-CBI-VlB
130.00
-CBI-v/MILt
140.00
-CBI-v/MILt (8300201XC)
195.00
DAC870U
45.00
U/883B
65.00
50.00
UL
70.00
UL/883B
80.00
V
90.00
Vl883B
110.00
VlMIL
VL
85.00
VL/883B
95.00
VL/MIL
115.00

Page 3
Effective September 1, 1984
10-

24

25-

100-

249

55.00
58.00
55.00
58.00
55.00
58.00
91.00
79.00
91.00
79.00
91.00
77.00
357.00
420.00
357.00
420.00
34.50
36.50
34.50
36.50
23.00
25.00
22.00
34.50
36.50
36.50
22.50
28.50
79.00
130.00
105.00
141.00
34.00
75.00
78.00
33.00
35.00
49.00
53.00
76.00
145.00
136.00
141.00
115.00
125.00
120.00
130.00
140.00

99
48.00
52.00
48.00
52.00
48.00
52.00
79.00
71.00
79.00
71.00
79.00
67.00
357.00
420.00
357.00
420.00
29.00
29.00
31.00
32.50
18.50
20.00
17.60
29.00
29.00
32.50
17.90
22.50
63.00
106.00
95.00
127.00
27.00
60.00
63.00
26.00
28.00
39.00
42.50
61.00
130.00
121.00
123.00
105.00
115.00
110.00
120.00
130.00

95.00
105.00
100.00
110.00
120.00

195.00
45.00
65.00
50.00
70.00
80.00
90.00
110.00
85.00
95.00
115.00

178.00
40.00
60.00
45.00
65.00
75.00
85.00
105.00
80.00
90.00
110.00

165.00
35.00
55.00
40.00
60.00
67.00
75.00
90.00
72.00
80.00
95.00

t Qualification reports $40 each.
All prices subject to change without notice.
Minimum order $75.

42.00
48.00
42.00
48.00
42.00
48.00
62.00
55.00
62.00
55.00
62.00
53.00

22.00
22.95
22.00
22.95
15.50
16.75
14.75
22.00
22.95
22.95
14.90
18.90
53.00
86.00
86.00
115.00
23.00
55.00
58.00
22.00
23.50
33.00
35.50
56.00

CUSTOMER PRICE LIST

Page 4
Prices in U.S. dollars.
Model
Number
OAC87U-CBI-1
U-CBI-I/B
U-CBI-V
U-CBI-V/BOY
OAC90BG
BGQ
SG
SGQ
OlVl00HP
JP
KP
OTP-05
E
INA101AG
AM
CG
CM
SG
SM
INA104AM
BM
CM
HP
JP
KP
INA258UG
UG/883B
UL
UU883B
VG
VG/883B
VG/MIL
VL
VU883B
VUMIL
WG
WG/883B
WG/MIL
WL
WLl883B
WLIMIL
IS0100AP
BP
CP
LOG100JP
MP10
MP11
MP20
MP22BG
MP32BG
CG
MPC16S
MPC40
MPC800KG
SG
MPC801KG
SG
MPC80
S

F.O.B. Tucson, Arizona
19
90.00
100.00
95.00
105.00
19.50
26.00
27.00
36.00
30.25
42.25
60.35
195.00
195.00
17.95
14.00
23.00
18.40
24.75
19.50
24.25
29.00
37.45
18.75
22.50
29.00
34.00
38.00
37.00
41.00
45.00
54.00
70.00
49.00
59.00
77.00
58.00
69.00
87.00
64.00
76.00
96.00
32.50
35.40
39.50
43.00
169.00
175.00
336.00
324.00
324.00
405.00
23.21
12.97
27.86
55.67
14.50
30.00
23.21
12.97

1024
90.00
100.00
95.00
105.00
19.50
26.00
27 . 00
36.00
30.25
42.25
60.35
195.00
195.00
17.95
14.00
23.00
18.40
24.75
19.50
24.25
29.00
37.45
18.75
22.50
29.00
34.00
38.00
37.00
41.00
45.00
54.00
70.00
49.00
59.00
77.00
58.00
69.00
87.00
64.00
76.00
96.00
32.50
35.40
39.50
43.00
169.00
175.00
336.00
285.00
280.00
405.00
23.21
12.97
27.86
55.67
14.50 .
30.00
23.21
12.97

2599
80.00
90.00
85.00
95.00
15.50
21.00
22.00
29.00
24.15
36.25
51.95
195.00
195.00
13.50.
10.50
17.25
13.80
18.50
14.65
19.25
23.25
29.85
14.95
17.95
23.25
34.00
38.00
37.00
41.00
41.00
49.00
63.00
45.00
53.00
69.00
52.00
62.00
78.00
57.00
68.00
.86.00
28.75
31.60
36.30
35.00
135.00
140.00
269.00
259.00
259.00
324.00
20.06
11.21
23.06
46.07
12.00
24.83
20.06
11.21

Quantity discounts available.
100249
70.00
80.00
75.00
85.00
13.00
17.50
18.00
25.00
18.15
27.75
39.85

12.75
8.50
16.35
12.85
17.65
13.95
17.95
21.65
27.85
13.95
16.75
21.65
25.00
28.00
27.00
31.00
38.00
46.00
60.00
42.00
51.00
66.00
49.00
59.00
74.00
53.00
64.00
81.00
25.50
28.65
33.60
30.00

17.00
9.50
19.22
38.39
10.00
20.69
17.00
9.50

Model
Number
MPY100AG
AM
BG
BM
CG
CM
SG
SM
OPA100AM
BM
CM
OPA101AM
BM
OPA102AM
BM
OPA103AM
BM
CM
OM
OPA104AM
BM
CM
OPA105UM
UM/883B
VM
VM/883B
VM/MIL t
WM
WM/883B
WM/MIL t
OPA106UM
UM/883B
VM
VM/883B
VM/MIL t
WM
WM/883B
WM/MIL t
OPA111AM
BM
SM
OPA11HT
OPA201AG
BG
CG
RG
SG
OPA21AJ
AZ
BJ
BZ
EJ
EZ
FJ
FZ
GJ
GZ

Effective September 1, 1984
19
13.85
10.50
22.45
17.00
33.70
25.50
50.55
38.25
11.00
14.00
20,00
35.00
43.50
37.00
45.00
10.50
14.20
18.60
29.85
17.50
23.65
29.50
25.00
30.00
35.00
43.00
55.00
47.00
57.00
75.00
28.00
34.00
38.00
47.00
60.00
50.00
61.00
80.00
9.75
15.35
16.85
49.00
11.25
15.75
18.35
14.75
21.35
20.35
17.75
14.85
12.85
10.95
9.40
8.65
6.90
6.25
4.95

1024
13.85
10.50
22.45
17.00
33.70
25.50
50.55
38.25
11.00
14.00
20.00
35.00
43.50
37.00
45.00
10.50
14.20
18.60
29.85
17.50
23.65
29.50
25.00
30.00
35.00
43.00
55.00
47.00
57.00
75.00
28.00
34.00
38.00
47.00
60.00
50.00
61.00
80.00
9.75
15.35
16.85
49.00
11.25
15.75
18.35
14.75
21.35
20.35
17.75
14.85
12.85
10.95
9.40
8.65
6.90
6.25
4.95

t Qualification reports $40 each.
All prices subject to change without notice.
Minimum order $75.

2599
12.45
9.45
20.45
15.45
31.00
23.45
48.50
35.20
9.00
11.00
16.00
29.85
37.50
31.75
38.65
8.60
11.45
14.85
23.85
13.95
18.95
23.50
23.50
28.00
32.00
39.00
50.00
42.00
51.00
67.00
25.00
32.00
35.00
43.00
55.00
45.00
55.00
72.00
7.95
12.25
13.95
46.55
9.25
13.50
15.75
12.70
18.45
16.35
14.45
11.95
9.95
8.85
7.50
6.90
5.55
5.00
4.00

100249
11.25
8.50
18.65
14.10
28.65
21.70
43.00
32.55
7.95
9.85
12.00
23.25
32.75
24.25
33.50
6.80
8.95
11.55
18.50
10.25
14.50
19.00
22.00
25.00
30.00
35.00
45.00
40.00
45.00
60.00
22.00
28.00
32.00
38.00
50.00
42.00
50.00
65.00
6.35
9.95
11.95
39.20
6.95
10.50
12.35
9.60
14.35
. 13.50
11.95
9.95
8.45
7.20
6.25
5.75
4.60
4.15
3.30

CUSTOMER PRICE LIST
Prices in U.S. dollars.
Model
Number

OPA27AJ
AZ
BJ
BZ
CJ
CZ
EJ
EZ
FJ
FZ
GJ
GZ
OPA37AJ
AZ
BJ
BZ
CJ
CZ
EJ
EZ
FJ
FZ
GJ
GZ
OPA501AM
BM
RM
SM
OPA600UM
UM/883
VM
VM/883B
VM/MIL t
OPA605AM
CM
HG
KG
OPA8780
UM
UM/883B
VM/883B
VM/MIL t
PCM52JG-V
PCM53JG-1
JG-V
JP-V
PCM75JG
KG
PGA100AG
BG
PGA200AG
BG
PGA201AG
BG
PSX-24
PWR70
REF101JM
KM
RM
SM
REF10JM
KM
RM
SM
RF-500-108
SDM853

F.O.B. Tucson, Arizona
1-

9
20.95
22.25
14.95
15.95
10.95
11.80
16.00
17.00
10.70
11.25
8.20
8.65
20.95
22.25
14.95
15.95
.10.95
11.80
16.00
17.00
10.70
11.25
8.20
8.65
53.40
63.00
68.50
82.00
143.00
165.00
180.00
195.00
215.00
64.00
89.00
51.50
76.65
125.00
102.00
135.00
190.00
240.00
37.00
37.00
37.00
29.00
198.00
249.00
65.00
72.00
51.50
57.85
51.50
57.85
35.00
40.00
30.90
38.50
33.75
42.35
17.40
21.85
19.95
29.40
8.00
329.00

1024

20.95
22.25
14.95
15.95
10.95
11.80
16.00
17.00
10.70
11.25
8.20
8.65
20.95
22.25
14.95
15.95
10.95
11.80
16.00
17.00
10.70
11.25
8.20
8.65
53.40
63.00
68.50
82.00
143.00
165.00
180.00
195.00
215.00
64.00
89.00
51.50
76.65
125.00
102.00
135.00
190.00
240.00
37.00
37.00
37.00
29.00
198.00
249.00
65.00
72.00
51.50
57.85
51.50
57.85
35.00
40.00
30.90
38.50
33.75
42.35
17.40
21.85
19.95
29.40
8.00
329.00

2599
16.70
17.80
11.95
12.80
8.75
9.45
12.80
13.65
8.55
9.00
6.55
6.90

16.70
17.80
11.95
12.80
8.75
9.45
12.80
13.65
8.55
9.00
6.55
6.90
40.00
47.85
49.25
59.85
115.00
145.00
153.00
166.00
185.00
54.50
74.50
45.00
67.00
99.00
81.00
106.00
151.00
190.00

100249

12.95
13.80
9.25
9.90
7.00
7.55
9.90
10.60
6.85
7.25
5.25
5.50
12.95
13.80
9.25
9.90
7.00
7.55
9.90
10.60
6.85
7.25
5.25
5.50
32.50
37.85
42.50
49.95
102.00
118.00
126.00
135.00
175.00
48.00
66.75
40.50
57.50
88.00
72.00
95.00
134.00
170.00
23.00

32.50
32.50
32.50
26.00
179.00
235.00
55.00
62.00

145.00
189.00
49.50
54.00

39.95
46.75

34.75
41.00

39.95
46.75
35.00

34.75
41.00

27.80
35.00
30.70
38.95
15.65
19.65
17.95
26.35
7.50
329.00

Page 5

Quantity discounts available.

23.00
23.00
19.00

Model
Number

SDM854AG
BG
SDM856JG
KG
SDM857JG
KG
SHC298AM
SHC803BM
CM
SHC804BM
CM
SHC80KP
SHC85
ET
ETQ
Q
SHM60
UAF11
UAF21
UAF31
UAF41
VFC320BG
BM
CG
CM
SM
VFC32BM
BMQ
KP
SM
SMQ
UM
UM/883B
VM
VM/883B
VM/MIL
WM
WM/883B
VFC42BM
BP
SM
VFC52BM
BP
SM
VFC62BG
BM
CG
CM
SM
XTR100AM
AP
BM
BP

Effective September 1,1984
1-

9
210.00
233.00
181.00
219.00
194.00
232.00
6.95
162.00
164.00
145.00
159.00
51.00
85.00
129.00
179.00
137.00
140.00
53.60
85.50
35.20
20.85
15.95
15.60
18.50
16.60
20.65
14.90
19.95
10.15
19.70
26.00
15.00
20.00
26.00
35.00
66.00
40.00
45.00
29.65
21.35
36.00
29.65
21.35
36.00
15.95
15.60
18.50
16.60
20.65
38.00
30.00
46.00
36.00

1024

210.00
233.00
181.00
219.00
194.00
232.00
6.95
143.00
163.00
129.00
141.00
51.00
79.00
116.00
170.00
129.00
140.00
53.60
85.50
35.20
20.85
15.95
15.60
18.50
16.60
20.65

,

14.90
19.95
10.15
19.70
26.00
15.00
20.00
26.00
35.00
66.00
40.00
45.00
29.65
21.35
36.00
29.65
21.35
36.00
15.95
15.60
18.50
16.60
20.65
38.00
30.00
46.00
36.00

20.00
22.50
28.80
25.20
32.40
13.35
16.75
15.35
22.50
7.00

t

Qualification reports $40 each.
All prices subject to change without notice.
Minimum order $75.

2599

100249

168.00
187.00
145.00
175.00
155.00
186.00
5.50
129.00
146.00
115.00
126.00
41.00

4.50
117.00
133.00
105.00
115.00
34.00

68.00
110.00
162.00
110.00
140.00

57.00

40.70
78.65

26.40
53.35
19.35

27.20
14.10
11.75
11.40
13.65
12.45
15.60
10.85
15.50
8.65
15.00
20.00
11.00
16.00
21.00
29.00
54.00
35.00
40.00
25.15
17.35
30.00
25.00
17.35
30.00
11.75
11.40
13.65
12.45
15.60
35.65
27.80
43.35
33.95

11.50
8.95
8.75
11.50
10.45
13.40
8.35
11.95
6.15
11.85
16.40
7.50
12.50
18.00
23.00
43.00
30.00
35.00
21.95
15.70
24.65
21.95
15.70
24.65
8.95
8.75
11.50
10.40
13.40
28.95
23.85
35.95
29.25

CUSTOMER PRICE LIST

PageS

F.O.B. Tucson, Arizona

Prices in U.S. dollars.

MICROTERMINALS"

MICROCOMPUTER 1/0 BOARDS
Model
Number
MP1104
MP1216
-PGA
MP6102-Q
-1
MP6202-0
-1
-2
MP6303-8
-16
-24
-32
MP6304-0
MP6305-4
-8
MP6309-0
-1
MP6311-Q1
MP6394-Q
MP6421-0
MP701
MP702
MP710
-NS
MP7104
MP71 05
-NS
MP7208
MP7209
-NS
MP7216
MP7217
-NS
MP7218
MP7408
-AO
-NS-AO
-NS
MP.7432
-AO
-NS-AO
-NS
MP7504
MP7608
-I
MP8001
MP8002
MP8003
MP8004
MP8005
MP801
MP802
MP810
-AC
-DB
-LV
-NS
MP820-05
-15

199
895
815
925
570
570
260
175
375
550
610
660
720
230
335
430
410
290
410
320
375
365
625
450
395
825
710
630
885
775
830
885
775
630
560
550
670
620
495
650
770
720
595
780
795
795
90
30
110
60
40
365
625
450
450
495
395
395
475
760

Model
Number
MP821-05
-15
MP830-72
-72R
MP8304
MP8305
MP8305-NS
MP8316-1

-v

MP8408
MP8409
-NS
MP8416
MP8417
-NS
MP8418
-AO
-EXP
-ISOE
-PGA
-PGA-AO
MP8430
MP8608
-AO
MP8616
-AO
MP8632
-AO
MPV901
A
P
MPV950D
S
SM50123-001
-002
-003

Effective September 1, 1984

199
575
860
450
575
775
650
625
785
685
840
740
645
910
780
660
820
955
610
825
950
1150
950
595
720
595
720
680
795
1495
1720
2020
2840
2390
50
65
75

Model
Number
TM25-300HM
HT
NM
NT
TM27
-12
TM70
TM71
-21
-10
-10-21
B-11
B-12
B-21
B-22
B-31
B-32
TM76
K
TM77
-21
-10
-10-21
B-11
B-12
B-21
B-22
B-31
B-32
K
K-21
K-IO
K-10-21
TMT-01

149
325
265
325
265
250
250
495
595
595
695
695
1495
1495
1495
1495
1495
1495
495
595
595
595
695
695
1495
1495
1495
1495
1495
1495
695
695
795
795
18

All prices subject to change
. without notice.
Minimum order $75.

CUSTOMER PRICE LIST
Prices in U.S. dollars.

F.O.B. Tucson, Arizona

Page 7
Effective September 1, 1984

TM900 TRANSACTION PROCESSOR
Model #
TM900

Type

Type/Descriptlon

Base unit

32-terminal configuration: 19" rack mount, central processor PC board, host/consolel
link ports, 1 peripheral processor PC board, 2 RS-422/20mA Microterminal'" ports
(interface for 32 Microterminals'"), standard 115VAC power supply.
54-terminal configuration: same as above, with 1 peripheral processor PC board, and
4 RS-422/20mA Microterminal'" ports (interface for 54 Microterminals'").
96-terminal configuration: same as above, with 2 peripheral processor PC boards, and
6 RS-422/20mA Microterminal'" ports (interface for 96 Microterminals'").
128-terminal configuration: same as above, with 2 peripheral processor PC boards, and
8 RS-422/20mA Microterminal'" ports (interface for 128 Microterminals'").
24VDC battery backup power supply with internal batteries.
10MB Winchester disk drive.
Termination assembly.
Peripheral processor board.
Central processor board.
Front panel display board.
Power supply.
Battery backup power supply.

Base unit
Base unit
Base unit
PSB100
TM910
SM50196
SM50226
SM50231
SM50197
SM50229
SM51170

Option
Option
Spare part
Spare part
Spare part
Spare part
Spare part
Spare part

1-9

7500
8500
9500
10,500
1500
7680
95
2300
4250
125
1200
1800

CUSTOMER PRICE LIST

Page 8
Prices in U.S. dollars.

F.O.B. Tucson, Arizona

Quantity discounts available.

Effective September 1, 1984

PCI INTELLIGENT INSTRUMENTATION PRODUCTS
Modell!
PCI-ll0l
PCI-ll02
PCI-ll03
PCI-ll04
PCI-1201-1
-2
PCI-1202-1
-2
-3
-4
PCI-3001-1
PCI-3001-2
PCI-3301-2
-3
PCI-3302-1
PCI-3303-2
-4
PCI-3304-1
-2
-3
-4
-5
-6
PCI-3305-1
-2
PCI-3306-1
PCI-3701-1
-2
PCI-3702-1
-2
PCI-3703-1
-2
PCI-3704-1
PCI-3705-1

Type
Isolator
Isolator
Isolator
Isolator
Cable
Cable
Cable
Cable
Cable
Cable
Master
Master
Board
Board
Board
Board
Board
Board
Board
Board
Board
Board
Board
Board
Board
Board
Panel
Panel
Panel
Panel
Panel
Panel
Panel
Panel

PCI-3706-1
PCI-3901-1
-2
PCI-3902-1
PCI-3903-1
PCI-3904-1
PCI-3905-1
PCI-3906-1

Panel
MPU
MPU
Firmware
IEEE
Manual
Rack
IEEE

PCI-3907-'1
PCI-3908-1
PCI-3909-1
-2
PCI-3910-1

Rack
Cover
Expansion
Expansion
8k RAM

Type/Description
DC input opto-isolator (10-32V).
AC input opto-isolator (90-140V).
DC output opto-isolator, switches up to 60V at 3A.
AC output opto-isolator, switches 12-140V at 3A.
IEEE-488 cable, 6 feet long.
IEEE-488 cable, 12 feet long.
RS-232C cable, 3 feet long.
RS-232C cable, 6 feet long.
RS-232C cable, 10 feet long.
RS-232C cable, 20 feet long.
System enclosure (85-130VAC) with user manual.
System enclosure (200-260VAC) with user manual.
32-channel digital I/O and 16-channel single-ended analog input.
32-channel digital I/O and 8-channel differential analog input.
64-channel digital 110.
64-channel single-ended analog input.
32-channel differential analog input.
8-channel ±10V analog output.
8-channel 4-20mA analog output.
4-channel ±10V analog output.
4-channel 4-20mA analog output.
2-channel ±10V analog output.
2-channel 4-20mA analog output.
4-channel analog output and 7 counter input/pulse output.
7 ,counter input/pulse output.
32-channel J, K, T thermocouple input.
16-channel digital termination with space for custom input circuits.
16-channel digital termination with straight-through jumpers.
8/16-channel analog termination with space for custom Input circuits.
8/16 channel analog termination with straight-through jumpers.
32/16-channel analog termination with space for custom input circuits.
32/16-channel analog termination with straight-through jumpers.
16-channel thermocouple termination.
Laboratory termination, with 64 analog in, 64 digital 1/0, 4 analog out, 7 counter/pulse,
controls and PS terminals.
16-channel opto-isolator digital 1/0 requires PCI-l100 series isolators.
PC board microcomputer, without EPROM and RAM.
PC board microcomputer, with latest revision EPROM and RAM.
Latest revision firmware, with EPROMs and RAM IC's.
IEEE-488 communication port.
Additional user's manual.
Rack mount slide for master enclosure and expansion enclosure.
IEEE-488 upgrade for IBM PC, XT; includes PCI-3903 and PCI-1201-1 plus 488 board
and software for PC, XT.
Rack mount enclosure for termination panels.
Cover for rack mount termination panel enclosure.
System enclosure (85-130V).
System enclosure (200-260V).
Memory expansion IC's.

1-9
25
25
25
25
85
95
25
35
40
45
2995
2995
1395
1395
795
1695
1695
1595
1595
1125
1125
870
870
1295
790
2390
170
180
170
180
195
230
495
1150
160
995
1465
470
198
50
85
990
49
25
1495
1495
195

u.s.

SALES DIRECTORY
BURR-BROWN OFFICES

ARIZONA (H_ OH....)
In.............. Alrpori
I n _ P....
P.O. 80.11_
Tucoon 85734
T... 102-748-1111
TWX 110-152-1111
T..........11
CALIFORNIA (NorIhem)
1975 Homillon A. .~ S". 31
Ion_9II125
Tel._55..TWX 110-338-0230

CALIFORNIA (Sou_)
31225 Le ...,. DrI...
Sullo 112
W_k.VII.I1_
T... I1... . , _

ILLINOIS
33 N. Add...... Rd•• S".102
AclclloonlO101
,.... 312-832-1520
TWX 110-254-1431

1l0I-4II-7111
TWX 11G-33I-1184

MABBACHUSETTS
817 H""I_ A _ _

2001 E. Fourth Sl. Sui" 104
Ion.. _t2705
T... 714-135-0712
TWX 1110-595-1711
COLORADO
320 E. Third SINe!. Sui" A
LoveI.nd 80537
Tel. 303-183-4440
TWX 110-930-9028

_02182
TeI.eI7-444-_
TWX 7111-325-1741
MICHIGAN
23550 HeggerIJ RoecI
F.rmlnglon _
T.I. 313-474-a33
T.... 23-5238

NEW YORK

(_ropoIlIon Moo)
_

N. B.......,. Sullo 301

TEXAS (North.m)
1700 E...... Dr.• S".12O
G._75041

Yonk... 10701

,....21~-5711

,....114-_5252

TWX 110-e80-5511

TWX71o-~

OHIO
72N. Hlllh Sl
Dublin 43Ct17

,.... 814-784-11784
TWX 110-997_

-

WASHINGTON
330 112111 N.E .• Sullo 100

.........

T.I. 208-455-2111
TWX 11CJ.443-3C132

TEXAS (Sou_)

8t01 eorpo.... 0 .....
Sullo 221
Houeton 77038
T.I. 713-9I11-II54I
TWX I1C1-881-7152

SALES REPRESENTATIVES
ALABAMA
Conley & Associates
Tel. 205-882-Q316

ILLINOIS
PVA Company
Tel. 312-579-9300

ALASKA
(see Washinglon)

INDIANA
Electronic Instruments
Assoc., Inc.
Tel. 317-257-7231

ARIZONA
(see above)

IOWA
Rep Associates Corp.
Tel. 319-373-()152

ARKANSAS
(see Dallas, Texas)
CALIFORNIA
(see above)
CONNECTICUT
(see NY Matropclilan Area)
DELAWARE
ISIS Corp.
Tel. 302-478-8211
FLORIDA
Conley & Associates, Inc.

Orlando
Tel. 305-365-3283

GEORGIA
Conley & Associates, Inc.
Tal. 404-447-8992
HAWAII
(see Southern California)
IDAHO
(see Washington)

MONTANA
(see Utah)
NEBRASKA
(saa Kansas)
NEVADA (Norlh.m)
(see Northern California)
NEVADA (Soutll.m)
(see Southern California)

KENTUCKY
(s. . Ohio)

NEW HAMPSHIRE
(see Massachusetts)

LOUISIANA (Northern)
(see Dallas. Texas)

NEW JERSEY
KLS Associates, Inc.
Tel. 201-785-4450

LOUISIANA (Sou_)
(see Houston, Texas)

MARYLAND
Marktron, Inc.

Tampa
Tel. 813-885-7858

MISSOURI
Be Electronic Sales
Tel. 314-291-1101

KANSAS
Be Electronic Sales
Tel. 316-942-9840 Wichita
913-342-1211 Kansas City

MAINE
(see Massachusetts)

Boca Raton
Tal. 305-395-6108

MISSISSIPPI
(see Alabama)

Rockville
Tal. 301-251-8990
Hunt Valley
Tal. 301-628-1111
ISIS Corp.
Tel. 302-478-8211
MINNESOTA
Busch Electronics
Tal. 612-835-2044
Electronic Sales AgencY,lnc.
Tel. 612-884-8291

NEW MEXICO
Thorson Desert States, Inc.
Tel. 505-293-8555
NEW YORK
Advanced Components Corp.
North Syracuse
Tal. 315-699-2671

Endicott
Tel. 807-785-3191
Scottsville
Tel. 716-889-1429
Rochester
Tel. 716-544-7017

NORTH CAROLINA
Mureota Corporation
Tal. 919-722-9445
NORTH DAKOTA
(see Minnesota)
OHIO (No-.em)
K· T OEPCO Marketing
Tal. 216-729-3588
OHIO (SOU....m)
Alpha Conlrols. Inc.
Tel. 513-772-5544
RPM Industrial Sales
Tel. 216-247-3295
OKLAHOMA
(see Oallas, Texas)
OREGON
Branam Instrument
Tel. 503-283-2555 Portland
503-772-3187 Medford
PENNSYLVANIA (E_m)
QeD Electronics. Inc.
Tal. 215-657-5800
PENNSYLVANIA (W_m)
K-T OEPCO Marketing
Tel. 412-467-8777
Greye Glass Associates
Tel. 412-366-8664
RHODE ISLAND
(see Massachusetts)
SOUTH CAROLINA
(see North Carolina)

SOUTH DAKOTA
(see Minnesota)
TENNESSE
(see Gaorgia)
TEXAS
(see above)
UTAH
Aspen Sales
Tel. 801-467-2401
VERMONT
(see Massachusetts)
VIRGINIA
Marktron. Inc.
Tel. 301-251-8990
WASHINGTON
Branam Instruments
Tal: 206-762-6050 Saattle
509-943-8664 Richland
WASHINGTON. D.C.
(sae Maryland)
WEST VIRGINIA
(see Ohio)
WISCONSIN
Stapleman Corp.
Tel. 414-352-5777
WISCONSIN (E....m)
(see Illinois)
WISCONSIN (W....m)
(see Minnesota)
WYOMING
(see Utah)

Clinton
Tel. 315-853-6438
Robart F. Lamb Co.
Tel. 716-874-4900

For more information about products in Sections 13, 14, and 15 contact:
DATA ACQUISITION AND CONTROL SYSTEMS DIVISION
3631 E. 44th Street. Tucson. AZ 85713
(602) 747-0711
TWX: 910-952-1115

,

BURR-BROWN®

I'

I
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Create Date : 2017:08:09 19:31:56-08:00 Modify Date : 2017:08:09 20:27:38-07:00 Metadata Date : 2017:08:09 20:27:38-07:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:3e3b75e8-3a61-614d-8475-e649ec7dab1c Instance ID : uuid:ee23a2b1-6754-d04b-bf4b-727f785d1101 Page Layout : SinglePage Page Mode : UseNone Page Count : 1260
EXIF Metadata provided by EXIF.tools
1984_Burr Brown_Product_Data_Book 1984 Burr Brown Product Data Book

Navigation menu

Versions of this User Manual:

Views

Navigation
