1984_DL135_Motorola_TMOS_Power_MOSFET 1984 DL135 Motorola TMOS Power MOSFET
User Manual: 1984_DL135_Motorola_TMOS_Power_MOSFET
Open the PDF directly: View PDF 
.
Page Count: 499
| Download | |
| Open PDF In Browser | View PDF |
MOTOROLA TMOS POWER MOSFET DATA
Theory and Applications
Chapters 1 through 13
Selector Guide
II
II
Power Data Sheets
Small-Signal Data Sheets
Index
The information in this book has been carefully
checked and is believed to be accurate; however, no
responsibility is assumed for inaccuracies.
Motorola reserves the right to make changes without further notice to any products herein to improve
reliability, function or design. Motorola does not assume any liability arising out of the application or use
of any product or circuit described herein; neither
does it convey any license under its patent rights nor
the rights of others. Motorola and 8 are registered
trademarks of Motorola, Inc. Motorola, Inc. is an
Equal Employment Opportunity/Affirmative Action
Employer.
Motorola, Inc. general policy does not recommend
the use of its components in life support applications
wherein a failure or malfunction of the component
may directly threaten life or injury. Per Motorola
Terms and Conditions of Sale, the user of Motorola
components in life support applications assumes all
risks of such use and indemnifies Motorola against
all damages.
DeSigner's, Switch mode, Thermopad, Thermowatt, TMOS and
are trademarks of Motorola Inc.
Kapton® and Teflon are trademarks of E.I. DuPont
!.[
II
II
([5) . MOTOROL.A
POWER MOSFET TRANSISTOR DATA
Prepared by
Technical Information Center
Preface
After several years of development, Motorola introduced its first power MOSFETs in 1980. Several technologies
were evaluated and the final choice was the double diffused (DMOS) process which Motorola has acronymed
TMOS. This process is highly manufacturable and is capable of producing devices with the best characteristics
for product needed for power control. Most suppliers of power MOSFETs use the basic DMOS process.
The key to success of power MOSFETs is the control of vertical current flow, which enables suppliers to
reduce chip sizes comparable to bipolar transistors. This development opens a new dimension for designers
of power control systems.
This manual is intended to give the users of power MOSFETs the basic information on the product, application
ideas of power MOSFETs and data sheets of the broadest line of power MOSFETs with over 225 device types
in eleven package configurations currently available from Motorola. Chips for hybrid circuits are also available
on all the products included in this manual. The product offering is far from complete. New products will be
introduced ... doubling the product offering in the next year, offering designers an even better selection of
products for their designs.
Motorola has a long history of supplying high quality power transistors in large volume to the automotive,
television, industrial and computer markets. Being the leading supplier of power transistors in the world, we
know how to serve our customers' needs.
Printed in U.S.A.
First Edition
©MOTOROLA INC., 1984
"All Rights. Reserved"
Theory and Applications
Chapters 1 through 13
TABLE OF CONTENTS
Chapter 1: Symbols, Terms and
Definitions ................... A-1
Basic TMOS Structure, Operation
and Physics . . . . . . . . . . . . . . . .. A-6
Distinct Advantages of Power
MOSFETs .................. A-9
Chapter 2: Basic Characteristics
of Power MOSFETs .......... A-12
Chapter 3: Electrostatic Discharge
and Power MOSFETs ......... A-22
Chapter 4: Design Considerations
in Using Power MOSFETs ..... A-26
Chapter 5: Gate Drive
Requirements ................ A-33
Chapter 6: Paralleling Power
MOSFETs ................... A-49
Chapter 7: TMOS Applications .. A-72
Chapter 8: Spin-off
Technologies ............... A-101
Chapter 9: Relative Efficiencies
of Semiconductor Devices ... A-118
Chapter 10: Packaging ........ A-130
Chapter 11: Characterization and
Measurements ........... '" A-142
Chapter 12: Reliability and
Quality ..................... A-168
Chapter 13: Mounting Techniques
for Power MOSFETs ......... A-181
•
•
II
Chapter 1: Symbols, Terms and Definitions
The following are the most commonly used letter symbols, terms and definitions associated with Power MOSFETs.
Symbol
Term
Definition
Cds
drain-source capacitance
The capacitance between the drain and source terminals
with the gate terminal connected to the guard terminal of
a three-terminal bridge.
Cdg
Cgs
drain-gate capacitance
The same as Crss - See Crss .
gate-'$ource capacitance
The capacitance between the gate and source terminals
with the drain terminal connected to the guard terminal of
a three-terminal bridge.
Ciss
short-circuit input capacitance,
common-source
The capacitance between the input terminals (gate and
source) with the drain short-circuited to the source for
alternating current. (Ref. IEEE No. 255)
Coss
short-circuit output capacitance,
common-source
The capacitance between the output terminals (drain and
source) with the gate short-circuited to the source for
alternating current. (Ref. IEEE No. 255)
Crss
short-circuit reverse transfer
capacitance, common-source
The capacitance between the drain and gate terminals with
the source connected to the guard terminal of a threeterminal bridge.
9fs
common-source small-signal
transconductance
The ratio of the change in drain current due to a change
in gate-to-source voltage
10
drain current, dc
The direct current into the drain terminal.
10(on)
on-state drain current
The direct current into the drain terminal with a specified
forward gate-source voltage applied to bias the device to
the on-state.
lOSS
zero-gate-voltage drain current
The direct current into the drain terminal when the gatesource voltage is zero. This is an on-state current in a
depletion-type device, an off-state in an enhancement-type
device.
gate current, dc
The direct current into the gate terminal.
reverse gate current, drain short-circuited
to source
The direct current into the gate terminal of a junction-gate
field-effect transistor when the gate terminal is reverse
biased with respect to the source terminal and the drain
terminal is short-circuited to the source terminal.
MOTOROLA TMOS POWER MOSFET DATA
A-1
13
Symbol
Term
Definition
IGSSF
forward gate current, drain short-circuited
to source
The direct current into the gate terminal of an insulatedgate field-effect transistor with a forward gate-source voltage applied and the drain terminal short-circuited to the
source terminal.
IGSSR
reverse gate current, drain short-circuited
to source
The direct current into the gate terminal of an insulatedgate field-effect transistor with a reverse gate-source voltage applied and the drain terminal short-circuited to the
source terminal.
IS
source current, dc
The direct current into the source terminal.
PT,PD
total nonreactive power input to all
terminals
The sum of the products of the dc input currents and voltages.
rOS(on)
static drain-source on-state resistance
The dc resistance between the drain and source terminals
with a specified gate-source voltage applied to bias the
device to the on state.
thermal resistance, case-to-ambient
The thermal resistance (steady-state) from the device case
to the ambient.
RruA
thermal resistance, junction-to-ambient
The thermal resistance (steady-state) from the semiconductor junction(s) to the ambient.
Rruc
thermal resistance, junction-to-case
The thermal resistance (steady-state) from the semiconductor junction(s) to a stated location on the case.
thermal resistance, junction-to-mounting
surface
The thermal resistance (steady-state) from the semiconductor junction(s) to a stated location on the mounting
surface.
ambient temperature or free-air
temperature
The air temperature measured below a device, in an environment of substantially uniform temperature, cooled only
by natural air convection and not materially affected by
reflective and radiant surfaces.
case temperature
The temperature measured at a specified location on the
case of a device.
.
turn-off crossover time
The time interval during which drain voltage rises from 10%
of its peak off-state value and drain current falls to 10% of
its peak on-state value, in both cases ignoring spikes that
are not charge-carrier induced.
TC
TJ
channel. temperature
The temperature of the channel of a field-effect transistor.
Tstg
storage temperature
The temperature at which the device, without any power
applied, may be stored.
fcI(off)
turn-off delay time
Synonym for current turn-off delay time (see Note 1)*.
fcI(off)i
current turn-off delay time
The interval during which an input pulse that is switching
the transistor from a conducting to a nonconducting state
falls from 90% of its peak amplitude and the drain current
waveform falls to 90% of its on-state amplitude, ignoring
spikes that are not charge-carrier induced.
td(off)v
voltage turn-off delay time
The time interval during which an input pulse that is switching the transistor from a conducting to a nonconducting
state falls from 90% of its peak amplitude and the drain
voltage waveform rises to 10% of its off-state amplitude,
ignoring spikes that are not charge-carrier induced.
tei(ol'l)
turn-on delay time
Synonym for current turn-on delay time (see Note 1)*.
MOTOROLA TMOS POWER MOSFET DATA
A-2
Symbol
Term
Definition
td(on)i
current turn-on delay time
The time interval during which an input pulse that is switching the transistor from a nonconducting to a conducting
state rises from 10% of its peak amplitude and the drain
current waveform rises to 10% of its on-state amplitude,
ignoring spikes that are not charge-carrier induced.
td(on)v
voltage turn-on delay time
The time interval during which an input pulse that is switching the transistor from a nonconducting to a conducting
state rises from 10% of its peak amplitude and the drain
voltage waveform falls to 90% of its off-state amplitude,
ignoring spikes that are not charge-carrier induced.
tf
fall time
Synonym for current fall time (See Note 1)*.
tli
current fall time
The time interval during which the drain current changes
from 90% to 10% of its peak off-state value, ignoring spikes
that are not charge-carrier induced.
ttv
voltage fall time
The time interval during which the drain voltage changes
from 90% to 10% of its peak off-state value, ignoring spikes
that are not charge-carrier induced.
toff
turn-off time
Synonym for current turn-off time (see Note 1)*.
toff(i)
current turn-off time
The sum of current turn-off delay time and current fall time,
i.e., td(off)i + tfi·
Ioff(v)
voltage turn-off time
The sum of voltage turn-off delay time and voltage rise
time, i.e., td(off)v + trv·
Ion
turn-on time
Synonym for current turn-on time (See Note 1)*.
ton (i)
current turn-on time
The sum of current turn-on delay time and current rise time,
i.e., td(on)i + trio
ton(v)
voltage turn-on time
The sum of voltage turn-on delay time and voltage fall time,
i.e., td(on)v + ttv·
tp
pulse duration
The time interval between a reference point on the leading
edge of a pulse waveform and a reference point on the
trailing edge of the same waveform.
Note: The two reference points are usually 90% of the steady-state amplitude of the waveform existing after the leading edge, measured with
respect to the steady-state amplitude existing before the leading edge. If
the reference points are 50% points, the symbol tw and term average
pulse duration should be used.
tr
rise time
Synonym for current rise time (See Note 1)*.
tri
current rise time
The time interval during which the drain current changes
from 10% to 90% of its peak on-state value, ignoring spikes
that are not charge-carrier induced.
trv
voltage rise time
The time interval during which the drain voltage changes
from 10% to 90% of its peak off-state value,ignoring spikes
that are not charge-carrier induced.
tti
current tail time
The time interval following current fall time during which
the drain current changes from 10% to 2% of its peak onstate value, ignoring spikes that are not charge-carrier induced.
MOTOROLA TMOS POWER MOSFET DATA
A-3
III
•
Symbol
Term
Definition
tw
average pulse duration
The time interval between a reference point on the leading
edge of a pulse waveform and a reference point on the
trailing edge of the same waveform, with both reference
points being 50% of the steady-state amplitude of the waveform existing after the leading edge, measured with respect to the steady-state amplitude existing before the leading edge.
Note: If the reference pOints are not 50% points, the symbollp and term
pulse duration should be used.
V(BR)DSR
drain-source breakdown voltage with
(resistance between gate and source)
V(BR)DSS
gate short-circuited to source
V(BR)DSV
voltage between gate and source
V(BR)DSX
circuit between gate ahd source
V(BR)GSSF
forward gate-source breakdown voltage
The breakdown voltage between the drain terminal and the
source terminal when the gate terminal is (as indicated by
the last subscript letter) as follows:
R = returned to the source terminal through a specified
resistance.
S = short-circuited to the source terminal.
V = returned to the source terminal through a specified
voltage.
X = returned to the source terminal through a specified
circuit.
The breakdown voltage between the gate and source terminals with a forward gate-source voltage applied and the
drain terminal short-circuited to the source terminal.
V(BR)GSSR
reverse gate-source breakdown voltage
The breakdown voltage between the gate and source terminals with a reverse gate-source voltage applied and the
drain terminal short-circuited to the source terminal.
VDD, VGG
VSS
supply voltage, dc (drain, gate, source)
voltage
The dc supply voltage applied to a circuit or connected to
the reference terminal.
VDG
VDS
VGD
VGS
VSD
VSG
drain-to-gate
drain-to-source
gate-to-drain
gate-to-source
source-to-drain
source-to-gate
The dc voltage between the terminal indicated by the first
subscript and the reference terminal indicated by the second subscript (stated in terms of the polarity at the terminal
indicated by the first subscript).
VOS(on)
drain-source on-state voltage
The voltage between the drain and source terminals with
a specified forward gate-source voltage applied to bias the
device to the on state.
VGS(th)
gate-source threshold voltage
The forward gate-source voltage at which the magnitude
of the drain current of an enhancement-type field-effect
transistor has been increased to a specified low value.
ZruA(t)
transient thermal impedance,
junction-to-ambient
The transient thermal impedance from the semiconductor
junction(s) to the ambient.
ZruC(t)
transient thermal impedance,
junction-to-case
The transient thermal impedance from the semiconductor
junction(s) to a stated location on the case.
Note 1: As names of time intervals for characterizing switching transistors, the terms "fall time" and "rise time" always refer to the change that is taking
place in the magnitude of the output current even though measurements may be made using voltage waveforms. In a purely resistive circuit, the
(current) rise time may be considered equal and coincident to the voltage fall time and the (current) fall time may be considered equal and coincident
to the voltage rise time. The delay times for current and voltage will be equal and coincident. When significant amounts of inductance are present in
a circuit, these equalities and coincidences no longer exist, and use of the unmodified terms delay time, fall time, and rise time must be avoided.
MOTOROLA TMOS POWER MOSFET DATA
A-4
-------------
II
--------90%
I
I
I
I
Input Voltage
(Idealized wave shape)
---------------1-
-------10%
I
toff = toff(i) I ..
.. ,
Itd(off)=td(Off)i I
ton" ton(i)
I..
.. I
IId(on)=td(on)i :
~tr"'tril
I
I
1
1
1
I
~
I
I
------I
I
I
ID(on)
---+ --90
-:---r--
I
toff(v)
I..
Itd(off)v
~tfvl
%
I Drain
I Current
(Idealized wave shape)
10%
I --
ID(off)
..I
I
r---'trvl
---...:I-------+------------t~
I
__ 90%
~VDD
I
I
1
1
Current
(Practical wave shape
including spikes caused
by currents that are
not charge~carrier
induced)
I---ttf"'tfii
I
~
___________ +_____
t
I.. on(v) .. I
Itd(On)vl:
Drain
I
-----------
I
I
FIGURE 1-1 - WAVEFORMS FOR RESISTIVE-LOAD SWITCHING
Input
Voltage
F1-I
~---------------toff(i)
Id(off)i
Drain
Current
10%--2% --T"'-t---- ID(off)
--~
I..
"'1
I tc (or t xo ) I
I-~:....,..j
t--tti
- - - - - - - - - - VDSM
1
- - Vclamp or V(BR)DSX
- - 90%
(See Note)
1 trvl
1
I
1
I..
Drain
Voltage
~
td(off)v
1
...,
I
1
1
1
••
1 10% - VDS(on) ----t!),........:.I---~·
I
~VDD
Ioff(v)
I"
NOTE: Vcl amp (in a clamped inductive-load switching circuit) or V(BR)D5X (in an unclamped circuit) is the peak off-state voltage
excluding spikes.
FIGURE 1-2 - WAVEFORMS FOR INDUCTIVE LOAD SWITCHING, TURN-OFF
MOTOROLA TMOS POWER MOSFET DATA
A-5
•
Basic TMOS Structure, Operation and Physics
Structures:
Motorola's TMOS Power MOSFET family is a matrix of
diffused channel, vertical, metal"oxide-semiconductor
power field-effect transistors which offer an exceptionally
wide range of voltages and currents with low rOS(on). The
inherent advantages of Motorola's power MOSFETs include:
• Nearly infinite static input impedance featuring:
- Voltage driven input
- Low input power
- Few driver circuit components
• Very fast switching times
- No minority carriers
- Minimal turn-off delay time
- Large reversed biased safe operating area
- High gain bandwidth product
• Positive temperature coefficient of on-resistance
- Large forward biased safe operating area
- Ease in paralleling
• Almost constant transconductance
• High dv/dt immunity
DRAIN METAL + VDD
FIGURE 1-3 - CONVENTIONAL SMALL-siGNAL MOSFET HAS
LbNG LATERAL CHANNEL RESULTING IN RELATIVELY HIGH
DRAIN-TO-SOURCE RESISTANCE.
S
• Low Cost
Motorola's TMOS power MOSFET line is the latest step
in an evolutionary progression that began with the conventional small-signal MOSFET and superseded the intermediate lateral double diffused MOSFET (LOMOSFET)
and the vertical V-groove MOSFET (VMOSFET).
The conventional small-signal lateral N~channel
MOSFET consists of a lightly doped P-type substrate into
which two highly doped N+ regions are diffused, as
shown in Figure 1-3. The N + regions act as source and
drain which are separated by a channel whose length is
determined by photolithographic constraints. This configuration resulted in long channel lengths, low current capability, low reverse blocking voltage and high rOS(on).
Two major changes in the ,small-signal MOSFET structure were responsible for the evolution of the power
MOSFET. One was the use of self aligned, double diffusion techniques to achieve very short channel lengths,
which allowed higher channel packing denSities, resulting
in higher current capability and lower roS(on). The other
was the incorporation of a lightly doped N + region between the channel and the N + drain allowing high reverse
blocking Voltages.
,
These changes resulted in the lateral double diffused
MOSFET power transistor (LOMOS) structure shown in
Figure 1-4, in which all the device terminals are still on
the top surface of the die. The major disadvantage of this
configuration is its inefficient use of silicon area due to
the area needed for the top drain contact.
'
T
G
D
T
FIGURE 104 - LATERAL DOUBLE DIFFUSED MOSFET STRUCTURE FEATURING SHORT CHANNEL LENGTHS AND HIGH PACKINGDENSITIES FOR LOWER ON RESISTANCE.
The next step in the evolutionary process was a vertical
structure in which the drain contact was on the back of
the die, further increasing the channel packing density.
The initial concept used a V-groove MOSFET power transistor as shown In Figure 1-5. The channels In this device
are defined by preferentially etching V-grooves through
double diffused N + and P - regions. The requirements
of adequate packing density, efficient silicon usage and
adequate reverse blocking voltage are all met by this configuration. However, due to its non-planar structure, process consistency and cleanliness requirements resulted
in higher die costs.
The cell structure chosen for Motorola's TMOS power
MOSFET's is shown in Figure 1-6. This structure is similar
, to that of Figure 1-4 except that the drain contact is
dropped through the N - substrate to the back of the die.
The gate structure is now made with polysilicon sandwiched between two oxide layers and the source metal
MOTOROLA TMOSPOWER MOSFET OATA
A"6
applied continuously over the entire active area. This two
layer electrical contact gives the optimum in packing density and maintains the processing advantages of planar
LOMOS. This results in a highly manufacturable process
which yields low rOS(on) and high voltage product.
As the drain voltage is increased, the drain current saturates and becomes proportional to the square of the
applied gate-to-source voltage, VGS, as indicated in
Equation (2).
(2)
S
G
S
Where fL = Carrier Mobility
Co = Gate Oxide Capacitance per unit area
Z = Channel Width
L = Channel Length
xol
-.l
T
These values are selected by the device design engineer to meet design requirements and may be used in
modeling and circuit simulations. They explain the shape
of the output characteristics discussed in Chapter 2.
n-
It
n+
Z
10 = 2L fLCO [VGS-VGS(th)12
··r
... :.::.
D
FIGURE 1-5 - V-GROOVE MOSFET STRUCTURE HAS SHORT VERTICAL CHANNELS WITH LOW DRAIN-TO-SOURCE RESISTANCE.
Transconductance, 9fs:
The transconductance or gain of the TMOS power
MOSFET is defined as the ratio of the change in drain
current and an accompanying small change in applied
gate-to-source voltage and is represented by Equation (3).
(3) 9fs
= ~~~~~t) = ~ fLCO
[VGS-VGS(th)l
The parameters are the same as above and demonstrate that drain current and transconductance are directly
related and are a function of the die design. Note that
transconductance is a linear function of the gate voltage,
an important feature in amplifier design.
Threshold Voltage, VGS(th)
FIGURE 1-6 - TMOS POWER MOSFET STRUCTURE OFFERS VERTICAL CURRENT FLOW, LOW RESISTANCE PATHS AND PERMITS
COMPACT METALIZATION ON TOP AND BOTTOM SURFACES TO
REDUCE CHIP SIZE.
Operation:
Transistor action and the primary electrical parameters
of Motorola's TMOS power MOSFET can be defined as
follows:
Threshold voltage is the gate-to-source voltage required to achieve surface inversion of the diffused channel
region, (rCH in Figure 1-7 page A-8) and as a result,
conduction in the channel.
As the gate voltage increases the more the channel is
"enhanced," or the lower its resistance (rCH) is made,
the more current will flow. Threshold voltage is measured
at a specified value of current to maintain measurement
correlations. A value of 1.0 mA is common throughout the
industry. This value is primarily a function of the gate oxide
thickness and channel doping level which are chosen during the die design to give a high enough value to keep
the device off with no bias on the gate at high temperatures. A minimum value of 1.5 volts at room temperature
will guarantee the transistor remains an enhancement
mode device at junction temperatures up to 150°C.
Drain Current, 10:
When a gate voltage of appropriate polarity and magnitude is applied to the gate terminal, the polysilicon gate
induces an inversion layer at the surface of the diffused
channel region represented by rCH in Figure 1-7 (page
A-8). This inversion layer or channel connects the source
to the lightly doped region of the drain and current begins
to flow. For small values of applied drain-to-source voltage, VOS, drain current increases linearly and can be
represented by Equation (1).
(1)
10 =
Z
On-ReSistance, rOS(on)=
On-resistance is defined as the total resistance encountered by the drain current as it flows from the drain
terminal to the source terminal. Referring to Figure 1-7,
rOS(on) is composed primarily of four resistive components associated with:
The Inversion channel, rCH; the Gate-Drain Accumulation Region, rACC; the junction FET Pinch region,
rJFET; and the lightly doped Drain Region, rO, as indicated in Equation (4).
L fLCO [VGS-VGS(th)l VOS
(4) rOS(on) = rCH + rACC + rJFET + rO
MOTOROLA TMOS POWER MOSFET DATA
A-7
II
S
G
the on-resistance continues to decrease as VGS is increased toward the maximum rating of the device.
Note: ros(on) is inversely proportional 10 thE! carrier mobility. This
means that the rOS(on) of the P-Channel MOSFET is approximately 2.5
to 3.0 times that of a similar N-Channel MOSFET. Therefore, in order
to have matched complementary on characteristics, the ZlL ratio of the
P-Channel device must be 2.5-{3.0 Umes that of the N-Channel device.
This means larger die are required for P-Channel MOSFET's with the
same roS(on) and same breakdown voltage as an N-Channel device
and thu~ device capacitances and costs will be correspondingly higher.
Breakdown Voltage, V{BR)DSS:
o
FIGURE 1-7 - TMOS DEVICE ON-RESISTANCE
S
G
.
Breakdown voltage or reverse blocking voltage of the
TMOS power MOSFET is defined in the same manner as
V(BRlCES in the bipolar transistor and occurs as an avalanche breakdown. This voltage limit is reached when
the carriers within the depletion region of the reverse
biased P-N junction acquire suffficient kinetic energy to
cause ionization or when the critical electric field is
reached. The magnitude of this voltage is determined
mainly by the characteristics of the lightly doped drain
region and the type of termination of the die's surface
electric field.
Figure 1-9 shows a schematic' representation of· the
cross-section in Figure 1-8 and depicts the bipolar transistor built in the epi layer. Point A shows where the emitter
and base of the bipolar is shorted together. This is why
V(BR)DSS of the power FET is equal to V(BR)CES of the
bipolar. Also note the short brings the base in contact with
the source metal allowing the use of the base-collector
junction. This is. the diode across the TMOS power
MOSFET.
o
FIGURE 1-8 - TMOS DEVICE PARASITIC CAPACITANCES
Whereas the channel resistance increases with channel
length, the accumulation resistance increases with poly
width and the JFET pinch resistance increases with epi
resistivity and all three are inversely proportional to the
channel width and gate-to-sourcevoltage. The drain resistance is proportional to the epi reSistivity, poly width
and Inversefy proportional to channel width. This says that
the on-resistance of TMOS powerFETs with the thick and
high resistivity epi required for high voltage parts will be
dominated by rD.
Low voltage devices have thin, low resistivity epi and
rCH will be a large portion of the total on-resistance. This
is why high voltage devices are "full on" with moderate
voltages on the gate, whereas with low voltage devices
o
o
S
S
FIGURE 1-9 - SCHEMATIC DIAGRAM OF ALL THE COMPONENTS
OF THE CROSS SECTION OF FIGURE 1~7.
MOTOROLA TMOS POWER MOSFET DATA
A-S
TMOS Power MOSFET Capacitances:
Two types of intrinsic capacitances occur in the TMOS
power MOSFET - those associated with the MOS structure and those associated with the P-N junction.
The two MOS capacitances associated with the MOSFET cell are:
Gate-Source Capacitance, Cgs
Gate-Drain Capacitance, Cgd
The magnitude of each is determined by !he die geometry
and the oxides associated with the silicon gate.
The P-N junction formed during fabrication of the power
MOSFET results in the drain-to-source capacitance, Cds.
This capacitance is defined the same as any other planar
junction capacitance and is a direct function of the channel
drain area and the width of the reverse biased junction
depletion region.
The dielectric insulator of CgS and Cgd is basically a
glass. Thus these are very stafile capacitors and will not
vary with voltage or temperature. If excessive voltage is
placed on the gate, breakdown will occur through the
glass, creating a resistive path and destroying MOSFET
operation.
Optimizing TMOS Geometry:
The geometry and packing density of Motorola's
MOSFETs vary according to the magnitude of the reverse
blocking Voltage.
The geometry of the source site, as well as the spacing
between source sites, represents important factors in efficient power MOSFET design. Both parameters determine the channel packing density, i.e.: ratio of channel
width per cell to cell area.
For low voltage devices, channel width is crucial for
minimizing rOS(on), since the major contributing component of rOS(on) IS rCH. However, at high voltages, the
major contributing component of resistance is rO and thus
minimizing rOS(on) is dependent on maximizing the ratio
of active drain area per cell to cell area. These two conditions for minimizing rOS(on) cannot be met by a single
geometry pattern for both low and high voltage devices.
Distinct Advantages of Power MOSFETs
rating of power handling capability as a function of applied
voltage. The phenomena of second breakdown does not
occur within the ratings of the device. Depending on the
application, snubber circuits may be eliminated or a
smaller capacitance value may be used in the snubber
circuit. The safe operating boundaries are limited by the
peak current ratings, breakdown voltages and the power
capabilities of the devices.
Power MOSFETs offer unique characteristics and capabilities that are not available with bipolar power transistors. By taking advantage of these differences, overall
systems cost savings can result without sacrificing reliability.
Speed
Power MOSFETs are majority carrier devices, therefore
their switching speeds are inherently faster. Without the
minority carrier stored base charge common in bipolar
transistors, storage time is eliminated. The high switching
speeds allow efficient switching at higher frequencies
which reduces the cost, size and weight of reactive components.
MOSFET switching speeds are primarily dependent on
charging and discharging the device capacitances and are
essentially independent of operating temperature.
On-Voltage
The minimum on-voltage of a power MOSFET is determined by the device on-resistance rOS(on). For low
voltage devices the value of rOS(on) is extremely low, but
with high voltage devices the value increases. rOS(on)
has a positive temperature coefficient which aids in paralleling devices. Because of the positive temperature coefficient of rOS(on) and the negative temperature coefficient
of transconductance, power MOSFET circuits are inherently less susceptible to thermal runaway.
Input Characteristics
Examples of Advantages Offered by
MOSFETs
The gate of a power MOSFET is electrically isolated
from the source by an oxide layer that represents a dc
resistance greater than 40 megohms. The devices are
fully biased-on with a gate voltage of 10 volts. This significantly simplifies the drive circuits and in many instances the gate may be driven directly from logic inte. grated circuits such as CMOS and TTL to control high
power circuits directly.
Since the gate is isolated from the source, the drive
requirements are nearly independent of the load current.
This reduces the complexity of the drive circuit and results
in overall system cost reduction.
High Voltage Flyback Converter
An obvious way of showing the advantages of power
MOSFETs over bipolars is to compare the two devices in
the same system. Since the drive requirements are not
the same, it is not a question of simply replacing the bipolar with the FET, but one of designing the respective
drive circuits to produce an equivalent output, as described in Figures 1-1 0 and 1-11.
For this application, a peak output voltage of about 700
V driving a 30 kO load (PO(pk) '" 16 W) was required.
With the component values and timing shown, the inductor/device current required to generate this flyback voltage
would have to ramp up to about 3.0 A.
Safe Operating Area
Power MOSFETs unlike bipolars, do not require de-
MOTOROLA TMOS POWER MOSFET DATA
A-9
II
II
+Voo" 36V
1.6 mH
MR510
MTM2N90
01
'VO" 800 V
RL
30 k
15V
oJL
68
PW .. 350 p.s
f = 1.7 kHz
1.0 k
FIGURE 1-10 - TMOS OUTPUT STAGE
+V
+VCC" 32V
150 pF
2.2 {l
2.0W
MJE200
01
O.OlI'F
V o ';;':700V
02
O.51£F
270
03
MJE200
MJ8505
lN914
2N2905
-V
FIGURE 1-11 - BIPOLAR DRIVER AND OUTPUT STAGE
FIGURES 1-10 AND 1-11 - CIRCUIT CONFIGURATIONS FOR A TMOS AND
BIPOLAR OUTPUT STAGE OF A HIGH VOLTAGE FLYBACK CONVERTER
• High input impedance
Compare this circuit with the bipolar version of Figure
I-II.
To achieve the output voltage, using a high voltage
Switch mode MJ8505 power transistor, requires a rather
cqmplex drive circuit for generating the proper IBI and
IB2. This circuit uses three additional transistors (two of
which are power transistors), three Baker clamp diodes,
eleven passive components and a negative power supply
for generating an off-bias Voltage. Also, the RBSOA
capability of this device is only 3.0 A at 900 V and 4.7 A
at 800 V, values below the 7.0 A, 900 V rating of the
MOSFET. A detailed description of these circuits is shown
in Chapter 7, TMOS applications.
• Fast Switching
20 kHz Switcher
Figure 1-10 shows the TMOS version. Because of its
high input impedance, the FET, an MTM2N90, can be
directly driven from the pulse width modulator. However,
the PWM output should be about 15 volts in amplitude
and for relatively fast FET switching be capable of sourcing and sinking 100 mA. Thus, all that is required to drive
the FET is a resistor or two. The peak drain current of 3.2
A is within the MTM2N90 pulsed current rating of 7.0 A
(2.0 A continuous), and the turn-off load line of 3.2 A, 700
V is well within the Switching SOA (7.0 A, 900 V) of the
device. Thus, the circuit demonstrates the advantages of
TMOS:
An example of TMOS advantage over bipolar that ii-
• No Second breakdown
MOTOROLA TMOS POWER MOSFET DATA
A~10
II
Vee
MC34060
Q1
MC3406
MTP4N50
I . -_ _...J
PWM
200
47
MPSA55
FIGURE 1·13 - BIPOLAR VERSION
FIGURE 1·12 - TMOS VERSION
FIGURES 1·12 AND 1·13 - COMPARISON OF mos versus
BIPOLAR IN THE POWER OUTPUT STAGE OF A
20 kHz SWITCHER
Iustrates its superior switching speed is shown in the
power output section of Figures 1·12 and 1·13. In addition
to the drive Simplicity and reduced component count, the
faster SWitching speed offers better circuit efficiency. For
this 35 W switching regulator, using the same small heat·
sink for either device, a case temperature rise of only 1SoC
was measured for the MTP4N50 power MOSFET com·
pared to a 46°C rise for the MJE13005 bipolar transistor.
Although the saturation losses were greater for the TMOS,
its lowllr switching losses predominated, resulting in a
more efficient switching device. A more detailed description of this Switcher is shown in Chapter 9.
In general, at low switching frequencies, where static
losses predominate, bipolars are more efficient. At higher
frequencies, above 30 kHz to 100 kHz, the. power MOS·
FETs are more efficient
MOTOROLA mos POWER MOSFET DATA
A·11
Chapter 2: Basic Characteristics of Power MOSFETs
Output Characteristics
One of the three obvious.t!ifferences between Figures
2-1 and 2-2 is the family of curves for the power MOSFET
Perhaps the most direct way to become familiarwitli
the basic operatioh of a device i$to study its outpulcharacterlstics. In this case, a comparison of the MOSFET
characteristics with those of a bipolar transistor with similar ratings is in order, since the curves of a bipolar device
are almost universally familiar to power circuit design engineers.
As indicatet! in Figures 2-1 and 2-2, the output characteristics of the power MOSFET and the bipolar transistor can be divided similarly into two basic regions. The
figures also show the numerous and often confusing terms
assigned to those regions. To ayoidpossible confusion,
this section will refer to the MOSFET regions as the "on"
(or "ohmic") and "active" regions and bipolar regions as
the "saturation" and "active" regions.
is generated'by changes in gate voltage and not by base
current variations. A second difference is the slope of the
curve in the bipolar saturation region is steeper than the;
slope in the ohmic region of the power MOSFET indicating
that the on-resistance of the MOSFET is higher than the
effective on-resistance of the bipolar.
The third major difference between the output charac-..
teristics is that in the active regions the slope of the bipolar
curve is steeper than the slope of the TMOS curve, .making the MOSFET a better constant current source. The
limiting of 10 is due to pinch~.off occurring in the MOSFET
channel.
.
Basic MOSFET Parameters
On-Resistance
POWER MOSFET
The on-resistance, or rOS(on), of a power MOSFET is
an important figure of merit .because' it. de.termines the
amount of current the device can handle without excessive power dissipation. When switching the MOSFET from
off to on, the drain-source resistance falls from.a very high
value to rOS(on), which is a relatively low value. To.minimize rOS(on) the gate voltage should be large enough
for a given drain current to maintain operation.in the· ohmic
region. Data sheets usually include a graph, such as'Figure 2-3, which relates this information. As Figure 2-4 indicates, increasing the gate voltage above 12 volts has a
diminishing effect on lowering on-resistance (especially in
high voltage devices) and increases the possibility of spuri.ous gate-source voltage spikes exceeding the maximum
gate voltage rating of 20 volts. Somewhat like driving a
bipolar transistor deep into saturation, unnecessarily high
gate voltages will increase tum-off time because of the
excess charge stored in the input capacitance. All
Motorola TMOS FETs will conduct the rated continuous
drain current with a gate voltage of 10 volts.
As the drain current rises, especially above the continuous rating, the on-resistance also increases. Another
important relationship, which is addressed later with the
other temperature dependent parameters, is the effect
that temperature has on the on-resistance. Increasing TJ
and 10 both effect an increase in rOS(on) as shown in
Figure 2-5.
10
iii
~
9.0
8.0
~ 7.0
~
ffi
6.0
!5
540
u:
'-'
Z 4.0
~c
.9
3.0
2.0
1.0
a
a
4.0
B.O
12
16
vDS DRAIN-SOURCE VOLTAGE (VOLTS)
FIGURE 2-1 - ID-VDS TRANSFER CHARACTERISTICS OF
MTP8N15. REGION A IS CALLED THE OHMIC, ON, CONSTANT RESISTANCE OR UNEAR REGION. REGION B IS CALLED THE ACTIVE, CONSTANT CURRENT, OR SATURATION REGION.
BIPOLAR POWER TRANSISTOR
1.0
~ 9 ..0
i
B.D
!zw
7.0
~ 6.0
Transconductance
::;)
~ 5 ..0
Since the transconductance, or 9fs, denotes the gain
of the MOSFET, much like beta represents the gain of
the bipolar transistor, it is an important parameter when
the device is operated in the active, or constant current,
region. Defined as the ratio of the change in drain
current corresponding to a change .in gate voltage
(9fs = dIO/dVGS), the transconductance varies with operating conditions as seen in Figure 2-6. The value of 9fs
is determined from the active portion of the VOS-IO transfer characteristics where a change in VOS no longer significantly influences 9fs. Typically the transconductance
rating is specified at half the rated continuous drain current
and at a VOS of 15 V.
§ 4.0
~ 3.0
8
~
2.0
1 ..0
·0
a
4 ..0
B.D
12
16
VCE. COLLECT.oR-EMITIER V.oLTAGE (V.oLTS)
FIGURE 2-2 - IC-VCE TRANSFER CHARACTERISTICS .oF
MJE15030 (NPN,IC C.oNTINUOUS = B.O A, VCE.o = 150 V) REGI.oN
A IS THE SATURATION REGION. REGION B IS THE LINEAR .oR
ACTIVE REGION.
MOTOROLA TMOS POWER MOSFET PATA
A-12
ie
10;1.0A
Ib
VOS;30V
6. 0
~
I
~ 4. 0
I'
Q
~
z
~
//~
TJ; 100°C
'"~
~
25°C
'II
.9. 2.0
h VI-
0
.....: ~
2.0
4.0
0.60
m0.50
A'If
u
0 .30
~
0.20
o
6.0
8.0
0.40
6
'7
z
--55°C
~O.IO
10
~
VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)
°0~~2~.0~~4~.0~6~.0~8~.0~~1~0--1~2~~14~~1~6--'~8~~20·
FIGURE 2-3 - TRANSFER CHARACTERISTICS OF MTP4N50
iii 0.5
::;;
§
~
TJ; 100°C
0.4
~
~
TJ; 25°C
0.3
!i:::>
~
I--
--
VGS. GATE·SOURCE VOLTAGE (VOLTS)
FIGURE 2-4 - VARIATION OF rDS(on) WITH
VGS AND ID FOR MTP8N15 POWER MOSFET
3.0
V
~
z
......-
t
.-/
:::>
~O.I
Curve Falls as
2.0
0
z
Device Enters
Sen
-
TJ; -55°C
0.2
z
,
10 ;8.0 A
~ 0.70
:>:
~
ffi
z
III
0.80
8.0
Ohmic Region
(VOS Dependent)
"'z
zw
;2::;;
I-~
o!!!
i
1.0
~
~
0
o
5.0
10
15
20
0
4.0
25
10. DRAIN CURRENT (AMPS)
9.0
10
11
12
VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)
FIGURE 2-5 - VARIATION OF rDS(on) WITH DRAIN
CURRENT AND TEMPERATURE FOA MTM15N45
FIGURE 2-6 - SMALL-SIGNAL TRANSCONDUCTANCE
versus VGS OF MTP8Nl0
For designers interested only in switching the power
MOSFET between the on and off states, the transconductance is often an unused parameter. Obviously when
the device is switched fully on, the transistor will be operating in its ohmic region where the gate voltage will be
high. In that region, a change in an already high gate
voltage will do little to increase the drain current; therefore,
9fs is almost zero.
one milliampere. Device designers can control the value
of the threshold voltage and target VGS(th) to optimize
device performance and practicality. A low threshold voltage is desired so the TMOS FET can be controlled by
low voltage chips such as CMOS and TTL. A low value
also speeds switching because less current needs to be
transferred to charge the parasitic input capacitances. But
the threshold voltage can be too low if noise can trigger
the device or designers have difficulty dealing with currents from previous stages. Also, a positive-going voltage
transient on the drain can be coupled to the gate by the
gate-to-drain parasitiC capacitance and can cause spurious turn-on of a device with a low VGS(th).
Threshold Voltage
Threshold Voltage, VGS(th), is the lowest gate voltage
at which a specified small amount of drain current begins
to flow. Motorola normally specifies VGS(th) at an 10 of
MOTOROLA TMOS POWER MOSFET DATA
A-13
•
Using the TMOS Power MOSFET Designer's Data Sheets
Motorola Designer's Data Sheets are user oriented
guides that provide information concerning all the basic
TMOS parameters and characteristics needed for successful circuit design. An example of the MTM4N45 data
sheet is shown on the following pages. 'Helpful comments
and explanations have been added to clarify some of the
parameter definitions and device characteristics.
IksignE:'I"S Data Sheet
N.CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSiSTOR
These TMDS Power FETs are designed for high voltage, high
speed power switching:applications such as line operated switching
regulators. converters, solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds Specified at l00"C
•
Switching Times
Designer's Data-lOSS. VDS{on), SDA and VGS{th) Specified at
Elevated Temperature
• Rugged - SDA is Power Dissipation Limited
•
MAXIMUM RATINGS
• Represent the extreme capabilhles of the de·
vice.
• Not to be used as design condition.
0
I--"'
lr
Vas
• All Motorola ThIOS power MOSFETs lea1Ure
a rated VaS(max) of ",20 V.
• Exceeding V.r.:(max) may resutt in permanent device egradation.
• Umtt gatil voltage spi~ ~iIh a small 20
zener diode II requirad.
-
• Po
• rOS(on)
• Wire size and metallization
• Combination 01 the above
Po - MAXIMUM POWER AT A CASE
TEMPERATURE OF 25"C
• Limit Po and TC so that TC + PO· RfJJC
< TJ(max)
TJ(m~ -
MAXIMUM JUNCTION
TEMP RATURE
• Reflacta a minimum acceptable device ser·
vice IIIetime.
• Presently speclfled at l5O"C for all Motorola
power MOSFETs.
• Opereflng et conditions that guarantee a
Junction temperature less than TJ(max) may
enhance long term operating life.
~~
G'"
TMOS
V
10 - MAXIMUM CONTINUOUS DRAIN
CURRENT
10M - MAXIMUM PULSED DRAIN
CURRENT MAY BE LIMITED BY
Source to Drain Diode Characterized for Use With
Inductive Loads
--
S·
MAXIMUM RATINGS
Symbol
MTM4N45
MTP4N45
MTM4N50
MTP4N50
Unit
Drain-Source Voltage
VOSS
450
500
Vdc
Drain-Gate Voltage
(!lGS : 1.0 M!lI
VOGR·
450
500
Vdc
Rating
-
~~~
Gate-Source Voltage
Orain'Current
Continuous
Pulsed
VGS
±20
Vdc
Adc
r-
Total Power
Dissipation @ TC : 25°C
. Derate above 25°C
r-
Operating and Storage
Temperature Range
t-..-
Thermal Resistance
Junction to Case
10
10M
4.0
10
Po
75
Watts
0.6
W/oC
TJ, Tstg
-65 to 150
°C
R8JC
1.67
°CIW
TL
275
°C
THERMAL CHARACTERISTICS
Maximum lead Temp. for
Soldering Purposes, liS"
from case for 5 seconds
oeligner'. Data for "Worst
ea.." Condition.
The Designers Data Sheet permits the design of most circuits entirely from the
information presented. Limit data - representing device characteristics boundaries - are
given to facilitate "worst case" deSign.
TMOS and Designer's are trademarks of Motorola Inc.
MOTOROLA TMOS'POWER MOSFET DATA
A-14
Designer's Data Sheets
Motorola TMOS Power FETs are characterized on "Designer's Data Sheets." These data sheets permit the design of
most circuits entirely with the information provided. Key parameters are specified at elevated temperature to provide
practical circuit designs.
I
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
I
Characteristic
Min
Symbol
Max
Unit
OFF CHARACTERISTICS
r-
r-r--
Drain-Source Breakdown Voltage
(VGS = 0, 10 = 5.0 rnA)
Vdc
V(BR)OSS
MTM4N45/MTP4N45
MTM4N50/MTP4N50
Ze~o
Gate Voltage Drain Current
(VOS = 0.85 Rated VOSS, VGS = 0)
TC = 100°C
450
500
-
-
0.25
2.5
lOSS
mAdc
-
Gate-Body Leakage Current
(VGS = 20 Vdc, VOS = 0)
500
IGSS
nAdc
V(BR)OSS (BVOSS)
• Maximum sustaining voltage
• No "negative resistance" region In the I-V
characteristic
• Positive temperature coefficient
I
lOSS
• Specified at 25"C and 1OO"C
I
I • Gate must be terminated to source
I
IGSS
• Specified at max. reted VGS
ON CHARACTERISTICS'
---
Gate Threshold Voltage
00 = 1.0 rnA, VOS = VGS)
TJ= 100°C
VGS(th)
Drain-Source On-Voltage (VGS = 10 V)
00= 2.0 Adc)
(10 = 4.0 Adc)
00 = 2.0 Adc, TJ = 100°C)
VOS(on)
-
Static Drain-Source On-Resistance
(VGS = 10 Vdc, 10 = 2.0 Adc)
Vdc
2.0
1.5
4.5
4.0
-
3.0
Vdc
roSlon )
..- f---
Forward Transconductance
IVOS = 15 V, 10 = 2.0 A)
.---------~
1.5
9fs
7.5
6.0
1.5
Ohms
-
mhos
..
VGS(th)
• The gate voltege that must be applied to initiate conduction (Figure 2-7).
• Specified at 25'C and l00"C
• Negative temperature coefficient of about -6.7 mVi
"C (Figure 2-8).
VOS(on), ros(on)
• rOS(on)
•
•
•
•
~
VOS(on)
10
Analogous to !lie VCE(sat) of a bipolar daVios
SpecifIed with a maximum VGS of 10 V for Motorola
TMOS power MOSFETs.
Specified at 25"C and 100"C
PositIve temperature coefficient promotes current
sharing when devices are parallated.
91s
• The MOSFET "gain" pararnater - analogous to hFE
• Equal to the slope of the transfer characteristic
(FigUre 2-7) .
.. ~~
9fs - aVGS
• In current saturation region (Figure 2-7).
Id ~ 91. [VGS - VGS(th)J
• Relathrely constant for VGS(th) < VGS < VOS
VGS(th)
MOTOROLA TMOS POWER MOSFET DATA
A-15
+
•
•
B.O
IA
v;
l'-
VOS=30V
0
0
0
~
2.0
Jh
'11
I- V;-
'"
~
3.0
o
.>
VOS = VGS
10 = 1.0 mAde
............
...............
~ 2.8
.I
if!
TJ= 100°C
3.4
;;; 3.2
J
0
3.6
2:>
2.4
'".~
-TJ=-55°C
B.O
4.0
6.0
VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)
2.6
~
~
5
TJ = 25°C
~
~
..........
'"
.........
............
2.2
2.0
............
.............
$1.8
1.6- 50
10
FIGURE 2-7 - TRANSFER CHARACTERISTICS
-25
o
25
50
75
100
TJ. JUNCTION TEMPERATURE lOCI
125
150
FIGURE 2-8 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
DYNAMIC CHARACTERISTICS
Input Capacitance
(VOS = 25 V, VGS = 0, f = 1.0 MHz)
Output Capacitance
~
(VDS = 25 V. VGS = 0, f = 1.0 MHz)
Reverse Transfer Capacitance
(VOS = 25 V. VGS = O. f = 1.0 MHz)
Ciss
-
1200
pF
Coss
-
300
pF
Crss
-
80
pF
MOSFET CAPACITANCES
'--
The physical structure of a MOSFET results in capacitors between the terminals. The metal oxide gate structure determines the capaCitors from gate-ta-drain (CQd),
and gate-to-source (Cgs)' The PN junction formed dunng
the fabrication of the TMOS FET results in a junction
2000
capacitance from drain-to-source (Cds).
c-Cg~ DRAIN
These capacitances are characterized as input (Ciss),
1600
Ciss = ~d + C~s
output (Cos s) and reverse transfer (C rss) capacitances
Coss = gd + ds
t-'
~CdS
on data sheets. The relationships between the interelecCrss = Cgd
!1200
trode capacitances and those given on data sheets, along
Cgs
SOURCE
with their variations as a function of Drlilin Voltage, are ~
... BOO
I'-..
I
shown in Figure 2-9.
Cis.
1\
In driving a MOSFET, the input capacitance, Ciss is an ..s
important parameter. This capacitance must be charged
I
400 \\
and discharged by the drive circuit to effect the switching
\
I'....
cos.
function. The impedance of the drive source strongly afc,.......
0
fects the switching speed of a MOSFET. The lower the
0
10
20
30
40
50
driving source impedance, the faster the switching
voSo DRAIN·TO·SOURCE VOLTAGE (VOLTS)
speeds. Temperature variations have little effect on the
FIGURE 2-9 - TMOS INTERELECTRODE CAPACITANCES
device capacitances; therefore, switching times are affected very little by temperature variations.
r-~
~
§
MOTOROLA TMOS POWER MOSFET DATA
A-16
_SWIT CH ING CHARACTERISTICS' (TJ= 100°Cl
Turn-On Delay Time
(VoS = 25 V. 10 = 2.0 A. Rgen = 50 ohms)
Rise Time
(VoS = 25 V. 10 = ·2.0 A. Rgen 50 ohms)
Turn-Off Delay Time
(VoS = 25 V. 10 = 2.0 A. Rgen = 50 ohms)
Fall Time
(VoS = 25 V. 10 = 2.0 A. Rgen = 50 ohms)
Id(on)
-
50
ns
Ir
-
100
ns
200
ns
100
ns
Id(off)
-
If
Switching Characteristics
-
MOSFET switching speeds are very fast, relative to comparably sized bipolar transistors. Since they are majority
carrier devices, there is no storage time associated with the turn-off time; consequently, the switching waveform
components are associated with the charging and discharging of the interelectrode capacitances. Driving a MOSFET through a switching cycle involves driving these non-linear capacitances. Switching times, therefore. will
strongly depend on the impedances of the driving source and drain load. Maximum limits at elevated temperature
are specified.
• During td(on) - The drive circu.it charges Ciss to VGS(th)' No drain current flows; VDS remains essentially
at VDD.
- Ciss is charged by the drive circuit to VGS(on)' Cos s discharges from VDD to approach
• During tr
VDS(on) and ID increases from zero, approaching its maximum. As VD'S approaches VDS(on),
the rapid rise of Cos s at low drain voltages delays the rise of ID' likewise the increase of Ciss
inhibits the rise of VGS through the drive impedance.
• During td(off) - Ciss begins to discharge through the gate circuit impedance. The transistor turns off and the
drain supply charges Cos s through the load. The initial rise of VDS is slowed by the high
value of Cos s at low drain voltages.
- Coss diminishes rapidly as the drain voltage rises. Virtually no additional charge is required
• During tf
to be sourced by the drain supply; VDS rises rapidly to VDD (and beyond if inductance is
present in the load).
Resistive Switching
Id(on)
Output, Vout
Inverted
FIGURE 2-10 -
SWITCHING TEST CIRCUIT
FIGURE 2-11 -
MOTOROLA TMOS POWER MOSFET DATA
A-17
SWITCHING WAVEFORMS
II
SOURCE-DRAIN DIODE CHARACTERISTICS·
IS = 4.0 A
Symbol
VSD
Typ
1.1
VGS=O
ton
trr
250
420
Characteristic
I
Forward On-Voltage
Forward Turn'-On Time
I
Reverse Recovery Time
I
Unit
Vdc
ns
ns
·Pulse Test: Pulse Width E:;;300 Ill. Duty Cycle ~2%.
• An integral feature of all power
MOSFET structures.
• Reverse recovery times are comparable
with those of fast recovery rectifiers.
• Rated current equal to that of the MOSFET
• May be used as a commutator in complementary
totem-pole or H-bridge configurations with
inductive loads, or in a "Synchronous
Rectifier" mode.
+ VOO
THE POWER MOSFET
SOURCE-DRAIN DIODE
L
EQUIVALENT TEST CIRCUIT
IFM - - -
90 /:-"1"-----,
0
L
L
o
ton
OUT WAVEFORM
TOTEM-POLE
N-CHANNEL
COMPLEMENTARY
P-CHANNEUNCHANNEL
DURING TURN-OFF OF aI, 02 PROTECTS
01; LIKEWISE
DURING TURN-OFF OF a2, 01 PROTECTS
02
FIGURE 2-12 -
SOURCE-Ta-DRAIN DIODE TEST CIRCUIT AND WAVEFORM
MOTOROLA TMOS POWER MOSFET DATA
A-18
-IRM
I
~
r - - - - - - - - - - - . S A F E OPERATING AREA INFORMATION
mmEmD
10
0.1
I
10"s
ml
5.0
IOI-+-+--I--+-I-+-+-f-+--i---I---I
.0 ms
i 2.
~
!iii
-
~-i-1--~~~11~10~~~"~~~~HH~
(
!iii
...~
de
l.:~~~~~~~~I!~~~~~iI~~~
- 'lIS(o.llim"
~ 0.5 ----PIOOge lim
~
Thennallim"
I
Q
I
I
MTM/MTP4H4S'" t'<;::
TC= 25°C
0.1 VGS = 20 V, Singl. Pulse
MTM/MTP4NSO
IO
30
50
100
300 500
Vos. ORAIN·TO-SOURCE WlTAGE (WlTSI
TJ" ISooC---II-+-+-t-+-t--+--+---i
6.0 -
~
MTM/MTP4N45 ~
~ 4.01-+-+-+-+-IMTM/MTP4N50fr-=JI-,...--::-I-t---i
.s;. 0.2
I
8.111--'-+-+--+---+--+--+-1--+--+-+--+-~
2.01-+---+-+-+~1--+--+--+--+--f-+--;
r-
110
1000
FIGURE 2-13 - MAXIMUM RATED FORWARD BIASED
SAFE OPERATING AREA
600
200
310
0
500
Vas. ORAIN·TO·SOURCE WlTAGE (WlTSI
FIGURE 2-14 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
THERMAL RESPONSE
0-0.5
~ 0.5
.. z , , 0 m_
~ 0.3 1---+-+-+-+-+, ~,!
e
~ f3
_
~11
0.2
.
~! ~~~ ~~OI"iii~l-~jliP-~~~ I-JUl'
t---j
co '"
~ 0.1
ffi
it
i
~
0.70
-50
-25
25
50
75
100
125
""-..
N+ Substrate
150..
Drain Metallization
TJ. JUNCTION TEMPERATURE ('CI
FIGURE 2-16 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
FIGURE 2-17 - CROSS SECTION OF TMOS CELL
MOTOROLA TMOS POWER MOSFET DATA
A-20
I
I
drain. Since the diode may be an important circuit element, Motorola Designer's Data Sheets specify typical
values of the forward on-voltage, forward turn-on and reverse recovery time. The forward characteristics of the
drain-source diodes of several TMOS power MOSFETs
are shown in Figure 2-19.
magnitude and the rate of change of current from the
forward current magnitude to the reverse current peak.
When tested under the same circuit conditions, the parasitic drain-source diode of a TMOS transistor has a trr
similar to that of a fast recovery rectifier.
Drain
Gate~
Source
FIGURE 2-18 - COMPLETE N-CHANNEL POWER MOSFET SYMBOL
INCLUDING DRAIN-SOURCE DIODE
Most rectifiers, a notable exception being the Schottky
diode, exhibit a "reverse recovery" characteristic as depicted in Figure 2-20. When forward current flows in a
standard diode, a carrier gradient is formed in the high
resistivity ,side of the junction resulting in an apparent
storage of charge. Upon sudden application of a reverse
bias, the stored charge temporarily produces a negative
current flow during the reverse recovery time, or t rr , until
the charge is depleted. The circuit conditions that influence trr and the stored charge are the forward current
In many applications, the drain-source diode is never
forward biased and does not influence circuit operation.
However, in multi-transistor configurations, such as the
totem pole network of Figure 2-21, the parasitic diodes
play an important and useful role. Each transistor is protected from excessive flyback voltages, not by Its own
drain-source diode, but by the diode of the opposite transistor. As an illustration, assume that 02 of Figure 2-21
is turned on, 01 is off and current is flowing up from
ground, through the load and into 02. When 02 turns off,
current is diverted into the drain-source diode of 01 which
clamps the load's inductive kick to V +. By similar reasoning, one can see that DZ protects 01 during its turnoff.
As a note of caution, it should be realized that the drainsource diode of a power MOSFET, like all diodes except'
the Schottky, have forward recovery times, meaning they
do not instantaneously conduct when forward biased.
Therefore, in a totem pole configuration, the TMOS drainsource diode may be too slow to protect the complementary transistor from excessive flyback voltage. Because
of this possibility, rapid switching of such configurations
may require other clamping schemes.
Is ' 0.5 A/div
II
11111!
1= 100 ns/div
100
50
~
~
/
w
f2
~
~
MTM: Melal'TO-3
MTP: PlaSlic TO-220
I
"
TC '25OC
300 "s Pulse 60 pps
/
I
t
1.0
6
,. .' "
-"'0.5
I
/,1
I I
I
0.1
o
+v
/,
if/'// 1/
jI '/,'
I
/
:
ill P1i ~.
/,
I
a:
~
r~
I
10 ,
--1 ____ L_ .
01
Continuou~
MTP1N60:
Mtp5N06:
MTMSN10:
MTM15N06:
MTM15N15:
MTM25N06:
II'!.iiii
FIGURE 2-20 - REVERSE RECOVERY CHARACTERISTICS OF
MTM15N15 DRAIN-SOURCE DIODE
~;lN60
/,
tI;
5.0
(J)
,/,/
/MTP5N06',./
/
,','
~ 10
i~
:IB
MTP25NO~/~
MTP15N15
MTM15N06
MTMSN10
I
~
1.0 A
5.0 A
S.OA
15A
15 A
25 A
I ........J
1.0
2.0
3.0
4.0
5.0
6.0
VSD . D-S DIODE FORWARD ON-VOLTAGE (VOLTS)
-v
FIGURE 2-19 - FORWARD CHARACTERISTICS
OF POWER MOSFETs D-S DIODES
FIGURE 2-21 - TMOS TOTEM POLE NETWORK
WITH INTEGRAL DRAIN-SOURCE DIODES
MOTOROLA TMOS POWER MOSFET DATA
A-21
~
•
Chapter 3: Electrostatic Discharge and Power MOSFETs
TABLE 3 - Typical Electrostatic Voltages
One of the ~ajor·problems plaguing electronics cOmponents todayls damage by electrostatic discharge
(ESO). ESO can cause degradation or complete component failure. Shown in Table 1 are the susceptibility
ranges of various devices to ESO. As circuitry becomes
more complex and dense,device geometries shrink, making ESO a major concern of the electronics Industry_
Electrostatic Voltages
10 to 20
Percent
Relative
Humidity
65 to 90
Percent
Relative
Humidity
Walking across carpet
35,000
1,500
Walking over vinyl floor
Means of
Static Generation
Generation of ESD
Electrostatic potential is a function of the separation of
non-conductors on the list of materials known as the TriboelectricSeries. (See Table 2.) Additional factors in
charge generation are the intimacy of contact, rate of separation and humidity, which makes the material surfaces
partially conductive. Whenever two non-conductive mj!.~
terials are flowing or moving with respect to each other,
an electrostatic potential is generated.
12,000
250
Worker at bench
6,000
100
Vinyl envelopes per
work instructions
7,000
600
Common poly bag
picked up from bench
20,000
1,200
Work chair padded with
polyurethane foam
18,000
1,500
TABLE 1 - Susceptibility to ESD
Range of ESD
Susceptibility (Volts)
Device Type
Power MOSFET
100-200
JFET
140-10,000
CMOS
250-2,000
Sch6ttky DiOdes, TTL
~~2,500
Bipolar Transistors
300;-.7,000
ECl
500
SeR
From the Tables,it is apparent that sensitive electronic
components can·be easily damaged or destroyed if precautions are not taken.
ESD and .Power MOSFETs
Being MOS devices, TMOS transistors can be damaged
by ESO due to improper handling or installation. However,
TMOS devices are not as susceptible as CMOS. Due to
their large input capacitances, they are able to absorb
more energy before being charged to the gate-breakdown
voltage. Nevertheless, once breakdown begins, there is
enough energy stored in the gate-source capacitance to
cause complete perforation of the gate oxide. With a gateto-source rating of VGS .= ± 20 V maximum and electrostatic voltages typically being 100-25,000 volts, it becomes very clear that these devices require special handling procedures. Figure 3-1 shows curve tracer photos
of a goOd device, and the same device degraded by ESO.
680-1,000
.
TABLE 2 - Trlboelectrlc Series
Air
Human Skin
Glass
Human Hair
Wool
Fur
Paper
Cotton
Wood
Hard Rubber
Acetate Rayon
Polyester
Polyurethane
PVC (Vinyl)
Teflon
~
Static Protection
Increasingly
Positive
The basic method for protecting electronic components
combines the prevention of static build up with the removal
of existing charges. The mechanism of charge removal
from charged objects differs between insulators and conductors. Since charge cannot flow through an insulator, it
cannot be removed by contact with a .conductor. If the
item to be discharged is an insulator (plastic box, person's
clothing, etc.), ionized air is required. If the object to be
discharged is a conductor (metal tray, conductive bag,
person's body, etc.), complete discharge can be accomplished by grounding it.
A complete static-safe work station should include a
grounded conductive table top, floor mats, grounded operators (wrist straps), conductive containers, and an ionized air blower to remove static ·from non-conductors. All
soldering irons should be grounded. All non"conductive
items such as styrofoam coffee cups, cellophane wrappers, paper, plastic handbags, etc. should be removed
from the work area. A periodic survey of the work area
Increasingly
Negative
From Table 2, it can be seen that cotton is relatively
neutral. The materials that tend to reject moisture are the
most significant Contributors to ESO. Table 3 gives examples of the potentials that can be generated under various conditions .•..
MOTOROLA TMOS POWER MOSFET DATA
A-22
r--
I
I
I
-I
I
!
I
---I
I
~
I
I
-I
I
I
I
r--
--"1
I
r-I
~
~--
.9
,
r--r-'-'--r~--r-.--r-.--~·--,
I
+-1+.'1
I
I
I
--"1
I
-"1
I
r-
-~
j---
I
j---
j-I
r
~
I
I
j---
I
j--
J
-
I
j-I
I
~
r--
I
I
J
L
- -~
~
I
£l f-l+'"'
---I
I
~
I
--~
1-++:-+
--"1II
r- -
L
VDS
Normal Device
Vertical = 1.0 rnA/Division
Horizontal = 20 VlDivision
"
~
~
-'
"
I
+< +~
---III
--I
I
- --I
I
~
I
J
VDS
Same Device Degraded by ESD
Vertical = 1.0 rnA/Division
Horizontal = 20 VIDivision
FIGURE 3-1 - CURVE TRACER DRAWINGS OF A GOOD DEVICE AND A DEVICE
WITH A DEGRADED GATE. DEVICE IS A 100 VOLT, 12 AMP POWER MOSFET
with a static meter is good practice and any problems
detected should be corrected immediately. Above all, education of all personnel in the proper handling of staticsensitive devices is key to preventing ESD failures. Figure
3-2 shows a typical manufacturing work station.
Test Method:
Military specifications MIL-STD-883B Method 3015.1,
DOD-HDBK263, and DOD-STD-1686 classify the sensitivity of semiconductor devices to electrostatic discharge
as a function of exposure to the output of a charged network (Table 4). Through measurements and general
agreement, the "human-body model" was specified as a
network that closely approximated the charge storage capability (100 pF) and the series resistance (1.5 k) of a
typical individual (Figure 3-3). Discharge of this network
directly into a device indicates that the model assumes a
"hard" ground is in contact with the part. Although all pin
combinations should be evaluated in both polarities (a
total of six combinations for a TMOS Power MOSFET),
preliminary tests usually show that gate-oxide breakdown
is most likely, and that reverse-biased junctions are about
an order of magnitude more sensitive than forward-biased
ones. The amount of testing, and components required,
can therefore be reduced to sensible levels, yet still yield
statistically sound data. The damage mechanism, which
can be identified through failure analysis of shorted or
degraded samples, is usually oxide puncture or junction
meltthrough.
NOTES: 1. 1/16 inch conductive sheet stock covering bench top work
area
2. Ground strap
3. Wrist strap in contact with skin
4. Static neutralizer (Ionized air blower directed at work) Primarily for use in areas where direct grounding is impractical
Rl
1.5 k
Cl
FIGURE 3-2 - TYPICAL MANUFACTURING WORK STATION
100 pF
By following the above procedures, and using the
proper eqUipment, ESD sensitive devices can be handled
without being damaged. The key items to remember are:
1 -
Handle all static sensitive components at a static
safeguarded work area.
2 -
Transport all static sensitive components in static
shielding containers or packages.
3 -
Education of all personnel in proper handling of
static sensitive components.
DUT
FIGURE 3-3 - THE HUMAN-BODY EQUIVALENT NETWORK
Significance of Sensitivity Data
Assuming that corrective measures cannot be immediately applied in a manufacturing area, or that products
manufactured using MOSFET components are likely to
MOTOROLA TMOS POWER MOSFET DATA
A-23
--
I
•
be exposed to ESD events in the field, the sensitivity of
the device can be used as a general indicator of the
likelihood of failure. Additionally, the extent and cost of
TABLE 4 Device
Sensitivity
(C1 Peak Voltage)
Sensitivity of Semiconductors to ESD from .a Charged Network
MIL-STD-883
Class
1000-2000
Class 1 }
Class 3
B
ea." ..,...,. ae.Ig",
Wrist Straps, Ionized Air,
Conductive Flooring, Conductive
Clothing, etc. Field-Strength Alarm.
( Antistatic Carpet Spray, Wrist Straps,
Conductive Packaging Materials.
Humidity Adjustment
(Nonsensitive)
4000-15,000(1)
Typical
Preventive Measures(2)
Cmefur
Class 2 }
B
2000-4000
t
DOD-HDBK-263
Class
A
(Sensitive)
A
0-1000
protective measures increases as device susceptibility increases.
Class 3
Notes: 1. Data collected In many applications have shown that under special conditions voltages considerably in excess of 15 kV can be generatad
with certain materials In the Trlboelectric Series.
2. These examples are intended only as very general guidelines. The actual accuracy of a given method is highly variable, as a large number
of interdependent factors influence electrostatic field generation. Operator awareness, complemented with a high quality hand-held electrostatic field-strength meter referenced to ground, can be very effective in controlling profit losses due to ESO.
A Simple ESD Pulser
A simple electrostatic discharge circuit, which simulates
the human body model, is shown in Figure 3-4.
The high voltage supply consists of a 20mAconstant,
current luminous-tube transformer and a half-wave voltage doubler circuit. Adjustment of the high voltage is accomplished with a 1.0 Amp Variac. (An oscillator-type supply may also be constructed, using a flyback transformer.)
Power
e>----:
e.
~
...«""
~
..,"?cz
~ T =
0.4
~
c 0.2
(----
TJ
./
V
...- ~"
-
0.6
w
'-'
'"=>c
TJ.IOOoC
O.B
~
°
~ ~55°C
-
V
VGS - 10 V
~
c
<7f
e
4.0
B.O
12
16
RGURE 4-3 - ON-RESISTANCE versus DRAIN
CURRENT FOR THE MTM8N40
rOS(on) and the typical rOS(on) under the same operating
conditions can be used as a multiplier. In this situation,
an rOS(on) maximum of O.S ohms is specified at an 10 of
4.0 A and a TC of 25°C. At these same conditions, rOS(on)
is typically at O.4S ohms (Figure 4-3). Assuming the ratio
between typical and worst case values remains fairly conD
ArOS(on)
~ =
0.97 - 0.58 ohms
100 - 25°C
=!1
T
IRMS =
IRMS
AI 12A,
CT =
20
10. DRAIN CURRENT (AMPS)
D
0.0052 ohmsrC
Assuming TJ = 110°C
av'll
=D
=~
IRMS
=
aft
rOS(On)]TJ = 1100C= rOS(On)]TJ = 250C+ (TJ -25) CT
= 0.58 ohms + (110°C + 25OC) 0.0052 ohmsrC
= 1.02 ohms
IRMS =
This value of rOS(on) is derived from a typical curve
and does not represent a worst case value. To obtain a
worst case estimate, the ratio between the maximum rated
0
FIGURE 4-4 - RMS VALUES OF SOME COMMON
CURRENT WAFEFORMS
MOTOROLA TMOS POWER MOSFET DATA
A-27
50
ros(on) MAX
08)
stant, the multiplier is 1.67 (
TYP = 04·8 .
. rOS(on)·.
.
Therefore, the worst case rOS(on) at 12 A,11O°Cis approximately 1.67 x 1.02 ohms, or 1.7 ohms.
40
MTM/MTH8N35 -
f-
MTM/MTH8N40
From the trapezoid waveform in Figure 4-4:
IRMS
MTM/MTH7N45
MTM/MTH7N50
__ oJa2 +ab+b2
. 3
= 0.5
TJ.<;; 150°C
)82+ 8.~6 + 162
o
o
= 6.11 A
and Po = 12 RMS rOS(on)
= (6.11)21.7
FIGURE 4-5 - MAXIMUM RATED SWITCHING
SAFE OPERATING ARE OF THE MTM8N40
=63W
through load or stray inductances can force VOS to exceed V(BR)OSS may contain enough energy to destroy
the deVice if It begins to avalanche. Transients on the
drain supply voltage can also destroy the power MOSFET.
Fortunately, if there is any danger of these destructive
transients, the solutions to the problems are fairly simple.
Figure 4-6 illustrates a FET switching an inductive load
in a circuit which provides no protection from excessive
flyback Voltages. The accompanying waveform depicts
the turn-off voltage transient due to the load and the parasitic lead and wiring inductance. The MTM20N10 experiences the unrecommended avalance condition for
about 300 ns at its breakdown voltage of 122 volts. One
of the simplest methods of protecting devices from flyback
voltages is to place a clamping diode across the inductive
load. Using this method, the diode will clamp most, but
not all, of the voltage transient. VOS will still overshoot
VOO by the sum of the effects of the forward recovery
characteristic of the diode; the diode lead inductance and
the paraSitic series inductances as shown in Figure 4-7.
If switching losses are significant, they should be
included at this step. Proceeding with the computation
of TJ,
TJC=
=
TJ =
=
500
100
200
300
400
VOS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
Po R/JJC
(63) (0.415) = 26°C
TC + TJC
80 + 26°C = 106°C
then the calculated TJ of 106°C replaces the original
110°C estimate and rOS(on), Po and TJ are recomputed.
Since the initial guess was close, 106°C is the final solution
and the transistor is operating within its thermal limitations
and, therefore, its current handling capabilities.
SSOA:
Switching Safe Operating Area defines the MOSFETs
voltage and current limitations durinjg switching transitions. Although an SSOA curve also outlines turn-on
boundaries; it is normally used asa turn-off SOA. As such,
it is the MOSFET equivalent of the Reverse Biased SOA
(RBSOA) of bipolars.
Like RBSOA ratings, tum-off SOA curves are generated
by observing device performance as it switches a clamped
inductive load. An inductive load is used because it causes
the greatest turn-off stress, but it must be clamped so as
not to avalanche the transistor with an uncontrolled drainsource "flyback voltage." Switching speeds, which directly
determine crossover times and switching losses, also influence the turn-off SOA.
As shown in Figure 4-5, the SSOA curve of the
MOSFET is bounded by its maximum pulsed drain current, 10M, and the maximum drain-source voltage, VOSS,
as long as switching times are less than 1.0 JLS. If
MOSFETs are operated within their 10M, VOSS and
TJ(maxl ratings, their SSOA curves guarantee that a secondary breakdown derating is unnecessary.
g
0
~
w
'"
J
Jq
Q
;>
w
'"~
0
;>
i!l
""0
'"~
"
0
Q
FIGURE 4-6 - vDS TRANSIENT DUE TO UNCLAMPED
INDUCTIVE LOAD
If the series resistance of the load is small compared
to its inductance, a simple diode clamp may allow current
to circulate through the load-diode loop for a significant
amount of time after the MOSFET is turned off. When this
lingering current is unacceptable, a resistor can be inserted in series with the diode at the expense of increasing
the peak flyback voltage seen at the drain.
Drain-Source Overvoltage Protection
The most common cause of failure in a power MOSFET
is due to an excursion across an SOA boundary. A good
portion of these failures are a result of exceeding the
maximum rated drain-source voltage, V(BR)OSS. Orain
voltage transients caused by switching high currents
MOTOROLA TMOS POWER MOSFET OATA
A-28
that the RC clamp network must absorb. From the power
and the desired clamp voltage, the resistance can be
sized. Finally, the magnitude of the capacitance may be
determined by relating the RC time constant to the period
of the waveform.
As an example, a similar circuit has the following characteristics:
>V
~
~
>'"
0
w
'~"
0
>
w
u
::>
0
'"
L
"!
= 10 /oLH
z
= 3.0 A (load current just before turn-off
~
0
= 25 kHz
FIGURE 4-7 -
VDS TRANSIENT WITH CLAMPING DIODE
Vc
=1/2U 2 xf=I.125W
P
The component values can be determined:
V~
= R = 3.2K = 3.3K
P
Let T = RC = 5.0 + f = 200 /oLs
C = 0.061 /oLF = 0.05 /oLF
While this is a common and efficient cricuit, the switching speeds of MOSFETs may produce transients that are
too rapid to be attentuated by this method. If the flyback
voltage reaches its peak during the first 50 ns, the effectiveness of the circuit will be undermined due to the forward recovery characteristic of the clamp diode and any
stray circuit inductance. It may be prudent in these cases
to include a zener with a breakdown voltage slightly higher
than the clamp voltage. When placed directly across the
drain and source terminals, the lead lengths are short
enough and the zener is fast enough to catch most transients. Since the zener's only purpose is to clip the initial
flyback peak and not to absorb the entire energy stored
in the inductor, the zener power rating can be smaller than
that needed when one is used as the sole clamping element.
A fourth way to protect power MOSFETs from large
drain-source voltage transients is to use an RC snubber
network like that of Figure 4-10. Although it effectively
reduces the peak drain voltage, the snubber network is
not as efficient as a true clamping scheme. Whereas a
clamping network only dissipates energy during the transient, the RC snubber also absorbs energy during portions
of the switching cycle that are not overstressing the transistor. This configuration also slows turn-on due to the
additional drain-source capacitance that must be discharged.
VDS TRANSIENT WITH ZENER CLAMP
Figure 4-9 shows an RC clamp network that suppresses
flyback voltages greater than the potential across the capacitor. Sized to sustain a nearly constant voltage during
the entire switch cycle, the capacitor absorbs energy only
during transients and dumps that energy into the resistance during the remaining portion of the cycle. Component values may be computed by considering the power
_
V (desired clamp voltage)
The power to be absorbed by the clamp network is:
Protecting the drain-source from voltage transients with
a zener diode, which is a wide band device, is another
simple and effective solution. Except for the effects of the
lead and wiring inductances and the very short forward
recovery time, the zener will clip the voltage transient at
its breakdown voltage. A transient with a slow dVDS/dt
will be clipped completely while a transient with a rapid
dv/dt might momentarily exceed the zener breakdown
voltage. These effects are shown in Figure 4-8. Even
though it is a very simple remedy, the zener diode is one
of the most effective means of transient suppression. Obviously, the power rating of the zener should be scaled
so that the clipped energy is safely dissipated.
FIGURE 4-8 -
= 60
20V/div
'"'J
+V
~
l!l
>
ul
'"
g~
~
::>
Sl
Z
~
Clamp Voltage, VC
Vos
0
o
600 ns/div
FIGURE 4-9 -
VDS TRANSIENT AND RC CLAMP VOLTAGE WITH RC CLAMP NETWORK
MOTOROLA TMOS POWER MOSFET DATA
A-29
•
No matter which scheme is used, very rapid inductive
turn-off can cause transients during the first tens of nanoseconds that. may be overlooked unless a wideband
oscilloscope (B,W. ;;;. 200 MHz) is used to observe the
VOS waveform.
consequently, their maximum di/dt capabilities have also
risen. Single die devices are now available with pulsed
current ratings greater tlian 100 A, and the multiple die
MTE100N06 has an 10M of 500 A.:ThevelYlarge di/dt
capabilities that accompany these current ratings can produ.ce significant VOS stress in addition to that observed
at the drain-source terminals.
To assure that the peak VOS at the chip does not exceed the maximum VOSS rating of the device, the following equation can be used:
+V
VOS(max) = V(BR)OSS - L(di/dt)
where VOS(max) is the maximum allowable voltage appearing across the drain-source terminals, V(BR)OSS is
the maximum device rating, L is the parasitic source inductance and di/dt is the rate of change in 10 coincident
with VOS(max)'
Voltages appearing across the package source inductance also affect the magnitude of the gate-source voltage
at the chip and are of such polarity that they slow both
the turn-on and turn-off transitions. If large currents are
being switched, the parasitic package inductance is large
enough to be the factor that limits the MOSFET's switching
speeds.
Except for circuits that produce very large di/dt's, the
proceeding discussion of package inductance is of academic interest only. However, wiring inductance is often
much larger than the package inductance and its effects
are proportionately greater. Therefore, the above considerations may become very practical problems in applications in which the di/dt's are not extreme. The quality
of the circuit layout dictates the degree of concem;
FIGURE 4-10 - VDS TRANSIENT WITH RC SNUBBER
Package and Lead Inductance Considerations
The drain and source parasitic package inductance can
influence the magnitude of VOS during rapid switching of
very large currents. In Figure 4-11, the drain and source
package inductance has been combined and placed in
the source because that wirebond and lead length accounts for tlie bulk of the inductance. The magnitude of
LS in the TO-204, (TO-3) and the TO-220 packages is
around' 7.0 or 8.0 nH and is large enough to produce
appreciable'voltage during a very rapid rate of change in
drain current. The polarity of the induced voltage is such
that the drain-source voltage appearing at the chip is
greater than that ,appearing at the device terminals.
As an example, assume that an MTM35N06 is turned
off in 50 ns after conducting 50 A. A di/dt of this magnitude
will produce about 8.0 volts across the parasitic package
inductance (v '= L di/dt = 8:0 nH 50 Al50 ns). If the drainsource voltage at the terminals is 50 V, then VOS at the
die is 58 volts.
dv/dtLlmitatlons in Power MOSFETs
Power MOSFET performance is eventually limited by
extremely rapid rates of change in drain-source voltage.
These very high dv/dt's can disturb proper circuit performance and even cause device failure in certain situations.
High dv/dt's occur during three conditions, each having
its own dv/dt threshold before problems arise. The first is
what is termed "static dv/dt" and occurs when the device
is off. A voltage transient across the drain and source can
be coupled to the gate via the gate-to-drain paraSitic capaCitance, Crss . Oepending on the magnitude of the gateto-source impedance and the displacement current flowing into the gate node (i = C dv/dt), the gate-to-source
voltage may rise above VGS(th), causing spurious turnon.
Obviously, for this case the dV/dt immunity of the device
depends to a large extent on the gate-to-source impedance. This underscores the importance of proper gate
termination to promote good noise immunity and is one
reason why operation of power MOSFETswith the gate
open circuited is not recommended.
With its gate shorted to its source, each of Motorola's
TMOS devices will withstand dv/dt's of at least 30 V/ns,
which is in excess of. values commonly seen in practical
applications.
'
If the gate-to-source impedance is high and a voltage
transient occurs between drain and source, spurious turnon is much more likely than device failure. Typically, the
, , " ":J-----
Gate
Terminal
~
Vosatdie=
VOS at terminals + vL
LS
~
B.O nH
+
Source Terminal
FIGURE 4-11 - VI'RY RAPID TURN'()FF INCREASES
DRAIN-SOURCE VOLTAGE STRESS
Although all power MOSFETs experience some internally generated voltages during rapid switching, peak
di/dt's are usually not extreme and the associated voltages are generally small. However, the current ratings of
power MOSFETs recently have inCreased rapidly and,
MOTOROLA TMOS POWER MOSFET OATA
A-30
transient will be coupled to the gate and cause the
MOSFETto begin its turn-on. But as VGS rises, VOS falls
and the dv/dt is reduced. Thus, the phenomena is selfextinguishing and generally is not destructive to any circuit
elements.
The second mode in which dv/dt may be of concern
occurs when the MOSFET is turned off and an extremely
rapidly-rising flyback voltage is generated. Since all loads
appear inductive at high switching speeds, the device experiences simultaneous stresses imposed by a high drain
current, a high VOS and large displacement currents in
the parasitic capacitances. Problems associated with this
"dynamic dv/dt" (so named because the device is being
switched off and is generating its own dv/dt) are evidenced
by device failure.
Unless extraordinary circuit layout techniques are used
- e.g., hybridized circuits that eliminate package and lead
impedance - maximum attainable dv/dt's in the dynamic
mode range from 10 to 45 V/ns, depending on the VOSS
rating of the device. Among the various product lines,
maximum turn-off speeds do not differ widely and the
attainable dv/dt is mainly determined by the magnitude of
the voltage that the drain can be switched through. Consequently, a 1000 V MOSFET can generate a greater
dynamic dv/dt than a 60 V device, regardless of die size.
All TMOS mask sets are tested and found to be immune
to self generated dv/dt's during very rapid, clamped inductive turn-off. The test circuit used has an extremely
tight RF layout, and the switching speeds and dv/dt's generated are assumed to be practical limits.
The third condition in which rapidly riSing drain-tosource voltage may cause problems is the most stressful
and probably most common. It occurs in bridge configurations wherein the drain-source diode is allowed to conduct current. Failures are usually catastrophic and are
limited to a specific set of conditions. The circuit in Figure
4-12 will serve as an illustration.
Assume the inductive load is being pulse-width mod-
ulated by 01 and 02 and that the intrinsic drain-source
diodes 01 and 02 provide the current conduction path
after the. MOSFETs are turned off. When 01 is turned on,
it establishes current 11. The load current (12) is commutated to 02 when 01 is turned off. If 01 is rapidly turned
on again while 02 is still conducting, dv/dt considerations
are in order. 02 may suffer damage because its diode is
conducting while it experiences a rapid rise in VOS.
Studies have shown that failures can occur at dv/dt's
in the range of 1.0 V/ns and are common to all MOSFETs
tested, regardless of the manufacturer. Since these
dv/dt's are not difficult to attain with power MOSFETs,
steps must be taken to ensure reliability.
Suggestions for circumventing this problem have already been introduced. One such topology is shown in
Figure 4-13. Obviously, the intent of this circuit is to eliminate the problem by not allowing the intrinsic diode to
conduct. However, the higher parts count, additional cost
and the voltage drop due to the diode in series with the
FET are all undesirable. Another solution is to limit the
dv/dt with snubbers or by slowing the MOSFET turn-on.
v+
~I
v+
Q1
~I
01
vFIGURE 4-13 - CIRCUIT TO ELIMINATE CURRENT
CONDUCTION IN THE MOSFET D-S DIODE
Protecting the Gate
The gate of the MOSFET, which is electrically isolated
from the rest of the die by a very thin layer of Si02, may
be damaged if the power MOSFET is handled or installed
improperly. Exceeding the 20 V maximum gate-to-source
voltage rating, VGS(maxl, can rupture the gate insulation
and destroy the FET. TMOS FETs are not nearly as susceptible as CMOS devices to damage due to static discharge because the input capacitances of power
MOSFETs are much larger and absorb more energy before being charged to the gate breakdown voltage. However, once breakdown begins, there is enough energy
vFIGURE 4-12 - TOTEM POLE CIRCUIT IN WHICH
DV/DT MAY BE CONCERN
MOTOROLA TMOS POWER MOSFET DATA
A-31
stored in the gate~source capacitance to ensure the complete perforation of the gate oxide. To avoid the possibility
of device failure caused by 'static discharge, precautions
similar to those taken with small-signal MOSFET and
CMOS devices apply to power MOSFETs.
When shipping, the devices should be transported only
in antistatic bags or conductive foam. Upon removal from
the packaging, careful handling procedures should·be adhered to. Those handling the devices should wear groundIng straps and devices not in the antistatic packaging
should be kept in metal tote bins. MOSFETs should be
handled by the case and not by the leads. and when
testing the device, all leads' should make good electrical
contaqt before voltage is applied. As a final note, when
placing the FET into the system it is designed for, sol-
dering should be done with a grounded iron.
The gate of the power MOSFET could stili be in danger
after the device is placed in the intended circuit. If the
gate may see voltage transients which exceed VGS(max),
the circuit designer should place a 20 V zener across the
gate and source terminals to clamp any potentially destructive spikes. Using a resistor to keep the gate-tosource· impedance low also helps damp transients and
serves another Important function. Voltage transients on
the draln.can be coupled to the gate through the parasitic
gate-drain capacitance. 'If the' gate-to-source impedance
and the rate of voltage change on the drain are both high,
then the signal coupled to the gate may be large enough
to exceed the gate-threshold voltage and turn the device
on.
MOTOROLA TMOS POWERMOSFET DATA
A-32
Chapter 5: Gate Drive Requirements
Power MOSFET Gate Drive Requirements
(if the gate is consid~red the positive electrode). When
the drain is "off" and is blocking a relatively high drainto-source voltage, Cgd is. charged to quite a different
potential. In this case the voltage across Cgd is a high
negative value since the potential from gate-to-source is
near or below zero volts and VDS is essentially the drain
supply voltage.
During turn-on and turn-off, these large swings in gateto-drain voltage tax the current sourcing and sinking capabilities of the gate-drive. In addition to charging and
discharging Cgs , the gate-drive must also supply the displacement current required by Cgd (igate = Cgd dVDS/
dt). Unless the gate-drive impedance is fairly low, the VGS
waveform commonly plateaus during rapid changes in the
drain-source voltage.
By dividing the switching transition into three distinct
periods, an accurate estimate of the switching speeds can
be obtained. Figure 5-2 illustrates the transfer function of
an MTP3N40. To reach a given operating point, the drain
current follows this transfer function as VGS increases
from zero to VGS(on)'
1. In Region I in Figure 5-2 and between times to and
t1 in Figure 5-3, the device is "off" and drain current is
essentially zero. Input capacitance is Ciss; this capacitance must ~ charged to VGS(th), the boundary between
Region I and II. At time t1 the device is just beginning to
turn on.
2. In Region II, which corresponds to the time between
t1 and t2, the device is in the transition between "off" and
"on." Drain current is controlled by 9fs, the device transconductance. Since VGS increases only slightly in
Region II, little additional charge enters Cgs . Drain voltage, however, falls from VDD to slightly above VDS(on)'
This, in effect, multiplies Cgd by the circuit voltage gain,
the familiar Miller Effect. Tile drive circuitry must supply
the displacement current to Cgd during the transition
through Region II.
3. In Region'" and between times t2 and Is, the device
is "on" and the drain-source impedance is mainly resistive. Drain current depends for the most part on VDS and
only to a lesser extent on VGS. Input capacitance is,
again, Ciss and must be charged to VGS(on)'
Bipolar power transistors have been around for decades
drive circuits for these devices abound. Power
MOSFETs are new arrivals. They differ from their bipolar
counterparts especially in their input characteristics.
These differences and their implications must be understood in order to insure that the MOSFET is operated in
an optimum fashion.
Driving a power MOSFET is tantamount to driving a
capacitive reactance network. Depending on the region
of operation, the input "sees" either Ciss, the CommonSource Input capacitance, or Crss , the Common-Source
Reverse Transfer capacitance. Ciss is the sum of the
gate-to-source capacitance, Cgs, and the gate-to-drain
capacitance, Cgd. Cgs , consisting for the most part of the
capacitance between the gate structure and source metal,
is relatively independent of voltage; Crss (Cgd) on the
other hand, is mainly the MOS capacitance befween gate
and drain region and increases sharply (Figure 5-1) for
drain voltages less than about 5.0 volts.
500
TJ = 25°C
400
~
z 300
'"
VGS = 0
\
f= 1.0 MHz
Ciss
c(
ti
c(
"5 200
\'.
Li
\
100
\
r--
o '--.
o
Coss
Crss
10
20
30
40
50
VDS, DRAIN·TO·SOURCE VOLTAGE (VOLTSI
FIGURE 5-1 - CAPACITANCE VARIATION
OFMTP3N40
The device capacitances, especially the reverse transfer capacitance, and the gate-drive source impedance
largely determine the device switching speed. Since the
MOSFET input capacitances vary significantly with the
die area, a given gate-drive will switch a smaller device
such as the MTP5N06 more rapidly than the larger
MTM15N40. However, two considerations complicate the
task of estimating switching times .. First, since the magnitude of the input capacitance, Ciss, varies with VDS,
the RC time constant determined by the gate-drive impedance and Ciss changes during the switching cycle. Consequently, computation of the rise time of the gate voltage
by using a specific gate-drive impedance and input capacitance yields only a rough estimate. The second consideration is the effect of the "Miller" capacitance, Crss ,
which is referred to as Cgd in the following discussion.
An example best explains why it influences switching
times.
When a high voltage device is "on," VDS is fairly small
andVGS is about 15V. Cgd is charged to VGS - VDS(on)
REGION I
I
I
I
I
I REGION III
I
I
I
I
I
1/
REGION III
(VDSlonl. Idol
I
I
I
I
/1
I
I
11
I
VGS(on)
VGSlltI)
VGs. GATE-TO-SOURCE VOLTAGE
FIGURE 5-2 - TYPICAL POWER MOSFET
TRANSFER FUNCTION
MOTOROLA TMOS POWER MOSFET DATA
A-33
II
II
the potential across Cgd is changing. This is an especially
demanding time for ttie gate-drive since Cgd is not only
acting as a Miller capacitance, but its magnitude is greatest at low drain-source voltages, as seen in Figure 5-1.
As soon as VDS ri,ses above 10 V (where the magnitude
of Cgd is smaller), the switching process accelerates.. Between t2 and 13, the drain-source voltage rises rapidly and
VGS falls only slightly. Except for abberations caused by
circuit parasitics, ID falls in accordance with the transfer
characteristics (Figure 5-5). For example, some of the
"drain" current shown in Figure 5-4 is actually flowing into
Cgd.
.,
The 200 V zener across the drain-source (Figure 4-8)
begins to conduct at t3 and rapidly diverts current from
the MTP3N40. Since VDS is no longer changing, the Miller
effect is no longer a factor and the gate-drive easily discharges Ciss between t3 and 4, completing the turn-off.
0--1'---(
to
FIGURE 5-3 - IDEALIZED RESISTIVE TURN-ON WAVEFORMS
Drive circuit requirements for the three regions may be
summarized as follows:
IG = Ciss· VGS(th)1I1 - to)
IG = Crss • (VDD - VDS(on))/(t2 -t1)
IG = Ciss· (VGS(on) -: VGS(th))/(t3 - t2)
Region I
Region II
Region III
Ciss and Crss can be determined from the Designer's
Data Sheet typical characteristic curves. For Regions I
and II, assume Ciss and Crss values at about VDS =
1/2 VDD. For Region III, assume aCiss value corresponding to VDS = VDS(on)'
The above relations assume no gate circuit resistance.
Adding resistance is an easy way to increase device
switching time. If it is desired to increase turn-on time
without affecting turn-off time, (for instance, to limit inrush
current to a stalled motor) the configuration below may
be used: .
~r*-l
VOS
I(~·II±. I
~1-
-
conversely, to minimize problems associated with very
rapid turn-off, such as large flyback voltages,the arrangement below will increase turn-off time without affeCting
turn-on 'time:
~r*o
20 nsIDlV
FIGURE 5-4 - CLAMPED INDUCTIVE TURN-OFF
WAVEFORMS OF AN MTP3N40
I~
~1-
1--
Just as they govern the turn~on process, the parasitic
capacitances and gate-drive impedance also dictate turnoff speeds. At faster switching speeds, turn-off waveforms
are particularly interesting because di/dt's are not limited
by load or wiring inductance.
The oscillogram of Figure 5-4 shows the turn-off waveforms of an MTP3N40. Between times to and t1, the
gate-drive decreases VGS from 11.5 to about 6.75 V,
which is the gate-source potential needed to maintain the
3.0 A load cu'rren!. Below that voltage the device begins
its transition through the active region.
Note that between t1 and t2 the progress appears to
be stalled. During this time VDS is beginning to rise and
VGS. GATE·TO·SOURCE VOLTAGE (VOLTSI
FIGURE 5-5 - TRANSFER CHARACTERISTICS
OF AN MTP3N40
MOTOROLA TMOS POWER MOSFET DATA
A-34
II
+15V
COMMON SOURCE SWITCHING
TTL Gate-Drives
Driving a TMOS power transistor directly from a CMOS
or open-collector TTL device is possible, but this circuit
simplicity is obtained at the cost of slower switching
speeds due to the charging current required by the
MOSFET's parasitic input capacitance and the limited
source and sink capabilities of these drivers.
A TTL device with a totem pole output and no additional
circuitry is generally not an acceptable gate-drive network.
In this case, the output voltage available is approximately
3.5 volts, which is insufficient to ensure the MOSFET will
be driven into the ohmic region. A slightly more promising
situation would be to use a pull-up resistor on the TTL
output to utilize the entire 5.0 V supply, but even the full
5.0 V on the gate would not guarantee the MOSFET will
conduct even half of its rated continuous drain current.
The open-collector TTL device, when used with a pullup resistor tied to a separate 10 to 15 V supply, can
guarantee rapid gate turn-off and ensure sufficient gate
voltage to turn the MOSFET fully on (Figure 5-6). Turrion is not as rapid because the pull-up resistor must be
sized to limit power disSipation in the lower TTL output
transistor. However, when concerned about dynamic
losses incurred while switching an inductive load, the gate
fall time is more critical than the rise time due to the phase
relationship between the drain current and drain-source
Voltage. Figure 5-7 shows a configuration providing fast
turn-on, yet reducing power dissipation in the TTL device.
When the lower transistor in the TTL output stage is
turned on, shunting the MOSFET input capacitance to
ground, modeling the bipolar asa saturated device may
not be appropriate. The current sinking capabilities of TTL
devices in the low output state is limited by the beta of
the pull-down transistor and its available base current,
which varies with the product line and TTL family. Table
1 shows the current source and sink capabilities of various
TTL families.
Although the TTL peak current sinking capability might
be twice the continuous rating, faster turn-off can be
achieved by using an outboard transistor to clamp the
gate-Io-ground (Figure 5-8). In this configuration, the bipolars are operating as emitter followers. As such, they
FIGURE 5-7 - OPEN COLLECTOR TTL-TMOS INTERFACE FOR
FASTER TURN-ON AND REDUCED POWER DISSIPATION
are never driven into saturation and their associated storage times do not significantly, affect the switching frequency limit.
CMOS Gate-Drives
Driving the power MOSFET directly from CMOS presents a different set of advantages and disadvantages.
Perhaps most important, CMOS and power MOSFETs
can be operated from the same 10 to 15 volt supply. A
gate voltage of at least 10 volts will ensure the MOSFET
is operating ,in its ohmic region when conducting its rated
TABLE 1 - TTL Output Current Source
and Sink Capabilities
Output Drive
J
Family
High (Source)
Low (Sink)
74LSoo
0.4mA
8.0mA
7400
0.8mA
16mA
9000
O.SmA
16mA
74Hoo
1.0mA
20mA
74SOO
1.0mA
'20mA
Voo
+5.0 V
-----+------, +15 V
FIGiJRE 5-8 - OPEN COLLECTOR TTL DRIVING
COMPLEMENTARY EMITTER FOLLOWER
FIGURE 5-6 - DRIVING TMOS WITH OPEN COLLECTOR TTL
MOTOROLA TMOS POWER MOSFET DATA
A-35
•
cOntinuous current. This benefit allows the designer to
directly interface CMOS and TMOS without any additional
circuitry including external pull-up resistors. Again, however, circuit simplicity results in slower MOSFET switching
due to the ilmited current source and sink capabilities of
CMOS devices. Table 2 compares the output current capabilities of standard CMOS 'gates to that of the CMOS
buffers (MC14049, 14050). Note that while the current
sinking capacity of the buffers is improved significantly
over that of the standard CMOS gate, the current sourcihg
capacity is not. The figures in Tables 1 and 2 indicate the
current at which the device can still maintain its output
voltage within the proper logic level for a given logic state.
As an illustration, with a VOS of 15 V, a standard CMOS
gate can typically source 8.8 mA in the HIGH state without
its output falling below 13:5 volts.
If the switching speeds of CMOS buffers are not rapid
enough, the discrete buffers suggested for use with TTL
devices (Figures 5-7 and 5-8) can also be used to interface
CMOS to TMOS. The only difference is the pull-up resistors are unnecessary for CMOS. Another difference in the
two technologies that may.affect the maximum switching
frequency limit is that the TTL gates typically have faster
switching times.
+13.5V
-04%:~- Duty Cycle; 10%
0~--~~~~n7.n7-~~~n7.~-t----
-1.5V
+10V
vGS
O--~~~~~~~~~~r-----~-
-5.0 V
RGURE 5-9 - VARIATION OF VGS WITH DUTY CYCLE
IN PULSE TRANSFORMER GATE-DRIVE
volts, the peak gate voltage falls below 10 volts and may
eventually drop to a point where the device is no longer
operating in the ohmic region. Increasing the primary voltage to 20 volts would increase the maximum allowable
duty cycle.
The basic pulse transformer topology of Circuit 1 also
has both maximum and minimum pulse width limitations
in addition to those imposed by the volt-seconds requirements. The current in the primary winding may. ramp-up
to excessive levels due to magnetic saturation, especially
in the smaller pulse transformers, if the pulse width is too
wide. On the other hand, very short pulse widths may
cause two different problems. First, transformer leakage
inductance may limit current sourcing capability during a
significant portion of the turn-on interval of a very small
pulse width. Second, the pulse width must be wide enough
to allow the magnetizing current (1m) to ramp-up significantly, because the stored energy (defined by the current
in the magnetizing inductance) provides turn-off drive to
the MOSFET gate. To eliminate the problem of 1m varying
with pulse width and to improve turn-off drive, the circuit
shown in Figure 5-10 may be used.
A modification to. the basic transformer gate-drive circuit
described above is the addition of a zener diode in series
with the clamping diode (Circuit 2). The zener allows ad-
Other Gate-Drives
In certain situations pulse transformers are an effective
means of driving the gate of a power MOSFET. They
provide the isolation needed to drive bridge configurations
or to control an N-Channel MOSFET driving a grounded
load. One of the simplest examples of such a circuit is
the first circuit in Table 3 where the rise, fall, and delay
times for this and the other circuits to be discussed are
tabulated.
The diode in Circuit 1 is present simply to limit the
flyback voltage appearing across the drive transistor Q1.
A transformer turns ratio of one-to-one was chosen to
provide an appropriate voltage at the secondary given the
15 volt primary supply voltage. A potential problem with
this circuit is that the duty cycle influences the magnitude
of VGS because the volt-seconds produced during the on
and off intervals at the secondary must sum to zero. Figure 5-9 indicates that increasing the duty cycle decreases
the maximum gate-source voltage. As the duty cycle increases above 33%, for the given primary voltage of 15
TABLE 2 - CMOS Current Source and Sink Capabilities
B-S.,i.. Gat.. IMC14001 CP)
Current
Source
Capability
Current
Sink
Capability
CMOS Buff.... IMC14049. 14060CP)
VDD
MinimA)
TyplmA)
MinimA)
TyplmA)
VOH ;2.5 V
5.0V
-2.1
-4.2
-1.25
-2.5
VOH;9.5V
10V
-1.1
-2.25
-1.25
-2.5
VOH; 13.5V
15V
-3.0
-8.8
-3.75
-10
VOL ;0.4V
5.0V
0.44
0.88
3.2
6.0
VOL ;0.5V
10V
1.1
2.25
8.0
16
VOL = 1.5 V
15V
3.0
8.8
24
40
MOTOROLA TMOS POWER MOSFET DATA
A-36
+v
during low duty cycle operation may be critical if efficiency
is a major concern.
Circuits 7 and 8 are similar versions of a circuit that can
be used as a high performance gate-drive. The base currents for the bipolar drives must be push-pulled as shown
in Figure 5-11. MOSFET turn-on is initiated during a positive transition of the input pulse. 01 is turned on, supplying the required base current for 03, which is Baker
clamped to minimize its turn-off storage time. Both circuits
have excellent turn-on times because of the low impedance path provided between the supply and the gate of
the MOSFET.
Turn-off occurs when the falling edge of the input pulse
is differentiated by the series combination of R1 and C1,
thus turning on 02. Base current is then free to flow into
04, clamping the gate-to-ground or a negative potential.
The duration of the clamping interval may be adjusted by
varying the RC network. Before the occurrence of another
input pulse, the MOSFET will remain off due to the 470 n
gate-source resistance.
Circuits 9 through 12 are examples of how TTL devices
may interface with the TMOS power MOSFET. The first
of the circuits, number 9, has a very simple interface between the open collector, Low Power Schottky SN74LS05
hex inverter and the MTP12N10. Turn-off speed is fair,
considering the circuit simplicity, but turn-on speed is poor
because of the large value of R1 needed to protect the
inverter from excessive power dissipation when the TTL
output is low. Putting three such buffers in parallel, Circuit
10, reduces all the associated switching times by a factor
of nearly two-thirds.
Another TTL device with an open collector output is
utilized in Circuit 11. Two of the six buffers in the SN7407
operate in parallel with only a pull-up resistor and the gate
of the MOSFET connected to -the collector of the high
voltage (30 volts) output transistors. The associated
switching times are quite respectable given the simplicity
of the drive circuit.
Another application of the SN7407, as mentioned earlier, is to use it to drive a discrete complementary emitterfollower buffer (Circuit 12). Lowering the pull-up resistor,
R1, increases the turn-on speed at the expense of increasing gate turn-off power dissipation.
Figure 5-12 shows an MTM12N10 being driven by a
CMOS MC14050CLHex Buffer. To obtain the maximum
output current source and sink capability, all six buffer
elements are paralleled.
While the pull-up resistor is not a necessity (as it is with
open-collector TTL devices), it does balance the current
source and sink capabilities of the CMOS buffer. Without
that resistor, one could expect slower turn-on but the drive
circuit would be more efficient because the CMOS device
no longer must sink the current drawn through R1 when
the CMOS outputs are low. Of course, fewer than the six
paralleled inverters could be used at the cost of slower
switching. Figure 5-13 shows the switching waveforms
without a pull-up resistor. For the six buffer elements in
parallel the peak IG during turn-on is about 350 rnA and
900 inA during turn-off.
While not as fast as other more elaborate drive circuits,
the MC14050CL offers an inexpensive single power sup-
FIGURE 5-10 - CIRCUIT TO ELIMINATE THE VARYING OF 1m
WITH PULSE WIDTH
ditional flyback voltage to appear across the primary terminal, when 01 is turned off. When this additional potential is induced across the secondary, it initially provides
greater reset voltage levels and, thus, more rapid gate
turn-off. Naturally, inherent in this circuit are the same duty
cycle, pulse width and frequency limitations that accompanied Circuit 1.
Circuit 3 is very similar to Circuit 1 except the gate
resistances are scaled upward and one is shunted by a
diode. The purpose of this configuration is to speed up
the MOSFET turn-on while leaving the turn-off slow in
comparison. While the MOSFET input capacitance can
charge rapidly through the diode, it must discharge
through the two relatively high impedance gate resistances. This might be done to minimize inductive flyback
voltage or any other undesired phenomena occurring during very rapid turn-off.
A variation of the push-pull converter is used to drive
the gate of the MOSFET in Circuit 4. When 01 is turned
on, the 10 volts across the lower of the two primary windings induces the same potential in N2. The voltage seen
at the secondary, due to the 2:1 step-down ratio (N1 +
N2/N3), equals the primary supply voltage. At turn-off, the
potential across N2 reverses and is clamped to the to V
supply by D1. Now N2 induces its voltage in N1 and the
potential appearing at the secondary reverses in polarity
but the magnitude is still 10 volts. If the pulse width is long
enough to generate sufficient magnetizing current, this
circuit yields good current sinking capabilities.
Two opto-coupled drive circuits are shown in Circuits 5
and 6. Circuit 5 is one of the most straightforward ways
of developing a low impedance gate-drive from the output
of the optocoupler. This circuit, however, is plagued by
long switching delays that limit the useful operating frequency. These delays are inherent in the optocoupler and
their magnitudes are affected by the phototransistor's output load impedance. If this impedance is lowered, as accomplished with Circuit 6, the gate-drive turn-off delay is
significantly lower. Besides the complexity of these circuits, especially Circuit 6, the gate-drive's bipolar output
tranSistor, 02, must remain on the entire time that the
MOSFET is off. The energy dissipated in these two drivers
MOTOROLA TMOS POWER MOSFET DATA
A-37
I
TABLEc3 - Switching Speeds
of Various TMOS Gate Drives
;s::
P
Tran~ormer
01"
J'1..
o
~
>
m
::IJ
;s::
~
Tum-off
Dalay
(Vin voV 2'
230
25
25
185
20
25
190
30
25
125
35
95
220
1250
60
35
640
230
1500
280
1100
220
340
660
230
15
85
35
15
90
30
50
Turn-off
Fell
Time
Tum-off
Rise
Time
-.
3:!
g
C3
:E
Tum-on
Fall
Time
Daley
(V in VIV,'
Turn'off
Dalay
(VinVaV"
v,"
Q
~
~
Turn-on
Daley
(Vin V1V2'
Tum-on
,Ri. .
Time
·V
Vl lV2
,·'5V
Circuit 1,
Simple Pulse
D.rain Switching Tim... (nl'
Gate Switching Ti",.. (nl'
Turn-on
N
Circuit 2
""df"
J"
Pulse
Transformer
w/Flyback
°
Yin
Zener
.n.
o
1 ..
410
01
~
»~
~
N
With
.,5V
p
Circuit 3
Pulse
Transformer
w/Speed-up
Diode
J1..
v,"
1:1
01
-
-
.Vl lV2
Diode
01
Without
Diode
01
TABLE 3 - Switching Speeds
of Various TMOS Gate Drives (continued)
Gate Switching Times (ns)
Turn-on
Delay
(VinvsV,)
Turn-on
Drain Switching Times (ns)
Ris.
Time
Turn-off
Delay
(V in vs V,)
Turn-off
Fall
Time
Turn-on
Delay
(V in VI V2)
Turn-on
Fall
Time
Turn-off
Delay
(V in VI V2)
Turn-off
Ri.e
Time
15
85
40
230
30
25
160
35
3900
460
1600
140
4000
80
1750
20
3700
420
450
120
3800
75
520
20
20
60
25
30
30
20
45
15
N
'f,'" 1
""~"
·11
Circuit 4
Quasi
-
Push-Pull
s::
18
"OV~
N1
Transformer
Drive
N3
470
vin\)--
JL
01
0
d
:0
1
0
):
.v
. / W. .,
v~rrl~ ~2 15:1
-I
s::
0
~
<0
en
"tJ
0
:E
vee
Circu~ 5
Standard
Opto-Coupling
Circuit
m
750
In
:0
s::
1
0
en
N
TI
Vee
-I
c
~
»
ffi
r
m
Circuit 6
HighB.W.
Opto-Coupling
Circuit
J-
100
fl
."
JL
0..::.
Vin
~~ ~,~
6635
01
03
0.1
...I~
VI
V2
350
220
1
N
Circuit 7
High
Performance
Push-Pull
Circuit
"6V
~ Q1~;YI
V2
220
JL
02
470
-
_I_
I
TABLE 3 - Switching Speeds
of Various TMOS Gate Drives (continued)
CircuitS
High
Turn-on
Dalay
IVinva V2)
FaU
Time
Tum-off
Delay
IVinvsV2)
Tum-off
Ri..
Time
70
40
25
85
15
60
600
480
1000
375
150
1800
30
210
180
310
140
50
710
30
140
60
60
130
30
Ri..
Time
Turn-off
FaU
Time
20
60
45
110
5000
45
25
.v
01
L.f"22
Vl
Push-Pull
Q2
V2
q
Performance
Circuit
Turn-on
Tur...,off
Delay
IVin vaV,)
Turn~on
1
'-15V
V;n
Drain Switching Tim .. Ins)
Gate Switching Tim.. Ina)
Turn-on
Dalay
IV in vs V,)
<\70
.
..n..
~
-v
~
>
'V
-I
s::
t
o
~
(g
:E
10V
CircuitS
116 SN74tS05
Low Power
Schottky
TTL
lV2
1.2 k
q
Yin
..n..
m
VI
:0
s::
~
!!l
o
»~
1
>V
Circuit 10
Paralleled
Low Power
Schottky
TTL
3/6 SN74LS05
~
390
v;n
.n.
8.
V2
~
VI
1
>V
Circuit 11
Paralleled
SN7407
Buffers with
Pull-Up
Resistance
q
~"
"v
~.
VI
216 SN7407
TABLE 3 - Switching Speeds
of Various TMOS Gate Drives (continued)
1
Turn-on
Turn-off
Turn-on
Turn-on
Time
Tum-off
Delav
(Vin vsV,1
Fall
Time
Delay
(V in vsV21
Fall
Time
Turn-off
Delay
(Vin vIV2)
Tum-off
Ri..
Time
Rl =2.0k
30
140
20
20
50
20
40
10
Rl =5.1 k
60
430
20
20
110
40
40
10
30
920
20
130
100
160
90
30
370
100
170
BO
280
50
230
15
Ri..
.v
15V
Circuit 12
SN7407 Buffer
Driving a
Complementary
Emitter~follower
Vl -
Rl
J1.
Yin
q
Drain Switching Tim.. (nil
Gate Switching Times (nIl
Turn-on
Delay
(Vin""V,1
V2
SN7407
~
Q
oJJ
o
>
~
~
~
(3
:E
lq
•.• MC1:: 'V
Circuit 13
Six Paralleled
CMOS Inverters
(MCI4049UBI
,
von .
200
V2
VI
m
JJ
~
fJ
"T1
~
o
»~
Circuit 14
Dual
Peripheral
Driver
(MCI472)
',5:,
c':·°r,V
l'V
~c-i: f25 !
V2
1472~q
:
,
JL ~ _
I
__ I--J
VI
*Transformer Specs:
Ferroxcube 3019P3CB
Nl =N2 = N3 = 10 Turns
#19 Trifilar Wound
Lp = 0.6 mH
II
II
+15V
+V
Jq
270
Vin
0.003pF
680
Rl
+15V
1.5 k
tN9t4
FIGURE 5-11 - PUSH-PULL BASE DRIVE FOR CIRCUITS 7 AND 8
ply device that interfaces directly to CMOS and MHTL
circuitry.
Figure 5-14 shows the results of the MTM12N10 being
driven by a single MC14050CL buffer element. Note the
time scale has been doubled to allow VGS to rise to its
upper rail. The gate current scale is a factor of four. smaller:
peak gate. currents of about 70 mA during turn-on and
240 mA during turn-off are seen.
Several ICs that were originally intended for other applications have been adopted by some circuit designers
looking for fast, yet simple and efficient MOSFET gatedrive schemes. One such device is the MC1472, a dual
peripheral driver, designed to interface MOS logic to high
. current loads such as relays, lamps and printer hammers.
Because each of the two output transistors. can sink 300
mA, MOSFET turn-off times are short when this. device
is used in a gate-drive network. Turn-on times are also
short in Circuit 14 because the value of R1 is so low that
it only minimally impedes the current during the charging
of the MOSFET input capacitances. The advantage of this
large current sourcing capability is once again offset by
the significant currents that will flow whenever the
MC1472 output is low to turn the MOSFET off. In fact, for
the 25 ohm pull-up resistor and a VCC1 of 15 volts, that
current approaches the combined sinking capabilities of
the two output transistors in that package.
The MMH0026 Clock Driver haS been designed to drive
high capacitance loads. It features a peak output current
of 1.5 A and transition times of about 30 ns when' driving
capacitance loads equivalent to the Ciss of a power
MOSFET. Input drive voltages for the MMHOO26 are compatible with Series 54174 TTL devices,such as the
MC7405 Hex Inverter (OC). Detailed information regarding transition times versus load capacitance and pOwer
dissipation can be found in the MMHOO26 data sheet.
Figure 5-15 identifies the MMH0026 driving an
MTM12N10. To illustrate the high peak gate currents that
can be sourced by the MMHOO26, no resistance was in. eluded between driver oiJtput and MOSFETgate. It is
important to remember that, with gate current transitions
occurring in the low nanosecond range, any lead inductance between driver and gate will add (URg) delay to the
gate circuit. Keep the distance between driver output and
gate terminal as short as possible when fast switching
times are important.
Vee = 15V
.---1>----~-O
25pF~
10VJL
r
0.1
FIGURE 5-12 - MCl4050CL HEX BUFFER AS A DRIVER
FOR POWER MOSFET
MOTOROLA TMOS POWER MOSFET DATA
A-42
3.70
25 V
1------0.4 A
IG---O
1------20 V
VOS--l0V
1------0
1------l0V
VGS--5.0V
1------0
100 ns/div
FIGURE 5-13 - POWER MOSFET SWITCHING WAVEFORMS
WITH MC14050CL HEX BUFFER
(6 BUFFER ELEMENTS IN PARALLEL)
1------+0.1 A
IG--'-O
1------0.·1 A
1-------'-20 V
VOS-'-'-10V
I--~---O
1---~--10V
VGS--5.0V
1-----0
200 ns/div
FIGURE 5-14 - POWER MOSFET SWITCHING WAVEFORMS
WITH MC14050CL HEX BUFFER
(SINGLE BUFFER ELEMENT)
MOTOROLA TMOS POWER MOSFET DATA
A-43
•
.-~~-------o25V
3:70
MMH0026CL
5:VJ-~rk
51 .
-
,
FIGURE 5-15 - MMHOO26 CLOCK DRIVER AS A
DRIVER FOR POWER MOSFET
the kick-back of the 3.7 ohm load resistor's parasitic inductance of about 90 nH.This drain voltage spike can be
limited by the insertion of an appropriately sized resistor
in series with the MMH0026 and the gate of the
MTM12N10, to increase the RgCiss time constant, if the
increase in turn-on time is acceptable.
Other examples of ICs that are used to drive the gate
of a power MOSFET are the MC1555 timer, the TL494
Input/output waveforms of the MTM12N10 are shown
in Figure 5-16. Although not shown, the maximum drain
current was 5.8 A. Figure 5-16 shows that 1.2 A gate
current spike that occurs during the turn-on phase, and
the 1.5 A negative current pulse occurring during the turnoff phase as Cgd is re-charged through the 3.7 ohm load
resistor by the 25 V supply. The high voltage pulse that
occurs as VOS rises towards 25 V can be attributed to
r------2.0 A
r------~-1.0 A
IG--O
\----------20 V
VOS-.-10V
\----------0
r--,--------, 20 V
VGS----10V
\---,----0
100 n./div
FIGURE 5-16 -
POWER MOSFET SWITCHII'lG WAVEFORMS
WITH MMH0026 CLOCK DRIVER
MOTOROLA TMOS POWER MOSFET DATA
A-44
,
pulse width modulation control circuit and the MC75451
peripheral driver. As power MOSFETs gain in popularity,
more drivers specifically designed for MOSFETs will appear.
Besides showing the MTP8N10 is not always the best
choice for a complement to the MTP8P10, the table also
indicates the die area of a P-channel device must be
approximately doubled to achieve the on-resistance of an
N-channel device with the same V(BR)DSS rating.
P-channel power MOSFETs can simplify certain circuit
configurations much in the same way that PNP blpolars
can. The circuit simplicity obtained when using P-channel
devices to switch a grounded load, for instance, may more
than offset the price differential between the N- and Pchannel devices.
In Figure 5-19 the source is connected to the positive
rail and the drain is attached to the load. As such, the
MOSFET is off when VGS = 0 V and begins to turn on
as VGS (a negative quantity) rises in absolute magnitude
above the device threshold voltage. Current would then
be free to flow from the source-to-drain and into the load.
Still, a logic signal, which is normally referenced to ground,
must be used to control the gate. A level shifter, followed
by a discrete emitter-follower buffer can supply the proper
logic levels while at the same time provide rapid MOSFET
switching. The NPN-PNP buffer could be omitted if slower
switching is desired.
HIGH SIDE SWITCHING
In some situations, connecting the load to the negative
bus is either convenient or necessary. In such instances
the switching element must be referenced to the positive
rail as shown in Figure 5-17. As with PNP and NPN bipolars, both P-channel and N-channel power MOSFETs
can perform this switching function. The following discussion of high side switching centers about the P-channel
in a common source configuration, and an N-channel
source follower as illustrated in Figures 5-17a and 5-17b.
All of the concepts presented also apply to the upper
switch (or switches) in totem pole or bridge configurations.
Figure 5-18 shows that 01 is essentially operating in a
source follower mode when 02 is turned off and is effectively out of the circuit.
P·Channel Power MOSFETs
To complement some of the N-channel devices,
Motorola also produces P-channel power MOSFETs. Because current carriers in the P-channel devices are holes,
which have lower mobility than the electron carriers of the
N-channel devices, the rDS(on) of P-channel MOSFETs
is always greater for a given die size and drain-source
breakdown voltage. This impedes the development of truly
complementary devices. For instance, if equal on-resistances are deSired, the unequal die dimensions will mandate differences in all die area dependent parameters
such as capacitances, pulsed current ratings, thermal resistance and safe operating areas.
The application will determine which of the device parameters - whether it be the on-resistance, drain-source
breakdown voltage, transconductance, etc. , - need be
matched closely. Table 4 compares the pertinent electrical
parameters of the MTP8P10 with those of N-channel devices that may be considered as device complements.
vFIGURE 5-17 - HIGH
SIDE SWITCHING
J
FIGURE 5-178 - P-CHANNEL IN
A COMMON SOURCE
CONFIGURATION
N-Channel High Side Switching
Instead of using a P-channel as the high side switch,
another choice is to use a less expensive N-channel
power MOSFET with the load placed in the source circuit
- a source follower.
Since there is no voltage gain in a source follower, the
gate voltage must equal the output voltage plus the gatesource voltage at that particular load current. Also, for
efficient power transfer, the source voltage, when
switched on, should approach the positive rail (limited by
rDS(on))' Thus, the gate voltage should be well above the
positive rail, i.e., VG = VGS(on) + Vs "" VGS(on) +
VDD. For hard gate turn-on, VGS should be greater than
10 V. Consequently, the gate voltage for a 12 V system
could approach 22 V. This higher than VDD supply gate
voltage can be achieved by several techniques:
vFIGURE 5-17b - N·CHANNEL
AS A SOURCE FOLLOWER
MOTOROLA TMOS POWER MOSFET DATA
A-45
FIGURE 5-18 - TOTEM POLE
NETWORK REQUIRES HIGH
SIDE SWITCHING
~
I
TABLE 4 -
CQmplements of MTP8P10
P~Channel
N-Channel
Units
MTP8P10
MTP8N10
MTP10N10
MTP12N10
Oraill-Sourco Voltage (Max)
100
100
100
100
Vdc
"' Continuous
Adc
8.0
8.0
10
12
I Pulsed
25
20
25
30
Adc
Max Power Dissipation
75
75
75
75
Watts
2.0 to 4.5
2.0to4.5
2.0 to 4.5
2.0 to 4.5
Vdc
0.4
0.5
0.33
0,18
ohms
10
Threshold Voltage
On-Resistance @ 10/2 (Max)
Transconductance (Min)
2.0
1.5
:/.5
3.0
mhos
Input Capacitance (Max)
1200
400
600
1200
pF
Output Capacitance (Max)
600
350
400
500
pF
Reverse Transfer Capacitance (Max)
180'
100
80
250
pF
Fall Time (Max)
150
120
150
150
ns
Rise Time (Max)
150
60
50
100
ns
Normalized Die Area
1.0
0.45
0.66
1.0
-
initiate turn-on. Inherent in .the circuit simplicity is the obvious. disadvantage of the' need of the second supply,
especially since its output must be greater than what is
commonly the system's high voltage bus. Another consideration is that turn·off switching speeds will be degraded due to the flyback voltage forward biasing the gatesource 'unless the load inductance is clamped with a freewheeling diode.
1. A separate gate supply at least 10 V greater than
VDD·
2. Pulse Transformer
3. Optocoupler
4. Bootstrapping
5. Voltage doubler
6. Inductive (flyback)
PULSE TRANSFORMERS
Pulse transformers are a very popular and practical way
of driving an N-channel MOSFET serving as the upper
element in a bridge network or as any other high side
switch. The beauty of the transformer drive is that the
gate-drive signal is easily referenced to the source of the
MOSFET, as Figure 5-21 illustrates. Circuits 1 through 4,
(page.A-38 and A-39) will perform just as well with the
load common to the source and the drain tied to the pos-
SEPARATE SUPPLY
The most straightfoward way to accomplish high side
switching with an N-channel MOSFET is to drive its gate
with a separate supply (Figure 5-20). The auxiliary supply
voltage must be from 10 to 20 volts greater than VDD to
+v
V}J~VOO
P-Channel
TMOS
+10V
FIGURE 5-19 - LEVEL SHIFTER FOR P-CHANNEL MOSFET
DRIVING A GROUNDED LOAD
J
Load
FIGURE 5-20 - HIGH SIDE SWITCHING USING
AN AUXILIARY SUPPLY
MOTOROLA TMOS POWER MOSFET DATA
A-46
+v
Cl
VFIGURE 5-21 - PULSE TRANSFORMER DRIVER
itive rail. Other considerations for pulse transformer gatedrive design 'are also addressed in that section.
FIGURE 5-23 - BOOTSTRAPPING CIRCUIT TO DRIVE
A GROUNDED LOAD WITH N-CHANNEL TMOS
OPTOCOUPLERS
A third way to drive a source follower is to reference
the gate-drive signal to the source of the MOSFET with
the aid of an optocoupler. Figure 5-22 is an example of
such a drive network. As long as the VCC2 supply and
the emitter of the optocoupler remain referenced to the
source, the load can be common to either the source or
the drain. The additional supply to power the output of the
optocoupler must be able to raise the gate voltage above
VOO. Either the supply must be isolated from the VOO
supply or must be generated from it with a bootstrapping
technique.
finite charge stored in Cl is eventually bled off. A second
problem is that this circuit cannot switch high voltages
since Cl will be charged to the system supply voltage
and then this potential will be impressed across the gateto-source. Fortunately, in applications that require
grounded loads, such as those in the automotive industry,
the supply voltages are often compatible with this method
of bootstrapping.
VOLTAGE DOUBLER
The gate voltage can be raised much higher than the
source or supply voltage by using a voltage doubler, as
shown in Figure 5-24. Voltage multipliers using diodes
and capacitors require an oscillator input of which a simple
and inexpensive method of obtaining this signal uses a
CMOS astable multivibrator, designed with a quad twoinput NOR gate MC14001. Gates Gl and G2 form the MV
and the parallel connected gates G3 and G4 serve as a
low output impedance buffer stage for driving the doubler
network. When these gates are powered with the same
VOO supply as the power MOSFET high side switch, the
output of the doubler (input to the FET gate) will approach
twice VOO, due to the voltage doubling effect of diodes
01-03, capacitors Cl , C2 and the input capacitance Ciss
of the FET switch. Obviously, VOO cannot exceed the
maximum voltage of the CMOS (+ 18 V).
If greater switch output voltage is required with increasing VOO, the CMOS supply can be zenered and more
diode-capacitor stages cascaded to raise the gate voltage.
With the component values shown, the astable MV will
oscillate at about 350 kHz. This signal and, consequently,
the switch can be gated ON and OFF by applying the
indicated control voltage to the second input of gates G3
and G4. However, due to the low power output of the
CMOS IC, switching speeds are quite slow - tens of
milliseconds - limiting this circuit to slow switching applications. Turn-off lime can be substantially improved by
BOOTSTRAPPING
The simplicity of bootstrapping makes that method the
one of choice if its limitations are inconsequential in the
specific application or they can somehow be circumvented. The bootstrapping circuit in Figure 5-23 generates
the required gate-to-source signal. One of the main problems with this topology is that the load cannot remain in
the on state for an unlimited period of time because the
Voo
~
FIGURE 5-22 - DRIVING A SOURCE FOLLOWER WITH
AN OPTOCOUPLER
MOTOROLA TMOS POWER MOSFET DATA
A-47
VOD'" 15V
MC14001
.. MTP12N05
68 k
RL
f = 350 kHz
30 pF
Astable MV
~
VCONTROL
Off
Cl
10pF
2.50
---, VOO
ovL On
FIGURE 5-24 - N-CHANNEL SOURCE FOLLOWER WITH VOLTAGE DOUBLER DRIVE
(MTP12N05), about 13 V gate-source(2B V gate-ground).
The series connected 15 V zener diode blocks the VDD
supply from reaching the gate of 02, when 01 is off.
With this amount of gate-drive, the VDSQf 02, under
a 6.0 A load, measured about 0.5 V, resulting in fDS(on)
of O.OB n. This calculates to about a 97% yoltage tranSfer
(94% power transfer).
As in the previous source·follower gate-drive circuit, the
power switch is enabled. by a zero logic level to one input
of NOR Gate G1.·For this circuit, however, turn-off switch·
ing speeds are much faster - about 0.15 ms ~ due to
the relatively higher power output of the converter gatedrive.
This type of gate-drive can also be used in totem-pole
(half or full-bridge) configurations, where the upper switch
is also essentially a source follower. For details, see the
Motor Controller Section.
employing an input capacitance Ciss discharging clamp
transistor. .
FlYBACK CONVERTER
Another circuit for raising the gate voltage well above
the supply voltage, one that uses a flyback conVerter, is
shown in Figure 5-25. The power switch used in this converter, an MTP3N12 power MOSFET (01), is easily driven
by the CMOS, 100 kHz; astable multivibrator (MV). This
circuit uses two of the Hex Inverter MC14572 gates (G1
and G2) as the MV with the remaining four inverters, in
parallel, providing the gate-drive to the FET, about 25 mA
peak to charge Ciss. When 01 turns on, the drain current
ramps-up to about O.B A and upon turn-Off, the flyback
voltage reaches about 60 V. This inductor stored energy
is then dumped into the diode-resistor-capacitor load circuitto provide the bias for the power FET switch 02
+15V
+15V
L
90 p.H
MC14572
+15V
+15V
~'ff"L OV
On
VCONTROL
100 k
-= al
. MTP3N12
f = 100 kHz
47 pF
FIGURE 5-25 - N-CHANNEL SOURCE FOLLOWER WITH FLYBACK CONVERTER DRIVE
MOTOROLA TMOS POWER MOSFET DATA
A-48
Chapter 6: Paralleling Power MOSFETs
mal coupling of the paralleled devices, provided that the
total heat sinking capability is not compromised by dOing
so. This will tend to minimize the differences in both case
and junction temperature. Before a worst case example
of these concepts can be examined, some knowledge of
the range of the variation of rOS(on) within production
devices must be obtained.
Unless devices are matched for identical onresistances, there will be at least a slight mismatch in their
individual drain currents. The worst case situation is obviously the paralleling of devices with the widest possible
variation in rOS(on)' Two wafer lots of the MTP8N18 were
sampled to obtain some idea of the range of variation of
rOS(on) within the same wafer lot and between wafer lots.
In addition to information on rOS(on), Table 1 contains
data on the parameters important to dynamic current sharing which will be addressed later. From this information,
one will have to design for a worst case rOS(on) mismatch
of 30%.
In some applications, the most beneficial characteristic
of the power MOSFET is its ability to be paralleled to
increase current conduction and power switching capabilities. Current sharing among devices is important in all
of the modes in which the MOSFET may conduct current.
These modes are:
1 -
Fully "on" during static conditions.
2 -
Switching applications including transient (turnon and turn-off) and pulsed conditions.
3 -
Linear applications.
4 -
Applications in which the drain-source diode will
conduct current.
Since the considerations for each case are quite different, each must be investigated independently before
the MOSFET can be regarded as a device that is easily
paralleled. The following sections show that the MOSFET
can be paralleled in each of the four modes provided
certain simple recommendations are followed.
TABLE 1 - Variation of rOS(on),gfs, and VGS(th) In
Two Water Lots ofthe MTP8N18
Static Current Sharing Design
Considerations
Although increasing junction temperature raises the
on-resistance and the conduction losses of the power
MOSFET, definite benefits are attributable to the positive
temperature coefficient of rOS(on)' If a portion of the chip
begins to hog current, the localized temperature will increase, causing a corresponding increase in the rOS(on)
of that portion of the chip, and current will shift away to
the cooler, less active, portions of the die. This trait accounts for the tendency of the device to share current
over the entire surface of the die's active region. Because
current crowding and hotspotting are eliminated under
normal operating conditions, there is no need to derate
power MOSFETs to guard against secondary breakdown.
The argument supporting current sharing within a device, due to the positive temperature coefficient of
rOS(on), is easily extended to the .case of paralleled devices. As within a single device with some imbalance in
rOS(on) over the die's active area, an imbalance or mismatch of rOS(on) between devices will cause an initial
current loading imbalance between devices. The resulting
rise in junction temperature and on-resistance of the device with the lowest rOS(on) will decrease that device's
drain current and will establish a more equal distribution
of the total load current in all paralleled devices.
While this tendency is definitely observable, its influence on the degree of current sharing is often overestimated. In the power MOSFET, the current sharing
mechanism is not triggered simply by high junction ·temperature, but by the difference in TJ between the low and
high rOS(on) devices. Oue to the generally small thermal
coefficient of rOS(on), this difference in junction temperature sometimes must be substantial to attain a high degree of current sharing.
Since the ultimate concern is for optimum reliability, the
emphasis should not be placed on obtaining large deltas
in TJ to force a greater degree of current sharing. On the
contrary, the effort should be focused on decreasing TJ
of the hottest device. This is accomplished by close ther-
rOS(on)
9"
VGSITHI
Sample
Max. Min. Max.
Size
Wafer Lot I
0.231 0.297 3.704 4.878 2.300 4.080
100
Wafer Lot I
0.239 0.305 3.571 4;878 3.685 3.910
50
Min.
Max.
Min.
• Maximum Rated rOSlen) is 0.4 ohms.
rOS(on) is influenced by the magnitude of the drain
current and the junction temperature. 10 and TJ are, in
turn, a function of the power dissipation, which is strongly
dependent upon rOS(on)' The quality of heat sinking and
thermal coupling between devices also affects 10 and TJ.
These interdependent relationships make an analytical
attempt to determine the degree of current sharing between several devices with a given rOS(on) mismatch
rather complicated. An example of an iterative analytical
process used to accomplish this end follows. The estimated 10 mismatch is somewhat dependent on the initial
assumptions.
Design requirements could include the following:
1. Maximum desired junction temperature is 125°C.
2. Sufficient heat sinking will be supplied to maintain a
90°C case temperature when TA = 35°C during
maximum power dissipation.
3. Assume worst case rOS(on) mismatch for the
MTP8N18 is 0.230 to 0.400 ohms @ 10 = 4.0 A
and TJ = 25°C.
From these conditions, the worst case variation in 10,
Po and TJ needs to be determined. First, the thermal
coefficient of rOS(on), CT, must be determined from the
on-resistance versus drain current curve (Figure 6-1).
In addition to assuming that CT is invariant with temperature and drain current, it is also supposed that thermal
coupling between device heat sinks is negligible. From
the maximum desired junction temperature (TJ = 125°C),
case temperature (TC = 90°C), and the junction to case
MOTOROLA TMOS POWER MOSFET DATA
A-49
II
•
0.8
~
e.
8
VGS
= 10V
0.6
~
~
.1"';'"
J
e 0.4
!
TJ
-
25°C
TJ
=
-55°C
,./'
V
= 100°C
T·
/
I.---
~ 0.2
o
o
4.0
V
--
8.0
12.0
ID' Drain Current (Amps)
rOS(on) I
. - rOS(on) ITJ = 25°C
.
TJ = 100°C
_ ""osIon) _
.
I
CT 10 = 8.0 A AT
100°C-25°C
= 0.47
- 0.32!l
75°C
= 0 002 nrc
.
16.0
FIGURE 6-1 - ON-RESISTANCE versus DRAIN CURRENT - MTP8N18
thermal resistance (ROJC = 1.67°CIW) of the MTP8N18,
the maximum power dissipation and case to ambient thermal resistance are eaSily calculated.
= TJ
P
- TC
ROJC
D
R
OCA
After two more iterations, the algorithm converges. The
results are tabulated for comparison with those of the low
resistance device in Table 2. In addition to the case of
negligible thermal coupling, the idealizedsituafion of perfect thermal coupling of the cases is also included for
direct comparison. The performance trade-off between
the two examples is that little thermal coupling will achieve
a greater degree of current sharing at the expense of
higher junction temperature in the hottest device (119°C
versus 12S0C). Since TJ(max) most directly influences
reliability, close thermal coupling of devices is encouraged. The manufacturer can best do this by paralleling
chips on a common heat sink.
= 125-90°C = 2096 W
1.67°CIW
.
TC - TA = 90-35°C = 2620CIW
PD
20.96 W
.
Attention is then focused on the device with the lowest
rDS(on) since it will be dissipating the most power. At a
TJ of 125°C its rDS(on), drain current, and VDS are:
'OS(on)1
TJ = 125°C
= 0.230
= 'OS(on)1
+
TJ = 25°C
+
TABLE 2 - . Static Current Sharing Performance of
Mismatched MTP8N18s
(TJ - 25°C) CT
(125-25) .002
= 0.430 0
10
.
=
- D- = J20.96
-- =
~
'OS(on)
0.430
Negligible The,mal
Case Coupling
6.98 = 7.0 Amp
rOSton)
rOSton)
rOSton)
rOSfon)
Min
Device
Max
Device
Min
Device
Max
Device
0.230
0.400
0.230
0.400
10 (Amps)
7.00
5.38
7.14
5.24
Po (Watts)
21.0
16.1
21;3
15.7
Steady State TJ(0C)
125
104
119
110
0.430
0.558
0.419
0.570
VOS = 10' rOS(on) = (7) • (0.430) = 3.0 Volts
·'OS(oni @ TJ
To determine the operating conditions of a high resistance device operated in parallel with a low resistance
device, an iterative technique must be employed. The
approach is to es,irnate the junction temperature of the
cooler device and from that, compute the rDS(on) at that
TJ, the current and power dissipated, and the new Junction
temperature. The computations are then repeated until
the process converges on the correct solution.
The first iteration proceeds as follows:
.
TJ = 100°C
= 0.400
Po
=
'05(on) I··
TJ = 2SoC
+ (100-2S) 0.002
'OSlooi @ Steady
State T J (ll)
A point essential to the above calculations is that the
steady state thermal resistance was employed to compute
the junction temperatures. For pulsed conditions ROJC
can vary significantly, and the transient thermal resistance
obtained from the thermal response curves must be used
to make this calculation. During switching transitions,
there is insufficient time to establish differences in junction
temperature and power MOSFETs may not current share
in the same manner.
+ (TJ - 2S0C) CT
= O.SSO!l
32
V2
= - - = - - = 16.36W
r05(on)
O.S50
L>TJC = Po' Rruc = 16.36' 1.67
= 27.33°C
Po' ROCA = 16.36' 2.62 = 42.87"C
TJ = L>TJC + L>TCA + TA = 27.33 + 42.87 + 35
= 25°C
(Ohms)
Fo,TJ = 100°C:
'OS(on)1
Perfect The,mal
Case Coupling
L>TCA =
= 10S.2°C
MOTOROLA TMOS POWER MOSFET DATA
A,50
~
Dynamic Current Sharing Design
Considerations
The term "dynamic" is broadened here to include not
only current during turn-on and turn-off, but also peak
current during narrow pulses and small duty cycles. Under
these conditions, not enough RMS current is present to
cause differential heating of the junctions which triggers
the tendencies of the devices to share current. Since the
argument supporting current sharing under static conditions is based on differe(1ces in junction temperature due
to an imbalance of power dissipation and drain currents,
that reasoning does not support the concept of current
sharing during dynamic conditions. However, even without
the benefit of the positive temperature coefficient, power
MOSFETs can current share reasonably well with simple
and efficient gate-drive circuitry.
The issues of greatest concern to those interested in
dynamic current sharing of paralleled MOSFETs are listed
and described in order below.
I
10
2Afdiv
I
VGS
10Vfdlv
50nsfdlv
1. Device parameters that influence dynamic current
sharing.
FIGURE &-28 -
PARALLELED TURN-ON
FIGURE &-2b -
PARALLELED TURN-OFF
10
2A/div
2. Variation of pertinent device parameters from lot to
lot.
3. Required device parameter matching to achieve
safe levels of current distribution.
VGS
10Vfdiv
4. The effects of switching speed on dynamic current
sharing.
5. The requirements and effects of circuit layout.
6: The possibility of self-induced oscillations.
50nsfdiv
Device Parameters That Influence Dynamic
Current Sharing
The device parameters that influence the degree of dynamic current sharing are the transconductance (9fs),
gate-source threshold voltage [VGS(th)I, input capacitance, and the on-resistance rDs(onl' However, the device characteristic that most accurate y predicts how well
paralleled MOSFETs will current share during turn-on or
turn-off is the transconductance curve, i.e., the relationship between the drain current and the gate-source voltage. To obtain optimum current distribution during turnon and turn-off, the ideal situation is to have all gatesource voltages rising (or falling) simultaneously on devices with identical transconductance curves. This combination would ensure that as the devices switch through
the active region, none would be overstressed by a current
imbalance. Figures 6-2a, 6-2b and 6-2c show the nearly
perfect degree of current sharing obtainable solely by
matching the 9fs curves. The current probe used induced
a 20 ns delay in the current waveform in the oscillograms
shown.
Since plotting the entire 9fs curve of each device is very
time consuming, matching VGS(th) or 9fs at some drain
current has been suggested as a simpler criterion for
matching paralleled MOSFETs. While much of the literature suggests the importance of matching VGS(th),
which is normally defined as the minimum gate voltage
at which a small drain current (usually specified as 1.0
mAl begins to flow, this does not accurately indicate the
10
2A/div
o
20l's/dlv
FIGURE &-2c - COMPOSITE ID WAVEFORM FOR
TURN-ON AND TURN-OFF
FIGURE 6-2 - INDIVIDUAL ID WAVEFORMS OF
FOUR PARALLELED MTP8N18s WITH MATCHED
TRANSCONDUCTANCE CURVES RESISTIVE LOAD (DRAIN CURRENT WAVEFORMS
ARE DELAYED 20 ns)
MOTOROLA TMOS POWER MOSFET DATA
A-51
..
I
Device #33/
12
!!l::>
10
...z
~
u
0
c
I
4. 0
4.0
/
2.0
o
4.0
./
7.0
9.0
10
11
VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)
FIGURE 6-3 -
5.0
6.0
7.0
8.0
9.0
10
VGS.GATE·TO·SOURCE VOLTAGE (VOLTS)
11
WIDEST VARIATION IN TRANSCONDUCTANCE
CURVES FOUND IN WAFER LOT I
.
Required Matching for Safe Levels of Current
Distribution
After characterization and determining the degree of
variation possible, the effects of matching or mismatching
the critical device characteristics can be observed. The
circuit used for this study is shown in Figure 6-5. Some
of the possible modifications of the circuit include adding
resistors in series with the gate to slow the turn-on and
turn-off, and a second MOSFET may be included to clamp
the gate bus to ground to observe the effects of very rapid
turn-off.
In this discussion of resistive switching, Figure 6-2 will
serve as a standard for comparisons since matching transconductance curves has achieved such good performance. Extreme care was taken to provide as pure a
resistive load as possible. The 1.6 ohm load was constructed from 39, 62-ohm carbon composition resistors
connected in parallel between two copper plates. Though
the drain wiring and load inductances were very small,
during rapid turn-on, the UR time constant of the circuit
may be the factor that limits the current rise times and not
the switching speed of the MOSFETs.
One of the worst case situations is to parallel devices
with greatly mismatched 9fs curves. Representing the
/
/
B.O
~
Obviously, the possibility of larger than expected variations in these pertinent parameters diminishes as the
number of sampled wafer lots increases. To get an adequate sampling of available devices, the user could characterize devices with different date codes or obtain units
from several distributors.
V
6.0
-~
RGURE 6-4 -
'/
5.0
Device #55
~rt
2. 0
#35, #52, #53, and #70 are naarly identical
I
6.0
W
lib
VI
0
Curves "for Devices
8.0
.9
I
J
/ I!/
0
Vos = 15V
Pulse Width = 80 ,a
TJ = 25°C
z
;i;
/J
12
16
~
:::;;
-
Device #64.1
I II Device #78
4
20
14
I
16
0
4.0
-
VDS = 15V
Pulse Width = 80,a
TJ = 25°C
8
Variation of Pertinent Device Parameters .
from Lot to Lot
Before any definitive statement may be made concerning the degree or type Of matching required for safe dynamic current sharing, the variation of pertinent device
parameters from 1.0t to lot must be known. Two wafer lots
of the NiTP8N18s, with sample sizes of 100 and 50 units
respectively, were characterized for this pupose. The
maximum and minimum values. of threshold voltage,
transconductance, and on-resistance are shown in Table
1. Figure 6-4 illustrates the widest variation in 9fs curves
within Wafer Lot I and is similar to the results obtained
from Wafer Lot II.
18
-
0
shape 9f the 10 versus VGS curve at higher currents.
Devices with 1.0 rnA thresholds that vary by as much as
2.0 volts do not usu~lIy, but can,. have nearly identical
transconductance curves above 100 rnA. Conversely,
those devices out'ora group of one hundred MTP8N18s
found to have the widest variation of 9fs curves had
thresholds that varied by only 4%. Therefore, for optimum
current sharing, the ideal solution is to use devices with
identical curves, and comparing thresholds may not be
the best way to achieve this.
Another simple, yet more consistent, method is to match
devices by comparing the maximum drain current they will
conduct at a gate voltage higher than VGS(th)' For example, all four devices shown in Figure 6-2 conduct an
10 of 4.0 A at a VGS of 6.0 volts and were found to have
nearly identical 9fs curves (Figure 6-3). Though similar to
matching thresholds, this method matches points on the
9fs curve that are more germane to the intended application of the devices.
TRANSCONDUCTANCE CURVES OF
MATCHED MTP8N188
MOTOROLA TMOS POWER MOSFET OATA
A-52
0.02 JLF
+20 V
Pulse
Generator
47
51
10
+20 V
51
'::'
100
0.001
1.0 k
4.7 k
FIGURE 6-5 -
DUT
DYNAMIC CURRENT SHARING TEST CIRCUIT
widest variation in the 9fs curves in Wafer· Lot I, Figure
6-4 shows the curve of a device that will begin to turn on
with a rising VGS slightly sooner than the other three
devices. It may be expected that device #33 will turn on
first and possibly fail due to current overload. However,
since the variation in the 10 versus VGS curves of these
mismatched devices is small, the failure will not occur. As
shown in Figure 6-6, parallel operation of these mis-
matched devices in the given circuit poses no significant
reliability hazard.
Matching the 1.0 mA thresholds does not guarantee the
nearly perfect results of matching the 9fs curves, as
shown in Figure 6-7. Although their thresholds were
matched to within 2%, these devices exhibited a fairly wide
variation in 9fs curves (Figure 6-8) which resulted in device #45 beginning its turn-off slightly sooner than the
10
10
2A/div
2A1div
o
50ns/div
FIGURE 6-68 -
50ns/div
FIGURE 6-6b -
PARALLELED TURN-ON
PARALLELED TURN-OFF
FIGURE 6-6 - INDIVIDUAL ID WAVEFORMS OF FOUR PARALLELED
MTPBN1Bs WITH MISMATCHED TRANSCONDUCTANCE CURVES
- RESISTIVE LOAD
MOTOROLA TMOS POWER MOSFET DATA
A-53
10
5A/div
10
5A/div
o
o
100ns/div
100ns/div
FIGURE 6-78 -
FIGURE 6-7b -
PARALLELED TURN-ON
PARALLELED TURN-OFF
FIGURE 6-7 - INDIVIDUAL 10 WAVEFORM OF FOUR PARALLELED
MTP8N16a WITH MATCHED THRESHOLD VOLTAGES
- RESISTIVE LOAD
Waveform/Curve Relations
Note: The order of the device numbers shown in all the current waveforms is important. The first number indicates the upper current waveform
in each group with succeeding curves corresponding to the following device numbers. The order of waveforms is identified to enable the reader
to correlate the devices' performance in the current waveforms to the devices' 9fs curves provided.
rest. The waveform photos again indicate that the performance of this group is also quite adequate. For comparison, the devices in Figures 6-9 and 6-10 have fairly
similar 9fs curves even though their 1.0 mA threshold
voltages vary by as much as 33%. Turn-on times for this
group are almost simultaneous while the turn-off is just
short of ideal.
Because the MTP8N18s of the two wafer lots were so
close in characteristics, the worst conceivable mismatch
that might occur could not be found. In order to study the
effects of such a wide disparity between parameters, an
MTP12N10 was paired with three closely matched
10
5A/div
VGS
10V/div
50ns/div
FIGURE 6-9b -
PARALLELED TURN-OFF
14
12
~.
:E
10
...z
~
10
5A/diV
~
a: 8.0
:::>
u
z
VGS
5V/dlv
8.0
Crss
(pF)
f
12
L'oo
}
J
.9
4.0
/
2.0
0
I
o
=
X =
A =
I =
I
~.750
Device #108 vciS(th) =
V
Device #117 VGS(th) = 3.800 V
Device #118 VGS(th) = 3.825 V
Device #130 VGS(th) = 3A70 V
L
~
L
5.0
6.0
7.0
8.0
9.0
10
VGS, GATE·TO-SOURCE VOLTAGE (VOLTS)
~
4.0
VOS=15V
Pulse Width = 80 p$.
TJ = 25"C
J.
Vas
5V/div
FIGURE 6-10 - TRANSCONDUCTANCE CURVES OF MTPBN1Bs
WITH THRESHOLD VOLTAGE VGS(th) MISMATCH
MTP12Nl0
Device #122
~
::;
/
/,
/
1/
10
$
I-
Z
~
8.0
~
6.0
az
0
.9
4.0
2.0
o
h
U
/
50ns/div
U
FIGURE 6-128 -
PARALLELED TURN-ON
FIGURE 6-12b -
PARALLELED TURN-OFF
Coincident 9f. Curves
ofthe MTPBN18s
Devices #52, #53, and #70
10
2A1div
VI
V
M
10
2A1div
,/ /
14
12
10 = 4.0 A
VGS = 15 V
(Volts)
1
14
!z
g§
VGS(th)
10 = 1.0 mA
(Volts)
VGS
5Vldiv
"OS = 15V
Pulse Width = 80 1'1'
TJ = 25"C
~
U
I
I
M
W
SOns/div
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
FIGURE 6-12 ~ INDIVIDUAL 10 WAVEFORMS OF AN MTP12N10
PARALLELED WITH THREE MTPBN1Bs - RESISTIVE LOAD
FIGURE 6-11 -TRANSCONDUCTANCE CURVES OF AN MTP12N10
AND THREE MTPBN1Bs
MOTOROLA TMOS POWER MOSFET DATA
A-55
•
10
2A/div
10
2A1div
Vas
5V/dlv
VGS
5V/div
o
500ns/dlv
SOOns/div
FIGURE 6-13a - PARALLELED ,TURN-oN
FIGURE 6-13b - PARALLELED TURN-OFF
FIGURE &-13 -INDIVIDUAL 10 WAVEFORMS OF AN MTP12N10
PARALLELED WITH THREE MTP8N188 - RESISTIVE LOADSLOW SWITCHING
current has been substantially reduced and the slightly
unsynchronized tum~off poses no threat to the MTP12N1 0
at these switching speeds.
ltis apparent that for this specific application, i.e., resistive switching' at moderate switching speed, device
matChing improves paralleled performance but is not necessary for safe operation. This recommendation will be
extended to include both fast and slow switching speeds
for both resistive and inductive loads provided certain circuit layout criteria are met.
not quite as predictable, rapid rt;lsistive switching also appears safe.
A comparison of Figures 6-12,6-13, and 6-14 indicates
that faster switching tends to improve dynamic current
sharing. This is.in part a consequence of switching the
devices through the active region at a much faster rate
and correspondingly decreasing any difference in switching speeds. The parasitiC source inductance also plays
an important role as discussed below.
Dynamic Current Sharing With Inductive Loads
The investigation of the effects of current sharing with
inductive loads was conducted using a fast recovery diode
(40 A, 400 V) placed in parallel with a135 ~H inductor
as a load. The diode was included not so much to protect
the MOSFET against flyback voltages, but to test the paralleled transistors' ability to conduct the large peak reverse recovery current required by the diode. The standard of performance is again set by devices with matched
9ts curves and shown in Figure 6-15.
Eff8cts of SWitching SpeE!d on Dynamic
.
Current Sharing
The gate-drive circuit used to switch the MTP12N10
and the three MTP8N18s was altered to either increase
or decrease the switching speed: The four 0.02~Fspeed
up capacitors were removed 10 determine the quality of
current sharing as the gate-source voltages rise or fall at
speeds that are fairly slow for power MOSFETs. The
MTP12N10 is the .first to tum on and the last to tum off
(Figure 6-13) due to the differences in the devices' 9fs
curves. During slow switching, the 10 versus VGS curves
can be used to accurately predict the 10 curves. For instance; the MTP12N10 begins to tum on when the composite'gate-source voltage waveform reaches 4.0 volts,
but the MTP8N18s hesitate until VGS reaches 4.5 volts.
Since the 10 waveforms are easily related via the 9fs
curves to the rising or falling gate voltages and the variation in thegfs curves over a product nne are fairly small,
slow switching of unmatched 1MOS power MOSFETs can
be a safe undertaking.
To judge the effects of rapid tum-of:!, a second MOSFET
waS added to clamp the gate-to-ground. This method
achieves the ·20 ns current fall, times depicted in Figure
6-14. During such rapid switching, the VGS and 9fs curves
can no longer be used to accurately predict device performance due to package and .Iead parasitics such as the
package source inductance. Once again however, these
mismatched devices performed well .as they were
switched very rapidly through the active region. Although
10
2A1div
VGS
10V/div
20ns/div
FIGURE 6-14 - iNDIVIDUAL 10 W! ns, the voltage appearing .across the parasitic
lead inductance is appr
'"
g
«
I
Devi
#1:~/ I
12
Device
#102
1
l
6.0
15
.§
4.0
Ii
2.0
o
U
"//
Protecting the Circuit From Self-Induced
~
Vos = 15V
Pulse Width = 80",.
TJ = 25"C
hV
M
~
~
U
I
I
U
W
Oscillations
Two of the most highly esteemed characteristics of the
power MOSFET can combine to Cause a problem in paralleled devices. Their high input impedance and very high
frequency response may cause parasitic oscillations at
frequencies greater than 100 MHz. This problem occurs
when all gates-are driven directly ·from a common node
as in th~circuit in Figure 6-19. Without individual gate
VG!;' GATE·TO-SOURCE VOLTAGE (VOLTSJ
FIGURE 6-16 - WIDEST VARIATION. IN TRANSCONDUCTANCE
CURVES OF 250 ADDITIONAL MTP8N18s
10
2A1div
VGS
5V /div
100ns/div
200ns/div
FIGURE 6-178 - RAPID TURN-ON SUPPLYING REVERSE
RECOVERY CURRENT OF FREEWHEELING DIODE
FIGURE 6-17b - SLOW TURN-ON SUPPLYING REVERSE
RECOVERY CURRENT oj: FREEWHEELING DIODE
10
2A/dIV
VGS
5V/div
20ns/div
200ns/div
FIGURE 6-17d - SLOW INDUC11VE TURN-OFF
FIGURE 6-17c - RAPID INDUCTIVE TURN-OFF
FIGURE 6-17 - INDIVIDUAL ID WAVEFORMS OF MISMATCHED
MTP8N188 SWITCHING AN INDUCTIVE LOAD
MOTOROLA TMOS· POWER MOSFET DATA
A-58
10
2A/div
10
2A/div
VGS
5V/div
VGS
10V/div
50ns/div
FIGURE 6-188 -
50ns/div
FIGURE 6-18b -
TURN-ON
FIGURE 6-18 -
EFFECTS OF IMBALANCED SOURCE INDUCTANCES ON
PARALLELED PERFORMANCE
resistances a high-Q network (Figure 6-20) is established
that may cause the device to oscillate when operating in
or switching through the active region. The device transconductance, gate-to-drain parasitic capacitance, and
drain and gate parasitic inductances have all been shown
to influence the stability of the circuit.
Although potentially serious, this problem is easily
averted. By decoupling the gates of each device with lossy
elements such as resistors or ferrite beads, the Q of the
circuit can be sufficiently degraded to the point that oscillations are no longer possible (note dotted resistors
shown in Figure 19). For the maximum switching speeds,
the value of gate decoupling resistors should be kept as
low as safely allowable. A value in the range of 10 to 20
ohms is generally sufficient.
A Practical ApplicaUon Load
TURN-OFF
shown in Figure 6-21. At a 50% duty cycle and a VOO of
44 V, the MOSFETs delivered about 450 W to the RC
load. To minimize the power that the drain-source zener
clamp must dissipate, MOSFET turn-off speed was limited
by the placement of an 82 0 resistor in series with each
gate.
Again, the performance of interest is that of mismatched
devices. In this· case, fifty units from a newly designed
mask set were tested for the widest variation in onresistance (0.255 0 to 0.230 0). The three highest
rOS(on) devices were grouped with the lowest rOS(on)
unit. Since a low rOS(on) usually indicates a high gis, the
transconductance curves of these devices were also mismatched.
The degree of current sharing among these four units
was well within safe. operating limits. As expected, the
lowest rOS(on) device carried the· greatest on-state current. For clarity, only the on-state currents of the lowest
and highest rOS(on) units are shown in Figure 6-22. The
currents of the other two devices were nearly identical to
device #8. As Figure 6-23 shows, the drain current of the
lowest rOS(on) device, #11, peaked slightly due to its
different 9fs curve.
An Inductive
To show the feasibility of paralleling power MOSFETs
in an application that imposes stresses typical of an inductive load, four MTP8N20's were paralleled in the circuit
Drain Bus
voo
Gate
Drive
Input
Source Bus
RGURE 6-20 - PARASITIC HIGH-Q EQUIVALENT CIRCUIT
OF PARALLELED MOSFETs WITHOUT GATE DECOUPLING
RESISTORS
FIGURE 6-19 - METHOD FOR DRIVING PARALLELED MOSFETs
USING GATE DECOUPLING RESISTORS
MOTOROLA TMOS POWER MOSFET OATA
A-59
+ 12·Volts
68
+~
Pulse
Generator
MUR830A
150pF
750
2.7 k
":"
MTP
8N20
(4)
820
(4)
2.2 k
510 pF
2.7
ISO
1.0kW
1500
p.F
1.0 k
":"
":"
470
":"
180,2.0 W
MJE200
MDSSIA
lN914
S6
1.0 k
":"
+ 12 Volts
FIGURE 6-21 -
CURRENT SHARING TEST CIRCUIT WITH AN INDUCTIVE LOAD
1. For static. current sharing, the current mismatches
.. are determined by the rOS(on) mismatch. A small
degree of guardbanding or rOS(on) matching will
ensure safe operation.
Each device was mounted on a separate heat sink, and
the case temperatures were monitored to detect any thermal imbalances. Because of its low rOS(on), theory predicts that the case temperature of deVice #11 will be
higher than the others. However, since the operating frequency was fairly high (40 kHz), the difference in switching
losses may have also influenced the temperature comparison. Whether it was due to a variation in rOS(on) or
9fs curves, the temperature difference was very small
(54.3°e for device #11 and 52.3°e for device #8) and did
not significantly affect device performance, i.e., the degree
of current sharing.
The following is a summary of recommendations and
findings concerning static and dynamic current, sharing
in paralleled power MOSFETs.
2. For dynamic current sharing, the turn-on and turnoff waveforms are largely determined by the transconductance curves. If matching is deemed necessary in a particular application, selecting devices
by comparing 9fs curves is the most accurate approach. A simple, yet adequate, substitute is to
match a single point on the 9fs curves at which the
devices conduct significant drain currents.
3. Increasing the switching speeds in symmetrical circuits tends to equalize the rate of current rise and
#8
#8
#11
#11
#8
#8
5.0,..
FIGURE 6-23 - ID TURN-OFF WAVEFORMS OF LOW
AND HIGH rDS(on) DEVICES - INDUCTIVE LOAD
FIGURE 6-22 - ID WAVEFORMS OF LOW AND HIGH
rDS(on) DEVICES - INDUCTIVE LOAD
MOTOROLA TMOS POWER MOSFET OATA
A-60
fall in paralleled devices due to the ballasting effect
of the parasitic source inductance.
relate no information concerning how the operating point
may vary within a given product line. For example, on the
transfer characteristics curve a desired quiescent drain
current of 4.0 amps may correspond to a gate-source
voltage of 5.75 volts in a typical device. This gate voltage
applied to an atypical device of the same product line may
result in a drain current that ranges from 2.5 to 4.5 A.
Matching device parameters is often proposed as a
means of ensuring some minimum variation in the Q-point.
This approach, especially using the threshold voltage, is
not the optimum solution. The gate-threshold voltage is
defined as the minimum gate-source voltage at which the
MOSFET conducts some small drain current, usually
speCified as 1.0 mAo On the scale that the transfer characteristics are usually drawn, this 1.0 mA drain current is
very small and the exact threshold voltage is indiscernable. It is not difficult to find two devices with nearly identical transfer characteristics that have thresholds that vary
by nearly 2.0 volts. Conversely, devices with matched
thresholds can have significantly different transfer curves,
usually due to a 9fs mismatch. Attempting to match devices by comparing transconductance or on-resistance
also gives little assurance that the transfer curves will be
similar.
If component screening is desired, the most direct
method is to actually compare each 10 versus VGS curve.
Since this is often impractical, one of two other courses
may be taken. The criteria for matching could be the drain
current at the gate voltage that is typical of the desired
quiescent current. Referring back to the previous example, one may select devices on the basis of 10 at a VGS
of 5.75 volts. The other solution, which completely eliminates any device screening, involves the use of source
resistors and is detailed in the next section.
Junction temperature is another important variable that
influences the quiescent operation point. Figure 6-25
shows that the 9fs curve of the.MOSFET can be divided
into two regions .. Below a VGS of 6.1 volts, an increase
in TJ increases
This is due to the negative temperature
coefficient of VGS(th) dominating the positive coefficient
of rOS(on)' As TJ rises, the threshold voltage falls and 10
increases despite an increase in rOS(on).
At gate-to-source voltages greater than 6.1 volts, the
temperature dependence of rOS(on) governs the change
4. The circuit layout should be as symmetrical as possible with respect to the gate-drive and the source,
gate, and drain parasitic inductances.
5. In all applications, the gates should be decoupled
with small resistors or ferrite beads to eliminate parasitic oscillations.
Paralleling Power MOSFETs In Linear Applications
Often lauded for their efficient high frequency switching
capability, power MO$FETs are ideally suited for a myriad
of switching applications. However, some of their other
less renowned characteristics also make them attractive
to designers of linear systems. Often the reason cited for
their use is the inherent ruggedness of the MOSFET as
evidenced by the lack of a second breakdown derating.
Another characteristic that is appealing is the high input
impedance that results in simplified gate-drive circuitry.
Also, the transconductance is nearly linear over a wide
operating range and its variation among devices in a given
product line is small.
Although these benefits are Significant, a method of
predicting and stabilizing the operating point is necessary
before linear operation ean be successful. In the following
sections a product line is characterized for the parameters
pertinent to Q-point variation in the linear mode. The effects of a source resistor on the operating point and the
small-signal transconductance are then discussed for single device operation. Finally, these concepts are extended
to include the case of paralleled devices with special attention paid to the degree of current sharing.
.
Device Characteristics Important for Operating
Point Stability
When developing a system that operates in the linear
mode, it is often either desirable or imperative to accurately fix the system quiescent operating point (Q-point).
The most pertinent graphs describing the operation of
TMOS Power MOSFETs in the linear mode are those
showing the output characteristics (Figure 6-24) and the
transfer characteristics, or transconductance curves (Figure 6-25). However, since these are typical curves, they
16
VGS= 20 V lOV:
/~
Irr
-T ~ V
,
o
2
25 c C
I
u
U
U
0
10
VOS, DRAIN·TO-SOURCE VOLTAGE (VOLTS}
FIGURE 6-24 -
TYPICAL OUTPUT CHARACTERISTICS
OF AN MTP8N20
t::t fL
A
0
5~ v -
t----' 'j) 100~C
II;
II
0
6~ v -
), V
u
TJ = -55 C C
7.0 V
V
II J/
vos= 10V
1
/~
o
6
~ ~ J.-.-c::: ~vGS= 8.0 v
LV~V
TJ= 25 C C
10.
/1/
..:::
~~
2.0
4.0
6.0
8.0
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
FIGURE 6-25 - TYPICAL TRANSCONDUCTANCE
CURVES OF AN MTP8N20
MOTOROLA TMOS POWER MOSFET DATA
A-61
10
•
in 10. Even though VGS(th) is falling as TJ rises, the effect
of the increase in rOS(on) begins to dominate, causing
10 to decrease. The temperature dependence of 10' necessitates the consideration of the effect that TJ has on
the Q-point, especially at low drain currents where the
percentage change in 10 is high.
line through the 9fs curve will indicate the drain current
at a given VGS. For instance, the device depicted in Figure
R-?7 will cnnnuct O.~75 A at a VGS of 4.7 volts.
If a source resistor is included, the abscissa represents
the gate-to-ground voltage (VGG). The relationship between VGG 'and 10 is determined by an RS load line
through a given VGG with a slope of -1/RS. Figure 6-27
shows that for an RS of 2.0 0 and a VGG of 5.45 V,
the a-point is fixed so that 10 is still 0.375 A. The effects
of varying the gate-to-ground voltage can be determined
by constructing parallel lines through the gate voltages of
interest. Changing the slope of the line graphically models
changes in RS.
.
To use the technique of employing a source resistor to
improve a-point stability, the worst case variation in the
9fs curves needs to be determined for the product line in
question. For this study, 350 MTP8N18's from the same
wafer lot were checked for the greatest difference in transconductance curves. The results are shown in Figure
6-28. With these curves; actually sizing RS and determining the gate voltage for a desired operating point (with
a defined allowable variation) is a very simple geometric
exercise.
Assume that the desired conditions are as follows:
Using a Source Resistor to Stabilize the Q-Polnt
Operating PQint stability can be improved without preselecting devices by using a source resistor. The placement of such a resistor provides degenerative feedback
to the gate by decreasing VGS by an amount proportional
to the drain current (Figure 6-26). Equations for the smallsignal transconductance and voltage gain with and without
the source resistor are derived In Table 4.
Determining the effect of a source resistor on the operating pOint of a power MOSFET is a simple geometric
exercise. The first step is to obtain, usually with a curve
tracer, the transconductance curve of the device in question. With no source resistance (RS = 0 0), a vertical
10 quiescent = 0.4 A
Allowable loa variation from 0.4 A is 0.05 A
TJ = 100°C
An RS load line drawn through points A and Band
extending down to the gate voltage axis determines both
the required magnitude of RS and the quiescent gate
voltage. The figure could also be used to show the effects
of swinging the gate voltage above and below the quiescent VGG. The dashed curves in Figure 6-28 represent
the transfer characteristics at a junction temperature of
25°C. Obviously, the curves vary enough to influence the
vGS = vGG- IORS
FIGURE 6-26 -
SOURCE RESISTOR SUPPLIES NEGAl1VE
FEEDBACK TO THE GATE
TABLE 4 - Equations for the Smail-Signal
Transconductance and Voltage Gain With and
Without a Source Resistor
WIth No
Source Resiltor
1.4
1.3
With A
Source Resistor
1.2
- ...!!Q.
9fs - 6VGS
1.0
~
9fs (6VGG -610RSI = 61 0
g§
=>
Vo~ag.
Gain
=~
6
g'fs RL
.9
=~
1+9,. RS
,5
,4
,3
6101gfs
:. Ay= -g,. RL
. A' =--=.!!L
.. v 119,.+RS
Circuits
VGG=V~1
' \ m = -1/2 = -IIR
,2
,1
VOOJ RL
I
I
o.7
i :.
9 Is- 6VGG -I+RS 9fs
Small Signal
\I
O.9
~ O.8
9fs 6VGG =610(1 +RS g,.)
A'y-
DEVICE #10~ _
TJ = 100'C
5
, _..!!JL_---IDL...
Ay= - 6VOS
6VGS
I
I
1.1
_ ..!!JL
9fs - 6VGS
Small Signal
Transconductance
J 1
VDD = 15 VOLTS
VOOJ RL
°4,0
1
VGGJ
+
RS
VGS- ~
V
V
4.4
:\!.R = 2,on
~ = lon l "{5.45Vj
4,8
5,2
5,6
6,0
VGG, GATE·TO·GROUND VOLTAGE (VOLTSI
FIGURE 6-27 - GRAPHICAL METHOD OF
PREDICl1NG THE EFFECT OF A SOURCE RESISTOR
ON THE QUIESCENT OPERAl1NG POINT
Primed numbers Indicate the effective values for the MOSFET and
source resistor combination.
MOTOROLA TMOS POWER MOSFET DATA
A-62
1.4
1.3 ' -
DE~'CE ~,OJ I
TJ
1.2
,
1.1
en
!IE
~
!z
tl!
~
0.9
O.S
I
1
~ 0.6
~ 0.5
I
0.3
U
I
r-
J
DEVICE #106_
I TJ = 25'C
I
[')C..B
/
I
~,
I
'I/
~,
0.4
o
I I I
/
0.7
u
O. 1
DEVICE #108
TJ = 25'C -
I ,I / ~EVIC~ #)06- f I IlTJ = 100'C
II ,
1.0
0.2
are operated in parallel in the linear mode, the second
would dissipate far more power than the first. Unlike
MOSFETs that are paralleled in switching applications,
the difference in junction temperature forces an even
greater disparity in the amount of current each device
conducts.
As explained earlier, at low drain currents the temperature dependence of the drain current is dominated by
the negative temperature coefficient of VGS(th) rather
than the positive coefficient of rOS(on). Consequently, the
device that is dissipating the most power will heat up,
carry more current and dissipate even more power.
Although the situation appears to be hopeless - very
wide variations in 9fs curves causing even greater differences in power dissipation - the use of source resistors
can minimize the differences and dramatically improve the
chance of success.
Using a source resistor to stabilize the operating point
of devices with widely differing 9fs curves is also applicable to improving current sharing among MOSFETs operated in the linear mode. If the a-points are closely
matched, then the paralleled devices will, by definition,
carry nearly the same drain currents and incur approximately the same power disSipation.
In this study, the devices with widest variation in 9fs
curves were paralleled in the circuit shown in Figure
6-29. Individual source resistances of 3.3 n were chosen
as a good compromise between a stable a-point and the
lower system gain are poorer efficiency attributable to an
increase in RS. Table 5 establishes the equations for 9fs
and small signal voltage gain of paralleled MOSFETs with
and without source resistors.
Figure 6-30 shows the results of pairing the devices
with the widest mismatch in 9fs curves. Note how the drain
currents can be predicted by relating the 9fs curves
(Figure 6-31) to the instantaneous gate voltage. Case
temperatures were also monitored, but the difference was
not as great as expected. While the device that carried
the most current ran hotter, it did so by only a couple of
degrees (83 versus 85°C). A difference of 5 to 1Q°C was
expected but did not materialize, most likely due to slight
variations in the heat sinks. The MOSFETs were mounted
on separate heat sinks, again to simulate a worst case
I
= 100'C
~ m = -0.375 - -I/RS
IV
1-... RS = 2.67 0
..... '" U
U
U
N
U
U
VGG, GATE·TO-GROUND VOLTAGE (VOLTS)
FIGURE 6-28 - USING A SOURCE RESISTOR
TO STABILIZE THE QUIESCENT OPERATING POINT
selection of RS if the device experiences large swings in
TJ.
Paralleling MOSFETs in the Linear Mode
In many applications using MOSFETs in the linear
mode, the quest is to obtain large swings in the load
voltage and utilize as much of the maximum drain-tosource voltage rating as possible. With a large quiescent
drain voltage, loa must be fairly small to keep the
MOSFET power dissipation within manageable levels.
Unfortunately, paralleling in the linear mode at a low
loa and a high Vosa is not as straightforward as paralleling in switching applications, for instance. Since this
is the most difficult and most common case of paralleling
in the linear mode, it is the one that is addressed here.
One problem is that at low currents the potential 10
mismatches, as a percent of the total load current are
much greater. As an illustration, one device may conduct
0.3 A at a VGS of 5.0 V, whereas a second device may
conduct 1.25 A at the same VGS. If these two devices
Voo =
110V
62.50
100W
VGSOAdjust
FIGURE 6-29 - CIRCUIT TO TEST CURRENT SHARING IN PARALLELED
MOSFETs OPERATING IN THE LINEAR MODE
MOTOROLA TMOS POWER MOSFET DATA
A-63
II
•
TABLE 5 - Equations for the Small Signal Transconductance and Voltage Gain of Two
Paralleled MOSFETs With and Without Individual Source Resistances.
With No
Source Resistors
With Individual Source
Resistors, RS
9f.l (dVGSll = dlOl, 9f.2 (dVGS21 = dlO2
9f.l (dVGG - dlD1 flSI + 9f.2 (dVGG - dl02 RSI =
dlD1 + dlO2
AIOl = 9f.l , dl02 = 9f.2
dVGS
dVGS
9f.l (dVGGI + 9f.2 (dVGGI = dlOl (1 + 9fsl RSI
+ dl02 (1.0 + 9fs2 RSI
dlOl + dl02 = 9f.l + 9f.2
dVGS
Small Si9nal
Transconductance
(9f.l + 9fs2)(dVGGI=(dlD1 + dI02)(1.0 + 9f8 RSI,
9f 1 + 9fs2 = dlD1 + dlO2
•
dVGS
:. 9fsT = 9f81 + 9fs2
A
Small Signal
Voltage Gain
where lIfs = 9fsl + 9f02
2
.,
_ ~.:. 9f81 + gf82
··9f.T - dVGG - 1.0 + iifsRS
_ ~dVoS
v- dVGS
= -dIOT RL
dlOT/9fsT
A'vT = -9'fsT RL
= -RL(9fs.l +9fs21
1.0 + iifs RS
:. AvT = -9fsT RL
Primed variables mdlcate the effective value for the MOSFET and source resistor combmatlon.
Subscript "T" indicates the total value for all MOSFETs in parallel.
condition. Close thermal coupling by placing units on the
same heat sink is recommended to minimize variations in
T C and TJ and therefore decrease any thermally induced
differences in 9fs curves.
The benefits of device matching are shown in Figure
6-32. The nearly identical drain currents were obtained
by matching devices by comparing the drain currents they
would conduct at a VGS of 4.7 volts and a junction temperature of 25°C. The slight mismatch at higher drain cur-·
- --I
i/fJ
--
1.0
0.9- DEVICE
#108
0.8
0.7
'0:6-'-~ '0]"-
a
I
-1--1.
-II-
.~
------~., ./- ~~ ... ...
/
0
4.0
VGG
1.0 V/div
4.4
I
TJ : lOO'C
RS: 3.31l
-
I
..,
/
____ ..9 0.3
-
II DEVICE #106
I
...
......
...
...
r-.....
4.8.
5.2
5.6
6.0
...
6.4
'~~Kr;J
U
FIGURE 6-31 - TRANSFER CHARACTERISTICS AND
RS LOADLINE OF MISMATCHED MTP8N18s
10
O.l·A1div
rents is mainly due to a small difference in 9fs curves at
a TJ of 100°C. The case tei1Jperatures of these two devices were essentially identical. The 20 n gate resistors
in Figure 6-29 serve an important function. The high input
impedance and high frequency capabilities of the
MOSFET present the possibility of self-induced oscillations in paralleled devices. Inserting small resistances in
series with each gate defuses the problem by degrading
the Q of the LC network formed by the gate-and-drain
inductances and the MOSFETs gate-to-drain capacitance. The magnitude of RS necessary to allow troublefree operation depends on the value of each of the circuit
parasitics. The circuit in Figure 6-29 oscillated with series
gate resistances of 10 n, but stabilized with 20 n. Increasing RS results in a more stable circuit at the expense
of lower bandwidth.
In conclusion, the same method used to stabilize the
operating .quiescent point of small signal MOSFETs can
Vos
20 Vidiv
20 p.S
FIGURE 6-30 - VGG, ID AND VDS WAVEFORMS OF MISMATCHED
MTP8N208 PARALLED IN THE LINEAR MODERS = 3.3 0
MOTOROLA TMOS POWER MOSFET DATA
A-64
MOSFETs were paralleled in the circuit shown in Figure
6-34. The test circuit (a complete schematic is shown in
Figure 11-19 of Chapter 11) was duty cycle controlled to
produce a continuous load current; thus, the com mutated
diode current indicated both the reverse recovery time trr
and turn-on time ton. The individual and total diode currents, as well as the driver drain current, were monitored.
To obtain some indication of a worst case condition, a
modest sample (20 pieces) of MTM20N15s were characterized for parameters that affect their paralleled performance. The forward on-voltage of the diodes at 10 A
ranged from 1.05 to 1.20 volts, and trr varied from 0.25
to 0.32 f.LS. Devices with the widest mismatch in parameters were grouped and tested in the circuit shown in Figure
6-34.
Testing indicated that current mismatches were small,
even in devices with the greatest difference in D-S diode
on-voltage. Figure 6-35 shows the current waveforms of
three paralleled diodes and the expected mild mismatch.
Also shown is a representation of ITOTAL, which is somewhat distorted due to the saturation of the current transformer that was used.
Current waveforms of devices with the widest variation
in trr are shown in Figure 6-36. Again, even though the
diodes are mismatched, the synchronized turn-on and
turn-off transitions illustrate the high degree of current
sharing that Occurs as the load current is com mutated
between the freewheeling diodes and the drive transistor.
VGG
1.0 Vld;v
10
0.1 Ald;v
Vos
20 Vld;v
20 ""
FIGURE 6-32- VGG, ID AND VDS WAVEFORMS OF MATCHED
3.3 0
MTP8N20s PARALLELED IN THE LINEAR MODE RS
=
be easily extended to linear applications of power
MOSFETs. After sampling a product line to obtain the
widest expected variation in 9fs curves, a simple graphical
technique can be used to accurately predict the Q-point ass0ciated with a given source resistor and gate-to-ground voltage.
Applications. of Paralleling MOSFETs
Paralleling Power MOSFETs in a Very Fast, High
Voltage High Current Switch
There are many applications requiring an extremely fast
high voltage, high current semiconductor switch, especially for device characterization, where the switch must
Since small variations in Q-point limit possible variations
in drain current, successful paralleling is also achievable
with this same method. The only additional consideration
is the need io limit potential self-induced oscillations with
individual gate suppression reistors.
VDD
Drain-ta-Source Diodes
The previous text on paralleling power MOSFETs has
shown the effects of parameter matching (or unmatching)
on the degree of current sharing when the FETs are operating in either switching or linear applications. However,
it has not described the effects on the paralleled drainsource diodes when these diodes are used as clamp or
free-wheeling diodes in practical applications. These
diodes can be used in multi-MOSFET switching applications (see Chapter 11 on characterizing D-S Diodes) when
the. diode switching speeds are commensurate with the
application. In a half bridge, as an example, the diode of
one FET prOtf;lcts the drain-source of the second FET and,
conversely, the diode of the second FET protects the first
FET. Whatever the circuit configuration, the equivalent
circuit reduces to that of a clamped inductive load,
whereby the drain-source diode is effectively across the
load inductance (Fi~ure 6-33).
When power MOSFETs are paralleled in switching applications, the question arises as to how well their intrinsic
diodes share the clamped current. To determine this, three
o':JLJ
FIGURE 6-33 - INTRINSIC D-S DIODE
CLAMPING AN INDUCTIVE LOAD
MOTOROLA TMOS POWER MOSFET DATA
A-65
II
II
VDD
Jq
FIGURE &-34 - TEST CIRCUIT TO OBSERVE
CURRENT SHARING OF PARALLELED D-S DIODES
IDIODE
5.0Aldiv
ITOTAl
20 Aldiv
0.5/LSfdiv
5.0/LSfdiv
FIGURE 6-36 - PARALLELED DIODE TURN-ON AND
TURN-OFF OF MTM15N20s WITH MISMATCHED Irr
FIGURE &-35 - DRAIN-SOURCE DIODE ON
CHARACTERISTICS OF THREE MTM20NI5s
WITH MISMATCHED D-S DIODE ON-VOLTAGES
be much faster than the device under test (OUT). Power
MOSFETs serve this function extremely well, but they are
presently limited in current capability. However, they can
be readily paralleled to increase the current, without using
current sharing ballast resistors, due to the inherent positive temperature coefficient of the drain-source ON-resistance rOSlon)' For example, if the transconductance
9fs of the FETs are unmatched, the FET with the highest
9fs would tend to take initially the largest drain current,
but due to the greater dissipation (l o2 rOS (on)) and resuiting temperature rise, rOS(on) would increase, thus, selflimiting the current. This process tends to. equalize the
drain currents of the respective devices.
A circuit for generating this fast pulse is shown in Figure
6-38. It uses 15 N-Channel power MOSFETs in parallel
as the output power switch to achieve the system capability of 150 A of peak, pulsed current. The FETs used
were unmatched TO-220 MTP5N4O(2.7 V < Vr.C:Uth) <
3.9 V) with 400 V blocking capability BVdss, 5.0 A continuous drain current rating (10 A pulsed) and specified
rOS(on) of 1.0 {1 max. The TO-220 devices lend themselves to efficient circuit layout and packaging (Figure
6-37).
The particular application for which this circuit was designed required the DUT to be referenced to ground (drain
circuit); consequently, the switch is powered with a negative, high voltage supply (- Vss) tied to the FETs
sources. Thus, .the ground referenced pulse generator
output must be level translated to this negative supply.
For fast switching, this translator must have the current
drive capability for quickly charging the power MOSFETs
input capacitances Ciss and reverse transfer capacitance
Crss . To accomplish this, two P-Channel MTP2P45's are
configured as a parallel connected, series switch. These
FETs are turned on by the. negative going input pulse
derived from a 50 V, 10 ns rise time pulse generator. A
MOTOROLA TMOS POWER MOSFET DATA
A-66
II
PARALLELED MOS
RGURE 6-37 - BREADBOARD LAYOUT OF THE SWITCH
ILLUSTRATING TIGHT PACKAGING CONCEPTS
up capacitor and protection zener diodes. The zener
diodes come into operation when high VSS ( -160 V) is
.used. When VSS is reduced to as low as 40 V, the gatedrive voltage dividers still provide adequate drive. For low
duty cycles « 1~0%), the resistors can be relatively low
wattage. The circuit can be operated within the blocking
20 V zener diode is used to protect the gate-source and
still allows adequate gate-drive for rapid switching of the
drain circuit. Connected to the drain is a cu~rent limiting
resistor R2 (with speed-up capacitor C2) feeding the 15
respective gate circuits (only circuits 1 and 15 are shown);
each circuit consists of a direct-coupled resistor, speed-
r
150
I
I
L
MTP2P45
017
(216)
200 II
2.0W
RL
0.911
430W
-160V
01
MTP
5N40
015
(2)
20V
LOW
1 N4747
20V
1.0 W
1N4747
60 ~F:r.+
350V _
:r.
FIGURE 6·38 - PARALLELED POWER MOSFETs 150 A SWITCH
MOTOROLA TMOS POWER MOSFET DATA
A-67
-vss
-160V
::=+
•
0-
Vo
50V
orv
10
50A
"'ffiV
05.0 p.sIDiv
FIGURE 6-38 -
50 ns/Div
FIGURE 6-39 -
SWITCHED VOLTAGE AND CURRENT
TURN-ON DRAIN VOLTAGE AND CURRENT
0-
vo·
50V
or;
10
~
Div
0-
50 ns/Oiv
FIGURE 6-40 -
TURN-OFF WITH CLAMP, RD
= 0
about 1.0 JLS (Figure 6-41 a) due to the time required to
discharge the FET's capacitances.
With the clamp, this time can be substantially reduced
(0.2 JLS) as shown in the photos of Figures 6-41b and
6-41c, the capacitance discharge limiting resistance RD
being 10 nand 5.0 n respectively. As this resistor value
is decreased, the FETwili turn-off faster, but consequently
be subjected to greater switching perturbations (Figure
6-40, RD = 0). Thus! the turn-off characteristics can be
somewhat tailored to the requirements.
Care. should be exercised in the layout of the fifteen
parallel FET's, especially with the gate-source drive circuitry. The fifteen FET's are mounted side-by-side with
the gates and sources tied to their two respective, parallel
run busses (Figure 6-37). Device lead lengths should be
made as short as possible and Ute source buss should
be RF by-passed at several points along its length to
minimize reactive effects.
Obtaining high power resistive loads with low inductance is a problem. For a pulsed current of 150 A and a
low resistance of about 0.93 n, the peak power would be
about 21 kW. Obviously, the dutv cvcle has to be very low
voltage capability of the FETs (to 400 V), but the passive
circuit elements should be scaled up accDrdingly.
To improve the turn-off switching times of the power
switch, the FET capacitance must be quickly discharged.
This is accomplished by the N-channel FET clamp 018
which, when turned on, supplies the .reverse gate voltage
to the power switch through the voltage storing effect of
C3 across R3. FET Q18 is turned on coincident with the
trailing edge of the input pulse by means of the differentiating network C1-R1, the derived positive-going pulse
supplying the gate-drive and duration for the clamp action.
The complete pulse-width voltage and current waveforms are shown in Figure 6-38 with the time expanded
turn-on and turn-off waveforms shown in Figures 6-39 and
6-40.
For these test conditions (VSS = -160 V, R1 "" 0.93 n),
approximately 150 A at 140 V (21 kW peak) was switched
in extremely fast times; the voltage turn-on time was less
than 10 ns and the current rise time being circuit inductance limited to about 250 ns.
Without the turn-off clamp circuit of 018 the drain voltage (and resistive load drain current) turn-off time was
MOTOROLA TMOS POWER MOSFET DATA
A-68
II
-
FIGURE 6-418 -
TURN-OFF ORAIN VOLTAGE RO
0
-0
= .,
FIGURE 6-41b -
TURN-OFF ORAIN VOLTAGE RO
= 100
-0
Vert. = 500 VIOiv
Horiz. = 500 ns/Oiv
FIGURE 6-41c -
TURN-DFF ORAIN VOLTAGE RO
= 5.00
for this application to avoid overheating the load resistor.
This resistor was fashioned with 216,200 n, 2.0 W, metal
oxide resistors sandwiched in parallel. This resulted in a
load resistor of approximately 430 W capability. Therefore,
duty cycles of less than 1.0% should be used to ensure
operation within the load rating while still offering good
oscilloscope viewing.
time is required between the switching transistors to avoid
simultaneous conduction. The duration of the dead time
and the dv/dt of the reapplied blocking voltage can be
critical, especially for some power MOSFETs. This complementary switch, with dv/dt adjustment and control of
the dead time, can help determine the capability of power
FETs in circuits when the above conditions are important.
Fast, Complementary Power MOSFET
Switch
Circuit Configuration and Operation
Two CMOS Ouad 2 input NOR gates (MC14001) are
used for pulse generation and signal delay. Gates A 1 and
A2 are configured as an astable multivibrator (MV), clocking the respective delay and pulse width monostable
MV's. The turn-on pulse is frequency (R1) and width adjustable (R4) whose output feeds, in order, cascaded
bipolar transistors 05, 06, power FET 07 and the NChannel output switch OS.
Pulse delay (R2) and width control (R3) for the PChannel switch (04) are obtained with Gates 81, 82, 83
and 84 which drives two cascaded bipolar transistors 01 ,
02 and power FET 03.
Transistor 09 drives power FET 010 as an optional
clamp to turn-off OS rapidly by discharging gate capacitance through a low impedance path. Duration of the
clamp interval is dictated by the RC differentiating circuit
in the base of 09.
The complementary output FETs 04 and OS consist of
four P-Channel (MTPSP10's) in parallel and four NChannel (MTP20N10's) in parallel. A limiting resistor RD
is shown in the drain of OS but may be in the drain of 04
or in both drains. The external load may be a test rectifier
Many present day semiconductors require test circuits
that can supply large pulsed currents and fast voltage
transitions.
In today's real world circuits, rectifiers are vital components in motor controls and in switching power supplies
as the operating frequency and power level increases.
Rectifier characteristics and selection can be critical for
these applications.
Due to its fast switching speed, the complementary
power FET switch, shown in Figure 6-42, is useful in measuring forward (tfr) and reverse (trr) recovery times of fast
recovery rectifiers, as well as for general uses requiring
a complementary power signal.
The internal collector-emitter diode in power Darlington
transistors and the drain-source diode in power FETs can
be of great interest to the circuit designer. Rectifier operation is dependent on several conditions, two of which
are the turn-off rate (di/dt) of forward current and the rate
of rise (dv/dt) of the reapplied blocking Voltage.
In some switching power supplies, a designed-in dead
MOTOROLA TMOS POWER MOSFET DATA
A-69
I
V+ '" 60 V
+16V
.20V
220
+15V
R3
,02
1.0k ~
500 k
Q4D
100
2N
3763
+15V
200 pF
- - - - - - - , OUT
+16 V 10 k
*
RL
470
100
s:::
~
tp(olllMV
200 pF
0
:D
0
~
":"
0
» en
'1l
..:...
10 k
DelayMV
RO
2N3906
~m
Q7
15k
+15V
*Ferrite
MTPBP10
Beads
:D
s:::
0
en
"T1
Off
I.mp.o'
~
m
":"
-l
200 pF
0
~
»
IFM
+15V
10 k
);
0
I
¥
':"
On
10 k
QBD
470 pF
Freq
510 pF
10 k
Control
-15V
1.0 k
A2(Clock)
B1(DeI.y)
B4(toff)
-.J
I
MCl4001
V- '" -50V
____ II
tp(ON) MV
+
Ql0
MTP10Nl0
L
_---'TlL---_ _ __
Turn-Off Clamp
A3(lon)
L-+
*Ferrne Beads
FIGURE 6-42 - FAST, COMPLEMENTARY POWER FET SWITCH
V-
or any other load requiring the unique drive characteristics
of this tester: fast, adjustable, complementary waveforms.
The negative output switch 08 (N-Channel) is capable of
switching at least 100 A, whereas the positive switch 04
(P-Channel) is limited to about 50 A due to the differences
in the respective on-resistances. Additional devices can
be paralleled for either switch for higher currents, if so
required. Also, power FETs with higher VOSS ratings may
be used.
ages have very fast leading edges (about 10 ns) and slow
trailing edges (about 3.0 ~ and 1.0 /Ls, respectively).
Figure 6-43b shows the same switched voltages but with
the clamp transistor (010) switched on. This discharges
08 gates through a low impedance path and speeds up
the trailing edge of the negative voltage to about 25 ns
instead of 3.0 ~.
In Figure 6-45, a MR821 fast recovery rectififer is shown
as the load, with IFM = 40 A, di/dt = 300 AI~, and the
dv/dt of the applied blocking voltage about 2500 V/~.
Adjustment of dv/dt is accomplished with R5 for the
positive switched voltage and with R6 for the negative
voltage.
Figure 6-44 shows the transition time of about 35 ns
between the negative and positive voltages, with both the
clamp on and with 04 diverting current from 08.
Output Waveforms
The negative and positive switched output waveforms
are shown in Figures 6-43a and 6-43b, with the positive
voltage delayed about 2.0 ~, in Figure 6-43a. The extemalload resistor RL is about 2.0 ohms, with the switched
voltages of about ± 42 volts.
In Figure 6-43a, the switched negative and positive volt-
Q4
04
Vaut
1Q1
div
Vaut
.19.Y.
0
div
0
08
os
5.0 JLSIdiv
5.0 JLSIdiv
FIGURE 6-438 -
FIGURE 6-43b - FAST TRAILING EDGE, NEG.
VOLTAGE, TURN-OFF CLAMP Ql0 "ON"
FAST LEADING EDGE
FIGURE 6-43 - NEGATIVE AND POSITIVE SWITCHED OUTPUT. VOLTAGE
WITH RL - 2.00, V- AND v+ ~ 42 V, DRAIN QS
IFM
20A
04
diV
Vaut
.JQ..Y. 0
div
os
50 nsidiv
50 nsidiv
FIGURE 6-45 - REVERSE RECOVERY (trr)
OF MR821 FAST RECOVERY RECTIFIER
FIGURE 6-44 - NEGATIVE AND POSITIVE
TRANSITION, DRAIN QS,
TURN-OFF CLAMP Ql0 "ON"
MOTOROLA TMOS POWER MOSFET DATA
A-71
II
II
Chapter 7: TMOS Applications
100 kHz Switcher
,Power FETs have proven themSelves' to be performance competitive and cost effective in flyback regulators
operating at 100kHz to 200 kHz.
The circuit described here proves the pOint: It is a
60 W 100kHz FET switcher with four output voltages
± 5.0 V and ± 12 V. It operates from 120 Vac, has an
efficiency of 75% and the total parts cost is approximately
of ripple occurs' at the outputs.' Power loss is less
than 0.5W.
Circuit DeSign
The goal of mostloW~power flyback deSigns is for reduced parts count (or size) and reduced cost. The 60 W
100 kHz switcher shown schematically in Figure 7-1, met
these requirements. At 100 kHz, the transformer size and
cost are, reduced by about 30% compared with a 20 kHz
design. Also, at 100 kHz, a FET can be driven directly
from logic circuits (100 to 200 mAl and still switch very
efficiently. This ,eliminates the need for drive interface circuits. The output caps used are' about 50% small,er and
they cost less as well. Finally, a relatively new three-chip
control system is used. It replaces an expensive and performance limited drive transformer with a lower-cost
optocoupler.
The FET is the control element for the flyback transformer and is directly driven from the MC34000 linear IC.
A rather standard off line starter circuit is used to initially
power the control circuit and this is also lower in cost than
the filament transformer supply which is often used to
power a single-chip system. The design procedure followed here was:
$35.
Components unique to this high frequency design include the following:'
• Motorola's MTP5N40 power FET. This 5.0 A, 400 V
device has only one ohm of on-resistance and is
driven directly from a linear IC. It not only switches
in less than 50 ns but has enough RBSOA to eiiminate the need for snubbers.
• Pulse Engineering's PE63133 power transformer.
This is a continuous mode flyback transformer which
is ideally suited to high frequency operation. Zener
clamps are not, required because the clamp winding
is interleaved With primary halves. Regulation of the
auxiliary ®tputs is within ±,10% under varying con'
ditions of line an~ loaq.
• Motorola's MC34060 Switchmode controllC, 4N27
optocoupler, and, MC1723 linear regulator. These devices are used in apractical demonstration of a lowcost, threecchip control system. The MC1723 is the
error amplifier, the MC34060 is a fixed frequency
PWM, and the AN27 couples the feedback signal
from the MC1723 to the MC34060.,
1. Design and test the power stage.
2.Add and stabilize the control loop.
3. Change from de to ac power.
The FET waveforms obtained with the design are
shown in Figure 7-2. The exceptional switching speed of
the FET can be varified here (less than 50 ns) and ringing
on the current waveform is due to the layout which includes a current-sense loop and noise pickup on the
scope probe.
The input capacitor does not reduce in size like the
outputs because it is needed for energy storage which
still occurs at 60 .Hz. Noise filters used here include a
toroid from PE and the economical 41 GS series of tan-
• Motorola's MBR1 035 (TO-220) Schottky rectifier was
used to rectify the + 5.0 V output at h£:!lf the cost of
a comparable 00-4. Similar cost savings resuit from
using the TO-220 fast recovery rectifiers, i.e., the
MUR805 in the ± 12 V outputs.
• Mepco/Electra's 3428 series of output capacitors.
These high frequency electrolytics feature iow ESR
and highRMS current ratings: Only 50 to 70 mV (PP)
Flvback
Transformer
160 Vdc
120
Vari
+12V
Start
Circuit
-,
I
I
I
I
I
L... _ _ _ _ _
.J
I
I
IL ___________ _
":"
FIGURE 7-1 - REGULATOR BLOCK,DIAGRAM
MOTOROLA TMOS POWER MOSFET DATA
A-72
I
I
I
I
__________ .JI
t-igure 7-3. The first chip is an MC1723 linear regulator.
It is used here to provide a 5.0 V reference and an error
amplifier. It is powered from the + 12 V output winding
and receives feedback or control signal from the + 5.0 V
output. The MC1723 drives the second chip, a 4N27 optocoupler. The coupler maintains isolation between the
primary and secondary windings and couples the dc control signal to the input of the third chip, a MC34060. The
MC34060 performs a fixed frequency pulse width modulator (PWM) function and is used to directly drive the
FET power switch which is connected to the primary or
energy storage winding.
The key regulating blocks are the 0 to 3.0 V sawtooth
oscillator and the feedback comparator. As the feedback
Signal is raised from 0 to 3.0 V, it gradually narrows the
on time of output pulse coming from the comparator. During start up, the feedback is missing and resistor divider
network controls the second or dead-time comparator to
ensure that on time cannot exceed 45%. This, and the
soft start capacitor, prevents transformer saturation problems during start-up. Pull down of the gate voltage is
accomplished as shown in Figure 7-3 with the addition of
a low cost TO-92 PNP transistor (03). In this design, the
MC34060 is started off line with the addition of a 200 V
transistor (02) and 12 V zener as shown in Figure 7-4. It
ultimately (at normal line voltage) runs off the 12 V auxiliary winding which back biases this transistor. Because
it and the FET gate draw so little current from the line,
about 20 mA, undervoltage inhibiting common to bipolar
designs was not required here and this current becomes
functional and runs safely when the input reaches 40 Vac.
The performance of this 100 kHz switcher is similar to
most others. It is relatively easy to keep output ripple, both
talum capacitor from M/E. The 12 V output rectifiers were
Motorola's MURB05 ultrafast recovery button rectifiers
which are housed in a TO-220 package. They were ideally
suited to this relatively high current (10-15 A peak) application because the correct amount of heat sinking was
easily attained by simply bolting a fin to the tab.
The relatively new MBR1035 TO-220 Schottky rectifier
is the best choice for rectifying the 5.0 V output. It is about
half the cost of the equivalent 00-4 version, a 1N6095.
The overall efficiency of this regulator (including the
control circuits) is 75%. As usual, most of the losses are
associated with the power handling components as noted
in Table 1.
TABLE 1 -
Efficiency Data
1. Input Power
PA
PF
96
95'
100%
56%
+12.0
8.0
13.2
21.5
-12.0
8.0
13.3
22.0
Fast Recovery (both)
Misc.
8.0 W
5.0 W
Vln
160 Vde
120 Vae
lin
PPRMS
0.6 A
96
1.4 A
170
'Note using Clark-Hess wattmeter.
2. Output Power
Winding
Load (ohms)
Voltage
Power
3. Efficiency
Elf. = PdPln
5.0
1.0
5.1
2.5
-5.0
10.0
5.1
2.6
= 72 W/95 W = 75%
4. Estlmeted Losses
FET
4.0 W
SchoHky
4.0 W
Transformer
2.0 W
The control loop contains three chips as noted earlier.
The functional diagram of this arrangement is shown in
10
11.0 AlDIVI
Vos
1100 VIDIVI
Vos
1100 VIDIVI
VGS
15.0 VIOIV)
Vos
1100 VIDIVI
0.5 AlOIV
10
11.0AlDlV)
t
10
VGS
15.0 VIOIV)
Vos--
50 V101V
FIGURE 7-2 - FET WAVEFORMS - 120 Vae, FULL LOAD
MOTOROLA TMOS POWER MOSFET DATA
A-73
II
160 Vdc
Secondaries" + l2V
T1
I
I
I
I
I
I
Signal
Error
Amplifier
L __ '- ____ ~------J
Pulse Width,.
Cantrall.C.
'::"
4N27
Optacoupler
FIGURE 7-3 - THREE CHIP CONTROL SYSTEM
T1 Pulee Eng......I""
#PE83133
OYtputCapacltors
111720 & 1000 p.f
WE 3428 Series
all 10 pFTantelum
MIE 41G5 Sarles
L1-PE51590 -12p.H, S.OA
L2.1.3-PESl591 -20,di,2.0A
2.0 A
01
Tl
AlternateT1
Ferroxcube Ec-41
Gap 30 mils, l.3mH
Prim
70T #24 (2 layers)
Clamp
roT #28 (1 layeI')
:!:12V
8T#20Bifylar
::!:5.0 V
4T #2(1 Quadfylat
12 V Aux 8T #20
__=
L3
rvV'\__.....__-o
-12V
02
MDA
'-__...__-+-__JYY"I__-+-______....__-o
+160V
202
D6
r -__"'I-~
+12V
220pF C2
310p f
200 V
2.0W
+12 VAux
MTP
5N4O
ca
C12
R5
o~
lOOk
l,OW
2.0 kV
':'
1N5242
08
12V
lOOk
All
Al0
pF
C14
51 k
10k
0.1
~
______J22kL-________________________~
FIGURE 7-4 - 100 kHz FET REGULATOR
MOTOROLA TMOS POWER MOSFET DATA
A·74
A16
1k
T
C1 •
10pF
~
Tl
1t5\ II~
115 Vac
±20%
.
..
1.0 A
+
1'330 ,
35 V
'f?o'
1/
0~~1
t:l
•
VCC
2
....
22 k
MC
34060P
3
0.1
I
~+
Vref
Dr CT
RT
~~PS::; qoi
G~
Ll
"
200
47 k
+"
r-1.0 +
510,
~Sk
:--n
11 k
Pout
FIGURE 7-5 -
5.0V
RET
+12 V/O.S A
";. r' 10
t " 1000
I
I
I
I
+ I
lN4933
r
lN4933
Vo
TL431CLP
~L3
A5S
27 k
+1 0.0
" 1OV
+
±12V
RET
[' 10
-12 V/O.S A
r-------.,
E 8
~
I~
33 k ,
--L4
Ul
13
4.7 k
4.7 k
Fl ~(
1.Ok
+ ,,1.0
+
1000, "
·;N4:'34
cJ
10
~+
33 k
-"
;;;;;;;;;;;;;;;
100
lN4934
•
67)4N3S
..
+
2200::;
10V
T3 •
470
i" 200 V
~//
1/2
4.7 k
--L2
1/24N36
lN4002
+
<1.0I'H
MBR1035
lN4003
~
~
I
L
•
~II!
L
---,
I
~tr'
13005 :
47
I
1/2W
:
fo~Ol
~
lN4937
I
I
IL _____________ ...JI
20 kHz SWITCHING POWER SUPPLY USING A BIPOLAR SWITCH
Unless otherwise noted:
All nssistors are 1/2 W
All capacitors rated 25 V
Transformer Data
T1 :
Internal power supply transformer for switching regulator
TRAIO F90X Primary -
T2:
Black-red and black green. Secondary -
Core:
Windings:
Ferroxcube 768Tl83-3C8
Primary
-
Secondary T3:
L2:
1 turn, #26 Awg. lead from primary of T3 looped through
center of T2, note dots.
100 turns, #28 Awg.
High frequency output transformer
Core:
Coilcraft 11-464-16, 0.025 gap in each leg.
Bobbin:
Coilcraft 37-573
Windings:
Primary
-
Secondary -
L1:
Blue and green
Collector current sense transformer Coilcraft 01870
2 windings 75 turns each, #26 Awg, bnilar wound.
One winding is connected to the MJE13OO5 and
the second is connected to the 1N4937, note dots.
5.0 V, 6 turns, #16 Awg.
12 V, 14 turns, #22 Awg, Milar wound.
r---j-l
Base drive inductor
Core:
Nolie
Bobbin:
Ferroxcube 1408Fl0
Winding:
39 turns, #28 Awg., 10.5 I'H
Ul
~~!
S6~ i
I
I
I
_______ ...JI
5.0 Volt output filter inductor
Coilcraft Z7156, 15 I'H at 5.0 A
L3,L4: 12 V output filter inductors
Coilcraft Z7257, 25.I'H at 1.0 A
RGURE 7-6 -
MOTOROLA TMOS POWER MOSFET DATA
A-75
POWER MOSFET VERSION
•
providing a good relative measure of its efficiency as a
switching element.
When an MTP4N50 FET is substituted for the bipolar
transistor, the drive circuit is greatly simplified as illustrated in Figure 7-7. Now the MC34060 control circuit is
capable of directly driving the FET, eliminating the complex base drive circuitry required for the bipolar. The end
result is that the FET can be substituted for the bipolar
by removing five components and changing one resistor
value. Thus, the FET SUbstitution, results in a reduced
components count.
Performance wise, the FET is the better choice, with a
considerably improved crossover time, Figure 7-8, and a
case temperature rise of only 18°C.
60 Hz and 100 kHz, below 100 mV on all outputs. (See
Table 2.) Line regulation here was excellent, less than
0.1%, but load reg (2.0%) could have been better. Normally tight layouts and higher loop gain can get this down
to 0.1 to 0.5% as well. Efficiency (75%) and cross regulation (± 10%) are also similar to other multiple output
switcher designs.
TABLE 2 -
Output Data
t. Ripple Voltages (120 Vae, Full Load)
Winding
100 k Ripple (PP)
60 Hz Ripple (PP)
Noise Spikes (PP)
+5.0
60 mV
20mV
2.0 V
-5.0
300mV
50 mV
2.0 V
+12
70mV
70mV
2.0 V
-12
50mV
60mV
2.0V
2. + 5.0 V Regulation
Line
Load
Voltage
*Note:
Automotive DC-DC Converter
100 Vae 100 Vae 130 Vac 130 Vae
Full
Half'
Full
Half
5.10
5.21
5.10
5.21
+ 5.0
In the previous example, FET drive circuitry was maximally simplified. The penalty for this simplification is that
tum-on gate-source voltage, applied across a relatively
low gate-source resistor, draws approximately as much
drive power as a bipolar would. This example illustrates
how the FET's low drive power requirements can be used
advantageously. The circuit, shown in Figure 7-9, is a 25
watt DC-DC converter that is designed for automotive use.
It uses the same control IC as the' previous example. The
significant difference is the addition of Q1, 03, & 06 to
the drive. loop. This arrangement provides a low impedance loop for fast tum-off, while drawing a negligible
amount of current from the IC after the FET is turned-on.
The FET and this circuit work well together. Efficiency
was measured at 78% with Vin at 13.6 volts, load regulation at O.4%/Amp., and line regulation at O.Ol%lvolt.
In general, the comparatively low rDS(on) of FETs with
100 V (or less) ratings makes the FET a particularly good
choice for this type of application.
V Load increased to 2.0 ohms and -12 V load removed.
Load Reg. = 1!.vrYVo = 0.11/5.1 = 2.2%.
Line Reg. AVrYVo
= 0.005/5.1 =
1.0%.
20 kHz Switcher,
A less novel 20 kHz flyback switcher provides a good
illustration of the interchangeability of FETs and bipolar
transistors. The 35 watt supply shown in Figure 7-5 was
originally designed around the MJE13005 bipolar output
transistor. With the bipolar, crossover time and case temperature rise were measured with Vin at 160 Vdc and
outputs fully loaded.
A view of the crossover waveforms is shown in Figure
7-7. At the full load case temperature of 71°C, the
MJE13005 is turning on in a crossover time of slightly
under one microsecond, (46°C case temperature rise),
o
o
FIGURE 7-8 - FET CROSSOVER TIME
FIGURE 7-7 - BIPOLAR CROSSOVER TIME
MOTOROLA TMOS POWER MOSFET DATA
A-76
01
lN5821
Input
9-24V
O. I
Ll
15 ~h
r
Oo-.,-......,....,=YY:;;:;T"\._-_+---""""1r-------------....,
:~
~F
I
'i
i dt
331 i30
):20
~r
02
lN4148
6T
#18
10
33k
0.Q1
10 k
•
9
C~
~-F I~~:
~
8.2 k
14 +
EL.!.L 75
0.9 V
12 VREF
22~f:
27
k
1.8 k
GNO
1- -
OT CT RT
6
4
5
1.35V
10 k
F-
73~
100~F
4
1.0 k
#26
,
O. I
~
8.2
k
•
13
8.2 k
8.2
k
I
MC34060P
~~.~~----~COMP
0.1
54V
*22~
ICI
: I
05
lN4935
"'
i~:
~
.
100 k
V
MTP
lN4148
1.0 k
V:zW
476 ~F
,;)~t
03
MPS
A5~~
D4
lN4148
loon
06
IN
.~~ 4748
18 V
Lr'"
0.05
::::
0.1
~~----------------------------------~
CORE = FERROXCUBE 3019·LOO-3Ce
BOBBIN = FERROXCUBE 3019F-l0
GAP = 0.015"
T2: COILCRAFT 01871 CURRENT SENSE XFMR.
T3: CORE = COILCRAFT 11·484-41 EE-19
BOBBIN = COILCRAFT 37-612·001
GAP = 0.0075"
T1:
Ll: COILCRAFT Z7156, 151'H
L2: COILCRAFT Z7157. 25 I'H
FIGURE 7-9 - AUTOMOTIVE DC-DC CONVERTER
MOSFET HV Flyback Converter
Figure 7-10c. This transistor has breakdown voltage ratings VCEO(sus) and VCEV of 800 V and 1400 V, respectively, and a continuous collector current of 10 A. But,
most important, it has a reverse bias safe operating area
(RBSOA) curve, shown in Figure 7-11a, which allows a
peak flyback voltage of about 700 V, generated by a peak
collector current in the 3.0 to 4.0 A range.
To achieve this RBSOA capability an off-bias voltage,
VBE(off), of about -S.O V is required. Also, since there
The advantages of power MOSFETs over bipolars high input impedance (low drive power), fast switching,
freedom from second breakdown - have been cited
many times and can clearly be shown when the two technologies are used in the same application. Such is the
case when a HV flyback converter, initially deSigned with
a bipolar, was redesigned for the power MOSFET.
The first design used a Switchmode high-voltage bipolar
MJ8S0S output transistor in a PWM flyback converter,
MOTOROLA TMOS POWER MOSFET DATA
A-77
•
is a trade-off of ~ with high-voltage transistors (~min =
7.S at IC = 1.S A), a low forced beta ~F of about 2.S (lBI
= 1.S A) was chosen to ensure device saturation. To
produce clean, monotonic, relatively fast clamped inductive turn-off waveforms, the Baker Clamp network of
diodes (02-04) is suggested. Consequently, a power amplifier consisting of an IBI forward base current circuit
(transistors 01 and 02) and an off-bias circuit (transistors
03 and Q4) is required to interface the low level PWM
with the MJ8S0S. The PWM (Ul), for this example, need
only provide a + S.O V pulse to the power Amp with about
20 mA sourcing and sinking capability.
If, however, the output device is a comparably rated
power MOSFET, MTM2N90 the drive circuitry can be
greatly simplified, with the resulting savings in cost and
improved reliability. Moreover, the faster switching
L2 = 2.0 mH
100T #20
Pot Core: 42293CB
Gap: 65 mil
+voo
<36 V
+VOO
L1 = 1.6mH
100T #24
Pot Core: 3019P3B7
L1
MR510
01
RL
Vo
30 k
Vo
68
+15
RL
1.0 k
U1
1.0 k
0.1 p.F
1.0 kV
MTM2N90
PWM
(2)
MTM2N90
68
"::"
1.0 k
PWM
FIGURE 7-10b - TWO PARALLEL MOSFET OUTPUT
FIGURE 7-108 - SINGLE MOSFET OUTPUT
+5.0V
Power
Amp
220
100
150 pF
Y,
~--I:-
Q2
MJE210
+VCC
W
2.0
PWM
5.0W
1N4007
02
MR510.
r-~----~~-t~O~-~-oVo
1N914
C1
MJE
200
270
1.0 k
"::"
RL
60 k
100
-5.0V
FIGURE 7-10c - DRIVER WITH BIPOLAR OUTPUT
FIGURE 7-10 -
HIGH VOLTAGE FLYBACK CONVERTER WITH POWER MOSFET & BIPOLAR OUTPUTS
MOTOROLA TMOS POWER MOSFET DATA
A-78
0
1\
\
0
B. 0
VBEloffi' = 2:0 to 7.0 V
Of-- t-
0
\
'C"B2:2.0
TJS100·C
f-- t0
MTM2N90
MTP2N90
"\
I'"
200
400
600
BOO
MTM2NB5
MTP2,NB5
TJ";150 0 C
0
\
0
0
•
0
1000
0
r-
I--
1200
0
1400
1000
400
600
BOO
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
200
VCE. COLLECTOR·EMITTER VOLTAGE (VOLTS)
FIGURE 7-118 - RBSOA. REVERSE BIAS SWITCHING
SAFE OPERATING AREA
FIGURE 7-11b - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
MOSFET improves system efficiency and as subsequently described. greater RBSOA or turn-off switching
SOA is achieved (see Figure 7-11 for comparison of the
MTM2N90 with the MJB505).
The PWM can be any of the 15 V powered I.C.'s with
source and sink capability in the 100 mA range. This current level is amendable to driving power MOSFETs at a
relatively fast switching speed. the current sourcing.
charging up the FET input capacitance Ciss and the sinking. discharging the capaCitance for fast turn-off switching.
Also. the near 15 V PWM output ensures that the FET is
well turned on.
This is exactly what was done for the second version
of the high voltage Switchmode power supply; the PWM
directly drives the FET gate. Using a single N-channel.
high-voltage TMOS MTM2N90 transistor (VBR(OSS) =
900 V. 10 = 2.0 A). a high-voltage output of 750 V peak.
capable of driving a 60 k load was achieved. With the
illustrated load inductor L 1 and switching frequency. the
peak drain current was about 2.5 A (limited by the magnetic saturation of the inductor) and the flyback voltage
was about 750 V.
Atlhough this current exceeds the continuous 2.0 A
drain current rating of the device. it is well within the
7.0 A pulsed current rating. But. of even greater interest.
since the FET has no second breakdown limitations as do bipolars - it can sustain simultaneous high switching voltages and currents. Thus. the 750 V. 2.5 A load
line is well within the SOA rating.
To produce even higher output power levels. two parallel connected power MOSFETs can be driven. as illustrated in Figure 7-10b. USing a larger inductor L2. the
circuit .was capable of easily producing an BOO V output
into a 30 k load. The total peak drain current was 3.5 A
with each driver sharing current inversely proportional to
its rOS(on): I.e.• matchedon~resistance of 5.0 n produced
about equal values of 10 of 1.75 A. unmatched 5.0 and
B.O
about 2.1 A and 1.4 A respectively. Reducing the
load resistance even further. resulted in greater power
output. with the individual device drain current being well
within spec limits. as shown in Table 3:
TABLE 3
RL
VOO
Vo
Total
IO(pk)
Po
30 k
25 k
21 k
2B V
31 V
34V
BOO V
BOO V
BOO V
3.6 A
3.BA
4.2 A
21.3W
25.6W
30.5W
And finally. to make a direct comparison between the
two devices. the loads and ',ne stored energy inductor
should be the same. Since the bipolar originally was tested
with the larger inductor and a 30 k load to produce as
great as a 700 V output from a peak collector current of
3.2 A. the single TMOS was also tested to these conditions. Not only did the power MOSFET reach this energy
level. it also reached BOO V at 3.6 A. To achieve the
required inductor stored energy and power output for this
application. the switching frequency was about 1.7 kHz.
Even at this low frequency. the relatively high static losses
[VOS(on) = rOS(on) 10 = B.O n (max) (3.2 A) "" 25 V]
contributed little to the total device loss.
Admittedly. power MOSFETs are still more expensive
than a comparably die sized bipolar. but. as progression
along the learning curve is achieved. the FET will become
more cost competitive. Nevertheless. it has been shown
that the single power FET circuit is much simpler and cost
effective to drive in this example than the bipolar and offers
the second breakdown free rectangular SOA curve that
allows full VSR(OSS). 10 switching capabilities.
SWITCHMODE Power Supply (SMPS)
Configurations
The implementation of switching power supplies by the
non-specialist is becoming increasingly easy due to the
availability of power devices and control ICs especially
developed for this purpose by the semiconductor manufacturer.
This section is meant to help in the preliminary selection
of the devices required for the implementation of the listed
switching power supplies.
n.
MOTOROLA TMOS POWER MOSFET DATA
A-79
•
Flyback Switching Power Supplies:
50Wto 250 W
-
+
• Converter efficiency: T/ = 80%
• Maximum FETworking voltage:VDSW = 2.0· Vin(max) • V2.O
• Output regulation by duty cycle (8) variation:
8max = -0.4
• Minimum FET drain-source voltage:
VDS;;' 1.2·VDSW
• Maximum MOSFET working current:
I =
2.0 Pout
= 5.5 Pout
w
T/. 8max • v'In(min) • V2.O
Yin
• Working frequency: f = 20 to 200 kHz
• Input line variation: Yin
10%, - 20%
Output
Rectifier
DC Output
Line
Input
Input
Rectifier
Control
Circuitry
FIGURE 7·12 - BASIC FLYBACK CONFIGURATION
TABLE 4 -
Flyback Semiconductor Selection -Chart
175W
100W
SOW
Output Power
250'11
Input Line Voltage, Yin
120 V
220 V
or
240 V
120 V
220 V
or
240 V
120 V
220 V
or
240 V
120 V
MOSFET Requirements
Max Working Current, Iw
Max Working Voltage, VDSW
2.25 A
380 V
1.2 A
750 V
4.0 A
380 V
2.5A
750 V
8.0 A
380 V
4.4 A
750 V
11.4 A
380 V
Power MOSFETs Recommended
_ MTM4N45 MTM2N90 MTM4N45 MTM2N90 MTM7N45 MTM4N90
Metal (TO-204M) (TO-3)
MTP4N45 MTP2N90 MTP4N45 MTP2N90
Plastic (TO-220AB)
Plastic (TO-218AC)
MTH7N45
-
-
Input Rectifiers
Max Working Current, IDC
Recommended Types
Output Rectifiers
Recommended types for
Output Voltage of: 5.0V
10 V
20 V
50V
100 V
Recommended Control Circuits
-
-
-
2.35 A
MDA970
1.25 A
MDA210
-
0.4 A
0.25 A
0.4 A
MDA104A MDA106A MDA206
MBR3035PT
MUR3010PT
MUR1615CT
MUR1615CT
MUR440, MUR840A
0.5 A
MDA210
MBR3035PT
MUR3010PT
MUR1615CT
MUR1615CT
MUR840A
MBR12035CT
MURlool0CT
MUR3015PT
MUR1615CT
MUR840A
SG1525A, SG1526, TL494; Inverter Control Circuit
MC3423, MC3424; Overvoltage Detector
Error Amplifier: SINGLE TL431; DUAL-MC3438, LM358;
QUAD - MC3403, LM~24,LM2902"
MOTOROLA TMOS POWER MOSFET DATA
A-SO
MTM15N45
-
4.6 A
MDA3506"
MBR2oo35CT
MUR100l0CT
MUR10015CT
MUR3015PT
MUR840A
Push-Pull Switching Power Supplies:
100 W to 500 W
+
• Converter efficiency: 1/ = BO%
• Maximum FET working voltage:
VOSW = 2.0' Vin(max) • v2.O
• Output regulation by duty cycle (.5) variation:
.5max = O.B
• Minimum FET drain-source voltage:
VOS;;" 1.2·VOSW
• Maximum MOSFET working current:
I Pout
_ 1.4 Pout
Yin
w - 1/' .5max • Vin(min) • v2.O -
• Working frequency: f = 20 to 200 kHz
• Input line variation: Yin
10%, -'- 20%
Output
Filter
r
Output I
Rectifier .L
DC Output
Line
Input
Control
Circuitry
Input
Rectifier
Power
Inverter
FIGURE 7·13 - BASIC PUSH-PULL CONFIGURATION
TABLE 5 -
Push-Pull Semiconductor Selection Chart
100W
Output Power
250W
Input Line Voltage, Yin
120 V
220 V
240 V
MOSFET Requirements
Max Working Current, Iw
Max Working Voltage, VOSW
1.2 A
3BOV
0.6A
750 V
MTM2N45
MTP2N45
MTM2N90
MTP2N90
Power MOSFETs Recommended
Metal (TO-204AA) (TO-3)
Plastic (TO-220AB)
Plastic (TO-21BAC)
Input Rectifiers
Max Working Current, IOC
Recommended Types
Output Rectifiers:
Recommended types
for output voltages of:
5.0 V
10 V
20 V
SOV
100 V
-
0.9A
MDA206
-
0.5A
MDA210
MBR3035PT
MBR3045PT
MUR3010PT
MUR1615CT
MUR1615CT
MURB40A, MUR440
Recommended Control Circuits
500W
120 V
220 V
240 V
2.9 A
3BO V
1.6 A
750 V
MTM4N45
MTP4N45
MTM2N90
MTP2N94
-
2.35 A
MDA970-5
220 V
240 V
5.7 A
3BO V
3.1 A
750 V
MTM7N45
MTM4N90
-
-
MTH7N45
1.25 A
MOA210
4.SA
MOA350S
-
.2.5A
MOA3510
MBR12035CT
MUR10010CT
MBR20035CT
MUR1 001 OCT
MUR3015PT
MUR1615CT
MURB40A
MUR10015CT
MUR3015PT
MURB40A
See Table 4
MOTOROLA TMOS POWER MOSFET DATA
A-81
120V
Half-Bridge Switching Power Supplies:
100 Wto 500 W
• Input line variation:Vin + 10%, - 20%
• Maximum FET working voltage:
VDSW = Vin(max)· V2.O
• Converter efficiency: 1/ = 80%
• Output regulation by duty cycle (.5) variation:
c5max = 0.8
• Minimum FET drain-source voltage:
VDS ;., 1.2· VDSW
• Working frequency: f = 20 to 200 kHz
• Maximum MOSFET working current:
I _
2.0 Pout
_ 2.B Pout
Vin
w - 1/. c5max • Vin(min) • V2.O -
Output
Rectifier
r-
--,
L_
_-1
I
Output
Filter
DC Output
I
---,I
.---~--~-+-r--~~
W-rl
I
Line
Input
Control
Circuitry
I
I
I
Power
Inverter
Ll.01
,
L..---_-----------r--'___
Input
Rectifier
I
FIGURE 7-14 -
TABLE 6 -
BASIC HALF-BRIDGE CONFIGURATION
Half-Bridge Semiconductor Selection Chart
100W
Output Power
350W
500W
Input Voltage, Vin
120 V
220 V
240 V
120 V
220 V
240 V
120 V
220 V
240 V
MOSFET Requirements
Max Working Current, Iw
Max Working Voltage, VDSW
2.3A
190 V
1.25 A
3BOV
5.7 A
190 V
3.1 A
3BOV
11.5 A
190 V
6.25 A
380 V
MTM3N35
MTP3N35
MTM2N45
MTP2N45
MTMBN35
-
MTM4N45
MTP4N45
MTM10N25
MTP10N25
MTM7N45
2.3 A
MDA970-5
1.25 A
MDA210
Power MOSFETs Recommended
Metal (TO-204AA) (TO-3)
Plastic (TO-220AB)
Plastic (TO-218AC)
Input Rectifiers
Max Working Current, IDC
Recommended Types
Output Rectifiers:
Recommended types
for output voltage of:
5.0 V
10 V
20V
50V
100 V
-
0.9 A
MDA206
0.5A
MDA210
MBR3035PT
MBR3045PT
MUR3010PT
MUR1615CT
MUR1615CT
MUR840A, MUR440
-
MTH8N35
2.5 A
MDA351 0
MBR20035CT
MUR10010CT
MUR3015PT
MUR1615CT
MUR840A
MUR10015CT
MUR3015PT
MUR840A
MOTOROLA TMOS POWER MOSFET DATA
A-82
4.6 A
MDA3506
-
MTH7N45
MBR12035CT
MUR10010CT
See Table 4
Recommended Control Circuits
-
Full-Bridge Switching Power Supplies:
500 W to 1000 W
• Input line variation: Vin + 10%, - 20%
•
• Converter efficiency: 1/ = BO%
• Maximum MOSFET working voltage:
VDSW = Vin(max)· '\12.0
• Output regulation by duty cycle (il) variation:
ilmax = O.B
• Minimum FET drain-source voltage:
VDS;;' 1.2· VDSW
• Maximum MOSFET working current:
I Pout
_ 1.4 Pout
w - 1/. ilmax • Vin(min) • '\12.0 Vin
• Working frequency: f = 20 to 200 kHz
Output
Filter
Output
Rectifier
r -----,
~ _____
J
DC Output
Control
Circuitry
-
Line
Input
Input
Rectifier
-
-
-----11--11----'
~I
Inverter
FIGURE 7-14 -
TABLE 7 -
BASIC FULL-BRIDGE CONFIGURATION
Full Bridge Semiconductor Selection Chart
500W
Output Power
750W
1000W
Input Voltage, Vin
120 V
220 V
240 V
120 V
220 V
240 V
120 V
220 V
240 V
MOSFET Requirements
Max Working Current, Iw
Max Working Voltage, VDSW
5.7 A
190 V
3.1 A
3BOV
B.6A
190V
4.7 A
3BOV
11.5 A
190 V
6.25 A
3BO V
MTM7N20
MTP7N20
MTM4N45
MTP4N45
MTM10N25
MTP10N25
MTM7N45
MTP4N45
MTH7N45
MTM12N20
MTP12N20
MTH15N20
MTM7N45
3.B A
9.25 A
5.0 A
Power MOSFETs Recommended
Metal (TO-204AA) (TO-3)
Plastic (TO-22DAB)
Plastic (TO-21BAC)
Input Rectifiers
Max Working Current, IDC
Recommended Types
Output Rectifiers:
Recommended types
for output voltages of:
5.0 V
10 V
20 V
50V
100 V
-
4.6 A
MDA3506
2.5A
MDA3510
MBR20035CT
MUR1 001 OCT
MUR10015CT
MUR3015PT
MURB04PT
7.0 A
MBR30035CT
MUR10010CT*
MUR10015CT
MUR3015PT*
MUR3040PT*
See Table 4
Recommended Control Circuits
'More than one device per leg, matched.
MOTOROLA TMOS POWER MOSFET DATA
A-83
MTH7N45
MBR30035CT*
MUR10010CT*
MUR10015CT*
MUR10015CT
MUR3040PT
•
Motor Controls
motor magnets try to align producing torque. A Simplified
representation of a stepping motor is shown in Figure
7-16. Initially, Poles A and B are both energized With north
up, drawing the rotor's south pole to the up position. Reversing the polarity of Pole A draws the rotor 90° clockwise
to its final position; this is known as a full step. If pole A
had been turned off instead of reverSed; the rotor would
have rotated only 45° clockwise to line up with the field
created by Pole B; this is known asa half step. Stepping
motors obtain small angle step increments by using large
numbers of poles. Stator pole reversal can be accomplished by reversing the current flow direction in the winding or by using alternate halves of a center-tapped
winding. .
An external block diagram of a center-tapped stepping
motor plus control switches, inductive clamp diodes, resistive current limiting and power supply is shown in Figure
7-17. Pole A, for instance, can be energized to one polarity
by turning Switch 1 on and Switch 2 off; the opposite
polarity is generated by turning Switch 1 off and Switch
2 on.
It follows that the proper magnetic polarity sequence
for stepping can be generated by contrOlling Switches
1-4. Clamp diodes prevent the voltage across the inductive winding from flying up and destroying the switches
as they are turned off. The required switching sequences
for full and half step operation are shown in Figure 7-18.
Reversing the sequences of Figure 7-18 will reverse the
direction of motor rotation.
Rapid stepping requires high dildt in the motor windings.
Since di/dt is a function of supply voltage, a high supply
voltage is desirable. The average winding current is limited by the motor manufacturer's specification. As an example, Superior Electric's SLO-SYN model M093-FC07
has a current rating of 3.5 amps/winding with 1.23 0/
winding resistance and 7.94 mH/winding inductance. The
recommended power supply is 24 volts; currents are limited to the maximum rating by a 6.5 0, 100 W resistor/
winding. This yields a dc current of about 3.0 A and an
UR time constant of 1.0 ms. Higher supply voltages and
Power MOSFETs are interesting devices for motor drive
applications. The advantages and disadvantages are similar to those discussed for switching power supplies. With.
motor drives, however, there is more of a distinction.
Whereas FETs are not yet a match for bipolar Darlingtons
in off-line multiple horsepower drives, they are an excellent choice for fractional horsepower drives and drives
that are operated off busses less than 100 V.
Three examples are illustrated. They include a stepping
motor drive, a high efficiency H bridge, and a onetransistor PM motor speed control.
Using Power MOSFETs in Stepping
Motor Control
Stepping motors are used extenSively in electromechanical positioning systems. Applications range from
printers to tape drivers, floppy disk drives, numerically
controlled machinery and other digitally controlled POSItioning systems. The task of the stepping motor controller
is to drive the rotation generating sequential current flows
in the field winding of the motor on command from an
external device.
The use of TMOS Power MOSFETs and CMOS logic
simplifies the drive circuitry while allowing considerable
flexibility of control. This section describes several types
of stepping motor control circuits including an 88.0% efficient switching drive. Stepping motor logic sequencing,
power requirements and dynamiCS are briefly examined.
DRIVE TECHNIQUES
Stepping Motor Characteristics
A basic understanding of stepping motors is desirable.
A permanent magnet stepping motor consists of a series
of permanent magnets distributed radially on a rotor shaft
surrounded by electromagnets attached to the stationary
housing. Energizing the electromagnets with the proper
polarities generates a magnetic field pattern to which the
Protection Diode
FIGURE 7-16 - SIMPUFIED STEPPING MOTOR
FIGURE 7-17 - SIMPUFIED STEPPING MOTOR AND CONTROL
BLOCK DIAGRAM'
'Colors are for Superior Electric
SLO-SYN dc Stepping Motors
MOTOROLA TMOS POWER MOSFET DATA
A-84
the resulting larger current limiting resistor will decrease
UR and increase the obtainable stepping rate.
Depending on rotor inertia, torque requirements and
winding currents, a stepping motor may exhibit oscillatory
behavior including vibration, lost steps and/or stalling near
self-resonant stepping frequencies. Oscillatory behavior
may be lessened or eliminated by adjusting winding currents, by adjusting interial and/or torque loading or by the
use of mechanical dampers.
winding drive sections plus the complete control logic is
shown in Figure 7-21. The total drive consists of four
N-Channel and four P-Channel TMOS Power FETs arranged in two push-pull drives per winding (the M093FC07 center tap leads were floated, inductance/full winding = 31.76 ,..H, resistance/full winding = 2.46 nand
rated current = 2.0 amps/winding).
Phasing signals are obtained with the shift register technique described earlier. The circuit of Figure 7-21 will provide a full or half step sequence as clocked into the two
CMOS shift registers during a preset (a full step only controller can be implemented with one 4-bit CMOS shift register). Gate signals for the N-Channel FETs are taken
directly from the CMOS registers. Gate signals for the
P-Channel FETs are translated and referenced to the motor power rail through 09-Q10.
Sufficient capacitance across the sources of the bridge
FETs must be used to limit P-Channel gate-source voltage
transients to below the pass frequency of the collector
resistor and the P-Channel gate capacitance. During
switching transients, it is possible that both FETs in a given
complementary pair could briefly be on at once. This condition could short power to ground through the complementary pair. To avoid exceeding peak drain current rating, the gate-drive on the P-Channel FET is restricted to
10 V.
TMOS Power FETs are constructed with internal
source-to-drain diodes. The circuit of Figure 7-21 uses
these diodes to shunt turn-off transient currents from the
ground plane to the power rail; thus, a given FET is protected from winding turn-off energy by the source-drain
diode of its complement. The source-drain diode, how-
A Full Step Center-Tapped Drive
Figure.7 -19 illustrates a full step center-tapped stepping
motor controller using one CMOS 4-bit presettable shift
register to drive four N-Channel TMOS Power FETs. Examining the full-step sequence of Figure 7-18, shows that
the sequences for the various gate signals are the same
except for a phase shift. Therefore, the desired control
sequence of two on-time periods followed by two off-time
periods may be preset into the 4-bit shift register
(MC14194) of Figure 7-19. The required phasings are
obtained by tapping the appropriate shift register outputs.
Clockwise stepping is obtained by right shifting the
MC14194; left shifting yields counterclockwise stepping.
Control signals SO and S1 plus a clock line control stepping. On power-up, the MC14194 requires a preset obtained by setting SO, S1 = 1,1 and supplying a leading
edge clock; this puts the logic in a known state. The remainder of the control functions are illustrated in the control table of Figure 7-19; stepping occurs in a leading edge
clock. Diodes 1-4 prevent the inductive turn-off spike from
avalanching the TMOS Power FETs. Resistor R3 creates
a back voltage which halts winding current rapidly on turnoff. R3 is selected to limit the voltage spike to the TMOS
S-D voltage rating. TMOS power FETs.switch extremely
fast, and the turn-on delay of the diodes may not be short
enough to prevent S-D avalanche. A small capacitor (0.01
to 0.1 ,..F) placed across the motor winding will usually
lower dv/dt sufficiently to prevent S-D avalanche. Resistors R1 and R2 limit motor winding currents.
Full-Step Sequence
STEP
SW1
SW2
SW3
SW4
1
OFF
ON
OFF
ON
2
OFF
ON
ON
OFF
3
ON
OFF
ON
OFF
A Full or Half Step Center-Tapped Drive
4
ON
OFF
OFF
ON
Figure 7-20 illustrates a full or half step controller. As
in the full step sequence, the gate control signals for the
half step sequence are identical except for a phase shift.
Similarly, the desired pattern of three on-time periods followed by five off-time periods can be preset on a leading
edge clock into an eight-bit shift register formed by two
MC14194's. The full step sequence can be generated by
setting the half step line high and performing a preset.
Right shifting and left shifting control the motor shaft's
direction of rotation as before. A full step will be executed
for every two riSing clock pulses independent of stepping
sequence. Diodes D1-D4 and resistor R3 form the overvoltage protection for the TMOS Power FETs. R1 and R2
limit motor winding currents.
1
OFF
ON
OFF
ON
STEP
SW1
SW2
SW3
SW4
1
OFF
ON
OFF
ON
2
OFF
ON
OFF
OFF
3
OFF
ON
ON
OFF
4
OFF
OFF
ON
OFF
5
ON
OFF
ON
OFF
6
ON
OFF
OFF
OFF
7
ON
OFF
OFF
ON
8
OFF
OFF
OFF
ON
1
OFF
ON
OFF
ON
Half-Step Sequence
Push-Pull Drive
AGURE 7-18 - STEPPING SEQUENCES"
Figure 7-21 illustrates a complementary push-pull drive
for a non-center tapped stepping motor driven from a 24
volt motor supply and a 15 volt logic supply. One of two
"Clockwise Rotation as Viewed from the
Nameplate End of the Motor
MOTOROLA TMOS POWER MOSFET DATA
A-55
•
•
ever, requires about 300 ns of turn-on time. A 0.1·p,F
capacitor is placed across each winding so that the windings dv/dt is low enough to allow for diode turn~on without
avalanching the FETs. Winding currents are limited by the
9,0 ohm 5.0 watt resistors.
for left to right current flow is 1,0. This turns the upper left
P-Channel and the lower right N-Channel on placing the
full power supply across the motor winding. Current 11
increases with di/dt = V/L. When 11 increases to 2.0
amps, the voltage across the lower right 0.1 sensing resistor will be 0.2 volts, and the lower right comparator will
go low after a short filter delay shutting off the upper left
P-Channel FET. The current through the motor winding
begins to decay around the I2 current path.
When the comparator went low, i1shifted its positive
input reference down by about 70 mY. 12 decays until the
voltage across the 0.1 sense resistor falls below the hysteresis determined level; at that pOint, the comparator will
go high turning on the upper left P-Channel FET and
recharging the winding current along the 11 current path.
The winding current within the C1, C2 control envelope
increases to the reference level and oscillates. around that
level at a value set by RH, Rref and the logic supply
voltage. The frequency of oscillation is set by V/L, the
hysteresis value and the current path resistances.
The circuit of Figure 7-22 places a negative voltage on
Switched Current Limiting
The circuit of Figure 7-21 uses resistive current limiting.
With 2.0 amps flowing in each winding, 4.0 amps will be
drawn off of the 24 volt supply yielding 96 watts of draw
with only 25% of that power being delivered to the motor.
Some form of switched current limiting is clearly desirable.
Figure 7-22 illustrates a simple switching scheme.
Starting with zero current flow, let the desired current
flow be left to right through the motor winding. Let the
referenced voltage Vref be 0.2 volts. Assuming RH > >
Rref, the positive comparator inputs will be approximately
0.2 volts. With no current flow, the sense resistors will
have no voltage across them and the comparators will
have high outputs; this enables the C1 and C2 inputs to
drive the P-Channel Power FETs. The proper C1, C2 input
24 Volts
24VoitS
R3
Black
White
Green/White
Red/White
Green
so
51
04
<>::====~J
Clock
(Leading Edge)
Sl
so 0
SO,Sl
Result
0,0
Hold
0,1
Shift Left
1,1
Preset
Motor
Control Signals
Shift Right
1,0
Stepping
Clock
(Leading Edgel
Control Signals
Logic Levels are 5ta ndard
15V, CMOS
MC14194 is a Standard 16 Pin DIP.
50,51
Result
0,0
Hold
0,1
Shift Right
1,0
Shift Left
1,1
Preset
Parts:
1. Example Motor is M093-FC07 Manufactured
By Superior Electric
2. Diodes, 01-04, 1 N4002
3. R3, 10n lOW
4. Rl,R2,6.5nl00W
5. Integrated Circuit, MC14194 (CMOS)
6. 01-04, MTM12NOB or MTP12NOB
PARTS:
1. Example Motor is Superior Electric's
Model M093-FC07
2. Diodes, 01-04, 1 N4002 or Equivalent
3. R3,10!l10W
4. Rl, R2, 6.5!l 100 W
5. Integrated Circuits, MC14194 (2 Required)
6. 01-04, MTM12NOB or MTP12NOB
FIGURE 7-19 - CENTER-TAPPED
STEPPING MOTOR DRIVE
FIGURE 7-20 - HALF- OR FULL-STEP DRIVE
FOR CENTER-TAPPED STEPPING MOTORS
MOTOROLA TMOS POWER MOSFET DATA
A-86
the negative input terminal of the comparators during the
12 current path. This is not detrimental to the comparator
provided that the terminal current doesn't exceed a few
milliamps.
The complete logic circuit plus one of two required winding drive sections for a push-pull stepping motor with
switched current limiting is shown in Figure 7-23. Figure
7-24 is the corresponding parts list for the complete circuit.
The circuit of Figure 7-23 is limited to 8.0 amps continuous
with a motor power supply voltage of about 70 volts by
the specified P-Channel TMOS Power FETs. Thus, the
controller can handle up to 560 watts delivered to each
winding. Changes in RH, Rref and the sensing resistor
may be desirable for motors other than the example motor.
For low inductance motors driven from high voltage supplies with low levels of hysteresis, faster components in
the switched feedback loop may be required.
delivered to the M093-FC07. Calculations indicated that
greater than 50.0% of the control circuit power consumption was due to the SoD diode drop during the 12 current
loop (Figure 7-22). This drop could be lowered byoperating the lower N-Channel Power FETs as synchronous
rectifiers. The additional logic required for synchronous
rectification amounts to three CMOS integrated circuits.
A complete logic circuit plus one of the two required winding drive sections is shown in Figure 7-25. Essentially, the
lower N-Channel is turned on when the upper complementary P-Channel is turned off by the comparator or
when the N-Channel control signal is high. The circuit of
Figure 7-25 yielded 88.4% efficiency at 2.0 amps/winding.
Further Possibilities
Shaping of the applied current waveform is often desirable. If a large stepping torque followed by a low holding
torque is desired, the required current waveform can be
applied to the positive comparator input. Within the comparator hysteresis and the circuit's current response
speed, the current in the motor will follow the comparator
reference. The dildt circuit response Is limited byapproximately Vmotor supply/Lmotor, provided that the series
resistance drops only a few percent of the supply Voltage.
If current is allowed to decay without applying a reverse
supply voltage, current decay time will be set by the
Lmotor/Rdecay loop time constant.
In summary, the switching circuit of Figure 7-23 yields
79.0% efficiency at 2.0 amps/winding with faster current
response than the 25.0% efficient resistive current limited
circuit of Figure 7-20. Adding three CMOS integrated circuits to the circuit of Figure 7-23 yields the 88.0% efficient
circuit of Figure 7-25. The use of TMOS Power FETs and
CMOS logiC in the designs of Figures 7-23 and 7-25 allowed high efficiency and considerable control flexibility
to be achieved without excessive parts count or undue
complexity.
Utilizing Synchronous Rectification
The circuit of Figure 7-23 required 26.4 watts to maintain 2.0 amps/winding with 78.8% of the drawn power
SO,SI
Result
0,0
Hold
0,1
Shift Right
1,0
Shift Left
1,1
Preset
Parts:
1.2xMCI4194(CMOS)
2. Ql-Q4, 4 x MTP8P08 or MTM8P08
(TMOS Power FETs)
3. Q5-Q8. 4 x MTP12N08 or MTM12N08
(TMOS Power FETs)
4. Q9-QI2. 4" MPS8099 (NPN Small Signal)
5. 2 x 9 Ohm 50 Watt Resistors
6. 4 x 0.68 kO 114 W Resistors
7. 4 x 1.0 kO 114 W Resistors
Example Motor: Superior Electric SLO-SYN Model
M093-F007
FIGURE 7-22 - COMPARATOR SWITCHED CURRENT LIMITING
FIGURE 7-21 - HALF- OR FULL-STEP RESISTIVE CURRENT
LIMITED DRIVE FOR STEPPING MOTORS WITHOUT CENTER-TAP
MOTOROLA TMOS POWER MOSFET DATA
A-87
'. Integrated Circuits
1. .2 _ MC141.94B,.CMOS 4-Bit Shift Register
2. 1 - MC14081 B, CMOS Ouad "AND" Gate
3. 1 -MLM399P, Ouad Comparator
TMOS Power FETa
1. 01-04; 4 - MTPBPOB or MTM8P08, P·Channel
Power FET
2. 05-08,4- !\I1TP12N08 or MTM 12N08, N-Channel
Power FET
. Transistors .
1.
09-012,4- MPS8099, NPN Small Signal
Transistors
Resistors
1. 4-0.102.0W
2. 4 - 680 0 114 W
3. 5 -1.0 kO 1/4W
4.2-10k01/4W
5. 1 - 30 kO 114 W
6. 1 - 30 kO Adjustable, 114 W
7. 6x100k01/4W
8. 2 x 22 MO 118 W
Zaner Diode
1. 1 x MZ4679, 2 V Reference
SO,S1
CapaCitors
1. 3xO.1"F 100V
2. 4 x 50 pF 50 V
Result
0,0
Hold
0,1
Shift Right
1,0
Shift Left
1,1
Preset
FIGURE 7-24 - PARTS LIST FOR CIRCUIT OF FIGURE 8
FIGURE 7-2:! - HALF- OR FULL-STEP SWITCHED CURRENT DRIVE
FOR STEPPING MOTORS WITHOUT CENTER-TAP
H. Bridge Performance Comparisons
Power MOSFETs are excellent candidates for low voltage H Bridges. In this example, MOSFETs are compared
with two other popular alternatives, bipolar discretes and
bipolar Darlingtons. Circuits were designed for all three
types of output power devices, Each circuit design is optimized for the output device used.
GENERAL "H" SWITCH DESIGN CONSIDERATIONS:
• P.M. DC Motor, 2.0 A run, 15 A stall/start.
• 12 V protected bus, 32 V max peak, 14 V nominal.
• "H" switch input, 2.0 mA max sink requirement.
• Discrete driver stages (for comparison of designs).
• Maximum ambient temperature of 100·C, maximum
junction temperature = 150°C.
• Off the shelf type output power devices using maximum data sheet limits to calculate drive requirements and forward "on" voltage levels. The power
output devices were chosen such that die sizes for
the three types are approximately equal.
Discrete Bipolar "H" Switch
TIP35 and TIP36 power transistors were selected for
their low cost and high current capacity. The high currentgain specification for these units results in base drive requirement of 1.5 amperes to switch a 15-ampere load
current. It may be that base drive can be reduced by 30
percent if the units are screened for high-current hfe, but
for this design comparison, only "off-the-shelf" standard
devices with the regular data-sheet specifications are under consideration.
The bipolar "H" switch design requires medium size
driver transistors and large-wattage voltage-dropping resistors in the base-drive. circuit. A buffer stage is also
required. The control lines are shown tied to a SPOT
center off switch. In an actual circuit, this switch would be
a logic array or a microcontroller output network. A protective counter-EMF voltage clamp is provided by the
back-to-back Zener rectifiers. The Darlington and TMOS
units have built-in clamp diodes and for many applications
would not require the zeners. Capacitor and resistor snubbing networks may be required with all three types output
devices.
As indicated in the performance table, the bipolar design is not very practical because of the large base drive
requirement. Of the three power devices, it is the least
efficient by a wide margin. In most situations, FETs or
Darlingtons are a better choice,
MOTOROLA TMOS POWER MOSFET DATA
A-SS
•
SO, SI
Result
0,0
Hold
0,1
Shift Right
1,0
Shift Left
1,1
Preset
Parts in Addition to Figure 8, 1 x MC14049UB,
1 x MC14081B, 1 x MG14071B
FIGURE 7-25 - HALF- OR FULL-STEP SWITCHED CURRENT DRIVE WITH SYNCHRONOUS RECTIFICATION
VCE(sat) = 1.8 V@ 15 A. 18 = 1.5 A
VCE(sat) = 0.4 V @ 2.0 A, 18 = 1.5 A
Base Orive Po = 14 V x 1.5 A
= 21 W
10.4Vx 15A
MTR Po
EFF = 75
EFF =
=
13.2 V x 2.0 A
=
+
Base Drive Po
= 67.5% at stall condition
156W
MTR Po
156
+ 156,75 = SW Po
26.4
22.6 + 26.4
53.8% at nominal run condition
+14V
26.4W
6.2 k
OFF
4
1
R
5
FIGURE 7-26 - "H" SWITCH BIPOLAR CONTROL CIRCUIT
MOTOROLA TMOS POWER MOSFET DATA
A-89
•
Discrete Darlington "H" Switch
peres for this dc control, and can be derived from a single
voltage pump-up circuit using TMOS gates and voltage
doubling networks.
Motorola MJ4030 and MJ4033 power TO-204 (TO-3)
Darlingtons were chosen for the Darlington version of the
H bridge. As the chart shows, the drive-power requirements are substantially reduced from the bipolar power
design. The tradeoff is that the forward "on" voltage is
raised to such a high level that this particular motor will
no longer be within its terminal voltage specification during
stall or start-up. Also, the Darlington's dissipation will require a larger heat sink than the bipolar design. The Darlington does provide internal clamp diodes.
The Darlington "H" switch design works best in highvoltage, low-current load control circuits where the Darlington's high saturation power loss is not significant.
Test Measurement Calculations
The following equations were used to determine the
circuit performance values for this example.
1. MOTOR POWER CONSUMPTION - The applied
voltage across the motor load-terminals multiplied
times the normal motor current.
PD(MTR) = 1.0 x (VSATT - 2.0 x VF(on))
I = 2.0 AMPS RUN MODE 1= 15 AMPS STALL
MODE
Power TMOS "H" Switch
VF(on) = VCE(sat) or VDS per data sheet
An MTP25N05 Power FET was chosen for this design.
Since the die size falls somewhat shy of the bipolar and
Darlington device die sizes, an adjustment was made in
the conduction loss calculation. Actual VDS(on) measurements were scaled according to the area ratio in order
to arrive at the numbers presented here. As the comparison chart reveals, the TMOS design is clearly superior
to the bipolar and Darlington designs. Its only technical
drawback is the 34 volt bias supply requirement. This
supply only has to source approximately 200 microam-
VCE(sat) = 3.0 V @ 15 A. 18 = O.OS A
VCE(sat) = 1.1 V @ 2.0 A. 18 = O.OS A
Base Drive Po = 1.12 W
MTR
Po
MTR
Po
2. OUTPUT DEVICE POWER DISSIPATION
PD(sw) = (I x VF(on)) x 2.0
3. "H" SWITCH CONTROL EFFICIENCY
EFF = Power Out
Power In
Power Out = PD(MTR)
Power In = PD(sw)
EFF =
+
PD(MTR)
120
91.1 + 120
57% stall mode
=
EFF=~
5.3 + 23.6
= 81% run mode
S.OVx 15A
120W
= 11.8 V x 2.0 A
= 23.6W
=
=
+14V
Y
MJ4030
2.0 k
t
02A
6.2 k
0.007 A,
•
2k
~
MPSA70
I
~
"2.0 Wr---!---lr-:-r-........
100
3.9 k
MPSA70
~~~
., 1----,
,
(0.08
MJ4030
H
LOAD
~
100
2.0W
MJ4030
K2N3903
2N3903
12 k
1
-
MJ4033
MJ4033
OFF
1
FIGURE 7-27 -
R
"H" SWITCH DARLINGTON CIRCUIT '
MOTOROLA TMOS POWER MOSFET DATA
A-90
I
6.2k
3.9 k
>-12 k
1.1
EFF=~
VDS(on) = 0.9 V @ 15 A, VGS = 20 V
VDS(on) = 0.12 V @ 2.0 A, VGS = 20 V
BIAS CIRCUIT Po = 0.01 W MAX
MTR Po = 12.2,2.0 V x 15 A
= 183W
MTR Po = 13.76 V x 2.0 A
= 27.5W
27 + 183
= 87% STALL MODE
27.5
EFF = 0.48 + 27.5
= 98% RUN MODE
+34V>-_-..
~-.....--<+34V
680 k
680 k
+34 v+f)
200 k
~:o~;:;.1
200 k
100 k
100 k
I'
FIGURE 7-28 -
"H" SWITCH POWER TMOS CIRCUITS
"H" SWITCH DESIGN COMPARISON CHART FOR AUTOMOTIVE MOTOR LOAD
54%
68%
13.2V 10.4 V High base current required
Darlington
200
60V
16A
1.1 V
3.0V
1.1 W 4.2W
90W
81%
57%
11.8V
TMOS
176
40 V
20 A
0.12 V
0.9 V
0.01 W 0.48 W
27 W
98%
87%
13.8 V 12.2V 34 V 200 pA Bias supply
required
Bipolar
NOTES:
1) Bipolar devices are TIP35 and TIP36 T0-218 plastic NPN and PNP
2) Darlington devices are MJ4030 and MJ4033 TO-204 (TO-3) metal NPN and PNP.
3) TMOS devices are MTP25N05.
4) Figures shown above are the worst case data sheet condition for the parameter calculated.
MOTOROLA TMOS POWER MOSFET DATA
A-91
8.0V.
Large forward voltage drop
•
MOSFETs Improve Motor-Drive Efficiency
The Darlington tranSistors, sense the motor's counter
EMF (via the 20 V snubber zeners that become forward
biased when the motor's back EMF appears) and shunt
the drive-reversal signal to ground until the back EMF
decays. The transistors will hold the gate-drive line low
until the counter EMF drops below the base-to-emitter
threshold voltage. This action causes the circuit to wait
until the motor nearly stops rotating before applying reverse Voltage. If faster response times are needed, the
Darlingtons can be eliminated while connecting the 1.0
MO base resistors to ground - this change, however,
would necessitate higher current MOSFETs because of
the large peak-reversal currents that would ensue.
Figure 7-30 shows the dramatic difference in the peak
currents that occur with and without the back-EMFsensing feature. With the sensing circuit disabled (a), the
currents exceed 50 A; the resulting MOSFET dissipation
is approximately 140 W. Enabling the circuit (b) reduces
the currents to approximately 30 A and the MOSFETs'
dissipation to about 14 W. A 16 V zener diode limits the
By using power MOSFETs in Figure 7-29b's circuit,
fractional-horsepower motors can be driven bidirectionally
with only a small percentage'of the base-drive power that
bipolars require. Moreover, by sensing the motor's back
EMF and delaying drive-voltage reversal, the circuit
reduces the peak currents encountered during motor
reversal. This feature allows theus'i! of lower current
MOSFETs than an instantaneous-reversal method would
dictate.
A basic H switch, Figure 7-29a reverses the motor's
supply voltage for bidirectional control. In Figure 7-29b's
circuit, two pairs of N-channel MOSFETs serve as the,CW
(clockwise) and CCW (counterclockwise) switches. A
flyback-type dc/dc inverter, composed of a CMOS hex
inverter and a small signal MOSFET, drives the FET
switches. The 3-inverter oscillator operates at 240 kHz;
the three remaining inverter's average output tracks the
power-supply input, ensuring adequate gate-bias voltage
even for input-supply voltages as low as 6.0 V.
+1
......--oSupply
r----------_-:-::o=~:---.._-
1+
CW~M
CCW
28 V Suppressor
r-'2\1\O"'V......--'I-...
Motor
i
CCWt
MR2530L
100k
lN5250
CW
(a)
g
t-----.
1.0M
2N6427
1.0 M
CWoff CCW
100 k
2N6427
DPDT (Center Off)
0.1 p.F
Flyback Inv. Waveforms
(b)
FIGURE 7-29 - DRIVE FRACTIONAL-HORSEPOWER MOTORS
EFFICIENTLY WITH THIS POWER·MOSFET H-BRIDGE CIRCUIT. IT
DISSIPATES MUCH LESS POWER THAN A BIPOLAR-TRANSISTOR
DRIVER - MOREOVER, IT ALLOWS THE USE OF LOW-CURRENT
MOSFETs BY DELAYING REVERSAL VOLTAGE UNTIL THE MOTOR
COASTS TO A STOP.
MOTOROLA TMOS POWER MOSFET DATA
A-92
input voltage to the flyback inverter in case the supply
rises higher than 16 V; the transient suppressor protects
the MOSFETs from supply spikes greater than 28 V.
In this design, the MOSFETs require heat sinking to
keep their junction temperatures less than 150°C in worstcase conditions (that could occur, for example, with a
16 V supply, 100°C ambient temperature and a stalled
motor). As an option, a current-sensing circuit can be
added to gate-off the power FETs aiter detecting a stall
condition.
modulated control with a minimum number of components. The key feature is direct drive of the power FET
from a CMOS control IC. The result is a control system
with minimized parts count.
The control system is based upon the MC14528B dual
monostable multivibrator. One-half of the monostable is
connected in an astable mode, producing a pulse oscillator. The remaining half is then used as a one-shot, with
its adjustable pulse-width determining the duty cycle and,
therefore, motor speed.
In addition to its simplicity, the circuit of Figure 7-31 is
notable for its low standby power drain. The combination
CMOS control and TMOS power gives a very low quiescent current drain that is desirable in battery operated
applications.
PWM MOTOR Speed Control
FETs can be used to considerable advantage for simplifying permanent-magnet motor speed control. The circuit shown in Figure 7-31 provides efficient pulse-width
BACK EMF SENSE
CIRCUIT DISABLED
PEAK CURRENTS> 50 A
POWER DIS. = 140 W
10 AlDIV
(a)
1.0 SECIDIV
BACK EMF SENSE
CKTENABLED
PEAK CURRENT
~
30 A
POWER DIS. = 14 W
10 AlDIV
(b)
1.0 SEc/DIV
VERTICAL
HORIZONTAL
10 AlDIV
1.0 SEC/DIY
FIGURE 7-30 - COMPARISON OF "H" SWITCH PEAK CURRENTS
DURING MAXIMUM FORWARD TO REVERSE SWITCHING WITH
MANUAL TOGGLE SWITCH
MOTOROLA TMOS POWER MOSFET DATA
A-93
II
Other Applications of Power MOSFETs
HORIZONTAL DEFLECTION CIRCUITS
Power MOSFETs can be a good alternative to bipolars
in high resolutiOn CRT sweep circuits. The most obvious
advantage is simpiicity. However, MOSFET horizontal
outputs also offer significant benefits in terms of increased
reliability and faster switching times.
Drive simplification with the MOSFET is even more significant than in the preceeding switching power supply
examples. In most cases, a base-drive transformer is eliminated, as well. as di/dt wave shaping networks.
The reliability issue is a little more complex, and relates
to differences in SOA characteristics. It is normal design
practice to exceed bipolar collector-emitter breakdown ratings during the retrace pulse transition. This is permissible
if the base-emitter voltage is held negative during the
retrace period. If, however, a positive noise pulse occurs
during the retrace period, the bipolar base-emitter junction
can become forward biased when collector-emitter voltage is greater than VCEO(sus)' The bipolar's safe operating area is then violated, creating a substantial risk of
failure. MOSFETs, on the other hand, will handle this type
of stress quite readily, since their FBSOA capability extends beyond peak retrace voltage. Therefore, increased
reliability with the MOSFET horizontal output is directly
related to the probability of noise occurring in the drive
circuitry.
Speed is also an important issue. At a 30 kHz scan
rate, 1.0 JLS of bipolar storage-time delay represents 3%
of the horizontal line period, or a loss of 30 lines of data
in a field of 1024 lines. In addition, bipolar storage time
is not a fixed constant, but changes from device to device
and with temperature. A horizontal phase locked loop can
be added to compensate for the storage-time delays in
the horizontal output stage. The active video data time
may also be cut back, accordingly, to allow for internal
horizontal timing delay.
Based upon these considerations, effective use of the
bipolar transistor at high scan frequencies requires a complex base drive Circuit, custom selection of the bipolar
device for minimum storage-time variation, and an accurate phase locked loop to compensate for saturation
time delays. Power MOSFETs, on the other hand, can be
driven from a CMOS IC, do not require critical parameter
screening, exhibit minimal turn-off delay, and do not require a phase locked loop for correcting device-induced
timing errors.
DeSign Example
The power MOSFET, until recently, could not handle
much current at voltages above 500 V. Recent technology
developments have pushed this limit up to the 1000 V
range with increased current ratings. Therefore, a power
MOSFET can now be selected for computer CRT display
systems with power supply requirements ranging from
12 V to 75 V.
The standard horizontal raster scan system is used in
this design. That is, the horizontal yoke and flyback transfOrmer are both switched by one output device. It should
be pOinted out that the power MOSFET has been switched
up to 120 kHz scan rates, but due to other device constraints, the CRT anode high voltage network's performance is very marginal at this high frequency rate. Even
a scan frequency of 30 kHz is pushing the limits of the
high-voltage rectifier and associated components.
On/Off
+14V
lN5246 16 V
'::'
I
I
,
1.0 k
I adj
50kl sPd
2.0 k
0.1 p.F
T1
T2
Co VCC
Tl
T2
CD
10 k
1.0M
MC14528B
lN918
Power MOSFET
15 k
S
FIGURE 7-31 - POWER
MOSFET MOTOR SPEED CONTROL CIRCUIT
MOTOROLA TMOS POWER MOSFET DATA
A-94
MTP5N05
2.0 A MTR
MTP15N05
MTP25N05
6.0 A MTR
15 A MTR
MTE100N05
60 A MTR
The design concept is shown in the block diagram of
Figure 7-32. The horizontal drive signal can be supplied
by a free running synchronous clocked oscillator or by
extemal computer logic. The safest method is to use a
free running synchronous oscillator to insure the horizontal frequency is held within safe limits. There are several
horizontal processor linear integrated circuits containing
a phase detector, oscillator and predriver available. A partiallist includes SGS TDA1180 and Motorola MC1391.
None of these devices are presently designed to drive a
MOSFET power unit directly; so some type of an interface
or buffer circuit is required. Three power MOSFET drive
circuits are shown in Figure 7-33. These circuits perform
adequately in the horizontal system described here.
Essentially, the prime requirement for driving the power
MOSFET for this horizontal scan output design is to insure
sufficient gate on-voltage and low enough impedance for
a fast turn-off transition. Since the power MOSFET has a
high gate input impedance, the gate voltage requirement
is easily met, with little wasted power. The off transition
requires that the power MOSFET's internal 1000 pF gate
capacitance be discharged very quickly. This is accomplished by using a single hex inverter IC, with all the gates
wired in parallel. As mentioned before, other devices can
be used to drive the MOSFET. The CMOS inverter was
chosen to show that CMOS technology is sufficient to
drive the MOSFET.
The system described above provides excellent performance. The gate-drive voltage of the power MOSFET
was purposely pulsed during the peak retrace drain voltage pulse to simulate destructive transients due to anomalies such as arcing.
It was found that a controlled drain-to-source current
occurred, with no catastrophic failures, as long as the total
power dissipation was held within the limits of the power
FET's safe operating area ratings. Figure 7-34 shows the
waveforms associated with the retrace pulse test. Since
the MOSFET is a high input impedance device, it is important to insure the gate of the power MOSFET is at a
low impedance during the retrace period. The gate should
not be driven negative, to minimize the possibility of voltage spikes causing gate avalanche. The gate cannot withstand an avalanche condition of any measurable current
intenSity and survive. Since the power MOSFET device
selected for this design exhibits at least a 2.0 volt threshold, a negative gate-drive is not important.
Circuit Description
The design presented in Figure 7-34 eliminates the
driver transformer, driver transistor, and associated passive components that would normally be found in a bipolar
design. A MLM311 comparator is used to invert and levelshift the incoming positive going synchronous pulse. The
comparator output is ac coupled to the MC1391 horizontal
processor which consists of a phase comparator and voltage controlled oscillator with adjustable duty cycle. The
phase comparator of the MC1391 is connected to the
incoming conditioned horizontal synchronous pulse and
the output of the MC1391 's internal oscillator. An error
voltage is applied to the oscillator timing control voltage
to lock in the external synchronous pulse and the oscillator. The duty cycle of the MC1391 oscillator output is
set to provide a 63% "ON" time to the power MOSFET
gate.
+
+12V
H.V.
Power
MOSFET
I
I
I
I
-=-
I
IIII
I
I
I
Sync
Horiz. Processor
II
CR
I Gate
I Driver
I
Ly
I
JCS
I
I
I
I
I
Horiz.
Phasing
FIGURE 7-32 - POWER MOSFET HORIZONTAL OUTPUT SYSTEM
MOTOROLA TMOS POWER MOSFET DATA
A-95
Figure 7-35 shows a comparison of the key horizontal
output· circuit waveform patterns between a bipolar and
MOSFET design. Note the large reduction in the horizontal output drive power and lack of storage time in the
MOSFET design.
when driven by a low-voltage source, sacrifice switching
speed.
Yet a third possible solution - paralleling fast, lowcurrent transistors- presents two problems: current sharing and physical layout.
The MOSFET driver circuit in Figure 7-36 uses two
N-channel devices with positive and negative polarities.
Fast transitions are possible, even when a low-voltage
source is used. The circuit returns to 0 V between pulses,
an important feature when driving high-power Darlington
transistors with base-bias resistors and speed-up diodes.
In· this case, excessive hEiating would otherwise occur
during the off-time interval.
Small size, simple configuration, and· minimum component count join with ease of operation to make this driver
circuit very useful for applications in variable-frequency
switched-mode power supplies, and inverters.
In operation, a single-polarity, negative-going pulse
from a pulse generator is applied to the input. The pulse,
whose width can vary anywhere from 5.0 JLS to 3.0 ms,
turns on PNP predriver transistors Q2. for the positivepolarity output.
FAST HIGH-CURRENT MOSFET DRIVER
A totem-pole MOSFET driver circuit shines when highcurrent, fast-transition pulses must be generated from lowvoltage sources. ItsMOSFETs sidestep a number of problems that their bipolar counterparts present in the same
circuit.
High-speed transistors and high-current transistors intended for PWM applications have created a need for
high-current, fast-drive circuits. Transistors that demand
20 to 35 A of reverse base current for rapid turn-off and
can be driven by as little as 5.0 V of off-voltage are a
common requirement. Bipolar devices switch in nanoseconds but are limited to 5.0 to 10 A when driven from lowvoltage collector supplies. With higher current capability,
such transistors require power transistors as drivers and,
+12V
+12V
S·
1.0 k
VCC
2.0 k
5.0 V Pulse >--""",,'Ir-~i. MPS5172
Out
1-'3'---_--.
1.0 k
Discrete
Linear Bipolar IC
MCl455
+12V
Horiz•
..------i Output
D
5.0 V Pulse
~
MOSFET Output
MTMSN20 thru
MTM5N100, etc.
G
S
FIGURE 7-33 - MOSFET DRIVE CIRCUITS
MOTOROLA TMOS POWER MOSFET DATA
A-96
Circuit
+24V
MC78L12
+12_ +75V
+12V
+
!10,.F
§
MLM311
Horiz. Flyback
0
:0
0
>
-I
s::
& High Voltage
Network
20 k
CRT Anode V.
CRT Control V.
g
~
~
"tJ
~
m
:0
s::
en
"TI
0
'::'
~
0
»~
h
O.D1.L
,.F
..
.
2,4,6
10,12,15
5~ ~orizontal
10
'::'-
Processor
,"_M,..
~.
,-------------------------------------------
(All Inverters
- " ....,""
'::'
___ J
..
----------
]
Horiz. Yoke
Network
Power MOSFET
Select Device Type
Per Voltage & Current
Requirements.
FIGURE 7-34 - POWER MOSFET HORIZONTAL SWEEP DESIGN
II
II
r-----------'---- EXTRA IINJECTEDI HORIZ. DRIVE PULSE
GAlE DRIVE
VGS
10V/DIV
VDS
100 VIDIV
HORIZ. FLYBACK PULSE
--
10
10 AlDIV
-I
t
2.0 "",DIV
•
+
I
'.
,
j
.,
-
-
HORIZ. OUTPUT DEVICE CURRENT
j--
, - - - - - - - - - - - - - - - - - - - - PULSE ADJUSTED TO COINCIDE
DURING PEAK OF FLYBACK PULSE
VGS
10 VIDIV
VDS
500 V/DIV
10 MDIV
t
2.01-'slDIV
. . . . - - - - - - - - - - - - - - - - - - - - A S A B O V E , EXCEPT PULSE WIDTH
EXlENDED TO 1.0 ""
•
VGS
10 VIDIV
VDS
500V/DIV
10 AlDIV
t
2.0 !'SIDIV
FIGURE 7-35 - HORIZONTAL DEFLECTION RETRACE PULSE TEST WAVEFORMS
MOTOROLA TMOS POWER MOSFET DATA
A-98
BIPOLAR
toft = 3.5 p,s
II
MOSFET
toft = 155 ns
versus
Video
Video
18
1.0 AlOIV
IG
1.0 AlOIV
IC
5.0 AlOIV
5.0 AlOIV
'0
-
VOS
500 V/OIV
VCE
500 VIDIV
- I
L
~
Compl.te Waveforms
Video
Video
IS
IG
IC
10
1.0p.slOIV
Time Expanded
I
I
-1-----1 IG
0.5 AlDIV
-
- --1I
1
I
Note:
External Damper
Rectifier left
in ckt to minimize
ringing during start
of negative yoke current
10
1.0AlDIV
MOSFET CURRENTS EXPANDED
TURN-OFF WAVEFORMS
FIGURE 7-36 - BIPOLAR versus MOSFET
MOTOROLA TMOS POWER MOSFET DATA
A-99
I
IliJ!!
10 !'5iDIV
I
•
ration of the negative drive. The negative voltage remains
for about 10 p,S and then returns to zero, completing a
single cycle.
The circuit can be used with FETs by replacing Rb with
a short and the positive and negative voltages applied to
the devices' gates. For controlled gate-impedance drive,
resistors can be inserted in series with the gates. Similarly,
a resistor added in series with the base of the bipolar
transistor results in controlled base-current drive.
Resistor Rb, inserted in series with the drain lead of 02
and the supply, sets the positive drive level. The resistor
should be selected for a drive of 10 V or greater as well
as the amount of desired current.
After the required on-time of the positive output current,
the pulse generator returns to zero. Then, the RG. differeritiator netw~rkapplies a positive voltage to the gate of
MOSFET 03, which supplies the negative polarity output.
The values shown can be changed to lengthen the du-
Rb
10
0-,
-v U
+
r
10 /LF
MTM12N08
10
Output
Input
50
R
500
2.0/LF
100
'C'
-v
FIGURE 7-37 - MOSFET DRIVER CIRCUIT
MOTOROLA TMOS POWER MOSFET DATA
A-100
Chapter 8: Spin-Off Technologies of TMOS
The GEMFET Control
A New Option for Power
pier and more efficient. Oarlingtons also simplify drive
requirements, but on-VOltage is compromised in doing so.
.So~etimes MOSFETs are used in low frequency applications because of their simple gate-drive requirements. In many low frequency, high voltage circuits, replacement of the MOSFET with a GEMFET improves
efficiency or reduces the cost of the switch. Because their
structures and gate-drive considerations are so similar
the change usually entails no significant circuit modifi:
cations. Substitution of a GEMFET with approximately the
same die area dramatically improves on-state efficiency
and current ratings.
If cost is a major concern, another option is to replace
the power MOSFET with a GEMFET that has a smaller
die area. The result can be a device with a similar current
rating and comparable on-state losses. Except at higher
frequencies, the cost/performance tradeoffs are substantially in favor of the GEMFET.
The GEMFET is suitable for high current, high voltage,
low frequ~ncy applications because of its low forward drop
and relatively long turn-off time. Appropriate applications
for the GEMFET include motor drive circuits, automotive
switches, programmable controllers, robotics, home appliances, machine tools, etc.
The ~orld of f:lOwer switching is constantly searching
for the Ideal sWitch. Such a switch would have infinite
resistance in the off-state, zero resistance in the on-state
instantaneous switching times, and require zero input
power to operate. In a real switching application, one must
choose the device that most closely approximates the
ideal switch for that particular application. The choice involves considerations such as voltage, current, switching
frequency, drive circuitry, inductive loads, temperature effects, etc. Every switching device has its strong pOints
and weak points and the designer is always forced to
make trade-offs to find the best switch for a given situation.
For a solid state switch, the three characteristics that
are most desirable are fast switching speeds, simple drive
requirements and low on-state losses. In low voltage applications, the new generations of power MOSFETs have
very low on-resistance and closely model the ideal switch.
But in high voltage devices, comparatively high onresistance still limits the MOSFETs efficiency. Furthermore, future advances in decreasing rOS(on) will become
more difficult as on-resistances fall closer to the theoretical minimum, which is determined by the optimum cell
geometry and the resistivity of the N-epi layer. Therefore,
subsequent I.arge r~ductions in rOS(on) of high voltage
MOSFETs will require new technologies.
The GEMFET (gain Enhanced MOSFET) is the result
o! one such technological advance. It is a relatively new
high voltage power semiconductor device with a combination of characteristics previously unavailable to the designer of power circuitry. Closely related to the power
MOSFET in structure, this new device has forward voltage
?rop ~mparable to bipolars while maintaining the high
Input Impedance and fast turn-on associated with the isolated gate of the MOSFET. Although turn-on speeds are
very fast, current fall times of approximately 4.0 ,."S are
quite slow, and may restrict the use of at least the first
~eneration of these devices to lower frequency applications.
At switching frequencies below about 10kHz, however,
the GEMFET is an attractive alternative to the more traditional bipolars, power MOSFETsand thyristors. Compared to a standard thyristor, the GEMFET is faster and
has a higher input impedance, better dv/dt immunity and,
above all, gate turn-off capability. While some thyristors,
e.g. GTOs, can be turned off at the gate, this requires
substantial reverse gate-drive current, whereas, turning
off the GEMFET requires only that the gate capacitance
be discha!ged. On the other hand, thyristors generally
have a slightly lower forward drop and a higher surge
current rating than a comparable GEMFET.
In a comparison of drive requirements;, the GEMFET
clearly outperforms bipolar transistors. In a 10 A application, for instance, the bipolar requires 2.0 A of base
drive (assuming a beta of 5.0) while the GEMFET requires
only nanoamperes of gate current to remain in the "on"
s!ate. Without the large base"drive current required by the
bipolar, the GEMFET gate-drive circuit can be much sim-
DEVICE STRUCTURE
The GEMFET is very similar to the double-diffused
power MOSFET. Simply by varying starting materials and
by altering certain process steps, a GEMFET may be
produced from a power MOSFET mask set. Figure 8-1
Illustrates that the two structures are identical except for
the P + layer adjacent to the drain metalization. Additional
current carriers in the form of holes are injected from the
P + substrate into the normally high resistivity N-epi layer
and markedly reduce the on-voltage. The resulting four
layer structure (P-N-P-N) allows current densities much
greater than those attainable in power MOSFETs and
comparable to those of bipolars.
Like the power MOSFET, the gate of the GEMFET is
electrically isolated from the rest of the chip by a thin layer
?f Si02. Accordingly, the GEMFET is also a high input
Impedance device and exhibits the associated advantages of modest gate-drive requirements and excellent
gate-drive efficiencies. The uniqueness of the GEMFET
is that low on-voltages as well as high input impedances
are now available in high voltage power semiconductors.
The symbols and equivalent circuits of the GEMFET
and MOSFET are shown in Figure 8-2. Because of its
four layer structure, the GEMFET lacks the parasitic drainsource diode common to nearly all power MOSFETs.
DEVICE CHARACTERISTICS
Output Characteristics
In the forward conduction mode; the GEMFET closely
resembles a power MOSFET. The equivalent circuit is
best modeled as shown in Figure 8-2 in which a low voltage, !ow rpS(on), N-Channel MOSFET is driving a PNP
transistor In a compound configuration. The PNP device
not only helps lower the effective rOS(on), but also en-
MOTOROLA TMOS POWER MOSFET OATA
A-101
II
•
Source Metalization
Drain
Gate Oxide
r-1
Polysilicon' Gate
IV...!
~
~
o::Jq
II'::
SQurce
~'~
P
N-Epi
I
~~
(
MOSFET Symbol
P
Source
MOSFET
Equivalent Circuit
JDrain
N+ Substrate
!
o::J'l Gd
Drain
FIGURE B-1. - CROSS SECTION OF TMOS CELL
Source
Source Matalization
Source
GEMFET Symbol
Gate'Oxide
GEMFET
Equivalent Circuit
FIGURE B-2 - MOSFET AND GEMFET
SYMBOLS AND EQUIVALENT CIRCUITS
Polysilicon Gate
8.0
ie
:z
$
....
z
7.0
6.0
~
a: 5.0
13
z
~ 4.0
0
£. 3.0
2.0
Drain
1.0
FIGURE B-1b - CROSS SECTION OF GEMFET CELL
U
U
M M ro
U
M W
~
~
VOS, ORAIN-TO·SOURCE VOLTAGE (VOLTSI
FIGURE 8-3a - OUTPUT CHARACTERISTICS
OF POWER MOSFET (MTP4N50)
hances the device gain (transconductance) at high drain
currents. Except at excessive drain currents or junction
temperatures, the NPN device is considered to be a parasitic and does not influence circuit operation.
The output characteristics of a popular power MOSFET
(MTP4N50) and a GEMFET (MGP20N50) of identical die
dimensions and similar breakdown voltages are shown in
Figures 8-3a and 8-3b. The two major differences between the curves are:
1 -
The GEMFET has a much lower on-resistance at
currents greater than 2.0 A.
2 -
Before the GEMFET can conduct current, the P-N
junction formed by the P + substrate and the
N-epi layer must be forward biased. Consequently, the GEMFET curves a,re offset from the
origin by a diode drop, similar to SCRs or DarIIngtons.
Figure 8-4 indicates that at 25°C the 20 A, 500 V
MGP20N50 gives no hint of a propensity to latch at currents up to 62 A, which is much larger than the pulsed
current rating of the MOSFET.
2.0
4.0 6.0 8.0 10
12 14 16
18
VOS, ORAIN-TO-SOURCE VOLTAGE (VOLTSI
FIGURE B-3b - OUTPUT CHARACTERISTICS
OF GEMFET (MGP20N50)
MOTOROLA TMOS POWER MOSFET DATA
A-102
20
70
I
Even though MOSFETs are championed fortheir simple
gate-drive requirements, at high operating frequencies
sizable peak gate currents must be supplied to ensure
rapid switching. Since this first generation GEMFET is, by
comparison, much slower, the gate drive-impedance can
be fairly high without affecting tum-off speeds. In the circuit shown in Figure 8-6, RG was varied from 0 to 1.0 kll,
but the current fall time essentially remained constant at
3.75 pS (Table 1).
60
60
I-
1l'i 40
~
a
z
~
30
20
10
2.0 4.0 6.0 8.0 10 12 14 16
VOS, ORAIN·TQ·SOURCE VOLTAGE (VOLTS)
18
v+--u-
FIGURE 8-4 - OUTPUT CHARACTERISTICS
OF GEMFET AT HIGH DRAIN CURRENTS
I
I
I
oIL
Switching Speeds
Presently, the feature that limits the GEMFET from serving a very wide range of applications is its relatively slow
turn-off speed. While turn-on is fairly rapid, current fall
times at turn-off can exceed 4.0 pS.
The tum-off of the GEMFET is rather slow because
many minority carriers are stored in the N-epi region.
When the gate is initially brought below threshold, the
N-epi contains a very large concentration of electrons,
consequently, there will be significant electron injection
into the P + substrate and a corresponding hole current
into N-epi.
As the electron concentration in the N-region decreases, the electron injection decreases, leaving the rest
of the holes and electrons to recombine. The tum-off of
the GEMFET should then have two phases: the injection
phase where the drain current falls very quickly; and a
recombination phase where the drain current decreases
more slowly. Figure 8-5 shows the clamped inductive turnoff waveforms of the MGP20N50.
Although tum-off speeds are not impressive, this is the
first generation of these devices and improvements in
switching speeds can be expected. For GEMFETs, there
is an rOS(on) - switching speed trade-off. Theoretically,
tum-off times can be decreased without large increases
in rOS(on) by controlling carrier lifetimes or by other Proprietary methods.
FIGURE 8-6 - CIRCUIT TO TEST
VARIATIONS IN CURRENT FALL TIMES WITH
CHANGES IN GATE DRIVE IMPEDANCE
TABLE 1 - Effect of Series Gate
Resistance on Turn-off Speeds
Series Gate
Resistance
500
1000 2000 5000 10000
140 ns 140 ns 150 ns 180 ns 350 ns 810 ns
Drain Current
Fall Time
3.75 JLS 3.75 JLS 3.75"s 3.75 JLS 3.75 JLS 3.75"s
Comparison of On-State Losses
The most pronounced advantage of the GEMFET over
the power MOSFET is its lower on-resistance. The
VOS(on) of a high voltage MOSFET is fairly large and
rises with increasing junction temperature and drain current. Conversely, the VOS(on) of a GEMFET decreases
with increasing TJ and is not greatly affected by '0. Figure
8-7 compares the on-voltages of the two technologies at
various drain currents and at a TJ of 25°C and 100°C.
Since the MOSFET does not have the GEMFET's offset
voltage in its output characteristics, at low currents the
MOSFET on-voltage is slightly lower. However, as the
illustration suggests, at high currents and temperatures
the difference is dramatic. For comparison, a bipolar transistor was also included in Figure 8-7. Its on-VOltage is a
function of the transistor'S high current beta and the magnitude of the base current.
On-state efficiencies are not solely determined by onvoltages. Gate or base-drive currents are also contributing
factors. Its high input impedance allows the GEMFET to
rival the on-state efficiency of the bipolar transistor, even
though its on-voltages are comparable to those of SCRs
(one diode drop in addition to a bipolar saturation voltage).
The bipolar device chosen for this comparison had a
forced beta so low (about 5) at the desired collector current
that the base current losses were important.
10
1.0AIDIV
Vos
50 VIDIV
0.5 "wo1V
AGURE 8·5 -
00
Drain Voltage
AiseTlme
CLAMPED INDUCTIVE TURN·OFF
OFGEMFET
MOTOROLA TMOS POWER MOSFET DATA
A-103
II
,
II
14
12 I - f-~OJR I
MOSFEl
11 l - f- TJ=
10
9.0
I
II
~ 8.0
~
!:;
7.0
6.0
~
0
I
5.0
4.0
/ J
3.0
2.0
1.0
J
~
/
1\ MOSFET
/
'J
.\
.\
1/
10Cffi
.
~
80
II
13
TJ = 25'C
I
1\
1/
"-
I
II
I
V
GEMFET
oo
To illustrate the variation in the on·state efficiencies of
each technolOgy, a biPolar transistor, MOSFET and
GEMFET were used as the switching element in an open
loop PWM dc motor control circuit. The bipolar
(MJEl3007) was a 156 x 156 mil chip rated at 8.0 A, 400
volts. The 20 A, SOO volt GEMFET (MGM20NSO) and the
4.0 A,500 volt MOSFET (MTP4N50) had areas equivalent
to a die size of 150 x 150 mil. To keep switching losses
to a minimum, the frequency waS held constant at about
90 Hz as the duty cycle was varied from 9% to 71 %. Since
a motor is a nonlinear load and conditions such as motor
speed and back EMF change with pulse width, the results
TMOS
MJE13007
T = 11.2ms
1. Even though its on·voltage is very low, the bipolar
is not the most efficient device at high duty cycles.
The power consumed by the device due to its large
base current is great enough to be reflected in an
increase in case temperature. Because of the bi·
On-State Efficiency Testing: Pulse Width Modulation of DC Motor
Case
Temp
(GC)
Power
Dissipation
(W)
On
Voltage
(Volts)
VDsor
VCE'fsk)
(Vol s)
Relative
Power
Out
(Speed)
0.69
0.70
0.75
0.79
0.86
1.0
1.1
1.1
1~5
2.0
1.75
2.0
2.5
78
77
73
4~0
64
6.5
49
2.0
2.0
2.0
2.0
2.0
0.75
0.80
1.25
2.25
3.50
37.2
37.4
38.5
39
40.9
' 38.6
42.1
49.4
62
77.4
'0.76
0.91
1:22
1.77
2.44
1.0.
1.3
2.0
4.5
7.5
1.75
2.25
3~25
' '6.50
,,11.,00
78
.. 2.0
77
2.0
70
48
18,
2~0
0.80
1.1
1.5
2.75
4.5
49.7
45.7
40.7
34.8
32.6
1.24
1.06
0.85
0.59
0.50
0.1
0.2
0.2
0.3
0.5
82
81
78
70
59
140
104
72
36
20
Pulse
Width
(ms)
Duty
Cycle
%
ID(max)
(A)
8.0
6.0
4.0
2.0
1.0
71
54
36
18
9.0
0.75
1.0
1.6
2.75
4.50
8.0
6.0
4.0
2.0
1.0
71
54
36
18
9.0
71
8,.0
6.0
4.0
2.0
1.0
100
80
of the comparison (Table 2 and Figure 8·8) should be
carefully interpreted.
The "relative power out" referred to in Table 2 is simply
a measurement proportional, to the motor speed and is
inversely related to the saturatio!,!. voltage. If the on·
voltage is high, the potential across the motor is dimin·
ished and the speed is decreased. The "relative power
in," a measure of forward base (or gate) current, is useful
for comparing the required base or gate power necessary
to control a five ampere load.
The following generalizations can be drawn from Table
2 and Figure 8·8:
FIGURE 8-7 - ON·VOLTAGE versus DRAIN OR COLLECTOR
CURRENT FOR A GEMFET, I/IOSFET AND BIPOLAR OF
EQUIVALENT DIE SIZE
GEMFET
60
RGURE 8-B - ON·STATE EFFICIENCY COMPARISON PULSE WIDTH MODULATION OF DC MOTOR
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10
10. DRAIN CURRENT OR IC. COLLECTOR CURRENT lAMPS)
TABLE 2 -
G~~FET
40
DUTY CYCLE 1%)
It- V
~ I-"
'i--""
20
...L. 6==
Il
iI=i TJ = 10Cf':'
......
MJEl3007
BIPOLAR
Ielis = 5.0
TJ = 25'C
BIPOLAR
"'- ~ .- i--'"
.- i'---
54
36
18
9.0
1=90Hz
Voo = 14 V
R6HS = 23'CIW
MOTOROLA TMOS POWER MOSFET DATA
A·104
0:8
1.0
1.5
3.0
5.0
Relative
Power
In
2.0
2.0
Switching Losses
The present maximum operating frequency of the
GEMFET is limited by its turn-off speed. Oefining a specific upper limit could be misleading because the frequency limitation depends on heat sinking, drain current,
drain supply voltage, gate-drive impedance, and drainsource flyback voltage. To set a benchmark for a specific
set of conditions, the following test circuit and procedure
was developed to compare the switching efficiencies of a
GEMFET (MGP20N50), MOSFET (MTP4N50), and bipolar (MJEI3007).
In the test procedure, the independent variable was
switching frequency, which was varied by changing the
timing capacitor CI in the test circuit shown in Figure 8-9.
By adjusting potentiometer AI and by properly sizing the
inductive load, the load current waveform was fixed to a
25% duty cycle and a peak of 5.0 A.
For the MJEI3007, the forced beta of 5.0 required a
base current of 1.0 A. Tum-off of all three types of devices
was initiated by clamping the base (or gate) to - 5.0 volts.
The oscillograms in Figure 8-10 show the drain (or collector) current and drain-source (or collector-emitter) voltage of each device at 7.0 kHz.
Again, the test results were quite predictable, and the
case temperature versus frequency for this specific case
is plotted in Figure 8~ II. The efficiency of the heat sink,
in this instance a 4112" x 4'12" x Va" copper plate (AOCA =
5°CfW), markedly influences the temperature rise results.
A larger or smaller heat sink would have decreased, or
increased, the noted temperature differences. The testing
was restricted to lower frequencies because above 40 kHz
polar's low beta, the case temperature and power
dissipation closely track the relative power in.
2, The bipolar invariably results in the highest motor
speed for a given pulse width because its saturation
voltage is always lowest.
3. For the MOSFET, high on-resistance, especially at
higher currents and temperatures, influences the
performance. As the duty cycle decreases, the motor
speed and back EMF also decline. With the lower
back EMF, the effective motor voltage is higher, allowing higher currents. The increasing current and
on-reSistance combine to elevate the case temperature at low duty cycles.
4. The case temperature of the GEMFET remains aimost unchanged as conditions vary. Unlike the bipolar, its input power is very small and does not
significantly affect the power dissipation at high duty
cycles. At lower duty cycles and higher currents, the
GEMFET on-VOltage is much lower than the
MOSFET's. Again, the result is cooler case temperatures.
While the GEMFET looks quite respectable in this comparison, the peak current chosen influences the relative
efficiencies. If the motor supply voltage had been increased to obtain larger peak currents, the comparison
would have been even more in favor of the GEMFET. The
MOSFET would have performed more poorly due to its
IO-rOS(on) relationship, and the bipolar's base drive
losses, due to forced betas' less than 5.0, would further
reduce its efficiencies at large pulse widths.
V+
100 k
0.01 pJ
lN914
1.5 k
-5.0V
FIGURE 8-9 - CIRCUIT TO COMPARE SWITCHING EFFICIENCIES
OF GEMFET, MOSFET AND BIPOLAR
MOTOAOLA TMOS POWEA MOSFETOATA
A-I 05
•
I
I
i
VOS
looV/OIV
10
2.0 A1DIV
20l"lDIV
20 I"IOIV.
FIGURE 8-10b - CLAMPED INDUCTIVE SWITCHING
WAVEFORMS AT 7.0 kHz ~ MOSFET
FIGURE 8-108 - CLAMPED INDUCnVE
SWITCHING WAVEFORMS AT 7.0 kHz - GEMFET
200
180
II IIII
. II
~m.120N50
= ICM = 5.0 A
GEMFET /~
DUTY CYCLE = 25%
~
~ 140 -TA = 25'C
~ 120 - HEAT SINK = 4" x 4"x Vs" COPPER PLATE
/
~ 100
.r
160 ~IDM
VCE
lOOV/DIV
::E
~
~
IC
2.0 AIOIV
,9
80
60
MTP4N50
MOSFET
40
20
20l"lDIV
i'POiAi
o
1.0
0.1
FIGURE 8-1Oc :.... CLAMPED INDUCTIVE SWITCHING
WAVEFORMS AT 7.0 kHz ~ BIPOLAR
~
JJE13OO7
10.0
100
SWITCHING FREQUENCY (kHz)
FIGURE 8-11 - COMPARISON OF CASE TEMPERATURE
versus FREQUENCY FOR A GEMFET, MOSFET AND BIPOLAR
secondary effects began to influence and distort the comparison.
The GEMFET switching losses rose rapidly with frequency, illustrating its high-frequency limitations. By comparison, the bipolar's case temperature increased only
slightly while the MOSFET proved its high frequency capability with virtually no case temperature rise.
the MTP4N50 and the MGP20N50 were both typically
O.67°CIW. This suggests that the two methods are in fairly
close agreement and that the thermal resistances of a
MOSFET and GEMFET of equal die area are essentially
the same.
Safe Operating Areas
Important ratings of any solid state switching element
are its Safe Operating Areas. For the GEMFET, these
include its Forward Biased SOA, orFBSOA, and R~verse
Biased SOA, or RBSOA. Since non-destructive fixtures
were used to determine both of these SOA limitations, an
entire curve could be drawn with each device tested. With
this capability, device trends readily became apparent.
Figure 8-12 shows the dc FBSOA limits of an MTP5N40
and an MGP20N50. Even though the curves are quite
similar, at either end there are significant differences. At
high voltages and low currents, the GEMFET's curve begins to roll off somewhat like the curve of a bipolar that
is approaching a second breakdown limitation. This is not
surprising since the parasitic PNP bipolar is instrumental
in sustaining its unique mode of current conduction.
At the low voltage, high current portion of the FBSOA
curve, the effect of rOS(on) is evidenced in two different
ways. First, at very low drain-source voltages, rOSlon)
can limit 10. This is simply a manifestation of Ohm's Law
and does not indicate a stress-related limit. As Figure 8-12
suggests, the wide difference in on-resistances between
MOSFET and GEMFET is reflected in the rOS(on) limit
Thermal Resistance, R8JC
As expected, GEMFETs and power MOSFETs produced from the same mask set have very similar junctionto-case thermal resistances. RruC of a power MOSFET
can be determined by testing for variations in one of the
following temperature sensitive parameters, or TSPs:
1. Drain-source diode on-voltage
2. Gate-source threshold voltage
3. Drain-source on-resistance
All previous thermal resistance testing of the TMOS
power MOSFET was based on the temperature dependence of the on-voltage of its drain-source diode. For the
MTP4N50, the results were typically about 0.79°CIW. Because the GEMFET has no parasitic diode, this method
was inappropriate for the MGP20N50. Instead, RruC of
the GEMFET was determined by using a second circuit
that detects variations in the gate-source threshold voltage due to changes in TJ. Before testing the GEMFET,
correlation between the two test methods was obtained
by comparing the results of testing the MOSFET in each
circuit. By testing for variations in VGS(th), the RruC of
MOTOROLA TMOS POWER MOSFET DATA
A-106
100
GEMFET
'Dslon)
UMT
/
ie
~ 10
MAXIMUM PULSED CURRENT
RATING OF GEMFET
.::::0
.....
m
As for the GEMFET, special RBSOA considerations are
necessary to ensure optimum reliability. Junction temperature and turn-off speed are especially noteworthy parameters since they can dramatically alter the GEMFET
RBSOA capability. With all other conditions fixed, an increase in TJ can lessen the reverse-biased safe operating
area if the drain current is high. At turnoff, lower gatedrive impedances are also more stressful, as explained
below.
Figures 8-13 and 8-14 outline the operating limits of
typical MGM20N50 (20 A, 500 V GEMFET in a TO-2D4
(TO-3) Package). The figures are typical of the devices
used in this evaluation and do not represent a guaranteed
RBSOA rating. A more thorough evaluation is being conducted to provide guaranteed curves for the data sheet.
The gate-drive circuit used (Figure 8-15) allows adjustment of the gate-drive output impedance at turn-off simply
by varying RGS.
To generate each "fail" point, a resistor, drain current
and temperature were selected, then the magnitude of the
clamp voltage was increased until the device either dissipated the coil's energy in avalanche or entered second
breakdown. If the test device experienced a rapid collapse
of its drain-source voltage (which is characteristic of second breakdown), the non-destruct fixture rapidly (150 ns)
removed energy from the OUT before its die suffered damage.
Interestingly, the failure mechanism is not simply power
related, i.e., slower switching speeds and greater crossover times tend to increase its RBSOA. This is clearly
shown in the turn-off waveforms of Figures 8-16a and
8-16b. Even though the device enjoys lower switching
losses with an RGS of 51 n, its RBSOA is lessened. This
phenomena may be due to a very rapid MOSFET turnoff that places a dv/dt stress on the PNP bipolar.
If the GEMFET is turned off more slowly, the MOSFET
MAXIMUM PULSED CURRENT
RATING OF MOSFET
!z
~
az
~ 1.0
'"9
:-,.
~TMOS"""
'DS(on)
~(x -
o
--
0.1
1.0
"FAIL" POINTS GENERATED BY
NON·OESTRUCT FBSOA TESTER
400 V POWER MOSFET
550 V GEMFET
PROJECTED DATA ,
lIil
10
100
VOS, ORAIN·SOURCE VOLTAGE (VOLTS)
1000
FIGURE 8-12 - COMPARISON OF FBSOA CURVES OF A
400 V MOSFET AND 550 V GEMFET OF EQUAL DIE AREA
of their respective FBSOA curves. Second, a lower onresistance also increases a device's peak-current rating
by virtue of its more efficient current conduction. This limit
is stress related and also is illustrated for both devices in
Figure 8-12.
An RBSOA rating details the maximum drain-current
and drain-source voltage stress allowable during clamped
inductive turn-off. If a device undergoes second breakdown at some combination of VOS and 10 that is within
its pulsed power dissipation capability, an RBSOA derating curve is in order. In essence, an RBSOA derating
indicates that a device may fail due to localized hotspotting
even though its average junction temperature is within its
TJ(max) rating. Second breakdown of the MOSFET only
occurs when its maximum junction temperature is exceeded. Therefore, operation of the MOSFET is only limited by its TJ(max), 10M and VOSS ratings.
600
600
ID = 15A
10 = 20A
RGS = 5.0 k
550
550
L\
\\
\\
\ l\
~\~.
RGS=1.0k- ~
:~ ~
RGS
l'\
1,\ l\
= soon \
l\~
\~\
RGS = 5.0 k
1\' ~.
"(
~
RGS=1.0k300
II
300
250
RGS =
l(
soon
,
~
250
25
50
75
100
125
TC, CASE TEMPERATURE
150
25
FIGURE 8-13 - EFFECT OF GATE DRIVE IMPEDANCE
AND CASE TEMPERATURE ON GEMFET RBSOA
50
75
100
125
TC, CASE TEMPERATURE
150
FIGURE 8-14 - EFFECT OF GATE DRIVE IMPEDANCE
AND CASE TEMPERATURE ON GEMFET RBSOA
MOTOROLA TMOS POWER MOSFET DATA
A-107
vL
When the tranSistor - whether it be a Darlington, GEMFET, or Power MOSFET - turns on, the primary current
ramps up to 3.0 to 7.0 A (6.0 A peak for this exercise).
Altum-off, the inductive kick, or flyback voltage, is allowed
to rise as high as practical to produce the very high transformer secondary voltages (20 kV) required to generate
a spark. In the present systems that employ high voltage
Darlingtons, voltage is often clamped to about 400 V by
a zener placed from collector. to base. As soon as the
collector-base voltage exceeds the nominal zener voltage,
the zener supplies the base current to. the Darlington,
turning it on and thus clamping VCE to VZ. In this mode
the zener carries only a small fraction of the load current
and its power dissipation rating can be sized accordingly
(a collector-emitter zener must carry the full peak primary
current). On the other hand, the transistor is acting as its
own voltage clamp and must dissipate the energy contained in the inductive kick.
When a GEMFET is used in place of a Darlington, the
same clamping scheme can be used. If the zener is placed
across the drain and gate terminals, any zener avalanche
current soon changes the GEMFET's input.capacitance
and initiates turn-on. With this clamping method, the GEMFET experiences the same high power dissipation interval
as the Darlington. One additional component is needed
in the GEMFET version of the clamp. A diode in series
with the zener is needed to block any current that would
otherwise flow if the gate were more positive than the
drain [high VGS, low VDsI.
Since the GEMFET performed very well in this evaluation, the question arises as to the applicability of the
power MOSFET in this same circuit. Again the comparison
is of the MGM20N50 and the MTM4N50, which are a
GEMFET and a MOSFET of identical die size. The first
consideration is that a peak drain current of 6.0 A exceeds
the MOSFET's 4.0 A continuous rating. This in itself is
not a problem, but thermal limitations are possible at
higher duty cycles and elevated case temperatures.
Although the greatest stress on the switch occurs during
the clamping of the inductive kick and generation of the
spark, that clamping interval does not necessarily contribute more to the average power dissipation than does
the interval in which the switch is on and current ramps
up in the primary. This is especially true of the power
MOSFET due to its high rDS(on).
D
Vee
.
I
FIGURE 8-15 -
.
.
V<>AM'
.
GEMFET RBSOA GATE DRIVE CIRCUIT
carries a greater portion of the load current and lessens
the strain on the bipolar during this critical portion of the
switching cycle.
The GEMFET is poised to alter the options available to
power circuit designers. While its slow turn-off speeds limit
its potential applications at this point, the GEMFET's low
rDS(on) and high input impedance make it the technology
of choice for many applications requiring low frequency
switching.
An Application of the GEMFET
An ideal example of a GEMFET application would highlight its three strongest features. It would require a switch
with high blocking voltage capability, a large current rating
and simple drive requirements. The switching element in
an automotive electronic ignition control system is one of
many such applications in which the GEMFET deserves
consideration as an alternative to the switches currently
in use.
Presently, high voltage Darlingtons are the most commonly used switch in automotive ignition systems. The
advantage of using a GEMFET as its replacement is the
elimination of the Darlington's base drive circuitry. Since
the required switching frequency is below 1.0 kHz, the
GEMFET's high input impedance and low drive requirements make it ideally suited to be driven directly from
CMOS logic.
Vos
100V/01V
Vos
100 V/OIV
10
10 AlOIV
10
5.0 AlOIV
1.0 I"
FIGURE 8-168 -
1.0 I"
CLAMPED INDUCTIVE TURN-OFF WAVEFORMS
OF MGM20N50 .-. RGS '" 51 0
FIGURE 8-16b -
CLAMPED INDUCTIVE TURN-OFF WAVEFORMS
OF MGM20N50 - RGS
5100
MOTOROLA TMOS POWER MOSFET DATA
A-108
=
Ignition
Coil
ID
2.0 AlDIV
Vos
100 VlDIV 0
"
Pulse
Generator
5.0!J.S/OIV
FIGURE 8·17 - AN AUTOMOTIVE ELECTRONIC IGNITION SYSTEM
IS AN APPLICATION FOR WHICH THE GEMFET SHOWS GREAT
PROMISE. THE SIMPLE GATE DRIVE CIRCUITRY (b) IS ONE OF
THE MAJOR ADVANTAGES IN THIS SYSTEM. BECAUSE OF THE
DRAIN·T()'GATE ZENER, CURRENT FALL TIME IS DICTATED BY
THE AMOUNT OF ENERGY STORED IN THE INDUCTIVE KICK.
51
b)
1 ~l
Spark
-
of the high input impedance and fast turn-on of a power
MOSFET and the regenerative, latching action of a thyristor. Consequently, a new device symbol had to be created, one that combines the features of both technologies,
as proposed by the symbol in Figure 8-18, i.e., SCR with
FET gate.
The MOS SCR was developed from the vertical structured TMOS where the substrate doping was changed
from N + material to P +. Thus, a four layer structure
evolved (PNPN), creating the two-transistor analogue of
an SCR controlled by an N-Channel MOSFET. This evolution is illustrated in Figure 8-19 whereby the power
MOSFET symbol progresses through the various equiv·
alent circuits to the final MOS SCR configuration. Note
that Figure 8-19d contains the PNP transistor 01 and the
MOS parasitic NPN transistor 02 of the SCR equivalent
circuit and also that the MOSFET 03 shunts transistor
02.
Switching action starts by turning on FET 03 with a
positive gate-cathode (source) voltage VGT (or VGS(on))'
The resulting drain current is the base current of 01 which
turns on this PNP transistor. As in a normal SCR, the
collector current of 01 supplies the base current to 02
and if adequate loop gain exists [(a1 + a2»1)j, regeneration will occur, latching the device. The gate signal can
then be removed and the device will remain latched until
the principal current falls below the hold current - that
current which satisfies the loop gain criteria.
Due to the MOSFET input, the device exhibits the characteristics of the basic power MOSFET, that is, high input
impedance and fast turn-on. And, because of this high,
static input impedance, the MOS SCR can be readily
driven by standard CMOS logic.
Even though a power MOSFET has an extremely high
static input impedance, in order for the device to switch
in the tens of nanosecond range, the gate input capacitance must be quickly charged (or discharged during turnoff). The gate-source and gate-drain capacitance (and its
The difference between the rDS(onl of the MOSFET
and the GEMFET becomes evident dUring the monitoring
of the case temperatures. Under the same conditions (us·
ing a Thermalloy heat sink #60168), the GEMFET's TC
is 37°C, while the MOSFET's is 59°C, representing a
2.5 W difference in power dissipation. .
A second problem, again related to the MOSFET's
higher rDS(on), also complicates its use in an electronic
ignition contror system. Due to the limited battery potential,
especially during engine startup in very cold weather, the
rDS(on) of the switch must remain low so as not to limit
the peak current in the primary of the ignition coil. There·
fore, the 1.5 n maximum specification for the MTM4N50
is probably too high for this application. In this test the
"battery" voltage must be increased by about 30% to
achieve the same primary current that the GEMFET con·
ducted.
In addition to its higher on·state efficiency, the GEMFET
can also offer a cost advantage over the power MOSFET.
A large portion of a power transistor's cost is associated
with its die area. Since the GEMFET can operate at cur·
rent densities at least five times that of a high voltage
MOSFET, significant savings can result from using a
GEMFET with a smaller die size.
The MOS SCR, A New Thyristor
Technology
With the introduction of the MOS SCR, the circuit designer is now offered a device which has the advantages
FIGURE 8·18 -
400 V
PROPOSED MOS SCR SYMBOL
MOTOROLA TMOS POWER MOSFET DATA
A-109
D
MOSFET Symbol
with Equivalent
Drain-Source Diode
GJ~
A
J
MOS with Parasitic
Bipolar Transistor
(b)
(a)
A
S
SCR 2-Transistor
Equivalent Circuit
'--+--.--I~
(c)
Go-----l
L
Q3
MOS SCR Equivalent
G
Ci~~~it
.
K
K
FIGURE &-19 - EQUIVALENT CIRCUIT EVOLUTION OF THE MOS .SCR
Miller capacitance effect) may require peak charging (dynamic) currents in the one-half to several ampere range.
Thus, the gate-driver must supply these sometimes high,
peak charging currents.
With this in mind, several CMOS gates were used,
either individually or in parallel, to generate the MOS SCR
gate capacitance charging currents (Figure 8-20). As an
example, a single, standard CMOS gate (MC14001) is
metallization limited to 10 mA, a quad gate in parallel,
about 30 rnA and six parallel connected hex buffer gates
(MC14049) to perhaps 80 mA of sourcing CUrrent. USing
the illustrated drivers, zero crOSSing turn-on characteristics of the ac powered MOS SCR was determined. For
this exercise, the gate current limiting resistor R1 and 1he
R6
+1SV
1SV
120 V
60 Hz
oIL
~
Rl
R2
(1/4) MC14001
£1,
I
1SV
:L.-J
0---+--1
MC14049
FIGURE &-20 - EXAMPLES OF INDIVIDUAL OR PARALLEL CONNECTED
CMOS DRIVERS FOR MOS SCR
MOTOROLA TMOSPOWER MOSFET DATA
A-110
r
CONDITIONS:
VD = 165 Vpk
60 Hz
IT= 3 Apk
P.W. = 20 p'
gate-cathode R2 were proportionally scaled, e.g., R11 =
100, R21 = 1.0 k; R12 = 10 k, R22 = 100 k; R13 =
100 k, R23 = 1.0 M. The input pulse width was phase
delayed to the pOint just before the MOS SCR started to
regenerate. Figures 8-21 a, 8-21 band 8-21 c illustrate the
turn-on switching waveforms for the three gate impedance
cases, with the top trace describing the gate compliance
voltage (CMOS output), the middle trace, the gate-source
voltage and the bottom trace, the anoc;le-cathode voltage
just before the MOS SCR fires (latches). For comparison,
Figure 8-22 shows the anode-cathode voltage just before
firing (not enough delay in the input pulse) and just after
firing (input pulse delay increased slightly). Increasing the
pulse delay or increasing the pulse width resulted in the
same non-conduction angle (the point measured from
positive zero crossing to where the SCR fired).
Note that the magnitude of the anode-cathode voltage
near firing varied inversely with gate impedance, being
about 30 V, 15 V and 15 V (due to longer gate capacitance
discharge time) when R1 was 100 0, 10 k and 100 k
respectively. The results were opposite of what were expected: the lower the gate limiting impedance, the earlier
the SCR firing (lower non-conduction angle).
However, upon closer examination of the MOS SCR
equivalent circuit (Figure 8-19d), the cause of this effect
became apparent: FET Q3 shunts the NPN transistor Q2.
With low gate-drive impedance, Q3 turns on very hard
and thus offers a very low impedance shunt across Q2
(rOS(on) varies with gate-drive), effectively lowering the
beta of Q2. Consequently a higher anode voltage is required to satisfy the loop gain criteria. This is illustrated
in Figure 8-21c (R1 = 100 k) where VAK does not drop
as low as in Figure 8-21a (R1 = 1000).
The conclusion is that rather than have a larger charging
current capability, a lower one is more desirable. Second,
the lower current (larger gate-series resistance) is more
compatible with the output sourcing capability of standard
CMOS gates; the less current that is sourced, the higher
the CMOS high level output voltage will be due to the
Vo CMOS
10 V/Div
VGK
10V/Div
VAK
20 V/Div
RI = 100
VOCMOS
10 V/Div
VAK
20 V/Div
Before
Firing
VGK
10V/Div
RI ='10 K
IT= 3.0 A
VAK
20V/Div
VAK
20V/Div
Alter
(el
RI
Firing
= 100 k
FIGURE 8-22 - ANODE-CATHODE VOLTAGE WAVEFORMS OF
THE MOSSCR
FIGURE 8-21 - MOS SCR TURN-ON WAVEFORMS
MOTOROLA TMOS POWER MOSFET DATA
A-111
,.
rDS(on) IOH voltage drop. This allows the high logic level
output to. be used for ariving other CMOS logic, if so required. .
.
However, the high gate impedance can create dv/dt
problems. As in any semiconductor, be it a FET, bipolar
or SCR, the junction capacitance (Cds in Figure 8-19b)
Can couple into the input circuit of the device a.capacitiVe
current when a fast, positive goirig step function of voliage
is. applied to .the output. If this current, or resulting voltage
is large e.nough, the device can be inadvertently turned
on: To minimize the dv/dt effect, the gate of the MOS SCR
should be terminated in an impedance (similar to the. gatecathode resistance of a sensitive gate SCR or gate-source
resistance 6f a power MOSFE:T).
The resistance bypasses the capacitive current from
the input of the device, the lower the resistance, the
greater the degree of shunting. Thus with lower resistance, the MOS SCR will have greater dv/dt immunity and
consequently higher blocking voltage capability. This effect is illustrated in the curve of Figure 8-23 whereby a
150 V step function with controlled dv/dt is applied to the
anode (through a limiting resistance) of the MOS SCA.
The gate-cathode resistance is varied and the maximum
dv/dt for that cQndition is noted. Typically, with a 1.0 k
resistqr, the device will block 150 V/p$ and a 10k resistor,
about 10 V/p$. The 1.0 k gate-cathode resistor will also
!'Insure peak forward blocking voltage VDRM of 600 V
peak, 60 Hz.
Thus, for. an optimum CMOS-MOS SCA drive circuit,
two inipedance conditions should be satisfied:
N-channel portion of the CMOS when its output is low
(MOS SCR is off) and the speed-up capacito~ produces
just enough gate current peaking to minimize MOS SCR
turn-on delay time when narrow input pulses are used
«5.011$). Using various combinations of resistor R (1,0 k
to 100 k) and/or capaeitor C (0,001 p.Fand 0.01 p.F), but
alw?ys withdiodeD,anoptimum netWork was achieved
- i one that is cOmpatible with the. output sourcing limitations of· the CMOS. With R = 10. k, C = 0.Q1 p,F, the
folloWing turn-on times were ac;hreved:
ld =-
40 ns
tr =80ns
For this. exercise, the anode supply voltage was a 150 V
pulse with a dv/dt of 150 V/p$,
Anode voltage for this resistive load and gate voltage
and current waveforms for the optimum drive circuit are
shown in Figures 8-25a and 8-2Sb, Note that although the
peak gate current is about 40 rnA for about 1,0 11$, being
limited by the rDS(on) and transconductance Vfs of the
CMOS gate, it is wen within its CMOS average power
limits.
The same gate-drive circuit was then used to fire an ac
1. The. gate circuit should limit the degree of the
MOSFET turn-on;
2. The gate-cathode impedance should be low to increase the device blocking voltage capability.
But how large should this limiting impedance be before
the charging of the gate capacitance results in unacceptable delay times? To determine this, the circuit of
Figure 24 was fashioned using a resistor, speed-up capacitor, and/or reverse diode combinations as the gate
limiting impedance. The resistor R limits the gate overdrive; the diode D provides the low impedance gatecathode path through the rDS(on) (typically 200 0) of the
100a
150V
VDR
I
.!..-_--I
n
VGK
Static dv/dt Capability as a Function of ~
G'ata·Cathode Resistance for the
MCR1000 Series MaS .SCR
r--.
0
IA
VOR
OE
"'0'4
RGK
1. o
lao
I
dv/dt
150V
XLov
150V
,
I
VAKI
.
500 lK
5Kl0K
RGK, GATE-CATHODE RESISTANCE
1N914
(114) MC14001
50K
FIGURE 8-23 - TYPICAL dvldt CAPABILITY OF THE
MCR1000 MOS SCR
I
I
I
I
I r
VTMJ
I
I
RGURE 8-24 - PREFERRED CMOS DRIVE CIRCUIT
AND WAVEFORMS
MOTOROLA TMOS POWER MOSFET DATA
A-112
load at peak line voltage; the resulting turn-on times were
the same as in the pulsed dc test. The gate pulse was
then advanced to the zero voltage crossing of the ac line
and the point at which the MOS SCA just fired was noted.
The anode voltage at which this occurred was typically
15 V, resulting in an effective gate pulse width for this
circuit of about 240 J.LS, (phase delay of 5°).
Finally the MOS SCA was characterized for its commutation time tq; the test conditions were AGK = 1.0 k,
ITM = 3.0 A, dv/dt = 100 V/J.LS. The typical commutation
time was:
tq
= 6.0 J.LS
Conditions: VDR = 150 V, RL = 25 n
R = 10k,C = 0.01 poF
VAK
25 V/Div
VGK
2.0 V/Div
100 n·s/Div
TURN-ON TIME
(al
VGK
5.0 V/Div
o
IG
20 mA/Div
o
2.0 "s/Div
INPUT DRIVE CHAt:lA·CTERISTICS
(bl
FIGURE 8-25 - SWITCHING CHARACTERISTICS OF THE MCR1000
WITH THE PREFERRED GATE-DRIVE CIRCUIT
APPLICATIONS OF THE MOS SCR
The following circuits illustrate the unique characteristics of the MOS SCA: high input impedance (low drive
power), fast turn-on, and latch capability.
DC Static Switch
When an SCA, MOS or bipolar, is used in a dc circuit,
some means is required to turn the device off. An example
of a dc application using the MOS SCR being turned off
is shown in Figure 8-26. For this illustration, the loads in
the respective anode circuits of the two MOS SCA's are
equal, resulting in a power flip-flop. They can be unequal,
if so required, with the lighter load simply being the commutating source. Assuming that MOS SCA (01) is initially
on, the commutating capacitor C will be charged through
AL2 and AS to the supply voltage VOA (minus the "on"
voltage VTM of 01); the capacitor is thus charged; negative on the left plate, positive on the right. When 02 is
then turned on, the right plate is pulled to near ground
and since the voltage across the capacitor cannot change
instantaneously, the left plate will consequently be pulled
below ground. This momentary reverse bias of the anode
of 01 commutates the device off. The com mutating cap~citor will now .start to charge up through ALI, producing
the exponentially rising voltage VOl (Figure 8-27). To ensure stable commutation, the time required to charge up
to zE;lro volts should be greater than the tq of the device.
In the example shown (ALI = AL2 = 50 ohms, C =
0.22/LF), the time was about 6.0 J.LS, satisfying the tq
requirements of the MOS SCA. The maximum operating
frequency is also dictated by the AC time constant, as the
capacitor should be near full charge before the next cycle
begins. The series resistor AS limits the initial capacitor
dump current as shown by the IA waveform of Figure 8-27.
A simple and inexpensive circuit for toggling the flipflop, one that uses a CMOS quad, 2 input NOA gate, is
shown in Figure 8-26. Gates Gl and G2 comprise an
astable multivibrator running at about 13 kHz with the duty
cycle being set by potentiometer AI.
Gate G2 provides the buffered drive to MOS SCA 01
and also the complementary drive through G4 to 02. Both
gate drivers are configured with the optimum circuit previously described. Thus, using MOS SCAs, a low drive
power, fast turn-on, power flip-flop was readily achieved.
AC Static Switches
Examples of how the MOS SCA can be used in ac
applications are shown in Figures 8-28 and 8-31. The first
circuit, an ac power switch (Figure 8-28), uses aMOS
SCA connected across the dc output of a rectifier bridge
to switch an output ac load. The bridge rectifies the input
ac, allowing the one MOS SCA to control both half-cycles
of the input signal. As in the other examples, the gate of
the MOS SCA is driven by a ground referenced CMOS
gate, which means the power circuit must be floating (the
alternative is to float the gate driver, and ground-reference
the ac circuit). For gate full-wave rectified applications,
the load should be placed in series with the MOS SCA
across the bridge dc output terminals. Examples of both
gated ac and full-wave rectified output waveforms are
MOTOAOLA TMOS POWEA MOSFET DATA
A-113
•
VOR
0,01 p,F
+40V
RL1
RL2
50
50
C
RS
50W
SOW 0.22p.F 10
MCR1000-4
10 k
02
47 k
lN914
0,01 p,F
10 k
·f = 13 kHz
510 pF;
lN914
FIGURE q·26 - POWER FLlp·FLOP USING MOS SCRa
IA
2.0 AJDIV
Vo,
'0 VIOIV
FIGURE 8-27 - OUTPUT WAVEFORMS OF POWER FLlP·FLOP
+15V
O,01p,F
10 k
MCR1000·4 [
(V.)MCI4001
FIGURE 8-28 -
lN914
AC POWER SWITCH USING· THE MOS SCR
MOTOROLA TMOS POWER MOSFET DATA
A·114
VOae
•
VOae
20V/DIV
t
1.0mS/DIV
ft.
= 2.0 kHz
fG = 200 Hz
FIGURE 8-29 - OUTPUT WAVEFORM OF AC POWER SWITCH
Vade
20V/DIV
t
1.0 msIDlV
FIGURE 8-30 - GATED FULL-WAVE OUTPUT OF AC POWER SWITCH
configuration of anac power switch (Figure 8-31) should
be considered. Since each device is only operating for
half of a cycle, the circuit commutation turn-off time tq
becomes the limiting parameter for high frequency operation.
shown in Figures 8-29 and 8-30 for the respective configurations where a 2.0 kHz signal is gated by a 200 Hz
signal.
When higher frequencies have to be gated or modulated, particularly with inductive loads, then the two SeR
+15V
lN914
,--_+-l""O.,;:k:..J 0.01 p,F
lN914
10 k 0.01 p.F
L...-.-4"":":"'::..J
RL
1.0 k
FIGURE 8-31 - BIDIRECTIONAL POWER SWITCH USING TWO MOS SCRs
MOTOROLA TMOS POWER MOSFET DATA
A-115
•
Vo
20 VIOIV
t
tOms
FIGURE 8-32 -
2.0 kHz SIGNAL GATED BY 200 Hz
The two MOS SCRs are driven in push-pull using the
same CMOS drive circuits described in Figure 8-26. Consequently, when the ac input goes positive, and MOS SCR
01 is turned on, the signal will be condilcted to the load
through diode 02. In a like manner, the negative-going
signal will flow through 01 and 02. An example of the
output waveform that can be achieved is shown in Figure
8-32 where a 2.0 kHz input signal is gated by a 200 Hz
control signal.
All of ac switches described were powered by a signal
generator whose maximum peak output was 60 V into a
1.0 k load. This is not the power limitation of the circuit;
the limitations are the MOS SCR which for the MCR1 000
family is a VRRM of 100 V and an anode current IA of 15
ARMS.
able, large enough to drive the MOS SeR gate, but too
large to power the MF00405F fiber optics integrated deteelor/preamplifier (receiver) whose maximum VCC is 7.5 V.
This receiver has two complementary outputs, one at a
quiescent level of about 0.6 V and the second at 3.0 V.
By adding a 4.7 V zener in series with the return bus, the
effective. Vee becomes 5.3 V and also the 0.6 V output
level is translated up to about 5.3 V. This level is now
compatible with the reference input (5.9 V) of the singleended powered op-amp acting as a comparator.
Under no-signal conditions (fiber optic emitter deenergized), the receiver output is lower than the op-amp
reference and, consequently, the op-amp output is high,
turning on the MOS SeA. When the emitter is energized,
the receiver output goes more positive, exceeding the
reference to the op-amp and causing its output to switch
low to near ground. The reference voltage should be compatible with the fiber optic sensitivity; for this illustration,
pulsing the emitter with about 80 rnA and using a onemeter fiber length resulted in a receiver output pulse of
about 1.0 V. To ensure that the MOS SeR is cut-off, two
diodes (01 and 02) are placed in series with the gate.
Thus, by varying the duty cycle to the emitter, the MOS
SeR power controls the load on a multicycle, half-wave
basis, but it can also be used in phase-control applications. Diode 03 is used to block the peak negative half of
the ac input which would exceed the VRRM spec of 100
V. The load can be resistive, a light dimmer as an example,
or inductive. As with any thyristor inductive load, a snubber
.. network may be required to minimize the dv/dt effects of
that type of load.
CROWBAR
Another application which should serve the fast turnon capability of the MOS SeR is as a crowbar. Experimentation has shown that the device can dump an 8,000
J.l-F capacitor (simulating the output filter capacitor of a
linear power supply) charged to 20 V with 0.1 n currentlimiting resistance in the discharge path. The·end result
is peak-current pulse of about 140 A, decaying exponentially to its 10.0% value in about 3.5 ms. Related specifications of the MCR1000 family of MOS SCR's are: peak
Ie Driver
Drivers fOr the MOS SCR are certainly not limited to
only CMOS gates; in fact, any semiconductor device, or
even mechanical switch, that satisfies the gateimpedance requirements can suffice. In Figure 8-33, an
op-amp is used to interface between a fiber optic system
and the MOS SCR to multi-cycle, half-wave control of a
load. For this application, a 10 V power supply was avail-
OUlv
120V
lN
+10V
MCR1000-4
MFOD404F
A,/"CI
==O=p=tic=a=1F=ib=~=r
::::II
10 k
-=
4.7 V
MFOE106F
1.0 W
1N4732
FIGURE 8-33 -
-=
5.6 k
OP-AMP GATE DRIVER IN A FIBER OPTIC SYSTEM
MOTOROLA TMOS POWER MOSFET DATA
A-116
forward surge current ITSM of 90 A and an 12t rating of
34A2S.
In summary, the MOS SCR is a new device combining
the properties of power MOSFETs and SCRs high input
impedance, fast switching and latching action. It is easily
driven by low power logic - CMOS in this case - but
the driver can be any IC or circuit with pull-down (sinking)
capability. Gate current can be limited to tens of microamps, if required, but switching speed trade-off must
be made at these low currents. To ensure high blocking
voltage and dv/dt immunity, the gate cathode should be
terminated in a relative low impedance: A simple, inexpensive method of accomplishing this is to use the CMOS
low-level output and a reverse diode.
MOTOROLA TMOS POWER MOSFET DATA
A-117
Chapter 9: Relative Efficiencies of TMOS and
Other Semiconductor Power Switches
bipolars in all or many swithcing applications? The answer
is - it depends. Efficiency is a measure of diSSipation,
which, iri Switchmode circuits, consists primarily of switching losses, both turn-off and turn-on, and saturation
losses. Since switching losses are a function of the switching frequency and saturation losses are relatively constant, a point is reached in the frequency spectrum where
one loss predominates over the other. Thus, in low frequency applications, devices with low saturation or onvoltage would show lower losses as measured by the
device case temperature, and at high frequencies, the fast
switchers would run cooier. This applies to all types of
semiconductors, be they power MOSFETs, Bipolars, Darlingtons, GTO (Gate Turn Off) SCRs or a GEMFET (Gain
Enhanced MOSFET) (A standard SCR can also be used
wiith commutating circuitry; however, it is not included in
this evaluation due to the additional circuit reqUirements
and associated costs.)
The prime requisite of a power switch (semiconductor
or mechanical) is to transfer the maximum power to .the
load. A compilrison of the relative efficiencies of various
power semiconductor switches will be demonstrated with
three different switching loads: resistive, Inductive and a
dc motor.
There are four factors that contribute to the system
losses: input or driving power losses due to the input
current and/or voltage required to turn on the device; saturation or static losses when the device is ON (a product
of the on-VOltage and current); switching or dynamic
losses that result from the transition times when the device
Is turned ON and OFF; and off losses due to the product
of leakage current and the power supply voltage. Generally off losses are by far the least significant since modern semiconductors have low leakage currents and can
be ignored in system loss calculations.
The variation of input power losses can be substantial
for the various semiconductors. As an example, a high
voltage switching transistor would have relatively low current gain and, consequently, requires relatively high input
base current to turn it fully on whereas a MOSFET, with
its extremely high static input impedance, would require
very little input power to turn it on.
The output power losses are illustrated in Figure 9-1.
It is apparent that the switching losses, depending on the
switching frequency and transition times, can contribute
a large share of the total system losses. Thus, for high
frequency applications, where switching losses predomInate, fast switching devices should be used. Conversely,
for low switching frequency applications, low on or saturation losses are more important.
Power MOSFETs are recognized· as being extremely
fast switching devices, but are they more efficient than
Temperature Testing High Voltage Devices
TMOS versus Bipolar SMI and III
CD
'"
h·
~
~
~':~ f"''''~
E
~
1.0
On Current
U
~
.dJ
Switching Losses
~
CD
~ c:
,!:.~ 0.25
~'=
"
Q.
°is
~
O"==~~~@~@~~@~@~.m==
FIGURE 9-1 - NORMAUZED SWITCHING WAVEFORMS
FOR A RESISTIVE LOAD
A simple way of measuring the relative efficiencies of
the OUTs, one that measures the total device losses, is
by measuring the case temperature. This is accomplished
by attaching a thermocouple to the mounting flange of a
TO-204 (TO-3) package or tab of a plastic (TO-220) package. The first evaluation was to compare the switching
efficiency of three high voltage switching transistors the 2N6545, one of the first transistors characterized for
Switchmode applications, called Switchmode I, (SMI); the
MJ16004, a state-of-the-art Switchmode III Transistor
(SMIII) designed for higher frequencies; and the Power
MOSFET MTM5N40. All these devices are of similar die
size and have similar ratings (Table 1). All were tested
with nearly identical loads and were driven by the same
test circuit, except that the forward input current (lB1) and
input resistance were scaled for the particular DUn. Reverse current or turn-off current was derived from the
same input clamp transistor switch and the magnitude of
this current (lB2) was dictated by the stored charge of the
device under test (DUn.
Since the input drive for both turn-on and turn-off can
be chosen to optimize the switching speed, the drives
selected were those generally shown on the data sheet;
i.e., forced gains of 5.0 and 7~O, respectively, for the
2N6545 and the MJ16004; off-bias voltages of -5.0 V
and - 2.0 V for the above; and a gate-drive of greater
than 10 V for the MTM5N40.
Resistive loads were chosen for the temperature riseversus-frequency test since the load current could be
maintained at a constant 2.5 A as the frequency was
varied. Recognizing that the "real world" load is usually
inductive and that inductive turn-off switching losses are
greater than turn-on due to the rectangular load line, a
single frequency (75 kHz) inductive test was also run. Due
to the different on-voltages and turn-off times for Bipolar
and MOSFET devices, the load inductances had to be
slightly different to achieve the same peak collector (drain)
MOTOROLA TMOS POWER MOSFET DATA
A-H8
TABLE 1 -
Die Size
(Area)
Specifications of OUTs
SMI
2N6545
SM'"
MJ16004
160x160 mil
(25600 m1l2)
157x175 mil
(24649 mil2)
TMOS
MTM5N40
126x182 mil
(22932 mil2)
IC,IO
8.0 A
5.0 A
5.0 A
VCEO,VOSS
400 V
450 V
400 V
VCE(sat)max,
VOS(sat)max
1.5 V@5.0A
2.5V@3.0A
2.5 V@2.5A,
ros~n) max
1.0
VCE(sat)typ,
VOSisatitVp
hFE(min),
9fs(min)
0.3 V
0.3V
7.0@5.0A
7.0@5.0A
der test is driven at a 33% duty cycle. However, at high
frequencies (low on times), DUTs with greater storage
times will effectively be powered for longer duty cycles
and therefore have greater saturation losses contributing
to the device temperature rise. As an example, at 150
kHz (period of 6.7 ILS) the 33% dc drive on-time of about
2.2 ILS would result in about 48% power on-time with only
1.0 I's of storage time.
The clocks for this system, one for the resistive load
case and the other for the inducutive load, consist of two
CMOS gate configured RC astable multivibrators. Switchable timing capacitors set the frequencies for the resistive
load at 5.0, 25, 75 and 150 kHz respectively; the inductive
load clock is set at a fixed frequency of 75 kHz. The output
of these MV's clock the MC14002 Octal Counter Divider
connected as a three-phase ring counter whose respective emitter-follower, positive-going outputs control the
three virtually identical drivers.
Forward base current for the bipolar transistors is set
by turning on the NPN transistors 02 and 07 and the
following PNP transistors 03 and 08. To minimize storage
time, 03 and Q8 are fashioned as constant-current generators, supplying the base currents to the 2N6545
=
2.2V@0.9(}
2.0 mhos @
2.5 A
currents for a normalized test. For the 75 kHz test, the
peak ramp current of about 3.0 A peak was achieved with
inductances of 32 I'H and 27 I'H respectively when VCC
and VDD were + 16 V.
The temperature rise test fixture (Figure 9-2) consists
of a clocked, three-phase counter sequentially driving the
three respective switching circuits; thus, each device un-
SWSlA
+10 V
R
,..--~~--~";;o L
~
60 V
"4-~S~W_S_3B~~~
L
16V
PowerSW
~
-5.0V
~5.0V
SWS3C
Load Sel.
~4r-+~~-~+-4r~~~
VCiamp
Inductive Load
Astable MV
O.88",F
400 V
270
O.OO1~F
FIGURE 9-2 - TEMPERATURE RISE FIXTURE SWITCHMODE I,
SWITCHMODE III, TMOS
MOTOROLA TMOS POWER MOSFET DATA
A-119
(~F=5.0, IB1 =600 mAl and MJ16004 (WF=7.0,
IS1 =430 mAl for the inductive load current of 3.0A peak.
Forward gate voltage for the powef MOSFET is generated
by turning on PNP transistor Q13 (Baker clamped to minimize ts) and thereby applying nearly the full 15 V rail<
voltage to the gate. The 15 ohm current limiting resistor
provides the low source impedance for quickly charging
(and thus switching) the MOSFET input capacitance Ciss.
Reverse bias voltage VBE(off) or VGS(off) for rapidly
turning off the OUTs, are derived· by differentiating the
input pulse with the resistor-capaCitor networks in the
base circuits of Q4, Q9.and Q14. The resulting negative
going pulses, which are coincident with the trailing edge
of the input pulse, then turns on the following respective
PNP transistors Q4, ·QS and Q13 for about 3.0 /LS. These
transistors then turn on NPN transistors Q5, 010 and Q15
whose emitters are referenced to a negative power supply; thus, the reverse bias voltages and resulting reverse
bias currents (IB2 for bipolars) are applied .to the OUT for
the 3.0 /LS immediately following the turn-on pulse. This
reverse bias voltage can then be varied to determine its
effect on switching speeds, power dissipation and case
temperature rise. For the following described temperature
tests the bias voltages were set for -2.0 V and -5.0 V
respectively, the presumed optimum values that are listed
VCE = vos
in the respective data sheets.
The resistive loads, being somewhat inductive wirewOl)nd resistors, h.ave turn-on switching current rise times
limited by the UR time constant (Figure 9-3) and thus
independent of input drive. However, the turn:offvoltage
and current switching times are affected by off-bias (Figure 9-4); :thus at optimum bias voltage, the switching
losses and therefore case temperature can be. minimized.
This is quite evident in the curves of Figure 9-5 showing
temperature rise versus frequency at two off·bias volt·
ages. All three devices showed slightly lower case tem·
peratLires (1.0 to 3.0°C) when the optimum off·bias was
used at the higher frequencies where switching losses
predominate.
The Power MOSFET also runs cooler at higher off-bias
voltage. This is due to the charged input capacitance Ciss
being discharged more quickly when clamped to a greater
negative voltage; thus the turn-off switching speeds are
improved.
As expected at low frequencies, where on losses predominate both the 2N6545 (SMI) and the MJ16004 (SMIII)
have temperature rises proportional to VCE(sat), both
being about 0.3 V at 2.5 A. The Power MOS transistor
(TMOS), with a typical on-resistance rOS(on) of about 0.9
ohm [1.0 ohm(max)] has an on-voltage of about 2.2 V at
= 100V/01V
SMIII VCE
SMI
VCE
TMOS
VDS
SMIII
CONDITIONS:
VCC= 50V
VOD~50V
RL = 20 n
f = 75 kHz
VBE(off) = -2.0 v
VGS(off) = -2.0 v
IC
IC = 2.0 A/DIV
t = 2.0 /ts/DIV
FIGURE 9-3 -
RESISTIVE LOAD SWITCHING OF
OUTs AT 75 kHz
vGS(olf) = -5.0 V
VCE = 20 V/DIV
t = 1.0 p.S/DIV
IC = 0.5 A/DIV
t = 1.0 p.S/DIV
FIGURE 9-4 -
RESISTIVE LOAD SWITCHING OF SWITCHMODE III
MJ16004 AT TWO OFF·BIAS VOLTAGES
MOTOROLA TMOS POWER MOSFET DATA
A-120
55
&'
Resistive load
Ie, 10 = 2.5 A
Vee. Voo = 50 V
Rl = 2011
50
w
0::
=>
!;(
0::'
w
":;
w
w
....
III
45
....
I
SMI 2N6545
I
/
ITUos MTMJN40
40
.. v
"".-. V~
'"u""
U
f'
~~
35
,L
.1
II
1
VSE(off)
I
I
-5.0 V
= -2.0 V
VSE(off)
-5.0 V
VGS(Off)
5.0 V
= -2.0 V
SMI
V I I=Llil
~ -;2.0~ I III
F'-,.d,
TMOS
SMIII MJ16004
30
25
1.0
5.0
10
25
50
SOD
75 100 150
1000
f. FREQUENCY (kHz)
FIGURE 9-5 - TEMPERATURE RISE OF SWITCH MODE
DEVICES AS A FUNCTION OF FREQUENCY
CONDITIONS:
vos= 100V/OIV
0-
10 = 1.0 AlOIV
VGS(off) = -5.0 V
0FIGURE 9-6 - CLAMPED INDUCTIVE LOAD SWITCHING
WAVEFORMS OF TMOS MTM5N40
2.S A, resulting in the higher case temperature. As the
frequency is increased, the extremely fast switching
MOSFET introduces lillie additional switching losses~ resutting in a relatively constant case temperature.
The first generation SMltransistor shows the expected
increasing temperature rise with increasing .frequencies
due to its relatively slow switching speed (the device was
designed for 20 kHz applications). By contrast, the Switchmode III Transistor, MJ16004, which was designed for
improved operation at higher frequencies with improved
reverse bias safe operating area," shows a much lower
case temperature rise; in fact, it typically operated cooler
than the Power MOSFET up to the 7S-100'kHz range.
The illustrated temperature rise curves were derived
with typical devices. Testing of about ten sets of devices
produced similar results, atthough in some cases the effects of off-bias were not as pronounced due to slight
differences in device processing, temperature measurement repeatability and accuracy, particularly where small
differences in temperature had to be determined.
Although the curves show defined temperatures, the
magnitude of the rise is only relative as it is obviously a
function of the size and efficiency of the heat sink chosen.
For this exercise, small heat sinks were chosen to raise
the case temperature for higher differential temperature
measurements. Secondly, the heat sinks (both the small
ones. for the OUTs and the large ones for the resistive
and inductive loads) were thermally isolated from each
other to minimize mutual thermal coupling effects; (the
OUT heat sinks were mounted on ceramic standoffs and
.the load sinks on plastic washers to reduce thermal conduction to the chassis and hence to each device).
The vertical temperature axis of Figure 9-S could have
been labeled Power Dissipation (PO), knowing the thermal
resistance ofthe heat sink (R8SA) used and the relationship between case temperature and thermal resistance
(PO = TC - TA
). !iowever, for relative efficiency
.
R8CS + R8SA
considerations, measuring the device case temperature
will .suffice.
.For clamped inductive loads, the greatest switching dissipation generally occurs during turn-off where the device,
due to the rectangular load line, can be stressed simultaneously with both high current and voltage. The illustrated inductive loads simulate a flyback switching regu-
MOTOROLA TMOS POWER MOSFET DATA
A-121
VBE(off) =
-2.0V
-5.0 V
-2.0 V
-5:0 V
VCEM
veE =
IC=.
0.5 AIDIV
50V/DIV
1=
50 ns/DIV
FIGURE 9-7 - CLAMPED INDUCTIVE LOAD TURN-OFF
TIMES OF SWITCHMODE I 2N6545 WITH TWO OFF-BIAS VOLTAGES
lator where the energies stored in Ihe inductors when the
OUTs are Iurned on are transferred via their respective
clamp diodes to the resislor-capacitor load during turn-off
lime. By proper selection of this load, the resulting clamp
voltage was set for about 250 Vdc. The actual peak collector-Io-emitter voltage VCEM overshoot can be somewhat higher, being dependenl on the rale of collector current fall time Ifi' Ihe forward recovery time of the clamp
diode and the degree of proper RF layout (Figure g-7). It
is nol uncommon for this overshoot to exceed the clamp
supply voltage by 100 Volts.
An example of how reverse bias affects the swilching
speed, and thus efficiency, of the 2N6545 is shown in the
photos of Figure 9-7. Note the difference in ts , Ifj, VCEM
and collector-emitter vollage rise lime Irv' At the optimum
bias of about - 5.0 V, the device lurns off faster, Ihere is
less energy to be dissipated and a lower case temperature
resulls. This is also Irue of the olher two OUTs.
AlIhough there is no "storage lime" associated wilh
FETs, there is a turn-off delay time id(off) due 10 device
capacitances having to be discharged. The photos of Fig-
ure 9-8 describe the turn-off times when the off-bias is
varied from 0 V, - 2.0 V and - 5.0 V respectively. A.s
mentioned previously, Ihe greater off-bias resulls in Ihe
lowest turn-off times.
The average temperature rise measurements of the
three OUTs for the inductive load case (Table 2) illustrates
the effect of off-bias on device efficiency.
. A direct point-by-point comparison between the inductive load and resistive load tests at 75 kHz can't be made
since the respective load currents, and thus power dis. . sipation are not the same. However, the trends can be
. compared; i.e., for the inductive load test, a greater temperature differential resulted between the optimum offbiaS voltage and the second tested voltage, being as high
as about 15°C for 8M!. By comparison, the resistive load
test showed only a few degrees difference. This is due to
the change in turn-off switching time having a greater
effect on the more energy stressful inductive load switching than on the resistive load.
In addition to driving the bipolar devices with the recommended forced beta, f3F of about 5.0 and 7.0 respec-
CONDITIONS:
f= 75 kHz
VDD= 50V
vGS(off)=ov
vGS
01 = 1.0 "s/DIV
VDS
0VGS(off) = -5.0 v
VGS(off) = -2.0 V
RGURE 9-8 - THE EFFECT Of Ufl'-tlIA!; VOLTAGE
VGS(ofI) ON TURN-OFF TIMES OF TMOS MTM5N40,
RESISTIVE LOAD
MOTOROLA TM08 POWER MOSFET DATA
A-122
parably sized first generation Power MOSFETs.
Technology advancements of Motorola Power MOSFETs have been made to significantly reduce the onresistance, rDS(on)to make these devices competitive with the bipolars.
TABLE 2
Temperature Rise of an Inductive Load
f = 75 kHz, ICM = 3.0 A, VCEM =,250 V
Case Temperature
Off-Bias
Voltage
SMI
SMIII
TMOS
-2.0V
58°C
34°C
42°C
-5.0V
43°C
39°C
38°C
• Switch mode III MJ16004 compares favorably to
Power MOSFET MTM5N40 at 75 kHz with an offbias of - 5.0 V and generally runs cooler at the optimum bias of - 2.0 V (relative to - 5.0 V for TMOS).
Although not described in this text, the SOA of SMI
& SM"I is not as large as TMOS.
• For "real world" inductive loads, where the turn-off
switching losses predominate, insufficient off-bias
can produce higher case temperature rise for SMI
transistors due to slower turn-off switching speeds
(e.g., @ 75 kHz TC = 58°C for VBE(off) = -2.0 V
compared with 43°C for - 5.0 V).
tively for the 2N6545 and MJ16004, a brief test was conducted by reversing f3F (7.0 and 5.0 respectively).
Although the dynamic saturation characteristic of the bipolars changed subtly due to different base drive, and the
turn-off switching time (even with off-bias) changed by
only a second order, the change in power dissipation was
minimal, if any. Within measurement repeatability, the resultant case temperatures were about the same, suggesting no great requirement of maintaining a defined f3F.
Examination of the above test results, the resistive temperature curves and the photos of the switching waveforms lead to the following conclusions about the switching efficiency of the test devices:
• Optimum off-bias will reduce turn-off switching times
and thus switching losses for the bipolars and FET,
but does not necessarily minimize the storage time
(e.g., for SM'" tfi(min) and ts(min) occur at about
- 2.0 V and - 5.0 respectively.
• Under optimum off-bias voltage condition, the tf of
SM"I approaches that of the very fast TMOS, however, drive power is high.
• The temperature rise results are a measure of total
device dissipation, including the input drive loss.
• Switchmode I 2N6545 can be comparably operated
to 75 kHz when there is sufficient off-bias voltage (or
reverse base current), approximately -5.0 V.
• The fast switching speeds of TMOS coupled with the
low drive power requirements and relatively simple
drive circuitry make the MOSFET an attractive high
frequency device.
• Storage time, when it is not compensated for by circuit feedback techniques, somewhat affects efficiency at high frequencies due to increased ON
losses.
• Power MOSFETs become more efficient at frequencies beyond about 100 kHz when compared to the
new generation of switch mode bipolar transistors.
• Specified force beta f3F of the bipolars are not too
critical for efficiency considerations as the turn-on
times are partially dictated by the load. Off-bias tends
to minimize the storage time effects as f3F is varied;
however, excessive overdrive can cause IC tail lifts
during turn-off which may contribute to larger temperature rise.
• Power MOSFETs have lower id(off) when sufficiently
reverse biased than bipolar ts , thus allowing a higher
operating frequency.
• At low frequencies, ON (static) losses predominate;
thus bipolars are presently more efficient than com-
Low Voltage Devices: TMOS versus
Bipolar, Darlington and GTO Devices
PWM DC Motor Controller Test
The load used in this test is a dc motor whose speed
is controlled by PWM. Consequently, when narrow pulse
widths are applied - low speed - the back emf is low
and the load current (collector, drain or anode current) Is
high, about 11 A. To ensure device saturation under this
worst case condition, adequate input current must be applied. For the devices tested, the forward input current for
the bipolar, Darlington, TMOS and GTO were about 700
rnA, 100 rnA, 1.0 mA, and 120 rnA, respectively.
Due to the motor time constant, the switching frequency
was set for about 100Hz and the min/max duty cycles
were about 8% and 70% respectively. At this low frequency, the use of off-bias for the bipolar, Darlington and
TMOS produces negligible improvement In efficiency as
the decrease in turn-off time is extremely small for the
time frame involved. However, the GTO does require offbias which for this test circuit and DUT was as much as
2.2 A lasting for about 10 pS. This turn-off power should
MOTOROLA TMOS POWER MOSFET'DATA
A-123
•
be considered in the efficiency calculations.· At low frequencies, it is relatively small, but as frequency increases,
it can become substantial (refer to Figure 9-10 for drive
circuits and input power equations).
The bipolar, Darlington, and TMOS are turned on by
the input pulse whpse width is a function of the required
motor speed; whereas the GTO is turned on by a relatively
narrow, positive gate current pulse and turned off by a
narrow, negative gate current pulse. As the. frequency is
increased. it is apparent that the GTO input power increases and will reach a point where its input power is
greater than that of the bipolar or Darlington. This crossover frequency is a function of the power supplies used
and the particular duty cycle chosen. As an example, for
a 50% duty cycle with the illustrated power supplies, this
crossover pOint between the Darlington and GTO would
be about 2.0 kHz.
TEST CIRCUIT ANALYSIS
The test cirCUit, shown in Figure 9-9, consists of a two
gate CMOS, astable multivibrator (MV) clocking a CMOS
configured monostable multivibrator (MV) to produce the
approximate 100 Hz, variable pulse width output. Dar-
lington transistor 01 furnishes the buffered output to drive
the two channels of the power amplifier, with transistors
02 and 03 supplying the positive input current to the OUT
and 04 and 05 the negative current. When the OUT Selector Switch S1 is in positions 1, 2, or 3, the full pulse
width will be applied to the OUTs as differentiating capaCitor C1 is shorted out. Thus, positive input current is
generated by the direct coupled pulse turning on the NPN
transistor 02 and the following PNP transistor 03 connected, in positions 1, 2, and 4, as a constant current
source. The respective emitter resistors set the current
IB1 or IGT for the OUTs. Negative current is derived by
differentiating the input pulse with C2, R2 and using the
negative going, trailing edge pulse for turning on the following PNP transistors 04 and NPN clamp transistor 05.
Thus, an off-bias voltage (clamped by diodes 01 and 02)
is supplied to .the selected OUT. If required, the off-bias
can be removed by the Negative Bias Switch S2.
The GTO requires only a relatively narrow positive gate
current pulse to turn it on. This pulse is derived from the
differentiating network C1, R1 (switch S1A open), with the
positive going, leading edge pulse turning on 02 and 03.
For the component values shown, a turn-on, positive drive
current pulse IGT of about 120 rnA in amplitude and 40
PULSE
WIDTH
+12V
CONTROL
OUT + 12 V 0-..---..,
SEL SW
v+
4 0 S1A
MOTOR: PHOTO CIRCUITS
TYPE U9M4H/U6
30 V, 4.6 A, 3250 RPM
TACHOMETER: IV/lOOO RPM
MR750
OUTS MOUNTED ON
THERMALLOY G107
HEAT SINK
C2
39 V
1.5W
09
1N
4001
4.7 V
1.5W
1N5917A
-12V
BIPOLAR
2N64S7
v-
FIGURE 9-9 -
DARLINGTON
TIP 100
TEST CIRCUIT FOR MEASURING RELATIVE EFFICIENCY OF OUT
MOTOROLA TMOS POWER MOSFET DATA
A-124
TMOS
MTP 12N06
GTO
THYRISTOR
ILS wide is generated, followed by an approximate - 6.0
V, 35 ILs wide turn-off voltage pulse that is coincident with
the trailing edge of the input pulse. This voltage pulse
produces a reverse current IGR of about 2.2 A for 10 ILs
(anode current of about 11 A) when the stored charge is
depleted. Obviously, if no reverse bias is applied (Switch
S2 open), the GTO will lose control, always being on, and
the motor will run at its maximum speed.
put RPM by means of a tachometer coupled to the motor.
The output voltmeter, in effect, measures the relative saturation loss of the OUT since this voltage is subtracted
from the applied motor voltage and, consequently, the
motor speed will be indicative of this loss. Only the relative
positive input current is measured as the reverse currents
at this low frequency contribute very little additional drive
power. However, as the power equations note in Figure
9-10, with increased operating frequency, this off-bias
power can be substantial.
The relative efficiency measurements for the four OUTs
are listed in Table 3. Of interest, in regard to efficiency,
are the measured input currents (both pulsed and relative
average), and tachometer outputs, on-voltages and case
RELATIVE EFFICIENCY MEASUREMENT OF OUTs
In order to measure the relative efficiencies of the OUTs,
both input power and output power are recorded. This is
simply done by switching in a current meter to measure
the average input current, or a voltmeter to measure out-
BIPOLAR. DARLINGTON
TMOS
v-
GTO
AGURE 9-10 -
OUT DRIVE AND INPUT POWER CALCULATION
MOTOROLA TMOS POWER MOSFET DATA
A-125
II
temperatures. Within measurement .repeatability, the
OUTs with the highest on-voltage had the lowest relative
output power due to reduced motor voltage and the case
TABLE 3 OUT
temperature rise correlated with the total power dissipation (input plus output).. These readings generally confirmed what was expected:
Relative Efficiency Measurement of OUTs
Bipolar
2N6487
Darlington
TIP 100
TMOS
MTP12N06
GTO
Thyristor
110 x 130
1202
1202
1802
VoHage
Rating
SOV
60 V
60V
300 V
Current
Rating
15A
8.0A
12A .
10 A
Switching Speeds
(Relative)
Medium
Medium
Fast
Slow
Input Current,
(Forward/(P'W.)
700 mA
100mA
1.0mA
120 mA (40 !'8)
Input Current,
Reverse/(P.W.)
1.0 A @ IMAX (0.2 !'8)
Duty Cycle
8%
12%
56%"
8%
12%
81%*
8%
12%
74%*
8%
12%
68%*
Load Current, Peak
11 A
5.0 A
0.9 A
11 A
5.0 A
0.9 A
11 A
5.0 A
0.9A
11 A
5.0A
0.9 A
Power In (Relative)
5.0
13
75
3.0
4.0
11
1.0
2.0
2.0
1.0
2.0
2.0
Power Out (Relative)
20
59
85
16
57
84
17
59
87
17
55
84
1.9V
1.3 V
1.0 V
2.8 V
2.0V
1.6V
12V
12V
12V
1.4 V
1.2V
0.85 V
Die Size (MIL)
V(onlIN
V(on)OUT
Case Temp
0.4 A @IMAX (0.1 !'8)
0.2 @ IMAX (0.1 I's)
2.2 @ IMAX (10 !'8)
1.2V
0.4 V
0.12V
2.1 V
1.3V
0.78 V
1.7V
0.9 V
0.15V
2.0 V
1.5V
1.0V
36.6·C
32.9·C
38.3·C
43.6·C
41.3·C
40.4·C
42.3·C
36.0·C
29.5·C
39SC
41.1'C
38.2'C
*CIock varied with temperature
TMOS MTP12N06
At low frequency and low motor current, the TMOS is the most
efficient device. Its input drive power is extremely low and its On
voltage, due to the zero offset, relatively linear rDS(on) is low.
DARLINGTON TIP100
Total device dissipation and thus case temperature rise is due to
input and output dissipation. The Darlington, with its high VCE(set),
can stili have lower case temperature than the bipolar at some peak
collector currents, due to its low drive power.
BIPOLAR 2N6487
The bipolar, with its low VCE(set), has low output dissipation but
its input power is the highest to setisfy high collector current - forced
f3 conditions.
At medium and high load currents, the bipolar has the lowest On
voRage followed by the TMOS with the Darlington and GTO being
about equal in third place.
GTO THYRISTOR (Experimental)
The GTO is extremely efficient at low frequencies from a drive
point of view since it requires only narrow turn-on and turn-off current
pulses, but becomes less efficient as the frequency increases due
to the higher duty cycles involved.
Test Results
The results of this efficiency versus frequency test, as
measured by the case temperature rise using a small
heatsink, are shown in Figure 9-11.
Efficiency as a Function of Frequency Tests
The PMW Motor Control Circuit was tested at a constant, low frequency, so the relative efficiencies measured
were primarily due to static (saturation) losses. To determine the effect of the dynamic (switching) losses, which
increase with increasing frequencies, the four different
devices were tested with a resistive load, using a variable
frequency, constant duty cycle (50%) input signal. The
load current was set for about 4.0 A (VCC = 28 V,
R1 -=7.00) and the same basic test circuit shown in Figure 9-9 was used. Most of the modifications were in the
reverse bias circuit, with the off-bias voltage being either
o V or - 5.0 V for the bipolar, Darlington and TMOS tests
and -12 V for the GTO.
Transistor 04 emitter resistor (2.0 0) was shorted out
to form an off-bias voltage source; 03 emitter was tied to
the + 12 V bus to furnish drive to 04 when VBE(off) was
oV; and differentiating capacitor C2 was increased to 0.02
JLF to allow greater turn-off time for the GTO. Also, the
bipolar forward base current was set fo 600 rnA, resulting
in a f3F of about 7.0.
TMOS MTP12N06
As expected, the TMOS device ran the coolest at higher
frequencies, being very constant in temperatures up to
about 10 kHz and then rising slightly thereafter. At low
frequencies, where static losses predominate, the TMOS
MTP12N06 case temperature was only about 2°C warmer
than the bipolar 2N6487, due to the respective saturation
voltages of about.0;6 V (rOS(on) Typ= 0.150) and 0.4 V.
Although not shown, increasing the off-bias voltage
(VGS(off)) from 0 V to -5.0 V showed only about a 2°C
improvement at 33.kHz, due to slightly faster turn-off time;
otherwise, at lower frequencies, the difference in turn-off
time had little effect in case temperature.
BIPOLAR 2N6487
The bipolar transistor 2N6487 showed marked improve-
MOTOROLA TMOS POWER MOSFET DATA
A-126
140
r----------,,------------,----------,------------,-----------,------------,
VBE(off) = 0 V
RESISTIVE LOAD
LOAD CURRENT
120
f--------
= 4.0 A
DARLINGTON
OUTY CYCLE = 50% .
VBE(off)
TA
= 25°C
= 5.0 V
HEAT SINK: THERMALLOY
6061B
100
E
w
0:
!;;:
0:
80
1-----------+&---6
W
DARLINGTON TIP 100
IL
[j----[] TMOSMTP12N06
w
V----..s;:;
::;;
0-
VBE(off) = - 5.0 V
GTO THYRISTOR
w
en
~
60
o-U
o
~
_________ L_ _ _ _ _ _ _ _ _ _
0.3
0.1
~
_ _ _ _ _ _ _ _ _ _ _ L_ _ _ _ _ _ _ _ _ _ _ L_ _ _ _ _ _ _ _ _ _
3.0
1.0
10
~
__________
~
30
f. FREQUENCY (kHz)
FIGURE 9-11 - TEMPERATURE RISE OF POWER SEMICONDUCTOR AS A FUNCTION OF FREQUENCY
ments in efficiency at the higher frequencies when the
VSE(offl was increased from 0 V (base-emitter clamp) to
- S.O V. Without off-bias, the case temperature approached 11SoC at 33 kHz, whereas, with - S.O V, it was
only about 70°C.
load current rise time is limited by the inductance of the
wire-wound load resistor and that the TMOS switches
much faster. Second, to ensure turn-off of the GTO at
elevated temperatures, the peak reverse gate current with
VGR of -12 V was about 6.0 A with a pulse width of
about 1.0 JJS at the SO% point.
DARLINGTON TIP100
The low voltage TIP100 Darlington does not have a
speed-up diode across its input emitter-base resistor and
thus the stored charge of the output transistor cannot be
efficiently removed. Consequently, there is no improvement in case temperature at low or nominal frequencies and only some moderate improvement at 33 kHz
(117"C relative to 133°C) when the off-bias was increased
to -S.O V.
The Darlington, with the highest saturation voltage of
the four devices, not surprisingly, had the highest case
temperature at low frequencies and, beyond S.O kHz, was
about as inefficient as the GTO.
GTO (EXPERIMENTAL)
The experimental GTO exhibited static losses somewhere between the bipolar and the Darlington due to its
on-voltage of about 1.2 V at 4.0 A. The device did perform
at 33 kHz, however, its case temperature rose to about
12SoC. This was due to its relatively slower switching
times, as shown by the oscillograms in Figure 9-12. Figure
9-12 (a), (b) and (c) show the 33 kHz waveforms of anode
current, anode-cathode voltage and gate current, respectively, relative to the TMOS drain current (Figure 9-12d)
and drain-source voltage (Figure 9-12e). Note that the
The GEMFET versus the MOSFET and
Bipolar
The GEMFET (Gain Enhanced MOSFET) is a new
power semiconductor device with a combination of characteristics that were previously unavailable to the designer
of power circuitry. Closely related to the power MOSFET
in structure, this device has a forward voltage drop comparable to bipolars while maintaining the high input impedance and fast turn-on of its isolated gate. While turn-on
speeds are very fast, turn-off is presently relatively slow
and will restrict the use of at least the first generration of
these devices to lower frequency applications.
The most pronounced advantage of the GEMFET over
the power MOSFET is its lower on-resistance. The
rDS(on) of a high voltage MOSFET is fairly large and rises
with increasing junction temperature and drain current.
Conversely, the rDS(on) of a GEMFET decreases with
increasing TJ and is not greatly affected by 'D. Since the
MOSFET does not have the GEMFET's offset voltage in
its output transfer characteristics, at low currents the
MOSFET on-resistance is slightly lower. However, at high
currents and temperatures, the difference is dramatically
in favor of the GEMFET.
MOTOROLA TMOS POWER MOSFET DATA
A-127
II
VAK=
10V/0IV
0-
FIGURE 9-12a -
FIGURE 9-12b -
GTO ANODE CURRENT
GTO ANODE-CATHODE VOLTAGE
MeR 5050
0-
R L"'7n
WIREWOUNO
RESISTOR
IG = 2A/OIV
,= 51's/OlV
FIGURE 9-12c -
GTO GATE CURRENT
10= lA/OIV
,= 51's/0lV
MTP12N06
0-
FIGURE 9-12d -
TMOS DRAIN CURRENT
FIGURE 9-12 -
FIGURE 9-128 -
TMOS DRAIN-SOURCE VOLTAGE
COMPARATIVE SWITCHING OF A GTO AND TMOS AT 33 kHz
To illustrate the relative efficiencies of these two
TO-220 devices - MGP20N50 GEMFET and MTP4N50
MOSFET - with that of a comparable die size, TO-220,
high voltage Switch mode bipolar MJE13007, the .Iow frequency, PWM motor controller test described in the previous section was performed. The results of a duty cycle
versus case temperature rise test is shown in Figure 913. Note that at his low frequency test, where saturation
losses predominate, the GEMFET is much more efficient
than the MOSFET at low duty cycles (high motor armature
currents), and even runs cooler than the bipolar device
as the pulse width increases (motor current decreases).
The second test, comparing the three devices with an
inductive load at several frequencies (the inductances
were changed to maintain the same peak currents for all
frequencies) is illustrated in Figure 9-14. Now, at the
higher frequencies, the GEMFET runs the hottest - due
to its slow turn-off switching time - and the MOSFET
becomes more efficient than the bipolar at about 25 kHz.
For more information on the GEMFET, please refer to
Chapter 8, the Spin-off Technologies of TMOS.
The Efficiency of TMOS versus Bipolar and
Darlington Devices in the Energy
Management Package
In high current packages, FETs add a new dimension
of capabilities to power semiconductors. With ratings that
allow operation in excess, of 100 A, field-effect transistors
now compete with other types of switches in heavy duty
applications.
High current packages that were originally intended for
bipolar Darlingtons are readily adapted to FETs. These
Case 353 packages, labeled Energy Management Series
(EMS) are, shown in Figure 9-15.
In addition to testing relative efficiencies of devices encased in TO-204 (TO-3) and TO-220 packages, comparative temperature tests were also run on the EMS of transistors. The OUTs were the lOW-VOltage, medium-current
power MOSFET, MTE100N06 (100 A, 60 V) and similar
die-size, low-voltage, experimental bipolar and Darlington
transistors. The results of this resistor-load, variablefrequency test (100 Hz to 12 kHz) is shown in the temp-
MOTOROLA TMOS POWER MOSFET DATA
A-128
80
11",1,
70
\
60
~
~
:::>
~
i;l:'
:;;
~
50
~
\ "-
~
u
U
>-
/
7
FIGURE 9-15 -
BIPOLAR TRANSISTOR
'">/
,./
.......
40
10
-
~
160
FIGURE 9-13 -
~ 0~7 ri, ~06 ~
RL
II
ID ~ IC ~ 30 A
DUTY CYCLE ~ 50%
TA ~ 25'C
140
GEMr
~
~ 120
30
20
HEA~ SINt
:::>
40
50
DUTY CYCLE 1%)
60
70
80
g
100
ON-STATE EFFICIENCY COMPARISONPWM OF DC MOTOR
~
80
120
~
~
:::>
~
90
'"
60
i;l:'
~
~
-
Cl
VCl
tlZ
10
GateJ
I
::I
(,.)
"0
.sdJ
FIGURE 10-4 - IDEALIZED WAVEFORMS OF A DUAL
CLAMPING SCHEME PROVIDING DRAIN-80URCE
OVERVOLTAGE PROTECTION
effeCt of the clamping factor. Automotive button surge suppressors, such as the MR2525. performed well during
development and testing of Motorola's multi-chip power
MOSFETs.
To ensure that the voltage appearing across the drainsource terminals does not exceed the maximum VOS rating, proper measurement techniques are warranted. For
very rapid switching, flyback voltage transients should be
measured with a wideband oscilloscope and voltage
probe (> 150 MHz). The use of probes with grounding
leads is not recommended. Rather, a chassis-mount test
jack, with Its ground soldered directly to the source lead
and its tip to the drain, is a more precise technique.
Even with an ideal RF layout and a perfect drain-source
voltage clamp, large· di/dt's may necessitate considerations of the effects of the parasitic package inductances.
"ON" VOLTAGE COMPARISON
FETs are often associated with higher levels of on-state
power dissipation than bipolars, particularly at higher
power levels. While this perception is accurate at powerline voltages. at voltages below 100 volts, FETs have a
distinct advantage. Figures 10-9 and 10-10 illustrate the
Drain
Terminal
VDS DERATING FOR LARGE di/dt's
When a MOSFET, including both multiple and singledie devices, generates a large di/dt at turn-off, the source
and drain package inductances can produce significant
drain-source voltage stress in addition to that observed
at the device terminals. This situation deserves special
attention in multi-chip devices, in part due to the larger
package Inductances. The increased magnitude of the
current being switched also exacerbates the problem.
Since the circuit designer has no control over internally
generated voltages, a derating of the maximum allowable
VOS is warranted when large currents are switched rapidly.
The circuit elements internal to the "Medium Current"
multi-chip MOSFET, including the significant parasitics,
are illustrated in Figure 10-S. The three individual source
inductances represent the inductance of the source wirebonds, and the inductances at the source and drain terminals model the source and drain bus. Figure 10-6 shows
an oscillogram that compares the drain-source flyback
Gate
Terminal
Source
Terminal
FIGURE 10.5 -INTERNAL CIRCUIT
ELEMENTS OF MEDIUM CURRENT
POWER MOSFET
MOTOROLA TMOS POWER MOSFET OATA
A-136
t
I
10
20 AlDIV
1
;
~
II
J
I
;
VOS
20 VIDIV
o
20 ns
20 ns
FIGURE 10-88 - DRAIN CURRENT AND DRAIN-SOURCE VOLTAGE
APPEARING AT TERMINALS - MTE60N20 OFF BIAS = -4.0 VOLTS
FIGURE l006b - DRAIN CURRENT AND DRAIN-SOURCE VOLTAGE
APPEARING NEAR CHIPS - MTE60N20 OFF BIAS
-4.0 VOLTS
.........
.........
=
-
.......
Peak VOS at Terminals
r.....
.......
Vclamp
MTE1ooN06
""
..........
["'....
101------1.
........
.......
MTElooN05
I
I
I I
w
w
r.....
.......
t-....
f"'....
~
~
I'....
Vos
f"'....
~
o
60
VOSM.' PEAK DRAIN·TO·SOURCE VOLTAGE (VOLTSI
FIGURE 10-8 - CONDITION AT WHICH dl/dl-VDS
DERATING IS COMPUTED
FIGURE 10.7 - MAXIMUM ALLOWABLE dloJdt
PEAK DRAIN-SOURCE VOLTAGE FOR MTElOON06
~O
320
280
~~
en
en
9
~
~
u
!5
V>
240
200
EQUIVALENT BIPOLAR
2N5883(x31
160
~
-,.,:::::. ~
20
!.i~
/
9
....- ~ V
.... ~ ~
60
V
./
u
MTE100N06
MOfFET
80
VCEO = VOSS = 200 V
TA = 25"C
~
!5
en
100
----
r-
~
r-200
~
20
100
IL' LOAD CURRENT (AMPI
/
300
en
en
. / "/
120 ~~CEO = VOSS = BOV
TA = 25"C
80
en
/
V
/: ...-V
/
"';;TE60N20
MOSFET
"".,.
L
~048
BIP
~~
100
~
90
u
80
~
~ 70
60
50
I >175'C
I
I
Duty Cycle = 50%
TA :: 25"C
Heat Sink:: 4" X 4w x 'lAo" COPPER PLATE
I
I"' IIIII1
VGS(off)
VGS(off)
VGS(off)
EXP LV DARLINGTON
EXILi~~f.l..l:
'I-_t1 l
'1
I
= 0 V, RG = 50 n
= 5.0 V, RG = 50 n
= 0 V, RG = 10 fI
~n-J.xml
0.1
,
At. '" O.67fi.6OQW
1e='o=30A
4>
-~.
z
--::: -::::::-
TMOS MTElOON06
1.0
I 120'C
,
.\
"'\r\
",
"\
r",
u;
c.
E
~
2.0
Rated DC FBSOA
TC = 25'C
Ul
9
1.0
100 ms Pulse
,r-.
",
~msrse
"
m
i
~
"
"
"
u
.~
creases with increasing current at a constant power level,
it was thought that the same may be true for power MOSFETs and that this could steepen the SOA slope (46). If
R6JC increases with voltage (decreasing current), the device would not be able to dissipate as much power at the
high voltage, low current end of the curve.
To investigate this premise, many thermal resistance
measurements were taken on the OUTs, all at a constant
power level, but varying 10 and VOS (VOS1 101 = VOS2
102, etc.). A thermal resistance fixture that used a switching technique to measure the voltage drop across the
parasitic drain-to-source diode was used initially. The inherent measurement error in this method tended to suppress any trends in the variation of R6JC with 10.
A second method that measures the junction temperature of a decapped device with an infrared microradiometer proved to be more accurate. The instrument read
out an average temperature of about 10.0% of the die
area that was located in the center or the hottest part of
the chip. Again, 10 and VOS were varied while Po was
held constant. As shown in Figure 11-7, R6JC does decrease with increasing 10 at a constant PO, like bipolars,
but the 10.0% change in R6JC is not enough to account
for the approximate 30.0% change in power handling capabilities (m = 1.4). Although R6JC varies and does steepen the FBSOA slope, it has only a partial effect under
these test conditions. These results must be qualified because the equipment did not allow the measurement of
R6JC at a power level near the FBSOA limits where the
change in R6JC could be more or less significant.
The failure mechanism and thus the slope of the curves
obtained from the FBSOA test fixture, is a function of
junction temperature, VOS, 10 and a variable thermal resistance. Because the junction temperature rose so high,
the device could be going into avalanche breakdown
which would be a strong function of VOS, as the curves
indicate. This temperature at failure is above TJ(max) ratings and demonstrates why users must not exceed published SOA curves.
1.37
, ""
,
0.5
0
0.2
0.1
10
100
20
50
Drain Source Voltage, VDS (Voltsl
200
FIGURE 11-3 - DC FBSOA OF MTM5N20
The questions "Why does the empirical FBSOA slope
deviate from the - 1.0 slope of constant power?" and
"What is the significance of the slope on the SOA curves?"
still remain. Since thermal resistance of bipolars de10
'-.
5.0
,
'I.
"
I\.
\
,,
"
~
2.0
E
~
i
~
,
I\.
"\
'-,
i\
?=
,
\
"-
1.3
"
0.5
Bipolar Transistor
\
~~
"
'. ,""'I.
.~
0
1"<
1.0
u
"
"
V ,
Rated DC FBSOA
TC = 25'C
Ul
9
TC> 120'C
One Second Pulse
r\
~~
===
"
N-Chann~1 ~
Line of Constant
Vpower Dissipation
MOSFET
,
~
\
50
100
20
Drain-Source Voltage, VDS (Volts)
'\
~
WithlWithout
Negative Resistance
Effect
0.1
10
I"-
,~
\\.
0.2
200
I'
Log of Drain Voltage (Voltsl
FIGURE 11-4 - DC FBSOA TEST ON MTP7N20
FIGURE 11-5 - COMPARISON OF TYPICAL FBSOA SLOPES
MOTOROLA TMOS POWER MOSFET DATA
A-145
N
Drain
FIGURE 11-68'- TYPICAL CURRENT FLOW IN TMOS
POWER MOSFET
FIGURE
FIGURE 11-6b - CURRENT FLOW DURING AVALANCHE
"-6c - CURRENT FLOW DURING NEGATIVE RESISTANCE BREAKDOWN
Since power MOSFETs or, for that matter, bipolar transistors, do change their thermal resistance as operating
conditions vary, this could warrant a change in the published SOA curves. The thermally limited portion of the
curve is presently based on one thermal resistance reading taken at a single operating condition. If this is a worst
case reading (taken at low current, high voltage), this
could significantly underrate the device at the highcurrent, low-voltage portion of the curve. Conversely, if
the reading is taken at the high-current end, this could
overrate the device at the' low-current end. Further study
needs. to be done to determine if the change in Rruc is
significant enough to alter the way manufacturers derive
published SOA curves.
The significance of the slope greater than minus one,
as accurately derived from the non-destruct FBSOA
tester, is that a simple power limit of, say, 75 W may not
be appropriate because it could overrate a device under
certain conditions and underrate the same device at the
same power level but lower voltage and higher current.
Motorola establishes conservative derating of RruC to
ensure reliable operation under all bias conditions.
Turn-off Switching SOA of Power
MOSFETs
One of the advantages of power MOSFETs over bipolars is its superior reverse bias safe operating area
(RBSOA) performance. Power MOSFET RBSOA curves
are generally "square" at IO(max) and V(BR)DSS, (Figure
11-8) indicating that performance is bounded only by maximum voltage and maximum pulsed current ratings. In
other words, MOSFETs are not generally RBSOA limited.
There are possible exceptions to this rule, however. As
noted in thedv/dt section outlined earlier in Chapter 4,
rapid changes in drain-source voltages can limit the RBSOA
(tum-off switching SOA) capability of the MOSFET due to
the injected current into the Crss capacitance inadvertently
biasing-on the MOSFET.
Many practical power loads are inductive which can
cause severe stress on the power switching device during
turn-off. Due to the nature of an inductive load line, the
switch, be it a power MOSFET or bipolar tranSistor, can
simultaneously experience a high current and high
0.900
~
l\oeVice #1
0.850
"~
~
u
01
a:
8'
lii
0.800
~
1;)
~
~ce#2
1\r--
OJ
E
Q)
{5.
0,750
0.700
0.0
r--
1.0
2.0
-.......
3.0
Drain Current, 10 (Amps)
FIGURE 11-7 - THERMAL RESISTANCE OF MTM12N10 versus
DRAIN CURRENT AT Po = 50 W
MOTOROLA TMOS POWER MOSFET DATA
A-146
20
rate dictated by the time-constant of the relatively large
inductance in the collector circuit. When the DUT tums
off, the energy stored in the inductor (E = 1/2L1CM2) has
to be dissipated in the transistor since there Is no external
circuit, or clamp, to "catch" this energy as the current
ramps down. Also, immediately at tum-off, the collectoremitter voltage flies back up due to the "inductive kick"
(v = L dildt). If the stored energy is great enough and the
transistor tum-off time fast enough, this voltage will fly
back to the breakdown voltage ofthe device (V(BR)CEX),
causing the transistor to avalanche. The transistor thus
has to dissipate the energy due to this unclamped operation by sustaining its breakdown voltage until the collector current falls to zero and the inductor discharges. The
maximum energy that the device can sustain, defined as
Second Breakdown Energy (ES/b), is determined by increasing the collector current until the device fails. Usually
this current is below the nominal operating current of the
device since the transistor has to absorb the relatively
high inductor energy and generally cannot sustain its maximum specified current. Theory and practice have shown
that most low-voltage transistors have decreasing Es/b
capability with increasing reverse-bias voltage due to current croWding.
The unclamped inductive loads stress the power
MOSFET in a similar manner. Now, the failing drain current will cause the flyback voltage to avalanche the drainsource of the MOSFET (V(BR)DSS).
The problem with this Es/b rating is that the derived
energy is only related to that particular inductance and is
highly dependent on its Q (quality factor, i.e., series re-
16
~
:;
~ 12
MTMlMTP7N12
!Z
MTM/MTP7N15
~
a,
z
I----
MTMlMTP5N18
8.0
MTM/MTP5N20
:
c
.9 4.0
TJ'; 150°C
o
o
40
80
120
160
VOS. DRAIN·TO-SOURCE VOLTAGE IVOL,S)
200
FIGURE 11-8 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
voltage. Depending on whether the switch is unclamped
(Figure 11-9a) or protected with a clamp circuit (Figure
11-9b) will determine the two energy limitations during
inductive turn-off: Second Breakdown Energy (Eslb) and
RBSOA.
SECOND BREAKDOWN ENERGY (Es/b)
Power transistors were originally characterized with an
unclamped inductive load (Figure 11-9a). The Device Under Test (DUn, typically a low voltage, extremely rugged
transistor, is turned on by applying a positive pulse to its
base through a resistive network terminated in a reverse
bias voltage VBB2. Collector current then ramps up at a
FIGURE 11-9& - UNCLAMPED,
Eslb
FIGURE 11-9b - CLAMPED,
RBSOA
VCC
Voo
L<1.0 mH
L>1.0 mH
~G:::{'~'q
our
VI~
V[]l(BR)CEX.
VCC
I
--, VCE(sat)
I
I
I
VGS(off)
V
Clamp
VCE
(VCe)
VOO -'~-f---l
:
I
I
~I----:
ICM
IC:
I
o
o
I
I
I
I
I
I
'FM ~I____ I
I
.
o
FIGURE 11-9c - TURN-OFF TIMES EXPANDED
'Waveforms shown for MOSFET OUT.
Bipolar Terms in Parentheses.
FIGURE 11-9 - INDUCTIVE LOAD SWITCHING
MOTOROLA TMOS POWER MOSFET DATA
A-147
.I
,
sistance). Additionally, the indUctance specified to achieve
Eslb is generally quite large, 10 mH or greater, and does
not represent the real world .inductance seen in Switchmode applications. Finally, and most important, most applications use some form of celamping to prevent drainvoltage breakdoWns. For tlJis reason, most high voltage
switching transistors are specified with a clamped inductive load.
RBSOA
.. '
..
A more precise and definite' inductive turn-off rating is
the clamped inductive turn-off fating labeled RBSOA. In
the simplified test circuit of Figure 11 '9b, the OUT is subjected to a real world clamped condition. The inductance
ne.ed be only large enough to ensure that the flyback time
is greater than the drain current fall time, generally resulting in inductances from 100 pH to 1.0 mHo These
values also more accurately represent the leakage inductances encountered in switching applications.
To subject the device to the greatest stress during turnoff, the inductance should be of high Q to ensure that the
peak drain. current, 10M,and'flyback voltage, VOSM, are
simultaneously presented to the OUT, Figure 11-9c, resulting in a turn-off load line that approximates a rectangle.
Under these conditions, 10 will start to fall· when VOS
forward .biases the clamp diode, at which time the stored
indllctor energy (current) will be transferred to the external
diode circuit.
To determine the RBSOA capability of the device, 10M
is set to a typical operating current and the clamp voltage
is increased until the transistor goes into second break~
down. Then other current levels are tested until the complete RBSOA curve is established. These second breakdown paints relate to the energy dissipated in the device
during turn-off, specifically the crossover time tc , (Figure
11-9c) and represents the energy encountered in inductive switching applications, (whereas, the lower 10M for
the unclamped Es/b mode does not). Reverse biasing in
this example is provided by a transistor clamp from the
gate of the N-Channel MOSFET to either a negative voltage or ground.
SWITCHING SAFE OPERATING AREA (SSOA)
The term Switching Safe Operating Area is the generalized SOA limitation during turn-on and turn-off of the.
power MOSFET. Turn-off switching SOA is equivalent to
RBSOA for bipolar devices and will henceforth be used
to describe this characteristic.
The straightforward method of determining the turn-off
switching SOA is through destructively testing the power
MOSFET in the clamped inductive turn-off circuit. This is
accomplished by setting the drain current to a specified
value by either adjusting the applied input pulse width
(tPW) or the drain supply voltage VOO since 10 '"
vooLt pw . Then the clamp supply voltage is gradually
increased until one of two conditions occurs. If the specified 10 is less than the 10M rating, the clamp voltage can
be increased until the device avalanches and begins dissipating the inductor's energy. Since the MOSFET is operating in an Es/b mode at this point, failures may occur.
At drain currents greater than 10M, the device is operating outside its current ratings and the MOSFET may
fail at clamp voltages less than V(BR)OSS. In short, the
MOSFET's SSOA curves guarantee that the locus of failures is outside the 10M - V(BR)OSS boundaries. The
SSOA curve shown in Figure 11-13 is applicable for both
turn-on and turn-off of devices with switching times less
than one microsecond.
Normally a destructive fixture is used to ensure that the
fail paints lie outside the turn-off SOA boundaries. This
requires testing of many devices and device trends are
difficult to determine. The use of a non-destructive fixture
greatly simplifies establishing the SSOA ratings since usually only one OUT can be used to generate a complete
turn-off switching SOA curve.
N-CHANNEL NON-DESTRUCT TURN-OFF
SWITCHING SOA TEST FIXTURE
In order to save the OUT from the normally destructive
second breakdown energy, the stored inductive energy
must be quickly diverted from the transistor to an external
crowbar circuit. A test fixture, based on the work done at
the United States National Bureau of Standards,31 was
designed to have the capability of crowbarring as much
as 50 A and blocking as much as 1000 V. The 10 A
crowbarred propagation delay was about 70 ns and the
current rise time was about 40 ns. Triggering of the crowbar was accomplished by detecting the fast rate of change
of the collapsing drain-source voltage once the device
weht into second breakdown. Using this test fixture, a
complete SOA curve can often be formed using only one
OUT; consequently, the OUT must sustain as many as 30
or 40 crowbars (second breakdowns) to establish the
curve. Not all devices will survive so many crowbars without degradation or failure, but a large percentage do, allowing a relatively simple and non-ambiguous curve to be
generated. Oegradation is measured by a relatively large
change in drain leakage current, lOSS, after testing. For
this magnitude of leakage current change, subsequent
retesting will usually show a decrease in device turn-off
SOA capability.
The main elements of the non-destruct SOA test fixture
are illustrated in the block diagram of Figure 11-10. Of
these blocks the most important are the Orive Circuit consisting of the VGS(on) and VGS(off) Transistor Switches,
the Oetector/Crowbar and a Pulse Generator capable of
being inhibited when crowbarring occurs. Of secondary
importance are the VOO Switch, and a Greater than 10%
Outy Cycle Lockout circuit. Also required is an externally
connected inductor, typically about 200 IJ-H.
Referring to Figure 11-10, the circuit operates as follows: An input pulse, Yin, is applied to the input of the
Orive Circuit controlling the three respective switches,
VGS(on), VGS(off), and VOO· The VGS(on) switch supplies the positive turn-on gate voltage and concurrent with
its turn-off, the VGS(off) switch is turned on. The drain
suppiyis also turned on (VOO switch) when positive gate
voltage is applied and, to ensure proper system operation,
will remain on for several microseconds (due to drive transistor storage time) after removal of the input pulse. Ouring
this on-time, the collector current ramps-up and, upon
MOTOROLA TMOS POWER MOSFET DATA
A-148
•
VClamp
DUT
Differentiator
FIGURE 11-10 - BLOCK DIAGRAM OF THE N-CHANNEL NON-DESTRUCT
TURN-OFF SWITCHING SOA TEST FIXTURE
turn-off, the drain voltage flies back. When the f1yback
voltage reaches the clamp voltage, the inductor current
is transferred to the clamp circuit. The drain voltage will
then fall at a relatively slow rate, typically a couple of
hundred nanoseconds, as the energy stored in the inductor is completely discharged.
If, however, excessive energy is applied to the OUT
during this switching time, the FET can go into second
breakdown. Then the drain voltage falls very rapidly, possibly in less than 10 ns. When this occurs, the low R-C
time-constant Oifferentiator detects this fast falling waveform - discriminating against the normal slow falling waveform - and produces a negative-going pulse which ultimately triggers the crowbar. The crowbar fires and the
current in the OUT is quickly diverted to the crowbar,
removing the turn-off energy stress from the transistor.
The Pulse Generator is also disabled, preventing any successive pulses from being reapplied until the system is
reset.
DRIVE CIRCUIT
The drive circuit for the SOA test fixture is shown in
Figure 11-11 and consists of the three aforementioned
switches. A Oarlington transistor, 01, is used to buffer the
CMOS-derived input pulse of 15 V from the drive circuit.
Positive gate voltage is generated by turning on the
NPN transistor, 02, with the positive going input pulse.
This stage supplies drive to the PNP Baker-clamp-,
configured transistor, 03, whose output feeds the gate of
the OUT, turning it on.
Reverse bias is derived by differentiating the input pulse
with the R1Cl network. The generated negative-going
pulse; which is coincident with the trailing edge of the
input pulse, then turns on PNP transistor, 04, and the
following NPN transistor, 05.
This off-bias voltage pulse is set by R1Cl and, for the
values chosen, is about 10 /Ls. Also, due to the trailing
edge coincidence of the two pulses (plus approximately
equal propagation delays through the two respective
switches), the transition time between VGS(on) and
VGS(off) can be relatively fast for some OUTs and operating conditions, approaching less than 200 ns.
The drain switch is used as a safety device, removing
current from the inductor if the OUT were to fail short.
This circuit utilizes two cascaded Baker-clamped monolithic Oarlingtons (NPN 06 and PNP 07) to reach the 50
A capability of the fixture. The Baker-clamp diodes (03,
04 and 05, 06) minimize the storage time of this switch
after the OUT is turned off.
Once the OUT is turned off, the inductor-stored energy
is dissipated through the two clamp diodes (07 and 08
for high-voltage capability), the clamp supply and filter
network, and 07 clamp diode 09. Diodes 010 and 011
in the drain circuit of the OUT are used to prevent reverse
drain currents from flowing and also to ensure that the
crowbar saturation voltage is lower than the parasitic transistor second breakdown voltage, thus diverting the drain
current.
Drain current can be monitored by the current loop as
shown. Additionally, the current-sense resistor, R2, can
be used to monitor 10, but care must be taken in the layout
to minimize ground loops which can distort this current
replica. As in any high-speed, high-current switch, good
RF techniques should be used in the layout.
DETECTOR/CROWBAR CIRCUIT
As previously mentioned, an RC differentiator is used
to discriminate between the normal VOS fall time and
second breakdown fall time; the components used are a
1.0 kV capacitor, C2, fixed resistor R3, and Sensitivity
Control R4.
Originally, the output pulse from this network fired a 25 A
MOTOROLA TMOS POWER MOSFET OATA
A-149
•
SCR as a crowbar, but the tum-on time of about 600 ns
proved to be too long to save the DUT. What is required
is a fast latching crowbar. This is now achieved by using
a common-base-connected NPN transistor, 010, as a
level detector-pulse amplifier, triggering a fast, discrete
monostable multivibrator (MV) consisting of PNP transistcrs 011 and 012. This 25 JLS MV, which allows adequate
time for the inductor stored energy to be dissipated, then
drives the direct-coupled NPN transistor, 013, and following PNP transistor, 014, to a power level capable of tuming on the crowbar. Diode D12 is used to block any noise
pulses on the VDD line from false triggering the monostable MV.
The crowbar consists of four parallel MJ 10011 monolithic Darlington transistors (015-Q18) selected for VCEO
greater than 1000 V. This transistor, designed for horizontal deflection circuits, offers the best blocking voltageswitching speed tradeoff of the several different devices
tested. By using fast, wide-band transistors throughout,
propagation delay and rise time of 70 ns and 40 ns, respectively, were measured at an IC of 10 A.
Diode D13 and resistor R5 prevent possible high dv/dt
+15V
P.W.
Con<
MC14001
0.001 pF
+15V
'50'
+1SV
470 ,
'Ok
Rep Rate Cont.
0.001 F
Control Circuit
'Ok
sao
..... sw
'3
~LED'
LED Indicator,
Pulse Inhibit
019
2N5060
0.1
-=
'"
1.0k
'00'
470'
>10% Duty Cycle
Lo<,"""
~
-=
2000
'"
25V·
,,",DC
LED
C,
12pF
1,OkV
R3
1.0k
(4)
MJl0011
01S-018 r--1f--.....- _ . . . . J
R4
R8
'00
'00
FIGURE 11-11- N-CHANNEL POWER MOSFET NON-DESTRUCT TURN-OFF SWITCHING SOA TESTER 1000 V, 50 A
MOTOROLA TMOS POWER MOSFET DATA
A-150
flyback voltages from falsely turning on the crowbar.
The resistor-diode networks (RS-9, D14-21) in the respective Darlington emitter circuits serve both as a ballasting-voltage clipping circuit and a crowbar indication
source for the second breakdown LED indicator circuit. .
PULSE GENERATOR
The timing functions for the Non-Destruct Turn-off SOA
Test Fixture are generated by a quad, 2-input NOR gate,
MC14001. These gates are configured as an astable MV
(gates A 1 and A2) clocking a monostable MV (gates A3
and A4) for pulse-width generation. By setting the RepRate Control and the Pulse-Width Control, periods of from
90 JLS to 1.4 ms and pulse-widths of 4.0 JLS to 180 JLS are
achievable.
The Control Circuit produces free running pulses whose
duty cycle should be maintained at less than 10% (limited
by the driver circuit resistor power ratings). One-shot operation can also be generated by simply setting switch S2
to the one shot position and depressing the pushbutton
start switch S1, thus providing a triggerto the Pulse-Width
Mono MV.
COMPLETE N-CHANNEL NON-DESTRUCT SOA
SYSTEM
Included in Figure 11-11, the complete N-channel NonDestruct Turn-off Switching Tester, are two other circuits
not previously described. They are:
breakdown voltage of the switch. Various types of suppressors or "snubber" circuits such as Zeners, MOVs, RC
networks and clamp or "free-wheeling" diodes are generally used. The energy stored in the inductor is diverted
from the transistor at turn-off and is harmlessly dissipated
in the snubber, thus protecting the transistor switch.
To protect Single power MOSFET switches, the snubber
can be placed across either the inductor or the MOSFET.
A Zener diode or RC snubber circuit can protect the drainsource of the power MOSFET but a simple clamp diode
across these terminals will not, as it will only come into
operation if its reverse blocking voltage is exceeded. However, in the multitransistor configurations commonly used
for switching regulators, inverters and motor controllers,
clamp diodes across the semiconductor switches are frequently used (Figure 11-12). The diodes do not protect
their respective FETs but rather the complementary FET.
As an example, in the totem-pole configuration of Figure
11-12c, diode D2 protects Q1 and D1 protects Q2.
To illustrate this, assume Q2 is initially conducting,
causing load current to flow up through the inductor from
ground. When Q2 turns off, the inductive current will continue but now through 01, through the power supply V +
and return to the ground side of the inductor. Consequently, the fly-back voltage will be clamped to V + (from
V - ), resulting in an amplitude of 2.0 V + when V + equals
V-.
If the output power devices are power MOSFETs with
D-S diodes, the question arises as to whether these
diodes are capable of adequately clamping the turn-off
inductive load current. In other words, do the diodes switch
fast enough and can they take the commutated load current?
The following discussion characterizes the O-S diode
of a number of power MOSFETs so that the circuit designer can make the performance/cost comparisons between using these internal diodes or discrete outboard
ones.
1. The Greater Than 10% Duty Cycle Lockout Circuit.
2. The LED Indicator/Pulse Inhibit Circuit.
The 10% Duty Cycle circuit integrates the input pulse
train with an RC network in the base circuit of the smallsignal PNP Darlington MPSAS5 (Q8). The resultant dc
base voltage is compared with the emitter reference voltage derived from a 1N914 diode (D20). At duty cycles
greater than about 15-20%, the Darlington will turn-on,
lighting a LED indicator and turning on the NPN 2N3904
(Q9) transistor clamp across the input of the MPSU45
emitter follower (Ql). This effectively limits the duty cycle
and the power dissipated in the drive circuit.
The LED Indicator/Pulse Inhibit circuit is enabled when
the crowbar fires. The control signal is derived from the
emitters of the Darlington crowbars and fed to the gate of
the second breakdown SCR (Q19), turning it on. Placed
in the anode circuit of this SCR are the series-connected
second breakdown LED, reset switch (S3) and base biasing resistors for the 2N390S pulse inhibit transistor (Q20).
Thus, when the SCR fires, the LED will turn on, indicating
second breakdown. The inhibit transistor will also turn on,
placing the input to astable MV (A 1) high, thereby disabling the pulse train. The system is enabled by opening
(depressing) the normally closed pushbutton reset switch,
thus unlatching the SCA-
SWITCHING CHARACTERISTICS
The important switching characteristics of clamp diodes
in switch mode applications are reverse recovery time, trr ,
and turn-on time, ton. Diodes with long trr times can cause
excessive turn-on stress on the FET they should be protecting as both the diode and the FET will be conducting
during this time interval. The result will be a feed through
drain current spike which could exceed the forward bias
SOA of the FET. If the diode has relatively slow ton times
or high overshoot voltage - modulation voltage
VFM(DYN) - then, in a similar manner, the FET might
not adequately be protected during inductive turn-off.
In the past, most semiconductor manufacturers would
characterize and specify (if they did it at all) the internal
diodes for switching, using the JEOEC suggested circuits
of Figure 11-13a and 11-13b. There are several problems
associated with these circuits; for one, they were originally
developed for sine-wave rectifier applications. As such,
the trr test circuit would produce a half sine-wave of controllable current amplitude, IFM, and di/dt of the current
fall time. However, since the current waveform was derived from a capacitor dump, tuned circuit, the resulting
Characterizing Drain-To-Source Diodes Of
Power MOSFET For Switchmode
Applications
When turning off inductive loads with a semiconductor
switch, some means must be used to suppress, limit or
clamp the resulting "inductive kick" from exceeding the
MOTOROLA TMOS POWER MOSFET DATA
A-151
01
02
FIGURE 11-128 - COMMON SOURCE
FIGURE 11-12c - TOTEM-POLE
FIGURE 11-12b - COMMON DRAIN D-S
Compl~mentarv
Push-Pull
V+
L
J
L
FIGURE 11-12. - H BRIDGE
FIGURE 11-1211 -1/2 BRIDGE
FIGURE 11-121 - TRANSFORMER PUSH-PULL
FIGURE 11-12 - MULTIPLE POWER FET DRIVE CONFIGURATIONS USING D-S DIODES
current duration tp was dictated by IFM and di/dt. Under
some high di/dt conditions, tp can become relatively short
compared to the trr of the device under test (OUT) and
consequently the diode is not fully turned on, thus producing inaccurate trr measurements. To ensure adequate
OUT turn-on, tp should exceed five times trr .
Second, since trr is dependent on IFM and di/dt, what
should these variables be set to? IFM is obvious: it should
be the diverted drain current, but di/dt could be anything,
be it 25 AIJLS or 100 AI p,s, etc. In reality, this diode current
tum-off time is controlled by the complementary FET turnon ,time.
L1
R1
Current Viewing
Resistor
FIGURE 11-13a - REVERSE RECOVERY TEST CIRCUIT AND WAVEFORM
Oscilloscope
Channel B
OUT
Common
OSCilloscope
Channel A
Inverted
Time
FIGURE 11-13b - DIODE TURN-ON TEST CIRCUIT AND WAVEFORMS
FIGURE 11-13 - JEDEC SUGGESTED DIODE SWITCHING TEST CIRCUITS
MOTOROLA TMOS POWER MOSFET DATA
A-152
2 V+
V+
V+
J
vFIGURE 11-148TOTEM-POLE
~-tJL
o
J9
J9
V+~
v-
vFIGURE 11-14b COMPLEMENTARY
V+
P
~
o -U-
2 V+-
V+
FIGURE 11-14c FIGURE 11-14dSIMPLIFIED CLAMP CIRCUIT LEVEL TRANSLATED
FIGURE 11-14eTEST CIRCUIT
FIGURE 11-14 - EVOLUTION OF INDUCTIVE CLAMP TEST CIRCUIT
The problem with the ton test circuit was the difficulty
in defining and controlling the rise time of the current pulse
applied to the OUT. Since this current pulse affects the
measured VFM(OYMI and ton of the OUT, its shape
should be related to the real world conditions.
This is what the proposed test circuit does. Its configuration is derived from a typical two transistor Switch mode
application, be it a totem-pole for characterizing N-channel
O-S diodes or a complementary common source for characterizing P-channel O-S diodes (Figure 11-14). These
configurations reduce to the simple, single-ended inductive clamp circuit (Figure 11-14e) whereby the clamp
diode would be the O-S diode of either the N-channel FET
(totem-pole) or the complementary P-channel FET.
The reverse recovery time is of greatest significance
for continuous load currents common in switching inductive loads. Figure 11-15a describes the idealized current
waveforms when a continuous inductive load current IL
is com mutated between the FET (10) and clamp diode
(IF). Figure 11-15b shows the time expansion of both the
leading and trailing edges of 10 and IF. Note that the drain
current fall time tliC controls the diode current rise time
tflO (or ton) and in a similar manner, the dlO/dt (or triO)
of the drain current turn-on time dictates the dlF/dt of the
diode current turn-off time. Thus, the faster the FET
SWitches, the greater is the di/dt applied to the diode. The
diode dildt then dictates the magnitude of the reverse
recovery time trr and current IRM(REC). Since the current
through the inductor is equal to 10 plus IF the peak drain
current 10M at turn-on will consequently have the magnitude of 10M impressed on it. This is illustrated in Figure
11-16 whereby the switching times of 10 and IF are the
mirror image of each other; the sum of the two waveforms
would yield the inductor current, whose ripple magnitude
is dependent on the switching frequency and load inductance.
An example of discontinuous and continuous load current waveforms are shown in Figures 11-17a and 11-17b
respectively. Note that for the discontinuous case, where
the inductor current IL is allowed to completely discharge,
the dildt of IF is extremely low, thus producing no IRM or
t rr . For the continuous current case, the resultant di/dt
produces significant IRM and t rr .
The size of the inductor used has little, if any, effect on
the trr measurements as shOwn in Figures 11-18a and
11-18b; Figure 11-18a shows the full cycle and time
expanded waveform of diode current for inductances of
FIGURE 11-158 -IDEALIZED CURRENT WAVEFORMS
Turn-On
I
D-S Diode
Turn-Off
I
= 2.5 Aldiv
FIGURE 11-15b - WAVEFORMS TIME EXPANSION
FIGURE 11·16 - SWITCHING CURRENTS OF A
CLAMPED INDUCTIVE LOAD
FIGURE 11-15 - CONTINUOUS LOAD CURRENT
SWITCHING WAVEFORMS
MOTOROLA TMOS POWER MOSFET DATA
A-153
•
L = 100/LH
I = 2.0 Aldiv, t = 100 p.sIdiv
o
o
IRM(REC)
FIGURE 11-17b - CONTINUOUS LOAD CURRENT
FIGURE 11-178 - DISCONTINUOUS LOAD CURRENT
FIGURE 11-17 - THE EFFECT OF SWITCHING INDUCTIVE LOAD CURRENT ON trr AND IRM(REC) OF D-S DIODE
transistor 03 and the following NPN transistor 04. This
transistor acts as the off-bias switch, applying to the driver
a negative voltage pulse (approximately V-) coincident
with the trailing edge of the input pulse and lasting as long
as the R2C1 time constant, about 5.0 JLS for the component values shown.
100 /LH (air core) and Figure 11-18b for a 10 mH (iron
core) inductor. The major difference is the magnitude of
the ripple current, the larger inductor producing a more
constant current source.
TEST CIRCUIT
The test circuit used for generating the diode switching
characteristics, a translation of the "real world" circuit of
Figure 11-14e, is shown in Figure 11-19. It consists of a
CMOS, astable multivibrator (Gates G1 and G2) driving
two parallel connected Gates 3 and 4 as a buffer. Potentiometer R1 varies the duty cycle of the approximately 25
kHz output which therefore sets the magnitude of the OUT
current (along with VOO). The positive-going output from
the buffer is direct-coupled to turn on the NPN transistor
01 and the following Baker-clamped PNP transistor 02.
To produce an off-bias to the driver, which can shape
its turn-off time and consequently the diode turn-on time,
the negative going edge of the output pulse from the buffer
is used. Capacitor C1 and resistor R2 form a differentiating
circuit to produce the negative pulse for turning on PNP
SWITCHING TEST RESULTS
TMOS O-S diodes are usually tested at the rated continuous drain current. The supply voltage VOO should be
greater than 10 V to ensure that the OUT driver is operating with typical transconductance. Since the OUT current is a function of duty cycle and/or VOO, reducing the
input pulse width will allow a greater VOO to be used, if
so required.
Although it is not always possible to test the OUT with
its real world supply voltage (Le., high voltage devices
with higher VOOs than low voltage devices), the results
would be more indicative if it were possible, since 9fs and
switching speeds will vary somewhat with VOO.
10 ~ 2.0 A/div
L ~ 100 ~H
FIGURE 11-188 -100 pH INDUCTOR
'0
t = 5.0
~s/div
~ 2.0 A/div
L = 10 mH
FIGURE 11-18b -10 mH INDUCTOR
t = 1.0 I's/div
FIGURE 11-18 - THE EFFECTS OF LOAD INDUCTANCE ON D-S DIODE REVERSE RECOVERY CHARACTERISTICS
MOTOROLA TMOS POWER MOSFET OATA
A-154
VDD
100 I'H, 30 A
(2)200 I'H, 15 A Inductors
in Parallel
J. W. MILLER: 07828
270 K
Rl: Duty Cycle
Control
f
~
25 kHz
OUT
DRIVER
To Set 0-5 Diode Current 'S,
Adjust Rl and/or VCC
-V", -5.0 V
NOTE: OUT is Shown as an N-Channel TMOS but can also be
a P-Channel when appropriately connected. OUT
Driver is the same device as OUT .Diode (or Complement for P-Channel OUT Diode)
FIGURE 11-19 - TMOS D-S DIODE SWITCHING TIME TESTER
Testing of several different FETs as a function of VDD
showed a second order variation in trr measurements. At
any rate, to ensure measurement repeatability, VDD, frequency, duty cycle and inductor specification should be
listed. For most of the TMOS FETs tested, the inductor
was either one 200 p,H, 15 A rated air core or two in
parallel (100 p,H, 30 A). Whatever the conditions, the DUT
driver and diode under test should be adequately heat
sunk to minimize excessive case temperature rise.
The switching characteristics of an MTM15N15 as
shown in Figure 11-20, and the complete switching results
for the TMOS FETs tested are compiled in Table 1.
Also shown (Figure 11-21) for comparison, are switching photos of discrete rectifiers. Note that the fast recovery
rectifier, as expected, had the lowest trr and that the standard rectifier, the largest t rr . But of even more interest,
the TMOS. D-S diode had the lowest trr of all diodes tested
(Table 1).
From this data, the circuit designer can now decide if
the switching characteristics of the diode are adequate
for his application.
MTM15N15
0-5 Diode Current IS (IF)
FIGURE 11-208FULL CYCLE
IS = 2.0 Aldiv
t = 5.0 I's/div
o
FIGURE 11-20bD-S DIODE Irr
IS = 0.5 Aldiv
t = 100 nsldiv
o
FIGURE 11-20cD-S DIODE Ion
SURGE CHARACTERISTICS
An equally important consideration is whether the diode
can handle the commutated load current in which, under
continuous load current, high duty cycle conditions, the
energy can be quite high.
The TMOS D-S diode is the result of the parasitic NPN
transistor across the FET and as such, actually has more
die area available to conduct diode current than the FET
has for drain current. For data sheet purposes, the drainsource diode current, labeled IS, is made equal to the
drain current ID.
To verify these current ratings, the D-S diodes were
subjected to two different pulse width surge tests, a one
IS = 2.0 A/div
t = 50 ns/div
o
FIGURE 11-20 - SWITCHING CHARACTERISTICS OF A
TMOS D-S DIODE
MOTOROLA TMOS POWER MOSFET DATA
A-155
•
TABLE 1 -
Switching and Surge Current Characteristics of TMOS D-S Diodes
,-----Switching
1.0.
1 Shot
(A)
(AIl's)
IRM
(A)
(I's)
(I's)
MTM8N10
N·
8.0
6.0
8.5
1.0
0.20
0.20
30
11
MTM15N06
N
15
10
9.0
1.0
0.24
0.29
80
24
Device
IFM
(A)
Surge Current
3001'8
60pps
(A)
Type
(Chan)
Spec 10
Cont
(A)
dildt
trr
ton
MTM15N15
N
15
10
5.0
0.8
0.28
0.05
120
19
MTP1N60
N
1.0
1.0
10
0.3
2.0
0.03
25
6.0
MTP5N06
N
5.0
5.0
3.7
0.24
0.14
0.09
50
12
MTP25N06
N
25
25
10
1.0
0.20
1.0
140
35
second, one-shot pulse and a 300 p,S, 1.8% duty cycle
(60 Hz rep rate) pulse train. The one second test, which
approximates adc test, was run with the DUT bolted to
a four inch square copper heat sink, initially water cooled
and then in free air. The DUT forward current was then
increased until the device was destroyed. The test results
on one product line for the water cooled versus free air
cooled were virtually identical so all subsequent tests were
done in free air. The results of these tests are shown in
the surge current sections of Table 1.
For power dissipation purposes and clamping efficiency
determination, the typical forward characteristics of the
diodes were also taken, as shown in Figure 11-22. These
VF-IF curves were derived from a curve tracer using a
300 '}LS current pulse at 60 PPS; the low duty cycle en-
sured low case temperature readings. For comparison
purposes,' Figure 11-23 describes the forward characteristics of discrete diodes under the same test conditions.
Knowing the voltage drop and current, the diode dissipation can be calculated. For any combination of power
dissipation, the total diode and FET dissipations should
not exceed the rating of the devices. After determining
the switching characteristics and the power handling capability of the diodes, a cost/performance trade-off can be
made. If the switcher is in the development phase, it is
relatively simple to determine the effects of using the internal monolithic diode over a discrete, outboard diode,
i.e. measuring case temperature rise, current and voltage
waveforms, load lines to ensure safe SOA, device and
system efficiency, etc.
Diode Current IF = 0.5 Aldiv. t = 1.0 /LS/div
FIGURE 11-218 -lN4001 STANDARD RECtiFIER
FIGURE 11-21b -1N4935 FAST RECOVERY RECTIFIER
FIGURE 11-21 - COMPARISON OF DISCRETE RECTIFIERS
FOR REVERSE RECOVERY CHARACTERISTICS
MOTOROLA TMOS POWER MOSFET DATA
A-156
Cii
~
~
MTP25N06~/'
100
~
Curve Tracer,
176 High Current Fil
MTP5NO~
C-E DIODE
MJ10007
~/i ~~P1N60
/
10
ftl/,
I
,I
I!MTM-: Metal TO-3
MTP-: Plastic TO-220
TC=25"C
300 itS Pulse. 60 pps
'I
I /1
:1,
/
~
/1/
;
1.0
~'==-;;; 0.5
/l
I
!b
j'/I
':
I
0.1
~,/
/
~
I
~ 5.0
a:
~c
/
MTMBN10(
~
a~
/:..<::
MTP15N15
50 TM15N06
300 itS Pulse. 60 pps
Tektronix Type 576
100
'D Continuous
MTP1N60:
1.0 A
MTP5N06:
MTMBN10:
MTMI5N06:
MTMI5NI5:
MTP25N06:
lOA Darlington C-E Diode
6.0 A Rectifier
12 A Rectifier
5.0 A Fast Recovery Rectifier
12 A Fast Recovery Rectifier
1.0 A Fast Recovery Rectifier
1.0 A Rectifier
5.0 A
B.OA
15 A
15A
25 A
__ L ___ L _l--J
1.0 2.0 3.0 4.0
5.0 6.0
\lsD. D-S DIODE FORWARD ON-VOLTAGE (VOLTS)
o
I
I
I
5.0
6.0
7.0
VF. DIODE FORWARD VOLTAGE (VOLTS)
F1GURE 11-23 - FORWARD CHARACTERISTICS OF
DISCRETE RECTIFIERS
F1GURE 11-22 - FORWARD CHARACTERISTICS OF
POWER MOSFETs D-S DIODES
Thermal Measurements
to the test device. The transistor is operated in the active
region and power dissipation can be adjusted by varying
IE and/or VCE until the junction is at the calibration temperature. This condition is known by monitoring the baseemitter voltage during the time when 1M only is flowing,
with either an oscilloscope or a sample-and-hold circuit.
When VBE is equal to the value obtained in the calibration
procedure, the junction temperature is known. The case
temperature is noted at this time, as well as IE and VCE.
The heating period Is long, so the temperature of the
transistor case is stabilized and the interval of power interruption short, usually 300 JLS, so junction cooling will
be minimal.
The steady state thermal resistance can be easily calculated from the information obtained in the calibration
and power dissipation procedures. The simple formula is
derived from the basic thermal resistance model (Figure
11-25) showing the thermal to electrical analogy for a
semiconductor.
Steady state thermal resistance, junction-to-case, is as
follows:
TJ - TC
RruC = VCE x IE
STEADY STATE THERMAL RESISTANCE
MEASUREMENTS
H is a well known fact that, for reliable operation of a semiconductor, junction temperature is of great concern. All
semiconductor die have a critical temperature which must
not be exceeded or failure will occur. Also, semiconductor
operating life can be either extended or shortened by its
operating temperature.
The usual semiconductor die is enclosed in some type
of package which prevents a direct temperature measurement. Due to the inaccessibility of the die, an indirect
method must be used to determine the junction temperature. A common method is to use a temperature sensitive
electrical parameter. The parameter used can vary, depending upon the type of semiconductor measured.
A basic block diagram for steady-state thermal resistance measurements for bipolar transistors is shown in
Figure 11-24. Th~ forward biased base-emitter-junction is
used as the temperature sensitive parameter. This junction is calibrated at an elevated temperature in the forward
direction, with a low calibration current (1M), and should
be in the linear region above the diode knee. Also, 1M
should not contribute significantly to junction temperature
nor turn-on the transistor; typical values are 2.0 to 10 mA.
The calibration procedure can be performed in a temperature chamber, with the temperature set for a normal
cperating temperature value for the semiconductor being
measured. A typical temperature for a silicon die is around
100°C. The base-emitter forward voltage is measured and
recorded at 1M and at the calibration temperature.
After calibration, a power switching fixture (Figure
11-24) is used to alternately apply and interrupt the power
aT
or
Po
For junction-to-case measurements, sufficient heat
sinking should be provided to prevent excessive junction
temperature. Measurement accuracy is improved with a
large temperature delta between the junction and case.
This delta can be achieved by using an efficient heat sink
permitting a power dissipation (IE VCE) of sufficient magnitude to reach the calibration temperature.
MOTOROLA TMOS POWER MOSFET DATA
A-157
•
Temperatures
TJ, Junction -
_--'----'-.,
R8JC
Po
ROCS
Vee
TA,AmbientPower
Dissipation
ms
FIGURE 11-24 - BASIC BLOCK DIAGRAM OF STEADY STATE
THERMAL RESISTANCE TEST CIRCUIT FOR BIPOLAR
TRANSISTORS
USING TEMPERATURE SENSITIVE PARAMETERS
FOR MEASURING POWER MOSFETs THERMAL
RESISTANCE
FIGURE 11-25 - BASIC THERMAL RESISTANCE MODEL
SHOWING THERMAL TO ELECTRICAL ANALOGY FOR
A SEMICONDUCTOR
measuring the voltage or resistance variations with temperature in an oven, as an example - the device temperature, when powered, can be determined and the thermal resistance can be calculated.
These temperature sensitive parameters (TSP) of a
power MOSFET with their approximate temperature coefficients are listed as follows:
In order to detennine the !hennal resistance of any semiconductor device, an accurate and repeatable method of
measuring the device temperature is required. The linear
temperature dependence of the on-voltage of a forward
biased semiconductor junction has proven to be a reliable
parameter and is consequently used for bipolar transistors
(emitter-base or collect-base junctions), rectifiers, zeners
and thyristors. Because of their intrinsic D-S diode, this
technique is also applicable to TMOS power MOSFETs.
When measuring the thermal resistance of power
MOSFETs, the gate-source threshold voltage or the drainsource on-resistance rDS(on) (:an be used in addition to
the on-voltages of the drain-source diode. Knowing the
temperature characteristics of these parameters - by
Drain-Source Diode"" -2.0 mVrC
Gate-Source Threshold Voltage
=
-2.0 to -6.0 mVrC
Drain-Source On-Resistance"" + 7.0 more when
rDS(on) = 1.0 0
How these TSP can be measured is described in the
simplified schematics of Figure 11-26, with Figure 11-26a
using the D-S diode, Figure 11-26b, the VGS(th) and Figure 11-26c, the rDS(on).
.
VDD
FIGURE 11-26a - DRAIN-SOURCE
DIODE VOLTAGE
FIGURE
11~26-
FIGURE 11-26b - GATE-SOURCE
THRESHOLD VOLTAGE
FIGURE 11-26C - DRAIN-SOURCE
ON RESISTANCE
CIRCUIT CONFIGURATIONS FOR MEASURING TSP
MOTOROLA TMOS POWER MOSFET DATA
A-158
off for the 300 JLS sense time. Drain current is set and
readily controlled by ID Control potentiometer Rl in the
gate-source, closed loop, regulator circuit (op-amp US).
During the sense interval, DUT power is turned off (02
is off, 03 is on) and the sense current IS is applied to the
now forward biased D-S diode by means of turned on
transistors 04 and 05. The resultant D-S diode voltage
can be observed by a scope or measured by the Sample
and Hold circuit consisting of series FET switch 06, buffer
amp U6, sample driver 07 and line synchronized, Delay
Monostable MV gates G2C and G2D. The Delay Control
of this MV allows the sample pulse to be positioned some
time after the start of the Sense time so as to measure
the settled voltage of the D-S diode, ignoring the possible
thermal and/or electrical switching transients on the leading edge of the sense pulse. This delay time is typically
50 JLS to 150 JLS.
Using similar sample-and-hold circuitry, the applied
power (VDS/10 and ID/l0) can be measured. This is accomplished by the respective FETs 08 and 09, sample
driver 010, buffer U3A and U3B and difference connected
op-amps U4A and U4B.
O-S Diode TSP
Generally, the most often used circuit for measuring
RruC of power MOSFETs uses the D-S diode. When
electronic switches S1 and S2are in position 1, the FET
is biased on and the heating power (VDSID) is applied to
the FET for a relatively long period. Then the switches
are thrown to position 2 for a short period of time (sense
time) so that the FET temperature will not change appreciably. Next, the FET is turned off and a constant current
1M (the same sense current at which the TSP was temperature calibrated) is applied to the forward biased D-S
diode. By measuring the forward voltage drop of the diode
and comparing it to the calibration curve, the FET junction
temperature can be asc.ertained. Knowing the input power
and the junction temperature, the thermal resistance can
be calculated. In practice, the input power, either voltage
or current, is varied until the D-S diode drop is equal to
a calibration pOint, thus simplifying the test procedure by
not having to generate a complete calibration curve.
Gate-Source Threshold Voltage TSP
This thermal resistance test circuit is extremely useful
for measuring RruC of GEMFETs since this device has
no parasitic diode. As in the D-S diode tester, heating
power is applied to the DUT when switch S1 is in position
1. Then, switch S1 is briefly thrown to position 2, applying
the sense current to the FET (lD at VGS(th» and the gatesource threshold voltage is measured. Input power (VDSIS) is varied to make VGS(th) equal to the elevated temperature, calibration reading resulting in a known junction
temperature and thus RruC.
Drain-Source On-Resistance
This circuit is conceptually similar to the D-S diode
tester. However, now when the switch is in position 2
(Sense Time), a positive constant current 1M and + 15 V
gate bias are applied to the device, turning it on. 1M should
be of a value to produce about 0.5 V VDS. The voltage
VDS measured (VM) is related to rDS(on) by:
rDS(on) = VM"M
Thermal Test Fixtures
D-S O;OOE THERMAL FIXTURE
RruC
The D-S diode Thermal Fixture, shown in Figure
11-27,is partially an implementation of the simplified circuit of Figure 11-26. It also contains circuitry for measuring
transient thermal resistance r(t) and the analogue circuits
for reading out the drain-source diode forward voltage and
input power (VDS and ID). Thermal resistance is measured when the Mode Selector Switch S1 is in position 1,
RruC. System timing is line synchronized and is derived
from the Schmitt trigger (gates G1A and GIS) shaping
circuit clocking the 300 JLS Sense Time Monostable Multivibrator (gatesG2A and G2B). Thus, the power MOSFET
DUT is turned on via the Drain Switch circuit (cascade
transistor 01 and 02) and unclamped gate transistor 03
for 8.0 ms (full-wave rectified line rate minus 300 /-Ls) and
Transient Thermal Resistance r(t)
Transient thermal resistance, r(t), is measured when
switch S1 is in position 2. Now the system timing is derived
by the 22 second astable MV (gates G1 C and G1 D) which
turns the DUT on and off for about 11 seconds each.
During the off time, cooling cycle, the voltage of the D-S
diode can be measured at any selected period of time.
This is accomplished by selecting the various resistorcapacitor timing components of the Delay MV, thus positioning the sample pulse accordingly. The six switchable
capacitors, by means of Selector Switch S2, will produce
the six time decades of control (100 JLS to 10 s) and the
three resistors (switch S3), the multipliers within the decade, e.g., 0.2, 0.5 and 1.0.
GATE THRESHOLD VOLTAGE VGS{th) THERMAL
FIXTURE
The Gate-Source Threshold Voltage (VGS(th» Thermal
Fixture, Figure 11-28, was specifically designed for measuring the thermal resistance of GEMFETs as this device
does not have a D-S diode. Since it detects temperature
induced variations in the gate-source threshold voltage,
it can also be used for power MOSFETs. Its line synchronization and current regulator loop around the gate
and source make it very similar to D-S Diode Thermal
Fixture. The major difference is the setting of the two
different drain currents (or source currents), the power
current, IS, and sense current 1M. This is accomplished
by switching two different reference voltages to the positive input of the loop regulator op-amp U3. As in any
regulator loop of this type, the voltage at the negative
input of the op-amp, as derived from the voltage drop
across the source sense resistor R1, will be driven by the
closed loop to a value equal to the reference input. Thus,
if a heating current, IS, of say 10 A is required, the reference voltage should be 3.0 V (10 A x 0.3 0). If a sense
currentiM of 10 mA is specified, VREF should be 3.0 mV.
Although most power MOSFETs are specified for a 1.0
MOTOROLA TMOS POWER MOSFET DATA
A-159
II
•
'0'
Thermal
ModeSei
SW S'A
.'1
2
TrladF90,X
o---/J
'4Y
'20Y
0---/
"",,,,MY
C1 130 pF
C2 0.001",
C3 a.01F
C4 0.1,!1f
30V
+
20M
MC14001
U1
22M
C5 1.0,.F
CO C2IiO~.20V
22 Sec MV
FIGURE 11-'Z'! - POWER MOSFET THERMAL FIXTURE
mA drain current at VGS~h)' the 10 mA level was chosen
for measurement simpliCity; in reality, there is negligible
difference in the test results at either currents.
As in the D-S Diode Fixture, the system timing is line
synchronized by Schmitt Trigger U1A and U1B, whose
complementary outputs are used to clock the 370·!JS
sense MV (U1C and U1D), and the variable delay MV
(U1E and U1F)for the sample pulse. This type of line
synchronization offers several advantages: at high power
heating drain currents, It simplifies the oscilloscope viewing, particularly when the external power supplies are not
well regulated, and it is easily derived from one hex gate
CMOS IC MC14572.
During the 370 !JS sense time, the output of U1D is
high; thus, PNP Darlington, 01 is Off and the reference
voltage is determined solely by the voltage divider R2 (the
10 mA Set Control), R4 and R5. To set R2, switchS2 is
opened and the drain current is monitored for the required
10mA.
When U1 0 goes low for the approximate 8.0 ms power
cycle, 01 is tumed on, placing R3, the IS control, into the
reference voltage circuit. Consequently, the reference
voltage will be switched from the 3.0 mV sense voltage
to the IS control voltage.
During the sense time the magnitude of the gate-source
voltage, can be monitored with a scope or read out with
the sample-and-hold circuit consisting of FET series
switch 03, buffer amps U2A and U2B, sample driver 02
and delay MV U1E and U1F. Power to the OUT is then
varied, either VDS or 10, to make VGS(th) equal to the
calibrated value; thus, TJ and PIN are known and RruC
can be calculated (RruC = (TJp- TC).
IN
POWER MOSFET MEASUREMENT
TECHNIQUES FOR THE CURVE TRACER
The curve tracer is an extremely useful tool in measuring the pertinent power MOSFET parameters. The
MOTOROLA TMOS POWER MOSFET DATA
A-160
techniques are not dissimilar to those used for measuring
bipolar transistors. Table 2 lists the equivalent parameters
between the two.
No FET parameters are measured in an open gate
condition. To prevent damage to the part, the gate
should always be terminated with a resistor (typically RGS
= 1.0 MO) or a short for the appropriate test condition.
measured at a specific drain current, 10; Gate shorted to
the source.
lOSS, Drain-Current With Zero Gate Voltage - Drain
leakage current at a specified drain-source voltage,
VOSS; Gate shorted to source.
DEFINITIONS OF ELECTRICAL CHARACTERISTICS
IGSS, Gate Body Leakage Current - Gate leakage current for a specified gate-source voltage; Drain shorted to
source.
Off Characteristics
On Characteristics
V(BR)DSS, Drain-Source Breakdown Voltage - Maximum sustaining voltage between the drain and source,
VGS(th), Gate Threshold Voltage - Value of the gate
voltage that must be applied to initiate conduction. It has
+15V
Voo
U2
(V,)MC1458
U2
(V,)MC1458
VGS(th)
1.0 k
3.0k
100 k
+15V
U3
(V,)MCl458
StH
lN914
15 k
+15V
150 k
Q2
Rl
0.30
lOW
lN914
+15V
R4
220 pF
470 k
o.oOll'F
580
0.011'F
1
100 k
R2
220 k
10mA
Set
Ul
MC14572
Triad
F90X
lOOI'F
30 V
FIGURE 11-28 - POWER MOSFET VGS(th)
THERMAL FIXTURE
MOTOROLA TMOS POWER MOSFET DATA
A-161
II
•
TABLE 2
Transistor
Collector
Emitter
Base
V(BR)CES
VCBO
IC
ICES
lEBO
VBE(on)
VCE(sat)
Cib
Cob
hFE
VCE(sat)
RCE(sat) = --ICVEC
4 -
When switching from one test range to another,
voltage settings should be reduced to zero to
avoid generation of potentially destructive voltage
surges during switching.
The test set-ups to follow are. for the Motorola
MTP12Nl0 Power MOSFET, which is a 12 Amp, 100 volt
N-Channel device in the TO-220 package.
MOSFET
Drain
Source
Gate
V(BR)OSS
VOGR
V(BR)OSS - Also known as BVOSS. Specified at an 10
of 5.0 mA at TC = 25°C.
10
lOSS
IGSS
VGS(th)
VOS(on)
Ciss
Coss
9fs
Test set-up and Source Trace (See Figure 11-29).
1 - Set maximum peak volts on 350, Series Resistors
on 3.0 k.
2 - Polarity to NPN, Mode to Norm.
3 - Vertical on 1.0 mAlDivision, Display Offset on 0,
Horizontal on 20 volts/Division.
4 - Step Generator is not used for this measurement.
5 - Emitter grounded; Base Term on short.
6 - With device in socket, adjust variable collector
supply until trace breaks and reaches 5.0 mA.
VOS(on)
rOS(on) = -1-0VSO
a negative temperature coefficient of about -6.7 mVfC.
VOS(on), Drain-Source On-Voltage - Voltage drop measured between the drain and source at a specified drain
current and specified gate-source voltage.
lOSS - Specified at 85% of rated V(BR)OSS. Maximum
allowable leakage is 250 pA at TC = 25°C.
Test Set-Up
Set-up is the same as V(BR)oss/excepl:
1 - Set Mode Switch to Leakage.
2 - Set Vertical to 50 pAlOivision
3 - Adjust variable collector supply to 85 volls and
read leakage. If Leakage reads 0, adjust Vertical
to desired level (This increases sensitivity on low
leakage devices).
rOS(on), Drain-Source On-Resistance - Value of the resistance measured between drain and source at a specified drain current and a specified gate-source voltage. It
is defined as:
VOS(on)
rDS(on) = -1-09fs, Forward Transconductance - The MOSFET gain
parameter. It is the ratio between the change in drain
current, 10, for a given change in gate-source voltage, at
a specified drain-source voltage and specified drain current. In algebraic form:
aiD
9fs = aVGS
IGSS - Specified at VGS = ± 20 volls, maximum allowable leakage is 500 nA at TC - 25°C.
Test Set-Up
1 - Drain and gate connections on socket are reversed so drain is shorted to source.
2 - Set maximum peak volls to 75, and Series Resistors to 140 O.
3 - Polarity to NPN and Mode Switch to Leakage.
4 - Vertical on 50 nAlOivision, Display Offset on 0,
Horizontal on 2.0 Volls/Oivision.
5 - Step generator is not used for this measurement.
6 - Emitter grounded; Base Term on short.
7 - With device in socket, adjust variable collector
supply to 20 volls and read Leakage. If leakage
reads 0, adjust vertical to desired level.
VSO, Diode Forward On-Voltage - The forward voltage
drop between the source and drain at a specified S-O
diode current IS.
Curve Tracer Measurements
The following explains how to measure the parameters
listed above on a curve tracer. Although the set-up charts
correspond to the Tektronic Type 576 Curve Tracer, the
same measurements can be performed on a Tektronix
Type 577 Curve Tracer.
Before applying power to MOSFETs on a curve tracer,
the following precautions should be observed:
1 - Test stations should be protected from ElectroStatic Discharge.
2 - When inserting parts into a curve tracer, voltage
should not be applied until all terminals are solidly
connected in the socket.
3 - A resistor of 100 0 should be connected in series
with the gate to damp spurious oscillations that
can occur on the tracer.
VGS(th) - Specified at 1.0 mA with limits of 2.0 volts
minimum and 4.5 volts maximum at TC = 25°C.
(Figure 11-30)
1 - Set Maximum Peak Volls to IS, Series Resistors
to 0.3 O.
2 - Polarity to NPN, Mode Switch on Normal.
3 - Vertical on 0.2 mAlOivision, Display Offset on 0,
Horizontal on 2.0 Volts/Division.
MOTOROLA TMOS POWER MOSFET DATA
A-162
TYPE 578
•
CURVE TRACER
Not Used
For
V(BR)DSS
b
~.
.~
.
-
Gr
.
c@
a@
Sl@
c@
@
@
a@
e@
@
@
..-
u, ...
o
000
0
FIGURE 11-29 - TEST SET-UP CHART TYPE 576 FOR MEASURING POWER MOSFET PARAMETERS
MOTOROLA TMOS POWER MOSFET DATA
A-163
I
4 -
Step Generator; number of steps = 1, Offset Mult
on 0, Offset on Aid, Steps Button in, Step Family
on Single, Rate on Norm, Step offset amplitude
= 1.0 V.
5 6 -
Emitter grounded; Base Term on Step GeneratOr.
With device in socket, adjust variable collector
supply to 10 volts, then adjust Offset Mult until
trace reaches 1.0 mA. Read VGS(th) directly from
Offset Mult Control.
.
, ~,
FIGURE 11-31 - CURVE TRACER PRESENTATION FOR VOS(on)
r
4 -
Step Generator; number of steps = 10, Offset on
zero, Pulsed Steps on 300 /Ls, Step Family on
Rep, rate on Norm, Step Offset Amplitude -1.0 V.
5 6 7 -
Emitter grounded; Base Term on Step Gen.
Readout ilium turned fully clockwise.
With device in socket, adjust variable collector
supply until trace with steps closest to 6.0 Amps
reaches 15 volts. 9fs is the number of divisions
between those two steps, as designated by the
right hand corner of the screen labeled gm per
Division.
FIGURE 11-30 - CURVE TRACER PRESENTATION
FOR VGS(lh) - MTP12N10
VDS(on) - Specified at VGS = 10 volts and at one half
rated ID. rDS(on) is calculated from measured VDS(on)
value.
(Figure 11-33)
Set Maximum Peak Volts on 15, Series Resistors
on 0.3 O.
2 -
Polarity on NPN, Mode to Norm.
3 -
Vertical on 1.0 AlDivision, Display Offset on 0,
Horizontal on 0.5 Volts/Division.
4 -
Step Generator; number of steps - 10, Offset on
zero, pulsed steps on 300 pS, Step Family on Rep,
rate on Norm, Step OffseVAmplitude = 1.0 V.
Emitter grounded; Base Term on Step Gen.
5 6 -
9fs -
1
/
/
V
With device in socket, adjust variable collector
supply until the top left dot on trace reaches 6.0
Amps then read VDS(on) off horizontal scale.
J
/1
'l
Specified at one half rated ID at VDS = 15 volts.
(Figure 11-32)
1 -
Set Maximum Peak Volts on 15 and Series Resistors on 0.3 O.
-
(Figure 11-31)
1 -
Specified at rated ID with VGS = O.
VSD -
Polarity on NPN, Mode to Norm.
3 -
Vertical on 1.0 Amp/Division/Display Offset on
zero, Horizontal on 2.0 Volts/Division.
,/
'1
-,'
r"\
A
l
l
9FS
~
./
~
Maximum Peak Volts on 15, Series Resistors on
/I
..,.,
0.30.
2 -
/-
FIGURE 11-32 - CURVE TRACER FOR 9fs
MOTOROLA TMOS POWER MOSFET DATA
A-164
2 -
Polarity on PNP, Mode on Norm.
3 -
Vertical on 2.0 Amps/Division, Display Offset on
0, Horizontal on 0.5 Volts/Division.
4 -
Push Display Invert in.
5 -
Step Generator is not used for this measurement.
6 -
With device in socket, adjust variable collector
supply until trace reaches 12 Amps and read voltage.
Hard tooling is committed. Initially, or months, or even
years later, the equipment begins to fail as it comes off
the production line. Perhaps with less fortune, the equipment fails in the field. The reason, which is at first elusive,
boils down to the equipment requiring a combination of
non-reproducible characteristics in one or more of the key
components.
All too many people have been adversely affected by
just this kind of scenario. Yet, minimizing the risks associated with component selection is considerably easier
than might be expected. Guidelines for minimizing the
risks, with respect to power MOSFETs, are presented
here. In addition to general guidelines, a straightforward
method for determining safe operating safety margin is
highlighted. The discussion begins with statistical concepts.
Semiconductor components have three statistical populations which are relevant to the equipment designer.
They are:
I
1) Wafer lot
II
2) Wafer
3) Individual component
A wafer lot is a group of wafers which are processed
together. A typical example for switching power supply
output transistors is fifty wafers per lot and 100 transistors
per wafer, for a total of roughly 5,000 transistors per wafer
lot. The statistical considerations arise from the way semiconductors are batch processed in wafer lots. The cookie
analogy is a helpful illustration.
Suppose a baker has three groups of raw cookies. Each
group is sufficiently large to fully use available space in
the baking oven. The three groups are therefore baked
sequentially. The first group is slightly overdone and relatively dark. The second group comes out slightly underdone and very light. The third group turns out medium.
Lightness or darkness of the individual cookies will vary
somewhat within each group, but probably not by very
much. Variations in color are much more dependent upon
which group a cookie was baked in than which individual
cookie was chosen from a given group. A sample of cookies chosen from anyone group will poorly predict the
variations expected from the baking process.
Semiconductor characteristics vary in much the same
way. Many characteristics are far more dependent upon
the wafer lot in which a device is processed than upon
which individual device is chosen from a given wafer lot.
An illustration is shown in Figure 11-34.
Population densities for transistors in two different wafer
lots, curves A and A', are plotted on the same scale as
the wafer lot distribution for the same parameter. It is clear
that a sample selected from wafer lot A will poorly predict
the performance expected from transistors in lot A' . These
curves are typical of the way many transistor parameters
vary. They are also descriptive of batch processed components in general.
From an equipment design point of view, these characteristics have serious implications. The validity of a 100
piece design sample becomes questionable, when the
possibility that all 100 devices may be from the same wafer
lot is considered. In fact, the validity of using 100 devices,
I
I
'/
.....".
FIGURE 11-33 -
CURVE TRACER PRESENTATION FOR vSD
Additional Reference Material: Measurement Concepts
From Tektronix.
Characterizing Power MOSFETs For
Unspecified Parameters
Although many modern data sheets characterize power
MOSFETs specifically for operation in power conversion
equipment, it is not practical to guarantee operation for
every conceivable set of operating conditions: Therefore,
equipment design frequently requires the use of power
MOSFETs in conditions for which they are not specified.
To compensate for the unknowns, use of a relatively large
design sample is common practice. A relatively large sample gives a feeling of statistical security. All too often, the
sample comes from transistors purchased in a single
group, with predictably unfortunate results. A common
scenario goes something like this.
DESIGN SCENARIO
The designer orders as many as 100 of each of the key
components to try in this equipment. He may simply verify
that the equipment performs satisfactorily, or he may attempt to do a wOrst case analysis based upon parametric
variations. Either way, it is believed that the 100 pieces
constitute a statistically conservative sample.
With performance and worst case analysis indicating
satisfactory performance, the design is finalized. Preproduction begins with components from the initial 100
piece order. Except for routine debugging, all goes well.
MOTOROLA TMOS POWER MOSFET DATA
A-16S
transistors from a number of different date codes. Here
are some suggestions.
1) Place several small orders sequentially in time.
2) Order from several different distributors, preferably
in more than one geographic location. Five 20 piece
shipments from five different distributors will cost
more than a single shipment of 100 pieces, but the
benefits dwarf the added expense.
3) Ask the manufacturer for assistance.
As a practical matter, it will generally be rather difficult
to obtain a sample with more than four or five wafer lots
represented. Since this is a relatively small sample, a
working knowledge of parameter variations is very helpful.
This is particularly true of Safe Operating Area (SOA)
which is presented here as a special case.
A
Safe Operating Area
Safe Operating Area is probably the most troublesome
of the unspecified parameters. Operation in unspecified
regions is difficult to avoid since it is not practical to guarantee the transistor for all conditions in which it can be
used. Usually, unspecified operation is related to the fact
that SOA curves are drawn for given circuit configurations
and _bias conditions. Operation in conditions other than
specified is not necessarily guaranteed. Therefore, it is
often easy to operate fully within the boundaries of an
SOA curve, yet be in an unspecified region because of
differences in circuit configuration or bias.
At times _like this, a straightforward test can be very
effective~ The steps are as follows:
1. Starting with the equipment in which the transistor
will operate, or a suitable test Circuit, raise the input
bus voltage to 1.25 x its worst case value. Test the
equipment for survivability. If any transistors in the
design sample fail, there is notenough safety margin. Future trouble is almost guaranteed. If none fail,
proceed to Step 2.
2. Raise the bus voltage to 1.33 x its worst case value.
Repeat the testing. If more than 50% of the sample
transistors survive, then SOA safety margin is probably more than adequate.
3. Recognize that worst case SOA stress, in switching
power conversion systems, will often occur at conditions other than full load and high temperature. It
is important to either choose conditions which maximize transistor stress, or cycle the equipment
through its mini-max load and temperature ranges.
Successful results will depend largely on attention
to test conditions. An example is noteworthy.
SOA stress is often maximized in the first or last
switching cycle, when the equipment is turned-on or
turned-off. Load lines for the first or last cycle often
have-larger excursions than steady state full load
operation. A single excursion to a high voltage is
usually more hazardous than operating at a lower
voltage on a continuous basis.
These steps are very effective at eliminating unwanted
surprises, provided transistors from at least three wafer
lots are included in the test. They form the same basic
FIGURE 11-34 - EXAMPLE PROBABILITY DISTRIBUTIONS
which are purchased all in one group, is more than questionable. For those parameters which are highly wafer lot
dependent, such a sample is, in effect, not a 100 piece
sample, but a one piece sample, since there is a very
high probability that only one wafer lot is represented.
The unfortunate circumstances in the opening scenario
are a direct result of a one piece wafer lot sample. The
one piece sample does not buy much statistical insurance.
Surprises are likely, since a false sense of security is
generated when it is believed that 100 physical units in a
design sample represent a 100 piece statistical sample.
The results are predictable and unpleasant for all concerned.
DESIGN SAMPLES
A key factor in top notch design work is obtaining statistically relevant samples of key components. With re"
spect to power transistors, this means including a number
of different wafer lots in the design sample. This task can
be seemingly difficult since, in general, the number of
wafer lots in a given sample is not known. However, the
minimum number of wafer lots in a sample can be determined by assuming that each date code consists of separate wafer lots. There may be many wafer lots in a date
code, but usually two date codes will not contain transistors from the same wafer lot.
Often, transistors have two date codes, one which corresponds to the time period in which they are tested and
the other which denotes the time period in which they
were assembled. The assembly -date code is by far the
more valuable of the two. As an example, Motorola
TO-204 transistors have a three-digit assembly date code
stamped on the ear. The first digit is coded to the year.
The second and third digits correspond to workweek. A
transistor built in the last workweek of 1982 would read
252.
Sample selection, then; hinges on being able to obtain
MOTOROLA TMOS POWER MOSFET DATA
A-166
procedure that is used to generate data sheet SOA
curves.
II
TABLE 2
General Guidelines
It is often of interest to obtain reasonable limits for parameters other than SOA. A discussion of expected variations is a good place to start.
Variations within a given sample are obvious. Of interest
here is the expected worst case variations over the life of
a multi-year production run. Table 2 gives an indication
of what can generally be expected for various parameters.
Measured mean values come from data taken on transistors in the design sample. They are normalized to 1.0
for ease of comparison. It is important to note that Table
2 applies only if at least three wafer lots are included in
the sample data.
Although some of the resulting tolerances may seem
rather large, they are realistic when production runs spanning a number of years are considered. It is far better to
face these numbers up front, than be surprised downstream with equipment failures.
Parameter
Leakage Currents
Breakdown Voltages
Gain
Turn·On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Crossover Time
Gate Threshold Voltage
rOS(on)
VOS(on)
Ciss
Coss
Crss
Measured
Mean
Value
1.0
1.0
1.0
1.0.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Expected
Min
10.3
0.7
0.5
0.7
0.5
0.5
0.5
0.5
0.6
0.5
0.5
0.7
0.5
0.6
Expected
Max
10+ 3
1.5
4.0
1.5
2.0
2.0
2.0
2.0
1.5
2.0
2.0
1.5
2.0
1.6
duced by straightforward improvements in the selection
of design samples. Risks are further minimized with realistic estimation of worst case parameter variations, and
the proper choice of test conditions for maximum stress.
Conclusion
The risk of equipment failure can be significantly ra-
MOTOROLA TMOS POWER MOSFET DATA
A-167
..
Chapter 12: Reliability and Quality
!
A failure occurs when the leakage achieves such a high
level that the power dissipation causes the device to go
into a thermal runaway.
The leakage current of a stable device should remain
relatively constant, or increase slightly over the period of
the test, typically 1000 hours.
Typical conditions:
TA = 125·C on product ;;;. 500 V VOS
TA = 150·C on product .;; 500 V VOS
VOS = 80% of maximum rating
VGS = 0 (shorted)
Introduction
Quality and reliability are two essential elements in order for a semiconductor company to be successful in the
marketplace today. Quality and reliability are interrelated
because reliability is quality extended over the expected
life of the product.
Quality is: The assurance that a product will fulfill customers' expectations.
Reliability is: The probability that a product will perform
its intended function satisfactorily for a prescribed life under certain stated conditions.
In today's market, with customer expectations for better
and better quality and ever increasing reliability, the old
standards of quality and reliability are not acceptable.
For a manufacturer to remain in the semiconductor business at all, his product must inherently meet and exceed
~asic quality/reliability standards. Motorola, as the world's
largest supplier of semiconductors, has successfully
achieved inherent reliability that meets the most strenuous
applications and the most adverse environments. Motorola's TMOS products are no exception.
The quality and reliability of Motorola TMOS products
are achieved with a four step program:
1. Thoroughly tested designs and materials.
2. Stringent in-process controls and inspections.
3. Process average testing along with 100% quality
assurance redundant testing.
4. Reliability verifications through audits and reliability
studies.
These steps are detailed in the following pages to provide the reader with a greater insight into the quality and
reliability capabilities of Motorola TMOS products.
INTERMITTENT OPERATING LIFE:
(IOL OR POWER CYCLING) PER MIL-STD-750,
METHOD 1037.
The purpose of the IOL test is to determine the integrity
of the chip and/or package assembly to cycling on (device
thermally heated due to power dissipation) and cycling off
(device thermally cooling due to removal of power applied)
as is normally experienced in a "real world" environment.
OC power is applied to the device until the desired
function temperature Is reached. The power is then
switched off, and forced air cooling applied until the junction temperature decreases to ambient temperature.
~TJ = ~TC + RruCPd
~TJ = 1000C
(typically, which is an accelerated condition)
Motorola TMOS products are subjected to a series of
extensive reliability tests to verify conformance. These
tests are designed to accelerate the failure mechanisms
encountered in practical applications, thereby ensuring
satisfactory reliable performance in "real world" applications.
The follOWing describes the reliability tests that are routinely performed on Motorola's TMOS devices.
~TC = TC HIGH - TC LOW
The sequence is repeated for the specified number of
cycles. The temperature excursion is carefully maintained
for repeatability of results.
The Intermittent Operating Life test indicates the degree
of thermal fatigue of the die bond interface between the
chip and the mounting surface and between the chip and
the wire bond interface.
For TMOS devices, parameters used to monitor performance are thermal resistance, threshold voltage, onresistance, gate-source leakage current and drain-source
leakage current.
A failure occurs when thermal fatigue causes the thermal resistance or the on-resistance to increase beyond
the maximum value specified by the manufacturer's data
sheets.
HIGH TEMPERATURE REVERSE BIAS (HTRB) PER
MIL-STD-750, METHOD 1039:
The HTRB test is designed to check the stability of the
device under "reverse bias" conditions of the main blocking junction at high temperature, as a function of time.
The stability and leakage current over a period of time,
for a given temperature and voltage applied across the
junction, is indicative of junction surface stability. It is
therefore a good indicator of device quality and reliability.
For TMOS devices, voltage is applied between drain
and source, and lOSS is monitored. The gate is shorted
to the source, to prevent damage due to buildup of
charges on the gate.
TEMPERATURE CYCLE (TC) PER MIL-STD-750,
METHOD 1051:
The purpose of the Temperature Cycle Test is to determine the resistance of the device to high and low temperature excursions in an air medium and the effects of
cycling at these extremes.
The test is performed by placing the devices alternatively in separate chambers set for high and low temperatures. The air temperature of each chamber is evenly
maintained by means of circulation. The chambers have
sufficient thermal capacity so that the specified ambient
is reached after the devices have been transferred to the
chamber.
Reliability Tests
MOTOROLA TMOS POWER MOSFETOATA
A-168
WAFER PROCESS INSPECTION POINTS
TMOS
INCOMING WAFER/MASK INSPECTIONS
INCOMING
WAFER
OXIDATION
RESIST THICKNESS
P+
PHOTO RESIST
P+
DIFFUSION
PINHOLE
DENSITY
SOURCE
DIFFUSION
GATE
OXIDE
ADIIACI·
INSPECTIONS
lSTL-_-----'
PRE-OHMIC
P/R
1\
ACIIADI INSPECTIONS·
OXIDE
2ND
PRE·OHMIC
P/R
FRONT METAL
-DENOTES
Q;A. INSPECTION
POINT
~
·AFTER DEVELOP INSPJ
AFTER CLEAN INSP.
~
__________________--J
VISUAL,
TO FINAL OUTGOING
ASSEMBLY
UNIT
PROBE
OTHER GENERAL INSPECTIONS
AIR QUALITY - PARTICLE COUNTS
WATER PURITY - RESISTIVITY MEASUREMENTS
MOTOROLA TMOS POWER MOSFET DATA
A-169
BACK
LAP
&
BACK
METAL
•
IPQA INSPECTION POINTS
POWER METAL TMOS
100% SAW
THRU
Q.A. VISUAL
DIE BOND
Q.A. DIE BOND VISUAL
PROCESS CONTROL CHARTS
WIRE BOND
Q.A. WIRE BOND VISUAL
& DESTRUCT WIRE PULL
WELD
Q.A. DIE COAT VISUAL
DIE COAT
Q.A. VISUAL GATE AND
NON-DESTRUCT WIRE PULL
Q.A. FINE & GROSS LEAK
FINAL TEST (100% de
ELECT. TEST)
SOLDER DIP
Q.A. SOLDER VISUAL
MARK
CUSTOMER
OFI
SHIPPING
Q.A.
OUTGOING
IPOA INSPECTION POINTS FOR PLASTIC POWER TMOS
DIE BOND
100% SAW
THRU
MARKING
.----,
Q.A. VISUAL
SOLDERABILITY
WIRE"
BOND
DIE COAT
Q.A. VISUAL
Q.A. VISUAL
100% de AFTER 100%
TEMPERATURE CYCLE
TOQ.A.
CUSTOMER
Q.A.
OUTGOING
SHIPPING
*100",1, NON-DESTRUCT WIRE PULL AFTER WIRE BOND
MOTOROLA TMOS POWER MOSFET DATA
A-170
OFI
tained for a minimum of 24 hours (reliability evaluations
have demonstrated conclusively that particular epoxies
are very near hermetic). The devices are then removed
and air dried for a minimum of four hours and a maximum
of 24 hours before data is recorded.
Parameters that are usually monitored are leakage currents and voltage.
Each cycle consists of an exposure to one extreme
temperature for 15 minutes minimum, then immediately
transferred to the other extreme temperature for 15 minutes minimum; this completes one cycle. Note that it is
an immediate transfer between temperature extremes and
thereby stressing the device greater than non-immediate
transfer.
Typical Extremes
(Metal) TO-204 Package device: - 65/ + 200°C
(Plastic) TO-220 Package device: - 65/ + 150°C
The number of cycles can be correlated to the severity
of the expected environment. It is commonly accepted in
the industry that ten cycles is sufficient to determine the
quality of the device.
HIGH TEMPERATURE GATE BIAS (HTGB):
PER MIL-STD-750, METHOD 1039:
The HTGB test is designed to electrically stress the gate
oxide at the maximum rated dc bias voltage at high temperature. The test is designed to detect for drift caused
by random oxide defects and ionic oxide contamination.
For TMOS devices, a voltage of ± 20 V is applied between the gate-source. The drain is shorted to the source
which is at ground potential. Typical temperature, TA =
150°C, time = 168 hours ;;. t .;;; 1000 hours.
Any oxide defects present will lead to early device failure in the form of IGSS short.
Typical Cycles for ,Evaluations and Audits:
TO-204 and TO-220 devices: Minimum 100 cycles
TO-204 and TO-220 devices: Maximum 1000 cycles
Temperature cycling identifies any excessive strains set
up between materials within the device due to differences
in coefficients of expansion.
A failure occurs when there is a change in the device's
parameters beyond specified levels, or when a device
checks electrically as "open" or "short".
HIGH TEMPERATURE STORAGE LIFE (HTSL) TEST:
PER MIL-5TD-750, METHOD 1032.
The HTSL test is designed to indicate the stability of
the devices, their potential to withstand high temperatures
and the internal manufacturing integrity of the package.
Although devices are not exposed to such extreme high
temperatures in the field, the purpose of this test is to
accelerate any failure mechanisms that could occur during
long periods at storage temperatures.
The test is performed by placing the devices in a mesh
basket, then placed in a high temperature chamber at a
controlled ambient temperature, as a function of time. Typical conditions:
TA = 150°C on Plastic package
TA = 200·C on Metal package
t = 1000 hours
THERMAL SHOCK (TC) PER MIL-STD-750,
METHOD 1056:
The purpose of this test is to determine the resistance
of the device to sudden exposure to extreme changes in
temperature.
The test is performed by placing the devices in a mesh
basket, then alternatively immerse in baths of liquid (maintained at - 55°C and + 150°C). They are kept for thirty
seconds in each bath and immediately transferred to the
alternate bath.
This test produces sudden heating and cooling of the
device, and produces unusual stresses due to the short
term temperature gradients that are set up. It is cornmonly
accepted in the industry that five cycles is sufficient to
determine the quality qf the device.
A failure occurs when there is a change in the device's
parameters beyond specified levels, or when a device
checks electrically as "open" or "short".
HIGH HUMIDITY HIGH TEMPERATURE REVERSE
BIAS (H3TRB) TEST: PER MIL-STD-750, METHOD
1039.
The H3TRB test is designed to determine the resistance
of component parts and constituent materials to the combined deteriorative effects of prolonged operation in a high
temperature/high humidity environment. This test only applies to nonhermetic devices.
Humidity has been a traditional enemy of semiconductors, particularly plastic packaged devices. Most moisture
related degradations result, directly or indirectly, from penetration of moisture vapor through passivating materials,
and from surface corrosion. At Motorola, this former problem has been effectively addressed and controlled
through use of junction "passivation" process, die coating,
and proper selection of package materials.
For TMOS devices, voltage is applied between drain
and source. The gate is shorted to the source, to prevent
damage due to buildup of charges on the gate. The test
is performed in a chamber at 85 percent relative humidity
and 85°C. Typical time = 168 hours;;. t .;;; 1000 hours.
PRESSURE COOKER TEST (OR AUTOCLAVE
TEST):
The purpose of the "pressure cooker" test is to determine the resistance of the device to moisture by subjecting
it to relatively high steam pressure levels. This is only
performed on nonhermetic packages (I.e., plastic/epoxy
encapsulated devices), and not on hermetic packages
(I.e., metal can devices).
A "pressure cooker" providing a pressure of 15 pounds
per square inch over atmosphere is used (1 atmosphere
= 14.7 psig). A wire mesh tray is constructed inside to
keep the devices approximately two inches above the
surface of deionized water and to prevent condensed
water from collecting on them.
After achieving the working value, the pressure is main-
MOTOROLA TMOS POWER MOSFET DATA
A-171
1.1
vices (plastic and metal TMOS) with a total of three
failures, which equates to equivalent device hours at 90°C
of 1.8 x 108 or 20 fits.' In terms of customer expectation,
this relates to a mean (average) time between failure of
5,723.4 years.
High Temperature Gate Bias (HTGB) checks the stability of the device under "gate bias" forward conditions
at accelerated high temperature, as a function of time.
This test is performed to electrically stress the gate oxide
to detect for drift caused by random oxide defect. This
failure mechanism appears in the infant and random
zones of the reliability "bath tub curve" at a very low rate
of defect. Motorola has processed 812 devices. (plastic
and metal TMOS) with a total of one failure, which equates
to equivalent device hours at 90°C of 2.4 x 107 or 68 fits.
In terms of customer expectation, this relates to a mean
(average) time between failures of 1,717.0 years..
Intermittent Operating Life (IOL) is an excellent accelerated stress test to determine the. integrity of the chip
and/or package assembly to cycling on (device thermally
heated due to power dissipation) and cycling off (device
thermally cooling due to removal of power applied). This
test is perhaps the most important test of all, along with
simulating what is normally experienced in a "real world"
environment. IOL exercises die bond, wire bonds, turning
on the device, turning off the device, relates the device
performance, and verifying the thermal expansion of all
materials are compatible. Motorola performs exten~ive
IOL testing as a continual process control monitor that
best relates to the "device system"" as a whole. Motorola
also performs extensive analysis and comparison of delta
junction temperatures. Motorola has determined that to
effectively stress the device a delta Tj of 100°C is necessary therefore, far exceeding many customers' application and beller determine the reliability modeling of the
device. Motorola has processed 6,429 devices (plastic
and metal TMOS) with a total of 2 failures, which equates
to actual device cycles of 2.3 x 107 or 115 fits. In terms
of customer expectation, this relates to a mean (average)
time between failures of 1,007.3 years.
Temperature Cycling (TC) is also an excellent stress
testlo determine the resistance of the device to high and
low temperature excursions in an air medium. Where IOL
electrically stresses the "device system" from internally,
temperature cycle stresses the "device system" thermally
from external environment conditions. Motorola has processed 14,149 devices (plastic and metal TMOS) .with a
total of zero failures, which equates to actual device cycles
of 9.4 x 105 or 800 fits. In.terms of customer expectation,
this mean (average) time between failures of 143.1 years.
High Temperature Storage Life (HTSL), High Humidity
Temperature Reverse Bias (H3TRB), Thermal Shock (TC)
and "Pressure Cooker" (Autoclave) are routinely tested,
however it is felt by Motorola Reliability Engineering that
HTRB, HTGB, IOL and TC are the most important tests
ENVIRONMENTAL PACKAGE RELATED TEST
PROGRAMS:
A.
Physical Dimensions - Mil-Std-750, Method 2066.
This test is· performed to determine the conformance to device oulline drawing specifications.
B. VisuaJ and mechanical examination - Mil-Std-750,
Method 2071. A test to determine the acceptability
of product to certain cosmetic and functional criteria
such as marking legibility, stains, etc.
C. Resistance to Solvents - Mil-Std-202, Method
2025.3. A test to determine the solderability of device terminals.·
D. Terminal Strength - Mil-Std-750, Method 2036.
This test is a lead bend test to check for lead
strength.
E.
Constant Acceleration - MiloStd-750, Method
2006. The parts are accelerated to 20,000 G's and
higher to check for defects that would show up in
this environment.
F.
Vibration Variable Frequency - Mil-Std-750,
Method 2056. Parts are vibrated in different planes
and at different frequencies to check for loose particles or ruptured wire or die bonds.
Every manufacturing process exhibits a quality and reliability distribution. This distribution must be controlled to
assure It high mean value, a narrow range and a consistent shape. Through proper design and process control
this can be accomplished, thereby reducing the task of
screening programs which allemptlo eliminate the lower
tail of the distribution.
ACCELERATED STRESS TESTING
The nature of some tests in this report is such that they
far exceed that which the devices would see in normal
operating conditions. Thus, the test conditions "accelerate" the failure mechanisms in question and allow
Motorola to predict failure rates in a much shorter amount
of time than otherwise possible. Failure modes that are
temperature dependent are characterized by the Arrhenius model.
AF=e EA
K
(.!.._.!.. )
T2
T1
EA = Activation Energy, approximately 1.0 ev
K = Soltzman's Constant = 8.62 x 105 evfOK
T2 = Operating Temperature
T1 = Test Temperature
Therefore, actual device hours (attest conditions)
AF (accumulated device hours at operating temperature).
See following charts.
REVIEW OF DATA
High Temperature Reverse Bias (HTRB) indicates the
stability of leakage current, which is related to the field
distortion of TMOS devices. HTRB enhances the failure
mechanism by high temperature reverse bias testing, and
therefore is a good indicator of device quality and reliability, along with verification that process controls are effective. Motorola has processed through HTRB 6,166 de-
'fit(s): The value of fit is calculated directly from the failure rate which is • calculation based upon the number of rejects and total device hours/cycles.
One fit represents one failure in one billion hours.
uOevice System: The mechanical and physical properties combination which,
once manufactured result in"tt)e form of a device.
MOTOROLA TMOS POWER MOSFET DATA
A-172
and therefore the area of concentration. Motorola has
been in the semiconductor industry for many, many years
and would not have remained there without our continued
reliability, quality and customer relations.
TABLE 1
Total
No. of
Devices
Total
No. of
Failures
Actual Device
Hrs. or Cycles
Equivalent
Device Hrs.
@9O"C
Random
Failure Rate
%11000 hr•.
Fits
Note 2
HTRB
VOS = 80% max rating
VGS = 0 (shorted),
TA = 125'C on product
'" 500 V VOS
TA = 1500C on product
< 500 V VOS
6,166
3
1.8 x 106
1.8 x 108
0.0020
HTGB
VGS= +20V
VOS=O (shorted)
TA=l50'C
812
1
2.3 x 105
2.4 x t07
H3TRB
85'C@85%RH
VGS=O (shorted)
VOS=80% max rating
up to 500 V
2131
0
2.1 x 105
369
0
3.7 x 105
6,429
2
2.3 x 107
-
0.0115
14,149
0
9.4 x 105
-
0.0800
THERMAL SHOCK
- 551 + 150'C extremes
329
0
3.3 x 104
PRESSURE COOKER
P= 14.7psig, no bias,
T = 121'C
830
2
6.2 x 104
-
Test
HTSl
T A = 150'C for TO-220
T A = 200'C for TO-204 (TO-3)
IOl
ATj = l00'C
Free Air
TEMPERATURE CYCLE
T0-220 - 651 + 150'C
extremes
TO-204 (TO-3) - 651 + 200'C
extremes
MTBF
(Hours)
Note 3
MTBF
(Years)
20
5.0 x 107
5,723.4
0.0068
68
1.5 x 107
1,717.0
-
0.3200
3,200
3.1 x 105
35.0
3.820 x 107
0.0019
19
5.4 x 107
6,181.3
115
8.8 x 106
1007.
800
1.3 x 106
143.1
2.1
21,000
4.7 x 104
5.4
4.1
41,000
2.4 x 104
2.7
NOTE 2: Failure Unit (FIT):
Modem electroniC system reliability utilizing today's semiconductor devices requires quite low component failure rates, and therefore requires a workable number.
This number called a FIT (~ailure Un~) is defined as: FIT = one failure on 109 device hours.
NOTE 3: Mean Time Between Failures (MTBF):
The significant distribution properties of electronic system reliability is expressed as MTBF, which is defined as:
= lIX
Where, t
t
1\.
= time, hours
= failure rate
Audit Program and AOQ Monitors
enon along with the associated failure modeling. Through
proper failure identification and modeling, Motorola's Reliability engineers can effectively calculate meaningful failure rates.
AUDIT PROGRAM
Motorola has maintained a real time process control
audit program for a number of years since entering the
TMOS marketplace. The audit is continually expanding
and being refined, through short and long-term stress testing. The concept of Motorola's real time short-term stress
testing is to detect infant mortality defects, failure modeling through identification of failure mode/mechanism,
and data base generation that verifies all process controls
are effective. Once these defects are highlighted in the
audit testing, the system requires rapid corrective action
so that problems are kept within the factory and are not
sent to the customer. The concept of the long-term stress
testing is to detect random failure and wear out phenom-
AVERAGE OUTGOING QUALITY (AOQ)
With the industry trend to average outgoing qualities
(AOO) of less than 100 ppm, the role of device final test,
and final outgoing quality assurance have become a key
ingredient to success. At Motorola, all parts are 100%
tested to process average limits then the yields are monitored closely by product engineers, and abnormal areas
of fallout are held for engineering investigation. Motorola
also 100% redundant tests all DC parameters again after
MOTOROLA TMOS POWER MOSFET DATA
A-173
•
marking the device to further reduce any mixing problems
associated with the first test. Prior to shipping, the parts
are again sampled, tested to a tight sampling plan by our
Quality Assurance department, and finally our OFI inspection checks for paperwork, mixed product, visual and
mechanical prior to packaging to the customers.
AVERAGE OUTGOING QUALITY (AOQ)
AOQ = Process Average x Probability of Acceptance x 106 (PPM)
_ No. of Reject Devices
P
A
rocess verage - No. of Devices Tested
..
No. of Lots Rejected
Probability of Acceptance = (1 - No. of Lot!) Tested)
106 = To Convert to Parts Per Million
AOQ = No. of Reject Devices x (1 _ No. of Lots Rejected) x 106 (PPM)
No. of Devices Tested
No. of Lots Tested
FLOW CHART OF TMOS PRODUCTS
Samples Removed for
Long and Short Term Audits
Marking & 100% DC Electricals
Quality Assurance Outgoing
Sampled Per Mil-Std 105
Rejected
Returned to Final Test
for Corrective ACtion
from Product
Engineers
_ _ _ _ _..,.-_ _ _ _.... Rejected
Note 1: See Wafer Flow Chart (Page 12-2) .
Note 2: See Assembly Flow Chart (Page 12-3)
MOTOROLA TMOS POWER MOSFET DATA
A-174
Essentials of Reliability:
Paramount in the mind of every semiconductor user is
the question of device performance versus time. After the
applicability of a particular device has been established,
its effectiveness depends on the length of trouble free
service it can offer. The reliability of a device is exactly
that - an expression of how well it will serve the customer.
Reliability can be redefined as the probability of failure
free performance, under a given manufacturer's specifications, for a given period of time. The failure rate of
semiconductors in general, when plotted versus a long
period of time, exhibit what has been called the "bath tub
curve" (Figure 12-1).
INFANT
MORTALITY
RANDOM FAILURE
MECHANISM
5O%CL
X
I
I
I
I
r
/[?'[.900
CL/
I
I
.
I
S
~,
I
I
FAILURE RATE
FIGURE 12-2 - CONFIDENCE LIMITS AND THE DISTRIBUTION
OF SAMPLE FAILURE RATES
to A2 tables. The number of rejects is a critical factor since
the definition of rejects often differs between manufacturers. Due to the increasing chance of a test not being
representative of the entire population as sample size and
test time are decreased, the A2 calculation produces surprisingly high values of A for short test durations even
though the true long term failure rate may be quite low.
For this reason relatively large amounts of data must be
gathered to demonstrate the real long term failure rate.
Since this would require years of testing on thousands of
devices, methods of accelerated testing have been developed.
Years of semiconductor device testing has shown that
temperature will accelerate failures and that this behavior
fits the form of the Arrhenius equation:
R(t) = Ro(t)e- o/KT
WEAROUT
PHENOMENON
w
~
w
a:
=»
....I
~
FIGURE 12-1 - FAILURE RATE OF SEMICONDUCTOR
Where .R(t) = reaction rate as a function of time and
temperature
RELIABILITY MECHANICS
Since reliability evaluations usually involve only samples of an entire population of devices, the concept of the
central limit theorem applies and a failure rate is calculated
using the A2 distribution through the equation:
Ro = A constant
t = Time
T = Absolute temperature, °Kelvin CC
+
273°)
o = Activation energy in electron volts (ev)
A2 (a, 2r + 2)
A ,.; :":""...!c:.2:=n-=-t-'-'~
K
= Boltzman's constant = 8.62 x 10- 5 evfK
This equation can also be put in the form:
A2
= chi squared distribution
where a =
AF = Acceleration factor
100 - cl
----wo-
A
= Failure rate
cl
= Confidence limit in percent
n
= Number of devices
T2 .= User temperature
T1 = Actual test temperature
The Arrhenius equation states that reaction rate increases exponentially with the temperature. This produces a straight line when plotted on log-linear paper with
a slope expressed by o. 0 may be physically interpreted
as the energy threshold of a particular reaction or failure
mechanism. The overall activation energy exhibited by
TMOS Power FETs is 1.0 ev.
= Number of rejects
= Duration of tests
The confidence limit is the degree of conservatism desired in the calculation. The central limit theorem states
that the values of any sample of units out of a large population will produce a normal distribution. A 50% confidence limit is termed the best estimate, and is the mean
of this distribution. A 90% confidence limit is a very conservative value and results in a higher A which represents
the point at which 90% of the area of the distribution is to
the left of that value (Figure 12-2).
The term ( ~
- /'
Heat Sink
Suface
\
~~
made to the package and this is one of the several variables.
There are seven factors which determine the power
dissipation capability of a given package and they are:
Attachment, Power Dissipation, Package Orientation, Still
Free Air, Ambient Temperature, Lead Length (if applicable), and TJ(max).
One of the chief variables is mounting attachments. For
maximum power dissipation, it is helpful if the electrical
connection to the terminal which will permit the greatest
heat removal be as massive as possible. For a metal
package, it would be the case and for a plastic package
lead mounted, it would be the drain lead for a power
MOSFET.
tf.---.
Machine Screw or
Sheet Metal·Screw
Eyelet
Compression Washer
.
..~ The.rmopad Package
g~
Mica Washer
(Optional)
Mica Washer (Optional)
Spring Lock Washer
Machine or Speed
Nut
(a) Machine Screw M9unting
~'-1\
~
(b) Eyelet Mounting
Parts C50272-011 and C51451-011
Par' C52825-011
Material: Heat-Treated Spring
Steel 0.011 Thickness
Material: Heat-Treated Spring
Steel 0.011 Thickness
tM '
, = u \\,=*
S
0.105
0.500
TO-225AB Clip
Panel
Range
Range
- - 0.480
(e) Tinnerman Clips (Eaton Corp.)
TO-225AA Clip
FIGURE 13-7 - RECOMMENDED MOUNTING ARRANGEMENTS FOR To-225AA (TO-126)
MOTOROLA TMOS POWER MOSFET DATA
A-1BB
Free Air and Socket Mounting
In applications where average power dissipation is of
the order of a watt or so, power semiconductors may be
mounted with little or no heat sinking. The leads of the
various metal power packages are not designed to support the packages; their cases must be firmly supported
to avoid the possibility of cracked glass-to-metal seals
around the leads. The plastic packages may be supported
by their leads in applications where high shock and vi-
a) Preferred Arrangement
for Isolated or Non-isolated
Mounting. Screw is at Semiconductor Case Potential.
6-32 Hardware is Used.
b) Alternate Arrangement
for Isolated Mounting
when Screw must be at
Heat Sink Potential.
4-40 Hardware is Used.
Choose from Parts Listed
Below.
Use Parts Listed Below.
....
. . v---
4-40 Hex Head Screw
6-32 Hex ~
Head Screw
I!
lllr/
(1)Rectangular Steel!
Washer
\1
semicond~cto; I
(Case
bration stresses are not encountered and where no heat
sink is used. The leads should be as short as possible to
increase vibration resistance and reduce thermal resistance.
In many situations, because its leads are fairly heavy,
the TO-225AB package has supported a small heat sink;
however, no definitive data is available. When using a
small heat sink, it is good practice to have the sink rigidly
Non-Isolated
Mounting
.....
I
6-32 Hex Head
Screw
q __
4-40 Hex Head Screw
I
Standard
,....,...:c...,.--, _ _ _ Nylon Insulating Bushing
L1!:fOJ
~
I
Semiconductor
:
Motorola
Semiconductor
Case 340-01
TO-218AC
I
I
""
1
:==:::;:::=:==1
Heat Sink
Heat Sink
or
Chas~s
c=J
!
'';====>
! (
I
I
=:::JIC~i=:c======~,,::::::J1
CI
'\
~:
Standard
Mica Insulator
LJiI
(2)Nylon Bushing
(1) Flat wash~
(3)Flat Washer
'-==::::s
(4)Compression.
or Lock Washer
.........\F:.:;.,i.......,!~(
i
. . . . . D: Xl
_________ 4-40 Hex Nut
I
(1)
(2)
(3)
(4)
--~
I
c::.
6-32 Hex Nut
.....
I
I
(2)Rectangular Mica!
'\.
Insulating Mounting
From Screw
Nylon Insulating Bushing
?J~22=lA=)==::::::>
22~ 1221~) i
Insula~
I
I
Used with thin chassis and/or large hole.
Used when isolation is required.
Required when nylon bushing and lock washer are used.
Compression washer preferred when plastic insulating
material is used.
Torque Requirements
Compression
•
/
Nut or
I
Lock Washer -'\L......Li~...
i -.J('
I
I Y ]_ _ 4-40 Hex Nut
( T
6-32 Hex Nut ---,-·"",A",-,..~",,"..J.
II
Torque Requirements
0.68 NM (6 in.ilbs.) max.
Recommended Torque: 0.57 Nm/5 in.ilbs. -5.5 kg/cm.
Insulated 0.68 N-M (6 in-Ibs) max
Noninsulated 0.9 N-M (8 in-Ibs) max
FIGURE 13-8 - MOUNTING ARRANGEMENTS FOR
THERMOWATT PACKAGES (To-220)
Compression Washer
(1) Use with Lock Washer
FIGURE 13-9 -
MOUNTING METHODS FOR TO-218AC PACKAGE
MOTOROLA TMOS POWER MOSFET DATA
A-189
•
Handling Pins, Leads,and Tabs
mounted such that the sink or the board is providing total
support for the semiconductor. Two possible arrangements are shown.in Figure 13-11. The arrangement of
part (a) could be used with any plastic package, but the
scheme of part (b) is more practical with Case 77. With
the other package types, mounting the transistor on top
of the heat sink is more practical.
The pins and lugs of metal-packaged devices are not
designed for any bending or stress. If abused, the glassto-metal seals could crack. Wires may be attached using
sockets, crimp connectors, or solder, provided the data
sheet ratings are observed.
The leads and tabs of the plastic packages are more
flexible ,and can be reshaped, although this is not a recommended procedure for users to 'do. In some cases, a
heat sink can be chosen which makes lead-bending unnecessary. Numerous lead- and tab-forming options are
available from Motorola. Preformed leads remove the risk
of device damage caused by bending from the users.
In certain situations, in particular where semiconductor
testing is required, sockets are desirable. Manufacturers
have provided sockets for all the packages available from
Motorola. The user is urged to consult manufacturers'
catalogs for specific details.
T
Case 353-01
'y
Case 346-01 (MO-()4()AA)
#10-32 (x 5mm)
Binder Head _
Screw or
Round Head
'Belleville Washer
I
I
I
~ _ _ 'Belleville Washer,
_~
j---...,
-
Motorola Semiconductor _
MO-04OAA
Case 346-01
:
I
If===:::::::jl
--,
I:
\
'r-----i--+---i
I I
_ _ Motorola Semiconductor
I.
Case 353-01
!
i
[=:::::r=========:r::I~::::J"Mica Insulator
1
3 Mil Part #B12387B003
'Mica Washer
3 Mil Part
#B12387B001
Heat Sink _
1
1-1- -
:
I
#6-32 (=3mm)
RoundHead
Screw
-
I
..I'<--
\L__-'----:-'-_________...l..:-'-_ _
Flat Washer_
Lock Washer _
~- Flat Washer
~
c;;;;;t:::J _
1
Lock Washer
I
I
C¥ -
10-32 N u t _ ~
TORQUE REQUIREMENTS
1) Mounting To Heat Sink
#10-32 (X 5mm) Screws: 20 in.-Lb.
2) Lead To Buss with 114-20 Screws:
20 in.-Lb.
Heat Sink
4=
I
I
"Include Mica Washer For Isolated Mounting
6-32 Nut
TORQUE REQUIREMENTS
1) Mounting To Heat Sink with
6-32 (=3mm) Screws: 8 in.-Lb.
2) Lead To Buss with 5mm (=10-32)
Screws: 20 in.-Lb.
'RECOMMENDED BELLEVILLE WASHERS
WASHER
0-.0-.--
1.0.
Thickness
Pounds Flat
Part Number
Source:
0.472"
0.205"
0.024"
150 Lb
Am125206
CASE 346-01
CASE 353-01
0.281
0.138
0.Q13
43 Lb
60281'013
Rolex Co., National Disc Spring Div.
385 Hillside Ave.
Hillside, N.J. 07205
Associated Spring
961 N. DuPage Ave.
Lombard, III. 60148
RGURE 13-10 - MOUNTING OF ENERGY MANAGEMENT SERIES, CASE 346-01 AND CASE 353-01
MOTOROLA TMOS POWER MOSFET DATA
A-190
I
I
TABLE 3 -
Typical Junction-to-Ambient Thermal Resistance and Typical Power Dissipation
for Various Transistor Packages Without Heat Sinking
Without Heat Sink in Free Air
Motorola
Case Number
JEDEC
Number
Typical
R8JA ("C/W)
Typical Power
Dissipation (Watts)
1
TO-204M
(TO-3)
50
3.5
77
TO-225M
(TO-126)
83
1.5
80
TO-213M
(T0-66)
60
2.9
197
TO-204AE
(TO-3)
50
3.5
221A
TO-220AB
62
2.0
340
TO-218AC
45
2.8
If, however, lead-bending is done by the user, several
basic considerations should be observed. When bending
the lead, support must be placed between the point of
bending and the package. For forming small quantities of
units, a pair of pliers may be used to clamp the leads at
the case, while bending with the fingers or another pair
of pliers. For production quantities, 'a suitable fixture
should be made.
The following rules should be observed to avoid damage to the package.
Thermopad
Heat Sink Surface
Twist Locks
or
"'
Circuit Board
Soldera'tile
Legs
(al Simple Plate, Vertically Mounted
Heat Sink
1. A lead-bend radius greater than 1/16 inch is advisable for the TO-225M and 1/32 inch for TO-220.
2. No twisting of leads should be done at the case.
3. No axial motion of the lead should be allowed with
respect to the case.
The leads of plastic packages are not designed to withstand excessive axial pull. Force in this direction greater
than four pounds may result in permanent damage to the
device. If the mounting arrangement imposes axial stress
on the leads, a condition which may be caused by thermal
cycling, some method of strain relief should be devised.
An acceptable lead-forming method that provides this relief is to incorporate an S-bend into the lead. Wire wrapping of the leads is permissible, provided that the lead is
restrained between the plastic case and the point of the
wrapping. The leads may be soldered; the maximum soldering temperature, however, must not exceed 275°C and
must be applied for not more than five seconds at a distance greater than 1/8 inch from the plastiC case. When
wires are used for connections, care should be exercised
to assure that movement of the wire does not cause movement of the lead-to-plastic junctions.
Circuit Board
(bl Commercial Sink, Horizontally Mounted
FIGURE 13-11 - METHODS OF USING SMALL HEAT SINKS
WITH PLASTIC SEMICONDUCTOR PACKAGES
MOTOROLA TMOS POWER MOSFET DATA
A-191
II
I
Cleaning Circuit Boards
TJ = TC+ R6JC x Po
It is important that any solvents or cleaning ctiemicais
used in the process of degreasing .or flux removal do not
affect the reliability of the devices.
Alcohol and unchlorinated Freon solvents are generally
satisfactory for use with plastic devices, since they do not
damage the package. Hydrocarbons such as gasoline
may cause the encapsulant to swell, possibly damaging
the transistor die. Likewise, chlorinated Freon solvents are
unsuitable, sinoe they may cause the outer package to
dissolve and swell.
When using an ultrasonic cleaner for cleaning circuit
boards, care should be taken with regard to ultrasonic
energy and time of application. This is particularly true if
the packages are free-standing without support.
Thermal System Evaluation
Assuming that a suitable method of mounting the semiconductor without incurring damage has been achieved,
it is important to ascertain whether the junction temperature is within bounds.
In applications where the power disSipated in the semiconductor consists of pulses at a low duty cycle, the instantaneous or peak junction temperature, not average
temperature, may be the limiting condition. In this case,
use must be made of transient thermal resistance data.
For a full explanation of its use, see Motorola Application
Note, AN-SS9.
Other applications including switches driving highly reactive loads, may create severe current crowding conditions which render the traditional concepts of thermal resistance or transient thermal impedance invalid. In this
case,transistor safe operating area must be observed.
Fortunately, in many applications, a calculation of the
average junction temperature is sufficient: It is based on
the concept of thermal resistance between the junction
and a temperature reference point on the case. (See Appendix A) A fine thermocouple should be used, such as
#32AWG, to determine case temperature. Average operating junction temperature can be computed from the
following equation:
where
TJ = junction temperature (0C)
TC = case temperature (0C)
R6JC = thermal resistance junction-to-case as
specified on the data sheet (OC/W)
PO= power dissipated in the device (W).
The difficul.ty in applying the equation often lies in determining the power dissipation. Two commonly used empirical methods are graphical integration and substitution.
Graphical Integration
Graphical integration may be performed by taking oscilloscope pictures of a complete cycle of the voltage and
current waveforms, using a limit device. The pictures
should be taken with the temperature stabilized. Corresponding points are then read from each photo at a suitable number of time increments. Each pair of voltage and
current values are multiplied together to give instantaneous values of power. The results are plotted on linear
graph paper, the number of squares within the curve
counted, and the total divided by the number of squares
along the time axis. The quotient is the average power
dissipation.
Substitution
This method is based upon substituting an easily measurable, smooth dc source for a complex waveform. A
switching arrangement is provided which allows operating
the load with the device under test, until it stabilizes in
temperature. Case temperature is monitored. By throwing
the switch to the "test" pOSition, the device under test is
connected to a dc power supply, while another pole of the
switch supplies the normal power to the load to keep it
operating at full power level. The dc supply is adjusted so
that the semiconductor case temperature remains approximately constant when the switch is thrown to each
position for about 10 seconds. The dc voltage and current
values are multiplied together to obtain average power. It
is generally necessary that a Kelvin connection be used
for the device voltage measurement.
MOTOROLA TMOS POWER MOSFET DATA
A-192
APPENDIX A
THERMAL RESISTANCE CONCEPTS
The basic equation for heat transfer under steady-state
conditions is generally written as:
q = hMT
(1)
where q = rate of heat transfer or power dissipation
(PO),
h = heat transfer coefficient,
A = area involved in heat transfer,
.1.T = temperature difference between regions
of heat transfer.
However, electrical engineers generally find it easier to
work in terms of thermal resistance, defined as the ratio
of temperature to power. From Equation 1, thermal resistance, Ro, is
RO = .1.T/q = 1/hA
(2)
The coefficient (h) depends upon the heat transfer mechanism used and various factors involved in that particular
mechanism.
An analogy between Equation (2) and Ohm's Law is
often made to form models of heat flow. Note that .1.T
could be thought of as a voltage; thermal resistance corresponds to electrical resistance (R); and, power (q) is
analogous to current (I). This gives rise to a basic thermal
resistance model for a semiconductor as indicated by Figure A1.
The equivalent electrical circuit may be analyzed by
using Kirchoff's Law and the following equation results:
TJ = PO(Rruc + RoCS + ROSA) + TA
(3)
where
TJ = junction temperature,
Po = power dissipation,
RruC
semiconductor thermal resistance
ijunction to case),
RoeS
interface thermal resistance (case to
heat sink),
ROSA = heat sink thermal resistance (heat
sink to ambient),
TA = ambient temperature.
The thermal resistance junction to ambient is the sum
of the individual components. Each component must be
minimized if the lowest junction temperature is to result.
The value for the interface thermal reSistance, RoeS, Is
affected by the mounting procedure and may be significant compared to the other thermal-resistance terms.
The thermal resistance of the heat sink is not constant;
it decreases as ambient temperature increases and is
affected by orientation of the sink. The thermal resistance
of the semiconductor is also variable; it is a function of
biasing and temperature. In some applications such as in
RF power amplifiers and short-pulse applications, the concept may be invalid because of localized heating in the
semiconductor chip.
FIGURE A1 - BASIC THERMAL RESISTANCE MODEL SHOWING THERMAL TO ELECTRICAL ANALOGY FOR A SEMICONDUCTOR
MOTOROLA TMOS POWER MOSFET OATA
A-193
-
I
I
APPENDIXB
SOURCES OF ACCESSORIES
Insulators
Manufacturer
Aavid Eng.
AHAM
Astrodyne
Delbert Blinn
Ther-o-link 1000
#829
-
IERC
Thermate
Staver
-
Thermalloy
Tor
Tran-tee
Wakefield Eng.
Wei Corp.
Heat Sinks
Plastic Silicone
Unit/Duo
Rubber Stud Flange Disc Thermowall
Wall
"oint Compound BaO AI02 Anodize Mica Film
Thermacote
TJC
- - X
- - X
X
X
X
- -
"-
X
XLSOO
Type 120
-
-
-
-
-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
-
-
-
-
-
X
X
-
X
X
X
-
-
-
X
X
-
X
X
X
X
-
X
-
X
X
X
X
X
X
X
X
X
-
X
X
X
-
-
-
-
-
X
X
X
X
X
X
X
X
-
-
X
X
X
X
X
X
X
-
-
-
-
X
-
-
X
-
X
-
RF
Strlpllns
-
Other sources for Joint Compounds: Dow Corning, Type 340
Emerson & Cuming, Eccoshield - SO (Electrically Conducting)
Emerson & Cuming, Eccothenn - TC-4 (Electrically Insulating)
APPENDIX B
SUPPLIERS ADDRESSES
International Electronics Research Corporation, 135 West
Magnolia Boulevard, Burbank, California 91502
(213) 849-2481
The Staver Company, Inc., 41-51 North Saxon Avenue,
Bay Shore, Long Island, New York 11706
(516) 666-8000
Thermalloy, Inc" P.O, Box 34829, 2021 West Valley View
Lane, Dallas, Texas 75234
(214) 243-4321
Tor Corporation, 14715 Arminta Street, Van Nuys,
California 91402
(213) 786-6524
Tran-tec Corporation, P.O, Box 1044, Columbus,
Nebraska 68601
(402) 564-2748
Wakefield Engineering, Inc., Wakefield, Massachusetts
01880
(617) 245-5900
Wei Corporation, 1405 South Village Way, Santa Ana,
California 92705
(614) 834-9333
Aavid Engineering, Inc" 30 Cook Court, Laconia, New
Hampshire 03246
(603) 524-4443
AHAM Heat Sinks, 27901 Front Street, Rancho, California
92390
(714) 676-4151
Astrodyne, Inc., 353 Middlesex Avenue, Wilmington,
Massachusetts 01887
(617) 272-3850
Delbert Blinn Company, P.O. Box 2007, Pomona, California 91766
(714) 623-1257
Dow Corning, Savage Road Building, Midland, Michigan
(517) 636-8000
48640
Dayton Corporation, Engineered Fasteners Division,
Tinnerman Plant, P.O. Box 6688, Cleveland, Ohio 44101
(216) 523-5327
Emerson & Cuming, Inc., Dielectric Materials Division, 869
Washington Street, Canton, Massachusetts 02021
(617) 828-3300
MOTOROLA TMOS POWER MOSFET DATA
A-194
REFERENCES
1. K. Gauen, A. Pshaenich, "Investigation of Power
MOSFET FBSOA Using a Non-destruct Tester;" 14th
Annual IEEE Power Electronics Specialists Conference, 1983.
20. T. Lee, "Construction and Application of a Tester for
Measuring EOS-ESD Thresholds to 15 KV," EOSESD Symposium Proceedings, September, 1983.
21. R. Valentine, "FETs Improve Motor-Drive Efficiency,"
EON, September 15, 1983.
2. K. Gauen, "Designing With TMOS Power.
MOSFETs," Motorola Application Note AN-913,
1983.
22. W. Roehr, "Mounting Techniques for Power Semiconductors," Motorola Application Note AN-778,
1978.
3. K. Gauen, "Paralleling Power MOSFETs in Switching
Applications," Motorola Application Note AN-918,
1983.
23. T. Suva and B. Haver, "Flyback Switching Power Supplies," Motorola Engineering Bulletin EB-87A, 1982.
4. A. Pshaenich, "Characterizing C-E and D-S Diodes
for Switchmode Applications," Powerconversion
International, April, 1982, Motorola TDT-101A.
24. J. Alberkrack, "Theory and Applications of the
MC34063 and J,£A78540," Motorola AN-920, 1984.
5. R. Haver, "A 100 kHz FET Switcher," Powerconversion International, April, 1982.
25. A. Pshaenich, "New Power Bipolars compare Favorably with FETs for Switching EffiCiency," Motorola
Application Note AN-845, 1982.
6. C. Moyer, "Using Power MOSFETs in Stepping Motor
Control," Motorola Application Note AN-876, 1982.
26. W. Roehr, "Avoiding Second Breakdown," Motorola
Application Note AN-415A, 1972.
7. J. Schroeder, "MOSFETs Best Bipolars In Fast High
Current Driver," Electronic Design, October 28, 1982.
27. W. Roehr and B. Shiner, "Transient Thermal Resistance General Data and Use," Motorola Application
Note AN-569, 1972.
8. A. Pshaenich, "The MOS SCR, A New Thyristor
Technology," Motorola Engineering Bulletin EB-103,
1982.
28. W. Schultz, "A Method of Characterizing Power Transistors for Unspecified Parameters," Proceedings of
Powercon 10, March, 1983.
9. A. Pshaenich, "MOS Thyristor Improves PowerSwitching Circuits," Electronic Desigll, May 12, 1983.
29. D. Blackburn and D. Berning, "Power MOSFET Temperature Measurements," 13th Annual IEEE Power
Electronics Specialists Conference, 1982.
10. H. Saladin, "Fast Power FET Switch," Electronic
Design, December 22, 1983.
11. J. Phipps, "Two Integrated Circuit Drivers for Power
MOSFETs," Motorola TMOS Power FET Design Tips
TDT-102, 1982.
12. J. Phipps, "Drive Considerations
MOSFETs," Motorola TDT-103, 1982.
for
30. D. Blackburn, "An Electrical Technique for the Measurement of the Peak Junction Temperature of Power
TranSistors," 13th Annual Proceedings Reliability
Physics.
Power
31. D. Berning, "A Reverse Bias Safe Operating Area
Transistor Tester," NBS Special Publication 500-54,
U.S. Department of Commerce/National Bureau of
Standards.
13. H. Saladin and A. Pshaenich, "Paralleling Power
MOSFETs," Motorola TDT-104, 1982.
14. "Using the Motorola TMOS Designers Data Sheet,
TDT-105, 1982.
32. R. Severns, "dv/dt Effects in MOSFET and Bipolar
Junction Transistor Switches," PESC, 1981.
15. J. Takesuye and G. Fay, "MOSFETs Replace Bipolars and Circuits Are Better For It," Electronic Design,
December 20, 1980.
33. W. J. Slusark et ai, "Catastrophic Burn Out in Power
VDMOS Field Effect Transistors," Reliability Physics
Symposium, April, 1983, Phoenix, Arizona.
16. A. Pshaenich, "The Effects of Base Drive Considerations on RBSOA," Motorola Application Note
AN-828,1981.
34. E. Hebenstreit, "Overcoming the dv/dt Problem in
Power MOSFET Switching Stages During Commutation," PCI, September, 1982 Proceedings.
17. A. Pshaenich, "Relative Efficiencies of Motorola
Power Semiconductors in a PWM DC Motor Controller," Motorola Engineering Bulletin EB-108, 1983.
35. S. Clemente, B. R. Pelly and B. Smith, "The
HEXFETs Integral Body-Diode - Its Characteristics
and Limitations," AN-934A, International Rectifier.
18. K. Gauen, "Special Design Considerations for High
Power Multiple Die MOSFET Circuits," Powerconversion International, November-December, 1983.
36. J. G. Kassakian, "Some Issues Related to the Behavior of Multiple Paralleled Power MOSFETs," Electrical Power Systems Engineering Laboratory, M.I.T.,
Cambridge, Massachusetts 02139.
19. A. Pshaenich, "Dual Timer Supplies High Voltage
Ramp," Electronics, October 20, 1983.
MOTOROLA TMOS POWER MOSFET DATA
A-195
43. I. Yoshida, T. Okabe, M. Katsueda, S. Ochi and M.
Nagata, "Thermal Stability and Secondary Breakdown in Planar Power MOSFETs," IEEE Transactions
in Electron Devices, Vol. ED-27, No.2, February,
1980.
.
37. B. J. Baliga et ai, "The Insulated Gate Rectifier (lGn:
A New Power Switching Device," IEDM Technical
Digest, 1982, P. 264.
38. K. Gauen, "Paralleling Power MOSFETs in Linear
Applications," Proceedings of PCI/Motorocon, 1984.
39. W. Schultz, "High Current FETs - A New Level of
Performance," Powerconversion International,
March, 1984.
44. D. P. Kennedy, A. Phillips, Jr., "Source-Drain Breakdown in an IGFET," Int. Elec. Dev. Meet, Tech Dig,
pp. 160-163, paper 8.5, December, 1973.
40.. K. Gauen, "Power MOSFET Variant Excells At High
Loads," Electronic Design, AprilS, 1984.
45. T. Toyabe, K. Yamaguchi, A. Asai and M. Mock,
"A Numerical Model of Avalanche Breakdown in
MOSFETs," IEEE Transactions on Electron Devices,
Vol. ED-25, p. 825, 1978.
41. K. Gauen,. "MOSFETs Aid In Switch-Mode Power
Supply Growth," Electronic Engineering Times, April
23,1984.
46. F. Oettinger, D. Blackburn, S. Rubin, "Thermal Characteriziation of Power Transistors," IEEE Transactions on Electron Devices, Vol. ED-23, No.8, August,
1976.
42. A. Pshaenich, "The Energy Management Series, A
New Medium Current Package Raises Current Levels
to 100 A Efficiently and Cost Effectively," TBA.
MOTOROLA TMOSPOWER MOSFET DATA
A-196
III
Selector Guide
Table 1 -
Plastic TMOS
Power MOSFETs
B-2
Table 2 -
Metal TMOS
Power MOSFETs
B-5
Table 3 -
Energy Management
Series TMOS Power
MOSFETs
B-7
Table 4 -
TMOS Small-Signal
MOSFETs
B-7
Table 5 -
TMOS Product Matrix B-8
Table 1 -
Plastic TMOS Power MOSFETs
G
G
o
s
o
s
(MTP and IRF devices: in TO-220)
(MTA devices are in T0-225AA)
rOS(on)@IO
V(BR)DSS
Volta
loConl
Amps
(Ohms)
Min',
.,ax
Amps
1000
950
900
850
600
10
0.5
B,O
1.0
12
2.5
1.2
12
2.5
1.2
B.O·
6.0
4.0
2.0
1.5
0.5
1.5
3.0
0.5
550
500
450
400
350
250
200
(MTH devices are in TO-218)
0.8
8.0
6.0
4.0
2.0
1.5
0.8
5.0
3.3
1.5
1.0
0.55
5.0
3.3
1.5
1.0
0.55
0.50
2.0
2.4
1.8
1.5
1.2
1.0
0.8
0.7
0.6
0.4
0.35
0.22
0.18
0.16
1.5
3.0
0.5
1.0
1.5
2.0
3.5
0.5
1.0
2.5
2.0
3.5
1.0
1.5
3.0
2.5
4.0
1.0
1.5
3.0
2.5
4.0
5.0
1.0
1.25
1.0
1.25
2.0
2.5
2.5
3.5
5.0
4.0
6.0
10
10
7.5
Device
Max
PO@TC=25OC
Watts
MTP1Nl00
MTP1N95
MTP2N90
MTP2NB5
MTP1N60
MTP3N60
MTH6N60
MTP1N55
MTP3N55
MTH6N55
MTP1N50
MTP2P50'
MTP2N50
IRF832
IRF830
MTP4N50
MTH7N50
MTP1N45
MTP2P45'
MTP2N45
IRF833
IRF831
MTP4N45
MTH7N45
MTP2N4O
MTP3N4O
IRF732
IRF730
MTP5N4O
MTH8N4O
MTP2N35
MTP3N35
IRF733
IRF731
MTP5N35
MTHBN35
MTP10N25
MTP2N25
IRF612
MTP2N20
IRF610
MTA4N20
IRF622
MTP5N20
IRF620
MTP7N20
IRF832
IRF630
MTP8N20
MTP12N20
IRF642
IRF640
MTH15N20
1.0
75
'IndIcates P-Channel
MOTOROLA TMOS POWER MOSFET DATA
8-2
2.0
1.0
3.0
6.0
1.0
3.0
6.0
1.0
2.0
150
40
75
150
50
75
4.0
4.5
4.0
7.0
1.0
2.0
150
50
75
4.0
4.5
4.0
7.0
2.0
3.0
4.5
5.5
5.0
8.0
2.0
3.0
4.5
5.5
5.0
8.0
10
2.0
2.5
4.0
5.0
5.0
7.0
8.0
9.0
8.0
12
16
18
15
150
50
75
150
50
75
150
100
50
20
50
20
30
40
75
40
75
100
125
150
Table 1 - Plastic TMOS Power MOSFETs
To-220AB, TO-225AA and To-218AC (continued)
CASE 221A-02, CASE
n-04 CASE 340-01
~on)@ID
VIBR)DSS
IpConI
I hmo)
v_
Amps
IIIn
Max
Amp.
180
1.8
1.2
1.0
0.7
0.4
0.35
0.16
2.4
1.5
1.3
1.2
0.9
0.8
0.7
0.6
0.5
0.4
1.0
2.0
2.5
3.5
4.0
6.0
7.5
1.25
150
120
100
0.3
0.25
0.22
0.18
0.12
1.3
1.2
0.7
0.5
0.3
0.25
0.12
0.8
0.33
0.3
0.25
0.18
80
0.15
0.11
0.085
0.070
0.8
0.6
0.5
0.4
0.33
0.18
0.15
0.07
MTP2N18
MTA4N18
MTP5N18
2.0
4.0
5.0
7.0
B.O
12
15
2.0
2.5
3.0
4.0
5.0
4.0
7.0
B.O
B.O
9.0
10
15
16
18
20
3.0
5.0
7.0
B.O
10
15
50
30
75
5.0
5.0
7.5
10
IRFB31
MTP10N15
MTP15N15
IRF643
0.6
0.5
0.4
w_
3.5
5.0
4.0
1.5
2.5
3.5
4.0
5.0
7.5
10
2.0
3.0
4.0
5.0
4.0
B.O
6.0
10
15
12.5
2.0
3.0
4.0
5.0
6.0
10
12.5
= 250C
Max
MTP7N18
MTP8N18
MTP12N18
MTH15N18
IRF613
IRF611
MTP3N15
IRF623
MTASN15
IRF621
MTP7N15
IRF633
MTP8N15
1.5
2.5
PD@TC
Dovlce
IRF641
MTH2ON15
MTP3N12
MTASN12
MTP7N12
MTP8N12
MTP10N12
MTP15N12
MTH2ON12
MTP4N10
IRF512
IRF51 0
MTA6Nl0
MTP8Nl0
MTP8Pl0"
IRF522
MTP10N10
IRF520
IRF532
IRF530
MTP12N10
MTP20Nl0
IRF542
IRF540
MTH25N10
MTP4NOB
MTA6N08
MTPBNOB
MTPBP08"
MTP10NOB
MTP12N08
MTP2ON08
MTH25N08
"Indicates P-Channel
MOTOROLA TMOS POWER MOSFET DATA
B-3
20
4.0
3.5
4.0
6.0
8.0
100
150
20
50
40
30
40
75
100
125
150
50
30
75
100
150
50
20
30
75
7.0
10
B.O
12
14
12
40
75
20
24
100
125
40
75
27
25
4.0
6.0
8.0
150
50
30
75
10
12
20
25
100
150
.....
...
~
Table 1 - PI.astlc TMOS Power MOSFETs
T()'220AB, to-225AA and TO-218AC (continued)
CASE 221A-02. CASE 77-04 CASE 340-01
'D~)@ID
( ml)
V(BR)DSS
V_
Min
Max
OO
0..8
loCon !
Amps
Amps
2.0.
a.s
2.5
3.5
0..4
4.0.
50
0..3
0..28
0..25
0..20.
0..18
0..16
0..11
.0..065
0..06
0..0.55
0..8
0..4
0..28
0..20
0..16
0.10.
0..06
0.0.55
5.0.
8.0.
6.0.
8.0.
7.5
15
12.5
17.5
2.5
3.5
5.0.
s.a
7.5
6.0.
12.5
17.5
W_
IRF513
IRF511
MTP5NaS
MTA7NOs
IRF523
IRF521
MTPlalilbe
IRF533
MTP12Nas
IRF531
MTPI5N06
IRF543
IRF541
MTP25N06
MTH35Nae
MTP5Na5
MTA7Na5
MTP10N05
MTP12N05
3.5
20
4.0.
5.0.
7.0.
14
15
24
5.0.
7.0.
10.
50
30
75
12
100
150
35
~~0
~
Amps
Amps
0..5
8.0.
1.0.
2.5
1.2
1.5
2.5
1.2
6.0.
4.0.
2.0.
3.0.
1.5
3.0.
1.0.
2.5
2.0.
3.0.
0..8
0..4
6.0.
4.0.
2.0.
3.5
7.5
1.0.
2.5
1.5
2.0.
0..8
0..40
3.3
1.5
3.5
7.5
1.5
3.0.
1.0.
0..55
0.30
0
G0
IDCont
1.5
400
100
150
25
(Ohms)
10.
450
25
35
12
15
'DS(on)@ID
1000
500
125
27
0
Max
550
75
12
Drain connected to case
MIn
25"C
50
30
40
8.0.
10.
MTP15Na5
BUZla
MTP25Na5
MTH35N05
CASE 1-04 and CASE 1-05
V(~
=
Max
Table 2 - Metal TMOS Power MOSFETs
TO-204 (Formerly TO-3)
950
900
950
800
PD@TC
Davl. .
2.5
3.5
4.0
7.5
PD @ Tc
= 25"C
Davie•..
Max
w_
MTM1Nlaa
1.0.
75
MTM1N95
MTM2N90
MTM2N85
MTM3N6a
MTM6N60
MTM3N55
MTM6N55
MTM2P5a'
MTM2N50
IRF432
IRF430
MTM4N50
2N6762
MTM7N50
MTM15N5a
MTM2P45'
MTM2N45
IRF433. 2N6761
IRF431
MTM4N45
MTM7N45
MTM15N45
MTM3N4a
IRF332
IRF330
MTM5N4O
2N6760
MTM8N40
MTM15N4a
'Indicates P-Chennal
MOTOROLA TMOS POWER.MOSFET DATA
2.0.
3.0.
6.0.
3.0.
6.0.
2.0.
150.
75
150.
75
4.0.
4.5
4.0.
4.5
7.0.
15
150.
250.
2.0.
75
4.0.
4.5
4.0.
7.0.
15
3.0
4.5
5.5
ISO·
250.
75
5.0.
5.5
8.0
15
150
250.
Table 2 - Metal TMOS Power MOSFETs
TO-204 (Formerly TO-3) (continued)
V(BR)DSS
Volta
Min
350
250
200
'OS(on)@1o
(Ohms)
Max
Amps
3.3
1.5
1.0
1.5
3.0
0.55
0.30
0.50
1.2
1.0
0.8
0.7
0.6
0.4
0.35
0.22
0.18
0.16
0.12
180
150
loConl
Amps
0.085
0.08
1.0
0.70
0.40
0.35
0.16
0.08
1.2
0.8
0.7
0.6
2.5
4.0
7.5
5.0
2.5
3.5
5.0
6.0
4.0
6.0
10
7.5
16
20
2.5
3.5
4.0
6.0
7.5
20
2.5
MTM3N35
IRF333. 2N6759
IRF331
MTM5N35
MTM8N35
MTM15N35
MTM10N25
IRF222
MTM5N20
IRF220
MTM7N2O
IRF232
IRF230
2N6758
MTM8N20
MTM12N20
IRF242
IRF240
MTM15N2O
IRF252
IRF250
MTM40N20
MTM5N18
MTM7N18
MTM8N18
MTM12N18
3.0
4.5
5.5
5.0
8.0
15
10
4.0
5.0
0.4
0.33
0.3
0.25
O.lB
IRFl22
MTM10Nl0
IRF120
IRF132
IRF130
3.5
5.0
4.0
5.0
7.5
10
16
100
Max
MTM15N18
MTM40N18
IRF223
IRF221
MTM7N15
2N6757
IRF233
MTMBN15
IRF231
MTM10N15
MTM15N15
IRF243
IRF241
MTM2ON15
IRF253
IRF251
MTM45N15
MTM7N12
MTMBN12
MTM10N12
MTM15N12
MTM20N12
MTM45N12
MTMBN10
MTMBP10'
0.5
0.4
0.3
0.25
0.22
O.lB
0.12
120
Dsvlca
0.OB5
0.06
0.70
0.50
0.30
0.25
0.12
0.06
0.5
22.5
3.5
4.0
5.0
7.5
10
22.5
4.0
5.0
4.0
8.0
6.0
9.0
0.15
0.11
0.085
O.OB
10
15
0.07
20
12.5
O.OSS
0.04
20
27.5
MTM12Nl0
2N6758
MTM2ON10
IRF142
IRF140
IRF152
MTM25Nl0
IRF150
MTMSSN10
'Indicates P-Channal
MOTOROLA TMOS POWER MOSFET DATA
8-5
w_
PO@TC = 25"C
75
150
250
100
40
75
7.0
8.0
9.0
8.0
12
16
18
15
25
30
40
5.0
7.0
8.0
12
15
40
4.0
5.0
7.0
100
125
150
250
75
100
150
250
40
75
B.O
9.0
10
15
16
lB
20
25
30
45
7.0
B.O
10
15
20
45
B.O
7.0
10
B.O
12
14
12
14
20
24
150
125
150
250
75
150
250
75
40
40
75
100
125
27
33
25
40
55
150
250
Table 2 - Metal TMOS Power MOSFETs
T0-204 (Formerly TO·3) (continued)
CASE 1-04 and CASE 1'()5
~)@Io
V(~:lt.DSS
1!)ConI
( hms)
Ampa
Max
W_
4.0
MTM8NOS
MTM8POS-
8.0
75
5.0
6.0
10
12.5
27.5
MTM10N08
MTM12N08
MTM2ON08
MTM25N08
MTM55N08
IRFl23
IRF121
MTM10NOS
IRFl33,2N6755,
MTM12N05
IRF13f
MTM15N06
IRFl43
IRF141
MTM25N06
IRF153
MTM35NOS
IRF151
MTM80N06
MTM10N05
MTM12N06
MTM15N05
MTM25N05
MTM35N05
MTM60N06
10
12
Max
Amps
OO
0.50
0.40
0.33
0..18
0.15
0.07
0.04
80
0.4
0.3
0.28
0.25
0.20
0.18
0 ..16
0.11
0.85
0.08
0.055
50
0.028
0.28
0.20
0.16
0.08
0.055
0.028
PD@TC = 25'C
Dsvlce
Min
4.0
5.0
8.0
6.0
8.0
7.5
15
12.5
20
17.5
20
30
5.0
6.0
7.5
12.5
17.5
30
-Indicates P·Chsnnel
MOTOROLA TMOS POWER MOSFET DATA
8-6
20
25
55
7.0
8.0
10
12
14
15
24
27
25
33
35
40
80
10
12
15
25
35
60
100
150
250
40
75
125
100
150
250
75
100
150
250
Table 3 -
Energy Management Series
TMOS Power MOSFETs
5
5
CASE 346-01
0
~ ",.-
'",--
5
G
Mounting base is connected to the drain. CASE 353-01
'OS(on)@IO
VDSS
(Volta)
(0Itma)
(Amp)
30
60
30
60
32.5
80
0.048
0.024
0.048
0.024
0.038
0.020
0.038
0.020
0.028
0.012
0.028
0.012
0.Q18
50
0.008
0.Q18
200
180
150
120
100
80
65
32.5
65
31.5
75
31.5
15
50
100
50
100
0.008
Table 4 -
Device
MTE60N2O
MTE12ON2O
MTE60N18
MTE120N18
MTE65N15
MTE130N15
MTE65N12
MTE130N12
MTE15N10
MTE150N10
MTE15N08
MTE150N08
MTE100N06
IDiCont)
PO@TC=25"C
(Ampl)
(W_)
65
65
MTE200N06
MTE100N05
MTE200NOS
130
15
150
15
150
100
200
100
500
200
500
TMOS Small-Signal MOSFETs
(MO-001 AA)
250
500
250
500
250
500
250
L
(T0-39)
'~n)@lo
500
250
500
250
500
250
130
.," £~ 4r~~-IB)
~,
250
60
120
60
120
loCont
V(BR)DSS
Volta
Min
Amps
PO@TC=25"C
Ma.
Amps
Device
Max
Walls
Package
200
14
0.2
85101
0.25
0.6
TO-226M
(T0-92)
6.0
0.1
MPF9200
MFE9200
0.40
1.8
TO-206M
(TO-18)
5.0
0.2
B5110
0.50
0.6
Tg:~~
5.0
4.5
4.0
1.0
VN90AB
VN99AB
MPF6661
2N6661
2.0
6.25
TO-20SAD
(T0-39)
TO-22BAE
90
( hmo)
MPF990
MFE990
2.0
80
5.0
0.5
3.0
0.3
1.0
1.1
35
2.5
1.4
2.5
6.25
MFQ990C
MPF910/MPF10LM
MFE91 0
VN61AB
MPF6660
2N6660
2.5
6.25
0.5
2.0
4.0
2.5
6.25
2.5
6.25
MPF960
MFE980
2.5
6.25
MF0960C
VN35AB
4.0
6.25
MPF930
MFE930
2.5
6.25
MFQ930C
4.0
MOTOROLA TMOS POWER MOSFET DATA
8-7
Tg:~~D
T0-228AE
TO-205AO
(TO-39)
TO-116
TO-226AE
TO-205AO
(T0-39)
T0-226AE
Tg:6~~~0
TO-228AE
Tg:6.~D
TO-116
TO-205AO
(T0-39)
TO-228AB
Tg:6~D
TO-116
Table 5 -
TMOS Product Matrix
..1
'!:
0-oj
0
:Xl
0
~
2-2.9
2N50/45 I
MTM/MTP
2P50/45
en
OJ
Co
'1J
0
MTP
2N40/35
350
250
180
m
MFE9200
MPF9200
- 8S170
8S107
MTMlMTP
3N40/45
MTP
2N20/18
MTP
2N25
IRF610-12
:Xl
en
"m
12-13
20_24
14-19
50-'75
30-40
25-29
100-200
50/45
2N6759
MTM/MTP
5N40/35
2N67S0
IRF330·33
IRF730·33
IRF222
IRFS22
MTA
4N18/20
IRF220
IRFS20
MTM/MTP MTM/MTP MTM/MTP
7N20/18
5N20/18
8N20/18
IRF232
IRF632
MTMlMTP
10N25
2NS758
IRF230
IRF630
MTM/MTP IRF240.640
12N20/18
MTM
15N20118
IRF242.1
MTH
15N20/18
I
I
IRF252
IRFSll-13
MTP
3N15/12
IRF223.S23
MTA
5Nl2115
IRF221
IRF621
IRF221
IRF621
MTM/MTP
7N15/12
IRF233
IRFS33
2NS757
MTM/MTP
8N12/15
MTMIMTP
10N15/12
IRF231
IRF631
2N6757
MTMIMTP MTMIMTH
15N15/12 20N15/12
IRF241.641
100
80
2N6661
MPF6661
MPF990
MFE990
IRF512
MTP
4Nl0/08
MTA
SN08/10
IRF122
IRF522
MTM/MTP
8Nl0/08
MTM/MTP
8Pl0/08
IRF120
IRF520
MTM/MTP
10Nl0/08
MTMIMTP 12N6756I MTM/MTP
12Nl0/08
IRF130
20Nl0/08 I 25Nl0/08
IRF132
IRF530
IRF142
IRF532
IRF542
MTP
5NOS/05
IRF123
IRF523
MTA
7N05/0S
IRF121
IRF521
MTMlMTP
10N06l05
MTM/MTP MTM/MTP
12NOS/05 15N06/05
IRF131
2N6755
IRFl33
IRF531
IRF533
BUZ10
-oj
~
IRF510
1MFQ990C
60
50
I MPF910
MFE910 I 2N6660
MPF6660
MFE9S0
MPF9S0
MFQ960
MTM Prefix - TO-204
MTP PreIx - TO-220AB
MTH Prefix - T0-218AC
MTA Prefix - TO-225AA
IRF513
IRF511
MFE Prefix - TO-2OSAD (TO-39)
MPF Prefix - TO-226AA (T0-92)
MFO Prefix - TO-116
MTE Prefix - case 346 or 353
IRF100 1hru 400 Sertes IRF500 Ihru 800 Series -
I
TO-204
TO-220AB
IRFl43
IRF543
I
I
150
120
0
»
9-10
IRF830·33
400
:iE
'!:
0
8
I 7N50/45
I 4N50/45 I
-oj
'!:
0
-7
5-6
IRF250
MTM
IRF251
MTM
I
I
MTE
60N20/18
I
MTE
12ON2Of16
IS5N15/12
MTE
I130N15/12
MTE
I 75Nl0/08 I 150Nl0/08
..
)
Power Data Sheets
Data sheets are arranged in alphanumeric
sequence except when information applies to more
than one device, e.g., MTM10N08, MTM10N10,
MTP10N08 and MTP10N10. Consult the table of
contents for these part numbers.
®
2N6755
2N6756
MOTOROLA
Designer's Data Sheet
12.ilnd 14 AMPERE
N-CHANNEL TMOS
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
POWER FET
rDS(on) =0.25 OHM
60 VOLTS
rOS(on)= 0.18 OHM
100 VOLTS
These TMOS Power FETs are designed for low voltage, nigh
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds Specified at 100"C
Switching Times
• Designer's Data - lOSS, VOS(on), VGS(th) and SOA
Specified at Elevated Temperature
• Rugged -
SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
Loads
,r
GO---4/
TMOS
L~rE8~.~
t.
S
MAXIMUM RATINGS
Rating
c
Symbol
2N6755
2N6756
Unit
Drain-Source Voltage
VOSS
60"
100'
Vdc
Drain-Gilte Voltage
(RGS = 1.0 MOl
VDGR
60'
100'
Vdc
Gate Current -
__ ~____ •.
K
-w
------1
Q~F_~
V
Gate-Source Voltage
Drain Current
Continuous TC
TC
Pulsed
E
SEATI"G PLANE
+20
VGS
Vdc
H
..,
R
Adc
= 25"<:
= 100·C
Pulsed
Total Power
Dissipation @TC = 25·C
Derate above 25·C
Operating and Storage
Temperature Range
10
10M
IGM
12.0'
8.0"
25"
14"
9.0'
30"
1.5
U
PINt. GATE
Adc
2. SOURCE
CASE DRAIN
75'
0.6*
WI"C
-55" to 150'
·C
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Junction to Ambient
Maximum Lead Temp. for
Soldering Purposes, 1/16'
from case for seconds
S
STYLE3:
Watts
Po
TJ,Tstg
G
DIM
0c/w
R9JC
R9JA
1.67"
30"
TL
300*
A
B
C
,
0
·C
f
G
H
,
•
•
• JEDEC Registered Value.
V
Designer's Data for "Wons! Case" Conditions
The Designer's Data Sheet permits the design of most circuits entirely from
the information presented. Limit data - representing device characteristics
boundaries - are given to facilitate "worst case" design.
MOTOROLA TMOS POWER MOSFET DATA
C-2
.,.
MILLIMETERS
INCHES
MAX
MI. MAX
39.37
1.550
1.0
0
6.35
7.62 0.250
1.09
.038
0.043
0"
1.40
1.78 0.055 0.070
30.1588C
1.18188C
10.92 C
O.
5.46B8C
0.2158SC
16.898SC
O.65BSC
I1.1B 12.19 .
0.480
.81
.1
0.151 0.1
.87
1.050
0.100 O.lZ0
-
"
...
...
2.'
3 I
.18
0.18&
'-04
CASE
TO-204M
(TO-3TYPE)
2N6755,56
I
ELECTRICAL CHARACTERISTICS (TC
~ 25'C unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
60
100
-
-
-
-
1.0'
4.0'
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS ~ 0, 10 ~ 1.0 mAl
VBR(OSS)
2N6755
2N6756
Zero Gate Voltage Drain Current
(VOSS ~ Rated VOSS)
TJ ~ 125"<:
lOSS
Gate-Body Leakage Current, Forward
(VGSF ~ 20 V)
IGSSF
-
Gate-Body Leakage Current, Reverse
(VGSR = 20 V)
IGSSR
-
-
Vdc
mAdc
100'
nAdc
100'
nAdc
ON CHARACTERISTICS
Gate Threshold Voltage
liD ~ 1.0 mA, VOS ~ VGS)
TJ ~ l00"C
VGS(thl
Static Drain-Source On-Resistance (1)
(VGS ~ 10 Vdc, 10 ~ 8.0 Adc)
TC ~ 125'C
(VGS = 10 Vdc, 10 ~ 9.0 Adc)
TC ~ 125'C
rOS(on)
2.0'
1.5
2N6755
Orain·Source On·Voltage (VGS ~ 10 V) (1)
liD ~ 12 Adc)
liD ~ 14 Adc)
-
-
-
-
-
2N6756
VOS(on)
-
-
-
Vdc
4.0'
3.5
Ohms
0.25*
0.45'
0.18*
0.33*
Vdc
-
-
-
3.0'
2.52*
91s
4.0'
-
12.0'
mhos
-
800'
pF
2N6755
2N6756
Forward Transconductance (1)
(VOS ~ 15 V, 10 ~ 9.0 A)
-
CAPACITANCE
. Input Capacitance
Ciss
350'
Coss
150'
-
500*
Crss
50'
-
150*
-
-
30*
td(off)
-
-
40*
tf
-
-
45*
0.85'
0.90'
-
1.7*
I.S*
-
-
12'
14*
Adc
25
A
(VOS ~ 25 V, VGS ~ 0
f ~ 1.0 MHz)
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS
Turn-On Oelay Time
td(on)
(VOS ~ 36 V, 10 ~ 9.0 Adc
Zo ~ 150)
See Figs. 1 and 2
Rise Time
Turn-Off Delay Time
tr
Fall Time
ns
75*
SOURCE-DRAIN DIODE CHARACTERISTICS
Diode Forward Voltage (VGS ~ 0)
IS ~ 12A
IS ~ 14A
VF
2N6755
2N6756
Continuous Source Current. Body Diode
2N6755
2N6756
IS
Pulsed Source Current, Body Diode
2N6755
2N6756
ISM
I
I
Forward Turn-On Time
Reverse Recovery Time
ton
liS ~ Rated IS, VGS ~ 0)
trr
-
-
Vdc
-
-
-
250
-
325
-
30
*JEDEC registered values.
III Pulse Test: Pulse Width .. 300 ,.s, Duty Cycle" 2.0%.
RESISTIVE SWITCHING
FIGURE 2 - SWITCHING WAVEFORMS
FIGURE 1 - SWITCHING TEST CIRCUIT
td(on)
Pulse Generator
r----------,
I
I
Zo
Outpu\, Vout
Inverted
I
I
:
Zo
150
:20 V
tp = 1.0 I4S
L __________ J
MOTOROLA TMOS POWER MOSFET DATA
C-3
ns
2N6755,56
TYPICAl.. CHARACTERISTICS
FIGURE 3 - ON-REGION CHARACTERISTICS
30
•
/
TJl = 25'oC
25
~
....
/./ ./
' / /"
f-"
20
/ V/ ....-:
'z"'
-
, 'I
~ 10
'"
.9
5.0
o
/ /'
o
1.0
",-
'b IV
fW
V
30
g
g
// /
,"
~
§:
,
i
2.0
4.0
20
25
~
~
10
~
~
090
b"
I'
;3
I
B..O
10
12
:c
~
>
30
. VOS ~ VGS
'0· 10 mA
~
.... 080
"
6.0
1
'"
,
W
0
15
'0. ORAI.N CURRENT (AMPSI
~
100°C
10
12
~
VOS-l0V
'I
5.0
FIGURE 6 - GATE THRESHOLD VOLTAGE
VARIATION
'"
"'-
J
A
o
::;
W/
AV'+
1-1#
J J
1 ~
1J
o
...
TJ = 25"C- ~V
'r::"
........
0.70
-50
-15
VGS. GATHO-SOURCE VOLTAGE (VOLTSI
15
50
75
100
115150
TJ. JUNCTION TEMPERATURE lOCi
FIGURE 7 - THERMAL RESPONSE
>
I
-
ROJCltl - rill ROJC
ROJC = 1.67°C/W Max
I 111111
I
."
W
N
:0
o curves applv tor power
Pulse train shown
Read time' at 11
;!
"z
I
~ta~t
fJlpkl - TC = Plpkl ROJcitl ----j-t--H-tt
I
t, TIME (msl
MOTOROLA TMOS POWER MOSFETDATA
C-4
~
-55°C -
0.04
!?
70
V/
5. 0
..I.d.
0.08
Vi
20
3.0
40
50
6.0
Vos. ORAIN·TO·SOURCE VOLTAGE IVOLTSI
0
!--
25°C
~-
4'0- !-
-55°C_
-
0.16
5.0 V
3.5 V
0
.A
J.....r
~J=
:Ooo~- r-,..... r~ 1.
~ 1-
VGS=10V
~
~
""
J
r---
t;; 0.20
6.0 V
FIGURE 5 -TRANSFER CHARACTERISTICS
5
0.24
...z
........
/
~
~ 15
::>
e'"
u
1./7.0 V
Vi
...
FIGURE 4 - ON-RESISTANCE. VARIATION
~ 0.28
",
VGS = 20 vjt o v... Va.o 'k'
I
2N6755,56
OPERATING AREA INFORMATION
FIGURE 9 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
FIGURE 8 - MAXIMUM RATED FORWARD BIAS
SAFE OPERATING AREA, 2N6755
40
20
- - -- .-...
- - ....
~ 10
~ 6.0
:.
- -
--
-
--1-
-
40
0.1 ms
1.0m.
10 ms
;: 4. 0
z
de
~ 2. 0 e - - 'OSlon) Limit
u 1.0
~---- Package Limit
The,mal Limit
~ O. I-o 0.4
f-VGS
20
V. Single Pulse
.9 0.2
- TC = 25"<:
O. 1
0.06
0.04
1.0
2.0 3.0
5.0 7.0 10
20 30
VOS. DRAIN·TO·SOURCE VOLTAGE IVOLTS)
6~ =.
1==
=
2N6756_
2N67s5_
TJ '" 150"<:
50
o
o
70 100
20
40
60
80
VOS. DRAIN·TQ:SOURCE VOLTAGE IVOLTS)
100
FIGURE 10 - MAXIMUM RATED FORWARD BIAS
SAFE OPERATING AREA, 2N6756
0
20
~ 10
::;; 6.0
~ 40
~
...,..,
..-
a
2.0
~
.9
10ms
f--r.
~~ F'
o.4r-r-~
o. 2~ I-
1.
~ O.
The switching safe operating area (SOA) of Figure 9,
is the boundary that the load line may traverse without
incurring damage to the MOSFET. The fundamental lim·
its are the peak current, 10M and the breakdown voltage,
V(BR)OSS' The switching SOA shown in Figure 9 is applicable for both turn-on and turn-off of the devices for
switching times less than one microsecond.
The power averaged over a complete switching cycle
must be less than:
1.0ms
!z .
g§
SWITCHING SAFE OPERATING AREA
10J.00
0.043
0.070
1.1BlBse
0.40
O.21SBSC
O.665BSC
DMD 0.....
0.151 0.16
I. 0
-
0.100
0.t51
CASE 1·04
TO-204AA
(T0-3 TYPE)
0.120
0.16
2N6757,58
I
ELECTRICAL CHARACTERISTICS (TC = 25"<: unless otherwise noted)
Symbol
Characteristic
MIX
Min
Typ
150
200
-
-
-
-
1.0'
4.0'
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS = 0,10 = 1.0 mAl
VBR(OSS)
2N6757
2N6758
Vdc
Zero Gate Voltage Drain Current
(VOSS = Rated VOSS)
TJ = 125'C
lOSS
Gate-Body Leakage Current, Forward
(VGSF = 20 V)
IGSSF
-
-
lOa'
nAdo
Gate-Body Leakage Current, Reverse
(VGSR = 20 V)
'GSSR
-
-
lOa'
nAdo
-
mAde
ON CHARACTERISTICS
Gate Threshold Voltage
(10 = 1.0 mA, VOS = VGS)
TJ = l00'C
VGS(th)
Static Drain-Source On-Resistance (1)
(VGS = 10 Vdc, 10 = 5.0 Adc)
TC = 125'C
(VGS = 10 Vdc, '0 = 6.0 Adc)
TC = 125'C
rOS(on)
2N6757
2N6758
Drain-Source On-Voltage (VGS = 10 V) (1)
(10 = 8.0 Adc)
(10 = 9.0 Ado)
2.0'
1.5
-
-
4.0'
3.5
-
-
-
0.6'
1.13'
0.4'
0.75'
-
-
4.8'
3.6'
9.0'
mhos
pF
-
VOS(on)
2N6757
2N6758
Forward Transconductance (1)
(VOS = 15 V, 10 = 6.0 A)
Vdc
9ls
3.0'
Ohms
Vdc
CAPACITANCE
Input Capacitance
(VOS = 25 V, VGS = a
f = 1.0 MHz)
Output Capacitance
Reverse Transfer Capacitance
Ciss
350'
lOa'
-
BOO'
Coss
Grss
40'
-
150*
-
-
30'
tr
td(offl
-
SO'
-
-
tf
-
40*
0.75'
0.8'
-
1.50'
-
-
-
8.0'
9.0'
Ade
-
-
-
12
15
A
-
2SO
-
ns
325
450'
SWITCHING CHARACTERISTICS
Turn-On Delay Time
td(on)
(VOS = 175 V, 10 = 3.5 Ade
Zo = 150)
See Figs. 1 and 2
Rise Time
Turn-Off Delay Time
Fall Time
ns
50'
SOURCE-ORAIN DIODE CHARACTERISTICS
Diode Forward Voltage (VGS = 0)
IS = B.OA
IS = 9.0 A
VF
2N6757
2N6758
Continuous .Source Current, Body Diode
2N6757
2N6758
IS
Pulsed Source Current, Body Diode
2N6757
2N6758
ISM
Forward Turn-On Time
J
I
Reverse Recovery Time
-
ton
(IS = Rated 'S, VGS = 0)
trr
Vdc
1.60'
*JEOEC registered values.
(1) Pulse Test: Pulse Width :e; 300 pS, Duty Cycle"" 2.0%.
RESISTIVE SWITCHING
FIGURE 1 -
FIGURE 2 -
SWITCHING TEST CIRCUIT
SWITCHING WAVEFORMS
td(on)
Pulse Generator
r----------,I
:
:
I
Output, Vout
Inverted
Zo
...n..
:20V
ISO
PRF = 1.0 kHz
I
I
Zo
ISO
tp=I.0!'8
L __________ ..J
MOTOROLA TMOS POWER MOSFET DATA
C-7
•
2N6757,58
TYPICAL CHARACTERISTICS
FIGURE 3 - ON-REGION CHARACTERISTICS
16
v::
r I--"
~
10V-r ~ V
VGs l-20V I -
shv
•
/#V
7.0 V
1/
r
TJ =
0.4
./
f-
-55°C
~
5~ V -
lOooe
25°C
~
I
V
r---I
'"
"I
/
--- -
0.6
w
~
::>
66 v-
~V
VGS=10V
~
I
/.~
I~
o
:l
'"e.
'"~
I
Vb v
TJ=25°C
FIGURE 4 - ON-RESISTANCE VARIATION
_ O.B
0.2
c
I
o
2.0
4.0
6.0
B.O
VOS ORAIN·TO·SOURCE VOLTAGE (VOLTSI
10
VOS= 10V
r---
TJ = -55°C
1.2
~
11
..
'"
'"..
___ 100°C
;;0
~
10
'"
090
"'"
Vos =VGS
10 = 1.0 rnA
~
"--....
~
0
if!
~
,4
"'"
i!=
"'-.
i'..
::; o SO
'"
/II
"""
8
':j
H-VI
II;
25°C
~~
2.0
4.0
6.0
B.O
VGS ORAIN·TO·SOURCE VOLTAGE (VOLTSI
16
FIGURE 6 - GATE THRESHOLD VOLTAGE
VARIATION
II / I
L;.
12
10 DRAIN CURRENT (AMPSI
FIGURE 5 - TRANSFER CHARACTERISTICS
16
S.O
4.0
~ 0.70-50
,.
10
-25
50
25
100
75
"-
"-
125
"
150
TJ. JUNCTION TEMPERATURE (DC!
FIGURE 7 - THERMAL RESPONSE
10
..
.. 0 .. 0.5
0.5
r:::-
ott
0.3
0.1
.
-
0.1
0.05
0.1
--
---
f--- ..
-r....-r-
0.0
....
0.0 1
0.01
0.01
,.....
0.1
I
~l 11
~
1.0
1.0
50
·1
10
Read lime all,
TJlpkl
TC
Plpkl RI/JCIl!
I ! II II
10
t, TIME (ms)
MOTOROLA TMOS POWER MOSFET DATA
C-B
-
o curves apply for power
Pulse train shown
!
111I11
0.5
,
RI/JClll «11 RI/JC
RI/JC 1 67"C/W Max
'2
OUTYCVCII 0=11 '2
0.1
-
..
'
!JUL
r-
==
0.01
0.05
--
. _ ..
- ..
._-_.-
P1pkl
--
--- -Isrrmr
0.0 3 1__
--
"""
~
O.oz
0.0 5
"~l~ +-+
,,,,
..
.--~.-.
50
100
i
I
200
500
1000
2N6757,58
OPERATING AREA INFORMATION
FIGURE 8 - MAXIMUM RATED FORWARD BIAS
SAFE OPERATING AREA. 2N6757
FIGURE 9 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
18
--
10
-- - -- -
I"" --I-
--
0.1 ms
15
~
:;
LOms
~
10 .;;;-
~
=
~
~
u
de
2N6757-~
9.0
z
VGS 20 V, Single Pulse
:-- TC = 25°C
-
-
- r- TJ '" lSOOC
~ 6.0
-
o. 1
2N6758
!z
1--1..
- - - Package Limit
Thermal Limit
.
12
3.0
3.0
5.0
7.0 10
20 30
50 70 100
VDS, DRAIN·TQ·SOURCE VOLTAGE (VOLTS)
o
o
200 300
40
80
120
160
200
VDS, DRAIN·TO·SOURCE VOLTAGE (VOLTS)
240
FIGURE 10 - MAXIMUM RATED FORWARD BIAS
SAFE OPERATING AREA. 2N6758
30
20
SWITCHING SAFE OPERATING AREA
I
a
10 I"
~
10
le 7. 00
~ 5.
3. 0
2.0
0.1~===:::
The switching safe operating area (SOA) of Figure 9.
is the boundary that the load line may traverse without
incurring damage to the MOSFET. The fundamental limits are the peak current. 10M and the breakdown voltage.
V(BR)OSS. The switching SOA shown in Figure 9 is applicable for both turn-on and turn-off of the devices for
switching times less than one microsecond.
The power averaged over a complete switching cycle
must be less than:
1.0 ms
10 ms
de
0
~: 7
~
o. 5f=:
.9
o. 2f-f-o. 1
gs o.3[-0.07
0.05
0.03
--rOS(on) Limit
---- Package Limit
- - Thermal Limit
TJmax - TC
ROJC
3.0
5.0 7.0 10
20 30
50 70 100
VDS, DRAIN·TO·SOURCE VOLTAGE (VOLTS)
200 300
FORWARD BIASED SAFE OPERATING AREA
The dc data of Figures 8 and 10 are based on a case
temperature (TC) of 25°C and a maximum junction
temperature (TJmax) of 150°C. The actual junction
temperature depends on the power dissipated in the
device and its case temperature. For various pulse
widths. duty cycles. and case temperatures. the peak
allowable drain current (10M) may be calculated with
the aid of the following equation:
10M
Where
IO(25°C)
TJmax
TC
Po
R/lJC
r(t)
FIGURE 11- CAPACITANCE VARIATION
2000
TJ =1 250C
VGS = 0
f = 1 MHz
1500
~ 1200
;:!'
=IO(25°C) [TJmax - TC]
Po·R/lJc·r(t)
~
=dc drain current at TC = 25°C from Figure or
=Rated maximum junction temperature
=Oevice case temperature
=Rated power dissipation at TC = 25°C
= Rated steady state thermal resistance
= Normalized thermal response from Figure 7.
BOO
u
400
1\
,\
"
Ciss
\\
o
o
-~ t'--..
Coss
Crs.......
W
20
30
40
Vos, DRAIN·TO·SOURCE VOLTAGE (VOLTS)
MOTOROLA TMOS POWER MOSFET DATA
C-9
50
®
2N6759
2N6760
•
MOTOROLA
I)('sigrwl"'s Data Sheet
4.5 and 5.5 AMPERE
N-CHANNEL TMOS
POWER FET
rOS(on) = 1.5 OHM
N-CHANNEL ENHANCEMENT MODE SIUCON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
These TMOS Power FETs are designed for high voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds Specified at 100·C
350 VOLTS
rOSlon) = 1.0 OHM
400 VOLTS
Switching Times
• Designer's Data -lOSS, VOS(on), VGS(th) and SOA Specified
at Elevated Temperature
• Rugged - SOA is Power Dissipation Limited
• Source-to-Orain Diode Characterized for Use With Inductive
Loads
lr
TMDS
5
MAXIMUM RATINGS
Rattng
Symbol
2N6759
2N6760
Unit
Drain-Source Voltage
VOSS
350*
400*
Vdc
Drain-Gate Voltage
IRGS = 1.0 MO.l
VDGR
350*
400*
Vdc
Gate-Source Voltage
Drain Current
Continuous
:t20
VGS
Adc
TC
TC
= 25·C
= l00'C
Pulsed
10
10M
Gate Current ~ Pulsed
Total Power
Dissipation @ TC = 25'C
Derate above 25'C
Operating and Storage
Temperature Range
IGM
4.5*
3.0"
7.0
a
Vdc
5.5"
3.5"
B.O
1.5
STYLE3:
PIN I. GATE
2. SOURCE
CASE DRAIN
NOTES:
Adc
Watts
Po
75*
1. DIMENSIONS a AND v ARE DATUMS.
2. [jJ IS SEATING PLANE ANO DATUM.
3. POSITIONAL TOLERANCE FDA
MOUNTING HOLE 0:
I t 11.13(0.006)0 Ir Iv0 I
O.S"
WI'C
TJ, Tstg
-55* to 150*
'c
R6JC
R6JA
1.67"
30"
TL
300'
FOR LEADS:
I tll.13(O.00510rlv0I a01
4. DIMENSIONS AND TOLERANCES PER
ANSIYI4.5,1973.
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Junction to Ambient
Maximum Lead Temp. for Soldering
Purposes, y,." from case for
seconds
'CIW
01.
A
•
,,o
,
•a
C
'c
G
H
"JEDEC RegIstered Value.
R
-
U
Designer's Data for "Worst
v
ease" Conditions
The Designer's Data Sheet permits the design of most circuits entirely from the
information presented. Limit data - representing device characteristics boundaries
- are given to facilitate Uworst case" design.
MOTOROLA TMOS POWER MOSFET DATA
C-10
CASE 1-05
TO-2D4AA
(TO-3TYPEI
2N6759,60
ELECTRICAL CHARACTERISTICS (Tc
I
= 25°C unless otherwise noted)
I
Characteristic
Min
Symbol
Typ
Max
-
-
Unit
OFF CHARACTERISTICS
Breakdown Voltage
(VGS = 0,10 = 1.0 mAl
Drain~Source
VBR(OSS)
2N6759
2N6760
350
400
Vdc
-
-
-
-
1.0'
4.0'
-
100"
nAdc
-
-
100'
nAdc
2.0*
1.5
-
4.0'
3.5
-
-
1.5'
3.3"
1.0*
2.2*
-
-
7.0*
6.7'
.Zero Gate Voltage Drain Current
(VOSS = Rated VOSS, 10 = 1.0 rnA)
TJ = 125°C
lOSS
Gate-Body leakage Current, Forward
(VGSF = lOV)
IGSSF
-
Gate-Body Leakage Current, Reverse
(VGSR = 20V)
IGSSR
-
mAde
ON CHARACTERISTICS
Gate Threshold Voltage
(10 = 1.0 mA, VOS = VGS)
TJ = 100°C
VGS(th)
Static Drain-Source On-Resistance (1)
(VGS = 10 Vdc, 10 = 3.0 Adc)
TC = 125°C
(VGS = 10 Vdc, 10 = 3.5 Adc)
TC = 125°C
rOS(on)
2N6759
2N6760
Drain-Source On-Voltage (VGS = 10 V) (1)
(10 = 4.5 Adc)
(10 = 5.5 Adc)
VOS(on)
2N6759
2N6760
Forward Transconductance (I)
(VOS = 15 V, 10 = 3.5 A)
-
3.0'
9ls
Vdc
Ohms
Vdc
9.0'
mhos
600'
pF
CAPACITANCE
I
I
I
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
I
I
I
(VOS = 25 V,
VGS = 0
1= 1.0 MHz)
Ciss
Coss
Crss
I
I
I
350'
50'
20'
I
I
I
-
300'
80'
SWITCHING CHARACTERISTICS
Tum-On Delay Time
(VOS = 175 V,
10 = 3.5Adc
Zo = 15m
See Figs. 1 and 2
Rise TIme
Turn-Off Delay Time
-
30'
35*
-
-
0.70*
0.75'
-
1.40*
1.50*
-
-
-
-
4.5*
5.5'
-
-
7.0
8.0
A
-
ns
td(on)
-
tr
Id(off)
-
tl
Fall Time
ns
55*
35*
SOURCE-DRAIN DIODE CHARACTERISTICS
Diode Forward Voltage (VGS = 0)
IS = 4.5A
IS = 5.5 A
VSO
2N6759
2N6760
Continuous Source Current, Body Diode
IS
2N6759
2N6760
2N6759
2N6760
ISM
(Is = Rated IS,
ton
Pulsed Source Current, Body Diode
Forward Turn-On Time
J
Reverse Recovery Time
I
JEDEC registered values.
It
RGURE 1 -
VGS = 0)
trr
-
250
-
420
Adc
-
(1) Pulse Test = Pulse Width.;;; 300 itS, Duty Cycle.;;; 2.0%.
SWITCHING TEST CIRCUIT
RESISTIVE SWITCHING
FIGURE 2 -
SWITCHING WAVEFORMS
Pulse Generator
r----Zo- - - - - ,
Output, Vout
Inverted
I
I
I
I
Vdc
bov tp=1.0ps
L __________ ...1
Zo
150
MOTOROLA TMOS POWER MOSFET DATA
C-11
2N6759,60
TYPICAL CHARACTERISTICS
FIGURE 4 - ON-RESISTANCE VARIATION
FIGURE 3 - ON-REGION CHARACTERISTICS
10
•
8.0 V ~
/
~
VGS = 10V
8.0
i
t-TJ
1
6.0 V I - -
25°C
S.OV I - -
//
~
O. 8
~
So 2.0
.....
4.0
-~
f--
f
:i .
~ 4.0
z
~
I--
o
I
2.0
~
~
~
0.90
~
~
~
V/~
A
~
~
//J
_125°C
I--..
0.80
""
~
-55°C
v
I
10
8.0
VOS = VGS
lo=1.0mA
~
1.0
9
..L
TJ = 25°C
~
'"So 2.0
...........
11
w
I
1/
i
4.0
6.0
10. DRAIN CURRENT lAMPS)
1.2
I
I
;::- 6.0
I-
FIGURE 6 - GATE-THRESHOLD VOLTAGE VARIATION
5
/I
1/
.1
VOS = 30 V
2.0
20
8.0
12
16
VOS. ORAIN·TO·SOURCE VOLTAGE IVOLTS)
V
V
VGS= IOV
0
o
FIGURE 5 - TRANSFER CHARACTERISTICS
o
- --
4.0 V t---
10
8.0
/"
V
-55°C
o. 4
/
o
TJ~100o6
_r-"
1. 6
1. 2
/V'
4.0
-
1.0V
/ #: V
I/.-/. ~
;::- 6.0
~
V
1/ IP
25·~
:fi
z
.0
-'-
I
4.0
6.0
8.0
VGS. GATE-TO·SOURCE VOLTAGE IVOlTS).
~O.70
10
~
-50
-25
25
50
75
125
100
"'"
150
TJ. JUNCTION TEMPERATURE lOCI
FIGURE 7 - THERMAL RESPONSE
1.0
~
W2
D·O.5
0.5
~ ~ 0.3
~~
u.. IoU 0.2
U
~'"
w~
0.1
Q<
~
ffi 0,1
.....
<'"
II: ....
02
ZW
0.05
3-
0.0 5
~~ 0.0
~
0.0 2~
0.0 1
~
0.01
io'"
;;;;;-
Plpkl
frrmr
0.1
Pulse tram shown
~
'1 ~I
DUTV CVCIE 0=11 '1
~.~1.
0.05
o curves apply.tor power
"I~
~
....
R9JCIII '111 RHJC
R9JC 1.67°C/W Mall
JJUl
I
0.02
...... 0.02
-
..- -
--
--
;...-
i II II
I
0.2
0.5
1.0
5.0
2.0
t,
TIME
10
Read orne at 'I
TJlpkl
TC =Plpkl ReJc111
I
III II
20
50
(ms)
MOTOROLA TMOS POWER MOSFET DATA
C-12
100
I I
200
500
1000
2N6759,60
OPERATING AREA INFORMATION
FIGURE 9 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
FIGURE 8 - MAXIMUM RATED FORWARD BIAS
SAFE OPERATING AREA, 2N6759
10
10
-
5.0
u;
~ 3.0
;: 2.0
z
~
!5
u
1.0
;;;
10 ItS
....
1.0ms
......
~ 8.0
~
r-...
I-
~ 6.0
10m,
=----
PACKAGE LIMIT
c
-'
THERMAL LIMIT
9 0.3 -VGS :" 20 V, sniGU: PULSE
0.2 -TC 25"C
~ 0.5
0.1 ms
a
de
c
d
-
II
0.1
10
20
2N67S9_
~ 4.0
2.0
a
30
50
100
200 300
500
VDS, DRAIN·TO·SOURCE VOLTAGE (VOLTS)
2N6760-
1000
f----
TJ'" 150"C
o
100
200
300
400
VDS, DRAIN·TO-SOURCE VOLTAGE (VOLTS)
500
FIGURE 10 - MAXIMUM RATED FORWARD BIAS
SAFE OPERATING AREA, 2N6760
a
10 1"
5.0
u;
~ 3.0
~
.....
"-
2.0
1.0ms
ifi
a'"
10 ms
1.0
___ PACKAGE LIMIT - de
THERMAL UMIT
z
~ o. 5
9
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) of Figure 9,
is the boundary that the load line may 'traverse without
incurring damage to the MOSFET. The fundamentallimits are the peak current, 10M and the breakdown voltage,
V(BR)OSS. The switching SOA shown in Figure 9 is applicable for both turn-on and turn-off of the devices for
switching times less than one microsecond.
The power averaged over a complete switching cycle
must be less than:
0.1 ms
o. 3
o.2
o. 1
- VGS = 20 V, SINGLE PULSE
_ TC = 25°C
......
TJmax - TC
RruC
II
10
20 30
50
100
200 300
VDS, DRAIN·TO·SOURCE VOLTAGE (VOLTS)
500
FORWARD BIASED SAFE OPERATING AREA
The de data of Figures 8 and 10 are based on a case
temperature (TC) of 25"C and a maximum junction temperature (TJmax) of l50"C. The actual junction temper,
ature depends on the power dissipated in the device
and its case temperature. For various pulse widths; duty
cycles, and case temperatures, the peak allowable drain
current (10M) may be calculated with the aid of the following equation:
10M
FIGURE 11 - CAPACITANCE VARIATION
2000
TJ =1 25oC
VGS = 0
f = 1 MHz
1600
~
~ 1200
= IO,(25"C) [ TJmax - TC ]
Po . RruC . r(t)
~
Where
10 (25"C) = dc drain current at TC = 25"C from
Figure
or
TJmax = Rated maximum junction temperature
= Oevice case temperature
TC
= Rated power dissipation at TC = 25"C
Po
= Rated steady state thermal resistance
R8JC
r(t)
= Normalized thermal response from Figure 7.
'-' 800
\
"
CisS
l\
\\
'\ t"-..
o
a
Co..
Crs~
10
20
30
40
VDS, DRAIN-TO·SOURCE VOLTAGE (VOLTSI
MOTOROLA TMOS POWER MOSFET DATA
C-13
50
®
2N6761
2N6762
MOTOROLA
4.0 and 4.SAMPERE
N-CHANNEL TMOS
N-CHANNEL ENHANCEMENT MODE SIUCON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
POWER FET
reSlon) = 2.0 OHMS
450 VOLTS
reSlon) = 1.S OHMS
SOOVOLTS
These TMOS Power FETs are designed for high voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
• Silicon Gate for FaSt Switching Speeds Specified at 100°C
SWitching Times
• Designer's Data - 'OSS, VDS(on), VGS(th) and SOA
Specified at Elevated Temperature
• Rugged -
SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
Loads
1r
TMDS
Ir~t."
J -,
s
MAXIMUM RAnNGS
IE
.Symbol
2N6761
2N6762
Unit
Drain-Source Voltage
VOSS
450*
500*
Vdc
Drain-Gate Voltage
(RGS = 1.0 MOl
VOGR
450*
500*
Vdc
Rating
Gate-Source Voltage
10
10M
Gate Current -
IGM
Pulsed
Total Power
Dissipation @ TC = 25·C
Derate above 25°C
Operating and Storage
Temperature Range
±20
VGS
Drain Current
Continuous TC = 25·C
TC = l00·C
Pulsed
Maximum Lead Temp. for
Soldering Purposes, 1/16"
from case for seconds
r
0
K
j
Vdc
Adc
4.0*
2.5'
6.0
4.5*
3.0*
7.0
1.5
TJ,Tstg
PIN 1. GATE
2. SOURCE
CASE DRAIN
Adc
Watts
Po
u-
ST'VlE3
75*
0.6'
wrc
-55* to 150'
·C
NOTES:
1. DIMENSIONS Q AND V ARE DATUMS.
Z. [jJ IS SEATING PLANE AND DATUM.
3. POSITIONAL TOLERANCE fOR
MOUNTING HOLE Q:
I +11.I3(oOO51@ ITIv@1
FOR LEADS:
I +1,.13I"""I@T Iv@1 Q@I
4. DIMENSIONS AND TOLERANCES PER
ANSIYI4.5,I973.
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Junction to Ambient
E!}I
,'
.C/W
R8JC
R8JA
1.67*
30*
TL
300*
·C
*JEDEC Registered Value.
Designer's Data for "Worst Case" Conditions
The Designer's Data Sheet permits the design of most circuits entirely from
the information presented. Limit data - representing device characteristics
boundaries - are given to facilitate "worst case" design.
MOTOROLA TMOS POWER MOSFET DATA
C-14
CASE 1-115
TO-204AA
(T0-3 TYPE)
2N676T.62
I
ELECTRICAL CHARACTERISTICS ITC = 25'C unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
450
500
-
-
-
1.0"
4.0"
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
IVGS = 0,10 = 4.0 mAl
VBRIOSS)
2N6761
2N6762
Zero Gate Voltage Drain Current
IVoss = Rated VOSS, 10 = 1.0 mAl
TJ = 125'C
lOSS
-
Vdc
mAde
Gate-Body Leakage Current, Forward
IVGSF = 20 Vdc)
IGSSF
-
-
Gate-Body Leakage Current, Reverse
IVGSR = 20 Vdc)
IGSSR
-
-
100"
2.0"
1.5
2.7
2.2
4.0"
2N6761
-
-
2N6762
-
-
100"
nAdc
nAdc
ON CHARACTERISTICS
Gate Threshold Voltage
(10 = 1.0 mA, VOS = VGS)
TJ = l00'C
VGSlth)
Static Drain-Source On-Resistance 11)
IVGS = 10 Vdc, 10 = 2.5 Adc)
TC = 125'C
IVGS = 10 Vdc, 10 = 3.0 Adc)
TC = 125'C
rOSlon)
Vdc
-
-
-
8.0"
7.7"
2.5"
-
7.5"
-
VOSlon)
Forward Transconductance (1)
IVoS = 15 V, 10 = 3.0 A)
-
-
2N6761
2N6762
9fs
Ohms
2.0"
4.4"
1.5"
-
Drain-Source On-Voltage IVGS = 10 V) 11)
(10 = 4.0 Adc)
(10 = 4.5 Adc)
3.5
3.3"
Vdc
mhos
CAPACITANCE
I
I
I
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
IVoS = 25 V, VGS =
f = 1.0 MHz)
a
I
I
I
Ciss
Coss
Crss
I
I
I
350"
25"
IS"
I
I
I
I
I
I
800"
200"
50"
I
I
I
pF
I
SWITCHING CHARACTERISTICS
Turn-On Delay Time
-
Idlon)
IVoS = 225 V, 10 = 3.0 Adc
Zo = 150)
See Figs. 1 and 2
Rise Time
Turn-Off Delay Time
tr
-
td(off)
Fall TIme
tf
-
30"
-
30"
-
30"
1.10
1.15
1.3"
1.4"
-
ns
55"
SOURCE-DRAIN DIODE CHARACTERISTICS
Diode Forward Voltage IVGS = 0)
IS = 4.0A
IS=4.5A
0.65"
0.70"
Continuous Source Current. Body Diode
2N6761
2N6762
IS
Pulsed Source Current, Body Diode
2N6761
2N6762
ISM
I
I
Forward Turn-On Time
Reverse Recovery Time
Vdc
VSO
2N6761
2N6762
-
ton
(IS = Rated IS, VGS = 0)
trr
-
-
250
420
4.0"
4.5"
Adc
6.0
7.0
A
-
*JEOEC registered values.
(1) Pulse Test: Pulse Width oS: 300".s. Duty Cycle .... 2%.
RESISTIVE SWITCHING
FIGURE 1 -
FIGURE 2 -
SWITCHING TEST CIRCUIT
V~~~
~out
V,
SWITCHING WAVEFORMS
td(on)
OUT
Pulse Generator
,----z;-----,
Output, V out
Inverted
I
I
:
120 V
Zo
150
tp = 1.0 p.S
L __________ ...J
MOTOROLA TMOS POWER MOSFET DATA
C-15
ns
2N6761,62
TYPICAL CHARACTERISTICS
FIGURE 3 - ON-REGION CHARACTERISTICS
8.0
f
~ T~
VGS=IOV~
= 25JC
/~
6.0
~_
a
z
..-
/V
~
4.0
~
Q
~
Eo 2.0
~
~
V
FIGURE 4 - ON·RESISTANCE VARIATION
~,
"'~
~
illw
I. 2
'"
..,.
O. 8
6.0J
25°C
Q
Z
5.0J
-55 o
~ O. 4
JIL
II'
VOS=30V
0
.1 ---
L
0
:#/-
TJ = 100°C
0
'I
ffi
1.2
~
1.1
.
.'"
::!
..
-
0
~
w
--- r---
2.0
!--
4.0
6.0
10. DRAIN CURRENT (AMPS)
"
~
,...-
8.0
10
1.0
~
VOS = VGS
10 = 1.0 mA
~
~
0
>
g
25°C
I
0.90
w
0.80
i'-...
i=
.tVJ- r--- 55° C
....::. ~
4.0
6.0
8.0
2.0
-
FIGURE 6 ..... GATE THRESHOLD VOLTAGE
VARIATION
FIGURE 5 - TRANSFER CHARACTERISTICS
8.0
1--1-"
VGS-IOV
0
e
20
,/
....... ......
I
t
4.0
8.0
12
16
VOS. ORAIN·TO·SOURCE VOLTAGE IVOLTSI
.-1--'"""
t
Q
0;-
0
--
u
::>
"?
Q
./
1100o~
z
~
.1
4.0 V
o
TJ
1. 6
u
7.0V
Iv
",
o
2. 0
!;<
~
~
'"
~O.70
10
>
-50
50
25
-25
VGs. GATE·TO·SOURCE VOLTAGE (VOLTS)
75
100
"
125
"
150
TJ. JUNCTION TEMPERATURE 1°C)
FIGURE 7 - THERMAL RESPONSE
1.0
0" 0.5
0.5
- ,J1SL
w
>
~
.."~
~
z
"
'"
--
~i
0.3
~
0.2
0.1
0.1
I-
0.05
1-:-:'"1-
p-
0.0 31--'
0.0 21--"
.....
............
V
0.0 1
0.01
0.02
~
frlil1r
0.05
0.1
'1·1=,
DUTY CYel{ 0
1 'I
I1II11
0.2
0.5
1.0
2.0
5.0
10
E
11111I
20
t, TIME (ms)
MOTOROLA TMOS POWER MOSFET DATA
C-16
r-
Rruell) = ril) Rrue
Rrue = 1.67°CIW Max
ocurves apply for power
Pulse Irain shown
R.ad time atll
TJlpk) - Te = Plpk) Rruell)
.
-l 'if· I
~~,
. ..
I-- -
j-_..j---
Plpkl
-t
0.02
0.05
--
50
100
100
500
lOaD
2N6761,62
OPERATING AREA INFORMATION
FIGURE 8 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA, 2N6761
FIGURE 9 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
10.0
10 ""
0.1 ms
"
1.0ms
10ms
le 8.0
1
6.0
=>
z 4.0
~
20
2N676;2N6762
'"
30
50
100
200 300
VOS, ORAIN·TO·SOURCE VOLTAGE (VOLTS)
500
1000
o
o
100
200
300
400
VOS, ORAIN·TO·SOURCE VOLTAGE (VOLTS)
FIGURE 10 - MAXIMUM RATED FORWARD BIAS
SAFE OPERATING AREA, 2N6762
--
.,.,.
1.0ms
r-....
10m....
I'-....
dc
The switching safe operating area (SOA) of Figure 9,
is the boundary that the load line may traverse without
incurring damage to the MOSFET. The, fundamental limits are the peak current, 10M and the breakdown voltage,
V(BR)OSS. The switching SOA shown in Figure 9 is applicable for both turn-on and turn-off of the devices for
switching times less than one microsecond.
The power averaged over a complete switching cycle
must be less than:
10 ""
0.1 ms
"
r-..
Package Limit
Thermal Limit
r-....
TJmax - TC
ROJC
"'- r-....
VGS = 20 V, Single Pulse
TC = 25"C
. '.1 1
1
10
20 30
50
100
200 300
VOS, DRAIN·TQ·SOURCE VOLTAGE (VOLTS)
500
1000
FORWARD BIASED SAFE OPERATING AREA
FIGURE 11 - CAPACITANCE VARIATION
2000
The dc data of Figures 8 and 10 are based on a case
temperature (TC) of 25°C and a maximum junction
temperature (TJmax) of 150°C. The actual junction
temperature depends on the power dissipated in the
device and its case temperature. For various pulse
widths, duty cycles, and case temperatures, the peak
allowable drain current (10M) may be calculated with
the aid of the following equation:
10M
500
SWITCHING SAFE OPERATING AREA
10
--
Tj'" 150"C
9 2.0
II
10
--
u
o
VGS = 20 V, Single Pulse
TC = 25"C
0.1
-
~
"-
"
de
- - - Package limit
Thermal limit
0.1
,,
10
TJ =1 25"C
VGS = 0
f = 1 MHz
1600
,\
Ciss
l\
=IO(25°C) [TJmax - TC]
Po·Rruc·r(t)
\\
400
Where
IO(25°C) =dc drain current at TC = 25°C from Figure or
TJmax = Rated maximum junction temperature
= Oevice case tem peratu re
TC
= Rated power dissipation at TC = 25°C
= Rated steady state thermal resistance
Rruc
r(t)
= Normalized thermal response from Figure 7.
o
o
'\ "-
Coss
Crs~
10
20
30
40
VOS, ORAIN·TQ·SOURCE VOLTAGE (VOLTS)
Po
MOTOROLA TMOS POWER MOSFET DATA
C-17
50
IRF120
IRF121
IRF122
IRF123
IRF520
IRF521
IRF522
IRF523
®
Advance Information
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
MOTOROLA
Part Number
VDS
rDSlon)
ID
IRF120i520
100V
0.3 {}
8.0A
8.0A
IRF1211521
60V
0.3 {}
IRF1221522
100 V
0.4 {}
7.0 A
IRF1231523
60V
0.4 {}
7.0A
IRF120
IRF121
IRF122
IRF123
These TMOS Power FETs are designed for low voltage. high
speed power switching applications such as switching regulators•.
converters. solenoid and relay drivers.
JF··~·r
t.~K
cr/+o..
.1
• Silicon Gate for Fast Switching Speeds
• Rugged - SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
loads
,r
o
Go----"I!
STYLE 3
PIN 1. GATE
2. SOURCE
CASE DRAIN
TMOS
S
CASE 1-05
TO-204AA
(TO-3)
MAXIMUM RATINGS
IRF
Symbol
120
520
522
123
523
Drain-Source Voltage
VOSS
100
60
100
60
Vdc
Drain-Gate Voltage
(RGS = 1.0 MOl
VDGR
100
60
100
60
Vdc
10
8.0
8.0
7.0
7.0
Adc
10
5.0
5.0
4.0
4.0
Adc
.IDM
32
32
28
28
Adc
Rating
Gate-Source Voltage
Continuous Drain Current TC
Continuous Drain Current TC
Drain Current -
25·C
100·C
Pulsed
Gate Current·- Pulsed
Total Power
Dissipation @TC = 25·C
Derate above 25·C
Operating and Storage
Temperature Range
IGM
122
·::t20
VGS
=
=
121
521
Unit
Vdc
::tl.5
Adc
Watts
Po
Maximum Lead Temp. for Soldering
Purposes. 118" from case for 5 seconds
S
40
0.32
WI"C
TJ.Tstg
-55 to 150
·C
RruC
3.12
·CIW
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
·C
CASE 221A-02
TO-220AB
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
IRF520
IRF521
'IRF522
IRF523
TL
300
MOTOROLATMOS POWER MOSFET DATA
C-18
2.04
1.14
5.97
0.76
V
2.79
1.39
6.48
1.21
1.14
-
2.03
0.080
IRF120-123/520-523
I
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
-
-
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS = 0, 10 = 250 ,..A)
V(BR)OSS
IRF121,123,521,523
IRF120,122,520,522
Zero Gate Voltage Drain Current
(VGS = 0 V, VOS Rated VOSS)
(VGS = 0 V, VOS = 0.8 Rated VOSS, TC
60
100
lOSS
-
-
-
Vde
-
mAde
-
0.25
1.0
Forward Gate-Body leakage Current
(VGS = 20 V, VOS = 0)
IGSSF
-
-
100
nAde
Reverse Gate-Body leakage Curient
(VGS = -20 V, VOS = 0)
IGSSR
-
-
-100
nAdc
VGS(th)
2.0
-
4.0
Vdc
=
125°C)
ON CHARACTERISTICS·
Gate Threshold Voltage
(VOS = VGS, 10 = 250 ,..A)
On-State Drain Current
(VOS = 25 V, VGS = 10 V)
Adc
10(on)
IRF120,121,520,521
IRF122,123,522,523
Static Drain-Source On-Resistance
(VGS = 10 V, 10 = 4.0 A)
rOSlon)
IRF120,121,520,521
IRF122,123,522,523
Forward Transconductance
(VOS = 15 V, 10 = 4.0 A)
9fs
8.0
7.0
-
-
-
-
1.5
Ohms
0.30
0.40
-
mhos
pF
DYNAMIC CHARACTERISTICS
Input Capacitance
-
600
-
400
Crss
-
-
100
td(on)
-
tr
-
td(off)
-
-
100
tf
-
-
70
Ciss
Output Capacitance
(VOS
= 25 V, VGS = 0, f =
1.0 MHz)
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS' (TJ
=
100°C)
Turn-On Delay Time
Rise Time
Coss
VOO
Turn-Off Delay TIme
= 0.5 VOSS, 10 = 4.0 A
Zo = 50 n
Fall Time
40
ns
70
SOURCE DRAIN DIODE CHARACTERISTICS'
Characteristic
Forward On-Voltage
Reverse Recovery Time
I
I
(IS = Rated 10, VGS = 0)
Symbol
Typ
Unit
VSO
2.3
Vdc
trr
280
ns
'Pulse Test: Pulse Width .. 300 ".., Duty Cycle .. 2.0 %.
FIGURE 1 -
SWITCHING TEST CIRCUIT
FIGURE 2 -
Output, Vout
Inverted
MOTOROLA TMOS POWER MOSFET DATA
C-19
SWITCHING WAVEFORMS
•
IRF140
IRF141
IRF142
IRF143
IRF540
IRF541
IRF542
IRF543
®
Advance Information
II
MOTOROLA
Pa.t Numb••
VDS
'DSlonl
IRFl40/540
100V
0.085
• Rugged -
0.085 (}
100 V
0.11 (}
24A
IRFl43/543
GOV
0.11 (}
24.A
L
iF A.--=;-L
'./l
·c
-+
~~
SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
Loads
1r
27 A
SOV
IRF142/542
IRF140
IRF141
IRF142
IRFl43
• Silicon Gate for Fast Switching Speeds
27 A
IRF141/541
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
These TMOS Power FETs are designed for low voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
.
ID
n
.... ..".., ., •.....••
..
- .. •
....
•
I LIM
DIM M
STYLE 3:
PIN 1. GATE
2. SOURCE
CASE.ORAIN
TMOS
•,•
19.30
D
.1.46
B."
R
•
lUI
"".
INCHES
1.610
.1
7
E
1 B7
CASE 197-01
TO-Z04AE
(TO-3TYPEI
S
K
11.11
1 "
D." D.
• 7 • 3
0.135
1.177
.
.
"
11
1
MAXIMUM RATINGS
IRF
140
540
141
541
142
Symbol
542
143
543
Unit
Drain-Source Voltage
VOSS
100
60
100
60
Vdc
Drain-Gate Voltage
(RGS = 1.0 MOl
VOGR
100
60
100
60
Vdc
27
27
24
Adc
Rating
Gate-Source Voltage
Continuous Drain Current TC = 2S·C
Continuous Drain Current TC = 100·C
Pulsed Drain Current
Gate Current -
Pulsed
Total Power
Dissipation @ TC = 2SOC
Derate above 2S·C
Operating and Storage
Temperature Range
±20
VGS
10
24
Vdc
10
17
17
15
15
Adc
10M
108
108
96
96
Adc
IGM
1.5
Po
Adc
Maximum Lead Temp. for Soldering
Purposes, 1/8" from case for 5 seconds
G
Watts
125
1.0
wrc
TJ,Tstg
-55 to 150
·C
ReJC
1.0
·C/W
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
TL
300
·C
CASE 221A-GZ
TO-220AB
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
IRF540
IRFS41
IRf542
IRF543
MOTOROLA TMOS .POWER MOSFET DATA
C-20
MILLIMETERS
INCHES
DIM MIN MAX
MIN MAX
A 15.11 15.7
0.595 0.620
8
9.6510.290.36
0.45
C
4.06
4.82 0,160 0.190
0.64 0.890.0250.035
F
3.61
3.730.1420.147
2.41
2.670.0950.10
H 2.19
3.30 0.110 0.130
J
0.36
0.56 0.014 0.022
It 12.10 14.270.5000.562
L' 1.14
1.3 0.0450.855
N
4.83
5.33 0.190 0.210
Q
2.54
3.114 01
0.20
R
2.114
2.79 O.OBO O.ltO
S
1.14
1.390.11450.055
T
5.91
6.48 0.235 0.25
U 0.76
1.270.0300.050
1.14
0.045
2.03
0.080
IRF140-143/540-543
I
ELECTRICAL CHARACTERISTICS (TC
~ 25'C unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS ~ 0, 10 ~ 250 pAl
V(BR)OSS
IRFI40,142,540,542
IRFI41,143,541,543
-
100
60
-
Vdc
-
0.25
1.0
-
100
nAdc
-
-100
nAdc
2.0
-
4.0
Vdc
27
24
-
-
-
-
0.085
0.11
-
-
mhos
-
1600
pF
Zero Gate Voltage Drain Current
VGS ~ 0 V, VOS ~ Rated VOSS)
(VGS = 0 V, VOS = 0.8 Rated VOSS, TC ~ 125'C)
lOSS
Forward Gate-Body Leakage Current
(VGS = 20 V, VOS ~ 0)
'GSSF
Reverse Gate-Body Leakage Current
(VGS = -20 V, VOS ~ 0)
IGSSR
-
VGS(th)
-
-
mAdc
ON CHARACTERISTICS'
Gate Threshold Voltage
(VOS = VGS, '0 = 250 pAl
On-State Drain Current
(VOS = 25 V, VGS ~ 10 V)
10(on)
IRF140,141 ,540,541
IRFI42,143,542,543
Static Drain-Source On-Resistance
(VGS = 10 V, 10 = 15 A)
rOS(on)
IRFI40,141,540,541
IRF142,143,542,543
Forward Transconductance
(VOS = 15V,IO ~ 15A)
Ohm
6.0
9fs
Adc
DYNAMIC CHARACTERISTICS
Input Capacitance
-
Ciss
Output Capacitance
(VOS = 25 V, VGS = 0, f = 1.0 MHz)
Reverse Transfer Capacitance
Coss
Crss
SWITCHING CHARACTERISTICS' (TJ
=
-
~
800
300
100'C)
Tum-On Delay Time
Rise Time
VOO=30V,IO = 15A
Zo = 4.7 {}
Turn-Off Delay Time
Fall TIme
td(on)
-
tr
-
-
30
-
60
td(off)
-
-
80
tf
-
-
30
ns
SOURCE DRAIN DIODE CHARACTERISTICS'
Characteristic
I
Forward On-Voltage
Reverse Recovery Time
(IS = Rated '0, VGS
I
= 0)
Symbol
Typ
Unit
VSO
2.3
Vdc
trr
600
ns
·Puls. Test: Pulse W"fth '" 300 ,.s, Duty Cycle", 2.0 %.
FIGURE 1 -
Pulse Generator
r---:7"------,
:
I
I
Rgen
I
SWITCHING WAVEFORMS
Output, Vout
Inverted
:
100{}
5.0 {}
I
I
L
FIGURE 2 -
SWITCHING TEST CIRCUIT
_______ ...II
MOTOROLA TMOS POWER MOSFET DATA
C-21
IRF150
IRF151
IRF152
IRF153
®
Advance Information
MOTOROLA
Part Number
VDS
IRFl50
100 V
rDS(on)
0.0550
ID
40A
IRF151
SOV
0.0550
40A
IRF152
100V
0.080
33A
IRFl53
SOV
0.080
33A
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
IRF150
IRF151
IRF152
IRF153
These TMOS Power FETs are designed for low voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds
• Rugged -
SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
Loads
,r
C
G
1;
TMOS
SEATING
s
PLANE
F
a
MAXIMUM RATINGS
IRF
Rating
Symbol
150
151
152
153
Unit
Drain-Source Voltage
VOSS
100
60
100
60
Vdc
Drain-Gate'Voltage
(RGS = 1.0 MO)
VDGR
100
60
100
60
Vdc
Gate-Source Voltage
Continuous Drain Current TC = 25'C
Continuous Drain Current TC = 100'C
Drain Current Gate Current -
Pulsed
Pulsed
Total Power
Dissipation @'TC = 25'C
Derate above 25'C
Operating and Storage
Temperature Range
:!:20
40
40
Vdc
33
33
Adc
DIM
A
B
C
D
£
F
G
H
l
K
II
10
25
25
20
20
Adc
10M
160
160
132
132
Adc
IGM
1.5
Po
TJ,Tstg
Adc
Watts
150
1.2
wrc
-55 to 150
'c
R
THE~MAL CHARACTE~ISTICS
Thermal Resistance
Junction to Case
Maximum Lead Temp. for Soldering
Purposes, 118" from case for 5 seconds
2: Source
ease: Drain
VGS
10
Pin 1: Gate
RruC
0.83
'CIW
TL
300
·C
MOTOROLA TMOS POWER MOSFET DATA
C-22
MILLIMETERS
MIN
MAX
38.35 39.37
19.30 21.08
6.35
7.62
1.45
1.60
3.43
29.90 30.40
10.67 11.18
5.21
5.7
16.64 1 .15
11.18 12.19
3.84 4.09
24.68 26.67
INCHES
MIN
MAX
1.510 1.550
0.760 0.830
0.250 0.300
0.057 0.063
0.135
1.177 1.1[1
0.420 0.440
0.205 0.225
0.655 0.675
0.440 0.480
0.151 0.161
0.980 1.050
CASE 197-01
TO-2D4AE (TYPE)
(TO-3 TYPE)
IRF1S0-1S3
I
ELECTRICAL CHARACTERISTICS (Tc = 25'C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
100
60
-
-
-
Unit
OFF CHARACTERISTICS
Orain-Source Breakdown Voltage
(VGS = 0, 10 = 250 pAl
V(BR)OSS
IRF150,152
IRF151,153
Zero Gate Voltage Orain Current
(VGS = 0 V, VOS = Rated VOSS)
(VGS = 0 V, VOS = 0.8 Rated VOSS, TC = 125'C)
lOSS
Forward Gate-Body Leakage Current
(VGS = 20 V, VOS = 0)
IGSSF
-
-
Reverse Gate-Body Leakage Current
(VGS = -20 V, VOS = 0)
IGSSR
-
VGS(th)
Vdc
mAdc
0.25
1.0
100
nAdc
-
-100
nAdc
2.0
-
4.0
Vdc
40
33
-
-
-
-
-
0.055
0.08
9.0
-
-
mhos
-
3000
pF
-
1500
500
ON CHARACTERISTICS'
Gate Threshold Voltage
(VOS = VGS, 10 = 250,.A)
On-State Orain Current
(VOS = 25 V, VGS = 10 V)
10(on)
IRF150,151
IRF152,153
Static Drain-Source On-Resistance
(VGS = 10 V, 10 = 20 A)
rOS(on)
Forward Transconductance
(VOS = 15 V, 10 = 20 A)
Ohm
-
IRF150,151
IRF152,153
9fs
Adc
DYNAMIC CHARACTERISTICS
Input Capacitance
Coss
-
Crss
-
-
tdlonl
-
tr
-
-
Ciss
Output Capacitance
(VOS = 25 V, VGS = 0, f = 1.0 MHz)
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS' (TJ = 100'C)
Turn-On Oelay Time
Rise Time
VOO = 24 V, 10 = 20 A
Zo = 4.70
Turn-Oil Oelay Time
Fall Time
td(oll)
-
tf
-
35
ns
100
125
100
SOURCE DRAIN DIODE CHARACTERISTICS'
Characteristic
Forward On-Voltage
J
Reverse Recovery Time
(IS = Rated 10,-VGS = 0)
I
Symbol
Typ
Unit
VSO
2.3
Vdc
trr
600
ns
'Pulse Test: Pulse Width", 300 1'8, Outy Cycle", 2.0 %.
FIGURE 1 -
Pulse Generator
r----------,
:
:
I
I
IL
Rgen
AGURE 2 -
SWITCHING TEST CIRCUIT
Output, Vout
Inverted
:
1000
SWITCHING WAVEFORMS
5.00
_______ ...JI
MOTOROLA TMOS POWER MOSFET DATA
C-23
•
IRF620
IRF62I
IRF622
IRF623
IRF220
IRF22 I
IRF222
IRF223
•
®
Advance Information
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
MOTOROLA
Part Number
VOS
rOSlon)
10
IRF220/620
200 V
0.80
5.0 A
IRF221/621
150V
0.80
5.0 A
IRF2221622
200 V
1.20
4.0 A
IRF223/623
150V
1.20
4.0 A
IRF220
IRF221
IRF222
IRF223
These TMOS Power FETs are designed for low voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds
• Rugged - SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
Loads
LU4J h'
l. ..
_~
0
_____ .
K
_~~.~_l
F ---
,r
OIM
A
•
C
STYLE 3
PIN 1. GATE
2. SOURCE
CASE ORAIN
TMDS
S
CASE 1-05
TO-2D4AA
(TO-3TYPE)
o
E
f
G
H
J
K
•
R
U
V
MAXIMUM RATINGS
IRF
221
621
222
622
223
623
Unit
Symbol
220
620
Drain-Source Voltage
VOSS
200
150
200
150
Vdc
Drain-Gate Voltage
(RGS = 1.0 MOl
VDGR
200
150
200
150
Vdc
10
5.0
5.0
4.0
4.0
Adc
10
3.0
3.0
2.5
2.5
Adc
10M
20
20
16
16
Adc
Rating
Gate-Source Voltage
Continuous Drain Current TC
Continuous Drain Current TC
Drain Current Gate Current -
±20
VGS
= 2S·C
= 1000C
Pulsed
Pulsed
Total Power
Dissipation @ TC = 25·C
Derate above 25·C
Operating and Storage
Temperature Range
IGM
1.5
40
TJ,Tstg
Vdc
Adc
Watts
Po
0.32
wrc
-55to 150
·C
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Maximum Lead Temp. for Soldering
Purposes, 1/8" from case for 5 seconds
R8JC
TL
3.12
300
IRF620
IRF621
IRF622
IRF623
·crw
'c
DIM
0
A
S
CASE 221A-02
TO-220AB
9.65
Us
0.84
3.61
2.41
J
2.19
0.36
K
12.10
H
STYLE 5:
PIN 1. GATE
2. ORAIN
3. SOURCE
4. DRAIN
MOTOROLA TMOS POWER MOSFET DATA
C-24
•
C
0
f
G
MILLIMETERS
MIN MAX
\5.11 15.75
L
••
1.14
4.83
2.54
R
S
T
5.97
V
0.16
1.14
u
Z
2.04
\.14
10.29
4.82
0.89
3.13
2.81
3.30
0.56
14.27
0.105
5.33
3.04
2.19
0.120
.,
0.130
0.022
0.562
0.065
0.210
D.ll(}
0.055
0.255
0.050
1.39
6.48
1.27
2.03
-
0.080
IRF220-223/620-623
ELECTRICAL CHARACTERISTICS (TC = 25·C unless otherwise noted)
1
Symbol
Characteristic
I'
Min
Typ
200
150
-
-
-
-
0.25
1.0
-
100
nAdc
-
-100
nAdc
Vdc
Max
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS = 0, 10 = 250 pAl
V(BR)OSS
IRF220,222,620,622
IRF221 ,223,621 ,623
Zero Gate Voltage Drain Current
(VGS = 0 V, VOS = Rated VOSS)
(VGS = 0 V, VOS = 0.8 Rated VOSS, TC
lOSS
=
mAde
-
125·C)
Vdc
~
Forward Gate-Body Leakage Current
(VGS = 20 V, VOS = 0)
IGSSF
Reverse Gate-Body Leakage Current
(VGS = -20 V, VOS = 0)
IGSSR
-
VGS(th)
2.0
-
4.0
5.0
4.0
-
-
-
-
ON CHARACTERISTICS'
Gate Threshold Voltage
(VOS = VGS, 10 = 250 pAl
On-State Drain Current
(VOS = 25 V, VGS = 10 V)
Adc
10(on)
IRF220,221 ,620,621
IRF222,223,622,623
Static Drain-Source On-Resistance
(VGS = 10 V, 10 = 2.5 A)
rOS(on)
IRF220,221 ,620,621
IRF222,223,622,623
Forward Transconductance
(VOS = 15 V, 10 = 2.5 A)
9fs
1.3
Ohms
0.8
1.2
-
mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
-
600
-.
300
Crss
-
-
80
td(on)
-
tr
-
td(off)
-
tf
-
-
Ciss
Output Capacitance
(VOS
= 25 V, VGS = 0, f =
1.0 MHz)
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS' (TJ
=
Coss
pF
100·C)
Turn-On Delay Time
Rise Time
VOO = 0.5 VOSS, 10 = 2.5 A
Zo=50n
Turn-Off Delay Time
Fall Time
40
ns
60
100
60
SOURCE DRAIN DIODE CHARACTERISTICS'
Characteristic
Forward On-Voltage
Reverse Recovery Time
·Pulse Test: Pulse Width
FIGURE 1 -
~
I
I
(IS = Rated 10, VGS = 0)
300 IJS, Duty Cycle
~
Symbol
Typ
Unit
VSO
1.8
Vdc
trr
450
ns
2.0%.
SWITCHING TEST CIRCUIT
FIGURE 2 -
Output, Vout
Inverted
MOTOROLA TMOS POWER MOSFET DATA
C-25
SWITCHING WAVEFORMS
IRF630
IRF631
IRF632
IRF633
IRF230
IRF231
IRF232
IRF233
•
®
Advance Information
MOTOROLA
Part Number
VDS
rOS(onl
10
IRF230/630
200 V
0.40
9.0 A
IRF231/631
150 V
0.40
9·9A
IRF232/S32
200 V
O.SO
B.OA
IRF233/633
150V
0.60
B.OA
N-CHANNEL ENHANCEMENT MODE SIUCON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
These TMOS Power FETs are designed for low voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds
• Rugged -
SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
Loads
1r
A
B
C
STYLE 3
PIN 1. GATE
2. SOURCE
CASE DRAIN
TMOS
S
o
E
F
G
H
J
K
CASE 1-05
TQ-204AA
(TOoll
MAXIMUM RATINGS
IRF
Symbol
230
630
633
Unit
Drain-Source Voltage
VOSS
200
150
200
150
Vdc
Drain-Gate Voltage
(RGS = 1.0 Mfl)
VDGR
200
150
200
150
Vdc
10
9.0
9.0
8.0
B.O
Adc
10
6.0
6.0
5.0
5.0
Adc
10M
36
36
32
32
Adc
Rating
Gate-Source Voltage
Continuous Drain Current
Gate Current -
232
632
Pulsed
Pulsed
Total Power
Dissipation @ TC = 25·C
Derate above 25·C
Operating and Storage
Temperature Range
IGM
233
1.5
Adc
Maximum Lead Temp. for Soldering
Purposes. liS" from case for 5 seconds
G
Watts
Po
75
0.6
wrc
TJ,Tstg
-55 to 150
·C
R8JC
1.67
·CIW
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
TL
300
·C
CASE 221A-02
TO-220AB
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
IRF630
IRF631
IRF632
IRF633
Vdc
±20
VGS
TC = 25·C
Continuous Drain Current TC = 1000C
Drain Current -
231
631
MOTOROLA TMOS POWER MOSFET DATA
C-26
Q
•U
v
1
IRF230-233/630-633
I
ELECTRICAL CHARACTERISTICS (TC = 25'C unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
-
-
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS = 0, 10 = 250 ,.A)
V(BR)OSS
IRF230,232;630,632
IRF231 ,233,631 ,633
200
150
Zero Gate Voltage Drain Current
(VGS = 0 V, VOS = Rated VOSS)
(VGS = 0 V, VOS = O.S Rated VOSS, TC = 125'C)
lOSS
Forward Gate-Body Leakage Current
(VGS = 20 V, VOS = 0)
IGSSF
Reverse Gate-Body Leakage Current
(VGS = -20 V, VOS = 0)
IGSSR
-
VGS(th)
2.0
-
Vdc
,
-
mAde
-
100
nAdc
-100
nAdc
-
4.0
Vdc
0.25
1.0
ON CHARACTERISTICS'
Gate Threshold Voltage
(VOS = VGS, 10 = 250 ,.A)
On-State Drain Current
(VOS = 25 V, VGS = 10 V)
10(on)
IRF230,231,630,631
IRF232,233,632,633
Static Drain-Source On-Resistance
(VGS = 10 V, 10=5.0 A)
-
9.0
8.0
rOS(on)
-
IRF230,231 ,630,631
IRF232,233,632,633
Forward Transconductance
(VOS = 15 V, 10 = 5.0 A)
3.0
9fs
-
Adc
-
Ohm
0.4
0.6
-
mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
-
-
SOO
Coss
-
450
Crss
-
-
150
td(on)
-
-
30
tr
tdloff)
-
-
tf
-
-
Ciss
(VOS = 25 V, VGS = 0, f = 1.0 MHz)
Output Capacitance
Reverse Transfer Capacitance
pF
SWITCHING CHARACTERISTICS' (TJ = 100'C)
Turn-On Delay Time
Rise Time
VOO = 90 V, 10 = 5.0 A
Zo = 150
Turn-Off Delay Time
Fall Time
ns
50
50
40
SOURCE DRAIN DIODE CHARACTERISTICS'
Characteristic
I
Forward On-Voltage
Reverse Recovery Time
(IS = Rated 10, VGS = 0)
I
Symbol
Typ
Unit
VSO
1.S
Vdc
trr
450
ns
'Pulse Test: Pulse Width" 300 !'S, Duty Cycle" 2.0 %.
FIGURE 1 -
SWITCHING TEST CIRCUIT
FIGURE 2 -
SWITCHING WAVEFORMS
'd(on)
Pulse Generator
,---------,
:
I
I
Rgen
150
150
I
I
I
L
Output, Vout
Inverted
I
_______ ..JI
MOTOROLA TMOS POWER MOSFET DATA
C-27
~
IRF240
IRF241
IRF242
IRF243
IRF640
IRF641
IRF642
IRF643
®
Advance Information
II
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
MOTOROLA
Part !\lumber
VDS
rDSlon)
10
IRF240/640
200 V
0.180
18A
IRF241/641
150V
0.180
18A
IRF242/642
200 V
0.220
16A
IRF243/643
150 V
0.220
16A
IF
IRF240
A.-_
IRF241
~B.•c
IRF242
L
IRF243.-
These TMOS Power FETs are designed for low voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
~ "';~::r-' _D.:
• Silicon Gate for Fast Switching Speeds
• Rugged - SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
Loads
-+
~
@
.J-
'~
a
-
H
1
---.J.
'0
R
·G .
1r
STYLE 3:
PIN 1. GATE
2. SOURCE
CASE. DRAIN
TMOS
CASE 197-01
TO-2D4AE
(TO-3TVPE)
S
MAXIMUM RATINGS
IRF
241
641
242
243
Symbol
240
640
642
643
Unh
Drain-Source Voltage
VOSS
200
150
200
150
Vdc
Drain-Gate Voltage
(RGS = 1.0 MO)
VOGR
200
150
200
150
Vdc
Rating
Gate·Source Voltage
Vdc
±20
VGS
Continuous Drain Current TC = 25"<:
10
18
18
16
16
Adc
Continuous Drain Current TC = 100·C
10
11
11
10
10
Adc
10M
72
72
64
64
Adc
Drain Current Gate Current -
Pulsed
Pulsed
Total Power
Oissipation@ TC = 25·C
Derate above 2S·C
Operating and Storage
Temperature Range
IGM
1.5
Po
Adc
Watts
125
1.0
wrc
TJ.Tstg
-55to 150
·C
R8JC
1.0
.C/W
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
Tl
300
·C
CASE 221A-02
TO-220AB
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Maximum lead Temp. for Soldering
Purposes, 118" from case for 5 seconds
IRF640
IRF641
IRF642
IRF643
MOTOROLA TMOS POWER MOSFET DATA
C-28
MllLlM£TER
DIM MIN • X
38.35 39.37
19.30 21.
C
7.62
D
.. 45
1.80
E
'.43
29.0 30.40
10.&7 11.18
H
.1
••
,
•
..
."
.
"
INCHES
MAX
1.510
0.780
.260
0.051
0.135
1.177
.420
,
• • • ....
K
0
11.18
1.550
0.830
.,,,
....,
.1
12.19 0.... D.
.151
&.67
.11
1.
IRF240-24l/640-643
I
ELECTRICAl CHARACTERISTICS
(TC = 25·C unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
-
-
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS = 0, 10 = 250 pA)
V(BR)OSS
IRF240,242,640,642
IRF241 ,243,641 ,643
200
150
Zero Gate Voltage Drain Current
(VGS = 0 V, VOS = Rated VOSS)
(VGS = 0 V, VOS = 0.8 Rated VOSS, TC= 125°C)
lOSS
Forward Gate-Bodv Leakage Current
(VGS = 20 V, VOS = 0)
IGSSF
-
Reverse Gate-Body Leakage Current
(VGS = -20 V, VOS = 0)
IGSSR
VGS(th)
-
-
Vdc
mAde
100
nAdc
-
-
-100
nAdc
2.0
-
4.0
Vdc
•
0.25
1.0
ON CHARACTERISTICS
Gate Threahold Voltage
(VOS = VGS, 10 = 250 pA)
On-State Drain Current
(VOS = 25 V, VGS=10 V)
10(on)
Static Drain-Source On-Resistance
(VGS= 10V,10=10A)
-
18
16
IRF240,241,640,641
IRF242,243,642,643
6.0
-
Coso
-
-
Cros
-
-
300
-
-
30
rOS(on)
IRF240,241 ,640,641
IRF242,243,642,643
Forward Transconductance
(VOS = 15V,I0 = lOA)
-
9fs
-
Adc
Ohm
0.18
0.22
-
mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
Ciss
(VOS = 25 V, VGS = 0, f = 1.0 MHz)
Output Capacitance
Reverse Transfer Capacitance
1600
pF
750
SWITCHING CHARACTERISncS· (TJ = l00·C)
Turn-On Delay TIme
td(on)
Rise Time
VOO = 75 V, 10 = 10 A
Zo = 4.70
Turn-Off Delay TIme
Fall Time
tr
td(ofl)
tf
-
no
60
80
60
SOURCE DRAIN DIODE CHARACTERISTICS·
Characteristic
Forward On-Voltage
Reverse Recovery Time
I
I
(IS = Rated 10. VGS = 0)
Symbol
Typ
Unit
VSO
1.9
Vdc
trr
650
ns
'Pulse rest: Puis. Width", 300 1'8, Duty Cycle" 2.0 %.
FIGURE 2 - SWITCHING WAVEFORMS
FIGURE 1 - SWITCHING TEST CIRCUIT
Pulse Generator
r----:------,
:
I
I
Rgen
Output. Vout
Inverted
:
1000
I
5.00
I
I
L_-' _____ ..JI
MOTOROLA TMOS POWER MOSFET DATA
C-29
IRF250
1RF251
IRF252
IRF253
®
Advance Information
II
MOTOROLA
Part NIImber
VDS
'OSlon)
10
IRF250
200 V
0.0850
30A
IRF251
150 V
0.0850
30.A
IRF252
200 V
0~120
0
25A
IRF253
150V
0.1200
25A
NoCHANNEL ENHANCEMENT MODE SILICON GATE
TII/IOS POWER FIELD EFFECT TRANSISTOR
These TMOS Power FETs are designed for high voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
IRF250
IRF261
IRF252
IRF253
• Silicon Gate for Fast Switching Speeds
• Rugged - SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
Loads
TM
TMOS
S
MAXIMUM RAnNGS
IRF
Symbol
250
251
252
253
Drain-Source Voltage
VOSS
200
150
200
150
Vdc
Drain-Gate Voltage
IRGS = 1.0 MOl
VOGR
200
150
200
150
Vdc
Rating
Gate-Source Voltage
Continuous Drain Current TC
Continuous Drain Current
±20
VGS
= 25'C
= 100'C
25
25
Adc
19
.16
16
Adc
120
100
100
Adc
10
120
Gate Current -
IGM
Operating and Storage
Temperature Range
CASE DRAIN
30
10M
Pulsed
STVLE3:
PIN1. GATE
2. SOURCE
30
Pulsed Drain Current
Totel Power
Dissipation @ TC = 25'C
Derate above 25'C
Vdc
10
19
TC
Unit
1.5
Adc
Wails
Po
150
1.2
TJ,Tstg
-55 to 150
wrc
'c
R8JC
0.83
'CIW
TL
300
'C
THERMAL CHARACTERISTICS
Thermal Resiatance
Junction to Case
Maximum Lead Temp. for Soldering
Purposes, 1/8' from case for 5 seconds
MOTOROLA TMOS POWER MOSFET DATA
C-30
MILLIMETERS
DIM MIN
MAX
A 38.35 39.37
B \9.30 21.08
7.62
C
6.35
\.45
0
1.80
3.43
E
F
29.90 30.40
G 10.67 11.\8
5.21
H
5.72
j
\6.64
7.\
K 11.\8 \2.\9
0
3.84
4.09
R 24.89 26.67
INCHES
MIN
MAX
\.5\0 \.550
0.780 0.830
0.250 0.300
0.057 0.063
0.\35
.197
1.177
0.420 0.440
0.25
655
5
0.440 0.480
0.\5\ 0.161
0.980 1.050
-
CASE 197-01
TO-204AE
ITO-3TVPE)
IRF250-253
I
ELECTRICAL CHARACTERISTICS ITC = 25'C unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
-
-
-
0.25
1.00
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
IVGS = 0, 10 = 250 pAl
VIBR)DSS
IRF250,252
IRF251,253
Zero Gate Voltage Drain Current
(VGS = 0 V, VOS = Rated VOSS)
IVGS = 0 V, VOS = 0.8 Rated VOSS, TC
200
150
IDSS
=
125'C)
Vdc
mAde
Forward Gate-Body Leakage Current
IVGS = 20 V, VOS = 0)
IGSSF
-
-
100
nAde
Reverse Gate-Body Leakage Current
IVGS = -20 V, VOS = 0)
IGSSR
-
-
-100
nAdc
2.0
-
4.0
Vdc
-
-
ON CHARACTERISTICS'
Gate Threshold Voltage
IVOS = VGS, 10 = 250 pAl
VGSlth)
On-State Drain Current
IVoS = 25 V, VGS = 10 V)
1010n)
IRF250,251
IRF252,253
Static Drain-Source On-Resistance
IVGS = 10 V, 10 = 16 A)
30
25
rOSlon)
IRF250,251
IRF252,253
-
Forward Transconductance
(VOS = 15 V, 10 = 16 A)
9fs
8.0
Adc
Ohm
0.085
0.120
-
mhos
3000
pF
DYNAMIC CHARACTERISTICS
Input Capacitance
IVOS = 25 V, VGS = 0, f = 1.0 MHz)
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS' ITJ
=
Ciss
-
Coss
-
Crss
-
-
-
-
100
-
100
-
1200
500
100'C)
Turn-On Delay Time
tdlon)
Rise Time
VOO = 95 V, 10 = 16 A
Zo = 4.7 n
Turn-Off Delay TIme
tr
tdloff)
Fall Time
tf
35
n.
125
SOURCE DRAIN DIODE CHARACTERISTICS'
Characteristic
I
Forward On-Voltage
Reverse Recovery Time
*PUIS8 Test: Pulse Width
~
(IS
I
300 p.s, Duty Cycle
os;;
= Rated
10, VGS
=
0)
Symbol
Typ
Unit
VSO
1.8
Vdc
trr
750
ns
2.0 %.
RESISTIVE SWITCHING
FIGURE 1 -
FIGURE 2 - SWITCHING WAVEFORMS
SWITCHING TEST CIRCUIT
V~~~
\
RJ-:0ut
OUT
r !!!I,!!, _G.!r:!!'!.a.!~_,
:
Rgen
Output, Vout
Inverted
:
I
I
I
I
5.0n
I _______ .JI
L
MOTOROLA TMOS POWER MOSFET DATA
C-31
®
IRF330-333/430-433
IRF730-733/830-833
•
MOTOROLA
4.0-5-5 AMPERE
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
N-CHANNEL TMOS
POWER FETs
· .. designed for high-voltage, high-speed power-switching applications, such as line-operated switching regulators, converters, solenoid and relay drivers. These del(ice.s are direct replacements for
International Rectifier (IR) Power MOSFETs.
Switching Times
•
Silicon Gate for Fast Switching Speeds
Specified at Elevated Temperatures.
•
Rugged -
•
Low Drive Requirement, VGS(th) = 4.0 Volts (max)
A
'.
~
t. m
0
0
. '
•
.. __.-.1
--F~
,
H
'i
NOTES'
I. DIMENSIONS Q AND V ARE DATUMS.
2.
IS SEATING PLANE AND DATUM.
3. POSITIONAL TOLERANCE FOR
MOUNTING HOLE 0.:
lr
-=::;I ,
L~tB-::±-t:1C
IRF430-433
.
SOA Is Power Dissipation Limited
~
IRF330-333
'J
CD
[t [1.131,.00"0 [,[v0[
FOR LEADS:
[ t [
':'3{,oo"0' [vfrlifiJ
4. DIMENSIONS AND TOLERANCES PER
ANsr Y14.5. 1973.
TMOS
DIM
A
,•o
S
STYLE 3
PIN 1. GATE
2. SOURCE
E
f
G
CASE DRAIN
H
J
K
•
CASE 1-05
R
U
TO~204AA
V
MAXIMUM RATINGS
Symbol
Value
Unit
Drain-Source Voltage
vOSS
See Table 2, TO-204AA
See Table 3, TO-220AB
Vdc
Gate-Source Voltage
Rating
VGS
±20
Vdc
Drain Current - Continuous
10
See Table 2, TO-204AA
See Table 3. TO-220AB
Adc
Total Power
Dissipation @TC= 25°C
Derate above 25°C
Po
75
0.6
Watts
W/oC
-55 to 150
°c
Operating and Storage
Temperature Range
TJ, Tstg
IRF730-733
IRFS30-S33
K
L
•
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Maximum Lead Temp. for
Soldering Purposes, 1IS"
from case for 5 seconds
Q
R8JC
1.67
°C/W
TL
275
°c
•
S
T
U
12.10
1.14
483
2.54
2.04
1.14
5.97
0.16
1.14
-
STYLE 5:
PIN 1. GATE
Z. DRAIN
3. SOURCE
4. DRAIN
14.27 0.500
1.39 0.045
533 0.190
3." 0.100
2.19 0.080
139 0.045
6.48 0.23
1.21 0.30
0.045
2.03
ALLOWED.
4. ~::.~~~'~~'NG AND TOLERANCING PER ANSI
5. CONTROLLING DIMENSION: INCH.
C-32
0.08
NOTES:
1. DIMENSION If APPLIES TO ALL LEADS.
2. 01MENsrON L APPllESTO LEAOS 1 ANO 3 ONLY.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BOOYANO LEAD IRREGULARITIES ARE
CASE 221A-02
TO.220AB
MOTOROLA TMOS POWER MOSFET DATA
0.562
0.055
0.210
0.120
0.110
0.055
'.2
0.060
IRF330-333/430-433/730-733/830-833
TABLE 2 - TO-204AA (Formerly TO-3)
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
VOSS
(Volts)
10
(Amp)
'OS (on)
(Ohm)
Max
IRF330
400
5.5
1.0
IRF331
350
IRF332
400
4.5
1.5
IRF333
350
Device
IRF430
500
IRF431
450
IRF432
500
IRF433
450
@
10
(Amp)
VGS(th)
(Volts)
MiniMax
3.0
ton
(ns)
Max
toff
(ns)
Max
3.0
110
85
3.0
2.5
90
85
2.5
@
2.0/4.0
2.5
4.0
10
(Amp)
9f.
(mho)
Min
2.0
TABLE 3 - TO-220AB
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
VOSS
(Volts)
10
(Amp)
'OS(on)
(Ohm)
Max
IRF730
400
5.5
1.0
IRF731
350
IRF732
400
4.5
1.5
IRF733
350
Device
IRF830
500
IRF831
450
IRF832
500
IRF833
450
@
10
(Amp)
VGS(th)
(Volts)
MiniMax
3.0
ton
(ns)
Max
to.ff
(ns).
Max
3.0
110
85
3.0
2.5
90
85
2.5
@
2.0/4.0
2.5
4.0
10
(Amp)
9fs
(mho)
Min
2.0
MOTOROLA TMOS POWER MOSFET DATA
C-33
IRF510
IRF511
IRF512
IRF513
•
®
Advance Information
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
MOTOROLA
Part Number
VDS
ros on
ID
IRF510
l00V
0.60
4.0 A
IRF511
60V
0.6 ()
4.0 A
IRF512
100V
O.SO
3.5 A
IRF513
6O,V
O.SO
3.5 A
IRF510
IRF511
IRF512
IRF513
These TMOS Power FETs are designed for low voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds
• Rugged - SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
Loads
G
D
S
,r.
TMCS
S
MAXIMUM RATINGS
IRF
Rating
Symbol
510
511
512
513
Unit
Drain-Source Voltage
VDSS
100
60
100
60
Vdc
Drain-Gate Voltage
(RGS = 1.0 MO)
VDGR
100
60
100
60
Vdc
ID
4.0
4.0
3.5
3.5
Adc
ID
2.5
2.5
2.0
2.0
Adc
Drain Current Pulsed
IDM
16
16
14
14
Adc
Gate Current -
IGM
Gate-Source Voltage
Continuous Drain Current TC
Continuous Drain Current TC
Pulsed
Total Power
Dissipation @ TC = 25'C
Derate above 25'C
Operating and Storage
Temperature Range
Vdc
±20
VGS
= 25'C
= 100'C
1.5
Adc
Watts
PD
TJ,Tstg
NOTES:
1. DIMENSION H APPLIES TO ALL LEAOS.
2. DIMENSION L APPLIES TO LEADS 1 AND 3 ONLY.
3. OIMENSION Z DEfiNES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
4. DIMENSIONING AND TOLERANCING PER ANSI
YI4.51913.
5. CONTROLLING DIMENSION: INCH.
Maximum Lead Temp. for Soldering
Purposes, liS" from case for 5 seconds
C
o
F
G
H
20
0.16
wrc
-55 to 150
'c
K
L
N
R
S
T
U
V
J
Q
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
DIM
RIkIC
6.4
'CIW
TL
300
'C
z
MILLIMETERS
MIN
MAX
4.06
0.64
3.61
2.41
2.19
0.36
12.10
1.14
4.83
2.54
2.04
1.14
5.91
0.16
1.14
4.82
0.89
3.13
2.61
3.30
0.56
14.21
1.39
5.33
3.04
2.19
1.39
6.48
1.21
INCHES
MIN MAX
0.160
0.025
0.142
0.095
0.110
0.014
0.500
0.045
0.190
0.100
0.080
0.045
0.235
0.030
0.045
2.03
CASE 221A-G2
TO-220AB
MOTOROLATMOS POWER MOSFET DATA
C-34
0.190
0.035
0.141
0.105
0.130
0.022
0.562
0.055
0.210
0.120
0.110
0.055
0.255
0.050
0.080
IRF510-513
I
ELECTRICAL CHARACTERISTICS
(TC = 25'C unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
-
-
Unit
OFF CHARACTERIS11CS
Drain-Source Breakdown Voltage
(VGS = 0, 10 = 250 pAl
V(BR)OSS
IRF510,512
IRF511,513
Zero Gate Voltage Drain Current
(VGS = 0 V, VOS = Rated VOSS)
(VGS = 0 V, VOS = 0.8 Rated VOSS, TC
100
60
lOSS
Forward Gate-Body Leakage Current
(VGS = 20 V, VOS = 0)
IGSSF
Reverse Gate-Body Leakage Current
(VGS = -20 V, VOS = 0)
IGSSR
-
VGS(th)
= 125'C)
Vdc
mAdc
0.25
1.0
100
nAdc
-
-100
nAdc
2.0
-
4.0
Vdc
4.0
3.5
-
-
-
0.6
0.8
ON CHARACTERISTICS'
Gate Threshold Voltage
(VOS = VGS, 10 = 250 pAl
On-State Drain Current
(VOS = 25 V, vGS = 10 V)
10(on)
IRF510,511
IRF512,513
Static Drain-Source On-Resistance
(VGS = 10 V, 10 = 2.0 A)
Ohms
rOS(on)
-
IRF510,511
IRF512,513
Forward Transconductance
(Vos = 15 V, 10 = 2.0 A)
Adc
-
1.0
9f.
-
mhos
150
pF
DYNAMIC CHARACTERISTICS
Input Capacitance
-
-
Crs•
-
-
tdlon)
-
Ir
-
!dloff)
-
tf
-
-
Ciss
Output Capacitance
(VOS
= 25 V, VGS = 0, f = 1.0 MHz)
COBS
Reverse Transfer Capacitance
100
25
SWITCHING CHARACTERl5nCS' (TJ - 100'C)
Tum-On Delay Time
Rise Time
VOO = 0.5 VOSS, 10
Zo=50n
Turn-Off Oelay Time
= 2.0 A
Fall Time
20
n.
25
25
20
SOURCE DRAIN DIODE CHARACTERISTICS·
Characteristic
I
I
Forward On-Voltage
Reverse Recovery Time
'Pulse Test: Pulse Width", 300
p.O,
(IS = Rated 10, VGS = 0)
Symbol
Typ
Unit
VSO
2.0
Vdc
Irr
230
n.
Duty Cycle", 2.0 %.
RESISTIVE SWITCHING
FIGURE 1 -
SWITCHING TEST CIRCUIT
FIGURE 2 -
SWITCHING WAVEFORMS
td(onl
Output, Vout
Inverted
MOTOROLA TMOS POWER MOSFET DATA
C-35
IRF530
IRF531
IRF532
IRF533
•
IRF130
IRF131
IRF132
IRF133
®
Advance Information
MOTORoLA
Part Number
Vos
rOSlonl
10
IRF530/130
100 V
0.180
14A
IRF531/131
60V
0.180
14A
IRF532/132
,i.oov
0.250
12A
IRF5331133
SOV
0.250
12 A
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
~A
IRF130
:~~~~~
These TMOS Power FETs are designed for low voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
L
.•
.
IRF133
~"l;
• Silicon Gate for Fast Switching Speeds
• Rugged - SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
loads
'-~-r
--t
~
.;"_.
1
H
1r
STYLE 3
PIN 1.
GATE
2. SOIlRCE
CASE"DRAIN
•
s
J
MAXIMUM RATiNGS
IRF
Symbol
530
130
531
131
532
132
533
133
Unit
Drain-Source Voltage
VOSS
100
60
100
60
Vdc
Drain-Gate Voltage
(RGS = 1.0 MOl .
VOGR
100
60
100
60
Vdc
10
14
14
12
12
Adc
10
9.0
9.0
8.0
8.0
Adc
10M
66
56
48
48
Adc
Continuous Drain Current TC
Continuous. Drain Current TC
Drain Current Gate Current -
±20
VGS
= 25"C
= 10O"C
Pulsed
Pulsed
Total Power
Dissipation @ TC = 25"C
Derate above 25'C
Operating and Storage
Temperature Range
IGM
1.5
Po
Maximum Lead Temp. for Soldering
Purposes, 118" from case for 5 seconds
•
Q
"
U
v
IRF530
IRF531
IRF532
IRF533
Vdc
Adc
Watts
75
0.6
wrc
TJ,Tstg
-55 to 150
'c
R6JC
1.67
'c/w
TL
300
'c
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
C
D
E
CASE 1-05
T0-204AA
(TO-3TYPEI
Gsta-8ource Voltage
•
F
G
TMOS
Rating
DIM
A
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
CASE 221A-02
TO-220AB
MOTOROLA TMOS POWER MOSFET DATA
C,36
,.,
V
1.14
5.91
0.16
1.14
Z
-
2.03
-
0.080
IRF530·533/130·133
I
ELECTRICAL CHARACTERISTICS (TC =
25·C unless otherwise noted)
Symbol
Charactarlstlc
Min
Typ
Max
-
100
nAde
-100
nAde
-
4.0
Vdc
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS = 0, 10 = 250 ,..A)
V(BR)OSS
IRF130,132,530,532
IRF131,133,531,533
Zero Gate Voltage Drain Current
(VGS = 0 V, VOS = Rated VOSS)
(VGS = 0 V, VOS = 0.8 Rated VOSS, TC
100
60
lOSS
Forward Gate-Body Leakage Current
(VGS = 20 V, VOS = 0)
IGSSF
Reverse Gate-Body Leakage Current
(VGS = -20 V, VOS = 0)
IGSSR
-
VGS(th)
2.0
= 125·C)
Vdc
mAde
0.25
1.0
ON CHARACTERrsncs*
Gale Threshold Vollage
(VOS = VGS, 10 = 250 pAl
On-Stale Drain Currenl
(VOS = 25 V, VGS = 10 V)
10(on)
Slatic Drain-Source On-Resistance
(VGS = 10 V, 10 = 8.0 A)
4.0
-
-
-
-
-
14
12
IRF130,131 ,530,531
IRF132,133,532,533
rOS(on)
IRF130,131 ,530,531
IRF132,133,532,533
Forward Transconductance
(VOS = 15 V,IO = 8.0 A)
9fs
-
-
Ade
Ohm
0.18
0.25
-
mhos
800
pF
DYNAMIC CHARACTERISTICS
Inpul Capacilance
Ciss
Oulpul Capacilanee
= 25 V, VGS = 0, f = 1.0 MHz)
(VOS
Coss
Crss
Reverse Transfer Capacilanee
SwrrcHlNG CHARACTERISTICS* (TJ
=
500
150
100·C)
Turn-On Delay TIme
Idlon)
Rise Time
Ir
VOO = 36 V, 10 = 8.0 A
Zo = 150
Turn-Off Delay Time
Id(off)
Fall Time
If
-
30
ns
75
40
45
SOURCE DRAIN DIODE CHARACTERISTICS*
Characteristic
I
I
Forward On-Voltage
Reverse Recovery Time
(IS = Raled 10, VGS = 0)
Symbol
Typ
Unit
VSO
2.3
Vde
Irr
360
ns
·Pulse Test: Pulss Width", 300 p,S, Duty Cycle'" 2.0 %.
FIGURE 1 -
FIGURE 2 -
SWITCHING TEST CIRCUIT
V~~~
\
Idlon)
RJ.-:0UI
Pulse Generalor
r----------,
I
Rgen
I
I
I
I
I
OUT
OUlpUl, VOUI
Inverted
150
I
I
I _______ .JI
L
MOTOROLA TMOS POWER MOSFET DATA
C-37
SWITCHING WAVEFORMS
•
IRF610
IRF611
IRF612
IRF613
•
®
Advance Information
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TM.OS POWER FIELD EFFECT TRANSISTOR
MOTOROLA
Part Number
VDS
IRF610
200 V
150V
1.50
2.5A
IRF612
200 V
2.40
2.0 A
IRF613
150V
2.40
2.0 A
G
SOA is Power Dissipation Limited
D
S
• Source-to-Drain Diode Characterized fo~ Use With Inductive
Loads
Q
vW --6
-r
r~r1J
o
s
lr
1
F./~Ii
A . . .J
i
tu
-I-
TMOS
I
K!
S
-~
-1
0-
.-{=~
J
~:
II
-J
i--~
g~~~N
!:
~~~~~E
~f i A-A
I
G
-I
PIN
MAXIMUM RATINGS
IRF
Symbol
610
611
612
613
Unit
Drain-Source Voltage
VOSS
200
150
200
150
Vdc
Drain-Gate Voltage
(RGS·= 1.0 MO)
VOGR
200
150
200
150
Vdc
±20
VGS
Vdc
10
2.5
2.5
2.0
2.0
Adc
B
ID
1.5
1.5
1.25
1.25
Adc
C
D
IDM
10
10
8.0
8.0
Adc
Gata Current -
Pulsed
Total Power
Dissipation @ TC = 25·C
Derate above 25·C
Operating and Storage
Temperature Range
IGM
Adc
Watts
PD
20
0.16
WI"C
-55 to 150
·C
RWC
6.4
.C/W
TL
300
·C
TJ,Tstg
Maximum Lead Temp. for Soldering
Purposes, 118" from case for 5 seconds
F
G
H
J
K
L
N
n
R
S
T
THERMAL CHARACTERISTICS
Thermal Resiatance
Junction to Case
U
V
Z
MOTOROLA TMOS POWER MOSFET DATA
C-38
!~ L-r
l~1'
.
L
II~ '~LG
--l !-.
0
___ N
MILLIMETERS
INCHES
DIM MIN MAX
MIN MAX
A 15.11 15.75 0.595 0.620
Continuous Drain Current TC = loo·C
1.5
VI
--;;
NOTES,
1. DIMENSION H APPLIES TO ALL LEADS.
2. DIMENSIDN L APPLIES TD LEADS 1 AND 3 DNLY.
3. DIMENSION Z DEFINES A ZDNE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
4. DIMENSIDNING AND TDLERANCING PER ANSI
YI4.51973.
5. CONTROLLING DIMENSION, INCH.
Continuous Drain Current TC = 25·C
Drain Currant - Pulsed
1--;-J13"'
z t
STYLE 5. -
Gate-Source Voltage
ID
IRF611
• Silicon Gate for Fast Switching Speeds
Rating
2.5 A
IRF610
IRF611
IRF612
IRF613
These TMOS Power FETs are designed for low voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
• Rugged -
rDSlon)
1.50
9.65
4.06
0.64
3.61
2.41
2.79
0.36
12.70
1.14
4.B3
2.54
2.04
1.14
5.97
0.76
1.14
10.29
4.B2
0.B9
3.73
2.67
3.30
0.56
14.27
1.39
5.33
3.04
2.79
1.39
6.48
1.27
0.3BO
0.160
0.025
0.142
0.095
0.110
0.014
0.500
0.045
0.190
0.100
O.OBO
0.045
0.235
0.030
0.045
2.03
CASE 221A-02
TO-220AB
0.405
0.190
0.035
0.147
0.105
0.130
0.022
0.562
0.055
0.210
0.120
0.110
0.055
0.255
O.OSO
O.OBO
IRF610-613
I
ELECTRICAL CHARACTERISTICS (TC
= 25·C unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
-
0.25
1.0
-
100
nAdc
-
-100
nAdc
-
4.0
Vdc
-
-
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS = O. 10 = 250 !LA)
V(BR)OSS
IRF610.612
IRF611.613
200
150
Zero Gate Voltage Drain Current
(VGS = 0 V. VOS = Rated VOSS)
(VGS = 0 V. VOS = 0.8 Rated VOSS. TC = 125·C)
lOSS
Forward Gate-Body Leakage Current
(VGS = 20 V. VOS = 0)
IGSSF
Reverse Gate-Body Leakage Current
(VGS = -20 V. VOS = 0)
'GSSR
-
VGS(th)
2.0
-
Vdc
-
mAdc
ON CHARACTERISTICS·
Gate Threshold Voltage
(VOS = VGS. 10 = 250
!LA)
On-State Drain Current
(VOS = 25 V. VGS = 10 V)
'O(on)
IRF610.611
IRF612.613
Static Drain-Source On-Resistance
(VGS = 10 V. 10 = 1.25 A)
2.5
2.0
rOS(on)
IRF610.611
IRF612.613
Forward Transconductance
(VOS = 15 V.ID = 1.25 A)
-
-
9fs
0.8
Adc
Ohms
-
1.5
2.4
-
-
mhos
pF
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VOS = 25 V. VGS = O. f = 1.0 MHz)
Reverse Transfer Capacitance
=
SWITCHING CHARACTERISTICS· (TJ
VOO = 0.5 VOSS. 10
Zo = 50 {)
Turn-Off Delay Time
-
-
150
-
-
80
Crss
-
-
25
td(on)
-
-
25
-
15
-
15
100·C)
Turn-On Delay Time
Rise Time
Ciss
Coss
=
tr
1.25 A
td(off)
Fall TIme
tf
-
15
ns
SOURCE DRAIN DIODE CHARACTERISTICS·
Characteristic
Forward On-Voltage
Reverse Recovery Time
I
l
(Is
=
Rated '0. VGS
= 0)
Symbol
Typ
Unit
VSO
1.8
Vdc
trr
290
ns
·Puls. T.st: Puis. Width" 300 ,..s. Duty Cycl. " 2.0 %.
FIGURE 1 -
SWITCHING TEST CIRCUIT
VO~ ~
FIGURE 2 -
\
td(on)
R~out
OUT
Pulse Generator
Output. Vout
Inverted
50 {)
MOTOROLA TMOS POWER MOSFET DATA
C-39
SWITCHING WAVEFORMS
®
MeRIOOO
series
IIj
MOTOROLA
THYRISTORS
15 AMPERES RMS
200-400-600 VOLTS
ASYMMETRICAL
SILICON CONTROLLED RECTIFIERS
· .. designed primarily for very high speed switching. high current
pulse applications - laser modulators. printers. florescent lighting.
switching power supplies and particle accelerators.
• Asymmetrical Blocking Voltage To 600 V
• Very High dvldt - 1000 VII's @TJ= 125°C'
• Very Fast Switching - t q @TJ= 25°C. 8.0 I's Max
• Technology Leadership TMOS SCR
• For More Information See EB-103
MAXIMUM RATINGS
Symbol
Rating
Peak Forward Blocking Voltage
Value
MCR1000-4
MCR1000-6
MCR1000-B
Forward Current RMS (T C = 25°C)
(All Conduction Angles)
Unit
Volts
VORM
200
400
600
IT(RMS)
15
Amps
'TSM
90
Amps
,2t
34
A2s
Peak Gate Voltage
VGM
±20
Volts
Forward Peak Gate Current
IGM
1.5
Amps
Peak Forward Surge Current
(112 Cycle. Sine Wave. 60 Hz)
TJ= 125°C)
Circuit Fusing Considerations
(TJ = 0 to +125°C. t = 1.0 to B.3 ms)
Operating Junction Temperature Range
Storage Temperature Range
TJ
-Oto+125
°c
Tstg
-65 to +150
°c
Symbol
Max
Unit
R9JC
1.67
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance, Junction to Case
°C/W
STYLE 3:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
NOTES:
1. DIMENSIONS LAND H APPllESTO All LEADS.
2. DIMENSION Z DEFINESA ZONE WHERE All
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
3. DIMENSIONING AND TOlERANCING PER ANSI
YI4.51973.
4. CONTROlliNG DIMENSION; INCH
MILLIMETERS
DIM MIN MAX
A 15.11 15.75
B
9.6510.29
C 4.06
4.82
D 0.64
0.89
F
3.61
3.73
G 2.41
2.61
H
2.19
3.30
J
0.36
0.58
K
12.10
L
1.14
N
4.83
2.54
2.04
.14
5.91
0.18
1.14
Q
R
S
T
U
14.21
1.21
5.33
3.04
2.19
1.39
6.48
1.27
2.03
-
0.080
CASE 221 A-02
TO-220AB
MOTOROLA TMOS POWER MOSFET DATA
C-40
MCR1000 Series
ELECTRICAL CHARACTERISTICS (TJ = 25°C' unless otherwise noted.
Symbol
Min
Typ
Max
Unit
Peak Forward Blocking Current
(Rated VORM @ TJ = 125°C)
IORM
-
-
2.0
mA
Peak Reverse Blocking Current
(Rated VRRM @ TJ = 125°C)
'RRM
-
-
2.0
mA
Peak Reverse Blocking Voltage
VRRM
-
-
100
Volts
3.5
4.0
Volts
Characteristic
Forward "On" Voltage
(ITM = 20 A Peak)
VTM
Gate Trigger Voltage (Continuous dc)
(Anode Voltage = 12 Vdc, RL = 100 Ohms)
(Anode Voltage = Rated VORM, AL = 100 Ohms, TJ = 125°C)
-
2.0
2.5
0.2
-
-
Volts
Holding Current
(Anode Voltage = 12 Vdc)
'H
-
10
40
mA
Turn-On Time
(See Figure 6)
tgt
-
-
200
ns
Turn-Off Time (VORM = rated voltage)
(ITM = 3.0 A, 'R = 2.0 A, dv/dt = 100 V/~s)
tq
-
-
8.0
~s
Forward Voltage Application Rate
(TJ = 125°C, RGK';;; 200 O)(See Figure 7)
dv/dt
-
-
Maximum Rate of Change of On State Current
(Rated VORM, 'TM = 20 A peak, TJ = 125°C)
di/dt
130
~ 120
\..... ~ .........
~ 100
\~ ~
90
\
'" 80
;'l
""
:2
<.)
I-
~ :~
'-....
,\ \ :--."-.
70 - ] = ) 0 0
60
~o~-
Q=
i'-...
\\\\."
Conduttion'Angle-
i'--..
I'-.
6'00 90012\0150~
180°
50
'j
'r
6.0
8.0
"'-
40
o
2.0
4.0
10
12
de
i"
14
16
2.0
IT(AV), AVERAGE ON·STATE FORWARD CURRENT (AMPS)
~
'"~
w
""'"~
'"
>
4.0
6.0
8.0
10
12
14
16
'J(AV), AVERAGE ON·STATE FORWARD CURRENT (AMPS)
FIGURE 4 - TYPICAL HOLDING CURRENT
FIGURE 3 - TYPICAL GATE TRIGGER VOLTAGE
.,
A/~s
100
~-
~
110
x
-
-
V/~s
140
=>
:2
=>
:2
1000
I
FIGURE 2 - MAXIMUM ON-STATE POWER
DISSIPATION
FIGURE 1 - AVERAGE CURRENT DERATING
~
w
~
Volts
VGT
VGO
r
I
0
7.0
5.0
4.0
«
2.0
tz
E.
a
~
~
ffi 1.0
'" 0.1
'"z
!!1!
9c:>
I-
~
'",.:.
>'"
'"~
-60
20
-40
-20
20
40
60
80
TJ. JUNCTION TEMPERATURE (OC)
100
120
140
10
7. 0
~
-
5. 0
3. 0
-60
-40
-20
20
40
60
80
TJ. JUNCTION TEMPERATURE (0C)
MOTOROLA TMOS POWER MOSFET DATA
C-41
r-
100
120
140
MCR1000 Series
FIGURE 5 - THERMAL RESPONSE
1.0
0.7
0.5
'"z
'"
I;;
0.3
0;
II
0" 0.5
Ii!
~C
"'~
~~
"'~
~'"
:~
....
0.2
-
0.2
r-
0;
0.1
ROJc(11 " ,(II ROJC
ROJC 1.6JOC/W Max
o curves apply for power
",
!Z
~ 0.07 F-OD5
~ -
0.05
~
0.03
.".
0.02
z
~
f--- 0.02
Pulse train shown
Read time at 11
~
TJ(pkl - TC " P(pkl ROJc(11
.....r-1
0.01
0.01
0.02
0.05
0.1
0.2
0.5
10
2.0
1.0
5.0
t. TIME (msl
20
50
100
500
200
FIGURE 5 - MCR1000 SERIES TYPICAL TURN-ON CIRCUIT
WITH CMOS GATING
10%
Anode Voltage
Gate
Delay
-::::l
Rise
Time
I
Time
r
I
;.IO__---Turn-Dn---..:
Trigger I
Time
I
pUlsejt
10%JL 50%
:
: 00---...
\50%
Gate Puis. Width
FIGURE 7 - TYPICAL dv/dt CAPABILITY
1000
Static dv/dt Capability as a Function of
Gate-Cathode Resistance
Il'.
VDR
'"cl
E
dv/dt
150V
J!Lov
RGK
~
1. 0
100
500 lK
5K 10K
RGK. GATE-CATHODE RESISTANCE (0)
50K
MOTOROLA TMOS POWER MOSFET DATA
C-42
-----.-ii
lk
®
MGM20N4S
MGM20NSO
MGP20N4S
MGP20NSO
MOTOROLA
Designer's Data Sheet
.
20 AMPERE
N-CHANNEL TMOS
GEMFET
N-CHANNEL ENHANCEMENT MODE SILICON GATE.
GAIN ENHANCED MOS FIELD EFFECT TRANSISTOR
fDSlon) = 0.27 Ohm
450 and 500 Volts
These GEMFETS are designed for high voltage. high current
power controls such as line operated motor controls and
converters.
MGM20N45
MGM20N50
• High Input Impedance
• Low On-Voltage. 2.7 V max @ 10 A
• High Peak Current Capability -
30 A
• Voltage Driven Device
,r
STYLE 3
PIN 1. GATE
2. SOURCE
CASE DRAIN
TMDS
TO-2D4AA
CASE 1-05
(TOol TYPE)
MAXIMUM RATINGS
Symbol
MGM20N45
MGP20N45
MGM20N50
MGP20N50
Unit
Drain-Source Voltage
VOSS
450
500
Vdc
Drain-Gate Voltage
(RGS = 1.0 Mn)
VOGR
450
500
Vdc
Rating
Gate-Source Voltage
Drain Current
Continuous
Pulsed
Gate Current -
VGS
±20
Vdc
Adc
Pulsed
Total Power
Dissipation @TC = 25°C
Derate above 25°C
Operating and Storage
Temperature Range
10
10M
20
30
IGM
1.5
MGP20N45
MGP20N50
Adc
Watts
Po
100
0.8
wrc
TJ, Tstg
-65to 150
°c
Rruc
1.25
°CIW
TL
275
°C
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Maximum Lead Temp. for
Soldering Purposes, 1/8'
from case for 5 seconds
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
Designer's Data fOf "Worst Case" Conditions
The Designer's Data Sheet permits the design of most circuits entirely
from the information presented. Limit curves - representing boundaries
on device characteristics - are given to facilitate "worst case" design.
CASE 221A-G2
TO-220AB
MOTOROLA TMOS POWER MOSFET DATA
C-43
MGM/MGP20N45, 50
I
ELECTRICAL CHARACTERISt.ICS
(TC = 250C unless otherwise noted)
Symbol
Ch.r.cterfatlc
Min
Max
450
500
-
Unit
OFF CHARACTERISTICS
Orein sOurce Breakdown Voltage
(VGS =0; 10":=5.0 mAl
V(BR)OSS
MGM20N45, MGP20N45
MGM20N50, MGP20N50
Zero Gate Voltage Orain Current
NOS = 0.85 Rated VOSS, VGS = 0)
TJ = l00'C
lOSS
Gate-Body LeekageCurrent
(VGS = 20 Vdc, VOS = 0)
IGSS
-.
-
Vdc
mAdc
0.25
2.5
500
nAdc
ON CHARACTERIS11CS*
Gate Threshold Voltage
(10 = 1.0 mA, VOS = VGS)
TJ = l000C
VGS(th)
Drain-Source On-Voltage
(10 = 10 Adc, VGS = 10 V)
(10 = 20 Adc, VGS = 15 V)
(10 = 10 Adc, VGS = 10 V, TJ = l00'C)
VOS(on)
Static Orain-Source On-Resistance
(VGS = 10 Vdc, 10 = 10 Adc)
Vdc
2.0
1.5
Forward Transconductance
(VOS = 10V, 10 = lOA)
4.5
4.0
Vdc
rOS(on)
-
0.27
Ohms
9fs
3.0
-
mhos
950
pF
150
pF
60
pF
0.075
/LS
0.150
/LS
2.7
5.0
3.0
DYNAMIC CHARACTERISTICS
Input Capacitance
Ciss
Output Capacitance
(VOS
= 25 V, VGS
= 0, f = 1.0 MHz)
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS·
Coss
Crss
-
(TJ = 100'C)
RESISTIVE SWITCHING
Turn-On Oelay Time
tr
-
ldloff)
-
4.0
/LS
tf
-
B.O
/LS
4.0
/LS
6.0
/LS
9.5
/LS
9.5
/LS
td(on)
IVOS = 250 V, 10 = 20 A,
RG = 1.0 kil,
Vin = 15 V)
Rise Time
Turn-Off Oelay Time
FaJi TIme
INDUCTIVE SWITCHING
Turn-Off Delay Time
(Vclamp = 250 V,
10M = 20 A, L = 180 .,.H,
Vin=15V)
Crossover TIme
Turn-Off Oelay Time
RG = 1.0 kil
Idloff)
Ie
RG = 4.0 kil
ldloff)
Crossover Time
Ie
-
'Pulse Test: Pulse Width .. 300 I'S, Duty Cycle .. 2.0%.
RESISTIVE SWITCHING
FIGURE 1 -
Pulsa Generator
r- -Rge" - - --:
:
50n:
I
:
I
FIGURE 2 -
SWITCHING TEST CIRCUIT
SWITCHING WAVEFORMS
Output, Vout
Inverted
I
rL _______ .JI
MOTOROLA TMOS POWER MOSFET DATA
C-44
MGM/MGP20N45, 50
TYPICAL ELECTRICAL CHARACTERISTICS
FIGURE 3 - OUTPUT CHARACTERISTICS
FIGURE 4 - ON-REGION CHARACTERISTiCS
40
40
-
TJ ='25°C
i
!Z
~
az:
~
I-vJs = l1v
~ 32 f--
I
32
~
!Z
16 v
24
az
8.0 V
~
24
16
o
50
100
150
200
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
250
1
8.0 V
I
/I . /
£! 8.0
1
o
16v- I---
I. ~
J' , /
'/
6.0 V
o
I
./
b
o
1
£! 8.0
V
,
T~ = 25!C
ll'
0:
1
16
, 40 7 14V- r-v~s = l L - f-:-
//
6.0 V
~
I
o
FIGURE 5 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
2.0
4.0
6.0
8.0
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
FIGURE 6 - TRANSFER CHARACTERISTICS
o
~ 1.4
~
o
VDS = VGS
10 = 1.0mA-
r-....
~
~
1.0
9
~
~
:--.....
~
;--......
0.8
25
50
75
100
TJ. JUNCTION TEMPERATURE (OCI
150
~
~
Iii
0.5
II
)
~
o U
~
g
1000
j
u
"-
z
I"
0.2
~
§o
--
::::,...
~0.1
o U
M
M
W
U
M
m m
~
FIGURE 8 - CAPACITANCE VARIATION
~
0.3
W
IL
VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)
VG~ = lJV
\
ll!
'//
1250
1\
0.4
q.. -100"C
II
d
125
/ /L
(h
fA
IA
FIGURE 7 - ON-RESISTANCE versus'
DRAIN CURRENT
§
25"C.,4
16
o
o
-25
c-V~S = Jov
- 8.0
~
~50
TJ = -55"C_
~
az
............
~ 0.6
~
_ 32
~ 24
~
!
r--
~
i!O 12
!ll
. ............
10
W
M
M
W
U
TJ
...~
l00"C-
u
25°C 10
M
1_
250
~
,....,
Ciss
'\........
Coss
5
10
15
20
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTSI
MOTOROLA TMOS POWER MOSFET DATA
C-45
--
~
o Crss
o
'0. DRAIN CURRENT (AMPS)
TJ ~ 2sod _
VGS = 0
f = 1.0 MHz-
500
u
- 55
m m
750
\
\
25
MGM/MGP20N45, 50
FIGURE 9 - MAXIMUM RATED FORWARD BIAS
SAFE OPERATING AREA
50
30
20
ie
•
40
tOms
5.0
z , 3.0
l!i
2.0
a::
~
ie 32
de
I'-..
~
~
!Z 24
ii§
0
lOOms
~roslonl.Limit ----1.0 ~ ~ermal Umit
...,
1.0 p.s
ITTTr
10
~
I-
FIGURE 10 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
az 16
z
F= Psekage limit
~
0.50
0
0.30
9
0.20 I-TC = 25'C
I--VGS = 15 V
MGM2ON45
0.10
gSingle Pulse
MGM2ON50
0.05
1.0
10
100
0.1
VDS, DRAlN·TO·SOURCE VOLTAGE (VOLTSI
-
~
9
25
1000
::::---. f-Vd = 250V
-....;::: ~
Vd= RatedVDSS!- '---"
VGS = 15V
RG = 4.0kn
Single Pulse
TJ "'15O'C
75
100
TC, CASE TEMPERATURE I'CI
50
125
-....
150
FORWARD BI,ASED SAFE OPERATING AREA
SWITCHING SAFE OPERATING AREA
The dc data of Figure 9 is based on a case temperature (Te) of 25'C and a maximum junction temperature
(TJmax) of 150'. The actual junction temperature de·
pends on the power dissipated in the device and its
case temperature. For various pulse widths, duty cycles,
and case temperatures, the peak allowable drain current
(10M) may be calculated with the aid of the following
equation:
The switching safe operating area (SSOA) of a GEMFET device is a composite function of gate turn-off time,
inductive clamp voltage (Vcl) and device junction temperature (TJ). Figure 10 illustrates that 10 is 30 A for Vcl
.. 250 V and TJ .. 87.5'C, and for Vcl .. 500 V and TJ
.. 62.5'C. Additionally, it is seen that for a peak drain
current of 24 A, TJ must be maintained less than 118'C
for Vel = 250 V, and less than 106'C for Vcl = 500 V,
TJ may be calculated from the equation:
TJ = TC
= 10(25'C)[TJ(maXI - TC]
Po . ReJC . r(t)
+
Po·Rruc·r(t)
where
Po is the power averaged over a complete switching
cycle.
Generally, SSOA current declines with decreasing
gate turn-off time, Gate turn-off time is controlled by
RG; lowering RG decreases gate turn-off time. A !lug'
gested rule-of-thumb is to derate the 10 of Figure Hi by
2.5 A for every 1100 ohms of RG below 4.0 kG for case
temperatures greater than 55'C.
where
10(25'C) = the dc drain current at TC = 25'C from
Figure 9·
TJ(max)= rated maximum junction temperature
TC
= device case temperature
Po
= rated power dissipation at TC = 25'C
RruC
= rated steady state thermal resistance
r(t)
= normalized thermal response from Figure 11
FIGURE 11- THERMAL RESPONSE
1.0
I-
D - 0.5
~ 0.5
o.~
15:::; 0.3
~n~ 0.2
~iii
~~
0.1
~ii~O.05
I:ti
~iO.03
ffi
F O.02
~
~
0.01
0.01
--
0.02
;::;;0-"
I-
0.02
.....
~~
-
0.1
0.05
~
DUTY CYCLE, D
0.01
Stgi
0.05
e
1m
0.1
0.2
0.5
1.0
R8JCltl rttl R8JC
R8JC 1.25'c,w Max
DCURVES APPLY FOR POWER
, PULSE TRAIN SHOWN
READ TIME AT '1
TJlpkl- TC Plpkl R8JCltl
tIUl
1"'1""
Ie:'
Plpkl
2.0
~
5.0
TIME Imol
II
10
20
MOTOROLA TMOS POWER MOSFET DATA
C-46
tllt2
50
If II
100
200
II
500
1000
®
MTASN12
MTASN1S
MTA4N18
MTA4N20
MOTOROLA
Designer's Data Sheet
4.0 and 5.0 AMPERE
N-CHANNEL TMOS
POWER FETs
rDSlon) = 0_9 OHM
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
120 and 150 VOLTS
rDSlon) = 1_2 OHM
180 and 200 VOLTS
These TMOS Power FETs are designed for low voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds - Switching Times
Specified at 100°C
• Designer's Data - lOSS, VDS(on), VGS(th) and SOA
Specified at Elevated Temperature
• Rugged - SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
Loads
,r
Go----->.{
TMOS
S
MAXIMUM RATINGS
~H
MTA
Rating
Drain-Source Voltage
VOSS
120
150
180
200
Vdc
Drain-Gate Voltage
(RGS = 1.0 Mil)
VDGR
120
150
180
200
Vdc
Gate-Source Voltage
Drain Current
Continuous
Pulsed
Gate Cu rrent -
K
Symbol 5N12 5N15 4N18 4N20 Unit
",20
VGS
Vdc
Adc
10
10M
Pu Ised
Total Power
Dissipation @TC = 25°C
Derate above 25°C
Operating and Storage
Temperature Range
IGM
5.0
10
4.0
8.0
1.5
Watts
Po
30
0.32
wrc
TJ,Tstg
-65 to 150
°c
RWC
3.12
°CIW
~
lL
275
°c
J
K
M
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Maximum Lead Temp. for Soldllring
Purposes, 1/8" from case for 5 seconds
STYLE 9:
PIN I. GATE
2. DRAIN
3. SOURCE
Adc
MILLIMETERS
DIM MIN MAX
A 10.80 11.05
7.49
7.75
B
C
2.41
2.67
D 0.51
0.66
F
2.92
3.18
Q
Designer's Data for "Worst Case" Conditions
The Designer's Data Sheet permits the design of most circuits entirely from
the information presented. Limit data - representing device characteristics
boundaries - are given to facilitate "worst case" design.
MOTOROLA TMOS POWER MOSFET DATA
C-47
R
S
U
V
U;
0.38
15.11
INCHES
MIN MAX
0.425 0.4 5
0.295
0.095
0.020
0.115
~::~ ~~:'
0.64
16.64
3TYP
3.18
4.01
1.14
1.40
OM
0.89
3.68 3.94
1.02
f-
0.015P
0.595
JOT
0.148 0.158
0.045 0.055
0.025 0.035
0.145 0.155
0.040-
CASE 77-04
•
MTA5N12, 15/4N18, 20
I
ELECTRICAL CHARACTERISTICS (TC = 25'C unless otherwise noted)
Symbol
Characterilltlc
Min
Max
120
150
180
200
7"
-
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS = 0,10 = 5.0 mAl
•
VBR(OSS)
MTA5N12
MTA5N15
MTA4N18
MTA4N20
Zero Gate Voltage Drain Current
(VOSS = 0.85 Rated VOSS, VGS = 0)
TC = 1OO'C
lOSS
Gate-Bodv Leakage Current
(VGS = 20 Vdc, VOS = 0)
IGSS
-
Vdc
mAde
0.25
2.5
500
nAdc
ON CHARACTERISTICS"
Gate Threshold Voltage
(10 = 1.0 mA, VOS = VGS)
TJ=IOO'C
Static Drain-Source On-Resistance
(VGS = 10 Vdc, 10 = 2.5 Adc)
(VGS = 10 Vdc, 10 = 2.0 Adc)
2.0
1.5
rOS(on)
MTA5NI21MTA5NI5
MTA4N 1BlMTA4N20
Drain-Source On-Voltage (VGS = 10 V)
MTA5N12/MTA5NI5
(10 = 5.0 Adc)
MTA5NI21MTA5NI5
(10 = 2.5 Adc, TJ= 100'C)
MTA4N1B1MTA4N20
(10 = 4.0 Adc)
MTA4NI8/MTA4N20
(10 = 2.0 Adc, TC = lOO'C)
Forward Transconductance
(VOS = 16 V, 10 = 2.5 A)
NOS = 15 V, 10 = 2.0 A)
Vdc
VGS(th)
VOS(on)
-
Ohm
0.9
1.2
Vdc
6.4
4.5
6.0
4.8
mhos
9fs
0.75
0.75
MTA5NI2IMTA5NI5
MTA4NI8/MTA4N20
4.5
4.0
-
-
DYNAMIC CHARACTERISTICS
Input Capacitance
(VOS = 25 V, VGS = 0
f = 1.0 MHz)
Output Capacilance
Reverse Transfer Capacitance
Ciss
-
250
Coss
-
100
Crss
-
40
Idlon)
-
20
tr
-
20
td(off)
-
50
tf
-
50
Symbol
Typ
Unit
VSD
2.0
Vdc
Ion
150
ns
Irr
250
ns
pF
SWITCHING CHARACTERISTICS" (TJ = 100'C)
Turn-On Oelav Time
(VOO = 25 V, 10 = 0.5 Rated ID,
Rgen = 50 ohms)
See Figures 1 and 2
Rise Tillie
Turn-Off Delav Time
Fall Time
ns
SOURCE-DRAIN DIODE CHARACTERISTICS"
Characterilltic
Forward On-Voltage
IS = Rated 10
VGS = 0
See Figures 16 and 17
Forward Turn-On Time
Reverse Recovery Time
'Pulse Test: Pulse Width", 300 ps, Duty Cycle'" 2.0%.
RESISTIVE SWITCHING
FIGURE 1 -
SWITCHING TEST CIRCUIT
VO~ ~
FIGURE 2 - SWITCHING WAVEFORMS
\
R~out
OUT
Output, Vout
Inverted
50n
MOTOROLA TMOS POWER MOSFET DATA
C-48
MTA5N12, 15/4N18, 20
TYPICAL CHARACTERISTICS
MTA5N12. MTA5N15
FIGURE 3 -
vGi
~ 6.0
/'
W
A v:
'"
a
z 4.0
~
~ 20~
/-'"
,
o
/
1
i
7.0 V
~
6,0 V
.9 1.0
5.0 V
I
U
"
o
10
II
~
I
-55'C
25'C
.Y
V lOO'C
Q
~
1.0
25!C
0.75
Z
I
a
~
~ O.SO
-
-55!C
~"" 0.25
,./
V
----
--VGS
~
~
e
0
2.0
~
10 V
V//
4.0
6.0
8.0
10
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS!
12
FIGURE 8 - ON-RESISTANCE versus DRAIN CURRENT
~ 2.0
"
..... ,...,
:I:
r
Q
-
r-T)~ 100le
w
V
6
u;
~
1.2
25'C
1§
~
0.8
~
r-
eu;
10
0
0
1.0
2.0
3.0
10, DRAIN CURRENT (AMPS)
MOTOROLA TMOS POWER MOSFET DATA
C-49
-- -
V
/
-
VGS = 10 V
Z 0.4
~
8.0
----
-I--
1c
55
~
10 V
4.0
6.0
ID, DRAIN CURRENT (AMPS!
VOS
/ / '/'
2.0
'"o
0
/ V
1//
V
/ II
o
:5
u;
J
.9 1.0
12
1/25'C /l00'C
~
~
'"
.".'"
~
u;
~
lOolC
20
J /
z 2.0
4.0
6.0
8.0
10
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
-..:::r:-
-55'cll
'"
=>
u
VDS~10V
../ / . ' /
r- TJ 1-
~
~ 3.0
FIGURE 7 - ON-RESISTANCE versus
DRAIN CURRENT
iii 1.25
::;;
TJ
~
'/ /
2.0
4.0
8.0
12
16
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS!
_ 4.0
le
J
o
5.0 V
5.0
I /
11//
I, V
/ n
II
r
FIGURE 6 - TRANSFER CHARACTERISTICS
FIGURE 5 - TRANSFER CHARACTERISTICS
TJ
6.0V
o
2.0
4.0
6.0
8.0
VDS, DRAIN-TO-SDURCE VDLTAGE (VOLTS!
5.0
7.0 V
_ 4.0
le
8.0 V
~~
~
o
-VG~~20~ / VlOV
-I
1// V
'(//
TJ = 25'1
~
V
3.0
//
az 2.0 1///
f--'"
9.0 V
~~
.9 2.0
--
5.0
10 V
-T~ ~ 25lC
~
FIGURE 4 - ON-REGION CHARACTERISTICS
ON-REGION CHARACTERISTICS
10
_ 8.0
le
MTA4N18. MTA4N20
4.0
5.0
MTA5N12, 15/4N18, 20
TYPICAL CHARACTERISTICS
FIGURE 9 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
o
FIGURE 10 ~. CAPACITANCE VARIATION
1.2
:s~
500
...........
1.1
;;
""" "'"
~
'"~
1.0
~
9
~
I
VDS ~ VGS
0.90
i
~
'"
~ 300
~
~
~
il! 0.80
~
~ 200
,<,$
r-....
r-....
~
~ 0.70
,J;
-50
-25
I
TJ ~ 25°C - f-VGS ~ OV
f ~ 1.0MH,- f - -
400
ID~I.OmA
o
25
50
75
100
TJ, JUNCTION TEMPERATURE (OCI
125
100
.......
o
150
f\ ....
\
\
"-
Ciss
~
Coss
Crss....
o
10
20
30
40
VDS, DRAIN·TO·SOURCE VOLTAGE (VOLTSI
50
FIGURE 11 - THERMAL RESPONSE
MTA5N12. MTA5N15, MTA4N18, MTA4N20
1.0
_ 0.7 =0
~ 0.5
!z
~
!
u
:z
~
.9
"
"
-
I
!
10 JLS
"'-
I
-_.
"'"
~
"-
~
~/
ffi./
~ms
tOms
I'\.
'\~Nll~
~ 1.0~~~~~~~~~~~~~~~~~!f~
r-, -,
-rOS(onl Umit = =dc
Package Umit
ThermalUmit
I
MTA4N18. MTA4N20
10 JLS
1
mg.
• 0_m a m
100!,s
100 JLS
~Ims
I'\.
=---=
-
_
0
- -
-- ,
FIGURE 13 -
MTA5N12. MTA5N15
~
~----
rOS(onl Umit
PackageUmit _ _ dc
.Th,ermal Limit
"
-VGS = 2ov'-+I++I++
111-+-H-t-t+l'It-r--..."H-++++++++
f-.
<
2
z
.P>
S
DIODE SWITCHING WAVEFORM
10%
t
/
1-7
1/
"""i\
I
- .j Ion
~
LI\ dl
/
\
.-
\1-- 1, , -H
IRM{RECI
V
A" ~
25%
IRj{RECI
tIme
FIGURE 17 -
TMOS DIODE SWITCHING
TEST CIRCUIT
VCC
+ 15 V
L
= 100"H. 30 A
(2.200 "H. 15 A Inductors
in Parallel)
J. W. MILLER: 07828
270 K
R1: Duty Cycle
Control
f~2SkHz
OUT
DRIVER
To Set D-S Diode Current IS.
Adjust R1 andlor V CC
-V .. s.OV
NOTE: OUT 'is Shown as an N-Channel TMOS but can also be
a P-Channel when appropriately connected. OUT
Driver is the same device as OUT Diode (or Complement for P-Channel OUT Diode)
.
MOTOROLA TMOS POWER MOSFET DATA
C-52
MTA6N08
MTA6N10
MTA7NOS
MTA7N06
@ MOTOROLA
Designer's Data Sh(>pt
6.0 and 7.0 AMPERE
N-CHANNEL TMOS
POWER FETs
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
'DS(on) = 0.6 OHM
80 and 100 VOLTS
These TMOS Power FETs are designed for low voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds Specified at 100°C
'DS(on) = 0.4 OHM
50 and 60 VOLTS
Switching Times
• Designer's Data - lOSS, VDS(on), VGS(th) and SOA
Specified at Elevated Temperature
• Rugged - SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
Loads
S
,r
Go----->..i
TMOS
S
MAXIMUM RATINGS
~H
MTA
Rating
Drain-Source Voltage
VOSS
50
60
80
100
Vdc
Drain-Gate Voltage
(RGS = 1.0 MOl
VDGR
SO
60
80
100
Vdc
Gate-Source Voltage
Drain Current
Continuous
Pulsed
Gate Current -
K
Symbol 7NOS 7N06 6NOB 6N10 Unit
±20
VGS
Vdc
Adc
10
10M
Pulsed
Total Power
Dissipation @ TC = 2SoC
Derate above 25°C
Operating and Storage
Temperature Range
IGM
7.0
14
6.0
12
1.5
Adc
Watts
Po
30
0.32
wrc
TJ,Tstg
-65 to 1S0
°C
R8JC
3.12
0c/w
Tt
27S
°C
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Maximum lead Temp. for Soldering
Purposes, 1/8" from case for 5 seconds
Designer's Data for "Worst Case" Conditions
The Designer's Data Sheet permits the design of most circuits entirely from
the information presented. limit data - representing device characteristics
boundaries - are given to facilitate "worst case" design.
MOTOROLA TMOS POWER MOSFET DATA
C-53
STYLE 9:
PIN 1. GATE
2. DRAIN
3. SOURCE
MILLIMETERS
DIM MIN MAX
A 10.80 11.05
B
7.49
7.75
2.41
2.67
C
0.51
0.66
0
2.92
F
3.18
2.31
2.46
G
1.27
2.41
H
J
0.38
0.64
K 15.11 16.64
30 TYP
M
Q
4.01
3.76
R
1.14
1.40
S
O. 4 0.89
U
3.68 3.94
V
1.02
-
INCHES
MIN MAX
0.425 0.435
0.295 0.305
0.095 0.105
0.020 0.026
0.115 0.125
0.091 0.097
0.050 0.095
0.015 0.025
0.595 0.655
30 TYP
0:148 0.158
0.045 0.055
O. 12~ 0.035
0.145 0.155
0.040
CASE 77-04
-
MTA6N08, 1017N05, 06
I
ELECTRICAL CHARACTERISTICS (TC = 25'C unless otherwise noted)
Symbol
Characteristic
Min
Max
50
60
BO
100
-
Unit
OFF CHARACTERISTICS
Drain-Source. Breakdown Voltage
(VGS = 0, ID = 5.0 rnA)
II
VBR(DSS)
MTA7N05
MTA7N06
MTA6NOB
MTA6Nl0
Zero Gate Voltage Drain Current
(VDSS = 0.B5 Rated VDSS, VGS
TC = l00'C
.'
IDSS
= 0)
Gate-Body Leakage Current
(VGS = 20 Vdc, VDS = 0)
-
IGSS
Vdc
mAde
0.25
2.5
500
nAdc
ON CHARACTERISTICS"
Gate Threshold Voltage
(lD = 1.0 rnA, VDS = VGS)
TJ = 100'C
2.0
1.6
Static Drain-Source On-Resistance
(VGS = 10 Vdc, ID = 3.5 Adc)
(VGS = 10 Vdc, ID = 3.0 Adc)
Drain-Source On-Voltage (VGS
(lD = 7.0 Adc)
(lD = 3.5 Adc, TJ = 100'C)
(lD = 6.0 Adc)
(lD = 3.0 Adc, TC = l00'C)
Vdc
VGS(th)
=
rDS(on)
-
MTA7N05/MTA7N06
MTA6NOB/MTA6Nl0
-
10 V)
VDS(on)
-
MTA7N05/MTA7N06
MTA7N05/MTA7N06
MTAGNOS/MTA6Nl0
MTA6NOS/MTA6Nl0
Forward Transconductance
(VDS = 15 V, ID = 3.5 A)
(VDS = 15 V, ID = 3.0 A)
Ohm
0.4
0.6
Vdc
-
3.4
2.B
4.5
3.6
1.0
1.0
-
-
300
9fs
MTA7N051MTA7N06
MTA6NOSIMTA6Nl0
4.5
4.0
mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS
Output Capacitance
= 25 V, VGS
f = 1.0 MHz)
Ciss
=0
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS" (TJ
=
Crss
-
td(on)
-
25
tr
-
25
td(off)
-
50
tf
-
50
Coss
pF
160
50
100'C)
Turn-On Delay Time
(VDD = 25 V, ID = 0.5 Rated ID,
Rgen = 50 ohms)
See Figures 1 and 2
Rise Time
Turn-Off Delay Time
Fall Time
ns
SOURCE-DRAIN DIODE CHARACTERISTICS"
Characteristic
Forward On-Voltage
IS = Rated ID
VGS = 0
Forward Turn-On Time
Reverse Recovery Time
·Pulse Test: Pulse Width",," 300 p.s, Duty Cycle
:!6;
Symbol
Typ
Unit
VSD
1.5
Vdc
tan
150
ns
trr
250
ns
2.0%.
RESISTIVE SWITCHING
FIGURE 1 -
SWITCHING TEST CIRCUIT
FIGURE 2 -
SWITCHING WAVEFORMS
Output, Vout
Inverted
MOTOROLA TMOS POWER MOSFET DATA
C-S4
MTA6N08, 10/7N05, 06
TYPICAL CHARACTERISTICS
MTA7N05, MTA7N06
MTA6N08, MTA6N10
FIGURE 3 - ON-REGION CHARACTERISTICS
10
-
r-VGr
~ 8.0
~
/./
/. V ...........
TJ ~ 25°C /
~ 6.0
6
710V- -
i
6.0 V
u
6
I
V/
Ih
VDS~10V
~ 6.0
~
~
4.0
~
/'
./
TJ ~ -55°C
B.O
!z
100°C
VDS
~ 6.0
..5
~
4.0
/
.9
2.0
~ 0.5
2.0
10
~ 0.4
::g 0.3
25°C
~
~ 0.2
~
I---"'
-
....
~
z
o
0,6
,.-
-
..TJ
·joooc
L_
I
~
~
~ 0.4
VGS
~
C'
0
2.0
4.0
6.0
ID, DRAIN CURRENT lAMPS)
B.O
~
10
I
I
0
0
2.0
MOTOROLA TMOS POWER MOSFET DATA
C-55
~
./
V
.
I-- I---'
..-
/'
I--"'"
/"
...........
!----
-55°C
~ 02
10V
0
25°C
I
Cl
~
Cl
[!§
gl
12
4.0
6.0
B.O
10
VGS, GATE·TO·SOURCE VOLTAGE IVOLTS)
I
~ 0.8
;'!:
i..--'"
55°C
0.1
.L
......-:: ~
§
o
~
z
25°C/
~ If
~ 1.0
./
I-'"""'""
100°C
Ul
Z
o
V
I
FIGURE 8 - ON-RESISTANCE versus
DRAIN CURRENT
-
:I:
~
10
1--"'"..-,,:: ~
?::: ;../'
FIGURE 7 - ON-RESISTANCE versus
DRAIN CURRENT
TJ
I
I / ./
1/ . / 100°C
V
10 V
z
2.0
4.0
6.0
B.O
VGS, GATE·TO·SOURCE VOLTAGE IVOLTS)
Q
w
~
u
IV'
~V
o
o
2.0
4.0
6.0
B.O
VDS, DRAIN·TO·SOURCE VOLTAGE IVOLTS)
FIGURE 6 - TRANSFER CHARACTERISTICS
/7/
.9 2.0
6.0 V
5.0V
10
I~ V
'"
7.0 V
J.~
~
o
/'
25°C/
~
B.O V
II#.. V
FIGURE 5 - TRANSFER CHARACTERISTICS
~
g.OV
V/
I/, V
2.0
5.0
1.0
2.0
3.0
4.0
VDS, DRAIN·TQ·SOURCE VOLTAGE IVOLTS)
_ B.O
1//V
25°C
oI#'
I
I
~
TJ
6.0
4.0 V
TJ ~ -WC
10 V
I V
~ 4.0
-
L'"
J
=>
5.0V
10
~ 20V ~'2~
I - - VGS
~ 8.0
::;;
$
I
'rK
o
o
-
~
I. ~
'I.V
~
FIGURE 4 - ON-REGION CHARACTERISTICS
10
-~OV- -
V ~
/1/# Y___ r-
'"
a
;;; 4.0
- 2.0
/
~ 2J~ ~1~ ............
g.o V
VGS~10V
4.0
6.0
ID' DRAIN CURRENT lAMPS)
B.O
10
MTA6N08, 10/7N05, 06
TYPICAL CHARACTERISTICS
FIGURE 9 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
a
FIGURE 10 - CAPACITANCE VARIATION
soo
1.2
~~
..........
"
1.1
~
~
1.0
~
9
~
VDS = VGS
10 = 1.0 mA
\
[\\
~ 300
...........
l!l
::<:
"'-
~ 0.80
~
-50
o
-25
~
1!:.
200
()
I'-..
25
50
75
100
TJ, JUNCTION TEMPERATURE lOCI
U
i'....
125
.......
f
= 25°C
= 1.0 MHz
\.\
z
5
['....
~ 0.70
TJ
~
...........
0.90
~
~
400
1\
\
100
Ciss
" .......
Coss
.1
'-....
erss
o
o
150
10
20
30
40
VDS, DRAIN·TO·SOURCE VOLTAGE IVOLTSI
50
FIGURE 11 - THERMAL RESPONSE
1.0
_ 0.7 r=D
~ 0.5
!Z
~
-55"C
TJ = 100'C
25,J
0.04
~
~ 0.02
= 10V
20
VGS - 10V
~~ 0.06
= l00'C
25,J
VGS
0.08
55'C
I
Q
40
60
10. DRAIN CURRENT (AMPS)
80
100
I
0
o
20
40
60
10. DRAIN CURRENT (AMPS)
MOTOROLA TMOS POWER MOSFET DATA
C-60
BO
100
MTE60N18, 20/65N12, 15
TYPICAL CHARACTERISTICS
FIGURE 7 - GATE-THRESHOLD VOLTAGE
VARlAnON WITH TEMPERATURE
§
~
1.1
VOS
0.90
~
0.80
"""
,",-
~
\
i'....
t'.....
"I'-..
10:70
>
7 50
-25
f
I\.
~
;a
TJ = '25"C r-= 1.0 MHz
VGS = 0 r--
8000
~
1.0
~
~
'"
'"
lI!
=VGS
10 =1.0 mA
~
~
::b
CAPACITANCE VARIATION
1.2
~
i
FIGURE 8 -
25
50
75
100
\
125
1\
150
- -~
2000
........,
'Ciss
o ......
o
Coss
Crss
W
20
~
~
VOS. ORAIN·TO-SOURCE VOLTAGE (VOLTS)
TJ. JUNCTION TEMPERATURE 1°C)
50
TMOS SOURCE-TO-DRAIN DIODE CHARACTERISTICS
In the fabrication of a TMOS FET. a diode is formed
across the source-to-drain terminals as shown in Figure
9. Reversal of the drain voltage will cause current flow
in the reverse direction. This diode may be used in circuits requiring external fast recovery diodes. therefore.
typical characteristics of the on voltage. forward turnon and reverse recovery times are given.
FIGURE 10 -
FIGURE 9 - TMOS FET WITH
SOURCE-TO-DRAIN DIODE
Is
0
~ ~
.6
Lt\..dt
L
L
4
\
10% !-
-
GO----.l.,!
"\
90% !-7
.8
2
DIODE SWITCHING WAVEFORM
\r--- trr - tj
A"~
IRM{REC)~ ,
ton
IRM(REC)
tIme
s
VCC
+15V
FIGURE 11- DIODE SWITCHING TEST CIRCUIT
L = 100ItH, 30 A
(2,200 ItH, 15 A Inductors
In Parallel)
J. W. MILLER: 07828
270 K
R,: Duty Cycle
Control
f=25kHz
OUT
DRIVER
To Set D-S Diode Current IS.
Adjust R, and/or VCC
-V", 5.0 V
NOTE: OUT is Shown as an N-Channel TMOS but can also be
a P-Channel when appropriately connected. OUT
Driver is the same device as OUT Diode (or Complement for P-Channel DUT Diode)
MOTOROLA TMOS POWER MOSFET DATA
C-61
•
MTE60N18, 20/65N12, 15
SAFE OPERATING AREA INFORMATION.
MAXIMUM RATED FORWARD BIASED SAFE OPERATING AREA
FIGURE 13 - MTE65N12. MTE65N15
FIGURE 12 - MTE60N18. MTE60N20
•
300
180
100
70
i
_.
-.... -- .
101'"
~ 50
~3O
l!';
~
.......
-
3.0
'"
1.0
0.7 ~
0.5
0.3 3.0
=
roSIONI Limil - - Package Limil - '
Thermal Limil
VGS 20 V
lC 25'C
Single Pulse
I.
-
~~
100
70
~
._.
10 I'" '
-r-"
S
~
§
de
MTE60NI8
MTE60N20
1-
100 I'"
30
r~
P"- C-
1.0ms
........
10:'
10
de
7.0
rOSIONI Limit --u 5.0 ====
Package Limit - ' ~ 3.0 Thermal Limit
'" 2.0 VGS 20V
.:;
- 1.0
TC 250C
JTE65N12
0.7 ~ Single Pulse
MTE65N15
0.5
0.3
3.0
5.0 7.0 10
20 30
50 70
VOS. ORAIN·TO·SOURCE VOLTAGE IVOLTSI
10~
5.0 7.0 10
30
50 70 100
VOS. ORAlN·TO·SOURCE VOLTAGE IVOLTSI
-' r-'
::-
-50
1.0ms
!Z
a~ 7.05.010 ~
.t
l~bl'"
300
200
=
==
200 300
FIGURE 14.- MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
100
200
FIGURE 15 - THERMAL RESPONSE
0
250
DC 0.5
Plpkl
1
TillL
0=0.1
0 0.03
Single Pulse
MTE65NI2- !---+
MTE65N15
MTE60N18
MTE60N20
1~
ROJCII) = rjl) ROJC
ROJC = 0.5 'C/W Max
o Curves Apply for Power Pulse Train Shown
TJ'" 150'C
o
o
t'::
12~.J
oulV Cvcle. 0 - ,,/12
50
100
150
200
VOS. ORAIN·TO·SOURCE VOLTAGE IVOLTSI
~
250
0.01
Read Tim. @ '1
TJlpkl - TC = Plpkl ROJCIII
1.0
10
0.1
I. TIMElms)
100
1000
GUARANTEED SAFE OPERATING AREA
The de data presented in Figures 12 and 13 is for a
single one second pulse. applied while maintaining the
case temperature TC at 25·C. For multiple pulses and
case temperatures other than 25°C. the de drain current
at a case temperature of 25°C should be de-rated as
follows:
I (T) = I (250C) [ 150 - TC ]
o
0
Po • RruC • r(tl
where Po is the maximum power rating at 25°C. RruC
is the junction-to-case thermal resistance. and r(t) is the
normalized thermal response from Figure 15. corresponding to the appropriate pulse width and duty cycle.
EXAMPLE: Determine the maximum allowable drain
current for an MTESON18 at 25 volts drain voltage. with
a pulse width of 10 ms and duty cycle of 50%. at a case
temperature of 800C.
From Figure 13. the dc drain current at VOS = 25
volts is 10 A. For a 10 ms pulse and duty cycle of 50%.
Figure 15 gives an r(tl of O.S; then. with Po = 250 watts
at 25°C and RruC = 0.5 °CIW.
I = 10 x
150 - 80
= 9.33 A
250 x 0.5 x O.S
o
The switching safe operating area in Figure 14 is the
boundary that the load line may traverse without incurring damage to the device. The fundamental limits
are the maximum rated peak drain current '0M. the
minimum drain-to-source breakdown voltage VSR(OSSI
and the maximum rated junction temperature. The
boundaries are applicable for both turn-on and turn-off
of the devices for rise and fall times of less than one
microsecond.
MOTOROLA TMOS POWER MOSFET DATA
C-S2
MTE60N18, 20/65N12, 15
FIGURE 16 - INDUCTIVE LOAD
SWITCHING CIRCUIT
FIGURE 17 - CLAMPED INDUCTIVE
LOAD SWITCHING WAFEFORMS
A-+ VOM '" VOSS
./
/'
\
/'
-
vi--!
td
10/
/
Vos
Vin
1/
V
90%
Note 4 Even with good RF layout and ideal clamping
below the maximum V(BR)DSS of the device,
significant potentials may be generated across
the package drain and source parasitic inductances during rapid turn off of a large magnitude
of current. These induced voltages which are
internal to the package add to the clamp voltage. Therefore, to protect· the chips from excessive voltage, the diD/dt must be limited in
accordance to the peak voltage seen across the
terminals. of the device. The MAXIMUM ALLOWABLE dioldt must be limited in accordance
to the peak VDS appearing at the device terminals as shown in Figure 18.
For applications requiring slower switching !lpeeds,
increasing the gate drive impedance will increase the
switching times. This can be accomplished by adding
a resistor in series with the gate.
versus
10,000
8000
~
6000
!'
III
~
~
::::0
,
us
TJ = 100'C
0.03
~
~
g
2
TJ
~ 0.02
l'5 0.01
0
0.03
100'C
o
55!C
i
VGS = 10V
~
::::0
25'C
~ 0.02
MTE100N05, MTE100N06
0.05
40
60
10, DRAIN CURRENT (AMPS)
80
~
100
25"<:
55"C
0.01
0
20
40
6
10. DRAIN CURRENT (AMPS)
MOTOROLA TMOS POWER MOSFET DATA
C-66
100
MTE75N08, 101100N05, 06
TYPICAL CHARACTERISTICS
FIGURE 7 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
e
~
'"c
:;;
...........
1.1
""" """
~
:ll
,.!:;""c
1.0
9
c
:z: 0.90
...~:z:
!:i
, Vos = VGS
10= 1.0 rnA
~ 8,000
~
~ 6,000
..........
~
~
U 4,00
~
""-
0.80
!
~ 0.10
CAPACITANCE VARIATION
-50
50
25
-25
15
100
"
2,000
00
150
VGS - 0
\.
f
\~
.......... r--
01\
.........,
125
TJ - 25"C
1\
z
'"
,.
FIGURE 8 -
10,000
1.2
"r-
= 1.0 MHz
CiSS
r-I-
Coss
drs,
r-
JI)
20
Vos, ORAIN-TO-SOURCE VOLTAGE (VOLTS)
TJ. JUNCTION TEMPERATURE lOCI
0
TMOS SOURCE-TO-DRAIN DIODE CHARACTERISTICS
In the fabrication of a TMOS FET, a diode is formed
across the source-to-drain terminals as shown in Figure
9_ Reversal of the drain voltage will cause current flow
in the reverse direction. This diode may be used in circuits requiring external fast recovery diodes, therefore,
typical characteristics of the on voltage, forward turnon and reverse recovery times are given.
FIGURE 10 -
DIODE SWITCHING WAVEFORM
!z
~
Is
B
1. 01--t-gccO
%cc.r-H",+-f---t...""'\-+--t--t--t---j
FIGURE 9 - TMOS FET WITH
SOURCE-TO-DRAIN DIODE
~
0.81--+---fV
++-I--t---l--'H-II.---+---f--t----1
I' ~
0.61--+-j*",+-t--+-+-tT
L t\ dt -t----j~-t----1
53 0.41---+-,H--H-+---+--+\-\I--+----t--I
!::t
L
"" 0.2f-:c----hf-H-t--t---t---t--'\+___+--++-1
~
10%!\t--!rr- rj
'"
~
o
~
-
~
d~
IRM(REC)~"
Ion
IRM(RECI
tIme
s
VCC
FIGURE 11 -
DIODE SWITCHING TEST CIRCUIT
L = 100p.H, 30 A
(2,200 pI'!, 15 A Inductors
in Parallel)
J. W. MILLER: 07828
270 K
R1: Duty Cycle
Control
f=25kHz
OUT
DRIVER
To Set D-S Diode Current IS,
Adjust R1 and/or VCC
-V .. 5_0 V
NOTE: OUT is Shown as an N-Channel TMOS but can also be
a P-Channel when appropriately connected. OUT
Driver is the same device as OUT Diode (or Complement for P-Channel OUT Diode)
MOTOROLA TMOS POWER MOSFET DATA
C-67
MTE75N08, 10/100N05, 06
SAFE OPERATING AREA INFORMATION
MAXIMUM RATED FORWARD BIASED SAFE OPERATING AREA
FIGURE 13 - MTE100N05, MTE100N06
FIGURE 12 - MTE75N08, MTE75N10
_.
1000
500
300
I
!,-
100
0
!~
z
~;~
100 pll
,
lOI'S
~.
~.
f-
10ms
ts
- -- roS(ONI Li mit t"s
·-Package Limit
3.0
1.0
0.3 0.50.11.0
az
10
~
5. 0
I---VGS 20V
f==Single Pulse
I---TC 25'C
9 3.0
1.0
O.1
0.81.0
300
-de
1------ rOS(ONI Lim~
I--- -.- PacI
ie
6.0 V
/15 V,/10 V
/ 1//
~ 120
~ :;...-
MTEl30N15. MTE130N15
I
/
160
7.0 V
/ b
~
I--
~........ V
/.
~
VGS=20V
V......:: V VI-"
TJ-25"C
~ 120
B.OV
FY /"'"
/./': V
160
FIGURE 2 -
200
r
o
;;
6.0 V
't;'
5.0 V
1.0
2.0
3.0
4.0
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
'.0
TRANSFER CHARACTERISTICS
FIGURE 3 -
MTE120N18. MTe120N20
200
II
FIGURE 4 -
200
/
/
ir
::;;
25°C-
~
I(Jf
VDS= 10 V
~
~
g;;
V
az
l00"C-
80
~
..0 V
o
120
o
.Q 40
v.::- ~
o
2.0
4.0
6.0
B.O
VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)
I I
1I /
TJ= -"oc- r;
2,oC- f.1 /
160
---I V /
'-h /
l00°C- fA
TJ= -55°C-
o
o
10
MTE130N12. MTE130N15
'h
A
VII
VDS=10V
/ Vi
2.0
I---:::::: ~
4.0
6.0
8.0
VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)
10
ON-RESISTANCE versus DRAIN CURRENT
i
g
FIGURE 5 -
MTE120N18. MTE120N20
51
~
z
25°C
.g
~
:z
Z
i
;;; o.oOB
e
0
25
1,50 C
.OOB
~ .004
VGS=10V
Z
a
.012
~
-55°C
~
0.012
c
2,OC
:i
=>
0.016
MTE130N12. MTE130N15
TJ 100°C
~
z
~ .016
TJ = il00°C
is
=
~
FIGURE 6 -
.020
50
75
10, DRAIN CURRENT (AMPS)
100
12,
00
VGS=10V
30
60
90
10, DRAIN CURRENT (AMPS)
MOTOROLA TMOS POWER MOSFET DATA
C-72
120
150
MTE120N18, 20/130N12, 15
TYPICAL CHARACTERISTICS
FIGURE 7 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
FIGURE 8 - CAPACITANCE VARIATION
CAPACITANCE VARIATION
40.000
1
~~
...........
VOS = VGS
10 = 1.0 mA
~
"'-..
1.0
IS
~
~
i'-.....
~ 0.90
~
:z:
I'--.
r-....
D.an
0
25
50
75
TJ. JUNCTION TEMPERATURE 1°C)
100
~
Coss
8000
.......
III
1\
U
i \Crss .......
........
-25
24,000
~
~ 16,000
to
10.70
>
-50
2JoC _ >--VGS = 0
f = 1.0 MHz- f---
~
9
~
T~ =
32.000
125
150
o
o
10
20
30
40
50
VDS, DRAIN·TO·SOURCE VOLTAGE IVOLTS)
TMOS SOURCE-TO-DRAIN DIODE CHARACTERISTICS
typical characteristics of the on-voltage, forward turnon and reverse recovery times are given.
In the fabrication of a TMOS FET, a diode is formed
across the source-to-drain terminals as shown in Figure
9. Reversal of the drain voltage will cause current flow
in the reverse direction. This diode may be used in circuits requiring external fast recovery diodes, therefore,
FIGURE 10 -
Is
0
FIGURE 9 - TMOS FET WITH
SOURCE·TO-DRAIN DIODE
90%
8
.6
4
2
DIODE SWITCHING WAVEFORM
/
'\
rt
~
/
\
10% f-
ton
dis
Lr\ dt
\I---l rr -
~
IRMIREC)
V
I-
H
/~
/
IRMIREC)
5
VCC
FIGURE 11 -
DIODE SWITCHING TEST CIRCUIT
100!,H, 30 A
(2)200 !,H, 15 A Inductors
in Parallel
J. W. MILLER: 07828
270 K
R1: Duty Cycle
Control
OUT
DRIVER
f=25kHz
To Set 0-5 Diode Current IS,
Adjust R, andlor VCC
V "" -5.0V
NOTE: OUT is Shown as an N-Channel TMOS but can also be
a P-Channel when appropriately connected. OUT
Driver is the same device as DUT Diode lor Complement for P-Channel OUT Diode)
MOTOROLA TMOS POWER MOSFET DATA
C-73
MTE120N18, 20/130N12, 15
SAFE OPERATING AREA INFORMATION
MAXIMUM RATED FORWARD BIASED SAFE OPERATING AREA
FIGURE 13 - MTE120N12. MTE130N15
FIGURE 12 - MTE120N18. MTE120N20
MAXIMUM RATED FORWARD BIASED
SAFE OPERATING AREA
MAXIMUM RATED FORWARD BIASED
SAFE OPERATING AREA
1000
500
1000
500
•
~loo
....
.-
100"
i. ms
tOms
z
~
Oms
dc
10ms
a:
'-'
:::>
rDSlon)Limit -----;....: ~c
z
«a: 10 ,,/8Ckage Limit - Thermal Limit
0
£0
VGS 20V
Singl. Pulse
TC=25OC
1.0
1.0
MTE120N18
MTE120N20
rOSlon) Limit - - - Package Lim~ - -Thermal Limit
VGS 20 V
Single Pulse
TC=25'C
f-
10
100
200
VOS, ORAIN-TO-SOURCE VOLTAGE IVOLTS)
S
~
w
'-'
z
~
TJ"'150'C
!Z300
~
!
~
£0 100
;;;;; 1000
i
o
o
\
\
\
\
\
1\
\
\
1\
\
\ \
\ \
\ \
\
\
\
\
\
\
\
\
40
80
120
160
VDSM,' PEAK DRAIN SOURCE VOLTAGE (VOLTS)
'MAXIMUM DRAIN SOURCE VOLTAGE APPEARING
BETWEEN THE DRAIN HEADER AND SOURCE SENSE LEAD
\
':c 10%
r-tfi-I
90°10
l - t c - ---i
Monitoring VDS by observing the potential that appears across the drain header (package heat sink) and
the source sense terminal gives the best indication of
the potential appearing at the chip. Due to the source
and drain bus inductances, sensing VDS across the
drain and source terminals may yield a significantly
lower resu It.
Regardless of where VDS is measured, at very large
dioldt's the package inductance (e.g., the source wirebonds) will induce drain-source voltages at the die that
are greater than those observable externally. To guard
against excessive voltages, VDS should be monitored
across the drain header and source sense terminal, and
the maximum allowable dioldt should be derated in
accordance with the pack VDS as shown in Figure 18.
\
\
\
1/
:;-10%
Note 4 Even with good RF layout and ideal clamping
below the maximum V(BR)DSS of the device,
significant potentials may be generated
across the package drain and source parasitic
inductances during rapid turn off of a large
magnitude of current. These induced voltages, which are internal to the package, add
to the clamp voltage.
FIGURE 18 - MAXIMUM ALLOWABLE dioJdt
!
tdv-I
Note 3 Since most "real world" loads are inductive,
the fast turn-off peak flyback voltage (e =
L dildt) must not exceed the VBR(DSS) rating, an instantaneous voltage limit. The protective circuitry, including parasitics, must
have response times commensurate with
the Power MOSFET switching speed, e.g.,
rectifiers must have very short recovery
times. The forward recovery time tfr' overshoot voltage VFM(DYN) and reverse recovery time trr should be low to minimize the
switching stress on the transistor.
Note 1 As in any wideband circuit, good RF layout
techniques must be maintained, i.e., short
lead lengths, adequate ground planes and
decoupled power supplies.
200
MOTOROLA TMOS POWER MOSFET DATA
C-7S
I
\
time
CONSIDERATIONS IN DESIGNING WITH
POWER MOSFETS
5000
Vclamp
].90%
V
..
MTE1S0N08
MTE1S0Nl0
MTE200NOS
MTE200N06
•
®
Designer's Data Shpet
MOTOROLA
150 and 200 AMPERE
N·CHANNEL TMOS
ENERGY MANAGEMENT SERIES
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTORS
POWER FET
roS(on) = 0.009 OHM
50 and 60 VOLTS
rDSlon) = 0.012 OHM
80 and 100 VOLTS
These TMOS Power FETs are designed for high current, high
speed power switching applications such as switching regulators,
converters, and motor controls.
• lOSS, VOS(onl, SOA and VGS(thl Specified at Elevated
Temperature
III"
• Rugged - SOA is Power Dissipation Limited
• High di/dt Capability
,--------,
:~;~~~~~:=:.::I. S,. .
TMOS
MAXIMUM RATINGS
MTE
Rating
Symbol
200NOS 2OON06 150N06 150N10
Unit
Drain-Source Voltage
VOSS
50
60
80
100
Vdc
Drain-Gate Voltage
(RGS = 1.0 MOl
VOGR
50
60
80
100
Vdc
Gate-Source Voltage
±20
VGS
Drain Current
Continuous
Pulsed
Vdc
Adc
10
10M
200
800
150
600
diotdt
See Note 4 and Figure 18
. in Considerations
AJp.s
IGM
2.0
Adc
500
4.0
Watts
TJ, Tstg
-65to 150
"C
Mounting Torque (To heat sink
with 10-32 screw)(1)
.(m)
20
in-Ib
Lead Torque (Lead to bus with
%-20 screw) (2)
.(1)
20
in-Ib
Per Unit Weight
W
120
grams
R/lJC
0.25
"C/W
TL
275
"C
Turn-Off Rate of Change
Gate Current -
Pulsed
Total Power
Dissipation @TC = 25"C
Derate above 25"C
Operating and Storage
Temperature· Rl'nge
Po
wry
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Maximum Lead Temp. for
Soldering Purposes, Yo"
from case for 5 seconds
1+110.36 (0.0141@ITI'§!!1 8(9)1
4. DIMENSIONING AND TOlERANCING
PER ANSI Y14.5. 1973.
.!!.!(!!
-}
D
E
f
G
H
J
K
L
M
N
P
0
R
S
v
W
X
1. A BeUsvllle washer of 0.472" 0.0., 0.205"1.0., 0.024" thick and ISO pounds flat i. recommended.
2. The maximum penetration of the screw should be limited to 0.76",
.003" thick mica IMulator available . . . . .parete Item. Motorola PIN 48ASB1238TBOO1
MOTOROLA TMOS POWER MOSFET DATA
C-76
If
1:
6.10
6.80
IETERS
MAX
63.84
5139
1
6.BO
1.11
0.11
0.81
43.31 Bse
12.57 12.82
1~2
1.52
9.50
9.75
10.21 10.46
18.92 19.18
23.61
5.08
3.53
6.16
14.13
5.33
6.40
7.37
23.93
5.21
3.78
1.26
15.24
5.84
6~5
1.87
INC
MIN
2.090
2.180
.240
O. 0
0.028
1.705
0.495
O.OBO
0.314
0.402
0.145
0.932
0.200
0.139
0.266
0~80
0.210
0.22
0.290
CASE 346-01
MO-G4OAA
0.755
D.942
0.05
0.149
0.286
a.BOO
0.230
0.262
0.310
MTE150N08, 10/200N05, 06
I
ELECTRICAL CHARACTERISTICS
(TC = 25'C unless otherwise noted)
Characteristic
I Symbol
Min
Max
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS = 0, 10 = 5.0 mAl
V(BR)OSS
MTE200N05
MTE200N06
MTE150NOS
MTE150Nl0
50
60
60
100
Zero Gate Voltage Drain Current
(VOS = 0.S5 Rated VOSS, VGS = 0)
(TJ = 100'C)
lOSS
Gate-Body Leakage Current
(VGS = 20 Vdc, VOS = 0)
IGSS
-
-
Vdc
mAdc
0.25
2.5
500
nAdc
ON CHARACTERISTICS·
Gate Threshold Voltage
(10 = 1.0 mA. VOS = VGS)
(TJ = 100'C)
Vdc
VGS(th)
2.0
1.5
Static Drain-Source On-Resistance
(VGS = 10 Vdc, 10 = 100 Adc)
rOS(on)
-
MTE200N05
MTE200N06
MTE150N08
MTE150Nl0
(VGS = 10 Vdc, 10 = 75 Adc)
Drain-Source On-Voltage (VGS = 10 V)
(10 = 200 Adc)
(10 = 100 Adc, TJ = 100'C)
(10 = 150 Adc)
(10 = 75 Adc, TJ = 100'C)
Forward Transconductance
(VOS = 15 V, 10 = 100 A)
VOS(on)
-
MTE200N05
MTE200N06
MTE200N05
MTE200N06
MTE15ONOB
MTE15ON10
MTE150NOB
MTE15ON10
9ls
MTE200N05
MTE200N06
MTE150NOB
MTE150Nl0
(VOS = 15 V, 10 = 75 A)
40
40
4.5
4.0
Ohms
0.009
0.012
Vdc
2.1
1.B
2.2
1.S
-
mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
-
Ciss
(VOS = 25 V, VGS = 0, 1= 1.0 MHz)
Output Capacitance
Reverse Transfer Capacitance
-
Coss
Crss
lS,OOO
pF
10,000
4,000
SWITCHING CHARACTERISTICS' (TJ = 100'C)
Inductive Load, Clamped -
MTE200N05 and MTE200N06
Turn-Off Delay Time
(Vcl amp = 25 Vdc, 10 = 100 Adc
Crossover Time
L = 25 I£H, Yin = 10 Vdc
Ie
Raen = 50 0) See Figures 16 and 17
tli
Current Fall Time
Inductive Load, Clamped -
Idv
'.
-
1400
ns
2000
700
MTE 15ONOB and MTE15ON10
Turn-Off Delay Time
(Vcl amp = 25 Vdc, 10 = 75 Adc
Crossover Time
L = 251£H, Yin = 10 Vdc
Ie
Current Fall Time
Rilen = 50 0) See Figures 16 and 17
tli
-
tdv
1400
ns
1200
400
Symbal
Typical
Unit
VSO
2.0
Vdc
Forward Turn-On Time
Ion
50
ns
Reverse Recovery Time
trr
650
ns
SOURCE-DRAIN DIODE CHARACTERISTICS'
Forward On-Voltage
(IS = Rated '0, VGS = 0)
·Pul •• Teat: Pul•• Width .. 300 1£8, Duty Cvcl. " 2%.
MOTOROLA TMOS POWER MOSFET DATA
C-77
•
MTE150N08, 10/200NOS, 06
TYPICAL CHARACTERISTICS
ON·REGION CHARACTERISTICS
FIGURE 1 - MTE150NOI. MTE150N10
I
vGS 20V
150
•
r IIr
I 11/
120 f--l0J
-
i!Z
I
£-
I
TJ = 25°C f---
I
6.0 V
5.L-
~
!Z
~
:>
120
z
80
'-'
~
1
,
30
2.0
1.0
4.0
3.0
20vJII V
IW
I
TJ = 25'C
I111
'"
Ii.
I
I
V
'1/
, '"
6.0 V
I/)
o
I--
7.h- -
1
,
5.6v
oV
5.0
B.OV
10V
/I,
.9 40
f---
r
o
o
VGS
~ 160
1
I V
/I
60
I
7.0 V
!J.
1/
II
90
~
I-s.ov
FIGURE 2 - MTE200N05. MTEZOON08
200
2.0
1.0
VDS. DRAIN·TQ·SOURCE (VOLTS)
3.0
4.0
5.0
VOS. DRAlN·TO·SOURCE VOLTAGE (VOLTS)
TRANSFER CHARACTERISTICS
150
I--
v~ = l'OV
TJ =
120
I
!Z
I I
-55'C f./II
~
25°C
60
~
200
/
j.t..-l00'C
~
!Z
120
z
80
!
.4
I./h'
~W
.9 30
~
o
I /
25'C- f-+ W V
TJ = -55°C_ f-+.j
l00'C
II V
111/
A
.A'll
.9 40
.......-:: ~
o
1/
I- V~ = lov
~ 160
J
'1 V
'II
90
~
z
FIGURE 4 - MTE200N05. MTEZOONOB
FIGURE 3 - MTE150N08. MTE150N10
2.0
4.0
6.0
8.0
VGS. GATE·TO.sOURCE VOLTAGE (VOLTS)
o
o
10
~
~
'"
v
2.0
4.0
6.0
8.0
VGS. GATE·TO·50URCE VOLTAGE (VOLTS)
10
ON·RESISTANCE versus DRAIN CURRENT
~
§
FIGURE 5 - MTE150NOB. MTE150N10
0.020
~
~ 0.016
,
§
I- VGS = 10V
~0.016
I
z 0.012
o
TJ
I:!
TJ
o
~0.008
= l00'C
25'C
~
-55'C_ -
-55'C
Z
~0.004
0.004
00
= 10V
I:!
0.008
i
I
-VGS
"
~:::; 0.012
l00'C- 25'C
~
FIGURE 6 - MTEZOON05. MTE200NOB
~ 0.020
,I,
c
30
60
90
120
150
I
00
80
40
120
10. DRAIN CURRENT (AMPS)
II), DRAIN CURRENT (AMPS)
MOTOROLA TMOS POWER MOSFET DATA
C·78
180
200
MTE150N08, 10/200N05, 06
TYPICAL CHARACTERISTICS
AGURE 7 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
5
;
15
...........
1.1
"-
...
1.0
~
9
~
'"
!
CAPACITANCE VARIATION
40.000
1.2
1';.
~
FIGURE 8 -
VOS = VGS
lo=1.0mA
"-
0.90
""
32,000
....
\\
'\ \
...........
"'-.,.
"
0.80
-25
I
I
TJ = 25"C VGS = 0
1=1.oMHz_
.~
<3.....
~ 0.70
.g' -SO
I
o
25
50
75
100
TJ, JUNCTION TEMPERATURE lOCI
.......
125
\. ........
s.ooo
..... i'..
150
Ciss
o
o
"
Coss
C,.s
10
20
40
30
50
VOS. DRAIN-TO·SOURCE VOLTAGE IVOLTS)
TMOS SOURCE-TO-DRAIN DIODE CHARACTERISTICS
In the fabrication of a TMOS FET, a diode is formed
across the source-to-drain terminals as shown in Figure
9. Reversal of the drain voltage will cause current flow
in the reverse direction, This diode may be used in circuits requiring external'fast recovery diodes, therefore,
typical characteristics of the on-voltage, forward turnon and reverse recovery times are given.
FIGURE 10 - DIODE SWITCHING WAVEFORM
Is
RGURE 9 - TMOS FET WITH
SOURCE-TO-DRAIN DIODE
'\.
90% r-7
'I
1\
z
u
"
r-- ~
h2 r-
rOS(on) Limit
Thermal Limit
10
1== F=
5.0
1== r=
VGS
20V
Single Pulse
TC
25°C
30
~
.!?
"
I
MTE15ON08
MTE15ON10
i~5~CI
-dc~
f= f=
"-
r-.
1111111
MTE200N05
MTE200N06
3.0
0.3
1.0
3.0
5.0
10
30
50
100
0.1
0.3 0.5
1000
~
1.0
I
0.5
:::l
2. 0
~
h ~
~
a:
Q
5.0 V
Q
L
0
4.0 V
0
50
100
150
200
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
250
FIGURE 5 - GATE·THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
~V
~V
6.0 V
5.0 V
/
.5> 1.0
.5>1. 0
le
I-"""
4.0 V
4.0
8.0
12
16
VOS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
'"
TJ = -55°C
VOS = VGS
10 = 1.0 rnA
4. 0
~
'" """ ,
;;
0
~
50
15
100
125
//
.0
--
2000
-
1600
~
~1200
,
2:
5... 800
~
-55°C
.0
400
I
1.0
I
2.0
3.0
ID. DRAIN CURRENT lAMPS)
4.0
5.0
o
o
10
-
\
\
r--...
Ciss
.\
\\
\ r-.....
Coss
Crio'
10
20
30
40
VDS. DRAIN· TO·SOURCE VOLTAGE (VOLTS)
MOTOROLA TMOS POWER MOSFET DATA
C-104
I
TJ = 25°C VGS = 0
_
f = 1.0 MHz
VGS= 10 V
25°C
'fI
FIGURE 8 - CAPACITANCE VARIATION
--t-- rI--
4-- 100°C
4.0
6.0
6.0
VGS. GATE·TOoS·OURCE VOLTAGE (VOLTS)
FIGURE 7 - ON RESISTANCE versus
DRAIN CURRENT
'--
III
V/
.&:. ~
0
150
TJ. JUNCTION TEMPERATURE 1°C)
TJ = 100°C
/-; F- 25°C
.I
0
.........
25
/ /
'II
/1 /
VDS=20V
0
"t--.
-25
20
FIGURE 6 - TRANSFER CHARACTERISTICS
5. 0
"""-
-
VGS= 10 V
:;
Y
2.0
TJ = 25°C
u; 3. 0
Q.
6.0 V
50
MTM/MTP2N85, 90
SAFE OPERATING AREA INFORMATION
FIGURE 10 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
FIGURE 9 - MAXIMUM RATED FORWARO BIASED
SAFE OPERATING AREA
a
80
'0 !,S
r--
1--'
100 !Is
I-- -i-<-
I--
-
/"
8. a
~1."1.0mS
lams
a
1'.
"l _I l'
I'
a
de
/
-
TJ";1500C
Typical rOSlon) Limit
a
Package Limit"
MTM2N90
MTP2N90
111117ermallli.m\t I I I
MTM2N85
TC 25°C Single Pulse
MTP2N85
VGS 20 V
MTM2N90
O. 1
MTP2N90
10
100
VDS. DRAIN-TO-SOURCE VOLTAGE (VOLTS)
=
=
II
400
600
800
200
VDS. DRAIN-TD-SDURCE VOLTAGE (VOLTS)
1000
Rruc
r(t)
FORWARD BIASED SAFE OPERATING AREA
The dc data of Figure 9 is based on a case temperature
(TC) of 25°C and a maximum junction temperature
(TJmax) of 150°. The actual junction temperature de·
pends on the power dissipated in the device and its case
temperature. For various pulse widths, duty cycles, and
case temperatures, the peak allowable drain current
(10M) may be calculated with the aid of the following
equation:
IDM
MTM2N85
MTP2r85
IO(250C)[TJ(maXI - TC]
Po . RruC . r(t)
the dc drain current at TC ~ 25°C from
Figure 9.
TJ(max) ~ rated maximum junction temperature.
device case temperature.
TC
rated power dissipation at TC ~ 25°C.
Po
1000
rated steady state thermal resistance.
normalized thermal response from
Figure 12.
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) of Figure 10
is the boundary that the load line may traverse without
incurring damage to the MOSFET. The Fundamental
limits are the peak current, 10M and the breakdown
voltage, V(BR)OSS' The switching SOA shown in Figure
10 is applicable for both turn-on and turn-off of the
devices for switching times less than one microsecond.
The power averaged over a complete switching cycle
must be less than:
TMOS POWER FET CONSIDERATIONS
Switching Speed - The switching speeds of these devices are
dependent on the driving impedance. Extremely fast switching
devices due to voltage build-up on the input capacitor due to
leakage currents or pickup.
speeds can be attained by driving the gate from a voltage source.
Gate Protection - These devices do not have an internal
monolithic zener diode from gate to source. The addition of an
internal zener diode may result in detrimental effects on the
reliability of a power MOSFET. If gate protection is required, an
external zener diode is recommended.
Transfer Characteristics - The transfer characteristics Bre
linear at drain currents of 500 rnA. (See Figure 6.) Linear amplifiers with high frequency response can be designed using this
product.
Gate Voltage Rating - Never exceed the gate voltage rating
of ±20 V. Exceeding the rated VGS can result in permanent
damage to the oxide layer in the gate region.
Gats Termination - The gate of these devices are essentially
capaCitors. Circuits that leave the gate open-circuited or floating
should be avoided. These conditions can result in turn-on of the
Handling and Packaging - MOS ICs are susceptible to damage
from electrostatic charge. Experience has shown that these
devices are more rugged than MOS les. This is primarily due
to the comparatively larger capacitances associated with
power devices, however, reasonable precautions in handling
and packaging MOS devices should be observed.
MOTOROLA TMOS POWER MOSFET DATA
C-105
MTM/MTP2N85. 90
THERMAL RESPONSE
FIGURE 11 - MTM2N85/MTM2N90
1.0
II
D·0.5
~
0.5
~ ~
0.3
~j
0""
~ ~ 0.1
0.05
wz
~~
tt
~.O.2
--
0.1
w~
---= ,...
~
>.---
DUTY CYCLE. D " '1/'2
PI~klnn
.
0.0
"I-
",,'"
a: I- 0.0 5
oz
zW
:g ~ 0.0 3""~
0.0
,....
~
2~
0.0 1
0.01
11~2j
9.9 1,
.....- ~
0.02
l
~-C
frrmr
0.05
0,1
0.2
0.5
2.0
1.0
5.0
10
ROJCIII " rill RIIJC
ROJC" 1.67°C/W Max
o curves apply for power
Pulse train shown
Read time at t 1
TJlpkl- TC" P,pkl ROJcll1
50
20
100
200
500
1000
t, TIME (ms)
FIGURE 12 -
lii
i;j
~~ i5'
""~
:ot::l
~~
1.0
0.7
D" 0.5
0.5
0.3
0.2
0.2
-
~
'E-
0.02
!z ~
~ -
z
~
AI
0.01
0.01
0.02
-
i-'
l-
f-"
0.1
0.1
0.07 =.0.05
0.05
-0.02
0.03
1-0:
MTP2N85/MTP2N90
~
~
P,pkl
Pulse train shown
Read ti~e at t1
TJlpkl - TC = P,pkl ROJCIII
DUTY CYCLE. D= 11 112
Sl~G\E r~lfl
0.1
ROJC 1.67°C/W Max
D curves apply for power
~~~
,....
I-
0.05
ROJClll = rill ROJC
tJ1SL
0.2
0.5
1.0
2.0
t.
5.0
TIME
10
20
Im.'
MOTOROLA TMOS POWER.MOSFET DATA
C-106
50
100
200
500
lk
®
MTM2P4S, MTM2PSO
MTP2P4S,MTP2PSO
MOTOROLA
Designc,"s Data Sheet
2.0 AMPERE
P-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
P-CHANNEL TMOS
POWER FET
These TMOS Power FETs are designed for high voltage, high
speed power switching applications such as line operated switching
regulators, converters, solenoid and relav drivers,
• Silicon Gate for Fast Switching Speeds Specified at 1000c
rOSlon) = 6.0 OHMS
450 and 500 VOLTS
rl4lJ
~ ~I·_. ~r
Switching Times
• DeSigner's Data - lOSS, YOSlon) and SOA Specified at
Eleveted Temperature
• Rugged -
MTM2P45
SOA is Power Dissipation Limited
• Source-to-Orain Diode Characterized for Use With
Inductive Loads
• Low Drive Requirement, YG(th)
Q
o
STYlE 3
PIN 1. GATE
1r
2. SOURCE
CASE DRAIN
TMOS
CASE 1-05
TO-2Q4AA
/TO-3TYPE)
MAXIMUM RATINGS
Symbol
MTM2P46
MTP2P46
MTM2P50
MTP2P60
Unit
Drain-$ource Voltage
VOSS
450
500
Vdc
Drain-Gate Voltage
IRGS = 1.0 MOl
VOGR
450
500
Vdc
Rating
Gate-Source Voltage
VGS
±20
Drain Current
Continuous
Pulsed
10
10M
B.O
Gate Current - Pulsed
IGM
1.5
Adc
Po
75
Watts
0.6
W/oC
TJ, Tstg
-65 to 150
°C
Total Power
Dissipation @ TC = 25°C
Derate above 25°C
Operating and Storage
Temperature Range
Vdc
Maximum Lead Temp. for
Soldering Purposes, 118from case for 5 seconds
MTPZP45
MTPZP50
Adc
2.0
G
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Casa
1-
~
= 4,5 Yolts (max)
R6JC
1.67
°C/W
TL
275
°C
Designar's Data for "Worst Case" Conditions
The Oa.igner's Data Sheet permits the deSign of most circuits entirely from the.
information presented. Limit data - representing device characteristics boundaries- are
given to facilitate "worst case" design.
o
STYLE 5:
PIN 1. GATE
2, DRAIN
SOURCE
4. DRAIN
a.
CASE ZZ1A-OZ
TO-ZZOAB
MOTOROLA TMOS POWER MOSFET DATA
C-107
----+---.F_
J - +------->-
ftlTMVftnTP2P45,50
ELECTRICAL CHARACTERISTICS (TC =
25"<: unless otherwise noted)
I
Characterlatic
Min
Symbol
OFFCHARACTEmsncs*
Max
~
:. .,;
Orain-Source Breakdown Voltage
(VGS = 0, 10 = 5.0 mAl
Zero Gate Voltage Orain Current
(VOS = 0.85 Rated VOSS, vGS
TJ = 1000c
V(BR)OSS
MTM2P45/MTP2P45
MTM2P50/MTP2P50
450
500
lOSS
= 0)
-
...
"-.'
Gate-Body Leakage Current
(VGS = 20 Vdi:, VOS = 0)
IGSS
Unit
'.
-
Vdc
n;J.Mc
0;25
2.5
500
.'./
nAdc
ON CHARACTERISTICS'
Gate Threshold Voltage
(TC = 25·C)
(10 = 1.0 mA, VOS = VGS, TJ
VGS(th)
Orain-Source On-Voltage (VGS
(10 = 1.0 Adc)
(10 = 2.0 Adc)
(10 = 1.0 Adc, TJ = l00·C)
VOS(on)
Vdc
2.0
1.5
= 100·C)
= 10 V)
Static Orain-Source On-Resistance
(VGS = 10 Vdc, 10 = 1.0 Adc)
Forward Transconductance
(VOS = 15 V,IO = 1.0 A)
r~Ston)
-
9fs
0.5
4.5
4.0
Vdc
6.0
12.5
12.0
6.0
Ohms
-
. mhos
SAFE OPERATING AREAS
Forward Biased Safe Operating Area
Switching Safe Operating Area
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(Vos = 25 V. VGS = O. f = 1.0 MHz) 1 - - = ' - - - 1 - - - Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS*ITJ = 1000 C)
Turn-On Delay Time
Rise ,me
(VOS = 125 V. 10 = 1.0 A.
Turn-Off Delay Time
Rgen = 50 ohms)
Fa" Time
SOURCE DRAIN DIODE CHARACTERISTICS
tdlon)
tr
td(off)
tf
.
Characteristic
Forward On-Voltage
Forward Turn-On Time
IS = 2.0 A
VGS=O
.
Reverse Recovery Time
-
50·
-
100
150
ns
ns
ns
50
nS
Symbol
Typ
Unit
VSO
ton
trr
1.8
50
120
Vdc
ns
ns
Pulse Test. Pulse Width :e;;;300 pS, Duty Cvcle~2% .
RESISTIVE SWITCHING
FIGURE 2 - SWITCHING WAVEFORMS
FIGURE 1 - SWITCHING TEST CIRCUIT
VO,O~
V
R~out
OUT
~
__________~~--90%
MOTOROLA TMOS POWER MOSFET DATA
C-108
:,A: '
MTMIMTP2P45, 50
TYPICAL CHARACTERISTICS
FIGURE 3 - OUTPUT CHARACTERISTICS
-4. 0
FIGURE 4 - ON-CHARACTERISTICS
4.0
--'lG = -lO V
; -3. 0
TJ = 25°C
~
~
....
~
..~
-2.0
:.
-6.0 V.....
£1·1.0
£1-1. 0
-5.0 V
0
-50
-4.0 V-
-
~
-250
-100
-150
-200
Vos. DRAIN-TO-SOURCE VOLTAGE (VOLTS)
~~
g
-
1. 1
"""
1.0
I
_5.0 V", r-VGS = -4.0 V_
-16
~12
-B.O
0
i':
"
~
~
-25
25
50
75
"
-20
125
100
'"
'/
V
0
.......
I 'I
'I r\
~ 'I \
II 100°C
VI
r--t
!J /
0
r---..
~ 0.80
-50
25°C
0
..........
~
~ 0.70
TJ = -55°C
VOS=20V
~
~ 0.90
"
-7l,-
FIGURE 6 - TRANSFER CHARACTERISTICS
VOS = VGS
10= 1.0 mA
ill
~V
-6.0 V,
5. 0
...........
9
..
~V
~
VOS. ORAIN-TO-SOURCE VOLTAGE (VOLTS)
1.2
w
'"
~
"
~
-4.0
FIGURE 5 - GATE·THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE (NORMALIZED)
6
::?:
~~
!!§
z
./
P"......
k% y
TJ = 25°C
!Z
-7.0 V
.... -2. 0
-10 V
~ -3.0
_BI{y
i§
V~S= 20V
-10 V
I
:A
~~
0
2.0
150
TJ. JUNCTION TEMPERATURE (OC)
FIGURE 7 - ON-RESISTANCE versus
DRAIN CURRENT
4.0
6.0
B.O
VGS. GATE·TQ·SOURCE VOLTAGE (VOLTS)
10
FIGURE 8 - CAPACITANCE VARIATION
0
200 0
VGS=10V
-
- - --
TJ = 100°C
0
25°C
0
--
~
-
0
-55°C
0
1.0
2.0
3.0
10. DRAIN CURRENT (AMPS)
0
40 0
4.0
~5OC
TJ =
I-VGS= 0
1= 1.0 MHz I--
1600
5.0
0
.......
Ciss .....
~\..
Coss
10
20
3D
4D
Vos. ORAIN·TO·SOURCE VOLTAGE (VOLTS)
MOTOROLA TMOS POWER MOSFET DATA
C-109
Cras
50
MTMlMTP2P45, 50
SAFE OPERATING AREA INFORMATION
FIGURE 10 - MAXIMUM RATED SWITCHING.
SAFE OPERATING AREA
FIGURE 9 - MAXIMUM RATED FORWARD BIASED
SAFE OPERATING AREA
'10
10
-
8, 0
~
~
~ 6. 0
~~f'
"
'OSlon) limit - - - Package limit
Thermal limit
0
100~
~
I,"" r-
~-
0
MS
il§
10 m
a
z
4, 0
MTM/MTP2P45
~
o,1
1,0
t- dc
MTM2PSO
Vgs = 20 V
t- Single Pulse
TC = 25°C
Mr
10
c
E 2.0
r
2 S
MTM2P4S
,D
MTP2P45
100
200
0
500
"os. ORAIN·TO·SOURCE VOLTAGE (VOLTS)
MTM/MTP2P50
TJ ';;1500 C
100
200
300
400
500
VOS. ORAIN·TO-SOURCE VOLTAGE IVOLTS)
FORWARD BIASED SAFE OPERATING AREA
SWITCHING SAFE OPERATING AREA
The de data of Figure 9 is based on a case temperature
(Te) of 25°C and a maximum junctiOn temperature
(TJmax) of 150°. The actual junction temperature depends on the power dissipated in the device and its case
temperature. For various pulse widths, duty cycles, and
case temperatures, the peak allowable drain current
(10M) may be calculated witl) the aid of the following
equation:
The switching safe operating area (SOA) of Figure 10
is the boundary that the load line may traverse without
incurring damage to the MOSFET. The Fundamental
limits are the peak current, 10M and the breakdown
voltage, V(BR)OSS. The switching SOA shown in Figure
10 is applicable for both turn-on and turn-off of the
devices for switching times less than one microsecond.
The power averaged over a complete switching cycle
must be less than:
IO(25'C)[TJlmaX) - TC]
PO· RruC' r(t)
TJlmax) - TC
RruC
where
IO(25°C) = the dc drain current at TC = 25'C from
Figure 9.
TJ(max) = rated maximum junction temperature.
device case temperature.
TC
rated power dissipation at TC = 25°C.
rated steady state the'rmal resistance.
RruC
r(t)
normalized thermal response from
Figures 11 or 12.
Po
MOTOROLA TMOS POWER MOSFET DATA
C-ll0
MTM/MTP2P45, 50
~
THERMAL RESPONSE
FIGURE 11 - MTM2P45/MTM2P50
1.0
~
wz
0-0.5
~ ~ 0.3
~~
tt ~ 0.2
U
0.1
::Ow
",I
",f-
a::
I-
02
Zw
:g ~
~
0.0 5
-
0.1
0.05
w~
c'"
~ ~
--
0.5
0.02
--
0.0 3 -
0.0 1
0.01
0.02
I-
...
frrmr
0.05
R8JCIII = r(11 R8JC
%JC = 1.67°C/W Ma,
DUTY CYCLE. D = 11/12
0.1
-
-
111=:2~
I
0.2
0.5
1.0
5.0
..
TJlpkl - TC = plpkl R8JCIII
I
I I 1
I I 111111
2.0
o curves apply for power
Pulse train shown
Read time" at t1
==
:::::
lInn
~,
...... ~
0.0 2 ...............
P'"
f0-
10
I
20
I IIII
50
100
I
200
500
1000
t, TIME (ms)
FIGURE 12 - MTP2P45/MTP2P50
0.7
0.5
D 0.5
0.3
_r-:
-.-::;;::;-
%Jclll =. ~II R8JC
.R8JC = 1.B7°C/W Ma,
D curve. apply lor power
Pulse train shown
Read lime at 11
TJlpkl- TC = P(pkl R8JC(11
I. TIME Im.1
TMOS POWER FET CONSIDERATIONS
Switching Speed - The switching speeds of these devices are
dependent on the driving impedance. Extremely fast switching
speeds can be attained by driving the gate from a voltage source.
devices due to voltage build-up on the input capacitor due to
leakage currents or pickup.
Gate Protection - These devices do not have an internal
monolithic zener diode from gate to source. The addition of an
internal zener diode may result in detrimental effects on the
reliability of a power MOSFET. If gate protection is required, an
external zener diode is recommended.
Transfer Characteristics - The transfer characteristics are
linear at drain currents of 500 rnA. (See Figure 6.1 Linear amplifiers with high frequency response can be designed using this
product.
Gate Voltage Rating -
Never exceed the gate voltage rating
Handling and Packaging - MOS ICs are susceptible to damage
of ±20 V. Exceeding the raled VGS can result in permanent
from electrostatic charge. Experience has shown that these
devices are more rugged than MOS ICs. This is primarily due
to the comparatively larger capacitances associated with
power devices, however, 'reasonable precautions in handling
damage to the oxide layer in the gate region.
Gate Termination - The gate of these devices are essentially
capacitors. Circuits that leave the gate open-circuited or floating
should be avoided. These conditions can result in turn-on of the
and packaging MOS devices should be observed.
MOTOROLA TMOS POWER MOSFET DATA
C-111
:
@ MOTOROLA
MTM3N35, MTM3N40
MTP3N35, MTP3N40
Designer's Data Sheet
3.0 AMPERE
N-CI:IANNEL TMOS
POWER FET
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
rDSlon) = 3.3 OHMS
350 and 400 VOLTS
These TMOS Power FETs are designed for high voltage, high
speed power switching applications such as line operated switching regulators, converters, solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds Specified at 100°C
Switching Times
MTM3N35
MTM3N40
• Designer's Data -lOSS, VDS(on), VGS(th) and SOA
Specified at Elevated Temperature
• Rugged -
SOA is Power Dissipation Limited
rs~.]J=tc
to
ED/
• Source-to-Drain Diode Characterized for Use With
Inductive Loads
• Low Drive Requirement, VG(th)= 4.5 Volts (max)
1r
Go----l,!
TMOS
STYLE 3
PIN 1. GATE
2. SOURCE
CASE DRAIN
MAXIMUM RATINGS
Symbol
MTM3N35
MTP3N35
Drain-Source Voltage
VOSS
350
400
Vdc
Drain-Gate Voltage
(RGS = 1.0 Mil)
VOGR
350
400
Vdc
Gate-Source Voltage
VGS
±20
Drain Current
Continuous
Pulsed
10
10M
3.0
8.0
Gate Current - Pulsed
IGM
1.5
Rating
MTM3N4O
MTP3N4O
Unit
Vdc
CASE 1-05
TO-204AA
ITO-3TVPE)
MTP3N35
MTP3N40
Adc
Total Power
Dissipation @TC = 25°C
Derate above 25°C
Oparating and Storage
Temperature Range
Adc
Watts
Po
75
0.6
Wf'C
-65 to 150
°C
R8JC
1.67
0c/w
TL
275
°c
TJ; Tstg
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Maximum Lead Temp. for
Soldering Purposes, 1/8"
from case for 5 seconds
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
Designer's Data for "Worst Case" Conditions
The Designers Data Sheet permits the design of most circuits entirely from the
information presented. Limitdata - representing device characteristics boundaries - are
given to facilitate "worst case" design.
CASE 221A-02
TO-220AB
MOTOROLA TMOS POWER MOSFET DATA
C-112
a
K
I
MTM/MTP3N35, 40
ELECTRICAL CHARACTERISTICS (TC = 25'C unless olherwise noled)
Symbol
Characteristic
Min
Max
350
400
-
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS = 0, 10 = 5.0 mA
Zero Gate Voltage Drain Current
(VOS = 0.85 Aaled VOSS, VGS
TJ = 100"C
V(BA)OSS
MTM3N351MTP3N35
MTM3N40/MTP3N40
lOSS
mAde
-
0.25
2.5
2.0
1.5
4.5
4.0
5.0
12
10
rOS(on)
-
3.3
Ohms
9ls
0.75
-
mhos
= 0)
Gate-Bodv leakage Current
(VGS = 20 Vdc, VOS = 0)
Vdc
IGSS
500
nAdc
ON CHARACTERISTICS·
Gale Threshold Voltage
(10 = 1.0 mA, VOS = VGS)
TJ = l000c
Drain-Source On-Voltage (VGS
(10 = 1.5Adc)
(10 = 3.0 Adc)
(10 = 1.5 Adc, TJ = 100"C)
Vdc
VGS(lh)
=
10 V)
VOS(on)
Static Drain-Source On-Resistance
(VGS = 10 Vdc, 10 = 1.5 Adc)
Forward Transconductance
(VOS = 15 V,IO = 1.5 A)
Vdc
SAFE OPERATING AREAS
Forward Biased Safe Operating Area
Switching Safe Operating Area
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VOS
= 25 V, VGS = 0, I =
1.0 MHz)
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS· (TJ = lOO'C)
Turn-On Delay Time
Id(on)
Rise Time
(VOS
Turn-Off Delay Time
=
125 V, 10
Agen
=
=
1.5 A,
Ir
50 ohms)
Id(ofl)
Fan Time
II
-::: ..........
---
40
ns
60
ns
-
60
ns
30
ns
Symbol
Typ
Unit
VSO
1.0
Vdc
Ion
190
ns
I"
300
ns
SOURCE DRAIN DIODE CHARACTERISTICS·
Chsracteristlc
Forward On-Voltage
Forward Turn-On Time
Reverse Recovery Time
I
I
I
= 3.0A
VGS = a
IS
'Pulse Test: Pulse Width", 300 ~s, Duty Cycle "'2%.
RESISTIVE SWITCHING
FIGURE 1 -- SWITCHING TEST CIRCUIT
FIGURE 2 -
SWITCHING WAVEFORMS
Id(on)
Output, Vout
Inverted
MOTOROLA TMOS POWER MOSFET DATA
C-113
MTM/MTP3N35, 40
TYPICAL CHARACTERISTICS
FI~URE
4.0
3 - OUTPUT CHARACTERISTICS
FIGURE 4 - ON-CHARACTERISTICS
4.0
NS=10I V
VGs· 1I0V
7.0 V
0
~
)~
6.0 V
2.0
!
0
o
50
100
150
200
VOS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
oI/"
o
250
~
1. 1
t!l
;!
..........
~
1.0
~
9
I"..:
"
i=
~
0.80
'"
: 0.70
-50
>
-25
25
_ 4.0
i15
TJ = -55°C
50
75
~
~
100
~ 1.0
~
.........
125
150
FIGURE 7 - ON-RESISTANCE vefSUS
DRAIN CURRENT
~
TJ = 100°C
4.0
~
~
~ 3.0
~
25°C
~
V
'"
.,.~ 2.0
c
0
o
-
.!!o
..,zw
..,t::
2.0
10. DRAIN CURRENT (AMPS)
10
3.0
VGS = 0
300
1\
f= 1.0 MHz
Ciss
c(
c(
";3 200
\
.;
100
o
1.0
8.0
TJ = 25°C
400
~
VGS = 10 V
§
~
A
W
FIGURE 8 - CAPACITANCE VARIATION
L-.--
~55°C
:s~ 1.0
25°C
500
./
~
!a
20
.J \I
/J. I-- 100°C
2.0
4.0
6.0
VGS. GATE-TO-SOURCE VOLTAGE (VOLTS)
TJ. JUNCTION TEMPERATURE 1°C)
;;;5.0
1,-/
/ ~ I//J
//
3.0
i!! 2.0
1--.
16
II VI
VOS=20V
~
""-
~ 0.90
ill
4.0
8.0
12
VOS. DRAIN-TO-SOURCE VOLTAGE (VOLTS)
FIGURE 6 - TRANSFER CHARACTERISTICS
VOS = VG!,
10 = 1.0 rnA
..........
5.0 V
5.0
.'
i
6.0 V
F
FI~URE 6 - ~ATE-THRESHOLD VOLTA~E
VARIATION WITI;I TE\IIIPERATURE! (NORMALIZED)
1.2
S
VJis = 7.0 V
V
J
5.0 V
o
I--
V
V........
TJ = 25°C
~ 1.0
...
)- V
TJ = 25°C
~ 3:0
~
~
..,i'"
t\
4.0
"'\
,
o
~I-
C".
10
20
30
40
VDS. DRAIN-TO-SOURCECAPACITANCE (VOLTS)
MOTOROLA TMOS POWER MOSFET DATA
C-114
Coss
50
MTM/MTP3N35. 40
SAFE OPERATING AREA INFORMATION
FIGURE 9 - MAXIMUM RATED FORWARD BIASED
SAFE OPERATING AREA
10
10
10",
r--
-
VGS=20V
Singl. Pulse
TC = 25°C
!~ 6.0
f'... 1"'-
'DSlon) Limit ----
Package limit
Thermal limit
~
1.0 m"-
t'\
1.0
_8.0
IJ',.IOO '"
,.....V
D. I
FIGURE 10 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
--
l!1
Om
MTM3N40
MTP3N4O
~ 4.0
MTM3N40MTP3N40
~
t- de
r-----
r--..
P2.0
I MTM3N35
MTP3N35- I-
10
100
VDS. DRAIN·TO·SOURCE VOLTAGE IVOLTS)
TJ .;;150 0 C
o
o
400
MTM3N35 MTP3N35
i---'
100
200
300
400
VDS. DRAIN·TO·SOURCE VOLTAGE IVOlTS)
500
FORWARD BIASED SAFE OPERATING AREA
SWITCHING SAFE OPERATING AREA
The de data of Figure 9 is based on a case temperature
(Tel of 25°C and a maximum junction temperature
(TJmax) of 150°. The actual junction temperature depends on the power dissipated in the device and its case
temperature. For various pulse widths, duty cycles, and
case temperatures, the peak allowable drain current
(10M) may be calculated with the aid of the following
equation:
The switching safe operating area (SOA) of Figure 10
is the boundary that the load line may traverse without
incurring damage to the MOSFET. The Fundamental
limits are the peak current, 10M and the breakdown
voltage, V(BR)OSS. The switching SOA shown in Figure
10 is applicable for both turn-on and turn-off of the
devices for switching times less than one microsecond.
The power averaged over a complete switching cycle
must be less than:
'O(25'C) [TJ(max) - TC]
Po . RruC . r(t)
TJ(max) - TC
RruC
where
'O(25'C) = the dc drain current at TC = 25'C from
Figure 9.
TJ(max) = rated maximum junction temperature.
device case temperature.
TC
rated power dissipation at TC = 25'C.
Po
rated steady state thermal resistance.
RruC
r(t)
normalized thermal response from
Figures 11 or 12.
MOTOROLA TMOS POWER MOSFET DATA
C-115
MTMIMTP3N35, 40
THERMAL RESPONSE
FIGURE 11 - MTM3N36/MTM3N40
i
S 1.0
0 0,5
0,7
-
i! 0,5
o-b
•
I" ::
I
~
0, 1
0,0 7
0.05
!2
0.03
!
0.02
ll!
~
:g
0-0.1
..1- ....
0- 0,05
PIPkl
I-'
R8JClti = rltl R8JC
R8JC'= 1.67°C/W Ma,
tSlIl
0 0,01
SINGLE PULSE
o cur.ves apply for power
Pulse train shown
12~1
Read time at t t
TJlpki
TC - Plpkl R8JClti
12DUTY CYCLE, D - II 112
io""
I II II
0,0 1
0,01
0,02 0,03
0,05
0,1
0,2
0,3
0,5
1.0
2.0 3,0
5,0
t,TlME Im,l
I r I II
10
20
30
II111
50
100
-.l
1l
200 300
500
1000
500
1000
FIGURE 12 - MTP3N36/MTP3N40
~ 1.0
o -0,5
i,..
_
0.7
0,5
LJ
0.3
0 0,2
0.2
0 0.1
0,05 _
~
III
'" 0, 1
0,07
i= 0.05
ill
i<:O'
Plpkl
r-'
0 0,01
~ 0,03
0.02 .....
Read time at 11
TJlpki - TC = P1Pki RnJClti
DUTY CYCLE, D = IJ 112
~
g 0,0 1
0,0\
o curves apply'for power
Pulse train shown
12~1
11-
~
:=
ROJClti = rill R8JC
R8JC = 1 67°C/W Ma,
tSlIl
11111
0,02 0,03 0,05
0,\
0,2
0,3
0,5
1.0
2,0
3,0
5,0
10
1111
20
30
50
100
I I
200
I
300
t. TIME 1m"
TMOS POWER FET CONSIDERATIONS
Switching Speed - The switching speeds of these devices are
dependent on tlie driving impedance. Extremely fast switching
speeds can be attained by driving the gate from a voltage source,
Transfer Characteristics - The transfer characteristics are
linear at drain currents of 500 mA, (See Figure 6.) Linear amplifiers with high frequency response can be designed using this
product,
Gate Voltage Rating - Never exceed the gate voltage rating
of ±20 V, Exceeding the rated VGS can result in permanent
damage to the oxide layer in the gate region.
Gate Termination - The gate of these devices are essentially
capacitors. Circuits that leave the gate open-circuited or floating
should be avoided. These conditions can result in turn-on of the
devices due to voltage build-up on the input capacitor due to
leakage currents or pickup.
Gate Protection - These devices do not have an internal
monolithic zener diode from gate to source. The addition of an
internal zener diode may result in detrimental effects on the
reliability of a power MOSFET. If gate protection is required, an
external zener diode is recommended.
Handling and Packaging - MOS ICs are susceptible to damage
from electrostatic charge. Experience has shown that these
devices are more rugged than MOS ICs. This is primarily due
to the comparatively larger capacitances associated with
power devices, however, reasonable precautions in handling
and packaging MOS devices should be observed,
MOTOROLA TMOS POWER MOSFET DATA
C-116
®
MTM3N55, MTM3N60
MTP3N55,MTP3N60
MOTOROLA
,
Iksigner's Data Slwl't
3.0 AMPERE
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
N-CHANNEL TMOS
POWER FET
These TMOS Power FETs are designed for high voltage, high
speed power switching applications such as line operated switching
regulators, converters, solenoid and relay drivers.
rOSlon); 2.5 OHMS
560 and 600 VOLTS
• Silicon Gate for Fast Switching Speeds Specified at 100·C
Switching Times
MTM3N55
MTM3N60
• Designer's Data - lOSS, VDS(on) and SOA Specified at
Elevated Temperature
• Rugged -
SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With
Inductive Loads
• Low Drive Requirement, VG(th) = 4.5 Volts (max)
Q
1r
STYLEl
PIN 1. GATE
2. SOURCE
CASE DRAIN
TMOS
S
MAXIMUM RATINGS
Symbol
MTM3N55
MTP3N55
MTM3N60
MTP3N60
Unit
Drain-Source Voltage
VDSS
550
600
Vdo
Drain-Gate Voltage
(RGS = 1.0 MO)
VDGR
550
600
Vdc
Rating
Gate-Source Voltage
VGS
±20
Drain Current
Continuous
Pulsed
ID
10M
3.0
10
Gate Current - Pulsed
IGM
1.5
Ado
PD
75
Watts
0.6
W/·C
TJ, Tstg
-65 to 150
°c
R8JC
1.67
·C/W
TL
275
°c
CASE 1-05
T0-204AA
ITO-3TYPE)
MTP3N56
MTP3N60
Vdc
Ado
Total Power
Dissipation @ TC ; 25·C
Derate above 25·C
Operating and Storage
Temperature Range
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Go
S
Maximum Lead Temp. for
Soldering Purposes, liSfrom case for 5 seconds
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
Oe8igner'. Data for "Worst Case" Condition.
The Designer's Data Sheet permits the design of most circuits entirelv from the
information presented. Limit data - representing device characteristics boundaries- are
given to facilitate "worst case" design.
CASE 221A-02
TO-220AB
MOTOROLA TMOS POWER MOSFET DATA
C-117
MTMIMTP3N55, 60
ELECTRICAL CHARACTERISTICS (TC = 25°C unles. olherwise noled)
"I,
1
Characteristic
Symbol
Min
Max
550
600
-
-
0.25
2.5
2.0
4.5
4.0
Unit
OFF CHARACTERISTICS
Orain-Sou!ce Breakdown Vollage
(VGS = 0, 10 = 5.0 mAl
II
Vdc
V(BR)OSS
MTM3N55/MTP3N55
MTM3N60/MTP3N60
Zero Gale Vollage Drain Currenl
(VOS ='0,85 Raled VOSS, VGS = 0)
TJ = 100°C
lOSS
Gale-Body Leakage Currenl
(VGS = 20 Vde, VOS = 0)
IGSS
mAde
500
nAdc'
ON CHARACTERISTICS'
Gale Threshold Vollage
(10 = 1.0 mA, VOS = VGS)
TJ= 100°C
VGS(lh}
Drain-Source On-Voltage'lVGS = 10 V)
(10= 1.5 Ade)
(10= 3.0Ade)
(10 = 1.5 Ade, TJ = 100°e)
VOS(on)
Static Drain~Source On-Resistance
(VGS = 10 Vde, 10 = 1.5 Ade)
rOS(on)
Vdc
1.5
Forward Transconductance
(VOS = 15 V, 10 = 1.5 A)
9fs
Vde
1.5
3.75
9.0
7.5
2.5
Ohms
-
mhos
SAFE OPERATING AREAS
See Figure 9
Forward Biased Safe Operaling Area
Swilching Safe Operaling Area
See Figure 10
DYNAMIC CHARACTERISTICS
Inpul Capacila nee
(VOS = 25 V, VGS = 0, f = 1.0 MHZ)f-_.=:"-_+-_ _ _--(~.......;.~-_+---"--_(
OUlpul Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS' iTJ = 100°C)
Turn-On Delay Time
Id(on)
Ir
=125 V, 10 =1.5 A,
Rgen =50 ohms)
Rise Time
(VOS
Turn-Off Delay Time
Id(off)
If
Fall Time
-
50
ns
-
100
ns
180
ns
80
ns
SOURCE DRAIN DIODE CHARACTERISTICS'
Characteristic
Forward On-Vollage
Forward Turn-On Time
Reverse Recovery Time
I
I
I
*Pulse Test: Pulse Width ~300 J,lS, Duty Cycle
Symbol
Typ
Unit
IS= 3.0A
VSO
1.1
Vde
VGS = 0, di/dl ~ 25A/"s
ton
70
ns
I"
165
ns
~2%.
RESISTIVE SWITCHING
FIGURE 1 -
SWITCHING TEST CIRCUIT
FIGURE 2 -
SWITCHING WAVEFORMS
Id(on)
OUlput, YOU!
Inverted
MOTOROLA TMOS POWER MOSFET DATA
C-118
MTM/MTP3N55, 60
FIGURE 3 - OUTPUT CHARACTERISTICS
0
VGS
FIGURE 4 - ON·REGION CHARACTERISTICS
0
v~s =B.b V
= 10 V
/. :/'"
0
6.10 V
5.0 V
r
50
100
~
0./
150
200
250
4.0
VOS. ORAIN-TO-SOURCE VOLTAGE (VOLTS)
FIGURE 5 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
8
:::
'"
~
'"~
'"'"
~
"
~
-........,
1.1
""-..
1.0
VOS = VGS
10 = 1.0 rnA
O.BO
25
-25
50
i'....
I"---
75
100
./'
-
0
0
"" ........
125
.0
//
TJ = 100°C
./"'"
3_0
4.0
5.0
ID. DRAIN CURRENT (AMPS)
I
~
~ 1200
~;3
-55°C
7.0
_55 0
8.0
lD
-
\
BOO
,\
"'-
400
\\
\ r-.....
o
C,,;:--'
o
Ciss
Coss
10
20
30
40
VOs. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
MOTOROLA TMOS POWER MOSFET DATA
C-1'19
I
TJ = 25°C VGS = 0
_
1= 1.0 MHz
z
25°C
6.0
25°C
2.0
4.0
6.0
8.0
VGS. GATE-TO·SOURCE VOLTAGE (VOLTS)
1600
...-
"
FIGURE 8 - CAPACITANCE VARIATION
./
--
./
W
2000
I
2.0
V;;
~ ~ r--
0
VGS=10V1.0
// f/
Tr 100 C
150
V
.0
20
//
FIGURE 7 - ON-RESISTANCE versus DRAIN CURRENT
0
4.0 V
!,'V"
TJ. JUNCTION TEMPERATURE (0e)
5. 0
6.0 V
8.0
12
16
VOS. DRAIN-TO·SOURCE VOLTAGE (VOLTS)
0
......
-50
7!!--
5.0 V
0
~
"'"
i-"'""
I----
VDS = 20 V
8. 0
-........,
0.90
~O.70
:>
---
....- r--
0
>--
:,;:
'"
h V
~ i-"'""
"./"
I<
FIGURE 6 - TRANSFER CHARACTERISTICS
1.2
:>
~
.hi ~
P
20
4.10 V
0
~
0
I
I
L
1OJ.-
.-
0
2. o
0
=25°&
TJ
7.10 V
0,
vGS = 8.0 v...,
TJ = 25°C
I
0
50
MTM/MTP3N55, 60
SAFE OPERATING AREA INFORMATION
FIGURE 10 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
FIG.URE 9 - MAXIMUM FORWARD BIASED
SAFE OPERATING AREA
10
•
...:::;iii
5-
4.0
....
2.0
'"C->z
1.0
~
-
- -
7.0
~
V
-
,
' - 100
'\
1~
~!C - 25°C
I-Package Urnit -----
r- RaS(on) Urnit
E
0.2
I0.1
1.0
~~~:a~~i~,itlllill
Single Pulse
.-
10
14
1'"
I'SP'k:
1
~
5- 10
b~s
1'\
i
_ 8.0
~
a
~ 6.0
o
de
I--
E
MTM/MTP3N55
,
Miililir
o
100
10
12
:::;
4.0
-
I-- TJ';; 150°C
MTMlMTP3N55
MTM/MTP3N60
2.0
i
:
6001000
o
o
VDS. DRAIN·TO·SDURCE VOLTAGE (VOLTS)
RlIJe
ret)
FORWARD BIASED SAFE OPERATING AREA
The dc data of Figure 9 is based on a case temperature
(Te) of 25°C and a maximum junction temperature
(TJmax) of 150°. The actual junction temperature depends on the power dissipated in the device and its case
temperature. For various pulse widths, duty cycles, and
case temperatures, the peak allowable drain current
(10M) may be calculated with the aid of the following
equation:
I
100
r-
-
I
200
300
400
500
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
600
700
rated steady state thermal resistance.
normalized thermal response from
Figures 11 or 12.
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) of Figure 10
is the boundary that the load line may traverse without
incurring damage to the MOSFET. The Fundamental
limits are the peak current, 10M and the breakdown
voltage, V(BR)OSS' The switching SOA shown in Figure
10 is applicable for both turn-on and turn-off of the
devices for switching times less than one microsecond.
The power averaged over a complete switching cycle
must be less than:
IO(25oe)[TJ(maXI - Te]
Po . RlIJe . rlt)
where
IO(25°e) = the dc drain current at Te = 25°C from
Figure 9.
TJ(max) = rated maximum junction temperature.
device case temperature.
Te
rated power dissipation at Te = 25°e.
Po
TJ(maxl - Te
RlIJe
TMOS POWER FET CONSIDERATIONS
devices due to voltage build-up on the input capaCitor due to
leakage currents or pickup.
Switching Speed - The switching speeds of these devices are
dependent on the driving impedance. Extremely fast switching
speeds can be attained by driving the gate from a voltage source.
Gate Protection - These devices do not have an internal
monolithic zener diode from gate to source. The addition of an
internal zener diode" may result in detrimental effects on the
reliability of a power MOSFET. If gate protection is required. an
external zener diode is recommended.
Transfer Characteristics - The transfer characteristics are
linear at drain currents of 2.0 Amps. (See Figure 6.) Linear amplifiers with high frequency response can be designed using this
product.
Gata Voltage Rating - Never exceed the gate voltage rating
of ±20 V. Exceeding the rated VGS can result in permanent
damage to the oxide layer in the gate region.
Handling and Packaging - MOS ICs are susceptible to damage
from electrostatic ·charge. Experience has shown that these
devices are more rugged than MOS ICs. This is primarily due
to the comparatively larger capacitances associated with
power devices, however, reasonable precautions in handling
and packaging MOS devices should be observed.
Gate Termination - The gate of these devices are essentially
capaCitors. Circuits that leave the gate open-circuited or floating
should be avoided. These conditions can result in turn-on of the
MOTOROLA TMOS POWER MOSFET DATA
C-120
MTM/MTP3N55, 60
THERMAL RESPONSE
I
~
FIGURE 11 - MTM3N55/MTM3N80
1.0
~
>.,
0.5
wz
i=1- 0.3
~ 0.2
w~
0"
~ ~ 0.1
.,I
"'oz.... 0.05
0.1
f-
0.05
-I-
zW
0.0
P"'"
~
0.0
·t~-I
(2"·
--- -Isrrmr
f-
V
0.01
0.02
0.01
0.05
0.1
Pulse train shown
Read time at 11
TJlpkl - TC - Plpkl ROJCllI
DUTY CYClE. 0 = '1/11
1......-
0.0 1
ROJCllI ' rill RflJC
ROJC - 1 67°CIW Max
o curves applv tar power
lJUl
0.01
3-
j
"""
Plpkl
rr!-
:? ~
.-
--
--
---
U
b3~
tt
.. -
._=4.~
0·0.5
IIIIII
0.1
0.5
1.0
1.0
5.0
I III II
10
20
50
I
·100
200
500
1000
I, TIME 1,",1
FIGURE 12 - MTP3N55/MTP3N80
1a
07
0-0.5
03
~
'"
~ !g
'l'~
~~
~
-
02
0.2
I-
0
__
~
i
1
0071==0.05
005 f--0.02
I L--~
~
--1111-1
~ 12 --
g
0.03
r
'"
0 02
1-diiij]--t.-..jC+-I-H-++-+-+--+-+-+-HH-1+--+-+--t---t-1
~
I--1n L.Jn L
Plpkl
DUTY CYCLE. 0 = 11/12
R'IJCIII - rill RtlJC
RIIJC - 1 67°CIW Ma,
o curves apply
tOf
power
Pulse train shown
Read time at 11
TJlpkl- TC - Plpkl ROJell1
SI~G\Er~Lf\r-1-t-~1-ItHtr-1-t-l-t1~~~~~~,,-nnT.-~r-'-,,-n~
0.01 """::...J..-'-_L.-L..!--'-Ll.J",---I.-I._~J......I...J...u..u....--L--L_.J-.J-.......u."""--J--J_.......................u..u._'-'--'--'-:-'-'-'-LL
001002
00501
02
05
10
20
5.0
10
20
50
100200
5001k
I, iiME. ims)
MOTOROLA TMOS POWER MOSFET DATA
C-121
®
MTM3N75 MTP3N75
MTM3N80 . MTP3N80
MOTOROLA
3.0 AMPERE
N-CHANNEL TMOS
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
POWER FET
rOS(on) = 7_0 OHMS
750 and BOO VOLTS
These TMOS Power FETs are designed for high voltage, high
speed power switching applications such as switching regulators,
converters, high voltage power supplies and grid drivers.
• Silicon Gate for Fast Switching Speeds Specified at 1aaoc
Switching Times
• Designers Data -lOSS, VDS(on) and SOA Specified at Elevated
Temperature
• Rugged - SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
loads
• low Drive Requirement, VG(th) =4.5 Volts (max)
o
1r
$TYlEJ
PIN 1. GATE
G 0----'11
2, SOURCE
CASEDRAtN
TMDS
s
T0-204AA
CASE 1-05
(FORMERLY TO-3)
MAXIMUM RATINGS
Rating.
Svmbol
MTM3N75 MTM3N80
MTP3N75 MTP3NBO
Unit
Drain-Source Voltage
Voss
750
800
Vdc
Drain-Gate Voltage
(RGS = 1.0 mOl
VDGR
750
800
Vdc
Gate-Source Voltage
VGS
±20
Drain Current
Continuous
Pulsed
10
10M
3.0
8.0
IGM
1.5
Gate Current -
Vdc
MTP3N75
MTP3NBO
Adc
Pulsed
Total Power
Dissipation @ TC = 25·C
Derate above 25·C
Operating and Storage
Temperature Range
Adc
Watts
Po
75
0.6
wrc
TJ, Tstg
-65to 150
·C
R8JC
1.67
·CIW
TL
275
·C
STYLE 5:
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Maximum lead Temp. for
Soldering Purposes, 1/8"
from case for 5 seconds
PIN I. GATE
Designer's Data for "Worst Case" Conditions
2. DRAIN
3. SOURCE
4.
CASE 221A-G2
TO-220AB
The Designer's Data Sheat permits the design of most circuits entirelv from the
information presented. Limit data - representing device characteristics boundaries
- are given to facilitate "worst case" design.
MOTOROLA TMOS POWER MOSFET DATA
C-122
DRAIN
MTM/MTP3N75,3N80
ELECTRICAL CHARACTERISTICS
(TC=25'C unless otherwise noted)
I
Characteristic
Symbol
Min
Max
750
800
-
Unit
OFF CHARACTERlsncs
Orain-Source Breakdown Voltage
(VGS=O, 10=5.0 mAl
V(BR)OSS
MTM3N751MTP3N80
MTM3N751MTP3N80
Zero Gate Voltage Orain Current
(VOS = 0.85 Rated VOSS, VGS=O)
TJ = l00'C
lOSS
Gate-Body Leakage Current
(VGS = 20 Vdc, VOS = 0)
IGSS
-
Vdc
mAde
-
0.25
2.5
-
500
2.0
1.5
4.5
4.0
-
-
10.5
21.0
21.0
nAdc
ON CHARACTERISTICS'
Gate Threshold Voltage
(10 = 1.0 rnA, VOS = VGS)
TJ = l00'C
VGS(th)
Orain-Source On-Voltage (VGS = 10 V)
(10 = 1.5 Adc)
(10 = 3.0 Adc)
(10 = 1.5 Adc, TJ = l00'C)
VOS(on)
Static Orain-Source On-Resistance
(VGS = 10 Vdc, 10 = 1.5 Adc)
rOS(on)
-
7.0
Ohms
9fs
0.5
-
mhos
Forward Transconductance
(VOS = 15 V, 10 = 1.5 A)
Vdc
Vdc
SAFE OPERATING AREAS
Forward Biased Safe Operating Area
See Figure 9
Switching Safe Operating Area
See Figure 10
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Ciss
(VOS =25 V, VGS = 0,
f = 1.0 MHz)
Reverse Transfer Capacitance
Coss
Crss
-
1200
pF
300
pF
80
pF
SWITCHING CHARACTERISTICS· (TJ = l00'C)
Turn-On Oelay Time
Rise Time
Turn-Off Oelay Time
-
50
ns
Ir
150
ns
Id(off)
-
200
ns
If
-
100
ns
Id(on)
VOS = 125 V, 10 = 1.5 A,
Rgen '" 50 ohms)
Fall Time
SOURCE DRAIN DIODE CHARACTERISTICS'
Symbol
TVp
Unit
Forward On-Voltage
Characteristic
IS = 3.0 A
VSO
1.0
Vdc
Forward Turn-On Time
VGS = 0
ton
250
ns
Reverse Recovery Time
See Figures 14 and 15
I"
420
ns
RESISTIVE SWITCHING
FIGURE 2 - SWITCHING WAVEFORMS
FIGURE 1 - SWITCHING TEST CIRCUIT
MOTOROLA TMOS POWER MOSFET.DATA
C-123
II
MTM/MTP3N75, 3NSO
TYPICAL .CHARACTERISTICS
FIGURE 3 - OUTPUT CHARACTERISTICS
4. 0
{VGS~ 10 V
oWY
II
0
FIGURE 4 -
i8
I
I
2.0
h
z
i;i!
'"
E
50
200
150
100
VOS. ORAIN·TO-SOURCE VOLTAGE IVOLTSI
-.........
~
~
1.0
.~
'"
9
0.90
~
0.80
~
!
:>
4. 0
~
"
-25
II /
25
i'-.
50
75
1
-.......
//
100
125
2.0
--r---
_0
4.0
I
=--
-~
~
_r-
-
:i
5
;;: 800
.0
;:'i
.Of----- f-- TJ - -55°C
1.0
400
1
2.0
3.0
f-----
'---
~
tj 1200
TJ I= 25°~
"I
I
TJ = 25°C VGS =0
f = 1 0 MHz
VGS = 10 V
1600
.0
10
8.0
6.0
FIGURE 8 - CAPACITANCE VARIATION
2000
TJ-l00°C
'fI
VGS. GATE-TO-SOURCE VOLTAGE IVOLTS)
FIGURE 7 - ON-RESISTANCE versus
DRAIN CURRENT
:---
t
TJ = 100°C
'1/
...? ~
0
150
TJ. JUNCTION TEMPERATURE I"CI
0
1/ r - -
0
"-.
0.70
-50
I / /1
=-55°C - j /----; f-TJ =25°C
0
'"
20
12
16
4.0
8.0
VOS. ORAIN-TO-SOURCE VOLTAGE (VOLTSI
VDS = 20 V
:>
'"
VGS = 4.0 V
TJ
VOS c VGS·
10 . lOrnA
~
I
--
5. 0
1.1
I
FIGURE 6 - TRANSFER CHARACTERISTICS
1.2
~
VGS= 6.0 V
VGS = 5.0 V
~V
L
0
250
~
k:: --.....-
IV
/
1. 0
- - f-----
FIGURE 5 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
~
,.,.- ~ f--
~
0
«
VGS= 10V ~
:5-
VGS = 4.0 V
'"~
TJ = 25°C
~ 3.0
VGS! 6.0 V
0
~
j
TJ; 25°C
VGS = 5.0 V
~
ON-REGIONCHARACTERlsncs
4. 0
5.0
10. DRAIN CURRENT (AMPS)
o
o
\
r-....
Ciss
,\
\\
\ ['....
Coss
Crs........
10
20
30
40
VOS. ORAIN-TO·SOURCE VOLTAGE WOLlS)
MOTOROLA TMOS POWER MOSFET DATA
C-124-
50
MTM/MTP3N75, 3N80
SAFE OPERATING AREA INFORMATION
RGURE 9 - MAXIMUM RATED FORWARD BIASED
SAFE OPERATING AREA
0
--
FIGURE 10 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
10
--
-~
100~
-
rOS(on) limit Package limit 1~ Thermal Limit
- - -
~:.
e we
-
3
~ 6.0
6
.W
BOO
FORWARD BIASED SAFE OPERATING AREA
The dc data of Figure 9 is based on a case temperature
(TC) of 25°C and a maximum junction temperature
(TJ(max)) of 150°. The actual junction temperature depends on the power dissipated in the device and its case
temperature. For various pulse widths, duty cycles, and
case temperatures, the peak allowable drain current
(10M) may be calculated with the aid of the following
equation:
10M
a
o
RWC
r(t)
MTM MTP3NBO- -
200
....
400
600
BOO
VOS. ORAIN·TO-SOURCE VOLTAGE IVOLTSI
1000
= rated steady state thermal resistance.
= normalized thermal response from Figure
11 or Figure 12.
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) of Figure 10
is the boundary that the load line may traverse without
incurring damage to the MOSFET. The fundamental limits are the peak current, 10M and the breakdown voltage,
V(BR)OSS' The switching SOA shown in Figure 14 is
applicable for both turn-on and turn-off of the devices
for switching times less than one microsecond.
The power averaged over a complete switching cycle
must be less than:
= I (25 C)[TJ(max) - TC]
o
MTM MTP3N75---
- 2.0
MTM MTP3N75
II
I I I
M ~rr3NfO
10
100
VOS. ORAIN·TO-SOURCE VOLTAGE (VOLTS)
TJ'" 150°C
~ 4.0
o
--
.-
VGS = 20V
T =
Singl. Puls._: _: :_:
0.0 1
t.O
~
....
r-
--._-
-l::
1.0m
10m
dc
_.
•
~ 8.0
"10..
.0
0
Po . RWC . r(t)
where
IO(25°C) = the dc drain current at TC = 25"C from
Figures 9 and 13.
TJ(max) = rated maximum junction temperature.
TC
= device case temperature.
Po
= rated power dissipation at TC - 25"C.
TJ(max) - TC
RWC
TMOS POWER FET CONSIDERATIONS
Switching Speed - The switching speeds of these devices are dependent on the driving impedance. Extremely fast switching speeds can be attained by driving
the gate from a voltage source.
build-up on the input capacitor due to leakagecurrents
or pickup.
Gate Protection - These devices do not have an internal monolithic zener diode from gate to source. The
addition of an internal zener diode may result in detrimental effects on the reliability of a power MOSFET. If
gate protection is required, an external zener diode is
recommended.
Transfer Characteristics - The transfer characteristics
are linear at drain currents of 500 mAo (See Figure 6.)
Linear amplifiers with high frequency response can be
designed using this product.
Gate Voltage Rating - Never exceed the gate voltage
rating of ±20 V. Exceeding the rated VGS can result in
permanent damage to the oxide layer in the gate region.
Handling and Packaging - MOS ICs are susceptible to
damage from electrostatic charge. Experience has
shown that these devices are more rugged than MOS
ICs. This is primarily due to the comparatively larger
capacitances associated with power devices, however,
reasonable precautions in handling and packaging MOS
devices should be observed.
Gate Termination - The gate of these devices are essentially capacitors. Circuits that leave the gate opencircuited or floating should be avoided. These conditions can result in turn-on of the devices due to voltage
MOTOROLA TMOS POWER MOSFET DATA
C-125
MTM/MTP3N75,3N80
THERMAL RESPONSE
AGURE 11 -
MTM3N75/MTM3N80
1.0
~
wz
0" 0.5
OJi
>"
~ ~ 0.2
""
~ ~ 0.1
:Ow
""
"'""
~;; 0.0 5
zw
:g ~
0.0
~ 0.0
0.05
~f..---
0.02
--
0.1
w~
---_...
---
;;;- -.-"
-r"
_.
-
--
3---0.01
.......
~
0.02
---
~'nl
'"
Ynmr-
~
0.05
0.1
....
-
-
~
~
~C
~~
~~
~~
~-
g
0.7
_-
._ ..
't:;_1
--_ ....
.-
DUTY CYCLE. '0 '1 /1 2
±ITIn
--:-~
-_ ..._-
--
---
0.5
1.0
2.0
5.0
10
---
RIJJCII) c rlti RIJJC
RIJJC 1.67°C/W Max
0
D curves ~pply for power
Pulse tram shown
-- -
Read lillie at IJ
TJlpk)
TC
PIpk) RIJJClti
I
50
20
-"-- .-
--
---
I
0.2
100
200
500
1000
I, TIME (illS!
FIGURE 12 -
u
.. -
..
2-
0.0 1
-- --
....
tl
~ ~ 0.3
MTP3N75/MTP3N80
0-0.5
0.5
03
0.2
0.2
-- O.r
P1pk)
1
0.07 t=:.O.05
tJUl
005 '---- 0.02
I -L.-- _
0.03
002
ROJcll1 rill ROJC
ROJC - 1.67°C/W Max
c-f-- --
i-"
-oo'I--:b--¥'f--+++++--f-f--+-++++++f-+-+-t-H
o curves apply for power
~ ~_I
DUTY CYCLE.
Pulse train shown
Read time at 11
TJlpk) - TC =Plpk) ROJCII)
0=11/12
t~~~1C:~S~LGflLEliP~Ll~5\t=1=t=1=t1l1nt=1=t=1=t1Jlra:J[r::CIJJJID::[]:J[]JJDI~
0.01
0.01
0.02
0.05
0.1
0.2
05
10
20
5.0
10
20
. t. TIME 1m,)
MOTOROLA TMOS POWER MOSFETDATA
C-126
50
100
200
500
lk
®
MTM4N4S, MTP4N4S
MTM4NSO, MTP4NSO
MTMSN3S, MTPSN3S
MTMSN40, MTPSN40
MOTOROLA
Designer's Data Sheet
4.0 and 5.0 AMPERE
N-CHANNEL TMOS
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
POWER FET
=
'DS(on)
1.5 OHMS
450 and 500 VOLTS
These TMOS Power FETs are designed for high voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds Specified at 100'C
roS(onl = 1.0 OHM
350 and 400 VOLTS
Switching Times
• Designer's Data - lOSS. VDS(on). SOA and VGS(th)
Specified at Elevated Temperature
• Rugged -
SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With
Inductive Loads
a
lr
STYLE 3
PIN I. GATE
2. SOURCE
CASE DRAIN
Go---,
~ T~;
I
_ TJ; 25°C
B.O
.!?
FIGURE 4 - MTM4N45, MTM4N50
MTP4N45, MTP4N50
MTM5N35, MTM5N40
MTr:'5N35, MTP5N40
4.0
B.O
12
16
VOS, ORAIN· TO·SOURCE VOLTAGE (VOLTS)
20
TRANSFER CHARACTERISTICS
FIGURE 5 - MTM5N35, MTM5N40
MTP5N35, MTP5N40
10
!--
8.0
FIGURE 6 - MTM4N45, MTM4N50
MTP4N45, MTP4N50
,
8.0
II
.1
_!
VOS; 3D V
1//
Ib
VOS;30V
~ 6.0
;;;-
~
~ 6.0
1i'i
~
84.0
z
~
II!
13
.!? 2.0
o
o
f--
125°C
I
//J
'II/",
.!?
2. 0
0
60
60
10
-
25°C
"~I
/, If-
-55°C
I
f---
III
TJ; 100°C
Q
~V
40
~O
4. 0
~
.. -
J
z
.£
TJ; 25°C
~
Q
/
~
I
J
VI
2,0
vGS, GATE·TO·SOURCE VOLTAGE (VOLTSj
c---55°C
-::. ~
4.0
6.0
8.0
VGs. GATE-TO·SOURCE VOLTAGE (VOLTSj
10
ON-RESISTANCE versus DRAIN CURRENT
FIGURE B - MTM4N45, MTM4N50
MTP4N45, MTP4N50
FIGURE 7 - ON-RESISTANCE versus DRAIN CUURRENT
2. 0
TJ
2
-- -
1100O~
25°C
.,/
f.-.--
-
..---
:I:
'/
i-"
2.4
:1
~
2.0
il5
1.6
~
:--
z
;;;:
4.0
6.0
10, DRAIN CURRENT (AMPSj
8.0
~
E'
0.8
0
...J....-
i----'r"
-55°C
0
2.0
MOTOROLA TMOS POWER MOSFET DATA
C-129
I
TJ _100°C
25°C
'" 0.4
~
10
,...... -
~
~
'-'
VGS=lOV
2.0
I--VGS; 10V
'"~
~ 1.2
~
-~
-55°C
o
o
~. 2.B
/'
4.0
6.0
10. DRAIN CURRENT (AMPSj
B.O
10
MTMlMTP4N45, 50/5N35, 40
TYPICAL CHARACTERISTICS (continued)
FIGURE 9 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
5
FIGURE 10 - CAPACITANCE VARIATION
2000
1.2
~a:~
..........
1.1
~
VoS ~ VGS
""'" """
to
~
1.0
g
9
~ 0.90
13
!!l
~
oS
lj 1200
"""
:
'"
0.80
~
"'-
£
~ 0,70
25
-25
-50
>
50
.\
g
I'---.
75
100
125
\\
\ ['...
C...
C"......
o
o
150
Cil'
l\
400
........
I
"-
800
c::l
u
"'
I
-
1600
lo~1.0mA
w
I
TJ ~ 25°C - VGS ~ 0
_.
I ~ 1.0 MHz
10
TJ. JUNCTION TEMPERATURE (OCI
20
30
40
VoS. oRAIN-To·SoURCE VOLTAGE (VOLTS)
50
THERMAL RESPONSE
FIGURE 11 - MTM4N45, MTM4N50, MTM5N35, MTM5N40
1.0
~
0-0.5
0.5
W",
~;
~.l
0.3
tt! f3 0.2
'"
0"
0.1
0.05
.. %
0.02
...
w-'
~ ~ 0.1
:EIa:: .... 0,05
0",
zW
:E ~ 0,03 ~
......-
0.02 - -
0.0 1
0.01
-.
,. ,....
0.02
I--
--
-
".
;;;.-
Plpkl
0.05
0.1
R9JCIII " rill RHJC
R9JC " 1.67°C/W M..
D curves apply fOf powef
DUTY CYCLE. D= '1/2
TJlpkl. '- TC = P(pkl R9JCI1I
~-I
r- 12·
~?Ql.
frrmr
lnn
--1'1
I
0.2
0.5
1.0
2.0
Pulse tram shown
Read orne at t 1
II III
5.0
II III
10
50
20
100
200
500
1000
t. TIME (ms)
FIGURE 12 - MTP4N45, MTP4N50, MTP5N35, MTP5N40
'-'
~
u;
lIi_
c.I ~
!c.I
~I
1.0
0.7
0.5
0=0.5
0.3
0.2
0.2
c--
--.-:
.... :;;;0-
01
~
o.
1
0.07 ~0.05
~- 0.05
_.0.02
~ 0.03
1ii!E
~
0.02
~
......t'1
0.01
0.01
0.02
P(pkl
DUTY CYCLE. 0 = 11/12
St~G~E rlL~
0.1
o
h~~
V
0.05
RruC(t)
r(t! ROJC
1.67'CIW Max
RruC
curves apply for power
Pulse train shown
Read time at tl
Tj(pk) - TC'= P(pk) ROJClt)
tnn
0.2
0.5
1.0
. 2.0
5.0
t TlME(...)
10
20
MOTOROLA TMOS POWER MOSFET DATA
C-130
50
tOO
200
500
1k
MTM/MTP4N45, 50/5N35, 40
RATED SAFE OPERATING AREA INFORMATION
FORWARD BIASED SAFE OPERATING AREA
FIGURE 13 - MAXIMUM RATED FORWARD BIASED
SAFE OPERATING AREA
5
0
- - ,..--- -
- - --I0.1 ms
The de data of Figures 13 ~nd 14 is based on a case temperature
ITel of 25°e and a maximum junction temperato·re ITJmaxl of
150°, The actual junction temperature depends on the power
dissipated in the device and its case temperature. For various
101,,~
pulse widths. d.uty cycles, ~nd case temperatures, the peak allow-
0
able drain current (10M) may be calculated with the aid of the
following equation:
1.0 ms
0
I'-.
10 ms
e
-
0
r-.....
10M
rOSlonl limit
-- --- Paclcage limit
Thermal
limit
5
o
3 Te - 25°C
MTM/MTP5N35- ".."....
VGS = 20 V. Single Pulse MTM/MTP5N40
0.1
10
30
50
100
300
500
1000
VOS. ORAIN·TO·SOURCE VOLTAGE IVOLTSI
FIGURE 14 - MAXIMUM RATED FORWARD BIASED
SAFE OPERATING AREA
0
-
0.1 mi-
10ms
I'-.
de
.0
"
rOSIOflILimit
.5 ----Plclclge Limit
Thermillimit
2
.1
TC = 25°C
VGS = 20 V. Single Pulse
30
where
IO(25°q = the dcdrain current at Te = 25°C from Figures 13
and 14
TJlmaxl = rated maximum junction temperature
::: device case temperature
TC
Po
::: rated power disSipation at lC ::: 25°C
R8JC
rlt)
::: rated steady state thermal resistance
:; normalized thermal response from Figures 11
and 12
TJlmax)- Te
MTM/MTP4N45
50
r<:::
R8JC
I MTM/MTP4N50 i 100
300
500
1000
VOs. DRAIN-TO-SOURCE VOLTAGE (VOLTSI
FIGURE 15 - MAXIMUM RATED
SWITCHING SAFE OPERATING AREA
4
2
0
0
01-- 0
2. 0
0
TJ';;150oC
MTM/MTP5N35 MTM/MTP5N40
r-
MTM/MTP4N45
MTM/MTP4N50
100
200
300
400
VOs. ORAIN-TO·SOURCE VOLTAGE IVOLTSI
1
r(t~
The switching safe operating area (SOAI of Figure 15. is the
bou ndary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the peak
current. 10M and the breakdo·wn voltage. VIBR)OSS. The
switching SOA shown in Figure 14 is applicable for both turn-on
and turn-off of the devices for switching times less than one
microsecond.
The pO"Yer averaged over a complete, switching cycle must be
less than:
1.0 ms
I'-.
o . R8JC .
SWITCHING SAFE OPERATING AREA
10"s
.0
.0
r
= I 125oq[ TJlmax) - Te
500
MOTOROLA TMOS POWER MOSFET DATA
C-131
MTMSN18, MTPSN18
MTMSN20, MTPSN20
MTM7N12, MTP7N12
MTM7N1S, MTP7NlS
•
®
MOTOROLA
Designer's Data Sheet
5.0 and 'l.0 AMPERE
N·CHANNEL TMOS
POWER FET
=
=
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
rDS(on)
1.0 OHM
1ao and 200 VOLTS
rDS(on)
0.7 OHM
120 and 150 VOLTS
These TMOS Power FETs are designed for low voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds -,. Switching Times
Specified at 100·C
L~'"=f
MTM6N18
MTM5N20
MTM7N12
MTM7N15
• Designer's Data ~ lOSS, VDS(on), VGS(th) and SOA
Specified a~ Elevated Temperature
T; .
D
K
__..1
~
@
,~-'=:tt~Tl
.
• Rugged - SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
Loads
Q.
1
•
.
u
11[
NOTES:
I.OIMENSIOMSQANOVAREOATUMS.
2. [!J ISUATING I'I.AJ'I~ AND DATUM.
3. POSITIONAL TOLERANCE ~OR
MOUNTING HOLE 0:
STI'LE3
PIN!. GAH
2. SOUlleE
.~ASE
..
'.~
H
1+lt.13!O.0051@ITlv@1
DRAIN
FORHADS'
1+1t.t3(o.lIQij@)Tlvelo®1
4.DIMEi'fSIONSANOTOLEIlANCESPER
ANSI VI4.5. 191!.
GO--~
TMDS
S
MAXIMUM RATINGS
Rating
Symbol
Drain-Source Voltage
Drain·Gate Voltage
(RGS = 1.0 MO)
MTM orMTP
Unit
7N12
7N15
5N18
5N20
VDSS
120
150
180
200
Vdc
VDGR
120
150
180
200
Vdc
Gate·Source Voltage
VGS
Drain Current
Continuous
Pulsed
ID
IDM
Gate Current - Pulsed
IGM
Vdc
±20
Adc
Total Power
7.0
18
Operating and Storage
Temperature Range
Wans
W/oC
-65 to 150
°c
R8JC
1.67
°C/W
TL
275
°C
THERMAL CHARACTERISTICS
Thermal Resistance
Junction 10 Case
Maximum lead Temp. for
Soldering Purposes. 1/8"
from case for 5 seconds
MTP5N18
MTP5N20
MTP7N12
MTP7N15
Adc
1.5
75
0.6
TJ. Tstg
(T0-3 TYPE)
5.0
15
PD
Dissipation @ TC = 25°C
Derate above 25°C
CASE 1-115
TO·204AA
of
D
NOTES:
1. DIMENSION HAPPUE$TO ALL LEA08.
2.0IMEIiSIONLAPPUESTOLEAOStAN030NLV.
3.0IMENSlDNZDEFINESAZDNEWIlEREALL
80DVANO LEAD IRREGULARtT1ESARE
AllOWED.
..'
4. O'MeHSIDNING AND TOURANCING P£II AMI
V14.51813.
6.CONTRDLlINClOIMENSION:INCH.
s
STVLE 5;
PIN 1. GATE
2. DRAIN
J. SOURCE
4. DRAIN
Designer"s Data for "Worst Case'" Conditions
The DeSigner's Data Sheet permits the design of most circuits entirely from the
information presented. limit data - representing device characteristics boundaries - a"re
.given to facilitate "worst case" design.
CASE 221A-02
TO·220AB
MOTOROLA TMOS POWERMOSFET DATA
C-132
MTM/MTP5N18, 20/7N12, 15
I
ELECTRICAL CHARACTERlSTICS (TC 0 25°C unless otherwise noted)
I
Characteristic
Symbol
Min
Max
120
150
180
200
-
Unit
-
J
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS 0, 10 5.0 mAl
=
MTM7N12/MTP7N12
MTM7N 15/MTP7N 15
MTM5N 18/MTP5N 18
MTM5N20/MTP5N20
Zero Gate Voltage Drain Current
(VOS 0.85 Rated VOSS, VGS 0 0)
ITJ 100°C)
lOSS
Gate-Body Leakage Current
(VGS 20 Vdc, VOS 0)
IGSS
=
=
=
Vdc
V(BR)OSS
=
=
-
mAdc
-
0.25
2.5
2.0
1.5
4.5
4.0
-
0.7
-
1.0
-
5.9
-
5.0
-
6.0
-
5.0
1.5
-
1.5
-
500
nAdc
ON CHARACTERISTICS'
Gate Threshold Voltage
(10 1.0 mA. VOS VGS)
(TJ 100°C)
=
=
Static Drain-Source On-Resistance
(VGS 10 Vdc; 10 3.5 Adc)
=
=
IVGS 0 10 Vdc, 10 =2.5 Adc)
rOS(on).
MTM7N 121MTM7N 15
MTP7NI21MTP7NI5
MTM5N18/MTM5N20
MTP5N18/MTP5N20
Orain-Source On-Voltage (VGS - 10 V)
MTM7NI21MTM7NI5
110 7.0 Adc)
MTP7NI21MTP7NI5
MTM5NI8, MTM5N20
(10 3.5 Adc, TJ 100°C)
MTP5N 18/MTP5N20
MTM7N 12/MTM7N 15
110 5.0 Adc)
MTP7N 121MTP7N 15
MTM5N IS/MTM5N20
110 2.5 Adc, TJ 100°C)
MTP5N 18/MTP5N20
=
=
=
=
Vdc
VGS(lh)
=
VOS(on)
=
=
Forward Transconductance
(VOS 0 15 V, 1003.5 A)
Vdc
9fs
MTM7NI21MTM7NI5
MTP7N 121MTP7N 15
MTM5N18/MTM5N20
MTP5N 18/MTP5N20
(VOS 0 15 V, 1002.5 A)
Ohms
mhos
DYNAMIC CHARACTERISTICS
Input Capacita nee
Output Capacita nce
IVoS = 25 V, VGS = 0, f 0 1.0 MHz)
f---"Fc--+---~-t---'--=--Ic---'--;:,----i
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS' (TJ 01 OO°C)
tdlon)
Ir
-
20
ns
(VOS 0 25 V, 10 = 0.5 Rated 10,
150
ns
Rgen = 50 ohms,
See Figures 1 and 2)
tdlof!)
tf.
-
50
ns
50
ns
Turn-On Oelay Time
Rise Time
Turn-Off Oelay Time
Fall Time
SOURCE DRAIN DIODE CHARACTERISTICS'
Characteristic
Forward On-Voltage
Forward Turn-On Time
Reverse Recovery Time
.. Pu Ise Test: Pulse Width
~300
I
I
I
Symbol
Typ
Unit
liS = Rated ID'
VSD
2.0
Vdc
VGS 0 0,
ton
200
ns
t"
300
ns
IJ.s, Duty Cycle ~2%.
FIGURE 2 - SWITCHING WAVEFORMS
FIGURE 1 - SWITCHING TEST CIRCUIT
td(onl
Output, Vout
Inverted
MOTOROLA TMOS POWER MOSFET DATA
C-133
MTMlMTP5N18, 20/7N12, 15
TYPICAL CHARACTERISTICS
ON-REGION CHARACTERISTICS
FIGURE 4 - MTM7N12. MTM7N16
MTP7N 12. MTP7N 16
FIGURE 3 - MTM6N18. MTM6N20
MTP6N18. MTP6N20
0
v- y
VGS" 20
10 V
TJ = 2SoC
.0
7"
10
.......- V
--
~
l.?-: v:;: "'~
-
8.0
8.0 V
7.0 V
~
IF"
Ail""
'"
hV
:::I
'-' 40
~ .
/$
~
c
.!?
s.o V
r
o
o
10
6.0V
....-
5.0V
L- ,.....
2.0
4.0 V
.0
6.0
4.0
8.0
VOs. ORAIN·TO·SOURCE VOLTAGE (VOLTS)
I--
7.0V
/// V
I
6.0 V
~
0
TJ =25°C
;: 6.0
VGS=8.0V
/ ,/
/, V
~
:;;
V
r-r- .y ....-
10V
§. ~
AV
.0
f-----./
VGS=20V
~
4.0V f--2.0
4.0
6.0
8.0
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
10
TRANSFER CHARACTERISTICS
FIGURE 6 - MTM6N18. MTM5N20
MTP6N18. MTP6N20
0
.0
VOS = 10 V
10
I /
II /
'if
25°C- H '/
/U ~100°C
TJ = -SSOC- ~
.0
.0
A
h
0
FIGURE 6 - MTM7N12. MTM7N15
MTP7N 12. MTP7N 15
~
~
i
I //
TJ= 100oC.~
8.0
VDS=10V
TJ = ZsoC
I V
IP. I- -55°C
6.0
'"
If
~
4.0
.,/
!i!
c
/1/
.!?
~
0 f:;:/'
'II
2.0
,///
o
o
1
8.0
4.0
6.0
2.0
VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)
//
',---/- ~/
~ '?'
2.0
4.0
6.0
8.0
VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)
10
ON-RESISTANCE versus DRAIN CURRENT
FIGURE 7 - MTM6N18. MTM6N20
MTP5N18. MTP5N20
.S
.2
TJ= 1000
y
/
;;; 1.0
:;;
V
:>:
i
e
/'
./
.- k-1
2SoC_ V
-55°C
FIGURE 8 - MTM7N12. MTM7N15
MTP7N12. MTP7N16
I--
V
V
.,
.L.
~
0.8
~SOC
~ 0.4
-SsoC
:::I
..,.
C>
~
VGS = 10 V
is
0.2
4.0
6.0
10. DRAIN CURRENT (AMPS)
8.0
10
~
0
o
2.0
4.0
6.0
10. DRAIN CURRENT (AMPS)
MOTOROLATMOS POWER MOSFET DATA
C-134
....-
VGS = 10 V
t
2.0
V
TJ = 100°C
0.6
iii
8.0
10
MTM/MTP5N18, 20/7N12, 15
TYPICAL CHARACTERISTICS
FIGURE 9 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
§"
::l
""
~
""-
1.1
'"c
""cto
""" """
1.0
:>
~
iJi
~
1=
0.90
~
0.80
VOS =VGS
10 =1.0 mA
"""-
~
w
'"
FIGURE 10 - CAPACITANCE VARIATION
100a
1.2
TJ = 25°C
I'-.,
o~
i'-.-
'" '"
10.70
-50
75
50
25
-25
r~s, ~o °MHz
a
'"
>
80
100
20 o
"""
125
a
Ciss
I
'\
\ ...... ~Crss
c!ss
50
10
40
20
30
VOS. ORAIN-TO·SOURCE VOlTAGE (VOLTS)
150
TJ. JUNCTION TEMPERATURE (OC)
THERMAL RESPONSE
FIGURE 11 -
MTM7N12. MTM7N15. MTM5N18 AND MTM5N20
~ 1.0
IIi ~~
0:0.5
~
o-J;.!..
;;i
O. 1
0-0.05
~
0.07
0-0.01
rJlJL
I--
Plpkl
..I-
~ 0.05
ffi~
.....
_r-
0-0.2
0.3
~ 0.2
"'"
SINGLE PULSE
Pulse Iram shown
Read time al '1
-I
1-12
DUTV CVCLE. D 0 '1/'2
0.03
0.0 1
0.01
o curves apply tor power
~
--1 I,
~ 0.02
~
RBJCIII =,It) RBJC
R8JC = 1 67°C/W Max
JLLLlJL j i l l
0.02 0.03
0.05
01
0.2
0.3
0.5
1.0
20
3.0
5.0
t. TIME (ms)
10
20
TC
TJlpkl
30
11 111
50
P1pk) R8JClti
I
I
100
200
300
500
1000
FIGURE 12 - MTP7N12. MTP7N15. MTP5N18 AND MTP5N20
~ 1.0
,.~
0.7
r-
D - 0.5
-
~ 0.5
~ 0.3
D 0.2
~ 0.2
D 0.1
~
~
rJlJL
~I--I
"'"
D 0.01
i= 0.05
"'
P/pkl
0.05_
0.1
10.07
~
....
0.02 ..... .....
g 0.0 1
II III
0.02 0.03
Pulse ir'ain shown
Read time at 'I
TJlpk)- TC = P1pk) R8JCII)
'2OUTY CVCLE. a 0'1 /' 2
0.03
0.01
R8JCII) = ,It) R6JC
ReJC = I 67 6 C/W Max
o curves applv for power
0.05
0.1
0.2
0.3
0.5
1.0
2.0
3.0
5.0
10
I I
20
II II
3D
I. TIME 1m,)
MOTOROLA TMOS POWER MOSFET DATA
C-135
50
100
I
I
200
I
JOO
500
1000
MTM/MTP5N18, 20nN12, 15
SAFE OPERATING AREA INFORMATION
MAXIMUM RATED FORWARD BIASED SAFE OPERATING AREA
FIGURE 13 - MTM5N18. MTM5N20
MTP5N18. MTP5N20
-
r--r
---I-.
-J.ttt-
-I--
FIGURE 14 - MTM7N12. MTM7N15
MTP7N12. MTP7N15
10
10 ",
::::::: --
:::~
1=
100
-~
,
Ij.~m~
1\
/
rOS(on) limit---~ Package Limit ~Therm.1 Limit
VGS= 20 V
Single pUI;etw,
1.0 m
Ill..
"\.
~'rOS(on) Li·m~ -
cdc
VGS=20V
Single Pul.e
Te = 25 0 e
~~~e- f-~~~i~m~~g-<
0.2
1.0
10
100 ISO
VOS. DRAIN·TO-SOURCE VOLTAGE (VOLTS)
IO(25°C) = the de drain current at TC= 25°C from Figures 13
and 14
TJ(maxl ;;:; rated maximum junction temperature
;;:; device case temperature
TC
:;:: fated power dissipation at Te:; 25°C
Po
:;;: rated steady state thermal resistance
ROJC
r(tl
= normalized thermal response from Figures 11
and 12
Thede data of Figures 13and 14 is based ana case temperature
(TC) of 25°C and a maximum junction temperature (TJmax) of
150°, The actual junction temperature depends on the power
dissipated in the device and its case temperature. For various
pulse widths, duty cycles, and case temperatures, the peak allow~
able drain current (10M) may be calculated with the aid of the
following equation:
1
SWITCHING SAFE OPERATING AREA
= I (25ocJ TJ(maxl - TC
ROJC . r(t~
o l"o .
M M/MT 7N12
MTM/MTP7N15
where
FORWARD BIASED SAFE OPI;RATING AREA
10M
c
Packago UmR- - Thenmal Limit
10
100 2 0
VOS. ORAIN-TO-SOURCE VOLTAGE (VOLTS)
1.0
10".
10 m.
10 m.
,~'
I~b~
The switching safe operating area (SOA) of Figure 15, is the
boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the peak
current. 10M and the breakdown voltage. V(BRIOSS. The
switching SOAshown in Figure 15 isapplicableforboth turn-on
and turn-off of the devices for switching times less than one
microsecond.
The power averaged over a complete switching cycle must be
less than:
FIGURE 15 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
20
16
~
!
i
MTM/MTP7NI2
12
MTM/MTP7NI5
0::
--
MTM/MTP5N18
a
8.0
z
..
MTM/MTP5N20
IS
.5>4.0
TJ" 1500 C
o
o
40
80
120
160
VOS. ORAIN-TO-SOURCE VOLTAGE (VOLTS)
200
MOTOROLA TMOS POWf;R MOSFET DATA
C-136
®
MTM6N55
MTM6N60
MTH6N55
MTH6N60
MOTOROLA
Designer's Data Sheet
6.0 AMPERE
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
N-CHANNEL TMOS
POWER FET
These TMOS Power FETs are designed for high voltage, high
speed power switching applications such as line operated switching regulators, converters, solenoid and relay drivers.
rDS(onl
1.2 OHMS
550 and 600 VOLTS
• Silicon Gate for Fast Switching Speeds Specified at 100°C
=
Switching Times
• Designer's Data - IDSS, VDS(on), VGS(th) and SOA Specified
at Elevated Temperature
1rr
;j1 ]] ~
O""N"
~ ~I~·., ,.
v.
~ a@:.;J.
• Rugged - SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
Loads
tI
T
'.'
mu~
PIN1. BATE
2. SOURCE
CASE DRAIN
TMOS
s
MAXIMUM RATINGS
Symbol
MTM6N55
MTH6N55
MTM6N60
MTH6N60
Unit
Drain - Source Voltage
VOSS
550
600
Vdc
Drain - Gate Voltage
(RGS = 1.0 m!l)
VDGR
550
600
Vdc
Rating
Gate - Source Voltage
Drain Current
Continuous
Pulsed
Gate Current -
VGS
±20
Vdc
Adc
10
10M
Pulsed
Total Power
Dissipation @TC = 25·C
Derate above 25·C
Operating and Storage
Temperature Range
6.0
30
IGM
1.5
Adc
Po
150
Watts
1.2
wrc
TJ, Tstg
-65 to 150
·C
Thermal Resistance
Junction to Case
Maximum Lead Temp. for
Soldering Purposes, 1/8"
from case for 5 seconds
CASE 1-05
TO-204AA
(Formerly TO-3)
MTH6N55
MTH6N60
,
STYLE 2:
PIN 1. GATE
THERMAL CHARACTERISTICS
2,DRAIN
RWC
0.83
·CIW
TL
275
·C
3 SOURCE
4,DRAIN
Designer's Data for "Worst Case" Conditions
The Designer's Data Sheet permits the design of most circuits entirely
from the information presented. Limit curves - representing boundaries
on device characteristics - are given to facilitate "worst case" design.
MOTOROLA TMOS POWER MOSFET DATA
C-137
,
~
u
CASE 340-01
TO-218AC
MTMIMTH6N55, 60
" ':".
,
Characteristic
Symbol
Min
Nlax
550
-
,Unit
OFF CHARAcTERISTICS
Drain-Source B,reakdown Voltage
MTM6N55/MTH6N55
(VGS =: 0,10 = 5.0 rnA)
MTM6N60/MTH6NSO
V(BR)OSS
600
Zero Gate Voltage Drain Current
(VOS = 0.85 BVOSS, VGS = 0)
TJ = 100"C
lOSS
Gate-Body Leakage Current
(VGS = 20 Vdc, VOS = 0)
IGSS
Vdc
-
mAdc
-
0.25
2.5
-
500
2.0
1.5
4.5
4.0
nAdc
ON CHARACTERISTICS·
Gate Threshold Voltage
(10 "" 1.0 rnA, VOS = VGS)
TJ = 100'C
Drain-Source On-Voltage (VGS
(10 = 3.0 Adc)
(10 = S.O Adc)
(10 = 3.0 Adc, TJ = 100'C)
Vdc
VGS(th)
=
10 V)
VOS(on)
Static Drain-Source On-Resistance
(VGS = 10 Vdc, 10 = 3.0 Adc)
-
rOS(on)
Forward Transconductance
(VOS = 15 V, 10 = 3.0 A)
2.0
9fs
Vdc '
3.S
9.0
7.2
1.2
Ohms
-
mhos
SAFE OPERATING AREAS
Forward Biased Safe Operating Arl1a
,See Figur'! ,9
Switching Safe Operating Area
See Figure 10 .
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
-
1800
pF
Coss
350
pF
Crss
-
150
pF
Ciss
(VOS = 25 V, VGS
f = 1.0 MHz)
= 0,
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS' (TJ = 100'C)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
(VOO = 125 V, 10
Rgen
Idlon)
-
60
ns
Ir
-
150
ns
Id(off)
-
200
ns
If
-
120
ns
= 3.0 A,
= 50 ohms)
Fall Time
SOURCE DRAIN DIODE CHARACTERISTICS'
Symbol
Typ
Unit
Forward On-Voltage
Characteristic
IS = S.OA
VSO
1.3
Vdc
Forward Turn-On Time
VGS = 0, dildt = 25 A/IJS
Ion
175
ns
Irr
600
ns
Reverse Recovery Time
*Pulse Test: Pulse Width E>.300 J.LS. Duty Cycle "'"'2"10.
RESISTIVE SWITCHING
AGURE 1 _ SWITCHING TEST CIRCUIT
FIGURE 2 -
SWITCHING WAVEFORMS
Oulput, Vout
Inverted
MOTOROLA TMOS POWER MOSFET DATA
C-138
MTM/MTH6N55, 60
TYPICAL CHARACTERISTICS
RGURE 3 - OUTPUT CHARACTERISTICS
10
f
8.0
It. -
VGS ~ 10 Volts
I- -
VGS ~ 7.0 Volts
FIGURE 4 - ON-REGION CHARACTERISTICS
10
VG~ ~ 6.0 IVolts
u;- 8.0
TJ: 25°C
i
z
~
Q
E
~
VGS : 5.0 Volts
60
6.0
z
4.0
~
,
E
VGS : 4.0 Volts
2.0
50
100
150
200
250
~
"--..
1.0
~
"--..
0.90
5
S
~
'-..,
E
........
..........
25
50
75
100
125
a
2.0
-
= 1100"c
I--
V
1600
--
1550C
4,0
6.0
6,0
10
8.0
FIGURE 8 - CAPACITANCE VARIATION
VGS
2,0
'"""" ~4.0
2000
TJ - 25"C
TJ
VOS:20V
VGS, GATE TO SOURCE VOLTAGE (VOLTS)
FIGURE 7 - ON-RESISTANCE versus
DRAIN CURRENT
I--ITJ
TJ: 11000C
/JI
TJ, JUNCTION TEMPERATURE 1°C)
a
"A
1(//
2.a
a
150
-I
"
Q
~
-25
J
4. a
;2
"
'"""
0.10
-50
It h{TJ': 25°~
II
6. a
~
~
~ 0.80
:>
III /
A L
~
~
>-
~
8. 0
'"
~
~
~
TJ: -55°C
Vas 0 VGS
10 = 1.0 mA
9
'"
20
FIGURE 6 - TRANSFER CHARACTERISTICS
0
1.1
16
12
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
1.2
;;0
'"~
8.0
4.0
FIGURE 5 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE (NORMALIZED)
""
Volts
VGS : 4.0 Volts
VDS, ORAIN-TO-SOURCE VOLTAGE (VOLTS)
~
:
1/
a
:oi
V~S 5.~
~'p-
Q
2.0
/.r
~
,..
.£-
TJ: 25°C
>-
Is
4. a
a
§
2 ::::;:..
A ~
~
~
......-: ~:6.~VOlts
VGS: 10 Volts
VGS - 7.0 Volts
-
~
f-"""
TJ: 20°C
I 0 a
VGS
1= 1.0 MHz
.......
Ciss
1200
z
~
U
~
800
5
400
= 10 V
8,0
~C
\
10
10. DRAIN CURRENT (AMPS)
,\
"- .......
Coss
\.
Crss
10
20
30
Vas, ORAIN-TO-SOURCE VOLTAGE (VOLTS)
MOTOROLA TMOS POWER MOSFET DATA
C-139
~
40
MTM/MTH6N55, 60
FIGURE 9 - MAXIMUM RATED FORWARD BIASED
SAFE OPERATING AREA
FIGURE 10 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
40
10 J.'S
30
!e
:;
100,1"
.......
0
:$
t-
I
l.ri~
t-
'"
=>
'"
u
z
VGS = 20 V
SINGLE PULSE
TC = 25·C
.9
O. 1
rmCK.jGEILIMIIT
10
1.0
25
=>
u
20
...
TJ .. 150·C
z
........de
'OS(onl LIMIT
THERMAL LIMIT
1. 0
~
0
30
z
~
rr:
10 nit'
~
35
~
.9
MTM/MTH6N55
MTM/MTH6N60
100
15
MTM/MTH6N55 10
5.0
F=
600
200
400
600
VOS, ORAIN·TO·SOURCE VOLTAGE (VOLTSI
VOS, ORAIN·TO·SOURCE VOLTAGE (VOLTSI
FORWARD BIASED SAFE OPERATING AREA
Po
The dc data of Figure 9 is based on a case temperature
(TC) of 25°C. and a maximum junction temperature
(TJmax) of 150°. The actual junction temperature depends on the power dissipated in the device and its case
temperature. For various pulse widths, duty cycles, and
case temperatures, the peak allowable drain current
(10M) may be calculated with the aid of the following
equation:
ROJC
r(t)
800
=' rated power dissipation at TC = 25°C
= rated steady state thermal resistance
= normalized thermal response from Figure 11
SWITCHING SAFE OPERATING AREA
The switching safe opprating area (SOA) of Figure 10,
is the boundary that the load line may traverse without
incurring damage to the MOSFET. The fundamentallimits are the peak current, 10M and the breakdown voltage,
V(BR)OSS' The switching SOA shown in Figure 9 is applicable for both turn-on and turn-off of the devices for
switching times less than one microsecond.
The power averaged over a complete switching cycle
must be less than:
= IO(250C)[TJlmaXI - TC]
Po . RIiJC . r(t)
where
IO(25°C)
I-
MTM/MTH6N60
= the
dc drain current at TC = 25°C from
Figure 9
TJ(max) = rated maximum junction temperature
TC
= device case temperature
TJlmaxl - TC
ROJC
THERMAL RESPONSE
FIGURE 11 - MTM6N55/MTM6N60/MTH6N55/MTH6N60
1.0
0.7
'-'
z
i
0.3
~
0- 0.2
<~
:;!::!
fficr
~
0
0.5
if
0.5
0.2
f-- 0.1
~
0,1
~ li 0.07
~ :- 0.05
z
!
0.03
~
0.02
--
-~
.....t1
0.01
0.01
0.02
SINGLE
0.1
o curves apply for power
Pulse train shown
Read .time at t1
TJlpkl- Te = Plpkl R8JCIII
OUTY CYCLE. 0 = 11/12
ru lf~
0.05
R8JcIII - rill R8JC
R8JC = 0.83 C/W Max
~~~
......
~-
Plpkl
tJUl
1==005
f-- 0.02
I?""
0.2
0.5
1.0
2.0
5.0
I. TlMElmsl
10
20
MOTOROLA TMOS POWER MOSFET DATA
C-140
50
100
200
500
Ik
MTM/MTH6N55, 60
TMOS POWER FET CONSIDERATIONS
build-up on the input capacitor due to leakage currents
or pickup.
Switching Sileeci - The switching speeds of these devices are dependent on the driving impedance. Extremely fast switching speeds can be attained by driving
the gate from a voltage source.
Gate Protection - These devices do not have lin internal monolithic zener diode from gate to source. The
addition of an internal zener diode may result in detrimental effects on the reliability of a power MOSFET. If
gate protection is required, an external zener diode is
recommended.
Transfer Characteristics - The transfer characteristics
are linear at drain currents of 500 mA. (See Figure 6.)
Linear amplifiers with high frequency response can be
designed using this product.
Gate Voltage Rating - Never exceed the gate voltage
rating of ±20 V. Exceeding the rated VGS can result in
permanent damage to the oxide layer in the gate region.
Handling and Packaging - MOS ICs are susceptible to
damage from electrostatic charge. Experience has shown
that these devices are more rugged than MOS ICs. This
is primarily due to the comparatively larger capacitances associated with power devices, however, reasonable precautions in handling and packaging MOS
devices should be observed.
Gate Termination - The gate of these devices are essentially capacitors. Circuits that leave the gate opencircuited or floating should be avoided. These conditions can result in turn-on of the devices due to voltage
MOTOROLA TMOS POWER MOSFET DATA
C-141
MTM7N18, MTP7N18
MTM7N20, MTP7N20
MTM8N12, MTP8N12
MTM8N15, MTP8N15
®
MOTOROLA
D('signer's Data Shed
7,0 and 8.0 AMPERE
N-CHANNEL TMOS
POWER FET
roS(on) = 0.7 OHM
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
180 lind 200 VOLTS
=
roS(on)' 0.5 OHM
120 and 150 VOLTS
These TMOS Power FETs are designed for high voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds Specified at 100°C
MTM7N1S
MTM7N20
MTMSN12
MTMSN1S
Switching Times
• Designer's Data - lOSS, VDS(on), SOA and VGS(th)
Specified at Elevated Temperature
• Rugged -
~ ~'Tl5~_joo
~~FJf1
SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With
Inductive Loads
lr
H
U
PINl GATE
2. SOURCE
CASE DRAIN
S
CASE 1-04
TO-204AA
(TO-3 TYPE)
SN12
MTMor MTP
SN1S 7N1S
7N20
Unit
VOSS
120
150
180
200
Vdc
Drain-Gate Voltage
(RGS = 1.0 MOl
VOGR
120
150
180
200
Vdc
±20
VGS
Vdc
Adc
Drain Current
Continuous
10
10M
Pulsed
Gate Current - Pulsed
Total Power
IGM
8.0
20
Operating and Storage
Temperature Range
1.5
Adc
Watts
75
0.6
W/OC
-65 to 150
°c
ROJC
1.67
°C/W
TL
275
°c
TJ, Tstg
MTP7N18
MTP7N20
MTPSN12
MTP8N15
7.0
18
Po
Dissipation @ TC = 25°C
Derate abo,", 25°C
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Maximum Lead Temp. for
Soldering Purposes, 1IS"
from case for 5 seconds
-
FI
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
Designer'. Data for "Worst C..." Conditions
CASE 221A-02
TO-220AB
The Designer's Data Sheet permits the design of most circuits entirely from the
information presented. Limitdata - representing device characteristics boundaries- are
given to facilitate "worst case" design.
MOTOROLA TMOS POWER MOSFET DATA
C-142
S
MILLIMETERS
INCHES
.AX
MI. .AX
DI •
1.550
A
39.31
0.830
B
21.0
0.250
C • 5
0.043
0.97
1.09
B
D
E 1.40
.78 0.055 M70
l.t818SC
f
30.15BSC
0
10.928SC
5.46 BSC ,
0.215B8&
N
0.885B8&
16.89B8&
K 11,18 12.19 0.440 0.480
3.81
.19
15• 0.16
28.87
1.
3.05 0100 0.120
U 2.54
419 0.150 0.1
V 31
-
GO--~
Drain-Source Voltage
Gate-Source Voltage
.,.
STYLE 3
MAXIMUM RATINGS
Symbol
..,
G
TMDS
Rating
LrB+tc
-
.
.. '"
•..
•
••
-
MTM/MTP7N18, 20/8N12, 15
I
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
I
Charactaristic
Symbol
Min
Max
120
150
180
200
-
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS = 0, 10 = 5.0 rnA)
Vdc
V{BR)OSS
MTMBNl21MTPBN12
MTMBN15/MTPBN15
MTM7N1B/MTP7N18
MTM7N20/MTP7N20
Zero Gate Voltage Drain Current
(VOS = 0.B5 Rated VOSS, VGS = 0)
(TJ = 100°C)
lOSS
Gate-Body Leakage Current
(VGS = 20 Vde, VOS = 0)
IGSS
-
mAdc
-
-
0.25
2.5
-
500
2.0
1.5
4.5
4.0
-
0.5
-
0.7
-
-
4.5
3.2
5.9
5.0
2.0
-
1.5
-
nAde
ON CHARACTERISTICS'
Gate Threshold Voltage
(lo = 1.0 mA, VOS = VGS)
(TJ = 100°C)
Vde
VGS{th)
MTMBN12/MTMBN15
MTPBNl21MTPBN15
MTM7N1B/MTM7N20
MTP7N lB/MTP7N20
Static Drain-Source On-Resistance
IVGS = 10 Vde, 10 = 4.0 Ade)
(VGS = 10 Vde, 10 = 3.5 Ade)
Drain-Source On-Voltage (VGS - 10 V)
(lo = B.O Ade)
(lo = 4.0 Ade, TJ = 100°C)
(lo = 7.0 Ade)
(l0= 3.5 Adc, TJ= 100°C)
Forward Transconductance
rOSlon)
VOS{on)
MTMBN12/MTM8N15
MTPBNl21MTP8N15
MTM7N1B, MTM7N20
MTP7N lB/MTP7N20
MTMBN 12/MTMBN 15
MTPBN12/MTPBN15
MTM7N1B/MTM7N20
MTP7N1B/MTP7N20
(VOS = 15 V, 10 = 4.0 A)
(VOS= 15V, 10= 3.5 A)
9fs
Ohms
Vdc
mhos
DYNAMIC CHARACTERISTICS
Ciss
-
700
pF
Output Capaeita nee
IVos = 25 V, VGS = 0, f = 1.0 MHz)
Coss
-
300
pF
Reverse Transfer Capacitance
(VOS = 25 V, VGS = 0, f = 1.0 MHz)
Crss
-
BO
pF
td{on)
-
50
ns
150
·100
ns
50
ns
Input Capacitance
IVOS = 25 V, VGS = 0, f = 1.0 MHz)
SWITCHING CHARACTERISTICS' (Tj = 100°C)
Turn-On Delay Time
(VOS = 25 V, 10 = 0.5 Rated 10,
Rise Time
tr
Rgen = 50 ohms)
Turn-Off Delay Time
td{off)
tf
See Fig ures 1 and 2
Fall Time
ns
SOURCE DRAIN DIODE CHARACTERISTICS'
Characteristic
I
Forward On-Voltage
Forward Turn-On Time
Reverse Recovery Time
"'Pulse Test: Pulse Width
FIGURE 1 -
~300
I
Svmbol
Typ
Unit
{IS = Rated 10,
VSO
1.7
Vdc
VGS=O,
ton
BO
ns
Irr
700
ns
I
jJ.s, Duty Cycle ~2%.
SWITCHING TEST CIRCUIT
Output, Vout
Inverted
MOTOROLA TMOS POWER MOSFET DATA
C-143
MTM/MTP7N18, 20/8N12, 15
TYPICAL CHARACTERISTICS
ON-REGION CHARACTERISTICS
FIGURE 3 - MTM7N18. MTM7N20
MTP7N18. MTP7N20
0
VGS=20V
•
10 V
0
//
h:. :/""
o TJ = 25°C
.....-
~
0
0
0
~
h
--
F7
12
V
,/
b
FIGURE 4 - MTM8N12. MTM8N15
MTP8N12. MTP8N15
~
,/
~
J
/
~
~
6.0
~ 4.0
//
Q
6.0 V
,A ......
E> 2.0
5.0 V
or
o
10
2.0
4.0
6.0
8.0
Vas. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
~
/ ~
/1#
B
'l.OV
,.
i/
~ 8.0
h
V
'/ V
v
,/
Y
,.....-
/'
-
VGS=IOV
~~
V
V
/
TJ = 25°C
in
8.0 V
,/
VGS~20V
I
10
9.0 V
I
8.0 V
l- e-
I
I
7.0 V
I
~.O V
5.0 V
1.0
2.0
3.0
4.0
5.0
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
6.0
7.0
TRANSFER CHARACTERISTICS
FIGURE 5 - MTM7N18. MTM7N20
MTP7N18. MTP7N20
0
0
FIGURE 6 - MTM8N12. MTM8N15
MTP8N12. MTP8N15
10
I /
TJ = -55°C_
'-1 /
25°C- f-/,
VOS=IOV
~
'"
/1/
0
~
I-
~
a
/I
0
100°C 0
......-::
b.?
I /
/
-! V V
25°CTi /
'/ V
VDS= 10V
I'
,/1
/. /
TJ = -55°C
8.0
6.0
'"~
4.0
E>
2.0
I/- rIOO°C
///
V
Q
,/,/
2.0
4.0
6.0
8.0
VGS. GATE TO SOURCE VOLTAGE (VOLTS)
A
./~
-:::: ~
o
o
10
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
vGs. GATE·TO·SOURCE VOLTAGE (VOLTS)
ON-RESISTANCE versus DRAIN CURRENT
FIGURE 7 - MTM7N18. MTM7N20
MTP7N18. MTP7N20
FIGURE 8 - MTM8N12. MTM8N15
MTP8N12. MTP8N15
.0
VGS=IOV
.6
1.0
/
TJ = 100°C
-
./
Q
/f'
~
-55°C
.4
/
0.8
V
~
tQ 0.6
f--
ill
./'
TJ = 100°C
~
.........
--
~ f-
/
VGS=IOV
in
::;;
~ 0.4
:::>
---
25°C
li.l
-
,/
V
-55°C
..- /
8.0
12
~
Z 0.2
.2
~
0
2.0
4.0
6.0
10. DRAIN CURRENT (AMPS)
8.0
10
o
o
4.0
10. DRAIN CURRENT (AMPS)
MOTOROLA TMOS POWER MOSFET DATA
C-144
16
20
MTM/MTP7N18, 20/8N12, 15
TYPICAL CHARACTERISTICS
FIGURE 9 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
§"
~
:0
"'"
1.1
0:
0
~
~
1:l
~
1.0
VOS' VGS
10= 1.0 mA
~
0
>
90
%
~
FIGURE 10 - CAPACITANCE VARIATION
1000
1.2
~
0.90
~
,
~
600
:
!'-..
%
!;< 0.80
400
5
r-.....
w
50
100
75
....... '-.
200
125
Coss
\.
Crss
o
o
150
-
Ciss
........
oS
........
'-...,
25
-25
\\
\
g'"
>-
...
~ 0.70-50
>
I
TJ,25°C
VGS' 0 V
f, 1.0 MHz
800
10
TJ. JUNCTION TEMPERATURE 1°C)
40
30
20
50
VOS. DRAIN·TO·SOURCE VOLTAGE IVOLTSI
THERMAL RESPONSE
FIGURE 11 - MTM7N18. MTM7N20. MTM8N12. MTM8N15
1.0
0.7
D, 0.5
-
0.5
I
....I
0= 0.2
0 1 0.3
"'W
~ ~
w'"
"'''
0,
0.2
D= 0.05
:: ~ 0.1
ZZ
~
- 0.07
i~005
c-- -
"'''
....,.
"::~ 002
"....
~~ 0.03 !:;;;o-
._-
aI
..l-
~
BLIL
~--J
D 0.01
SINGLE PULSE
DUTY CYCLE. D tdt2
-I
0.01
0,0)
0.02 0.03
0.1
0.05
a2
OJ
0.5
1.0
20
30
R(!Jcl'l = rl'l R(!JC
1=
~
~
r-
~
A(JJC':::: 1.67°C/W Max
o curves apply for power
Pulse train shown
r-t
Read time at 11
TJlpkl- TC = Plpkl ROJCI'1
I I I I IIII
I I I
II II
10
5.0
I 11111
20
30
50
lOa
I
I
200
300
500
1000
'.TIME Im,l
FIGURE 12 - MTP7N18. MTP7N20. MTP8N12. MTP8N15
~
~
~
o
O. 7
D " 0.5
05
~
0, J
~
O. 2
0.2
,.....
~
0.1
O. 1
'" 0.0 7 - 0.05
0.05
- 0.02
;:: 0.0J
~
i
~ 0.0 2-'"
in
"~
w::::
n
0.01 /
D.O'
002
-
;..
~
~I"""
in
--
Plpkl
RIIJClll = rl'l RIIJC
RIIJC 1.67°C/W Max
o curves applv for power
Pulse train shown
r~
~~I
'2-
....-
Read time at '1
TJlpkl - TC Plpkl R/lJClti
=
OUTY CYCLE. D' •1/'2
SlnEriLfi
005
O.
02
05
2
i. TIME
.0
20
(ms)
MOTOROLA TMOS POWER MOSFET DATA
C-14S
,50
'00
200
500
• k
MTMlMTP7N1S, 20/SN12, 15
SAFE OPERATING AREA INFORMATION
MAXIMUM RATED FORWARD BIASED SAFE OPERATING AREA
FIGURE 14 - MTM8N12. MTM8N16
MTP8N12. MTp8N16
FIGURE 13 - MTM7N18. MTM7N20
MTP7N18. MTP7N20
r-- r-
-1-
01:= I -
~ I:::""
18
•
~[110"sec
I I I 10 "s
20
10 "sec
1.0 ms
-
~ 10
~ 7.0
10 ms
V
MTM/MTP7N2o.
10
1.0
~
z
J'\..
MTM/MTP7N18
O. 1
I
de
rOS(on) Um"---Packa,. Um"--°FThermalLim"
~
VGS~20V
Singl. Pul••'
TC = 25°C
I-
- -
rOS(on) limit
Packag. limit
---Thermal limit
1,0
O. 3
200
1.0 ms
I- - - - - -
~
....
100
I- -
F VGS = 20 V. Singl. Pul••
~Tr 2150~
I I I II
2.0
VOs. ORAIN·TO.sOURCE VOLTAGE (VOLTS)
~O ,,,sl- "-
- --.......
f- I--
"f-
...... r-!,0 ms
de
"-
MTM/MTP8N15
MTM/MTP8N12
10
100
200
Vas. ORAIN·TO·SOURCE VOLTAGE (VOLTS)
FORWARD BIASED SAFE OPERATIN(3 AREA
Where
lo(25 0C) =thedcdraincurrentatTc=25°CfromFigure 13
The de data of Figures 13 and.14 is based on a case temperature
(TC) of 25°C and a maximum junction temperature (TJmax) of
150°, The actual junction temperature depends on the power
dissipated in the device and its case temperature. For various
pulse widths. duty cycles. and case temperatures. the peak allowable drain current (10M) may be calculated with the aid of the
following equation:
,10M
of! 4
TJ(max) ;;: rated maximum junction temperature
= device case temperature
Te
Po
ReJC
r(t)
= rBted power diSSipation at TC :;: 25°C
= rated steady state thermal resistance
;; normalized thermal response from Figures 11
and 12
= lo(250Q[TJ(max) - TC ]
ReJC : r(t)
l!'o .
FIGURE 15 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
0
6
SWITCHING SAFE OPERATING AREA
",TM/MTP8NI2
The switching .afe operating area (SOA) of Figure 15. is the
boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the peak
curren't. 10M and the breakdown Voltage. V(BR)OSS. The
switching SOA shown in Figure 15 is applicable for both turn-on
and turn-off of the devices for switching ,times less than one
microsec.;:md.
The power averaged over a complete switching cycle must be
less than:
i-
MTM/MTP8N15
2
MTM/MTP7N18 - t
MTM/MTP7N20- _
a
TJ";150oC
TJ(max) - TC
0
ReJC
0
50
100
150
200
250
VOS. ORAIN-TO.sOURCE vilLTAGE (VOIJS)
MOTOROLA TMOS POWER MOSFET DATA
C·146
®
MTM7N45
MTM7N50
MTM8N35
MTM8N40
MOTOROLA
.
MTH7N45
MTH7N50
MTH8N35
MTH8N40
Designer's Data Sheet
7,0 and 8.0 AMPERE
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
N-CHANNEL TMOS
POWER FETs
These TMOS Power FETs are designed for high voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
'OS(on) = O,B OHM
460 and 500 VOLTS
rOSlon) = 0.56 OHM
350 and 400 VOLTS
• Silicon Gate for Fast Switching Speeds Specified at 100°C
Switching Times
• Designer's Data -lOSS, VDS(on), VGS(th) and SOA
Specified at Elevated Temperature
• Rugged -
MTM7N45
MTM7N50
MTM8N35
MTM8N40
SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With
Inductive Loads
1r
Go--~
TMOS
STYLE 3
PIN t. GATE
2. SOURCE
CASE DRAIN
S
MAXIMUM RATINGS
Rating
Symbol
MTMorMTH
BN40
7N45
BN35
7N50
Unit
Drain-Source Voltage
vOSS
350
400
450
500
Vdc
Drain-Gate Voltage
(RGS = 1.0 MOl
VOGR
350
400
450
500
Vdc
Gate-Source Voltage
VGS
10
10M
Pulsed
Gate Current -
±20
Vdc
Adc
Drain Current
Continuous
Pulsed
Total Power
8.0
48
7.0
40
1.5
Adc
150
1.2
W/OC
-65 to 150
°c
R6JC
0.83
°C/W
TL
275
°c
IGM
CASE '-05
TO-204AA
(TO-3TYPE)
DIM
A
•
C
•
E
F
G
H
J
K
•
MTH7N45
MTH7N50
MTHBN35
MTH8N40
Po
Dissipation @ TC = 25°C
Derate above 25°C
Operating and Storage
TJ, Tstg
Watts
Temperature Range
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Maximum L,ead Temp. for
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
Soldering Purposes, 1/8"
from case for 5 seconds
Designer's Date for "Worst Case" Conditions
CASE 340-01
TO-21BAC
The Designer's Data Sheet permits the design of most circuits entirely from the
information presented. Limit data - representing device characteristics boundaries - are
given to facilitate "worst case" design.
MOTOROLA TMOS POWER MOSFET DATA
C-147
MfLLlMETERS
.'M MI. MAX
A 20.32 21.08
15.49 15.90
C 4.19
I.,
I.B5
INCHES
MI. .'X
0.800 0.830
0.610 0.626
0.165 0.200
,.040 0.065
.. ....
,.
....
•
,
• ".
,.53
5.72 .'05
3.20 ,....
E
G
H
J
X
l
••
1.65
S>I
/AI
0.38
12.10
15.88
12.19
4.04
15.49
IS.51
12.70
4.22
0.015
0.500
0.225
1).126
0.025
0.610
0.625
0.480
0.159
0.500
0.168
MTM/MTH7N45, 50/8N35, 40
.. ELECTRic'ALCHARACTERISTICS (Tc = 25°C unless otherwise noted)
,I
I
Characteristic
Symbol
Min
Max
Unit
OFF CHARACTERISTICS
Drain-Source Bre"akdown Voltage
(VGS = 0, TO" 5,0 rnA)
•
Vdc
V(BR)OSS
MTM8N35/MTH8N35
MTM8N40/MTH8N40
MTM7N45/MTH7N45
MTM7N50/MTH7N50
350
400
450
,500
Zero Gate Voltage.'Drain Current
(VOS = 0,85 Rated VOSS, VGS = 0)
TC= 100°C
lOSS
Gate-Body Leakage Current
(VGS = 20 Vde, VOS = 0)
IGSS
-
-
~
mAde
-
0,25
2,5
2.0
1.5
4.5
4.0
-
0.55
-
0.80
-
5.3
-
4.4
-
7.0
-
5.6
3.0
-
2.0
-
500
nAdc
ON CHARACTERISTICS'
Gale Threshold Vollage
(VOS = VGS, 10 = 1.0 mAl
TJ= 100°C
Static Drain-Source On-Resistance
(VGS = 10 Vde, 10 = 4.0 Ade)
rOS(on)
MTM8N35/MTH8N35
MTM8N40/MTH8N40
MTM7N45/MTH7N45
MTM7N50/MTH7N50
(VGS = 10 Vdc, 10 = 3.5 Adc)
Orain-Source On-Vollage (VGS = 10 V)
(10 = 8,0 Adc)
(10 = 4.0 Ade, TJ = 100°C)
(10 = 7.0 Ade)
(10 = 3.5 Ade, T C = 100°C)
Forward Transconductance
(VOS= 10V, 10=4,OA)
(VOS = 10 V, '0 = 3,5 A)
Vde
VGS(th)
Ohm
Vdc
VOS(on)
M~M8N35/MTH8N35
MTM8N40/MTH8N40
MTM8N35/MTH8N35
MTM8N40/MTH8N40
MTM7N45/MTH7N45
MTM7N50/MTH7N50
MTM7N45/MTH7N45
MTM7N50/MTH7N50
mhos
9fs
MTM8N35/MTH8N35
MTM8N40/MTH8N40
MTM7N45/MTH7N45
MTM7N50/MTH7N50
DYNAMIC CHARACTERISTICS
Input Capacitance
Ciss
(VOS = 25 V, VGS = 0,
Output Capacitance
Coss
f= 1.0 MHz)
Reverse Transfer Capacitance
erss
-
1800
pF
350
150
SWITCHING CHARACTERISTICS' (TJ = 100°C)
Turn-On Delay Time
Rise Time
Turn-Off Oelay Time
(VOO = 25 V, 10 = 0.5 Rated 10
Id(on)
I,
Rgen = 50 ohms)
See Figures 10 and 11
Fall Time
Id(off)
tf
-
60
ns
150
200
120
SOURCE DRAIN DIODE CHARACTERISTICS'
Characteristic
Symbol,
Typ
Unit
Forward On-Voltage
IS = Rated 10
VSO
1.1 (1)
Vdc
Forward Turn-On Time
VGS=O
ton
175
ns
Irr
600
ns
Reverse Recovery Time
·Pulse Test: Pulse Width ~300 ,us, Duty Cycle ~2%.
11) Add 0.5 V to VSD for MTM/MTH8N35 and MTM/MTH8N40,
MOTOROLA TMOS POWER MOSFET DATA
C-148
MTM/MTH7N45. 50/8N35. 40
TYPICAL CHARACTERISTICS
MTM8N35.MTM8N40.MTH8N35.MTH8N40
MTM7N45.MTM7N50.MTH7N45.MTH7N50
fiGURE 1 -
ON·REGION CHARACTERISTICS
10
VGS
TJ
10V
O
~
25°C
0
B.O
~~
"/
I
...z
i!:!
a
~
4.0 V
4.0
B.O
12
16
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
TJ
VDS
20
~
2.0
6. 0
B
~
4. 0
0
4.0
6.0
B.O
VGS. GATE TO SOURCE VOLTAGE (VOLTS)
10
in 2.0
I
J
:;;
~
~
1.6
TJ = 100°C
In
~
...I--"""
1.2
~
I
~ 0.8
J5 0 C
=>
:$z
~
_55°C
0.4
e
I
~
./
/
V
o
0.8
~
~
0.6
w
'-'
'"=>
W
....,%,
4.0
2.0
6.0
I-- r--
~
z
:;;:
~
V
TJ = 100°C
B.O
10
V
12
V
-V
r--
25°C
-
~55OC
~ 0.4
.....-
./
../
V
0.2
Z
VGS=10V
Q
I
4.0
~
'"
VGS - 10 V
~
Q
~ a
Ii
/11
~ 1.0
./
-
I
II
FIGURE 6 - ON-RESISTANCE versus
DRAIN CURRENT
V
....... V
'I
VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)
FIGURE 5 - ON·RESISTANCE versus
ORAIN CURRENT
e
H
~ 25°C
'I/~ ~ 100°C
I,
.s? 2. 0
'II
2.0
,
Q
~/
o
Vos - 20 V
5-
J
A
lit
~ 40
TJ - -55°C-
I
:;; B. 0
:;;
g§
20
mANSFER CHARACTERISTICS
~
J'
I
o
0
/I.
~ 60
'"E
FIGURE 4 2
0
~
8.0
12
16
Vos. ORAIN·TO·SOURCE VOLTAGE (VOlTS)
f 25°C
'I ~ TJ ~ 100 e
'I
in
4.0 V
4.0
~ -55°C
20 V
0
5.0 V
l
IE
FIGURE 3 - TRANSFER CHARACTERISTICS
BO
6.0 V
~v
z
'"94. 0
I
7.0 V
~
,
8.0
nGS=110V
./
// /""
5-
I
10
§
~1 2
5.0 V
I/"
/./
TJ = 25°C
in
I
I
/. ",.'f/
ON·REGION CHARACTERISTICS
VGS=20V
7.0 V
0
6.0 V
~V
/
VGS
I
V
~V
,
FIGURE 2 6
B.O
12
10. DRAIN CURRENT (AMPS)
16
20
~ 0
o
4.0
8.0
12
10. DRAIN CURRENT (AMPS)
MOTOROLA TMOS POWER MOSFET DATA
C-149
16
20
MTMlMTH7N45, 50/8N35, 40
TYPICAL CHARACTERISTrCS
FIGURE 7 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
•
~
FIGURE 8 - CAPACITANCE VARIATION
2000
12
~
'"::E
'"'
'"
~
""" """-
II
~
~
10
'"C
l2
0.90
VOS " VGS
""-.
~
""-.
'">
"'-
-SO
25
-25
So
7S
\
5
"
~
>
100
400
.......
125
"-
I\,
"""
ISO
0.02
0.05
0.1
Ciss
0.2
0.5
1.0
-
Coss
Crss -
2.0
5.0
10
20
50
100
200
t. TIME (rnsl
RESISTIVE SWITCHING
FIGURE
to -
r40
10
20
30
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTSI
TJ. JUNCTION TEMPERATURE 1°C)
0.01
f = 1.0 MHz
"-
1200
5:. 800
'-....
080
~ 0.70
TJI=250~t=
VGS = 0
'"
'%"'
....
~
\
1600
10' I 0 rnA
SWITCHING TEST CIRCUIT
FIGURE 11 - SWITCHING WAVEFORMS
'd(onl
Output. Vout
Inverted
MOTOROLA TMOS POWER MOSFET DATA
C-1S0
500
1.0 k
MTM/MTH7N45, 50/8N35, 40
OPERATING AREA INFORMATION
FIGURE 12 -
MAXIMUM RATED FORWARD BIAS
SAFE OPERATING AREA
FORWARD BIASED SAFE OPERATING AREA
100
I--
-
>-
"'"
1. . . . . . . .
The de data of Figures 12 and 13 is based on a case temperature (Te) of 25°C and a maximum junction temperature (TJmax)
of 1500C. The a~tual junction temperature depends on the power
dissipate~ in "the device and its case temperature. For various
pulse widths, duty cycles, and case temperatures, the peak
allowable drain current (10M) may be calculated with the aid of
the following equation:
10 !,s
, ...100 !,s
1, Olms
10 ms
-17
;Z
==
0,
rDSlonl limit -
Thermal limit
Package Limit
-
- VGS - 20 V
_Single Pulse
1- TC =25°C
-
de
I........
10M
TJmax - TC
PO' RBJC' rltl
Where
10 (25"C)=dc drain current at TC=25"C from Figures 12 or 13
MTM/MTH7N45 MTM/MTH7N50
TJmax
TC
Po
R8JC
r(t)
I
10
100
VDS. DRAIN·TD·SOURCE VOLTAGE IVOLTS)
1,0
= IOI25°CI
500
= rated maximum junction temperature
= device case temperature
= rated power dissipation at TC=25"C
= rated steady state thermal resistance
= normalized thermal response from Figure 9
SWITCHING SAFE OPERATING AREA
FIGURE 13 -
MAXIMUM RATED FORWARD BIAS
SAFE OPERATING AREA
The switching safe operating area ISOA) of Figure 14. is the
bou ndary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the peak
current. 10M and the breakdown voltage. V(BR)OSS. The switching S·OA shown in Figure 14 is applicable for both turn-on and
turn-off of the devices for switching times less. than one microsecond.
The power averaged over a complete svvitching cycle must be
less than:
50
10,u.s
~
:E
10
100 !,s
- --
I-
1.0 ms
........
10 ms
~
I-
!
z
:;;:
7
'"'"
p
f:: VGS - 20 V
I- TC = 25°C
1.0
-
TJmax - TC
........
MTM/MTHBN35
MTM/MTHBN40
t-- Sin.gle Pulse
0.1
de
'DSlonl Limit-
~ - Thermal limit
1.0 E
'= Package Limit
ABJC
-
I
10
100
VDS. DRAIN·TO-SOURCE VOLTAGE (VOLTSI
400
FIGURE 14 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
50
40
MTM/MTHBN35 MTM/MTHBN40
--
MTM/MTH7N45
MTM/MTH7N50
TJ':; 150°C
o
o
100
200
300
400
VOS. DRAIN·TD·SOURCE VOLTAGE (VOLTSI
500
MOTOROLA TMOSPOWER MOSFET DATA
MTM8N08, MTP8N08
MTM8NIO, MTP8NIO
MTMIONOS,MTPIONOS
MTMION06,MTPION06
®
MOTOROLA
8.0 and 10 AMPERE
I)('s i gn l'J"' s I) a t a S h(,(,t
N-CHANNEL TMOS
POWER FET
roslon) = O.S OHM
80 and 100 VOLTS
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
=
roSlon)
0.28 OHM
50 and 60 VOLTS
These TMOS Power FETs are designed for low voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds Specified at 100'C
MTM8N08
MTM8Nl0
MTM10N05
• Designer's Data -lOSS, VDS(on), SOA and VGS(th)
Specified at Elevated Temperature
• Rugged - SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
Loads
.
lr
STYLE 3
PIN 1.
GO----}"J
CASE 1-05
To-204AA
ITO-3TYPEI
S
MAXIMUM RATINGS
Symbol
MTMorMTP
10N05 10N06 8N08
8Nl0
Unit
Drain-Source Voltage
Voss
50
60
80
100
Vdc
Drain-Gate Voltage
IRGS = 1.0 MOl
VDGR
50
60
80
100
Vdc
Gate-Source Voltage
VGS
Drain Current
Continuous
Pulsed
10
10M
Gate Current - Pulsed
IGM
Vdc
±20
Adc
Total Power
Dissipation @ TC ; 25'C
Derate above 25'C
Operating and Storage
Temperature Range
GATE
2. SOURCE
CASE DRAIN
TMOS
Rating
10
28
Adc
1.5
Walts
75
0.6
W/DC
-65 to 150
'c
ROJC
1.67
'C/W
TL
275
DC
TJ, Tstg
MTP8N08
MTP8Nl0
MTP10NOS
MTP10N06
8.0
20
Po
THERMAL CHARACTERISTICS
Thermal Resista nee
Junction to Case
Maximum Lead Temp. for
Soldering Purposes, 1 IS"
from case for 5 seconds
5
ST"t'lE 5:
Designer's Date for "Worst Case" Conditions
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
CASE 221A-02
TO-220AB
The Designer'S Data Sheet permits the deSign of most circuits entirely from the
information presented. Limi~data - representing device characteristics boundaries- are
given to facilita.te "worst case" deSign.
MOTOROLA TMOS POWER MOSFET DATA
C-152
If
!"-
A
--~
B--j
L~
ij ot.~~"
Switching Times
-1
. -l
c
MTM/MTP8N08. 10/10N05. 06
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
I
Characteristic
Symbol
Min
Max
50
60
BO
100
-
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS = 0, 10 = 5.0 mAl
V(BR)OSS
MTM 1ON05/MTP 10N05
MTM 1ON06/MTP 1ON06
MTMBNOB/MTPBNOB
MTMBN10/MTPBN10
Zero Gate Voltage Drain Current
(VOS = 0.B5 Rated VOSS, VGS = 0)
(TJ = 100°C)
lOSS
Gate-Body Leakage Current
(VGS = 20 Vdc, VOS = 0)
IGSS
Vdc
-
mAdc
-
-
0.25
2.5
-
500
2.0
1.5
4.5
4.0
nAdc
ON CHARACTERISTICS'
Gate Threshold Voltage
(10 = 1.0 mA. VOS = VGS)
(TJ = 100°C)
Vdc
VGS(th)
Static Drain-Source On-Resistance
(VGS = 10 Vde, 10 = 5.0 Adc)
(VGS = 10 Vdc, 10 = 4.0 Adc)
rOS(on)
MTM10N05/MTM10N06
MTPI ON05/MTP 1ON06
MTMBNOB/MTMBN 10
MTPBNOS/MTPBN 10
Drain-Source On-Voltage (VGS - 10 V)
MTM 1ON05/MTM 10N06
(10 = 10 Adc)
MTP10N05/MTP10N06
MTMBNOB, MTMBN10
(10 = 5.0 Adc, TJ = 100°C)
MTPBNOS/MTPBN 10
MTM10N05, MTM10N06
(10 = S.O Adc)
MTPI ON05/MTP 1ON06
(10 = 4.0 Adc, TJ = 100°C)
MTMBNOB/MTMBN 10
MTPBN08/MTPBN 10
VOS(on)
Forward Transconductance
Ohms
-
0.2B
-
0.50
-
3.4
Vdc
-
2.B
-
4.B
-
4.0
2.5
-
1.5
-
mhos
9fs
MTM10N05/MTM10N06
MTP10N05/MTP10N06
MTMBNOS/MTMBN 10
MTP8NOB/MTPBN 10
(VOS = 15 V, 10 = 5.0 A)
(VOS= 15 V, 10 = 4.0 A)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VOS = 25 V, VGS = 0, f = 1.0 MHz) I - - : : = ' - - t - - - - - - + - - = : - - - i
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS' (TJ = 100°C)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
(VOS = 25 V, 10 = 0.5 Rated 10,
td(on)
-
50
Rgen = 50 ohms
See Figures 1 and 2)
tr
-
120
td(off)
tf
-
50
Fall Time
ns
60
SOURCE DRAIN DIODE CHARACTERISTICS'
Characteristic
Forward On-Voltage
Forward Turn-On Time
Reverse Recovery Time
I
I
Symbol
Typ
Unit
(IS = Rated 10,
VSO
1.9
Vdc
VGS =0,
ton
200
ns
trr
300
ns
I
*Pulse Test: Pulse Width ~300 P.s, Duty Cycle :S;;;2%.
FIGURE 1 -
FIGURE 2 - SWITCHING WAVEFORMS
SWITCHING TEST CIRCUIT
td(on)
Output, Vout
Inverted
MOTOROLA TMOS POWER MOSFET DATA
C-1S3
MTMlMTP8N08, 10/10NOS, 06
TYPICAL CHARACTERISTICS
ON-REGION CHARACTERISTICS
FIGURE 4 - MTM10N05, MTM10N06
MTP10N05, MTP10N06
FIGURE 3 - MTMBNOB, MTMBN10
MTPBNOB, MTPBN10
10
•
i
VGS = 20 Vohs.j
V
!....
6.0
::
z
4.0
E
2.0
!13
B.O Volts
,
7.0 Volts
IJ. ~
10 Vohs
~
7.0 V!hS-
Jb
5.0 Volts
o
o
10
-
6.0 Volts
r,
B.O
4.0
6.0
2.0
VDS. DRAIN·TO·SOURCE VOLTAGE IVOLTS)
-
8.0 Vohs
'P
5.0 Volts
~olts-
9.0
h"
I
6.0 Volts
III
o
o
n
TJ = 25°C
//1,
VGS = 12 VOI:S- f.--
/ ..... V
V
TJ = ~5OC !/
/ V
/ I/.
16
Iff..
co
VGS= 20 Votts
9.0VJlts-
1/
/ V
/ V/
// !/
B. 0
20
VGS = 10 Volts
/-
2.0
4.0
6.0
8.0
VDS. DRAIN·TO·SOURCE VOLTAGE IVOLTS)
10
TRANSFER CHARACTERISTICS
FIGURE 6 - MTM10N05, MTM10N06
MTP10N05,MTP10N06
FIGURE 5 - MTMBNOB, MTMBN10
MTPBNOB, MTPBN10
10
VDS = 10 V
TJ = -55°C -
in 8.0
25°C .---,
~
5.
~ 6.0
~
E
12
'-.1 /
in 10
4.0
1
1
,
~ 8.0
o
o
~
hi
~W
~ 8:/'
/
/
./
-I
I
~tJ= 100o C_
i--
1,('
'"
,l,rl
~
o
o
10
~ '-TJ = 25°C
A
4.0
- 2.0
4.0
6.0
8.0
2.0
VGS. GATE TO SOURCE VOLTAGE IVOLTS)
A
/1
IT17
6 .0
z
2.0
/
_TJ=-55°C_
~
~
0
I
1 1 1
1
' - - VDS=10V-
/J /
/y
~
Z
/ /
-I
//
100°C
00
'-'
4
~
2.0
4.0
6.0
B.O
10
VGS. GATE TD SOURCE VOLTAGE IVOLTS)·
12
14
ON·RESISTANCE versus DRAIN CURRENT
FIGURE B - MTM10N05, MTM10N06
MTP10N05,MTP10N06
FIGURE 7 - MTMBNOB, MTMBN10
MTPBNOB, MTPBN10
in 0.5
VGS = 10 V
:2
e'"
~
~
0.4
~
0.3
0.2
o
0.1
~
-
-55
~
o
6
.,..,
t
-r
0
in 0.5
V
1c
[;!
~
1000~
25O~
~
::l
TJ;
----
......
2.0
4.0
6.0
ID. DRAIN CURRENT lAMPS)
8.0
./
/
~ 0.4
~
ill
./
TJ = /OOOC
--'
0.3
:;!
~
co
"I 0.2
co
>-;-
25°C
'"
-55°C
.
~
o
-VG~= 10lv
~
e
10
o. 1
J
0
o
3.0
6.0
9.0
10. DRAIN CURRENT lAMPS)
MOTOROLA TMOS POWER MOSFET DATA
C-154
-
;:..;..;-
---
12
15
MTMlMTP8N08, 10/10N05, 06
TYPICAL CHARACTERISTICS
FIGURE 9 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
C
1.2
~
1.1
'"
;3
1.0
~
c:>
~
w
""'-
"'"
§;
VOS = VGS
10= 1.0 mA
~
"--
0.90
ill
1\
\
;;t
\\
5400
~
"'-
i!:
~ 0.80
........ ~
0.70
25
-25
-50
50
100
75
..... ~
125
r--
200 1\
i',.
~
i
600
<.i
'"
>
~5°C
TJ =
I-VGS = 0
t= 1.0 MHz I - -
800
g
~
9
i!
FIGURE 10 - CAPACITANCE VARIATION
1000
"
o
o
150
'"
TJ. JUNCTION TEMPERATURE (OC)
-
Cis!
c~
'--
I-I--
10
20
30
40
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS)
50
THERMAL RESPONSE
FIGURE 11 - MTM8N08. MTM8N10. MTM10N05. MTM10N06
!!l
1.0
7
i~
!
~
~
0-0.5
3
0=0.2
02
0-0.1
- 0.05
O. 1
~
0.0 7
;: 0.05
ai~ 0.0 3
e:
-
5
0.02
0
io""
P(pkl
r-
.1-'"'
tr--I
SINGLE PULSE
Read time at '1
'2DUTY CYCLE. D = '1/'2
......
:E 0.0 I
1111111
0.01
RHJC(tl = '(tl RHJC
ROJC = 1 67°C/W Max
o curves apply for power
Pulse train shown
fJUl
0.01
0.02 0.03
0.05
0.1
0.2
03
0.5
1.0
2.0
3D
5.0
t. TIME Im,l
TJ(pkl - TC = Plpkl RHJCltl
I I I
10
20
I II III
30
50
100
I I I I I
100
300
500
1000
FIGURE 12 - MTM8N08. MTM8N10. MTM10N05. MTM10N06
~ 1.0
~ OJ
ii
)--
0- 0.5
0.5
D~·
~ 0.3
r;;
0.2
0.2
D 0.1
-0.05 _
~
...
~
0.1
~ 0.07
~ 0.05
0
Plpkl
tr--I
IS
'1DUTY CYCLE. 0 = Ii 112
~ 0.03
f= 0.02
~ 0.01
.....
0.01
i..-'
I
0.02 0.03
RHJC{t) = '(tl ROJC
ROJC = 1.67°C/W Max
o curves apply tor power
Pulse tram shown
Read rime al 11
fJUl
0.01
0.05
0.1
0.1
0.3
0.5
1.0
2.0
3.0
TJ(pkl- TC = P1pkl RHJCIII
I
11111
5.0
10
20
30
t. TIME (m'l
MOTOROLA TMOS POWER MOSFET DATA
C-155
11111
50
100
I I I
200
I
300
500
.1 000
MTM/MTP8N08, 10/10N05, 06
SAFE OPERATING AREA INFORMATION
MAXIMUM RATED FORWARD BIASED SAFE OPERATING AREA
FIGURE 13 - MTM8N08, MTM8N10
MTP8N08, MTM8N10
10
II
r-
f-- f-f--
roo-- ~~~~
1.0 ms
FIGURE 14 - MTM10N05, IIIITM10N06
MTP10N06, MTM10N06
°
10
IOl's
10 ms
'~"
'OS(onl Limit - - -
~
.....
F~ F,'7
f-- J;-'
r--- F-
de
Package limit _ .. -
I..,
':':
1.0 ms
10m
r- Single Pulse
a
=
0
z
MTM/MTP8Nl0
MTM/MTP8N08
E-
TC; 25°C
O. 2 VGS; 20 V. Single Pulse
10
100
1.0
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTSI
rTC = 25°C
f--' I
I
I
'OS(on l Limit
Pac age limit
Thermal limit
I
1.0
1.0
Po
FORWARD BIASED SAFE OPERATING AREA
The de data of Figures 13 and 14 is based on a case
temperature (TC) of 25°C and a maximum junction temperature (TJmax) of 150°. The actual Junction temperature depends on the power dissipated in the device
and its case temperature. Fo.r various pulse widths, duty
cycles, and case temperatures, the peak allowable drain
current (10M) may be calculated with the aid of the following equation:
.
IO(250 C)[TJ(maXI - TC]
Po . RIJJC . r(t)
where
IO(25°C) = the de drain current at TC = 25°C from
Figures 13 and 14.
TJ(max) = rated maximum junction temperature.
device case temperature.
TC
RIJJC
r(t)
--------
5-
!z
~
az
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) of Figure 15
is the boundary that the load line may traverse without
incurring damage to the MOSFET. The fundamental
limits are the peak current, 10M and the breakdown
voltage, V(BR)OSS' The switching SOA shown in Figure
15 is applicable for both turn-on and turn-off of the
devices for switching times less than one microsecond.
The power averaged over a complete switching cycle
must be less than:
TJlmaxl - TC
ROJC
L-
MTM/MTP10NOS
16
TJ ';;150 0 C
:
o
o
JTM/MTP8Nl0
MTM/MTP8N08 -
~ B.O
20
40
60
80
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTSI
100
MOTOROLA TMOS POWER MOSFETDATA
C-156
MTM/MTP10N05
I I I I
MTM/IMTPl10rOlB
rated power dissipation at TC = 25°C.
rated steady state thermal resistance.
normalized thermal response from
Figures 11 or 12.
32
MTM/MTPI ON05
de
10
60
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTSI
FIGURE 15 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
~ 24
::;;
10 I'
_ _ ~I'S
~VGS; 20 V
Thermal limit - -
=> 1.0
10M
-
®
MTM8N18, MTM8N20
MTP8N18,MTP8N20
MOTOROLA
J)esignel"s Data Sheet
8.0 AMPERE
N-CHANNEL TMOS
POWER FET
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
rOSlon) = 0.4 OHM
180 and 200 VOLTS
These TMOS Power FETs are designed for high speed power
switching applications such as switching regulators, converters,
solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds Specified at 100DC
Switching Times
MTMBN18
MTM8N20
• Designer's Data - lOSS, VDS(on), SOA and VGS(th)
Specified at Elevated Temperature
• Rugged -
J~E·.-'frn
fC
SOA is Power Dissipation Limited
T:E
• Source-to-Drain Diode Characterized for Use With
Inductive Loads
S£AnNGPLANl
STYLE3:
PIN 1. GATE
2. SOURCE
CAS~
1r
DRAIN
TMOS
S
CASE 1-04
TO-204AA
MAXIMUM RATINGS
(TO-3 TYPE)
Symbol
MTM8N18
MTP8N18
MTM8N20
MTP8N20
Unit
Drain-Source Voltage
VOSS
180
200
Vdc
Drain-Gate Voltage
(RGS = 1.0 Mil)
VOGR
180
200
Vdc
Rating
Gate-Source Voltage
Vdc
VGS
±20
10
10M
8.0
25
IGM
1.5
Adc
Po
75
Watts
0.6
W/DC
TJ, Tstg
-65 to 150
°C
R9JC
1.67
DC/W
TL
275
°C
MTP8N18
MTP8N20
Adc
Drain Current
Continuous
Pulsed
Gate Current - Pulsed
Total Power
Dissipation @ TC = 25 D C
Derate above 25 D C
Operating and Storage
Temperature Range
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
STYLES:
PIN I. GATE
2. DRAIN
3. SOURce
Maximum Lead Temp. for
Soldering Purposes, 1/8"
from case for 5 seconds
Designer·. Data for "Worst Case" Conditions
4.
CASE 221A-02
TO-220AB
The Designers Data Sheet permits the design of most circuits entirely from the
information presented. limit data - representing device characteristics boundaries - are
given to facilitate "worst case" design.
MOTOROLA TMOS POWER MOSFET DATA
C-1S7
DRAIN
--D
_.
K
.
i
MTMIMTPSN18,20
I
ELECTRICAL CHARACTERISTICS (TC ~ 25°C unless otherwise noted)
I
Characteristic
Min
Symbol
Max
Unit
OFF CHARACTI'RISTICS
Drain-Source Breakdown Voltage
(VGS ~ O. 10 ~ 5.0 mAl
•
Vdc
V(BR)OSS
MTMBN18/MTP8N18
MTMNB1B/MTPBN20
lBO
200
Zero Gate Voltage Drain Current
(VOS ~ 0.B5 BVOSS. VGS ~ 0)
TJ~ 100°C
lOSS
Gate-Body Leakage Current
(VGS ~ 20 Vdc. VOS ~ 0)
IGSS
-
mAdc
-
0.25
2.5
500
nAdc
2.0
1.5
4.5
4.0
Vdc
-
1.6
4.0
3.2
ON CHARACTERISTICS'
Gate Threshold Voltage
(10 ~ 1.0 mA. VOS = VGS)
Drain-Source On-Voltage (VGS = 10 V)
(10 ~ 4.0 Adc)
(10 = B.O Adc)
(10 = 4.0 Adc. TJ = 100°C)
VGS(th)
TJ= 100°C
Vdc
VOSlon)
-
Static Drain-Source On-Resistance
(VGS = 10 Vdc. 10 = 4.0 Adc)
Forward Transconductance
IVoS = 15 V. 10 ~ 4.0 A)
rOS(on)
-
0.4
9f.
3.0
-
Ohms
mhos
SAFE OPERATING AREAS
Forward Biased Safe Operating Area
Switching Safe Operating Area
DYNAMIC CHARACTERISTICS
Input Capacitance
I--0~ut-,:p_u:-tc--:a,.:p-,.a_c:-;ita-,.n--:c;;ce:-:-=_-l (VOS ~ 25 V. VGS ~ O. f ~ 1.0 MHz) f--~~--+-----1~---=:::"'-~I---"'-:----l
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS' (TJ = 100°C)
Turn-On Delay Time
Rise Time
IVoS = 25 V. 10 = 4.0 A.
Turn-Off Delay Time
Rgen ~ 50 ohms)
Fall Time
tdlon)
tr
-
tdloffl
tf
-
40
ns
150
ns
100
ns
100
ns
Symbol
Typ
Unit
VSO
2.0
Vdc
ton
250
ns
t"
325
ns
SOURCE DRAIN DIODE CHARACTERISTICS'
Characteristic
Forward On-Voltage
Forward Turn-On Time
Reverse Recovery Time
I
I
IS = B.OA
VGS~O
I
*Pulse Test: Pulse WIdth ~300 p.s. Duty Cycle 0;;;;2%.
RESISTIVE SWITCHING
FIGURE 1 -
FIGURE 2 -
SWITCHING TEST CIRCUIT
SWITCHING WAVEFORMS
tdlon)
Output. Vout
Inverted
MOTOROLA TMOS POWER MOSFET DATA
C-158
MTM/MTP8N18.20
TYPICAL CHARACTERISTICS
FIGURE 3 - OUTPUT CHARACTERISTICS
16
'tL
~
FIGURE 4 - ON-REGION CHARACTERISTICS
16
I
!-VGS' 20 V
10 if
t - 8.0'V
VGS'20V -
I
TJ.25°C
10V:-Z
/b V
VGS' 7.0 V
I
6.L
6.~V -
I~
,-"
I
5.~V -
V
1/
10
20
30
40
Vos. ORAIN-TO·SOURCE VOLTAGE (VOLTS)
a
50
FIGURE 5 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
o
~
6.0
8.0
4.0
2.0
VOS ORAIN·TO·SOURCE VOLTAGE (VOLTS)
16
VOS·IOV
'":;;;.
~
"'-...
1.1
'"~
~
~
,.'"~
1.0
'3
~
0.90
~
0.80
'"
~
VOS' VGS
'0'1.0mA
"'" "'"
te
TJ' -55°C
12
~5°C
!
!z
B8.0
;;\
~
A
'"~4.0
/II
"""'1'-..
~~
.........
: 0.70
,.
-50
-25
25
50
75
100
125
2.0
4.0
6.0
8.0
VGS, GATE·TO·SOURCE VOLTAGE (VOLTS)
150
TJ, JUNCTION TEMPERATURE 1°C)
FIGURE 7 - ON-RESISTANCE versus
DRAIN CURRENT
10
TJ'IOOoC
-r
1ll
~ 0.4
25°C
:::>
'"
"!
~
~ 0.2
-55°C
'"t
~
TJ' 25°C
VGF 10 V
0.6
0
o
4.0
---
...........
'"
tl
/'
~8.0
'"'"~ 6.0
tl
--- -
8.0
10 ORAIN CURRENT (AMPS)
r-
12
10
FIGURE 8 - ON-VOLTAGE VARIATION
_ 0.8
'"
:E
:x:
ew
'"~
TJ = \OOoc
II!
z
:-.....
----;VIIIfA/ /
,
~
'-.",
""
10
FIGURE 6 - TRANSFER CHARACTERISTICS
1.2
§
I
Irr
I
o
7.0 V
//J v.-
TJ·25°C
5.! V
o
,.y /: ~ ~v;,S'80V
~ /'
I
./"
w
[;i!
:::>
~ 4.0
::;z
8.0A- -
:;;:
~2.0
4.0 A
2.0 A
.;
,.'"
16
'0 = 1.0 A
2.0
4.0
6.0
8.0
VGS GATE·TO:SOURCE VOLTAGE (VOLTS)
MOTOROLA TMOS POWER MOSFET DATA
C-1S9
10
MTM/MTP8N18,20
TYPICAL CHARACTERISTICS
FIGURE 9 - CAPACITANCE VARIATION
1000
~\
TJ = 25°C
800 1\
\"\
\
VGS=
Ci~S
-
:,
I'-.
200
a
f= 1.0 MHz -
r---
Coss
I
\.
Crss
a
a
10
2D
30
40
Vas. DRAIN-TO-SOURCE VOLTAGE IVOLTS)
50
THERMAL RESPONSE
FIGURE 10 - MTM8N18/MTM8N20
1.0
0-0.5
~ 0.5
.... z
~ j:! 0.3
:il~
U
....
0.1
:t :;i
0.2
~
0<
~ ~ 0.1
:;; ....
....
;;;#i'
~i-
0.05
"'"
~
16
I
TJ = 25°C
15 V
...
in 16
VGS = 8.0 Volts
I
,r
12
I)
6.0
4.0
V
....$
...'"z
I
0:
::>
Ih
<1 8.0
6J
So
4.0
5V
o
~
10~
,;'
I
~V
7V
6V
5V
4V
o
50
!
I
VGS = 8.0 Voks
,
o
10
20
30
40
VOs. ORAIN-TO-SOURCE VOLTAGE (VOLTS)
9V
/ ' -t-r
I.~
~
J,~
0:
0
4V
o
h '/'
i5 12
7V
I
ON-REGION CHARACTERISTICS
TJ = 25°C
:;
0
So
9V
V/
:IE
$
....
V//io V
FIGURE 4 20
2.0
4.0
6.0
8.0
10
VOS. ORAIN-TO-SOURCE VOLTAGE (VOLTS)
12
14
FIGURE 5 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
FIGURE 6 - TRANSFER CHARACTERISTICS
in
!:i
~ 3.4
~
VOS=,VGS, _
10= 1.0 rnA
3. 2
~ 3. 0
S!
I
TJ = -55°&
25°&
100°&
$
-...........
....
-.... r-..
to
2. 0
$1.
24
~
:; 20
-""""t--.,
i= 2. 4
~ 22
~
r--
r--......
~ 2. 8
2. 6
28
~
16
0:
-...........
a
z
0
So
8
~
r--
8.0
-25
0
25
50
75
100
TJ. JUNCTION TEMPERATURE (OC)
I
I
150
125
/
-I
f--I J
J
VOS=20V
4.0
-50
I I
~
J
'II
12
<1
0:
-
2.0
II
I!iiI'"
""'4.0
"
"
v-
6.0
8.0
10
12
14
VGS. GATE-TO·SOURCE VOLTAGE (VOLTS)
FIGURE 7 - ON-VOLTAGE versus TEMPERATURE
in
!:i
2000
- ---
w
'"
«
3.0
'"
:>
z
...'"
w
0:
1.0
::>
'"'"Z
-
f.---
..
'".....z
'"
0.3
4.0 A .,.,... r--:-::-::
w
~
1200
~
;j
0.1
I---
400
I
-60
-40
-20
0 20
40
60
80
TJ. JUNCTION TEMPERATURE (OC)
100
o
120
L
I
\\
~
800
<.3
VGS=15V
0
:>
TJ I=250 C I _
VGS = 0 V
f=10MHzI'
~ 1600
8.0A- I---
<1
0:
I
10=20A= ~
'"
~
!:i
FIGURE 8 - CAPACITANCE VARIATION
10
\
o
""
....... t--.,
'\.....
Cosi_
-
Cras
10
20
30
VDS. DRAIN·TD-SOURCE VOLTAGE (VOLTS)
MOTOROLA TMOS POWER MOSFET DATA
0-164
Cisl
40
MTM/MTP8P08, 10
TYPICAL CHARACTERISTICS
FIGURE 9 - ON-RESISTANCE versus
DRAIN CURRENT
FIGURE 10 - ON-VOLTAGE VARIATION
12
0.56
~ _ 0.48
---
f-- VGS = 15 V
,.,'"
::>:;;
5 0.40
~~
~
25°C_
0.16
-55°C
I
O.OS
o
10
~
w
'"
!:l
c
>
4.0
S.O
12
2A 4A
8.0
SA
~4A ~
~ 6.0
"-
c
'"
z~
-
4.0
I\..
~
c
10 = 20 A_
"'- ......... "'-
--
.;, 2.0
~
20
16
\
TJ = 25°C
w
'-'
o
o
I
r--
c(
TJ - I~OOL -
~ ~ 0.32
:5~
t~ 0.24
~~
!:l
'"c
Ie. DRAIN CURRENT (AMPS)
o
2.0
4.0
6.0
S.O
10
VGS. GATE-TO-SOURCE VOLTAGE (VOLTS)
12
14
THERMAL RESPONSE
FIGURE 11 - MTMSPOS/MTMSP10
I. TIME Ims)
FIGURE 12 - MTPSPOS/MTPSP10
z
10
07
0.5
~
0.2
u
~
~C
"w
:;;!>!
w"
"':;;
OJ
,.,~
~'"
0"05
02
-
oi
R6JC(II r(II R6JC
R6JC " 1 67°C/W M3k
1
~ ~ 007 :==.005
~ - 0.05
o curves apply for power
Pulse train shown
Read time at 11
_002
z
g
oOJ
-
0'02
~
TJlpkl - TC
=Plpkl R6JCfli
..-+-1
001
001
002
005
01
02
05
10
20
I.
50
TlMllmsi
10
20
MOTOROLA TMOS POWER MOSFET DATA
C-165
50
100
200
500
lk
MTMlMTPSP08,10
SAFE OPERATING AREA INFORMATION
FIGURE 13 - MAXIMUM RATED FORWARD BIAS
SAFE OPERATING AREA
..
-- -- - -/.
30
20
...c;;~
!iii
~
~
'"'z
;;l!
0
.Ii?
10
7.0
5.0
--------
-
=1==1=1=1=
FIGURE 14 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
25
10 "s
100 "s
-,...,1.0 m•
>--
5.0 7.0
..
z
10
MTM/MTP8N08
0
!i?
1= MTM/MTP8P08
=
3.0
..,""
""
1.0
0.7 =TC=25°C
VGS = 20 V. Singla Pulsa
0.5
0.3
2.0
150~C
~
I'....
- - : - rOS(on) Limit
- - :.. - Paekaga Lim~
~--- Thermal Limit
I - TJI..,
15
~
3.0
-
~
:'!.
de
2.0
20
'"~
10 ms
1-,'
. . .
.rTM/~~Pl~
10
20
3D
50
70
100
lOO
5.0
o
o
-
MTM/MTP8Nl0
20
40
60
80
100
VOS. DRAIN-TO-SOURCE VOLTAGE (VOLTS)
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
FORWARD BIASED SAFE OPERATING AREA
SWITCHING SAFE OPERATING AREA
The dc data of Figure 13 isbasedonacasetemperature(Tc)of
25°C and a maximum junction temperature (TJmax)of 150°, The
actual junction temperature depends on the power dissipated in
the device and its case temperature. For various pulse widths,
duty cycles, and case temperatures, the peak allowable drain
current (10M) may be calculated with the aid of the following
The switching safe operating area (SOA) of Figure 14. is the
boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the peak
current. 10M and the breakdown Voltage. V(BR)OSS' The
switching SOAshown in Figure 15 isapplicabJeforboth turn~on
and turn~off of the devices for switching times less than one
microsecond.
The power averaged over a complete switching cycle must be
less than:
equation:
10M
o to .
= I (250C)[ TJ(max) - TC
1
TJ(max) - TC
ROJC . r1t)J
ROJC
where
IO(25°C)
TJ(max)
TC
Po
ROJC
r(t)
=the dc drain current atTC =25°C from Figure 13
::: rated maximum junction temperature
;:: device case temperature
= rated power dissipation at TC = 25°C
:::: rated steady state thermal resistance
= normalized thermal response from Figures 11
and 12
TMOS POWER FET CONSIDERATIONS
Switching Speed - The switching speeds of these devices are
dependent on the driving impedance. Extremely fast switching
speeds can be attained by driving the gate from a voltage source.
Transfer Characteristics - The transfer characteristics are
linear at drain curren'ts of 500 rnA. (See Figure 6.) Linear amplifiers with high frequency response can be designed using this
product.
Gate 'Voltage Rating - Never exceed the gate voltage rating
of ±20 V. Exceeding the rated VGS can result in permanent
damage to the oxide layer in the gate region.
Gat8 Termination - The gate of these devices are essentially
capacitors. Circuits that leave the gate open-circuited or floating
should be avoided. These conditions can result in turn-on of the
devices due to voltage build-up on the input capacitor due to
leakage currents or pickup.
Gate Protection - These devices do not have an internal
mOr1t;Jlithic zener diode from gate to source. The addition of an
internal zener diode may result in detrimental effects· on the
reliability of a power MOSFET. If gate protection is required, an
external ,zener diode is recommended.
Handling and Packaging - Mo.S ICs are susceptible to damage
from electrostatic charge. Experience has shown that these
devices are more rugged than MOS ICs. This is primarily due
to the comparatively larger capacitances associated with
power devices, however, reasonable precautions in handling
and packaging MOS devices should be observed.
MOTOROLA TMOS POWER MOSFET DATA
C-166
®
MTM10N08
MTM10Nl0
MTP10N08
MTP10Nl0
MOTOROLA
Designer's Data Sheet
10 AMPERE
N-CHANNEL TMOS
POWER FET
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
rOS(on) = 0.33 OHM
SO and 100 VOLTS
These TMOS Power FETs are designed for high speed power
switching applications such as switching regulators, converters,
solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds Specified at 100°C
MTM10NOS
MTM10Nl0
Switching Times
• Designer's Data - lOSS, VDS(onl, VGS(thl and SOA
Specified at Elevated Temperature
t.
SEATING PLANE
• Rugged -
SOA is Power Dissipation Limited
~~
~
• Source-to-Drain Diode Characterized for Use With
Inductive Loads
,r
"O[~~L RULES AND NOTES ASSOCIATED WITH
REFERENCEDTO-2D4AA OUTLINE SHAll APPLY.
STYLE 3:
PIN 1. GATE
2. SOURCE
CASE DRAIN
TMOS
,
S
MAXIMUM RATINGS
Rating
Symbol
MTM10NOS MTM10N10
MTP10NOS MTP10N10
Unit
Orain-Source Voltage
VOSS
80
100
Vdc
Drain-Gate Voltage
(RGS = 1.0 MOl
VOGR
80
100
Vdc
Gate-Source Voltage
VGS
MIlliMETERS
DI. MI. MAX
A
39.31
B
21
C
D D.91
1.78
1.4D
F
30.15Bse
G 10.92BSC
5.46B5e
H
16.89Bse
J
X 11.18 12.19
3.81
4.19
26.7
U 2.54
3.05
V 3.81
4.19
±20
CASE1-G4
TO-2D4AA
(TO-3TYPEI
..
••
MTP10NOS
MTP10Nl0
Vdc
Adc
Drain Current
Continuous
Pulsed
Gate Current - Pulsed
Total Power
Dissipation @ TC = 25°C
Derate above 25°C
Operating and Storage
10
10M
10
25
IGM
1.5
Adc
Watts
Po
TJ, Tstg
75
0.6
W/oC
-65 to 150
°C
Temperature Range
G 0
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Maximum Lead Temp. for
Soldering Pu rposes, liS"
from case for 5 seconds
S
DIM
A
R8JC
1.67
°CIW
TL
275
°C
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
B
C
D
F
G
H
2.79
J
K
0.36
12.70
L
1.14
N
•.
n
Designer'. Data for "Worst Case" Conditions
The Designer's Data Sheet permits the design of most circuits entirely from
the information presented. Limit curves-representing boundaries on device
characteristics-are given to facilitate "worst case" deSign.
CASE 221A-02
TO-220AB
MOTOROLA lMOS POWER MOSFET DATA
C-167
2.54
R
2.04
S
1.14
T
U
5.97
0.16
1.14
0.,
MTM/MTP10N08,10
I
ELECTRICAL CHARACTERISTICS ITC = 25°C unless olherwise nOled)
I
Characteristic
Symbol
Min
Max
80
100
-
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS = 0,10 = 5.0 rnA)
Vdc
VIBR)OSS
MTM 1ON08/MTPI ON08
MTM10Nl0/MTP10Nl0
;Zero Gale Voltage Drain Current
(VOS = 0.B5 RatjJd VOSS, VGS = 0)
TJ= 100°C
lOSS
Gate-Body Leakage Currenl
(VGS = 20 Vdc, VOS = 0)
IGSS
mAdc
-
0.25
2.5
-.
500
2.0
1.5
4 .• 5
4.0
-
nAdc
ON CHARACTERISTICS'
Gale Threshold Vollage
(10 = 1.0 rnA, VOS = VGS)
TJ= l000C
VGS(lh)
Drain-Source On-Voltage (VGS = 10 V)
(10 = 5.0 Adc)
(10= 10 Adc)
(10 = 5.0 Adc, TJ = 100°C)
VOSlon)
-
1.65
4.0
3.3
Static Drain-Source On-Resistance
(VGS = 10 Vdc, 10 = 5.0 Adc)
rOSlon)
-
0.33
Ohms
9fs
2.5
-
mhos
Forward Transconductance
(VOS = 15 V.IO= 5.0 A)
Vdc
Vdc
SAFE OPERATING AREAS
Forward Biased Safe Operating Area
Swilching Safe Operating Area
DYNAMIC CHARACTERISTICS
Input Capacitance
)-O'-U_I.::.P_ul'-C_a,:.p_a_c'_·ta_n_c_e_ _ _- - j IVos = 25 V, VGS = 0, f = 1.0 MHz) I-~;?!"---+-----t--=--+--~::----t
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS' (TJ = 100°C)
tdlon)
Ir
-
50
ns
(VOS = 25 V, 10 = 5.0 A,
150
ns
Rgen = 50 ohms)
Id(off)
-
100
ns
If
-
50
ns
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
SOURCE DRAIN DIODE CHARACTERISTICS'
Symbol
Typ
Unit
Forward On-Vollage
I
IS= lOA
VSO
2.0
Vdc
Forward Turn-On Time
I
VGS=O
ton
n.
Reverse Recovery Time
I
80
700
Characteristic
I"
"Pulse Test: Pulse WIdth ..s;;;300 iJ.S. Duty Cycle ~2%.
RESISTIVE SWITCHING
FIGURE 1 - SWITCHING TEST CIRCUIT
FIGURE 2 - SWITCHING WAVEFORMS
Outpul. VOUI
Inverted
MOTOROLA TMOS POWER MOSFET DATA
C-168
n5
MTM/MTP10N08, 10
TYPICAL CHARACTERISTICS
FIGURE 3 - OUTPUT CHARACTERISTICS
12
!If- VGS = 20 V
10 V
t-f-
10
...
~
ii'l
Tj = 25~C- -
I
I
B.O
~
J
6.0
7.0 V
B.O
~
6.0
;;;: 4.0
0
'"
I
2.0
0
0
10
20
40
30
7.0 V
I
6.0 V
III
510 V
4.0
2.0
~
'"~
<>
>
2. 6
;::
2. 4
~
2. 2
r---..
:E" 2. 0
fii 1. B
~
~
o
-25
25
50
75
100
TJ. JUNCTION TEMPERATURE (0C)
125
ia
~
J
40
VDS= 10V
I
I
I
2.0
o
o
150
//-
'/
/I
'II
~~
2.0
8.0
6.0
4.0
12
FIGURE 8 - CAPACITANCE VARIATION
1000
t _-
VGS = 10V
0.4
TJI = 25 0
VGS = 0 V
f= 1.0MH,-
80 0
t;;
TJ
loooc
25°C
lil
-55°C
~ O. 2
:;'\
:Z
<.$
O. 3
~
::>
<>
<> O. 1
2.0
4.0
\\
600
"- ~
5
~
0
10
VGS. GATE·TO-SOURCE VOLTAGE (VOLTSi
5
~
25"C
100"C
1//.
6.0
z
<>
V
//
1 V-I1L LA-
FIGURE 7 - 'OS(onl- ON·RESISTANCE ve.sus
DRAIN CURRENT
~
1
~
- --
t----...
12
10
r---- / /
~ 8.0
............ r-.
-50
I
TJ - -55"C
10
VOS = VGS
10 = 1.0 mA- -
.....r---.
3. 0
<>
x
;;
I
3. 4
3. 2
B.O
FIGURE 6 - TRANSFER CHARACTERISTICS
2
9 2. B
'"
li'
6.0
VOS. DRAIN-TO-SOURCE VOLTAGE (VOLTSi
FIGURE 5 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
~
-
I
VOs. DRAIN-TO-SOURCE VOLTAGE (VOLTSi
u;
!:o
I
1
I,
60
50
,
/'
12
510 V
b -
TJ = 25 C_
810 V
I
~ 4.0
0
6.0 V
2.0
I
,I V
//
z
z
12
~
....
I
1 /
1 1/
u;
I
ON·REGION CHARACTERISTICS
If- t-VGS= 20 V
10 V
jo-
10
vris = BIO V
u;
....~
I
FIGURE 4 12
6.0
8.0
400
\
200
o
o
10
Ciss
.....
"-
-
10
Coss
20
Crss
30
40
VDS. ORAIN-TO-SOURCE VOLTAGE (VOLTSi
10. DRAIN CURRENT (AMPSi
MOTOROLA TMOS POWER MOSFET DATA
C-169
-
50
MTM/MTP10N08, 10
SAFE OPERATING AREA INFORMATION
FIGURE 10 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
FIGURE 9 - MAXIMUM RATED FORWARD BIASED
SAFE OPERATING AREA
25 I-
•
- -. :.:t:t.it
100
- -.., LOrn.
1--
I--
~.
f-of-o- l;!~
"""
10
'"
!!!!
...
0;-
:;
10m.
~ Tl<;;150ic
30
~
l-
ia
de
~
.a
IZ
e-- TC; 25°C
~
~
40
10 ~.
VGS ; 20 V. Single Pul••
1.0
F
----- rOS(oni
Limit
r-- Package Limit
t==
'".s?
r--
~
1.0
MTM/MTP10NOS ,....-
Q
.s? 10
MTM/MTP10Nl0
Thermal limit
o
o
MTM/MTP10NOS
MTM/MTPI ONI 0
0.1
20
z
III
10
20
40
60
SO
Vas. DRAIN·TO·SOURCE VOLTAGE (VOlTSI
100
100
VOS. ORAIN·TO·SOURC,E VOLTAGE (VOLTSI
FORWARD BIASED SAFE OPERATING AREA
SWITCHING SAFE OPERATING AREA
The dc data of Figure 9 is based on a casetemperature
(Te) of 25°C and a maximum junction temperature
(TJmax) of 150°. The actual junction temperature depends on the power dissipated in the device and its case
temperature. For various pulse widths, duty cycles, and
case temperatures, the peak allowable drain current
(10M) may be calculated with the aid of the following
equation:
The switching safe operating area (SOA) of Figure 10
is the boundary that the load line may traverse without
incurring damage to the MOSFET. The Fundamental
limits are the peak current, 10M and the breakdown
voltage, V(BR)OSS' The switching SOA shown in Figure
10 is applicable for both turn-on and turn-off of the
devices for switching times less than one microsecond.
The power averaged over a complete switching cycle
must be less than:
IO(25'C)[TJ(max) - TC]
Po . RWC . r(t)
TJlmax) - TC
Rwe
where
IO(25°C) = the dc drain current at TC = 25'C from
Figure 9.
TJ(max) = rated maximum junction temperature.
device case temperature.
TC
rated power dissipation at TC = 25'C.
Po
rated steady state thermal resistance.
RWC
r(t)
normalized thermal response from
Figures 11 or 12.
MOTOROLA TMOS POWER MOSFET DATA
C-170
MTM/MTP10N08, 10
THERMAL RESPONSE
FIGURE 11 -- MTM10N08/10N10
0
7= t=
-
0= 0.5
5
3 - i-
0.2
....-::::;; 1iII~
2
I-- t- I- 0.1
If--- I- 0.05
P ~ 0.02
.......
0.02
...
ROJCIII = rill RoJC
ROJC - 1.67°C/W Max
D curves apply for power
±,nn
V
0.05
JLl
0.1
0.2
-
-
1J~2~
II
0.01
0.02
=
-
Pulse train shown
Read lime alII
_
TJlpkl - TC = Plpkl R9JCIII=
-
DUTY CYCLE. D 1)/12
I- f--;:::: i::;:~
0.01
SINGliPUtSE
........
:'t:'
.......
0.5
1.0
2.0
11111
5.0
10
I. TIMElmsl
20
50
100
200
500
1000
2000
FIGURE 12 -- MTP10N08/10N10
0.7
0.5
~
~_
.,J
TMDS
S
CASE '-04
TO-204M
(TO-3TYPE)
MAXIMUM RATINGS
R.ting
Svmbol
MTM10N12 MTM10N15
MTP10N12 MTP10N15
Unit
Drain-Source Voltage
Drain-Gate Voilege
(RGS = 1.0 MO)
VOSS
120
150
Vdc
VOGR
120
150
Vdc
Gate-Source Voltege
VGS
±20
Drain Current
Continuous
Pulsed
10
10M
10
28
Gate Current - Pulsed
IGM
'1.5
Vdc
MTP10N12
MTP10N15
Adc
Total Power
Dissipation @ TC = 25·C
Derate above 25·C
Opsrating and Storage
Tempsrature Range
Adc
Watts
Po
TJ, Tstg
75
0.6
W/·C
-66 to 150
·C
THERMAL CHARACTERISTICS
Thermal Resilit8nce
Junction to case
Maximum Lead Temp. for
Soldering Purposes, 1/8"
from case for 6 seconds
0'
S
STYLE 5:
PIN 1. GATE
ReJC
1.67
·C/W
TL
275
·C
Delign.,'. Data fo, ''Wont C..... Condition.
I,OrMEIdIQNHmLIEITOALLLEAOS.
Z.OLIIE"IIG" lA"LI&STO LiADil AND)OIlLY.
3.DIME... IONlOEfINE.... ZOliIlWltElULL
.OOVAND LEAD I'"EOULAIUTIU ..."E
ALlOWEO.
4.DIMENIIONINO"IUITOLER""CIIlI8P£II"""
VIU"JJ.
5.COwrlOLLlIIGOIMEIIIIOII:INCN.
2. DRAIN
3. SOURCE
4. DRAIN
..
,,
CASE 221A-C12
TO-22OAB
The Designers Data Sheet psrmlts the design of most circuits entirely from the
information presented. Limit data - representing device characteristics boundaries - are
given to facilitate "worst ca.... design.
MOTOROLA TMOS POWER MOSFET DATA
C-172
NOTES:
I
MTM/MTP10N12. 15
I
I
ELECTRICAL CHARACTERISTICS ITc = 25°C unless otherwise. noted)
I
Characteriric
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS = 0, 10 = 5.0 mAl
Symbol
Min
Max
120
150
-
V(BR)OSS
MTM10NI21MTP10NI2
MTM10N15/MTP10N15
Zero Gate Voltage Drain Current
(VOS = 0.B5 Rated VOSS, VGS = 0)
TJ = 100°C
lOSS
Gate-Body Leakage Current
(VGS = 20 Vdc, VOS = 0)
IGSS
Unit
Vdc
-
mAdc
-
0.25
2.5
2.0
1.5
4.5
4.0
-
1.5
3.0
2.5
500
nAdc
ON CHARACTERISTICS'·
Gate Threshold Voltage
(10 = 1.0 mA, VOS = VGS)
TJ= 100°C
Drain-Source On-Voltage (VGS = 10 V)
(10= 5.0 Adc)
(10= 10 Adc)
(10 = 5.0 Adc, TJ = lOOOC)
Vdc
VOS(on)
Static Drain-Source On-Resistance
rOS(on).
-
0.3
Ohms
9fs
2.5
-
mhos
Ciss
-
1200
pF
Coss
-
500
pF
Crss
-
120
pF
-
50
ns
180
ns
td(otl)
-
200
ns
tf
-
100
ns
VGS
(VGS = 10 Vdc, 10 = 5.0 Adc)
Forward Transconductance
(VOS = 10V, 10 = 5.0 A)
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
(VOS = 25 V, VGS = 0, f = 1.0 MHz
Output Capaoitanc~
(VOS = 25 V, VGS = 0, f = 1.0 MHz
Reverse Transfer Capacitance
(VOS = 25 V, VGS= 0, f= 1.0 MHz
SWITCHING CHARACTERISTICS' (TJ = lOOOC)
Turn-On Delay Time
(VOS = 25 V, 10 = 5.0 A, Roen = 50 ohms)
td(on)
Rise Time
tr
(VOS = 25 V, 10 = 5.0 A, Rgen = 50 ohms)
Turn-Off Delay Time
(VOS = 25 V, 10 = 5.0 A, Rgen = 50 ohms)
Fall Time
(VOS = 25V, 10 = 5 ..0 A, Raen = 50 ohms)
SOURCE DRAIN DIODE CHARACTERISTICS'
Symbol
Typ
Unit
IS= 10A
VSO
1.3
Vdc
VGS = 0, dildt = 25 AIl's
ton
trr
250
ns
325
ns
Characteristic
I
Forward On-Voltage
I
I
Forward Turn-On Time
Reverse Recovery Ti me
·Pulse Test Pulse Width ~300 p.S, Duty Cycle ::S;;;2%.
RESISTIVE SWITCHING
FIGURE 1 - SWITCHING TEST CIRCUIT
FIGURE 2 - SWITCHING WAVEFORMS
'd(an)
r- -Age; - - - j
Pulse Generator
I
I
I
IL
:
I
Output, V out
Inverted
50
n
I
_______ ...JI
MOTOROLA TMOS POWER MOSFET DATA
C-173
I
I
--
MTMlMTP10N12, 15
TYPICAL CHARACTERISTICS
FIGURE 4 - ON-REGION CHARACTERISTICS
FIGURE 3 - OUTPUT CHARACTERISTICS
•
.
20
0;:!'
~
~
a'"'"
3!;
~
Q
16
12
8.0
10 V
r
9V
,
,
./
TJ
~
20
:!'
....~
16
'"
a
12
~
[)
'";;;:
7V
'"
'">
3.2
30
9
2.S
;=
2.4
'"'"~
60
f--
~
a'"'"
:;;:
'"
.......... r-....
'"
'"
.!?
t-.......
I'-......
o
25
50
75
100
TJ. JUNCTION TEMPERATURE 1°C)
-25
~ I--IO'~
>
'"
w
'"~
=>
"!
1.0
'"
~
125
7.0
TJ • 25°C
I
I
TJ.' -55°C
I
1.8j
'II
1.#
4.0
J - lOooC
I
I
h
/ ' / -55°C
I'l. -I -I
":.IV
I~ V
I
I
4.0
6.0
S.O
VGS. GATE-TO-SOURCE VOLTAGE (VOLTS I
2.0
10
FIGURE 8 - CAPACITANCE VARIATION
1600
,....,
~
==
1200
5'"
...- H
t::::10 • 4.0 A
:: 800
5
400
'"
~
>
JI IIJ. i--
6.0
150
~
'"~ 0.1
-
2000
......r
~
6V
5V I--
10
o
1=1=10 - 20 A
w
7V
VOS' 10V
2.0
10
~
[/
I
I
FIGURE 7 - ON-VOLTAGE VARIATION
versus TEMPERATURE
~
r- r-
15 8.0
~ 2.0
-50
SV
I-
.......
....
~ 2,2
I
V
1/ . /
V [....-
!.! ~
2.0
3.0
4.0
5.0
6.0
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS)
12
:!'
~
I'---.
5; I.S
V
10 VV' I -
FIGURE 6 - TRANSFER CHARACTERISTICS
...... t--......
!i:
'"'
14
...........
2.6
~~
~
1.0
1
VOS ~ VGS
10 ~ 1.0 rnA
20 V
/. v. . . .
1.1'
20
30
40
50
Vas. ORAIN·TO·SOURCE VOLTAGE (VOLTS)
25°C
/
S.O
4.0
6V
!:;
1
~
~V
FIGURE 5 - GATE·THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
'"~
~
Q
0;-
VG
10-
5V
~
TJ
r-
.!?
10
1
I
~
25°C
8V
.!? 4.0
1
-60 -40 -20 0 20 40 60 SO 100 120
TJ. JUNCTION TEMPERATURE (OCI
,
\..
\........
1\ "\
-
.............
"-
I
TJ ~ 25°C
VGS = 0 V
f~ 1.0 MHz
f--
Ciss
1
Coss
Crss
10
20
30
Vas. DRAIN·TO·SOURCE VOLTAGE (VOLTSI
MOTOROLA TMOS POWER MOSFET DATA
C-174
f--
40
MTMIMTP10N12, 15
TYPICAL CHARACTERISTICS
FIGURE 9 - ON-RESISTANCE versus
FIGURE 10- ON-VOLTAGE VARIATION
DRAIN CURRENT
0.30
VGS= 10V
TJ = 100°C
u; 0.25
~
:::e
:I:
co
J
~
0.20
I 25
:1
~
0.15
1-55O~
~ 0.10
0
--
12
/
;;;
--
TJ = 25°C
~
10
~
!:l
co
,.'"
S.O
a:
~
6.0
"I
c
z
..,.
4.0
SA
6A
4A
iii0
2.0
IA
~
5
t
~ 0.05
,.'"
\
IDA
2A
0
o
o
4.0
S.O
12
10. DRAIN CURRENT IAMPSI
16
a
20
a
2.0
-
~~ I - -
-
4.0
6.0
S.O
10
VGS. GATE-TO·SOURCE VOLTAGE IVOLTSI
12
14
THERMAL RESPONSE
FIGURE 11 - MTM10N12/MTM10N15
1. 0
O. 7~
~O 0.5
5
31--- r-
-
0.2
;;;;;;;; ".
2
I-- r- 0.1
II-- r- 0.05
P F- 0.02
0=
0.02
..-
.......
=
0.2
o
0.3
'--
Ilh2~
0.5
1.0
2.0
FIGURE 12 -
0.7
0.5
-
±'TIfi
II
0.1
-
OUTY CYCLE. 0 = 11/12
--;:::.. f:::;;:
II
0.05
5.0
10
t. TIME Im.1
II II
20
50
100
~~
200
500
1000
2000
MTP10N12iMTP10N15
0.5
02
0.2
I
oi
Plpkl
0.1
~ ~ 0.07 1==.0.05
~ - 0.05
z
1--0.02
~ 0.03 I I.J--t 2 -0.02 ~I --:--:bo-A-+++tt-......,f--f---+-+++-+t+f--+-+-t-H DUTY CYCLE. DOli 112
:::e!>!
"eJCltl = rill RsJC
RsJC = 1.67°C/W Ma.
ocurve. apply for power
Pulse ,train shown
_
Read lime at II
.
_
T.I(""I - TC = Plpk, RsJCII)
-
0.01
~INGl\ PUtSE
0.01
0.02
;;:s
...
I--
ROJCIII - rill R9JC
ROJC - 1.67°C/W Ma.
tSlJl
o curves apply for power
--:1'11--1
Pulse train shown
Read lime at 11
TJlpk) - TC = Plpkl ROJCIII
r-
0.01..---+--1
0.01
0.02
SI~G\E r~Ln
0.05
0.1
02
0.5
1.0
2.0
I.
5.0
TIME 1m.)
10
20
MOTOROLA TMOS POWER MOSFET DATA
C-175
50
100
200
500
Ik
MTM/MTP10N12, 15
SAFE OPERATING AREA INFORMATION
FIGURE 14 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
FIGURE 13 - MAXIMUM RATED FORWARD BIAS
SAFE OPERATING AREA
30
20
-- -- ----- I'..
- --
,:
=TJ~:s
1'..1.0ms
-
10
~s
35
i'
10 ms
--
- -rDSlon) Limit
_____ Package limit
de
---Thermal Limit
I.......
11 LI
TJ';150°C
I-TC = 25°C,
~VGS - 20 V Single Pulse
0.3
3,0
MTM/MTPlON12MTM/MTP10N12
MTM MTP10N15
t10
30
50
100
VDS, DRAIN-TO·SOURCE VOLTAGE IVOLTS)
5.0
o
200
Po
FORWARD BIASED SAFE OPERATING AREA
The dc data of Figure 13 is based on a case temperature (TC) of 25°C and a maximum junction temperature
(TJmax) of 150°, The actual junction temperature de:
pends on the power dissipated in the device and its case
temperature. For various pulse widths, duty cycles, and
case temperatures, the peak allowable drain current
(10M) may be calculated with the aid of the following
equation:
IO(250C)[TJ(max) - TC]
Po . R/lJC . r(t)
where
IO(25°C) = the dc drain current at TC = 25°C from
Figure 13.
TJ(max) = rated maximum junction temperature.
device case temperature.
TC
MTM(MTP10~15
o
R/lJC
r(t)
20
40
60
80
100
120
VOS. DRAIN·TQ·SOURCE VOLTAGE IVOLTS)
140
160
rated power dissipation at TC = 25°C.
rated steady state thermal resistance.
normalized thermal response from
Figures 11 or 12.
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) of Figure 14
is the boundary that 'the load line may traverse without
incurring damage to the MOSFET. The Fundamental
limits are the peak current, 10M and the breakdown
voltage, V(BR)OSS. The switching SOA shown in Figure
14 is applicable for both turn-on and turn-off of the
devices for switching times less than one microsecond.
The power averaged over a complete switching cycle
must be less than:
TJ(max) - TC
R/lJC
TMOS POWER FET CONSIDERATIONS
Switching Speed - The switching speeds of these devices are
dependent on the driving impedance. Extremely fast switching
speeds can be attained by driving the gate from a voltage
of the devices due to voltage build-up on the input capacitor
due to leakage currents or pickup.
source.
Gate Protection - These devices do not have an internal monolithic zener diode from gate to source. The addition of an
internal zener diode may result in detrimental effects on the
reliability of a power MOSFET. If gate protection is required,
an external zener diode is recommended.
Transfer Characteristics - The transfer characteristics are linear at drain currents of 500 rnA. (See Figure 6.) Linear amplifiers with high frequency response can be designed using this
product.
Gate Voltage Rating - Never exceed the gate voltage rating
of ±20 V. Exceeding the rated VGS can result in permanent
damage to the oxide layer in the gate region.
Handling and Packaging - MOS ICs are susceptible to damage
from electrostatic charge. Experience has shown that these
devices are more rugged than MOS ICs. This is primarily due
to the comparatively larger capacitances associated with
power devices, however, reasonable precautions in handling
and packaging MOS devices should be observed.
Gate Termination - The gate of these devices are essentially
capacitors. Circuits that leave the gate open-circuited or floating should be aVOided., These conditions can result in turn-on
MOTOROLA TMOS POWER MOSFET DATA
C~176
®
MTM10N25
MTP10N25
MOTOROI.A
Designer's Data Sheet
N-CHANNEL TMOS
POWER FET
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
'OS(on) = 0.45 OHM
250 VOLTS
These TMOS Power FETs are designed for 120 V line operated
high speed power switching applications such as motor controls,
switching regulators, converters, solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds Specified at 100°C
MTM10N25
Switching Times
~IE=~~
~ .~.
• Designer's Data - 'OSS, VDS(on), VGS(th) and SOA
Specified at Elevated Temperature
• Rugged -
-. 0:--
SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With
Inductive Loads
SEATING PLANE
_
•..
J
U
CASE 1-04
TO-2D4AA
(T0-3 TYPE)
D
E
F
G
H
J
K
D
MTM10N25
MTP10N25
Unit
Drain-Source Voltage
Voss
250
Vdc
Drain-Gate Voltage
(RGS = 1.0 MOl
VOGR
250
Vdc
VGS
±20
Vdc
10
10M
10
30
IGM
1.5
. Drain Current
Gate Current -
•
U
V
Adc
Continuous
Pulsed
Pulsed
Total Power
Dissipation @ TC 0 25°C
Derate above 25°C
Operating and Storage
Temperature Range
Adc
Watts
Po
100
O.S
W/oC
TJ, Tst9
-65 to 150
°c
R8JC
1.25
°C/W
TL
275
ST~I~E 2.~~
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Maximum Lead Temp. for
.,.-
MILLIMETERS
••
C
MAXIMUM RATINGS
Gate - Source Voltage
•
NOTES:
1. ALL RULES ANO NOTES ASSOCIATED WITH
REFERENCED TD·3 OUTLINE SHALL APPLY.
DIM
Symbol
GATE
DRAIN
3. SOURCE
4. DRAIN
°c
Soldering Purposes, 1IS"
from case for 5 seconds
Designer·. Data for "Worst Case" Conditions
CASE 221A-02
TO-220AB
The Designer's Data Sheet permits the design of most circuits entirely from
the information presented. Limit curves-representing boundaries on device
characteristics-are given to facilitate "worst case" design.
MOTOROLA TMOS POWER MOSFET DATA
C-177
.
,
'
STYlE 3
PIN 1 GATE
2 SOURCE
CASE DRAIN
s
...1
"l
•
H
,r
Rating
_______ .. ___
~
""
Q
TMOS
•
10 AMPERE
I
MAX
39.37
21.08
7.62
,.,
6.3
0.91
1.40
1.18
30.1588C
10.92B8C
5.46BSC
16.B9BSC
11.18 12.19
3.Bl
4.19
26.67
2.54
3.05
3.81
4.19
INCHES
M.X
1.550
0.83
MI.
-
o.
0.043
0.055 0.070
1.187BSC
O.OBC
O.2ISBSC
0.6658SC
oA40 0.480
0.151 0.185
1.050
0.100 0.120
0.038
-
.,51
D.l
MTM/MTP10N25
ELECTRICAL CHARACTERISTICS (Tc = 25°C unless otherwise noled)
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS = 0, 10 = 5.0 mAl
V(BR)OSS
MTM10N26/MTP10N2&
Zero Gate Voltage Drain Current
(VOS = 0.B5 Rated VOSS, VGS= 0)
TJ= l000C
Gate-Body Leakage Current
(VGS = 20 Vdc, VOS = 0)
lOSS
,
IGSS
Min
Max
250
-
-
0.25
'2.5
-
500
Unit
Vdc
mAdc
nAdc
ON CHARACTERISTICS'
Gate Threshold Voltage
(10 = 1.0 mA, VOS = VGS)
TJ= 100°C
Drain-Source On-Voltage (VOS = 10 V)
(10 = 5.0 Adc)
"
(10= 10Adc)
(10 = 5.0 Adc, TJ = 100°C)
VGS(lh)'
Vdc
4.5
4.0
rOS(on)
-
2.25
5.60
4.50
0.45
9ls
3.0
VOS(on)
Static Drain-Source On-Resislance
(VGS = 10 Vdc, 10" 5.0 Adc)
Forward Transconductance
(VOS= 15 V, 10= 5.0 A)
','
2.0
1.5
Vdc
Ohms
mhos
SAFE OPERATING AREAS
Forward Biased Sale Operating Area
Switching Sale Operaling Area
DYNAMIC CHARACTERISTICS
Input Capacitance
r,,-0_ut.;,p_u_t..,Ca::'..
pa_c..,it_an_c,..e_-,-_ _-i (VOS = 26 V, VGS = 0, 1= 1.0 MHz) f--,?-"--+------+-..,.."""'--+'---'-~-_i
Reverse Transfer capacitance
SWITCHING CHARACTERISTICS' (TJ = 100°C)
Turn-On Delay Time
td(on)
tr
(VOS = 26 V, 10 = 5.0 A,
Rgen = 50 ohms)
See Figures 1 and 2.
Rise Time
Turn-Off Oelav Time
Fall Time
Id(9fft
If
-
1;10
ns
-
250
100
ns
ns
120
ns
SOURCE DRAIN DIODE CHARACTERISTICS'
Characteristic
Forward Turn-On Time
I
I
Reverse Recovery TIme
I
Forward On-Voltage
Symbol
Typ
Unit
IS= IDA
VSO
1.5
Vdc
VGS=O
Ion
Irr
50
ns
300
ns
·Pulse Test: Pulse Width E;;300 ~s. Duty Cycle "2%.
RESISTIVE SWITCHING
FIGURE 1 - SWITCHING TEST CIRCUIT
FIGURE 2 - SWITCHING WAVEFORMS
v~~R~ut
~
V.
td(on)
OUT
Output. VOUI
Inverted
MOTOROLA TMOS POWER MOSFET DATA
C-178
MTM/MTP10N25
TYPICAL CHARACTERISTICS
FIGURE 4 - ON-REGION CHARACTERISTICS
FIGURE 3 - OUTPUT CHARACTERISTICS
20
20
VGS; 8.0 V
20 V /9.0V
1
~
~ 16
:;;
,
§
'-'
~ 8.0
6.0 V
C
-
20
40
60
80
VDS. DRAIN·TD-SOURCE VOLTAGE (VOLTS)
o
FIGURE 5 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
g
ac
Q
..........
"""-
1.0
Q
>
~
'"'
f!l
'"'
"""-
0.90
~
-50
>
100°C
Z
~
.!?
50
75
100
.........
IW
.I
8.0
VDg; 10 V
4.0
....-
FIGURE 7 - ON RESISTANCE versus
DRAIN CURRENT
en
e.
'"'
~
~
~
1.0
o. 8
A
VGS;10V
V
0.6
./
~
--- --
'-'
ac
:::>
f-"'"
Q
~ 0.4
~
0.2
~
0
V
FIGURE 8 - CAPACITANCE VARIATION
/
/
25°~
TJ1;
_
VGS; 0 V
f; 1.0MH.- t - -
1600
./
1./
t! 1200
25°C
5
"
::i!
~55°C
~
-~
4.0
8.0
12
10. DRAIN CURRENT (AMPS)
16
800
u
Ciss
t-
400
20
Coss
\.
o
o
Crss
10
20
30
40
VDS. DRAIN-TD-SOURCE VOLTAGE (VOLTS)
MOTOROLA TMOS POWER MOSFET DATA
C-179
r--
\
c(
t
o
10
2000
TJ; 100°C
A
71
/,1
'/
~V
2.0
4.0
6.0
8.0
VGS. GATE· TO-SOURCE VOLTAGE (VOLTS)
TJ. JUNCTION TEMPERATURE 1°C!
:;;
//
f)
o
o
150
125
VI
--I
2
Q
"'
25
~
a
~
"-.,
-25
25°C
~
0.80
10.70
I
I
~
...~
~55°C
~ 16
!;;
""-
20
FIGURE 6 - TRANSFER CHARACTERISTICS
VDS; VGS
ID;1.0mA
.......,."
~
~
4.0
8.0
12
16
VDS(on). DRAIN-TO-SOURCE VOLTAGE (VOLTS)
TJ;
1.1
~
...
5.0 V
20
12
~:&
6.0 V
II
o
100
7.0 V
/,
4.0
5.0 V
I
8.0 V
---
W
If'
Q
TJ ; 25°C
/ /. ~ -VGS; 9.0 Ii
0...-
~./.
TJ; 25°C
~ 12
t
ldv /,
~
~trY-
~
7.0 V
o
o
_I.
-VGS;20V
50
•
MTM/MTP10N25
SAFE OPERATING AREA,INFORMATION
FIGURE 9 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
30
20
:=~
in
!Ii
,t::::
,......
10
f---
.91.0
0.7
0.5
1.0
.u.IOO~S 10~s
1[: '
ia
de
"- .....
rOSlon) Lim~ - - - Package Lim~ - - Thermal Limit - - -
2
f
!,...
IO ms
iz
a 3.0
~co
40
-
~.:::::
r-
;- 7.0
5.0
FIGURE 10 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
24
~ 16
Q
.9 B.O
TC = 25°C
VGS I= 20 Vi Singl~I~~lse
3.0 5.07.010
3D 5070100
o
o
3005007001000
VOS. ORAIN·TO·SOURCE VOLTAGE IVOLTS)
MTM/MJP10N25 TJE;;150OC
50
100
150
200
VOS. ORAIN·TO·SOURCE VOLTAGE IVOLTS)
FORWARD BIASED SAFE OPERATING AREA
The de data of Figure 9 is based on a case temperature
ITe) of 25°e and a maximum junction temperature ITJmax) of
1500 . The actual junction temperature depends on the power
dissipated in the device and its case temperature. For various
pulse widths, duty cycles, and case temperatures, the peak allowable drain current (10M) may be calculated with the aid of the
following equation:o
= I 1250el TJlmax) - Te ]
o
LPo . RBJe . rlt)
where
loI25°C) = the dc drain current at Te = 25°e from Figure 9.
TJ(max) :::: rated maximum junction temperature
Te
::: device case temperature
Po
::: rated power dissipation at Te::: 25°C
ROJC
= rated steady state thermal resistance
r(t)
= normalized thermal response from Figures 11
and 12
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) of Figure 10, is the
boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the peak
current, 10M and the breakdown voltage. VIBR)OSS. The
switching SOA shown in Figure 10 is applicable for both
turn-on and turn-off of the devices for switching times less than
one microsecond.
The power averaged over a complete switching cycle must be
. les. than:
TJ(max) - Te
RBJe
MOTOROLA TMOS POWER MOSFET DATA
C-180
250
MTM/MTP10N25
THERMAL RESPONSE
FIGURE 11 - MTM10N25
~
wz
0=0.5
1,0m_
_~111
0.5
fil~ ~~ 0.3
1---+-++++ U
0.2
;;..~
___
"~ ..ffi 0.1
0.05
I--f$~ill :: 0.0'2~~~~i~~101'liiii-lf-i111111;'>~i~J
0.
0
2
05
li! ~ 003r-. ,---.,..r'" p.ql,
~
Plpkl
.. :z:
~i
i-""
0
•
ReJCltl = 1.25°C/W Max
==~ R6JCIII=rtllReJC
0 Curves Apply for Power
=~ Pulse Train Shown
tl '""
=~ Read Time at tl
C;2 0
1_
TJlpkl- TC=PlpkI R6JC(tl
uty yee. =tl t2
I
-t=
~ ::::~"""""':---L-J·I,-:-,::,-Srr.J...U.J.rE
II 1=--1--:':::--'-~.
0.01 0.02 0.05 nr_E
0.1 -:'-:-'---'-..I.-..I...L.L.---'---I......J.....JI-:-,--,-,I
0.2 0.5 1.0 2.0 5.0 1.. u10. . .111---'--l--'--::-.L..U..J
20
100 200 500 1000
50
t. TIME (m.)
FIGURE 12 - MTP10N25
R6Jcltl = rltl R6JC
R6JC(tl = 1.25°C/W Max
oCurves Apply for Power
Pulse Train Shown
Read Time at 11
TJ(pkl - TC = Plpkl R9JC(tl
0.05 0.1
02
05 1.0
2.0
5.0
t. TIME (ms)
10
20
50 100 200
500 1.0
k
TMOS POWER FET CONSIDERATIONS
Switching Speed - The switching speeds of these devices are
dependent on the driving impedance. Extremely fast switching
speeds can be attained by driving the gate from a voltage source.
devices due to voltage build·up on the input capacitor due to
leakage currents or pickup.
Gate Protection - These devices do not have an internal
monolithic zener diode from gate to source. The addition of an
internal zener diode may result in detrimental effects on the
reliability of a power MOSFET. If gate protection is required, an
external zener diode is recommended.
Transfer Characteristics - The transfer characteristics are
linear atdrain currents of 2.0Amps.(See Figure 6.) Linear amplifiers with high frequency response can be designed using this
product.
Gate Voltage Rating - Never exceed the gate voltage rating
of ±20 V. Exceeding the rated VGS can result in permanent
damage to the oxide layer in the gate region.
Handling and Packaging - MOS )Cs are susceptible to damage
from electrostatic charge. Experience has shown that these
devices are more rugged than MOS ICs. This is primarily due
to the comparatively. larger capacitances associated with
power devices, however, reasonable precautions in handling
and packaging MOS devices should be observed.
Gate Termination - The gate of these devices are essentially
capacitors. Circuits that leave the gate open·circuited or floating
should be avoided. These conditions can result in turn·on of the
MOTOROLA TMOS POWER MOSFET DATA
C-181
®
M[M12NOS,NrrM12N06
M[P12NOS,NrrP12N06
MOTOROLA
Designer's Data Sheet
12 AMPERE
N-CHANNEL TMOS
POWER FET
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
'OS(on); 0.2 OHM
60 and 60 VOLTS
These TMOS Power FETs are designed for low voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds - Switching Times
Specified at 100°C
MTM12N05
MTM12N06
• Designer's Data - lOSS. VDS(on) and SOA Specified at
Elevated Temperature
~
• Rugged - SOA is Power Dissipation limited
• Source-to-Drain Diode Characterized for Use With
Inductive Loads
L
-w
'EAT"'~LAIIE.~
-@J
..
Q
o
STYLE 3
PIN 1.
2.
lr
H
TO-204AA
S
(T0-3TVPE)
Symbol
MTM12N05 MTM12N06
MTP12N05 MTP12N06
Unit
Voss
50
60
Vdc
VOGR
50
60
Vdc
VGS
±20
10
10M
12
30
IGM
1.5
Wc
MTP12N05
MTP12N06
Adc
Pulsed
Total Power
Dissipation @TC.;25°C
Derate above 25°C
Operating and Storage
Temperature Range
Adc
Watts
PO'
75
0.6
W/oC
TJ. Tstg
-65 to 150
°c
R8JC
1.67
°CIW
TL
275
°c
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Maximum Lead Temp. for
Soldering Purposes, 1IS"
from case for 5 seconds
STYLES:
PINt. GATE
DRAIN
SOURCE
4. DRAIN
CASE 221A-G2
TO-220AB
Designer's Data fo, "Worst Case" Conditions
The DeSigners Data Sheet permits the design of most circuits entirely from the
information presented. Limit data - representing device characteristics boundaries - are.
given to facilitate "worst case" design.
MOTOROLA TMOS POWER MOSFET DATA
C-182
•
DIM
MilLIMETERS
M,N MAX
A
39.37
C
Drain-Source Voltage,
Gate Current - Pulsed
0
•
CASE 1-114
Drain-Gate Voltage
(RGS = 1,0 MO)
Drain Current
Continuous
It
I
U .
MAXIMUM RATINGS
Gate-Source Voltage
+
GATE
SOURCE
CASE DRAIN
TMOS
Rating
J
<5
• Low Drive Requirement. VG(th) = 4.5 Volts (max)
-
21.08
7.62
6.35
0.91
1.09
1.40
1.78
F
30.1585C
G
lO.!l2BSC
H
1i.46BSC
J
16.898se
X 11.18 12.19
Q
3.81 4.1
R
26.67
U 2.54
3.05
4.19
V 3.81
D
E
INCHES
M,N MAX
1.550
D.BlO
.25
.00
0.038 0.043
0.055 0.070
1.18785C
0.4 DB
0.21585C
0.66585C
0.440 0.480
.165
" 0 1.050
0.100 0.120
0.150 0165
-
MTM/MTP12N05,06
I
ELECTRICAL CHARACTERISTICS (TC = 25·C unless otherwise noted)
Characterl,dc
Symbol
I
OFF CHARACTERISTICS
Drain-Source Breekdown Voltege
(VGS = 0, 10 = 5.0 mAl
V(BR)OSS
MTM12N05/MTP12N05
MTM12NOB/MTP12NOB
Zero Gale Voltage Drain Currenl
(VOS = 0.85 Raled VOSS, VGS = 0)
TJ=I00·C
Gale-Body Leakage Currenl
(VGS = 20 Vdc, VOS = 0)
lOSS
Min
50
60
-
ON CHARACTERISTICS·
Gale Threshold Vollage
(10= 1.0 mA, VOS= 0)
TJ = l00·C·
Drain-Source On-Vollage (VGS = 10 V)
(10 = B.O Adc)
(10= 12 Adc)
(10 = B.O Adc, TJ = 100·C)
Static Drain-Source On-Resistance
(VGS = 10 Vdc, 10 = B.O Adc)
Forward Transconductance
(VOS = 15 V, 10= B.OA)
VGS(lh)
VOS(on)
--
Vdc
mAde
-
0.25
2.5
500
2.0
1.5
4.5
4.0
-
Ohms
mhos
IGSS
Unit
nAdc
Vdc
We
rOS(on)
-
1.2
3.2
2.4
0.2
9fs
3.0
-
-
-
SAFE OPERATING AREAS
Forward Biased Safe Operaling Area
Switch i ng Safe Operati ng Area
See Figure 9
See Figure 10
OYNAMIC CHARACTERISTICS
Inpul Capecitance
Outpul Capacilance
(VOS = 25 V, VGS = 0, f = 1.0 MHz)l-_o='--_+-_ _ _-+_-:-~-_t_---''--_I
Reverse Transfer Capacilance
SWITCHING CHARACTERISTICS· (TJ = lOO·C)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Idlon)
Ir
(VOS = 25 V, 10 = B.O A,
Rgen = 50 ohms)
Idloffl
If
SOURCE DRAIN DIODE CHARACTERISTICS·
Cheractarl.tlc
Forward On-Voltage
IS= 12A
Forward Turn-On Time
VGS=O
Reverse Recovery Time
.
J
J
I
-
-
BO
.160
80
110
Symbol
Typ
VSD
2.0
80
700
Ion
Irr
Pulse Test. Pulse Width ~300 #lS. Dutv Cvcle ~2% .
RESISTIVE SWITCHING
FIGURE 1 - SWITCHING TEST CIRCUIT
FIGURE 2 - SWITCHING WAVEFORMS
Idlon)
Output, Vout
Inverted
MOTOROLA TMOS POWER MOSFET DATA
C-183
ns
ns
ns
ns
Unit
Vdc
ns
ns
MTMlMTP12N05,06
FIGURE 3 - OUTPUTCHARACTERISTICS
18
•
f
f1
/...
16
I
-VGS=20V
10 V
~
I
I
~
~ B.O
7.0 V
E4.0
6.0 V
::.
~
/J /
o
10
20
3D
40
VoS. oRAIN·To·SOURCE VOLTAGE (VOLTS)
'"'!.
~
,
!:j
1.0
'"
>
9
'"
:I:
til
0.90
""" """
....
:I:
...c.o
~ 0.80
10.70
>
-50
I
I I
20
f
az
~ 8.0
.......
25
50
75
125
100
0
C
/,
W/
.
E
J /
/
25°C- 'rJ.t /
!/. ... 100
J
1/
4.0
.Ail
........
-25
, I
TJ = -55°C- ~
~ 12
'"
,I
,I
VOS-l0 V
~ 16
!i;
r-....
)0
FIGURE 6 - TRANSFER CHARACTERISTICS
VOS = VGS
10=1.0mA
"'" '"
5.0 V
2.0
4.0
6.0
S·.O
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS)
24
""
6.0 V
o
50
1.2
1.1
7.0 V
r£
FIGURE 5 - GATE·THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE (NORMALIZED)
~
8.0 V
'ff/
5.'0 V
~
TJ = 25°C
VGS = 9.0 V
U/
o
o
VGS = 10 V
/ / ,/
,
,
r
/
I V/
It / '
8.0 V
!i; 12
V
VGS=2DVV
VGS = 9.0 V
If
~
FIGURE 4 - ON-REGION CHARACTERISTICS
,
20
TJ = 25°C
~V
2.0
150
TJ. JUNCTION TEMPERATURE (OC)
FIGURE 7 - ON-RESISTANCE versus
DRAIN CURRENT
4.0
6.0
8.0
10
VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)
12
14
FIGURE 8 - CAPACITANCE VARIATION
1200
VGS=10V
1000
/
~
V
TJ = 100°C
V
-55°C
\
600
\
'-'
z:
- I--
25°C
800
5~
8.0
12
10. DRAIN CURRENT (AMPS)
16
\
."-
-r--
;3 400
u
,\
200 \.
o
4.0
TJ = 25°C
VGS = 0 V
f = 1.0 MHz
20
o
'-..
10
coss
l -i---
cr!s
20
30
40
50
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS)
MOTOROLA TMOS POWER MOSFET DATA
C-1B4
ciss
r--
60
MTMlMTP12N05, 06
SAFE OPERATING AREA INFORMATION
FIGURE 9 - MAXIMUM RATED FORWARO BIASED
SWITCHING SAFE OPERATING AREA
FIGURE 10 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
100
40
r--
-,
'.
~;Z •
!-..
.
10 J.Lsec
~ 30
r-- 100itsec
.
.
::;;
~
- o~J~~
....
~
B
z
Package Limit
---rOS(on)limit
Thermal limit
VGS = 20 V
Single Pulse
TC = 25°C
1.0
1.0
20
~
10
-
MTM/MTPI2N06
MTMfMTPI ~N05 ::J:::;:
-
il'i
0:
12
:::>
5.0 V
/
<.>
~ 8.0
410- r-
E
I
4.0
III
2.0
3.0
4.0
5.0
6.0
VOS, ORAIN·TO·SOURCE VOLTAGE (VOlTS)
2.0
7.0
0:
:::>
<.>
~
c
TJ =-55°C_ Io{#
15
10
E
5.0
~
o
o
I
'f
'"
J
~1 6
~o:
1
J
G
10
0.24
z
~
I--
......r
VGS=10V
..-
~ 0.20
~
~
~
2:
'"~
z
0.16
in
!?
..& V
4.0
2.0
6.0
8.0
10
12
FIGURE 6 - ON-RESISTANCE versus
DRAIN CURRENT
..A
~J = looo~- I -I-""
1 1 1
1 j ..l
in 0.2 0
:;
:z:
!:!.
t-- t- VG~ = 10 ~
~ 0.1 6
TJ 1= 100dc
.,~
~
0.1 2
~
<.>
TJ
=25°.C
TJ
=-55°C
I-- r-
0.12
0.08
TJ
-55°C - I--
~
-
c
~ 0.0 8
~
-r-
0:
:::>
0
1m
o
o
12
~J = ~5OC_ I--
:; . 0.04
1
IJ
VGS, GATE TO SOURCE VOLTAGE (VOLTS)
~ 0.2 8
:z:
~
~
4.0
FIGURE 5 - ON-RESISTANCE versus
DRAIN CURRENT
!:!.
lY
c
VOS= 10V
VA
IIIJ. t- TJ = 100°C r-
12
z
~ 8.0
6.0
4.0
8.0
VGS, GATE·TO-SOURCE VOLTAGE (VOLTS)
10
.l.L
..6 t: TJ1= 2SoC-TJ = -55°C 't-I 'I
J.J.
~
TJ - 100°C
w
2.0
8.0
LL
1
I-- t- VOS=10V
20
bV
W/
,W-
6.0
FIGURE 4 - TRANSFER CHARACTERISTICS
// V
;
4.0
24
V/
5. 20
>-
I
6.0 1V
VOS, ORAIN·TO·SOURCE VOLTAGE (VOLTS)
FIGURE 3 - TRANSFER CHARACTERISTICS
2S
TJ - 25 C_
VG! = 5.0 1V
~
30
~
:;
I
vG~
0:
C
3.5 V
J _ .J,
VG! = 7.0 1V
IVI
0:
_r-
~~
FIGURE 2 - ON-REGION CHARACTERISTICS
20
8.0 V
~ 0.0 4
:i'
c
0
5.0
10
15
20
2S
10. ORAIN CURRENT (AMPS)
30
~
0
4.0
8.0
12
10. DRAIN CURRENT (AMPS)
MOTOROLA TMOS POWER MOSFET DATA
C-189
16
20
MTMlMTP12N08, 10
TYPICAL CHARACTERISTICS
FIGURE 7 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
1.2
§"
!:!
.
:=;
II
FIGURE 8 - CAPACITANCE VARIATION
2000
""-
1.1
15
~
~
'">3
1.0
VDS = VGS
10 = 1.0 rnA
~
~
9
~i=
0.90
~
O.BO
;:li
f"-...
~
i'..
~
~
50
25
-25
~
1200
~_
;:l
BOO
z
I'-.-.
~O.70
>
-50
100
75
TJ = 25°C
VGS = 0 V
f = 1.0 MHz
1600
"
\...
\....... t---
I
...........
\
..........
Coss
"'-..
Crss
150
125
Ciss
'\.
400
~
-
10
20
30
VOS. DRAIN·TO·SDURCE VOLTAGE IVOLTSI
TJ. JUNCTION TEMPERATURE lOCI
40
THERMAL RESPONSE
FIGURE 9 - MTM12N08/MTM12N10
MTM15N05/MTM15N06
1.0
~
0" 0.5
0.5
"'z
~ i5
. tt:~~~
"'~
Q",
ffi
~
"'0:
,. ...
=
I-
QZ
0.2
0.1
'-
0.05
1--"-
.
0,1
-:.-
,...- ...-- I-"
I--'"
\ .•...--'
0.0
0.0 I
0.01
0.02
frrmr
0.1
o curves applv for power
=f::=
tlrJ
12
DUTY CYCLE. 0 "11/12 -
P·9 1,
0.05
ROJCIII = rill ROJC
ROJC = 1.67°C/W Max
I
1==1 I 111111
PIPW~ r==
~
0.0 5
~ ~ 0.0 3 -
....
;?'
0.02
Z"'
1=
-
b.l
0.3
r--
I I 11I111
0.2
0.5
1.0
II III
2.0
5.0
10
I
Pulse train shown
Read lime al "
TJlpkl - TC = Plpkl ROJCIII
20
I
II III
50
100
I
200
500
t. TIME (ms)
FIGURE 10 - MTP12N08/MTP12N10
MTP15N05/MTP15N06
10
07
0.5
u
~
'0.3
-,5
0.2
~
"'~
::Eo:!
~;
...
",
0=05
-
02
-
O. 1
~ ~ 0.07 =005
~ -
0.05
~
'='
003
0.02
-0.02
~
.....n-
0.01
001
0,02
--=
;;;..- --~
01
Plpkl
tJUl
I-"
Read lime al t 1
TJlpkl - Te = Plpkl ROJCIII
DUTY CYCLE. 0 = 11"2
SI~G\E r~Lf\
0.1
o curves apply for power
Pulse Irain shown
~~~
,/
0.05
ROJCIII = rill R8JC
R8JC 1.67°C/W Max
0.2
0.5
1.0
2.0
5.0
10
20
I, TIME 1m.)
MOTOROLA TMOS POWER MOSFET DATA
C-190
50
100
200
500
1000
MTMlMTP12N08, 10
OPERATING AREA INFORMATION
FIGURE 11 -
40
--
30
20
i
;
~
-
1.0 ms
de
"
3.0
2.0
10p5_
100 pI
-I-t"-
10 ms
5.0
Q
.!?
- --t---
-
- """~
10
;::- 7.0
a
MAXIMUM RATED FORWARD BIAS
SAFE OPERATING AREA
---rDS(on) Lim~
---- Packaga limit
r-....
FORWARD BIASED SAFE OPERATING AREA
- - . Thermal limit
1.0
0.7 VGS = 20 V. ~ingla Pulsa_ r-- MTM/MTP12N08
-TC = 25°C
MTM/MTP12Nl0
0.4
2.0
3.0
5.0 7.0
10
20
30
50
70
100
200
VDS. DRAIN·TO-SOURCE VOLTAGE (VOLTS)
FIGURE 12 -
The dc data of Figures 11 and 12 is based on a case temperature (TC) of 25°C a nd a maximum I unction temperature (TJmax)
of 150°C. The actual junction temperature depends on the power
dissipated in the device and its case temperature. For various
pulse widths. duty cycles. and case temperatures. the peak
allowable drain current (10M) may be calculated with the aid of
the following equation:
MAXIMUM RATED FORWARD BIAS
SAFE OPERATING AREA
Where
10 (25°C)
=de drain currentatTc= 25°C from Figure
11 or 12
Rated maximum hmction temperature
TJmax
::=
TC
Po
ROJC
r(t)
= Oevice caSe temperature
= Rated power dissipation at TC = 25°C
=Rated steady state thermal resistance
= Normalized thermal response from Figures 9
and 10.
MTM/MTPI5N05
MTM/MTP15N06
0.1 ,::---'--'---:-,:-,-:,-:-,-u..':-':---'---'-_=--...l...:~..L..L.l:'
1.0
3.0
5.0
10
30
50
100
VDS. DRAIN-TO-SOURCE VOLTAGE (VOLTS)
SWITCHING
SAFE OPERATING AREA
FIGURE 13 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
40
i
The switching safe operating area (SOA) of Figure 13. is the
boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the peak
current. 10M and the breakdown voltage. V(BR)OSS. The switching SOA shown in Figure 12 is applicable for both turn-on and
turn~off of the devices for switching times less than one microsecond.
The power averaged over a complete switching cycle must be
less than:
30
!i
azi20
:
TJ'" 15O'C
Q
.!?
10
I--
r--
o
o
ro
MTM~15N05- ,..---
MTMIMTPI5N06
MTMIMTPI2N08
MTMIMTP12NI0
~
~
40
~
~
~
~
00
~
VOS. DRAIN-TD-SOURCE VOLTAGE (VOLTS)
MOTOROLA TMOS POWER MOSFET DATA
C-191
•
MTM12N18,MTP12N18
MTM12N20,MTP12N20
MTM15N12,MTP15N12
MTM15N15,MTP15N15
•
®
MOTOROLA
Designer's Data Sheet
12 and 15 AMPERE
N-CHANNEL TMOS
POWER FET
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
180 and 200 VOLTS
•
Silicon Gate for Fast Switching Speeds Specified at 1 4.0
// V
4.0
J .;:rI I V
7
T}= -55 C .......
'/
H.
'IA.
2S)C
!
20
L-55)C, ......... ..,I II J
'1/
//.
~#
2.0
VGS. GATE-TO-SOURCE VOLTAGE (VOLTSI
4.0
6.0
B.O
10
VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)
ON-RESISTANCE versus DRAIN CURRENT
FIGURE S - MTM12N1S. MTM12N20
MTP12N18.MTP12N20
FIGURE 7 - MTM16N12. MTM15N15
MTP16N12.MTP16N16
iii 0.30
I
i
I
!.,.
0.2 5
-
I
I
TJ = 100°C
---
~ 0.1 5
~
I!i
g
-55°C
0.10
ur
S' 0.05
o
4.0·
B.O
~o:
,..,
'j
12
/"
---""2~-
0.3
d
20
4.0
10. DRAIN CURRENT (AMPS)
B.O
12
10. DRAIN CURRENT (AMPS)
MOTOROLA TMOS POWER MOSFET DATA
C-194
----
V~S= 10,V-I - -
1
,
16
J.
TJ=1000y
-55 C
VGS= 10V- f---
I
I
I
~ 0.4
---
25O~
/
e
./
V
-I
0.20
iii 0.5
111
./
16
20
MTMlMTP12N18,20,15N12,15
TYPICAL CHARACTERISTICS
FIGURE 9 - GATE·THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
is
1.2
I
1.1
~
~
..........
"'" "'"
w
c.o
;:!:
1.0
g
9
~ 0.90
Vas ° VGS
10°I.OmA
~
1200
g
"-....
...........
~
800
400
$ 07~50
-25
25
75
50
100
125
"
Coss
Crss
o
o
150
r-
\.
c.o
t
Ciss
r-...
u
i'.. ......,
0.80
-
-
\
«
~
I'-...
~
..
TJ o 25°C _
VGS ° 0 v
f°I.OMHz-
1600
~
i!:
~
FIGURE 10 - CAPACITANCE VARIATION
2000
20
10
30
40
VOS. ORAIN·TO·SOURCE VOLTAGE IVOLTSI
TJ. JUNCTION TEMPERATURE lOCi
50
THERMAL RESPONSE
FIGURE 11 - MTM12N18. MTM12N20. MTM15N12 AND MTM15N15
1.0
~
0.5
§~
0.3
wz
0·0.5
bJ
'" 0.2
0'"
~ ~ 0.1
u.
UoI
... ..'" 0.05
"'oz
CI: ~
zw
~! 0.03 ~
2---
0.0
.............
0.0 1
0.01
-
--= :;;0. ....
-;;;-
f1--"'"
0.1
0.05
...
w~
PI~~
111=====
0.02
,......
12
..,...
~
'Isrrmr
0.D2
0.05
0.1
_
Outy Cycle. 0 = 11/12 -
p.Ql.
0.2
=
-
1.0
2.0
5.0
10
Read Time at t1
TJlpk) - TC = Plpk) R6JCII)
II III
II III
0.5
R6Jcll) = ~I) R6JG
R6JClt) = 1.25°C/W Max
o CUNSS Apply for Power
Pulse Train Shown
50
20
100
200
SOD
IODD
I,TlMElm.)
~
io~
=
..,
~
FIGURE 12 - MTP12N18, MTP12N20, MTP15N12 AND MTP15N15
1.0
0.1
0.5 0·0.5
0.3
0.2
In
~
...
0.2
0.1
R6Jcll) = ~I) R6JC
R6JCII) = 1.25°C/W Max
0.1
0.07 r-- 0.05
~ 0.05
~
-0.02
:: 0.03
~,....
~ 0.02 """"'~---b-l""H-I++1--1-1I--l-·+-H-H-++-+-+--+-+--1
~
~
0.01 ..... ....-,
..
0.D1
0.02
-:i
"
SI~Gn~Lr~
0.05
0.1
o Curve. Apply for Power
Pulse Train Shown
Read Time at t1
Duty Cycle. 0 = 11/12
IIIII
0.2
10
05
I, TIME
TJlpk) - TC = Plpk) R9JCII)
I I
I I I IIIII
20
fms~
MOTOROLA TMOS POWER MOSFET DATA
C-195
50
100
I I
200
I I I III
SOD
l.ok
MTMlMTP12N18,20, 15N12,15
RATED SAFE OPERATING AREA INFORMATION
.FIGURE 13 - MTM15N12. MTM15N15
MTP15N12. MTP15N15
•
FORWARD BIASED SAFE O'PERATING AREA
The de data of Figure$13and 14 i.sbased on a case temperature
ITC) of 25°C and a maximum junction temperature ITJmax) of
150°, The actual junction temperature depends on the power
dissipated in the device and its case temperature. For various
pulse widths, duty cycles. and case temperatures, the peakallow.able .drain current 110M) may be calculated with the aid of the
following equation:
10 a
-
-- I-----
"'::;.1-
rOSlon) Lim~ ---Thermal Limit--
Package limit
a
s
1. ms
.........
0
10",=
a
a
- F"'-<
de
10M
--
VGS - 20 V Single Pulse- r- MTM/MTP15N12
MTM/MTPI5NI5
TC= 25°C'
-
r-
0, I
3,0
5,0
200 300
1
100
30
50
VOS. ORAIN-TO-SOURCE VOLTAGE IVOLTS)
FIGURE 14 - MTM12N18. MTM12N20
MTP12N18. MTP'12N20
10a
= I 1250cl TJlmax)' TC ]
ROJC . r(t)
o
[,po .
where
IO(25°C) =the dcdrain currentatTc = 25°C from Figures 13
and 14
TJlmax) ::; rated maximum junction temperature
::;;
device
case temperature
TC
::;; rated power dissipation at TC = 25°C
Po
= rated steady state thermal resistance
ROJC
rlt)
= normalized thermal response from Figures 11
and 12
SWITCHING SAFE OPERATING AREA
-
-
100
N.:0 ms
.........
a
The switching safe operating area (SOA) of Figure 15, is the
boundary that the load line may traverse without incurring
damage to the -MOSFET. The fundamental limits are the peak
current. 10M and the breakdown Voltage. VIBR)OSS. The
switching SOAshown in Figure 14 is applicable for both turn-an
and turn-off of the devices for switching times less 'than one
microsecond.
The power averaged over a complete switching cycle must be
less than:
1',- .,----10 ps
10 ms
de
rOSlon) Limit - - Thermallimit---
i"'-..
Package limit- - -
a
TJlmax) -.IC
VGS - 20 V Single Pulse
TC = 25°C
0_ 1
3.0
5,0
MTM/MTP12N18
MTM/MTP12N20
10
30
50
100
ROJC
200
VOS. ORAIN-Til-sOURCE VOLTAGE IVOLTS)
FIGURE 15 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
50
iE
40
:!
!!.
;]
a""z
:c
30
MTM/MTP15N12
MTM/MTP15N15
MTM/MTP12N18
20
MTM(MTPI2N20
""
Q
JP
10 ) - - f- TJ
"
o
o
....--
"150~C
,
40
80
120
160
200
Vos. ORAIN·TO-SOURCE VOLTAGE IVOLTS)
MOTOROLA TMOS POWER MOSFET DATA
C-196
®
MTM15N18
MTM15N20
MTM20N12
MTM20N15
MOTOROLA
Dpsig-IH'I"S Data Sheet
15 and 20 AMPERE
N-CHANNEL TMOS
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTORS
POWER FET
=
roSlon)
0.18 OHM
1ao and 200 VOLTS
These TMOS Power FETs are designed for high-speed power
switching applications such as switching regulators, converters,
solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds SpeCified at 100·C
=
rDS(on)
0.12 OHM
120 and 150 VOLTS
Switching Times
• Designer's Data - lOSS, VDS(on), VGS(th) and SOA
Specified at Elevated Temperature
• Rugged - SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
loads
,r
TMOS
MTM15N1S
MTM15N20
MTM20N12
MTM20N15
s
r;=AL~B
:r
MAXIMUM RATINGS
C
MTM
Rating
Symbol
20N12
20N1S
1SN18
1SN20
Unit
Drain-Source,voltage
VOSS
120
150
180
200
Vdc
Drain-Gate Voltage
(RGS = 1.0 MO)
VDGR
120
150
180
200
Vdc
Gate-Source Voltage
K
t
0
!'lANE
Vdc
Adc
Drain Current
Continuous
Pulsed
Gate Current -
±20
VGS
-t
t-="E
SlATING
10
10M
Pulsed
Total Power
Dissipation @ TC = 25·C
Derate above 25°C
Operating and Storage
Temperature Range
IGM
20
100
15
80
Adc
1.5
150
1.2
wrc
TJ, Tstg
-65 to 150
RruC
0.83
"C
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Maximum Lead Temp. for
Soldering Purposes, 118"
from case for 5 seconds
TL
STYLE 3,
PIN 1. GATE
2" SOURCE
CASE. DRAIN
Watts
Po
0c/w
·C
275
MI LlMETEAS
DIM MIN MAX
A 38.35 39.31
1.3 21.
1.&2
8.
D
1.46
1.811
3.43
E
F
29.9 30.411
1
11.18
-
K
Q
11.18
3.84
2
12.19
4.
INCHES
MIN
MAX
1.510 1.550
0.80 0.8
0.051
-
1.111
0.
0.440 0._
0.151 D.111
21.
Designer's Data for "Worst Cas." Conditions
The Designer's Data Sheet permits the design of most circuits entirely from the
information presented. Limit data - representing device characteristics boundaries - are
given to facilitate "worst case" design.
MOTOROLA TMOS POWER MOSFET DATA
C-197
0.1183
0.1
.1
D.
CASE 197-01
TO-204AE TVpe
(TO-3TYPE)
MTM15N18, 20/20N12, 15
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Symbol
Characteristic
I
Min
Max
I
Unit
OFF CHAR.o.CTERISTICS
Drain-Source Breakdown Voltage
(VGS = 0, 10 = 5.0 rnA)
Vdc
V(BR)OSS
MTM20N12
MTM20N15
MTM15N18
MTM1.5N20
120
150
lBO
200
Zero Gate Volt"ge Drain Current
(VOS = 0.8 Rated VOSS, VGS = 0)
(TJ = 1000C)
lOSS
Gate-Body Leakage Current
(VGS = 20 Vdc, VOS = 0)'
IGSS
-
-
mAde
-
-
0.25
2.5
-
500
2.0
1.5
4.5
4.0
nAdc
ON CHARACTERISTICS'
Gate Threshold Voltage
(10 = 1.0 mA, VOS = VGS)
(TJ= l000C)
Vdc
VG5(lh)
Static Drain-Source On~RE:,sistance
(VGS = 10 Vdc, 10 = 10 Adc)
(VGS = 10 Vdc, 10 = 7.5 Adc)
rOS(on)
MTM20N 121MTM20N 15
MTM15Nl B/MTM15N20
Drain-Source On-Vollage (VGS = 10 V)
MTM20Nl21MTM20N15
(10= 20 Adc)
MTM20N12/MTM20N15
(10 = 10 Adc, TJ = l000C)
MTM15N18, MTM15N20
(10= 15 Adc)
MTM15Nl B/MTM15N20
(10 = 7.5 Adc, TJ = 100°C)
Forward Transconductance
(VOS = 15 V.IO= 10 A)
(VOS = 15 V. 10 = 7.6 A)
VOS(on)
ats
MTM20N12/MTM20N15
MTM15N18/MTM15N20
Ohms
-
0.12
0.16
-
3.0
2.4
3.0
2.4
8.0
4.0
-
Vdc
mhos
-
DYNAMIC CHARACTERISTICS
Input Capacitance
fc0=-U_I'-P_ul_c-::a:-'-p_a_ci-,.Ia_n-;c:-e_-::-_--I (VOS = 25 V, VGS = 0, f = 1.0 MHz)
Reverse Transfer Capacitance
f---::.=-=---+-----:-t--=::---i
SWITCHING CHARACTERISTICS' (TJ = 100°C)
Turn-On Delay Time
.Id(on)
(VOO = 25 V, 10 = 0.5 Raled 10,
Rise Time
Turn·Oll Delay Time
-
ns
220
Id(oll)
Fall Time
60
300
Ir
Rgen = 50 ohms,
See Figures 1 and 2)
If
-
250
SOURCE DRAIN DIODE CHARACTERISTICS'
Characteristic
Forward On·Voltage
Forward Turn-On Time
Reverse Recovery Time
*Pulse Test: Pulse WIdth
~300
I
I
Symbol
Typ
Unit
(IS - Raled 10,
VSO
2.0
Vdc
VGS=O,
Ion
50
ns
Irr
450
ns
I
IJ.s. Duty Cycle :S;:;Z%.
RESISTIVE SWITCHING
fiGURE 1 - SWITCHING TEST CIRCUIT
FIGURE 2 - SWITCHING WAVEFORMS
'd(on)
Output, Vout
Inverted
MOTOROLA TMOS POWER MOSFET DATA
C-198
I
MTM15N18, 20/20N12, 15
TYPICAL CHARACTERISTICS
ON-REGION CHARACTERISTICS
FIGURE 3 - MTM20N12, MTM20N15
FIGURE 4 - MTM15N18, MTM1&N20
so
100
~
BO
I--
TJ; 12S0C
~
~
z
~
--
/ " I-"
:;;
>-
k::::::
60
.....O!e
40
~~
£> 20
~
oVo
~
10V
10 V
B.OV-
~
-
~V
10
4.0
6.0
B.O
o
o
10
-
"
1.0 V
6.0V
S.OV
6.0
2.0
4.0
B.O
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
VDS. ORAIN·TO·SOURCE VOLTAGE (VOLTS)
II
B.O V
~V
~
S.O V
I
> I--"'"
l/::: ~
~ I"""
6.0 V
2.0
~
TJ - 2SoC
9.0 V
1.0V-
~
Q
VGS=20V
VGS;20V _
10
TRANSFER CHARACTERISTICS
FIGURE 6 - MTM15N18. MTM15N20
FIGURE 5 - MTM20N12. MTM20N15
so
VI
TJ = -55°C
2SoC
--I 1/ /
20
/
--Ii /
~
I
If. _100°C
V
~
I'
I /
J. f- TJ';2SoC
13
z 8.0
,A
~
~
Q
£>4.0
V/I
...0 ~
o
r---
~ 12
#. ,.4-100?C
o
-SSoc
~
1//
I-- -Vas; 10 V
VOS=10V
16
o
10
2.0
4.0
6.0
B.O
VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)
~
b:;:::: ~
o
2.0
Jl
V/J
VI
4.0
VGS.
GATE·TO·SOU~CE
6.0
8.0
VOlTAGE (VOLTS)
10
ON-RESISTANCE versus DRAIN CURRENT
FIGURE B - MTM15N18. MTM1&N20
FIGURE 7 - MTM20N12. MTM20N15
iii" 0.20
:;;
e'"
.,_
I-V~S= lJV
~ 0.16
-
TJ; 100°C
i
~ 0.12
w
u
:;;
-I-"
::::I
Q
6
..,.
0.08
'" 0.32
ii
-Ssoc
---
~
~. 6.24
~
:;:
l§ 0.04
~
§
20
30
40
TJ
w
u
!5
5l
z
10
VSs= 10 V
Q
-
250
oc
0.40
50
~
.
0.16
0.08
0
~5OC
-55°C
o
4.0
10. DRAIN CURRENT lAMPS)
MOTOROLATMOS POWER MOSFET DATA
C-199
100°C
8.0
12
10. DRAIN CURRENT lAMPS)
16
20
MTM15N18, 20/20N12, 15
TYPICAL CHARACTERISTICS
FIGURE 9 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
II (:'
I
FIGURE 10 - CAPACITANCE VARIATION
4000
"'-
VOS =VGS
iO =1.0 mA
"'-..
t_
T)= 25 0
f-VGS = 0
f=I.OMHz- e---
3200
~
~
~
""'" "'-.. r---....
1.0
~
~
0.90
~
1='
~
""
0.80
;:li
~2400
25
50
75
\...
\:
11800
d
.......
100
800
'-,125
"
o
l"-.. ....
Ciss
"-
Crss
o
150
Coss
r-.
10
20
30
40
50
"os. ORAIN-TO·SOURCE VOLTAGE (VOLTSj
TJ. JUNCTiON TEMPERATURE (OCj
THERMAL RESPONSE
FIGURE 11 - MTM15N18, MTM15N20, MTM20N12 AND MTM20N15
1.0
;
'"
_
-' S
~~
ffici
0.5
0.3
0.2
0.2
-
0.1
R9JC(tj ~tj R9JC
R9JC =0.83°C/W Max
D curves apply for power
Pulse train shown
Read time at 11
~ ~ 0,1
!Z ~ 0.07 =0.05
~
-
0.05 _
0.02
~
TJ(pkj - TC = P(pkj R9JC(tj
0.05
0.1
0.2
0.5
1.0
2.0
5.0
10
20
I. TIME (m.j
MOTOROLA TMOS POWER MOSFET DATA
C-200
50
100
200
500
1.0 k
MTM15N18, 20/20N12, 15
RATED SAFE OPERATING AREA INFORMATION
FIGURE 12 - MTM20N12. MTM20N15
100
"-
:5. 10
....
~
'"
'"
~
'"
~
- - - - - rDS(on) Limil-
dissipated in the device and its 'case temperature. F.or various
pulse widths. duty cycles. and case temperatures. the peak allowable drain current (10M) may be calculated with the aid of the
following equation:
de
Package Limit
::>
Q
~Ims
10ms
:-....
:IE
The de data of Figures 12 and 13 is based on a case temperature
(TC) of 25°C and a maximum junction temperature (TJmax) of
150°, The actual junction temperature depends on the power
101"
100 ",
-
.
FORWARD BIASED SAFE OPERATING AREA
-I---Thormallimil
10M
1.0
VGS=20V
TC = 25°C
Singlo Pulse
E
MTM20N12
MTM20N15
IO(25°C) = the dc drain current atTc= 25°C from Figures 12
and 13.
10
TJ(max) ;;: rated maximum junction temperature.
150
TC
Po
R8JC
r(t)
FIGURE 13 -
MTM15N1 B. MTM15N20
-
- rDS(on) Limit
f-- Thermal limit
r- Package Limit
-
--
100
"S
1.0 ms-
-
"""~ ':::'.
-
---------
10ms
= ....
li'o .
where
VOS. ORAIN-TO-SOURCE VOLTAGE (VOLTS)
100
de
= device. case temperature.
;: rated power dissipation at Tc:::: 25.'1C.
= rated steady state thermal resistance
= normalized thermal response from Figure 11.
SWITCHING SAFE OPERATING AREA
101"
=
-
-
-
=-
.-
The switching safe operating area (SOA) of Figure 14. is the
boundary that the load line may traverse without incurring
dall)age to the M05FET. The fundamental limits are the peak
current. 10M and the breakdown voltage. V(BR)OSS. The
switching SOAshown in Figure 14 is applicable.#or both turn-on
and turn-off of the devices for switching times less than one
microsecond.
The power averaged over a complete switching cycle must be
less than:
TJ(max)- TC
R8JC
I- VGS = 20 V. Single Pulse
D.
MTM15N18MTM15N20
1 r- TC = 25°C
3.0
10
100
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
200
FIGURE 14 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
100
I
MTM20N12
r-----
I
MTM20N15 -
,.---00
I
MTM15N18
TJ";; 150°C
I
MTM15N20
1
o
I
o
50
1
= I (25oclTJ(max)- TC
D
R8JC . r(tU
100
150
200
Vas. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
250
MOTOROLA TMOS POWER MOSFET DATA
C-201
!
~
i
®
MTM15N35
MTM1SN40
.I
MOTOROLA
15 AMPERE
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
TMOS
POWER FET
N-CHANNEl
These TMOS Power FETs are designed for high voltage, high
speed power switching applications such as line operated switching
regulators, converters, solenoid and relav drivers.
=
I'DSlon)
0.3 OHMS
350 and 400 VOLTS
• Silicon Gate for Fast Switching Speeds":" Switching TImes
Specified at .100·C
• Designer's Data - lOSS, VDSton) and SOA Specified at
Elevated Temperature
• Rugged -
SOA is Pc;>wer Dissipation Limited
• Source-to-Drain Diode Characterized for Use With
Inductive Loads
• Low Drive Requirement, VGlthl
1r
= 4.5 Volts.(maxl
~J)
G
TM
TMOS
MTM15N35
MTM15N40
L~'
.
S
Ie
MAXIMUM RAnNGS
Rating
Symbol
MTM15N35
MTM15N40
Unit
Drain-Source Voltage
VOSS
350
400
Vdc
Drain-Gate Voltage
.(RGS = 1.0 MOl
VOGR
350
400
Vdc
Gate·Source Voltage
Drain Current
Continuous
Pulsed
Gate Current -
VGS
±20
Vdc
Adc
10
10M
Pulsed
IGM
1.5
Adc
Po
250
Watts
2.0
wrc
TJ,Tstg
-65 to 150
"C
Total Power
Dissipation @ TC = 25°C
Derate above 25"C
Operating and Storage
Temperature Range
15
70
RfJJC
0.5
"C/W
TL
275
·C
Maximum Lead Temp. for
Soldering Purposes, 118"
from c;ase for 5 saconds
Designer's Data for "Worst ea.... Conditions
K
i
. 0
r--F~
I--J-
a~V
L
STYLE 3:
PIN 1. GATE
2. SOURCE
CASE. DRAIN
A
B
C
D
E
F
G
H
K
a
R
MILUM TERS
MIN
MAX
38.35 39.37
19.30 21.!It
6.35 1.62
1.45 1.80
3.4
29.90 30.40
10.61 11.18
5.
11
11.18 12.19
3 4 4.
24. 9
.61
-
INCHES
MAX
MIN
1.510 1.550
0.160 0.930
0.250 0.3DD
0.051 11.063
0.136
1.111 .IR
0.420 0.440
0.
-
0.440
0.151
0
0.480
0.181
1.
The Designer's Data Sheet permits the deSign of most circuits entirely from the
information presented. Limit data - representing device characteristics boundaries - are
given to facilitate "worst case" design.
MOTOROLA TMOS POWER MOSFET DATA
C-202
1
~
I
+--'E~
H\
,IT
!
~
DIM
THERMAL CHARACTERISTICS
Tharmal Resistance
Junction tD Case
SEATING
PLAN£
CASE 197.01
TO-204AE (TYPE)
(10-3 TYPE)
I
R
lG
MTM15N35, 40
I
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
I
Characteristic
Symbol
Min
Max
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS = O. 10 = 5.0 mAl
Vdc
V(BR)OSS
MTM15N35
MTM15N40
350
400
Zero Gate Voltage Drain Current
(VOS = 0.85 Rated VOSS. VGS = 0)
TJ= 100°C
lOSS
Gate-Body Leakage Current
(VGS = 20 Vdc. VOS = 0)
IGSS
mAde
-
0.25
2.5
-
500
2.0
1.5
4.5
4.0
-
2.25
nAde
ON CHARACTERISTICS'
Gate Threshold Voltage
110 = 1.0 mAo VOS = VGS)
TJ=100oC
VGS(th)
Orain-Source On-Voltage (VGS = 10 V)
(10 = 7.5 Ade)
(10= 15 Adc)
(10 = 7.5 Ade. TJ = 100°C)
VOS(on)
-
4.5
Static Drain-Source On-Resistance
rOSlon)
-
0.3
Ohms
9fs
6.0
-
mhos
Vde
Vdc
6.0
(VGS = 10 Vde. 10 = 7.5 Adc)
Forward Tra nsconducta nee
(VOS = 15 V. 10 = 7.5 A)
SAFE OPERATING AREAS
Forward Biased Safe Operating Area
,Switching Safe Operating Area
DYNAMIC CHARACTERISTICS
Input Capacitance
IVoS = 25 V. VGS = O.
f=1.0MHz)
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS' (TJ = 100°C)
td(on)
Ir
-
IVOS = 125 V. 10 = 7.5 A.
Rgen = 50 ohms)
Id(off)
-
Turn-On Delay Time
Rise Time
Turn-Off Oelay Time
Fall Time
If
120
ns
300
ns
400
ns
240
ns
SOURCE DRAIN DIODE CHARACTERISTICS'
Symbol
Typ
Unit
IS= 15 A
VSO
1.0
Vdc
VGS= 0
Ion
175
ns
Irr
600
ns
Characteristic
Forward On-Voltage
Forward Turn-On Time
Reverse Recovery Time
J
J
I
"'Pulse Test: Pulse Wrdth ::;;;300 JiS, Duty Cycle ~2%.
RESISTIVE SWITCHING
FIGURE 1 - SWITCHING TEST CIRCUIT
FIGURE 2 - SWITCHING WAVEFORMS
Idlon)
Output, Vout
Inverted
MOTOROLA TMOS POWER MOSFET DATA
C-203
MTM15N35. 40
TYPICAL CHARACTERISTICS
FIGURE 4 - ON CHARACTERISTICS
FIGURE 3 - OUTPUT CHARACTERISTICS
5
5
~
VGS = 20 V. 10 v-:7.0 V
•
'"\
/L
17'7 r-VGS = 20 V. 10 V. 7.0 V
TJ = 25°C
TJ = 25°C
0
I/,
6.0 V
5
5
0
0
5.0 V
.0
0
4.0 V
51l
100
150
200
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS)
:11'
V
~
""
"'"l!!:.w
'"b""
1.1
,
"'"
...........
~
10.10
-50
>
0
I
!J
0
..............
..........
'.
50
75
100
125
150
2.0
6.0
8.0
10
5000
i"
-
;:: 0.4
./
TJ = 100°C
V
-
f0-
~ 0.3 r0.2
2 °C
I--
-55°C
400
~
~ 200 o
~
1000
t
TJ = 25°C
VSS= 0
f= 1.0 MHz
o ,\.
~3000
o. 1
~ 00
4.0
FIGURE 8 - CAPACITANCE VARIATION
FIGURE 7 - ON-RESISTANCE versus DRAIN CURRENT
c
~
VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)
O. 5
;;!
~
"
AI
~
0
TJ. JUNCTION TEMPERATURE (OC)
f3
'"w
'"'
'"'"~
..,.
I
I
...........
b"
25
-I I ~1000C
II
"-25
25 O C -
/
/ V
TJ=-55°C-
5
~
0.80
'"""
I I
VOS=20V
~
1.0
20
FIGURE 6 - TRANSFER CHARACTERISTICS
VOS = VGS
lo=1.0mA
0.90
...'"
~
4.0 V
8.0
12
16
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
5
"9>.
~
5.0 V.
4.0
1.2
::l
1
//
250
FIGURE 5 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
:;;
6.0 V
V/
/J, V-
"'
Cjss
,\
\
\.
..........
rss·.....
r-
Coss
C
5.0
10
15
10. DRAIN CURRENT (AMPS)
20
25
0
10
20
30
40
VOS. DRAIN·TO-SOURCE VOLTAGE (VOLTS)
MOTOROLA TMOS POWER MOSFET DATA
C-204
50
MTM15N35, 40
SAFE OPERATING AREA INFORMATION
FIGURE 9 - MAXIMUM RATED FORWARD BIASED
SAFE OPERATING AREA
FIGURE 10 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
80
100
-
-
-
10 1'$
70
r.-
in
1001'$
~ 60
5-
1.0 m.
~
r-
-
_Typical rOS(on) Limil
- - -Package limit
Thermal limit
2.0
0
0
z
~ 30
dc
c
TJ<;;1500C
S2 0
TC - 25°C
r- VGS - 20 V. Singl. Puis.
1
0'1.0
~
a
10 ms
MTM15N35
MTMI5N40
-
4.0 8.010
20
40
80100 200
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
MTMI5N35MTMI5140
0
400
00
1000
Po
RruC
r(tl
FORWARD BIASED SAFE OPERATING AREA
The dc data of Figure 9 is based on a case temperature
(TCI of 250C and a maximum junction temperature
(TJmaxl of 150°. The actual junction temperature depends on the power dissipated in the device and its case
temperature. For various pulse widths, duty cycles, and
case temperatures, the peak allowable drain current
(loMI may be calculated with the aid of the following
equation:
100
200
300
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTSI
400
rated power dissipation at TC = 25°C.
rated steady state thermal resistance.
normalized thermal response from
Figure 11.
SWITCHING SAFE OPERATING AREA
IO(250CI[TJ(maXI - TC]
Po . RruC . r(tl
where
IO(25°CI = the dc drain current at TC = 25°C from
Figure 9.
TJ(maxl= rated maximum junction temperature.
device case temperature.
TC
The switching safe operating area (SOAI of Figure 10
is the boundary that the load line may traverse without
incurring damage to the MOSFET. The fundamental
limits are the peak current, 10M and the breakdown
voltage, V(BRIOSS' The switching SOA shown in Figure
10 is applicable for both turn-on and turn,off of the
devices for switching times less than one microsecond.
The power averaged over a complete switching cycle
must be less than:
TJ(maxl - TC
RruC
THERMAL RESPONSE
FIGURE 11 - MTM15N35/MTM15N40
1. 0
5
~ t:::
~
~
-
D Curves ApplV for Power
Pulse Train Shown
t::= ? "
Read Time at tl
TJ(pk) - TC = P(pkl RBJC(11
f-:~
0-.1
I
0.1
RBJC(II = r(11 RBJC
RBJC - 0.5°C/W Max
0" .2
2
0.0 I
0-.5
tJUl
Single Pulse
III
I
III
I
1.0
1:~~
~UTY
100
10
1. TIME IMS}
MOTOROLA TMOS POWER MOSFET DATA
C-205
CYCLE. 0" 11/12
1000
10000
®
MTM1SN45
MTM15N50
MOTOROLA
Designer's Data Sheet
15 AMPERE
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
N-CHANNEL TMOS
POWER FET
These TMOS Power FETs are designed for high voltage. high
speed power switching applications such as line operated switching
regulators. converters. and motor controls.
• Silicon Gate for Fast Switching Speeds Specified at lOQ·C
ro5(on) = 0.4 OHM
450 and 500 VOLTS
Switching Times
• Designer's Data - lOSS, VDS(on) and SOA Specified at
Elevated Temperature
• Rugged -
SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With
Inductive Loads
• Low Drive Requirement, VG(th) = 4.5 Volts (max)
,r
MTM15N45
MTM15N50
TMOS
S
L
A-----<
~
te·
MAXIMUM RATINGS
Rating
IF
Symbol
Drain·Source Voltage
Drain-Gate Voltage
(RGS = 1.0 MO)
Gate-Source Voltage
VGS
MTM15N45 MTM15N50
Unit
VOSS
450
500
Vdc
VOGO
450
500
Vdc
K
SEATING
'LANE
0
,
Vdc
±20
Adc
Drain Current
Continuous
Pulsed
Gate Current - Pulsed
Total Power
Dissipation @ TC; 25·C
Derate above 25·C
Operating and Storage
10
10M
15
65
IGM
t.5
Adc
TJ. Tstg
250
2.0
W/·C
-65 to 150
·C
Temperature Range
THERMAL CHARACTERISTICS
Thermal Resistance
R8JC
0.5
·C/W
TL
275
·C
Junction 10 Case
Maximum Lead Temp. for
Soldering Purposes. 1/8"
from case for 5 seconds
STYLE 1:
PIN 1. GATE
2. SOURCE
CASE. DRAIN
Watts
Po
Designer's Data for "Worst Case" Conditions
The Designer's Data Sheet permits the design of most circuits entirelyfrom
the information presented. Limit curves-representing boundaries on device
characteristics-are given to facilitate "worst case" design.
MOTOROLA TMOS POWER MOSFET DATA
C-206
IL IMETERS
OIM MIN MAX
A
38.35 39.31
B 19.30 21.08
C
6.35 1.12
0
1.45
1.60
E
3.43
F 29.90 30.40
-
6
H
10.61
5.1
K
11.18
R
4-
c
INCHES
MIN MAX
1.510 1.550
0.160 0.830
0.250
0.051 0.083
0.135
1.111 1.191
11.18 0.420 0.440
O.
5.
5
1 1
12.19 0.440 0.480
4.09 0.1&1 o.lBl
28.61 0.910 1.0&0
-
CASE 197·01
TO·204AE (TYPE)
(T()-3 TYPE)
MTM15N45, 50
I
ELECTRICAL CHARACTERISTICS ITC = 25°C unless otherwise noted)
I
Characteristic
Symbol
Min
Max
450
-
Unit
OFF CHARACTERISTICS
Orain-Source Breakdown Voltage
IVGS = 0, 10 = 5.0 mAl
VIBR)OSS
MTM15N45
MTM15N50
500
Zero Gate Voltage Orain Current
IVoS = 0.85 Rated VOSS, VGS = 0)
TJ=l00°C
loSS
Gate-Body Leakage Current
IVGS = 20 Vdc, VOS = 0)
IGSS
-
Vdc
.
mAdc
0.25
2.5
500
nAdc
ON CHARACTERISTICS'
Gate Threshold Voltage
110 = 1.0 mA, VOS = VGS)
TJ = 100°C
VGSlth)
Orain-Source On-Voltage IVGS = 10 V)
(10= 7.5 Adc)
110= 15 Adc)
110 = 7.5 Adc, TJ = 100°C)
VOSlon)
Static Drain-Source On-Resistance
IVGS =.10 Vdc, 10 = 7.5 Adc)
Forward Transconductance
IVOS = 15 V,IO = 7.5 A)
Vdc
2.0
1.5
4.5
4.0
3,0
rOSlon)
-
0.4
Ohms
9fs
4.0
-
mhos
-
Vdc
7.5
6.0
SAFE OPERATING AREAS
Forward Biased Safe Operating Area
See Figure 9
Switching Safe Operating Area
See Figure 10
OYNAMIC CHARACTERISTICS
Input Capacitance
I-0::-=-ut",p.;;uc...t-":ca;;'p"'a:..:c;,;it.:.an.;;c:::e_-:-_ _-l IVos = 25 V, VGS = 0, f = 1.0 MHz) I-_'::'!"~_+____-I-__~:-_-I-_-"=-_-I
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS' ITJ = 100°C)
Turn-On Oelay Time
Rise Time
Turn-Off Oelay Time
120
ns
300
ns
tdlolt)
-
400
ns
tf
-
240
ns
IVos = 125 V, 10 = 7.5 A,
Ic:Ilonl
tr
Rgen = 50 ohms)
Fall Time
SOURCE DRAIN DIODE CHARACTERISTICS'
Characteristic
Forward On-Voltage
Forward Turn-On Time
Reverse Recovery Time
I
I
I
Symbol
TVp
Unit
IS= 15A
VSO
1.5
Vdc
VGS=O
ton
175
ns
trr
600
ns
·Pulse Test: Pulse Width :E;;300 ~s. Duty Cycle ~2%.
RESISTIVE SWITCHING
FIGURE 2 - SWITCHING WAVEFORMS
fiGURE 1 - SWITCHING TEST CIRCUIT
tdlon)
Output, Vout
Inverted
MOTOROLA TMOS POWER MOSFET DATA
C-207
MTM15N45, 50
TYPICAL CHARACTERISTICS
FIGURE 3 - OUTPUT CHARACTERISTICS
25
t-
~
~
5-
Tl=25o~-
VGS=20V
10 V
20
FIGURE 4 - ON-REGION CHARACTERISTICS
25
15
~
I..,
,
::::>
10
~
a::
IIh
10
~
a:
co
5.0
.Ii? 5.0
co
v
.Ii? 5.0
4.01V
0
0
100
50
150
j
5.0 V
4.~ V
.
..,.!:l'"
..
25
"""'"
:;;.
"'"
to
1.0
VOS'= VGS
10 = 1.0 mA
~
5-
'"'"
0.90
.1_1
f-- Ves = 20 V
TJ
ia
~
z
I'-...
~
0'"
~
i'-...
'" O.BO
!;;:
-50
-25
25
50
75
100
15
1
10
I
co
125
150
h
~W
o
o
2.0
FIGURE 7 - ON-RESISTANCE versus
DRAIN CURRENT
5!.
~ 0.4
TJ = 100°C
iii
I--
25°C
~
!;!
0.3
is
"1
f;
0.2
-- - -
-55°C
!
0
o
4000
..... /
10
15
100°C
II
'I
6.0
B.O
10
-
20
25
10. DRAIN CURRENT (AMPS)
"'
,\
o \
100o
TJ = 25°C
VGS = 0
f= 1.0 MHz
\
0
0
5.0
r
i
FIGURE 8 - CAPACITANCE VARIATION
co 0.1
J
4.0
/
/ /
5000
/
1li:
20
VGS. GATE·TO-SOURCE VOLTAGE (VOLTS)
TJ. JUNCTION TEMPERATURE (oC)
;;; 0.5
J
/
.Ii? 5.0
......,
........
10.70
I
25°C .....,
to
,.
= -55°C_
20
::;;
"'-.....
9
ili
16
FIGURE 6 - TRANSFER CHARACTERISTICS
1.2
1.1
12
VOS. ORAIN-TO·SOURCE VOLTAGE (VOLTS)
FIGURE 5 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE (NORMALIZED)
~
il!
B.O
4.0
Vos ORAIN·TO·SOURCE VOLTAGE (VOLTS)
8
6.0 v
W. . . .
~
IF
250
200
7.0 V
/#
15
0-
a::
a
/,~
~
5-
6.0 V
Tl=25o~-
VA'
!~ ~VGS=10V
;;; 20
7.0 V
0-
VGS=20V~
\
Ciss
\.
\.
Cras-
........
--
Coss
10
20
30
40
VOS. ORAIN·TO-SOURCE VOLTAGE (VOLTS)
MOTOROLA TMOS POWER MOSFET DATA
C-208
50
MTM15N45. 50
SAFE OPERATING AREA INFORMATION
FIGURE 10 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
FIGURE 9 - MAXIMUM RATED FORWARD BIAS
SAFE OPERATING AREA
100
100
101"
- f--
f"
::;;
I-
:5- 10
..
90
-1001'~~
-
l'. .0 m.
80
in
"::;;
10 m. ~
70
:5-
I-
I-
!!1
'"
'"
Z
:0
r-- r-- ~ 1.0
E~
Q
.!?
f=
r-0.1
1.0
!!1
'"
'"z
de
Package limit
Thermal limit
TC = 25°C
VGS = 20 V. Singl. Pulse 10
40
~
30
Q
.!?
~
MTMI5N50
,
-TJ ';150 0 C
"
20
MTMI5N45
MTMI5N45
MTMI5N50
100
...
50
:0
- - - - 'OS(on} Limit
- -
60
10
1000
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS)
o
o
100
200
300
1-
400
500
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS)
FORWARD BIASED SAFE OPERATING AREA
SWITCHING SAFE OPERATING AREA
The dc data of Figure 9 is based on a case temperature
(TCI of 25°C and a maximum junction temperature
(TJmax) of 150°. The actual junction temperature depends on the power dissipated in the device and its case
temperature. For various pulse widths, duty cycles, and
case temperatures, the peak allowable drain current
(10M) may be calculated with the aid of the following
equation:
The switching safe operating area (SOA) of Figure 10
is the boundary that the load line may traverse without
incurring damage to the MOSFET. The fundamental
limits are the peak current, 10M and the breakdown
voltage, V(BR)OSS. The switching SOA shown in Figure
10 is applicable for both turn-on and turn-off of the
devices for switching times less than one microsecond.
The power averaged over a complete switching cycle
must be less than:
IO(250C) [TJ(maXI - TC]
Po . RruC . r(t)
TJ(maxl - TC
RIiJC
where
IO(25°C) = the dc drain current at TC = 25°C from
Figure 9.
TJ(max) = rated maximum junction temperature.
device case temperature.
TC
rated power dissipation at TC = 25°C.
Po
rated steady state thermal resistance.
RruC
r(t)
normalized thermal response from
Figure 11.
MOTOROLA TMOS POWER MOSFET DATA
C-209
MTM15N45, 50
FIGURE 11 - MTM1SN4S/MTM1SNSO
1.0
5
= f=
O' .5
L ..
'-
O' .2
2
O' .1
1
ReJcltl- rlt) ROJC
ReJC • D.5.CIW Max
O CURVES APPLY FDVOWER
PULSE TRAIN. SHOWN
READ TIME AliI
TJlpki - TC' Plpkl ReJcllI
Plpkl
;::::: p-
tJUl
5
i-"""
-I---"
0.0 1
0.1
Single Pulse
~~~
III
ill
1.0
DUTY CYCLE, D• '1/12
100
10
I,
TIME IMSI
TMOS POWER FET CONSIDERATIONS
Switching Speed - The switching speeds of these devices are
dependent on the driving impedance. Extremely fast switching
speeds can be attained by driving the gate from a voltage source.
Transfer Characteristics - The transfer characteristics afe
linear at drain currents of 2.5 Amps. (See Figure 6.) Linear amplifiers with high frequency response can be designed using this
product:
Gate Voltage Rating - Never exceed the gate voltage rating
of ±20 V. Exceeding the rated VGS can result in permanent
damage to the oxide layer in the gate region.
Gate Termination - The gate of these devices are essentially
capacitors. Circuits that leave the gate open-circuited or floating
should be avoided. These conditions can result in turn-on of the
devices due to vortage build-up on the input capacitor due to
leakage currents or pickup.
Gate Protection - These devices do not have an internal
monolithic zener diode from gate to source. The addition of an
internal zener diode may result in detrimental. effects on the
reliability of a power MOSFET. If gate protection is required, an
external zener diode is recommended.
Handling and Packaging - MOS les are susceptible to damage
from electrostatic charge. Experience has shown that these
devices are more rugged than MOS ICs. This is primarily due
to the comparatively larger capacitances associated with
power devices, however, reasonable precautions in handling
and packaging MOS devices should be observed.
MOTOROLA TMOS POWER MOSFET DATA
C-210
1000
10000
®
MTM20N08
MTM20N10
MTM2SNOS
MTM2SN06
MOTOROLA
Designer's Data Sheet
MTP20N08
MTP20N10
MTP2SNOS
MTP2SN06
20 and 25 AMPERE
N-CHANNEL TMOS
POWER FETs
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
rOS(on) = 0.15 OHM
SO and 100 VOLTS
rOS(on) = O.OS OHM
50 and 60 VOLTS
These TMOS Power FETs are designed for low voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds - Switching Times
Specified at 100°C
MTM25N05
MTM25N06
MTM20NOS
MTM20Nl0
• Designer's Data -lOSS, VDS(on), VGS(th) and SOA
Specified at Elevated Temperature
• Rugged - SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
Loads
1r
E
R
tG j
S
PIN I. GATE
2.S0UACE
CASE DRAIN
S
25N05
MTM orMTP
25N06 20NOS
20Nl0
Unit
100
Vdc
Drain-Gate Voltage
(RGS = 1.0 MOl
VOGR
50
60
80
100
Vdc
±20
VGS
Vdc
Adc
Pulsed
i
STYLE:!:
80
Gate Current -
f~
- - .--'k-.--' . --- _ .
'..'j-1
I
v
-.'
ilf----
U
60
Total Power
i
.J
GO--~
50
10
10M
K
_.
1
vOSS
Gate-Source Voltage
•
!.
Q
Drain-Source Voltage
. Drain Current
Continuous
Pulsed
_
~- F
MAXIMUM RATINGS
Symbol
-0
SEATING PLANE
TMOS
Rating
r:::C-~4 l c
L~I
~ ~I--t--f
T--1-00
25
80
20
60
IGM
1.5
Adc
Po
100
Watts
0.8
W/OC
TJ. Tstg
-65 to 150
°C
CASE 1-04
TO-204AA
(TO-3 TYPE)
MTP25N05
MTP25N06
MTP20NOS
MTP20Nl0
Oissipation @ TC = 25°C
Derate abo\'e 25°C
Operating and Storage
Temperature Range
NOTES:
1. DIMENSION H AI'PLIESTOALl lEADS
2. DIMENSfONLAI'PlI£SrGLEADS 1 AND 3 OIfLY,
3.DIMENSlONt.DEFINESAZONEWIIEIIEALL
BGO'fANO LEAD IRREGULARITIES ARE
ALLOWED.
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Maximum Lead Temp. for
Soldering Purposes, liS"
from case for 5 seconds
4. DIMENSIONING Afl:D TOLERANCING PER ANSI
ROJC
1.25
°C/W
TL
275
°C
Y1U1913.
5. CDNTIIOlLiNG DlMENSIGN: INCH.
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
Designer's Data for "Worst Case" Conditions
The Designer's Data Sheet permits the design of most circuits entirely from the
information presented. Limit data - representing device characteristics boundaries - are
given to facilitate "worst case" design.
CASE 221A-02
TO·220AB
MOTOROLA TMOS POWER MOSFET DATA
C-211
MTM/MTP20N08, 10/25N05, 06
I
i:LlicTRicAL' CHARACTERIST,ICS (TC" 25°C unless otherwise noted)
I
Characteristic
Symbol
Min
Max
50
60
SO
100
-
-
0.25
2.5
Unit
OFF CHARACTERISTICS
Orain.-Source Breakdowr Voltal1"
(VGS =.0, 10 = 5.0 mAl
V(BR)OSS
MTM25N05/MTP25N05
. MTM25N06/MTP25N06
MTM20NOS/MTP20NOS
MTM20N 10/MTP20N 10
Zero Gate Voltage Orain Current
(VOS = 0.S5 .Rated VOSS, VGS = 0)
TC=100oC
lOSS
Gate-Body Leakage Current
(VGS = 20 Vdc, VOS = 0)
IGSS
.;
-
Vdc
mAdc
500
nAdc
ON CHARACTERISTICS'
Gate Threshold Voltage
(10 = 1.0 mA. VOS = VGS)
TJ = 100°C
Static Drain-Source On-Resistance
(VGS = 10 Vdc, 10 = 12.5 Adc)
(VGS= 10Vdc,10= 10Adc)
2.0
1.5
rOS(on)
MTM25N05/MTP25N05
MTM25N06/MTP25N06
MTM20NOS/MTP20NOS
MTM20Nl0/MTP20Nl0
Orain-Source On-Voltage (VGS = 10 V)
MTM25N05/MTP25N05
(10 = 25 Adc
MTM25N06/MTP25N06
(10 = 12.5 Adc, TJ = 100°C)
MTM25N05/MTP25N05
MTM25N06/MTP25N06
(10 = 20 Adc)
MTM20NOS/MTP20NOB
MTM20Nl0/MTP20Nl0
MTM20NOB/MTP20NOB
(10 = 10 Adc, TC = 100°C)
MTM20N 10/MTP20N 10
Forward Transconductance
(V"S = 15 V, 10 = 12.5 A)
Vdc
VGS(th)
VOS(on)
(VOS= 10V,10= lOA)
Ohm
-
O.OS
-
0.15
-
2.4
Vdc
-
2.0
-
3.6.
-
3.Q
6.0
-
6.0
-
-
1400
mhos
9fs
MTM25N05/MTP25N05
MTM25N06/MTP25N06
MTM20NOB/MTP20NOS
MTM20Nl0/MTP20Nl0
4.5
4.0
DYNAMIC CHARACTERISTICS
Input Capacitance
Ciss
(VOS = 25 V, VGS = 0,
f = 1.0 MHz)
Output Capecita nce
erss
-
td(onl
tr
-
450
td(ofl)
-
200
Coss
Reverse Transfer Capacitance
pF
1200
400
SWITCHING CHARACTERISTICS' (TJ = 100°C)
Turn-On Oelay Time
(VOS = 25 V, 10 = 0.5 Rated 10)
Rise Time
Rgen = 50 ohms)
Turn-Off Oelay Time
Fall Time
tf
50
ns
100
SOURCE DRAIN DIODE CHARACTERISTICS'
Symbol
Typ
Unit
IS - Rated 10
VSO
2.0(1)
Vdc
VGS=O
ton
50
ns
trr
300
ns
Characteristic
Forward Turn-On Time
I
I
Reverse Recowry Time
I
Forward On-Voltage
·Pulse Test: Pulse Width
~300
",s, Duty Cycle
~2%.
(1) Add 0.5 V for MTM/MTP25N05 and MTM/MTP25N06.
MOTOROLA TMOS POWER MOSFET DATA
C-212
MTM/MTP20N08. 10/25N05. 06
TYPICAL CHARACTERISTICS
MTM25N05. MTM25N06. MTP25N05. MTP25N06
MTM20N08.MTM20N10.MTP20N08.MTP20N10
FIGURE 1 - ON· REGION CHARACTERISTICS
20
/
VGS = 20 V /
I
~ 16
V
:;
12
g§
II
;'l
~ 8.0
II-
13
c
~
0
II
«
I/'
=>
~ 10
~
6.0 V
Q
E5.0
TJ = 25°C
5.0 V
U!/
If
10
0
I VI
I//-
0
4.0
6.0
8.0
L
25°C
100°C
~l /
VOS=10V
WI
/;il
8.0
2.0
10
, /VJ
k::::: ~ V
4.0
6.0
--
~ 0.1
:z:
- --
TJ = 100°C
25°C
1
e
TJ = OooC
~ 0.0 8
~
25°C
!<2
'"
~
0.0 6
55°C
w
I--
.
6 0.04
....
-
z
;;:
~ 0.0 2
~
co
5
8.0
r-
~
=>
co
.1 55oC
4.0
10
FIGURE 6 - ON· RESISTANCE versus
DRAIN CURRENT
5
5
8.0
VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)
FIGURE 5 - ON· RESISTANCE versus
DRAIN CURRENT
VGS=10V
/
I
i.J
VI
0
VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)
2
10
IV-- 100°C
5
l---:::: I-'l'
2.0
E.O
TJ = -55°C
0
.4
VII
/. 'I
V IV
0
4.0
FIGURE 4 - TRANSFER CHARACTERISTICS
TJ = -55°C
2
2.0
5
--II I
25°C
+L
VOS=10V
5.0 V
VOS. ORAIN·TO.sOURCE VOLTAGE (VOLTS)
FIGURE 3 - TRANSFER CHARACTERISTICS
6
TJ = 25°C
6.0 V
l
V-
6.0
8.0
2.0
4.0
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS)
0
•
7.0 V
//
g§
//
8.0 V
1//
'/ /
;::1
5
:z
7.0 V
lIT
0
VGS = 20 V VGS - 1O.J--
:;
IW
/4 v
- 4.0
8.0 V
10 V
V
I
/ IV
/ II
~
!2
FIGURE 2 - ON· REGION CHARACTERISTICS
5
12
16
20
~
0
VGS = 10 V
5.0
10
15
10. DRAIN CURRENT (AMPSI
10. DRAIN CURRENT (AMPS)
MOTOROLA TMOS POWER MOSFET DATA
C-213
20
25
MTM/MTP20N08, 10/25N05, 06
TYPICAL CHARACTERISTICS
FIGURE 7 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
ffi
~
Ic
II
FIGURE 8 - CAPACITANCE VARIATION
200
1.2
"""
1.1
:!.
~
~
~
""" """
1.0
§;
9
~ 0.90
lI!
i=
..'"
~
0.80
VOS" VGS
10 " 1.0 mA
160
0\
""" '"
0 1\
~
:--..
25
50
100
75
:-- ~~
'"
0
150
Ciss
\.
40 0
125
'\
""" ~
.........
-25
TJ=~;±VGS
=0
f= 1.0 MHz
\.
'\
0
........ b"
~ 0.70-50
>
o \
Crss
10
TJ. JUNCTION TEMPERATURE 1°C)
20
30
40
VOS. ORAIN-TO-SOURCE VOLTAGE IVOLTSI
50
THERMAL RESPONSE
FIGURE 9 - MTM20N08/MTM20N10
MTM25N05/MTM25N06
1.0
~
wz
~ ~
~~
t::: ~
0·0.5
0.5
U
0.3
0.2
O.t
w~
0""
~ ~ 0.1
::;w
,,>--
PIPFf1{l
~-~.~
a: I- 0.0 5
~~
~"!"
~.qt.
I-:g ~ 0.0
~
:= 0.0 2~ ........
0.0 t
O.Ot
0.02
frrmr
0.05
ReJcltl = rltl ReJC
ReJC = 1.25°C/W Max
;;;;.--
0.02
3-:...---
",,"
--
--
>---
0.05
r-;;;;.. ~
O.t
== 1==
F=
~ t.=
Duty Cycle. D= 1j It2 -
-
o Curves Apply for Power
Pulse Train Shown
Read Time at tl
TJlpkl - TC· = Plpkl ReJcltl
0.2
0.5
t.O
5.0
1.0
IIII
10
II IIII
50
10
I
I
I I II
100
200
1000
500
t, TIME (ms)
~
N
FIGURE 10 - MTP20N08/MTP20N10
MTP25N05/MTP25N06
1.0
~
O. 1
~ '0. 5
o
:!; O. 3
'-'
:i
to
;;;
~
o • 0.5
0.1
<
">--
I-
0.03
ffi
0.02
~ 0.0 5
z
~
>--
-
I--:
r- -=-'"
~
O. 1
0.0 H-- 0.05
;;;
-
0.2
O. 2
r-
f-=' ~ - I-S'jGjEfilil
i-"""
0.01""'0.01
0.02
0.05
0.1
tJUl
-r-~~
.....
0.02
Plpk)
IIIII
10
0.5
I
I
20
I, TIME (ms)
MOTOROLA TMOS POWER MOSFET DATA
C-214
Pulse Train Shown
Read Time at t1
TJlpkl- TC = Plpkl ReJc111
Duty Cycle. D= 11/12
0.2
ReJcltl = rltl ReJC
ReJC = 1.25°C/W Max
D Curves Apply for Power
I
I I IIIII
100
50
I
I
200
I
I I I II
500
1.0k
MTM/MTP20N08, 10/25N05, 06
OPERATING AREA INFORMATION
FIGURE 11 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
FORWARD BIASED SAFE OPERATING AREA
The de data of Figures 11 and 12 is based on a case temperature (TC) of 25°C and a maximum junction temperature (TJmax)
of 150o C_ The actualjunction teroperaturedependson the power
10-l's
0
1001's
1.0ms
- /-;
dissipated in
~
/
0
~he
device and its case temperature. For various
pulse widths. duty cycles. and case iemperatures. the peak
allowable drain current (10M) may be calculated with the aid of
the following equation:
r-!0 ms
de
rOS(on) limit
Package limit
Thermal li~ill
VGS;20V
Single Pulse
TC; 25°C
-
10M
IIIII
i+MTrlMnOm
10
100
VOS. ORAIN-TO-SOURCE VOLTAGE (VOLTS)
FIGURE 12 - MAXIMUM FORWARD BIAS
SAFE OPERATING AREA
80
The switching safe operating area (SOA) of Figure 13. is the
boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the peak
current. 10M and the breakdown voltage. V(BRjOSS' The switching SOA shown in Figure 12 is applicable for both turn-on and
turn-off of the devices for switching times less than one microsecond.
The power averaged over a complete switching cycle must be
less than:
1001's
1.0ms
-
10 ms
r-7'- .-
1'-.
~e " "-
0
rOS(on) limit
Package limit
Thermal limit
TJmax - Te
ReJC
I IIII
TC ; 25°C
VGS;20V
MTM/MTP25N05
I IIII
Singl!' PU)I"I
I. 0 1.0
MTMjMT~2JN~ci
10
60
VOS. ORAIN-TO-SOURCE VOLTAGE (VOLTS)
FIGURE 13 - MAXIMUM SWITCHING
SAFE OPERATING AREA
100
~8 0
~
5
MTMlMTP25N05 -
~
MTM/MTP25N06 -
i'l
MTM/MTP20N08
;;:
MTM/MTP20Nl0
!2 60
a:
z 40
~
Eo
~
20
TJ";; 150°C
20
TJmax-TC ]
ReJc' ret)
SWITCHING SAFE OPERATING AREA
10 I'S
I----.
rLPo'
Where
10 (25°C) ;dcdraincurrentatTc; 25°C from Figuresll or 12
TJmax ::: Rated maximum junction temperature
TC
= Device case temperature
Po
; Rated power dissipation at TC ; 25°C
R8JC
; Rated steady state thermal resistance
ret)
; Normalized thermal response from Figures 9
and 10.
r- MTM/MTP20N08
111111
I. 0 1.0
; IO(25°C)
40
60
80
100
VOS. ORAIN-TO-SOURCE VOLTAGE (VOLTS)
MOTOROLA TMOS POWER MOSFET DATA
C-215
•
MTM2SN08
MTM2SNIO
MTM3SNOS
MTM3SN06
•
®
MOTOROLA
Designer's Data Sheet
26 and 35 AMPERE
N-CHANNELTMOS
POWER FETs
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
rOS(on) = 0.075 OHM
ao and 100 VOLTS
These TMOS Power FETs are designed for low voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds Specified at 100°C
rDS(on)
Switching Times
• Designer's Data - IDSS, VDS(on), VGS(th) and SOA
Specified at Elevated Temperature
• Rugged -
MTM35N06
MTM35NOS
MTM25NOS
MTM25N10
SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
Loads
1r
= 0.056 OHM
50 and 60 VOLTS
Go--~
TMOS
S
MAXIMUM RATINGS
Rating
Symbol
36N06
MTM
36NOS 26NOa
26N10
Drain-Source Voltage
VOSS
50
60
SO
100
Drain-Gate Voltage
IRGS = 1.0 MO)
VOGR
50
60
SO
100
Unit
Vdc
Vdc
Vdc
±20
Gate-Source. Voltage
VGS
Drain Current
Continuous
Pulsed
10
10M
Gate Current - Pulsed
IGM
1.5
Po
150
Watts
1.2
W/DC
-65 to 150
°c
Adc
Total Power
Dissipation @ TC = 25 DC
Derate above 25 DC
Operating and Storage
Temperature Range
TJ. Tstg
35
150
25
126
Adc
PIN 1. GATE
2. SOURCE
CASE. DRAIN
NOTES:
1. DIMENSIONS 0 AND U ARE DATUMS
AND
IS BOTH A DATUM AND
SEATING PLANE. ,
2. posmONAL TOLERANCE FOR HOLE 0:
It :1
2sdc
i
!!i
10
;!
'"
~
~
c:>
4.0
6.0
8.0
VGS. GATE·rO·SOURCE VOLTAGE (VOLTS)
I--vris= IJV
!:a
TJ = 100°C
S
in
"
~ 0.10
r--- vris = Id V
~ 0.12
/
FIGURE 6 - ON-RESISTANCE versus
DRAIN CURRENT
FIGURE 6 - ON-RESISTANCE ve,sus
DRAIN CURRENT
§
/
/
/ '/
///
20
o
10
/
7 /
7 iA
100°C
10
........-:: ~ V
o
10
/
2S"C_
40
~ 30
~
7
I
z
:1/
/
TJ = -55'e
50
~
41
:!
o
8.0 V
FIGURE 4 - TRANSFER CHARACTERISTICS
60
...'"
B
9.0I V_ I---
5.0 V - r---
o
10
I I /
W 1/
25°C I-I-J /
!;;; 30
..-
Ii.
TJ = -55°C
~ 40
I
10 V
u
o
FIGURE 3 - TRANSFER CHARACTERISTICS
50
./
V
Jrb
5.0V-
o
VGS=12V
./
W~ /""
6.0V-
./
I
J
V
u;
o
!?
10
20
30
ID. DRAIN CURRENT (AMPS)
40
50
0
o
10
MOTOROLA TMOS POWER MOSFET DATA
C-218
20
30
10. DRAIN CURRENT (AMPS)
40
50
MTM25N08, 10/35N05, 06
TYPICAL CHARACTERISTICS
FIGURE 7 - GATE THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
S
FIGURE 8 - CAPACITANCE VARIATION
5000
12
'"
-25
-50
25
\
~\
~
;5
o
50
75
100
125
VGS' 0
1-1.0 MHz
..........
1\
1000
"""
•
TJ' 25°C
~ 3000
.~
i
I
I
I
Ciss
I"-
Coss
"'-
C:ss
o
o
150
50
10
20
30
40
VDS, DRAIN·TO·SOURCE VOLTAGE (VOLTS)
TJ. JUNCTION TEMPERATURE (OCI
THERMAL RESPONSE
FIGURE 9 - MTM25N08/MTM26N10
MTM35N05/MTM35N06
10
o7
~
«w
05
03
-;;..-
0.2
0.2
«
:;0'"
~
0
0.5
~
~.... Ei
~011
01
"':;0
1-0:00 7=005
-
,.--t:;;;::::'"
::5
z
~
~ 0.05
-002
:*
003
~
00
001
~~~
V
I-
00
002
01
02
0,
10
IIII1
20
5.0
10
t TIME (m"
I I
20
MOTOROLA TMOS POWER MOSFET DATA
C-219
ROJC(ti 0 r(11 ROJC
ROJC 0 0.83°C/W Max
o Curves Apply for Power
Pulse Train Shown
Read Time at tl
OUly Cycle, 0 0 IJ 112
St 9:e i"!'i I
005
P(pkl
r~
.... 0
u;
~
I-:: 10-
TJ(pkl - TC
I l Jl 1III
50
100
0
P(pkl ROJC(II
J L lullL
200
500
1.0 k
MTM25N08,10/35N05, 06
OPERATING AREA INFORMATION
FORWARD BIASED SAFE OPERATING AREA
FIGURE 10 - MAXIMUM RATED FORWARD BIASED
SAFE OPERATING AREA
100 r-
•
--
-- -
i... :: ..
--~
g§
~ 2.0 f-5>1.0
0.5
~~
de
10M
Thermal limit
~
f= ==
10 m•
.........
al 10
t=
==
1 OJ.ir.:
1.0 ms
----rOS(on) limit
a 5.0 ~ F=
t= • Package limit
1!E
1-- --1- .. - 1--1-
I"-
The de data of Figur~ 10 and 11 is based on a case temperature ITcI of 25°C and a maximum junction temperature (TJmax)
of 150°C. The actual junction temperature depends on the power
dissipated in the device and its case temperature. For various
pulse widths, duty cycles, and case temperatures, the peak
allowable drain 'current flaM) may be calculated with the aid of
the following equation:
10 Il'
E~GS=20V
Single Pul••
TC = 25°C
MTM25NOB
_~TMt2S~I~
0.2
2.0
4.0 6.0
10
20
40 60
Vos, ORAIN-TO-SOURCE VOLTAGE (VOLTS)
TJmax-TC]
= 10 (26OC) [ Po' R6JC . r(t)
Where
10 (25'C}=dc drain current at TC=25'C from Figures 10 or 11
TJmax = rated maximum junction temperature
TC
= device case temperature
Po
= rated power dissipation at TC = 25'C
RruC
= rated ateady state thermal resistance
r(t)
= normalized thermal response from Figure 9
100
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) of Figure 12, is the
boundary thatthe load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the peak
current,lOM and the breakdown voltage, V(BR)OSS· The switching SDA shown in Figure 12 is applicable for both turn-on and
turn~off of the devices for switching times less than one microsecond.
The power averaged over a complete switching cycle must be
less than:
FIGURE 11 - MAXIMUM RATED FORWARD BIASED
SAFE OPERATING AREA
200
.
100
-
- --
-
0
........
0
of
----rOS(on) limit
..
Package Limit
~
f---Thermal limit
EO
f=
f:= I-
O. 2
1.0
TJ(max) - TC
R6JC
MTM3SNOS
VGS=20V
Single Pulse
TC = 25°C
2.0
10ms
de
0
O. S F
100 IlS
1.0 ms
0
0
10 Il'
- 1---1--
MTM3SN06
4.0 6.0
10
20
40
VOs. ORAIN-TO-SOURCE VOLTAGE (VOLTS)
60
100
FIGURE 12 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
160
140
in
~ 120
!2
~
::I
....
~
100
MTM3SNOS_
MTM3SN06_
MTM25N08
80
80
MT~2SN10
Q
-
5>40
20
TJ'" 150°C
40
M
M
VOs. DRAIN-TO-SOURCE VOLTAGE (VOLTS)
~
1M
MOTOROLA TMOS POWER MOSFETDATA
C-220
®
MTM40N18
MTM40N20
MTM45N12
MTM45N15
MOTOROLA
Designer's Data Sheet
40 and 45 AMPERE
N-CHANNEL TMOS
POWER FETs
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
'DSlon) = 0.08 OHM
180 and 200 VOLTS
These TMOS Power FETs are designed for low voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds Specified at 100·C
=
'DSlon)
0.06 OHM
120 and 150 VOLTS
Switching Times
• Designer'S Data - lOSS, VDS(on), VGS(th) and SOA
Specified at Elevated Temperature
MTM.oN18
MTM.oN20
MTM45N12
MTM45N15
• Rugged - SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
Loads
1r
Go--~
TMDS
S
MAXIMUM RATINGS
MTM
Rating
Symbol
45N12
45N15
.oN18
.oN20
Drain-Source Voltage
VOSS
120
150
laO
200
Vdc
Drain-Gate Voltage
(RGS = 1.0 MO)
VOGR
120
150
laO
200
Vdc
Gate-Source Voltage
±20
VGS
Vdc
Drain Current
Adc
Continuous
45
225
10
10M
Pulsed
Gate Current -
Unit
Pulsed
Total Power
Dissipation @ TC = 25"(;
Derate above 25·C
Operating and Storage
Temperature Range
40
200
Adc
1.5
IGM
Po
Watts
250
1.43
WfC
-65 to 150
·C
RruC
0.7
·CIW
Tl
275
·C
TJ,Tstg
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
Maximum lead Temp. for
Soldering Purposes, 118"
from case for 5 seconds
Designer's Data for "Worst Cas." Conditions
The Designer's Data Sheet permits the design of most circuits entirelv from the
information presented. Limit data - representing device characteristics boundaries
- are given to facilitate "worst case" design.
MOTOROLA TMOS POWER MOSFET DATA
C-221
STYLE 2:
PIN 1. GATE
2. SOURCE
CASE. DRAIN
MILLIMETERS
DIM MIN MAX
A 38.36 39.37
B 19.30 21.08
C
6.36 7.62
II
1.46
1.60
3.43
E
F 29.90 30.40
G 10.67 11.18
H
5.lZ
U
16.84 17.15
K 11.18 12.19
.84 4II
R ·24.89 28.91
-
INCHES
MIN
MAX
1.510
0.760
0.260
0.057
1.177
0.420
0.2oti
0.666
0.440
.151
0.880
CASE 197-01
TO-2D4AE
(TO-3 TYPE)
I
1.191
0.440
0.226
0.676
0.490
0.1 I
1.11&0
MTM40N18,20/45N12,15
I
ELECTRICAL CHARACTERISTICS (TC
= 25·C unless otherwise noted)
Symbol
Characteristic
Min
Max
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS =0,10 ,= 5.0 mAl
.
II
VBR(OSS)
MTM45N12
MTM45N15
MTM40N18
MTM40N20
120
150
180
200 '
Ze,o G81e Voltage Drain Current
(VOSS = 0.85 Rated VOSS, VGS = 0)
TC = 100"C
lOSS
Gate-Body Leakage Current
(VGS = 20 Vdc, VOS = 0)
IGSS
-
-
Vdc
mAdc
0.25
2.5
500
nAdc
ON CHARACTERISTICS·
Gate Threshold Voltage
(to = 1.0 mA, VOS = VGS)
TJ=100·C
Static Drain-Source On-Resistance
(VGS = 10 Vdc, 10 = 22.5 Adc)
(VGS = 10 Vdc, 10 = 20 Adc)
2.0
1.5
rOS(on)
-
MTM45N 12/MTM45N 15
MTM40N 181MTM40N20
-
Drain-Source On-Voltage (VGS = 10 V)
MTM45N12/MTM45N15
(to = 45 Adc)
MTM45N12/MTM45N15
(to = 22.5 Adc, TJ = 100·C)
MTM40N18/MTM40N20
(to = 40 Adc)
MTM40N18/MTM40N20
(to = 20 Adc, TC = 100·C)
Forward Transconductance
(VOS = 15 V, 10 = 12.5 A)
(VOS = 15 V, 10 = 10 A)
Vdc
VGS(th)
VOS(on)
-
9ls
MTM45N12/MTM45N15
MTM40N181MTM40N20
10
10
4.5
4.0
Ohm
0.06
0.08
Vdc
3.24
2.70
3.80
3.20
-
mhos
-
DYNAMIC CHARACTERISTICS
Input Capacitance
Coss
-
erss
-
500
-
300
Ciss
(VOS = 25 V, VGS = 0
1= 1.0 MHz)
Output Capacitance
Reverse Transfer Capacitance
5500
pF
1500
SWITCHING CHARACTERISTICS' (TJ = 100·C)
Turn-On Delay Time
td(on)
(VOO = 25 V, 10 = 0.5 Rated 10,
Rgen = 50 ohms)
See Figures 1 and 2
Rise Time
Turn-Off Delay Time
t,
-
td(off)
Fall Time
tl
50
ns
150
150
SOURCE-DRAIN DIODE CHARACTERISTICS'
Characteristic
Forward On-Voltage
IS = Rated 10
VGS = 0
Forward Turn-On Time
Reverse Recovery Time
*Pulse Test: Pulse Width
'!5i
Symbol
Typ
Unit
VSO
1.0
Vdc
ton
150
ns
trr
200
ns
300 p.S, Duty Cycle,,;;; 2.0%.
RESISTIVE SWITCHING
FIGURE 1 -
SWITCHING TEST CIRCUIT
VO~~
FIGURE 2 -
\
SWITCHING WAVEFORMS
td(on)
R~out
OUT
Output, Vout
Inverted
500
MOTOROLA TMOS POWER MOSFET DATA
C-222
MTM40N18,20/45N12,15
TYPICAL CHARACTERISTICS
MTM45N12, MTM45N15
MTM40N18, MTM40N20
RGURE 3 - ON-REGION CHARACTERISTICS
100
~
TJ
/ //
1/ .-
.... SO
VGS
9.0 V
/ ./'
TJ = 25°C
~
B.OV
ISO
~
ffi
.,.
lib
:!!gs
I
~4O
~
.9
100
VGS = 2Q~ V'OV
BO
RGURE 4 - ON-REGION CHARACTERISTICS
7.0V
6.0 V
'"
.9
Z
~
o
"
o
I.'
"
5.0 V r-2.0
4.0
S.O
B.O
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS)
RGURE 5 - TRANSFER CHARACTERISTICS
50
I /
I 1/
VOS = 10V
TJ = -SSOC- ~L
25°C-
/
~ 0.07
§.
:i!
0.06
illZ
0.05
~.
I /
J
/
11.lf--10Il"C
~
~~I--+-_l_-~-r---t--HU~V-+---t-----Ir-~
Ij
OL-~-L__~~~~~~~
__L-~~~~
o
~
~
M
M
W
10
VGS. GATE-lO-SOURCE VOLTAGE (VOLTS)
FIGURE 7 - ON-RESISTANCE versus
DRAIN CURRENT
FIGURE 8 - ON-RESISTANCE versus
DRAIN CURRENT
u;
~ 0.1 2
lJ
', 01l"C
I!j
~
0.1 0
~
0.08
j
~
5SoC
VGS = 10V
TJ _"OOOC
2SOC
~
:::>
;
Z
0.06
55°C
~ 0.04
0.03
'"
'"~
10
10
.910r--r--r--r--r--b~Jjr~r_-r--r--r~
//
'"
!i~.l 0.04
~0.02
E?
0
--
2.0
4.0
6.0
8.0
Ves. ORAIN-lO-SOURCE VOLlAGE (VOLTS)
~
25°C
~
S.OV
~
2SOC r---f-. /
!iii 30 1--r---t--I--+---t-----I-t-1hf-+-----i---i
17 V
4.0
6.0
8.0
VGS. GATE·lO-SOURCE VOLTAGE (VOLTS)
VGS = IOV
S.OV
11"'
~ 40 1--r--'--t-----
c
10l"s
10ms
ie
::>
'"
u
200
MTM40N1B, MTM40N20
---1- T.Om~oo!Ls
225
~
The dc data of Figures 12 and 13 is based on a case
temperature (TC) cif 25°C and a maximum junction tem·
perature (TJmax) of 150°. The actual junction temper·
ature depends on the power dissipated in the device
and its case temperature. For various pulse widths, duty
cycles, and case temperatures, the peak allowable drain
current (10M) may be calculated with the aid of the following equation:
10 !Ls
ie
::;
!z
~
'"
=>
'-'
FORWARD BIASED SAFE OPERATING AREA
MTM45N12
MTM45N15
TJ(max) - TC
ROJC
10
100
VOS, ORAIN-TO-SOURCE VOLTAGE (VOLTS)
FIGURE 14 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
250
200
TJ '" 150°C
MTM45N12 ~
MTM45N15
MTM40N18
MTM40N20
o
o
50
100
150
200
VOS, ORAIN-TO·SOURCE VOLTAGE (VOLTS)
250
MOTOROLA TMOS POWER MOSFET DATA
C·225
MTMS5N08
MTMSSNIO
.®
MTM60NOS·
MOTOROLA
MTM60N06
De~igner'~
Data Slw('(
55 and 60 AMPERE
N·CHANNEL TMOS
POWER FETs
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
=
'OS(on)
0.04 OHM
60 and 100 VOLTS
These TMOS Power FETs are designed for .low voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relav drivers.
• Silicon Gate for Fast Switching Speeds Specified at 100"C
'OS(on) = 0.028 OHM
50 and 60 VOLTS
Switching Times
• Designer's Data -lOSS, VDS(on),VGS(th) and SOA
Specified at Elevated Temperature
MTM55N06
MTM55N10
MTM60N05
MTM60N06
• Rugged - SOA is Power Dissipation Limited
• Source-to-Drain Diode Characterized for Use With Inductive
Loads
"
PIN 1: GATE
2: SOURCE
CASE: DRAIN
TMOS
S
c
MAXIMUM RATINGS
MTM
Rating
Symbol
60N05
6ON06
55N06
55N10
Unit
Ora.in-Source Voltage
VOSS
50
60
80
100
Vdc
Orain·Gate Voltage
(RGS = 1.0 MO.)
VOGR
50
60
80
100
Vdc
Gate-Source Voltage
Drain Current
Continuous
Pulsed
Gate Current -
PLANE
F--
Vdc
±20
VGS
Ie
SEATING
Adc
10
10M
Pulsed
Total Power
Dissipation @TC = 25'C
Derate above 25'C
Operating and Storage
Temperature Range
IGM
60
300
55
276
1.5
Adc
Watts
Po
TJ.Tstg
wrc
-65 to 150
'C
B
C
E
F
G
H
J
K
II
Maximum Lead Temp. for
Soldering Purposes, 118"
from case for 5 seconds
A
D
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
MI LlMETERS
DIM MIN MAX
250
1.43
ReJC
0.7
'c!w
TL
275
'C
R
38.35
19.30
6.35
1.45
-
29.90
10.67
5.21
16.64
11.18
3.94
24;89
38.37
21.08
7.62
1.60
3.43
3D.40
11.18
5.72
17.15
12.19
4.09
26.67
INCHES
MIN
MAX
1.510 1.550
0.760 0.830
0.250 0.300
0.067 0.063
0.135
1.177 1.197
0.420 0.440
__~205 0.225
0.655
.675
.440 0.480
0.151 0.161
0.980 1.050
CASE 197.01
Designer's Data for "Worst Case" Conditions
TD-Z04AE
The Designer's Data Sheet permits the design of most circuits entirely from
the information presented. limit date - representing device characteristics
boundaries - are given to facilitate "worst case" design.
(TO-3TYPEI
MOTOROLA TMOS POWER MOSFET DATA
C-226
MTM5508,10/60N05,06
I
ELECTRICAL CHARACTERISTICS
(TC = 25°C unless otherwise noted)
Symbol
Characteristic
Min
Max
50
60
80
100
-
Unit
OFF CHARACTERISTICS
Orain-Source Breakdown Voltage
(VGS = 0, 10 = 5.0 mAl
VBR(OSS)
MTM60N05
MTM60N06
MTM55N08
MTM55N10
Zero Gate Voltage Orain Current
(VOS = 0.85 Rated VOS, VGS = 0)
TC = 100°C
lOSS
Gate-Body Leakage Current
(VGS = 20 Vdc, VOS = 0)
IGSS
-
Vdc
mAde
0.25
2.5
500
nAdc
ON CHARACTERISTICS'
Gate Threshold Voltage
(10 = 1.0 mA, VOS = VGS)
TJ = 100°C
2.0
1.5
Static Orain-Source On-Resistance
(VGS = 10 Vdc, 10 = 30 Adc)
(VGS = 10 Vdc, 10 = 27.5 Adc)
Orain-Source On-Voltage (VGS
(10 = 60 Adc)
(10 = 30 Adc, TJ = 100°C)
(10 = 55 Adc)
(10 = 27.5 Adc, TC = 100°C)
Forward Transconductance
(VOS = 15 V, 10 = 30 A)
(VOS = 15 V, 10 = 27.5 A)
Vdc
VGS(th)
=
rOS(on)
MTM60N05/MTM60N06
MTM55N08/MTM55Nl0
10 V)
VOS(on)
MTM60N05/MTM60N06
MTM60N05/MTM60N06
MTM55NOBlMTM55Nl0
MTM55NOBlMTM55N 10
-
Ohm
-
1.98
1.68
2.60
2.20
Vdc
gts
MTM60N05/MTM60N06
MTM55NOBlMTM55N10
4.5
4.0
0.028
0.04
10
10
-
mhos
-
DYNAMIC CHARACTERISTICS
Input Capacitance
(VOS
Output Capacitance
Coss
-
Crss
-
1000
-
300
td(off)
-
150
tf
-
100
Symbol
Typ
Unit
VSO
1.0
Vdc
Ion
150
ns
trr
200
ns
Ciss
= 25 V, VGS = 0,
f = 1.0 MHz)
Reverse Transfer capacitance
5000
pF
2500
SWITCHING CHARACTERISTICS' (TJ = 100°C)
Turn-On Oelay Time
(VOO
Rise Time
Turn-Off Oelay Time
= 25 V, 10 = 0.5 Rated
Rgen = 50 ohms)
t7:: V ~
~ :.-' ~
TJ = 25°C
~
20 V-
10 V--:
5.0 V
O. 4
10
2.0
4.0
6.0
8.0
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
/
V
6.0 V
/
5.0 V
0
2.0
4.0
6.0
8.0
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
10
TRANSFER CHARACTERISTICS
FIGURE 5 - MTP1N45. MTP1N50
.0
TJ =
.6
II
-55°C:-J fl-:l00oC
25°C
'rtt
If
II/
~
II) ~100oC
//1
VDS= 10V
/I
/ III
/ V
:/"
4
/, 'J
0
2
If!
8
VII
O.
/I
'iit 17'-25°C
.4
~
VDS = 10 V
I
6
TJ = -55°C-
/I
.2
8
FIGURE 6 - MTP2N35. MTP2N40
2. 0
~
2.0
4.0
6.0
8.0
VGS. GATE-TO·SOURCE VOLTAGE (VOLTS)
10
0
0
~
8.0
2.0
VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)
10
ON-RESISTANCE versus DRAIN CURRENT
FIGURE 7 - MTP1N45. MTP1N50
FIGURE 8 - MTP2N35. MTP2N40
0
0
6
TJ = 100°C
2
--
,...-
0
......
TJ= 100 C_
25°C
0
25 C
I
--
V
,...,.-
,/
-
-
V
f.--
-55°C
-55°C
0
VGS
0.2
I
I
0
1
0
J
I
o
0.4
0.6
10. DRAIN CURRENT (AMPS)
0.8
10 V
0
1.0
0.4
0.8
1.2
10. DRAIN CURRENT (AMPS)
MOTOROLA TMOS POWER MOSFET DATA
C-233
I
I
VGS = 10 V
1.6
2.0
MTP1N45, 5012N35, 40
TYPICAL CHARACTERISTICS
FIGURE 9 -'- GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
FIGURE 10 - CAPACITANCE VARIATION
.2
200
.,...""
.1
VOS = VGS
10=I.OmA
"'-..
16 0
"
...........
:
0
~
"""-
0
~ 80
........
0
25
-25
50
15
.
100
\
OS
u
'r--...
'"
125
40
..........
\
o
o
150
J
Ciss
120
g
"- I'x
0
I
TJ = 25°C _
VGS= 0 V
f=1.0MHz -
\
Coss
/
..........
........
10
erss
20
3D
40
50
VOS. ORAIN-TO-SOURCE VOLTAGE IVOlTSI
TJ. JUNCTION TEMPERATURE lOCI
FIGURE 11 - THERMAL RESPONSE
MTP1N45. MTP1N50. MlP2N35 AND MTP2N40
1
"
o. 7 =0"0.5
-
1_ o. 5
~o
:z:~
...
I-~
~
D. 3== 0.2
-
~~ O. 2
in'"
zo
- 0.1
"z
~: o. 1=:0.05
-
,...- -io-'
......
R6Jclt) rlt) R6JC
R6JClt) 2.5°C/W Max
o Curves ApplV for Power
IPulse Train Shown
Read Time at t1
TJlpkl - TC = Plpk) R6JCll)_
~ ~o.o 7 ===0.02
§ ~ 0.05
~~
:t ~ 0.03
0.02
-
0.0 t
0.01
PmJl
AI:
0.01
tf-I
SINGLE PULSE
'2Duty Cycle. 0 = t1/12
I II
0.02 0.03
0.05
0.1
0.2
0.3
10
0.5
20
30
50
100
200 300
500
1000
t. TIME (ms)
TMOS POWER FET CONSIDERATIONS
devices due to voltage buildMup on the input capacitor due to
leakage currents or pickup.
Switching Speed - The switching speeds of these devices are
dependent on the driving impedance. Extremely fast switching
speeds can be attained by driving the gate from a voltage source.
Gate Protection - These devices do not have an interne:.,
monolithic· zener diode from gate to source. The addition of an
internal zener diode may result in detrimental effects on the
reliability of a power MOSFET. If gate protection is required. an
external zener diode is recommended.
Transfer Characteristics - The tra oster characteristics are
lineer at drain currents of 0.5 Amp.ISee Figures 5 and 6_I.Linear
amplifiers with high frequency response can be designed using
this product.
Handling and Packaging - MOS ICs are susceptible to damage
from electrostatic· charge. Experience has shown that these
devices are more rugged than MOS les. This is primarily due
to· the comparatively larger capacitances associated with
power devices, however, reasonable precautions in handling
and packaging MOS devices should be observed.
Gat. Voltage Rating -' Never exceed the gate voltage. rating
of·±20 V. Exceeding the rated VGS can result in permanent
damage to the oxide layer in the gale region.
Gate Termination - The gate of these devices are essentially
capacitors. Circuits that leave the gate open-circuited or floating
should be avoided. These conditions can result in turn·on Of the
MOTOROLA TMOS POWER MOSFET DATA
C-234
MTP1N45, 50/2N35, 40
SAFE OPERATING AREA INFORMATION
MAXIMUM RATED FORWARD BIASED SAFE OPERATING AREA
FIGURE 12 - MTP1N45. MTP1N50
--_.
4. Or-- -
'"
~
~,
------
I- ,
r---
- ,~
r-r-
~, -
1. Of-- I--- -
-:-:,.-
r- ,-
i13 r f--rz
VGS = 20 V
PO. If==:F=Single Pulse =-=
f::::=~TC = 25°C=_
:
J
3:
1.0
~
..
~s
t
j
I
~.'
K
r~ I'..'
,
.
MTP1N45MTP1N50
W-.ll.L- __ '-_
10
100
Vas, ORAIN-TO-SOURCE VOLTAGE (VOLTS)
. __
10
.- --100 MS
1.0 ms
~hermlall \i~:t - - -
~
=-1:+
oj
\
10 ms
r-----:-.I'--- rOSlon) limit --~=
Package limit - - .-
Q
FIGURE 13 - MTP2N35. MTP2N40
L
500
Vas. ORAIN-TO-SOURCE VOLTAGE IVOLTS)
FORWARD BIASED SAFE OPERATING AREA
IDM
The de data of Figures 12 and 13 is based on a case temperature
(Te) of 75°C and a maximum junction temperature (TJmax) of
1500 . The actual junction temperature depends on the power
dissipated in the device and its case temperature. For various
pulse widths, duty cycles, and case temperatures. the peak allowable drain current (10M) may be calculated with the aid of the
following equation:
= I 1250Cl- TJ(max) - TC ]
o
[:D' ROJC' rlt)
Where
IO(25°C) :: the de drain current at Te:: 25°C from Figures 12
and 13
TJ(max) :: rated maximum junction temperature
:: device case temperature.
TC
rated power dissipation at Te:: 25°C
PD
rated steady state thermal resistance
ROJC
r(t)
:: normalized thermal response from Figure 11
=
=
FIGURE 14 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
5. 0
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) of Figure 14, is the
boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the peak
current, 10M and the breakdown voltage, V(BR)OSS. The
switching SOA shown in Figure 14 is applicable for both turn~on
and turn-off
the devices for switching times less than one
microsecond.
The power averaged over a complete switching cycle must be
less than:
_ 4. 0
~
:.
5~
3. 0
of
i'l!
'"13
TJ';; 150°C
z 2. 0
~
E
1.0
MTP2N35MTP2N40
MTP1N45
MTP1N50
400
100
200
300
VOS. ORAIN-TO-SOURCE VOLTAGE IVOLTS)
TJ(max) - TC
R9JC
500
MOTOROLA TMOS POWER MOSFET DATA
C-235
®
MTPIN55, MTPIN60
MOTOROLA
Designer"s Data Sheet
1.0AMPERE
N-CHANNEL TMOS
POWER FET
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
n
rOS(onl = 12
550 and 600 VOLTS
These TMOS Power FETs are designed for high voltage, high
speed power switching applications such as line operated switching
regulators, converters, solenoid and relay drivers.
•
Silicon Gate for Fast Switching Speeds Specified at 100°C
Switching Times
MTP1N65
MTP1N60
D
• Designer's Data ~ lOSS, VOS(on) VGS(th) and SOA Specified at
Elevated Temperature
• Rugged •
SOA is Power Dissipation Limited
Source-to-Orain Diode Characterized for Use With
Inductive Loads
G
• Low Drive Requirement, VG(th) = 4.5 Volts (max)
1r
Gu--~
TMOS
S
MAXIMUM RATINGS
Drain -
Rating
Symbol
MTP1N55
MTP1N60
Unit
Source Voltage
VDSS
550
600
Vdc
VDGR
550
600
Vdc
Drain - Gate Voltage
RGS = 1 Mll
Gate -
Source Voltage
Drain Current
Continuous
Pulsed
Gate Current -
VGS
±20
Vdc
Adc
Pulsed
Total Power'
ID
IDM
1.0
3.0
IGM
1.5
Adc
PD
40
Watts
0.4
W/oC
TJ, Tslg
-6510150
°C
ROJC
2.5
°C/W
TL
275
°C
Dissipation @ TC = 25°C
Derate above 25°C
Operating and Storage
NOTES:
1. DIMENSIONSL ANO H APPLIES TO ALL LEADS.
2. DIMENSION Z DEFINES A ZONE WHERE ALL
BOOY ANO LEAD IRREGULARITIESARE
ALLOWED.
3. DIMENSIONING ANO TOLERANCING PER ANSI
Y14.51973.
4. CONTROLLING DIMENSION: INCH.
Temperature Range
THERMAL CHARACTERISTICS
Thermal Resista nee
Junction to Case
Maximum Lead Temp. for
Soldering Purposes, 1/8from case for 5 seconds
Designer's Data for "Worst Case" Conditions
The Designer's Data Sheet permits the design of most circuits entirely from the
information presented. Limit data - representing device characteristics boundaries - are
given to facilitate "worst case" design.
MOTOROLA TMOS POWER MOSFET DATA
C-236
MILLIMETERS
DIM MIN MAX
A 15.11 15.75
B 9.65 10.29
C 4.06
4.82
o 0.64 0.89
F
3.61
3.73
G
2.41
2.67
H
2.79
3.30
J
0.36
0.56
K 12.70 14.27
L
1.14
1.27
N 4.83
5.33
Q
2.54
3.04
R
2.04
2.79
S
1.14
1.39
T
5.97
6.48
U 0.76
1.27
INCHES
MIN MAX
0.595 0.620
0.380 0.405
0.160 0.190
0.025 0.035
0.142 0.147
0.095 0.105
0.110 0.130
0.014 0.022
0.500 0.562
0.045 0.050
0.190 0.210
0.100 0.120
0.080 0.110
0.045 0.055
0.235 0.255
0.030 0.050
0.045
2.03
0.080
CASE 221A-02
TO-22DAB
MTP1N55,60
ELECTRICAL CHARACTERISTICS ITC = 25°C unless otherwise noted)
I
Characteristic
Symbol
Min
Max
550
600
-
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
IVGS = 0, 10 = 5.0 mAl
VIBR)OSS
MTP1N55
MTP1N60
Zero Gate Voltage Drain Current
(VOS = 0.85 Rated VOSS, VGS = 0)
TJ = 100°C
lOSS
Gate-Body Leakage Current
IVGS = 20 Vdc, VOS = 0)
IGSS
Vdc
mAdc
-
0.25
2.5
2.0
1.5
4.5
4.0
-
6.0
16
12
500
nAdc
ON CHARACTERISTICS'
Gate Threshold Voltage
IVo = 1.0 mA, VOS = VGS)
TJ = 100°C
VGSlth)
Drain-Source On-Voltage IVGS = 10 V)
110 = 0.5 Adc)
110 = 1.0 Adc)
110 = 0.5 Adc, TJ = 100°C)
VOSlon)
Static Drain-Source On-Resistance
IVGS = 10 Vdc, 10 = 0.5 Adc)
rOSlon)
-
12
Ohms
gl.
0.5
-
mhos
Forward Transconductance
IVos = 15 V, 10 = 0.5 A)
Vdc
Vdc
SAFE OPERATING AREAS
Forward Biased Safe Operating Area
Switching Safe Operating Area
DYNAMIC CHARACTERISTICS
Input Capacitance
"""'o,..-u-'tP_u_t_C"'a.::-pa_c-,it;-a.:.-nc"'e_-,-_ _--lIVOS = 25 V, VGS = 0, 1= 1.0
Reverse Transfer Capacitance
MHz)I-_"?"'-_+_____I-_-:-::--l
SWITCHING CHARACTERISTICS'ITJ = 100°C)
Turn-On Delay Time
Rise Time
tdlon)
tr
IVos = 25 V, 10 = 0.5 A,
Turn-Off Delay Time
Rgen = 50 ohms)
tdlo")
tl
Fall Time
-
35
-
30
20
ns
15
SOURCE DRAIN DIODE CHARACTERISTICS'
Characteristic
Forward On-Voltage
Forward Turn-On Time
Reverse Recovery Time
*Pulse Test: Pulse Width
~300
I
I
I
,.,.5. Duty Cycle
Symbol
Typ
Unit
IS = 1.0 A
VSO
1.0
Vdc
VGS=O
ton
30
ns
trr
250
ns
~2%.
RESISTIVE SWITCHING
FIGURE 1 -
FIGURE 2 - SWITCHING WAVEFORMS
SWITCHING TEST CIRCUIT
Idlon)
Output, Vout
Inverted
MOTOROLA TMOS POWER MOSFET DATA
C-237
MTP1N55,60
TYPICAL CHARACTERISTICS
FIGURE 4 - TRANSFER CHARACTERISTICS
FIGURE 3 - ON-REGION CHARACTERISTICS
1.0
~o
8
6
2
I~
IVGS =
V
VGS=10V
,
4
TJ = 25°C
~ ~-r Jov
I GS I
/. ijiiI"
II
6
VGS=7.0V
TJ = 100°C
8
VGS = 6.0 V
-
0
TJ =1 100oCI
6
2
TJ = 25°C
I
--
o
o
10
2.0
4.0
6.0
8.0
VoS. oRAIN-TO-SOURCE VOLTAGE IVOLTS)
ffi
~
il'e>!
!--I ..,-
p
'"~
............
1. 1
I
1.0
"""" 1""'-, ~
0.90
i'..
...'"
"-
~ 0.60
VoS=10V
0.8
~.
i;!
::>
0
160
0
IO=~~
~ 5. 0
: 3. 0
co
t
$
--I-
10
5)
I;t OIS AI
10 = 0.25
-I-
01 ~ -I-60 -40 -20
.... 1-
40
60
125
150
--
80
100
TJ~25od
\
120
40
140
TJ. JUNCTION TEMPERATURE (0C)
_
VGS = 0 V
f= 1.0 MHz -
I'
II": .,:;';'
vtstt ~
~20
100
FIGURE 8 - CAPACITANCE VARIATION
200
e>
75
TJ. JUNCTION TEMPERATURE (0C)
t:l
t:l
50
25
-25
>
FIGURE 7 - ON-VOLTAGE VARIATION
~
.......
.........
~ 0.10-50
1.0
u;10 0
!;i!
Vos = VGS
10= LOrnA
~
§;
L--- ~
0.4
0.6
10. DRAIN CURRENT (AMPS)
10
1.2
9
TJ I-55°C
:.,..... V
2.0
4.0
6.0
8.0
VGS. GATE-TO-SOURCE VOLTAGE (VOLTS)
~
I--
I
V/.
FIGURE 6 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE (NORMALIZED)
FIGURE 5 - ON-RESISTANCE VARIATION
e>
~
-"-
2
/
0.2
/
TJ = 25°C-"-
~
0
/
TJ = -55°C_ ~
VGS = 10 V
W
"
Ir
o
o
2.0
1\
\
o 'o
Ciss
,
Coss
/
10
20
30
40
VoS. ORAIN-TO-SOURCE VOLTAGE (VOLTS)
MOTOROLA TMOS POWER MOSFET DATA
C-238
Crss
50
MTP1N55,60
SAFE OPERATING AREA INFORMATION
FIGURE 9 - MAXIMUM RATED FORWARD
BIAS SAFE OPERATING AREA
10
--.,
I.0
00
~
FIGURE 10 - MAXIMUM RATED SWITCHING
SAFE OPERATING AREA
jI'
jlS
.,',0 ms
~. 3.0
10 m
!
tz
~ 2.0
dc
lE:::;---- rOSlon) Um~
~.
Tharmal Limtt
f---. - Package Limit
a
~
TJ';; lS00C
:-
MTP1NSSMTilN60- :-
~1. 0
MTP1N55MTP1N60
0.0 1§~GS = 20 V. Singla Pul••
FTC = 2SOC
10
100
VDS, DRAIN-TO.sOURCE VOLTAGE (VOLTS)
100
1000
200
300.
-
SOD
4DO
600
VDS, DRAIN-TD-SOURCE VOLTAGE (VOLTS)
FORWARD BIASED SAFE OPERATING AREA
SWITCHING SAFE OPERATING AREA
The de data of Figure 9 is based on a case temperature (Te) of
25°C and a maximum junction temperature (TJmax)of 1500 • The
actual junction temperature depends on the power dissipated in
the device and its case temperature. For various pulse widths,
duty cycles, and case temperatures, the peak allowable drain
current 110M) may be calculated with the aid of the following
The switching safe operating area (SOA) of Figure 10, is the
boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the peak
current, 10M and the breakdown voltage, V(BR)OSS. The
switching SOA shown in Figure 10 is applicable for both turn~on
and turn-off of the devices for switching .times less than one
microsecond.
The power averaged over a cample.te switching cycle must be
less than:
equation:
10M
= I (250C) TJ(max) - TC
o
Po . ROJC . r(t)
TJ(max) - TC'
ROJC
Where
IO(25°C) = the dc drain current at TC = 25°C from Figure 9.
TJ(max) ::; rated maximum junction temperature.
TC
:; device case temperature.
Po
= rated power dissipation at TC = 25°C.
ROJC
== rated steady state thermal resistance
r(U
= normalized thermal response from Figure 11.
FIGURE 11 - THERMAL RESPONSE
1
«
~
"W
O. 3== 0.1
O. 1
;:;;
C>
/
/
%
8
25°:"- .........
...........
1. 8
--
VGS = 10 V
c;;
00
1.0
2.0
3.0
10. DRAIN CURRENT (AMPS)
4.0
5.0
!? O. 30
1.0
2.0
3.0
ID. DRAIN CURRENT (AMPS)
MOrOROLA TMOS POWER MOSFET DATA
C-242
4.0
5.0
MTP2N18, 20/3N12, 15
TYPICAL CHARACTERISTICS
FIGURE 9 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
~
1.2
:IE
a:
1.1
.
.
!:!
CI
FIGURE 10 - CAPACITANCE VARIATION
250
..........
VOS = VGS
10=1.0mA
...........
~
I'.
\
~
!:;
""'"
1.0
§!
9CI
:z: 0.90
~
..
........
I'-...
~
I'....
0.80
......
,
~
50
.........
:f 0.70
25
-25
-50
>
50
Cisl
\
-........
!i!
~
b_
TJ=25 o
I-VGS = 0 V
1=1.0MHz-I - -
200
100
75
125
o
ISO
\
'\
...........
COl.
........
o
I
10
TJ. JUNCTION TEMPERATURE (OCI
Cr..
20
30
40
VDS. DRAIN·TD-SOURCE VOLTAGE (VOLTS)
50
FIGURE 11 - THERMAL RESPONSE
MTP2N18. MTP2N20. MTP3N12 AND MTP3N15
I
""
-.
o. 7=0'05
_ o. 5
~
wO
,",W
t- ~
>-~
O. 3== 0.2
w~
o. 2
z<
u;'"
ZO
...'" 0.6 r-
..,'"
i
'"t
FIGURE 8 - MTP5N05. MTP5N06
;;;- 0.8
::;;
-I""'" -'-55°C
,.....
-..:-- ..-
--- ----
/'v
:.:
~
V
V
~a:
~
~ 0.4
=
~
~
'" 0.6
:...--
::>
~
...'"
_V
f.---'"
100°C
-55°C
-
~
V
V
V V
~
~ 0.2
~
VGS= 10 V -
0.4
T
I
E' 0.2
o
1.0
2.0
3.0
10. DRAIN CURRENT (AMPS)
4.0
VGS = 10 V
t
i1f
5.0
~
0
o
1.0
2.0
3.0 4.0
5.0
6.0
7.0
10. DRAIN CURRENT lAMPS)
MOTOROLA TMOS POWER MOSFET DATA
C-247
8.0
9.0
10
MTP4N08, 10/5N05, 06
TYPICAL CHARACTERISTICS
FIGURE 9 - GATE-THRESHOLD VOLTAGE
VARIATION WITH TEMPERATURE
e-
1.2
II:
1.1
~:Ii
0
"'-
VOS ; VGS
~
!!.
w
'"~
1.0
40
10; 1.0 mA
~
0
>
~
"'- ...........
:z: 0.90
[jl
....:z:
...
~ 0.80
-25
25
50
75
100
125
o
o
150
-
Ciss
Cos
"-
.........
-50
~
100 1\
........ ~
'"t
-
\
o\.
r-...
~ 0.70
I
I
TJ; 25°C _
VGS; 0 V
f=1.0MHz -
0 1\
o\
90
>
FIGURE 10,- CAPACITANCE VARIATION
500
s
Crss
10
20
30
40
VOS, ORAIN·TO·SOURCE VOLTAGE IVOLTS)
TJ. JUNCTION TEMPERATURE laC)
50
FIGURE 11 - THERMAL RESPONSE
I
o. If-Ooos
"
~ _ 0.5
we
::::: 03 ~ 0.2
~ ~ 0.2
0;'"
",0
"'"
r----
-
-,.
01
~;: O. IF=005
~ ~ 0.0 7~002
~ ~ 0.05
~~
~ ~ 0.03
0.02
-
r----
0.01
0.01
R6JCII) - rll) R6JC
R6JC(I)- 2.5°C/W Max
--
",w
>--
o Curves ApplV for Power
Pulse Train Shown
Read Time at 11
TJlpk) - Te = Plpk) R6JCII)
PmJl
..K"
0.01
-tIl
SINGLE PULSE
0.02 0.03
~-J
' OUl'( Cycle, 0 ; 11/12
I II
O.OS
0.1
02
0.3
10
O.S
I,
10
30
50
100
200
300
500
HllIO
TIME (ms!
TMOS POWER FET CONSIDERATIONS
Switching Speed - The switching speeds of these devices are
dependent on the driving impedance. Extremely fast switching
speeds can be attained by driving the gate from a voltage source.
devices due to voltage build·up on the input capacitor due to
leakage currents or pickup.
Gate Protection - These devices do not have an internal
monolithic zener diode from gate to source. The addition of an
internal zener diode may result in detrimental effects on the
reliability of a power MOSFET. If gate protection is required, an
external zener diode is recommended.
Transfer Characteristics - The transfer characteristics are
linear at drain currents of 0.5 Amp. (See Figures 5 and 6.) Linear
amplifiers with high frequency response can be designed using
this product.
Gate Voltage Rating - Never exceed the gate voltage rsting
of ±20 V, Exceeding the rated VGS can result in permanent
damage to the oxide layer in the gate region.
Handling and Packaging - MOS ICs are susceptible to damage
from electrostatic charge. Experience has shown that these
devices are more rugged than MOS ICs. This is primarily due
to the comparatively larger capacitances associated with
power devices. however. reasonable precautions in handling
and packaging MOS devices should be observed.
Gate Termination - The gate of these devices are essentially
capacitors. Circuits that leave the gate open-circuited or floating
should be avoided. These conditions can result in turn-on of the
MOTOROLA TMOS POWER MOSFET DATA
C-248
MTP4N08, 10/5N05, 06
SAFE OPERATING AREA INFORMATION
MAXIMUM RATED FORWARD BIASED SAFE OPERATING AREA
FIGURE 13 - MTP5N05. MTP5N05
FIGURE 12 - MTP4N08. MTP4N10
9.0
=
-
10
10 ps
po(
,
100 ps
f-VGS = 20 V 1.0ms
Single Pulse I I I I I
FTC = 25°C _10 ms
" -""'V\
V
ie
"' "' i\
~
1»
~
!S
u
.-:::-
dc
- - - - rOSlonl limit
- Package limit
- - - Thermal limn
10 ps
100 ps
10 m.
1.0ms
d~
1.0
z
MTP5N05
MTP5N06
~
rOSlonl limit - - - - _
Package Limit
_ MTP4NOS
I
I I I
Thermal Limit - - -
c
E>
f-- VGS = 20 V
_ Single Pulse
TC = 25°C
-rTPnol
1111I11
0.1
1.0
- -
-
0.1
1.0
10
100
VOS. ORAIN-TO·SOURCE VOLTAGE IVOLTSI
I I I
10
60
VOS. ORAIN·TO·SOURCE VOLTAGE IVOLTSI
FORWARD BIASED SAFE OPERATING AREA
Where
lo125°CI = the dc drain current aITC= 25°C from Figures 12
and 13
TJlmaxl ::; rated maximum junction temperature
== device case temperature
TC
= rated power dissipation at TC = 25°C
Po
:;: rated steady state thermal resistance
R6JC
::; normalized thermal response from Figure 11
rltl
Thede data of Figures 12and 13 ;sbasedon a case temperature
ITCI of 25°C and a maximum junction temperature ITJmaxl of
1500 . The actual junction temperature depends on the power
dissipated in the device and its case temperature. For various
pulse widths, duty cycles. and case temperatures, the peakallowable drain current IIOMI may be calculated with the aid of the
following equation:
I
OM
1
= I 1250qf TJlmaxl' TC
0
!.PO . R8JC . rltlj
FIGURE 14 - MTP4N08. MTP4N10
10
..
SWITCHING SAFE OPERATING AREA
S.O
'"
~
MTP5N05
MTP5N06
~ 6.0
~
-
::>
-
1c
-TJ'; 150
~ 4.0
MTP4NOS ~
MTP!Nl0
~
E> 2.0
o
o
The switching safe operating area ISOAI of Figure 14. is the
boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the peak
current. 10M and the breakdown Voltage. VIBRIOSS. The
switching SOA shown iniFigure 14isapplicableforboth turn-on
and turn-off of the devices for switching times less than one
microsecond.
The power averaged over a complete switching cycle must be
less than:
r
2D
40
60
SO
VOS. ORAIN-TO-SOURCE VOLTAGE IVOLTSI
TJlmax) - TC
R8JC
100
MOTOROLA TMOS POWER MOSFET DATA
C-249
•
•
Small-Signal Data Sheets
Data sheets are arranged in alphanumeric
sequence except when information applies to more
than one device, e.g., MFE930, MFE960 and
MFE990. Consult the table of contents for these
part numbers.
®
2N6660 MPF6660
2N6661 MPF6661
MOTOROLA
N-CHANNEL ENHANCEMENT-MODE
TMOS FIELD-EFFECT TRANSISTOR
2.0 AMPERE
N-CHANNEL TMOS
These TMOS FETs are designed for high-speed switching applications such as switching power supplies, CMOS logic, microprocessor or TTL-to-high current interface and line drivers.
FET
60. 90 VOLTS
• Fast Switching Speed -
ton = toff = 5.0 ns Max
2.0 Ohm Typ - 2N6660/2N6661
• Low On-Resistance -
-
MPF666iJ/MPF6661
• Low Drive Requirement, VGS(th) = 2.0 V Max
• Inherent Current Sharing Capability Permits Easy Paralleling of
Many Devices
2N6660
2N6661
lr
TMOS
s
CASE 79-02
TO-205AD
(TO-39)
MAXIMUM RATINGS
Svmbol
2N6660
MPF6660
2N6661
MPf6661
Unit
Drain-Source Voltage
VOSS
60
90
Vdc
Drain-Gate Voltage
VDGO
60
90
Vdc
Rating
Gate-Source Voltage
VGS
± 30
Vdc
Drain Current Continuous (1)
Pulsed (2)
10
10M
2.0
3.0
Adc
Total Power Dissipation
@!TC = 25'C
Derate above 2S'C
Po
Total Power Dissipation
@TA=2S'C
Derate above 25'C
Po
Operating and Storage
Temperature Range
TJ. Tatg
2N6660
2N6661
MPF6660
MPF6661
6.25
SO
2.5
20
mWrC
-
1.0
8.0
mWrC
MPF6660
MPF6661
Watts
Watts
-5Sto +150
·C
(1.1 The Power Dissipation of the Dackage may result in a lower continuous drain current.
CASE 29-03
TO-226AE
(21 Pulee Width .. 300 "" Duty Cvcle .. 2.0%
MOTOROLA TMOS POWER MOSFET DATA
0-2
2N6660, 611MPF6660, 61
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted.)
I
Characteristics
I
Typ
Max
10
pAdc
IGSS
-
-
100
nAdc
VGS(th)
0.8
1.4
2.0
Vdc
-
-
3.0
4.0
0.9
0.9
1.5
1.6
Symbol
Min
Unit
OFF CHARACTERISTICS
Orain-Source Breakdown Voltage
(VGS = 0, 10 = 10 pA)
Zero Gate Voltage Orain Current
(VOS = Maximum Rating, VGS
Vdc
V(BR)OSS
2N6660, MPF6660
2N6661, MPF6661
= 0)
Gate-Body leakage Current
(VGS = 15 V, VOS = 0)
60
90
lOSS
ON CHARACTERISTICS'
Gate Threshold Voltage
(VOS = VGS, 10 = 1.0 mAl
Orain-Source On-Voltage
(VGS = 10 V, 10 = 1.0 A)
(VGS = 5.0 V, 10
Vdc
VOS(on)
2N6660, MPF6660
2N6661, MPF6661
= 0.3 A)
2N6660, MPF6660
2N6661, MPF6661
Static Orain-Source On-Resistance
(VGS = 10 Vdc, 10 = 1.0 Adc)
Ohms
rOS(on)
-
-
10{on)
1.0
2.0
9ls
170
Input Capacitance
(VOS = 25 V, VGS = 0, 1= 1.0 MHz)
Ciss
Output Capacitance
(VOS = 25 V, VGS = 0, I
2N6660, MPF6660
2N6661, MPF6661
On-State Orain Current
(VOS = 25 V, VGS = 10 V)
Forward Transconductance
(VOS = 25 V, 10 = 0.5 A)
-
3.0
4.0
-
-
mmhos
-
30
50
pF
Coss
-
20
40
pF
Crss
-
3.6
10
pF
5.0
ns
5.0
ns
5.0
ns
5.0
ns
Amps
DYNAMIC CHARACTERISTICS
=
1.0 MHz)
Reverse Transler Capacitance
(VOS = 25 V, VGS = 0, I = 1.0 MHz)
SWITCHING CHARACTERISTICS'
Rise Time
tr
-
Fall Time
tl
-
Turn-On Time (See Figure 1)
ton
Turn-Off Time (See Figure 1)
toft
·Pulse Test: Pulse Width
:$0
300 JLS, Duty Cycle,;;; 2%.
MOTOROLA TMOS POWER MOSFET DATA
0-3
-
•
2N6660, 61/MPF6660, 61
RESISTIVE SWITCHING
FIGURE 2 _ SWITC'HING WAVEFORMS
FIGURE 1 - SWITCHING TEST CIRCUIT
+
25V
To Sampling Scope
23,rn_ToTB-f-._-it-=-=-=450 n Input
Vout
Output
Vout
Inverted
Input
AGURE 3 -
FIGURE 4 -
VGS(th) NORMALIZED versus TEMPERATURE
2,0
~
'"~
0
90
:J:
V>
~ 0,8
ON-REGION CHARACTERISTICS
2,0
VOS = VGS
10 = tOmA
1,6
> 1,2
Vin
--
-r--
i!:
?~ 0,4
°
°
-50
FIGURE 5 -
VGS
-
./
,/
r--.
r---
-""
~~
-
~V
~~
..... ~
150 lOCI
2,0
VGS
/'
%
~
z<-> 60
;::0
~
7,OV
'/
6,0 V
«
40
<->
I
5,0 V
20
...'I",
VGS
5,OV
4,0 V
4,0
40
°
V
\
\
\.
~
CiSS I
........ r-
Coss
~
10
Cr••
20
30
40
50
VOS, ORAIN·TQ·SOURCE VOLTAGE IVOLTSI
MOTOROLA TMOS POWER MOSFET DATA
0-4
=
!\
U
4,0 V
10
20
30
Vas, ORAIN·TO·SOURCE VOLTAGE IVOLTS)
6,OV
~
CAPACITANCE versus DRAIN-TO-SOURCE VOLTAGE
80
8,0 V
U
rI
7,0:!.,
100
= 10V
9,0 V
,-
~
to
2,0
3,0
VOS, DRAIN·TO·SOURCE VOLTAGE IVOLTSI
FIGURE 6 -
OUTPUT CHARACTERISTICS
-
=.,!!
........ ~
l.e: -::- ~
~
50
100
TJ, JUNCTION TEMPERATURE
I
60
2N6660, 61/MPF6660, 61
FIGURE 7 - ON-VOLTAGE versus TEMPERATURE
10
;
5.0
~
r=VGS
l...- I--"
~
1.0
I...- .....
1.SA
10
10V
1.0A
.....
-
.....
-~
:=>
~
I?z ~::
..-
-
""""
~
r-
~ 0.3
_ 0.2
J
0.1
-50 -30 -10
10
30
50
70
90
TJ. JUNCTION TEMPERATURE (OCI
110
130
150
OUTUNE DIMENSIONS
,J1 -l
R1n~~
B
J'!rl~'r !
fe
K
_J-, DU
D-:'3i+;
PLANE
rlR ""~'
~±-j
--+-,
t
'. PIN 1. SOURCE
2. GATE
3. DRAIN/CASE
G.
/i?f\
O-:_t:ro-
'(yJ
Vty
MIlliMETERS
MIN MAX
8.89 9.40
8.00 8.51
6.10 6.60
0
0.406 0.533
E
0.229 3.18
F
0.406 0.483
G
4.83 5.33
H
0.711 0.864
J
0.737 1.02
K 12.70
L
6.35
M
45' NOM
P
1.27
Q
90' NOM
R
2.54
DIM
A
B
C
IlllI 0.10 (O.004)(~ITIA ~I B@I
4. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5, 1913.
-
STYLE 6:
M
NOTES:
1. DIMENSIONS ·A· AND ·B· ARE DATUMS.
2. ·T· IS SEATING PLANE.
3. POSITIONAL TOLERANCE FOR LEADS:
MILLIMETERS
MIN MAX
7.37
7.87
5.21
4.44
3.18 4.19
0.61
0
.0.46
1.27 BSC
G
J
2.54 BSC
12.70
K
2.03
2.92
N
R
3.43
0.46
0.61
S
!
Ii
-<-·D
rN
N
DIM
A
B
C
I
~
a '··-r
STYlE no
PIN 1. SOURCE
2. GATE
3. DRAIN
f
L
,-~K
SEATING
i-L~
hs
J~l
-
- - -1
INCHES
MIN MAX
0.290 0.310
0.205
0.17
0.125 0.165
0.D18 0.024
0.050 BSC
0.100 BSC
0.500
O.OBO 0.115
0.135
0.D18 0.024
-
INCHES
MIN MAX
'J
0.315
0.240
0.016
0.009
0.016
0.190
0.028
0.029
0.500
0.250
45' NOM
0.050
90' NOM
0.100
-
All JEOEC dimensions and notesapplv.
CASE 79-02
TO-205AD
(TO-39)
CASE 29-03
TO-226AE
MOTOROLA TMOS POWER MOSFET DATA
0·5
®
85107
85107A
MOTOROLA
Advance Information
200 VOLTS
N·CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS FIELD EFFECT TRANSISTOR
N·CHANNEL TMOS
FET
This TMOS FET is designed for high voltage, high speed switching applications such as line drivers, relay drivers, CMOS logic,
microprocessor or TTL to high voltage interface and high voltage
display drivers.
• Fast Switching Speed - ton = toff 6 ns typ
• Low On-Resistance - 4.5 Ohms typ (BS107A)
• Low Drive Requirement, VGS(th) 3.0 V max
• Inherent Current Sharing Capability Permits Easy Paralleling
of Many Devices
,r
G o---l.{
TMOS
s
MAXIMUM RATINGS
Symbol
Value
Unit
Drain-Source Voltage
Rating
VDS
200
Vdc
Gate-Source Voltage
VGS
:t20
Vdc
Drain Current
Continuous(1 )
Pulsed(2)
10
10M
250
500
mAde
Po
0.6
Watt.
TJ,Tstg
-55 to 150
·C
Total Device Dissipation (a TC = 25°C
Derate above 25°C
Operating and Storage Junction
Temperature Range
(1) The Power Dissipation of the package may result in a lower continuous drain current.
12) Puis. Width", 300 1'8, Duty Cycle'" 2.0%.
STYLE 30:
PIN 1. DRAIN
2. GATE
3. SOURCE
MILLIMETERS
INCHES
MIN MAX
MIN MAX
4.32
5.33 0.170 0.210
B
4.44
.175 0.2 5
5.2
C
3.18
4.19 0.125 0.165
D
0.41
0.56 0.016 0.022
F
0.41
0.48 0.016 0.019
1.14
1.40 0.045 0.055
G
H
2.54
- 0.100
J
2.41
2.67 0.095 0.105
K 12.70
0.500
L
6.35
.2 0
2.67 0.080 0.105
N
2.03
P
2.92
0.115
R
3.43
- 0.135
S
0.36
0.41 0.014 0.016
All JED ec dimensions and notes apply.
CASE 29-02
ITO-226M)
DIM
A
-
-
MOTOROLA TMOS POWER MOSFET DATA
0-6
-
85107, A
I
ELECTRICAL CHARACTERISTICS (TA = 25"C unless otherwise noted.)
Symbol
Min
Typ
Max
Unit
Zero-Gate-Voltage Drain Current
(VOS = 130 V, VGS = 0)
lOSS
-
-
30
nAdc
Drain-Source Breakdown Voltage
(VGS = 0, 10 = 10 !LA)
V(BR)OSX
200
-
-
IGSS
-
0.Q1
10
nAdc
Gate Threshold Voltage
(10 = 1.0 rnA, VOS = VGS)
VGS(Th)
1.0
-
3.0
Vdc
Static Drain-Source On Resistance
BS107
(VGS = 2.6 V, 10 = 20 rnA)
(VGS = 10 V, 10 = 200 rnA)
BS107A
(VGS = 10 Vdc)
(10 = 100 rnA)
(10 = 250 rnA)
rOS(on)
Characteristic
OFF CHARACTERISTICS
Gate Reverse Cu rrent
(VGS = 15 Vdc, VOS = 0)
Vdc
ON CHARACTERISTICS·
Ohms
-
-
28
14
-
-
4.5
4.8
6.4
6.0
SMALL-SIGNAL CHARACTERISTICS
Input Capacitance
(VOS = 25 V, VGS = 0, f = 1.0 MHz)
Ciss
-
72
90
pF
Reverse Transfer Capacitance
(VOS = 25 V, VGS = 0, f = 1.0 MHz)
Crss
-
2.8
3.5
pF
Output Capacitance
(VOS = 25 V, VGS = 0, f = 1.0 MHz)
Coss
-
15
20
pF
9fs
200
400
Forward Transconductance
(VOS = 25 V, 10 = 250 rnA)
SWITCHING CHARACTERISTICS
Turn-On Time
Turn-Off Time
*Pulse Test: Pulse Width
EO
300 p,s, Duty Cycle
os;;
2.0%.
MOTOROLA TMOS POWER MOSFET DATA
0-7
-
mmhos
1:1
®.
BS170
II
MOTOROLA
N-CHANNEL ENHANCEMENT-MODE
TMOS FIELD-EFFECT TRANSISTOR
60 VOLTS
This TMOS FET is designed for high-voltage. high-speed switching applications such as line drivers. relay drivers. CMOS logic.
microprocessor or TTL-to-high voltage interface and high voltage
display drivers.
N-CHANNEL TMOS
FET
• Fast Switching Speed - ton = toff = 6.0 ns Typ
• Low On-Resistance - 5.0 Ohms Max
• Low Drive Requirement. VGS(th) = 3.0 V Max
• Inherent Current Sharing Capability Permits Easy Paralleling of
Many Devices
,r
G0----'.i
TMDS
STYLE 30:
PIN 1. DRAIN
2. GATE
3. SOURCE
s
NOTES:
1. CONTOUR OF PACKAGE BEYOND ZONE "P"
IS UNCONTROLLED.
2. DIM "F" APPLIES BETWEEN "H" AND
"L" DIM "0" & "S" APPLIES BETWEEN
"L" & 11.70 mm 10.5") FROM SEATING
PLANE. LEAD DIM IS UNCONTROLLED
IN "H"' & BEYOND 12.70 mm 10.5")
FROM SEATING PLANE.
MAXIMUM RATINGS
Symbol
Value
Unit
Drain-Source Voltage
VOSS
60
Vdc
Gate-Source Voltage
VGS
±20
Vdc
10
0.5
Adc
Po
0.83
Watts
TJ. Tstg
-55to +150
·C
Rating
Drain Current -
Continuous (1)
Total Power Dissipation @ TC = 25"(;
Operating and Storage Temperature Range
I
(11 The Power Dissipation of the package may result in
8
lower continuous drain current.
DIM
A
B
C
D
F
G
H
J
K
L
N
P
R
S
MILLIMETERS
MIN
MAX
5.33
4.32
4.44
5.21
3.18
4.19
0,56
0.41
0,41
0.48
1.14
1.40
2.54
2,41
2.67
12.70
6.35
2,67
2.03
2,92
3.43
0,41
0.36
INCHES
MIN MAX
0.170 0.210
0.175 0.205
0,125 0.165
0.016 0.022
0.016 0.019
0,045 0.055
0.100
0.095 0.105
0.500
0.250
0,080 0.105
0.115
.0,115..
0.014 0.016
-
-
AU JEDEC dimensions and nDtesapply.
CASE 29-02
TO-226AA
(TO-92)
MOTOROLA TMOS POWER MOSFET DATA
0-8
85170
ELECTRICAL CHARACTERISTICS (TA = 25'C unless otherwise noted.)
I
Characteristics
Symbol
I
Min
Typ
Max
Unit
60
90
-
Vdc
-
0.01
10
nAdc
0.8
2.0
3.0
Vdc
-
-
0.5
pA
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS = 0,10 = 100 pA)
V(BR)OSS
Gate-Body Leakage Current
(VGS = 15 V, VOS = 0)
IGSS
ON CHARACTERISTICS'
Gate Threshold Voltage
(VOS = VGS, 10 = 1.0 mAl
VGS(th)
On-State Drain Current
(VOS = 25 V, VGS = 0 V)
10(off)
1.8
5.0
Ohms
9fs
-
200
-
mmhos
Turn-On Time
(10 = 0.2 A) See Figure 1
ton
-
4.0
10
ns
Turn-Off Time
(10 = 0.2 A) See Figure 1
toff
-
4.0
10
ns
Static Drain-Source On-Resistance
(VGS = 10 V, 10 = 200 rnA)
rOS(on)
Forward Transconductance
(VOS = 10 V, 10 = 250 mAl
DYNAMIC CHARACTERISTICS
Input Capacitance
(VOS = 10 V, VGS
= 0, f =
1.0 MHz)
SWITCHING CHARACTERISTICS'
*Pulse Test: Pulse Width
~
300 J.lS, Duty Cycle
~
2%.
RESISTIVE SWITCHING
FIGURE 2 - SWITCHING WAVEFORMS
FIGURE 1 - SWITCHING TEST CIRCUIT
+ 25 V
Pulse Generator
,----..,
50
{l
20 dB
Attenuator
I
I
50 {l I
IL I t____ JI
50
{l
Output Vout
Inverted
(Vin Amplitude 10 Volts)
Input
Vin
MOTOROLA TMOS POWER MOSFET DATA
0-9
85170
FIGURE 3 -
VGS(th) NORMALIZED versus TEMPERATURE
FIGURE 4 _ ON·REGION CHARACTERISTICS
2.0
2.0
-~
-
VGS 1= 10 V
~ 1.6
~
~
5
1.2
~
~ 0.8
~
---
~ 0.4
II
VOS = VGS
10 = 1.0mA
----
r--
~
...z
1.6
~
o
FIGURE 5 -
z
u
r-- t--
;;;;
'"
0.8
§
0.4
§
50
100
TJ, JUNCTION TEMPERATURE
VGS
/'
1.6
~
!z
~ 1.2
az
~
:§ 0.4
FIGURE 6 -
= 10V
100
9.0 V
80
~
t':j
YI
6.OV
I--"""'"
60
~
u
40
20
4.0 V
~~
~ :;:......-- r~ ~ ,..--
6.OV
5.0 V
~
r--
4.0 V
4.0
CAPACITANCE versus DRAIN·TO·SOURCE VOLTAGE
1\
1\
1\
~
Ciss-
...... ,....,
.1
1\
Coss
I"'-10
20
30
Vos, ORAIN·TQ·SOURCE VOLTAGE (VOLTS)
-
a.ov
7.0V
VGS - 0 V
u
5.0 V
'f/
z
~
7.0V
'/
~~
I--
~
1.0
2.0
3.0
VOS, DRAIN·TO·SOURCE VOLTAGE (VOLTS)
8.0 V
U
~ 0.8
"2
150 1°C)
OUTPUT CHARACTERISTICS
2.0
:e
L
1.2
o
-50
./
~
40
10
Crss
20
30
40
50
VOS, ORAIN·TQ·SOURCE VOLTAGE (VOLTS)
MOTOROLA TMOS POWER MOSFET DATA
0-10
60
®
MFE910
MPF910
MOTOROLA
N·CHANNEL ENHANCEMENT·MODE
TMOS FIELD·EFFECT TRANSISTOR
60 VOLTS
This TMOS FET is designed for high-voltage, high-speed switching applications such as line drivers, relay drivers, CMOS logic,
microprocessor of TIL-to-high voltage interface and high voltage
display drivers.
• Fast Switching Speed • Low On-Resistance -
ton
N-CHANNEL TMOS
FET
= toff = 6.0 ns Typ
2.0 Ohms Typ
• Low Drive Requirement, VGS(th) = 2.5 V Max
• Inherent Current Sharing Capability Permits Easy Paralleling of
Many Devices
MFE91 0
1r
TMDS
s
CASE 79-02
TO-205AO
(TO-39)
MAXIMUM RATINGS
Symbol
Value
Unit
Drain-Source Voltage
Rating
VOSS
60
Vdc
Gate-Source Voltage
VGS
±15
Vdc
Drain Current -
10
10M
0.5
1.0
Adc
Total Power Dissipation @ TC = 25°C
MFE910
Derate a bove 25°C
Po
6.25
50
Watts
mWfC
Total Power Dissipation @ T A = 25°C
Derate above 25°C
MPF910
Po
1.0
8.0
Watts
mWfC
TJ, Tst!!
-55 to +150
°c
Continuous (11
Pulsed (2)
Operating and Storage Temperature Range
MPF910
(1) The Power Dissipation of the package may result in a lower continuous drain current.
12) Pul •• Width" 300 ,.s. Duty Cycl. " 2.0%.
CASE 29-03
TO-226AE
MOTOROLA TMOS POWER MOSFET DATA
0-11
MFE91O/MPF910
ELECTRICAL CHARACTERISTICS (TA
= 25°C unless otherwise
noted.)
Typ
Max
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
IVGS = 0, ID = 100,.,A)
V(BR)DSS
60
90
-
Zero Gate Voltage Drain Current
(VDS = 40 V, VGS = 0)
IDSS
-
0.1
10
,.,Adc
Gate-Body Leakage Current
(VGS = 10 V, VDS = 0)
IGSS
-
0.01
10
nAdc
Gate Threshold Voltage
(VDS = VGS, ID = 1.0 mAl
VGS(th)
0.3
1.5
2.5
Vdc
Drain-Source On-Voltage
IVGS = 10 V, ID = 500 mAl
VDS(on)
-
-
2.5
Vdc
On-State Drain Current
(VDS = 25 V, VGS = 10 V)
ID(on)
500
-
-
mA
Forward Transconductance
(VDS = 15 V, ID = 500 mAl
Qf.
100
-
-
mmhos
Vdc
ON CHARACTERISTICS
FIGURE 1 -
VGS(th) NORMALIZED versus TEMPERATURE
FIGURE 2 -
2.0
ON-REGION CHARACTERISTICS
2.0
-
VGS 1= 10V
~
1.6
VDS = VGS
ID = 1.0 mA
-r--
~
9 1.2
o
:I:
~
~ 0.8
,.
r---
~ 1.6
>-
~
r-- t---
u
2
;';!; 0.8
o
-50
FIGURE 3 -
2. 0
~
!z
~
100
~
~
150 1°C}
OUTPUT CHARACTERISTICS
1/
-- i - -
Coss
\
~~
40 ~
20
-35 -15
+5.0
25
45
6,5
85
105
125
o
o
145
t:::::",
TRANSFER CHARACTERISTIC
VOS=10V
FIGURE 6 -
/
2.1
~
!Z
1
0
/"
1.8
1.5
V
1.2
~ 0.9
""
~
OUTPUT CHARACTERISTIC
VGS = 10V-
~
9.0
~ 2.0
/
!z
~
a:
a
8.0
1.6
r'
7.0
2
6.0
~0.8
§
5.0
:§ 0.4
0.3
4.0
..... V
1.0
2.0
3.0
4.0
50
2.4
/
10.6
~
2.8
/
z
~
Ciss
r-
VOS. ORAIN.sOURCE VOLTAGE (VOLTS)
2.4
S
Crs•
w
u
TJ. JUNCTION TEMPERATURE 1°C)
FIGURE 5 -
-- -
--.::: ~
u 60
i--
0.1
-55
CAPACITANCE VARIATION
200
180
5.0
6.0
7.0
8.0
9.0
u
10
w
~
FIGURE 7 -
SATURATION CHARACTERISTIC
2.8
VGS = 10'y--
I-
2.4
/
9.0
/
/
~
~
4
2
~
~
~~
0.5
~
~
VOS.ORAIN-SOURCE VOLTAGE (VOLTS)
VGS. GATE·SOURCE VOLTAGE (VOLTS)
IV
.........
/
I::i'/'"
/'
8.0
V/
/
7.0
6.0
5.0
4.0
1.0
2.0
3.0
4.0
VDS. DRAIN·SOURCE VOLTAGE (VOLTS)
MOTOROLA TMOS POWER MOSFET DATA
0-16
5.0
50
®
MFE9200
MOTOROLA
200 VOLTS
N-CHANNEL ENHANCEMENT MODE
TMOS FIELD EFFECT TRANSISTOR
This TMOS FET is designed for high-voltage, high-speed switching applications such as line drivers, relay drivers, CMOS logic,
microprocessor or TIL-to-high voltage interface and high-voltage
display drivers.
• Fast Switching Speed • Low On-Resistance -
ton
=
toff
=
N-CHANNEL TMOS
FET
6.0 ns Typ
4.5 Ohms Typ
• Low Drive Requirement, VGS(th) = 4.0 V Max
• Inherent Current Sharing Capability Permits Easy Paralleling of
Many Devices
1r
GD---->.i.
TMOS
S
MAXIMUM RATINGS
Symbol
Value
Drain-Source Voltage
Rating
VOSS
200
Vdc
Gate-Source Voltage
VGS
±20
Vdc
Drain Current
Continuous (1)
Pulsed (21
10
10M
400
800
mAde
Total Power ~issipation
@TC = 25·C
Derate above 25·C
Operating and Storage
Temperature Range
Po
Unit
STYlE 12:
~N 1. SOURCE
2. GATE
3. ORAlN ICASEI
Watts
1.8
14.4
mWrC
-55 to 150
·C
DIM
A
B
TJ,Ts!R
(1) The Power Dissipation of the package may result in a [ower continuous drain current.
(2) Pulse Width ~ 300 P.s, Duty Cycle:::;;; 2.0%.
e
0
E
f
G
H
J
K
L
M
N
P
MILLIMETERS
MIN
MAX
INCHES
MIN
MAX
5.84
0.209 0.230
0.178 0.195
4.95
0.170 0.210
5.33
0.533 0.016 0.021
0.030
0.762
0.406 0.483 0.01' 0.019
0.100
BSe
2.54 BSC
0.914 1.17
0.036 0.046
0.711 1.22
0.028 0.048
10.5UU
12.70
6.35
O. 50
45u _BSC
45' BSC
0.050 B.C
1.27 BSC
1.27
0.050
5.31
4.52
4.32
0.406
-
All JEDEC notes and dimensions apply.
CASE 22-03
TO-206AA
(TO-1S)
MOTOROLA TMOS POWER MOSFET DATA
0-17
MFE9200
ELECTRICAL CHARACTERISTICS (TA = 25'C unless otherwise noted.)
I
Symbol
Min
Drain-Source Breakdown Voltage
(VGS = 0, 10 = 10!lA)
V(BR)OSS
200
Zero Gate Voltage Drain Current
(VOS = 200 V, VGS ~ 0)
lOSS
Gate-Body Leakage Current
(VGS = 15 Vdc, VOS = 0)
Characteristic
Typ
Max
Unit
-
-
Vdc
OFF CHARACTERISTICS
0.1
10
!lAde
IGSS
-
0.Q1
50
nAdc
VGS(th)
1.0
-
4.0
Vdc
ON CHARACTERISTICS·
Gate Threshold Voltage
(VOS = VGS, 10 = 1.0 rnA)
Drain-Source On-Voltage (VGS
(10 = 100 rnA)
(10 = 250 rnA)
(10 = 500 rnA)
=
10 V)
VOS(on)
On-State Drain Current
(VOS = 25 V, VGS = 10 V)
State Drain~Source
(VGS = 10 Vdc)
(10 = 100 rnA)
(10 = 250 rnA)
(10 = 500 rnA)
10(on)
On~Resistance
Vdc
-
0.45
1.20
3.0
400
700
0.6
1.60
-
rnA
Ohms
rOS(on)
-
4.5
4.8
6.0
200
400
-
Cjss
-
72
90
pF
Coss
-
15
20
pF
erss
-
2.8
3.5
pF
Turn-On Time
See Figure 1
ton
-
6.0
15
ns
Turn-Oft Time
See Figure I
toft
-
6.0
15
ns
Forward Transconductance
(VOS = 25 V, 10 = 250 rnA)
9fs
6.0
6.4
mmhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(VOS = 25 V, VGS
= 0, f =
1.0 MHz)
Output Capacitance
(VOS = 25 V, VGS
= 0, f =
1.0 MHz)
Reverse Transfer Capacitance
(VOS = 25 V, VGS = 0, f = 1.0 MHz)
SWITCHING CHARACTERISTICS'
* Pulse Test:
Pulse Width
~
300
IJ.~,
Duty Cycle.:;;; 2.0%.
RESISTIVE SWITCHING
FIGURE 1 -
FIGURE 2 -
SWITCHING TEST CIRCUIT
+25 V
23
Pulse Generator
[-,p-IF~
L-J-_~
-=.
Vin
i}T,;:1'
:'
·1' M
-=':"
To Sampling Scope
n Input
r-20idE''"1_-fl~::..::~;50Vout
Output Vout
Inverted
-=
Input Vin
MOTOROLA TMOS POWER MOSFET DATA
0-18
SWITCHING WAVEFORMS
MFE9200
FIGURE 3 -
FIGURE 4 -
ON VOLTAGE versus TEMPERATURE
10
200
~ 5.0
160
~
180
~
VGS = 10 V
::l
-
~ 2.0
~
~ 1.0
~
~ 0.5
~
-
~ f--
250 mA
.....
I---
~140
~120
z
~100
100 mA
~'-'
t---
80
U 60
>--
VGS = 0 V
,r
Ciss f - -
\
40
1\ r--.....
20
0.2
0.1
-55
-35 -15
+5.0
25
45
65
85
105
125
o
o
145
FIGURE 5 -
10
~
i
VGS = 10 V
10/
O. 6
en
0.6
a 0.4
/
z
~ 0.3
o
gO.2
1$
:os
t-
/
2.0
3.0
4.0
50
/
II
V
5.0 V
1/
'/
/1
az 0.3
4.0V
-
'5
SEClA''''
MAXIMUM RATINGS
Rating
Symbol
MPF930
MPF960
MPF990
Unit
60
90
Vdc
60
90
Vdc
VDSS
35
Drain-Gate Voltage
VDGO
35
Gate Source Voltage
VGS
Drain~Source
Voltage
Vdc
±30
Total Power Dissipation
ID
IDM
2.0
3.0
PD
1.0
Watts
8.0
mW/OC
TJ, Tstg
-55 to 150
°C
8JA
125
°C/W
@TA=25°C
Derate above 25°C
Operating and Storage
N
N
Ill.r 0.10(0.004)@ITIA@ls@!
'4. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5 1973.
Temperature Range
Thermal Resistance
~IR
C
P1!f - . -
NOTES:
1. DIMENSIONS ·A· AND ·S· ARE DATUMS.
2. ·T· ISSEATING PLANE.
3. POSITIONAL TOLERANCE FOR LEADS:
Adc
Drain Current
Continuous (1)
Pulsed (2)
STYLE 22:
PIN 1. SOURCE
2. GATE
3. DRAIN
(1) The Power Dissipation of the package may result in a lower continuous drain current.
(2) PulsQ Width ~ 300 ps. Duty Cycle =;;;; 2.0%.
MILLIMETERS
MIN MAX
7.37
7.87
4.44
5.21
3.18
4.19
0.61
0.46
1.27 SSC
2.54 SSC
12.70
2.03
2.92
3.43
R
0.46
0.61
S
DIM
A
B
C
D
G
J
K
N
-
INCHES
MIN
MAX
0.290 0.310
0.175 0.205
0.125 0.165
0.018 0.024
0.050 SSC
'0.100 SSC
0.500
0.080 0.115
0.135
0.G18 0.024
CASE 29-03
TO·226AE
MOTOROLA TMOS POWER MOSFET DATA
0-22
-
MPF930,960,g90
ELECTRICAL CHARACTERISTICS (TA = 25'C unless otherwise noted)
I
Characteristic
Symbol
I
Min
Typ
Max
35
SO
90
-
-
Unit
OFF CHARACTERISTICS
Drain-Source Breakdown Voltage
(VGS = 0,10 = 10 fLA)
V(BR)OSS
MPF930
MPF960
MPF990
Vdc
Zero Gate Voltage Drain Current
(VOS = Maximum Rating, VGS = 0)
lOSS
-
-
10
fLAdc
Gate-Body Leakage Current
(VGS = 15 Vdc, VOS = 0)
IGSS
-
-
50
nAdc
Gate Threshold Voltage
(ID = 1.0 mA, VOS = VGS)
VGS(th)
1.0
-
3.5
Vdc
Drain-Source On-Voltage (VGS = 10 V)
(lD = O.5A)
MPF930
MPF9S0
MPF990
VDS(on)
-
0.4
0.5
0.5
0.7
0.8
.1.0
-
0.9
1.2
1.2
1.4
1.7
2.0
2.2
2.8
2.8
3.0
3.5
4.0
-
0.9
1.2.
1.2
1.4
1.7
2.0
ON CHARACTERISTICS'
liD = 1.0A)
MPF930
MPF960
MPF990
liD = 2.0 A)
MPF930
MPF960
MPF990
Static Drain-Source On-Resistance
MPF930
(VGS = 10 Vdc, ID = 1.0 Adc)
MPF960
MPF990
Vdc
-
-
rOS(on)
Ohms
-
On State Drain Current
(VDS ~ 25 V, VGS = 10 V
ID(on)
1.0
2.0
-
Amps
Forward Transconductance
91s
200
380
-
mmhos
Ciss
-
SO
70
pF
Coss
-
49
60
pF
Crss
-
13
18
pF
Turn-On Time
See Figure 1
ton
-
7.0
15
ns
Turn-OIl Time
See Figure 1
toll
-
7.0
15
ns
(VDS = 25 V, 10 = 0.5 A)
DYNAMIC CHARACTERISTICS
Input Capacitance
(VOS = 25 V, VGS
= 0, I =
1 MHz)
Output Capacitance
(VDS = 25 V, VGS
= 0, I =
1 MHz)
Reverse Transfer Capacitance
(VOS = 25 V, VGS = 0, I = 1 MHz)
SWITCHING CHARACTERISTICS'
* Pulse Test: Pulse Width:!:;; 300
~s,
Duty Cycle
:!EO
2%.
RESISTIVE SWITCHING
FIGURE 1 -
SWITCHING TEST CIRCUIT
FIGURE Z -
+25 V
23 (}
Pulse Generator
To Sampling Scope
r-20~I~_-e~=-=3-;50 VnoutInput
r----.,
I
I
I
Output V out
Inverted
Input Vin
MOTOROLA TMOS POWER MOSFET DATA
0-23
SWITCHING WAVEFORMS
•
MPF930, 960, 990
FIGURE 3 - ON VOLTAGE versus TEMPERATURE
FIGURE 4 -CAPACITANCE VARiATION
10
200
180
~
5.0
o
~
w
~
g
-
-VGS = 10V
2.0
~ 1.0
~ 0.5
z
~",,0.2
-- --
1
~140
~'00
<5
060
40
\
~~
-........;:
u
;:: 80
>--
Coss
\
~ 120
z
........
0
- 35 -15
+5.0
25
45
65
85
105
125
FIGURE 5 - TRANSFER CHARACTERISTIC
VOS = 10V
/"
iii
"
VGS = 10 V-
lC 2.4
~
>-
i:'i
~
3.0
7.0
~ 1.2
c
6.0
o
90.4
5.0
~0.8
/
2.0
8.0
1.6
u
/
1.0
2.0
::>
1/
/
9.0
:;;
/
0.3
4.0
V
4.0
50
40
2.B
V
~0.6
~
FIGURE 6 - OUTPUT CHARACTERISTIC
/
2.1
~ 0.9
a:
~
Ciss
to-
VOS, ORAIN SOURCE VOLTAGE (VOLTS)
2.4
:z 1.5
~
B
1.2
Crss
-- -
w
u
145
TJ, JUNCTION TEMPERATURE (OC)
~ 1.8
~
!\..
0
?
0.1
- 55
VGS = 0 V
160
~
5.0
6.0
7.0
B.O
9.0
u
10
w
~
FIGURE 7 - SATURATION CHARACTERISTIC
2.8
VGS
lC 2.4
:E
v../"
a
h ./"
tv../"
g§ 1.6
~ 1.2
8.0
7.0
~ ,../
6.0
V/
z
I--
9.0
,..-
i:'i
90.4
O. 2
10~
L
~2.0
>-
o
=
.;-
-,-0.8
A V
5.0
~
~V
4.0
:til
0.5
~
40
VOS,ORAIN-SOURCE VOLTAGE (VOLTS)
VGS, GATE·SOURCE VOLTAGE (VOLTS)
1.0
3.0
2.0
4.0
VOS. ORAIN·SOURCE VOLTAGE (VOLTS)
MOTOROLA TMOS POWER MOSFET DATA
0-24
5.0
50
®
MPF9200
MOTOROLA
200 VOLTS
N-CHANNEL ENHANCEMENT-MODE
TMOS FIELD-EFFECT TRANSISTOR
N-CHANNEL TMOS
FET
This TMOS FET is designed for high voltage, high speed switching
applications such as line drivers, relay drivers, CMOS logic, microprocessor or TTL to high voltage interface and high voltage display
drivers.
•
Fast Switching Speed -
•
Low On-Resistance -
ton = toft = 6.0 ns typ
4.5 Ohms typ
•
Low Drive Requirement, VGSlth) = 4.0 V max
•
Inherent Current Sharing Capability Permits Easy Paralleling of
Many Devices
,r
STYLE 30:
PIN 1. DRAIN
2. GATE
3. SOURCE
G 0----'./
TMOS
MAXIMUM RATINGS
Rating
Drain~Source
Symbol
Voltage
Value
Unit
Vde
VOSS
200
Gate-Source Voltage
VGS
±20
Vde
Drain Current -
10
10M
400
800
mAde
Po
0.6
4.8
Watts
mW/oC
TJ, Tstg
-55 to 150
°C
OJA
208
°C/W
Continuous (1)
Pulsed (2)
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Operating and Storage Temperature Range
Thermal Resistance Junction to Ambient
NOTES:
I. CONTOUR OF PACKAGE BEYOND ZONE "P"
IS UNCONTROLLED.
2. DIM "F" APPLIES BETWEEN "H" AND
"L". DIM "0" & "S" APPLIES BETWEEN
"L" & 12.70 mm (0.5") FROM SEATING
PLANE. LEAO OIM IS UNCONTROLLED
IN "H" & BEYOND 11.70 mm (0.5")
FROM SEATING PLANE.
(1) The Power Dissipation of the package may result in a lower continuous drain current.
(2) Pulse Width';:;; 300 p.S, Duty Cycle:;:;; 2.0%.
DIM
A
B
C
D
F
G
MILLIMETERS
MIN MAX
4.32
5.33
4.44
5.21
3.18
4.19
0.41
0.56
0.41
0.48
1.14
1.40
2.54
H
J
K
L
N
P
R
S
2.41
12.70
6.35
2.03
2.92
3.43
0.36
2.67
2.92
0.41
INCHES
MIN
MAX
0.170 0.210
0.175 0.205
0.125 0.165
0.016 0.022
0.016 0.019
0.045 0.055
0.100
0.095 0.105
0.500
.250
0.080 0.115
0.115
0.135
.0.014 0.Q16
-
All JEDEC dimensions and notes apply.
CASE 29-02
(TO-92)
MOTOROLA TMOS POWER MOSFET DATA
0-25
MPF9200
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted.)
I
1
. .1
Symbol
Min
Typ
Max
Orain-Source Breakdown Voltage
(VGS = 0.10= lOI'A)
V(BR)OSS
200
-
-
Zero Gate Voltage Orain Current
(VOS = 200 V. VGS = 0)
lOSS
-
0.1
10
I'Ade
Gate-Body Leakage Current
(VGS = 15 Vde. VOS = 0)
IGSS
-
0.01
50
nAde
-
4.0
Vde
Characteristic
Unit
I..
OFF CHARACTERISTICS
Vdc
ON CHARACTERISTICS'
Gate Threshold Voltage
(10 = 1.0 rnA. VOS = VGS)
1.0
VGS(th)
Ora in-Source On-Vollage (VGS
(10 = 100 rnA)
(10= 250 rnA)
(10= 500 rnA)
=10 V)
Vde
VOS(on)
-
0.45
1.20
3.0
-
On State Drain Current
400
10(on)
700
0.6
1.60
-
rnA
(VOS = 25 V. VGS = 10 V
Static Drain-Source On-Resistance
(VGS = 10 Vde)
(10= 100 rnA)
(10= 250 rnA)
(10= 500 rnA)
Ohms
rDSlon)
-
4.5
4.8
6.0
6.0
6.4
9fs
200
400
-
mmhos
Input Capacitance
OVOS = 25 V. VGS = O. f = 1.0 MHz)
Ciss
-
72
90
pF'
Output Capacitance
(VOS = 25 V. VGS = O. f = 1.0 MHz)
Coss
-
15
·20
pF
Reverse Transfer Capacitance
(VDS = 25 V. VGS = O. f = 1.0 MHz)
erss
-
2.8
3.5
pF
Turn-On Time
See Figure 1
Ion
-
6.0
15
ns
Turn-Off Time
See Figure 1
toff
-
12
15
ns
-
Forward Transconductance
(VOS 25 V. 10 = 250 rnA)
=
DYNAMIC CHARACTERISTICS
SWITCHING CHARACTERISTICS'
"Pulse Test: Pulse Width
~
300 ",5, Duty Cycle ~ 2%.
RESISTIVE SWITCHING
FIGURE 1 -
FIGURE 2 -
SWITCHING TEST CIRCUIT
+25V
Pulse Generator
c----,
... )
1
~500'.!---1-
1)
1L.. _ _ _ .J
'='
i
Vj"
---
500
-=
46 0
To Sampling Scope
n Inpul
r:-:-:20idiil~_,~=-=-:t-;50Vout
1
Output Vout
Inverted
Input Vin
MOTOROLA TMOS POWER MOSFET DATA
D-26
SWITCHING WAVEFORMS
MPF9200
FIGURE 3 - ON VOLTAGE versus TEMPERATURE
FIGURE 4 - CAPACITANCE VARIATION
10
200
~
180
~ 5.0
w
--
VGS - 10 V
C>
~
2.0
0
>
~
1.0
-
250 mA
-
~
140
~
120
~
80
z
~ 100 ~
I--
100 mA
VGS = 0 V
160
u
1\
~
40
0.2
20
0.1
- 55
- 35
-15
+5.0
25
45
65
85
105
125
o
0.7
U>
~ 0.6
;=
a5
I
VOS= 10V
05
r·
//
./
::;;
,:; o. 5
t.
z>-
1/
~ o. 4
a
II
~ o. 3
4.0 V'
o
o
/
O. 1
£>
o.
/
1.0
2.0
5.0 V
/
O. 6
I. ,/
//
~O. 2
.9 0.2
50
V
10 V
ir
/
3
0
/
/
0.4
c;;-
40
30
FIGURE 6 - OUTPUT CHARACTERISTIC
o. 7
I
a
Source Exif Data:
File Type : PDF
File Type Extension : pdf
MIME Type : application/pdf
PDF Version : 1.3
Linearized : No
XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Create Date : 2018:02:28 08:48:19-08:00
Modify Date : 2018:02:28 09:24:26-08:00
Metadata Date : 2018:02:28 09:24:26-08:00
Producer : Adobe Acrobat 9.0 Paper Capture Plug-in
Format : application/pdf
Document ID : uuid:b0367c85-25c8-0a4f-9f9a-c285ac00e874
Instance ID : uuid:857058cb-bf2d-ce43-aa94-e8c2aafe23de
Page Layout : SinglePage
Page Mode : UseNone
Page Count : 499
EXIF Metadata provided by EXIF.tools