1984_Exar_Databook 1984 Exar Databook
User Manual: 1984_Exar_Databook
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Disclaimer
Exar reserves the right to make changes in the products contained in this book in order to improve design or performance and to supply the best possible products. Exar also assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representations that the circuits are
free from patent infringement. Applications for any integrated circuits contained in this publication are for illustration
purposes only and Exar makes no representation or warranty that such applications will be suitable for the use specified without further testing or modification. Reproduction of any portion hereof without the prior written consent of
Exar is prohibited.
750 Palomar Avenue
Sunnyvale, CA 94086
Telephone (408) 732·7970
TWX: 910·339·9233
EXAR Corporation
750 Palomar Avenue
Sunnyvale, CA 94086
Telephone (408) 732·7970
TWX: 910·339·9233
Introduction
Introduction
This Data Book contains a complete summary of technical information covering Exar's full line of standard,
semi-custom, and custom IC products. Each of the
products presented covers a wide range of applications, greatly simplifying most system designs. To help
the designer find the right device for his application,
the products are grouped by function, and a convenient
cross-reference chart is provided to show Exar's direct
replacement for a number of popular industry products.
EXPERIENCE AND PRODUCTS
Exar's innovativeness, product quality, and responsiveness to customer need, has been the key to its success. Exar offers a broad line of linear and interface circuits. In the field of standard linear IC products, Exar
has extended its circuit technological leadership into
the areas of communications and control circuits. Today, Exar has one of the most complete lines of oscillators, timing circuits and phase-locked loop ICs in the
industry. Exar also manufactures a large family of
telecommunication circuits, such as tone decoders,
compandors, modulators, PCM repeaters, and FSK and
PSK modem circuits. In the field of industrial control circuits, Exar manufactures a broad line of quad and dual
operational amplifiers, voltage regulators, radio-control
and servo driver ICs, and power control circuits.
Exar's experience and expertise in the area of bipolar,
CMOS and 12L IC technology extends into both custom
and standard IC products. In the area of custom ICs,
Exar has designed, developed, and manufactured a
wide range of full custom monolithic circuits, particularly for applications in the areas of telecommunications, consumer electronics, and industrial controls.
In addition to the full custom capability, Exar also offers
a unique semi-custom IC development capability, for
low to medium volume requirements. This semi-custom
program is intended for those customers seeking costeffective solutions; reducing component count and
board size in order to compete more effectively in a
changing marketplace. The program allows a customized monolithic IC to be developed with a turnaround
time of several weeks, at a small fraction of the cost of
a full custom development program.
EXCELLENCE IN ENGINEERING
Exar quality starts in Engineering where highly qualified
people are backed up with the advanced instruments
and facilities needed for design and manufacture of
custom, semi-custom and standard integrated circuits.
Exar's engineering and facilities are geared to handle
all three classes of IC design: (1) Semi-custom design
programs using Exar's bipolar and 12L Master Chips; (2)
Full custom IC design, and (3) Development and highvolume production of standard products.
Some of the challenging and complex development programs successfully completed by Exar include analog
compandors and PCM repeaters for telecommunication, electronic fuel-injection, anti-skid braking systems, and voltage regulators for automotive electronics, digital voltmeter circuits, 40-MHz frequency synthesizers, high-current, high-voltage display and relay
driver ICs, and many others.
NEW TECHNOLOGIES
Through company sponsored research and development activities, Exar constantly stays abreast of all
technology areas related to changing customer needs
and requirements. Exar has a complete design engineering group dedicated to new technology.
FIRST IN QUALITY
From incoming inspection of all materials, to the final
test of finished goods, Exar performs sample testing of
each lot to ensure that every product meets Exar's high
quality standards. Exar's manufacturing process is inspected or tested in accordance with its own stringent
Quality Assurance Program, which is in compliance
with MIL-I-4520B. Additional special screening and testing can be negotiated to meet individual customer
requirements.
Throughout the wafer fab and assembly process, the
latest scientific instruments, such as scanning electron
microscopes, are used for inspection, and modern automated equipment is used for wafer probe, ac, dc, and
functional testing. Environmental and burn-in testing of
finished products is also done in-house. For special environmental or high-reliability burn-in tests, outside testing laboratories are used to complement Exar's own extensive in-house facilities.
FIRST IN SERVICE
Exar has the ability and flexibility to serve the customer
in a variety of ways, from wafer fabrication to full parametric selection of assembled units for individual customer requirements. Special marking, special packaging, and military screening, are only a few of the service
options available from Exar. We are certain that Exar's
service is flexible enough to satisfy 99% of your needs.
The company has a large staff of Applications Engineers to assist the customer in the use of the product,
and to handle any request, large or small.
Standard Products
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STANDARD PRODUCTS
Phase-Locked Loops
Fundamentals of Phase-Locked Loops ........................................................ 1-5
Applications of PPL IC's .....•. " . . . . . . . . . • • . . . . . • . . . . . • . . • . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Choosing the Right PLL Circuit ..........•.•......•.......................................... 1-8
XR-210 ............. , .........•..........•...•..•..•.................................... 1-9
XR-215 ................................................................................ 1-14
XR-2211 ..•............................................................................ 1-23
XR-2212 .............•.••....•.•..•.................................................... 1-31
XR-2213 ...............•.............•................................................. 1-38
Tone Decoders
XR-567 ................•.•..•. ,', .. ,,",.',.,',," .. , .. " .. ',.,',.,""""""""',., 1-43
XR-567A " . " " , . " , . " " " " " " " . " " . " " " " " . " " " " . " " " " " " " , .. " ... "., 1-53
XR-L567 "."",.""" .• " " " . " " . " , . " " " " , .. ".".".""."." .. """"",." 1-55
XR-2567 "."",."", .. ", .. , . " , . " . " " , . " " " " " " " " " " " . , .. ", .. ".,., .. "" 1-62
Filters
XR-l000/1008 .• ",.,.""" .. ,.""."""""" •. """"".".".".",." .. ".,." .. 1-71
XR-2103 "",.""""."",." .. ".".""",."."",.".,.,.,.",.".""""", .. ,. 1-73
XR-2120 " , . , . " " " " " " . " " " . " " " . " " " " " . , .. " " " " " " . " " " . , . " , .. ", .. 1-78
XR-2120A "',.""'"."., ... ".,',.,,.,"',.,"',.,"""',.,.,.,", ....... ,., .. , ..... 1-84
Modem Circuits
Modem Basics, • , , , , , ". , , , , . , . , , , , ... , , , , . , , . , ,,' ... , .. , , .. " , , , " , . , , , , , " , , , , " " , " , , 1-87
XR-14412 , . " " " . " . " . " " " , . " , . " . " " , . " " . " " " " " " " " . " . " " " , . " " " ... 1-93
XR-2121/2122 ."',',.".,,.,"""'.',.,"".",.,',.,', .. ,"', .. ,., .. ,""',.,,",",. 1-99
XR-2123 "."',,.,' ," , '. , , , , , '. , , • , . " , ,. , , , , .,' , , , ,. , , , , , ,. , ". , ,. , . ,., . , , . , , " , , , , , , , 1-103
XR-2125 " " " " " , .•• ,."""".",.",.""",.",.""".",.", ... ""."".",.", 1-109
Interface Circuits
XR-1488/1489A " " " " " " " " " " " " ' " , " " " " " " " " " " " " " " " " " " " " " " " 1-111
Dis k Drive Circuits
XR-2247/2247A "",."""""."".,." .. , .• " " " , . " " " . " " , . " . " . " " " " " " " . 1-114
XR-3470A/3470B "".""".",.",."".",." .. ", .. " " , . " . " , . " " " " " " . " " " " 1-121
Timing Circuits
Fundamentals of IC Timers .. ,""',.,.,""",.,"""", ... "., .. ".,"".,""',.,"",., 1-128
Choosing the Right IC Timer, , , , , , .• " , , , . , ,. ". , ,. , , '" , , ". , ,. , , , , , , , ,. , . , , " , , " " ,. , , , , , 1-131
1-1
STANDARD PRODUCTS
(CONTINUED)
XR·320 .••...•.....•................................................................... 1·134
XR·555 .............................................•.................................. 1·139
XR·L555 .......................................................••.....•................ 1·142
XR·556 ...................•............................................................ 1·146
XR·L556 ............................................................................... 1·149
XR·558/559 ...............•...................•........................................ 1·155
XR·2556 ............................................................................... 1·159
XR·2240 .....................•......•.................................................. 1·168
XR·2242 ............................................................................... 1·176
XR·2243 ............................................................................... 1·180
Function Generators
Fundamentals 01 Monolithic Wavelorm
Generation and Shaping .........•......................................................... 1·184
Choosing the Right IC Oscillator ............................................................. 1·186
XR·205 ................................................................................ 1·188
XR·2206 .........•..................................................................... 1·193
XR·2207 ............................................................................... 1·199
XR·2209 ............................................................................... 1·208
XR·8038 ............................................................................... 1·213
XR·8038A ......•....................................................................... 1·217
Multipliers/Modulators
XR·2208 ..........•...................................•................................ 1·219
XR·2228 .•............................................................................. 1·22,7
Display Drivers
XR·2271 ............................................................................... 1·236
XR·2272 ............................................................................... 1·238
XR·2276 ...............•............................................................... 1·241
XR·2277/2278 .......................................................................... 1·246
XR·2279 ............................................................................... 1·251
XR·2284/2288 .....................•.................................................... 1·255
XR·6118/6128 .......................................................................... 1·259
Operational Ampliliers
Fundamentals 01 Operational Amplifiers ....................................................... 1·262
Delinitlons 01 Operational Amplifier Terms .......•............................................. 1·263
Basic Applications 01 Operational Ampilliers ................................................... 1·264
Choosing the Right Op Amp ................................................................ 1·270
XR·082/083 ............................................................................. 1·272
XR·084 ................................................................................ 1·275
1·2
STANDARD PRODUCTS
(CONTINUED)
XR"094/095 .•.••.•...••..•.•.....•...••..••...••.•••...•..••....•......•.......•..•.... 1-277
XR-096 ••••.••.•.•••.••..•..•••..••....•..•••..•...•...••.••.....•......•......•..••... 1-279
XR-146/246/346 ........................................................................ 1-281
XR-1458/4558 .•..•...•.•••.••..••...•••.•.....•.••...••.•.•....•.....•••..•••.•..••...• 1-285
XR-3403/3503 ..•..•..••..•...•...••..••.•••...••...•...........•••..........•..•.••.... 1-287
XR-4136 .••.•..•.•...••..•..••...•...••..••...••.••.......••....•••.....•..•...•..••..• 1-290
XR-4202 .•..•••..•......••..•••..••..••.•••...••.••....•..••.....•.............•...•... 1-293
XR-4212 ...••.•..•..•..•••.••..••...••...•...••.•....••.•••....•.....••.......•..•....• 1-297
XR-4739 .•..•.••.•...•..••.••..•.•..••..•••..••.•••..••.•.••..••••....••..•.•.....••... 1-300
XR-4741 .•..•.••.•...••.••.••....••..••.•••...•..••...•.........•••.....•......•..••..• 1-303
XR-5532/5532A .••....••..•..•••..••..•.•...•••.•.......•..••.......................••.. 1-306
XR-5533/5533A ••.•.....••.•••..••...••..••...••.•...•....••.......•...••..•.•..•.•....• 1-310
XR-5534/5534A ••.•......•••••..•••..•••.••...••.•••.•.•.•••....••••...•••......•..•.... 1-314
VoHage Regulators
XR-1468/1568 ...•..•.....•....•...•........•...•..•...•.......................•..•...•. 1-318
XR-494 ..........•..•......•.......••..•.......•............•••....•....•.............. 1-320
XR-495 ....•........•.....•....•.......•....•..•....••..•.•.•......•...............•... 1-324
XR-1524/2524/3524 ..................................................................... 1-328
XR-1525A/2525A/3525A
XR-1527A12527A/3527A .••......•...•.......................•............................ 1-336
XR-1543/2543/3543 .•................................................................... 1-343
XR-2230 •.......•...•.••..•...•....•.......••..•.......•..•............•...•.....•...•. 1-351
XR-4194 ..•..•.••.•...•..•..•...........••......•....••.••...••.....•...•.............. 1-358
XR-4195 ........•..•..•..•..••...•...••..•....•..••..••.•....••.....•....•......•...... 1-361
High Current Drivers
XR-2001/2002/2003/2004 .......•.......•...•..........•...............•...•••........... 1-364
XR-2011/2012/2013/2014 ..•..•.......•........•..•.......••..••......•.................. 1-368
XR-2200 ..•....•.•....•.••.••..•....•........•.........•..•••••................•..•.... 1-372
XR-2201/2202/2203/2204 .•..••.......•................•..•.••••.....•....•.........•...• 1-374
Special Functions
XR-S200 •.....•.•.....••.•....•....••.....•...••.••...•........•......•....•..•..•..•.. 1-376
XR-1310 ...•....•..•...•.•....•...••..•..••...••.••...•.•......•.....•...•......•...•.. 1-385
XR-2264/2265 .•.......••.•....•...••..•..••...•..••..••.•...•.•.....•.................. 1-387
XR-2266 ••••.••.•.••.•••.•..•••..••.•••.••..••.•...••..•..••••.....•..........•......•. 1-390
XR-9201 .••.......•...•..•..•.......••......•..•.......•..•••••....•.............••...• 1-398
XR-4151 .••..•.•.....••..•..••......•.......••.•...•...•..•••....••........•.....•..... 1-406
XR-7000 ..•..•...•...••..•.••...•...•.......•..•...•..••..••.....•.........•..•..•..... 1-411
1·3
STANDARD PRODUCTS
(CONTINUED)
XR·2216 ............................................................................... 1·413
XR·13600 .............................................................................. 1·417
Repeaters
XR·C240 ...............................................................................
XR·C262 ...............................................................................
XR·C277 ...............................................................................
XR·C587/C588 ..........................................................................
XR· 15600115620 ........................•...............................................
XR·15640 ..............................................................................
XR·15650 ..............................................................................
XR·15660 ..............................................................................
XR·15700115720 ........................................................................
XR·15740 ..............................................................................
XR·15750 ..............................................................................
XR·15760 ..............................................................................
1·4
1·428
1~430
1·432 '
1·434
1·440
1·447
1·449
1·451
1·453
1·460
1·462
1·464
Phased-Locked Loops
Fundamentals of Phase-Locked Loops
is always smaller than the lock range and is related to
the low-pass filter bandwidth. It decreases as the filter
bandwidth is reduced.
The phase locked loop provides frequency selective
tuning and filtering without the need for coils or inductors. As shown in Figure 1, the PLL in its most basic
form is a feedback system comprised of three basic
functional blocks: a phase comparator, low-pass filter
and voltage controlled oscillator (VeO).
The lock and the capture ranges of a PLL can be illustrated with reference to Figure 2, which shows the typical frequency-to-voltage characteristics of a PLL. In the
figure, the input is assumed to be swept slowly over a
broad frequency range. The vertical scale corresponds
to the loop error voltage.
The basic principle of operation of a PLL can briefly be
explained as follows: With no input signal applied to the
system, the error voltage Vd is equal to zero. The veo
operates at a set frequency, fo, which is known as the
free-running frequency. If an input signal is applied to
the system, the phase comparator compares the phase
and frequency of the input signal with the veo frequency and generates an error voltage, Ve(t), that is related
to the phase and frequency difference between the two
signals. This error voltage is then filtered and applied to
the control terminal of the veo. If the input frequency,
fs, is sufficiently close to fo, the feedback nature of the
PLL causes the veo to synchronize, or lock, with the
incoming signal. Once in lock, the veo frequency is
identical to the input signal, except for a finite phase difference.
In the upper part of Figure 2, the loop frequency is being gradually increased. The loop does not respond to
the signal until it reaches a frequency f 1, corresponding to the lower edge of the capture range. Then, the
loop suddenly locks on the input, causing a negative
jump of the loop error voltage. Next, Vd varies with
frequency with a slope equal to the reciprocal of the
veo voltage-to-frequency conversion gain, and goes
through zero as fs = fo . The loop tracks the input until
the input frequency reaches f2' corresponding to the
upper edge of the lock range. The PLL then loses lock,
and the error voltage drops to zero.
If the input frequency is now swept slowly back, the cycle repeats itself as shown in the lower part of Figure 2.
The loop recaptures the signal at f3 and traces it down
to f4. The frequency spread between (f1, f3) and (f2, f4)
corresponds to the total capture and lock ranges of the
system; that is, f3 - f1 = capture range and f2 - f4 =
lock range. The PLL responds only to those input signals sufficiently close to the veo frequency, fo, to fall
within the "lock" or "capture" range of the system. Its
performance characteristics, therefore, offer a high degree of frequency selectiVity, with the selectivity characteristics centered about fo .
Two key parameters of a PLL system are its lock and
capture ranges. They can be defined as follows:
Lock range: The range of frequencies in the vicinity of fo ,
over which the PLL can maintain lock with an input signal. It is also known as the tracking or holding range.
Lock range increases as the over-all gain of the PLL is
increased.
Capture range: The band of frequencies in the vicinity of
fo where the PLL can establish or acquire lock with an
input signal. It is also known as the acquisition range. It
t--NL--I
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LOCK RANGE
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CAPTURE
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RANGE
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Figure 1. The basic phase locked loop consists of three functional blocks: a phase comparator, a low pass finer
and a vonage-controlled oscillator.
FREQUENCY
FREQUENCY
Figure 2. Typical PLL frequency-to-vonage transfer characterIstics are shown for increasing (upper diagram) and
decreasing (lower diagram) input frequency.
1-5
Applications of PLL Ie's
The basic concept of the phase locked loop (PLL) has
been around since the early 1930's and has been used
for a variety of applications in instrumentation and
space telemetry. However, before the advent of monolithic integration, cost and complexity considerations
limited its use to precision measurements requiring
very narrow bandwidths. In the past few years, the advantages of monolithic integration have changed the
phase locked loop from a specialized design technique
to a general-purpose building block. Therefore, what is
"new" at this pOint is not the concept of the PLL, but its
availability in a low-cost self contained monolithic Ie
package.
Applications for PLLs Abound
As a versatile building block, the PLL covers a wide
range of applications. Some of the more important are
the following:
FM demodulation: In this application, the PLL is locked on
the input FM signal, and the loop-error voltage, Vd(t) in
Figure 1 (see Box), which keeps the veo in lock with
the input signal, represents the demodulated output.
Since the system responds only t6 input signals within
the capture range of the PLL, it also provides a high degree of frequency selectivity. In most applications the
quality of the demodulated output (i.e., its linearity and
signal/noise ratio) obtained from a PLL is superior to
that of a conventional discriminator.
In many ways, this is similar to the case of the monolithic operational amplifier, which, until less than a decade
ago, was an expensive building block. Today, with the
advent of monolithic technology, it has become a basic
building block in .nearly every system design. The
monolithic phase locked loop also offers a similar potential. In fact, many of the applications of the PLL outlined in this article become economically feasible only
because the PLL is now available as a low-cost Ie building block.
FSK demodulation: Frequency-shift keyed (FSK) signals
are commonly used to transmit digital information over
telephone lines. In this type of modulation, the carrier
signal is shifted between. two discrete frequencies to
encode the binary data. When the PLL is locked on the
input signal, tracking the shifts in the input frequency,
the error voltage in the loop, Vd(t), converts the frequency shifts back to binary logic pulses.
Signal conditioning: When the PLL is locked on a noisy input signal, the veo output duplicates the frequency of
the desired input but greatly attenuates the noise, undesired sidebands and interference present at the input. It
is also a tracking filter since it can track a slowly varying input frequency.
Today, over a dozen different integrated PLL products
are available from a number of Ie manufacturers. Some
of these are designed as "general-purpose" circuits,
suitable for a multitude of uses; others are intended or
optimized for special applications such as tone detection, stereo decoding and frequency synthesis. This article is intended as a brief survey of the expanding field
of monolithic phase locked loops. Its purpose is to familiarize the reader with their individual characteristics,
capabilities and applications.
PROGHAMMABLE
COUNTER
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Frequency synthesis: The PLL can be used to generate
new frequencies from a stable reference source by either frequency multiplication and division, or by frequency translation. Figure 3 shows a typical frequency
multiplication and division circuit, using a PLL and two
programmable counters. In this application, one of the
counters is inserted between the veo and phase comparator and effectively divides the veo frequency by
OFFSET
INPUT
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OUTPUT
'II" fR t 'I
Figure 4. Frequency translation. can be accomplished with a
phase locked loop by adding a multiplier and an additional low-pass flltar to the basic PLL.
Figure 3. A frequency multiplier/divider can be constructed
using a phase locked loop.
1-6
the counter's modulus N. When the system is in lock,
the YCO output is related to the reference frequency,
fR, by the counter moduli M and N as:
fo =
(~)
PLL
AMOR
TONE
INPUT
fR
By adding a multiplier and an additional low·pass filter
to a PLL (Figure 4), one can form a frequency translation loop. In this application, the YCO output is shifted
from the reference frequency, fR, by an amount equal
to the offset frequency, fl' i.e., fo = (fR + fl)'
Data synchronization: The PLL can be used to extract synchronization from a composite signal, or can be used to
synchronize two data streams or system clocks to the
same frequency reference. Such applications are useful in PCM data transmission, regenerative repeaters,
CRT scanning and or drum memory read-write synchronization.
DEMODULATED
OUTPUT
Figure 5. AM and tone detection are possible by adding three
functional blocks to the basic phase locked loop.
AM detection: The PLL can be converted to a synchronous AM detector with the addition of a non-critical
phase-shift network, an analog multiplier and a lowpass filter. The system block diagram for this application is shown in Figure 5.
achieved using a PLL system, as shown in Figure 6.
The YCO section of the monolithic PLL is separated
from the phase-comparator and used to generate a voltage controlled reference frequency, fRo The motor shaft
and the tachometer output provide the second signal,
frequency fM, which is compared to the reference frequency. The controller is a power amplifier which drives
the speed-control windings of the motor. Thus, the motor and tachometer combination essentially functions
as a YCO which is phase locked to the voltage controlled reference frequency, fRo
In this application, as the PLL tracks the carrier of the
input signal, the YCO regenerates the unmodulated carrier and feeds it to the reference input of the multiplier
section. In this manner, the system functions as a synchronous demodulator with the filtered output of the
multiplier representing the demodulated audio information.
Stereo decoding: In commercial FM broadcasting, suppressed carrier AM modulation is used to superimpose
the stereo information on the FM signal. To demodulate
the complex stereo signal, low-level pilot tone is transmitted at 19 kHz (1/2 of actual carrier frequency). The
PLL can be used to lock onto this pilot tone, and regenerate a coherent 38 kHz carrier which is then used to
demodulate the complete stereo signal. A number of
highly specialized monolithic circuits have been developed for this application. A typical example of monolithic stereo decoder circuits using the PLL principle is the
XR-1310 stereo demodulator IC.
Tone detection: In this application, the PLL is again connected as shown in Figure 5. When a signal tone is
present at the input, within a frequency band corresponding to the capture range of the PLL, the output dc
voltage is shifted from its tone-absent level. This shift is
easily converted to a logic signal by adding a threshold
detector with logic-compatible output levels.
Motor speed control: Many electromechanical systems,
such as magnetic tape drives and disc or drum head
drivers, require precise speed control. This can be
L ________ _
ANALOG CONTROL
INPUT
Figure 6. Very precise motor speed control Is possible with a phase locked loop system of this type.
1-7
Choosing the Right PLL Circuit
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o
o
Center frequency stability.
Logic compatible output.
Control of VCO conversion gain.
Center frequency stability is essential to insure that the
VCO frequency range stays within the Signal band over
the operating temperature range. A logic compatible
output is desirable to avoid the need for an external
voltage comparator (slicer) to square the output pulses.
It is particularly convenient if the output conforms to
RS-232C standard, thereby eliminating the need for a
separate line-driver circuit. Control of the VCO's conversion gain allows the circuit to be used for both large deviation FSK signals (such as 1200 baud operation) as
well as for small deviation (75 baud) FSK signals.
At the onset of his design, the user of monolithic PLL
products is faced with the key question of choosing the
phase-locked loop IC best suited to his application. The
broad line of PLL products offered by Exar cover a wide
range of applications. It is often difficult to determine at
a glance the best circuit for a given application. The
purpose of this section is to review some of the key performance requirements, from an applications point of
view, and help answer the question, "What is the best
PLL product for the job?"
Table 2 gives a brief listing of some of the major classes
of PLL applications, and lists the recommended circuits
for each. A further discussion of the key performance
parameters associated with each application are also
listed below.
For FSK decoding at low frequencies (i.e., below 300
kHz) the XR-2211 is by far the optimum circuit to use
because of its frequency stability and carrier-detect capability. For FSK detection at higher frequencies (up to
10 MHz) the XR-210 is the recommended circuit.
FM demodulation: Essentially all the PLL circuits listed in
Table 1 can be used for FM demodulation. However, it is
often possible to narrow the choice down to 2 or 3 circuits, based on the particular performance criteria. In
general, there are three key performance parameters
which should be examined:
Frequency synthesis: This application requires a PLL circuit with the loop opened between the VCO output and
the phase comparator input, so that an external frequency divider can be inserted into the feedback loop
of the PLL. This requirement is satisfied by XR-S200,
XR-210, XR-215 and the XR-2212 PLL circuits.
o
Quality of demodulated output: This is normally
measured in terms of the output level, distortion,
and signal/noise ratio for a given FM deviation.
o
VCO frequency range and frequency stability: For
reliable operation, VCO upper frequency limit (see
Table 1) should be at least 20% above the FM carrier frequency. VCO frequency stability is important,
especially if a narrow-band filter is used in front of
the PLL, or multiple input channels are present. If
the VCO exhibits excessive drift, the PLL can drift
out of the input signal band as the ambient temperature varies.
For frequency synthesis at low frequencies (i.e., with
maximum output frequency less than 300 kHz) the
XR-2212 is by far the best suited circuit since it has the
best VCO stability and interfaces easily with all logic
families. For operation above 300 kHz, either the
XR-210 or the XR-215 PLL IC's can be used for frequency synthesis; however the XR-215 offers the highest frequency capability.
o
Detection threshold: This parameter determines
minimum signal level necessary for the PLL to lock
and demodulate an FM signal of given deviation.
require very narrow-band operation of the PLL. This in
turn may require the use of active filters within the loop
(between the phase detector and the VCO). The PLL circuits which allow active filers to be inserted into the
loop are the XR-S200 and the XR-2212. Both of these
circuits already contain an op. amp. on the chip for active filtering. For low frequencies (i.e. below 300 kHz)
the XR-2212 is the best suited circuit because of its adjustable tracking bandwidth and excellent frequency
stability. For higher frequencies the XR-S200 is the recommended circuit.
Signal conditioning: Most signal conditioning applications
In most FM demodulation applications, it is also desirable to control the amplitude of the demodulated output. This feature is provided in some of the PLL circuits
(such as the XR-215 and the XR-2212) by means of a
variable-gain amplifier contained on the chip.
For low-frequency FM detection (below 300 kHz carrier
frequency) the XR-2212 is recommended because of its
versatility and temperature stability. For FM demodulation at frequencies above 300 kHz, the XR-2215 offers
the best performance because of its high frequency capability.
Tone decoding: The PLL circuits especially designed for
this application are the XR-567, the XR-L567, the
XR-2567 and the XR-2211. The XR-2211 offers the highest frequency stability, and independent control of system bandwidth and response time, among the three circuits. The XR-567 has a relatively high input threshold
('" 20 mV, rms) and may require input preamplification;
however it requires fewer external components that the
XR-2211. The XR-2567, which contains two independent 567-type tone decoders on the same chip may be
more economical to use in mUltiple-tone detection systems.
FSK decoding: Frequency-shift keying used in digital
communications is very similar to analog FM modulation. Therefore, any PLL IC can be used for FSK decoding, provided that its input sensitivity and the tracking
range are sufficient for a given FSK signal deviation.
Some of the basic requirements and desirable features
for a PLL used in FSK decoding are:
1-8
XR·210
FSK Modulator/Demodulator
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-210 is a highly versatile monolithic phaselocked loop system, especially designed for data communications. It is particularly well suited for FSK
modulation/demodulation (MODEM) applications, frequency synthesis, tracking filters, and tone decoding.
The XR-210 operates over a power supply range of 5V
to 26V, and over a frequency band of 0.5 Hz to 20 MHz.
The circuit can accommodate analog signals between
300 p.V and 3V, and can interface with conventional
DTL, TIL, and ECL logic families.
VOLTAGE
COMPARATOR
INPUT
+Vcc
r
vco
OUTPUT
PHASE
OETECTOR
OUTPUTS
l
L
VCO
TIMING
CAPACITOR
INPUT
#1
J
l
BIAS
VCOGAIN
AND SWEEP
CONTROLS
INPUT
#2
FEATURES
Wide Frequency Range
0.5 Hz to 20 MHz
Wide Supply Voltage Range
5V to 26V
Digital Programming Capability
RS-232C Compatible Demodulator Output
DTL, TIL and ECL Logic Compatibility
Wide Dynamic Range
300 p.V to 3V
ON-OFF Keying & Sweep Capability
Wide Tracking Range
±1% to ±50%
200 ppm/DC
Good Temperature Stability
High-Current Logic Output
50 mA
Independent "Mark" and "Space"
Frequency Adjustment
VCO Duty Cycle Control
J
vco
GROUND
KEYING
INPUT
(-VEE)
vco
LOGIC
OUTPUT
FINE-TUNE
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-210M
XR-210CN
Ceramic
Ceramic
-55°C to + 125°C
O°C to + 70°C
APPLICATIONS
Data Synchronization
Signal Conditioning
FSK Generation
Tone Decoding
Frequency Synthesis
FSK Demodulation
Tracking Filter
FM Detection
FM and Sweep Generation
Wideband Discrimination
SYSTEM DESCRIPTION
The XR-210 is made up of a stable wide-range voltagecontrolled oscillator (VCO), exclusive OR gate type
phase detector, and an analog voltage comparator. The
VCO, which produces a square wave as an output, is either used in conjunction with the phase detector to
form a phase-locked loop (PLL) for FSK demodulation
and tone detection or as a generator in FSK modulation
schemes. The phase detector when used in the PLL
configuration produces a differentional output voltage
with a 6 KO output impedance, which when capacitively
loaded forms a single pole loop filter. The voltage comparator is used to sense the phase detector output and
produces the output in the FSK demodulation connection.
ABSOLUTE MAXIMUM RATINGS
Power Supply
Power Dissipation
Derate Above +25°C
Storage Temperature
26 Volts
750 mW
6.0 mW/oC
-65°C to + 150°C
1-9
XR·210
ELECTRICAL CHARACTERISTICS
Test Conditions: V+
= 12V (single supply), TA = +25'C, Test circuit of Figure 1 with Co = 0.02"F, Sl, S2, S5 closed, S3, S4,
S6, S7 open, unless otherwise specified.
SYMBOL
PARAMETERS
MIN
TYP
MAX
UNIT
26
±13
16
V dc
V dc
mA
MHz
Hz
500
0.5
ppm/'C
CONOITIONS
GENERAL CHARACTERISTICS
VCC
ICC
fUL
fLL
Supply Voltage
Single Supply
Split Supply
Supply Current
Upper Frequency Limit
Lowest Practical Operating
Frequency
5
±2.5
9
15
12
20
0.5
See Figure 1
See Figure 2
See Figure 1, S2 open
See Figure 1, Sl open, S4 closed
Co = 500 "F
VCO SECTION
TC
PSR
fSW
Stability
Temperature
Power Supply
Sweep Range
Vo
DC
TR
TF
Output Voltage Swing
Duty Cycle Asymmetry
Rise Time
Fall Time
5:1
1.5
200
0.05
8:1
2.5
±1
20
40
±3
%N
V pop
%
ns
ns
f = 10 kHz, V+ '" 10V, a < TA < 75'C
10V < V+ < 24V
S3 closed, S4 open, 0 < Vs < 6V
See Figure 5, V + = 12V
S5 open
S5 open
10 pF to ground at Pin 15, S5 open
10 pF to ground at Pin 15, S5 open
PHASE DETECTOR SECTION
KD
Zo
VOOS
Conversion Gain
Output Impedance
Output Offset Voltage
2
6
35
150
Vlrad
kO
mV
Yin > 50 mV rms, see Figure 8
Measured looking into Pin 2 or 3
Measured across Pin 1 and 3, Yin = 0,
S5 open
VOLTAGE COMPARATOR SECTION
AVOL
ZIN
VOS
IB
CMRR
Open Loop Voltage Gain
Input Impedance
Input Offset Voltage
Input Bias Current
Common Mode Rejection
66
0.5
dB
MO
mV
nA
dB
80
2
1
80
90
f - 20 Hz
Measured looking into Pin 1
LOGIC OUTPUT SECTION
SR
IOL
VOL
ISINK
Slew Rate
"1" Output Leakage Current
"0" Output Voltage
Current Sink Capability
30
15
0.02
0.2
50
V/"sec
10
0.4
"A
V
mA
RL - 3 kO, CL - 10 pF, S2 closed
Vo = +24V
IL = 10 mA
Va :5 lV
EQUIVALENT SCHEMATIC DIAGRAM
PRINCIPLES OF OPERATION
Description of Controls
Phase-Detector Inputs (Pin 4 and 6):
One input to the phase detector is used as the signal input; the remaining input should be ac coupled to the
veo output (Pin 15), to complete the PLL (see Figure 1).
For split supply operation, these inputs are biased from
ground as shown in Figure 2.
Phase-Detector Bias (Pin 5):
This terminal should be dc biased as shown in Figures
1 and 2, and ac grounded with a bypass capacitor. The
1-10
XR·210
bias resistor in series with this pin should be half as
large as those in series with Pin 4 and 6.
Fine Tune Control (Pin 9):
For a given choice of timing capacitor, CO, the VCO frequency can be further fine·adjusted to a desired frequency, fl' by means of a trimmer resistor, RT, connected from Pin 9 to Pin 7, as shown in Figure 6. The fine
tuned VCO frequency, fl' is related to RT as:
Phase-Detector Outputs (Pin 2 and 3):
The low·frequency (or dc) voltage across these pins
corresponds to the phase difference between the two
signals at the phase-detector inputs (Pin 4 and 6).
These differential phase·detector outputs are internally
connected to the VCO control terminals. Pin 3 is also internally connected to the reference input of the voltage
comparator section.
fl '" 220(: + 0.1) Hz
Co
RT
where Co is in /LF, and
AT
is in kll.
VCO Timing Capacitor (Pin 13 and 14):
In normal use, the low·pass loop·filter capacitor, Cl, is
connected between Pin 2 and 3. The 6 kll impedances
of the two outputs add to 12 kll in the single-pole RC
low-pass loop filter. Pin 2 is externally connected to the
voltage comparator input (Pin 1) through an RC lowpass filter.
The VCO free· running frequency, fo, is inversely proportional to the timing capacitor, CO, connected between
Pin 13 and 14. With Pin 9 and 10 open'circuited, the
VCO frequency is related to Co as:
fO '" 220 Hz
Co
Frequency-Keying Input (Pin 10):
The VCO frequency can be varied between two discrete
frequencies, fl and f2' by connecting an external resistor, RX, to this terminal. Referring to Figure 6, the VCO
frequency is proportional to the sum of currents, 11 and
12, through the transistors, Tl and T2, on the monolithic
chip. These transistors are biased from a fixed internal
reference. The current, 11, is set internally, and is partially controllable by the fine·tune adjustment, RT. The
current, 12, is set by the external resistor, RX, connected between Pin 10 and Pin 7. For any Co setting, the
VCO frequency, f2' with RX connected to Pin 10, can be
expressed as:
f2 = fl (:
+
~:)
where Co is in /LF.
YCO Output (Pin 15):
The VCO produces approximately a 2.5V p-p square
wave output signal at this pin. The dc output level is approximately 2 volts below VCC. This pin should be connected to Pin 7 through a 10 kll resistor to increase the
output current drive capability. For high-voltage operation (VCC > 20V), a 20 kll resistor is recommended. It
is also advisable to connect a 5001l resistor in series
with this output, for short-circuit protection.
Using the frequency-keying control, the VCO frequency
can also be stepped in a binary manner by applying a
logic signal to Pin 10, as shown in Figure 6. For highlevel logiC inputs, the transistor, T2, is turned off, RX is
effectively switched out of the circuit, and the VCO frequency is shifted from f2 to fl.
Hz
where fl is the frequency with Pin 10 open-circuited,
and RX is in kll. Note that f2 can be fine-tuned to a desired value by the proper choice of RX'
VoHage Comparator Input (Pin 1):
This pin provides the signal input to the voltage comparator section. The comparator section is normally used
for post·demodulation slicing and pulse shaping. Normally. Pin 1 is connected to Pin 2 through a 15K external resistor, as shown in Figures 1 and 2. The input impedance level at this pin is approximately 2 Mil.
YCO Sweep Input (Pin 12):
The VCO frequency can be swept over a broad range
by applying an analog sweep voltage, Vs to Pin 12 (see
Figure 5). The impedance level looking into the sweep
input is approximately 501l. Therefore, for sweep applications, a current limiting resistor, RS, should be connected in series with this terminal. Typical sweep characteristics of the circuit are shown In Figure 5. The VCO
temperature dependence is minimal when the sweep
input is not used, and should be left open-Circuited.
Logic Driver Output (Pin 8):
This pin provides a binary logic output corresponding to
the polarity of the input signal, at the voltage comparator inputs. It is a bare·collector type stage with highcurrent sinking capability.
CAUTION: For safe operation of the circuit, the maximum current, IS, drawn from the sweep terminal should
be limited to 5 mA or less, under all operating conditions.
Definition of Terms
Phase-Detector Gain, Kd:
Kd is the output voltage from the phase detector per radian of phase difference at the phase-detector inputs
(Pin 4 and 6). Kd is proportional to the input Signal for
lOW-level inputs (:so 25 mV rms), and is constant at highinput levels (see Figure 8).
YCO Conversion Gain (Pin 11):
The VCO voltage· to-frequency conversion gain, 1<0, is
inversely proportional to the value of the external gain·
control resistor, RO, connected across Pin 11 and 12.
1-11
V'OR
GROUND
0.02
1-"0-"'0-"""
"
OUTPUT
J1f
Figure 2. Test Circuit for Split Supply Operation
Figure 1. Test Circuits lor Single Supply Operation
VCO Conversion Gain,
Ko:
KO" 700
CORO
(radians/sec)/volt
where Co is in I'F and RO is in kO. For most applica·
tions, recommended values for RO range from 1 kO to
10 kO.
DEMODULATED
o.1,.F
L---',+~ OU'jl
,,:;iH-''---<>'-1-I
INPUT
4K
When the XR·210 is connected as a PLL, its lock range
can be controlled by varying the VCO gain control resis·
tor, RO, across Pin 11 and 12. For input signals greater
than 30 mV rms, the PLL loop·gain is independent of
signal amplitude, but is inversely proportional to RO.
Figure 7 shows the dependence of lock range, ± .:1fL,
on RO.
O.I,.F
'"
Lock Range (.:1wL):
The range of frequencies in the vicinity of fo over which
the PLL can maintain lock with an input signal. If satura·
tion or limiting does not occur, the lock range is equal to
the loop gain; Le., .:1wL = KT = KdKo.
Figure 3. Circuit Connection for FSK Demodulation
(Single Supply)
Capture Range (.:1wC):
The band of frequencies in the vicinity of fo where the
PLL can establish or acquire lock with an input signal. It
is also known as the acquisition range. It is always
smaller than the lock range, and is related to the lowpass filter bandwidth. It can be approximated by a parametric equation of the form:
+5
-
~
w
t!I
Z
«
0
II
:t:
(,J
>
(,J
z
w
where IF(j.:1WC) I is the low-pass filter magnitude response at w = .:1wC. For a simple lag filter, it can be expressed as:
::l
0 -5
w
I%:
u.
0
(,J
>
-10
APPLICATIONS INFORMATION
o
I
5
10
15
20
25
TOTAL SUPPLY VOLTAGE (VOLTS)
FSK Demodulation
Figure 3 shows a generalized circuit connection for
FSK demodulation. The circuit is connected as a PLL
Figure 4. VCO Frequency Variation as a Function of Supply
Voltage
1-12
6
:0
2
I)
5
~
(,.)
Z
w
4
V
::J
C
w
a:
u.
0
3 l-
w
N
:::;
«
2
/
/
:E
a:
0
Z
/
XR·210
80
_0
/
40
~
wCl
20
Z
«
a:
10
lI<:
(,.)
0
oJ
oJ
«
I-
VIN
'0
0
I-
~
lVrms
~ 2 MHz
1
0
+2
o
-2
-4
-6
-8
1
-10
10
NET APPLIED SWEEP VOLTAGE, VS-VSO
(VOLTS)
100
RO' Kn
Figure 7_ Total Lock Range, ± ~IL' versus VCO Gain Control
Resistor, RO
10.0
z
o
RS
t;-
+o-~~~~-----<~
Vs
ffi~
2K
>-
z ~
8~
1
1.0
I
/
a:'"
0:;
1-0
«>
a:C1:
'D
:Ell<:
(NOTE: Vso~" Vcc - 5V ~ Open Circuit Voltage at pin 12)
0.1
Oz'
/
;;::;;:
",Cl
«
J:
Figure 5, Frequency Sweep Characteristics as a Function 01
Net Applied Sweep Voltage (Pin 10 Open)
0..
/'
0.01
,., 2V/rad
r'
HIGH LEVEL INPUT
CONsiANT
0.1
~
rms
100
10
1000
10,000
LOW LEVEL INPUT AMPLITUDE (mV, rms)
Figure 8. Phase Detector Conversion Gain, Kd, versus Input
Amplitude
1'.
INTERNAL
BIAS
+5V
'1
L.::.+-o--~-K.~
ov
'2'"'1
'1
I~~~T
f=
0.3)
(1 +iiX
co
220 (
=
and space frequencies of the input Signal. Typical component values for 300 baud (103-type) and 1200 baud
(202-type) MODEM applications are listed below:
'2
OPERATING
CONDITIONS
0.1)
t+iiT
TYPICAL COMPONENT
VALUES
300 Baud
Figure 6. VCO Fine-Tune (Pin 9) and Frequency-Keying
(Pin 10) Controls
system, by ac coupling the VCO output (Pin 15) to Pin 6.
The FSK input is applied to Pin 4. When the input frequency is shifted, corresponding to a data bit, the polarity of the dc voltage across the phase-detector outputs
(Pin 2 and 3) is reversed. The voltage comparator and
the logic driver section convert this dc level shift to a binary pulse. The capacitor, C1, serves as the PLL loop
filter, and C2 and C3 as post-detection filters. The timing capacitor, CO, and fine-tune adjustments are used
to set the VCO frequency, fo, midway between the mark
= 5.1
~
1070 Hz
Ro
'2
~
1270 Hz
Cl ~ C2 = 0.047 "F,
C3 = 0.033"F
High Band: '1 ~ 2025 Hz
RO
kll. Co
= 8.2 kll. Co = 0.1
"F
'2 ~ 2225 Hz
Cl = C2 = C3 = 0.033 "F
'1 = 1200 Hz
Cl ~ 0.033 "F,
C3 = 0.02"F
C2 = O.Ol"F
1200 Baud
'2 = 2200 Hz
1-13
= 0.22"F
Low Band: '1
XR·215
Monolithic Phase-Locked Loop
FUNCTIONAL BLOCK DIAGRAM
The XR-215 is a highly versatile monolithic phaselocked loop (PLL) system designed for a wide variety of
applications in both analog and digital communication
systems. It is especially well suited for FM or FSK demodulation, frequency synthesis and tracking filter applications. The XR-215 can operate over a large choice
of power supply voltages ranging from 5 V to 26 V and a
wide frequency band of 0.5 Hz to 35 MHz. It can accommodate analog signals between 300 microvolts
and 3 volts and can interface with conventional DTL,
TTL, and EeL logiC families.
FEATURES
Wide Frequency Range: 0.5 Hz to 35 MHz
Wide Supply Voltage Range: 5V to 26V
Digital Programming Capability
DTL, TTL and ECL Logic Compatibility
Wide Dynamic Range: 300 p.V to 3V
ON-OFF Keying and Sweep Capability
Wide Tracking Range: Adjustable from ± 1 % to ± 50%
High-Quality FM Detection: Distortion 0.15%
Signal/Noise 65dB
ORDERING INFORMATION
Pari Number
Package
Operating Temperatura
XR-215CN
Ceramic
O°C to 70°C
APPLICATIONS
SYSTEM DESCRIPTION
FM Demodulation
Frequency SyntheSiS
FSK CodingJDecoding (MODEM)
Tracking Filters
Signal Conditioning
Tone Decoding
Data Synchronization
Telemetry CodlngJDecoding
FM, FSK and Sweep Generation
Crystal Controlled Detection
Wideband Frequency Discrimination
Voltage-to-Frequency Conversion
The XR-215 monolithic PLL system consists of a balanced phase comparator, a highly stable voltagecontrolled oscillator (VCO) and a high speed operation
amplifier. Figure 1 depicts the functional block diagram
of the circuit. The phase comparator outputs are internally connected to the VCO inputs and to the noninverting input of the operational amplifier. A selfcontained PLL System is formed by simple AC coupling
the VCO output to either of the phase comparator inputs and adding a low-pass filter to the phase comparator output terminals.
The VCO section has frequency sweep, on-off keying,
sync, and digital programming capabilities. Its frequency is highly stable and is determined by a single exernal
capacitor. The operational amplifier can be used to for
audio preamplification in FM detector applications or
as a high speed sense amplifier (or comparator) in FSK
demodulation.
ABSOLUTE MAXIMUM RATINGS
Power Supply
Power Dissipation
Derate above + 25°C
Temperature
Storage
26 volts
750 mW
5 mW/oC
- 65°C to
+ 150°C
1-14
XR·215
ELECTRICAL CHARACTERISTICS
Test Conditions: V + = 12V (single supply), TA
= 25 D C, Test Circuit of Figure 2 with Co = 100 pF, (silver-mica) 81,
82, 85, closed, 83, 84 open unless otherwise specified.
LIMITS
PARAMETERS
MIN
TYP
MAX
UNITS
CONDITIONS
11
26
±13
15
35
V dc
V dc
mA
MHz
See
See
See
See
0.5
Hz
Co
I-GENERAL CHARACTERISTICS
SUPPLY VOLTAGE
Single Supply
Split Supply
Supply Current
Upper Frequency Limit
Lowest Practical Operating
Frequency
5
±2.5
8
20
Figure
Figure
Figure
Figure
=
2
3
2
2, SI open, S4 closed
500 "F
VCO SECTION:
Stability:
Temperature
Power Supply
Sweep Range
600
250
0.1
8:1
5:1
ppm/DC
%N
2.5
20
20
Vp _p
ns
ns
Conversion Gain
2
V/rad
Output Impedance
Output Offset Voltage
6
20
kll
mV
Output Voltage Swing
Rise Time
Fall Time
1.5
See Figure 2, ODC '" TA'" 75'C
V+ > 10V
S3 closed, S4 open,
0< Vs < 6V
See Figure 9, Co = 2000 pF
S5 open
10 pF to ground at Pin 15
PHASE COMPARATOR SECTION:
100
Yin > 50 mV rms (See
characteristic curves)
Measured looking into Pins 2 or 3
Measured across Pins 2 and 3
Yin = 0, S5 open
OP AMP SECTION:
Open Loop Voltage Gain
Slew Rate
Input Impedance
Output Impedance
Output Swing
Input Offset Voltage
Input Bias Current
Common Mode Rejection
66
dB
V/" sec
Mil
kll
80
2.5
2
2
10
1
80
90
0.5
7
",gif
Detection Threshold
Demodulated Output Amplitude
Distortion (THO)
AM Rejection
Output Signal/Noise
55
8) Tracklng FIHer
Discriminator Output
I(ll
"
XR·215
Figure 2. Test Circuit For Single Supply Operation
'(lV
Figure 5. Test Circuit For Tracking Filter
IltMIIIlUIAIIII
101(
UUTPUT
p
XR 215
S,,;NAl
INPUT
1501!
r
!
-800
>-
~
"
g '400
Velll!!,II'I!1
"{J t:11l1~;I' II.
w
0
"'..
u
~
01 jJf
01..,1
2.
21(
2K
10K
2
01
p'
SOUrlC[1 -::-
g
§
Figure 3. Test Circuit For Split-Supply Operation
0
U
>
'12V
Or
400 t-
800
10 KHI
100 KHt
1 MHl
10MHI
~AEOUENCY
Figure 6. Typical YCO Temperature Coefficient Range as a
Function 01 Operating Frequency (pin 10 open)
10' . -.....~-------------....,
,.
t-"'<>--t----o ~~~PUT
OK
10
VCO F REOUENCY IHzl
Figure 4. Test Circuit For FM Demodulation
Figure 7. YCO Free Running Frequency vs Timing Capacitor
1-16
XR·215
l00dB~----~------'-------------~------'
PHASE COMPARATOR OUTPUTS (PINS 2 ANO 3)
The low frequency (or dc) voltage across these pins
corresponds to the phase difference between the two
Signals at the phase comparator inputs (pins 4 and 6).
The phase comparator outputs are internally connected
to the veo control terminals (see Figure 1). One of the
outputs (pin 3) is internally connected to the noninverting input of the operational amplifier. The low-pass
filter is achieved by connecting an Re network to the
phase comparator outputs as shown in Figure 14.
VOUT
z
;;:
1
WdB~~~-T------~~
"~ 40 dB I-...:.\:~.:...r~----+------P,
w
>-
o-'
> 20dBI-~~~~~~,-------r---~
VCO TIMING CAPACITOR (PINS 13 AND 14)
The veo free-running frequency, fo, is inversely proportional to timing capacitor eO connected between pins
13 and 14. (See Figure 7).
VCO OUTPUT (PIN 15)
Figure 10. XR-215 Op Amp Frequency Response
The veo produces approximately a 2.5 Vp_p output signal at this pin. The dc output level is approximately
2 volts below Vee. This pin should be connected to pin
9 through a 10 kO resistor to increase the output current drive capability. For high voltage operation (Vee>
20V), a 20 kO resistor is recommended. It is also advisable to connect a 5000 resistor in series with this output for short circuit protection.
VCO SWEEP INPUT (PIN 12)
The veo Frequency can be swept over a broad range
by applying an analog sweep voltage, VS, to pin 12 (see
Figure 9). The impedance level looking into the sweep
input is approximately 500. Therefore, for sweep applications, a current limiting reSistor, RS, should be connected in series with this terminal. Typical sweep characteristics of the circuit are shown in Figure 9. The veo
temperature dependence is minimum when the sweep
input is not used.
CAUTION: For safe operation of the circuit, the maxi-
lOW LEVel INPUT AMPlITUOE fmV .• ms'
mum current, IS, drawn from the sweep terminal should
be limited to 5 mA or less under all operating conditions.
Figure 8. Phase Comparator Conversion Gain, Kd, versus
Input Amplitude
ON-OFF KEYING: With pin 10 open circuited, the veo
~
can be keyed off by applying a positive voltage pulse to
the sweep input terminal. With RS = 2 kO, oscillations
will stop if the applied potential at pin 12 is raised
3 volts above its open-circuit value. When sweep, sync,
or on-off keying functions are not used, RS should be
left open circuited.
4
>-
u
z
~ 3
51
:::
Ii!
N
~
:§
z
2
INTERNAL
BIAS
I
10
Bias Pins 1,4,5,6 to Vccl2
IJV
J:A~(;:'S~::CT
INPUT
0\1 I
.2
-2
-4
-6
-8
-10
f]
-12
11
I:;>
(1'~:)
NET APPLIED SWEEP VOLTAGE. Vs - VSO (VOL lS)
Figure 9. Typical Frequency Sweep Characteristics as a
Function of Applied Sweep Voltage
(Note: VSO =- VCC - 5V = Open Circuit Voltage at pin 12)
Figure 11. Explanation of VCD Range-Select Controls
1-17
XR·215
RANGE-SELECT (PIN 10)
tem comprised of three basic functional blocks: phase
comparator, low-pass filter and voltage-controlled oscillator (VeO). The basic principle of operation of a PLL
can be briefly explained as follows: with no input signal
applied to the system, the error voltage Vd,is equal to
zero. The veo operates at a set frequency, fo, which is
known as the "free-running" frequency. If an input signal is applied to the system, the phase comparator
compares the phase and frequency of the input signal
with the veo frequency and generates an error voltage,
Ve(t), that is related to the phase and frequency difference between the two signals. This error voltage is then
filtered and applied to the control terminal of the veo. If
the input frequency, fs, is sufficiently close to fo, the
feedback nature of the PLL causes the veo to synchronize or "lock" with the incoming signal. Once in lock,
the veo frequency is identical to the input signal, except for a finite phase difference.
The frequency range of the XR-215 can be extended by
connecting an external resistor, RX, between pins 9 and
10. With reference to Figure 11, the operation of the
range-select terminal can be explained as follows: The
veo frequency is proportional to the sum of currents 11
and 12 through transistors T1 and T2 on the monolithic
chip. These transistors are biased from a fixed internal
reference. The current 11 is set internally, whereas 12 is
set by the external resistor RX' Thus, at any eO setting,
the veo frequency can be expressed as:
fo = f1 (1
+
~:)
where f1 is the frequency with pin 10 open circuited
and RX is in kO. External resistor RX ( ... 7500) is recommended for operation at frequencies in excess of
5 MHz.
A LINEARIZED MODEL FOR PLL
The range select terminal can also be used for fine tuning. the veo frequency, by varying the value of RX. Similarly, the veo frequency can be changed in discrete
steps by switching in different values of RX between
pins 9 and 10.
When the PLL is in lock, it can be approximated by the
linear feedback system shown in Figure 13. : (Kif> is
the differential dc voltage across Pins 10 and 11,
per unit of phase error at phase detector input):
determined by external timing resistor, RO, connected
from this terminal to ground. The VCO free-running frequency, fO, is:
Kif> = 02VR/r volts/radian
fO = _1_Hz
ROCo
8. VCO Conversion gain, KO: (KO is the amount of
change in VCO frequency, per unit of dc voltage
change at Pin 11):
where Co is the timing capacitor across Pins 13 and 14.
For optimum temperature stability, RO must be in the
range of 10 KIl to 100 KIl see Figure 8).
KO = -1NRCoR1 Hz/volt
1-25
XR·2211
9. Total Loop Gain, Kp
The recommended value is RO iii 20 KIl. The final
value of RO is normally fine-tuned with the series potentiometer, RX.
KT = 211"K.pKO = 4/COR1 rad/sec/volt
10. Peak Phase Detector Current IA:
c) Calculate value of Co from design equation (1) or
from Figure 6:
IA = VR (volts)/25 mA
Co = 1/ROfO
APPLICATIONS INFORMATION
d) Calculate R1 to give a .<1f equal to the mark space
deviation:
FSK DECODING:
R1 = RO[fo/(f1 =f2)]
Figure 9 shows the basic circuit connection for FSK decoding. With reference to Figures 2 and 9, the functions of external components are defined as follows: RO
and Co set the PLL center frequency, R1 sets the system bandwidth, and C1 sets the loop filter time constant and the loop damping factor. CF and RF form a
one-pole post-detection filter for the FSK data output.
The resistor RB (= 510 KIl) from Pin 7 to Pin 8 introduces positive feedback across the FSK comparator to
facilitate rapid transition between output logic states.
e) Calculate C1 to set loop damping. (See design equation No.4.):
Normally,
r ..
1/2 is recommended.
Then: C1 = CO/4 for
r=
1/2
f) Calculate Data Filter Capacitance, CF:
For RF = 100 KIl, RB = 510 KIl, the recommended
value of CF is:
Recommended component values for some of the most
commonly used FSK bands are given in Table 1.
CF .. 3/(Baud Rate) /IF
Design Instructions:
The circuit of Figure 9 can be tailored for any FSK decoding application by the choice of five key circuit components: RO, R1, CO, C1 and CF For a given set of FSK
mark and space frequencies, f1 and f2' these parameters can be calculated as follows:
Note: All calculated component values except RO can
be rounded to the nearest standard value, and RO can
be varied to fine-tune center frequency, through a series potentiometer, RX- (See Figure 9.)
a) Calculate PLL center frequency, fo:
fa = f1
+
f2
2
b) Choose value of timing resistor RO, to be in the
range of 10 KIl to 100 KIl. This choice is arbitrary.
y+
.....-+--->
1
I
TOPttASE
OETECTOR
u
flo.
5 lUI
........V
10
V
V
I--"~
V ~Ro.'0K
V
~
V V I--" I-'" ~f--I-
-- rr
~
~~~
F-
~
"
~
~
~
•
U
SUPPLY VOLTAGE. Y+ (VOLTS)
10K ]
VIN MINIMUM .. V+ [ -20K ± 2.8 mV
(PEAK)
Ax +
Figure 4. lYplcal Supply Current vs V+ (Logic Outputs
Open Circuited)
Figure 3. Desensitizing Input Stage
1-26
M
XR·2211
1.0
'"
I,
"-
~
.
...::
01
8
t-..
'" "-
1000
"r'\
'\.
r'\.
'\
~1>.
~~o~
'" t-.. 1'\t-..i"'~~
~' " '1~
1>.~~
"'0"t,.
~>~~
"00
'
'\..
"\ 1:-"
f'\.
"r'\
0.01
100
"'.""
1"\
'\.
I'\.
'\
'"
g
100
r--.'" t\.'"
1'\
I'-.
1000
"
'"
~
....
,,"'"
10
o
'....-
'\
'0'00 ,
~ '0:- r-:s:. . K
o~
10,000
'0 (Hz)
.~ '\."'~K"
t'\.
~
0",
~·o
I"
o~
'\..
I'\.
~.
1,r'\'O •
i
1'\
'\.
I'\.
'\
r'\
J
I""
I'\.
'\.
'\..
c?"......c-
i"
~
""
~
'\.
"
"'"
'\
"'"
'''
'\
'\
1"\
1000
I"'"
10,000
'O(Hz)
Figure 5. YCO Frequency vs Timing Resistor
Figure 6. YCO Frequency vs Timing Capacitor
1.02
to
~
1.0 1
Z
'":::>o
'"
~
1.00
o
'"
~
.
0.99
:I
~
Z
0.98
0.97
5
= 1 kHz
5
R • 10 RO
~
--
.~ ~
i
V t;:/
~
(., V
CURVE
RO
1
5K
10 K
30 K
100 K
300K
3
•
5
10
12
14
16
Ii:
ii'
o
>u
3
•
2
!
~
V,
18
20
z
'"g:::>
..
a:
o
'"
~
~
z
I-22
24
V+ (VOLTS)
TEMPERATURE
Figure 7. Typical 10 vs Power Supply Characteristics
re)
Figure 8. Typical Center Frequency Drill vs Temperature
v.
Figure 9. Circuit Connection lor FSK Decoding
1-27
XR·2211
Design Example:
will be disabled at "low" state, until there is a carrier
within the detection band of the PPL, and the Pin 6 output goes "high," to enable the data output.
75 Baud FSK demodulator with mark space
frequencies of 1110/1170 Hz:
Step 1: Calculate fO: fO (1110
1140 Hz
+
The minimum value of the lock detect filter capacitance
Co is inversely proportional to the capture range, ±
Afc. This is the range of incoming frequencies over
which the loop can acquire lock and is always less than
the tracking range. It is further limited by Cl. For most
applications, Afc > Afl2. For RO = 470 KIl, the approximate minimum value of CD can be determined by:
1170) (1/2) =
Step 2: Choose RO - 20 KIl (18 KIl fixed resistor in
series with 5 KIl potentiometer)
Step 3: Calculate Co from Figure 6: Co = 0.044,.F
CD (,.F)
Step 4: Calculate Rl: Rl = RO (2240/60) = 380 KIl
16/capture range in Hz.
With values of CD that are too small, chatter can be observed on the lock detect output as an incoming signal
frequency approaches the capture bandwidth. Excessively large values of CD will slow the response time of
the lock detect output.
Step 5: Calculate Cl: Cl = CO/4 = 0.011 ,.F
Note: All values except RO can be rounded to nearest
standard value.
TONE DETECTION:
Table 1. Recommended Component Values for
Commonly Used FSK Bands.
(See Circuit of Figure 9.)
FSK BAND
~
Figure 11 shows the generalized circuit connection for
tone detection. The logic outputs, Q and Q at Pins 5 and
6 are normally at "high" and "low" logic states, respectively. When a tone is present within the detection band
of the PLL, the logic state at these outputs become reversed for the duration of the input tone. Each logic output can sink 5 mA of load current.
COMPONENT VALUES
300 Baud
fl = 1070 Hz
F2 = 1270 Hz
Co
Cl
Rl
= 0.039,.F
= 0.01 ,.F
= 100 KIl
CF
RO
= 0.005,.F
= 18 KIl
300 Baud
fl = 2025 Hz
f2 = 2225 Hz
Co
Cl
Rl
= 0.022,.F
= 0.0047,.F
= 200 KIl
CF
RO
= 0.005,.F
= 18 KIl
1200 Baud
fl = 1200 Hz
f2 = 2200 Hz
Co
Cl
Rl
= 0.027,.F
= 0.01 ,.F
= 30 KIl
CF
RO
= 0.0022 j4F
= 18 KIl
Both logic outputs at Pins 5 and 6 are open collector
type stages, and require external pull-up resistors RL 1
and RL2, as shown in Figure 11.
FSK DECODING WITH CARRIER DETECT:
The lock detect section of XR-2211 can be used as a
carrier detect option, for FSK decoding. The recommended circuit connection for this application is shown
in Figure 10. The open collector lock detect output, Pin
6, is shorted to data output (Pin 7). Thus, data output
CD
LOOt(
"LJ
OUTPUT
'*
Q
Figure 11. Circuit Connection for Tone Detection
With reference to Figures 2 and 11, the functions of the
external circuit components can be explained as follows: RO and Co set VCO center frequency; Rl sets the
detection bandwidth; C1 sets the low pass-loop filter
time constant and the loop damping factor. RL 1 and
RL2 are the respective pull-up resistors for the Q and
Qlogic outputs.
Design Instructions:
Figure 10. External Connectors for FSK Demodulation with
Carrier Detect Capability
/
The circuit of Figure 11 can be optimized for any tone
detection application by the choice of the 5 key circuit
components: RO, R1, CO, C1 and CD. For a given input,
Note: Data Output Is "Low" When No Carrier Is Present.
1-28
XR·2211
the tone frequency, fS, these parameters are calculated as follows:
at Pin 11. Normally, a non-inverting unity gain op amp
can be used as a buffer amplifier, as shown in Figure
12.
a) Choose RO to be in the range of 15 KO to 100 KO.
This choice is arbitrary.
...--..---..--0
b) Calculate Co to set center frequency, fO equal to fs
(see Figure 6): Co = 1/ROfS
c) Calculate R1 to set bandwidth ±af (see design
equation No.5):
v+
0.1 ",F
Co
R1 = RO(fO/af)
12
Note: The total detection bandwidth covers the frequency range of fO ± af.
11
AO
-=
v+
d) Calculate value of C1 for a given loop damping
factor;
C1
= CO/16 \2
Normally \ "" 1/2 is optimum for most tone detector applications, giving C1 = 0.25 CO.
Increasing C1 improves the out-of-band signal rejection, but increases the PLL capture time.
Figure 12. Linear FM Detector Using XR-2211 and an External
Op Amp. (See Section on Design Equation for Component Values.)
e) Calculate value of filter capacitor CO. To avoid chatter at the logic output, with RO = 470 KO, Co must
be:
The FM detector gain, i.e., the output voltage change
per unit of FM deviation can be given as:
CO(,.F) 2: (16/capture range in Hz)
Vout = R1 VR/100 RO Volts/% deviation
Increasing Co slows down the logic output response
time.
where VR is the internal reference voltage (VR = V + /2
- 650 mY). For the choice of external components R1,
RO, CO, C1 and Cf; see section on design equations.
Design Examples:
Tone detector with a detection band of 1 kHz ± 20 Hz:
PRINCIPLES OF OPERATION
a) Choose RO = 20 KO (18 KO in series with 5 KO potentiometer).
=
b) Choose Co for fO
0.05,.F.
Signal Input (Pin 2): Signal is ac coupled to this terminal.
The internal impedance at Pin 2 is 20 KO. Recommended input signal level is in the range of 10 mV rms
to 3V rms.
1 kHz (from Figure 6): Co
Quadrature Phase Detector Output (Pin 3): This is the high
impedance output of quadrature phase detector and is
internally connected to the input of lock detect voltage
comparator. In tone detection applications, Pin 3 is connected to ground through a parallel combination of RO
and Co (see Figure 2) to eliminate the chatter at lock
detect outputs. If the tone detect section is not used,
Pin 3 can be left open circuited.
c) Calculate R1: R1 = (RO) (1000/20) = 1 MO.
d) Calculate C1: for
0.013,.F.
!
= 1/2, C1 = 0.25, Co =
e) Calculate CO: Co = 16/38 = 0.42,.F.
f) Fine-tune center frequency with 5 KO potentiometer,
RX-
Lock Detect Output, Q (Pin 5): The output at Pin 5 is at
LINEAR FM DETECTION:
"high" state when the PLL is out of lock and goes to
"low" or conducting state when the PLL is locked. It is
an open collector type output and requires a pull-up resistor, RL, to V + for proper operation. At "low" state, it
can sink up to 5 mA of load current.
XR-2211 can be used as a linear FM detector for a wide
range of analog communications and telemetry applications. The recommended circuit connection for this
application is shown in Figure 12. The demodulated
output is taken from the loop phase detector output (Pin
11), through a post-detection filter made up of RF and
Cf; and an extemal buffer amplifier. This buffer amplifier is necessary because of the high impedance output
Lock Detect Complement, Ii (Pin 6): The output at Pin 6 is
the logic complement of the lock detect output at Pin 5.
This output is also an open collector type stage which
can sink 5 mA of load current at low or "on" state.
1-29
XR·2211
FSK Data Output (Pin 7): This output is an open collector
logic stage which requires a pull-up resistor, RL, to V+
for proper operation. It can sink 5 mA of load current.
When decoding FSK signals, FSK data output is at
"high" or "off" state for low input frequency, and at
"low" or "on" state for high input frequency. If no input
signal is present, the logic state at Pin 7 is indetermi·
nate.
FSK Comparilor Input (Pin 8): This is the high impedance
input to the FSK voltage comparator. Normally, an FSK
post-detection or data filter is connected between this
terminal and the PLL phase detector output (Pin 11).
This data filter is formed by RF and CF of Figure 2. The
threshold voltage of the comparator is set by the internal reference voltage, VR,available at Pin 10.
EaUIVALENT SCHEMATIC DIAGRAM
v.
r----------,----------,------------------T-------,
I
I
I
I
I
I
I
I
REFt
VOLTAGE
OUTPIfT
10 I
i
i
:•
~~I~__~~~
I
:
t.-+-7--.,..--11::.
.. K
I
I
I
I
I
L __________
I
~
_________
~
________________
INPUT PREAIIPLlFJER
AND UIlITE"
~
______
QUADRATURE
PHASE DETECTOR
I
~
LOCK DETECT
COMPARATOR
------------------,--------,
I
I
I
I
I
I
I
I
I
'SK
I
INPUT
I COMPARATOR
LOOP
"'~"JrEpc,;.OR :
A'
I:
I
I
I
I
I
I
I
I
I
,
:
• - I
I
~D~ _ _ _ _ _ _ _ _ _ _ _ _ ~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~ _ _ _ _ _ _ _ _ ~
VOLTAGE CONTROLLED
OSCILLATOR
LOOP PHASE DETECTOR
1-30
FSK COMPARATOR
7
XR·2212
Precision Phase-Locked Loop
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-2212 is an ultra-stable monolithic phase-locked
loop (Pll) system especially designed for data communications and control system applications. Its on board
reference and uncommitted operational amplifier, together with a typical temperature stability of better
than 20 ppm/oC, make it ideally suited for frequency
synthesis, FM detection, and tracking filter applications. The wide input dynamic range, large operating
voltage range, large frequency range, and ECl, DTl,
and TIL compatibility contribute to the usefulness and
wide applicability of this device.
FEATURES
Quadrature VCO Outputs
Wide Frequency Range
0.01 Hz to 300 kHz
Wide Supply Voltage Range
4.5V to 20V
DTLlTILlECl logic Compatibility
Wide Dynamic Range
2 mV to 3 Vrms
Adjustable Tracking Range (± 1 % to ±80%)
Excellent Temp. Stability
20 ppm/oC, Typ.
ORDERING INFORMATION
APPLICATIONS
Package
Operating Temperature
Ceramic
Ceramic
Plastic
Ceramic
Plastic
- 55°C to + 125°C
O°C to + 70°C
O°C to + 70°C
-40°C to +85°C
-40°C to +85°C
SYSTEM DESCRIPTION
Frequency Synthesis
Data Synchronization
FM Detection
Tracking Filters
FSK Demodulation
The XR-2212 is a complete Pll system with buffered
inputs and outputs, an internal reference, and an uncommited op amp. Two VCO outputs are pinned out;
one sources current, the other sources voltage. This
enables operation as a frequency synthesizer using an
external programmable divider. The op amp section
can be used as an audio preamplifier for FM detection
or as a high speed sense amplifier (comparator) for
FSK demodulation. The center frequency, bandwidth,
and tracking range of the Pll are controlled independantly by external components. The Pll output is directly compatible with MOS, DTl, ECl, and TIL logic
families as well as microprocessor peripheral systems.
ABSOLUTE MAXIMUM RATINGS
Power Supply
Input Signal level
Power Dissipation
Ceramic Package:
Derate Above TA = + 25°C
Plastic Package:
Derate Above TA = + 25°C
Part Number
XR-2212M
XR2212CN
XR-2212CP
XR-2212N
XR-2212P
18V
3 Vrms
The precision Pll system operates over a supply voltage range of 4.5 V to 20 V, a frequency range of 0.01
Hz to 300 kHz, and accepts input signals in the range of
2 mV to 3 Vrms. Temperature stability of the VCO is typically better than 20 ppm/oC.
750 mW
6 mW/oC
625 mW
5 mW/oC
1-31
XR·2212
ELECTRICAL CHARACTERISTICS
= + 12V, TA = +25°C, RO
component designation.
Tast Conditions: V+
PARAMETERS
= 30 kO, Co = 0.033 /LF, unless otherwise specified. See Figure 2 for
XR-2212C
XR-221212212M
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
15
10
4.5
6
6
15
12
V
mA
±1
±3
±1
±20
0.05
.2
±50
0.5
±20
0.05
.2
CONDITIONS
GENERAL
Supply Voltage
Supply Current
4.5
OSCILLATOR SECTION
Frequency Accuracy
Frequency Stability
Temperature
Power Supply
Upper Frequency Limit
Lowest Practical
Operating Frequency
Timing Resistor, RO
Operating Range
Recommended Range
100
300
2000
100
5
15
Deviation from fO = 1/ROCO
R1 = 00
ppm/DC See Fig. 8.
%N V+ = 12 ±1 V. See Fig. 7.
OfoN V+ = 5 ±0.5V.
See Fig. 7.
kHz
RO = 8.2 KO, Co = 400 pF
%
300
0.01
0.01
5
15
RO VA
~
Reference Voltage, VR (Pin 11): This pin is internally biased at the reference voltage level, VR:VR = V + 12650 mV. The dc voltage level at this pin forms an internal reference for the voltage levels at pins 10, 12 and
16. Pin 1 must be bypassed to ground with a 0.1 I'F capacitor, for proper operation of the circuit.
0
a:
12
~
!:
~
VA
~
tTL
to
'TH
INPUT SIGNAL FREQUENCY
VCO Control Input (Pin 12): VCO free-running frequency is
determined by external timing resistor, RO, connected
from this terminal to ground. For optimum temperature
stability, RO must be in the range of 10 KO to 100 KO
(see Figure 8).
Figure 9. Phase Detector Output Voltage (Pin 10) as a
Function of Input Signal Frequency. Note: Output
Voltage is Referenced to Internal Reference Voltage
VR at Pin 11
VCO Frequency Adjustment: VCO can be fine-tuned by
connecting a potentiometer, RX, in series with RO at Pin
12 (see Figure 10).
Design Equations:
(See Figure 2 and Figure g for definition of components.)
This terminal is a low-impedance point, and is internally
biased at a dc level equal to VR. The maximum timing
current drawn from Pin 12 must be limited to s 3 mA for
proper operation of the circuit.
1. VCO Center Frequency, fO:
1-34
fO = 1/ROCO Hz
XR·2212
2. Internal Reference Voltage, VR (measured at Pin 11)
VR = V+/2 - 650 mV
3. Loop Low-Pass Filter Time Constant, T:
.
4. Loop Damping,
t: r =
!{fco
1/4
-
C1
where N is the external frequency divider modular
(See 2). If no divider is used, N = 1.
5. Loop Tracking Bandwidth, ±.:1f/fO:
.:1f1fO = RO/R1
6. Phase Detector Conversion Gain, K.p: (Kq, is the differential dc voltage across Pins 10 and 11, per unit
of phase error at phase-detector input) K.p =
- 2VR/1I' volts/radian
Figure 10. Circun Connection for FM Demodulation
7. VCO Conversion Gain, KO: (KO is the amount of
change in VCO frequency, per unit of dc voltage
change at Pin 10. It is the reciprocal of the slope of
conversion characteristics shown in Figure 9). KO
= -1NRCOR1 Hz/volt
a) Choose VCO center frequency fO to be the same as
FM carrier frequency.
b) Choose value of timing resistor RO, to be in the
range of 10 KG to 100 KG. This choice is arbitrary.
The recommended value is RO ;: 20 KG. The final
value of RO is normally fine-tuned with the series potentiometer, RX'
8. Total Loop Gain, KT:
KT
= 211'K.pKO = 4/COR1
rad/sec/volt
9. Peak Phase-Detector Current, IA; available at pin 10.
c) Calculate value of Co from design equation (1) or
from Figure 6:
IA = VR (volts)/25 mA
Co = 1/ROfO
APPLICATION INFORMATION
d) Choose R1 to determine the tracking bandwidth, .:1f
(see design equation 5). The tracking bandwidth, .:1f,
should be set Significantly wider than the maximum
input FM signal deviation, .:1fSM. Assuming the
tracking bandwidth to be "N" times larger than
.:1fSM' one can re-unite design equation 5 as:
FM DEMODULATION:
XR-2212 can be used as a linear FM demodulator for
both narrow-band and wide-band FM signals. The generalized circuit connection for this application is shown
in Figure 10, where the VCO output (pin 5) is directly
connected to the phase detector input (pin 16). The demodulated signal is obtained at phase detector output
(pin 10). In the circuit connection of Figure 10, the op
amp section of XR-2212 is used as a buffer amplifier to
provide both additional voltage amplification as well as
current drive capability. Thus, the demodulated output
signal available at the op amp output (pin 8) is fully buffered from the rest of the circuit.
.:1f
RO
.:1fSM
-=-=N-fO
R1
fO
Table I lists recommended values of N, for various
values of the maximum deviation of the input FM
Signal.
In the circuit of Figure 10, ROCO set the VCO center frequency, R1 sets the tracking bandwidth, C1 sets the
low-pass filter time constant. Op amp feedback resistors RF and RC set the voltage gain of the amplifier section.
Design Instructions:
The circuit of Figure 10 can be tailored to any FM demodulation application by a choice of the external components RO, R1, RC, RF, Co and C1. For a given FM
center frequency and frequency deviation, the choice
of these components can be calculated as follows,
using the design equations and definitions given on
page 1-34, 1-35 and 1-36.
% Deviation 01 FM
Signal 1.:1ISMIfOI
Recommended value 01
Bandwidth Ratio, N
IN = .:1f1.:1ISMI
1 % or less
1 to 3%
1 to 5%
5to 10%
10 to 30%
30 to 50%
10
5
4
3
2
1.5
TABLE I
Recommended values of bandwidth ratio, N, for various
values of FM signal frequency deviation. (Note: N is the
ratio of tracking bandwidth .:1f to max. signal frequency
deviation, .:1fSM).
1-35
XR·2212
N is the modulus of the external frequency divider. Conversely, the VCO output frequency, f1 is equal to NfS.
e) Calculate C1 to set loop damping (see design equation 4). Normally, ! = 1/2 is recommended. Then, C1
= CO/4 for! = 1/2.
In the circuit configuration of Figure 11, the external
timing components, RO and CO, set the VCO freerunning frequency; R1 sets the tracking bandwidth and
C1 sets the loop damping, Le., the low-pass filter time
constant (see design equations).
f) Calculate RC and RF to set peak output signal amplitude. Output signal amplitude, Vout, is given as:
Vout =
e:~M) (VR) (:~) [RC R: RF]
r---~--------------~~V'
In most applications, RF = 100 KD is recommended;
then RC, can be calculated from the above equation
to give desired output swing. The output amplifier
can also be used as a unity-gain voltage follower, by
open circuiting RC (Le., RC = 00).
0.1
o---j
INPUT
SIGNAL
I,
Note: All calculated component values except RO
can be rounded-off to the nearest standard value,
and RO can be varied to fine-tune center frequency,
through a series potentiometer, RX' (See Figure 10.)
,.
OUTPUT t 1 " N is
Design Example:
V'
"
Demodulator for FM Signal with 67 kHz carrier frequency with ± 5 kHz frequency deviation. Supply voltage is
+ 12V and required peak output swing is ± 4 volts.
-'4Sl900RC,I..,llAR
Figure 11. Circuit Connection for Frequency Synthesizer
Step a) fO is chosen as 67 kHz.
The total tracking range of the PLL (see Figure 9),
should be chosen to accommodate the lowest and the
highest frequency, fmax and fmin, to be synthesized.
A recommended choice for most applications is to
choose a tracking half-bandwidth ~f, such that:
Step b) Choose RO = 20 KD (18 KD fixed resistor in series with 5 KG potentiometer).
Step c) Calculate CO; from design Eq. (1).
Co = 746 pF
Step d) Calculate R1. For given FM deviation,
= 0.0746, and N = 3 from Table I.
~f
~fSM/fO
=-
fmax - fmin.
If a fixed output frequency is desired, Le. Nand fS are
fixed, then a ± 10% tracking bandwidth is recommended. Excessively large tracking bandwidth may
cause the PLL to lock on the harmonics of the input signals; and the small tracking range increases the "lockup" or acquisition time.
Then:
RO/R1 = (3)(0.0746) = 0.224
or:
If a variable input frequency and a variable counter
modulus N is used, then the maximum and the minimum values of output frequency will be:
R1 = 89.3 KD.
Step e) Calculate C1 = (CO/4) = 186 pF.
fmax = Nmax (fS)max and fmin = Nmin (fS)min·
Step f) Calculate RC and RF to get ± 4 volts peak output swing: Let RF = 100 KD. Then,
DeSign Instructions:
RC = 80.6 KG.
For a given performance requirement, the circuit of
Figure 11 can be optimized as follows:
Note: All values except RO can be rounded-off to nearest standard value.
a) Choose center frequency, fO, to be equal to the output frequency to be synthesized. If a range of output
frequencies is desired, set fO to be at mid-point of
the desired range.
FREQUENCY SYNTHESIS
Figure 11 shows the generalized circuit connection for
frequency synthesis. In this application an external frequency divider is connected between the VCO output
(pin 5) and the phase-detector input (pin 16). When the
circuit is in lock, the two signals going into the phase·
detector are at the same frequency, or fS = f1/N where
b) Choose timing resistor RO to be in the range of 15
KD to 100 KD. This choice is arbitrary. RO can be fine
tuned with a series potentiometer, RX.
c) Choose timing capacitor, Co from Figure 6 or Equation 1.
1-36
XR·2212
d) Calculate R1 to set tracking bandwidth (see Figure
9, and design equation 5). If a range of output frequencies are desired, set R1 to get:
6.f
= f max
e) Calculate C1 to obtain desired loop damping. (See
design equation 4). For most applications, r = 1/2 is
recommended, thus:
- fmin.
If a single fixed output frequency is desired, set R1
to get:
6.f =
Note: All component values except Ra can be roundedoff to nearest standard value.
a.1 fa.
1-37
XR·2213
Precision Phase-Locked Loop/Tone Decoder
GENERAL DESCRIPTIDN
FUNCTIONAL BLOCK DIAGRAM
The XR-2213 is a highly stable phase-locked loop (PLL)
system designed for control systems and tone detection applications. It combines the features of the XR2211 and XR-2212 into a single monolithic IC. The circuit consists of a high stability VCO, input preamplifier,
phase detector, quadrature phase detector, and high
gain voltage comparator. Initial VCO frequency accuracy and supply rejection are an order of magnitude
better than industry standards like the 567 decoder. An
on board reference contributes to reliable operation
and complementary outputs aid applicability.
FEATURES
Wide Frequency Range
0.01 Hz to 300 kHz
Wide Supply Voltage Ran~
4.5 V to 15 V
Uncommitted VCO Q and Q Outputs
Wide Dynamic Input Voltage Range 2MV to 3 V RMS
20 PPM/oC Typ.
Excellent VCO Stability
ORDERING INFORMATION
APPLICATIONS
Tone Detection
Frequency Synthesis
FM Detection
Tracking Filters
Package
Operating Temperature
Ceramic
Ceramic
Plastic
Ceramic
Plastic
-55°C to
O°C to
O°C to
-40°C to
- 40°C to
+
+
+
+
+
125°C
70°C
70°C
85°C
85°C
SYSTEM DESCRIPTION
The XR-2213 is a complete PLL system including circuitry enabling dedicated tone detection capability
over a frequency range of 0.01 Hz to 300 kHz. Supply
voltage may range from 4.5 V to 15 V.
ABSOLUTE MAXIMUM RATINGS
Power Supply
Input Signal Level
Power Dissipation
Ceramic Package:
Derate Above TA = +25°C
Plastic Package:
Derate Above TA = + 25°C
Storage Temperature
Part Number
XR-2213M
XR-2213CN
XR-2213CP
XR-2213N
XR-2213P
The input preamplifier has a dynamic range of 2 mV to
3 Vrms. The high stability VCO, with buffered complementary outputs, typically features better than 20 ppml
°C temperature drift and 0.05%N supply rejection. An
on board voltage reference is provided, and can sink 2
mAo The complementary lock detect outputs are each
capable of sinking more than 7 mAo All system parameters are independantly determined by external components.
15 V
3 V RMS
750 MW
6 MW/oC
625 MW
5 MW/oC
- 55°C to + 150°C
1-38
XR·2213
ELECTRICAL CHARACTERISTICS
= + 12V, TA = + 25°C, RO
component designation.
Test Conditions: VCC
= 10 kO, Co = 0.1
XR-221312213M
PARAMETERS
MIN
/LF, unless otherwise specified. See Figure 2 for
XR-2213C
TYP
MAX
MIN
TYP
MAX
UNITS
15
11
4.5
9
9
15
12
V
mA
±1
±3
±1
%
20
0.05
300
50
0.5
20
0.05
300
PPM/oC
%IV
kHz
CONOITIONS
GENERAL
Supply voltage
Supply current
4.5
Ro
~
10KO
OSCILLATOR SECTION
Frequency accuracy
Frequency stability
Temperature
Power supply
Upper frequency limit
100
Timing resistor Ro
operating range
Recommended range
5
10
Deviation from
fo = _1_
RoCo
Rl = x
V+
Ro
Co
= 12V
=
=
± tV
8.2KO,
400pF
KO
KO
2000
100
OSCILLATOR OUTPUT
Voltage output
Positive swing
Negative swing
9.5
11.5
0.4
2.5
0.8
4.5
0.4
IL :5 100~
IL = 2mA
V
V
0.8
LOOP PHASE DETECTOR SECTION
Peak output current
Output offset current
Output impedance
Maximum swing
±150
±4
±200
±1
1
±5
±100
±4
±200
±2
1
±5
/LA
/LA
MO
V
20
2
KO
MVRMS
Referenced to
VREF
INPUT PREAMP SECTION
Input impedance
Input signal to cause limiting
20
2
10
Internal Reference
Voltage level
Output impedance
4.9
5.3
100
5.7
4.75
5.3
100
5.85
V
0
PRINCIPLES OF OPERATION
Figure 2 shows the standard connection for tone detection. The input Signal at Pin 4 is amplified and squaredup by the preamp before it is fed to the loop phase detector. The VCO Q output provides the other loop phase
detector input. The VCO provided in the XR-2213 is actually a current controlled oscillator, ICO. The input to
the ICO, Pin 13, is internally biased at VREF, with the
current drawn from this pin controlling the frequency of
operation of the ICO. The resistor RO from Pin 13 to
ground will provide a constant current which will be
made up of the current from Pin 13 and the current
from Rl or the phase detector output. The phase detector output, filtered by C1, will provide a voltage to Rl,
which is proportional to the phase difference between
the input frequency and the ICO frequency. The relationship between this voltage and phase difference is
shown in Figure 3. If the phase difference is 90°, Pin 6
will be at VREf; and therefore there will be no current
flow in Rl with all of the current in RO coming from Pin
13. This pOint is defined as the center frequency, fa, of
the PLL and is calculated by:
*fO
= _1_
ROCO
If the input frequency is increased, the phase shift will
decrease causing the voltage at Pin 6 to decrease. Current will now flow from Pin 13 to both RO and Rl, causing an increase in ICO input current and thus an output
frequency increase. If the phase detector swings all the
way to a volts, the current in R1, will be:
IRI
VREF
=--
R1
·This condition will also occur if no input signal is applied to Pin 4.
1-39
XR·2213
Vee
LOCK DETECT
OUTPUTS
INTERNAL
VOLTAGE
REFERENCE
r'
Figure 2. Generalized Circuit Connection for Tone Detection
PHASE SHIFT
BETWEEN
fa ± a.f
\/Po
'oANO'1
'10"
The capture range of the PLL, which is always less than
the tracking range, is described by:
2 VRfF
to"
a.Wc = 211"a.fc =
VREF
T =
fc
~
-V----;--T-
R1Cli00P time constant
range
= capture
Figure 3. PLL Input/Output Relationships
The internal voltage reference provides a voltage equal
to:
At fa, the current from Pin 13 was:
VREF
113=-RO
Vee -.7V
VREF = -
If the ratio of Pin 13 current at fa and the change, a.,
from fa is written, the tracking range can be determined:
2
This reference can sink up to 2 mA, but source only 100
p.A.
The quadrature phase detector will provide a high level,
- VCC, at Pin 8 whenever a frequency within the PLL
capture range is present at Pin 4. This will drive the
lock-detect outputs for a tone-detection indication. The
response of the lock-detect section can be controlled
by the capacitor, CO, from Pin 8 to ground.,_ The minimum value of Co is calculated by the formula:
VREF
a.fL
Rl
RO
RO
= -- = or a.fL = fa
VREF
AI
Rl
RO
If the input frequency was decreased, a.f will have the
same magnitude in the opposite direction. The tracking
range of the PLL will then be:
Co (p.F)
2:
~
fc
1-40
fc = capture range in Hz
XR·2213
RD = 470 KQ is suitable for most applications.
9. Loop capture range, ± afc:
The input to the phase detector may be directly connected to the VCO output in the stand-alone connection. If the VCO is not connected to the phase detector,
the signal driving this pin must have sufficient amplitude to drive the pin above and below a voltage equal to
VREF For low level signals, Pin 5 should be connected
to VREF through a 10 KO resistor and the signal capac itively coupled to Pin 5. The impedance into Pin 5 is approximately 100 KO and this pin is clamped for swings
above VREF + 2 V.
afc =
fL
---Hz
2'l1'R1 C1
10. Lock detect filter capacitor:
APPLICATIONS INFORMATION
DESIGN EQUATIONS
Figure 2 shows the XR-C453 connected for tone detection. The input signal is capacitively coupled to Pin 4
and may range from 2 mV to 3 V RMS. The VCO Q output is directly connected to the phase detector input,
Pin 5. The detection bandwidth is set by the ratio of RO
and R1 and the loop time constant, T. This corresponds
to the capture range of the PLL. The lock-detect output,
Pins 9 and 10, will give an active high and low indication when a tone in the detection bandwidth is present.
Refer to Figure 2 for component definitions.
1. VCO center frequency, fO:
fO = _1_Hz
ROCO
2. Internal voltage reference, VREF:
VCC
VREF = - - .7V
2
R£
V
DESIGN EXAMPLE:
20 kHz tone detector with a ± 1 kHz detection band.
3. Loop tracking range, ± afL:
A. Choose RO
= 15 KO, 12 KO resistor plus 50 potenti-
ometer.
B. Calculate Co
4. Loop low-pass filter time constant, T:
5. Loop damping,
fORO
= R1C1 sec.
T
Co
C. Calculate C1 = -
t:
4
s= ~ JCo
4
E. Calculate CD = .!§.
fc
KO = _ 2 VREF volts
...
radian
7. VCO conversion gain,
== .001 /otF
RO
D. Calculate R1 = fO = 300 KO
afc
C1
6. Loop phase detector conversion gain, KO:
KO = _
= _1_ .0033 /otF
== 0.01 /otF
F. Fine tune fO with Rx, 5 K potentiometer.
Ko:
The complete circuit is shown in Figure 4.
1
Hz
VREF COR1 volt
Figure 5 shows the connection for a frequency synthesizer. Here an input frequency of 10kHz produces an
output frequency of 40 kHz. The VCO center frequency,
fO, is set for 40 kHz. The divide by four will then provide
the phase detector input with 10 kHz. The lock range is
set to approximately 10% of fO. For larger divider ratios, C1 should be increased to minimize phase jitter.
8. Total loop gain, KT:
4
KT = KOKO = - - Hz
COR1
1-41
XR·2213
~C~--------------~-4~----------------------------------------------------~-,
XR·2213
10K
10K
12K
·'0----------; I'-'"'-+---~
r---;-----------~~--~_<)Q
OUTPUTS
~--r-------------~_{)Q
GNOC>----------~~~r_~~----------------------------------------------t_----~~
INPUT
300kfl
19kHz""1'!!021kHz
19kHz>'1>21kHz
Figure 4. Tone Detector
+4
+5V<>------.-~-1~----_f--t_~------r_;
.old~~
'08=1=
lOKI!
SKU
lOOK
GNDC>--------~--------------~~----~----------------------------------------------------J
-=
'1.,0 kHz. fo
=40 kHz,Ie1 = IC2 =
. Va OM7473 DUAL JK FLIP-FLOP
Figure 5. Frequency Synthesizer
1·42
Q
0
Vee 0
0
Vee
Tone Decoders
XR·567
Monolithic Tone Decoder
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-567 is a monolithic phase-locked loop system
designed for general purpose tone and frequency decoding. The circuit operates over a wide frequency
band of 0.01 Hz to 500 kHz and contains a logic compatible output which can sink up to 100 milliamps of
load current. The bandwidth, center frequency, and output delay are independently determined by the selection of four external components.
OUTPUT
fll T£ R
lOW PASS
LOOP fll TER
Figure 1 contains a functional block diagram of the
complete monolithic system. The circuit consists of a
phase detector, low-pass filter, and current-controlled
oscillator which comprise the basic phase-locked loop;
plus an additional low-pass filter and quadrature detector that enable the system to distinguish between the
presence or absence of an input signal at the center
frequency.
ORDERING INFORMATION
FEATURES
Bandwidth adjustable from 0 to 14 %
Logic compatible output with 100 mA current sinking
capability
High stable center frequency
Center frequency adjustable from 0.01 Hz to 500 kHz
Inherent immunity to false signals
High rejection of out-of-band signals and noise
Frequency range adjustable over 20:1 range by external resistor
Part Number
Package
Operating Temperature
XR-567M
XR-567CN
XR-567CP
Ceramic
Ceramic
Plastic
-55°C to +125°C
O°C to + 70°C
O°C to + 70°C
SYSTEM DESCRIPTION
The XR-567 monolithic tone decoder consists of a
phase detector, low pass filter, and current controlled
oscillator which comprise the basic phase-locked loop,
plus an additional low pass filter and quadrature detector enabling detection on in-band signals. The device
has a normally high open collector output capable of
sinking 100 mA.
APPLICATIONS
Touch-Tone® Decoding
Sequential Tone Decoding
Communications Paging
Ultrasonic Remote-Control
Telemetry Decoding
The input signal is applied to Pin 3 (20 kO nominal input
resistance). Free running frequency is controlled by an
RC network at Pins 5 and 6 and can typically reach 500
kHz. A capacitor on Pin 1 serves as the output filter and
eliminates out-of-band triggering. PLL filtering is accomplished with a capacitor on Pin 2; bandwidth and
skew are also dependant upon the circuitry here. Bandwidth is adjustable from 0% to 14% of the center frequency. Pin 4 is + VCC (4.75 to 9V nominal, 10V maximum); Pin 7 is ground; and Pin 8 is open collector output, pulling low when an in-band signal triggers the
device.
ABSOLUTE MAXIMUM RATINGS
Power Supply
10 volts
Power Dissipation (package limitation)
Ceramic Package
385 mW
Plastic Package
300 mW
2.5 mW/oC
Derate Above + 25°C
Temperature
Operating
XR-567M
-55°Cto +125°C
XR-567CN/567CP
O°C to + 70°C
Storage
-65°C to +150°C
In applications requiring two or more 567-type devices,
consider the XR-2567 dual tone decoder. Where center
frequency accuracy and drift are critical, compare the
XR-567A. Investigate employing the XR-L567 in low
power circuits.
1-43
XR·567
ELECTRICAL CHARACTERISTICS
Test Conditions: VCC = +5V. TA = 25°C, unless otherwise specified. Test circuit of Figure 2.
LIMITS
PARAMETERS
MIN
TYP
MAX
UNITS
9.0
V dc
8
10
13
15
15
-10
Vee + 0.5
mA
mA
mA
mA
V
V
V
CONDITIONS
GENERAL
Supply Voltage Range
Supply Current
Quiescent XR-567M
XR-567C
Activated XR-567M
XR-567C
Output Voltage
Negative Voltage at Input
Positive Voltage at Input
4.75
6
7
11
12
RL
RL
RL
RL
=
=
=
=
20kll
20 kll
20 kll
20 kll
CENTER FREQUENCY
Highest Center Frequency
Center Frequency Stability
Temperature TA = 25°C
0< TA < 70°C
-55 < TA < + 125°C
Supply Voltage
XR-567M
XR-567C
100
500
kHz
35
±60
±140
ppm/oC
ppm/oC
ppm/oC
See Figure 9
See Figure 9
See Figure 9
0.5
0.7
1.0
2.0
%N
%N
fo = 100 kHz
fo = 100 kHz
14
14
16
18
% of fo
% of fo
fo = 100 kHz
fo= 100 kHz
1
2
2
3
% offo
% offo
DETECTION BANDWIDTH
Largest Detection Bandwidth
XR-567M
XR-567C
Largest Detection Bandwidth Skew
XR-567M
XR-567C
Largest Detection Bandwidth Variation
Temperature
Supply Voltage
12
10
%/OC
%N
±0.1
±2
Vin = 300 mV rms
Vin = 300 mV rms
INPUT
Input Resistance
Smallest Detectable Input Voltage
Largest No-Output Input Voltage
Greatest Simultaneous Outband
Signal to Inband Signal Ratio
Minimum Input Signal to Wideband
Noise Ratio
10
20
20
15
25
kll
mVrms
mVrms
IL = 100 mA, fi = fo
IL = 100 mA, fi = fo
+6
dB
-6
dB
Bn = 140 kHz
V
V
,.A
IL = 30 mA, "in = 25 mV rms
IL = 100 mA, Vin = 25 mV rms
ns
ns
RL = 501l
RL = 501l
OUTPUT
Output Saturation Voltage
Output Leakage Current
Fastest ON-OFF Cycling Rate
Output Rise Time
Output Fall Time
0.2
0.6
0.01
fo/20
150
30
1-44
0.4
1.0
25
XR·567
DEFINITION OF XR-567 PARAMETERS
If the value of C3 becomes too large, the turn-on or
turn-off time of the output stage will be delayed until the
voltage change across C3 reaches the threshold voltage. In certain applications, the delay may be desirable
as a means of suppressing spurious outputs. Conversely, if the value of C3 is too small, the beat rate at
the output of the quadrature detector (see Figure 1)
may cause a false logic level change at the output.
(Pin 8)
CENTER FREQUENCY fo
fo is the free-running frequency of the currentcontrolled oscillator with no input signal. It is determined by resistor R1 between pins 5 and 6, and capacitor C1 from pin 6 to ground fo can be approximated by
fo .. - 1 R1 C1
The average voltage (during lock) at pin 1 is a function
of the inband input amplitude in accordance with the
given transfer characteristic.
where R1 is in ohms and C1 is in farads.
Vcc
DETECTION BANDWIDTH (BW)
"5V
The detection bandwidth is the frequency range centered about fo, within which an input signal larger than
the threshold voltage (typically 20 mV rms) will cause a
logic zero state at the output. The detection bandwidth
corresponds to the capture range of the PLL and is determined by the low-pass bandwidth filter. The bandwidth of the filter, as a percent of fo, can be determined
by the approximation
BW = 1070
~rF_+
__~________-,
0.01 pF 3
0---1
ft!.
XR
567
_,
foC2
where Vi is the input signal in volts, rms, and C2 is the
capacitance at pin 2 in I'F.
LARGEST DETECTION BANDWIDTH
24K
The largest detection bandwidth is the largest frequency range within which an input signal above the threshold voltage will cause a logical zero state at the output.
The maximum detection bandwidth corresponds to the
lock range of the PLL.
'AdjUS! for fo
'I
~
100 kHz
100 kHl, f5V
c'
IOOO33
Figure 2. XR-567 Tast Circuit
DETECTION BAND SKEW
The detection band skew is a measure of how accurately the largest detection band is centered about the
center frequency, fo . It is defined as (f max + fmin - 2
fo)/l o , where fmax and fmin are the frequencies corresponding to the edges of the detection band. If necessary, the detection band skew can be reduced to zero
by an optional centering adjustment. (See Optional
Controls).
INPUT
LOW PASS
F 1L TE A
0---1
,-----0-...,
XA
DESCRIPTION OF CIRCUIT CONTROLS
OUTPUT FIlTER - C3 (Pin 1)
Capacitor C3 connected from pin 1 to ground forms a
simple low-pass post detection filter to eliminate spurious outputs due to out-of-band signals. The time constant of the filter can be expressed as T3 = R3C3,
where R3 (4.7 kO) is the internal impedance at pin 1.
The precise value of C3 is not critical for most applications. To eliminate the possibility of false triggering by
spurious signals, it is recommended that C3 be ~ 2 C2,
where C2 is the loop filter capacitance at pin 2.
Figura 3. XR-567 Connection Diagram
1-45
567
XR·567
TYPICAL CHARACTERISTIC CURVES
25r---~---r---r--~----r-~
<
20
5
,
r\.
f----j---+--\-
e
I
~
I
M
15
105
~
~
1l
~
~
~
I\.
0
~
~
106
~
10
t
~
iil
~~
10'
i'-..... r-....... r-.......
§
°4L--~--~~--L---J----L-~,0
o
SUPPLY VOLTAGE - VOLTS
100 KHz
, MHz
250
15
14
12.5
12
.?
~
>
i5
e
...I
I
w
;:
"<~
e
i'i
i:i
~
"
10
10
7,5
-
6
e
z
~
~
~
5.0
4
~
2,5
2
BANDWIDTH AT
o
'a
+25
-25
+50
+75
~
w
w
"
-
~
w
~
~
t.1
!':
+100 +125
-/
'.........
r.........
-1.0
vee"
5.75V I
-2.0
'A
vee" 7.ev
-3.0
~
-4.0
-75
-50
-25
25
so
75
100
125
TEMPERATURE H'C)
°c
Figure 9. Frequency Drift with
Temperature
1000
I
0.'
........
h.
t-.....
-.....
5
0.7
~
0.6
/
/
500
400
300
"
200
'\
100
1',
II
I',
-200
6,0
6,5
SUPPLY VOLTAGE - VOL T8
Figure 10. Temperature CoeffiCient of
Center Frequency (Mean and S.D.)
7,0
o
2
3 4 5
30
10
10
20 3040 &0
100
CENTEA FREQUENCY - kHz
Figure 11. Power Supply Dependence of
Center Frequency
1-46
1\
"
'\.
·20
V
1
LIMITED
BY C2
50
./
0, 1
~ANDWIDTH
40
V
0,2
5,5
........
~
1.0
--r-.. .......
5.0
16
fa
~
:::.-:: 1,.-'"
~
-100
4,5
C2
14
0.9
.........
-300
12
Vee'" 4.7SV"
1.0
Figure 8. Bandwidth Variation with
Temperature
'-,. . >. . . '- 'r.......
-50
TEMPERATURE _
Figure 7. Bandwidth Versus Input Signal
Amplitude (C2 in "F)
-
2.0
"<1° -5.0
-75
......
25~C
C3
r---.
3.0
z
Z
•
~
~
100
10
r-......
Figure 6. Detection Bandwidth as a
Function of C2 and C3
~
~
r-........
BANDWIDTH - % OF
Figure 5. Largest Detection Bandwidth
Versus Operating Frequency
r-r-,.-,.--r-,.-,.--r--,
BANDWIDTH - % OF
o
CENTER FREQUENCY
Figure 4. Supply CUllent Versus Supply
Voltage
·300
10 KHz
1 KHz
100 Hz
r-.......
103
ANDWIDTH LIMITED BY
~TERNAL RESISTOR
IM'~'M~MI Cf'
1
2
3 4 5
10
20 30 4050
BANDWIDTH (% of fol
Figure 12. Greatest Number of Cycles
Before Output
100
XR·567
LOOP FILTER - C2 (Pin 2)
Capacitor C2 connected from pin 2 to ground serves as
a single pole, low-pass filter for the PLL portion of the
XR-567. The filter time constant is given by T2 = R2C2,
where R2 (10 kO) is the impedance at pin 2.
INPUT
The selection of C2 is determined by the detection
bandwidth requirements, as shown in Figure 6. For additional information see section on "Definition of
XR-567 Parameters".
OUTPUT
The voltage at pin 2, the phase detector output, is a linear function of frequency over the range of 0.95 to 1.05
fo, with a slope of approximately 20 mV/% frequency
deviation.
Response to 100 mV rms tone burst.
R L = 100 ohms.
INPUT (Pin 3)
The input signal is applied to pin 3 through a coupling
capacitor. This terminal is internally biased at a dc level
2 volts above ground, and has an input impedance level
of approximately 20 kO.
INPUT
TIMING RESISTOR R1 AND CAPACITOR C1 (Pins 5 and 6)
The center frequency of the decoder is set by resistor
Rl between pins 5 and 6, and capacitor Cl from pin 6
to ground, as shown in Figure 3.
OUTPUT
Pin 5 is the oscillator squarewave output which has a
magnitude of approximately VCC - l.4V and an average dc level of VCC/2. A 1 kO load may be driven from
this point. The voltage at pin 6 is an exponential triangle
waveform with a peak-to-peak amplitude of 1 volt and
an average dc level of Vcd2. Only high impedance
loads should be connected to pin 6 to avoid disturbing
the temperature stability or duty cycle of the oscillator.
Response to same input tone burst with wideband noise.
S
'R=-6dB
RL=1000hms
Noise Bandwidth = 140 Hz
Figure 13. Typical Response
1. Rl and Cl should be selected for the desired center
frequency by the expression fo .. 1/R1Cl. For optimum temperature stability, Rl should be selected
such that 2kO s Rl s 20 kO, and the R1Cl product
should have sufficient stability over the projected
operating temperature range.
LOGIC OUTPUT (Pin 8)
Terminal 8 provides a binary logic output when an input
signal is present within the pass-band of the decoder.
The logic output is an uncommitted, "base-collector"
power transistor capable of switching high current
loads. The current level at the output is determined by
an external load resistor, RL, connected from pin 8 to
the positive supply.
2. Low-pass capaCitor, C2, can be determined from the
Bandwidth versus Input Signal Amplitude graph of
Fi~ure 7. One approach is to select an area of operation from the graph, and then adjust the input level
and value of C2 accordingly. Or, if the input amplitude variation is known, the required foC2 product
can be found to give the desired bandwidth. Constant bandwidth operation requires Vi > 200 mV
rms. Then, as noted on the graph, bandwidth will be
controlled solely by the foC2 product.
When an in-band signal is present, the output transistor
at pin 8 saturates with a collector voltage less than 1
volt (typically 0.6V) at full rated current of 100 mAo If
large output voltage swings are needed, RL can be connected to a supply voltage, V +, higher than the VCC
supply. For safe operation, V + s 20 volts.
OPERATING INSTRUCTIONS
3. Capacitor C3 sets the band edge of the low-pass filter which attenuates frequencies outside of the detection band and thereby eliminates spurious outputs. If C3 is too small, frequencies adjacent to the
detection band may switch the output stage off and
on at the beat frequency, or the output may pulse off
and on during the turn-on transient. A typical minimum value of C3 is 2 C2.
SELECTION OF EXTERNAL COMPONENTS
A typical connection diagram for the XR-567 is shown
in Figure 3. For most applications, the following procedure will be sufficient for determination of the external
components Rl, Cl, C2, and C3.
1-47
XR·567
Conversely, if C3 is too large, turn-on and turn-off of
the output stage will be delayed until the voltage
across C3 passes the threshold value.
losing information due to turn-on transient or output
chatter is about 10 cycles/bit, which corresponds to an
information transfer rate of fo/l0 baud.
PRINCIPLE OF OPERATION
C2 = 130, C3 = 260 ,.F
fo
fo
The XR-567 is a frequency selective tone decoder sys·
tem based on the phase-locked loop (PLL) principle.
The system is comprised of a phase-locked loop, a
quadrature AM detector, a voltage comparator, and an
output logic driver. The four sections are internally inter·
connected as shown in Figure 1.
In situations where minimum turn-off time is of less importance than fast turn-on, the optional sensitivity adjustment circuit of Figure 14 can be used to bring the
quiescent C3 voltage closer to the threshold voltage.
Sensitivity to beat frequencies, nOise, and extraneous
signals, however, will be increased.
When an input tone is present within the pass-band of
the circuit, the PLL synchronizes or "locks" on the input signal. The quadrature detector serves as a lock indicator: when the PLL is locked on an input signal, the
dc voltage at the output of the detector is shifted. This
dc level shift is then converted to an output logic pulse
by the amplifier and logic driver. The logic driver is a
"bare collector" transistor stage capable of switching
100 mA loads.
-v
~,~"
L::1iI
XR-S67
C3
INCREASE
SENSITIVITY
DECREASE
SENSITIVITY
The logic output at pin 8 is normally in a "high" state,
until a tone that is within the capture range of the decoder is present at the input. When the decoder is
locked on an input signal, the logic output at pin 8 goes
to a "low" state.
t--......-"oI'VY_-<..
The center frequency of the detector is set by the freerunning frequency of the current-controlled oscillator in
the PLL. This free-running frequency, fo, is determined
by the selection of Rl and Cl connected to pins 5 and
6, as shown in Figure 3. The detection bandwidth is determined by the size of the PLL filter capacitor, C2; and
the output response speed is controlled by the output
filter capacitor, C3.
R
DECREASE
SENSITIVITY
•
AA
XRS67
I
C3
SDK
~~K t
INCREASE
SENSITIVITY
AC
1.0K
1
SILICON
DIODES FOR
TEMPE RATUA E
COMPENSATION
10PTIONAli
OPTIONAL CONTROLS
PROGRAMMING
Figure 14. Optional Sensitivity Connections
Varying the value of resistor Rl and/or capacitor Cl will
change the center frequency. The value of Rl can be
changed either mechanically or by solid state switches.
Additional Cl capaCitors can be added by grounding
them through saturated npn transistors.
CHATTER
When the value of C3 is small, the lock transient and ac
components at the lock detector output may cause the
output stage to move through its threshold more than
once, resulting in output chatter.
SPEED OF RESPONSE
Although some loads, such as lamps and relays will not
respond to chatter, logic may interpret chatter as a series of output signals. Chatter can be eliminated by
feeding a portion of the output back to the input (pin 1)
or, by increasing the size of capacitor C3. Generally, the
feedback method is preferred since keeping C3 small
will enable faster operation. Three alternate schemes
for chatter prevention are shown in Figure 15. Generally, it is only necessary to assure that the feedback
time constant does not get so large that it prevents operation at the highest antiCipated speed.
The minimum lock-up time is inversely related to the
loop frequency. As the natural loop frequency is lowered, the turn-on transient becomes greater. Thus maximum operating speed is obtained when the value of capacitor C2 is minimum. At the instant an input signal is
applied its phase may drive the oscillator away from the
incoming frequency rather than toward it. Under this
condition, the lock-up transient is in a worst case situation, and the minimum theoretical lock-up time will not
be achievable.
The following expressions yield the values of C2 and
C3, in microfarads, which allow the maximum operating
speeds for various center frequencies. The minimum
rate that digital information may be detected without
SKEW ADJUSTMENT
The circuits shown in Figure 16 can be used to change
the position of the detection band (capture range) with1-48
XR·567
~
.V
'VRl
XR
~67
Figure 18 shows the proper method of reducing the
loop gain for reduc~d bandwidth. This technique will improve damping and permit faster performance under
narrow band operation. The reduced impedance level
at pin 2 will require a larger value of C2 for a given cutoff frequency.
.V
RA
:<'00 TO 1K
8
",
C,
I
10K
.V
C
R!'
3J 10K
'V
'V
XR-567
RA
200 TO lK
'OPTIONAL
"""~
LOWE A VALUE OF C,
Figure 15. Methods of Reducing Chatter
RA
10K
+v
----l
r::::::'
J
l:1i
LOWERS fa
r
~
,:
XR·567
PERMITS
Lr'
*C A
C'J_
J
~:
J
20K
UNLATCH
CA PREVENTS LATCH UP
WHEN POWER SUPPL Y 15
TURNED ON
XR-567
Figure 17. Output Latching
C2
RAISES fa
+v
Vl
200
;;;
a:
XR·567
>
E
150
UJ
<:J
100
....
:0
Q.
~
50
Figure 16. Connections to Reposition Detection Band
10
DETECT ION BAND
in the largest detection band (or lock range). By moving
the detection band to either edge of the lock range, input signal variations will expand the detection band in
one direction only. Since R3 also has a slight effect on
the duty cycle, this approach may be useful to obtain a
precise duty cycle when the circuit is used as an oscillator.
12
14
% of fa
+v
OUTPUT LATCHING
In order to latch the output of the XR-567 "on" after a
signal is received, it is necessary to include a feedback
resistor around the output stage, between pin 8 and pin
1, as shown in Figure 17. Pin 1 is pulled up to unlatch
the output stage.
OPTIONAL SILICON
DIODES FOR
TEMPERATURE
COMPENSATION
BANDWIDTH REDUCTION
The bandwidth of the XR-567 can be reduced by either
increasing capacitor C2 or reducing the loop gain. Increasing C2 may be an undesirable solution since this
will also reduce the damping of the loop and thus slow
the circuit response time.
NOTE· ADJUST CONTROL FOR SYMMETRY OF
DETECTION BAND EDGES ABOUT f o .
Figure 18. Bandwidth Reduction
1-49
16
L
XR~567
+vcc
PRECAUTIONS
1. The XR-567 will lock on signals near (2n + 1) fo and
produce an output for signals near (4n + 1) fo, for n
= 0,1,2 - etc. Signals at 5 fo and 9 fo can cause an
unwanted output and should, therefore, be attenuated before reaching the input of the circuil.
r
2. Operating the XR-567 in a reduced bandwidth mode
of operation at input levels less than 200 mV rms
results in maximum immunity to noise and out-band
signals. Decreased loop damping, however, causes
the worst-case lock-up time to increase, as shown
by the graph of Figure 12.
t,
0.1
3. Bandwidth variations due to changes in the in-band
signal amplitude can be eliminated by operating the
XR-567 in the high input level mode, above 200 mY.
The input stage is then limiting, however, so that outband signals or high noise levels can cause an apparent bandwidth reduction as the in-band signal is
suppressed. In addition, the limited input stage will
create in-band components from subharmonic signals so that the circuit components from subharmonic signals so that the circuit becomes sensitive
to signals at fo/3, fol5 etc.
-=-
~F
Q 1 = 2N2906
Vo
8
XR-567
-=-
Cc
3
Vlo---i
r
0.1
6
Rl
~F
5
4
r-=-
+vcc
Figure 19. Dual Time Constant Tone Decoder
C1
can be used to detect the presence of the carrier signal. The output of the XR-567 is used to turn off the FM
demodulator when no carrier is present, thus acting as
a squelch. In the circuit shown, an XR-215 FM demodulator is used because of its wide dynamic range, high
signal/noise ratio and low distortion. The XR-567 will
detect the presence of a carrier at frequencies up to
500 kHz.
4. Care should be exercised in lead routing and lead
lengths should be kept as short as possible. Power
supply leads should be properly bypassed close to
the integrated circuit and grounding paths should be
carefully determined to avoid ground loops and undesirable voltage variations. In addition, circuits requiring heavy load currents should be provided by a
separate power supply, or filter capacitors increased
to minimize supply voltage variations.
0.1 "F
ADDITIONAL APPLICATIONS
JOOpF
:lOOOpF
2000pF
DUAL TIME CONSTANT TONE DECODER
For some applications it is important to have a tone decoder with narrow bandwidth and fast response time.
This can be accomplished by the dual time constant
tone decoder circuit shown in Figure 19. The circuit has
two low-pass loop filter capacitors, C2 and C'2. With no
input signal present, the output at pin 8 is high, transistor 01 is off, and C' 2 is switched out of the circuil. Thus
the loop low-pass filter is comprised of C2, which can
be kept as small as possible for minimum response
time.
lOOK
DEMODULATED
OUTPUT
When an in-band signal is detected, the output at pin 8
will go low, 01 will turn on, and capacitor C' 2 will be
switched in parallel with capacitor C2. The low-pass filter capacitance will then be C2 + C'2. The value of C'2
can be quite large in order to achieve narrow bandwidth. Notice that during the time that no input signal is
being received, the bandwidth is determined by capacitor C2.
NARROW BAND FM DEMODULATOR WITH
CARRIER DETECT
For FM demodulation applications where the bandwidth
is less than 10% of the carrier frequency, an XR-567
Figure 20. Narrow Band FM Demodulator with Carrier Detect
1-50
XR·567
DUAL TONE DECODER
other. Due to the internal biaSing arrangement the
actual phase shift between the two outputs is typically 80 0 •
In dual tone communication systems, information is
transmitted by the simultaneous presence of two separate tones at the input. In such applications two XR-567
units can be connected in parallel, as shown in Figure
21 to form a dual tone decoder. The resistor and capacitor values of each decoder are selected to provide the
desired center frequencies and bandwidth require·
ments.
IIIIiii Oil
,
Iiiiiii 00iI
i_
'11
II
~
~ ~ ~j
, [4 ~ ~ ~ ~
~ D~
' ~J
,J I
~J
~
~~
R,
g. , ..
NOR
INPUT
~~tE~~~~ o--i
Vo
C'I c2I I C3
Figure 22. Oscillator Output Waveform Available From CCO
Section.
Top: Square Wave Output at Pin 5:
Amplitude = (V + -1.4VJ, pp.,
Avg. Value = V + 12
Bottom: Exponential Triangle Wave at Pin 6:
Amplitude = 1V pp., Avg. Value = V + 12
1/4 SN7402
-=
V·
Ij.
C":r
C"2
JJ
c' 3
Figure 21. Dual Tone Decoder
X R 567
PRECISION OSCILLATOR
The current-controlled oscillator (CeO) section of the
XR-567 provides two basic output waveforms as shown
in Figure 22. The squarewave is obtained from pin 5,
and the exponential ramp from pin 6. The relative phase
relationships of the waveforms are also provided in the
figure. In addition to being used as a general purpose
oscillator or clock generator, the ceo can also be used
for any of the following special purpose oscillator applications:
6
\leo
!
'6'"''
1
5
1
1. High-Current Oscillator
The oscillator output of the XR-567 can be amplified
using the output amplifier and high-current logic output available at pin 8. In this manner, the circuit can
switch 100 mA load currents without sacrificing oscillator stability. A recommended circuit connection
for this application is shown in Figure 23. The oscillator frequency can be modulated over ±6% in frequency by applying a control voltage to pin 2.
Figure 23. PreCision Oscillator to Switch 1DO mA Loads
3. Oscillator with Frequency Doubled Outpul
The ceo frequency can be doubled by applying a
portion of the squarewave output at pin 5 back to the
input at pin 3, as shown in Figure 25. In this manner,
the quadrature detector functions as a frequency
doubler and produces an output of 2 fo at pin 8.
2. Oscillator with Quadrature Outputs
Using the circuit connection of Figure 24 the XR-567
can function as a precision oscillator with two separate squarewave outputs (at pins 5 and 8, respectively) that are at nearly quadrature phase with each
FSK DECODING
XR-567 can be used as a low speed FSK demodulator.
In this application the center frequency is set to one of
1-51
XR·567
V'
the input frequencies, and the bandwidth is adjusted to
leave the second frequency outside the detection band.
When the input signal is frequency keyed between the
in-band signal and the out-band signal, the logic state of
the output at pin 8 is reversed. Figure 26 shows the
FSK input (f2 = 3 f1) and the demodulated output signals, with fo = f2 = 1 kHz. The circuit can handle data
rates up to fo/1 0 baud.
X R 561
8
JLflJl.P
3
V·
V·
4
3 XR 561 8
7
6
"
CONNECT PIN 3
TO liN TO
INVERT OUTPUT
Figure 25. Oscillator with Double Frequency Output
Figure 24. Oscillator with Quadrature Output
Figure 26. Input and Output Waveforms for FSK Decoding
Top: Input FSK Signal (f2 = 3f1)
Bottom: Demodulated Output
1-52
'0
XR·567A
Precision Tone Decoder
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-567A provides all the necessary circuitry for
constructing a variety of tone detector and frequency
decoder applications. Phase-locked loop circuit techniques are used to provide operation from 0.01 Hz to
500 kHz. The circuit also features an input preamp, a
high-current logic output, and programmable output delay.
OUTPUT
FILTER
OUTPUT
LOW-PASS
LOOP FILTER
GROUND
-,
INPUT
The XR-567A, available in an 8-Pin DIL package, is designed to offer improved frequency accuracy and drift
characteristics over the standard industry 567. These
changes offer improved overall circuit performance,
while reducing initial circuit adjustments.
RESISTOR
AND
CAPACITOR
+Vcc
..J
ORDERING INFORMATION
FEATURES
Programmable Detection Bandwidth
0% to 14%
Logic Output
100 mA
Wide Center
0.01 Hz to 500 kHz
Frequency Range
High Rejection
of Out-of-Band Signals and Noise
Direct Replacement for standard 567
Inherent immunity to
out-of-band signals & noise
Part Number
Package
Operating Temperature
XR-567AM
XR-567ACN
XR-567ACP
Ceramic
Ceramic
Plastic
-55·C to + 125·C
O·C to + 70·C
O·C to + 70·C
SYSTEM DESCRIPTION
The XR-567A is an improved version of the popular 567
tone decoder. Center frequency accuracy is guaranteed by design modifications and testing to 5 %, and is
typically better than 2%. Temperature drift of the center frequency is also improved. Thus, in most applications, no trimming is required.
APPLICATIONS
Tone Detection
Touch-Tonel!> Decoding
Communications Paging
Ultrasonic Remote Control
Precision Oscillator
Wireless Intercom
Carrier-Tone Transceiver
FSK Demodulation
Dual Time Constant Tone Detector
The XR-567A monolithic tone decoder consists of a
phase detector, low pass filter, and current controlled
oscillator which comprise the basic phase-locked loop,
plus an additional low pass filter and quadrature detector enabling detection of in-band signals. The device
has a normally high open collector output capable of
sinking 100 mAo
The input signal is applied to Pin 3 (20 kll nominal input
resistance). Free running frequency is controlled by an
RC network at Pins 5 and 6 and can typically reach 500
kHz. A capacitor on Pin 1 serves as the output filter and
eliminates out-of-band triggering. PLL filtering is accomplished with a capacitor on Pin 2; bandwidth and
skew are also dependant upon the circuitry here. Bandwidth is adjustable from 0% to 14% of the center frequency. Pin 4 is +VCC (4.75 to 9V nominal, 10V maximum); Pin 7 is ground; and Pin 8 is open collector output, pulling low when an in band signal triggers the
device.
ABSOLUTE MAXIMUM RATINGS
Power Supply
Power Dissipation
Ceramic Package
Plastic Package
Derate above 25·C
Operating Temperature Range
XR-567AM
XR-567 ACN/ACP
Storage Temperature Range
TIMING
10 volts
385 mW
300 mW
2.5 mW/·C
- 55·C to + 125·C
O·C to +70·C
- 65·C to + 150·C
1-53
XR·567A
ELECTRICAL CHARACTERISTICS
Test Conditions: Vee = + 5V. TA
=
25° e, unless otherwise specified.
LIMITS
PARAMETL
MIN
TYP
MAX
UNITS
9.0
Vdc
8
10
13
15
15
-10
VCC +0.5
mA
mA
mA
mA
V
V
V
CONDITIONS
GENERAL
Supply Voltage Range
Supply Current
Quiescent XR-567AM
Quiescent XR-567 AC
Activated XR-567 AM
Activated XR-567 AC
Output Voltage
Negative Voltage at Input
Positive Voltage at Input
4.75
6
7
11
12
RL
RL
RL
RL
=
=
=
=
20
20
20
20
kG
kG
kG
kll
CENTER FREQUENCY
Highest Center Frequency
Center Frequency Stability
Temperature TA = 25°C
o < TA < 70°C
-55 < TA < +125°C
Supply Voltage
XR-567AM
XR-567AC
Initial Accuracy
100
500
kHz
35
±60
±120
ppm/oC
ppm/oC
ppm/oC
0.5
0.7
±2.0
1.0
2.0
±5.0
%N
%N
%
10 = 100 kHz
10 = 100 kHz
10 = 100 kHz
14
14
16
18
% 0110
% 0110
10 = 100 kHz
10 = 100 kHz
1
2
2
3
% 0110
% 0110
±0.1
±1
±2
%N
25
kG
mVrms
mVrms
DETECTION BANDWIDTH
Largest Detection Bandwidth
XR-567AM
XR-567AC
Largest Detection Bandwidth Skew
XR-567AM
XR-567AC
Largest Detection Bandwidth Variation
Temperature
Supply Voltage
12
10
%/oC
Yin = 300 mV rms
Yin = 300 mV rms
INPUT
I nput Resistance
Smallest Detectable Input Voltage
Largest No-Output Input Voltage
Greatest Simultaneous Outband
Signal to Inband Signal Ratio
Minimum Input Signal to Wideband
Noise Ratio
10
20
20
15
IL = 100 mA, Ii = 10
IL = tOO mA, Ii =10
+6
dB
-6
dB
Bn = 140 kHz
V
V
p.A
IL = 30 mA, Yin = 25 mV rms
IL = 100 mA, Yin = 25 mV rms
ns
ns
RL = 501l
RL = 50G
OUTPUT
Output Saturation Voltage
Output Leakage Current
Fastest ON/OFF Cycling Rate
Output Rise Time
Output Fall Time
0.2
0.6
0.01
10/20
150
30
1-54
0.4
1.0
25
XR·L567
Micropower Tone Decoder
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-L567 is a micropower phase-locked loop (PLL)
circuit designed for general purpose tone and frequency decoding. In applications requiring very low power
dissipation, the XR-L567 can replace the popular 567type decoder with only minor component value
changes. The XR-L567 offers approximately 1/10th the
power dissipation of the conventional 567-type tone decoder, without sacrificing its key features such as the
oscillator stability, frequency selectivity, and detection
threshold. Typical quiescent power dissipation is less
than 4 mW at 5 volts. It operates over a wide frequency
band of 0.01 Hz to 60 kHz and contains a logic compatible output which can sink up to 10 milliamps of load
current. The bandwidth, center frequency, and output
delay are independently determined by the selection of
four external components.
OUTPUT
FILTER
LOW PASS
LOOP fiLTER
ORDERING INFORMATION
FEATURES
Very Low Power Dissipation ('" 4 mW at 5V).
Bandwidth Adjustable from 0 to 14 % .
Logic Compatible Output with 10 mA Currerit Sinking
Capability.
Highly Stable Center Frequency.
Center Frequency Adjustable from 0.01 Hz to 60 kHz.
Inherent Immunity to False Signals.
High Rejection of Out-of-Band Signals and Noise.
Frequency Range Adjustable Over 20:1 Range by External Resistor.
Part Number
Package
Operating Temperature
XR-L567CN
XR-L567CP
Ceramic
Plastic
O°C to + 70°C
O°C to + 70°C
SYSTEM DESCRIPTION
The XR-L567 monolithic circuit consists of a phase detector, low pass filter, and current controlled oscillator
which comprise the basic phase-locked loop, plus an
additional low pass filter and quadrature detector enabling detection of in-band signals. The device has a normally high open collector output.
APPLICATIONS
ABSOLUTE MAXIMUM RATINGS
The input signal is applied to Pin 3 (100 k!l nominal input resistance). Free running frequency is controlled by
an RC network at Pins 5 and 6. A capacitor on Pin 1
serves as the output filter and eliminates out-of-band
triggering. PLL filtering is accomplished with a capacitor on Pin 2; band-width and skew are also dependant
upon the circuitry here. Pin 4 is + Vee (4.75 to 8V nominal, 10V maximum); Pin 7 is ground; and Pin 8 is the
open collector output, pulling low when an in-band signal triggers the device.
Power Supply
10 volts
Power Dissipation (package limitation)
Ceramic Package
385 mW
Plastic Package
300 mW
Derate Above +25°C
2.5 mW/oC
Operating Temperature
O°C to + 70°C
Storage Temperature
- 65°C to + 150°C
The XR-L567 is pin-for-pin compatible with the standard
XR-567-type decoder. Internal resistors have been
scaled up by a factor of ten, thereby reducing power
diSSipation and allowing use of smaller capacitors for
the same applications compared to the standard part.
This scaling also lowers maximum device center frequency and load current sinking capabilities.
Battery-Operated Tone Detection
Touch-Tone" Decoding
Sequential Tone Decoding
Communications Paging
Ultrasonic Remote-Control
Telemetry Decoding
1-55
XR·L567
ELECTRICAL CHARACTERISTICS
Test Conditions: VCC = + 5V. TA = 25°C, unless otherwise specified. Test Circuit of Figure 1.
PARAMETERS
MIN
LIMITS
TYP
MAX
UNITS
CONDITIONS
General
Supply Voltage Range
Supply Current
Quiescent
Activated
4.75
0.6
0.8
8.0
V
1.0
1.4
mA
mA
RL = 20 kO
RL = 20 kO
Center Frequency
Highest Center Frequency
Center Frequency Drift
Temperature TA = 25°C
0< TA < 70°C
Supply Voltage
10
60
kHz
-35
-150
0.5
3.0
ppm/oC
ppm/oC
%N
See Figu res 10 and 11
See Figures 10 and 11
fo = 10kHz, VCC = 5.25 ± 0.5V
14
2
18
3
% of fo
% offo
fo = 10 kHz
See Figure 13 for Definition
Detection Bandwidth
Largest Detection Bandwidth
Largest Detection Bandwidth Skew
Largest Detection Bandwidth Variation
Temperature
Supply Voltage
10
±0.1
±2
%IOC
%N
Yin = 300 mV rms
Yin = 300 mV rms
kO
mVrms
mVrms
IL = 10 mA, fi = fo
IL = 10 mA, fi = fo
Inputs
Input Resistance
Smallest Detectable Input Voltage
Largest No-Output Input Voltage
Greatest Simultaneous Outband
Signal to Inband Signal Ratio
Minimum Input Signal to Wideband
Noise Ratio
10
100
20
15
25
+6
dB
-6
dB
Bn = 140 kHz
V
V
pA
IL = 2 mA, Yin = 25 mV rms
IL = 10 mA, Yin = 25 mV rms
ns
ns
RL = 1 kO
RL = 1 kO
Outputs
Output Saturation Voltage
Output Leakage Current
Fastest OnlOff Cycling Rate
Output Rise Time
Output Fall Time
0.2
0.3
0.01
fo/20
150
30
EQUIVALENT SCHEMATIC DIAGRAM
0.4
0.6
25
PRINCIPLES OF OPERATION
The XR-L567 is a frequency selective tone decoder system based on the phase-locked loop (PLL) principle.
The system is comprised of a phase-locked ,loop, a
quadrature am detector, a voltage comparator, and an
output logic driver.
When an input tone is present within the pass-band of
the circuit, the PLL synchronizes or "locks" on the input signal. The quadrature detector serves as a lock in.
dicator: when the PLL is locked on an input signal, the
dc voltage at the output of the detector is shifted. This
dc level shift is then converted to an output logiC pulse
by the amplifier and logic driver. The logic output at Pin
8 is an "open-collector" NPN transistor stage capable
of switching 10 mA current loads.
1-56
XR·L567
The logic output at Pin 8 is normally in a "high" state,
until a tone that is within the capture range of the decoder is present at the input. When the decoder is
locked on an input signal, the logic output at Pin 8 goes
to a "low" state.
Yee
Figure 3 shows the typical output response of the circuit for a tone-burst applied to the input, within the detection band.
OUTPUT
The center frequency of the detector is set by the freerunning frequency of the current-controlled oscillator in
the PLL. This free-running frequency, fo, is determined
by the selection of Rl and Cl connected to Pins 5 and
6, as shown in Figure 2. The detection bandwidth is determined by the size of the PLL filter capacitor, C2 (see
Figure 10); and the output response speed is controlled
by the output filter capacitor, C3.
Figure 2. XR-L567 Generalized Connection Diagram
DEFINITION OF DEVICE PARAMETERS
Largest Detection Bandwidth
Center Frequency to
The largest detection bandwidth is the largest frequency range within which an input signal above the threshold voltage will cause a logical zero stage at the output.
The maximum detection bandwidth corresponds to the
lock range of the PLL.
fo is the free-running frequency of the currentcontrolled oscillator with no input signal. It is determined by resistor Rl between Pins 5 and 6, and capacitor Cl from Pin 6 to ground. fo can be approximated by
Detection Band Skew
fo " _l_Hz
R1 Cl
The detection band skew is a measure of how accurately the largest detection band is centered about the
center frequency, fo . This parameter is graphically illustrated in Figure 4. In the figure, fmin and f max correspond to the lower and the upper ends of the largest detection band, and fl corresponds to the apparent center of the detection band, and is defined as the
arithmetic average of fmin and f max and fo is the freerunning frequency of the XR-L567 oscillator section.
The bandwidth skew, .a.fx, is the difference between
these frequencies. Normalized to fo, this bandwidth
skew can be expressed as:
where Rl is in ohms and Cl is in farads.
Detection Bandwidth (BW)
The largest detection bandwidth is the frequency range
centered about fo, within which an input signal larger
than the threshold voltage (typically 20 mV rms) will
cause a logic zero state at the output. The detection
bandwidth corresponds to the capture range of the PLL
and is determined by the low-pass loop filter at Pin 2.
Typical dependence of detection bandwidth on the filter capacitance and the input signal amplitude is shown
in Figures 10 and 11, or may be calculated by the approximation
VI (RMS)
BW (%) .. 338
Fo(Hz)' C2 (,.F)
Bandwidth Skew
= .a.fx = (fmax +
fo
fmin - 2fo)
2fo
INPUT
201111
OUTPUT
OUTPUT
"Adjus' for fo
Ii
Response to 100 mV rms tone burst.
RL = lK ohms
= to kHz
= 1011Hz. +5V
Figure 3. lYplcal Output Response to 100 mY Input
Tone-Burst
Figure 1. XR-L567 Test Circuit
1-57
XR·L567
If necessary, the detection band skew can be reduced
to zero by an optional centering adjustment. (See Optional Controls.)
I~
OUTPUT
LOGIC LEVEL
LARGEST DETECTION
BAND
L=l
[:"NG
FREQUENCY
II
to 11
fO = PLl free-running frequency
If the value of C3 becomes too large, the turn-on or
turn-off time of the output stage will be delayed until the
voltage change across C3 reaches the threshold voltage. In certain applications, the delay may be desirable
as a means of suppressing spurious outputs. Conversely, if the value of C3 is too small, the beat rate at
the output of the quadrature detector may cause a
false logic level change at the output (Pin 8).
~I
-l ~
'min
stant of the filter can be expressed as T3 = R3C3,
where R3 (47 kO) is the internal impedance at Pin 1.
fmn
1m . .
The average voltage (during lock) at Pin 1 is a function
of the in-band input amplitude in accordance with the
given transfer characteristic.
+ 'min
11 '" Center freq. of detection blind = - - -
2
Figure 4. Definition of Bandwidth Skew
Logic Output (Pin 8)
DESCRIPTION OF CIRCUIT CONTROLS
Terminal 8 provides a binary logic output when an input
signal is present within the pass-band of the decoder.
The logic output is an uncommitted, open-collector
power transistor capable of switching high current
loads. The current level at the output is determined by
an external load resistor, RL, connected from Pin 8 to
the positive supply.
Input (Pin 3)
The input signal is applied to Pin 3 through a coupling
capacitor. This terminal is internally biased at a dc level
2 volts above ground, and has an input impedance level
of approximately 100 kll.
When an in-band signal is present the output transistor
at Pin 8 saturates with a collector voltage of less than
0.6V at full rated output current of 10 mAo If large output voltage swings are needed, RL can be connected to
a supply voltage, V +, higher than the VCC supply. For
safe operation, V + :515 volts.
Timing Resistor R1 and Capacitor C1 (Pins 5 and 6)
The center frequency of the decoder is set by resistor
R1 between Pins 5 and 6, and capacitor C1 from Pin 6
to ground, as shown in Figure 2.
Pin 5 is the oscillator squarewave output which has a
magnitude of approximately VCC - 1.4V and an average dc level of VCcJ2. A 5 kO load may be driven from
this point. The voltage at Pin 6 is an exponential triangle
waveform with a peak-to-peak amplitude of '" (VCC 1.3)/3.5 volts and an average dc level of VCcJ2. Only
high impedance loads should be connected to Pin 6 to
avoid disturbing the temperature stability or duty cycle
of the oscillator.
OPERATING INSTRUCTIONS
Selection of External Components
A typical connection diagram for the XR-L567 is shown
in Figure 2. For most applications, the following procedure will be sufficient for determination of the external
components R1, C1, C2, and C3·
1. R1 and C1 should be selected for the desired center
frequency by the expression fo '" 1/R1C1. For optimum temperature stability, R1 should be selected
such that 20 kO :5 R1 :5 200 kO, and the R1C1 product should have sufficient stability over the projected operating temperature range.
Loop Filter-C2 (Pin 2)
Capacitor C2 connected from Pin 2 to ground serves as
a single pole, low-pass filter for the PLL portion of the
XR-L567. The filter time constant is given by T2 =
R2C2, where R2 (100 kO) is the impedance at Pin 2.
2. Low-pass capacitor, C2, can be determined from the
Bandwidth versus Input Signal Amplitude graph of
Figure 10. One approach is to select an area of operation from the graph, and then adjust the input level and value of C2 accordingly. Or, if the input amplitude variation is known, the required f oC2 product
can be found to give the desired bandwidth. Constant bandwidth operation requires Vi > 200 mV
rms. Then, as noted on the graph, bandwidth will be
controlled solely by the f oC2 product.
The selection of C2 is determined by the detection
bandwidth requirements, as shown in Figure 10. For
additional information see section on "Definition of Device Parameters."
The voltage at Pin 2, the phase detector output, is a linear function of frequency over the range of 0.95 fo to
1.05 fo, with a slope of approximately 20 mV/% frequency deviation.
Output Filter-C3 (Pin 1)
3. Capacitor C3 sets the band edge of the low-pass filter which attenuates frequencies outside of the detection band and thereby eliminates spurious outputs. If C3 is too small, frequencies adjacent to the
Capacitor C3 connected from Pin 1 to ground forms a
simple low-pass post detection filter to eliminate spurious outputs due to out-of-band signals. The time con-
1-58
XR·L567
der this condition, the lock-up transient is in a worst
case situation, and the minimum theoretical lock-up
time will not be achievable.
detection band may switch the output stage off and
on at the beat frequency, or the output may pulse off
and on during the turn-on transient. A typical minimum value for C3 is 2 C2.
The following expressions yield the values of C2 and
C3, in microfarads, which allow the maximum operating
speeds for various center frequencies where fo is Hz.
Conversely, if C3 is too large, turn-on and turn-off of
the output stage will be delayed until the voltage
across C3 passes the threshold value.
C2 = ~ , C3 = 26 "F
fo
fo
Precautions
1. The XR-L567 will lock on signals near (2n + 1) fo
and produce an output for signals near (4n + 1) fo ,
for n = 0,1 ,2-etc. Signals at 5 fo and 9 fo can
cause an unwanted output and should, therefore, be
attenuated before reaching the input of the circuit.
The minimum rate that digital information may be detected without losing information due to turn-on transient or output chatter is about 10 cycles/bit, which corresponds to an information transfer rate of fo/10 baud.
In situations where minimum turn-off is of less importance than fast turn-on, the optional sensitivity adjust·
ment circuit of Figure 5 can be used to bring the quiescent C3 voltage closer to the threshold voltage. Sen·
sitivity to beat frequencies, noise, and extraneous
signals, however, will be increased.
2. Operating the XR-L567 in a reduced bandwidth
mode of operation at input levels less than 200 mV
rms results in maximum immunity to noise and outband signals. Decreased loop damping, however,
causes the worst-case lock-up time to increase, as
shown by the graph of Figure 13.
+V
3. Bandwidth variations due to changes in the in-band
signal amplitude can be eliminated by operating the
XR-L567 in the high input level mode, above 200 mV.
The input stage is then limiting, however, so that outband signals or high noise levels can cause an apparent bandwidth reduction as the in-band signal is
suppressed. In addition, the limited input stage will
create in-band components from subharmonic sig·
nals so that the circuit becomes sensitive to signals
at fo/3, fo/5 etc.
r:::)R
t:fir
DECREASE
SENSITIVITY
XR-L567
C3
INCREASE
SENSITIVITY
_
+V
DECREASE
SENSITIVITY
XR·L567 t-.-.VIIV+<,=: ~
4. Care should be exercised in lead routing and lead
lengths should be kept as short as possible. Power
supply leads should be properly bypassed close to
the integrated circuit and grounding paths should be
carefully determined to avoid ground loops and undesirable voltage variations. In addition, circuits requiring heavy load currents should be provided by a
separate power supply, or filter capacitors increased
to minimize supply voltage variations.
INCREASE
SENSITIVITY
SILICON
DIODES FOR
} TEMPERATURE
COMPENSATION
(OPTIONAL)
Figure 5. Adjustable Sensitivity Connections
OPTIONAL CONTROLS
Chatter
Programming
When the value of C3 is small, the lock transient and ac
components at the lock detector output may cause the
output stage to move through its threshold more than
once, resulting in output chatter.
Varying the value of resistor R1 and/or capacitor C1 will
change the center frequency. The value of R1 can be
changed either mechanically or by solid state switches.
Additional C1 capacitors can be added by grounding
them through saturated npn trallsistors.
Although some loads, such as lamps and relays will not
respond to chatter, logic may interpret chatter as a series of output signals. Chatter can be eliminated by
feeding a portion of the output back to the input (Pin 1)
or, by increasing the size of capacitor C3. Generally, the
feedback method is preferred since keeping C3 small
will enable faster operation. Three alternate schemes
for chatter prevention are shown in Figure 6. Generally,
it is only necessary to assure that the feedback time
constant does not get so large that it prevents operation at the highest anticipated speed.
Speed of Response
The minimum lock-up time is inversely related to the
loop frequency. As the natural loop frequency is lowered, the turn·on transients becomes greater. Thus
maximum operating speed is obtained when the value
of capacitor C2 is minimum. At the instant an input sig·
nal is applied, its phase may drive the oscillator away
from the incoming frequency rather than toward it. Un·
1-59
XR·L567
+y
+V
~
XR-LS67
15
+v
+y
.
.L
S!
0
I .
,
1
i.
• C,
Iii
.A
tOOK
~
2K 10 10K
'OPTIONAL -
10
z
,.
Cl
.....
I
•
~
PERMITS
~
LOWER VALUE OF C,
o
10 Hz
Figure 6. Methods of Reducing Chatter
1 kHz
10 kHz
100 kHz
CENTER FREOUENCY
Skew Adjustment
Figure 9. Largest Detection Bandwidth Versus
Operating Frequency
The circuits shown in Figure 7 can be used to change
the position of the detection band (capture range) with·
in the largest detection band (lock range). By moving
the detection band to either edge of the lock range, in·
put signal variations will expand the detection band in
one direction only. Since R3 also has a slight effect on
the duty cycle, this approach may be useful to obtain a
precise duty cycle when the circuit is used as an oscil·
lator.
105
•
!
...
1
.1
104
~
r:::).
l::1ir
~
Ii:
+v
LOWERS '0
100 Hz
Ii:
•
!
1
103
~~
....... ......... .......
1
102
+v
.,
I'-. I'-. ....... C3
~
C2
-=-
t
RAISES
•
10
.....
12
C2
14
18
BANDWIDTH - % OF 10
LOWERSfO
I-
E 200
1
E
III
"......
c
...=>~
A!
II:
II:
=>
u
Ii:
250
AA-
150
100
OPTIONAL
SENSITIVITY
50
ADJUSTMENT
REOUIRED
10
BANDWIDTH - .,. OF
12
14
16
to
10
SUPPLY VOLTAG~ - VOLTS
Figure 11. Bandwidth Versus Inpqt Signal Amplitude
(C21n /-IF)
Figure 8. Supply Current Versus Supply VoHage
1·60
XR·L567
IS
1000
14
lU
Ii
~
10
I
500
10
400
300
7.5
•
•
5.0
4
it
I
%
12
..
'\
~
u 100
r;
50
40
30
r-
2
2.5
"
200
BANDWIDTH LIMITED
BYC2
1\
"
(MINIMUM C2)
10
-75 -SO -25
0 +25 +50 +75 +100 +125
I
TEMPERATURE. 'C
I
1
0.7
100
to)
o
It
I
0.6
0.5
~
d
....
u
u
> 0.4
..,
~
20304050
100
0.'
l,
10
Figure 13. Greatest Number of Cycles Before Output
1.0
0.9
g
2345
BANDWIDTH (% DF
Figure 12. Bandwidth Variation With Temperature
~
BANDWIDTH
LIMITED BY _
" K/;~~~::~-
20
BANDWIDTH AT 25"C
o
1
~
-100
'\
-200
~~
0.2
c
0.1
o
0.1
0.20.30.40.5 1.0
2 3 4 5
-400
-500
-25
10
,
1\
~
'" -300
0.3
CENTER FREQUENCY - kHz
o
25
50
75
TEMPERATURE. C
Figure 14. Power Supply Dependence of Center Frequency
........
Figure 15. Typical Center Frequency Drift With Temperature
(V+ = 5V, R1 = 80 kO, fo = 1 kHz)
I"- ~
!"-to =
r-
Y+
t
I
5Y
kHZ~
I
"
r'\
~ [\
to = 10 kHz'
I
25
50
~
75
TEMPERATURE. 'C
Figure 16. lYpical Frequency Drift as a Function of
Temperature
1·61
XR·2567
Dual Monolithic Tone Decoder
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-2567 is a dual monolithic tone decoder of the
567-type that is ideally suited for tone or frequency decoding in multiple-tone communication systems. Each
decoder of the XR-2567 can be used independently or
both sections can be interconnected for dual operation. The matching and temperature tracking characteristics between decoders on this monolithic chip are
superior to those available from two separate tone decoder packages.
The XR-2567 operates over a frequency range of 0.01
Hz to 500 kHz. Supply voltages can vary from 4.5V to
12V, with internal voltage regulation provided for supplies between 7V and 12V. Each decoder consists of a
phase-locked loop (PLL), a quadrature AM detector, a
voltage comparator, and a logic compatible output that
can sink more than 100 mA of load current.
Operating Temperature
XR-2567M
XR-2567C
Storage Temperature
The center frequency of each decoder is set by an external resistor and capacitor which determine the freerunning frequency of each PLL. When an input tone is
present within the passband of the circuit, the PLL
"locks" on the input signal. The logic output, which is
normally "high", then switches to a "low" state during
this "lock" condition.
ORDERING INFORMATION
FEATURES
Replaces two 567-type decoders
Excellent temperature tracking between decoders
Bandwidth adjustable from a to 14 %
Logic compatible outputs with 100 mA sink capability
Center frequency matching (1 % typ.)
Center frequency adjustable from 0.01 Hz to 500 kHz
Inherent immunity to false triggering
Frequency range adjustable over 20:1 range by
external resistor.
Part Number
Package
Temperature Range
XR-2567M
XR-2567CN
XR-2567CP
Ceramic
Ceramic
Plastic
- 55°C to + 125°C
O°C to + 70°C
O°C to + 70°C
SYSTEM DESCRIPTION
The XR-2567 dual monolithic tone decoder consists of
two independant 567-type circuits and an on board voltage regulator. Each decoder has a phase detector, low
pass filter, and current controlled oscillator which comprise the basic phase locked loop, plus an additional
low pass filter and quadrature detector enabling detection of in-band signals. Both devices have normally high
open collector outputs capable of sinking 100 mAo
APPLICATIONS
Touch-Tonel» Decoding
Sequential Tone Decoding
Dual-Tone Decoding/
Encoding
Communications Paging
Ultrasonic RemoteControl and Monitoring
- 55°C to + 125°C
O°C to + 70°C
- 65°C to + 150°C
Full-Duplex Carrier-Tone
Transceiver
Wireless Intercom
Dual Precision
Oscillator
FSK Generation and
Detection
The input signal is applied to Pin 14 (device A) or Pin 11
(device B), both with 20 kO nominal input resistance.
Free running frequency is controlled by an RC network
at Pins 1 and 16 (device A) or Pins 8 and 9 (device B). A
capacitor on Pin 2 (A), or Pin 7 (B) serves as the output
filter and eliminates out-of-band triggering. PLL filtering
is accomplished with a capacitor on Pin 15 (A), or Pin
10 (B): bandwidth and skew are also dependant upon
the circuitry here. Bandwidth is adjustable from 0% to
14 % of the center frequency. Pin 13 is + VCC (4.75 to
12V nominal, 14V maximum): Pin 7 is ground: and Pin 3
(A) or Pin 6 (B) is the open collector output, pulling low
when an in-band signal triggers the device.
ABSOLUTE MAXIMUM RATINGS
Power Supply
With Internal Regulator
14V
Without Regulator (Pins 12 and 13 shorted)
10V
Power Dissipation
Ceramic Package
750mW
Derate Above + 25°C
6 mW/oC
Plastic Package
625 mW/oC
Derate Above +25°C
5.5 mW/oC
Voltage supplies below 7V necessitate bypassing the
internal regulator. This is accomplished by shorting Pin
12 to VCC: for supplies over 7V, a bypass capacitor of
at least 1 fJ-F should AC ground Pin 12.
1-62
XR·2567
ELECTRICAL CHARACTERISTICS
Tesl Conditions: Vee = +5V, TA
= 25° e, unless otherwise specified.Test circuit of Figure 2, 81 closed unless
otherwise specified.
LIMITS
PARAMETERS
MIN
TYP
MAX
UNITS
7
12
Vdc
Vdc
16
20
26
30
15
-10
Vee+ 0.5
mA
mA
mA
mA
V
V
V
CONDITIONS
GENERAL
Supply Voltage Range
Without Regulator
With Internal Regulator
Supply Current (both decoders)
Quiescent XR-2567M
XR-2567C
Activated XR-2567M
XR-2567C
Output Voltage
Negative Voltage at Input
Positive Voltage at Input
4.75
6.5
12
14
22
24
See Figure 5. SI closed.
See Figure 5, SI open.
See Figure 7, 8
RL = 20 Idl
RL = 20 kll
RL = 20 kll
RL =20 kll
CENTER FREQUENCY (each decoder section)
Highest Center Frequency
Center Frequency Stability
Temperature TA = 25°C
0° M/V
Cc COUPLING CAPACITOR
Co BYPASS CAPACITOR
f
"'oB
5, OPEN FOR 7V TO 12V
OPERATION CLOSED
FOR 4.5V TO 7V OP,ERATION
Figure 4. Circuit Connection Diagram
For decoder section A, the oscillator output can be obtained at either Pin 1 or 16. Pin 16 is the oscillator
squarewave output which has a magnitude of approximately Vee -. 1.4V and an average dc level of Vcct2. A
1 kG load may be driven from this point. The voltage at
Vi
foC2
where Vi is the input signal in volts, rms, and C2 is the
capacitance in "F at Pins 10 or 15.
1-64
XR·2567
TYPICAL CHARACTERISTICS
'000
.---,---,----,r---,--..,
0.'
800
~
z
0
~
t=
600
~
I
0.7
I
0.5
S
~
C 400
~
60r---,--,---,---,--,---,
'.0
0.'
~
0.6
o. 4
,
/
.,,
o.
4
"
6
SUPPLY VOLTAGE,
v· /VOL TS)
.-
0V
.
10 KHz
100 KHz
CENTER fREQUENCY
51~
I\-
20
2
3 4 5
BANDWIDTH - " Of
20 30 4050
,0'
3.0
2.0
~
1.0
~ -1.0
Vcc" 5.75V I
I>\.
Vcc· 7.0V
~ -3.0
11
11
~ -4.0
-5.0
-75
-50
-25
0
25
50
'.0
:::::
,..
r-
-15
-25
100
r-
-"-
.~
..... r--
r.....
.......
.......
~
~
~
-200
'0·' kHz
~ -300
100
4.6
125
5.0
5.'
'.0
..•
,',
7.0
SUPPLY VOLTAGE - VOLTS
TEMPERATURE T I'CI
Figure 15. Temperature Coefficient 01
Center Frequency (Mean and S.D.)
Figure 14. Frequency Drill With
Temperature
1-65
'15
+100 +125
Figure 13. Bandwidth Variation With
Temperature
!
75
25
TEMPERATURE -'C
"
~
..
BANDWIDTH AT 25"C
•
16
14
11-:: I~ f If-... 1/ 1',
-2.0
~
r-- c,
12
VCC'" 4.75V,
:;...~ ~-
7.6
to
~
'o·,kHz
z
~
':40
10
Figure 12. Detection Bandwidth as a
Function 01 C2 and C3
!i
z
o
BANDWIDTH - "Of
Figure 11. Greatest Number 01
Cycles Before Output
~
,
%
5
~
I'--
100
"
12.5
.
l"- f'.
f'. 1'- r--. c,
BANOWIDTH 1%0' '01
fa
~
~ (\
'"
~
~
~
~
Figure 10. Bandwidth vs. Input
Signal Amplitude (C2 in ,..F)
...
ANDWIDTH LIMITED BY
~TERNAt..RESISTOR
(MINIMUM C21
10
" "$
,.
BYC 2
"\.
~
'],
1 MHz
Figure 9. Largest Detection
Bandwidth
~ANDWIDTH LIMITED
40
0
1 KHz
,OB
30
x
o
100Hz
/VOLTSI
500
1"-
'],
-
'000
'\
'],
'], '],
1\
Figure 8. Total Supply Current vs.
Supply Voltage for Operation with
Internal Regulator (Pins 12 and 13
Not Connected)
"
v· (VOLTSj
Figure 7. Total Supply Current vs.
Supply Voltage lor Operation Without
Internal Regulator (Pins 12 and 13
Shorted)
'00 r--r-,r-,--,-;--,--"
,
,.
v+
7
>--
CURRENT
SUPPLY VOLTAGE.
.
5
SUPPLY VOLTAGE,
0
CNUOR~~~~ "'-
"ON"
0
100
,'"
20 304050
OPER~TlNG ~ANGE
oV ~,
~
10
RECOJMENDE'D
WITH REGULATOR
0
;
345
6
•
,'"
2
./
Figure 6. Power Supply Dependence
01 Center Frequency
.
400
f-"
CENTER fREQUENCY - kHz
Figure 5. Internal Power Dissipation
VS. Supply Voltage. Both Units
Activated. RL = 20 k
'00
40
1/
0.3
o.
'00
60r-~--~---+---+---r--~
I
I
XR·2567
LOGIC OUTPUT (Pins 3 and 6)
pin 1 is an exponential triangle waveform with a peakto-peak amplitude of 1 volt and an average dc level of
VCcJ2. Only high impedance loads should be connected to Pin 1 to avoid disturbing the temperature stability
or duty cycle of the oscillator. For section B, Pin 9 is the
squarewave output and Pin 8 the exponential triangle
waveform output.
Output terminals 3 and 6 provide a binary logic output
when an input signal tone is present within the
detection-band of each respective decoder section.
The logic outputs are uncommitted "bare-collector"
power transistors capable of switching high current
loads. The current level at the output is determined by
an external load resistor, RL, connected from Vee to
Pins 3 or 6.
LOOP FILTER, C2 (Pins 10 and 15)
Capacitors C2A and C2B connected from Pins 15 and
10 to ground are the single-pole, low-pass filters for the
PLL portion of decoder sections A and B. The filter time
constant is given by T2 = R2C2, where R2 (10 kll) is the
impedance at Pins 10 or 15. The selection of C2 is determined by the detection bandwidth requirements and
input signal amplitude as shown in Figures 10 and 12.
One approach is to select an area of operation from the
graph and then adjust the input level and value of C2
accordingly. Or, if the input amplitude variation is
known, the required foC2 product can be found to give
the desired bandwidth. Constant bandwidth operation
requires Vi >200 mV rms. Then, as noted in Figure 10,
bandwidth will be controlled solely by the f oC2 product.
(For additional information, see Optional Controls Section, "Speed of Response" and "Bandwidth Reduction".)
When an in-band signal is present, the output transistor
at Pins 3 or 6 saturates with a collector voltage less
than 1 volt (typically 0.6V) at full rated current of 100
mAo If large output voltage swings are needed, RL can
be connected to a supply voltage, V + higher than the
VCC supply. For safe operation, V + s 15 volts.
REGULATOR BY-PASS (Pin 12)
This pin corresponds to the output of the voltage regulator section. For circuit operation with a supply voltage
greater than 7V, Pin 12 should be ac grounded with a
bypass capacitor ~ 1 /LF. For circuit operation over a
supply voltage range of 4.5 to 7V, the voltage regulator
section is not required; Pin 12 should be shorted to
VCC·
GROUND TERMINALS (Pins 4 and 5)
Pins 10 and 15 correspond to the PLL phase detector
outputs of sections A and B, respectively. The voltage
level at these pins is a linear function of frequency over
the range of 0.95 to 1.05 fo, with a slope of approxi·
mately 20 mV/% frequency deviation.
To eliminate parasitic interaction, each decoder section
has a separate ground terminal. The internal regulator shares a common ground with decoder section A
(Pin 4).
OUTPUT FILTER, C3 (Pins 2 and 7)
Independent ground terminals also allow additional
flexibility for split supply operation. Pin 4 can be used as
V -, and Pin 5 as ground, as shown in Figure 16. When
the circuit is operated with split supplies, the positive
supply should always be > 6V, and the dc potential
across Pins 13 and 14 should not exceed 15 volts.
Capacitors C3A and C3B connected from Pins 2 and 7
to ground form low-pass post detection filters for sections A and B respectively. The function of the post de·
tection filter is to eliminate spurious outputs caused by
out-of-band signals. The time constant of the filter can
be expressed as T3 = R3C3, where R3 (4.7 k) is the internal impedance at Pins 2 or 7.
V'
The precise value of C3 is not critical for most applica·
tions. To eliminate the possibility of false triggering by
spurious signals, a minimum value for C3 is 2C2, where
C2 is the loop filter capacitance for the corresponding
decoder section. If C3 is smaller than 2C2, then frequencies adjacent to the detection band may switch
the output stage "off" and "on" at the beat frequency,
or the output may pulse "off" and "on" during the turnon transient.
"FOR OPERATION WITH v'~' 7V,
SHORT PINS 12AND 13
RLS
t-1.j--+-O
OUTPUT
V'OR
8
r
v'
JGROUND
GROUND
-:
t-1.j--+--O
INOTE
If the value of C3 becomes too large, the turn-on or
turn-off time of the output stage will be delayed until the
voltage change across C3 reaches the threshold voltage. In certain applications, this delay may be desirable
as a means of suppressing spurious outputs. (For additional information, see Optional Controls Section,
"Speed of Response" and "Chatter".)
r
"LA
OUZUT
-l v-
v' OR GROUND
DC VOllA{iE AT PIN 4
MUST ALWAYS BE '. PIN &1
Figure 16. Split-Supply Operation Using Independent Ground
Terminals of Units A and B. Unit A Operates
Between V+ and V-; Unit B Operates Between
V+ and Ground
.
1-66
XR·2567
OPTIONAL CONTROLS
"
"
v'
200 TO lK
The minimum lock-up time is inversely related to the
loop frequency. As the natural loop frequency is lowered, the turn-on transient becomes greater. Thus, maximum operating speed is obtained when the value of capacitor C2 is minimum. At the instant an input signal is
applied, its phase may drive the oscillator away from
the incoming frequency rather than toward it. Under
this condition, the lock-up transient is in a worst case
situation, and the minimum theoretical lock-up time will
not be achievable.
LOWER VALUE Of CI
Figure 18. Methods of Reducing Chatter
SKEW ADJUSTMENT
The circuits shown in Figure 19 can be used to change
the position of the detection band (capture range) within the largest detection band (or lock range). By moving
the detection band to either edge of the lock range, input signal variations will expand the detection band in
one direction only. Since R3 also has a slight effect on
the duty cycle, this approach may be useful to obtain a
precise duty cycle when the circuit is used as an oscillator.
= 130, C3 = 260
fo
'.
200 TO lK
'OPTIONAl- PERMITS
The following expressions yield the values of C2 and
C3, in microfarads, which allow the maximum operating
speeds for various center frequencies. The minimum
rate that digital information may be detected without
losing information due to turn-on transient or output
chatter is about 10 cycles/bit, which corresponds to an
information transfer rate of fo/l0 baud.
C2
"
'.
SPEED OF RESPONSE
fo
In situations where minimum turn-off time is of less importance than fast turn-on, the optional sensitivity adjustment circuit of Figure 17 can be used to bring the
quiescent C3 voltage closer to the threshold voltage.
Sensitivity to beat frequencies, noise, and extraneous
Signals, however, will be increased.
"
}'"''''
'"
DIODES
TeMPERATURE
COMPENSAnON
iOPTIONAU
Of CR~ AS!
SHISllIVITV
"
Kh-~N'~;:K :
Figure 19. Connections to Reposition Detection Band
IfIICREI\SE
Re
SENSITIVITY
) ""00'
DIODES
OUTPUT LATCHING
~OR
TEMPERATURE
COMPENSATION
IOPTlONAl!
After a signal is received, the output of either decoder
section can be latched "on" by connecting a 20 kO resistor and diode from the "output" terminal to the "output filter" terminal as shown in Figure 20. The output
stage can be unlatched by raising the voltage level at
the output filter terminal.
Figure 17. Optional Connections for Sensitivity Control
CHATTER
"
When the value of C3 is small, the lock transient and ac
components at the lock detector output may cause the
output stage to move through its threshold more than
once, resulting in output chatter.
"
"
"""
Although some loads, such as lamps and relays will not
respond to chatter, "logic" may interpret chatter as a
series of output signals. Chatter can be eliminated by
feeding a portion of the output back to the input or, by
increasing the size of capacitor C3. Generally, the feedback method is preferred since keeping C3 small will
enable faster operation. Three alternate schemes for
chatter prevention are shown in Figure 18. Generally, it
is only necessary to assure that the feedback time constant does not get so large that it prevents operation at
the highest anticipated speed.
C,,'flEVENTStATCHVP
WHEN POWER SUPPLY IS
TUANEDON
Figure 20. Output Latching
POSITIONING OF DETECTION BANDS
Figure 21 defines the respective band-edge and bandcenter frequencies for sectiOnS A and B of the dual tone
decoder.
1-67
XR·2567
Frequencies fL and FH with appropriate subscripts refer to the low and the high band-edge frequencies for
decoder sections A and B, and fo is the center frequency.
I
DETECTION BAND
OFUN'TA
I
I
DETECTION 8ANO
OFUNITB
,.,
foe
II
'"
1/
1f"1/ II/, ~
;-::: .....
~-
I
ll~
a
loA
I'" I'" I'"
/1/
I",
V
-
II"
r'
OPTtONALSILICON
I ,,~
.......
,'"
DETECT'ONIAND-"'~IO
_
PINta
OR 15
OIODESFOI!
TE"PEFIATUIIE
COW'ENSATlOIrI
l~ (!...~ii~!) o.c,..:
tr,; p~.~.!I)
NOTE" ADJUST CONTIIOl FOR
SVMMlTII.~
0'
DETECTION lAND EOGES ABOUT '0
Figura 22. Bandwidth Raductlon
FREOUENCV
(a) Independent Detection of 1Wo Separate Tones
APPLICATIONS
I
TOTAL DE:e::ION lAND
I
DUAL·TONE DETECTION
ll~
5
loA
'08
In most dual-tone detection systems, the decoder output is required to change state only when both input
tones are present simultaneously. This can be implemented by setting the detection bandwidth of each of
the XR-2567 decoder sections to cover one of the input
tones; and then connecting the respective outputs
through a NOR gate, as shown in Figure 23. In this
case, the output of the NOR gate will be "high" only
when both input tones are present simultaneously.
_
FREOUENCY
(b) Addition of Detection Bandwidth for Wide-Band
Detection
TOTAL DETECTION
-"1
BAND
j-
l§--~~
foA
f,B
FREOUENCY
(c) Subtraction of Bandwidths for Narrow·Band Detection
Figura 21. Positioning of Detactlon Bands
The two sections can be interconnected to form a single tone detector with an overall detection bandwidth
equal to the sum or the difference of the detection
bands for the two individual detector sections. For example, if the individual decoder sections are interconnected as shown in Figure 25, then the total detection
bandwidth would be approximately equal to the sum of
the respective bandwidths as shown in Figure 21 (b).
Similarly, if the decoders are interconnected as shown
in Figure 23, then the overall detection band would be
equal to the difference, or the overlap, between the respective bandwidths as shown in Figure 21(c).
lJ4SN1402
Figura 23. Connection for Decoding Dual·Tone Encoded Input
Signals
BANDWIDTH REDUCTION
Figure 24 shows additional circuit configurations which
can be used for decoding multiple-tone input signals, In
Figure 24(a), the output of Unit A is connected to the
output filter (Pin 7) of Unit B through the diode 01. If no
The bandwidth of each decoder can be reduced by either increasing the loop filter capacitor C2 or reducing
the loop gain. Increasing C2 may be an undesirable solution since this will also reduce the damping of the
loop and thus slow the circuit response time.
input tone is present within the detection-band of Unit
A, then its output (pin 3) is "high", which keeps diode
Figure 22 shows the proper method of reducing the
loop gain for reduced bandwidth. This technique will improve damping and permit faster performance under
narrow band operation. Bandwidth reduction can also
be obtained by subtracting overlapping bandwidths of
the two decoder sections (see Figures 21(c) and 23).
01 conducting and "disables" Unit B by keeping its output (pin 6) "high". If an input tone is present within the
detection-band of Unit A, Pin 3 is low, diode D1 is reverse biased, and decoder B is no longer disabled. If
under these conditions an input signal is' present within
the detection-band of Unit B, then its output at Pin 6
would be "low". Thus, the output at Pin 6 is "low" only
1-68
XR·2567
SEQUENTIAL TONE DECODING
when input tones within the detection-band of A and B
are present simultaneously.
The dual-tone decoder circuit of Figure 24(b) makes
use of the split-ground feature of the XR-2567. The output terminal of Unit A is used as a "switch" in series
with the ground terminal (Pin 5) of Unit B. If the input
tone A is not present, Pin 3 is at its high-impedance
state, and the ground terminal of Unit B is opencircuited. When the input tone A is present, Pin 3 goes
to a low-impedance state and Unit B is activated. In this
manner, the output of Unit B will be "low" only when
both tones A and B are present.
Dual-tone decoder circuits can also be used for sequential tone decoding where one tone must be present
before the other for the circuit to operate. This can be
achieved by making the output filter capacitance, C3,
of one of the sections large with respect to the other.
For example, in the circuits of Figures 24(a) and 24(b), if
C3A is chosen to be much larger than C3B (C3A ;;:
C3B), then Unit A will remain "on" and activate B for a
finite time duration after tone A is terminated. Thus, the
circuit will be able to detect the two tones only if they
are present sequentially, with tone A preceding tone B.
In the circuit connection of Figure 24(b), Unit B does
not draw any current until it is activated. Therefore, its
power dissipation in a stand-by condition is lower than
other dual-tone decoder configurations. However, due
to finite series resistance between Pin 3 and ground
when Unit B is activated, the output current sink capability is limited to s 10 mA.
The circuit of Figure 24(a) can also be modified for sequential tone decoding by addition of a diode, D2, between pins 3 and 6. Once activated by Unit A, Unit B
will stay "on" as long as tone B is present, even though
tone A may terminate. Once tone B disappears, the circuit is reset to its original state and would require tone
A to be present for activation.
HIGH·SPEED NARROW·BAND TONE DECODER
"IA
The circuit of Figure 23 can be used as a narrow-band
tone decoder by overlapping the detection bands of
Units A and B (see Figure 21(c)). The output of the NOR
gate will be high only when an input signal is present
within the overlapping portions of the detection band.
To maintain uniform response within the pass-band, the
input signal amplitude should be ----o"ItOATA
Figure 7
1-88
DEMODULATION TECHNIQUES
The output jitter is usually specified in percent, indicating what percentage of the bit frame the peak to peak
jitter is.
Once data has been encoded onto a carrier, Txcar, by
the modulator in either FSK or PSK formats, the receiving modem (answer mode) must decode or demodulate
this received carrier, Rxcar. For FSK encoding, analog
and digital techniques are used for demodulation. Popular analog schemes often employ PLL type demodulation. Using this method, illustrated in Figure 7, a PLL
locks to the incoming FSK frequencies and produces
two different DC error voltages at the phase detector
output. These voltages are compared to a reference to
indicate whether the incoming frequencies lie above or
below a reference frequency, or whether they are mark
(high) or space (low) frequencies.
.
[Tmaximum - Tminimum]
Jitter =
T
(%)
b
100
FILTER REQUIREMENTS
Filters in modems serve two functions; to filter the modulator output for band limiting and filtering of the received carrier (Rxcar) before the demodulator. Figure
10 illustrates these filter functions.
A second phase detector (quadrature) is often added
whose output, when filtered and sliced, produces a carrier detector (CD) output. This output is active only when
the PLL is in lock, allowing an indication when valid data is present at Rx data.
Figure 10. Transmit/Receive Filtering
The transmit filter is typically a lowpass or bandpass
structure. As this filter is used to bandlimit the modulated carrier, it is usually of low order (lOW number of poles
to zeros). The complexity is defined by the frequency
spectrum generated by the modulator and how well this
has to be confined on the media. For example; telephone lines have restrictions as to the amplitude of frequency even above its narrow 3 kHz band width (see
FCC requirements).
PSK demodulators typically employ one of two popular
schemes, differential digital or coherent demodulation
techniques. The differential scheme examines zero
crossings to determine carrier phase. With coherent
demodulators internal PLl:s are used to lock and to determine the phase of the incoming carrier. Coherent
schemes usually provide better overall performance,
but at the sacrifice of higher circuit complexity and
cost.
The demodulator affects and determines several key
parameters of the modem. The demodulation process
adds several degradations to the other originally transmitted data. One, Bias distortion, illustrated in Figure 8, is
easiest seen in an alternating 0,1,0,1 ... data pattern.
This pattern should have equal times for each bit, high
(1) and low (0) (TlI = Tot).
The receive filter serves two functions: remove noise
from the received signal and more importantly remove
any local modulator signal which gets mixed with the
receiver carrier. Figure 11 illustrates the function of the
receive filter.
An additional block (duplexer) must be considered
when specifying the receive filter. The duplexer acts to
channel the received carrier from the media to the demodulator, A, and channel the transmit carrier to the
media, B (four to two wire conversion). Imperfections in
the duplexer allow some of the Txcar to get into the Rxcar, C. Therefore, to maintain a good SIN (signal to
noise) ratio at the demodulator input, Rxcar, the receive
filter must remove this unwanted local Txcar. An example illustrates the consideration in terminating the complexity of the receive filter. In this case, an FSK, Bell
103 Type, modem is examined, as shown in Figure 11,
with the following requirements:
RICII!YID
_~:...---,
DATA
AX DATA
Figure B. Bias Distortion
Bias distortion describes how far from equal the received data, RXdata, high and low times are:
R~ORX] 100
Bias distortion = [(.5) T1 p;1
(%)
+
Demodulator: fmark = 2225 Hz; fspace = 2025 Hz,
2225 Hz - 2025 Hz
fc=
= 2125Hz
Output jitter is another parameter describing the quality
of the demodulation process. Illustrated in FigL:(e 9
again with an alternating 0,1,0,1 ... data pattern.
2
Rxcar dynamic range = -10 dBm to
-48 dBm
sin at Rxcar = 15 dB
Modulator:
Figure 9
fmark = 1270 Hz, fspace = 1070 Hz,
fc = 1170 Hz
Txcar (B) = - 9 dBm
1-89
.-
"-
"IIDIolA
'IIDA'A
Figure 11. Modem Signal Paths
Because of line impedance variations, 6000 ± 1000 or
more (telephone lines), the duplexer may only be able to
maintain 10 dB of Txcar ejection to the receive filter in·
put. Rxcar will contain more than ·19 dBm of Txcar and
at a minimum, Rxcar = 54 dB [Path (A) has a 6 dB loss
due to termination]. If the receive filter has 0 dB pass·
band gain, to achieve a 15 dB sIn ratio at Rxcar the Tx·
car "bleed through" (Path C) attenuation is calculated
as follows:
T_
T _ _- - - - - - - - - - '
Figure 13. Mode Switching
tent of the transmitted local carrier. An example of prob·
lems caused by the term are seen in the FSK 103 type
modem. If the local modulator is transmitting 1070 Hz,
the second harmonic content (2140 Hz) falls right in the
receive filter's passband. Therefore, the transmit filter
must attenuate this harmonic content to an acceptable
level.
at Rxcar: Signal = 54 dBm
Txcar (C) = ·54 dBm ·15 dBm = ·69 dBm
Attenuation
50 dB
PHONE LINE INTERFACING
= ·10 dBm . (·69 dBm) =
The phone line interfacing has to couple the Txcar onto
the line while removing the Rxcar and channeling it to
the receiver. Figure 14 shows a simple acoustical connection which uses the telephone's internal carbon microphone and speaker.
The filter requirements are illustrated in Figure 12.
Other requirements to consider are filter bandwidth,
which optimally is set close to the FSK baud rate, or
here 300 Hz (small bandwidths can alter the transmit·
ted carrier's spectrum). The phase response or specifically group delay within the passband can degrade the
quality of the Rx data in terms of jitter. The group delay
(GD) is a measure of the difference in time it takes for a
mark or space frequency to pass through the filter. It is
calculated by taking the first derivative of phase, with
respect to frequency:
dlJ
GO = df
Figure 14. Acoustical Coupling
-.
In this connection the telephone headset itself acts as
the duplexer or 2 to 4 wire converter. Attenuation of Tx·
car to Rxcar should be infinite, but mechanical trans·
mission or bleed through may occur and should be con·
sidered.
-00
Typically acoustical coupling is only used for FSK type
modems with low data rates,. 1200 BPS and down. This
is because of the poor quality carbon microphones
found in most telephones.
1070
1170 1210
2021
2t21
The other coupling configuration is the direct connect,
typically design DAA (Direct Access Arrangements). The
OM, shown in Figure 15, serves to:
221
FREQUENCY CKNd
Figure 12. 103 FSK Receive Filter
1. Provide DC isolation between modem and telephone
line·Tl·
Typical differential group delay values for the 103 example are 50 - 300 us over the pass band.
r:--------,
For full or half-duplex modems the receive filter can be
used for transmit filtering of the opposite band, shown
in Figure 13 (mode switching).
T_
An additional filtering requirement for many modems
must be considered. This is the second harmonic con·
Figure 15
1-90
ations. The dotted line in Figure 18 illustrates a compromise line equalization to flatten the effective group delay variation.
2. Provide a ring detect to control the on/off hook
switch-may be manual.
3. Provide a DC current path during off-hook to
"hold" the Line-L 1. This current is monitored by
the telephone company to indicate when someone
is connected to the line.
Direct connection to the telephone line requires FCC approval
as specified in Part 68 of the FCC regulations. One of
the main requirements of this FCC regulation is the
maximum in-band power levels over frequency bands
not only within the 300 to 3000 Hz line bandwidth, but
also above it be restricted to given levels. Figure 19
shows the maximum power levels to be put on the line.
4. Provide transient protection-R1/Z1.
A hybrid transformer is often used in place of the differentially connected op amp to perform the duplexer
function, shown in Figure 16.
Because modems communicate over vast distances often automatically operated, test facilities are often added. These test facilities are used to test the local modem as well as the distant one. Figure 20 illustrates
these functions.
The hybrid transformer, T1, provides better Txcar bleedthrough attenuation (typically 20 dB) but at additional
expense over the op amp duplexer.
I ....
/
0 CGWROU.'OUAL,zrR
"',,-r-.. . J
I
\
I
I
I
I
\
I
I
I
I
Figure 16
COMPLETE MODEM SPECIFICATIONS
'REQUENCY IkMlI
Line Signals received by the modem are often greatly
changed by the media from the originally transmitted
signal at the originating modem. With telephone communications Bell specifies five different lines which appear in standard dial-up lines as shown in Figure 17.
Since which line will appear is totally unknown, the
worst case line (Bell 3002) is generally used for modem
evaluation.
Figure 18. Group Delay Characteristics
Frequency
(KHz) 3.995 to 4.005 4 to to 10 to 25 25 to 40 Above 50
Maximum
Power Level
(dBm)
From Figure 17 it can be seen that severe amplitude
variations can occur on received line Signals. Typically
modems should function with received line Signals from
to -45 dBm (2.2V to 12.3 mVp-p).
-18
-16
-24
-36
-50
Figure 19. FCC Phone Line Restrictions
....-~!
I
a
Group delay also can experience large changes. Figure
18 shows the general shape of the group delay characteristics as a function of frequency. Medium to high
speed modems (PSK encoding) generally use some
kind of equalization to compensate for group delay vari-
'.CA.
cJ'Lf
,,(CliVI
'ILTEII
TIIANIIIIT
.ILTER
H
H
Figure 20. Test Facilities
-- I !
- f'L"DATA
o
ilia DATA
DIGITAL
..--
BELL SCHEDULE
3002
Cl
C2
C4
DCS-S#
Attenuation Characteristic
(referenced to 1000 Hz)
300 to 3000 Hz
-3to+12dB
300 to 2700 Hz
-2 to +6 dB
300 to 3000 Hz
-2 to +6 dB
300 to 3200 Hz
-2to +6dB
300 to 3000 Hz
-1 to +3 dB
Envelope Delay Distortion
(max. "sec)
800 to 2600 Hz
1750 "sec
1000 to 2400 Hz
1000 "sec
1000 to 2600 Hz
500 "sec
1000 to 2600 Hz
300 "sec
1000 to 2600 Hz
100 "sec
800 to 2600 Hz
1750 "sec
600 to 2600 Hz
1500 "sec
800 to 2800 Hz
500 "sec
600 to 2600 Hz
300 "sec
500 to 2800 Hz
3000 "sec
600 to 3000 Hz
1500 "sec
500 to 2800 Hz
600 "sec
500 to 3000 Hz
3000 "sec
Figure 17. Bell Dial-up Line Characteristics
1-91
EXAR CROSS REFERENCE TO MODEM TYPE
STANDARD
XR PART NUMBER
XR-210
XR-2211
XR-2206
XR-2207
XR-14412
XR-2103
XR-2104*
XR-2120
XR-2120A
XR-2121
XR-2122
XR-2123
XR-2125
FUNCTION
FSK Mod or Demod
FSK Demod
FSK Mod
FSK Mod
FSK ModlDemod
FSK Filter
FSK Filter
PSKIFSK Filter
PSKIFSK Filter
PSKIFSK Modulator
PSKIFSK Demodulator
PSK Mod/Demod
Data Buffer
CCITT
BELL
103,
103,
103,
103,
103
103
212A (FSK),
212A (FSK),
212A (FSK),
212A (FSK),
202, NS
202, NS
NS
NS
212A, 103
212A, 103
212A
212A
212A (PSK), 201
212A
V.21, V.23,
V.21 , V.23,
V.21 , V.23,
V.21, V.23,
V.21
NS
NS
NS
NS
V.21
V.22 (needs 1800 Hz notch)
V.22
V.22 (no guard tone generator)
V.22
V.22, V.26, NS
NS = Non Standard
* No Data Available at Time of Printing
EXAR MODEM SUPPORT CIRCUITS
XR PART NUMBER
LINE INTERFACE
XR-1488
XR-1489
OPERATIONAL AMPLIFIERS
XR-082/083
XR-084
XR-094
XR-095
XR-096
XR-146/246/346
XR-1458/4558
XR-3403/3503
XR-4136
XR-4202
XR-4212
XR-4739
XR-4741
TONE DECODERS
XR-567/567A
XR-L567
XR-2567
FUNCTION
Quad Line Driver
Quad Line Receiver
Dual Bipolar JFET Operational Amplifier
Quad Bipolar JFET Operational Amplifier
Quad Programmable Bipolar JFET Operational Amplifier
Quad Programmable Bipolar JFET Operational Amplifier
Quad Programmable Bipolar JFET Operational Amplifier
Programmable Quad Operational Amplifier
Dual Operational Amplifier
Quad Operational Amplifier
Quad Operational Amplifier
Programmable Quad Operational Amplifier
Quad Operational Amplifier
Dual Low-Noise Operational Amplifier
Quad Operational Amplifier
Monolithic Tone Decoder
Micropower Tone Decoder
Dual Monolithic Ton~ Decoder
1-92
XR·14412
FSK Modem System
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-14412 contains all the necessary circuitry to
construct a complete FSK modulator/demodulator
(MODEM) system. Included is circuitry for pinprogrammable frequency bands, either U.S. or foreign
(CCITT) standards for low-speed MODEMS. The
XR-14412 provides T2L-compatible inputs and outputs.
Included in the XR-14412 are features for self-testing
and an echo suppression tone generator. The XR-14412
utilizes complementary MOS technology for low-power
operation.
voo
TTLD
TYPE
ECHO
TXEN
FEATURES
Tx DATA
Simplex, Half-Duplex, and Full-Duplex Operation
Crystal Controlled
Answer or Originate Modes
Single Supply Operation
Self-test Mode
Selectable Data Rates-300, or 600 bps
T2L- or CMOS-Compatible Inputs and Outputs
Echo Suppressor Disable Tone Generator
U.S. or Foreign (CCITT) Compatible
MODE
TXCAA
ORDERING INFORMATION
APPLICATIONS
Stand-Alone MODEMS
Remote Terminals
Acoustical Couplers
Built-in MODEMS
Part Number
Package
XR-14412FP
XR-14412VP
XR-14412FN
XR-14412VN
Plastic
Plastic
Ceramic
Ceramic
Operating
Voltage Range
4.75V
4.75V
4.75V
4.75V
to
to
to
to
15V
6V
15V
6V
SYSTEM DESCRIPTION
The XR-14412 is basically comprised of two main components; the FSK modulator and demodulator. The
modulator serves to convert or encode incoming binary
data into two discrete frequencies. The pair of frequencies generated are determined by which standard (US
or CCITT), and mode (answer or originate), are selected. These frequencies are within a range suitable for
transmission over the telephone lines. The demodulator
performs the opposite function by decoding the received pairs of frequencies into binary data. It also responds to those frequencies selected by the standard
and mode selected. All functions within the XR-14412
are digital and controlled by a master clock. This clock
is generated by an external crystal connected between
the OSCIN and OSCOUT pins. As well as being used internally by the 14412, the clock may be used to clock
other circuitry by using the OSCOUT pin.
ABSOLUTE MAXIMUM RATINGS
Power Supply
XR-14412F
15V
6V
XR-14412V
Any Input Voltage
VDD + .5V to VSS - .5V
Output Current from any Pin
10 mA
(Except Pins 7 or 8)
Output Current from Pin 7 or 8
35 mA
Operating Temperature Range
-40°C to +85°C
Storage Temperature Range
- 65°C to + 150°C
Power Dissipation
Ceramic Package
1000 mW
Derate Above TA = + 25°C
8.0 mW/oC
Plastic Package
625 mW
5.0 mW/oC
Derate Above TA = + 25°C
1-93
XR·14412
ELECTRICAL CHARACTERISTICS
-40°C
SYMBOL
VOL
VOO**
Vdc
PARAMETERS
Output Voltage
VIN=VDD or 0
VOH
"0" Level
5.0
10
15
"1" Level
5.0
10
15
VIN=O orVDD
VIL
liN
Ip
CIN
IT
0.05
0.05
0.05
MAX
0
0
0
0.05
0.05
0.05
-
5.0
10
15
-
-
-
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
3.5
7.0
11.0
0.8
2.75
5.50
8.25
2.0
-
4.95
9.95
14.95
-
-
MIN MAX UNIT
4.95
9.95
14.95
-
0.05
0.05
0.05
-
-
(Pin 7)
(VOL =0.4)
(VOL·=0.5)
(VOL = 1.5)
Vdc
Vdc
Vdc
5.0
10
15
Pins 12, 15 5 to 15
Output Drive Current
(VOH=2.5)
(VOH=9.5)
(VOH= 13.5)
Vdc
1.5
3.0
4.0
"1" Level
(VO=0.5 or 4.5 Vdc)
(VA = 1.0 or 9.0 Vdc)
(Va = 1.5 or 13.5 Vdc)
IOL
4.95
9.95
14.95
5.0
10
15
VIH
IOH
-
+85°C
TYP
MIN MAX MIN
"0" Level
Input Voltage"
(VA = 4.5 or 0.5 Vdc)
(VA = 9.0 or 1.0 Vdc)
(VA = 13.5 or 1.5 Vdc)
+25°C
3.5
7.0
11.0
0.75
-
-
-
-
5
10
15
-0.62
-0.62
-1.8
-
-1.5
-1.0
-3.6
-
-
-0.5
-0.5
-1.5
4.75
10
15
2.3
5.3
15
-
2.0
4.5
13
4.0
10
35
-
Input Current (Pin 15 = VDD)
-
-
-
-
Input Pull-up Resistor Source Current
(Pin 15=VSS, VIN=2.4 Vdc)
Pin 1,2,5,6,10,11,12,13,14
5
285
-
250
460
Input Capacitance
5
10
15
-
-
Total Supply Current
(Pin 15=VDD)
4.5
13
27
-
-
-
ACC
Modulator/Demodulator Frequency
Accuracy
(Excluding Crystal)
5 to 15
V2H
Transmit Carrier Output
2nd Harmonic
5 to 10
10 to 15
VOUT
Transmit Carrier Output
Voltage (RL = 100 kD)
(Pin 9)
5
10
15
tTLH,
tTHL
Receive Carrier Rise and
Fall Times (Pin 1)
5
10
15
-
-
-
15
5.0
4.0
-
-
±0.00001 ±0.1
3.5
7.0
11.0
0.85
-
-
1.6
3.6
10
-
mAdc
-
-
,..Adc
-
pF
-
-
205
5.0
-
-
1.1
4.0
8.0
4.0
12
25
-
-
0.5
-
-20
-25
-26
-32
-
0.2
0.5
1.0
0.30
0.85
1.5
-
-
-
-
-
15
5.0
4.0
-
-
-
-
mAdc
-0.35
-0.35
-1.1 -
,..Adc
-
3.5 mAdc
11
23
-
-
%
-
-
-
-
dB
-
15
5.0
4.0
VRMS
ns
"DC Noise Immunity (VIL,VIH) is defined as the maximum voltage change from an ideal "0" or "1" input level,
that the circuit will withstand before accepting an erroneous input.
""Note: Only 5-Volt specifications apply to XR-14412VP devices.
1-94
XR·14412
EQUIVALENT
SCHEMATIC
DIAGRAM
TRANSMIT
ENABLE'Z
TRANSMJT
OA1'" I'
TTlPULL·UP
DISABLE
15
RECEIVE
CARRIER
RECEIVE
DATA
1
'DO
Figure 1. Typical
C
. of the
XR_144120~nectlOn
10 a Compl t
Modem System
ee
Trans mit. Carrier S·me Wave
RECEiVED
DATAlOBE
DATA
TRANSMln[D
. Transmit Carner
Figure 3. ly plcal
. Frequency Spectrum
1-95
XR·14412
PRINCIPLES OF OPERATION
Receive Carrier (RX CAR, Pin 1): The FSK-encoded receive
carrier is fed into this input. The input signal must have
either TTL or CMOS logic levels with a duty cycle of
50% ± 4%.
Figure 1 shows the typical connection for the XR-14412
as a modem system. The system has four main component blocks. They are FSK modulator and demodulator,
which are contained in the XR-14412, the bandpass filter, and the line hybrid. The function of each block is as
follows:
Receive Data Rate (RX RATE, Pin 6): This input is used to
adjust the demodulator for the incoming data rate.
Self-Test (Pin 2): This input can be used for self-testing
the demodulator section. A square wave applied to this
pin will internally apply an FSK signal to the demodulator input, thus causing the RX data output, Pin 7, to follow Pin 2.
Line Hybrid: This block acts to direct received FSK information to the bandpass filter and demodulator, while
the FSK modulated carrier is directed to the telephone
network.
Reset (RS, Pin 5): This input can be used to disable the
demodulator. With reset at logic "1", the demodulator
output is forced high, logic "1". For normal operation,
reset is tied low, logic "0".
Bandpass Filter and Limiter: Received FSK information is
filtered by this block to remove extraneous signals received from the telephone network. The local transmitter carrier is also filtered out. The limiter stage is used
to provide the XR-14412 with a TTL- or CMOScompatible signal.
Crystal (OSCIN, OSCOUT, Pin 4, Pin 3, respectively): A
1.0 MHz crystal is connected between these two pins
for utilizing the on-chip oscillator. An external oscillator
can also be used by feeding it into the OSCIN, Pin 4, input. In the crystal mode, external parasitic capacitance, including crystal shunt capacitance, must be
less than 9 picofarads at Pin 4.
Modulator: This block, contained in the XR-14412, converts serial binary data into an FSK-encoded carrier signal. The carrier frequency is controlled by the mode
and type inputs. Input data must be TTL- or CMOScompatible. The output of the modulator is a digitally
synthesized sine wave (see Fig. 2), with its harmonic
content shown in Fig. 3.
TTL Pull-Up Disable (TTLD, Pin 15): All of the inputs to the
XR-14412 have on-chip pull-up resistors. These pull-up
resistors may be disabled when interfacing to CMOS
logic by taking the TTLD input to a logic "1". For TTL
logic interfacing, TTLD is tied to a logic "0".
Demodulator: This is used to convert an FSK-encoded
carrier signal into serial data. The rate at which data
can be received and decoded is controlled by the RX
rate and type control inputs.
Description of Control Inputs-Refer to Figure 1 and Table 1.
APPLICATIONS
Type (Pin 14): This input is used to select either U.S. or
CCITT operating frequencies.
Figure 4 shows the XR-14412 connected as a 300-baud
FSK modem. Amplifiers A1 - A3 are connected as
bandpass filters to remove extraneous signals picked
up from the phone line as well as local oscillator isolation. A4 is connected as a comparator to provide limiting to the received carrier and provide the necessary
square wave for Pin 1, RX CAR. input. A5 acts as a line
hybrid. It provides amplification to the received carrier
while attenuating the local oscillator, trying to go toward
the bandpass filter. A6 is simply used to buffer the TX
CAR. Pin 9, output of the XR-14412.
Transmit Data (TX DATA, Pin 11): This is the input for binary
serial data.
Transmit Carrier (TX CAR, Pin 9): This output provides a
digitally synthesized sine wave derived from a 1 MHz
crystal oscillator. The carrier frequency is controlled by
the type and mode inputs.
Transmit Enable (TX ENABLE, Pin 12): This pin is used to
enable and disable the modulator, or TX CAR, output.
The configuration as shown is for answer mode, as the
mode pin is at a logic "0". This circuit will work over a
received carrier range of -10 dBm to -40 dBm.
Mode (Pin 10): In conjunction with the type input, the
carrier frequencies are selected with this input.
Echo (Pin 13): This input is used to program the modulator to produce a 2100-Hz tone for disabling line echo
suppressors.
Figure 5 shows a connection using the two spare amplifiers from the XR-346 to provide a carrier detect output.
Here A7 acts to amplify and peak detect the received
carrier from the output of the bandpass filter. This voltage is then fed to AS, connected as a comparator, to
provide a logic output for carrier detect indication.
Receive Data (RX DATA, Pin 7): This is the binary data output resulting from demodulating the FSK-encoded receive carrier.
1-96
XR·14412
Table 1. Input/Output Controls
INPUTS
OUTPUTS
TX ENABLE
(12)
RX RATE
(6)
MODE
(10)
TYPE
(14)
ECHO
(13)
STANDARD
MODE
1
1
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
0
0
US
US
US
US
ORIGINATE
ORIGINATE
ANSWER
ANSWER
MARK
SPACE
MARK
SPACE
1
0
1
0
1270
1070
2225
2025
Hz
Hz
Hz
Hz
600
600
600
600
bps
bps
bps
bps
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
US
US
US
US
ORIGINATE
ORIGINATE
ANSWER
ANSWER
MARK
SPACE
MARK
SPACE
1
0
1
0
1270
1070
2225
2025
Hz
Hz
Hz
Hz
300
300
300
300
bps
bps
bps
bps
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
CCID
CCID
CCID
CCID
CHANNEL 1
CHANNELl
CHANNEL 2
CHANNEL 2
MARK
SPACE
MARK
SPACE
1
0
1
0
980
1180
1650
1850
Hz
Hz
Hz
Hz
300
300
300
300
bps
bps
bps
bps
CCID
CHANNEL 2
1-
oX-
1
X
0
0
1
0
x
x
x
x
,
-
,
,
TX DATA
-
BAUD RATE
TX CARRIER
1
-
2100 Hz
-
NO OUTPUT
-
,
Input or output IS at a digital high, refer to Electrical Characteristics for exact value,
Input or output is at a digital low, refer to Electrical Characteristics for exact value,
Can be either a 1 or a 0,
O.OII'F
Q.DI,.F
DAT"YO
BE SENT
-------==t=============!=tOAYA
A,-A4::: . XR·346
AS-A6 = 'Iz XR·346
L
• CRYSTAL MODE - PARALLEL
FREQUENCY _ IMHz ~ 0.1 %
RS = 540 11 TYP, Co = 7 pF TYP
SUGGESTEO SUPPLIERS
TYCO, eTS KNIGHT, MOTOROLA CRYSTAL PRODUCTS
. . FOR DIRECT CONNECT TO PHONE LINE, SYSTEM MUST BE APPROVED BY FCC
T, = MICROTRAN 11104 OR EaUIVALENT
P, = . ADJUSTED FOR 50% saUARE WAVE AT AX CAR INPUT AT MINIMUM RECEIVED CARRIER
RECEIVED
Figure 4. Complete 300 Baud, Answer Mode, FSK Modem
.5V
2.2M
10K
82011
22K
TO (+) INPUT A4 --""'''r-~--l
TO (+)INPUT A3
-------1
A7-A8 '" 'h XR·346
0, '" . L.E.D.
.
".F I
>---4----0:
20K
Figure 5. Carrier Detect Circuit
1-97
XR·14412
GRND.
PHONE LINE
PHONE LINE
'5V
DATA TO X MH
DATA AEelEVED
GRND.
COMPONENT
SIDE
SHOWN
(SCALE 32:1)
Figure 6. Complete FSK Modem Printed Circuit Board Layout
(Circuit Shown in Figure 4)
Table 2. Parts List for 300 Baud MODEM.
"1% tolerance; all other resistors are 1/4W, 10%; all capacitors are 10%.
Resistors are in ohms and capacitors are in /LF.
"R1
"R2
"R3
"R4
"R5
"R6
"R7
"R8
"R9
R10-R11
R12
R13
R14
R15
R16
R17-R18
"R19
R20
R21
R22
R23
R24
R25
ANSWER
ORIGINATE
40.2K
499
270K
383K
680
60AK
160K
24.9K
1.21K
1K
500K
500K Pot
10K
220K
15M
10K
600
220K
22K
2.2M
3.0K
20K
30K
47.5K
191
357K
270K
160
39AK
160K
20K
360
1K
500K
SOOK Pot
10K
220K
15M
10K
600
220K
22K
2.2M
3.0K
20K
30K
ANSWER
ORIGINATE
R24
R26
"R27
20K
500
600
20K
500
600
C1-C6
C7
C8
C9
C10
C11
.01
.1
22
.01
4.7
3.3
.01
.1
22
.01
4.7
3.3
D1
D2
IN914
LED
IN914
LED
T1
Microtran
T1104
Microtran
T1104
CRYSTAL
1 MHz ± .1%
1 MHz ± .1%
A1-A8
XR·346
XR·346
MODEM IC1
XR·14412VP
XR·14412VP
1·98
ADVANCE
INFORMATION
XR·2121/2122
Bell 212A Modulator/Demodulator
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAMS
The XR-2121 and XR-2122 are designed to provide the
complete modulator and demodulator functions for the
Bell Standard 212A PSK Modem. These devices, when
used with the XR-2120 PSK Filter, offer a three-chip solution for realizing this 1200/300 bps Modem System.
The XR-2121 Modulator Provides either a 1200 bps PSK
or 0 to 300 bps FSK output. Crystal controlled operation
offers extremely accurate and stable 1200/2400 Hz carriers for the PSK and 1170/2125 Hz carriers for the
FSK. An enable/disable pin is provided for blanking the
modulator output. A transmit clock output, 1200 Hz, is
also provided for synchronization of the terminal and
other facilities. An internal scrambler and an asynchronous to synchronous converter are also provided.
The XR-2122 Demodulator provides the complete demodulation function for either 1200 bps PSK or 0 to 300
bps FSK incoming carriers. Auto speed selection is provided for the answer mode. An internal descrambler
and an synchronous to asynchronous converter are also provided.
Both XR-2121 and XR-2122 utilize CMOS technology for
low power operation. They are designed to operate
from dual 6-volt power supplies, and provide CMOS or
r2L compatible inputs and outputs.
FEATURES
Bell Standard 212A Compatible
XR-2121-Modulator
6-Bit Synthesized Sine Wave Output
Enable/Disable Input
1200 Hz Transmit Clock Output
Internal Scrambler
Asynchronous to Synchronous Converter
Crystal Controlled with Buffered Clock Output
External Clock Input
CMOSITTL Compatible Inputs
XR-2122-Demodulator
Automatic Speed Selection in Answer Mode
36 dB (- 9 to - 45 dBm) Dynamic Input Range
On-Board Descrambler
Synchronous to Asynchronous Converter
Carrier Detect Output
ORDERING INFORMATION
APPLICATIONS
Stand-Alone Modems
Remote Terminals
Built-In Modems
1-99
Part Numbar
Packaga
Oparatlng Tamparatura
XR-2121122CN
XR-2121122CP
Ceramic
Plastic
O°C to +70°C
O°C to +70°C
XR·2121/2122
ELECTRICAL CHARACTERISTICS
Test Conditions: VDD
SYMBOL
DIGITAL SECTION
VOH
VOL
VIH
VIO
liN
IOH
IOl
Cl
= 6V, VSS = - 6V,
XIN
PARAMETERS
=
1.8432 MHz, TJ
MIN
Output High Voltage
Output low Voltage
Input High Voltage
Input low Voltage
Input Current
Output Drive Current
Output Drive Current
ClK OUT Drive Capability
= 25°C
TYP
MAX
3.5
0.5
3.5
1.5
10
-0.5
2.0
-1.5
4.0
50
UNIT
V
V
V
V
pA
mA
mA
pF
CONDITIONS
10
10
= 1 mA
= 1.5 mA
VOH
VOL
= 3.5V
= 0.5V
ANALOG SECTION
ZIN
VOCAR
V2H
ViCAR
IDD
VSUP
Terminal:
or
CPU
Input Impedance RX CAR
Output level - TX CAR
2nd Harmonic Content TXCAR
Dynamic Range - RX CAR
Power Supply Current
Supply Voltage Range
K!)
50
0.3
V rms
0.4
-40
-9
-45
100
±6
150
dB
dBM
mA
V
XR·2122
XR-2121, Rl "" 600!)
Referenced to Vo CAR
XR-2122
MODEM
UART
SIGNAL
PROCESSOR
Telephone
or Leased
Line
RS.:.... 232
HANDSHAKING CONTRO
~~ACU-~
Figure 1. Modem Block Diagram
1·100
XR·2121/2122
PRINCIPLES OF OPERATION
SPEED SEl: 1200 bps PSK or 0 to 300 bps operation is
selected by this input.
Figure 1 illustrates a general block diagram of a com·
plete modem system. These blocks are necessary for
the modem to be able to: (1) Interface to the telephone
network; (2) accept control signals and supply timing,
(3) process data, and (4) modulate and demodulate
data.
ENABLE CoNV/CoNV lENGTH: These pins select the bit
length of input characters, and if the internal asyn·
chronous to synchronous converter is used or not. In·
put character length is either 9 or 10 bits.
The XR·2121 and XR·2122 provide the modulation and
demodulation function, and when used with the
XR·2120 filter, perform the complete modem signal
processor function.
TX DATA: This is the input for data to be transmitted.
XR-2122
Description of Control Inputs and Outputs
ClK IN: A 1.8432 MHz clock is fed into this pin from the
XR·2121 or other source.
XR-2121
RC ClK: A 1200 Hz signal is available at this output for
XIN, XoUT: These are the crystal input pins.
synchronization of other circuits.
ClK OUT: This provides a buffered crystal output for the
XR·2122 or other circuits.
CD, RCo, CCo: CD provides a carrier detect output indio
cating a valid carrier is present at the RX CAR input.
The RCD and CCD input provide the carrier ON and car·
rier OFF times.
TRANS ClK: A 1200 Hz square wave is available at this
output for a terminal or other circuits.
MODE SEl: Answer or originate mode is selected by this
TRANS ClK IN/EXT: This selects whether an external
pin.
trans clock at the EXT TRANS ClK input is used for car·
rier timing or an internal clock is used.
RX DATA: Demodulated Data is present at this output.
EXT TRANS ClK: Provides an input for an external trans·
RX CAR: Received modulated carriers are input to this
mit clock input.
pin.
TX CAR: This output provides a digitally synthesized
ATTACK TIME: These pins are used to set attack and de·
cay times of the input AGC circuit.
sine wave output. The modulation on this carrier, either
FSK or PSK, is determined by the speed input.
APPLICATIONS INFORMATION
TX ENABLE: This input can be used to enable or disable
the TX CAR output.
Figure 2 shows the interconnections between the
XR·2121 and XR·2122 Modulator/Demodulator, and the
XR·2120 Filter. Here the XR·2121 supplies the XR·2122
with its clock input. The auto speed function of the
XR·2122 sets the speed of the XR·2121 automatically
through the speed indicator output of the XR·2122.
CTS: The clear·to·send signal is supplied by this pin.
MODE: Answer or originate mode of operation is select·
ed by this pin.
1.8432 MHZ
~--",XR,-,-::..:2",'2,,-'_~
CAR
ADJ
COMP
XR -2120A
XR - 2125
TxD
soon
TxCAR
TxD
SYNC
TxC
TxC
TxCAR
eL.K OUT
MODULATOR
~~K ~-----+-----li ~~K
ASYNC
DEMODUl.ATOR
XR - 2122
TELEPHONE
CLK
IN
RxD
NETWORK
RxD
RxCAR
1---___<
600n
FILTER
DATA
BUFFER
-
Figure 2. Complete 1200/300 BPS Modem Signal Processor
1·101
><
.....
.....
........
.....
XA·212AS
BELL 212A TYPE MODEM
:D
•
I\)
XR·212t
MODULATOR
I\)
R"
I\)
Voo
XR·212(JA
FILTER
I\)
I\)
Voo
T,
I
EXT Txc
I
I
TXDIN
0
I\)
~
TELEPHONE
C NETWORK
L _____ _
RXDOUT
-'
-'
III
R,
RxCLKOUT
MANUAL
'200I300
SELECT
CD
A.~
~
~
V
ANALOGGND
DIGITAL GND
VDD
Yss
+5V" O.2Sv
-SV ~ O.25v
DAA
FCC REGISTERED CIRCUIT
FOR DIRECT CONNECT
XR·212AS 8ell 212A Type Modem
XR·2123
PSK Modulator/Demodulator
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-2123 provides the phase-shift keying (PSK)
Modulator and Demodulator Functions for implementing a full-duplex 1200 bps or 2400 half-duplex Modem
System. Using fully digital circuit techniques allows the
XR-2123 to be externally programmed for operation for
Bell Standards 201 Band C or 212A (1200 bps only),
and CCID V22 or V26. Internal logic and timing functions minimized external parts, while crystal controlled
operation provides stable and accurate operation.
VDD
LSD
C22
NIY
RXS
The XR-2123 utilizes CMOS technology for low power
operation while providing single + 5 volt operation,
packaged in a standard 28 pin DIL plastic or ceramic
package. The XR-2123 operates from O°C to 70°C.
PSK
MODULATOR
SYN
RBA
BAC
RXD
iiXC
QUA
RBY
FEATURES
Single + 5 Volt Operation
Low Power Consumption (Typ 10mw)
1200 bps Full-Duplex
2400 bps Half-Duplex
Programmable for US or European Standards
(CCID)
Dibit PSK (DPSK) Operation
Crystal Controlled
Synthesized Sine Wave Modulator Output
Adjustable Modulator Output Amplitude
Input Protection
22 TTG
MOC
CONTROL
lOGIC
CCl
21 TXC
TRM
V..22
TXS
COD
APPLICATIONS
TlV
RTE
Bell Standard 201 or 212A Modems
CCID Standard V22 or V26 Modems
RlD
ABSOLUTE MAXIMUM RATINGS
4CR
ANI
VSS
RTS
Power Supply
Power Dissipation
Derate Above 25°C
Operating Temperature
Storage Temperature
All Input Voltage
DC Current Into Any Input
5.5V
1.0W
5 mW/oC
O°C to 70°C
- 65°C to 150°C
- 0.5V to (VDD to 0.5V)
±1 mA
Package
Operating Temperature
XR-2123CN
XR-2123CP
Ceramic
Plastic
ooe to + 70°C
ooe to + 70°C
TDA
SYSTEM DESCRIPTION
The XR-2123 provides the complete demodulation,
modulation, and control functions for DPSK Modem
Systems. The Demodulation is a digital type using
Phase-Locked Loops (PLL). The Modulator provides a
synthesized sine wave output in a dibit Phase-Shift Keying (DSPK) Format. The Phase Shifts and carrier frequencies are programmable with logic inputs.
ORDERING INFORMATION
Part Number
PSK
DEMODULATOR
1-103
XR·2123
ELECTRICAL CHARACTERISTICS
Test Conditions: VDD =
Digital Inputs:
+ 5V,
VSS = OV, Tj = O°C to 70°C
RXS, MOC, CCL, RTS, ANS, TDA, RTE, COD, V22, TXC, BAC, SYN, NSY, LSD
Digital Outputs: C22, RBA, RXD, QUA, TBA, 4CR, TTG, RBY, RXC
MIN
SYMBOL
PARAMETERS
VOL
VOH
VIL
VIH
IlL
IDD
CI
tR
tF
VTXS
Output Low Voltage
Output High Voltage
Input Low Voltage
Input High Voltage
Input Leakage Current
Power Supply Current
Input Capacitance
Low to High Logic Transition Time
High to Low Logic Transition Time
Transmitted Carrier Signal Level
TYP
4.6
0.5
3.5
MAX
UNIT
CONDITIONS
0.4
V
V
V
V
pA
MA
pF
nS
nS
dBm
IOL = 1.6 MA
IOH = 1.0 MA
11
5
100
2.5
5
20
20
-9
4
CL = 10 pF
CL = 10 pF
VplN 11 = O.BV
EQUIVALENT SCHEMATIC DIAGRAM
TLV ~.
10
17
13
TDA
TXC
RTS
RTE
MODULATOR
21
~. TRM
18
20
COD
19
ANS
16
...
GATING
14.608 MHz)
,
ri';'10or
~
BAC
~
SYN
26
LSD
28
NSY
27
~
20~ -
+32
..r-
CCL
~
4~
,
H
~~
r-
H
VDD
VSS
,
~..;. 2/15 or 4/5:
RXS
4CR
1~. RLD
15
V.22
MOC
TXS
r="~
2
~
~';-6orI6r
+- 32
+-8
';'2
22
~
C22
TIG
24
~YN
-'!.. RBA
+1
23
RBY
f-~.
OUA
~~
RXD
•
'---
DEMODULATOR
1-104
XR·2123
·Coding
00
01
10
11
European/US SId.
+90°
0°
180°
-90°
ALTA
chronized digital phase-locked loop which maintains
the basic timing and initiates all phase shift detection
operations.
ANSI SId.
+45°
135°
315°
225°
ALTB
This filtered signal is then applied to Pin 3 (RXS). The
phase-locked loop is synchronized by the signal available from Pin 13 (4CR). Synchronization is maintained
by generating a sync pulse from the phase-locked loop
and applying it to Pin 26 (SYN). RBA, Pin 4, provides the
output from the receiver'S synchronizer. This output
command the phase shift detector to start a single
measuring cycle.
RTE (Pin 18) controls the baud rate of the modem.
When RTE is LO the transmission rate is 1200 b/s, and
when RTE is HI, the transmission rate is 2400 b/s. ANS
(Pin 16) controls the answering tone (2100 Hz) to the
transmission line. When ANS is LO and V22 is HI, the
answering tone (2100 Hz) is connected to the transmis·
sion line.
Coherent demodulation techniques are used in the receiver section. The reference frequency used to detect
phase shifts in the carrier from the transmission line is
generated in an internal phase locked loop. In the case
of a 1200 bit/sec application, the reference frequency
is synchronized to the line carrier.
BAC (Pin 25) is the time base input which is 512 times
the normal receiver baud timing. In the case of a 1200
b/s, full duplex modem, BAC = 307.2 kHz or MOC/15
TXC (Pin 21) is the transmitter bit timing input. It may be
tied directly to TIG (Pin 22) which is the transmitter timming set by RTE.
In applications requiring 2400 bits/sec and upwards,
the reference frequency is five (5) times the carrier.
This permits phase detection at much higher rates.
RTE HI TIG = BAC/256
RTE LO TIG = BAC/512
This phase shift detector subtracts the carrier from the
reference. The difference sets a "window" in which
standard pulses are counted. The following table shows
the correlation between angles and counts:
Of course external timing signals may be applied for
nonstandard uses.
TLV (Pin 11) sets the transmitter amplitude by using a
resistive divider between + 5V and ground. This signal
may be set between 1.0V and 5V. TRM (Pin 9) Signals
that the modem is in the transmit mode. When TRM is
HI, the unit is transmitting, When TRM is LO, the unit is
not transmitting. The relationship between the voltage
at TLV and the amplitude of TXS is shown in the Electrical Characteristics.
Phase Angles (0)
A
B
90
180
270
45
135
225
315
o
Pulse Counts
Reg. 1 Reg. 2
64
64
64
192
192
192
64
192
MSB (bit 8)
Reg. 1 Reg. 2
o
0
1
1
0
1
o
1
The counting results should be identical to the table. If
not, the reference is either ahead or behind the ideal
phase. This information is decoded and the phase
locked loop is either accelerated or decelerated.
The data to be modulated and transmitted is applied at
TDA (Pin 17). The modulated signal is output at TXS (Pin
10).
DEMODU LATION
Once demodulation has been accomplished, the data is
available at Pin 5 (RXD). The data at RXD is changed to
"1" when Pin 28 (LSD) is "0" or Pin 27 (NSY) is "1".
LSD is a line signal detector which tells the system that
there is a signal present. The 1.8 kHz filter is applied to
a level detection circuit, which consists of a comparator. NSY is a "new synchronizer" input. When it is "1 ",
data is disabled; when "0", date is enabled. However,
on the transition from "1" to "0", the receiver clock,
Pin 24 (RXe) , immediately synchronizes with the SYN
signal during the next symbol interval. RXC provides the
user with bit rate timing (baud timing) for synchronized
transmission to the receiving terminal. The following table represents the above discussion.
There are two types of incoming signal processing
which will be discussed. The first concerns full duplex
reception. In this case, using the Bell 212A as our example, the received signal will be centered on 1200 Hz.
The signal is passed through a 1200 Hz filter and applied to a peak detection circuit. This signal is then
passed through an amplification stage and applied to
Pin 3 (RXS). After the amplifier stage, the signal is simultaneously applied to a sync-generating circuit and
passed to Pin 26 (SYN). The output of the peak detector
is also applied to a level detector and provides the input
for Pin 28 (LSD) and Pin 27 (NSY).
LSD
0
0
1
1
1
The second type of modem to discuss is a half-duplex
system. Speeds of up to 3200 b/s are available for use
on leased lines. The received signal is coupled through
the line interface to a 1.8 kHz filter. The signal is then
sent to a peak-detector circuit and is then applied to a
narrow band filter. The signal is then applied to a syn-
1-105
NXY
0
1
0
RXD
1
1
Data
Data
RXC
free running
free running
Synchronized
Synchronized
Fast Synchronization
XR·2123
Pin 2 (C22/TBY) provides the carrier clock signal for
both reception and transmission. When V22 is "0", C22
is defined as in the following table:
V22
o
ANS
o
o
o
o
1
1
o
nce
.,. -,L_______
ATS
COD C22
o 1228.8 kHz (512 x 2400 Hz)
1
614.4 kHz (512 x 1200 Hz)
o 614.4 kHz
1
1228.8 kHz
............
TXS
,e===:..,J.e:==:>
C::::::;>----,
IZZZ====2r---:-~
12
~
,.....==::..L"...........
P
::!.-
34
............:;;'-I~
raM .J
R"
:: 1,
I ....."h ' ~'
C22 may be tied directly to Pin 8 (CCl). With V22
"1", TBY provides transmitter byte timing which is 16
times the transmitter baud timing.
V~
TBM
4
J
C7
D
V
'4V
c..\?~
-.J
I
Figure 1. Timing Diagram of the Transmmer
10
I;
10
I
~
".
V
ioI'
·'0
z
>
R,o _ _ _ _ _ _ _ _..JIIIl::O::ODJ==r
/
Ii:
30
·40
/
ATe 1
Figure 2. Timing Diagram of the Receiver
"
V221
·50
0.01
0.1
10
TBY
'11~Lf1.11.I'"lJ"Lf
TTO
-,
I
10
Figure 5. TXS vs VTLV
Pin 12 (RlD) provides a signal which indicates to the receiving terminal that a signal has been detected. RlD
= "1" when a received signal is detected, and RlD =
"0" when a received signal is not present.
Figure 3. Timing Circuit
RBY, Pin 23, provides a timing signal for 3000 bls, halfduplex modem usage. It is similar in use to RXC.
QUA, Pin 6, provides an indication of the quality of the
demodulated signal. It is "0" when errors are greater
than 22.5° during one symbol interval. This phase error
is measured with respect to RBA.
Figure 4. Quality
1-106
,
I
L-.
XR·2123
·SV
rfot-c:::>
Q:;AN~S~_ _ _ _ ~_
COO
r-
I
I
I
~
i
XR.!!!!..J~_
TLV
17
AFiS
16
I
10
-------------.-@~2 19
• .......t.~ 20
...Ef 18
RTE
_ _. _ _
TX'
______
13
T~~]I
T " - - -_ _ _ _ _ _ _ _ _ _
r~I7
RT2-
irfS
reA
._
[®}
4608kHzG
__ tj~~
15
I.'
Moe
I
25
-.!.l.";:
27
__ l!~ 23
28~;;::--+--+
L. T!'L...--_ _ _ _ _ _ _ _...!..7lJ3 ]2
,RXC
_ _ _ _ _ _ _ _ _ _ J!.~c 21.
WQ~---------=-~~
~-.---------._---UL!..':<
I.se
,
L---~IT'~VS~S~-~
.;.::.CA"',Re..-<>-___________.. ____.___._________ _
---------.-.--- .._-
'lEC
HDX - - - - - - - - - - - - - - - . - - - - - - - - -.....---1
O:-[O:::"------_______________.-!-4-1
------------CAR
Carrier detector
REC
HDJ(
LOP
Rec"elv' mode
Half duplex
"0" Connects Locol Lcop
V.26/201 Modem 2400 bps
LOP .. I .. Conn.c Is Local Loop
ANS .. , .. Cont'Iects
CHN
answering
ron.
'0 lin.
Selects Ihe chann.ls
V.221212A (PSK Only) Modem 1200 bps
1·107
XR·2123
OUTPUTS
The following is a description of the operation of each
pin of the XR-2123.
INPUTS
Pin
Number
Deslgnation
1
14
VDD
VSS
+5V ± 0.5%
ground
19
20
16
COD
V.22
ANS
code
V.22 mode
Description
answering tone
Pin
Number
Deslgnation
10
TXS
Transmitted signal
Modulated 8 level sine. wave
Transmit mode
Description
9
TRM
13
4CR
4 x Carrier frequency in square wave
2
C22
m=o
Carrier clock for V.22 modem
C22 can be connected directly to
{ Mode
selection
~8~l)
V22 ANs COD
11
TlV
0
0
0
0
0
1
0
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
V
0
0
0
0
V.22/212A modem; Tx high ch;
Rx high ch. (local loop)
V.22/212A modem; Tx low ch;
Rx low ch. (local loop)
V.22/212A modem; Tx high ch;
Rx low ch. (answer mode)
V.22/212A modem; Tx low ch;
Rx high ch. (call mode)
Answering tone (2100 Hz)
Answering tone (2225 Hz)
V.26 modem code A (n x 90')
V.26 modem code B (n x 45')
Transmitter level.
The sending level is directly dependent
on the voltage of TlV signal 1 ... 5.5V
(Soo aoctrlcal Charactorlstlcs)
7
MOC
Modulator clock
4.608 MHz SQuare wave
17
TDA
Transmitted data
21
TXC
Transmitter bit timing
18
RTE
Rate
low bit rate
1 high bit rate
15
RTS
Request·to·send
1 transmitter clamped
transmitter sending
BAC
26
SYN
28
LSD
SCOD C22
1228.8 kHz (5 t 2 x 2400 Hz)
0
1
6144 kHz (512 x 1200 Hz)
0
6144 kHz
t
1228.8 kHz
TBY
V22 = t
Transmitter byte timing
Square wave 16 x transmitter baud timing
22
TTG
Timing for transmitter
RTE = 0 TTG = BAC/512
RTE = 1 TTG = BAC/256
23
RBY
Receiver byte timing
Square wave 16 x received baud timing
24
RxC
Received bit timing
4
RBA
Received baud timing
6
QUA
Quality of demodulated signal.
"0" when error Is demodulated signal
is more than 22.5°
5
RXD
Received data
12
RlD
Received data. Ready signal to terminal.
o
V.221212A APPLICATION
o
25
0
0
1
1
Baud clock
512 x nominal receiver baud timing
Synchronizaton
The receiver baud timing will synchronize
to this square wave signal
INPUT
STATE
V22
COD
COD
La
La
HI
Line signal detector
1 Receive
27
NSY
New synchronizing
I-state forces the received data to "1" state.
New synchronizing is made when the 'Fm'7
goes from 1 to 0
3
RXS
Received signal
Received signal in square wave form
8
CCl
Carrier clock
512 x Received carrier signal
(Max. 4.608 MHz)
fc
fc
0
00
01
11
10
1200 BPS
EURO/US
= 2400 Hz'
= 1200 Hz'
European/US Std.
·Coding
oThe receiver Is clamped
DESCRIPTION
90
0
270 (-90)
180
600 BPS
EURO
modes i, ii, iii, iv
V.261201 APPLICATION
INPUT
STATE
DESCRIPTION
V22
HI
La
fc = 1800Hz
European/U.S. Std. Coding"
ANSI Coding·'
COD
COD
TRANSMISSION
The transmission sequence is initiated by the external
signal at RTS (Pin 15) changing from a H I state to a La
state. The transmission mode may be selected from
several possibilities by the concurrent manipulation of
the external signals at RTE (Pin 18), V22 (Pin 20), COD
(Pin 19), ANS (Pin 16). With the input frequency at MaC
(Pin 7) at 4.608 MHz, the following table applies:
··Coding
00
01
11
10
1-108
European/US Std.
o
ANSI Std.
90
180
270
45
135
225
315
all. A
all. B
XR·2125
ADVANCE INFORMATION
Data Buffer
GENERAL DESCRIPTIDN
FUNCTIONAL BLOCK DIAGRAM
The XR-2125 is a logic circuit designed to perform the
data buffer function for Bell 212A Type Modem Systems. Both asynchronous to synchronous and synchronous to asynchronous conversion are performed at
nominal data rates of 1200 bits per second. The XR2125 is selectable for character lengths of 9 or 10 bits.
Separate enable/disable inputs are supplied for async
to sync and sync to async converter sections. These inputs allow the same data lines to be used for asynchronous or synchronous operation.
VDD
TXD OUT
TXC IN
elK IN
RXD IN
The receive data buffer section (sync to async) accepts
input sync data (typically from the modem demodulator) at 1200 BPS and converts it to a 1219 BPS async
data format. The transmit data buffer (async to sync)
accepts input async format data with a data rate of
1200 BPS ± 1 %, - 2.5 % and it is synchronized to
1200 BPS, which is typically sent to the modem modulator. This section also provides break signal automatic
extension.
Rxe IN
10/9
ORDERING INFORMATION
The XR-2125 is constructed using silicon gate CMOS
technology for low power operation. Operation is designed for an input clock frequency of 1.8432 MHz. The
XR-2125, available in a 14 Pin package, is designed for
single 5 volt operation.
Part Number
Package
Operating Temperature
XR-2125CN
XR-2125CP
Ceramic
Plastic
O°C to 70°C
O°C to 70°C
SYSTEM DESCRIPTION
FEATURES
The XR-2125 provides the complete interface between
synchronous and character - asynchronous data systems. The synchronous side consists of two data lines
TXD and RXD, each with their respective clocks, TXC
and RCX. The synchronous portion is designed for data
rates of 1200 ± .01 % BPS. The asynchronous side
handles data oriented in characters where the actual
data bits are bracketed by a start and stop bit. Character lengths are 9 or 10 bit (7 or 8 data bits), pin selectable.
Bell 212A Compatible
Asynchronous to Synchronous Conversion
Synchronous to Asynchronous Conversion
Independent Disable Input for
Receiver and Transmitter Sections
1.8432 MHz Clock
Break Signal Automatic Extension for Transmitter
1200 BPS + 1 %, - 2.5 % Operation
Single 5 Volt Operation
To perform this interface, the XR-2125 consists of two
main sections: synchronous to asynchronous (receive
section) converter to reinsert stop bits deleted by the
sending modem. The other section is asynchronous to
synchronous converter (transmit section) to add or delete stop bits to correct the transmit data rate to 1200
BPS. This section also extends the break signal to two
character lengths plus three bits when it comes in at a
shorter period.
APPLICATIONS
Bell 212A Data Buffer
ABSOLUTE MAXIMUM RATINGS
Power Supply
Input Voltage
DC Input Current (any input)
Power Dissipation
Storage Temperature Range
-0.3 to +5.5V
-0.3 to VDD +0.3
±10 mA
250 mW
- 65°C to + 125°C
A standby mode is included to put the XR-2125 in a low
supply current, non-operative, mode on command.
1-109
XR·2125
ELECTRICAL CHARACTERISTICS
Test Conditions: VDD
=
SYMBOL
= 25°C, ClK IN = 1.8432 MHz, unless otherwise specified.
±5V ±5%, TJ
PARAMETERS
MIN
TYP
MAX
UNIT
0.4
V
V
V
V
rnA
CONDITIONS
DC CHARACTERISTICS
VOL
VOH
Vil
VIH
IOl
IOH
liN
IDD
Output low Voltage
Output High Voltage
Input low Voltage
Input High Voltage
Output low Current
Output High Current
Input Cu rrent
Supply Current Quiesent
2.4
2
0.8
4
400
±10
80
600
Supply Current Standby
IDD
AC CHARACTERISTICS
ftxd
f scx
tdtxd
th
f rxco
tWrxco
TXD In Baud Rate
Internal Sampling
Clock Frequency
TXD Out Delay Time
10
1170
RXD Out Delay Time
RXC Out Frequency
RXCO Out Pulse Width
1200
1212
IOl = 1.6 rnA
IOH = 400 p.A
p.A
p.A
p.A
p.A
p.A
TA
= 70°C
BPS
1200
10.5
Hz
Bits
See Note 1
Cl = pF; 10/9= Hi
8
1219
410
Bits
Hz
p's
10/9= Hi
Note 1: f sxc = f clk/1536. When the character start bit comes, internal sampling clock is synchronized with
this bit.
10/9
19.2 KHZ
ClKIN
+96 COUNTER
lOAD PULSE GENERATOR
RS
PRESETTABlE +16 COUNTER
TX EN
RX EN
RXDIN
RXCIN
RXD OUT
5 I-------+-----f
RXCOUT 6 1 - - - - - - - - i
EQUIVALENT SCHEMATIC DIAGRAM
1·110
Interface Circuits
XR·1488/1489A
Quad Line Driver/Receiver
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAMS
The XR-1488 is a monolithic quad line driver designed
to interface data terminal equipment with data communications equipment in conformance with the specifications of EIA Standard No. RS232C. This extremely versatile integrated circuit can be used to perform a wide
range of applications. Features such as output current
limiting, independent positive and negative power supply driving elements, and compatibility with all DTL and
TIL logic families greatly enhance the versatility of the
circuit.
The XR-1489A is a monolithic quad line receiver designed to interface data terminal equipment with data
communications equipment. the XR-1489A quad receiver along with its companion circuit, the XR-1488
quad driver, provide a complete interface system between DTL or TIL logic levels and the RS232C defined
voltage and impedance levels.
ABSOLUTE MAXIMUM RATINGS
Power Supply
XR-1488
XR-1489A
Power Dissipation
Ceramic Package
Derate above +25°C
Plastic Package
Derate above + 25°C
± 15 Vdc
+10 Vdc
1000 mW
6.7 mW/oC
650 mW/oC
5 mW/oC
SYSTEM DESCRIPTION
The XR-1488 and XR-1489A are a matched set of quad
line drivers and line receivers designed for interfacing
between TIUDTL and RS232C data communication
lines.
The XR-1488 contains four independent split supply line
drivers, each with a ± 10 mA current limited output. For
RS232C applications, the slew rate can be reduced to
the 30 V/p.S limit by shunting the output to ground with a
410 pF capacitor. The XR-1489A contains four independent line receivers, designed for interfacing RS232C to
TIUDTL. Each receiver features independently programmable switching thresholds with hysteresis, and
input protection to ± 30 V. The output can typically
source 3 mA and sink 20 mAo
ORDERING INFORMATION
Part Number
Package
XR-1488N
XR-1488P
XR-1489AN
XR-1489AP
Ceramic
Plastic
Ceramic
Plastic
Operating Temperature
O°C
O°C
O°C
O°C
to
to
to
to
+ 70°C
+ 70°C
+ 70°C
+ 70°C
1-111
XR·1488/1489A
ELECTRICAL CHARACTERISTICS
Test Conditions: (V+
=
+9.0 ± 1 % Vdc, V- = -9.0 ± 1 % Vdc, TA == OCC to + 70 c C, unless otherwise noted)
XR-1488 LIMITS
PARAMETERS
MIN
Forward Input Current
TYP
MAX
UNITS
1.0
1.6
mA
Reverse Input Current
10
pA
Output Voltage High
V+
V+
=
=
Vdc
+9.0 Vdc, V- = -9.0 Vdc
+ 13.2 Vdc, V- = -13.2 Vdc
+7.0
+10.5
+6.0
+9.0
Output Voltage Low
V+
V+
=
=
Vdc
+9.0 Vdc, V- = -9.0 Vdc
+ 13.2 Vdc, V- = -13.2 Vdc
-6.0
-9.0
+6.0
+10
+12
mA
Negative Output Short-Circuit Current
-6.0
-10
-12
mA
= V- = 0
300
Ohms
Positive Supply Current (RI = (0)
Yin = 1.9 Vdc, V+ = +9.0 Vdc
Yin = 0.8 Vdc, V + = +9.0 Vdc
Yin = 1.9Vdc,V+ = +12 Vdc
Yin = 0.8 Vdc, V + = + 12 Vdc
Yin = 1.9 Vdc, V+ = + 15 Vdc
Yin = 0.8 Vdc, V + = +15 Vdc
+15
+4.5
+19
+5.5
+20
+6.0
+25
+7.0
+34
+12
-13
0
-18
0
-17
0
-23
0
-34
-2.5
=
±2.0V
mA
Power Dissipation
V+ = 9.0 Vdc, VV+ = 12 Vdc, V-
Switching
IVol
mA
Negative Supply Current (RL = (0)
Yin = 1.9 Vdc, V- = -9.0 Vdc
Yin = 0.8 Vdc, V- = -9.0 Vdc
Yin = 1.9 Vdc, V- = -12 Vdc
Yin = 0.8 Vdc, V- = -12 Vdc
Yin = 1.9 Vdc, V- = -15 Vdc
Yin = 0.8 Vdc, V- = -15 Vdc
= -9.0 Vdc
= 12 Vdc
Characteristics (V + = + 9.0
Yin = 1.9 Vdc,
RL = 3.0 kll
-7.0
-10.5
Positive Output Short-Circuit Current
Output Resistance V +
CONDITIONS
= 0 Vdc
Yin = + 5.0 Vdc
Yin = 0.8 Vdc,
RL = 3.0 kll
Yin
mW
333
576
± 1 % Vdc, V-
=
- 9.0 ± 1 % Vdc, TA
=
+ 25 c C)
Propagation Delay time (tpd + )
150
200
ns
ZL
Fall Time
45
75
ns
ZL
Propagation Delay Time (tpd )
65
120
ns
ZL
Rise Time
55
100
ns
ZL
1-112
= 3.0k and 15 pF
= 3.0k and 15 pF
= 3.0k and 15 pF
= 3.0k and 15 pF
XR·1488/1489A
ELECTRICAL CHARACTERISTICS
+ 5.0 Vdc ± 1 %, TA = O°C to + 75°C,
Tast Conditions: Response control pin is open. (V +
unless otherwise noted)
XR-1489 LIMITS
PARAMETERS
MIN
TYP
MAX
Positive Input Current
Vin = +25 Vdc
Vin = + 3.0 Vdc
3.6
0.43
8.3
Negative Input Current
Vin = -25 Vdc
-3.6
-
UNITS
CONDITIONS
mA
mA
8.3
Vin = - 3.0 Vdc
-0.43
Input Turn-On Threshold Voltage
TA = +25°C, VOL :s0.45 V
1.75
1.95
2.25
Input Turn-Off Threshold Voltage
TA = +25°C, VOH 2:2.5 V
0.75
0.8
1.25
Output Voltage High
Vin = 0.75 V
Input Open Circuit
2.6
2.6
4.0
4.0
5.0
5.0
Output Voltage Low
0.2
0.45
Output Short-Circuit Current
3.0
Power Supply Current
20
26
mA
Vin = +5.0 Vdc
Power Dissipation
100
130
mW
Vin = +5.0 Vdc
Vdc
Vdc
IL = -0.5 mA
Vdc
IL = -0.5 mA
Vdc
Vin = 3.0 V,
IL = 10mA
mA
Switching Charactaristics (V + = 5.0 Vdc ± 1 %, TA = + 25°C)
Propagation Delay Time (tPLH)
25
85
ns
RL = 3.9 kO
Rise Time
120
175
ns
RL = 3.9 kO
Propagation Delay Time (tPHL)
25
50
ns
RL = 390 kO
Fall Time
10
20
ns
RL = 390 kO
EQUIVALENT SCHEMATIC DIAGRAMS
XR-1488
v·
XR-1489A
'4o--........---_-_-K1-_-"M"--O 6
OUTPUT
J OUTPUT
INPUT
1 o-...,.".......,-+-..,.--~
L........L_~>---_+_-_+__o 7GAOUNO
GND7~
1-113
Disk Drive Circuits
XR·2247/2247 A
Floppy Disk Write Amplifier
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-224 7/224 7A is a write amplifier designed to provide the complete interface between write data signals
and tunnel-erase magnetic heads. Although primarily
intended for floppy disk drive systems, the XR-2247/
2247A can also be used in other magnetic media systems such as tape drives. To minimize external part
count for dual head systems, complete head switching
is does internally with emitter-coupled PNP transistors
in the XR-2247 and diodes (which offer improved broadband noise characteristics) in the XR-2247A. Write and
erase currents are each externally programmable with
a single resistor. Also included is circuitry for inner
track write current compensation. To prevent false
write current outputs during power-on, an inhibit input
has been provided. Erase turn-on and turn-off times are
each externally programmable.
The XR-2247/2247A, available in a 22-Pin DIP, operates
from a single power supply and provides TTL compatible inputs.
FEATURES
ORDERING INFORMATION
Fully Programmable Write and Erase Currents
Fully Programmable Erase Turn-onlTurn-off Times
Internal Head Switching for Dual Head Drives
Single Supply Operation
Inner Track Write Current Compensation
Inhibit Input
TTL Compatible Inputs
Low External Parts Count
Part Number
Package
XR-2247CN
XR-2247CP
XR-2247ACN
XR-2247ACP
Ceramic
Plastic
Ceramic
Plastic
Operating Temperature
O°C
O°C
O°C
O°C
to
to
to
to
+ 70°C
+70°C
+70°C
+70°C
SYSTEM DESCRIPTION
The XR-2247/2247A accepts a serial binary data
stream input. With the write mode selected, negative
transitions of this input signal will alternately provide
write current to each half of the head. The XR-2247/
2247A provides two sets of current outputs for dual
head drives, with the head select (HS) control determining which is active. The write current is externally programmed with a resistor between the internal voltage
reference and the current setting input. Two highcurrent open-collector outputs provide the erase coil
drive. Turn-on and turn-off delay circuitry is provided for
these outputs, with the delay externally programmed.
APPLICATIONS
Floppy Disk Drives
Single/Dual Head Systems
Magnetic Tape Write Amplifier
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage (Pin 1)
16 V dc
Input Voltage (all digital inputs)
-0.2V to + 16 V dc
Reference Current (Pin 4)
10 mA dc
Output Current (Pins 2, 10, 12,22)
100 mA dc
Storage Temperature
- 55°C to + 150°C
Operating Junction Temperature
150°C
Power Dissipation
750 mW
6.5 mW/oC
Derate Above 25°C
An inhibit input (INH) is provided to disable the outputs
to prevent false writing during power-on. With the read
mode selected, internal head switching channels the
proper head to the read outputs.
1-114
XR·2247/2247 A
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°C, VCC = 12V, Rref = 10 kg, unless otherwise specified.
SYMBOL
ICC
VCC
PARAMETERS
Power Supply Current
Power Supply Range
MIN TYP MAX UNIT
-
CONDITIONS
=
13
12
20
16
mA
V
-
0.8
V
V
0.1
15
4.0
100
p.A
p.A
10.2
0.1
0.2
V
V
0.01
1.0
0.45 0.5
0.9
1.0
20
1.5
0.55
1.1
p.A
V
mS
mS
VCC - 16V
lout = 100 mA
R01 = 4.55 Kg, C01
R02 = 9.54 Kg, C02
8.0 8.5
9.0
7.8
8.2
8.8
0.65 0.80 0.95
0.03 15
V
V
V
p.A
Iref - 1 mA
Iref = 10 mA
Iref = 1 mA
7
-
12
V
3.7
4.1
4.5
mA
IRWS
=
Low
5.1
5.7
6.3
mA
IRWS
=
High
-
-
40
p.A
IRWS
=
Low (Note 1)
-
4
1
-
9
VCC
9V to 16V
DIGITAL INPUT VOLTAGE
VIH
VIL
High Level Voltage
Low Level Voltage
2.0
-
DIGITAL INPUT CURRENTS
IIH
IlL
High Level Current
Low Level Current
-
-
VI
=
2.4V
CTa or CT1 OUTPUTS
VCTH
VCTL
Output High Voltage
Output Low Voltage
9.5
-
lout - 100 mA
lout = 1 mA
ED or E1 OUTPUTS
IOL
VOEL
TO ON
TO OFF
Output High Leakage
Output Low Voltage
Erase Turn-on Delay
Erase Turn-off Delay
-
=
=
CURRENT SOURCE
Vref
Reference - Pin 4
Vmir
IWRL
Iref Input Voltage - Pin 13
Write Current Off Leakage Pins 15, 16, 19,20
Current Sink Compliance Pins 15, 16, 19,20
Write Current w/o IRWS Pins 15, 16, 19,20
Write Current with IRWS Pins 15, 16, 19, 20
Difference in Write Current
Vcomp
IWR
IWRS
vee1
11
Figure 5. Input Amplifier
1.
FIF
Figura 6. Digital Section
1-124
XR·3470Al3470B
R/W HEAD COUPLING
so C1 should not be made too low. C1 = 0.1 /LF is nominal for most floppy disk applications.
When switching from the write channel to the read
channel, one must be careful not to present a differential voltage to the inputs of the amplifier, for this will
result in an amplified swing at the output of the amplifier, which will cause peak shifting at the digital output. A
balanced diode network or FET switches, as shown in
Figure 4, may be used to overcome this problem.
READ-BACK
SIGNAL
II
'4
(AMPLIFIER
INPUT)
"
FILTER NETWORK
The filter network, between the XR-3470Al3470B amplifier stage and differentiator stage, is subject to several
system and circuit considerations.
The filter network, first and foremost, must be designed
to pass all frequencies up to 1/2 the maximum baud
rate, with a constant gain and phase shift. This frequency can be stated as f max , where
'0
aJ
f max = 1/2 (Baud rate}max
DIFFERENTIATED
READ·BACK
SIGNAL
In order to avoid saturation of the amplifier current
sources, the current into the filter must not exceed
2.8 mAo In order to meet this condition the impedance
of the filter must be governed by the following constraint
bJ
COMPARATOR
OUTPUT
oj
OS1 OUTPUT
dJ
z .
TIME DOMAIN
FILTER OUTPUT
> (AVO EP}max
min
oj
DIGITAL OUTPUT
(OS2)
where
Figure 7a-1. Waveforms Through the XR-347DAl347DB
The amplifier stage will typically amplify the read back
signal by a factor of 110. In order to eliminate any offset
between the amplifier stages, a capacitor, C1, should
be inserted between Pins 3 and 4. If the input signal to
the amplifier is to be above 25 mY, clamping of the amplifier may occur. To reduce the gain, a resistor Rx may
be inserted in series with C1 between Pins 3 and 4. The
graph in Figure 8 shows a plot of normalized gain vs Rx.
ACTIVE OIFFERENTIATOR
The amplified filtered read back signal is fed into the active differentiator. Here, the peaks of the read back signal are transformed into zero crossings as shown by
Figures 7a and 7b.
It should be noted that capacitor C1 with Rx and the resistance looking into Pins 3 and 4, will create a pole at
approximately
+
AVO is the gain of the amplifier
Ep is the maximum peak voltage of the
input signal
The differentiator inputs are dc biased internally. This
implies that the dc level from the amplifier stage must
be blocked in order not to disturb these levels. Therefore blocking capacitors, Cb1 and Cb2, should be
placed before the differentiator inputs. In order to keep
the transient response to a minimum it is best to place
the dc blocking capaCitors before the filter network.
AMPLIFIER STAGE
w P - (Rx
2.8 mA
In order to perform the differentiator function a capacitor Co is needed across Pins 12 and 13. The selection
of Co for accurate zero crossing is optimized by maximizing current slew rate through CO, which occurs
when
1
250) C1
NORMALIZEO
GAIN
Co =
'.00
0.80
Where
0.60
0.40
0.20
L--+--+--+--t-j--t--t--+--+-j'---100
200
300
400
500
600
700
800 900
Rxl!!)
1 mA
(AVO Epw}max AF
AVO is the gain of the amplifier
Ep is the maximum expected input voltage
w is the maximum operating frequency in
radians/sec of the system
AF is the gain of the filter network
1000
If Co is greater than the maximum value calculated
above, peak shifting will occur.
Figure B. Normalized Gain vs Rx for Amplifier Stage
1-125
XR·3470Al3470B
As can be seen from Figure 9; the capacitor Co and the
effective output resistance, RO of transistors Qt and
Q2 produce a pole given by
IcU)
1
wp = 2ROCO
Co AVOEpw
where RO is typically 400.
wVin(t)
Figure 10. Dlflerentialor Response for Co and R
~~nlt~)---------4----------+----------'
In order to reduce the noise bandwidth further a second
pole can be introduced at 10 wmax by placing an inductor in series with Co and RO, where LO is given by
LO =
1
100(wmax)2 Co
Figure 9. Simplified Active Dlilerentiator Section
The damping ratio, 0, should be between .3 and 1 where
0= .:....(R-"'O.:....+--=O.=5R~O~)~C..::.o
In order to obtain a phase shift approaching 90° for perfect differentiation wp would have to approach 00 since
NLOCO
() = tan -1 (wpfwo)
Wo = operating frequency
It must be considered, however, that making wp as high
as possible also produces a noise bandwidth as high as
possible.
In order to come to a reasonable compromise wp
should be selected to be ten times the maximum expected operating frequency.
wp = 10 wmax
where Wmax is the maximum operating frequency of
the system in radians/sec.
OOing this produces a phase shift of approximately 84°,
while limiting the noise bandwidth. The design criteria
is now given by
Figure 11. Oiflerenliator Response with RD, CD. and l
1
wmax = 20ROCO
It may be that RO is too low, creating a pole at a higher
frequency than 10 wmax. If this is so one can insert a
resistor RO in series with CO, giving the equation
PEAK SHIFT CONSIDERATIONS
The arrangement shown in Figure 12 will eliminate the
current imbalance in the differentiator, and offset in the
comparator, thus minimizing the peak shift at the digital
output. The potentiometer is adjusted with a minimum
sinusoidal Epw at the input, for symmetrical digital
waveform at the digital output, Pin 10.
1
wmax = 20RCO
where R = RO + 0.5RO
1-126
XR·3470Al3470B
ZERO CROSSING DETECTOR
MONOSTABLE #2 (OS2)
The differentiated output signals from the active differ·
entiator are run into a comparator. 8ince the outputs of
the active differentiator are 180· out of phase, the com·
parator will produce an output pulse whenever the dif·
ferentiated signal crosses zero. This is shown in Fig·
ures 7b and 7c.
This one shot is used to adjust the pulse width of the
digital output pulses at Pin 10. The adjustment of this
one shot is done via external components R2 and C2
where
MONOSTABLE #1 (OSl)
The pulse width of the output pulse is given by
1.5 K < R2 < 10K
150pF < C2 < 680pF
This one shot is used to prevent false digital outputs
due to noise at zero crossings as shown at time tA, in
Figure 7a. The adjustment of the one shot is done via
external components R1 and C1 where
to = R2C2 (0.625)
This one shot is triggered on the rising and falling edges
of the time domain filter output, as shown on Figures 7e
and 7f, giving the corresponding digital pulses for the
peaks of the read back signal, shifted by 081 's time, t,
as can be seen from Figures 7a, 7d, and 7f.
1.5K is generated from the supply voltage by means of a resistor divider as shown in Figure 1. Then, VREF is equal to a
fraction of the supply voltage:
Both the one-shot and the timerlcounter type IC's can
be operated in either their monostable or free-running
(i.e., self-triggering) mode. They can also be used for
sequential timing, clock generation, as well as for
pulse-position or pulse-width modulation, as outlined in
Table I.
VREF = VCC
[~]
R1 + R2
(2)
and the basic timing equation becomes independent of
the supply voltage:
Precision Timing
T = RC 1n [1
+
:~]
(3)
Time-Delay Generation
Sequential Timing
--------,
Pulse Generation/Shaping
Pulse-Position Modulation
I A,
Pulse-Width Modulation
I
I
Missing-Pulse Detection
Jl
Sweep Generation
Pulse Counting
I- -I
T
Clock Generation
Table 1. Typical Applications of Monolithic Timers
I
I"
_____ ., J
J ":'
c
~
I
I
MLA'••'A
Figure 1. Exponential-Ramp Type Timing Circuit
1-128
Since the resistors R1 and R2 are inside the IC, their
ratio is set by the design of the IC, and is normally accurate to within ± 1 %. Thus, virtually all the accuracy
of the timing interval is determined by the external R
and C.
(PWM), or pulse-position modulated (PPM) Signals, or
allows the timer circuit to be used as a voltagecontrolled oscillator.
An alternate approach to the design of one-shot timers
is the "linear-ramp generator" circuit, shown in Figure
2. This circuit operates on a principle similar to that of
the basic exponential timer, except the timing capaCitor
C is now charged linearly with a constant current, I, and
generates a linear-ramp waveform with a constant
slope of (I/C). The constant-current is in turn controlled
by an external control voltage, VC, applied to the current source. The total timing interval, T, is the time n'!lcessary for the voltage across C to rise from ground to
VREF> at a constant slope of (I/C), or:
The accurate timing intervals which can be obtained
from commercially available one-shot type timer IC's
are limited to the range of several micro-seconds to
several minutes. For generating very short timing
pulses (in the few micro-second range) the internal time
delays associated with the switching speeds of the
comparator, the flip-flop and the discharge transistor
(i.e., the switch S1) may contribute additional timing errors. Similarly, for long time delays (in the several minute range) which require large values of Rand C, the Input bias current of the comparator, and the leakage currents associated with the timing capaCitor, or the
internal discharge transistor, may limit the timing accuracy of the circuit.
T = (VREF)(C/I)
PRACTICAL LIMITATIONS OF ONE-SHOT TIMERS
(4)
Normally, VREF and Vc (and consequently I) would be
derived from VCC by means of resistor-dividers; therefore, they would be both proportional to Vee. Thus, the
effects of supply voltage variations cancel, and the basic timing equation for the linear-ramp type timer circuit
of Figure 2 becomes
In general, for timing applications requiring time delays
in excess of several minutes, the multiple-cycle or
timerlcounter type timer circuits provide a more economical and practical solution than the one-shot type
IC timers.
T = aRC
Vee
where a is a constant of proportionality set by the internal resistor-dividers within the IC, and Rand C are the
external timing components.
The exponential-ramp type timing circuit of Figure 1 is
inherently simpler and more accurate than the linearramp type circuit. However, the latter has the advantage of providing a linear voltage across the capacitor
which is proportional to the elapsed-time during the timing cycle and can be used as a "linear sweep" or timebase signal for oscilloscope or X-V recorder displays.
I .JL:ES
JLRIGOC_'R_ _ _---'
o"_ _ _ _ _--'
Normally, the internal threshold reference, VREF, of
one-shot IC's is available as a package terminal and
can be modulated by an external input signal. This permits the user to modulate or vary the timing interval by
means of an external control signal. This feature can also be used for generating pulse-width modulated
Tg ' NT
Figure 3. Simplified Block Diagram of a Timer/Counter
TIMER/COUNTER CIRCUITS
Vc
The timerlcounter, or multiple-cycle timing circuits use
the combination of a time-base oscillator and a binary
counter to generate the desired time delay. Figure 3
shows a simplified block diagram of a timerlcounter IC,
which is made up of three basic blocks: (1) a time-base
oscillator; (2) a binary counter; and (3) a control flip-flop.
JL
h-I
With reference to the simplified block diagram of Figure
3, the principle of operation of a timerlcounter can be
explained as follows: when the circuit is at rest, or reset
condition, the time-base oscillator is disabled, and the
counter is reset to zero. Once the circuit is triggered,
the time-base oscillator is activated and produces a
series of timing pulses whose repetition rate is proportional to external timing resistor R, and the capacitor
hlLR'GGER
Figure 2. Block Diagram of a Linear-Ramp Type Timer Circuit
1-129
C. These timing pulses are then counted by the binary counter; and when a pre-programmed count is
reached, the binary-counter resets the control flip-flops,
stops the time-base oscillator and ends the timing cycle. The total timing interval, TO, is then proportional
to N times the (RC) product, where N is the preprogrammed count.
ed by the binary counter; and when a given count, N, is
reached, the control flip-flop is latched in its reset condition until the next trigger input to the circuit.
In most timer/counter designs, it is convenient to set
the ratio of resistors R1 and R2 such that:
(7)
r----,-------------.""'-"O Vee
R,
"
where "e" is the base of the natural logarithm. This
makes the period of the time-base oscillator directly
equal to 1.0 RC and simplifies the selection of external
R or C values for a given timer setting.
.... , -<
JLJl..
T'RC
UNIQUE FEATURES OF TIMER/COUNTERS
The combination of a stable time-base oscillator and a
programmable binary counter on the same IC chip offer
some unique application and performance features.
Some of these are outlined below:
Generating Long Delays with Small Capacitors: For a given
time delay setting, the timer/counter would require a
timing capacitor, C, that is N times smaller than that
needed for the "one·shot" type timer, where N is the
count programmed into the binary counter. Since largevalue, low-leakage capacitors are quite expensive, this
technique may provide substantial cost savings for generating long time delays in excess of several minutes.
figure 4. Simplified Schematic of a Time-Base Oscillator
Circuit
Time-Base Oscillator: The time-base oscillator used in
most of the timer/counter IC's is derived from the simple exponential-ramp type timer circuit. Figure 4 shows
the simplified circuit diagram of such an oscillator. The
timing components, Rand C, are external to the chip.
The operation of such an oscillator can be described as
follows: when the circuit is at rest the flip-flop is latched
in its reset state, and the transistor 01 is "off", the external capacitor C is fully charged to a voltage approxi·
mately equal to VCC. When the circuit is triggered, the
flip-flop is unlatched and set, which causes the discharge transistor 01 to turn "on" and discharge C rapidly. When the voltage across C discharges to the voltage level VB, the comparator #2 changes state, resets
the flip-flop and turns 01 "off". Then, C charges toward
VCC with a time constant set by the external Rand C.
When the voltage across it reaches the upper threshold, VA, comparator #1 changes state and sets the flip·
flop again, and discharges C back to the lower threshold level. VB. In this manner, the circuit continues to oscillate, with the voltage level across C exponentially
rising to VA, then rapidly decaying to VB, and then repeating its cycle. The output of the circuit is a sequence of narrow pulses, with a repetition rate T, given
as:
Generating Ultra-Long Delays by Cascading: When a cascading two timer/counters, one cascades the counter stages of both timers. Since the second timer/counter further divides down the counter output of the first timer,
the total available count is increased geometrically,
rather than arithmetically. For example,if one timer/
counter gives a time delay of NRC, two such timer/
counters cascaded will produce a time delay of N2 RC
where N is the count setting of the binary counter. Thus,
a cascade of two timer/counter IC's, each with an a-bit
binary counter, can produce a time delay in excess of
32,000 RC.
Generating Multiple Delays From Same KC Setting: By using a
programmable binary counter, whose total count can
be programmed between a minimum count of 1, to a
maximum count of N, one can obtain N different time
intervals from the same external RC setting.
Easy to Set or Calibrate: Although timer/counters are normally used for generating long time delays or intervals,
their accuracy characteristics are only determined by
the characteristics of the time-base oscillator. The
counter section does not affect the over-all timing accuracy. Thus, time setting or calibration for long interval
timing can be done quickly, without waiting for the entire timing cycle, by setting the accuracy of the timebase oscillator.
(6)
where R1 and R2 are the internal bias resistors setting
up the threshold levels VA and VB. The train of output
pulses coming out of the time-base oscillator are count-
1·130
Choosing the Right IC Timer
Because of its versatility, the monolithic IC timer offers
a very wide range of applications in circuit or system
design. However, during the design phase, once the
"paper design" is accomplished, the user is faced with
the key question: which IC timer is the best choice for a
given application? If the performance characteristics
and the limitations of the timer IC is not carefully considered, the total system performance may be degraded; similarly, if the timing function is overspecified with
an excessive amount of "overkill", particularly with regards to its stability and accuracy requirements, then
the system cost will increase unnecessarily.
Sequential Timing: Many timing applications require se·
quencing of timing functions, i.e., one timer completes
its operation and initiates the next timer, and so on.
Since these applications require a multiplicity of timer
circuits, they are best served by dual-timer IC's, such
as the XR-556 or the XR-2556.
Delayed Timing: Certain timing applications require that
the start of the timing pulse be delayed by a specific
time from the occurrence of the trigger. This can be
easily accomplished by using a dual-timer, such as the
XR·556, where one section of the dual·timer can be
used to set the initial "delay" subsequent to the trigger;
and the second section can be used to generate the actual timing pulse.
The key selection criteria in choosing the right timer for
the job is finding the monolithic IC which will result in
the lowest system cost (including the external components) for a given performance requirement.
Event Counting: In such an application, one needs to
keep an accurate count of "events" which are normally
a series of incoming pulses. This function can be easily
performed with a programmable timer/counter IC, such
as the XR-2240, where the binary counter section can
be programmed to count a given number of input
pulses and stop the count, and/or reset the circuit when
the programmed count is reached. In the case of the
XR-2240, the existing count in the counters is displayed
in a a-bit parallel binary-format.
A very large majority of applications for IC timers can
be classified into one of the four categories listed below:
• Interval or Event Timing
• Pulse Generation and Shaping
• Oscillation or Clock·Generation
• Ramp Generation
These categories of applications are discussed in more
detail in the following sections, with the particular emphasis on "choosing the right IC timer" for the particular application.
Digitally-Programmed Timing: Some timing applications
may require that the timing interval be digitally programmable, without switching additional precision resistors and capacitors into the circuit. Such a function
can be easily achieved by using a programmable timer/
counter, such as the XR-2240, where output duration
can be programmed from 1.0 RC to 255 RC, in 1 RC increments, where Rand C are the external timing components.
INTERVAL OR EVENT TIMING
In such an application one uses the IC timer either to
control the time interval between events, or the dura·
tion of an event. A typical example of such application
would be to control the opening or closing of an electro·
mechanical relay or sequencing of indicator lights.
PULSE GENERATION AND SHAPING
General Purpose Timing: Most timing applications fall within the time interval range of a few microseconds to several minutes. For such applications the basic one-shot
timer, such as the XR-555, is often the best choice,
based on its low cost and versatility.
A popular class of applications for the one-shot type
timers is pulse shaping or stretching. Some specific examples of such applications and the recommended
types of IC timers for each are given below.
Pulse Stretching: In such an application the IC timer is
operated in its monostable mode and is triggered by an
input series of pulses, whose repetition period is longer
than that timing period of the IC. The output from the
timer will then have the same repetition rate as the input pulse train, except that each output pulse will now
have a uniform duration or length, as set by the RC time
constant of the timer. The twolC's best suited to this
application are the XR-555 and the XR-320. The XR-555
has the advantage of low unit price, whereas the
XR-320 has the advantage of being able to trigger on
either positive- or negative-going edge of the input
pulses.
Low-Power Timing: Many timing applications involving
battery-operated or portable equipment, require a lowpower timer which can perform the general purpose
timing functions with a minimum amount of power dissipation. The XR·L555 Micropower Timer IC, which oper·
ates with less than 1 mW of power dissipation and with
supply voltages as low as 2.7 volts, is especially designed for such applications.
Long Interval Timing: For timing applications requiring in·
terval timing in the minutes, hours, or days range, the
timer/counter IC's present the most economical approach, since they can produce long time delays using
a small value capacitor. For such an application of the
low-cost XR-2242 Long Range Timer, which operates
on the timer/counter prinCiple, is the most cost·
effective circuit.
Delayed-Pulse Generation: In this application it is necessary to convert the input pulse train to a different pulse
sequence which has the same repetition rate but a different duration and a different phase. This function can
1-131
be accomplished with a dual-timer circuit, such as the
XR-556 or the XR-2556, where the first timer which is
triggered by the input signal, sets the phase difference
or "delay" between the input and the output pulse sequence; and the second timer which is triggered at the
trailing-edge of the first one, sets the output pulsewidth.
Mlcropower Oscillator: Battery operated or remote-controlled instruments often require a low-power clock oscillator. The XR-L555 Micropower Timer, which operates
with less than 1 mW of power drain, is therecommended choice for such applications, since it dissipates 1/15th the power of the conventional 555-type
timer.
Pulse Blanking: In this application it is necessary to selectively "interrupt" or "blank-out" a pulse train. Such
an application can be performed using a dual-timer IC,
such as the XR-556, where one section of the timer can
be operated as a "pulse-stretcher" triggered by the input pulse train; and the second timer section can be
triggered by a separate timing signal and serve as an
enable/disable control for the first timer, thus interrupting or "blanking" its output during its timing interval.
Voltage-Controlled Oscillator: Voltage-controlled oscillator
(VCO) circuits find a wide range of applications in
phase-locked loop systems. The XR-555 (or its lowpower/low-voltage version of the XR-L555) which has a
separate modulation terminal (Pin 5) can be used as a
VCO by applying the proper control voltage to its modulation terminal and operating the IC in its self-triggering
mode.
Low-Voltage Oscillator: Low threshold CMOS logic circuits
Pulse-Width Modulation: In certain timing applications it is
normally require stable clock oscillators which can operate with a single 3 volt supply. The XR-L555 Micropower Timer which can operate with supply voltages as
low as 2.7 volts is particularly suited for such applications.
necessary to modulate the pulse-width of an output
pulse sequence, without affecting its repetition rate.
Such a requirement can be met by a one-shot timer,
such a~ the XR-555, operating in its monostable mode
and being triggered by a fixed-frequency input pulsetrain. The width of the output pulses from the timer IC
can be modified without affecting the repetition rate, by
simply applying a control-voltage to the modulation terminal of XR-555.
Ultra-Low Frequency Oscillator: Certain battery operated or
remote-controlled equipment require a stable ultra-low
frequency clock oscillator, whose frequency can be as
low as one cycle per day. The XR-2242 Long-Range
Timer circuit which produces a square-wave output
with a period of 256 RC, when operating in its freerunning mode, is a very cost-effective replacement for
such an oscillator.
Pulse-Position Modulation: This application requires the
generation of a pulse sequence whose pulse-width is
constant (and usually very narrow) and, whose repetition rate is modulated. Such a function can be easily
implemented using a dual-timer IC, such as the XR-556,
where the second timer generates the narrow output
pulses when triggered by the output of the first timer.
The first timer section is then operated in its freerunning (Le., astable) mode and its frequency is then
externally modulated by applying a control-voltage to its
modulation terminal.
Digitally-Programmed Oscillator: In certain applications it
may be necessary to program the frequency of an oscillator by means of a binary control signal, without
switching additional resistors or capacitors .into the circuit. The XR-2240 Programmable Timer/Counter, when
operating in its delayed-trigger mode (see Exar Application Note AN-O?) can be used in such an application to
generate an output frequency whose period is equal to
(N + 1)RC, where N is the binary count which can be
digitally programmed by an external 8-bit binary signal,
to be any inleger between 1 and 255.
OSCILLATION OR CLOCK-GENERATION
IC Timers can be operated in their free-running or "selftriggering" mode, to generate periodic timing pulses.
Since the output pulse-width or the frequency can be
controlled by the choice of external resistors and capacitors. These circuits make excellent low-cost clock
oscillators, for a number of digital systems. Some of
these applications are outlined below.
Binary Pattern Generator: In certain test instrumentation
design, it is necessary to generate a pseudorandom binary data pattern, which would then repeat itself periodically. The XR-2240 Programmable Timer/Counter
which provides eight separate "open-collector" outputs, can perform such a function by selective Shorting
of one or more of its outputs to a common pull-up resistor.
Clock Generator: In such applications, the IC is used to
generate a fixed-frequency output waveform with nearly
50% duty cycle. The XR-555 timer, whose output dutycycle can be controlled by the choice of two external
resistors, is ideally suited for such an application, for
clock frequencies up to 300 kHz.
Tone-Burst Generator: Some instrumentation applications
require the generation of a certain tone or frequency
signal, at periodic intervals. This function can be accomplished using a dual-timer IC, such as the XR-556
or the XR-2556, where one of the timer sections would
operate as a keyed oscillator which is turned "on" and
"off" by the other timer section. The output of the first
timer section will then be a "tone-burst", which will be
present only during the timing cycle of the second timer.
High-Current Oscillator: Certain oscillator applications require that the circuit output should be able to source or
sink high load currents ("" 100 mA) in order to drive
electromechanical relays or capacitive loads. The
XR-555 Timer IC, which can provide up to 200 mA of
current drive, is well suited for such applications.
1-132
RAMP GENERATION
from the ground level and rises up to a voltage level approximately equal to 80% of the supply voltage, during
the timing interval. Since the current-source output at
Pin 3 is a high impedance terminal, the sweep or linear
ramp signal at this point should be buffered by a high
impedance op amp connected as a voltage follower.
amp connected as a voltage follower.
In a number of timing applications, it is necessary to
generate an analog voltage which is proportional to the
time elapsed during the timing cycle. This function is
particularly useful for generating linear sweep voltage
for oscilloscope or X-V recorder display applications
and it can be accomplished either linear/y or digitally,
as described below.
Digital Ramp Generalor: In certain applications, a digitally
generated "staircase" voltage is preferred over a linear
ramp signal. Such a digital ramp signal can be generated using the XR-2240 Programmable Timer/Counter,
along with an external resistor ladder and a currentsumming op amp. The digital ramp signal is particularly
useful for analog-Io-digital conversion or digital sampleand-hold applications.
tions.
Linear Ramp Generator: A linear ramp can be obtained by
charging a timing capacitor with a constant-current
source. Since the XR-320 Timer IC operates on such a
principle, it is ideally suited for this application. Upon
triggering, the XR-320 produces a positive-going ramp
at its current-source output (Pin 3). This ramp starts
1-133
XR·320
Monolithic Timing Circuit
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-320 monolithic timing circuit is designed for use
in instrumentation and digital communications equipment, and for a wide variety of industrial control and
special testing applications. In many cases, this circuit
provides a monolithic replacement for mechanical or
electromechanical timing devices.
CIJHHfNI
suunc(
INPut
The XR-320 timing circuit generates precise timing
pulses (or time delays) whose repetition rate (or length)
is determined by an external timing resistor, R, and timing capacitor, C. The timing period is exactly equal to
2RC and can be continuously varied from 1 "sec to 1
hour. The circuits can be operated in a monostable or
free-running (self-triggering) mode. They can be used
for sequential timing and sweep generation, and also
for pulse-position and pulse-width modulation.
CIIRfUNI
HIGH
nuiPut
CURRENT
OUTPUT
sounct
SIJ 1
'~(GA'IVf.
lOGIC
OutPUT
GOIN"
flOHCitRI
S(ll
IPOSl1tVf.
GOING
'RltjUrRI
The XR-320 Integrated circuit is comprised of a stable
internal bias reference, a precision current source, a
voltage comparator, a flip-flop, a timing switch, and a
pair of output logic drivers. The high current output at
pin 12 can sink or source up to 100 milliamps of current.
Part Number
Package
FEATURES
XR-320P
Plastic
RlSfl
ORDERING INFORMATION
Wide Timing Range: 1 "sec to 1 hour
High Accuracy: 1 %
Excellent Temperature Stability: 100 ppm/oC
Wide Supply Voltage Range: 4.5V to 18V
Triggering with Positive or Negative-Going Pulses
Programmable
Resistor Programming: 3 decades
Capacitor Program: 9 decades
Logic Compatible Outputs
High Current Drive Capability: 100 mA
Operating Temperature
O°C to +70°C
SYSTEM DESCRIPTION
The XR-320 is an extremely versatile monolithic timer
capable of delays ranging from 1 "sec to 1 hou r. It
works with both positive and negative triggering, and
features both normally high and normally low outputs.
An on board current source, programmable by an external resistor, changes the timing capacitor. This produces a true ramp function and allows accurate timing
intervals equal to 2 RC.
APPLICATIONS
Precision Timing
Time-Delay Generation
Sequential Timing
Pulse Generation/Shaping
Pulse-Position Modulation
Pulse-Width Modulation
Sweep Generation
Positive going triggering is applied to Pin 6; negative
triggering Is applied to Pin 5. After a trigger pulse is applied, the open collector output (Pin 10) will go high and
the high current output (Pin 12) switches into the current sink mode. At timeout, the open collector pulls low,
and can sink 10 mA; the high current output goes high
and can source 100 mA. Utilizing the high current output requires a pull-up resistor from Pin 10 to + Vee.
The resistor must limit current to no more than 10 mA;
1 mA is sufficient. Timing is interrupted and the device
is reset when Pin 7 is grounded. Astable operation is attained by tying the negative going (falling) trigger (Pin 5)
to the timing capacitor (Pin 3). In this configuration, the
device will automatically ret rigger itself upon completion of the timing interval.
ABSOLUTE MAXIMUM RATINGS
Power Supply
Internal Power Dissipation
Plastic Package:
Derate above TA = +25°C
Storage Temperature Range
GROUND
18 volts
750mW
625 mW
5 mW/oC
- 65°C to + 150°C
1-134
XR·320
ELECTRICAL CHARACTERISTICS
Tast Conditions: Supply Voltage
= 12V
±5%, Test Circuit of Figure 2, TA
= 25°C, unless otherwise specified.
XR-320
PARAMETERS
MIN
Supply Voltage
Quiescent Supply Current
V+ = 5V
V+ = 12V
V+ = 18V
4.5
MAX
UNITS
18
Vdc
2.0
6.0
10.0
3.5
7.0
12.5
mA
mA
mA
2.5
6.5
12.0
4.0
8.0
14.0
mA
mA
mA
Timing Accuracy
V+ = 5V
V+ = 12V
V+ = 18V
1.0
1.0
1.0
5.0
5.0
5.0
%
%
%
Timing Cycle Supply Current
V+ = 5V
V+ = 12V
V+ = 18V
TYP
Temperature Drift
100
Timing vs. Supply Voltage
0.1
Stand-by Voltage (Pin 3)
0.7
Comparator Threshold
Voltage (Pin 3)
V+ = 5V
V+ = 12V
V+ = 18V
Current Source Input
Voltage (Pin 1)
V+ = 5V
V+ = 12V
V+ = 18V
Trigger Voltage
Set (Pin 5)
Set 2 (Pin 6)
Reset (Pin 7)
Output 1 (Pin 10) (Normally low)
"low" Voltage
"High" Voltage
Rise Time
Fall Time
Output 2 (Pin 12) (Normally high)
"High" Voltage
"low" Voltage
Rise Time
Fall Time
ppm/oC
0.5
%N
V
4.5
2.4
5.2
8.4
6.0
V
V
V
9.0
4.15
9.75
16.15
10.6
V
V
V
0.5
1.0
1.4
0.7
Trigger Current
Set 1 (Pin 5)
Set 2 (Pin 6)
Reset (Pin 7)
1.5
1.5
V
V
V
10
60
30
p.A
p.A
p.A
0.1
5.0
140
50
V
V
nsec
nsec
10.4
V
V
nsec
nsec
4.0
CONDITIONS
1.5
100
40
See Figure 11
See Figure 12
Isource = 100 mA
Isink = 100 mA
DEFINITIONS
Timing Accuracy:
the timing error solely introduced by the XR-320, defined in per cent
as:
100 X
Timing vs Supply
Voltage:
measured timing
2 RC based on actual
pulse length - component values
%
2 RC based on actual component values
the maximum timing drift over the power supply range of 5 to 18 volts
referenced to 12 volt operation, defined in per cent per volt as:
100 X
15
max. timing pulse length
min. timing pulse length
over 5 to 18 volt supply -over 5 to 18 volt supply %N
timing pulse length with 12 volt supply
1-135
Stand-by Voltage:
Comparator Threshold
Voltage (Pin 3):
Trigger Voltage:
the voltage between pin
3 and ground in reset
condition.
the voltage at which the
internal comparator triggers the flip-flop and the
timing capaCitor discharges.
the DC voltage level applied to each set or reset terminal which
causes the output to
change state.
EQUIVALENT SCHEMATIC DIAGRAM
OPERATING INSTRUCTIONS
A'IooK
Figures 2 and 3 show typical connections for the XR320. Only three external components are required for
basic operation: the resistor R and capacitor C which
determine the time delay (2RC); and an external load resistor, RL. The circuit provides two independent logic
outputs: a medium current output (up to 10 mAl at pin
10, and a high current output (up to 100 mAl at pin 12.
The output at pin 10 is of the "bare-collector" type
which requires an external pUIl-uf resistor, RL, connected between this terminal and V for proper circuit operation.
J.::.-"'-- 30
For this application, the XR-320 should be connected
as shown in Figure 9.
CL
::E
:>
::E 20
~
::E 10
The modulation input is applied to pin 1 through coupling capacitor, ee. The input signal modulates the current through the timing resistor, R, and, in turn, changes
the width of the output timing pulses. The resistor RM,
in series with the signal source, is used to control the
amount of modulation for a given input signal level.
o
/
o
~
0.25
/
/
Yf
----
.,;:
"
,/
0_5
0_75
1_0
1.25
VOLTAGE LEVEL AT PIN 5 (VOLTSI
R
Figure 11. Minimum Pulse Width lor Triggering at Pin 5
1--+--0 OUTPUT 2
1--+--0 OUTPUT 1
Figure 9. Circuit Connection lor Pulse-width Modulation
\,
i
"'
60
i\." •
~.I.~ ....
Yo!
" q,....r.
0
....
X
u
70
I
TA· 25 C
./
10""
•
'4-"\~
X
~
~---
9
~
~
..,j
Yo!
U
a::
~ -4%
•
15
30
20
Z
i
10
o
-6%
10
40
i
s:>
S
5
, '\
I\~
I-
~ -2%
2.5
\
!to
20
~
~~ l\
\
\
~I
o
0.5
1_0
1.5
2.0
VOLTAGE LEVEL AT PIN 6 (VOLTSI
SUPPL V VOLT AG E (VOL TSI
Figure 1D. Change in Timing vs. Supply Voltage
Figure 12. Minimum Pulse Width lor Triggering at Pin 6
1-138
2_5
XR·555
Timing Circuit
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-555 monolithic timing circuit is a highly stable
controller capable of producing accurate timing pulses.
It is a direct, pin-for-pin replacement for the SEINE 555
timer. The circuit contains independent control terminals for triggering or resetting if desired.
In the monostable mode of operation, the time delay is
controlled by one external resistor and one capacitor.
For astable operation as an oscillator, the free-running
frequency and the duty cycle are accurately controlled
with two external resistors and one capacitor (as
shown in Figure 2).
ORDERING INFORMATION
The XR-555 may be triggered or reset on falling waveforms. Its output can source or sink up to 200 mA or
drive TTL circuits.
FEATURES
Direct Replacement for SEINE 555
Timing from Microseconds Thru Hours
Operates in Both Monostable and Astable Modes
High Current Drive Capability (200 mAl
TTL and DTL Compatible Outputs
Adjustable Duty Cycle
Temperature Stability of 0.005%/OC
Part Number
Package
Operating Temperature
XR-555M
XR-555CM
XR-555CP
Ceramic
Ceramic
Plastic
- 55°C to + 125°C
O°C to + 70°C
O°C to + 70°C
SYSTEM DESCRIPTION
The XR-555 is an industry standard timing circuit capable of both monostable and astable operation with timing intervals ranging from low microseconds up
through several hours. Timing is independent of supply
voltage, which may range from 4.5 V to 18 V. The output stage can source or sink 200 mAo
APPLICATIONS
Precision Timing
Pulse Generation
Sequential Timing
Pulse Shaping
Clock Generation
Missing Pulse Detection
Pulse-Width Modulation
Frequency Division
Pulse-Position Modulation
Appliance Timing
In the monostable (one shot) mode, timing is determined by one resistor and capacitor. Astable operations (oscillation) requires an additional resistor, which
controls duty cycle. An internal resistive divider provides a reference voltage of 2/3 VCC, which provides a
timing interval of 1.1 RC. As the reference is related to
Vee, the interval is independent of supply voltage; however, for maximum accuracy, the user should ensure
VCC does not vary during timing.
The output of the XR-555 is high during the timing interval, and pulls low at timeout. It is triggered and reset on
falling waveforms. The·control voltage input (Pin 5) may
serve as a pulse width modulation point.
ABSOLUTE MAXIMUM RATINGS
18 volts
Power Supply
Power Dissipation (package limitation)
385 mW
Ceramic Package
300 mW
Plastic Package
2.5 mW/oC
Derate above + 25°C
- 65°C to + 125°C
Storage Temperature
For applications requiring dual matched 555-type timers, see the XR-556 and XR-2556. For low voltage andl
or low power drain applications, consider the XR-L555
and XR-L556 devices.
1-139
XR·555
ELECTRICAL CHARACTERISTICS
Test Conditions: (TA = 25°C, VCC = + 5V to + 15V, unless otherwise specified.)
XR-555M
PARAMETERS
Supply Voltage
MIN
TYP
4.5
XR-555C
MAX
MIN
18
4.5
TYP
MAX
UNITS
16
V
CONDITIONS
3
10
5
12
3
10
6
15
mA
mA
Low State Output (Note 1)
Vee = 5V, RL = co
Vee = 15V, RL = co
Timing Error (Monostable)
Initial Accuracy
Orin with Temperature
Drift with Supply Voltage
0.5
30
0.05
2.0
100
0.2
1.0
50
0.1
3.0
%
ppm/oC
RA, RB = 1 KO to 100 KO
Note 2, e = 0.1 I'F
ooe s TA s75°e
0.5
%N
Timing Error (Astable)
Initial Accuracy (Note 2)
Drift with Temperature
Drift with Supply Voltage
1.5
90
0.15
Supply Current
2.25
150
0.3
10.0
3.33
%N
11.2
4.2
Threshold Voltage
9.4
2.7
10.0
3.33
10.6
4.0
Trigger Voltage
1.45
4.8
t67
5.0
1.9
5.2
1.67
5.0
0.5
0.9
0.5
2.0
Trigger Current
Reset Voltage
0.4
Reset Current
Threshold Current
0.7
1.0
0.4
1.0
8.8
2.4
%
ppm/oe
0.4
RA, RB = 1 KO to 100 KO
e = 0.1 I'F
Vee = 15V
V
V
Vee
Vee
V
V
Vee
Vce
= 15V
= 5V
= 5V
= 15V
j4A
0.7
1.0
V
0.4
1.5
mA
Trigger Input High
0.1
0.25
j4A
(Note 3)
3.33
10.0
4.2
11.2
V
V
0.25
0.2
0.3
0.25
0.35
V
V
0.15
0.5
2.2
0.1
0.4
2.0
2.5
0.1
0.25
3.33
10.0
4.0
10.6
0.10
0.05
0.1
0.4
2.0
2.5
12.5
V
= 5V
= 15V
Vee = 5V
Isink . = 8.0 mA
Isink = 5.0 mA
Vee = 15V
Isink = 10 mA
Isink = 50 mA
Isink = 100 mA
Isink = 200 mA
Isource = 100 mA
Vee = 5V
Vee = 15V
Isource = 200 mA
Vee = 15V
Turn Off Time (Note 4)
0.5
0.2
0.5
I's
VRESET High
Rise Time of Output
100
200
100
300
nsec
Fall Time of Output
100
200
100
300
nsec
Discharge Transistor Leakage
20
100
20
100
nA
Control Voltage level
2,7
9.4
2.4
8.8
Output Voltage Drop (Low)
0.25
0.75
2.5
V
V
V
V
Output Voltage Drop (High)
3.0
13
3.3
13.3
2.75
12.75
12.5
V
V
3.3
13.3
Vee
Vee
Note 1: Supply current when output IS high IS tYPically 1.0 mA less.
Note 2: Tested at Vee = 5V and Vee = 15V.
Note 3: This will determine the maximum value of RA + RB for 15V operation. The maximum total R = 20
megohms and for 5V operation, the maximum RT = 3.4 megohms.
Note 4: Time measured from a positive-going input pulse from 0 to 0.8 x Vee into the threshold to the drop from
high to low of the output. Trigger is tied to threshold.
1-140
XR·555
5
CONTROL
'VCCo-----~------~--------~--~~--------~--~----------~~--~--_T------_,
A13
3.91<.
THRESHOLD
A10
3
7K
OUTPUT
G"
A,
'K
RESET
OISCHAAGE0------,
A,
A,
A6
tOOK
10K
1
'K
GND~
EQUIVALENT SCHEMATIC DIAGRAM
r-------~----~-o
T
11 RAe
JL
'c-
T
If
OUTPUT
l..SlS
0----<:)-,---1
-i
X R 555
OUTPUT
XR-555
1---<>----,
~~P~~RO L O----'---I
T R I GG E R 0----<0-:--1
I-=-
f"'~--~~-
(R A + 2RslC
0.01 fJF
CONTROL
VOLTAGE
RB
DUTY CYCLE" RA + 2RB
Figure 1. Monostable (One-Shot) Circuit
Figure 2. Astable (Free-Running) Circuit
1·141
+Vee
XR·L555
Micropower Timing Circuit
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-L555 is a stable micropower controller capable
of producing accurate timing pulses. It is a direct replacement for the popular 555-tlmer for applications requiring very low power dissipation. The XR-L555 has
approximately 1/15th the power dissipation of the standard 555-timer and can operate down to 2.7 volts without sacrificing such key features as timing accuracy
and frequency stability. At 5-volt operation, typical
power diSSipation of the XR-L555 is 900 microwatts.
The circuit contains independent control terminals for
triggering or resetting if desired. In the monostable
mode of operation, the time delay is controlled by one
external resistor and one capacitor. For astable operation as an oscillator the free-running frequency and the
duty cycle are accurately controlled with two external
resistors and one capacitor as shown in Figure 2. The
XR-L555 is triggered or reset on falling waveforms. Its
output can source up to 100 mA or drive TIL circuits.
ABSOLUTE MAXIMUM RATINGS
Power Supply
18 volts
Power Dissipation (package limitation)
Ceramic Package
385 mW
Plastic Package
300mW
2.5 mW/oC
Derate above +25°C
Storage Temperature
- 65°C to + 125°C
ORDERING INFORMATION
Because of its temperature stability and low-voltage
(2.7V) operation capability, the XR-L555 is ideally suited
as a micropower clock oscillator or VCO for low-power
CMOS systems. It can operate up to 1500 hours with
only two 300 mA-Hr NiCd batteries.
Part Number
Package
Operating Temperature
XR-L555M
XR-L555CN
XR-L555CP
Ceramic
Ceramic
Plastic
- 55°C to + 125°C
O°C to + 70°C
O°C to + 70°C
SYSTEM DESCRIPTION
FEATURES
The XR-L555 is a micropower timing circuit similar to
the industry standard 555-type timer. It is capable of
both monostable and astable operation with timing intervals ranging from low microseconds up through several hours. Timing is independent of supply voltage
which may range from 2.7 V to 15 V. The output stage
can source 50 mA.
Pin Compatible with Standard 555 Timer
Less than 1 mW Power Dissipation (V + = 5V)
Timing from Microseconds to Minutes
Over 1000-Hour Operation with 2 NiCd Batteries
Low Voltage Operation (V + = 2.7V)
Operates in Both Monostable and Astable Modes
CMOS TIL and DTL Compatible Outputs
In the monostable (one shot) mode, timing is determined by one resistor and capaCitor. Astable operation
(oscillation) requires an additional resistor, which controls duty cycle. An internal resistive divider provides a
reference voltage of 2/3 VCC, the interval is independent of supply voltage; however, for maximum accuracy, the user should ensure VCC does not vary during
timing.
APPLICATIONS
Battery Operated Timing
Micropower Clock Generator
Pulse Shaping and Detection
Micropower PLL Design
Power-On Reset Controller
Micropower Oscillator
Sequential Timing
Pulse Width Modulation
Appliance Timing
Remote-Control Sequencer
The output of the XR-L555 is high during the timing interval. It is triggered and reset on falling waveforms.
The control voltage input (Pin 5) may serve as a pulse
width modulation point.
For applications requiring dual L555-type timers, see
the XR-L556.
1-142
XR·L555
ELECTRICAL CHARACTERISTICS
Test Conditions: (TA
= 25°C, VCC = + 5V,
unless otherwise specified.)
XR-L555M
PARAMETERS
MIN
Supply Voltage
TYP
XR-L555C
MAX
MIN
15
2.7
2.7
TYP
MAX
UNITS
15
V
500
p.A
Supply Current
150
190
300
Timing Error
Initial Accuracy
Drift with Temperature
Drift with Supply Voltage
0.5
30
0.05
Threshold Voltage
2.0
100
1.0
50
0.05
%
ppm/·C
%IV
2/3
xVCC
1.9
5.2
1.67
5.0
V
V
2/3
Trigger Voltage
1.45
4.8
1.67
5.0
0.5
Trigger Current
Reset Voltage
0.4
Reset Cu rrent
1.0
0.4
0.1
Threshold Current
Control Voltage Level
2.90
9.6
Output Voltage Drop (Low)
0.7
1.0
0.1
0.25
3.80
10.4
0.1
0.3
2.60
9.0
VCC
VCC
3.3
13.3
2.75
12.75
0.1
0.25
,..A
3.33
10.0
4.00
11.0
V
0.25
0.35
V
= 5V
= 15V
Isink = 1.5 mA
Isource = 10 mA
VCC = 5V
VCC = 15V
Isource = 100 mA
VCC = 15V
VCC
VCC
V
V
3.3
13.3
12.5
12.5
V
Rise Time of Output
100
100
nsec
Fall Time of Output
100
100
nsec
Discharge Transistor
Leakage
0.1
0.1
p.A
T= 1.1 RAC
R
L 4
~OUTOP_U_T-o~3~
!--!-l
If
= 5V
= 15V
mA
Output Voltage Drop (High)
3.0
13
8
~
OUTPCU~T~~3~~__"
XR-L~r;5
XR-L555 1-0----,
TRIGGER 2
CONTROL
5
INPUT O--o-:'-L--,_J
f =
'_46
iR A +2R s )C
RS
DUTY CYCLE = RA + 2Rs
Figure 1_ Monostable (One-Shot) CircuH
Figure 2_ Astable (Free-Running) CircuH
1-143
00
RA, RS = 1 KG to
100 KG
C = 0.1 ,..F
O·C s TA s 75°C
V
0.1
3.33
10.0
Low State Output
VCC = 5V, RL =
p.A
0.5
0.7
CONDITIONS
XR·L555
CHARACTERISTIC CURVES
GENERAL CHARACTERISTICS
400
_
.is
320
T~'~2SJ~ ~ ~t2~OC
e-. 1--
!zeo
/"
240
1/
I<
~200
> '60 l J
~
.20
H
V
I:::: ,......
-,......
V- ::::: p- ~A
i-'"
"'.7Sr)C-
r-
500
~
6
8
+4
~ +2
V
:i
" +.
V
Z
v
to-
J
r-T " . " 5 C
O
TA --2SoC
0
Z
0
600
I<
200
400
1 i
I I
./
V
0.2
0.3
o
0.1
0.4
0.2
0.3
~ 2
2.0
.
L
I<
If
"z I"-- r~ 0
e
L
f"\
-,
N
:;
~
~
~ -2
v:
I
I
Z
-4
o
5
10
15
-~25
20
Figura 6. Typical Timing Accuracy as a
Function 01 Supply Vollage
!
~ +2
. JJ.oJ .,H:J
o
>
ffi
~
.
i
.5
Sl;.:: ~ Rsl.oolK
I<
A
..
N
::o
2
~
-3
o
ro
5
~
"
Figura 9. Typical Frequancy SlabliRy as a
Function 01 Supply Vollage
5DO
TA
,
iii
Iboo
8
~ 100
&
400
-f
I
0
25
50
75
I
1.0
t;
.."
0.1
o
~
I
!
o
0.2
0.4
0.6
D..
1.0
10
w
~
~U
U
Figura 12. Comparison 01 Supply Curranl
Translanl of Conventional 555-Timer wHh
XR-L555 Micropower Timer
i'-.
Figure 11. Normalized Frequency of Oscillation
as a Function 01 Control VoHage
iL
3-
u 0.01
IlOO
~
,--.,--,--,--.,-...,..-,,"'71
l-
IlOO
~
1.0
N
~
10
u
.....
.
VCC '5V
Figure 10. Typical Frequency SlabilRy IS a
Function of Temparature (RA = Ra = 10KIl,
C = O.II'F)
Z
::a
~ O.S
w
XR·L5SS
TIMER
200
I"- t-....
~
-1.5
-25
iL
3-
CONVENTIONAL
SSSoTIMER
-\
\\
0
o
-0.5
100
A
~4OD
.. aoo I - -
~ 1.5
g
-l"-
= :lS"C
"
~
'",
~
I
-4
o
0.2
0.4
0.5
o.a
1.0
Figure 8. Normalized Time Delay as a Function
01 Control VoHage
2.0
i -.
TA -zsoc
I
o
75
1\
w
::;
i
50
+1
~ +0.5
A
.fa . . 1/
I<
2SoC
+1.5
o
>
0
-1
0
Figure 7. Typical Timing Accuracy as a
Function 01 Temperalure (VCC = 51V,
RA = 100KIl, C = 0.01 I'F)
ASTABLE OPERATION
!: +1
0.4
Figure 5. Propagation Delay as a Function of
Voltage Level of Trigger Pulse
g
1/
~ -2
:E
~ .. 3
VC-5~
° /I
~.1
TA'75~
.L
;:
Figure 4. Minimum Pulse-Widlh Required for
Triggering
J
N
800
II
I-0.1
V
I<
I
:1VCC'5V
/
200
~
10 12 14 16 18
000
/
100
..
1.
~.
....
"
.21
600
II
~ +3
-1
400
.200
III
v _z.sv LIl
cc
I II
700
~
iii
MONOSTABLE OPERATION
fa
:E
..
i
Figura 3. Supply Currenl as a Function 01
Supply VoHage
0
-
1000
900
Z 300
2
iii
;:
ii'
=
X
.
I I
J I
I I
TA _+25 bC
1100
0
/"
JV
I
ao
40
.200
.....l-
360
0.001 IL...L-,/'--L..+--'_+--..J
10 ps 1.0 ms
100 m. 10 I
Figure 13. Timing Period, T, as a Function 01
External R-C Nelwork
1-144
0.01
0.001
'--....L_.L--L_-'-.>....J,_~
0.1
1.0
10 100 10K 1.0K lOOK
Figure 14. Free Running Frequency as I
Function of External Timing Components
(Nole: R= RA + 2Ra)
XR·L555
FEATURES OF XR-L555
The XR-L555 micropower timer is, in most instances, a
direct pin-for-pin replacement for the conventional 555type timer. However, compared to conventional 555timer, it offers the following important performance features:
enced to 2/3 VCC with the use of three equal internal resistors. When the voltage across the capacitor reaches
this level, the flip-flop is reset, the capacitor is discharged rapidly, and the output level moves toward
ground, and the timing cycle is completed.
Reduced Power Dissipation: The current drain is 1/15th of
the conventional 555-timer.
The duration of the timing period, T, during which the
output logic level is at a "high" state is given by the
equation:
T = 1.1 RAC
No Supply Current Transients: The conventional 555-timer
can produce 300 to 400 mA of supply current spikes
during switching. The XR-L555 is virtually transient-free
as shown in Figure 12.
The time delay varies linearly with the choice of RA and
C as shown by the timing curves of Figure 13. For
proper operation of the circuit, the trigger pulse-width
must be less than the timing period.
Low-Voltage Operation: The XR-L555 operates down to 2.7
volts of supply voltage, vs. 4.5V minimum operating
voltage needed for conventional 555-timer. Thus, the
XR-L555 can operate safely and reliably with two 1.5V
NiCd batteries.
APPLICATIONS INFORMATION
Once the circuit is triggered it is immune to additional
trigger inputs until the present timing-period has been
completed. The timing-cycle can be interrupted by using the reset control (pin 4). When the reset control is
"low", the internal discharge transistor is turned "on"
and prevents the capacitor from charging. As long as
the reset voltage is applied, the digital output level will
remain unchanged, i.e. "low". The reset pin should be
connected to + VCC when not used to avoid the possibility of false triggering.
MONOSTABLE (ONE-SHOT) OPERATION
ASTABLE (SELF-TRIGGERING) OPERATION
The circuit connection for monostable, or one-shot operation of the XR-L555 is shown in Figure 1. The internal flip-flop is triggered by lowering the trigger level at
pin 2 to less than 1/3 of VCC. The circuit triggers on a
negative-going slope. Upon triggering, the flip-flop is
set to one side, which releases the short circuit across
the capacitor and also moves the output level at pin 3
toward VCC. The voltage across the capacitor, therefore, starts increasing exponentially with a time constant 7 = RAC. A high impedance comparator is refer-
For astable (or self-triggering) operation, the correct circuit connection is shown in Figure 2. The external capacitor charges to 2/3 VCC through the parallel combination of RA and RB, and discharges to 1/3 VCC
through RB. In this manner, the capacitor voltage oscillates between 113 VCC and 2/3 Vcc, with an exponential waveform. The oscillations can be keyed "on" and
"off" using the reset control. The frequency of oscillation can be readily calculated from the equations in Figure 2 and Figure 14.
Proven Bipolar Technology: The XR-L555 is fabricated using conventional bipolar process technology. Thus, it is
immune to electrostatic burn-out problems associated
with low-power timers using CMOS technology.
EQUIVALENT SCHEMATIC DIAGRAM
1-145
XR·556
Dual Timer
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-556 dual timing circuit contains two independent 555-type timers on a single monolithic chip. It is a
direct, pin-for-pin replacement for the SEINE 556 dual
timer. Each timer section is a highly stable controller
capable of producing accurate time delays or oscillations. Independent output and control terminals are
provided for each section as shown in the functional
block diagram.
DISCHARGE
In the monostable mode of operation, the time delay for
each section is precisely controlled by one external resistor and one capacitor. For astable operation as an
oscillator, the free-running frequency and the duty cycle of each section are accurately controlled with two
external resistors and one capacitor.
THRESHOLD
DISCHARGE
CONTROL
VOL TAGE
THRESHOLD
CONTROL
VOLTAGE
RESET
RESET
OUTPUT
The XR-556 may be triggered or reset on falling waveforms. Each output can source or sink up to 150 mA or
drive TIL circuits. The matching and temperature tracking characteristics between each timer section of the
XR-556 are superior to those available from two separate timer packages.
TRIGGER
OUTPUT
GROUND
TRIGGER
ABSOWTE MAXIMUM RATINGS
Power Supply
Power Dissipation
Ceramic Dual-In-Line
Derate above TA = 25°C
Plastic Dual-In-Line
Derate above TA = 25°C
Storage Temperature Range
FEATURES
Direct Replacement for SEINE 556
Replaces Two 555-Type Timers
TIL Compatible Pinouts
Timing from Microseconds Thru Hours
Excellent Matching Between Timer Sections
Operates in Both Monostable and Astable Modes
High Current Drive Capability (150 mA each output)
TIL and DTL Compatible Outputs
Adjustable Duty Cycle
Temperature Stability of 0.005%/OC
18V
750 mW
6 mW/oC
625 mW
5 mW/oC
- 65°C to + 150°C
ORDERING INFORMATION
APPLICATIONS
Precision Timing
Pulse Generation
Sequential Timing
Pulse Shaping
Time Delay Generation
Clock Pattern Generation
Missing Pulse Detection
Pulse-Width Modulation
Frequency Division
Clock Synchronization
Pulse-Position Modulation
Appliance Timing
Part Number
Package
Operating Temperature
XR-556M
XR-556CN
XR-556CP
Ceramic
Ceramic
Plastic
- 55°C to + 125°C
O°C to +70°C
O°C to + 70°C
SYSTEM DESCRIPTION
The XR-556 is an industry standard dual timing circuit
capable of both monostable and astable operation with
timing intervals ranging from low microseconds up
through several hours. Timing is independent of supply
voltage, which may range from, 4.5 V to 18 V. The output stage can source or sink 150 mAo Each timer section is fully independent and similar to 555-type devices.
1-146
XR·556
CONTROL
5K
023
OUTPUT
5K
DISCHARGE
5K
GND~
EQUIVALENT SCHEMATIC DIAGRAM
SYSTEM DESCRIPTION (continued)
The output of the XR-556 is high during the timing interval, and pulls low at timeout. It is triggered and reset on
falling waveforms. The control voltage inputs (Pins 3
and 11) may serve as pulse width modulation points.
Matching between sections is typically better than
0.05% initially, with temperature drift trackinQ to ± 10
ppm/oe and supply voltage drift tracking to 0.1 'ioN For
low voltage andlor low power drain applications, consider the XR-L556.
In the monostable (one shot) mode, timing is determined by one resistor and capacitor. Astable operation
(oscillation) requires an additional resistor, which controls duty cycle. An internal resistive divider provides a
reference voltage of 2/3 Vee, which produces a timing
interval of 1.1 Re. As the reference is related to Vee,
the interval is independent of supply voltage; however,
for maximum accuracy, the user should ensure Vee
does not vary during timing.
1-147
XR·556
ELECTRICAL CHARACTERISTICS
Tast Conditions: (Each timer section, TA = 25°e, Vee =
+ 5V
XR·556M
PARAMETERS
Supply Voltage
MIN
TYP
4.5
to
+ 15V,
unless otherwise specified.)
XR·556C
MAX
MIN
18
4.5
TYP
MAX
UNITS
16
V
Supply Current
(Each Timer Section)
3
5
3
6
mA
10
11
10
14
mA
Total Supply Current
(Soth Timer Sections)
6
10
6
12
mA
20
22
20
28
mA
0.5
30
0.05
1.5
100
0.2
.75
50
0.1
3
%
ppm/oC
0.5
%N
Timing Error (Monostable)
Initial Accuracy
Drift with Temperature
Drift with Supply Voltage
Timing Error (Astable)
Initial Accuracy (Note 2)
Drift with Temperature
Drift with Supply Voltage
2.25
150
0.3
1.5
90
0.15
%
ppm/oC
%N
CONDITIONS
Low State Output,
Note 1
VCC = 5V,
RL = 00
Vee = 15V,
RL = 00
Low State Output.
Note 1
Vee = 5V,
RL = 00
VCC = 15V,
RL = 00
Timing, R = 1 KG
to 100 KG
Note 2, C = 1.0 "F
DoC sTA s75°C
RA, RS = 1 KG
to 100 KG
C = 0.1 "F
Vee = 15V
= 15V
= 5V
9.4
2.7
10.0
3.33
10.6
4.0
8.8
2.4
10.0
3.33
11.2
4.2
V
V
VCC
Vee
1.45
4.8
1.67
5.0
1.9
5.2
4.5
1.67
5.0
5.6
V
V
VCC
VCC
0.5
0.9
0.5
2
,.A
= 5V
= 15V
VTRIG = OV
0.4
0.7
1.0
0.7
1.0
V
VTRIG High
Reset Current
0.4
1
0.4
1.5
mA
VRESET
Threshold Current
0.03
0.1
0.03
0.1
"A
Note 3
3.33
10.0
3.80
10.4
3.33
10.0
4.00
11.0
0.10
0.05
0.25
0.20
0.3
0.25
0.35
0.1
0.4
2.0
2.5
0.15
0.5
2.25
0.1
0.4
2.0
2.5
Th reshold Voltage
Trigger Voltage
Trigger Current
Reset Voltage
0.4
Control Voltage Level
2.90
9.6
2.60
9.0
V
V
V
V
V
V
Output Voltage Drop (High)
3.0
13
2.75
12.75
3.3
13.3
12.5
V
V
3.3
13.3
12.5
V
Rise Time of Output
100
200
100
300
nsec
Fall Time of Output
100
200
100
300
nsec
0.05
±10
0.1
0.1
±10
0.2
%
ppm/oC
0.1
0.2
0.2
0.5
%N
Matching Characteristic
Initial Timing Accuracy
Timing Drift with
Temperature
Drift with Supply Voltage
= 5V
= 15V
VCC = 5V
Isink = 8.0 mA
Isink = 5.0 mA
VCC = 15V
Isink = 10 mA
Isink = 50 mA
Isink = 100 mA
Isink = 200 mA
Isource = 100 mA
VCC = 5V
VCC = 15V
Isource = 200 mA
VCC = 15V
Vee
VCC
Output Voltage Drop (Low)
0.25
0.75
2.75
= OV
Note 4
Note 1: Supply current when output is high is typically 1.0 mA less.
Note 2: Tested at Vee = 5V and Vee = 15V.
Note 3: This will determine the maximum value of RA + RS for 15V operation. The maximum total R = 10
megohms, and for 5V operation, the maximum R = 3.4 megohms.
Note 4: Matching characteristics refer to the difference between performance characteristics of each timer section.
1·148
XR·L556
Micropower Dual Timer
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-L556 dual timer contains two independent micropower timer sections on a monolithic chip. It is a direct replacement for the conventional 556-type dual
timers, for applications requiring very low power dissipation. Each section of the XR-L556 dual timer is equivalent to Exar's XR-L555 micropower timer. The circuit
dissipates only 1I15th of the stand-by power of conventional dual timers and can operate down to 2.5 volts
without sacrificing such key features as timing accuracy and stability. At 5 volt operation, typical power dissipation of the dual-timer circuit is less than 2 mW; and
it can operate in excess of 500 hours with only two 300
mA-Hr NiCd batteries.
DISCHARGE
THRESHOLD
CONTROL
VOLTAGE
RElET
OUTPUT
'RIGGER
GROUND
The two timer sections of the circuit have separate controls and outputs, but share common supply and
ground terminals. Each output can source up to 100
mA of output current or drive TIL circuits.
FEATURES
ORDERING INFORMATION
Replaces two XR-L555 Micropower Timers
Pin Compatible with Standard 556-Type Dual Timer
Less than 1 mW Power Dissipation per Section (VCC =
5V)
Timing from Microseconds to Minutes
Over 500-Hour Operation with 2 NiCd Batteries Low
Voltage Operation (Vee = 2.5V)
Operates in Both Monostable and Astable Modes
CMOS TIL and DTL Compatible Outputs
Introduces No Switching Transients
Package
Operating Temperature
Ceramic
Ceramic
Plastic
-55°C to +125°C
O°C to + 70°C
O°C to +70°C
SYSTEM DESCRIPTION
The XR-L556 is a micropower version of the industry
standard XR-556 timing circuit, capable of both
monostable and astable operation with timing intervals
ranging from low microseconds up through several
hours. Timing is independent of supply voltage, which
may range from 2.5 V to 15 V. The output stage can
source 100 mAo Each timer section is fully independent
and similar to the XR-L555.
APPLICATIONS
Battery Operated Timing
Micropower Clock Generator
Pulse Shaping and Detection
Micropower PLL Design
Power-On Reset Controller
Micropower Oscillator
Sequential Timing
Pulse-Width Modulation
Appliance Timing
Remote-Control Sequencer
In the monostable (one shot) mode, timing is determined by one resistor and capacitor. Astable operation
(oscillation) requires an additional resistor, which controls duty cycle. An internal resistive divider provides a
reference voltage of 2/3 VCC, which produces a timing
interval of 1.1 RC. As the reference is related to VCC,
the interval is independent of supply voltage; however,
for maximum accuracy, the user should ensure VCC
does not vary during timing.
ABSOLUTE MAXIMUM RATINGS
Power Supply
Power Dissipation
Ceramic Dual-In-Line
Derate above TA = 25°C
Plastic Dual-In-Line
Derate above TA = 25°C
Storage Temperature Range
Part Number
XR-L556 M
XR-L556 CN
XR-L556 CP
18V
750 mW
6 mW/oC
625mW
5 mW/oC
- 65°C to + 150°C
The output of the XR-L556 is high during the timing interval. It is triggered and reset on falling waveforms.
The control voltage inputs (Pins 3 and 11) may serve as
pulse width modulation pOints.
1-149
XR·L556,
ELELTRICAL CHARACTERISTICS
Tast Conditions: (TA = 25°DC, VCC = +5V, unless otherwise specified)
XR-L556M
PARAMETERS
MIN
Supply Voltage
TYP
XR-L556C
MAX
MIN
15
2.7
2.5
TYP
MAX
UNITS
15
V
Supply Current
(Each Timer Section)
Total Supply Current
(Soth Timer Sections)
150
300
200
500
,.A
300
600
400
1000
,.A
Timing Error
Initial Accuracy
Drift with Temperature
Drift with Supply Voltage
0.5
50
0.5
200
1.0
50
0,5
%
ppm/oC
Threshold Voltage
2/3
2/3
x Vee
1.67
5.0
V
Trigger Voltage
1.45
4.8
1.67
5.0
Trigger Current
1.9
5.2
20
0.4
Reset Voltage
0.4
10
Threshold Current
Control Voltage Level
2.90
9.6
Output Voltage Drop (Low)
V
20
1.0
0.7
Reset Curerent
%N
10
50
3.80
10.4
0.1
0.3
2.60
9.0
1.0
3.3
13.3
2.75
12.75
RA, RS = 1 KO to 100 KO
C = 0.1,.F
O°C s TA s 70°C
Monostable Operation
VCC
VCC
= 5V
= 15V
V
20
100
nA
3.33
10.0
4.00
11.0
V
V
0.15
0.35
V
3.3
13.3
V
V
12.5
12.5
V
Rise Time of Output
200
200
nsec
Fall Time of Output
100
100
nsec
Discharge Transistor
Leakage
0.1
0.1
p.A
= 5V
= 15V
Isink = 1.5 mA
Isource = 10mA
VCC = 5V
VCC = 15V
Isource = 100 mA
VCC = 15V
VCC
VCC
r----..,....-~--ov.
~---..,....-~--ovoc
••
RESET
n
-.J
AL
L
\-T-l
~
RA
1.
"
OUTPUT
OUTPUT
DISCHARGE
DISCtfARGE
112 OF
xn l5S6
If
I--().--,
T>RI-0G-'-R-----TR~,G>G'-R~..___r--~
00
p.A
Output Voltage Drop (High)
3.0
13
Low State Output
Vee = 5V, RL =
nA
0.7
10
3.33
10.0
CONDITION
lflOF XR556
A.
THRESHOLD
CONTROL
I-:
TRIGGER
C
THRESHOLD
CONTROL
INPUT
CONTROL
INPUT
f.~
IRA + 2RBIC
Figura 1. Monostabla (One-Shot) Circuit
DUTyCyCLE.--!!....
RA + 2RB
Figure 2. Astabla (Free-Running) Circuit
1·150
XR·L556
CHARACTERISTIC CURVES
GENERAL CHARACTERISTICS
800
720
T~
_ 640 I-- t -
..
~560
~25J~ X
,/
~ 480
a:
/
!5 400
V
u
> 320
~
t 240
iil
=
T
, A
--
1200
1 1-1-
1
;0
1100
10
-25 C
f-"'"
",_ f--
T A ;::+7SC
160
..J
600
ii?
8
10
/
0.1
12 14 16 18 20
If
l"-
>
..
_T A -·2SoC
.:o
I
I/v
/
........ ~
1
0.2
0,3
BOO
Figure 3. Total Supply Current as a
Function of Supply Voltage
z
o
600
CJ
~
400
~g:
200
+4
a:
~ +2
ffi
Cl
+1
V
Z
i1
;::
0
1/
N
-2
>.
~
w
2
a:
a:
w
o
z
i1
;::
0
~ t-
........
N
::i -,
1'\
~
)
«
:Ii
o
I
o
0.4
0.2
0.6
0.8
1.0
CONTROL VOLTAGE AS FRACTION OF VCC
o
10
15
-3
20
0
25 C
-25
ASTABLE OPERATION
a:
+1
>
~
0
R
o
_ +1.5
l)J
B l--t:1
A
-1
a:
b~RB~,ooIK
o
w -2
..
N
:::;
>,
U
Z
+1
o
>
~ +0.5
w
1.5 I--a
w
\
w
"I'..I-
:J
~
II
f!:
2.0
!!
1;:
II
:J
75
Figure 8. Normalized Time
Figure 7. Typical Timing
Accuracy as a Function of
Delay as a Function of
Temperature
Con trol Voltage
(VCC= 5V, RA = IOOKn,C= O.OltLF)
Figure 6. Typical Timing
Accuracy as a Function of
Supply Voltage
+2
50
TEMPERATURE lOCI
SUPPLY VOLTAGE Vee (VOLTS)
~
I
I
a:
~ -2
-4
w
I
V
0.5
z
~
1;:
/
t= 1.0
~
N
:::;
II
a:
~ -3
I
1/
1.5
:Ii
~
:Ii
2.0
w
Cl
/
il
S -1
~
V
0.4
Figure 5. Propagation Delay as a
Function of Voltage Level of
Trigger Pulse
.
~
:3
0.3
0.2
LOWEST TRIGGER VOLTAGE
LEVEL I X veel
Figure 4. Minimum Pulse-Width
Required for Triggering
V
If"
0,1
0.4
MONOSTABLE OPERATION
~ +3
1/1
I
-I
T A'" _25°C
LOWEST VOLTAGE LEVEL OF
TRIGGER PULSE IX veel
SUPPLY VOLTAGE. Vee (VOL TSI
IO
=75~
I
I
ce =5V
/
200
o 1/
6
Vee· 2.5V/
300
V
=5V+.
e,
I
TA
,000
400
100
4
I
500
:Ii
:J
:Ii
1200
III
1
700
i1
I
80
i
800
Z
.........
=+25~C
900
w
on
-"V
L,....-V
.
i
0
V
TA
iii 1000
c
f!:
o
~
..
-0.5
f!:
S
N
~
II
-4
o
TA = 25°C
I
r
o
10
15
SUPPLY VOLTAGE, Vee (VOLTS)
Figure 9. Typical Frequency
Stability as a Function of
Supply Voltage
i'...
:::;
I
:Ii 0.5
a:
-1.5
-25
I
0,2
Ve(5~
~
I
0
z
-1
Z
20
" i"
1.0
..
r- r--. .......
:::;
~ -3
"
0.4
0.6
0.8
1.0
CONTROL VOLTAGE AS FRACTION OF Vee
o
25
50
TEMPERATURE fOCI
75
Figure 10. Typical Frequency
Stability as a Function of
Temperature
(R A = R8 = IOKn. C = O.IJ.LF)
1·151
Figure t I. Normalized Frequency
of Oscillation as a Function of
Con trol Voltage
XR·L556
FEATURES OF XR-L556
500
TA -Z5OC
The XR-L556 micropower dual timer is, in most instances, a direct pin-far-pin replacement for the conventional 556-type dual timer. However, compared to
conventional 556-timer, it offers the following important
performance features:
A
400
CONVENTIONAL
NE556 DUAL TIMER
C
~
I- 300
.
\
\
Z
IIC
IIC
Reduced Power Dissipation: The current drain is 1/15th of
the conventional 556-type dual timer.
:;)
u
..
200
iil
100
>
t
No Supply Current transients: The conventional 556-timer
can produce 300 to 400 mA of supply current spikes
during switching of either one of its timer sections. The
XR-L556 is virtually transient-free as shown in Figure
-
0
12.
Low-YoHage Dperation: The XR-L556 operates down to 2.7
volts of supply voltage, vs. 4.5V minimum operating
voltage needed for conventional 556-timer. Thus, the
XR-L556 can operate safely and reliably with two 1.5V
NiCd batteries.
'\ ~
X R-L556
DUAL TlrER
o
zoo
600
400
TIME AFTER TRIGGER INPUT (nSoc)
aoo
Figure 12. Comparison of Supply Current transient 01
Conventional NE556 Dual Timer with XR-L556
Micropower Dual Timer
Proven Bipolar Technology: The XR-L556 is fabricated using conventional bipolar process technology. Thus, it is
immune to electrostatic burn-out problems associated
with low-power timers using eMOS technology.
i.e. "low". The reset pin should be connected to + Vee
when not used to avoid the possibility of false triggering.
PRINCIPLES OF OPERATION
ASTABLE (SELF-TRIGGERING) OPERATION
MONOSTABLE (ONE-SHOT) OPERATION
For astable (or self-triggering) operation, the correct circuit connection is shown in Figure 2. The external capacitor charges to 2/3 Vee through the series combination of RA and RB, and discharges to 1/3 Vee through
RB. In this manner, the capacitor voltage oscillates between 113 Vee and 2/3 Vee, with an exponential waveform. The output level at pin 5 (or 9) is high during the
charging cycle, and goes low during the discharge cycle. The charge and the discharge times are independent of supply Voltage. The oscillations can be keyed
"on" and "off" using the reset controls (pin 4 or 10).
The circuit connection for monostable, or one-shot operation is one of the timer sections of the XR-L556 is
shown in Figure 1. The internal flip-flop is triggered by
lowering the trigger level to less than 1/3 of Vee. The
circuit triggers on a negative-going slope. Upon triggerIng, the flip-flop is set, which releases the short circuit
across the capacitor and also moves the output level
toward Vee. The voltage across the capacitor, therefore, starts increasing exponentially with a time constant T = RAe. A comparator is referenced to 2/3 Vee
with the use of three equal internal resistors. When the
voltage across the capacity reaches this level, the flipflop is reset, the capacitor is discharged rapidly, the
output level moves toward ground and the timing cycle
is completed. The duration of the timing period, T, during which the output logic level is at a "high" state is
given by the equation:
u:
S.
10
w
u
Z
1.0
j!
T = 1.1 RAe
~
This time delay varies linearly with the choice of RA and
e as shown by the timing curves of Figure 13. For
proper operation of the circuit, the trigger pulse-width
must be less than the timing period.
0.1
a..
c(
U
ri
0.01
0.001
Once the circuit is triggered it is immune to additional
trigger inputs until the present period has been completed. The timing-cycle can be interrupted by using the
reset control. When the reset control is "low", the internal discharge transistor is turned "on" and prevents the
capacitor from charging. As long as the reset voltage is
applied, the digital output level will remain unchanged
IC-....J£:_.X-.---I.~.L.---L_...L--.J
10 Ils
1.0 ms
100 ms
10 s
TIMING PERIOD, T
Figure 13. Timing Period, T, as a Function 01 External R-C
Network
1-152
XR·L556
The charge time (output high) is given by:
t1 = 0.695 (RA
100
+ RB)C
~
The discharge time (output low) by:
10
~
w
t2 = 0.695 (RB)C
1.0
(.)
Z
<
Thus the total period is given by:
!:
T = t1 + t2 = 0.695 ((RA + 1RB)C
0.1
(.)
<
<
(.)
~
The frequency of oscillation is then:
0.01
(.)
f=.1.=
1.44
and
(RA + 2RB)C
T
0.001
0.1
may be easily found as shown in Figure 14.
10
100 10K 1.0K 100K
f. FREE·RUNNING FREQUENCY (Hzl
The duty cycle D, is given by:
D =
1.0
Figure 14. Free Running Frequency as a Functionof External
Timing Components (Note: R = RA + 2RB)
RB
RA + 2RB
T2 = 1.1 R2C2. In this manner, the unit behaves as a
"delayed one-shot" where the output of Timer 2 is delayed from the initial trigger at pin 6 by a time delay of
T1
APPLICATIONS INFORMATION
INDEPENDENT TIME DELAYS
Each timer section of the XR-L556 can opera:e as an independent timer to generate a time delay, T, set by the
respective external timing components. Figure 15 is a
circuit connection where each section is used sepa·
rately in the monostable mode to produce respective
time delays of T1 and T2, where:
KEYED OSCILLATOR
SEQUENTIAL TIMING (DELAYED ONE-SHOT)
One of the timer sections of the XR-L556 can be operated in its free-running mode, and the other timer section
can be used to key it "on" and "off". A recommended
circuit connection is shown in Figure 17. Timer 2 is
used as the oscillator section, and its frequency is set
by the resistors RA, RB and the capacitor C2. Timer 1 is
operated as a monostable circuit, and its output is connected to the reset terminal (pin 10 of Timer 2).
In this application, the output of one timer section (Timer 1) is capacitively coupled to the trigger terminal of
the second, as shown in Figure 16. When Timer 1 is
triggered at pin 6, its output at pin 5 goes "high" for a
time duration T1 = 1.1 R1 C1. At the end of this timing
cycle, pin 5 goes "low" and triggers Timer 2 through
the capacitive coupling, Ce, between pins 5 thru 8.
Then, the output at pin 9 goes "high" for a time duration
When the circuit is at rest, the logic level at the output
of Timer 1 is "low"; and the oscillations of Timer 2 are
inhibited. Upon application of a trigger signal to Timer
1, the logic level at pin 1 goes "high" and the oscillator
section (Timer 2) is keyed "on". Thus, the output of Timer 2 appears as a tone burst whose frequency is set by
RA, RB and C2, and whose duration is set by R1 and C1
of Figure 17 .
T1 = 1.1 R1C1 and T2 = 1.1 R2C2
.
,
c,
-f
TIMER 1
TIMER 2
13
v'
H-O-.......- - < l OUTPUT :I
1f
TRIGGER
Figure 15. Generation of Two Independent Time Delays
Figure 16. Sequential Timing
1·153
XR·L556
.Vee
R,
~'
v'
1-+..:0-4---=-----0 OUTPUt
1f
1-
TRIGGER
JUlIUl
I
,1
Figure 18. Frequency Divider and Pulse-Shaper
Tl. , .,R 1C
1,46
20'
(R.A+ 2RS}C2
MICROPOWER OSCILLATOR WITH INDEPENDENT
FREQUENCY AND DUTY CYCLE ADJUSTMENT
Figure 17. Keyed Oscillator
If Timer 1 is operated in its astable mode and Timer 2 is
operated in its monostable mode, as shown in Figure
19, then an oscillator with fixed frequency and variable
duty cycle results.
FREQUENCY DIVIDER AND PULSE SHAPER
If the frequency of the input is known, each timer section of the XR-L556 can be used as a frequency divider
by adjusting the length of its timing cycle. If the timing
interval T 1 (= 1.1 R1 C1) is larger than the period of the
input pulse trigger, then only those input pulses which
are spaced more than 1.1 R1C1 will actually trigger the
circuit.
Timer 1 generates a basic periodic waveform that is
then used to trigger Timer 2. If the time delay, T2, of
Timer 2 is chosen to be less than the period of oscilla·
tions of Timer 1, then the output at pin 9 has the same
frequency as Timer 1, but has its duty cycle determined
by the timing cycle of Timer 2. The output duty cycle
can be adjusted over a wide range (from 1 % to 99%)
by adjusting R2.
The output frequency is equal to (1/N) times the input
frequency. The division factor N is in the range:
r----~----,.--<>.vcc
l_1 ----1
When operating either timer section of the XR-2556 in
the monostable mode, a single resistor and a capacitor
are used to set the timing cycle. The discharge and
threshold terminals are also interconnected in this
mode, as shown in Figure 3.
Figure 3_ Monostable (one·Shot) Circuit
Referring to Figure 2, monostable operation of the
XR-2556 is explained as follows: the external timing capacitor e is held discharged by the internal transistor,
To. The internal flip-flop is triggered by lowering the trigger levels (pins 2 or 12) to less than 1/3 Vee. The circuit
triggers on a negative-going slope. Upon triggering, the
flip-flop is set to one side, which releases the short circuit across the capacitor and also moves the output
level at pins 1 or 13 toward Vee. The voltage across the
capacitor, therefore, starts increasing exponentially
with a time constant T = RA- A high impedance comparator is referenced to 2/3 Vee with the use of three
equal interval resistors. When the voltage across the
capaCitor reaches this level, the flip-flop is reset, the
capacitor is discharged rapidly, and the output level
moves toward ground, and the timing cycle is completed.
CONTROL
VOLTAGE
140ft 101
Vee
14
Figure 4_ Monostable Waveforms
Top: Trigger Input
Middle: Exponential Ramp across Timing CapaCitor
Bottom: Output Logie Level
u:
.3
w
u
..
z
«
Figure 2. Functional Diagram of One Timer Section
~
Once the circuit is triggerd it is immune to additional
trigger inputs until the present timing-period has been
completed. The timing-cycle can be interrupted by using the reset control (pins 6 or 8). When the reset control is "low", the internal discharge transistor is turned
"on" and prevents the capacitor from charging. As long
as the reset voltage is applied, the digital output level
will remain unchanged, i.e. "low". The reset pin should
be connected to V+ when not used to avoid the possibility of false triggering.
Figure 5_ Timing Period, T, as a Function of External R-C
Network
OUTPUT
11 OR 13)
GROUND
u
u-
TIMING PERIOD, T (sac_I
1-161
XR·2556
TYPICAL CHARACTERISTICS (Each Timer Section)
ASTABLE (SELF-TRIGGERING) OPERATION
middle is the exponential ramp across the timing capacitor. The bottom waveform is the output logic state
(at pins 1 or 13) during the timing cycle. For proper operation of the circuit, the trigger pulse-width must be
less than the timing period.
For astable (or self-triggering) operation, the correct circuit connection is shown in Figure 15. The external capacitor charges to 2/3 Vee through the parallel combination of RA and RB, and discharges to 1.3 Vee
through RB. In this manner, the capacitor voltage oscillates between 1/3 Vee and 2/3 Vee, with the exponential waveform as shown in Figure 16. The output level at
pin 1 (or 13) is high during the charging cycle, and goes
low during the discharge cycle. The charge and the discharge times are independent of supply voltage. The
oscillations can be keyed "on" and "off" using the reset controls (pin 6 or 8)
The duration of the timing period, T, during which the
output logic level is at a "high" state is given by the
equation:
T = 1.1 RAe
This time delay varies linearly with the choice or RA
and as shown by the timing curves of Figure 5.
e
~
E
"
~
i"
>
..J
H ._-
~
0:
~~-~ 1
-~
O~l
03
0~.~.....J.....J-L-~'0~.....J-L-~"
04
Vs. SUI'Pl '( VOL T Al;l
Vrl,,,,,,,' MINIMUM TRIGG£:R VOL TA(;i()( Vee VIII')
\Vltc~
1("
20
~o
!.IO
100
ISOUIiCf \PllAI
Figure 7. Supply Current (Both Timer
Sections)
Figure 6. Trigger Pulse Width
-----. -
,
OL-_~~~.....J_--I...--I...~_~
Figure B. High Output Voltage
,--,--r-n--,--.,--r-·rr---.
1 (I
~
~
~
~
>
0
~
~
~
0 1
(J
01
--:-.l.-.J.-+---:,:-0 -:f:'O~~5':-0----,,'100
-~..I-...'--I...-,l---.....J.....J--L",J,,--l1{lO
0.0''-,
1...,
'SlJ'.JK· 1mAI
I DIS
I --1
1
I
j
1010
!::~~\!j: Lt:
~
~
o~
1010 . - .
0995 0990 _
\
-
I
--
I
-+++11--t:·rL~i
!
10
15
Figure 12. Delay Time VS. Supply
Voltage
'00. ---
'000 __
;>:
~
J J_. ----t.-
Vs. SUPPl v VOL lAGE IVtlc!
'"
:
~
._- -_..
--- --- - -
_
Figure 11. Low Output Voltage
Vec = 15 Vdc
...__ .
f---- -..- t---f-.- -._+---t---
~~t--
__ 1_
r-t-r-
09951---+--11---+--+-+--+-- I---
o
o· 0 '90 I---
098. L---L--l'--..L-L_.L...L--l--l
o
I SINK - ImAI
Figure 10. Low Output Voltage
Vce = 10 Vdc
1 01b .---r---r-;--,--..----,---,--.
Figure 9. Low Output Voltage
Vec = 5.0 Vdc
20
f--- -
---
o B8~ .,,75,......,5'-::0---J.2~5--"0-''''''''--''"'.0"""''''~5-'-"00---"125
TA _AMBIENT TEMPERATURE ( C,
Figure 13. Delay Time VS. Temperature
1-162
04
VT1mtn ). MINIMUM TRIGGER VOL TAGE
(X Vee
Vl1rl
Figure 14. Propagation Delay VS.
Trigger Voltage
XR·2556
The charge time (output high) is given by:
t1 = 0.695 (RA
To obtain the maximum duty cycle, RA must be as small
as possible; but it must also be large enough to limit the
discharge current (pin 5 current) within the maximum
rating of the discharge transistor (200 mA).
+ RS)C
The discharge time (output low) by:
DESCRIPTION OF CIRCUIT CONTROLS
t2 = 0.695 (RS)C
OUTPUT (PINS 1 or 13)
Thus the total period is given by:
T
= t1 +
t2
= 0.695 (RA +
The output logic level is normally in a "low" state, and
goes "high" during the timing cycle. Each output of the
XR-2556 is a "totem pole" type capable of sinking or
sourcing 200 mA of load current (see Figure 18).
2RS)C
The frequency of oscillation is then:
f =
.1.
1.44
=
T
(RA
100
and
+ 2RS)C
may be easily found as shown in Figure 17.
The duty cycle, D, is given by:
RS
D = ----'=--RA + 2RS
. - - - -__- _ - 0 0
l.I1.J
5
OUTPUT
1/2
XR-2556
RB
0.001 L...-~L--~:---~--:-~-~:;-"'""":l~OOK
0_1
1.0
10
100
f, FREE-RUNNING FREOUENCY (Hz)
f~p~~ROLo-_~4~
f.
1.46
(R A + 2R B)C
Figure 17_ Free Running Frequency as a Function of
External Timing Components
7
RB
DUTY CYCLE· RA + 2RB
Figure 15. Astable (Free-Running) Circuit
Figure 18, Circuit Schematic-1/2 of XR-2256
TRIGGER (PINS 2 OR 12)
The timing cycle is initiated by lowering the dc level at
the trigger terminal below 113 Vee. Once triggered, the
circuit is immune to additional triggering until the timing
cycle is completed.
THRESHOLD (PINS 3 or 11)
The timing cycle is completed when the voltage level at
the trigger terminal reaches 2/3 VCC. At this point,
Comparator #2 of Figure 2 changes state, resets the internal flip-flop, and initiates the discharge cycle.
Figure 16. Astable Waveforms
Top: Output Waveform
Bottom: Waveform Across Timing Capacitor
1-163
XR·2556
2.0,..---..,.---,----r----,r-----r--.,
rately in the monostable mode to produce respective
time delays of T 1 and T2, where:
Tl
z
~. 1.51---+--+--+----:1---,'+----1
~
i
V~'~_"~
____
1.0f----
~ 0.5
/
//
o
_
_ L_ _
~
2V
__
4V
i
i
__
6V
I
~
__
~
= 1.1
R2C2
In this application, the output of one timer section
(Timer 1) is capacitively coupled to the trigger terminal
of the second, as shown in Figure 21. When Timer 1 is
triggered at pin 2, its output at pin 1 goes "high" for a
time duration T1 = 1.1 R1Cl. At the end of this timing
cycle, pin 1 goes "low" and triggers Timer 2 through
the capacitive coupling, CC, between pins 1 and 12.
Then, the output at pin 13 goes "high" for a time duration T2 = 1.1 R2C2. In this manner, the unit behaves as
a "delayed one-shot" where the output of Timer 2 is
delayed from the initial trigger at pin 2 by a time delay
of Tl.
/
/
~
1.1 R1Cl and T2
SEQUENTIAL TIMING (DELAYED ONE-SHOT)
1----+---+-.;"--+---,.---- r - - -
O~
=
__
~
v'
SV
10V
12V
MODULATION VOLTAGE AT CONTROL TERMINAL
(PINS 4 OR 101
Figure 19. Normalized Tims Delay vs. Modulation Voltage
CONTROL OR FM (PINS 4 OR 10)
The timing cycle or the frequency of oscillation can be
controlled or modulated by applying a dc control voltage to pin 4 or 10. This terminal is internally biased at
2./3 VCC. The control signal for frequency modulation or
pulse-width modulation is applied to this terminal. Figure 19 shows the variation of the timing period, T, as a
function of dc voltage at the control terminal. When not
in use, the control terminals should be ac grounded
through 0.01 j'F decoupling capacitors.
"
Figure 20. Generation of Two Independent Time Delays
.---------r-C>v·
DISCHARGE (PINS 5 OR 9)
R,
C,
This terminal corresponds to the collector of the discharge transistor, To, of Figure 2. During the charging
cycle, this terminal behaves as an open-circuit; during
discharge, it becomes a low impedance path to ground.
~
11
RL
v'
RESET (PINS 6 OR 8)
OUTPUT ::2
1J
The timing cycle can be interrupted by grounding the
reset terminal. When the reset signal is applied, the
output goes "low" and remains in .that state while the
rest voltage is applied. When the reset signal is removed, the output remains "low" until re-triggered.
When not used, the reset terminals should be connected to VCC in order to avoid any possibility of false triggering. When the timing circuits are operated in the
astable mode, the reset terminals can be used for "on"
and "off" keying of the oscillations. (See Figure 22).
-l--IL
TRIGGER
001,..F
~"+ -I "
O.Ol"F
T 1'" 1.1 R,e,
30K
v'
T2 "" 1.1 R 2C2
0OOl .. F
Cc
Figure 21. Sequential Timing
KEYED OSCILLATOR
One of the timer sections of the XR-2556 can be operated in its free-running mode, and the other timer section
can be used to key it "on" and "off". A recommended
circuit connection is shown in Figure 22. Timer 2 is
used as the oscillator section, and its frequency is set
by the resistors RA, RB and the capacitor C2. Timer 1 is
operated as a monostable circuit, and its output is connected to the reset terminal (pin 8) of Timer 2.
APPLICATIONS INFORMATION
INDEPENDENT TIME DELAYS
Each timer section of the XR-2556 can operate as an independent timer to generate a time delay, T, set by the
respective external timing components. Figure 20 is a
circuit connection where each section is used sepa1-164
XR·2556
When the circuit is at rest, the logic level at the output
of Timer 1 is "low"; and the oscillations of Timer 2 are
inhibited. Upon application of a trigger signal to Timer
1, the logic level at pin 1 goes "high" and the oscillator
section (Timer 2) is keyed "on". Thus, the output of
Timer 2 appears as a tone burst whose frequency is set
by RA , RB and C2, and whose duration is set by R1 and
C1 of Figure 22.
FREQUENCY DIVIDER
If the frequency of the input is known, each timer section of the XR-2556 can be used as a frequency divider
by adjusting the length of its timing cycle. If the timing
interval T 1 (= 1.1 R1C1) is larger than the period of the
input pulse trigger, then only those input pulses which
are spaced more than 1.1 R1C1 will actually trigger the
circuit.
Figure 23. Frequency Divider Waveforms
Top: Input Pulse Train (f = 5 kHz)
Middle: Waveforms Across Timing Capacitor
Bottom: Output Waveform (f = 1 kHz)
RS
TIMER
TIMER
#1
#2
C2
11
~
12
FREQUENCY DIVIDER AND PULSE SHAPER
Frequency division can be performed by 1/2 of the
XR-2556. The remaining timer section can be used as a
"pulse-shaper" to adjust the duty cycle of the output
waveform. As seen in Figure 24, Timer 1 is used as the
frequency divider section and Timer 2 is used as the
pulse-shaper.
v·
RL
13
1f
TRIGGER
7
0.01 j.lF
10
OUTPUT
8
v·
O.OlIlF
v·
20K
Figura 22. Keyed Oscillator
The output frequency is equal to (1/N) times the input
frequency. The division factor N is in the range:
( l_
Tp
INPUT
1) < N< l
'.
Tp
'-'siN
where Tp is the period of the input pulse signal.
~O-~~~--------~
Figure 23 shows the circuit waveforms for divide-by-five
operation for one of the timer sections of the XR-2556.
In this case, the timing period of the circuit is set to be
approximately 4.5 times the period of the input pulse.
Figure 24. Frequency Divider and Pulse-Shaper
The output of Timer 1 (pin 1) triggers Timer 2, which
produces an output pulse whose frequency is the same
as the output frequency of Timer 1, and whose duty cycle is controlled by the timing resistor and capacitor of
Timer 2. The duty cycle of the output of Timer 2 (pin 13)
can be adjusted from 1 % to 99 % by varying the value
of R2.
Since the two timer sections of the XR-2556 are electrically independent, each can be used as a frequency divider. Thus, if the trigger terminals of both timer sections are connected to a common input, the XR-2556
can produce two independent outputs at frequencies f1
and f2:
Figure 25 shows the circuit waveforms in this application. The top waveform is the input signal of frequency
fs applied to the trigger input (pin 2) of Timer 1. The middle waveform is the output of Timer 1 for divide-by-three
operation; and the bottom waveform is the pulseshaped output obtained from Timer 2 (pin 13).
where N1 and N2 are the division factors for respective
timer sections, set by external resistors and capacitors
at pins (3, 5) and (9, 11).
1-165
XR·2556
Frequency =
(RA
Duty Cycle =
1.44
2RB)Cl
+
(1.6) R2C2
=-,---'
--::::.....::.-:(RA
+
2RBC1)
OSCILLATOR WITH SYNCHRONIZED OUTPUTS
The circuit of Figure 26 can also be used as an oscillator with synchronized multiple frequency outputs.
Timer 1 generates an output at frequency fl at pin 1, a$
set by resistor RA, RB, and Cl. Timer 2 is used as a frequency divider by setting its timing cycle, T2, to be larger than the period of Timer 1 (see section on frequency
division). The resulting output of Timer 2 (pin 13) is at
frequency f2 given as:
f2 = fllN
Figure 25. Frequency DIvider and Pulse-Shaper Waveforms
Top: Input Signal (Is = 9 kHz)
Middle: Output at Pin 1 lor Divide-by-3
Bottom: Variable Duty Cycle Output at Pin 13
where N is the divider ratio set by the external R-C networks as described by Figures 23 and 24.
PULSE-WIDTH MODULATION
For pulse-width modulation, one-half of the XR-2556 is
connected as shown in Figure 27. The circuit operates
in its monostable mode and is triggered with a continuous pulse train. Output pulses are generated at the
same rate as the input pulse train, except the output
pulse-width is determined by the timing components Rl
and Cl.
v·
OUTPUT
PWM
OUTPUT.i
FREQUENCY· iRA
20K
~o-~~~----------~
~::~)C1
1/2
XR·2556
(1.8) RzC2
DUTY CYCLE - (R A + 2Re)C,
CLOCK INPUT
0--<:"::--1
MOOULATION
INPUT
Figure 26. Fixed Frequency Oscillator With Variable Duty
Cycle
Figure 27. Pulse-Width Modulation
FIXED-FREQUENCY, VARIABLE DUTY CYCLE OSCILLATOR
If Timer 1 is operated in its astable mode and Timer 2 is
operated in its monostable mode, as shown in Figure
26, then an oscillator with fixed frequency and variable
duty cycle results.
In this mode of operation, the duration of the timing cycle (i.e .• the output pUlse-width) can be modulated by
applying a modulation input to the control voltage terminals (pins 4 or 10). The control characteristics associated with the modulation terminals are depicted in Figure 19. Figure 28 shows the actual circuit waveforms
generated in this manner.
Timer 1 generates a basic periodic waveform that is
then used to trigger Timer 2. If the time delay, T2, of
Timer 2 is chosen to be less than the period of oscillations of Timer 1, then the output at pin 13 has the same
frequency as Timer 1. but has its duty cycle determined
by the timing cycle of Timer 2. The output duty cycle
can be adjusted over a wide range (from 1 % to 99%)
by adjusting R2.
When using the XR-2556 for pulse-width modulation. an
external clock signal is not necessary. since one section can be operated in its astable mode (see Figure 15)
and serve as the clock generator. Figure 29 is the recommended connection for such an application. In this
case, Timer 2 is used as the clock generator, and Timer
1 is used as the pUlse-width modulator section.
The frequency and the duty cycle of the output waveform are given as:
1-166
XR·2556
a
PULSE-POSITION MODULATION
b
When a timer section of the XR-2556 is operated in its
astable mode (see Figure 15), the period of the output
pulse train can be varied by applying a modulation voltage to the corresponding modulation control terminal.
In this manner, the repetition rate of the output pulse
train can be varied, resulting in a pulse-position modulated output. Typical transfer characteristics between
the timing cycle and the modulation voltage are given in
Figure 19.
c
LOGIC "AND" AND "OR" CONNECTION OF OUTPUTS
The individual outputs (pins 1 and 13) of the XR-2556
can be interconnected as shown in Figure 30 to perform logic "or" and "and" functions. Since the output
of each timer section is a high-current "totem-pole"
type, external diodes are needed to avoid current flow
from one output into the other.
d
Figure 28. Pulse-Width Modulation Waveforms
a) Clock Input at Pin 2
b) Modulation Input at Pin 4
c) Capacitor Voltage at Pin 3
d) Pulse-Width Modulated Output at Pin 1
Referring to Figure 30(a), the output logic level "P"
would read "high" when either one of the outputs at
pins 1 or 13 is "high." For Figure 30(b), the output will
read "high" only when both outputs at pins 1 and 13 are
"high".
y.
",
"i
.,
TIMER
y.
C,
PWM
OUTPUT.!.
TIMER
'2
#2
11
~
C2
I-:l
0.001
MODULATION
INPUT
.F
~-------+~~-oy.
20K
IA)
Figure 29. Pulse-Width Modulation With Internal Clock
Figure 30. Logic "OR" and "AND"
One section of XR-2556
EQUIVALENT SCHEMATIC DIAGRAM
1-167
IB)
XR·2240
Programmable Timer/Counter
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-2240 Programmable Timer/Counter is a monolithic controller capable of producing ultra-long time delays without sacrificing accuracy. In most applications,
it provides a direct replacement for mechanical or electromechanical timing devices and generates programmable time delays from micro-seconds up to five days.
Two timing circuits can be cascaded to generate time
delays up to three years.
As shown in Figure 1, the circuit is comprised of an
internal time-base oscillator, a programmable 8-bit
counter and a control flip-flop. The time delay is set by
an external R-C network and can be programmed to any
value from 1 RC to 255 RC.
In astable operation, the circuit can generate 256 separate frequencies or pulse-patterns from a single RC setting and can be syncronized with external clock signals. Both the control inputs and the outputs are compatible with TIL and DTL logic levels.
ORDERING INFORMATION
FEATURES
Timing from micro-seconds to days
Programmable delays: 1RC to 255 RC
Wide supply range; 4V to 15V
TIL and DTL compatible outputs
High accuracy: 0.5%
External Sync and Modulation Capability
Excellent Supply Rejection: 0.2%N
Operating Temperature
-55°C to + 125°C
O°C to + 70°C
O°C to + 70°C
O°C to + 70°C
O°C to +70°C
The XR-2240 is a combination timer/counter capable of
generating accurate timing intervals ranging from microseconds through several days. The time base works
as an astable multivibrator with a period equal to RC.
The eight bit counter can divide the time base output by
any integer value from 1 to 255. The wide supply voltage range of 4.5 to 15 V, TIL and DTL logic compatibility, and 0.5% accuracy allow wide applicability. The
counter may operate independently of the time base.
Counter outputs are open collector and may be wireOR connected.
Frequency Synthesis
Pulse Counting/Summing
AID Conversion
Digital Sample and Hold
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Power DiSSipation
Ceramic Package
Derate above + 25°C
Plastic Package
Derate above + 25°C
Operating Temperature
XR-2240M
XR-2240C
Storage Temperature
Package
Ceramic
Ceramic
Ceramic
Plastic
Plastic
SYSTEM DESCRIPTION
APPLICATIONS
Precision Timing
Long Delay Generation
Sequential Timing
Binary Pattern Generation
Part Number
XR-2240M
XR-2240N
XR-2240CN
XR-2240P
XR-2240CP
18V
The circuit is triggered or reset with positive going
pulses. By connecting the reset pin (Pin 10) to one of
the counter outputs, the time base will halt at timeout.
If none of the outputs are connected to the reset, the
circuit will continue to operate in the astable mode. Activating the trigger terminal (Pin 11) while the timebase
is stopped will set all counter outputs to the low state
and"start the timebase.
750mW
6 mw/oC
625 mW
5 mW/oC
- 55°C to + 125°C
O°C to + 70°C
- 65°C to + 150°C
1-168
XR·2240
ELECTRICAL CHARACTERISTICS
Test Conditions: See Figure 2, V +
5V, TA
=
25°C, R
XR-2240
PARAMETERS
MIN
GENERAL CHARACTERISTICS
Supply Voltage
TYP
4
Supply Current
Total Circuit
3.5
12
1
Counter Only
Regulator Output, VR
4.1
6.0
4.4
6.3
100
0.5
150
80
0.05
130
TIME BASE SECTION
Timing Accuracy·
Temperature Drift
= 10 kO,
C
= 0.1 /LF, unless otherwise noted.
XR-2240C
MAX
MIN
15
4
6
16
6.6
TYP
4
13
1.5
3.9
5.8
4.4
6.3
MAX
UNIT
15
V
7
18
rnA
rnA
rnA
V
V
6.8
CONDITIONS
For V+
Pin 16
V+
V+
< 4.5V,
Short Pin 15 to
= 5V, VTR = 0, VRS = 5V
= 15V, VTR = 0, VRS = 5V
See Figure 3
Measured at Pin 15, V+
= 15V, See Figure 4
See Figure 2
Supply Drift
Max. Frequency
2.0
300
0.5
200
80
0.08
130
0.2
5
%
ppm/'C
ppm/'C
%N
kHz
0.3
Modulation Voltage
Level
Recommended Range
of Timing Components
Timing Resistor, R
Timing Capacitor, C
3.50
10.5
Input:
Impedance
Threshold
Output:
Rise Time
Fall Time
Sink Current
Leakage Current
R
=
1 kG, C
= 0.007 "F
4.0
2.80
3.50
10.5
4.20
V
V
V+ 5V
V+ = 15V
See Figure 8
0.001
0.007
10
1000
TRIGGER/RESET CONTROLS
Trigger
Trigger Threshold
Trigger Current
Impedance
Response Time'·
Reset
Reset Threshold
Reset Current
Impedance
Response Time"
COUNTER SECTION
Max. lOggle Rate
VRS = 0, VTR = 5V
V+ = 5V
O'C s T s 75'C
V+ = 15V
V + 2!: 8 Volts, See Figure 11
Measured at Pin 12
3.00
10
1000
MG
1.4
10
25
1
2.0
V
1.4
10
25
0.8
2.0
0.001
0.01
"F
Measures at Pin 11, VRS
1.4
8
25
1
2.0
1.4
8
25
0.8
2.0
0.8
1.5
1.0
20
1.4
1.0
180
180
5
0.01
3
2
8
VRS
= 0, VTR = 2V
"A
kG
/Lsec.
VTR
= 0, VRS = 2V
1.5
MHz
VRS
20
1.4
kG
180
180
4
0.01
nsec.
nsec.
rnA
~
kG
"sec.
V
See Figure 4, V+ = 5V
= 0, VTR = 5V
Measured at Pin 14
V
15
"A
Measured at Pins 1 thru 8
RL = 3k, CL = 10 pF
VOL s O.4V
VOH = 15V
'Timing error solely introduced by XR·2240, measured as % of ideal time·base period of T = 1.00 RC.
"Propagation delay from application of trigger (or reset) input to corresponding state change in counter output at pin 1.
......
....
..
..
,.
V·
,
,
,
,
,
,
,
e
= 5V
V+
"'-'-4V
v'
A
~
S
>
~
c
~
iii
Figure 2. Generalized Test Circuit
iVA.
t VTA
Figure 3. Test Circuit for Low-Power
Operation (Time-Base Powered Down)
1-169
Figure 4. Test Circuit for Counter
Section
=0
XR·2240
PRINCIPLES OF OPERATION
PROGRAMMING CAPABILITY
The timing cycle for the XR-2240 is initiated by applying
a positive-going trigger pulse to pin 11. The trigger input actuates the time-base oscillator, enables the
counter section, and sets all the counter outputs to
"low" state. The time-base oscillator generates timing
pulses with its period, T, equal to 1 RG. These clock
pulses are counted by the binary counter section. The
timing cycle is completed when a positive-going reset
pulse is applied to pin 10.
The binary counter outputs (pins 1 through 8) are opencollector type stages and can be shorted together to a
common pull-up resistor to form a "wired-or" connection. The combined output will be "low" as long as any
one of the outputs is low. In this manner, the time delays associated with each counter output can be
summed by simply shorting them together to a common output bus as shown in Figure 6. For example, if
only pin 6 is connected to the output and the rest left
open, the total duration of the timing cycle, To, would
be 32T Similarly, if pins 1, 5, and 6 were shorted to the
output bus, the total time delay would be To =
(1 + 16 + 32) T = 49T In this manner, by proper choice
of counter terminals connected to the output bus, one
can program the timing cycle to be: 1T :s; To :s; 255T,
where T = RG.
Figure 5 gives the timing sequence of output waveforms at various circuit terminals, subsequent to a trigger input. When the circuit is at reset state, both the
time-base and the counter sections are disabled and all
the counter outputs are at "high" state.
In most timing applications, one or more of the counter
outputs are connected back to the reset terminal, as
shown in Figure 6, with S1 closed. In this manner, the
circuit will start timing when a trigger is applied and will
automatically reset itself to complete the timing cycle
when a programmed count is completed. If none of the
counter outputs are connected back to the reset terminal (switch S1 open), the circuit would operate in its
ilstable or free-running mode, subsequent to a trigger
input.
TRIGGER AND RESET CONDITIONS
When power is applied to the XR-2240 with no trigger or
reset inputs, the circuit reverts to "reset" state. Once
triggered, the circuit is immune to additional trigger inputs, until the timing cycle is completed or a reset input
is applied. If both the reset and the trigger controls are
activated simultaneously trigger overrides reset.
\11
1-.lJ.---------,
",.,"
TlUaGER
IN,ut
UflllllUIJJlllllWUIL
DESCRIPTION OF CIRCUIT CONTROLS
TlMf8as[
ounUT
"IN 141
COUNTER OUTPUTS (PINS 1 THROUGH 8)
tmnn.nnnnnnnnI
_.
.
_,"".1
COUPftfR
OUTPUTS
The binary counter outputs are buffered "opencollector" type stages, as shown in Figure 15. Each
output is capable of sinking "" 5 mA of load current. At
reset condition, all the counter outputs are at high or
non-conducting state. Subsequent to a trigger input,
the outputs change state in accordance with the timing
diagram of Figure 5.
D...O.J:lllilll_, ".,
tlL...------J'-------'L...-----II_, "••
h_ _ _
-J.
_,'INS
The counter outputs can be used individually, or can be
connected together in a "wired-or" configuration, as
described in the Programming section.
Figure 5. Timing Diagram of Output Waveforms
RESET AND TRIGGER INPUTS (PINS 10 AND 11)
v·
The circuit is reset or triggered with positive-going control pulses applied to pins 10 and 11. The threshold lev·
el for these controls is approximately two diode drops
(",,1.4V) above ground.
Minimum pulse widths for reset and trigger inputs are
shown in Figure 10. Once triggered, the circuit is immune to additional trigger inputs until the end of the
timing cycle.
Jl
JL
TRIGGER
RESET
MODULATION AND SYNC INPUT (PIN 12)
The period T of the time·base oscillator can be modulated by applying a dc voltage to this terminal (see Figure 13). The time-base oscillator can be synchronized
to an external clock by applying a sync pulse to pin 12,
as shown in Figure 16. Recommended sync pulse
widths and amplitudes are also given in the figure.
n-i .......w .......-O.:.:"'-j XA·2240
SYNC
5.1K
INPUT
Figure 16. Operation with External Sync Signal.
(a) Circuit for Sync Input
(b) Recommended Sync Waveform
Flgura 15. Simplified Circuit Diagram of XR·2240
1-171
.-~
.. ,.
XR·2240
HARMONIC SYNCHRONIZATION
REGULATOR OUTPUT (PIN 15)
Time-base can be synchronized with integer multiples
or harmonics of input sync frequency, by setting the
time-base period, T, to be an integer multiple of the
sync pulse period, T s. This can be done by choosing
the timing components Rand C at pin 13 such that:
This terminal can serve as a V + supply to additional
XR-2240 circuits when several timer circuits are cascaded (See Figure 20), to minimize power dissipation.
For circuit operation with external clock, pin 15 can be
used as the V+ terminal to power-down the internal
time-base and reduce power dissipation. The output
current shall not exceed 10 mA.
T
= RC = (Ts/m) where
m is an integer, 1
s m s 10.
When the internal time-base is used with V+
pin 15 should be shorted to pin 16.
Figure 17 gives the typical pull-in range for harmonic
synchronization, for various values of harmonic modulus, m. For m < 10, typical pull-in range is greater than
±4% of time-base frequency.
s
4.5V,
APPLICATIONS INFORMATION
PRECISION TIMING (Monostable Operation)
TIMING TERMINAL (PIN 13)
In preciSion timing applications, the XR-2240 is used in
its monostable or "self-resetting" mode. The generalized circuit connection for this application is shown in
Figure 18.
The time-base period T is determined by the external
R-C network connected to this pin. When the time-base
is triggered, the waveform at pin 13 is an exponential
ramp with a period T = 1.0 RC.
v'
10K
RL
_ , . -_ _~_ _- - , , - -
TIME·BASE OUTPUT (PIN 14)
y'
Time-Base output is an open-collector type stage, as
shown in Figure 15 and requires a 20 KO pull-up resistor to Pin 15 for proper operation of the circuit. At reset
state, the time-base output is at "high" state. Subsequent to triggering, it produces a negative-going pulse
train with a period T = RC, as shown in the diagram of
Figure 5.
11.
11.
"Eur
TRIGQU
Time-base output is internally connected to the binary
counter section and also serves as the input for the external clock signal when the circuit is operated with an
external time-base.
OUTPUT
~ "LJ"
The counter input triggers on the negative-going edge
of the timing or clock pulses applied to pin 14. The trigger threshold for the counter section is '"' + 1.5 volts.
The counter section can be disabled by clamping the
voltage level at pin 14 to ground.
Note:
Under certain operating conditions such as high supply
voltages (V+ > 7V) and small values of timing capacitor (C < 0.1 JLF) the pulse-width of the time-base output
at pin 14 may be too narrow to trigger the counter section. This can be corrected by connecting a 300 pF capaCitor from pin 14 to ground.
~
-I
The output is normally "high" and goes to "low" subsequent to a trigger input. It stays low for the time duration To and then returns to the high state. The duration
of the timing cycle To is given as:
To = NT = NRC
where T = RC is the time-base period as set by the
choice of timing components at pin 13 (See Figure 9). N
is an integer in the range of:
,1
!
!
1
t1 2
~
,
n Jl
where m is the harmonic number, and N is the pro
grammed counter modulus. For a range of 1 :s; N :s
255, the circuit of Figure 25 can produce 1500 sepa
rate frequencies from a single fixed reference.
TRIGGER
.----_-0 Jl
RESET
51K
O.l,.F
~ REF!RENCE INPUT
tR
v'
Figure 23. Operation with External Clock
FREQUENCY SYNTHESIZER
The programmable counter section of XR-2240 can be
used to generate 255 discrete frequencies from a given
time base setting using the circuit connection of Figure
24. The output of the circuit is a positive pulse train with
a pulse width equal to T, and a period equal to (N + 1) T
where N is the programmed count in the counter.
3OOP~
lOOp'
Figure 25. Frequency SyntheSis by harmonic Locking to
External Reference
1-174
a
XR·2240
One particular application of the circuit of Figure 25 is
generating frequencies which are not harmonically related to a reference input. For example, by choosing
the external R-C to set m = 10 and setting N = 5, one
can obtain a 100 Hz output frequency synchronized to
60 Hz power line frequency.
STAIRCASE GENERATOR
The XR-2240 Timer/Counter can be interconnected
with an external operational amplifier and a precision
resistor ladder to form a staircase generator, as shown
in Figure 26. Under reset condition, the output is low.
When a trigger is applied, the op. amp. output goes to a
high state and generates a negative going staircase of
256 equal steps. The time duration of each step is
equal to the time-base period T. The staircase can be
stopped at any desired level by applying a "disable"
signal to pin 14, through a steering diode, as shown in
Figure 26. The count is stopped when pin 14 is clamped
at a voltage level less than 1.4V.
11
STROBE IN,...,T
Figure 27. DigRal Sample and Hold Circuit
ANALOG-TO·OIGITAL CONVERTER
v'
Figure 28 shows a simple 8-bit AID converter system
using the XR-2240. The operation of the circuit is very
similar to that described in connection with the digital
sample/hold system of Figure 15. In the case of AID
conversion, the digital output is obtained in parallel format from the binary counter outputs, with the output at
pin 8 corresponding to the most significant bit (MS8).
The re-cycle time of the AID converter is '" 6 msec.
ENABLE
-F
o--f+vcc
The time base oscillator is a simple exponential ramp
type timer circuit. The timing components, Rand e, are
external to the chip. The operation of such an oscillator
can be described as follows: when the circuit is at rest
the flip-flop is latched in its reset state, the discharge
transistor is "off", and the external capacitor, e, is fully
charged to a voltage approximately equal to Vee.
When the circuit is triggered, the flip-flop is unlatched
and set, which causes the discharge transistor to turn
"on" and discharge e rapidly. When the voltage across
e discharges to the voltage level Vth _ , the upper comparator changes state, resets the flip-flop and turns the
discharge transistor "off". Then, e charges toward
Vee with a time constant set by the external Rand e.
When the voltage across it reaches the upper threshold, Vth + ' the comparator changes state, sets the flipflop again, and discharges e back to the lower threshold level, Vth _. In this manner, the circuit continues to
oscillate with the voltage level across e exponentially
rising to Vth +, then rapidly decaying to Vth _ and then
repeating this cycle until the timing period ends.
j.To..j
~
OUTPUT
S1
51K
TO = 1024RC
Figure 2. Typical. Operation Diagram
ASTABLE ANO MONOSTABLE MODE
Figure 2 shows the basic connection diagram for
astable and monostable modes. When switch S1 is
open, the circuit is in its astable mode of operation.
Upon the application of a trigger pulse, the time base
oscillator resumes the timing cycles. Until the application of a reset pulse, the circuit will keep on working
while generating a square wave at the last stage output, whose frequency is 1/2048 of the time base oscillator frequency. When switch S1 is closed, the circuit is
in its monostable mode of operation, with the last stage
being connected to the reset input via an external resistor. This way, when a trigger pulse is applied, and the
time base resumes its timing cycle, the last stage output will go low with the first pulse generated by the time
COUNTER SECTION (Pin 8)
The counter consists of eleven stages connected in a
"ripple counter" configuration. The operating injector
currents are set from a bus of 1.2 volts. This current is
supply independent. Pin 8, which is time based o/p, is
also the counter section input.
12L counters are D-type flip-flops with their Q output internally connected to their D input; basically, they form
1-182
XR·2243
base generator, and will stay low for 1024 pulses. With
the arrival of the 1024th pulse, the last output will go to
a high state since it is coupled to the reset input (see
Figure 3). When this stage goes high, the timing cycle
is completed.
(1024)3 RC time delay, and so on. Thus, one can easily
achieve time delays in the range of days, months, or
years, simply by cascading two or three such counter!
timer circuits.
Figure 4 shows the basic connection for cascaded op·
eration. Unit 2's time base is disabled by grounding Pin
7 to ground via 1 kll resistor. The last stage output of
Unit 1 is connected to the input of the counter section
of Unit 2. When the circuit is triggered, Unit 1 will
resume generating a frequency whose period T =
RextCext. The output of Unit 1 will change state every
1024 pulses. Since these pulses are supplied to Unit 2,
the circuit will stop the timing cycle after 1024 pulses
are generated by Unit 1. Therefore, a time delay of
(1024)2 RC is generated.
TRIIc:.~MJ
(PIN I)
'-----------------
TIME IIAlI! -""""I'"T"TT"I"T"I'"T"""""I'"T"TT-nI"T"I"TTT"TT"
o~~~
1111111111111111111111111111
FIAST
STAGE
O~~J
~I- - - - - I
c=~-,
(PIN3)
'--------55;--------'
r-
Figure 3. Timing Diagram of Output Waveforms
SEQUENTIAL TIMING APPLICATIONS
CASCADED MDDE
Figure 5 shows the basic connections for sequential
timing applications. In this mode of operation, Unit 2's
trigger input is connected to Unit 1's last output, while
each unit's reset input is connected to their last output
via external resistors. This way, Unit 1 will generate a
time delay 1024 R1C1 upon the application of a trigger
pulse. Once 1024 R1C1 seconds have elapsed, Unit 2
will be triggered, generating in its turn a delay equal to
1024 R2C2 seconds; therefore, resulting in an overall
time delay of 1024 R1C1 + 1024 R2C2 .
The cascaded mode of operation allows the generation
of ultra·long time delays. When several XR·2243 cir·
cuits are cascaded, such that their counter sections
are connected in series, the total count available in·
creases geometrically rather than arithmetically. Since
one XR-2243 is capable of generating a total of 1024
RC time delay, where Rand C are the external timing
components, then when two such timers are cascaded,
they will produce (1024)2 RC and three will produce
•vcco-_....,..._ _ _ _ _ _ _ _ _ _ _- . . , _ - - - - - - - . ,
0--..+---o REIIT
'------------f_+---<>1lI10GER
Figure 4. Cascaded Operation of Two XR·2243 Timer Circuits
·ycc-t---------~---.--------__,
'.
"
l ! } - + - - - O TRIGGER
Figure 5. Sequential Timing Using XR·2243 Timer Circuits
1·183
-I"1..
Function Generators
Fundamentals of Monolithic Waveform
Generation and Shaping
Waveform or function generators find a wide range of
applications in communications and telemetry equipment, as well as for testing and calibration in the laboratory. In most of these applications, commerciallyavailable monolithic IC oscillators and function generators provide the system designer with a low-cost
alternative to conventional, non~integrated units costing
several hundred dollars or more.
Co goes off. Except for a half cycle delay, output VB(t) is
the same as VA(t).
v+
.J1J1.
The fundamental techniques of waveform generation
and shaping are well suited to monolithic IC technology.
In fact, monolithic integrated circuits offer some inherent advantages to the circuit designer, such as the
availability of a large number of active devices and
close matching and thermal tracking of component values. By making efficient use of the capabilities of integrated components and the batch-processing advantages of monolithic circuits, it is now possible to design
integrated waveform generator circuits that can provide
a performance comparable to that of complex discrete
generators, at a very small fraction of the cost. This article provides a brief review of the fundamental principles of monolithic waveform generation and waveshaping methods.
Basics of
SYNC OUTPUT
rv
OR
AM INPUT
OUT PUT
IV\
IOPTIONAL)
DC LEVEL
CONTROL
SEI.ECT
v-
Figure 1. Basically, a waveform generator consists of lour
sections. Each section can be built readily in
monolithic form with established Ie technology.
02
01
Ie Waveform Generation
Essentially a waveform generator is a stable oscillator
circuit that outputs well-defined waveforms; and, these
can be externally modulated or swept over a frequency
range. A waveform generator usually conSists of four
sections: (1) an oscillator to generate the basic periodic
waveform; (2) a wave-shaper; (3) an optional modulator
section to provide AM capability, and (4) an output
buffer amplifier to provide the necessary load drive.
v A(I) O - + - - - - - - - i f - - - - - - - + - O vB(t)
Figure 1 shows a simplified generator using the four
functional blocks. Each block can be built readily in
monolithic form with established linear IC technology.
Hence fabrication of all four blocks on a Single monolithic chip has evolved as a natural extension of earlier
circuits.
v
o
(Ill?U n U 1'1
The oscillator, usually a relaxation type, can generate
linear, triangle or ramp waveforms. The usual technique
involves constant-current charging and discharging of
an external timing capacitor. Figure 2 shows a typical,
though simplified, example: an emitter-coupled multivibrator circuit, which can generate a square wave as
well as a triangle or a linear ramp output.
The circuit's operation is as follows: At any given time,
either Q1 and 01 or Q2 and 02 are conducting such
that capaCitor Co is alternately charged and discharged
by constant-current 11. The output across 01 and 02
corresponds to a symmetrical square wave, having a
pk-pk amplitude of 2VBE, or twice the transistor baseemitter voltage drop. Output VA, constant when Q1 is
on, becomes a linear ramp with a slope equal to -111
Figure 2. A simple oscillator circuit can be used to generate
square, ramp and triangle waveforms.
1-184
acteristics. A simpler, and more practical, sine shaper
for monolithic circuits employs the "gradual cutoff"
characteristics of a basic differential gain stage, as in
Figure 3.
Both linear ramp waveforms have pk-pk amplitudes of
2VBE. Their frequency of oscillation, fo, can be determined from the formula
11
fo = - - - .
4VBEC o
Reduction of the emitter = degeneration resistance, RE,
allows either transistor 03 or 04 to be brought near
their cutoff point when the input triangle waveform
reaches its peaks. For the proper choice of the input
amplitude and bias-current levels, the transfer characteristics at the peaks of the input triangle waveform become logarithmic rather than linear. Thus, the peaks of
the triangle become rounded, and the output appears
as a low distortion sine wave.
And fo can be controlled by variation of chargingcurrent 11 via control voltage VC. A subtraction of one
output ramp voltage from the other, by use of a simple
differential amplifier, obtains the linear triangular waveform.
Symmetry of triangle and square-wave outputs may be
adjusted by replacement of one of the two current
sources in Figure 2 by 12, where 12 ,f. 11. Then the duty
cycle of the output waveforms becomes the following:
Duty Cycle = 50
Use of this technique permits output harmonics to be
reduced to less than 0.5% with only a single adjustment. The low distortion is possible because the technique relies on component matching rather than their
absolute values. Since monolithic ICs can be designed
readily for close matching, this wave-shaping is ideally
suited to monolithic design.
~ %.
12
The duty cycle of the output may be varied over a wide
range by varying the ratio of the currents 11 and 12.
r------_----Q v+
Wave-Shaping Techniques
t----o SINE WAVE
OUTPUT
The most useful waveform in Signal processing applications is the sine wave. In the design of function generators, sinusoidal output is normally obtained by passing
a triangular wave through a wave shaping circuit. In
most discrete-component generators, wave-shaping involves a diode-resistor or a transistor-resistor ladder
network. Introduction of a finite number of "break
pOints" on the triangle wave changes it to a lower distortion sine wave.
N
rv
TRIANGLE
INPUT
Figure 3. Conversion of triangle to sine wave employs a
differential gain stage, which avoids dependence
on absolute values of components.
Although this method can also be adapted to monolithic
circuits, it is not as practical because it requires extremely tight control of resistor values and diode char-
1-185
Choosing The Right IC Oscillator
FM Generation
At the onset of his design, the user of monolithic oscillator products is faced with the key question of choosing the oscillator or the function generator best suited
to his application. The broad line of function generator
products offered by Exar covers a wide range of applications. It is often difficult to determine at a glance the
best circuit for a given application. The purpose of this
section is to review some of the key performance requirements, from an applications point of view, and
help answer the question. "What is the best IC oscillator for the job?"
Essentially all of Exar's IC oscillator circuits can be
used for generating frequency-modulated waveforms.
For small frequency deviations (Le., ± 5 % or less)
about the center frequency, all of these oscillators have
FM nonlinearity of 0.1 % or less. However, if wider FM
deviations are required the XR-2209, XR-2207 and the
XR-2206 offer the best FM linearity.
FSK Generation
Sine Wave Generation
Frequency-shift keying (FSK) is widely used in digital
communications, particularly in data-interface or
acoustical-coupler type MODEM systems. In monolithic IC oscillators, FSK capability is obtained by using a
current-controlled oscillator and keying its control current between two or more programmed levels which
are set by external resistors. This results in output
waveforms which are phase-continuous during the frequency transitions between the "mark" and "space"
frequencies.
In evaluating the output characteristics of sinusoidallC
OSCillators, total harmonic distortion (THO) of the output waveform is usually the key performance criteria.
In a number of vOice-grade telecommUnication or laboratory applications, sine wave distortion of 2% to 3%
may be tolerable. However, for audio-quality Signals,
distortion level of 1 % or less is required. Furthermore,
it is desirable that the output distortion should be relatively independent of the output amplitude, frequency
or temperature changes; and that the distortion level
be minimized with a minimum amount of external adjustments.
The XR-2207 can produce four discrete frequencies,
set by one external capaCitor and four setting resistors.
Frequency keying between these four frequencies is
achieved by a two-bit binary logic input. The circuit produces both triangle and square wave outputs. The
XR-2206 produces two discrete frequencies, f1 and f2'
and has a one-bit keying logic input. The key advantage
of XR-2206 over the XR-2207 in FSK MODEM design is
the availability of a sinusoidal output waveform.
Exar manufactures three separate families of IC oscillators which provide sinusoidal output waveforms.
These are the XR-205, XR-2206 and the XR-8038. All of
these circuits require external trimming to minimize the
output distortion. In the case of XR-205, the untrimmed
distortion is about 5 %; in the case of the XR-2206 and
the XR-8038, untrimmed distortion is typically less than
2%, and can be reduced to 0.5% with additional trimming.
Exar has compiled a comprehensive application note
describing the use of both of these IC products in the
design of FSK MODEM systems. This application note
entitled "Stable FSK MODEMs Featuring the XR-2207,
XR-2206 and the XR-2211" is also included in this Data
Book.
For low frequency sine wave generation (below 100
kHz), the XR-2206 and the XR-8038 are the recommended circuits. The XR-8038 has a fixed output level,
whereas the XR-2206 offers separate output dc level
and amplitude adjustment capability.
Laboratory Function Generator
AM Generation
One of the main applications for oscillators is for laboratory or test instrumentation or calibration where a variety of different output waveforms are required. Most
such applications require both AM/FM modulation capability, linear frequency sweep and sinusoidal output.
The circuit which fits this application best is the XR2206 since it has all the fundamental features of a complete function generator system costing upwards of
several hundred dollars.
Linear modulation of output amplitude by means of an
analog control signal is a desirable feature for telemetry and data transmission applications. In monolithic IC
OSCillators, this capability is normally obtained by including a four-quadrant transconductance multiplier on
the IC chip. Both the XR-205 and the XR-2206 circuits
have such a feature included on the chip and can be
used for generating sinusoidal AM signals. They can
operate both in suppressed-carrier or conventional
double-sideband AM generator mode. For operation
with frequencies below 100 kHz, the XR-2206 has superior performance characteristics over the XR-205.
A comprehensive description of building a self-contained laboratory-quality function generator system using the XR-2206, Application Note AN-14, is included in
this Data Book.
1-186
Phase-Locked Loop Design
Low-Cost General Purpose Oscillator
The current-controlled or voltage-controlled oscillator
(VCO) is one of the essential components of a phaselocked loop (PLL) system. The key requirement for this
application is that the oscillator should have a high degree of frequency stability and linear voltage or
current-to-frequency conversion characteristics. Sinusoidal output, although often useful, is generally not required in this application.
In many digital design applications, one needs a stable,
low-cost oscillator IC to serve as the system clock. For
such applications, the XR-2209 preciSion oscillator is a
logical design choice since it is a simple, low-cost oscillator circuit and offers 20 ppm/DC frequency stability.
The monolithic timer circuits, such as the XR-555, or its
micropower version, the XR-L555, can also be used as
low-cost, general purpose oscillators by operating
them in their free-running, i.e., self-triggering, mode.
Although all of Exar's IC oscillators can be used as a
VCO in designing PLL systems, the XR-2207 or its lowcost and simplified version, the XR-2209, are often the
best suited devices for this application. For additional
information refer to Application Note AN-06, entitled
"Precision PLL System Using the XR-2207 and the XR2208," which is included in this Data Book.
Ultra-LOW Frequency Oscillator
In certain applications such as interval-timing or sequencing, stable, ultra-low frequency oscillators which
can operate at frequencies of 0.01 Hz or lower are required. Among Exar's oscillator circuits, the IC most
suited to such an application is the XR-8038 since it
can operate with a polarized electrolytic capacitor as
its timing component. All other oscillator circuits described in this book require non-polar timing capacitors, and therefore are not as practical as the XR-8038
for ultra-low frequency operation.
Sweep Oscillator
A sweep oscillator is required to have a large linear
sweep range. Among Exar's function generators, the
XR-2207 and the XR-2206 have the widest linear sweep
range (over 1000:1), and are best suited for such an application.
An alternate approach to obtaining stable ultra-low frequency oscillators is to use the XR-2242 counter/timer
as an oscillator in its free-running mode. Such a circuit
generates a square wave output with a frequency of
(1/256 RC) where Rand C are the external timing components.
By using a linear ramp output from the XR-2207 to
sweep the frequency of the XR-2206, one can build a
two-chip sweep oscillator system which has a 2000:1
sweep range and sinusoidal output.
1-187
XR·205
Monolithic Waveform Generator
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTIDN
The XR-205 is a highly versatile, monolithic waveform
generator designed for diverse applications in communication and telemetry equipment, as well as in systems design and testing. It is a self-contained, totally
monolithic signal generator that provides sine, square,
triangle, ramp and sawtooth output waveforms, which
can be both amplitude and frequency modulated.
MODULATOR
OUTPUTS
TIMING
CAPACITOR
MODULATOR
FM, SYNC.,
AND SWEEP
INPUT'
X·INPUTS
The circuit has three separate sections: a voltagecontrolled oscillator (VCO) which generates the basic
P!lriodic waveforms; a balanced modulator which provides amplitude or phase modulation; a buffer amplifier
section which provides a low impedance output with
high current drive capability.
SOUAREWAVE
OUTPUT
MODULATOR
Y·1NPUTS
BUFFER
OUTPUT
WAVEFORM
AOJ
FEATURES
High Frequency Operation
AM and FM Capabilities
Sine, Triangle, Square, Sawtooth, Ramp
and Pulse Waveforms
Wide Supply Range 8 V to 26 V
Split Supply Capability
APPLICATIONS
Waveform Generation
Sinewave
Sawtooth
Triangle
Ramp
Square
Pulse
AM Generation Double Sideband Suppressed Carrier
Crystal-Controlled
FM Generation
Sweep Generation
Tone Burst Generation
Simultaneous AM/FM
Frequency-Shift Keyed (FSK) Signal Generation
Phase-Shift Keyed (PSK) Signal Generation
On-Off Keyed Oscillation
Clock Generation
ORDERING INFORMATION
Package
Operating Temperature
Ceramic
O°C to + 70°C
SYSTEM DESCRIPTION
The XR-205 is a high frequency monolithic function
generator capable of sine, square, triangle, ramp, sawtooth, and pulse waveforms with frequencies ranging to
4 MHz. Operating frequency is determined by a single
capacitor and may be externally swept over a 10:1
range. Duty cycle is variable from 10% to 90%. Amplitude modulation, up to 100%, is accomplished using
the modulator X inputs (Pins 3 and 4). The on board
buffer amplifier features 500 output resistance and 20
mA output capability. The XR-205 operates with either
single or split supplies.
ABSOLUTE MAXIMUM RATINGS
Power Supply
Power Dissipation
Derate above +25°C
Temperature
Storage
Part Number
XR-205
26 Volts
750 mW
6 mW/oC
1-188
XR·205
ELECTRICAL CHARACTERISTICS
Test CondHions: Supply Voltage = 12V (single supply) TA = 2SoC, f· 10 kHz, RL = 3 kll, unless otherwise specified.
LIMITS
PARAMETERS
MIN
TYP
MAX
UNITS
CONDITIONS
26
±13
Vdc
Vdc
See Figure 1
See Figures 2 and 3
10
12
rnA
w/o buffer amp
0.2
300
O.S
600
%N
ppm/DC
IVcc - VEEI > 10V
Sweep input open circuit
I - General Characteristics
Supply Voltage:
Single Supply
Split Supply
8
±S
Supply Current
8
Frequency Stability:
Power Supply
Temperature
Frequency Sweep Range
Output Swing:
Single Ended
Differential
Output Dlff. Offset Voltage
7:1
10:1
2
4
3
6
0.1
Amplitude Control Range
Buffer Amplifier Output
Resistance
Output Current Swing
See Figure 7
0.4
Vpp
Vpp
Vdc
60
dB
SO
ohms
±6
±10
rnA
2
2
4
3
2.S
MHz
Vpp
Measured at pin 1 or 2
Measured across 1 and 2
Measured across 1 and 2
Controlled by Rq (see Figure 1)
RL
= 7S01l
II - Output WavelflTms
Sinusoidal:
Upper Frequency Limit
Peak Output Swing
Distortion (THD)
Triangle:
Peak Swing
Non·Linearity
Asymmetry
2
3
1.S
Vpp
Vpp
%
See Figure 1, S2 and S3 open
pin 10 shorted to pin 15
Vpp
See Figure 1, S2 and S3 open,
pin 10 shorted to pin 12
10 pF connected from pin 11
to ground
Ramp:
Peak·Swlng
Non·Linearity
1
1.4
1
O.S
0.7
q±1
20
20
Pulse Output:
Peak Swing
Rise Time
Fall Time
Duty Cycle Range
2
2
2
Measured at Pin 11
S1, S2 open, S3 closed
f
10 kHz
Vpp
%
2
Squarewave (High Level):
Peak Swing
Duty Cycle Asymmetry
Rise Time
Fall Time
%
4
±1
±1
Sawtooth:
Peak Swing
Non·Linearity
Squarewave (Low Level):
Output Swing
Duty Cycle Asymmetry
Rise Time
Fall Time
4
Measured at Pin 11
S1, S3 closed, S2 open
closed S2 open
3
±1
80
60
%
%
±4
%
ns
ns
Vpp
±4
=
See Figure 1, S2 closed;
S2 and S3 closed
See Figure 3, S2 open
%
ns
ns
10 pF connected from pin 11
to ground
3
3
80
60
Vpp
Vpp
ns
ns
See Figure 3, S2 closed
See Figure 3, S2 closed
20·80
%
Adjustable (see Figu re 6)
%
See Figure 2
for 30% modulation
III - Modulation Characteristics (sine, triangle and squarewave):
Amplitude Modulation:
Double Sideband
Modulation Range
Linearity
Sideband Symmetry
Suppressed Carrier
Carrier Suppression
Frequency Modulation:
Distortion
0·100
0.5
1.0
%
52
dB
f
0.3
%
See Figure 2 (± 10 frequency
deviation)
%
1·189
<
1 MHz
XR·205
DESCRIPTIDN OF CIRCUIT CONTROLS
TEST CIRCUITS
(Refer to functional block diagram)
.--------0 ..n..n..
TIMING CAPACITOR (PINS 14 AND 15)
The oscillator frequency is inversely proportional to the
value of the timing capaCitor, Co, connected between
pins 14 and 15. With the sweep input open circuited, fre·
quecy fo can be approximated as: fo = 400/Co where fo
is in Hz and Co is in microforads. (See Figure 4.)
'K
MODULATOR V-INPUTS (PINS 5 AND 6)
These inputs are normally connected to the oscillator
outputs. For sinewave or trianglewave outputs, they are
dc coupled to pins 14 and 15 (see Figure 1); lor high·
level squarewave or pulse output, ac coupling is used
as shown in Figure 3.
BUFFER OUTPUT
Figure 1. Test Circuit lor Single-Supply Operation
MODULAR X-INPUTS (PINS 3 AND 4)
Modulator output (at pins 1 or 2) is proportional to a dc
voltage applied across these inputs . (see Figure 5).
These inputs can be used for amplitude modulation or,
as an output amplitude control. The phase of the output
voltage is reversed if the polarity of the dc bias across
pins 3 and 4 is reversed; therefore these inputs can be
used for phase·shift keyed (PSI<) modulation.
~~.-J~~~!---~--~~~~~
I-O-~-o.l\..r
-BY
MODULATOR OUTPUTS (PINS 1 AND 2)
All of the high level output waveforms are obtained at
these terminals. The output waveforms appear differen·
tially between pins 1 and 2. The terminals can, there·
fore, be used for either in-phase or out·of·phase outputs. Normally, a 15 KO load resistor should be con·
nected between these terminals to prevent the output
from saturating or clipping at large output voltage
swings.
I-C-r--o I"\../\.,
OR
~~---r---rro-r~
'\IV
LOW LEVEL SQUAREWAVE OUTPUT (PIN 12)
Figure 2. Test Circuit lor Spilt-Supply Operation and AM/FM
Modulation
SWEEPOA
The output at this pin is a symmetrical squarewave with
0.7V amplitude and 20 ns rise time. It can be used di·
rectly as an output waveform, or amplified to a 3 Vpp
signal level using the modulator section of the XR·205
as an amplifier (see Figure 3).
1K
SYNC
INPUT
1,.
SWEEP OR FM INPUT (PIN 13)
The oscillator frequency increases linearly with an increasing negative voltage, Vs , applied to this terminal.
Normally a series resistor, Rs (Rs '" approx. 1 KO) is
connected in series with this terminal to provide current
limiting and linear voltage·to·frequency transfer charac·
teristics. The frequency derivation (for any given modu·
lation level) is inversely proportional to Rs. Typical
sweep characteristics of the circuit are shown in Figure
7. For proper operation of the circuit with Rs = 1 KO,
the sweep voltage, Vs , must be within range: (Vso . 6)
> Vs > (V so + 1) where Vso is the open circuit voltage
at pin 13. The frequency of oscillation can also be syn·
chronized to an external source by applying a sync
"'.
...
OUTPUT
...n.n..
Rq
+_...J
:~~UTUOf ' - -_ _ _ _ _
' - - - - - 0 -A.JL
~~T:~T ,..-yOUTPUT
VEE
I BV,
SQUARE WAVE 51 OPEN
PULSE S7ClOSEO
Figure 3. Test Circuit lor Hlgh-Lavel Pulse and Squarewave
Output
1-190
XR·205
pulse to this terminal. For Rs = 1 Kn, a sync
pulse of 0.1V to 1V amplitude is recommended.
OUTPUT WAVEFORMS
TRIANGLE OUTPUT
WAVEFORM ADJUSTMENT (PINS 7 AND 8)
The shape of the output waveform at pins 1 and 2 is
controlled by a potentiometer, Rj, connected between
these terminals as shown in Figure 1. For sinewave outputs at pins 1 and 2, the value of Rj is adjusted to minimize the harmonic content of the output waveform. This
adjustment is independent of frequency and needs to
be done only once. The output can be converted to a
symmetrical triangle waveform by increasing the effective resistance across these terminals. This can be
done without changing the potentiometer setting, by
opening the switch S2 as shown in Figures 1-3.
BUFFER INPUT AND OUTPUT (PINS 10 AND 11)
The buffer amplifier can be connected to any of the circuit outputs (pins 1, 2, 12, 14 or 15) to provide low output impedance and high current drive capability. For
proper operation of the buffer amplifier, pin 11 must be
connected to the most negative potential in the circuit,
with an external load resistor RL (0.75 Kn < RL < 10
Kn). The maximum output current at this pin must not
exceed 20 mA.
DUTY CYCLE ADJUSTMENT
The duty-cycle of the output waveforms can be adjusted by connecting a resistor RB across pins 13 and 14,
as shown in Figures 1-3. With switch S2 open, the output waveform will be symmetrical. Duty cycle is reduced as RB is decreased. (See Figure 6.)
The circuit is connected as shown in Figures 1 or 2,
with switches S1 and S2 open.
SINEWAVE OUTPUT
The circuit is connected as shown in Figures 1 or 2,
with switch S2 open and S1 closed. The output waveform is adjusted for minimum harmonic distortion using
trimmer resistor Rj connected across pins 7 and 8. Sinusoidal output is obtained from pins 1 or 2 (or pin 11 if
the buffer amplifier is used). The amplitude of the output waveform is controlled by the differential dc voltage
appearing between pins 3 and 4. This bias can be controlled by potentiometer Rq . for a differential bias between these terminals of ± 2 volts or greater, the output
amplitude is maximum and equal to approximately 3
volts pop.
SAWTOOTH OUTPUT
The circuit is connected as shown in Figures 1 or 2,
with switch S1 open and S2 closed. Closing S2 places
resistor RB across pins 13 and 14. This changes the duty cycle of the triangle output and converts it to a sawtooth waveform. The polarity of the sawtooth can be
changed by reversing the polarity of the dc bias across
pins 3 and 4. If S1 is closed, the linear sawtooth waveform is converted to the sinusoidal sawtooth waveform
of Figure 9A.
RAMP OUTPUT (FIGURE 9B)
ADDITIONAL GAIN CONTROL
For amplitude modulated output signals, the dc level
across pins 3 and 4 is fixed by the modulation index required. In this case, the output amplitude can be controlled without effecting the modulation by connecting a
potentiometer between pins 1 and 2.
ON-OFF KEYING
The oscillator can be keyed off by applying a positive
voltage pulse to the sweep input terminal. With Rs = 1
Kn, oscillations will stop if the applied potential at pin
13 is raised 3 volts above its open-circuit value.
1-191
For ramp outputs, switch S3 of Figure 1 or 2 is opened,
and pin 10 is shorted to pin 14. This results in a 1.4 volt
pop ramp output at pin 11. The duty cycle of this ramp
can be controlled by connecting RB across pins (13-14)
or (13-15).
SQUAREWAVE AND PULSE OUTPUTS
For squarewave outputs, the circuit is connected as
shown in Figure 3, with S2 open. The output can be
converted to a pulse by closing S2. The duty cycle of
:he pulse output is controlled by potentiometer RD. The
amplitude and polarity of either the pulse or squarewave output can be controlled by potentiometer Rq .
XR·205
.02
..
"'-
1---
.
'1--
r-±-
1--- ---
.~
--~ --
-•• -6
1
r----t----,----------
-- -- -
10
102
103
104
-r- f\
105
10&
10'
FflEOUENCV IHd
Figure 4. Frequency as a Function 01 CD
Across Pins 14 and 15
Figure 5. Modular Section Phasa and
AmplHude Transfer Characteristics
Figure 6. Duty-Cycle Ind Frequency
Variation as I Function 01 Re.istar Ra
Connected Acrass Pins 13 and 14
NORMAlIZr.O fAEQU£NCY Iflfol
Figura 7. HOImaUnd Frequency VI.
SWllP VoHage
Figure 8. Sinusoidal Output Distortion
as a Function 01 Frequency SWllP
Figure 9. Sinusoidal SaWIGoth and
Une.r Rlmp Outputs
11
BUfHfI
AMPLtFIUI
OSClll,.ATOR
EQUIVALENT SCHEMATIC DIAGRAM
1-192
XR·2206
Monolithic Function Generator
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-2206 is a monolithic function generator integrated circuit capable of producing high quality sine,
square, triangle, ramp, and pulse waveforms of highstability and accuracy. The output waveforms can be
both amplitude and frequency modulated by an external voltage. Frequency of operation can be selected
externally over a range of 0.01 Hz to more than 1 MHz.
The circuit is ideally suited for communications, instrumentation, and function generator applications requiring sinusoidal tone, AM, FM, or FSK generation. It has a
typical drift specification of 20 ppm/DC. The oscillator
frequency can be linearly swept over a 2000:1 frequency range, with an external control voltage, having a
very small affect on distortion.
l
AM
INPUT
SYMMETRY
ADJ.
,..,..ORN
J
OUTPUT
l
MULT.OUT
WAVEFORM
ADJ.
J
+vcc
GROUND
TIMlk
CAPACITOR
L
FEATURES
Low-Sine Wave Distortion
Excellent Temperature Stability
Wide Sweep Range
Low-Supply Sensitivity
Linear Amplitude Modulation
TIL Compatible FSK Controls
Wide Supply Range
Adjustable Duty Cycle
r
BYPASS
L
INPUT
TIMING
RESISTORS
0.5%,
20 ppm/DC,
2000:1,
0.01 % V,
Typical
Typical
Typical
Typical
FSK
ORDERING INFORMATION
10V to 26V
1% to 99%
APPLICATIONS
Waveform Generation
Sweep Generation
AM/FM Generation
V/F Conversion
FSK Generation
Phase-Locked Loops (VCO)
Part Number
Package
Operating Temperature
XR-2206M
XR-2206N
XR-2206P
XR-2206CN
XR-2206CP
Ceramic
Ceramic
Plastic
Ceramic
Plastic
- 55°C to + 125°C
O°C to + 70°C
O°C to +70°C
O°C to +70°C
O°C to +70°C
SYSTEM DESCRIPTION
The XR-2206 is comprised of four functional blocks; a
voltage-controlled oscillator (VCO), an analog multiplier
and sine-shaper; a unity gain buffer amplifier; and a set
of current switches.
The VCO actually produces an output frequency proportional to an input current, which is produced by a resistor from the timing terminals to ground. The current
switches route one of the timing pins current to the
VCO controlled by an FSK input pin, to produce an output frequency. With two timing pins, two discrete output
frequencies can be independently produced for FSK
Generation Applications.
ABSOLUTE MAXIMUM RP.TINGS
Power Supply
Power Dissipation
Derate Above 25°C
Total Timing Current
Storage Temperature
SYNC
OUTPUT
26V
750 mW
5 mW/oC
6 mA
- 65°C to + 150°C
1-193
XR·2206
ELECTRICAL CHARACTERISTICS
last Conditions: Test Circuit 01 Figure 1, V + = 12V, TA = 25°, C = 0.01 ,..F, Rl = 100 kO, R2 = 10 kO, R3 = 25 kO
unless otherwise specified. Sl open far triangle, closed for sine wave.
PARAMETERS
MIN
XR-220SM
TYP MAX
MIN
XR-220SC
TYP MAX
UNITS
CONDITIONS
GENERAL CHARACTERISTICS
Single Supply Voltage
Split-Supply Voltage
Supply Current
10
±5
12
26
±13
17
10
±5
14
26
±13
20'
V
V
mA
Rl "" 10 k 0
OSCILLATOR SECTION
Max. Operating Frequency
Lowest Practical Frequency
Frequency Accuracy
Temperature Stability
0.5
Supply Sensitivity
Sweep Range
Reference Bypass Voltage
MHz
Hz
% 0110
ppm/oC
0.1
0.01
%IV
2000:1
fH=fL
2
8
2
8
%
%
0.1
0.1
%
0.01
0.5
1000:1 2000:1
Sweep Linearity
10:1 Sweep
1000:1 Sweep
FM Distortion
Recommended Timing
Components
Timing Capacitor: C
Timing Resistors:
Rl & R2
Triangle Sine Wave Output
Triangle Amplitude
Sine Wave Amplitude
Max. Output Swing
Output Impedance
Triangle Linearity
Amplitude Stability
Sine Wave Amplitude
Stability
Sine Wave Distortion
Without Adjustment
With Adjustment
Amplitude Modulation
Input Impedance
Modulation Range
Carrier Suppression
Linearity
Square-Wave Output
Amplitude
Rise Time
Fall Time
Saturation Voltage
Leakage Current
FSK Keying Level (Pin 9)
±4
±50
1
0.01
±2
±20
1
0.01
±1
±10
0.001
1
40
100
2000
160
60
6
600
1
0.5
4800
2.5
0.4
50
0.001
1
160
60
6
600
1
0.5
4800
80
2.5
0.5
1.0
100
100
55
2
100
2000
50
,..F
kO
mV/kO
mV/kO
V pop
0
%
dB
ppm/oC
C = 1000pF, Rl = 1 kO
C = 50 ,..F, Rl = 2 M 0
fo = l/R1C
O°C :s TA :s 70°C,
Rl = R2 = 20 k 0
VLOW = 10V, VHIGH =
20V,
Rl = R2 = 20 k 0
fH @ Rl = 1 k 0
fL @ Rl = 2 M 0
fL = 1 kHz, fH = 10 kHz
fL = 100 kHz, fH = 100
kHz
± 10% Deviation
See Figure 4.
See Note 1, Figure 2.
Figure 1, Sl Open
Figure 1, Sl Closed
For 1000:1 Sweep
See Note 2.
%
%
Rl = 30 k 0
See Figures 6 and 7.
100
100
55
2
kO
%
dB
%
For 95% modulation
0.6
100
2.4
V pop
nsec
nsec
V
3.5
0.8
12
250
50
0.2
0.1
1.4
0.4
20
2.4
0.8
12
250
50
0.2
0.1
1.4
2.9
3.1
3.3
2.5
3
1.5
,..A
V
V
Measured at Pin 11.
CL = 10 pF
CL = 10 pF
IL = 2 mA
Vll = 26V
See section on circuit
controls
Measured at Pin 10.
Note 1: Output amplitude is directly proportional to the resistance, R3, on Pin 3. See Figure 2.
Note 2: For maximum amplitude stability, R3 should be a positive temperature coefficient resistor.
1-194
XR·2206
L
- r.l
S, = OPEN FOR TRIANGLE
CLOSED FOR SINE WAVE.
f--
\
~
cr----~~~-Ov+
/
1\
V
V
1\V
V+f2
DC YOLTAGE AT PIN 1
Figure 1. Basic Test Circuit.
Figure 5. Normalized Output Amplitude versus DC Bias at
AM Input (Pin 1).
T~IANGLE II
/
/
/
/
~RiJ:JG~o~
MINIMUM
DISTORTION AT30Kll
VSINEWAYE
/
./V
I
/V
W' ..
~ ........
. ..
20
100
10
1.0
100
TIMINGRKU
Figure 2. Output Amplitude as a Function of the Resistor,
R3, at Pin 3.
--
10'
Figure 6. Trimmed Distortion versus Timing Resistor.
1
R=3KII
.•
YOUT = 0.5 YRMS PIN 2
AL'" 10KJl
r:
I
/
V
is
10 L-__- L__
~
____L-__
,.
12
~
20
___
2.
26
10
100
tK
Ycc(Y)
10K
lOOK
1M
FREQUENCY (Hz)
Figure 3. Supply Current versus Supply Voltage, Timing, R.
Figure 7. Sine Wave Distortion versus Operating Frequency
with Timing Capacitors Varied.
1DMn , . . - - , - - - , - - , - - , - - , . - - - , - - , - -
1 un
1-4--I---I--+--+--+--f----j
l
i
1-: 1-~==r!!.!.1---+---T'_=1='l
10Kn~
lKn~
10-2
10
102
-.
I--+---I----jr--+---I-~--~
_,L-~
104
-so
108
FREQUENCY Hz
__
-25
L-~
0
__
25
~~
50
__
75
~~
100
AMBIENTTEMPEAATURE rC)
Figure 4. R versus Oscillation Frequency.
Figure 8. Frequency Drift versus Temperature.
1·195
XR·2206
Re
SWEEP
INPUT
+ Ve
~-
-Ie
liB
-=-
_IT
PIN7
ORB
af
12
Figure 9. Circuit Connection for Frequency Sweep.
10!-,F
S.lK
v. o---+:----'=--IU
V+o-~~--==--r
saUAREWAVE
OUTPUT
..iIUl
51 CLOSED FOR SINEWAVE
Figure 10. Circuit for Sine Wave Generation without External
Adjustment. (See Figure 2 for Choice of R3)'
Figure 12. Sinusoidal FSK Generator.
t
2
C
R,' R;2
OUTVCYClE
Figure 13. Circuit for Pulse and Ramp Generation.
Figure 11. Circuit for Sine Wave Generation with Minimum
Harmonic Distortion. (R3 Determines Output
Swing-See Figure 2.)
1-196
R 1A,I R2
XR·2206
Frequency-Shift Keying:
FSK Generation
The XR-2206 can be operated with two separate timing
resistors, R1 and R2, connected to the timing Pin 7 and
8, respectively, as shown in Figure 12. Depending on
the polarity of the logic signal at Pin 9, either one or the
other of these timing resistors is activated. If Pin 9 is
open-circuited or connected to a bias voltage ~ 2V, only
R1 is activated. Similarly, if the voltage level at Pin 9 is
:s 1V, only R2 is activated. Thus, the output frequency
can be keyed between two levels, Ij and f2' as:
Figure 12 shows the circuit connection for sinusoidal
FSK signal operation. Mark and space frequencies can
be independently adjusted, by the choice of timing resistors, R1 and R2; the output is phase-continuous during transitions. The keying signal is applied to Pin 9. The
circuit can be converted to split-supply operation by
simply replacing ground with V-.
f1 = 1/R1C and f2 = 1/R2C
Figure 13 shows the circuit for pulse and ramp waveform generation. In this mode of operation, the FSK keying terminal (Pin 9) is shorted to the square-wave output
(Pin 11), and the circuit automatically frequency-shift
keys itself between two separate frequencies during
the positive-going and negative-going output waveforms. The pulse width and duty cycle can be adjusted
from 1 % to 99%, by the choice of R1 and R2. The values of R1 and R2 should be in the range of 1 kO to 2
MO.
Pulse and Ramp Generation
For split-supply operation, the keying voltage at Pin 9 is
referenced to V - .
Output DC Level Control:
The dc level at the output (Pin 2) is approximately the
same as the dc bias at Pin 3. In Figures 10, 11 and 12,
Pin 3 is biased midway between V+ and ground, to
give an output dc level of .. V + 12.
APPLICATIONS INFORMATION
PRINCIPLES OF OPERATION
Sine Wave Generation
Description of Controls
Without External Adjustment:
Frequency 01 Operation:
Figure 10 shows the circuit connection for generating a
sinusoidal output from the XR-2206. The potentiometer,
R1 at Pin 7, provides the desired frequency tuning. The
maximum output swing is greater than V + 12, and the
typical distortion (THO) is <2.5%. If lower sine wave
distortion is desired, additional adjustments can be provided as described in the following section.
The frequency of oscillation, fo, is determined by the external timing capacitor, C, across Pin 5 and 6, and by
the timing resistor, R, connected to either Pin 7 or 8.
The frequency is given as:
The circuit of Figure 10 can be converted to split-supply
operation, simply by replacing all ground connections
with V-. For split-supply operation, R3 can be directly
connected to ground.
and can be adjusted by varying either R or C. The recommended values of R, for a given frequency range, as
shown in Figure 4. Temperature stability is optimum for
4 kO < R < 200 kO. Recommended values of Care
from 1000 pF to 100 /-IF.
fo =
With External Adjustment:
....L
RC
Hz
Frequency Sweep and Modulation:
The harmonic content of sinusoidal output can be reduced to .. 0.5% by additional adjustments as shown
in Figure 11. The potentiometer, RA, adjusts the sineshaping resistor, and RS provides the fine adjustment
for the waveform symmetry. The adjustment procedure
is as follows:
Frequency of oscillation is proportional to the total timing current, ITo drawn from Pin 7 or 8:
_ 320 IT (mA) H
f C (/-IF)
z
1. Set RS at midpoint, and adjust RA for minimum
distortion.
Timing terminals (Pin 7 or 8) are low-impedance points,
and are internally biased at + 3V, with respect to Pin 12.
Frequency varies linearly with IT, over a wide range of
current values, from 1 /-IA to 3 mA. The frequency can
be controlled by applying a control voltage, VC, to the
activated timing pin as shown in Figure 9. The frequency of oscillation is related to Vc as:
2. With RA set as above, adjust RS to further reduce
distortion.
Triangle Wave Generation
The circuits of Figures 10 and 11 can be converted to
triangle wave generation, by simply open-circuiting Pin
13 and 14 (i.e., S1 open). Amplitude of the triangle is approximately twice the sine wave output.
f = _1_1 + ...!!....(1- VC) Hz
RC
RC
3
1-197
XR·2206
Amplituda Modulation:
where Veis in volts. The voltage-to-frequency conversion gain, K, is given as:
K = iJfliJVe = -
Output amplitude can be modulated by applying a dc bias and a modulating signal to Pin 1. The internal impedance at Pin 1 is approximately 100 kO. Output amplitude varies linearly with the applied voltage at Pin 1, for
values of dc bias at this pin, within ± 4 volts of V + 12 as
shown in Figure 5. As this bias level approaches V + 12,
the phase of the output signal is reversed, and the amplitude goes through zero. This propert~ is suitable for
phase-shift keying and suppressed-carner AM generation. Total dynamic range of amplitude modulation is approximately 55 dB.
0.32 HzN
Ree
CAUTION: For safety operation of the circuit, IT
should be limited to s3 mAo
Output Amplituda:
Maximum output amplitude is inversely proportional to
the external resistor, R3, connected to Pin 3 (see Figure
2). For sine wave output, amplitude is approximately 60
mV peak per kO of R3; for triangle, the peak amplitude
is approximately 160 mV peak per kO of R3. Thus, for
example, R3 = 50 kO would produce approximately
± 3V sinusoidal output amplitude.
CAUTION: AM control must be used in conjunction
with a well· regulated supply, since the output amplitude
now becomes a function of V + .
v+
v+
4
INT'NL.
REG.
12
EQUIVALENT SCHEMATIC DIAGRAM
1-198
XR·2207
Voltage-Controlled Oscillator
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-2207 is a monolithic voltage-controlled oscillator (VCO) integrated circuit featuring excellent frequency stability and a wide tuning range. The circuit provides simultaneous triangle and squarewave outputs
over a frequency range of 0.01 Hz to 1 MHz. It is ideally
suited for FM, FSK, and sweep or tone generation, as
well as for phase-locked loop applications.
+Vcc
TRIANGLE
WAVE OUT
I
SQUARE
WAVE OUT
TIMING
CAPACITOR
L
VEE
~
The XR-2207 has a typical drift specification of 20 ppm/
DC. The oscillator frequency can be linearly swept over
a 1000:1 range with an external control voltage; and the
duty cycle of both the triangle and the squarewave outputs can be varied from 0.1 % to 99.9% to generate
stable pulse and sawtooth waveforms.
I
I
BIAS
GROUND
R,
TIMING
RESISTORS
--,
R,
BINARY
KEYING
INPUTS
~
FEATURES
Excellent Temperature Stability (20 ppm/DC)
Linear Frequency Sweep
Adjustable Duty Cycle (0.1 % to 99.9%)
Two or Four Level FSK Capability
Wide Sweep Range (1000:1 Min)
Logic Compatible Input and Output Levels
Wide Supply Voltage Range (±4V to ± 13V)
Low Supply Sensitivity (0.1 % N)
Wide Frequency Range (0.01 Hz to 1 MHz)
Simultaneous Triangle and Squarewave Outputs
-.J
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR2207M
XR2207N
XR2207P
XR2207CN
XR2207CP
Ceramic
Ceramic
Plastic
Ceramic
Plastic
- 55°C to + 125°C
O°C to + 70°C
O°C to + 70°C
O°C to +70°C
O°C to +70°C
SYSTEM DESCRIPTION
APPLICATIONS
The XR-2207 utilizes four main functional blocks for frequency generation. These are a voltage controlled oscillator (VCO), four current switches which are activated
by binary keying inputs, and two buffer amplifiers for triangle and squarewave outputs. The VCO is actually a
current controlled oscillator which gets its input from
the current switches. As the output frequency is proportional to the input current, the VCO produces four discrete output frequencies. Two binary input pins determine which timing currents are channelled to the VCO.
These currents are set by resistors to ground from each
of the four timing terminals.
FSK Generation
Voltage and Current-to-Frequency Conversion
Stable Phase-Locked Loop
Waveform Generation
Triangle, Sawtooth, Pulse, Squarewave
FM and Sweep Generation
ABSOLUTE MAXIMUM RATINGS
26V
Power Supply
Power Dissipation (package limitation)
Ceramic package
750 mW
6.0 mW/oC
Derate above +25°C
625 mW
Plastic package
5 mW/oC
Derate above + 25°C
Storage Temperature Range
-65°C to + 150°C
The triangle output buffer provides a low impedance
output (1011 TVP) while the squarewpve is an opencollector type. A programmable reference point allows
the XR-2207 to be used in either single or slip supply
configurations.
1-199
XR·2207
ELECTRICAL CHARACTERISTICS
Test Conditions: Test Circuit of Figure 1, V + = V - = 6V, TA = + 25°C, C = 5000 pF, R1 = R2 = R3 = R4
20 KO, RL = 4.7 KO, Binary Inputs grounded, 81 and 82 closed unless otherwise specified.
XR·2207/XR·2207M
PARAMETERS
MIN
TYP
XR·2207C
MAX
MIN
26
±13
8
±4
TYP
MAX
UNITS
26
±13
V
V
CONOITIONS
GENERAL CHARACTERISTICS
Supply Voltage
Single Supply
Split Supplies
Supply Current
Single Supply
8
±4
Split Supplies
Positive
Negative
See Figure 3
5
7
5
8
mA
Measured at pin 1, SI and S2 open
See Figure 2
5
4
7
6
5
4
8
7
mA
mA
Measured at pin 1, SI, S2 open
Measured at pin 12, SI, S2 open
OSCILLATOR SECTION - FREQUENCY CHARACTERISTICS
Upper Frequency Limit
Lowest Practical Frequency
Frequency Accuracy
Frequency Matching
Frequency Stability
Temperature
Power Supply
Sweep Range
Sweep Linearity
10:1 Sweep
1000:1 Sweep
FM Distortion
Recommended Range of
Timing Resistors
Impedance at Timing Pins
DC Level at Timing Terminals
0.5
1000:1
1.0
0.01
±1
0.5
20
0.15
3000:1
0.5
±3
50
1.0
0.01
±1
0.5
±5
30
0.15
1000:1
MHz
Hz
% of fo
% of fo
C = 500 pF, R3 = 2 KIl
C = 50 I'F, R3 = 2 Mil
ppm/oC
DoC
fHlfL
%
1
5
0.1
1.5
2
2000
1.5
5
0.1
1.5
75
10
<
TA
<
70°C
%N
2000
75
10
%
KIl
Il
mV
R3 = 1.5 KIl for fHl
R3 = 2 Mil for fL
C = 5000 pF
fH = 10kHz, fL = 1 kHz
fH = 100 kHz, fL = 100 Hz
±10% FM Deviation
See Characteristic Curves
Measured at pins 4, 5, 6, or 7
BINARY KEYING INPUTS
Switching Threshold
1.4
Input Impedance
2.2
2.8
1.4
5
2.2
2.8
V
5
KIl
6
Vpp
Il
mV
%
Measured at pins 8 and 9,
Referenced to pin 10
OUTPUT CHARACTERISTICS
Triangle Output
Amplitude
Impedance
DC Level
Linearity
Squarewave Output
Amplitude
Saturation Voltage
Rise Time
Fall Time
Measured at pin 13
4
11
6
10
+100
0.1
12
0.2
200
20
4
10
+100
0.1
11
0.4
12
0.2
200
20
0.4
Vpp
V
nsec
nsec
Referenced to pin 10
From 10% to 90% to swing
Measured at pin 13, S2 closed
Referenced to pin 12
CL ,;; 10 pF
CL ,;; 10 pF
PRECAUTIONS
nent damage to the device may occur if the total
timing current exceeds 10 mAo
2. Terminals 2, 3, 4, 5, 6, and 7 have very low internal
impedance and should, therefore, be protected from
accidental shorting to ground or the supply voltages.
3. The keying logic pulse amplitude should not exceed
the supply voltage.
The following precautions should be observed when operating the XR-2207 family of integrated circuits:
1. Pulling excessive current from the timing terminals
will adversely effect the temperature stability of the
circuit. To minimize this disturbance, it is recommended that the total current drawn from pins 4, 5,
6, and 7 be limited to ~6 mA. In addition, perma-
1-200
XR·2207'
r-~--------~----~~~--·--~~------4---~~---------'----oV'
TAIANGU WAVE
14 OUTPUT
~-------L--------~~----~--~~--oV·
12
EQUIVALENT SCHEMATIC DIAGRAM
o.~
I,'
1-'..:.3o-....{) ~~~~A~UT
14
1-'..:.3o-....{)
TRIANGLE
WAVE OUT
Figure 1. Test Circuit For Split Supply Operation
14
~~~~RJuT
TRIANGLE
WAVE OUT
Figure 2. Test Circuit For Single Supply Operation
range from 100 pF to 100 p.F. The capacitor should be
non·polar.
PRINCIPLES OF OPERATION
TIMING CAPACITOR (PINS 2 AND 3)
TIMING RESISTORS (PINS 4, 5, 6, AND 7)
The oscillator frequency is inversely proportional to the
timing capacitor, C, as indicated in Figure 8. The mini·
mum capacitance value is limited by stray capaci·
tances and the maximum value by physical size and
leakage current considerations. Recommended values
The timing resistors determine the total timing current,
IT, available to charge the timing capacitor. Values for
timing resistors can range from 2 KIl to 2 Mil; however,
for optimum temperature and power supply stability,
1·201
XR·2207
recommended values are 4 KO to 200 KO (see Figures
4, 5, and 7). To avoid parasitic pick up, timing resistor
leads should be kept as short as possible. For noisy environments, unused or deactivated timing terminals
should be bypassed to ground through 0.1 /LF capacitors.
are activated by the logic signals at the binary keying
inputs (pins 8 and 9), as shown in the logic table (Table
1). If a single timing resistor is activated, the frequency
is 1IRC. Otherwise, the frequency is either 1I(RlI1R2)C
or 1/(R3I1R4)C.
The squarewave output is obtained at pin 13 and has a
peak-to-peak voltage swing equal to the supply voltages. This output is an "open-collector" type and requires an external pull-up load resistor (nominally 5 KO)
to the positive supply. The triangle waveform obtained
at pin 14 is centered about ground and has a peak am-'
plitude of V + 12.
SUPPLY VOLTAGE (PINS 1 AND 12)
The XR-2207 is designed to operat!! over a power supply range of ±4V to± 13V for split supplies, or 8V to
26V for single supplies. At high supply voltages, the frequency sweep range is reduced (see Figures 3 and 4).
Performance is optimum for ±6V, or 12V single supply
operation.
BINARY KEYING INPUTS (PINS BAND 9)
The circuit operates with supply voltages ranging from
±4V to ± 13V. Minimum drift occurs with ±6 volt supplies. For operation with unequal supply voltages, see
Figure 3.
The internal impedance at these pins is approximately
5 KO. Keying levels are < l.4V for "zero" and > 3V for
"one" logic levels referenced to the dc voltage at pin
10 (see Figure 8).
Note: For Single-Supply Operation, Logic Levels are
Referenced to Voltage at Pin 10
BIAS FOR SINGLE SUPPLY (PIN 11)
For single supply operation, pin 11 should be externally
biased to a potential between V + 13 and V + 12 volts
(see Figure 2). The bias current at pin 11 is nominally
5 % of the total oscillation timing current, Iy.
SINGLE SUPPLY OPERATION
The circuit should be interconnected as shown in Figure 11 for single supply operation. Pin 12 should be
grounded, and pin 11 biased from V+ through a resistive divider to a value of bias voltage between V + 13
and V+ 12. Pin 10 is bypassed to ground through a 1 /LF
capacitor.
GROUND (PIN 10)
For split supply operation, this pin serves as circuit
ground. For single supply operation, pin 10 should be
ac grounded through a 1 /LF bypass capacitor. During
split supply operation, a ground current of 21T flows out
of this terminal, where IT is the total timing current.
For single supply operation, the dc voltage at pin 10
and the timing terminals (pins 4 through 7) are equal
and approximately 0.6V above VB, the bias voltage at
pin 11. The logic levels at the binary keying terminals
are referenced to the voltage at pin 10.
SQUAREWAVE OUTPUT (PIN 13)
The squarewave output at pin 13 is a "open-collector"
stage capable of sinking up to 20 mA of load current.
RL serves as a pull-up load resistor for this output. Recommended values for RL range from 1 KO to 100 KO.
For a fixed frequency of f3 = 1/R3C, the external circuit connections can be simplified as shown in Figure
l1b.
TRIANGLE OUTPUT (PIN 14)
The output at pin 14 is a triangle wave with a peak
swing of approximately one-half of the total supply voltage. Pin 14 has a very low output impedance of 100
and is internally protected against short circuits.
Table 1
Logic Table for Binary Keying Controls
BYPASS CAPACITORS
The recommended value for bypass capacitors is 1 /LF,
although larger values are required for very low frequency operation.
LOGIC
LEVEL SELECTED
- r - TIMING
FREQUENCY
PINS
B 9
SPLIT SUPPLY OPERATION
a a
a 1
1 a
Figure 1 is the recommended circuit connection for
split supply operation. The frequency of operation is determined by the timing capacitor, C, and the activated
timing resistors (Rl through R4). The timing resistors
1
1-202
6
6 and 7
11
5
1 I 4and5
12
DEFINITIONS
=
=
lIR3C, 411 - lIR4C
11
11
+ 411
12
12
Logic Levels:
+ 412
1/R2C,412 - 1/R1C
a-
1 - >3 V
Ground
XR·2207
25r------r------r------r-----,
1 "'"I-------tJt,~~~----+:__=-=-l
20f---~~~----_r------+_----_1
1 KU
O~----.•7:-V:-----.~.V-:-----':-:,2'::V----.-:-!16'V
SPLIT SUPPt y
1~
°0~-------~5:-------~1~0-------~,5:-------~~
Figure 4. Recommended Timing Resistor Value
Supply Voltage·
Figure 3. lYplcal Operating Range For Spilt Supply Voltage
1,04
/
Vs = '6V
C = 5000
~ 3
13a:
a:
w
1
/'
> 0
U
5w -2
-3
,/
-4
~
VI.
Power
r---.,.----,r---,-----,r---.,.---,
1.02 /----P\.-----1r----t------1i--
o
>
pF
~ 1.00 t----t~~~§::t:=~~~~~~
/
::>
ow
V
~
.98 1------ti<------1r---+--~I'-l:::_+----;
0
w
N
./
~ -1
ff:
t
j
/
2
32
SUPPLY VOt TAGE IVOl lSI ...
NEGATIVE SUPPLY IVOlTl
5
i..
SINGLE SUPPL V
:::; .96
u
z
w
0
:>
0
w
...a:
0
-1%
w
N
:::;
and 7
fl
fl+MI
0
I
5
4 and 5
f2
1'2 +M2
I
v'
DEFINITIONS
fl=I/R3C.~fl=I/R4C
SQUARE WAVE
OUT
1'2= I/R2C.~f2= I/RIC
Logic Levels: 0 = Ground
TRIANGLE WAVE
OUT
I =>3V
Figure B. Logic Table For Binary Keying Controls.
Note: For Single-Supply Operation, Logic Lavels are
Referenced to Vohage at Pin 10
A
TIMING CAPACITOR
v'
v'
v'
SQUARE WAVE
OUT
TRIANGLE WAVE
OUT
10
BINARY
~~~~~~lS 1--+-""1r--1
v-
Figure 10. Split-Supply Operation:
la) General
Ib) Fixed Frequency
Figure 9. Simplified Schematic of Frequency Control
Mechanism
The frequency f will increase as the control voltage is
made more negative. If R3 = 2 Mil. Re = 2 KIl. e =
5000 pF. then at 1000: 1 frequency sweep would result
for a negativ sweep voltage Ve "" V-.
FREQUENCY CONTROL ISWEEP AND FM)
The frequency of operation is controlled by varying the
total timing current, IT, drawn from the activated timing
pins 4, 5, 6, or 7. The timing current can be modulated
by applying a control voltage. Ve. to the activated timing pin through a series resistor Re as shown in Figures
12 & 13.
The voltage to frequency conversion gain, K, is controlled by the series resistance Re and can be expressed as:
K = ~ = - __l-Hzlvolt
AVe
Reev-
For split supply operation. a negative control voltage,
Ve. applied to the circuits of Figures 15 & 16 causes
the total timing current, IT. and the frequency, to increase.
The circuit of Figure 12 can operate both with positive
and negative values of control voltage. However. for
positive values of Ve with small (RdR3) ratio, the direction of the timing current IT is reversed and the oscillations will stop.
As an example. in the circuit of Figure 12. the binary
keying inputs are grounded. Therefore, only timing pin
6 is activated.
The frequency of operation. normally f =
R~e'
Figure 13 shows an alternate circuit for frequency control where two timing pins, 6 and 7. are activated. The
frequency and the conversion gain expressions are the
same as before, except that the circuit would operate
only with negative values of Ve. For Ve > 0, pin 7 becomes deactivated
is now
proportional to the control voltage, Ve. and determined
as:
f = _1_
R3e
R3 HZ]
[1 _Ve
ReV -
and the frequency is fixed at f
1-204
= R~e.
XR·2207
with Figure 11. For a "high" logic level at pin 8, the tim·
ing resistors Rl and R2 are activated. Similarly, for a
"low" logic level, timing resistors R3 and R4 are enabled.
CAUTION
For operation of the circuit, total timing current IT must
be less than 6 rnA over the frequency control range.
The "high" and "low" logic levels at pin 9 determine
the respective high and low frequencies within the selected FSK channel.
DUTY CYCLE CONTROL
The duty cycle of the output waveforms can be controlled by frequency shift keying at the end of every half
cycle of oscillator output. This is accomplished by connecting one or both of the binary keying inputs (pins 8
or 9) to the squarewave output at pin 13. The output
waveforms can then be converted to positive or negative pulses and sawtooth waveforms.
Recommended component values for various com·
monly used FSK frequencies are given in Table 1. When
only a single FSK channel is used, the remaining channel can be deactivated by connecting pin 8 to either
V+ or ground. In this case, the unused timing resistors
can also be omitted from the circuit.
The low and high frequencies, fl and f2' for a given
FSK channel can be fine tuned using potentiometers
connected in series with respective timing resistors. In
fine tuning the frequencies, fl should be set first with
the logic level at pin 9 in a "low" level.
Figure 14 is the recommended circuit connection for
duty cycle control. Pin 8 is shorted to pin 13 so that the
circuit switches between the "0,0" and the "1,0" logic
states given in Figure 11. Timing pin 5 is activated
when the output is "high," and the timing pin is activated when the squarewave output goes to a low state.
Typical frequency drift of the circuit for DoC to 75°C operation is ±0.2%. Since the frequency stability is di·
rectly related to the external timing components, care
must be taken to use timing components with low temperature coefficients.
The duty cycle of the output waveforms is given as:
Duty Cycle =
~
R2 + R3
FSK TRANSCEIVER (FULL-DUPLEX MODEM)
and can be varied from 0.1 % to 99.9% by proper
choice of timing resistors. The frequency of oscillation,
f, is given as:
f -
~ [R2 :
The XR-2207 can be used in conjunction with the XR210, FSK demodulator, to form a full-duplex FSK transceiver, or modem. A recommended circuit connection
for this application is shown in Figure 20. Table 1 shows
the recommended component values for 300-Baud
(103-type) and 1200-Baud (202-type) Modem applications.
R3J
The frequency can be modulated or swept without
changing the duty cycle by connecting R2 and R3 to a
common control voltage VC, instead of to V- (see Figure 15). The sawtooth and the pulse output waveforms
are shown in Figure 15.
v·
BINARY KEYING
INf'UTS
DN-OFF KEYING
v·
The XR-2207 can be keyed on and off by simply activating an open circuited timing pin. Under certain conditions, the circuit may exhibit very low frequency « 1
Hz) residual oscillations in the "off" state due to internal bias currents. If this effect is undesirable, it can be
eliminated by connecting a 10 MO resistor from pin 3 to
V+.
to •
TWO-CHANNEL FSK GENERATOR
(MODEM TRANSMITTER)
The multi·level frequency shift·keying capability of XR2207 makes it ideally suited for two-channel FSK generation. A recommended circuit connection for this application is shown in Figure 16.
B
For two-channel FSK generation, the "mark" and
"space" frequencies of the respective channels are
determined by the timing resistor pairs (Rl' R2) and
(R3, R4)· Pin 8 is the "channel-select" control in accord
Figure 11. Single Supply Operation:
(a) General
(b) FIxed Frequency
1-205
,[ (V"
- vc) (")]
--v;oRC
CR3
A
1+
XR·2207
v·
v·
saUAREWAVE
OUT
TRIANGLE WAVE
OUT
A
CB • BVPASS CAPACITOR
lie
r-~~EP·
-
v-
OR
'M
INPUT
Figure 12. Frequency Sweep Operation
B
v·
SQUARE WAVE
OUT
TRIANGLE WAVE
OUT
c
v·
Figure 15. Output Waveforms:
la) Squarewave and Triangle Outputs
Ib) Pulse and Sawtooth Outputs
Ic) Frequency-Shift Keyed Output
Top: FSK Output With 12 = 211
Bottom: Keying Logic Input
CB· BYPASS CAPACITOR
f.~
CRl
FOR Vc:::
[1- VeRl]
°
RJ
RCV-
ONLY.
• ve cc>-:J...
v-
SWEEP
-=
OR
FMINPUT
Figure 13. Alternate Frequency Sweep Operation
v· (+6Vl
v·
,"
~
SAWTOOTH
OUTPUT
v·
4.7K
CB· BYPASS CAPACITOR
·2
DUTY CYCLE· R2 + R3
XA-2207
frequency· { -
'2
10K
R2
50K
10K
SDK
I'"
4.1K
R3
v-
Figure 14. Sawtooth and Pulse Outputs
PULSE
OUTPUT
Figure 16. Multi-Channel FSK Generation
1-206
V'
~
XR·2207
12V
Co
1"F
01"F
rl
RO
i~;UT~
"
'2
4K
C.
'~
2K
XR·210
C2
I'"F
FSK
DEMODULATOR
4K
CJ
O.l/'F
500!!
DATA
OUTPUT
2K
10K
FINE TUNE
-= -=
~12V
V·
S1~
O.OljJf
5"'1
-=
FSK OUTPUT
~
SDK
SPACE
ADJ.
MARK
AOJ.
Figure 17. Full Duplex FSK Modem Using XR·21D and
XR·22D7 (See Table 1 For Component Values)
15
TA=2S'C
5
V
/
V
V
0
6
8
10
12
14
SPLIT SUPPL V VOL TAGE (VOL lSI
SINGLE SUPPl Y VOLTAGE (VOL IS)
Figure 18. Positive Supply Current, I + (Measured at Pin 1)
vs. Supply Voltage*
Figure 19. Negative Supply Current, 1- (Measured at Pin
12) vs. Supply Voltage
*Note: RT
1·207
Parallel Combination of Activated Timing Resistors
XR·2209
Precision Oscillator
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-2209 is a monolithic variable frequency oscillator circuit featuring excellent temperature stability and
a wide linear sweep range. The circuit provides simultaneous triangle and squarewave outputs over a frequency range of 0.01 Hz to 1 MHz. The frequency is set
by an external RC product. It is ideally suited for frequency modulation, voltage to frequency or current to
frequency conversion, sweep or tone generation as
well as for phase-locked loop applications when used in
conjunction with a phase comparator such as the XR2208.
TRIANGLE
OUTPUT
7
SOUARE
WAVE
OUTPUT
FEATURES
Excellent Temperature Stability (20 ppm/°C)
Linear Frequency Sweep
Wide Sweep Range (1000:1 Min)
Wide Supply Voltage Range (±4V to ± 13V)
Low Supply Sensitivity (0.15%N)
Wide Frequency Range (0.01 Hz to 1 MHz)
Simultaneous Triangle and Squarewave Outputs
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-2209M
XR-2209CN
XR-2209CP
Ceramic
Ceramic
Plastic
-55·C to + 125·C
O·C to + 70·C
O·C to + 70·C
APPLICATIONS
Voltage and Current-to-Frequency Conversion
Stable Phase-Locked Loop
Waveform Generation
FM and Sweep Generation
SYSTEM DESCRIPTION
The XR-2209 precision oscillator is comprised of three
functional blocks: a variable frequency oscillator which
generates the basic periodic waveforms and two buffer
amplifiers for the triangle and the squarewave outputs.
The oscillator frequency, set by an external capacitor,
C, and the timing resistor, R, operates over 8 frequency
decades, from 0.01 Hz to 1 MHz. With no sweep signal
applied, the frequency of oscillation is equal to l/RC.
ABSOLUTE MAXIMUM RATINGS
Power Supply
26 volts
Power Dissipation (package limitation)
Ceramic Package
385 mW
Plastic Package
300 mW
2.5 mW/oC
Derate above + 25°C
Operating Temperatue Range
XR-2209M
-55°C to +125°C
XR-2209C
O°C to + 70·C
Storage Temperature Range
- 65·C to + 150·C
The XR-2209 has a typical drift specification of 20 ppml
·C. Its frequency can be linearly swept over a 1000:1
range with an external control signal. Output duty cycle
is adjustable from less than 1 % to over 99%. The device may operate from either single or split supplies
from 8 V to 26 V (± 4 V to ± 13 V).
1-208
XR·2209
ELECTRICAL CHARACTERISTICS
= V - = 6V, TA
closed unless otherwise specified.
Test CondHions: Test Circuit of Figure 1, V+
PARAMETERS
MIN
=
+ 25°C, C
= 5000 pF, R - 20 KIl, RL = 4.7 kll. S1
XR·2209M
XR·2209C
TYP MAX MIN TYP MAX UNITS
and S2
CONDITIONS
GENERAL CHARACTERISTICS
Supply Voltage
Single Supply
Split Supplies
Supply Current
Single Supply
26
±13
8
±4
Split Supplies
Positive
Negative
8
±4
26
±13
V
V
See Figure 2
See Figure 1
5
7
5
8
mA
Measured at pin 1, S1, S2 open
See Figure 2
5
4
7
6
5
4
8
7
mA
mA
Measured at pin 1, 8" S2 opfln
Measured at pin 4, S1, S2 open
MHz
Hz
% of
fo
C
C
OSCILLATOR SECTION - FREQUENCY CHARACTERISTICS
Upper Frequency Limit
Lowest Practical Frequency
Frequency Accuracy
Frequency Stability
Temperature
Power Supply
Sweep Range
Sweep Linearity
10:1 Sweep
1000:1 Sweep
FM Distortion
Recommended Range of
Timing Resistors
Impedance at Timing Pin
0.5
1.0
0.01
±1
20
0.15
1000:1 3000:1
0.5
±3
50
1.0
0.01
±1
±5
ppm/oC O°C < TA < 70°C
30
0.15
1000:1
%N
%
KIl
R = 1.5 KIl for fH1
R = 2 Mil for fL
C = 5000 pF
fH = 10kHz, fL = 1 kHz
fH = 100 kHz, fL = 100Hz
± 10% FM Deviation
See Characteristic Curves
75
Il
Measured at pin 4
6
10
0.1
Vpp
Il
%
fH/fL
%
1
5
0.1
1.5
1.5
5
0.1
2
2000
1.5
2000
75
= 500 pF, R = 2 KIl
= 50 ,..F, R = 2 Mil
OUTPUT CHARACTERISTICS
Triangle Output
Amplitude
Impedance
Linearity
Squarewave Output
Amplitude
Saturation Voltage
Rise Time
Fall Time
Measured at pin 8
4
11
4
6
10
0.1
12
0.2
200
20
11
0.4
12
0.2
200
20
0.4
Vpp
V
nsec
nsec
10% to 90% of swing
Measured at pin 7, S2 closed
Referenced to pin 6
CL ::s 10 pF, RL = 4.7 KIl
CL::S 10 pF
3. Triangle waveform linearity is sensitive to parasitic
coupling between the square and the triangle-wave
outputs (pins 7 and 8). In board layout or circuit wiring care should be taken to minimize stray wiring capacitances between these pins.
PRECAUTIONS
The following precautions should be observed when operating the XR-2209 family of integrated circuits:
1. Pulling excessive current from the timing terminal
will adversely effect the temperature stability of the
circuit. To minimize this disturbance, it is recommended that the total current drawn from pin 4 be
limited to ::s6 mAo
2. Terminals 2, 3, and 4 have very low internal impedance and should, therefore, be protected from accidental shorting to ground or the supply voltages.
DESCRIPTION OF CIRCUIT CONTROLS
TIMING CAPACITOR (PINS 2 and 3)
The oscillator frequency is inversely proportional to the
timing capacitor, C. The minimum capacitance value is
limited by stray capaCitances and the maximum value
'·209
XR·2209
1N
Figure 1. Test Circuit for Split Supply Operation (01
4148 or Equivalent)
Figure 2. Test Circuit for Single Supply Operation
CHARACTERISTIC CURVES
Ii
!'ooKn~--~~~~~~~r--1
lKnoL---~~--~--~~--~,~,w
°o~--~----~----~--~
Figure 3. Typical Operating Range
For Split Supply Voltage
$l'LlTSUPf'LV
1~
32
2<1
StNGtESUPPlV
SUl'f'lV VOLTAGE NOl lSI
NEGATIVE SUPPL V IVOl lSI
Figure 4. Recommended Timing Resistor Value vs. Power supply Voltage"
Figure 5. Output Waveforms
Top: Triangle Output (Pin 8)
Bottom: Squarewave Output (Pin 7)
" L.......l__....L__...L.__-'--__L.....J.
12
~',c..,---:':",,:---'""OO-,---:':".----,J
TIMING Rf51STANCf !OHMSI
Figure 6. Frequency Accuracy vs.
Timing Resistance
t.(
t6
i8
tlO
112
SPLIT SUPPl Y VOL lAGE ,VOL lSI
~
I~
16
2"
SINGLE SUPPl V VOL TAGE IVOL lSI
Figure 7. Frequency Drift vs. Supply
Voltage
"Note: RT = Timing Resistor at Pin 4
Figure 8. Normalized Frequency
Drift With Temperature
RECOMMENDED CIRCUIT CONNECTIONS
Figure 9. Circuit Connection for Single
Supply Operation
Figure 10. Generalized Circuit Connection for Split Supply Operation
1-210
Figure 11. Simplified Circuit Connection
for Split Supply Operation With VCC =
VEE > ± 7V (Note: Triangle wave
output has + O. 6V offset with respect to ground.)
XR·2209
OPERATING INSTRUCTIONS
by physical size and leakage current considerations.
Recommended values range from 100 pF to 100 /LF.
The capacitor should be non-polar.
SPLIT SUPPLY OPERATION
The recommended circuit for split supply operation is
shown in Figure 10. Diode 01 in the figure assures that
the triangle output swing at pin 8 is symmetrical about
ground. This circuit operates with supply voltages ranging from ±4V to ±13V. Minimum drift occurs at ±6V
supplies. See Figure 3 for operation with unequal supplies.
TIMING RESISTOR (PIN 4)
The timing resistor determines the total timing current,
Ir, available to charge the timing capacitor. Values for
the timing resistor can range from 1.5 KO to 2 MO; however, for optimum temperature and power supply stability, recommended values are 4 KO to 200 KO (see Figures 4,7, and 8). To avoid parasitic pick up, timing resistor leads should be kept as short as possible.
Simplified Connection
For operation with split supplies in excess of ± 7 volts,
the simplified circuit connection of Figure 11 can be
used. This circuit eliminates the diode 01 used in Figure 10; however the triangle wave output at pin 8 now
has a +0.6 volt DC offset with respect to ground.
SUPPLY VOLTAGE (PINS 1 AND 6)
The XR-2209 is designed to operate over a power supply range of ± 4V to ± 13V for split supplies, or 8V to
26V for single supplies. At high supply voltages, the frequency sweep range is reduced (see Figures 3 and 4).
Performance is optimum for ± 6V, or 12V single supply
operation.
SINGLE SUPPLY OPERATION
The recommended circuit connection for single-supply
operation is shown in Figure 9. Pin 6 is grounded; and
pin 5 is biased from V+ through a resistive divider as
shown in the figure, and is bypassed to ground with a 1
/LF capacitor.
BIAS FOR SINGLE SUPPLY (PIN 5)
For single supply operation, pin 5 should be externally
biased to a potential between V + 13 and V + 12 volts
(see Figure 9). The bias current at pin 5 is nominally 5%
of the total oscillation timing current, IT, at pin 4. This
pin should be bypassed to ground with 0.1 /LF capacitor.
For single supply operation, the DC voltage at the timing terminal, pin 4, is approximately 0.6 volts above VB,
the bias voltage at pin 5.
The frequency of operation is determined by the timing
capacitor C and the timing resistor R, and is equal to 11
RC. The squarewave output is obtained at pin 7 and has
a peak-to-peak voltage swing equal to the supply voltage. This output is an "open-collector" type and requires an external pull-up load resistor (nominally 5 KO)
to V+. The triangle waveform obtained at pin 8 is centered about a voltage level Vo where:
SQUAREWAVE OUTPUT (PIN 7)
The squarewave output at pin 7 is a "open-collector"
stage capable of sinking up to 20 mA of load current.
RLserves as a pull-up load resistor for this output. Recommended values for RL range from 1 KO to 100 KO.
TRIANGLE OUTPUT (PIN 8)
The output at pin 8 is a triangle wave with a peak swing
of approximately one-half of the total supply voltage.
Pin 8 has a very low output impedance of 100 and is internally protected against short circuits.
Vo = VB + 0.6V
where VB is the bias voltage at pin 5. The peak-to-peak
output swing of triangle wave is approximately equal to
V+/2.
FREQUENCY CONTROL (SWEEP AND FM)
--- r--Ie
+
t
o+
RS
Vc
~
The frequency of operation is proportional to the total
timing current IT drawn from the timing pin, pin 4. This
timing current, and the frequency of operation can be
modulated by applying a control voltage, VC, to the timing pin, through a series resistor, RS, as shown in Figure 12. If Vc is negative with respect to VA, the voltage
level at pin 4, then an additional current 10 is drawn
from the timing pin causing IT to increase, thus increasing the frequency. Conversely, making Vc higher
than VA causes the frequency to decrease by decreasing IT.
IT
R
t
4
XR-2209
VA
~
The frequency of operation, is determined by:
6
f = fo [1 + R
Vc R]
RS - VA RS
":'
Figure 12. Frequency Sweep Operation
where fo = l/RC.
1-211
XR·2209
,
r-~---------r----~~----~~~----~~~~'-----------~--O~
TIIIANGLI .AVI
• OU"VT
••
T....IIIQ
IIIIIITOII
EQUIVALENT SCHEMATIC DIAGRAM
1·212
XR·8038
Precision Waveform Generator
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-S03S is a precision waveform generator IC capable of producing sine, square, triangular, sawtooth
and pulse waveforms with a minimum number of external components and adjustments. Its operating frequency can be selected over nine decades of frequency, from 0.001 Hz to 1 MHz by the choice of external RC components. The frequency of oscillation is highly
stable over a wide range of temperature and supply
voltage changes. The frequency control, sweep and
modulation can be accomplished with an external control voltage, without affecting the quality of the output
waveforms. Each of the three basic waveforms, I.e.,
sinewave, triangle and square wave outputs are available simultaneously, from independent output terminals.
ORDERING INFORMATION
The XR-S03S monolithic waveform generator uses advanced processing technology and Schottky-barrier diodes to enhance its frequency performance. It can be
readily interfaced with a monolithic phase-detector circuit, such as the XR-220S, to form stable phase-locked
loop circuits.
Part Number
Package
Operating Temperature
XR-S03SM
XR-S038N
XR-S03SP
XR-S03SCN
XR-S03SCP
Ceramic
Ceramic
Plastic
Ceramic
Plastic
- 55°C to + 125°C
O°C to + 70°C
O°C to + 70°C
O°C to +70°C
O°C to +70°C
FEATURES
SYSTEM DESCRIPTION
Direct Replacement for Intersil S03S
Low Frequency Drift-50 ppm/oC Max.
Simultaneous Sine, Triangle and Square-Wave Outputs
Low Distortion-THO"" 1 %
High FM and Triangle Linearity
Wide Frequency Range-0.001 Hz to 1 MHz
Variable Duty-Cycle-2% to 9S%
APPLICATIONS
The XR-S03S precision waveform generator produces
highly stable and sweepable square, triangle and sine
waves across nine frequency decades. The device
time base employs resistors and a capacitor for frequency and duty cycle determination. The generator
contains dual comparators, a flip-flop driving a switch,
current sources, a buffer amplifier and a sine wave
converter. Three identical frequency waveforms are simultaneously available. Supply voltage can range from
10V to 30V, or ± 5V with dual supplies.
Precision Waveform Generation Sine, Triangle, Square,
Pulse
Sweep and FM Generation
Tone Generation
Instrumentation and Test Equipment Design
Precision PLL Design
Unadjusted sine wave distortion is typically less than
0.7%, with Pin 1 open and S kO from Pin 12 to Pin 11
(- VEE or ground). Sine wave distortion may be improved by including two 100 kO potentiometers between Vee and VEE (or ground), with one wiper connected to Pin 1 and the other connected to Pin 12.
ABSOLUTE MAXIMUM RATINGS
Frequency sweeping or FM is accomplished by applying modulation to Pins 7 and S for small deviations, or
only to Pin S for large shifts. Sweep range typically exceeds 1000:1.
Power Supply
36V
Power Dissipation (package limitation)
750 mW
Ceramic package
6.0 mW/oC
Derate above + 25°C
625 mW
Plastic package
5 mW/oC
Derate above + 25°C
Storage Temperature Range
-65°C to +150°C
The square wave output is an open collector transistor;
output amplitude swing closely approaches the supply
voltage. Triangle output amplitude is typically 1/3 of the
supply, and sine wave output reaches 0.22 VS.
1-213
XR·8038
ELECTRICAL CHARACTERISTICS
Test Conditions: Vs = ±5V to ± 15V, TA = 25°C, RL = 1 MO, RA = RB = 10 Idl, Cl = 3300 pF, S1 closed,
unless otherwise specified. See Test Circuit of Figure 1.
PARAMETERS
XR-8038M/XR-8038
XR-8038C
MIN TYP MAX MIN TYP MAX UNITS
CONDITIONS
GENERAL CHARACTERISTICS
Supply Voltage, Vs
Single Supply
Dual Supplies
Supply Current
10
±5
12
30
±15
15
10
±5
30
±15
20
12
V
V
rnA
Vs = ± 10V. See Note 1.
FREQUENCY CHARACTERISTICS (Measured at Pin 91
Range of Adjustment
Max. Operating Frequency
Lowest Practical Frequency
Max. FM Sweep Frequency
FM Sweep Range
FM Linearity
Range of Timing Resistors
Temperature Stability
XR-8038M
XR-8038
XR-8038C
Power Supply Stability
1
1
MHz
0.001
0.001
Hz
100
1000:1
0.1
100
1000:1
0.2
kHz
0.5
-
1000 0.5
20
50
-
50
100
-
-
1000
-
-
-
50
0.05
0.05
RA = RB = 5000, C1 = 0,
RL = 15 kO
RA = RB = 1 MO, C1 =
500,.F
S1 Open. See Notes 2 and 3.
S1 Open. See Note 3.
Values of RA and RB
%
kO
ppm/oC
ppm/oC
ppm/oC
%N
See Note 4.
OUTPUT CHARACTERISTICS
Square-Wave
Amplitude
Saturation Voltage
Rise Time
Fall Time
Duty Cycle Adj.
Triangle/Sawtooth/Ramp
Amplitude
Linearity
Output Impedance
Sine-Wave Amplitude
Distortion
Unadjusted
Adjusted
0.9
0.98
0.2
100
40
2
0.9
0.4
98
0.98
0.2
100
40
0.5
2
98
x Vs
V
nsec
nsec
%
0.3
0.33
0.05
200
0.3
0.33
0.1
200
x Vs
%
0
0.2
0.22
0.2
0.22
x Vs
0.7
0.5
1.5
0.8
0.5
3
Note 1: Currents through RA ad RB not included.
Note 2: Vs = 20V,f = 10 kHz, RA = RB = 10kO.
Note 3: Apply sweep voltage at Pin 8.
(2/3 Vs + 2V) S Vsweep S Vs
Note 4: 10V S Vs:s 30Vor ±5V S Vs S ±15V.
Note 5: 81 kO resistor connected between Pins 11
and 12.
%
%
Measured at Pin 9.
RL = 100 kO
Isink = 2 rnA
RL = 4.7 kO
RL = 4.7 kO
Measured at Pin 3.
RL = 100 kO
lout=5mA·
RL = 100 kO
RL = 1 MO. See Note 5.
RL = 1 MO
r---"---r-~p--O ·ISV
"
XR.a038
11
12
L..----4-_ _......._ _--o -ISV
Figure 1. Generalized Test Circuit
1-214
XR·8038
CHARACTERISTIC CURVES
10 J
I :
I
102
z
o
;:
~
150
I---t-+-+-
z
z
::
099
10
a
09
er- l-
15
20
25
30
I-
10
Supply Voltage
Power Dissipation vs. Supply Voltage
f-
1
20
UNAgJUSTE~
30
10Hz
Supply Voltage
Frequency Drift vs. Power Supply
WAVEFORM ADJUSTMENT
~ Jl
2
:25
11
4
f-
i
150
L
I !
~
1
C
~
10
I
10
I
+
.~.
-+
I
100
8
I_t-
II +-t
10 1
~
12
!
I
100Hz
)
AD1\1" ~t--
1kHz
10kHz
100kHz
1MHz
Sinewave THO vs. Frequency
slightly more convenient. If no adjustment of the duty
cycle is desired, terminals 4 and 5 can be shorted together, as shown in Figure 2c. This connection, however, carries an inherently larger variation of the dutycycle.
The symmetry of all waveforms can be adjusted with
the external timing resistors. Two possible ways to accomplish this are shown in Figure 2. Best results are
obtained by keeping the timing resistors RA and RB
separate (a). RA controls the rising portion of the triangle and sine-wave and the "Low" state of the square
wave.
With two separate timing resistors, the frequency is
given by
The magnitude of the triangle waveform is set at 1/3
Vee; therefore, the duration of the rising portion of the
triangle is:
t1
=e x
V
=e x
I
113 x Vee x RA
1/5 x Vee
= ~ RA x
or, if RA
e
=
RB
3
=
R
f = 0.3/Re (for Figure 2a)
The duration of the falling portion of the triangle and the
sinewave, and the "High" state of the square-wave is:
t2
=e x
I
V
=
2
e x 1/3 Vee
Vee
1 Vee
-x----x-5
RB
5
=~ x
3
If a single timing resistor is used (Figures 2b and c), the
frequency is
RARBe
2RA - RB
f = 0.15/Re
RA
The frequency of oscillation is independent of supply
voltage, even though none of the voltages are regulated
inside the integrated circuit. This is due to the fact that
both currents and thresholds are direct, linear function
of the supply voltage and thus their effects cancel.
Thus a 50% duty cycle is achieved when RA = RB.
If the duty-cycle is to be varied over a small range
about 50% only, the connection shown in Figure 2b is
-Vee
'Vee
'vee
'c
'c
'c
IU1
IU1
XR~038
'V'v
XR~038
'"
'V'v
'"
Figure 2_ Possible Connections lor the External Timing Resistors.
1-215
IU1
XR-8038
'V'v
'"
XR·8038
(load resistor connected to + 5 Volts) while the waveform generator itself is powered from a higher supply
voltage.
DISTORTION ADJUSTMENT
To minimize sine-wave distortion the a1 kO resistor between pins 11 and 12 is best made a variable one. With
this arrangement distortion of less than 1 % is achievable. To reduce this even further, two potentiometers can
be connected as shown in Figure 3. This configuration
allows a reduction of sine-wave distortion close to
0.5%
RA
[~
~
9
II
12
For small deviations (e.g., ± 10%) the modulating signal can be applied directly to pin a by merely providing
ac coupling with a capacitor, as shown in Figure 4a. An
external resistor between pins 7 and a is not necessary,
but it can be used to increase input impedance. Without it (i.e. terminals 7 and a connected together), the input impedance is akO); with it, this impedance increases to (R + akO).
nn
6
XR-lI038
'-0
The frequency of the waveform generator is a direct
function of the De voltage at terminal a (measured from
+ Vee). By altering this voltage, frequency modulation
is performed.
AL
A,
",
•
FREQUENCY MODULATION AND SWEEP
3
1
f-----<> V'v
2~
For larger FM deviations or for frequency sweeping, the
modulating signal is applied between the positive supply voltage and pin a (Figure 4b). In this way the entire
bias for the current sources is created by the modulating signal and a very large (e.g., 1000:1) sweep range is
obtained (f = 0 at Vsweep = 0). eare must be taken,
however, to regulate the supply voltage; in this configuration the charge current is no longer a function of the
supply voltage (yet the trigger thresholds still are) and
thus the frequency becomes dependent on the supply
voltage. The potential on Pin a may be swept from Vee
to 2/3 Vee + 2V.
""
r100kn
I
~ c
l00kn
I
~V Of
GNO
Figure 3. Connection to Achieve Minimum Sine-Wave Distortion.
SELECTING TIMING COMPONENTS
For any given output frequency, there is a wide range of
Re combinations that will work. However certain constraints are placed upon the magnitude of the charging
current for optimum performance. At the low end, currents of less than 0.1 p.A are undesirable because circuit leakages will contribute significant errors at high
temperatures. At higher currents (1 > 5 mAl, transistor
betas and saturation voltages will contribute increasingly larger errors. Optimum performance will be obtained for charging currents of 1 p. to 1 mAo If pins 7 and
a are shorted together the magnitude of the charging
current due to RA can be calculated from:
1
= R1
x Vee x
(R1 + R2)
(al
A,
XR·8038
10
II
"
J.... = Vee
RA
5RA
v o.
GND
A similar calculation holds for RB.
(bl
SINGLE-SUPPLY AND SPLIT-SUPPLY OPERATION
The waveform generator can be operated either from a
single power-supply (10 to 30 Volts) or a dual powersupply (± 5 to ± 15 Volts). With a single power-supply
the average levels of the triangle and sine-wave are at
exactly one-half of the supply voltage, while the squarewave alternates between + Vee and ground. A split
power supply has the advantage that all waveforms
move symmetrically about ground.
The square-wave output is not committed. A load resistor can be connected to a different power-supply, as
long as the applied voltage remains within the breakdown capability of the waveform generator (30V). In this
way, the square-wave output will be TIL compatible
-Vee
I
RA
A,
RL
$WFfP
VOL lAGE
nn
1
V'v
XR-lI038
10
12
'lk
""
L....---4>-----4-----o - v 0'
GND
Figure 4. Connections for Frequency Modulation (a) and Sweep (b).
1-216
XR·8038A
Precision Waveform Generator
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-8038A is a precision waveform generator IC capable of producing sine, square, triangular, sawtooth,
and pulse waveforms, with a minimum number of external components and adjustments. The 8038A allows
the elimination of the external distortion adjusting resistor which greatly improves the temperature drift of distortion, as well as lowering external parts count. Its operating frequency can be selected over nine decades
of frequency, from 0.001 Hz to 1 MHz, by the choice of
external R-C components. The frequency of oscillation
is highly stable over a wide range of temperature and
supply voltage changes. The frequency control, the
sweep, and the modulation can be accomplished with
an external control voltage, without affecting the quality of the output waveforms. Each of the three basic
waveform outputs, (i.e., sine, triangle and square) are
simultaneously available from independent output terminals.
SINE ADJ
M
r
DUTY CYCLE
AoJ
L
FM BIAS
ORDERING INFORMATION
Part Number
Package
Operating Temperature
The XR-8038A monolithic waveform generator uses advanced processing technology and Schottky-barrier diodes to enhance its frequency performance. It can be
readily interfaced with a monolithic phase-detector circuit, such as the XR-2228 to form stable phase-locked
circuits.
.
XR-8038AM
XR-8038AN
XR-8038AP
XR-8038ACN
XR-8038ACP
Ceramic
Ceramic
Plastic
Ceramic
PlastiC
-55°C to +125°C
O°C to + 70°C
O°C to +70°C
O°C to + 70°C
O°C to +70°C
FEATURES
The XR-8038A precision waveform generator produces
highly stable and sweepable square, triangle, and sine
waves across nine frequency decades. The XR-8038A
is an advanced version of the XR-8038, with improved
sine distortion temperature drift. The device time base
employs resistors and a capacitor for frequency and
duty cycle determination. The generator contains dual
comparators, a flip-flop driving a switch, current
sources, a buffer amplifier, and a sine wave convertor.
Three identical frequency outputs are simultaneously
available. Supply voltage can range from 10V to 30V, or
± 5V to ± 15V with dual supplies.
SYSTEM DESCRIPTION
Low Frequency Drift
50 ppm/oC, Typical
Simultaneous Sine, Triangle, and Square Wave Outputs
THD 1 %
Low Distortion
High FM and Triangle Linearity
0.001 Hz to 1 MHz, Typical
Wide Frequency Range
Variable Duty Cycle
2% to 98%
Low Distortion Variation with Temperature
APPLICATIONS
Precision Waveform Generation
Sweep and FM Generation
Tone Generation
Instrumentation and Test Equipment Design
Precision PLL Design
Unadjusted sine wave distortion is typically less than
0.7% with the sine wave distortion adjust pin (Pin 1)
open. Distortion levels may be improved by including a
100k!] potentiometer between the supplies, with the
wiper connected to Pin 1.
ABSOLUTE MAXIMUM RATINGS
Frequency sweeping or FM is accomplished by applying modulation to Pins 7 and 8 for small deviations, or
only Pin 8 for large shifts. Sweep range typically exceed 1000:1.
36V
Power Supply
Power Dissipation (package limitation)
750 mW
Ceramic Package
6.0 mW/oC
Derate Above + 25°C
625 mW
Plastic Package
5 mW/oC
Derate Above + 25°C
Storage Temperature Range
-65°C to + 150°C
The square wave output is an open collector transistor;
output amplitude swing closely approaches the supply
voltage. Triangle output amplitude is typically 1/3 of the
supply, and sine wave output reaches 0.22VS.
1-217
XR·8038A
ELECTRICAL CHARACTERISTICS
= ± 5V to ± 15V, TA = 25·C, RL
unless otherwise specified.
Tast Conditions: Vs
= 1 MO,
XR-B03BAM
PARAMETERS
MIN
TYP
RA
= RB = 10 kO,
C1
= 3300 pF,
S1 closed,
XR-B03BAC
MAX MIN
TYP
MAX
UNITS
12
30
±15
20
V
V
mA
CONDITIONS
GENERAL CHARACTERISTICS
Supply Voltage, Vs
Single Supply
Dual Supplies
Supply Current
10
±5
12
30
±15
15
10
±5
Vs
=
±10V (Note 1)
FREQUENCY CHARACTERISTICSjMaasurad at Pin 9
Range of Adjustment
Max. Operating Frequency
Lowest Practical Frequency
Max. FM Sweep Frequency
FM Sweep Range
FM Linearity
Range of Timing Resistors
Temperature Stability
XR-8038AM
XR-8038AC
Power Supply Stability
1
1
MHz
0.001
0.001
Hz
100
1000:1
0.1
100
1000:1
0.2
kHz
0.5
50
1000
0.5
100
-
1000
-
-
20
0.05
0.05
%
kO
RA = RB = 5000,
C1 = 0, RL = 15 kO
RA = RB = 1 MO,
C1 = 500 "F
S1 Open (Note 2 & 3)
S1 Open (Note 3)
Values of RA and RB
ppm/·C TA = -55·C to + 125·C
ppm/·C TA = O·C to + 70·C
%N (Note 4)
OUTPUT CHARACTERISTICS
Square-Wave
Amplitude
Saturation Voltage
Rise Time
Fall Time
Duty Cycle Adjustment
Triangle/Sawtooth/Ramp
Amplitude
Linearity
Output Impedance
Sine-Wave Amplitude
Distortion
Unadjusted
Adjusted
ATHD/AT
0.9
0.98
0.2
100
40
0.9
0.4
2
0.3
0.2
98
0.7
0.5
0.5
0.2
1.5
Nota 1: Currents through RA ad RB not included.
Nota 2: Vs = 20V, f = 10 kHz, RA = RB = 10kll.
Note 3: Apply sweep voltage at Pin 8.
2/3 Vs
2
0.3
0.33
0.05
200
0.22
s Vsweep s VSN.
Nota 4: 10V s Vs s 30Vor ±5V s Vs s ±15V.
Nota 5: Pin 12 open circuited (No 81 kll resistor as
standard 8038).
Nota 6: Triangle duty cycle set to 50%, use RA and
RB·
1-218
0.98
0.2
100
40
0.5
98
0.33
0.1
200
0.22
0.8
0.5
0.3
x Vs
V
nsec
nsec
%
x Vs
%
x Vs
3
%
%
%
Measured at Pin 9
RL = 100 kO
Isink = 2 mA
RL = 4.7 kO
RL = 4.7 kO
Measured at Pin 3
RL = 100 kO
lout = 5 mA
RL = 100 kll
RL
RL
= 1 Mil (Note 5 & 6)
= 1 Mil (Note 5 & 6)
Multipliers/Modulators
XR·2208
Operational Multiplier
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-2208 operational multiplier combines a fourquadrant analog multiplier (or modulator), a high frequency buffer amplifier, and an operational amplifier in
a monolithic circuit that is ideally suited for both analog
computation and communications signal processing
application. As shown in the functional block diagram,
for maximum versatility the multiplier and operational
amplifier sections are not internally connected. They
can be interconnected, with a minimum number of external components, to perform arithmetic computation,
such as multiplication, division, square-root extraction.
The operational amplifier can also function as a preamplifier for low-level input signals, or as a post detection amplifier for synchronous demodulator applications. For signal processing, the high frequency buffer
amplifier output is available at pin 15. This multiplier/
buffer amplifier combination extends the small signal
3-db bandwidth to 8-MHz and the transconductance
bandwidth to 100 MHz.
V·
MULTIPLIER
OUTPUTS
HIGH FREO.
OUTPUT
L
1
OPAMP
X
INPUT
INPUTS
J
COMMON
y
INPUT
COMPo
r
l
QPAMP
OUTPUT
Y·CAIN
V-
X-GAIN
ABSOLUTE MAXIMUM RATINGS
The XR-2208 operates over a wide range of supply voltages, ± 4.5V to ± 16V. Current and voltage levels are
internally regulated to provide excellent power supply
rejection and temperature stability. The XR-2208 operates over a O°C to 70°C temperature range. The XR2208M is specified for operation over the military temperature range of - 55°C to + 125°C.
Power Supply V +
+ 18 Volts
-18 Volts
V-
Power Dissipation
Ceramic Package
Derate above +25°C
Plastic Package
Derate above +25°C
Storage Temperature Range
FEATURES
750mW
6mW/oC
625 mW
5 mW/oC
-65°C to +150°C
Maximum Versatility
Independent Multiplier, Op Amp, and Buffer
Excellent Linearity (0.3 % typ.)
Wide Bandwidth
3 dB BW.-8 MHz typo
3° Phase Shift BW.-1.2 MHz typo
Transconductance B.W.-100 MHz typo
Simplified Offset Adjustments
Wide Supply Voltage Range (± 4.5V to ± 16V)
ORDERING INFORMATION
APPLICATIONS
SYSTEM DESCRIPTION
Triangle-to-Sinewave
Analog Computation
Converter
Multiplication
AGC Amplifier
Division
Phase Detector
Squaring
Phase-Locked Loop (PLL)
Square-Root
Signal Processing
Applications
AM Generation
Motor Speed Control
Frequency Doubling
Precision PLL
Carrier Detection
Frequency Translation
Synchronous AM Detection Phase-Locked AM
Demodulation
The XR-2228 multiplier/detector contains a four quadrant multiplier and a fully independent operational amplifier. The four quadrant multiplier has fully differential
X and Y inputs and outputs. Both inputs have 3 MHz dynamic response and 100 MHz transconductance bandwidth. The operational amplifier features high gain and
a large common mode range. The device is powered by
4.5V to 16V split supplies.
Part Number
XR-2208M
XR-2208N
XR-2208P
XR-2208CN
XR-2208CP
Package
Ceramic
Ceramic
Plastic
Ceramic
Plastic
Operating Temperature
- 55°C to + 125°C
O°C to + 70°C
O°C to + 70°C
O°C to + 70°C
O°C to + 70°C
For higher frequency applications, consider the XR2208.
1-219
XR·2208
ELECTRICAL CHARACTERISTICS
Tast Conditions: Supply Voltage
=
± 15V, TA
= 25·C, unless otherwise specified.
XR-220BI
XR-220BM
PARAMETERS
MIN
XR-220BC
TYP
MAX MIN
TYP
4
±16 ±4.5
7
5
CONDITIONS
MAX UNITS FIGURES
I. GENERAL
Supply Voltage
Supply Current
±4.5
±16
8
Vdc
mA
2
See Figure 11
Measured at Pin 16
II. MULTIPLIER SECTION
Non·linearity
(Output Error
in % of Full Scale)
Feedthrough
a) With Offset Adj.
X-input
V-input
b) No Offset Adj.
X-input
Y-input
Temperature Coefficient of Scale
Factor
Input Bias Current
X, Y input
Common input
Input Resistance
Output Offset Voltage
Avg. Temp. Drift
Dynamic Response
3-dB Bandwidth
X-input
Y-input
3° Phase-Shift Bandwdith
1 % Absolute Error Bandwidth
Transconductance Bandwidth
Output Impedance
No external ollset trim
0.5
0.5
1.0
0.5
0.5
0.8
1.0
1.0
45
60
80
100
70
90
120 mVp-p
150 mVp-p
120
120
±0.07
0.5
%
%
%
0.3
0.3
0.7
200
200
±0.07
3
Vx = 20 Vp-p ".:;, = 0
Vy = 20 Vp-p, x = 0
mVp-p
mVp-p
Vx = 20 Vp-p, Vx = 0
Vy = 20 Vp-p, Vx = 0
TLOW :S TA :S THIGH (Note 1)
%/OC
2
4
1.0
6
12
3
6
1.0
8
16
p.A
p.A
Mil
2
2
2
50
0.5
80
80
0.5
140
mV
mV/oC
2
5
6
3
8
4
1.2
30
100
6
6
3
Vy = ±10V, -10V < Vx < +10V
Vx = ±10V, -10V < V~ < +10V
TLOW :S TA :S THIGH ( ate 1)
f = 50 Hz
13,15 of Figure 2
14 of Figure 2
Measured looking into Pin 3 or
Pin 5
Measured across Pins 1 and 2
TLOW :S TA :S THIGH
See Definition Section
8
4
1.2
30
100
6
MHz
MHz
MHz
kHz
MHz
200
1.0
II
5
Measured looking into Pin 15
mV
6
RS < 5011
TLOW :S TA :S THIGH
IB1- IB2
IBI + IB2
kIl
Measured looking into Pins 1 or 2
III. BUFFER AMPLIFIER
Output Impedance
Gain
200
1.0
IV. OPERATIONAL AMPLIFIER
Input Offset Voltage
Temperature Coefficient of Input
Offset Voltage
Input Offset Current
Input Bias Current
Voltage Gain
Differential Input Resistance
Output Voltage Swing
Input Common
Mode Range
Common Mode Rejection
Output Resistance
Slew Rate
Power Supply Sensitivity
70
0.5
±10
+12
-10
70
1
6
3
20
9
6
30
",V/oC
4
75
10
100
nA
6
30
200
50
300
75
3
±12
+14
-12
90
2
0.5
2
70
±10
+12
-10
70
30
Note 1: TLOW = -55·C, THIGH = +125°CforXR-2208M
75
3
±12
+14
-12
90
2
0.5
30
nA
6
dB
Mil
V
6
6
V
dB
kll
V/",s
6
6
6
7
",VN
6
2
RL O!: 2K, Va = ±10V, 1= 20 Hz
RL O!: 2K, TLOW :S TA :S THIGH
f = 20 Hz
Gain = 1, RL O!: 2K CL :S 100 pF
CC=20pF
RS :S 10K
TLOW = O°C, THIGH = + 70°C for XR-2208IXR-2208C
CAUTION: When using only the op amp or only the multiplier section of the XR-2208, the input terminals to the unused
section must be grounded. Thus, when using the multiplier section alone, ground pins 13 and 14; when using
the op amp section alone, ground pins 3, 4 and 5.
1-220
XR·2208
Vo
10pF
6189
"
13
"
.'SV
SII(
Figure 1. Test Circuit for Quiescent Supply Current,
Multiplier Input Bias and Output Offset Voltage.
SII(
Figure 4. Test Circuit for Multiplier Small-Signal Bandwidth
for X-Input (For Y-Input, reverse connections
between Pin 3 and 5).
Kit :n08
>---;-"<>-T--T-"""-oVo
'.,
'.
'"
Figure 2. Linearity Test Circuit
Figure 5. Test Circuit for Op Amp DC Parameters
Figure 3. Test Circuit for Feedthrough Measurement.
X-Input Feedthrough = Vz with S1, open, S2 closed.
Y-Input Feedthrough = Vz with S1, closed, S2 open.
Figure 6. Op Amp AC Test Circuit
plier with scale factor K can be written as:
DEFINITION OF MULTIPLIER TERMS
Vz = K[(Vx + I/>x) (Vy + I/>y)] + 1/>0
NONLINEARITY: Nonlinearity is the maximum deviation
of the output voltage from a straight-line transfer function. It is measured separately for the X and Y inputs
and is specified as (%) of full scale output.
where I/>x and I/>y are the offset voltages associated with
the respective inputs, 1/>0 is the offset voltage of the output, Vz is the multiplier output, Vx and Vy are the multiplier inputs. As shown in Figures 13 and 14, each of
these offset voltages can be nulled to zero by external
adjustments.
FEEDTHROUGH: The amount of peak-to· peak output volt·
age present with one input grounded and a specified
peak·to-peak input applied to the other input. Feedthrough is a function of multiplier offsets and can be
minimized by offset adjustment (see Figure 13).
SCALE FACTOR, K: The constant of proportionality that
relates the multiplier output to the X and Y inputs. If the
offset terms are neglected, the multiplier output, Vz, is
related to the X and Y inputs as Vz = K(Vx'Vy), The
scale factor K has the dimensions of (volts) -1 and can
be adjusted externally.
OFFSET VOLTAGES: A four-quadrant analog multiplier has
three separate offsets: the X and Y input offsets and the
output offset. The transfer function of a practical multi1·221
XR·2208
TYPICAL CHARACTERISTIC CURVES
I. ,.---r---r----r---_,
5mAr-----~·------r-----_,
1.00
1 'mA
..--,---r--,---,.--,---,.--,
•. ,. t--t----1---r---t--t--t-;
:;"
a~
3mA
·-1. t----t---
.... t--t----1~-t--t--r--t--;
2m.
-2.
0.25
>
~
r-- _-"-+_1--+-"'1\
•.
.•
-~~,~~,~~-~,.~--~,OO=---~,~
FREaUENCY IMHzI
SUPPLY VOLTAGE, VOLTS
TA' AMBIENT TEMPERATURE IQCI
Figure 8. Small·Slgnal Frequency
Response for the Multiplier Section.
(Output Measured at Pin 15-See
Fig. 4).
Figure 7. Supply Current vs Supply
Voltage
Figure 9. Temperature Dependence of
Output Nonlinearity for X or Y Inputs
(See Figure 2).
,15 , - - - - - - , - - - - - - - , . - - - - ,
100
'1' ••
".
~
e
A,"SonJcao . . . .
j
.s
~
"~
50
I
!
-,
~
R,"'SOOU CC "Z.5PF
~
~
5
I!:
~
e
40
g 20
<
~
-12
·8
-10
'12
'14
-I.
-15
··1. '---~-'-_'---'--'-_'--'--'
'16
•
suprl Y VOLTAGE., VOL f5
Figure 10. Multiplier Input Dynamic
Range vs Power Supply
ee'·.
80
'5V
"OV
SUPPLY VOL rAGE, VOLTS
'1SV
R,
~. r--~
~
~5K C~"5PF
Rl.~.CCI"20PF
l00Hl
I
1kHz
"
'\
10kHz
100kHz
lMlU
FREQUENcV
Figure 12. Dp Amp Frequency
Response
Figure 11. Dp Amp Output Swing vs
Power Supply
In most arithmetic applications the multiplier and op
amp sections of the XR-220B are interconnected as
shown in Figure 14. In such applications, over-all scale
factor K can be written as:
K = (Km)(Ka) =
(~)
VxYy
'.
(Vz)
Vo
l!OHSn
""
where Km is the gain constant of the multiplier section,
and Ka is the gain of the op amp stage in Figure 14, Vo
is the multiplier output across pins 1 and 2, and Vz is
the op amp output at pin 11. With reference to Figure
14, these gain constants can be expressed as:
Km
=<
~(volts)-l;
RxRy
,
Figure 13. Offset Adjustment
MULTIPLIER BANDWIDTH: Depending on the particular
application, a different definition of "multiplier bandwidth" may be used. The most commonly accepted
definitions are:
Rf
Ka=-6 + Ri
a) 3-dB Bandwidth: Frequency where the multiplier
output is 3-dS below its low frequency (f = 20 Hz)
level.
where all resistors are in kO.
Thus, overall scale factor K can be adjusted by varying
Rx , Ry, Rf. For fine adjustment of the scale factor, K, an
additional potentiometer can be included into the circuit, as shown in Figure 14.
b) 30 Phase Shift Bandwidth: Frequency where the net
phase shift across the multiplier is equal to 30 ..
c) 1% Absolute Error Bandwidth: Frequency where
the phase vector error between the actual and ideal
output vectors is equal to 1 %. This frequency is
reached when the net phase shift across the multiplier is equal to 0.01 radian or 0.57".
INPUT DYNAMIC RANGE: The maximum peak signal
which can be applied to the X or Y inputs for a given
supply voltage without impairing linearity. (See Figure
10).
1-222
XR·2208
DP AMP INPUTS (PINS 13 AND 14)
d) Transconductance Bandwidth: Frequency where
the transconductance of the multiplier drops 3-d8
below its low frequency value. This bandwidth defines the frequency range of operation for phasedetector and synchronous AM detector applications.
DESCRIPTION OF CIRCUIT CONTROLS
Pin 13 is the non-inverting and pin 14 the inverting inputs for the op amp section. In most multiplier applications, these terminals are connected to the multiplier
outputs (pins 1 and 2). Note: When the op amp section is not
used, these terminals should be grounded.
MULTIPLIER INPUTS (PINS 3, 4, AND 5)
DP AMP COMPENSATION (PIN 12)
The X and Y inputs to the multiplier are applied to pins 3
and 5 respectively. The third input (pin 4) is common to
both X and Y portions of the multiplier, and in most applications serves as a "reference" or ground terminal.
The typical bias current at the multiplier inputs is 3 p.A
for the X- and Y- inputs and 6 /LA for the "common" terminal. In circuit applications such as "synchronous AM
detection" or "frequency doubling" where the same input signal is applied to both X and Y inputs, pin 4 can be
used as the input terminal since it is common to both X
and Y sections of the multiplier.
The op amp section can be compensated for unconditional stability with a 20 pF capacitor connected between pin 12 and pin 11. For op amp voltage gains
greater than unity, this compensation capacitance can
be reduced to improve slew rate and small Signal bandwidth as shown in Figure 12.
OP AMP OUTPUT (PIN 11)
This terminal serves as the output for the op amp section. It is internally protected against accidental short
circuit conditions, and can sink or source 10 mA of current into a resistive load. In most multiplier applications,
pin 11 is the actual XR-2208 output, with the op amp inputs being connected to the multiplier outputs.
MULTIPLIER OUTPUTS (PINS 1 AND 2)
The differential output voltage, Yo, across these terminals is proportional to the linear product of voltages Vx
and Vy applied to the inputs. Vo can be expressed as:
Vo
BUFFER AMPLIFIER OUTPUT (PIN 15)
The buffer amp is internally connected to the multiplier
section. The buffer amp has unity voltage gain, and provides a low-impedance output at pin 15 for the multiplier section. The buffer amp is particularly useful for high
frequency operation since it minimizes the capacitive
loading effects at the multiplier outputs.
~ (R~!) (VXVy)
where all voltages are in volts and the resistors are in
kO. Rx and Ry are the gain control resistors for X and Y
sections of tile multiplier.
The buffer amplifier is activated by connecting a load
resistor, R1, from pin 15 to ground. When it is not used,
pin 15 can be left open circuited. However, since the
buffer amplifier output is a low impedance point, reasonable care should be taken to avoid burnout due to
accidental short circuits. The maximum dc current
drawn from pin 15 should be limited to 10 mA. The dc
voltage at pin 15 is typically 4.5 volts below V + .
The common-mode dc potential at the multiplier outputs is approximately 3 volts below the positive supply.
One of the multiplier outputs (pin 1) is internally connected to the unity-gain buffer amplifier input for highfrequency applications.
In most analog computation operations, such as multiplication, division, etc., pins 1 and 2 are dc coupled to
the op amp inputs (pins 13 and 14). The final output, Vz ,
is then obtained from the op amp output at pin 11, as
shown in Figure 14.
APPLICATIONS INFORMATION
PART I: ARITHMETIC OPERATIONS
X AND Y GAIN ADJUST (PINS 6, 7, 8, 9)
Multiplication
The gains of the X and Y sections of the multiplier are
inversely proportional to resistors Rx and Ry connected
across the respective gain terminals. Ttie multiplier
conversion gain, Km , can be expressed as:
Km = ~
RxRy
For most multiplication applications, the multiplier and
op amp sections are interconnected as shown in Figure
15 to provide a single-ended analog output with a wide
dynamic range. The circuit of Figure 14 provides a linear output swing of 10V for maximum input signals of
10V, with a scale factor K = 0.1. The trimming procedure for the circuit is as follows:
(volts)-1
where Rx and Ry are in kO.
1. Apply OV to both inputs and adjust the output offset
to OV using the output offset control.
X AND Y OFFSET ADJUST (PINS 7 AND 8)
Two of the gain-control terminals, pins 7 and 8, are also
used for adjusting X and Y offsets. Figure 13 shows the
typical adjustment circuitry which can be connected to
these pins to nUll-out input offsets.
2. Apply 20V pop at 50 Hz to the X-input and OV to the
Y-input. Trim the Y-offset adjust for minimum peak-topeak output.
1-223
XR·2208
Dividing Circuit
3. Apply 20V p-p to the Y-input and OV to the X-input.
Trim X-offset adjust for minimum peak-to-peak output.
Recommended circuit connection for performing analog division is shown in Figure 16. This circuit uses the
multiplier if'] the feedback path of the op amp. For the
circuit shown, Vo = + 10 VzlVx where Vx < 0 and Vz
can have either sign. Positive values of Vx are not allowed, since this will reverse the polarity of the feedback loop, causing positive feedback and latchup.
4. Repeat step 1.
5. Apply + 10V to both inputs and adjust scale factor
for Vo = + 10V. This step may be repeated with different amplitudes and polarities of input voltages to
optimize accuracy over the entire range of input
voltages, or over any specific portion of input voltage range.
This latchup mode is nondestructive to the XR-220B,
and is common to all analog division circuits. The divide
circuit is trimmed as follows:
Squaring Circuit
1. Apply Vz = 0 and trim the output offset adjustment
for constant output voltage as Vx is varied from -W
to -10V.
The recommended circuit connection for squaring applications is shown in Figure 15. This circuit is the same
as the basic multiplier circuit with both inputs tied together, except only one input offset adjustment is necessary. Trimming procedure for the squaring circuit is
as follows:
2. Keeping Vz = 0, and applying Vx
V-offset adjust until Vo = O.
=
-10V, trim the
1. Apply 0 volts to the input and adjust the output offset
to zero.
3. Let Vz = Vx and/or Vz = - Vx and trim the X-offset
adjustment for constant output voltage as Vx is varied from -1V to -10V.
2. Apply 1.0V to the input and adjust the y-ciffset until
Vo = 0.10V.
4. Repeat steps 1 and 2 if step 3 required a large initial
adjustment.
3. Apply 10V to the input and adjust the scale factor
until Vo = + 10V.
5. Keeping Vz = Vx, adjust the scale factor trim for Vo
- 10V as Vx is varied from -1V to - 10V.
4. Apply -1 OV to the input and check that Vo = + 10V.
If not, repeat steps 1 through 3. Some compromise
may be necessary in scale factor adjustments given
in steps 3 and 4.
Figure 16. Dividing Circuit
Square Root Circuit
This is essentially the dividing circuit with the X input
tied to the output. Thus, the voltage on the Z input is divided by the output voltage, i.e. the output is proportional to the square root of the input. A diode is included in
series with the output to prevent a latchup condition
which would result if Vz were allowed to go negative.
The square root circuit may be trimmed as a divider by
disconnecting the X-input from the output, keeping Vz
> 0 and Vx < O. The square root circuit may also be
trimmed in the closed-loop mode by the following procedure:
Figure 14. Multiplication Circuit
'.
v
~
OFFSET
"DJ
'i'"
1. Apply Vz = + 0.1 OV and trim the output offset adjust
for Vo = - 0.316V.
."
<'!II(
lOOK
2. Apply Vz = +0.9V and trim the X-offset adjust for
Vo = -3.0V.
'"
Figure 15. Squaring Circuit
1-224
XR·2208
SYNCHRONOUS AM DETECTION
3. Apply Vz = + 10V and trim the scale factor adjust
for Vo = -10V.
Figure 18 is a typical circuit connection for synchronous AM detection for carrier frequencies up to 100
MHz. The AM input signal is applied to the multiplier
"common" terminal (pin 4). The Y-gain terminals are
shorted, and this section of the multiplier serves as a
"limiter" for input signals 2: 50 mVrms; the X-section of
the multiplier operates in its linear mode. The low-pass
filter capacitors, C1, at pins 1 and 2 are used to filter
the carrier feedthrough. If desired, the op amp section
can be used as an audio preamplifier to increase the
demodulated output amplitude.
4. Repeat steps 1 through 3 until desired accuracy is
achieved.
EQUIVALENT SCHEMATIC DIAGRAM
TRIANGLE-TO-SINEWAVE CONVERSION
A triangular input can be converted into a low distortion
(THD < 1 %) sinusoidal output with the XR-2208. A recommended connection for this application is shown in
Figure 19. The triangle input signal is applied to the
X-input (pin 3). The multiplier section rounds off the
peaks of this input and converts it to a low distortion
sine wave. For the component values shown in Figure
19, the recommended input signal level at pin 3 is ""
300 mV pp in order to obtain a 2V pp sine wave output
at pin 15. This waveform can be further amplified using
the op amp section to provide high level (10V pp), low
distortion output at pin 11.
PART II: SIGNAL PROCESSING
AM GENERATION
Figure 17 is the recommended circuit connection for
generating double side-band (DSB) or suppressed carrier AM signals. Modulation and carrier inputs are applied to the X and Y inputs respectively. The carrier level at the output can be adjusted by the dc voltage applied to pin 3. For suppressed carrier operation, the
carrier feedthrough can be further reduced by using the
X and Y offset adjustments. In this application, the
unity-gain buffer amplifier section will provide a low impedance output if desired. If the buffer amp is not used,
pin 15 should be open circuited to reduce power dissipation.
Typical carrier suppression without offset adjustment is
40 dB for frequencies up to 1 MHz, and 30 dB for frequencies up to 10 MHz. For low frequency applications
(f < 10kHz), carrier suppression can be reduced to
60 dB by using the offset adjustment controls.
OUTP\Jt
AYPUTUOl
'0'
'.
."
rv
,THO
"-1-<,..--,
0-;<--.........
~~'D .. CC
Figure 1g, Trlangle-to-Slne Converter
PHASE DETECTION
The multiplier section can be used as a phase detector.
A recommended circuit connection is shown in Figure
20. The reference input is applied to pin 5, and the input
signal whose phase is to be detected is applied to pin 3.
The differential dc voltage, Vq,' at the multiplier outputs
(pins 1 and 2) is related to the phase difference, q" between the two input signals, V1 and V2, as:
Figure 17. AM Generation
Vq, =
ix) (Vy + y)] + <1>0
where x and y are the offset voltages associated
with the respective inputs, <1>0 is the offset voltage of
the output. Vz is the multiplier output, Vx and Vy are the
multiplier inputs. As shown in Figures 13 and 14, each
of these offset voltages can be nulled to zero by external adjustments.
1-230
XR·2228
TYPICAL CHARACTERISTICS CURVES
.m.r-----r-----~----~
10
1·m.r-----t-~~~~~~
~
S
~ 3mA~~~~----+_----~
'.75
~INPUT
0.5
YIN~
!
..........
us
-20
1mA,~.V,-----±:-----+.::----.c:!"V
.
-30
-SS
0.1
SUPPLVVOLTAGE, VOLTS
FREQUENCY IMHz!
/'
.
"5
V
V V
.... V
.........
,
,~
r--..
-1.
.2
4
8
.8
10
12
14
,
6
75K
~5K
""'-
7
(
8
(
+125
g
~
R,,"SOSl,lc- o
60
I
R 1 ·!>OOU Cc -2.SPF
A , -5IC
20
R1 ....
~
~
C~-5Pf
,ccI.
I
"'-_ISV
"
20PF
""
10kHz
1 MHz
FREQUENCY
Figure 12. Op Amp Frequency
Response
Rx
AOJ
K = (Km)(Ka) =
lOOK
ADJ
+100
In most arithmetic applications the multiplier and op
amp sections of the XR·2228 are interconnected as
shown in Figure 14. In such applications, over·all scale
factor K can be written as:
9
Ry
+75
related to the X and Y inputs as Vz = K (Vx . Vy). The
scale factor K has the dimensions of (volts) -1 and can
be adjusted externally.
(~)
VxY
x
~
(Vz)
Vo
where Km is the gain constant of the multiplier section,
and Ka is the gain of the op amp stage in Figure 14. Vo
is the multiplier output across pins 1 and 16, and Vz is
the op amp output at pin 11. With reference to Figure
14, the gain constants can be expressed as:
X OFFSET
lOOK
I
~
OUTPUT SWING
X
Y OFFseT
...
PEAK-TO·PEAK
XR-2228
r'
n
~
z
Figure 11. Op Amp output Swing vs
Power Supply
Figure 10. Multiplier Input Dynamic
Range vs Power Supply
+50
R,"O,CC·O
SUPPLY VOLTAGE. VOLTS
SUPPLY VOLTAGE,VOLTS
+:25
0
:c
.sv
,16
0
100
./'
~
..........
25
Figure 9. Temperature Dependence of
Output Nonlinearity for X or
Y Inputs (See Figure 2)
/........V
./
T A' AMBIENT TEMPERATURE lOCI
Figure 8. Small-Signal Frequency
Response for the Multiplier
Section. (Output Measured
at Pin 16-Se8 Fig. 4)
Figure 7. Supply Current vs Supply
Voltage
"
•
v
Figure 13. Offset Adjustment
where \1
PHASE DETECTION
The multiplier section of the XR-2228 can be used as a
linear phase-discriminator. A recommended circuit connection for this application is shown in Figure 16. In this
case, the reference input (input 1) is applied to pin 2,
and the input signal whose phase is to be detected (input 2) is applied to pin 5. For input signal amplitudes
~ 50 mV rms, the differential output voltage, Vo across
pins 1 and 16 is directly proportional to the phase difference, q,. between the two input signals. It can be expressed as
Figure 14. Multiplication Circuit
vzo-_ _'~OO~K_ _ _ _ _ _,
24K
Vx
24K
o-t---<>:-H
>+"<;>--0
va .•
'O,,:Z
20pF
SK
~---<>-''H
Vo(q,) = 5
_ _.-l
Where
SK
-=Y - OFFSET ADJ
-15V
~
62K
is the phase difference expressed in radians.
V_·....,.._ _ _- - ,
' •• K
OUTPUT
OFFSET ADJ
-15V
·15V ~
~
q,
e: -1)
lOOK
lOOK
INP~ f--+-,"",,""f
V _ OfFSET ADJ
·15V
XR·Z228
x
Cc
Figure 15. Dividing Circuit
DIVIDING CIRCUIT
INP~f-+_..J
I'
Co
Recommended circuit connection for performing analog division is shown in Figure 15. This circuit uses the
multiplier in the feedback path of the op amp. For the
circuit shown, Vo = + 10 VzNx where Vx < 0 and Vz
can have either sign. Positive values of Vx are not allowed, since this will reverse the polarity of the feedback loop, causing positive feedback and latch up.
INPUT 1 -",-E,,,"I'"'oll
Cc •
INPUTl -\.'2-£2,.,,1..:.01+01
(;8 • B'IPASS CAPACITOR
OUTPUT 'V.I,,'·
s{lf' - 1)
Figure 16. Phase·Detector Circuit
This latchup mode is nondestructive to the XR-2228,
1-233
COUPLING CAPACITOR
o .. PHASE
DIFFERENCE IN RADIANS
XR·2228
Figure 19. The triangle input signal is applied to the
X-input (pin 2). The multiplier section rounds off the
peaks of this input and converts it to a low distortion
sine wave.
The capacitors C1 at pins 1 and 16 provide a low-pass
filter with a time constant T i< = R1 C1, where R1 = 5
kll is the international impedance level at these pins.
If needed, the phase conversion gain can be increased
by using the op amp section of the XR-2228 to further
amplify the output voltage, Vo(.p). The XR-2228 is suitable for phase detection of input frequencies up to 100
MHz.
For the component values shown in Figure 19, the recommended input signal level at pin 2 is ;;; 300 mV pp, in
order to obtain a 2V pp signal at pins 1 or 16, with RX
set at approximately 1DOll. The dc level at pin 5 can be
used for adjusting the output amplitude, or providing
amplitude modulation. The sensitivity of the output amplitude to the dc voltage level at pin 5 is inversely proportional to the external resistor across pins 6 and 7.
SYNCHRONOUS AM DETECTION
Figure 17 is a typical circuit connection for synchronous AM detection for carrier frequencies up to 100
MHz. The AM input signal is applied to the multiplier Xand Y-input terminals (pins 3 and 4) simultaneously.
If higher amplitude output signal is required, the op
amp section of XR-2228 can be used to provide additional amplification.
The V-gain terminals (pins 6 and 7) are shorted, and this
section of the multiplier serves as a "limiter" for input
signals 2:50 mVrms; the X-section of the multiplier operates in its linear mode. The low-pass filter capacitors,
C1, and at pins 1 and 16 are used to filter the carrier
feedthrough. If desired, the op amp section can be
used as an audio preamplifier to increase the demodulated output amplitude.
PHASE-LOCKED AM DETECTION
The XR-2228 can be used in conjunction with anyone
of the commercially available monolithic phase-locked
loop (PLL) IC's to provide phase-locked AM detection.
In this manner, frequency-selective detection capabilities of PLL circuits can be extended to AM signals.
.
, ."
OEMODULATED
OUTPUT
Cc
<>--1 .......---I--6-4H
AM INPUT
(,
789
V'N
Figure 17. Synchronous AM Detector
10 ' 840
PRECISION PHASE-LOCKED LOOP DESIGN
~H.
10' Co' 200 of ,nd RL
T
1 6K
Figure 18. !lrBcislon PLL
A precision phase-locked loop may be constructed using an XR-2209 voltage controlled oscillator and an
XR-2228. (See Figure 18.) Due to the excellent temperature stability and wide sweep range of the XR-2209 this
PLL circuit exhibits especially good stability of center
frequency and wide lock range. In this application the
XR-2228 serves as a phase comparator and level shilter. Resistor RL adjusts the loop gain of the PLL, thus
varying the lock range. Tracking range may be varied
from about 1.5:1 up to 12:1. For large values of RL, temperature stability of center frequency is better than 30
ppm/cC.
SINU$OIOAl
TRIANGLE
INPUT
x
v'0
V'j
'OK
OUTPUT
LEVEL
TRIANGLE-TO-SINEWAVE CONVERSION
ADJUST
v·
'OPTIONAL
AM
CONfROLI
A triangular input can be converted into a low distortion
(THO < 1 %) sinusoidal output with the XR-2228. A recommended connection for this application is shown in
VOUT
1-_ _.1-"16-0'_
.,.
,.
SOO!!
AIlJUSl
A. fOR
MIN THD
Figure 19. Triangla-to-Sinewave Converter
1-234
XR·2228
Figure 20 shows the circuit connection diagram for a
two-chip AM and FM detection system, using the
XR-215 high-frequency PLL in conjunction with the
XR-2228 multiplier/detector. Because of the highfrequency capability of the XR-215, the circuit is useful
as a phase-locked AM detector for carrier frequencies
up to 20 MHz, and operates over a supply voltage range
of 10V to 20V.
The VCO section of XR-215 does not have a separate
"quadrature" output. However, this problem can be
overcome by driving the XR-2228 multiplier directly
from the timing capacitor terminals (pins 13 and 14) of
XR-215. The V-input of the XR-2228 is operated with
maximum gain, since the V-gain control terminals (pins
6 and 7) are shorted together. This causes the triangular waveform across the timing capacitor, CO, to be converted to an effective "quadrature" drive.
Figure 20. Phase· Locked AM Detection Using XR·215
MonOlithic PLL and XR·2228 Multiplier/Detector
The V-inputs (pins 4 and 5) are driven differentially from
the VCO timing capacitor signal (available at pins 13
and 14 of the PLL IC) which is AC coupled to pins 4 and
5 of the XR-2228 multiplier input. the differential DC
voltage level at the multiplier output terminals (pins 1
and 16) is offset by means of an external resistor, RA
This initial offset causes the op amp output of the XR2228 to settle to a known state when there is no carrier
or tone Signal to be detected. With the op amp input
connections as shown in Figure 21, the op amp output
(pin 11) would be at a "low" state when the PLL is not
locked on a tone, and goes to a "high" state (i.e., near
+ VCC) when the PLL circuit is "locked" on to an input
tone. The output logic polarity can be reversed simply
by reversing the op amp inputs.
The modulated input Signal is simultaneously applied to
both circuits through coupling capacitors. The phasedetector inputs of the XR-215, as well as the multiplier
X-inputs of the XR-2228, are biased at approximated
one-half of VCC, by means of an external resistive divider.
In Figure 20, Co sets the VCO frequency of the XR-215.
In the case of FM demodulation, Rl and C1 serve as
the post-detection filter for the detected FM Signal and
RFl sets the gain of the FM post-detection amplifier.
The V-input of the XR-2228 is operated in its switching
mode, with the Y-gain terminals (pins 6 and 7) shorted
together. The AM and/or FM signal is simultaneously
applied to both circuits through coupling capacitors;
the output of the multiplier, at pin 16, is AC coupled to
the op amp section of the XR-2228, which serves as the
post-detection amplifier for the demodulated AM signal.
In the circuit, RX sets the amplifier demodulation gain,
C3 serves as the low-pass post-detection filter.
The filter capacitor, CA, connected across pins 1 and
16 of the multiplier outputs, serves as the postdetection low-pass filter. The value of CA is chosen to
provide a compromise between the response time and
the spurious noise rejection characteristics of the circuit: increasing CA improves the noise rejection characteristics of the circuit, but slows down the response
time.
A detailed description of the principle of operation of
the circuit of Figure 21 is given in Exar's Application
Note AN-12 entitled: "Designing High Frequency
Phase-Locked Loop Carrier-Detector Circuits".
A detailed description of the circuit operation, and the
design equations for calculating the external component values are given in Exar's Application Note AN-13,
entitled "Frequency Selective AM Detection using
Monolithic Phase-Locked Loops."
PHASE·LOCKED LOOP TONE DETECTION
~:::,
The XR-2228 multiplier/detector can be used in conjunction with the XR-210 or the XR-215 high-frequency
PLL circuits, to provide high-frequency tone or carrierdetect systems. The generalized circuit connection for
such an application is given in Figure 21. The circuit, as
shown, can operate with a single power supply, from
10V, to 20V, or with split supplies in the range of ± 5V to
± 10V. In the case of split power supplies, the resistor
string biasing the input terminals of the XR-2228 is not
necessary and can be eliminated by connecting node A
of Figure 21 to ground.
'"',"'
___
".
1--4-
~--t~---ll~~.,~
X" Jl~
'"I1.Il·lOCIUiOLODP
I
I
I
I
_______ -1
:J;'"
Figure 21. Recommended Circuit Connection of the XR·2228
with the XR·21D or the XR·215 High·Frequency
Phase·Locked Loops for Tone or Carrier·Detector
Application
The input signal is AC coupled, with separate coupling
capacitors, both to the input of the particular PLL circuit to be used and to the X-input terminal (pin 2) of the
XR-2228.
1-235
Display Drivers
rEX4R
XR·2271
Fluorescent Display Driver
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-2271 is a monolithic 7-digit or 7-segment display driver designed to interface MOS logic with fluorescent displays. It features active high logic and low input
current. Each XR-2271 is capable of driving seven digits
or segments of a display panel and provides complete
input and output isolation. Since the output pull up resistors are incorporated on chip, no external parts are
required to interface fluorescent displays.
INPUTS
FEATURES
Active High Logic
Low Input Current
Complete Input Output Isolation
Output Pull Up Resistors On Chip
No External Parts Required To Drive
Fluorescent Displays
APPLICATIONS
Fluorescent Display Driver
MOS Logic/High-Voltage Interface
ORDERING INFORMATION
Part Number
Package
XR-2271CN
XR-2271CP
Ceramic
Plastic
Operating Temperature
O°C to
O°C to
+ 70°C
+ 70°C
ABSOLUTE MAXIMUM RATINGS (Nota 1)
VSS - V Input to VOutputs to V ISS
Power Dissipation TA S 25°C
Derate above 25°C
Storage Temperature
SYSTEM DESCRIPTION
50V Max.
50V Max.
50V Max.
20 mA Max.
625 mW Max.
5 mW/oC
- 65°C to + 150°C
The XR-2271 fluorescent display driver requires no additional components to interface seven segment fluorescent displays to MOS Logic. The output is an emitter
follower and can switch up to 50V at 20 mAo All inputs
are protected to 50V and pull up resistors are integrated onto the device.
1-236
ELECTRICAL CHARACTERISTICS (TA
PARAMETERS
Logical "1"
Input Voltage
=
MIN
+ 25°C, VSS = OV, V-
TYP
MAX
XR·2271
- 40V, Note 2)
UNITS
SYMBOL
CONDITIONS
0
V
Vin on
Vo = -2.0V
10 = -7.5 mA
-6
V
Vin off
Vo = V- +2V
0.25
0.8
mA
lin on
Vin = -1.2V
Vo = -2.0V
-50
0
-90
50
p.A
p.A
lin off
Vo = V- +2V
Vin = -6V
Vin = -15V
-2.0
-0.9
0
V
Vo on
Vo on
Logical "0"
Output Voltage
-40
-38
V
Vo off
Vin = -6V
Output Pull
Down Resistance
45
KO
RO
Vin = -6V
Note 3
Output Pull
Down Current
350
p.A
IS
Vo = -5V
Vin = -6V
Note 3
Power Supply
Current
-1.2
-7
mA
mA
I-off
I-on
UNITS
SYMBOL
-1.2
Logical "0"
Input Voltage
Logical "1"
Input Current
Logical "0"
Input Current
Logical "1"
Output Voltage
-1.4
-12.0
All inputs - 6V
All inputs - 1.2V
AC Parameters (TA = +25°C, Test Circuit Figure 2)
PARAMETERS
MIN
Output on
Delay Time
TYP
MAX
CONDITIONS
1
5
p.S
td
CL = 25 pF
RL = 10 KO
Output on
Rise Time
0.5
2
p.S
tr
CL = 25 pi
RL = 10K
Output off
Storage Time
0.8
5
p.S
ts
CL = 25 pF
RL = 10 KO
Output off
Fall Time
0.6
2
2.0
25
p.S
p.S
tl
CL = 25 pF
RL = 10K
RL = 00
Nole 1. The "Absolute MaXimum Ratings" are those values beyond which the deVice may be damaged.
Nole 2. All voltages measured with respect to VSS unless otherwise noted. Positive current flow is into a device pin.
Nole 3. The output pull down resistance is an N channel junction FET. For Vo "" V - it is resistive, and lor IVo (V - ) I > 20V, it is current sink.
'''C'~
JV
JV
I
r-----
I
I
BV
I
ov-
-+
I'
,..,:,{. ..2-1
I'nl
I-j
t~
90"~
_____
I
~"o.: ~':
I
mHM
I
I
_______
ton
I
1(l"x.
tal!
~
"
":;-
INPUT
OUTPUT
Cl
EQUIVALENT SCHEMATIC DIAGRAM
RL
Figure 2. XR-2271 AC Parameter Test Circuit
1·237
XR·2272
High·Voltage 7· Digit Display Driver
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-2272 is a monolithic high voltage display driver
array specifically designed to drive gas-filled digit displays. The circuit is made up of seven independent digit
driver sections in the same monolithic package. Its
main application is to act as buffer interface between
MOS outputs and the anodes of a gas discharge panel.
The XR-2272 is particularly well suited to interfacing
with Panaplex II type displays.
FEATURES
Active Low Inputs
High Breakdown Voltage
Low Power Dissipation
Complete Input-Output Isolation
On-Chip Pull-Up Resistors
Versatility for Display Interface
APPLICATIONS
Gas Discharge Display Driver
Panaplex Display Driver
MOS Logic to High-Voltage Interface
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ( - VEE)
- 75V Max.
- 20 mA Max.
Output on Current Each Output
- 50 mA Max.
Output on Current All Combined
Positive Supply Current Iss
60 mA Max.
Input Current
±3 mA Max.
Input Voltage
- VEE, Min., VSS, Max.
625 mW (Plastic)
Package Power Dissipation, 25°C
Derating above 25°C
5 mW/oC
Operating Temperature Range
O°C to + 70°C
Storage Temperature Range
-65°C to 150°C
Pari Number
Package
Operating Temperature
XR-2272CN
XR-2272CP
Ceramic
Plastic
O°C to + 70°C
O°C to + 70°C
SYSTEM DESCRIPTION
The XR-2272 high voltage display driver features seven
independent sections, each capable of switching - 75
Vat up to 20 mA. Each has active low inputs and monolithic pull-up resistors. The output is an emitter follower.
1-238
XR·2272
Vss
- - --,
r-----
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
INPUT 0 - - + - - - - - - '
(9-15)
I
I
I
I TYPICAL
~..2~_?-E~VERS
_
EQUIVALENT SCHEMATIC DIAGRAM
1-239
I
J
OUTPUT
(2-8)
XR·2272
ELECTRICAL CHARACTERISTICS (TA = +25°C, VSS
PARAMETERS
MIN
TYP
Input Off Voltage
-1.8
Input Off Current
-20
Input On Voltage
Input On Current
MAX
UNITS
SYMBOL
-1.2
V
Vinoff
pA
lin off
-S
V
Yin on
-SOO
-250
-100
pA
lin on
-so
-48
V
Va off
-1.4
-0.9
0
V
Va on
Output Off Voltage
Output On Voltage
-SOY, Note 1)
= OV, V-
CONDITIONS
= -5pA
Yin = -1.2V
10 = -5 p.A
Va = -l.4V
10 = -15 mA
Va = -l.4V
10 = -15 mA
Yin = -1.2V
Yin = -SV
10 = -15 mA
Yin = -SV
10
Output Pull
Down Resistance
45
KO
RO
Output Pull
Down Current
350
pA
IS
Vo = -5V
Yin = -SV
Note 2
All inputs at - 1.2V
Supply Current
Off State
Note 2
1
150
pA
1-
One Segment On
0.35
2
mA
l-
One input at - SV
All Segments On
2.2
S
mA
I
All inputs at - SV
1
5
p.S
td
CL
RL
Output on Rise Time
0.5
2
p.S
tr
CL
RL
Output off Storage Time
0.8
5
p.S
ts
CL
RL
Output off Fpll Time
O.S
2
2.0
25
p.S
p.S
tf
CL
RL
RL
AC Parameters (TA = + 25°C, Test Circuit Figure 2)
Output on Delay Time
..
= 25 pF
= 10 KO
= 25 pF
= 10 K
= 25 pF
= 10 KO
= 25 pF
= 10K
= 00
Note 1. All voltages measured with respect to VSS unless otherwise noted. Positive current flow IS Into a device
pin.
Note 2. The output pull down resistance is an N-Channel junction FET. For Vo ,., V - it is resistive, and for IVo (V -) I > 20V, it is a current sink.
-12V
INPUT
,..---QVSS
-3\1_
I~
o--t--4
OV
OUTPUT
.j. -
! - ,.,---+--:
i
I
'0
f--j
I
-60V
40V
I
- _I
I
I-~
Figure 3. AC Test Waveforms
1-240
'F
.-l
I
I
I
i
----...,.-Figure 2. XR-2272 AC Parameter Test Circuit
-3V
"I-'-R"I'!--s-v""
I
'NPUT
7/
-- --
j - --- -
I
I
'all
1--._-_
.... -,
XR·2276
Bar Graph Display Generator
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-2276 is a 12-point logarithmic bar graph display
generator designed for interfacing with fluorescent displays. The device's twelve comparators, internally biased at logarithmic intervals about an adjustable reference, controlling twelve fluorescent drivers. The XR2276 may also drive LEDs if the maximum device
power dissipation is not exceeded.
The XR-2276 is especially suited for generating 12point bar graphs or other multi-segment fluorescent
displays, such as those used for audio level-detector or
level-indicator applications.
INPUT
OdB
·-20 dB
+8 dB
ADJUSTMENT
·15dB
-10dS
+3dB
7 dB
+1 dB
5 dB
OdB
3dB
-1 dB
OUTPUTS
OUTPUTS
GROUND
FEATURES
High Input Impedance
Internal Pull-Down Resistors
Logarithmic Display Characteristics
External Reference Level Adjustment
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-2276CP
Plastic
ODC to +70 DC
APPLICATIONS
Bar-Graph Display Generator
12-Point Display Driver
Audio Level Indicator
Channel Separation Indicator
12-Point Digital Controller
Sequential Display Generator
SYSTEM DESCRIPTION
The XR-2276 is a logarithimic level detection and fluorescent display driver. The circuit is comprised of an input buffer amplifier, 12 high gain comparators, an internal voltage reference and a bias-setting resistor string.
All of the twelve comparator stages have independent
buffered outputs.
ABSOLUTE MAXIMUM RATINGS
Power Supply
Input Signal Range
Output Current
Power Dissipation
Derate Above +25 DC
Operating Temperature
Storage Temperature
Each of the comparators have a threshold level higher
than the preceeding comparator stage. With no input
Signal, all of the comparators are "off" and all the outputs are at a low state. As the input level is increased,
the outputs successively switch to their high state. The
threshold levels are within the range of - 20 dB to + 8
dB with reference to a 0 dB level setting. The 12 ranges
are: -20dB, -15dB, -10dB, -7dB, -5dB, -3dB,
- 1 dB, 0 dB, 1 dB, 3 dB, 5 dB, and 8 dB.
24V
-lV to +10V
5 mA
625 mW
5 mW/DC
ODC to + 70 DC
- 65 DC to + 125 DC
1-241
XR·2276
ELECTRICAL CHARACTERISTICS
Test Conditions: VCC = 18 Volts, TA = 25°C, unless otherwise specified. (See Test Circuit of Figure 1)
LIMITS
TYP
MAX
UNITS
SYMBOL
Input Current
30
300
nA
liN
Output Low Voltage
0
0.5
V
VOL
RL
Measured at each output
V
VOH
RL = 15 Kn
Measured at each output
V
VOS
PARAMETERS
MIN
Output High Voltage
14.0
15.5
Input Bias Voltage
0.9
1.25
1.6
Comparator Threshold
Voltages
o dB Output
- 20 dB Output
- 15 dB Output
-10 dB Output
-7 dB Output
-5 dB Output
-3 dB Output
-1 dB Output
+ 1 dB Output
+3 dB Output
+5 dB Output
+8 dB Output
2.10
0.40
0.65
0.92
1.15
1.43
1.77
2.21
2.76
3.37
4.72
0.3
0.46
0.73
0.99
1.23
1.52
1.88
2.34
2.93
3.66
5.12
ODB
Adjust
Range
-
V
V
V
V
V
V
V
V
V
V
V
V
0.52
0.83
1.07
1.30
1.61
2.00
2.49
3.10
3.97
5.56
10K Trim Pot from pin 16
toGND
VIN = 3.35V
+1
Segments
-2
Comparator Threshold
Change with Supply
-0.6
Supply Current
13
= 7.5 Volts
= 220 Kn
Input level above VOS
necessary to change
comparator state.
Measured at pin 11 after 0
dB adjustment
Measured at pin 2
Measured at pin 3
Measured at pin 4
Measured at pin 5
Measured at pin 6
Measured at pin 7
Measured at pin 10
Measured at pin 12
Measured at pin 13
Measured at pin 14
Measured at pin 15
Vc
-
CONDITIONS
VIN
+0.6
dB
t.vC
il.VCC = 6V
RL = 15 Kn
20
mA
ICC
VIN = 7.5V
RL = 220 Kn, VCC
18V
rr
..v
_ICC
,..-----0
=
'Vee
.. v
12V
;
VOH
.v
1K!!
v,.
.-1
-ltN
i'lL
R,
---_______
•
Vo
INPUT SIGNAL LEvEL.
(al
(bl
Figure 1. Basic Test Circuit: (a) Circuit Connection, (b) Output Waveform.
1-242
vc "'
XR·2276
TYPICAL PERFORMANCE CHARACTERISTICS
OUTPUT VOLTAGE VS LOAD CURRENT
....
~
I~
W
"!:i«
g
10
....
I!::::l '
:::l
o
I
I'l"I
TURN ON TIME VS SEGMENT
TURN OFF TIME VS SEGMENT
Vee = l8V
008 ,. 3.l5V TOT AL
RL z 220K
CL ~ 22.5 of
Vee = 11'1
I
VIN"O~9V
I-...,
r-....
........ i-
-
~
,/
~
f-.po.~,......-+-.....,-+--+--+--+--+ ~~ ;:~,:v TOTAL
Cl~22.5pF
•
~
~
z
/
"- r-....
I
V
j ,
t'-...
1
II:
'
.
VIN=O~I\I
1'.............
, f-+-+-+-f-f-f-f-HH--I--I--I
~
SEGMENT
IL (mol
SEGMENT
APPLICATION INFORMATION
plate segments that are to remain constantly on are
tied to the V + line. All other plate connections are
switched by either the XR-2276 or some other means
(i.e., a selective switch for a Dolby symbol, etc.). The
o db point is adjusted for each device by the 10K pot
from pin 16 to ground.
Vacuum Fluorescent Displays: Vacuum fluorescent displays operate like vacuum tubes. The display consists
of a filament, a grid and several plates. Each segment
on the bar graph and the other symbols, reference numbers, etc., are plates coated with fluorescent material.
As with a vacuum tube, when the plate is at a potential
lower than that of the grid, no plate current flows and
the segment associated with that plate is cut off. When
the plate is at the same potential as the grid, electrons
flow from the filament to the plate, striking the fluorescent material, thus, causing it to glow. Most of the new
low voltage vacuum fluorescent displays operate with a
plate voltage of about 16V-18V, a filament voltage of 3V
rms and a filament current of about 100 mao
Design Example: Design a gain scaling and peak detector
circuit to drive the circuit in Figure 2, to yield an audio
level indicator with 0 db referenced to 1 mw into 6000.
The circuit should have an input impedance of 100 kO,
respond to frequencies from 50 Hz to 15 kHz, have an
output dc offset of 1.25V to bias the input of the
XR-2276 and operate from a single 16V supply. This circuit is shown in Figure 3.
XR-2276 Detailed Description: The XR-2276 contains an input buffer amplifier, a bias network and 12 comparators. The input buffer amplifier, pin I, must be biased at
approximately + 1.25V under quiescent conditions. The
signal is then applied in addition to this bias voltage.
The full scale calibration of the XR-2276 can be fine
tuned by varying the bias voltage slightly.
The buffer amplifier is a high input impedance unity
gain amplifier that applies the input voltage to one input
of each of the twelve comparators.
The bias network consists of a voltage reference and a
string of weighted resistors Which provide the threshold
voltages for the twelve comparators. The reference
voltage is adjustable by connecting a 10K trimpot from
pin 16 to ground. This feature allows a precise setting
of the 0 db point.
Figure 2. 2 Channel Display
Calculate the component values for the gain scaling
stage.
The rms voltage that corresponds to 1 mw in 6000 is:
Since decibels are ratios with respect to a reference
value, the threshold voltages determined by the resistor
string may not correspond to the desired reference. In
this case it will be necessary to scale the input signal
with either gain or attenuation to obtain the desired correspondence (see the design examples below).
v'PR =
.../(1 mwX6000} = .774 Vrms
Therefore
Vpeak
The comparators have a high open loop gain, NPN output transistors with 220K resistors connected from the
emitters to the ground terminal, pin 8, and a 1.5K resistor in series with the output.
= (1.414}(.774}V rms =
1.095V
The dc input voltage to the XR-2276 that gives a 0 db indication is 2.1 Ov.
The gain required is 2.10/1.095 = 1.92. For a noninverting amplifier gain = 1 + RF/RS. If we choose,
Applications Circuits: Figure 2 shows a typical connection
for a two channel display. Note that the grid and any
RF
1-243
= 22K Then
RS
= 22K/.92 = 24K
XR·2276
A1 = A2 = 200K to bias the input at V + 12 and yield an
input impedance of 100K.
The gain for the input amplifier would have to be
Gain = (2.10)/1.735 = 1.21
C1 = 1/211"(50 Hz)(100K) '" .033/LF
As/Af = .21 for non inverting amplifier
C2 = 1/211"(50 Hz)(24K) '" .15 /LF
if
The input impedance to the peak detector is:
47K H 100K '" 32K
As
C3 = 1/211"(50 Hz)(32K) ;: 0.1 /LF
Af = 24K
'" 5.1K
= (24K)(.21)
Driving LED's with the XR-2276: LED's can be driven by
the XR·2276 provided care is taken not to exceed the
maximum power dissipation of the device. This can be
accomplished in two ways. First, the cathodes of the
display device can be multiplexed such that the total
current sourced by the XR-2276 at anyone time, does
not cause excessive power to be dissipated. An alter·
nate method is to drive an external pass device, such
as an XA-2203, which in turn drives the LED's. In this
way the power dissipation is moved off of the XR-2276.
The peak detector circuit provides full wave rectifica·
tion of the incoming audio signal. A1 serves an inverting unity gain peak detector giving a positive output for
the negative half cycle of the incoming signal. A2
serves as a unity gain non-inverting peak detector giv·
ing a positive output for the positive half cycle of the in·
coming signal. 03 and 04 serve as rectifier diodes and
01 and 02 keep the feedback loops on A1 and A2, respectively, closed during the amplifiers non·rectifying
half cycle. A5 and A7 set the closed loop gain of A1 at
unity. A8 and A7 together with C5 provide a filter for the
peak detector output. C5 can be adjusted to provide the
desired damping. A4, R6, C4, 05 and 06 prevent the input of A2 from being pulled below ground by the large
negative transients. A9 ' A10 and C6 establish the 1.25
volt (adjustable by RlO) dc bias for the XA2276 input.
The operational amplifier chosen to be used in this circuit is the XR-3403. It has adequate ac performance
and is ideally suited to single supply operation, since its
common mode input voltage range includes ground.
DeSign Example: How many LED's can be driven simultaneously without exceeding the maximum power dissi·
pation of 625 mw? VCC = + 18V, TA = 25°C.
The 1.5K resistor in series with the output can be as
high as 3K and the no load output high voltage of the
XA·2276 should be "'VCC - 1V. If the forward voltage
on an LED is "" 1.7V, the current typically available to
drive the LED would be:
(18V - 1V - 1.7V)/1.5K
= 10.2 ma
(5.1 ma if the series resistor = 3K)
The total voltage across each output would be 16.3V.
The total power dissipated per segment is:
Po
= (16.3V)(10.2 mal =
166 mw
The quiescent dissipation of the device
PDq = (lsupply max)(Vsupply)
or
(20ma)(18V) = 360 mw
The total number of segments that can be on at once is:
Figure 3. Peak Detector
625 mw - 360 mw/166 mwlsegment ",,1 Segment
The circuit in Figure 4 shows an acceptable method for
using the XR·2276 in conjunction with LED's.
Design Example: Design a vu indicator. The circuit above
could be used to make a vu indicator with a slight adjustment in the circuit gain. Since 0 vu is 4 dB above
1 mw into 600D:
DeSign Example: How can 12 LED's be driven simultane·
ously at 20 ma without causing excessive power dissipation in the XA-2276:
4 dB = 20 10g(0 vu)/1.095
This can be done easily using two XR·2203's to drive
the LED's as shown in Figure 7. The current through the
LED's is limited by the series resistors.
(10)1/5(1.095)V = 0 vu
o vu
= 1.735Vpea k
1-244
XR·2276
-{>o-
=1/7 XR·2203
-{>o-
-1/7 XR·2203
Figure 4. Multiplexed Display
Figure 5. Continuous Display
I~
AOJlJSTM£ lilT
1_
r-
.1._.
IIIIHRIIIAL_I'_ IIIIPIJT -----i_-COMPAHATOH
BIAS
HUFF I H
-I
1110 1
---,
_f-COMPAHATOH
1110 12
EQUIVALENT SCHEMATIC DIAGRAM
1-245
---0_..1...- -
llliTEHIliAl
fUGUlATOH
-----j
y~~
I":
-=vAR
XR·2277/2278
·~1
Dot and Bar Graph Display Generators
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-2277 and XR-2278 are 12 point level detector
circuits designed for direct interfacing to light emitting
diode (LED) mOVing-dot or bar-graph displays. Each of
the circuits is comprised of an input buffer amplifier
and 12 comparators, biased from a resistor string at
logarithmic intervals. Accuracy is enhanced by an internal reference. Each comparator provides a high impedance current source output which are all very
closely matched and simultaneously adjustable with a
single external resistor. A control signal applied to the
mode select pin determines whether the display is driven in a moving-dot or bar-graph format.
FEATURES
High Impedance Buffered Input
Direct LED Interface
Constant Current Outputs
External Dot/Bar Mode Select
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-2277P
XR-2278P
Plastic
Plastic
DOC to +7DoC
DOC to + 7DoC
SYSTEM DESCRIPTION
APPLICATIONS
The XR-2277 and XR-2278 are 12 point logarithmic level detectors and LED drivers. LED driving current is
provided by on board adjustable current sinks; no series limiting resistors are required. All LEOs receive
matched currents, ensuring equal brightness. The drivers can be programmed to source up to 22 mA.
Bar-Graph Display Generator/Driver
Moving-dot Display Driver
Sequential Display Indicator
Audio Level Indicator
The LED current is set by a resistor from Pin 2 to
Ground. The zero dB reference is set by varying the bias on Pin 3. The output may be either moving dot (one
segment only) or bar mode (all segments up to the measured value illuminated). This is determined by Pin 18.
The XR-2277 provides 12 discrete outputs for an input
level range of - 3D dB to + 6 dB, referenced to an internally set zero dB level which is typically D.2 VRMS. The
XR-2278 has similar electrical charcteristics, providing
a - 2D dB to + 8 dB input dynamic range referenced to
D.13 VRMS. Both parts operate from a nominal 12V
supply.
ABSOLUTE MAXIMUM RATINGS
Power Supply
Power Dissipation
Derate Above 25°C
Operating Temperature Range
Storage Temperature Range
15V
625 mW
5 mW/oC
DOC to + 7DoC
- 65°C to + 15DoC
1-246
ELECTRICAL CHARACTERISTICS vee
XR·2277/2278
= 12 Volts, TA = 25°C, unless otherwise specified. (See Test Circuit of Figure 2.)
XR-2277
PARAMETERS
Supply Voltage
XR-2278
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
10
12
14
10
12
14
VDC
VF(LED)
5
10
5
10
rnA
VIN
22
rnA
R2 Varied
See Figure 4
Supply Current
LED Current
22
LED Current
12
15
ILED Matching between Outputs
-1.5
Input Voltage for 0 dB Output
0.10
0.20
Input Current
Outputs
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
18
12
+1.5
-1.5
0.25
0.09
15
0.13
50
1 (pin 17)
2 (pin 16)
3 (pin 15)
4 (pin 14)
5 (pin 13)
6 (pin 12)
7 (pin 11)
8 (pin 10)
9 (pin 8)
10 (pin 7)
11 (pin 6)
12 (pin 5)
-31.5
-25.0
-21.5
-18.5
-15.5
-11.0
-8.0
-5.0
+2.0
+4.5
18
rnA
R2
+1.5
rnA
R2
0.18
VRMS
50
-28.5
-30.0
-27.0
-24.0
-20.0
-17.0
-14.0
-10.0
-7.0
-4.0
0
+3.0
+6.0
-23.0
-18.5
-15.5
-12.5
-9.0
-6.0
-3.0
+0.5
+2.0
+4.0
+6.5
+4.0
+7.5
=2V
=0V
= 27 KO
= 27 KO
o dB Output Threshold
nA
20.0
-15.0
-10.0
-7.0
-5.0
-3.0
-1.0
0
+1.0
+3.0
+5.0
+8.0
-16.5
-11.5
-8.0
-6.0
-4.0
-1.5
CONDITIONS
-13.5
-8.5
-6.0
-4.0
-2.0
-0.5
+1.5
+4.0
+6.0
+9.5
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
See Note 1
See Note 2
NOTES:
1. Calibration adjustment for XR-2277: An
setting, and R1 is adjusted until Output
2. Calibration adjustment for XR-2278: An
setting, and R1 is adjusted until Output
input voltage, VIN, is applied at - 27 dB level, referenced to zero dB
2 (Pin 16) turns on.
input voltage, VIN, is applied at - 20 dB level, referenced to zero dB
1 (Pin 17) turns on.
Vee
--------------
RL
OUTPUT
0---.
1
-
ICC
?~
C,
o-L
~ ILED
17
15
16
14
13
12
11
10
7
8
9
XR-2277/XR-2278
2
3
5
4
6
I
R3
R,
RL
!IIN
RL
-------
A4
r
~
RZ
lis
~~C2
GND
Figure 2. Generalized Test Circuit
1·247
RL
R1
R2
R3
R4
Rs
C1
C2
= soon
= 27Kll
= 330KH
= 10KH
= 10KH
= 2.2~F
= 10~F
RL = 200H
XR·2277/2278
OUTPUTS
OUTPUT
CURRENT ADJ.
r-----------------------~A~------------------------~
17
16
15
14
13
12
11
20-----,
GROUND
9
EQUIVALENT SCHEMATIC DIAGRAM
1·248
10
8
6
5
XR·2277/2278
PRINCIPLES OF OPERATION
As shown in the equivalent circuit schematic of Figure
1, each circuit is comprised of 12 voltage comparators
with current source outputs. One input in each of the
comparators is connected to a common voltage line.
The input voltage, VIN, is applied to this signal line
through a buffer amplifier. The remaining input of each
of the comparators is biased from an internal resistor
ladder connected to a voltage reference on the IC chip.
Thus, each of the 12 ladder taps corresponds to the
particular output thresholds, listed as outputs one
through twelve, in the electrical characteristics.
shows the available output drive current, ILED' as a
function of R2.
Response Adjustment
Transient response of the circuit is adjusted by an external resistor, R5, and capacitor, C2, connected from Pin
4 to ground. Typical component values for audio frequency applications, from 20 Hz to 20 kHz, are: R5 =
10 kO and C2 = 10 p.F. The internal impedance at Pin 4
is approximately 100 ohms. C2 functions as a holding
capacitor of the internal peak rectifier circuit, with R5
controlling its decay time.
As the input voltage applied to the device is increased,
each of the 12 comparators in the chip changes state
sequentially at the time the input signal levels reach
their respective threshold levels. The current source
outputs of these comparators can directly drive LED
displays. The circuit can operate both in moving-dot or
bar-graph display format.
Scale Adjustment
The output thresholds for the XR-2277or the XR-2278
are measured relative to an internal zero dB reference
level. Thus, for a given input signal dynamic range,
each circuit must be calibrated with respect to the zero
dB reference level setting. This calibration is performed
by adjusting the potentiometer, R1, shown in Figure 2.
The scale adjustment is performed with an audio frequency ac signal applied to the circuit.
Figure 3 shows the typical output current waveforms
for operating in either the moving-dot or the bar-graph
modes. The mode of operation is selected by the logic
state at Pin 18. If this pin is grounded, the output display is in the moving-dot format where only one of the
current outputs is active at anyone time, depending on
the input signal level.
XR-2277
Step 1: Determine exact value of input voltage to produce zero dB output. This is done by increasing the ac
input signal amplitude until Output 10 (Pin 7) begins
conduction.
If Pin 18 is left an open circuit, then the IC operates as
a bar-graph display generator. In this mode of operation, the external LEDs are connected in series, in
groups of four to minimize power dissipation.
Step 2: Reduce input voltage level to - 27 dB referenced to the input level of Step 1. Adjust R1 until Output
1 (Pin 16) begins conduction.
The outputs of the comparators (4), (8), and (12), continue conducting in this manner as long as the voltage
level is above in respective threshold pOints.
XR-2278
EXTERNAL ADJUSTMENTS
Output Brightness Adjustment
Step 1: Determine exact value of input voltage to produce zero dB output. Do this by increasing ac input signal level until Output 8 (Pin 10) begins conduction.
The output current level for each of the 12 outputs is
controlled by an external current setting resistor, R2,
(R2 ~ 20 kO) connected from Pin 2 to Ground, Figure 4
Step 2: Reduce input voltage level by - 20dB referenced to its zero dB level. Adjust R1 until Output 1 (Pin
17) beings conduction .
V~2
--
.
---------
r'\.
'" I':..
II
112
INPUT SIONAL lEVEL.
YJN
1'2
ON
"
ON
"
ON
"'" I'--.... ......I"-..
.=;
(8)LlJllUoIILYRISINQINPUTSlQNAL
........ 1'--..
--
------------
..
(b) OUTPUT CURIII!JmI IN MOYING-OO'T MODI!
Figure 3. Typical Output Waveforms in Moving-Dot Display
Mode
2S
30
:IS
RzINKIl
.0
<5
Figure 4. Output Drive Current as a Function of Current
Setting Resistor, R2
1-249
10
XR·2277/2278
APPLICATIONS
Vee
MOVING-DOT DISPLAY
Figure 5 shows the basic connection of the XR-2277, or
the XR-2278, as a moving-dot display generator and
driver. In this mode of operation Pin 18 is connected to
ground. Increasing the voltage at the input will cause
each one of the 12 LEOs to turn on, one at a time, at the
appropriate input level, and thus generate a moving dot
of light. Output waveforms for this mode are shown in
Figure 3(b).
AI
17K
Rs
+Cz
'~F
10k
BAR-GRAPH DISPLAY
*R, • 50011 • CALIBRATION POTEtmOMETEA.
Figure S shows the basic circuit connection for the XR2277, or the XR-2278, as a bar-graph display generator
and driver. Note that in this mode of operation the 12
LEOs are connected in series in three groups of four
LEOs, and the mode-select terminal (Pin 18) is left an
open circuit. Each LED will turn on and stay on as the
input signal amplitude is increased as long as the input
voltage stays above the threshold level corresponding
to that particular output.
Figure 5_ ClrcuH Connection for Moving-Dot Display
Generation
Vee
AUDIO LEVEL INDICATOR
Figure 7 shows a complete audio level indicator system
made up of either the XR-2277 or the XR-2278 Display
Generator and an adjustable gain amplifier. For a given
dynamic range of the input audio voltage, VA, the potentiometer RS is used to set the gain of the input amplifier which is adjusted to give the desired zero dB output
level from the display generator IC. The potentiometer
R1 is then adjusted to set the lowest output level; i.e.,
the - 27 dB level for the XR-2277 or the - 20 dB level
for the XR-2278. The display output format can be either the moving-dot or the bar-graph type, by choosing
the LED interconnections and the logic Signal applied
to Pin 18.
.....R.
c~'- 5-'W'o-n----'
v~I--.-f-....:=-J
•
e.
'0,.'
-A, .50011 = CAUBRATION POTENTIOMETER.
Figure 6. CircuH Connection for Bar-Graph Display
Generation
v c c o - - - - - - - - - _ . . . - - - -.....- -...... - - - - - - - - - - - - - -
IS
10Kli
14
13
12
11
10
XR-2277/XR-2278
9
AUDIO INPUT
+
VA o----t,.....-'V\IIr-~W\..-t---__I
10"F
7.SK!!
10Kl!
RS
10K!!
AI = V, OF XR-082
• Rl = CALIBRATION POTENTIOMETER.
Figura 7. Typical Audio Lavel Indicator System Using the XR-2277/XR-227B.
1-250
- -- --
XR·2279
Dot and Bar-Graph Display Generators
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-2279 is a 12 point logarithmic dot or bar-graph
generator/LED driver. The device compares an input
signal with an adjustable reference and graphically displays the results. Since LED driving current is provided
by on board adjustable current sources, no current limiting resistors are required. A special feature of the XR2279 is the four highest outputs sink one half the current of the lower eight; this allows equivalent brightness with red and green mixed displays.
Dot or bar mode selection is provided. The twelve output levels are in 3 dB steps from - 27 dB to + 6 dB. The
reference point is externally adjustable.
FEATURES
Direct LED Interface
Constant Three dB/Step Logarithmic Scale
External Dot/Bar Mode Select for Dot/Bar-Graph
Formats
Adjustable Output Current Levels
Current Source Outputs
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-2279CP
Plastic
O°C to + 70°C
SYSTEM DESCRIPTION
The XR-2279 is a 12 point logarithmic level detector circuit designed for direct interfacing to light emitting diode (LED) moving-dot or bar-graph displays. The circuit
is comprised of an input buffer amplifier and 12 comparators which are biased from an internal voltage reference. Each comparator provides a high impedance
current source output which are all very closely
matched and simultaneously adjustable with a single
external resistor. A control signal applied to the mode
select Pin 18 determines whether the display is driven
in a moving-dot or bar-graph format.
APPLICATIONS
Bar Graph Display Generator
Moving-dot Display Generator
Logarithmic Level Indicator
Sequential Level Indicator
The circuit provides 12 discrete outputs for an input
level range of - 27 dB to + 6 dB, referenced to an internally set zero dB level, typically 0.2 VRMS. Each step
represents 3 dB, and the reference level is adjustable.
ABSOLUTE MAXIMUM RATINGS
Power Supply
Power Dissipation
Derate Above 25°C
Operating Temperature Range
Storage Temperature Range
The upper four outputs, 9-12 (see Equivalent Schematic
Diagram), are internally set to provide one-half the current out as outputs 1-8. This is for driving red LEOs (as
over-range indicators) which require less current than
other colors.
15V
625 mW
5 mW/oC
O°C to + 75°C
- 65°C to + 150°C
1-251
XR·2279
ELECTRICAL CHARACTERISTICS
Tast Conditions: VCC
= 12 Volts, TA = 25°C, unless otherwise specified. (See Test Circuit of Figure 2.)
XR-2279
PARAMETERS
Supply Voltage
MIN
TYP
MAX
UNITS
10
12
14
5
10
VDC
mA
Supply Current
Output Current
Outputs 1 through 8
Outputs 9 through 12
12
6
Output Current Matching
Outputs 1 through 8
Outputs 9 through 12
-2.0
-1.0
15
8
Maximum Drive Current
Outputs 1 through 8
Outputs 9 through 12
Input Voltage for 0 dB Output
0.10
Input Current
Outputs
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
0.20
-25.5
-22.5
-19.5
-16.5
-13.5
-10.5
-7.0
-4.0
+2.0
+4.5
-27
-24.0
-21.0
-18.0
-15.0
-12.0
-9.0
-6.0
-3.0
0
+3.0
+6.0
VIN
= 2V
= OV
18
10
mA
rnA
R2 = 27KO
Measured at Pins 10 through 17
Measured at Pins 5 through 8
+2.0
+1.0
mA
mA
R2 = 27KO
Measured at Pins 10 through 17
Measured at Pins 5 through 8
22
11
mA
mA
R2 varied· see Figure 4
Measured at Pins 10 through 17
Measured at Pins 5 through 8
0.25
VRMS
nA
50
1 (Pin 7)
2 (Pin 16)
3 (Pin 15)
4 (Pin 14)
5 (Pin 13)
6 (Pin 12)
7 (Pin 11)
8 (Pin 10)
9 (Pin 5)
10 (Pin 6)
11 (Pin 7)
12 (Pin 8)
CONDITIONS
VF(LED)
-22.5
-19.5
-16.5
-13.5
-10.5
-7.5
-5.0
-2.0
+4.0
+7.5
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
o dB Output Threshold
Measured at Pin 3
See Note 1
See Note 1
Nota 1:
Determine exact value of input voltage to produce zero dB output. This is done by increasing the ac input signal
amplitude until Output 10 (Pin 6) begins conduction.
Reduce input voltage level to - 27 dB referenced to the input level of Note 1. Adjust R1 until Output 1 (Pin 17)
begins conduction.
EQUIVALENT SCHEMATIC DIAGRAM
0UT1'UTS
OUTPIIT
r -__----------------JA~------------------,
CURRENT ADJ.
1-252
XR·2279
"L
_____________
~
V'2
ilL
..
OI.fTPOT()--
+llEO
In
A1 = 50011
~ ':
'"
"
"
'" 0-1.
"
.
" " " " " " "
~".zl79
)
I
I
".
•
$
•
7
•
i!~ ~t------·t·,
·ft,·
:'/
R2 '"
R3 =
A4'"
AS '"
C1 =
CI
27KlI
330KII
fOKn
1QKn
2.2J-lF
~~
!;;~
:9
:.0
C2 = lOJlF
AL = 200n
0'"
uffi
a:
~
V2
V,
Figure 2. Generalized Test Circuit
INPUT SIGNAL LEVEL. VIN
(0) LINEARLY RISING INPUT SIGNAL
PRINCIPLES OF OPERATION
112
ON
OFF
As shown in the equivalent circuit schematic, the circuit is comprised of 12 voltage comparators with current source outputs. One input in each of the comparators is connected to a common voltage line. The input
voltage, VIN, is applied to this signal line through a
buffer amplifier. The remaining input of each of the
comparators is biased from an internal resistor ladder
connected to a voltage reference on the IC chip. Thus,
each of the 12 ladder taps corresponds to the particular output thresholds, listed as outputs one through
twelve, in the electrical characteristics.
12
~---------......
ON
OFF
I,
ON
OFF
~~~--------------
(b) OUTPUT CURRENTS IN MOVING·DOT MODE
Figure 3. Typical Output Waveforms In Moving-Dol Display
Mode
As the input voltage applied to the device is increased,
each of the 12 comparators in the chip changes state
sequentially at the time the input signal levels reach
their respective threshold levels. The output currents of
the last four outputs (Pins 5 through 8) are set at onehalf the current output of the first eight outputs. This is
done to minimize power dissipation since the last four
outputs normally drive red LEOs to indicate "overrange" condition. The red LEOs are normally more efficient than other colors and require approximately onehalf as much current for the same brightness.
EXTERNAL ADJUSTMENTS
Output Brightness Adjustment
The output current level for each of the 12 outputs is
controlled by an external current setting resistor, R2,
(R2 2: 20 kO) connected from Pin 2 to Ground. Figure 4
shows the available output drive current, ILEO, as a
function of R2 .
..
Figure 3 shows the typical output current waveforms
for operating in the moving-dot mode. The mode of operation is selected by the logic state at Pin 18. If this pin
is grounded, the output display is in the moving-dot format where only one of the current outputs is active at
anyone time, depending on the input signal level (see
Figure 3(b)).
I\.
"-
11
~
r 0.;,:,:••
~
/ o.::':Ugh 12 " t--..
~
If Pin 18 is left an open circuit, then the IC operates as
a bar-graph display generator. In this mode of operation, the external LEOs are connected in series, in
groups of four to minimize power dissipation.
..
The outputs of the comparators, (4), (8), and (12), continue conducting in this manner as long as the voltage
level is above the respective threshold points.
o.
........
--- --- 30
................
.. .
50
Figure 4. Output Drive Current as a Function of Current
Setting Resistor, R2
1-253
XR·2279
Response Adjustment
Vee
Transient response of the circuit is adjusted by an external resistor, R5, and capacitor, C2, connected from Pin
4 to ground. Typical component values for audio frequency applications, from 20 Hz to 20 kHz, are: R5 =
10 kO and C2 = 10 /LF. The internal impedance at Pin 4
is approximately 100 ohms. C2 functions as a holding
capacitor of the internal peak rectifier circuit, with R5
controlling its decay time.
••
.30.
e~":>_~~---,
Scale Adjustment
vo,i1.l--",.-+--=-'
The output thresholds for the XR-2279 are measured
relative to an internal zero dB reference level. Thus, for
a given input signal dynamic range, each circuit must
be calibrated with respect to the zero dB reference level setting. This calibration is performed by adjusting the
potentiometer, R1, shown in Figure 2, with an audio frequency ac signal applied to the circuit in two steps, as
follows:
Figure 6. Circuit Connection for Bar-Graph Display
Generation
IORt •
soon. CALl8RATlOH POTEN11OIIETER.
will turn on and stay on as the input signal amplitude is
increased as long as the input voltage stays above the
threshold level corresponding to that particular output.
Step 1: Determine exact value of input voltage to produce zero dB output. This is done by increasing the ac
input signal amplitude until Output 10 (Pin 7) begins
conduction.
AUDIO LEVEL INDICATOR
Figure 7 shows a complete audio level indicator system
made up of the XR-2279 Display Generator and an adjustable gain amplifier. For a given dynamic range of
the input audio voltage, VA, the potentiometer Re is
used to set the gain of the input amplifier which is adjusted to give the desired zero dB output level from the
display generator IC. The potentiometer R1 is then adjusted to set the lowest output level; i.e .. the - 27 dB
level. The display output format can be either the
moving-dot or the bar-graph type, by choosing the LED
interconnections and the logic signal applied to Pin 18.
Step 2: Reduce input voltage level to - 27 dB referenced to the input level of Step 1. Adjust R1 until Output
1 (Pin 7) begins conduction.
Vee
BAR-GRAPH DISPLAY
VIN C,
~.H---t-'---=-J 1.,
:17K
.5
10K
+
Figure e shows the basic circuit connection for the XR2279 as a bar-graph display generator and driver. Note
that in this mode of operation the 12 LEOs are connected in series in three groups of four LEOs, and the modeselect terminal (Pin 18) is left an open circuit. Each LED
e,
10,.F
GND
'''~-----'----r----''-------------------.
Figure 5. Circuit Connection for Moving-Dot Display
Generation
"
MOVING-DOT DISPLAY
Figure 5 shows the basic connection of the XR-2279 as
a moving-dot display generator and driver. In this mode
of operation pin 18 is connected to ground. Increasing
the voltage at the input will cause each one of the 12
LEOs to turn on, one at a time, at the appropriate input
level, and thus generate a moving dot of light. Output
waveforms for this mode are shown in Figure 3(b).
AUrH°v7~f.r;"1:""~t:'::~~rH~-I-J
"1 " V.OfllR-\1e2
°Al
~C"'UBR"'TXlNPOTENTlOIfETE".
Figura 7. Typical Audio Level Indicator System
USing the XR-2279.
1-254
XR·2284/2288
High-Voltage AC Plasma Display Drivers
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAMS
The XR-2284 and the XR-2288 are high voltage display
driver arrays especially designed for interfacing with ac
plasma display systems. The XR-2284 contains four independent driver channels, whereas its dual version,
the XR-2288, contains eight driver channels. Each driver array can be used for either the segment or the column (or digit) drive, and several arrays can be
"stacked" together to drive a large number of display
segments.
NC
NC
:>O-::---l!.!l
l
OUTPUTS
J
TOGGlE
INPUT
All four channels of the XR-2284 are driven by a common ac toggle voltage; however, the XR-2288 has two
independent toggle inputs, one for each of the four
channels in the IC. The XR-2284 and the XR-2288 are
designed for 360 volt ac plasma systems and have minimum stand-off voltages of 90 volts. The XR-2284C and
the XR-2288C are designed for 240 volt plasma systems, and have minimum stand-off voltages of 60 volts.
NC
The circuits can operate with ac toggle frequencies up
to 200 kHz, and each driver channel can sink or source
100 mA of capacitive load current. For proper operation, the substrate terminals of all drivers must be
grounded through an external disconnect diode, DX, as
shown in the schematic diagram.
FEATURES
High Stand-off Voltage
90 V minimum for XR-2284IXR-2288
60 V minimum for XR-2284C/XR-2288C
Very Low AC Standby Power
(= 25 mW/channel at 100 kHz)
Zero DC Standby Power
100 mA Output Drive Capability
TIL and CMOS Compatible Inputs
Digital or Segment Drive Capability
Power Dissipation
XR-2284P/XR-2284CP
XR-2288P/XR-2288CP
Derate above + 25°C
Storage Temperature
APPLICATIONS
High Voltage AC Plasma Panels
High Voltage Pulsed Displays
Pulsed AC Switching
625 mW
900mW
5 mW/oC
-65°C to 150°C
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Part Number
Package
Toggle Input Voltage
XR-2284PIXR-2288P
XR-2284CP/XR-2288CP
XR-2284P
XR-2284CP
XR-2288P
XR-2288CP
Plastic
Plastic
Plastic
Plastic
±90V peak
±60B peak
1-255
Operating Temperature
O°C
O°C
O°C
O°C
to
to
to
to
70°C
70°C
70°C
70°C
XR·2284/2288
ELECTRICAL CHARACTERISTICS
Test Conditions: Test Circuit of Figure 1, with external diode DX
= IN4002 or equivalent, TA = 25°C, unless otherwise
specified. (See operating precautions.)
XR·2284/XR·2288
XR·2284C/XR·2288C
MIN
TYP
MAX UNIT
MAX MIN
TYP
PARAMETERS
Maximum Toggle Voltage
±90
Output Current Capability
Max Sourcing Current
100
150
100
Max Sinking Current
100
120
100
±60
SYMBOL
CONDITIONS
Peak-to-peak
ACvoltageSee Figure 3.
V pp
VT
120
mA
Isource
120
mA
Isink
12% Duty Cycle
12% Duty Cycle
See Figure 4.
Output Voltage
High Output)
(selected)
High Output
(non-selected)
Low output
(VT-4)
(VT-4)
4V
4V
200
High-Level Input
2
Low-Level Input
Input Current
Switching Characteristics
Rise Delay
Fall Delay
(selected)
Fall Delay
(non-selected)
1.4
VOHS
VOHN
(-VT+2)
~peak
VOL
100
200
kHz
fT
2
1.4
(-VT+2)
Maximum Toggle
Frequency
~peak
V
VIH
1.2
0.8
1.2
0.8
V
VIL
8
16
8
16
mA
liN
See Figure 3.
See Figure 4.
500
500
500
500
nsec
nsec
trd
tfds
500
500
nsec
tfdn
IMPORTANT OPERATING PRECAUTIONS
nel does not exceed 100 mA. This can be done by limiting the slewrate of toggle voltage to:
1. External diode DX with reverse breakdown voltage
~ VT must be included in all circuit applications. This
diode decouples or "floats" the IC from the circuit
ground during the negative excursions of the toggle
voltage, VT.
( dVT) max
dt
~ 100 mA,
CL
where CL is the total load capacitance, including the
capacitance of the display elements, driven by the particular output.
2. the rise and fall times of toggle voltages, Vr, must be
held to a value such that output current of each chan-
....
+Vy
TOGGLE ov
INPUT
10%
/
/
-Vy
(+Yy-4,
gn~;J'T ~
,
1<'%
=
(-VT+2
I\,
L I
-
I-
-
I-
Trd ~~,i.~~ Tfdl
Figure 2. Typical Timing Waveforms
Figure 1. Generalized Test Circuit
1-256
/
-
...
XR·2284/2288
-4-++1~~ ~I++H+~~ ~f+r--+VT
ov U
U] UUU
FUNDAMENTALS OF AC PLASMA DISPLAYS
Ac plasma display offer significant advantages over
other alpha-numeric displays such as fluorescent or
LEO type panels. Some of these advantages are the
low cost of the display itself, its wide viewing angle, and
the ease of formatting in the selection of display segments and digits. Plasma systems typically require high
voltage (200V or higher) ac drivers operating at relatively high frequencies (100 kHz and up). Although the
plasma display panel is a capacitive load and does not
draw dc current, the display driver output is required to
provide a high output drive current (typically 50 to 100
mAl, during the rising and the falling edges of the toggle
voltage, so that the driver output can still follow the ac
toggle voltage at high frequencies.
_. I
_Vy
(01 Toggle
.0"-
VIN~
ov------------~---------
VO~=+YT
ov
The ac plasma displays normally require a net voltage
in excess of 200 volts across the display to turn it on. In
practice, this is achieved by "pulsing" the display with
two out-of-phase toggle voltages (VT), such that a net
peak-to-peak voltage of 2VT appears across the selected display portion to make it turn on. Thus, in controlling the plasma display, one must control the amplitude
of two peak-to-peak toggle swings, one on the
"segment-side" and the other on the "digit-side" of the
display, where each toggle swing is equal to only onehalf of the total voltage swing needed to light up the display. For example, for 240 volt ac plasma display systems, the toggle voltage used (VT) would be 120 volts;
and for 360 volt display systems, 180 volt toggle voltage
will be needed.
I
=
-VT
DE-AcnVATED
CHANNEL
(e) Chennel output vott.oe. VOUT
Figure 3_ Timing Diagram of Circuit Waveforms
pearing across the entire plasma panel.
CIRCUIT DESCRIPTION
Both the XR-2284 and the XR-2288 are multichannel
driver circuits, packaged in 14 and 20-pin dual-in-line IC
packages respectively. The XR-2284 is a four-channel
display driver, whereas the XR-2288 is an eight-channel
circuit, made up of two four-channel driver chips in the
same dual-in-line package. Thus, the XR-2288 has two
toggle voltage and substrate inputs; one for each of the
two four-channel IC chips sharing the same package.
PRINCIPLES OF OPERATION
The XR-2284 and the XR-2288 ac plasma display driver
circuits control the drive voltage applied to the segment
or the digit section of an ac plasma panel.
The equivalent circuit diagram for a typical driver channel is shown in the schematic. All the channels have
their own independent inputs and outputs, but share a
common toggle or clock input and a common substrate
or ground connection. The circuit is designed as a series connection of two controlled-switches, or SCR's.
The transistors, 03 and 02, form one of the controlledswitches, and 01 and 04, form the second controlledswitch. The internal junction capacitance, Cj, causes
Figure 3 shows the timing waveforms associated with
the ac plasma driver circuit, for the case of a 360 volt
display system (i.e., VT = ± 90V = 180V pp). In normal
operation, all of the driver channels are driven by a
common ac toggle voltage (VT) shown in Figure 3(a).
When the control input to a driver channel, Vin, is at
"high" state, as shown in Figure 3(b), its output would
be clamped nearly to ground and would follow the negative excursions of the toggle voltage, VT. This produces only 1/2 of the required peak-to-peak voltage
across the particular display segment, which is not
enough to light it. However, if Vin is at a "low" state, the
driver output, Vout, would be enabled and follow close!y
the peak-to-peak excursions of the toggle voltage. This
would then cause the nearly full peak-to-peak swing of
the ac drive to appear across the selected display segment.
COMMON TO
COIIIION TO
ALLQAlVEAS
It should be noted that due to the external blocking diode Ox of Figure 1, the monolithic IC substrate is completely decoupled from ground during the negative excursion of the toggle voltage and the internal diode, 02,
of the schematic diagram causes the output to follow
the toggle voltage within one diode drop. In this manner, the IC has to withstand only one-half of the total ac
signal swing, or the one-fourth of the total voltage ap-
C_TO
AU. DRtVEAS
AL1: DAtVER!
COIIIIOH TO
AUDRlYIERS
:.,
"
Figure 4. Generalized Connection Diagram XR-2284 and
XR-2288.
1-257
XR·2284/2288
the respective controlled-switches to be turned on during the positive and negative edges of the toggle input,
VI-
I
I
I I-I I I I I
I. I I. I I. I I.
An external diode, Ox with a brekdown voltage 2!:: VT, is
used to "float" the substrate or decouple it from ground
during the negative excursions of the toggle voltage.
This external decoupling diode is common to all channels, and can serve more than one IC package, as
shown in Figure 4. In this manner, many driver IC's, either of the four-channel (XR-2284) or the eight-channel
(XR-2288) type, can be "stacked" to drive a large number of display segments or columns, with only one common blocking diode and a common toggle input, as
shown in the Figure 4.
.,.
COMPLEMENTARY
TOGGLE VOLTAGE
NOTE: EXTERNAL otOOE, Ox (tN4002 OR EQUIVALENT) SHOULD
BE SEPARATE FOR DIGIT AND SEGMENT $IDES
Under dc conditions, I.e., with no ac toggle drive, the
driver IC's do not diSSipate any appreciable standby
power. However, when the ac toggle voltage, VT, is applied and a particular channel is enabled, then the corresponding output can follow the peak-to-peak toggle
voltage and sink or source up to 100 mA of capacitive
load current to the plasma panel.
Figure 5.
~pical Circuit Connection for Driving 7-Segment
4-Diglt Display with Decimal Point
swing of the toggle voltage, VT, is chosen so that the firing voltage, Vf, necessary for the display to light up,
falls into the range of:
APPLICATIONS
3 VT
Driving Saven-Segment Displays
< Vf < 4 VI-
In this manner, only the selected and enabled display
cells will have an energizing voltage 2!:: Vf.
Figure 5 illustrates a four digit, seven-segment plasma
display panel with decimal point. The entire display can
be driven by one XR-2288 driver for the segment side
and one XR-2284 driver for the digit side. The segment
and the digit drivers each must have their external disconnect diode, OX, as shown in the figure. The segment and the digit sides of the display are driven by outof-phase toggle Signals, VT and Vr. which cause a total
firing voltage of four VT to appear across the enabled
display segment. Segments not enabled will have a net
voltage of three VT across them. The peak-Io-peak
Driving Alpha-Numeric Displays
Figure 6 shows the circuil connection for driving an
eight digit, 16-segment alpha-numeric display. The
number of digits can be increased by connecting additional XR-2284 or XR-2288 driver arrays into Ihe digit
side. These additional arrays can be directly "stacked"
using the same external disconnect diode, OX, and the
same toggle voltage drive lines already present on the
digit side.
EQUIVALENT SCHEMATIC DIAGRAM
/\//1 1\//1 1\/71 liV! /J7I IV/! IV/! IV/!
1l!.9 !l!J/ 1l!.9 Id\/ Idl/ Id\/ IdV 1l!.9
OUTPUT
NOTE: EXTERNAL DtODE,
DX. IS REQUIRED FOA
PROPER OPERATION.
........
COMPl.EIIENTAlilY
YOI.TAOE
'--I-----t-+-..
DX~~UIYALENT
Figure 6. Circuit Configuration for Driving 16-Sagment
Alpha-Numeric Display Panel
~
1-258
- one channel only -
XR·6118/6128
Fluorescent Display Drivers
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-6118 and the XR-6128 are high-voltage display
driver arrays which are designed to interface between
low-level digital logic and vacuum fluorescent displays.
Each circuit consists of eight independent signal channels comprised of Darlington output stages and
common-emitter type inputs. All stages on the chip
share common power supply and ground connections.
Both device types are capable of driving digits and/or
segments of fluorescent displays, and all of the eight
outputs can be activated simultaneously.
XR ...11B/28
-t>----
17
~--1>--
OUTPUTS
INPUTS
1---~t>-.----1
FEATURES
Direct Replacement for Sprague UDN-6118A,
UDN-6128A, and UDN-6118P-2 (60V)
Digit or Segment Drive Capability
Low Input Current
Integral Output Pulldown Resistors
Low Power
High Output Breakdown Voltage
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-6118P
XR-6128P
XR-6118P-2
Plastic
Plastic
Plastic
O°C to + 70°C
O°C to + 70°C
O°C to + 70°C
SYSTEM DESCRIPTION
The XR-6118 and XR-6128 fluorscent display drivers
can switch up to 85V and 40 mAo Inputs are protected
to 20V. The XR-6118 is compatible with TTL, Schottky
TTL, DTL and 5 Volt CMOS logic families. The XR-6128
is intended for use with PMOS or CMOS logic families
operating with supply voltages of 6V to 15V. The two device types differ only in their input threshold levels (See
Figure 1). With either device type, the output load is activated when the inputs are pulled toward positive supply. Output pulldown resistors are included on the die.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VBB
Output Voltage, VOUT
Input Voltage, VIN
Output Current, lOUT
Power Dissipation, (TA :s; 25°C)
Derate Above 25°C
Operating Temperature
Storage Temperature
85V
85V
20V
40 mA
1W
8 mW/oC
O°C to +85°C
- 55°C to + 150°C
1-259
XR·6118/6128
ELECTRICAL CHARACTERISTICS
Test Conditions:(TA
SYMBOL
= 25 DC, VSS = 80V) Full Temp.
PARAMETERS
ICEX
Output Leakage
Current
VOUT
Output ON Voltage
ISS(OFF)
XR-6118A
MIN TYP MAX
XR-6128A
MIN
15
15
75
75
+ 70 DC, XR-6118A only.
TYP
MAX
UNIT
15
p.A
75
CONDITIONS
VIN = 0.4 V
V
lOUT = 25 mA
VIN = 2.4 V (XR-6118)
VIN = 4 V (XR-6128)
Input On Voltage
2.4
2.4
4.0
V
lOUT = 25 mA
Input ON Current
500
550
900
p.A
VIN = 5 V (XR-6118)
VIN = 15 V (XR-6128)
Supply Current
Off Condition
225
225
On Condition
ISS(ON)
lOUT
Range ODC to
Output Pulldown
Current
225
p.A
ALL Inputs Open
8
8
8
mA
VIN = 2.4 V (XR-6118)
(ALL Inputs)
800
950
800
p.A
ALL Inputs Open
VOUT = 80 V
VBB
SEGMENT SELECT
XR...e1t8/28
dp
-----------00------------0
D.
Figure 2. Typical Multiplexed Fluorescent Display Drive Application
1-260
XR·6118/6128
+Yaa
30K
INPUT
"a·
One of Eight
Stages
OUTPUT
15 K
AIN·
IK
120 K
(*) For XA·6118
A'N = 10K, AS = 30 K
For XA·6128:
A'N = AS = 20 K
EQUIVALENT SCHEMATIC DIAGRAM
1-261
Operational Amplifiers
Fundamentals of Operational Amplifiers
The "ideal" operational amplifier can be defined as a
voltage-controlled voltage amplifier circuit which offers
infinite voltage gains with an infinite input impedance,
zero output impedance, and infinite bandwidth. The advantage of such an idealized block of gain is that one
can perform a large number of mathematical "operations", or generate a number of circuit functions by applying passive feedback around the amplifier.
The key features of operational amplifier application
can be illustrated using the simple feedback circuit of
Figure 1, and assuming that the operational amplifier
has infinite gain and infinite input impedance. Then, the
following two conditions have to be satisfied:
+ o---"...
R~S~-+----f
-o-r----+;
a) Since the voltage gain is infinite, the net voltage
across the input terminals of the operational amplifier must be zero, if the operational amplifier output
voltage is to be finite. In the circuit of Figure 1, this
causes the inverting input terminal of the operational amplifier to behave as a "virtual ground".
=
VQUT
1-
Figure 2. Basic Feedback Configuration Using an Operational
Amplifier With Finite Input Impedance and Gain
11 should be noted that, for large values of RIN, as the
voltage gain increases (I.e. A .... 00), this expression rapidly converges to that given in equation 2; and the circuit performance becomes solely determined by the external components.
b) Since the input impedance of the ideal operational
amplifier is infinite, no input current is drawn by the
operational amplifier, the total current going into the
circuit node connected to the inverting input of the
operational amplifier (node Q in Figure 1) must be
equal to the total current coming out, I.e.:
IS = -IF and VIN
RS
>-----......---"'+
VIN
In addition to having finite gain and input impedance,
an actual operational amplifier circuit also has finite input bias currents as well as input offset voltage and currents. A more complete model of a practical operational
amplifier is shown in Figure 3 where IS indicates the finite input bias currents; Vio and lio represent the voltage and current offsets associated with the circuit and
RO is the output resistance. Due to non-zero values of
Vio and lio in a practical operational amplifier circuit,
VOUT
0 for VIN = O.
(1)
Solving for the overall voltage gain, one obtains:
'*
(2)
Secause of this property, the noninverting input of
an operational amplifier is often referred to as its
"summing input".
r', ,
I
+O-JVvv---+~--~
VIN
,
-.....
!
>-----4----<:>+
J~OUT
RS
+
1
~
In the case of actual operational amplifiers, both the
voltage gain and the input impedance are quite high,
but still finite. Figure 2 shows the same basic feedback
circuit assuming that the amplifier now has a finite input resistance, RIN, and a finite voltage gain A. For simplicity, the output impedance of the operational amplifier is assumed to be negligible. The overall voltage gain
of the circuit can now be expressed as:
-.....
......
I v io",,: ;-( "lIB
- .... 1--'
Vl!
v IN
Figure 1. The "Ideal" Operational Amplifier as a Feedback
Amplifier
:-I
,,
"\~t~
! RIN
R2
I
'
'1~ 1;/0
1+
/'
I
I
~/'
/'
.....
.....
, ......
AVl ......
/'
,-, RQ,
" .I
+--
",.
,.'
+
",./
/'
",.
Vo U1'
/'
/'
Figure 3. Equivalent Circuit of a Practical Operational
Amplifier Showing the Effects of Finite Input
Impedance, Current and Voltage Offsets
1-262
-
Definitions of Operational Amplifier Terms
Output Voltage Swing: The peak output voltage swing, re-
Since the operational amplifier has become a universal
building block for circuit and system design, a number
of widely accepted design terms have evolved which
describe the comparative merits of various operational
amplifiers. Some of these terms are defined below:
ferred to zero, that can be obtained without clipping.
Large·Signal Voltage Gain: The ratio of the output voltage
swing to the change in input voltage required to drive
the output from zero to this voltage.
Input Offset Voltage: The input voltage which must be applied across the input terminals to obtain zero output
voltage.
Full·Power Bandwidth: Maximum frequency over which
the full output voltage swing can be obtained.
Input Offset Current: The difference of the currents into
the two input terminals with the output at zero volts.
Unity-Gain Bandwidth: Frequency at which the open loop
voltage gain is equal to unity.
Input Bias Current: The average of the two input cur-
Slew Rate: The maximum time rate of change of the output voltage, for a voltage step applied to the input. It is
normally measured at the zero crossing point of the
output voltage swing with the amplifier frequ~ncy compensated for unity gain.
rents.
Input Common· Mode Range: Maximum range of input voltage that can be simultaneously applied to both inputs
without causing cutoff or saturation of amplifier gain
stages.
Overload Recovery Time: Time required for the output
stage to return to active region, when driven into hard
saturation.
Common· Mode Rejection Ratio: Ratio of the differential
open-loop gain to the common-mode open-loop gain.
Gain Margin: The amount by which the voltage gain is
below the unity (0 dB) level, at the frequency where the
excess phase shift across the amplifier is exactly 180°.
It is measured in decibels, and must be positive for unconditional stability.
Supply Voltage Rejection Ratio: Input offset voltage
change per volt of supply voltage change.
Input Resistance: The ratio of the change in input voltage
to the change in input current on either input with the
other grounded.
Phase Margin: 180° minus the excess phase shift at the
Frequency where the magnitude of the open loop voltage gain is equal to unity. It is measured in degrees and
must be positive for unconditional stability.
Supply Current: The current required from the power
supply to operate the amplifier with no load and the output at zero.
1-263
Basic Applications of
Operational Amplifiers
The general usefulness of the operational amplifier
stems from the fact that when used in a feedback loop,
its overall performance and transfer characteristics are
determined almost totally by the choice of feedback
components. To be universally useful in such an application, the "ideal" operational amplifier should exhibit
infinite gain, infinite input impedance and infinite bandwidth. Although these are all idealized characteristics,
the practical monolithic operational amplifiers closely
approximate these features, particularly for low frequency applications.
the amplifier input without circuit adjustment, the
source resistance for both inputs should be equal. In
this case, the maximum offset voltage would be the algebraic sum of amplifier offset voltage and the voltage
drop across the source resistance due to offset current. Amplifier offset voltage is the predominant error
term for low source resistances, and offset current
causes the main error for high source resistances.
The availability and the low-cost of the integrated operational amplifier makes it an extremely versatile building block for analog system or equipment design.
Therefore, it is mandatory that the circuit designer be
familiar with the fundamental applications of operational amplifiers. This section of Exar's Operational Amplifier Data Book is intended to familiarize the designer with
some of the simple but fundamental circuit configurations using IC operational amplifiers. The discussion is
slanted toward the practical applications of operational
amplifiers, as controlled by the external feedback circuitry. The particular operational amplifier parameters
will be discussed as they effect the circuit performance
and accuracy.
>"'-{)VOUT
Figure 1. Inverting Amplifier
The integrated operational amplifiers shown in the figures are for the most part internally compensated, so
frequency stabilization components are not shown:
however, other amplifiers using external compensation
may be utilized to achieve greater operating speed in
many circuits.
In high source resistance applications, offset voltage at
the amplifier output may be adjusted by adjusting the
value of R3 and using the variation in voltage drop
across it as an input offset voltage trim.
The Inverting Amplifier
Offset voltage at the amplifier output is not as important
in AC coupled applications. Here the only consideration
is that any offset voltage at the output reduces the
peak-to-peak linear output swing of the amplifier.
The basic operational amplifier circuit is shown in Figure 1. This circuit gives closed-loop gain of R2/R1 when
this ratio is small compared with the amplifier openloop gain and, as the name implies, is an inverting circuit. The input impedance is equal to R1. The closedloop bandwidth is equal to the unity-gain frequency divided by one plus the closed·loop gain.
The gain-frequency characteristic of the amplifier and
its feedback network must be such that oscillation does
not occur. To meet this condition, the phase shift
through amplifier and feedback network must never ex·
ceed 180 0 for any frequency where the combined gain
of the amplifier and its feedback network is greater than
unity. In practical applications, the phase shift should
not approach 180 0 since this is the situation of conditional stability. Obviously, the most critical case occurs
when the attenuation of the feedback network is zero.
The only cautions to be observed are that R3 should be
chosen to be equal to the parallel combination of R1
and R2 to minimize the offset voltage error due to bias
current; and that there will be a DC offset voltage error
due to bias current; and that there will be a DC offset
voltage at the amplifier output equal to closed-loop gain
times the offset voltage at the amplifier input.
Amplifiers which are not internally compensated may
be used to achieve increased performance in circuits
where feedback network attenuation is high, I.e., the
amount of feedback around the amplifier is low. The
compensation trade·off for a particular connection is
stability versus bandwidth. Larger values of compensa·
tion capacitor yield greater stability and lower bandwidth and vice versa.
.
Offset voltage at the input of an operational amplifier is
comprised of two components, these components are
identified in specifying the amplifier as input offset volt·
age and input bias current. The input offset voltage is
fixed for a particular amplifier; however, the contribution due to input bias current is dependent on the circuit configuration used. For minimum offset voltage at
1-264
The Non-Inverting Amplifier
The cautions to be observed in applying this circuit are
as follows: the amplifier must be compensated for
unity-gain operation, and the output swing of the amplifier may be limited by the amplifier common-mode
range. The input signal swing should not exceed the input common-mode range, since this may cause a latchup condition.
Figure 2 shows a high input impedance non-inverting
circuit. This circuit gives a closed-loop gain equal to the
ratio of (R1 + R2) to R1. Its closed-loop 3-dB bandwidth
is equal to the amplifier unity-gain frequency divided by
the closed-loop gain.
VIN0-------I
VOUT
= vlN
Figure 3. Unity-Gain Buffer
Summing Amplifier
The summing amplifier, a special case of the inverting
amplifier, is shown in Figure 4. The circuit gives an inverted output which is equal to the weighted algebraic
sum of all three inputs. The gain of any input of this circuit is equal to the inverse ratio of the appropriate input
resistor to the feedback resistor, R4. Amplifier bandwidth may be calculated as in the inverting amplifier
shown in Figure 1 by assuming the input resistor to be
the parallel combination of R1, R2, and R3. Application
cautions are the same as those for the inverting amplifier. If an uncompensated amplifier is used, compensation is calculated on the basis of this bandwidth as is
discussed in the section describing the simple inverting
amplifier.
Figure 2. Non-Inverting Amplifier
The primary differences between this connection and
the inverting circuit are that the output is not inverted
and that the input impedance is very high and is equal
to the differential input impedance multiplied by loop
gain (open-loop gain/closed-loop gain). In DC coupled
applications, input impedance is not as important as input current and its voltage drop across the source resistance. To minimize the output error due to the input
bias current of the operational amplifier, (R1 + R2)
should be chosen equal to the source impedance of the
input signal. Applications cautions are the same for this
amplifier as for the inverting amplifier with one exception: the amplifier output will go into saturation if the input is allowed to float. This may be important if the amplifier must be switched from source to source. The
compensation trade off discussed for the inverting amplifier is also valid for this connection.
Rl
R4
V2
R2
v3
R3
VOUT
The Unity-Gain Buffer
The unity-gain buffer is shown in Figure 3. The circuit
gives the highest input impedance of any operational
amplifier circuit. Input impedance is equal to the differential input impedance multiplied by the open-loop
gain, in parallel with common mode input impedance.
The gain error of this circuit is equal to the reciprocal of
the amplifier open-loop gain or to the common-mode rejection, whichever is less. Input impedance is a misleading concept in a DC coupled unity-gain buffer. Bias
current for the amplifier will be supplied by the source
resistance and will cause an error at the amplifier input
due to its voltage drop across the source resistance.
Figure 4. Summing Amplifier
The advantage of this circuit is that there is no interaction between inputs, therefore, operations such as summing and weighted-averaging are implemented very
easily.
1-265
The Difference Amplifier
tion of two additional components, R1 and C2. R2 and
C2 form a 6 dB per octave high frequency roll-off in the
feedback network, and R1C1 form a 6 dB per octave
roll·off network in the input network for a total high frequency roll-off of 12 dB per octave, to reduce the effect
of high frequency input and amplifier noise. In addition
R1C1 and R2C2 form lead networks in the feedback
loop which, if placed below the amplifier unity-gain frequency, provide 90· phase lead to compensate the 90·
phase lag of R2C1 and prevent loop instability.
The difference amplifier is the complement of the summing amplifier and allows the subtraction of two voltages or, as a special case, the cancellation of a single
common to the two inputs. This circuit is shown in Figure 5 and is useful as a computational amplifier, in making a differential to single-ended conversion, or in rejecting an unwanted common-mode signal.
VINo---i
c,
VOUT
-
VOUT
R2
= Ai
1V2 - V,I
Figure 5. Difference Amplifier
Figure 6. Basic Differentiator Connection
Circuit bandwidth may be calculated in the same manner as for the inverting amplifier, but input impedance is
somewhat more complicated. Input impedance for the
two inputs is not necessarily equal: inverting input impedance is the same as for the inverting amplifier of
Figure 1 and the non inverting input impedance is the
sum of R3 and R4. Gain for either input is the ratio of R1
to R2 for the special case of a differential input singleended output where R1 = R3 and R2 = R4. The general expression for gain is given in the figure. Compensation should be chosen on the basis of amplifier bandwidth.
,_ ,
Care must be exercised in applying this circuit since in·
put impedances are not equal for minimum bias current
error.
c - 2nR,C,
fh
Differentiator Circuit
=-'--=-'2nR2C, 2nR2C2
Figure 7. Practical Differentlator Circuit
The basic principle of a differentiator circuit is shown in
the simplified connection diagram of Figure 6. However, although mathematically accurate, this particular
connection is not directly useful in practice because it
is extremely susceptible to high frequency noise since
AC gain increases at the rate of 6 dB per octave. In addition, the feedback network of the differentiator made
up of the resistor R3 and the capacitor C3 is an RC low
pass filter which contributes 90· phase shift to the loop
and may cause stability problems even with an amplifier which is compensated for unity-gain.
Integrator Circuit
Figure 8 shows the basic circuit connection for performing the mathematical operation of integration. This
circuit is essentially a low-pass filter with a constant
frequency roll-off of - 6 dB per octave.
The circuit must be provided with an external method of
establishing initial conditions. This is shown in the figure as the double-pole, single-throw switch 81. When
81 is in position 1, the amplifier is connected in unitygain configuration, and capaCitor C1 is discharged, setting an initial condition of zero volts. When 81 is in posi-
A practical differentiator which corrects the high frequency noise problem is shown in Figure 7. Here both
the stability and noise problems are corrected by addi1-266
tion 2, the amplifier is connected as an integrator, and
its output will be the time-integral of the input voltage.
c,
r---------,S,B
I
I
I
I
I
I
2
C,
I
I
I
VOUT
S1AI
f
_ _, _
L-2wR,C,
fC=_'-
2wR3C,
Av=-~
R,
Figure 9. A Simple Low-Pass Filter Circuil
Figura 8. The Integrator Circuit
The cautions to be observed with this circuit are two:
the amplifier used should generally be stabilized for
unity-gain operation and R2 must equal R, for minimum
error due to bias current.
60
Simple Low-Pass Filter
40
The simple low-pass filter is shown in Figure 9. This circuit has a 6 dB per octave roll-off after a closed-loop
3-dB point defined by fC. Gain below this corner frequency is defined by the ratio of R3 to R,. The circuit
may be considered as an AC integrator at frequencies
well above fC; however, the time domain response is
that of a single RC rather than an integral.
20
o
A gain vs. frequency plot of circuit response is shown in
Figure '0 to illustrate the difference between this circuit and the true integrator. Note that the frequency response is flat for frequencies below fC
where fC
R3
--100
R,
fe
-20
0-1
= --'-
""'"
10
fL
""
100
1000
Normalized Frequency, fIfe
2rR3C,
Current-to-Voltage Converter
Figure 10_ Frequency Response of the Simple Low-Pass
Filter
Current may be measured in two ways with an operational amplifier: the current may be converted into a
voltage with a resistor and then amplified or it may be
injected directly into a summing node. Converting into
voltage is undesirable for two reasons: first, an impedance is inserted into the measuring line causing an error; second, amplifier offset voltage is also amplified
with a subsequent loss of accuracy. The use of a
current-to-voltage converter avoids both of these problems.
scale factor of this circuit is R, volts per ampere of current. The only conversion error in this circuit is the bias
current of the operational amplifier input which is
summed algebraically with the input current, liN. The
main design constraints are that scale factors must be
chosen to minimize errors due to bias current and since
voltage gain and source impedance are often indeterminate (as with photocells) the amplifier must be compensated for unity-gain operation.
The current-to-voltage converter is shown in Figure ".
The input current is fed directly into the summing note,
and the amplifier output voltage changes to extract the
same current from the summing node through R,. The
1-267
~IIN
':>-.....-00+
VOUT
50K
Figure 11. Operational Amplifier as a Current-to-Voltage
Converter
v+ -VIN
IO=-R-,-
Voltage Controlled Current-Source
Figures 12, 13, and 14 show three simple circuit config·
urations for voltage·controlled constant·current stages.
The circuit of Figure 12 is a basic current·sink circuit
which uses a pair of Darlington connected NPN transis·
tors external to the operational amplifier. Assuming that
the base current of T1 is negligible compared to the
controlled current 10, the current of the output transis·
tors is equal to VIN/R1.
Figure 13. Voltage-Controlled Current-Source Circuit
Figure 14 shows an alternate approach to obtaining a
voltage·controlled current source which does not reo
quire additional active devices. The circuit provides an
output current proportional to the input voltage VIN. If
the resistors R1 through R4 are chosen to be equal and
much larger than R5, then the output current is:
The above expression assumes that the current
through R3 is much smaller than 10·
50K
R4
Figure 14. A Voltage-Controlled Current Source Circuit
Which Does Not Require External Active Devices
Figure 12. Voltage-Controlled Current-Sink Circuit
This circuit can supply an output current of either polarity, up to the maximum positive or negative output current available from the operational amplifier. The maximum voltage compliance of the output is limited by the
output swing of the operational amplifier minus the voltage drop across the sensing resistor, R5.
Figure 13 shows a current·source circuit which uses a
composite connection of external PNP and NPN tran·
sistors and produces a constant output current which is
proportional to the net voltage drop across the sensing
resistor, R1.
1-268
Triangle Wave Oscillator
state until the voltage at its input again reverses. The
complete circuit operation may be understood byexamining the operation with the output of the threshold detector in the positive state. The detector positive saturation voltage is applied to the integrator summing junction through the combination R3 and R4 causing the
current IA to flow.
A constant amplitude triangular wave generator is
shown in Figure 15. This circuit provides a variable frequency triangular wave whose amplitude is independent of frequency. This entire circuit can be built inexpensively, using a dual operational amplifier IC, such as
the XR-4558.
The integrator then generates a negative-going ramp
with a rate of IA/Cl volts per second until its output
equals the negative trip point of the threshold detector.
The threshold detector then changes to the negative
output state, and supplies a negative current, IB, at the
integrator summing point. The integrator now generates
a positive-going ramp with a rate of IBICl volts per second until its output equals the positive trip point of the
threshold detector, where the detector again changes
output state and the cycle repeats.
INTEGRATOR
C1
10K
1M
Triangular wave frequency is determined by R3, R4 and
C1 and the positive and negative saturation voltages of
the amplifier A1. Amplitude is determined by the ratio of
R5 to the combination of R1 and R2 and the threshold
detector saturation voltages. Positive and negative
ramp rates are equal and positive and negative peaks
are equal if the detector has equal positive and negative saturation voltages. The output waveform may be
offset with respect to ground if the inverting input of the
threshold detector, Al, is offset with respect to ground.
B.2K
Figure 15. A Simple Triangle Wave Oscillator
The generator embodies an integrator as a ramp generator and a threshold detector with hysteresis as a reset
circuit. The integrator has been described in a previous
section and requires no further explanation. The threshold detector is similar to a Schmitt trigger in that it is a
latch circuit with a large dead zone. This function is implemented by using positive feedback around an operational amplifier. When the amplifier output is in either
the positive or negative saturated state, the positive
fe,edback network provides a voltage at the noninverting input which is determined by the attenuation
of the feedback loop and the saturation voltage of the
amplifier. To cause the amplifier to change states, the
voltage at the input of the amplifier must be caused to
change polarity by an amount in excess of the amplifier
input offset voltage. When this is done, the amplifier
saturates in the opposite direction and remains in that
The generator may be made independent of temperature and supply voltage if the detector is clamped with
matched zener diodes.
The integrator section should be compensated for
unity-gain. The detector section may require compensation if power supply impedance causes oscillation
during its transition time. The current into the integrator
should be large with respect to the input bias current
for maximum symmetry; and offset voltage should be
small with respect to peak output voltage swing.
1-269
Choosing the Right Op Amp
Because oi its versatility and ease of application, the
op-amp is often the easiest active component to design
into the circuit. However, once the initial "paper design" is accomplished, the user is faced with the key
question: which op-amp is the best choice for the particular application? The availability of a very wide
choice of IC op-amps of varying part numbers, types
and features does not make the answer to this question
an easy one. If the op-amp characteristics are not carefully considered, the total system performance may be
degraded: similarly if each op-amp is overspecified with
an excessive amount of "overkill" for the particular application, then the system cost will increase unnecessarily. The key selection criteria is finding the lowest
cost operational amplifier which will be sufficient to
meet the system performance requirements. This section provides a brief summary of various classes of IC
op-amps, their features and key applications, to assist
the user in choosing the most cost-effective operational
amplifier for his application.
they can be operated with a single positive supply, and
stili be able to detect or sense small signals near
ground potential. The particular circuit recommended
for this application is Exar's XR-3403 quad operational
amplifier.
Programmable Op-Amps
Programmable op-amps allow the user to "program" or
set the operating current levels within the IC op-amp by
means of an external setting resistor, and thus be able
to trade-off power dissipation for slew-rate or signal
bandwidth. These circuits are normally available in
quad form, where the power levels of all or some of the
op-amps in the package can be programmed by one or
two external setting resistors. The key areas of applications for programmable op-amps are active filters and
telecommunication channel filters where the user is
normally concerned with power dissipation. These opamps can also be programmed to operate at micropower levels, by the choice of external setting resistors.
General Purpose Op-Amps
The programmable quad operational amplifiers are
available with either one or two separate setting controls. Those with a single setting control have all four of
the operational amplifiers programmed from same current setting control. Those with two setting controls
have the four op-amps on the chip programmed either
in groups oftwo, or in groups of one and three op-amps.
The advantage of partitioned programming is that some
of the op-amps in the IC package can be operated at a
different power or bandwidth level than the rest of the
op-amps in the same chip. For example, in an active filter application, the three op-amps performing the filtering can be operated at a low-power level, yet the fourth
op-amp which may be serving as an output buffer can
be operated at a higher power level to provide loaddrive capability.
A wide variety of op-amp applications such as lowfrequency amplifiers, active filters, voltage-to-current
converters and voltage regulators are most economically accomplished using the low-cost general purpose
IC op-amps. These op-amps are almost all variations of
the basic 741-type op-amp, and offer significant cost
savings over any special-purpose op-amps. They are
commercially available in single, dual or quad versions.
The dual and quad op-amps are particularly costeffective for applications such as active filters which require a multiplicity of op-amps. The cost per op-amp is
usually lower if one can use multiple op-amp IC's rather
than single op-amps.
The Single and dual general purpose op-amps are available in both internally compensated and uncompensated versions. The quad op-amps are almost invariably internally compensated, to reduce the IC package pin
count. Most general purpose IC op-amps have comparable electrical characteristics, namely open loop gain
of <: 20 mVN, small-signal unity gain bandwidth of 1 to
2 MHz and a slew rate of "" 1V/p.sec.
Exar offers the broadest product line of programmable
op-amps in the industry: The XR-4202, XR-146 and the
XR-346-2 families of op-amps are all-bipolar programmable quad op-amp circuits. The XR-4202 offers a single .current-setting control for all of the four op-amps on
the chip; the XR-146 and the XR-346-2 offer partitioned
programming of the four op amps. The XR-094 and
XR-095 families are programmable FET-input quad opamps which have the same pin configuration as the
XR-146 and the XR-346-2 families, respectively. These
programmable FET-input quad op-amps are fabricated
using Exar's ion-implanted bipolar/FET or BIFET process technology which combines matched junction
FETs and high-performance bipolar tranSistors on the
same chip.
Exar manufactures a wide choice of dual or quad general purpose op-amps. All of these op-amps are internally compensated to make them cost-effective and reduce the external parts count. Exar's general purpose
op-amps recommended for most applications are
XR-1458 and XR-4558 for duals, and XR-4136, XR-4212
and XR-4741 for quad op-amps.
Ground Sensing Op-Amps
FET-Input Op-Amps
These types of op-amps have an input stage commonmode range which extends all the way to the negative
supply rail. This is obtained by using Darlingtonconnected PN P transistors at the input stage of the opamp. The key advantage of this class of op-amps is that
Finite input impedance or input bias currents associated with conventional bipolar op-amps can be a problem in specific applications such as sample-hold circuits or signal sensing applications from high1-270
impedance signal source such as transducer systems.
For such applications, op-amps with junction-FET input
stages offer significant performance advantages since
they offer input resistances of the order of 10 12 ohms,
and input bias currents in the low pi co-ampere range.
Another unique feature of FET-input op-amps is their
high slew-rate and wide bandwidth. For example, most
FET-input op-amps offer slew-rates in excess of 10
V//Lsec and unity gain bandwidth of 3 MHz.
low noise characteristics than the FET-input op-amps.
Exar manufactures a number of low noise op-amp circuits uniquely suited to audio applications. Among Exar's family of low noise op-amps, the XR-5534 operational amplifier, and its dual versions, the XR-5532 and
the XR-5533 offer the best noise performance.
The FET-input op-amps offer somewhat higher offset
voltages and input noise than all-bipolar op-amps.
In addition to low noise characteristics, another key
performance requirement for audio applications is low
distortion. The distortion characteristics of op-amps are
normally determined by the design of the output stage
as well as the amplifier bandwidth characteristics. The
total harmonic distortion (THO) is made up of three
components: (a) intermodulation distortion; (b) crossover distortion which depends on output stage design,
and (c) slew-induced distortion which occurs when the
output of the op-amp is forced to slew faster than its
slew-rate.
Low Distortion Op-Amps
Exar offers a wide selection of FET·input dual and quad
op-amps which are manufactured using Exar's ionimplanted BIPOLAR/FET process. The XR-OB2IXR·OB3
are dual op-amps; the XR-OB4 is a quad FET-input opamp. The XR-094 and the XR-095 are programmable
quad FET-input op-amps. Because of their low power
capability, the programmable JFET op-amps are particularly suitable for low-power active filter designs.
Low Noisa Op-Amps
The cross-over distortion can be avoided by using opamps which have class-AB, rather than class-B type
output stages. All of Exar's op-amps fall into this category.
These op-amps are particularly suited for audio amplifi·
er and mixer applications, where low noise is of prime
importance. The noise characteristics of an op-amp are
determined by the noise generated at the input stage,
since the noise generated at this point is amplified by
the full open-loop gain of the lilllPlifier. In most cases,
input noise voltages of 10 nV/.JHz or less is required to
be suitable for high quality or professional audio signal
processing applications. Such low noise characteristics are normally obtained by careful device design and
manufacturing processing of the Ie chips. In general,
all-bipolar operational amplifiers tend to have better
To avoid slew-induced distortion, one should ensure
that the slew rate of the amplifier is never exceeded
during the excursions of the input signal. The highspeed operational amplifiers such as Exar's XR-5533 or
XR-5534 op-amps which have slew rates in excess of
10 V//Lsec with a power bandwidth of 200 kHz can easily cover the entire audio frequency range without introducing slew-induced distortion.
1-271
XR·082/083
Dual Bipolar JFET Operational Amplifier
FUNCTIONAL BLOCK DIAGRAMS
GENERAL DESCRIPTION
The XR-082/XR-083 family of dual bipolar JFET operational amplifiers are designed to offer higher performance than conventional bipolar op amps. Each amplifier
features high slew rate, low input bias and offset currents, and low offset voltage drift with temperature.
These operational amplifier circuits are fabricated using ion-implantation technology which combines wellmatched junction JFETs and high-performance bipolar
transistors on the same monolithic chip.
XR-082
The XR-082 of family of dual bipolar JFET op amps are
packaged in 8-pin dual-in-line packages. The XR-083
family of op amps offer independent offset adjustment
for each of the individual op amps on the same chip,
and are available in 14-pin dual-in-line packages.
OUTPUT A
-Vee
-INPUT A
OUTPUT B
+INPUT A
-INPUT B
+INPUT 8
FEATURES
Direct Replacement for TL082ITL083
Low Power Consumption
Wide Common-Mode and Differential Voltage Ranges
Low Input Bias and Offset Currents
Output Short Circuit Protection
High Input Impedance .. JFET Input Stage
Internal Frequency Compensation
Latch-Up-Free Operation
High Slew Rate .. 13 V/p.s, Typical
APPLICATIONS
-INPUT A
OFFSET
NULL A
+INPUT A
+Vcc
OFFSET
NULL A
Buffer Amplifiers
Summing/Differencing Amplifiers
Instrumentation Amplifiers
Active Filters
Signal Processing
Sample and Differencing
I to V Converters
Integ rato rs
Simulated Components
Analog Computers
OUTPUT A
Ne
-VEE
OFFSET
NULL B
OUTPUT B
+INPUT B
-Vee
-INPUT B
OFFSET
NULL B
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
±18V
Differential Input Voltage
±30V
Input Voltage Range (Note 1)
±15V
Output Short Circuit Duration (Note 2)
Indefinite
Package Power Dissipation:
Plastic Package
625mW
5.0 mWoC
Derate Above TA = + 25°C
Ceramic Package
750 mW
6.0 mW/oC
Derate Above TA = + 25°C
Storage Temperature Range
-65°C to + 150°C
ORDERING INFORMATION
1-272
Part Number
Package
XR-082M/XR-083M
XR-082N/XR-083N
XR-082P/XR-083P
XR-082CN/XR-083CN
XR-082CP/XR-083CP
Ceramic
Ceramic
Plastic
Ceramic
Plastic
Operating Temperature
- 55°C to
-25°C to
- 25°C to
O°C to
O°C to
+ 125°C
+ 85°C
+ 85°C
+ 70°C
+ 70°C
XR·082/083
ELECTRICAL CHARACTERISTICS TA
= 25°C, VCC =
± 15V, unless otherwise specified.
XR·082MI
XR·083M
SYMBOL
VOS
VOS
~VOS/~T
PARAMETERS
3
6
3
9
10
IB
Input Bias Current
30
IB
Input Bias Current
Over Temp.
Input Offset Current
5
ViCM
Input Common Mode
Range
AVOL
Voltage Gain
VOPP
Max. Output Swing
(peak-to-peak)
1.4
50
200
25
RIN
Input Resistance
BW
Unity-Gain Bandwidth
200
30
100
5
24
24
1.4
30
100
5
50
24
24
1.4
2.8
200
25
27
24
24
UNIT
mV
mV
p.VloC
400
pA
20
nA
200
pA
5
2.8
=
Full Range
nA
TA
=
Full Range
mA
No Load,
No Input Signal
200
VlmV
RL 2: 2 kO,
Vo = ±10V
TA = Full Range
27
V
RL 2: 10 kO
TA = Full Range
15
10 12
1012
10 12
0
3
3
3
MHz
Common-Mode
Rejection
80
86
80
86
70
76
dB
PSRR
Supply-Voltage
Rejection
80
86
80
86
70
76
dB
dB
120
120
120
dVOUT/DT Slew Rate
13
13
13
Rise Time
0.1
0.1
0.1
10
10
10
20
20
20
TR
TO
EN
Overshoot
Equivalent Input
Noise Voltage
= 500
= 500,
= Full Range
RS = 500,
TA = Full Range
RS
RS
TA
TA
CMRR
Channel Separation
CONDITIONS
V
±10
25
27
200
10
2.8
15
20
10
20
±12
±12
5
10
20
Supply Current
(per amplifier)
6
9
50
Input Offset Current
Over Temp.
ICC
XR·082CI
XR·083C
MIN TYP MAX MIN TYP MAX MIN TYP MAX
Input Offset Voltage
Offset Voltage
Temp. Coef.
lOS
XR·0821
XR·083
RS
:s 10 kO
AV = 100,
Freq. = 1 kHz
= 1,
= 2 kO
= 100 pF,
= 10V
p'sec AV = 1,
RL = 2 kO
%
CL = 100 pF,
Vl = 20 mV
nVI...[Hz RS = 1000
VIp.S
AV
RL
CL
Vl
f = 1 kHz
Note 1: For Supply Voltage less than ± 15 V, the absolute maximum input voltage is equal to the supply voltage.
Note 2: The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be
limited to ensure that the dissipation rating is not exceeded.
1-273
XR·082/083
+Vcc O-------------~------------------._--------_1~------_.--------~----__,
NON'INVE:!:~~~
0o====:~:~:::::~:::::::::::~---...,
INVERTING
12811
INPUT
t-~W"""--ir------t--o OUTPUT
rI
I
I
+VCC
o--+----~--------~------~--~~--------~----------_4--------~----~~~
6
6
OFFSET NULL
OFFSET NULL
(N1)'
(N2)'
• AVAILABLE IN XR·083 ONLY.
(ONE CHANNEL ONLY)
EQUIVALENT SCHEMATIC DIAGRAM
1·274
XR·084
Quad Bipolar JFET Operational Amplifier
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-084 quad bipolar JFET operational amplifier is
designed to offer higher performance than conventional bipolar quad op amps. Each of the four op amps on
the chip is closely matched in performance characteristics, and each amplifier features high slew rate, low
input bias and offset currents, and low offset voltage
drift with temperature. The XR-084 JFET input quad op
amp is fabricated using ion-implanted bipolar JFET
technology which combines well-matched JFETs and
high-performance bipolar transistors on the same monolithic integrated circuit.
OUTPUT II
-INPUT II
+INPUT II
+Vcc
+INPUT B
FEATURES
-INPUT B
Direct Replacement for TL084
Same Pin Configuration as XR-3403, LM324
High-Impedance JFET Input Stage
Internal Frequency Compensation
Low Power Consumption
Wide Common-Mode and Differential Voltage Ranges
Low Input Bias and Offset Currents
Output Short Circuit Protection
Latch-Up-Free Operation
High Slew Rate ... 13 V/p.s, Typical
OUTPUTB
APPLICATIONS
ORDERING INFORMATION
Buffer Amplifiers
Summing/Differencing Amplifiers
Instrumentation Amplifiers
Active Filters
Signal Processing
Sample and Differencing
I to V Converters
Integrators
Simulated Components
Analog Computers
Part Number
Package
XR-084M
XR-084N
XR-084P
XR-084CN
XR-084CP
Ceramic
Ceramic
Plastic
Ceramic
Plastic
Operating Temperature
- 55°C to
- 25°C to
-25°C to
O°C to
O°C to
+ 125°C
+ 85°C
+ 85°C
+ 70°C
+ 70°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
±18V
Differential Input Voltage
±30V
Input Voltage Range (Note 1)
±15V
Output Short Circuit Duration (Note 2)
Indefinite
Package Power Dissipation:
625 mW
Plastic Package
5.0 mW/oC
Derate Above TA = + 25°C
750mW
Ceramic Package
6.0 mW/oC
Derate Above TA = + 25°C
-65°C to +150°C
Storage Temperature Range
SYSTEM DESCRIPTION
The XR-084 is a quad JFET input operational. amplifier
featuring extremely high input resistance, low input bias and offset currents, large common mode voltage
range, and large output swing range. Unity gain bandwidth is 3 MHz and slew rate is 13V/I'S. The devices are
unity gain compensated.
.
1-275
XR·084
ELECTRICAL CHARACTERISTICS TA = 25°C, Vee
± 15, unless otherwise specified.
XR-084
XR-084M
SYMBOL
PARAMETERS
MIN
TYP
MAX
3
6
Vas
Vas
Input Offset Voltage
AVOSlllT
Offset Voltage
Temp. Coef.
10
IB
Input Bias Current
30
IB
Input Bias Current
Over Temp.
lOS
Input Offset Current
MIN
TYP
MAX
3
6
ICC
Supply Current
(per amplifier)
VICM
Input Common Mode
200
30
±12
MAX
UNIT
CONDITIONS
5
15
20
mV
mV
RS- 5011
RS = 5011,
TA = Full Range
200
30
20
100
5
20
1.4
TYP
100
5
10
2.8
1.4
2.8
1.4
±10
±12
pV/·C
10
10
50
5
MIN
9
9
Input Offset Current
Over Temp.
XR-084C
RS
TA
= SOil.
= Full Range
TA
= Full
Range
= Full
Range
400
pA
20
nA
200
pA
5
nA
TA
2.8
mA
No Load.
No Input Signal
V
Range
AvOL
Voltage Gain
VOPP
Max. Output Swing
(peak·to·peak)
50
200
25
24
24
50
200
25
27
24
24
24
24
RIN
Input Resistance
BW
Unity-Gain Bandwidth
CMRR
Common·Mode
Rejection
80
86
80
86
PSRR
Supply·Voltage
Rejection
80
86
80
86
Channel Separation
V/mV
RL>: 2 kll.
Vo = ±10V
TA = Full Range
27
V
RL>: 10 kll
TA = Full Range
15
25
27
200
1012
10 12
1012
II
3
3
3
MHz
70
76
dB
70
76
dB
120
dB
120
120
RS" 10 kll
= 100.
= 1 kHz
Ay = 1.
RL = 2 kO
CL = 100 pF.
VI = 10V
Ay = 1.
RL = 2 kO
CL = 100 pF.
VI = 20 mV
RS = 10011
f = 1 kHz
Ay
Freq.
DVOUTIDT
Slew Rate
13
13
t3
VipS
TR
Rise Time
0.1
0.1
0.1
"sec
TO
Overshoot
10
10
10
%
EN
Equivalent Input
NOise Voltage
20
20
20
nV/...{Rz
Note 1: For Supply Voltage less than ± 15V. the absolute maximum input voltage is equal to the supply voltage.
Note 2: The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the dissipation rating
is not exceeded.
EQUIVALENT SCHEMATIC DIAGRAM
1-276
XR·094/095
Quad Programmable Bipolar J FET
Operational Amplifiers
FUNCTIONAL BLOCK DIAGRAMS
GENERAL DESCRIPTION
The XR-094 and XR-095 bipolar JFET input quad programmable operational amplifiers consist of four independent, high gain, internally compensated amplifiers.
Two external resistors (RSET) allow the user to program
supply current slew-rate input noise without the usual
sacrifice of gain bandwidth product. For example, the
user can trade-off slew-rate for supply current or optimize the noise figure for a given source impedance. Except for the two programming pins at the end of the
package, the XR-094 and XR-095 pin-out is the same as
the popular 324,3403, 124, 148 and 4741 operational
amplifiers.
OUTPUT A
1
-INPUT A l
+INPUT A 3
+INPUT B 5
OUTPUT C
OUTPUT B 7
In the case of the XR-094, three of the op amps on the
chip share a common programming pin; and the fourth
op amp is programmed separately. In the case of the·
XR-095, each pair of op amps share a common programming pin.
FEATURES
Same Pin Configuration as LM-346
High-Impedance FET Input Stage
Internal Frequency Compensation
Low Power Consumption
Wide Common-Mode and Differential Voltage Ranges
Low Input Bias and Offset Currents
Output Short-Circuit Protection
High Slew-Rate ... 13 V/p.s, Typical
Programmable Electrical Characteristics
ABSOLUTE MAXIMUM RATINGS (Continued)
Derate Above TA = +25°C
Ceramic Package
Derate Above TA = +25°C
Storage Temperature Range
APPLICATIONS
Total Supply Current = 5.6 mA (lSET/320 p.A)
Slew Rate = 13 V/p.s (ISET/320 p.A)
ISET = Current into set terminal
Note 1: For Supply Voltage less than ± 15V, the absolute maximum input voltage is equal to the supply voltage.
I
_ VCC - (VEE - 0.6V)
SET RSET
Note 2: The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the dissipation rating is not exceeded.
Note. ISET must be :s; 400p.A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Differential Input Voltage
Input Voltage Range (Note 1)
Output Short-Circuit Duration (Note 2)
Package Power Dissipation:
Plastic Package
5.0 mV/oC
750 mW
6.0 mW/oC
- 65°C to + 150°C
ORDERING INFORMATION
±18V
±30V
±15V
Indefinite
625 mW
1-277
Part Number
Package
XR-094/XR-095N
XR-094/XR-095P
XR-094/XR-095CN
XR-094IXR-095CP
Ceramic
Plastic
Ceramic
Plastic
Operating Temperature
-25°C
-25°C
O°C
O°C
to
to
to
to
+85°C
+85°C
+ 70°C
+ 70°C
XR·094/095
ELECTRICAL CHARACTERISTICS
TA = 25°C, VCC
ISET = 320 pA
=
± 15V, unless otherwise specified.
XR-094/095
PARAMETERS
MIN
XR-094/095C
TYP MAX MIN TYP MAX
Input Offset Voltage
3
Offset Voltage
Temp. Coel.
10
6
15
20
5
9
UNITS
SYMBOL
CONDITIONS
mV
mV
Vas
Vas
RS = 500, TA = 25°C
Rs = 500, TA = Full Range
p.V/oC
10
Input Bias Current
IB
80
600
20
80
800
20
pA
nA
40
300
10
40
500
5
pA
nA
1.4
2.8
1.4
2.8
mA
ICC
V
ViCM
Input Offset Current
±12
±10
TA = 25°C
TA = Full Range
50
25
200
25
15
200
24
24
27
24
24
27
Input Resistance
Unity-Gain Bandwidth
V
RL O!: 2KO, Vo = ±10V
TA = 25°C
TA = Full Range
VOpp
RL O!: 10 KO
TA = 25°C
TA = Full Range
1012
1012
0
Rin
TA = 25°C
3
3
MHz
BW
TA = 25°C
Common-Mode Rejection
80
86
70
76
dB
CMRR
Supply-Voltage Rejection
80
86
70
76
dB
PSRR
Channel Separation
No Load, No Input Signal
AvOL
V/mV
Voltage Gain
Max. Output Swing
(peak·to-peak)
TA = 25°C
TA = Full Range
lOS
Supply Current
(per amplifier)
Input Common Mode
Range
I:!.VOSII:!.T RS = 500, TA = Full Range
RS:S; 10 KO
120
120
dB
Slew Rate
13
13
V/p.S
Rise Time
Overshoot
0.1
10
0.1
10
p'sec
%
tr
to
AV = 1, RL = 2 KO
CL = 100 pF, V1 = 20 mV
Equivalent Input
Noise Voltage
18
18
nV/.JHz
en
RS = 1000
f = 1 kHz
(One Channel Onlyl
EQUIVALENT SCHEMATIC DIAGRAM
1-278
AV = 100, Freq. = 1 kHz
dVout/dt AV = 1, RL = 2 KO
CL = 100 pF, V1 = 10V
XR·096
Quad Programmable Bipolar JFET
Operational Amplifier
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-096 monolithic circuit contains four independently programmable JFET operational amplifiers in a
single IC package. Each of the four op amp sections on
the chip has its own external bias terminal; thus its performance characteristics and power dissipation can be
independently controlled, without effecting the other op
amp sections on the chip. The respective bias-setting
resisters, RSET, connected to the programming terminals of the circuit allow one to trade-off power dissipation for slew-rate, without sacrificing the gainbandwidth product of the circuit. These individual bias
terminals can also be used to switch the op amp sections "on" and "off", and thus, multiplex between various op amp channels on the same chip.
+fNPUT B
+INPUT 0
FEATURES
-INPUT B
-INPUT C
SET 0
SET A
OUTPUT A
OUTPUT 0
-INPUT A
-INPUT 0
.,NPUT A
+INPUT 0
+Vcc
Programmable Version of XR-084
Independent Programming of All Four Op Amps
Programmable for Micropower Operation
High-Impedance JFET Input Stage
Internal Frequency Compensation
Low Input Bias and Offset Currents
-VEE
OUTPUT C
OUTPUT B
SETe
SET B
APPLICATIONS
Total Supply Current = 5.6 mA (lSET/320 pAl
Slew-Rate = 13 V/p.s (lSET/320 pAl
ISET = Current into set terminal
ISET =
ORDERING INFORMATION
VCC - (VEE - 0.6V)
-=-=----'-=----'
RSET
Note. ISET must be :s; 400pA
Part Number
Package
XR-096N
XR-096P
XR-096CN
XR-096CP
Ceramic
Plastic
Ceramic
Plastic
Operating Temperature
-25°C to
- 25°C to
O°C to
O°C to
+85°C
+ 85°C
+ 70°C
+ 70°C
ABSOLUTE MAXIMUM RATINGS
±18V
Supply Voltage
±30V
Differential Input Voltage
±15V
Input Voltage Range (Note 1)
Indefinite
Output Short-Circuit Duration (Note 2)
Package Power Dissipation:
Plastic Package
625 mW
Derate Above TA = +25°C
5.0 mV/oC
Ceramic Package
750 mW
Derate Above TA = +25°C
6.0 mW/oC
Storage Temperature Range
-65°C to + 150°C
Note 1: For Supply Voltage less than ± 15V, the absolute maxi-
SYSTEM DESCRIPTION
The XR-096 is a quad independently programmable
JFET input operational amplifier featuring extremely
high input resistance, low input bias and offset current,
large common mode voltage range, and large output
swing range. Unity gain bandwidth is 3 MHz, and slew
rate is 13V/p.S. The devices are unity gain compensated.
Each of the form amplifiers may be independently
"programmed"-rebiased-by connecting a resistor from
the bias adjust pin to the positive supply. Bias current
may range up to 400 pA, thus affording the designer
flexibility along the pOWF!r consumption/speed curve.
mum input voltage is equal to the supply voltage.
Note 2: The output may be shorted to ground or to eliher supply. Temperature and/or supply voltages must be limited to ensure that the dissipation rating is not exceeded.
1-279
XR·096
ELECTRICAL CHARACTERISTICS
TA = 25°C, VCC = ± 15V, unless otherwise specified.
ISET = 320 p.A.
XR·096
PARAMETERS
XR·096C
MIN TYP MAX MIN TYP MAX
Input Offset Voltage
3
Offset Voltage
Temp. Coef.
10
5
6
9
15
20
UNITS
SYMBOL
mV
mV
VOS
VOS
p.V/oC
10
ilVOS/ilT RS
Input Bias Current
IB
80
600
20
80
800
20
pA
nA
40
300
10
40
500
5
pA
nA
1.4
2.8
1.4
2.8
mA
ICC
V
ViCM
Input Offset Current
±12
±10
Voltage Gain
Max. Output Swing
(peak-to-peak)
200
25
15
200
24
24
27
24
24
27
Input Resistance
Unity-Gain Bandwidth
TA
TA
= 25°C
= Full Range
No Load, No Input Signal
RL 2! 2KO, Vo = ±10V
TA = 25°C
TA = Full Range
V
VOpp
RL 2! 10 KO
TA = 25°C
TA = Full Range
10"
10"
0
3
3
MHz
Rin
BW
Common-Mode Rejection
80
86
70
76
dB
CMRR
Supply-Voltage Rejection
80
86
70
76
dB
PSRR
Channel Separation
= 25°C
= Full Range
AVOL
V/mV
50
25
= 500, TA = 25°C
= 500, TA = Full Range
= 500, TA = Full Range
TA
TA
lOS
Supply Current
(per amplifier)
Input Common Mode
Range
CONDITIONS
RS
RS
TA
TA
= 25°C
= 25°C
RS :s 10 KO
120
120
dB
Slew Rate
13
13
V/p.s
AV 100, Freq.
dVout/dt
Rise Time
Overshoot
0.1
10
0.1
10
p'sec
%
tr
to
AV
CL
Equivalent Input
Noise Voltage
18
18
nV/VHz
en
RS
f = 1 kHz
A.J =
CL
.i'co--r---r----r----r---,
(Onl Chlnn.1 Only)
~"II
au_TUTIl
EQUIVALENT SCHEMATIC DIAGRAM
1-280
= 1 kHz
1, RL = 2 KO
100 pF, Vl = 10V
=
= 1, RL = 2 KO
= 100 pF, Vl = 20 mV
= 1000
XR·146/246/346
Programmable Quad Operational Amplifiers
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAMS
The XR-146 family of quad operational amplifiers contain four independent high-gain, low-power, programmable op-amps on a monolithic chip. The use of external bias setting resistors permit the user to program
gain-bandwidth product, supply current, input bias current, input offset current, input noise and the slew rate.
OUTPUT 0
-INPUT 0
+INPUT 0
-VEE
The basic XR-146 family of circuits offer partitioned
programming of the internal op-amps where one setting resistor is used to set the bias levels in the three
op-amps, and a second bias setting is used for the remaining op-amp. Its modified version, the XR-346-2 provides a separate bias setting resistor for each of the
two op-amp pairs.
+INPUT C
-INPUTC
OUTPUT C
'SET
FEATURES
Programmable
Micropower operation
Low noise
Wide power supply range
Class AB output
Ideal pin out for biquad active filters
Overload protection for input and output
Internal frequency compensation
OUTPUT A
OUTPUT 0
-INPUT A
-INPUT 0
+INPUT A
+INPUT 0
+VCC
-VEE
APPLICATIONS
+INPUT B
+INPUTC
Total Supply Current = 1.4 mA (lSET/1 0 ,.A)
Gain Bandwidth Product = 1 MHz (lSET/10I'A)
Slew Rate = O.4Y/l's (lSET/10 I'A)
Input Bias Current =50 nA (lSET/10 I'A)
-INPUT B
-INPUTC
OUTPUT B
OUTPUTC
'SET
ISET = Current into pin 8, pin 9 (see schematic)
Y+ -Y- -0.6Y
ISET = -'----'---...::..:.::..:...
RSET
--,;;;;,;.;---~-
'SET
ABSOLUTE MAXIMUM RATINGS (continued)
ABSOLUTE MAXIMUM RATINGS
Supply Yoltage
XR-146
XR-246/346
Differential Input Yoltage (Note 1)
XR-146/246/346
Common Mode Input Yoltage (Note 1)
XR-146/246/346
Power Dissipation (Note 2)
XR-146
XR-246/346
Output Short Circuit Duration (Note 3)
XR-146/246/346
Maximum Junction Temperature
XR146
XR-246
XR-346
Storage Temperature Range
XR-146/246/346
±22Y
±18Y
±30Y
ORDERING INFORMATION
±15Y
900 mW
500 mW
Indefinite
1-281
Part Number
Package
Operating Temperature
XR-146M
XR-246N
XR-246P
XR-3461
346-2CN
XR-3461
346-2CP
Ceramic
Ceramic
Plastic
-55°C to + 125°C
-25°C to +85°C
-25°C to +85°C
Ceramic
O°C to + 70°C
Plastic
O°C to + 70°C
XR·146/246/346
ELECTRICAL CHARACTERISTICS (TA
=
+25°C, Vs
=
± 15V, ISET
XR·146
PARAMETERS
MIN
Input Offset Voltage
= 10 p.A)
XR·246/346
TYP
MAX
0.5
5
MIN
TYP
MAX
UNITS
0.5
6
mV
VCM = OV,
RS :s 500
CONDITIONS
Input Offset Current
2
20
2
100
nA
VCM
Input Bias Current
50
100
50
250
nA
VCM
1.4
2.0
1.4
2.5
Supply Current (4 Op·Amps)
Large Signal Voltage Gain
Input CM Range
100
1000
50
1000
rnA
VlmV
RL = 10 kO,
.<1VOUT = ±10V
±13.5
±14
±13.5
±14
V
CM Rejection Ratio
80
100
70
100
dB
RS
Power Supply Rejection Ratio
80
100
74
100
dB
RS
Output Voltage Swing
±12
±14
±12
±14
V
RL
Short-Circuit Current
Gain Bandwidth Product
5
20
0.8
1.2
30
5
20
0.5
1.2
= OV
= OV
30
:s
:s
:s
10 kO
10 kO
10 kO
rnA
MHz
Phase Margin
60
60
Deg
Slew Rate
0.4
0.4
Vlp.s
Input Noise Voltage
28
28
nV/-IRz
Channel Separation
120
120
dB
Input Resistance
1.0
1.0
MO
Input Capacitance
2.0
2.0
pF
f = 1 kHz
RL = 10 kO,
.<1VOUT = OV to +12V
The fOllowing specifications apply over the Maximum Operating Temperature Range
Input Offset Voltage
0.5
0.5
6
7.5
mV
VCM = OV,
RS :s 500
Input Offset Current
2
25
2
100
nA
VCM = OV
Input Bias Current
50
100
50
250
nA
VCM = OV
Supply Current (4 Op-Amps)
1.5
2.0
1.5
2.5
rnA
25
1000
VlmV
Large Signal Voltage Gain
Input CM Range
50
1000
RL = 10 kO,
.<1VOUT = ±10V
±13.5
±14
±13.5
±14
V
CM Rejection Ratio
70
100
70
100
dB
RS
Power Supply Rejection Ratio
76
100
74
100
dB
RS
±12
±14
±12
±14
V
RL ~ 10 kO
mV
VCM = OV,
RS :s 500
VCM
Output Voltage Swing
:s
:s
500
500
ELECTRICAL CHARACTERISTICS (TA = 25°C, Vs = ± 15V, ISET = 1 p.A)
Input Offset Voltage
0.5
5
0.5
6
Input Bias Current
7.5
20
7.5
100
nA
Supply Current (4 Op-Amps)
140
250
140
300
p.A
Gain Bandwidth Product
80
100
50
100
= OV
kHz
ELECTRICAL CHARACTERISTICS (TA = + 25°C, Vs = ± 1.5V, ISET = 10 p.A)
Input Offset Voltage
Input CM Range
0.5
±0.7
CM Rejection Ratio
Output Voltage Swing
5
0.5
±0.7
80
±0.6
1-282
mV
VCM = OV,
RS :s 500
V
80
±0.6
7
dB
V
RS
:s 500
RL ~ 10 kO
XR·146/246/346
EQUIVALENT SCHEMATIC DIAGRAM
(One Channel Only)
l - - - - - - -......;:;.I.•u:.~~,~()Oo\------_l--- ;0-,..
TYPICAL PERFORMANCE CHARACTERISTICS
Input Bial Current VI ISET
Supply Current
VI
Open loop Voltage Gain v.
ISET
ISET
110
'"
z
II.
u
11.'
~
L
""
"~
1.1
VI
"
40
VS· iliV
2'
TA-noc
'SET "'"
Gain Bandwidth Product VI
ISET
ISET
Pha.e Margin v. ISET
10M
11
lDO
11
0.1
'SET "'"
ISET "'"
Slew Retll
l-
so I-
•
lDO
10
14.
~
lDO
to
! ."
I.
1M
S
a
'.1
"
<;
lOOk
i
~
;
'"
1.11
11
f
i-
50
40
30
2.
VS. t15V
TA· noc
10
,.
1.
101
10'
•
Open loop Voltage Gain
VI Temperature
140
'SlT"'"
",
101
ISET ·'0"A
-
ISET·"A~
-
15£1- 0.1 JJA
-
lDO
II
Slew Rate VI
Temperature
Gain Bandwidth Product
Temperature
VI
ISET-'"'' TO ,O,..A
,,5
lDO
1.
'.1
ISET "'"
~§
'.1
'SETath"
EE ~ ISET- hA
If
41
104
21
VS· tHiV
I
-55 -31 -15
5 ZS 45 15 Ii 105 125
TEM'ERATURE reI
, 3 ~~~~~f'~VS~.~'~15~V
-55 -35 -15
5 25 45 15 15 105 125
TEM,ERATURE (OC)
1-283
0.01
E~ ~IS£T·G.1j.1A
'.001
I I I
-is -35 -15 5
FFF
Vs· !I5V
Z5 4S .5 IS 101 US
TEMI'ERATURE COCI
XR·146/246/346
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Input Nol .. Voltage
~
i
Frequency
':'"
111111
la
=
,.
~
II
IS~T ~I,I;~I
; ... ~~~;A
B
I •....• ~ f:SU·S"A
'~f.r ',~~,
I b
..
IS!T~I,I;~I
II
31
'sn""o"",
I ::
•,.
Isn- lOu '"
.
T... "'ZS·C
'00
111111
1
I-
U
•..
'.7
~ ...
...
:: •..
"
f-
!
>
:l;
~
i
..
""
S
..
l-
~
vs· ~ISV
D.'
I
'A • 25·C
."
Isn"'''1
!"
a
..
...
ll Jl f!t 1;lTI·l·j,sj.c~
Al-IDk !!
I
•
I
I
101214
II
FREQUENCY IHII
"D
'00
i.
6
i
ID
II
~
'0
;;:
VS" !15Y
T... "'ZS·C
11
tI
"
'm"'" "
ID
.
1
t--~ I
v,·
'00
Isn("A)
Input Bias Currlnt VI
I nput Common-Modo
Voltago
.00
'SET" 10,.'"
1
i
Isn"a.t/J'"
~
~
vs· '15Y
' ... "25"C
'sn"'."A
•
Z
...
I
II
12
14
~
i
-II
Input Offset Current VI
Temperatura
!1SV
10
"
-I
!I
Isn-"'"
D
-55 -35 -II 5 25 45 15 II 105 US
!.
I
''-'--'--"'-"'-",-",-.J....J..-J
-IS -15-15
5
25 45 IS 15 las 125
TEMPERATURE ('CI
VI
~ISET·,a"A
.!
, 1-+-+-+++-+ VS ·!ISV
"
"
C
I
TEM'UATURE '·CI
-"
SupplV Current
Temperatur.
rr-r-r-r-r-r-,-,-,
30
"
'A" noc
I.'
11
II
i3
Isn·'"A
"
INPUT COMMON·MODE VOLTAGE (VI
". - f -" -- I-- rSE!" ,LA --1--+f--
i.
..
VS-!15V
.2~
::;;
Input Bia, Cunent VI
Temperature
,•
10
SUPPl Y VOL TAGE ('VI
'00
'DOl
'00
i3
•
1a.
"
i
"
~
111
Power Supply Rejection
Ratio v. ISET
"
D.T
tOO
FREQUENCY (Mil
§
'SET ·10".10
•
"
~'"
TID
a
~~~~-+~d-~r-~
0
Input Voltage Range VI
Supply Voltage
"liB
•
100
'00
I"
Ie
"
1ft
"i
Common-Mode Rejection
Ratio v. ISET
Output Voltage Swing ys
Supply Voltage
i
TI. , . . , . - , - - , - , - - , . . ,
I. .
w
U
OJ
DJ
f
,..
..
; :
'SfT· ' hA
1.1
, Input O'h.t Voltage, v. ISET
' ... ·25"C
1111111
1.1
"'
fREQUENCY IHt)
~
VS· !15Y
~
;;
vs" ~I5V
u
Isn·','~A
\i:
III
Powo. Supply Rejection
Ratio ys Frequency
Input Noise Current VI
VI
Frequency
.j-c-=
~lsn·'jlA
;;;;0
D.'
I."
Vs"
~llY
'-'--'--'--'--'--1....:~........,
-55 -35 -15 5
U 45 15 IS lOS 125
TEM'ERATURI ria
Note 1: For supply voltages less than ± 15V, the absolute maximum input voltage is equal to the supply voltage.
Note 2: The maximum power dissipation for these devices must be derated at elevated temperatures and is
dictated by TjMAX, )9jA, and the ambient temperature, TA The maximum available power dissipation at
any temperature is Pd = (TjMAX - TAl/9jA or the 25°C PdMAX, whichever is less.
Note 3: Any of the amplifier outputs can be shorted to ground indefinitely; however, more than one should be
simultaneously shorted as the maximum junction temperature will be exceeded.
1-284
XR·1458/4558
Dual Operational Amplifier
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-1458/4558 is a pair of independent internally
compensated operational amplifiers on a single silicon
chip, each similar to the popular 741, but with a power
consumption less than one 741. Good thermal tracking
and matched gain-bandwidth products make these Dual Op-amps useful for active filter applications.
FEATURES
Direct Pin-for-Pin Replacement for MC1458, RC4558,
N5558
Low Power Consumption - 50 mW typo and
120mW max.
Short-Circuit Protection
Internal Frequency Compensation
No Latch-Up
Wide Common-Mode and Differential Voltage Ranges
Matched Gain-Bandwidth
APPLICATIONS
Buffer Amplifiers
SumminglDifferencing Amplifiers
Instrumentation Amplifiers
Active Filters
Signal Processing
Sample and Differencing
I to V Converters
Integrators
Simulated Components
Analog Computers
ORDERING INFORMATION
Part Number
Package
XR-1458CN
XR-1458CP
XR-4558CN
XR-4558CP
Ceramic
Plastic
Ceramic
Plastic
Operating Temperature
O°C
O°C
O°C
O°C
to
to
to
to
+ 70°C
+ 70°C
+ 70°C
+ 70°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
±18V
XR-4558CP
±15V
Input Voltage (Note 1)
Common Mode
Voltage Range
VEE to VCC
Output Short-Circuit Duration (Note 2)
indefinite
±30V
Differential Input Voltage
Internal Power DisSipation (Note 3)
Plastic Package:
500 mW
Storage Temperature Range:
- 65°C to + 150°C
Operating Temperature Range:
O°C to + 70°C
Note 1: For supply voltages less than ± 15V, the absolute max-
SYSTEM DESCRIPTION
The XR-1458 and XR-4558 are dual general purpose op
amps featuring better performance than industry standard devices such as the 741; bandwidth, slew rate,
and input resistance are greatly improved. Internal protection circuitry includes latch-Up elimination, short circuit current limiting, and internal compensation.
imum input voltage is equal to the supply voltage.
Note 2: Short circuit may be to ground or either supply. Rating
applies to + 125°C case temperature of + 75°C ambient temperature for XR1458/4558.
Note 3: Rating applies for case temperatures to 125°C: derate
linearly at 6.5mW/oC for ambient temperatures above
+ 75°C for XR1458/4558.
The two amplifiers are completely independent, sharing bias circuitry only.
1-285
XR·1458/4558
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = + 25°C, ± 15V, unless otherwise specified.
MIN
PARAMETERS
XR1458/4558CP
TYP
MAX
Input Offset Voltage
0.5
UNITS
SYMBOLS
6.0
mV
IViol
Input Offset Current
5
200
nA
lIiol
Input Bias Current
40
500
nA
Ilbl
CONDITIONS
s 10 KO
Rs
Input Resistance
0.3
5
MO
Rin
Large Signal Voltage Gain
20
300
V/mV
AVOL
RL ~ 2 KO
Vout = ±10V
Output Voltage Swing
±12
±10
±14
±13
V
V
Vout
Vout
RL ~ 10 KD
RL ~ 2 KD
Input Voltage Range
±12
±14
V
Common Mode Rejection Ratio
70
90
dB
ViCM
CMRR
Rs
Rs
Supply Voltage Rejection Ratio
30
150
p.VN
PSRR
Power Consumption
50
170
mW
Pi
p's
%
Transient Response (unity gain)
Risetime
Overshoot
0.13
5
s 10 KO
s 10 KO
Yin = 20 mV
RL = 2 KD
CL s 100 pF
Unity Gain Bandwidth
3.0
MHz
tr
to
BW
Slew Rate (unity gain)
1.0
V/p.s
dVout/dt
Channel Separation (open loop)
120
dB
f = 10 kHz
Rs = 1 KD
105
dB
f = 10 kHz
Rs=1KO
(Gain of 100)
s TA
The following speCifications apply for O°C
S
RL ~ 2 KO
+ 70°C for XR4558CP
Input Offset Voltage
7.5
MV
IViol
Input Offset Current
300
nA
lIiol
nA
Ib
Large-Signal Voltage Gain
15
V/mV
AVOL
Output Voltage Swing
±10
mV
Vout
Input Bias Current
800
Power Consumption
Rs S 10 kD
Rs ~ 2 KO
Vout = ±10V
RL ~ 2 KD
Vs = ±15V
90
120
Pi
Pi
J~
l
INVERTING
INPUT
mW
mW
150
200
NONrNVERTING
INPUT
I
t
rrrK r
EQUIVALENT SCHEMATIC DIAGRAM
1-286
Z
f
~
OUTPUT
1
VEEISUBSTRAT()
TA = High
TA = Low
XR·3403/3503
Quad Operational Amplifiers
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-3403 and XR-3503 are quad operational amplifiers specifically designed for single supply operation. All
four amplifiers are similar in characteristics to industry
standard op amps like the 741. The XR-3403 is available in both ceramic and plastic packages; the XR3503 is available in a 14 pin ceramic package with
guaranteed performances across the military temperature range.
OUTPUT A
OUTPUT 0
-INPUT A
-INPUT 0
.INPUT 0
+INPUT A
FEATURES
vEE
vee
Short Circuit Protected Outputs
Class AB Output Stage for Minimal Crossover
Distortion
True Differential Input Stage
Single Supply Operation: 3.0 to 36 Volts
Split Supply Operation: ± 1.5 to ± 18 Volts
Low Input Bias Currents: 500 nA Max
Four Amplifiers per Package
Internally Compensated
Similar Performance to Popular 741
Direct Pin-for-Pin Replacement for MC3403/3503,
LM324 and RC4137
+INPUT B
+INPUT C
-INPUT B
-INPUT C
OUTPUT B
OUTPUT C
APPLICATIONS
Buffer Amplifiers
SumminglDifferencing Amplifiers
Instrumentation Amplifiers
Active Filters
Signal Processing
Sample and Differencing
I to V Converters
Integrators
Simulated Components
Analog Computers
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-3503M
XR-3403CN
XR-3403CP
Ceramic
Ceramic
Plastic
- 55°C to + 125°C
DoC to + 70°C
DoC to + 70°C
ABSOLUTE MAXIMUM RATINGS
SYSTEM DESCRIPTION
Power Supply Voltages
36V
Single Supply
±18V
Split Supplies
Input Differential Voltage Range with
±30V
Split Power Supply
±15V
Input Common Mode Voltage Range'
Package Power Dissipation:
625 mW
Plastic Package
5.0 mV/oC
Derate above TA = + 25°C
750 mW
Ceramic Package
6.0 mW/oC
Derate above TA = + 25°C
-65°C to +150°C
Storage Temperature Range
The XR-3403 is an array of four independent operational amplifiers, each with true differential inputs. The device has electrical characteristics similar to the popular 741. However, the XR-3403 has several distinct advantages over standard operational amplifier types in
single supply applications. The XR-3403 can operate at
supply voltages as low as 3.0 volts or as high as 36
volts with quiescent currents about one-fifty of those
associated with the 741 (on a per amplifier basis). The
common mode input range includes the negative supply, thereby eliminating the necessity for external biasing components in many applications. The output voltage range also includes the negative power supply voltage.
* For Supply Voltage less than ± 15V, the absolute maximum input voltage is equal to the supply voltage.
1-287
XR·3403/3503
ELECTRICAL CHARACTERISTICS
Test Conditions: Vee
= + 15V, VEE = 15V, TA
+25°e unless otherwise noted.
XR-3503M
PARAMETERS
XR-3403C
TYP
MAX
TYP
MAX
UNITS
Input Offset Voltage
2.0
5.0
6.0
2.0
10
12
mV
Input Offset Current
30
50
200
30
50
200
nA
MIN
MIN
Large Signal Open· Loop
Voltage Gain
TA = Thigh to Tlow 1
TA = Thigh to Tlow
V/mV
50
25
200
300
Input Bias Current
-200
-300
Output Impedance
75
20
15
200
-200
-500
-1500
CONDITIONS
Vo = ±10V
RL = 2.0 KIl
TA = Thigh to Tlow
-500
-800
nA
TA = Thigh to Tlow
75
Il
f = 20 Hz
f = 20Hz
Input Impedance
0.3
1.0
0.3
1.0
Mil
Output Voltage Swing
±12
±10
±10
±13.5
±13
±12
±10
±10
±13.5
±13
V
+ 13V,VEE
+ 13.5V,VEE
+ 13V-VEE
+ 13.5V,VEE
V
70
90
70
90
dB
RS < 10 KO
RL =
Input Common Mode Voltage
Range
Common Mode Rejection
Ratio
Power Supply Current
(Vo = 0)
±30
±45
Positive Power Supply
Rejection Ratio
30
Negative Power Supply
Rejection Ratio
30
Average Temperature
Coefficient of Input
Offset Current
50
50
pN°C
TA = Thigh to Tlow
Average Temperature
Coefficient of Input
Offset Voltage
10
10
~V/oC
TA = Thigh to Tlow
Power Bandwidth
9.0
9.0
kHz
AV = 1. RL = 2.0 KO
Vo = 20V (p.p)
THD = 5%
Small Signal Bandwidth
1.0
1.0
MHz
AV = 1, RL = 10 KIl
Vo = 50 mV
Slew Rate
0.6
0.6
V/~s
AV = 1, Vi = -lOV
to +10V
Rise Time
0.6
0.6
~s
AV = 1.RL = lOKn
Vo = 50 mV
Fall Time
0.6
0.6
~s
AV -1,RL -10KIl
Vo = 50 mV
Overshoot
20
20
%
Av = 1,RL = 10KIl
Vo = 50 mV
Phase Margin
60
60
Degrees
AV - 1, RL - 2.0 KIl
CL = 200 pF
Crossover Distortion
1.0
1.0
%
1Thi9h = + 125°C for XR·3503M, + 70°C for XR·3403C
Tlow = - 55°C for XR·3503M, O°C for XR-3403C
mA
±20
±45
mA
150
30
150
~VIV
150
30
150
~VIV
10 KIl
2.0 KO
2.0 KIl
Thigh to Tlow
4.0
±20
7.0
=
=
=
=
2.8
Individual Output
Short·Circuit Current 2
2.8
RL
RL
RL
TA
±10
(Vin = 30 mV p.p
Vout = 2.0V p.p
F=10kHz)
2Not to exceed maximum package power dissipation.
30utput will swing to ground.
1-288
00
XR·3403/3503
ELECTRICAL CHARACTERISTICS
Tesl Conditions: Vee = 5.0V. VEE = Gnd. TA = + 25°e. unless otherwise noted.
XR-3503M
PARAMETERS
MIN
XR-3403C
TYP
MAX
Input Offset Voltage
2.0
5.0
Input Offset Current
30
50
-200
-500
Input Bias Current
Large Signal Open Loop
Voltage Gain
20
200
Power Supply Rejection
Ratio
Output Voltage Range 3
Power Supply Current
Channel Separation
MIN
20
TYP
MAX
UNITS
2.0
10
mV
30
50
nA
-200
-500
200
150
3.5
3.5
VCC-l.5V
VCC-l.5V
2.5
4.0
-120
7.0
RL
=
2.0 KIl
p.V/v
Vp·p
2.5
-120
nA
V/mV
150
CONDITIONS
RL = 10 KIl
VCC = 5.0V
RL = 10 KIl
5.0V :s VCC :s 30V
mA
dB
f = 1.0 kHz to 20 kHz
(Input Referenced)
OUTPUT
BIAS CIRCUITRV
COMMON TO FOUR
AMPLIFIERS
Vee
EQUIVALENT SCHEMATIC DIAGRAM
1·289
XR·4136
Quad Operational Amplifier
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTIDN
The XR-4136 is an array of four independent internally
compensated operational amplifiers on a single silicon
chip, each similar to the popular 741. Good thermal
tracking and matched gain-bandwidth products make
these Quad Op-amps useful for active filter applications.
FEATURES
Direct Pin-for-Pin Replacement for RC4136 and
RM4136
Short-Circuit Protection
Internal Frequency Compensation
No Latch-Up
Wide Common-Mode and Differential Voltage Ranges
Matched Gain-Bandwidth
-INPUT A
-INPUT 0
+INPUT A
+INPUT 0
OUTPUT A
OUTPUT 0
OUTPUT B
Vee
+INPUT B
OUTPUT e
-INPUT B
+INPUT e
VEE
-INPUT e
APPLICATIONS
Buffer Amplifiers
SumminglDifferencing Amplifiers
Instrumentation Amplifiers
Active Filters
Signal Processing
Sample and Differencing
I to V Converters
Integrators
Simulated Components
Analog Computers
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-4136M
XR-4136CN
XR-4136CP
Ceramic
Ceramic
Plastic
- 55°C to + 125°C
O°C to + 70°C
O°C to + 70°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
XR-4136M
XR-4136C
Common Mode
Voltage Range
Output Short-Circuit Duration
Differential Input Voltage
Internal Power Dissipation
Ceramic Package:
Derate above TA = +25°C
Plastic Package:
Derate above TA = +25°C
Storage Temperature Range:
±22V
±18V
VEE to VCC
Indefinite
±30V
SYSTEM DESCRIPTION
750 mW
6 mW/oC
625 mW
5 mW/oC
- 65°C to + 150°C
The XR-4136 is a quad operational amplifier featuring
similar characteristics to standard 741-type devices.
As all four are monolithic, they have matched characteristics, including thermal tracking and gain bandwidth
products.
1-290
XR·4136
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = + 25°C, Vs = ± 15V, unless otherwise specified.
XR4136M
PARAMETERS
MIN
XR4136C
TYP
MAX
TYP
MAX
UNITS
SYMBOLS
Input Offset Voltage
.5
5.0
.5
6.0
mV
IViol
Input Offset Cu rrent
5.0
200
5.0
200
nA
Iliol
Input Bias Current
40
500
40
500
nA
lib I
Input Resistance
0.3
5.0
Large Signal Voltage Gain
50
Output Voltage Swing
Input Voltage range
Common Mode Rejection Ratio
CONDITIONS
Rs ::; 10 KIl
0.3
5.0
Mil
Rin
300
20
300
V/mV
AVOL
RL 2: 2 KIl
Vout = ±10V
±12
±14
±12
±14
V
Vout
RL 2: 10 KIl
±10
±13
±10
±13
V
Vout
RL 2: 2 KIl
±12
±14.0
±12
±14.0
V
ViCM
70
105
70
105
Supply Voltage Rejection Ratio
Power Consumption
Transient Response (unity gain)
Risetime
Overshoot
Unity Gain Bandwidth
MIN
2.0
Slew Rate (unity gain)
dB
CMRR
Rs :s 10 KIl
10
150
10
150
p.VIV
PSRR
Rs :s 10 KIl
210
340
210
340
mW
Pi
.13
5.0
.13
5.0
3.0
3.0
MHz
BW
1.5
1
V/p.s
dVoutidt
P.s
%
Vin = 20 mV
RL = 2 KIl
CL :s 100 pF
tr
to
RL 2: 2 KIl
Channel Separation (open loop)
105
105
dB
f = 10 KHz
Rs = 1 KIl
(Gain of 100)
105
105
dB
f = 10 KHz
Rs = 1 KIl
The following specifications apply for - 55°C :S TA :S + 125°C for XR·4136M: O°C :S TA :S + 70°C for XR·4136C
Input Offset Voltage
6.0
7.5
mV
IViol
Input Offset Current
500
300
nA
lIiol
Input Bias Current
Large,Signal Voltage Gain
Output Voltage Swing
1500
Rs :S 10 KIl
nA
Ib
25
15
V/mV
AVOL
±10
±10
V
Vout
RL 2: 2 KIl
mW
mW
Pi
Pi
Vs= ±15V
TA = High
TA = Low
mA
ISC
Power Consumption
180
240
Output Short·Circuit Current
45
800
300
400
100
240
300
400
45
RL 2: 2 KIl
Vout = ± 10V
TYPICAL PARAMETER MATCHING:
Test Conditions: TA = + 25°C, Vs = ± 15V unless otherwise noted
PARAMETERS
XR4136M
TYP
XR4136C
TYP
UNITS
SYMBOLS
CONDITIONS
Input Offset Voltage
±1.0
±2.0
mV
IViol
Rs 2: 10 KIl
Input Offset Current
±7.5
±7.5
nA
Iliol
Input Bias Current
±15
±15
nA
Ib
Voltage Gain
±0.5
±1.0
dB
AVOL
1·291
Rs 2: 2 KIl
XR·4136
OUTPUT
VEE (SUBSTRATEI
1/4 of XR-4136
EQUIVALENT SCHEMATIC DIAGRAM
1·292
XR·4202
Programmable Quad Operational Amplifier
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-4202 is an array of four independent operational
amplifiers on a single silicon chip. The operating current of the array is externally controlled by a single resistor or current source, allowing the user to trade-off
power dissipation for bandwidth.
FEATURES
Programmable
Micropower Operation
Wide Input Voltage and Common Mode Range
Internal Frequency Compensation
No Latch-Up
Matched Parameters
Short-Circuit Protection
!'Hz
= ±20 mV
Freq. = Hz:
RL = 20 KIl,
f:t.Vo = ±0.5 V
Freq. = 1 KHz:
RL = 10 KIl,
f:t.Vo = ±0.5V
Bandwidth = 100 Hz
Channel Separation
Equivalent Input Voltage Noise
en
±20 mV
f:t.Vo
to 10 KHz
PARAMETER MATCHING (\SET
PARAMETERS
= 75,.A (2))
MIN
TYP
MAX
UNITS
SYMBOL
Input Offset Voltage
1
±mV
Vos
Input Bias Current
10
±nA
IB
los
2
±nA
Gain-Bandwidth Product
Input Offset Current
100
±KHz
f1
Slew Rate
0.2
±V/,.s
dVo/dt
NOTES: 1. All tests refer to a single Op. amp unless otherwise specified.
2. Tests apply for parameter matching between any Op. amp pair.
3. Tests apply to four Op. amps and bias network.
1-295
CONDITIONS
Rss 10 KG
XR·4202
•
I
OUTPUT
BIAS
100
I
I
~ Rsn
I
-.L
ISEY
VEE ISUBSTRATEI
1/4 of XR-4202
EQUIVALENT SCHEMATIC DIAGRAM
1-296
XR·4212
Quad Operational Amplifier
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-4212 is an array of four independent internally
compensated operational amplifiers on a single silicon
chip, each similar to the popular 741, but with a power
consumption less than one 741. Good thermal tracking
and matched gain-bandwidth products make these
Quad Op-amps useful for active filter applications.
OUTPUT A
-INPUT A
+INPUT A
FEATURES
vee
Same Pinout as MC3403 and LM324
Low Power Consumption-50 mW typo and
120mW max.
Short-Circuit Protection
Internal Frequency Compensation
No Latch-Up
Wide Common-Mode and Differential Voltage Ranges
Matched Gain-Bandwidth
+INPUT B
-INPUT B
OUTPUT B
APPLICATIONS
Buffer Amplifiers
Summing/Differencing Amplifiers
Instrumentation Amplifiers
Active Filters
Signal Processing
Sample and Differencing
I to V Converters
Integrators
Simulated Components
Analog Computers
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-4212M
XR-4212CN
XR-4212CP
Ceramic
Ceramic
Plastic
-55°C to +125°C
O°C to + 70°C
O°C to + 70°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
XR-4212M
XR-4212C
Common Mode
Voltage
Output Short-Circuit Duration
Differential Input Voltage
Internal Power Dissipation
Ceramic Package:
Derate above TA = +25°C
Plastic Package:
Derate above TA = +25°C
Storage Temperature Range:
±22V
±18V
SYSTEM DESCRIPTION
VEE to Vee
The XR-4212 is a quad independently programmable
operational amplifier featuring improved performance
over industry standard devices such as the 741. Amplifier bias currents can be "programmed" by a single resistor to Pin 8. Bias currents can range from less than 1
/LA to over 75 p.A, thus affording the designer flexibility
along the device speed/power consumption trade off
curve.
Indefinite
±30V
750 mW
6 mW/oC
625 mW
5 mW/oC
- 65°C to + 150°C
1-297
XR·4212
ELECTRICAL CHARACTERISTICS
Test Conditions: TA
= + 25°C, Vs =
± 15V, unless otherwise specified.
XR·4212M
PARAMETERS
MIN
XR·4212C
TYP
MAX
Input Offset Voltage
1
Input Offset Current
10
BO
500
Input Bias Current
MIN
UNITS SYMBOLS
TYP
MAX
5.0
t
6.0
mV
IViol
50
10
50
nA
Iliol
BO
500
nA
IIbl
CONDITIONS
Rs :s to KO
Input Resistance
0.3
1.B
0.3
1.B
Mil
Rin
Large Signal Voltage Gain
20
60
5
40
V/mV
AvOL
RL'" 2 KIl
Vout = ±10V
±12
±14
±12
±14
V
Vout
RL'" 10 KO
±10
±12
±10
±12
V
Vout
RL'" 2 KIl
±12
±13.5
±12
±13.5
V
ViCM
70
105
70
105
Output Voltage Swing
Input Voltage Range
dB
CMRR
Rs :s 10 KIl
Supply Voltage Rejection Ratio
10
150
10
150
,..VN
PSRR
Rs :s 10 KO
Power Consumption
50
120
50
120
mW
PI
tr
Common Mode Rejection Ratio
Transient Response (unity gain)
Risetime
Overshoot
Unity Gain Bandwidth
2.0
0.07
20
0.07
20
,..s
%
to
3.0
3.0
MHz
BW
dVout/dt
Yin = 20 mV
RL = 2 KO
CL :s 100 pF
Slew Rate (unity gain)
1.6
1.6
V/,..s
Channel Separation (open loop)
120
120
dB
f = 10 KHz
Rs = 1 KIl
105
105
dB
f = 10 KHz
Rs = 1 KO
(Gain of 100)
+ 70°C for XR·4212C
The following specifications apply for - 55°C :S TA :S
+ 125°C for XR·4212M:
Input Offset Voltage
6.0
7.5
mV
IViol
Input Offset Current
200
200
nA
Iliol
Input Bias Current
O°C :S TA :S
1500
Large·Signal Voltage Gain
Output Voltage Swing
nA
Ib
20
5
V/mV
AvOL
±10
±10
V
Vout
Power Consumption
BOO
150
200
Output Short·Circuit Current
17
5
35
5
150
200
mW
mW
Pi
Pi
35
mA
ISC
17
RL'" 2 KIl
Rs :S 10 KIl
RL'" 2 KO
Vout = ±10V
RL'" 2 KIl
Vs= ±15V
TA = High
TA = Low
TYPICAL PARAMETER MATCHING:
Test Conditions: TA
= + 25°C, Vs =
± 15V unless ·otherwise noted
XR·4212M
PARAMETERS
XR-4212C
TYP
TYP
UNITS
SYMBOLS
CONDITIONS
Input Offset Voltage
±1.0
±2.0
mV
IViol
Rs 2: 10 KO
Input Offset Current
±7.5
±7.5
nA
Iliol
Input Bias Current
±15
±15
nA
Ib
Voltage Gain
±0.5
±1.0
dB
AlOl
1-298
Rs 2: 2 KO
XR·4212
OUTPUT
VEE (SUBSTRATE)
1/4 of XR-4212
EQUIVALENT SCHEMATIC DIAGRAM
1-299
XR·4739
Dual Low-Noise Operational Amplifier
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-4739 is a monolithic dual op amp featuring low
noise and a large gain bandwidth product. The device
is ideal for preamplifiers, signal processing equipment,
and active filters.
A OUTPUT
NC
FEATURES
NC
Internally Compensated Replacement for p.A 739
and MC1303
Signal-to-Noise Ratio 76dB (RIM 10 mV ref.)
Channel Separation 125dB
Unity Gain Bandwidth 3MHz
Output Short-circuit Protected
0.1 % Distortion at B.5V RMS Output into 2KD Load
NC
+A INPUT
-A INPUT
v-
APPLICATIONS
Buffer Amplifiers
SummingiDifferencing Amplifiers
Instrumentation Amplifiers
Active Filters
Signal Processing
Sample and Differencing
I to V Converters
Integrators
Simulated Components
Analog Computers
ORDERING INFORMATION
Part Number
Package
XR-4739CN
XR-4739CP
Ceramic
Plastic
Operating Temperature
O°C to
O°C to
+ 70°C
+ 70°C
SYSTEM DESCRIPTION
The XR-4739 dual low-noise operational amplifier is fabricated on a single silicon chip using the planar epitaxial process. It was designed primarily for preamplifiers
in consumer and industrial signal processing equipment. The device is pin compatible with the p.A739 and
MC1303, however, compensation is internal. This permits a lowered external parts count and simplified application.
ABSOLUTE MAXIMUM RATINGS
±1BV
Supply Voltage
500 mW
Internal Power Dissipation (Note 1)
±30V
Differential Input Voltage
±15V
Input Voltage (Note 2)
Storage Temperature Range
-65°C to + 150°C
Lead Temperature (Soldering, 60s)
300°C
Indefinite
Output Short-Circuit Duration (Note 3)
The XR-4739 is available in a ceramic or molded dual
inline 14 Pin package, and operates over the commercial temperature range from O°C to + 70°C.
1-300
XR·4739
ELECTRICAL CHARACTERISTICS
Tesl Condillons: TA = 25°C, VCC = ± 15V, unless otherwise specified.
PARAMETERS
MIN
TVP
MAX
UNITS
Input Offset Voltage
2.0
6.0
mV
Input Offset Current
5.0
200
nA
40
500
Input Bias Current
CONDITIONS
RS
s 10 kD
nA
Input Resistance
0.3
5.0
MD
Large-Signal Voltage Gain
20
60
K
RL __....__-r_-o
VOUT
RF
R,
V'N
IO"F1
6001!
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN LOOP FREQUENCY
RESPONSE
CLOSED LOOP FREQUENCY
RESPONSE
LARGE~IGNALFREQUENCY
RESPONSE
TYPICAL VALUES
V,",I,
I
YPICAL VALUES
'\
~
~
\
20~~~~~~-1-~-+-~
1,\
\
10 3
,04
105
108
101
\
,0 8
tlth)
INPUT BIAS CURRENT
OUTPUT SHORT·CIRCUIT
CURRENT
INPUT COMMON MODE
VOLTAGE RANGE
V S""5V
1.2
"- .........
-
r-"
I--f--- ----
[-- --+- -_._f--+-+--1
o. -[-- ._._--
-f--
I----!--j._--
L --[---
" [--- --L--t-+---t---I
55
-2& 0
-
/
/
SUPPLY VOLTAGE IVI
1·308
XR·553215532A
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
SUPPLY CURRENT
INPUT NOISE VOLTAGE DENSITY
102r------r-----,------~------
12
1
...
2
"'ex:ex:
a
TYP
r
l--
~
I~
<~
--
10
...........
TYP
~r----4-----i
"'
":;"
o
>
"'o
'"
>
....
t
2
....
:l
" 101 t-------lr-------+-------~-------J
'"
~
~
'"
102
t20
~
____~____~______~____~
102
10
103
SUPPLYVQLTAGE (V)
1()4
FREQUENCY (Hz)
TYPICAL APPLICATION
PREAMPLIFIER-RIAA/NAB
COMPENSATION
'-,'\
ON~"
l
.
BODE PLOT
~<"
f- ACTUAL RESPONSf
:~
'~
Z
RSL
~
"~
'\.
"
",
103
10'
,0'
.
..
ALL R£StS1QR VALUES AR£ IN OHMS
""
30
"
~
ACTUAL
/RESPONSE
~+-
10
,"
HIEOUENCV IH/
'SHECT TO PROVIDf SPECIFIED TRANSDUCER LOADING
OUTPUT NOISE
0 B mV ,m\ IWI TH INPUT SHORTE 01
BODE PLOT
JI
,....-~
10'
10'
103
,0'
10'
FREDUENCV tH,1
BOOE PLOT Of RIAI\ EOUAltlA liON AND THE
BODE PLOT OF NAB EOUALIZATION AND THE
RESPONSE REALIZED IN AN ACTUAL CIRCUIT
USINC THE XR SSJl
~!!~:!~3~E ALIZED IN THE ACTUAL CIRCUIT USrNO
EQUIVALENT SCHEMATIC DIAGRAM
ITr--------,--I----T----..---------~.-<) tVee
1/2 of XR·5532
1-309
XR·5533/5533A
Dual Low-Noise Operational Amplifier
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-5533 dual low-noise operational amplifier is especially deSigned for applications in high quality professional audio equipment. The low-noise, wide bandwidth
and output drive capability make it ideally suited for instrumentation and control circuits as well as active filter design.
BALANCEI
-INPUT A
COMP.A
COMPo A
The XR-5533A is the specially screened version of the
XR-5533 with guaranteed worst-case noise specifications.
OUTPUT A
BALANCE A
-VEE
FEATURES
OUTPUT B
BALANCE B
Direct Replacement for Signetics SEINE 5533
Wide Small-Signal Bandwidth: 10 MHz
High-Current Drive Capability
(10V rms into 6000 at Vs = ±18V)
High Slew Rate: 13 V/p.s
Wide Power-Bandwidth: 200 kHz
Very Low Input Noise: 4 nV/..JHZ
COMP.B
BALANCEI
COMP.B
APPLICATIONS
High Quality Audio Amplification
Telephone Channel Amplifier
Servo control Systems
Low-Level Signal Detection
Active Filter Design
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Power Supply
±22V
Input Common-Mode Range
-VEE to +VCC
±0.5V
Differential Input Voltage (Note 1)
Short Circuit Duration (Note 2)
Indefinite
Power Dissipation (Package Limitation)
Ceramic Package 14-Pin
750 mW
600mW
Plastic Package 14-Pin
5 mW/oC
Derate Above TA = 25°C
Storage Temperature
- 60 a C to + 150 a C
Part Number
Package
XR-5533AN
XR-5533AP
XR-5533N
XR-5533P
Ceramic
Plastic
Ceramic
Plastic
Operating Temperature
DoC
DoC
DoC
DoC
to
to
to
to
+70°C
+ 70°C
+ 70 a C
+ 70°C
SYSTEM DESCRIPTION
Note 1: Diodes protect the inputs against over-voltage. Therefore, unless current-limiting resistors are used, large
currents will flow if the differential input voltage exceeds O.BY. Maximum current should be limited to ±
The XR-5533 and XR-5533A are dual monolithic operational amplifiers featuring low noise and very large gain
bandwidth products. The devices have low output resistance and can drive 10 Vrms into 6000. Input noise
is 100% tested on the XR-5533A, and is typically only 4
nV/..fHZ. The small signal bandwidth is 10 MHz and
slew rate exceeds 13 V/p.S.
lOrnA.
Note 2: Output may be shorted to ground at Vee = VEE =
15V, TA = 25°C. Temperature and/or supply voltages
must be limited to ensure dissipation rating is not exceeded.
1-310
XR·5533/5533A
ELECTRICAL CHARACTERISTICS
Test Conditions: TA
=
25°e, Vee
=
VEE
=
15V unless otherwise specified.
XR-5533A
PARAMETERS
MIN.
XR-5533
TYP.
MAX.
0.5
MIN.
TYP.
MAX.
UNITS
4
5
0.5
4
5
mV
mV
20
300
400
20
300
400
nA
nA
500
1500
2000
500
1500
2000
nA
nA
SYMBOL
CONDITIONS
DC CHARACTERISTICS
Input Offset Voltage
VOS
Input Offset Current
lOS
Input Bias Current
TA = 25°C
TA = Full Range
IB
Large Signal Voltage
Gain
TA = 25°C
TA = Full Range
AvOL
25
15
Supply Current
(Each Amplifier)
100
4
25
15
100
8
4
V/mV
V/mV
8
mA
Output Swing
ICC
VOUT
±12
±15
Output Short Circuit
Current
Input Resistance
TA = 25°C
TA = Full Range
±13
±16
±12
±15
±13
±16
V
V
38
mA
38
ISC
30
100
30
100
kO
RIN
Common·Mode
Range
±12
±13
±12
±13
V
ViCM
Common· Mode
Rejection
70
100
70
100
dB
CMRR
p.VN
PSRR
Power Supply
Rejection
Channel Separation
10
100
10
100
110
110
dB
20
20
nsec
tr
20
20
%
to
6
2.2
6
2.2
VlmV
V/mV
Unity-Gain
Bandwidth
10
10
MHz
Slew Rate
13
6
13
6
V/p.lsec
V/p.lsec
Power Bandwidth
95
95
kHz
200
200
kHz
7
4
nVl-JRz
nV/-JRz
1.5
0.4
2.5
0.6
pAl-JRz
pAl-JRz
0.9
0.9
dB
RL "
VO=
TA =
TA =
6000.
±10V
25°C
Full Range
RL = Open
RL " 6000
VCC = VEE = 15V
VCC = VEE = 18V
(Note 2)
f = 1 kHz,
RS = 5 kO
AC CHARACTERISTICS
Transient Response
Rise Time
Overshoot
AC Gain
Voltage Follower
RL = 6000,
Cc = 22 pF
CL = 100 pF
VIN = 50 mV
f = 10 kHz
Cc = a
Cc = 22 pF
BW
Cc = 22 pF,
CL = 100 pF
Cc = a
Cc = 22 pF
fp
VOUT = ±10V,
Cc = 22 pF
Cc = a pF
NOISE CHARACTERISTICS
Input Noise Voltage
en
5.5
3.5
7
4.5
Input Noise Current
Broadband Noise
Figure
fa = 30 Hz
fa = 1 kHz
in
1-311
fa = 30 Hz
fa = 1 kHz
RN
FS = 5 kO
f = 10Hzto
20 kHz
XR·5533/5533A
TEST CIRCUITS
FREQUENCY COMPENSATION ANO OFFSET
VOLTAGE AOJUSTMENT CIRCUIT
CLOSED LOOP FREQUENCY RESPONSE
".
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN LOOP FREQUENCY RESPONSE
SLEW-RATE AS A FUNCTION OF
COMPENSATION CAPACITANCE
Vs"
TYPICAL VALUES
CLOSED LOOP FREQUENCY
RESPONSE
15V
ee
0-
~
'~ee.o
Il
\
CC=22PF"~
~
I\.
N
10102,03,04
105
106
"
TV'
f'-.
107
10l'04
FREOUENCYIH,)
TO S
CC(pF)
LARGE-SIGNAL FREQUENCY
RESPONSE
106
10 '
108
FReQUENCY (HI)
OUTPUT SHORT -CI RCUIT
CURRENT
INPUT BIAS CURRENT
VS"'5V
Vs=' 15V
VS=t16V
TYPICAL VALUU
de't- J
OpF
./
\V +-- 22~F
47~F
r\
_
l - el - e-
...... r---,
r- t--
,
0.8
TYP
TV'
l\
\\
"'" c-.... r-
0.4
1--
~~
102
103,04
105
106
107
"
75
100
-25
125
25
5(1
75
100
125
FREQUENCY (Hz}
INPUT COMMON MODE
VOLTAGE RANGE
INPUT NOISE VOLTAGE
DENSITY
SUPPLY CURRENT
PEROP-AMP
102
TVPICAL VALUES
TV'
1#
#
VPOS
~
....-- r-
-
~
~
~
10
~
~
101
102
! 10
SUPPLY VOLTAGE WI
! 10
SUPPLY VOLTAGE tV)
1-312
~
__1-T_V_'~____~
~
~
#V
,-----r---,--,-----,,---,
10" 0
r---t--1---t----i---4
'-_~
10
_ _~_ _~_~_ _--'
102
103
104
FREOUENCV (HI)
XR·5533/5533A
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
INPUT NOISE CURRENT DENSITY
BROADBAND INPUT
NOISE VOLTAGE
TOTAL INPUT NOISE DENSITY
102
106
101 . - - . , - - . . . , . . - - - , - - . . . . , . - - - . - - ,
TYPICAL VALUES
~
~
>
~
~
~
g
~TYP
~
101
~
105
104
10Hz
/
103
/ V':
102
./ ~
10
,..,
1kHz
I-'
THERMAL NOISE OF
V
SOURCE RESISTANCE
101
101
102
102
102
10
102
103
10
104
102
103
104
FREQUENCY (Hzl
106
102
106
,03
104
Rsml
105
106
RSlm
TYPICAL APPLICATION
PREAMPLIFIER-RIAA/NAB
COMPENSATION
70
60
"'-'\
0.22
IN~
m
lR~'
~"
40
z
~
1M
RIA,A
NAB
.
30
BODE PLOT
~-~
50
ACTUAL RESPONSE
"
m
z
'~
~
-'r\.
'\
30
20
20
101
103
102
FREQUENCY (Hz)
·SELECT TO PROVIDE SPECIFIED TRANSDUCER LOADING
.tI
104
"
BOOE PLOT OF RIAA EQUALIZATION AND THE
""
105
ACTUAL
/RESPONSE
~
-
10
101
102
103
104
105
FREQUENCY (Hzl
BODE PLOT OF NAB EQUALIZATION AND THE
OUTPUT NOISE;;' 0.8 mV rlnS IWITH INPUT SHORTED)
RESPONSE REALIZED IN AN ACTUAL CIRCUIT
RESPONSE REALIZED IN THE ACTUAL CIRCUIT USING
ALL RESISTOR VALUES ARE IN OHMS.
USING THE KR·5533.
THE XR-5533
EQUIVALENT SCHEMATIC DIAGRAM
'/2 of
KR·SS33
1-313
(SUBSTRATE)
XR·5534/5534A
Low-Noise Operational Amplifier
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-5534 is a high performance low-noise operational amplifier especially designed for application in
high quality and professional audio equipment. It offers
five-fold improvement in noise characteristics, output
drive capability and full-power bandwidth over conventional74Hype op amps. The op amp is internally compensated for gain equal to, or higher than, three. The
frequency response can be optimzed with an external
compensation capacitor for various applications such
as operating in unity gain mode or driving capacitive
loads.
XR·5534
BALANCE/COMP
+Vcc
OUTPUT
The XR-5534A is a specially-screened version of the
XR-5534, with guaranteed noise specifications.
-Vu
4
'-------15
COMPENSATION
FEATURES
Direct Replacement for Signetics NE/SE 5534
Wide Small-Signal Bandwidth: 10 MHz
High-Current Drive Capability
(10V rms into 6000 at Vs = ± 18V)
High Slew Rate: 13 V/p.s
Wide Power-Bandwidth: 200 kHz typo
Very Low Input Noise: 4 nV/.JHi. typo
ORDERING INFORMATION
APPLICATIONS
Part Number
Package
Operating Temperature
High Quality Audio Amplification
Telephone Channel Amplifiers
Servo Control Systems
Low-Level Signal Detection
Active Filter Design
5534AM
5534M
5534ACN
5534CN
5534ACP
5534CP
Ceramic
Ceramic
Ceramic
Ceramic
Plastic
Plastic
- 55°C to + 125°C
- 55°C to + 125°C
O°C to + 70°C
O°C to +70°C
O°C to +70°C
O°C to + 70°C
ABSOLUTE MAXIMUM RATINGS
SYSTEM DESCRIPTION
Power Supply
±22 V
Input Common-Mode Voltage
+VCC to -VEE
Differential Input Voltage (Note 1)
±0.5 V
Power Dissipation (Package Limitation)
Ceramic Package
385 mW
Plastic Package
300 mW
2.5 mW/oC
Derate Above + 24°C
Short Circuit Duration (Note 2)
Indefinite
Storage Temperature
- 60°C to + 150°C
The XR-5534 and XR-5534A are monolithic operational
amplifiers featuring low noise and a very large gain
bandwidth product. The devices offer low output resistance and can drive 10 Vrms into 6000. Input noise is
100% tested on the XR-5534A, and is typically only 4
nV/..fHz. The small signal bandwidth is 10 MHz and
slew rate exceeds 13 V/p.S.
Note 1: Diodes protect the inputs against over-voltage. Therefore, unless current-limiting resistors are used, large
currents will flow if the differential input voltage exceeds 0.6V. Maximum current should be limited to ±
10 rnA.
Note 2: Output may be shorted to ground at Vs = ± 15V, TA =
25°C. Temperature and/or supply voltages must be limited to ensure dissipation rating is not exceeded.
Reverse parallel diodes provide input prV
INPUT BIAS CURnENT
,.---;--:~V'.!UiiV
r - c-- ,.- f - --1-- - \ - -
-\-- . _-1---+--1
.• TYPICAL VALUn_
._-
-'--'I--~-f-
-
" " - f-..._. ~-I;;::- .--1--1-I --I -I'-_TYP
--1--
. --
_. -
•.•
1-
0.'
r\.
._-
--- -
i'-
-+-+-=+:::j::==!-.....j
._+--j--j-+---t--
IH,}
-- f - -- -
TVP
~
0.'
- - - ---f-f--t--+--+--I
-56
INPUT COMMON MODE
VOLTAGE RANGE
0
-Zi
25
50
SUPPI.V CURRENT
INPUT NOISE VOLTAGE DENSITY
10-0
TV'
I-'"
/" l-
-
--
·
f"".....
m
·
·
~
SUPPLY VOl. TAGE 11,11
75
T"fCI
FREOUENCY IHd
·
10
SUPPLY VOLTAGE IV)
1-316
.0>
to:l
...
XR·5534/5534A
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
INPUT NOISE CURRENT DENSITY
."
,"
I'-...
",
",
-",
",
...
.. ,-,-,-,-,-,-,
,
T'("'CAL VALUES
.
~Y'
BROADBAND INPUT
NOISE VOLTAGE
TOTAL INPUT NOISE DENSITY
10 HI
/
/ [L
"H,
-./ ~
~
~
._-
THERMAL NOISE OF
StlURCE RESISTANCE
", I--+--+--+--+--+--i
10'
", L.._L-_L-_L-_L-_L---J
10l!
103
104
10"
108
1'15 1:11
TYPICAL APPLICATION
PREAMPLIFIER-RIAA/NAB
COMPENSATION
",
",
",
....
",
",
...
",
....
...
FAfOUENCV,th1
·SIUCY TO 'ROVlat SPECIFIED TRANSOUCER ~OAOING
OUT1"UrNOIS£ 08",V,~'W"HlfIIPUrSHORJfOt
ALL RESISTOR VALUES ARE IN OHMS
BALANCE
BODE PLOT OF NAB H1UAlIZA110N ,.ND TIt!;
",!:SPONSE REALIZED IN THE A.CTUAl CIRCUIT USING
THE XR-!>!oJ".
BOD[ PLor OF RIAA fOUAlllAT'QN "NO THE
RE$PCNSf REALIZED IN AN ACTUAL CIRelllr
USING THE "R-5!>34
BALANCE/COMP
eOMI'.
ISUBSTRATfI
EQUIVALENT SCHEMATIC DIAGRAM
1-317
Voltage Regulators
XR·1468/1568
Dual·Polarity Tracking Voltage Regulator
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-1468/1568 is a dual polarity tracking voltage
regulator, internally trimmed for symmetrical positive
and negative 15V outputs. Current output capability is
100 rnA, and may be increased by adding external pass
transistors. The device is intended for local "on-card"
regulation, which eliminates the distribution problems
associated with single point regulation.
OND
BALANCE
ADJUST
COMP>
The XR-1468CN and XR-1568N are guaranteed over
the O°C to 70°C commercial temperature range. The
XR-1568M is rated over the full military temperature
range of - 55°C to + 125°C.
SENSE>
FEATURES
N.C.
N.C.
Internally Set for ± 15V Outputs
± 100 rnA Peak Output Current
Output Voltages Balanced Within 1 % (XR-1568)
0.06% Line and Load Regulation
Low Stand-By Current
Output Externally Adjustable from ±8 to ±20 Volts
Externally Adjustable Current Limiting
Remote Sensing
vee
ORDERING INFORMATION
APPLICATIONS
Part NumbBr
Main Regulation in Small Instruments
On-Card Regulation in Analog and Digital Systems
Point-of-Load Precision Regulation
XR-1568M -55°C to + 125°C ± 150 mV maxCeramic
XR-1568N
O°Cto +70°C ±150mVmaxCeramic
XR-1468CN O°C to + 70°C ±300 mV maxCeramic
ABSOLUTE MAXIMUM RATINGS
SYSTEM DESCRIPTION
Power Supply
±30 Volts
4.0 Ohms
Minimum Short-Circuit Resistance
Load Current, Peak
±100 rnA
Power Dissipation
Ceramic (N) Package
1.0 Watt
6.7 mW/oC
Derate Above + 25°C
Operating Temperature
- 55°C to + 125°C
XR-1568M
O°C to + 70°C
XR-1568/XR-1468C
Storage Temperature
- 65°C to + 150°C
The XR-1468/1568 is a dual polarity tracking voltage
regulator combining two separate regulators with a
common reference element in a Single monolithic circuit, thus providing a very close balance between the
positive and negative output voltages. Outputs are internally set to ± 15 Volts but can be externally adjusted
between ±8.0 to ±20 Volts with a single control. The
circuit features ± 100 rnA output current, with externally adjustable current limiting, and provision for remote voltage sensing.
1-318
Temperature
Output Offset
Package
XR·1468/1568
ELECTRICAL CHARACTERISTICS
= + 20V, VEE = - 20V, C1 = C2 = 1500 pF, C3 = C4 = 1,0 ",F, RSC + = RSC - = 4.00. I L +
= IL - = 0, TC = +25°C unless otherwise noted.)
Test conditions: (VCC
XR·1468C
PARAMETERS
Output Voltage
XR·1568
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
14.5
15
15.5
14.8
15
15.2
Vdc
Input Voltage
-
-
30
-
-
30
Vdc
Input-Output Voltage Differential
2.0
-
-
2.0
-
-
Vdc
Output Voltage Balance
-
Line Regulation Voltage
(Vin = 18V to 30V)
(TLt to TH)tt
-
±50
-
-
±300
-
10
20
-
±50
mV
±150
mV
-
10
20
-
Load Regulation Voltage
(lL = 0 to 50 mA, TJ
(TA = TL to TH)
mV
= constant)
Output Voltage Range
=
-
-
10
30
-
-
10
30
8.0
-
20
8.0
-
20
Vdc
dB
-
75
-
-
75
-
Output Voltage Temperature Stability
(TL to TH)
-
0.3
1.0
-
0.3
1.0
Short-Circuit Limit
(RSC = 10 ohms)
-
60
-
-
60
-
Output Noise Voltage
(BW = 10 Hz - 10 kHz)
-
100
-
-
100
-
Positive Standby Current
(Vin = +30V)
-
2.4
4.0
-
2.4
4.0
Negative Standby Current
(Vin = -30V)
-
1.0
3.0
-
1.0
3.0
Long-Term Stability
-
0.2
-
-
0.2
-
Ripple Rejection (f
120 Hz)
mA
",V(rms)
mA
mA
+ 70°C for XR-1468C/1568
+ 125°C for XR-1568M
tTL = O°C for XR-1468C/1568
= -55°C for XR-1568M
INPUT
%
%/KHr
TJ = Junction Temp.
TC = Case Temp.
..
l.lo_-__o!..fv~cc;--~v;;,~o----o INPUT H
.
INPUT (.)
7
•
"oc
"oc'
•
lOOK
Vee
VEE
Vo
Vo-
SENSE
SENSE
(.)
H
14 V'-I
GND
BlI"j
I
INPU TI-)
"sc·
10
11
•
lOOK
eOMPEN(~t ljOMPENH
1500pF
'V.
+lSY4h
1.0,.F
e3
1.0"F
C4
1500pF
-Vo
-16Vck
'"
C1 ... C21houkl blioelted. dOle to Iht device as possible. A 0.1 pF Cll'lfnic Cllpecitor
may be required on the input I..... it .... dft'a it loa... 11'1 appreciable distlnC' tram
'"
C4;.O,uF
C3 1.0"F
th.rectlf_'i_~
'Vo
·'&Vdc
C3"" C4 ...., be inInaId to irrtpnwe to.d tnnlient response and to rtduct. the output
non. volotl. At low ten'I.,..etu,. opwltion. it m8y be ,.....y '0 bypns C4 with •
O.1IAF . .emk: dilc apecltar.
Figure 1. Basic 50 rnA Regulator
-=-
-Yo
-15Ydc
Figure 2. Voltage Adjust and Balance Adjust Circuit
1-319
XR·494
Pulse-Width Modulating Regulator
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-494 is a monolithic pulse width modulating regulator designed to contain all the blocks necessary for
a switching regulator. Included in a 16 pin dual in-line
package is a voltage reference, OSCillator, control logic,
error amplifiers, and dual uncommitted outputs. This
device can be used for switching regulators of either
polarity, polarity converters, transformer coupled DC to
DC converters, transformerless voltage doublers, and
many other power control applications. The XR-494M is
fully specified for operation over the full military temperature range from - 55°C to + 125°C, while the XR494CN and XR-494CP are deSigned for commercial applications over O°C to + 70°C.
•0.
INV
INPUT
.0•
16
1
,.,
,.,
INPUT
INPUT
FEED
REF
OUT
BACK
DEAD
TIME
CONTROL
INV
INPUT
OUTPUT
4
CONTROL
FEATURES
Complete PWM Power Control Circuitry
Uncommitted Outputs for 200-mA Sink or Source
Output Control Selects Single-Ended
or Push-Pull Operation
Internal Circuitry Prohibits Double Pulse
at Either Output
Variable Dead Time Provides Control Over Total
Range
Internal Regulator Provides a Stable
5-V Reference Supply
Circuit Architecture Provides Easy Synchronization
ORDERING INFORMATION
Amplifier Input Voltages
Output Current
Supply Voltage
Collector Output Voltage
Power Dissipation
Total, at or below 25°C
Ceramic Package
Derate above +28°C
Plastic Package
Derate above +41°C
Operating Temperature
- 55°C to + 125°C
O°C to + 70°C
O°C to + 70°C
All functions required to construct a pulse-width modulating regulator are incorporated on a single monolithic
chip in the XR-494. The device is primarily designed for
power supply control and contains a on-chip five volt
regulator, two error amplifiers, an adjustable oscillator,
dead-time control comparator, a pulse-steering flip-flop,
and output control circuits. Either common emitter or
emitter follower output capability is provided by the uncommitted output transistors. Single ended or push-pull
output operation may be selected through the output
control function. The XR-494 architecture prohibits the
possibility or either output being pulsed twice during
push-pull operation. The internal amplifiers's circuitry
allows for a common-mode input voltage range of - 0.3
volt to VCC - 2 volts. The dead time control comparator provides approximately 5% dead time unless the
dead time control is externally driven. The on-chip
oscillator may be used to drive the common XR-494
circuitry and provide a sawtooth input for associated
control circuitry in synchronous multiple-rail power
supplies, or may be bypassed by terminating RT (Pin 6)
to the reference output and providing a sawtooth input
to CT (Pin 5).
Pulse-Width Modulated Power Control Systems
Switching Regulators
=
Package
Ceramic
Ceramic
Plastic
SYSTEM DESCRIPTION
APPLICATIONS
ABSOLUTE MAXIMUM RATINGS, TA
Part Number
XR-494M
XR-494CN
XR-494CP
25°C
VCC = ± 0.3 Volts
250 mA
41 Volts
41 Volts
1000 mW
1-320
XR·494
RECOMMENDED OPERATING CONDITIONS
XR-494CN
XR-494CP
XR-494M
PARAMETERS
Supply voltage, VCC
Amplifier input voltages, VI
MIN
MAX
MIN
MAX
UNIT
7
40
7
40
V
-0.3
VCC -2
-0.3
VCC -2
V
40
40
V
200
200
mA
Collector output voltage, Vo
Collector output current
(each transistor)
Current into feedback terminal
0.3
Timing capacitor, CT
Timing resistor, RT
Oscillator frequency
Operating free-air temperature, TA
SWITCHING CHARACTERISTICS TA
0.3
mA
0.47
10,000
0.47
10,000
nF
1.8
500
1.8
500
kO
1
300
1
300
kHz
-55
125
0
75
°c
= 25°C
.-
Typ.1
MAX.
UNIT
Output Voltage Rise Time
Output Voltage Fall Time
100
25
200
100
ns
ns
Common-Emitter Configuration,
See Figure 1
Output Voltage Rise Time
Output Voltage Fall Time
100
40
200
100
ns
ns
Emitter-Follower Configuration,
See Figure 2
MIN.
PARAMETER
TEST CONDITIONS
1. All typical values except for temperature coefficients are at TA = 25°C.
'--C rcr
-I
"""""..
:
..
':w'
_______ -1
Cl
I'NCLUO.S
J
,. ~f
'~OBE
... 0
.. -±=f~>---~--------C'
CT-i--C=:::J
'------E.
ERROR
AUPLIFJERS
NONINVERTING INPUT ------l~
INYERllNG INI'UT - -_ _ _
--1.,
**~~I~------l~
-------1;/
INYEIITING INt'UT
FEEDBACK---------_
EQUIVALENT SCHEMATIC DIAGRAM
Vee. ,sv
r-"""1,----<. Vee:
VOlTAGE
ATet
.--.,.-_ _ .Vee
VOLTAGE
---.
ATCt
VOLUOI:
ATC,
orAD-TIME
CONTROL
'"PUT
.",
,,
nED.,.,Clt
I
Uyr'------+,---------C==C1
I
"
,
r-~_-;-J\-~-r~~_~r-----C2
RT-------r:~::J
eT
--r--L__...J
......-----E2
DEAD O
. "'V~====~~----------~:r~~__:t~~~~~-r~~~~~
r-------,
TIME---IICONTROL
I
I
Vee
I
NONINYERTING INPUT
INVERTING INPUT
NONINYEATING INPUT
INVERTING INPUT
I
----------fl,
----------t;"
---------...p,
----------t;"
1 - - - - - ~~~
I
1
I
I t---~~----~--~~-------------GND
I
1
Vz
L _ _ _ _ _ _ ..1
FEEDBACK - - - - - - - - - - - - - - - - - - '
EDUIVALENT SCHEMATIC DIAGRAM
ERROR AMPLIFIER
UNDER TEST
FUNCTION TABLE
INPUTS
VREF
0--------1
Figure 4. Error Amplifier Characteristics
OUTPUT
CONTROL
STEERING
INPUT
Grounded
Open
AtVref
At Vref
At Vref
Open
VIOAV
OUTPUT FUNCTION
Single-ended or parallel
output
Normal push·pull operation
PWM Output at 01
PWM Output at 02
OSCILLATOR FREQUENCY .nd
FREQUENCY VARIATION' ....
TIMING RESISTANCE
AMPliFIER VOLTAGE AMPLIFICATION
Vee .. 15¥
= 2S"C
fA
I-- ,.
I
r--
a.oGlpF
Vcc
'\
,
,
" '--'--'-...LJ..J..LUL__.l-.L..i--1..l..LllL30..--'---'-,'-'-.l..U.JJ
1IC
10K
tOK
tCllllli
Ry-lIMiNG RESlSTANCE-U
,
,
1 Frequency variation Is the change In oscillator frequency that
occurs over the full temperature range.
l'5\'
;:0 ::.c-
j\.
'" "-
'" "~
~
~
t-FREQUENCy_1tJ:
Figure 5. Oscillator Frequency and Frequency Varlation1 vs
Timing Resistance
Figure 6. Amplifier VoHaga Amplification vs Frequency
1-327
XR·15/25/3524
Pulse-Width Modulating Regulator
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-1524 family of monolithic integrated circuits
contain all the control circuitry for a regulating power
supply inverter or switching regulator. Included in a 16pin dual-in-line package is the voltage reference, erroramplifier, oscillator, pulse width modulator, pulse steering flip-flop, dual alternating output switches and current limiting and shut-down circuitry. This device can be
used for switching regulators of either polarity, transformer coupled DC to DC converters, transformerless
voltage doublers and polarity converters, as well as
other power control applications. The XR-1524 is specified for operation over the full military temperature
range of - 55°C to + 125°C, while the XR-2524 and XR3524 are designed for commercial applications of O°C
to + 70°C.
FEATURES
Direct Replacement for SG-1524/2524/3524
Complete PWM power control circuitry
Single ended or push-pull outputs
Line and load regulation of 0.2%
1 % maximum temperature variation
Total supply current less than 10 mA
Operation beyond 100 kHz
ORDERING INFORMATION
APPLICATIONS
Switching Regulators
Pulse-width Modulated Power Control Systems
Package
Operating Temperature
Ceramic
Ceramic
Plastic
Ceramic
Plastic
-55°C to +125°C
O°C to + 70°C
O°C to + 70°C
O°C to + 70°C
O°C to + 70°C
SYSTEM DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
Input Voltage
Output Current (each output)
Reference Output Current
Oscillator Charging Current
Power Dissipation
Ceramic Package
Derate above + 25°C
Plastic Package
Derate above + 25°C
Operating Temperature Range
XR-1524
XR-2524/XR-3524
Storage Temperature Range
Part Number
XR-1524M
XR-2524N
XR-2524P
XR-3524N
XR-3524P
The XR-1524/2524/3524 pulse width modulating regulator is a complete monolithic switching regulator. An internal 5V reference, capable of supplying up to 50 mA
to external loads, provides an on board operating standard. The oscillator frequency and duty cycle are adjusted by an external RC network. Regulation is controlled by an error amplifier which, combined with the
sense amplifier, also allows current limiting and remote
shutdown functions. The outputs of the XR-1524/25241
3524 are two identical NPN transistors with both emitters and collectors uncommitted. Each output transistor has antisaturation circuitry for fast response and local current limiting set at 100 mA.
40V
100 mA
50 mA
5 mA
1000 mW
8 mW/oC
625 mW/oC
5 mW/oC
- 55°C to + 125°C
O°C to + 70°C
-65°C to +150°C
1-328
XR·15/25/3524
ELECTRICAL SPECIFICATIONS
Test Conditions: TA = - 55°C to + 125°C lor the XR-1524 and O°C to + 70°C lor the XR-2524 and XR-3524, VIN
20V, and I = 20 kHz, unless specilied otherwise.
XR·1524/
XR·2524
PARAMETERS
=
XR·3524
MIN TYP MAX MIN TYP MAX UNITS
CONDITIONS
REFERENCE SECTION
Output Voltage
Line Regulation
Load Regulation
Ripple Rejection
Short Circuit Current Limit
Temperature Stability
Long Term Stability
4.8
5.0
10
20
66
100
0.3
20
5.2
20
50
4.6
1
5.0
10
20
66
100
0.3
20
5.4
30
50
1
V
mV
mV
dB
mA
%
mV/khr
VIN = 8 to 40 Volts
IL = 0 to 20 mA
I = 120 Hz, TA = 25°C
VREF = 0, TA = 25°C
Over Operating Temperature Range
TA = 25°C
KHz
%
%
%
V
/LS
CT = .001 /LF, RT = 2 KO
RT and CT constant
VIN = 8 to 40 Volts, TA = 25°C
Over Operating Temperature Range
Pin3, TA = 25°C
CT = .01 mfd, TA = 25°C
mV
/LA
dB
V
dB
MHz
V
VCM - 2.5 Volts
VCM = 2.5 Volts
OSCILLATOR SECTION
Maximum Frequency
Initial Accuracy
Voltage Stability
Temperature Stability
Output Amplitude
Output Pulse Width
300
5
300
5
1
2
1
2
3.5
0.5
3.5
0.5
ERROR AMPLlFIEO SECTION
Input Offset Voltage
Input Bias Current
Open Loop Voltage Gain
Common Mode Voltage
Common Mode Rejection Ratio
Small Signal Bandwidth
Output Voltage
72
1.8
0.5
2
80
5
10
3.4
60
1.8
70
3
0.5
2
2
80
10
10
3.4
70
3
3.8
0.5
45
0
3.8
TA
TA
AV
TA
= 25°C
= 25°C
= 0 dB, TA =
= 25°C
25°C
COMPARATOR SECTION
Duty Cycle
Input Threshold
Input Threshold
Input Bias Current
0
1
3.5
1
45
%
V
V
/LA
220
mV
1
3.5
1
CURRENT LIMITING SECTION
Sense Voltage
Sense Voltage Temp. Coef.
Common Mode Voltage
190 200
0.2
-1
210
+1
180 200
0.2
-1
% Each Output On
Zero Duty Cycle
Max. Duty Cycle
Pin 9 = 2V with Error Amplifier
Set for Max. Out, TA = 25°C
mV/oC
+1
V
OUTPUT SECTION (Each Output)
Max. Collector-Emitter Voltage
Collector Leakage Current
Saturation Voltage
Emitter Output Voltage
Rise Time
Fall Time
TOTAL STANDBY CURRENT
40
17
40
0.1
1
18
0.2
0.1
50
2
8
10
17
0.1
1
18
0.2
0.1
50
2
8
10
(Excluding oscillator charging
current, error and current limit
dividers, and with outputs
open)
1-329
V
/LA
V
V
/LS
/LS
VCE = 40V
IC = 50 mA
VIN = 20V
RC = 2 KO, TA
RC = 2 KO, TA
mA
VIN
= 40V
=
=
25°C
25°C
XR·15/25/3524
OPEN LOOP TEST CIRCUIT
~
2k
lW
V..!..N
12
13
111-5 141--
15
OSC.OUTO- 3
VREFo-~ 16
XR-1524
6
8
7
9
1
2
10
QRAMP( )IN.I..~
INPUT
INPUT
COMPo ( )
V IN
8-40V
2k
0.1
CT
RT
L-:
10k
t,
4
2k
lW
~ OUTPUTS
SHUTj(rURREN
DOWN
LIMIT
10k
~'k
>-
2k
DESCRIPTION OF CIRCUIT OPERATION
VOLTAGE REFERENCE SECTION
The internal voltage reference and regulator section
provides a 5-volt reference output at pin 16. This voltage also serves as a regulated voltage source for the
internal timing and control circuitry. This regulator may
be bypassed for operation from a fixed 5-volt supply by
connecting pins 15 and 16 together to the input voltage.
In this configuration, the maximum input voltage is 6.0
volts.
J
ILTOI.OA
DEPENDING
ON CHOICE
FOROI
This reference regulator may be used as a 5-volt source
for other circuitry. It will provide up to 50 mA of current
itself and can easily be expanded to higher currents
with an external PNP as shown in Figure 2.
Figure 2. Using the Internal Regulator as 5V Power Supply
for External CircuHry
+SV TO All
INTERNAL CIRCUITRY
INV. INPUT
1
. SENse
GROUND
0--J.
ISUBSTRATEI 8
9
COMPENSATION
Ik
10I).-lVVl_-C
SHUT DOWN
Figure 1. Detailed System Block Diagram of XR-1524
1-330
":"
XR·15/25/3524
OSCILLATOR SECTION
10
The oscillator section in the XR-1524 uses an external
resistor (RT) to establish a constant charging current into an external capacitor (CT)' While this uses more current than a series connected RC, it provides a linear
ramp voltage on the capacitor which is also used as a
reference for the comparator. The charging current is
equal to 3.6Y + RT and should be kept within the range
of approximately 30 p.A to 2 mA, I.e., 1.8K < RT <
100K.
I'
V
2
o.
The oscillator period is apprQximately T = R'jCT where
T is in microseconds when RT = ohms and CT =
microfarads.
-~
•
V
o. 3
.001
The use of Figure 3 allows the selection of RT and CT
for a wide range of operating frequencies. Note that for
series regulator applications, the two outputs can be
connected in parallel for an effective 0 - 90% duty cycle and the frequency of the oscillator is the frequency
of the output. For push-pull applications, the outputs
are separated and the flip-flop divides the frequency
such that each output's duty cycle is 0 - 45% and the
overall frequency is 1/2 that of the oscillator.
100
V
0
.002
.005
.01
.02
.05
TIMING CAPACITOR VALUE Itrl - MICROFARADS
Figure 4. Output Stage Dead Time as a Function of the
Timing Capacitor Value
If it is desired to synchronize the XR·1524 to an external
clock, a pulse of '" + 3 volts may be applied to the oscillator output terminal with R'jCT set slightly greater
than the clock period. The same considerations of
pulse width apply. The impedance to ground at this
point is approximately 2K ohms.
~+-+--+--1--4..--r-,.r...,..-h..-l
If two or more XR-1524 circuits must be synchronized
together, one must be designated as master with its
R'jCT set for the correct period. The slaves should each
have an R'jCT set for approximately 10% longer period
than the master with the added requirement that CT
(slave) = 1/2 CT (master). Then connecting pin 3 on all
units together will insure that the master output pulse which occurs first and has a wider pulse width - will reset the slave units.
ERROR AMPLIFIER SECTION
10
:10
50
100
200
500
1ms
The error amplifier is a simple differential-input, transconductance amplifier. The output is the compensation
terminal, pin 9, which is a high-impedance node (RL ...
5 MO). The gain is
2ms
OSCILLATOR PERIOD - MICROSECONDS
Figure 3. Oscillator Period as a Function of RT and CT
8 IC RL
Ay = gm RL = - - - ' " .002 RL
2kT
The range of values for CT also has limits as the discharge time of CT determines the pulse width of the oscillator output pulse. This pulse is used (among other
things) as a blanking pulse to both outputs to insure that
there is no possibility of having both outputs on simultaneously during transitions. This output dead time relationship is shown in Figure 4. A pulse width below approximately 0.5 microseconds may allow false triggering of one output by removing the blanking pulse prior
to the flip-flop's reaching a stable state. If small values
of CT must be used, the pulse width may still be expanded by adding a shunt capacitance ('" 100 pF) to
ground at the oscillator output. (Note: Although the oscillator output is a convenient oscilloscope sync input,
the cable and input capacitance may increase the
blanking pulse width slightly.) Obviously, the upper limit
to the pulse width is determined by the maximum duty
cycle acceptable. Practical values of CT fall between
.001 and 0.1 p.F.
and can easily be reduced from a nominal of 10,000 by
an external shunt resistance from pin 9 to ground, as
shown in Figure 5.
In addition to DC gain control, the compensation terminal is also the place for AC phase compensation. The
frequency response curves of Figure 5 show the uncompensated amplifier with a single pole at approximately 200 Hz and a unity gain cross-over at 5 MHz.
Typically, most output filter designs will introduce one or
more additional poles at a significantly lower frequency.
Therefore, the best stabilizing network is a series R-C
combination between pin 9 and ground which introduces a zero to cancel one of the output filter poles. A
good starting point is 50 KO plus .001 p.F.
1-331
XR·15/25/3524
R2
r--Ni.--
80
POSITIVE
OUTPUT
VOLTAGES
RL " ' "
R
1 Mil
RL
300
HL
100k1!
RL
30kH
60
0
k~!
"--. .....
-""-
'"""'"
~
0
Rl
~
'0
'00
lK
!OK
"
R,
GNO-+--'-
,,
Resistance hom Pin 910 ground
0
Vo • 2.SV ':,' • A, I
"-
NEGATIVE
"
' " - _ ' ; " " ' _ OUTPUT
VOLTAGES
GNO
R, R,
~.2 ....n
age to get 25% duty cycle with the error amplifier signaling maximum duty cycle.
'OM
FREQUENCY-HERTZ
.,
Figure 6. Error Amplifier Biasing Circuits. (Note: Change
in Input Connections for OppOSite Polarity
Outputs)
"
tOOK
Ok
In addition to constant current limiting, pins 4 and 5
may also be used in transformer-coupled circuits to
sense primary current and shorten an output pulse,
should transformer saturation occur. (Refer to Figure
15.) Another application is to ground pin 5 and use pin 4
as an additional shutdown terminal, i.e., the output will
be off with pin 4 open and on when it is grounded. Finally, foldback current limiting can be provided with the
network of Figure 8. This circuit can reduce the short-
Figure 5. Error Amplifier Frequency Response as a Function
of External Resistor, Rt. at Pin 9
One final point on the compensation terminal is that
this is also a convenient place to insert any programming signal which is to override the error amplifier. Internal shutdown and current limit circuits are connected here, but any other circuit which can sink 200 pA
can pull this pOint to ground, thus shutting off both outputs.
While feedback is normally applied around the entire
regulator, the error amplifier can be used with conventional operational amplifier feedback and is stable in either the inverting or non-inverting mode. Regardless of
the connections, however, input common-mode limits
must be observed or output signal inversions may
result. For conventional regulator applications, the 5volt reference voltage must be divided down as shown
in Figure 6. The error amplifier may also be used in
fixed duty cycle applications by using the unit gain configuration shown in the open loop test circuit.
Figure 7. Current Limiting Circuitry 01 the XR·1524
CURRENT LIMITING CONTROLS
circuit current (ISC) to approximately one-third the maximum available output current (IMAX>.
The current limiting circuitry of the XR-1524 is shown in
Figure 7.
OUTPUT CIRCUITS
The outputs of the XR-1524 are two identical NPN transistors with both collectors and emitters uncommitted.
Each output transistor has antisaturation circuitry for
fast response, and current limiting set for a maximum
output current of approximately 100 mAo The availability
of both collectors and emitters allows maximum versatility to enable driving either NPN or PNP external transistors.
By matching the base-emitter voltages of 01 and 02,
and assuming negligible voltage drop across R1,
Threshold
= VBE (01)+11
R2-VBE (02)
=200 mV
=
11 R2
Although this circuit provides a relatively small threshold with a negligible temperature coefficient, there are
some limitations to its use, the most important of which
is the ± 1 volt common mode range which requires
sensing in the ground line. Another factor to consider is
that the frequency compensation provided by R1C1
and 01 provides a roll-off pole at approximately 300
Hertz.
'~
~
I••• · - V,N ·
v••
A,
l'c.Y~."
A, tA,
_her.
v, ... 200 mY
Since the gain of this circuit is relatively low, there is a
transition region as the current limit amplifier takes
over pulse width control from the error amplifier. For
testing purposes, threshold is defined as the input volt-
Figure 8. Foldback Current limiting Can Be Used to Reduce
Power Dissipation Under Shorted Output Conditions
1-332
XR·15/25/3524
In considering the application of the XR-1524 to voltage
regulator circuitry, there are a multitude of output configurations possible. In general, however, they fall into
three basic classifications:
1. Capacitor-diode coupled voltage multipliers
2. Inductor-capacitor single-ended circuits
3. Transformer-coupled circuits
Examples of each category are shown in Figures 9, 10
and 11. In each case, the switches indicated can be either the output transistors in the XR-1524 or added external transistors according to the load current requirements.
(a) Push-Pull
(b) Flyback
Figure 11. Push-Pull and Flyback Connections for
Transformer-Coupled Outputs
DEADBAND CONTROL
The XR-1524 pulse width modulating regulator provides
two outputs which alternate in turning on for push-pull
inverter applications. The internal oscillator sends a
momentary blanking pulse to both outputs at the end of
each period to provide a deadband so that there cannot
be a condition when both outputs are on at the same
time. The amount of deadband is determined by the
width of the blanking pulse appearing on pin 3 and can
be controlled by anyone of the four techniques described below:
Figure 9. Capacitor-Diode Coupled VoHage Multiplier Output
Stages. (Note: Diode 01 is Necessary to
Prevent Reverse Emitter-Base Breakdown of
Transistor Switch SA)
'V'N~ ~
'A",
I
~I
I
I
Method 1: For 0.2 to 2.0 microseconds, the deadband
is controlled by the timing capacitor. Cr, on
pin 7. The relationship between CT and
deadband is shown in Figure 4. Of course,
since CT also helps determine the operating
frequency. the range of control is somewhat
limited.
'V o
V tN ' Vo
Method 2: For 0.5 to 5.0 microseconds, the blanking
pulse may be extended by adding a small
capacitor from pin 3 to ground. The value of
the capacitor must be less than 1000 pF or
triggering will become unreliable.
Method 3: For longer and more well-controlled blanking
pulses. a simple one-shot latch similar to the
circuit shown in Figure 12 should be used.
Figure 10. Single-ended Inductor Circuits Where the Two
Outputs of the XR-1524 are Connected in Parallel
1-333
XR·15/25/3524
APPLICATIONS INFORMATION
POLARITY CONVERTING REGULATOR
10k
The XR-1524 pulse width modulating regulator can be
interconnected as shown in Figure 14. The component
values shown in the figure are chosen to generate a -5
volt regulated supply voltage from a + 15 volt input.
This circuit is useful for an output current of up to 20
mA with no additional boost transistors required. Since
the output transistors are current limited, no additional
protection is necessary. Also, the lack of an inductor allows the circuit to be stabilized with only the output capacitor.
10k
Figure 12. Recommended External Circuitry for Long
Duration Blanking Pulse Generation (Method 3 of
Deadband Control. Note: For 5 p'sec blanking,
choose Ca = 200 pF, Ra = 10 KG)
FLYBACK CONVERTER
Figure 15 shows the application of XR-1524 in a lowcurrent DC-DC converter, using the flyback converter
principle (see Figure 11 b). The particular values given
in the figure are chosen to generate ± 15 volts at 20
mA from a + 5 volt regulated line. The reference generator in the XR-1524 is unused. The reference is provided by the input voltage. Current limiting in a flyback
converter is difficult and is accomplished here by sensing current in the primary line and resetting a soft-start
circuit.
When this circuit is triggered by the oscillator output pulse, it will latch for a period determined by CBRB providing a well-defined
deadband.
Another use for this circuit is as a buffer
when several other circuits are to be synchronized to one master oscillator. This oneshot latch will provide an adequate signal to
insure that all the slave circuits are completely reset before allowing the next timing
period to begin.
SINGLE ENDED REGULATOR
The XR-1524 operates as an efficient single-ended
pulse width modulating regulator, using the circuit connection shown in Figure 16. In this configuration, the
two output transistors of the circuit are connected in
parallel by shorting pins (12,13) and (11,14) together,
respectively, to provide for effective 0 - 90% duty-cycle
modulation. The use of an output inductance requires
an R-C phase compensation on pin 9, as shown in the
figure.
Note that with this circuit, the blanking pulse
holds off the oscillator so its width must be
subtracted from the overall period when selecting RT and CT
Method 4: Another way of providing greater deadband
is just to limit the maximum pulse width.
This can be done by using a clamp to limit
the output voltage from the error amplifier. A
simple way of achieving this clamp is with
the circuit shown in Figure 13.
This circuit will limit the error amplifier's voltage range since its current source output
will only supply 200 p.A. Additionally, this circuit will not affect the operating frequency.
+1SV
ISK
SK
VREF 16~----------~
SK
-4 RT
....;;,'K...._ _
IN916
Compo
Gild
®f---I~)l..I-"~.'/
-sv
20mA
~.o'~I_---fCT
5k
osc.
8
GNO
Figure 13. Using a Clamp Diode to Control Deadband
(Method 4 of Deadband Control)
Figure 14. Circuit Connection for Polarity Converting
Regulator (Vin = + 15V, Vout = - 5V)
1-334
GNO
XR·15/25/3524
PUSH-PULL CONVERTER
The circuit of Figure 17 shows the use of XR-1524 in a
transformer-coupled DC-DC converter with push-pull
outputs (see Figure 11 a). Note that the oscillator must
be set at twice the desired output frequency as the XR1524's internal flip-flop divides the frequency by 2 as it
switches the PW.M. signal from one output to the other.
Current limiting is done in the primary. This causes the
pulse/width to be reduced automatically if the transformer saturation occurs.
c,'t-------+--9
caMP
GND
001
'OK
RETURN
------t-:,:-:,;:"!!+....oUNO
' - - - - - - - -....
Figure 16. Conventional Single-Ended Regulator Connection
(Vin = + 28V, Vo = + 5V, lout oS 1 Amp)
l500pf
sv
E--t--t-O"
t...l!!.j ...- -.... c,
F(RO)CCUBf
:1'2131' -A:750
~r1~rt~~~--+·~7
"--'T'--'
Figure 15. A Low-Current DC-DC Converter Using Flyback
Principle (Vout = ± 15V, Yin = + 5V, IL oS 20
rnA)
Figure 17_ A High-Current DC-DC Converter with Push-Pull
Outputs (Vin = + 28V, Vo = + 5V, 10 oS 5A)
1-335
XR·1525A12525A13525A
XR·1527 A12527 A13527 A
Pulse-Width Modulating Regulators
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-1525A11527A is a series of monolithic integrated circuits that contain all of the control circuitry
necessary for a pulse-width modulating regulator. Included in the 16-Pin dual-in-line package is a voltage
reference, an error amplifier, a pulse-width modulator,
an oscillator, under-voltage lockout, soft-start circuitry,
and output drivers.
INV
INPUT
NON-INV.
INPUT
SYNC
The XR-1525A12525A13525A series features NOR logic,
giving a LOW output for an OFF state. The XR-1527A1
2525A13527A series features OR logic, giving a HIGH
output for an OFF state.
OSCILLATOR
OUTPUT
CT
RT
FEATURES
DISCHARGE
8V to 35V Operation
5.1V Reference Trimmed to ± 1 %
100 Hz to 500 kHz Oscillator Range
Separate Oscillator Sync Terminal
Adjustable Deadtime Control
Internal Soft-Start
Input Under-voltage Lockout
Latching PWM to Prevent Double Pulsing
Dual Source/Sink Output Drivers
Capable of Over 200 mA
Power-FET Drive Capability
SOFT-START
ORDERING INFORMATION
APPLICATIONS
Power Control Systems
Switching Regulators
Industrial Controls
Part Number
Package
Operating Temperature
XR-1525A127M
XR-2525A127 AN
XR-2525A127 AP
XR-3525A127CN
XR-3525A127CP
Ceramic
Ceramic
Plastic
Ceramic
Plastic
- 55·C to + 125·C
- 25·C to + 85°C
- 25°C to + 85°C
O°C to + 70°C
O·C to +70·C
SYSTEM DESCRIPTION
The on-chip 5.1-volt reference is trimmed to ± 1 % initial accuracy, and the common-mode input range of the
error amplifier is extended to include the reference
voltage. Deadtime is adjustable with a single external
resistor. A sync input to the oscillator allows multiple
units to be slaved together, or a single unit to be synchronized to an external clock. A positive-going signal
applied to the shutdoown pin provides instantaneous
turnoff of the outputs. The under-voltage lockout circuitry keeps the output drivers off, and the soft-start capacitor discharged, for an input voltage below the required value. The latch on the PWM comparator insures the outputs to be active only once per oscillator
period, thereby eliminating any double pulSing. The
latch is reset with each clock pulse.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (+ VIN)
+40V
+40V
Collector Supply Voltage (Vc)
Logic Inputs
- 0.3V to 5.5V
Analog Inputs
- 0.3V to + VIN
Output Current, Source or Sink
500mA
Reference Output Current
50mA
Oscillator Charging Current
5 mA
Power DisSipation
Ceramic Package
1000 mW
Derate above TA = + 25·C
8.0 mW/·C
625 mW
Plastic Package
5.0 mW/·C
Derate above TA = + 25·C
Operating Junction Temperature (TJ)
+ 150·C
Storage Temperature Range
- 65·C to + 150·C
The output drivers are totem-pole designs capable of
sinking and sourcing over 200 mAo
1-336
XR·1527 A12527 A13527 A
XR·1525A12525A13525A
ELECTRICAL CHARACTERISTICS
Test Conditions: VIN
=
+20V, TJ
= Full operating temperature range,
XR·1525A/2525A
XR·1527A12527A
PARAMETERS
unless otherwise specified.
XR·3525A
XR·3527A
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
5.05
5.10
10
20
20
5.00
5.10
10
20
20
80
5.15
20
50
50
5.20
100
80
5.20
20
50
50
5.25
100
V
mV
mV
mV
V
mA
40
20
200
50
40
20
200
50
p.V rms
mV/kHR
±2
±3
±0.3
±S
±S
±1
100
±2
±3
±1
±S
±S
±2
100
2.0
3.5
0.5
2.0
1.0
2.2
2.0
3.5
0.5
2.0
1.0
2.2
%
%
%
Hz
kHz
mA
V
p'sec
V
mA
2
1
10
10
1
CONDITIONS
VOLTAGE REFERENCE SECTION
Output Voltage
Line Regulation
Load Regulation
Temperature Stability (2)
Total Output Variation (2)
Output Short Circuit
Current
Output Noise Voltage (2)
Long Term Stability (2)
5.00
4.95
TJ = 25°C
VIN = 8V to 35V
IL = 0 to 20 mA
TJ = Full Operating Range
Line, Load and Temperature
TJ = 25°C, Vrel = OV
TJ = 25°C, 10 Hz :s f :s 10 kHz
TJ = 125°C
OSCILLATOR SECTION (Note 3)
Initial Accuracy (2,3)
Temperature Stability (2)
Input Voltage Stability (2,3)
Minimum Frequency
Maximum Frequency
Current Mirror
Clock Amplitude (2,3)
Clock Pulse Width (2,3)
Sync Threshold
Sync Input Current
400
1.7
3.0
0.3
1.2
ERROR AMPLIFIER SECTION (VCM
Input Offset Voltage
Input Bias Current
Input Offset Current
DC Open-Loop Gain
Gain Bandwidth Product (2)
Output Low Voltage
Output High Voltage
Common-Mode Rejection
Ratio
Supply Voltage Rejection
Ratio
1.0
2.8
2.5
TJ = 25°C, RD = 011
Sync Voltage = 3.5V
= 5.1V)
0.5
1
SO
1
1.0
2.8
2.5
400
1.7
3.0
0.3
1.2
TJ = 25°C, f = 40 kHz
TJ = Full Operating Range
VIN = 8V to 35V
RT = 150 kll, CT = 0.1 p.F
AT = 2 kll, CT = 1 nF
IRT = 2 mA
3.8
SO
75
2
0.2
5.5
75
50
SO
5.0
10
1
SO
1
mV
p.A
p.A
dB
MHz
V
V
dB
3.8
SO
75
2
0.2
5.5
75
50
SO
45
0.5
49
0.9
3.3
0.05
3.5
1.0
%
%
V
V
p.A
50
0.4
0.4
80
0.5
1.0
p.A
V
mA
0.2
1.0
19
18
7
0.4
2.0
100
50
0.2
8
200
SOD
300
0.5
V
V
V
V
V
p.A
nsec
nsec
p'sec
14
20
mA
0.5
0.5
dB
RL'" 10 Mil
TJ = 25°C
VCM = 1.5V to 5.2V
VIN = 8V to 35V
PULSE·WIDTH MODULATING COMPARATOR
Minimum Duty Cycle
Maximum Duty Cycle
Input Threshold (3)
Input Threshold (3)
Input Bias Current (2)
0
45
0.5
49
0.9
3.3
0.05
3.5
1.0
50
0.4
0.4
80
0.6
1.0
0
Zero Duty Cycle
Maximum Duty Cycle
SOFT-START SECTION
Solt-Start Current
Solt-Start Voltage
Shutdown Input Current
25
OUTPUT DRIVERS (Each Output) Vc
Output Low Voltage
Output Low Voltage
Output High Voltage
Output High Voltage
Under-voltage Lockout
Collector Leakage (4)
Rise Time (2)
Fall Time (2)
Shutdown Delay (2)
18
17
6
25
Vshutdown = OV
Vshutdown = 2V
Vshutdown = 2.5V
= 20V
0.2
1.0
19
18
7
0.4
2.0
100
50
0.2
8
200
SOD
300
0.5
14
20
18
17
6
Isink';' 20 mA
Isink = 100 mA
Isource = 20 mA
Isource = 100 mA
Vcomp and VSS = High
Vc = 35V
TJ = 25°C, CL = 1 nF
TJ = 25°C, CL = 1 nF
VSD = 3~CS = 0, TJ = 25°C
TOTAL STANDBY CURRENT
Supply Current
VIN = 35V
Note 2: These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production.
Note 3: Tested at I = 40 kHz (RT = 3.6 kll, CT = 0.01 p.F, RD = 011).
Note 4: Applies to XR-1525N2525N3525A only, due to polarity 01 output pulses.
1-337
XR·1525A12525A13525A
XR·1527 A12527 A13527 A
PRINCIPLES OF OPERATION
Error Amplifier
The different control blocks within the XR-1525A11527A
function as follows:
The error amplifier of the XR-1525A11527A is a differential input transconductance amplifier. Its commonmode range covers the reference voltage. Its open-loop
gain, typically 75 dB, can be reduced by a load resistor
on Pin 9. To ensure proper operation, the output load
should be limited to 50 kO or greater. An equivalent circuit schematic of the error amplifier is shown in Figure 9.
Voltage Reference Section
The internal voltage reference circuit of the XR-1525A1
1527A is based on the well-known "band-gap" reference, with a nominal output voltage of 5.1 volts, internally trimmed to ± 1 % accuracy. It is short circuit protected and is capable of providing up to 20 mA of
reference current. A simplified circuit schematic is
shown in Figure 7.
Soft-Start Circuitry
The soft-start function is provided to achieve controlled
turn-on of the pulse-width modulator. When power is
applied to the device, the external capacitor, Csoftstart, on Pin 8 is charged by a 50 ,.A constant current
source. The ramp voltage appearing on this capacitor
is fed into the pUlse-width modulator,. which gradually
increases its output duty cycle from zero to the prescribed value. When the shutdown terminal is raised to
a positive value, an internal transistor turns ON, and
discharges the capacitor, CS, causing the PWM to turn
OFF. When the shutdown terminal is open or pulled low,
the transistor turns OFF, and Cs begins charging as before. The turn-on time (time required to charge Cs to
+2.7 volts) can be approximated as:
Oscillator Section
The sawtooth oscillator derives its frequency from an
external timing resistor/capacitor pair. The timing resistor, AT, determines the charging current into the timing
capacitor, CT. The magnitude of this current is approximately given by:
Vref - 2VBE
AT
3.7V
"'--
AT
where AT may range from 2 kO to 150 kO. In general,
temperature stability is maximized with lower values of
Rr The current source charging CT creates a linear
ramp voltage which is compared to fixed thresholds
within. When the capacitor voltage reaches + 3.3 volts,
the oscillator output (Pin 4) goes high, turning ON the
discharge transistor. The capacitor is discharged
through the deadtime resistor, RD. When the voltage on
CT falls to + 1.0 volt, the oscillator output goes low, the
discharge transistor is turned OFF, and the capacitor is
charged through the constant current source as another cycle starts. With large values of RD (5000, maximum), deadtime is increased. The actual operating frequency is thus a function of the charge and discharge
times. Figure 2 shows how charge time is related to AT
and CT, with RD = 00. Deadtime is a function of RD
and Cr, and can vary between 0.5 to 7 ",sec, with RD =
00, as shown in Figure 3. The equivalent circuit schematic of the oscillator section is shown in Figure 8.
RECOMMENDED OPERATING CONDITIONS
A unit can be synchronized to an external source by selecting its free-running oscillator period to be 10%
longer than the period of the external source. A
positive-going pulse of at least 300 nsec wide should be
applied to the sync terminal for reliable triggering; however, it should not exceed the free-running pulse width
by more than 200 nsec. The amplifier of the pulse
should be kept between 2 aAd 5 volts. Multiple units
can be synchronized to each other by connecting all CT
pins, and oscillator output pins together; AT pins and
discharge pins on slave oscillators must be left open.
Note 1: Range over which the device is fUnctional
and parameter limits are guaranteed.
Collector Supply Voltage (VC)
+ 4.5V to + 35V
Sink/Source Load Current
(Steady State)
o to 100 mA
o to 400 mA
Sink/Source Load Current (Peak)
Reference Load Current
Ot020mA
Oscillator Frequency Range
100 Hz to 400 kHz
Oscillator Timing Resistor
2 kO to 150 kO
Oscillator Timing Capacitor
0.001 ",F to 0.1 ",F
Deadtime Resistor Range
o to 5000
TC (msec) = 54 Cs
where Cs is in ",F.
Output Section
The output drivers of the XR-1525A11527A are totempole designs capable of sinking and sourcing 200 mAo
The low source impedance in the high or low states provides ideal interfacing with bipolar as well as FET
power transistors. Either push-pull or single-ended output configurations are possible with separate collector
supply terminals. The equivalent schematic of the output drivers is shown in Figure 10.
1-338
XR·1525A12525A13525A
XR·1527 Al2527 Al3527 A
r
VREF
XR·1525A OUTPUT STAGE
16
+ytN
GROUND
DISCHARGE
I
______ J
I
.::rl~""t>-.--J:.
SO/loA
SOFT START
I
I
[!]f------.------+-....J
r----~--------------....J
SHUTDOWN
~.lJ-
5K
101---¥>I\r----+--~
52 K
I
-::XR·1527A OUTPUT STAGE
L
EQUIVALENT SCHEMATIC DIAGRAM
Crf5,
P.W.M.
INPUTI91.,....,........_
P.W.M.
DUTPUT
ose
11
OUTPUT A (11)
OUTPUT B (141
J
u
u
5
OUTPUT A (111
OUTPUT8(14,
to
20
50'00 200 SOO'ma2m.Sm.'Oms
CHARGE TIME (JiaKl
1
n
n
r
1--._.......I 1--_.......1 1--_.......1
Figure 1: 'IIIplcal Waveforms-XR-1525A/1527A
Figure 2. Oscillator Charge Tlma vs RT and CT
1·339
..J
XR·1525A12525A13525A
XR·1527 A12527 A13527 A
500
80~
c
_ _.,....._......
400
60
II:
I
.
II:
0
!!!
'""
",.
~I·CP
300
II:
"cc
~
200
RZ
"
100
10
100
~~.'--~0~.5~~~~~-£~10~~2~0--~5~0--'00~~200
lK
10K
tOOK
1M
10M
FREQUENCY (HI:)
DISCHARGE TIME (Ilsec)
Figure 4. Error Amplifier Open-Loop Frequency Response.
Figure 3. Oscillator Discharge Time vs RO and CT
50
10
O~~~~~~~~--~~~~~~
.01
.02
.03 .04.05
.07
.10
.2.3.4,5.7
3
1A
ERROR VOLTAGE (VOLTS)
OUTPUT CURRENT. SOURCE OR SINK (AMPS)
Figure 6. Output Duty Cycle vs Error VoHage
Figure 5. Output Saturation Characteristics
VW~------------------'--4r----~--------4r--~
"
's
"
O.
",
TO
..
""
o.
.
FRO"
"
SHUTDOWN
&
~
~
10KU
~ 3
80
S
§
.
z
~
5M
INPUT
INPUT
~.
AT=30KU
AT
1M
uLL11
LL11
~
VIN -10V
RL-2KO
TJ.2S'C
AT·100Kn
I
c
lOOK
FREQUENCY (HERtZ)
Figure 2. Current Limiting Amplifier-Frequency Response
~ 00
80
3!.
10K
lK
Figure 1. Current Limiting Threshold (VTH) vs. Threshold
Selling Resistor (RT)
Ii
20
..~
0
50
0
0
40
100
lK
lOOK
10K
FREQUENCV (HERtZ)
2.41
1M
iii
1.0
.
.
DELAY·
~
0.1
!.
...c
U
..:5
"
200
~
150 -
.I:l
100
~
II
I.
i:z:
..e.
ID
~
0
0.01
~
..~
0.001
:i
0.0001
0.001
0.01
0.1
1.0
DEli.V TIME (MILLISECONDS)
2.50
2.S2
2.50
SENSE INPUT VOLTAQE (VOLTS)
2.54
Figure 4. Over-Voltage and Under-Voltage Comparator
Hysteresis
Figure 3. Current Limiting Amplifier Gain vs. Threshold
Setting Resistor (RT
"ca:
2.41
RECOMMENDED SERIES GATE RESISTANCE. RG
FOR USE WITH HIGHER SUPPLY VOLTAGES
I
I
RG;o VIU.;S
/
50
l/
V
:/
/
/'
V
10
VIN
10
n
15
20
25
30
40
SUPP~ Y VOL TAGE (VO~TSI
Figure 6. SCR Trigger-Series Gate Resistance (RG) vs.
Input Voltage
Figure 5. Comparator Activation Delay vs. Capacitor Value
1·345
XR·15/25/3543
PRINCIPLES OF OPERATION
input common mode range extending from ground to
approximately 3 volts below the positive supply. With a
2 kO pull-up resistor, the open-lOOp voltage gain is 72
dB minimum with a unity gain bandwidth beyond 5
MHz. The operational amplifier may be used as a comparator or, if linear amplification is required, external
compensation may be added for stable performance
over a wide frequency range.
The internal control blocks of the XR-1543 operate as
follows:
VoRage Reference Section
The internal voltage reference circuit of the XR-1543 is
based on the well-known "band-gap reference" with a
nominal output voltage of 2.50 volts, internally trimmed
to give an accuracy of ± 1 % at 25°C. It is capable of
providing a stable output voltage over a wide input voltage range. Furthermore, its performance is guaranteed
for changes in line and load conditions. The accuracy
of the output voltage is guaranteed to ± 2% maximum
for the XR-1543/2543, and ± 4% maximum for the XR3543, over the entire operating temperature range.
The input offset voltage of this amplifier is specified for
10 mV maximum; however, it may be programmed externally for thresholds up to 200 mV. By connecting a
resistor, Ry, from Pin 12 to ground, the input threshold
voltage can be varied. For most current sensing applications, the required threshold polarity calls for a positive voltage on the inverting input. Reducing the impedance on Pin 12 also lowers the overall voltage gain of
the amplifier, which makes this pin a convenient point
to apply frequency compensation. This can be accomplished by either connecting C1 to the output, or C2 to
ground as shown in Figure 8. The diode, 01, and the reSistor, RC, are used only if it is necessary to increase
the frequency response by operating the output at a
higher current and/or isolating the load from RC and
C1, when the amplifier is off.
The output of the reference circuit is capable of providing up to 10 mA of current for use as a reference for external circuitry. The primary function of this circuit is to
provide a very accurate and stable reference input for
the under-voltage and over-voltage comparators, thereby enabling very precise monitoring of line and output
voltages without potentiometers.
Comparator Section
SCR Trigger Section
The under-voltage and over-voltage sensing comparators of the XR-1543 are identical except for the input polarities. Each section is made up of two comparators in
series whose inputs are referenced to 2.50 volts. The
delay terminal between the comparators requires an
external capacitor to ground for programmable time delays on the output.
The SCR trigger sectionof the XR-1543 is connected to
the output of the over-voltage comparator and is capable of handling 300 mA. The circuit also provides for remote activation of the output as well as a reset terminal. When an over-voltage situation occurs, the output
of the sensing comparator goes low, turning "on" the
over-voltage indicate transistor. At the same time, the
comparator drives an npn Darlington pair which provides 300 mA to activate an external SCR crowbar.
When an out-of-tolerance situation occurs, the first
comparator activates a current source which then
charges the external capaCitor at a constant rate. This
ramp voltage is then compared to the reference voltage
by the second comparator which activates the output
indicating circuit. With no external capacitor, the overall
time delay from sense input to output is approximately
0.5 /Lsec. The charging current for the capacitor, CD, is
approximately 250 ~ which results in the following relationship:
A remote activation circuit is included to allow the user
to activate the SCR crowbar in other than an overvoltage situation. When this terminal, Pin 2, is grounded, it forces the output of the comparator low which activates the output circuitry in the same manner as the
over-voltage comparator does.
Another function of this circuit is to provide the capability to latch the O.v. indicate and SCR trigger outputs
"on", after a fault is sensed. This is done by connecting
the remote activate terminal (Pin 2) to the O.V. indicating terminal (Pin 4). When an O.V. condition occurs, Pin
2 is pulled low, which in turn holds the outputs in the
"on" condition until the reset terminal is externally
grounded, removing the latch and turning "off" the outputs. If the external connection is not made, the high
current output will be activated only as long as a fault
condition exists. When the fault condition disappears,
the outputs will be disabled. The thresholds for both remote activation and reset terminals are approximately
1.2 volts.
Time delay = 10 CD (msec)
where CD is in I'F.
The output npn transistors are capable of sinking 10
mA with saturation voltage of less than 0.4 volts. The
outputs can be "wired OR'd" to provide a single output
indicator.
Current SenSing Amplifier
The operational amplifier used in the XR-1543 is a highgain, externally compensated amplifier with open collector outputs. The pnp input stage provides for a wide
1-346
XR·15/25/3543
EQUIVALENT SCHEMATIC DIAGRAM
2.35 K
SCR
TRIGGER
U.V.
INDICATE
SCR
TRIGGER
O.V.
INDICATE
INV.
NJ.
REMOTE
ACTIVATE
OFFSET/COMP
GROUND
2
RESET
(GROUND TO ACTIVATE)
~~-----------
1
':"
Figure 7. XR-1543 Block Diagram
1-347
XR·15/25/3543
APPLICATIONS INFORMATION
2. C1 is determined by the loop dynamics.
A typical application of the XR-1S43 is to monitor a single power supply output voltage as shown in Figure 9.
In this circuit, both over· and under-voltage sensing and
current-limiting functions are performed. The circuit
shown is powered from an external bias capable of supplying 10 mA in addition to the activation current for the
SCR trigger. With Pin 2 tied to Pin 4, a latch has been
provided such that when an over-voltage situation occurs, the o.v. indicator and SCR trigger are activated
and held until the reset terminal is externally grounded.
3. Peak current to load,
In powering an SCR from supply voltages greater than S
volts, an external resistor, RG, is required on Pin 1to
limit the power dissipation for the XR-1S43. Although
the XR-1S43 is capable of handling 300 mA of current,
its power dissipation must be kept below the absolute
maximum ratings.
S. Low output voltage limit,
I
VTH
Vo (
R2
)
P '" RSC + RSC R2 + R3
4. Short circuit current,
ISC = VTH
RSC
Vo (low) = 2.S(R4 + RS + R6)
RS + R6
6. High output voltage limit,
In this circuit, current-limiting is performed by sensing
the voltage drop across the resistor, RSC, in the positive supply line. The threshold for the amplifier is externally set by the resistor, AT
Vo (high) = 2.S(R4
7. Voltage sensing delay, TO
The values of the external components used in Figure 9
are calculated as follows:
+
RS
R6
RG
> VIN -S
0.2
v+
-IN
t---I(I--
TO ~:'~ROL
Figure 8. Current Umiting Amplifier Connections lor
Threshold Control and Frequency Compensation
1-348
R6)
= 10,000 Co
8. SCR trigger power limiting resistor,
1. Current limiting threshold, VTH '" 1000
RT
+
XR·15/25/3543
V,N o-~r---""-------------------------'-",
·sc
FROM
POWER
SUPPLY
4---r---~--~r-VVY-~-~----------------~--~----~
TO
SYST~M
CONTROL
••
••
TO VOLTAGE
CONTROL LOOP
••
·3
-I_CI~
..
___~~____~.____~____~
Figure 9. Typical Connection for Linear Foldback Current Limiting as well as Over-Voltage and Under-VoHage Protection.
r-----------------,
XR-l503
I
I
I
I
I
I
I
I
I
I
I
I
r-i~--~--~--+'4
I
I
I
~ II >----+---+
I
I
I
I
I
L______
I
_~
PIN 7
INPUT
PIN 8
DELAY _ _ _,
O~~~~------------------------,U~-----------OFF
ON
Figure 10. XR-1543-lnput Line MonHor Circuit
1-349
XR·1512513543
MAIN SUPPLY
BUS
VOLT~~~
00--------·-----4
r---~------
- - - - - XA.is.3- - - - - - -:
I
I
I
I
I
I
I
I
I
I
SCR
"CROWBAR"
I
I
I
L
RESET
RSC
SUPPLY BUS
RETURN
Figure 11. XR·1543-Dver Current Shutdown Circuitry
+VIN
+
VOUT
GND
Figure 12. XR·1543 - DC Converter with Isolated Current Umitlng
1-350
XR·2230
Pulse-Width Modulator Control System
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-2230 is a high-performance monolithic pulse
width modulator control system. It contains all the necessary control blocks for designing switch mode power
supplies, and other power control systems. Included in
the 18-Pin dual-in-line package are two error amplifiers,
a sawtooth generator, and the necessary control logic
to drive two open-collector power transistors. Also included are protective features, such as adjustable
dead-time control, thermal shutdown, soft-start control,
and double-pulse protection circuitry.
COMPl
COMP2
SET
OSCILLATOR
OUTPUT
vcc
The device provides two open-collector output transistors which are driven 180° out-of-phase, and are capable of sinking 30 mAo These outputs can be used to implement single-ended or push-pull switching regulation
of either polarity in transformerless or transformercoupled converters.
EXTERNAL
SHUTDOWN
DTADJ
PWM OUT
PWM IN
GND
oun
FEATURES
Thermal Shutdown
Adjustable Dead-time
Dual Open-Collector
30 mA Output Transistors
Double-Pulse Protection Circuit
Soft-Start Control
High-Speed Remote Shut-Down Input
Two High-Performance Error Amplifiers
with ± 5V Input Common-Mode Range
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-2230CP
Plastic
O°C to + 70°C
SYSTEM DESCRIPTION
The XR-2230 PWM circuit contains two highperformance error amplifiers with wide input commonmode range, and large voltage gains. Typically, one amplifier (Pins 16, 17, 18) is used for current sensing and
the other (Pins 1, 2, 3) is used as an error amplifier to
sense the output voltage. The XR-2230 requires a split
supply between ± 8 volts and ± 15 volts, however, it
can be operated from a single supply with proper external biasing on the ground pin and input pins of the error
amplifiers. The output drivers capable of sinking 30 mA
at a saturation voltage of about 0.3V can be used in a
push-pull configuration, or can be paralleled for a
single-ended configuration with a duty cycle between
0% to over 90%.
APPLICATIONS
Switching Regulators
Motor-Speed Controllers
Pulse-Width Modulated Control Systems
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage
Negative Supply Voltage
Input Voltage
Output Voltage
Power Dissipation (TA S 25°C)
Operating Temperature
Storage Temperature
OUT2
-0.5 to + 18V
+0.5 to -18V
-18to +18V
-0.5 to + 18V
400 mW
-10°Cto +85°C
- 55°C to + 125°C
The XR-2230 features a self-protecting thermalshutdown circuitry which turns off the output drivers
when the junction temperature exceeds 130°C. The onboard regulator stabilizes the oscillator frequency to
0.1 %IV for reliable performance.
1-351
XR·2230
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°C, VCC = + 12V, VEE = -12V, fOSC = 20 kHz, unless otherwise specified.
SYMBOL
PARAMETERS
MIN
TYP
MAX
UNIT
11.0
-6.0
-10
15.0
-2.0
V
V
rnA
rnA
100
15
kHz
%
CONOITIONS
SUPPLY SECTION
VCC
VEE
ICC
lEE
Positive Supply Voltage
Negative Supply Voltage
Positive Supply Current
Negative Supply Current
+10
7.0
-2.0
OSCILLATOR SECTION
fOSC
VOSC
6
Frequency Range
Initial Accuracy
Supply Voltage Stability
Low Supply Voltage
Temperature Stability
Sawtooth Peak Voltage
Duty Cycle Range
10
%N
0.1
-20
3.0
10
+20
0.01
3.5
%
RT = 30 kO,
CT = 4700 pF
Vee = +10V ... +15V
Vee = + 18V, VEE = -8V
%/OC
4.0
90
V
%
10
-30
mV
fOSC = 20 kHz
VOLTAGE ERROR AMPLIFIER
YOM
Input Offset Voltage
Input Bias Current
Open-Loop Gain
Closed-Loop Bandwidth
Common·Mode Rejection
Ratio
Output Voltage Swing
SR
Slew Rate
VOS
IBIAS
AVO
f-3dB
CMMR
60
2
-.5
90
25
p.A
60
dB
kHz
dB
±5
V
2
Input Voltage Range
4
VII'S
±5
V
AVCL = 40 dB
VICM = ±4.5V
RL = 10 kO
Vee = +8V, VEE = -8V
AVCL = 14 dB,
RF = 10 kO
CURRENT ERROR AMPLIFIER
YOM
Input Offset Voltage
Input Bias Current
Open-Loop Gain
Closed-Loop Bandwidth
Common-Mode Rejection
Ratio
Output Voltage Swing
SR
Slew Rate
VOS
IBIAS
AVO
L3dB
CMRR
60
60
±5
±4
4
Input Voltage Range
4
-1.0
90
25
90
20
-60
mV
p.A
dB
kHz
dB
V
V
8
VII'S
±5
V
AVCL = 40 dB
VICM = ±4.5V
RL = 10 kO
Vee = +8V, VEE = -8V
AACL = 14 dB,
RF = 10 kO
MODULATOR SECTION
td
tf
Set Input Open Voltage
(Pin 15)
Modin Input Open Voltage
(Pin 11)
Inhibit Input Current (Pin 13)
Inhibit Propagation Delay
Out1, Out2, Output Voltage
(Pins 9 and 10)
Low Supply Voltage
Out1, Out2 Fall Time
Modout Output Voltage
(Pin 12)
Under Low Supply Voltage
Oscillator Output Voltage
(Pin 14)
Thermal Shutdown Temp.
3.1
2.8
3.1
2.8
-50
3.6
3.3
3.6
3.3
-10
60
4.1
4.3
4.1
4.3
30
0.3
0.4
0.3
0.4
0.6
1·352
Vee = +8V, VEE = -8V
VCC = +8V, VEE = -8V
p.A
0.3
0.4
0.3
130
V
V
V
V
ns
V
V
V
ns
V
V
V
V
V
°c
10 = 30 rnA, TA = 25°C
TA = -10 ... +85°C
10 = 27 rnA, TA = 25°C
10 =
TA =
10 =
10 =
TA =
16 rnA, TA = 25°C
-10 ... +85°C
24 rnA, TA = 25°C
3 rnA, TA = 25°C
- 10 ... + 85°C
XR·2230
"ADJ
DT.ADJ
IS.
Figure 1. Equivalent Schematic Diagram
PWM output so that the output transistor's off time is
a function of the error amplifier's input voltage.
PRINCIPLES OF OPERATION
The heart of the XR-2230 is the sawtooth generator. As
seen in Figure 1, this sawtooth drives one input of each
of the three system comparators. Comparators one and
two have their other inputs tied to the outputs of the error amplifiers. These comparators will now produce, at
their outputs, square waves which will have a duty cycle proportional to the voltage at the inputs to the error
amplifiers, or pulse width information. The pulse width
information is fed into the NOR gate and used to provide the reset information to the pulse-width modulation
flip-flop (PWM). The PWM flip-flop information is fed in
to the NAND gate with the external shutdown and PWM
flip-flop set input. The information from the NAND gate
drives an open-collector transistor to provide the pulsewidth modulation output, Pin 12. The PWM output will
be a square wave with a frequency set by the sawtooth
generator, and a duty cycle equal to either comparator,
one or two, whichever is shorter. If the external shutdown, Pin 13 is driven low, the PWM output will remain
low or go to zero duty cycle. The set input of the PWM
flip-flop, Pin 15, is normally connected to the buffered
sawtooth generator output, Pin 14, so that a reset pulse
is provided every cycle. Each output transistor is driven
by a three input NAND gate. These inputs consist of:
2. Pulse-steering information from flip-flop two, which
will determine which output transistor receives the
PWM input signal. Flip-flop two will toggle once every cycle of the sawtooth generator's output, which
will make the output transistor's toggle frequency
one-half that of the sawtooth generator's.
3. Information from dead-time and thermal shutdown
circuitry. The dead-time is an externally adjustable
time between one output transistor turning off and
the other turning on. This is used to protect external
circuitry. This dead-time is controlled by an external
voltage applied to Pin 6, which is internally compared with the sawtooth waveform. The thermal
shutdown circuitry will drive the input to the NAND
gate low, if the junction temperature exceeds 130·C.
This will make both outputs low.
The circuit control blocks and functions operate as follows:
Error Ampliliers- These are high-gain op amps which are
used to sense output conditions, voltage and current,
and provide a dc voltage to comparators one and two.
This will in turn adjust the PWM output duty cycle and
ultimately that of the output transistors to correct for errors in the output voltage or overcurrent conditions. The
amplifier's outputs are provided for tailoring the closed-
1. Pulse width Information from the PWM input, Pin 11,
which is used to control the off time of the output
transistors. The PWM input is normally tied to the
1-353
XR·2230
loop gain or frequency response of the system. Figure
2 shows the relationship between output duty cycle,
Pins 11 and 12 connected, and the voltage at Pins 1 or
18. Amplifier two is approximately twice as fast as Amplifier one, and should, therefore, be used to sense output current.
External Shutdown, Pin 13-A low level signal applied to
this pin will turn both outputs on. If not used, this input
should be left open-circuited. The impedanoe at this
node is approximately 1 MO.
Oscillator Output, Pin 14-This is an open-collector output
which will be a square wave with a frequency set by the
sawtooth generator. The duty cycle of this output will
vary from 10 to 90 %, and is a function of the dead-time
setting. This pin is normally connected to Pin 15, set to
provide reset pulses lor the PWM flip-flop.
Set, Pin 15-This is the set input for the PWM flip-flop. A
low-going signal at this pin will cause the flip-flop to be
reset. The impedance at this pin is approximately 7.5
kO. This pin is normally connected to the oscillator output, Pin 14.
FAOJ, Pin 7-A resistor, Rext to + VCC, and a capacitor,
Cext, to ground from this pin, set the frequency of the
sawtooth and oscillator output, by the relationship:
FOSC =
The sawtooth waveform a Signal varying from zero volts
to + 5V, will be present at Pin 7. Normal values of Rext
will range from 1 kO to 100 kO. Figure 3 shows the oscillator period as a function of various Rext and Cext values.
The dead-time (minimum time from one output turning
on to the other turning off) is controlled by the voltage
applied to Pin 6.
Oead-time Control, Pin 6-Figure 4 shows output deadtime
as a function of VplN 6. The maximum duty cycle of
each output is also controlled by the dead-time, and
may be determined by the following expression:
Duty Cycle Max (%) = (1 -
PWM Out, Pin 12-This is an open-collector output which
provides a square wave with a duty cycle determined
by the error amplifiers. This output is normally connected to PWM IN, Pin 11.
PWM In, Pin 11-This is the input which controls the duty
cycle of the output transistors. A low level on this pin
will drive both output transistors on. The impedance into this pin is approximately 7.4 kO.
Output Transistors, Pins 9 and 10-These pins provide the
open-collector output transistors which are capable of
sinking 30 mA, typically. They are alternately turned off,
180 0 out-ol-phase, at a rate equal to one-half the frequency of the oscillator.
The impedance into this pin is approximately 10 kO.
APPLICATIONS INFORMATION
The soft-start function may be implemented as shown
in Figure 7. This configuration will reduce the output duty cycle to zero, and gradually increase to its normal
operating pOint, whenever power is applied to the circuit, or after an external shutdown command has been
given. This is used to keep the magnetics in the circuit
from saturating.
+'V
v'o
"'<
rr.~
/
V
10K
<
l/
L /
V
<
'00
'00
soo
5"
i
10"
L
V
20"
:W"
Z2
V
/ V
-;;"f----t---
,<
"V;I//
7
,,<
d 60
V
,
<1>'
50<
V1,181MV}
/
/
L L
V
,L
Vf. ,0
L
~-=--=
100",
2001'
~'"
Figure 3. Oscillation Period vs REXT and CEXT
1-354
t-
/
S.wtDOlh W,v.fQml Pelir.od(")
Figure 2. Modulation Duty Cycle vs Error Voltage
x 50%
VplN 6 <3.5V
100<
~
~)
VplN 6
.of----+
'j
2.68
Rext x Cext
500,.
XR·2230
The time for the duty cycle to start will be approximately
equal to R1 x C1.
0.'
A typical step-down switching regulator configuration is
shown in Figure 8. Only one output transistor is used,
so that the maximum duty cycle will be limited to 45 %.
If a larger duty cycle range is needed, the two outputs
may be externally NOR'd as shown in Figure 9. This
configuration will allow up to 90% duty cycles.
...
ICC
/
C 7.0
V
--
!.
..."'
Figure 10 shows a detailed timing diagram of circuit operation.
-~ 1.0
11. . 1
50
••
1\
5.'
..•
\
30
/
IOV
IV
t2V
vee
\\
.. --
/
10
16V
I4V
I-fEW'"
Figure 5. Supply Current vs Supply VoHage
......
..
\
'00
!.
=
~
\
~
••
TA·25C
300
VPWMOUT
:
•
!
,;
!
....y' KUT1.2
...
,
~
Figure 4. Dead Time vs Dead Time Adjustment VoHage
./
......
/'~
100
/
'---
,V
vY
..
10
..
30
'OIJT!mA.
Figure 6. Output Saturation VoHage
VB
Load Current
RECOMMENDED OPERATING CONDITIONS
CONDITION
UNIT
Vee
SYMBOL
Positive Supply Voltage
+10 .. +15
V
VEE
Negative Supply Voltage
-10=-15
V
RR
Minimum Feedback Resistance
10
kO
AV
Minimum Voltage Gain
14
5
dB
VIV
PARAMETER
1-355
50
XR·2230
EXTERNAL
SHUTDOWN
OR POWER DOWN
Yee
0,
'3
R,
6
XR·2230
D.T.ADJ
D.T.ADJ.
Figure 7. Soft Start Connection
XR·2230
,OK
Yo _...JW'\r~"""
-'5Yo------.----------+_--------------~
+',
-16Yo------+--~~--._+_~--~~--~--~
,OK
GN~
0, '> MR 850
01 '" MJE 171
L, ,.. 40 TURNS #20 WIRE ON
FERROXCUIIE #K300502
TOROID CORE
+15V @ 200 mA
Figure 8. + 10V Step-Down Regulator
1·356
XR·2230
Figure 9. Outputs Nor'd for up to 90% Duty Cycle's
NO.... AL OPERA TIOH
STEADY IT ATl WITH
VOl. TACt !ERROR FtEOIACK
'ROTlCT1ON OF
OOUIU·PU\.SlNQ
DfTECTION
Figure 10. Timing Waveform Diagram
1·357
IIUIMUIIWT'Y
CYCLE UMIT
OPERATION
XR·4194
Dual-Tracking Voltage Regulator
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-4194 is a dual-polarity tracking regulator designed to provide balanced or unbalanced positive and
negative output voltages at currents of up to 200 mAo A
single resistor can be used to adjust both outputs between the limits of ±50mV and ±42 V. The device Is
ideal for local on-card regulation, which eliminates the
distribution problems associated with single-point regulation. The XR-4194 is available in a 14-pin ceramic
dual-in-line package, which has a 900 mW rating.
+YIN
NC
GND
RSET
RO
FEATURES
NC
Direct Replacement for RM/RC 4194
Both Outputs Adjust with Single Resistor
Load Current to ±200 mA with 0.2% Load Regulation
Low External Parts Count
Internal Thermal Shutdown at TJ = 175·C
External Adjustment for ± Vo Unbalancing
Yo-
APPLICATIONS
On-Card Regulation
Adjustable Regulator
ORDERINB INFORMATION
Part Number
Package
Operating Temperalure
XR-4194CN
XR-4194M
Ceramic DIP
Ceramic DIP
O·C to +70·C
-55·Cto +125·C
ABSOLUTE MAXIMUM RATINGS
Input Voltage ± V to Ground
±45 V
XR-4194M
±35 V
XR-4194CN
±45 V
Input/Output Voltage Differential
900mW
Power Dissipation at TA = 25·C
150mA
Load Current
Operating Junction Temperature Range
XR-4194M
- 55·C to + 150·C
XR-4194CN
O·C to + 125·C
Storage Temperature Range
- 65·C to + 150·C
SYSTEM DESCRIPTION
The XR·4194 is a dual polarity tracking voltage regulator. An on board reference, set by a single reSistor, determines both output voltages. Tracking accuracy is
. better than 1 %. Non-symmetrical output voltages are
obtained by connecting a resistor to the balance adjust
(Pin 4). Internal protection circuits include thermal
shutdown and active current limiting.
1-358
XR·4194
ELECTRICAL CHARACTERISTICS
Tast Conditions: + 5
:$
-
- 55°C
:$
TJ
:$
VOUT
VMAA; XR-4194M - 55°C
:$
+ 125°C
PARAMETERS
:$
XR-4194M
MIN
+ 125°C; XR-4194CN O°C
TJ
:$
:$
+ 70°C
XR-4194CN
TYP
MAX
TYP
MAX
UNIT
Line Regulation
0.02
0.1
0.02
0.1
%VOUT
A.VIN ~ 0.1 VIN
Load Regulation
0.001
0.0025
0.001
0.004
o/,VO/mA
XR-4194CN, M:
IL ~ 5 to 100 mA
CONDITIONS
0.002
0.020
0.003
0.015
'101°C
from
+0.3
+1.0
+0.3
+1.5
mA
to
-1.2
-2.0
-1.2
-2.0
±45
±9.5
±35
V
2.5
2.55
2.38
2.5
2.62
KOIV
RSET ~ 71.5 K
TJ ~ 25°C
+42
0.05
±32
V
RSET ~ 71.5 K
2.0
%
TC of Output Voltage
·Stand-by Current Drain
MIN
Input Voltage Range
±9.5
Output Voltage Scale Factor
2.45
Output Voltage Range
0.05
LO
Output Voltage Tracking
Ripple Rejection
70
Input-Output Voltage Differential
70
f
dB
3.0
3.0
VIN ~ VMAX, Vo ~ OV
VIN ~ VMAX, Vo ~ OV
~
120 Hz, TJ
~
25°C
IL ~ 50mA
V
VIN ~ ±30 V Max
Output Short Circuit Current
300
300
mA
Output Noise Voltage
250
250
p.V RMS
Internal Thermal Shutdown
175
175
°C
CL ~ 4.7 p.F, Vo ~ ± 15 V
f ~ 10 Hz to 100 KHz
• ± IQuiescent will increase by 50 p.AIVOUT on positive side and 100 p.ANOUT on negative side.
THERMAL CHARACTERISTICS
XR-4194M
PARAMETERS
MIN
TYP
Power Dissipation
XR-4194CN
MAX
MIN
TYP
900 mW
2.2W
Thermal Resistance
Junction to Ambient
Junction to Case
128°C/W
55°C/W
MAX
CONDITIONS
900mW
2.2W
TA ~ 25°C
TC = 25°C
128°CIW
55°CIW
+VOUT
1
-Your
+YOUT
....
+Vo
-.
4.7... f TANTALUM
~
-Yo
-0 !-AN..-.,
X~1IM
Ro
GNO
c+
cO.oo,... F
p.,
71.5K'
VII+
v.. -
1 ·°'. .'
":"
Ao (KfI)
+VIN
.. 2.5 Your
'For8n1 Ttldttnv Tempe,.lu,.co.tIK: .. nI
01 AoShouIclBe Samelw For Rs
Adj ..... Ro lor ~VS ~ 6 V tl!i KUIIhIIII
Mj ..... ABfor .. VS-IZVj20KU)
Figure 2. Typical Applications
1-359
71.5K'
-YIN
I
":"
,O'l'f
Ro (KII) .. 2.5 YOUT
XR·4194
• ¥IIi
COMP+
'IAL
I
110 IISIT
...J
...,
OND
Yo-
,
L ________________
~------------------~
EQUIVALENT SCHEMATIC DIAGRAM
1-360
., -V.
~
XR·4195
+ 15V Dual-Tracking Voltage Regulator
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-4195 is a dual-polarity tracking regulator designed to provide balanced positive and negative 15V
output voltages at currents of up to 100mA.
COMP'
The device is ideal for local "on-card" regulation, which
eliminates the distribution problems associated with
single-point regulation. Intended for ease of application,
the XR-4195 requires only two external components for
operation.
PO$ITIVf.
H[(iUl ATOH
fiAl
FEATURES
Direct Replacement for RM/RC 4195
± 15V Operational Amplifier Power
Thermal Shutdown at Tj = + 175°C
Output Currents to 100mA
As a Single Output Regulator, it may be used with up to
+50V Output
Available in a-Pin Plastic Mini-DIP
Low External Parts Count
ORDERING INFORMATION
Part Number
Package
XR-4195CP
Dip
Operating Temperature
O°C to + 70°C
APPLICATIONS
Operational Amplifier Supply
On-Card Regulation
Regulating High Voltage
SYSTEM DESCRIPTION
The XR-4195 is a dual polarity tracking voltage regulator, internally trimmed to ± 15V. Only output capacitors
are required for operation. Internal protection circuits
include thermal shutdown and active current limiting.
The device may be configured as a single output high
voltage regulator by adding a voltage divider between
an output pin, the device ground (Pin 2) and system
ground.
ABSOLUTE MAXIMUM RATINGS
Input Voltage ±V to Ground
Power Dissipation at TA = 25°C
Load Current
Operating Junction Temperature
Range
Storage Temperature Range
±30 V
600mW
100 mA
O°C to + 125°C
- 65°C to + 150°C
1-361
XR·4195
ELECTRICAL CHARACTERISTICS
Tast Conditions: (lL
=
1mA, VCC
=
±20V, CL
=
10ltF unless otherwise specified)
XR·4195CP
PARAMETERS
MIN
TYP
MAX
UNITS
Line Regulation
2
20
mV
VIN
Load Regulation
5
30
mV
IL
0.005
0.015
%IOC
±1.5
±3.0
mA
30
V
Output Voltage Temperature
Stability
Standby Current Drain
Input Voltage Range
18
14.5
Output Voltage
Output Voltage Tracking
Ripple Rejection
15
15.5
V
±50
±300
mV
VIN
Ti
dB
Short-Circuit Current
220
mA
=
±30V, IL
Output Noise Voltage
60
ltV RMS
Internal Thermal Shutdown
175
°c
= OmA
+25°C
= 50mA
= +25°C
Ti = +25°C,
f = 100 Hz to
V
3
=
f = 120 Hz, Ti
+25°C
75
Input-Output Voltage Differential
CONDITIONS
= ±18to ±30V
= 1 to 100 mA
=
IL
Ti
100 kHz
THERMAL CHARACTERISTICS
XR·4195CP
PARAMETERS
MIN
TYP
Power Dissipation
Thermal Resistance
MAX
CONDITIONS
0.6W
TA
TC
= 25°C
= 25°C
OJ-C
210°C/W
OJ-A
+15V at lCOmA
Vo = +50V at lOOmA
-15V at 100mA
lO.F
10J.lF
Rl
R2
tr-l-i-;--.....,
.Pr-'I.
"---'_
-::-
+Vo
XR-4195
XR-4195
GND
GNO
R2
VO=+15V (1 +""R,"")
....,....--,r-ot
.1BV to +30V
(VO+3V)""+---1
I
c
.~
1
E1.5
--
!!
~ '.0
....
!!iU
l'
"
20
22
INPUT VOLTAGE - YIN
:M
H
0
5
~
.-Jot..
f.--'
0.5
i
!;
!I:
J
I-- r-
~PIC"~ f-po- f-..;;r"'-
!! •. 51--+--t--1r:•.:H..--+:.\.-!-:;I""t""-1
5
i1I!"Dtl~5J
0.5
il
!!
7.
.0
",.
D.L..D-.L..-!-:---!-::-':--'-:--~--:~-!
INPUT VOLTAGE - VIN
Figure 1. Input Current as a Function of Input Voltages
lOll
,
/
,
...
,
I
/
V
.I
I
/~I'
~
'.#
,.
,,It''j
L
~--
,-~~-t-<>
XR-2203
XR-2204
1-375
Special Functions
XR·S200
Multi-Function PLL System
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-S200 integrated circuit is a highly versatile,
multipurpose circuit that contains all of the essential
functions of most communication system designs on a
single monolithic substrate. The function contained in
the XR-S200 include: 1. a four quadrant analog multiplier, 2. a high frequency voltage controlled oscillator
(VCO) and 3. a high performance operational amplifier.
The three functions can be used independently, or directly interconnected in any order to perform a large
number of complex circuit functions, from phaselocked loops to the generation of complex waveforms.
The XR-S200 can accommodate both analog and digital
signals, over a frequency range of 0.1 Hz to 30 MHz,
and operate with a wide choice of power supplies extending from ± 3 volts to ± 30 volts.
FEATURES
Wide VCO Frequency Range
0.1 Hz to 300 MHz
Wide Supply Voltage Range
± 3V to ± 30 V
Uncommitted Inputs and Outputs for Maximum
Flexibility
Large Input Dynamic Range
UP AMP
CUMP
APPLICATIONS
Phase-locked loops
FM demodulation
Narrow and wideband FM
Commercial FM-IF
TV sound and SCA detection
FSK detection (MODEM)
PSK demodulation
Signal conditioning
Tracking filters
Frequency synthesis
Telemetry coding/decoding
AM detection
Quadrature detectors
Synchronous detectors
Linear sweep & AM generation
Crystal controlled
Suppressed carrier
Double sideband
Tone generation/detection
Waveform generation
Single/square/triangle/sawtooth
Analog multiplication
ABSOLUTE MAXIMUM RATINGS
Power Supply
Power Dissipation
Derate above +25°C
Temperature
Operating
Storage
Input Signal Level, Vs
30 Volts
900 mW
5 mW/oC
- 55°C to + 125°C
-65°C to + 150°C
6 V,p-p
ORDERING INFORMATION
1-376
Part Number
Package
Operating Temperature
XR-S200
Ceramic
O°C to + 70°C
XR·S200
ELECTRICAL SPECIFICATIONS (T = 25°C, 'v'SUPPLY = ± 10V)
LIMITS
PARAMETERS
MIN
TYP
MAX
UNITS
CONDITIONS
MULTIPLIER SECTION: See Figure 2, Rx = Ry = 15k, Pins 1, 2, 6, 23, 24 Grounded.
Output Offset Voltage
Input Bias Current
Input Offset Current
Linearity
(Output error, %
of full scale)
Scale Factor, KM
Input Resistance
3 dB Bandwidth
Phase detection B.W.
Differential Output Swing
Output Impedance
Single Ended
Differential
±40
5
0.1
0.3
3
50
±4
±120
15
1.0
mV
p.A
p.A
Vx = Vy = 0, Vio = IV3-V41
Measured at pins 5 and 7
Measured at pins 5 and 7
%
%
-5 < Vx < +5, Vy = ±5V
-5 < V~ < +5, Vx = ±5V
KM = 2 IRxRy (Adjustable)
f = 20 Hz, Measured at pins 5 and 7
CL oS 5 pF
Rx = Ry = 0
Measured across pins 3 and 4
1.0
1.5
0.1
1.0
6
100
±6
M!l
MHz
MHz
V pop
6
12
k!l
k!l
-
Measured at pins 3 and 4
OPERATIONAL AMPLIFIER SECTION: See Figure 10 and 11, RL = 20k, CL = 550 pF.
Input Bias Current
Input Offset Current
Input Offset Voltage
Differential Input Impedance
Resistance
Capacitance
Common Mode Range
Common Mode Rejection
Open Loop Voltage Gain
Output Impedance
Output Voltage Swing
Power Supply Sensitivity
Slew Rate
O.OS
0.02
1.0
0.5
0.2
6.0
p.A
p.A
mVdc
Open loop, f
0.4
70
66
±7
2.0
1.0
±S
90
SO
2
±9
30
2.5
M!l
pF
V
dB
dB
k!l
V
p.VN
V/p.sec
f
=
RL
Rs
Av
=
20 Hz
20 Hz
2:
oS
=
20 k!l
10 k!l
1, CL = 10 pF
VCO SECTION: See Figure 11, RL = 10k, fo = 1 MHz.
Upper Frequency Limit
Sweep Range
Linearity
(distortion for
df/f = 10%)
Frequency Stability
Power Supply
Temperature
Analog Input Impedance
Resistance
Capacitance
Output Amplitude
Output Rise Time
Fall Time
Input Common Mode Range
15
S:1
30
10:1
-
Co = 10 pF
fo = 10 kHz, See Figure 14
Digital Controls Off
Digital Controls Off
MHz
.2
1.0
%
O.OS
300
0.5
650
%N
VCC > SV, fo = 1 MHz
Sweep Input Open
ppm/oC
Measured at pins 23 and 24
0.1
+6
-4
0.5
1.5
3
15
20
+S
-6
M!l
pF
V pop
ns
ns
Vdc
Vdc
Squarewave
CL = 10 pF, RL
=
5 k!l
CAUTION: When using only some of the blocks within the XR-S200, the input terminals to the unused section must
be grounded (for split-supply operation); or connected to an ac ground biased at V + 12 (for single supply
operation).
1-377
XR·S200
XR-S200 ANALOG MULTIPLIER SECTION
10K
1{){lK
The analog multiplier in the XR-S200 (Figure 2) provides
linear four-quadrant multiplication over a broad range of
input signal levels. It also serves as a balanced modulator, phase comparator, or synchronous detector. Gain is
externally adjustable. Nonlinearity is less than 2% of
full scale output.
,IOV
n
')
1
10011.
All lUST
>--+-'''-0--0
OUTPUT
TYPICAL APPLICATIONS OF MULTIPLIER SECTION
•
•
•
•
•
•
Analog multiplication/division
Phase detection
Balanced modulation/demodulation
Electronic gain control
Synchronous detection
Frequency doubling
10V
TO X AND Y
AD,)
-=-
m ~SET
ANALOG MULTIPLICATION
Figure 3. Analog Multiplication
The XR-S200 multiplier section can be combined with
the amplifier section to perform analog multiplication
without the need for dc level shifting between input and
output. The amplifier functions as an operational amplifier with a single-ended output at ground level when
connected as shown in Figure 3.
VA(t)
AEFERENCE INPUT
~I--..---o:'----I
C,
IK
XR 5200
MULTIPLIER
SECTION
c,
5
'--T'"---r--T'"-'
SIGNAL INPUT
XR-S200
MULTIPLIER
SECTION
X-v GROUND
Vv
Cc "- COUPLING CAPACITOR
VA!!) ,. EAcos wo t
vs(t)
-=
OUTPUT
lK
v~f-4-O':"";
OUTPUT
3
X-INPUT
J. c.
'--"T"--"T""---r-~
~
Escos(wot
t
",I
C
e ..
BYPASS CAPACITOR
Figura 4. XR-S200 MuHipliar Saction as a Phasa Comparator
V-INPUT
normally a high level reference signal and the other input a low level information signal. Since the XR-S200
multiplier section offers symmetrical response with respect to the X and Y inputs, either input can be used as
the carrier or signal input. For low input levels, the conversion gain is proportional to the input signal amplitude. For high level inputs, (VS > 40 mV, rms) Kq, is
constant and approximately equal to 2V/rad.
Figura 2. XR-S200 Multlpllar Sactlon
PHASE COMPARATOR
For phase comparison, a low-level reference signal is
normally applied to one input and a high-level reference
or carrier signal to the other input, as in Figure 4. The
signalrnay be applied to either the X or Y input, since
the response is symmetrical.
SUPPRESSED-CARRIER AM
The multiplier generates suppressed-carrier AM signals
when connected as in Figure 6. Again, the symmetrical
response allows the X or Y inputs to be used interchangeably as the carrier or modulation inputs. The X
and Y offset adjustments optimize carrier suppression.
Gain control resistors RX and Ry typically range from 1
KO to 10 KO, depending on input signal amplitudes. The
values shown give approximately 60 dB carrier suppression at 500 kHz and 40 dB at 10 MHz.
If the two inputs, VR(t) and VS(t) are at the same frequency, then the dc voltage at the output of the phase
comparator can be related to the phase angle q, between the two signals as
vq, =
Kq,cosq,
where Kq, is the conversion gain in volts per radian (Figure 5). For phase comparator applications, one input is
1-378
XR·S200
DOUBLE-SIDEBAND AM GENERATION
AX
The connection for double-sideband AM generation is
shown in Figure 7. The dc offset adjustment on the
modulation input terminal sets the carrier output level,
while the dc offset of the carrier input governs symmetry of the output waveform. The modulation input can
also be used as a linear gain control (AGC), to control
amplification with respect to the carrier input signals.
22
MODULATION
INPUT
IOV
8K Ry
8K
+Vcc
·lOV
10
11
0-----+------\
XR 5200
MULTIPLIER
SECTION
'"
"
->-
-10V
0.1
0.-
"
Figure 7. Double Sideband Amplitude Modulation Using
XR-S200 Multiplier Section
HIGH LEVEL INPUT
CONSTANT'" lV. rms
o
u
w
'"
it
--
u
I
tE::>
~ 2.0
~
.
1.3V
to" tOl
15
INTERNAL
BIAS
fa'"' 110
:J
"z
3.0V
-VEE
12
~-----4---------4-----o0R
DIGITAL INPUT CODE
GROUND
Figure 15. Explanation of veo Digital Controls
Figure 13. VCO Digital Tuning Characteristics
1-381
(MOST NEGATIVE
POINT!
XR·S200
TYPICAL APPLICATIONS OF YCO SECTION
FREQUENCY·SELECTIVE FM DEMODULATION
•
•
•
•
•
•
•
•
•
•
For FM demodulation, the PLL connection is used (Figure 17.) The multiplier, with its gain terminals shorted,
serves as the phase detector, and the VCO and filter
govern the operating frequencies.
Voltage/frequency conversion
Phase-locked loops
Frequency synthesis
Signal conditioning
Carrier generation
Synchronization
Sweep and FM generator
Crystal oscillator
Waveform generator
Keyed oscillator
The gain block is used as an audio preamplifier to set
the demodulated output signal level. Volume is controlled by the variable feedback resistor R7. If R6
equals R7, the dc output level will be very close to
ground, for circuit operation with split power supplies.
C3 .is the amplifier's compensation capacitor. R8 and
C2 set the output de-emphasis time constant TO, which
is normally 75 /Lsec. for commercial FM applications (fo
= 10.7 MHz).
APPLICATIONS OF THE XR·S200 SYSTEM
PHASE·LOCKED LOOP
FSK DETECTION
A self-contained phase-locked loop is formed by connecting the XR-S200 as outlined in Figure 16.
FSK signals are detected and demodulated with the
PLL connection, as well. It is shown in Figure 18 as a
monolithic MODEM suitable for Bell 103 or 202 type data sets operating at data rates to 1800 baud. An input
frequency shift corresponding to a data bit causes the
multiplier's dc voltage output to reverse polarity. The dc
level is changed to a binary output pulse by the gain
block, connected as a voltage comparator.
In most PLL applications, the amplifier is available for
functions useful outside the loop, since the phase comparator (multiplier section) and VCO provide sufficient
conversion gain. In this case, the amplifier gain does
not enter the PLL gain expression. Assuming unity dc
gain for the filter, the PLL loop gain is KT = K,p KO
where K.p and KO are the multiplier and VCO conversion
gains, respectively.
c,
vco
OUTPUT
Figure 16. XR·S2DD as a Phase·Locked Loop
("
COUPllNti CAPACI lUI'!
CH
BYPAS~
CAPACI TOH
Figure 18. FSK Detection
FREQUENCY SYNTHESIZER
Frequency synthesis is performed in Figure 19 by a
phase-locked loop closed with a programmable counter
or digital divide-by·N circuit inserted into the feedback
loop. The VCO frequency is divided by N, so that when
the circuit locks to an input signal at frequency fs, the
Figure 17. Circuit Connection for FM Detection
1-382
XR·S200
oscillator output is Nfs . A large number of discrete frequencies can be synthesized from a given reference
frequency by changing N.
s.... uP
SQUAREWAVE
OUTPUT
IJV ~!>'
WAVEf()RM
o~~~~~~__~
TRIAfII(,UQR
SlfIIEWAVE
OUTPUT
16Vpp,
C<
COUPLING CAP
C8
BYp .... S~ CAP
Figure 21. Wavelorm Generator Typical Circuit Connection
Diagram
Figure 19. Frequency Synthesizer
TRACKING FILTER AND WIDI'BAND DISCRIMINATOR
In tracking filter applications, the XR-S200 again forms
a PLL system (Figure 20). When the PLL locks on an input signal, it functions as a "frequency-filter" and produces a filtered version of the input signal frequency at
the veo output. Since it can track the input over a
broad range of frequencies around the veo freerunning frequency, it is also called a "tracking filter".
The system can track input signals over a 3:1 frequency range.
WAVEFORM GENERATOR
The XR·S200 can also be interconnected to form a versatile waveform generator. The typical circuit shown in
Figure 21 generates the basic periodic square (or saw·
tooth) waveform. The multiplier section, connected as a
linear differential amplifier, convert the differential sawtooth waveform input into a triangle wave output at pins
J
Figure 21-1. Basic Waveforms Available Irom XR-S2DD
3 and 4. The waveform adjustment pot across pins 8
and 9 can be used to round the peaks of the triangle
waveform and convert it to a low distortion sinewave
(THD<2%). Terminals 3 and 4 can be used either differentially or single endedly to provide both in-phase
and out-of-phase output waveforms.
The output frequency can be swept or frequency modulated by applying the proper analog control input to the
circuit. For linear FM modulation with relatively small
frequency deviation (.6.f/f < 10 %) the modulation input
can be applied across terminals 23 and 24. For large
deviation sweep inputs, a negative going sweep voltage, Vs , can be applied to pin 18.
C
'
INPUT
SIGNAL
Cc
This allows the frequency to be voltage-tuned over approximately a 10:1 range in frequency. The digital control inputs (15 and 16) can be used for frequency-shiftkeying (FSK) applications. They can be disabled by connecting them to ground through a current-limiting
resistor.
COUPLING CAPACITOR
Figure 20. Recommended Circuit Connection for Tracking
Filter Application (10 = 1 MHz)
1-383
XR·S200
AM 8r FM SIGNAL GENERATION
The oscillator and multiplier sections can be interconnected as a general purpose radio·frequency signal
generator with AM, FM and sweep capability as shown
in Figure 22.
AM
The oscillator section can be used as a voltage·tuned,
variable frequency oscillator, or as a highly stable carri·
er or reference generator by connecting a reference
crystal across terminals 19 and 20. In this case, a small
capacitor (typically 10 to 100 pF) fine tunes the crystal
frequency. The multiplier section introduces the amplitude modulation on the carrier signal generated by the
veo. The balanced nature of the multiplier allows suppressed carrier as well as double sideband modulation
(Figures 22·1 and 22·2). Typical carrier suppression is
in excess of 40 dB for frequencies up to 10 MHz.
o----j
MODU!.ATION
INPUT~
Cc
2QK
Figure 22. Circuit Connection 'or AM/FM or CrystalControlled AM Generator Application
If a timing capacitor is used instead of a crystal, the os·
cillator section can provide highly linear FM or frequency sweep. The digital control terminals of the oscillator
are used for frequency-shift-keying.
j
j
t
_. 1
Figure 22-1. Double Sideband AM Output Waveform
'carrier = 3.688 MHz 'mod = 1 kHz
(90% modulation)
I
MULT'PUll!
- - SECTION
Figure 22-2. Suppressed Carrier AM Output Waveform
'carrier = 3.688 MHz 'mod = 1 kHz
j----
- rl
OSCILLAlOA
SECTION
1---
- , -
EQUIVALENT SCHEMATIC DIAGRAM
1·384
UP
-.,..P
I
SfCTlO"'-
XR·1310
Stereo Demodulator
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-131 0 is a unique FM stereo demodulator which
uses phase-locked techniques to derive the right and
left audio channels from the composite signal. Using a
phase-locked loop to regenerate the 38 kHz subcarrier,
it requires no external L-C tanks for tuning. Alignment is
accomplished with a single potentiometer.
POWER
SUPPLY
VCO
CONTROL
COMPOSITE
INPUT
LOOP
FILTER
COMPOSITE
OUTPUT
FILTER
LOOP
PHASE
LEFT OUTPUTI
DEEMPHASIS
FEATURES
11
RIGHT OUTPUTI
DEEMPHASIS
Requires No Inductors
Low External Part Count
Simple, Noncritical Tuning by Single
Potentiometer Adjustment
Internal Stereo/Monaural Switch with
100 mA Lamp Driving Capability
Wide Dynamic Range: 600 mV (RMS)
Maximum Composite
Input Signal
Wide Supply Voltage Range: 8 to 14 Volts
Excellent Channel Separation
Low Distortion
Excellent SCA Rejection
OETECTOR
INPUTS
PILOT
·MONITOR
LAMP
DRIVER
THRESHOLD
FILTER
THRESHOLD
FILTER
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-1310CP
Plastic
-40°C to +85°C
SYSTEM DESCRIPTION
APPLICATIONS
The XR-1310 is a complete stereo demodulator specifically designed for transforming a composite FM stereo
signal into its left and right channel components.
FM Stereo Demodulation
Stereo Indicator
The composite FM stereo input signal, from the receiver detector, is applied to the buffer amplifier, Pin 2. Buffered output (gain = 1) is applied to the L + R, L - R decoder.
ABSOLUTE MAXIMUM RATINGS
The VCO of the PLL runs at 76 kHz, four times the 19
kHz pilot frequency. Free-running frequency is set by
the parallel RC circuit on Pin 14. The VCO output drives
a controlled switch which allows demodulation. When
the PLL is locked, the lamp driver open collector output
(Pin 6) can sink up to 100 mAo
(TA = +25°C unless otherwise noted)
Power Supply Voltage
14V
Lamp Current
75 mA
(nominal rating, 12 V lamp)
Power Dissipation
625 mW
(package limitation)
5.0 mW/oC
Derate above TA = + 25°C
- 40 to + 85°C
Operating Temperature
Range (Ambient)
- 65 to + 150°C
Storage Temperature Range
Left and right channel outputs are taken from Pins 4
and 5 respectively. De-emphasis is performed by the
RC circuit here; slightly higher gain is possible by increasing the resistor size, but the RC product should
remain constant.
1-385
XR·1310
ELECTRICAL CHARACTERISTICS
Test Conditions: Unless otherwise noted; VCC' = + 12 Vdc, TA = + 25°C, 560 mV (RMS) (2.8 Vp-p) standard multiplex
composite signal with Lor R channel only modulated at 1.0 kHz and with 100 mV (RMS) (10% pilot
level), using circuit of Figure 1.
PARAMETERS
MIN
Maximum Standard Composite Input Signal (0.5% THD)
2.8
Maximum Monaural Input Signal (1.0% THD)
2.8
Input Impedance
Stereo Channel Separation (50 Hz -
30
15 KHz)
Audio Output Voltage (deSired channel)
TYP
MAX
UNIT
Vp-p
Vp-p
50
kO
40
dB
mV (RMS)
485
1.5
Monaural Channel Balance (pilot tone "off")
dB
Total Harmonic Distortion
0.3
%
Ultrasonic Frequency Rejection 19 kHz
38 kHz
34.4
45
dB
80
dB
Inherent SCA Rejection
(f = 67 kHz; 9.0 kHz beat note measured with
1.0 kHz modulation "off")
Stereo Switch Level
(19 kHz input for lamp "on")
Hysteresis
13
20
6
±3.5
Capture Range (permissable tuning error of internal
oscillator, reference circuit values of Figure 1)
%
14
8.0
Operating Supply Voltage (loads reduced to 2.7 kO for
8.0-volt operation)
Current Drain (lamp "off")
mV (RMS)
dB
Vdc
mAdc
13
'Symbols conform to JEDEC Engineering Bulletin No.1 where applicable.
Vee
0.05 ~F
14
470 pF
2.0 IJ.F
INPUT
0.02
0----)
13
16K
~F
12
lK
3.9K
XR-1310
II
3.9K
10
19 kHz
MONITOR
0.021iF
0.25
STEREO
LAMP
(100 mAl
Figure 1. Typical Application
1·386
~F
5K
XR·2264/2265
Pulse-Proportional Servo Circuit
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-2264 and 2265 are Monolithic circuits designed
for use in pulse-proportional servo systems. They have
been specifically designed for Radio Control applications. These devices are capable of controlling positions in direct proportion to the width of input pulses.
The 2264 can interface directly with servo motors requiring up to 350mA of drive current. The 2265 with
open collector outputs can drive relays, optical couplers and triacs, directly. Both the 2264 and 2265 can
drive external PNP transistors for 500mA output drive
requirements.
l
'ULSE
STRETCHER
AC
BOOST
OUT
OUT
GAOUNO
GAOUNO
The XR-2264 or 2265, combined with a servo motor and
a feedback potentiometer form a closed-loop system.
These devices have internal one-shot multivibrators.
The pulse width of this one-shot is controlled by the servo potentiometer. When an input pulse is applied, the
motor is turned "on" in the direction necessary to make
the internal one-shot pulse width equal to the incoming
pulse width. Because the transfer characteristics of the
XR-2264 and 2265 can be controlled by the selection of
external components, it can be used in many industrial
and radio controlled servo-system applications.
OUT
BOOST
OUT
PULSE
IN
ORDERING INFORMATION
FEATURES
Wide Supply Voltage Range (3.OV to 6.0V)
Bi-directional Operation with Single Supply
Separately-Adjustable Dead Band and Pulse Stretching
2264 - 350mA Source and Sink on Chip.
500mA with External PNP
2265 - 500mA Sink Capability on chip.
500mA Sink or Source Capability with external PNP
Package
Plastic DualIn-Line
Operating Temperature
-10°C to +50°C
SYSTEM DESCRIPTION
Figure 3 shows the circuit connection diagram for the
XR-2264. The external component values shown are
selected for a pulse width range of 1 to 2 msec, a frame
time of 12.5 msec, and a dead band' that is suitable for
use with small radio-controlled servos. However, with a
proper choice of external components, the characteristics of these devices can be adapted to provide optimum performance for a broad range of hobby and industrial servo control applications.
APPLICATIONS
Remote Control Toys
Robotics Applications
The shaft of potentiometer R2 is connected to the servo
output shaft; the voltage on the wiper provides positional feedback to the one-shot multivibrator of the XR-2264
or 2265. The one-shot pulse width range is set by the
product of Rl and Cl; Rl should be kept in the range of
8Kfl to 16Kfl. For operation over a range of pulse widths
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Power Dissipation
Storage Temperature Range
Part Number
XR-2264 CP
XR-2265 CP
6.5V
550 mW
-65°C to + 150°C
1-387
XR·2264/2265
ELECTRICAL CHARACTERISTICS
Tast Conditions: VCC
= 5.0V, TA = 25°C
LIMIT
PARAMETERS
Supply Voltage
MIN
TYP
MAX
UNITS
3.2
5.0
6.5
V
4.5
10.0
mA
2.0
2.2
2.4
V
Supply Current
Regulated Output Voltage
Input Current
0.1
Input Voltage Range
CONDITIONS
Measured into Pins 1 & 7
Voltage at Pin 12
mA
2.4
Pulse Timing Error
6.0
V
±300
/LSec
Initial Setting 1.07 sec;
Curcuit of Figure 3
OUTPUT CHARACTERISTICS
LIMIT
PARAMETER
DEVICE
2264
MIN
Output Current Range
0
Output Current Range
0
TYP
VCE
VCE (VCC - VOH)
2265
Output Current Range
0
VCE
MAX
UNITS
500
mA
I sink
CONDITIONS
I source
350
mA
0.25
V
I sink 500mA
1
V
I source 350mA
500
mA
0.25
V
I sink
I sink 500mA
of less than 2 to 1, the value of potentiometer R2 may
be reduced; the value of the 2.2KO resistor to ground
should be increased by about the same amount.
The voltage on C2 provides the input signal for the Schmitt trigger. In order for the motor to be driven, pin 14
must remain low, long enough to pull C2 down to the
lower threshold via R3. The motor will be turned off only
after pin 14 has turned off and C2 has charged to the
upper Schmitt trigger threshold through R4. Thus, the
dead band is controlled by C2 (R3 + Ri) where Ri is the
"on" resistance at Pin 14. The pulse stretching is controlled by the product of C2 and R4. Figure 4 shows the
effect of R3 and R4 upon the dead band and pulsestretching performance of the XR-2264 with C2 =
0.22/LF.
A TRANSMITTED
SIGNAL
II OEMOOULATED
SIGNAL
"Note: The "Dead band" is the narrow region about a
given shaft position which 2264 will not produce a
Stretched Pulse large enough to drive the motor. Some
dead band width is necessary because the motor shaft
has inertia; otherwise, the motor would never stop
"hunting" its target position.
..... ...-
~-
NO~
Figure 2. Radio Control System
1-388
XR·2264/2265
-zoo
- tID
-110
-140
-120
-10
- tOO
c
"NOTE: XR·2264 01 and 02 optional; only needed for
Servos requiring 500mA drive current.
""NOTE: XR·2265 01 and 02 needed if output current
source is required.
B
Figure 4. XR-2264 and XR-2265 Output
Dead Band. Circuit of Figure 3
Figure 3. Connection Diagram of XR-2264 and XR-2265 Servo
ControllC
1·389
VS.
Input Showing
'Y¥. I:vnR
~1··
XR·2266
I~
Monolithic Servo Controller
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-2266 is a monolithic servo controller specifically designed for radio controlled model cars. The device is capable of controlling speed in forward or reverse, direction Qf turn, backup lights, and turn signals
with programmable flash rate. Supply voltage may
range from 3.5V to 9V.
PULSE STRETCHER
SP£EDSEAYO
INTEGRATOR
PUlSE STRETCHER
STEERING SEAVO
2
CAPACITOR FOR
STEERtNG SERVO
SPEED SERVO
CAPACITOR FOR
SPEED SERVO
OUTPUT
OUTPUT
SPEED SERVO
REFERENCE GENERATOR
SERVO POT INPUT
FEATURES
Internal Channel Divider
Internal Steering Servo with Direct Drive for
Servomotor and Turn Signal Indicators
Directional Signal Time Constant
Externally Settable
Variable Speed Control with Direct Drive
for Backup lights
Wide Supply Range (3.5 - 8.0 volts)
Steering and Speed Servos Independently
Programmed
5
Hf-+--'
BACKUP
LIGHT
6 ~~:j===;-,
DIRECTtONAL SIGNAL
TfME CONSTANT
STEERING SERVO
OUTPUT
BLINKER OUTPUT
8
STEERING SERYO
OUTPUT
BUNKER OUTPUT
9
GROUND
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-2266
Plastic
O°C to + 70°C
SYSTEM DESCRIPTION
APPLICATIONS
The XR-2266 is a monolithic servo controller system
specifically designed for radio-controlled model cars.
The integrated circuit is a self-contained system made
up of two servo controller channels: one controls the
direction and speed of travel, the other provides the
steering function. The circuit contains an internal channel separator section which automatically steers the incoming control signal to the appropriate servo controller channel.
Radio Controlled Cars
The entire servo controller system is available in an 18Pin dual-in-line package, with terminals provided for accessory controls such as turn indicator signals and
backup lights. The entire system is fabricated on a
monolithic chip, using low-power integrated injection
logic (12L) technology along with precision analog Circuitry. It operates with supply voltages in the range of
3.5 volts to 8 volts.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Power Dissipation
Derate above TA = 25°C
Storage Temperature Range
9V
1100 mW
6 mW/oC
- 65°C to + 150°C
1-390
XR·2266
ELECTRICAL CHARACTERISTICS
Test Conditions: VCC = 6 Volts TA = 25°C unless otherwise specified
LIMITS
PARAMETERS
Supply Current
Operating Supply Range
Input Threshold
Reference Generator Output Current
MIN
3.5
TYP
30
6.0
0.7
100
MAX
UNITS
8.0
rnA
V
V
CONDITIONS
p.A
Measured at Pin 6
%
%
%
rnA
Voltage at Pin 6 (Blinker "off")
Voltage at Pin 6 (Pin 8 Blinker "on")
Voltage at Pin 6 (Pin 9 Blinker "on")
rnA
rnA
Pin 11 or 12
Pin 11 or 12
rnA
Pin 14
Directional Detector
Pin 5 Voltage
Pin 5 Voltage
Pin 5 Voltage
Output Current
55
61
48
100
Steering SERVO
Output Soruce Current
Output Sink Current
350
350
Reverse Detector
Output Current
100
Speed Control Servo
Output HIGH Voltage
Output Low Voltage
Output Impedance
VCC-1V
0.2
700
1-391
V
V
!l
Pin 15 or 16
Pin 15 or 16
Pin 15 or 16
XR·2266
tection circuit has also been built into the IC to detect
when the car is going in reverse and turn on the backup
lights.
PRINCIPLES OF OPERATION
The theory of operation can be explained with reference to the block diagram of Figure 2 and the timing diagram of Figure 3. The direction and speed information
are encoded onto a carrier by either Amplitude Modulation (illustrated Curve A) or Frequency Modulation (not
shown). This signal is received and demodulated into
Waveform B. The timing of Waveform B is as follows: TF
is the frame time and determines the frequency with
which the servos are controlled. TS is a space pulse
used to separate the channel information of T1 and T2.
The width of T1 and T2 contain the steering and speed
information respectively.
SYSTEM BLOCKS
The XR-2266 is comprised of three independent systems internally connected as in Figure 4 to perform the
complete car function. These blocks are the channel divider, steering servo and a speed control circuil. (While
a total understanding of these circuits is not necessary
a fundamental knowledge of the operation of each
block will be an asset to any servo design.)
Waveform B is applied to the input of the XR-2266. This
signal is integrated into Waveform C which is then
squared to form D. Waveform D is used as a reset to the
channel divider circuil. The channel divider circuit triggers on the leading edge of the input signal and generates two outputs; one for steering and the other for the
speed control; Waveforms E and F, respectively.
CHANNEL
DIVIDER
Waveform E is applied to the input of Servo No.1 which
serves as the pOSitional control for the steering wheel.
The servo pot on the linkage forms a closed loop system with the servoamplifier to position the front wheels
to the required position. The servo pot is also connected to the directional indicator circuit which determines
whether the wheels are turned enough to enable the
blinker lights.
Figure 4. Three Primary Systems of XR-2266
Channel Divider: The function of the channel divider is to
decode the channel information from the demodulated
input signal and to synchronize the receiver to the
transmitter. The synchronization is required to assure
that the decoded input is applied to the correct servo.
The generation of the synchronization signal is illustrated in Figure 3 and can be explained as follows: The
input signal B is integrated by the RC time constant on
pin 2 to form waveform C. This integrated signal is then
squared to form the synchronization signal D. This signal resets the channel divider when high, guaranteeing
that the first input be directed to the channel one servo
and the second input be directed to the channel two
servo, as illustrated by waveforms E and F, respectively.
The width of the input signals is determined by the time
interval between two successive positive going edges
of waveform B. After the channel two input ends, the integrator charges up to the reset level and enables
channel one for the next rising edge of the input signal.
The time constant for the integrator is externally set by
the RC time constant on pin 2. It is recommended that
the time constant be chosen such that the reset occurs
midway between the input frame time.
Waveform F is the input to the variable speed control
servo. This servo determines the error between the input signal and the preset nominal value and applies
drive to the motor proportional to this differel"lce. A de-
Figure 2. Radio Controlled System Block Diagram
••
••
••
c
~~--------~
L--JIl~
~
______________
__~rl
\~--------~
~rI~
______________
rl
Figure 3. Timing Diagram
1-392
____________
rI~__________
~rI~
XR·2266
Steering Servo: The block diagram of the steering servoamplifier is illustrated in Figure 5. The primary function of this block is to control the position of the front
wheels of the car in direct proportion to the input pulse
width. The XR-2266 has the additional feature of being
able to detect the magnitude and direction of the position of the wheels from their center position and if it is
greater than an externally preset amount, to activate a
blinker circuit for the appropriate turn-direction. The operation of the steering servoamplifier can be explained
with reference to the block diagram of Figure 5 and timing diagram Figure 6. On the leading edge of the input
signal an internal one-shot is triggered. The one-shot
generates an output pulse whose width is directly proportional to the present position of the shaft of the servomotor. The position information is supplied via the
servo pot. The width of these two pulses are then compared and two error Signals are generated; one is the
directional error which is used to determine the output
drive direction and the other is the magnitude error
which is applied to the pulse stretcher section which
determines whether the error was of sufficient magnitude to enable the output driver stage. If the dead band
is exceeded, the error pulse of several microseconds is
then stretched to several milliseconds of output drive.
The dead band is required to assure that the motor
does not oscillate about its center point. The XR-2266
has internal driver transistors that are capable of sinking or sourcing 350 mAo The positional information from
the servo pot is also applied to a window comparator
and the output of this circuit determines the deviation
of the steering wheel from its center pOSition. If this is
greater than the preset amount, the blinker signals are
activated. The time constant of the blinkers is set by the
capacitor on pin 7. The blinker outputs are open collector type capable of sinking 100 mA each.
Speed Control Circuit: The channel two output Waveform
F from the channel divider, as shown in Figure 7, is applied to the input of the speed control servo. This circuit
is similar to the steering control servo with the exception that it is operated in an open loop configuration.
Thus, the duty cycle of the output drive increases until
a maximum drive is reached. The drive characteristics
for the speed control are set independently of the steering by an RC time constant on pin 18. Due to the high
power motors required for speed control, an external
driver transistor must be used. A typical connection for
these transistors is illustrated in Figure 7. The speed
control amplifier also features an additional output for
the backup lights. This output is obtained from the directionallogic which determines whether the car is going in the forward or reverse direction. The motor terminals could also be reversed and the output used to
drive the front headlights when the car is going forward.
The output for the driver lamps is an open collector
transistor and is capable of sinking 100 mAo Since this
is an open collector output, care should be taken to
avoid any possible shorting to the Vee pin, as this will
damage the device.
Figure 7. Speed Control Servo System with Connection lor
External Driver Transistors
DESCRIPTION OF CONTROLS
Input (Pin 1): The demodulated output from the receiver
is applied to this pin. The threshold for the input is approximately 0.7V. It is recommended that a 0.0022 ,.F
capacitor be connected from this point to ground to
eliminate any RF signal at the input.
Reset Integrator (Pin 2): The function of this pin is to synchronize the servo control to the transmitter. This assures that the steering and speed control signals are
not interchanged. The time constant used for this circuit is dependent upon the frame time of the input signal. For a 15 millisecond frame, the value for Rl is 510K
and for Cl, 0.1 ,.F. Other frame rates may be used, in
which case the RC time constant may be determined by
the following equation:
Figure 5. Steering Servo System
where
TF
X
TN
= Frame Time
= Number of Servos
= Nominal Pulse Width for Servos
VCC = Nominal Supply Voltage
Figure 6. Timing Diagram
1-393
XR·2266
Pulse Stretcher (Pin 17 &0 18): The RC time constant on pin
17 and pin 18 is used to set the dead band and the maximum drive pulse to the steering servo and speed control servo, respectively. The dead band time is determined by:
Timing Cap for Steering Servo (Pin 3): The capacitor on this
pin is used to determine the nominal one-shot time constant for the steering control. The capacitor value is
chosen by the following equation:
C2 = TN/(R2
+
Rp/2)
TdS = (51.4)(C)
where R2 is a 1K potentiometer and Rp is the servo pot,
nominally 5K. This yields 0.47 IotF for C2. RF is a damping resistor that provides a momentum feedback to prevent the servo from overshooting. The recommended
values for RF are 100K to 700K, depending on the required loop damping.
The maximum drive time is determined by:
TMD= RC1n [(vcc- .73e-(1x10- 6/C))/(VCC- .66)]
Power Supply (Pin 13 &0 10): The battery should be connected from pin 13 (VCC) to pin 10 (ground). The operating power supply range is 3.5 to 9 volts. A 100 IotF capacitor is recommended across the power supply terminals.
Timing Cap for Speed Control (Pin 4): This capacitor determines the nominal one-shot time constant for the speed
control servo. The capacitor value is determined by:
C3 = 1.3 TN/(Rp
+
APPLICATION EXAMPLE
R2)
Reference Generator (Pin 5): Pin 5 is used to generate the
reference level for the speed and steering servos and
also control the degree of turning before the directional
indicators are activated. This pin is directly connected
to one end of the servo pot with the other connected to
a 1K pot or fixed resistor to ground. This 1K pot is used
to adjust the dead time for the directional indicators. In
noisy environments, pin 5 should be bypassed to
ground via a 0.001 IotF capacitor.
The method for determining the component values for
any servo application can be obtained by the following
design rules. These equations will yield values suitable
for proper operation and can later be adjusted to suit
particular applications. For the example chosen,the
frame time is 15 ms and the pulse width is nominally
1.4 ms with a deviation of 500 lots. Dead band is chosen
to be 30 lots and 80 lots for the steering and speed control
sections, respectively. The servo pot is a 5K pot and the
operating supply voltage is 6 volts.
Steering Positional Input (Pin 6): The wiper of the servo pot
is connected to this pin to supply the positional information to the one-shot of the steering servo. In noisy environments this pin should be bypassed to ground via a
0.002 IotF capacitor.
Procedure:
1. To determine the time constant of the integrator on
pin 2, use the following formula with R1 assumed to
be between 100K and 1M. In this example we set C1
= 0.1 IotF and calculate R1.
Directional Signal Time Constant (Pin 7): The capaCitor connected to this pin determines the time constant for the
directional indicators. The ratio of 'ON' to 'OFF' is approximately 2:1 and the frequency is determined by:
R1 =[TF - X(TN)]/2C11 n[Vcd(Vcc - .66)]
This
yi~lds
R1 '" 510K
F(Hz) = 81/C4 (IotF)
2. C3 and R2 setting (using a 1K pot) is determined by
the following: First approximate R2 to be one half of
its value and solve for C3.
Outputs for Directional Indicators (Pin 8 &0 9): These pins are
used to drive the directional signal indicators. These
are open collector outputs that can sink a maximum
current of 100 mA.
C3 = 1.3TN/(Rp
Steering Motor Drive (Pin 11 &0 12): These outputs connect
directly to the steering servomotor and are capable of
sinking or sourcing 350 mAo
+
R2/2)
C3'" .33 IotF
C3 = 0.25 IotF
Output for Backup Ughts (Pin 14): This terminal is activated when the car is driving in the reverse direction.
This is an open collector output with a maximum current of 100 mAo
Select nearest standard value for C3 and calculate
R2 value
Note: by reversing the motor leads, this terminal could
be used to control front headlights when the car is moving forward.
R2 '" 5150
R2 = (1.3TN/C3) - Rp
3. C2 is determined by the following: Use value for R2
as calculated above.
Output for Speed Control (Pin 15 &0 16): These pins are used
to drive an external power bridge to control the speed
of the car. A typical connection is illustrated in Figure 7.
C2 = TN/(R2
+
Rp/2)
C2 '" .47 IotF
1-394
XR·2266
9. Set RF = 510K. To adjust value see Table I.
4. C4 determines the blinker frequency, for a frequency
of 2 times per second.
The complete circuit with the calculated values is illustrated in Figure 8. The circuit layout is illustrated in Figure 9.
C4(Hz) = 81/F(Hz)
C4 "" 47.0 ",F
Table I lists the recommended values for the servo application outlined above and describes the result if improper values are used.
5. C5 determines the dead band time for the steering
servo for most car applications. This is chosen to be
approximately 30 ",s. Solving for C5 yields:
C5 = TdB/51.4
C5 "" .47 ",F
6. R5 is selected via the formula
R5 = TMO/[C1n(VCC- .73e-(1x10- 6 /4C»NCC- .66)]
R5 = 910K
7. C6 is chosen with the same formula as C5 except
dead band is set to approximately 80 "'s. This gives
the system better speed control.
Figure 8. Typical Application Schematic
8. R6 is chosen via the same equation as R5.
R6= TMO/[C1n(VCC- .73e-(1X10- 6/C»NCC- .66)]
R6 = 430K
XR-2266
GND MO
MO
Figure g. Printed Circuit Board Layout (4x)
1-395
XR·2266
TABLE I
COMPONENT
NUMBER
R1
510K
RF
510K
VALUES
EFFECTS
Small
The integrator rise time becomes too fast and the fall time becomes too slow.
Therefore, the integrator may reset too soon.
Large
The integrator rise time becomes too slow and the integrator may not reset
before the next input.
Recommended
200K -
Small
Too much negative feedback occurs, causing the response of the servo to be
too slow.
700 K carbon film R25 series.
Large
Almost no negative feedback occurs and a large positional overshoot results.
Recommended
100K - 800K should be selected by the actual test results (dependent upon
motor gears and linkage used). Carbon film R25 series.
Small
The pulse stretcher gain becomes too small and this reduces output drive time
causing wheels to turn slowly.
Large
The pulse stretcher gain becomes too large and the motor tends to oscillate
(hunt) about its position.
Recommended
500K - 1M, largely dependant upon the value of C5, frame time and maximum
deviation of the input pulse width. The equation for determining the nominal
value is given in the "Description of Controls" section for pins 17 and 18.
Small
The pulse stretcher gain becomes too small and the maximum speed of the car
is reduced.
Large
The pulse stretcher gain becomes too large and the car speed becomes hard to
control. It is either 'ON' full, or 'OFF'.
Recommended
400K - 700K, depending on the value of the capacitor; since this is for the
speed, the dead band width is set larger and pulse stretcher gain is set high.
Carbon film R25 series.
~~
Recommended
This is the servo pot connected to the steering linkage, a B type volume
potentiometer is recommended.
R2
1K
Recommended
This potentiometer is used to set both the neutral position for the speed control
and the range of operation for the directional indicators. A temperature stable
carbon type is recommended.
C1
0.1,..F
Small
The charging time tends to be short and the discharging time constant tends to
be long, therefore, the integrator may reset too soon.
Large
The charging time tends to become long and the integrator may not reset before
the next input.
Recommended
If R1 = 510K, C1 should be between 0.047 ,..F to 0.22 ,..F. Mylar recommended.
R5
910K
R6
430K
1-396
XR·2266
COMPONENT
NUMBER
VALUES
EFFECTS
Small
The width of the one-shot for the steering servo becomes too small and the front
wheels may turn fully in one direction.
Large
The width of the one-shot for the steering servo becomes too large and the front
wheels may turn fully in one direction.
Recommended
If the nominal input width is 1.4 ms, 0.47 /-LF is recommended. For operation
with other conditions, see "Description of Controls" section for pin 3. Tantalum
type is recommended.
Small
The width of the one-shot for the speed control servo becomes too small and
drive occurs in only one direction.
Large
The width of the one-shot for the speed control servo becomes too large and
drive occurs only in one direction.
Recommended
If the nominal input width is 1.4 ms, 0.33 /-LF is recommended. For operation
with other conditions, see "Description of Controls" section for pin 4. Tantalum
type is recommended.
C4
33/-LF
Recommended
This capacitor determines the direction signal time constant. The capacitor
value is determined by the equation in the "Description of Controls" section for
pin 7.
C5
0.47/-LF
Small
Dependent upon the value of R5. Generally the pulse stretcher gain becomes
smaller, thus, slowing down the general speed and making acute turns slower.
This also decreases dead band causing hunting about its position.
Large
Depending on the value of R5, the pulse stretcher gain becomes extremely
large and although turning speed improves, the hunting condition becomes
worse. This also increased dead band causing the motor to jump position.
Recommended
In case of R5 = 910K, 0.1 /-LF to 0.S8 /-LF is suitable. Tantalum type is
recommended.
Small
Depending on the value of RS, the pulse stretcher gain becomes smaller and
you cannot achieve 100% drive; also, the dead band is reduced and the neutral
position on the stick may be eliminated.
Large
The pulse stretch gain increases causing rapid increase in speed, once the
dead band is exceeded; also, the dead band increases causing a long amount
of neutral position in the control stick.
Recommended
In case of R2 = 430K, 0.S8 to 2.2 /-LF is suitable. Tantalum type is
recommended.
C7
2200 pF
Recommended
As mentioned in the "Description of Controls" section for pin 2, this value
should be between 0.001 and 0.01 /-LF. Ceramic or mylar is the best choice.
C8
1000 pF
Recommended
As mentioned in the "Description of Controls" section for pin 5, this value
should be between 0.01 and 0.001 /-LF. Ceramic or mylar are recommended.
C9
Recommended
Same as above.
ClO
100/-LF
Recommended
As mentioned in the "Description of Controls" section for pin 10 and 13, this
capacitor helps to stabilize the power supply when the car is running. If
opelation becomes intermittent, this value should be increased. Recommended
10 to 470 /-LF tantalum.
C2
0.47/-LF
C3
0.33/-LF
Cs
1/-LF
1-397
XR·9201
8-Bit Microprocessor Compatible
Digital-lo-Analog Converter
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-9201 is a monolithic 8-Bit ,.,p compatible digitalto-analog converter with differential current outputs. It
contains an internal data latch, making it suitable for interfacing with microprocessors. The chip contains a
stable voltage reference (2.0 V Nominal) which is externally adjustable and can be used as a reference for other D/A and AID converters.
The XR-9201 features non-linearity of ± V. LSB maximum (± .19% of full scale current). The internal voltage reference maintains a temperature coefficient of
50 ppm/oC.
-Vee
+Vcc
VAEF
DB?
TRIM
DB6
-VREf IN
DB5
+VREf IN
084
10
083
10
DB.
CE
DBl
GROUND
DBO
FEATURES
8-Bit Resolution
Input Data Latches
Internal Voltage Reference
Microprocessor Compatible
Non Linearity
Full Scale Current Stability
Reference Voltage Stability
Differential Current Outputs
TIL Compatible
± V. LSB Maximum
±50 ppm/oC
±50 ppm/oC
ORDERING INFORMATION
Part Number
Package
XR-9201 CP
Plastic
Operating Temperature
0° to
+ 70°C
SYSTEM DESCRIPTION
APPLICATIONS
To convert the output currents of the digital-to-analog
converter to a voltage, an operational amplifier can be
used as shown in Figure 12.
Bipolar and Unipolar D/A Conversion
AID Conversion
Test Equipment
Measuring Instruments
Programmable Current Source
Programmable Voltage Source
Care must be taken in selecting an operational amplifier to be used in D/A conversion. For accurate conversion, the operational amplifier should have low input
offset voltage, low input bias and offset currents, and
fast settling times. Input offset voltage contributes a
DC error on the output and should be properly nulled.
Input bias current contributes to the D/A converter current flowing through the feedback reSistor, RFB, and also causes a DC error on the output voltage. This error
can be reduced by the addition of a resistor equal in
value to RFB from the noninverting input to ground.
Settling time is important because it rules how fast the
output reaches its prescribed voltage level. The OP-01
is suitable for D/A converter applications producing
negligible errors.
ABSOLUTE MAXIMUM RATINGS
+ VCC
Positive Supply Voltage
- VCC Negative Supply Voltage
Logic Input Voltages
Power Dissipation
Derate Above 25°C
Storage Temperature
+6V
-8.5V
o to +6V
500mW
5 mW/oC
-55°C to + 150°C
1-398
XR·9201
ELECTRICAL CHARACTERISTICS
Test Conditions: VCC
=
SYMBOL
PARAMETERS
+ 5V, - VCC
= - 7V, TA = 25°C,
IREF
=
1.0 mA, unless otherwise specified.
MIN
TYP
MAX
UNIT
Resolution
8
8
8
Bits
Monotonicity
8
8
Non-linearity
+VCC
Positive Supply
Voltage
-VCC
Negative Supply
Voltage
8
Bits
±0.5
±0.19
LSB
%IFS
4.5
5.0
5.5
V
-7.7
-7.0
-6.3
V
VIH
Data Input and Chip Enable
"High" Voltage
VIL
Data Input and Chip Enable
"Low" Voltage
0.8
V
IIH
Data Input and Chip Enable
"High" Current
500
p.A
IlL
Data Input and Chip Enable
"Low" Current
±20
p.A
2.070
mA
±10
p.A
IFS
Full Scale Output Current
IZO
Zero Scale Output Current
TCIFS
Full Scale Current
Temperature Sensitivity
IFSS
Full Scale Symmetry
VREF
Internal Reference Voltage
2.0
1.914
V
1.992
ppm/oC
±50
±10
2.005
+ ICC
±50
Positive Supply Current
Negative Supply Current
15
-25
25
RADJ
RADJ
RADJ
ppm/oC
VREF
mA
-15
mA
Positive Output
Voltage Compliance
+5.0
V
Negative Output
Voltage Compliance
-1.0
V
3
mA
Settling Time
600
nsec
Data Set-up Time
170
nsec
tH
Data Hold Time
40
nsec
tw
Minimum Chip Enable (CE)
Pulse Width
170
nsec
tD
Propagation Delay Time
500
nsec
-ICC
Maximum Full Scale
Current
ts
tsu
1-399
= 1.000 mA
O·C :S TA :S 75°C
V
2.000
TCREF
IREF
p.A
1.990
VREF Temperature Stability
CONDITIONS
= 50 KO
= 00
= 60
= 2.00 V
XR·9201
.,
..
II
..
.,
.,
II
.
c•
--1
,,
:
TAiM
11'i}-+--\-----4
G~ r.nr+--~------J
-VAEFIN
• ......' -_ _ _ _~:..'"
L____ ___ __ __ ________ ___ ___ ___ _________________________________________________ _
IIR·tZ01
Figure 2. Functional Block Diagram
,
-Vee
Figure 3A. Equivalent Circuit of Data Latches and Current Switches
1-400
XR·9201
3
TRIM
2
YAEF
•
-YREF IN
+VREF IN
~----~----~----~---4~---O-Vee
XR·9201
Figure 3B. Equivalent Circuit 01 Voltage Reference and Input Amplifier
2~~----------~~~--~
ATRIM'" 6 KH
-Vee'" -7.0 Y
i
------,
r
------DATA
1.4 V
ill
a:
'------------
I.'
>
CHIP
ENABLE
'~'--~--~--~--~--~"~~'~2--~~~~~~~~~
CURRENT OUT ON VREF (PIN 2) mA
Figure 5. VREF VS. Current Output
OUTPUT
2.0
-O-.T-.-----..." r - - - - - --
iii
....
....
1.4 Y
..'"
0
c:.
a:
>
1.4 Y
RTRIM = 6 Kil
1.0
-Vee = -7.0 V
(STAYS IN OnlGINAl STATE)
OUTPUT
+Vee (VOLTS)
Figure 4. Timing Diagram
Figure 6. VREF VS. + VCC
H01
XR·9201
DEFINITIONS OF SWITCHING PARAMETERS
Settling Time (t s):
Time required for output to reach
its final value (to within ± .19 % of
full scale output) after data is applied to the inputs. Chip enable,
CE, is held "high."
Data Set-Up Time (t su ): Minimum time required for
data to be present at the inputs
while CE is "high", in order to obtain valid output data. It is measured from when proper data is
applied to the inputs to when CE
goes "low".
Data Hole Time (th): Maximum time required for data to
be present at the inputs before CE
goes "low", in order to obtain valid
output data. It is measured from
when the input data changes state
to when CE goes "low", and still
obtain valid output data of the previous input state. Data hold time
indicates that the input data does
not have to be present during the
latter part of the CE high state, and
still have valid output data.
Chip Enable Pulse Width (tw): Minimum pulse width
required for chip enable signal in
order to obtain valid output data.
Propagation Delay Time (tdl: Time required for output
to reach its final value (50%) after
CE is applied. It is measured from
the falling edge of the CE pulse to
50% of the output pulse under
minimum data set-up time conditions.
DESCRIPTION OF PIN CONTROLS
VREF (PIN 2):
Internal voltage reference output provides +2.00 V Nominal voltage. Can
be used as reference voltage for other circuitry. Maximum output current
c~ability is approximately 9 mA with
V = 5.0 V.
TRIM (PIN 3):
VREF can be adjusted by connecting
a 10 KO potentiometer between the
trim pin and ground. Temperature stability is optimized for VREF = 2.00 V
to 10-50 ppm/DC.
the D/A converter. Either the internal
VREF (Pin 2) or an external VREF can
be connected to this pin. IREF is approximately equal to VREF/R. Maximum value for IREF is about 1.5 mA
before internal saturation occurs.
- VREF IN (PIN 4): This pin is tied to ground through
a resistor, R, equal in value to that of
Pin 5 and VREF
+ VREF IN (PIN 5): Reference voltage is connected
+Vcc
-Vee
.
~
Complement output current.
10 (PIN ?):
Output current. The sum of To and 10
is always equal to the full scale output
current (IFS).
CE (PIN 8):
Chip enable pin controls the input data into the internal data latch. The
latch is transparent in the "high"
state.
DBO-DB? (PIN 10-17): Data input pins. DBO corresponds to the LSB. DB? corresponds
to the MSB.
to this pin using a resistor, R, to provide the reference current, IREF' for
~ 2.010
To (PIN 6):
+Vcc =5,011
-Vee = -7.0 V
'REF = 1.000 mA
= 5.0 V
= -7.0 V
RTRIM = 6 KII
~ 2.000
>
1.990
-25 C
0 C
2S'C
SO"C
1.996_I::,=-.-~--:',.~-.L..o--7"".--..-...'00-----
75 v C
AMBIENT TEMPERATURE ( C)
AMBIENT TEMPERATURE ('Cl
Figure 7. VREF VS. Temperature
Figure 8. IFS VS. Temperature
1-402
XR·9201
PRINCIPLES OF OPERATION
Figure 10 shows the basic configuration of the XR-9201
D/A converter. The input data bits to the chip can be
latched (stored) in the D/A by controlling the chip enable (CE) pin. When CE is "high" (>2.0 volts), the latch
is transparent and data bits present are passed
through the latch and directly control the D/A converter
switches. When CE is "low" « 0.8 volts), the data bits
within the latch are retained and remain there until CE
goes "high" again. When CE is "low", the data bits at
the inputs are ignored until CE goes "high". This interval latch provides a useful interface with microprocessors.
1.0
+Vcc = 5.0 V
-Vee = -7.0 V
0.1
_ _ _----:--'-:-_ _ _--:-'::--_ ______
The output currents, 10 and To, are related to IREF as
follows:
0.01
'0 =
Figure 9. IFS vs. IREF
'--~'-----.L...""""
0.001
0.10
1.00
'REF (mA)
b7
2 'REF [ 2
bs
bs
b4
b3
b2
b1
4
8
16
32
64
128
+- +- +- +- +- +-
bO]
+-
256
CE
8·BIT DATA
+5 Y
Where: bn = 1 if Bit N is "High"
= 0 if Bit N is "Low"
b7 = MSB (Pin 17)
bO = LSB (Pin 10)
To is the complement current output of 10 . For all possible input data combinations,
'REF
10 + To = IFS = full scale output current.
where 'FS = 2 'REF
I
2
I
8
~------oio
• 1
~-;r--T-----"
(~~~)
10 KII
The XR-9201 D/A converter contains an internal reference voltage (VREF) with nominal value of 2.00V using
a 6 KO resistor to ground. VREF can be adjusted using
a 10 KO potentiometer tied between Pin 3 and ground.
For maximum temperature stability, VREF should be
set to 2.00V. The maximum output current capability of
VREF is about 9 mA (see Figure 5) and can be used to
provide a reference voltage for other DACs, as well as
other circuitry.
-7V
ATRIM
~
Figure 10. Basic Configuration
board layout. Specifically, connection between the current output terminals, 10 and To, and the operational
amplifier inputs needs to be as short as possible so as
to minimize capacitance at the node. Oscillations on
the operational amplifier output may result with long
wires. A capaCitor in the feedback loop of the operational amplifier can reduce these oscillations.
The reference current (lREF) for the D/A converter is
established by a resistor, R, connected between VREF
and Pin 5 (+ VREF IN), or between an external reference source and Pin 5, and is approximately given as:
ZERO AND FULL SCALE ADJUSTMENTS
Figure 13 shows a circuit for zero and full scale adjustments. It allows the output voltage to be nulled with
zero scale input conditions (0000,0000). This is done by
shorting out RFB and adjusting the vas adjust potentiometer of the operational amplifier until the output
reads zero volts. This is performed with all digital bits
set to zeros. Iflo is the output being used, then all digital bits are set to ones and the zero scale is adjusted.
VREF
IREF = - R
For IREF :s; 1 mAo The maximum IREF allowed is about
1.5 mA beyond which saturation occurs in the internal
circuitry. To balance the internal operational amplifier, a
resistor equal to R must be placed between Pin 4
(- VREF IN) and ground.
For full scale adjustment, all digital inputs are set to
ones and the IREF potentiometer, from Pin 2 to Pin 5, is
adjusted until the output is at the desired voltage level
(e.g., output is adjusted to 10.000 volts for nominal
9.960 volts output).
NOTE:
When operating the XR-9201 D/A converter with an operational amplifier, care must be taken with the PC
1-403
XR·9201
+5V
+ycc
+VREF
..J1JL
11
II 4
(MSB}
..
5
SN
74'93
11
6
7
8
9
10
'ERROR
RF
11
15
10
4-BIT
t COUNTER 1
14
I
13
12
LSB
"::'
lOUT'
CE
10K
+ Vee
MSB
-=-
-1SV
II 4
17 16 15 14 13 12 11
11
15
SN
14183
10
"
XR·9201
10
4-BIT
COUNTER
SKU
-=
5 KU
-Vec
10 KII
Yo = RF ('ERROR)
AF;II 10 Kti
CF
>=
.01
~F
Figure 11. Relative Accuracy Test Circuit
'REF"
lonA
!
EO
2 YREF
& KII
EO
XR-9201
3KU
R
10
FULL
10
SCALE
ADJUST
oy· EO' 10YFORAFB=5KU,IREF=1mA
'FS = Z(IREFI (25512561
FOR OPERATION WITH NEGATIVE LOGIC D/A CONVERSION, I.E. ZERO FULL SCALE
(0000 0000) CORRESPONDING TO FULL SCALE OUTPUT, CONNECT THE INVERTlNG
INPUT OF OP AMP TO 10 (P'" I) AND CONNECT to (PIN 7) TO GROUND.
Figure 13. Full Scale and Zero Scale Adjustment
Figure 12. Digltal-to-Analog Conversion: Unipolar Operation
Table 1. Unipolar Operation - Input/Output Relationship
Positive Full Scale
B7
B6
B5
B4
B3
B2
B1
Bo
10 (rnA)
EO (V)
1
1
1
1
1
1
1
1
1.992
9.960
9.922
Pos. Full Scale
-
LSB
1
1
1
1
1
1
1
0
1.984
Pos. Full Scale
-
MSB
0
1
1
1
1
1
1
1
0.992
4.961
Zero Full Scale
+
LSB
0
0
0
0
0
0
0
1
0.008
0.039
1-404
XR·9201
Table 2. Bipolar Operation: Input/Output Relationship
B7
B6
B5
B4
B3
B2
B1
Bo
E1 (V)
Full Scale Output
1
1
1
1
1
1
1
1
0.000
10.00
Full Scale - LSB
1
1
1
1
1
1
1
0
0.016
9.921
Zero Scale + MSB
1
0
0
0
0
0
0
0
1.984
0.078
Full Scale - MSB
0
1
1
1
1
1
1
1
2.000
0.000
Zero Scale + LSB
0
0
0
0
0
0
0
1
3.968
-9.844
Zero Scale
0
0
0
0
0
0
0
0
3.984
-9.922
.001
BIPOLAR OUTPUT OPERATION
~F
~
Figure 14 shows a basic bipolar output operation. For
full scale input (1111,1111) the output voltage is equal
to 1.0y' For zero scale input (0000,0000), output voltage
is equal to - 1.0V. Due to the internal circuitry of the
XR-9201, the current output terminals should not be
pulled below approximately -1.0 volt. Therefore the circuit shown in Figure 14 would not function for Eo less
than -1.0y' For bipolar operation with larger output
voltages, the circuit shown in Figure 15 is recommended. Note that the current outputs, 10 and 10 , are
held at zero volts for all digital inputs for greater accuracy.
ED (V)
E·7~F=!:+5 V
+VIN
o----<>-t,.
·A .---:.,.:-----"""IR-9201
XR-4194
.001 ",F
AO = 17.5 KlI
ADJUST RO FOR - YOUT '" -7 V
~VtN
:!"10V
RAo =SOKU
ADJUST RIl FOR +YOUT .. +5 y
Figure 15. Dlgltal-to-Analog Conversion - Bipolar Operation
8-BITDATA
1-81T DATA
VREF
0,
IROF =
0.5 mAo
1
---.
1 mA
~~------'
IREF
-1.0 V' EO' 1.0 V
IE: 2(IREF) fAF)' 1.0 VOLT
Figure 14. Digital-to-Analog Conversion - Bipolar Operation
VAEF .2 Y, R = 2 K. RFB ... 2 K, R2 '" 50 K, A, • 10 K
NOTE: (I
+ IREF) MUST BE LESS THAN 6 mA FOR PROPER OPERATION.
Figure 16. Regulated Supplies for XR-9201
1-405
XR·4151
VOltage-to-Frequency Converter
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-4151 is a device designed to provide a simple,
low-cost method for converting a DC voltage into a proportional pulse repetition frequency. It is also capable
of converting an input frequency into a proportional
output voltage. The XR-4151 is useful in a wide range of
applications including AID and D/A conversion and data transmission.
CURRENT
SOURCE OUTPUT
FEATURES
Single Supply Operation (- 8V to + 22V)
Pulse Output Compatible With All Logic Forms
Programmable Scale Factor (K)
Linearity ± 0.05 % Typical-Precision Mode
Temperature Stability ± 100% ppm/oC Typical
High Noise Rejection
Inherent Monotonicity
Easily Transmittable Output
Simple Full Scale Trim
Single-Ended Input, Referenced to Ground
Also Provides Frequency-to-Voltage Conversion
Direct Replacement for RC/RV/RM-4151
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-4151P
XR-4151CP
Plastic
Plastic
-40°C to +85°C
O°C to + 70°C
APPLICATIONS
Voltage-to-Frequency Conversion
AID and D/A Conversion
Data Transmission
Frequency-to-Voltage Conversion
Transducer Interface
System Isolation
SYSTEM DESCRIPTION
The XR-4151 is a precision voltage to frequency convertor featuring 0.05% conversion linearity, high noise
rejection, monotonicity, and single supply operation
from 8V to 22V. An RC network on Pin 5 sets the maximum full scale frequency. Input voltage on Pin 7 is
compared with the voltage on Pin 6 (which is generally
controlled by the current source output, Pin 1). Frequency output is proportioned to the voltage on Pin 7.
The current source is controlled by the resistance on
Pin 2 (nominally 14kO) with 1 = 1.9 VIR. The output is
an open collector at Pin 3.
ABSOLUTE MAXIMUM RATINGS
Power Supply
Output Sink Current
Internal Power Dissipation
Input Voltage
Output Short Circuit to Ground
22V
20 mA
500 mW
- 0.2V to + Vee
Continuous
1-406
XR·4151
ELECTRICAL CHARACTERISTICS
Tast Conditions: (VCC = 15V, TA =
+ 25°C,
unless otherwise specified)
MIN
LIMITS
TYP
MAX
UNITS
CONDITIONS
2.0
2.0
3.5
4.5
6.0
7.5
mA
mA
8V VI. When this condition is achieved,
the current source remains off and the voltage VB decays until VB is again equal to VI. This completes one
cycle. The VFC will now run in a steady state mode. The
current source dumps lumps of charge into the capacitor CB at a rate fast enough to keep VB 2:: VI. Since the
discharge rate of capacitor CB is proportional to VB'
RB, the frequency at which the system runs will be proportional to the input voltage.
SINGLE SUPPLY MODE VOLTAGE-TO-FREQUENCY CONVERTER
In this application, the XR-4151 functions as a standalone voltage-to-frequency converter operating on a
single positive power supply. Refer to the functional
block diagram and Figure 3, the circuit connection for
single supply voltage-to-frequency conversion. The XR4151 contains a voltage comparator, a one-shot, and a
precision switched current source. The voltage comparator compares a positive input voltage applied at pin
7 to the voltage at pin 6. If the input voltage is higher,
the comparator will fire the one-shot. The output of the
one-shot is connected to both the logic output and the
precision switched current source. During the one-shot
period, T, the logic output will go low and the current
source will turn on with current I. At the end of the one
shot period the logic output will go high and the current
source will shut off. At this time the current source has
injected an amount of charge Q = lOT into the network
RB-CB. If this charge has not increased the voltage VB
such that VB > VI, the comparator again fires the oneshot and the current source injects another lump of
••
......
ro Lf'L..J
'-I t--
to-"VI,WHEftEIC-o." ::ftoCO
Figura 3. VOltaga-to-Fraquancy Convartar
1-407
~
XR·4151
op-amp prevents the voltage at pin 7 of the XR-4151
from going below O. Use a low-leakage diode here,
since any leakage will degrade the accuracy. This circuit can be operated from a single positive supply if an
XR-3403 ground-sensing op-amp is used for the integrator. In this case, the diode can be left out. Note that
even though the circuit itself will operate from a single
supply, the input voltage is necessarily negative. For
operation above 10kHz, bypass pin 6 of the XR-4151
with .01/,F.
TYPICAL APPLICATIONS
SINGLE SUPPLY VOLTAGE-TO-FREQUENCY CONVERTER
Figure 3 shows the simplest type of VFC that can be
made with the XR-4151. The input voltage range is from
o to + 10V and the output frequency is from 0 to 10
kHz. The f~1I scale frequency can be tuned by adjusting
RS, the output current set resistor.. This circui~ has the
advantage of being simple and low In cost, but It suff~rs
from inaccuracy due to a number of error sources. Linearity error is typically 1 %. A frequency offset will also
be introduced by the input comparator offset voltage.
Also, response time for this circuit is limited by the passive integration network RB CB. For the component values shown in Figure 3, response time for a step change
input from 0 to + 1OV will be 135 msec. For applications
which require fast response time and high accuracy,
use the circuit of Figure 4.
FREQUENCY-TO-VOLTAGE CONVERSION
The XR-4151 can be used as a frequency-to-voltage
converter. Figure 5 shows the single-supply FVC configuration. With no signal applied, the resistor bias networks tied to pins 6 and 7 hold the input comparator in
the off state. A negative going pulse applied to pin 6 (or
positive pulse to pin 7) will cause the comparator to fire
the one-shot. For proper operation, the pulse width
must be less than the period of the one-shot, T = 1.1
RO CO. For a 5V pop square-wave input the differentiator network formed by the input coupling capacitor and
the resistor bias network will provide pulses which correctly trigger the one-shot. An external voltage comparator can be used to "square-up" sinusoidal input signals before they are applied to the XR-4151. Also, the
component values for the input signal differentiator and
bias network can be altered to accommodate square
waves with different amplitudes and frequencies. The
passive integrator network RB CB filters the current
pulses from the pin 1 output. For less output ripple, increase the value of CB.
PRECISION VOLTAGE-TO-FREQUENCY CONVERTER
In this application (Figure 4) the XR-4151 is used with
an operational amplifier integrator to provide typical linearity of 0.05% over the range of 0 to -10~. Offse~ is
adjustable to zero. Unlike many VFC designs which
lose linearity below 10mV, this circuit retains linearity
over the full range of input voltage, all the way to Ov.
Trim the full scale adjust pot at VI = - 1OV for an output
frequency of 10kHz. The offset adjust pot should be set
for 10Hz with an input voltage of - 10mV.
The operational amplifier integrator improves linearity
of this circuit over that of Figure 3 by holding the output
of the source, Pin 1, at a 90nstant OV. Therefore, the linearity error due to the current source output conductance is eliminated. The diode connected around the
For increased accuracy and linearity, use an operational arnplifier integrator as shown in Figure 6, the precision FVC configuration. Trim the offset to give -10mV
out with 10Hz in and trim the full scale adjust for -1 OV
out with 10kHz in. Input signal conditioning for this circuit is necessary just as for the single supply mode and
the scale factor can be programmed by the choice of
component values. A tradeoff exists between the
amount of output ripple and the response time, through
the choice or integration capacitor CI. If CI = 0.1 /,f the
ripple will be about 100mV. Response time constant 'TR
= RB CI. For RB = 100 kll and CI = 0.1 /,f, 'TR
10msec.
.,
.-.
,Nfl,
,.....
·1
1GOlen
RIa
'OO'Ulv.~y.
Yo VOLTAGE OUTPUT
FREQUENCY INPUT
T010V
L.nJ"L
'5 V," SOUAAEWAYI
lDOKn
'001,
"
1.022,.,
v.
y •• ,1V
18K1I
&.1ICn
XA-4111
ROI.IKII
10Ku
Figure 4. Precision VOltage-to-Frequency Converter
Figure 5. Frequency-to-Voltage Converter
1-408
10KII
~
.....
XR·4151
PRECAUTIONS
2. SetT = 1.1 ROCO = 0.75[1/fo]wherefoisthede·
sired full scale frequency. For optimum performance
make 6.8kO >RO >680kO and O.OOl"f ~_.",..---<
Alternately, the op-amp inverting input (summing
node) can be used as a current input with the full
scale input current 110 = -100,.A.
Vo
VOLTAGEOUTJIUT
-1OY~ VO" 0
5. For the FVC's, pick the value of Cs or CI to give the
optimum tradeoff between the response time and
output ripple for the particular application.
DESIGN EXAMPLE
I. Design a precision VFC (from Figure 5) with fo =
100kHz and VIO = -lOY.
t. Set RS = 14.0kO
2. T = 0.75 [\110 5] = 7.5"sec
Let RO
= 6.8kO and Co = 0.001 "f.
3. CI = 5 x 105 [1/10 5 ] = 500pf.
Figure 6. Precision Frequency-to-Voltage Converter
Op-amp slew rate must be at least
SR
=
135 x 106 [1/500pf]
= 0.27V/!,sec
4. RS = 10V/l00"A = 100kO.
PROGRAMMING THE XR-4151
II. Design a precision VFC with fo
10V.
The XR-4151 can be programmed to operate with a full
scale frequency anywhere from 1.0Hz to 100kHz. In the
case of the VFC configuration, nearly any full scale input voltage from 1.0V and up can be tolerated if proper
scaling is employed. Here is how to determine component values for any desired full scale frequency.
= 1Hz and VIO =
1. Let RS = 14.0kQ
2. T
= 0.75 [1/1] = 0.75 sec
Let RO = 680kO and Co = 1.0"f.
3. CI = 5 x 10- 5 [1I1]F = 50!,1.
1. Set RS = 14kO or use a 12k resistor and 5k pot as
shown in the figures. (The only exception to this is
Figure 4.)
4. RS = 100kQ.
1·409
XR·4151
III. Design a single supply FVC to operate with a supply
voltage of 9V and full scale input frequency fo =
83.3 Hz. The output voltage must reach at least
0.63 of its final value in 200msec. Determine the
outPUt ripple.
4. RB
= 5V/100pA = 50kO.
.5. Output response time constant is TR :s; 200
msec
Therefore-
= (200
1. Set RS = 14.0kO
CB :s; TR/RB
2. T = 0.75 [1/83.3] = 9msec
Worst case ripple voltage is
Let RO = 82kO and Co = 0.1 /Lf.
x 10 - 3)/(50 x 103)
VR = (9mS x 135/LA) I 4/Lf = 304mV.
3. Since this FVC must operate from 8.0V, we shall
make the full scale output voltage at pin 6 equal
to 5.0V.
@
EQUIVALENT SCHEMATIC DIAGRAM
1-410
= 4/Lf
XR·7000
ADVANCE INFORMATION
Log Video Amplifier
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-7000 is a universal logarithmic video amplifier
chip. Because of its extremely wide bandwidth, it can
be used in systems ranging from audio applications to
radar subsystems. The XR-7000 utilizes seven separate
precision logarithmic elements. These elements may
be used separately for small dynamic ranges or cascaded to offer an extremely wide dynamic range of operation.
The XR-7000 has an internal band-gap voltage reference, a differential video summing amplifier, and a precision die temperature sensor, to aid in its system interfacing. Also included are internal power supply regulators to provide excellent power supply rejection.
The XR-7000 is available in a 40-Pin ceramic or plastic
package. It is designed to operate from dual 11 to 15
volt power supplies
FEATURES
Seven Uncommitted Logging Elements
Internal Band-Gap Voltage Reference
Dual Tracking Regulators On-Board
Precision Die Temperature Sensor
APPLICATIONS
ORDERING INFORMATION
Receiver Subsystems
Radar Subsystems
Spectrum Analyzers
Power Meters
Test Equipment
Video Cartridge Tape Recorders
Audio Tape Recorders
Smoke Detectors
Chemical Process Systems
Ultrasonic Imaging
Medical Equipment (Tomography)
Part Number
Package
Operating Temperature
XR-7000M
XR-7000CP
Ceramic
Plastic
- 55°C to + 125°C
O°C to + 70°C
SYSTEM DESCRIPTION
30V
1.0W
5 mW/oC
The main section of the XR-7000 comprises seven logarithmic sections. Each section has a dynamic range of
approximately 12 dBV. For wide range applications, the
seven sections may be cascaded to provide a total dynamic range of over 90 dBV. The logarithmic sections
provide current outputs, which can be summed and
converted to voltages, using the on-board summing
amplifiers. A unipolar output with built-in offset is also
available for use with an external I to V converter.
-55°C to + 125°C
O°C to + 70°C
VCC + .5V to VEE - .5V
The precision die temperature sensor is useful in dccoupled applications to provide stability over its temperature range.
ABSOLUTE MAXIMUM RATINGS
Power Supply
Power Dissipation
Derate Above at 25°C
Operating Temperature
Ceramic
Plastic
Any Input Voltage
1-411
XR·7000
ELECTRICAL CHARACTERISTICS
= + 12V, VEE + -12V, TAMB = 25°C, dual polarity output load resistances
100 ohms, unipolar internal load resistance = 200 ohms, unless specified otherwise.
Test Conditions: With VCC
=
SYMBOL
PARAMETERS
MIN
TYP
MAX
UNIT
Vcc
Vee
Icc
lee
+Vout
Positive Supply Voltage
Positive Supply Voltage
Positive Supply Current
Negative Supply Current
Positive Regulator
Output Voltage
Negative Regulator
Output Voltage
11
11
12
12
15
15
15
15
V
V
mA
mA
5.8
6.0
6.2
V
Reference Untrimmed
-5.8
-6.0
-6.2
V
Reference Untrimmed
dB
Dual Polarity Output
1000 Dill. Load
10% Points
-Vout
CONDITIONS
LOG SECTION
LG
BW
Tr
Tpd
Trec
lin
PSRR
VTRAC
Ttcv
Vout
Vout
Rout
Nout
Log Range per Element
Bandwidth
Risetime
Prop. Delay
Saturation Recovery
Input Bias Current
Power Supply Rejection
Ratio
Tracking of Regulators
Output Tempco
Output Voltage
per Stage
Output Voltage
per Stage
Unipolar Output
ReSistance
Output Noise
14
6
60
150
12
30
12
10
20
2
65
MHz
25
12
ns
ns
ns
p.A
dBV
DC to 100 MHz
20
50
118
ppm
ppm
mV
Trimmed
Unipolar
120
mV
Bipolar each Output
200
100
1-412
250
ohms
p.Vrms
Unipolar connection
XR·2216
Monolithic Compandor
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-2216 is a monolithic audio frequency compandor designed to compress or expand the dynamic
range of speech or other analog signals transmitted
through telecommunication systems. The monolithic
circuit can be connected as either a compressor or an
expander, the choice being determined by the external
circuitry.
AMPLIFIER
COMPENSA nON
AMPLIFIER
OUTPUT
REFERENCE
AMPLIFIER
NON· INVERTING
INPUT
LEVEL
SCALE SET
R,'
Fil TER
LOW LEVEL
TRACKING
TRIM
FEATURES
Functions as either a Compressor or an Expander
Wide Dynamic Range: 60 dB
Wide Supply Range: 6 to 20 Volts
Excellent Transfer Function Tracking
Low Power Supply Drain
Controlled Attack and Release Times
Low Noise and Low Distortion
AC/DC
CONVERTER
INPUT
EXPANDER
INPUT
ORDERING INFORMATION
APPLICATIONS
Telephone Trunk-Line Compandor
Speech/Data Compression and Expansion
Telecommunication Systems
Mobile Communications
Model Data Processing
Part Number
Package
(16 Pin DIP)
XR-2216CN
XR-2216CP
Ceramic
Plastic
Operating Temperature
- 40°C to + 60°C
- 40°C to + 60°C
SYSTEM DESCRIPTION
20V
The XR-2216 is comprised of four basic blocks: (1) an
internal voltage reference; (2) an AC/DC converter
which converts AC Signal input to a DC current level;
(3) an impedance converter whose impedance level is
a function of a DC control signal; and (4) a high gain operational amplifier.
750 mW
6 mW/oC
625 mW
5 mW/oC
- 60°C to + 150°C
The XR-2216 is deSigned to accommodate a wide
range of system configurations. It can be operated with
positive or negative single supply systems, or dual
power supplies over a power supply range of 6 volts to
20 volts.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Power Dissipation
Ceramic Package
Derate above +25°C
Plastic Package
Derate above + 25°C
Storage Temperature
1-413
XR·2216
ELECTRICAL CHARACTERISTICS
Test CondHlons: Vc
= + 12V, TA = 25°C
COMPANOOR
PARAMETERS
MIN
TVP
MAX
UNITS
Power Supply Voltage
6
20
VDC
Nominal Power Supply Voltage
12
18
VDC
3
rnA
+1
dB
Power Supply Current, No Signal Input
Gain Change Over Frequency Tolerance
-1
Distortion Measured at - 4 dB·
Input Level at 1 KHz
Attack Time Measured at - 10 dB
Input Level
Transfer Characteristics··
Compandor Output With Input Levels of:
-4 dB
-8dB
-10dB
- 14 dB (reference)
-24 dB
-34 dB
-44 dB
-54 dB
-64 dB
3.5
-0.5
-1.5
300 - 3500 Hz
% THD
3
Decay Time Measured at -10 dB
Input Level
CONDITIONS
5
ms
To 90% of Final Value
5
ms
To 10% of Final Value
7.5
3.5
+1.5
-15.5
-25.5
-36.5
-49
-59
+6
+2
0
-4
-14
-24
-34
-44
-54
-12.5
-22.5
-32.5
-42.5
-52.5
dB
dB
dB
dB
dB
dB
dB
dB
dB
MIN
TVP
MAX
UNITS
COMPRESSOR
PARAMETERS
Input Impedance
50
Output Impedance
50
Output Signal Level for - 10 dB
Input at 1 KHz
Output Voltage Swing
-10
ohm
dB
dB
0
Output Noise, Input AC Grounded
30
Compressor Transfer Characteristics··
Compressor Output With Input Levels of:
-4 dB
-8 dB
-10 dB
- 14 dB(reference)
-24 dB
-34 dB
-44 dB
-54 dB
-64 dB
CONDITIONS
Kohm
-7
dBrnc
dB
dB
dB
dB
dB
dB
dB
dB
dB
-9
-10
-12
-17
-22
-27
-32
-37
EXPANDER
PARAMETERS
Input Impedance
MIN
TVP
50
dB
+8
Output Noise Input AC Grounded
Notes: ·0 dB = 0.775 Vrms (1 mW across 600 ohm load)
ohm
dB
0
Expender Transfer Characteristics··
Expander Input Levels Required for
Output of:
+6dB
+2dB
OdB
- 4 dB(reference)
-14 dB
-24 dB
-34 dB
-44 dB
-55 dB
UNITS
Kohm
Output Impedance
Output Signal level for - 10 dB
Output Voltage Swing
MAX
50
+5
-7
-9
-10
-12
-17
-22
-27
-32
-37
dBrnc
dB
dB
dB
dB
dB
dB
dB
dB
dB
"Recommended transfer characteristics.
1-414
CONDITIONS
XR·2216
EQUIVALENT SCHEMATIC DIAGRAM
9
CIRCUIT DESCRIPTION
The analog signal compressor/expander or "compandor" circuits are among the most fundamental building
blocks in telecommunication systems. These circuits
are intended to compress or expand the dynamic range
of speech or other analog signals transmitted through
telecommunication systems.
system is comprised of four basic blocks: (1) an internal
voltage reference; (2) an ac/dc converter which converts ac signal input to a dc current level; (3) an impedance converter whose impedance level is a function of
a dc control signal; and (4) a high gain operational amplifier.
Figure 1 shows the simplified block diagram of a typical
speech transmission system, using the compression/
expansion or "companding" technique. The dynamic
range of the input signal is first compressed at the
transmitting end; then transmitted through the system,
and finally expanded back to the original amplitude at
the receiving end. Thus, the "compressor" and the "expander" sections of a compandor system perform reciprocal functions. In a bi-directional transmission system, there is a compandor at each end of the line which
compresses the out-going signal, or expands the incoming signal by an equal amount.
The XR-2216 is designed to accommodate a wide
range of system configurations It can be operated with
positive, or negative, single-supply systems, or with balanced power supplies, over a power supply range of
6 volts to 20 volts.
Some of its key features are: low external component
count, excellent transfer function, tracking, low power
supply drain, controlled attack and release times, low
noise and low distortion.
EXPANDER (Figure 3)
Figure 3 shows the external circuit connections and
components necessary to operate XR-2216 as an expander. An input signal is applied to Pin 7 which is the
Figure 2 shows the typical transfer characteristics of
compressor and expander circuits commonly used in
telecommunication systems. In the compressor, the
output amplitude varies 1 dB for every 2 dB change of
input amplitude; the reverse is true for the expander.
AC/DC converter input. The AC/DC converter converts
the AC signal input to a dc current level which in turn
controls the transconductance of the impedance converter. Part of the input signal is applied to the impedance converter by connecting Pins 8 and 10. Thus the
signal current at Pin 11 is proportional to the product of
the input signal and its average value.
The functional block diagram of XR-2216 compandor is
shown on Page 1, in terms of the monolithic circuit
package. The XR-2216 is designed to be connected as
either a compressor or an expander, the choice being
determined by the external circuitry. The monolithic
tNT
1
6
°o
SIGNAL
COMPRESSOR
TRANSMISSION
SYSTEM
SIGNAL
EXPANDOR
n
Figure 1. Simplified Block Diagram of a Speech Transmission System Using Companding Technique
1-415
XR·2216
The output signal current is then fed to the operational
amplifier by connecting Pins 11 and 16, and the output
signal voltage is directly proportional to the signal current flowing into Pin 16. The output signal of the expander is available at Pin 2. In this operation, the reference level is set by the trim pot R1, and the trim pot R2
provides a means for trimming low level tracking.
J/
-,0
-20
COMPRE?
-30
In the connection of Figure 3, the input signals of - 37
dBm to - 7 dBm are expanded to 60 dB output range
with up to a dBm power matched output to 600n load.
/'
I
-50
-60
-80 -70 -60 -50 -40
Figure 4 shows the typical circuit connection for compressor operation. It is just a non-inverting voltage amplifier whose input level is proportional to the product of
the incoming signal and the impedance of the impedance converter which is inversely proportional to the
amplifier output. Consequently, the output signal at Pin
2 is proportional to square root of the input signal.
tf
I
V
,-V
-40
COMPRESSOR (Figure 4)
V
I
ElxPANiER
-30
-20
-,0
0
INPUT (dBm)
Figure 2. Transfer Characteristics of Compressor 2
Expander Circuits
EXPANDER
OUTPUT
In this operation, just like expander operation, the reference level is set by the trim pot R1 and low level tracking is adjusted by the trim pot R2. In the connection of
Figure 4, the output change is 1 dB for 2 dB change at
input. The output range can be adjusted to - 37 dBm to
- 7 dBm for input signals of 60 dB dynamic range.
Note: Attack and Decay Times:
The speed with which gain changes to follow changes
in input signal levels is determined by the capacitor C1
and the resistor R1. A small capaCitor will yield rapid response but will not fully filter low frequency signals. Any
ripple on the gain control signal will modulate the signal
passing through the impedance converter. In an expander and compressor application, this would lead to
a 3rd harmonic distortion, so there is a tradeoff to be
made between fast attack and decay times, and distortion.
Figura 3. External Connections for Oparation Expander
COMPRESSOR
OUTPUT
TYPICAL PERFORMANCE CURVES
Figura 4. External Connections for Compressor Operation
.,
~
,
T~.'.O~
~ .....
~ +1r--t--t--t~~~~~~
V
......
TA"-15~C
~ .....
J
-,
-60
Figura 5. XR-2216 Comprassor Output
Error vs. Input Signal Amplitude
-3 1---f1e--1
1 1
-50 -40 -30 -20 -10
0
EXfANDER OUTPUT SIGNAL dB
Figure 6. EX·2216 Expander Input
Error VS. Output Signal Amplitude
1-416
-,I--Y-Cf/''I--+--+-
B
Vee .. 12V.'F. 1 kHz
COMPRESSOR INPUT SIGNAL. dBm600n
i
~ -'r-~~+--+--~~---r-;
uC
r:+25
A
-I
~
! 0r--t-;~~~~::~:r~
.10
COMPANDOR INPUT SIGNAL, dIM 600U
Figure 7. XR-2216 Compandor
Tracking Error VI. Input Signal
XR·13600
Dual Operational Transconductance
Amplifier
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-13600 is a dual operational transconductance
(norton) amplifier with predistortion diodes and noncommitted Darlington buffer outputs.
BIAS
BIAS
A
The device is especially suitable for electronically controllable gain amplifiers, controlled frequency filters, an
other applications requiring current or voltage adjustments.
B
DIODE
BIAS
DIODE
BIAS
INPUT
INPUT
1+1
1+1
INPUT
INPUT
I-I
I-I
OUTPUT
FEATURES
OUTPUT
Direct Replacement for LM-13600 and LM-13600 A
Transconductance Adjustable Over 4 Decades
Excellent Transconductance-Control Linearity
Uncommitted Darlington Output Buffers
On-Chip Predistortion Diodes
Excellent Matching Between Amplifiers
Wide Supply Range: ± 2V to ± 18V
BUFFER
INPUT
BUFFER
INPUT
BUFFER
OUTPUT
BUFFER
OUTPUT
APPLICATIONS
Current-Controlled Amplifiers
Current-Controlled Impedances
Current-Controlled Filters
Current-Controlled Oscillators
Multipliers/Attenuators
Sample and Hold Circuits
Electronic Music Synthesis
ORDERING INFORMATION
Part Number
Package
XR-13600AP
XR-13600CP
Plastic
Plastic
Operating Temperature
O°C to + 70°C
O°C to + 70°C
SYSTEM DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
The XR-13600 consists of two programmable transcon-ductance amplifiers with high input impedance and
push-pull outputs. The two amplifiers share common
supplies but otherwise operate independently. Each
amplifier's transconductance is directly proportional to
its applied bias current. To improve signal-to-noise performance, predistortion diodes are included on the inputs; the use of these diodes results in a 10 dB improvement referenced to 0.5% THD. Independent
Darlington emitter followers are included to buffer the
outputs.
Supply Voltage (See Note 1)
±22 V
Power Dissipation (TA = 25°C, see Note 2) 625 mW
Derate Above 25°C
5 mW/oC
DC Input Voltage
+VCC to -VEE
Differential Input Voltage
±5V
Diode Bias Current (lD)
2 mA
Amplifier Bias Current (lB)
2 mA
Output Short Circuit Duration
Indefinite
Buffer Output Current (Note 3)
20 mA
Storage Temperature Range
- 65°C to + 150°C
1-417
XR·13600
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = + 25°e, Supply Voltage
= ± 15V, unless otherwise specified.
XR-13600A
PARAMETERS
TYP
MAX
Input Offset Voltage (Vas)
0.4
Vas Including Diodes
Input Offset Change
Input Offset Current
Input Bias Current
0.3
0.5
0.1
0.1
0.4
1
2
5
2
2
3
0.6
5
7
9600
12000
Forward Transconductance
(gm)
gm Tracking
Peak Output Current
Peak Output Voltage
Positive
Negative
Supply Current
Vas Sensitivity
Positive
Negative
CMRR
Common Mode Range
Channel Separation
Diff. Input Current
Leakage Current
Input Resistance
Open Loop Bandwidth
Slew Rate
Buff. Input Current
Peak Buffer Output Voltage
MIN
XR-13600C
7700
4000
3
350
300
+12
-12
80
±12
10
0.3
5
500
7
650
+t4.2
-14.4
2.6
20
20
110
±13.5
100
0.02
0.2
26
2
50
0.4
10
MIN
6700
5400
350
300
+12
-12
150
150
80
±12
10
5
10
5
TYP
MAX
UNITS
0.4
5
0.3
0.5
O.t
O.t
0.4
1
5
5
0.6
5
8
mV
mV
mV
mV
mV
,..A
,..A
,..A
9600
13000
0.3
5
500
650
+t4.2
-14.4
2.6
20
20
110
±13.5
100
0.02
0.2
26
2
50
0.4
10
,..mho
,..mho
dB
,..A
,..A
,..A
V
V
mA
150
150
100
100
5
,..VN
,..VN
dB
V
dB
nA
nA
KIl
MHz
VI,..Sec
,..A
V
CONDITIONS
Over Temperature Range
IB = 5,..A
Diode Bias Current (lD) = 500,..A
5,..A :s IB:S 500,..A
TA = 25°C
Over Temperature Range
TA = 25°C
Over Temperature Range
RL
RL
RL
= 0, IB = 5,..A
= 0, IB = 500,..A
= 0, Over Specified Temp Range
RL = "", 5 ,..A :S IB :S 500,..A
RL = "", 5 ,..A :S IB :S 500 ,..A
IB = 500,..A, Both Channels
II. Vas/II. V +
II. Vas/II. VReferred to Input (Note 5)
20 Hz < f < 20 KHz
IB = 0, Input = ±4 V
IB = 0 (refer To Test Circuit)
Unity Gain Compensated
(Note 5)
(Note 5)
TEST CIRCUITS
'36V
_IS. V
DIFFERENTIAL INPUT CURRENT TEST CIRCUIT
LEAKAGE CURRENT TEST CIRCUIT
Note 4. These specifications apply for Vee = VEE =
15V, TA = 25°e, amplifier bias current (lB) =
500 pA, pins 2 and 15 open unless otherwise
specified. The inputs to the buffers are grounded and outputs are open.
Note 5. These specifications apply for Vee = VEE =
.
15 V, IB = 500 p.A, ROUT = 5 kO connected
from the buffer output to - VEE and the input
of the buffer is connected to the transconductance amplifier output.
Note 1. For selections to a supply voltage above ± 22
V, contact factory.
Note 2. For operating at high temperatures, the device
may be derated based on a 150 0 e maximum
junction temperature and a thermal resistance
of 175° e/w which applies for the device soldered in a printed circuit board, operating in
still air.
Note 3. Buffer output current should be limited so as to
not exceed package disSipation.
1-418
XR·13600
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT OFFSET VOLTAGE
INPUT OFFSET CURRENT
IIJ;~I~ 15~
INPUT BIAS CURRENT
10'
II
II
II
10'.
+12S"C
5S"C
~
-,
10'
tlZ1iOC
-.
-5
0.'
''''.
AMPLIFIER 81AS CURRENT
L..;L..JIil=II-.u..L.I.LWI......J...llJJIlII....J...I.J.J.IIW
''''A
"~A
"e'
' .... A
'....
1ooO$lA
AMPLIFIEH BIAS CURRfNT lIal
PEAK OUTPUT VOLTAGE AND
COMMON MODE RANGE
~
~
-
I
I
tJ
"
'....
' .... A
AMPLIFIER BIAS CURRENT IISI
lL:
10'
11111
-13
VeMR
-13.5
J /
10'
11111
~f
'....
'_A
INPUT LEAKAGE
ov
/A
10ooj.lo\
10
-so·c _25°C
AMPLifiER 81AS CURRENT flSI
o°c
25·C
AMBIENT
TRANSCONDUCTANCE
'0'
~
/
10'
T1Ili!2S"C
-14.5
"A
~(+IVIN '" (-WIN" VOUT" 36 V~
RLOAO"""
-14
.1}'A
t=::=::
II~CMRII
t~I~I",lv I
13.5
LEAKAGE CURRENT
10'
II~guT II
14.5
' ....A
AMI'LIFIEH BIAS CURRENT (lal
50 C
75·C
H:MP~HATUR{
100 C
US C
IlAl
INPUT RESISTANCE
10'
10'
+l25°C
,.,
",
'0'
-'0'
~25·C
10'
''''A
"~A
AMPLifIER BIAS CURRENT IIBI
AMPLIFIER BIAS VOLTAGE VS
AMPLIFIER BIAS CURRENT
INPUT AND OUtPUT CAPACITANCE
2000
,...
1800
il)J'
• 2S o C
'000
...
800
400
..... TIII
-
!,W~
l00~A
O.lpF
,,,,A
"A
AMl'llf
I~H
' .... A
BIAS CUHfUNT (IBI
OUTPUT RESISTANCE
I~. !';~'~. T A • +~~J~'
1111
1400
1200
' ....A
INPUT DiffERENTIAL VOLTAGE
I-
II
-
1/
C, •
Cc
200
.1O'A
''''.
' ....A
AMPLifiER BIAS CURRENT IIBI
l/o1A
100A
10~A
AMPLIFU:.R BIAS CURRENT Ila'
1-419
AMl'lIHlR 81ASCURIIENT (lBI
1000j,lA
XR·13600
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
..
VOLTAGE VI AMPLIFIER BIAS CURRENT
"""'"
RL· 10 KU
:;....
-20
,
~
-
·t*'IP..J>
-40
OUTPUT NOISE VS fREQUENCY
'00
VS .. 111,IJI~
c('..J"
~
1
.,~
z
...
"-
;
z
-00
DIFFERENTIAL INPUT VOLTAGE (mVppl
&GO
"" ,.0
a
;..-
0
O"~BI
1\
~
~
-80
,GO
Isa'mA
il
:,\.;.O,,.t.
'0"
~ II !Jill
,,,,A
"A
"'1,ll-,1~A
"
.
,
AMPLIFIER BIASCUHRENT 18
'K
'OOK
fREQUENCY IH"
TYPICAL CIRCUIT CONNECTION
.,SV
10K
INPUT o-~--'Vyy.-~------o:"'i
'90
1.31(
10K
-tSV
O.OOl,..F
UNITY GAIN FOLLOWER
approaches unity and the Taylor series of the 1n function can be approximated as:
CIRCUIT OESCRIPTION
The differential transistor pair 04 and 05 form a transconductance stage in that the ratio of their collector
currents is defined by the differential input voltage according to the transfer function:
VIN = KT 1n §
q
14
~ 1n§ "" ~ 15- 14
q
14
q
14"" 15 ""
(1)
where VIN is the differential input voltage, KT/q is approximately 26 mV at 25° C and 15 and 14 are the collector currents of transistors 05 and 04 respectively. With
the exception of 03 and 013, all transistors and diodes
are identical in size. Transistors 01 and 02 with Diode
01 form a current mirror which forces the sum of currents 14 and 15 to equal IS;
VIN
[(I:~)] =
14
~2
15- 14
(4)
Collector currents 14 and 15 are not very useful by themselves and it is necessary to subtract one current from
the other. The remaining transistors and diodes form
three current mirrors that produce an output current
equal to 15 minus 14 thus:
(2)
VIN [(lS)(q)]
2KT
where IS is the amplifier bias current applied to the gain
pin.
= lOUT
(5)
The term in brackets is then the transconductance of
the amplifier and is proportional to IS.
For small differential input voltages the ratio of 14 and 15
1-420
XR·13600
LINEARIZING DIODES
APPLICATIONS
For differential voltages greater than a few millivolts,
Equation 3 is no longer accurate, and the transconductance becomes increasingly nonlinear. Figure 1 demonstrates how the internal diodes can linearize the transfer function of the amplifier. For convenience assume
the diodes are biased with current sources and the input signal is the form of current IS. Since the sum of 14
and 15 is IB and the difference is lOUT, currents 14 and
15 can be written as follows:
VOLTAGE CONTROLLED AMPLIFIERS (VCA)
Figure 2 shows how the linearizing diodes can be used
in a voltage controlled amplifier. To understand the input biasing, it is best to consider the 13 KI1 resistor as a
current source and use a Therenin equivalent circuit as
shown in Figure 3. This circuit is similar to Figure 1 and
operates the same. The potentiometer in Figure 2 is adjusted to minimize the effects of the control signal at
the output.
30K
~--'VV\r---o ~~~~ROL
R.
-
IOUT-2IS(
~
:~)
RA
13K
lK
OUTPUT
t-----o-j
RIN
30K
-VI
-VI
VON
Figure 2, Voltage Controlled Amplifier (VCA) Circuit
Figure 1. linearizing Diodes
Since the diodes and the input transistors have identical geometries and are subject to similar voltages and
temperatures, the following is true:
0,
.!a
10 + IS
+ lout
2_ _2_
KT 1n_2_ _ = KT 1n_
q
10 _ IS
2
_', lout = IS
(3.!a)
10
.!a _ lout
q
2
RTH
tiS
2
rv VTH
for
lis I <.!Q.
(6)
2
Figure 3, Equivalent VCA Input Circuit
Notice that in deriving Equation 6, no approximations
have been made and there are no temperature dependent terms. The limitations are that the signal current
not exceed 10/2 and that the diodes be biased with currents. In practice, replacing the current sources with
resistors will generate insignificant errors.
For optimum signal-to-noise performance, IB should be
as large as possible as shown by the Output Voltage vs.
Amplifier Bias Current graph. Larger amplitudes of input signal also improve the SIN ratio. The linearizing diodes help here by allowing larger input signals for the
same output distortion as shown by the Distortion vs.
Differential Input voltage graph. SIN may be optimized
by adjusting the magnitude of the input signal via RIN
(Figure 2) until the output distortion is below some desired level. The output voltage swing can then be set at
any level by selecting RL.
CONTROLLED IMPEDANCE BUFFERS
The upper limit of transconductance is defined by the
maximum value of IB (2 mAl. The lowest value of IB for
which the amplifier will function therefore determines
the overall dynamic range. At very low values of IB, a
buffer which has very low input bias current is desirable. A FET follower satisfies the low input current requirement, but is some what non-linear for large voltage
wing. The controlled impedance buffer is a Darlington
which modifies its input bias current to suit the need.
For low values of IB, the buffer's input current is minimal. At higher levels of IB, transistor Q3 biases up to
Q12 with a current proportional to IB for fast slew rate.
Although the noise contribution of the linearizing diodes
is negligible relative to the contribution of the amplifier's internal transistors, 10 should be as large as pOSSible. This minimizes the dynamic junction resistance of
the diodes (re) and maximizes their linearizing action
when balanced against RIN. A value of 1 mA is recommended for 10 unless the specific application demands
otherwise.
1-421
XR·13600
'.
,.,
STEREO VOLUME CONTROL
V1N:r
MODULATION
The circuit of Figure 4 uses the excellent matching of
the two XR-13600 amplifiers to provide a Stereo Volume Control with a typical channel-to-channel gain
tracking of 0.3 dB. Rp is provided to minimize the output offset voltage and may be replaced with two 5100
resistors in AC-coupled applications. For the component values given, amplifier gain is derived from Figure
2 as being:
Rt
1'0
VOl
v,
10'
Vo = 940xlB (mA)
VIN
Figure 5. Amplitude Modulator
30K
v,.
VOl
Figure 6. Four-Quadrant Multiplier
V02
10K
Figure 4. Stereo Volume Control
~
If Vc is derived from a second signal source then the
circuit becomes an amplitude modulator or twoquadrant multiplier as shown in Figure 5, where:
so,
'lOS
Vo
"
-15'1
Figure 7. AGC Amplifier
VOLTAGE CONTROLLEO RESISTORS (VCR)
The constant term in the above equation may be cancelled by feeding IS x IDRC/2(V + 1.4 V) into 10. The
circuit of Figure 6 adds RM to provide this current, resulting in a four-quadrant multiplier where RC is
trimmed such that Vo = OV for VIN2 = OV. RM also
serves as the load resistor for 10.
An Operational Transconductance Amplifier (OTA) may
be used to implement a Voltage Controlled Resistor as
shown in Figure 8. A signal voltage applied at RX generates a VIN to the XR-13600 which is then multiplied by
the gm of the amplifier to produce an output current,
thus:
Noting that the gain of the XR-13600 amplifier of Figure
3 may be controlled by varying the linearizing diode
current ID as well as by varying IB, Figure 7 shows an
AGC Amplifier using this approach. As Vo reaches a
high enough amplitude (3VBE) to turn on the Darlington
transistors and the linearizing diodes, the increase in
10 reduces the amplifier gain so as to hold Vo at that
level.
RX = R + RA
gmRA
where gm "" 19.2 IB at 25°C. Note that the attenuation
of Vo by Rand RA is necessary to maintain VIN within
the linear range of the XR-13600 input.
1-422
XR·13600
30K
Q---'V\illr---O Vc
Vo
R"
ZOOU
Figure 11. Vonage Controlled Low-Pass Finer
Figure 8. Vonage Controlled Resistor, Single-Ended
Figure 12 shows a voltage controlled high-pass filter
which operates in much the same manner, providing a
single RC roll-off below the defined cut-off frequency.
Figure 9 shows a similar VCR where the linearizing di·
odes are added. essentially improving the nose per·
formance of the resistor. A floating VCR is shown in Fig·
ure 10, where each "end" of the "resistor" may be at
any voltage within the output voltage range of the XR·
13600.
Vo
O.OD5sl
I
C
v,.
Figure 12. Voltage Controlled High-Pass Finer
Additional amplifiers may be used to implement higher
order filters as demonstrated by the two-pole Butterworth lowpass filter of Figure 13 and the state varia·
ble filter of Figure 14. Due to the excellent gm tracking
of the two amplifiers and the varied bias of the buffer
Darlingtons, these filters perform well over several decades of frequency.
Figure 9. Vonage Controlled Resistor with Unearizing Diodes
'-------0
RX':: RA 0 - - - - - - - - '
-Iii V
'.....
Figure 10. Floating Voltage Controlled Resistor
-16V
VOLTAGE CONTROLLED FILTERS
Figure 13. Vonage Controlled 2-Pole Butterworth Low-Pass
Finer
OTA's are extremely useful for implementing voltage
controlled filters, with the XR·13600 having the advan·
tage that the required buffers are included on the I.C.
The VC Lo·Pass Filter of Figure 11 performs as a unity·
gain buffer amplifier at frequencies below cut·off, with
the cut-off frequency being the point at which Xc/gm
equals the closed-loop gain of (R/RAJ. At frequencies
above cut-off the circuit provides a single RC roll-off (6
dB per octave) of the input signal amplitude with a - 3
dB point defined by the given equation, where gm is
again 19.2 x IB at room temperature.
VOLTAGE CONTROLLED OSCILLATORS (VCO)
The classic Triangular/Square Wave VCO of Figure 15 is
one of a variety of Voltage Controlled Oscillators which
may be built utilizing the XR-13600. With the compo·
nent values shown, this oscillator provides signals from
200 kHz to below 2 Hz as IC is varied from 1rnA to
10nA. The output amplitudes are set by IA x RA. Note
that the peak differential input voltage must be less
than 5 volts to prevent zenering the inputs.
1-423
XR·13600
360· or 180· for the inverter and 60· per filter stage.
This veo operates from 5 Hz to 50 kHz with less than
1% THD.
V,N
o---~----------~~~-oVc
10K
LO-PASS
OUT
I.
"K
BANDPASS OUT
Figure 14. Voltage Controlled State Variable Filter
Vc
Figure 17. Sinusoidal VCO Using Two XR-13600 Circuits
Figure 18 shows how to build a veo using one amplifier
when the other amplifier is needed for another function.
Figure 15. Triangular/Square-Wave VCO
'0 K
.,
30K
o----'VVIt--+-Ovc
A few modifications to this circuit produce the ramp/
pulse veo of Figure 16. When V02 is high, IF is added
to Ie to increase amplifier A 1's bias current and thus to
increase the charging rate of capacitor e. When V02 is
low, IF goes to zero and the capacitor discharge current is set by Ie.
~~
vco-"Nv=,,=:..,~--,.,------------------,
$1011.
Figure 18. Single Amplifier VCO
ADDITIONAL APPLICATIONS
IV+-.I V1A 2
VPK·~
L-________________-+__
lOOK
-J~r_~
Rl
Figure 19 presents an interesting one-shot which draws
no power supply current until it is triggered. A positivegoing trigger pulse of at least 2V amplitude turns on the
amplifier through RB and pulls the non-inverting input
high. The amplifier regenerates and latches it output
high until capacitor C charges to the voltage level on
the non-inverting input. The output then switches low,
turning off the amplifier and discharging the capacitor.
The capacitor discharge rate is speeded up by shorting
the diode bias pin to the inverting input so that an additional discharge current flows through D1 when the amplifier output switches low. A special feature of this timer is that the other amplifier, when biased from Va, can
perform another function and draw zero stand-by power
as well.
avPKC
lH·~
t La
Ie '"
ZVPII.C
lC
~PKO
1111 le« IF
Figure 16. Ramp/Pulse VCO
The voltage-controlled low-pass filter of Figure 11 may
be used to design a high-quality sinusoidal veo. The
circuit of Figure 17 employs two XR-13600 packages,
with three of the amplifiers configured as low-pass filters and the fourth as a limiter/inverter. The circuit oscillates at the frequency at which the loop phase-shift is
1-424
XR·13600
...
,. S
r-~---~""'-----1Ht--vvv-o
o--"V'VV---t
TlUGGEA
D.01"F
7MS
JL
vo
+-----ovo
".
..
VI'Q-<..3 __ 2KTVC
The voltage on the base of 01 is then
VS1 = (R1
+
-VREF
VOut. 1:1
V~~31~:I~IIII::: IRsl
In
:~~::1
R2) VIN1
R1
The ratio of the 01 to 02 collector currents is defined
by:
Figure 29. log Amplifier
VS1 = KT 1n IC2 = KT 1n!.6
q
IC1
q
11
Combining and solving for IS yields:
2(R1 + R2) vc]
IS= (I)
1 exp [
12R1 RC
-t t-t"
TIl ~
~z
IIOUT I-T~
This logarithmic current can be used to bias the circuit
of Figure 4 to provide temperature independent stereo
attenuation characteristic.
CONSTANT
tp'-,-Ct,SV
Figure 30. Pulse Width Modulator
For generating IS over a range of 4 to 6 decades of current, the system of Figure 31 provides a logarithmic
current out for a linear voltage in.
Since the closed-loop configuration ensures that the input to A2 is held equal to Ov, the output current of A1 is
equal to 13 = - VdRc.
The differential voltage between 01 and 02 is attenuated by the R1, R2 network so that A1 may be assumed
to be operating within its linear range. From equation
(5), the input voltage to A1 is:
-15V
Figure 31. logarithmic Current Source
. Vcccr------~---.------------------~----~------~~~
11
DIODE 81AS
BUFFER
OUTPUT
OUTPUT
-INPUT
O-- ..- ....... NETWORK
.....--+t~
L...IIIL.&---'l
ALBO
DIODES ........-
VCDO
CLOCK DRIVE
OUTPUT
CLOCK
INPUTS
ALBO DRIVE
CURRENT
......I--.....HI
ALBO
FILTER
Figure 2. Block Diagram of C5871C588 Interconnected
1-439
V+
X-TAL
CIRCUIT
XR· T56001T5620
11, T148C, & 2 M Bills PCM Line Repealer
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-T5600/T5620 is a bipolar monolithic repeater IC
designed for PCM carrier systems operating at 1.544 M
bills (T1), 2 M bills, or 2.37 M bills (T148C). It provides
all of the active circuits required for one side of a PCM
repeater. A crystal filter clock extraction version of
XR-T5600/T5620 is available as XR-T5700/T5720.
SUBSTRATE: GROUND
ALBO GROUND
ALBO
POAT 1
ALBO
CONTROL
ALBO
PORT 2
CLOCK
AMPLIFIER
BIAS
ALBO
PORT 3
FEATURES
LC TANK
PREAMP
-vE INPUT
Single 5.1 V Power Supply
Less than 10 ns Sampling Pulse over the Operating
Range
Triple Matched ALBO Ports
2 M Bills Capability
CLOCK
PREAMP
.VE INPUT
PREAMP
-vE OUTPUT
~-_--L..;..;;;,j OUTPUT
tlr:::==!:~:r]-JlPI:ill~~
PREAMP
-VE OUTPUT
CLOCK SHIFTED
INPUT
PHASE
-VE DATA
OUTPUT
DIGITA.L
GROUND
APPLICATIONS
T1 PCM Repeater
T148C PCM Repeater
European 2 M Bitls PCM Repeater
T1C PCM Repeater (requires external preamplifier)
SYSTEM DESCRIPTION
The XR-T5600/T5620 performs most of the functions required for one side of a PCM repeater operating at 2 M
bills or similar baud rate. The integrated circuit amplifies the received positive and negative pulses and
feeds them into Automatic Line Build-out (ALBO), clock
and data threshold detectors, see Figure 1. The ALBO
threshold detector ensures that the received pulses at
Pins 7 and 8 have the correct amplitude and shape.
This is carried out by controlling the gain and frequency
shaping of the ALBO network with three variable impedance ALBO ports.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
- 65°C to + 150°C
Operating Temperature
-40°C to +85°C
Supply Voltage
-0.5 to + 10V
Supply Voltage Surge (10 ms)
+25V
Input Voltage (except Pin 2,3,4,17)
-0.5 to 7V
Input Voltage (Pin 2,3,4,17)
-0.5 to +0.5V
Data Output Voltage (Pin 10,11)
20V
Voltage Surge (Pin 5,6,10,11) (10 msec only)
50V
The clock threshold detector extracts timing information from the pulses received at Pins 7 and 8 and
passes it into the external tank coil at Pin 15. The
sinusoidal-type waveform is amplified into a square
wave at Pin 13, and forwarded through an external
phase shift network into Pin 12. This waveform provides the <;lata sampling pulse which opens latches into
which the data from the data threshold detectors is
passed. The resulting pluses are stored for half a bit
period (normally 488 ns) in the latches. They appear as
half-width output pulses at Pins 10 and 11.
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-T5600/T5620
Ceramic
-40°C to 85°C
1-440
XR·T5600
ELECTRICAL CHARACTERISTICS
Tast Conditions: TA = 25°C, VCC = 5.1 V ± 5%, unless specified otherwise (see Figure 1).
PARAMETERS
Supply Current
Data Output Leakage Current
ALBO Port Off Voltage
Amplifier Pin Voltage
PINS
MIN
TVP
MAX
UNIT
22
0
30
100
mA
,.A
0
2.9
0.1
3.4
V
V
0
50
50
53
200
mV
dB
kO
0
25
25
kO
0
1.6
80
49
1.4
V
%
%
mA
14
10,11
2,3,4
5,6,7,8
2.4
CONDITIONS
Vpull- up = 15 V, Vcc =
5.35 V
DYNAMIC CHARACTERISTICS AMPLIFIER
Output Offset Voltage
AC Gain @ 1 MHz
Input Impedance
Output Impedance
-50
47
20
Rs = 8.2 kO
ALBO
ALBO Off Impedance
ALBO On Impedance
20
THRESHOLDS
ALBO Threshold
Clock Threshold as % of ALBO Threshold
DATA Threshold as % of ALBO Threshold
Clock Drive Current
1.4
68
42
0.7
1.5
OUTPUT STAGES
Output Pulse Rise Time
Output Pulse Fall Time
Output Pulse Width
Output Pulse Width Differential
Buffer Gate Voltage (Low)
Buffer Gate Voltage Differential
At Vo = VALBO Threshold
RL =1300, Vpull- up =
5.1 ±5%
224
-10
0.65
-0.15
244
1-441
40
40
264
+10
0.95
0.15
ns
ns
ns
ns
V
V
XR·T5620
ELECTRICAL CHARACTERISTICS
Test Condhlons: Unless otherwise stated, all characteristics shall apply over the operating temperature range of - 40°C to + 85°C
with Vcc = 5.1 V ±5%, all voltages referred to ground = 0 V.
SYMBOL
PARAMETERS
PINS
MIN
TYP
MAX
UNIT
22
30
mA
6
100
,..A
2.9
0
3.4
0.1
V
V
CONOITIONS
GENERAL (ReI. Figure 2)
IS
ILD
Supply Current
Data Output Leakage
Current
14
10,11
Amplifier Pin Voltages
ALBO Ports Off Voltage
5,6,7,8
2,3,4
2.4
From Vs
(See Note 1)
Note 1: Vs = 15V, VCC = 5.35V
AMPLIFIER (ReI. Figure 2, Only Pins 1,9,10 ... 18 (connected)
Input Offset Voltage
5&6
-10
+10
mV
Input Bias Current
5&6
0
5
,..A
Input Offset Current
5&6
-1
1
,..A
Output Offset Voltage
7&8
-50
-50
mV
Common Mode
Rejection Ratio
Output Voltage Swing
7&8
7&8
30
2.2
0
RS =
(See
RS =
(See
RS =
(See
RS =
(See
8.2 kO
Note 1)
8.2 kO
Note 1)
8.2 kO
Note 1)
8.2 kO
Note 1)
dB
V
Vcc ±10%
6
mV
10
,..A
RS = 10kO
(See Note 1)
T = 25°C
Note 1: RS = Source Resistance
CLOCK AMPLIFIER (ReI. Figure 2 Disconnect Pin 15 from Pin 16)
Notes: 1.
2.
3.
4.
5.
Input Offset Voltage
15 & 16
Input Bias Current
Max Output Voltage
Min Output Voltage
Max.lMin Output
Voltage Difference
15 & 16
13
13
..
-
0.5
V
V
0.7
0.7
0.7
50
mV
RS = Source reSistance, Pin 15 poSItive With respect to Pin 16
Pin 15 = Pin 16 = 3.6V
Pin 15 = 2.6V, Pin 16 = 3.6V
Pin 15 = 4.6V, Pin 16 = 3.6V
Calculation only
ALBo (Ref Figure 2)
I
On Current
Drive Current
Resistance Pin 17 to Ground
I
1
mA
mA
17
I
kO
V8- V7 = ±1.75V
V8-V7= ±1.75V
Not Powered
DYNAMIC CHARACTERISTICS
AMPLIFIER (ReI. Figure 3)
Ao
Zin
Zout
I
AC Gain at 1 MHz
Input Impedance
Output Impedance
I
5 to 8
5
dB
kO
o
7,8
I
(See Note 1)
(See Note 2)
Notes: 1. At 1 MHz, AC ground Pins 7 and 8 disconnect 51 0 resistor. Allow for in-circuit R,C
2. At 1 MHz, use Figure 2.
CLOCK AMPLIFIER (ReI. Figure 3)
Ao
BW
td
Zout
AC Gain
- 3 dB Bandwidth
Delay
Output Impedance
Notes: 1. Remove dc offset,
2. Remove dc offset,
3. Remove dc offset,
edge.
4. Remove de offset,
15,16 to 13
15,16 to 13
15 to 13
13
32
10
8
12
200
dB
MHz
ns
0
(See
(See
(See
(See
Note
Note
Note
Note
1)
2)
3)
4)
at 2,048 MHz, Pin 13 = 1 V pk-pk Sine wave
Pin 13 = 1 V pk-pk sine wave
Pin 15 = 2 V pk-pk sine wave; delay from Pin 15 negative-going zero crossover to Pin 13 positive
at 2,048 MHz
1-442
XR·T5620
SYMBOL
PARAMETERS
PINS
MIN
2,3,4
20
TYP
MAX
UNIT
CONDITIONS
ALBO (Ref. Figure 2)
Off Impedance
Intermediate Impedance
Difference
On Impedance
Transconductance
Notes: 1.
2.
3.
4.
At
At
At
At
1
1
1
1
MHz,
MHz,
MHz,
MHz,
kll
(See Note 1)
5
25
0.03
%
11
dB
(See Note 2)
(See Note 3)
(See Note 4)
1.5
1.5
0
1.6
1.6
5
V
V
%
(See Notes 1 & 2)
(See Notes 1 & 2)
(See Note 3)
1.0
1.4
mA
(See Note 4)
1.0
1.3
mA
(See Note 5)
0
5
80
80
5
48
48
3
%
%
%
%
%
%
%
(See Note 3)
(See Notes 1, 6, 8)
(see Notes 1, 7, 8)
(See Note 3)
(See Notes 1,8,9, 11)
(See Notes 1,8, 10, 11)
(See Note 3)
2,3,4
2,3,4
7/8 to 1
allow for In'CIrCUlt R,C
V8-V7 adjusted for current at Pin 1 = 100,..A
V8-V7 adjusted for ± 1.75 V
change in V8-V7 for current at Pin 1 = 10,..A to 100,..A
THRESHOLD VOLTAGES (Ref. Figure 3)
ALBa Threshold + ve
ALBa Threshold -ve
ALBa Threshold Difference
Clock Drive on Current
(Peak) +ve
Clock Drive on Current
(Peak) -ve
Clock Drive on Current
Difference
Clock Threshold + ve
Clock Threshold - ve
Clock ThreshOld Difference
Data Threshold + ve
Data Threshold - ve
Data Threshold Difference
Notes:
8-7
7-8
-
1.4
1.4
-5
18
18
8-7
7-8
8-7
7-8
-
-5
68
68
-5
44
44
-3
0
46
46
0
..
1. Pklpk voltage at PinS 7 and 8 of a 1 MHz Sine wave derived through amplifier and measured dlfferenllally
2. Pklpk voltage at Pins 7 and 8 adjusted for current at Pin 1 = 3 mA
3. Calculation only
( higher value
)
percentage difference calculated from
lower value -1
x 100 %
4.
5.
6.
7.
8.
9.
10.
11.
V8-V7 adjusted to ALBa threshold + ve voltage ref. Pin 16 = 3.6 V
VrV8 adjusted to ALBa threshold -ve voltage ref. Pin 16 = 3.6 V
V8-V7 adjusted to peak current at Pin 18 = 1/2 (clock drive on current peak +ve)
VrV8 adjusted to peak current at Pin 18 = 1/2 (clock drive on current peak -vel
Figure taken as a percentage of lower ALBa threshold
V8-V7 increased until 1 MHz PRF on counter at Pin 10
VrV8 increased until 1 MHz PRF on counter at Pin 11
With 2,048 MHz 2 V pk-pk sine wave to Pin 15 with 180,..H in parallel with 36 11 to Pin 16 = 3.6 V
OUTPUT STAGES (Ref. Figure 3. Use 180 JLH inductor between Pins 15 and 16. Apply 2.048 MHz 2V pk/pk to Pin 15.)
tr
tr
tf
tf
tw
.a.tw
VOL
VOL
.a.VOL
Output Pulse Rise
Time +ve
Output Pulse Rise
Time -ve
Output Pulse Fall
Time +ve
Output Pulse Fall
Time -ve
Output Pulse Width + ve
Output Pulse Width -ve
Output Pulse Width
Difference
Buffer Gate Voltage
(low) +ve
Buffer Gate Voltage
(low) -ve
Buffer Gate Voltage
Difference
10
40
ns
10% - 90%
11
40
ns
10% to 90%
10
40
ns
10%-90%
11
10
11
224
224
40
264
264
ns
ns
ns
10%-90%
at 50%
at 50%
-
-10
10
ns
10
0.65
0.95
V
11
0.65
0.95
V
-
-0.15
0.15
V
1-443
244
244
XR·T5620
Vee
1
Vs
Figure 2. D.C. Parameter Test Circuit
CLOCK
Vee
INPUT
Vee
O.l~F
AMPLIFIER INPUT
~
1
51
Figure 3. A.C. Parameter Test Circuit
1·444
XR·T5620
SYMBOL
I
I
PARAMETERS
PINS
I
MIN
I
TYP
I
I
10
I
MAX
I
UNIT
I
I
ns
I
CONDITIONS
SAMPLE PULSE WIDTH (ReI. Figure 4. Cy = 27 pF)
ISample Pulse Width
I
I
(See Notes 1... 5)
Notes: 1. The sample pulse width IS the period dUring which the output latches are opened to accept a signal above the data
threshold at Pin 7 or 8 and cause a half·width output pulse at Pin 11 or 10 respectively.
2. Sample pulse width is specified with a 2.048 MHz TIL waveform at clock input (Pin 15) and a 2.400 MHz Schottky TIL
waveform at amplifier input in the circuit of Figure 4. Figure 7 shows the relevant Ie waveforms.
3. Monitor the frequency of coincident output pulses at Pins 10 and 11 either directly or through output circuit to
frequency counter.
4. Sample pulse width = X ns + (0.1 x measured frequency in kHz) ns where X is the mean rise/fall times of the
waveform at Pin 8 between 25% and 75%.
5. X to be within the range 10 ns < X < 12 ns. This requires HF layout techniques with the amplifier operated closed
loop.
SAMPLE PULSE GENERATOR INPUT WAVEFORM (Pin 12 ReI. Figure 4, Cy
I
Output Pulse Frequency
I
10,11
I
1.024
-100 ppm
I
40 pF)
=
1.024
I
1.024
+100 ppm
I
MHz
I
(See Note 1)
Notes: 1. Width 2.048 MHz ± 100 ppm TIL waveform at clock input with half of above waveform frequency at amplifier input.
CLOCK
INPUT
t.
I,,",
,"
~
~
Figure 4. Sampling Pulse Test Circuit
1-445
XR·T5620
TYPICAL AT 5.1 V AND AT 25°C
60
53
50
47
40
r- ..... 1"-
r---. ...........
30
........
GAIN (dB I
~
180
~~~ GAIN (MAXI
t'-
"
..... i'
20
10
0
'"
I"::~~~
I
GAIN (MINI
PHASE (MAXI "
~V
'"
1\
-10
\
\
-20
-30
2
3
4
6
8 10
2
120
~~"
,,~ ,
3
4
PHASE (DEGREESI
~
60
, , ~tTl
6
8100
2
3
4
0
-60
-120
6
81000
FREQUENCY (MHzl
Figure 5. Typical and Limiting Values of Gain and Phase
INPUT WAVEFORMS
+2.4V
+O.4V
CLOCK liP 2.048 MHz
+2.4V
AMPLIFIER lIP 2.400 MHz
+0.4V
IC WAVEFORMS
SAMPLE PULSE (INTERNAl)
PIN 8
r----
PIN 10
+5.1V
+0.7V TYP.
+5.1V
PIN 11
+0.7V TYP.
~
COINCIDENT OUTPUT PULSES
Figure 6.
Ie Waveforms for Measuring Sampling Pulse Width
1·446
XR·T5640
PCM AMI Line Receiver and
Clock Recovery Circuit
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-T5640 is a monolithic bipolar IC designed for T1
type line receiver application operating at 1.544 M bit/so
It provides all the active circuitry required to perform
automatic line build out (ALBO), threshold detection,
binary NRZ data and clock recovery.
ALBO
GND
ALBO
PORT'
A clock recovery using crystal filter circuit version of
the XR-T5640 is also available as XR-T5740.
ALBO
PORT"
ALBO
PORT
FEATURES
'~
PREAMP
-VE INPUT
On Chip NRZ Data and Clock Recovery
Less than 10 ns Sampling Pulse Over the Operating
Range
Triple Matched ALBO Ports
Single 5.1 Power Supply
PREAM"
. 'JE INPUT
PREAMP
Vf OUTPUT
PREAMP
·vE OUTPUT
DIGITAL
GROUND
SUBSTRATE
GND
ALBO
CONHIOl
CLOCK
AMPLIFIER
BIAS
LC TANK
vee
CLOCK
OUTPUT
PHASe SHIFTED
CLOCK INPUT
CLOCK
NRZ DATA
APPLICATIONS
T1 PCM Line Receiver
T1C PCM Line Receiver (requires external gain)
General Purpose Bipolar Line Receiver
SYSTEM DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
The XR-T5640 is designed as a receiver for interfacing
T1 PCM carrier lines on plastic or pulp insulated cables. It can also be used as a general purpose alternate
mark inversion (AMI) receiver.
Storage Temperature
- 65°C to + 150°C
Operating Temperature
- 40°C to + 85°C
Supply Voltage
- 0.5 to + 10V
+ 25V
Supply Voltage Surge (10 ms)
Input Voltage (except Pins 2,3,4,17)
- 0.5 to 7V
Input Voltage (Pins 2,3,4,17)
- 0.5 to + 0.5V
Data Output Voltage (Pins 10,11)
20V
Voltage Surge (Pins 5,6,10,11) (10 msec only)
50V
The XR-T5640 is a modified version of XR-T5620 PCM
repeater IC. It contains all the active circuitry needed
to build a T1 line receiver for interfacing up to 6300 ft.
The preamplifier, the clock amplifier, threshold detectors, ALBO port, data latches and output drivers are
similar to the ones on XR-T5620. Clock extraction is
done by means of an L-C tank circuit.
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-T5640
Ceramic
- 40°C to 85°C
Bipolar + 1 and - 1 pulses are combined within the IC
to form a binary non-return to zero PCM Signal at Pin
10. A synchronous clock signal is made available at Pin
11. Both outputs have open collector transistors.
1-447
XR·T5640
ELECTRICAL CHARACTERISTICS
Tast Conditions: TA = 25°C, VCC = 5.1 V ± 5 %
PARAMETERS
Supply Current
Clock & Data Output Leakage Current
Amplifier Pin Voltages
Amplifier Output Voltage Swing
Amplifier Output Offset Voltage
Amplifier Input Bias Current
ALBO on Current
Drive Current
MIN
2.4
2.2
-50
TYP
MAX
UNIT
22
0
2.9
30
100
3.4
mA
0
50
5
p.A
V
V
mV
CONDITIONS
ALBO Off
VPUII-UP = 15V
A Unity DC Gain
Rs
= 8.2 kll
p.A
mA
mA
3
1
AC CHARACTERISTICS
Pre-Amplifier
AC Gain at 1 MHz
Input Impedance
Output Impedance
Clock Amplifier
AC Gain
- 3 dB Bandwidth
Delay
Output Impedance
50
Open Loop
200
dB
kll
11
Open Loop
200
dB
MHz
ns
11
25
kll
11
20
32
10
10
ALBO
Off Inpedance
On Impedance
20
RL = 13011, VpUIl- Up
5.W ± 5%
CLOCK OATA OUTPUT BUFFERS
Rise Time
Fall Time
Output Pulse Width
Sample Pulse Width
VOL
IL sink
30
30
244
10
0.7
35
=
ns
ns
ns
ns
V
mA
THRESHOLDS
ALBO
Clock Drive Current Peak
Clock Thresholds
% of ALBO
Data Threshold
% of ALBO
1.4
1.5
1.0
63
40
46
1-448
1.6
V
mA
75
%
52
%
At Va
= VALBO Threshold
XR·T5650
PCM Line Receiver and
Clock Recovery Circuit
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-T5650 is a monolithic bipolar IC designed for
PCM type line receiver applications operating at T1,
T148C, T1C and 2 M bitls data rates. It provides all the
active circuitry required to perform automatic line build
out (ALBO), threshold detection, positive and negative
data and clock recovery.
ALBO
eND
Clock recover using a crystal filter instead of an LC
tank circuit is also available as XR-T5750.
FEATURES
On Chip Positive and Negative Data, Clock Recovery
Less than 10 ns Sampling Pulse over the Operating
Range
Double Matched ALBO Ports
Single 5.1 V Power Supply
2 M Bitts Capability
ALBO
CONTROL
ALBO
PORT 2
AMPLIFIER
BIAS
LC TANK
INPUT
AMPLIFIER
'VE INPUT
vee
AMPLIFIER
CLOCK
OUTPUT
DIGITAL
GROUND
·1 DRIVER
Package
Operating Temperature
-40°C to +85°C
-1 DRIVER
The XR-5650 is a modified version of XR-T5620 PCM repeater IC. It contains all the active circuitry needed to
build a PCM line receiver up to 6300 It cable length.
The preamplifier, the clock amplifier, threshold detectors, data latches and output drivers are similar to the
ones on XR-T5620. Clock extraction is done by means
of an LC tank circuit.
In addition to plus and minus one outputs, a synchronous clock signal is made available at Pin 11 by deleting one of the ALBO ports on XR-T5620 thus leaving
two matched ALBO parts. All outputs have high current
open collector transistors.
ORDERING INFORMATION
Ceramic
CLOCK
The XR-T5650 is designed for interfacing T1, T148C
and 2 Mbit/s PCM carrier lines on plastic or pulp insulated cables. It can also be used at T1 Crate (3.152 M
bit/s) with external gain. Since it outputs plus and minus
ones on a bipolar pulse stream together with the clock,
it can be used to interface systems having different line
codes like AMI, AMI-B8ZS or AMI-HDB3.
- 65°C to + 150°C
Storage Temperature
-40° to +85°C
Operating Temperature
-0.5 to + 10V
Supply Voltage
+25V
Supply Voltage Surge (1 Oms)
-0.5t07V
Input Voltage (except Pins 2,3,4,17)
- 0.5 to + 0.5V
Input Voltage (Pins 2,3,4,17)
20V
Data Output Voltage (Pins 10,11)
50V
Voltage Surge (Pins 5,6,10,11) (10 msec only)
Part Number
PHASE SHIFTED
CLOCK INPUT
SYSTEM DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
XR-T5650
CLOCK
AMPLIFIER
·VE INPUT
AMPLIFIER
·VE OUTPUT
T1 PCM Line Receiver
T148C Line Receiver
T1C PCM Line Receiver (requires external amplifier)
General Purpose Bipolar Line Receiver
HDB3 Line Receiver
B8ZS Line Receiver
eND
ALBO
PORT 1
VE OUTPUT
APPLICATIONS
SUBSTRATE
1-449
XR·T5650
ELECTRICAL CHARACTERISTICS
Test CondHlons: Vee = 5.1 V ± 5 %, TA = 25°C, unless specified otherwise.
PARAMETERS
Supply Current
Clock and Data Output
Output Leakeage Current
Amplifier Pin Voltages
Amplifier Output
Offset Voltage
Voltage Swing
Amplifier Input
Bias Current
Alba on Current
Drive Current
MIN
2.4
-50
2.2
TYP
MAX
UNIT
24
30
mA
ALBO Off
0
2.9
100
3.4
f'A
Vrull- uB = 15 V
A DC nity Gain
0
50
mV
V
Rs = 8.2 kO
Measured Differentially
from Pin 7 to Pin 6
5
V
CONDITIONS
f'A
mA
mA
3
1
AC CHARACTERISTICS
Pre-Amplifier
AC Gain at 1 MHz
Input Impedance
Output Impedance
Clock Amplifier
AC Gain
- 3 dB Bandwidth
Delay
Output Impedance
ALBO
Off Impedance
On Impedance
50
200
dB
kO
0
200
dB
MHz
ns
0
25
kO
0
20
32
10
10
20
CLOCK DATA OUTPUT BUFFERS
RL = 1300, VPull-up =
, 5,1 V±5%
Rise Time
Fall Time
Output Pulse Width
Sample Pulse Width
VOL
IL sink
30
30
244
10
0.7
35
ns
ns
ns
ns
V
mA
THRESHOLDS
ALBO
Clock Drive Current Peak
1.5
1.0
1,6
63
68
75
%
40
46
52
%
1.4
V
mA
CLOCK THRESHOLD
% of ALBO
DATA THRESHOLD
% of ALBO
1-450
At Va = VALBO Threshold
XR·T5660
Low Power T1, T148C, & 2 M Bitls Repeater
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-T5660 is a monolithic bipolar low power version
of the XR-T5620 repeater circuit for Tl type carrier system operating at 1.544 M bitls (Tl), European 2 M bitls
or 2.37 M bitls (T148C). It provides all of the active circuitry required for one side of a PCM repeater. A crystal
filter clock extraction version is available as XR-T5760.
ALBO
GROUND
ALBO
APPLICATIONS
Tl PCM Repeater
T148C PCM Repeater
European 2 M Bitts PCM Repeater
T1C PCM Repeater (requires external amplifier)
ALBO
PORT 1
CONTROL
ALBO
PORT 2
CLOCK
AMPLIFIER
BIAS
ALBO
PORT 3
LC TANK
FEATURES
Low Power
Single 5.1 V Power Supply
Triple Matched Automatic Line Build-out (ALBO) Ports
2 M Bitls Capability
SUBSTRATE
GROUND
PREAMP
-VE INPUT
Vee
PREAMP
+VE INPUT
CLOCK
OUTPUT
PHASE SHIFTED
PREAMP
-VE OUTPUT
CLOCK INPUT
PREAMP
+VE OUTPUT
-VE DATA
OUTPUT
DIGITAL
·VE DATA
OUTPUT
GROUND
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
-65°C to + 150°C
Operating Temperature
- 40°C to + 85°C
Supply Voltage
-0.5 to +10V
Supply Voltage Surge (10 ms)
+25V
Input Voltage (except Pins 2,3,4,17)
-0.5 to 7V
Input voltage (Pins 2,3,4,17)
- 0.5 to + 0.5V
Data Output Voltage (Pins 10,11)
20V
Voltage Surge (Pins 5,6,10,11) (1 msec only)
50V
Bipolar PCM signal is attenuated and dispersed in time
as it travels along the transmission cable, characteristics of which vary with length, frequency, temperature
and humidity. The PCM signal when received is amplified, equalized for amplitude characteristics and reconstructed by the preamplifier, automatic line build out
(ALBO), clock and data threshold circuits. Amplitude
equalization is achieved through shaping the frequency
spectrum with the help of variable impedance ALBO
ports.
°
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-T5660
Ceramic
- 40°C to + 85°C
Timing information is contained in the incoming pulse
stream. This signal is full wave rectified and applied to
an L-C tank circuit to extract the clock signal at the data rate. The clock signal is amplified and phase shifted
between Pins 13 and 12 to obtain 90° phase shift by
means of an R-L-C circuit.
SYSTEM DESCRIPTION
The XR-T5660 is a monolithic bipolar PCM repeater IC
operating at 1.544 (T1), 2.048 and 2.37 (T148C) M bitsl
sec. It is the low power version of XR-T5620 PCM repeater IC. It contains all the active circuitry to implement one side of a PCM repeater operating on either
pulp or plastic insulated cables. Repeater to repeater
spacing on either type of cable is 6300 ft. max.
Data is sampled and stored in the output data latches
by an internally generated sampling pulse. Buffer drivers are then enabled to produce preCisely timed output
pulses whose width and time of occurence are controlled by the regenerated clock.
1-451
XR·T5660
ELECTRICAL CHARACTERISTICS
Test Conditions: VCC
= 5.W,
PARAMETERS
Supply Current
Clock & Data Output
Output Leakage Current
Amplifier Pin Voltages
Amplifier Output
Offset Voltage
Voltage Swing
Amplifier Input
Bias Current
ALBO on Current
Drive Current
±5%, TA
= 25°C,
MIN
2.4
-50
2.2
unless otherwise specified.
TYP
MAX
UNIT
9
14
mA
ALBO Off
0
2.9
100
3.4
p.A
Vru ll- u5 = 15 V
A DC nity Gain
0
50
mV
V
5
p.A
mA
mA
3
1
V
CONDITIONS
Rs = 8.2 kO
Measured Differentially
from Pin 8 to Pin 7
AC CHARACTERISTICS
Pre-Amplifier
AC Gain at 1 MHz
Input Impedance
Output Impedance
Clock Amplifier
AC Gain
- 3 dB Bandwidth
Delay
Output Impedance
ALBO
Off Impedance
On Impedance
200
dB
kO
0
200
dB
MHz
ns
0
25
kO
0
50
20
32
10
10
20
DATA OUTPUT BUFFERS
RL = 1300, Vpull- up =
5.1 V ± 5%
Rise Time
Fall Time
Output Pulse Width
Sample Pulse Width
VOL
IL sink
ns
ns
ns
ns
V
mA
30
30
244
10
0.7
35
THRESHOLDS
ALBO
Clock Drive Current Peak
1.4
1.5
1.0
1.6
V
mA
63
68
75
%
40
46
52
%
CLOCK THRESHOLD
% of ALBO
DATA THRESHOLD
% of ALBO
1-452
At Va = VALBO Threshold
XR· T57001T5720
T1, T148C, & 2 M Bitls PCM Line Repeater
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-T5700JT5720 is a bipolar monolithic repeater IC
that provides all the active circuits required for one
side of a PCM repeater. The IC is designed for clock extraction by using a crystal filter.
ALBO GROUND
ANALOG GROUND
SUBSTRATE GROUND
The primary applications of XR-T5700 are T1 (1.544 M
bit/s), T148C (2.37 M bitls) and European 2 M bitls PCM
repeater.
A tank circuit clock extraction version of XR-T57001
T5720 is available as XR-T5600JT5620.
CLOCK
DRIVE
-,,,u~,~
ALBO
PORT 1
ALBO
CONTROL
ALBO
PORT 2
CLOCK
AMPLIFIER
ALBO
PORTJ
CLOCK
AMPLIFIER
INPUT
AMPLIFIER
-VE INPUT
AMPLIFIER
",VEINPUT
Vee
--~L-:..;::;J
CLOCK
OUTPUT
FEATURES
AMPLIFIER
-VEOUTPUT
Crystal Clock Extraction
Single 5.1 V Power Supply
Less than 10 ns Sampling Pulse over the Operating
Range
Triple Matched ALBO Ports
AMPLIFIER
+VE OUTPUT
GROUND
APPLICATIONS
PHASE SHIFTED
_~~O-J I~::.J
CLOCK INPUT
-VE DATA
OUTPUT
+VE DATA
OUTPUT
SYSTEM DESCRIPTION
T1 PCM Repeater
T148C PCM Repeater
T1C PCM Repeater (requires external preamplifier)
European 2 M Bitls PCM Repeater
The XR-T5700JT5720 performs most of the functions required for one side of a PCM repeater operating at 2 M
bitls or similar baud rate. The integrated circuit amplifies the received positive and negative pulses and
feeds them into Automatic Line Build-out (ALBO), clock
and data threshold detectors, see Figure 1. The ALBO
threshold detector ensures that the received pulses at
Pins 7 and 8 have the correct amplitude and shape.
This is carried out by controlling the gain and frequency
shaping of the ALBO network with three variable impedance ALBO ports.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
-65°C to +150°C
Operating Temperature
- 40°C to + 85°C
Supply Voltage
-0.5 to +10V
Supply Voltage Surge (10 ms)
+25V
Input Voltage (except Pins 2,3,4,17)
-0.5 to 7V
Input Voltage (Pins 2,3,4,17)
- 0.5 to + 0.5V
Data Output Voltage (Pins 10,11)
20V
Voltage Surge (Pins 5,6,10,11) (10 msec only)
50V
The clock threshold detector extracts timing information from the pulses received at Pins 7 and 8 and
passes it into open collector Pin 18. A crystal filter is
connected from Pin 18 to clock amplifier input Pins 16
and 15. The sinusoidal-type waveform is amplified into
a square wave at Pin 13, and forwarded through an external phase shift network into Pin 12. This waveform
provides the data sampling pulse which opens latches
into which the data from the data threshold detectors is
passed. The resulting pulses are stored for half a bit period (normally 488 ns for 2 M bitls) in the latches. They
appear as half-width output pulses at Pins 10 and 11.
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-T57001
T5720
Ceramic
-40C to +85°C
1-453
XR·T5700
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25°C, VCC = 5.1 V ± 5% unless specified otherwise (see Figure 1).
PARAMETERS
Supply Current
Data Output Leakage Current
ALBO Port Off Voltage
Amplifier Pin Voltage
PINS
MIN
14
10,11
2,3,4
5,6,7,8
2.4
TYP
MAX
UNIT
22
0
30
100
mA
p.A.
0
2.9
0.1
3.4
V
V
0
50
50
53
mV
dB
kO
0
CONDITIONS
Vpull- up = 15 V, Vcc ;;'
5.35 V
DYNAMIC CHARACTERISTICS AMPLIFIER
Output Offset Voltage
AC Gain @ 1 MHz
Input Impedance
Output Impedance
-50
47
20
200
Rs = 8.2 kO
ALBO
ALBO Off Impedance
ALBO On Impedance
20
25
25
kG
1.6
80
49
1.4
V
%
%
mA
0
THRESHOLDS
ALBO Threshold
Clock Threshold as % of ALBO Threshold
DATA Threshold as % of ALBO Threshold
Clock Drive Current
1.5
1.4
68
42
0.7
OUTPUT STAGES
Output Pulse Rise Time
Output Pulse Fall Time
Output Pulse Width
Output Pulse Width Differential
Buffer Gate Voltage (Low)
Buffer Gate Voltage Differential
At Vo = VALBO Threshold
RL = 1300, Vpull- up =
5.1 ±5%
224
-10
0.65
-0.15
1-454
244
40
40
264
+10
0.95
0.15
ns
ns
ns
ns
V
V
XR·T5720
ELECTRICAL CHARACTERISTICS
Test Conditions: Unless otherwise stated, all characteristics shall apply over the operating temperature range of - 40°C to + 85°C
with Vcc = 5.1 V ±5%, all voltages referred to ground = 0 V.
PARAMETERS
SYMBOL
PINS
TYP
MAX
UNIT
22
30
rnA
100
,.A-
3.4
0.1
V
V
-10
+10
mV
p.A
MIN
CONDITIONS
GENERAL CHARACTERISTICS (Ref. Figure 2)
Supply Current
Data Output Leakage
Current
IS
ILD
14
10,11
Amplifier Pin Voltages
ALBO Ports Off Voltage
Note 1: Vs
5,6,7,8
2,3,4
2.4
2.9
0
from Vs
(See Note 1)
= 15V, Vee = 5.35V
AMPLIFIER (Ref. Figure 2, Only Pins 1,9,10... 18 (Connected)
Input Offset Voltage
5&6
Input Bias Current
5&6
0
5
Input Offset Current
5&6
-1
1
Output Offset Voltage
7&8
-50
7&8
30
dB
Vcm ±O.3 V
7&8
7&8
30
2.2
dB
Vcc ± 10
Common Mode
Rejection Ratio
Power Supply
Rejection Ratio
Output Voltage Swing
mV
-50
0
RS =
(See
RS =
(See
RS =
(See
RS =
(See
8.2 kll
Note 1)
8.2 kll
Note 1)
8.2 kll
Note 1)
8.2 kll
Note 1)
V
Note 1: RS = Source Resistance
CLOCK AMPLIFIER (Ref. Figure 2 Disconnect Pin 15 from Pin 16)
Input Offset Voltage
15& 16
Input Bias Current
Max Output Voltage
Min Output Voltage
Max.lMin Output
Voltage Difference
15 & 16
13
13
0.5
6
mV
10
,.AV
0.7
0.7
RS = kll
(See Note 1)
T = 25°C
V
50
mV
1.4
rnA
rnA
kO
..
Notes: 1. RS = Source reSistance, Pm 15 poSItive With respect to Pin 16
2. Pin 15 = Pin 16 = 3.6V
3. Pin 15 = 2.6V, Pin 16 = 3.6V
4. Pin 15 = 4.6V, Pin 16 = 3.6V
5. Calculation only
ALBO (Ref Figura 2)
I
On Current
Drive Current
Resistance Pin 17 to GN
1
I
17
I
3
0.4
35
I
50
I
50
I
70
I
53
I
I V8-V7
V8- V7 = ± 1.75 V
= ±1.75V
Not Powered
DYNAMIC CHARACTERISTICS
AMPLIFIER (Ref. Figure 3)
Ao
Zin
Zout
I
AC Gain at 1 MHz
Input Impedance
Output Impedance
I
5 to 8
5
7,8
I
47
20
I
200
kO
0
I
(See Note 1)
(See Note 2)
Notes: 1. At 1 MHz, AC ground Pins 7 and 8 disconnect 51 0 resistor. Allow for in-circuit R,C
2. At 1 MHz, use Figure 2.
CLOCK AMPLIFIER (ReI. Figure 3)
Ao
BW
AC Gain
- 3 dB Bandwidth
Delay
Output Impedance
Notes: 1. Remove dc offset,
2. Remove dc offset,
3. Remove dc offset,
edge.
4. Remove dc offset,
15,16 to 13
15,16 to 13
15,16 to 13
13
32
10
8
12
200
dB
MHz
ns
0
(See
(See
(See
(See
Note
Note
Note
Note
1)
2)
3)
4)
at 2,048 MHz, Pm 13 = 1 V pk-pk sme wave
Pin 13 = 1 V pk-pk sine wave
Pin 15 = 2 V pk-pk sine wave. Delay from Pin 15 negative-going zero crossover to Pin 13 positive
at 2,048 MHz
1-455
XR·T57·20
SYMBOL
PARAMETERS
PINS
MIN
TYP
MAX
CONDITIONS
UNIT
ALBO (ReI. Figure 2)
2,3,4
Off Impedance
Intermediate Impedance
Difference
On Impedance
Transconductance
Notes: 1.
2.
3.
4.
At
At
At
At
1
1
1
1
MHz,
MHz,
MHz,
MHz,
20
5
25
0.03
2,3,4
2,3,4
7/S to 1
kll
(See Note 1)
M
dB
(See Note 2)
(See Note 3)
(See Note 4)
allow for in·circuit R,C
VS·V7 adjusted for current at Pin 1 = 100pA
VS·V7 adjusted for ± 1.75 V
change in VS·V7 for current at Pin 1 = 10 pA to 100 pA
THRESHOLD VOLTAGES (ReI. Figure 3)
.
ALBO Threshold + ve
ALBO Threshold -ve
ALBO Threshold Difference
Clock Drive on Current
(Peak) +ve
Clock Drive on Current
(Peak) -ve
Clock Drive on Current
Difference
Clock Threshold + ve
Clock Threshold - ve
Clock Threshold Difference
Data Threshold +ve
Data Threshold - ve
Data Threshold Difference
8-7
7·S
-
1.4
1.4
.5
1.5
1.5
0
1.6
1.6
5
V
V
(See Notes 1 & 2)
(See Notes 1 & 2)
(See Note 3)
1S
0.65
1.0
1.4
mA
(See Note 4)
1S
0.65
1.0
1.3
mA
(See Note 5)
-
.5
6S
6S
-5
44
44
-3
0
5
SO
SO
5
48
4S
3
%
%
%
%
%
(See Note 3)
(See Notes 1, 6, S)
(see Notes 1, 7, S)
(See Note 3)
(See Notes 1, S, 9,11)
(See Notes 1, S, 10, 11)
(See Note 3)
8-7
7-S
-
S-7
7-S
-
0
46
46
0
Notes: 1. Pklpk voltage at Pins 7 and S of a 1 MHz sine wave derived through amplifier and measured dlfferenllally
2. Pklpk voltage at Pins 7 and S adjusted for current at Pin 1 = 3 mA .
3. Calculation only
( higher value
)
lower value - 1
x 100 %
percentage difference calculated from
4.
5.
6.
7.
S.
9.
10.
11.
VS-V7 adjusted to ALBO threshold +ve voltage (ref. Pin 16 = 3.6 V)
VrVs adjusted to ALBO threshold -ve voltage (ref. Pin 16 = 3.6 V)
VS-V7 adjusted to peak current at Pin 1S = 1/2 (clock drive on current peak +ve)
VrVs adjusted to peak current at Pin 1S = 1/2 (clock drive on current peak -vel
Figure taken as a percentage of lower ALBO threshold
VS-V7 increased until 1 MHz PRF on counter at Pin 10
VrVs increased until 1 MHz PRF on counter at Pin 11
With 2,04S MHz 2 V pk-pk sine wave to Pin 15 with 180 "H in parallel with 3611 to Pin 16
=
3.6 V
OUTPUT STAGES (ReI. Figure 3. Use 180 "H Inductor between Pins 15 and 16. Apply 2.048 MHz 2V pk/pk to Pin 15.)
tr
tr
tf
tf
tw
tw
Ytw
VOL
VOL
bVOL
Output Pulse Rise
Time +ve
Output Pulse Rise
Time -ve
Output Pulse Fall
Time +ve
Output Pulse Fall
Time -ve
Output Pulse Width + ve
Output Pulse Width - ve
Output Pulse Width
Difference
Buffer Gate Voltage
(low) +ve
Buffer Gate Voltage
(low) -ve
Buffer Gate Voltage
Difference
10
40
ns
10% -90%
11
40
ns
10% to 90%
10
40
ns
10%·90%
40
264
264
ns
ns
ns
10%-90%
at 50%
at 50%
11
10
11
244
244
244
244
-
-10
10
ns
10
0.65
0.95
V
11
0.65
0:95
V
-
-0.15
0.15
V
1-456
XR·T5720
Figure 2. D.C. Parameter Test Circuit
CLOCK
INPUT
Vee
1
27 "
3,3k
O.l/A F
AMPLIFIER INPUT
~
1"...
Figure 3. A.C. Parameter Test ClrcuH
1·457
Vee
XR·T5720
SYMBOL
I
PARAMETERS
I
I
PINS
MIN
I
TYP
I
MAX
I
UNIT
I
CONDITIONS
I
10
I
20
I
ns
I
(See Notes 1... 5)
SAMPLE PULSE WIDTH (Ref. Figure 4. Cy = 27 pF)
I
Sample Pulse Width
I
-
I
Notes: 1. The sample pulse width IS the period dUring which the output latches are opened to accept a signal above the data
threshold at Pin 7 or 8 and cause a half·width output pulse at Pin 11 or 10 respectively.
2. Sample. pulse width is specified with a 2.048 MHz TIL waveform at clock input (Pin 15) and a 2.400 MHz Schottky TL
waveform at amplifier input in the circuit of Figure 5. Figure 7 shows the relevant IC waveforms.
3. Monitor the frequency of coincident output pulses at Pins 10 and 11 either directly or through output circuit to
frequency counter.
4. Sample pulse width = Xns + (0.1 x measured frequency in kHz ns where X is the mean rise/fall times of the
waveform at Pin 8 between 25% and 75%.
5. X to be within the range 10 ns < X < 12 ns. This requires HF layout techniques with the amplifier operated closed
loop.
SAMPLE PULSE GENERATOR INPUT WAVEFORM (Pin 12 ReI. Figure 4, Cy = 40 pF)
I Output Pulse Frequency I
10,11
I
1,024
-100 ppm
I
1,024
I
1,024
+100 ppm
I
MHz
I (See Note 1)
Notes: 1. Width 2.048 MHz ± 100 ppm TIL waveform at clock input with half of above waveform frequence at amplifier input.
2. Sample pulse width is specified with a 2,048 MHz TIL waveform at clock input (Pin 15) and a 2,400 MHz Schottky TL
waveform at amplifier input in the circuit of Figure 5. Figure 7 shows the relevant IC waveforms.
CLOCK
INPUT
36
!Ol~F
130
3'"
3.9k
AMPLIFIER INPUT
e--.tV\I'.._ -..........
* *
Figure 4. Sampling Pulse Test Circuit
1·458
130
XR·T5720
TYPICAL AT 5.1V AND AT 25°C
180
120
GAIN (dB)
20
PHASE
(DEGREES)
I-
60
10 I-
-60
2
3
6
4
8 10
2
3
4
6
8100
3
2
4
FREQUENCY (MHz)
Figure 5. Typical and Limiting Values of Gain and Phase
INPUT WAVEFORMS
+204V
CLOCK liP 2.048 MHz
+Oo4V
+204V
AMPLIFIER liP 20400 MHz
+Oo4V
IC WAVEFORMS
SAMPLE PULSE (INTERNAl!
PIN 8
+5.1V
PIN 10
+0.7V TYP.
+5.1V
PIN 11
+0.7V TYP.
NOTE
COINCIDENT OUTPUT PULSES
Figure 6.
Ie Waveforms
for Measuring Sampling Pulse Width
1·459
XR·T5740
PCM AMI Line Receiver and
Clock Recovery Circuit
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-T5740 is a monolithic bipolar IC designed for T1
line receiver application operating at 1.544 M bit/so It
provides all the active circuitry required to perform automatic line build out (ALBO), threshold detection,
binary NRZ data and clock recovery as the XR-T5640
but with a crystal filter instead of a LC tank circuit.
ALBO GROUND
ANALOG GROUND
SUBSTRATE GAOUND
ALBO
A clock recovery using an LC filter circuit version of the
XR-T5740 is also available as the XR-T5640.
PORT 1
ALSD
PORT 2
CLOCK
AMPLIFIER
INPUT
ALBO
Clock Recovery using Crystal Filter
On-chip NRZ Data and Clock Recovery Circuitry
Less than 10 ns Sampling Pulse Over the Operating
Range
Triple Matched ALBO Ports
Single 5.1 V Power Supply
DRivE
ALSO
CONTROL
PO AT 3
FEATURES
CLOCK
CLOCK
AMPLIFIER
INPUT
-ve
AMPLIFIER
INPUT
'cc
AMPLIFIER
+ve INPUT
OUTPUT
AMPLIFIER
-VE OUTPUT
CLOCK
PHASE SHIFTED
CLOCK INPUT
AMPLIFIER
+ VE OUTPUT
GROUND
NRlDATA
APPLICATIONS
T1 PCM Line Receiver
T1C PCM Line Receiver (requires external gain)
General Purpose Bipolar Line Receiver
SYSTEM DESCRIPTION
The XR-T5740 is designed as a receiver for interfacing
T1 PCM carrier lines on plastic or pulp insulated
cables. It can also be used as a general purpose alternate mark inversion (AMI) receiver.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
- 65°C to + 150°C
Operating Temperature
- 40°C to + 85°C
- 0.5 to + 10V
Supply Voltage
Supply Voltage Surge (10 ms only)
+25V
Input Voltage (except Pins 2,3.4,17)
- 0.5 to + 7V
Input Voltage (Pins 2,3.4,17)
- 0.5 to + 0.5V
Data and Clock Output Voltage
- 0.5 to 20V
Voltage Sure (Pins 5,6,10,11) (10 ms only)
+50V
The XR-T5740 is a modified version of XR-T5720 PCM
repeater IC. It contains all the active circuitry needed
to build a T1 receiver for interfacing up to 6300 ft. The
preamplifier, the clock amplifier, threshold detectors,
ALBO port, data latches and output drivers are similar
to the ones on XR-T5720. Clock extraction is done by
means of a crystal filter circuit.
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-T5740
Ceramic
-40°C to +85°C
Bipolar + 1 and - 1 pulses are combined within the IC
to form a binary non-return to zero PCM signal at Pin
10. A synchronous clock signal is made available at
Pin 11. Both outputs have open collector transistors.
1-460
XR·T5740
ELECTRICAL CHARACTERISTICS
Test Conditions: TA
= 25°C, VCC = 5.1
PARAMETERS
Supply Current
Clock & Data Output Leakage Current
Amplifier Pin Voltages
Amplifier Output Voltage Swing
Amplifier Output Offset Voltage
Amplifier Input Bias Current
ALBO on Current
Drive Current
V ± 5%
MIN
2.4
2.2
-50
TYP
MAX
UNIT
22
0
2.9
30
100
3.4
ALBO Off
Vfull-up = 15V
A Unity DC Gain
0
50
5
mA
p.A
V
V
mV
p.A
mA
mA
Open Loop
200
dB
kO
0
Open Loop
200
dB
MHz
ns
0
25
kO
0
3
1
CONDITIONS
Rs = 8.2 kO
AC CHARACTERISTICS
Pre-Amplifier
AC Gain at 1 MHz
Input Impedance
Output Impedance
Clock Amplifier
AC Gain
- 3 dB Bandwidth
Delay
Output Impedance
50
20
32
10
10
ALBO
Off Inpedance
On Impedance
20
CLOCK DATA OUTPUT BUFFERS
RL = 1300, Vpull- up =
5.1V ± 5%
Rise Time
Fall Time
Output Pulse Width
Sample Pulse Width
VOL
IL sink
ns
ns
ns
ns
V
mA
30
30
244
10
0.7
35
THRESHOLDS
ALBO
Clock Drive Current Peak
Clock Thresholds
% of ALBO
Data Threshold
%of ALBO
1.4
1.5
1.0
63
40
46
1-461
1.6
V
mA
75
%
52
%
At Vo = VALBO Threshold
XR·T5750
PCM Line Receiver and
Clock Recovery Circuit
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
The XR-T5750 is a monolithic bipolar IC designed for
PCM type line receiver applications operating at T1,
T148C, T1 C and 2 M bitls data rates. It provides all the
active circuitry required to perform automatic line build
out (ALBO), threshold detection, positive and negative
data and clock recovery using a crystal filter.
ALBO
GNP
SUBSTRATE
GNO
ALBO
PORT 1
ALBO
PORT 2
Clock recovery using an LC tank circuit instead of a
crystal filter is also available as XR-T5650.
PREAMPLIFIER
·\lE INPtlT
PREAMPLIFIER
FEATURES
"VE INPUT
On Chip Positive and Negative Data, Clock Recovery
Less than 10 ns Sampling Pulse over the Operating
Range
Double Matched ALBO Ports
Single 5.1 V Power Supply
2 M Bills Capability
Clock Recovery using Crystal Filter
CLOCK
DRIVE
ALBO
CONTROL
CLOCK
AMPLIFIER
INPUT
CLOCK
AMPLIFIER
INPUT
Vee
PREAMPLIFIER
\IE OUTPut
CLOCK
aUTPU"T
PREAMPLIFIER
SHIFTED
CLOCK
F'HASE
"VE OUTPUT
INPUT
DIGITAL
GROUND
~,
DRIVER
APPLICATIONS
SYSTEM DESCRIPTION
T1 PCM Line Receiver
T148C Line Receiver
T1C PCM Line Receiver (requires external amplifier)
General Purpose Bipolar Line Receiver
HD83 Line Receiver
B8ZS Line Receiver
The XR-T5750 is designed for interfacing T1, T148C
and 2 Mbills PCM carrier lines on plastic or pulp insulated cables. It can also be used at T1 Crate (3.152 M
bitls) with external gain. Since it outputs plus and minus
ones on a bipolar pulse stream together with the clock,
it can be used to interface systems having different line
codes like AMI, AMI-B8ZS or AMI-HDB3.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
- 65°C to + 150°C
Operating Temperature
- 40° to + 85°C
Supply Voltage
-0.5 to +10V
Supply Voltage Surge (10 ms)
+25V
Input Voltage (except Pins 2,3.4,17)
-0.5 to 7V
Input Voltage (Pins 2,3.4,17)
-0.5 to +0.5V
Data Output Voltage (Pins 10,11)
20V
Voltage Surge (Pins 5,6,10,11) (10 msec only)
50V
The XR-5750 is a modified version of XR-T5720 PCM repeater IC. It contains all the active circuitry needed to·
build a PCM line receiver up to 6300 ft cable length.
The preamplifier, the clock amplifier, threshold detectors, data latchs and output drivers are similar to the
ones on XR-T5720. Clock extraction is done by means
of a crystal filter circuit.
In addition to plus and minus one outputs, a synchronous clock signal is made available at Pin 11 by deleting one of the ALBO ports on XR-T5720 thus leaving
two matched ALBO ports. All outputs have high current
open collector transistors.
ORDERING INFORMATION
Part Number
Package
Operating Temperature
XR-T5750
Ceramic
- 40°C to 85°C
1-462
XR·T5750
ELECTRICAL CHARACTERISTICS
Test Conditions: VCC
= 5.1V,
± 5 %, TA
PARAMETERS
Supply Current
Clock & Data Output
Output Leakage Current
Amplifier Pin Voltages
Amplifier Output
Offset Voltage
Voltage Swing
Amplifier Input
Bias Current
ALBO on Current
Drive Current
= 25°C, unless otherwise specified.
MIN
2.4
-50
2.2
TYP
MAX
UNIT
24
30
mA
0
2.9
100
3.4
p.
V
0
50
mV
V
5
p.A
mA
mA
3
1
CONDITIONS
ALBO Off
Vpull- uB = 15 V
A DC nity Gain
Rs = 8.2 kO
Measured Differentially
from Pin 7 to Pin 6
AC CHARACTERISTICS
Pre-Amplifier
AC Gain at 1 MHz
Input Impedance
Output Impedance
Clock Amplifier
AC Gain
- 3 dB Bandwidth
Delay
Output Impedance
ALBO
Off Impedance
On Impedance
200
dB
kO
0
200
dB
MHz
ns
0
25
kO
0
50
20
32
10
10
20
RL = 1300, Vpull-up
5.1 V ± 5%
CLOCK DATA OUTPUT BUFFERS
Rise Time
Fall Time
Output Pulse Width
Sample Pulse Width
VOL
IL sink
THRESHOLDS
ALBO
Clock Drive Current Peak
ns
ns
ns
ns
V
mA
30
30
244
10
0.7
35
1.4
1.5
1.0
1.6
V
mA
63
68
75
%
40
46
52
%
CLOCK THRESHOLD
% of ALBO
DATA THRESHOLD
% of ALBO
=
1-463
At Vo
= VALBO Threshold
XR·T5760
Low Power T1, T148C & 2 M Bit/s Repeater
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The XR-T5760 is a low power version of the XR-T5700
repeater circuit for T1 carrier system operating at
1.544 M bitls (T1), European 2 M bitls or 2.37 M bitls
(T148C). It provides all of the active circuitry required
for one side of a PCM repeater and also has the cability
of clock extraction using a crystal filter.
ALBO GROUND
ANALOG GROUND
SUBSTRATE GROUND
ALBO
Clock recovery using an LC tank circuit instead of a
crystal filter is also available as XR-T5660.
ALBO
PORT 2
CLOCK
AMPLIFIER
INPUT
ALBO
PORT 3
CLOCK
AMPLIFIER
INPUT
Storage Temperature
-65°C to +150C
-40°C to +85°C
Operating Temperature
Supply Voltage
-0.5 to + 10V
+25V
Supply Voltage Surge (10 ms)
Input Voltage (except Pins 2,3,4,17)
-0.5 to 7V
Input Voltage (Pins 2,3,4,17)
- 0.5 to + 0.5V
Data Output Voltage (Pins 10,11)
20V
50V
Voltage Surge (Pins 5,6,10,11) (10 msec only)
Package
Operating Temperature
- 40°C to + 85°C
PHASE SHIFTED
CLOCK INPUT
AMPLIFIER
+VE OUTPUT
OUTPUT
-\IE DATA
+VE DATA
OUTPUT
Timing information is contained in the incoming pulse
stream. This signal is full wave rectified and applied to
a crystal filter circuit to extract the clock signal at the
data rate. The clock signal is amplified and phase
shifted between Pins 13 and 12 to obtain 90° phase
shift by means of an R-L-C circuit.
ORDERING INFORMATION
Ceramic
AMPLIFIER
-VE OUTPUT
OUTPUT
Bipolar PCM signal is attenuated and dispersed in time
as it travels along the transmission cable, characteristics of which vary with length, frequency, temperature
and humidity. The PCM signal when received is amplified, equalized for amplitude characteristics and reconstructed by the preamplifier, automatic line build out
(ALBO), clock and data threshold circuits. Amplitude
equalization is achieved through shaping the frequency
spectrum with the help of variable impedance ALBO
ports.
ABSOLUTE MAXIMUM RATINGS
Part Number
AMPLIFIER
+VE INPUT
peater IC. It contains all the active circuitry to implement one side of a PCM, repeater operating on either
pulp or plastic insulated cables. Repeater to repeater
spacing on either type of cable is 6300 ft. max.
T1 PCM Repeater
T148C PCM Repeater
European 2 M Bitls PCM Repeater
T1C PCM Repeater (requires external preamplifier)
XR-T5760
Vee
CLOCK
GROUND
APPLICATIONS
ALBO
CONTROL
AMPLIFIER
Low Power
Crystal Filter Clock Extraction
Single 5.1 V Power Supply
Less than 10 ns Sampling Pulse Over the Operating
Range
Triple Matched Automatic Line Build-out (ALBO) Ports
2 M Bitls Capability
CLOCK
DRIVE
PORT 1
-VE INPUT
FEATURES
- .............
SYSTEM DESCRIPTION
Data is sampled and stored in the output data latches
by an internally generated sampling pulse. Buffer drivers are then enabled to produce precisely timed output
pulses whose width and time of occurence are controlled by the regenerated clock.
The XR-T5760 is a monolithic bipolar PCM repeater IC
operating at 1.544 (T1), 2.048 and 2.37 (T148C) M bitsl
sec. It is the low power version of XR-T5720 PCM re1-464
XR·T5760
ELECTRICAL CHARACTERISTICS
Tast Conditions: VCC = 5.1 V ± 5%, TA = 25°C, unless specified otherwise.
PARAMETERS
Supply Current
Clock and Data Output
Output Leakeage Current
Amplifier Pin Voltages
Amplifier Output
Offset Voltage
Voltage Swing
Amplifier Input
Bias Current
ALBO on Current
Drive Current
MIN
2.4
-50
2.2
TYP
MAX
UNIT
14
mA
ALBO Off
0
2.9
100
3.4
p.A
V
Vrull- uB = 15 V
A DC nity Gain
0
50
mV
V
Rs = 8.2 kO
Measured Differentially
from Pin 8 to Pin 7
5
p.A
mA
mA
3
1
CONDITIONS
AC CHARACTERISTICS
Pre-Amplifier
AC Gain at 1 MHz
Input Impedance
Output Impedance
Clock Amplifier
AC Gain
- 3 dB Bandwidth
Delay
Output Impedance
ALBO
Off Impedance
On Impedance
200
dB
kO
0
200
dB
MHz
ns
0
25
kO
0
50
20
32
10
10
20
DATA OUTPUT BUFFERS
RL = 1300, Vpull-up =
5.1 V ±5%
Rise Time
Fall Time
Output Pulse Width
Sample Pulse Width
VOL
IL sink
30
30
244
10
0.7
35
ns
ns
ns
ns
V
mA
THRESHOLDS
ALBO
Clock Drive Current Peak
1.4
1.5
1.0
1.6
V
mA
63
68
75
%
40
46
52
%
CLOCK THRESHOLD
% of ALBO
DATA THRESHOLD
% of ALBO
1-465
At Vo =VALBOThreshold
Custom/Semi-Custom Products
CUSTOM/SEMI-CUSTOM PRODUCTS
Semi-Custom Design Concept .................................................................. 2-2
Answers to Frequently Asked Questions ....................................................... 2-5
Economics of Semi-Custom Design ............................................................ 2-6
Converting Semi-Custom to Full Custom ....................................................... 2-7
Full Custom Development ................................................................... 2-8
Testing of Semi-Custom IC's ................................................................. 2-10
Linear Semi-Custom Design ................................................................... 2-11
XR-A100 Master-Chip ...................................................................... 2-13
XR-B100 Master-Chip ...................................................................... 2-14
XR-C100A Master-Chip ............................... " .................................... 2-15
XR-D100 Master-Chip ............................................... " ..................... 2-16
XR-E100 Master-Chip ...................................................................... 2-17
XR-F100 Master-Chip ...................................................................... 2-18
XR-G100 Master-Chip ...................................................................... 2-19
XR-H100 Master-Chip ...................................................................... 2-20
XR-J100 Master-Chip ...................................................................... 2-21
XR-L1 00 Master-Chip ...................................................................... 2-22
XR-M100 Master-Chip ..................................................................... 2-23
XR-U100 Master-Chip .................................................................... 2-24
XR-V100 Master-Chip ...................................................................... 2-25
XR-W10o Master-Chip ..................................................................... 2-26
XR-X100 Master-Chip ...................................................................... 2-27
XR-40o 12L Master-Chip .................................................................... 2-28
Linear Semi-Custom Design Cycle ............................................................ 2-29
Electrical Characteristics of Linear Master-Chip Components ....................................... 2-35
12L Semi-Custom Design ..................................................................... 2-36
Features of 12L Technology .................................................................. 2-36
Designing with 12L Master-Chip .............................................................. 2-37
XR-20o 12L Master-Chip .................................................................... 2-42
XR-300 12L Master-Chip .................................................................... 2-43
XR-400 12L Master-Chip .................................................................... 2-44
XR-500 12L Master-Chip .................................................................... 2-45
12L Design Kit ............................................................................ 2-47
XR-C409 12L Evaluation Circuit .............................................................. 2-49
Electrical Characteristics of 12L Master-Chip .................................................... 2-51
CMOS Semi-Custom Design and Features ........................................................ 2-52
CMOS Semi-Custom Design Cycle ............................................................ 2-53
Electrical Characteristics of CMOS Master-Chips ................................................. 2-54
Designing with CMOS Master-Chips ........................................................... 2-55
XR-CMA Master-Chip ...................................................................... 2-57
XR-CMB Master-Chip ...................................................................... 2-58
XR-CMC Master-Chip ...................................................................... 2-59
XR-CMD Master-Chip ...................................................................... 2-60
2·1
SEMI-CUSTOM DESIGN CONCEPT
tive or cooperative development effort between Exar
and the customer. In most cases, the cost and development time for the program can be reduced even further,
if the customer does the design and breadboarding of
his own semi-custom IC, using Exar Design Kits, instruction manuals and layout sheets.
Traditionally, the development of custom IC's has been
a long and costly undertaking. The development time
would normally run in excess of one year, design
changes are slow and costly, and it may take a long
time to get from the prototype stage to full production.
Because of these difficulties, the use of custom IC's
could be economically justified only when a very large
quantity of circuits, i.e., several hundred-thousand
units, were required during the life of the end product.
In the past, these drawbacks have severely limited the
use of custom monolithic IC's.
The semi-custom design approach is based on a number of standardized IC chips with fixed component locations. These standardized IC chips, called MasterChips, contain a large number of undedicated active
and passive components (i.e., transistors, resistors,
logic gates, etc.). These integrated components can be
interconnected in thousands ·of different ways with a
customizing interconnection pattern. Each different
metal interconnection pattern creates a new custom IC.
The figures below show the magnified photograph of a
Master-Chip, both in its prefabricated form and after its
customization with a special interconnection pattern.
This method is called semi-custom rather than full custom, since only the last layer of tooling is changed to
customize an IC chip, and rest of the layers are standard. As a result, the development phase is very short,
far less expensive and risk free, compared to conventional full or dedicated custom IC's. Similarly, if a design
change or iteration is necessary, it can be readily accommodated within a matter of weeks by simply generating a new or modified interconnection pattern.
The semi-custom design concept, pioneered by Exar,
now overcomes this traditional problem. Exar makes
this possible by stocking wafers that are completely
fabricated except for the final process step of device interconnection which metalizes all selected components together in the required circuit configuration. This
enables an engineer to deSign a metal mask based on
his circuit which will interconnect the uncommitted
components on the prefabricated wafers, and thus convert them into customized chips corresponding to the
customer's design. This unique method of IC design
and development allows one to develop an almost unlimited variety of custom linear or digital integrated circuits at very substantial cost savings.
The semi-custom program is intended for those customers seeking cost effective methods of reducing
component count and board size in order to compete
more effectively in a changing marketplace. The program allows a customized monolithic IC to be developed with a turnaround time of several weeks, at approximately 10% to 20% of the development costs for
tooling associated with the conventional full custom designs. The semi-custom design concept is an interac-
Exar offers a wide choice of Master-Chips for linear and
digital semi-custom design. Presently, Master-Chips are
available in linear bipolar, linear compatible 12L and
CMOS technologies. Additional chips are under development for a variety of special applications. The details
of each of the presently available chips are discussed
in the later section of this book.
Magnified Photograph of a Unear Master-Chip Before and After Customizing
2-2
DESIGN KITS
tomer and is essential to the success of the program. It
avoids any possible design pitfalls or misunderstandings. This early interaction also allows you to find out
some of the options or variations available in Exar's
semi-custom programs and choose the one which is
best suited to your needs.
Exar offers three Design Kits: One for linear bipolar, one
for 12L and one for CMOS. Since the general approach
to semi-custom design is the same as that for full custom, thes.e design kits are valuable tools for both full
custom and semi-custom design work. This is especially true in the case of linear design. Each of these kits
contain a comprehensive design manual, a set of semicustom layout sheets and a P.C. board, IC sockets and
other hardware for building your breadboard. The only
active components in these kits, that are meant for use
in breadboarding, are the transistor arrays found in the
linear bipolar and 12L design kits. The logic blocks
found in the 12L design kit is meant to be used for process evaluation. Digital breadboarding can be done using the appropriate logic family such as 74LXX, 74CXX
or 4XXX. The kits are designed so that an engineer,
armed only with a background in discrete design, a calculator and a pencil, can design his own customized integrated circuit. The technical material is presented in
a straight forward, no-nonsense format with iots of illustrative figures and all of the pertinent equations.
The following is required by Exar's technical staff to provide you with an accurate feasibility study of your project. and a budgetary estimate of the development
costs, timetables and production pricing.
• A block diagram of circuit function and input/output
interface requirements.
• A circuit schematic or logic diagram of your circuit.
• Preliminary or objective performance specifications
and limits on critical circuit parameters (also possible
tradeoffs which may be allowed).
• Types of electrical testing required for production
units (i.e., ac or dc parametric testing, functional testing, etc.).
After the circuit is designed, and before it is breadboarded, it is recommended that the customer send
Exar a schematic and a circuit description for an engineering evaluation. Normally, there is no charge for
such an evaluation. Exar has successfully completed
well over 850 custom design programs and our experience can provide valuable guidelines. Exar's Applications Engineering department is ready and able to help
our semi-custom design program customers in both the
breadboard and layout stage. We can provide immediate answers to your circuit design or testing questions,
and speed your custom design on its way.
• Packaging requirements.
• Production quantity requirements.
• Desired development and production timetables.
• An indication of how much of the breadboarding, layout, etc., can be done by you, the customer, using
Exar's Design Kits or standard logic blocks (74LXX,
74CXX or 4XXX).
YOUR FIRST STEP
Once the above data package is submitted to Exar, we
would review it and respond to you within a few days.
Your very first step, at the start of a semi-custom program, should be to contact Exar for a preliminary analysis and discussion of your needs. This can be done
even while the program is still at the thought stage. This
initial review by Exar is performed at no cost to the cus-
Normally, the test system development effort is initiated
in parallel with chip development. Exar has a complete
computer controlled IC test facility and offers complete
IC testing capability for production units.
CUSTOMER
METAL
LAVOUT
MASK
Steps 01 Semi-Custom DeSign
2-3
FINISHED
CHIP
WHAT PACKAGE TYPES ARE AVAILABLE?
WHAT IF MY PRODUCTION REQUIREMENTS
EXCEED MY INITIAL EXPECTATIONS?
All semi-custom IC's are available in dual-in-line (DIP)
packages. Commercial grade units are normally packaged in plastic DIP packages. Exar offers a wide selection of such packages, in 8-,14·, 16-, 18-, 20-, 22-, 24-,
28- and 40'pin versions. The industrial or military grade
products requiring hermetic packaging are available in
frit-seal ceramic packages (CERDIP). Other packages,
such as molded plastic flat packs, single-in-line (SIP),
small-outline (S.D.) packages and lead less carriers, are
also available. All of the packaged units are subjected
to Exar's stringent quality assurance specifications prior to shipment.
Using the semi-custom IC, it is not unusual for an end
product to be extremely successful in a very short time.
In that case, the anticipated volume of the custom IC
may jump from a few thousand units to several hundred
thousand units. When this happens, Exar can quickly
convert your semi-custom design to a full custom chip
and make it much more cost effective for you. Translating a semi-custom design to a full custom IC is a very
simple, trouble free step which can normally be done in
less than six months, and at a modest cost.
CAN EXAR SUPPLY CHIPS?
IS THERE A SECOND SOURCE FOR
SEMI-CUSTOM IC's?
All of Exar's semi-custom products can also be supplied in chip fonn for hybird assemblies. A detailed description of the electrical specifications, visual inspec·
tion criteria, and the handling and shipping options
available for monolithic chips is given in a later section
of this book.
In most high volume production applications of IC's the
customer often requires more than one supplier of a
given IC. Anticipating this alternate source requirement, Exar has made contractual agreements with other IC manufacturers to provide a second source for
Exar's semi-custom IC's.
CAN EXAR DO ENVIRONMENTAL SCREENING?
In certain cases, where a critical supply situation may
exist, Exar can also provide a special bonded inventory
of parts, either in chip form or in packaged form, by prior arrangement with the customer.
Exar has complete burn-in, environmental test and
screening services available for temperature stressing,
thermal shock or humidity and hermeticity tests. For a
detailed analysis of your needs, consult Exar's Market·
ing department.
START
Circuit Function
and Specs
Finalized by
Customer
r--
Semi-Custom
Fusibility
Study
r---
Preliminary
eost Estimate
Initial
Production
Pricing
t---
Pencil
r--
Layout
Construction
and Evaluation
*
**
'--
t---
Mask
*
r--
Computer
Simulation
Mask
Tooling
r--
* *These steps mUlt be done by Ex.ar.
FLOW CHART OF TYPICAL SEMI-CUSTOM DEVELOPMENT
2·4
..
FInish
r--
**
Prototype
Evaluation
by Customer
*"these steps are not done by Exar they should be done ,n consultation with Exar.
Prototype
WeIer
Fabrication
*
*
r--
*
*
t---
or Digitizing
t----
*
Breadboard
Design
Review
Circuit
Design
**
*
r--
r----
r--
Prototype
Test and
Assembly
t----
**
FREQUENTLY ASKED QUESTIDNS
AND THEIR ANSWERS
Typical costs of additional design cycles are $2,000 to
$4,500 for bipolar and CMOS designs and $3,500 to
$5,000 for 12L designs. These costs also include the additional prototypes supplied at the completion of the design iteration cycle.
Based on our long experience with Exar's semi-custom
Master-Chips, we have compiled a comprehensive
glossary of the most often asked questions concerning
the program. The following is a list of these questions
and their answers.
WHAT ABOUT PRODUCTION PRICING?
WHAT IS THE COST OF THE BASIC PROGRAM?
The production pricing of monolithic IC's depends upon
a number of important factors such as:
The cost of the semi-custom development program depends on how much of the design and layout is done by
the customer. In general, the basic semi-custom program is where the customer does the design, breadboard evaluation and pencil layout on the Master-Chip
worksheet; and Exar does only the IC tooling and prototype fabrication. This is the most economical and cost
effective approach.
a) Master-Chip type.
b) Circuit complexity (i.e., yield).
c) Device performance and test requirements.
d) Special environmental screening requirements
(burn-in, hermeticity tests, etc.).
For bipolar semi-custom designs, the development cost
of the basic program is in the range of $3,500 to
$6,000, starting with an accurate layout supplied by the
customer. The above prices also include the cost of 50
monolithic prototypes delivered at the completion of the
program. Additional prototypes are available at a nominal cost, in minimum lots of 200 units.
e) Package type required.
In the case of a custom IC, it is impossible to anticipate
the impact of these factors without detailed knowledge
about the circuit and its application. Each custom IC,
by definition, has some unique requirement or feature
associated with it. After reviewing your specific needs,
particularly with regard to the circuit performance and
quality requirements, Exar can provide you with a detailed proposal outlining the development costs and
production pricing for your particular circuit.
In the case of 12L or CMOS semi-custom designs, the
basic development program costs are in the range of
$4,200 to $8,500, depending on the layout complexity
and the particular Master-Chip used. This development
cost also includes 25 monolithic prototypes. Additional
prototypes are available at a nominal cost, in minimum
lots of 200 units each.
WHAT ABOUT THE TESTING OF SEMI-CUSTOM IC's?
Exar will develop test software and fixtures to provide
fully tested production IC's. All production devices receive 100% electrical test and screening to a mutually
agreed upon device specification. In addition to the
complete electrical testing, all of the production devices are screened by Exar's Quality Assurance department to assure compliance with the agreed upon Acceptable Quality Level (AQL) standards.
WHAT IS THE DEVELOPMENT TIME?
Typical development time for the basic bipolar semicustom program is four to six weeks, starting with the
customer's pencil layout and ending with the monolithic
prototypes. If Exar is required to do the IC layout or
breadboard evaluation, several additional weeks may
be required to complete the development program.
In the case of 12L or CMOS semi-custom development
programs, the typical development time is eight to ten
weeks, starting with the pencil layout of the MasterChip worksheet. The 12L semi-custom program takes
slightly longer than bipolar or CMOS because it requires three layers of custom tooling, rather than one,
to customize a prefabricated Master-Chip.
There is normally a nonrecurring engineering charge
associated with this test system generation. This covers the cost of the test fixture and computer software
development. Depending on the complexity of the test
requirements, this test engineering charge is normally
in the range of $800 to $1,250.
Exar can perform two basic types of tests for production IC's: (1) parametriC testing which measures a specific parameter value (normally current or voltage) and
compares it against pre-established limits; (2) functional testing which applies a series of operating conditions
and compares the circuit under test with a known good
device. These two types of tests can be performed both
as steady state (dc) or dynamic (ac) measurements.
WHAT IF ADDITIONAL DESIGN CYCLES ARE NEEDED?
If the customer desires to modify the design or layout
after evaluation of the initial prototypes, a new design iteration cycle can be completed within five weeks for
the bipolar and CMOS designs, and within eight to ten
weeks for the 12L designs.
2-5
ECONOMICS OF SEMI-CUSTOM DESIGN
In developing either linear or digital custom circuits,
one is always confronted with the following key question: for a given product type and production requirement, is it cheaper to develop a semi-custom or full
custom IC? Since the functional requirements of each
custom IC program vary greatly, there is no general answer to the above question. However, based on Exar's
long experience in both full and semi-custom IC design
and depending on the overall production requirements,
it is possible to establish some sound economic guidelines for choosing the most cost effective approach.
priced at $3.20 each, at the same 50,000 production
level. Then, its amortized per unit price will be $3.30, or
approximately 20% cheaper than a full custom.
The figure below gives a comparative graph of the amortized unit price for a typical full custom deSign, along
with the equivalent in semi-custom form for various production quantities. For comparison purposes, the relative ratio of the amortized unit price is plotted along the
vertical axis. If this ratio. is greater than 1.0 then the
semi-custom method is the more cost effective solution.
COST FACTORS INVOLVED
NO TWO IC's ARE THE SAME
Any custom IC development, whether full or semicustom, involves similar types of cost factors. These
are:
By definition, each custom IC type is unique. Therefore,
the cost comparison curve given below is shown as a
spread rather than a single line. This is because, in addition to the production quantity, the cost of monolithic
IC's also depends on the circuit complexity, special test
requirements and the IC package type.
1. Non recurring engineering (NRE) or development
costs.
2. Cost or unit price of the product in production quantities.
The key information contained in the relative cost vs.
quantity figure can be summarized as follows:
In the case of monolithic IC's, particularly those which
have relatively limited production volume, the development costs may be a significant factor in the cost of the
end product. Therefore, when discussing the economics of custom IC's for medium to low production
quantities, it is best to consider the cost tradeoffs in
terms of the amortized unit price of the IC at a given
production volume. This amortized unit price is defined
as the actual cost of each unit including its share of the
development cost. As an example, a full custom IC may
cost $50,000 to develop and may be priced at $2.90
each at a 50,000 piece total production level. Then, its
true amortized unit price including development costs
will be $2.90 plus $1.00, or $3.90. Similarly, an equivalent semi-custom IC may cost $5,000 to develop and be
1. For a total production requirement of 50,000 pieces
or less, the semi-custom approach is definitely the
most economical.
2. For a production requirement of 200,000 pieces or
more, the. full custom deSign is more cost effective.
3. For production quantity requirements in the 50,000
to 200,000 piece range, the crossover point for the
most economical approach will depend strongly on
the specifics of a particular IC function; i.e., its special test, environmental screening, and package requirements.
3.0
IiI
..5'I·
2.0
U
c~
1.01-----4-----+-----+=:::!!
lk
3k
10k
30k
lOOk
300k
Tolal Qu.n'lty oIIC·. Purch._ (In 'hou. .nd.)
TYPICAL COST VS QUANTITY COMPARISON OF FULL CUSTOM AND SEMI-CUSTOM DESIGNS
2-6
l000k
CONVERTING SEMI-CUSTOM TO FULL CUSTOM
Exar can offer you the combined advantages of semicustom and full custom design programs. This is because Exar has a complete semiconductor manufacturing facilities. This unique capability allows Exar to state
a custom development program using a combination of
semi-custom Master-Chips during the initial phases of a
customer's product, taking full advantage of the low
tooling cost and short development cycle. As the product matures and its market expands (resulting in higher
volume production run rates) Exar can convert the mUltiple semi-custom chip approach into a single custom
IC, thus achieving a cost reduction and in many cases
a performance improvement. The significant advantage
of this type of program is that the risk associated with a
custom development is greatly reduced. The Ie design
approach has been proven, production "bugs" are out
of the product and your production line continues to
flow during the full custom chip development. Once the
custom chip is completely characterized and found acceptable, the semi-custom IC system in your product
can be phased out while the full custom IC is being
phased in.
In this manner, the customer has the best of both
worlds with the combination of these two technologies.
The quick turnaround advantage of semi-custom
Master-Chips provide prototypes and initial production
units, while the subsequent full custom design provides
cost savings at high volume production. During this
transition, the customer is assured of a continuous flow
of product through its production line.
In such a two-step development, the semi-custom prototypes often serve as a monolithic breadboard to optimize and debug the final design. This allows design iterations or changes to be made quickly and inexpensively. In fact, the only difference between the semi-custom
and full custom chip is the actual size of the silicon
chip.
Once the design is satisfactory, conversion of a semicustom to a full custom chip is very straight forward
and relatively risk free. We simply remove the unused
electrical components from the chip to reduce the chip
size and pass the resulting cost savings on to you in the
form of a reduced unit price.
SEMI- AND FULL CUSTOM COMBINATION:
THE TWO-STEP DEVELOPMENT
The two-step development capability; i.e., start as semicustom and finish as full custom, is a very powerful design technique. It avoids the risks associated with a
conventional black box type of custom design where
one does not know until the very last day of development whether the circuit works or if it can be manufactured.
In many custom development programs one is faced
with very short development times and a rapid transfer
into high volume production. Such a requirement does
not leave room for lengthy development and design
change or iteration cycles associated with conventional
full custom IC design.
The two-step program is faster and less expensive than
the conventional full custom development, since it
avoids costly and lengthy design iteration or modification cycles for a full custom IC. In addition, it gives the
customer a very high degree of assurance that the final
full custom unit will work the first time.
Exar combines full and semi-custom design capabilities, and a complete wafer fabrication facility under one
roof, therefore, providing a unique solution to this problem; initially developing the prototypes in a semicustom form, and then converting them to full custom.
SEMI-CUSTOM DESIGN AND ITS FULL CUSTOM EQUIVALENT
2-7
FULL CUSTOM DEVELOPMENT
Exar offers a complete design and production capability
for full custom IC development This provides an excellent complement to Exar's unique semi-custom capability. Exar's full custom IC development and production
capabilities offer complete flexibility to meet changing
customer needs or design problems. We can develop a
complete custom IC starting from your black box specifications, or reduce your working breadboard prototype
to a monolithic chip. Alternately, if you have the facilities and resources to do the IC design and layout, Exar
will provide you with the device characteristics and IC
layout rules for the particular process suitable to your
design and review your IC layout for you. Then, Exar
can generate the IC tooling and fabricate your IC prototypes.
els, operating frequency, timing diagrams, input/
output impedances, power dissipation, etc.
5. Production requirements and the desired development timetable.
6. Packaging requirements.
7. Level of screening required.
IC FABRICATION FROM CUSTOMER'S TOOLING
Exar has a complete in-house silicon wafer fabrication
and processing line at its main manufacturing plant in
Sunnyvale, California. This facility currently runs 3-inch
silicon wafers and will soon add 4-inch capability, and is
also available for manufacturing custom IC's directly
from a set of customer supplied IC tooling, in coordination with Exar's Mask Design department
YOUR FIRST STEP FOR FULL CUSTOM DESIGN
The following technical data package is required in order for Exar to provide you with a quotation for your full
custom development program:
3. Description of circuit operation and pertinent application information.
If you have a set of IC tooling (masks and composite
overlays) or are contemplating having one designed for
you, Exar's technical staff will be glad to review it for
you to assure compatibility with Exar's technology and
layout tolerances. Our wafer processing technology
and capabilities are compatible with the industry standards, and with the technologies of other leading Ie
manufacturers.
4. Preliminary or objective device specification indicating minimax conditions and limits for the critical parameters; i.e., input/output voltage and current lev-
For additional information on Exar's wafer fabrication
services, contact Exar directly. We pride ourselves in
our flexibility and quick response to your needs.
1. Circuit block diagram with subblocks.
2. Circuit schematic or logic diagram.
START
Circuit Function
and Specs
Finalized by
Customer
f---
Full Custom
Feasibility
Study
I---
Preliminary
Cost Estimate
*
,---
Initial
Production
Pricing
I---
Design
Review
**
'--
Pencil
Layout
I---
Mask
Digitizing
*
Mask
Tooling
by Exar they should be done In consultation with Exar.
**These steps must be done by Exar.
FLOW CHART OF TYPICAL FULL CUSTOM DEVELOPMENT
2-8
Computer
Simulation
Finish
f--
*
I---
Prototype
Waler
Fabrication
*
*
Prototype
Evaluation
these steps are not done
f---
*
I---
~
*
Breadboard
Construction
and Evaluation
by Customer
*tf
Circuit
Design
**
*
r--
f---
.--
f--
**
Prototype
Test and
I--
Assembly
**
Advantages of
Semi-Custom Design
over Discrete Design
Advantages of
Full Custom Design
over Discrete Design
Quick Turn-around
Low initial Development Cost
High Reliability
100% Tested
Small Size
Fewer Connections
Fewer Components
Simple to Trouble-Shoot
Reduced Labor Costs
Smaller Inventory of Parts
Increased Protection Against Imitation
Lower Supply Current Possible
Reduced System Cost
Increased System Features
Specialized Components Possible
Higher Level of Integration than Semi-Custom
Lower Unit Cost Than Semi-Custom
More Optimum Design Possible
THE RELATIVE ADVANTAGES OF SEMI-CUSTOM AND FULL CUSTOM DESIGN OVER DISCRETE DESIGN
2-9
TESTING OF SEMI-CUSTOM IC's
TEST INTERFACE DEVELOPMENT
All production units of semi-custom IC's are 100%
electrically tested and screened to test specifications
which have been mutually agreed upon between Exar
and the customer, using one of Exar's several computerized test systems. In addition, Exar's Quality Assurance department performs an independent set of electrical tests on randomly selected samples of production
units, prior to shipment, to assure conformity with
Exar's Acceptable Quality Level (AQL) standards.
The performance and characterization data derived
from careful prototype evaluation is the basis upon
which test hardware and software is developed. Exar
and the customer will jointly determine the performance expectations to be placed on this new IC, and
once these specifications are agreed upon, Exar will
proceed with test development.
Test development involves the design and construction
of a test interface circuit, probe card and automatic
handler hardware as well as writing the software which
allows Exar's test system to perform the desired electrical tests. All these elements are then brought together under actual production conditions for evaluation
and system debugging. This process can take from
four to six weeks to complete, depending on the sophistication and complexity of the test plan under development. Test development begins concurrently with the
start of production wafers (which require approximately
6 weeks to process).
EXAR's TEST CAPABILITIES
Exar can perform two basic types of tests for production IC's: (1) parametric testing which measures a specific parameter value (normally current or voltage) and
compares it against pre-established limits; (2) functional testing which applies a series of operating conditions
and compares the circuit under test with a known good
device. These two types of tests can be performed both
as steady state (dc) or dynamic (ac) measurements.
Exar provides 100% electrical testing of IC chips in wafer form, using automated wafer probe stations, and in
packaged form, using automatic handlers. Exar's test
facility currently has fifteen independent computer controlled test systems, with more being added as we
grow. Exar's automated test system compliment is
comprised of:
•
•
•
•
•
SPECIFICATION AGREEMENT LETTER
With each new custom IC Exar issues a Specification
Agreement Letter. This specification states precisely
the test conditions, performance levels and environmental requirements which each production IC must
meet before it can leave our factory, and is the document upon which acceptability of the IC is judged. It is
issued in duplicate and signed by responsible representatives from both companies prior to beginning production. One copy is retained by the customer, the other is returned to Exar.
Teradyne A311
Teradyne A312
Teradyne A360
Teradyne J273
Fairchild 5000C
Testing is one of the most critical steps in IC production. Therefore, to insure efficient and cost effective
testing of production IC's, it is essential that a preliminary test plan be prepared jointly between the customer and Exar at an early stage of the custom development. This preliminary test plan will lead to the final
detailed test specifications, once the development prototypes are fully evaluated and characterized and the
circuit is ready to release to production.
If, for some reason, changes in the IC's specification
are required, a new Specification Agreement Letter will
be issued by Exar reflecting these changes. No
change, however, will be put into effect until both companies have signed the new agreement. This document
will then supercede all prior agreements and remain in
effect until both firms, again agree, a change is required.
2-10
LINEAR SEMI·CUSTOM DESIGN
cases are those where the package pin-outs are predetermined, or the choice of component locations on the
die may be fixed due to thermal consideration, circuitry
symmetry or offset requirements. In certain cases the
series or parallel connection of several resistors to obtain a predetermined value, or paralleling several transistors to increase their current handling capability,
may also limit the total component utilization.
COMPONENT UTILIZATION
The total number of components on the Exar Linear
Master-Chips range from 110 on the XR-C100A to 850
on the XR-W100. However, the number of these components that are actually usable depends upon many
considerations. The first thing that must be evaluated is
the general requirements of the finished circuit. Factors such as the number of pins that are required,
breakdown voltage as well as die size limitation imposed by packaging requirements, determine which of
the Master-Chips are suitable. This can impose limitations on the number of available components.
Over 850 custom programs have been completed to
date, using Exar's bipolar Master-chips. Thus, Exar's
Engineering department has a great wealth of experience concerning the layout techniques utilizing the
Master-Chips. In many cases, it is advantageous for the
customer to call Exar for a free consultation regarding
the choice of a particular Master-Chip which may be
best suited for his application.
Circuit characteristics also impose limitations upon the
number of usable components. For example, a circuit
whose package pin configuration can be chosen freely,
that handles small signals, low supply voltages, is insensitive to dc offset voltages, and whose various circuit blocks follow one another with a minimum of interconnections between blocks, may be able to use over
90% of the components on the selected Master-Chip.
The bipolar Master-Chips are laid out to provide easy
routing of metal interconnection paths. In addition, a
multiplicity of low resistance crossunders are provided
on the chip to simplify the interconnection layout.
Based on our experience in the layout of various
Master-Chips, the table below gives a rough estimate of
the ease of interconnection of a circuit on each of the
Master-Chips, versus the number of components used
in the circuit.
On the other hand, in more complex designs requiring
special layout or design considerations, the component
utilization may be as low as 50%. Examples of such
Ease of Metal Interconnection vs Components Used
Master-Chip
Type
Somewhat
DlfflcuH
Easy
Difficult
NPN
PNP
Resistance
NPN
PNP
ReSistance
NPN
PNP
XR-A100
40
12
120k ohm
45
15
140k ohm
48
16
Resistance
160k ohm
XR-B100
50
7
150k ohm
52
9
170k ohm
58
12
200k ohm
XR-C100A
17
6
50k ohm
18
7
60k ohm
20
8
75k ohm
XR-D100
38
20*
90k ohm
41
24*
100k ohm
45
26*
120k ohm
XR-E100
38
20*
90k ohm
41
24*
100k ohm
45
26*
120k ohm
XR-F100
60
40*
250k ohm
70
46*
300k ohm
80
54*
340k ohm
XR-G100
50
7
150k ohm
52
9
170k ohm
58
12
200k ohm
XR-H100
50
28
190k ohm
55
34
225k ohm
61
38
260k ohm
XR-J100
23
16
90k ohm
28
18
110k ohm
30
20
125k ohm
XR-L100
56
28
200k ohm
61
34
230k ohm
68
38
265k ohm
XR-M100
103
80
410k ohm
113
95
475k ohm
126
108
550k ohm
XR-U100
to be announced -
call for information
XR-V100
100
77
1440k ohm
(1.4M)
110
92
1675k ohm
(1.675M)
122
104
1940k ohm
(1.94M)
XR-W100
150
86
1790k ohm
(1.79M)
165
103
2080k ohm
(2.08M)
183
117
2400k ohm
(2.4M)
XR-X100
17
20
170k ohm
20
25
200k ohm
22
26
220k ohm
2-11
EXAR LINEAR MASTER-CHIPS
The following section profiles the available Exar linear Master-Chips. The brief description of each Master-Chip includes a small layout of the chip indicating component locations, a brief outline of the key features of the chip, and applications that it is especially well suited for, as well as a tabulation of the type and number of components each
Master-Chip contains.
Linear Mastar-Chip Selection Guide
Master-Chip
Type
XR-A100
XR-B100
XR-C100A
XR-D100
Chip Size
Mils
78x73
85x85
62x56
Possible
Pins
Maximum
Vonage
Total
Components
81 x80
16
20V
260
24
20V
300
14
20V
110
16
36V
209
XR-E100
82x82
18
20V
200
XR-F100
115x98
24
20V
472
XR-G100
90x90
18
20V
309
XR-H100
95x80
18
20V
378
XR-J100
80x75
18
20V
170
XR-L100
102x85
24
20V
408
XR~M100
176x121
28
20V
812
T.B.D.
XR-U100
T.B.D.
36V
T.B.D.
147x113
28
36V
672
XR-W100
164x134
40
36V
850
XR-X100
115x95
18
75V
230
XR-V100
2-12
XR·A 100 Master·ChipTM
Chip Size: 73 x 83 mils
Total Components: 260
Bonding Pads: 16
Max. Operating Voltage: 20V
NPN Transistors
Small Signal: 58
High Current: 2 (200 mAl
PNP Transistors: 18
Schottky Diodes: 15
Pinch Resistors
3OkQ: 4
100kQ: 4
Diffused Resistors
200Q: 16
1.8kQ: 29
450Q: 43
3.6kQ: 28
9OOQ: 43
Total Resistance: 214kQ
XR-A100
2·13
XR·B100 Master·ChipTM
Chip Size: 85 x 85 mils
Total Components: 300
Bonding Pads: 16
Max. Operating Voltage: 2fJV
NPN Transistors
Small Signal: 69
High Current: None
Dual PNP Transistors: 12
Schottky Diodes: 16
Pinch Resistors
3OkQ: 6
100kQ: 6
Diffused Resistors
2OOQ: 27
1.8kQ: 39
4500: 44
3.6kQ: 36
9QOQ:45
Total Resistance: 255k
XR-B1DD
2·14
XR·C100A Master·ChipTM
Chip Size: 56 x 62 mils
Total Components: 110
Bonding Pads: 14
Max. Operating Voltage: 20V
NPN Transistors
Small Signal: 23
High Current: None
PNP Transistors: 8
Schottky Diodes: 6
Pinch Resistors
3OkQ: 2
Difused Resistors
2000: 8
1.8kQ: 13
45QQ: 18
3.6kQ: 12
9OQQ: 20
Total Resistance: 154kQ
XR-Cl00A
2-15
XR·D100 Master·ChipTM
Chip Size: 80 x 81 mils
Total Components: 193
Bonding Pads: 16
Max. Operating Voltage: 36V
NPN Transistors
Small Signal: 50
Dual PNP Transistors: 16
Pinch Resistors
6OkQ:2
Diffused Resistors
2OOQ: 15
1.8kQ: 29
4500: 29
3.6kQ: 24
9Q()Q: 28
Total Resistance: 180kQ
-,
-,
XR-0100
2·16
XR·E100 Master·ChipTM
Chip Size: 80 x 81 mils
Total Components: 187
Bonding Pads: 18
Max. Operating Voltage: 20V
NPN Transistors
Small Signal: 48
Dual PNP Transistors: 15
Pinch Resistors
~kQ:5
Diffused Resistors
2OOQ: 8
1.8kQ: 25
450Q: 32
3.6kQ: 26
9OQQ: 28
Total Resistance: 180kQ
----_._._--
XR·E100
2-17
XR·F100 Master·ChipTM
Chip Size: 96 x 115 mils
Total Components: 440
Bonding Pads: 24
Max. Operating Voltage: 20V
NPN Transistors
Small Signal: 93
High Current: 4
Dual PNP Transistors: 36
Pinch Resistors
3OkQ: 9
Diffused Resistors
2OQQ: 18
1.8kQ: 61
450Q: 90
3.6kQ: 61
900Q: 68
Total Resistance: 425kQ
XR-F100
2-18
XR-G100 Master-ChipTM
Chip Size: 90 x 90 mils
Total Components: 309
Bonding Pads: 18
Max. Operating Voltage: 2fJV
NPN Transistors
Small Signal: 58
High Current: 2
PNP Transistors: 18
Schottky Diodes: None
Pinch Resistors
6OkQ: 8
Diffused Resistors
2OOQ: 19
1.8kQ: 44
450Q: 68
3.6kQ: 27
9000: 65
Total Resistance: 269kQ
XR-G1DD
2·19
XR·H100 Master·ChipTM
Chip Size: 95 x 80 mils
Total Components: 378
Bonding Pads: 18
Max. Operating Voltage: 20V
NPN Transistors
Small Signal: 70
Medium: 2
PNP Transistors
Lateral: 22
_._______________._____ ____ ._____..____
~
Pinch Resistors
6OkQ: 8
Diffused Resistors
2OOkQ: 29
1.8kQ: 54
450kQ: 82
1.8kQ: 36
9OOkQ: 75
1~~'~~IIN!.,~~~o::.:~~:r~,~~~~~~~",_"_"",,,,,,,,,,,,,,,,,,,,,,,,,,!_,,,,
XR-H100
2·20
__,,,,_,,,,,,
XR·J100 Master·ChipTM
Linear, bipolar
Chip Size: 80 x 75 mils
Total Components: 170
Bonding Pads: 18
Max. Operating Voltage: 20V
NPN Transistors
Small Signal: 36
Medium: 2
Dual PNP Transistors: 12
Pinch Resistors
6OkQ: 4
Diffused Resistors
200Q: 8
1.8kQ: 20
450Q: 34
3.6kQ: 20
9OQQ: 30
Total Resistance: 399k
XR-J1DD
2-21
XR·L 100 Master·ChipTM
Chip Size: 102 x 85 mils
Total Components: 408
Bonding Pads: 24
Max. Operating Voltage: 20V
NPN Transistors
Small Signal: 76
Medium: 2
Large: 2
PNP Transistors
Lateral: 22
Quad Collector. 4
Pinch Resistors
6OkQ: 10
Diffused Resistors
2OOkQ: 23
450kQ: 103
900/(Q: 77
1.8kQ: 53
3.6kQ: 36
XR-L1DD
2-22
XR·M100 Master·ChipTM
Chip Size: 176 x 121 mils
Total Components: 812
Bonding Pads: 28
Max. Operating Voltage: 20V
NPN Transistors
Small Signal: 137
Low Noise: 4
Medium: 4
Large: 4
PNP Transistors
Lateral: 44
Quad Collector: 8
Large Vertical: 4
Pinch Resistors
6OkQ: 16
Diffused Resistors
200kQ: 60
450kQ: 188
9OOkQ: 140
1.8kQ: 104
3.6kQ: 84
Cross Under Resistors
15kQ: 11
2·23
XR·U100 Master·ChipTM
XR-Ul0D
2·24
XR·V100 Master·ChipTM
Chip Size: 113 x 147 mils
Total Components: 672
Bonding Pads: 28
Max. Operating Voltage: 36V
NPN Transistors
Small Signal: 140
Large: 4
PNP Transistors
Lateral: 56
Small Vertical: 4
Large Vertical: 4
JFET Transistors
P-Channel: 4
Diffused Resistors
2Q()Q: 28
3.6kQ: 60
450Q: 84
1.8kQ: 68
9JOQ:68
Total Resistance: 443k
Ion Implant
5Ok: 24
5k: 24
2Ok:24
1k: 20
10k: 24
Total Resistors: 2.06 MegQ
Cross Under Resistors
5Q:4
XR-V100
2-25
Oxide capacitor: 4 x 10 pF
XR-W100 Master-ChipTM
Chip Size: 164 x 134 mils
Total Components: 850
Bonding Pads: 40
Max. Operating Voltage: :EV
NPN Transistors
Small Signal: 196
Medium Quad: 4
Large: 4
PNP Transistors
Lateral: 60
Small Vertical: 10
Large Vertical: 4
Diffused Resistors
2ookQ: 24
1.8kQ: 88
450kQ: 100
3.6kQ: 72
900kQ: 100
Ion Implant
5OkQ: 2B
5kQ: 32
2OkQ: 32
1kQ: 32
10kQ: 32
Cross Under Resistors
5kQ:4
XR-W100
2-26
Oxide Capacitor 8 x 10 pF
XR·X100 Master·ChipTM
Chip Size: 115 x 95 mils
Total Components: 230
Bonding Pads: 18
Max. Operating Voltage: 75V
NPN Transistors
Small Signal: 30
High Current: 4
PNP Transistors: 46
Pinch Resistors
3OkQ: 3
100kQ: 3
Diffused Resistors
5Q: 14
1kQ: 27
10Q: 7
2kQ: 57
2OQ: 8
5kQ: 12
500Q: 49
Total Resistance: 615k
~•
1111
XR-X100
2-27
...
.I~
III~
IIII~I"
XR-400 12L Master-ChipTM
Chip Size: 119 x 149 mils
5·0utput 12L Gates: 256
Bonding Pads: 40
Max. Operating Voltage: 7V
NPN Transistors: 45
4-Coliector PNP
Transistors: 12
Schottky·Bipolar 1/0
Interfaces: 18
Diffused Resistors
7ooQ: 200
2.5kQ: 116
5kQ:20
Total Resistance: 530k
XR-400 r2L
2·28
LINEAR SEMI-CUSTOM DESIGN CYCLE: SIX SIMPLE STEPS
The basic linear semi-custom design program involves only 6 single steps, from the beginning of circuit design to the
completion of monolithic prototypes. The first four of these steps can be done by either the customer in consultation
with Exar or by Exar. The last two are performed by Exar.
Step 1
Circuit design and
breadboard using
Linear Design Kit
Customer purchases Exar's Linear IC Design Kit, made up of a comprehensive Design Manual and monolithic kit parts. The circuit is designed, breadboarded and its
performance evaluated using these kit parts. The electrical characteristics of the kit
parts Are virtually identical to the component which will be on the finished IC chip.
Thus, this step provides a true simulation of the final IC performance.
Circuit layout
is prepared
After the completion of breadboard evaluation, a layout of the circuit on the selected
Master Chip by following the basic layout rules given in the Design Manual. The layout is done simply by interconnecting appropriate device terminals with pen or pencil lines on oversize drawings of the Master Chips supplied with the kit.
Layout review
Exar reviews the circuit layout and schematic to check the following:
a) That basic circuit function is feasible
b) No layout rules are violated
c) Circuit layout accurately represents the circuit schematic.
Step 2
Step 3
NOTE: Exar offers consulting service and design advice during these first three
steps.
Step 4
Exar generates custom
interconnection paltern.
Using the completed Master-Chip layout sheet, Exar generates a custom interconnection pattern, or metal mask to be applied to pre-fabricated Master-Chip wafers.
Exar fabricates customized
IC wafers.
Exar applies the custom interconnection patterns to pre-fabricated Master-Chip wafers. During this customization process, the hardware and software necessary to
test the prototypes is made ready. After the wafers are customized, each die is tested by an automatic tester.
Step 5
Step 6
Exar assembles and
delivers monolithic
prototypes.
The customized IC wafers are scribed or cut into individual IC chips. After a visual inspection, several die that tested "good" are assembled in cerdip packages. These
packaged devices are then tested again before shipment. Fifty assembled IC's, and
test data for correlation purposes, are sent to the customer in a prototype package
that includes a die photo, device schematic test details and a layout sheet.
2-29
LINEAR DESIGN KIT
Exar's Linear Design Kit is comprised of thirty-eight
monolithic kit parts or breadboard components, a comprehensive Linear Design Manual, and a number of layout forms corresponding to Exar's Linear Master-Chips.
This design kit provides an ideal vehicle for the customer to do his own semi-custom IC design. he can
evaluate his breadboard performance using the kit
parts and then proceed to do his own layout on the
Master-Chip worksheet.
on a breadboard in a couple of minutes with a pair of
pliers and a hot soldering iron. Changes on an IC are
much more expensive and time consuming. The breadboard can be tested over temperature in a temperature
chamber and circuit performance can be measured
with worst case resistor values. Preliminary test specifications can also be readily developed from a properly
functioning breadboard. Next to the initial paper design, breadboarding is the most important step in IC development.
The Linear Design Manual Provided as a part of the design kit gives a detailed description of the basic guidelines and rules of IC design, evaluation and layout. It also describes the electrical characteristics of each type
of component available in the Master-Chips, and gives
some of 'the anticipated parameter distribution and
worst case tolerances associated with each. In addition, several design and layout examples are provided
to demonstrate the efficient use of the IC chips.
KIT PARTS
Since the purpose of breadboarding is to build a circuit
that will duplicate, as closely as possible, the performance of the finished IC, Exar has included with this design kit a generous supply of kit parts. These kit parts
are the same integrated components that you will find
on the finished IC. They are metalized and brought out
individually so that you can use them to connect your
circuit. The table below lists the kit parts that come with
the design kit; how many of each are included, and
which components are found on each Master-Chip.
Once the breadboard evaluation is complete, the designer is ready to start his own IC layout using the appropriate Master-Chip layout form supplied with the kit.
When this layout is ready and is reviewed by Exar, the
prototype fabrication portion of the custom program is
ready to begin.
Generally speaking, the integrated resistor arrays need
only be used in circuits where certain characteristics of
these resistors, such as high frequency response or
temperature coefficients, are critical to circuit performance. In most cases, standard off-the-shelf carbon film
resistors are entirely adequate for breadboarding.
TECHNICAL ASSISTANCE
If any special or unusual circuit design or layout problems are encountered in the preparation of your semicustom IC layout, Exar's technical staff will be glad to
review your design problem and provide technical guidance. In many cases, it is beneficial to call Exar for a
preliminary discussion of your custom IC needs even
before you decide to buy a design kit.
BREADBOARDING TECHNIQUES
The single most important thing to remember when you
are building a breadboard is that you are trying to simulate the operation of a circuit that measures approximately a tenth of an inch on a side with one that measures several inches on a side. Although this task is not
impossible, it does require a significant amount of planning and forethought, if It Is to be successful.
ADDITIONAL KIT PARTS
The number of kit parts supplied as part of the Linear
Design Kit is sufficient for most designs. However, if
additional kit parts are required to complete your evaluation, these can be obtained either directly from Exar
or through your local Exar technical representative.
Included in the Exar Design Kit are conveniences, such
as a prototyping board and IC sockets, to make breadboarding easier and quicker.
It is arranged on a matrix format so that individual kit
parts can be easily located and identified. Space is provided at the top of the breadboard for identifying the circuit title, the design engineer, the revision, as well as
the data of construction. The interdigitated metal runs
are designed to serve as V + and ground for single supply applications; or as V+ and V- with the outside border serving as ground or dual supply applications. An
edge connector has been provided so that you can easily connect your breadboard to power supplies, signal
sources and test equipment, without having to solder
leads directly to the breadboard. This allows you to disconnect the breadboard to test kit parts on a curve
tracer or to make circuit modifications without destroying your test setup.
BREADBOARDING
After a circuit has been designed and analyzed on paper, it is time to reduce the theoretical design to a functioning circuit that will duplicate, as closely as possible,
the operation of the finished integrated circuit. This is
the purpose of breadboarding. A great deal of care
needs to be taken during this phase of IC development.
Accurate breadboarding will not only allow you to gain
an accurate assessment of the performance you can
expect from the finished IC, but it will also allow you to
discover circuit design flaws. A correctly connected,
nonfunctional breadboard is a very vivid indication that
something has been overlooked. Changes can be made
2-30
Kit Part #
20V
Mastarchlps
XR-AXR-8XR-F-
101
...
...
103
...
108
111
XR-W-
...
75V
Mastarchips
XR-X-
...
...
...
...
...
117
206
202
210
213
215
216
...
...
421
...
XR-M-
XR-D-
114
...
XR-J-
36V
Mastarchlps
112
...
...
...
...
...
...
...
...
...
...
...
General Notes on Kit Parts
1) Dual collector PNP's will have both collectors tied together and acting as one collector unless shown otherwise in a kit part outline.
2) Kit parts with small NPN's use all available collector
contacts on each device. The designer should note
that if fewer than the full complement of collector
contacts (generally four) are used when designing
the I.C. layout, slightly degraded performance may
result.
3) For proper operation of these kit parts the substrate
pin, labeled ~ ,must be tied to the lowest potential
in the circuit. Resistor kit parts require connection to
both the most positive and most negative potentials
within a circuit for proper operation.
Breadboarding Recommendations
For Designs Using
Exar Mastar-Chip
Usa Kit Parts
A100
8100
C100
XR-A-NNN*
XR-8-NNN
D100
XR-D-NNN
E100
F100
G100
H100
J100
K100
L100
M100
XR-F-NNN
XR-J-NNN
XR-M-NNN
U100
V100
W100
XR-W-NNN
X100
XR-X-NNN
4)
S)
6)
.~ Denotes transistors designed to operate
above 10 mAo
~
r;;::;:
Denotes Schottky transistors.
Denotes pinch or FET resistors.
Resistor networks RN1 and RN2 are only available for
Exar's 20V process. RN3 devices are available for both
20V and 36V operation. To order, specify:
RN1:
RN2:
RN3:
* NNN = Kit part number.
XR-A-104
XR-A-10S
XR-F-XXX
XR-W-XXX
For 20V operation
For 36V operation
xxx =
Resistor value in kQ. Avalilable Values for base
diffused and ion implant resistors are shown below.
Ordering Information
ION IMPLANT
BASE
Additional or extra kit parts may be ordered from your
local distributor or Exar representative. To order, specify the desired device(s) by using the part number code as
shown above.
Example: XR-F-101
XR-J-21S
XR-W-421
2-31
Valua
XXX
3.6K
1.8K
9000
4S00
2000
3R6
1R8
R90
R4S
R20
Valua
SOK
20K
10K
SK
1K
XXX
SOR
20R
10R
OSR
01R
EXAR LINEAR KIT PARTS
101
111
103
108
112
114
2 Medium NPN's
2 Large Vertical PNP's
1 Small NPN
117
202
,------,. ;------,
2-32
206
EXAR LINEAR KIT PARTS
210
213
215
NOTE: 5 Small & 2 Large Vertical PNP's.
Resistance shown Is substrate
resistance between middle and
edge of die.
216
421
NOTE: Drain and Source
are Interchangeable
Resistor Networks
RN1
RN2
RN3
NOTE: All resistors are the same vatue
2·33
ELECTRICAL CHARACTERISTICS OF LINEAR MASTER-CHIP COMPONENTS
The following tables list the electrical characteristics of the circuit components available on Exar's linear MasterChips. Whenever applicable, the "worst case" tolerances and the parameter distributions are also listed.
PARAMETERS
TYPICAL VALUES
Smail-Signal NPN Transistors
Current gain (hFE) @ 1 rnA, 5V
Temperature Coefficiency of hFE
- 55°C to 25°C
25°C to 125°C
Matching of hFE
Breakdown voltage (LVCEO)
20-V Master-Chips
36-V Master-Chips
Collector-Base Leakage Current @ 20 V
Cutoff Frequency (fy) @ 5 rnA
Storage Time (ts)
Saturation Resistance (All except 0100)
One collector contact
Two collector contacts
Saturation Resistance (0100 chip)
One collector contact
Two collector contacts
180
+0.5%/OC
+1%/OC
-
23V
40V
1 nA
500 MHz
50 nsec
u-LlMIT
WORST CASE
TOLERANCE
-
80-300
3%
10%
-
-
20-30V
36-50V
0.1-50 nA
-
100 Ohms
50 Ohms
±50 Ohms
±20 Ohms
60-160 Ohms
30-80 Ohms
300 Ohms
150 Ohms
± 100 Ohms
±50 Ohms
150-480 Ohms
75-240 Ohms
180
100
3%
-
80-300
50-200
High-Current NPN Transistors
Current Gain (hFE)
@ 1 mA,5V
@ 100 rnA, 5V
Temperature Coefficient of hFE
- 55°C to 25°C
25°C to 125°C
Matching hFE
Breakdown Voltage (LVCEO)
Collector-Base Leakage Current @ 20V
Cutoff Frequency (fT)
Storage Time (ts)
Saturation Resistance
+0.5%/OC
+1 %/OC
-
23V
20 nA
100 MHz
200 nsec
5 Ohms
±10hm
10%
20-35V
1-500 nA
-
3-8 Ohms
Lateral PNP Transistors
Current Gain (hFE) @ 100~, 5V
Temperature Coefficient of hFE
Matching of hFE
Breakdown Voltage (LVCEO)
20-V Master Chips
36-V Master Chips
Collector-Base Leakage Current @ 20V
Cutoff Frequency (fy)
Storage Time (ts)
Saturation Resistance
5-80
-
-
5%
15%
35V
45V
5 nA
5 MHz
500 nsec
600 Ohms
-
25V-40V
36-60V
0.1 to 100 nA
20
± 1.0%/OC
-
-
±100 Ohms
300-900 Ohms
±200 mV
2 mV
0.68-0.8V
6mV
5,.V/oC
15,.V/oC
±200 mV
3mV
0.62-0.76V
5 mV
8,.V/oC
25,.V/oC
TRANSISTORS CONNECTED AS DIODES
(Collector and Base Shorted)
Small NPN
Forward Voltage Drop @ 1 rnA, 25°C
Forward Voltage Matching
Forward Voltage Tracking
Lateral PNP
Forward Voltage Drop @ 200 ~, 25°C
Forward Voltage Matching
Forward Voltage Tracking
0.74V
--
0.70V
-
2-34
PARAMETERS
TYPICAL VALUES
a-LIMIT
WORST CASE
TOLERANCE
6.35V
6.7V
+2.5 mV/oC
±0.15V
±0.2V
±0.3 mV/oC
5.9-6.8V
6.0-7.2V
1.8-3.1 mV/oC
0.36V
±0.02V
0.22 to 0.44V
-1.5 mV/oC
30V
200 nA
±0.1 mV/oC
-
±0.3 mV/oC
20-40V
1 nA-1 p.A
±10%
±25%
±100 ppm
±40 ppm
±40 ppm
±20 ppm
±40 ppm
-
NPN Base-Emitter Junctions Used
as Zener Diodes
Small NPN Transistors
Breakdown Voltage @ 100 p.A
20-V Master Chips
36-V Master Chips
Temperature Coefficient
Schottky-Barrier Diodes
(A100/B100/C100 Only)
Forward Voltage Drop @ 10 p.A
Temperature Coefficient of Forward
Voltage Drop
Reverse Breakdown Voltage
Leakage Current @ 20V
-
Diffused Resistors (All Master-Chips)
Absolute Values
Temperature Coefficients
-55°C to -25°C
-25°C to O°C
O°C to 25°C
25°C to 75°C
75°C to 125°C
Matching Between Resistors
Identical Values
Non-Identical Values
200-450
200-900
200-1.8K
200-3.6K
450-900
450-1.8K
450-3.6K
900-1.8K
900-3.6K
1.8K-3.6K
-650 ppm/DC
+150 ppm/DC
+680 ppm/DC
+ 1040 ppm/DC
+ 1400 ppm/DC
-
±0.8%
±2.4%
-
±1.6%
±1.7%
±1.9%
±2.0%
±1.5%
±1.7%
±1.9%
±1.5%
±1.7%
±1.5%
±4.8%
±5.1%
±5.7%
±6.0%
±4.5%
±5.1%
±5.7%
±4.5%
±5.1%
±4.5%
-
-
Pinch-Resistors
Absolute Value Tolerance
Matching Between Identical Resistors
Breakdown Voltage
Temp. Coefficient
±50%
±20%
6.4V
+ 6,000 ppm/DC
2-35
-
+ 100% to - 50%
-
8,000 ppm/DC
12L SEMI·CUSTOM DESIGN
used with 12L Master-Chips to be generated simultaneously from a customer's pencil layout on the MasterChip worksheet. This unique mask generation technique, and the three-mask customizing method, are the
heart of Exar's 12L semi-custom program. In this manner, one is able to combine low cost, quick turnaround
capabilities of semi-custom designs with the high functional density of 12L technology, and still make very efficient use of the chip area.
Integrated Injection Logic (12L) technology extends the
capabilities of semi-custom design to high complexity
digital or combined analog/digital systems. Exar has
made this possible by the development of a family of
12L Master-Chips which combine a large number of 12L
gates and Schottky bipolar transistors on the same
chip. Similar to its bipolar counterpart, Exar's 12L semicustom program also utilizes partially fabricated silicon
wafers which are then customized by the application of
special mask patterns.
WHEN TO USE DIGITAL SEMI-CUSTOM
Exar's 12L Master-Chips utilize bipolar input/output (I/O)
interface circuitry on the same chip with the high density 12L logic arrays. Thus, outwardly the 12L semicustom chip looks and performs exactly as a bipolar LSI
chip, which can readily interface with TIL level signals.
In other words, these gate array Master-Chips combine
the high functional density advantages of 12L technology with the interface and load drive capability of the bipolar circuitry on the same IC. This feature makes it
very convenient to retrofit 12L LSI designs into existing
TIL type logic systems.
The key application of 12L semi-custom design is to replace complex blocks of random logic with a single
monolithic chip. An entire digital subsystem comprised
of many SSI or MSI chips, or discrete components, can
be put on a single 12L Master-Chip. This can provide
significant cost and space savings and greatly improve
system reliability. The availability of bipolar input/output
interface circuitry on the same chip with the high density 12L logic makes it very convenient to retrofit 12L designs into existing TIL logic systems. Therefore, semicustom 12L LSI designs provide cost effective solutions
for complex custom LSI reqUirements, even at production volumes as low as a few thousand pieces.
ACHIEVING HIGH COMPLEXITY
Traditionally, the application of semi-custom technology
to complex digital systems has been somewhat limited
due to one key factor; in order to be economically feasible, a complex digital LSI circuit must achieve a high
functional density on the chip (high gate count per unit
of chip area). This requirement is not compatible with
the random interconnection concept which is key to the
semi-custom or Master-Chip design technique. Exar's
approach overcomes this limitation, by making use of
the unique layout and interconnection properties of 12L
gates, and by extending the customizing steps to mask
layers. In addition to the metal interconnection pattern,
Exar can achieve high packing density and still retain
the quick turnaround features and low cost of semicustom.
FEATURES OF 12L TECHNOLOGY
High Functional Density: 12L logic gates offer a much
smaller size than their bipolar counterparts. Thus, a
much higher degree of logic complexity or functional
density can be achieved on a given IC Chip.
Easy to Interconnect: Unique structure and geometry of
121 gates make them ideal for semi-custom design. An
entire array of gates can be easily customized and interconnected using only three masks without sacrificing high functional density.
Bipolar Compatible Processing: 12L is a direct derivative of
conventional bipolar IC technology. Therefore, one can
combine bipolar devices on the same chip as 12L gates.
This feature has the following key advantages:
Exar's 12L Master-Chips are customized by not one but
three mask layers:
• Input/output section of 12L chips are bipolar. Thus,
they can readily interface with existing logic families
or retrofit into existing systems.
1. A custom diffusion pattern to define gate outputs
and custom underpasses for interconnection.
2. A custom contact mask which opens contact windows or activates only those devices actually used
in the design.
• Analog and digital functions can be combined on the
same chip. One of Exar's Master-Chips, the XR-400,
is specifically designed for such an application.
3. A custom metal interconnection mask which interconnects all the activated devices.
FULLY AUTOMATED MASK GENERATION
Low Voltage Operation: 12L gates can operate with supply
voltages as low as one volt, and require only a single
power supply.
Exar has developed a fully automated mask generation
technique which allows all three custom mask layers
Low Current and Low Power Operation: Depending on
speed reqUirements, 12L gates can operate with current
2-36
LOGIC CONVERSION TO 12L GATES
levels in the nanoampere range. This feature, along
with its low voltage operation makes it ideal for applications in low power, battery operated systems.
Converting conventional logic diagrams from their
NAND/NOR gate eqUivalents to 12L gates is a simple
and straightforward procedure. This information is contained in the 12L Design Manual, which is available as a
part of Exar's 12L Design Kit. In addition, Exar has developed a large library of 12L logic subblocks corresponding to popular logiC functions, such as decoders,
flip-flops and counters, which greatly simplifies this
conversion process.
Higher Reliability Than MOS: Since 12L gates have the
same basic features as bipolar transistors, they are not
subject to electrostatic burn-out problems associated
with MOS transistors and do not require special handling precautions.
Wide Operating Temperature: 12L gates are not seriously
affected by leakage currents as are their MOS counterparts. Thus, they can accommodate the full military
temperature range.
I •••
DESIGNING WITH 12L MASTER-CHIPS
..----.,----r---,----.----,
Exar currently has four 12L Master-Chips in production.
These are the XR-200, XR-300, XR-400 and the XR-500
Master-Chips. The XR-200, XR-300 and the XR-500 are
designed for digital systems. The XR-400 Master-Chip is
intended for systems requiring both analog and digital
functions.
All four of these Master-Chips are fabricated with the
same manufacturing process. They differ only in their
architecture and in the number of components. All of
these chips are especially designed for Exar's unique
three-mask customization process using fully automated mask generation techniques.
COMPARISON OF SPEED AND POWER CAPABILITIES
OF VARIOUS LOGIC FAMILIES
XR-200, XR-300 and XR-500 MASTER-CHIPS
These Master-Chips are primarily designed for applications requiring only digital signal processing. They contain a large number of multiple output 12L gates along
with Schottky bipolar input/output buffers. Except for
the difference in size, all three chips have the same architecture shown below. The 12L gates are arranged in
array form at the center of the chip and the input/output
buffers are located along the periphery of the Chip. The
bipolar I/O sections of the chips contain two identical
sets of resistor arrays located at opposite ends of the
chip which are used for biasing the injectors of the 12L
gates. The XR-200 contains 192 five-output 12L gates
and 24 I/O buffers. The XR-300 contains 288 five-output
12L gates and 28 I/O buffers. The XR-500 contains 520
five-output 12L gates and 40 I/O buffers. A detailed description of the bipolar input/output interface circuitry is
given further on in the text.
THE BASIC 12L GATE
The 12L logic technology is derived from the basic single input, multiple output inverter circuit shown below.
The logic functions are performed in a manner similar
to the conventional open-collector logic. The outputs of
various gates are interconnected together in a wiredAND configuration. Many sections of the 12L gate share
common semi-conductor regions. For example, the collector of the pnp is the same as the base of the npn,
and the emitter of the npn is the same as the base of
the pnp. This leads to a very compact device structure
which occupies a correspondingly small chip area. As a
result, the functional density of 12L gates is comparable
to that of some MOS technologies and is approximately
5 times higher than conventional TIL logic.
THE BASIC 12L GATE
(8) Aclual Gale
(b) Equivalenl Circuil
2-37
(c) LogiC" Symbol
BIPOLAR 110 INTERFACE
INPUT/OUTPUT
INTERFACE
INPUT/OUTPUT
INTERFACE
BIPOLAR 1/0 INTERFACE
BASIC LAYOUT OF XR-400 MASTER CHIP
BASIC LAYOUT OF XR-200, XR-300 AND XR-500
MASTER CHIPS
Components on XR 12L Master-Chips
XR-400 MASTER-CHIP
The XR-400 Master-Chip is designed primarily for applications requiring the combination of analog and digital
functions on the same chip. Thus, it is made up of both
a linear and a digital section. The digital section of the
chip has the same basic architecture as the XR-300. It
contains 256 five"output 12L gates and 18 Schottky bipolar I/O interface sections. The linear section of the
chip is made up of an array of npn and pnp transistors
and resistors and is very similar to Exsr's bipolar
Master-Chips.
Quantity
Component Type
XR·200
XR-300
XR-400
XR·500
5-0utput 12L Gates
192
288
256
520
24
28
18
40
7V
7V
7V
7V
0
0
45
0
0
0
12
0
0
0
0
0
200
116
20
0
0
0
Schottky·Bipolar
1/0 Interfaces
Max Operating
Voltage
N PN Transistors
4-Coliector PN P
Transistors
Diffused Resistors
70011
2,5 K
5K
COMPONENT UTILIZATION
The unique three-mask customizing technique used in
Exar's 12L Master-Chips makes them very' efficient for
both ease of logic layout and component utilization.
One of the three customizing mask steps is a custom
diffusion step which allows the placement of low resistance crossunders, or underpasses, selectively on the
chip. This technique provides the designer with virtually
two layers of interconnection on the chip and, thus,
greatly simplifies the logic layout and improves the
component utilization efficiency. Normally, in the case
of random combinational logic, one can easily utilize
60% to 80% of the total gates available on a given 12L
Master-Chip. In the case of sequential and repetitive
logic Circuits, the gate utilization is normally as high as
80% to 100%.
Bonding Pads
Chip Size (mils)
In the case of the XR-400 Master-Chip, which combines
analog circuit components and digital gates on the
same chip, the three-mask customizing technique is
applicable to the digital section, while the analog section of the chip is customized with one mask in the
same way as the linear Master-Chips.
2-38
0
0
30
34
40
42
98 x 119
106 x 144
119 x 149
122 x 185
THE 12L GATE ARRAY SECTION
L-
P.TYPE"FINGER"
".
OIFFUSIOHFOR
This section of the 12L Master-Chip is made up of logic
cells which contain a number of multiple output 12L inverters grouped together. The figure below shows a typicallayout of such a cell made up of eight multiple output inverters which share a common set of four injectors. The basic gate cells forming the 12L gate array are
made up of p-type injectors and p-type gate fingers
which serve as the base regions of the 12L gates. The
six dots on each gate area indicate the possible locations (or sites) for gate inputs or outputs. The particular
use of these sItes as an input or output is determined
by two custom masks. An n-type collector diffusion
mask defines the locations of outputs and a custom
contact mask opens the appropriate input and output
contacts. Finally, a third custom mask is applied to
form the metal interconnections between the gates and
the gate cells. The custom n-type diffusion step, which
determines the locations of gate outputs, is also used
for forming low resistivity underpasses between the
gate cells. The area between each of the gate cells can
accommodate two or three parallel underpasses in the
horizontal or vertical direction. Since the n-type diffusion which forms these underpasses is a part of the
customizing step, the location and length of each underpass can be chosen to fit a given interconnection
requirement. This method provides the designer with
virtually all of the advantages and capabilities of multilayer interconnection paths on the surface of the chip
and allows approximately 80% of the gates on the chip
to be utilized in a typical logic layout.
The custom logic interconnections can be easily laid
out in pencil on a layout sheet by simply interconnecting the desired gate sites with a pencil line and appropriately defining the function of the site as an input, output, injector contact or an underpass. The function of
each of the potential sites is defined by Simply drawing
an appropriate symbol on it, such as a circle for an output and a square for an input, as defined in the example
below.
12 lGATES
rADJACENT
CELL
~~"
.~~~
· ...
....
·· ...
...
"
Ii- • • •
r
I
DOTS INDICATE LOCATION 0
r
BASIC 8 GATE CELL PRIOR TO CUSTOMIZATION
__
o -
• METAL INTE..cONNECTlOIII
INJECTOR CONTACT
o . GATE OUTPUT
o
·GATEI~
~.UNDI"'AII
L-_-----'I
IHI'LI..!,.
-
0,
~
I@ ~
~~
~
; :;;r1'
....
'1OEClOO
=:S'!fe --A
.,- ~13 -~
0,
-
'--
SAMPLE PENCIL LAYOUT ON MASTER CHIP
WORKSHEET
~
~
INPUT
rGATE OUTPUT
r--.~
~
j
~~ :::~;
"'/ V-:ET~~~
DIFFU
~'!Il
p","
~V~NDER'"
~~ ~
~-
II
!II -
~[!ii
.u,
IN.EeT
-
0,
I
SAMPLE LAYOUT OF 8 GATE CELL AFTER
CUSTOMIZING WITH N+ COLLECTOR DIFFUSION,
CONTACT MASK AND METAL INTERCONNECTION
PATTERN
2-39
BIPOLAR INPUT/OUTPUT INTERFACE SECTION
~
A7=
5001/
m[O~S1
~
BONDING
Q1
PAD
I [D~S2
[§
~-~ II,~~
Q2
[Q)
~
R5
=2.5 K
The bipolar input/output interface sections of the 12L
Master-Chips are located along the periphery of the
chips. The component locations in a typical I/O cell are
shown in the adjacent figure. Each I/O cell is designed
to be either an input or an output interface depending
on the choice of the metal interconnection pattern applied to the cell. Furthermore, two adjacent cells can
be combined together to provide a three-state type output buffer. Some of the basic input and output circuit
configurations available from the I/O interface are
shown below. In the case of a three-state output configuration, one would also utilize several gates from the
12L logic section to perform the necessary gating functions.
R.
=2.5 K
t@
Each input/output interface cell contains one bonding
pad, several resistors of varying values, a clamp diode
to substrate and two npn transistors with optional
Schottky diode clamps. Each npn transistor is capable
of sinking 5 mA of current with Schottky diode clamps
and 10 mA of current without, at a saturation voltage of
:s 0.5V. The breakdown voltage of the bipolar I/O section is 7V.
R, = 10 K
R2 = 10 K
A TYPICAL SCHOTTKY-BIPOLAR INPUT/OUTPUT
INTERFACE CELL
, . - - - - - . - - v'
INPUT
10K
5K
20K
10K
OUTPUT
(a) Input Interlace CirCUIt
(b) Output Interface Clrcuil
15K
10K
10K
DATA INPUT _ _~_-J---~llf--o;~=r-~-II--4--~
FROM 12L
GATES
500
OUTPUT
TRI·STATE
ENABLE
CONTROL
I~.----
ADDITIONAL
GATING
TRI·STATE
- - - - f - - - - - :~~~~R
(e) Tri-State Output Interface Circuit
TYPICAL BIPOLAR INPUT/OUTPUT INTERFACE CIRCUITS AVAILABLE FROM 110 INTERFACE CELL
2-40
EXAR 12L Master-ChipsTM
The following section profiles the available Exar 12L
Master-Chips"'. The brief description of Master-Chip"
includes a small layout sheet of the chip indicating
component locations, a brief outline of the key features
of the chip, and applications for which it is well suited
as well as a tabulation of the type and number of components each chip contains.
2-41
XR·200 12L Master·ChipTM
Chip Size: 98 x 119 mils
5-0utput 12L Gates: 192
Schottky-Bipolar I/O
Interfaces: 24
Bonding Pads: 30
Max. Operating Voltage: 7V
The XR-200 12L Master-Chip'" is designed for applications that require medium complexity logic on a single
chip. The bipolar 1/0 interface cells make the XR-200
compatible with standard TTL or 5V CMOS logic families.
•
~
II
..."',,
'",,"
XR-200 12L
2-42
til
...
[i]
GL1
GJ
XR·300 12L Master·ChipTM
Chip Size: 106 x 144 mils
5-0utput 12L Gates: 288
Schottky-Bipolar 1/0
Interfaces: 28
Bonding Pads: 34
Max. Operating Voltage: 7V
The XR-300 12L Master-Chip" is designed for applications which require high density random logic on a single chip. The eight gate logic cells allow room for crossunders between cells thus increasing layout efficiency.
The bipolar 1/0 interface cells make the XR-300 compatible with standard TIL or 5V CMOS logic families.
[;]
XR-3DD 12L
2-43
..
XR-400 12L Master-ChipTM
Digital Components: 149
Chip Size: 119 x 149 mils
5-0utput 12L Gates: 256
Schottky-Bipolar I/O
Interfaces: 18
Bonding Pads: 40
Max. Operating Voltage: 7V
Linear Components:
NPN Transistors: 45
4-Collector PNP
Transistors: 12
Diffused Resistors:
7000: 200
2.5kO: 116
5kO: 20
Total Resistance: 530K
XR·400 12L
2-44
The XR-400 is a unique Master-Chip" that provides the
capability of combining moderately complex linear circuitry on the same die as complex logic circuitry. This
Master-Chip is an excellent choice when the advantages and capabilities of linear and digital techniques
must be combined. The bipolar 1/0 interface cells make
the XR-400's 12L section compatible with standard TTL
or 5V CMOS logic families.
XR·500 12L Master·ChipTM
Chip Size: 122 x 185 mils
5-0utput 12L Gates: 520
Schottky-Bipolar 1/0
Interfaces: 40
Bonding Pads: 42
Max_ Operating Voltage: 7V
[~
G
I·1
i
[oJ
The XR-500 12L Master-Chip'" is designed for applications which require high density logiC on a single chip_
The eight gate logic cells allow room for cross-unders
between cells for increased layout efficiency_ A generous number of I/O cells and bonding pads allows many
connections between the on board logic and the outside world. The bipolar 1/0 interface cells make the
XR-500 compatible with standard TIL or 5V CMOS
logic families.
EJ
[R]
cc
0
L
[5']
I
/cP'
I
:1
, ,
[";
I
,
~
I
l __
XR-500 12L
2-45
12L SEMI-CUSTOM DESIGN CYCLE
In many cases, the first two steps indicated in the flow
chart can be done by the customer, in consultation with
Exar, using Exar's 12L Design Kit and the design instruction manual. Whenever possible, such an approach is
recommended since it greatly reduces the development costs and turnaround time.
The digital semi-custom LSI design program using Exar's 12L Master-Chips is devised for maximum versatility
and flexibility to suit varying customer needs and capabilities. The flow chart below gives the outline and sequence of six basic steps associated with a typical 12L
semi-custom program.
3
1
FEASIBILITY REVIEW
AND LOGIC CONVERSION
TO f2L OATES
1
2
PENCIL LAYOUT ON
GATE ARRAY WORKSHEETS
5
CUSTOMIZING PRE·FAB
WAFERS: COLLECTDR DIFF.
CONTACT AND METAL
COMPUTERIZED MASK
ARTWORK GENERATION
•
1
~
8
MASK FABRICATION
N+/CONTACT/METAL MASKS
ASSEMBLYITEST AND
PROTOTYPE DELIVERY
SIX BASIC STEPS OF SEMI-CUSTOM 12L LSI DEVELOPMENT
STEP 1: FEASIBILITY REVIEW AND LOGIC
CONVERSION
·IC tooling (n-type diffusion, contact window opening
and metal interconnections) can be automatically gen·
erated by a single digitizing step from the pencil layout.
This simultaneous and automated generation of the
custom mask layers greatly reduces the tooling cost
and turnaround time, and avoids mask errors.
Starting with the customer's logic diagram (preferably
reduced to flip·flops and gates), the first step is a detailed review of the system requirements with regard to
the overall gate count, I/O reqUirements, operating
speeds, etc., to assure feasibility and to choose the
most economical gate array. The next step is to convert
the logic diagram into 12L gates. At this state a computer simulation of the logic diagram may also be performed, if deemed necessary.
STEP 4: MASK FABRICATION
The photographic tooling plates, or masks, are fabricated by a pattern generation technique from the digitized coordinate information stored in the computer.
STEP 2: PENCIL LAYOUT ON GATE ARRAY
WORKSHEETS
STEP 5: CUSTOMIZING PREFABRICATED WAFERS
Once the logic diagram is converted to 12L gates, the
next step will be to make a pencil layout of the circuit on
the appropriate array worksheet. This pencil layout is
done on a blank worksheet where the gate input and
output locations are shown as target dots. During the
layout, the interconnections and underpasses between
the gates are indicated by pencil lines and appropriate
symbols. The bipolar I/O cells do not need to be inter·
nally interconnected. Since these cells are standardized, it is only necessary for the designer to specify if a
particular I/O cell is to be used as an input or output.
The prefabricated 12L wafers containing the p-type
base diffusion and gate fingers are customized into
completed monolithic LSI chips using the custom IC
tooling generated in Steps 3 and 4.
STEP 6: ASSEMBLYITEST AND PROTOTYPE DELIVERY
The completed monolithic chips are first evaluated on
the finished IC wafer and later assembled, electrically
tested and delivered as completed prototypes. The
amount of electrical testing done on the initial prototypes depends on the customer's specific needs and
requirements.
STEP 3: COMPUTERIZED MASK ARTWORK
GENERATION
Using a specially developed computerized mask generation technique, the three layers of necessary custom
2·46
DESIGN EXAMPLE
layout of his own semi·custom 12L Chip. This Design Kit
contains the following:
The multiple output 12L gates on the Exar Master-Chips
are arranged in a-gate or 16-gate cells. A complex logic
array can be partitioned into subsections and each of
these subsections can be laid out on one or more of
these cells. The example below shows the layout of a
D·type flip-flop on one of Exar's Master-Chips. The dark
lines in the layout example correspond to the metal in·
terconnection busses; the circles and squares indicate
the respective gate outputs and inputs. As a part of the
12L Design Kit, Exar supplies a complete Design Manual and special layout worksheets which enable the
customer to do his own logic conversion and layout.
• A set of 40 monolithic kit parts for process evaluation
and critical circuit breadboarding.
• A comprehensive design manual which covers the
fundamentals of 12L logic and provides design and
layout examples.
• A set of layout worksheets which lets the user prepare his own logic layout directly on the 12L MasterChip.
• A breadboard kit which includes a P.C. board, IC
sockets, and an edge connector, as well as other
hardware.
The monolithic kit parts which make up the 12L Design
Kit are comprised of basic logic building blocks such as
gate arrays, latches and flip·flops, as well as bipolar
input/output buffers. The kit parts allow the designer to
characterize the 12L circuit performance and optimize
his design well in advance of performing the final circuit layout. In this manner, the problems and pitfalls
normally encountered in converting a discrete logic
system into a monolithic design are avoided. In addition, the kit also includes a special 12L evaluation or
test chip, the XR·C409. This test circuit contains frequency dividers and ring oscillators to evaluate the
high frequency capabilities and the power speed tradeoffs of 12L gates.
o
The 12L Design Manual gives a comprehensive review
of 12L logic technology and describes the electrical
characteristics of each type of component available on
the Master-Chips. It also presents some of the antici·
pated parameter distributions and the worst case tolerances associated with each type of circuit component.
In addition, the design manual also provides a library of
12L equivalents of logic subblocks corresponding to
popular logic functions such as decoders, flip·flops,
counters and multiplexers, and gives layout examples
which demonstrate the efficient use of layout worksheets.
(a) NAND LOGIC DIAGRAM
-
R
CK
D
.. • -r--
-
-
'-ABC
o
o
o
r-- r--
- .-
~
D
--
'--
E
F
-G
INJECTOR
RAIL
r-
I· i-
Q
ADDITIONAL KIT PARTS
'-H
The number of kit parts supplied as a part of the 12L de·
sign kit are generally sufficient. However, if additional
kit parts are required to complete your evaluation,
these can be obtained either directly from Exar, or
through your local Exar technical representative.
GATE OUTPUT
GATE INPUT
INJECTOR CONTACT
METAL INTERCONNECT
TECHNICAL ASSISTANCE
(b) TYPICAL PENCIL LAYOUT ON MASTER
CHIP WORKSHEET
If any special or unusual circuit design or layout prob·
lems are encountered in the preparation of your semi·
custom IC layout, Exar's technical staff will be glad to
review your design problem and provide technical guid·
ance. In many cases it is beneficial to call Exar for a
preliminary discussion of your custom IC needs, even
before you decide to buy a design kit.
12L Design Kit
Exar's 12L Design Kit provides an ideal vehicle for the
customer to familiarize himself with the fundamentals
of 12L logic. He can then proceed to do the design and
2-47
COMPONENTS INCLUDED IN 12
DESIGN KIT
XR-C502
12L NOR-GATE ARRAY
Part Number
Description
Quantity
XR·C501
XR·C502
XR·C503
XR·C504
12L Triple Inverter Array
Quad NOR·Gate Arry
Dual D·type Flip·Flop (unbuffered)
Dual D·type Flip·Flop with Bipolar
1/0 Buffers
Dual J·K Flip·Flop (unbuffered)
12L Compatible NPN Transistor Array
12L Evaluation Circuit
15
4
8
2
Total
40
XR·C505
XR·C506
XR·C507
XR-C502 contains two singleand tWb dual-output 12L NOR
gates. All four gates share a
common injector.
4
2
1
Pin 16 '" Injector
Pin 8 '" Ground
XR-C503
Dual "0" FLIP-FLOP
XR-C503 contains two independent D-type flip-flops. Both
flip-flops share a common injector and trigger on positivegoing edges. Both the inputs
and outputs of each flip-flop
unbuffered.
When breadboarding with 12L kit parts included in the
design kit, a word of caution is in order: The high frequency capabilities of 12L gates in the kit, which have
buffered outputs, are to a large extent limited by the
parasitic capacitances associated with the package or
the external wiring on the circuit board. In the monolithic design, when the electrical connections are made internal to the chip and the outputs are buffered, these
parasitic package capacitances do not present a prob·
lem. However, when breadboarding with 12L kit parts
which have no buffered outputs, these package capacitances may limit the switching speeds obtainable at the
kit part breadboard stage. For this reason it is recommended that logic verification breadboards be built with
74CXX or 74LXX logic. The buffered 12L kit parts are
useful for circuit areas that are sensitive to the propagation delays and/or frequency limitations of the 12L
process.
Pin 16 "" Injector
Pin
a '"
Ground
XR-C504
BUFFERED DUAL-D FLIP-FLOP
XR-C504 is a buffered version of
the XR-C503 flip-flop array. Both
flip-flops contain Schottkybipolar input and output buffers
(see page 26). The two flip-flops
share a common injector which
is internally connected to V+ =
5V, the 12L gates are biased at
approximately 50 p.A gate and
are positive edge triggered.
COMPONENTS IN 12L DESIGN KIT
XR-C501
12L INVERTER ARRAY
Pin 16 '" V+
Pin 8 = Ground
Option
XR-C501
contains
three
multiple·output 12L inverters.
These three gates each have independent inputs and outputs,
however they share a common
injector.
XR-C505
DUAL J-K FLIP-FLOP
XR-C505 contains two independent J-K flip-flops which
share a common injector. Both
the inputs and outputs are comprised of unbuffered 12L gates.
Both flip-flops are positive edge
triggered.
Pin 1& '" Injector
Pin 8 '" Ground
Pin 16 = Injector
Pin 8 = Ground
2-48
FREQUENCY DIVIDER SECTION
XR-CS06
12L COMPATIBLE NPN TRANSISTOR ARRAY
IS
IS
The frequency divider section of the XR-C409 test circuit are made up of two D-type flip-flops internally connected in the ( 2) mode. These frequency dividers are
operated with serial clocking and parallel reset controls. The flip-flops operate on the negative transitions
of the clock input and reset with a high logic state.
When the circuit is reset, all the outputs go to a low
state. The logic polarities and timing sequence of the
circuit waveforms are shown in the following drawing.
XA-CS06 contains four small
signal NPN transistors. These
are equivalent to the transistors
available in the linear section of
the XA·400 Master·Chip.
Pi"' .. Subst'ate
XR-C507
12L COMPATIBLE PNP TRANSISTOR ARRAY
15
Il
CLOCK INPUT
(PIN 16)
XA-C507 contains two fourcollector laleral PNP transistors.
These devices are equivalenllo
the PNP transistors available in
the linear section of the XA-400
Masler-Chip.
RESET
(PIN 15)
~~
__________
~r-
2 OUTPUT
(PIN 14)
4 OUTPUTS
(PINS 2 AND 3)
_ _---oJ
TIMING DIAGRAM FOR FREQUENCY DIVIDER SECTION
XR·C409 12L EVALUATION CIRCUIT
The XR-C409 monolithic IC is a test circuit for evaluating the speed and performance capabilities of Exar's
Integrated Injection Logic (12L) technology. It is intended to familiarize the 12L user and the digital system designer with some of the performance features of 12L,
such as its high frequency capability and power speed
tradeoffs.
The XR-C409 12L test circuit is comprised of five separate evaluation blocks as shown below. Blocks 1 and 2
are D-type flip-flops which are internally connected as
frequency dividers. Each of these dividers provides buffered open collector outputs (Blocks 3, 4, and 5, etc.) to
be used for measuring gate propagation delays at different injector current levels. The XR-C409 evaluation
circuit is included as a part of Exar's 12L Design Kit.
1 MHz)
Low-Frequency «1 MHz)
In many of the applications, more than one product
type is recommended. In such cases, the user can
choose the device best suited to his specific application by either consulting with Exar's Applications department, or by reviewing the electrical specifications
of the individual devices involved.
Low-Power
Carrier-Tone Transceiver
Clock Generation (See Oscillators)
Low-Frequency « 1 MHz)
Low-Power
*ADVANCED INFORMATION
High-Frequency
Phase Locked
A
Clock Extraction
Phase Locked
Active Filters
XR·OS4, XR·094,
XR·096, XR·346,
XR·3403, XR·4202
Acoustical Couplers (See Modems)
XR·2206, XR·2207,
XR·2211
AID Conversion (Pulse Counting Type) XR·2240
Amplitude Detection
Phase· Locked AM Detection
XR·215/XR·222S,
XR-2212IXR-222S
Synchronous AM Detection
XR-S200, XR-220S,
XR-222S
XR-2276, XR-2277,
Amplitude Level Detection
XR-227S, XR-2279
XR-205, XR-2206
Amplitude Modulated Oscillator
XR-S200, XR-205
Crystal Controlled AM Oscillator
XR-2206, XR-2208,
Amplitude Modulation
XR·222S, XR-13600
Analog Computation
Analog Multiplication/Division
XR-2208, XR-2228
Analog Square/Square-Root OperationXR-220S
Analog-To-Frequency Conversion
XR-2209, XR-4151
Analog Sample· Hold
XR-13600IXR-082
Analog Semi-Custom Design
XR-A100, XR·B100,
(Master Chips)
XR-G100, XR·D100,
XR-F100, XR-G100,
XR-X100
Appliance Timing
XR-555, XR-556,
XR-558, XR-559,
XR-2240, XR-2242,
XR-2243
XR-5532, XR-5534
Audio Amplifier/Preamp
XR-2276, XR-2279
Audio Level Detector
XR-220S, XR-2216,
Automatic Gain Control (AGC)
XR-2228, XR·13600
PCM Signal Clock
Clock Pattern Generation
Clock Synchronization
High-Frequency (> 1 MHz)
Low-Frequency « 1 MHz)
Commandor (Speech/Data)
Current-to-Frequency Converter
Current Drive
XR-215/XR-2228
XR-567 A, XR·2211,
XR-L567
XR-L567
XR·2567
XR-555, XR-2209,
XR-2242
XR-L555, XR-L556,
XR-2243
XR-205
XR-215, XR·2212,
XR·2213
XR-210, XR·215,
XR-2212, XR-2213
XR-C262, XR·C277
XR-2240
XR·210, XR-215
XR-2212, XR-2213
XR·2216
XR-2206, XR-2207,
XR-2209
XR-2247, XR-2247A
o
Darlington Arrays
(High-Current, High-Voltage)
Data Synchronization
High-Frequency (>1 MHz)
Low-Frequency « 1 MHz)
DC/DC Converter (See
Switching Regulators)
3-2
XR-2200, XR-2201,
XR-2202, XR-2203,
XR-2204, XR·2001,
XR-2002, XR-2003,
XR-2004, XR-2011,
XR-2012, XR-2013,
XR·2014
XR-210, XR-215
XR-2212, XR-2213
XR-1524, XR-2524,
XR·3524, XR-1525A,
XR-1527A,
XR-2525A,
XR-3525A,
XR-2527A,
XR-3527A
Detector
FM
FSK
Tone
PSK
Amplitude Level
Amplitude Modulation
Differential Multiplier
Digital Sample/Hold
Digital Semi·Custom Design (l2L,
CMOS Gate Arrays)
Complete Digital Design (12L)
Complete Digital Design (CMOS)
Combined AnalogiDigital Design
Display Driver
Fluorescent
Bar·Graph
Plasma Displays
Division (Analog)
Division (Frequency)
Dual Opera1ional Amplifiers
Dual· 741 Type
High·Frequency (> 1 MHz)
Low·Frequency « 1 MHz)
XR-215, XR-2122
XR-210, XR-2211,
XR-14412, XR-2122
XR·567, XR·L567,
XR-2211, XR-2567,
XR-2122, XR-2123
XR-2276, XR-2279
XR-2208
XR-2228
XR-2240
Frequency Division
Frequency Doubling
FM Detection
High·Frequency (> 1 MHz)
Low·Frequency « 1 MHz)
Low·Power
Dual Tone Detector
XR-215
XR-215, XR-2212,
XR-2213
FM Generation
High·Frequency (> 1 MHz)
Low·Frequency « 1 MHz)
XR-200, XR-300,
XR-500
CMA, CMB, CMC,
CMD
XR-400
XR·S200, XR-205
XR-2206, XR-2207,
XR-2209, XR-8038
Frequency Multiplication (Synthesis)
High·Frequency (> 1 MHz)
Low·Frequency « 1 MHz)
Frequency Translation
High·Frequency (> 1 MHz)
Low·Frequency «1 MHz)
FrequencyIVoltage (FIV) Converter
Wideband
Narrow·Band
FSK Detection (Decoding)
High·Frequency (> 1 MHz)
Low·Frequency « 1 MHz)
FSK Generation (Encoding)
High·Frequency (> 1 MHz)
Low·Frequency « 1 MHz)
XR-2271, XR-2272,
XR-6118, XR-6128
XR-2276, XR-2277,
XR-2278, XR-2279
XR-2284, XR-2288
XR-2208
XR-2240
XR-1458, XR-4558,
XR-4739
XR-5532, XR-5533
XR·082, XR·083
XR-13600
XR-556, XR-2556,
XR-2567
XR·L556
XR-2567
Low·Noise
Bipolar FET
Transconductance
Dual Oscillator
XR-215
XR-2212, XR-4151,
XR-2213
XR-320, XR-555,
XR-2240, XR-2242,
XR-2243
XR-2208, XR-2228
Sinusoidal Output
Multiple Frequency Levels
FSK Modem (Modulator/
Demodulator)
XR·S200, XR-215
XR·2212, XR-2213
XR-215/XR-2228
XR-2212IXR-2228
XR-4151
XR-2212, XR-2213
XR-210
XR-2211, XR-14412,
XR-210
XR-2206, XR-2207,
XR-14412, XR-2121
XR-2206, XR-14412,
XR-2121
XR-2207
XR-2211/XR-2206
XR-2211IXR-2207,
XR-14412,
XR-2121/XR-2122
E
Electronic Gain Control
G
XR-2208, XR-2216,
XR-2228, XR-13600
XR-2216
Expandor (Speech/Data)
Gate Arrays (See
Digital Semi·Custom)
F
Filters
Active Filters
Tracking Filters (Phase Locked)
Switched Capacitor
Floppy Disk
Read Amplifier
Write Amplifier
Fluorescent Display Driver
Medium Voltage (s 50V)
High·Voltage (>50V)
Bar·Graph Display
Frequency Detection (See
Tone Detection)
High·Frequency (> 1 MHz)
Low·Frequency « 1 MHz)
Multiple Frequency
Frequency Discriminator (See
FN Converter)
XR-200, XR-300,
XR-400, XR-500
CMA, CMB, CMC,
CMD
XR-205, XR-2206,
XR-8038
XR-3403
XR·094, XR-346,
XR-3403, XR-4202,
XR-13600
Generator (See
Function Generators)
Ground·Sensing Op Amps
Gyrator Design
XR·084, XR·094,
XR-346, XR-3403,
XR-4202
XR·S200, XR-215,
XR-2212
XR·2120, XR-2103
H
XR-3470A, XR-3470B
XR-2247, XR-2247A
Hammer Driver (See High·
Current Drivers)
XR-2271, XR-2272
XR-6118, XR-6128
XR-2276, XR-2277,
XR-2278, XR-2279
High·Voltage Driver
XR-215/XR-2228
XR-567, XR-2211,
XR-2213
XR-2567
Indicator, Amplitude (See
AM Detector, Level Detector)
3-3
XR-2200, XR-2201,
XR-2202, XR-2203,
XR-2204
XR-6118, XR-6128,
XR-2284, XR-2288
XR-2208, XR-2228,
XR-2276, XR-2279
Indicator, Frequency (See
Frequency Detector)
Intercom
XR-215, XR-2212,
XR-4151
XR-2206IXR-2211,
XR-2567
XR-555, XR-L555,
XR-556, XR-L556,
XR-558, XR-559
Interval Timing
Programmable Quad Op Amp
Ground Sensing Quad Op Amp
Ultra Low-Noise Op Amp
Bipolar FET Op Amps
Dual Bipolar FET
Quad Bipolar FET
Programmable Bipolar FET
L
LED Driver
XR-2200, XR-2201,
XR-2202, XR-2203,
XR-2204
XR-320, XR-2207
XR-2206, XR-2207,
XR-2209
XR-2216
XR-1488
XR-1489A
XR-2242, XR-2243
XR-L555
XR-L567
XR-L555, XR-L556,
XR-2243
XR-L555, XR-L556,
XR-2243
Linear-Ramp Generation
Linear-Sweep Oscillator
Line Compandor
Line Driver (RS-232C Spec)
Line Receiver (RS-232C Spec)
Long Delay Generation
Low-Power Oscillator
Low-Power PLL
Low-Power Timer
Low-Voltage Timer/Oscillator
XR-4136, XR-4212,
XR-4741
XR-094, XR-095,
XR-096, XR-346,
XR-4202
XR-3403
XR-5532, XR-5333,
XR-5534
XR-082, XR-083
XR-084
XR-094, XR-095,
XR-096
Operational Transconductance
Amplifier (OTA)
XR-13600
Oscillators (See Function Generators)
High-Frequency Oscillator
XR-205, XR-210,
(>1 MHz)
XR-215
Low-Frequency Oscillator
XR-2206, XR-2207,
XR-2209, XR-8038,
«1 MHz)
XR-8038A
High-Current Output Oscillator
XR-567
Low-Cost Oscillator
XR-555, XR-L555
Low-Power Oscillator (Single)
XR-L555, XR-L567
Low-Power Oscillator
XR-L556, XR-2243
Dual Oscillator
XR-558, XR-559
Sinusoidal Output
XR-205, XR-2206,
XR-8038
FSK Keyed Oscillator
XR-2206, XR-2207
Oscillator with Quadrature Outputs XR-2212
M
P
Micropower Circuits (See Low-Power)
Micropower Oscillator
XR-L555, XR-L556
Micropower Tone Decoder (PLL)
XR-L567
Micropower Timer
XR-L555, XR-L556,
XR-2243
Missing Pulse Detection
XR-320, XR-555,
XR-L555
Modem Filter Design
XR-346, XR-3403,
XR-4202, XR-2120,
XR-2103
Modem (Frequency-Shift Keyed)
XR-210, XR-2206,
XR-2207, XR-2211,
XR-14412,
XR-2121/XR-2122
(Phase-Shift Keyed)
XR-2121/XR-2122
XR-2123
Modulators (See Multipliers)
Amplitude Modulator
XR-205, XR-2206
FSK Modulator
XR-2206, XR-2207,
XR-2121
Frequency Modulator
XR-205, XR-2206,
XR-2209
PSK Modulator
XR-2121*, XR-2123
Phase Modulator
XR-2212
Motor-Speed Control
XR-2208, XR-2212,
XR-2213
Multi-Function PLL
XR-S200
Multiplier, Analog
XR-2208, XR-2228
PCM Repeater (See Regenerator)
Phase-Comparator (Phase-Detector)
Phase-Locked Loop
High-Frequency (> 1 MHz)
Low-Frequency « 1 MHz)
Ultra-Stable
FM Detector
FSK Detector
Tone Detector
Low-Power
AM Detector
Stero Decoder
Plasma Display Driver
Power Supply Supervision
Power-On-Reset
Precision Oscillator
Precision PLL
Process Controller
Programmable Op Amp (See
Op Amps)
Quad Bipolar
0
Quad Bipolar FET
Operational Amplifiers
Single Op Amp
Dual Op Amp
Quad Op Amp
XR-5534
XR-082, XR-083,
XR-1458, XR-4558,
XR-4739
XR-084, XR-3403,
Programmable Oscillator
Programmable Timer
PSK Generator (Bipolar-phase
and Quad-phase
3-4
XR-C240, XR-C262,
XR-C277
XR-2208, XR-2228
XR-S200, XR-210,
XR-215
XR-567, XR-L567,
XR-2567, XR-2211,
XR-2212, XR-2213
XR-2211, XR-2212
XR-215, XR-2212
XR-210, XR-2211
XR-567A, XR-L567,
XR-2567
XR-L567
XR-215/XR-2228,
XR-2212IXR-2228
XR-1310
XR-2284, XR-2288
XR-1543
XR-320, XR-555,
XR-L555
XR-2206, XR-2209,
XR-8038A
XR-2212, XR-2213
XR-2206/XR-2211,
XR-2240, XR-4151
XR-346, XR-346-2,
XR-4202
XR-094, XR-095,
XR-096
XR-2206, XR-2207
XR-2240
XR-205, XR-2206,
XR-2228, XR-2121,
XR-2123
Pulse Blanking
Pulse-Code Modulation (PCM)
Regenerator
Pulse Counting
Pulse Generation
Pulse-Position Modulation (PPM)
Pulse-Proportioned Servo Controller
Pulse Shaping
Pulse Stretching
Pulse-Width Modulation (PWM)
Pulse-Width Modulating Regulator
Low-Frequency « 1 MHz)
Simultaneous AM/FM Detection
XR-556, XR-2556
XR-C240, XR-C262,
XR-C277
XR-2240
XR-320, XR-555,
XR-L555, XR-556
XR-320
XR-2264, XR-2265,
XR-2266
XR-555, XR-556,
XR-558, XR-559
XR-320, XR-555,
XR-556
XR-320, XR-555
XR-1524, XR-2524,
XR-3524, XR-1525A,
XR-2525A,
XR-3525A,
XR-1527A,
XR-2527A,
XR-3527A
Simultaneous AM/FM Generation
Sine Wave Converter
Sine Wave Generator
Solenoid Driver (See
Relay Driver)
Speech Compandor
Square-Root Extraction
Squaring (Analog)
Stable PLL
Stereo Demodulator (Decoder)
Suppressed Carrier AM Generator
Sweep Generation (See
Saw-Tooth Generation)
Switching Regulators
a
Quadrature AM Detector
Quadrature-Output Oscillator
Synchronization (Clock Frequency)
Synchronous AM Detection
XR-2208, XR-2228
XR-2212
R
Radio-Controlled Servo Driver
Radio-FM I.E Demodulation
-AM 1. F. Detection
Relay Driver (See
Hammer Driver)
Remote-Control Timer/Sequencer
Remote-Control Transceiver
Reset Controller (See
Power-On Reset)
Digital (12L) Master-Chips
Digital (CMOS) Master-Chips
Sequential Timing
Sequential Tone Decoding
Servo ControlierlDriver
Signal Conditioning
High-Frequency (> 1 MHz)
XR-1524, XR-2524,
XR-3524, XR-1525A,
XR-2525A, XR-3525A,
XR-1527A, XR-2527A,
XR-3527A, XR-2230,
XR-494, XR-495
XR-215, XR-2212
XR-215/XR-2228,
XR-2212/XR-2228
T
XR-2264, XR-2265,
XR-2266
XR-215
XR-2228
XR-2200, XR-2201,
XR-2202, XR-2203,
XR-2204
XR-L555, XR-L556,
XR-2240
XR-567A, XR-L567,
XR-2567
XR-L555, XR-L556
Telecommunication Circuits
PCM Repeater (T1-type)
Speech Compandor
Tone Decoder (PLL-type)
Tone Encoder
Timing Circuits (Timers)
General Purpose Timers - Single
General Purpose Timers - Dual
General Purpose Timers - Quad
Low-Power Timers
Long Delay Timer
Programmable Timer
Tone Decoder (PLL-type)
General Purpose - Single
General Purpose - Dual
Precision
Low-Power
Tone Encoder
Tracking Filter
High-Frequency (>1 MHz)
Low-Frequency « 1 MHz)
Tracking Regulator
S
Sample/Hold (See Bipolar
FET Op Amps)
Saw-Tooth Generator
Semi-Custom Design
Linear Master-Chips
XR-2212, XR-2213
XR-215/XR-2228,
XR-2212/XR-2228
XR-205, XR-2206
XR-2212/XR-2228
XR-205, XR-2206,
XR-8038, XR-8038A
XR-2200, XR-2201,
XR-2202, XR-2203,
XR-2204
XR-2216
XR-2208
XR-2208, XR-2228
XR-2211, XR-2212
XR-1310
XR-205, XR-2206,
XR-2208, XR-2228
XR-320, XR-2207
XR-082, XR-084
XR-320, XR-2207
XR-A100, XR-B100,
XR-C100, XR-D100,
XR-E100, XR-F100,
XR-G100, XR-H100,
XR-L100, XR-M100,
XR-U100, XR-V100,
XR-W100, XR-X100
XR-200, XR-300,
XR-400, XR-500
CMA, CMB, CMC,
CMD
XR-566, XR-L566,
XR-588, XR-559
XR-567 A, XR-L567
XR-2567
XR-2264, XR-2266
XR-C240, XR-C262,
XR-C277
XR-2216
XR-567, XR-L567,
XR-2211, XR-2567
XR-2206, XR-2207
XR-320, XR-555
XR-556, XR-2556
XR-558, XR-559
XR-L555, XR-L556,
XR-2243
XR-2242, XR-2243
XR-2240
XR-567A
XR-2567
XR-2211, XR-2213
XR-L567
XR-2206, XR-2207
Transceiver (Wireless Intercom)
Triangle-to-Sine Wave Converter
Triangle Wave Oscillator
TV Sound Detection
XR-S200, XR-215
XR-2212, XR-2213
XR-1468, XR-4194,
XR-4195
XR-2567
XR-2208, XR-2228
XR-2206, XR-2207,
XR-2209, XR-8038
XR-215
U
Ultra Low-Frequency Oscillator
Ultrasonic Remote Control
XR-S200, XR-215,
XR-2212
Universal Sine Wave Converter
3-5
XR-2242, XR-2243
XR-567, XR-2211,
XR-2567
XR-2212/XR-2228
VOltage-to-Frequency (V/F)
Conversion
v
Voltage-Controlled Amplifier
Voltage-Controlled Oscillator (VCO)
High-Frequency (>1 MHz)
Low-Frequency « 1 MHz)
Ultra-Stable
Sinusoidal Output
Wide Linear Sweep
VOltage-to-Current Conversion
XA-2209, XA-4151
W
XA-2208, XA-2228,
XA-13600
Waveform Generator (See Oscillators)
XA-205
High-Frequency (> 1 MHz)
XA-2206, XA-2209,
Low-Frequency « 1 MHz)
XA-8038, XA-8038A
XA-2208, XA-2228
Waveform Shaping/Modulation
Wideband Discriminator (FM)
XA-S200, XA-215
High-Frequency (>1 MHz)
XA-2212, XR-4151
Low-Frequency « 1 MHz)
XA-215, XA-567A,
Wireless Intercom
XA-2212
XA-S200, XA-205
XA-2206, XA-2207,
XA-2209, XA-8038A
XA-2206, XA-2207,
XA-2209
XA-2206, XA-8038,
XA-8038A
XA-2207, XA-2209
XA-13600
3-6
AN·01
Stable FSK Modems featuring
the XR·2207, XR·2206 and XR·2211
INTROOUCTION
The circuit connection for the XR-2206 FSK Generator
is shown in Figure 1. The data input is applied to Pin g.
A high-level signal selects the frequency (1/R6C3) Hz; a
low level signal selects the frequency (1/R7C3) Hz, (resistors in ohms and capacitors in farads). For optimum
stability, R6 and R7 should be within the range of 10 kO
to 100 kO. The voltage applied to Pin g should be selected to fall between ground and V +.
Frequency-shift keying (FSK) is the most commonly
used method for transmitting digital data over telecommunications links. In order to use FSK, a modulator/
demodulator (modem) is needed to translate digital 1's
and O's into their respective frequencies and back
again. This application note describes the design of a
modem using state-of-the-art Exar devices specifically
intended for modem application.
Note: Over and under voltage may damage the device.
The devices featured in this application note are the
XR-2206 and XR-2207 FSK Modulators, and the
XR-2211 FSK demodulator with carrier detect capability. Because of the superior frequency stability of these
devices (typically 20 ppm/oC), a properly designed modem will be virtually free of the temperature and
voltage-dependent drift problems associated with many
other designs. In addition, the demodulator performance is independent of incoming signal strength variation over a 60 dB dynamic range. Because bias voltages are generated internally, the external parts count
is much lower than in most other designs. The modem
designs shown in this application note can be used with
mark and space frequencies, anywhere from several
Hz to 100 kHz.
Potentiometers, RS and Rg, should be adjusted for minimum total harmonic distortion. lri applications where
minimal distortion is unnecessary, Pins 15 and 16 may
be left open-circuited and RS may be replaced by a
fixed 2000 resistor.
5.1K
PRINCIPLES OF OPERATION
+12V
0-.,....-----1
THE XR-2206 FSK MODULATOR
FEATURES
Typically 20 ppm/DC Temperature Stability
Choice of 0.5% THD Sine Wave, Triangle,
or Square Wave Output
Phase-Continuous FSK Output
Inputs are TIL and CMOS Compatible
Low-Power Supply Sensitivity (0.01 %)
R••
Low-Power Supply Sensitivity (0.01 %N)
Split or Single Supply Operation
Low External Parts Count
R7.
v+
Figure 1. The XR-2206 Sinusoidal FSK Generator.
The XR-2206 is ideal for FSK applications requiring the
spectral purity of a sinusoidal output waveform. It offers
TIL and CMOS compatibility, excellent frequency stability, and ease of application. The XR-2206 can typically
provide a 3-volt pop sine wave output. Total harmonic
distortion can be trimmed to 0.5 %. If left untrimmed, it
is approximately 2.5%.
In applications where a triangular output waveform is
satisfactory, Pins 13 through 16 may be left opencircuited.
The output impedance at Pin 2 is about 6000, with ac
coupling normally being used.
3-7
AN·01
+12V
THE XR·2207 FSK MODULATOR
FEATURES
RL
5.1K
4.7K
Typically 20 ppm/DC Temperature Stability
Phase-Continuous FSK Output
Provides Both Triangle and Square Wave Outputs
Operates Single-Channel or Two-Channel Multiplex
Inputs are TIL and CMOS Compatible
Split- or Single-Power Supply Operation
Low-Power Supply Sensitivity (0.15%/V)
Low External Parts Count
The XR-2207 is a stable FSK generator which is designed for those applications where only a triangle or
square wave output is required. It is capable of either
single-channel or two-channel multiplex operation, and
can be used easily with either split- or single-power
supplies.
Figure 2. The XR·2207 FSK Modulator Single-Supply
Operation.
+6V
Figure 2 shows the XR-2207 using a single-supply and
Figure 3 shows split-supply operation. When used as an
FSK modulator, Pin 8 and 9 provide the digital inputs.
When the 2207 is used with a split-supply; the threshold
at these pins is approximately + 2 volts, which is a level
that is compatible with both TTL and CMOS logic forms.
When used with a single-supply, the threshold is near
mid-supply and is CMOS compatible. Table 1 shows
how to select the timing resistors, R1 through R4, to determine the output frequency based on the logic levels
applied to Pin 8 and 9. For optimum stability, the values
of R1 and R3 should be selected to fall between 10 kO
and 100 kO.
R,
4.7K
rn~"'-mil-~-o MIN. ...
JUUl OUTPUT
IID---+'--O
(ID----O -6V
ID--=--o DATA INPUT.
Ul__J!l---o ~=::~~~::~i~TOR
With Pin 8 grounded, Pin 9 serves as the data input. A
high-level signal applied to Pin 8 will disable the oscillator. When used in this manner, Pin 8 of the XR-2207
serves as the channel select input. For two-channel
multiplex operation, Pin 4 and 5 should be connected
as shown by the dotted lines. (For single channel operation, Pin 4 and 5 should be left open-circuited.)
Figure 3. The XR-2207 FSK Modulator Split-Supply Operation.
Tabla 1.
XR-2207 FSK Input Control Logic
Logic Level
The XR-2207 provides two outputs: a square wave at
Pin 13 and a triangle wave at Pin 14. (For safe operation, current into Pin 13 should be limited to 20 mA.)
When used with a split-supply, the triangle wave peakto-peak amplitude is equal to V - and the dc level is
near ground. Direct coupling is usually used. With a
single-supply, the peak-to-peak amplitude is approximately equal to one-half/v + , the dc level is approximately at mid-supply, and ac coupling is usually necessary. In either case, the output impedance is typically
100 and is internally protected against short circuits.
Pin 8
Pin 9
Active
Timing
Resistor
L
L
Pin 6
Output
Frequency
-1Co R1
L
H
Pins 6 and 7
H
L
Pin 5
_1_+_1_
Co R1
Co R2
1
CoR3
H
The square wave output has an npn open-collector configuration. When connected as shown in Figure 2 and 3,
this output voltage will swing between V + and the voltage at Pin 12.
H
Pin 4 and 5
_1_+_1_
CoR3
Units: Resistors - Ohms; CapaCitors Frequency - Hz
3-8
CoR4
Farads;
AN·01
The XR-2211 FSK DEMODULATOR
The XR-2211 has three npn open-collector outputs,
each of which is capable of sinking up to 5 mA. Pin 7 is
the FSK data output, Pin 5 is the Q lock-detect output
which goes low when a carrier is detected, and Pin 6 is
the Q lock-detect output which goes high when lock is
detected. If Pin 6 and 7 are wired together, the output
signal from these terminals will provide data when FSK
is applied, and will be LOW when no carrier is present.
FEATURES
Typically 20 ppm/oC Temperature Stability
Simultaneous FSK and Carrier-Detect Output
Outputs are TIL and CMOS Compatible
Wide Dynamic Range (2 mV to 3V rms)
Split or Single Supply Operation
Low-Power Supply Sensitivity (0.05%/V)
Low External Parts Count
If the lock·detect feature is not required, Pins 3, 5 and 6
may be left open-circuited.
The XR-2211 is an FSK demodulator which operates on
the phase-locked loop principle. Its performance is virtually independent of input signal strength variations,
over the range of 2 mV to 3V rms.
Figure 4 shows the circuit connection for the XR-2211.
The center frequency is determined by fo = (1/Cl R4)
Hz, where capacitance is in farads and resistance is in
ohms. Calculation for fo should fall mid-way between
the mark and space frequencies.
The tracking range (± t.f) is the range of frequencies
over which the phase-locked loop can retain lock with a
swept input signal. This range is determined by the formula: t.f = (R4fO/R5) Hz. t.f should be made equal to,
or slightly less than, the difference between the mark
and space frequencies. For optimum stability, choose
an R4 between 10 kO and 100 kO.
Figure 4: The XR-2211 FSK Demodulator with Carrier
Detect
The capture range (± t.fd is the range of frequencies
over which the phase-locked loop can acquire lock. It is
always less than the tracking range. The capture range
is limited by C2, which, in conjunction with R5, forms
the loop filter time constant. In most modem applications, t.fc = (80%-99%) t.f.
VPD
k---1
IE---"::"I
2VREF
-----------J
I
-':.f
I
I
t"-"{ ~
m
j
:
I
I
y,vREF- -
~
1_-'- ___ + - - - - - Iii
~VREF
The loop-damping factor
determines the amount of
overshoot, undershoot, or ringing present in the phaselocked loop's response to step change in frequency. it
is determined by I = 1/4 Cl/C2. For most modem applications, choose I '" 112.
Lock Range
~~
-
I
VREF
r-+----
I
-l- - - 1- -
!
IS
1
'0
1M
-------------------
The FSK output filter time constant (TF) removes chatter from the FSK output. The formula is: TF = RFCF
Normally calculate TF to be approximately equal to [0.31
(baud rate)] seconds.
XR-2211 TRACKING CHARACTERISTICS
The lock-detect filter capacitor (CD) removes chatter
from the lock-detect output. With RD = 510 kO, the
minimum value of CD can be determined by: CD(/Lf) '"
16/capture range in Hz.
As seen above, the XR-2211 produces at its phase detector output a voltage VpD, which has a peak to peak
value equal to about VREF for a frequency swing from
fM (mark) to FS (space). The DC level VPD will be about
VREF (V2+ - .65).
Note: Excessive values of CD will unnecessarily slow
the lock-detect response time.
3-9
AN-01
CIRCUIT DESIGN
DESIGN EXAMPLES
I. Design a modem to handle a 10 kilobaud data rate, using
Table 2 shows recommended component values for the
three most commonly used FSK bands. In many instances, system constraints dictate the use of some
non-standard FSK bands. The XR-2206/XR-2207/XR2211 combination is suitable for any range of frequencies from several Hertz to 100 kiloHertz.
the minimum necessary bandwidth.
A. Frequency Calculation
Because we want to use the minimum possible
bandwidth (lowest possible upper frequency) we
will use a 55:100 frequency ratio. The frequency
difference, or 45% of the upper frequency, will
be 83 % of 10,000. We therefore chose an upper
frequency:
Here are several guidelines to use when calculating
non-standard frequencies:
• For maximum baud rate, choose the highest upper
frequency that is consistent with the system bandwidth.
83 xl 0,000 = 18.444 kHz", 18.5 kHz.
45
• The lower frequency must be at least 55 % of the upper frequency (less than a 2:1 ratio).
and the lower frequency:
0.55 x 18.5 kHz = 10.175 kHz.
• For minimum demodulated output pUlse-width jitter,
select an FSK band whose mark and space frequencies are both high, compared to the baud rate. (i.e.,
for a 300 baud channel, mark and space frequencies
of 2025 Hz and 2225 Hz would result in significantly
less pulse-width jitter than 300 Hz and 550 Hz).
B. Component Selection
1. For the XR-2207 FSK modulator, set Rl '" 30
kO. Now, select a value of Co to generate
10.175 kHz with Rl:
10.175 kHz = l/(Co x 30,000); Co = 3300pF.
• For any given pair of mark and space frequencies,
there is a limit to the baud rate that can be achieved.
When maximum spacing between the mark and
space frequencies is used (where the ratio is close to
2:1) the relationship
18.500 khz - 10.175 kHz = 8.325 kHz =
1/CoR2; R2 = 36 kO.
A good choice would be to use 10 kO potentiometers for R1A and R2A, and to set Rl B = 24 kO
and R2B = 30 kO.
mark-space frequency difference (Hz)
------'---------'----'------'------'- >83%
maximum data rate (baud)
should be observed.
2. For the XR-2206, we can make R7 equal to
Rl, and C3 equal to Co above. To determine
R6:
For narrower spacing, the minimum ratio should be
about 67%.
18.5 kHz = 1/R6C3; R6 = 16 kO
The values shown in Table 2 may be scaled proportionately for mark and space frequencies, maximum baud
rate, and (inversely) capacitor value. It is best to retain
(approximately) the resistor values shown.
Use at 10 kO potentiometer for R6A and set
R6B = 13 kO.
Table 2.
Recommended Component Values for Typical FSK Bands
XR-2207
FSK Band
Baud
Rate
fL
fH
XR-220S
R1A R1B R2A R2B
R3A R3B R4A R4B
CD
XR-2211
RSA RSB R7A R7B
C3
R4A R4B
R5
C1
C2
CF
CD
300 1070 1270 10
20
100 100 .039
10
18
10
20
.039
10
18
100 .039 .01
.005
.05
300 2025 2225
10
18
150 160 .022
10
16
10
18
.022
10
18
200 .022 .0047 .005
.05
1200 1200 2200 20
30
20
10
16
20
30
.022
10
18
Units: Frequency -
Hz; Resistors -
36 .022
kO; Capacitors -
j.tF
3-10
30 .027 .0033 .0022 .01
AN·01
III. Design a 2 channel multiplex FSK modulator to operate at
the following pairs of mark and space frequencies: 600 Hz
and 900 Hz, and 1400 and 1700 Hz (each of these channels could handle about 400 baud).
3. For the XR-2211 demodulator, we need to
first determine R4 and C1· First, fo = (fL +
fH)/2 = (10.175 + 18.500)/2 = 14.338 kHz.
If we make R4 = 25 kU, then 1/(C1 x 25,000)
= 14,338; C1 = 2790 pF ... 2700 pF. With
that value of C1, the precise value of R4 is
now 25.8 kU. Select R4B = 18 kU and use a
10 kU for R4A.
For this task, we will use the XR-2207. The only real
consideration here is that, if possible, we want to
keep the following resistances all between 10 kU
and 100 kU: R1, R1/R2, R3 and R3/R4. The ratio between the maximum and minimum frequencies is
less than 3:1, so we should have no trouble meeting
this criterion. If we set our maximum frequency with
an R of about 20 kU, we have: 1700 = 11
(Co x 20,000); Co = 0.029 ILf which is approximately equal to 0.033 ILf.
C. Frequency Component Selection
1. To calculate R5, we first need our af, which is
18,500 - 10.175, or 8.325 kHz:
8325 = (25,800 x 14,338)/R5
R5 = 44.4 kU ... 47 kU.
2. To determine C2 use r = 1/2 = 114
Then, C2 = 1/4C1; C2 = 670 pF:
Calculating R1 using 600 Hz and 0.033 ILf, we get
R1 = 50,5 kU. We can use R1 B = 47 kU and R1A =
10 kU. For R2, we get 101 kU. Use R2B = 91 kU and
R2A = 20 kU. To determine R3, use: 1400 Hz = 11
R3Co, which gives us R3 = 21.6 kU. Use R3B = 18
kU and R3A = 5 kU. R4 must generate a 300 Hz
shift in frequency, the same as R2. Therefore, set
R4 equal to R2.
C1/C2.
3. To select CF, we use TF = [O.3/(baud rate)]
seconds:
TF = 0.3/10,000 = 30 ILsec.
with
v+
51NEWAVE
OUTPUT
RF = 100 kU, CF = 300 pF
Rl
IA Q---f--....=--'7.::;-{:1]
O. Lock Range Selection
To select CO, let us start with the actual lock
range:
4.7K
saUAREWAVE
!Ii}-:==-_~F.oSK
S.lK
OUT
DATA INP:J-Il
UI__-.J:D''--=-----O"
af = R4fo/R5 Hz = 7870 Hz
If we assume a capture range of 80%:
afC
10K
= 6296 Hz
therefore, our total capture range of ± afC is
12,592 Hz. Our minimum value for Co is (161
12,592) ILf or 0.0013 ILl.
FSK IN
E. Completed Circuit Example
See Figure 5.
6----j
5.1K
DATA OUT
II. Design a 3 kilobaud modem to operate with low output jitter. The bandwidth available is 13 kHz.
CARRIER DETeCT
10K
v+
For this modem, we can take the values from two
for the 300 baud modem operating at 1070 Hz and
1270 Hz, multiply our baud rate and mark and
space frequencies by ten, and divide all capacitor
values on the table by ten. Resistor values should
be left as they are.
Figure 5: Full Duplex FSK Modem Using XR-2206 and
XR-2211. (See Table 2 for Component Values.)
3-11
AN·01
Adjustment Procedure
The only adjustments that are required with any of the
circuits in this application note are those for frequency
fine tuning. Although these adjustments are fairly simple and straightforward, there are a couple of recommendations that should be followed.
the lock range. There are several ways that fo can
be monitored:
The XR·2207: Always adjust the lower frequency first
2. Open R5 and monitor Pin 13 or 14 with a highimpedance probe; or
1. Short Pin 2 to Pin 10 and measure fo at Pin 3
with Co disconnect;
with R1 8 or R38 and a low level on Pin 9. Then with
a high level on Pin 9, adjust the high frequency using R28 or R48· The second adjustment affects only the high-frequency, whereas the first adjustment
affects both the low- and the high-frequencies.
3. Remove the resistor between Pin 7 and 8, and
find the input frequency at which the FSK output changes state.
The XR·2206: The upper and lower frequency adjust-
Note: Do NOT adjlistthe center frequency of the XR·2211
by monitoring the timing capacitor frequency with every·
thing connected and no input signal applied.
ments are independent, and the sequence is not
important.
The XR·2211: With the input open-circuited, the loop-
For further information regarding the use of the XR2207, XR-2206 and XR-2211 refer to the individual product data sheets.
phase detector output voltage is essentially undefined and VCO frequency may be anywhere within
3-12
AN·02
XR·C240 Monolithic PCM Repeater
INTRODUCTION
The XR-C240 is a monolithic repeater circuit for PulseCode Modulated (PCM) telephone systems. It is designed to operate as a regenerative repeater at 1.544
Mega bits per second (Mbps) data rates on T-1 type
PCM lines. The device is packaged in hermetic 16-pin
DIP package and is designed to operate over a temperature range of -40·C to +85·C. It contains all the basic functional blocks of a regenerative repeater system
including Automatic Line Build-out (ALBO) and equalization, and is insensitive to reflections caused by cable
discontinuities. Compared to conventional repeater designs using discrete components, the XR-C240 monolithic repeater IC offers greatly improved reliability and
performance and provides significant savings in power
consumption and system cost.
SIGNAL FLOW -
I
~II
_
SIGNAL FLOW
Figure 1. Block Diagram of a Bi·directional Digital
Repeater System.
THE T·1 REPEATER SYSTEM:
The T-1 Repeater Line is designed to provide a transmission capability for 24 two-way voice frequency signals which are transmitted digitally using a Pulse-Code
Modulation (PCM) technique. The system operates at a
data rate of 1.544 Mbps, with bipolar data pulses. It can
operate on either pulp- or polyethylene-insulated paired
cable that is either pole mounted or buried. Operation is
possible with a variety of wire gauges, provided that the
total cable loss at 772 kHz is less than 36 dB. Thus, the
system can operate satisfactorily on nearly all paired
cables which are used for voice frequency trunk circuits.
The XR-C240 monolithic IC replaces about 90% of the
electronic components and circuitry within the "digital
repeater" sections of Figure 1. Thus, a bi-directional repeater system would require two XR-C240 ICs, one for
each direction of information flow.
Figure 2 shows the functional block diagram of one of
the digital repeater sections, along with the external
zener regulator. The basic system architecture shown
in the figure is the same as that utilized in the design of
the XR-C240 monolithic IC.
The transmission system is designed to operate with
both directions of transmission within the same cable
sheath. The system performance is limited primarily by
near-end crosstalk produced by other systems operating within the same cable sheath. In order to insure that
the probability of a bit error is less than 10 - 6, the maximum allowable repeater spacing, when used with 22gauge pulp cable, is approximately 6000 feet.
Ii
BIPOLAR
OUTPUT
The details of the T-1 type PCM systems are well covered in the literature listed in References 1 through 5.
Figure 1 shows the block diagram of a bi-directional
PCM repeater system consisting of two identical digital
regenerator or repeater sections, one for each direction
of transmission. These repeaters share a common
power supply. The dc power is simplexed over the
paired cable and is extracted at each repeater by
means of a series zener diode regulator.
Figure 2. Functional Block Diagram of a Digital PCM
Repeater Section.
3-13
AN·02
The supply currents IA and IB drawn from the two supply voltages applied to the chip are specified to be within the following limits:
In terms of the functional blocks shown in Figure 2, the
basic operation of the repeater can be briefly explained
as follows:
a. Current from B.2V supply voltage, IA:
The bipolar signal, after traversing through a dispersive,
noisy medium is applied to a linear amplifier and automatic equalizer. It is the function of this circuit to provide the necessary amount of gain and phase equalization and, in addition, to band limit the signal in order to
optimize the performance of the repeater for near-end
crosstalk produced by other systems operating within
the same cable sheath.
1.lmA:s; IA:S; 2.5mA
b. Current from 4.3V supply voltage, IB:
6mA:s; IB :s; 11mA
The external components necessary for proper operation of the circuit are shown in Figure 5, in terms of the
The output signals of the preamplifier which are balanced and of opposite phases are applied to the clock
extraction circuit and also to the pulse regenerator. The
signals applied to the clock extraction circuit are rectified and then applied to a high-Q resonant circuit. This
resonant circuit extracts a 1.544 MHz frequency component from the applied signal. The extracted signal is
first amplified and then used to control the time at
which the output signals of the preamplifier are sampled and also to control the width of the regenerated
pulse.
It is the function of the pulse regenerator to perform the
sampling and threshold operations and to regenerate
the appropriate pulse. The regenerated pulse is in turn
applied to a discrete switch which is used to drive the
next section of the paired cable.
REFERENCES ON PCM REPEATERS:
1. Mayo, J. S., "A Bipolar Repeater for Pulse Code Sig·
nals," B.S.T.J., Vol. 41, January, 1962, pp. 25-97.
2. Aaron, M. R., "PCM Transmission in the Exchange
Plant," B.S.T.J., Vol. 41, January, 1962, pp. 99·143.
3. Davis, C. G., "An Experimental Pulse Code Modulation System for Short-Haul Trunks," B.S.T.J., Vol. 41,
January, 1962, pp. 1-25.
4. Fultz, K. E., and Penick, D. B., "The T-1 Carrier System," B.S.T.J., Vol. 44, September, 1965, pp. 14051452.
5. Tarbox, R. A., "A Regenerative Repeater Utilizing Hybrid IC Technology," Proceedings of International
Communications Conference, 1969, pp. 46-5 46·10.
Figure 3. Package Diagram of XR-C240 Monolithic
PC M Repeater.
Y++
+
Y22
3.9V
_18
+
7
8.2V
Y21
OPERATION OF THE XR-C24D
XR-C240
+
t
The XR-C240 combines all the functional blocks of a
PCM repeater system in a single monolithic IC chip.
The pin connections for each of the functional circuits
within the repeater chip are shown in Figure 3, for a
16-pin dual-in-line (DIP) package.
4.3Y
!
The circuit is designed to operate with two positive supply voltages, V++ andV+ which are nominally set to
be B.2V and 4.3V, respectively. Figure 4 gives a typical
recommended power supply connection for the circuit.
15
30011
6
13
Figure 4. Recommended supply Voltage Connection
for XR-C240 (Note: See Figure 6 for
Recommended bypass capacitors).
3-14
AN-02
15
'Set c, to obt.ln ....onant
..nk frequency 01 1.544MHz
3.51K
311
Figure 5. External Components Necessary for Circuit Operation.
A,
R4
5.'
A,
R,
556
L2
3.3/-1H
C7
INPUT
A,
R7
C6
130
0.'
OUTPUT
+
R2S
300
C17
0.'
4.3V
8.2V
POWER TO REPEATER
SECTION NO.2
Figure 6. A Typical Circuit Connection for XR·C240 in 1.544 MHz T·1 Repeater System.
3-15
AN·02
DESCRIPTION DF CIRCUIT OPERATION:
system block diagram. Note that all the blocks shown in
Figure 6 are a part of the monolithic IC; and the numbered circuit terminals correspond to the IC package
pins (see Figure 4).
This section gives a brief description of the internal circuitry contained within the XR-C240 monolithic IC.
Figure 6 shows a .practical circuit connection for the
XR = C240 in an actual PCM repeater application for
1.544 Mbps T-1 Repeater application. For simplification
purposes, the lightening protection circuitry and the
second repeater section are not shown in the figure.
The circuit diagram of the preamplifier section is shown
in Figure 7. This section is designed as a two-stage differential amplifier with a broadband voltage gain of
52db. The differential outputs of the preamplifier (Pins 4
and 5) are internally connected to the peak-detector,
Y+ =4.3Y
7}---~--------------~
PEAK
DETECTOR
INPUT
B
~---JVV~----~------~16
Figure 7. Circuil Diagram of Preamplifier Section.
6 r - - -___A..,_ _ _ _
~
GND
PEAK
DETECTOR
Figure 9. Automatic Une Build-Out (ALBO) Section.
FULL WAVE
RECTIFIER
THRESHOLD
DETECTOR
INPUT
FROM
PREAMP
~----------~,----------~
,---------~,--------~
r----..
A- A+
B
15
D
v+ =
Figure 8. Circuit Diagram of Threshold-Detector, Full-Wave'Rectifier and Peak-Detector Sections.
3-16
4.3V
AN·02
full-wave rectifier and the threshold detector sections
of the XR-C240 as shown in Figure 8.
of the second gain stage is "integrated" by the phaseshift capacitor, C1, externally connected to Pins 11 and
12. (See timing diagrams of Figure 13.) The nominal value of this capaCitor is in the 30 to 40pf range. The triangular waveform across Pins 11 and 12 is at quadrature
phase with the sinusoidal voltage swing across the L-C
tank circuit. This waveform is then used to generate the
"strobe" signal, Cp, and the clock pulse C, which is
applied to the data latches of the logic section.
The peak-detector output (terminal B of Figure 8) is internally connected to the Automatic Line Build-out
(ALBO) section of the circuit and controls the DC bias
current through the ALBO diodes 019 through 020, as
shown in Figure 9.
The full-wave rectifier output (output D of Figure 8) is internally connected to the clock-extractor section of the
repeater and provides the excitation signal for the L-C
tuned tank circuit (Pin 14) of the injection locked oscillator. The threshold-detector outputs (G + and G - of
Figure 8) provide the differential logic drive to the data
latches of the logic section of XR-C240.
The strobe and clock pulses out of the clockregenerator section are applied to the output data
latches shown in Figure 11. The two parallel output R-S
flip-flops are driven by the differential inputs (G + and
G -) from the data comparator of £lgure 8. T~ two
sets of differential data signals, F1, F1 and F2, F2 are
then applied to the output driver amplifier shown in Figure 12. The high-current outputs of the driver stage
(Pins 8 and 9) are connected to the center-tapped output transformer as shown in Figure 5. The voltage
swing across the output is one diode drop (VBE) less
than the supply voltage spread, i.e.:
The clock-extractor section of XR-C240 is designed as
an injection locked oscillator as shown in the circuit
schematic of Figure 10. The excitation is applied to the
emitter of 023, through terminal D which is internally
connected to the output of the threshold comparator.
This signal in turn controls the current in the resonant
L-C tank circuit connected to Pin 14. The sinusoidal
waveform across the tank is then amplified and
squared through the cascaded differential gain stages
made up of 031, 032 and 035, 036. The output swing
Peak Output Swing = (V++) - (V+) - (VBE) = 3.2V
The output stage is designed to work into a nominal
load impedance of 100 ohms, and can handle peak
load currents of 30mA.
,.
~-------r--'--+--1
C--+--I
In an emergency situation, the local transmitter can be
activated by its carrier-control input, which causes it to
transmit a tone, fTO, at its center frequency. When this
tone is received by the CPU, it will be treated as a priority request to transmit information; the CPU will immediately interrogate the corresponding local modem by
sending out its address tone at frequency, fRO.
INPUTS
TIMING
RESISTORS
Dual-Channel Receive
4
56
7
YEE
GROUND
-VEE 0 - - - -.............- - 4 - - - - - - - - - - '
Figure 3_ Functional Diagram of XR-2207 Monolithic
FSK Generator.
As an option, the receiver can provide serial data outputs, through separate terminals, D1 and D2 of Figure
2, for half-bandwidth deviations of the input FSK signals. In this mode, the input data will be in the form of
center-to-mark frequency shifts for one channel, and
center-to-space shifts for the other. This mode of operation allows two separate sets of data or control instructions to be transmitted within the same channel bandwidth, provided that only one of these channels is used
at anyone time.
The frequency of oscillation is set by an external timing
capacitor, and by the combination of one or more of the
external timing resistors, R1 through R4. The keying terminals switch these external resistors in and out of the
circuit and thus control the operating frequency. Table 1
shows the four discrete frequencies which can be obtained as a function of four logic states at Pin 8 and 9. It
should be noted that the frequency is inversely proportional to the timing resistor connected to the activated
timing pin. For example, if only one of the timing pins,
say Pin 5, is activated and its associated resistor, R3, is
left open-circuited (i.e., R3 = 00) the oscillator will be
keyed OFF since this corresponds to a zero-frequency
state.
Dual-Channel Transmit
As an option, the transmitter can also transmit two separate channels, using half-bandwidth deviations of the
transmit signal. In this case, the outgoing data will be
encoded with center-to-mark transitions of the transmitter frequency in one of the channels, and center-tospace transitions in the other. However, similar to the
case of the receiver, only one or the other, and not both,
of these half-bandwidth channels can be on at a given
time.
Table 1.
Output Frequency of the XR-2207
as a Function of the Keying Logic.
Logic Level
XR-2207 As A Three-State FSK Transmitter
The XR-2207 is a monolithic voltage-controlled oscillator (VCO) circuit with excellent temperature stability. It
provides simultaneous triangle and square wave outputs, and can be keyed to anyone of four preprogrammed frequencies by means of external logic signals. These four discrete frequencies are preprogrammed by the choice of four external timing
resistors.
Pin 8
Pin 9
Active
Timing
Resistor
L
L
Pin 6
Output
Frequency
---
1
Co R1
Figure 3 shows a functional block diagram of the XR2207 monolithic FSK generator chip. The circuit is comprised of four functional blocks: A variable-frequency
oscillator which generates the basic periodic waveforms; four current switches actuated by binary keying
inputs, and buffer amplifiers for both the triangle and
square wave outputs. The internal current switches
transfer the oscillator current to any of four external tim-
L
H
Pin 6 and 7
_1_+_1_
Co R1
Co R2
H
L
Pin 5
--
1
CoR3
H
H
Pin 4 and 5
_1_+_1_
CaR3
(* Frequency in Hz, R in Ohms and C in Farads.)
3-37
CoR4
AN-OS
+12V
RL
5.1K
4.7K
NI/M
XA·2207
~===j~~~;;;;~-------o JU1fL
FSK
OUTPUT
Figure 4. Three-State FSK Transmitter Using the XR-2207.
Table 2.
Three-State Transmitter Operating Modes
as a Function of Control Inputs
Figure 4 shows the recommended circuit connection of
the XR·2207, for its operation as a three·state FSK
transmitter. The three resistors, R1, R2 and R4, are
used to set the three discrete frequencies to be transmitted in accordance with the frequency expressions
given in Table 1, where:
Control
Input
States
Level
at
Pin 9
Transmitter Transmitter
Operating
Output
Mode
Frequency
A
B
C
Level
at
Pin 9
L
L
L
L
H
OFF
Transmitter
H
L
L
L
H
OFF
Off
L
H
L
L
L
fT1
Transmit
H
H
L
H
L
fT2
Data
L
L
H
H
H
fTO
Transmit
fT1
It should be noted that Pin 5 is left open circuited (I.e.,
R3 = 00). This allows the circuit to be keyed OFF, or disabled, by applying a high-logic state to Pin 8, and a lowlogic state to Pin 9 (see Table 1).
The functions of the three control terminals can be described as follows:
L
H
H
H
H
iTO
Carrier
H
H
H
H
H
fTO
Only
a. FSK Data Input:
The serial binary data is applied to
this terminal. With the carrier control at low- and
enable/disable control at high-state, the binary data causes the transmitter to generate the mark
and space frequencies, fT1 and fT2.
XR-2211 As A Three-State Receiver
The XR-2211 is a monolithic FSK demodulator which
operates on the phase-locked loop principle. In addition
to the basic PLL system, the monolithic chip also contains a quadrature-detector circuit which produces a
logic signal when a carrier signal, or tone, is present
within the capture range of the PLL. A simplified functional block diagram of the circuit is shown in Figure 5.
b. Enable/Disable Control: When this input is at lowstate, the transmitter is disabled.
c. Carrier-Control:
When this terminal is at high-state,
the transmitter generates a continuous tone at frequency, fTO.
With the external logic circuitry shown in Figure 4,
carrier-control can override both the enable/disable or
the FSK data inputs. A detailed truth-table of the circuit
outputs is given in Table 2, for various states of the
three control inputs.
Basic Bi-State Operation
The basic operation of the XR-2211, in conventional bistate modems, is described in detail in Exar's Application Note, AN-01. It will be briefly reviewed below.
3-38
+Vee
,I, DEl
OUTPUT
yeo
INPUT
veo
TIMING
CAP
AN-OS
FSK
COMP
INPUT
+12V
Figure 5. Functional Block Diagram of XR-2211 FSK and
Tone Detector.
Figure 6. XR-2211 as a Bi-Stale Receiver with ToneDetection Capability.
The basic circuit connection for the XR·2211 for bi·state
FSK detection is shown in Figure 6. The center frequen·
cy is determined by fo = (1/C1 R4) Hz, where capaci·
tance is in farads and resistance is in ohms. Calcula·
tions for fo should fall midway between the mark and
space frequencies.
always less than the tracking range. The capture range
is limited by C2, which, in conjunction with R5, forms
the loop-filter time constant. In most modern applications, ilfc is chosen to be "'60% to 95% of the tracking range, ilf.
The bi-state FSK data filter, made up of RF and Cf, removes the jitter from the demodulated FSK signal. Similarly, the lock-detect filter capacitor (CD) removes chat·
ter from the lock-detect output. With RD = 510 kO, the
minimum value of CD can be determined by: CD(/Lf)
'" 16/capture range in Hz. The XR·2211 has three npn
open-collector outputs, each of which is capable of
sinking up to 5 mA. Pin 7 is the FSK data output, Pin 5 is
the Q lock-detect output which toes low when a carrier
is detected, and Pin 6 is the Q lock-detect output which
goes high when lock is detected. If Pin 6 and 7 are
wired together, the output signal from these terminals
will provide data when FSK is applied, and will be low
when no carrier is present.
The tracking range (± ilt) is the range of frequencies
over which the phase·locked loop can retain a lock with
a swept input signal. This range is determined by the
formula:
ilf = (R4fo/R5) Hz.
ilf should be made equal to, or slightly less than, the
difference between the mark and space frequencies.
For optimum stability, the recommended range of val·
ues for R4 is between 10 kO and 100 kO.
The capture range (±ilfcl is the range of frequencies
over which the phase-locked loop can acquire lock. It is
+12V
RA
~~-------------FSK
Sll~~~~
0---+------------D,
D,
I
VB
t---------------,
Ry
1/2 OF
XR-45S8
fro DETECTOR OUTPUT
(TRANSMITTER ENABLE/DISABLE)
Figure 7. Circuit Connection for Operating XR-2211 as a Three-State FSK Receiver.
3·39
AN-05
Three-State Operation
The XR-2211 FSK demodulator circuit can be made to
operate as a three-state receiver (see Block B of Figure
2), using the circuit configuration shown in Figure 7.
With reference to the Figure, the basic operation of the
circuit can be described as follows: The basic FSK decoding function, converting the incoming mark and
space signals at frequencies fR1 and fR2' is performed
in the same manner as in the bi-state case, and the resulting output is available at Pin 7 of XR-2211. Pin 7 is
connected to the tone-detect output, and then gated by
the complement of the carrier-detect output. Thus, the
data output terminal will be enabled only when the mark
and space frequencies are present, but not when the
receive-carrier, fRO, is present.
The output of Pin 11 is filtered by RK and CK, and is
used to drive the external voltage comparators. The
outputs of these comparators are then connected
through the external logic gates, to produce the carrierdetect or the enable/disable signal. The resulting logic
output will be noramlly at a low state, and will go high
only when the carrier signal, fRO, is present. This logic
signal is normally used for transmitter enable/disable
control, as shown in Figure 2.
The logic level changes, at the external comparator outputs, correspond to mark-to-carrier or space-to-carrier
frequency shifts (see Figure 8); thus, these outputs can
be utilized as optional dual-mode monitor outputs, D1
and D2 of Figure 2.
The external voltage comparators shown in Figure 7 are
added to the circuit to distinguish PLL output voltage
levels corresponding to various input frequencies. The
function of the XR-2211 frequency-to-voltage transfer
characteristics can be understood by referring to Pin 11
in Figure 8. The voltage levels and polarities shown are
relative to the XR-2211 internal reference voltage, V1O,
at Pin 10. The mark and space frequencies, fR1 and
'R2, generate the maximum dc level shifts. VR1 and
VR2, sensed by the internal FSK comparator (see Figure 5) whichis internally biased from the reference voltage, V1O.
l
~
.!C
~
~ TOTAL TRACKING BANDWIDTH ~
l
,.0~ >a
I
5
~ i
0
~
~"
"---/
Vln
VA
va
"".
The external comparators, Comp. A and Compo B of Figure 7, are biased at voltage levels, VA and VB, approximately halfway between VR1 and VR2, to trip at frequencies fA and fB, which are halfway between markto-center and space-to-center frequency shifts. This
biasing is achieved with the external resistive dividers,
RA, RB, RX, and Ry of Figure 7, which generate the reference voltage levels, VA and VB, with respect to the
XR-2211 internal reference at Pin 10. It should be noted
that the value of the resistors (RA + RB) and (RX + Ry)
must be as large as possible (typically in excess of 100
kO) to avoid disturbing the voltage level at Pin 10:
- - - - - _ . INPUT SIGNAL FREQUENCY
Figure B. XR-2211 Frequency-to-Voltage Transtar
Characteristics. (Note: V11 and V10 are
the dc voltage lavels at Pins 11 and 10,
respectively. )
3-40
AN-06
Precision PLL System using
the XR·2207 and the XR·2208
INTRODUCTION
The phase-locked loop (PLL) is a versatile system block,
sUitable for a wide range of applications in data communications and signal conditioning. In most of these
applications, the PLL is required to have a highly stable
and predictable center frequency and a well-controlled
bandwidth. Presently available monolithic PLL circuits
often lack the frequency stability and the versatility required in these applications.
INPUT
SIGNAL
~
PHASE
COMPARATOR
Vetl)
LOW PASS
FILTER
~
Va(t)
'0
This application note describes the design and the application of two-chip PLL system using the XR-2207 and
the XR-2208 monolithic circuits. The XR-2207 is a precision voltage controlled oscillator (VeO) circuit with excellent temperature stability (±20 ppmlce, typical) and
linear sweep capability. The XR-2208 is an operational
multiplier which combines a four quadrant multiplier
and a high gain operational amplifier in the same package. Both circuits are designed to interface directly
with each other with a minimum number of external
components. Their combination functions as a high performance PLL, with the XR-2207 forming the veo section of the loop, and the XR-2208 serving as the phasedetector and loop amplifier.
VCO
t--r---o
v.
Figure 1. Block Diagram 01 a Phase-Locked Loop.
the veo to synchronize or "lock" with the incoming signal. Once in lock, the veo frequency is identical to the
input Signal, except for a finite phase difference.
Two key parameters of a phase-locked loop system are
its "lock" and "capture" ranges. These can be defined
as follows:
Lock Range = The band of frequencies in the vicinity
of fo over which the PLL can maintain lock with an input
signal. It is also known as the "tracking" or "holding"
range. Lock range increases as the overall loop gain of
the PLL is increased.
Capture Range = The band of frequencies in the vicinity of fo where the PLL can establish or acquire lock with
an input signal. It is also known as the "acquisition"
range. The capture is always smaller than the lock
range. It is related to the low pass filter bandwidth and
decreases as the low pass filter time constant increased.
As compared with the presently available single-chip
PLL circuits such as the XR-210 or the Harris HI-2820,
the two-chip PLL system described in this paper offers
approximately a factor of 10 improvement in temperature stability and center frequency accuracy. The system can operate from 0.01 Hz to 100 kHz, and its performance characteristics can be tailored to given design requirements with the choice of only four external
components.
The PLL responds to only those input signals sufficiently close to the veo frequency, fO, to fall within the
"lock" or "capture" ranges of the system. Its performance characteristics, therefore, offer a high degree of
frequency selectivity, with the selectivity characteristics centered about fO. Figure 2 shows the typical
frequency-to-voltage transfer characteristics of the
PLL. The input is assumed to be a sine wave whose frequency is swept slowly, over a broad frequency range
covering both the "lock" and the- "capture" ranges of
the PLL. The vertical scale corresponds to the filtered
loop error voltage, Vd, appearing at the veo control terminal.
OEFINITIONS OF PLL PARAMETERS
The phase-locked loop (PLL) is a unique and versatile
feedback system that provides frequency selective tuning and filtering without the need for coils or inductors.
It consists of three basic functional blocks; phase comparator, low-pass filter, and voltage-controlled oscillator,
interconnected as shown in Figure 1. With no input signal applied to the system, the error voltage, Vd, is equal
to zero. The veo operates at a set "free-running" frequency, fo . If an input signal is applied to the system,
the phase comparator compares the phase and frequency of the input signal with the veo frequency and
generates an error voltage, Ve(t), that is related to the
phase and frequency difference between the two signals. This error voltage is then filtered and applied to
the control terminal of the veo. If the input signal frequency, fS, is sufficiently close to fo, feedback causes
As the input frequency, fS, is swept up (Figure 2(a)) the
system does not respond to the input signal until the input frequency reaches the lower end of capture range,
feL. Then, the loop suddenly locks on the input signal,
causing a positive jump in the error voltage Vd. Next,
Vd varies at a slope equal to the reciprocal of veo
3-41
AN-06
PRECISION PLL USING XR-2207 AND XR-2208
The XR-2207 VCO and the XR-2208 operational multiplier can be inter-connected as shown in Figure 3, to form
a highly stable PLL system. The circuit of Figure 3 operates with supply voltages in the range of + 12V to
+ 26V; and over a frequency range of 0.01 Hz to 100
kHz. In the PLL system of Figure 3, all the basic performance characteristics of the PLL can be controlled
and adjusted by the choice external 4 components
identified as resistors RO and Rl, and the capacitors Co
and Cl, Co and RO control the VCO center frequency;
Rl and Cl determine the tracking range and the low
pass filter characteristics. The tWO-Chip PLL system
can be readily converted to split supply operation by
inter-connecting the circuit as shown in Figure 4. The
PLL circuit of Figure 4 operates over a supply voltage
range of ± 6 volts to ± 13 volts.
(+)
v,
0
I--JJr--...L..~:---'-------FREaUENCY
_
INCREASING
FREQUENCV '.
H
(.)
ILL
leL
'0
ICH
'LH
I
I
I
I
I
(+)
v,
0
r-..'Ir---'---:....----r-------- FREQUENCY
-
DECREASING
FReQUENCY'.
H
(bl
Figure 2. Frequency to Voltage Transfer Characteristics of a
PLL System; (a) Increasing Input Frequency; (b)
Decreasing Input Frequency.
For best results, the timing resistor RO should be in the
range of 5k to lOOk, and Rl > RO. Under these conditions, the basic parameters of the PLL can be easily
calculated from the design equations listed in Table 1.
voltage-to-frequency conversion gain, (Kv), and goes
through zero at fs = fO. The loop tracks the input frequency until fs reaches the upper edge of the lock
range, fLH. Then the PLL loses lock, and the error voltage drops to zero. If the input frequency is swept back
slowly, from high towards low frequencies the cycle reo
peats itself, with the characteristics shown in Figure
2(b). The loop captures the signal at the upper edge of
the capture range, fCH, and tracks it down the lower
edge of the lock range, fLL. With reference to the figure, the "lock" and the "capture" ranges can be defined as:
Design Example
As an example, consider the design of a PLL system using the circuit of Figure 3, to meet the following nominal
performance specifications:
a) Center Frequency = 10kHz
b) Tracking Range = 20% (9 kHz to 11 kHz)
c) Capture Range = 10% (9.5 kHz to 10.5 kHz)
Solution:
Lock Range = .: Phase detector output per unit of
phase difference between the two signals appearing at
the phase detector inputs. It is normally measured in
volts per radian.
Co
= (I!fORO) = 0.01
/-IF
b) Set Lock Range:
From equation 2 of Table 1:
VCO Conversion Gain, Kv: VCO frequency change per unit
of input voltage. It is normally measured in radians!
sec.lvolt.
Rl = (0.45) RO = 45k
c) Set Capture Range:
Since capture range is significantly smaller than
Lock range, equation 8(a) applies.
Loop Gain, KL: Total dc gain around the feedback loop. It
is equal to the product of Kef> and Kv.
r.
Loop Damping Factor, Defines the response of the loop
error voltage Vd, to a step change in frequency. If \< 1,
the loop is underdamped; and the error voltage Vd will
exhibit an underdamped response for a step change of
signal frequency.
Solving equation 8(a) for Cl, one obtains:
Cl = 0.032/-1F
PRECISION SINE WAVE OUTPUT PLL USING XR-2208
AND XR-2206
The lock range of the phase-locked loop is controlled by
the loop gain, KL. The capture range and the damping
factor are controlled by both the loop gain and the low
pass filter.
The interconnection of the XR-2208 and XR-2206 as
shown in Figure 5 forms a precision phase-locked loop
system with a sine wave output. The phase-locked loop
3-42
AN-06
typically 2.5% unadjusted with R4 = 2000 and R5
open, and 0.5% adjusted using R4 and R5. Sine wave
amplitude is adjusted by R3 with the conversion gain
equalling typically:
characteristics are adjusted with the same lour external components as previously described. Equation 2 in
Table 1 is modilied to:
(2) Lock Range (AIL/lo) = (0.5) (Ro/R1)
60mVp_p
This change is because the relerence 01 the XR-2206 is
internally set. The clamp network with Q1 has been
added to adjust the swing to the VCO to compensate lor
this relerence. The sine wave characteristics are adjusted by R4 and R5, which adjust sine-shaping and
symmetry respectively. Sine wave distortion levels are
KO 01 R3
The phase-locked loop input characteristics allow locking to input signal levels 01 50 mV RMS to 2V RMS.
Table 1
Phase-Locked Loop Design Equations'
(1) Center Frequency: 10 = _1_ Hz
ROCO
(7) Loop Damping: =
1
--
(2) Lock Range: (AIL/IO) = (0.9)(RO/R1)
Co
C1
a) Underdamped Loop (1< 1/2):
(Alc/fO) =
0.8 RO
Co
R1
C1
--
(4) VCO Conversion Gain:
b) Overdamped Loop
1
.J2
(8) Capture Range:
(3) Phase Detector Gain: Kcp = 0.5 VCC volts/radian
Where VCC = V + lor split supply; VCC = V + /2
for single supply.
KV =
=
2.J7KL
rad/sec/volt
2 VCCCOR1
-
(I> 1):
(Afc/IO) = 0.8(RO/R1)
(5) Loop Gain: KL = KcpKV =
0.25 sec - 1
COR1
(6) Low Pass Filter Time Constant:
T
'See Figures 3 and 4 for component designation.
= C1 R1 sec.
2
Co
v+
v+
10K
5.1K
v+
16
2
13
14
5.1K
SQUARE WAVE
OUTPUT
5.1K
2K
XR-2208
5.1K
6
7
-=-'
6
I
>---+--013
'----+--0 14
C1
AO
12
9
TAIANGLE
OUTPUT
-=-
S.lK
-=-
Cc
0-----1
SIGNAL
INPUT
1.-=-
S.lK
Cc
=0
CB
= BYPASS
I-=
COUPLING CAPACITOR
CAPACITOR
C2
(v+ = 12V to 24V)
Figure 3. Circuit Interconnections lor Single Supply
Operation,
3-43
-=-
AN-06
v+
'OK
16
2
14
'3
,.K
'K
-=
s:::~~
SQUARE WAVE
OUTPUT
rLfl
",
J
1K
o------t f--4---'
,.
'3
C
,
"0
IV\
TRIANGLE
OUTPUT
Cc
v-
Figure 4. Circuit Interconnections for the Precision PLL System using the XR·2207 and the XR·2208 Monolithic Circuits.
(Split·Supplyoperation, ± 6V to ± l3V.
+12V
S.1K
•
I
o-j
Cc
+
S.1K
X
3
.' 2K
T'"F
"3l:
'3
2
.....
•
INPUT
SIGNAL
-
,. ,
5.1K
7
20K
1>
XA·HOI
•
2.K
'4
••
11
.~
,
2K
.oK
",
rlJF
GNO
Figure 5.
3·44
",
it-
7
VCO
/
C,
".
•
1'"
~
:>
0,
2N2904
•
4
~
'2
1
16 15
2~
".
-1'"
S.lK
11
SQUARE WAVE
OUTPUT
SlNEW"VE
OUTPUT
2
XR-HOI
9:~:·
I'"F
500 "4
'OK
AN·07
Single-Chip Frequency Synthesizer
Employing the XR-2240
INTRODUCTION
The XR-2240 monolithic timer/counter contains an 8-bit
programmable binary counter and a stable time-base
oscillator in a single 16-pin IC package. Although the
circuit was originally designed as a long-delay timer capable of generating time delays from microseconds to
weeks, it also offers a wide range of other applications
beyond simple time-delay generatiqn. One such unique
application is its use as a single-chip, frequency synthesizer, where it can generate over 2,500 discrete frequencies from a single reference frequency input.
set frquency, fS (fS = 1/RC), where Rand C are the external components at pin 13. The 8-bit binary counter
can be programmed to divide the time-base frequency
by an integer count, N, and generate an output pulse
train whose frequency is:
The operation of the XR-2240 as a frequency synthesizer is possible because of the ability of the circuit to both
multip/y and divide the input frequency reference. It
can, simultaneously, multiply the input frequency by a
factor, "M," and divide it by a factor "N + 1," where
both M and N are adjustable integer values. Therefore,
the circuit can produce an output frequency, fo, related
to the input reference frequency fR as:
Frequency Multiplication by "M":
M
fo = f R - 1 + N
1
fo = f 8 - 1 + N
Frequency multiplication is achieved by synchronizing
the time-base oscillator with the harmonics of the input
sync or reference signal. Thus, if the time-base oscillator is made to free-run at "M" times the input frequency, it cari be made to synchronize the "M"th harmonic
of the input reference Signal. Typical capital range of
the circuit is better than ± 3 %, for values of 1 :s; M:s; 10;
and since the time-base is accurate to within ± 0.5 % of
the external R-C setting, lock-up does not present a
problem for a given harmonic lock setting.
Figure 1 shows the circuit connection for operating the
XR-2240 timer/counter as a self-contained frequency
synthesizer. The integer values M and N can be externally adjusted over a broad range:
1 ~ M ~ 10
1:s; N :s; 225
The multiplication factor M is obtained by locking on the
harmonics of the input frequency. The division factor N
is determined by the pre-programmed count in the binary counter section. The principle of operation of the circuit can be best understood by briefly examining its capabilities for frequency division and multiplication separately.
Frequency Division by (1 + N):
When there is no external reference input, fR, the timebase oscillator section of the XR-2240 free-runs at its
Figure 1
3-45
AN·07
Circuit Operation:
With reference to Figure 1, the operation of the synthesizer circuit can be briefly explained as follows: The reference input frequency, fR, is applied to the time-base
sync terminal (pin 12) through a 5.1 KO series resistance and a coupling capacitor. The recommended
waveform for the input frequency, fR, is a 3 Vpp pulse
train with a pulse width in the range of 30% to 80% of
the time-base period, T. The multiplication factor M is
chosen by the potentiometer R1 which sets the timebase period T (T = RC). If no external reference is used
'
then M is automatically equal to 1.
The divider modulus, N, is chosen by shorting various
counter outputs to a 3K common pull-up resistor. The
output waveform is a pulse train with a fixed pulse
width, T = RC, and a period TO = (N + 1)RC.
circuit to maintain a periodic output waveform. For the
component values shown in Figure 1, the circuit can
operate with the timing components Rand C in the
range of:
0.005/LFsCs.1/LF; 1 KOsRs 1 MO
The XR-2240 is a low-frequency circuit. Therefore, the
maximum output frequency is limited to .. 200 kHz, by
the frequency capability of the internal time base oscillator.
A particularly useful application of the simple synthesizer circuit of Figure 1 is to generate stable clock frequencies which are synchronized to an external reference, such as the 60 Hz line frequency. For example,
one can generate a 100 Hz reference synchronized to
60 Hz line frequency simply by setting M = 5 and N =
2 such that:
The external R-C network between the output and the
trigger and reset terminals of the XR-2240 is a noncritical delay network which resets and re-triggers the
fo
3-46
M
5
= fR - - = (60)-- =
1
+N
1
+2
100 Hz
AN-OS
Dual Tone Decoding with
XR·567 and XR·2567
INTRODUCTION
+v
+V
Two integrated tone decoders, XR-567 units, can be
connected (as shown in Figure 1A) to permit decoding
of simultaneous or sequential tones. Both units must be
on before an output is given. R1C1 and R' 1C' 1 are chosen, respectively, for Tones 1 and 2. If sequential tones
(1 followed by 2) are to be decoded, then C3 is made
very large to delay turn-off of Unit 1 until Unit 2 has
turned on and the NOR gate is activated. Note that the
wrong sequence (2 followed by 1) will not provide an
output since Unit 2 will turn off before Unit 1 comes on.
Figure 1B shows a circuit variation which eliminates
the NOR gate. The output is taken from Unit 2, but the
Unit 2 output stage is biased off by R2 and CR1 until activated by Tone 1. A further variation is given in Figure
1C. Here, Unit 2 is turned on by the Unit 1 output when
Tone 1 appears, reducing the standby power to half.
Thus, when Unit 2 is on, Tone 1 is or was present. If
Tone 2 is now present, Unit 2 comes on also and an output is given. Since a transient output pulse may appear
+v
+v
RL
TONE 1
DECODER
20 K
81--+----,
1/4 B005
~
C2
1:
INPUT
+V
C3
~*
+V
'48005
20K
R2
TONE 2
DECOOER
6
5
-=-
~
_ _ _~20K
Figure 1A. Detection of Two Simultaneous or
Sequential Tones
+v
+V
+V
5
IN~
+v
OUTPUT
TONE 1
DECODER
7
5
C,
C2
J
3-47
6
2
1
**
C3
Figure 1C
6
7
2
1
AN-OS
DIGIT
0--1
0546
III
CONIPONENT VALUES (TYPICAL)
l
R,
R2
R3
Ct
C2
C3
C4
Figure 2. Low-Cost Touch
3-48
Tone~
Decoder
6.81015 K
4.7 K ohm
2.0 K ohm
0.1 mid
1.0 mid
2.2 mid
250
ohm
6 V
6 V
6 V
AN-08
during Unit 1 turn-on, even if Tone 2 is not present, the
load must be slow in response to avoid a false output
due to Tone 1 alone.
the R2 resistors of the two 567's which are being activated. Capacitor C4 (optional) decouples the ac currents at the common point.
The XR-2567 Dual Tone Decoder can replace two integrated tone decoders in this application.
LOW COST FREQUENCY INDICATOR
Figure 3 shows how two tone decoders set up with
overlapping detection bands can be used for a go/no/go
frequency meter. Unit 1 is set 6% above the desired
sensing frequency and Unit 2 is set 6% below the desired frequency. Now, if the incoming frequency is within 13 % of the desired frequency, either Unit 1 or Unit 2
will give an output. If both units are on, it means that the
incoming frequency is within 1 % of the desired frequency. Three light bulbs and a transistor allow low
cost read-out.
HIGH SPEED, NARROW BAND TONE DECODER
The circuit of Figure 1 may be used to obtain a fast, narrow band tone decoder. The detection bandwidth is
achieved by overlapping the detection bands of the two
tone decoders. Thus, only a tone within the overlap portion will result in an output. The input amplitude should
be greater than 70 mV rms at all times to prevent detection band shrinkage and C2 should be between 130/fo
and 1300/fo mfd where fo is the nominal detection frequency. The small value of C2 allows operation at the
maximum speed so that worst-case output delay is only
about 14 cycles.
+V
TOUCH-TONE DECODER
Touch-Tone decoding is of great interest since all sorts
of remote control applications are possible if you make
use of the encoder (the push-button dial) that will ultimately be part of every tone. A low-cost decoder can be
made as shown in Figure 2. Seven 567 tone decoders,
their inputs connected in common to a phone line or
acoustical coupler, drive three integrated NOR gate
packages. Each tone decoder is tuned, by means of R1
and C1, to one of the seven tones. The R2 resistor reduces the bandwidth to about 8% of 100 mV and 5% at
50 mV rms. Capacitor C4 decouples the seven units. If
you are willing to settle for a somewhat slower response at low input voltages (50 to 10 mV rms), the
bandwidth can be controlled in the normal manner by
selecting C2, thereby eliminating the seven R2 resistors
and C4. In this case, C2 would be 4.7 mfd for the three
lower frequencies or 2.2 mfd for the four higher frequencies.
ON
FREOUENCY
R,
INP~
I
100-1000 mV rms
II
HIGH
c,
I
The only unusual feature of this circuit is the means of
bandwidth reduction using the R2 resistors. As shown
in the 567 data sheet under Alternate Method of Bandwidth Reduction, the external resistor RA can be used
to reduce the loop gain and, therefore, the bandwidth.
Resistor R2 serves the same function as RA except that
instead of going to a voltage divider for dc bias it goes
to a common point with the six other R2 resistors. In effect, the five 567's which are not being activated during
the decoding process serve bias voltage sources for
SENSING
CENTER FREQUENCY
Figure 3. Frequency Meter with Low-Cost Lamp
Readout
3-49
AN·09
Sinusoidal Output from XR·215
Monolithic PLL Circuit
INTRODUCTION
In a wide range of communication or signal conditioning applications, it is necessary to obtain a sinusoidal
output signal which is synchronized to a desired reference or clock input. This can be achieved by using the
XR-215 type monolithic PLL circuit and an additional
sine-shaping network_
system is formed by simply ac coupling the VCO output
to either of the phase comparator inputs and adding a
low-pass filter to the phase comparator output terminals. The XR-215 can operate over a large choice of
power supply voltages ranging from 5 volts to 26 volts
and a wide frequency band of 0.5 Hz to 35 MHz. It can
accommodate analog signals between 300 microvolts
and 3 volts and can interface with conventional OTL,
TIL and ECL logic families.
When a periodic input signal is present within the capture range of the XR-215 PLL, the system will lock on
the input; and the VCO section of the PLL will synchronize with the input frequency_ The output of the oscillator section of the PLL can then be converted to a low
distortion sine wave by a relatively simple sine-shaping
circuit.
Figure 2 shows the simplified circuit schematic of the
XR-215 phase-locked loop IC. The VCO part of XR-215,
shown in the center section of Figure 2, is an emittercoupled multivibrator Circuit, whose frequency is set by
an external capacitor, CO, connected across the timing
terminals (Pins 13 and 14). In this type of an oscillator,
the differential voltage waveform across the timing capacitor, CO, is a linear triangle, with a peak-to-peak amplitude of 1.4 volts. This output amplitude across the
timing capacitor is independent of supply Voltage.
GENERAL DESCRIPTION
Figure 1 contains a functional block diagram of the XR215 monolithic PLL system. The circuit consists of a
balanced phase comparator, a highly stable voltagecontrolled oscillator (VCO) and high speed operational
amplifier. The phase comparator outputs are internally
connected to the VCO inputs and to the non-inverting
input of the operational amplifier. A self-contained PLL
Vee
PHASE
COMPARATOR
OUTPUTS
This triangular waveform can be shaped into a low distortion sine wave by passing it through a simple differential gain stage, as shown in Figure 3. By adjusting the
potentiometer Rq of Figure 3, the input transistors
T 1and T2 of the differential stage can be brought to the
verge of cutoff at the positive and the negative extremities of the input triangle wave. This causes the peaks of
the triangle waveform to be rounded, resulting in a
nearly sinusoidal output waveform from the differential
stage. If the transistor characteristics and the current
levels in the differential gain stage are well matched,
one can reduce the total harmonic distortion (THO) of
the sinusoidal output waveform to less than 3%.
yeo
RANGE
TIMING
SELECT CAPACITOR
PHASE
COMPARATOR
'-----If'-'<) 7;~U~WEEP
INPUTS
The sine-shaper circuit of Figure :3 can be designed by
using the XR-Ol0l NPN transistor array, which provides five identical NPN transistors in a single IC package. Figure 4 shows the package diagram of XR-Ol0l
chip, in terms of its 16-pin OIP package.
'--_--+':.:.'0 ~~~;:~~
PHASE
COMPARA~~: 0-"+----'
The five independent transistors contained in the XR0101 transistor array can be interconnected, as shown
in Figure 5, to form the differential sine wave-shaping
circuit of Figure 3. The inputs of the sine-shaper can be
directly connected to the timing capacitor terminals
(Pins 13 and 14) of the XR-215 PLL.
OPAMP
OPAMP
INPUT
OUTPUT
OPAMP
COMPENSATION
Figure 1_ Functional Block Diagram of XR·215
Monolithic PLL Circuit
3-50
AN·091.
jfo.t-______ P~:~. ------_o+j..-------VCo------_...,.j.._____ OP. AMP. -----.-j0j
Figure 2. Simplified Schematic of XR-215
r----------1~---_o V+ (12 V)
5.1 K
NV
INPUT! ~
FROM PINS
13 AND 14
OF
XR·215
-
SINUSOIDAL
OUTPUT
. .00------£
12 K
r----~--'lM~-.() V· 112 VI
1 K
510 II
Figure 3. A Simple Triangle-to-Sine Wave Converter Using a Differential Gain Stage
3·51
AN·09
OPAMP
INPUT
+vcc
I
veo
PHASE
COMPARATOR
OUTPUTS
OUTPUT
l
l
veo
TIMING
JPACITOR
PHASE
COMPARATOR
INPUTS
PHASE
COMPARATOR
BIAS
veo
PHASE
COMPARATOR
INPUTS
veo
SWEEP
INPUT
GAIN
CONTROL
OPAMP
COMPENSATION
RANGE
SELECT
OPAMP
OUTPUT
PIN 8 = SUBSTRATE
Figure 4. Package Diagram lor XR-D101 Matched NPN Transistor Array
WAVE FROM ADJ.·
1+""
1
3
1K
•
13
"
5.1 K
2
XR·D101
FROM PINS
13 AND 14
OF
XR-215
~
1.
NPN
15
TRANSISTOR ARRAY
~
SIN USOIOAL
0 UTPUT
•r-
8
,.
12
7
5
•
11
1K
1K
1
-
12 K
v+
(12 V)
510ll
1
·ADJUST Rq FOR MINIMUM HARMONIC DISTORTION.
Figure 5. Use 01 XR-D101 Transistor Array to Obtain Sinusoidal Output from XR-215 PLL
3-52
AN·10
XR·C262 High·Performance
PCM Repeater IC
INTRODUCTION
The XR-C262 is a monolithic repeater circuit for PulseCode Modulated (PCM) telephone systems. It is designed to operate as a regenerative repeater at 1.544
Megabits per second (Mbps) data rates on T-l type PCM
lines. It is packaged in a hermetic 16-pin CERDIP package and is designed to operate over a temperature
range of -40°C to + 85°C. It contains all the basic functional blocks of a regenerative repeater system including Automatic Line Built-Out (ALBO) and equalization,
and is insensitive to reflections caused by cable discontinuities.
SIGNAL FLOW
-;:===-__. ,
II
II
~II
The XR-C262 operates with a single 6.8-volt power supply, and with a typical supply current of 13 mAo It provides bipolar output drive with high-current handling capability. The clock extractor section of XR-C262 uses
the resonant-tank circuit principle, rather than the
injection-locked oscillator technique used in earlier
monolithic repeater designs. The bipolar output drivers
are designed to go to "off" state automatically when
there is no input signal present. Compared to conventional repeater designs using discrete components, the
XR-C262 monolithic repeater IC offers greatly improved
reliability and performance and provides significant
savings in power consumption and system cost.
lie
_ - - - SIGNAL FLOW
Figure 1. Block Diagram 01 a BI-Directlonal Digital
Repeater System.
can operate on either pulp- or polyethylene-insulated
paired cable that is either pole-mounted or buried. Operation is possible with a variety of wire gauges, provided that the total cable loss at 772 kHz is less than 36
dB. Thus, the system can operate satisfactorily on nearly all paired cables which are used for voice frequency
trunk circuits.
This application note outlines the basic design principles and the electrical characteristics of the XR-C262
monolithic repeater IC. In addition, circuit connections
and applications information are provided for its utilization in T-l type 1.544 Megabit PCM repeater systems.
The T-l type transmission system is designed to operate with both directions of transmission within the same
cable sheath. The system performance is limited primarily by near-end cross-talk produced by other systems operating within the same cable sheath. In order
to insure that the probability of a bit error is less than
10- 6 , the maximum allowable repeater spacing, when
used with 22-gauge pulp cable, is approximately 6000
feet.
FUNDAMENTALS OF PCM REPEATERS
The Pulse-Code Modulation (PCM) telephone systems
are designed to provide a transmission capability for
multiple-channel two-way voice frequency signals
which are transmitted in a digital PCM format. In order
to minimize error rates, and provide transmission over
long distances, this digital signal must be regenerated
at periodic intervals, using a regenerative repeater system. Figure 1 shows the block diagram of a bidirectional PCM repeater system consisting of two
identical digital regenerator or repeater sections, one
for each direction of transmission. These repeaters
share a common power supply. The DC power is simplexed over the paired cable and is extracted at each
repeater by means of a series zener diode regulator.
The XR-C262 monolithic IC replaces about 90% of the
electronic components and circuitry within the digital
repeater sections of Figure 1. Thus, a bi-directional repeater system should require two XR-C262 ICs, one for
each direction of information flow.
OPERATION OF THE XR·C262
The XR-C262 monolithic repeater is packaged in a 16pin dual-in-line hermetic package, and is fabricated using bipolar process technology. The functions of the circuit terminals are defined in Figure 2, in terms of the
monolithic IC package.
In the United States, the most widely used PCM telephone system is the T-l type system which operates at
a data rate of 1.544 Mbps, with bipolar data pulses. It
3-53
AN·10
blocks shown within the dotted area are included on the
monolithic chip. The numbers on the circuit terminals
correspond to the pin numbers of the 16-pin IC package
containing the repeater chip. In terms of the system
block diagram of Figure 3, the overall repeater operation can be briefly explained as follows.
XR·C262
The bipolar PCM signals which are attenuated and distorted due to the preceding transmission medium are
applied to the input of a preamplifier (Block 1) through
an Automatic Line Build-Out (ALBO) circuit. The impedance, Z 1, corresponds to the passive section of the ALBO network. The preamplifier section, along with the
passive equalizer networks Z2 and Z3 connected in
feedback around it, provides gain to compensate for
line losses and band-limiting to reject unwanted noise
as well as gain and phase equalization to shape received pulses.
The ALBO circuitry provides attenuation and shaping to
automatically adjust for varying cable characteristics.
The output of the preamplifier is controlled to swing between two established peak levels. This is accomplished by feedback circuitry, and is similar in concept
to automatic gain control. When the preamplifier output
passes through the peak thresholds it is detected by
the peak detector (Block 2) and produces a signal
which is used to control a feedback loop establishing
Figure 2. Package Diagram of XR·C262 Monolithic PCM
Repeater.
A more detailed system block diagram for the monolithic repeater system is given in Figure 3. The system
"4
'eMSIGNAL
IN':T]
II
14
CB = BYPASS CAP.
Ca = COUPLING CAP.
I
~
___
~I'i}-
_ _ _ _-J
CLOCK
SOURCE
eTR. TAP
J 0-tI
INPUT
Ca
-
I
I
I
®-+-
ANALOG
+VCC
DIGITAL
I
0-t-
I
I
I
XA·C262
MONOLITHIC REPEATER
ANALOG,
GROUND
®-+--,
DIGITAL
DRIVER
I
L ______________ J
(13)
Figure 3. Detailed Block Diagram of the XR·C262 Monolithic Repeater System.
3-54
~ENERATEO
COUT'UT
AN·10
the attenuation and shaping of the AlBO network. The
actual circuit design associated with this function is described in more detail in the discussion of peak detection and AlBO circuitry.
DATA AND CLOCK
THRESHOLDS
The output of the preamplifier drives a set of data comparators which are internally biased from a voltage reference (Block 4) and the precision voltage divider network (Block 5). Thus, the preamplifier output is "sliced"
at various voltage levels to eliminate the effects of the
baseline noise. This output is full-wave rectified and
amplified through Block 6 of Figure 3. The resulting signal has a strong Fourier component at the clock frequency and is used to drive a high Q (,.,100) resonant
circuit tuned to that frequency. The output of the resonant circuit is transformer-coupled to a zero-crossing
detector and clock limiter (Block 10). The resultant output is the desired recovered timing. This resonant circuit is driven by a low impedance amplifier, and the resulting clock edges are in phase with the peak of the received pulses.
PREAIIP OUTPUT.
"EYE" PATTERN
I
I
I
I
I
I
I
I
I
I
I
I
I
i
~
I
I
I
I
I
I
I
The regeneration of the data is achieved through the
two data comparators (Blocks 7 and 8) and the ECl
latches (Block 9) which function as tracking flip-flops.
The positive and negative data paths are separate; and,
with the exception of the data limiter and slicer levels,
identical in design. The preamplifier output is sliced at
about 45 percent of the peak voltage and its amplitude
is limited to provide digital data pulses. The data is applied to one of the inputs to the tracking flip-flop, whose
state is latched and unlatched by the clock. During acquisition, the flip-flop acquires data; during hold, further
data transitions are ignored and the state of the flip-flop
output determines whether an output pulse is transmitted. The implication of using the clock to perform data
sampling is that path delays of the data and clock must
be controlled to be equal. The monolithic integrated circuit technology affords this control. The advantage of
this technique is that the need for clock shifting or
strobe pulse generating circuitry for accurate sampling
alignment is eliminated. Actual circuit implementation
resulted in a 40-nsec misalignment of clock and data.
This 40-nsec error in sampling time amounts to less
than 0.4 dB degradation in SNR performance. Figure 4
shows the idealized timing and signal waveforms within
the circuit.
I
RESONATOA
DRIVING
WAVEFORM
I
I
I
I
I
I
I
RESONATOR
OUTPUT
WAVEFORM
CLOCK
LIMITER
WAVEFORM
Figure 4. Timing Diagrams of Voltage Waveforms within
the Clock Regeneration Section.
es will not latch in the "on" state. When no input signal
is present, the absence of clock is sensed and the output drivers are held in the "off" state.
The output drivers use latched data and clock to produce an output pulse-width which is accurately controlled by the duration of the clock. Non-saturating output drivers (Blocks 12 and 13) insure that output pulse
rise and fall times are less than 100 nsec. The zero input shut-down circuitry (Block 11) guarantees that in
the event incoming data disappears, the output switch-
Figure 5 shows a practical circuit connection for the
XR-C262 in an actual PCM repeater application for
1.544 Mbps T-1 repeater system. For simplification purposes, the lightening protection circuitry and the second repeater section for the reverse channel are not
shown in the figure.
3-55
AN·10
430,lotH
SIGNAL
IN
II
2 K!!
6.8 V
~
NOTE:
= ANALOG GROUND
d7 = DIGITAL GROUND
;,l;
0 .• 7 .F
Figure 5. A Recommended Circuit Connection Diagram lor T·1 Type Repeater Application.
DESCRIPTION OF CIRCUIT OPERATION
data·comparator sections. The circuit exhibits a high
differential input resistance ( .. 106 ohms) and a low out·
put impedance ( ... ao ohms). It has a nominal voltage
gain of 69 dB at DC and 1 and i[>1, which are 90° apart in
phase, but have the same frequency as the input signal
to be detected. One of these Signals, i[>1, is used to
drive the PLL phase detector: the other output, which is
called the "quadrature output" is used to drive a quadrature phase-detector, as shown in Figure 1. If the PLL
is locked on the input Signal, then the input signal and
the VCO signal applied to the quadrature phasedetector are coherent in phase and frequency. This
causes a DC level shift at the low-pass filtered output of
the quadrature phase-detector and makes the voltage
comparator output change its output logic state. Thus,
an output logic signal is produced indicating the lock
condition of the PLL.
PHASE·LOCKED LOOP
r - - - - - - - - - -- - - - l
!
TONE OR
CARRIER
INPUT
DEMODULATED
FM OR FSK
OUTPUT
DH
TONE DETECT
QUADRATURE DETECTOR
OUTPUT
Figure 1. Functional Block Diagram of a PLL Tone- or
Carrier-Detector System.
3-65
AN·12
PHASE
COMPARATOR
OUTPUTS
veo
RANGE
TIMING
SELECT
CAPACITOR
Ca)
PHASE
COMPARATOR
BIAS
C>----1I-""-o OUTPUT
11
- VEE
OP AMP
INPUT
OP AMP
COMPENSATION
veo TIMING
VVVV\
6
<>-'--t----'
(b) WAVEFORM ACROSS
/\/\/\/\
veo
PHASE
COMPARATOR
INPUTS
CAPACITOR
(PINS 11 and 12)
nnnn
veo
GAIN
CONTROL
~
veo OUTPUT
WAVEFORM
(PIN 15)
U LTLTL
(el ."SLlCED" VERSION
OF TIMING
CAPACITOR
WAVEFORM
Figure 4. Timing Diagram of VCO Output Waveforms
Available from XR-210 or XR-215 High-Frequency
PLL Circuits.
OP AMP
OUTPUT
Figure 2. Functional Block Diagram of XR-210
High-Frequency FSK Modulator {Demodulator.
MULT1PLE
PHASE
veo
COMPARATOR
TIMING
OUTPUTS
CONTROLS CAPACITOR
OP AMP
INPUTS
OUTPUTS
+Vcc
veo
15
1
16
14 13
OP AMP
COMPARATOR
12
veo
x
'>--11-'5-0 OUTPUT
PHASE
COMPARATOR
INPUTS
PHASE
COMPARATOR
6
veo SWEep
'-----11--0 AND GAIN
L-_+.!.!.o
<>"--t----'
8
CONTROLS
LOGIC
FOUR-QUA.DRANT
MULTIPLIER
OUTPUT
BIAS
6 7 8
Y GAIN
SET
COMPARATOR
INPUT
Figure 3. Functional Block Diagram of XR-215
High-Frequency Phase-Locked Loop.
9
X GAIN
SET
10
-VEE
Figure 5. Functional Block Diagram of XR-222B
Multiplier {Detector.
serve as such a quadrature output if it is amplified and
"sliced" externally. as shown in the timing diagram of
Figure 4.
given in their respective data sheets, only the external
circuitry associated with the XR-2228 is shown in the
figure. The circuit, as shown, can operate with a single
power supply, from 10 V to 20 V, or with split supplies in
the range of ± 5 V to ± 10 V. In the case of split power
supplies, the resistor string biasing the input terminals
of the XR-2228 is not necessary and can be eliminated
by connecting node A of Figure 6 to ground.
XR-2228 MULTIPLIER/DETECTOR CIRCUIT
The XR-2228 is comprised of a four-quadrant multiplier
and a high-gain op amp on a single monolithic chip. It is
packaged in a 16-pin dual-in-line package and has the
functional block diagram shown in Figure 5. It contains
independent and fully differential X- and Y-inputs which
makes it easy to interface with the XR-210 or the XR215 type PLL circuit for carrier-detection applications.
In the tone- or carrier-detect application, the multiplier
section of the XR-2228 is used as the quadrature
phase-detector section of the block diagram of Figure
1. The op amp is used as a high-gain voltage comparator which converts the differential voltage level
changes at the multiplier outputs into logic level output
signals.
The input signal is AC coupled, with separate coupling
capacitors, both to the input of the particular PLL circuit to be used, and to the X-input terminal (Pin 2) of the
XR-2228.
The V-inputs (Pins 4 and 5) are driven differentially from
the VCO timing capacitor signal (available at Pins 13
and 14 of the PLL IC) which is AC coupled to Pins 4 and
5 of the XR-2228 multiplier input. The multiplier input
stage "slices" this signal to produce the quadrature frequency waveform shown in Figure 4(c).
CIRCUIT OPERATION
The differential DC voltage level at the multiplier output
terminals (Pins 1 and 6) is offset by means of an external resistor, RA, as shown in Figure 6. This initial offset
causes the op amp output of the XR-2228 to settle to a
known state when there is no carrier or tone signal to
be detected. With the op amp input connections as
shown in Figure 6, the op amp output (Pin 11) would be
Figure 6 shows the generalized circuit connection of
the XR-2228, along with either the XR-210 or the XR215 high frequency PLL IC, for tone- or carrierdetection application. Since the external connections
for the XR-210 or the XR-215 are the same as those
3-66
AN·12
+VCC
'"±
I-T-j
INP
UT
SIGN AL
O·
-.J'#tI
I
I
13
I
A~
l~,
I
I
I
I
f15
10 K
RA
14
3K
~--f-;O~~---l
XR-210
OR
XR·215
HIGH FREQUENCY
PHASE-LOCKED lOOP
3K
1
~R-222.
~
13
•
1
X
2
3
7
MULTIPLIER
I
fc~
I
I
I
_ _ _ _ _ _ _ _ _ .J
14
OUTPUT
9
1
10 K
CARRIER-
DETECT
TCA ,.
10 K
11
1.
i'O
0.1 /-IF
4
5
0.1/-1 F
10 K
•
~
RX
I
10 K
I
L-
2 "F
Figure 6_ Recommended Circuit Connection of the XR-2228 with the XR-210 or the XR-215 High-Frequency Phase-Locked Loops
for Tone- or Carrier-Detector Application_
lOGO
at a "low" state when the PLL is not locked on a tone,
and goes to a "high" state (near + VCe) when the PLL
circuit is locked on to an input tone. The output logic
polarity can be reversed simply by reversing the op
amp inputs.
I,;
!
800
'"c:>
..5
The filter capacitor, CA, connected across Pins 1 and
16 of the multiplier outputs, serves as the postdetection low-pass filter (Block 5 of Figure 1). The time
constant of this filter is equal to (CA RB where RB ( .. 8
KG is the internal resistance of the IC at Pins 1 and 16.
The value of CA is chosen to provide a compromise between the response time and the spurious noise rejection characteristics of the circuit: increasing CA improves the noise rejection characteristics of the circuit,
but slows down the response time.
/
~
'"cz
600
"iii
.
I-
:>
!
400
~
II
C
l-
V
'"c
'"
:I
I-
:>
:I
The detection threshold (minimum detectable input signal amplitude) varies inversely with the multiplier gainsetting resistor RX. Figure 7 shows the typical detectable signal level, as a function of Rx, with the output
offset resistor, RA, equal to 10 KG. Note that the minimum detectable input Signal, with RX = 0, is approximately 100 mV, rms.
Z
200
V
/
/
V
V
/
RA = (0 K!J
i
lK
2K
3K
4K
AX IN Kfl
Figure 7. Minimum Detectable Input Carrier Level, as a
Function of Multiplier Gain Setting ReSistor, RX-
3-67
SK
AN·13
Frequency-Selective AM Detection using
Monolithic Phase-Locked Loops
INTRODUCTION
This application note describes the use of monolithic
phase-locked loop (PLL) circuits in detection of
amplitude-modulated (AM) signals. The detection capabilities of a PLL system, which is a frequency-selective
FM demodulator, can be extended to cover AM signals
simply by the addition of an analog multiplier (or mixer)
and a low-pass filter to the basic phase-locked loop.
This technique of AM demodulation, which is called
synchronous AM detection, offers significant performance advantages over conventional peak-detector type
AM demodulators, in terms of its dynamic range and
noise characteristics.
The phase-locked loop AM detectors also operate on a
similar principle: the PLL is made to "lock" on the carrier frequency of the input AM signal; then the VCO output of the PLL will regenerate the unmodulated coherent carrier signal necessary for detection. When this
signal is mixed with the input AM signal and the resulting composite signal is passed through a low pass filter,
one obtains the demodulated output. Figure 2 gives a
block diagram of such an AM detector system. Compared to the basic synchronous AM detector system of
Figure 1, the phase-locked loop AM detector of Figure 2
also has one added feature: the output of the PLL control voltage (I.e., output of the PLL low-pass filter) can
be used as an FM detector or a frequency discriminator. Thus, such a system is capable of simultaneous AM
and FM detection. In other words, the frequency and
the amplitude modulation information present on the input signal can be separately and simultaneously demodulated. The particular design and application examples given in this application note fall into this category.
This application note outlines some of the fundamental
principles of synchronous AM detectors, and gives design examples using the XR-2228 multiplierldetector IC
in conjunction with the XR-215 and the XR-2212 monolithic PLL circuits.
PRINCIPLES OF OPERATION
The phase-locked loop AM detector circuits operate on
the so-called "coherent AM detection" principle, where
the amplitude modulated input signal is mixed with an
unmodulated "coherent" carrier Signal, and then lowpass filtered to produce the desired demodulated output signal. Figure 1 gives a simplified block diagram of
such a detector system.
AM SIGNAL
INPUT
Vm(t)cos,,,ot
~
X
Vo(+)
r---
MULTIPLIER
b
~
DEMODULATED
OUTPUT
KOVm(t)
LQWPASS
FILTER
1
UNMODULATEO
CARRIER SIGNAL
Eccoswot
The amplitude-modulated input signal can be described
by an expression of the form:
Figure 1 Block Diagram of a Synchronous AM Detector.
Input Signal = Vm(t) cos wot
where Vm(t) is the modulated amplitude of the input signal and Wo is the input signal frequency expressed in
radians. If this signal is linearly multiplied with an unmodulated signal which has the same frequency and
phase as the input Signal, then the output of the multiplier, VO(t), is a composite signal of the form:
Vo(t) = KO Vm(t) [1
+
AMORFM
INPUT
cos (2 wot)]
where KO is the gain of the multiplier circuit. If the
above signal is then passed through a low-pass filter, to
eliminate the double-frequency term, the resulting output signal is:
Vout
= Output Signal =
I--I--~
I
I
MUlTIPLJER
lOW PASS
I
~~Mo~~~'ltrTEO
L _____ F~E~ _ _ ._J
SYNCHRONOUS DETECTOR
KO Vm(t)
Figure 2. The Basic Phase-Locked Loop AM Detector.
which corresponds to the detected AM information.
3-68
AN·13
XR-2212 AND XR-2228 MONOLITHIC CIRCUITS
~ Vcc
PHASE DET
INPUT
PHASE DET
OUTPUT
OP AMP
INPUTS
TIMING
VCD
INPUT
12
~
X
4
V
DPAMP
OUTPUT
'-----
6
,
,i
9
Y,GAIN X-GAIN
SET
SET
Figure 4. Functional Block Diagram of XR-2228
Multiplier/Detector IC_
AM/FM DETECTION USING THE XR-2212 PLL
Figure 7 shows a generalized circuit connection diagram for a two-chip AM and FM detection system, utilizing the XR-2212 PLL and the XR-2228 multiplier/
detector. The XR-2212 section serves as the basic FM
detector. The quadrature output of its VCO (Pin 15) is
AC coupled to the Y input of the XR-2228.
The Y input of the XR-2228 is operated in its switching
mode, with the Y gain terminals (Pins 6 and 7) shorted
together. The AM and/or FM signal is simultaneously
applied to both circuits through coupling capacitors;
and all the mutliplier inputs are DC biased from the internal reference output of the XR-2212 (Pin 11). The output of the multiplier, at Pin 16, is AC coupled to the op
amp section of the XR-2228, which serves as the postdetection amplifier for the demodulated AM signal.
,CO
CAP
OP AMP
COMP
FOUR·CUADRANT
MULTIPLIER
VOLTAGE
OUTPUT
vco
02f--4
5
OP AMP
COMP
QUADRATURE
1413
2
X-INPUTS
DPAMP
OUTPUT
OUTPUT
16
I
The XR-2228 multiplier/detector IC is specifically intended as a basic building block for synchronous AM
detection. It contains a four-quadrant analog multiplier
and a high-gain op amp on the same chip, as shown in
the functional block diagram of Figure 4.
• Vcc
OP AMP
INPUTS
,
I"
The XR-2212 monolithic PLL is made up of an input preamplifier, a phase-detector, a high-gain differential amplifier and a stable voltage-controlled oscillator (VCO)
as shown in Figure 3. The key feature of the XR-2212
PLL is the temperature stability and the frequency accuracy of its VCO section; it offers 20 ppm/oC typical
temperature stability and a frequency accuracy of ±
1 % for an external RC setting. The oscillator section of
the XR-2212 contains a separate "quadrature output"
terminal (Pin 15) which is particularly intended for interfacing with a synchronous AM detector such as the XR2228.
MULl
OUTPUTS
The circuit configuration shown in Figure 7 can operate
with a single power supply, over the supply voltage
range, of 10V to 20V. Its operation or performance can
be tailored for any particular AM and FM detection application by the choice external components shown in
the figure, over a carrier frequency band of 1 kHz to
(TIMING
RESISTOR)
Figure 3. Functional Block Diagram of XR-2212 Precision
Phase-Locked Loop.
XR-215 HIGH FREQUENCY PHASE-LOCKED LOOP
The XR-215 is a high frequency phase-locked loop circuit capable operating with input signal frequencies up
to 35 MHz. It is comprised of a high frequency VCO, a
phase-detector and an op amp section, as shown in the
block diagram of Figure 5.
of
PHASE
COMPARATOR
Vee OUTPUTS
RANGE
SELECT
VCO
TIMING
CAPACITOR
>---11--"'--0 veo OUTPUT
PHASE
Unlike the XR-2212 PLL, the VCO section of the XR-215
does not have a separate quadrature output terminal.
However, such a quadrature oscillator signal can be obtained by amplifying and "slicing" the triangle waveform available across the timing capacitor (Pins 13 and
14) of the XR-215 oscillator section. Figure 6 shows the
relative phase relationship of these oscillator waveforms available from the circuit. The desired quadrature
output signal (curve C of Figure 6) can be obtained by
directly connecting one pair of the differential inputs of
the XR-2228 directly across the timing capacitor terminals of the XR-215.
COMPARATOR
INPUTS
vCOGAI"!
CONTROL
PHASE
COMPARATOR
BIAS
CPAMP
OPAMP
DPAMP
INPUT
COMPENSATION
OUTPUT
Figure 5. Functional Diagram of XR-215 High-Frequency
Phase-Locked Loop.
3-69
AN·13
(a)~
(b)
(c)
/\
/\
/\
/\
\/\/V\I\
nnnn
~
U U UL
This tracking bandwidth, .:If, is the band of frequencies in the vicinity of fO, over which the PLL can
maintain lock.
veo
OUTPUT
WAVEFORM
(PlfII15)
c) C1 sets the loop-damping factor for the PLL. For
most applications, C1 is chosen to be equal to onehalf of CO.
WAVEFORM ACROSS
veo TIMING CAP
IPINS 11 AND 12)
d) R2 and C2 form a low-pass filter for the detected FM
signal. The 3 dB frequencing, f2' of this low-pass filter is:
SLICED VERSION
OF TIMING CAP
WAVEFORM
Figure 6. Timing Diagrams of VCD Output Waveforms from
XR-215 Monolithic Phase-Locked Loop.
300 kHz. The functions of these external components
are as follows:
Normally, f2 is chosen to be equal to the demodulated FM information bandwidth.
a) RO and Co set the VCO center frequency for the XR2212 PLL circuit. The center frequency, fo, is given
as:
e) RC and RF1 set the gain of the op amp section of
the XR-2212 as:
fO
RF1
AV=1+-RC
ROCO
The VCO frequency fO is chosen to be equal to the
carrier frequency of the input signal. RO is normally
chosen to be in the range of 10 kO to 100 kO. This
choice is arbitrary. For most applications RO "" 20
kO is recommended. Once fO is given and RO is chosen, the Co can be calculated from the above equation.
This op amp section serves as the post-detection
amplifier for the demodulated FM signals.
f) RX sets the multiplier gain for the X input and RF2
sets the gain of the op amp section of the XR-2228.
Thus, the demodulated AM signal output swing, Vout,
for a given input signal of peak amplitude of VM and
modulation index of m (0 :s; m :s; 1) can be approximated as:
b) R1 determines the tracking bandwidth of the PLL.
For a required tracking bandwidth, Lif (see Figure 9
of XR-2212 data sheet) and fO, R1 can be calculated
as:
Vout = (VM)m RF2
4
RX
R fO
°Lif
1~~~==4==;--
r
e'~
w~
30pF
",
L
~-O--+---j
-;~~
I
JOpF
"OK
I
e'1"
AM OR FM
SIGNAL
INPUT
--0 DEMODULATED
____j-__~FMOUTPUT
~-6-"'---~_
12
",
'"
T
VV'v--------48
!.r
Figure 7. A Two-Chip AM/FM Detector System Using the XR-2212 Phase-Locked Loop and the XR-2228 Multiplier/Detector.
3-70
AN·13
Thus, for example, a 100 mV peak input signal with
30% AM modulation (m = 0.3) will give a demodulated output of 150 mV peak, with RF2 = 100 kll and
RX = 5 kll, at Pin 11 of the XR-2228.
input carrier level, the value of RF2 to get one
volt demodulated output is: RF2 = 67 kll.
Step 5) Calculate C3 to get 3 kHz bandwidth for postdetection filter: C3 '" 0.01 I'F.
g) C3, in conjunction with the 5 kll internal impedance
of the multiplier output (Pin 16) serves as the lowpass post-detection filter for the demodulated AM
signal.
AM DETECTION USING THE XR-215 PLL
Figure 8 shows the circuit connection diagram for a
two-chip AM and FM detection system, using the XR215 high-frequency PLL in conjunction with the XR2228 multiplier/detector. Because of the high-frequency
capability of the XR-215, the circuit of Figure 8 is useful
as a phase-locked AM detector for carrier frequencies
up to 20 MHz, and operates over a supply voltage range
of 10V to 20V.
For further explanation and description for the system
design equations, the reader is referred to the XR-2212
and the XR-2228 data sheets.
Design Example
Design an AM demodulator for 100 kHz carrier frequency with a detection (tracking) bandwidth of ±4%. The
demodulated information bandwidth is 3 kHz and an
output level of one volt peak is required for a one volt
peak input with 30% modulation.
The VCO section of XR-215 does not have a separate
quadrature output. However, this problem can be overcome by driving the XR-2228 multiplier directly from the
timing capacitor terminals (Pins 13 and 14) of XR-215.
The Y input of the XR-2228 is operated with maximum
gain, since the Y gain control terminals (Pins 6 and 7)
are shorted together. This causes the triangular waveform across Co to be converted to an effective quadrature drive as indicated by the timing diagram of Figure
6. The modulated input signal is simultaneously applied
to both circuits through coupling capacitors. The
phase-detector inputs of the XR-215, as well as the mUltiplier X inputs of the XR-2228, are biased at approximately one-half of VCC, by means of an external resistive divider.
Using the circuit of Figure 7, one proceeds as follows:
Since FM detection is not required in this example,
components R2, C2, RC and RF1 are not essential to
circuit operation. R2 and RC can be short-circuited, C2
and RF1 can be left open-circuited. The rest of the component values are calculated as follows:
Step 1) Set fO = 100 kHz by choosing RO = 20 kll and
calculating Co from paragraph (a) above.
1
Co = - - = 500 pF
ROfO
In Figure 8, Co sets the VCO frequency of the XR-215.
In the case of FM demodulation, R1 and C1 serve as
the post-detection filter for the detected FM signal and
RF1 sets the gain of the FM post-detection amplifier:
Step 2) Determine R1 to set tracking bandwidth to ±
4%, from paragraph (b): R1 = 500 kll.
Step 3) Calculate C1 :C1 '" CO/2 '" 250 pF.
The mode of operation of the XR-2228 is virtually the
same as that described in connection with Figure 7: RX
sets the multiplier demodulation gain; C3 serves as the
low-pass post-detection filter. The values of RX, RF2
and C3 are calculated as given in paragraphs (f) and (g).
Step 4) From paragraph (f), calculate the value of RX
and RF2. For a typical choice of RX = 5 kll,
and m = 0.3 (30% modulation) with one volt
ru~GfO~--J~----------------"MOO.'----------------------r-----~~~~v~~~
",
+Vcc
~.~ .. F
IC
1
2'
+Vcc
2.
,.
2.
2.
4.8JLF
Cc '" COUPLING CAPACITOR
Figure 8. Circuit Connection for a High-Frequency AM and FM Detector Using the XR-215 and XR-2228.
3-71
AN·14
High-Quality Function Generator System
with the XR-2206
INTRODUCTION
Waveform or function generators capable of producing
AM/FM modulated sine wave outputs find a wide range
of applications in electrical measurement and laboratory instrumentation. This application note describes
the design, construction and the performance of such a
complete function generator system suitable for laboratory usage or hobbyist applications. The entire function
generator is comprised of a single XR-2206 monolithic
IC and a limited number of passive circuit components.
It provides the engineer, student, 'or hobbyist with a
highly versatile laboratory instrument for waveform generation at a very small fraction of the cost of conventional function generators available today.
(a) Frequency Ranges: The function generator system is
designed to operate over four overlapping frequency ranges:
1 Hz to 100 Hz
10 Hz to 1 kHz
100 Hz to 10 kHz
1 kHz to 100 kHz
The range selection is made by switching in different timing capacitors.
(b) Frequency Setting: At any range setting, frequency
can be varied over a 100:1 tuning range with a potentiometer (see R13 of Figure 1).
GENERAL DESCRIPTION
(c) Frequency Accuracy: Frequency accuracy of the XR2206 is set by the timing resistor R and the timing
capacitor C, and is given as:
The basic circuit configuration and the external components necessary for the high-quality function generator
system is shown in Figure 1. The circuit shown in the
figure is designed to operate with either a 12 V single
power supply, or with ± 6 V split supplies. For most applications, split-supply operation is preferred since it
results in an output dc level which is nearly at ground
potential.
f = I/RC
The above expression is accurate to within ± 5 % at
any range setting. The timing resistor R is the series
combination of resistors R4 and R13 of Figure 1.
The timing capacitor C is anyone of the capacitors
C3 through C6, shown in the figure.
The circuit configuration of Figure 1 provides three basic waveforms: since, triangle and square wave. There
are four overlapping frequency ranges which give an
overall frequency range of 1 Hz to 100 kHz. In each
range, the frequency may be varied over a 100:1 tuning
range.
(d) Sine and Triangle Output: The sine and triangle output
amplitudes are variable from 0 V to 6 Vpp. The amplitude is set by an external potentiometer, R12 of
Figure 1. At any given amplitude setting, the triangle output amplitude is approximately twice as high
as the sinewave output. The internal impedance of
the output is 600 O.
The sine or triangle output can be varied from 0 to over
6 V (peak to peak) from a 600 ohm source at the output
terminal.
(e) Sinewavs Distortion: The total harmonic distortion of
sinewave is less than 1 % from 10Hz to 10kHz and
less than 3% over the entire frequency range. The
selection of a waveform is made by the triangle/sine
selector switch, 82.
A squarewave output is available at the sync output terminal for oscilloscope synchronizing or driving logic circuits.
TYPICAL PERFORMANCE CHARACTERISTICS
(f) Sync Output: The sync output provides a 50 % duty
cycle pulse output with either full swing or upper
half swing of the supply voltage depending on the
choice of sync output terminals on the printed circuit board (see Figure 1).
The performance characteristics listed below are not
guaranteed or warranted by Exar. However, they represent the typical performance characteristics measured
by Exar's application engineers during the laboratory
evaluation of the function generator system shown in
Figure 1. The typical performance specifications listed
below apply only when all of the recommended assembly instructions and adjustment procedures are followed:
(g) Frequency Modulation (External Sweep): Frequency can
be modulated or swept by applying an external control voltage to sweep terminal (Terminal I of Figure
1). When not used, this terminal should be left open3-72
AN·14
AMPLITUDE
012
AM INPUT
OUTPUT
,------0
----------------,
Q
I
I
I
I
V-~r_~----~------~--~~--~--------------------~------------_,
-6V
GND
I
is
Cl 10J.l/l0V
lr
~
Al
r--4__
~oAxr_~~~~--~·DK
I
I
XA·2206
DC
R9
07
1K
TAl/SINE SW
o
OFFSET
1M
V+~c-~-+--~~0~2~100=K~--------~~
+6V
r-------1r-----------+--"'V- SYNC
OUTPUT
(FULL SWING)
~f"D."""'---;
C7
R6
~I-'D"".D1"'-"_-+
51
O.
~O.OOlJ.l
L
10p)6V
5K
"'
1K
___________
'--------------------'\fVI,----4>---c---------+---<;>- SYNC OUTPUT
(HALF SWING)
RS SK
OK
I
I
I
-.J
I
R13
V-
1M
SWEEP
INPUT
FAEQUENCY
NOTE:
1. For Single Supply Operation Lift GND Connection Keeping R12 Across Terminals Rand B Intact, and Connect
Terminal A to GND.
2. For Maximum Output, AX may
be open. RX
= 68 K!2 is Recommended for
External Amplitude Modulation.
Figure 1. Circuit Connection Diagram for Function Generator. (See Note 1 for Single Supply Operation.)
circuited. The open circuit voltage at this terminal is
approximately 3V above the negative supply voltage
and its impedance is approximately 1000 ohms.
inversely proportional to the timing capacitor connected across Pins 5 and 6 of the XR-2206 circuit. Nominal
capacitance values and frequency ranges corresponding to switch positions of Sl are as follows:
(h) Amplitude Modulation: The output amplitude varies linPosition
early with modulation voltage applied to AM input
(terminal Q of Figure 1). The output amplitude
reaches its minimum as the AM control voltage approaches the half of the total power supply voltage.
The phase of the output signal reverses as the amplitude goes through its minimum value. The total
dynamic range is approximately 55 dB, with AM
control voltage range of 4V referenced to the half of
the total supply voltage. When not used, AM terminal should be left open-circuited.
1
2
3
4
Nominal Range
Timing Capacitance
1 Hz to 100 Hz
10 Hz to 1 kHz
100 Hz to 10 kHz
1 Hz to 100 kHz
l/-1 F
0.1 /-IF
O.Ol/-1 F
0.001 /-IF
If additional frequency ranges are needed, they can be
added by introducing additional switch positions.
Triangle/Sine Wavefor.m Switch, S2: Selects the triangle
or sine output waveform.
(I) Power Source: Split supplies: ± 6 V, or single supply: +
12 V. Supply Current 15 mA (see Figure 3).
Trimmers and Potentiometers
EXPLANATION OF CIRCUIT CONTROLS:
Switches
Dc Offset Adjustment, R9: The potentiometer used for
adjusting the dc offset level of the triangle or sine output waveform.
Range Select Switch, Sl: Selects the frequency range
of operation for the function generator. The frequency is
Sinewave Distortion Adjustment, Rl0: Adjusted to minimize the harmonic content of sinewave output.
3-73
AN·14
Sinewave Symmetry Adjustment, R11: Adjusted to optimize the symmetry of the sinewave output.
Capacitors:
C1,C2,C7
C3
C4
C5
C6
Amplitude Control, R12: Sets the amplitude of the triangle or sinewave output.
Frequency Adjust, R13: Sets the oscillator frequency
for any range setting of S1. Thus, R13 serves as a frequency dial on a conventional waveform generator and
varies the frequency of the oscillator over an approximate 100 to 1 range.
Resistors:
B.
C.
D.
E.
F.
G.
H.
I.
J.
K.
L.
M.
N.
O.
P.
Q.
R.
Negative Supply -6V
Ground
Positive Supply + 6V
Range 1, timing capacitor terminal
Range 2, timing capacitor terminal
Range 3, timing capacitor terminal
Range 4, timing capacitor terminal
Timing capacitor common terminal
Sweep Input
Frequency adjust potentiometer terminal
Frequency adjust potentiometer negative
supply terminal
Sync output (1/2 swing)
Sync output (full swing)
Triangle/sine waveform switch terminals
Triangle/sine waveform switch terminals
Triangle or sinewave output
AM input
Amplitude control terminal
30 KO, 1/4 W, 10%
100 KO, 1/4 W, 10%
1 KO, 1/4 W, 10%
9 KO, 1/4 W, 10%
5 KO, 1/4 W, 10%
300 KO, 1/4 W, 10%
62 KO, 1/4 W, 10% (RX can be eliminated
for maximum output)
R1
R2
R3, R7
R4
R5, R6
Terminals
A.
Electrolytic, 10 /LF, 10V
Mylar, 1 /LF, nonpolar, 10%
Mylar, 0.1 J.tF, 10%
Mylar, 0.01 /LF, 10%
Mylar, 1000 pF, 10%
AS
RX
Potentiometers:
Trim, 1 MO, 1/4 W
Trim, 1 KO, 1/4 W
Trim, 25 KO, 1/4 W
R9
R10
R11
The following additional items are recommended to
convert the circuit of Figure 1 to a complete laboratory
instrument:
Potentiometers:
R12
R13
Amplitude control, linear, 50 KO
Frequency control, audio taper, 1 MO
PARTS LIST
Switches:
The following is a list of external circuit components
necessary to provide the circuit interconnections
shown in Figure 1.
S1
S2
(a) Split Supply PC Board Layout
Rotary switch, 1-pole, 4 positions
Toggle or slide, SPST
(b) Single Supply PC Board Layout
Figure 2_ Recommended PC Board Layout for Function Generator Circuit of Figure 1_
3-74
AN·14
Case:
Any simple power supply having reasonable regulation
may be used. Figure 3 gives some recommended
power supply configurations.
7" X 4" X 4" (approx.) Metal or Plastic
(See Figures 4(a) and 4(b).)
Precaution: Keep the lead lengths small for the range
selector switch.
Power Supply:
Dual supplies ± 6 V or single + 12 V
Batteries or power supply unit
(See Figures 3(a) and 3(b).)
ADJUSTMENT PROCEDURE
When assembly is completed and you are ready to put
the function generator into operation, make sure that
the polarity of power supply and the orientation of the
IC unit are correct. Then apply the dc power to the unit.
Miscellaneous:
Knobs, solder, wires, terminals, etc.
To adjust for minimum distortion, connect the scope
probe to the triangle/sine output. Close S2 and adjust
the amplitude control to give non-clipping maximum
swing. Then adjust R10 and R11 alternately for minimum distortion by observing the sinusoidal waveform. If
a distortion meter is available, you may use it as a final
check on the setting of sine-shaping trimmers. The minimum distortion obtained in this manner is typically less
than 1 % from 1 Hz to 10 kHz and less than 3% over
the entire frequency range.
BOARD LAYOUT
Figures 2(a) and 2(b) show the recommended printedcircuit board layout for the function generator circuit of
Figure 1.
RECOMMENDED ASSEMBLY PROCEDURE
The following instructions and recommendations for
the assembly of the function generator assume that the
basic PC board layout of Figure 2(a) or 2(b) is used in
the circuit assembly.
'''J~
All the parts of the generator, with the exception of frequency adjust potentiometer, amplitude control potentiometer, triangle/sine switch and frequency range select
switch, are mounted on the circuit board.
Install and solder all resistors, capacitors and trimmer
resistors on the PC board first. Be sure to observe the
polarity of capacitors C1, C2, C7. The timing capacitors
C3, C4, C5 and C6 must be non-polar type. Now install
IC1 on the board. We recommend the use of an IC socket to prevent possible damage to the IC during soldering and to provide for easy replacement in case of a
malfunction.
+. v
os
GNO
O•
•V
-. v
51 R2
rt:
(8) Zener Regulated Supply
~~'!..--l~+'v
The entire generator board along with power supply or
batteries and several switches and potentiometers will
fit into a case of the type readily available at electronic
hobby shops. It will be necessary to obtain either output
jacks or terminals for the outputs and am and frequency sweep inputs.
--
+
~GNO
1-- • V
-1-=
1-----0-. v
-
(b) Banery Power Supply
T1: Filament Transformer
Primary 115VlSeconduy 12.6 VCT, O.SA
01 - 04: IN4001 or Similar
05, 06:
IN4735 or similar
Rl, R2: 5111, 1/2W, 10%
Install the frequency adjust pot, the frequency range
select switch, the output amplitude control pot, the
power switch, and the triangle/sine switch on the case.
Next, install the PC board in the case, along with a
power supply.
Figure 3. Recommended Power Supply Configurations.
3-75
AN·15
An Electronic Music Synthesizer using the
XR·2207 and the XR·2240
INTRODUCTION
Figure 3 shows the circuit connection for the electronic
music or time synthesizer system using the XR-2207
and the XR-2240. The XR-2207 produces a sequence of
tones by oscillating at a frequency set by the external
capacitor C1 and the resistors R1 through R6 connected to Pins 4 through 7. These resistors set the frequency or the "pitch" of the output tone sequence. The
counterltimer IC generates the pseudo-randorn pulse
patterns by selectively counting down the time-base
frequency. .The counter outputs of XR-2240 (Pins 1
through 8) then activate the timing resistors R1 through
R6 of the oscillator IC, which converts the binary pulse
patterns to tones. The time-base oscillator frequency of
the counterltimer sets the "beat" or the tempo of the
music. This setting is done through C3 and RO of Figure
This application note describes a simple, low-cost "music synthesizer" system made up of two monolithic IC's
and a minimum number of external components_ The
electronic music synthesizer is comprised of the XR2207 programmable tone generator IC which is driven
by the pseudo-random binary pulse pattern generated
by the XR-2240 monolithic counter/timer circuit
PRINCIPLES OF OPERATION
All the active components necessary for the electronic
music synthesizer system is contained in the two lowcost monolithic IC's, the XR-2207 variable frequency
oscillator and the XR-2240 programmable counter/
timer. Figure 1 shows the functional block diagram of
the XR-2207 oscillator. This monolithic IC is comprised
of four functional blocks: a variable-frequency oscillator
which generates the basic periodic waveforms; four
current switches actuated by binary keying inputs; and
buffer amplifiers for both the triangle and squarewave
outputs. The internal current switches transfer the oscillator current to any of four external timing resistors to
produce four discrete frequencies which are selected
according to the binary logic levels at the keying terminals (pins 8 and 9).
3.
The pulse sequence coming out of the counterltimer IC
can be programmed by the choice of counter outputs
(Pins 1 through 8 of XR-2240 connected to the programming pins (Pins 4 through 7) of the XR-2207 VCO. The
connection of Figure 3 is recommended since it gives a
particularly melodic tone sequence at the output
The pseudo-random pulse pattern out of the countertimer repeats itself at 8-bit (or 256 count) intervals of
the time-base period. Thus, the output tone sequence
continues for about 1 to 2 minutes (depending on the
"beat") and then repeats itself. The counterltimer resets to zero when the device is turned on; thus, the music, or the tone sequence, always starts from the same
point when the synthesizer is turned on.
The XR-2240 programmable counter/timer is comprised
of an internal time-base oscillator, a control flip-flop and
a programmable 8-bit binary counter. Its functional
block diagram is shown in Figure 2, in terms of the 16pin IC package. The eight separate output terminals of
the XR-2240 are "open-collector" type outputs which
can either be used individually, or can be connected in
a "wired-or" configuration.
,------.
TIMING
CAPACITOR
L
TIMING
RESISTORS
Figure 1. Functional Block Diagram of XR-2207 Oscillator
Circuit.
Figure 2. Functional Block Diagram of XR-2240 Counter/
Timer.
3-76
AN·15
RS
R9
+12V
VOLUME
CONTROL
R7
XR·2207
SPEAKER
RO THRU R6; 100K
R7; 10 KS1
+12V o---*-------.J
I
C4
1 /lF
R16
OFF
-{)
ON
+12V
Figure 3. Circuit Connection Diagram lor the Music Synthesizer.
3·77
+12\
AN·16
Semi-Custom LSI Design with 12L
Gate Arrays
INTRODUCTION
The 12L logic technology is developed around the basic
single-input, mUltiple-output inverter· circuit shown in
Figure 2. A recommended circuit symbol for this gate
circuit is also defined in the figure. Most terminals of
the 12L gate share the same semi-conductor region (for
example, the collector of the PNP is the same as the
base of the NPN; and the emitter of the NPN is the
same as the base of the PNP). This leads to a very compact device structure, and results in very high packing
density in monolithic device fabrication. Figure 3 illustrates the basic device structure and the cross-section
for a bipolar-compatible 12L gate. Since the individual
12L gates do not require separate P-type isolation diffusions, they can be placed in a common N-type tub. This
feature greatly enhances the packing density on the
chip since it eliminates the need for separate isolation
pockets for individual gates. With conventional photomasking and diffusion tolerances, gate densities of
greater than 200 gates/mm 2 can be readily achieved in
full-custom layout. Using the semi-custom approach
which is outlined in this paper, one can maintain a packing density of greater than 120 gates/mm 2 even with
random metallization or interconnection requirements.
This offers at least a factor of four improvement over
conventional bipolar master-slice technology and approximately a factor of two improvement over MOS
master-slice approach in terms of gate-density and chip
area utilization.
In designing semi-custom monolithic LSI, one uses a
partially fabricated silicon wafer which is "customized"
by the application of one or more special mask patterns. This technique greatly reduces the design and
tooling cost and the prototype fabrication cycle associated with the conventional full-custom IC development
cycle; and thus makes custom IC's economically feasible even at low production volumes.
Until recently, the application of semi-custom design
technology to complex digital systems has been somewhat limited due to one key factor: to be economically
feasible, a complex digital LSI chip must achieve a high
functional density on the chip (I.e., high gate count per
unit chip area). Traditionally, this requirement is not
compatible with the random interconnection concept
which is key to the semi-custom or master-slice design
approach. This paper describes a new approach to the
master-slice concept which overcomes this age-old
problem. It achieves packing densities approaching
those of full-custom digital LSI layout while still maintaining the low-cost and the quick turn-around attributes of semi-custom IC design. This is achieved by
making use of unique layout and interconnection properties of 12L gates, and by extending the maskprogramming to additional mask layers besides the
metal interconnection.
FEATURES OF 12L TECHNOLOGY
10j.js
Integrated Injection LogiC (12L) is one of the most significant recent advances in the area of monolithic LSI
technology. Compared to other monolithic LSI technologies, 12L offers the following unique advantages:
,.,---,-----r---.,---,-----,
PMOS
High Packing Density
Bipolar Compatible Processing
Low Power and Low Voltage Operation
Low (Power x Delay) Product
Figure 1 gives a comparison of the speed and power
capabilities of various logic families, including 12L.
Since 12L technology is a direct extension of the conventional bipolar IC technology, it readily lends itself to
combining high-density digital functions on the same
chip along with conventional Schottky-bipolar circuitry.
The availability of bipolar input-output interface on the
same chip along with the high-density 12L logic makes it
very convenient to retrofit custom 12L designs into
many existing logic systems.
ECl
",
'"S,L:,w::---:,o::-1,=w--::,oo::"-,=w---;'~mw:--~,:;;om::;w;;--~,oo~mw
POWER!GATE
Figure 1. Comparison of Speed and Power Capabilities 01
Various Logic Families.
3-78
AN·16
Table 1
List of Components on XR-300 and XR-500
Semi-Custom Chips
A
0----+--1
Component Type
Multiple Output 12L Gates
Input/Output Buffers
. Schottky - NPN Transistors
Resistors
Bonding Pads
Chip Size (mils)
(b)
(a)
Figure 2. Equivalent Circuit (aI, and a Recommended
Symbol (b) for an 11L Gate.
.~:
~
ISOLATION
A
Chip Type
XR-500
XR-300
288
28
56
168
34
104 x 140
520
40
80
240
42
122x 185
0----+-1
,
,----,.----------------,
~ 1~l[~L~I~
Figure 4. Basic Architecture of XR-300 and XR-500 12L Gate
Arrays.
a) The 12L Gate Matrix;
------
LuNvIN'''J,
~ h1/ector Contact
Gatf! Output
t;l = Gate Input
o .
'tij
~:Undf!rpiss
~It
-
·~ -''''. -. ""-.
,......
INPU~
Q,
""
""
· . "" .
·.
5il/=ii:: ~'" [2e
~
·· .
=
\
}~
~!:: ~ ~
DOTS INO ICATE LOCATION OF
INPUT 10UTPUT SITES
Figure 5. Basic B-Gate Cell Before Customization.
~ lr
t
I",
The custom logic interconnections can be easily laid
out in pencil on a layout sheet by simply interconnecting the desired gate "sites" with a pencil line
and appropriately defining the function of the site as
an input, output, injector contact or an underpass.
Figure 6 shows a typical example of such a logic layout. The corresponding symbols defining the function of the sites on the layout are also identified in
the figure. For convenience, an underpass is indicated with a resistor symbol, connecting two trian·
gles corresponding to the terminal points of the underpass.
Q~
-,
INJECTOR
BUS
~
~
,~
~
...!. .!. ...:...
..:..
0,
I
r-
Figure 6. Sample Pencil layout on a logic Cell.
---.J
GATE INPUT
Figure 7 shows the sample layout of the same B-gate
cell, after its customization with a selective N-type
collector diffusion, contact-window cut and the metal interconnection patterns.
INPUT
GATE OUTPUT
METAL
INTERCONNECTION
DIFFUSEO
UNDERPASS
Typical electrical characteristics of the 12L gates
within the gate matrix are listed in Table 2. Typical operating characteristics of the gates are given in Fig-
INJECTOR
eus
Table 2
Typical Characteristics of 12l Gates
~pl..1 Ch,ncl8rlstlcs
a,
,I Yarlou. Inloctor Currents
Parameter
11~100 nA
11-1 ~A
11-10~A
11-100 ~A
Oulput Sink Current. 10
Oulput Set. Voltage. VOL
Input Threshold
Pwr.-Oelay Product (V+ ~ tV)
300 nA
3mV
0.48 mV
0.6 pJ
8~A
3mV
0.54 mV
0.6 pJ
80 ~A
4 mV
0.60 mV
t.O pJ
600 ~A
to mV
0.66 mV
3 pJ
Average Prop Delay
S "sec
0.6 "sec
200 nsec
50 nsec
Max. Toggle Freq (0 F/F)
Input OFF Current (V'N~O)
Output Breakdown Voltage
6 kHz
t50nA
3V
60 kHz
400 kHz
3 MHz
t.5~
t5~
t30~
3V
3V
3V
---,
1'Figure 7. Sample layout of B-Gate Call Altar Customizing it
with N+ Collactor Diffusion, Contact Mask and
Metal Interconnection Pattern.
3-BO
AN·16
operation with Ij S 50 pA, turn-off delay becomes the
dominant limitation in speed. Typical toggle rate of a
D-type flip-flop as a function of injector current is
shown in Figure 10. As indicated in the figure, toggle
rates of 3 MHz are obtained at injector current levels
of approximately 100 p.A per gate.
For operating with current levels below 1 p.A/gate, an
external current setting resistor can also be used.
The component layout of a typical bipolar input!
output interface cell is shown in Figure 11. Such an
I/O interface cell contains one bonding-pad, several
diffused resistors of varying values, two Schottkyclamped NPN transistors and a clamp diode to the
substrate. Each of the NPN bipolar transistors are
capable of sinking 1OmA of output current, with typically a saturation voltage of 0.5V. The breakdown
voltage of the bipolar output transistors is 6V; however, modified versions of the XR-300 and XR-500
12L gate arrays are also available with output breakdown voltage in excess of 15V. Figure 12 shows
some of the most commonly used input and output
~~N::l[[!ffiDSl
,,",I'--_--,--____
Figura 8. Propagation Delay Characteristics of 12L Gatas as a
Function of Injector Current.
II
PAD
d!~~
~J-
--
R1
>
10K
Figure 11. A Typical Schottky-BIpolar Input/Output Interface
Cell.
Figure 9. Average Turn-On and Turn-Off Delay vs. Injector Current.
U
=
Q1_
10MHz
. . - - - _ T O 12L GATES
~
::J
~
...
I[
w
.J
""0
...
~
::J
:!
..
, MHz
500
200
100 kHz
50
x
20
~
10 kHz
O.OlIlA
'.A
10IJA
100,uA
(a) Input Interface Circuit
, mA
...----.....--v+
INJECTOR CURRENT PER GATE
Figure 10. Maximum Toggle Rate of 0-Type Flip-Flop as a
Function 01 Injector Current.
5K
b) Schottky-Bipolar I/O Section:
The Schottky-bipolar input/output interface sections
are located along the periphery of the XR-300 and
the XR-500 gate array chips. In addition, this bipolar
section of the chip contains two sets of resistor arrays located at oppOSite ends of the chip (see Figure
4) for programming or setting the injector current
levels for the 12L gates. By proper tapping of these
resistor arrays, the injector currents of the gates can
be set to any value between 1 pA to 100 p.A per gate.
FROM 12L GATE ....._
......~
OUTPUT
(b) Output Interface Circuit
Figure 1;i. Tyipcal Bipolar I/O Interface Circuits.
3-81
AN·16
the appropriate array worksheet. This pencil layout is
done on a blank worksheet where the gate input and
output locations are shown as target dots (see Figure
5). During the layout, an appropriate symbol is placed
over the corresponding dot on the gate outline, and the
interconnections and the underpasses between the
gates are indicated by pencil lines and with the symbols
defined in tM layout example of Figure 6. In this layout,
the bipolar 1/0 cells do not need to be internally interconnected. Since these cells are standardized, it is only
necessary for the designer to specify if a particular 1/0
cell is to be used as an input or an output.
interface circuit configurations available from the
basic bipolar 110 cell.
SEMI-CUSTOM DESIGN CYCLE
The semi-custom LSI design program utilizing the XR300 and XR-500, is devised for maximum versatility, to
suit varying customer needs or capabilities. Figure 13
gives an outline of the six basic steps associated with a
typical 12L semi-custom program. The sequence of
these steps are also outlined below:
(I)
Feasihility Review
and
Logic Conversion to 12 L Gates
Step 3. Computerized Mask Artwork Generation:
f
Using a specially developed computerized mask generation technique, the three layers of necessary custom
Ie tooling (i.e., for custom N-type diffusion, contact window cut; and the metal interconnections) can be automatically generated by a single "digitizing" step from
the pencil layout. This simultaneous and automated
generation of the three custom mask layers greatly reduces the tooling cost and turnaround time, and avoids
mask errors.
(2)
Pencil Layout on Gate Array Worksheets
(3)
(4)
(5)
•
computerized Mask Artwork
Generation
Step 4. Mask fabrication:
.-
The photographic tooling plates, or "masks," are fabricated by a pattern-generation technique from the digitized coordinate information stored in the computer.
Mask Fahrication
N+/Contact/Metal Masks
•
Step 5. Customizing Prefabricated Wafers:
The prefabricated 12L wafers containing the P-type base
diffusion and the gate "fingers" (see Figure 5) are customized into completed monolithic LSI chips using the
custom Ie tooling generated in Steps 3 and 4.
Customizing Pre-Fah Wafers:
Collector Diff./Contact and Metal
t
(6)
Step 6. Assembly/Test and Prototype Delivery:
Assem hly ITest and
Prototype Delivery
The completed monolithic chips are first evaluated on
the finished Ie wafer, and later assembled, electrically
tested and delivered as the completed prototypes.
Figure 13. Sequence of Steps Associated with a SemiCustom lSI Development Cycle.
In many cases, the first two steps indicated in the flow
chart of Figure 13, can be done by" the customer, in consultation with Exar, using Exar's 12L Design Kit and the
design instruction manual. Whenever possible, such an
approach is recommended, since it greatly reduces the
development costs and the turnaround time.
Step 1. Feasibility Review and Logic Conversion:
Starting with the customer's logic diagram (preferably
reduced to flip-flops and gates) the first step is a detailed review of the system requirements with regards
to the overall gate count, 1/0 requirements, operating
speeds, etc., to assure feasibility of integration, and to
choose the most economical gate array chip to be
used. If the results of this review indicate feasibility, the
next step is to convert the logic diagram into 12L gates.
At this state, a computer simulation of the logic diagram may also be performed, if deemed necessary.
Typical development cycle containing all the steps outlined in the flow chart of Figure 13, takes about 8 to 12
weeks, depending on the circuit complexity, and whether the customer or Exar does the logic conversion and
pencil layout.
Figure 14 shows the photo-micrograph of a typical
semicustom LSI chip, fabricated using the technology
outlined in this paper. As indicated in the figure, the use
of 3-mask customization step results in an efficient layout and utilization of the available active devices within
the 12L gate array.
Step 2. Pencil Layout on Gate Array Worksheets:
Once the logic diagram is converted to 12L gates, the
next step will be to make a pencil layout of the circuit on
3-82
AN·16
tremely high development costs (typically in the range
of $50,000 to $100,000) associated with full custom designs make the amortized unit cost of full custom IC's
far more expensive than semi·custom designs, at low
production quantities. Similarly, for the lower chip cost
of full custom IC's make this approach more economi·
cal for high production volumes. Typical cross·over
point between the economics of the full or semi·custom
technology comes about in the quantity range of
50,000 pieces to 150,000 pieces, as implied by the illus·
tration of Figure 15. However, it should be noted that
Figure 15 is only a typical "case study," and that the ac·
tual cross·over point for a given program will depend on
the circuit complexity, performance and test require·
ments, and the type of IC package used.
1000K
Figure 14. Photo-Micrograph of a Typical Seini-Custom
12l lSI Chip.
Total Quantity of Units Purchased
Figure 15. A Comparison of Relative Cost Advantages of SemiCustom and Full Custom lSI Products. (NOTE: Amortized cost per unit includes the development
cost.)
ECONOMICS OF SEMI-CUSTOM DESIGN
In developing custom LSI circuits, one is confronted by
the following key question: for a given production reo
quirement, is it cheaper to develop a full or semi·
custom IC? Since the performance and functional reo
quirements of custom IC's vary greatly, there is no gen·
eral answer to the above question. However, based on
the overall production requirements it is possible to es·
tablish some economic guidelines for deciding which
custom IC technology to use, and when.
CONVERTING SEMI-CUSTOM TO FULL CUSTOM
It is often possible to start a development program us·
ing the semi·custom technology, such as the 12L gate
arrays described in this paper, and later change to a full
custom design when the production quantities increase
beyond the cost cross·over point illustrated in Figure
15. Such two·phase approach often combines the best
advantages of each of the semi· and full custom tech·
nologies. For example, the initial development can be
done in a semi·custom manner, using Exar's 12L gate
arrays, and thus take full advantage of the low tooling
cost and the short development cycle. As a customer's
product matures and its market expands, resulting in
higher volume production run rates, Exar can convert
the multiple semi·custom chip approach into a single
custom IC, achieving a cost reduction and in many
cases a performance improvement. The significant ad·
vantage of this type of program is that the risk associ·
ated with a custom development is greatly reduced; the
IC design approach has been proven, and the deSign
"bugs" are removed at the semi·custom stage thus
eliminating the need for lengthy re·design cycles at the
full custom level. Once the semi·custom chip is com·
pletely characterized in the user's system, and is used
for the initial production runs, it can be gradually
"phased'out" by a full custom design without interrupt·
ing the user's production line.
One of the main advantages of semi·custom LSI design
over conventional full custom IC development is the
greatly reduced development cost. This development
cost generally amounts to 10% to 30% of that required
for a complete custom IC design. However, since the
semi·custom design technique tends to waste sor,le of
the IC chip area due to random interconnections, the
unit price of a semi·custom LSI chip in volume produc·
tion is slightly higher (approximately 10% to 30%) then
a full or complete custom design. Therefore, to decide
which is the most economical approach, it is best to
compare the estimated amortized unit cost per device
for various production quantities. Figure 15 gives such
a comparison for a "typical" custom LSI chip, as a
function of total production requirement. The total am·
ortized cost per unit is defined as the total cost of the
development plus the production purchase, divided by
the total number or quantity of units purchased. The ex·
3·83
AN·17
XR·C409 Monolithic 12L Test Circuit
INTRODUCTION
sections of XR-C409 is set by the external bias resistor,
RB, as:
The XR-C409 monolithic IC is a test circuit for evaluation of speed and performance capabilities of Exar's Integrated Injection Logic (l2L) technology. It is intended
to familiarize the 12L user and the digital system designer with some of the performance features of 12L, such
as its high-frequency capability and power-speed tradeoffs.
V+ - Vbe
(1)
RB
where Vbe ("" 0.7V) is the transistor base-emitter voltage drop.
Figure 1 shows the package diagram of the XR-C409
12L test circuit. It is comprised of five separate evaluation blocks as shown in the figure. Blocks 1 and 2 are
Ootype flip-flops which are internally connected as frequency dividers. Each of these dividers provide buffered open-collector outputs. Blocks 3, 4, and 5 are 8stage ring-oscillators with buffered outputs to be used
for measuring gate propagation delays at different injector current levels.
The total injector current, IT, is shared among 16 individual 12L gates forming the frequency-divider sections.
Thus, the operating current of each gate, Ij, is equal to
1/16 of the total injector bias, or:
(2)
Ij = IT/16
FREQUENCY DIVIDER SECTION
INJECTOR A
The frequency divider sections of XR-C409 test circuits
are made up of two Ootype flip-flops internally connected in the ( + 2) mode. These frequency dividers are operated with serial clocking and parallel reset controls.
4 OUTPUTS
CLOCK INPUT
r
RESET
OUTPUT
03
The internal interconnections of these Ootype flip-flop
sections are shown in Figure 2. The corresponding
package terminals are also identified in the figure. The
flip-flops operate on the negative-transitions of the
clock input, and reset with the reset at a "high" logic
state. When the circuit is reset, all the outputs go to a
"low" state. The logic polarities and the timing sequence of the circuit waveforms are given in Figure 3.
0, I 2)
INJECTOR 8
N.C.
OSCILLATOR
OUTPUT
N.C.
INJECTOR C
N.C.
OSCILLATOR
Evaluating the Frequency Divider Section
OUTPUT
OSCILLATOR
OUTPUT
GROUND
(SUBSTRATE)
INJECTOR 0
Figure 1. Package Terminals for XR·C4D9 Test IC.
Figure 4 shows the circuit connection for the frequency
divider section of the XR-C409. The recommended
clock input level is OV and + 1V for the "low" and
"high" levels. For optimizing high frequency performance, a square wave clock input is recommended with
a source impedance ~ 1000.
INJECTOR
...-------0
~
2 OUTPUT
'4
2
Biasing of Injectors
} + 4 OUTPUTS
All of the 16 12L gates forming the frequency divider
sections are biased by the total injector current, IT, applied to the injector terminal (Pin 1) as shown in Figure
4. The total injector current, IT, applied to the flip-flop
RESET
0-------------'
3
'5
Figure 2. Block Diagram of Frequency Divider Section.
3-84
AN·17
The value of the load resistor, RL, is determined by the
current sinking capability of the output transistor, T 1, in·
ternal to the chip. Since T1 is the output of an 12L gate,
its worst case sinking current is limited to the individual
gate current, i.e.:
CLOCK INPUT
(PIN 161
r-
RESET - - ,
(PIN lSI
IL-_ _ _ _ _ _ _ _ _ _ _--II
-:- 2 OUTPUT
(PIN 141
IT
16
+ 4 OUTPUTS
(PINS 2 AND 31
----'
(3)
This current·sinking capability in turn limits the minimum value of load resistance RL to:
Figure 3. Timing Diagram for Frequency Divider Section.
(4)
V'
Rl
elK INPUT
.'l
300!~
BRB
RB
• 'T
+~1UL
The peak output swing is limited to approximately 3
volts due to the collector-base breakdown of the 12L
gate output, i.e., transistor T1 of Figure 5 .
5V ---~-----,
High Frequency Capability
Rl
16
o-""VII'v--c......
:7 o-""300",,,,!~~'>5-i
ENABLE
U
OUTPUT
XA-C409
E
OR 14)
0,
..........,,....01'" LOW CAPACITANCE
CLAMPOIODE
The maximum operating frequency of 12L frequencydivider circuits is a function of the total injector current.
For low-current operation, the maximum togglefrequency of the flip-flops forming the frequency-divider
section increases linearly with increasing injector current. Typical maximum toggle frequency vs. injector
+O.7V
O
(PIN 2, 3,
':'
':'
TOMHl,----,.---,-----,---,.-----,
Figure 4. Test Circuit for Frequency Divider Section.
>
u
z
Measuring Output Waveforms
Each of the output terminals of XR-C409 frequencydivider are open-collector type terminals which require
a pull-up resistor to positive supply voltage. Thus, the
output rise-time is limited by the external RC time constant due to the load resistance, RL, and the parastic
andlor load capacitance, CL.
~
500
"g
200
~ l00kHll--~--_+----,,...-+_--_+---+
•x
·•
50
20
10mA
Figure 5 shows a recommended circuit connection to
test the output swing at high frequencies, using a lowcapacitance clamp-diode, D1, to clamp the output
swing to "" +0.7V above ground.
TOTAL INJECTO~ CURRENT, IT. APPLIED TO PIN 1 116 GATES!
Figure 6. Typical Maximum Toggle Frequency vs. Injector
Current Characteristics for XR-C409 Frequency
Divider Section
(NOTE: Clock Input: 1V pop Square Wave)
v'
current characteristics are shown in Figure 6. Note that
the maximum toggle-rate obtainable is in the range of 3
to 5 MHz, at a total injector current level of 1 to 2 mA,
which corresponds to individual injector currents of approximately 60 p.A to 120 p.A per gate.
OUTPUT
0,
=
RING-OSCILLATOR SECTIONS
CLAMP DIODE
0,
The ring-oscillator sections of XR·C409 test circuit are
intended for measurement of propagation delays associated with 12L gates. Each of these oscillators are
made up of a cascade of 8 four·output 12L gates. Figure
7(a) shows the basic electrical equivalent circuit of a
four-output 12L gate. Its corresponding logic symbol is
shown in Figure 7(b). The basic gate operates as an inverter with single input and four outputs.
Figure 5. Recommended External Connections to Measure
Output Waveforms.
3-85
AN·17
(PIN 4)
INJECTOR
(PINS)
,}
OSCillATOR
n-~-o OUTPUT
2
OUTPUTS
:
INPUTS
ILl"
1
~! }
EQUIVALENT CIRCUIT
OUTPUTS
LOGIC SYMBOL
Ring Oscillator Using Single Gate Output per Stage
(Section 3)
Figure 7. Four-Output 12l Gate
The propagation delay through an 12L gate depends on
the following sets of parameters:
(PIN 9)
1. Device design: (Le., manufacturing methods and
device layout used in fabrication process).
(PIN 10)
OSCILLATOR
n-~~ OUTPUT
2. Injector current level: (gate switching speed in·
creases with increasing current, until a maximum
is reached).
PIN 8
Ibl
3. Choice of outputs used: (the output closest to the
injector has minimum propagation delay at high
currents).
Ring Oscillator Using Two Gate-Outputs per Stage
(Section 5)
4. Number of outputs used: (if fewer outputs are
used and the unused outputs left open, the gate
delay is Lower at low currents. However, at high
currents, i.e., Ij ~100I'Algate, gates with fewer
outputs left unused show lower delays. This is due
to excess storage-time effects due to opencircuited gate outputs. See Figure 10.)
(PIN 6)
INJECTOR
~----
Figure 8 shows the basic seven-stage ring-oscillator circuits included on the XR-C409 chip to evaluate the
propagation delay characteristics of 12L gates. Since
the delay characteristics depend on the choice and the
number of gate outputs used, the test IC includes three
separate ring oscillator sections. The ring oscillator of
Figure 8(a) corresponds to section (3) in the package diagram of XR-C409 shown in Figure 1. This oscillator uses only one gate-output per gate. The output used is the
one closest to the injector, with the remaining outputs
left open-circuited.
PIN 8
1,1
Ring Oscillator Using Four Gate-Outputs per Stage
(Section 4)
Figure 8. Equivalent CircuHs of the 7-Stage Ring Oscillator
Section.
The ring-oscillator of Figure 8(b) uses two gate outputs
per stage. The outputs used are the two closest to the
injector. The ring oscillator of Figure 8(c) has all four
outputs shorted together.
r
All three oscillator sections of XR-C409 have separate
injectors, but share a common ground (pin 8). Each oscillator also has a separate output buffer stage.
~
8
v+
INJECTOR
(PINS 4, 6'rO_R_91""",,_..
RL
IL
t
OSCILLATOR
OUTPUT
JlJl
Figure 9 shows a recommended test circuit for evaluating gate delay vs. gate current characteristics using the
ring oscillator sections of XR-C409. Since each ringoscillator section is comprised of 8 gates, the actual injector current per gate, Ij, is 1/8 of the total injector current, 1,-;:
Ij = injector current/gate =
(PIN 7\
n-~--<> g~~lp\;~TOr,
01 = LOW CAPACITANCE
CLAMP DIODE
Figure 9, Recommended Test Circuit for Evaluating PowerDelay Characteristics of 12l Gates Using Ring
Oscillator Sections of XR-C409.
(5)
3-86
AN·17
The total injector current, IT, is determined by the external bias resistor, RBm as given by equation (1).
where N is the number of stages in the ring oscillator.
Measuring Output Waveforms
For the case of the 7-stage oscillator circuits in the XRC409 test chip, Td can be calculated from equation (8)
by setting N = 7.
The output terminals of XR-C409 ring counter sections
are open-collector type terminals, similar to the outputs
of the frequency divider sections. Thus, the outputs require pull-up resistors to the positive supply voltage.
The output rise-time is strongly affected by the external
RC time constant due to the load resistance, RL, and
the parasitic load capacitance, CL. In the test circuit of
Figure 9, a low-capacitance clamp diode, D1 is used to
limit the output swing and thus minimize the slow rise. time effects.
Figure 10 shows the typical gate-delay vs. injector current characteristics measured from the three ringoscillator sections of XR-C409. In the figure, the gate
delay is plotted as a function of the injector current per
gate. The gate geometry layout of XR-C409 ringoscillator sections is not optimized for high frequency
operation.
'~'r--------'--------r-------~------'
The minimum value of load resistance, RL, is determined by the current sinking capability of the output 12L
gate. For proper operation of the ring-oscillator circuits,
the load current, IL' should be limited to:
IL
IT
s4
'" 1----~~o------+----+_---__1
500
(6)
200
which limits the output load resistance, RL, for ringoscillator sections to:
l00"II------+-----~~~--+_---~
50
(7)
2.
Calculating Propagation Delays
10"5.'~"A.,.-J'----'~':-""A::---'---~::'~~A:-'----J..--;;'.:;-."-:;A--'---~~'mA
The average propagation delay Td per gate can be calculated from the ring oscillator frequency,. fo as:
1
Td = --sec
2Nfo
SECTION 4
(4 OUTPUTS/GATE)
INJECTOFI CURRENT PER GATE, Ij
Figure 10_ Typical Propagation Delay vs_ Injector Current
Characteristics as Measured from 7-Stage Ring
Oscillator Section of XR-C409_
(8)
3-87
AN·18
Designing Wide-Tracking
Phase-Locked Loop Systems
INTRODUCTION
The actual driving voltage for the VCO is now a voltage
proportional to fi which can be varied a fixed percentage by the phase detector.
Phase locked-loops with their excellent frequency
tracking characteristics have found their way into many
applications where synchronizing or synthesizing of signals is required. Although they do have the ability to
track an incoming signal very well, the actual tracking
range is quite limited by the nature of PLL:s to less than
2:1. This range of less than 2:1 must be observed if harmonic locking, a plague to the designer, is to be avoided.
CIRCUIT DESIGN
The heart of the circuit is the XR-2212 Precision PhaseLocked Loop. Figure 2 shows the XR-2212's internal
blocks and necessary external components. The VCO
in the XR-2212 is actually a current controlled oscillator.
Pin 12 is fixed at the reference voltage, Vr
V2+ , and
This application note describes the design of tracking
PLL with a tracking range of greater than 100:1, with
no harmonic locking problems. This design uses the
XR-2212 Precision Phase-Locked Loop in conjunction
with the XR-320 Monolithic Timer and an XR-084 Quad
BiFet Operational Amplifier to form a wide range PLL
with automatic tuning.
=
the current drawn from this terminal controls the frequency of oscillation of the VCO, fa. With RO grounded,
as shown, the VCO's free running or center frequency
is:
fa = _1_
ROCO
PRINCIPLES OF OPERATION
Figure 1 shows the block diagram of the tracking PLL.
The circuit is comprised of three blocks: the PLL, the
Frequency to Voltage Converter, and Precision Clamping Circuit. The blocks operate as follows. The PLL
locks onto the incoming frequency and produces an
output frequency identical to that of the input, but
phase shifted. The center of the lock range is controlled
by V1. V1 is derived from the FN converter, which produces a voltage proportional to the incoming frequency.
This voltage, V1, thus provides an automatic PLL center
frequency tuning signal. The swing of the phase detectors filtered voltage, V2, controls the amount the VCO
can be moved about its center frequency. The precision
clamp fixes the swing on V2 to a fixed percentage of V1,
keeping the tracking range of the PLL constant as its
center frequency is varied.
RO and Co are calculated using this relationship at fa
maximum. Wi.th the PLL locked on its center frequency,
the phase detector's dc output, Pin 10, is also at Vrand
the current flowing in RO is proportional to fa. If the bottom end of RO is now raised above ground, the current
in RO will change linearily with the voltage, as will fa
thus providing the voltage control input for the VCO. If
RO is left at zero volts and fi is moved, the dc voltage at
Pin 10 will inversely follow fi, increasing fi decreases
the voltage at Pin 10, modulating the current from Pin
10 and thus fO. The maximum swing of Pin 10 is ± Vr,
giving the following relationship:
=
±Vr
± ~ =
fO
R1
Vr
= RO ± (VrRO) = ± RO
R1
VrR1
RO
tlO--_-~·1
&f being the PLL:s tracking range.
INCOMING
SIGNAL
100--+--4--+-----<"1
OUTPUT
VI
Figure 2. XR-2212 Internal Blocks
with External Components.
Figure 1. Tracking PLL Block Diagram.
3-88
R1
AN·18
In our application a constant ~ is desired, so if the out-
WIDE RANGE SYNTHESIZER USING RR·2212 PLL
put of the phase detector, Pin 10, is clamped to - VRO,
the voltage across RO, a constant tracking range will be
maintained. C1 serves as the loop, low pass filter, and is
This same technique of automatic tuning can be used
to form a wide range synthesizer as shown in the block
diagram of Figure 5. Here a programmable frequency
divider has been put into the loop between the VCO output and the phase detector input. Since the PLL will
drive the VCO until its two inputs are at the same frequency, the VCO will be at:
made to equal
~o for a damping of V..
The voltage driving RO comes from the FIV converter
which is formed by the XR-320 Monolithic Timer. The internal blocks and external components of the XR-320
are shown in Figure 3. The input to the FIV is brought to
the trigger input, Pin 6, which, when driven above the
threshold, triggers the F/F and opens the internal
switch transistor, S1. The voltage on CT will Iinearily
rise, at a rate set by AT until Vr is reached at which time
the comparator resets the F/F and closes S1, waiting
now for the next rising edge on Pin 6. Once triggered
the output, Pin 12, will go low for the timing period defined by the relationship:
fVCO = Nf r
where N in the binary number applied to the programmable divider
(N
;2:
1)
The FN converter used in the previous application to
drive RO, or tune the PLL, is now replaced with a digitalto-analog converter, DAC. Its digital inputs come from
the same lines which control N. The DAC's output voltage, which drives RO, will now vary proportionally with
N, or retuning the PLL with each new N. The same
clamping network is used on the phase detectors output as discussed earlier.
Since Pin 12 will now have a constant low time and a
repetition rate equal to that of the incoming Signal, fi, it
can be filtered to provide a voltage proportional to fi.
Figure 4 shows the complete tracking PLL circuit. The
precision clamp is formed by A1-A3 which samples the
voltage across RO and clamps the XR-2212's phase detectors output to ± VRO. With the given values, the
tracking range of the circuit is one kHz to 100 kHz, with
the XR-2212's tracking range set at approximately ±
0.33 fO. The input frequency voltage range is 10 mV
RMS to 3 V RMS with the output producing a 10 V P-P
square wave. Calibration is done by first applying 100
kHz to the input and adjusting P1 for fO equal to fi in frequency but shifted in phase by approximately 90·, then
with fi = 1 kHz P2 is adjusted again for equal frequencies with 90· of phase shift.
INPUT FROM II
HIGH CURRENT
...r
OUTPUT
12
LOGIC
aUT
Figure 3. XR·320 Internal Blocks with
External Components.
XR-2212
.,2 vo--------..-----------.:l--Jl
wo--------r------4-4~-l-~~~~-~--~
10K
S.IK
R-r v·
L--------~TA a~·r_-~~-~~~------~~------------~
(12)
c,-
GND
A,-A 3 =>XR-D84
P, = >FULL SCALE ADJUST
P2= >ZERO ADJUST
Figure 4. Wide Range Tracking PLL.
3-89
AN·18
put voltage range is 10 mV RMS to 3 V RMS with the
output providing a T2L compatible square wave.
Figure 6 shows the complete wide range synthesizer
circuit. The two 4-bit binary counters, 74161, and magnitude comparator, 8130, form the programmable divider. The output of the divider is a variable duty cycle
pulse so that the flip-flop, 7474, was added so that
phase detector was always presented with a square
wave. Since the flip-flop also divides by two, the minimum value for the divider will be 2 or the actual N of the
overall divider will be the binary input times two, 2N.
The DAC uses the reference voltage of the XR-2212 as
its reference with amplifier ~ used to scale the voltage
to RO correctly. C1 provides loop compensation and its
value will determine not only the response of the circuit
but the short term frequency stability of fO. A trade off
must be made here as decreasing C1 will provide for a
faster responding loop but decrease the short term stability of fO. It is probably most desirable to have a highly
stable output frequency and slower responding loop,
which the values in Figure 6 provide for.
'.D---t-oot
FROM Y REF
OF Xft..2212
With the values shown, fo will be one kHz to 100 kHz
with fref = 500 Hz and N = 1 to 100. The reference in-
Figure 5. Wide Range Synthesizer Block Diagram.
XA-2212
,.oK
24K
. . 12v o - - - - - - - - - - - - - - -....---+---+-'-I
'.EF O - - - - - - - - - - - - - - - - - - - - I t - - t - - - - R
wo-----1---+-----.--------.
'5V~-n===E~~:tl:l
<>----;t,
o.Gll AL GND
ANALOGGND~
75011
Al - A4 = > XR-084
P, = > FUll SCALE ADJUST
Pz = >ZEROADJUST
fo=2Nl re I1:s;N:s10D
tret
'OK
LSB
5,K
MSB
-12vo-------.....--IV
B3 8 4 85 86 87 B8
~
YlC
io
-
V REF- VREF+ 10
+12\/
20K
20K
Figure 6. Wide Range Synthesizer.
3-90
= 500HZ
AN·18
Typical input and output waveforms for rref = 500 Hz.
top trace. and fo • bottom trace. with N switching from
40 to 8 are shown in Figure 7.
Calibration is done by first adjusting P1 for a 100 kHz
output with N = 100 and then adjusting P2 for a one
kHz output with N = 1.
Figure 7. Typical Input and Dutput Waveform.
3-91
AN·19
Clock Recovery System
INTRODUCTION
Recovering encoded serial data from floppy disk systems poses a major design problem as the synchronized clock used to encode data is embedded within
the data stream. The clock cannot be readily extracted
using common phase-locked loop techniques as the actual clock may appear for only short periods of time in a
common encoding format such as NRZI. This clock is
necessary to decode the serial data and retrieve the
original data.
Figure 2 shows the block diagram of the clock recovery
system. The XR-320 forms a bi-directional one-shot. It
will produce a positive output pulse for both rising and
falling edges on its input. The period of these output
pulses is set equal to one half the total period of clock.
This is used to provide a frequency component in the
data stream equal to the clock even under worst case
data conditions of five ones, zero, five ones, zero. (Seen
in Figure 1.) This can also be seen to double the frequency of the data stream which is desirable as the
PLL will now be able to lock to the original clock. The
XR-2212 forms the PLL which, when the actual clock
appears in the data stream, locks to and produces a
frequency at its veo output equal to and synchronized
with the clock. The PLt:s phase detector output is connected to the input of a sample and hold (StH) as well
as the StH's output through a switch. This switch is held
open by the 74123 as long as the clock appears in the
data stream. Whenever a one is present the clock will
not appear in the data stream and the 74123 places the
sample and hold in the hold mode and closes the
switch. This holds the voltage at the phase detector and
keeps the proper driving voltage to the veo, thus maintaining the frequency at the output of the veo equal to
and synchronized with the clock.
This application note describes the design of a PLL
(phase-locked loop) system which can be used to recover the clock from a serial data stream using NRZI
proto"col with very excellent stability. The design utilizes
the XR-2212 Precision Phase-Locked Loop in conjunction with the XR-320 Monolithic Timer to form the heart
of the system. The system also uses a 74123 Dual OneShot and 398t13333 for timing and sample and hold
purposes.
PRINCIPLES OF OPERATION
Figure 1 shows a data stream and clock using a typical
NRZI protocol. In this protocol changes in levels represents a binary zero, while no transitions a binary one.
From the figure it can be seen that the data stream can
have a maximum rate of change corresponding to a frequency equal to one half the clock frequency with the
actual data being a string of zeros. This format guarantees that there will be no more than five ones in a row.
The slowest rate of change will then be a frequency
corresponding to one twelfth the clock.
ACTUAl. DATA
0
0
0
0
1
1
1
1
1
0
1
1
1
1
1
0
0
0
DUAL ONE-SHOT
1
NRZI
ENCODED
DATA STREAM
CLOCK
"
T,
Figure 2. Clock Regenerator Block Diagram.
I i~ I
H RETRIGGERED BEFORE
When the clock reappears in the data stream the 74121
drives the switch open and 8tH to the sample mode
with the PLL once again tracking the clock in the data
stream. The length of T1 is made equal to slightly less
than the period of the clock so that the 8tH is always
ready in the event the clock is not in the data stream
and any sample to hold glitches will not be transmitted
to the phase detector's output. The length of T2 is made
slightly longer than the clock period which will cause
the switch to close immediately after one clock pulse is
missed. With a clock period T, these times, T1 and T2,
are set equal to 0.8 T and 1.2 T, respectively.
n ...__---'r---i
1.2T IT TIMED OUT
V,
10
REGENQRATED
CLOCK
Figure 1. System Timing Diagram.
3-92
AN·19
CIRCUIT DESIGN
..
'0 AND "
The heart of the circuit is the XR-2212 Precision PhaseLocked Loop. Figure 3 shows the XR-2212's internal
blocks and necessary external components. The phase
detector output is a high impedance current source output so it can be forced or held at a particular voltage
easily, as by the S/H. The PLL:s center frequency is
equal to:
,
I
I
Figura 4. PLL In/Out Phasa Ralatlonshlps.
The XR-320 Monolithic Timer used for the bi-directional
one-shot is shown in block form with its external components in Figure 5. The control flip-flop can be triggered by either positive or negative edges on its inputs,
which are tied together for this application to provide bidirectional triggering. Once triggered, the output will
provide a low level signal for a period defined by:
RO and Co are calculated using the data stream's clock
frequency set equal to fo . The tracking range of PLL is
given by the following relationship:
~f
V' 2
I
ROCO
Rl
fo Rl
V'
r--
1
fo = - -
~f =
V,
PHASE SHIFT
BETWEEN
=> tracking range
how
= 2 RrCT
These components are calculated with TLOW set equal
to one half the clock period.
c.
"/
--'1~
Figura 3. XR-2212 Intarnal Blocks with Extarnal
Componants.
, -=
V'le--- -------'.K
The phase relationship between the incoming signal, fi'
and the output signal, fo, will be 90· if fi is equal to fo
and will vary up 90· or down 90· from this nominal if fi
is at either end of the tracking range. The voltage at the
output of the phase detector will also vary linearly with
these phase relationships. These relationships are
shown in Figure 4. The tracking range is made very
large since a constant phase relationship between the
recovered clock is desirable. Therefore, any errors in
the S/H or drops through the switch will not significantly
alter this phase relationship. ~f is made equal to approximately 0.8 fo, and Rl is calculated accordingly. Cl
is used to remove the double frequency component
from the phase detectors output and also in conjunction with Co controls the PLL transient response characteristics, a'ccording to the following relationship:
lOGIC
OUTPUT
Figura 5. XR-320 Intarnal Blocks with Extarnal Componants.
Table 1 summarizes the previously described formulas
as well as those for the 74121 Dual One-Shot.
Tabla 1
FOR XR-2212
FOR XR-320
FOR 74123
(1) RoCo ~ _1_
fCLK
(2) Rl
~
1.2 Ro
Co
(3)Cl ~"4
for a loop damping of V2, Cl =
10
~o
0.8 fCLK In 2
(6) REX2CEX2 ~
1.2 fCLK In 2
3-93
AN·19
*
+5VO~------------------~~~------------~----------
IN91~
'O·,......_X_R,_3'_0......, '4
DATA sT;A-M--------------I-+----I,°~pr
PLUS CLOCK
T
I
5 ""'--
1:
RT
,..
+a-
OUT
GND
CT
~
' -_ _......
Rex,
'4K
15'
=~
lO~~ t-:3:=-------.--~---"°'i TR,
'0'
"2 s: ~
I"
Vee
V' - ; -
• .r
_ _
~~~----~-----,
74123 ,. 13
l00pF
IN914
__
CT
100pF
I,
~'eEX'
Q,
GND
8
.!...-'OOOpF
rr
GNDo-------------------~~~------------~----1_------~-.~----~------------~--------,
[1,~
• "V o-------------~--t__----------------,-___I--------------------<~+------------+._____,
XR-2212
r
10
,
~~
510pF
-+. ~~
o----------------.~~__'__l
DEl
~~~.,,~
'0
I--+'-'---~--__<~W'\r_~__'__l
REGENERA TED
..
,
CLOCK
5
,e,
rSD
12
v
5
H
GNrr:
V~
0
~
7
15
5K
10
~~
14
:-
'~~A-I--"--<
O.Ol.,F
v-
Ro
:,p,
-12Vo-----------------------------------------------------~~--------------~
P, :::. ~~ ADJUST SO POSITIVE PORTION OF Ii IS EQUAL TO 12 OF THE CLOCK PERIOD
P2 :::. :-- ADJUST FOR 90 PHASE SHIFT BETWEEN f1 and fo WITH ,. :::. 'elK
Figure 6. Complete Clock Regenerator.
Figure 6 shows the complete clock recovery circuit
with values designed for a clock of 122 kHZ. The input
to the system will accept input low levels from 0 V to
0.5 V levels and high levels from 1.5 V to 5 V. The output
provides a 10 V pop square-wave. Calibration is accomplished by adjusting P1 for the output of the XR-320 to
equal exactly one half of the clock period and P2 for a
90 0 phase shift between fi and fa with a constant string
of zeros applied at fi.
The oscilloscope photograph in Figure 7 shows the system waveforms with the input data stream on top and fa
on the bottom.
The same circuit can be used to regenerate or clean up
a clock with occasional miSSing cycles by applying it to
the paint labeled fi and eliminating the XR-320 from the
circuit.
Figure 7. System Waveforms.
3-94
LF 13333
V.6....-
5
8.2K
12
V.
MYLAR
13 y~J '4
Co 820pF
R,
VIN
169
LOGIC
THRESH
4
AN·20
Building a Complete FSK Modem Using
XR·2211 and XR·2206
INTRODUCTION
GENERAL DESCRIPTION
phone line, while it will decode to "1 's" and "O's" 2025
Hz and 2225 Hz received from the line. The originate
modem simply reverses the frequencies for send and
receive. The sinewave modulator will produce two discrete frequencies at its output corresponding to a "1"
or a "0" at its data input. The line hybrid will steer these
frequencies to the phone line while causing received
frequencies to go to the bandpass filter and demodulator. This block will therefore provide isolation between
modulator and demodulator at each end. The bandpass
filter is used to remove unwanted signals and noise received from the phone line before they reach the
demodulator.
Figure 1 shows the block diagram of an FSK system.
The complete system is comprised of an answer and
originate modem. The answer modem will convert input
data to either 1070 Hz or 1270 Hz and send it to the
The PLL demodulator will lock onto incoming frequencies at its input and produce" 1's" or "O's" at its output.
The carrier detect output will produce a low, "0" signal
out when valid data is being received.
With the number of digital systems and equipment
growing so rapidly, the need for a method of moving data has also become a fast growing field. This application note describes the construction of a modem system using frequency shift keying, FSK, for serial data
transmission. The system utilizes the XR-2206 as a
modulator, the XR-2211 as a demodulator, and an
XR-084 op amp as a bandpass filter. These three IC's
make up a complete working 300 baud, full duplex, FSK
modem.
ANSWER MODEM
ORIGINATE MODEM
PHONE LINE
Figure 1. Block Diagram of FSK Modem System.
OPERATION AND CALIBRATION
number of bits per second which can be sent and received. The answer can be used to drive the originate
and vice-versa. R19 is then adjusted for a square-wave
on the data received output.
The circuit has been designed for + 12 volt operation.
The data inputs accept TIL compatible signal levels,
while the outputs provide OV to + 12V signal levels.
Calibration is done by first adjusting the modulator. With
a low signal on its input, R21 is adjusted for 1270 Hz or
2225 Hz for originate and answer respectively. Then
with a high signal in, R22 is adjusted for 1070 Hz or
2025.
R20 is used to set the modulator output level. With the
modulator output set at - 6 dBm, the system will operate with an input signal range of + 10 dBm to - 48
dBm.
CIRCUIT CONSTRUCTION
The demodulator is easiest adjusted by feeding into the
modem input an alternating 1070 Hz/1270 Hz or 2025
Hz/2225 Hz signal in a square-wave fashion. The modulating frequency should be 150 Hz, which is one-half
the system baud rate of 300. The baud rate refers to the
Figures 2 and 3 show the circuit schematic and component layout. One PC board is used for answer or originate and should use the appropriate components as
listed in Table 1.
3-95
AN·20
~--~--~----'--4r-~---------------------------"--~~·-oV.
A13
CARRIER
OETECT
A12
DATA
e12
RECEIVED
le2
A1
A14
A15
e15
~~~+-+-~~-------t----------~~~---t---+~--~~~GND
A2.
A27
e17
~~~~--------1-~
le3
PHo~l
lI~
A21
A24
Figura 2. Completa FSK Modam Using XR·2211 and XR·2206.
PHONE
LINE
Figura 3. XR Modam foil Sida Shown (Not to Scala).
3-96
A25
AN·20
Table 1. Modem Parts List
IC1A·D
IC2
IC3
Rl *
R2*
R3*
R4*
R5*
R6*
R7*
R8*
R9*
Rl0
Rll
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
Cl,C6*
C7
C8
C9
ClO
Cll
C12
C13
C14
C15
C16
C17
XR·084
XR·2211
XR·2206
ANSWER
ORIGINATE
40.2K
499
270K
60.4K
680
383K
24.9K
1.21K
160K
lK
lK
5.1K
5.1K
510K
510K
lOOK
47K
7.5K
2K
50K
2K
2K
3.9K
3.6K
200
1M
1M
0.01
0.1
22
0.01
0.1
0.022
0.1
1
0.1
0.1
1
1
47.5K
191
357K
39.4K
160
270K
20K
360
160K
lK
lK
5.1K
5.1K
510K
510K
lOOK
lOOK
9.1K
2K
50K
2K
2K
8.2K
6.8K
200
1M
1M
0.01
0.1
22
0.01
0.1
0.01
0.047
1
0.1
0.1
1
1
All resistors are 1/4 watt - 5% tolerance. except as
marked with (*) which are 1 % tolerance. Values given
in (0).
All capacitors are 5 % tolerance. except as marked with
(*) which are 1 % tolerance. Values given in "F.
3·97
AN·21
Precision Narrow-Band Tone Detector
INTROOUCTION
PRINCIPLES OF OPERATION
The Phase-Locked Loop (PLL) is a very versatile building block with a wide range of applications in signal processing and communication systems. As a tone detector or tone discriminator, the PLL is accurate and stable
enough for most applications not requiring very narrow
bandwidths. The smallest, practical detection band is
limited by the temperature stability of the PLL center
frequency and accuracies of external components. For
example, designing a tone detector using a single PLL
to discriminate a 10Hz tone out of 100 kHz can present
great difficulty. A PLL with center frequency of 100·kHz
can drift by 2 Hz/oe given a typical center frequency
drift of 20 ppm/oe. A slight change in ambient temperature can cause the PLL to unlock. On the other hand,
there are various applications involving pressure transducers and crystal oscillators that require a very stable
system capable of detecting a small change in frequency over a wide frequency spectrum.
Figure 1 shows the block diagram of the narrow-band
tone detector using the XR-2208 and XR-2213. The
XR-2208 is being operated as a balanced modulator or
frequency mixer. It "mixes" the input frequency, fiN,
with a stable frequency source, fe, to produce the sum
and difference frequencies of fiN and fe. The low pass
filter removes the higher frequency component (fiN +
fe) and passes the difference frequency to the XR-2213
PLL. The input signal is "mixed-down" in frequency in
this manner, allowing the PLL center frequency, fo, to
be set at a much lower frequency than the input signal.
With a lower fo, the PLL drift (Hz/°C) becomes less,
making the tone Jetector less susceptible to ambient
temperature changes.
The input signal to the XR-2208 is a periodic waveform
with frequency of:
fiN ± .AfiN
This application note describes the use of the XR-2213
PLL in conjunction with the XR-2208 analog multiplier
as a frequency mixer. It is capable of detecting a 1 Hz
tone out of a frequency spectrum greater than 1 MHz. It
can accept almost any periodic waveform including
sine, square, and triangular waves. Error due to temperature drift is typically 0.2 %Ioe. The tone detector output changes to a high state when the input is within the
detection band.
where .AfiN is the detection range. The range of frequencies for detection is between fiN - .AfiN and fiN
+ .AfIN. It is necessary to band-limit the input frequency for proper operation of the tone detector. Since the
XR-2208 takes the "absolute" difference in frequency
between fiN and fe, it is possible to obtain the same
output frequency with different values for fiN, causing
the tone detector to lock onto the "wrong" frequencies.
lIN
2213
r-- - - - - - - - - - ,I
te
fiN -
I
I
I
I
Ie
I
I
I
I
I
t-------t:>--r-oVOUT
L ___________
I rHI
.J
--.J LO
Figure 1. Functional Diagram of Narrow Band Tone Decoder.
3-98
AN·21
In order to band-limit the input frequencies, a low pass
filter with very sharp roll-off (6th order or higher) with
the corner frequency around fiN can be used. For high
frequency applications (fiN> 100 kHz), a bandpass
crystal filter can be used. Crystal filters have stable frequency characteristics and very high a's (a > 1000)
making very sharp bandpass filters. Crystal filters are
commercially available through various manufacturers.
Table 1. Tone Decoder Performance VS. AflN"o
±IlIIN
-10
0.1
0.5
1.0
5.0
10.0
20.0
The control frequency, fC, must come from a very stable and accurate source since any error in fC will directly affect the tone decoder. A crystal oscillator with a
"divide-by-N" counter as shown in Figure 2 can generate a very stable frequency, with temperature stability
in the range of 1 ppm/oC.
0.02
0.004
0.002
0.0004
0.0002
0.0001
fiN, Ilf'N fo in Hz.
The control frequency is given by:
fC = fiN
%
%
%
%
%
%
TYPICAL
PLL 10
STABILITY
(Hz/oC)
x
x
x
x
x
x
NORMALIZED
RELATIVE
ACQUISITION
TIME
MAXIMUM liN
ALLOWED (Hz)
0.1
0.5
1.0
5.0
10.0
20.0
Ilf'N
Ilf'N
Ilf'N
Ilf'N
Ilf'N
M,N
fiN
fiN
fiN
fiN
fiN
fiN
+ Ilf,N(1999)
+ Ilf'N(399)
+ Ilf'N(199)
+ Ilf'N(39)
+ Ilf'N(19)
+ Ilf'N(9)
fo ~ PLL center frequency
fiN ± Ilf'N ~ input frequency range
DESIGN EQUATIONS (All R's in ohms; all C's in farads)
+ fa
1. The XR-220S control frequency, fC, is given by:
where fa is the PLL center frequency in Hz. the Choice
of fa is arbitrary, however the larger fa is, the more the
PLL becomes susceptible to temperature variations but
the better the acquisition time or "pull-in" time becomes. One the other hand, if fa is small, then temperature variation has less effect but acquisition time becomes worse. Table 1 shows the relative performances
of the tone decoder with respect to the ratio of AfIN/fo.
fC = fiN
+ fa
2. The maximum input frequency allowed is:
I,N(max) ~ liN
+ 210 - AfC
Where ± AfC is the capture range 01 the PLL.
3. The capture range, ±AIC, is set as:
The output of the low pass filter is fed into the pre-amp
of the XR-2213 PLL. When this frequency falls within
the detection band or the PLL (fa ± AfC), the voltage
comparator goes to a high state and remains there until
the input frequency falls outside the detection band;
the output voltage then goes to a low state. when there
is no input signal applied to the XR-220S, the PLL output remains low.
±AIC = ±AI'N
Where ±AI'N is the input frequency variation.
4. The lock range, ± AIL, is set equal to ± AfC:
(Hz)
5. The loOp damping factor, 0, is set to 0.63:
Ie
0=.1
@Q
4",c.;
6. The PLL center frequency, fa, is given by:
R
fa = _1_ (Hz)
ROCO
7. Loop detect filter capacitor, Cd, is given by:
L - - - - - - t e,
AfC in Hz
RD is set to 470 kO.
Increasing Cd slows down the logic output response
time.
5 Mil - 10 Mil
20 pF
S. The low pass filter time constants, CF and RF
1 pG - 30 pF
C1 Pulls the crystal down (lower frequency)
RF CF
= .l
RF
fo
C2 Pulls the crystal up (higher frequency)
Where fa is the PLL center frequency.
Figure 2. Crystal Oscillator_
3-99
~
20 kO
AN·21
DESIGN EXAMPLE
5. ±afC = ±afL = ± 10 Hz
Consider the design of a narrow-band tone detector
with frequency detection range of 111.7 kHz ± 10Hz
(liN ± afIN)·
R1 = Rofo/alC = 100 KO
6. The damping factor is set to 0.63:
1. Choose the PLL center frequency to be 100 Hz.
C1
= Co (~y = 0.16"F
IC = 111.8 kHz
7. Loop detect filter constants:
fC can be produced by using a 3.58 MHz crystal (adjusted to 3.5776 MHz) and using a divide-by-32
counter in a crystal oscillator.
Choose RD
= 75 KO to prevent harmonic locking.
= 16/20 Hz = 0.8 "F
Cd
2. Maximum input frequency allowed is:
8. Low pass filter time constants, CF and RF
fIN(max) = 111,890 Hz
RF = 20 KO
3. Capture range, ±afC is:
CF = 1lfoRo = 0.5 "F
±afC = ±10 Hz
A circuit schematic for the above tone detector is
shown in Figure 3.
4. PLL center frequency is 100 Hz (fo):
Choose Ro = 10 KO (choice is arbitrarily set between 10 KO s Ro s 100 KO)
Co
=
1lfoRo
=
Typical acquisition time for this circuit is less than 100
msec.
1.0 "F
+10V
*O.,/,F
+lDV
*,o.tfl.
F
RO
SKO+5KOpot
Co
1.0 p.F (non-polar)
R1
100 KO
C1 =0.16p.F
RD = 75 KO
+••
~'I'F
CD = O.S p.F
RF = 20 KO
CF = 0.5 p.F
Figure 3. Circuit Schematic of Narrow Band Tone Decoder.
3-100
AN·22
XR·210/XR·215/XR·S200
Phase·Locked Loops
INTRODUCTION
produces a periodic Signal whose frequency is propor·
tional to the error voltage. The VCO is actually a "cur·
rent" controlled oscillator (ICO) in the sense that it is
the current derived from VOUT that actually controls
the frequency of oscillation.
This Application Note discusses the various parameters
and equations used in applying the XR·210, XR·215,
and XR·S200 Phase Lock Loop (PLL) successfully. It de·
scribes the operation of the phase detector and the
voltage controlled oscillator as well as a discussion on
phase comparator gain, VCO gain, lock range, capture
range and free running frequency. A section on low
pass filters contains most common RC filters and a dis·
cussion on damping factor. Finally, a summary of PLL
parameters and a design example are included.
PHASE
COMPARATOR
VOUT
lOW PASS
FIL TEA
XR-210
The functional diagram of the XR·210 Phase Locked
Loop (PLL) is shown in Figure 1. The phase comparator
produces a dc voltage which is directly proportional to
the phase difference between the two input signals.
This error voltage, VOUT, is then filtered and applied to
the voltage controlled oscillator (VCO), which in turn
fo
Figure 1. Phase Locked Loop Functional Diagram.
V+o-----------~----------~--------------------------_,
3.2 KI!
6 KII
6 K!!
1Your
040
1 mA
1 mA
BIAS
Figure 2. XR-210/XR-215 Phase Comparator.
3·101
AN·22
PHASE COMPARATOR
VIN (4)
The circuit diagram of the XR-2tO phase comparator is
shown in Figure 2. The input pins (4 and 6) and the bias
pin (5) are externally biased to approximately V2 V + to
insure proper operation. The input signals must be capacitively coupled to Pins 4 and 6.
The output voltage on Pins 2 and 3, VOUT, depends on
the relative phase, ef>, of the iput signals. The change of
VOUT with respect to the change in ef> is defined as the
phase comparator conversion gain and is given by:
Kef>
=
.:l VOUT VOLTS
.:lef> RADIAN
YOUT
Figure 3a. 90° Out of Phase.
(1)
+V
VIN (4)
To examine how VOUT changes with ef>, consider the following three cases. It is assumed that the input voltage
is large enough (> 50 mVRMS) to cause limiting in the
differential stage. All calculations are done at V + = t 2
volts.
-Y
VIN(6)
Case 1: Input voltages are equal to the bias voltage.
VOUT
The operating current is shared equally between transistors 022, 028, 039, and 040. This causes approximately 0.5 mA to flow through the output resistor (6 KO)
and hence VOUT = 0 volts. The voltage on Pin 2 and
Pin 3 is approximately equal to:
V+
-
Figure 3b. 45° Out of Phase.
PHASE
DIFFERENCE
(,1»
OUTPUT
VOLTAGE
(VOUT)
(0.5 mAl (6KO) = 9 volts.
Case 2: Input voltages are both greater than the bias.
022 and 040 conduct 1 mA each, causing 038 to conduct 1 mA. Therefore V2 == 6 volts, V3 == 12 volts and
hence VOUT == -6 volts.
+6 V
180
OV
90
The same output conditions are obtained if the input
voltages were both less than the bias.
-6 V
Case 3. Input voltages are out of phase and VIN (Pin 6)
Figure 4a. Phase Detector WHh No Saturation.
is greater than the bias.
022 and 039 conduct 1 mA each, causing 035 to conduct 1 mAo Therefore, V3 == 6 volts, V2 == 12 volts and
hence VOUT == +6 volts.
VOLTAGE
PHASE
DIFFERENCE
(VOUT)
(0:.)
OUTPUT
The same output conditions are obtained if VIN (Pin 4)
were greater than the bias.
•
T 180
I
Figure 3 shows the output voltage wave form when the
input signals are 90° and 45° out of phase.
+1.7 V
Notice that the duty cycle of the output waveform
changes as the phase difference of the input signals
change. For illustration purposes, square waves are
shown as input signals, however, other periodic waveforms would produce similar output waveforms.
-1.7 V
OV
------~- ------~~~~~± ':
--------,t
)
I
10
~
Figure 4b. Phase Detector WHh Saturation.
3-102
AN·22
The output of the phase detector is connected to a low
pass filter which converts the square wave output to an
approximate dc voltage. The relationship of this dc voltage, VOUT, with respect to the input phase difference,
, is shown graphically in Figure 4a. Assuming no saturation occurs in the internal circuitry, a PLL can lock onto an input signal with maximum difference of 180° to
0° with respect to the veo signal.
It is possible to obtain a tracking range close to 90° ±
90° by connecting an external resistor network to the
phase detector output as shown in Figure 5. This circuitry limits the output swing to 10 ± 1 volt and prevents the internal circuitry from saturating at extreme
phase conditions.
The phase comparator gain for the XR-210 is approxi·
mately given by:
Due to internal saturation of the output, the maximum
phase difference the XR-210 can track is approximately
50° or 90° ± 25°. This is because the output transistors
of the phase detector saturate at approximately 8.3
volts and the maximum output voltage, VOUr. obtainable is about ± 1.7 volts. Figure 4b shows the phase
detector characteristic of the XR-210.
K :; 4.0 VOLTS
RADIAN
With the external bias network, it is approximately:
VOLTS
RADIAN
K :;
r----------,
I
142
I
n
I
I
I
I
0,
(2)
0,
~TE;;;A~
-
-
BIAS
-
"I" i
-1.- - -.".--J
ROUT = 2.0 KG
Figure 5. External Resistor Bias Network.
VOUT--~
Co
RT
Figure 6. XR·210 Current Controlled Oscillator.
3·103
(3)
AN·22
CURRENT CONTROLLED OSCILLATOR (ICO)
The change in timing current with RT is given by:
The functional diagram of the ICO is shown in Figure 6.
The output frequency, fo, is directly proportional to the
total timing current, IT, seen by the ICO.
.1 IT e 0.17 rnA
RT
(11)
The free running frequency can now be given by:
(4)
fo e 200 (1
Co
Any change in output voltage of the phase comparator
causes a change in fo as follows:
+
0.17 HZ)
(12)
AT
where RT is in KIl and Co is in p.F.
Af
.1 VOUT
"oct---
(5)
The ICO gain is now:
RO
where RO is the external resistor between Pins 11 and
12. It will be shown in the following section how RO sets
the lock range of the PLL.
KO=~
.1 VOUT
Combining equations 4 and 5 yields:
~=~
.1 VOUT
e
211' (200 1
Co
+
0.17)
AT
-~-=--:---~
RO IT
(13)
RO IT
However, the timing current is now:
(6)
IT e (IX
RO IT
where IT is the total timing current with VOUT = 0 volt.
In this case, IT = IX e 1 rnA. Substituting this into
equation 6 yields the ICO conversion gain:
KO = ~ e 211' fo RADIANS/SEC
.1 VOUT
RO
VOLT
211' fo
= --
+
°R~)
rnA = (1
+
°R~)
rnA
(14)
Substituting this into the ICO equation yields:
KO e 200(211') = 1256 RADIANS/SEC
Co RO
RO Co
VOLT
(7)
(15)
and remains unchanged with the addition of RT-
where RO is in KIl.
Note: The discrepancy between the calculated and
measured KO can be attributed to tolerances of
internal resistors and errors in approximating IX.
The minimum value of RO should be approximately
1.7 KIl. This is because the maximum current through
RO must be limited to 1 rnA and since VOUT has a maximum range of approximately ± 1.7 volts, RO must be
limited to greater than 1.7 KIl.
LOCK RANGE
The lock range of a PLL, ± .:lOlL, is given by:
The free running frequency of the PLL is given by:
F
fo e -200C"
0 IS In p..
Co
±.1ol = (K := 3.6 VOLTS
RADIAN
(18)
Ll.f
Saturation of the internal circuitry occurs limiting the
tracking range of the phase detector to about 90° +
25°.
-
LI. IT := 0. 7
RX
(23)
The ICO free running frequency is given by:
fo := 220
Co
An external resistor network shown in Figure 5 can increase the range to about 90° ± 90°. The correspondIng conversion gain becomes:
K := 1.3 VOLTS
RADIAN
Ci
(1 +
(24)
0.7)
RX
where RX is in Kg and Co is in /-IF.
KO:= 1140 RADIANS/SEC
RO Co
VOLT
(19)
(25)
ICO
and remains unchanged with the addition 01 RX.
The current controlled oscillator 01 the XR-215 is shown
in Figure 7. The ICO conversion gain is given by:
LOCK RANGE
The lock range 01 the XR-215, ± Ll.wL. is given by:
KO = 2'1r fo RADIANS/SEC
RO IX
VOLT
(20)
± Ll.wL = (K and KO yields:
Since IX = 1.1 mA and 10 = 220 ,
Co
KO:= 1256 RADIANS/SEC
RO Co
VOLT
± Ll.wL == 1765 RADIANS
(21)
RO Co
(27)
SEC
where RO is in Kg and Co is in /-IF.
where RO is in Kg and Co is in /-IF.
Note: Using the external bias network (Figure 5) does
not change KO' To calculate the lock range with
this network, eE should be set to approximately
'1r/2 radians (90°).
Experimental data yields:
KO:= 1140 RADIANS/SEC
RO Co
VOLT
(26)
(22)
I----VOUT
to.
Co
-1
Figure 7. XR·215 ICO.
3-105
1 mA
AN·22
With Pins 15 and 16 open, fo is given by:
XR-S200
The XR-S200 PLL is basically the same as the XR-21 0
and 215 except that many of the interconnections are
made external to the chip. These external connections
can aid In the flexibility of the chip.
since IX == 1 mA, 11 == 0.5 mA, 12 == 1 mAo
PHASE COMPARATOR
With Pins 15 and 16 tied high, fo is given by:
fo == 200 (IX + 11 + 12) = 500 Hz
Co
Co
The phase comparator outputs are not tied internally to
the ICO as the XR-210 and 215. The measured phase
comparator gain is approximately:
fo == 200 (IX) = 200 Hz
Co
Co
(30)
(31)
where Co is in "F.
K and KO yields:
± aWL;;; 2170 RADIANS
RO Co
SEC
<':
(37)
20
/
"
a.
a.
'z"
;;
::E
where RO is in KIl, and Co is in /LF.
::J
..
::E
;(
LOW PASS FILTER
10
::E
The low pass filter section for the XR-210/215/S200 is
formed by connecting an external capacitor or RC network across the output of phase comparator section.
Most common passive low pass filters are shown in
Figure 9. R1 is the internal resistor with nominal value
of 6 KIl. If an external bias network as shown in Figure
5 is used, R1 = 2 KIl. Pin numbers shown in Figure 9
apply to the XR-210 and XR·215.
/
V
/
10
20
26
V+ (VOLTS)
Figure 10. Maximum Input VoRaga VS. Supply VoRage.
The term KV shown in the filters is the total forward gain
of the Pll and is equal to the product of K and KO.
however, by adjusting T, the damping factor as well as
the capture range is changed. These two parameters
can be individually controlled in a lag-lead filter.
CAPTURE RANGE
The capture or acquisition range of the Pll, ± awC,
can be approximated as:
± awC ;;; ± aWL IF(j awc) I
General systems and control theory indicates that for
maximum stability the damping factor, 0, must be
greater than 0.7. In many FSK demodulation circuits
using Exar Plls, it was found that with 0 as low as 0.2,
the circuit functions properly at high baud rates.
(38)
where IF(j awe) I is the magnitude of the low pass filter
evaluated at w = awC. Since IF(j awe) I is always less
than unity, the capture range is always smaller than the
lock range.
DESIGN EXAMPLE
Design an FSK demodulator using the XR·210 with the
following specifications:
There is no explicit relationship for calculating awC,
however for a simple lag filter, it can be expressed as:
± awC;;;
{KV RADIANS
....;-;;;-
SEC
Mark frequency: 1070 Hz
Space frequency: 1270 Hz
Vce: + 12 volts
(39)
1. fo = 1170 Hz
For lag-lead filters, capture range can be roughly estimated by w'l' (See Figure 9.) Actual data indicates that
capture range is larger than w'l and approaches the
lock range.
Co = 200 ;;; 0.2 /LF
fo
AT (Pin
Adjust
DAMPING FACTOR
2. aWL
The advantage of using a lag-lead filter is that generally
speaking, it gives better stability due to the extra zero.
The damping factor can be adjusted without necessar·
ily changing the capture range. With a simple lag filter,
RO
=
211' (afl)
=
211' (200 Hz)
= ~ = 6.23 KIl
aWL Co
3-108
9 to GND) for correct fo .
=
1256 RAD/SEC
AN·22
3. Set capture range, AwC, equal to AWL. Using a laglead filter, AwC can be approximated by:
4. The damping factor is given by:
~ = .!
1
(1
2 v2 KV T1
+
T2 KV) == 0.22
Even with critical damping (~ < 1.0), the XR-210
functions properly as an FSK demodulator with baud
rate of 300 BPS.
KV = KOKI/> == 2921
»
Let R2 = 50 O. Thus T1
5. For V + of 12 volts, the input voltage should be limited to 5 volts PK·PK to avoid internal saturation (see
Figure 10).
T2
6. Schematic for the above example is shown in
C1 = 0.15 JLF
Figure 11.
12V
SK
10 •
S'
12 V
16
2.
SK
4.
4'
Co
=
0.2 f.LF
RO = 6.23 Kf!
C1 = 0.15 f.LF
R2 = 50 n
DATA OUT
f'
01 ",F
15
3.
FSK IN
11
14
10 •
AT = 10 KH
AT
Co
AO
Figure 11. XR·210 FSK Demodulation.
3·109
AN·22
Table 1. Summary of PLL Parameters (1)
PARAMETER
XR·215
XR·21 0
Phase Comparator
Kq,
4.0 VOLTS
RADIAN
3.6 VOLTS
RADIAN
VCO KO
-910- RAD/SEC
VOLT
RO Co
1565 RADIANS
SEC
RO Co
ROCO
Lock Range ± .6.wL
ROCO
Free Running
Frequency fo
Capture Range ± .6.wC
(Simple Lag) (3)
Damping Factor Il
(Simple Lag)
200 (1
Co
+
0.17) Hz
RT
~KOKq,
T1
1~
KOKq,T1
1262 RAD/SEC
VOLT
RO Ga
1765 RADIANS
SEC
ROGa
200 (1
Co
+
0.7) Hz
RT
2170 RADIANS
SEC
500 Hz
Co
~KOKq,
~KOKq,
1~
KOKq,T1
2
2
(1) RO, Rr. RX in KO
Co in ",F
(2) fo shown for Pins 15 and 16 open
(3) For other filter configurations, refer to the filter section. T1 = R1 C1.
3-110
4.0 VOLTS
RADIAN
1140 RAD/SEC
VOLT
T1
2
XR·S200
(2)
T1
1~
Ko Kq, T1
AN·23
High-Performance Frequency-lo-Voltage
Converter using the XR-2211
INTRODUCTION
A stable highly linear flv converter can be easily designed using the XR-2211 phase locked loop. The flv
can be used for a dynamic range from ± 1 % to ± 80 %
over a frequency range of .01 Hz to 1 MHz.
Figure 1. F/V Block Diagram.
Vo
The block diagram of the flv is shown in Figure 1. The
circuit will perform flv conversion according to the relationship
X INTERCEPT = K2
SLOPE = Kl
2 VREF
where K1 and K2 are set by the designer.
The transfer function relating Va to fiN is shown in Figure 2. The carrier detect output, Q, (Pin 5) which goes
high over the tracking range is shown in Figure 3.
lIN
10
The basic circuit diagram is shown in Figure 4. The
slope K1 is determined by the relationship
Figure 2. F/V Transfer Function.
K1 = _-_1_
VRCOR1
Q
where VR = VCC/2 - VBE
The x intercept or upper frequency, K2 Is determined by
the relationship
VCC
DESIGN EXAMPLE
Figure 3. F/V Carrier Detect Output.
Design a flv converter for the frequency range 100 Hz
to 600 Hz.
18 - 1.3
600 - 100
resolution '" VCC - VBE
fH - fL
The first step is to calculate the center frequency fo,
(Figure 2) in
33.4 mV
Hz
for VCC = 18 V
fo = fL
+
2
fH = 100
+
600 = 350 Hz
We can now calculate VREF
2
VREF = Vcd2 - VBE = 9 V - .65 V = 8.35 V
Supply voltage is directly proportional to the degree of
resolution obtainable.
The center frequency is given by
In order to obtain a greater resolution a higher supply
voltage is used. For this design an 18 V supply is used
giving us a resolution of approximately
fo = - ROCO
1
3-111
AN·23
'"
0,
l' 1. t
'0
00
Figure 4. F/V Circuit Diagram.
choosing RO = 20 K and rearranging
1
and a cut·off frequency
1
fC = _ _
1_
2,..RFCF
Co = ROFo = (20 KO) (350 Hz)
= .143,..F
Since
Selecting RF = 100, K, CF is then given by
C .. _3_ F
RO = (fH - fL)
F
2 fO RO
(fH - fU
~ = maximum expected rate of
where
2 (350 Hz) (20K)
(600 - 100) Hz
at
change of input frequency
~=
for
at
= 28 K
CF =
The selection of C1, the loop filter capacitor has a de·
gree of flexibility in its value. For a damping coefficient
of .5.
giving
7'
4
~,..F
300
= .01 ,..F
= 1 ,..secs FC = 160 Hz
detect filter. For RO = 470 K, and a capture range approaching the lock range, a minimum value of CD is
given by
It should be noted that an increased value of C1 will increase response time but reduce ripple, while a decreased value of C1 will reduce response time, in·
crease capture range, but increase ripple.
CO(,..F)
O?!
_1_6- = ...!§.. = .032 ,..F
fH - fL
500
The slope K1 can now be calculated
RO = 470 K
TEMPERATURE STABILITY
K1 = _ _
1_ =
1
VRCOR1
(8.35) (.143 ,..F) (28 K)
The XR-2211 is characterized by excellent temperature
stability, in the order of 50 ppm/oC. The output voltage
temperature coefficient can be calculated by
= 29.91 Hz
V
~ =
and since K2 = fMAX = 600 Hz
°c
The transfer function is then given by
fiN = - 29.91 Vo
300 cycles/sec
A carrier detect output is available at Pins 5 and 6 (0
and 0). The components Co and RO comprise the lock-
C1 .. Co = .143 ,..F = .035,..F
4
af/at'"
2 fa
R1
+
J....
K1
x 50 ppm x (fH - fU
°c
substituting
600
= 33.4 mV
Hz
The filter RF CF forms a one-pole post detection filter,
with a time constant
x 50 ppm x (600 - 100) Hz
.8 mV
°C
3-112
AN·24
Digitally Programmable Phase-Locked Loop
INTRODUCTION
CIRCUIT DESIGN
Most phase-locked loops require manual potentiometer
adjustment if the center frequency of the circuit is critical. Also, once adjusted, if ambient temperature
changes cause the PLL:s VCO or center frequency to
shift, the potentiometer would have to be readjusted if
the accurate center frequency was to be maintained.
Readjustments are, of course, an impractical solution.
Figure 2 shows the XR-215 internal blocks and necessary external components. The VCO center frequency,
fo, is calculated by the formula:
f
o
= 200 (1
Co
+ 0.6) Co .in /IF
RX
RX In K{}
(1)
In this application it is desirable to have a variable current drawn from Pin 10, and RX omitted. Equation 1 is
then modified to equation 2 is a current instead of a resistor is used at Pin 10.
This application note describes the design of a digitally
programmable PLL. Being digitally controlled, a microprocessor or other digital circuitry could easily tune or
retune the VCO when necessary. The design uses the
XR-215 monolithic PLL together with the XR-9201 D/A
converter, which provides the tuning function.
f
PRINCIPLES OF OPERATION
o
= 200 (1
Co
+I
) Co in /IF
PIN 10 IplN 10 in mA
(2)
Equation 2 can now be used to determine IplN 10 for a
given fo adjustment range. Once the center frequency
has been set, RO can be calculated to adjust the tracking range using the relationship:
Figure 1 shows the block diagram of the digitally programmable PLL. The circuit is comprised of two blocks:
the PLL and the D/A converter. The PLL is used for FM
demodulation, synchronizing signals, or frequency synthesis. It processes these signals, which are centered
around its free-running frequency, fo . This fo is set by
the internal vOltage-controlled oscillator, VCO, in the
PLL. The VCO within the XR-215 is really a currentcontrolled oscillator, ICO. This is, the frequency of oscillation of the ICO is directly proportional to the timing
current, IT IT is made up of two components: an internal fixed current and an externally programmable current, IplN 10· This IplN 10 control current is provided by
a D/A converter with a current output. Since the D/A
provides an output current that is directly set by an input digital code, this code will actually control the center frequency of the PLL:s ICO, fo .
AW _ 2 Af _ 1565 rad RO in K{}
± '"
L - 1I''''L---ROCO sec Co in /IF
or
RO =
1565 RO in K{}, Co in /IF
211'4fLCO
(3)
(4)
Now with RO calculated for 4fL, the capture range, 4fC
is set using the loop time constant capacitors C1:
±4WC
T1
Ko
K.p
= JKoK.p = 211'4FC
T1
(5)
= Loop Time Constant
=
VCO Conversion Gain
= Phase Detector Conversion Gain
XR-2t5
Substituting the values for
M-f--OYO
KoK.p and solving for FC:
4FC = ~
211'
100-+-4----<
or
0.684
ROCOC1
0.017
R in K{} C in F
4fC2ROCO 0
, 0 /l
(6)
(7)
The resistors RI and RF are used to set the gain of the
op amp when used for FM demodulation. Cc is op amp
compensation and is in the range of 300 pF for unity
gain to 50 pF for a gain of 10 and up. The resistors going to Pins 4, 5, and 6 are used to dc-bias the phase detector inputs at half supply, with their actual value not
critical. The capacitors C2 and C1 are used for capacitive coupling.
DATA INPUT
Figure 1. Programmable PLL Block Diagram.
3-113
AN·24
r-----------------~--~~C
R,
SK
2K
O.I.F t--"'IVIt--~_{
fin
0--11-+------....
Cl
2K
SK
,oo----+----------{11S}----<
10K
Figure 2. XR-215 with External Components.
DATA INPUT
17 - - - - - - - - - - - - -
lD
LATCHES
R
R
Figure 3. XR-9201 D/A with External Components.
Figure 3 shows the D/A converter internal blocks with
external circuitry. Data is fed into the input latches,
which will allow data to flow through to the current
switches when CE is high and hold data when CE is low.
The output currents are related to the digital inputs by:
Also: 10
+ iQ = IFS
= Full-scale Current
IFS = 2IREF(255)
256
(9)
(10)
The full-scale current is set using R by the relationship:
B7 Bs B5 B4 B3 B2 B1
BO]
10=21REF [ -+-+-+-+-+-+-+- (8)
2
4
8 16 32 64 128 256
(11)
where
BN
BN
B7
BO
= 1 if bit N is high
= 0 if bit N is low
= MSB
= LSB
The 10 KO potentiometer from Pin 3 to ground is used
to fine-adjust the internal reference to exactly 2.00 V.
3-114
AN·24
DESIGN EXAMPLE
Design a digitally programmable PLL with a center frequency, fo, equal to 20 kHz. Provide for a 10% digital
tuning range. The circuit shall also have the following
lock and capture ranges:
±4fL
= 5 kHz,
±4fC
4. C1 is determined by equation 7:
C
= 4 kHz
Co = 0.01 p.F
fo = 20 K
IAEF
= .50 p.A
7. Calibration of the system is accomplished by adjusting potentiometer A3 for VAEF on the XA-9201 to exactly 2.00 V.
3. AO Is now calculated from equation 4:
= 5 KO
Figure 4 shows the completed design example.
+tIVo-~------.
01
0._,.,1 I
o.n.,.,
s.
0,
to
PHAIE
>-+-''-+--ovo
DETECTOR
t.
0.1 "F
I.,
p'
s.
.A·III
•• 0-+-+-....
__-+-....:'=1.-<
OUTPUT
F
A = 2.00 = 40 KO
50 p.A
+ 2 K Adjustment Aange
,.
p.
6. The reference current setting resistor, A, is now determined using equation 11:
22 K (0.01) -1 = 0.1 mA
200
A =
1565
.
o
(211') (5 K) (0.01)
= 0.022
IplN 10 max = IFS 2IAEF(255)
256
2. This same equation is used to determine the maximum value of IplN 10 for a 10% change In f o. Aearranging equation 2 yields:
f_
Co_
IPIN 10 = _0
1
(max)
200
0.017
(4 K)2 (5) (0.01)
5. The D/A components can now by specified, first using equation 10 and the previously calculated IplN
10 maximum current:
1. Using equation 2, first with IplN 10 = 0 (digital inputs all zeros) Co can be determined.
fO = 200
Co
=
1
..
,.
,
o.a,."
OND
SI(
1"""'0
DATA INPUT
CE
.vcc
X.... lOt
..•
tOK
Figura 4. Digitally Programmable PLL.
3-115
4UC
+1'1
-7"
..,"'----+
-VII.,:'---l--+
AN·25
Full-Duplex 1200 BPS/300 BPS
Modem System
ceived signal range can vary from about 0 dBm to
-45 dBm.
INTRODUCTION
This application note describes the construction of a
full-duplex modem system which operates at either
1200 BPS with phase shift keying encoding (PSK)
or 300 BPS with frequency shift keying (FSK). The
1200 BPS is in a synchronous format or 300 BPS asynchronous.
DEMUX. Demultiplexer to switch transmitted carrier
(Txc) and received data (Rxd) between 300 BPS and
1200 BPS.
AUTO SPEED SELECT. Automatically senses whether
300 BPS or 1200 BPS information is being received
and controls the demux with this information.
This system is not intended to be directly connected to
the telephone network as this requires FCC approval.
SLICER. A voltage comparator used to convert analog receive carriers (Rxcar) into digital signals suitable for the XR-2123 and XR-14412 Rxcar inputs.
PRINCIPLES OF OPERATION
The heart of this system is three LSI integrated circuits.
The XR-2120 is a switched-capacitor filter (SCF) to
provide precise bandpass filtering at 1200 Hz and
2400 Hz. The XR-2123 performs the 1200 BPS PSK
modulation/demodulation and the XR-14412 the 300 BPS
FSK modulation/demodulation. These three devices are
shown with the necessary external functions to perform
a 212A type synchronous modem in Figure 1. These
other functions are described as follows:
CARRIER DETECT (CD). A level sensor with a digital
output to indicate when a Rxcar is present.
TIMING CIRCUIT. This circuit extracts a 600 Hz receive signal timing from the Rxcar for synchronization purposes in the XR-2123.
SCRAMBLER/DESCRAMBLER. These sections scramble the data to be transmitted (Txd) while descrambling the received data (Rxd).
LINE INTERFACE. Provide DC isolation between modem and telephone network. This section, known as
a direct-access arrangement, must be approved by
the FCC for direct connection to the telephone network.
DELAY CIRCUIT. To provide a delay between the request to send (RTS) data and clear to send (CTS) data commands.
Figure 2 shows the complete circuit implementation of
modem, with Table 1 listing the recommended circuit
values.
AGC. Automatic gain control to provide a constant
signal level to other portions of the circuit. Its re-
Figure 1. 212A Type Modem System.
3-116
CLOCK GENERATOR
~
-.J
AUTO SPEED SELECT
»
z
•
I\)
Figure 2. XR-212A Type Modem.
en
AN·25
A.
B.
C.
D.
E.
F.
G.
H.
I.
J.
K.
L.
M.
N.
O.
P.
Q.
R.
S.
T.
U.
XR-4741 Quad Op Amp
XR-4741 Quad Op Amp
XR-14S8 Dual Op Amp
LM-339 Quad Comparator
XR-14412 FSK Mod/Demod 300 BPS
XR-2120 Filter-Switched Cap
XR-2123 PSK Mod/Demod 1200 BPS
CD-4049 Hex Inverter
CD-4016 Quad B1-Lateral Switch
CD-4030 Quad Exclusive-OR Gate
CD-4013 Dual D Flip-Flop
CD-4013 Dual D Flip-Flop
Dual 4 Bit Static Register 401S
Dual 4 Bit Static Register 401S
Dual 4 Bit Static Register 401S
Dual 4 Bit Static Register 401S
MM7404 Hex Inverter
DM74193 Synchronous Up/Down Counter
XR-1488 Quad Line Driver
XR-1489 Quad Line Receiver
XR-4194 Dual Tracking Regulator
R1
R4
R7
RlO
R13
R16
R19
R22
R2S
R28
R31
R34
R37
R40
R43
R46
R49
RS2
RSS
RS8
R61
2.2K
2.2K
10K
10K
100K
10K
100K
62K
18K
4.7K
120K
68K
600
10K
39K"
39K"
39K"
13K
10K
10K
10K
R2
RS
R8
Rn
R14
R17
R20
R23
R26
R29
R32
R3S
R38
R41
R44
R47
RSO
RS3
RS6
RS9
2.2K
1.2K
10K
1K
47K
100K
10K
47K
62K
10K
10K
600
10K
10K
180K"
180K"
464"
71.SK
10K
1M
R3
R6
R9
R12
R1S
R18
R21
R24
R27
R30
R33
R36
R39
R42
R4S
R48
RS1
RS4
RS7
R60
All resistor values are in ohms.
" = > 1 % tolerance.
Crystals
C1
C2
C3
C4
Cs
C6
C7
C8
C9
ClO
Cn
C12
C13
82 pF
.0331'F
.0221'F
.1 I'F
.0331'F
.0331'F
.0331'F
.0331'F
.0331'F
.0331'F
.1 I'F
0.221'F
4.7 I'F
C14
C1S
C16
C17
C18
C19
C20
C21
C22
C23
C24
C2S
C26
CR1 CR2 CR3 -
1 I'F
.1 I'F
.001 I'F
.001 I'F
4.71'F
2.21'F
4.71'F
4.71'F
.1 I'F
.1 I'F
4.71'F
4.71'F
4.71'F
4.032 MHz
1,000 MHz
4.608 MHz
MTRON
FOX
X-TRON
Transformer
T1 -
T2220 MICROTRAN
Transistors
Q1 Q3 Q4 -
A8S4
C1741
C1741
FEls
Q2 -
Component Ust for 212A Type Modem System
3-118
2N4861
ROHM
ROHM
ROHM
2.2K
1M
1M
62K
62K
470K
10K
100K
1K
1M
1K
300
10K
10K
392"
392"
180K"
10K
10K
10K
AN·26
High-Speed FSK Modem Design
INTRODUCTION
DESIGN EQUATIONS - Refer to Figura 6
As the need for transmitting data increases, some applications require data to be sent faster than the conventional telephone line modems. This application note
describes the design and construction of a high speed
full-duplex, FSK modem using XR-2206 as a modulator
and XR-210 as the demodulator transmitting data at the
rate of 100 Kilobaud.
1. The frequency of oscillation of the XR-2206 when
used as a modulator, with the FSK input (Pin 9) is
high is:
R7A
PRINCIPLES OF OPERATION
The block diagram in Figure 1 describes the basic
building block in any FSK modem system. The major
difference is that in high speed applications, data is
transmitted over a twisted pair wire or coaxial cable instead of the telephone line with its limited bandwidth.
The complete system is comprised of an answer and
originate modem. Simply stated, the modulator converts the input data to two discrete frequencies corresponding to its 1's and O's and is then sent over a line or
cable. The line hybrid steers these frequencies to the
bandpass filter, where it will remove any unwanted signals that might have gotten through due to the line or
cable before reaching the demodulator. The demodulator, which is a phase locked loop, will lock onto the incoming frequencies and produce 1's and O's on its output. A detailed description on FSK techniques is given
in the EXAR MODEM DESIGN HANDBOOK.
R8A
DATA
0-
PLL
DEMODULATOR
j4-.-
Table 1
ORDER NO
C1
C2
2
3
4
1.414
3.546
1.082
2.613
1.753
3.235
.7071
1.392
.9241
.3825
1.354
.3090
5
0SENT
SINEWAVE
MODULATOR
T'
C3
.2024
.4214
ANSWER
BANDPASS
FILTER
f4-
,.-
BANDPASS
FILTER
560/640KHZ
DATA
rOBE
+ R8B C3
2. The filter best suited for modem applications is the
butterworth filter due to its linear phase response
within the passband. Table 1 shows the normalized
capacitor values for butterworth filters up to fifth order.
ORIGINATE
RECEIVED
+ R7B C3
When the FSK input (Pin 9) is low the frequency
equals
J
t
LINE
LINE
HYBRID
HVBRID
,~".
1'"'
1
TWISTED
PAIR WIRE OR
COAXIAL CABLE
Figure 1. Block Diagram of High Speed FSK Modem System
3-119
PLL
DEMODULATOR
SINEWAVE
MODULATOR
ro
DATA
RECEIVED
DATA
BE
-0 TO
SENT
AN·26
Figure 3 shows a third order active high pass filter. To
solve for the actual resistor values we use the formula:
The equations for using the XR-21 a as an FSK demodulator are as follows:
.1F L = (2).1F
R=--WcCNC
.1F = Fmark - Fspace
Where CN is the normalized capacitor and Wc = 2"11"Fc.
In this equation, make all capacitors equal.
.1FL
Fa
=
2(Fmark - Fspace)
Fmark
=
+
-234 ( 1
Fa =
After calculating Rx remember for single supply operation the op amp must be biased at 1/2 VCC; therefore
take twice the calculated value for Rx and configure as
shown in Figure 4.
c
AT is in
AT
KD
234
Co =
.1W
Co is in p.f
+.1)
-
Co
Figure 3.
Fspace
2
Fa
=J
Cl =
+V
RO =
.1WL
6KCl
.1WL
6K.1Wc 2
2(1565)
RO is in KD
.1WLCO
C18 =
C19 =
Figure 4.
Figure 5 shows a third order active butterworth low
pass filter. To convert from the normalized capacitor
values to the actual capacitor values, we use the formula:
10- 4
2"11" (Baud Rate)
10- 4
3"11" (Baud Rate)
DESIGN EXAMPLE
Design a FSK Demodulator with the following specification:
FO = 200 kHz
.1FL = 160 kHz
Where CN is the normalized capacitor value and Wc
2"11"Fc. In this equation, make all resistors equal.
=
Baud Rate = 100 Kilobaud
In this example, we must know the mark and space frequencies. If Fmark = 160 kHz and Fspace = 240 kHz,
the free running frequency is equal to
Fmark
+
Fspace
2
= 200 kHz
In order to calculate the free running frequency, we use
the formula:
Fa = 234
Co
Figure 5.
3-120
AN·26
In this example we will use a variable resistor (AT) in order to fine tune FO to exactly 200 kHz, therefore:
234
F0- - (1
Co
For the filter, 18 dB of attenuation should be sufficient;
therefore:
Design a third order high pass butterworth filter with fc
= 100 kHz.
+.1)
-
AT
1) In order to solve for actual resistor values use Table
1 and set all capacitors equal. The design example
is shown below:
The lock range (<1FU is equal to twice the difference of
the mark and space frequencies, so
<1FL = 2(Fspace - Fmark)
RO, which sets the lock range equals:
R _ 2(1565)
o - <1WLCO
C12 '
1000pI
<1WL = 211"FL
6.28 (160x 103)
= 1004800
2(1565)
c 1• •
'
1000p1
1000p1
::::·I'I---+--IRX~'-7-.BK----l
Where Co is in Itf
and RO is in KD
1004800.0015
c 1J
R= _ _
1_
WcCN C
= 2.0 KD
The Capture Range (<1Fcl is equal to:
<1W
c
r;;.wL
_
<1Wc = 2dF c
-V6KC17
1
= 450D
(6.28 x 100x 103)3.546(1000 x 10- 12)
R14=
1
(6.28 x 100 x 103)1.392(1000 x 10- 12)
1.1KO
R -
1
7.8KO
<1WL = 211"<1FL
In order to solve for C17 we rearrange the equation to
read.
x - (6.28x 100x 103).2024(1000 x 10- 12)
After calculating Rx take twice the value and configure as shown below:
<1WL
C17 =
R15=
(6K) Wc 2
+v
1004800
= 300x10- 12
(6K) 753600 2
!
R16 = 15.6K
therefore:
RX
<1W
_
c
/
R17 • 15.6K
1004800
-V '(6X 103) 300 x 10-12
= 118.97 kHz
Design a third order lowpassbutlerworth filter with Fc
= 300 kHz.
It is important to note C17 and 6K set the loop time constant. When used as an FSK Demodulator, the XR·210
has post detection filtering on the output of the phase
detector. In order to calculate the values for C18 and
C19 we use the relationships:
2) In order to solve the actual capacitances, use Table
1 and set all resistors equal. The design example is
shown below:
C10 • 1880 pi
10- 4
C18=----211" (Baud Rate)
10- 4
6.28 (100 x 103)
C19 =
10- 4
9.42 (100x 103)
160 x 10- 12 or 160 pf
Cg ' 7J8pl
106x10- 12 or 106 pf
3·121
I
AN .. 26
Design an FSK modulator with Fmark = 560 kHz and
Fspace = 640 kHz. The frequency of oscillation with
the FSK input (Pin 9) is high is equal to:
Wc = 2...Fc
C
=
3.546
2'1"(300 x 103) 1 x 103
C10 =
f
P
Fmark = - - - - - . : - - R7A + R7B C3
3.546
= 1880 f
1884000000
P
C9 = __
1._39_2_
1884000000
C11
= 1880
.2024
1884000000
- - - - - - = 560 x 103 or 560 kHz
1K
+
7850.001"f
738 pf
When FSK input (Pin 9) is low the frequency is equal to:
107 pf
Fspace =
R8A
+
R8B C3
-----:--:--:-:-:- = 640 x 103 or 640 kHz
1K
+
5620.001"f
'"
"
DATA
Figure 6. Complete Schematic for 100 Kilobaud FSK Modam
3-122
~
I\)
<..:>
l>
z•
Figure 7. P.C. Board Layout lor 100 Kilobaud FSK Modem-Component Side
I\)
0)
AN·26
PART NO.
ANSWER
ORIGINATE
PART NO.
ANSWER
ORIGINATE
Rl-R2
R3
R4
R5
R6-R7
*R8
R9-Rl0
Rll-R13
R14
R15
R16-R17
R18-R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
RO
RT2
R7A
R7B
R8A
R8B
RTl
5.1K
50KO Pot
2000
510
1000
750
10 KO
1 KO
1.1 KO
4500
16 KO
5 KO
2 KO
4 KO
10 KO
5 KO
249 KO
4 KO
3 KO
10 KO
5 KO
5620
1.3 KO
2.4 KO
1 KO Pot
1.4 KO
1 KO Pot
7500
1 KO Pot
500
5.1K
50KO Pot
2000
510
1000
750
10 KO
1 KO
2280
900
3 KO
5 KO
2 KO
4 KO
10 KO
5 KO
249 KO
4 KO
3 KO
10 KO
5 KO
5620
1.3 KO
7.4 KO
1 KO Pot
5620
1 KO Pot
3.3 KO
1 KO Pot
1000
Cl
C2
C3
C4
C5-C6
C7
C8
C9
Cl0
Cll
C12-C14
C15
C16
C17
C18
C19
C20
C21
C22-C25
01
Tl
Zl
IC 1
IC 2
IC 3
IC 4
IC 5
*1500
Jl-J2
47 iLl
4.7 ILl
.001 iLl
4.7 iLl
.1 iLl
4.7 iLl
1 iLl
738 pi
1800 pi
107 pi
1000 pi
.22 iLl
1 iLl
300 pi
150 pi
106 pi
10 pi
.1 iLl
4.7 iLl
2N2222A
PE-5760**
1 N5232
XR-2206
LH0033t
XR-5532
XR-5533
XR-210
47 iLl
4.7 iLl
.001 iLl
4.7 iLl
.1 iLl
4.7 iLl
1 iLl
317 pi
807 pi
46 pi
1000 pi
.22 iLl
1 iLl
300 pi
150 pi
106 pi
10 pi
.1 iLl
4.7 iLl
2N2222A
PE-5760**
lN5232
XR-2206
LH0033t
XR-5532
XR-5533
XR-210
JUMPER
WIRE
JUMPER
WIRE
*Twisted Pair Wire
**Pulse Engineering
:j:National
Figure 8_ Component List for 100 Kilobaud FSIC Modem
3-124
AN·27
High-Frequency TTL Compatible Output
from the XR-215 Monolithic PLL Circuit
INTRODUCTION
With digital circuitry as common as it is, it is necessary
to be able to interface analog signals to digital systems.
This can be done. by using the XR-215, a monolithic PLL
circuit, and an additional buffer circuit.
approximately 3 volts. The veo output is ac coupled in
order to block this dc level. The input signal causes 01
to be overdriven, where the amplitude is 400 mVpp offsetted at approximately 0.769 Vdc. When 01 is in the
offstate, the collector voltage will be forced high and
when this voltage exceeds 0.7 Vdc, 02 will turn on and
the collector of 01 will be clamped at 0.7 Vdc. The output of the veo at the TIL buffered output will be in
phase.
When an input signal is present within the capture
range of the PLL system, the XR-215 will lock on the in·
put signal and the veo section of the PLL will synchronize with the input frequency. The veo output can then
be buffered in order to produce a TIL compatible output.
veo
PHASE
COMPARATOR
+Vcc OUTPUTS
PRINCIPLES OF OPERATION
Figure 1 shows a functional block diagram of the XR215 monolithic PLL system. The circuit contains a
phase comparator, a voltage controlled oscillator (VeO),
and an operational amplifier. A complete phase locked
loop system can be made by simple ac coupling the
veo output to either of the phase comparator inputs,
and by adding a low pass filter to the phase comparator
outputs.
PHASE
COMPARATOR
RANGE
TIMING
SELeCT CAPACITOR
4
6
INPUTS
PHASE
COMPARATOR
INPUT
L-_f-":O ~~~T~~I~
Q-l!-I----'
BIAS
The veo output can be buffered in order to produce a
TIL compatible output at high frequencies by the simple common emitter circuit shown in Figure 2. The amplitude of veo degrades as frequency increases and at
21 MHz, the amplitude is reduced from approximately
2.5 Vpp to 400 mVpp. The dc output level is 2 volts below Vee so with Vee equal to ± 5 volts, the dc level is
-VEE
QP AMP
OP AMP
INPUT
OUTPUT
OP AMP
COMPENSA nON
Figure 1. Functional Block Diagram of XR-215 Monolithic PLL
Circuit_
TTL BUFFERED
OUTPUT
FROM PIN :;-15
OF XR-215
01 - 02=92N2369
Figure 2. Common Emitter Buffer Circuit.
3-125
AN·27
veo OUTPUT (PIN 15)
OF XR-215
TTL BUFFERED OUTPUT
AT 21 MHz MEASURED
WITH Xl00 PROBE.
PROPAGATION DELAY IS
APPROXIMATELY 5 ns
3-126
AN·27
HIGH FREQUENCY SYNTHESIS
An application where a high frequency TIL compatible
output would be useful is in high frequency synthesis,
as shown in Figure 3. The output of the buffer, which
can produce a high frequency TIL compatible output,
is divided down the divider modulus N. When the entire
system is synchronized to an input signal at frequency
fs, the veo output (pin 15) is at frequency Nfs, where N
is the divider modulus. This is useful because a large
number of discrete frequencies can be synthesized
from a given reference frequency.
CB
II I·
+5V
C1
Cc
INPUT
0
f = fs
C1
16
I
1Kn
4
8
5
1Kn
XR-215
6
'>---+-015 VCO OUTPUT
fo = Nfs
Cc
14
-5V
+5V
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