1984_Intel_Memory_Components_Handbook 1984 Intel Memory Components Handbook

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MEMORY COMPO'NENTS
HANDBOOK

1984

Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which rnay appear in
this document nor does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local sales office to obtain the latest specifications before placing your order.
The following are trademarks of Intel Corporation and may only be used to identify Intel Products:
BITBUS, COMMputer, CREblT. Data Pipeline, GENIUS, i, ~, ICE,iCS, iDBP,
iDIS, 12 1CE, iLBX, im , iMMX, Insite, Intel, intel, intelBOS, Intelevision, inteligent
Identifier, inteligent Programming, Intellec, Intellink,. iOSP, iPDS, iSBC, iSBX,
iSDM, iSXM, Library Manager, MCS, Megachassis, MICROMAINFRAME, MULTIBUS, MULTICHANNEL, MULTIMODULE, Plug-A-Bubble, PROMPT,
Promware, QUEST, QUEX, Ripplemode, RMX/BO, RUPI, Seamless, SOLO,
SYSTEM 2000, and UPI, and the combination of ICE, iCS, iRMX, iSBC, MCS, or
UPI and a numerical suffix.
MDS is an ordering code only and is not used as a product name or trademark. MDS") is a registered trademark of Mohawk Data
Sciences Corporation .
• MULTIBUS is a patented Intel bus.
Additional copies of this manual or other Intel literature may be obtained from:
Intel Corporation
Literature Department
3065 Bowers Avenue
Santa Clara, CA 95051

1983

Table of Contents
Alphanumeric Index ...................................................................... v

CHAPTER 1
Memory Overview . ................................................................. 1;1

CHAPTER 2
Intel Memory Technologies . ................................................. _..... "

2-1

CHAPTER 5
E2 PROMs & NVRAMs (Incircuit Programmable Writable Memories)
APPLICATION NOTES
AP100 Reliability Aspects of a Floating Gates E2 PROM .......................... 5·1
AP158 Designing with the System Friendly 2817 A 5V·Only E2 PROM . . . . . . . . . . . . . . .. 5·8
ARTICLE REPRINT
AR119 16K EE·PROM Relies On Tunneling for Byte Erasable
Program Storage ............................... o' • • • • • • • • • • • • • • • • • • • 5·q7
DATA SHEETS
.
2004, 4K (512 x 8) Non·Volatile Random Access Memory ......................... 5·73
2816A, 16K (2K x 8) Electrically Erasable PROM, .. : .....•...................... 5·83
2817A, 16K (2K x 8) Electrically Erasable PROM ................................ 5·95

CHAPTER 7
General Information ................................................................ 7·1

PREFACE
This handbook has been prepared to provide a comprehensive grouping of
technical literature covering Intel's memory products, with special emphasis
on microprocessor applications. In addition, a brief summary of current
memory technologies and basic segmentation cif product lines is provided.

Memory Overview

(

CHAPTER I: MEMORY OVERVIEW
Joe Altnether

MEMORY BACKGROUND
AND DEVELOPMENT

store important data on a non-volatile medium before
the power goes down.

Only ten years ago MOS LSI memories were little more
than laboratory curiosities. Any engineer brave enough
to design with semiconductor memories had a simple
choice of which memory type to use. The 2102 Static
RAM for ease of use or the 1103 Dynamic RAM for low
power were the only two devices available. Since then,
the memory market has come a long way, the types of
memory devices have proliferated, and more than 3,000
different memory devices are now available. Consequently, the designer has a lot to choose trom but the
choice is more difficult, and therefore, effective memory
selection is based on matching memory characteristics
to the application.
~'

Despite their volatility, RAMs have become very popular, and an industry was born that primarily fed computer
systems' insatiable appetites for higher bit capacities
and faster access speeds.

RAM Types
Two basic RAM types have evolved since 1970. Dynamic
RAMs are noted for high capacity, moderate speeds
and low power consumption. Their memory cells are
basically charge-storage capacitors with driver transistors. The presence or absence of charge in a capacitor is interpreted by the RAM's sense line as a logical
1 or O. Because of the charge's natural tendency to distribute itself into a lower energy-state configuration,
however, dynamic RAMs require periodic charge refreshing to maintain data storage.

Memory devices can be divided into two main categories: volatile and non-volatile. Volatile memories retain their data only as long as power is applied. In a great
many applications this limitation presents no problem.
The generic term random access memory.(RAM) has
come to be almost synonymous with volatile memory
in which there is a constant rewriting of stored data;

Traditionally, this requirement has meant that system
designers had to implement added circuitry to handle
dynamic RAM subsystem refresh. And at certain times,
refresh procedures made the RAM unavailable for writing or reading; the memory's control circuitry had toarbitrate access. However, there are nuw two available
alternatives that largely offset this disadvantage. For
relatively small memories in microprocessor environments, the integrated RAM or iRAM provides all
of the complex refresh circuitry on chip, thus, greatly
simplifying the system design. For larger storagerequirements, LSI dynamic memory controllers reduce
the refresh requirement to a minimal design by offering a monolithic controller solution.

'In other situations, however, it is imperative that a nonvolatile device be used because it retains its data
whether or not power is applied. An example of this requirement would be retaining data during a power
failure. (Tape and disk storage are also non-volatile
memories but are not included within the scope of this
.book which confines itself to solid-state technologies in
an IC form factor.)
Thus, when considering memory devices, it's helpful to
see how the memory in computer systems is segmented.
by applications and then look at the state-of-the-art in
these cases.

Where users are less concerned with space and cost
them with speed and reduced complexity, the second
RAM type - static RAMs - generally prove best.
Unlike their dynamic counterparts, static RAMs store
ones and zeros using traditional flip-flop logic-gatel:onfigurations. They are faster and require no refresh. A
user simply addresses the static RAM, and after a very
brief delay, obtains the bit stored in that location. Static
.devices are also simpler to design with than dynamic
RAMs, but the static cell',s complexity puts these nonvolatile chips far behind dynamics in bit capacity per
square mil of silicon.

Read/Write Memory ,
First examine read/write memory (RAM), which permits
the access of stored memory (reading) and the ability
to alter. the stored data (writing) ..
Before the advent of solid-state read/write memory,
active data (data being processed) was stored and retrieved from non-volatile core memory (a magneticstorage technology). Solid-state RAMs solved the size
and power consumption problems associated with core,
but added the element of volatility. Because RAMs lose
their memory when you turn off their power,.you must
leave systems on aU the time, add battery backup or

TheiRAM
There is away, however, to gain the static RAM's
design-in simplicity but with the dynamic RAM's higher
1-1

MEMORY OVERVIEW

The first ROMs contained cell arrays in which the sequence of ones and zeros was established by a metal ization interconnect mask step during fabrication. Thus,
users had to supply a ROM vendor with an interconnect
program so the vendor could complete the mask and
build the ROMs. Set-up charges were quite high - in
fact, even prohibitive unless users planned for large
volumes of the same ROM.

capacity and other advantages. An integrated RAM or
iRAM integrates a dy_namic RAM and its control and
refresh circuitry on one substrate, creating a chip that
has dynamic RAM density characteristics, but looks like
a static RAM to users. You simply address it and collect
your data without worrying about refresh and arbitration.
Before iRAM's introduction, users who built memory
blocks smaller than 8K bytes typically used static
RAMs because the device's higher price was offset by
the support-circuit simplicity. On the other hand, users
building blocks larger than 64K bytes usually opted for
dynamic RAMs because density and power considerations began to take precedence over circuit complexity issues.
For the application area between these two limits, decisions had to depend on less straightforward tradeoffs.
But iRAMs could meet this middle area's needs (See
Figure 1).

To offset this high set-up charge, manufacturers developed a user-programmable ROM (or PROM). The first
such devices used fusible links that could be melted or
"burned" with a special programmer system.
Once burned, a PROM was just like a ROM. If the burn
program was faulty, the chip had to be discarded. But,
. PROMs fur~ished a more cost-effective way to develop
program memory or firmware for low-volume purposes
than did ROMs.

Read-Only Memory

As one alternative to fusable-link programming, Intel
pioneered an erasable MOS-technology PROM (termed
an EPROM) that used charge-storage programming. It
came in a standard ceramic DIP package but had a window that permitted die exposure to light. When the chip
was exposed to ultraviolet light, high energy photons
could collide with the EPROM's electrons and scatter
them at randorr, thus erasing the memory.

Another memory class, read-only memory (ROM), is
similar to RAM in that a computer addresses it and then
retrieves data stored at that address. However, ROM includes no mechanism for altering the data stored ,at that
address - hence, the term read only.
ROM is basically used for storing information that isn't
subject to change - at least not frequently. Unlike
RAM, when system power goes down, ROM retains its
contents.

The EPROM was obviously not intended for use in
read/write applications, but it proved very useful in
research and development for prototypes, where the
need to alter the program several times is quite common. Indeed, the EPROM market consisted almost exclusively of development labs. As the fabrication process became mature; however, and volumes increased,
EPROM's lower prices made them attractive even for
medium-volume production-system applications.

ROM devices became very popular with the advent of
microprocessors. Most early microprocessor applications were dedicated systems; the system's program
was fixed and stored in ROM. Manipulated data could
vary and was therefore stored in RAM. This application
split caused ROM to be commonly called program
storage, and RAM, data storage.

Figure 7. Double Poly Structure
METAL--______

After fabrication is complete, the wafers· are sent for
testing. Each circuit is tested individually under conditions designed to determine which circuits will operate
properly both at low temperature and at conditions
found in actual operation. Circuits that fail these tests
are inked to distinguish them from good circuits. From
here the wafers are sent for assembly where they are
sawed into individual circuits with a paper-thin diamond
blade. The inked circuits are then separated out and the.
good circuits are sent on for packaging.

Figure 6. Completed Circuit Jwithout passivation)
2-3

inter

MEMORY TECHNOLOGIES

Packages fall into two categories - hermetic and nonhermetic. Hermetic packages are Cerdip, where two
ceramic halves are sealed with a glass fritt, or ceramic
with soldered metal lids. An example of hermetic
package assembly is shown in Table 1 , Non-hermetic
packages are molded plastics.

frame placed on top. This sets the lead frame in glass
attached to the base. The die is then attached and
bonded to the leads. Finally the lid is placed on the
package and it is insertedin a seal furnace where the
glass on the two halves melt together making a hermetic
package.

The ceramic package has two parts, the base, which
has the leads and die (or circuit) cavity, and the metal
lid. The base is placed on a heater block and a metal
alloy preform is inserted. The die is placed on top of the
preform which bonds it to the package. Once attached,
wires are bonded to the circuit and then connected to
the leads. Finally the package is placed in a dry inert atmosphere and the lid is soldered on.

In a plastic package, the key component is the lead
frame. The die is attached to a pad on the lead frame
and bonded out to the leads with gold wires. The frame
then goes to an injection molding machine and the
. package is formed around the lead frame. After mold
the excess plastic is removed and the leads trimmed.
After assembly, the individual circuits 'are retested at an
elevated operating temperature to assure critical operating parameters and separated according to speed and
power consumption into individual specification groups.

The cerdip package consists of a base, lead frame, and
lid. The base is placed on a heater block and the lead

Table 1. 2164A Hermetic Package Assembly
Flow,

Wafer
Die saw, wafer break
Die wash and plate
Die visual inspection

f-o

Passivation, metal

QA gate
Die attach
(Process monitor)

Wet out

Post die attach visual
Wire bond
(Process monitor)
QA gate

Cap align, glass
. integrity, moisture'

Temp cycle

2. _

-0

4 x/operator/
machine/shift
every lot

1/129, LTPD=3%

4 x Ifurnace/shift

0/15, LTPD=15%

lOx to mil std.
883 condo C

1/11, LTPD=20%

Hermeticity check
(Process mqnitor)

FIG leak

100% devices

Lead Trim
(Process monitor)

Burrs, etc. (visual)
Fine leak

4 x Istation/shift
2 x /station/shift

External visual

Solder voids, cap
alignment, etc.

Class test
(Process monitor)

Run standards
(good and reject)
Calibrate every
system using
"autover" program

Every 48 hrs.

1. _

0/11 LTPD = 20%

100% devices
All previous items

Seal and Mark
(Process monitor)

0/76, LTPD = 5%

4 x/operator/shift
100% of devices

. Orientation, lead
dressing, etc.

Post bond inspection

f-o

100% of die
Every lot

Mark,and Pack
Final QA

1. Units for assembly reliability monitor:

(See attached)
2. Units for product reliability monitor.

2-4

0/15, LTPD=15%
1/129, LTPD=3%

,.
1/129, LTPD=3%·

MEMORY TECHNOLOGIES

The finished circuits are marked and then readied for
shipment.

critical for high resolution. The wafer is baked at a low
temperature to solidify the resist into gel. It is then exposed with a machine that aligns a mask with the new
pattern on it to a previously defined layer. The photoresist will replicate this pattern on the wafer.

The basic process flow described above may make
VLSI device fabrication sound straightforward, however,
there are actually hundreds of individual operations that
must be performed correctly to complete a working circuit. It usually takes well over two months to complete .
. all these operations and the many tests and measurements involved throughout the manufacturing process.
Many of these details are responsible for ensuring the
performance, quality, and reliability you expect from
Intel products. The following sections will discuss the
technology underlying each of the major process
elements mentioned in the basic process flow.

PHOTOLITHOGRAPHY
The photo or masking technology is the most important
part of the manufacturing flow if for no other reason than
the number of times it is applied to each wafer. The
manufacturing process gets more complex in order to
make smaller and higher performance circuits. As this
happens the number of masking steps increases, the
features get smaller, and the tolerance required becomes
tighter. This is largely because the minimum size of
individual pattern elements determine the size of the
whole circuit, effecting its cost and limiting its potential
complexity. Early MOS IC's used minimum geometries
(lines or spaces) of 8-10 microns (1 micron= 10 - 6 meter
== 1/25,000 inch). The n-channel processes of the mid
1970's brought this down to approximately 5 microns,
and today minimum geometries are less than 2 micrOns '.
in production. This dramatic reduction in feature size
was achieved using the newer high resolution photo
resists and optimizing their processing to match improved optical printing systems.

Negative working resists are polymerized by the light
and the unexposed resist can be rinsed off with solvents. Positive working resists use photosensitive
polymerization inhibitors that allow a chemically reactive developer to remove the exposed areas. The positive resists require much tighter control of exposure and
development but yield higher resolution patterns than
negative resistance systems.
. The wafer is now ready to have its pattern etched. The
etch procedure is specialized for each layer to be
etched. Wet chemical etchants such as hydrofluoric
acid for silicon oxide or phosphoric acid for aluminum
are often used for this. The need for ~maller features
and tighter control of etched dimensions is increasing
the use of plasma e.tching in fabrication. Here a reactor is run with a partial vacuum into which etchant gases
are introduced and an electrical field is applied. This
yields a reactive plasma which etches the required
layer.
The wafer is now ready for the next process step. Its
single journey through the masking process required
the careful engineering of mechaniCS, optics, organic
chemistry, inorganic chemistry, plasma chemistry,
physics, and electronics,

DIFFUSION
The picture of cleah room garbed operators tending furnace tubes glowing cherry red is the one most often
associated with IC fabrication. These furnace operations are referred to collectively as diffusiqn because
they employ the principle of solid state diffusion of mat·
ter to accomplish their results. In MOS processing, there
are three main types of diffusion operations: predeps,
drives, and oxidations.

A second major factor in determining the size of the circuit is the registration
oyerlay error. This is how ac l
curatelY one pattern can be aligned to a previous one.
Design rules require that space be left in all directions
according to the overlay error so that unrelated patterns
do not overlap or interfere with one another. As the error
space increases the circuit size increases dramatically.
Only a few years ago standard alignment tolerances
were ~ ± 2 microns; now advanced Intel processes
have reduced this dramatically due mostly to the use of
advanced projection and step and repeat exposure
equipment.

Predeposition, or "predep," is an operation where a
dopant is introduced into the furnace from a solid, liquid,
or gaseous source and at the furnace temperature
(usually 900-1200°C) a sattJrated solution is formed at
the silicon surface. The temperature of the furnace, the
dopant atom, and rate of introduction are all engineered
to give a specific dose of the dopant on the wafer. Once
this is completed the wafer is given a drive cycle where
the dopant left at the surface by the predep is driven into
the wafer by high temperatures. These are generally at
different temperatures than the predeps and are designed to give the required junction depth and concentration profile.
.

The wafer that is ready for patterning must go through
many individual steps before that pattern is complete.
First the wafer is baked to remove moisture from its surface and is then treated with chemicals that ensure good
resist adhesion. The thick photoresist liquid is then applied and the wafer is spun flat to give a uniform coating,
2-5

intel"

MEMORY TECHNOLOGIES

Oxidation, the third category, is used at many steps of
the process as was shown in the process flow. The temperature and oxidizing ambient can range from 800 to
120QoC and from pure oxyge[l to mixtures of oxygen
and other gases to steam depending on the type of oxide required. Gate oxides require high dielectric breakdown strength for thin layers (between .01 and .1 micron)
and very tight control over thickness (typically ± .005
micron or less than ± 1/5,000,000 inch), while isolation
oxides need to be quite thick and because of this their
dielectric breakdown strength per unit thickness is much
less important.

vacuum and are accomplished by vaporizing the metal
with a high energy electron beam and redepositing it on
the wafer or by sputtering it from a target to the wafer
under an eiectric field.
Chemical vapor deposition can be done at atmospheric
pressure or under a moderate vacuum. This type of
deposition is performed when chemical gases react at
the wafer surface and deposit a solid film of the reaction product. These reactors, unlike their general industrial 'counterparts, must be controlled on a microscale to provide exact chemical and physical properties
for thin films such as silicon dioxide, silicon nitride, and
polysilicon.

The properties of the diffused junctions and oxides are
key to the performance and reliability of the finished
device so the diffusion operations must be extremely
well controlled for accuracy, consistency and purity.

The fabrication of modern memory devices is a long,
complex process where each step must be monitored,
measured and verified. Developing a totally new
manufacturing process for each new product or even
product line takes a long time and involves significant
risk. Because of this, Intel has developed process
families, such as HMOS, on/which a wide variety of
devices can be made. These families are scalable so
that circuits need not be totally redesignedJo meet your
needs for higher performance. 1 They are evolutionary
(HMOS I, HMOS II, HMOS III, CHMOS) so that develo~
ment time of new processes and products can be reduced without compromising Intel's commitment to consistency, quality, and reliability.

ION IMPLANT
Intel's high performance products require such high accuracy and repeatability of dopant control that even the
high degree of control provided by diffusion operations
is inadequate. However, this limitation has been overcome by replacing critical predeps with ion implantation.
In ion implantation, ionized dopant atoms are accelerated by an electric field and implanted directly into the
wafer. The acceleration potential determines the depth
,to which the dopant is implanted.

The 'manufacture of today's MQS memory devices requires a tremendous variety of technologies and manufacturing techniques, many more than could be mentioned
here. Each requires a team of experts to design, optimize, control and maintain it. All these people and thousands of others involved in engineering, design, testi[lg
and production stand behind Intel's products.

The charged ions can be counted electrically during implantation giving very tight control over dose. The ion
implanters used to perform this are a combination of
high vacuum system, ion source, mass spectrometer,
linear accelerator, ultra high resolution current integrator, and ion beam scanner. You can see that this important technique requires a host of sophisticated technologies to support it.

Because of these extensive requirements, most manufacturers have not been able to realize their needs for
custom circuits on high performance, high reliability processes. To address this Intel's expertise in thjs area is
now available to industry through the silicon foundry.
Intel supplies design rules and support to design and
debug circuits. This includes access to Intel's n-well
CHMOS technology. Users of the foundry can now
benefit from advanced technology without developing
processes and IC manufacturing capability themselves.

THIN FILMS
Thin film depositions make up most of the features on
the completed circuit. They include the silicon nitride for
defining isolation, polysilicon for the gate and intercon-·
nections, the glass for interlayer dielectric, metal for interconnectionand external connections, and passivation layers. Thin film depositions are done by two main'
methods: physical deposition and chemical vapor deposition. Physical deposition is most common for depositing metal. Physical depositions are performed in a

1 R. Pashley, K. Kokkonen, E. Boleky, R. Jecmen, S. Liu, and W.
Owen, "H-MOS Scales Traditional Devices to Higher Performance
Leve!," Electronics, August 18, 1977.

2-6

RAMs (Random
Access Memories)

INTEL CORPORATION. 1980

3-1

I
I

AP-74
which controls the write function. Separate data
input and output are available. Logical operation
of the 2147H is shown in the truth table. The
output is in the high impedance or three-state
mode unless the RAM is being read. Power
consumption switches from standby to active
under control of CS.

MEMORY ARRAY
64 ROWS
64 COLUMNS

4096 x 1 BIT
2147H
PIN CONFIGURATION
Vee

Ao-All ADDRESS INPUTS

DOUI

PIN NAMES

LOGIC SYMBOL

WRITE ENABLE
CHIP SELECT

Figure 2. 2147H Logic Diagram

SLOW DESelECT, FAST SELECT
SLOW DESELECT, FAST SELECT
FAST DESELECT, FAST SELECT
FAST DESELECT, FAST SELECT

Figure 3. 2147H Block Diagram

Internal structure of the 2147H is shown in the
block diagram of Figure 3. The major portions of
the device are: addresses, control (CS and WE), the
memory array and a substrate bias generator,
which is not shown.
The memory is organized into a two-dimensional
array of 64 rows and 64 columns of memory cells.
The lower-order six addresses decode one of 64 to
select the row while the upper-order six addresses
decode to select one column. The intersection of
the selected. row and the selected column locate the
desired memory cell. Additional logic in the
column selection circuit controls the flow of data
to the array and as stated in the truth table, WE
controls the output buffer.
As shown in Figure 4, the first three stages ofthe
address buffer are designed with an additional
transistor. In each stage, the lowest transistors
are the active devices, the middle transistors· are
load devices, while the upper transistors, con:
trolled by

0
D ..
0 .. . . .
0 ..

<::::> = .11'1 CERAMIC CAPACITOR

<::::>

0
0
0
0

<::::>

Figure 18. Decoupling

NOISE WITHOUT GRIDDING AND ONE DECOUPLING
CAPACITOR PEA 4 RAMS

GRIDDING AND ONE DECOUPLING
CAPACITOR PER 2 RAMS

Figure 19. Vee Noise With & Without Gridding

3·9

.r\

20 mV/DIV

AP-74
trace will have transmission line characteristics.
A simplified circuit is shown in Figure 20.

= LOAD CAPACITAN,CE

C'EFF-:=Cl

teo

Dependent on the values ofR, Land C,.there are
three cases shown in Figure 21. In case I, rise and
fall times are excessively long. In case III, the
current smoothly and clearly changes, while in
case II, the current overshoots and rings. If
ringing is severe enough, the voltage can cross the
threshold voltage of the device as in Figure 22.

'Figure 20. Signal Equivalent Circuit

MOS RAM input is essentially capacitive.
Simplifying the capacitance and writing the
differential equation.
() = Ldi +
dt

~dt

CJ'

The solution of this equation is:
i = K,e-r,t+K2e-r2t
where:
'

Figure 22. Access Push·Out Due

r, = R + j R2_1.
2L
4L2 LC
r 2 =R.
- J_
R2_ 1
2L
4L2 LC
K, = constantK2 = constant
CASE

FACTOR

GRAPH

Ringing

Effective access is stretched out until the wave
form settles. System access is the settling time
(~t) plus the specified device access. Case III is the
ideal case but in reality a compromise between
case I and case II is used because parameters vary
in a production environment. Enough series
resistance is inserted to prevent ringing but not
enough to significantly slow down the access. A
series resistance of 330 provides this compromise.
The exact value is determined emperically but
330 is a good first approximation.

SERIES TERMINATION/
PARALLEL TERMINATION
LC

Figure'23. S_eries,and Parallel Termination

R'
4L 2

CRITICALLY DAMPED

Figure 21.·Three Cases of Equation Solution

Series termination uses one resistor and consumes
little power. Current through the resistor creates a
voltage ·differential shifting the levels of input
voltage to the devices slightly. This shift is usually
insignificant because the 2147H has an extremely
high input impedance.
Termination could also oe accomplished by a
parallel termination as shown, in Figure 23.

3-10

AP-74
Parallel termination has the advantage of faster
rise and fall times but the disadvantage of higher
power consumption and increased board space
usage.

SYSTEM DELAYS
RAMs are connected to the system through an
interface, comprised of address, data and control
signals. Inherent in the interface is propagation
delay. Added to the RAM access time, propagation
delay lengthens system access time and hence system cycle time. Expressed as an equation:

Figure 24A.

tsa = tia + tpd
where:

taa = system access time

t d, = device access time
tpd = propagation delay
Device access is a fIxed value, guaranteed by the
data sheet. System efficien~y then, is a function of
system access and can be expressed as:
E ff = tda/ tsa
where: Eff = System Efficiency
This can be reduced by substitution for tsa to:
Eff = 1/(1 + tpd/tda)

<~-----_I~-START CYCLE
(REO)

Figure 27. System Timing

Figure 28. System Block Diagram

the address and control lines are perpendicular to
the data lines which minimizes crosstalk. Second,
troubleshooting is simplified. A failing row of
devices indicates a defective address or control
driver; whereas a failing column indicates a faulty
data driver.

control signals are coincident with the start of the
cycle. Access is not yet specified because it is
af:(ected by device access and the unknown
propagation delay. Access will be determined in
the design.
Figure 28 illustrates the elements of the system in
block diagram form. Addresses are buffered and
latched at the input to the printed circuit card.
Once through the latch, the addresses split to
perform three functions: board selection, chip
select (CS) generation, and RAM addressing.
Highest order addresses decode the board select,
which enables all of the board logic including CS.

SYSTEM DESIGN
Using previously discussed rules and guidelines,
the design of a typical high speed memory will be
reviewed to illustrate these techniques.
Configuration of the system is a series of identical
memory cards containing 16K words of 16 bits.
Timing and control logic is contained on each
board. System timing requires an 80 ns cycle as
shown in Figure 27. Cycle operation begins when
data and control signals arrive at the board. In
this design, addresses are shifted 30 ns to be valid
before the start of the cycle so that address, data,
and control arrive at the memory device at the
same time for maximum performance. Data and

Next higher order addresses decode CS, while the
lowest order addresses select the individual RAM
cell. Data enters the board from the bidirectional
bus through a buffer/latch, while output data
returns to the bidirectional bus via buffers. Only
two control signals - cycle request (MEMREQ)
and wnte (WR) control the activity on the board.
Figure 29 illustrates the levels of the delay in the

r
Figure 29. Worst Case Delay Path

system. Data and control have only one level. But
examine .the address path, it has three levels.
Addresses are decoded to activate the logic on the
board, select the row of RAM to be accessed and
finally locate the specific memory cell. C8 is in this
address path and is crucial for access; without it
RAM access cannot begin. But this path has the
most levels of decoding with associated
propagation delays. Consequently, the address
path to C8 is the critical path and has the greatest
effect on system delay and hence must be
minimized.
Examination of the system begins with the C8
portion of the critical path, followed by addresses,
data path, and finaily timing and control.

allows addresses to pass independent of any clock.
Delay time is measured from the signal rather
than· a clock. The Intel® 3404 is a high speed, 6-bit
latch operating in a flow-through mode with 12 ns
delay. This is acceptable but a faster latch can be
fashioned using a 2-to-lline multiplexer, either a
748157 or a 748158. The slower of the two is the
748157 with 7.5 ns delay. Although the 748158 is
faster with 6 ns delay, it requires an extra inverter
iIi the feedback path as shown in Figure 30. Between the 748157 and the 748158 latches, the trade
off is speed against board space and power. Individual designers will choose to optimize their
designs.
74504

CRITICAL PATH
Analysis of the critical path begins with the
address latch. The first decision to be made is to
the latch type. Latches can be divided into. two
types: Clocked and flow-through. Clocked latches
capture the data on the leading or trailing edge of
the clock. Associated with the clock is dataset-up
or hold-time that must be included in the delay
time. Accuracy of the clock affects the transit time
of the signal because any skew in the clock adds to
the delay time. As an example, a typical 748173
latch has a data set-up time of 5 ns and a
maximum propagation delay time from the clock
of 17 ns. Total delay time is 22 ns, excluding any
clock skew.
Flow-through latches have an enable rather than
clock. The enable opens the address window and

t)UTPUT

INPUT ------+---t~

Y4 OF 745158

tpo INPUT·OUTPUT
Ipo LATCH·OUTPUT

Figure 30. Fast Latch

3-14

MIN
2 ns
4 ns

MAX
6 ns
12 ns

AP-74
In either case, care must be exercised in
constructing the latch. Output data must be fed
back to the input having the shortest internal path
-' the A input. If the latch is constructed with the
output strapped to the B input, the input could be
deselected and the feedback loop not yet selected
because of the delay through the internal inverter.
In this situation data would be lost. Additional
delay through the external inverter (74S04) aids in
preventing data loss. Inverting addresses has no
system effect - except that it's faster than the
non-inverting latch. During a write cycle,. data
will be stored at the compliment of the system
address .. When this data is to be retrieved, the
same address will be complimented, fetching the
correct word.
.

a true input, defi"ning the output from the Board
Select decoder.
.
In the Board Select decoder, the high order adresses are matched to hard-wired logic levels
generated with switches for flexibility. Changing
a switch setting shifts the 16K range of the board.
Comparison of the switch setting and the address
can be accomplished with an exclusive-OR, a
74S86. NANDing all the exclusive-OR outputs will
generate a Board Select signal. Unfortunately,
this signal is active-low, requiring an additional,
inverter as in Figure 32A, and it also consumes
22.5 ns to decode. An MSI solution to board
selection is a 4-bit comparator - 74S85 - which
+Vcc

MAX PROP DELAY = 11.5 ns

The remaining eleinents in the critical path to be
designed are board selection and CS decoding. To
minimize the CS, decode path, the easiest method
is to work backwards from CS. In this manner input sig~als to a stage are determined and the
output from the preceding stage is defined. This
saves inserting an inverter at the cost of 5 ns to "
generate the proper input to a stage.

"!:::::'
'\
r-:::::'
r--

'\.

=
===f\.
I

---4r

Starting with theCS driver, the design analyzes
several approaches to select the fastest one. With
four rows of devices, there are four CS signalsto be
generated. A 2-to-4line decoder like the 74S138 is a
possible solution. It is compact, but has two
detriments: long propagation delay and
insufficient drive capability. Propagation delay
from enable is 11 ns. Enable is driven by board
selection which arrives later than the binary
inputs. Splitting the RAMs into two 4x8 arrays
eases the drive requirement but the demultiplexer
must still drive eight devices at 5 pF each - or40
pF total- which adds 1.75 ns to the delay. More
importantly, signal drive is required to switch
cleanly and maintain levels in spite of crosstalk
and reflections. A 74S240 buffer will solve this but
in the process consumes an additional 9 ns.

A second and preferred' approach is to use a discrete decoder to decode and drive the CS sigrlals.
Four input NAND buffers - 74S40 - fulfill this
function. AddressesAl~ 'and A13 are inverted via
74S04, providing true and compliment signals to
the buffer for decoding. ~s shown in Figure 31, the
delay is 11.5 ns.~~opagation delay for the 74S40 is
specified into a 50 pF load, eliminating the
additional loading !ielay. Left and right driversCSXL and CSXR - are in the same package to
minimize skew petween left and right bytes of
data. All of the 'decoders are enabled by Board
Select to prevent rows of devices on several boards
from being simult!lneously active. Board Select is
.(

3-15

CS Decode

~:~~g~ m~~ 1~:~!2.~6!1~:~:':~:

Figure 32B. Board Select

AP-74
consumes less board area and propagation delay
is improved at 16.5 ns.
, The best solution is attained by invertingthe high
order addresses to generate true and compliment
signals. the appropriate signal is connected into a
74S260, 5·input NOR. With an active· high output,
maximum delay is 11 ns as in Figure 32B.
Critical path timing is the sum ofthe latch, Board
Select, and CS delay times. In this example, latch
delay is 6 ns, Board Select is 11 ns and CS decode is
11.5 ns for a total of 28.5 ns. One additional delay
- trace delay - must be included for a complete
solution. Each 74S40 drives eight MOS inputs
having 5 pF/device for a load of 40 pF. Trace
capacitance is calculated on 5 in. of trace. At 1.5
pF/in., trace capacitance is 7.5 pF. Trace delay
calculated from equation 3 is 1.9 DS.
tpl = 1.8 ns x 5 in.
- f t - 12 in.lft
1 + 40 pF
tpl= 1.9 ns ' "
. ,7.5 pF
Total worst case maximum critical path delay has
been calculated to,be 30.4 ns(28.5 ns + 1.9 ns). With
the addresses shifted in time by an amount equal
to the worst case delay, device and system cycle
start are coincfdent. Start of system access and
device access differ only 0.4 ns when the addresses
are shifted 30 ns. From the system cycle start,
access is stretchid by 0.4 ns as shown in Figure 33. '
Thus, with a 35 ns 2147H-l, data is valid at the
output of the device 35.4 ns after the start of the
cycle.
'

From address change, the maximum delay in the
critical path is 30.4 ns while the minimum is 10.9
ns. The difference between these two times is skew
and will be important in later calculations.

ADDRESSES
Lower order addresses (Ao-Au) arrive at the devices earlier than' CS because they are not
decoded. Consequently, the address drivers do not
have a critical speed requirement. Once through
the 6 ns latch, addresses have 24 ns to arrive aUhe
devices.
While speed is not the primary prerequisite, drive.
capability is. Address drivers are located in the
center ofthe board, dividing the array into two sections of 32 devices each. For the moment, assume
one driver drives 32 devices as in Figure 34A. Each
device is rated at 5 pF linput, resulting in a load of
160 pF. In addition, there are four 5-in. traces one for each row. twenty inches of trace equates to
30 pF. Total capacitiv6load is 190 pF. A 74S04 is
specified at 5 ns delay into 15 pF. The.increased
capacitive load is 175 pF, which at 0.05 ns/pF increases the delay by 8.75 ns~ Under these conditions the worst cast driver relay is 5 ns plus 8.75 ns,
totalling 13.75 ns. It is 10 ns earlier tlian the 24ns
available.
'
I

ADDRESS

10.9ns

....- - _ 3 0 . 4 n 8

....- - - 3 0 " ' ---)~

Figure 33. CS Decode Time

The minimum delay also must be calculated. With
addresses valid prior to the start of the cycle, CS
decoding can start in the previous cycle. If it
occurs too soon, the previous cycle will not, be
properly completed. Minimum delay time is the
sum of the minimum propagation delays plus
capacitive loading delay plus trace delay.
Capacitive loading delay is less than 0.4 ns and
ignored. Minimum delay through the TTL is 9 ns,
and added to trace delay results in a total of 10.9
ns.

Figure 34A. Address Driver .

The first impression is that this is sufficient, but
the effect of crosstalk must be considered. For
example, as shown in Figure 35, each trace has
, inductance, and parallel traces take on the

3-16

AP-74
can sink 20 rnA, inducing a transient in an
adjacent trace. If the adjacent signal is switching
to a one level, only 400 pA of a source current from
the driver is available. The induced current will
generate a negative spike, driving the signal at a
one leval negative. Additional time of! 0 to 15 ns is
required to recover and re-establish a stable one
level. This may prevent stable address at the start
of the cycle. Recall:

characteristics of transformers. When a signal
switches from a one level to a zero level, its driver

, LO

i= C ddv or dt = C d.v
t

where: i = itistantaneous current
C = capacitance
dv
'
- = voltage time rate of change
dt
LO

The terril dvI dt can be maximized by increasing i
or decreasing C. Current can be doubled by using a
driver like a 748240, but it draws 150mA supply
current. In a large system the increased power is a
disadvantage because it requires a larger power
supply and additional cooling.
A better alternative is to reduce the capacitance,
wh~ch results in a corresponding increase in dv/dt
for quick recovery. 8plitting the loads to i6 devices
reduces the capacitance and allows a low power
driver, like a 74804, to be used, as in Figure 34B.
This has the double effect of decreased propagation delay and providing sharp rise and fall times.
Now, there are only 10 in. of trace or 15 pF load and
16 devices, representing 80 pF for a total of 95 pF.
Again, the 804 delay is 5 ns into 15 pF, but the
stretched delay due to 80 pF is, only 4.0 ns for a
total of 9.0 ns. 8table 'addresses are guaranteed at
the start of the cycle.

Figure 34B. Address Drivers

Figure 35. Cross Talk

DATA PATH

ADDRESS

SLOWes

Next in line for analysis is the data path.
Reference to the system block diagram shows that
the data is latched into the board on a write cycle
and buffered out during a read cycle. Data latches
are constructed from 748158 quad two-input
multiplexers. Because the data bus is I
bidirectional, 748240 three-sta~e drivers are used
for output buffers.
All that remains to complete the board access com- ,
putation is the calculation of the output propagation delay. Output delay of the active RAM is
caused by the capacitance loading of its own output plus the three idle RAMs, the input
capacitance of the 748240 bus driver and trace
capacitance. Output capacitance of the 2147Hs is
6 pF/device for a subtotal of 24 pF; input
capacitance of the 748240 is 3 pF and trace
capacitance of a 5-in. ,trace is 7.5 pF. total load

\':::k-+__-----'x t
WE

~'---------',r---FI--

Figure 36B. RaCe Condition Between Address and WE

3-17

I
I

AP-74
capacitance is 34.5 pF, and access time of the
2147H is specified driving a 30 pF load. Calculated
loading is close enough to the specified loading to
eliminate any significant effect on the access
calculations. Had there been a difference, the
effect would have been included in the calculation.
As previously calculated, transit time of the trace
is 1.6 ns. Adding this to the 7 ns'delay through the
74S240 bus driver results in an 8.6 ns, output
propagation defay from the RAM output to the
bus.
, f
Total access is 35Ans plus 8.6 ns output delay for a
total access of 44 ns. The efficiency of this system
is:
35
'
Eff = 44 or 80%

Figure 36B shows the proper operation controlled
with timing.
Finally, the data output buffers, controlled by.
timing signals, are enabled only during a read
. cycle while the board is selected preventing bus
contention with two or more boards in the system.
More importantly, timing' disables the output
prior to the start of the next cycle, allowing input
data to be stabilized on the bidirectional data bus
in preparation for a write cycle.

TIMING GENERATION
Having discussed the philosophy of timing and
control, we can now focus on the specifics of
address latching, write pulse 'generation and
output-enable timing. To perform these functions
timing can be generated from one of three sources:
clock and shift register" monosta ble
multivibrator, or delay line.

TIMING AND CONTROL
Timing and control gating regulates activity on
the board to guarantee operation in an orderly
fashion. This gating latches addresses, controls
the write pulse width and enables the three·state :
bus drivers. In addition, accurately generated
timing compensates for skew, effects. .
In anti~ipation' of the next cycle, the ,latch must be
opened for the new address. When ,the current
cycle has completed 50 ns, the latch~s are again
opened~ The next cyCle might not begin 30 ns after
the latch is opened because the system may skip
one or more memory cycles. Therefore, a signal
from the next active cycle must close the latch. In
,operation, a buffered Memory Request sign~l
latches the addresses.
'
The write pulse is controlled to guarantee set-up
and hold times for data and address and to
prevent an overlap of CS and write enable from
different cycles:To understand the consequences,
consider the followinl! examole.
Assume two memory banks, one has a minimum
es and the other has a maximum delay path iIi
es, and both have a minimum address delay.
Assume that WE is a level generated fro~ a write
command as shown in Figure 36A. The,operation
, under examination is a write cycle into the bank
with fast CS followed by a read cycle into the bank,
with slow CS.
.
Both the write cycle and the read cycle have device
specification violations. In the write cycle, the ad·
dresses change prior to CS and WE becoming
inactive; that new address location may be written
into. In the read cycle, the address change is
correct but WE is still active and the fast CS .
be/rins too soon, performing a non·existent write
cycle.. Clearly, controlling the width of WE will
solve the problems.

CLOCKED SHIFT REGISTE,R
A clocked shift register' circuit is shown in Figure
.37 consisting of a D·type flip flop and an 8·bit shift
register.
. . . - - - - , MEM~L_ _ _ __

I
CLK...JIlJ"lSl.J[ ,

-I

I+-

LATENCY

Figure 37. D Flip.Flop and Shift Register

On the leading ed~e ofMEMREQ, the Q output of
the D flip flop is clocked to a one state, enabling, a
"one" to be propagated through the shift register.
The one is clocked into the first stage of the shift
. register on the first clock edge after the A andB
inputs are "ones". After the clock, the output QA
goes true which subsequently clears the D flip flop,
clocking zeros'into the register to create a pulse
one clock period wide.
The accuracy and repeatability depends primarily
'on the accuracy and stability of the clock. Crystal
clocks can be built with +0.005% tolerance and less
than a 1% variation due to temperature.

3·18

An inherent difficulty is the synchronization of
Memory Request and the clock. At times there will
be a latency of one clock cycle between Memory
Request and the actual start of the cycle when
Memory Request becomes active just after the
clock edge. Assuming an 80 ns cycle and 20 ns
clock, the latency can be 20 n,s or 25% of a cycle
stretching both access and cycle accordingly. A
second. difficulty of this circuit is caused by the
asynchronous nature of the clock and the Memory
Request. The request becomes act;ive.just prior to

AP-74
the clock and the set-up time of the latch is
violated, the output QA "hangs" in a quasi-digital
state and could double or produce an invalid pulse
width; this and the latency hinder effective use in
high speed design.

generators. The leading edge travels down the
delay lines. When the edge reaches the 25ns tap,
the output is inverted and fed back to the R input of
the R-S flip flop, shaping the pulse to width to 25
ns. Twenty-five nanoseconds was chosen to match
as close as possible the write pulse width. A 25 ns
pulse limits the Memory Request signal width to
less than 25 ns to insure proper operation.
Otherwise, the R-S flip flop will not' clear until
Memory Request returns to a one level. As the
pulse travels down the delay' lines, it acquires
.additional skew of ±1 ns per delay line package for
a total of 6 ns overall. Figure 38 shows several
timing pulses andthe uncertainty of each edge calculated by worst case timing analysis. The
remaining prol>lem is selection oftiming edges to
operate the device. Now that the timing chain is
completely defined, specific details of the address
latch, write 'pulse and output enable can be
completed.

MONOSTABLE MULTIVIBRATOR
The second possible timing generator is a series of
monostable multivibrators, using a device such as
the AMD Am 26S02 multivibrator. It has a
maximum delay from input to output of 20 ns and
an approximate minimum of6 ns. However, with a
delay of 20 ns, the monostable multivibrator offers
no advantage over the clocked generator. Having
a minimum pulse width of 28 ns, the one-shot
offers no improvement over the 50 MHz clock, but
in fact the performance is worse because it is more
temperature .and voltage sensitive. The pulse
width is dependent on the RC network composed
of resistors and capacitors that are temperature
sensitive. Consequently, repeatability leaves.
somethin,g to be desired.

ADDRESS LATCH TIMING
An R-S flip flop activated by MEMREQ latches
the addresses. A second signal which we will now
calculate is used to open the latch. This signal has
two boundaries. If the latch opens too late, the
access of the cycle will be extended; if it opens too
soon, the current cycle will be aborted. Skew
through the R-S flip flop is 1.75 ns to 5.5 ns and
skew in the latch from enable to output is 4 ns to 12
ns for a total skew of 6 to 17.5 ns. With this skew
added to the 30 ns address set-up time, the latch
opening signal must be valid at 36 ns best case or

DELAY LINE
The third and best choice is a delay line. This
design uses STTLDM-406 delay lines from EC2
with tapped outputs at 5 ns increments. In
operation, Memory Request activates an R-S flip
flop fabricated from cross coupled NAND gates.
The output of this circuit starts the memory cycle.
Consequently, the cycle starts 5 ns after Memory
Request compa~ed to 20 ns for the other two timing

Figure 38. Timing Chain

3-19

AP-74·
47.5 ns worst case prior to the start of the memory
, cycle. Each cycle is 80 ns long, therefore, the latch
opening signal must begin 44 ns or 32.5 ns,
respectively, in the preceding cycle. From the·
delay line timing diagram, T35 will satisfy the
worst case requirements for opening the latch and
T 25 best case. In production, each board is tuned
by selecting T25, T30, or T3p to open the latch,
guaranteeing it opens between 35 and 30 ns prior
to the start of the cycle.

to 8 ns. Subtracting 8 ns from 50, ns sets the
termination of the write timing edge at 42 ns.
Using the inversion of T25 will end the write pulse .
at 43 ns with 7 ns to spare.
Data set-up time is guaranteed because data is
valid 6 ns (the worst case delay through the latch)
after the start of MEMREQ.

OUTPUT ENABLE TIMING
There is a 5.5 ns delay through the address driver
providing minimum device cycle of 50 ns. As a
result the earliest data can disappear from the bus
is at 54 ns because of delay through the output circuit. To select the timing tap for the output enable,
the skew of the enable circuit is 'subtracted from
the system access time.

WRITE PULSE TIMING
The next timing to be calculated is the write pulse.
Figure 39 shows the three parameters which
define the write pulse timing: data set-up time,
write pulse width and write recovery time. Data
set-up is assured by having data valid through
the entire cycle.
I WR

ADDRESS

------------~------~·I~---

DA~A)·_ _ _ _....JI'-------t_---"I'--

Figure 39. WE Constraints

Subtracting the 28. ns skew of the buffer enable circuit from the 44 ns access time of the system shows
that the latest the timing edge can occur is 16 ns,
.which is satisfiEld by edge TW. -The trailing edge,
however, ends at 37 ns and with minimum propagation delays the bus would become three-stated
at 44 ns, coincident with data becoming valid.'
ORing T20 with TW will guarantee the output is
valid until 54 ns, minimum. Selecting a timing gap
between T35 and T50, depending on the
propagation delay in the enable circuit, disables
the output at 70 ns, allowing input data to be valid
for 10 ns prior to start of cycle. The complete
~chematic is shown in Figure 40.

SUMMARY

Placement of WE in the cycle is controlled by
address change to comply with tWR. From
previous calculations th~ earliest addresses· can
change is 50 ns, which defines the end of the WE
signal. Our calculations begin at the· device and
work back to the timing edge. Eight devices
constitute a 40 pF load and a 74S40 is specified for
. a 50 pF load, reducing delay by 0.5 ns when
driving 40 pF. Trace delay l'!nd 74S40 delay is 3.5

The 2147H is an easy-to-use, high speed RAM. The
problems in a memory system design are the result
of inherent limitations in interfacing. Largest of
these is skew, which the designer must strive to
minimize. In this example, skew consumed 45 ns
of an 80 ns cycle while device access time was
extended by only 10 ns, resulting in an 80%
efficiency.

T45~r'--'I~I........,II
IIII

Figure 40. 16K X I6-Bit High Speed Static Memory

25 ns DELAY LINES
STTLD m 406

16-bit address words onto eight address input pins. The
two 8-bit address words are latched into the 2164A by
the two TTL level clocks: Row Address Strobe (RAS)
and Column Address Strobe (CAS). Noncritical timing
requirements allow the use of the multiplexing technique while maintaining high performance.

1. INTRODUCTION
The Intel® 2164A is a high performance, 65,536-word by
I-bit dynamic RAM, fabricated on Intel's advanced
HMOS-D III technology. The 2164A also incorporates
redundant elements to improve reliability and yield.
Packaged in the industry standard 16-pin DIP configuration, the 2164A is designed to operate with a single
+ 5V power supply with ± 10010 tolerances. Pin 1 is left
as a no-connect .(N/C) to allow for future system upgrade to 256K devices. The use of a single transistor cell
and advanced dynamic RAM circuitry en'ables the
2164A to achieve high speed at low power dissipation.

The 2164A is the first commercially available dynamic
RAM to be manufactured using redundant elements and
also features single + 5V operation, low input levels
allowing -2V overshoot, a wide tReD timing window,
low power dissipation, and pinout compatibility with
future system upgrades. These features make the 2164A
easy and desirable to use.

3. DEVICE OPERATION
3.1 A~dressing
A block diagram ofthe 2164A is shown in Figure 2. The
storage cells are divided into four 16,384-bit memory arrays. The arrays are arranged in a 128-row by 128column matrix. Each array has 128 sense amplifiers connected to folded bit lines.

2. DEVICE DESCRIPTION
The 2164A is the next generation high density dynamic
RAM from the 2118 +5V, 16K RAM. Pin 1 N/C provides for future system upgrade of 64K to 256K sockets.
The 2164A pin configuration and logic symbols are
shown in Figure 1.
.

Figure 3 depicts a bit map of the 2164A and also shows
the Boolean equations necessary to enable sequential
addressing of the 16 required address bits (Ao-AJ5)'
There is no requirement on the user to sequentially address the 2164A; the bit map and Boolean equations are
shown for information only.

Sixteen bits are required to address each of the 65,536
data bits. This is accomplished by multiplexing the

c-;;:;:;--===--,
~;~~:::::~:STAoaE
POWEllt+5VI

Figures 1 & 2. Intel 2164A Pin Assignments and Block Diagram
3-23

Ap·131

INPUT
ADDRESS
TOPOLOGICAL
ADDRESS
2164A

00001001
11001001
01001001
10101001
00101001
11101001
0110.001
10011001
00011001
11011001
010'1001
10111001
00111001

"",00'

10000101

"
. 2164A
ADDRESS
PIN

PROGRAMMED
ADDRESS

ROW

ROW ADDRESS
SCRAMBLING

RAO

NOTE: Bit Map can be determined
from Addre~s Map equations.

RA'
RA2
RA3
RA4
RAS
RAS
RA7
COLUMN
CAO
CA'
CA2
CA3
CA4
CAS
CAS
CA7

AOR
A'R
112R
A3R
A4R
ASR
ASR
A7R

A'R
A2R
A7R
A7R
A7R
A7R
A7R

,..

'""

10001101
11001101

00'01101
1110"01
0110,101

'0011101
000,,101

0111110'
100000"
00000011
11000011
01000011
00100011
,11100011
10010011
00010011
ttOl0011
01010011
00110011
11110011
00001011
"0010"
01001011

Iii! i i I
10000111
00000111
"000'11
01,000111
00100111
11100111
01100,111

01110111
10001111
00001111
11001111

01010111
10110111
00110111

ACo

"
m
'"
"'"
'"
"".

11010101
01010101
10110101

01100101

000.0111

AC7
ACS
ACS
AC4
AC3
AC2
AC'

10101111
00101111
10011111
00011111
11011111
00111111
11111111
011111"

COLUMN!

113

ADDRESSES

'"
,'"
'"
"
'"'"
,
"
"
'"

.".
.
.

"'"
'"
"
"

..."'"
"'"'"
'"
'"
'""
'"
"'"
"'"
"'
'"
m

1111111111111111111111111111
"'1111,1122222222223))333 333 3~ 4 4 ~ 4~ ~ ~ 1 ~ 5 5$5 5 5 5 5 558 8e~ 1116881' 1 " " 11 1 11181 '.'II~~ 9 ' 9 ' Dill DOO 00 0000 00 11' 11,11 1 1 122222222
0123451'.101231511111012345111101234511111012345618110123451111012345811'0123'II'8'0123451,.tOI234561"012345I'1110123451'1110123451'

~A1 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 000000000000000000000000000000000

INPUT
ADDRESS

COLUMN ADDRESS
SCRAMBLING

11000101
0100010.
10100101

0 0 0 00 0 0 0 0 00 0 0 0a 0 00 0 00 a a 0 0 0 0 00 0 0 0 0 0 0 00 0 a 0 0 0 0 0 00 0 0 a 00
1lA1,'1,1!I'1111'111,""11'I",'lll'"111",,',1111,,I,1111111111110000000000000000000000000000000000000000000000000000000000000000
~"$ 000000000000000000000000 DC 0 00 0 0 01 j 1 1111 1 I"
1 1111 1 , 1 11111 1 1 1 " , l I e 0 0 0 0 0 a 0 0 0 0 0 Q 00 DOC 0 0 0 0 0 0 0 0 0 0 0 0001' 1 11 1 11 1 \ 11 1 1 1 " , 11 1 1 1 1111'1 11 "

::; ~~g~~~g~~~~~~~~~ri~~~~~6~: i i::::: g~~g~~g~~~~~~~~~ ~~~~!ri~~:::::::: ~~~~~g~g~~~~~~~~~~~!~!~~::::::: :ggg~g~gg~~~~~~~~~~~~~~~~:::l::::

:! H!!l; H~n~l iHH!!i 1f~ ~~ ;!l 1HH!!ll ~ ~H!! i1HH!H 1H~ ~!! II H~~! !ll ~H~ rlll i ~H!!! 1HH!! II iH ~!!ll HH: ~ ii Hi~: ~ i1HH!!i: ii

DECIMAL
EQUIVALENT
~.r---------~------------------~--------------------------~--~~---ROWADORESSES

C835

Figure 3. Intel® 2164A Bit Map

3:24

Ap·131

ROW A D D R E S S E S - - - - - - - - - - - - - -

---~

",1111""'1"""'1111""",11111",\1"',1"",111111111111'1'1"111222222221122222122221222211222211222.22222222222222222222
ZI333331333S4444444444~!'lil'ISSI"'I •• a e ' 7 " " ' J , ' 7 1 " • • • • • • • • • 811 •• 111.0000DOOOOOI1111111112222222222233323U3Z.' •••• "USSISII
• I 0 1 234 S' 7., 0 I 2 Z. I . , •• 0 1 23. II r I I 0 I 2 I • S 1'1.0 I 2 I 4 S I , •• 0' 2 3. S' 7. I 0 1 2 3' S I , . t 0 1 2 3 4 5., I . Q 1 2 3' 5 I ' " 0 , ~ 3 4 I I ' I II 0 I 2 3 • 5 I ' I I 0 I 2
5 Ii , . /I 0 I Z ) I 5

"'111111111111111111111111111111111111111111111111111"11111111111"111111"IIIIIIII""1111In'1I"l1""1'1III""11111111111RAl
1I0DOOOOODOOOOOOOOOOOOOOO(l"OOOOODOOOOOODOOOOOOOOOOOOOli000000000000"1""" " " " " ' " 11111111111111111111111111111111111111",1"
11M
,111""""1",1',111111",'111,000000000000000000000000000000001"1"",,11,',,1,111111,,,',1,,000000000000000OOOOOOOOOoDOooOOORAS
111',,""',111100000000000000001111111,,1111'1100000000000000001'1'1""'1"1"000000000000000011""111"111"OOOOOOOOOOOoDODORA4
'11","0000000011'111"000000001"'11'100000000"""1'00000000'111"110000000011""1'00000000""'1'10000000011111111000000UAA3
11110000111100001111000011110000111100001111000011110000'111011001111000011110000111100001111000011110000111100001I'IOOoOll"0000!l.fo2
00,11100001,1'0000,11100001',10000',',00001,,1000011,10000',"0000,1110000111100001111000011,100001111000011II00001,,10000111100RIII
0,,0011001100110011001'00110011001'001'001'00110011001100110011001'00110011001100110011001100110011001'0011001100110011001100110RAO

11111111111111111 I 11111111111,1",1111111111 I I I I 111'1111111111111 ~~~a~I~~22112111211122221~22122~~12IZ2222222l2Z22IZ~2Z2211111111
.1 • • • • • • • • • • 7 1 7 7 1 " " ' • • • • • • ' ••• 55555555445544444."'33~l3333'ZZ 5555554444444444333333332233222222221111111111 oooooOOOOOttt,IUt
•• , 0' '5.0 I 32 •• , . I 3 S .0 I •• 4 I 1 ',2 3 I 0 I 1.1 • 5 3 2 •• 1 O. 1 5'," I 32 •• 1. I 3 5 4 0 I . , 135.0 I t I 45' • Z 3 I 06' t a. 5 3 Z I . I "6 , S' 0 1 3 2 I t ' 6 Z ~ 5' a I • I , 5 , 'Z 3 1 0' , •• 45 I 2

TOPOLOGICAL
ADDRESS

INPUT
ADDRESS

DECIMAL
EQUIVALENT

INPUT
ADDRESS
TOPOLOGICAL
ADDRESS

,.".
,.,.'"
,.
'm
,.,....".
,.,.
,.,...'",
,...,
,.'"
,.".
m

'"
m

~~~~~~~~
'10000000
00000000
11000000
01000000
'0100000
00100000
11100000

COLUMN
ADDRESSES

,
"
"n.
,~

DECIMAL
EQUIVALENT

Wimr
10001000
00001000
11001000
01000000
10'00000
11101000
01101000
'0011000
00011000
11011000
1011.1000
00111000
11111000
01111000
10000'00
00000100
11000100
01000100
10'00100
00100100
01100100
10010100
000'0100
"010100
01010100
10110100
00110100
11110'00
10001100
00001100
01001100
10101100
00101100
11101100
01101100
10011100
00011100
"01"00
01011100
06111100
11111100
10000010
00000010
11000010
01000010
10100010
0010.0010
11100010
01100010
10010010
00010010
11010010
101100'0
00110010
11110010
01110010
'0001010
00001010
11001010
01001010
1010'010
00101010
01101010
'00110'0
00011010
11011010
0'011010
10111010
11111010
10000110
00000110
01000110
10100110
00100110
11100110
01100110
'00101'0
00010110
"010110
01010110
10110110
00110110
01110110
10001110
11001110
01001110
10101110
00101110
11101110
01101110
10011,,0
00011110
11011110
10111110
00111110

DATA MAP EQUATION
INTERNAL DATA = DATA IN <±> IAOR <±> A7e(

·,,,
·,.,
··,...
·,......
,....
..
·
···o.,.'"
·

Figure 3. Intel® 2164A Bit·Map (continued)
3-25

Ap·131

(Figure Sb). The bit sense line is precharged to Voo
when RAS is high (Figure Sc). During an active cycle,
the row select line goes high, and the charge is redistributed (shared) with the bit sense line (Figure Sd).
The sense amplifier detects the level from the cell and
then reinstates full levels into the data cell via a capacitive bit line restore circuit. At the end of the active cycle, the row select line goes low, trapping the data level
charge on the stored cell.

3.2 Active Cycles
When i l l is activated, 512 cells are simultaneously
sensed. A sense amplifier automatically restores the
data. When CAS goes active, Column Addresses CAoC~ choose one of 128 column decoders. CA7 and RA7
gate data sensed from the sense amplifiers onto one of
the two separate differential I/O lines. One 110 pair is
then gated into the Data Out buffer and valid data appears at DOUT.

3.5 Data Sensing

Because of independent RAS and CAS circuitry, successive CAS data cycles can be implemented for transferring blocks of data to and from memory at the maximum rate - without reapplying the RAS clock. This
procedure is called Page Mode operation and is described in more detail in Section 4.6. If no CAS operation takes place during the active RAS cycle, a refreshonly operation occurs: ill-only refresh.

The 2164A sense amplifier compares a stored level to a
reference level (Vss) in a special, non-add~essable storage cell called a dummy cell.

The basic storage cell is shown in Figure 4. Note that the
2164A uses two dummy cells on each bit line to help
compensate for alignment effects. Data is stored in
single-transistor dynamic RAM cells. Each cell consists
of a single transistor and a storage capacitor. A cell is accessed by the occurrence of row select (RAS) clocks
Ao-A7 into the address pins, followed by column select
(CAS) multiplexing Ag-AJ5 into the address pins.

LINE
CROSS SECTION OF BASIC

--.--:---;;---:--::---:---::-:--:---:r

SElECT

SELECT

)~
a

CIRCUIT DIAGRAM OF BASIC

e -

e e el

--------'""""-...!....

STORAGE CELL

BASIC CELL IS ROW SELECTED
CHARGE IN CELL REDISTRIBUTED

WITHBITLINE

CELL CHARGE IS RESTORED

ROW SELECT GATE IS DESELECTED

63 STORAGE CELLS AND
2 DUMMY CELLS
STORAGE
NODE

I
~

Voo 0)..----_'-----', \-,---+-~'--.......-'

Figure 5. Sensing

Figure 6 depicts a simplified schematic of the 2164A
sense amplifier. The sense amp contains a pair of crosscoupled transistors (Q 1 and Q2), two isolation transistors (Q3 and Q4), and a common node which goes low
witli SAS (Sense Amp Strobe) and activates the sense
amp. The bit-sense lines (BSL and BSL) run parallel out
from the sense amp in a folded bit line approach. Each
bit line contains 64 data cells and two dummy cells. The
double dummy cell arrangement helps litnit the effect of
mask alignment on sensing margins by having a dummy
cell oriented in the same direction as the data cells.

Figure 4. Storage Cell
~.4

Charge Storage in Data Cell

Data is stored in the 2164A memory cells as one of the
two discrete voltage levels in the storage capacitor - a
high (Voo) and a low (Vss). These levels are sensed by
the sense amplifiers and are transmitted to the output
buffer. Sensing of stored levels is destructive, so
automatic restoration (rewriting or refreshing) must
also occur.

The folded bit line approach has several advantages,
one of which minimizes the effect of interbit line substrate noise and· 110 coupling by providing common
mode noise rejection. This sense amp arrangement uses
metal bit lines and polysilicon word lines.

The charge storage sensing mechanism for a stored low
is described in Figure S. The Voo storage plate creates a
potential well at the storage node. For a stored low, the
charge is stored in the cell relative to the storage plate
3-26

• FROM BIT LINE
ISOLATION CLOCK

DUMMY
SELECT
LINE

PLATE

Figure 6. Sense Amp

,To eliminate sensing problems, a three-step sensing
(Figure 7) is employed in the generation of Sense Amp
Strobe clock (SAS). Device A is triggered by the sense
strobe clock. This device pulls down slowly and when
fed back, triggers the two gates D and E. When SAS is.
low enough, device B turns on, pulling the SAS line
lower and at a later time, device epulis SAS down hard.
If sensing occurs too quickly, the sense amp. becomes
sensitive to capacitive imbalance and sensing errors
might happen. This design eliminates excessively fast
sensing which can occur when two sense strobe clocks
are being used.

precharge, the row select and dummy select lines are at
Vss, isolating the cells from the bit lines. When RAS
goes low, the precharge clock goes low, ending the pre-.
charge period. .
.

3..7 Data Sensing Operation
The row select and dummy select gating are arranged so
tbe selected data and dummy cells are on alternate bit
lines of the sense amp (Figure 6). The row select and
dummy select lines' go high simultaneously, resulting in
concurrent charge redistribution on the bit lines. The
relationship between the word select lines and the effect
of concurrent charge redistribution on the bit lines is
shown in Figure 8. An approximate 250 mV differential
results from this charge redistribution.

j.y

WORD SELECT LINES (DUMMY AND DATA)

SENSE
STROBE
CLOCK

>+_...r_

TIME (ns)

. -_.__.:~~~~~R~~~ __

vo0t-~--,.

Figure 7. Intel'" 2164A Sense Amp Clocks

-!"~

DUMMY DIS LINE

250 mV

............. __ .. _ _ _ _ _ _ _ ~~omv

3.6 Precharge

DATABISLlNE(STOREDLOW) .

-==--:-

Vss L _ _ _ _ _ _ _ _ _ _ _ _ _

A precharge period is required after any active cycle to
ready the memory device for the next cycle. This occurs
while RAS is high. The bit'lines are precharged to VDD ,
while the dummy cells are precharged to Vss. During

TIME (ns)
BIT LINES DURING CHARGE REDISTRIBUTION

Figure 8. Sensing Voltage Waveforms

3-27 '

Ap·131

After charge redistribution, the sense amp is activated.
The sense amp amplifies the,differences in the resultant
voltages on the bit lines. The line with the lower voltage
potential is driven to Vss. The other line remains at a
relatively high level, as shown in Figure 9.

lines. The I/O is a pair of opposite polarity data lines
(110 and 110) which are connected to the Data Input
(DIN) and Data Output (DOUT) buffers. Data is differentially placed on the 110 lines during read operation
and multiplexed to the final 110 lines. During a write
cycle, data is differentially placed on the final 110 lines
from DIN and decoded onto the internal 110 lines.
Stored levels are determined by CA7 column and RAo
row. exclusive-ORed product and then exclusive-ORed
again with DIN (Figure 3). Stored levels are decoded'
during DOUT operation and have no effect on device
use.

Voo
RESTORING
STORED HIGH

The 8-bit row and 'column address words are latched
into internal address buffer registers by RAS and CAS.
RAS strobes in the seven low-order addresses (Ao-A7)
both to select the appropriate data select and dummy
select lines and to begin the timing which enables the
sense amps. CAS strobes in the eight high-order addresses (As-AJ5) to select one of the column decoders
and enable 110 operation.

Figure 9. Bit/Sense Line Voltage

The bit line boost circuitry is shown in Figure 10. During sense operations, the boost capacitors are isolated.
After sensing, the bit line with a "0" has the capacitor
turned off (VGS"'O) and, conversely, the bit line with a
"1" has the capacitor turned on. The boost clock will
turn on and boost the I-level up above Vm), giving
maximum charge stored in the cell.

Figure 12 shows a simplified 2I64A address buffer. As

BSL - - , - - - - - ' - - '

BSL-------'

BIT LINE
BOOST
ISOLATION
CLOCK

tRWD min and tCWD>tcWD min). A
RAS-only refresh cycle or a CAS-only cycle will have no
effect on DOUT which will. remain in the Hi-Z state.
DOUT remains valid from access time until CAS goes
high. Holding CAS low and taking RAS high will not
affect the state of the DOUT' The DOUT remains valid
following a valid Read cycle regardless of the number of
subsequent RAS-only cycles performed on the device up
to the tCAS max limit. These secondary RAS cycles are
RAS-only refresh cycles to the 2164A.

RAS and CAS have minimum pulse widths as specified
in the. 2164A Data Sheet. These minimum pulse widths
and cycle times must be maintained for proper device
. operation and data integrity. A cycle, once begun, must
be within specification.
Figure 16 briefly summarizes the various active cycles
which are discussed in paragr~phs 4.1 through 4.6.

4.1 Read

~ycle

A Read cycle is performed by maintaining WE high during a RAS/CAS operation. The. output pin of a selected
device remains in a hIgh impedance state until valid data
appears at the output within the specified access time.

3.12 Power·On

Device access time, tACC, is the longer of two calculated
intervals:
. .

An initial pause of 500 Jl.S is required after the application of the VDD supply, followed by a minimum of eight
(S) initialization cycles (any combination of cycles containing a RAS clock such as RAS-only refresh) prior to
normal operation. Eight initialization cycles are required
after extended periods of bias (greater than 2 ms) without clocks. The VDD current (lj)D) requirement of the
2164A during power on is, however, dependent upon the
input levels of RAS and CAS and the rise time of VDD as
shown in Figure 15.

Eq. (1) tACC = tRAC or
Eq. (2) tACC = tReD + tCAC
Access time from RAS (tRAd, and access time from
CAS (tcAd, are device parameters. Row to column address strobe delay time, tRCD, is a system-dependent
timing parameter. For example, substituting the devic~
parameters of the 2164A-20 yields:
.
Eq. (3) tACC =tRAC =200 ns for 35 nS$tRCD$ SO ns
Eq. (4) tACC=tRCD+tCAC=tRCD+120 ns for
tRCD>SO ns

, ~: ""--,/1-,----,,---,-'---,I
~

Note that if 35 nS$t~CD$SO ns, device access time is
determined by equation 3 and is equal to tRAC. If
tRCD > SO ns, access time is determined by equation 4.
This 45 ns interval (shown in the tRCD inequality in
equation 3), in which the falling edge of CAS can occur
without affecting access time, allows for system timing
skew in the generation 'of CAS. This allowance for tRCD
skew is designed in at the device. level to ali6w the fastest
access times to be utilized in practical system designs.

ijl 1 f--/-----,i--i--II---I
I

0 1L..---'-'10~"""'20~---"!30'--47:!0
TIME (,<5)

4.2 Write Cycles ..
Figure 15. Typical 100 vs_ Voo During Power Up
4.2.1 EARLY WRITE CYCLE

If 'RAS = Vss during power on, the device may go into
an active cycle and IDD would' show spikes similar to
those shown for the RAS/CAS timings, It is recommended that RAS and CAS track with VDD during
power on or held at a valid VIH .

An early write cycle is performed by bringing WE low
before CAS. DIN is written into the selected bit. DOUT
remains in the Hi-Z state.
4.2.2 LATE WRITE CYCLE

4. DATA CYCLES/TIMING

A late write cycle happen's after RAS anq CAS go low.
During a late write cycle, tRWD and tcwD (RAS and
CAS delays to Write Enable) minimum timings are not
met. Since there is no guarantee that DOUT will remain
in a Hi-Z state, the condition of DOUT is indeterminate.

A memory cycle begins. with a negative transition of
RAS. Both the RAS and CAS clocks are TTL compatible. The 2164A input buffers convert the TTL level signals to MOS levels inside the device.
3-30

Ap·131

4.3 Read-Modify-Write Cycle
(Delayed Write)

4.4 CAS·Only Cycle
A CAS-only cycle has no effect on the 2164A. The
2164A remains in the lowest power, standby condition.

A Read-Modify-Write (R-M-W) cycle is performed by
bringing WE low after RAS and CAS are low. Here,
tRWD and tcWD minimum timings are satisfied. DOUT
has had time to become valid and is now latched by CASremaining low. As WE goes low, a write begins, transferring the data from DIN to the cell as DOUT remains
active with the previous data.

4.5 Refresh Cycle
A cycle at each of 128 row addresses will refresh all storage cells. Any memory cycle - Read, Write (Early
Write, Delayed Write, R-M-W) or RAS-only - refreshes the bits selected by the row address combinations of Ao through ~. Both 32K halves are refreshed,
as the state of A7 is irrelevant during refresh.

In any type of Write cycle, DIN must be valid at or
before the falling edge of WE or CAS, whichever is
latest.

"EARLY"
_ _ READ C ' l C l E - - - - W R I T E CYCLE-- --RAS ONLY CYCLE--

DOUT

-+-----{
--CAS ONLY CYClE---R,EADIMODIFY/WRITE C Y C l E - - - -

DOUT

LATE WRITE

-+-------,--t----'( VALID FROM READ ~+-----<

' - - _ _ _oJ

I - - - - - H I O D E N REFRESH C Y C L E - - - - - I
_ _ READ CYCLE-- - - R A S ONLY CVClE-_

Dour

-1---'-___~V~A~LlD~---J
PAGE MODE
READ/MODIFY/WAITE CYCLE

WE -+--------~

DOUT

-+-----{

VALID ~--+-------+-----

NOTE 1: FUTURE ADDRESS EXPANSION

NOTE; MEMORY DEVICE SPACING IS 0.425"

TRACES ARE 50 MIL:

Figure 22. 2164A Memory Array PC Board Layout

..,

spare rows and four spare columns were chosen for the
2164A.

7. DESCRIPTION OF REDUNDANT
CIRCUITS
The Intel 2164A is the first commercially produced
RAM to incorporate redundant elements into the de, sign. Redundancy allows bit-efficient use of silicon by
maximizing bits/wafer start. By overstressing and
eliminating weak oxide at sort, prior to fusing in redundant elements, long term oxide failures cim be greatly
reduced. Redundancy makes possible the use of larger
die sizes allowing better use of existing fab equipment,
and a more conservative layout to ,utilize larger cell
(storage) areas.
In choosing how redundant elements should be organized, single bits, blocks of bits and spare rows and columns were examined. For maximum efficiency, four

The address of a faulty element is programmed into the
spare element by electrically opening polysilicon fuses
during wafer probe. The basic circuit block diagram for
a spare row is shown in Figure 23. The key logic node
for the spare row is marked by an (A) on the diagram.
When the spare 'row is not in use, node (A) is held permanently! low by transistor (T) whose gate is held high
by the spare row enable block. When the spare row is to
be used, a fuse is opened within the spare row enable
block and the pulldown gate is' brought to ground so
'that the programming elements are enabled. Under control ofa fuse, either address true or address complement
is transmitted through each programming element.
Thus, by blowing the proper fuses, the address of a faulty row in the array is programmed into the spare row.
3·36

Ap·131

Figure 24 shows the basic configuration of a programming element. VG and VDP are special high voltage supplies used only during programming. They are brought
on-chip by extra pads probed at wafer sort. These pads
are not b?nded out to the package but instead, VG is
grounded and VDp is tied to VDO by on-chip transistors.
No inadvertent programming can occur at the package
level because PI cannot turn on and current through the
fuse is limited by the transistor connecting VDP and

Voo. To blow the fuse, the programming address is
brought low, which raises the gate of the programming
transistor P toa high voltage. A high current flows
through the fuse and it opens. When programming is
complete, VG is brought to ground. If the fuse has been
blown, current through depletion transistor D 1 pulls
node (B) to ground and transfer gate T2 passes Xi onto
Xpi. If the fuse has not been blown, node (B) stays near
VDp and Xi is transferred onto Xpi.
.

.... -----:---------,-------------NORMAL
ROW
DECODERS

Figure 23. Block Diagram for a Spare Row

VDP
Xi

x"i

PROGRAMMING ADDRESS

Figure 24. Simplified Circuitry for Programming Element

3·37

inter

Ap·131

data sheet specifications in every respect. Both· device
and system level characterizations have revealed no pattern sensitivity related to the 'use of redundancy, even
when spare elements are intentionally programmed to
locations expected to be most susceptible.

When the spare row is enabled, one task of the circuit is
to deselect the faulty element. Figure 25 illustrates the
. technique which is used. Whenever any spare select line
rises, it causes the "normal element disable" line (NEO)
to rise as well. NED is connected to one extra input of
every normal word select decoder. Thus, when a spare
element is selected, it automatically deselects not only
the faulty element it replaced, but also every other normal element of the array. The timing of the spare select
buffers and the NED generator are optimized to assure
that the faulty element is deselected prior to the selection of the spare element.

Analysis of 2l64A devices shows that the worst case patterns do not involve interactions between columns or
rows. Replacing the entire row or column introduces no
new sensitivity.
The internal 'delays of redundant element decoding are
buried within the internal clocks of the-21 64A and have
no effect on access time. Figure 26 shows access times
for a 2l64A before and after repair.

Another precaution is taken to avoid adverse effects
from possible breaks in the faulty select line. If the far
end of a broken line were allowed to float, it could present a hazard to data integrity. In the case of a broken
word line in the 2l64A, word line clamps protect the far
. end of each fow select line from floating high.

Vee
(VOLTS)

FROM PROGRAMMING ELEMENTS
AND SPARE NOR DECODERS

L - - - - - , - - - + - - - - I R A e (ns)
SPEC VALUE

NORMAL ELEMENT
DISABLE (NED)

NORMAL SELECT LINE

Figure 26. Intel® 2164A tRAC vs VCC

NORMAL
DECODER
INPUTS

..
FAULTY SELECT LINE

The concept of using redundancy for yield enhancement
'Is well-established. Initially researched by IBM in 1964,
Intel has now implemented this concept with theintroduction of the 2l64A. It is expected that others will follow this lead, and that by the mid-1980's, redundancy
will be standard in all memory devices.

Figure 25. Deselecting a Faulty Element
As mentioned previously, the repair of faulty elements
is done during wafer probing. As they come out of fabrication, all spare elements are disabled, allowing full
testing of the normal array. Bits are tested not only for
hard failures, but also for latent oxide or silicon defects
through stressing. The location of any bad bit is stored
in the tester's memory. This information is then processed to determine the optimum usage of the spare elements. Then, the spare elements are programmed into
their proper logical locations.' Finally, the die is tested
once more to assure that repair has occurred as planned.

8. SUMMARY
The Intel 2l64A, made possible by Intel's HMOS-D III
technology, ..introduces a new generation of denser
dynamic RAM devices, featuring redundancy, + 5V-only
TTL-compatible operation, high performance, low
power and ease of use. Additional system level design
information can be found in Intel Applications Note
AP-74, "High Speed Memory System Design Using the
2l47H," and AP-133, "Designing Memory Systems For
Microprocessors Using the Intel 2l64A and 2118
Dynamic Rams."

The dice are then assembled as usual. Rigorous class
testing is performed to guarantee that the devices meet

3-38

Ap·131

ADDENDUM

again checked for their performance to specifications.
Many devices are simultaneously evaillated whether in a
memory system test environment or in an actual system
manufactured by the user. Problems can also occur
from improper, gridding or decoupling on the memory
card itself. With the complicated signal paths in a
memory system, and the difference between vendor
specifications, careful attention must be given to timing
and skews not to exceed data sheet values. Errors from
timing can result in bus contention or can cause many
devices to {ail test. Of course, with dynamic RAMs, arbitration between access and refresh modes must be reliable to guarantee the refresh specifications of the RAM.

A typical user qualification program of memory devices
fits into two categories: device-level qualification and
system-level qualification. Occasionally during these
programs, failures occur that are not related to the
device under evaluation.
At the component level, devices are tested individually
for performance to specifications. These tests are usually accomplished with the use of sophisticated software-driven memory testers and environmental handlers. Due to the complexity of the test setup, several problem areas arise. Often testing (software) errors cause
failures. Omission of dummy cycles' or violation of
refresh specifications makes failures invalid. Many
times the device under test is remote from the test deck
of the system. This can cause excessive power supply
noise at the end of the cables. Timing skews, glitches on
clock lines and 110 levels at the device are complicated
by testing at the end of long cables. Output loading is
also critical for the device to perform to specifications.

These problems can be avoided with careful preparation. However, if problems do arise during qualification, don't hesitate to call your local field applications
engineer or sales office.

REFERENCES
1. Intei® 2164A Data Sheet, March 1982.

During system-level qualification, the problems encountered are significantly different. Here the. devices are

Order Number: 210443-001

the component count and overhead costs, both in design
and implementation.

1 INTRODUCTION

1.1 RAM Overview

Conversely, static RAMs need very little external control
circuitry and they interface easily to most microprocessors. An SRAM has no refresh requirement and usually
has all of its control signals generated directly by the
system microprocessor. A disadvantage of the SRAM is
its high cell complexity. A typical static RAM cell requires four to six transistors - resulting in a lower cell
density and higher manufacturing cost/bit than DRAMs.

Matching the correct RAM to microprocessors is fundamental to effective product design. Understanding the
advantages and disadvantages of each device type
enables a microprocessor system designer to choose the
best product for his particular design objective.
Two basic types of semiconductor random access
memories (RAMs) are in use at present: static RAMs
(SRAMs) and dynamic RAMs (DRAMs). Where large
amounts of memory at the lowest cost per bit is required,
such as main computer memory, the dynamic RAM
holds a commanding position. The extra costs of
refresh, timing,and arbitration overhead are spread over
a very large amount of memory. The. static RAM,
however, provides a better solution for relatively small
memory systems where high performance or simple
system design is desired. \

A new type of RAM has now been developed that combines the best features of the SRAM and DRAM and is
called the iRAM (integrated RAM). An iRAM is an entire dynamic RAM system integrated onto a single
silicon chip, including the memory 'array, refresh logic,
arbitration, and control logic. This new implementation
combines the cost, power and density advantages of a:
DRAM with the ease of use of a static RAM. Because all
of the DRAM control log\c is internal, the memory
system can operate autonomously, controlling its own
refresh and arbitration. This greatly simplifies
microprocessor interfacing and minimizes additional
TTL hardware support. Proper refresh is guaranteed
and overall system performance improved.

A major advantage of dynamic RAMs is low memory
component cost. A DRAM uses a simple one-transistor,
one-capacitor cell for binary storage. This simple design
achieves high integration density and low cost. When a
DRAM cell is not being written, read or refreshed, it
consumes almost no current. At any given time, the majority of the cells in a DRAM array will be in this condition - yielding low overall power con~umption.

1.2 iRAMConcept Background
With the advent of VLSI technology and 64K RAM densities, it became possible to further integrate and
simplify memory system design. LSI memory controllers
integrate, all of ' these components into a single device
(such as Intel's 8202A.and 8203 dynamic DRAM controllers). Figure 1 shows the major elements of such a
dynamic RAM controller.

One disadvantage of DRAMs are their extensive control
and interface requirements. The DRAM control circuitry must generate signals such as RAS and CAS, provide refresh cycles, and handle arbitration. This adds to

MEMORY
CONTROL
SIGNALS

TIMING
GENERATOR

ARBITER

REFRESH
ADDRESS
C~UNTER

t-..

""'7
MUX

t-..
ADDRESS FROM CPU

Figure 1. Memory Control Block Diagram

3·41

MEMORY
ADDRESSES

Ap·132

Figure 2 shows a simple microprocessor memory system
implemented with three major blocks: the C;:PU, the
memory array, and a memory controller. An example of
this configuration is a system comprising an 8088 CPU,
and 8203 DRAM controller and a 2164A memory array.
To advance this configuration to a higher level of integration would require a decision on whether to place
the memory control inside the CPU or within the
memory itself.

A sensible alternative is to integrate the memory controller circuits into the memory - completely freeing the
CPU of this task. While this approach places an additional burden on the device designer, it greatly simplifies
the task of the system designer by eliminating the design
problems associtated with refresh and timing. This permits a very simple interface to the CPU and yet provides
guaranteed refresh, optimized timing, and minimal
hardware support requirements.
A microprocessor integrates all the components of a central processing unit into one device. An iRAM integrates
all the components of a dynamic RAM memory system
into a single device. This is unlike the pseudostatic or
quasi-static RAM devices which only incorporate a portion of the refresh circuitry onto the memory chip and
still require much control from the CPU. The integration used in the iRAM includes the refresh timer, refresh
address control and counter, address multiplexing, and
memory cycle arbitration as well as an 8-bit wide
memory array. Figure 3 is a pictorial representation of
this concept:

. Figure 2. Separate Memory Control

1.3 Memory System Size and
Cost Constraints

Memory control incorporated within the CPU requires
CPU participation in all memory references - just to
preserv~ refresh. This includes DMA (direct memory access) which normally doesn't require or permit CPU intervention. Also, the CPU must run continuously.
Single stepping, hold operations, extended ~AIT states
and the special block data move instructions of some
microprocessors must all be carefully ~voided to
preserve refresh and maintain data integrity of the
memory system. While these constraints can be acommodated with careful design, the added overhead does
limit the full CPU processing capabilities and overall
system performance.

Integrated RAMs are primarily intended for use in
microprocessor memories usually less than or approximately equal to 64K bytes, while standard D~AMs with
a separate controller are more cost effective in larger
memories'. The relative costs of systems designed with
various device family types are shown in Figure 4. A
range is shown for each alternative to represent the
change in cost over time. Thus, the 2K x 8 SRAM is a
good choice for very small memory systems of less than
8K bytes while DRAMs provide a clear advantage in the
region beyond 64K bytes. In the region between 8K and

MICRO·
PROCESSOR

Figure 3. iRAM/Microprocessor Comparison

3·42

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ularly useful in development of microprocessor systems
in which the hardware design of the memory site may be
completed early in the design cycle before the RAMI
ROM mix has been specified. For example, a RAM
might be initially used to store microprocessor instruction code during the development and testing of the system software. This allows code to be run and debugged
at fuli system speed. Initial prototypes and small production runs .can place EPROMs in the same sockets,
while full scale production may change to PROMs or
ROMs. The universal site flexibility also allows an easy
upgrade path to next generation (higher density) devices.

64K, however, standard DRAMs are usualy not as cost
. effective because of the overhead involved in the design
and cost of the hardware for the controller. Based on
these comparisons, iRAMs have a clear advantage for
anything other than very small or very large memory
systems.

5
w

Iiio

A key feature of the universal memory site is the tWD-line
bus control with separate CE and OE to prevent bus contention in a system. This convention offers a distinct
advantage over devices with only one-line control.
(Eliminating the effects of bus contention is extremely
important and not always easy due to its subleties.
Generally, the current and voltage spiking on the power
. supply rails presents the major problem because this
type of noise can lead to a whole host of problems including invalid data, false triggering, race conditions,
and reflections, to name a few.)

":Ew

Iii
~
~

o
I-

8K
16K
SYSTEM RAM BLOCK SIZE (BYTES)

64K

Figure 4. System Cost Graph

1.4 Byte·wide·Universal Memory Site
1.4.1 ONE·L1NE CONTROL

The byte-wide universal memory site concept aitows a
system designer to create one or more memory sites that
can accommodate several types of x8 memories, including RAMs, ROMs, EPROMs, and E2PROMs. The
universal site is depicted in Figure 5. Though based on a
28-pin site, the universal site also supports 24-pin
devices. For this site to be truly universal, it should contain provisions for memory densities that have not yet
been developed.

With one-line control devices (Figure 7), bus contention
occurs when two devices simultaneously occupy a bus
(when CE of one device goes inactive simultaneously
with another devices' CE going active). This is the usual
situation. when chip selects are generated from a
decoder. The contention occurs because it takes more
time for the output of the deselected device to turn off
(switch to high impedence) than the short output buffer
turn-on time of the selected device. Because the data
lines are wire-ORed to a common data bus, any data bits
of opposite polarity will cause bus contention (Figure 8).

Figure 6 shows various memory classes and how they
conform to the universal site. The universal site is particSEE TABLE ~ 1
A,.,§ 2
A,
3

28 t:Jycc
27PiNE
26 ~ ,SEE TABLE

18pl/0
17t:J1I0
16§1I0
1SPI/0

SYSTEM HIGH VOLTAGE, TYPICALLY Vpp
OR REFRESH FOR INTEGRATED RAMS
26 Vee fOR 24 PIN DEVICES,
Au FOR 128K EPROMS
1

AII61

Figure 5. Byte·Wide Universal Memory Site
3-43

NC
A12
AT
A,
As
A,
A,
A,
A,
A,
1/00

Figure 6. Intel's Line of Universal Products

OUTPUTS 1
DESELECTING
OUTPUTS 2
ACTIVE

DATA 2 VALID

BUS ----------------------~--------------~XXXXX~~~~~r---------

CONTENTION _____________________________...:.__________~c....:.\£.~~~£:.:1...._________

1- O~~~~~P--I
Figure 7. One· line Control

3·44

1/0 1

AP-132

any given processor. All devices inserted in the path, demultiplexers; transceivers, decoders, etc., must be com'
pensated for by a higher speed memory.

Vee

2 DEVICE DESCRIPTION

2.1 Oveniiew
The 2186 and 2187 iRAMs are 5-volt only, dynamic
RAM 8K x 8 systems integrated on a single chip (Figure
10). The memory devices have been designed for easy
use with microcontrollers, multiplexed address/data bus
microprocessors, and processors with separate address
and data paths. These memories are referred to as integrated RAMs or "iRAMs" because they contain refresh
timing and control logic. The 2186/87 iRAMs include
the following major features:
• , Easy to use on-chip self-refresh, including:
- Internal refresh timer
- Refresh address counter
- High speed arbiter (2186 only)
-'- Refresh address multiplexer
- Complete internal timing control
• External refresh. control option (2187 only)
• Microprocessor handshake signal (2186 only)
• Outputs drive two low power Schottky TTL
loads and 100 pF '

Figure 8. Bus Contention

.1.4.2 TWO-LINE CONTROL'
Similar to one-line control, two-line control logic allows
the CE of one device to go inactive simultaneously with
another going active.' However, the timing diagram in
Figure 9 shows that no bus contention occurs because
the OE of the selected device is not enabled until the outputs of the deselected device have switched off the, bus.
The use of an independent output enable is the best way
to eliminate bus contention in the system. The use of
, non-integrated output buffers cannot achieve the ,same
result; they can only confine bus 'contention 'to a memory card or memory section ora large card. In addition,
as processor speeds increase, greater demands are pfuced
on memory performance and the use of external nonintegrated output buffers places still more constraints on
memory system performance. In this context, the time
between addresses out and data in is a fixed interval for

The 2186/87 iRAMs an; fabricated using an N-channel
double layer polysilicon gate process with depletion
loads: The four-quadrant memory array is built with
conventional one transistor DRAM 'cells, polysilicon
word lines and folded metal bit lines. Each of the four
quadrants contains 128 rows and columns. In addition,
four redundant columns and four .redundant rows are
provided. Two pairs of 110 lines from each of the quad-

ADDRESSES

-i........r-....~

COMMON - -............
OE(RD)

--«:

DATA BUS - -................................

DATA 1 VALID

ACTIVE

"_ - ......

Figure 9. Two·line Control

3·45

OVERLA~

Ap·132

rants provide a total of eight bits to the data bus. An active restore circuit boosts the bit lines back to a full Vee
level after every read or refresh cycle. Boosted word
lines and column select lines are used to write a full Vee
level into the memory cells. Wide internal operating
margins provide a high degree of reliability.

Intel's byte-wide universal memory site (Section 1.4).
Pin 1 (labeled' 'CNTRL") is the only external difference
between the 2186 and 2187. On the 2186, Pin 1 is a RDY
output - a signal to the system indicating memory
status. Pin 1 on the 2187 is a "refresh" strobe (REFEN),
an input signal for external refresh requests.

2.2 Device Pinout

Pins 2 thru 10, 21, and 23 thru 25 are the 12 address inputs required to select each of the 8192 bytes. Pins 11
through 13 and 15 through '19 are the eight bits ofthe bidirectional data bus.

The pinout of the 2186 and 2187 is shown in Figure 11.
The industry standard 28-pin package conforms to

Figure fO. 2186 Die Photo
3-46

inter

Ap·132

Pin 27 is the write pulse input strobe (WE) for data store
during Write cycles. Pin 20 is Chip Enable (CE), which
latches addresses and begins the internal memory cycle.
Pin 22 is Output Enable (OE), normally connected to a
CPU READ (RD) line. OE enables the iRAM output
buffers during a Read cycle.

capability as it has been designed for use in synchronous'
applications.
Pin 1 on the 2186 is the RDY output which serves as the
handshake signal (required in asynchronous systems)
and is usually bussed to the RDY input circuit of the processor. The RDY output is an open drain device, requiring a 510 ohm pull-up resistor which allows "wire-OR"
connections of other device RDY outputs without the
need for extra gates.

The 2187 receives external refresh requests via Pin 1
(REFEN). This input must be strobed 128 times within 2
milliseconds to perserve refresh in the dynamic RAM array. The 2187 iRAM is designed for use in synchronous
systems where the user wants control of the refresh
cycles. Hence, the designer must provide refresh requests to the iRAM. The 2187 has neither a RDY signal
nor any access cycle deferment and because it has .no
built-in arbitration capabilities, the user must also'
guarantee that access cycles are not requested during
refresh cycles.

A10

Ao
1100
110,
1102
GND . .;.;.. _ _ _....;.:.s-

1/07
IIO s
1/0 5
110.
1/0 3

Figure 11. 2186/87 Pinout

Refresh addresses are generated internally in both
devices by an onboard refresh address counter. In addition, both devices have an internal refresh timer which,
for the 2187, becomes active in a power-down mode.

2.3 Internal Description
2.3.1 ASYNCHRONOUS AND SYNCHRONOUS
REFRESH

2.3.2 FUNCTIONAL BLOCK DIAGRAM

The 2186 iRAM contains automatic internal refresh circui try making it an ideal choice for asynchronous applications. The 2187 does not have the internal arbitration

Figure 12 shows a functional block diagram of the
iRAM.

REFRESH
REQUEST

CE>-A~e~e~E~SS~R~E~Q~UE~S~T~~---~~---~~

SEQUENCER
AND
ARBITER

ACCESS
COMMAND

OE>----~-----~

WE>----------~
• ROY OUTPUT ONLY ON 2166
RE"F"EN INPUT ONLY ON 2187

Figur~

12. iRAM Block Diagram
3-47

BUSY

RDY'

AP-132

2.3.2.1 Refresh Timer

3 DEVICE DESCRIPTION

The refresh timer requests refresh cycles as required.
The refresh timer has been designed to track with temperature and process variations. The design optimizes
the rate at which refreshes occur while still guaranteeing
data integrity.

All timing signals used throughout this document are
denoted by various alpha character strings to indicate
certain basic conditions or parameters. Understanding
signal name derivation will enable the reader to arrive at
a correct interpretation of any signal name encountered.
Figure 13 illustrates the meaning of various letters used
in a signal name.

2.3.2.2 Sequencer· and Arbiter Circuits
The sequencer and arbiter circuits accept refresh requests
from the refresh timer and memory cycle requests from
the CE inp~t. The internal refresh command and the external memory accesses are asynchronous and either
may occur at any time with respect to the other. If one
does occur while the other is in progress, the request is
queued and the cycle performed after the existing cycle
has completed. If a refresh cycle is already in progress at
the time an access request occurs, the RDY signal on pin
1 is pulled to VOL informing the system that the access
cycle is being deferred. In this instance, the normal cycle
will be delayed until after the refresh cycle has been completed. RDY will remain low until shortly before valid
data becomes available, after which the cycle is com- .
pleted in a normal manner. The internal high speed arbiter resolves any conflict wherein an internal refresh
command and an external access occur simultaneously.
This circuit also generates the RDY handshake signal in
the 2186. The sequencer/arbiter circuit also decides
which type of memory cycle is to occur and contro~s the
operation.
2.3.2.3 Address' Buffers and Refresh Address
Counter
Exter.nal addresses Ao-A 12 are directed to internal row
and column address buffers to generate internal byte ad~
dresses. Refresh addresses are generated by an internal
refresh address counter and are multiplexed internally
with the external row addresses.

ll.. J

SIGNAL TERMINOLOGY

CONDITION
H - HIGH
l - LOW"
V - VALID
X -INVALID

CYCLE
TYPE (OPTIONAL)
R - REFRESH
F - FALSE
.

TELQXR

L - - - . SIGNAL OF INTEREST

REFERENCE. .
E _ ENABLE (CHIP)
G-OE
W- WE.
A - ADDRESS
Q-DATA
R - READY (ROY)

E - ENABLE (CHIP)
G-OE
W- WE
A - ADDRESS
Q-DATA
R - READY (ROy)

FJgure 13. Timing Signal Terminology
Each control signal is given a one-letter designer; i.e.,
CE is represented by E, OE by G, etc. Each of these letters is followed by another letter describing the state of
the foregoing. In addition, a timing descriptor may have
a ietter added to the end to describe a special case. For
example, TELGL is the time from CE low to OE low,
while TEHELF is the time from CE high to the next CE
low during a false memory cycle; TELQVR is the time
from CE low to data valid for a not ready condition.
The 2186 and 2187 are edge-triggered devices that recognize a timing edge as a signal to start an operation.
Because of this, CE must be allowed to make only one
transition per cycle, otherwise the device cycle time
(TELEL) will be violated. The 2186 and 2187 latch all
external addresses on the leading edge of CEo Data is
latched into the device on the leading edge of WE as opposed to the trailing edge write requirement which is
common among static RAMs.

.2.3.2.4 Data Buffers
Controlled by signals from the read/write data wntrol
circuit, the three-state bidirectional data buffers receive
or transmit eight data bits.
2.3.2.5 ,Read, Write Data Control

The 2186 provides four major types of cycles: read,
write, false memory, imd refresh.

The read/write da~a control circuit controls and directs
the flow of data between the 8K x 8 DRAM memory array and the data buff~rs.

Two major modes of operation texist for both read and
write cycles; CE pulsed mode and CE long mode. For
pulsed mode CE operation, the low CE time (TELEH)
must be less thano~ equal to TELGL(TELWL)max+
TGLEH(TWLEH)min, while long CE mode requires a
longer CEo (For more detailed timing information, consult the 2186 and 2187 data sheets.)

2.3.2.6 Cycle Terminator and Precharge
The cycle terminator and precharge circuits ensure proper
termination of all memory cycJesand precharge the dynamic circuitry in preparation for the next cycle.

3·48

Ap·132

3.1 Read Cycle

will beco'me valid and remain so for as long as OE is active, independent of CEo

A read cycle (Figure 14) is initiated by both CE and OE
going low during the same cycle. Depending on the low
time of CE, either a pulsed or long CE mode will occur.

Refresh cycle is in progress
If a refresh cycle is in progress at the time CE goes low,
the read cycle will be delayed (deferred read cycle) until
after the refresh cycle has completed. In this event, the
2186 will respond very quickly with a RDY low output
(TELRL). After the refresh cycle is completed, the read
cycle wiil commence and data will be available at a given
time after RDY returns high (TRHQV). As was the case
with the non-deferred read cycle, TELGL must be met
or an FMC will occur.
.

I.----TELEL----+j
TEHEL

3.1.2 LONG CE MODE READ

OE
WE ---1-~+_-+----~~----

For long CE, a read cycle mode is initiated on the falling
edge of CEo Similarly to pulsed mode CE, both deferred
and non-deferred write cycles may occur where a deferred cycle causes RDY to be pulled low.

ADDRESS

lID

----t--:=:-:t=~~~j

In the long CE mode of operation, CE must be held low
for a given period of time after 5E goes low (TGLEH).
Violation of this specification will cause an FMC to occur. At a given time after OE goes low, valid data will
become and remain available throughout the duration
of OE's active period, independent of CEo

READ

Note that deferred access cycles are not allowed for the
2187.
OE -,--+--I

A write cycle (Figure 15) occurs when both CE and WE
go low during the .same cycle. As is the case for the read
cycle, either a pulsed or a long CE mode can occur.

--t------{

3.2.1 PULSED MODE

CE WRITE

In the pulsed mode, a CE write cycle is initiated on the
falling edge of CEo At this time, a refresh cycle mayor
may not be in progress.

DEFERRED READ

Refresh cycle not in progress
With a refresh cycle not in progress, the memory cycle
can immediately commence (non-deferred write cycle).
After the falling edge ofCE, WE must go low within a
specified period of time. If this latter condition is not
met, a false memory cycle (FMC) will occur (see Section
3.3). On the falling edge of WE, data is latched into the
device.

Figure 14. Read Cycle Timing
3.1.1 PULSED MODE CE READ
For pulsed mode, a CE readcycle is initiated on the falling edge of CE at which time either a refresh is or is not
in progress.

Refresh cycle is in progress
If a refresh cycle is in progress at the time CE goes low,
the write cycle will be delayed (deferred write cycle) until
after the refresh cycle has completed. In this event, RDY
is brought low and held there until the refresh cycle has
completed. Note that data is still latched into the 2186 on
the falling edge of WE.

Refresh cycle not in progress
With a refresh cycle not in progress, the memory cycle
can immediately commence (non-deferred read cy<,:le).
After the falling edge of CE, OE must go low within a
specified period of time (TELGL): If this latter condition is not met, a false memory cycle (FMC) will occur
(see Section 3.3). At some point after OE goes low, data

3-49

Ap·132

Note that the CE high time (TEHELF) required after an
FMC is somewhat longer than the corresponding period
required for a read or write cycle (TEHEL).

I-----TELEL----J

As is the case with a read or write cycle, FMC cycles can
be deferred. ROY response time (TELRL) and recovery
time (TRHEL) are the same as for the read and write
cycles.

CE
~ -~-~+----~~--.--4_-

OE----+t-------------

WRITE
I-----TELELR -..,---~

OE----I----+------l----

READY - - - - .
TDVWL

--l

WE - - - - 1 - - - ; - - - + - - - - : - - - - - ..... TWLDX

Figure 15. Write Cycle Timing
Figure 16. False Memory Cycle Timing
3.2.2 LONG CE MODE WRITE

3.4 Refresh Modes

A long mode CE write cycle is initiated on the falling
edge of CEo As is the case for a pulsed mode CE, both
deferred and non-deferred write cycles may occur with
ROY being pulled low in the deferred cycle.

Both the 2186 and 2187 can be refreshed'by reading or
writing all 128 rows (Ao through A6) within a two millisecond period. Several specific modes of refresh opera.
tion exist for each part as outlined below.

For the long CE mode of operation, CE must be held
low. for a given period of time after WE goes low
(TWLEH). Violation of this specification will cause an
FMC to occur. On the falling edge of WE, data is latched
into the device.

3.4.1 2186 AUTOMATIC INTERNAL REFRESH

Refresh is totally automatic and requires' no external
control. In addition, the refresh address is computed internally and does not have to be supplied externally. A
high speed arbitration circuit resolves any potential conflict arising between simultaneous access and refresh cycle requests. If a refresh cycle is in progress at the time
CE becomes active (low), the 2186 will respond with a
ROY low output. If, on the other hand, an access or
false memory cycle is in progress at the time the internal
refresh timer times out, the refresh request will be
queued and then performed after the present cycle is
complete. Note that RDY will not go, low during a refresh unless the RAM is selected by CEo

3.3 False Memory Cycle (FMC)
A false memory cycle (Figure 16) occurs when CE is active and neither OE or WE go low. In this case, the cycle
will automatically be terminated on the trailing edge of
CEo This is a valid mode of operation in which precharge
and data integrity are guaranteed.
As an added feature of the false memory cycle, a refresh
cycle is performed on the row. which is selected by the'
seven external row addresses.
3-50

Ap-132

of this, ROY will not respond to these extended cycle
refreshes.

3.4.2 2187 EXTERNAL REFRESH
A high.to-Iow transition on the REFEN input will cause
a refresh cycle to be initiated (Figure 17). In this mode
REFEN must always be strobed 128 timesin a two millisecond period. The REFEN input may be strobed in distributed or burst mode. Refresh addresses are supplied
by an internal refresh address counter'.

REFEN

3.5.2 2187
The 2187 supports single-step operation by following the
beginning of a memory cycle with REFEN going and remaining low. Refresh cycles continue to occur periodically as long as REFEN is held low, even if OE or WE remain low indefinitely. Data remains valid on the bus as
long as OE is valid. WE latches data on its falling edge.Again, after REFEN returns to a high state, a minimum
amount of time (TRFHEL) must be allowed before the
next high-to-low transition of CEo
.

-+--+------l

3:6 power·up
EXTERNAL REFRESH

3.6.1 2186

l----TR-F-LR-F-H--S<~

To guarantee power-up, all control inputs must be inactive (high) for a 100 microsecond period after Vee is within
specification. No dummy cycles are required.

3.6.2 2187

POWER DOWN REFRESH

The 2187 power-up is accomplished by holding REFEN
active low for 100 microseconds after Vee is within specification. All inputs must be stable and within ·specification. CE; WE, and OE must remain inactive (high) during
user power-up.

Figure 17. External Refresh Timing
3.4.3 2187 POWER· DOWN AUTOMATIC
,INTERNAL REFRESH
If REFEN is kept low for greater than one timer period,
the internal refresh timer will be activated. Refresh in
this mode is totally automatic and requires no external
stimulus. REFEN must return high within a specified interval prior to the.next memory access cycle (TRFHEL).
Attempting to access the 2187 during a refresh cycle is
~ot a valid mode of op'eration;
,

4 INTERFACE CIRC.UITRY
"
There are three key interface circuit considerations when
designing with iRAMs.

1. The first consideration is the need for a single edge
("glitchless") transition of chip enable (CE) per cycle
- 'because the leading edge transition (active low) of '
CE latches addresses into the iRAMs and initiates
several internal device Clocks. Also, there is minimum specification for CE inactive time (to allow for
proper precharge of internal dynamic circuitry).

3.5 Single·step Operation
Both the 2186 and 2187 can support "single-step" operation for microprocessor system diagnostics. Single-step
operation is defined as inserting an unspecified number
of WAIT states in the middle of a normal RAM access.

2. The second consideration concerns write cycles. Because iRAMs write data on the leading edge of WE,
there is the need for valid data at the memory device
before the WE line is activated.

3.5.1 2.186
The 2186 supports single-step operation in microprocessor applications which hOld OE or WE valid (low) for
indefinite periods. Data ~ill remain valid on the bus as ,
long as OE is valid~ WE latches data on its falling edge.
Automatic refreshes will continue to be performed as
needed, even while OE. or WE is held low. During this
extended cycle, the internal array is free to be refreshed
with no threat of access/refresh cycle conflicts. Because

3-51

3. The third consideration is the value of same site compatibility with byte-wide SRAMs, EPROMs, ROMs,
and E2PROMs. In particular, allowance for the trailing edge write requirements of SRAMs should be
made.
/
Modest additional circuitry permits compatibility with .
SRAMs as second sources or allows the iRAM to substitute for ROM or EPROM during debug stages. Several

Ap·132

circuit examples to mt:et the various re'quirements of interfacing microprocessors to iRAMs will be described.
elK

Figure 18 shows circuitry for generation of a "glitchless"
CE from standard 8086 bus signals. Figure 19 shows the
circuit timing. This dual J-K flip-flop arrangement guarantees a number of operating conditions. The flip-flops
generate a stable CE for the iRAMs by enabling the 8205
decoder only after valid addresses have arrived, but
early enough to allow the 2186iRAMs' RDY signal to
. respond in time to insert a WAIT-state (ifrequired). The
circuit also ensures that a minimum CE high time is provided. (This is especially important during false memory
cycles (FMC) where the CE high time specification
stretches beyond that of normal cycles).

ALE

M/iO

eEX

Also of significance is the compatibility of this circuitry
with SRAMs and EPROMs. This includes requiring CE
to remain valid throughout the cycle.

The interfa~e circuit is simply a two-bit counter designed
to start a count sequence when flip-flop A is preset by
ALE going high. The Qoutput of flip-flop B along with
M/iO (52 for max mode) is used to enable the CE decoder to provide a CE to the desired iRAM.

-----I-:..;

-----+---1

Figure 19. Interface Circuit No.1 Timing

(52 for max mode), is used to enable and address
decoder to provide CE's to the iRAMs.

MilO

A certain amount of skew can occur between the falling
edge of ALE and the falling edge of the clock. Two situations can occur: (1) ALE goes low before the falling
edge of the clock, the E enable line to the decoder remains high until the falling edge of the clock, and (2)
ALE goes low at or after the falling edge of the clock, in
which case the E enable line is immediately activated and
enables the decoder. Note that the RESET line is used to
clear the MilO flip-flop. This causes the 74S138 to be
disabled, satisfying the power-up requirements of the
2186 (CE remains high). Also, a pull-up resistor is connected to the RD line. This ensures that OE remains high
during RESET (the 8086 three-states, RD during
RESET).
.

The READY signal is ANDed with the Qoutput of flip- flop
A and input into flip-flop B. As long as READY is low,
the K input of the flip-flop driving B will stay low, keeping
it from being reset. This in turn acts to keep CE active.
This input allows CE to stretch during a WAIT state to
meet the requirements or SRAMs or EPROMs that may
occupy the same memory site. However,the iRAMs do
not require that CE be held low for extended cycles.
The circuit in Figure 20 (only for the 8088 - enclosed in
dashed lines) offers an alternative. This circuit provides
an Enable signal (E) for the CE decoder which is synchronized with ALE. This Enable signal along with

READY

.----------------~-------~

_____

Figure 18. Interface Circuit No.1

3·52

I-=m

Vee
5100

ROY~~==================:-------------------____________~______~____~______~
A

'-----11---++---+--10

AOO·AO,,"'...-________

Either circuit will provide all of the interface needed for
a 5 MHz 8086 or 8088 max mode system, because
MWTC can be used to provide both leading and trailing
,edge writes. For a min mode system, the circuit in Figure
21 can be used to provide a leading edge write, and the
circuit in Figure ;Z2 can be used to provide both a leading
and trailing edge write.
WR
ClK

.....

A simple, one-gate alternative to the preceding example
along with the appropriate timings is shown in Figure
23. This cross-coupled NAND arrangement operates in
much'the same way as the CE generation circuit presented earlier, acting to synchronize the WR pulse with
the clock. This circuit will provide for botlt leading and
trailing edge writes.
-

5 SPECIFIC APPLICATION EXAMPLES

'N'

This section describes some typical memory interface
designs using three types of CPUs: an 8-bit microcontroller, an 8-bit microprocessor, and a 16-bit microprocessor. Design examples are included for both the 2186
and the 2187.
'
,

ClK

......

74l5D4
74574,

, Figure 21 ~ Leading Edge Write

5.1 a·pit Microcontroller
74lS04

WR--~--fD

Figure 24 shows a two-chip microcomputer system ~sing
-the 875118051. This system features 4K bytes of
EPROM/PROM and 8K bytes of data storage using the
2186 iRAM. Interface to'the multiplexed bus is simplified because the 2186 latches addresses from its external
bus on the falling edge of CE, eliminating the need for
latches. In this configuration, the ALE output from the
microcontroller is gated with P2'.7, and used to generate
CE of the 2186. The gating of ALE with P2.7 is important for the following reasons: when the 8051 does any
type of memory operation, it outputs ALE onto its external bus. This includes internal p~ogram memory
fetches, in which the ALE cycle time (Figure 25) is only
half of what it would be for an external data memory
fetch. During these "short" cycles, ALE must be inhibited from generating a ,CE to the 2186, or ,else the
2186 cycle time with WAIT specification (TELELR)
would be violated. To carry this' out, P2.7 is initially set
to a "1" which is done automatically upon RESET. This
"1"will be present on the output during all times except
external data memory fetches from addresses below
8000H, at which time P2.7 will go low, allowing ALE to

ClK -74C
lSD4---I>-ClK

74574

ClK

WR----+--i

-+_......___- , l - _ j - _

DATA _ _ _-,-......

(WRITE) _ _ _ _ _......_

....._ _ _.,.,..;--'1..--

WE - - - - - - ' - - - t i

Figure 22~ Leading and Trailing Edge Write '

,ClK

Figure 23. Simplified Write Enable Circuitry
!

3-54

AP·132

provide a CE to the 2186. After completion of the external data memory fetch, P2.7 will revert to its preset
value of "I".

the 8051 are tied directly to the WE and OE inputs to the
iRAM. Data to be written is guaranteed to be valid
before the leading edge of WR for the 8051. This provides the leading edge write needed by the 2186/87.
Although a RDY input does not exist 'for the 8051, a
2186 can still be used for data memory. At 8 MHz the
8051 does not require data back from the data memory
until 800 ns after the trailing edge of ALE. The 2186-25
specifies worst case access time at 675 ns from the trailing edge of CE, whic,h in this system, corresponds to
ALE. Even if .the 2186 is just starting a refresh cycle
when the 8051 requests an access, it will still have time to
complete the refresh cycle, and access valid data by the
time the 8051 requires it. Note that during RESET, CE is
kept high to satisfy the power-up requirements of the
2186.

RDY N.C.
8051
8751

74S32

WR
Rii

The access time required of program memory is somewhat faster than that needed for data memory. Because
of this, the 2186 cannot be used in an asynchronous refresh mode as program memory for a full speed system.
However, operation could be guaranteed if the system
clock were slowed down.

L-_ _..,....:E:::.rA

Vee

Figure 24. Asynchronous 8051 System

The synchronous 2187 iRAM can be used as program
storage for an 8051 running at 10 MHz by utilizing a
method known as clock stretching. The circuitry, as
shown in Figure 26, allows the 8051 clock to be stopped
in a high state whenever the 2187 requires a refresh cycle.
This stretched period is performed at the beginning of a
cycle while ALE is high.

Note that a pull-up resistor is used to ensure that P2.7
will return to a "I" before the next trailing edge of
ALE. Timings on the ALE are specified so that all CErelated parameters on the 2186 are guaranteed, including address setup (TAVEL) and hold times (TELAX),
and CE high time (TEHEL). The RD and WR outputs of

1---220--;·~lfooo'~------1500--------·~1

ALE ===~~'

--E'=~iQ::::=::::;1~

~,11 ~$1 ~--

PORTO
(R~,~ -------;-'.v~ATILInD-TI-'------~I'V"'A~LI~D;I---~---r--_______~.~A~D~D~RE~S~S~.~-~---~.~DA~T~A~.~~-~---L----l

I--

-11601--

~O:J~ ==============='=A:ci:~:~~:~:S='=='==~===V=A=L=ID=D=AT=A====~=='=================
VALID ADDRESS
8 MHz
8051/2186

Figure 25. Asynchronous 8051 System Timing
3-55

plished by allowing either PSEN or RD to enable the
2187 for a READ. Thus, it is possible to create a intermixed data and instruction field.

Operation of the clock stretching circuitry is straightforward (Figure 27). Under normal operation, U2 acts as a
frequency divider for the clock. U3 and U4 count clock
pulses, and when a full count occurs, a refresh cycle request is issued (RFRQ). This request sets UIA. On the
next high transition of ALE, this request is clocked into
UIB, where it 'causes REFEN to become active. A
refresh cycle within the 2187 begins at this time.

5.2 8088/2186 8·Bit Microprocessor
Design Example
An example of an 808812186 iRAM design is shown in
Figure 28. The 8088 is connected in a straightforward
manner to the 2186 iRAM array. The low order addresses
are latched from the multiplexed address/ data bus of the
CPU by ALE and are connected to the array. The CPU
RD provides OE for the iRAMs while the MWTC from
the 8288 bus controller serves as the WE for the memory. A stable chip select is generated by circuitry enclosed within the dashed lines. This circuit runs without
WAIT states at 5 MHz using the 250 ns 2186-25.

At the same time that REFEN becomes active, U5 is released from a clear state to start counting clocks, acting
as an interval timer to allow time for the refresh cycle to
occur.
On the first high transition of the system clock after U I B
is set, U2 will be preset, maintaining the already high
state of the clock. This high level is maintained until U5
has counted 10 clock cycles, at which point it acts to
reset the clock stretching circuitry and allow the clock to
return to a toggling condition.

5.3 8086/2186 16·Bit Microprocessor
Design '~xample

The clock stretching circuitry used in this system could be
utilized to a greater extent than just handling iRAM
refresh cycles. For example, it might be useful for some
type of DMA operation, or for use with slow peripherals:
Also note that no address latches are needed with this
system. To satisfy the power-up requirements of the 2187,
REFEN must be held low for 100 p'sec after Vee is within
its specified value. This is accomplished by driving REFEN
low during RESET.

The 5 MHz min mode system shown in Figures 29 and 30
depicts a typical interface of 2186 iRAMs with an 8086
16-bit microprocessor. With this arrangement, up to
128K words can be addressed.
To guarantee a stable CE, the first interface circuit described in Section 4 is used. The output of this dual 1-K
flip-flop arrangement is used to enable the 8205 CE decoder.

In a typical operation, a down-loader program would
reside onboard the 8051 in PROM. This program would
write program instructions into data memory. These instructions ~could then be "fetched" out of the same
memory which would now be acting as program storage.
This overlaying of program and data store is accom-

A False Memory Cycle (FMC) is generated by this circuit
during byte write cycles because both devices in the
16-bit word receive CE, but only one device (or byte)
receives a WE. The other devi~e enters an FMC without
any consequences at the system level.

eLK

ALE

175
PORTO

6"-5-\-,----+-------1

~~A~D~D~RE~S~S))---~====~~r(---------~c=

!--- - l
400

RFRC

--------------~rS-~---,----------

REFEN - - - - - - - - - - - - - - - - - - - - - - - - ,

~~~---~----~----~~-~r~rl--~_____
805112186

Figure 27. Synchronous 8051 System Timing
3-57

inter

Ap·132

In min mode, the 8086 does not guarantee that valid data
is present before the leading edge of WR. A technique to
delay this edge in order to provide the iRAMs with a
properly timed WE must be included in the system. The

cross coupled NAND arrangement described in Section
4 is used to provide both leading and trailing edge write
compatibility.

Figure 28. 8088/21'86 Microprocessor System
3·58

REQUIRED
RDY RESPONSE

WE--------------~------------~~----,

Figure 30. 8086 Min Mode System Timing
If an 8086 max mode system is to be used, the WE delay
circuitry is not needed. In this case, the normal WR provided by the 8288 bus controller meets the leading edge
write requirement. A diagram is shown in Figure 31.
Note that a D-type flip-flop is used to latch 82. This is
important, because during certain 8086 operations, such
as execution of a software HALT, Si is not guaranteed
to remain valid up to the trailing edge of ALE. To overcome this, 82 is latched on the leading edge of ALE, as
done here.
.

video priority table. This programmable ·table permits
up to 16 colors (out of 256 possible) per display frame. It
also assigns priority. For exa!llple, a red disk crosses a
green on the display. Does the red cross in front of the'
gr.een disc, the green in front of the red, or does the area
of the overlap .become yellow? The priority encoding
assigns answers to these questions.
By industry. standards, this 256 x 256 pixel display has
low-end to medium display resolution. For those unfamiliar with the capabilities at this level, visit a local video
game parlor and examine some of the dazzling displays
on the state-of-the-art video games such as Williams
Electronics Defender. Advanced machines such as this
are only beginning to approach this display density.

5.4 Graphics Example
All of the applications examples presented thus far are
non-specific; that is, all demonstrate how to connect the
iRAMs to various microprocessors in the most general
terms without regard to the total application. The design
that follows shows the 218612187 iRAM'in a specific application: a color graphics display memory.
In this example (Figure 32), the color display resolution
is 65,536 (256 x256 pixels) x 4 bits. The four bits select
the color of the pixel by addressing a color lookup and

The iRAM used in this example is the synchronous 2187.
: Due to the sequential addressing scheme of video dis. plays, video memory typically requires no additional circuitry for refresh. The 2187 is no exception, and in this
design the REFEN pin is tied high. The sequential scanning by the video' address generator automatically ~e
freshes the internal array of the iRAM.
3-60
.I

11-;::=:A:l~E;--t1~.rn-:::r::;~--iI074LS74Qt-----,

~~_""-_ _L-_L......I'\

RDY
VIDEO
MEMORY
CONTAOL
CIRCUIT

(CPU ACCESS)
WINDOW
CO"MP BLANK

-- 16 OF 256 COLORS
CAN BE DISPLAYED
PER FRAME
(ASSUMING TABLE
IS1Kx8ARRAY)

VID3

HSYNC
VSYNC

DISPLAY RESOLUTION: 256 x 256 x 16 COLORS/PIXELS

and vertical blanking (retrace) periods permits the real
time screen update required in an animated display.

Figure 32.is a simplified diagram. A detailed analysis of
the circuit and timing will not be discussed. Briefly, the
circuit functions as follows:
CPU addresses A 14 and A 15 are decoded to generate one
of four iRAM chip selects so that the (assumed 8-bit)
CPU can read or write information to the individual
memory planes (iRAMs). These chip selects are gated so
that all four iRAMs can be simultaneously enabled by
the Vcs signal from the video timing circuitry. A similar
circuit (not shown) would allow OE for the iRAMs to be
generated by either the CPU or the video timing genera- ,
tor. The iRAM addresses are generated by multiplexing
the CPU addresses with video timing addresses. The
32-bit output from the iRAMs ,is loaded into four 8-bit
shift registers and are se~ially shifted out as four bits of
video information used to address the color lookup
table. The four lines (Vid l -Vid4 ) are multiplexed with
CPU addresses Ao-A3 to create the actual addresses of
the lookup table. Comprised of two 2148H RAMs, the
eight data lines of the lookup table are directed to three
digital-to-analog converters for generating 16 of 256 different display colors.

5.5 External Refresh Systems
5.5.1 BURST REFRESH
Figure 33 shows an example of a burst mode refresh controller. Timings for this system are shown in Figure 34.
To ensure data integrity for a 2187, REFEN must be
strobed at least 128 times in each 2 ms period. After each
high-to-low transition of REFEN, one cycle time must
be allowed before REFEN (or CE) again becomes active.
The system. shown in Figure 33 accomplishes refresh by
interrupting the processor once each 1.63 ms (200 ns
clock period divided by 8192). Upon acknowledgment
of this interrupt, TEST is driven high, allowing REFEN
to be generated once every three clock cycles. TEST is
also routed back- to the TEST pin of the 8086 to indicate
that a burst is in progress. The 8086samples the state of
the TEST pin and loops in an idle state until the TEST
goes low. This is accomplished using the WAIT instruction.

Due to the byte-wide organization of the iRAMs, there is
plenty of time between video read cycles to allow CPU
access to the memory. With a pixel rate of 6 MHz, the
byte~wide iRAM has a video read rate of 6/8 MHz or
once every 1.33 microseconds. Only 350 ns of this time is
needed-for a video read cycle. The balance of the time
(approximately l!-'sec) can be used by the CPU to access
the memory. This interleaving of CPU cycles with video
timing cycles, combined with allowing the CPU unrestricted access to the memory during both horizontal

T~ 4-bit counters are used to count the REFEN pulses.
After 128 pulses, the count goes high. On the next rising
edge of the system clock, TEST is reset to a zero, block~
ing any further REFEN pulses, clearing the counters,
and signaling to the processor that the burst is complete.
Note that one non-access cycle should be inserted after
TEST is set low to ensure that sufficient time has been
allowed for the last refresh cycle to complete.

Figure 33_ Burst Refresh Circuit

3-63

AP·132

Figure 3:4. Burst Refresh Timing
nature of bank selecti9n used (AO:AI decoding), more
than a couple of consecutive accesses to ,anyone bank
are highly unlikely.

5.5.2 SYNC REFRESH SYSTEM

The system in Figure 35 represents one way in which synchronous refresh could be employed using the 2187. In '
this configuration, memory is divided into four banks,
selected via the two least significant addresses. To ensure
data integrity, each of the four banks must receive 128
REFEN pulses every 2 ms. In this system if anyone bank
is accessed, ea<:h of the other three banks receives a refresh pulse. Minimum cycl~ time cannot quite be attained
because the cycle time for the refresh cycle is the same as
that for an access cycle, and the fact that a one-gate
delay exists between CE to one device and the REFEN to
the others. At least 16 ns must be added to the minimum
cycle time of 425 ns. This number is derived by taking
the propagation delay difference between a "fast"
74155 and a "slow" 74155, and adding the maximum
delay through a 74811. This gives the CE to REFEN
delay time. This extra delay is not really critical in most
systems; the minimum cycle time for a 5 MHz 8086 is
800 ns.

One caution to note" however, has to do with powerdown refresh. If REFEN is kept low for longer than one
timer period, the timer will begin to time out. In this
, event, a period oftime (RFHEL) must be allowed before
CE can go low again after REFEN returns high. This, is
to ensure, that if a timer initiated refresh cycle started
just as REFENreturned to high state, it will have time
to complete before an access cycle is started.

6 SYSTEM CONCEPTS
6.1 System Reliability
New applications for microprocessor systems appear
almost every day. They appear in microwave ovens, automobiles, word processors, home computers, video
games, vending machines, lighting controls, medical
equipment, etc. The list' goes on' and on. Failures on
these systems cover equally broad ranges: acute annoy- ,
ance (such as losing your last quarter to the ,coffee machine), financial loss (a double debit is added to your
bank statement by an electric teller'inachine), and life
threatening system failures (the electronic carburator
control on your car faiis, opening the throttle wide
open).

With the circuitry described, data integrity would be
jeopardized if one bank were accessed consecutively too
many times, since the accessed bank would receive 'no
REFEN pulses. Assuming a 500 ns cycle time, one bank
would have to be accessed at least 30 consecutive times
to jeopardize data. This is the worst case. In actual oper~
ation, consecutive accesses to one bank could be many
more than this, as long as operation during any 2 ms period provides 128 REFEN pulses to all banks. Due to the
3-64

Ap·132

In many applications, relilibility is important enough to
. / be designed into the system. The computer memory sys- tern is one of the system components for which reliability is important. Also it is' one ofthe few system elements
which can be easily designed to enhance its reliability.
Since memory system reliability is inversely proportional
to the number of devices in the system, a system of a
given size should be designed with as few components as
possible. For example, a 32K byte system could be designed with sixteen 16K 2118 DRAMs. The system
MTBF (Mean Time Between Failures - the "up" time
of a system) could be calculated from the combined device soft and hard error rates (See Intel Application Note
AP-73 "Eee #2 Memory System Reliability With
Eee" for a model tQ calculate system MTBF's). The.
point is that, whatever the calculated system MTBF, the

2186 will be several times more reliable in a system due
to the lower device count.
A few example calculations are tabulated in Table 1.
Essentially what is shown is what the maximum acceptable
device soft error rate is for a specified system MTBF. For
example, if a design using 8K x 8 RAMs requires a
memory system MTBF for two years, and the system size
is 16K bytes, then the design allows a device."with a soft
error rate of 3. 1ll7o/1K-hrs. The 2186/87 soft error rate
goal is more than an order of magnitude better than that!
From the chart it can be seen that a 64K byte extra-reliable
memory system with a 10 year MTBF requires a device
with a soft error rate or 0.15Il7o/1K-hrs. Clearly the
2186/87 family ofiRAMs is reliable over the entire spectrum of typical application memory sizes.

Figure 35. Synchronous Refresh Scheme
Table 1. 2186/87 SER Data
No. of
Syst.
Rows

No.
of
Dev.

Sys.
Size

Elf.
Cycle
Time*

Maximum Allowable SER (%/K-Hrs.) .
1 Yr. MTBF
(8800 Hrs.)

2Yrs. MTBF
(17600 HI's.)

5Yrs. MTBF
(44000 Hrs.)

10Yrs. MTBF
(88000 Hrs.)

'" All times in microseconds
System has a 7p.Sec device cycle time.
Hard error rate=O.02'7o/IK-Hrs.

3-65

AP·132

6.2 Circuit Design Considerations

Skew is defined as simply the difference between the
maximum and minimum propagation delays through
devices in a parallel path. Figure 36 is a simple example.
Best case propagation of sigrial A is 6 nanoseconds versus worst case delay of signal B which is 16 nanoseconds.
This condition equates to 10 nanoseconds of skew
(Figure 37) which adds directly to system access or cycle
time. The worst case number of 16 ns would be used for
timing analysis in this 'type of delay calculation;
however, often the best case is the most important. For
example, as in Figure 38, the skew of concern deals with
the best case arrival of a write pulse versus worst case ar~
rival of data to a memory device.

Integrating components into systems requires a keen
awareness of basic concepts on the part of the designer.
Techniques for designing optimal performance memory
systems have been thoroughly covered in other literature. Two useful documents that cover these procedures
are AP-74 "H{gh Speed Memory System Design Using
the 2147H" and AP-133 entitled "Designing Memory
Systems/or Microprocessors Using the1ntel2164A and
2118 Dynamic RAMs. " There are essentially three areas
of major concern in a memory system design:
• Timing delay calculations. in the critical path
(worst case timing analysis)
• Memory circuit trace layout
• Power distribution and decoupling

SKEW-DIFFERENCE BETWEEN MAXIMUM AND
MINIMUM PROPAGATION DELAY THROUGH
DEVICES IN A PARALLEL PATH.

The following sections summarize these techniques as
they apply to the 2186 and 2187 iRAMs.
6.2.1 DELAY CALCULATIONS;

All memory designs requir)l a timing analysis to ensure
proper operation and compatibility of the memory and
the processor. Timing skews, capacitive delays and
propagation delays allihave to be accounted for in a
proper analysis. Propagation delay design rules for TTL
are furnished in the manufacturer's data book. The
maximum delay is the data book maximum and the
typical delay (usually useless for design) is the data book
typical. Intel has determined in work with TTL device
manufacturers that the minimum propagation delay is
y, the data book typical value.

DELAY MIN DElAY MAX -

2 ns
5 ns

2 ns
6 ns

DElAY MIN DElAY MAX -

SIGNAL "S'.
(DELAYED)
. . SKEW

f
I

P~TH

16 ns (MAX)==*
I
.

PATH "B" DEVICES
OPERATING AT
MAX,

~
~

SKEW:
SIGNAL "A" SIGNAL "S':

•

"A" DEVICES

OPERATING AT
MIN.

~-Ti--------------------.

2 ns
S ns

Figure 36. Skew

--l6-n-S~(M-I-N}--t==--------------------'.

~""-----------DELAYED

SIGNAL"Aoo~

SIGNAL ''-Aoo
(DELAYED)

2 ns ,
5

=MAX-MIN=1~ns-6ns

TO -~ 10 ns ISKEWI

ADDS DIRECTLY TO SYSTEM ACCESS/CYCLE TIME

Figure 37. Skew Timing

3-66

inter

Ap·132

capacitance, use the following standard derating factors:
Schottky TrL=O.OS ns/pF
Low Power Schottky TTL=O.1 ns/pF
Standard TTL = 0.7S ns/pF

WE TO DATA SKEWS PROHIBIT USE OF COMMANDS
DiRECTLY FROM 8086 PROCESSOR
CASE 1 -

DATA NOT VALID AT WRITE

~:ALlD

WORST CASE DA': FROM 8086
BEST CASE CAs/WE,FROM 8203

Add up all of the capacitance connected to a driver, including the circuit-printed trace capacitance of 2 pF per
inch, subtract out the manufacturer's capacitance drive
specification, (typically IS pF) then multiply this capacitance by the derating Jactor for the driver. This net result
is the additional delay due to capacitance. The equation
is:

~_
+-__
_
r:IDS

CASE 2 -

NOT ENOUGH TIME TO WRITE

BEST CASE CAS FROM 8203
WORST CASE COMMAND
FROM 8086 (MWTC)

DC = [ECIO + ECPCB - CSPEclTo

= delay due to capacitance
= sum of all input/output connections
attached to driver
ECPCB = 2 pF x number of inches of circuit
trace attached to driver
CSPEC = specified drive capacitance of driver
= capacitive derating factor
To

where: Dc

ECIO

Figure 38. Worst Case Timing

Unbalanced capacitive loading on address or control
line drivers also contribute to skew. Capacitance contributes to risetime degradation on these signals. The unbalanced loading causes differing rise times a~ shown in
Figure 39. The different rise times reach a logic threshhold at different times, contributing to skew. In all of
these examples, skew contributes to the overall delay,
and the goal of the designer is to minimize these skews.
Afew simple rules will help to achieve this in 2186/87
memory system ,design:
• Select logic gates for minimum delay per function
• Place parallel paths in the same package (device to
device skew is much less within sam~ package - O.S
ns max for STTL)
• Balance the output loading of device drivers to
equalize capacitive delays.'

6.2.2 TRACE LAYOUT

Address lines need to be kept as short and direct as possible. Route address fines in a comb-like fashion from a
central location. Routing control and address signals
together from a centralized bdard area will also
minimize skew.
Allow for proper termination of all address and control
lines because these circuit traces are actually transmissiOli lines. A series resistor close to the driver is the
recommended termination technique. Thirty-three ohms
is a good typ'ical value, although actual values are usually determined empirically. Figure 40 shows P.C.B. artwork that embodies these ,rules as well as proper power
and ground gridding with decoupling as described in the
following section.

SCHOITKY TTL CAPACATIVE LOAQING EFFECTS

6.2.~ POWER SUPPLY DISTRIBUTION

AND DECOUPLING.

TIL INPUT'
lOAD'
CAPACITANCE

Ground and power busses can contribute to excess noise
and voltage drops if not properly structured. The power
and ground network do not appear as a pure low
resistance element but 'rather as a transmission line,
because the current transients created by the RAMs are
high frequency in nature.

•• .. ·100 PF
---200 PF
-300PF

Figure 39. Capacitive Loading Effects

As previously stated, capacitance contributes to signal
risetime degradation. To determine the delay due to

Transient effects can be minimized by adding extra circuit board traces in parallel to reduce interconnection inductance. Extrapolation of this concept to its limits will
result in an infinite' number of parallel traces, or ,an ex,tremely wide low impedance trace, called a plane. Arranging power and ground voltages by plane provides
the best distribution; ~owever, correct gridding can cost
effectively approximate the benefits of planar distribu3-67

Ap·132

tion by surrounding each device with a ring of power and
ground traces (Figure 40).

generation is significant and must be dealt with during
design.

Consider two aspects of the memory device that contribute to power system noise: the active/standby power
modes of the RAMs, and the drive requirements of the
data I/O buffers. In a typical microprocessor-based
system, address space is ,divided into blocks of RAM,
ROM/EPROM, and I/O. When the microprocessor is
not accessing a given RAM, the RAM is usually deselected and in a power standby mode. When a previously
unselected RAM is selected, a large current surge is experienced. Because the connections supplying power to
the device will involve resistance and inductance, a
voltage variation will occur in association with the current surge in accordance with the equation:
V = Ri + Ldildt,
where V = instantaneous voltage,
L = inductance,
R = resistance,
and
= instantaneous current

Another factor that contributes to current surges are the'
drive requirements of the memory devices data I/O buf- .
fers. Consider first an I/O buffer outputting a logic one.
To accomplish this, the buffer must supply a current to
charge the capacitance of the line that it's driving to a
logic one level. This operation places a higher current requirement than normal on the Vee bus. Conversely, if
the I/O buffer is outputting a logic zero, it must discharge all of the capacitance on the line to ground. This
. produces a current surge to the ground bus, possibly
raising the local Vss potential above ground during the
transient.
The solution to this problem is to use a solid plane Vee
and ground bus on a P.c. board or use a proper power
and ground grid combined with adequate decpupling.
Adequate decoupling is also important in circuit design
to minimize transient effects on the power supply
system. For best results with the 2186/87,decoupling
capacitors are placed on the memory array board at
every device location (Figure 40). High frequency 0.1 JLF

Because a RAM may be selected and deselected hundreds of thousands of times a second, the transient noise

/
Vee

,.··
~.
..··'....~··..·'~IP·~...•..'~I
..~.·i
..~'...
.

GND

Figure 40. Example of Power and Ground Gridding

3·68

Ap·132

ceramic capacitors are the recommended type. Also included should be a large bulk decoupling capacitor in the
50 to 100 p.F range, placed where power is supplied to the,
memory system grid. In this arrangement, each memory
is effectively decoupled and the noise is minimized
because of the low impedallce across the circuit board
traces.

of DRAM density, power consumption, and price
without the added cost of designing the refresh control
circuitry. The 2186 and 2187 are the premier members of
this new byte-wide product family, designed for flexible
operation in virtually any microprocessor memory
system. By com forming to Intel's universal memory site
concept, these iRAMs are compatible with a wide variety
of byte-wide memory devices including SRAMs,
EPROMs, and E2PROMs.

7 SUMMARY

In sum'mary, Intel provides another innovative memory
product, the 2186/87 iRAMs - basic building blocks
for microprocessor memory solutions.

Intel's iRAMs provide a new approach to memory
design that allows the system designer to take advantage

Order Number: 210431·001

3·70 .

PREFACE
This application note has been developed to provide the memory system designer
with a detailed description of microprocessor memory· system design using Intel
Dynamic RAMs, the 16K 2118, 64K 2164A, and the 8203 Dynamic RAM Controller.
The 8086 bus interface to memory components is described and three major examples are presented and analyzed - ranging from simple to complex: the simple
solution, the 5 MHz No-WAIT State and the 10 MHz No-WAIT State systems. To
assist the designer, complete logic schematics, timing diagrams and system design
considerations are also .included in this application note;

3-71

Ap·133

Unfortunately, the simple cell has a drawback: the
capacitor is not a pure element and it has leakage. If left
alone, leakage current would cause the loss of data. The.
solution is to refresh the charge periodically. A refresh
cycle reads the data before it degrades too far and then
rewrites the data back into the cell. RAM organization is
tailored to aid the refresh function. As an example, the
Intel@2164A 64K RAM is organized internally as four
16K RAM arrays, each comprised of 128 rows by 128
columns. Consequently the row address accesses 128
columns in each. of the four quadrants. However, let's
concern ourselves with only one quadrant. Prior to
selection, the· bit sense line was charged to a high'
voltage. Via selection of the word line (row addresses)
128 bits are transferred onto their respective bit lines.
Electrons will migrate from the cell onto the bit line
destroying the stored charge. Each one of the 128 bit
lines has a separate sense amplifier associated with it.
Charge on the bit line is sensed, amplified and returned
to the cell. Each time the RAM clocks in a row address,
one row of the memory is refreshed. Sequencing through
all the ro~ addresses within 2 ms will keep the memory
refreshed.
.

1 INTRODUCTION
Matching the correct RAM to microprocessor application requirements isfundall1ental to effective product
design. A good understanding of the advantages and disadvantages of each technological approach and device
type will enable a memory system designer to best
choose the product that provides the optimalbenefit for
his particular design objective.

Two basic types of random access memories (RAMs)
have existed since the inception of MOS memories: static
RAMs (SRAMs) and dynamic RAMs (DRAMs). Where
highest performance and simplest system design is
desired, the static RAM can provide the optimum solutionior smaller memory systems. However, the dynamic
RAM holds a commanding position where large
amounts of memory and the lowest cost per bit are the
major 'criteria.
The major attributes of dynamic RAMs are low power
and low cost - a direct result of the simplicity of the
storage cell. This is achieved through the use of a single
transistor and a capacitor to store a single data bit
(Figure I).

In spite of the advantages of minimal cost per bit and
low power, the dynamic RAM has often been shunned in
microprocessor systems. Up until now, dynamic RAMs
have required a good deal of complicated circuitry to
support the refresh requirements, and associated timing
and interfacing needs. Circuitry for arbitration of
simultaneous data and refresh requests, for example,
has posed significant design problems. These require. ments all add to .the component count and system
overhead costs, both in design and implementation.

. BIT SENS:.:E;..;L",IN.:.:E'---r~_ _
ROW SELECT
TRANSISTOR
(WORD LINE)

-l

STORAGE
CAPACITOR

The development of the Intel family of dynamic RAM
controllers has brought a new level of design simplicity
to dynamic RAM memory systems. These new devices
include the solutions to the problems of arbitration, timing, and address mUltiplexing associated with dynamic

Figure 1. Dynamic RAM Memory Cell

The absence or presence of charge stored in the capacitor equates to a one or a zero respectively. The capacitor
is in series with the transistor eliminating the need for a
,continuous current flow to store data. In addition, the
input buffers, the output driver and all the circuitry in
the RAM have been designed to operate in a sequentially
clocked mode, thus consuming power only when being
accessed. The net result is low power consumption.
. Also, a single transistor dynamic cell as cOIl).pared to a
four or six-transistor cell of a static RAM, occupies less
die area. This results in more die per wafer.

1.1 2118 16K RAM

Because the manufacturing cost ofa wafer is fixed, more
die per wafer· translate into lower cost. For example,
assume a wafer costs $250 to manufacture. Yielding 250
die per wafer means each die costs one dollar. But, if only
'125 die are yielded, the cost per die is two dollars. The
rationale of the quest for smaller die size is obvious; the-simple dynamic memory cell fulfills this quest.

Thelntel 2118 is a high performance 16,384 word by I
bit dynamic RAM, fabricated on Intel's n-channel
HMOS technology. The Intel 2118 is packaged in the industry standard 16-pin DIP configuration, and only requires a single + 5V power supply (with ± 100/0
tolerances) and ground for operation, i.e., VDD (+ 5V)
and Vss (GND). The substrate bias voltage, usually

I~AMs.

This application note describes two basic memory
systems employing tlie use of the Intel® 2164A and 2118
dynamic RAMs in conjunction with the Intel® 8203 DynamicRAM Controller and the Intel 2164A, 64K dy.
namic RAM with a high speed TTL controller.

3·72

intel'

Ap·133

operate with a single + 5V power supply with ± IOOJo
tolerences. Pin I is left as a no-connect (N/C) to allow
for future system upgrade to 256K devices. The use of a
single transistor cell and advanced dynamic RAM circuitry enables the 2164A to achieve high speed at low
power dissipation.

designated VBB, is internally produced by a back bias
generator. The single + 5V power supply and reduced
HMOS geometries result in lower power dissipation and
higher performance,
1.1.1 2118 DEVICE DESCRIPTION

The 2118 pin configuration and performance ratings are
shown in Figure 2, Note that pins I and 9 are N/C (noconnects), This allows for future expansion up to 256K
bits in the same device (package). For a rigorous device
description, refer to AP-75, "Application of the Intel
2118 16K Dynamic RAM."

1.2.1 2164A DEVICE DESCRIPTION

The 21!)4A is the next generation high density dynamic
RAM from the 2118 +5V, 16K RAM. The 2164A pin
configuration and performance ratings 'are shown in
Figure 3. For a detailed device description, refer to
AP-13I, "Intel 2164A 64K Dynamic RAM Device Description. "

Access TIme (ns)
Cycle TIme (ns)
Operating Current (rnA)
Standby Current (rnA)

Access Time (ns)

Cycle Time (ns)
Operating Current (rnA)

Standby Current (rnA)

Figure 2. Intel® 2118 Pinout
1.2.2' 2118 ADDRESSING

Figure 3. Intel® 2164A Pinout

Fourteen addresses are required to access each of the
16,384 data bits. This.is accomplished by mllitiplexing
the addresses onto seven address input. pins. The two
7-bit address words are sequentially latched into the 2118
by the two TTL level clocks: Row Address Strobe (RAS)
.and Column Address Strobe (CAS). Noncritical timing
requirements allow the use of the multiplexing technique
while maintaining high performance. For example, a
wide t RCD window (RAS to CAS delay) allows relaxa- ,
tion of the timing sequence for RAS, address change,
and CAS while still permitting a fast tRAC (Row Access
Time). "

1.2.2 2164A ADDRESSING

Sixteen address lines are required to access each of the
65,536 data bits. This is accomplished by multiplexing
the 16-bit address words onto eight address input pins .
The two 8-bit address words are latched into the 2164A
by the two TTL level clocks: Row Address Strobe (RAS)
and Column Address Strobe (CAS). Noncritical timing
, requirements allow the use of the multiplexing technique
while maintaining high performance.

Data is stored in a single transistor dynamic storage celL
Refreshing is required for data retention and is accomplished automatically by performing a memory cycle (read, write or refresh) at all row addresses every 2
milliseconds.

1.2 2164A 64K RAM
The Intel 2164A is a high performance 65,536 word by
I bit dynamic RAM, fabricated on Irltel's advanced
HMOS-D III technology. The 2164A also incorporates
redundant elements. Packaged in the industry standard
16-pin DIP configuration, the 2164A is designed to

Data is stored in a single transistor dynamic storage cell.
Refreshing is required for data retention and is accomplished automatically by performing a memory cycle
(read, write or refresh) on the 128 combinations of Ao
through A6 (row addresses) during a 2 ms period. Address input A7 is a "don't care" during refresh cycles.
Thus, designing a system for 256 cycle refresh at 4 ms in
a distributed mode automatically provides 128 cycle
refresh at 2 ms and a more universal system design.

1.3 Compatibility of the 2118
and the 2164A
In 2118 memory systems designed for upgradability, it is
now possibl~ to take advantage of the direct upgrade,
3-73

AP·133

path to the 2164A. The common pinout and similarities
in A.C. and D.C. operating characteristics of most
systems make this upgrade easy and straightforward. A
simple jumper change to bring the additional multiplexed address into the memory array, a check for pro-'
per decoupling, and the replacement of t):!e 2118's with
2164A's usually completes the job. In the two sections
that follow, both device and system level compatibility
issues are examined, key parameters are compared, and
implications discussed. A data sheet for each device,
should be handy to aid in understanding the following
material.

2164A exceed those of the 2118-15, as well as those timings specific to the read and refresh cycles. Noteworthy
are the t RWL (write command to RAS lead time) and
tCWL (write command to CA~ lead time) specifications
of the 2164A. These are 60 ns less than those of the 2118,
allowing more flexibility in timing generation of the
write cycle: One other improvement is tpc (page mode,
read or write cycle) which is 125 ns. This parameter
allows, for the first time, a two-fold performance advantage for page mode called extended page mode. This is
offered as an option to read or write an entire page (row)
of data during a single RAS cycle. By providing a fast
tpc and long RAS pulse width (tRPM2), the 2164A-15
S6493 permits high-speed. transfers of large blocks of
data, such as required in bit-mapped graphics applications.

1.3.1 DEVICE COMPATIBILITY
Both the 2118 and 2164A are packaged in the industry
standard 16-pin DIP. Observation of the device's pinout
configurations shows that the only difference is the additional multiplexed address address input on pin 9 of the
2164A. This extra input is required to address the addi. tional memory within. Notice the N/C (no connect) on
pin 1 of the 2164A. This allows for another direct upgrade path to the 256K DRAM device, with pin 1 used as
the next address' input. The first and most obvious
specifications to compare are the speed and cycle times.
Clearly, when discussing compatibility and upgradability the same speed devices must be examined. A glance ~t
the respective data sheets shows that the 2118-15 and the
2164A-15 are the current devices available that are speed
and cycle time compatible, and further discussion will
center on these two specific device types.

There are a few of the 2164A timing' specifications
however, that exceed those of the 2118. These are:
tCAC (access from CAS) = 85 ns, 5 ns greater
than 2118
tRAH (row address hold time) = 20 ns, 5 ns greater
than 2118
tCAH (col address hold time) = 25 ns, 5ns greater
than 2118
tRCD (RAS to CAS delay time) = 30 to 65 ns,
versus the 2118, 25 to 70 ns
Usually only the tRAH specification has significance in
system applications. This and all other system level compatibility issues are discussed in the following section.

1.3.1.1 D.C. and Operating Characteristics
Both the 2164Aand the 2118 function in the same temperature environment (0-70°C) with a single 5 volt
± IOOJo power supply. All signal input voltage level
specifications are identical. The input load currents and
the output leakage currents are also the same. The
operating currents (IDDI' IDD2' IDD3, IDD4) of the
2l64A are greater than the 2118 because of the increased
density of the 2l64A. One other parametri~ difference
worth pointing out is the maximum capacitive load of
the control lines on the 2l64A. The maximum specificaand CAS lines, each respectively
tion is 8 pF'on the
1 pF greater than the 2118.

1.3.1.2 A.C. Characteristics
As mentioned above, the tRAC (access time from RAS)
spec of the 2164A-15, is a perfect match to the 2118'15.
G~nerally, the other A.C. timing specs of the 2164A
meet.or exceed those of the 2118. Both the read and
write cycle times (tRe> of the 2164A-15 are 60 ns less
than the 2118. Theread-modify-write cycle of the 2164A
runs 130 ns faster than the 2118. All parameters in the
write cycle (reference 2164A data sheet page 3) of the

1.3.2 SYSTEM LEVEL COMPATIBILITY
When designing a new system, the current (IDD) requirements of the 2164A do not present any particular
problems. Simply proceed with the normal power requirement analysis, and specify the power supply ac,cordingly. (A method for determining memory system
power requirements is detailed in Intel application note
AP-131 titled: Intel 2164A 64K Dynamic RAM Device
Description.) In a system being upgraded with 2164A
devices, check the new power supply reqirements against
the current power supply specifications to insure compatibility. Worth pointing out is the fact that in a 2118
system arranged as 64K by 16-bit word (32 devices) the
power/bit of the 12118-15 is 2.6 microwatts/bit (see
AP c75 , pp. 11-12). Replacing the 2118's with 2164A
DRAMS creates a 256K by 16-bit word (again, 32
devices) and the power per bit is 1.33microwatts/bit (see
AP-131 , pp. 11-12). The quadrupling in memory size
does not quadruple power supplYrequirements.
For a 64K by l6-bit to 256K by 16-bit conversion, the
additional powe~ required is 2.89 watts. (5.59,watts for
the 2164A system - 2.7 watts for the 2118 system). On
3-74

Ap·133

the other hand, to build a 64K by 16-bit system with
2118 requires 2.7 watts versus. only 1.4 watts for the
2164A, meaning that for a given system size, there is a
significant system power system savings by implementing the design with the 2164A.

system, and >. is the device failure rate. This equation
(MTBF = lin>.) says that system reliability is inversely
proportional to the number of devices in the system.
Therefore, a 1 Megabyte system (or any given system
size) built with 2164A devices is four times more reliable
as one built with 2118s.

The difference in current (I DD) specifications leads to
another system consideration, that of decoupling. The
larger current transients generated as a dynamic RAM
internally powers up as a response to refresh cycles or active cycles requires decoupling to keep noise off the
power grid and to prevent a transitory local voltage drop
across devices. Specifics of calculating local and bulk
decoupling requirements are presented in Section 6.3.4,
but in general Intel recommends .1 I'F high frequency
ceramic capacitors for every 2164A device, and 100 I'F
bulk decoupling for every 32 devices.

In summary, when upgrading a system to 64K devices,
increase the decoupling, check the power supply, and
tweak the timing only if necessary, then enjoy the improved system reliability; When engineering a new
design, become familiar with and be aware of the specification differences between the 2118 and the 2164A.

2 MICROPROCESSOR SYSTEM·
To effectively design a microcomputer memory, an
understanding of both the RAM and the microprocessor
is necessary. Since Intel microprocessors have been welldocumented in other publications, this applications note
will mainly focus upon operation during bus cycles as
related to the. memory interface.

In comparison to the 2118, the R,AS, CAS lines of the
2164A RAM have I pF additional load. This seems trivial on a device level, but in a system the extra capacitance
adds approximately .1 ns/pF propagation delay (assuming low power Schottky drivers) to the overall system access path. With 16 devices per driver, this extra load
adds up to a measurable increase in propagation delay.
Determining additional delay due to capacitance is
standard engineering practice in a new design. When
upgrading a current memory system with .2164A
DRAMs, the additional delay also has to be considered.
Refer to section 6.2 for the formula to determine if the
additional loading is a concern in any specific application.
Of the four timing specifications where the 2164A-15 exceeds the 2118-15 usually only tRAH specification is of
concern. If, however, the system being upgraded is CAS
access limited rather than RAS access; then check the
timing to determine if the extra 5 ns on tCAC will require
system re-tuning. The column address hold specification
(tCAH) needs also be checked in this case. In the majority of DRAM systems, the access speed of importance is
tRAC, the RAs access time. When optimizing a memory
system to achieve the design's fastest access time, set the
t RCD spec, to a value less than t RCD maximum. In these
high performance systems, be sure that the tighter 5 ns in
the 2164A tRCD spec window doesn't push out the
system access time by that amount, or if it does, that it
still conforms to the system timing requirements.

2.1 iAPX 86 Bus Operation
The iAPX 86 bus is divided into two parts: control bus
and time-multiplexed address data bus. The bus is the
microprocessor's only avenue for dialog with the
system. The processor communicates with both the
memory and I/O via the bus. As a result, it must
necessarily differentiate between a memory cycle and an
1/0 cycle. In the minimum mode, this differentation is
accomplished with the signal MilO which remains valid
during the ·entire cycle. Therefore, this signal need not be
latched. In the maximum mode, the processor commits
to a bus cycle by means of three status bits transmitted to
. the bus controller which generates the control signals.
The bus cycle is divided into four times, referred. to as
t-states, independent of the mode. Duration of this
t-time (tcLcd is the reciprocal of the clock frequency into the microprocessor. During each of these states, a
distinct suboperation occurs. In t \, the address becomes
valid and the system is informed of the type of bus cycle,
memory or I/O. In addition, a clock called ALE (Address Latch Enable) is generated to enable the system to
latch the address. This is required because the address
will disappear in anticipation of data on the bus. Intended to strobe a flow-through latch, ALE becomes active after the address is valid and deactivated prior to the
address becoming invalid. At the end·of t2, the Ready
input is sampled. If it is low, the processor will "idle,"
repeating the t3 state until the Ready line is high, allowing the memory or 110 to synchronize with the
microprocessor. In t3, the read or write operation commences and the high order status bits become valid.

Reliablityqualification data for the2164A and 2118 are
identical with projections of less than .1 %/IK-hrs for
soft errors caused by ex particles and less than
.02%/IK-hrs for hard failures. This leads to a distinct
system reliability advantage of the 2164A over the 2118.
System reliability is qualified as MTBF (mean time between failure). This is the "up-time" of the system and is
defined as lin>. where n is the number of devices in the

3·75

inter

Ap·133

Finally in t4, the machine cycle is terminated; input data
is latched into the processor in a read cycle or in ~ write
cycle output data disappears. The relationship of the
signals for minimum and maximum modes are shown in
Figures 4 and 5. Exact timing relationships will be
developed throughout the text. The design problem involves making the microproces~or signals intc;!lIigible to
the dynamic RAM.

MN/MX . - Vee

M l i l i l - - - - -..

Riil-----.

COMMAND BUS

1-----.
DTIA 1-----.
,..----,
WE

DEN

8086
CPU

The timing analysis is to be given with a read cycle for
the minimum. mode configuration of Figure 6. Unlike
static RAMs which access from whenever every input
signal is stable, dynamic RAMs begin a cycle on a clock
edge after addresses are stable. This will introduce a: certain amount of delay in the logic path. The exact amount
depends on the complexity of the memory controller.
Two paths to access will be considered: first, the control
signal to data input and second, address stable to\ data
input. In the read cycle there are four control signals;
MilO used to differentiate memory and 110 cycles, RD
used to control the output enable, DT iR: and DEN are
controls for data flow. Of these only MilO is a concern
to the memory design. Without WAIT states, no cycle
can be longer than four clock periods.

1---..,

I
I

GND
ALEI---+f:--t

!-----'\.. 1 MEGABYTE

Minimum Mode Operation

Figure 4. 8086 Bus Timing -

---I----I----J

AMwe

Minimum Mode and Figure 5. 8086 Bus Timing - Maximum M6de
3-76

inter

AP·133

Referring to Figure 5, the following is obtained:

Using this equation and the results from Table I, tACC
can be calculated.

MEMCY:5 4 tCLCL
MilO is stable tCHCTV from the previous clock high
time tCHCL, but;

tCHCL = 1I3tCLCL

Table 2. tACC Calculations -

5 MHz

For the 5 MHz clock, tCLCL

Min Mode

8 MHz

10 MHz

600
375
300
=
132
90
80
=
+ 20
5
= + 30
+ 22
+ 22
= + 22
SUBTOTAL (ns) =
184 -184 132 -132 107 -107
tACc(ns)
416
243
193
=

3tcLcLlns)
tADDR(ns)
tDVCL(ns)
tlVOV (ns)

200 ns

solving for tCHcL,
tCHCL = 68 ns
But tCHCTV is 110 ns.
As a result, MilO is a stable worst case 32 ns after the
start of a memory cycle. For an 8086-2, tCLCL is 125 ns
and tCHCTV is 60 ns. Similarly, MilO is stable 17 ns
after the start of the cycle.

Table 3 shows the system access time from stable address
to input data required. This time is the summation of the
RAM access time plus the control logic delay time.

Address calculations must include the buffer delay
(Figure 7). Stable addresses from the processor are
available tCLAV into the cycle and ALE is active tCLLH
into the cycle (Table 1). Addresses are on the bus tCLAV
plus tIVOV (latch delay) or tCLLH plus tSHOV (buffer
delay from strobe). The worst case number (tADDR) is
the greater of these two numbers.

Table 3. Data Setup Time -

5 MHz
110
=
= -110
= - 22
= - 22

tCVCTV (ns)
tCLDV (ns)
tlvov(ns)
tDS(ns)

During a write cycle, access is not the issue, but the write
pulse width, the data setup and hold time with respect to
the write pulse are of concern. The pulse width is simply
tWLWH, while data set-up time must be calculated from
a clock edge. Dynamic RAMs latch input data on the
falling edge of the write enable pulse'l so the calculation
is critical. Data is valid tCLDv plus the buffer delay
tIVOV in t2 while the write pulse begins tcvCTV in t2:
Worst case condition is a skew such that tCLDV is a maximum delay while tCVCTV has a minimum delay.

_TIVOV_~
.

ALE(STB) - 1 - - - TsHov - OUTPUTS

----.

Figure 7. 8282/8283 Latch Timing
Table 1. Address Latch Delays -

5 MHz
tCLAV(ns)
tlvOV(ns)
Flow Thru (ns)

= 110
= +- 22
132
=

tCLLH(ns)
=
tSHOV(ns)
=
Latch Delay (ns) =

tcvCTC - (tCLDv + t lVOV)

10 MHz
From the calculations in Table 3, the leading edge of the
write pulse must be delayed in the minimum mode.
These calculations will be used later.

50
+ 22
-

50
+ 40

+ 40

Having examined the major timing parameters of the
minimum mode configuration, let's now check the maximum mode timings.

In the maximum mode configuration of Figure 8, the
system has another component - an 8288 bus controller
- which generates ALE and the read and write control
signals. In this configuration a memory read cycle is not
committed until tCLML into t2 whereas in the minimum
mode operation, the information was known in t 1. In
this respect, a maximum mode system access cycle is less
than 3tCLCL'

Flow through delay is the limiting factor of the 5 MHz
system, whereas delay from the latch strobe (ALE) is the
limiting factor in the fastest processors. Finally, data
must be inputted tDVCL plus tlvOV to the data buffer
prior to the fourth t-state. Access from stable addresses
is:

3-77

Ap·133

Table 5. tACC Calculations 5 MHz
MN/MX

SO
51
52

3tcLcdns)
tAOOR(ns)
tovCL(ns)
t'VOV(ns)

=
= 132
= + 30
= + 22

1 MEGABYTE
ADDRESS BUS

82
72
+ 20
5
+ 22
+ 22
99
184 -184. 124 -124
416
251

SUB TOT AL (ns) =
tACC(ns)

Max Mode

- 99
-

201

Access from the read command (MRDC) must also be
determined. MRDC is valid tCLML from,t2, causing access (tCA) from MRDC to be:
tCA

2tCLCL - tCLML - (tovCL + t,vav)

Using this equation, Table 6 shows the access calculations.
l6·BIT
DATA BUS

Table 6. Access From Memory Read·Command
5 MHz

To determine address delay, we will, again, examine the
data flow path and the delay from the latch opening.
The greater of these two numbers is the worst case time
delay (tADDR)'
Flow-thru Delay = tCLAV + t,vov
Latch Delay = tCLLH + tSHOV
Using these equations and previous data, Table 4 shows
how Flow-thru Delay can be calculated.

5 MHz

tCLAV(ns)
=
t'VOV(ns)
=
Flow Thru Delay =
15
tCLLH(ns) .
=
tSHOV(ns)
= +40
Delay from ALE =
55

10 MHz

50
+ 22
-

+ 22
82
15
+40
55

Access from' the m~mory read command· (M"ROC) is
much more stringent than address access. Consequently
both access paths must be consideed in system design.
The write cycle has the same limitation as access from
memory read command. Memory write is identified by
MWTC having the same timing as the memory read
command. Address timing is the same for both the read
and write cycles. The write pulse, twp is generated by
MWTC with a pulse width of one clock cycle plus maximum tCLML plus the minimum overlap into the next cycle (tCLMH)'

tCLcL + tCLML - tCLMH

For the 5 MHz, 8 MHz, and 10 MHz system, twp is
calculated as shown in Table 7.
Table 7. twp Calculations -

In each case in Table 4, the limiting delay is flow-thru-

5 MHz

time. Access time from address can now be determined.
Again, data must be valid tDVCL plus the input buffer
delay (t,vov) before the end of t3. For maximum mode
access from the address valid time is:
tACC

10 MHz

400
250
200
35
35
35
+ 20
5
= + 30
+ 22
+ 22
= +- 22
SUBTOTAL (ns) =
87 - 87
77 - 77
62 - 62
138
313
173
tCA(ns)
=
2tCLCL (ns)
tCLML(ns)
tOVCL (ns)
t,vov(ns)

Figure 8. 8086 Maximum Mode Operation .

Table 4. Flow·through Delay -

125
100
200
35
35
35
=
- 10
- 10
= - - 10
SUBTOTAL (ns) =
25 - 25
25 - 25
25 - 25
75
Iwp(ns)
175
100
=

ICLCL (ns)
tCLML (ns)
ICLMH(ns)

3tCLCL - tADOR - (tovCL + t,vov)

Using this equation and previous data (Table 4), Table 5
shows how t ACC can be calculated.
3-78

inter

Ap·133

Data setup tim!; (t DS) to the leading edge of the write
pulse occurs approximately one tCLCL time later. From
tCLCL, the maximum tDVCL plus the minimum tCLML
must be subtracted:

tos = tCLCL - (tCLI)V

LOW ORDER

ADDRESSES-'

tCLML)

Now tDS can be computed as shown in Table 8 by using
data from previous calculations and the data sheet.
I

Table 8. Data Setup (tos) Calculations Max Mode
5 MHz

r-'-.,.---'-~~WE
CAS
RASo

10 MHz

c.,-...,..--"--- RAS.

Using MWTC as the write pulse allows sufficient data
set-up time for the dynamic RAMs. These, then, are the
basic timing equations for the system of Figures 6 and 8.
They are.general in that timing requirements for different clock frequencies (Le., 9 MHz) can be calculated
using them. Armed with these equations, the designer
can now shape the control and address signal in the time
domain with a memory controller to meet the dynamic
RAM requirements.

'20 TTL PACKAGES REQUIRED TO IMPLEMENT REFRESH/CONTROL

Figure 9. Refresh Timing and Control
Block Diagram

Consequently, a large delay is injected every 2 ms. On
the other hand, distributed refresh steals a single cycle,
128 times periodically throughout the 2 ms. Evenly distributed, a refresh cycle occurs once every 15 microseconds. Again assume a 350 ns refresh cycle, and our 5
MHz system need only inject two WAIT. states (worst
case) each time. Thus distributed refresh is preferable in
almost all microprocessor systems.

In addition to converting address, MRDC and MWTC
into RAS, CAS, WE, etc., to satisfy both the processor
and memory, another task called refresh must be performed by the memory controller.
Performing the interface translation, providing refresh
and controlling the signal timing to the RAM requires a
controller that consists of six elements as 'shown in
Figure 9. Of these, the, most basic is the oscillator
because it fulfills two functions: pr,?viding a time base
for refresh interval timing lind establishing precise times
for RAS, CAS, etc., to the RAM. The operating 'frequency must be high enough to provide sufficient increments between timing signals. The relationship of
timing signals will be multiple periods of the clock frequency. In addition, the oscillator drives a countdown
or divide by N circuit to measure the time between refresh cycles. Refresh can be either burst or distributed.
In the burst mode, a refresh request would occur once
every two ·milliseconds to meet the dynamic RAMs'
needs. For a 16K or 64K RAM with 128 refresh cycle requirement, all 128 refresh ,cycles would be performed
consecutively. A disadvantage of this method is that the
memory is "out of service" for a long period of time.
Assume a 350 ns cycle time, then the time required to
,perform refresh is 350 ns multiplied by 128 cycles or 44.8
microseconds operating with a 5 MHz 8086; this
translates to 224 consecutive WAIT states.

Guaranteeing that all 128 refresh addresses are exercised
is the task of the refresh address counter. It consists of
an eight-stage binary counter. After the re(resh cycle has
been completed, the counter is advanced one count. Incrementing after refresh eliminates any concern regarding
, address settling or setup time as the counter' outputs are
changing. This would be a concern if the counter were
incremented as the refresh cycle started.
Because the counter cycles through all 128 addresses
every 2 milliseconds, it isn't required to be, in a specific
state after power on, i.e., it need not start at address 0
after power on.
Next is the arbiter - which can be the bane of every
memory design. Deciding whether a memory cycle is an
access cycle: or a refresh cycle is the .function of the arbiter. Refresh requests' are derived from the oscillator
which operates asynchronously with the system clock.
The arbiter will grant the request when a refresh request
is made and no memory cycle is occuring or pending. If
3-79

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"
an access cycle is in progress, the arbiter mustinhi.bit the
refresh cycle until the current· cycle is completed. The
same logic process occurs if a refresh cycle is in progress
and access is requested. This sequence flows smoothly
most of the time. The difficulty arises when refresh and
access are requested simultaneously. In every arbiter
there exists an infinitely small but very real time period.
when the arbiter cannot make· a decision, much less the
correct one. Consider the arbiter in Figure 10 - a simple
cross-coupled NAND or an R-S flip-flop.

Effective solutions have reduced performance to max- .
imize reliability. One such method is a two stage clocked
flip-flop per Figure 12.

HAS MULTIPLE STAGES
(MASTER/SLAVE APPROACH)

If both requests are made simultaneously, both would be
granted - an impossibility!

~.. REFRESH G~A.NT . .
..

MEM CYCLE GRANT

SLAVE

Figure 12. 8203 Arbitration Logic
In this configuration arbitration is performed at the seccond stage so that even if the first stage "hangs" all will
be settled by the clocking of the second stage.

Another arbiter frequently used isa D-type flip-flop as
in Figure 11. Here arbitration is attempted between the
clock and the D input. Violating the setup or hold time
with respect to the clock can cause the output to enter a
quasi-stable state of non-TTL levels for as long as·75 ris.
This timing is too long for many high performance
systems.

The timing and control section is the core of the control- \
let. Urider its guidance, addresses are si,itched for multiplexing. RAS, CAS, WE are produced and sequenced in
a fashion understandable by the RAMs. One other fea-

o OUTPUT

DATA
DTYPE
LATCH

CLOCK

FLIp· FLOPS HAVE HIGH GAIN/HIGH POWER/HIGH SPEED
MASTER HAS SCHMIDT TRIGGER INPUTS
MASTER/SLAVE HAVE DIFFERENT THRESHOLDS
FLlP·FLOP D·INPUT IS INTEGRATED TO FILTER GLITCHES
CROSS COUPLING (POSITIVE FEEDBACK) IS USED
DATA LOCKOUT ON D·INPUT IS USED

Figure 10 .. ArbiterCross·coupled NAND Gates

DATA

r---£.

'!=SETUPCLOC K
tHOLD~

CAN BE UP TO 75 nsec FOR A 74574

Figure 11. D·type F/F Arbitration

ture required is a handshake signal with the processor to
indicate whether or not the memory is ready to be accessed. This is usually implemented with a System Acknowledge (SACK) (an early signal in the cycle) which
indicates a receipt by the controller of a memory access
request, or by a Transfer Acknowledge (XACK, a signal
occuring later in the memory cycle), indicating the valid
memory data is available.

The final piece of the memory controller is the address
multiplexers and buffers to drive the memory addresses.
During the normal memory cycle the parallel addresses
from the bus must be reduced by one half through time
multiplexing. In addition refresh addresses must be applied to the array through this same address path. Buffers are shown to drive the capacitance of the array with
signals having sharp rise and fall times.
Figure 9 also shows the quantity of TTL packages required to impiement such a controller. Twenty TTL
packages are usually required for a controllt:r.
To design a controller with discrete TTL components
can take several man months of design effort. Typically,
four weeks for design, two weeks for timing analysis,
four weeks to build and debug prototypes, six weeks for
circuit board layout, and another four weeks to add additional features or to tweak the original design. Obviously, the Intel 8203 DRAM controller is a desirable
alternative.

A block diagram of the 8203 is given in Figure 13which
illustrates how these features are integrated.
2.2.1 OSCILLATOR

The Intel 8203 generates its timing from an internal shift
register which is crystal controlled. This method provides highly accurate control of the timing required for
dynamic RAMs. This method is superior to a monostable mulitvibrator approach where transients and unitto-unit timing accuracies are difficult to control.

2.2 8203 Dynamic RAM Memory
Controller
The Intel 8203 is a Schottky bipolar de,vice housed in a
40-pin dual in-line package. It provides, a complete

AH o·AH 7

ALo-AL7

•

dynamic RAM controller for microprocessor systems
and expansion memories. All of the system control
signals are provided to operate and refresh the 2117,
2118 and 2164A dynamic RAMs. To accomplish this,
the 8203 provides the following features:
• Directly addresses 'one-half megabyte of 2164A
/with external drivers)
' ____ _
• Provides address multipexing and RAS, CAS, WE
strobes
• Provides a refresh timer and an 8-bit refresh address counter
• Refresh may be internally selected for automatic
refresh in a distributed fashion
/
• Refresh may be externally requested to provide for
syrichronous or transparent refresh
• Compatible with Intel 8080A, 8085A,' iAPX 88
_ and iAPX 86 families of microprocessors
• Provides system acknowledge and transfer acknowledge signals
• Allows asynchronous memory and refresh cycle requests
• Provisions for external clock or crystal oscillator

MUX

MUX
TIMING

GENERATOR
REFRESH
COUNTER

Ril/s;
WR

pcs
REFRQ/AlE

X,/ClK ....

Figure 13. 8203 Dynamic RAM Controller Block Diagram,
3-81

The arbiter resolves all conflicts between any cycles that
are requested simultaneously. These cycles can be
generated from one of four places:

The outputs from the multiplexer are inverted from the
address inputs. This is immaterial to the dynamic RAM
, array and does notrequire inversion for proper system
operation.
2.2.5 TIMING AND CONTROL

I. Read Cycle Request - RD/SI input

The timing and control logic allows either a read, write
or refresh cycle to occur. After any read or write cycle
request, SACK (System ACKnowledge) goes active if
the cycle was not requested during a refresh cycle. If it
was, SACK is delayed until XACK, thereby requesting
WAIT states from the ~ycle requester.

2. Write Cycle Request - WR input
3. External Refresh Request '7" REFRQI ALE
4. Internal Refresh Request --.: (refresh timer shown in
Figure 13)
If a refresh cycle is in progress and a read or write cycle is
requested, the requesting device receives a "not ready" ,
until the present cycle is completed. After completion of
the present refresh cycle a response from the 8203 called
System Acknowledge, or SACK, will notify the requesting device of availability for use. Ifa read or write request occurs simultaneously with a refresh request, the
read or write cycle will be performed first, then the refresh cycle. Read and write cycle requests cannot occur
simultaneously during normal operation. If the 8203 is
deselected, only an internal or external refresh cycle request will be accepted. Once' selected, it will continue
with the present memory cycle if one is being performed.
(Hence the chip select input is, 'called protected chip
select, PCS, because the current cycle is always completed regardless 'of any other pending request.)

Figure 14 is a diagram of the 8203 pinout. Table 9 lists
the pin numbers, the symbols,and the function of each
pin when the 8203 is configured for the 64K option.
The 8203 has two ways of providing dynamic RAM
refresh:
1. Internal (failsafe) refresh
2. External refresh
Both types of 8203 refresh cycles activate all of the RAS
outputs, while CAS, WE, SACK, and XACK remain inactive.

2.2.3 REFRESH TIMER AND COUNTER

The refresh timer is a counter that increments on each
pulse from the clock input until it reaches a preset
number causing an internal refresh request to occur.
Note thatthis causes the refresh rate to be 8203 clock cycle dependent. External refresh requests will cause the
refresh timer to reset, but will not disable it.
The internal address counter contains the address that
will be used during the next refresh cycle. The counter is
incremented after each refresh, counting up to 256
before resetting to zero after 'all RAM addresses have
been refreshed. All current generation Intel DRAMs require a 128-cycle refresh, hence, the most significant bit
is ignored. However, this extra bit allows use of 256 cycle 4 ms refresh devices without changing the current
memory system design.

Figure 14. 8203Pinout
2.2.6 REFRESH CYCLES

Internal refresh is generated by the on-chip refresh
timer. The timer uses the 8203 clock to ensure that
refresh of all rows of the dynamic RAM occurs every 2
milliseconds. IfREFRQ is inactive, the refresh timer will
request a refresh cycle every 10-16 microseconds.

2.2.4 MULTIPLEXER

The multiplexer is controlled by the timing and control
logic. It presents to the address bus one of the following:
1. The contents of the refresh counter when there is a
refresh cycle

External refresh is requested via the REFRQ input (pin
34). External refresh control is not aviLilable'when the
Advanced-Read mode is selected. External refresh requests are latched, then synchronized to the 8203 clock.

2. ALo-6 on a RAS pulse
3. AH o-6 on a CAS pulse

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Ap·133

Table 9. Pin Description (64K Option)
Symbol

Pin No.

Type

ALo
ALI
AL2
AL3
AL4
ALs
AL6
AL7

6
8
10
12
14
16
18
24

Input
Input

AHo
AHI
AH2
AH3
AH4
AHs
AH6
AH7

5
4
3
2
I
39
38
25

Input
Input
Input
Input
Input
Input
Input
Input

Address High: CPU address inputs used to generate memory column address.

Input

Bank Select Input: Used to gate the appropriate RASo·RAS I output for a
memory cycle.

PCS

Input

Protected Chip Select: Used to enable the memory read and write inputs. Once a
cycle is started, it will not abort even if PCS goes inactive before cycle comple·
tion.

External Refresh Request

OUTo
OUTI
OUT2
OUT3
OUT4
OUTs
OUT6
OUT7

7
9
II
13
15
17
19
23

Output
Output
Output
Output
Output
Output
Output
Output

Output of the Multiplexer: These outputs are designed to drive the addresses of
the dynamic RAM array. (Note that the OUTo.7 pins do not require inverters or
drivers for proper orientation.)

.28

Output

Write Enable: Drives the write enable inputs of the dynamic RAM array.

CAS

Output

Column Address Strobe: This output is used to latch the column address into the
dynamic RAM array.

RAS o
. RAS 1

21
22

Output
Output

Row Address Strobe: Used to latch the row address into bank of dynamic RAMs,
selected by the 8203 Bank Select Pin (Bo).

XACK

Output

Transfer Acknowledge: This output is a strobe indicating valid data during a read
cycle or data written during a write cyck XACK can be used to latch valid data
from the RAM array.

SACK

Output

System Acknowledge: This output indicates the beginning of a memory access
cycle. It can be ,used as an advanced transfer acknowledge to ,eliminate WAIT
states. (Note: if a memory access request is made during a refresh cycle, SACK is
delayed until XAGK in the memory access cycle.)

X O/OP 2

Input

Crystal Inputs: These inputs are designed for a quartz crystal to control the fre·
quency of the oscillator. XI/CLK becomes a TTL input for an external clock if
X/OP' is tied to Vee.

Name and Function
Addr~ss

Low: CPU address inputs used to generate memory row address.

Inpu~

Input
Input
Input
Input
Input

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Ap·133

The arbiter will allow the refresh request to start a '
refresh cycle only if the 8203 is not in a cycle.
Internally, if a memory request and a refresh request
reach the arbiter at the same time, the 8203 will honor
the refresh request first. However .. the external refresh
synchronization takes longer than the memory request
synchronization so, relative to the 8203 input signals, a
simultaneous memory request and external refresh reo
quest will result in the memory request being honored
first. This 8203 characteristic can be used to "hide"
refresh cycles during system operation. A circuit similiar
to Figure 15 can be used to decode the CPU's instruction
fetch status to generate an external refresh request. The
refresh request is latched while the 8203 performs the instruction fetch: the refresh cycle will start immediately
after the memory cycle is completed, even if the RD input has not gone inactive. If the CPU's instruction
de~ode time is long enough, 'the 8203 can complete the
refresh cycle before the next memory request is generated.

The user can select the desired Read request configuration via the BlIOPI hardware strapping option on pin
25.
Normal Reads are requested by activating the RD input,
and keeping, it active until the 8203 responds with an
XACK pulse. The RD input can go inactive as soon as
the command hold time (tCHS) is met.
Advanced Re'ad cycles are requested by pUlsing ALE
while SI is active; if SI is inactive (low) ALE is ignored.
Advanced Read timing is similiar to Normal Read timing, except the falling edge of ALE is used as the cycle
start reference.
If a read cycle is requested while a refresh cycle is in progress, then the 8203 will set the internal delayed-SACK
latch. When the Read cycle is eventually started, the
8203 will delay the active SACK transition until XACK.
goes active. This delay was designed to compellsate for
the CPU's READY setup-and hold times. The delayed'SACK latch is cleared after every READ cycle.

Based on system requirements, either SACK or XACK
can be used to generate the CPU READY signal. XACK
will normally be used; if the CPU can tolerate an advanced READY, then SACK can be used. If SACK arc
rives too early to provide the appropriate number of '
WAIT states, then either XACK or a delayed form of,
SACK should be used.
,WR~--------------------------iffi

Figure 15. Hidden Refresh Generator,

After each refresh cycle, the 8203 increments the refresh
'counter, reloads the refresh timer, and clears the external refresh latch. If the external refresh request is held
active, the latch will be set again, and another refresh cycle will be generated. If, however, a memory request is
pending, it will be honored before the second refresh request. This feature prevents refresh from locking out the
memory request.

2.2.8. WRITE CYCLES

Write cycles are similiar to Normal Read cycles, except
for the WE output. WE is held inactive for Read cycles,
but goes active for Write cycles. All 8203 Write cycles
are "early write" cycles; WE goes active before CAS
goes active by an amount of time sufficient to keep the
, dynamic RAM output buffers turned off.
'
For a more detailed analysis of the 8203, refer to Application Note AP-97A, 'entitled "Interfacing Dynamic
RAMs to iAPX 86/88 Systems Using the Intel 8202A
and 8203."

Certain system configurations require complete external
refresh control. If external refresh is requested faster
than the minimum internal refresh timer (tREP) then, in'
effect, all refresh cycles will b,e caused by the external
refresh request, and the internal refresh timer will never
generate a refresh request.

3 SIMPLE SOLUTION
An example of the ease of interfacing DRAMs to micro-

processors with the 8203 is shown in Figure 16. This is an
example of the 8203 and 2118's or 2164A's configured as
local memory to a min mode iAPX 88 System. The CPU~s
local bus is demultiplexed by an 8283 which latches the
addresses and presents them to the 8203. Notice the lack
of TTL support circuitry. The only additional components are a latch for the dynamic RAM output data
and a OR gate to steer the WE signal on byte writes. The
8203 handles' all the interface requirements of the

2.2.7 READ
, CYCLES
'

The 8203 can, accept two different types of memory
Read requests:
1. Normal Read, via theRD input
2. Advanced Read, using the 81 and ALE inputs

3·84

intel·

AP-133

ity of the 16 bit 8086 to perform byte operation~ requires
two gates (shown on the diagram of Figure 17 between
the 8203 and the 2164A array) to steer the write pulse
output from the 8203 to either the high or low byte or
both bytes as directed by AO and BHE (Byte High
Enable).

DRAM array, rendering a very simple solution to a
dynamic memory design.
,Figure 17 is an 820312164A memory system configured
as a global resource to a max-mode iAPX 86 microprocessor system. Although there are several more TTL
components involved, the buffers and transceivers are a
requirement" for proper system bus interface design. In
terms of controlling the memory, the 8203 and 2164A interface is as simple as in the previous example. The abil-

These examples balance ease of use and design throughput time with performance. The designs shown typically
require one to two WAIT states. With one WAIT state,

Figure 1,6. 8203/2118 Local Memory System

MULTIBUS!l
TYPE
SYSTEM
BUS

Figure 17. 8203/2164A Global Memory System

3·85

intJ

AP·133

processor performance is reduced to 91.70/0, and with
two WAIT states it drops to 83.7%. This may be acceptable in many applications, but where it is not, a modest
additional design effort can yield zero WAIT states.

not a simple task in minimum 'mode operation because·
the iAPX 86 processor produces the RD and WR signals '
in a fixed relationship after ALE occurs. However,
operating in a max-moc~e, the iAPX 86 outputs three
status bits (SO, Si, S2) which occur ahead of the ALE
signal. (Refer to the timing diagram shown in Figure 18.)
With proper logic circuitry, these status bits can be used
to initiate the advanced signals required.

4 5 MHz NO·WAIT STATE SYSTEMf

4.1 Circuit Description

The following discussion describes a 5 MHz no-WAIT
state microprocessor memory system designed for optimum performance. Figure 19 shows an iAPX 86 maximummode system modified for zero WAIT states. The
circuitry added to the system previously described is enclosed in the dashed lines. The 8205 decodes the three
status bits (SO,Si, 82) and outputs an advanced read or
write signal at pin 13 or 14, respectively. These signals
flow through the corresponding 74S158 (a 2: 1 mux con-

The DRAM/8203 microprocessor memory system discussed up to this point met all of our design criteria except one - optimum performance. In minimum mode
operation, inherent delays in the system RD and WR
commands resulted in a READY signal that was too late
to avoid processor WAIT states. Attaining zero WAIT
states requires minimizing these delays by transmitting
advanced read {itD) or write (WR) commands. This is
T,

1;'- .1- ~TCHLL
f
\
.~

--I~~~::: b,,-I
TA. RL
-

B288 OUTPUTS
SEe NOTES 5, 6

ITe~leH~If=J I_TeL2eL1~~

Figure 18. 8086 Bus Timing - lVIaximum Mode System (using 8288)
3-86

intel'

Ap·133

figured as a high speed flow through latch) and are latched
on the falling edge of ALE from the 8288. Latch outputs
(ADV WRC and ADV RDC) are connected to the 8203
WR and RD inputs. The two latches are cleared by
clocking the trailing edge of either the memory read
command (MRDC) or memory write command (MWTC)
through a 74S74 flip-flop, System acknowledge (SACK

- used in place of XACK because it occurs sooner) is
returned to the 8284A which provides a synchronous
ready signal to the iAPX 86. The advanced memory
write command, AMWC, clocked to provide appropriatetiming with CAS, is ORed with WE to obtain
the WR forthe 2118's. The S2 status bit is latched by the
74S158 on the trailing edge of ALE.

------------

~I~

Figure 19. 5 MHz No-WAIT State Microprocessor Memory System
3-87

inter

AP·133

latest PCS is generated' by decoding CPU addresses and
arrives within 133 ns. The SACK signal is then returned
within 127ns from PCS. The buffered SACK is used as
the READY signal to the iAPX 86, resulting in zero
WAIT states (except when the 8203 is performing a
refresh cycle). The maximum PCS to CAS delay is
shown to be 245 ns. Also accounted for is the maximum
access time from CAS to data valid of 80 ns and a propagationdelay of 45 ns for valid data to reach the processor.

4.2 Analysis and Description of
System Timing
Read cycle worst case analysis is shown in Figure 20
which only considers the maximum time delays .. The
four processor t states are indicated by t 1 through t4' To
accomplish zero WAIT states, valid data must reach the
iAPX 86 by the end of t 3 minus 30 ns. The latest read
data arrives at the iAPX 86 (next to the last waveform)
within this time frame. Timing relationships are as
follows:

In the write cycle, the relationship between data and WE
at the memory and the relationship between the leading
edge of WE and the trailing edge of CAS (tcwd must be

The ADV RDC flows through the 74S158 latch ;md
reaches the 8203 within 6 ns after the rise of ALE. The

_127ns_
LATEST SACK
FROM 8203

RE"'OY INPUT
(BUFFERED SACK)
TO 8284A

TR1VCH=3sns-1

NECESSARY ASYNCHRONOUS
- - { READY SETUP AT 8284A TO
GUARANTEE NO WAIT STATE

-TACK=10ns

_ - 245ns--_

pes TO CAS DELAY
AT 8203 (MAX)

-TeAC

=80nsFOR
SLOWEST 2118

MAXCASS~~C::;T~~~~---t-----~-------\._D_A_TA_V_A_LlD_O_U_T_O·F_'_"_'_ _t--'
PROP DELAY 70 ns

LATEST READ OATA
ARRIVAL AT'8086

READ DATA

-+--------------/I\.--::M;;;Us;;:T-;;BE~~O FOR NO
1--_ _ _ _ _ _ 570ns~_ _ _ _ _-'-1r..cW~A~IT:..:S~TA~T~ES~·--

~;~:~~~~~~~~~-~----------~----~~V-AL-'D-D-AT-A-A-T-CP-U__
r-TDVCL

READ CYCLE WORST CASE ANALYSIS
8086 IN MAX MODE AT 5 MHz'
8203 AT 2S MHz

Figure 20. Read Cycle Timing Analysis (5 MHz)
3-88

intel·

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preserved. Since DRAMs write data on the leading edge
of the write pulse, data must be valid before the fall of
WE. Timing analysis of the skew of the normal memory
write command (MWTC) to valid data shows that worse
case, it is possible to have data arrive after the falling
edge of WE (case 1 of Figure 21). Using the other write
pulse available from 8288 bus controller, the advanced
memory write command (AMWC), led to the problem
depicted in Figure 21, case 2, violation of the DRAM
specification tCWL. From these observations, the need
for the clocked AMWC pulse becomes apparent. By
delaying the AMWC pulse until the next rising edge of
the system clock and then gating this signal with the WR
output from the 8203, a "best-fit" write pulse is created
that meets all timing requirements.

generation and arrival of timing signals to the memory.
Since the controller is CAS access (t CAe) limited, the
tCAC spec of the 2118 and the 2164A must be compared
for the read cycle. tCAC on the 2164A-15 is 85 ns, 5 ns
greater than the 21 }O8. This means that valid data will arrive at the 8086 processor 5 ns later, for the worse case,
using the 64K device. The read cycle timing analysis
shows this is still well within the 570 ns require~ent of
the 8086. During the write cycle, two parameters were of
concern in the 5 MHz system:
tDS (data set-up before CAS)
tCWL (leading edge of write to trailing edge of CAS)
Since the tDS spec is the same for both devices (0 ns), the
original timing analysis for this parameter is still valid
and the 2164A fits. The tCWL spec for the 2164A-15 is
40 ns. This is 60 ns less than the 2118-15, so that
substituting the 2164A actually relieves a tight timing
spot in this design. The additional delay added to control line paths due to larger input capacitances of the
2164A is accounted for in the 8203 specification (the
8203 is specified to directly drive four rows of 2118's,
only two rows of 2164A's for this reason). After adding
decoupling to meet the 2164A-15 requirements, the
2164A memory system is up and running, doubling
memory size and reducing device count by one-half.

WE TO DATA SKEWS PROHIBIT USE OF COMMANDS
DIRECTLY FROM 8086 PROCESSOR
CASE 1 -

DATA NOT VALID AT WRITE

WOR~T CAS:A': FROM 8086
BEST CASE CASIWE FROM 8203

,~VALID

-----""l_+-_
_
~tDS

CASE 2 -

NOT ENOUGH TIME TO WRITE

BEST CASE CAS FROM 8203

4.4 System Reliability

WORST CASE COMMAND
FROM 8086 (MWTC)

Figure 21. Write Cycle Problems

Figure 22 depicts the worst case analysis of the write cycle. The timing relationships are similar to those for the
read cycle with a few exceptions. The advanced write
command, ADV WRC, flows through 74S158 and is
latched by the fall of ALE. The earliest CAS occurs 145
ns after the PCS. Valid data is output from the CPU
within 210 ns and reaches the memory 35 ns later. The
advanced memory write command, AMWC, and associated progation delays must satisfy the tcwL.requirement
of the 2118's which starts at the beginning of the AMWC
pulse and terminates with the end of CAS:--'The write
enable, WE, from the 8203, is ANDed with AMWC to
obtain the WR for memory.

The majority of microcomputer systems are designed in'to applications where system failure ranges from irritating (such as a vending machine failure) to a financial
loss '(such as a double debit from an electronic teller
machine). While these are not life threatening failures,
reliability is important enough to be designed into the
system.
A memory system is one of the system components for
which reliability is important. Also it is one of the few
system elements which can be easily altered to enhance
its reliability. The inclusion of some additional hardware allows the CPU to keep check on the integrity of
the data in memory. Figure 23 represents a five TTL chip
solution that, when added to the 5 MHz design example,
allows error detection in the memory.
Because the 16-bit 8086 has the ability to do selective
high or low byte writes in addition to full word operations, parity needs to be generated and checked on the
byte level. This requires two extra memory devices per
row to store the parity bits of the high and low bytes.

4.3 Compatibility of the 2118 and 2164A
The 5 MHz no-WAIT state system was designed with the
2118-15 DRAM. By following the guide lines in section
1.3 and examining tight timing areas specific to this application, it can be shown that the system is expandable
and works equally well by using two rows of 2164A-15
parts in place of four rows of 2118-15 parts. The 8203,
when configured in the 64K mode; guarantees proper

Parity is generated by exclusive ~Ring all the data bits in
'each byte (accomplished by the 74S280) which results in
a parity bit. This parityoit is the encoding bit of each
byte. Because there are eight data bits, the parity bit Cis:
C = b 1 (j;) b2 ...... b 7 (t) bs where b = value in the bit
positions.

SACK FROM 8203
READY INPUT
(BUFFERED SACK)
AT 8284A

--'_-+____-/-__"

MIN ROY seTUP
AT 8284A == 35 ns

ICASMIN _ _

200 ns

EARLIEST CAS
FROM DELAY

LATEST VALID DATA

FROMCPU _ _ _ _ _ _ _ _ _~_ _'I~---~;_----------J
22 ns PROP DELAY

LATESTVAUQDATA.

VALID DATA AT MEMORY
ARR'VALAT2118 _ _ _ _ _ _ _ _ _ _ _ _ _/I\.--~~----------....I

MIN=,,",
EARLIESTWii

} ORedtoGETWR

FROM 82{13

FOR 2118
EARLIEST CLOCKED

AMWC _ _ _ _ _ _ _ _ _ _ _.,...._,1

AT 74532 ON

~--

MEMORY CARD

8086 IN MAX MODE AT 5 MHz
8203 AT 25 MHz CLOCK
EARUEST CLOCKED

+ PROP

AMWc

-------------i.

DelAYS = YIR AT 2118
TDSMIN "" 8 ns WORST CASe"

l---t--'II--___ TDH
. 100 ns'

WRITE CYCLE WORST CASE ANALYSIS

TCWLMIN

'CRITICAl TIMING FOR ZERO WAIT STATES

Figure 22. Write Cycle Timing Analysis

74508

iNfA '>----r-...
iiWR.;.RESET

,Figure 23. Parity Checker/Generator

3·90

AP~133

i
,I
Using the encoded word "010" one possible double bit
error (DBE) is: '
111

The parity bit combines with the bits from the original
data byte to form the encoded \lalf-word (9-bit byte).
Encoded words always have either "odd" parity, which
is an odd number of Is (an odd'weight) or "even" parity
which is an even number of Is (an even weight). Odd and
even parity are never intermixed, so that the encoded
-words have either odd or even. parity - never both.

L-- Parity
Checking parity:
C=I(j)I=1

When the encoded' word is fetched, the parity bits are
, removed from the word and saved. Two new parity bits
are generated from each byte. Comparing these new
parity bits with the stored parity bit determines if a single
bit error has occurred in either byte.

The transmitted parity and the regenerated parity agree.
Therefore the technique of parity. can detect. only an odd
number of errors.
'
In the circuit of Figure 23, parity is generated and checked
in the same devices - the 74S280 pair. Should a parity
error occur in either the high or low byte (or both) the errodlip-flop is set, causing an interrupt to the,8086 to occur. When the 8086 responds with INTA (interrupt acknowledge) the flip~flop is reset. INTA also enables the
74S244 which gates the interrupt number onto the data
bus. The interrupt request signal to the CPU indicates a
memory error has occurred. The nature of the interrupt
procedure is heavily dependent on the user application,
but' typically ranges from retry or recovery routines to
simply turning on the parity error light and proceeding.

Consider the two bit data word whose value is "01".
Exdusive-NORing the two data bits generates a parity
bit which causes the encoded word to have odd parity:
C = 0(j)1

C=O
The encoded word becomes:
Data
Generated Parity Bit
01
0
Assume that an error occurs and the value of the word
becomes "1'10." Stripping off the parity bit and
generating a new parity bit:
transmitted parity == 0
transmitted word = 11

One other software consideration for this circuit is the'
requirement to initialize all the memory to a known
state. This initialization is needed to properly encode all
the memory to even parity. This is typically done upon
power-up by writing ze~os into all memory locations
prior to program storage.

New parity of transmitted word = 1 (j) 1 = 1; generated parity", transmitted parity.

In summary, single bit parity will detect the majority of
errors, but cannot be used to correct errors. Using parity
introduces a measure of confidence in the system.
Should a single bit error occur, it will be detected.

Note that the error could have occurred in the parity bit
and the final result would have been the same. An error
in the encoding bit as well as in the data bits can be
.
detected.

For a detailed treatment of error detection and also
techniques for error correcting, refer to Intel application
notes AP-46, "Error Detecting and Correcting Codes
Part #I,"and Application Note AP-73,"ECC #2
Memory System Reliability with Error ,Correction."

Although parity detects the error, no correction is possible. This is because each valid word can generate the
same error state. Illustration of. this is shown in Table
10.
Table 10. Pos'sible Errors
Possible Correct Word,
with Parity

Single Bit
Error

001
111
010

o 1 I,
o1 1
o1 1

4.5 Alternatives to 8203 Refresh
Control Designs
There are essentially four choices available when selecting a technique for refresh control circuitry. These are:
Separate c'ont~oller
CPU Hardware Control
CPU Software Control
Circuitry Internal to the RAM

Each of the errors is identical to th~ others and reconstruction of the original word is impossible.

Figure 24 is an implementation of a separate controller
design. This is a typical non-LSI version that requires 11
TTL packages, an 8282A octal latch, a .3242 address
multiplexer/refresh counter, two bidirectional bus
drivers, an 8212 octal latch and two active delay lines.

Parity fails to detect an even number of errors occurring
in the, word. If a double bit error occurs, no error is
ctetect,ed because two bits have changed state, causing
the weight of the word to remain the same.
3·91

Nothing is gained by using discrete packages where a
LSI device can be designed in. The plethora of TTL does
require a larger erlgineering effort exemplified by the cir·
cuit complexity and timing analysis for this circuit
(Figure 25). In terms of performance, the extra engineering effort can be fruitless - the CPU in this example is
forced into the HOLD condition every time a refresh cycle occurs, even if the meulOry is not being accessed.
This waiting period lasts 1.23 microseconds for every
refresh cycle performed. Contrast this with the 8203 circuit which runs without WAIT states (unless a refresh
cycle is in progress when the CPU requests a memory access, in whiCh case one WAIT state is inserted). The advantages of using the 8203 should be obvious by now.

usage of such a system however, precluding this type of
design in many applications.
To cite a. few disadvantages:
• CPU must run continuously - no single step,
HOLD, or extended WAIT states
• Multiprocessor operation is difficult
• CPU must always participate in memory operations
CPU software control of refresh is another alternative.
This· approach increases software development and
maintenance costs and may not be offset by the very low
or no hardware overhead for refresh. One method requires real-time analysis of all modules and possible
directions of the program, with branch-to-refresh instructions included in all paths so that a refresh procedure is executed at least every 2 ms. An option on this
technique requires a single interrupt time, which, when it
times out, interrupts the CPU, causing it to revert to the
burst refresh software routine.

Additional hardware closely coupled to the CPU timing
refresh for the microprocessor operation is one alternative to 8203 design. Some implementations include the
extra hardware within the microprocessor; rendering a
low cost, simple design. Wide restrictions govern the

(PAOCESSORADDRESSTAKESOVEABusf

600

00U1 (FROM BOUI

800

Figure 25. Timing Analysis Discrete Controller
3-93

1400

inter

AP·133

Figure 26 shows an ASM-86 implementation of a burst
refresh procedure. Accomplishing refresh in software is
simple: save all registers used, perform a read at each of
the 128 row addresses, then restore all registers and
return.
The pure software approach makes it very difficult to
make program changes and is limited to special applications. Also, since the refresh cycles are actually read
cycles, the memory consumes more power for' refresh
than in standard refresh cycles. Both software refresh

methods require that the CPU is always running, and
hence shares many of the disadvantages of a CPU hardware refresh design.
One approach to memory system refresh control is to
forge the entire system in silicon, incorporating the
dynamic RAM array and all of the refresh .control circuitry into one device. This, however, represents a
departure from classical,' dynamic RAM system design
methodologies and as such, are outside the scope of this
application note.

;*****************************************.*******************
BURST REFRESH ROUTINE IN ASM86
VERSION 1.0
MC APPLI~ATIONS LAB JAN 82

;

;~***********************************************************
CBEG SEGMENT
ASSUME CS:CSEG,DS:CSEG

;*************

BURST REFRESH INTERRUPT ROUTINE

**************

This procedure does .oftware refresh from an interrupt
performinS dumm~ reads On the first 128 device (row)
addresses •

.HARDWARE ASSUMPTIONS: RAS is common throuShout the arra~
with CAS decoded for a row select. An external timer
senerates the refresh interrupt ever~ 2 milliseconds.

;************************************************************
BURST:

BURS1:
REF:

PUS~

f'USH
PUSH
PUSH
MOV
MOV
MOV
MUV
MOV
))E(;

[lECLOOP

ISAVE REGISTER CONTENTS
AX
BX
CX
SI
BX, BASEAI'RS
DS,BX
-CX,REFCOUNT
SI,ADRCOUNT
AX,DS:[SIJ
51
51

REF

IPLACE SEG PNTR OF TARGET BOARD ROW IN BX
IINIT DATA SEG TO START OF A BOARD ROW
ISET LOOP COUNTER TO NUMBER OF DEVICE ROWS
IINIT MEM INDEX PNTR
IREAD 16 BIT WORD (DUMMY READ IS A REFRESH)
IDECREMENT REFRESH ADDRESS PNTR TO NEXT WORD
ILOOP ONCE FOR EACH DEVICE ROW

I 128 ROWS HAVE BEEN READ, (REFRESHED) SO EXIT

Exn:

POP
f'UP
POP
POP
IRET

SI
CX
BX
AX

IREST6RE REGISTERS

IRETURN FROM INTERRUPT

BASEADRS EGU 0000
REFCOUNT EGU 128
AURCOUNT EGU 256

ISET TO SEGMENT ADDRESS OF MEMORY
ISET,TO NUMBER OF DEVICE ROWS (128 FOR 2118)
ISET TO TWICE NUMBER OF DEVICE ~OWS

CSEG ENDS
END

Figure 26. PLM·86/ASM·86 Burst Refresh, Sheet 1 of 2

3·94

AP.-133

I~EFRSH:

DO;
BURSTREF: PROCEDURE;

II PROCEDURE PROVIDES A BURST REFRESH BY READING
ALL 128 DEVICE ROWS ON ALL BOARD LEVEL ROWSII

INCADR: PROCEDURECPTR) POINTER;
DECLARE

II INCREMENTS REFRESH ADDRESS POINTER II

PTR POINTER.
AtlR BASED PTR C2) WORD;

ADR(1)=ADRCl)+2;
RETURN PTR;
END INCADR;
INCBD: PROCEDURE (PTRIPOINTER;

IIINC WORD ADDRESS. I

1* INCREMENTS

~OARD

LtVEL ADDRESS POINTER II

DECLARE PTR POINTER,
ADDR BASED PTR (2) WORD;
ADDR(O)=ADDR(O)+03FFFHi
IF ADDR(ll=O THEN ADDR(OI=ADDR(O)+l;
RETURN PTR";
END INCHD;
DECLARE (BDROWIPTR,REFSPTR,STARTIPTR,LASTIPTR IPOINTER;
DECLARE (REF BASED REFIPTR,RDDATA I WORD;
DECLARE CDEVROWSI BYTE;
1* READ 128 ADDRESSES ON ALL BOARD ROWS II
DO;

STARTIPT~=20000H;

LASTIPTR=3FFFOH;
BDROWIPTR=STARTIPTR;
REF$PTR~START$PTR;

DO WHILE BDROWS~TR(=LASTSPTR;
J.lEVROWS=t28;
DO WHILE DEVROWS>=O;
R[IDATA=REF;
REFSPTR=INCADR(REFSPTR);
DEVROWS=DEVROWS-l;
END;
BDROWSPTR =INCBD(BDROWSPTR);
REFSpiR=BDROWSPTR; .
t:NII;

END;
END BURSTREF;
1* MAIN :tl
DO;
CALL BURSTREF;
END;

I
!

END REFRSH;

I
..

Figure 26. PLM·86/ASM·86 Burst Refresh, Sheet 2 of 2

3·95

Ap·133

One last technique for refresh control exists that doesn't
fit into any of the above catagories and is worth bringing
to light. Its use is heavily application dependent, hence
has the most severe limitations, but if it meets the design
requirements, its the most cost effective of all. The
memory must be configured so that all row addresses
will be strobed within 2 ms. Figure 27 is a block diagram
of an application where this is possible since successive
memory access addresses are predictable and defined.
The circuit depicts a simpified graphics terminal display
memory interfa'ce.' Assuming a requirement of a
512 x 512 display resolution, the memory array is arranged as two rows of eight 2i 18 devices. During each
read cycle, one byte is loaded from the memory into the
shift register and is serially clocked out as video. A single
RAS is common to the array and CAS is decoded to each
row. This configuration simultaneously refreshes one
row while reading data from the other row. A disadvantage of this arrangement is additional power supply and
decoupling requirements, since one row is always making a transition to active current (.:lIA) while the other
draws refresh cycle current (.:lIR)' Refer to Section 6.3.4
ondecoupling for calculations. The following is determined:

F = Frame rate of 60 Hz
R = Number of pixel clock times allowed for
horizontal retrace time = 160 (Usually
empirically determined., This nun\.ber establishes the width of the margins on the
left and right sides of the CRT display.)
Memory Cycle Rate = Byte read rate of the memory
=2.68 MHz
'
21.450 MHz
Meye (Hz) =
8
pixel rate
pixels/byte
I

Teye = 2.68 MHz =373 ns/cycle
The 2118-15 meets this Teye cycle time requirement.
Since the memory array is sequentially addressed, the
memory is automatically refreshed every 128 consecutive cycles.
Checking refresh timings: 128 cycles x 373 ns/cycle =
47.74 microseconds between total nifresh for each
device, ~asily within the 2 ms specification.

Pixel Clock (Hz)';' (N + R) * L *F = 21.450 MHz ,
where N = Number of displayed dots per line = 512
L = Number of horizontal lines per, frame
= 532 (512 visible lines + 20 line times allowed for vertical retrace)

rlOI-]

= 2.68 MHz

The worst case refresh occurs during vertical retrace
time when:
retrace time = 31.3 microseconds/line x 20 lines =
627 microseconds

TIMING
AND
VIDEO
CONTROL

VIDEO ADRS BUS

t- HZ BLANK
t- V BLANK

READY
CiV

,/
ADDRESS
MUX

;GRAPHICS
MEMORY
ARRAY

2 ROWS 2118
CPU
ADDRESS
BUS

Figure 27. Graphics Terminal Memory

worst case refresh rate = 627 microseconds + 47.7
microseconds = 674.7 microseconds, still well within
the 2 ms specification.

and data hold time of a flip-flop arbiter. This is a major
problem in purely asynchronous designs.

5.2 System Block Diagram

Writing is performed during horizontal or vertical retrace. More efficient designs would interleave memory,
eliminating the processor being in WAIT mode until the
memory is open. Here, and in some other limited applications, refresh can occur automatically by design,
and with no software or hardware overhead.

Figure 30 is a block diagram of the basic functions required for this system; refresh interval timer, refresh address counter, arbiter synchron.ization, address multiplexing and timing generation. Included also in the
diagram are the memory and CPU status decoders, data
latches and transceivers, bus control imd clock generation.

5 10 MHz NO·WAIT STATE SYSTEM

The functio,n of the refresh interval timer is to place requests for refresh cycles, distributed in approximately 15
microsecond intervals, so that each row of the memory
devices ,receives a refresh within 2 milliseconds. This
timer is comprised of two four-bit synchronous binary
counters and two flip-flops. The timer circuits divide the
10 MHz system clock by 150, then latches the count
carry bit to hold until recognized, through the arbiter,
by the refresh latch.

For fast high performance microprocessors such as the
10 MHz 8086, an LSI controller for dynamic RAM interfacing is unacceptable, due to the requirement for
WAIT states and resultant impact on performance.
Until faster LSI controllers appear, discrete controller
designs are required. In the example that follows, high
performance design techniques are coupled with Intel
high performance RAMs to yield a 10 MHi no-WAIT
state 808612164A system.
The key requirements are:
ALE to data in:
READY response:
2164A tRAe

The refresh address counter generates the refre,sh addresses that are submitted to the address multiplexer
during a refresh cycle. The counter is incremented once
at the end of each refresh cycle to update the refresh address; The outputs are wire-ORed to the microprocessor
address bus and are active only during a refresh cycle, at
which time the current count is presented to the address
multiplexer as the refresh address.

219 ns
89 ns
150 ns

The solution and implementation that follows, configures the 8086-1 in max-mode, incorporates a synchronous arbiter while providing a quasi-synchronous
refresh (refresh that is synchronous to the system clock,
but not to the microprocessor).

Timing generation for the memory array proQuces the
control signals for the address multiplexer and the gating
signals that provide for the properly timed arrival to the
memory of RAS, CAS, and addresses. In this design example, it is essentially a delay circuit with variable taps
to permit fine tuning of the memory inputs so as to allow
no-WAIT states by the microprocessor for a memory cycle. The strobe used to latch valid data from the memory
is also provided by the timing generator.

5.1 System Refresh
Rather than being constrained to the design configurations of purely 'synchronous or asynchronous refresh arbitration, a quasi-synchronous scheme was chosen taking advantage of the benefits of both, and avoiding
some of the drawbacks of implementing either one exclusively. Synchronizing the refresh arbitration to the
system clock ensures that its operations are inherently
and closely coupled to CPU operation and allowing
critical timing edges to always be predicted through
worst case analysis. However, unlike totally synchronous systems, if the CPU in this example were to
enter a HOLD, HALT, or otherwise stopped state,
refresh cycles would continue to keep valid data in the
memory, independent of the CPU operation. Also, synchronization of refresh requests to the system clock
make the task of the arbiter very easy. Memory cycle requests and refresh cycle requests never occur at the same
time (Figures 28 and 29, timing analysis). As a result,
there is no chance that a random cycle request can arrive
in a narrow time window that would violate data setup

The 2164A dynamic RAM requirement of multiplexed
row .and column addresses is met by the address
multiplexer. Here, the proper selection and transmission
of row/refresh or column addresses is accomplished by
control of the select line timing generation circuit.
In this design (Figure 31), arbitration is easily performed, Le., once a cycle type is latched into its respective flip-flop (refresh latch or memory access latch) its
'request is presented to the input of an AND gate that will
allow the request to pass through if a request of the other
type is not currently in execution. Once the request
passes the AND gate, the hardware is committed to a cycle of the requesting type and blocks any subsequent request until the current cycle is complete.
3-97

_.
~
T4

P1·8
8264A CLOCK

P23·3
SYSTEM CL.OCK 2

P3-26,27,28
B086 STATUS

P26·3
DECODED STATUS 1

P26·6
OECODED STATUS 2

P22·6
ACCESS PRESET 4

P26·8
ACCESS INITIATE

pH-a
- ACCESS REQUEST

P27·9
REFRESH REQUEST

REPRESENTS POSSIBLE REFRESH REOUEST TIME OUT

Pl·8
8284A CLOCK
P23·3
SYSTEM CLOCK 2

P3·2a, 27, 28
8086 STATUS

P26·3
DECODED STATUS 1
P26·8
DECODED STATUS 2

P22·6
ACCESS PRESET 4
P5·5
8288 ALE
P2s.a
ACCESS INITIATE

TIMER
Plg.s
CLOCK REFRESH

P2T·9
REFRESH REQUEST

Pl4-9
LATCHED REFRESH
P23-11
ACCESS BLOCK

REPRESENTS POSSIBLE REFRESH REQUeST TIME OUT

READ/WRITE FOLLOWED BY REFRESH

3
SIMPLIFIED INTERFACE LOGIC BLOCK DIAGRAM

~e".~ ••• ~· ~e •••; ••• ~·

N"''''''~~~~ ~

Figure 31, Logic Diagram -10 MHz System
3-101

N''''''''~~:!!_ ~

.inter

Ap·133

For example, suppose the CPU status decoder indicates
a memory cycle is pending and there is no refresh cycle in
progress. The status decoder outputs a bitindicatingthis
condition to the memory access latch and is latched on
the falling edge of ALE (address latch enable). After
propagating through the latch, this latched memory access bit is presented to the input of AND gate B (where it
will carry through the gate initiating a .memory cycle,
since there is no refresh cycle in progress) and its complement to AND gate A where it will block a refresh request
from propagating through until the memory cycle is
complete. As another example, assume that a refresh cycle is pending. The refresh timer times out, latches its
output signal into the refresh request latch which subsequently presents this latched refresh request to the input
of AND gate A. Here the signal is either held up or passed through depending upon the current CPU status.
Assuming that there is no memory cycle in progress or
that one has just ended, the AND gate passes the refresh
request through to the refresh cycle latch, committing
the. hardware to initiate a refresh cycle and blocking any
memory request that may occur until the end of the
refresh cycle.
The sole purpose of the CPU status decode block is to
inform the arbiter (as soon as possible) as to whether or
not the pending machine cycle is going to be a memory
cycle.
, The bus controller provides the memory write command
(MWTC) and is steered to a high andlor low byte write
by AO and BHE in the byte control block. Address latch
enable (ALE) used for latching valid addresses off the
multiplexed bus, data enable (DEN) used to enable the
data transceivers, and data transmit/receive (DT /R:)
used to control the direction of the data transceivers, are
all provid~d by the bus control block.
The refresh sync and ready sync blocks generate several
control signals for a number of functions that must exeecute to carry a refresh cycle to its natural end, all in
synchronization with the system clock. The first signals
generated are address disable - used to switch the CPU
address latches.into a high impedance state,and access
block - used to block a memory cycle request at AND
gate B. On the next rising clock edge a control signal is
output that will switch the refresh address counters onto
the address bus and enable a string of shift registers that
c()mprise the ready sync to start shifting the READY bit
through. Then, on the next rising edge of the clock, the
refresh cycle latch is cleared, and finally on the falling
edge of the clock the refresh signal is. output from the
ready sync block which is used by the RAS select block
to enable all the RAS lines ·at once, simultaneously performing refresh on all four memory rows.

5.3 Schematic
Refer to the logic scliematic (Figure 31) and to the block
diagram in Figure 30, during the following discussion involving the conversion of logic blocks to TTL logic.
The refresh interval timer is comprised of devices P2 and
P4, two 74LS163 four-bit synchronous binary courtters,
and one FIF from P14, a 74S74 flip-flop. Thecounters
are cascaded and free-running, being incremented by the
system clocks so as to output refresh request pulse
every 15 microseconds. This pulse is stored by P27 F IF,
the refresh request latch, which is part of the arbiter.

The refresh counter is a pair of AM25LS2569 three-state
binary upldown counters (located at PI7 and PI8) that
sequence from 0 to 28-1 (255) and then roll over to start
again. The MSB (most significant bit) of the counter is
unused. With the devices' clock inputtied to their OE,
the counters are automatically incremented at the end of
a refresh cycle when the outputs are switched off the address bus by OE going High. This sets up the count to the
next refresh address.
Memory address mUltiplexing is comprised of a pair of
74S158 quad 2:1 multiplexers (PI9, P20). Inverted data
output devices were selected because of their shorter
propagation delay. The arrival of addresses to the
memory is one of the tight timing constraints for zero
WAIT states. The select line is controlled by the timing
generator during a memory read or write cycle and is
used to switch from row to column addresses at the appropriate time. During a refresh cycle, the select line
does not change; thus, only the refresh addresses, which
are wire-ORed to the row addresses are presented to the
memory array.
The arbiter in this system is designed with two 74S74
FIFs, one from Pll and the other from P27, and two
gates: it 74SII AND gate at P25 and a 74S00 NAND gate
at P22. As previously discussed, the arbiter makes the
decision of whether to run a memory R/W cycle or a
refresh cycle, then commits the hardware to initiate the
cycle decided upon. Classically a difficult choice, the
task is greatly simplified by the quasi-synchronous
nature of this design. Memory and refresh cycle requests
never occur .at or near the same time and the worst case
data setup and hold times at each F IF are easily predicttable and are designed to avoid violations of these
specifications. The relatively simple nature of this arbitration circuit is demonstrated by. the small device
count and simplicity of the method involved.
The status decode block is implemented with two NAND
gates from 74S00 at P26 and one NAND gate from P22.
Low power Schottky devices were required because of
the limited (2 rnA) drive capability of the 8086 status
3-102

inter

Ap·133

lines. Through observation of the truth table for the status
bits SO-S2 on the schematic and the following logic, it is
apparent that NAND gate P26, pin 6 goes low during
memory read, memory write, or instruction fetch cycles.
This active low memory cycle status bit is latched into the
access latch on the trailing edge of the clocked ALE (from
S74 FIF at Pll) and informs the arbiter that this memory
cycle is in progress. For any other type of CPU cycle,
device P26, pin 6 is high, which enables NAND gate P22,
pin 5 to allow the next rising edge of the clock to preset
the memory access latch, indicating to the arbiter that this
is not a memory cycle.
The bus control block functions' are executed with an
Intel 8288 bus controller. In this circuit, ALE, DT IR,
DEN and MWTC are all generated at P5 from system
clock and CPU status bits inputs. The MWTC is used
for the write pulse to the memory array, being directed
to the higher or low byte by the pair of 74S32 gates at
P24 which comprised the uii: WE byte control block.
ALE is transmitted to Pillatch control (ENG) input of
the 74S373 three-state address latches P6-P8,thus latching valid addresses from the multiplexed CPU bus.
DT/R and DEN are wired to pins 1 and 19 respectively
of the pair of 8-bit 74LS245 data transceivers at P9 and
PlO, with DT/R controlling the direction of data flow
through the devices and DEN used to enable the device
output drivers in the direction selected by DT IR.
Timing generation for memory array related signals are
all derived from a STTLDM-595* active delay line at
P28. Activated only during a memory cycle via a single
input from the arbiter, this ol1e pulse is delayed 25 ns to
become the ACCESS ENABLE signal (the source of
RAS)" 50 ns to enable the flow through memory data
latches, 60 ns before switching the address multiplexer
and finally delayed 75 ns before becoming the source of
CAS.

speed microprocessor memory requirement, fulfilling
the needs at all performance levels. In particular, the
2164A DRAMs used in this 10 MHz design easily conform to the rigid requirements of this high performance
system.

6 HIGH PERFORMANCE SYSTEM
DESIGN CONSIDERATIONS
Designing a high performance, high speed memory
system requires consideration of the following areas:
1.
2.
3.
4.

6.1 Skew
Skew is the difference between maximum and minimun
propagation delay through devices in a parallel path.
For example, refer to Figure 32. Here signal A and signal
B propagate through the same number and types of
gates, each transversing a parallel path. For both signals
the total mimimum delay is 6 ns and the total maximum
delay is 16 ns. However, diagramming the worst case
(Figure 33), the skew between these signals can be as
much as 10 ns. This time (s!
1.0

• t prop MAX = Data Book maximum
• tprop Typical = Data Book typical
• t prop MIN = \12 Data Book typical

0.0
10

Figure 34. Schottky TTL Capacitive
Loading Effects
The goal to miniqtize skew is achieved by observing the
following guidelines:
• Seiect logic gates for minimum delay per ,function
• Place parallel paths in the same package (Device to
device skew within the sallie package = .5 ns max
for STTL,'2.0 ns max for high current drivers, i.e.,
74S240.)
• Balan,ce the output loading to equalize the
capacitive delays
• Use de.ay lines with tight t prop' and tri,e tolerances
(± 1 ns)

.. Capacitive loads add to the propagation delays specified
in the data books. The additional delay can be calculated
in the following manner: .
• Additional Delay = Dc X (Cload ,- C spec), where
Cload = sum of all input capacitance plus PCB
traces ("" 2 pF/in),
specified capacitance of the driver, and
C spec
the derating factor for the driver logic
Dc
family
.
3·104

Schottky. TTL = 0.5 ns/pF
Low power Schottky TTL
= .1 ns/pF
High current Schottky TTL
= .25ns/pF
TTL = .75 ns/pF

Ap·133

RIGHT
ADDRESS
DRIVERS

I
CARD EDGE CONNECTOR

Figure 35. Memory Board Layout

6.3

Cir~uit Design Techniques

Optimum circuit design demands attention to the
physical details of a 2164A memory system. A properly
produced layout will minimize board area while yielding
wider operating margins on timing and power supply requirem!'!nts. The key areas of consideration are:
I. Ground and power gridding
2. Memory array I control line trace routing
3. Control logic centralization
4. Power supply decoupling

Figure 36. Equivalent Circuit for Distribution

6.3.1 GROUND AND POWER GRIDDING

The power and ground network do not appear as a pure
low resistance element, but rather as a transmission line
because the current transients created by the RAMs are
high frequency in nature. The RAMs are the lumped
equivalent circuits of the power and ground transmission lines are shown in Figure 36.
The characteristic impedance of a transmission line is
shown in Figure 37A. By connecting two transmission
lines in parallel, the characteristic impedence is halved.
The result is shown in Figure 37B.

(A)

~Lo

3-105

= INDUCTANCE/UNIT LENGTH

= CAPACITANCE/UNIT LENGTH

~
!B)~
Lo

Transient effects can be minimized by adding extra circuit board traces in parallel to reduce interconnection inductance.

Zo -

Figure 37. Transmission Line Characteristic
Impedance

Ap·133

Extrapolation of this concept to its limit will result in an
infinite number of parallel traces, or an extremely wide
low impedance trace, called a plane. Distribution of
power and ground voltages by plane provides the best
distribution, however correct gridding can effectively
approximate the benefits of planar distribution by surrounding each device with a ring of power and ground
(Figure 38).

2164A

\ I

2164A

6.3.2 MEMORY ARRAY/CONTROL
LINE ROUTING

Address lines need to be kept as short and direct as possible. The lone serpentine line depicted in Figure 40 should
be avoided, since the devices farthest away from the
driver will receive a valid address at a later time than the
closer ones. A better way to route address lines is in a
.comb like fashion from a central location as depicted in
Figure 41. Routing control and address signals together
from a centralized board area will also minimize skew.

\
ADDRESS LINE LAYOUT
8 DEVICES

VERTICAL· TRACES ON COMPONENT sIDe
HORIZONTAL TRACES ON SOLDER SIDE

TOTAL LENGTH OF LINE - 20'

MAINQROUND BUS OR INTERCONNECTION TO TTL
CONTROl. ADDRESS, DATA BUFFERS

•

. Figure 40. Unacceptable Address Line
Routing (Serpentine)

Figure 38. Recommended Power Distribution
- Gridding

Improper ground and power gridding can contribute to
excess noise and voltage drops if not prQperly structured. An example of an unacceptable method is
presented in Figure 39. This type of layout promotes accumulated transient noise· and voltage drops' for the
device located at the end of each trace (path).

\ I

)

Figure 41. Recommended Address Line Routing

\ I

Allow for proper termination of all address and control
lines, since a P .C.B~ trace becomes a transmission line
when:

I
\

ADDRESS LINE LAYOUT
8 DEVICES

2164A

I
VDol -+ 5V)

2164A

2tpd "" tr or tf
where: tp = propagation delay down the line
tr = rise time
tf = fall time

VSS(GND)

Figure 39. Unacceptable Power Distribution
3-106

Ap·133

The maximum unloaded line lengths not displaying
transmission line characteristics are listed in Table 11.
The values assume propagation delay of a = 1.7 ns/ft.
Table 11. Transmission Characteristics
Logie
Family

Rise
Time

Fall
Time

54174L
54174
54H174H
54LS174LS
54S174S
IOKECL
lOOKECL

14 - 18 ns
6- 9 ns
4- 6 ns
4- 6 ns
1.8 - 2.8 ns
1.5 - 2.2 ns
0.5 - 1.1 ns

44221.6 1.5 0.5 -

6 ns
6 ns
3 ns
3 ns
2.6 ns
2.3 ns
1.1 ns

Max.
Length
14.1 inches
14.1 inches
7.0 inches
7.0 inches
5.6 inches
5.3 inches
1.8 inches

The maximum length of a loaded transmission line is:

where CD = Capacitive load/unit length
and Co = Capacitance/uI)it length

6.3.3 CONTROL LOGIC CENTRALIZATION
Memory control logic should be strategically located in a
centralized board position to reduce trace lengths to the
memory array (Figure 35).
Long· trace lines are prone to ringing and capacitive
coupling, which can cause false triggering of timing circuits. Short lines minimize this condition and also result
in less system.~kew.
A practical memory array layout is presented in Figure
42. Typically, this pattern and its "mirror image" 'are
placed on each side of the memory control logic for a
practical memory board design.

6.3.4 POWER SUPPLY DECOUPLING
For best results with the 2164A, decoupling capacitors
, are placed on the rnemory array board at every device
location (Figure 42). High frequency 0.1 p.F ceramic
capacitors are the recommended type. In this arrangement each memory is effectively decoupled and the noise
is minimized because of the low impedence across the

DECOUPLING

CAPACITOR

DOUT= •

NOTE 1: FUTURE ADDRESS EXPANSION

NOTE: MEMORY DEVICE SPACING IS 0.425"
TRACES ARe !iO MIL

Figure 42. 2164A Memory Array P.C. Board Layout
3-107

inter

Ap·133

circuit board traces. Typical VDD noise levels for this array are less than 300 mY.
A large tantalum capacitor (typically one 100 ",F per 32
devices) is required for the 2164A at the circuit board
edge connector power input pins to recharge the 0.1 ",F
capacitors between memory cycles..
'
Decoupling is of considerable importance in circuit
design in order to minimize transient effects on the
power supply system. In order to determine the values
for proper decoupling capacitors, the required amount
of charge storage for a capacitor must first be determined in the following manner:

Q = .dI.dT
where: Q = charge in coulombs

Bulk decoupling requirements are determined in a similar way:
Assuming the following:
50 ",sec power supply response time
15.6 ",sec refresh rate
Th~ee refresh cycles/50 ",sec period
IDD standby = 5.77 rnA
I
DD

STDBY = 45 rnA (.3 ",sec) + 5 rnA (15.3 ,.sec)
15.6 ",sec

=5.77 rnA
An example calculation with Y4 devices active proceeds
as shown:
Q = [50- (3) (.3») ",sec x 49.23 rnA (Y4) =604 nC

~: ~~ =6.0 ",F device

if V = 100 mV then C =

.dI = change in current is amperes
.dT = change in time is seconds

if V =500 mV then C= : : ~~ = 1.2 ",F device

and: .d V = Q/C
where: .d V = voltage change in volts
and C = capacitance in farads

The data shown'in Table 12 defines the decoupling requirements of2164A-15 and 2118-15 dynamic RAMs for
a 300 ns cycle time over ~arious device selections for a
given percentage.

Assumingthe following system parameters:
5 rnA to 55 rnA current switch for regular cycle
5 rnA to 45 rnA current switch for refresh cycle
1 microsecond bulk decoupling response time
260 ns cycle time
1/4 of devices selected (one of four rows)

Cycle time has a downward scalirig effect on the average
operating current according to the following equation:

An example calculation proceeds as follows:

Q = (45-5 rnA) (.3 ",sec) + Y4 (55-5) rnA (.7 ",sec)
Q = 20.75'nanocoulombs

IDDAVE = [IDD2 x

CR~~~~:~:;ing») ]

tRC (spec)
) ]
+ [IDDI X 1 - ( tRC (operating)

if VDD is restricted to 100 mV (21170) then
nC
I'
C = 20.8
100 mV = .21 ",F DeVice

At minimum cycle time,
if VDD is allowed to 500 mV (10%) then
20.8 nC
.
C= 500mV =.042",F/Devlce

tRC (spec)
tRC (operating)

so that worst case IDDAvE = IDD2, but as the cycle time
increases, IDDAvE approaches the standby current,
Table 12. Decoupling Chart

\ 0.1 ,I'fd/device will work if V.
, devices are active at one time.
+ 100 I'fd every 32 devices.

, 0.1 I'F12 devices + 27 I'F every
~2 devices (assuming V. of devices active)

infel'

Ap·133

becoming 6.3 rnA @ 10,000 ns cycle time. Figure 5 in the
2164A data sheet depicts this scaling effect. Be sure to
use the correct IDD value based on specific worst case
cycle time when computing specific decoupling requirements.

6.4 Timing Analysis the Worst Case

Determining

Once the control logic is designed, worst case system
delays must be determined to guarantee proper circuit
operation. There are two ways to perform these calculations:
I. A statistical worst case analysis (or the Monte Carlo

method) which assumes that all devices probably
won't be in their worst case condition at the same
time.
It is determined by the following formula:
STATISTICAL WORST CASE

= Vr.(A)2

+ (B)2 + (C)2 MAX STTL DELAYS
.+ TYPICAL STTL DELAYS

+ Jr. (A)2 + (B)2 + (C)2 SKEW DELAYS
+r. DELAYS DUE TO CAPACITIVE LOADING

+MAXIMUM DELAY ACCESSING MEMORY
DEVICE
WHERE (A), (B) OR (C) = MAX-TYP OR TYP-MIN

In summary, the following rules and guidelines apply to
worst case analysis:
I. All propagation' delays are from the industry TTL
books.
Max = Data book maximum
Typ = Data book typical
Min = Y, Data Book Typical
2. Skew device to device in same package = 0.5 ns Max
for Schottky TTL and 2 ns for 74S240.
3. STTLDM-595.is a special delay line with active outputs. Propagation delay = ± 1 ns per tap (i.e., 75 ±
1 ns). (10 MHz system.)
4. Capacitive loads add 0.5 ns/pF to propagation delays specified in device spec (Le., 74S04 is specified at
5.0 ns Max @ 15 pF. At 25 Pf propagation delay is
5.5 ns) Schottky TTL input capacitance is 3 pF. PCB
traces are 2 pF/inch.
5. PCB etch delay adds little or no skew to array address/ control timing signals. It adds 4 ns, however,
in the overall access time data path.
6. Timing components are immediately adjacent to
each other, making PCB etch delays in delay timing
chain negligible (exception is timing tap used to terminate delay line latch).

7. SUMMARY'
2. A true worst case analysis, using specified maximum
and minimum delays for peripheral circuits plus all
delays due to capacitive loading from device inputs
and distributive capacitance in PC board etched con
ductors. The following formula appears here:

The Intel 2164A and 2118 DRAMs meet all microprqcessor system requirements, offering high density,
speed, low power and ease of use. Follow th~ syste~
design guidelines presented to create a harmomous mIcroprocessor memory design.

WORST CASE
= r. MAXSTTL DELAYS + SKEW DELAYS

(PERIPHERAL DEVICES)

8. REFERENCES

+ r. DELAYS DUE TO CAPACITIVE LOADING
(INPUTS + P.C.B. TRACES)

AP-75

Application of the Intel 2118 16K Dynamic
RAM
AP-13 1 2164A 64K Dynamic RAM Device Description
AP-92A Interfacing Dynamic RAMs to iAPX 86/88
Systems Using the Intel 8202A and 8203
AP-46
Error Detecting and Correcting Codes Part #1
AP-73
ECC #2 Memory System Reliability with Error
Correction

+ MAXIMUM DELAY ACCESSING MEMORY
DEVICE (T RAC OR T cAd

Since the statistical approach can be justified only in
large systems with hundreds or thousands of components, the timing calculations used in all of the
previous examples are' based on a true worst case
analysis. Capacitive delay is formulated from the equations in Section 6.1.2 ..

INTRODUCfION
Complex electronic systems require the utmost in reliability. Especially when the storage and retrieval of
critical data demands faultless operation, the system
designer must strive for the highest reliability possible.
Extra effort must be expended to achieve this high
reliability. FortUliately, not all systems must operate with
these ultra reliability requirements.

1.000.000
100 YRS
0,01%11000
HR ,
100.000
10YRS

The majority of systems operate in an area where system
failure ranges from irritating, such as a video game
failure, to a financial loss, such as a misprinted check.
While these failures are not hazardous, reliability is
important enough to be designed into the system.

A memory system is one of the system components for
which reliability is important. Also, it is one of the few
system components which can be altered to greatly
enhance its reliability. The purpose of this report is to
examine different methods of error encoding, especially
Error Correction Codes (ECq, to increase the reliability
of the memory system.

...
:::E

1 WK
100

10.000Ioa...--....L.-I/'----..-I<'-----...J
1010
NUMBER OF DEVICES

SYSTEM RELIABILITY
Individual device reliability is the foundation of memory
system reliability. Reliability is expressed as mean time
between failures. The mean time between failures
(MTBF) of a system is a function of the number of
devices and the device failure rate. Failure rate of the
memory device can be obtained from the reliability
'report on the specific device. MTBF of the device is:

[II
where To = MTBF of the device
). =

and MTBF of the system is approximately:
To

1. System Reliability vs Number of Devices

and dividing by the size of the RAM. To illustrate,
assume a 1 megaword memory system with,a word width
of32 bits, implementedwith Intel@ 2104A4Kxl RAMs.
The number of required devices is:
, D - 1,048,576 x 32 _ 8 192 d .
'4,096
-,
eVlces
Prediction of failure for this system, shown in Figure I, is
667 hours or 28 days - assuming continuous use and
worst case temperature.

device failure rate (070/1000 hrs)

Flg~re

[21

where Ts = MTBF of the system
D = number of devices in the system
As the number of devices required to construct a system
becomes larger, the system MTBF becomes smaller,
A plot of system MTBF as a function of the number of
memory devices is Shown in Figure 1 for different failure
rates, Included for reference are the failure rates of the
Inte\@ 2104A 4Kxl RAM and the Intel@ 211716Kxl
RAM. Using RAMs which are organized one bit wide,
the amount of devices required for a system is calculated
by multiplying the number of words by the 'word length
3·111

Equation 2 showed that system MTBF is increased when
fewer devices are used. A one megaword memory having
32 bit wide words can be constructed with Intel 2117 16K
RAMs. In this case one fourth as many devices are
required - 2048 devices. From Equation 2, the expected
MTBF should be four times as large - 2668 hours. It is
not. The failure rate from Figure 1 for this system is 2000
hours. Different device failure rates account for this
difference. The failure rate of the 16K is not yet equal to
that of the 4K. Memory device reliability is a function of
time as shown in Figure 2. Reliability improvement often
is a result of increased experience in manufacturing and
testing. In time, the failure rate of the 16K will reach that
of the 4K and one fourth as many devices will result in a
system MTBF approximately four times better.

One measure of a code is its efficiency. Efficiency is the
ratio of the number of bits in the encoded word to the
number of bits of data:

0.07
=~ 0.06
i1:§ 0.05

----=== -1.0 L----'L---'----'--'-_-L_...L_-L-_-'-_L---.JL----'
~

YEAR

Figure 2. Device Failure Rate as a Function of Time.

As an example, consider a two bit word. It can assume 22
or 4 states, which are:

The failure rate of a system without error correction will
follow a similar curve over time. Indeed, in very large
systems built with large numbers of devices, the system
failure rate may be intolerable, even with very reasonable
device f;tilure rates. To increase the system reliability
beyond the device reliability, redundancy coding techniques have been developed for detecting and correcting
errors.

State
State
State
State

1111· .. ·11111····11

By adding one K bit to the two bit word error detectior
becomes possible. The value of the K bit will be such that
the encoded word has an odd number of ONES. As ~ill
be explained later, this technique is "odd" parity.
The sum of the ONES in a word is the weight of the
word. Parity operates by differentiating between odd and
even weights. The encoded word will always have a~ odd
weight as a result of having an odd number of ONES.

Mathematically, N is related to M and K by:

The mechanics of the encoding bits create encoded words
such that .every valid encoded word has a set of error
words which differ from all valid encoded words. When
an error dccurs, an error word is formed and this word is
recognized as contain'ing invalid data.

'----- K-----'

Figure 3. Encoded Word Form

where N

00
01
10
II

All possible states have been used as data; consequently
any error will cause the error state to be identical to a
valid data state.

Redundancy codes add bits to the data word to provide a
validity check on the entire. w.ord. These additional bits,
used to detect whether or not an error has occurred, are
called encoding bits. With M .data bits and K encoding
bits, the encoded word width is N bits. Shown in Figure 3
is the form of the encoded word.

L--M - - '

1
2
3
4

Figure 4. All State. of • Two-Bit Word

REDUNDANCY CODES

r-----~,N

All of the data are contained in the M bits. The K bits
contain no data, only validity checks. To maximize the
amount of data in the encoded word, the number of K
bits must be minimized. Examination of Equation 4
shows that the minimum value of K is zero. With K equal
to zero, the efficiency is unity. Efficiency is maximized,
but the word has no encoding bits. Theref~re, it has no
capability to\detect an error.

M+K

(3)

If a single bit error occurs, one bit in the encoded word
will change state and the word will have an even weight.
Then in this example, all encoded states with an even
weight - an even number of ones - lare error states.

number of bits in the encoded word

number of data bits

number of encoding bits

Exactly how K is related to M, and the number of
required -K bits depends on several factors which will be
described later.

The value of the encoding bit or parity bit is found by
counting the number of ones - calculating the weight and setting the value of K to make the weight of the
encoded word odd. Referring to Figure 4, State I was 00,

3-112

the weight of this word is 0, so K is set to 1 and the weight
of the encoded word is odd. State 2 is 01, the weight is
odd already, so K is set to O. The weight of State 3 is
identical to that of State 2 so K is again set to O. Finally,
State 4 has an even weight (1 + 1 = 2), thus K is 1. The
encoded states of the two bit data word are listed in
Figure 5.
Encoding' Bit

Dala

State
Stale
Stale
State

Figure 5. Code BIIs for All Possible States of a Two-Bit Word

To illustrate the error detection, Figure 6a lists all states
of the encoded data word and all possible single bit
errors. Because the encoded word is 3 bits long, there are
only 3 possible single bit errors for each encoded state.

MK
These two states have two bit positions which differ. This
difference is defined as distance and these two states have
a distance of two. Distance, then, is the number of bits
that differ between two words. The encoded words have
a minimum distance of two. Longer encoded words may
have distances greater than two but never less than two if
error detection is desired. The error states have a
minimum distance of one from their valid encoded state.
A minimum distance of two between encoded states is
required for error detection. A re-examination of a word
with no' encoding bits shows that the states have a
minimum distance of 1 (see Figure 8). No error detection
is possible because any single bit error will result in a
valid word.
State I

State 2

01::1}
10:1
Distance of I

PARITY

, Notice that every error state has an even weight, while the
valid encoded states have odd weights.
Converting all the values of these states to decimal
equivalents makes the errors more obvious as shown in
Figure 6b.

Error States

3
5

11::1

Figure 8. Minimum Distance of a Two·Blt Word

Figure 6a. All Possible Slngle·BIt Errors

(0)

Valid States

l!J I l!J

Figure 7. Bit Dlrterence.

Figure 6b. Decimal Representation of Errors

No error state is the same as any valid encoded state.
Identical error states can be found in several columns.
The fact, that some error states are identical prevents
identification of the bit in error, and hence correction is
impossible. Importantly though,error detection has
occurred.
Figure 6a demonstrates another property of codes. Every
error state differs from its valid encoded state by one bit,
whereas each of the encoded states differs from the
others by two bits. Examine the encoded states labeled B
and D in Figure 6a and shown in Figure 7.

A minimum distance of two code is implemented with
Parity. Refer to previous section for an explanation.
Parity is generated by exclusive-ORing all thc data bits in
the word, which results in a parity bit. This parity bit is
the K encoding bit of the word. If the word contains M
data bits, the parity bit is:
bl

(jJ

(jJ ••• (jJ

parity bit
value in the bit position

The parity bit combines with the original data bits to
form the encoded word as shown in Figure 9. Encoded
words always have either "odd" parity, which is an odd
number of Is ~an odd weight) or "even" parity which is
an even number of Is (an even weight). Odd and even
parity are never intermixed, so that the encoded words all
have either odd or even parity - never both.
When the encoded word is fetched, the parity bit is
removed from the word and saved. A new parity bit is
generated from the M bits. Comparing this new parity bit
with the stored parity bit determines if a, single bit error
has occurred.

3-113

Figure 9. Encoded Word Form

Consider the two bit data word whose value is "01."
Exclusive-NORing the two data bits generates a parity bit .
which causes the encoded word to have odd parity:
C~OElli

C=O

ERROR CORRECTION

The encoded word becomes:
M

Classical texts on error coding contain proofs showing
that a minimum distance of three between encoded words
is necessary to correct errors. While this fact does not
describe the code, it does give an indication of the form
of the code.

parity
LSB of data

Assume that an error occurs and the value of the word
becomes "110." Stripping off the parity bit and
generating a new parity bit:
transmitted parity = 0
transmitt~d

word

new parity of transmitted word

In summary, single bit parity will detect the majority of
errors, but cannot be used to correct errors. Using parity
introduces a measure of confidence in the system. Should
a single bit error occur, it will be detected.

= T$1 =
,

Correcting errors is not as difficult as it first appears. As
a result of a paper published by R. W. Hamming on error
correction the most widely used type of code is the
"Hamming" code. Using the same technique as parity,
Hamming code generates K encoding bits and appends
them to the M data bits. As shown in Figure II, this N bit
word is stored in memory.

111········111 DIJ

generated parity"* transmitted parity
Note that the error could have occurred in the parity bit
and the final result would have been the same. An error
in the encoding bit as well as in the data. bits can be"
detected.
Although parity detects the error, no correction is
possible. This is because each valid word can generate the
same error state. Illustration of this is shown in Figure
10.
eorred Word

Possible
Single Bit
Error

to.

Possible Errors "

L---------N-"--------~

Figure

Using the encoded word "010" one possible double bit
error (DBE) is:
I I
~parity

Checking parity:

Encoded Word Form

Thus far the mechanism is similar to parity. The only
difference is the number of K bits and how they relate to
the M data bits.
When the word is read from memory, a new set of code
bits (K ')" is generated from the M' data bits and
compared to the fetched K encoding bits. Comparison is
done by exclusive-ORing as shown in Figure 12. Like
parity the result of the comparison - called the
syndrome word - contains information to determine if
an error has occurred. Unlike parity, the syndrome word
also contains information to indicate which bit is in error.

Each of the errors is identical to the others and
reconstrudion of the original word is impossible.
Parity fails to detect an even number of errors occurring
in the word. If a double bit error occurs, no error is
detected because two bits have changed state, causing the
weight of the word to remain the same.

Figure 12. Syndrome Generation

The syndrome word is therefore K bits wide. The
syndrome word has a range of 2K values between 0 and
2K - 1. One of these values, usually zero, is used to
indicate that no error was detected, leaving 2K - I values
to indicate which of the N bits was in error. Each of
these 2K - 1 values can"be used to uniquely describe.a bit
in error. The range of K must be equal to or greater than
N. Mathematically, the formula is:
2K-I ~ N

The transmitted parity and the regenerated parity agree.
Therefore the technique of parity can detect only an odd
number of errors.

3·114

but N = M+K
and 2K - 1 ~ M + K

(5)

Equation 5 gives the number of K bits needed to correct a
single bit error in a word containing M data bits. Ranges
of M for various values of K are calculated and listed in
Table I.
Single Correct!
Single Detect

Single Correct/
Double Detect

CODE DEVELOPMENT
Contained in the syndrome word is sufficient information to specify which bit is in error. After decoding this
information, error correction is accomplished by
inverting 'the bit in error. All bits, including the encoding
bits - called check bits - , are identified by their
positions in the word.

Table I.
Range of M for Single Correct/Single Detect or Double Detect Codes
for Values of K

To detect and correct a single bit error in a 16 bit data
word, five encoding bits must be used. As a result, the
total number of bits in the encoded word is 21 bits.
Efficiencies of single detect - parity - and single
,detect/single correct codes as a function of the number of
data bits are shown in Figure 13. For large values of M,
'the efficiency of single detect/correct is approximately
equal to that of the single detect code - parity.

Figure 14. Positional Representation of Bits In the Word

Bits in the N bit word are organized as shown in Figure
14. Bit numbers shown in decimal form are converted to
binary numbers. From equation 5, this binary number
will be K bits wide. In Figure 15 is an example using a 16
bit data word. Because there are 16 data bits, M equals
16, K equals 5 and N equals 21. Shown in Figure 15 the
word'is binary equivalent of the position. Notice that
where the M and the K bits are located is not yet
specified.
_OO'lOOr---\OV'\~MN_O

NN----------~_~~~.~N_

Bit

~~~~~~~~~~~~~~~~~~~~~

Position

Value

101010101010101010101
00 II 00 II 00 II 00 II 00 II 0
110000111100001111000
000000
II I II I 10000000
I I I I I I 0 0 0 0 0 0 0 0 0 0 0 0 00 0

2°
2'
22
2'
2'

LSB

MSB

Figure IS. Binary Value of Bit Position.
E=M~K

The syndrome word is the difference between the fetched
check bits and the regenerated check bits. Identification
of the bit in error by the syndrome word is provided by
the binary value of the bit position. The, syndrome word
is generated by exclusive-ORing the fetched check bits
with the regenerated check bits. Any new check bits that
differ from the old check bits will sell s in-the'syndrome
word. To identify bit 3 as a bit in error, the syndrome
word will be 00011, which is the binary value of the bit
position. Weight is determined only by the I s in Ihe bit
position chart in Figure 15, so they are replaced wilh an
X and theOs are deleled. The resuh is shown in Figure 16.

SINGLE CORRECT
DOUBLE DETECT

-OO'lOOt-\CIV'I'o:t""N
..... _
O O'IOOt-\OV'I'o:tI"')N_
NN _ _ _ _ _ _ _ _ _

~~~~~~~~~~~~~~~~~~~~~

X X X X 'x xx x
cr
xx xx xx xx
a
C4
xxxx
xxxx
C8
xxxxxxxx
CI6

Figure 16. Relationship of Data Bits and Check Bits.

Figure 13. Code Efficiency vs Data Word Size

3-115

The simplest mechanism to calculate the check bits is
shown in Figure lB. The data word is aligned on the
chart. Because weight and hence parity are affected only
by "Is," only 'columns containing" Is" are circled for
identification. The check bits are the result of odd parity
generated on the rows. For example, the Cl row has three
"Xs" circled; therefore CI is 0 to keep the row parity
odd. In this example, all other rows contain an even
number of circled "Xs;" therefore the remaining check
bits are" I s," These check bits' are incorporated into the
data word, forming the encoded word. Performing this
function, the 21 bit encoded word is:

Check bit function is now defined by equating the check
bits to the powers of 2 in the binary positions. Each check
bit will operate on every bit position that has an X in the
row shown in Figure 16. Five bit positions - 1,2,4, B,
and 16 - have only one X in their columns. The corres,ponding check bits are in these respective locations.
Check bit CI is stored in Bit Position I, C2 is stored in
Bit Position 2, and C4, CB, and CI6 are stored in
positions 4, B, and 16 respectively. Because each of these
positions has one X in the column, the check bits are
independent of one another. If a check bit fails, the
syndrome word will contain a single "1." A data bit
failure will be identified by two or more "Is" in the
syndrome word.

CI6
0101 0

The data bits are filled in the positions between the check
bits. The least significant bit (LSB) of data is located in
position 3.

CB
000 0011

CI6
0101 0

000 0011 I

When the new check bits are exclusive-ORed with the old
check bits, the syndrome wor.d is formed:
CI6 CB C4 C2 CI

O· 0

CI = MleM2eM4eMSeM7eMgeMIleMI2eMI4eMI6

The result is 00111, indicating that bit position 7 - data
bit 3 - is in error. Bit position of the error is indicated
directly by the syndrome word.

CS = MSeM6eM7 .. MS .. MgeMlOeMII

= MI2 .. MI3eMI4eMISeMI6

How the Hamming code corrects an error is best shown
with an example. In this example, a data word will be
assumed, check bits will be generated, an error will be
forced, new check bits will be generated, and, the
syndrome word will be formed. Assuming the l6-bit data
word

While this "straight" Hamming code is simple, implementing it in hardware does present some problems.
First, the number of bits exclusive-ORed to generate
parity is not equal for all chec.k bits. In the preceding
example, the number of bits to be checked ranges from
10 to 5. The propagation delay of a 10 input exclusiveOR is much longer than that of a 5 input exclusive-OR.
The system must wait for the longest propagation delay
path, which slows the system. Equalizing the number of
bits checked will optimize the speed of the encoders.

0101 0000 001I 1001
Check bits are generated by overlaying the data word on.
the Hamming Chart of Figure 16 and performing an odd
parity calculation on the bits matching the "Xs,"

CI6
21

Old check bits

o 0

= M2 .. M3eM4 .. MS .. MgeMIO .. MII .. MI6eMI6

I New check bits

C2 = MleM3eM4eM6eM7eMlOeMII .. MI3 .. MI4

C2 CI

000

CI6 CB C4 C2CI

Parity check on the specified bits is used to generate the
. check bits. Each check bit is the result of exclusive-ORing
the data bits marked with an "X" in Figure lB. Check
bits are generated by these logic equations:

CI6

data bit 4:

A new set of check bits is generated on the error word as
shown in Figure IB and is:

When the check bits are generated for storage, bits I, 2,
4, 8, and 16 are omitted from the generation circuitry
because they do not yet exist, being the result of
generation.

Forcing an error with bit position 7 -

Data Bit 2 is stored in position 5 - position 4 is a check
bit. Figure 17 shows the positions of data bits and check
bits for sixteen bits of data.

Figure 17. Dala and Check Bit Posillons in Ihe Encoded Word.

Figure 18a. Hamming Chart.

Bi, Position 21
Da'a Bi' 16

:~IQ~~I:OQ ~ ~ : :~ ~ ~:: ~

CI '0
C2 I
C4 I
C8 I
CI6 I

CI I
C2 0
C4 0
C8 I
C16 I

Figure 18b. Check Bit Generation.

Secondly, two bits in error can cause a correct bit to be
indicated as being in error. For example, if check bits CI
and C2 failed, data bit I would be flagged as a bit in
error.

detectable as a double bit error by performing a parity
: check on the syndrome word. If two data bits fail, again
the syndrome word has an even weight - a detectable
error.

Because of these two difficulties, the Error Correction
Code (ECC) most commonly used is a "modified"
Hamming code is most widely used which will detect
double bit errors and correct single bit errors.
SINGLE BIT CORRECT /
DOUBLE BIT DETECT CODES

Adding one additional check bit to the correction check
bits provides the capability to detect double bit errors.
The number of encoding or check bits required to detect'
double bit errors and correct single bit errors is:

Substituting M + K for N:

Modern algebra can be used to prove that a minimum
distance of four is required between encoded words to
detect two errors or correct a single bit error. An excellent
text on this subject is Error Correcting Codes by Peterson
and Weldon.
One possible double bit error is two check bits. Using
straight Hamming code, the circuit would "correct" the
wrong bit. Double error detection techniques - modified
Hamming codes - prevent this by separating the
encoded words by a minimum distance of four. As a
result each data bit is protected by a minimum of three
check bits, so that the syndrome word always has an odd
weight. Therefore, even weight syndrome words cannot
be used. When two check bits fail, the syndrome word
has two "I s" or an even weight. Even weight is
3-117

2K-1

M+K

[6]

Equation 6 is similar to equation 5, which describes single
bit correct and detect except for the left side of the
inequality, which shows one additional encoding bit is
required. For single bit detect and correct the left side of
the inequality was 2K. Table I also list.s the ranges of M
for valui!s-of K, for a direct comparison to single bit
detect and single bit correct codes.
Figure 13 includes the efficiency curve for single bit
correct/ double bit detect (SBC/DBD) codes for values of
M., As would be expected, because of. the additional
encoding bit the efficiency is slightly lower. For large
values of M, the efficiency of this code approaches' unity'
like the two other curves.

Syndrome words for the SBC/DBD code are developed
like the straight Hamming code, except that syndrome
words do not map directly to bit positions. The syndrome
word has an odd weight and does not increment like
straight Hamming code. In addition, implementation
considerations can impose constraints. For example, the
74S280 parity generator is a nine input device. If a check
bit is generated from ten bits, extra hardware is required.
Empirical methods can be used to form the syndrome
words. All possible states of the encoding bits are listed
and those with an even weight are stricken from the list.
Again like Hamming code, states which have a weight of
one are used for syndrome words for check bits. For a
sixteen bit data word, six check bits are required. Figure
19 lists the possible states of syndrome words for a 16 bit
, data word.

Figure 19. Possible Syndrome Words

In Figure 19 only twenty syndrome words for data bits
are listed, because the possible words with a weight of 5
were eliminated so that every data bit would have' only
three bits protecting it. This simplifies the hardware
implementation. If there are more than 20 data bits,
states with a weight of 5 must be used. All states listed in
Figure 19 are valid syndrome words, so thatthe problem
becomes one of selecting the optimum set of syndrome
,words. ,To minimize circuit propagation delay the
. number of data bits checked by each encoding bit should
be as close as possible to all the others.
J

The syndrome words can be mapped to any bit position,
providing that identical, code generations are' done at
storage and retrieval times. Syndrome word mapping
may be arranged to solve system design problems. For
example, in byte oriented systems the lower order
syndrome bits are identical, so that the circuit design may
be simplified by using these syndromes to determine
which bit is in error, and the higher order syndromes to
determine which byte is in error. Double bit detect/single
bit correct code is implemented in hardware as a straight
Hamming code would be.
DESIGN EXAMPLE

To illustrate code development, the design example uses
single bit correct/double bit detect code on a 16 bit data
word. In addition to the memory, the ECC system has
five components: write check bit generator, read check
bit generator, syndrome generator, syndrome'decoder,
and bit correction. Connected together as shown in
Figure 20, these components comprise the basic system.
Features can be added to the system to enhance its
performance. Some systems include error logs as a
feature. Because the address of the error and the errors
are known, the address and the syndrome word are saved
in a non-volatile memory. At maintenance time this error
log is read and the indicated defective devices are
replaced. Being a basic design, this example does not
include an error log.
Write check bits are generated when data are written into,
the m~mory, while read check bits are generated when
data are read from the memory. Off-tile-shelf TTL is
used to implement the design'. Check bits are generated
by performing parity on a set of data bits, so that this
function is performed by 74S280 9'bit parity generators.
One parity generator for each check bit is required.
Because the read and write check bit generations are the
same, the circuits are sim.ilar. One minor difference
should be noted. In this example, the check bit will be
formed from parity on eight data bits. The 74S280 parity
generator has nine inputs; therefore, the write check bit
generator will have the extra input grounded while the
read generator has as an input the fetched check bit.
Developed directly in the read check bit generator is the
syndrome bit, ,which saves one level of gating. Figure 21
shows,the identical Jesuits of generating the syndrome bit
by exciusive-ORing the fetched check bit with the
regenerated check bit and forming the syndrome bit in
the' read check bit generator.
Implementing the syndrome generator word in this way
reduces the circuit propagation delay by approximately
10 nanoseconds. This implementation imposes a
restriction on the code to be used - the check bit must be
formed from no more than eight data bits.

READ
CHECK BIT
GENERATOR

~
SYNDROME
GENERATOR

MEMORY

WRITE
CHECK BIT
GENERATOR

Figure 20. Block Diagram of ECl; System.

5280

DATA BITS
FOR CHECK BIT
GENERATION
REGENERATED-JL../""SvNDROME
CHECK BIT
586
BIT

FETCHED CHECK BIT--\~

2000
FETCHED
CHECK BIT

SYNDROME
BIT

Figure 21. Syndrome Bit Generation.
(

While there are twenty possibilities for syndrome words,
only 16 are needed. Each row contains ten "Is" and each
column contains three "Is." Four columns are
eliminated but in a way that each row contains eight
"Is." When the columns are matched to data bits, the
"Is" i,n each row define inputs to the 748280 parity
generators' for the given check bit. Eliminating the two
columns from each end results in sixteen columns with
each row having eight "Is." These remaining sixteen
columns which match the data bits are rearranged in
Figure 23 for convenience of printed circuit board layout
and assigned to the data bits. The syndrome words for
check bits are also shown for complete code
development.

Figure 19 listed the possible syndrome words for a 16 bit
data word. T'hese are relisted in Figure 22 with the
syndrome words for the check bits and the zeros deleted.

II
I I
II I
I I
I
I I
I I
I
II
II
I I I
II I
I I I
III II I
I I II
\ I \ I \ I I I II

CI
C2
Cl
C4
C5
C6

Figure 22. Possible Syndrome Words with Three Check Bits.

Dala Bit

MI6 MIS MI4 MI3 MI2 Mil MIO M9
X

With this information the check bit generators can be
designed. Figure 24. depicts write check bit generators
while Figure 25 depiCts read check bit generators.

M02 •
M
M03 r
• i 1 8 rEVEN
•
Sl!
M04.
,
M05 ' . 5280
M06 •
rooD
M07 '

Double bit error detection is accomplished by generating'
parity on the syndrome bits. Except for the syndrome
word of 00000o - no error -even parity will be the
result of a double bit error. Hardware implementation is
shown in Figure 26. OR-ing the syndrome detects the
zero state, which has even parity. and prevents flagging
this state as a double bit error.

M08

P/l08 •
M078'
M09 '.
rEVEN
Sl!
M010 :
MOll
• 5280

Decoding the syndrome word must be done to invert the
one bit in error. Combinational logic will decode only
those syndrome states which select the one of sixteen bits
for correction. Figure 28 shows the logic of the decoder.

M05 •
M
M06 0
• 4 8 'rEVEN
M012 :
~
M013 • 5280

:g:~
011
013
016
018
0110
0112
0111
0116

M016
,C4

WO!)
54

5280

M03 •
M04
"
M
0
2 8 1EVEN
~
M09 :
MOll
• 5280
M013 :
1000'.
:g:~
53
C3 I

rooD
Cl

5280
M02 •
'
M 00
5'.
M
1 8 I EVEN
M07 :
Sl!
M09 • 5280

1000
C2

:g:~
M015
C2

013
014·
,
D
1(j2
019
0111
. 5280
0113
IOOO
g::~
C3

. 5.. 280

g::~'

M03 •
.
M06 •O l 8 rEVEN
M
M08:
.
S1
MOIO • 5280

:gg
:.
M016 •

015
.
016 1 ( j 4
0
0112
'.
0113
0114

WOO.
52.

~?OO

.·igure 25. Read Check Bit Generators
roOD
C4

017
018
019
OlIO
0111
0112
0113
0114

.'igure 24. "'rile Chet.'k Bil Generalors

f'igure 26. Double f.rror Decoder

~;::::)D-- DATA BIT 3

~~~::::)D-0ATA 8;r 11

~:::::)D-- DATA BIT 4

M12

B12~

DATA BIT 12

~~::::)D-- DATA BIT 5

~:::::)D-- DATA BIT 6

M14
B14---1

~~::::)D-- DATA BIT 7

M15---\~ DATA BIT

~:::::)D-- DATA BIT 8

Figure 27.Correction Circuit.

.--__. ., INHF . . -4_-~
ECC

MOl
MD2
MD3
M04
MD5
• MD6
MD7
MOB

MD()()- UNCORRECTED DATA
FROM MEMORY

5280
1000

C6
M07
M08
M09
M010
MOIl
MOI2.
M013
M014
C5

M04
M05
M06
M012
M013
M014
M015
M016
C4

M07
M09
M010
M014
M015
C2
MOl

52BO
1000

F='----'
51

S3
54

=g~
M08
M010
MOIl
M012
M018
Cl

55
56

'502

5280
1000

1-------'
Figure 28. Complete Correction Circuit

3-121

Enabling, the correction logic, the decoded B(x) signals
become "high" to invert the output of the 74S86 exclusive-OR circuits. If the B(x) signals are "low" the output
of the correction is the same level as the input. The
correction circuit is shown in Figure 29.
Connecting the five circuits as shown in. the block
diagram of Figure 20 completes the error correction
circuitry.

REFERENCES
I. "2107A12107B N-Channel Silicon Gate MOS 4K

RAMs," Reliability Report RR-7, Intel Corporation,
September, 1975.
2. "211512125 N-Channel Silicon Gate IK MOS
RAMs," Reliability Report RR-14, Intel Corporation,
1976.
3. "2104A N-Channel Silicon Gate 4K Dynamic RAM,"
Reliability ReportRR-15, Intel Corporation, September, 1977.

SUMMARY
An unprotected memory has a system MTBF which is
approximately equal to the device MTBF divided by the
.number of devices. Redundancy codes are used to protect
memories. While parity is a redundancy code, it only
indicates that an error has occurred. A "modified"
Hamming code tan correct single bit· errors and detect
double bit errors; truly enhancing the system MTBF.

4. "2116 N-Channel Silicon Gate 16K Dynamic RAM,"
Reliability Report RR-16, Intel Corporation, August,
1977.
5. R. W. Hamming, "Error Detectihg and Error Correcting Codes," Bell System Technical Journal, Vol. 26
(April 1950), pp. 147 -160.
6. Len Levine and Ware Meyers, "Semiconductor
Memory Reliability with Error Detecting and Correcting Codes," Computer, October, 1976, pp. 43-50.

This report has laid the foundation of ECC basic
concepts. Building on this foundation, the next report
will address the mathematics for calculating the
enhancement factor of ECC in a system environment.

7. -, "Modern Algebra for Coding,"
Technology, April, 1%5, pp. 59-66.

Electro-

8. William W. Peterson and E. J. Weldon Jr., Error
Correcting Codes, MIT Press; Cambridge, Mass.,
1972.

Intel Corporation, 1980

01305A

3·123

AP-73
1.

page and p pages per system. Note that a "page"
is defined as the number of memory words formed
by a minimum set of memory components.

INTRODUCTION

This Application Note explains reliability analysis as applied to a typical memory system_ (It follows Intel Application Note AP-46, which reviewed
basic ECC, Error Corrections Code, concepts.)
A number of examples demonstrate techniques to
calculate reliability of a mo.del memory system,
with and without ECC - emphasizing system
. reliability as a function of the number of devices
in a system and the individual device failure
rates.
.Since, a system with ECC can correct a single bit
failure and detect double bit errors within 'an accessed word, it has a decided advantage over a
system without ECC. A soft error rate of two or
three times device hard failure rate has significantly less effect on the Mean Time Between
Failures (MTBF) for a system with error correction. This is quantified as the Enhancement
Factor, EF - the ratio of MTBF for two identical
systems, one .with and one without ECC. The
Enhancement Factor can be predicted by the
application of statistical analysis.
The general model presented in this Application
Note numerically predicts the chance of memory
system failures during a specified length of time.
It also provides insights into the relationship of
device failure mechanisms and soft errors to
memory system reliability. Intel® 2117 Dynamic
RAM is used in the example memory system. The
reliability data for distribution of hard failures
was obtained from the 2117 Reliability Report
.
(Intel RR-20).

For example, 16K by 1 RAMs would have .a
minimum page size of 16384 words.
Figure 1 represents such a system, with the
horizontal axis corresponding to parallel, address:
accessed data bits and the vertical axis corresponding to the series' stacking of words and
pages. This memory structure is used for the
model system .

3.1 Hard Failures
'Hard failures are permanent physical defects,
such as shorts, open leads, micro-cracks or other
intrinsic flaws. They are classified as single cell
failures, row failures, column failures, combined
row-column failures; half-chip failures and full•
chip failures.
.
The failure type distribution within a device is a
function of the device design. Typical ratios are
50% single cell failures, 40% row' or column
failures, 10% combined failures and less than 0.1 %
half-chip or full-chip failures. (Refer to Figure 4.)
The accumulative independent events are expressed
as a single numeric value for the combined failure
rate of the device (EQ:1a). The standard mathematical symbol for device failure rate is the Greek
letter Lambda, A; i.e., A = 0.027%/1000 hrs.

2. MEMORY CONFIGURATION
2.1 Device
System reliability begins with the smallest physi-.
cal unit, the memory device. Each device can be
considered a system itself, with the smallest functional unit being a single storage cell. Device internal structures have inherent failure mechanisms
affecting individual memory cells.
The structure of a typical RAM device consists of
two-dimensional coordinate-addressed .arrays of
memory cells arranged in rows and columns, such
as the Intel® 2117 Dynanuc RAM shown in Figure
2. This device contains 16384 cells arranged in a
128 row by 128 column matrix; each cell is selected
by an encoded 7-bit row and 7-bit column address.

2.2 System
An array of memory devices on one or more circuit boards forms a typical memory system. A
system is defined by n bits per word, x words per

ERROR CLASSIFICATION

The,2117 failure mechanisms illustrated in Figure
3 are fairly representative for today's RAM devices.
These can be categorized as hard failures and
soft errors.

EQ:la Ahrd= Asingle+ Arow+ Acolumn + Arow/col+
Ahalfchip +Afullchip

3.2 Soft Errors

In contrast to hard failures, soft errors are characterized as being random in nature, non-recurring,
non,destructive single cell errors:
Traditional soft errors are caused by noisy system
environments, poor system design, or rare combinations of noise, data patterns, and temperature
effects which push the RAM beyond' its ,normal
specified range of operation. This type of soft
error has not been included in the analysis to .
follow because it is associated with system level
problems and the rate of failure is difficult to
quantify; in any case it is assumed.to be quite
small.

3-124

AP-73

PARALLEL
BINOMIAL
AXIS
-..n-bits

~ ~ ~ ~. ~ + ~ ~
; W?RO;

Figure 1. Memory Configuration

3-125

AP-73
4.

RELIABILITY

Reliability, as used in this application note, is
defined as "the probability that a component will
operate within specified. limits, for a given period
of time"l.The definition includes the term "probability", a quantitative measure for chance or
likelihood of occurrence, of a particular form of
event - in this case, operation without failure
within specified limits. In addition to the probabilistic aspect, the reliability definition also involves
length of operational time.
Since reliability is concerned with events which
occur in the time domain, they are classified as
incidental failures, which do not, clqster around
any mean life period, but occur at random time
intervals. The exact time of failure cannot be predicted; however, the probability of occurrence or
non-occurrence of a statistical mean in a given
operating frame of time can be analyzed by the
theories of probability. Since exact formulae exist
. for predicting the frequency of occurrence of events
following various statistical distributions, the
chance or probability of specified events can be
derived.

4.1 Component Reliability
Memory systems are operated where failures
occur randomly due only to chance causes. The
fundamental principles of reliability engineering
predict the failure rate of a group of devices which
will follow the so-called bathtub curve in Figure 6.
The curve is divided into three regions: Infant
Mortality, Random Failures, and Wearout Failures.
All classes of failure mechanisms can be assigned
to these regions.

Figure 2. Random Access Memory Device

Other soft errors are caused by ionizing radiation
of alpha particles changing memory cell charge
in semiconductor substrates with high impedance
nodes. The data bit error is realized during a
memory read to th~ failing cell. These errors are
purged by rewriting (restoring) the correct data
bit information to the cell. The failure rate for this
type of soft error is stated separately. from hard
failures because of its unique properties.
The total devIce failure rate becomes:
EQ:lb Ad" = Ah,d

+ ASft

The pie graph in Figure 5 depicts the combined
distribution of both hard and soft errors.

Infant Mortality, as the name implies, represents
the early life failures oLa device. These failures
are usually associated with one or more manufacturing defects. Memory device failures occurring
as the result of Infant Mortality have been eliminated by corrective actions relating design,
inspection, and test methods.
Wearout failures occur at the end of the device's
useful life and are characterized by a rising
failure rate with time as the device's "wearout"
both physically and electrically. This does not
occur for hundreds of years for integrated circuits.
The Random Failure portion of the curve represents the useful period of device life. As stated,
memory devices are operated in systems during
this period when failures occur randomly .. The
number of failures occurring during any time
interval Within the "Random" period is related
only to the total numbe~ of memory components
1 Reliability Mathematics - Amstadter

ROW-COLUMN
(256 CELLS)

HALF-DEVICE
(8192 CELLS)

FULL·DEVICE
(16.384 CEL~S)

Figure 3. Failure Geometry -

3-127

2117 Example

~P-73

COMBINED HARD FAILURE RATE=O.027%/1000 hrs

50%
SINGLE CELL
1 CELL

::::0%

ROW-COLUMN
256 CelLS

Figure 4. Failure Distribution - 2117 Example

SOFT ERROR SINGLE CELL RATE HARD ERROR COMBINED RATE -

operating. If sufficient numbers are operated, and
the measured interval is long enough, failure rate
approaches some relative constant value. For any
given component type, the failure rate value will
depend on operating and external environmental
conditions (voltage, temperature, timing, etc.) and
will be characteristic of this set of conditions.
When the conditions change, the failure rate will
correspondingly change.
For' example, if 500 devices are tested for 1,500
hours and two failures were observed during. the
test interval, then the failure rate is two failures
per 750,000 device-hours or one failure per 375,000
device-hours. For commonality, device failure rates
are expressed as a percentage value per 1000 devicehours. The above example then' becomes .00266
failures per 1000 device-hours or Adey = 0.27% per '
1000 hours. This is an overly simplified statement
on determining the device failure rate. Many tests,
designed to stress the devices over operating conditions and margins, are used in the final analysis
for the specification .of device failure rates.

0.1% PER 1000 hrs
0.027% PER 1.000 hrs

TOTAL = 0.127% PER 1000 hrs
HARD ERRORS
50.0% SINGLE CELL

4.1.1 RELIABILITY FUNCTION R(t)

The Reliability FUilction, R(t), follows an inverse,
natural logarithmic curve, which expresses the
rate of change for a memory component from an
operational state to a failure or error condition.
The curve is a familiar one to the physical scientists because of its relationship to growth and
de<;ay.

15.6% ROW
28.1% COLUMN
6.2% ROW/COLUMN

21.2%
COMBINED
HARD ERRORS

The general function for reliability is given in
EQ:2 where the exponent (A . t)represents the
device failure "lambda" times the independent
time variable "t". The graph in Figure 7 shows
the shape of the R-function curve. '
'

78.7%
SOFT ERROR
SINGLE CELL

R(t)=e-Io.t

EQ:2
Figure 5. Combined Distribution of 'Failure Type
1,0

RELIABILITY LIFE (BATHTUB) CURVE
~

Figure 6. Reliability Life Curve

Figure 7_ RCt) - Reliability Funcllon

3-128

AP-73
For any constant failure rate the value ofreliability depends only on time. The limits ofthe reliability function R(t) are:
R(O)

= 1.0

and H(oo)

= 0.0

The distribution is a one-parameter type; in that
once the failure rate is established, the reliability
function is completely defined. For high or low
failure rates the general shape of the curve
remains the same, but is adjusted along the time
axis.

4.2.1 EQUATION FOR A SERIES SYSTEM

The Reliability.Function for a series system is the
product of the reliabilities of the individual
components. If "nz' components with corresponding failure rate of AI, 11.2, 11.3, , , , 11.71 operate in
series to form a system then the equation for system reliability is:

EQ:3

R(t)sys= R(t) l' R(th' R(t)r , , ,R(t)."
where R(t)j = e- Aj·t

If each of the n components has the same device

4.2 System Reliability
Just as there is a functional relationship between
the components and the system, there is a functional relationship between component reliability
and system reliability. If a failure in anyone of
the components of a system causes the entire
system to fail, the system is a "Series System"
(Figure 8).

Figure 8. System of Series Components

If all the component devices must fail before the
system fails, the system is a "Parallel System"
(Figure 9).

failure rate lambda, then the system reliability
equation reduces to:

4.2.2 EQUATION FOR A PARALLEL
BINOMIAL SYSTEM

One of the fundamental concepts of reliability
engineering is the Binomial Theorem. The theorem
is used for computing the reliability of complex
redundant systems, where "j" out of "n" units are
required to operate for system success. The binomial distribution expresses the probabilities of
two states of an event, "a" and "b", where. the
event is permutated "n" ways. The general form
of the binomial distributiol) is (a + b)71, and is
expanded to:

EQ:5

a71 + rya'1-1'b +ry(1/I)a'1-2. b 2+

2!
ry(1/1 )(1/2)a'1-3. b3 + ... +b71
3!
It is applicable to a memory system operating in

parallel; i.e., when there are only two possible
states or results of an event - when a component
of the system either conforms to requirements or
is discrepant.
Figure 9. Parallel System

If a system has 'n' components which operate in
parallel, but 'j' out of the 'n' components need to
befuncponal for the system to operate, then this
system' is referred to ,as a "Parallel Binomial
System" (Figure 10).

}
Figure 10; Parallel Binomial System

If we assign to one state the function of reliability

- R(t), then the other state is Q(t), the function of
non-reliability, which is the probability of being
inoperative.
Recall that R(t) is a unity function, which ranges
from 1.0 to 0.0, as a function of time. Since the
sum of R(t) and Q(t) make up the whole "event",
then EQ:6 defines Q(t). This relationship is also
illustrated in Figure 11.

EQ:6
3-129

R(t)

+ Q(t) =

1 , then Q(t) = I - R(t)

. AP-73
By substituting R(t) and Q(t) respectively for a
and b, where R(t) is the probability of a device
being good, Q(t) is the probability of .the same
device being defective, and "n"the number of
units in parallel, then:
1.0

0.0

am
PROBABILITY
OF FAILURE

L-_ _ _ _ _ _ _ _.-!._ _
O.

Note, for simplicity, all references to (t) for the
reliability and non-reliability functions will not
btl indicated, but implied.'
.
It follows that the expansion of[R + Q]I) must also
equal unity example
EQ:8

R I) + rJRI)-I'Q

+ rJ{ rr I )R7f-~'Q2 +
2!
1)-3

rJ(rrl)(rr2)R

+".o + Q)=

which two are operative and one fails, then three
possible combinations exist: X and Yare operational and Z fails, X and Z operational and Y fails,
and Y and Z operational and X fails. The probability of each combination is (RxRyQz) + (RxQyRz)
+ (QxRyRz).
.
Again, since each combination is mutually exclusive and together they constitute all possible combinations, the probability of two operational devices
and one failure is 3R2'Q. Similarly, if there are n
·component~devices, the probability of all but one
being operative is nR'l":'1 . Q. Thus, the second
term of the binomial expansion series is the probability of exactly one device failure, and all other'
devices being good.
.

0.5

PROBABILITY
OF SUCCESS

If there are three' components X, Y, and Z, of

3!
We can next examine the meaning of each term in
the series on the left side of EQ:8. Suppose that
there are "n" identical components of a system, of
which the probability of a compone~t being
. operatiVe is R, and that the probability of its
being inoperative is Qor (1 - R). If there is only
one component (n =1), then the probabIlity of its
being not defective is simply R.

= 2), then the
probability of both being operative is R X R = R2;
and if there were three components, then the
probability of all three being good is R3. Consequently, if there are "n" components, the chance
of all "n" units being operative is RI) and the first
term in the series RI) is the probability of all
components being 'operational.

If there are two' components (n

By extending these derivations to cover each succeeding term, we find that the third term is .the
probability of exactly two failed components, the
fourth term is the probability of exactly three
I failures and so on. There are n + 1 terms in the
expansion, and· the .last term Q is the probability
all components are inoperative.'
.
The reliability of a· group of redundant items
depends not only on the reliability of each indi~
vidual item and on the number of items in redundant configuration, but also on how many are
required to operate to achieve system success. If
all are required, then the first term of the binomial
series represents system success. In this ca'se
there is really no redundancy. However, if all but
one are required (one failure perinitted), then
success is achieved if no failures occur or exactly
one failure occurs within word accessed from a
page of memory. The system reliability is thenthe
slim of the first two terms of the series .
If two failures are permitted, then the sum of the

first three terms represents the probability of
system success. In general, if r failures are permitted, system success is the sum of the first r + 1
terms.
The general equation then for a binomial system,
permitting one error, which is representative of a
memory system with single bit error correction ECC per accessed word is ex~ressed as:
EQ:9 RT(t) = RI) + rJ'RI)-I'Q

Next, suppose. there are two components X and Y,
one is operative and one has failed. There are two
ways that this can occur: X is operational and Y
fails, with the. probability Rx . Qy; or X fails and Y
is operational, with the probability Qx . Ry. Since
these are mutually exclusive and constitute all
possible combinations of one operative component
and one failure, the total probability is (RxQy) +
(QxRy), or 2RQ.
.

I st

2nd - binomial terms

Note that the remaining· terms 'of the binomial
expansion represent all combinations of failures
that are greater than oile failure, up to and including all componertts failing. RT(t) is still a unity
function of reliability and has a converse QT(t),
where QT(t) = 1 - RT(t). Thus; QT represents the
3rd through n-th terms of the binomial.

3-130

AP-73
5.

RELIABILITY ANALYSIS USING
PAGE/SYSTEM APPROACH.'

~
-A·n·t
EQ:ll R(t)PAGE necc = R(t)OEV necc = e

. .The analysis of the model system in Figure 1
begins with EQ:2 at the smallest non-redundant
failure level; by using standard rules for series
and parallel reliability, the combination of these
device exponential expressions will yield the system reliability equation. The method of approach
will be to calculate the reliability of a page of
memory and treat subsequent pages as a series
system where:

where "n" is the number of components in the
page and ~dev is the device combined failure rate.
The reliability for the memory system of "p"
pages is:
EQ:12
R(t)sys necc

=[ R(t)PAGE nec c1 p= l R(t)6EV t~

EQ:lO R(t)system=; [R(t)pagel P

5.2 Memory System With ECC

For clarity, the reliability of power supplies, fans,
backplane connections, TTL support logic, etc.
will not be included. These iteI1Js can be merged in
the final analysis by the reader as additional
series system equations for each type.

The analysis of reliability of a memory system
"with ECC" - (single bit error correction) is more
complex. The fundamental difference between the
two memory systems is that in a non-corrected
system, any error - no matter the type, single cell
failure, row failure, soft error, etc. - is considered
a system failure. In a memory system with ECC, a
system level failure only occurs when more than
one bit has failed in an accessed word.

5.1 Memory System Without ECC
The analysis of reliability of a memory system
"without" any form of ECC is simply the first
tenD. of the binomial equation EQ:9. Since this
terIn represents reliability of all components in a
page of memory without redundancy, it is equivalent to a "series system" equation (EQ:4). Therefore, the equation for a page of memory without
ECC is:

Thus in the analysis of a System with ECC, we
must deal with the probabilities of each failure
type occurring in random combinations which
align within a word of memory to cause multiple
bit failures as shown in Figure 12.

Memory Page Accessed Word Failure Alignment

.Figure 12. Memory Page Accessed Word Failure Alignment

Msz - Memory Page Size
Isz - Failure Size

Rp••• 0 [Rfil

Figure 14. Multiple Failure Type Illustration

Now that the binomial equation technique has
been applied to a single failure type, let's expand
the process to cover more than one failure type.
By the process of combining or permutating these
failure types, the Reliability Function can be calculated. Figure 14 shows a four component
system with the probability that two failure tYPes
.Ii or.li can occur in each component. Both failure
types affect fszl and fsz2 number of cells during a
failure, respectively. The calculation begins with
evaluating the probability offi occuring (EQ:14a)
and merging by a second calculation the probability of failure type f2. (EQ:14b).
ry

EQ:14a ~TI

EQ:14c
fsz

AI1_A dey ·X!·---.!.2
1 Msz
The total reliability for the page in Figure 13b is
given by equation 14d.
Msz
EQ:14d

R(t)page= [RT2J fsz~

By expanding on this process the equation for a
system of memory components with these failure
types: .Ii,.!i..h is given in EQ:15 ..

)1- 1

= Rtl + 7)Rtl 'Qtl
ry

EQ:14b

EQ:14c is the unit failure rate equation forti and

.Ii in this case.

ry-I

RT2 = Rh'[RTPJ + 7)[Rh"RtfJ 'Qh

EQ:15

NOTE: with Adev representing more than one failure type,fi andfi, Adev must be proportioned to the
"failure-type-distribution" in determining the
unit failure rates A/I and A!z. The term X/I and
Xh are introduced to quantify the failure type distribution as a percentage. (Ref: EQ:l and Figure 5).
3-133

We can now formulate a general set of equations
for multiple (fI) failure types in an error corrected
system.
.

AP-73
5.2.1 EQUATIONS FOR THE MODEL
The full model under analysis in this report has
six failure types, as described in the section' on
Error Classification. The reliability calculations
for a page of memory must permutate all combi'
nations of these six failure types. It is accomplished
by the set of equations in EQ:16.

5,2.2 THE ENHANCEMENT FACTOR
5.2.2.1 Mean Time Bel10veEm Failures

The Mean Time Between Failures (MTBF) for a
memory system, with or without ECC, is given in
EQ:17. MTBF is calculated by integrating the
system reliability function, R(t)sys, from t = 0 to
infinity .

Ri
t. Q,
1- Ri
Rs,- R, (Rs,-Il ,
RT, = R;'(RTi-ll'+ l')(RSi)ry-I'Qi

I ,

}~~~

MTBFsys = fR(t)sys'dt

On the average a system will fail once every
MTBFsys hours. The relationship between MTBF
and the R function is shown in Figure 17.
The bottom line conclusions on the effect that errorcorrection has on a given memory system is calculated by comparing the resultant MTBF ,ys-ecc
projection with the MTBF 'y'-necc of a similar system without ECC. The improvement of a memory
system with error correction logic over a comparable system without is expressed by EQ:18 asthe
enhancement factor EF.

= [R(t)PAGE ecc {ages
restrictions: RSo = RTo = fszo = 1.

R(t)SYSTEM ecc

The process begins at the word level with soft
errors and gradually increases the area of evaluation to single cell hard failures, then row or
column failures, combined row/column failures,
half-chip failures, and finally full-chip' failures.
Illustrated in Figures 15 and 16 are the six iterative steps to merge all combinations of failure
types - fi, Ii, fi, f4, Is, f6.
The first step calculates the chance of a single
word of the memory page not having more than
one soft error.

EQ:18

EF = MTBF sys-ecc
MTBF sys.necc

5.2.2.2 Mean Time To Failures

The second step calculates the probability of not
having more than one single-cell hardfailureand
merges step #1, for a combined result that no more
than one failure caused by either soft error or
single-cell failure has occurred within the single
word analyzed.
The third step calculates for row failures and
merges with step #2 all combinations ofthe three
failure types. Using the 2117 example memory
system from Figure 6 to illustrate this point - a
row or column failure affects 128 memory words
- the combined result from step #2, which analyzed a single word, is raised by the exponent 128
as a series equation. The combined result for step
#3 is the probability of not having a system
failure due to any of the failure types fi ,/2, Ii, in
any given word for a 128-word block.
This process continues up to step six, which'is the
calculation for all six failure types occuring in all
combinations that would cause a system failure
within the page of memory. The analysis of each
step therefore raises the results of each previous
step by the exponent ii.

The Mean Time To Failure (MTTF) is similar in
concept to MTBF, but differs in that it represents
the effects of maintenance on an error. corrected
memory system. When a maintenance policy is
adopted which allows for the replacement of
failed components before the system fails, system
failure is postponed (depending on how often the'
system is inspected and maintained). With this
policy a memory system fails less frequently than
it does without maintenance; it is assured that
every new operating period after inspection starts
with full redundancy restored. The maintai,ned
system .Mean Time To Failure thus becomes
greater than MTBF,y,.
If preventive maintenance is performed at an
arbitrary time T, then EQ:19 expresses mean time
to failure.
'

EQ:19

3·134

R(t)sys-ecc ·dt
MTTF _-=--o-----.=.~_ _
1 - R(T) sys-ecc

User Oefinltlons
2117 example

is =

I, = Soft Errors
I, = Single Cen Hard
I, = Row or Col Failures

l, = /sz,

''65 = Tolal Chip Failures
'sz, = 1
'sz, = 1
'sz, = 128
'sz, = 255
, 'szs =8192
'sz6 = 16384

Isz,
fSZ4

6,384

" = Combined Row/Col
= Half Chip Failures

X, = ,106
X, = ,092
X, = ,013

£, = 2
£, = 128
£2 = 1
j', = 1

RT, = combine[RT,]1',
-;""d-+-+--1128

RT, = row-COlo[RT,]i,
}
Adev

l' '

I. R" = single-ceno[RT,] ,

Ahrd + i\sft

I RT, = soft-errors

++++++++
~qRD:

,
1sz1
AIi = Adev • Xi • Msz

R, = e-"o, , 0, = 1 - R,

}

Rs, = R,o (Rs,_, ) £,
, = R,"(R
RT,
0
T,_, )£.,+ ry ( Rs,) '1-' • 0,

AP-73
5.2.3 SOFT ERROR SCRUBBING

5 -_ _ _ _L--, 111+12+13+141

&--'--------'--

+ .5 -

In the previous sectioris on MTBF and MTTF, soft
'errors and hard errors were treated the same.
They both accumulated to cause system failure or
, were removed at scheduled preventive mainte·
I?-a~ce (PM) intervals.

RT.S

{11+'2+'3+14+151 + 16 - RT.S"

Figure 16.

_---~~ MTBFsys

I
MTBF
HOURS
(THOuSANDS)

1.01---_'R

Figure 17.

Figures 18 and 19·show the relationship ofMTTF
to'the R function and M'ITF to MTBF respectively.

However, soft errors can have their own special
maintenance function. Recall that soft errors can
be purged from a system with ECC by rewriting
(restoring) the correct data bit information to the
failing memory cell. (Provided that no other bit
within the word containing the soft error has
failed.) Thus it is possible for the system to
maintain itself by software, etc. This special
maintenance function of scrubbing soft errors at
predetermined intervals is incorporated into the
system reliability equations by merely resetting
the time parameter t for the soft error portion of
the equations.
Figure 20 shows the relationship of soft error
scrubbing on MTBF and the system R functions.
~_--......,MTBFsys

The enhancement of a memory system with main·,
.tenance over a comparable system without ECC
'
,
is expressed in EQ:20.
EQ:20

5.2.4 APPLYING THE MODEL EQUATIONS

The basic set of equations for a model are derived
from EQ:16. The application ofthese equations is
best suited for implementation on a computer. An
example computer program is available on request.

TIME

Figure 18.

Figure 21 illustrates a simplified block diagram of
the model.

f R(t)sys' dt

O(T)

MTBF - mean time 10 failures

R(t} • system reliability function:
EFec::c: - enhar;acement factor

outpuls:

-------~----Figure 21. ,
LOG/LOG
SCALE

The required user'inputs are for component parameters - total memory size, number of rows and .
columns, hard failure rate, soft error rate, and

P.M. TIME

Figure 19.

3·136

AP-73
II. Table 3 shows the comparison of six memory
configurations, between two soft error rates.

failure mode distribution; for system parameters
- memory word size, ECC check bits, number of
pages, interval of time, and soft error scrub time.
Output is a set of discrete values of the reliability
function representing the complete memory system as a function of time.

Table 3. Memory Configurations versus SE Rates
HARD FAILURE RATE = 0.027% /1000 hrs

The integral functions for MTIF and MTBF are
evaluated by the trapezoidal rule of integration.
EQ:21

MTBF= ~11:!-[Rsys_I+Rsysl.lTime
i.::: I

where Rsyso = I
.1

Based on the Intel@ 2117 Dynamic Ram, the following three sections - (I, II, III) - compare
various system configurations and failure rate
parameters.
I.

Table 1 shows the comparison of six memory
configurations, ranging from 32K-bytes to 16
Megabytes. The Input parameters used were
those listed in Table 2.

configuration
16-bit word by '1 pg
16-bit word by 128 pgs

SOFT ERROR
RATE
1'1000
hrs
..2%
__ . __ ......
-_ ....... _-.....
MTBF. ecc
880 k hrs
70 k hrs

SOFT ERROR
,RATE
.5%/1000
hrs
.._--_
..... _- ..........
.
MTBF. ecc
575k hrs
44 k hrs

1 pg
32-bit word by
32-bit word by 128 pgs

492 k hrs
39 k hrs

322 k hrs
24 k hrs

64-bit word by
1 pg
64-bit word by 128 pgs

265 k hrs
21 k hrs

173 k hrs
13 k hrs

III. Table 4 shows the comparison of a memory
device with one failure type. The failure types
compared are devices with a single cell
failure modes and full-chip failure modes.
System A has devices with only "single cell"
failure types and System B has only "fullchip" type. All other parameters are identical.
Both system failure rates are 0.027%/1000
~L

Table 1. Memory Configuration versus MTBF
FAILURE RATE = .127% /1000 hrs
configuration

fII1TEl£,\non:~c~

ecc--_MTBF.
.. _- - ..........

E.F.

1 pg
16-bit word by
16-bit word by 128 pgs

49 k hrs
390 hrs

1170 k hrs
95 k hrs

24
249

1 pg
32-bit word by
32-bit word by 128 pgs

24 k hrs
195 hrs

658 k hrs
53 k hrs

64-bit word by
1 pg
64-bit word by 128 pgs

12 k hrs
98' hrs

355 k hrs
29 k hrs

27
278
29
299

Table 4. Single Cell versus Full Chip Failures

configuration:
64-bit by

SYSTEM A
with
........ ~inlll"'.~ell ..
MTBF

1 page

64-bit by 128 pages

SYSTEM B
with
...fll"~c:~.ip' ....
MTBF

Table 2. Model Input Parameters

5.2.5 DISTRIBUTION

Combined HARD FAILURE RATE = 0.027% / 1000 hours
Failure distributions:

Error correction in a system does not alter or
change the actual occurrence of failures. Failures
still occur at the MTBF necc period based on the
distribution in Figure 5. (For the example system,
the soft error rate is three times the hard failure
rate - .1% vs .. 027% - which represents a soft
error occurring 78% of the time.)

= 50.0%
single cell
row cells
= 15.6%
column cells = 28.1%
row-column cells
6.3%
half-chip
0.0%
= 0.0%
full-chip
total 100%
SOFT ERROR FAILURE RATE

= 0.1% /1000

hrs - est.

These results show an enhancement factor of
approximately 27 for a single page of memory
and over 278 for 128 pages.

. However, the fact that a multibit failure is required to cause a system failure in a system with
ECC modifies the failure distribution; soft errors
have much less effect than hard failures on
system performance. Figure 22 demonstrates this
by showing a modified distribution based on
average cells per failure, the Rate Geometry
Product, RGP.

3-137

AP-73
6.
INDIVIDUAL FAILURE RATE DISTRIBUTION OF A GIVEN TYPE
TIMES THE NUMBER OF CELLS AFFECTED
EQUALS AVERAGE CELLS PER FAILURE

This Application Note presents step-by-step
procedures for calculating system reliability. In a
system without ECC, a fault of any type can
cause system failure - predominantly types with
the highest failure rates. In a system with ECC,
only multi· bit errors within the same word cause
system failure - predominantly types with the
highest average cell errors as defined by the Rate
Geometry Product. An Enhancement Factor,
comparing a system without ECC to one with
ECC, can be used to determine if error correcting
techniques are advantageous for any specific
memory system.

FAILURE TYPE
SOFT ERROR:
SINGLE CELL
HARD ERRORS:
SINGLE CELL
ROW
COLUMN
ROW/COLUMN

CELLS

% DISTRIBUTION

78.7%
10.6%
6.0%
3.4%
1

DISTRIBUTION BY NUMBER OF AVERAGE CELLS

References
L Randall C. Cork, "Reliability with Error-Detecting and
Correcting 'Codes in Semiconductor Memories," Ph.D.
dissertation, Arizona State University, 1975.

Figure 22.

The illustration shows the statistical average cell
failure for each type derived by taking the product
of the. component failure rate distribution times
the number of cells affected. For the 2117 example
device, the total average cell failure is 16.2 of
which 11.8 are column and row failures.
intuitively, it can be seen that row -and column
failures are the most predominant, while the least
predominant are soft errors and single cell hard
errors.

3-138

2. Bertram L. Amstadter, Reliability Mathematics Fundamentals; Practices; Procedures, McGraw Hill, N.Y., 1971.
3. Byron L. Newton, Statistics for Business, Science Research
Associates, 1973.
4. Carl-Erik W. Sundberg, member IEEE, "Erasure and Error
Decoding for Semiconductor Memories", IEEE 1978.
5. Peter Elias, "Error Free Coding", MIT.
6. S.K. Wang & K. Lovelace, "Improvement of Memory Reliability by Single-Bit-Error Correction", Texas Instruments
Inc.
-

Ahrd= Asingle+ Arow+ Acolumn+ Arow/col+ Ahalfchip +Afullchip

EQ:lb
EQ:2
EQ:3

R(t) = e- At

. R(t)sys= R(t)!, R(th' R(th, , ,R(th
where R(t)i = e-Ai't

EQ:4

R(t)sys.= R(t)'1 = e -'1At

EQ:5

a'1 + 1]a'1-1'b +1](1/I)a'1-2, b 2+ 1](1/ 1)(1/2)a'1-3, b 3+, "+b'1

EQ:6

R(t) + Q(t) = I , then Q(t) = I - R(t)

EQ:7

[ R

EQ:8

R1] + 1]R'1-1'Q + 1](1/I)R'1-2'Q2 + 1](1/1)(1/2)R'1-3'Q3 + ' , , + Q'1 = 1

+ Q ]1] = 1
2L

EQ:9

RT(t) = R1] + 1]'R'1-1'Q

R(t)system=: [R(t)page.l P

EQ:ll

R(t)
.
= R(t)'1
= e-A:n,t
. PAGE necc
. OEV necc .

EQ:12

R(t)sys necc =[ R(t)PAGEnecc]P=[ R(t)OEvt'1

EQ:13

R(t)PAGEecc=
ry

EQ:14a

[R(t)~ + 1]'R(t);-I, Q(t)lx
1)-1

RTI = Rfl

+ 1]RfJ'Qfl

EQ:14b
EQ:14c

AI _ A 'Xf' fszfl
1 -deY

·l=~
.
1
fSZi_1
._
fSZi
1 Vi - Adc,' Xi' MSZ

restrictions: RSo = RTo = fszo = 1.

3-140

AP-73

EQ:17

MTBFsys = fR(t)sys·dt

EQ:18

EF - MTBF sys-ecc
MTBFsys-necc
.

EFmnt ~M~T;;-;B~F;';--
sys-ecc

EQ:21

MTBF=i ll/~'[RSYS_l+RSysl"IlTime
= I,
I
I

UNIT FAILURE RATES
Ahrd.ihll

UNIT ROW SIZE
SYSTEM WORD WIDTH

CIIIIII#IIII#IIIII#I#####I############################ ##
#
ECC RELIBILITY MODEL
REV 6B FEB79
#
r'
#
#
,-.
#
I NTEL CORP
#
r
#
MEMORY PRODUCTS DIVISION
#
C
#
?-iPPL I (;(.~ T ION:::: LAB
#
r'
#
?%LOHA. OREGON
#
,-.
#
#
C
#
#
C
#
~RROR CORRECTION RELIABILITY

C
C

#1:lt#4t##I#II###I##'IIII#III##I#####I############

0001
0002
000:::':
0004
0005
000f.~·

001 ~5

0016
001.7
001::::
C
001."

00:2:::::
0024
0025'

0026
00:27
002:::;:
002."
00:30
OO:~:t

00::::2

00:;::::::
00::':4
00:35

00:36
00::::7
OO:~:E:

IMPLICIT REAL*8 EO.R.S.T. ZI
DIMENSION KM(2).LH(2J.KL(4J.LQ(4)
BYTE LL(2).LR(21. IBUF(80). ILIST(80)
INTEGER*4 IIPTR.LPTR(13). IABORT. IHELP.LMFLGS(:3).IIXFG
COMMON IECC1/RXZ. RXS. RXR. RXC. RXF. RXE. RXH. RXT. RCNF. SZER. SXX
COMMON IECC2/RMSZ. RCSZ.RWD. BPG. RZD,RZOO, REC, RZERiRl.RTM,RTSF
COM~JN IECC:3/IM. ILLM. IULM.RSQ. JSFLG. EPGX. ISFLG.ST.R.RTH.R2
COMMON IECC4/ISW.RFF. IPM. RTTF. RZTTL. ICST.RALMT.IDBK.IQFG. IUCD
COMMON IECC5/ISFG.REC1.REC2. IEFLG •. RZSYS. ILIM. IOFLG.RAVE
COMMON IECC6/ITIN. ITOUT. ILP
COMMON IECC7/RZZ. RZS. RZR.RZC. RZF.RZE. RZH.RZT.RZDX
COMMON IECCS/ECI. ECS. ECR. ECC.ECF. ECE. ECH.ECT. ECX
COMMON IECC."/EW.EW1.EW2.RW,RW1.RW2.S.T.TSFT.THRO
COMMON /ECCA/EPG. EBD.EP8Z. ECA. EPX. EPY. EPZ
COMMON IECCC/I. IMN. RPRT.RTO. RTPG.RTX. RZDZ. RXX. RSPC1. RSPC2
DAT'(\ KLf'"
"', "'* "', . ' $ ...• "'*$"'1. IABORT/···ABOW·/. IHELP/'·HELp···/·
DATA' KI'1/"'KB"', "'MB"'I, LL/'" ". ····C··l .• LR/'" ...• "')"'/
DAT('~ LMFLG:::::/'" ::::Y::::··· . ···MPO···. ···M:=:O···./'

0007
000:::;:
0009
001.0
0011.
001.2
001:3
0014

0020
0021
0022

(:)PPLI CAT IONS NOTE

:::

4·

OATf.% L.PTR/···LIST···. " ::;;r ZE ...•..' RATE'· •..' OI::H···. " ClJMM···. ···OUMP·". ···FLAG·'.
* ···HXDR··. ···CYCL.···. ···PURG···. ···NECC···. ·. SECC···. "'[,fCC'" /
8
9
10
11
12
13
DAT(' L..C!/···G!l···. ··'C!2···. ···OX···. ···OZ·,,/
D('HA LH/'" _ ...• ···M-···/. IBELl1799l
D,"\T(.\ !TIN/51. ITOUT.l7/ . ILIM/l0/. IDFL..Gl1/. ILP/61
DATA RXZ/. 787400/. RXS/. 5000/,RXRl. 15600l.RXC/. 28100l.RXEl. 062D(
DATA RXH.lO. ODO/.RXT/Q 000/. RCNF/. :3700l.SZERl. 10-4/
DATA RRXS/5Q DO/.RRXR/15. 6DO/.RRXCl28. lDO/.RRXEl6. 200l
DATA RRXH/O. ODOl.RRXTlO. OOO/;SXXll. 0001
DATA RMSZ/16:384. ODO/.RCSZl128. ODO/.RWD/64. 000l.BPGl128. 0/
DATA RZD/O. 00027DOl.RZ~ElO. 001DO/.RECl-1. 000/, RZERlO. 0001
DATA RRZDfO. 027DO/.RRZSElO. lDOl.RRZTTLlO. OOOl.RRZSYSlO. 0001
DATA ~1/1. ODO/.RTM/2500. 000l,RTSFll000. ODOl.RAVE/228. 000/
DATA IM/O/. IL..L.M/O/, IUL.Ml:30/.RSOl2. ODOl,JSFLG/ll,EPGX/l. Ol
DATA ISFL..Gll/,STlO. ODOl;Rll00. ODOl.RTH/l00000. 000l.R2/2. 0001
DATA ISW/lif.RFFlO. 000/, IPMll0/.RTTFlO. 000/. RZTTXlO .. ODO/
DATA ICST.l2/.RAL.MT/O. 0100/. IDBKll/. IQFGlll. IUCOlOl. ISFG/ll
DATA RECllS. ODO/,REC2l15. 000/. IEFLG/Ol.RZSYXlO. OOOl
DATA IL.FG/1/.RTMSOlO. ODO/.RZTMP/Q 000/. JXFG/ll
DATA RZBI/O. ODO/.RZS2l0. ODO/.RRZSll0. 000/.RRZS2/0. 0001
D{H,:';, TTMCYL/!::i·. 002/, TMCYL./!'.:i. 002/, TTRCYLl1.. 504/. TRCYLll. 5D4l

3-144

inter

AP-73
V02. 04

FORTRAN IV
0039
0040
0041
0042

DATA TREF.l7. 03/, RRX1A.l66. 00.1, RX1A.I. 66DO.l, RRX1B/:;:3. 00/, RX1B.I".33DO/
RPSZ=RZER
SLM=RZER
EPG=BPG

r'-'

C###fi:################ REL I AB I L I TY EG!UAT IONS ###########.###############
C
,~

r'
C
r'

"*"

ReT] = N*GlT*[ RT*(RE*(RF*(RS*(RZ)**MS)**MF)**ME)**MT ]**(N-l)
(RT**N)*C N*GlE*[ R:=*(RF*(RS"*", /,
C T4, ~INTEL CORP. MPD/MCO
DJM FEB79',//.
C 14. 'FOR PROGRAM DESCRIPTION ENTER) HELP')
C######################################################################
10

INPUT PARAMETERS

C#######################################################################
C

0045
004·6
00470048
0049
0050
0051
0052
005:::;:
0054

100

CONTINUE
WRITE (ITOUT.90) IBEL
';'1)
FORMAT (A2.T5. 'POINTER, INDEX, TIME .• PAGE, BOARD')
101
FORMAT (T2. '** LIST OUTPUT PARAMETERS **',/,
C T2. "'* LOWER. UPPER. :::;KIP. UNCOND. MHINT • . CONF···)
1.02
FORMAT (T2. '** COMPONENT & MEMORY SYSTEM PARAMETERS **',/,
C T2. "'* RAM::HZE..
COLSIZE,
WORDSIZE.
CHECKBITS"')
10:3
FORMAT (T2, '** DEVICE & SYSTEM FAILURE RATES **'./.
C 12.'* . HARDX, . SOFTX, . TTLX, . SYSTEM%')
104
FORMAT (T2, '** DEVICE HARD FAILURE TYPE DISTRIBUTION **' . .1",
C T5. 'HINT: SC ROW COL CMB HLF FULL'./,
C T2, "* X2. X. X3. X, X4. X, X~ X, X6. X, X7. X~)
105
FORMAT (-T2, "** HEADER COMMENT **., , /, T2. "'*.,. ).
106 FORMAT (12, ... # ..,)
107 FORM{H (T2 •..' ** ERROR **". 1. X, 12)

V02.04
FORMAT FLG-'. I3.2X, 'CK-'.F4. O.2X. 'PG-'.
CF4. 0,3X. 'BD-',F4. 0)'
GO TO 200
190 CONTINUE
WRITE (ITOUT. 1091
~EAO (ITIN. 192) TTMCYl.TTRCYl.RRX1A.RRX1B
J. 92 FOf;:t'1(,T (:2 (F 1. 2. () I'. 2·( F::;:. II·) )
I EFl . Ci~'O
IF (CTTMCYL. LE. O. 01. OR. (TTRCYL LE. O. 0»
IEFLG=i
IF «RRX1A+RRX1BI. GT. 100.) IEFLG=2
IF «RF:X1(!;. LT. O. ). OR. (RF<:Xl.l::. L.T. O. » IEFLG=3
IF (IEFLCi. NE. 0) GO TO ~93

R X 1. (\""RRX 1('V 1. 00.
RX.1. B,-"PRX 1 B/ 100.

0223
0224

193

CiO TO 100
WRITE .(ITOUT, 194) TTMCYL.TTRCYL.RRX1A,RRX1B

···~2(F12,O~1.X)J2X~2(FE:.4,}1X»

GO TO 100
CONTINUE
PURGE
DO 197. INIT~1.5

3·148

AP-73
V02. 04

FORTRAN IV
022'~

02:30
02:31
02::::2
023:3
0234

196
1.97
198

WRITE (ILP,l~'t:.) (ILlST(NN),NN=L72)
FORMAT (T2,72A2)
CONTINUE
WRITE (ILP, 19::::>
FORMAT (lHl)
GO TO 100

1-'

C#I#I###################################################1111###########
C

C
r'

I NIT I r"tL. I ZE PARAMETER!::;

C######I#I#I################I###########################1#######111#####

0235
02:36

200

02:3B

02:39
0240
0241
024·2
0243
0244
024·t:.
0247

CONTINUE
IF (IEFL.G. EQ. 0) GO TO 202
WRITE (ITIN,201) IEFLG
FORMAT (T2, 'ERROR COND EXISTS - ABORT ',12)
GO TO 100
CONTINUE
!:::LM='.J!::;:*RTM
RE""-O.OO
IF (REe. LT. RZER) GO TO 208
RE==REC
/
GO TO ZO',I
CONTINUE
IF (IMM. EQ. 21 RE=RECI
IF (IMM. EQ. 3) RE=REC2
RW""RWD+RE
CONTINUE
. . . . . .. N(~ME CHANGE!::;; FOR SPEED REASON . ' S

0260
0261
0262
026::::
0264
0265

0266
02t:.7
0269

0270
0271
0272
0273
0274·
0275

0276
0277
027:::
0279

1 "'f;:~J 1

RWZ"-'RW-2. 0
E!fJZ=Rv,12
, . ,. SOFT ERROR ALGORITHM BY CYCLE TIMES ....
SMCYL"'Rlvj!:::Z
SMTIM=SMCYL*TMCYL
SRCYL=SMTIM/TRCYL
SRPG~(EPG*EBD)~l.

SECYL=CSMTIM+(SMTIM*SRPG)/(SMCYL+(SRCYL*SRPG»
SNRMLZ=TREF/SECYL
RZDD=(RX1A*RZSE*SNRMLZ)~(RX1B*RZSE)

IF (JXFG. NE. Z) RZDD=RZSE
RZDX"'RZD+RZDD
RX Z'''RZDO/RZDX

RXF'=RXR+RXC
RRS Z' 'RI'1!:::: Z/RCS Z
RFSZ=(RCSZ+RRSZ)/2.0
RESl=RMSZ/CRCSZ+RRSZ)
RH::::;Z"'Z.O
RT!3Z''''1. 0
Eez=1. 0
ECS=l. 0
ECR''''RR!:::;Z

3-149

AP-73
-FORTRAN IV
02:30
0281

0282
02:3:3
0284
0285
02::::e,
0287
0289

,)290
0291
02'5"2
029:3
0294

0295
0296
'0297
0298

0:300
0301

0:302
0:30::::
0:304
0:305

0306

0:307
0:309

V02. 04

ECC=RCSZ
ECF=RFSZ
ECE=(RRSZ+RCSZ)/RRSZ
ECH=RMSZ/(CRRSZ+RCSZ)*2.0)
ECT=2. 0
T=RZER
S=RZER
RINC=RTM/RTSF
RMTBF=RZER
RMTTF=RZER
RMNT=RZER
LG=l
IMFU3=1
ISFLG=l
,JSFLG=l
IXFLCi=1
ILFLCi=l
RM I L= 1000000.
r F (RTM. (iE. 100000. 0) I MFL(i=2
RZZ=(RXZ*RZDX)/RMSZ
RZS=~RXS*RZD)/RMSZ

RZR=(RXR*RZD)/RRSZ
RZC=(RXC*RZD)/RCSZ
RZF=(RXF*RZDI/RFSZ
RZE=(RXE*RZD)/RESZ
RZH=(RXH*RZD)/RHSZ,
, RZT=(RXT*RZD)
RHRD=l. O-RXZ
RTMP=(RXS/RMSZ)+CRXF/RFSZ1+(RXE/RESZ1+(RXH/RHSZ)+(RXTIRTSZl

0310

RAVE=RXZ+C(RTM~*RMSZ)*RHRD)+RFF

0:311
0312

,AZ=RXZ
AS=RHRD*RXS
AF=RHRD*RXF*(RMSZ/RFSZ)
AE=RHRD*RXE*IRMSZ/RESZ)'
AH=RHRD*RXH*(RMSZ/RHSZl
AT=RHRD*RXT*CRMSZ/RTSZ)
AXX=AS+AF+AE+AH+AT
8Z=(AZ/(AZ+AXX)I*R
8HRD=100. 00-8Z
BS=(A:::;/AXX )*R
BF=(AFfAXXI*R
BE=(AE.fAXX)*R
BH=(AH/AXX)*R
BT=UH/AXX I*R

031.3
0:314

0:315
0:316
031.7

0:318
0319
0:320
0:321

0322
0323

0::::24
0325

~ZDZ=RZDX*CRAVE/RMSZ)

0:?26
0:327,

ECA=RM8Z/RAVE
RZF:E:V'=O. (I
RZTOL=O.'O
RTPM=RTM/IPM
ROLD=l. 0
I SFLG'''' 1
Rn:;ED=RTTF
RSPC1~~1. 0
RSPC2=2. (>

EPX=CCRMSZ-RPSZI/RMSZI*EPG
EPY=CRPSZ/RMSZI*EPG
EPZ=O. 0
IF (RPSZ. LE. RMSZI GO TO 211
EP=(RPSZ-RMSZ)/RMSZ

0335
0:3:36
0337
0338
0340
0341
0342
0:343
0344
0346
0347
0348
03.49
0350
0351
0352
0354·
0355
0357·
0358

EPZ=EP~~EPG

211

EPY=(l.O-EP)*EPG
EPX''''O. ()
IF (~PSZ~LE. 2. O*RMSZ) GO TO 211
EPX=O. 0
EPY==O. (I
EPZ'-=(I. (I
CONTINUE
EPSZ=RP8Z
RZTMP=O. 0
IF! (RTTF. NE. RZERI. OR. (IMM. EI;t 1»

RZTMP=RWD*EPG*~BD*«RZD*SXX)+RZDD)

0367
0368
0370
0372
0373
0374
0375
0377
0378.

214

216
217

038i~

0381'
0382
0384
0385
0386
0387
0389

218
219

GO TO 212

IF CRZTMP. GT. O. 0) RTSED=1000. O/RZTMP
CONTINUE
RZTTL=O. 0
RZSYS=O. 0
RTMSO=O. 0
GO TO (ZI3,214,214),JXFG
NORMAL TTL SYSTEM CALCULATION..... .
RZTTL=RZTTX
RZSYS=RZSYX
IF (RZSY& GT. O. 0) RTMSO=100Q O/RZSYS
GO TO 216
MSO MODE RTMSO CALCULATION FOR HEADER O!'lLY
RZTMP=(E8D-RZTTXI+RZSYX
. IF (RZTM~ GT. O. 0) RTMSO=1000. O/RZTMP
IF (JXFa LT. 3) GO TO 216
RZSYS=RZTMP
CONTINUE
IMN=l
IF (RPSZ. GT. RZERI IMN=2
CONTINUE
IF « II I. Er). 0). OR. (I MM. EC.!. 0» GO TO 220
T=III*RINC
S==T
IF CJ& EQ. 0) GO TO 395
GO TO (218,219), ISFG
S=.JS*RINC
GO TO 395
IF (RTSF. GT. o. 01 S=SLM/RTSF
GO TO 395

C
C################################################################=1++1=####

C
C

.
PRINT HEAPER

C
C##############################################~########################

0390
0:391

:220
221

WRITE (ILP, 221) (IBUF ( 18 I, 18=1,72)
F.ORMAT "', Fb. '0, 'CELLS/PG",
0·'·05
r' T45. "'Rr~TE -) "', FlO. b • ..,~/. / 1000 HRS"', /. T2. "SOFT ERRORS: ", Tlb,·
C'" "*" .... T20. "'MAINT -) "', FlO. 0, '··HRS •..' i T45. "'RATE -) ", FlO. b,
r 'X / 1.000 HRS'./.T2. 'ANALYSIS DATA: '.T20, 'PERIOD:-) ~,Fl0. 2,
r ~HRS. '.T45. 'AVE CELL FAILURE -)'.F& 1)
040e.
f<'" 100
0407
WRITE (ILP. 11)
FORMAT I 'f2. "'FAILURE TYPE RATIOS:
"', 5( ... -------'--- ... ), j, T2,
0408
11.
C '=TVPE=',T14, '=DISTRIBUTION=GEOMETRY=UNIT. RATE/lK HRS=',
C 'AVE. CELLS=ECC. DISTR~EXPS=')
0409
WRITE (ILP. 12) RXZ*R.RMSZ.RZZ*R.AZ.BZ,RHRD*R,BHRD.RXS*R,
C RMSZ. RZS*R,AS, BS.ECS, RXF*R. RFSZ. RZF*R.AF,BF.ECF
FORMAT (T3. 'SOFT ERROR -)(~.F7. 3;'X]/',F7. 0,' = '.E12. 5, 'X,',
041.0
12
C Fil. 3.2X, '['.F6. 2. 'Xl',/,T3. 'HARD ERRORS -)[',F7. 3. 'Xl'.
r-' T65, . . [ . " Fe.. 2, "'X]"', /,
r T3, 'SINGLE CELL -)',FS. 4. 'X /'.F7. 0, ~ ~ ',EI2. 5, 'X, 'Fll. 3,2X,
r F6. 2, 'X~.2X,F4. O,/,T3, 'ROW OR COL -)',F8.·4, 'X /',F7. 0,' = 'i
C E12. 5. ···~/;, "', Fll.. ::::, lX, F6. 2. "'~/;"', lX, F4. 0)
041.1.
WRITE (ILP,17) RXE*R.RESZ.RZE*R.AE.BE.ECE,RXH*R.RHSZ.RZH*R,
C AH.BH.ECH.RXT*R.RTSZ.RZT*R.AT,BT,ECT .
0412
17
FORMAT (T3. ~COLUMN/Row -)'.FS. 4. 'X /',F? 0.' = "
C E12. !5 • ..,:'1;. "', Fl1. :3. 2X, Fb. 2, ":/.", 2X. FA. O. /, T:3, "'HALF CHIP
-)""
C F:::::.
"':1; /".1 F7. O•..' ,= :' ,-EI2. 5 • ..,:'1;. ···Fl1.. :3, 2X. F6. -1, ,":'1;', 2X, F4. 0, /,
C T3. 'TOTAL CHIP -)'.F8. 4. 'X /'.F? 0,' = ',EI2. 5, 'X.',
C Fl. J.. 3, 2X. Fl.:.. 2. ,":'1;". 2X. F4. 0, / l
01l·1=:3
IF (lMM. NE. 0) GO TO 390
0415
IIJRIlE (IL.P. :380)
380 FORMAT (lHl,t2,81'--------'»
0416
0417
GO TO 100
041.8
3';'0 CONT:I: NUE
II

II."

,r.

c.$SSSSSSS$$$$$ ••••••••••••• $$ •••• $ •••••••• $ •••••••••• $$$ •••••• $ ••• $~

3-152

AP-73
V02. 04

FOHTHAN IV

EC!UA T I ON L.OOP .
041.9
0420

WRITE (ILP, 14) LPTRCIMM+l0).LHCIMFLGI
FORMAT ITZ, 'PERIOD',Tll, 'PM@T: '.T24. 'RETJ. '.A4.T44, 'MTTF',
C T~~, 'ENHANCEMENT .T65;'% - RCT)',I.T2. ·---~-·.T8.
C '<',A2.' ~RS>',T23, '=FUNCTION=',T42.'< HRS >',T52 •.
C···. FACTOR. ···,"1'65.···.
@T. ")
I=O
j

04·21.
0422
0423
0424
0425
0426

395
400

TSFT~S

THRD=T
CONTINUE
,-'8=1
RENH=RZER

C########I####I####################################### #################

RELIABILITY EQUATIONS

C
C######ttlt#1i:'it1!"it####'it############################# ########################
1-'

OUTPUT DATA

C
C##:ft#i*##It.#lt#'If############i*####################### #######################

0428
0429
0431
0432
04:3:3
0434·
04:35
0436
0437
04:3';"1
04-4I
0442
.0444
0445
0447
0448
0449
0450
0451
6452
0454
0455
0456
0458
0460
0462

500

CONTINUE
IF (III. EQ.O) GO TO 510
WRITE CITOUT;502) L.PTRCIMM+I0). I, T*RTSF.RTPG
502 FORMAT el2, "'*i~ ". A4. 5X. " 1·=> ", 14, 5X. ···T=>. ,.~ FlO. 2. lOX.
C 'R => '.FI0. 7)
GO TO 10'0
510 IZFLG=O'
~TIM=T*RTSF

51'7
520
522

RTMX=-RTIM
IF CIMFLG. EQ. 2) RTMX=RTIM/RMIL
IF CI. EQ. 0) GO TO 522
RINT=CCROLD+RTPG)/2.0)*RTM
IF CISFLG. EQ. 2) RINT=RZER
RMTTF=RMTTF+RINT
IF (1. O-RTPQ LE. SZER) GO TO 517
RMNT=RMTTF/Cl.0-RTPG)
GO TO 520
IZFLG=2
ROLD=RTPG
CONTI NUE
IF « RTPG. LE. RCNF). AND. (LG. EQ. 1» ,-'G=2
KLI=KL(IXFG)
.
IFLG=O
IF CC(I1ISW)*ISW. NE. II. OR. (I. LT.ILLM» IFLG=l
IF (r. GT. IULM) IFLG=1
IF CI. EQ. ruCD) I FLG=O
RI=I
, I
I

0463
04640466
0467
0468
0469'
0471
0473
0474
0475

525

531
5,05

0476
0477
0478
04,79
04:30
0482

532
506
535
550
C

VO,2.04
IF H. EQ. 0) GO TO 525
IF (RTPG. LE. 0, 0)130 TO 525
RZREV=(DLOG(I. b/RTPG»/T
RZTOL=«R~TOL*(RI-l. O»+RZREV)/RI
CONTINUE
~F « 1. NE. 0), AND. (IFLG. EQ. 1»
GO TO 550
Li=LUJG)
L2=LR(JG)
RCFD=RTPG*lOO. 00
IF' , (RTSED. GE. 1. 0) RENH=RMNT /RTSED
IF « I SFLG+JSFL.G. EQ: 3), AND, (I LFG. EQ. 1» GO TO 535
GO TO, (531, 532), IMFLG
WRITE (ILP, 5(5) L RTMX, I
0520

AP-73
V02. 04
IXFG=-::::
T=T+RINC
1=1+1
GO TO (574.576). IXFLG
:::;''':3+R I NC
130 TO 578
S="RZER
IXFLG='i
CONTINUE
THRD=T
. T:::;FT''''S
IF (SL~ EQ. RZER) GO TO 580
TSFT~R1+(SLM/iOOO. )
IF (S. GE. (SLM/RTSF»
IXFLG=2
IF (IXFLG. EO. 2) IXFG=4
CONTI NUE

C
END EQUATION LOOP
C$$$$SS$$SS$S$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$"$$$$S$$SIS$SSS$S$$$$$$$$$
r'

i)5:30
05:31
05:;:2

5:35
1-'

05:3:3
0534
05:36
0537

590
1-'

05:38

0540
0541
0542
0543,
0544
0546
0547
0549
0550
0551
0552

660

595
600
c,50

IFLG=O
GO TO (585.590), IDFLG
CONTINUE
ITERATE TILL LIST COUNT ....
I FLG:-:. 1
IF « 1. GT. IULM). OR. (RTP('. LE. Rf~LMT» GO TO 650
GO TO 400
CONTINUE
ITERATE TILL R(T) BELOW LIMIT
IF «LG. EG!. 11. OR. (ILFLG. EG!. 2» GO TO 660
ACCELERATE FAILURE RATE ....
RINC=RINC-!~ IDBI<
ILFLG==2
CONTINUE
IFLG=2
IF (RTPa LE. RALMTI GO TO 650
IFLG=:3
IF (1. LT. IULM*IC::HI GO TO 400
WR ITE (I LP, 595 I
FORMAT (T2, ~****'I
CONTINUE
CONT I NUE

0553
0554
0556

RENH=O. 0
IF (RTPG.GT. RALMTI WRITE (ILP,5951
IF (RTSED. GT. 1. 01 RENH=RMTTF/RTSED
C

C########################################################################
C
C
THIS IS IT .....
SYSTEM MTBF
C

0558
0559

C###########################################W###########################
WR ITE (I LP, (75) 1. RTMX, RTPG, RMTTF, RENH

675

FORMAT (T38, '=MEMORY MTBF='.4X. '=EF='.I.T2. I4.T7.Fln 2.

inter

Ap·73

FORTR(.\N IV

V02. 04
C T24.F8. 5. T40.F12. 2.T52 •• F8.

0.I.T~.8(/-~------/I./1

0560
0:::;/:.1
0562

RZTOL=1000. IRMTTF
GO TO (67,::.• 6Tl.6781 •.JXFO
RZTMP=RZTOL+RZSYS
RTSYS=1000. O/RZTMP

0567
0568
0569
0570
0571
0573
0574

RZTMP=RZTOL+RZSYX+(EBD*RZTTXI
RTSYS=1000. O/RZTMP
GO TO 679
RTSYS=RMTTF
RZTMP=O. 0
CONTINUE
IF CRTSED. GT. O. 0) RENH=RTSYS/RTSED
WRITE (ILP.6801 IFLG.RTSYS.REN~RZTMP
FORMAT (T2. 'FIN'. lX. 13.T24. '=SYSTEM MTBF='.T40.F12. 2.T52.F8. O.

FORTRAN lV
0001.
0002
0003

V02. 1-1
REAL FUNCTION DRTI*8(RZX.RTM.EL.RTI
IMPLICIT REAL*8 (RI
DATA Rl/l. 0001

C#######################I###########.#.############################.###

c
C

RSCTI FUNCTION

C
C##I####II#.#######.## •• ###.####.### •• ##########.#######################

0004
0005
0006

DRTI=(Rl/DEXPCRZX*RTII*(RTM**El).
RETURN
END

FORTRt\N IV
0001
0002
0003

V02. 1-1
REAL FUNCTION DRTO*8CRZX.RXI.RXO.RN.El.RTI
IMPLICIT REAl*8 (Rl
DATAR1/1. 0001

C######I##########################I##I####################1#1##########

c
c

BINOMIAL EQUATION FUNCTION

C
C##II#############I#I########## •• #.####.###.######.###11###1##11########

0004
0005
0006
'0007
000::::

0009
0010
001.1
0012
001.::':

EN=RN.
EN1='RN-Rl
RR=Rl/DEXPCRZX*RTI
RXN:",RR**EN
RC!X:::::Rl-RR
RTRM1=RXN*(RXO**ELI
RTRM2=RN*RQX*CRXI**EN11
DRTO=RTRM1+RTRM2
RETURN
END

3-156

inter

AP-73

FORTRAN IV
0001
0002
0003

V02. 1-1
~

REAL FUNCTION DRTX*8(RZX.RXI.Rl0.R20.RN.EL.RTI
IMPLICIT REAL*8 (Rl
DATA Rt/l. ODO/.R2/2. 0001

C##########I########################################## ###################
C

BINOMIAL EQUATION FUNCTION FOR DOUBLE BIT CORRECTION

C
C########1t#######,,*################################## ######################

0004
0005
01)06
0007
0008
000'7
0010

0011
0012
001:~:

0014

0015
0016
0017
0018

EN=RN
.
RN1=::RN-Rl
EN1=RNl
RN2=RN-R2
EN2=RN2
E2=R2
RR=Rl/0EXPCRZX*RTI
RXN=RR**EN
RGlX=Rl-RR
RTRM1=RXN*CR20**ELI
RTRM2=RN*RGlX*(RR**ENll*(Rl0**ELI
RTRM3=(RN*RN1*CRGlX**E21*CRXI**EN2il*0.50
DRTX=RTRM1+RTRM2+RTRM3
RETURN
END

SUBROUTINE TEST( IMM)

0001
C

C#######################################################################4
C

C
C
C
C

EQUATIONS FOR:
NON ERROR CORREtTED SYSTEM
SINGLE' BIT CORRECTED SYSTEM
DOUBLE BIT CORRECTED SYSTEM
USE OF PARTIALS IN A SYSTEM

C#######################################################################
0002
IMPLICIT REAL*8 (D,R,S,T,Z)
C
0003
COMMON IECC1/RXZ, RXS, RXR,RXC, RXF, RXE, RXH, RXT, RCNF, SZER, SXX
0004
COMMON IECC2/RMSZ, RCSZ, RWD,BPG,RZD, RZDD, REC, RZER, Rl, RTM.RTSF
0005
COMMO~ IECC3/IM. ILLM. IULM, RSQ. JSFLG. EPGX. ISFLGiST,R.RTH.R2
0006
COMMON IECC4/ISW,RFF. IPM.RTTF.RZTTL. ICST.RALMT. IDBK. IQFG. IUCD
0007
C.)MMON IECC5/ISFG. RECl. REC2. IEFLG. RZSYS. IUM. IDFU3. RAVE
0008'
COMMON IECC6/ IT IN. ITOUT. I LP
0009
COMMON IECC7/RZZ.RZS. RZR. RZC, RZF. RZE. RZH. RZT.RZDX
0010
COMMON IECC8/ECZ.ECS. ECR. ECC. ECF. ECE, ECH. ECT. ECX
0011
COMMON /ECC9/EW. EW1. EW2. RW. RW1. RW2. S. T, tSFT, THRD
0012
COMMON IECCA/EPG,EBD. EPSZ. ECA. EPX. EPY, EPZ
0013
COMMON IECCB/ZT,ZR,ZF,ZE,EZL
0014
COMMON IECCC/LIMN. RPRT. RTO, RTPG. RTX. RZDZ. RXX. RSPC1. RSPC2
C
0015
GO TO ,(410.420.430). IMM
C
0016 ,410 CONTINIJE
######## SINGLE ERROR DETECT EQUATIONS ########
C
C
0017·
RIO- ( 1. O/DEXP (RZDD*S) ) **EW
0018
RXO=(1.0/DEXP(SXX*RZD*THRD»**EW
RYO=Cl.0/DEXP(RZTTL*THRD»**EW
0019·
C
0020
RTO=(RZO~RYO*RXO)**EPG
0021
RXO=(1.0/DEXP(RZTTL*THRD»*.EBD
0022
RTSYS=Cl.0/DEXP(RZSYS*THRD»
0023
RTPG=(CRTO*RXO)**EBD)*RTSYS
0024
GO TO 500
C
0025
420 CONTINUE
####### SINGLE BIT ERROR CORRECTION EG!UATIONS #####
C
C
0026
RZI=DRTI(RZZ. Rl.ECZ. TSFT)
0027
RZO=DRTOCR~Z.RZI.Rl.RW.ECZ~TSFT)
C
,0028
RSI=DRTICRZS.RZI.ECS.THRD)
0029
RSO=DRTOCRZS. RSI. RZOiRW. ECS. THRD)
C
.
0030
RFI=DRTICRZF.RSI.ECF.THRD)
0031
RFO~DRTO CRZF. RFI. RSO. RW. ECF. TH~D)
C
0032
REI=DRTICRZE.RFI.ECE.THRD)
I

V02. 1-1
REO==DRTOCRZE, REI, RFO, RW, ECE, THRD)

00:~::3

RHI=DRTICRZH,REI,ECH,THRO)
RHO=DRTOCRZH.RHI,REO, RW,ECH,THRD)

00:=:4
OO:~:5
(.

RTI=ORTI(RZT,RHI,ECT,THRO)
RTO=DRTOCRZT,RTI, RHO. RW,ECT,THRO)

00:36
00:37

C
RXI=DRTICRZTTL,RTO, EPG,THRO)
RXO=DRTOCRZTTL.RXI,RTO. RW, EPG,THRD)

003:::::
OO:3'~1
1-'

RTSYS=l. O/DEXPCRZSYS*THRD)

0040

0041
(.

0042
00/1.:3
004'l
004·5

0050
OO!:i2
OO~5:3
005~5

GO nJ (425,422,/1.22), IQFG
. . .. SPECIAL EQUATION FOR 2-D EFFECTS
RQR=l. O-Cl. O/DEXPCRXR*RZD*THRD*EW»
RQC=1. 0-(1. O/DEXPCRXC*R~D*THRD*EW»
RQF=1. 0-(1. O/DEXPCRXF*RZD*THRD*EW»
RQE=1. 0-(1. O/DEXPCRXE*RZD*THRD*EW)
GO TO (425.424.42:3). IQFG
RSPC1=(Cl. Q-(RQR*RQC»*C1. O-CRQF*RQE»)**EPG
GO TO 425
SC!X=RG!R
IF (RG!C. LT. RQR) SC!X=RG!C
::::;G!Z='RG!F
IF (RG!E. LT. RG!F) SC!Z==RC!E
RSPC1=«1. 0-SQX)*'1. O-SQZ)**EPG

0056

42~f

RTPG=«RXO*RSPC1J**EBD)*RTSYS

r'
09!~i7
1-'
i~2:::::

005:=:
OO~39

GO TO C500.428). IMN
. . .. EC!UATIONS FOR USE OF PARTIALS
RPRTO=C1.0/0EXP(RW1*RZDX*THRO»)**EPY
RTPX=CRXO*RSPCI)**EPX

RTPG=CCRTPX*RPRTO)**EBD)*RTSYS
GO TO 500

DOUBLE BIT ERROR CORRECTION EC!Uii-nONS

RZI=DR1ICRZZ.Rl.ECZ.TSFT)
RZO=DRTO(RZZ.RZI.Rl.RW1.ECZ.TSFT)

006:3
0064
OO'~1!5

RZX~DRTXCRZZ.RZI.Rl.Rl,ECZ.TSFT)

aSI=DRTICRZS,RZI.ECS.THRO)

0066
001.:.7
006::;:

RSO=DRTOCRlS~RSI.RZO.RW1.ECS.THRO)

RSX=DRTX(RZS, RSI. RlO. RZX.RW.ECS. THRD)
C

RFI=DRTICRZF.RSI.ECF.THRO)
RFO=DRTOCRZF. RFI. RSO, RW1.ECF. THRD)
RFX=DRTXCRZF. RFI. RSO. RSX. RW. ECF. THRD)

0069
0070
0071
C

0072

REI=DRTICRZE.RFI.ECE.THRD~

3·159

######

intJ
FORTRAN IV

AP-73
V02. 1-1
REO=DRTO( RZE, RE 1. RFO, RW 1.. ECE, THRD)
REX=DRTX(RZE, REI, RFO, RFX, RW. ECE, THRD)

0073
0074
C

RHI=DRTI(RZH,REI, ECH, THRD)
RHO=DRTO(RZH. RHI. REO. RW1. ECH. THRD)
RHX=bRTX(RZH. RHI, REO, REX, RW,ECH. THRD)

0075
0071:0077
0078
0079
0080

RTI =DRTI (RZT, RH I. ECT. THRD)
RTO=DRTO(RZT. RTI, RHO, RW1. ECT. THRD)
RTX=DRTX(RZT.RTI, RHO. RHX. RW. ECT. THRD)

C
0081
0082
0083

RXI=DRTI(RZTTL.RTI.EPG,THRD)

RXO=DRTO(RZTTL,~XI,RtO.RW1,EPG,THRD.

RXX=DRTX(RZTTL,RXI,RTO,RTX,RW,EPG,THRD)
C

0084
0085 "
0086
0087
0088
0089
0090
0091
0092
0093
0094
0095
,0096
0097
0098
0100
, 0101
0103
0104
0105
0106
0107
0108
0109
0110
0111
0112
0"113
0114
0115
0116
0117
0118

RTSYS==RllDEXP(RZSYS*THRD)
C
C
431

432
433

C
434
C
435
436

437
-438
439

GO TO (434,431,431), IQFG
. . .. SPECIAL EQUATION FOR 2-D EFFECTS
RTP=DRTI (RZR, Rl, Rl, THRD)
f
_
RQR=I.0-DRTOCRZR,RTP,Rl,RW1,Rl,THRD)
RTP=DRTI(RiC;Rl,Rl,THRD)
,
RQC=1.0-DRTO(RZC,RTP,Rl,RW1,Rl,THRD)
RTP=DRTI(RZF.Rl,Rl,THRD)
RQF=1. O-DRTO(RZF, RTP, R1. RW1. Rl,'THRD)
RTP=DRTI(RZE.Rl.Rl,THRD)·
RQE=I.0-DRTOCRZE,RTP.Rl.RW1.Rl.THRD)
GO TO (434,433.432), IQFG
RSPC2=«I. O-(RQR*RQC»*(l. O-(RQF*RQE»)**EPG
GO TO 434
SQX=RQR
IF eRQC. LT. RQR) SQX=RQC
SQZ=RQF
IF (RQE. LT. RQF) SQZ=RQE
R~PC2=«1. 0-SQX)*(1.0-SQZ»**EPG
RTPG=(CRXX*RSPC2)**EBD)*RTSYS
GO TO (500.435). IMN
..... EQUATIONS FOR USE OF PARTIALS
CONTINUE"
GO TO (439.436.436), IQFG
RQR=l. 0-(1. OlDEXP(RXR*RZD*THRD*EW»
RQC=1. 0-( 1: O/OEXP(RXC*RZD*THRO*EW»
RQF=1.0-( 1. O/DEXP(RXF*RZD*THRD*EW»
RQE=1.0";'( 1. O/DEXP(RXE*RZD*THRD*EW»
GO TO (439.438.437). IQFG
RSPCl == ( ( 1. 0- (RQR*RQC) ) * ( 1. 0- CRQF*RQE) ) ) **EPG
GO TO 439
RSPC1=«1. O-SQX)*(l. O-SQZ»**EPG
RPRTO=(1.0/DEXP(RW2*RZOX*THRD»**EPZ
RPRT 1= ( RTO*RSPC 1 ) **EPY RPRT2=(RTX*RSPC2)**EPX

C
0119

RTPG==«RPRTO*RPRT1*RPRT2)**EBO)*RTSYS

0122
500
012:3
0124
FORTRAN IV
0001 '.
0002
000:3
0004·

0011
0012
001:3
0014
0015
0016

CONTINUE
FUTURE TESTS HERE
CONTINUE
RETURN
END
V02. 1-1
SUBROUTINE HELP
COMMON /ECe6/ITIN, ITOUT, ILP
WRITE (ITOUT,20)
FORMAT (/,Tl0,2("'********"'),2X, /HELP TEXT /,2(/********~),.1.1
C ,T2, ~. PRAMETER. .. RANGE ................ COMMENTS. , , ... ~, /;
e T15, ~NECC - NON ECC EVALUATION RUN. ',/,T15, 'SECC - SINGLE',
C··' BIT ERROR CORRECTI ON RUN. /, f, T15, ' DECe - DOUBLE BIT ERROR'
C··' ERROR CORRECTION RUN. /)
WRITE (ITOUT,25)
FORMAT (T2, .J'INDEX: '·/T12/4( ..· ........ "'),T50,"'.-'

C ,/,TI8,'0 - ~PEeIFIES FULL-OUTPUT NORMAL RUN. ',/,T17, '>0 -',
C "SPECIFIES SINGLE POINT CALCULATION OF R-FUNCTION @ F, /,
C T22, /WHERE T == INDEX * TIME,
PURPOSE IS TO ASSIST USER/,f,
C 1'22, "'DET'ERMINE BEST TIME INTERVAL FOR RUNS, ~)
WRITE (lTOUT.:30)
FORMAT (ll. 'TIME: /,TI2.4(/ ........ ').T50, '(DATA TYPE FLOATING',
e·" PT, Y. /, T16, ">0. - :::;PECIFIES INTERVAL OF TIME BETWEEN RUN-~,
C 'TIME',/.T22, 'EVALUATION POINTS')
WRITE (lTOUT,:35)
FORMAT ('f2,'PAGE: '·,T12,4(~ ........ '),T50, '-(DATA TYPE INTEGER:>",
C /,T17, ':>1 - NUMBER OF MEMORY ROWS PER BOARn ',.I.
C T2, 'BOARDS: ',T12,4(', ....... '),T50, '-(DATA TYPE INTEGER:>',/,
C T17, " > 1 - NUMBER OF BOARDS PER MEMORY SYSTEM. " .I)
WRITE (ITOUT.40)
FORMAT ('f20, " ** HIT -(RETURN> TO CONTINUE**')
READ (ITIN,45) IDUM
~,
FORMAT (AZ)
WRITE (ITOUT,50)
FORMAT (//, TZO, " # ADDITIONAL POINTER PARAMETERS #', .I .I,
e T2,"'POINTER: '·,TI2.4(' ........ /),T50, "',/,
LIST OUTPUT PARAMETERS, ',.I,
C T15, 'LIST
C T15, 'SIZE
MEMORY COMPONENT & SYSTEM PARAMETERS, /,.1,
C T15, "RATE
COMPONENT f& SYSTEM FAILURE RATES. ", /.
C T15, "D,IST
COMPONENT' FA I LURE";"TYPE DISTRIBUTION. " .I,
C T15. "COMM
OUTPUT RUN-TIME COMMENT LINE')
WRITE (ITOUT.55)
FORMAT (T15/'ABORT - EXIT PROORAM. './.
C T15. /DUMP
DISPLAY < LIST~ SIZE. RATE. DIST, COMM >-./,
C T15. /PURGE - PRINT REST OF RUN-TIME OUTPUT BUFFER~,f/,
c' T15, "FLAG
USE OF TTL & SYSTEM FAILURE RATES, GI-FLAG~, /,
'C T22. 'SYS == TTL @ BOARD LEVEL, SYSTEM USED WITH MEMORY/,/,
C T22. "MPD == TTL N. U., SYSTEM RATE LISTED', IN HEADER ONLY', /,
C T28, 'SOFT ERRQR RATE SPECIAL MPD ALGORITHM- MEM CYCLES',/,
C· T22, .' MSO
(TTL X BOARDS) + SYSTEM COMB I NED WITH MEMORY ~ , /,
C T22, "Gll == ONE DIMENSIONAL ARRAY MODEV, /,
I C T22, "Gl2
SAME AS, GIL PLUS SPECIAL TWO DIMENSIONAL FIX', /,
C Tl0,5(/********/),///)
RETURN
END
END OF PROGRAM
3-161,

, AP-73 '
SYS /Ql

ECC PROBABILITY PROGRAM

INTEl..:-MPD/MC.

II'

MEMORY SYS:SIZE-::>
32. OKB
WORD WIDTH-::> 16. + 6: NO. PAGES-::>
1. X 1.
6.
RAM SIZE-::>
16384. COL SIZE-::> 128.
COMPONENT: TOTAL-::>
16. +
SYSTEM DATA:
TTL RATE -::> O. OOOOO:Y./IK"':HRS, SYSTEM RATE -::> O. 00000/./1K-HRS
FAILURE DATA:
MTBF. NECC -::>
49212. 60HRS, MTBF. SYS -::>
O. OOHRS .
HARD ERRORS:
PARTIAL -::>
0; CELLS/PG RATE -::>
O. 027000:Y. / 1000 HRS
SOFT ERRORS:
"*" MAINT ->
O. HRS, RATE -::>' O. 100000:Y. / 1000 HRS
ANALYSIS DATA:
PERIOD -::> 100000. OOHRS, AVE CELL FAILURE -::>
16. 2
FAILURE TYPE RATIOS:
-------------------------------------------------=TYPE=
=DISTRIBUTION=GEOMETRY=UNIT. RATE/IK HRS=AVE. CELLS=ECC. DISTR=EXPS=
SOFT ERROR -::>[ 78. 740:Y.]/ 16384. = o. 61035E-05:Y.,
O. 787 [ 4. 8n]
HARD ERRORS -:-,. [ 21. 260:Y.]
'.
[95. 13:Y.]
1.
SINGLE CELL -::> 50. 0000r. / 16384:
O. 82397E-06:Y.,
O. 106
O. 69:Y.
ROW OR COL -::> 43.7000r. I
128. = 0.92180E-04:Y.,
11.892
77.36r. 128.
2:
COLUMN/ROW -::> 6. 2000r. /
64.
o. 26156E-04/~,
:3. 374
21. .95:r.
32.
HALF CHIP
-::> o. OOOO~I. /
2.
o. OOCJOOE+OO/;,
o. 000
O. OO/~
2.
TOTAL CHIP -::> O. 0000r. /
1. = o. OOOOOE+OO/~,
O. 000
O. OO/~
PERIOD
0
1

2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23

24
25
26
27
28

29
30

PM(H:

O. 00
O. 10
O. 20
o. 30
O. 40
O. 50
O. 60
O. 70
O. 80
O. ';10
1. 00
1. 10
1. 20
1. 30
1. 40
1. 50
1. 60
1. 70
1. 80
1. 90
2. 00
2. 10
2. 20
2. :30
L . 40
2. 50
2. 60
2. 70
2. 80
2. 90
3. 00

R[TJ. SECC
=FUNCTION=
I. 00000
O. 91~332
O. 97:389
O. 94293
O. 90200
O. 85289
O. 79748
O. 73770
O. 675:37
O. 61217
O. 54·958
O. 48884
O. 43095
O. 37c.66
O. 32650
O. 28075
O. 23956
O. 20290
O. 17062
O. 14248
O. 11819
O. 09741
O. 07979
O. 06496
O. 05258
O. 04232
O. 03:388
O. 026';18
O. 021:37
O. 01685
O. 01:322

7584078.
5149121.
:3939900.
:3221005.
274732:3.
2413E:25.
2168007.
1980705.
18:34422.
1718017.
1624061.
1547397.
1484:334.
14:32149.
1388787.

ENHANCEMENT
FACTOR
O.
303.
154.
105.
80.
65.
56.
49.
44.
40 ..
:37.
:35.

1297395.

33.
31.
:30.
'-,c,
.,:;., .
28.
27.
27.
26.

12764:~:7.

26.

125899:3.
1244505.
12:32508.
1222606.
12144c.3.
1207796.

26.
25.
25.
25.
25.
25.
24·.
24.
24.
24.

1352605.
1322533.

1202:358.

1197945.
1194:379.
1191512.
=MEMORY MTBF=
1175755. :35

R
4. 1MB
WORD WIDTH"'">
1·6. + t;,.. NO. PAGES->
1. X 128.
COMPONENT: TOTAL-> 2048. +
768.
RAM SIZE->
,16884. COl: SIZE-> 128.
SYSTEM DATA:
TTL RATE -> o. 00000/~/1K-HRS,
SYSTEM RATE -> O.OOOOOI./lK-HRS
FAILURE DATA:
MTBF. NECC ->
384. 47HRS, MTBF. SYS ->
O. OOHRS
HARD ERRORS:
PARTIAL ->
O. CELLS/PG RATE ->
O. 0270001. I 1000 HRS
SOFT ERRORS:
U*U
MAINT ->
O. HRS, RATE ->
,0. 1000001. I 1000 HRS
ANALYSIS DATA:
PERIOD ->
8000. OOHRS, AVE CELL FAILURE ->
16. 2
FAILURE TYPE RATIOS:
------------------------~----------------------~-=TYP.E~
=DISTRIBUT ION=GEOMETRY=UN IT. RATE/1K HRS=AVE. CELLS=ECC. DISTR=EXPS=
SOFT ERROR ->1: 78. 740l.JI 16384. = O. 61035E-051.,
O. 787 I:
4. 871.] ,
HARD ERRORS ->1: 21. 2601.]
I: 95. 131.]
SINGLE CELL -> 50.00001. I 16384. = O. 82397E-0~.I.,
o. 10~.
0.691.
1.
ROW OR COL -> 43. 70001. I
128. = o. 92180E-041.,
11. 892
77. 361.
128.
COLUMN/ROW -> 6. 20001. I
64. = o. 26i56E-04/~,
3. 3'74
21. 951.
2.
HALF CHIP
-> O. 00001. I
2. =, O. OOOOOE+OOI.,
O. 000
o. 001.
32.
TOTAL CHIP -> O. 0000:1. /
1. = O. OOOOOE+OOI.,
O. 000
O. 001.
2.
PM@T:
HRS>
O.
8000.
,16000.
24000.
,32000.
40000.
48000.
56000.
64000.
72000.
80000.
88000.
96000.
104000.
112000.
120000.
128000.
,136000:
144000.
152000.
160000.
168000.
176000.

PERIOD

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
,30
31

~184000.

192000.
200000.
208000.
216000.
224000.
232000.
240000.
240000: 00

R[T]. SECC
=FUNCTION=
1. 00000
O. 99446
O. 97804
O. 95132
O. 91518
O. 87080
0.81955
O. 76294
'0.70256
O. 63998
O. 57670
0.51411
O. 45341
O. 39562
0.34153
0.29171
O. 24653
'0.20616
O. 17059
0, 13968
O. 11318
0.09076'
0.07202
0.05656
O. 04397
o. 03382
0.02575
0.01941
O. 01448
o. 01069
o. 00782
O.

0~782

MTTF
HRS

ENHANCEMENT
FACTOR

O.
1439611.
722580.
484470.
366101.
295&38.
249140.
'216349.
192135.
173652.
159190.
147663.
138346.
130737,
124475.
119297.
115001.
111433.
108471.
106017.
103990.
102322.
100958.
99849.
98954.
98237.
97668.
97220.
96872.
' 96603:'
96397.
, =MEMORY MTBF=
95643. 55

3744.,
1879.
1260.
952.
769.
648.
563.
500.
452.
414.
384.
360.
340.
324.
810.
299.
290.
282.
276.
270.
266.
263.
260.
257.
256.
254.
253.
252.
251.
251.
=EF=
249.

R(T>
@T
100. 01.
99. 41.
97. 81.
95. 11.
91. 51.
87. 11.
82. '01.
76. 31.
70. '31.
64. 01.
57.,71.
51. 41.
45. 31.
39. 61.
<: 34. 21.>
29.21.
24. 71.
20. 61.
17.11.
14. 01.
11. 31.
9. 11.
7. 21.
5. 71.
4. 41.
3. 41.
2. 6i1. 91.
1. 41.
1. 11.
0.'81.

------------------------------------------------------~---------

ECC PROBAB I LI TY PROGRAM "I NTEL -MPD/MC. "

WORD WIDTH-> 32. + 7. NO. PAGES->
1. X 1.
MEMORY SYS: SIZE->
64. OKB
COMPONENT: TOTAL-)
32. +
7.
RAM SIZE->
16384. COL SIZE-> 128.
SYSTEM RATE -) O. OOOOOY./IK-HRS
SYSTEM DATA:
TTL RATE -> o. OOOOOY./IK-HRS,
FAILURE DATA:
MTBF. NECC -)
24606. 30HRS, MTBF. SYS -)
O. OOHRS
HARD ERRORS:
PARTIAL -)
o. CELLS/PG RATE -)
0.027000Y. I 1000 HRS.
"*" MAINT ->
O. HRS, RATE ->
O. 100000Y. I 1000 HRS
SOFT ERRORS:
ANALYSIS DATA:
PERIOD -)
66000.00HRS, AVE CELL FAILURE -~>
16.2
FAILURE TYPE RATIOS:
-------------------------------------------------=TVPE=
=DISTRIBUTION=GEOMETRV=UNIT. RATE/IK HRS=AVE. CELLS=ECC. DISTR=EXPS=,
SOFT ERROR ->[ 78. 740Y.ll 16384. = Q 61035E-05Y.,
O. 787
[
~ 87Y.l
HARD ERRORS -)- [ 21. 260Y.]
. [ 95. 13Y. 1
1.
SINGLE CELL -:~. 50. OOOOY. I 16384. = O.. 82397E-06Y.,
o. 106
O. 69:'1;
ROW OR COL -)4a 7000Y. 1128. = Q 92180E-04Y.,
11.892
77.36Y. 128.
2.
COLUMN/ROW -) 6. 2000Y. I
64. =
o. 26156E-04Y.,
3. 374
21. 95Y.
32.
HALF CHIP
-). o. OOOO~/; /
2.
O. OOOOOE+OOY.,
O. 000
O. OOY.
2.
TOTAL CHIP -)
O.OOOOy. I
1. = O. OOOOOE+OO~;,
0.000\
O.OO/.
PERIOD

<
0
1
2

3
4
5
6

7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

PM(H:
HRS)

6e.000.
132000.
198000.
264000.
330000.
396000.
462000.
528000.
594000.
6e.0000.
726000.
792000.
858000.
924000.
990000.
1056000.
1122000.
1188000.
1254000.
1320000.
1386000.
1452000.
1518000.
1584000.
1650000.
1716000.
1782000.

28 1782000.00

FIN

R[Tl. SECC
=FUNCTION=
1.00000
O. 99070
0.96:388
O. ~/2173
O. 86699
o. 80276
O. 7:3219
o. 65828
o. 58374
o. 51088
O. 44151
O. 37700
O. 31821
o. 26564
O. 21942
O. 17941
o. 14528
o. 11655
O. 09267
0.07:305
O. 05712
0.044:31
0.03411
0.02607
0.01979
o. 01492
0.01118
0.008:32
0.008:32

MTTF
HR:3 .'

ENHANCEMENT
FACTOR

7066011.
3604737.
2458257.
1890484.
1554231.

287.
146.
100.
77.
c13.
54.
48.
4:3.
40.
37.

13337~/0.

1179584.
1066829.
'781755.
916096.
864581.
82:3(:.86.
790~/58.

764629.
74:3:388.
72e.238.
712400.
·70 125·?
692319.
685174.

~:5.

3:3.
32.
31.
30.
:30.

~,!.

6"71465.
668705.
6665.62.
664nO.
e.63644.
=MEMORV MTBF=
658122. 51

28.
28.
28.
28.
27.
27.
27.
27.
27.
.27.
=EF=
27.

R(T)
@T
100. 0:'1;
99. lY.
96.4:'1;
92. 2Y.
86. 7Y.
80. :3Y.
73. 2Y.
65. 8Y.
58. 4Y.
51. lY.
44.2:'1;
37. 7Y.
.,.'... 31. 8:'1;)
26. 6Y.
21. n
17.9Y.
14. 5Y.
11. 7Y.
9. :3Y.
7. :3Y.
5. 7Y.
4. 4Y.
3. 4Y.
2. 6Y.
2. OY.
1.5:'1;
1. 1:'1;

ECC PROBABILtTY PROGRAM "INTEL-MPD.lMC.

MEMORY SYS: SIZE-)
8. 2MB
WORD WIDTH-) 32. + 7. NO.PAGES->
1~ X12&
COMPONENT: TOTAL-> 4096. +
89(:·.
RAM ::::rZE-)
1(:.:384. COL SIZE-) 128.
SYSTEM DATA:
TTL RATE -) O. OOOOO%/lK-HRS.
SYSTEM RATE -> O. OOOOO%/lK-HRS
FAILURE DATA:
MTBF. NECC ->
HARD ERRORS:
PARTIAL ~>
".><." MAINT ->
SOFT ERRORS:
ANALYSIS DATA:
PERIOD ->

FAILURE TYPE RATIOS:

192. 24HRS.
O. CELLS/PG
O. HRS.
5000.00HRSj

MTBF. :3YS -:>
O.OOHRS
RATE ->
O. 027000% / 1000 HRS
RATE -~,
O. 100000% .I 1000 HRS
AVE CELL·FAILURE ->
16.2

--------------------------------------------------

""TYPE""
=DISTRIBUTION=GEOMETRY=UNIT. RATE.I.1K HRS=AVE. CELLS=ECC. DISTR=EXPS=
SOFT ERROR -)[ 78. 740:'1;]/ 16:384.
O. 610:;::5E-05:'1;.
O. 787
[
4. 87%]
HARD ERROR:::; - >[ 21. 260,;]
[ 95. 13,;]
SINGLE CELL - ) 50. 0000% .I 16:384. =
O. 82::::97E -06,;.
O. 106
O. 69%
1.
ROW OR COL - ) 4:3. 7000:;; .I
128.
O. 92180E-04:;;.
11.892
77. :3(:./.: 128.
~3.374
COLUMN/ROW -:>
6. 2000% /
64.
O. 26156E-0'l·%.
21. 95%
2.
-)
HALF CHIP
2.
O. OOOOOE +OO~/;.
O. 000
O. 00%
32.
O. 0000:;; I"
O. OOOOOE+OO:;;.
O. 000
O. 00%
2.
TOTAL CHIP -:> O. 0000:;; .I
1.
PERIOD

<:
0
1

PM@T:
HRS:~

11
1.-,
"'.;.,
1'-'
14
15
16
17
18
19
20
21
22
2:3
24
25
26
27

O.
5000.
lOOOO.,
15000.
20000.
250(10.
:30000.
:35000.
40000.
45000.
50000.
55000.
60000.
65000,
70000.
75000.
80000.
85000.
90000.
95000.
100000.
1050()0.
110000.
115000.
120000.
125000.
1:30000.
135000.

ReT]. SECC
=FUNCTION=
1. 00000
0 .. '7','306
O. 97257
O. 9:3940
O. 8'7494
O. 8409~i
O. 77946
O. 712(:.','
O. 6428:3
O. 57202
O. 50219
O. 4:34'79
O. ::::7176
0, :31::::51
O. 260.,'0
O. 21425
O. 17::::64
O. 13888
O. 10';'6:3
O. 08542
O. 06569
O. 04987
O. 0::::737
O. 027(:.5
O. 02019
O. 01456
O. 010:37
O. 00729

O. 00729

.,;:

MTTF
HRS:>
O.
71815(:..
:36076(:..
242201.
183350.

ENHANCEMENT
FACTOR
O.
:37:36 ..
1877.
1260.
954.

~/;

R(T)
@T
100. O~/;
·'i'9. 3%
97. 3%

772.
. 125:392.
1092:32.
97356.
88:344.
81:346.
75818.
71:398.
(:.78:35.
64949.
62605.
60702.
59159.
57913.

652.
5(:.8.
506.
460.
42:3.
394.
:371.
:35:~.
:=::3:3.
326.
:316.
30:::.

56116.
55486.
54992.
54609.
5431(:..
540.,'3.
53927.
5::::804.
=MEMORY MTBF=
53412. 22

:301.
296.
292.
28'7.
286.
284.
28:3.
281.
281.
280.
=EF=
278.

89.
84.
77.
71.
64.
57.
50.
43:
:37.
:3.1.
26.
21.
17.
1'-;'
~'.

l?;
9:;; ,
:3%
3%
2:;;
2%
5%
2~/~

4:;;)'
1%
4~t,;

4%
-::,~t,;

11. 0%
8. 5Y.
6.
5.
3.
2.
2.
1.
1.
O.

6%
0%
7X
8%
0%
5%
0%
7%

O. 18722E-Ol

inter.

AP-73
ECC PROBABILITY PROGRAM "INTEL-MPD.lMC. "

WORD WIDTH-)
64.+ 8. NO. PAGES-)
1. X ·1.
MEMORY SYS: SIZE-)
128. OKB
:3.
RAM -SIZE-)'
lb~:84.
COL. SIZE-> 128.
COMPONENT: TOTAL-)
64. +
SYSTEM RATE -) O. 00000%.I1K-HRS
SYSTEM DATA:
TTL RATE -) O. 00000%.I1K-HRS.
FAILURE DATA:
MTBF. NECC -'-)
12:30:3. 15HR:;. MTBF. SYS -)
O.OOHRS
HARD ERRORS:
PARTIAL -)
O. CELLS.lPG RATE ->
O. 027000% .I 1000 HRS
::::OFT ERROR:::::
"*" MAINT -)
O. HRS; RATE -)
O. 100000% .I 1000 HRS
PERIOD -:>
:3:3000.00HRS. AVE CELL FAILURE -)
16.2
ANALYSI:::: DATA:
FA I LURE TYPE RAT I 0::::
-------------------------------------------------=TVPE=
=DISTRIBUTION=GEOMETRY=UNIT. RATE.llKHRS=AVE. CELLS=EC~ DISTR=EXPS=
SOFT ERROR -)[ 7& 740%J.I 1638~
O. 61035E-05%.
~ 787
E ~87%]
HARD ERRORS -)E 21. 260%J
[ 95. 13%]
::::INGLE CELL -) 50. 0000:'1; .I 16:384.
O. 82:::':nE-06~/;.
O. 106
O. 69~1.
1.
O. "/2180E-04~/;.
11. E:92
77. :36:'1;
128.
12E:.
F:OW OR COL -:> 4::::. 7000~i. .I
2.
O. 26156E-04%.
a 374
21. 95%
e:A.
COLUMN/ROW -:> 6. 2000/~ /
O. OOOOOE+OO%.
~OOO
~ 00%
-:> o. (H)OO:'l; .I
2.
HALF CHIP
2.
O.OOOOOE+OO%.
O.OOO~. 00%
1.
TOTAL CHIP -:> O. OOOW; /
PM@T:
HR:::::)
O.
:3:3000.
66000.
':;19000.
1:32000.
165000.
1',1:3000.
2:31000.
264000.
2','7000.
:3:30000.
:36:;:000.
39e:,OOO.
429000.
462000.
4.';/5000.
528000.
561000.
594000.
627000.
660000.
.e:,9:;:000.
726000.
75';'000.
792000.
825000.
858000.
891000.
0;'24000.
957000.

I"....
1:3
14
15
16
17

RET]. SECC
""FUNCT I ON""
1. 00000
O. .,/9197
O. 96871
O. 93192
O. :=:8:376
O. 8261:.,::::
O. 76:308
0, 69556
O. 626:3'~1
O. 55758
O. 4·908:3
O. 42747
O. :::6848
O. 31451
O. 2l:0592
O. 22280
O. 1:3504
O. 15240
O. 12450
O. 1009:3
O. N::120
O. 06487
o. 05l.4e:,
O. 04056
O. 03176
O. 02472
O. 01912
O. 01471
O. 01125
O. 00856

O. 00856

MTTF,
HR:;::

ENHANCEMENT
FACTOR

4·092e:,67 .
2084463.
141E:701.
1088549.
892655.
76:3','11.
67:::5e:A.
e:,072:::8.
55e:8'49.
517906.
487054.
462:357.
442::::98.
426159.
.41.2889.
402018.
39:3104.
3857a;-/7 .....
379818.
374936.
:::70'~64.

:33~:.

169.
115.
8E:.
7:3.
1-.;;0 .-,
.....

55.
49. '
45.
42.
40.
:38 .
:3e:,.
:35.
:::4.
:3:3.

.......

':0'7
._

31.
31.
30.
30.
30.
:30.
:30.
29.
29.
2Q
29.

367744.
:3651'47.
:36:3061.
361395.
:360071.
359025.
35820:3.
:357561.
=MEMORY MTBF=
354499. 33

,-----,--, f - - - -... ERROR

L -_ _ _ _ _ _ _ _ _~-----~S~E~D~cu~R~m~~~~w~Z~~~M~,~.-~.-----~

1. The 8206's two 16-bit data buses, one lor data Irom the RAM (01 0 . 15 ) and one lo,data to the system bus
(0° 0 •,5), minimize the external control logic required.

Electronic Design. September 30. 1981

3-170

by single-bus EDCUs. The principal advantages of
dual-bus architecture can be illustrated by looking
at the three types of memory cycles: reads, writes,
and read-modify-writes.
In a read cycle (Fig. 2), data and check bits are
received from the. RAM outputs by the Dl and CBI
pins. New check bits are generated from the data
bits and compared to the check bits read from the
RAM. An error in either the data or the check bits
read from memory means the generated check bits
will not match the read check bits. If an error is
detected, the ERROR flag is activated and the correctable error (CE) flag tells the system if the error is
(or is not) correctable.
With the BM inputs high, the corrected word
appears at the DO pins (if the error was correctable),
or the unmodified word appears (if the error was
uncorrectable). Note that for this correction cycle
there is no control or timing logic required. The 8206's
dual buses isolate the RAM outputs from the EDCU
outputs. Special transceivers that prevent contention
between the uncorrected RAM data and corrected
EDCU data are not needed.
A syndrome word, five to eight bits in length and
containing all necessary information about the existence and location of an error, is provided at the
syndrome output (SYO/CBO/PPO) pins. Error logging
is accomplished by latching the syndrome and the
memory address ofthe word in error. The syndrome
decoding of Table 3 can be used as a table lookup
by the CPU.
If an error is detected during a read, the read cycle
is extended to a read-m'odify-write cycle where the
corrected dilta·is rewritten to the same location. This
offers several advantages:
• Since soft errors are random, independent processes, the longer a soft error is allowed to remain
in memory, the greater the probability that a second
soft error will occur in the memory word, resulting
in an uncorrectable double-bit error. By writing the
correct data back to RAM, the mean "lifetime" of
soft errors is reduced, greatly reducing the chance
of double-bit errors, and increasing reliability.
II "Error scrubbing" (going through the entire
memory and correcting any soft errors) may He done
as a background software task. F'or instance, the 8086
microprocessor's load string (LODS) instruction can
consecutively read all addresses in RAM. Any soft
errors will be corrected. Scrubbing further ihcrea§es
system reliability.
.• Error logging may be used to detect hard errors.
(A soft error is seen once when the affected word
is read and is then corrected, while a hard.error is
seen again and again.) An error logger shows a
consistent pattern if a hard error is present in a
particular word. A system may be configured to

2. The 8206 requires no control logic or timing inputs to
perform read-wilh-correction cycles.

• Uncorrected data

.. Uncorrected
check bits

"I
I
I
I

Corrected data

3. The 8206 can correct both. data bits and check bits.

generate an interrupt when the 8206 detects an error .
This last advantage allows the operating system
to re-read the address where the error occurred. If
the same error re-occurs, it is assumed to be a hard
error, and while the system can continue to function,
maintenance is indicated. The operating system may
mark that page of memory as "bad" untiLits PC card

3-171

Eleclronlc Dellgn • September 30. 1981

, Memory Technology: Error-correction chip
has bee,n serviced. Alternatively, thll memory system
may reconfigure itself and rttap the bit where the
hard error occurred to a spare dynamic RAM
whenever the affected memory page is accessed.
When a correctable error occurs during a read
cycle (Fig. 3), the system's dynamic RAM controller
(or CPU) examines the 8206 ERROR and CE outputs
to determi~e if a correctable error occurred. If it did,
the dynamic RAM controller (or 'CPU) forces R/W
low, telling the 8206 to latch the generated syndrome
and drive the corrected check bits onto the
SYO/CBO/PPO outputs. The corrected data is already
available on the DO/WDI pins. The dynamic' RAM
controller then writes the corrected data and check
, bits into memory. Once again the 8206's dual buses
allow this cycle to be implemented without special
bus transceivers.
The 8206 may be used to perform read-modifywrites in one or two RAM cycles. If it is done in two
cycles, the 8206 latches are used to hold the data and
check bits from the read cycle to be, used in the
immediately following write cycle. '

CPU or dynamic RAM controller, which can then performone of several optins: lengthen the current cycle
for correction, restart the' instruction, perform a
diagnostic routine, or activate the CRCT input to
enable error correction. Even with the CReT pin

Write cycle corrections

For a full-word write (Fig. 4) where an entire word'
is written to memory, data are written directly to
the RAM. This same data enter the 8206 through the
DO/WDI pins where five to eight check bits are
generated. The check bits are then sent to the RAM
~hrough the, SYO/CBO/PPO pint! for storage along with
the data word.
,
A byte write (Fig. 5) is implemented as a read, modify-write cyrle. Since the Hamming code works
only on entire words, to write on~ byte of the word,
it.is necessary to read the entire word to be modi{ied,
perform error correction, merge the new byte into
the old word inside the 8206, ,generate check bits for
the new word; and write the whole word plus check,
bits into RAM.
,Error correction on the old word is important.
Suppose a bit error occurs in the half of the old word
that was not changed. This old byte would, be
cornbined with the new byte, and check bits would
be generated for the whole word, including the bit
in error. The bit error now becomes "legitimate"; no
error will be detected when this word is read; and
the system may crash. Obviously, it is important to
eliminate this bit error before new check bits are
generated.
The 8206 may alternatively be used in a "checkonly" mode with the correct (CRCT) pin left inactive.
With the correction facility turned off, the delay of
generating and decoding th~ syndromes is avoided,
and the propagation delay from memory outputs to
8206 outputs is significantly shortened ..!n the event
of an error, the 8206 activates the ERRoR flag to the
Electronic De.lgn '. September 30. t981

_ddta
4. The 8206 generates check bits and ~rites them to memory.

• Uncorrected data'
•• Uncorrected
check btts

5. The "new data" byte is supplied by the CPU, while the
8206 supplies the corrected old byte. The 8206 also generales
new check bits.

3·172

inactive, the 8206 generates and decodes the syndrome bits, so that data may be corrected rapidly
if the CRCT is activated.
Multiple 8206 systems

A single 8206 handles eight or 16 bits of data and
five or six check bits, respectively. Up to five'8206's
can be cascaded for 80-bit data words with eight
check bits. When cascaded, one 8206 operates as a
master, and all others work as slaves (Fig. 6).
As an example, during a read cycle in a 32-bit
system with one master and one slave, the slave
calculates "partial parity" on its portion of the word
and presents it to the master through the partialparity output (SYO/CBO/PPO) pins. The master receives the partial· parity at "its partial-parity input
(PPIIPOS/NSL) pins and combines the partial parity
from the slave with the parity it calculated from its
own portion of the word to generate the syndrome.
The syndrome is then returned from the master to
the slave for error correction.
The 8206 uses a modified Hamming code which
was optimized for multi-chip EDCU systems. The
code is such that partial parity is computed by all
8206's in parallel. No 8206 requires more time for
logic propagation than any other, hence no single
device becomes a bottleneck in the parity operation.
The 8206 is easy to use with all kinds of dynamic
RAM controllers. Because of its dual-bus architecture, the amount of control logic needed is very small.

Data' memory
16bils

DI
32 bit
data

bus

Figure 7a shows a memory design using the 8206 with
Intel's 8203 64-kbit dynamic RAM controller and
2164 64-kbit dynamic RAM. As few as three additional ICs complete the memory control function
(Fig. 7b).
For simplicity, all memory cycles are implemented
as single-cycle read-modify-writes (Fig. 8). This cycle
. differs from a normal read or write primarily in
when the RAM Write Enable (WE) is activated. In
a normal write cycle, WE is activated early in the
cycle. In a read cycle, WE is inactive.
A read-modify-write cycle consists of two phases.
In the first phase, WE is inactive, and data are read·
from the RAM; for the second phase, WE is activated
and the (modified) data is written into the. same word
in the RAM. Dynamic RAMs have separate data
input and output pins so that modified data may be
written, even as the original data is being read.
Therefore, data may be read and written in only one
memory cycle.
In order. to perform read-modify-writes in one
cycle, the 8203 dynamic RAM's CAS strobe must be
active long enough for the 8206 to access and correct
data from the RAM, and write the corrected data
back into RAM. CAS active time (tCAS ) depends on the
8203's clock frequency. The clock frequency and
dynamic RAM must be chosen to satisfy:
tCAS(~r~) 2':

+ TDVQvsaJS +
TQVQvs206 + tDlAM +

• Data memory
16 bits

Check bits
7 bits

tCAc RAM

"6. No additional logic Is required for this 32~blt master-slav'e syste~. The slave calculates partial parity on
Its half olthe data, and the master determines which olthe 32 data bits and 7 check bits I.s h., error.
.

3-173

Eleclronlc Dellgn • September 30. 19B1

'Table 3. Syndrome decoding identifies and corrects
all single-bit errors.
~-----------O~O--~l--~O--~l~-O~-~l--'~O~-~l-~-O~--i'~o~~l--~O--~1--0~-1~

CB2 D
D 18 CB3_ D D O D
1
2 D
__ ..Ii . J. __Q._ .. _Q ... _.L.1.6 .1L _'L_.P___O__ ~~
_~"'!_Cl.. _ CBS
19 ___ 12_....:P. __ Q_~. __ 9___ p_.!Q.....Q_p__ J1_~
o 0 1 1
D . __ ~_ .. 1~_. _Q_J.~_._.o_ ... Q.~1.. __ gQ..._..Q_~_~..Q. 22. ~~
o
1
0
0
CB6
D
D
25
D
26 .t9. D
D 1!L.24 D27 D D 50
o
1 OlD
52
55
D
51
D - D 70 28
D D 65 D 53 54 D
o
1
1
0
D
29
31
D
64
D
D 69 68
D D 32 D 33 34 D
30
D
D
37
D
38
39 D
D
35 71 D 36 D D;--.!L
o
1
1
1
0
0
0
CB7 .__D_ ..
43 .__Q........zL_4.L..!L_.P___ ~i>_ 41 D 42 D 'D U
1
0
OlD
45
46
D _~._...Q_Q_E_.. }.~_ JJ D U D 73 U D
1
1
0
1
0
D
59
75
D
79
D
D 58 60
D D 56 D U 57 D
1
0
1
1
63
D
D
62
D
U
U D
D
U U D 61 D D U
U
U
DUD
"0 U 76 D D U D U U' D
1
1 ODD
0
1
78
D
DUD
U
U D
D
U U DUD D U
1
1
lOU
D
DUD
UU D
D
U U DUD D U
1
1
1111
D
U
UDUDDUUDDUDUUD
~...!I_..1_--,CB4 __[) ____ p

__ ? __ Q
__.!L_.__!L.11..j:)

2 ...

N No error
CBX =.Error in check bit X (correctable)
X = Error in data bit X (correctable)
>:::;

D = Double·bit error (detected but not corrected)
U = uncorrectable multi~bit error

A, - - - - -.....
SHE

DI~~~e
Sy"em
control
bus

{ CS

(b)

7 .. The 256-kbyte system (a) has'32 64-kbyte dynamic RAMs for data plus 12 dynamic RAMs for error
correction. The dynamic RAMs are controlled by the 8203 dynamic RAM controller while error correction
control Is supplied by the 8206: Intltrface logic (b) allows the 8203/8206 system to implement readmodify-write cycles by generating Write Enable (~l to the RAMs, Read/Write(RiWI to the 8206. an.d byte,
. control signals.
Electronic D•• lgn • September 30. 1981
3-174

Memory Technology: Error-correction chip
The 8203 itself performs normal reads and writes.
To perform read-modify-writes, simply !!hange the
timing of the WE signal. In Fig. 7b, WE is generated
by the interface logic-the 8203 WE' output is not
used. All other dynamic RAM control signals come
from the 8203. A 20-U damping resistor reduces the
WE signal ringing. These damping resistors are
included on-chip for all, 8203 outputs.
The interface logic generates the R/W input tothe
8206. Tohis signal is high for read cycles and low for
write cycles. During a read-modify-write cycle, RiW
is first high, then low.
The falling edge of R/W tells the 8206 to latch its
syndrome bits internally and generate corrected
check bits to be written to RAM. Corrected data are
already available from the DO pins. No, control
signals at all are required to generate corrected data.
R/W'is generated by delaying CAS from the 8203 with
TIL-buffered delay line. This delay (tD~LAY \) must
satisfy:
\

A'·A..)~_ _ _ _ _ _ _ _ I
RAS

8. In all memory cycles, the row and ,column
addresses are strobed to the RAMs byiiAs and CAs,
Sometime after the data out is valid, the control logic
in Fig. 7b generates Write EnablejWe) to write the data
back Into the RAMs.

composite word. This is difficult with most EDC
chips, but it is easy with the 8206.
Further qualifications on 8206 operation

Referring again to Fig. 7b, the 8206 byte-mark
inputs (HMo. liM,), are generated from AO and BHE,
tOELAY \ ~ tCA/AM + TDVRL 8200
respectively (off the 8086's address bus) to tell the
8206 which byte is being written. The 8206 performs
The 8206 uses multiplexed pins to output the
error correction on the entire word to be modified,
syndrome word and then the check bits. The R/W
signal may be used to latch the syndrome word
buta"~tates its DO/WDI pins for the byte to bewr\tten;
this byte, is provided from the data bus by enabling
externally for error logging. The 8206 also supplies
the corresponding 8286 transceiver. The 82Q6 then
two useful error signals: ERROR indicates an error
generates check bits for the new word.
'
is present in the data or check bits; CE tells if the
During a read cycle, BMo and BM, are forced inactive
error is correctable (single bit) or uncorrectable
(Le., the 8206 outputs both bytes even if 8086 is only
(multiple bits).
reading one). This is done since all cycles are imAfter R/W goes low, sufficient time is allowed for
plemented as read-modify-writes, so both pytes of
the 8206 to generate corrected check bits, then the
data (plus check bits) must be present at the RAM
interface logic activates WE to write both corrected
data in pins to be rewritten during the second phase
data and check bits into RAM. WE is generated by
of the read-modify-write cycle. Only tqose bytes
delaying CAS from the 8293 with the same delay line
actually being read by the 8086 are driven on the
used to generate R/W. This delay, tDELAY 2' must be
long enough to allow th"e 8206 to generate valid check
data bus by enabling the corresponding 8286
transceiver.
bits, but not so l!lng that the spec of the RAM
The 8286's Output Enables (OEBo, rn,) ~re
(tCWL) is violated. This is expressed by:
qualified by.the 8086'sRD, WR commands and the
8203's CS command. This serves two purposes: It
prevents data bus contention during read cycles and
Errors in both data and check bits are automatically
it prevents contention between the traniceivers and
corrected, without special 8206 programming.
the 8206 DO pins at the beginning of,. write cycle.
Since the 8203 terminates CAS to the RAMs at a
Thanks to the use of a 68-pin l~adless chip carrier,
fixed interval after the start of a memory cycle, a " the 8206 error detection and correction unit is able
latch is usually needed to maintain data on the bus
to implement an architecture with separate 16-pin
input and output buses. Thus single-bit !!rror correc- '
until the 8086 completes the read cycle. This is
conveniently done by connectingxACK from the 8203
tion may be added to a system with aminirilUm of
control signals or external 10gic.D
to the STB input of the 8206, latching the read data
and check bits inside the 8206.
The 8086,like all 16-bit CPUs, is capable of readi~g
and writing single-byte data to memory. As just
explained, the Hamming code works only on entire
words, so in byte writes, and new byte and old byte
must be merged, and new check bits wriUenfor the
3-175

ARTICLE
REPRINT

AR-197

JANUARY, 1982

COPYflght.by Computer DeSIgn Publlshmg Co. C January, 1982.

AH,Rights. Reserved. Reprinted by Permission

3·176

ORDER NUMBER: 210378

Ii
.

''''IA, ...." 01 •••DRY SY'' M'

DE~"

BETTER· PROCESSOR
PERFORMANCE VIA
GLOBAL MEMORY
Wait states are eliminated by joining global and local
memories through five TTL components
.

by Joseph P. Altnether

t least 600/0 of today's designs incorporate
microcomputers, which have become one of the
most widespread components in a variety of electronic equipment ranging from video games to naviga-·
tional flight computers. Microcomputers comprise
several elements. One of tl!emore important of these is
the memory. II). early systems· (and even in some of
today's low performance microcontrollers), the memory
is interfaced and accessed exactly like any other peripheral. Such an architecture is shown in Fig 1. For this
type of application, data store (random access
memory), control store (electrically programmable read
only memory/read only memory), and input/output
reside on a single bus connected directly to the central
·processing unit. This kind of application is usually a
dedicated system performing only one function, such as
control of a vending machine.
Memory consists of control store and data store. The
former occupies most· of the ·memorY and contains
about 16k bytes of program; the latter is small and contains less than 4k bytes. A major design goal is simplicity, which can be best achieved when the components
of control store and data store are compatible. It is
much simpler and certainly more efficient to use the

Joseph P. Altnether is technicai marketing manager
for memory products at Intel Corp. Aloha. OR
97005. Be/ore that. he worked as an applications
engineer at Intel and a memory system designer for
nuclear/medical instruments at G. D. Searle. Mr
Altnether has a BSEE/rom St Louis University.
JAlUARY 1982

same set of address
decoders and drivers, as·
well as data transceivers,
for both control and
data, store. ,This is
achieved with common
pinout and functionality
between random access
memory (RA¥) and electrically programmable
. read only memory/read
only memory (EPROMI
ROM). Therefore, the
memory should be an
8-byte wid'e RAM. Several
disadvantages are inherent in such a system: the address
space is limited; and because all elements-including the
central processing unit (cPu)-rcside on a common bus,
the cpu, as the bus controller, suspends processing to
control bus operations. .

Enhancing the system
.
The performance of this system can be enhanced by
upgrading to a microprocessor and storing a variety of
programs in permanent bulk memory. In this kind of
system, control store consists of a RAM containing up to .
64k bytes (Fig 2). This memory is much larger because'it
, serves a dual function: data store and control store.
Programs to be executed are downloaded via a boot
program residing in EPROM. The system overcomes the
memory addressing space deficit of the previous system'
but still retains the disadvantage of having all memory

3-177

COMPUTER DESIGI

checking and correction, and direct memory access all
become cost effective .

. _. because the global memory is so
large, the RAM used must be as dense
as possible to reduce the number of
components_
Fig 1 Single-bus architecture of dedi'cated microcontroller_
Though inexpensive, this configuration limits available
address space and requires that CPU suspend processing
when controlling bus.

~PRO,M [BU~:;fS qro
.
ROM

lAP I

---'--=:J

Fig 2 Improved performance results when microprocessor
using RAM program storage for up to 64k bytes of data and
control infonnation is used. Disadvantages of common bus
architecture are retained, however.
'

reside on the CPU bus. For example, throughput efficiency could be improved if it were possible to download other portions of the program into control store
while executing out of control store (dual porting).
High performance in both processing power and
speed is realized in distributed processing systems. In
such a configuration, several processors, together with
their local memories, are distributed throughout the
system. These could be structured like the' systems
previously described; however, they have an important
distinguishing element-multiple local buses with a
common system or global bus. Fig 3 depicts such a
system. Here, the advantages of dual porting, error

Residing on the system bus is a global memory to
which every processor has access. This memory can be
very large-even greater than 1M byte. Consequently, it
could be disk, tape, magnetic bubble, or. RAM. If built
with RAMs, the type used would be dynamic RAMs
(DRAMs) for several reasons. First, because the global
memory is so large, the RAM used must be as dense as
possible to reduce the number of components. Lower
component count reduces system cost and increases system reliability, which is inversely proportional to the
number of components in the system. Second, the components should consume minimal power. Even a small '
amount of power per device mUltiplied by hundreds of
devices will require a large power supply. In addition, as
the power requirements increase, so do the cooling requirements, which again add to the overall system cost
and operating cost.
Finally, the RAM must be low cost to be competitive
and provide ample operating margins. DRAMs meet
these requirements quite adequately as they provide the
lowest cost per bit and also consume the lowest power
per bit' of RAM devices. Unfortunately, designing with
DRAMs has long been considered esoteric and difficult.
In fact, some designers still believe that DRAMs do not
even work. The first of these beliefs was based on fact in
earlier days, but the second is based on an emotional

, ---- ----~ )Y~llM HU~
-;.- - - - - - - - / ;NON MlJllll'IIXIIJI

Fig 3 Distributed processing system using several
processors with local memories and common (global) bus
provide high performance. Each processor in system has
access to large (1M-byte) global memory.

Fig 4 Typical pRAM controller. Oscillator provides timing
and control logic for refresh timer.

3-178

to design. In theory, a D type flipflop could be an arbiter (Fig 5). If refresh request is set asynchronously
with respect to the system clock, a decision on the, Q
output can be made. If Q is true, the refresh cycle is
granted;' if false, the CPU is given access. Timing relationships of data and clock indicate that normal operation of the flipflop will occur if setup and hold times of
data with respect to the clock are met.
If the setup or hold times are violated, however, the Q
output is no longer a transistor-transistor logic (TIL)
level 1 or O. The output becomes an analog signal
floating between TIL levels somewhat like a 3-state output device with the output in a high impedance state.
This condition can persist for as long as 75 ns, duriIig ,

Q OUTPUI
o IYPE
LATCH
CLOCK

OATA

--l ISET~P

I~--------~-------

CLOCK -----------..JL~
,_
IHOLO QUASI 'STABlE STAlE

QOUT~P~UT============t===~~~~~~~~;=
I="
I
__

IPROP'
VIOLATING ANO SETUP
_IPROP'
OR IHOLO
,I

'CAN BE UP TO ]5 os FOR A ]4S]4

The ... DRAM controller... includes an
arbiter which synchronizes the refresh
and memory cycle requests to
eliminate the arbitration problem ..•.

Fig,s Timing diagrams for arbiter circuit show that when
certain conditions exist. output is analog signal floating
between TTL levels 1 and O. During this 75.ns,period. no
decisions can be made and refresh failure occurs.

reaction to a memory that forgets unless it is periodically told to remember. DRAMs do not lose data if they
are properly refreshed. This can be easily accomplished
by a memory interface controller.

which it i's impossible to make a decision. At the system
level this appears as a refresh failure. Lastly, the controlle'r requires multiplexers and drivers for the memory
addresses. The total system is built with 20 TIL com~
ponents (Fig 4).
Another consideration is design time. About four
weeks are usually required for design, two weeks for
worst-case analysis, six weeks for printed circuit board
layout, four weeks for building and debugging, and
another four weeks for redesigning to add features or
correCt errors. And this does not include a possible second iteration effort. In any case, the task could consume up to six man-months.

Designing a DRAM system
Although it is more difficult to design a DRAM system
than a' static RAM' (SRAM) system, it is not impossible.
Shown in Fig 4 is a typical DRAM controller. At the heart
of the controller is' an oscillator which provides timing
and control logic for the refresh timer. Because DRAMs
are clocked, they need signals like row address strobe
(RAS), column address strobe (CAS), and write enable
(WE), which come from the control logic. The refresh
timer will periodically time out, typically every 15 p's, to
request a refresh cycle asynchronously with respeCt to' A simpler solution
CPU memory requests. To decide which request (CPU or
Intel's dynamic RAM controller, the 8203, is contained iII
refresh) is granted first, an arbiter circuit is required. a single 4O~pin package that incorporates the entire
The arbiter is the most, complicated controller element DRAM controller (Fig 6). It includes an arbiter which
r---------------'----------------, synchronizes: the refresh and
memory cycle requests to eliminate
the arbitration problem previously
described. Compatible with the
AHO TO AH,
8080A. 808SA, iAPX88, and iAPX86
family of microprocessors, the
MUX
ALo TO AL]
device directly addresses half a
megabyte of memory composed of
ROW
64k RAMs (eg, the Intel 2164). All the
AOORESS
refresh functions are, provided:
BO
BI TO OPI
timer, 8-bit address counter, and
multiplexers for addresses. Because
Riilsl
ViR
refresh is usually performed asynPCS
chronously with the CPU cycles, proTIMING
ARBITER
GENERATOR
vision is made for performing synREFRQ/ALE
chronous refresh .if required. At
times the: controller will be providing refresh when the CPU requires
access. Consequently, the CPU must
XO'lOPl
be placed in a WAIT mode. This is
X'I/CLK
accomplished with a signal from the
8203 called SACK. In addition, the
signal XACK can be used to clock
,Fig 6 4O-pin, llO3 DRAM controller includes arbiter that synchronizes refresh and
memory cycle requests eliminating indecisive condition of Fig 5. Chip directly
data into the latches during a read
addresses O.5M byte.
cycle.

3·179

mode, a bus controller such as the
Intel 8288 is required. In this case,
MRDC
the iAPX86 outputs status bits S. to
MWrC
S, that are interpreted by the bus
controller. Commands for read and
write are now generated by the bus
controller. Independent of the
mode, the 8203 and memory, interface identically to the micro16
processor.
Ease of use or simplicity of design
have been balanced against performance. The simple system shown
(Fig 7) typically operates with one to
two WAIT states required. For the
minimum mode operation, the read
(RD) and write (WR) commands occur too late in the memory cycle to
allow the DRAM controller to
Fig 7 Typical global memory interface for microprocessor. Multiplexed
generate a ready signal early enough
address/data bus serves as local bus and demultiplexed address/data bus serves as
to avoid WAIT states. Operation
global bus. Minimum or maximum mode operation is possible.
without WAIT states can be accomTo illustrate the ease of interfacing' global memories plished by transmitting advance RD or WR commands to
to the microprocessor, an iAPX86 system using an 8086 is the memory. This is a non-trivial task in the minimum
shown. The multiplexed address/data bus is normally mode because. the iAPX86 prodjJces the RD and WR
thought of as the local bus, and the demultiplexed ad- signals in a fixed relationship after address latch enable
dress and data bus as the global bus. In much larger (ALE) occurs. For maximum mode operation, the iAPX86
systems, it would be possible for the local bus to be outputs status bit information' ahead of ALE. With
demultiplexed immediately at the processor and for proper logic circuitry, these status bits can be decoded
another bus that services the entire system to be the and the information used to initiate the advance RD and
global bus. The system described works on either WR commands.
demultiplexed bus. The iAPX86 can be operated in either
With a small amount of additionallogic,it is possible
of two modes,minimum or maximum (Fig 7). In the to combine ea'se of use of the DRAM controller with high
former mode, the microprocessor generates the read performance. As a result, the iAPX86 can operate at 5
and write commands directly, whereas in the latter MHz and requires no WAIT states unless the memory is

r--------------------------------

k======;;;::;:::::======~OOTO
01&
00 100 16
'MUST BE 74S151 CRITICAL fOR PROP[R LATCH OPERATION
ICONNECTTOVCCTHROUCHlkPULlUP

AODITIONAl CIRCUHRY REQUIRED FOR mlO WAil SlAHS

Fig 8 To achieve 5-MHz operation with no
must be added.

WAIT

states, additional circuitry (dashed lines)

3·180

indicated by TI through T4. To read
without WAIT states, valid data must
"
reach the processor by the end of T3
minus 30 ns. The latest read data
CLOCK
arrival at the processor does indeed
fall within this time frame. The
memory read cycle begins with ADV
RDC (Fig 9), which is latched by the
LATEST
Al'
falling edge of ALE. ADV RDC
LAmT ADY ROC --+---\1
reaches the 8203 at 160 ns into the
AT8!OJ
1'------,----+cycle and begins access. Within 80
lATfStsru -+---+~
ns, SACK is valid and ANDed with
FROM 1203
"--_-t-'Sic""'c..
PCS to be returned to the 8284A clock
READVINPUT
as READY. As a result, no WAIT
(8I1FFUEOSACK)
TO am -t----t-J1
states are required unless the DRAM
TACK = IOns
controller is performing a refresh
cycle. The system is CAS access
limited, and as such theADV RDC to
CAS delay is 225 ns. The 85-ns CAS
Ons TOffn"nfOR 216t
access time (tCAC) must be added to
mi. W SlOWES12164
ACCESS WITH -+--'-----:---------1G~~~~dj:=
this time. Finally, an additional
LATEST RE"DDATA - t - - - - - - - - - ' - - . l r - - 45-ns delay through the buffers is
ARRiYAlAT 8086 -t----'----:-----..Jj\-......."'"
included for a total delay time of
DATA MUST IE YAllDAT
510 ns. Access required is 3 T times
CPlJ= lTCLCl-TDYCl -:-J:======~5I~O.~'=========1~~~~
(600 ns) minus 30 ns, or 570 ns. The
system indeed requires no WAIT
'CRITICAL TIMING roRZERQ WAH SUUS
states for operation.
'In the write cycle, the reliltionship
Fig 9 Read, cycle worst-case analysis. Processor T states TI through T4. are
between data and WE and the relashown. For, read without WAIT states, valid data must reach processor 30 ns
tionship of CAS and WE must be
before end of 1'3.
guaranteed. Data are written into
being refreshed. The circuitry added to the system is the DRAM on the falling edge of WE. Consequently, data
shown inside the dashed lines in Fig 8. The 8205 is a must be valid prior to the falling edge of WE. The skew
3:8 line decoder which monitors the status lines. With of data from the processor and WR from the 8203 is such
the proper combination of status lines So, S., and S" an that it is possible for the data to be valid after the falling
advanced, RD command (ADV RDC) ot an advanced WR edge of WR. In this event, invalid data would be written
command (ADV WRC) will be output on pin 13 or pin 14, into the memory as shown in Fig 10(a). In addition,
, respectively.
DRAMS have a timing cons'traint, tCWL' which is the
The RDor WR command; whichever is true, is liltched overlap between CAS and WE. If CAS were early and
by the corresponding 14S74 on the falling edge of ALE MWTC were late, tcwL wOj1ld be violated as shown in
from the 8288 bus controller. Latch outputs at pins 5 and Fig 1O(b). Both of these requirements are satisfied by
9 (ADV WRC anc;l ADV RDC) are entered into the 8203A WR ANDing AMWC with WR.
\'
and RD inputs directly. The two latches ~re cleared later
on the trailing edge of either the memory read command
(MRDC) or memory write cornmand (MWRC) through the
WORST-CA~~ FROM 8086~
two 74500 gates. System acknowledge (SACK)-used in
BEST CASE CAS/WE FROM 8203
..
place of (XACK) because it occurs sooner-is ANDed
lOS
with protected chip select (PCS) and returned to the'
Tl

(a)

Global memory" can be easily built
using only DRAMs and the ...
DRAM controller.

BEST CASE

CAS

FROM 8203

WORST-CASE COMMAND FROM 8086 (MWTC)

.'
ICWl
(b)

82MA, which provides a synchronous ready signal to the
iAPX86. The S, status bit (memory operation) is latched
by the 74S157 on the trailing edge of ALE. The 2: I
multiplexer is configured as a high speed ,flow-through
latch by feeding the output back into the input:Propagation delay time is only 7.5 ns. The advanced memory
write command (AMWC) is ANDed with WE to provide
WE to the DRAMs.
Read cycle worst-case analysis (Fig 9) considers the
maximum time delays. The four processor T states are

Fig 10 Required WE delay timing to memory

Fig II d~picts the worst-case timing analysis for a
write cycle, which is similar to that for the read cycle
with a few exceptions ..The ADV WRC is latched on the
falling edge of ALE. The earliest that CAS can occur is
105 ns after ADV WRC starts the write cycle. Valid data
are output from the CPU within 210 ns and reach the
memory 35 ns later. By ANDing the AMWC with WR from

3-181

the 8203. WE falls a minimum of 8 ns
after data are stable and valid at the
memory. In addition, this· ANDing
guarantees a minimum tC"wL of
100 ns.
Overall system performance is improved by using global as well as
local memories. Global memory can
be easily built using only dynamic
RAMs and the 8203 dynamic RAM
controller. Performance, together
with ease of use, is achieved by add"
ing just five TTL components. The
design of a 5-MHz system that runs
without WAIT states is a good ex-_
ample of this approllch .

"
8086 CLOCK

EARLIEST ADYWiC

AT BlOl

SACifROM 8203
REAOYtNPUr
tBUfF(REDSACK)
•

"T8284

•mlnRDY SETUP
AT8284::.6Dns

Acknowledgment

EARLlfSToorROM
ADVWRcOELAY

The author would like to thank Bill
Righter and Oav.id Chamberlin for
their help in preparing this article.

lATEsrVAUOOATA
FROM CPU
LATEST VAlJD DATA
ARRIVAL AT

216~

min .. Uns
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EARLIEST CLOCK(O AMWC
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808& IN mu MOOEAI 5 "HI
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EARliEST CLQgEO "MWC

+ PROP DELAYS", WI AT IIf4

·CRITICAL TIMING fOR IEROWAIT STATES

R'!prmredwith permiSSIOn trom Computer Oeslgn, Ma,ch~ 1983 Copyright Computer Design Publishing Co., fAil fights reserved .I

3·183

OROER NUMBER: 230652-001

THE ·CHIP THAT
REFRESHES ITSELf.

An 8k x 8 memory chip withonchip refreSh and control
circuitry offers designers the best aspects of both dynamic
and static RAMS.

overhead of large memory systems is spread over a large
amount of memory. Between the tw,o extremes represented by static and dynamic RAMs, however, is a perJoseph P. Altnether, and
formance zone where all three ideal characteristics (low
William H. Righter
cost,flexibility, and ease of use) are required.
Low cost can be achieved with a DRAM cell. A major
he ideal microprocessor memory has ,three major factor determining the cost of a memory device is the
characteristics: ease of use, flexibility, and low'cost. . physical area occupied by the memory cell. Small cell .
Unfortunately, all of these characteristics are seldom size allows small die size, which results in more die per
available in a single device. Thus, memory system wafer. The net result is lower cost.. DRAMs achieve lower
design involves compromises. Matching memory com- unit costs because they use a single transistor for the
ponent characteristics to desired design parameters rarely memory cell. Each SRAM ceil, on the other hand,
results in a' perfect fit.
requires six transistors. In addition, the DRAM cell proTo optimize memory design, the designer must set vides the benefits of low power and high density. The
priorities in choosing between static random access remaining ideal characteristics (flexibility and ease of
memory (SRAM) and dynamic random access memory use) demand more innovative approaches 'than are pres(DRAM). Neither choice completely supplies all the bene- entlyavailable.
ficial characteristics. SRAMs are easy to use, but high
A microprocessor memory system using DRAMs concost, limited density, and high power consumption limit sists of three majot elements: microprocessor, memory,
their application to under 64k bytes. DRAMs are suitable and controller. To gain ease of use, the controller must
for large memory arrays (above 64k bytes) where density be incorporated into either the microprocessor or the
and low' power are important. In addition; the refresh memory. By including the memory control in the microprocessor, asimple memory device can be built in which
the cost Of the control logic is distributed over the entire
John J; Fallin is currently an applications engineer at
memory system. Sadly, this approach has inherent
Intel Memory Products, 2111 NE 25th, Hillsboro,. OR
faults. Because refresh is derived from microprocessor
97123. He is responsible for iRAM applicatiens.
timing, any operation that suspends or stretches the
Mr Fallin has a BSEEfrom Oregon State University:
timing must be carefully analyzed to ensure that it does
not violate system refresh timing. Examples of such
Joseph P. Altnether i~ the technical marketing
time stretching operations are extended wait states, hold
manager at Intel Memory Products and is involved in
operations in direct memory access, or the single-step
the technical marketing of Intel iRA Ms. Mr Altnether
operations important in system debugging. Moreover,
has a BSEEfrom St Louis University.
placing the burden of refresh on the microprocesso'r can
reduce processor performance by suspending operation
to service memory refresh.
William fl. Righter is also an. applications engineer at
Another technique for refresh control is to incorpoIntel Memory Products. He is responsible for the
rate most of the refresh mechanism on the RAM chip,
. graphics applications of dynamic RAMs. Mr Righter is
currently working on a BSEEfrom the University of
leaving the most difficult portion-the arbiter-to the
Portland..
system designer. This type of RAM is known as a

by John J. Fallin,

COMPUTER DESIGN/March 1983

3-184

pseudo- or quasi static RAM. Statistical techniques or'
special features of a particular central processing unit
(cpu) may be used to accomplish refresh, though it is
not always guaranteed. The system must be thoroughly
analyzed to ensure proper refresh timing.
. The third memory refresh method incorporates all of
the memory control logic, including arbitration logic,
into the RAM chip. Thus, all DRAM cell control is contained on the same piece of silicon, creating a complete
integrated memory system on a chip. This concept is
called an integrated RAM (iRAM.) Combining the best
features of dynamic and static RAM, the iRAM satishes
the ideal microprocessor memory requirements-a
DRAM storage cell for low cost, a Joint Electron Device
Engineering Council 28-pin package configuration conforming to universal flexibility standards, and ease of
use because of onchip control. (See the Panel.)
Intel's 8k x 8 iRAM contains all the elements needed
for complete memory control. Recognizing the need for
both synchronous and asynchronous refresh, Intel
offers the 2187 iRAM with synchronous, refresh for
special applications and the 2186 with asynchronous
refresh for general purpose designs. With onchip
refresh, the 2186 needs no external stimulus or control.
As a result, memory is autonomous; like an SRAM it can
be left alone with power applied and still retain data.
Any operation that suspends or stretches the system
timing has no effect on refresh operation. However,
because refresh is asynchronous with' the microprocessor, a memory request can occur during a refresh
cycle. In this case, the iRAM signals the system microprocessor that a delay will occur in the cycle.

Device operation
The 218612187 performs four types of cycles: read, write,
false memory, and refresh. It is important to note that
chip enable (CE) is an edge-triggered, not a leveltriggered, input. On the 2186/2187, an access cycle is
requested for every high to low transition of CEo Care
. must be taken to ensure that a new access cycle is not
requested before the previous cycle is completed. This
would violate memory cycle time (TELEL) arid would
jeopardize data integrity. A minimum precharge (CE
high time-TEHEL) must also be guaranteed. The violation of CE high time would most likely occur in systems
where noise spikes can occur, on chip enable.
Functioning like a clocked static RAM, iRAM addresses
are latch~ off the external address bus on the falling
edge of CEo This feature is useful in many designs
because it saves the designer one or two transistortransistor logic packages. In contrast to the trailing edge
write of the SRAM, the iRAM requires a leading edge
write. Further, the iRAM permits three different types of
access cycles. Depending on the'active time of CE and its
relation to output enable (GE) .or write enable (WE), a
long mode cycle, a pulsed mode cycle, or a false
memory cycle (FMc) can be performed.
. A Ion.!.mode cycle is similar to a fully static RAM cycle'
m that CE remains valid throughout the entire cycle. In
the pulsed mode cycle, the iRAM operates as a clocked
static RAM an~CE is 'active only at the beginning of the
cycle. When CE becomes active, without an OE or WE
the iRAM performs an FMC and terminates on the risin~

edge of CE. This is useful during byte write operations
of I.6-bit microprocessors. In this case, a 16-bit word is
selected (two iRAMS), and only one receives a write pulse
to perform byte write. The other selected iRAM performs an FMC .
~ssuming a refresh is not in progress when the 'cycle
begms, an access cycle is initiated on the high to low
transition of CE. After activating CE, addresses are
latched from the external bus and data are presented to
the bus. Data will remain at the bus as' long as OE
remains active, independent of the state of CE.

Any operation that suspends or
stretches the system timing has no
effect on refresh operation.
I[ a refresh cycle is in progress at the time CE goes
low, a deferred cycle occurs. In this case, ready (RDY)
~l respond by going low within a given time (TELRL) of
CE going low. After the refresh cycle and part of the
access cycle complete, RDY will return to a high state. At
a specified time after this (TRHQV), valid data will
become available at the data input/output (110) outputs.
It should be noted that DE can remain active for an
unlimited period of time, and data will remain on the
bus even though internal refresh cycles continue to be
performed. This allows operation in systems using
single-stepping hardware debug, since wait states can be
inserted at will. RDY does not respond under these
'
conditions.
For the sake of clarity, assume that a refresh cycle is
not in progress at the time of CE's falling edge. A write
cycle begins in the same way as a read cycle, with
addresses latched on the falling edge of CE. For a pulsed
mode, WE must go low within a specified time of the
falling edge of CE (TEL wL). If this specification time is
not met, an FMC occurs and thus, no write. For a long
mode, TWLEH must be met to ensure a write given setup
time before (TDVWL) and a given hold time (T»'LDX)
after the leading edge of WE.
I[ a refresh cycle is already in progress at the onset of
a write cycle, the RDY will respond at a given time
(TELRL) after CE's falling edge. Data will still be latched
into the device on the falling edge of WE, but the actual
write to the array will not occur until after the refresh
cycle is completed. RDY responds during write cycles to
prevent cycle timer (TELEL) violations. As in a read
cycle, CE and WE can remain active for an indefinite
period to accommodate single-step type operation. An
FMC occurs when CE becomes active but neither OE nor
WE becomes active. An FMC is a valid mode of operation
and also acts like a row address strobe (RAS) only
refresh, in which the row selected by the seven external
row addresses is refreshed.

Internal vs external refresh
The 2186 internal refresh is completely automatic
requiring no external stimulus; an internal timer provide~
refresh requests. If an access cycle is requested during a
refresh cycle, the 2186 will respond by outputting a RDY
low. For applications requiring maximum performance,

COMPUTER DESIGN/March 1983

3-185

the 2187 allows,external generation of refresh signals. A
high to low transition on the, refresh enable (REFEN)
input of the 2187 will initiate a refresh cycle. After
starting a refresh cycle, one cycle time (TELEL) must be
, allowed before attempting another access or refresh

cycle. Deferred access cycles are not allowed on the 2187,
as it has no arbitration circuitry. If REFEN is held low
for at least one tirper period, the internal timer will
begin to time out, and the 2187 will maintain refresh with
'
no outside intervention.

Inside the iRAM
Included in the 5-V iRAM device are a dynamic array, I
an arbiter, a refresh address counter, and, a refresh
I 00 TO 1/07
timer along with complete control and precharge circuitry. The 2187 differs from the 2186 only in the
w--~----__-------1-----r::::~
refresh timer and arbiter control circuitry. The diagram illustrates the interrelation of these iRAM
m--------------------~L;:::;J
elements.
'Oy-----------,
Arbiter
The arbiter that determines the priority sequence of
two or more. asynchronous inputs is the most significant eleme')t of the 2186 internal refresh circuitry. In
the 2186, the two inputs to the arbiter are an external
access cycle request and an internal refresh cycle
request. When either of these requests is made, the
arbiter decidek whether the cycle will proceed immediately or be delayed. For example, if an access cycle
is .in progress at the. time of an internal refresh
request, the refresh cycle will be delayed until after
the access cycle is completed. Conversely, if an
access cycle is requested while the 2186 is performing a refresh cycle, the access cycle will be
delayed. Here the 2186 will respond with a RDY low
output, instructing the device that more time must be
allowed. In the limit, both cycle requests can occur
simultaneously. Therefore, arbitration becomes necessary along with the simple state gating as outlined.

u---------1

iRAM Pin and Signal Definitions
Description/Function
Address inputs; These inputs provide

Array
The memory array, designed with direct random
access memory (DRAM) storage cells, is fabricated
using an N-channel double-layer polysilicon gate process. The array features polysilicon word lines and
folded metal, bit lines that provide high common
mode rejection.

the addresses needed to select one
of 8192 bytes. Addresses appearing
on these inputs afe latched into the
device on the high to low transition

of
1100 to 1/07

Refresh timer
Refresh peripheral circuitry is included on the device
to preserve the integrity of the data in the DRAM array.
A refresh timer provides refresh cycle requests at
appropriate intervals; The tim'er is designed to track
with both process variations and temperature so as
to guarantee proper refresh over all specified ranges.

Chip enable input. A high to low
transition on this pin latches
addresses and initiates an access

cycle.
Output enable input, During a read
cycle this input turns on the data

output buffers.

Row address counter
When the internal refresh cycle is granted, refresh
addiesses are'provided by a refresh address counter.
This counter contains the 7 -bit address of the next tROY
(2186 onlyl
'row to be refreshed and is incremented after each
refresh cycle. Cuntrol' logic within the peripheral circuitry handles the multiplexing of external memory
addresses and refresh addresses during appropriate ..J.REFEN
(2187 only)
cycles ..
Device pinout
The 2186/2187 comes in Joint Electron Device Engineering Council compatible 28-pin socket, Pin 1
(labeled "eNTRl") becomes the RDY output on the
2186, or the REFEN input on the 2187. Pin functions are,
described in the Table,

cr,

Data input/output. These bidirectional pins receive data to be written
to the device and output data during
a read cycle,

Write enable. input, Data are latched
into the device on the leading

(falling) edge of this signal.
This output becomes active to sig-

nify a delay in the cycle. It is open
drain, allowing the wire DRing of
several 2186 ROY outputs,
This input allows for external refresh
control. A high to low transition of

REFEN causes a refresh cycle to be
initiated, Holding REFEN low causes
asynchronous timer operation.

This input supplies operating voltage
to the device . Vee is specified at
5V±10%.

GND

Ground input for the device.

CDMPUTER DESIGN/March 1983

3-186

After REFEN returns high from this state, a minimum read only memory (ROM) or erasable programmable
amonnt of time (TRFHEL) must be allowed before the read only memory (EPROM) during system debug stages.
Following are applications that exemplify the technext falling edge of CE or REFEN in order to complete
any refresh cycles initiated by the timer. This mode of niques for interfacing the asynchronous 2186 and the
operation is called power-down refresh. The 2187 also 'synchronous 2187 iRAMs to various microprocessors.
supports a single-step mode of operation, which is Although the designs can be simpler, additional circuitry
accomplished by strobing REFEN low after an access is included to provide memory site compatibility with
cycle is started and then holding it low. REFEN can be SRAMS and EPROMs.
kept low indefinitely and data integrity guaranteed.
With REFEN held low, data remain valid on the 110 pins 5·MHz 8088 processor application
as long as OE remains active, even while refresh cycles TheJirst example involves as-MHz 8088 microprocessor
configured to a bank of 2186 iRAMs. It runs in the maxiare being performed.
Three requirements must be kept in mind when mum mode without wait states for normal memory'
building microprocessor memory systems with iRAMs. access cycles, except when RDY is activated due to interThe first is the need for a stable CE because the active nal refresh. The schematic diagram is shown in Fig 1.
low transition of CE latches addresses into the iRAM. The iRAM chip enable circuit is a simple cross-coupled
Also, there is a minimum specification between transi- latch that provides an active low enable signal (ii) syntions of CE (TEHEL) to ,allow for proper precharge of . chronized with address latch enable (ALE). This enable
internal dynamic circuitry. The second requirement is signal, along with latched status bit S2, is used to enable .
the need for valid data at the memory device when the the 74S138 address decoder to provide stable chip enable .
WE line is activated. This is a necessity since the iRAMs signals (CEO to CE7) to the 2186 iRAMS. The memory write
write data into the array on the leading edge of the write control (MWTC) output from the 8288 bus controller propulse. The third consideration is compatibility with vides for both leading and trailing edge write conditions.
The basic operation of 'the CE circuit is as follows:
SRAMs. In particular, the design should allow for the
trailing edge write OfSRAMs. This permits using SRAMs early in the CPU cycle, ALE goes high, then low, clearing
as second source chips, or allows the iRAM to replace the cross~coupled latch and driving Ii high. E remains

, Fig 1 Schematic for iRAM use with 8088 microprocessing unit running in maximum mode. To
ensure proper startup, all iRAM control inputs ,must be inactive for 100 ".S after VC;c reaches spec,
COMPUTER DESIGN/March 1983

Fig 2 Schematic for iRAM use with 8086 microprocessing unit operation in minimum mode. NAND
latch in processor's WR line ensures adequate delay of data to iRAM as well as supplying trailing
edge WR signal required by conventional &RAMS.

high at least as long as ALE holds the clear condition of
the latch. Due to the skew of the falling edge of ALE
with the system clock, two possible decoder enable timing
sequences exist. The first occUrs when ALE returns to a
low state before the falling edge of the system clock. In
this case., the latch remains cleared and E remains high.
On the falling edge of the system clock, the latch is set,
driving E low and enabling the decoder (depending on
the state of S2). The other timing sequence occurs when
ALE goes low after the falling edge of the system clock.
In this case, when ALE goes low, the E signal is immediately driven low as a result of the system clock (low)
input on the "set" side of the latch. The memory cycle
completes and early into the next cycle when.ALE goes
high, E returns to a high siate. This clearing action
occurs independently of the,state of the clock.
The, net result is the enabling of the 74S138 decoder
after its address inputs have stabilized. Thus, a transientfree chip enable is supplied to'the iRAMS. The balance of
t~e memory system is wired in a straightforward manner.
The DE signal for the memory array is connected directly
to the read control (RD) signal of the 8088 processor.
Bidirectional data lines of the memories are connected
to the processor's ADO to AD7 lines. CPU addresses are
latched by the 74S373s two gate delays after the falling
edge' of ALE. Although the iRAMs do not require the
address latches, they are included for completeness. A

typical system needs to latch the addresses from the
multiplexed bus for interfacing to SRAMs, EPRDMs, and
so on. The address lines feed the memory array via the
74S373 flow-through latches. All of the RDY lines of the,
memory array connect to a RDY input of the 8284A clock
generator in an DR configuration. A 51O-il pullup
resistor is used for stability.
Note that S2 is latched into a 74LS74 flipflop on the
rising edge of ALE. This is important because, during
certain CPU operations such as the execution of the halt
instruction, the status bits are not guaranteed to remain
valid until the falling edge of ALE. To guarantee proper
power-up of the 2186, all control inputs must remain
inactive for 100 JiS after V cc reaches specification. This
is accomplished by tying RESET to the clear input of the
MilO flipflop. A pullup resistor on the OE is also required
because the RD line on the 8088 goes into a high impedence state during RESET.

iRAMS in an 8086 based system
The interface requirements for an 8086/2186 system (Fig 2)
are similar to those for an 8088. The CE generation circuitry consists of two JK flipflops, arranged as a 4-state
sequencer. This sequencer makes its first transition on
the rising edge of ALE, when sequencer output A is set.
On the next falling edge of the system clock, sequencer
output Bis set, enabling the 8205 decoder if the cycle is a'

CO,MPUTER DESIGN/March 1983

3·188

memory access (MilO also gates the decoder). After one
more clock cycle, output A is reset,causing output B to
be reset on the fourth clock cycle. When output, B is
reset, the CE decoder is disabled, causing the CE to the
2186 to return to a high state. With this arrangement, CE
is low for only two processor T st,ates, allowing a' CE
, high time of at least two T states. This relatively long
deseIect time is important in l6-bit systems where a 2186.
could receive a CE but no OE or WE. This preceding condition would cause a false m~mory' cycle to occur, in
which case an extended CE high time is required because
TEHELF is greater than TEHEL.
'
For an 81186 operating in minimum mode, data output
during a write cycle is not guaranteed to be valid at the
falling edge of WR. To satisfy the leading edge write
requirement oethe 2186, the'leading edge of WR needs to
be delayed until data out is valid. This' can easily be
a:ccomplished through the use of a cross-coupled NANO
latch, which also provides the trailing edge write needed
for SRAMs. This delayed WE is then steered to either one
or both devices in the 16-bit word by oRing WE with,
either AD or bus high enable (BHE). This allows for
either word or byte writes. If wait states are needed, the
ROY outputs of the 2186 can be routed back to the RDY
input of the 8284A clock chip. Because the ROY outputs
are open drain, a 510-0 pullup resistor is required.

ROVI----LJ:::::~---------ROV
74L500

Fig 3 Additional circuitry required for to-MHz 8086
microprocessing unitliRAM operation with one wait state.

By adding a single AND gate to the 8086interface (Fig 3)
2186 can be run in one wait state IO-MHz 8086 system.
, Upon going high, ALE causes the flipflop driving A to be
set, forcing Alow. After a I-gate delay, ROY I is asserted.
On the next falling edge of clock after ALE goes high,
the flipflop driving A can now be reset on the next falling edge of clock, which occurs at the end of T2.
This arrangement ensures that ROY! will remain low
for the time frame required to insert at least one wait
s'tate. If the 2186 responds to this access with a ROY low

Fig 4 Interface circuitry required for iRAM operation with 5-MHz 801~ microprocessing unit/This '
system, based on popular iAPX 86 family of components, provides userS witb programmable memory
Chip selects for blocked memory applications.
COMPUTER DESI&I/March 1983

3-189

condition, the trailing edge of ROYI will be pushed out
to insert more wait states as nee'ded. The number of wait
states that can be inserted will never exceed six-assuming
a maximum ROY low time of 575 ns.
Fig 4 shows the circuitry required to interface the 2186
with Intel's 80186 high integration 16-bit processor. The
80186 is an integration of '10 common iAPX 86 components, including an enhanced 8086-2 CPlJ, a clock generator, a local bus controller, and an interrupt controller.
The clock speed of this configuration is 5 MHz. The
, 80186'S bus structure is ml!ch like that of the 8086, but
there are some useful additions, including programmable, memory chip select (MCS) outputs. These outputs
can be programmed to become active for a user-selected
block of memory. In Fig 4, one offour available midr,ange Mcss'would be programmed to become active iii
the memory space allocated to/ the iRAM. This MCS
signal is then used to initiate a count sequence with the
two JK flipfiops. The two flipfiops' outputs provide
both the CE and the properly positioned WE (for leading
edge writes) to the iRAMs.

FMCS, in which the iRAM receives a' CE but no OE or
WE, will occur any time a single byte write occurs. If this
is the case, the CE high time requirement becomes
somewhat longer, than 'that -required for a read or write
cycle, The CE circuitry' used was seh"cted with this consideration in mind because of the long CE high time it
guarantees.

Synchronous iRAMs in an 8088 system
One way to create a synchronous design using the 8088,
operating in maximum mode with the 2187 iRAM, is to
use a status decoder to generate a refresh signal during
an opcode fetch cycle. The follo~ing example assumes
that the 2187 iRAM is used for data store only, so that the
iRAM can be sent a refresh strobe during the time the
8088 is executing an instruction fetch fr<;>!J1 some other
portion of memory (ie, EPROM. ROM). It also assumes
that opcode fetches occur often enough to meet the 128
refreshesl2-ms refresh specification.
-In the circuit shown in Fig 5, it is evident that the 2187
and the 8088,are interconnected with a minimal amount

1o-~'R""AMa2r------I CE
iRAM3

I---'--l RESET
8088

. -_ _ _ _......:;A:::.O.:.:TO"'A:.::12=--_---.,_ _-v' 11/00 TO 1/07

Fig 5 System diagram of 2187/8088 synchronous system. iRAM refr~h occurs during 8088 itistruction
fetch cycle and is generated by external status decoder. Minimal transistor-transistor logic interface
'
circuitry is required.
COMPUTER DESIGI/March 1983

3-190

Combining memory and control
together on a single piece oj silicon ...
satisjies all the requirements jor
microprocessor memory.
of transistor-transistor logic interface circuitry. The
decoded 8088 signal MI is connected to the REFEN input
of the iRAM. This connection generates a refresh strobe
to the 2187 every time the 8088 performs an opcode fetch.
The 8288 bus controller generates memory read commands· and memory write commands that are properly
timed for alL memory requirements. Thus, these signals
may connect directly to the WE and OE control lines of
the iRAM without special conditio\ling circuitry. The
8-bit multiplexed address-data bus of the 8088 is connected directly to the 1/0 0 to 7 lines of the iRAM . The
low order addresses AD to A7 are latched by ALE at the
74LS373 latch and, together with lines A8 to A12, form
the iRAM device address.
The MilO signal is status bit S2. It i"s latched by ALE
and is used as·one of the enable inputs to the iRAM chip
enable decoder. The other decoder enable input is synchronized to ALE, providing a properly timed signal that
ensures a stable CE to the i RAM. The decoder is disabled
on the rising edge of ALE. However, due to the skew of
. the falling edge of ALE and the system clock, two slightly
different enable timing sequences can occur. If ALE goes
low at or after the falling edge of the clock, the E en.able

COMPUTER DESIGI/March 1983

line is immediately activated and enables the decoder.
Note that when RESET is low, REFEN will be forced low.
This guarantees proper 2187 power-up. This circuit runs
at 5 MHz without wait states.
Combining memory and control together on a single
piece· of silicon, the iRAM satisfies all the requirements
for microprocessor memory. Its ease of use, flexibility,
and low cost make it an attractive memory alternative.
By using it in some of the applications demonstrated,
engineers will find that the iRAMcan help them meet the
majority of both present and future memory system
design needs.

3-191

2114A
1024 X 4 BIT STATIC RAM
2114AL·1

I
I

Max. Access Time (ns)

Technology
• HMOS
Low
Power;
High Speed
•
• Identical Cycle and Access Times
• Single +SV Supply ±10%
• High Density 18 Pin Package
Static Memory - No
• orCompletely
Timing Strobe Required

2114A·4

2114A·5

Directly TTL Compatible: Air Inputs
• and
Outputs

C~ock

•

Data Input aind Output Using
Three-State Outputs

•

Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range

Commo~

The Intele 2114A is a 4096-blt static Random Access Memory organized as 1024 words by 4-bits using HMOS, a high performance MOS technology. It usas fully DC stable (static) circuitry throughout, In both the array and the decoding, therefore it
requires no clocks or refreshing to operate. Data access is particularly simple since address setup times are not required. The
da~ Ii read out nondestructlvely and has the same polarity
the Input data. Common input/output pins lire provided.

The 2114A Is designed for memory applications where the high performance and high reliability of HMOS, low cost, large bit
storage, and simple interfacing are Important design objectives. the 2114A is placed in an 18-pln package for the highest
possible denSity. .
. ' .
It Is Qlrectly TTL compatible in all respects: inputs, outputs, and a single +5V supply. A separate Chip Select (CS) lead allows
easy selection of an Individual package when outputs are or-tied.
.

MEMORY ARRAY
tl4ROWS
tl4CDLUMNS

110,

Ao
At:

110.

PIN NAMES
ADDRIiSS INPUTS
WRITE ENABLE
CHIP.ELECT
S
110,-110. DATAINPUTIOUTPUT

Act-A.
WE

.0 ..PIN NUMIIERS

V"" POWER (+5VI
GNDGROUND

INTEL COAPIlRATlON ASSU"ES NO RES~SIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBOOIEO IN AN INTEL PIIOOUCT NOOTHER CIRCUIT PATENT LICENSES ARE IMPLlEO.
~IIfTELCORPORATION.I977.1979
.
, . .
OECEMBER 1979
.

2114A FAMILY
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias ••••••..•••••••••• -10·C to BO·C
Storage Temperature .••••.•••••••.••.••. -6S·C to lS0·C
Voltage on any Pin
With Respect to Ground .................. -3.SV to +7V
Power Dil!sipation ................ '................. 1.0W
D.C. Output Current; ..•.••••....•••••. ; .••.•••••.•• SmA

·COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the devlc •.
This ~8 a stress rating only and functional operation ofthe davlc.
,at these or any other conditions above thosa Indicated In the
operational sections of this specification is not Implied. EIfposur, Is not implied. Elfposure to absolute m8lCimum rating
conditions for elCtended periods may affect device reliability.

D.C. AND OPERATING CHARACTERISTICS
TA =

unless otherwise noted

' PARAMETER

2114AL-l/L-2/L-3/L-4
Min. Typ.i 11 Max.

Min.

2114A-4/~S'
Typ.lll Max.

CONDITIONS

UNIT

IILlI

.Input Load Current
(All I nput Pins)

CS = V'H
Vila = 0 to 5.5

Icc

Power Supply Current

rnA

Vee = max. 1110 =.OmA.
TA = DoC

Output Short Cireu'it
Current'

NOTE: 1. Typical values are forTA =25°C and Vcc =5.0V.
2: Duration not to exceed 1 second.

LOAD FOR TOTO AND TOTW
+5V

CAPACITANCE
TA = 2S·C. f = 1.0 MHz
SYMBOL

TEST
Input/Output Capacitance

NOTE: This perameter is periodically ,,~pled and noi l,o~% tested.

A.C. CONDITIONS OF TEST
Input Pulse Level& .•...••••••••••.•••..••...•.•••.•...• '•••.... , ..•..• O.B Volt to 2.0 Volt
Input Rise and Fall Times •..•.•.•...••..•..•••••••••••...•••.••••.....•• ; •.••.. 10 nsec

DOUT

5pF

Input and Output Timing Levels .... , .. . .. .. .. .. . .. .. .. .. .. . .. .. .. . ... 0.8 Volts to 2.0 Volts
Output Load ......................................... , ...... 1 TTL Gate and C L = 100 pI'

Chip Selection 10 OutpulValid

lex 13)

Chip Seleclion 10 Outpul Active

Outpul Hold from
Address Change

Outpui 3-stale from Deselection

l3 )

± 10%. unless olherwi!le noled.

TA = O·C 10 70·C. Vee = 5V

WRITE CYCLE (2)
2114AL.1
PARAMETER

Output 3-state, from Write

tow

Data to Write Time Overlap

Data Hold from Write Time

NOTES:
1. A Read occurs during the overlap of a low CS and a high WE.
2: A Write occurs during the overlap of a low CS and a low WE. tw Is measured from the latter of Cs or WE going low to the earlier of
3. Measured at ±500 mVwith 1 ,TIL Gate and C L =500 pF.
'

WAVEFORMS,
READCYCLE®

ADo.E" -,...11\._ _ _ _ _ _ _ _ _ _+_"1'-___

~UT ----~-------~~~::~

1-'0'::1

NOTES:

DOUT

3. Wlls'!!!ph for a Read Cycle. .
,
4. If the CS low transition occurs simultaneously with the WE IO\"
transition. the output buffers remain in a high impedance state.
5. Wl must ,be high during all address transitions.

2114A FAMILY
TYPICAL D.C. AND A.C. CHARACTERISTICS
NORMALIZED ACCESS TIME VS.
SUPPLY VOLTAGE

NORMALIZED ACCESS TIME VS.
AMBIENT TEMPERATURE

NORMAUZED ACCESS TIME VS.
OUTPUT LOAD CAPACITANCE

NORMAUZED POWER SUPPLY CURRENT
VS. AMBIENT TEMPERATURE
.2

OUTPUT'SOURCE CURRENT
VS. OUTPUT VOLTAGE ,

OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE
80

2115A, 2125A FAMILY
HIGH SPEED 1K X 1 BIT STATIC RAM
2115AL,2125AL

• Pin Compatible To 93415A
(2115A) And 93425.A (2125A)
• Fan-Out Of 10 TTL (2115A Family)
-- 16mA Output Sink Current

• Available in EXPRESS
- Standard Temperature Range
.....l. Extended Temperature Range
• Uncommitted Collector (2115A)
And Three-State (2125A) Output

• Low· Operating Power Dissipation
--Max. 0.39mW/Bit (2115AL, 2125AL) • Standard 16-Pin Dual In-Line
\

Package

• TTL Inputs And Outputs

The Intel® 2115A and 2125A families are high-speed, 1024 words by 1 bit random access memories. Both open collector
(2115A) and three-state output (21'25A) are available_ The 2115A and 2125A use fully DC stable (static) circuitry through,out - in both .the array and the decoding and,therefore, require no clocks or refreshing to operate. The ~ata is read out nondestructively and has the same polarity as the input data.·
.
The 2115AL/2125AL at 45 ns maximum access time and the 2115AL-2/2125AL-2 af 70 ns maximum access time-are fully
compatible with the industry-produced 1 K bipolar RAMs, yet offer a 50% reduction in power of their bipolar equivalents.
The power dissipation of the 2115AL/2125AL and 2115AL-2/2125AL,2 is 394 mW maximum as compared to 814 mW
maximum of their bipolar equivalents. For systems already designed for' 1K bipolar RAMs, the 2115A/2125A and the
2115A-2/2125A-2 at 45 ns.and 70 ns maximum access times, respectively, offer complete compatibility with a 20% reduction
in maximum power dissipation.
.
.
The devices are directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. A separate select (CS) lead
allows easy ~election of an individual package when outputs are OR:tied.
The 2115A and 2125A families are fabricated with Intel's N-channel MOS Silicon Gate Technology.
PIN CONFIGURATION

PIN NAMES
CHIP SELECT
ADDRESS INPUTS
WRITE ENABLE
DATA INPUT

CONTROL
LOGIC
(SEE TRUTH
TABLE)

TRUTH TABLE
INPUTS
CS WE
H
X
L
L.
L
L
L
H

2115A FAMILY 2125A FAMILY :

NOT SELECTED
WRITE "1"

INTEL CORPORATION ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBOOIED IN AN INTEL PROOUCT. NO OTHER CIRCUIT PATENT LICENSES ARE IMPLlEO ..
-INTEL CORPORATION. 1977, 1979
3.196
NOVEMBER. 1979

2115A, 2125A FAMILY
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ............. -lOoC to +B5°C
Storage Temperature .............. -65°C to +150°C
All Output or Supply Voltages .......... -0.5V to +7V
All Input Voltages . . . . . . . . . . . . . . . . . ':"0.5V to +5.5V
D'.C. Output Curre~t . . . . . . . . . . . . . . . . . . . . . 20 mA

'COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress ra"ting only and functional operation of the device at these or
at any other conditions above those indicated in the operational"

sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device
reliability •

D.C. CHARACTERISTICSI1,21
Vcc = 5V ±5%, T A = O°C to 75°C
Symbol

2115A Family Output Low Voltage

0.45

IOL",,16mA

VOL2

2125A Family Output Low Voltage

VCC =' Max., VIN = 0.4V

VCC = Max., VIN = 4.5V

2115A Family Output Leakage Current

0.1

100

JJ.A

Vcc = Max., VOUT = 4.5V

2125A Family Output Current (High Z)

0.1

JJ.A,

Vcc ':' Max., VOUT = 0_5V/2.4V

Vcc= Max.

IIcEXI
lIoFFI

2125A Family Current Short Circuit
to Ground

IOS[31
VOH

Family Output High Voltage

ICC

Power Supply Current:
IcC1 : 2115AL, 2115AL-2, 2125AL,
2125AL-2

NOTES .

-100
2.4

ICC2: 2115A, 2115A-2, 2125A, 2125A-2

100

125

10H = -3.2 mA

All Inputs Grounded, Output
Open

1. The operating ambient temperature ranges are guaranteed wiJh transverse air flow exceeding 400 linear "feet per minute and a two minute
warm-up.· Typical thermal resistance values of the packag~ at maximum temperat~re are:

8JA (@400fpM air flowl = 45°C/W
8JA '(still aid ='60°C/W
8JC = 25°C/W
2. Typical limits are at Vee = 5V, TA = +25°e, and maximum loading.
3. D.uration of shQrt circuit current should no~ exceed 1 second.

3·197

2115A, 2125AFAMILY
2115A FAMILY A.C. CHARACTERISTICS[1.21 Vee = 5V

±~%. TA = O°C to 75°C

READ CYCLE
2115A Limits 2115AL-2 Limits 2115A-2 Limits
2115AL Limits
Min. Typ. Max. Min. Typ. Max~ Min. Typ. Max. Min. Typ. Max. Units

Chip Select F:ecovery Time

Previous Read Data Valid Atter
Change of Address

1'0

WRITE CYCLE
Symbol

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Units

Data Set·Up Time Prior to Write

-5

tWHD

Data Hold Time After Wri.te

Chip Select Set-Up Time

tWHes

Chip Select Hold Time

30pF
(INCLUDING
SCOPE AND
JIG)

_ _ _ _ _ _....,..._ _ _ __

! _ tAA _

DATA VALID

PROPAGATION DELAY FROM CHIP SELECT

tALL ABOVE MEASUREMENTS REFERENCED TO 1.5VI

3-198

•

90%

_1_ :__ .. _. ______ .: _\~_;..;.'..:.:'O%~_ _
I
I

2125 FAMILY A.C. CHARACTERISTICS[1.2)

Vee = 5V ±5%. T A =O°C to 75°C

READ CYCLE
Symbol

2125AL Limits
2125A Limits 2125AL-2 Limits 2125A-2 Limits
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Units

Chip Select to HIGH Z

tAA

Address Access Time

tOH

Previous Read Data Valid After
.Change of Address

10 -

WRITE CYCLE
Symbol

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min:

Test

tzws

Write Enable to HIGH Z

Data Set-Up Time Prior to Write

Data Hold Time After Write

Chip Select Set-Up Time

tWHes

Chip Select Hold Time

::;x
------------1;-i__
3.5Vp-~ ~. ~

\,,;_~_..;.;10%;;:...._ _

__ _ _ _ _ _ _ _ _ _ _ _

J)K""_________________________

---+--+-+. . . -'w- r--t--t--t--WE

-.-

PROPAGATION DELAY FROM CHIP SELECT

~~~-----.HIGHZ·L
.
twR

DouT

POUTBJ;)§;S%~~___
IALL ABOVE MEASUREMENTS REFERENCED TO 1.5VI

3-199

2115A, 2125A FAMILY
2125A FAMILY WRITE ENABLE TO HIGH Z DELAY
5V

WE
, WRITE ENABLE
7501l

DATA OUTPUT _ _-,"O_".;;.L';;.;V.;;.';..L

5pF

DOUT _ _ _
"I;..".;;.L';;.;V.;;.';..L_ _,

2125A FAMILY PROPAGATION DELAY FROM CHIP SELECT TO HIGH Z

r~-~,~7

DOUT I
DATA OUTPUT _ _ _
"O_"_L_'V_'_L_ _

tzxxx PARAM~TERS ARE MEASURED AT A DE~ TA.

OF O.SV FROM THE LOGIC lEVEL AND USING LOAD 1 )

2115A/2125A FAMILY CAPACITANCE* Vee 5V, f
SYMBOL

2125A Family
LIMITS
TYP.

CS = 5V, All Other Inputs =
Output Open

*Thls parameter IS periodically sampled and IS not 100% tested.

TYPICAL CHARACTERISTICS
ICC VS. TEMPERATURE
110

r-2.125A, 212SA-2 -:-

/2115A,2115A-2
2125A,2125A·2

'II"

ACCESS TIME VS. TEMPERATURE

V2115AL,2115Al.2
2125Al.2125Al.·2

o
10

2~'5AL'~'

211!A-2
212SAL·2,212SA-2

3·200

:::::::

2115AL,211SA
212SAL,2125A

2115H, 2125H FAMILY
HIGH SPEED 1K X 1 BIT STATIC RAM
MIx. T.u(nl)

• HMOS n Technology
• Pin Compatible to 93415A (2115H) and
934,25A (2125H)

• TTL Inputs and Outputs
• Single +5V Supply'
,

• Low Operating Power Dissipation Max. 0.53 mW/Bit (2115H-3, 2125H-3)
16~Pin

• Uncommitted Collector (2115H) and'
'Three~State (2125H) Output'
,

• 16mA Output Sink' Current,

• Standard

2115H:4,2125H.4

• Available in EXPRESS
- Standard Temperature Range
, ~ Extended Temperatur,e, Range

Dual In':Line,Package

The Intel® 2115H and 2125H families are high speed, 1024 words by 1-bit random access memories'fabricated witt)
HMOSIT, Intel's '1dvanced N-channel MOS 'silicon gate technology. Both open collector 12115H I and three-state output
(2125H,J are available. The 2115H and 2125'H' use fully DC stable I static I circuitry tllroughout -i.n both the array and. the
decoding and, therefore, require no clock,S or refreshing to operate. The data is read. out nqn~destructively and has the
same polarity as the input data.
'
,

HMOS ll's' advanced technology allows the production of the industry's fastest, low. power, 1K static RAMs.,.... offering
access times as low as 25ns.
HMOS IT allows the production of the 2115H/2125H families, fully compatible with the 1K Bipolar RAMs yet offering
substantial reductions in power dissipation. The power dissipations oi 525mW maxirTlU'm ,and 656mW maximum
'
compared to 814mw maximum offer red,uctions ,of 19% and 36% respectively.
The devices are directly TTL compatible in all respects:' inputs, outputs, and a single +5V supply, A separate s'elect I CS J
lead allows easy selection of an individual package when outputs'are (>A-tied.

CHIP SHECT
WRITE ENABLE

AoA, A2A3A(

INPUTS

~u,

LOGIC
(SEE TRUTH
TABLE)

OUTPUT
112!>H F AMll'V

NOT SELECTED
WRITE ·'0··

Intel Corporation Assumes No Respon81bllty for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied.

©rNTEL CORPORATION, 1980

3-201

inter

2115H/2125H FAMILY

ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias •••••.••••••• _1O°C to +8SoC
Storage'Temperature ••••••.•.••••• -6SoC,to +lS0°C
All Output or Supply Voltages • .' •.•• : ...

~0.S,ito+7V

All Input Voltages . • • . . . . • . . ' ..•••••

-l.SV to + 7V

D.C. Output Current ••. '••••• ,.' .• '...... ',' . : : 20 mA'

.,::"

,',

D.C. CHARACTERISTICS [1,2)
Vee,:, SV ±S%.

211SH Family Output Leakage Current·

los

212SH Family.current Short Circuit
to Ground,

VOH

Family Output High Voltage

Unit

0.4S
...

. Condition.
IOL = 16 rnA

0.8

-40'

Vee = Max •• V,N.= 0.4V

Vee = Max .• VO~T =4.SV

0,1

Vee = Max ... VOUT = 0:SVI2.4V

212SH Family Output Current (HighZ)

211SH/2SH Family Outp~tLow ~VolUig,e

V,H

o°c t07SoC

Symbol

'COMMENT: Stresses above those listed under "Absolute Maxi·
. mum Ratings" may cause permanent damage to ttle devics. This is a
stross rating only and functional operation of the device at these or
~t any other conditions 'above those indicated in the operational
sections of -this specification is not implied ..Exposure to absolute
maximum rating conditions for extended periods may affect device
reliability.
'

'2:4

4.SV

10H'= -S,2 rnA

Pow,er Supply Current:.

Icc

2115H-212125H-2
211SH-4/212SH-4

12S,

10C3: 211SH-3/212SH-3

125

rnA

1=:

All Inpilts Grounded. Output
.Open

NOTES.
1. The operating ambient temperature ranges are guaranteed with transverse air flow exce'eding 400 linear feet per minute.
2. Typical limits are at Vee = SV, T. = +2S0 C, and maximum loading.

2115H/2125H FAMILY

2115H FAMILY A.C. CHARACTERISTICS
READ CYCLE
2115H-3 Limits
Min.
Max.

2115H-2 Limits
Min.
Max.

Test

Symbol

2115H-4 Limit.
Min.
Max.

Chip Select Recovery Ti me

Address Access Time

tOH

Previous Read'Data Valid After
Change of Address

Data Set-Up Time Prior to Write

- ns

tWHD

Data Hold Time After Write

Chip Select Set-Up Time

tWHcs

Chip Select Hold Time

[1] These specifications are guaranteed by design and not production tested.

A.C. TEST CONDITIONS
Vee

--i....;;;-.;;-->r--}---- - - - - -- - __ :_~-;;;-;,..1:.:0%;::.._--

~~---------~~~~-----_;r~·:
--r
-= --; ~

.._ _ _ _ _ _ _ _ _ _ _ _ _ __

PROPAGATION DELAY FROM CHIP SELECT

(ALL ABOVE MEASUREMENTS REFERENCED TO 1.SV)

2125H FAMILYA.C. CHARACTERISTICS

Vee = 5V ±5%,TA =O'C to 75'C

READ CYCLE
Symbol

2125H·4 Llmlls
2125H·3 Llmlls
2125H·2 Limits
Min.
Max. Min.
Max. Min.
Max. Units

Tesl

tAcs

Chip Select Time

Chip Select to HIGH Z

IAA

Address Access Time

tOH

Previous Read Data Valid After
Change of Address

Write Enable to HIGH Z

Data Set·Up, Time Prior to Write

tWHD

Data Hold Time After Write

t WSA

Address Set·Up Time _

, ns
ns

Address Hold Time

twscs

Chip Select Set·Up Time

t WHCS

Chip Select Hold Time

[1]

tWHA

[1] These specifications are guaranteed by design and not production tested.

A.C. TEST CONDITIONS

All INPUT PULSES

T ---- 1_-_-_-_-------------------..... - - - - 90%
I
I
_:____________ _:-_=_....;1;,;0%;....._ _

~--------------------

Ao Ay

'DATA VALID
WE

PROPAGATION DELAY FROM CHIP SELECT

'L-""'--I-

f---- IWSCS"~

~UT";S~\....-.__

IALL ABOVE MEASUREMENTS REFERENCED TO 1.SVI

30pF
(INCLUDING
SCOPE AND

2125H FAMILY WRITE ENABLE TO HIGH Z DELAY

1ZWS r---;';GH-;
"'f
} O.5V

__
..;;.,O
...,:LE:..;V,;;;EL;;.,._ _

DOUT _ _',.:"..,;"L:.,;E,;;;VE:.,;L'--_-.J.

2125H FAMILY PROPAGATION DELAY FROM CHIP SELECT TO HIGH Z

DATAQUTPUl _ _..:"O_"L:;;;E..,;VE:;;;L_ _

O.5V

"1" LEVEL

OOUT

- - - = = - - ' \ I - } 0.5V
' - _ _ ~~~

DATA OUTPUT

(ALL tzxxx PARAMETERS ARE MEASURED AT A DELTA
OF O.5V FROM THE LOGIC lEVEL AND USING LOAD 1.)

2115H/2125H FAMILY CAPACITANCE*
SYMBOL

TEST

Vee= SV, f = 1 MHz, TA = 2SoC

211SH Family
LIMITS
TYP.

MAX.

212SH Family
. LIMITS
TYP.

All Inputs = OV, Output Open

Output Capacitance

CS = SV, All Other Inputs = OV,
Output Open

-This parameter is periodical IV sampled and is not 100.% tested.

3-205

intel®

2147H
HIGH SPEED 4096 x 1 BIT STATIC RAM '
2147H-1
35
180
30

Max. Access Time (ns)
Max. Active Current (mA)
Max. Standby Current (mA)

Pinout, Function, and Power Compatible to Industry Standard 2147

•

Direct Performance Upgrade for 2147

•

Automatic Power-Down

•
•

HMOS UTechnology
Completely Static Memory- No Clock
or Timing Strobe Required

•

High Density 18~Pin Package

•

•
•
•

Equal Access and Cycle Times
Single + 5V Supply
O.8-2.0V Output Timing Reference
Levels

Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range

•

Separate Data Input and Output

•. Three-State Output .

The Intel@ 2147H is a 4096·bit static Random Access Memory organized as 4096 words by 1·bit using
HMOS·II; Intel's next generation high·perf.0rmance MOS technology. It uses a uniquely innovative design
approach which provides the ease·of·use features associated with non·clocked static memories and the
reduced standby power dissipation associated with clocked static m~mories. To the user this means low
standby power dissipation without the need for clocks, address setup and hold times, nor reduced data
rates due to cycle times that are longer than access times.

es controls the power·down feature. In less than a cycle time after es goes high-deselecting the 2147H
-the part automatically reduces its power requirements and remains in this low power standby mode as
long as es remains high. This device feature results in syste'm power savings as great as 85% in larger
systems, where the majority of devices are deselected.
'
The 2147H is placed in an 1S·pin package configured with the industry standard 2147 pinout. It is directly
TIL compatible in all respects: inputs, output, and a single + 5V supply. The data is read ,out nondestruc·
tively and has the same polarity as, the input data. A data input and a separate three:state output are used.
PIN CONFIGURATION

MEMORV ARRAV
64ROWS .
MCOLUMNS

A,.
A"
DIN WE CS

Dour

PIN NAMES
Ao-A" ADDRESS INPUTS
WRITE ENABLE
CHIP SELECT
CS
DATA INPUT
D,N
DATA OUTPUT
DoUT

Vee POWER I+5VI
GND GROUND

TRUTH TABLE
~Wl

H
L
L

L
H

MODE
NOT SELECTED
WRITE
'READ

I I
OUtpUT

POWER

HIGH Z
HIGH Z
DoUT

STANDBY
ACTIVE
ACTIVE

Inlel Corporation assumes no responsibility tor the use of any circuitry other than Circuitry embodied
Intel Corporation, 1979.1980

3,206

an Intel product. No other CirCUIt palent licenses are Implied.
April. 1980

2147H
ABSOLUTE MAXIMUM RATINGS·

·COMMENT: Stresses above those listed under "Abso·
lute Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maxi·
mum rating conditions for extended periods may affect
device reliability.

Temperature Under Bias ............. -10·C to 85·C
Storage Temperature ............. - 65·C to + 150·C
Voltage on Any Pin
With Respect to Ground. . • . . • . . . . .. - 3.5V to + 7V
Power Dissipation ........................... 1.2W
D.C. Output Current ..... , ................... 20 rnA

D.C. AND OPERATING CHARACTERISTICS[1[
(TA= o·c to 70·C, Vcc = + 5'1/ ± 10%, unless otherwise noted.)

Symbol
IL
ILO

2147H-1, 2, 3
Min. Typ. Max.
0.01
1.0

Parameter
Input Load Current

(All Input Pins)
Output Leakage

0.1

2147H
Typ.l21

Min.

2147HL
Typ.l21 Max.
1.0
0.01

V,N = GND to Vee
CS = V,H • Vee = 5.5V
VouT=GND to 4.5V

CS=V,H
Vee = GND to Vee Min ..

Peak Power-On
Current

V"
V,H
VOL
VOH

Input Low Voltage
Input High Vollage
Output Low Voltage
Output High Voltage

Test Conditions

I
.1

Vee = Max.,

cs = V".
Outputs Open

CS= Lower of Vee or V1H Min.
-3.0
2.0

NOTES:
1. The operating ambient temperature range is guaranteed with transverse air flow exceeding 400 linear feet per minute.

2. Typical limits are at Vee = 5V, TA = + 2SoC, and specified loading.
3. A pull-up resistor to Vee on the CS input is required to keep the device deselected; otherwise, power-on current approaches Icc active.
Vee

A.C. TEST CONDITIONS

48011

Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Level (2147H·1)
Output Timing Reference Levels
(2147H, H·2, H·3; HL)
Output Load

GND to 3.0V
5 ns
1.5V
1.5V

DOUT - - -....._ - - .
30 pF
(lNCLUOING
SCOPE AND
JIG!

2550

0.8"-2.0V
See Figure 1

Figure 1. Output Load
. . . cc

CAPACITANCE[4[
Symbol

480n

(TA =25·C, f= 1.0 MHz)

Parameter

Dour - - -......- -..

NOTE:
4. This parameter is sampled and not 100% tested.

5 pF

Figure 2. Output Load for tHZ, tLZ. twz. tow

3·207

inter

2147H

A.C. CHARACTERISTICS
Read Cycle

Symbol

(TA = o·c t070·C, Vcc=

+ 5V

± 10%. unless otherwise noted.)

2147H.•
2147H·3
2147H·1
2147H·2
2147HL
Min. Max. Min. Max. Min. Max. Min. Max.

Chip Select Access Time

tOH
td2,3,7J

Output Hold from Address Change

Chip Selection to Output in Low Z

tHzI2,3,71

Chip Deselection to Output in High Z

tpu

Chip Selection to Power Up Time

tpo

Chip Deselection to Power Down Time

Chip Select Access Time

WAVEFORMS
Read Cycle No.

1[4,5)

ADDRUS.~·~~~~_~c~~~~~
•.

1--------'- <••· · - - - - - - - 1
1---.,.-- 'OH -----1
DATA OUT

"l~I- '- = =-'"=-~'-._C-S~-.,- - ~~-=-'-:-Rcl-------------1
-~t..,HIGH IMPEDANCE

_1 X X )!.r---.,.---------......----......

r'-.....,.....~.J 1"------------...,...-----JJo':,::::=::::-·'MPEDANeE

DATA OUT -----"-""""'=~---_,(

DATA VALID

::--~~~1.--so,,---------~-··-"~

NOTES:
1. All Read Cycle timings are referenced from the last valid address to the first transitioning address.
2. At any given temperature and voltage condition, tHZ max. is less than tLZ min. bbth for a given device and from device to device.
3. Transition is measured ± 500. mV from steady state voltage with specified loading in Figure 2.
.
4. WE is high for Read Gycles.
5. Device is continuou~y selected, CS = V'L. _
6. Addresses valid prior to or coincident with CS transition low.
7. This parameter is sampled and not 100% tested.
8. Chip deselected for greater than 55 ns prior to selection.
9. Chip deselected for a finite time that is less than 55 ns prior to selection. If the deselect time is 0 ns, the chip is by definition
selected and access occurs according to Read Cycle No. 1. Applies to 2147H, 2147HL, 2147H·3.

3-208

2147H
A.C. CHARACTERISTICS (Continued)
Write Cycle
2147H,
2147H·3
2147H·2
2147HL
2147H·1
Min. Max. Min. Max. Min. Max. Min. Max.

Chip Selection to End of Write

tAW

Address Valid to End of Write

Data Valid to End of Write

tOH
twZ(3)

Data Hold Time
Write Enabled to Output in High Z

tow(3)

Output Active from End of Write

WAVEFORMS
Write Cycle No.1
(WE

CONTROLLED~41

35
35
35
0
20
0
,20
10
0
0

45
45
45
0
25
0
25
10
0
0

55
45
45
0
25
10
25
10
0
0

70
55
55
0
40
15
30
10
0
0

Unit
ns
ns
ns
ns
ns
ns
ns
ns

ns
ns

ADDRESS

--~------------------------------~-------I-----,~--,--~

~- --,'.. ~---'---I-- .., ir------

-~ft:·:~·~t"~'---'-lDATA OUT

----------------------~

Write Cycle No.2
(CS

CONTROLLED~4)

- - - - - - - - - - - - t",c

'o.-~-'O"j
DATA IN VALID

f--- ..,---oJ

------------------------~---~I~__~H'~GH~'W~'O~~,,~
DATA UNDEFINED

NOTES:
1, If CS goes high simultaneously with WE high, the output remains in a high impedance state,
2, All Write Cycle timings are referenced from the last valid address to the first transitioning address,
3. Transition is measured ± 500 mV from steady state voltage with speCified loading in Figure 2.
4, CS or WE must be high durin'g address transitions.

2148H FAMILV
1024 x 4 BIT STATIC RAM
*2148H-2

Max. Access Time (ns)

Max. Active Current (mA)

150 .

*150

125

Max. Standby Current (mA)

• Improved Performance Margins

• HMOS· mTech~ology

• Automatic .Power-Down

• Common Data Input and Output

• Single + 5V Supply

• Three-State Output

• Completely Static Memory - No Clock
or Timing Strobe Required

• High Reliability Plastic or CERDIP
Package

, The Intel(l) 2148H is a 4096-bitstatic Random Access Memory organized as 1024 words by 4 bits Jsing HMOS III,
an ultra high-performance MOS technology. It uses a uniquely innovative design approach which provides the ease-of
use features associated with non-clocked static memories and the reduced standby power dissipation associated
with clocked static memories. To the user this means low standby power dissipation without the need for cloc~s,
add res:; setup and hold times,nor reduced data rates due to cycle times that are IQnger than'accesstimes.

CS controls the power-down feature. In less than a cycle time after.CS goes high - disabling the 2148H - the part
'automatically reduces its power requirements and remains in this low power standby mode as long as CS remains
high. This device feature results in system power savings as great as 85% in larger systems, where the majority
of devices are disabled. A non-power-down companion, the 2149H, is available to provide a fast chip select access
time for speed critical applications ..
The 2148H is assembled in an 18-pin plastic package configured with the industry standard 1K x 4 pinout. It is directly
TTL compatible in all respects: inputs, ouputs, and a single + 5V supply. The data is read out nondestructively and
has the same polarity as the input data.
• HM·OS is a-patent process of Intel. .
PIN CONFIGURATION

VO,-V04 DATA INPUT/OUTPUT

X NOT SELECTED H1GHZ STANDBY

Figure 1. Pin Configuratlon,Loglc Symbol,
Pin Names and Truth Table

w.~--~Jr----------------------~~--------~

Figura 2. 214BH .Block Diagram

... , ImprOved perrormance margins
The fc?lIowlng are trademarks of Intel Corporation Br1d may be used only to describe" Intel products: Intel, ICE, IMMX, iRMX, ISec. iSex, iSXM, MULT1BUS, Multichannel and MU~llMODULE.
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied In an Intel product. No other circuit patent licenses are Implied. Information contained
herein supercedes previously published ipecifications on these devices from Intel.
AUGUST, 1983

3.210

ORDER NUMBER: 230781-001

2148H FAMILY

ABSOLUTE MAXIMUM RATINGS·

• COMMENT: Stresses above those listed under "Absolute Maximum Ratings'" may cause permanent
damage to the device. This is a stress rating only and
functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.

Temperature Under Bias ........ -10°C to + 85°C
Storage Temperature CERDIP .. - 65°C to + 150°C
Storage Temperature Plastic .... - 65°C to + 125°C
Voltage on Any Pin with
Respect to Ground ............. - 3.5V to + 7V
D.C. Continuous Output Current ........... 20 rnA
Power Dissipation ......................... 1.2W

D.C. AND OPERATING CHARACTERISTICS'"
TA = O°C to'+ 70°C. Vee = + 5V ± 10% unless oiherwise noted.
2148H/H·3/H·2
(2)

Input Load Current (All Input Pins)

iw while RAS, is usedto execute RAS·only refresh cycles. Refreshing is accomplished by performing ~AS-only cycles, hidden refresh cycles, or normal read or write cycles on the 128 address combinations of
addresses Ao through As, during a 2 ms period.
BLOCK DIAGRAM
PIN
CONFIGURATION

AbORESS 1..uTS
COLUMN ADDRESS STR08E

ROW ADORESS STROBE
Vm

Ub 12' CELL
MEMORY ARRAY

Intel Corporalion'assumes ('\0 responsibility tor the use 01 any CirCUitry other than cirCUitry embodied

INTEL CORPORATION. 1982

3-219

ari"lnlel 'product: No other cirCUit palenlltcenses are Implied.

April. 1982
Order Number: 210425-001

,inter

2164A FAMILY

ABSOLUTE MAXIMUM RATINGS·

•COMMENT:
Stresses above those listed under "Absolute Maximum Rating"
may cause permanent damage to the device. This is a stress
rating only ,and functional operation of the device at these or at
any other condition above those indicated in the operational
sections of this'specification is 'no/ implied. Exposure to absolute maximum rating conditions. for extended periods may
affect device reliability.

Ambient·Temperature
Under Bias .................. -1O°Cto +80°C
Storage Temperature .. Cerdip - 65°C to +. 150°C
Plastic -55°Cto'+125°C
Voltage on Any Pin except VDD
Relative to Vss .................. - 2.0Vt07.5V
Voltage on VDD Relative to Vss .. ',' - 1,OV to 7.5V
Data Out Current ........... , .......... 50 rnA
Power Dissipation ...................... 1.0 W

D.C. AND OPERATINGCHARACTERISTICS[1]
TA= O°C to 70°C, VDD = 5V ± 10%, VSS ~ OV, ul'!less otherwise noted.

Input Load Current (any input)

/lA

VIN = Vss to Voo

IILOI

Output Leakage Current for
High Impedance State

10 '

/lA

Chip Deselected: CAS at VIH ,
DOUT = 0 to 5.5V '

1001

Voo Supply Current, Standby

1002

Voo Supply Current, RAS-Oilly
Cycle

1005

Voo Supply Current, Standby
Output Enabled

Notes

CAS and RAS at VIH

55,

2164A-15; tRC= tRCMIN

3
3

Voo Supply Current, Operating

1003

Test Conditions

2164A-20, tRC= tRCMIN

2164A-,15, IRC = tRCMIN

rnA

2164A-20, tRC = tRCMIN

CAS atVIL',RAS atVIH

VIL

Input Low Voltage (ali inputs)

..,.1.0

0.8

VIH

Input High Voltage (all inputs)

NOTES:
1. All voltages referenced to Vss '
2. Typical values are for TA = 25·C and nomi.nal supply voltages.
3. 100 is dependent on output loading when the device output is selected. Specified 100 MAX is measured with the output open.
4. Specified V,L MIN is for steady state operati!:>n. During trahsitions the inputs may overshoot to - 2.0V for periods not to exceed 20 ns.
5. Test conditio'ns apply c:mly for D,C.~haracteristics. A.C. parameters specified with a load equivalent t02 TTL loads and 100 pF.

CAPACITANCE[1]

NOTES:
1. Capacitance measured with Boonton Meter or effective,
capacitance calculated from the equation:

TA = 25°C, VDD = 5V ± 10%, VSS = OV,
unless otherwise noted.

C= lolt
olV
with olV equal to 3 volts and power supplies at nominal
levels.

3·220

2164A FAMILY

A.C. CHARACTERISTICS [1,2,3)
TA

=O·C to 70·C, Vee =5V ± 10%, Vss =OV, unless otherwise noted.

READ, WR[TE, READ·MODIFY·WRITE AND REFRESH CYCLES
Symbol
tRAC

;l164A·15
Max.
Min.
150
85
2
100
25
-20
30
65
85
. 150
0
20
0
25

Parameter
Access Time From RAS

c-AS Precharge Time (non·page cycles)

tCRP

CAS to RAS Precharge Time

tRCD

RAS to CAS Delay Time

Row Address Set·Up Time

tRAH

Row Address Hold Time

tASt:

Column Address Set·Up Time

tCAH

Column Address Hold Time

tAR

Column Address Hold Time to RAS

Transition time (Rise and Fall)

tOFF

Output Buffer Turn Off Delay

3
0

50
30

2164A·20
Min.
Max.
200
120
2
120
35
-20
35
80
120
200
0
25
0
30
110
3
50
0
40

,U"lt
ns
,ns

Notes
'4,5
5,6

ms
ns
ns
ns
ns

ns
ns
ns
ns
ns'
ns
ns
ns

READ AND REFRESH CYCLES
tRC

Random Read Cycle Time

Read Command Set·Up Time

tRCH

Read Command Hold Time referenced to

, tRRH

CAS

Read Command Hold Time referenced to FrAS

260
150
10000
85· ,,10000
0
5
20

330
200
120
0
5
20

'10000
10000

ns
ns
ns
ns

NOTES:
1. All voltages referenced 10 Vss.
2. An initial pause of SOO I'S is required after power up followed by a minimum of eight (8) initialization cycles (any combination of
cycles containing a RAS clock such as RAS·only refresh). 8 initialization cycles are required aflerextended perlodspf bias (greater
than 2 ms) without clocks.
,
'
3. A.C. Characteristics assume tT 5 ns.
, 4. Assumes that tACO S IACO(max). If tACO is greater than tACo(max) then t AAC will increase by the amount that tACO exceeds IACO(niax).
5. Load 2 TIL loads and 100 pF. "
,
6. Assumes.!RCo",tACO(max).
,
7. tACO(max) is specified as a referenc'e point only. If tACO is less than tRCO(max) access time is t AAC ' If tACO is greater ihan tACO(max)
access time is tACO + tCAC' tAc~(min) = tRAH + tAsc +. t~ + tT (tT'" 5 ns).
.
8. tT is measured between V1H(mln) and V1dmax).
9. Either tACH or tAAH must be satisfied.

3,221

intel

2164A FAMILY

A.C. CHARACTERISTICS (con't.)
WRITE CYCLE

Random Write Cycle Time

tRAS
tCAS'

CAS Pulse Width

'twcs

Write 'Command Set-Up Time

tWCH

Write Command Hold Time

tWCR
twp

Write Command Pulse Width

tRWL

Write Command to RAS Lead Time

tcwL

' Write Command to CAS Lead Time

260
150
85
-10
30
95
30
40
40
0
30
95

RAS Pulse Width
"

Write Command Hold Time to RAS

Data-In Hold Time to RAS

330
200
10000
120
10000
-10
40
120
40
50
50
0
40 .':.
120

Notes

ns
ns
ns
ns
,ns

ns
ns
ns
ns
lis
ns
ns

READ·MODIFY·WRITE CY~LE ,
t RWC

Read-Modify-Write Cycle time

tRRW

RMW Cycle RAS Pulse Width

tCRW

RMW Cycle CAS Pulse Width

NOTES:
10. Iwcs', lewD and t RWD arEr~pecified as reference points only. Iftwes:e:lwes(min) the cycle is an early write cycle and the data out
pin ~ill remain,high impedance throughout the entire cycle. If tewD:e: tewo(min) and tRWD:e: tRWD(min) the cycle is' a read·modifywrite cycle and the data out will contain the data read from the selected address, If neither of the above conditions is satisfied,
"
'
the c'ond,ition of the' data out 'is iDdeterminate,

WAVEFORMS.,
READ CYCLE
~---~~--~-~----IOC -------------~

v" -------,,,,..,L 1 - - - - - - - - - - 10 . . - - - - - - - - - - 1

========_____--+-+-_1 "--',-' :-'_1'

_______~==HI~GH7.=~------------------------~.-«'____V_A_Ll_D__~~
1
IMPEDANCE

WAVEFORMS
WRITE CYCLE

READ·MODIFY·WRITECYCLE
.~

--'
""1-){ CD AD~~~SS

- - - tcAc----1
',,,
L
HIGH

IMPEDANCE

NOTES: 1,2.
3,4.
5.
6.
7.

-,'··-v
'"0
o:;ttri

(»
VALID
OATAOUT

- 1-''''
1\0
,.;.

V,H MIN and V,L MAX are' reference levels for measuring timing of input signals.
VOH MIN and VOL MAX are reference levels for measuring timing of DOUT '
tOFF is measured to lOUT'" IILol·
t DS and tDH are referenced to CAS or WE, whichever occurs last
t eRP requirement is only applicable for AASfCAS cycles preceeded by a CAS-only cycle (i.e., for systems where CAS
has not been decoded with AAS).
8. Either tRCH or tRRH must be satisfied.

3·223

infel

2164A FAMILY

WAVEFORMS
RAS-ONL Y REFRESH CYCLE
----------------------.~-------------------------I

~---~""$I~H_------------~------------------

HIDDEN REFRESH CYCLE
V.

f
------------~\~~~~
_________________
~_LlD~~DA-TA------------------~-r.-------

NOTES: 1,2. VIH MIN and VIL MAX are reference levels for measuring timing of input signals.

3,4.
5.
6.
7.

VOH MIN and VOL MAX are reference levels for measuring timing of DouT .
tOFF is measured to 10UT:sIILOI.
tos and tOH are referenced to CAS or WE, whichever occurs last ..
tCAP requirement is only applicable for RAS/CAS cycles preceeded by a CAS·only cycle (i.e .. for systems where CAS
has not been decoded with RAS). .
8. Either tACH or tAAH must be satisfied.

3-224

2164A FAMILY

. D.C. AND A.C. CHARACTERISTICS, PAGE MODE [6,7,11)

=O°C to 70°C, VDD =5V ± 10%, Vss =OV, unless otherwise noted.

Symbo)

Parameter
Page Mode Read or Write Cycle

tpc
tpCM

Page Mode Read Modify Write

tcp

CAS Precharge Time, Page Cycle

tRPMl

RAS Pulse Width, Page Mode

tCAS

CAS Pulse Width

1004

Voo Supply Current Page Mode,
Minimum tpc, Minimum tCAS

2164A:15
S6493
Mal;C~
Min.

2164A·20
S6494
Min.
Max.

EXTENDED PAGE MODE[11,12)

Symbol

Parameter
RAS Pulse Width, Extended Page Mode

NOTES: 1,2.
3,4.
5.
6.
7.
8.
9.

tOFF

V,H MIN and. V,L MAX are reference levels for measuring timing of input signals.
VOH MIN and VOL MAX are reference levels for measuring timing of DOUT '
tOFF is measured to lOUT eo IILOI.
All voltages referenced to Vss.
A.C. characteristic assume tT = 5 ns.
See the typical characteristics section for v.alues-of this parameter under. alternate conditions.
t CRP requirement is only applicable for.RAS/CAS cycles preceeded by a CAS·onlycycle (i.e" for systems where CAS
has not been decoded with RAS).
10. Either tACH or tRRH must be satisfied.
11. All previously specified A.C. and D.C. characteristics are applicable.
12. For extended page mode operation, order 2164A·15 S6493. 2164A·20 S6494.

3·225

2164A FAMILY

WAVEFORMS
PAGE MODE WRITE CYCLE

PAGE MODE READ·MODIFY·WRITE CYCLE
~

RAS

___________________________________

t~.

____________________________

~
~ ____ b---~~L-'O~~:-

NOTES: 1,2.
3,4:
5.
6.
7.

and V,L MAX are reference levels for measuring timing of input signals.
and VOL MAX are reference levels for measuring timing of DOUT '
tOFF is measured to 10UT:S; IILOI.
t DS and tDH are referenced to CAS or WE, whichever occurs last.
t CAP requirement is only applicable for RASfCAS cycles preceeded by a CAS'only cycle (i.e .. for systems where CAS
has not been decoded with RAS).
MIN

TYPICAL SUPPLY CURRENT WAVEFORMS

Typical power supply waveforms vs. time are
shown for the RAS/CAS timings of Read/Write,
Read/Write (long RAS/CAS), and RAS-only refresh
cycles. 100 current transients at the RAS and CAS
edges require adequate decoupling of these supplies:
The effects of cycle time; Voo supply voltage and
ambient temperature on the 100 current are shown.
3-227

in graphs included in the Typical Characteristics
Section. Each family of curves for 1001,1002, and
1003 is related by a common point at Voo·= 5.0V
and TA = 25 DC for tRAS = 150 ns and tRe = 260 ns.
The typical 100 current for a given condition of cycle time, Voo and TA, can be determined by combining the effects of the appropriate family of
curves.

2164A FAMILY

TYPICAL CHARACTERISTICS
GRAPH 2
TYPICAL ACCESS TIME

GRAPH 1
TYPICAL ACCESS TIME

GRAPH 3
TYPICAL OUTPUT
SOURCE CURRENT

IRAe (NORMALIZED) 'IS.
AMBIENT TEMPERATURE

t RAe (NORMALIZED) 'IS. Veo

VDD - SUPPLY VOLTAGE (V)

. GRAPH S
TYPICAL OUTPUT
SINK CURRENT

1.5 ' -_ _L-_ _-'-_ _-'-------'---'
4.0
4.5
5.0
5.5
6.0

1.5 L...,---'--~L----'-----'
o
20
40
so
80

VDD - SUPPLY VOLTAG~ (V)

III

TA=2S D C

II
0'

TA - AMBIENT TEMPERATURE (OC)

GRAPH 7
TYPICAL OPERATING CURRENT

GRAPH 8
TYPICAL OPERATING CURRENT

1002 'IS. Veo

1002 VS. AMBIE:NT TEMP~RATURE

50 . . . - - -...- - - - , - - - , - - - - - ,

1001 'IS. AMBIENT TEMPERATURE

GRAPH 5
TYPICAL STANDBY CURRENT

4.0

!i:w

TA - A",BIENT TEMPERATURE (OC)

GRAPH 4
TYPICAL STANDBY CURRENT

GRAPH 9
TYPICAL OPERATING CURRENT
1002 'IS. i/l RC

T=25 D C .
Voo = S.OY
4.0

0'-----'-'-----'----'--,---,-';-'
4.5
5.0
5.S
VDD - SUPPLY VOLTAGE (V)

S.O

fA - AMBIENT TEMPERA.TURE (DC)

TYPICAL CHARACTERISTICS

TYPICAL RAS·ONLY
REFRESH CURRENT

REFRESH CURRENT

REFRESH CURRENT
lool VS. Von

TYPICAL RAS·ON LV

'003 vs. AMBIENT TEMPERATURE

'003 VS. lll RC

'RC

1000 ns

5o,----,-----,----,----,

Voo =S.OV

.s>-

z
~ 30r----+-----r----i-~~

a: 30

()

250 ns

~ 40~---+----~----+---~

~ 20r---~-----r.~~+-----

Voo - SUPPLY VOLTAGE (V)

6.0

°0L---~20--~-4LO----~60----~80
TA - AMBIENT TEMPERATURE (0G)

CYCLE RATE (1I1Rd M.Hz

output pin of a selected device will remain in a
high impedance state until valid data appears at
the output at access time.

DEVICE DESCRIPTION
The Intel 2164A is produced with HMOS,D III, a
high performance MOS technology which incorporates redundant elementS. This process, combined with new.circuit design concepts, allows the
2164A to operate from a single + 5V power supply,
eliminating the + 12V and -' 5V requirements. Pin
1 is not connected, which· allows P.C.B.layout for
future higher density memory generations.

Write Cycle
A Write cycle is performed by taking WE low during a RAS/CAS operation. Data Input (DIN must be
valid relative to the negative edge of WE or CAS,
whichever transition occurs last.

The 2164A is functionally compatible with the
2118, the industry standard 5V-only 16-pin 16K
dynamic RAM. This allows simple upgrade from
16K to 64K density merely by adding one additional multiplexed address line.

Refresh Cycles
There are. 512 sense amplifiers, each controlling
128 storage cells. Thus, the 2164A is refreshed 'in
128 cycles. A.ny combination of the seven (7) low
order Row Addresses RAo through RA6, will select
two rows of data cells (256 cells/row). Row address
7 is not critical during a refresh operation and can
be either high or low. Although any cycle, Read,
Write, Read-Modify-Write, or RAS-only, will refresh
the memory, the RAS-only cycle is recommended,
since itallows about 20% system power reduction
over the other types of cycles.

RAS/CAS Timing
RAS and CAS have minimum pulse widths as
defined by tRAS and tCAS respectively. These
minimum pulse widths must be maintained for
proper device operation and data integrity. A cycle, once begun by bringing RAS and/or CAS low,
must not be ended or aborted prior to fulfilling the
minimum clock signal pulse width(s). A new cycle
can not begin until the minimum precharge time,
tRP,has been met.

Hidden Refresh
A standard feature of the 2164A is that refresh
cycles may be performed while maintaining valid
data at the output pin. This is referred to as Hidden
Refresh. Hidden Refresh is performed by holding
CAS at VIL and taking RAS high and, after a
specified precharge period (tRP). executing a

Read Cycle
A Read cycle is performed by maintaining Write
Enable (WE)high during a RAS/CAS operation. The
3-229

2164A FAMILY

"RAS-Only" refresh cycle, but with CAS held low
(see figure below).

is recommended that RAS and CAS track with Voo
during power on or be held at a valid VIH .

Voo RISE TIME = 10,,5

~::k1

Dour

I ~~:kP
"""---1...-_.1.1_-,---,

f\
I \.
I

HIGHZ
(
--~~~~
_______D_AT_A__~__~

Voo RISE TIME: 1001.S

5
4

3
RAS=VOD

This feature allows a refresh cycle tobe "hidden"
among data cycles without affecting the data availability. The part will be internally refreshed at the·
row addressed at the time of the second RAS.

Figure 1. Typical 100 vs. Voo During PowerUp

Data Output Operation

Page Mode Operation

The 2164A Data Output (Dour), which has threestate capability, is controlled by CAS. During CAS
high state (CAS at VIH), the output is in the high impedance state. The following table summarizes
the Dour state for various types of cycles.

Page Mode operation allows additional columns
of the selected device to be accessed at the common row address set. This is done by maintaining
RAS low while successive CAS cycles are performed.

Intel® 2164A Data Output Operation
for Various Types of Cycles
Type of Cycle
Read Cycle
Early Write Cycle
RAS-Only Refresh Cycle
CAS-Only Cycle
Read-Modify-Write Cycle
Delayed Write Cycle

Dour State
Data from Addressed
Memory Cell
Hi-Z
Hi-Z
Hi-Z
Data from Addressed
Memory Cell
Indeterminate

Power On
An initial pause of 500 /Ls is required after the application of the Voo supply, followed by a minimum
of eight (8) initialization cycles (any cpmbination
of cycles containing a RAS clock such as RAS-only
refresh). 8 initialization cycles are required after
extended periods of bias (greater than 2 ms) without clocks. The Voo current (100) requirement of
the 2164A during power on, is however, dependent upon the input levels of RASand CAS and the
rise time of Voo shown in Figure 1.
If RAS =Vss during power on, the device may go
into an active cycle and 100 would show spikes
similar to those shown for.the·RAS/CAS timings. It

Page Mode operation allows a maximum data
transfer rate as Row addresses are maintained internally and do not have to be reapplied. During
this operation, Read, Write and Read-Modify-Write
cycles are possible. Following the entry cycle into
Page Mode operation, access is tCAC depE;lndent.
The Page Mode cycle is dependent upon CAS
pulse width (tCAS) and the CAS precharge period
(tcp)·

Extended Page Mode Operation
An optional feature of the 2164A is extended page
mode operation which allows an entire page (row)
of data to be read or written during a single RAS
cycle. By providing a fast tpc and long RAS pulse
width (tRPM2), the 2164A-15 S6493 permits transfers
of large blocks of data, such as required by bitmapped graphic applications.

SYSTEM DESIGN CONSIDERATIONS
Ground and Power Gridding
Ground and power gridding can contribute to excess noise and voltage drops. An example of an
unacceptable method is presented in Figure 2.
This type of layout results in accumulated transient noise and voltage drops for the device
located at the end of each trace (path).
3-230

ditional inner layers to the PC board, noise and
supply voltage fluctuations are greatly reduced. If
power and ground planes are'used, gridding is optional but typically used for increased reliability of
power and ground connecti9nsand further reduc'
,
tion of electromagnetic noise;

,It is preferable on power/ground planes to use circular voids for device pins rather than ,slotted
, voids:(Flgure 4). This provides. maximum decoupling and minimum crosstalk between signal traces.

Vss(OND)
RECOMMENDED, :'

NOT RECOMI/IENDED

Figure 2. Unacceptable Power Distribution
Transient effects can be minimized by, adding extra circuit board traces in parallel to reduce interconnection inductance (Figure '3).

. Figure 4. Recommended Voids for Multilayer
,
'PC Boards

Power Supply Oecoupling

21,64A

• TWO SIDED CARD
- VERTICAL TRACES ON COMPONENT SIDE
- HORIZONTAL TRACES ON SOLDER SIDE

, For best results, decoupling capacitors are placed
on the memory array board at each memory location (Figure 5). High frequency 0.1 /LF ceramic
capacitors are the recommended type. Noise i~
minimized because of the low impedance across
the circuit board traces. Typical Voo noise levels
for this arrangement are less than 300 mY.

- MAINO ROUND BUS OR INTERCONNECTION TO
TTL CONTROL. ADDRESS. DATA BUFFERS

A large tantalum capacitor (typically one 100 /LF
per 64 devices) is required at the circuit board
edge connector power input pins to recharge the
0.1 /LF capacitors between memory cycles.

Figure 3_ Recommended Power Distribution
- Gridding

For further detailssee application note (A.N.) #131,
2164A Dynamic RAM Device Description, or A.N.
#133, Designing Memory Systems for Microprocessor Using the Intel 2164A and 2118 Dynamic
RAMs.

Power and Ground Plane'
A better alternative to power and gridding is power
and ground planes. Although this requires two ad-

Dour= •
NOTE 1: FUTURE ADDRESS EXPANSION

NOTE: MEMORY DEVICE SPACING, IS O.42SH
TRACES ARE 50 MIL

Figure 5. 2164A Memory Array PC Board Layout

3·232

. 2186AFAMILY
8192 x 8 BIT INTEGRATED RAM
• Low-cost, high volume HMOS III
technology

• Simple asynchronous refresh operationl
static RAM compatible

• High density one transistor cell

• 2764 EPROM compatible piri-out·

• Single + 5V ± 10DAI supply

• Two-line bus control

• Proven HMOS reliability·

• JEDEC standard 28-pin site·

• Low active current (70 mAl

• Low standby current (20 mAl

The Intel 2186A is a8192 word by B-bit integrated random access memory (iRAM) fabricated on Intel's proven
HMOS dynamic RAM technology. Integrated refresh control provides static RAM characteristics at a significantly lOWer cost. Packaged in the industry standard 28-pin DIP, the 2186A conforms to the industry standard
JEDEC 28-pin site. Designs based on 2186A timings can be made fully compatible with EPROMs and static
RAMs.
The 2186A is particularly suited for microprocessor applications and incorporates many requisite system
features including low power dissipation, automatic initialization, extended cycle operation and two-line bus
.
.
control to eliminate bus contention.

BLOCK DIAGRAM

ROW
ADDRESS
MULTlP~EXER

PIN CONFIGURATION
ROY

A",

~,
A.
A,

CHIP ENABLE
OUTPUT ENABLE

A,
A,
A,
A,
A,
110 0

WRITE ENABLE

110,

DATA INPUT/OUTPUT
REAOV "
+5V POWER

Intel Co~poration Assumes No Resp.onslbility for th~ Use of Any Circuitry Other Than Circuitry Embodied in an Intel
Product. No Other Circuit Patent Licenses are Implied.
.
.
.... . .
© INTEL CORPORATION
.
OCTOBER 1983
3·233
ORDER .NO. 230867·001

ERRATA ENCLOSED
218657572/3/4
8192 x 8 BIT INTEGRATED RAM
• Low-cost, high-volume HMOS
technology

• Simple asynchronous refresh operationl
static RAM compatible

• High density one transistor cell

• 2764 EPROM compatible pin-out

• Single + 5V::!: 10% supply

• Two-line bus control

• Proven HMOS reliability

• JEDEC standard 2S-pin site

• Low active current (70 mAl

• Low standby current (20 mAl

The Intel 2186 is a 8192 word by 8-bit integrated random access memory (iRAM) fabricated on Intel's proven
HMOS dynamic RAM technology. Integrated refresh control provides static RAM characteristics at a significantly lower cost. Packaged in the industry standard 28-pin DIP, the 2186 conforms to the industry standard JEDEC 28-pin site. Designs based on 2186 timings can be made fully compatible with EPROMs and
static RAMs.
The 2186 is particularly suited for microprocessor applications and incorporates many requisite system
features including low power diss!pation, automatic initialization, extended cycle operation and two-line
bus control to eliminate bus contention.

PIN NAMES
~A"
Of
WE
1/0 0 •110 7
ROY
Vee
Vss

1/00······ 110 1

ADDRESS INPUTS
CHIP ENABLE
OUTPUT ENABLE
WRITE ENABLE
DATA INPUTfOUTPUT
READY
+5V POWER
GROUND

The following are trademarks 01 Intel Corporation and may be used only to describe Intel products. Intel, CREDIT. Inde~. In site, In\ellec, library Manager. Megachassls.
Mlcromap. MULTIBUS, PROMPT, UPI.1,Scope. Promware. MeS, ICE. IAMX. ,SBC. ,SBX, MUl TlMODULE and leS Intel Corporation assumes no responsibility lor the use of a~y
CIrcuitry other than CirCUitry embodied In ~n Intel product No other CirCUit palent licenses are Implied

C INTEL CORPORATION. 1982

3-234

April 1983

Order Number: 2101167-002

intJ

8192 x 8 BIT INTEGRATED' RAM

ERRATA
CHANGE IN THE INITIALIZATION PROCEDURE
256 initialization cycles are required to . guarantee
initialization. These may be Read, Write, or False Memory cycles.
The cycle timing for CE (and WE or OE) must meet the minimum
cycle time requirements shown in the A.C. characteristics. The
states of the address and data lines (Ajif-A12 and IOjif-I07) are not
critical.
.....
Initialization cycles may begin anytime after V cc is within
specification and after CE, OE, and WE have reached VI H. Normal
operation may begin anytime after the 256 initialization cycles have
been completed.
This initialization procedure replaces the' initialization'
procedure described .on page 6 and applies only to 5 spec parts
(numbers 57572, 57573, and 57574).

3·235

intJ

2186 FAMILY

'COMMENT: Stresses above those listed under
"Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.

ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias . ." . . .. ..,. 10°C to + SO°C
Storage Temperature ....... -65°Cto + 150°C
Voltage on Any Pin with
Respect to Ground . . . . . . . . .. - 1.0 V to + 7 V
D.C. Continuous Current per Output ....... 10 mA
D.C. Maximum Data Out Current. . . . . . . .. 50 mA
D.C. Power Dissipation ................. 1.0 W

D.C.

AND OPERATING

CHARACTERISTICS I11

TA=O°Cto +70°C, VCC= +5V±10% unless. otherwise noted.,.
Limits

.-,..,.-.,...-.,.----1.'

Inpllt Lead Current (All Input Pins)

IILOI

Output 'Leakage Current
Operating'Cur~ent : ; ,

VILlnput Lew.veltage .
VIH

Notes
VIN '" VSS to vec
OE.= VIH
.. Minimum Cycle Time
CE,~

NOTES FOR D.C. CHARACTERISTICS ' . '
1. Typical limits are VCC = + 5V, TA = 25°C.
2. ICC is dependent en .outputs leading when the deliice .output is selected. Specified ICC max. is measured with the .outputs .open.
3. Specified VIL min ...is fer steady state eperatien. During transmisstiens the inputs. may .oversheet te -,2,OV fer perieds net te ex, ceed 20 nsec. . ' . ,
..
'.'
."'. ::'
....
".'
.' '
.
4. 10Ller ROY is 4mA and VOller ROY is O.BV.
. '.'
"

A.C.

TEST CONDITIONS

+5V

Input Pulse and Timing
Reference Levels. , . . . . . . . . . . . .. O.SV to 2.4V

1.2K

Input Rise and Fall Times. . . . . . . . . . . . .. 10 nsec
Output Timing Reference Level's"
Output Load

(INCLUDING
ScePE AND
JIGI
Dour

TA=25°C, f= 1,0 MHz
Symbol
, C ADD
C lle
C 'N

Address. Capacitance
I/O Capacitance
Centrel Capacitarice

8
14
14

pF
pF
pF

VADD = OV
VIIO=OV
V,N=OV

NOTE: 5. This parameter is characterized and not 100% tested,

3·236

Figure 2.
(FeR HIGH IMPEDANCE
MEASUREMENTS eNLYI

5pF

2186 FAMILY

A.C. CHARACTERISTICS
TA= o·e to· + 70·e, vee= + 5V ± 10% unless otherwise noted.
READ CY C LE (WE = VH
I )

Cycle Time with Refresh

Access Time from CE w/Refresh

OE low to next CE low'

OE high·to next CE low

TGHOX

OE high to Data Float

ROY high to Data Valid

TRHEL

ROY high to next CE low

275

100
95
350

t+---.,-----TELEL - - - - - - . j

-----1----.:.,..-~-\:=~~~~~jl----

READ CYCLE WITH REFRESH

Oe(G)

ROY

DATA
OUT

--+---'-----,
--+---.

---t---!~~----t~~~s
3-237

A.C. CHARACTERISTICS
TA = O·C to

+ 70·C, VCC= + 5V ± 10% unless

WRITE CYCLE (OE = VIH)

" Cycle Time with Refresh

TELEH

otherwis~

TWLEL

WE low to next CE low

WE h!gh to next CE low

TDVWL

Data Set·Up to WE low

TWLDX

Data Hold from WE"low

RDY high to next CE low

WAVEFORMS
WRITE CYCLE

i..------TELEL-----..-j

ADDR

DATA IN

WRITE CYCLE WITH REFRESH

--~~~~~~~~~~--------

I__------TELELR--;====~

We(W)

RDY

---t---"-'-,
_~T~E~LR~L~~t.,....~}

TRHEL

~nn~~--------~--

'DATA IN ------{~D~AT~A~VA~L~ID=})---------

3·238

2186 FAMILY

A.C .. CHARACTERISTICS
+ 7o oe, vee= + 5V±10% unless otherwise noted.

TA';' ooe to

FAL$E MEMORY CYCLE (OEand WE = VIH)
57572
2186·25
Symbol

Cycle Time with Refresh

TELEHF

"CE Pulse Width

TEHELF

CE High Time during F.M.C.

ROY high to next CE low

WAVEFORMS
FALSE MEMORY CYCLE

i-------TELEL-----.-j
I-----TELEHF ---'--'--;.t:=.2~~=~

CE IE)

TELAX

ADDR~_______________~x====

FALSE MEMORY· CYCLE WITH REFRESH
t::::;j'-I----;""""i::;::::==~TRHEl---.j
ROY

---1-"'\

NOTi:SFOR A.C. CHARACTERISTICS:

1.. TELEL < TELELR and TELOV < TELOVR.
2. For reference only;
3. Transition is measured ± 500 mV from ste'ldy state logic level with specified loading inFigure 2.
4. CRDY < 100 pF and REXT = 12001l.
.
5. False Memory Cycles Only.
6. Note TEHELF > TEHEL. .

3·239

2186 FAMILY

nal access and internal refresh cycle requests. The
internal timer period is specified as 2: 5l1sec. ,

FUNCTIONAL DESCRIPTION
The 2186 has three control pins: CE (Chip Enable),
OE (Output Enable), and WE (Write Enable). An
open:drain output pin called RDY indicates if refresh is occurring during an access request'. RDY
will only respond when the 2186 has been selected
by CE going active low during a refresh cycle. '

The 2,186 may also be, refreshed by performing
Read, Write, or False Memory cycles on all 128
rows (AO through A6) within a two millisecond
period.

Cycles are initiated by latching addresses into the
2186 with the leading (falling) edge of CEo When
CE goes active du'ring internal.refresh, the RDY pin
is pulled low signaling a delay. RDY remains low
until shortly before both refresh and access (Readl
Write) cycles are complete.
On-chip control circuitry tracks all operations for
nearly transparent refresh. A high-speed on·chip
arbitration circuit prevents conflicts from occur- , ' ,
ring between refresh and access cycles.

Access Cycles
READ CYCLE
A read cycle is initiated by CE and OE.both going
active low during the ,same cycle. CE may be either
pulsed to initiate a cycle br held active low
throughout the cycle. at: is a logic level; OE controls the 2186 data output bus. Access times are
specified from Doth OE and CEo Data remains on
the data bus until OE returns inactive (high) independent of CE. WE may not go active during a
Read cycle.
WRITE CYCLE
A Write cycle is initiated by CE and WE going active low during the same cycle. CE may be a'pulse
or a logic level. WE leading edge latches data from
the data bus into the 2186. OE may not go active
, during a Write cycle.
FALSE MEMORY CYCLE (FMC)
A False Memory cycle is initiated by CE going active without either OE or WE going active. No
memory cycle wiil be ,performed. Note that address set-up and hold times must be observed for
'False Memory cycle operation.

Operating Modes
REFRESH OPERATION
Refresh is totally automatic and requires no external stimulus. All refresh functions are controlled
internally.
A high-speed arbitration circuit will resolve any potential conflict arising between simultaneous exter-

EXTENDED CYCLE OPERATION
Extended cycle operation is defined as holding OE
or WE valid (low) for indefinite periods. (CE; is allowed to return high.) Data will remain valid on the
bus as long as OE is valid. WE latches data on the
leading (falling) edge. Automatic refreshes will
continue to be performed as needed, even while
OE or WE is held low; RDY will not respond during
:these extended cycle refreshes.
INITIALIZATION
To guarantee initialization, all control inputs must
be inactive (high) for a 100 microsecond period after
Vcc is within specification. No extra cycles are required before normal operation may begin.

Interfacing Considerations
The 2186 is an edge enabled RAM. Below is an illustration of a simple interface for connecting microprocessors with edge enabled memories. A
stable CE clock is necessary to avoid accidentally
selecting the RAM. Generally, stable select signals are desirable in all types of microsystem applications. Most common decoding circuits allow
addresses to flow directly through the decoder
(Le. decoder permanently "enabled"). This technique may allow false decoder outputs to occur
when addresses are in transition. This may result
in false CEsignals and potentially, invalid memory
requests. A simple gating circuit will inhibit enabling the decoder until addresses are valid at the
decoder inputs.
Another interfacing consideration is the relationship between WE and valid data. The 2186 performs a write operation on the leading edge of WE.
In a minimum mode 8088 or 8086 system, WE occurs before data is valid. The cross-coupled NAND
gate configuration shown below on the WR signal
will prevent this from occyrring. This implementation also guarantees valid data on the rising-(trailing) edge of WE to maintain compatibility with fully
static RAMs. (For maximum mode 8088 or 8086
operation, the control signal MWTC directly from
the 8288 bus controller serves the same function,)
For a more detailed description of designing iRAM
3-240

2186 FAMILY

systems, refer to Intel App. Note #132 on "Designing Memory Systems with :the8K x BiRAM".

Layout Considerations
To ensure·compatibility with other 28·pin memory
devices such as EPROMs, several pins require
close examination; specifically, pins number1, 26
and 27. Following is a discussion of the system
level operation and the design considerations for
these pins.
PIN #1
Pin 1 on all EPROMs is reserved for the high voltage programming bias, Vpp. EPROMs are usually
programmed external to the system. Therefore, in
normal system operation, pin 1 is connected to Vee.
Pin 1 on the 2186 is the microprocessor handshake
signal, ROY. The ROY signal maybe bussed to the
ROY input of either the microprocessor or clock
generator. Because ROY is an open drain output,
all 2186 ROY signals may be "wire OR'd" with any
other ROY signals in the system. A 1200 ohm pullup resistor is required between ROY and Vee. For

the 2186 application, a trace should be run from
pin 1 o('each socke,t location to the ROY input of
either the microprocessor or clock generator.
Also, a provision for a pull-up resistor to Vee is
needed. For compatibility with EPROMs, include a
jumper to select Vee and the ROY line on pin 1.
PIN #26
While pin 26 is a No Connect for both the 21.86 and
the 2764 EPROM, a trace to pin 26 from Vee will
guarantee compatibility between 24 pin and 28 pin
EPROMs. Pin 26 'Nill carry the additional address
bit required to future higher density memories. For
flexibility, provide a jumper for an address bit
and/or Vee 0~pin26.
PIN #27
Pin 27 is labelled WE on the RAM and PGM on the
EPROM. While WE is a system level control signal,
PGM is only used when programming the EPROM
(Vpp at + 21V). PGM may be allowed to toggle duro
ing normal EPROM operation (Vpp at + 5V). There·
fore, WE may be bussed to every socket location
with no jeopardy of illegal operation.

iAAM IN,TERFACE
,-------------,

I
I

r--------,,-~--~J

I
I

8088
ALE I--~...r-....

2187A FAMILY
8192 x 8 BIT INTEGRATED RAM
• Low-cost, high-volume HMOS
technology
• High density one transistor cell

• Simple synchronous refresh operation
• 2764 EPROM compatible pin-out
• Two-line bus control

• Single + 5V ± 10% supply
• Proven HMOS Reliability

• JEDEC standard 28-pin site

• Low active current (70 mA)

• Low standby current (20 mA)

The Intel 2187 is an 8192 word by 8-bit integrated random access memory (iRAM) fabricated on Intel's proven HMOS
dynamic RAM technology. Packaged in the industry standard 28-pin DIP, the 2187 conforms to the industry standard
JEDEC 28-pin site.
The 2187 is particularly suited for use in microcontroller applications, incorporating many requisite system features.
These include low power dissipation, .automatic initialization, extended cycle operation and two-line bus control to
.
eliminate bus contention.

BLOCK DIAGRAM

PIN CONFIGURATION
REFEN

ADDRESS INPUTS
CHIP ENABLE
OUTPUT ENABLE
WRITE ENABLE

DATA INPUTJOUTPUT

V,s

REFRESH ENABLE
+5V POWER
GROUND

The follOWing are trademarks of Inlel Corporation and may be used only to describe Intel products: Inlel. ICE, iMMX, iAMX. iSBC. iSBX, iSXM, MULTIBUS. MULTICHANNEl and MUl TIMODULE

Inlel Corporation assumes no responsibility for the use 01 any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses afe implied.

o INTEL CORPORATION 1983

3-242

April,1983
Order Number: 210859-001

inter

2187A FAMILY

ABSOLUTE MAXIMUM RATINGS·

• COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

Temperature Under Bias ....... - 10°C to + 80°C
Storage Temperature ......... - 65°C to + 150°C
Voltage on Any Pin with
Respect to Ground . . . . . . . . . . .. - 1.0V to + 7V
D.C. Continuous Current per Output ....... 10 mA
D.C. Maximum Data Out Current .......... 50 mA
D.C. Power Dissipation .................. 1.0 W

D.C. AND OPERATING CHARACTERISTICS(1 1
TA = O°C to + 70°C, VCC = + 5V ± 10% unless otherwise noted.
Limits
Symbol

III

Parameter

Min.

Input Load Current (All Input Pins)

Test Conditions
OE=VIH

IILOI

Output Leakage Current

NOTES FOR D.~. CHARACTERISTICS:
1. Typical limits are VCC = + 5V, TA = 25°C.
2. ICC is dependent on outputs loading when the device output is selected. Specified ICC max. is measured with the outputs open.
3. Specified VIL min. is for steady state operation. During transitions the inputs may overshoot to - 2.0V for periods not to exceed 20 nsec.

A.C. TEST CONDITIONS

.sv

Input Pulse and Timing
Reference Levels ................ 0.8V to 2.4V
Input Rise and Fall Times .............. 10 nsec.
Output Timing Reference Levels .... 0.6V and 2.4V
Output Load ..................... See Figure 1

1.6K

Dou, - - -.......---1

Figure

CAPACITANCE 141

100pF

(INCLUDING
SCOPE AND
JIG)

910

1.6K

910

TA=25°C, f= 1.0 MHz
Figure 2.
Symbol
CADD

Parameter
Address Capacitance

NOTE: 4. This parameter is characterized and not 100% tested.

3-243

(FOR HIGH IMPEDANCE
MEASUREMENTS ONLY)

SpF

2187A FAMILY

A.C. CHARACTERISTICS
TA = ooe to +70 oe,

vee = + 5\1 ± 10% unle.ss otherwise noted

READ CYCLE (WE ~ ViH)

CE Pulse Width
CE High Time

OE low to next CE low

TGLGH

OE Pulse Width

TGHEL

OE high to next CE low

TGHOX

OE high to Data Float

40
40
0
35
250
65
40
0
40
425
250
70

40
40
0
35
300
75
40
·0

--:--+-~-~-t=~~~~=j'----

READ CYCLE FOLLOWED BY REFRESH
TELRFL

~
,..:. TGlaV
DATA VAllO
A'",.

3-244

ns
ns

I+----'----'--TELEL - - - -

A.C.CHARACTERISTICS
TA

=ooe to

+ 70 oe, vee = + 5V ± 10%

WRITE CYCLE (OE

Symbol

unless otherwise noted.

WE low to next CE low

TWLWH

WE Pulse Width

TWHEL

WE high to next CE low

TDVWL

Data Set·Up to WE low

TWLDX

Data Hold from WE low

Min.
425
40
40
0
35
250
40
40
0
40

2187-30
Max.

Min.
500
40
40
0
35
300
40
40
0
45

10,000
40
425
250
70

9800

2187-35
Max.

Min.
600
40
40
0
35
350
40
40
0
50

10,000
40
500
300
70

ns
ns
ns.
ns
ns
ns .
ns
ns
ns

40
600
350
70

ns
ns

9800

WAVEFORMS
··~---:---TElEl------

WE(W) ---t--~

DATA IN

U"~_....I

--....!!:~~~~~~~~r----------

WRITE CYCLE FOLLOWED BY REFRESH

CEIE}

WEIW} - - - - -__
TRFLRFH

AEFENIAF}

DATA IN

------1------"
-----{~DA~T~AV~A~lI~D:Jf---~------:-3·245

A.C. CHARACTERISTICS
TA=ooe to + 70 oe, vee = +5V ± 10% unless otherwise noted.
FALSE MEMORY CYCLE COE and WE = VIH)

CE High Time during,F.M.C.

,,2187-30
Min.• - 'Max.
500
110 10;000
250
0
35
500
250

2187-25
Min. Max.
..
425
40 10,000
200
0

CE.high 10 REFEN low after F.M,C.

35'

425
,200

WAVEFORMS

2187-35
Min. Max.
600
40 10,000
275
0
35
600
','
275,

Unit
ns
ns
ns
',ns
ns
"ns

FALSE MEMORY ,CYCLE

1 - - - - - - TELEL----~--J
I__---TELEHF ~-'--....-

,,:. ...

CE (E)

TELAX

AOOR~r'----------------------x====

'FALSE MEMORY CYCLE
FOLLOWED BY A REFRESH

___________________________

CHARACTERISTICS'
vee = +5V ±1 0%

TA = O°Cto +70°0,

unless otherwise noted.

REFRESH CYCLE

2187-25
Symbol
TELRFL

425
500
600
TRFLRFH
REFEN Pulse Width
70 .9800
70 9800
70 ,9800
TRFHEL
REFEN high to CE iow
40
40
40
TRFLRFL
REFEN cycle time to· guarantee refresh
350 15600
400 15600 450 15600
450
TRFLEL
REFEN lowto CE low'
350
400
450
350
REFEN high to CE low - extended cycle
TRFHELE
400
TGLRFL
. OE lowto REFEN low
250
275
300
WE low to REFEN low
250
300
350
TWLRFL
10,000
10,000
TRFLRFHE REFEN Pulse Width - extended cycle
10,000
TRFHRFLE REFEN high to REFEN low - extended cycle
425
500
600
"

WAVEFORMS
REFRESH CYCLE
f+-....,.-:----TRFLRFL-----~

OE(G), (READ CYCLE) .
. .,----,

V/E(W) (WRITE CYCLE) - - - - - , - - - - - - - - - - - - - - ' "

EXTENDED CYCLE REFRESH"

CE(E)

.....,..,..-+-___ r __

REFEN(RF) -:-

_41r__-...u.~j-,+---"\~--'-TR-F~L.RFHE
"

, TRFH,E, LE

.OE(G) - - , . . . . "

V/E(W)

....,..--.,....;-----4~-----"""'\

NOTES FOR A.C. CHARACTERISTICS:
I:Tran~itionis,;,easured±500mV from steady state logic lev'elwith specified loading in Figure 2.
2. 'Maximum applies forF.M.C: Only.
3. Note TEHElF > TEHEl.
' .
4. TRFHELE > TRFHEL and TRFLRFHE > TRFLRFH.
5.: Extended cycles occur when the REFEN pulse widthiso:l0 ~sec.

must be r:net to guarantee the ii,tegrity of internal data.
During an FMC; the 2187 performs a refresh cycle on the
externally addressed row.' ,

FUNCTIONAL DESCRIPTION'
The 2187 has four control pins: CE (Chip Enable), OE
(Output Enable), WE (Write Enable), and REFEN (Refresh Enable): These cot1trollines select and control the
operation of the iRAM.

Note that some of the CE timing specifications for an FMC
differ from those of a read or write cycle.,

CE is the general purpose Chip enable Iin!3. It is an edge "
triggered signal that controls several internal operation!?'
An access cycle begins with the leading (falling) edge of
CE. At this time, the external address is latched into the
2187 and is held throug~out the current cycle. CE may be
pulsed or it may remain low ~hroughout the cy?le.
OE selects a read cycle and controls the output data bus.
VIIhen OE goes ,active (low) du'ring a riilad cycle, the oLltput drivers of the 2187 are enabled. Data remains valid
on the output lines as long as OE is active - independentof the state of CE.
'
WE is the edge triggered input that defines a write cyde.
During write cycles, data is latched from the extermilbus
into the 2187 by the leading (falling) edge of WE. WE and
OE may not be active during the same cycle.
REFEN initiates the internal refresh cycles of the 2187.
A refresh cycle begins whenever REFEN goes active (low).
An internal refresh address counter provides the refresh
address. To prevent conflicts between refresh and access
cycles, several timing parameters, refer!3nced to REFEN,
must be met. These parameters ara specified in the timing tables of the 2J,87 A.C. Characteristics.

Access Cycles
READ CYCLE

A read cycle is initiated when both CE and OE go active
low during the same' cycle. Access times are specified
from both OE and CE. After OE goes active (low), and the
hold time for CE has been met (TGLEH), CE may go inactive. As long as OE remains active (low), data remains
"on the output lines - independent of the level ~f CEo
WE m'ay not go active (low) during the read cycle.
WRITE CYCLE

A write cycle occurs when both CE and WE go active (low)
, in the same cycle. Once WE has gone active (low), CE
may go inactive after a minimum hold time (TWLEH). The
leading (falling) edge of .WE latches data from the external
bus into the 2187. Data must be valid at this time.
OE must not go active during the write cycle.'
FALSE MEMORY CYCLE

..,J;. ",

A false memory cycle (FMC) occurs when CE goes active
(low), arid OE and WE remain inactive (high): No memory
cycle is performed, but address set-up and hold times

Other Operating Modtts
REFRESH OPERATION

The 2187 supports three refresh,modes. Two are controlled externally. The third mode can beellabled whim
the 2187 is not accessed rorextended periods of tir:ne
(during system stand-by or extended cycle operation).
An internal refresh timer guarantees refresh to maintain
data integrity.
'
'
A refresh cycle is initiated byth!3 leading (falling) edge
of REFEN. Once a refresh cyCle begins, cycle operation
is internal and automatic. REFEN may go inactive (high)
after the minimum active low pulse time has been met.
'Addresses are sLipplied by the internal refresh address
counter. To guarantee internal data integrity, REFEN
must be strobed ai least 128 times in every 2 millisecond
period. REFEN pulses may be distributed or grouped
(burst mode).
'

CE may not go active (low) while a refreSh cycle is in
progress.
The ~187 may also be refreshed by relid, write, or false'
,memory cyCles. To'accomplish this, the user's system
must cycle through each of the 128 rows in every 2 millisecond time frame. In this mode, the refresh address is
comprised of the seven lowesi order address bits (Ao-Ar),
supplied externally.
'
EXTENDED CYCLE OPERATION

Extended cycle operation is useful for single-step operations and is defined by OE or WE remaining active (low)
for indefinite periods of time. (CE is allowed to return high).
As long as OE is active (read cycles only), data will ramain
valid on the output bus. During write cycles, data is latched
on the 'leading (falling) edge of WE. Throughout the remainder of the extended cycle, data may change on the
external lines without affecting the contents of the iRAM.
To guarantee refresh of the iRAM array during extended
cycles, REFEN must go active (low) after CE has gone
, active (low). While REFEN is low, an internal timer guarantees that the iRAM array is adequately refreshed,
thus ensuring data Integrity. ~efresh cycles Will occur
automatically, even if
Of iRE r.emains low. While
REFEN is low, CE may not gO active (iow). Note:that if
REFEN is not enabled (Iow),properrefresh of the 2187
array cannot be guaranteed during extended cycles.

Once REFEN returns inactive (high), there are two timing
specifications that must be met before the iRAM is accessed again. These are TRFLEL and TRFHELE.
The internal refresh timer may also be enabled (by holding
REFEN low) when the iRAM will not be accessed for ex,
tended periods of time. It is up to the user to ensure that
when REFEN returns inactive (high), no timing specifications are violated.

Initialization
Once Vee is within specification, the 2187 is initialized
by holding REFEN active (low) and all other control inputs
inactive (high) for 100 microseconds. This may be done
any time after Vee meets specification. Normal operation
may begin immediately after initialization.

Interfacing Considerations
The 2187 is ideally suited for use with microcontroller
systems that use external memory. Figure 1 is an illustration of the simple circuitry required to interface a 2187
and an 8051 microcontrolier. In this particular design,
all program memory is located in the 8051 's internal ROM.

External data memory is mapped into the lower 32K bytes
of the 8051 address space.
The 2187 is an edge enabled RAM, therefore a stable
CE clock is necessary to guarantee proper iRAM operation. The system shown in Figure 1 uses ALE (Address
Latch Enable) to generate CE for the 2187. Because the
8051, generates ALE for all memory cycles, internal and
external, ALE must be gated with an external address
line. This ensures that the 2187 is only selected during
external cycles, and not during the shorter internal cycles.
To guarantee data integrity, the 2187 is refreshed whenever the 8051 performs an internal cycle. In this case,
the trailing (falling) edge of ALE is used to generate the
REFEN signal. Once a refresh cycle begins, it will terminate automatically. This design ensiJres that the 2187
ispr6perly refreshed and that it will always be ready to
respond to access cycles in systems running at speeds
up to 12 MHz.
Application note 132 "Designing memory systems with
the 8K x 8 iRAM", contains a detailed analysis of the iRAM
interface. It also describes several designs that incorporate the iRAM into microprocessor and microcontroller
systems.

RESET

8051

74F32
WR~--------------~WE

Figure 1.8051/2187 System Interface
3-249

inter

2187A FAMILY

be selected when the site is occupied by an EPROM.
(See Figure 2).

Layout Considerations
To ensure compatibility with other 28-pin memory devices
such as EPROMs, several pins require close examination:
specifically pins number 1,26, and 27. Following is a dis:
cussion of the system level operation and the desigr considerationsfor these. pins.

PIN #26
While pin 26 is a No Connect for both the 2186 and the
2764 EPROM, a trace to pin 26 from Vee will guarantee
compatibility between 24 pin and 28 pin EPROMs. Pin
26 will carry the additional address bit required to future
higher aensity memories. For flexibility, provide a jumper
for an address bit or Vee on pin 26.

PIN #1
Pin 1 on all EPROMs is reserved for the high voltage programming bias Vpp. EPROMS are usually programmed
external to the system. Therefore, in normal.systemoperation, pin 1 is connected to Vee.

PIN #27

Pin 1 on the 2187 is REFEN, the refresh control in'put.
REFEN may come from a microcontroller, or a synchronous refresh timing circuit. In a system incorporating a
28 pin universal site, a trace should .be run froni pin 1 .
to the source of the refresh control signal generator, with
an alternate trace running to Vee. A jumper option would
select REFEN when a 2~ 87 is in the socket. Vee would

Pin 27 is labelled WE on the RAM and PGM on the
EPROM. While WE is a system level control signal, PGM
is only used when programming the EPROM (Vpp at
+ 21V). PGM may be allowed to toggle during normal
EPROM operation (Vpp at +5V). Therefore, WE may be
bussed to every socket location with no jeopardy of illegal
operation.

Jumper Matrix Connections
Pin
1

Figure 2. Universal Site Jumper Matrix -iRAM/EPROM Interchange
3-250

intJ
51C64 FAMILY
65,536x1 BIT CHMOS DYNAMIC RAM
51 C64-1 0

51 C64L·1 0

51C64-12

51C64L·12

Maximum Access Time (ns)

100

120

Minimum Cycle Time (ns)

160

190

Maximum Column Address Access Time (ns)

• CHMOS·D 111* Technology
• Low power dissipation for the 51 C64
-

• Average soft error rate less than 10
FITs (0.001 %/1 000 hours) .

operating current
37 mA (max.)
standby current, TTL
3 mA (max.)

• Ripplemode ™ operation for a sustained
data rate up to 15.3 MHz

• Extend~d refresh and CHMOS standby
current for the 51C64L
-

• Low input/output capacitance

refresh period, standby mode 64 mS (max.)
standby current,'CHMOS
100 p.A (max.)

• High reliability plastic 16'pin DIP

The IntelC!> 51C64 is a high speed 65,536 birdynamic Random Access Memory. Fabricated on Intel's CHMOS·D III
technology, the 51C64 offers features not provided.by an NMOS technology: Ripplemode,lM fast usable speed, low
power, and an average soft error rate of less than 10 Failures In Time (FITs). The 51 C64 is ideally suited for applica·
tions such as graphic display terminals, battery backed-up and operated systems, and high-performance systems.
Ripplemode operation allows access of up to 256 bits at a 50 nslbit rate with random or sequential addresses within
a single row. Thus, a continuous data rate up to 15.3 million bits per second can be achieved. The 51C64 offers
high performance while relaxing many critical system timing requirements for fast usable speed. In addition, the
fast RAS and CAS access times are compatible with high performance microprocessors such as the 8 MHz iAPX '
286 with no WAIT state operation.
The 51 C64L offers a standby current of 100 p.a when RAS;:: Voo - 0.5V. During a RAS-only refresh cycle, the 51 C64L
extends the refresh period to 64 ms to reduce power consumption to typically 235 p.W for data retention. The 51 C64
comes in a 16-pin plastic dual in-line package. All inputs, outputs and control signals are TTL compatible. The input
and output capacita!1ce are significantly lowered to reduce system drive requirements.
PIN
CONFIGURATION

LOGIC
SYMBOL

BLOCK DIAGRAM

PIN NAMES
"rAJ AIMIRdSINI'\ITS
~

DIll

COLUMN ADDIIEU affiNE
DATAIN

• CHMOS.O lUis a patented process of Intel Corporation.
The loIlowlng are trademarks 01 Inlol Corporation end may be usod only to doscribelnlol products: Inlol, ICE, IMMX,IRMX, ISBC,IS8X, ISXM, MUL118US,Muhlchonnel, MULT!MOOULE
and RipplelTJ9de.lnlel Corporation assumes no responslbUIty forthe use of any,clrcuitry other than circuitry embodied in an Intel product. No other clrcuh patent licenses are Implled.lnformatIon contained herein supercedes previously pubJished speclflcatJons on these devices from Inlel.
"

3·251

July,l983

Order Number: 230131~01

·n+_I~

I.,.~'.
51C65 FAMILY
STATIC
COLUMN
CHMOS
DYNAMIC
.
.
.
:
.
. . RAM
.. .
,.

S1C65-10
Maximum Access Time (ns)

Minimum Cycle Tim,e (ns)

Maximum Column Address .Access Time (ns)

50
.,

....

• Low power dissipation for the 51C65"

• 65,536 x 1 Organization'

- operating current
37 mA (max.)
- standby current, TTL
3 mA (",ax.)

• Static Column Mode operation
...... data rate over 20 MHz,
- allows easy implementation of tesselation

• Low input/output capaci,ance
..
"

•

• Extended refresh and CHMOS standby
current for the 51C65L
- refresh period, standby mode 64 mS (max;)
,' ...... standby current, CHMOS .
'100'JlA (max.)

Av~rage

soft error rate less than 10
FITs (0.001 %11 000 hours)

• 'High reliability plastic 16-pin DIP

The Intel® 5.1C65 is a high speed 65,536 bit dynamic Random Access ·Memory. Fabricated on Intel's CHMOS-D 111*
technology~ the51 C65 offers features not provided by an NMOS technology: Static,Column Mode, fast usable speed,
low power; and an average soft error rate of less than 10 Failures In Time (FITs). Th~ .51 C65 is ideally suited for
applications such as graphicqiSPI?y terminals using ~esselation, and high-performance ,~ystems,
Static Column Mode operation allows access of up.to 256 bits at a 50 nslbit rate with random or sequential addresses
within a single row simply by changing the column addr.esses. A continuous.data rate over 20,million bits per. second
can be achieved, The 51C65 offers high performance while relaxing many critical system timing requirements for
fast usable speed.
The 51C65L offers a standby current of 100 l'aWhen RAS~VDD'" 0.5V. During a RAS-only refresh cycle, the 51C65L
extends the refresh period to 64 ms to reduce power consumption to typically 2351'W for data retention. The 51 C65
comes in a 1&-pin plastic dual in-line package. All inputs, outputs and control signals areTTLcompatible. The input·
and output capacitance are significantly lowered to reduce system drive'requirements.
PIN
CONFIGURATION

r------.---r~~,c·~,~
1 O~

IZI'.'Z8CELL
_OIlY,I,I'II1",'

0"•

~T.

QECOOEFIS

12B1< 12. C£U.
ME_VARRA't'

WAItEENA8LE
IIOWAODAESSSTAOIE •

* CHM05-O III is a patented process of Intel Corporation.
The' foI-OW:1ng are trade~arkS'Of l~t~1 :Corpo~tlon. arid ma~ ~ used only to describ~·lntel.pro(fucts: inlel, iCE. iMMX; iR~. iSB~, 'fs'ax, ISXM, MULneus, Muhlchannel, MULTIMOi:>LJ,-E
and Rlpplemode. Intel CorPoration ~umes no resPonslbllltyforthe use of any circuitrY other than circuitry embodied an In~1 pi'od~' No other circuit patent IIcen~s are !rnjJil~d. Information contained herein supercedes previously published specifications on these,devlces from Intel.
"
. .
.
.

3;252

.OCIobor, 1983

RAM FAMILY
EXPRESS
- Standard Temperature Range

-168 (±8) Hour .Burn-in Available

- Extended Temperature Range
-40°C- +85°C Available

- Inspected to.0.1% AQL

The Intel EXPRESS RAM family is a series of random-access memories which have received additional
processing to enhance product operating temperature range and infant mortality. EXPRESS processing is
available for several densities of RAM, allowing the choice of appropriate memory size to match system
applications.
EXPRESS RAM product is available with 168(±8) hour, 125°C dynamic burn-in using Intel's standard bias'
configuration. This process exceeds or meets most industry specifications of burn-in.
The standard EXPRESS RAM operating temperature range is O°C to 70 or 75° C. Extended operating temperature range (-40°C to 85°C) EXPRESS product is available. EXPRESS products plus military grade RAMs (-55°C
to 125°q provide the most complete choice of standard and extended temperature range RAMs available.
Like all Intel RAMs, the EXPRESS RAM family is inspected to 0.1% electrical AQL. This may allow the user to
reduce or eliminate incoming inspection testing.
Detailed individual product electrical specifications are available separately in Intel's respective commercial
and industrial grade product data sheets.

Pin Configuration
Inlel Corporation Assumes No Responsibilty for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied.
©INTEL COAPORATIO~, 1982
MARCH 1982
ORDER NUMBER: 210347-001

3-253

'intel"

RAM FAMILY
Table 1. RAM Product Family

Operating
Temperature

Burn-In

eC)

(±8 hours)

o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o,to 70
o to 70

OD2114A-4
OP 2114A-4
OD2114A-5
OP 2114A-5
OP 2114A-6
OD2114AL-1
OP 2114AL-1
OD2114AL-2
OP 2114AL-2
OD2114AL-3
OP 2114AL.:-3
OD2114AL-4
OP 2114AL-4

1K x 4
1K x 4
1K x 4
1K x 4
1K x4
1K x 4
1K x'4
1Kx 4
1K x 4
1K x 4
1K x 4
1K x 4
1K x 4

200
200
250
250
300
100
100
120
120
,150
150
200
200

5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V

±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%

LD
LD
LD
LD

2114A-4
2114A-5
2114AL-3
2114AL-4

2114A-4
2114A-5
2114AL-3
2114AL-4

1K x4
1K x4
1K x 4
1K x4

200
250
150
200

5V
5V
5V
5V

±10%
±10%
±10%
±10%

-'-40 to 85
-40 to 85
-40 to 85
-40 to 85

o to 75
o to 75
o to 75
o to 75
o to 75
o to 75
o to 75
o to 75
o to 75
o to 75
o to 75
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70

OD2115A
OD2115A-2
OD2115AL
OD2115AL-2

OD2125A
OD2125A-2
OD2125AL
OD2125AL-2

OD2125H-2
OD2125H-3
OD2115H-4

1K x 1
1K x 1
1K x 1

25
30
35

5V ±5%
5V ±5%
5V ±5%

OD2147H
OD2147H-1
OD2147H-2
OD2147H-3
OD2147HL
OD2147HL-3

5V ±10%
5V ±10%
5V ±10%
5V ±10%
5V±10%
5V ±10%

OD2148H
OD2148H-3
OD2148HL
OD2148HL-3

OD2149H
OD2149H-2
OD2149H-3
OD2149HL
OD2149HL-3

125°C
168
168
168
168
168
168
168
168
168
168
168
168
168
168
168
168
168

NONE
NONE
NONE
NONE
168
168
168
168
168
168
168
168
168
168
168
168
168
168
168
168
168
168
168
168
168
168
168
168
168
168
AFN-D2163A

- - - OV
2114/2148/2149
TIMING DIAGRAM

7 p,s CYCLE TIME

Figure 1, 2114A, 2148H,2149H Burn-in Corifiguratlon ,

,.....f---------7 "..-------_01
I
.

;-1- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ; - - - - - - - -

- - - 5V
-

211512125 TIMING DIAGRAM
7 p.S CYCLE TIME

Figure 2. 2115,2125 Burn-In Configuration

--------------------------------~~

"ADD. ADY. 1-1"·- - - - - - - - - - - - - - - 1 3 / L s - - - - - - - - - - - - - -...

500 ns
RAS

1~.~---4/LS----.~I!.====================9~.5~/LS~==================~.
.
Pin 5

CAS

4/LS~F.
. l/Ls

8.5/LS

IF';::::==========:;liiiO-;;/L;s==========:;'il"':::2~/LS~-tj~:--1.51'8-

MUX

IF';::::=====~6~.50/L;s::====:.~I.~:::::::::::::::7~/L~5::::::::::::::~.

STROBE

Pin 17

Pin 4

...--------'-----------,1___
---

5V
OV

13.5 1'5

(TYP)

I··---------------CYCLETIME--------------~·I

I
2118 TIMING DIAGRAM

Figure 3. 2118 Burn-in Configuration

I
------------,Ur-----

r-I

- - - IV

1-41------7,.1------_"1
·ADD.

·MUlI' I~I------------------------------~----- ...,-.:- IV
I

2147H
TIMING DIAGRAM
7,.. CYCLE TIME

Figure 4. 2147H Burn..n Configuration

3-258

8203
64K DYNAMIC RAM CONTROLLER
• Provides All Signals Necessary to
Control64K (2164) and 16K (2117, 2118)
Dynamic Memories

• Fully Compatible with Intel® 8080A,
808SA, iAPX 88, and iAPX 86 Family Microprocessors

• Directly Addresses and Drives Up to 64
Devices Without External Drivers

• Decodes CPU Status for Advanced Read
Capability in 16K mode with the 8203-1 and
the 8203-3.

• Provides Address Multiplexing and
Strobes

• Provides System Acknowledge and Transfer Acknowledge Signals

• Provides a Refresh Timer and a Refresh
Counter

• Refresh Cycles May be Internally or Externally Requested (For Transparent Refresh)

• Provides Refresh/ Access Arbitration

• Internal Series Damping Resistors on All
RAM Outputs

• Internal Clock Capability with the 8203-1
and the 8203-3

The Intel® 8203 is a Dynamic Ram System Controller designed to provide all signals necessary to use 2164, 2118
or 2117 Dynamic RAMs in microcomputer systems. The 8203 provides multiplexed addresses and address
strobes, refresh logic, refresh/access arbitration. Refresh cycles can be started internally or externally. The
8203-1 and the 8203-3 support an internal crystal oscillator and Advanced Read Capability. The 8203-3 is a ±5% Vee
part.

Figure 1. 8203 Block Diagram

Bl/OP, (AH71
BO (AL7)

Figure 2. Pin Configuration

Intel Corporation Assumes No Responsibility for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel,Product. No Other Circuit Patent Licenses are Implied.
©INTELCORPORATION.1982
JULY 1982

3·259

ORDER NUMBER: 21044-002

8203

Table 1. Pin Descriptions
Symbol

Pin
No. Type

Ala
All
Al2
Al3
Al4
Al5
Al6

Address Low: CPU address inputs used to generate memory
row address.

RASa
RASI
RAS21
OUT?
RAS3/BO

21,
22
23

0
0
0

1/0

AHO
AHI
AH2
AH3
AH4
AH5
AH6

5
4
3
2
1
39
38

Address High: CPU' address inputs used to generate memory
column address.

XACK

Transfer Acknowledge: This
output is a strobe indicating valid data during a read cyCle or
data written during a write. cycle.
XACK can be used to latch valid
data from the RAM array.

BO/Al7
Bl /OP l l
AH7

24
25

I
I

Bank Select Inputs: Used to
gate the appropriate RAS output
for a memory cycle.B 1 i OP 1 option used to select the Advanced
Read Mode. (Not available in
64K mode.) See Figure 5.
When in 64K RAM Mode, pins 24
and 25 operate as the AL 7 and
AH7 address inputs.

SACK

PCS

Protected Chip Select: Used to
enable the memory read and
write inputs. Once a cycle is
started, it will not abort even if
PCS goes inactive before cycle
completion.

System Acknowledge: This
output indicates the beginning of
a memory access cycle. It can
be used as an advanced transfer acknowledge to eliminate
wait states. (Note: Ii a memory
access request is made during a
refresh cycle, SACK is delayed
until XACK in the· memory access cycle), ,

36
37

1/0
110

External Refresh Request: ALE
function used in Advanced Read
mode, selected by OPI(pin 25).

Oscillator Inputs: These inputs
are designed for a quartz crystal
to control the frequency of the
oscillator, If XOIOP2 is shorted
to pin 40 (VCe> or ifXOIOP2 .is
connected to + 12V through a
1Kn resistor then XII ClK becomes a TTL input for an external clock. (Note:' Crystal mode
for the 8203-1 and the 8203-3
only),

16K/64K

Mode Select: This input selects
16K mode (2117,2118) or 64K
mode (2164). Pins 23-26
change function based on the
mode of operation,

Memory Write Request.

RDISl

Memory Read Request:, SI
function used in Advanced Read
mode selected by OP 1 (pin 25),

REFRQI
ALE

OUTo
OUTI
OUT2
OUT3
OUT4
OUT5
OUT6

7
9
11
13
15
17
19

0
0
0
0
0
0
0

Output of the Multiplexer:
These outputs are designed to
drive the addresses of the Dynamic RAM array. (Note that the
OUTO-7 pins do not require inverters or drivers for proper operation.)

Write Enable: Drives the Write
Enable inputs of the Dynamic
RAM array,

CAS

Row Address Strobe: Used to
latch the Row Address intcithe
bank of dynamic RAMs, selected by the 8203 Bank Select pins
(BO, B 11 OP 1). In 64~ mode,
only RASa and RASI are available; pin 23 operates as OUT7
and pin 26 operates as the BO
bank select input.

XO lOP2
Xl /ClK

,31

Name and Function

Column Address Strobe: This
output is used to latch the Column Address into the Dynamic
RAM array.

3-260

Functional Description
The 8203 provides a complete dynamic RAM controller for microprocessor systems as well as expansion
memory boards. All of the necessary control signals
are provided for2164, 2118and 2117 dynamic RAMs.
The 8203 has two modes, one for 16K dynamic RAMs
and one for 64Ks. controlled by pin 35.

AFN-02144B

8203

Other Option Selections

The 8203 has three strapping options. When OP1 is selected (16K mode only), pin 32 changes from a RD input to
an S 1 input, and pin 34 changes from a REFRQ input to an
ALE input. See "Refresh Cycles· and "Read Cycles· for
more detail. OP1 is selected by- tying pin 25 to +12V
through a 5.1 K ohm resistor on the 8203-1 or 8203-3
only.

Figure 3. erntel Oper!ltlon for the 8203-1 and
8203-3
. All 8203 timing is generated from a single reference clock.
This clock is provided via an external osciilator or an onchip crystal oscillator. All output signal transitionl! are !ilynchronous with respect to this cloCk reference, except for
the trailing edges of the CPU handshake signals SACK and
XACK.
.
,
CPU memory requests normally use the RD and WR inputs. The AdvancBd-Read mQde allows ALE and S 1 to be
used in place of _he RD input.
Failsafe refresh is provided via an internal timer which generates 'refresh requests. Refresh requests can also be
'
generated via theREFRQ input.
on-chip synchronizer I arbiter prevents memory andrefresh requests ·from· affecting a cyCle in progress. The
READ, WRITE, and el. No current
limiting resistor should be used. OP2 may also be selected
by tying pin 36 to +12V through a 1K!1 resistor .

Refresh Timer
The refresh timer is used to monitor the time since the last
refresh cycle occurred. When the appropriate amount of
time has elapsed, the refresh timer will request a refresh
cycle. External refresh requests will reset the refresh
timer.
.

Refresh Counter
The refresh counter is used to sequentially refresh all of
the memory's rows. The S-bit counter is incremented after
every refresh cycle.

RAS2
Bank Select (BO)
Bank Select (B 1)
RAS3

Address Output (OUT7)
Address Input (AL 7)
Address Input (AH7)
Bank Select (BO)

Figure 4. 16K/64K Mode Selection

16K/64K Option Seloction
Pin 3q is a "trap input that controls the two 8203 modes.
Figure 4 Shows the four pin$ that are multiplexed. In 16K
mode (pin 35 tied to Vee or lett open), the 8203 has two
Bank Select inputs to select one of four RAS outputs: In
this mode,the 8203 is exactly compatible with the Intel
8202A Dynamic RAM Controller. In 64K mode (pin 35 tied
to GND), there is only one Bank Select input (pin 26) to
select the twoRAS outputs. More than two banks of 641<
dynamic RAM's can Ile used with external logic.

RASo'RAS1 RAS2- RAS3
_1
11
0
1
0
1
1
1
1
1
0
11
0
1
0

1
0

Figure 5: Bank Selectio!)

. Normal Function

Description

Pin #.

B1/0P1 (16K only) I AH7.·

Bank (RAS) Select·

Advanced-Read Mode (8203-1. -3)

XO/OP2

Crystal Oscillator (8203·1 and 8203·3)

External Oscillator

Option Function .

Figure 6. 8203 Option Selection
AFN-02144e

8203

Address Multiplexer

Refresh Cycles

The address multiplexer takes the address inputsand-the
refresh counter outputs, and gates them onto the address
outputs at the appropriate time. The address outputs, in
conjunction with the RAS and CAS outputs, determine the
address used by the dynamic RAMs for read, write, and
refresh cycles. During the first part of a read or write cy'
cle, ALO-AL7 are gated to QUTO-QUT7, then AHO-AH7
are gated to the address outputs.

The 8203 has two ways of providing dynamic RAM
refresh:

During a refresh cycle, the refresh counter is gated onto
the address outputs. All refresh cycles are RAS-onIY refresh (CAS inactive, RAS active). '
To minimize buffer delay, the information on the address
outputs is inverted from that on the address inputs.
QUTO-QUT7 do not need inverters or buffersunless additional drive is required.

1) Internal (failsafe) refresh
2) External (hidden) refresh
Both types of 8203 refresh cycles activate all of the RAS
outputs, while CAS, WE, SACK, and XACK remain
inactive.
, :Internal refresh is generated by the on-chip'refresh timer.
The timer uses the 8203 clock to ensure that refresh of all
rows of the dynamic RAM' occurs every 2 milliseconds
(128 cycles) or every 4 milliseconds' (256 cycles). If
REFRQ is inactive, the refresh timer will request a refresh
cycle ev~ry 10-16 micros.econds.

Synchronizer / Arbiter
The 8203 has three inputs, REFRQ I ALE (pin 34), RD (pin
32) and WR (pin 31). The RD and WR inputs allow an external CPU to request a memory read or write cycle, respectively. The REFRQI ALE input allows refresh'requests
to be requested external to the 8203.
All three of these inputs may be asynchronous with respect to the 8203's clock. The arbiter will resolve conflicts
between refresh and memory requests, for both pending
cycles and cycles in progress. Read and write requests
will be given priority over refresh requests.

System Operation
The 8203 is always in one of the following states:
a)
b)
c)
d)
e)

IDLE
TEST Cycle
REFRESH Cycle
READ Cycle
WRITE Cycle

Externalr~fresh isr.equestedvia the REFRQ input (pin34).
External refresh control' is not available when the Advanced-Read mode is sel~Cted. External refresh req~ests
are latched, then synchronized to the 8203 clock." "
The arbiter will allow the, ~efresh request to start a refresh
cycle only if the 8203 is not in tile middle of a cycle.
When the 8203 is in the idle state a simultaneous memory
request and external refresh request will result in the memory request being honored first. This 8203.characteristic
can be used to "hide" refresh cycles during system operation.A circuit similar to Figure 7 ca~ be usedt() decode
the CPU'~.instructiori fetcti status to generate an external
refresh request. Therefreshrequest is latched while the
8203 performs the instruction fetch; the'refreSh cycle will
start immediately aft~r, the memory cycle is completed,
even if the RDinputhas,not gone inactive. .if the CPU's
instruction decode time 'is 10';9 enough, the 8203 can complete the refresh cycle before the next memory request is
generated.
If tile 82()3 isnotin the idle~tate. then '~ simultaneous 'm~~'
ory request arid an external refresh request may result in
the re(resh request being honored first. "
,

The 8203 is normally in the IDLE state. Whenever one of
the other cycles is requested, the 8203 will leave the IDLE
state to perform the desired cycle. If no other cycles are
pending, the 8203 will return to the IDLE state.
'

Test Cycle
The TEST Cycle is used to check operation of several
8203 internal functions. TEST cycles are requested by activating the PCS, RD and WR inputs. The TEST Cycle will ",
reset the refresh address counter and perform a WRITE
, Cycle. The TEST Cycle should not be used in normal system operation, since it would affect the dynamic RAM refresh.

3-262

Figure 7. Hidden R&fresh

AFN-02144B

inter

8203

Certain system configurations require complete external
refresh requests. If external refresh is requested faster
than the minimum internal refresh timer (tREF), then, in ef:
fect, all refresh cycles will be caused by the external refresh request, and the internal refresh timer will never
generate a refresh request.

Read Cycles
The 8203 can accept two different types of memory Read
requests:
1) Normal Read, via the RD input
2) Advanced Read, using the S1 and ALE inpuis (16K
,mode only)
The user can select the desired Read request configuration via the B1/0P1 hardware strapping option on pin 25.

Pin 25
Pin 32
Pin 34
# RAM banks
Ext. Refresh

Normal Read

Advanced Read

Bl input
RD input
REFRQ input
4 (RAS 0.3)
Yes

OPI (+12V)
Sl input
ALE input
2 (RAS 2.3)
No

Write Cycles
Write cycles are similiar to Normal Read cycles, except
for the WE output. WE is held inactive for Read cycles, but
goes active for Write cycles. All 8203 Write cycles are
"early-write" cycles; WE goesactiv.e before CAS goes active by an amount of time sufficient to keep the dynamic
RAM output buffers turned off.

General System Considerations
All memory requests (Normal Reads, Advanced Reads,
Writes) are qualified by the PCS input. PCS should be stable, either active or inactive, prior to the leading edge of
RD, WR, or ALE. Systems which use battery backup:
should pullup PCS to prevent erroneous memory requests.
In order to minimize propagation delay, the 8203 uses an
inverting address multiplexer without latches. The system
must provide adequate address setup and hold times to
guarantee RAS and CAS setup and hold times for tlie
RAM. The tAD AC parameter should be used for this system calculation.
The BO-B1 inputs are similiar to the address inputs in that
they are not latched. BO and B1 should not be changed
during a memory cycle, since they directly control which
RAS output is activated.

Figure 8. 8203 Read Options
Normal Reads are requested by activating the RD input,
and keeping it active until the 8203 responds with an
XACK pulse. The RD input can go inactive as soon as the
command hold time (tCHS) is met.
Advanced Read cycles are requested by pulsing ALE
while Sris active; if S1 is inactive (low) ALE is ignored.
Advanced Read timing is similiar to Normal Read timing,
except the falling edge of ALE is used as the cycle start
reference.
If a Read cycle is requested while a refresh cycle is in
progress, then the 8203 will set the internal delayedSACK latch. When the Read cycle is eventually started,
the 8203 will delay the active SACK transition until XACK
goes active, as shown in the AC timing diagrams: This delay was designed to compensate for the CPU's READY
setup and hold times. Th~ delayed-SACK latch is cleared
after every READ cycle.
Based on system requirements, either SACK or XACK can
be used to generate the CPU READY signal. XACK will
normally be used; if the CPU can tolerate an advanced
READY, then SACK can be used, but only if the CPU can
tolerate the amount of advance provided by SACK. If
SACK arrives too,early to provide the appropriate number
of WAIT states, then either XACK or a delayed form of
SACK should be used.

The 8203 uses a two-stage synchronizer for the memory
request inputs (RD, WR, ALE), and a separate two stage
synchronizer for the external refresh input (REFRQ). As
with any synchronizer, there is always a finite probability
of metastable states inducing system errors. The 8203
synchronizer was designed to have a system error rate
less than 1 memory cycle every three years based on the
full operating range of the 8203.
A microprocessor system is concerned when the data is
valid after RD goes low. See Figure 9. In order to calculate
memory read access times, the dynamic RAM's A.C.
specifications must be examined, especially the RAS-access time (tRAC) and the CAS-access time (tCAC). Most
configurations will be CAS-access limited; i.e., the data
from the RAM will be stable tcc,max (8203) + tCAC
(RAM) after a memory read cycle is started. Be sure to
add any delays (due to buffers, data latches, etc.) to calculate the overall read access time.
Since the 8203 normally performs "early·write" cycles,
the data must be stable at the RAM data inputs by the- time
CAS goes active, including the RAM's data setup time. If
the system does not normally guarantee sufficient write
data setup, you must either delay the WR input signal or
delay the 8203 WE output.
Delaying the WR input will delay all 8203 timing, including
the READY handshake signals, SACK and XACK, which

3-263

AFN.()2144B

8203

may increase the number of WAIT states generated by the
CPU.
AD

~'-------':'-"'-';""""""'-----JI
,_---tRUlY

f4:

If the WE output is externally delayed beyond the CAS active transition, then the RAM will use the falling edge of WE
to strobe the write data into the RAM. This WE transition
should not occur too late during the CAS active transition,
or else the WE to CAS requirements of the RAM will not be
met.

The RASO-3, CAS, OUTO-7' and WE outputs contain onchip series damping resistors (typically 20m to minimize
overshoot.

l rI

'---l
CAS - - - - - - - - - \

Some dynamic RAMs require more than 2.4V VII..f. Noise
immunity may pe improved for these RAMs by adding pull·
up resistors to the 8203's outputs. Intel RAtvls do not require pull-up resistors.

Figure 9. Read Access Time

Figure 10. Typical 8088 System
3-264

AFN.Q2144B

8203

MUlTIBUSIO)
o

TYPE
SYSTEM
BUS
MRDe
MWTC

A~'. ~-:-":':"""':;'-".J

Figure 11. 8086/256K Byte System

ABSOLUTE MAXIMUM RATINGS'
Ambient Temperature Under Bias ........... . DoC to 70°C
Storage Temperature ................ -65°C to +150°C
Voltage On any Pin
With Respect to Ground ................ -D.5V to + 7V4
Power Dissipation ............................ 1.6 Watts

D,C. CHARACTERISTICS

'NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage ,to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification 'is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.'

TA = O°C to 70°C· VCC = 50V +
- 10% (5 OV +- 5% for 8203-3)· GND = OV

Forward Input Current
ClK, 64KI 16K Mode select
All Other Inputs 3

Vil = 0.65 V
10H = -1 mA
10H = -1 mA

VBIAS = 2.5V, VCC = 5V
TA = 25°C

Min

Reverse Input Current 3

VOL

Output low Voltage
SACK,XACK
All Other Outputs
Output High Voltage
SACK,XACK
All Other Outputs

Test Conditions
IC = -5 mA

F = 1 MHz

NOTES:

1.
2.
3.
4.

IR = 200 !LA for pin 37 (elK).
For test mode RD & WR must be held at GND.
Except for pin 36 in XTAl mode.
8203-1 and 8203-3 supports both OP1 and OP2, 8203 only supports OP2.

Resistor Tolerance: ± 5%

3·266

AFN-02144B

8203

A.C. CHARACTERISTICS
TJ = o·c to 70·C; VCC = sv ± 10% (S.OV ±

S% for 8203·3); GND = OV

Measurements made with respect to RASO-RAS3, CAS, WE, OUTO-OUT6 are at 2.4V and 0.8V. All
other pins are measured at I.SV All times are in nsec.

External Clock High Time

tpL

External Clock Low Time-above (» 20 mHz

tpL

External Clock Low Time-below (s) 20 mHz

tRC

Memory Cycle Time

tREF

Refresh Time (128 cycles)

Address Hold From RAS

Address Hold from CAS

RD, WR, ALE, REFRQ delay from RAS

REFRQ setup to RD, WR

PCS Setup to RD, WR. ALE

RD. WR. ALE to RAS Delay

tcc

RD. WR, ALE to CAS Delay

RD. WR setup to REFRQ

tCA

RD. WR. ALE to SACK.Delay

SACK, XACK turn·off Delay

CMD Inactive Hold after SACK. XACK

WAVEFORMS
Normal Read or Write Cycle

WAVEFORMS (cont'd)
Read or Write Followed By External Refresh

I-----~~-----~
I__----~'ic.----.r----..J

External Refresh Followed By Read or Write

___~:::===-=--t-MR-P:;:~~~~~~~~----------

WAVEFORMS (cont'd)
Clock And System Timing

A.C. TESTING LOAD CIRCUIT

Table 2. 8203 Output Loading.
All speCifications are
for the Test Load unless otherwise noted.
Pin

Test Load

SACK,XACK
OUTO-OUTS
RASO-RASS

lS0 pF
SO pF
224 pF
320 pF

NOTES:
1. tsc is a reference point only. ALE, RD, WR, and REFRQ Inputs do
not have to be externally synchronized to 8203 clock.
2. If tRS min and tMRS min are met then tCA, tCR, and tcc are valid,
otherwise tcs is valid.
3. tASR, tRAH, tASC, tCAH; and tRSH depend upon 80-81 and CPU
address remaining stable throughout the memory cycle. The ad·
dress inputs are not latched by the 8203.
4. For back·to·back refresh cycles, tRC max = 13tp
5. tRC max is valid only If tRMP min is met (REAO, WRITE followed
by REFRESH) or tMRP min is met (REFRESH followed by READ,
WRITE).
6. tRFR is valid only if tRS min and tRMS min are met.
7. txw min applies when RD, WR has already gone high. Otherwise
XACK follows RD, WR.
8. WE goes high according to tWCH or tWW. whichever occurs
first.

3·270

NOTE:

CL includes jig capacitance

9. tCA applies only when in normal SACK mode. de.
10. tcs applies only when in delayed SACK mode.
11. tCHS must be be met only to ensure a SACK active pulse
when in delayed SACK mode. XACK will always be activated
for at least txw (tp-25 nS). Violating tCHS min does not
otherwise affect device operation.

AFN·02144B

8203

The typical rising and falling characteristic curves for the
OUT. RAS. CAS and WE output buffers can be used to
determine the effects of capacitive loading on the A.C.

Timing Parameters. Using this design tool in conjunction
with the timing waveforms. the designer can determine
typical timing shifts based on system capacitive load.

A.C. CHARACTERISTICS FOR DIFFERENT CAPACITIVE LOADS
'.0 r-_ _~---'-+_---r_---r---.._--~---__r_---'.--r_---=C:.::A':rA::.;CIc.:.:TA:.::N::.;C~::::~"

0 .•

1--_+--+"~,+=3II1iii;;;::::j::~_--1-__--1----+----1~--l---+-----1

0.0L-_ _~_ _ _+_---L---~---L---~---~---L---~--~

5n0

-1

•.0r-_ _~---+_---r_--_r---.._--_.---__r_---r_---=~:.::.:rA::.;CIc.:.:~:.::N::.;CE::::~.F

NOTE:
Use the Test Load as the base cap~citance for estimating timing
shifts for system critical timing parameters.

MEASUREMENT CONDITIONS:
TA = 25°C
VCC = +5V
tp = 50 ns

3-271

Pins not measured are loaded with
the Test Load capacitance

AFN·02144B

8203

Example: Find the effect on tCR'and tcc using,32 21.64
Dynamic RAMs configured in 2 banks.
1. Determine the typical RAS and CAS capacitance:
From the data sheet RAS = 5 pF and CAS =5 pF.
RAS load = 80 pF + board capacitance.
CAS load = 160 pF + board capacitance.
.
AssUme 2 pF / in (trace length) for board capacitance and for this example 4 inches for RAS and
8 inches for CAS.

3-272

2. From the waileform diagrams, we determine that the·
. falling edge timing is needed for tCR and tCC. Next find
the. curve that best approximates the test load; i.e.,
68 pF for RAS and 330 pF for CAS.
3. Ifwe use 88 pF for RAS loading, then tCR (min.) spec
should be increased by· about 1 ns,· and tCR (max.)
spec should be increased by about 2 ns. Similarly if we
use 176 pF for CAS, then tcc (min.) should decrease
by 3 ns and tcc (max.) should decrease by about 7 ns.

AFN.()2144B

intel'·

8203

WAVEFORMS (cont'd)
Memory Compatibility Timing

8-8'1_ _
_ ~'----------------~::; JI~
.~0

8206/8206-2
ERROR DETECTION AND CORRECTION 'UNIT
• Detects and Corrects All Single Bit
, Errors

• Separate Input and Output
Busses-No Timing Strobes Required

'. Detects All Double Bit and Most
Multiple Bit Errors

• Expandable to Handle 80'Bit Memories

'. 52 ns Maximum for Detection; 67 ns
Maximum for Correction (16 Bit
System)
,
• Syndrome Outputs for, Error Logging
• 8206-2 TIming Optimized for 8MHz iAPX
186, 188,86, 88 and 8207-:2 Systems

• Supports Reads With and Without
Correction, Writes, Partial (Byte)
Writes, and Rea~-Modify-Writes
• HMOS Technology for Low Power
• 68 Pin Leadless JEDEC Package
• Single +5V Supply

The HMOS 8206 Error Detection and Correction Unit is a high-speed device that provides error detection and
, correction for memory systems (static and dynamic) requiring high reliability and perf~rma~ce. Each 8206
. handles 8 or 16 data bits and up t08 check bits. 8206's can be cascaded to provide correction and ~etection for
up to 80 bits of data. Other 8206 features include the ability to handle byte writes, memory initialization, and
, error logging. ,

, - - - - - j I-----CE
CB1/SY1 0·:'

Figure 1. 8206 Block Diagram
Intel Corporation A.aumea No Reaponalbilty for the Use of Any Circuitry Other "than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenae, are Implied.
@ INTEL CORPORATION. 1982,

MARCH 1982

3·274

Order Number: 20522D-004

SYNDROME
DECODER
AND
ERROR
DETECTION

¢=-:i==l

DATA
CORRECTION

WRITE

PARTIAL PARITY
GENERATOR

Figure 2. 8206-2 Block Diagram

Table 1. 8206 Pin D"scrlption
Symbol
010-15
CBI/SYlo
CBI/SYI1
CBI/SYI2
CBI/SYI3
CBI/SYI4
CBI/SYI5
CBI/SYI6
CBI/SYI7
DOIWDlo
DOIWDl1
DOIWDI2
DOIWDI3
DOIWDI4
DOIWDI5
DOIWDI6
DOIWDI7
DOIWDls
DOIWDlg
DOIWDl10
DOIWDl11
DOIWDI12
DOIWDI13
DOIWDI14
DOIWDI15

Data In: These inputs accept a 16 bit data word from RAM for error detection
and/or correction.

5
6
7
8
9
10
11
12

I
I
I
I
I
I
I

Check Bits. In/Syndrome In: In a single 8206 system, or in the master in a multi8206 system, thllse inputs accept the check bits (5 to 8) from the RAM. In a
single 8206 16 bit system, CB10-5 are used. In slave 8206's these inputs accept
the syndrome from the master.

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

Data Oul/Wrlte Data In: In a read cycle, data accepted ~10-15 appears at
these outputs corrected if CRCT is low, or uncorrected if RCT is high. The BM
inputs- must be high to enable the output buffers during the read cycle. Ina
write cycle, data to be written into the RAM is accepted by these inputs for compuling the write check bits. In a partial-write cycle, the byte not to be modified
appears at either 000-7 if BMo is high, or DOS-15 if BM1 is high, for writing to
the RAM. When WZ is active, it caus,es the 8206 to output all zeros at 000-15,
with the proper write check bits on CBO.

51
50
49
,48
47
46
45
44
42
41
40
39
38
37
36
35

3·275'

AFN-02009B

8206/8206-2

Table 1. 8206 Pin Description (Continued)
Symbol

Pin No.

Type

Name and Function

SYO/CBO/PPOo
SYO/CBO/PP01
SYO/CBO/PP02
SYO/CBO/PP03
SYO/CBO/PP04
SYO/CBO/PPOs
· SYO/CBO/PPOs
SYO/CBO/PP07

23
24
25
27
28
.29
30
31

0
0

Syndrome Out/Check Bits Out/Partial Parity Out: In a single 8206 system, or
in the master in a multi'8206 system, the syndrome appears at these outputs
during a read. During a write; the write check bits appear. In slave 8206's the
partial parity bits used by the master appe~ at these outputs. The syndrome is
latched (during read-modify-writes) by R/W going low.

Partial Parity In/Position: In the master in a multi-8206 system, these inputs
accept partial parity bitsO and 1 from the slaves. In a slave 8206 these inputs inform it of its position within the system (1 to 4). Not used in a single 8206
system.

· PPI2/NSLo
· PPI3/NSL1

15
16

I
I

Partial Parity In/Nuinber of Slaves: In the master in a multi-8206 system, these
inputs accept partial parity bits 2 and 3 from the slaves. In a multi-8206 system
these inputs are used in slave number 1 to tell it the total numberof slaves in the
system (1 to 4). Not used in other slaves or in a single 8206 system.

· PPI4/CE

I/O

Partial Parity In/Correctable Error: In the master in a multi-8206 system this
pin accepts partial parity bit 4. In slave number 1 only, or in a sinfl)! 8206
system, this pin outputs the correctable error flag. CE is latched by R going
low. Not used in other slaves.

PPls
PPls
PPI7

18
19
20

I
I
I

Partial Parity In: In the master in a multi-8206 system these pins accept partial
parity bits 5 to 7. The number of partial parity bits equals the number of check
bits. Not used in single 8206 systems or in slaves.

ERROR

Error: This pin outputs the error flag in I!.§ingle 8206 system or in the master of
a multi-8206 system. It is latched by R/W going low. Not used in slaves.

CRCT

Correct: When. low this' pin causes data correction during a read or read-'
modify-write cycle. When high, it causes error correction to be disabled,
although error checking is still enabled.

Strobe: STB is an input control used to strobe data at the 01 inputs and checkbits at the CBI/SYI inputs. The signal is active high to admit the inputs. The
signals are latched by the high-to-Iow transition of STB.

33
32

I
I

Byte Marks: When high, the Data Out· pins are enabled for a read cycle. When
low, th.!LPata Out buffers are tristated for a write cycle. BMo controls 000_7,
while BM1 controls 008-15' In partial (byte) writes, the byte mark input is low
for the new byte to be written.
.

R/w

. "·1

'Read/Write: When high this pin causes the 8206 to perform detection ai-ui
correction (if CRCT is low), When low, it causes the 8206 .to generate check bits,
On the high-to-Iow transition the syndrome is latched internally for read.modify-write cycles.

Write Zero: When low this input overrides the BMo-1 and R/W inputs to·cause
the 8206 to output alLzeros at 000-15 with the corresponding check bits at
CBOO_7' Used for memory initialization.

Master/Slave: Input tells the 8206 whether it is a master (high) or a slave (low) ..
S,lngla EDC Unit.: Input'tel!s the master whether it is operating as a single 8206
(low) or as the master in a multi-8206 system (high). Not used in slaves.
.

Table 2. 8206-2 Pin Description Differences over the 8206.
Pin

Type

Name and Function

5-10

Check Bits In: In an 8206-2 system, these inputsaccept the check bits (5
to 6) from the RAM.

SYO/CBOo
SYO/CB0 1
SYO/CB0 2
SYO/CB0 3
SYO/CB0 4
SYO/CB05

23
24
25
27
28
29

0
0
0
0
0
0

Syndrome Out/Check Bits Out: In an 8206-2 system, the syndrome
appears at these outputs during a read. During awrite, the write check
bits appear. The syndrome is latched (during read-modify-writes) by RIW
going low.

Correctable Error: In an 8206-2 system, this pin outputs the correctable
error flag.CE is latched by R/IN going low.

Write Zero: When low thisinput overrides the BMo_1 and R/W inputs to
I cause the 8206-2 to output all zeros at 000 _15 with the corresponding check

Symbol
CBlo-5

: bits at CBOo_.s. Used for memory initialization.
Strap High

Note: These pins have internal pull-up resistors. but if possible should be
tied high or low.

N.C.

30, 31

Note: These are no connect pins and should be left open.

FUNCTIONAL DESCRIPTION
DATA WORD BITS
The 8206 Error Detection and Correction Unit
provides greater memory system reliability through
its ability to detect and correct memory errors. It is a
single chip device that can detect and correct all
single bit errors and detect all double bit and some
higher multiple bit errors. Some other odd multiple
bit errors (e.g., 5 bits in error) are interpreted as
single bit errors, and the CE flag .is raised. While
some even multiple bit errors (e.g., 4 bits in error) are
interpreted as no error, most are detected as double
bit errors. This error handling is a function of the
number of check bits used by the 8206 (see Figure 2)
and the specific Hamming co.de used. Errors in
check bits are not distinguished from errors. in a
word.
For more information on error correction codes, see
Intel Application Notes AP-46 and AP-73.
Asi[lgle 8206 or 8206-2 handles8 or 16 bits cif data, and,
up to 5 8206's can be cascaded in orderto handle data
paths of 80 bits. Fora single 8206 8 bit system, the
018-15, OOIWOIS_15 and BM1 inputs are grounded. See
the .• Multi-Chip syste,ms section for information on
24-80 bit systems.
the 8206 has a "flow through" architecture .. It supports two kinds of error correction archit/lcture: 1)
Flow-through, or correct-always; and .2) Parallel, or
check-only. There are two separate 16-pin busses,

CHECK BITS

Figure 3~ Number of Check Bits ,Used by 8206

one to accept data fr()m the RAM (DI)anclthe other
to ,deliver corrected ,data to the system. bu~ (00/
WDI). The logiC is entirely combinatorial during a
readcycle. Thi.s is,in contrast to an architecture with
only one bus, with bidirectional bus drivers that
must first read the data and then b.e turned around to
output the corrected data. The latter architecture
typically requiresaddHional hardware (latches
and/or transceivers) and may be slower in a system
due to timing skews of control signals.
3·277

AFN-02009B

inter

,8206/8206-2

with the syndrome internally 'latched by R/W going
low. Only. that part of the word not to be modified is
output onto the DO pins, as controlled by the Byte
Mark inputs. That portion of the word to be overwritten is supplied by the system bus. The 8206 then
calculates check bits for the new word, using the
byte from the previous read and the new byte from
the system bus, and writes them to the memory.

READ CYCLE
With the Rm pin I)igh, d&ta is received from the RAM
outputs into the, 01 pins where it is optionally latched
by the STB signal. Check bits are generated from the
data bits and compared to the check bits read from
the RAM into the CBI pins. If an error is detected the
ERROR flag is activated and the correctable error
flag (CE) is used to inform the system whether the
error was correctable or not. With the BM inputs
high, the word appears corrected at the DO pins if
the error was correctable, or unmodified if the error
was uncorrectable.
If more than one 8206 is being used, thenthecheck
bits are read by the master. The slaves generate a
partial parity output (PPO) and pass it to the master.
The master 8206 then generates and returns the
syndrome to the slaves (SYO) for correction of the
data.
The 8206 may alternativel"ibe used in a "checkonly" mode with the CRCT pin left high. With the
correction facility turned off, the propagation,delay
'from memorY outputs to 8206 outputs is significantly shortened. In this mode the 8206 issues an
ERROR flag to the CpU, which can then perform one
of several options: lengthen the current cycle for
correction, restart the instruction, perform a diagnostic routine, etc.

READ-MODIFY-WRITE CYCLES'
Upon detection of an error the 8206 may be used to
correct the bit in error in memory. This reduces the
probability of getting multiple-bit errors in subsequent read cycles. This correction is handled by
executing read-modify-write cycles.
The read-modify-write cycle is controlled by the Rm
, input. After (during) the read cycle, the system
dynamic RAM controller or CPU examines the 8206
ERROR a'nd CE outputs to determine if a correctable
error occurred. If it did, the dynamic RAM controller
or CPU forces Rm low, telling the 8206 to latch the
generated syndrome and drive the corrected check
bits onto the CBO outputs. The corrected data is
available on the ,DO pins. The DRAM controller then
writes the corrected data and corresponding check
bits into memory.
'

A syndrome word, five to eight bits in length and
containing all necessary information about the existence and location of an error, is made available to
the system at the SYOo-7 pins. Error logging may be
accomplished by latching the syndrome and the
memory address of the word in error.

WRITE CYCLE
For a full write, in which an entire word is written to,
memory, the data is written directly to the RAM,
bypassing the 8206. The same data enters the 8206
through the WDI pins where check bits are generated. The Byte Mark inputs must be low to tristate
the DO drivers. The check bits, 5 to 8 in number, are
then written to the RAM through the CBO' pins for
storage along with the data word. In Ii multi-chip
system, the master writes the check bits using partial parity information from ,the s l a v e s . "
Inapartial write, partofthe data wOrd is overwritten;
and 'part is retained in memory. This is accompliShed
by performing a read-modify-write cycle: The com~
plete old word is read into the 8206 and corrected,
3·278

The 8206 may be used to perform 'read-modifywrites in one or two RAM cycles. If it is done in two
cycles, the 8206 latches are used to hold the data
and check bits from the read cycle to be used in the
following write cycle. The Intel 8207 Advanced
Dynamic RAM controller allows read-modify-write
cycles in one memory cycle. See the System
Environment section.

INITIALIZATION
A memory system operating with ECC requires some
form of initialization at system power-up in order to
set valid data and check bit information in memory.
The 8206 supports memory initialization by the write
ze'ro fl,lnction.By activating the WZ pin, the 8206 will
write a data pattern of zeros and the associated
check bits in the currentwrite cyCle. By thus writing
to all memory at power-up, a controller can set
memory to valid data and check bits. Massive memoryfailure, as signified by both data and check bits
all ories or zeros, willbe detected as an uncorrecta~
ble error.
AFN-Q2009B

8206/8206-2

MULTI-CHIP SYSTEMS
A single 8206 handles 8 or 16 bits of data and 5 or 6
check bits', respectively. Up to 5 8206's can be cascaded for 80 bit memories, with 8 check bits.
When cascaded, one 8206 operates as a master, and
all others as slaves. As an example, during a read·
cycle in a 32 bit system with one master and one
slave, the slave calculates parity on its portion of the
word-"partial parity" -and presents it to the master through the PPO pins. The master combines the
partial parity from the slave with the parity it calculated from its own portion of the word to generate

the syndrome. The syndrome is then returned by the
master to the slave for error correction. In systems
with more than one slave the above description continues to apply, except that the partial parity outputs
of the slaves must be XOR'd externally. Figure 4
shows the necessarY external logic for multi-chip
systems. Write and read-modify-write cycles are carried out analogously. See the System Operation section for multi-chip wiring diagrams.

There are several pins used to define whether the
8206 will operate as a master or a slave. Tables 3 and
4 illustrate how these pins are tied.

Figure 4. External Logic For Mult-Chip Systems

'nIble 3. Master/Slave Pin Assignments
. Pin No.

4
3
13
.14
15
16

Master

Pin Name
MIS!
. SEDCU
PPlo/POSo.
PPll/POSl
PPI2/NSLo
PPI3/NSL1'

'.
See Table 3.
NOTE:
Pins 13, 14, 15, 1~ have internal pull·up resistors and may b~ left as N.C. where specified as connecting to +5Y.

Tabl!! 4. NSL Pin Assignments for Slave 1
Pin
PPI2/NSLo
. PPlalNSLl

1
Gnd
Gnd'"

Number of Slaves
2

+5V
Gild

The timing specifications for multi-chip systems
must be calculated to. take a.ccount of the external
.XOR gating in 3, 4, and 5-chip systems: Let tXORbe
the delay for a single external TTL XOR gate. Then,
.the following equations show how to calculate the
relevant timing parameters for2-chip (ri=O), 3-chip
(1)=1), 4-chip (n=2), and 5-chip (n=2) systems:
. Data-in to corrected data-out (read cycle) =
TDVSV + TPVSV + TSVQV -I' ntXOR
Data-i n to error flag (read cycle) c=
TDVSV + TPVEV + ntXOR
Data-in to correctable error flag (read cycle) =
TDVSV + TPVSV + TSVCV -+ ntXOR
Write data to check-bits valid (full write cycle) =
TQVQV + TPVSV + ntXOR
Data-in to check-bits valid (read-mod-write cycle) =
TDVSV + TPVSV + TSVQV + TQVQV + TPVSV +
2ntXOR
Data-in to check-bits valid (non-correcting readmodify-write cycle) '=
'
TDVQU + TQVaV + TPVSV + ntXOR
I

.' HAMMING CODE
The 8206 uses a modified Hamming code which was'
optimized for multi-chip EDCU systems. The code is
such that partial parity is computed by all 8206's in

parallel. No 8206 require!! more time for propagation
through logic levels than any. other one, and hence
no one device becomes a bottleneck in the parity
operation. However, one or two levels of external
TTL XOR gates are required in systems with three to
five chips. The code appears in Table 5. The check
bits are derived from the table by XORino. or XNOR-.
ing together the bits indicated by 'X's In each row
corresponding toa check' bit. For example, check bit
o in the MASTER for data word 1000110101"101011'
will be "0." It should be noted that the 8206 will
detect the gross-error condition of all lows or all
highs.
Error correction is accomplished by identifying the
bad bit'and inverting it. Table 5 can also be used as
an error syndrome table by replacing the 'X's with
'1's. Each'column t!len represents a different syn"
drome word, and by locating the column corresponding to a particular syndrome the bit to be cor"
rected may be identified. If the syndrome cannot be
located then the error cannot be· ,corrected.· For .
example, if the syndrome word is 001101-11, the bit
to be corrected is ,bit 5in the slj:1ve one data word (bit
21). :
the syndromede~ociing'lsalsosummarized in Tables 6
and 7 which can be used for error· logging. By finding
the appropriate syndrome word (starting with bit zero,
the least significant 6)t), the result is either: 1) no error;
2) an identified (correctable) single bit error; 3) a
double bit error; or 4) a multi-bit uncorrectable error.

AFN-02009B

(
Table 5. Modified Hamming Code Check Bit Generation
Check bits are generated by XOR'ing (except for the CBO and CB1 data bits, which are XNOR'ed in the Master) the data
bits in the rows corresponding to the check bits. Note there are 6 check bits in a 16-bit system, 7 in a32-bit system, and
8 in 48-or-more-bit systems.
BYTE NUMBER·
BIT NUMBER
CBa =
CB1 =
CHECK CB2 =
CB3 =
BITS
CB4 =
CB5 =
CB6 =
CB7 =

0
1 234 5 6 7

xx-x-xx- x

x - x - - x - x ~
-xx-x-xx xxxxx--- x
---xxxxx -

- - - - - - - - - - - - -

1
OPERATION
1 2 3 4 5 6 7
XNOR
- - x - x - 'X - x x - x XNOR
XOR
- x - x - - x
x x - - - ..
XOR
- - - - x x x
XOR
x x x X x x x
XOR
.
XOR
- XOR
- - - a 1 1 1 1 1 1

3
OPERATION
2 345 6 7

XOR
XOR
XOR
XOR
XOR
XOR
XOR
XOR

-xxx-xx- - x x - - x - x x x - - x - x x x - x
- x x x - x x x - - x x - -

x x - - x - x x x
x x - - x x x x - - - x x x x x - -- - x

- - x x - - .- x - x - - - - x x x

1 1 1 1 222 2 2 222 2 2 3 3
67890 1 2 3 4 5 678 9 0 1

16 BIT OR MASTER

SLAVE #1

CfI

BYTE NUMBER
BIT NUMBER
CBa =
CB1 =
CHECK CB2 =
.CB3 =
BITS
CB4 =
CB5 =
CB6 =
CB7 =
DATA BITS

x x - x
x - x - x x - - x
x x x -

x x x x x x x x
x x x x x x x x -

--.

- -

5
2 345 6 7

6
7
8
2 3 4 5 6 7 01234567 01234567

x - x - x
- - x - x
x - x x - x - - x x - x
x
- x
-xxx x x - - - - - x - x - -

- x - x x - x - x x x x x. - - - x
x x
x - - x x x x - x x - - x x - -

x -

- x x x x x - - - - - x x
- - x x x x x x x
x x x x x x
- - - - x x x x x x x

x.~

x - x x

- x x
x x - x x
x x x - - x
x x x x - x - - - x x -- x

9
OPERATION
2 3 4 5 6 7

- x x x
- - - - x x x x x x x x

3 3 3 3 3 3 3 3 444 4 4 4 4 4 4 4 5 5 5 5 5 5 5 555 6 6 6 6 6 6 6 6 6 6 7 7 7777777 7
234 5 6·7 8 9 o 1 234567 8 9 a 1 2 3 4 5 678 9 a 1 2 3 4 5 6 7 8 9 a 1 234 5 678 9
SLAVE #2

SLAVE #3

SLAVE #4

XOR
XOR
XOR
XOR
XOR
XOR
XOR
XOR
'@

Table 6. 8206 Syndrome Decoding
Syndrome
Bits

7
0
0
0
0
0
0,
0
0
1
1
1
1
1
1
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
,1
0
1

N CBO CBl 0 CB2
'CB4 0
0
5 ~O
0
CBS 0
0 '11
0
13 14
0
15.
25, 0
0
CB6 0
51
0
52 55 ,0
64
0
29 31
0
30
0
0
37
0
0
CB7 0
0
43
47
45 46
0
0
79
0
59 75
0
0, 62
o·
0
63
o. u u 0 u
78
0
0
u 0
0
U
u 0
0
0
U
0
U
U.

1
0
1
0

0
1
1
0

0
6
19
'0
26
0
0
38
77
0
0

0
18
7,
0
12 .0
0' 21
0'
49
0
70
0
69
39
0
44
0
74
0
0
58
u 0
0
U
u 0
u 0
0
u

u
u
0

N = No Error
CBX;= Error in Check Bit X
X = Error in Data Bit X
o = Double Bit Error
U = Uncorrectable Multi-Bit Error

DATAMEMDRY
18 BITS

1
0
1
0
1 , 0
0
1
CB3
0
0
20
0
28
68

0
3
8
0
48
0
0
35
40
0
0

0
16
9
0
24
0
0
71
41
0
0

0, 0' 1
.j ,0
0
10' '0
0
66
0
22
0
27
0
65
0
53
32 ' 0
33
0'
0
36
0
42
0
u 0 73
56
0
U
0
61
0
u 0 u
0
u 0
0 u 0
u 0
u

0
17
.67
0
50
54' 0
34
0
0
U
0
U
U
0
57
0
0
U
u 0
0
U
0
U
u 0

SYSTEM ENVIRONMENT
The 8206 interface to a typical 32 bit memory system
is illustrated in Figure 5. For larger systems. the
partial parity bits from slaves two'to four must be,

CHECK BITS
7BI1;S

DATA MEMORY
18 BITS
DO'

CRCT
CDNTROL {.
LINES
.

WI
STB

8206

'MASTER

R/W
lIIiIo
BYTE
MARKS

ERROR
SIGNALS

.5V

EiilmJI

Figure'S. 32-BII 8206 System Interface
$282

8206/8206-2

XOR'ed externally, which calls for one level of XOR
gating for three 8206's and two levels for four or five
8206's.

RAM implementation using the 8206 and 8207. The
8206/8207 combination permits such features as automatic scrubbing (correcting errors in memory during refresh), extending RAS and CAS timings for
Read-Modify-Writes in single memory cycles, and
automatic memory initialization upon reset. Together these two chips provide a complete dualport, error-corrected dynamic RAM subsystem.

The 8206 is designed for direct connection to the Intel
8207 Advanced Dynamic RAM Controller. The 8207
has the ability to perform dual port memory control,
and Figure 6 illustrates a highly integrated dual port

DYNAMIC
RAM
32 BITS +
7 CHECK BITS

Figure 6: Dual Port RAM Subsystem with 8206/8207 (32-blt bus)

3-283

AFN.()20Q9B

8206/8206-2

Table 7.8206-2 Syndrome Decoding
Syndrome' 0
Bits
1
5 4 3 2
0

CBO CB1, D, CB2 ,D," D

No Error
Error in Check Bit X
Error in Data Bit X
Double Bit Error

The 8206-2 handles 8 or 16 bits of data. For 8 bit
8206-2 systems, the Dls-15, DO/WDls-15 and BM1 in. puts are grounded.
ifhe8206-:2 is designed for direct:connection to the
,lntel,8207,..2Advanced Dynamic RAM Controller. The
8207-2 has the ability to perform dual port memory
control, and Figure 7 illustrates a highly integrated
iAPX 186 RAM implementation using the 8206-2 and
8207-2. The 8206-218207-2 combination permits such
features as automatic scrubbing (correcting errors in
memory during refresh), extending RAS and CAS timings for Read-Modify-Writes in single memory cycles,
and automatic memory initialization upon reset.
Together these two chips provide a complete dual-port,
error-corrected dynamic RAM subsystems.

ARDY elK

~r-----~~----~----~

51
SOr-'------------------~
80186

Figure 7. iAPX 186 RAM Correct Always Subsystem with the 8206-2 and the 8207-2

3-284

AFN·020091 B

8206/8206-2

ciously choosing the proper data word to
generate the desired check bits, through
the use of the 8206 Hamming code. To
read out the check bits it is first necessary .
to fill the data memory with all zeros,
which may be done by activating WZ and
incrementing memory addresses with WE
to the check bits memory held inactive,
and then performing ordinary reads. The
check bits will then appear directly at the
SYO outputs, with bits CSO and CS1
inverted.

MEMORY BOARD TESTING
The 8206 lends itself to straightforward memory
board testing with a minimum of hardware overhead. The following is a description of four common
test modes and their implementation.
Mode O-Read and write with error correction.
Implementation: This mode is the normal
8206 operating mode.
Mode 1-Read and write data with error correction
disabled to allow test of data memory.
Implementation: This mode is performed
with CRCT deactivated.
Mode 2-Read and write check bits with error correctiol') disabled to allow test of check bits
memory.
Implementation: Any pattern may be written into the check bits memory by judi-

Mode 3-Write data, without altering or writing
check bits, to allow the storage of bit
. combinations to cause error correction
and detection.
Implementation: This mode is implemented by writing the desired word to
memory with WE to the check bits array
'held inactive.

S'l!!la
!I.!
co c·2
w

NOTE:
The 6206 and 6206-2 is packaged in a 66 pin JEDEC TYPE A hermetic chip carrier

Figure 8. 8206 and 8206-2 Pinout Diagram

3·286

. AFN-02009B

8206/8206-2

"NOTE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ......... O°C to 70°C
Storage Temperature ............... -65°C to +150°C
Voltage On Any Pin
With Respect to Ground ............ -0.5V to +7V
Power Dissipation .......................... 1.5 Watts

D.C. CHARACTERISTICS
Symbol

Parameter,

Min.

Power Supply Current
-Single 8206, 8206-2 or
Slave #1
-Master in Multi-Chip
or Slaves #2, 3, 4

lee

VIL1
VIH

(TA = O°C to 70°C, Vee = 5.0V ± 10%, Vss= GND)

10L = 8mA
10L = 2.0mA

V
V

10H = -2mA
10H = -O.4mA

Output LowVoltage
-DO
-All Others

VOH

Output High Voltage
-DO,CBO
-All Other Outputs

I/O Leakage Current
-PPI4/CE

± 20
± 10

/LA
/LA

O.4SV s; VI/O s; Vee

-DO/WDI 0_1S
Input Leakage Current___ 2
- PPI 0-3, 5-7, CBI6-7. SEDCU
-All Other Input Only Pins

± 20
± 10

/LA
/LA

OV s; VIN s; Vee

NOTES:
1. SEDCU (pin 3) and MIS (pin 4) are device strapping options and should be tied to Vee or GND. VI H min = Vee -O.SV and VI L max ~ O,SV.
2, PPIO.7 (pins 13-20) and CB16.7 (pins '11,12) have internal pull·up resistors and if left unconnected will be pulled to Vee,

A.C. TESTING INPUT, OUTPUT WAVEFORM

A.C. TESTING LOAD CIRCUIT

DEVICE
UNDER
TEST

'Ie,
RL

A.C. TESTING: INPUTS ARE DRIVEN AT 2.4VFOR A LOGIC "" AND QASV FOR
A LOGIC '0."' TIMING MEASUREMENTS ARE MADE AT 2.0V FOR A LOGIC "1"
AND 0 8V FOR A LOGIC "0 ..

CL INCLUDES JIG CAPACITANCE

--'----i-I-¥'~~TBHQV-lI
I

---;-1 X'WWffi'4 i '~",
---f---.!

1--1'+-1- - - T D v s v - - - - ! . 1

----1TDVQV'------,---!.1

=~j~!'X;0~:~~~R~~;:::;:::.~~;:::;:::.~;:::;:::.~rir-J~.-VALlD~---'k=
14 I
:.1'

TDVEV',
TOVCV

.":

,'I

____~I~I~~~TR~HCV~~~~~,I~--------I
CE

_----.Jxw//ffi//////A '

WAVEFORMS (Continued)
READ-MASTER/SLAVE

_-,--;..J,-i!---JlL.....J:A,

I
DD(SLAVEI---:-:-..-,.,

eAROR~~///////4:
1SVC::
_ -----, .' I . '
TAH~V
1
CE

SYQ(MASTER) _ _
SYI (SLAVE)

c~:--_ ---!..I- - - -

FULL WRITE-MASTER/SLAVE

I+---TFtYSv------+-l

RIW - - - - - . , - - , - -........

-.,---~~!
r----------~!.
DATA OUT

)05R2zt,
I-- --I ,.
--~~4

PPO(SLAVEI--------L..,I

WAVEFORMS (Continued)
READ MODIFY WRITE

f!=-'
N _ _ _ __

STB)
II
TSj'VI+,'-----TlVSL----!·1 I.....---TSLlX-----'----l"I
- j rI I
I
I I
I
R/W

1+,'..L-'-------·TDVRL.---_.I_TRVSV----+j

I
' I
X----VAL-t-'D:------.--:
I

,
I

C~: -{+-:--~-T-i_VA----lLlD:_ _-+-_~1
, I.
TRHQV---+--+-l"I I
1-+10..:.;...1----TOVQV
.,
.1'

DO/WD'~: ---~!
t--:

I'
I

SYO/CBO

1-1.---TRVSV------l"1 J-1 I-TRLSX
I I 1 1

I
TDXQX -l j- I

f1+
TQXQ~L
I.
,

--,-I----)(///$/4: ;e.....c.....L.~-L-f'~'---C_B_pc
SYN

I I
I
----TDVSV------J·I 1--TQVQV-!

WAVEFORMS (Continued)
READ MODIFY WRITE-MASTER/SLAVE

~.~~------------~:----~X
I
I- TIVSL -l ,

-----------+-:,-t:,
"

~_ _ _ _ _ _r!~~:~~~,~-----r--.~-LID----~~
I

;--r-r~~;r~~----~ /7~~I~-------------'~1

~~Z0~~{------VALI-D--~~

WAVEFORMS (Continued)
NON-CORRECTING READ .

:,t~·--~--~'--~~-:~-~--~i~)

---,---,.......;--WA .
1

(TA = O"C to 70"C, vee
all times are in nsec.)

= +5V ±·10%, Vss = ov, RL=22O, CL = 50 pF;
8206-2

ERROR Valid from RlWt

TRHCV

CEValid from R/Wt (Single 8206)

TRHQV

Corrected Data Valid from RlWt

TRVSV

SYO/CBO/PPOValid from

R/W

TDVEV

ERROR Valid from Data/Check Bits In

TDVCV

CE Valid from Data/Check Bits In

TDVQV

Corrected Data Valid from Data/Check Bits In

TDVSV

SYO/PPOValid from Data/Check Bits In

TBHQV

Corrected Data Access Time

TDXQX

Hold Time from Data/check Bits In .

TBLQZ

Corrected Data Float Delay

TSHIV

STB HiQh to Data/Check Bits In Valid

TIVSL

Data/Check Bits In to StB~ Set·up

TSLIX

Data/Check Bits In from STB~ Hold

ERROR Valid from Partial Parity In

_ 30

TPVQV

Corrected Data (Master) from Partial Parity In

'1,3

TPVSV

Syndrome/Check Bits Out from Partial Parity In

'1,3

TSVQV

Corrected Data (Slave) Valid from Syndrome

51 '

"'S-

TSVCV

CEValid from Syndrome (Slave number 1)

TQVQV

Check Bits/Partial Parity Out from Write Data In

TRHSX

Check Bits/Partial Parity Out from R/W. WZ Hold

TRLSX

Syndrome Out from R/W Hold

3
69

TQXQX

Hold Time from Write Data In

TSVRL

Syndrome OUt to RIW~ Set-up

TDVRL

Data/Check Bits In to RIW Set-up

TDVQU

Uncorrected Data Out from Data In

TTVQV

Corrected Data Out from CRCT!

Zero Out from WZl Hold

3
41

1
36

NOTES:
1. A.C. Test Levels for eeo and DO are 2.4Vand 0.8\1.
. 2. TSHIV is required to guarantee output delay timings: TOVEY, Tovcv, TOVQV, Tovsv. TSHIV + TIVSL guarantees a min STe pulse
width of 35 ns (45 ns for the 8206-8).
3. Not required for 8116 bit systems

3-294

AFN-020098

8207
ADVANCED DYNAMIC RAM CONTROLLER
• Provides All Signals Necessary to
Control 16K (2118), 64K (2164A) and
256K Dynamic RAMs
I!I Directly Addresses and Drives up to.2
Megabytes without External Drivers

• Supports Intel iAPX 86, 88, 186, 188, and
286 Microprocessors
.

• Supports Single and Dual-Port
Configurations
• Automatic RAM Initialization in All
Modes

• Provides Signals to Directly Control the
8206 Error Detection and Correction Unit

• Four Programmable Refresh Modes
• Transparent Memory Scrubbing in
ECC Mode

• Data Transfer and Advance Acknowledge
Signals for Each Port

• Supports Synchronous or
Asynchronous Operation on Either Port
ill +5 Volt Only HMOSII Technology for

High Performance and Low Power

The Intel 8207 Advanced DynamiC RAM Controller (ADRC) is a high-performance, systems-oriented, Dynamic
RAM controller that is designed to easily interface 16K, 64K and. 256KDynamic RAMs to Intel and other
microprocessor systems. A dual-port interface allows two different busses to independently access memory. When
configured with an 8206 Error Detection and Correction Unit the 8207 supplies the necessary logic for designing
large error-corrected memory arrays. This combination provides automatic memory initialization and transparent
memory error scrubbing.

VssCLK---..
RESET---..

l======) AOo_o

Alo.aC====)
AHo.o'----_ _ _ _1/
850-1'----_ _ _-'-1/

Figure 1. 8207 Block Diagram
Intel Corporation Assumes No Responsibility for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit
Patent Licenses are Implied. Information Contained Herein Supercedes Previously Published Specifications On These Devices From Intel.
J C'INTELCORPORATION,1983.

JULY 1983

3-295

ORDER NUMBER: 210463-003

8207

Table 1. Pin description
Symbol

Type

Name and Function

LEN

ADDRESS LATCH ENABLE: In 1wo·port configurations, when Port A is running with iAPX 286 Status
interface mode, this output replaces the ALE signal from the system bus controller of port A and
generates an address latch enable signal which provides optimum setup and hold timing for the 8207.
This signal is used in Fast Cycle operation only.
.

XAGKAI
AGKA

TRANSFER ACKNOWLEDGE PORTA/ACKNOWLEDGE PORTA: In non-EGG mode, this pin is
XAGKA and inidcates that data on the bus is valid during a read cycle or that data may be removed
from the bus duringa write cycle for Port A. XAGKA is a Multibus-compatible signal. In EGG mode,'
this pin is AGKA which can be configured, depending on the programming of th~ogram bit,
as an~r AAGK strobe. The SA programming bit determines whether the AAGK will be an
early EAAGKA or a late LAAGKA interface signal.

XAGKBI
AGKB

3 ..

TRANSFER ACKNOWLEDGE PORT B/ACKNOWLEDGE PORT B: In non-EGG mode, this pin
is XAGKB and indicates that data on the bus is valid during a read cycle or that data may be removed from the bus during a write cycle for Port B. XAGKB is'a Multibus-compatible signal. In EGG
mode, this pin is AGKB which can be configured, depending on the programming of theC,trogram
bit, as an XAGK or AAGK strobe. The SB programming bit determines whether the AA
will be
an early EAAGKB. or a late LAAGKB interface signal.

AACKN
WZ

ADVANCED Ac:KNOWLEDGE PORT AIWRITE ZERO: ,In non-EGG mode, this pin is AAGKA
and indicates that the processor may continue processing and that data will be available when required. This signal is optimized for the system by programming the SA program bit for synchronous
or asynchronous operation. In EGG mode, after a RESET, this signal will cause the 8206 to force
the data to all zeros and generate the appropriate check bits.

AAGKBI
RiW

ADVANCED ACKNOWLEDGE PORT B/READIWRITE: In non-EGG mode, this pin is AAGKB and
indicates that theprocessor may continue processing and that data will be available when required.
This signal is optimized for the system by programming the SB program bit for synchronous or asynchronous operation. In EGG mode, this signal causes the 8206 EOGU to latch the syndrome and
error flags and generate check bits.

OBM

DISABLE BYTE MARKS: This is an EGG control output signal indicating that a read or refresh cycle is occurring; This output forces the byte address decoding logic to enable all 8206 data output
buffers. In EGG mode, this output is also asserted during memory initialization and the 8-cycle dynamic
RAM wake-up exercise. In non-EGG systems this signal indicates that either a read, refresh or 8-cycle
warm-up is in progress.

ESTB

ERROR STROBE: In EGG mode, this strobe is activated when an error is detected and allows a
negative-edge triggered flip·flop to latch the status of the 8206 EDGU GE for systems with error
logging capabilities. ESTB will not be issued during. refresh cycles. ,

LOGK

LOCK: This input instructs the 8207 to lock out the port not being serviced at the time LOGK was
issued.
'

Vee

9
43

DRIVER POWER: +5 Volts. Supplies Vee for the output driverS.
LOGIC POWER: +5 Volts. Supplies Vee for the internal logic circuits.

CORRECTABLE ERROR: This is an EGG input from the 8206 EOGU which instructs the 8207 whether
a detected error is correctable or not. A high input indicates a correctable error. A low input inhibits
the 8207 from activating WE to write the data back into RAM. This should be connected to the GE
output of the 8206.

ERROR

ERROR: This is an EGG input from the 8206 EOGU and instructs the 8207 ihat an error was detected.
This pin should be connected to,the ERROR output of the 8206.

MUXI

MULTIPLEXER CONTROL/PROGRAMMING CLOCK: Immediately after a RESET this pin is used
to clock serial programming data into the POI pin. In nonmal two-port operation, this pin is used
to select memory addresses from the appropriate port. When this signal is high, port A is selected
and when it is low, port B is selected. This signal may change state before the completion of a RAM
cycle, but the RAM address hold time is satisfied.

PSEL

PORT SELECT: This signal is used to select the appropriate port for data transfer. When this signal
is high port A is selected and when it is low port B is selected.

PSEN

PORT SELECT ENABLE: This signal used in conjunction with PSEL provides contention-free port
exchange on the data bus. When PSEN is low, port selection is allowed 10 change state.

WRITE ENABLE: This signal provides the dynamic RAM array the write enable input for a write
operation.

Table 1 Pin Description (Continued)
Symbol

Type

Name and FunctiOn

FWR

FULLWRITE: This is an ECC input signal that instructs the 8207, in an ECC configuration, whether the present write cycle is normal RAM write (full write) or a RAM partial
write (read-modify-write) cycle.

RESET

RESET: This signal causes all internal counters and state flip-flops to be reset and upon
release of RESET, data appearing at the POI pin is clocked in by the PCLK output. The
states of the POI, PGTLA, PGTLB and RFRO pins are sampled by RESET going inactive
and are used to program the 8207. An 8-cycle dynamic RAM warm-up is performed after
clocking POI bits into the 8207.

CASO
GAS1
CAS2
CAS3

18
19
20
21

COLUMN ADDRESS STROBE: These outputs are used by the dynamiC RAM array to
latch the column address, present on the AOO-8 pins. These outputs are selected by
the BSO and BS1 as programmed by program bits RBO and RB1. These outputs drive
the dynamic RAM array directly and need no external drivers.

DRIVER GROUND: Provides a ground for the output drivers.
LOGIC GROUND: Provides a ground for the remainder of the device.

AOO
A01
A02
A03
A04
A05
A06
A07
A08

35
34
33
32
31
30
29
28
27

a
a
a
a
a

ADDRESS OUTPUTS: These outputs are designed to provide the row and column
addresses of the selected port to the dynamic RAM array. These outputs .drive the
dynamic RAM array directly and need no external drivers.

BSO
BS1

36
37

BANK SELECT: These inputs are used to select one of four banks of the dynamic
RAM array as defined by the program bits RBO and RB1.

ALO
AL1
AL2
AL3
AL4
AL5
AL6
AL7
AL8

38
39
40
41
42
44
45
46
47

ADDRESS LOW: These lower-order address inputs are used to generate the row
address for the internal address multiplexer.

AHO
AH1
AH2
AH3
AH4
AH5
AH6
AH7
AH8

48
49
50
51
52
53
54
55
56

ADDRESS HIGH: These higher-order address inputs are used to generate the
column address for the internal address multiplexer.
I
I
I
I
I

POI

PROGRAM DATA INPUT: This input programs the various user-selectable options in the
8207, The PCLK pin shifts programming data into the POI input from optional external
shift registers. This pin may be strapped high or low to a default ECG (POI =Logic "I")
or non-ECG (POI = Logic "0") mode configuration.

REFRESH REQUEST: This input is sampled on the falling edge of RESET. ·If it is high
atBESET, then the 8207 is programmed for internal refresh request or external refresh
request with failsafe protection. If it is low at RESET, then the 8207 is programmed for
extemal refresh without failsafe protection or burst refresh. Once programmed the RFRO
pin accepts signals to start an external refresh with failsafe protection or external refresh
without failsafe protection or a burst refresh.

·RFRO

ROW ADDRESS STROBE: These outputs are used by the dynamic RAM array to latch
the row address, present on the AOO-8 pins. These outputs are selected by the BSO
and BS1 as programmed by program bits RBO and RB1. These outputs drive the
dynamic RAM array directly and need no external drivers.

Table 1. Pin Description (Continued)
Pin

Type

ClK

Symbol

CLOCK:, This input provides the basic timing for sequencing the internal logic.

RDB

'61

READ FOR PORT B: This pin,is the re~ memory request command input for port B.
This input also directly accepts the S1 status line from Intel processors.

WRB

WRITE FOR PORT B: This pin is the write memory request command input for port B.
This input also directly accepts the SO status line from Intel processors.

' 63

PORT ENABLE FOR PORT B: This pin serves to enable a RAM cycle request for port
B. It is generally decoded from·the port address.

PCTlB

PORT CONTROL FOR PORT B: This pin is sampled on the falling edge of RESET. It
configures port B to accept command inputs or processor status inputs, If low after
RESET, the 8207 is programmed to accept command or iAPX 286 status inputs or
Multibus commands. If high after RESET, the 8207 is programmed to accept status
inputs from iAPX 86 or iAPX 186 processors. The S2 status line should be connected,
to this input if programmed to accept iAPX 86 or iAPX 186 status inputs. When
programmed to accept commands or iAPX 286 status, it should be tied low or it may
be used as a Multibus-compatible inhibit signal.

RDA

READ FOR PORT A: This pin is the read memory request command input for port A.
This input als6 directly accepts the S1 status line from Intel processors.

WRA

WRITE FOR PORT A: This pin is the write memory request command input for port A.
This input also directly accepts the SO status line from Intel processors.

PEA

PORT ENABLE FOR PORT A: This pin serves to enable a RAM cycle request for port
A. It is generally decoded from the port address.

PCTlA

PORT CONTROL FOR PORT A: This pin is sampled on the falling edge of RESET. It
configures port A to accept command inputs or processor status inputs. If low after
RESET, the 8207 is programmed to accept command or iAPX 286 status inputs or
Multibus commands. If high after RESET, the 8207 is programmed to accept status
inputs from iAPX 86 or iAPX 186 processors. The S2 status line should be connected
to this input if programmed to accept iAPX 86 or iAPX 186 status inputs. When
programmed to aGcept commands or iAPX 286 status, it should be tied low or it may
be connected to INHIBIT when operating with Multibus,

PES

Name and Function

GENERAL DESCRIPTION

FUNCTIONAL DESCRIPTION

The Intel 8207 Advanced Dynamic RAM Controller
(ADRC) is a rnicrocomputer peripheral device which
provides the necessary signals to address, refresh
and directly drive 16K, 64K and 256K dynamic RAMs.
This controller also provides the necessary arbitration circuitry to support dual-port access of the
dynamic RAM array.
The ADRC supports several microprocessor interface
options including synchronous and asynchronous connection to iAPX 86, iAPX 88, iAPX 186, iAPX 188, iAPX
286 and Mliltibus. .
This device may be used with the 8206 Error Detec~
tion and Correction Unit (EDCU). When used with the
8206, the 8207 is programmed in the Error Checking
and Correction (ECC) mode. In this mode, the 8207
provides all the necessary control signals for the
8206 to perform memory initialization and transparent error scrubbing during refresh.

3-298

Processor Interface
The 8207 has control circuitry for two ports Elach
capable of supporting one of several possible bus
structures. The ports are independently configurable allowing the dynamic RAM to serve as an interface between two different bus structures.

Each port of the 8207 may be programmed to run
synchronous or asynchronous to the processor clock.
(See Synchronous/Asynchronous Mode) The 8207
has been optimized to run synchronously with Intel's
iAPX 86, iAPX88, iAPX 186, iAPX 188 and iAPX 286.
When the 8207 is programmed to run in asynchronous
mode, the 8207 inserts the necessary synchronization
circuitry for the RD, WR, PE, and PCTl inputs.

210463-003

intJ

8207

The 8207 achieves' high performance (i.e. no wait
states) by decoding the status lines directly from the
iAPX 86, iAPX 88, iAPX 186, iAPX 188 and iAPX 286
processors. The 8207, can also be programmed to
receive read or write Multibus, commands or commands
from a bus controller. (See Status/Command Mode)
The 8207 may be programmed to accept the clock of

the iAPX 86, 88, 186, 188, or 286. The 8207 adjusts
its internal timing to allow for the different clock
frequencies of these microprocessors. (See
Microprocessor Clock Frequency Option)
Figure 2 shows the different processor interfaces to
the 8207 using the synchronous or asynchronous
mode and status or command interface.

I---------;~Wii elK
t-----~RD

Slow-Cycle Synchronous-Status Interface

Slow-Cycle Asynchronous-Status Interface

Slow-Cycle Asynchronous~Command Interface

Slow-Cycle Synchronous-Command Interface

Figure 2A. Slow-cycle Port Interfaces Supported by the 8207

3·299

210463-003

8207

NOTE:
ADDRESS LATCH ,NOT REQUIRED IN SINGLE·PORT MODE. '

Fast-Cy!=le Synchronous-Status Interface

NOTE:
ADDRESS LATCH NOT REQUIRED IN SINGLE,.PORT MODE •.

Fast-Cycle Asynchronous-Status Interface

SYNCHRONOUS 80286

Fast-Cycle Synchronous-Command Interface

Fast-Cycle Asynchronous-Command Interface.

Figure 2B. Fast-cycle Port Interfaces Supported by the 8207

Single-Port Operation

Dynamic RAM Interface· .

The use of an address latch with the iAPX 286 status
interface is not needed since the 8207 can internally
latch'the addresses with an internal signal similar in
behavior to the LEN output. This operation is active only
in single-port ~pplications when the processor is interfaced to port A.

The 8207 is capable of addressing 16K, 64K and 256K·
dynamic RAMs. Figure 4 shows the connection of the
processor address bus to the 8207 using the different
RAMs. The 8207 directly supports the 2118 RAM
family or any RAM with similar timing requirements
and responses including the Intel 2164ARAM.

Dual-Port Operation

The 8207 divide.smemory.into as many as four banks,
each bank having its own Row (RAS) and Column
(CAS) Address StrObe pair. This organization 'permits
RAM cycle interleaving and permits error scrubbing
during ECC refresh cycles. RAM cycle interleaving
overlaps'the start of.the next RAM cycle with the RAM
· Precharge period of the previous cycle. Hiding the
· precharge period' of one RAM cycle behind the data
access period of the next RAM cycle optimizes memory
•bandwidth and is effective as long as successive RAM
cycles occur in alternate banks.

The 8207 provides for two-port operation, Two inde-.
pendent processors may access memory controlled
by the 8207. The 8207 arbitrates between each of the
processor requests and directs data to or from the
appropriate port. Selection is done on a priority concept that reassigns priorities based upon past history. Processor requests are internally queued.
.
Figure 3 sh9WS a dual-port configuration with two
iAPX 86 systems interfacing to dynamic RAM. One of
the processor systems is interfaced synchronously
using the status interface and the other is. inter.faced
asynchronously also using the status interface.

Successive data access to the same bank will cause
the 8207 to waitJor.theprecharge time of the previous
.
.
"
RAM cycle.

!::I
EXTENDED MEMORY U SING STATUS.
PORT A-SYNCHRQNQ US;

eLK AACKA AOo.e RASo_3

NOTE:
*These components are not necessary when using the 80186 components. These functions are provided directly by
the 80186.
Figure 3. 8086/80186 Dual Port System

NOTES:
(1)Unassigned addresS input pins should be strapped high or low.
(2) AO along with BHE are used to select a byte within a processor word.
(3) Low order address bits are used as bank select il')puts so that consec,utive memory access requests
are to ~lIier-nate-baIiKs.-aliowirig bank interleaving of m~mory cycles.
Figure 4. Processor Address Interface to the 8207 Using 16K, 64K, and 256K RAMS

If not all RAM banks are occupied, the 8207 reassigns
the RAS and CAS strobes to allow using wider data
words without increasing the loading on the RAS and
CAS drivers. Table 2 shows the bank selection
decoding and the word expansion, including RAS and
CAS assignments. For example, if only two RAM banks
are occupied, then two RAg and two CAS strobes are
activated per bank. Program bitsRB1 and RBO.are not
used to check the bank select inputs BS1 and BSO. The
system design must protect from accesses to "illegal",
non-existent banks of memory, by deactivating the
PEA, PEB inputs when addressing an illegal bank. ,
The 8207 can interface to fast (e.g., 2118-10) or slow
(e.g., 2118-15) RAMs. The 8207 adjusts andoptimizes
internal timings for either the fast or slow RAMs as
programmed. (See RAM Speed Option).

Table 2.
Bank Selection 'Decoding anl:l
Word Expansion
Program
Bank
Bits
Input
RB1 RBO BS1 BSe

RAS/CAS Pair Allocation

RASo_3, CASO_3to Bank 0 •

Illegal

- RASo,1, CASo 1 to Bank 0 .

-1

' 1

RAS2,3, CAS2,3 .toBank 1

Illegal

' 1

Illegal

Memory Initialization

After programming, the 8207 performs eight RAM
"warm-up", cycles to prepare the .dynamic RAM for
proper device operation. During "warm-up" some
RAM parameters, such as tRAH, tASC, may not be
met. This causes no harm to the dynamic RAM array. If configured for operation with error correction,
the 8207 and 8206 EDCU will proceed to initialize
all of memory (memory is written with zeros with
corresponding check bits).

RASO,CASO to Bank 0
RAS1; CAS1 to Bank 1

3-302

RASo, CASo to Bank 0

RAS2, CAS2 to Bank 2

RAS3, CAS3 to Bank 3
210463-003

8207

Because the time to initialize memory is fairly long,
the 8207 may be programmed to skip initialization in
ECC mode. The time required to initialize all, of
memory is dependent on the clock cycle time to the
8207 and can be calculated by the following
equation:
TINIT = (~3) TCLCL

eq.1
if TCLCL

125 ns then TI NIT = 1 sec.

8206 ECC Interface
For operation with Error Checking and Correction
(ECC), the 8207 adjusts its internal timing and
changes some pin functions to optimize performance and provide a clean dual-port memory interface between the 8206 EDCU and memory. The 8207
directly supports a master-only (16-bit word plus 6
check bits) system. Under extended operation and
reduced clock frequency, the 8207 will support any
EGC master-slave configuration up to 80 data bits,
which is the maximum set by the 8206 EDCU. (See
Extend Option)
.
Correctable errors detected during memory read
Gycles are corrected immediately and then written
back into memory.
In a'synchronous bus environment, ECC system performance has been optimized to enhance processor
throughput, while inan asynchronous bus environment (the Multibus), ECC performance has been optimized to get valid data onto the bus as quickly as
possible. Performance optimization, processor
throughput or quick data access may be selected via
the Transfer Acknowledge Option.
The main difference between the two ECC implementations is that, when optimized for processor
throughput, RAM data is always corrected and an
advanced transfer acknowledge is issued at a point
when, by knowing the processor characteristics,
data is guaranteed to be valid by the time the processor needs it.
When optimized for quick data access, (valid for Multibus) the 8206 is configured in the uncorrecting
mode where the delay associated with error correction circuitry is transparent, and a transfer acknowledg~ is issued as soon as valid data is known to exist.
If the ERROR flag is activated, then the transfer acknowledge is delayed until after the 8207 has instructed the 8206 to correct the data and the corrected
data becomes available on the bus. Figure 5 illustrates a dual-port ECC system.

Figure 6 illustrates the interface required to drive the
CRCT pin of the 8206, in the case that one port (PORT
A) receives an advanced acknowledge (not Multibuscompatible), while the other port (PORT B) receives
XACK (which is Multibus-compatible).

Error Scrubbing
The 8207/8206 performs error correction during
refresh cycles (error scrubbing). Since the 8207 must
refresh RAM, performing error scrubbing during
refresh 'allows it to be accomplished without additional performance penalties.
Upon detection of a correctable error during refresh,
the RAM refresh cycle is lengthened slightly to permit the 8206 to correct the error and for the corrected
word to be rewritten into memory. Uncorrectable errors detected during scrubbing are ignored.

Refresh
The 8207 provides an internal refresh interval counter and a refresh address counter to allow the 8207 to
refresh memory. The 8207 will refresh 128 rows every
2 milliseconds or 256 rows every 4 milliseconds,
which allows all RAM refresh options to be supported. In addition, there exists the ability to refresh
256 row address locations every 2 milliseconds via
the Refresh Period programming option.
The 8207 may be programmed for any of four different
refresh options: Internal refresh only, External refresh
with failsafe protection, External refresh without failsafe
protection, Burst Refresh mode, or no refresh. (See
Refresh Options)
It is possible to decrease the refresh time interval by
10%, 20% or 30%. This option allows the 8207 to
compensate for reduced clock frequencies. Note
that an additional 5% interval shortening is built-in in
all refresh interval options to compensate for clock
variations and non-immediate response to the internally generated refresh request. (See Refresh Period
Options)

External Refresh Requests after RESET
External refresh requests are not recognized by the
8207 until after it is finished programming and preparing memory for access. Memory preparation includes 8 RAM cycles to prepare and ensure proper

pt,::i,Eii~~S~Tt.;~LE

_1-

CYCLE WITHOUT
WAIT STATES

-t
I

NOTE:
OR BANK PRECHARGE
1. The RAS and CAS shown in figure are different banks being accessed.

,Figure 14. iAPX 286/8207 Synchronous-Status Timing Programmed in non-ECC Mode, CO
Configuration (Read Cycle)

(A) PE SET·UP AND HOLD TIME REQUIREMENTS FOR FAST CYCLE,
SYNCHRONOUS OPERATION (80286 CMD/STATUS)

8207CLK

COMMAND/STATUS - - - - - - - - ,

~ ------------~---£==~~~

(B).PE TIMING REQUIREMENTS FOR FAST OR SLOW CYCLE
ASYNCHRONOUS OPERATION

Figure 15.

Memory Acknowledge
(AACK, XACK)
In system configurations without error correction,
two memory acknowledge signals per port are sup·
plied by the 8207. They'are the Advanced Acknowledge strobe (AACK) and the Transfer Acknowledge
strobe (XACK). The CFS programming bit deter-'
mines for which processor AACKA and AACKB are
optimized, either 80286 (CFS = 1) or 8086/186 (CFS
= 0). while the SA and SB programming bits optimize
AACK for synchronous operation ("early" AACK) or
asynchronous operation ("late" AACK).
Both the early and late AACK strobes are three
clocks long for CFS = 1 and two clocks long for CFS
= 0; The XACK strobe is asserted when data is valid
(for reads) or when data may beremoved (for writes)
and meets the Multibus requirements. XACK is

removed asynchronously by the command going inactive. Since in asynchronous operation the 8207
removes read data before late AACK or XACK is
recognized by the CPU, the. user must provide for
data latching in the system until the CPU reads the
data. In synchronous operation, data latching is unnecessary since the 8207 will not remove data until
the CPU has read it.
In ECC-based systems there is one memory acknowledge (XACK or AACK) per port and a programming bit
associated with each acknowledge. If the X programming bit is high', the strobe is configured as XACK, while
if the bit is low, the strobe is configured as AACK. As
in non-ECC. the SA and SB programming bits deter·mine whether the AACK strobe is early or late (EAACK
or LAACK).
Data will always be valid a fixed time after the occurrence of the advanced acknowledge. Table 9 sum.marizes the various tra~sfer acknowledge options.

210463-003

8207

8284A"
ROY 1 ~OTHER ACKINPUTS
READY
CLK

CLK

8288"
DEN
DT/!!
READY

NOTE:
,
'These components are not necessary when using the 80186. These functions are
provided directly by the 80186.
Figure 16. 8086/80186, 8207 Single Port Non-ECC Synchronous Systems

Figure 17. 8028,6 Hook-up ~o 8207 Non-ECC Synchronous System-Single Port.

3-316

210463-003

8207

Table 8. Processor Interface/Acknowledge Summary
CYCLE

Table 9. Memory Acknowledge Option Summary
Synchronous

Asynchronous

XACK

AACK Optimized for
Remote 60266

Multibus Compatible

Fast Cycle

AACK Optimized
for Local 60266
AACK Optimized
for Local 6066/166

AACK Optimized for
Remote 6066/166

Multibus Compatible

Slow Cycle

Test Modes
Two special test modes exist in the 8207 to facilitate
testing. rest Mode 1 (non-EGC mode) splits the
refresh address counter into two separate counters
and Test Mode 2 (EGG mode) presets the refresh
address counter to a value slightly less than rollover.

8207 will normally be set in Test Mode 2. Test Mode 2
eliminates memory initialization in EGG mode. This
allows quick examination of the circuitry which
brings the 8207 out of memory initialization and into
normal operation.

Test Mode 1 splits the address counter into two, and
increments both counters simultaneously with each
refresh address update. By generating external
refresh requests, the tester is able to check for
proper operation of both counters. Once proper individual counter operation has been established, the
8207 must be returned to normal mode and a second
test performed to check that the carry from the first
counter increments the second counter. The outputs
of the counters are presented-on the address out bus
with the same timing as the row and column addresses of a normal scrubbing operation. During
Test Mode 1, memory initialization is inhibited, since
the 8207, by definition, is in non-EGG mode.

General System Considerations

Test Mode 2 sets the internal refresh counter to a
value slightly less than rollover. During functional
testing other than that covered in Test Mode 1, the

The RASO-3, GASO_3, AOO-B, output buffers were
designed to directly drive the heavy capacitive loads
associated with dynamic RAM arrays. To keep the RAM
driver outputs from ringing excessively in the system
environment and causing noise in other output pins it is
necessary to match the output impedance of the RAM
output buffers with the RAM array by using series
resistors and to add series resistors to other control
outputs for noise reduction if necessary. Each application may have different impedance characteristics and
may require different series resistance values. The
series resistance values should be determined for each
application. In non-ECG systems unused EGG input
pins should be tied high or low to improve noise
immunity.
.
I
The 8207 is packaged in a 68-pin, leadless JEDEG type
A hermetic chip carrier.

~~%~~~~~~~~~~9;~g
CCCCCc««mm<
~~~~~~~;~~;~~~~~~

31 AD4
30 ADS
29 AD6
28 AD7
27 AD8

26 Vss
25 RAS3
24 RAS2
23 'RAS1
22RASO
21CAS3
20 CAS2
19 CAS1
18 C1iSli

NOTE:

8207 is packaged ina 68 pin JEDEC Type A hermetic leadles~ chip carrier.
Figure 19. 8207 Pinout Diagram

3·318

210463-003

8207

ABSOLUTE MAXIMUM RATINGS
NOTICE: Btress ab.ove those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum. rating
conditions for· extended periods may affect device
reliability.

Ambient Temperature
Under Bias .•........ "'.' ..... -0° C to +70° C
Storage Temperature .......... -65°C to +150°C
Voltage On Any Pin With
Respect to Ground .... ; ......... - .5V to + 7V
Power Dissipation ..................... 2.5 Watts

D.C. CHARACTERISTICS
(TA

= O°C to

= 5.0V ± 10% for 8207; ±

+ 70°C, VCC

Symbol

Parameter

5% for 8207-2 and 8207-5, Vss

Output Low Voltage
Output High Voltage

VROl

RAM Output
Low Voltage

VROH

RAM Output
High Voltage

Clock Input
Low Voltage

+0.6

VeH

Clock Input
High Voltage

Vee + 0.5

CIN

Input Capacitance

Leakage Current
-0.5
3.8 .

fc= 1 MHz

NOTES:
IOL

=8 mA and IOH =-0.2 mA (Typically IOL = 10 mA and IOH =-0.88 mAl
A.C. Testing Input, Output Waveform

A.C. Testing Load CirCUit

"RASO•3: t---::----'";;..;.;;.."V'.,...,~.-o
8207

CAS~3 r=~~~~~~~~

AO~8~~~~~~
Other Outputs ~.A."-__.():;:;::-

I
RRAS
RCAS
RAO
RL

= 39Q
= 39Q
= 22Q·
= 39Q

CRAS =
CCAS =
CAD =
CL =

X. :__

A.C. Testing inputs .(except clock) are driven at
2.4V for a logic "1" and 0.45V for a logic "0"
(clocK is driven at 4,OV and 0.45V for logic "1" .
and "0" respectively). Timing measurements are
made at 2.0V, 2.4V for logic" 1" and 0.8 V for logic
"0",
'

150 pF
150 pF
380 pF
150 pF
3·319

210463-003

8207

A.C. CHARACTERISTICS
(TA = OOC to 70°C; Vcc = +5V ± 10% for 8207; ± 5% for 8207-2, 8207-5; VSS= OV)
Measurements made with respect to RAS().3 , CASo-s ' AOo-s ' are at 2.4V and 0.8V. All other pins are measured
at 2.0V and 0.8V. All times in nsec unless otherwise indicated. Testing done with specified test load ..
CLOCK AND PROGRAMMING
8207 & 8207-2
Ref.

8207
15
8207
TClCU2-12
8207-2 TClCU2-12

230

8207
8207
8207-2

235

20
TClClJ3..3
TClCU3-3

PCTl, POI, RFRQ 10 RESET! Selup

125

200

TRTlPGX

PCTl, RFRQ 10 RESET! Hold

A.C. CHARACTERISTICS (Continued)
RAM WARM-UP,AND INITIAUZATION
40

1 641 TClWZl 1 WZ from ClK! Delay

SYNCHRONOUS I-IP PORT INTERFACE
11

TPEVCl

PE to ClK! Setup

TKVCl

RD, WR, PE, PCTl to ClK! Setup

TCLKX

RD, WR, PE, PCTL to CLK! Hold

TKVCH

RD, WR, PCTL to CLKt Setup

PE from RD, WR! Delay

TRWlPEX

PE to RD, WR! Hold

TRWLPTV

PCTl from RD, WR! Delay

TRWLPTX

PCTl to RD, WR! Hold

TRWLPTV

PCTl from RD, WR! Delay

TRWlPTX

PCTl to RD, WR! Hold

ASYNCHRONOUS I-IP PORT INTERFACE
15

,30
2TClCL+30

2TCLCl+50

TCLCL-20
TCLCL-30
TCLCL-30

8207
8207
8207-2

TClCL-50

TCLCL-30
2TCLCL+30
2TCLCL-20
3TCLCL+30

A.C. CHARACTERISTICS (Continued)

Al, AH, BS to ClK. Setup

35 + IASR

55 + IASR

TClA)(

Al, AH, BS TO ClKI Hold

Colu")n AO to CAS. Setup

tCAH

Column AO to CAS Hold

TClCSl

CAS. from ClK. Delay

TClCLJ2-25
75
TClCl-25

TClCLJ4-10
40
TClCLJ2-10
90

ns
ns
ns

11,13,14
12,13,14
1,13,14

ns
ns
ns
ns

11,13,15
12,13,15
1,13,15,16
13,15,17

ns
ns
ns

11,13,19,20
12,13,19
1,13,19

10,18
5
5
TClCLJ2-26

5
(See DRAM Interface Tables)

XACK. from ClK. Delay

TRWlTKH

XACKt from ROt, WAt Delay

TCLAKl

AACK. from ClK. Delay

TCLAKH

AACKt from ClK. Delay

TClDl

DBM from ClK. Delay

2TClCl-4O
TClCl+
TCl-40

FWR from WR. Delay 8207
8207-2

A.C. CHARACTERIS!ICS (Continued)
PORT SWITCHING AND LOCK

LOCK from RDI. WRI Delay

TRWHlKX

lOCK to RDt. WRt Hold

Failsafe RFRQ Pulse Width

TClCl+30

TClCl+50

TRFXCl

Single RFRO Inactive to ClKI Setup

TBRFH

Burst RFRO Pulse Width

2TClCl+30

2TClCl+50

NOTES:
1.
2.
3.
4.
5.
: 6.

7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
1?
18.
19.
20.
21.
22.

Specification when rrogrammed in the Fast Cycle processor mode (iAPX 286 mode).
Specification when programmed in the Slow Cycle processor mode (iAPX 186 mode).
Must be programmed in Slow Cycle processa mode.
RESET is internally synchronized to elK. Hence a set-up time is required only to guarantee its recognition at a particular clock edge.
The first programr:ning bit (POO) is also sampled by RESET going low.
TCLPDX is guaranteed if programming' data is shifted using PCLK.
WZ is issued only in ~CC mode.
1 RWVCL is not required for an asynchronous command except to guarantee its recognition at a particular clock edge.
Valid when programmed in either Fast or Slow C}Cle mode.
tASR is a user specified pa-ameter and its value should be added accordngly to TAVCL.
When programmed in Slow Cycle, mode and 125 ns
TCLCl· <; 200 ns.
When programmed in Slow Cycle mode and 200 ns " TCLCL.
Specification for Test load conditions.
tACO (actual) = tACO (specification) +0.06 (ACRA~ - 0.06 (ACcARl where AC = C (test load) - C (actual) in pF. (These are firS: order approximations.)
tAAH (actual) = IAAH (specification) + 0.06 (AC RAS) - 0.0:;!2IACAol where AC = C, (test load), - C (actual) in pF. (lhese are first order approximations.)
When programmed in Fast Cycle mode (8207 only) and 62.5 ns " TCLCl < 200 ns.
When programmed in Fast Cycle mode (6207 only) and 200 ns ~ TQ.CL.
tASA (actual) ~ tASA (specification) +0.06 (ACAO) - 0.025 (ACAAsl where AC ~ C (test load) - C (actual) in pF. (These are first order approximations.)
lASC (actual) ~ lASC (specification) +0.06 (ACAol- 0.025 (ACcAsl where AC ~ C (test load) - C (actual) in pF. (These are first order approximations.)
tASC is a functioo of clock frequency aoo thus varies with changes in frequency. A miminum value is specified.
See 8207 DRAM Interface Tables 14 - 18.
~:~~c~I:~~a~~::e~o~~ ~ccR~~nous and asynchronous FWFf.ln systems in which ~ is decoded directly fran the address inputs to the 8207. TClFV is

23. TFVCl is defined fa synchronous FWR:
24. TClFV is defined fa both synchronous and asynchronous FWA. In systems in which FWAis decoded directly from the address inputs to the 8207.
TCLFV is automatically guaranteed by TCLAV.
25. ERROR and CE are set-up to ClK' in fast cycle mode and ClKt in slow cycle mode.
26. ERROR is set-up to the same edge as AtW is referenced to. in AMW cycles.
27. CE is set-up to the same edge as WE is referenced 10 in RMW cydes.
28. Specification when TCl < 25 ns.
29. Specification when Tel ~ 25 ns.
30. Synchronous operation only. Must arrive by the second clock falling edge after the-clock edge which recognizes the command in order to be effective.
31. LOCK must be held active for the entire period the opposite port must be locked out. One clock after the release of LOCK the opposite port will be able to obtain
-.
access to memory.
32. Asynchronous mode only. In this mode a synchronizer stage is used internally in the 8207 to synchronize up LOOt TAWLLKV and TA'M1lKX are only
required for guaranteeing that LOCK will be recognized for the requesting port. but these parameters are not required for correct 8207 operation.
33. TFRFH and TBRFH pertain to asynchronous operation only.
34. Single AFAO cann~ by supplied asynchronously.
35. tR and tF are referenced from the 3.5V and 1.0V levels.

WAVEFORMS
Clock and Programming Timings

ClK
RESET _ J l - - - - ( ,

----~~~~----

PCTl

REFAESlit,llOOE
PROGRAMMING

----.I-~'
-~..,~-------...!:JI®
®
'_----'-J'

RAM Warm-up and Memory Initialization Cycles

FIRST RAM WARM-UP CYCLE

,\.......:...._------'

LAST RAM WARM-UP OR
INITIALIZATION CYCLE

NOTES:
1. When in non-ECC mode or in ECC mode with the TM2 programming bit on, there are no initialization cycles,
when in ECC mode with TM2 off, the dummy cycles are followed by initialization cycles.
2. The present example assumes a RAS four clocks long.

3-324

210463-003

8207

WAVEFORMS (Continued)
Sy{,chronous Port Interface

COMMAND MODEl
FAST CYCLE

AD, WJr, I5E"

COMMAND MODEl
FAST CYCLE
PCTl (INHIBIT)

COMMAND MODEl
FAST CYCLE
I INTERNAL INHIBIT

SLOW CYCLE
RD,WR

---t---t--""'

---t----t-----"t------------------

SLOW CYCLE

SLOW CYCLE
PCTl

INTERNAL
CYCLE REQUEST

NOTE:Refer to Tables 12, 13 when using A.C. timing waveforms

3-325

210463-003

8207

WAVEFORMS (Continued)
Asynchronous Port Interface

CLK~~~U\.J\
FAST/SLOW CYCLE,
RD,WR
-'

r-----------~------------.., f-

FAST CYCLE
INTERNAL INHIBIT

INTERNAL
CYCLE REQUEST

.....,<-

FAST CYCLE
PCTL (INHIBIT)

)

210463·003

8207

WAVEFORMS (Continued)
RAMlnteriace Timing
ECC and Non-ECC Mode
CLOCK 0
CLK

COMMAND

~ t-fJ ~~ ~~

...

INTERNAL
CYCLE REQUEST

ALO - ALa
AHo - AHa
BSo - BS1

-@-I-- r--@"':'"
RAS
l-

Note:
Dashed waveform indicates that either clock edge'may cause the signal transition

3-327

210463-003

8207

WAVEFORMS (Continued)
Port Switching and Lock Timing
ClK
COMMAND ____+_--~--_+--------~--+_--~------~
PORTA
COMMAND
PORT B

PSEl ______________.... 1
PORTA

PORTA

lOCK----------~~--------~~~----------~+_------~

r--:---1

FASTCYCLE.~--....I'·
INTERNAL lOCK
DISABLE

\.-

\._-----------

1-----('58:)------1
!lL.______..:.....
____________

...
, _ _ _....

NOTE:
Transients during MUX switching.

Refresh Request Timing
\

ClK - - - - '

FAilSAFE REFRES::;;H..:...___________
REQUEST

SINGLE REFRESH
REQUEST

-----------------------'

_ ______________ . r®

BURST REFRESH
REQUEST

®'S3

f~_@-----------210463·003

"nt_l®

I•• ~ .

8207

WAVEFORMS (Continued)
ECC Interface. Timing

ClK
COMMAND
(WR)

INTERNAL
. CYCLE REQUEST _ _1--'1
FASTCYClE--~~~~-+~~--4--S·r-4---~------+-FWR

SLOW CYCLE -----".j,-;....,;,..--,.;,...--.....,l,.-__--4_----,.;,...__-
FWR

ERROR _ _ _ _ _ _ _ _ _ _ _,~-_I_--4_~~---_I_~~------------------~----+_~~~--~----~~h

XACK _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~~~-----~--

CE _______________~____..;,..._~~_+..;,...~~~--_I_~,-

ESTB _ _ _~-------~---~4_~~---_I_~~

WE ______~_ _ _..;,..._~______~L__ _ _ _~
NOTE:
1, This parameter is set-up to the falling edge of clock, as shown, for fast cycle configurations. It is set-up to the
rising edge of clock if in slow cycle configurations. Table 13A shows which clock and clock edge these
signals are set-up in the
L column.

.Rm

2. CE is set'up to the same edge as WE' is referenced to in RMW cycles~

3-329

210463-003

.8207

CONFIGURATION TIMING CHARTS
The timing charts that follow are based on 8 basic
system configurations where the 8207 operates.

Tables 10 and 11 give a description of non-EGG a"nd
EGG system configurations based on the 8207's
POO, P03, P04, P010 and P011 programming bits.

Table 10. Non-ECC System Configurations
Non-ECC Mode· PDO=O
Timing ConI.

Table 11. ECC System Configurations

Using the Timing Charts
The notation used to indicate which clock edge
triggers an output transition is "nl" or "nl", where
"n" is the number of clock periods that have passed
since clock 0, the reference clock, and "1" refers to
rising edge and "I to falling edge. A clock period is
defined as the interval from a clock falling edge to
the following falling edge. Clock edges are defined
as shown below.
I

The clock edges which trigger transitions on each
8207 output are tabulated in Table 12 for non-ECC
mode, and Table 13 for ECC mode. "H" refers to the
high-going transition, and "L" to low-going transition; "V'~ refers to valid, and '''Vn to non-valid.
Clock 0 is defined as the clock in which the 8207
begins a memory cycle, either as a result of a port
request which has just arrived, or of a port request
which was stored previously but could not be
serviced at the time of its arrival because the 8207
was performing another memory cycle. Clock 0 may
be identified externally by the leading edge of RAS.
wnichis always triggered on 01.

Cycle iAPX286 mode, and thus it is not activated
by a refresh cycle, although it may be activated
by port A during a refresh cycle.
3, ADDRESS - COIl
becomes valid. "

is the time column address

4. In non-ECC mode the CAS, EAACK, LAACK and
XACKoutputs are not issued during refresh.
5. In ECC mode there are really seven types of
cycles: Read without error, read with "error, full
write, partial write withoul error, partial write with
error, refresh without e~ror, and refresh with error. These cycles may be derived from the timing
chart as follows:
A. Read without error: Use row marked 'RD, RF'.
B. Read with error: Use row marked" 'RMW'
except for EAACK and LAACK, which should
be taken from 'RD, RF'. If the error is uncorrectable, WE will not be issued.
C. Full write: Use row marked 'WR'.
D. Partial write without error: Use row marked
'RMW', except that DBM and ESTB will not be
issued.
E. Partial write with error: Use row marked
'RMW',except that DBM will not be issued. If
the error is uncorrectable,WE will not be
issued'.

F. Refresh without ~ Use row marked 'RD,
RF', except that ESTB, EAACK, LAACK, and
XACK will not be issued.

Notes for interpreting the timing charts.
1. PSEL - valid is given as the latest time it can
occur. It is entirely possible for PSEL to become
valid before the time given. In a refresh cycle,
PSEL can switch as defined in the chart, but it
has no bearing on the refresh cycle itself, but
only on a subsequent cycle for one of the
external ports.
2. LEN -low is given as the latest time it can occur.
LEN is only activated by port Aconfigured in Fast

3-331

G. Refresh with error: Use row marked 'RMW'
except that EAACK, LAACK,
and
XACK will not be issued. If the error is
uncorrectable WE will not be issued.

ES'fB:

6. XACK - high is reset asynchronously by command
going inactive and not by a clock edge.
7. MUX - valid is given as the latest time it can occur.

210463-003

8207

Table 13 A. Timing Chart - ECC Mode
,

Table 13 B, Timing Chal1- EC,C Mode

. ~OLADDR ESTB EAACI< LM,CK
en CYCLE 'v V L H L H L H
Co

5+ 4+ WR -2+ 2+
8+' 7+ WR -2+ 2+

8+ 10+ 7+ 10+ 7+ 10+ 9+ WR
4./.

5./.. WR -2'/' 2./.
8./. 10'/' 7./. 10./. 7./. 10'/' 9./. WR -2./. 2./.
3./.

6./.

H 3./. 2t 4t 3t RD -H
H 3./. 2t 4t 3./. WR -H
5t 6t 3./. 5./. 4t 6t 5./. WR -H
2./., 4./. 3t 5t 3t RD -H
H 3./. 2t 4t- !3./. WR -H
5t 6t 3.j. 5./. 4t 6.f 5./. WR -H
H 3./. 1t 3t 2·t RD -H
H 3./. 1t ~t 2i. WR -H
3t 4t H 3+ 2t 4t 3./. WR -H

3·333

2./.
2./.
2./.
,2'/'
2+
2./.
2'/'
2./.
2'/'

210483-003

"m
..:...I®
I•• ~,
'

8207

8207 - DRAM Interface Parameter Equations

WRITE CYCLE

Several DRAM parameters, but'not all, are a direct
function of 8207 timings, and the equations for
these parameters are given in the following tables.
The following is a list of those DRAM parameters
which have NOT been included in.thefollowing
tables, with an explanation for their exclusion.

tRC:.
tRAS:
tCAS:
tWCS:

READ, WRITE, READ-MODIFY-WRITE &
REFRESH CYCLES
response ;'parameter.
tRAC:
tCAC:
response parameter.
tREF:
See. "Refresh' Period' Options"
tCRP:
must be met only if CAS-only cycles,
which do not occur with' 8207, exist.
tRAH:
See "A.C. Characteristics"
tRCD:
See "A.C. Characteristics"
tASC:
See "A.C. Characteristics"
See ·~A.C. Characteristics"
tASR:
tOFF:
response parameter.

tDS:
tDH:
tDHR:

guaranteed by tRWC.
guar~nteed by tRRW.
guaranteed by tCRW.
_
WE always activated after CAS is activated, except in memory initialization,
hence tWCS is always negative (this is
important for RMW only) except in memory initialization; in memory initialization
tWCS is positive and has several clocks of
margin ..
system-dependent parameter.
system-dependent parameter.
~ystem-depe~dent parameter.

READ-MODIFY-WRITE CYCLE
tRWD:
tCWD:·

don'tcare in 8207 write cycles, but tabulated 'for 8207 RMW cycles.
don't care in 8207 write cycles, burtabulated for 8207 RMW cycles.

READ & REFRESH CYCLES
tRCH:

WE always goes active after CAS goes
active, hence tACH is guaranteed by,
tCPN.

Table ·14. Non-ECC Mode;- RD,RF Cycles
. Fast Cycle Configurations

Slow Cycle Configurations

3TCLCL-T35 2.5TCLCL- T35 2.5TCLCL- T35

6TCLCL--'T26. 6TCLCL-T26

2TCLCL-T34 . 2TCLCL- T34

2TCLCL-TCL 2TCLCL-TCL 2TCLCL-TCL 1.5TCLCL- TCL 1.5TCLCL-TCL
-T36-TBUF

t2:
t2:
t2:
t2:
t2:
t2:
t2:
t2:
t2:
t2:
!1

H- I::IM t2:
H-

al::l

H- I::IM t2:

t2:
t2:- I::IM tE
t2:- al::l tv
t2:- I::IM tE
t2:- al::l tv
t2:- l;tM tE
t2:- al::l tE
1\ H 1
xnw >lOYX
H-

al::l

I::IM
t2: to t2: to
tE H t2: to .:Il::1'al::l
~E
t2: to
I::IM
~~ t2: to
tE H t2: to t2: to .:Il::1'al::l
tv H tv H tE to
I::IM
t9 tE t5 t2: tE to .:Il::1'al::l
tv H tv H tE to
I::IM
.:Il::1'al::l
tE
t5 t2: t5 t2:
to
tv H tv H t2: to
I::IM
t5 t2: tv H t2: to .:Il::1'al::l
H, 1
H 1
l! 1\ 310AO
,>lOYY1 ,>lOYY3 HCCV10::>
~E

c:~

apow 003-uON - lJ8lfO 6u!w!.L 'S C:~ alq8.L

tv
tv
tv ~2: tv
tE
t5 t2: t5
t9
t5 t2: t5

tv
tv
tv
tE
t5
tv
t5
tv
t5
tE

to
to
to
to
to
to
to
to
to
to
H 1
SVH

t2:
t2:
t2:
t2:
t2:
t2:
t2:
t2:
t2:
t2:

to
to
to
to
to
to
to·
to
to
to
H 1
N31

tv
tv
tv
tE
t5
t9
t5
t9
t5
tv

to
to
'to
to
to
to
to
to
to
to

13Sd

tE to
tE to
tE to
t2: to
tv to
t5 to
tv to
t5 to
tv to
tE to
H
1
N3Sd

apow 003-uON - lJ8lfO 6u!WI.L 'V C:~ alq8.L

A&lJ\WINl~!t1Ill~I~&lJ©J

Table 15. Non-ECCMode - WR Cycle
Slow Cycle Configurations'

Fast Cycle Configurations
Parameter

4TCLCL-T35 2.5TCLCL- T35 2.5TCLCL- T35

3TCLCL+TCL 3TCLCL+TCL 3TCLCL+TCL 3TCLCL+TCL 3TCLCL+TCL

tWCR

4TCLCL+TCL 4TCLCL+TCL 4TCLCL+TCL 3TCLCL+TCL 3TCLCL+TCL

2TCLCL+TCL 2TCLCL+TCL 2TCLCL+TCL 2TCLCL-T36

3TCLCL-TCL 3TCLCL-TCL
-T36-TBUF

Table 16 A. ECC Mode -

RD, RF Cycles

Fast Cycle Mode
Parameter

3TCLCL- T26. 3TCLCL-T26

Table 16 B. ECC Mode -

RD, RF Cycles

Slow Cycle Mode
Parameter

tRP
tCPN

Notes

2TCLCL-T26

1.5TCLCL- T35 1.5TCLCL- T35 1.5TCLCL-T35

0.5TCLCL-T36 0.5TCLCL- T36 0.5TCLCL- T36
-TBUF

Table 17 A. ECC Mode - WR Cycle

Fasl Cycle Mode
Pa~ameters

7TClCl::"'T26 ,7TClCl- T26

tCAH

tClCl~T34 , 2TClCl-T34

7TClCl-T26 7TClCL- T26 .

tCRW

5TClCl-T34 ,5TCLCl- T34 '6TClCl- T34

3TClCl-T36 3TClCl-T36

Table 17 B. ECC Mode - WR Cycle
Slow Cycle Mode
Parameters

2.5TCLCL-T35 2.5TCLCI:.-T35 2.5TCLCL-T35

5TCLCL- T26 . 4TCLCL-T26

3TCLCL~TCL 3TCLCL-TCL 3TCLCL-TCL

3TCLCL-TCL 3TCLCL-TCL 3TCLCL-TCL
-T36-TBUF

-T36-TBUF

3TCLCL-TCL 3TCLCL-TCL 3TCLCL-TCL
-T36-TBUF

Table 18'A. ECC Mode....; Rr.,W '
,-

, :' ,- ,Fast Cy~le Mode

4TCLCl~ T35, 4TClCL-' T35

8TClCl~T34

10TClCl-:-T34 10TClCl- T34

'9TClCL- T26

9TClCl~T26

11TClCl-;:-T26 11 TClCl-'-T26

3!CU;:t-T26 3TClCl-'-T26

9TClCl-T26 -11TClCl-;-T26 11TClCl-'-T26 , 1

tCAW

'8TClCl-T~4

8TClCl-T34 10TCLCl- T34 ' 10TClCl- T34

7TClCl-T34 , 7TClCl-:-T34

3TGlCl-T36
,

3TClCl-T36 : 3TCl,Cl- T36

INTEL CORPORATION, 1982

3-341

Order Number: 210860-001

THE DESIGNER'S GUIDE TO iRAMs
The iRAM is the first of a new generation of VLSI memories; a complete dynamic RAM system on a chip. It combines the advantages of the simple static RAM interface
with the high density and low power dissipation of the
more economical dynamic RAM. While extraordinarily
complex internally (more than 150,000 active elements),
the external interface of the iRAM is just slightly different
from the interface of the 2K x 8 static RAMs that you have
used before. The iRAM can sit in a 28-pin Universal Site.
Designs based on the 2 I 86 are fully compatible with
EPROMs, EEPROMs, and 8K x 8 static RAMs. This is
an important consideration when designing for compatibility with multiple vendors. There are three differences
between the iRAM and SRAM interface. These are described below.
This guide is intended to show you how to use the iRAM.
It contains a functional summary of the iRAM, and
several simple microprocessor and microcontroller application examples. The enclosed access time matrix matches
the access speeds of the iRA,M to the operating speed of
any Intel microprocessor. For more detailed design infor-

mation, please consult Intel Application Note 132 "Designing Memory Systems with the 8K x 8 iRAM".

FUNCTIONAL DESCRIPTION
Just like a static RAM (or EPROM), access to the iRAM
is initiated by activating the Chip Enable control signal (CE).
The bar over CE indicates that it is an active low signal.
Activating CE latches the valid external addresses from
the system bus into the RAM. In simple systems, the
iRAM's address latches can eliminate the need to demultiplex the address/data bus from the processor.
Because the leading (falling) edge of CE starts the internal
sequencing of a memory cycle, a transition on the CE control signal must be glitch-free. Any spurious transitions
of CE may inadvertantiy select the iRAM at the wrong time,
resulting in a loss of data or worse. Figure 1 shows a simple circuit that ensures a clean transition for CEo
Once CE has been activated, the user may select one of
three different cycles; a Read cycle, a Write cycle or a False
Memory cycle. For a Read cycle, the read control line, called
OE (Output Enable), is activated. Data will remain valid

HI ORDER ADDRESS LINES

E
101M

TIMING WAVEFORMS

ALE
SYSTEM
CLOCK
ENABLE
CEx

-------~

Figure 1. CE Generator

3-342

CEx

at the RAM outputs as long as OEis held active -'- regardless of the state of CEo OE must return to the inactive state
prior to the next occurence of CEo
For a Write cycle, the write control line, called WE (Write
Enable), is activated after CE is enabled. The only requirement for a successful Write cycle is that data be valid at
the data inputs prior to WE going active. Some older processors, and the iAPX 86/88 in minimum mode, require
the addition of a single flip-flop to delay WE going active
until data is valid. Figure 2 illustrates an example of this
circuit and the associated timing waveforms. Finally, WE
must return to the inactive state prior to the next occurence
of CEo Note that OE and WE may not both go active during
the same cycle.
A False Memory cycle (FMC) occurs whenever CE is activated and neither OE nor WE go active. Addresses must
be valid at the iRAM prior to CE going active for an FMC.
The designer should be aware that some unique timing requirements exist for FMCs.
Because internal refresh may be occurring at any time, a
simple handshake procedure is used to notify the processor
of a delay in the cycle. If CE arrives while the iRAM is in
the midst of a refresh cycle, the ready output line (ROY)
will go inactive low. ROY is usually used to generate WAIT
states, and several ROY lines can be "OR'd" together at
the system level. When both the internal refresh cycle and
the requested external access cycle are complett:, ROY is
released and the processor finishes the transfer.

, An alternate version of the iRAM gives the designer Lon!plete control over access and refresh cycles. On the 2187
iRAM, the ROY output is replaced by the refresh enable
input (REFEN). To initiate a refresh cycle, REFEN is
activated. An internal refresh row address counter
provides the refresh address. Note that CE and 'R'EFEN
may not both go active during the, same cycle. This
synchronous iRAM is especially suited for use with
microcontrollers that can not accept a ready handshake
line.
In summary, there are three key interface requirements
that the iRAM designer must address:
• CE input must be glitch free
• WE input may have to be delayed until data is
valid
• ROY output is used to request a WAIT state during refresh/access overl.ap.
Some examples of how to use the iRAM are shown on the
following pages. A microcontroller application and two
different microprocessor systems are outlined, complete
with their major interface elements. The timing charts
match the operating speed of your processor with the appropriate iRAM access time.
A list of the iRAM literature that is available from Intel
is included in this guide. You can get this literature, and
answers to any questions about the availability and pricing
of the iRAM from your local Intel sales office.

DELAYED WE CIRCUIT

TIMING WAVEFORMS

DATA--~------~t=====~~~~~==~~==>------WE

Figure 2. Delayed WE

inter

•

8051 MICROCONTROLLER SYSTEM
RESET

• USES THE 2187 SYNCHRONOUS FtEFRESH iRAM

• .THE 2187 PROVIDES 8K BYTES OF EXTERNAL DATA MEMORY
• VERY SIMPLE INTERFACE
• NO ADDRESS LATCHES REQUIRED
• REFRESH OCCURS Dl)RING INTERNAL MICROCONTROLLER
. OPCODE FETCHES
• SYSTEM RUNS AT 12 MHz

3·344

intel
•
iAPX 88 MINIMUM MODE SYSTEM

• SIMPLE'MINIMUM MODE SYSTEM
• FOUR 2186 iRAMs PROVIDE 32K BYTES OF LOCAL STORAG.E
• CLEAN.CE GENERATED BY ONE TTL PACKAGE (74LSOO) , .
• ONE TTL PACKAGE (74LSOO) DELAYS WE UNTIL DATA IS VALID
,.

• THE iRAMs ARE IN UNIVERAL SITE SOCKETS - COMPATIBLE
WITH SRAMs AND EPROMS
• SYSTEM RUNS AT 5 MHz WITH NO WAIT STATES

iAPX 186 SYSTEM
10MHz

1200!!

.RoVI-------------+------,
"01------------,---+-----,
WR 1 - - - - - - - - - - - ; - . ,
I

MCS K

745112

74504

.r---+---t--:-------..,.--+---t--~ WE LOW

>---1-t----t----t-+----t--~ WE HIGH

_---y-.,--_-,-,_ _ _-,-,_ _---'

\--_.-"-"""-"-."

A,~·A,~

• TWO 2186 iRAMs PROVIDE 8K WORDS OF LOCAL STORAGE
• SIMPLE CIRCUITRY GENERATES A CLEAN CE
• DELAYED WE GATED TO SELECT ONE OR BOTH iRAMs FOR
8 OR 16 BIT DATA TRANSFERS
• READY HANDSHAKE LINE (ROY) CONNECTS DIRECTLY TO THE
PROCESSOR
• THE iRAMs UNIVERSAL SITE SOCKETS ARE COMPATIBLE WITH
SRAMs AND EPROMs

3·346

Microprocessor Operating Speed Vs. IRAM Access Time'
Microprocessor
Speed

2186·35
2186·35
2186·30

2186-35
2186-35
2186·35

80863

5 Mhz
8 MHz
10 MHz

2186·30

2186·35
2186·30
2186·25

2186·35
2186-35
2186-35

2186·35
2186·35
2186·35

2186·35
2186·35
2186·25

NOTES:
1. Buffer delays not included.
2. Due to its RDY response requirements, the 8085 cannot run without wait states.
3. Timing also applicable for the 8088 microprocessor.
4. Specifications for higher clock speeds not available. Memory requirements for 10 MHz and 15 MHz are extrapolated from 8 MHz specifications.

8051 iRAM REQUIREMENTS t
PROGRAM MEMORY'

8051 OPERATING SPEED (MHz)

DATA MEMORY'

9.3
2187·35

'I'

4
8051 OPERATING SPEED (MHz)

NOTES:
1 Buffers delays not included.
2 Runs ,with no wait slates over this speed range
3. The IRAM IS used to store both program code and data.
4. Program code resides in the 8051'5 internal ROM or in external ROM

3·347

2187·30
'1_2187.25'1

2186/2187 Literature' \
,

I, G~neral introductionto iRAM system design, includes

Desigrier's Guide to
the iRAM '

All i,RAM users

system block diagrarri~ar:'d timing matrix: system
speed vs, iRAM access tirrie,

Designing memory
systems ,with the 8K x 8
iRAM

Application Note 132 - d~scribes the designoi iRAM
memory systems, includesa description of internal
iRAM functions,
'

The iRAM in
microcontr.oller systems

How to design microcontroller memory systems using
ttie syn~hronous 21,87 iRAM, Availflble February 83,

All 2187 users

Smart Memories

Article Reprint 235 - overview of latest trends in smart
rT)emory technologies

All iRAM users

Memory Components
Handbook

Data sheets and Ap Notes for all Intel Memory
Components - includes 2186S, 2187 data sheets and
AP 132

All iRAM users

iRAM System
Reliability

A summary of the system ,testing performed 09 the
2186, Includes reliability data and test descriptions,

iRAM Arbiter
Reliability

Report on the reliability of the iRAM arbitration Circuit.

All iRAM users

, iRAM users who require
extensive qUillification
iRAM users who reqUire
extensive qualification

21,86/2187 Literature Guide by Topic

Topic
iRAM Tech.
Design

Title
2186S Data Sheet
2187 Data Sheet

.. '.,

AP-132Designing'
Systems with iRAMs
AR·235 Smart Memories
Designer's Guide
to iRAMs

iRAM Arbit,er Reliability.

210859·001

*
*

210443-001
210784-001
210860

*
*

Available
on Request

Available
on Request'

The iRAM in
microcontroller systems

Order
Number
210857·001

iRAM System Reliability

iRAM
Reliability

3-348

Available
Feb,83

EpPROMS (EbrlasRabled
rogramma e ea y
Only Memories)

APPLICATION
NOTE

Ap·154

April 1983

©INTELCORPORAnON.1983

4-1

APRIL 1983
ORDER NUMBER: 210970-002

AP·154

INTRODUCTION
With the introduction of the 27256 32K byte EPROM, a new generation of high density componentized software is possible. Intel's process and product technology advances have increased EPROM memory storage capabilities from 2K bits to
256K bits. This non-volatile memory can allow the designer a more reliable, user-friendly system. Since it is produced in the
28 pin JEDEC-approved Intel universal site, the 27256 can easily be designed into existing printed circuit boards.
Figure 1 shows the evolution of Intel's EPROM family. The new generation 27256 brings with it improved performance and state-of-the-art reliability. The absence of mKI, replaced by A14, and a lower programming voltage
(l2.5V) highlight the additions accompanying the 27256. Advanced technology from the 27256 will soon bring
enhanced performance to lower density EPROMs, specifically the 2764A and 27128A. This document concerns programming characteristics of the 27256, concentrating on those factors which will be new to the EPROM memory
designer.

THE inteligent Programming™ ALGORITHM
The inteligent Programming™ Algorithm was developed as an improved alternative to the 50 msec per byte programm~
ing techniques for Intel's 2764 and 27128 EPROMs. By taking advantage of the variable programming times required by
the cells in an EPROM array, programming speed increases of 5 or 6 times have been achieved. The success of this
, algorithm, coupled with the long programming times which would be inherent in programming the 27256 with a 50 msec
. per byte algorithm, has prompted Intel to develop a new 27256 inteligent Programming™Algorithm specifically tailored
to the requirements of the customer.
The 27256 programming algorithm is similar to the inteligent Programming Algorithms used for Intel's 2764 and
27128 EPROMs. It is now available as a standard feature in many PROM programmers. -This new programming
;algorithm is fast and guarantees that each cell has been programmed reliably.

A12
A7
As
As
A!
A3
A2
Al
Ao
00
01
O2
Gnd

A12
A7
As
As
A!
A3
A2
Al
Ao
00
01
O2.
Gnd

A12
A7
As
As
A!
A3
A2
Al
Ao
00
01
62
Gnd

~
N

A7
As
As
A!
A3 .
A2
Al
Ao
00
01
O2
Gnd

...riI.....

Vee

PGM
A13
As
Ag
All
OE
Al0

A14
A13

PGM
N.C.
Vee
Vee
As
As
As
Ag
Ag
Ag
Vpp
All All
OE OE/Vpp OE
Al0
Al0 Al0
CE
CE
CE
'07
07
07
06
Os
Os
Os
Os
Os
04
04
O~
03
03
03

A7
As
As
A!
A3
A2
Al
Ao
00
01
O2
Gnd

Figure 1. Intel Universal Memory Site for EPROMs

4·2

CE
07
06
Os
04
03

As
As
All
OE
A10
CE
07
06
Os
04
03

Ap·154

The 27256 inteligent Programming Algorithm shown in figure 2 is a feedback control loop. In examining this diagram,
three distinct characteristics can be seen. First, the programming voltage has been reduced from 21 ±0.5 volts, as was
required on earlier generation 2764 and 27128 EPROMs, to 12.5 ± 0.5 volts. In all cases the Vpp voltage should never
exceed 14 volts, and 0.1 microfarad capacitor Should be placed between Vpp'and gcound to ins~re proper decoupling: The technology advances implemen.ted iri the27256 allow the programming voltage'to be reduced while taking ad 7
vantage of the performance of the p'rogrammed'cell. The second characteristic that should be noted is the maximum
number of Ims pulses which are applied throughout the closed loop program~ing algorithm. As shown, 25 iterations
of the loop is'the maximum nu~ber allowed. Intel's reliability data indicate that 25 iterations is suffiCient to reliably,
program each of the EPROM bits in the array. The last characteristic which should be mentioned isihe insertion' of a
byte verify after the iteration count has been maximized. This will save time by failing any device which may not verify
correctly after 25 onemsec pulses.
'

DEVICE
FAILED

Figure 2. inteligent Programming™ Algorithm

4-3

Ap·154

27256 PROGRAMMING WAVEFORMS
With the replacement·Df the PGM signal by AI4'Dn Pin' 27, ch~ngesa:re req~ired,in the manner in which the 27~56 is
prDgramriled .. Figure 3 shows the wavefDrms required to. progralj1 the 27256. As illustrated, the 27256 will be placed in
tile prDgram mDdewhen Vpp is'set to. 12.5 vDlts, and CE is pulsed to VI~. The'verify DperatiDn will then be selected
with CE at VIH, and OE held at VIL.This r~sults frDm multiplexing bDth'ihe ~hip enable fimctiDn imd the prDgramming enable fundiDnDntD Pin 20. The Vpp level, either 5 vDlts Dr 12.5 volts, gates whichfunctiDn isselected. Table 1 indicates the varia,us mDdes Df operation Df a 27256.
' , ' , '
In Dn-bDard gang prDgramming ap~licatiDns, care niust be taken nDt to. enable the outputs Df all resident 27256 devices
while in the verify mode. A CDmmDn OE signal cDuld cause bus cDntentiDn. AR-294 will discuss this issue, in detail.

PROGRAM

ADDRESSES V I : = = , -

NDTES:
1. ALL TIMES SHDWN IN [I ARE MINIMUM AND IN I'SEC UNLESS DTHERWISE SPECIFIED.
2. THE INPUT TIMING REFERENCE LEVEL IS .8V FDR A Vll AND 2V FQR A VIH.
3. tOE AND tOFP ARE CHARACTERISTICS QF THE DEVICE BUT MUST BE ACCQMQDATED BY THE PRQGRAMMER.
4. WHEN PRQGRAMMING THE 27256 A O,1"F CAPACITQR IS REQUIRED ACRQSS Vpp AND GRQUND TO. SUPRESS SPURIQUS
VQLTAGE TRANSIENTS WHICH CAN DAMAGE THE DEVICE,

Figure 3. Intellgent Program,mlJlg™Waveforms

4·4

Ap·154

Table 1. 27256 Operational Modes

OUTPUTS
(11·13,
15·19)

intellgent Programming

inteligent Identifier

VIL

NOTES:
1. X can be VIH or VIL·
2. VH = 12.0V ± O.5V

SUMMARY
The introduction of the 27256 continues Intel's leadership in high density EPROM storage capability. With this density increase comes the ability to design in system firmware, creating a more reliable, user-friendly environment for the
computer operator. The inteligent Programming Algorithm developed for Intel's 2764 and 27128 EPROMs, provides
many benefits, including lower costs, which r.esult from higher system manufacturing throughput. In line with this
strategy, the 27256 inteligent Programming Algorithm was designed to meet the technology requirements of the new
device. With this algorithm, the 27256 may be programmed according to the waveforms shown in figure 3, ensuring
programming reliability and efficiency.

MARCH 1983
ORDER NUMBER: 210988·001 .

4·6

Technical articles,_ _ _ _ _ _ _ _ _ __

E-PROMs graduate to 256-K density
with scaled n-channel process
With 32-K bytes per chip, erasable programmabl~ read-only memory
can carry application software for business and personal computers
by M. Van Buskirk, M. Holler, G.Korsh, B. Lee, S. Lee,
D. Tang, G. Teng, S. Fouts, P. Dang, and W. Fisher,lnteICorp .. Santa Clara. Calif.

o Since

the introduction of the 2-K 1702 in 1971, the
erasable programmable read-only memory has shaken off
its reputation as a mere prototyping tool and emerged as
a major commodity, worth'some $240 million last year in
the U. S. alone. Central to that growth, a heady pace of
process and circuit innovations has doubled E-PROM densities everyone to two years.
The advent of the 256-K chip-exemplified by the
27256 from Intel-signals the crossing of key technical
hurdles and with it an open path to accelerated development of megabit and larger arrays. Though clearly the
child of earlier generations of E-PROMS, the part has been
thoroughly scaled down to achieve thinner oxides and
minimum features of 1 micrometer. New sensing and
decoding circuitry are incorporated as well.
Along the path to even larger arrays, the price per bit
of E-PROMs will. continue to drop, closing in on that of
ROM, the least expensive semi'conductor storage. Indeed,
the 256-K ROM. has only a year's jump on the 27256. The
cost of E-PROM is projected at just .50% more than that
of ROM in 1985: 6 versus 4 millicents per bit.
Achieving 256-K density in an E-PROM calls for a host
of advances working in concert, dramatic scaling down
of device dimensions being only the most obvious one.
Processing changes also accompany the smaller geometries and thinner layers. New designs for the decoding
and sensing circuitry cope with the worsening problem of
statistical variations in device parameters among the
more than quarter million. bits in the array.
The flexibility of alterable nonvolatile storage coupled
with the economy of high chip density promises intriguing possibilities for the architect of microsystems, particularly portable computers for the mass market. As the
table on page 93 suggests, significant system and application software fits in a very few 256-K arrays. For example, two or three chips can carry a Pascal compiler and a
sophisticated word-processing program.
To the user of a machine incorporating such firmware,
the friendliness and convenience of fast, 200-nanosecond
memory accessed with the push of a button contrasts
sharply with the fuss and delay of floppy disks. Further,
for the end user and equipment maker alike, E-PROM
continues. to offer compelling advantages over ROM,_advantages that will come at an ever lower premium as 'EElectronics/ February 24, 1983

4-7

PROMs succeed in catching up with ROMs in density.
Speeding a product to market, for example, often
means last-minute software changes, a costly and impractical requirement with' mask-programmable chips, but a
simple matter for E-PROMS. Similarly, the E-PROM can
hold down the costs and delays involved in updating
programs or in correcting those last few bugs that somehow made it out into the field.
Scaling chip geometries down in size has been the
primary instrument of progress in all types of integrated
circuits in the last 6 to 10 years. The first major scaling
down of E-PROMS occurred in 1980 with the introduction

1. Scaled. Two-micrometer design rules squeeze the E-PROM cell
down to 6 by 6 pm. The active channel area, beneath the floating
polysilicon gate. is just 1 by 1.2 pm. The n' regions are 0.5 pm deep'.

REFERENCE
VOLTAGE

ERASABLE
PROGRAMMABLE
READ-ONLY
MEMORY CELL

WORD LINE 0

WORD LINE 1

ZERO-THRESHOLD
DEVICE

ENHANCEMENTMODE DEVICE

WORD LINE 511

ARRAY
COLUMN

2. Sensing scheme. Read circuitry on the 256-K chip tolerates process variations: Reference cells for each word line monitor read currents;
identical geometry for the array and reference load transistors ensures a constant current ratio for sensing_

of the 2764 64-K part with a 159-square-micrometer cell
and H-MOS (high-performance MOS) peripheral circuits.
The major technology advance prior to that was the
conversion in 1977 to n-channel MOS technology with
depletion-mode devices for the 16-K 2716, a move that
made operation possible from a single 5-volt power
supply.
A completely redesigned process and second major
scaling in 1982 have resulted in another leap in density
and performance for E-PROMs, producing a 256-K array
with a' 6-by-6-fLm cell, for a chip size of just 28,500
square mils. The floating-gate storage transistor, with a
channel effectively 1 I-'m long by 1.2 I-'m wide, ~mploys \!
first oxide 325 angstroms thick and a second of 400 A
(Fig. I). The peripheral circuitry, with a 0.5-picojoule
speed-power product, is equivalent to chips built in HMOS II, a second-generation high-performance MO~ technology that uses 2-m channel lengths and 400-A gate
oxides for minimum gate delays of 0.4 ns.

The practical constraint of maintaining the same 5-v
power supply used in previous technologies while'scaling
transistor sizes stresses the materials constituting the devices: both substrate and gate dielectrics are exposed to
much higher electric 'fields. The fabrication process must
build a margin of safety into the chip to preventunwantedeffects like time-dependent oxide failure, pn-junction
breakdown, and parasitic Mos-transistor action between
adjacent diffused regions.
In E-PROMs, the high voltage required for programming the cells further aggravates the situation. In fact, in
the storage transistor, the _oxide surrounding the ,floating
gate must be flawless, or else electrons leak off, losing the
stored data. For that reason, the programming voltage in
the 27256 is scaled down to 12.5v (see "Scaling down
the E-PROM cell," opposite). With that scaling, the 400-A
oxides in the transistors, of the peripheral circuitry that
rO,ute the programming voltage to the array experience
an electric field of 3.25 megavolts per centimeter, roughElectronics/ February 24, 1983

4-8

SCALING DATA FOR THE 256 K ERASABLE PROGRAMMABLE READ ONLY MEMORY

Electronics / February 24, 1983

4·9

TO LEFT SIDE
ROW'SELECT - - - - . . . . , . - - - - -......~,....;....;.,
CIRCUITS

'--t-----

WORD lINE·O.

ROW
ADDRESSES

1....-1-.....- ...- _ WORD LINE 16

1~ R~~LlbWv~i:E
TO LEFT SIDE
ROW·SELECT·
CIRCUITS

~ ENH. ANCEMENT-t L,
MODE DEVICE
FROM
PROGRAMMING
LOGIC

~. ZER.O'THRESHOLO
-n,'OEVICE

3.Blased decoder; With a D.S-volt bias applied to deselected word lines during a read operation, depletion-mode pass transistors can be used in
the decoder:They increase the selected word line'svollage, speeding access and extending thEI allowed pcwer-supply range.

Iy equal to the electric field found in previous parts;
The thin oxide between .the substrate and floating gate
i1hlstrates the engineering .that went into each pf the
process steps. Early in the development, that 325-A-thick
oxide showed defect densities of around. 100/cm'. (The
oxide integrity is judged with a sensitive measurement of
the. dc current flowing through a large-area 'capacitor
biased to 15 v;) Based on the total active area, A, of the
channels of the i56~K chip's array transistors, a simple
model for the yield, such ase"~D, predicts the loss due to
that defect density; D, at 54%, 'an unacceptably high
'
figure, for a single' prOCess step. .
With careful adjustment of process parameters, the
thin-oxide defect density was reduced below 5/cm', raising the yield of that 'step to an .estimated 96%. SimilarIy" each new.step could be fine-tuned independently of
any other procedures; simplifying 'the process' debugging.. Despite the many new procedures, the overall
structure and the sequence of steps do not depart radicillly from previous E-PROMS, a help in ,the retraining of
manufacturing' persomiel.
, ' , ..
In particular, 'the shared drain Contact" common
source diffusion, and self-aligned floating polysilicon'
gate of the E-PROM .cell have not changed conceptually
since the 2716 of five years ago. What .has changed
dramatically is the minimum feature size: the evolution'
from projection printing. 'and wet. etching to wafer-stepping lithography and anisotropic plasma etching on critical levels has shrunk the 27256's cell to the size of a
contact hole on the 0Id'.27l6.
.
Most elements of the E-PROM process arealfected by
that radicalshrink .. The field oxide that isolates adjacent
diffusions is thinned to 0.6 jJ.ni, a move that cuts the'
length of the bird's beak iIi half. (The bird's beak, or
transition region, between the oxide and the active de-"
vice is wasted area.),:As a.result, the minimum spaping
on the mask between adjacent field oxide regions is only

2 jJ.m. The thinner oxide is possible thanks to the lower
programming voltage, which reduces the chance of parasitic transistor action beneath the oxide.
The dose of boron' implanted in the transistor channels to set their- threshold voltage is increasoo, compensating for the effects oCthe shorter, narrower channels.
In tum, the gate oxides are thinned to boost the transconductance' of the more highly doped channels. The
arsenic for thc Source and drain regions is implanted 0.5
jJ.m ,or shallower to' control the channel length and
forestall punchthrough. To prevent the metalization
from penetrating those shallow, junctions, an aluminumsilicoll alloy substitutes for the usual a1uminum~
Although process development goes. far to ensure a
reliable part with good' margins, new' circuits were alSo'
required for the E-PROM's jump to 256-K density~ For
one, .some statistical variation in cell characteristics' is
inevitable, and the more bits per chip, the· greater the
likelihood that one or more bits will fall outside the
,acceptable limits. Thus, circuits that compensate for
.these process-induced' variations in effect raise yield.
Sensing circuitry offers one example. .
The 27256 uses two entire columns of reference cells,
associating two cells with each of the 512 word lines
rather than one with each of the eight comparators in
the output section (Fig;' 2). The tolerance to variations
in .read currents quintuples that in the 2764; Undoubtedly, future· E-PROMs will. extend this concept again;
incorporating multiple reference columns.
Before the 2764, E-PROMs employed single-:ended'
sense amplifierS, wIiich are comparators that switch
:when the input current exceeds some threshold, cillied
the'. trip current, which is not a function of any cell
parameters. T.o make the trip current dependent on the
read current itself, the 2764 used a differential comparator, which compares the read current with a fixed fraction' of the current from a reference cell-a replica of
Electronlcl' February 24, 1983

4·10

the array cells. If a cell's read current is lower than
expected, then the reference cell's current will probably
be low as well, adjusting the trip current accordingly.
Such a circuit not only continues to operate under process variations, but also allows the design of a comparator optimized for speed.
Unfortunately, carrying that scheme even further on
the 27256 and increasing the number of reference cells .
naturally leads to a wider distribution of their currents,
and the conventional differential comparator could introduce an error because of that variation. To compensate for that error, a constant-current-ratio differential
comparator was introduced. In it, the lower impedance
reference load is obtained by connecting several transis- selected word line still receives a reduced voltage.
tors in parallel, each of which is an identical copy of the
The 27256 also illustrates the utility of two circuit
array load device (see Fig. 2 again). The parallel con- features trademarked as the intelligent Identifier and the
nection then gives the correct impedance without chang- intelligent Programming Algorithm. A persistent probing the transistor operating point, permitting correct lem for the user of scaled-down E·PROM technology is the
operation over a much wider range of read current.
changing programming requirements. Each new generation forces customers to convert to lower voltages and
Extending a scheme
altered algorithms. The identifier, an on-chip, unalterIn the usual comparator, the dimensions of the load able, 2-byte code, specifies the chip's manufacturer, prodevice on the reference cell or column are adjusted to gramming algorithm, voltage, and pulse width.
give a lower impedance than that of the load device on
the array column. The voltage drops across the different Saving progamming time
With ever denser E·PROM arrays, the programming
impedances are the differential input to the comparator.
However, the different load-device dimensions change the algorithm proves its worth in saving programming time.
devices' threshold voltages, putting the reference load at This adaptive, closed-loop algorithm varies the width and
a different operating point. That difference means that the number of program pulses to reach an adequate
the ratio of the array current to the reference current margin in the minimum time, typically 4 milliseconds per
byte for the 27256.
changes with variations in the reference current.
The old programming algorithm, developed for the
Another innovation, in the row-decoder circuits, helps
speed access time and extend the power-supply variations 2716, used a fixed 50-ms pulse width. That width is
the chip will tolerate. The scheme devised for the 27256 determined by the worst-case programming time, that is,
uses a negative-threshold pass transistor; however, it also the longest time any bit in the array will need for comincorporates a bias-voltage generator to hold the deselect- plete programl!ling. As with other device characteristics,
ed word lines at about 0.5 v, rather than 0 v, during a process variations lead to a distribution of programming
read operation (Fig. 3). The bias current for the genera- times; the fixed-width pulse must be long enough to
tor is supplied by pull-up transistors connected to the program the slowest bit in the array. At the 256-K level,
programming voltage supply. The 0.5-v shift suffices to chances are good that at leas! one bit would need a very
reduce the leakage current without turning on deselected long programming pulse.
The closed-loop programming algorithm requires a
cells during a read operation.
However, during programming, when the high voltage method of determining the programmed cell "margin,"
applied to selected columns can couple to the /loating or retention characteristics. Margin· has generally been
gates, the 0.5-v bias would be enough to partially turn on represented as the maximum, supply voltage at which
deselected cells. Thus, a shunt transistor is included in both programmed and erased cells can be read. A prothe bias generator to pull the deselected word lines all grammed cell is one in which the threshold voltage has
been forced to a higher voltage. Increasing the supply
the 'way to ground during programming.
In a .conventional decoder, if a positive-threshold de- voltage boosts the voltage applied to a cell's gate; eventuvice is used, the word-line voltage rises very slowly above ally, the higher threshold is reached, turning on a cell
the level of one threshold below the supply voltage, slow- that is intended to remain off.
Thus, the strategy in the programming algorithm is to
ing access to the cells ... lt also ups the minimum powersupply voltage by about' t v. (The minimum supply volt- verify that a cell is programmed at an elevated supply
age is the cell's threshold voltage, plus that voltage voltage of 6 v. The procedure begins by applying a I-ms
required to generaie a detectable' current difference be- pulse to the first byte. At the end of the pulse, the chip
tween programmed and erased cells, typically about 3 v.) tries to read the programmed cells. If they are proUsing a negative-threshold device overcomes both grammed, an additional 3-ms pulse is applied, boosting
those effects, but introduces its own problems if not the margin about 1. 5 v. If the cell is not programmed, 1accompanied by a bias-voltage generator. With a deple- ms pulses continue to be applied until programming is
tion-mode pass transistor, the deselected devices still pass verified. When it is, a pulse three times as long as the
a significant leakage current. That current pulls down sum of the I-ms pulses already applied adds the required
the decoder output below the supply voltage so that the margin. To program a 27256 takes about 3 minutes. D
Electronics/ February 24, 1983

OUTPUT BUFFERS
V·GATING

AO-All
ADDRESS
INPUTS

X
DECODER

32,768·BIT
CELL MATRIX

Figure 2. Pin Configuration

Figure 1. Block Diagram

Intel Corporation Assumes No Responsibilty for the Use of Any Circuitry Other Than Circuitry Embodied ,in an Intel Product. No Other Circuit Patent Licenses are Implied.
©INTEL CORPORATION, INC. 1982

4-17

OCTOBER 1983
AFN.Q15458

2732A

ABSOLUTE MAXIMUM RATINGS*

"NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Temperature Under Bias ..... ,....... -10·Cto +80·C
Storage Temperature ............. - 65·C to + 125·C
All Input or Output Voltages with
Respectto Ground ......•.......... +6V to -0.3V
Voltage on Pin 22 with Respect
to Ground ...................... + 13.5V to -0.3V
Vpp Supply Voltage with Respect to Ground
During Programming ...... .' ....... +22V to -0.3V

D.C. AND A.C. OPERATING CONDITIONS DURING READ
,

2732A/A-2/ ~3/A~4-

Operating Temperature Range

I Vee Power Supply 1,2

READ OPERATION
D.C. CHARACTERISTICS
Symbol.

Output Leakage Current

VOUT = 5.5V

Vec Current (Standby)

A.C. CHARACTERISTICS
2732A-2.
2732A-20

Min. Max. Min. Max. Min. Max. Min. Max. Units

Test
Conditions f

tACC

Address to Output Delay

OE High to Output Not Driven

Output Hold trom Addresses,
CE or OE Whichever Oequrred
First

fA.C. TEST CONDITIONS
Output Load .............. 1 TTL gate and CL = 100 pF
Input Rise and Fall Times .......... , .... '..... " ",;; 20 ns
Input Pulse Levels .................... : .. 0.45V to 2.4V

Timing Measurement Reference Level:
Inputs: ... , .... , ....... , .... ,: ......... 0.8 and 2.0V
Outputs ..... ; ........................ 0:8 and 2.0V

NOTES: 1. Vec must be applied simultaneously or .before Vpp and removed simultaneously or after Vpp•
2. Vpp may be connected directly to Vcc except during programming. The supply currentwould then be the sum of Icc and IpP1 '
3. Typical values are for tA = 25·C and nominal supply voltages.
4. This parameter is only sampled and is not 100% tested. Output Float is defined as, the point where data is no longer
driven '- see timing diagram
'

4-18

AFN.()I545B

2732A

CAPACITANCE (2) (TA = 25°C, f = 1 MHz)
Symbol

Parameter

CIN1

Input Capacitance
Except OE/Vpp

CIN2

OE/Vpp Input
CapaCitance

A.C. TESTING INPUT/OUTPUT WAVEFORM

A.C. TESTING LOAD CIRCUIT

A.C. TESTING: INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC "1" ANOO 45V FOR
A LOGIC "0." TIMING MEASUREMENTS ARE MADE AT 2.0V FDA A LOGIC "'"
AND O.8V FOR A LOGIC "0."

~----+-----~OUT

c, = 100pF

100pF

Ct. INCLUDes JIG CAPACITANCE

A.C. WAVEFORMS

V,H------'
ADDRESS
VALID

ADDRESSES

V,L----__J
V,H -------:---1,...."'"

~----tcE------_t

V,H ---------1,...-----"'"
OENpp

1----------tACC·,---------.j

OUTPUT _ _ _ _ _ _~H~I~G~H~Z_ _ _ _ _ _~f_~rt~

ERASURE CHARACTERISTICS

Standby Mode

The erasure characteristics of the 2732A are such that
erasure begins to occur upon exposure to light with
wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain types of
fluorescent lamps have wavelengths In the 3000-4000A
range. Data show that constant exposure to room level
fluorescent lighting could erase the typical 2732A in ap·
proximately 3 years, while it would take approximately 1
week to cause erasure when exposed to direct sunlight. If
the 2732A is to be exposed to these types of lighting condi·
tions for extended periods of time, opaque labels should
be placed over the 2732A window to prevent unintentional
erasure.

The 2732A has a standby mode which reduces the max·
imum active current from 125 mA to 35 mA. The 2732A is
placed in the standby mode by applying a TIL-high signal
to the CE input. When in standby mode, the outputs are in
a high Impedance state, independent of the OE input.

Output OR-Tieing
Because EPROMs are usually used in larger memory arrays, Intel has provided a 2 line control function that accommodates this use of multiple memory connection.
The two line control function allows for:
a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will
not occur.

The recommended erasure procedure for the 2732A is
exposure to shortwave ultraviolet light which has a
wavelength of 2537 Angstroms (A). The integrated dose
(i.e., UV intensity X exposure time) for erasure should be
a minimum of 15 W-sec/cm2. The erasur,e time with this
dosage is approximately 15 to 20,. minutes using an
ultraviolet lamp with 12000"W/cm 2 power 'rating. The
2732A should be placed within 1 inch of the lamp tubes
during erasure.

To use these two control lines most effiCiently, CE (pin 18)
should be decoded and used as the primary deviceselecting function, while OE (pin 20) should be made a common
connection to all devices in the array and connected to the
READ line from the system control bus. This assures that
all deselecte'd memory devices are in their low power
standby mode and that the output pins are active only
when data is desired from a particular memory device:

DEVICE OPERATION

PROGRAMMING

The six modes of operatiOn of the 2732A are listed in Table
1. A single 5V power supply is required in the read mode.
All inputs are TIL levels except for OE/V pp during programming and 12V on Ag for.!!!.e inteligent IdentifierTM mode. In
the program mode the OE/V pp input is pulsed from a TIL
level to 21V.

CAUTION: ExCBlHling 22V on Pin 20 (OENpp) will
permBnent/ydBmBge the 2732A.

Initially, and after each erasure, all bits of the 2732A are
in the "1" state. Data is introduced by selectively programming "O's" into the desired bit·locations. Although
only "O's" will be programmed, both "1's" and "O's" can
be present in the data word. The only way to change a
"0" to a"1" is by ultraviolet light erasure.

Table 1. Mode Selection

Inteligent Identifier

V,L

Cod,e

DOUT

The 2732A is in the programming mode when the OE/Vpp
input is at 21 V. It is required that a 0.1 /LF capaCitor be
placed across OElV pp and ground to suppress spurious
voltage transients which may damage the device. The data
to be programmed is applied 8 bits in parallel to the data
output pins. The levels required 'for the address and data
inputs are TTL.

Notes: 1. X can be V,H or V,L
2. VH = 12.0 ± 0.5V

When the address and data are stable, a 50 msec, active
low, TTL program pulse is applied to th~ CE input. A program pulse must be applied at each address location to be
programmed. You can program any location at any time
-either individually, sequentially, or at random. The program pulse has a maximum width of 55 msec. The 2732A
must not be programmed with a DC signal applied to the
CE input.
'

Read Mode
The 2732A has two control functions, both of which must
be logically active in order to obtain data at the outputs.
Chip Enable (CE) is the power control and should be used
for device selection. Output Enable (OE) is the output
control and should be used to gate data from the output
pins, independent of device selection. Assuming that addresses are stable, address access time (tACe) is equal to
the delay from CE to output (tcEl. Data is available at the
outputs after the falling edge of OE, assuming that CE has
been low and addresses have been stable for at least
tACC-tOE'

Programming of multiple 2732As in' parallel with the
same data can be easily accomplished due to the simplicity of the programming requirements. Like inputs of the
paralleled 2732As may be connected together when they
are programmed with the same data. A" low level TIL pulse
applied to the CE input programs the paralleled 2732As.
4-20

AFN-QI545B

2732A

Program Inhibit

Intel began manufacturing 2732As during 1982 that contained the inteligent Identifier feature. Earlier generation devices do not contain identifier information, and if
erased, will respond with a "one" (V OH) on each data line
when operated in this mode. Programmed, preidentifier
mode 2732As will respond with the current data contained in locations a and 1 when subjected to the inteligent
Identifier operation.

Programming of multiple 2732As in parallel with different data is also easily accomplished. Except for CE, all
like inputs (including OE) of the parallel 2732As may be
; common. A TIL level program pulse applied to a 2732A's
CE input with OElVpp at 21V will program that 2732A. A
high level CE input inhibits the other 2732As from being
programmed.

System Consideration
Verify
The power switching characteristics of HMOS-E EPROMs
require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the
system designer-the standby current level, the active current level, and the transient current peaks that are produced by the falling and rising edges of Chip Enable. The
magnitude of these transient current peaks is dependent
on the output capacitive loading of the device. The
associated transie.nt voltage peaks can be suppressed by
complying with Intel's Two-Line Control, as detailed in In·
tel's 'Application Note, AP-72, and by properly selected
decoupling capacitors. It .is recommended that a 0.11'F
ceramic capacitor be used on every device between Vee
and GND. This should be a high frequency capacitor of low
inherent inductance and should be placed as close to the
device as possible. In addition, a 4.71'F bulk electrolytic
capacitor should be used between Vee and GND for every
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage
droop caused by the inductive effects of PC board-traces.

A verify (Read) should be performed on the programmed
bits to determine that they were correctly programmed.
The verify is accomplished with OElVpp and CE at V1L• Data
should be verified tov after the falling edge of CE.

inteligent Identifier™ Mode
The inteligent Identifier Mode allows the reading out of a
binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25 DC
± 5 DC ambient temperature range:
To activate this mode, the programming equipment must
force 11.5V to 12.5V on address line A9 (pin 22) of the
2732A. Two identi!ier bytes may then be sequenced from
the device outputs by toggling address line AO (pin 8) from
V1L to V1H • All other address lines must be held at V1L during
inteligent Identifier Mode.
Byte a (AO = VII) represents the manufacturer code and
byte 1 (AO = V1H ) the device identifier code. For the Intel
2732A, these two identifier bytes are given in Table 2. All
identifiers for manufacturer and device codes will possess
odd parity, with the MSB (07) defined as the parity bit.

Table 2. 2732A inleligenl Identilier™ Byles

PROGRAMMING[4]
D.C. PROGRAMMING CHARACTERISTICS':,TA = 2S ± SoC, Vcc = SV ± S%, Vpp = 21V ± O.SV

Input Current (All Inputs)

VOL

Output Low Voltage During Verify

VOH

Output High Voltage During Verify

Icc

Vcc Supply Current

VIL

Input Low Level (All Inputs)

VIH

Input High Level (All Inputs Except OElV pp)

Ipp

Vpp Supp'.y Current

VIO

A9 inteligent Identifier Voltage

A.C. PROGRAMMING CHARACTERISTICS: TA = 2S ± 5°C, Vcc = SV ± 5%, Vpp= 21V ± 0.5V
Limits
Symbol

OE High to Output Not Driven

tov

Data Valid from

tpw

CE Pulse Width During Programming

Rise Time During Programming

tA.C. TEST CONDITIONS
Input Rise and Fall Times (10% to 90%) ......... $20 ns
Input Pulse Levels ....................... O.4SV t02.4V
Input Timing Reference Level .......... 0.8V and 2.0V
Output Timing Reference Level' ..... '.... 0.8V and 2.0V
NOTES:
1. Typical values are for TA = 25°C and nominal supply voltages.
2. This parameter is only sampled and Is not 100% tested. Output float is defined as the pOint where data is no longer driven see timing diagram
.
3. OE may be delayed up to tACC-tOE after the falling edge of CE without impacting tACC,
4. When programming the 2732A, a O,lI'F capacitor is required across OE/vpp and ground to suppress spurious voltage
transients which may damage the device.

4,22

AFN.(l15458

2732A

PROGRAMMING WAVEFORMS
~----------------PROGRAM----------------~'-----

V'H _ _ _ _ _ _ _ _-,I

NOTES:
1. ALL TIMES SHOWN IN [I ARE MINIMUM AND IN .SEC UNLESS OTHERWISE SPECIFIED.
2. THE INPUT TIMING REFERENCE LEVEL IS O.BV FOR A VIL AND 2V FOR A VIH'

4·23

AFN.ol545B

intJ

P2732A
32K (4K x 8) PRODUCTION EPROM

• 200 ns (P2732A-2) Maximum Access
Time ... HMOS*-E Technology

.• Industry Standard Pinout ... JEDEC
Approved

• Compatible with High-Speed 8 MH~ iAPX
186 •.. Zero WAIT State

• Low Active Current ... 100 mA Max.
• inteligent Identifier'M Mode

• Two Line Control
• Compatible with 12 MHz 8051 Family

• Fast 20 ms Programming Time
• TTL Compatible

The Intel P2732A is a 5V-only, Electrically Programmable Read-Only Memory in a plastic package. One
time programmable, it has been designed for high volume production environments where a programmable memory is required for flexibility. The standard P2732A access time is 250 ns with speed selection
(P2732A-2) available at 200 ns. The access time is compatible with high performance microprocessors
such as the 8 MHz iAPX 186. In these systems, the P2732A allows the microprocessor to operate without
the addition of WAIT states.
The P2732A is ideal for volume production environments where inventory and lead time risks occur for program;
codes. Inventoried in the unprogrammed state, the P2732A is programmed quickly and efficiently when the need
to change code arises. Costs incurred for new ROM masks or obsoleted ROM inventories are avoided. The tight
package dimensional controls, inherent non-erasability, and high reliability of the P2732A make it the ideal
component for these production applications.
Using Intel's HMOS'-E technology, low power consumption combined with high speed data access are achieved.
The maximum P2732A active current is 100 mA, while standby is only 35mA. The standby mode is selected by
applying a TIL-high signal to the CE input.

AO_Al1!
ADDRESS
INPUTS

CE
0,
0.

32,768-BIT
CELL MATRIX

0.
03

Figure 1. Block Diagram

Figure 2. Pin Configuration

'HMOS is a patented process of Intel Corporation.
Intel Corporation Assumes No Responsibility for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit
OCTOBER 1983
Patent Licenses are Implied.
© INTEL CORPORATION, 1983.
4-24
ORDER NUMBER: 230724·002

P2732A

ABSOLUTE MAXIMUM RATINGS·

'NOTICE: Stresses above those listed under
':Absolute Maximum Ratings" may cause permanent, .
damage to the device. This is a stress rating only and
functional operation of the device at these or any other
conditions above those indicated in the operational
sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect device reliability.

Temperature Under Bias ........ -10°C to +80°C
Storage Temperature .......... -65°C to +125°C
All Input or Output Voltages with
Respect to Ground ............. +6V to -0.3V
Voltage on Pin 22 with Respect
. to Ground .................. +13.5V to -0.3V
Vpp Supply Voltage with Respect to Ground
During Programming .......... +22V to -0.3V

D.C. AND A.C. OPERATING CONDITIONS DURING READ
P2732A1A-2/ A-3/ A-4

I Operating Temperature Range
I Vcc Power Supply1,2

0°C-70°C
5V ± 5°/~

READ OPERATION
D.C. CHARACTERISTICS
Symbol

Output Leakage Current

Vcc Current (Standby)

A.C. CHARACTERISTICS
P2732A-2
Symbol

Min. Max. Min. Max. Min. Max. Min. Max. Units

Test
Conditionst

tACC

Address to Output Delay

OE High to Output Float

Outpu!.!::!.old from Addresses,
CE or OE Whichever Occurred
First

tA.C. TEST CONDITIONS
Output Load .......·1 TTL gate and CL = 100 pF
Input Rise and Fall Times ........ '....... ~20 ns
Input Pulse Levels ................ 0.45V to 2.4V

Timing Measurement Reference,Level:
Inputs . . . . . . . . . . . . . . . . . . . . . . . . .. 0.8 and 2.0V
Outputs ........................ 0.8 and 2.0V

NOTES:
1. Typical values are for TA = 25"C and nominal supply Voltages.
2. This parameter is only sampled and is hot 100% tested. Output float is defined as the point where data is no longer driven see timing diagram on page 4-18
..
3. '5E may be delayed up to IACC-IOE after the falling edge of CE with2,ul impacting IACC'
4. When programming the 2732A, a 0.11'F capacitor Is required across OElVpp and ground to suppress spurious voltage
transients which may damage the device.
.
4·25

i~®

P2732A

CAPACITANCe:[2]

(TA = 25°C, F = 1 MHz)

Symbol

Parameter'

CINl

Input Capacitance
Except OE/vpp

OE/vpp Input
Capacitance
Output Capacitance

A.C. TESTING INPUT/OUTPUT WAVEFORM

Conditions

A.C. TESTING LOAD CIRCUIT
1.3V
1N914

3.3Kn
DEVICE
UNDER
TEST

0.8

·'"'OUT
C," 100pF

A.C. TESTING: INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC "1" AND OASV FOR
A lOGIC 0.' TIMING MEASUREMENTS ARE MADE AT 2.0V FOR A LOGIC 1"
AND 08V FOR A LOGIC "0

Cl =100pF
Cl INCLUDES JIG CAPACITANCE

A.C. WAVEFORMS
v," _ _ _ _"""
ADDRESSES

v,"
OUTPUT _ _ _ _..;H~IG~H~Z_ _ _ _+t~i+<

HIGHZ

NOTES:

1. Typical values are for TA = 25°C and nominal supply voltages.
,
2. This parameter is only sampled and is not 100% tested. Output float is defined as the point where data is no longer driven-,--see
timing diagram on this page.
.
_
3. OE may be delayed up to tACC-tOE after the falling edge of CE without impacting tACC'
4. When programming the P2732A, a 0.1 (J.F capacitor is required across OENpp and ground to suppress spurious voltage
transients which may damage the device,
.

4·26

P2732A

APPLICATIONS INFORMATION'
Intel's P2732A is'the result of a mUlti-year effort to,
make EPROMs more cost effective for production
applicatio,ns. The benefits of a plastic package, enaqle
the P2732A to be used for high volume production
"with lower profile boards, and easier prodLiction assembly (no cover over UV transparent windows).
The reliability of plastic EPROMs i's equivalent to traditional CERDlp,packaging. The plastic is rugged and
durable making 'it' bptimal for alito insertion and auto
handling equipment.' Design 'and' testing ensures
d~vice programmabilitY, data integrity, and imperl11eabi,li~ to r,noisture.
"
Intel's, Plastic EPROMs are designed, for total compatillility with thfilir CERDIP packaged predecessors.
This' encompasses quality, reliability, and' programming. All Intel Plastic EPROMs~ave passed Intel's
strict process and product reliability 'qualifications.

DEVICE OPERATION
The six modes of operation of the P2732A are listed in
Table 1.A single 5V power'supply is required in the
~d mode. All inputs are TTL levels except for
OENpp during programming and 12V on A9 for the
!!:!!eligenl identifier'· mode. In 'the"program mode the
OENpp inpuUs pulsed from a !lL level to 21 V.

Table 1. Mode Selection'

Program Inhibit
Inteligent ldentifi,er

' VIH ..
Vil

NOTES: '
1. X can be VIH or VIL
2. VH = 12V ± O.5V

Read,Mode
The P2732A has two control functions, both of which
must be logically active in order to obtain data at the
'outputs. Chip Enable (CE) is the power control and
should be used for device selection. ,Output Enable
(OE) is the output control and should be used to gather
data from the output pins, independent of device selection. Assuming that addresses are stable, address
access time (tACel is equal to the delay from CE to
output (tCE)' Data is available at the outputs after the

falling edge of DE, assuming that'CE has been low
and addresses have been stable :for afieast:.tACC'
..tOE·

Standby Mode
The P2732A has a standby mode which reduces the
maximum active current from 100 rnA to 35 mAo The
P2732A is placed in the'standby mode by applying a
TTL-high signal to the CE input. When in standby
mode, the outputs are in a high impedance state,
independent of the OE input.

TWO LINE OUTPUT CONTROL
Because 'EPROMs are usually used in larger memory
arrays, Intel has provided two control lines which accommodate this multiple memory connection. The two
c,ontrollines allow for:
,
a) The lowest possible memory' pOINer diSSipation,
and
b) complete assurance that output bus contention wiil
not occur.
To use these two control lines most efficiently, CE (pin
18) should be decoded and ~d as the primary
,device selecting function, while OE (pin 20) should be
made a common connection to all devices in the array
and connected to the READ line from the system
control bus. This assures that all deselected memory
devices are in their low power standby mode and that
the output pins are active ,only when data is desired
from a particular memory device.

System Consideration
The power switching characteristics of HMOS-E
EPROMs require careful decoupling of the devices.'
The supply current, Icc, has three segments that are
of interest to the system designer-the standby current level, the active current level, and the transient
current peaks that are produced by the falling and
rising edges of Chip Enable. The magnitude of these
transient current peaks is dependent on the output
capacitive loading of the device. The associated transient voltage p,eaks can be suppressed by complying
with Intel's two line control and by use of properly
selected decoupling capacitors. It is recommended
that a 0.1 J.LF ceramic capacitor be used on every
device between Vcc and GND. This should be a high
frequency capaCitor of low inherent inductance and
should be placed as close to the device as possible. In
addition, a 4.7J.LF bulk electrolytic capacitor should be
used between Vcc and GND for every eight devices.
The bulk capacitor should be located near where the
, power supply is connected to the array. The purpose
of the bulk capacitor is to overcome the voltage droop
caused by the inductive effects of PC board traces.

P2732A

Application Note AP-72, which is available from Intel's
Literature Department, describes microprocessor
system implementation of the two-line control function
on Intel's EPROMs.
.

applied 8 bits in parallel to the data output pins. The.
levels required for the address and data inputs are
TTL.
.
.
.
When the address and data are stable, a 20ms active
low, TTL program pulse is applied to the.CE input. A'
program pulse.must be applied at each address location to be programmed. You can program any location
at any time-either individually, sequentially, .or at
random. The program pulse has a maximum width of
55ms. The P2732A must not beprograrrimed with a
DC signal applied to the CE input.

PROGRAMMING
CAUTION: Exceeding 22V on Pin 20 (OE/vpp) will
permanently damage the P2732A.
Initially all bits of the P2732A are in the "1 "'state. Data
is introduced by selectively programming "O's" into the
bit locations. Although only "O's"will be programrned,
~oth "1's" and "O's" can be present inthe data word.

Programming of multiple P2732As in paralleiwith the
same data can be easily accomplished due to the
Simplicity of the programming requirements. Like in-.
puts of the paralieledP2732Asmay' be connect!3d
together when they are programmed with the same
data .. A low level TTL pulse applied to theCE input
programs t~~ paralleled P2732A.
.

The P2732Ais in the programming mode when the
OENpp input is at 21 V. It is required that a 0.1JLF
capacitor be placed across OENpp and ground to
suppress spurious voltage transients which may
damage the device. The .data to.be programmed is

PROGRAMMING WAVEFORMS
1 - - - - - ' - - - .P R O G R A M - - - - - - - t - - -

NOTES:
1. ALL TIMES SHOWN IN [J ARE MINIMUM AND IN .SEC UNLESS OTHERWISE SPECIFIED ..
2.. THE INPUT TIMING REFERENCE LEVEL IS O.BV FOR A VIL AND 2V FOR AVIH.

PROGRAMMI~G[1 ]
D.C. PROGRAMMING CHARACTERISTICS: TA = 25 ± 5°C, Vee = 5V ± 5%, Vpp = 21V ± O.5V
Limits
Symbol

Parameter

III

Input Curre.nt (All Inputs)

VOL,

Output Low Voltage During Verify

VOH

Output High Voltage During Verify

Min.

Icc

Vcc Supply Current
Input Low Level (All Inputs)

V 1H

Input High Level (All Inputs Except OElVpp)

. A9 inteligent Identifier· Voltage

A.C. PROGRAMMING CHARACTERISTICS:

TA = 25 ± 5°C, Vce = 5V ± 5%, Vpp =21V ± O.5V
Limits

OE High to Output Not Driven

C'E Pulse Width During Programming

Pulse Rise Time During Programming

Test Condltlonst

".s

CE=V 1L, "Ol:=V 1L

A.C. TEST CONDITIONS
Input Rise and Fall Time (10% to 90%) ... "" 20 ns
Input Pulse Levels ................ 0.45V to 2.4V
Input Timing Referenc;e Level ...... O.8V and 2.0V
Output Timing Reference Level ..... 0.8V and 2.0V
NOTE:
1. When programming the P2732A, a 0.1 fLF capacitor is required across OElVpp and ground to suppress spurious voltage
transients which may damage the device.

4·29

P2732A

Program Inhibit

manufacturer and type. This mode is intended for use
by programming equipment for the purpose of automatically matching the device to be programmed with
its corresponding programming algorithm. This mode
is functional in the 25°C ±5°C ambient temperature
range.

Programming of multiple P2732As in parallel with different data is also easily accomplished. Exceptfor CE,
all like inputs (including OE) of the parallel P2732As
may be common. A TTL low level pulse applied to a
P2732A's CE input with OE/Vpp at 21V will program
that P2732A. Ahigh level CE input inhibits the other
P2732As from being programmed.

To activate this mode, the programming equipment
must force 11.5V to 12.5V on address line A9 (pin 22)
of the P2732A. Two identifier bytes may then be sequenced from the device outputs by toggling address
line AO (pin 8) from VIL to VIH. All other address lines
must be held at VIL during inteligent Identifier Mode.

Verify
A verify (Read) should be performed on the programmed bits to determine that they were correctly
programmed. The verify is accomplished with OElVpp
and CE at VIL. Data should be verified tDV after the
falling edge of CE.

Byte 0 (AO = VILl represents the manufacturer code
and byte 1(AO = VI H) the device identifier code. For
the Intel P2732A, these two identifier bytes are given
in Table 2. All identifiers for manufaCturer and device
codel> will possess odd parity, with the MSB (07)
defined as the parity bit.

inteligent Identifier ™ Mode
The inteligent Identifier Mode allows the reading out of
a binary code from an EPROM that will identify its

Table 2: P2732A inteligent Identifier'· Bytes

2764
64K (8K x 8) UV ERASABLE PROM
200 ns
Maximum Access
• Time
•.• HMOS*-E Technology
Compatible with High·Speed 8mHz
• iAPX
186... Zero WAIT State
• Two Line Control
• Pin Compatible to 27128 EPROM

• inteligent Programming™ Algorithm
Industry Standard Pinout, .. JEDEC
• Approved

(2764~2)

• Low Active Current. ..100mAMax.
• TTL Compatible

The Intel 2764 is a 5V only, 65,536-bit ultraviolet erasable and electrically programmable read-only memory (EPROM). The
standard 2764 access time is 250 ns with speed selection available at 200 ns. The access time is compatible with highperformance microprocessors such as Intel's 8 mHz iAPX 186. In these systems, the 2764 allows the microprocessor'to
operate without the addition of WAIT states. The 2764 is also compatible with the 12 MHz 8051 family.
An important'27!l4 feature is the separate output control, Output Enable (OE) from the Chip Enable control (CE). The OE
control eliminates bus contention in microprocessor systems. Intel's Application Note AP-72 describes the
microprocessor system implementation of the OE and CE controls on Intel's EPROMs. Ap·72 is available from Intel's
Literature Department.
The 2764 has a standby mode which reduces power consumption without increasing access time. The maximum active
current is 100 mA, while the maximum standby current is only 40 mAo The standby mode is selected by applying a TTL'
high signal to the CE input.
±10% Vee tolerance is available as an alternative to the standard ±5% Vee tolerance for the 2764. This can allow the system
deSigner more leeway with regard to his power supply requirements and other system parameters.
The 2764 is fabricated with HMOS*-E technology, Intel's high-speed N-channel MaS Silicon Gate technology.

inteligen! Identilier

Figure 2. Pin Configurations

Vpp
(1)

Program

Vpp

BLOCKS ADJACENT TO THE 2764 PINS

A,
A,
A,
All
All
OENpp DE
A10
A10

MODE SELECTION
6E

. NOTE: INTEL "UNIVERSAL SlTE"-COMPATIBLE EPROM PIN CONFIGURATIONS ARE SHOWN IN THE

Figure 1. Block Diagram

1'j

. . .. .
..., .. .. ..
A"
A,

PIN NAMES
A,-A
CE
OE

0-0
PGM
N,C.

ADDRESSES
CHIP ENABLE
OUTPUT ENABLE
OUTPUTS
PROGRAM
NO CONNECT

1. X can be VIH or VIL
2. VH
12.0V ± O.5V

*HMOS is a patented process of Intel Corporation.
Intel Corporation- Assumes No Responsibilty.for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied.
OCTOBER 1983
©INTEL CORPORATION, 1983
4-31
ORDER NUMBER: 21057()'OO3

intJ

2764

'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of .this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias .............. ~1 O°C to +80°C
Storage Temperature ................ -ElSoC to +12SoC
All Input or Output Voltages with
Respect to Ground ................ + 7.0V to -O.6V
Voltage on Pin 28 with
Respect to Ground ................. +13.SV to -O.6V
Vpp Supply Voltage with Respect to
Ground DuriQg Programming ........ +22V to -O.6V

D.C. AND A.C. OPERATING CONDITIONS DURING READ
2764'-2

.
Operating Temperature
Range
Vee Power Supply 1.2

Vpp'=Vee Vpp = Vee Vpp = Vee Vpp = Vee Vpp= Vee Vpp ='Vce Vpp ='Vce

READ OPERATION
D C CHARACTERISTICS
: Symbol

Output Leakage C'urrent

, Output High Voltage

CE = VIH
CE = OE = VIL

2764·25 &
2764 Limits
Min

Max

2764-30 &
2764·3 Limits
Min

Max

2764·45 &
2764·4 Lim Its
Min

Max , ,Unit

Test
Conditions

t Ace

Address to Output Delay

OE High to Output Float
...

Output Hold fr.om Addresses.
CE Or OE Wh,ichever Occu'rred

First
"

NOTES: 1.
2.
3.
4.

Vee must be .applled sImultaneously or before Vpp and removed sImultaneously or after Vpp •
Vpp may be connected directly to Vee except during programming. The supply current would then be the sum cif Icc and Ip" .
Typical values are for tA = 25'C and nominal supply voltages.
This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer
.,
;
,
driven - see timing diagram

AFN·01647A

inter

2764

CAPACITANCE
Symbol
C,N'
COUT

A.C. TESTING INPUT/OUTPUT WAVEFORM

A.C. TESTING LOAD CIRCUIT

ALL TIMES SHOWN IN [1 ARE MINIMUM AND IN pSEC UNLESS OTHERWISE SPECIFIED.
THE INPUT TIMING REFERENCE LEVEL IS .BV FOR VIL AND 2V FOR A V1H •
•
10E AND IDFP ARE CHARACTERISTICS OF THE DEVICE BUT MUST BE ACCOMMODATED BY THE PROGRAMMER.
WHEN PROGRAMMING THE 2764, A O.1pF CAPACITOR IS REQUIRED ACROSS Vpp AND GROUND TO SUPRESS
SPURIOUS VOLTAGE TRANSIENTS WHICH CAN DAMAGE THE DEVICE. '

ERASURE CHARACTERISTICS
The erasure characteristics of the 2764 are such that erasure
begins to occurlJponexposure to light with wavelengths
shorter than a'pproximately 4000 Angstroms (A). It should be
noted that sunlight and certain types of fluorescent lamps
have w'avelengths in the 3000-4000 A range. Data show that
constant exposure to room level fluorescent lighting could
erase the typical 2764 in approximately 3 years, while itwould
take approximately 1 week to cause erasure when exposed to
direct sunlight. If the 2764 is to be exposed to these types of
lighting conditions for extended periods of time,. opaque
labels should be placed over the 2764 window to prevent
unintentional erasure.
The recommended erasure procedure for the 2764 is exposure to shortwave ultraviolet light which has a wavelength of

4.-35

2537 Angstroms (A). The integrated dose (Le., UV intensity x
exposure time) for erasure should be a minimum' of ·15 Wsec/cm 2• The erasure time with this dosage isapproximat~ly
15 to 20 minutes using an ultraviolet lamp with a 12000
p.W/cm2 power rating. The 2764 should I;le placed within 1 inch
of the lamp tubes during erasure. The maximum integrated
dose a 2764 can be exposed to without damage is 7258
Wseclcm2 (1 week @ 12000 p.W/cm~, Exposure of the.2764 to
high intensity UV light for long periods may cause permanent
damage.

DEVICE. OPERATION
The eightrnodes of operation of the 2764 arii listed in Table
1. A single 5V power supply is. required in the read mode.
All inputs are TTL levels except for Vpp and 12V on A9 for
inteligent Identifier mode.

AFN·01647A

2764

System Considerations '

Table 1. MODE SELECTION

~
MODE

CE OE PGM Ag Vpp Vee
(20) (22) (27) (24) (1) (28)

inteligent Identifier

inteligent
Programming

NOTES:
1. XcanbeVIH orVIL
2: VH ~12,OV =O,SV

READ MODE
The 2764 has two control functions, both of which must be
logically active in order to obtain data at the outputs, Chip
Enable (CE) is the power control and should be used for
device selection. Output Enable (OE) is the output control
and should be used to gate data from the output pins, independent of device selection. Assuming that addresses are
stable, the address access time (tACe) is equal to the delay
from CE to output (tcEl. Data is available at the outputs
after a delay of tOE from the falling edge of DE, assuming
that CE has been low and addresses have been stable for at
least tAcc - tm:.

STANDBY MODE
The 2764 has standby mode which reduces the maximum
active current from 100 mA to .40 mAo The 2764 .is placed in
the standby mode by applying a TTL-high signal to the CE
input. When in standby mode, the outputs are In a high 1m·
pedance state, independent of the DE input.

Output OR·Tieing
. Because EPROMs are usually used in larger memory arrays.
Intel, tiasprovid.ed2 control. lines which accommodate this
multiple memory connection. The two control lines allow for:
a) the lowest possible m~mory power disSipation, arid
b) complete assurance that output bus contention will not
occur.
To use these two control lines most efficiently. CE (pin 20)
should be decoded and used as the primary device selecting
function, while OE (pin 22) sholild be made a commoricon·
nection to all devices in the array and connected to the READ
line from the system control bus. This assures that all de:
selected memory devices are in their low power standby
mode and that the output pins are active only when data is
desired from a particular memory device.

The power switching characteristics of HMOS-E EPROMs
require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer - the standby current level, the active current
level, and the transient current peaks that are produced by
the falling and rising edges of Chip Enable. The magnitude of
these transient current peaks is dependent on the output
capacitance loading of the device. The associated transient
voltage peaks can be suppressed by complying with Intel's
Two-Line Control, as detailed in Intel's Application Note, AP72, and by properly selected decoupling capacitors. It is recommended that a 0.1/LFceramic capacitor be used on
every device between VCC and GND. This should be a high
frequency capacitor of low inherent inductance and should
be placed as close to the device as possible. In addition, a 4.7
/LF bulk electrolytic capacitor should be used between Vcc
and GND for every eight devices. The bulk capacitor should
be located 'near where the power supply is connected to the
array. The purpose of the bulk capacitor is to overcome the.
voltage droop caused by the inductive effect of PC board·
traces.

PROGRAMMING MODES
, Caution: Exeeding 22 Von pin 1 (VppJ will
permanently damage the 2764.
. "1" state. Data is introduced by selectively programming "Os"
into the desired bit locations. Although only "Os" will be
programmed, both "1 s.. and "Os" can be present in the data
word. The only way to change a '''0'' to a "1" is by ultraviolet
light erasure.
The 2764 is in the programming mode when VPP input is at
21V and CE and PGM are both at TTL low. The data to be
programmed is applied 8 bits in parallel to the data output
pins. The levels required for the address. and data inputs
are TTL. .
'
.

Standard Programming
For programming, CE should be kept TTL·low at all times
while Vpp is kept at 21V. When the address and data are
stable, a 50 msec, active·low,TTL program pulse is applied to
the PGM input: A program pulse must be appUed at each ad·
dress location to be programmed. You can program any loca·
tionat any time-either individually, sequentially; or at r!u;·
dam. The Program pulse has a maximum, width of
55 msec.
.,
.
Programming of multiple 2764s iri parallel with the same data
can be easily accomplished due to the simplicity of the proc
gramming requirements, Like inputs of the paralleled 2764s
maybe connected together when they are programmed with
the same data. A low-level TTL pulse applied to the'PGM
input programs the paralleled 2764s.

Program Inhibit
Programming of multiple 2764s in parallel with different data
is also easily accomplished by using the Program inhibit

4·36

AFN-01647A

2764

Figure 3. 2764 intellgent Programming™ Flowchart

mode. A high-level CE or PGM input inhibits .the other 2764s
from being programmed. Except .for CE, all like inputs (in·
cluding OE) of the parallel 2764s may be common. A TTL lowlevel pulse applied to a 2764 CE and PGM Input with Vpp at
21Y will program that 2764.

Verify
A verify should be performed on the programmed bits to
determine that they were correctly programmed. The verify is
performed with CE and OE at VIL, PGM at VIH and Vpp at 21V.

inteligent Programming™ Algorithm
The 2764 inteligent Programming Algorithm is the preferred programming method since it allows Intel 2764s to be
programmed in a significantly faster time than the standard 50 msec per-byte programming routine. Typical programming times for 2764s are on the order of a, minute and
a half, which is a five-fold reduction in programming time
from the standard method. This fast algorithm results. in
improved reliability characteristics compared to the standard 50 msec algorithm. Aflowchart of the inteligent Programming Algorithm is shownin Figure 3. This is compatible with the 27128 inteligent Programming Algorithm.

4-37

AFN-01647A

2764

verify occurs: Up to 15 one-millisecond pulses per byte are
provided for, before the overprogram pulse Is applied.

This fast algorithm results in high reliability characteristics
through the "closed loop" technique of margin checking. To
ensure reliable program margin the inteligent Programming
Algorithm utilizes two different pulse types: initial and over·
program. The duration of the initial PGM pulse(s) is one
millisecond, which will then be followed by a longer over·
program pulse of length 4X msec. X is an iteratioh counter
and is equal to the nurnber of the initial one millisecond
pulses applied to a particular 2764 location, before a correct

The

entire sequence o( program pulses and byte verifications is
perfonnedat Vee = 6.0VandVpp = 21.0V. When the inteligent
, Programming cycle has been cqmpleted, all bytes should be
compared to the original data with Vee = Vpp = 5.0V.

inteligent Programming™ Algorithm
D.C. PROGRAMMING CHARACTERISTICS: T A = 25 ±5°C, Vee = 6.0V ±O.251J, Vpp = 21 V ±O.5V (see Note 1)

Symbol

Parameter

III

Input Current (All Inputs)

VIL

Input Low Level (All Inputs)

VIH

Input High Level

VOL

Output Low Voltage During Verify

VOH

Output High Voltage During Verify

Ice2

Vee Supply Current (Program & Verify)

IpP2

Vpp Supply Current (Program)

VIO

A9 for inteligent Identifier Voltage

A.C. PROGRAMMING CHARACTERISTICS: TA = 25 ±5°C, Vee = 6.0V ±O.251J, Vpp = 21V ±O.5V (see Note1)
Limits
Symbol

OE High to Output Float Delay

PGM Initial Program' Pulse Width

0.95

topw

PGM Overprogram Pulse Width

• A:C. CONDITIONS OF TEST
Input Rise and Fall Times (10% to 90%) .... :: .... 20 ns
Input Pulse Levels ........ , .... ,., .. , ... 0.45V to 2.4V
InputTiming Reierence Level ........... O.BVand 2.0V
Output Timing Reference Level .......... O.BV and 2.0V

NOTES:
1. Vee must be applied simultaneously or before Vpp and
removed simultaneously or after Vpp.
2. The length of the overprogram pulse will vary from 3.8 msec'
to 63 msec as a function of the iteration counter value X.
3. Initial Program P\flse w.idth tolerance is 1 msec,,: 5%.
4. This parameter Is only sampled and is not 100% tested. Out:
put Float is'definedas the,polnt where 'data is
'
no longer driven - see timing diagrarh'
.

inteligent Programming™ WAVEFORMS
PROGRAM

1. ALL TIMES SHOWN IN [[ ARE MINIMUM AND IN ~SEC UNLESS OTHERWISE SPECIFIED.
2. THE INPUT TIMING REFERENCE LEVEL IS .BV FOR V 1L AND 2V FOR A V 1H .
3. tOE AND tOFP ARE CHARACTERISTICS OF THE DEVICE BUT MUST BE i\.CCOMMODATED BY THE PROGRAMMER.
4. WHEN PROGRAMMING THE R2764 A O.l.F CAPACITOR IS REQUIRED ACROSS Vpp AND GROUND TO SUPRESS
SPURIOUS VOLTAGE TRANSIENTS WHICH CAN DAMAGE THE DEVICE.

4-39

AFN·Ol647A

2764

infeligent IdentifierTM Mode

The inteligent Identifier Mode allows the reading out of
binary code from an EPROM that will identify Its manufacturer and type. This mode Is Intended for use by programm·
Ing equipment, for the purl!ose of automaticalJy matching
the device to be programmed with Its corresponding pro·
gramming algorithm, This mode is functional In the 25'C
± 5'C ambient temperature range.

Byte 0 (AO = VIL) represents the manufacturer code and byte
1 (AO = VIH) the 'device identifier code, For the Intel 2764,
these two identifier bytes are given in Table 2, All identif(ers
fo~ manufacturer and device codes will ,'possess odd parity,
with the MSB (Or) defined all the parity bit.
During 1982, Intel will begin manufacturing 2764s that ';"'ill
contain the lnteligent Identifier feature: Earlier generation
devices will not contain identifier information; and if erased,
will respond with a "one" (VOH) on each data line when
operated in this mode. Programmed, pre-identifier mode
2764s will rl!spond with the current data contained in
locations 0 to 1 when subjected to the Intellgent Identifier'
operation.

To activate this mode, the programming equipment must
force 11.5V to 12.5V on address line "A9 (pin 24) of the 2764.
Two identifier bytes may then be sequenced from the device
outputs by toggling address lirie AO (pin 10) from VIL to VIH.
All other address lines must beheld at VIL during
inteligent Identifier Mode.,

Table 2. 2764 Intallgent IdentlflerTM Bytes

2764A
ADVANCED 64K (SKxS) UV ERASABLE PROM
• inteligent ProgrammingTh'l Algorithm
-Fastest EPROM Programming

• .200 nsec Standard Access Time

-HMOS II*-E Technology

• inteligent IdentifierTh'l Mode
-Automated Programming Operations
• Compatible with 2764, 27128, 27256

• Low Power
-60 mA Maximum Active
...;..20 mA Maximum Standby
• Two Line Control

• ±10% Vee Tolerance Available

The Intel 2764A is a 5V only, 65,536-bit ultraviolet erasable and electrically programmable read-only memory
(EPROM). The 2764A is an advanced version of the 2764 and is fabricated with Intel's HMOSII-E technology
which significantly reduces die size and greatly improves the device's performance, power consumption,
reliability and producibility.
.
The typical 2764A is the 2746A-2 with an access time of 200 ns. This is an improvement over the 2764 stan·
dard time of 250 ns. This is compatible with high-perfo'rmance microprocessors, such as Intel's 8 MHz
iAPX 186 allowing full speed operation without the addition of WAIT states. The 2764A is also directly
compatible with the 12 MHz 8051 family.
Several advanced features· have been designed into the 2764A that allow fast and reliable programming-the
inteligent Programming Algorithm and the inteligent Identifier Mode. Programming equipment that takes advantage of
these innovations will electronically identify the 2764A and then rapidly program it using an efficient programming
method.
The 2764A also offers reduced power consumption compared to the 2764. The maximum active current on
faster speed parts is 60 mA while the maximum standby current is only 20 mA. The standby mode lowers
power consumption without increasing access time.
Two-line control and JEDEC-approved, 28 pin packaging are standard features of all Intel higher density EPROMs.
This ensures easy microprocessor interfacing' and minimum design efforts when upgrading, adding or choosing
between non-volatile memory alternatives.

Figure 1. Block Diagram

intellgen!
Programmmg

Figure 2, Pin Configurations

(11-13,15-

A,
A,
A,

Vee

NOTE: INTEL "UNIVERSAL SITE"·COMPATIBLE EPROM PIN,CONFIGURATIONS
ARE SHOWN IN THE BLOCKS ADJACENT TO THE 2764A PINS

1. X can be VIH or VIL
2. VH = 12.0V ± O.5V

PIN NAMES
A.·A
CE
OE

0·0
PGM
N.C.

ADDRESSES
CHIP ENABLE
OUTPUT ENABLE
OUTPUTS
PROGRAM
NO CONNECT

"HMOS is a patented process of Intel. Corporation
Intel Corporation Assumes No Responsibilty for the Use of Any Circuitry Other Then Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses afe Implied.

4.41

OCTOBER 1983
ORDER NUMBER: 230702·002

2764A

ABSOLUTE MAXIMUM RATINGS·,,'

-NOTICE: Stresses above, those listed under ''Absolute
Maximum Ratings"may cause permanent darriage the
device. This is a stress rating only and functional operation of the device at these orany other conditions above
those indicated in the operational sections of this
specification is not implied; :Exposure to absolute maximum rating conditiongfor extendf3d periods may affect
device reliability.

Temperature Under Bias .............. -10°C to +80°C
Storage Temperature ............. ; .. -6S 0 Cto +125°C
All Input or Output Voltages with
'RespecttoGround .......•......... +6.2SVto-O.6V
Voltage' on' Pin 24 with
"
.
Respect to Ground ........" ........ +13.SV to,-O.6V
Vpp Supply Voltage with Respect to
" .
Ground During Programming ........ + 14V to -O.6V ,

D.C. AND A.C. OPERATING CONDITIONS DURING READ
2764A·1, 2764A·2, 2764A
2764A·3, 2764A·4

2764A-20; 2764A·25
2764A-30, 2764A·45

OO_70°C'

OO_70°C

Operating Temperature Range

VCC Power SUPPI? ,2
Vpp Voltage2.

D.C. CHARACTERISTICS
Symbol
III
IlO
IpPl" "

Input L.oad Current
: Output Leakage Current

CE = VIH
CE = DE = Vil

A.C. CHARACTERISTICS
Symbol

2764A-20"
2764A-30"
2764A-45 "
2764A-25 "
2764A-l Limits 2764A-2Umlts 2764A Limits 2764A-3 Llinlts 2764A-4 Limits
Min
Max
Min
Max Min
Max
Min
Max
Min
Max

DE High to Output
Float

tOH

Output Hol~om--,
Addresses CE or DE
Whichever Occurred
First

a
0

Test
Conditions

300

Address to Output
Delay

NOTES: 1. Vee must be applied,SimUltaneouSly or before Vpp and removed simultaneously or alte,rllpp .'
2. .vpp may be connecled"directly to Vee except during programming. The supply current ,,!ould then ,be the sum'of Icc and IpP1 '
, 3. Typical values an~ for tA ',;,: 25°C and nominal supply voltages:
'
4. This parameter is only sampled and Is not 100% tested. Output Float Is defined as the point where data is no longer
driven - see timing diagram on the following page.
5. Max Icc rating differs wi\h access time. Rallng of 60 rnA active and 20 rnA standby are for,2764As at 200 msec and·1BO
msec access lime only .. ' . ,
, ,'.,
"
'.
., ,
'

A.C. TESTING INPUT/OUTPUT WAVEFORM

=>(2.0

0 8 > TEST POINTS

0.45

A.C. TESTING LOAD CIRCUIT
1.3V

A.C. TESTING: INPUTS ARE DRIVEN AT 2.4V FOR A lOGIC , .. AND 0 45V FOR
A LOGIC D." TIMING MEASUREMENTS ARE MADE AT 20V FOR A LOGIC "

AND a.BV FOA A LOGIC "0 ..

,-,

Cl=100pF

100pF

C L INCLUDES JIG CAPACITANCE

A.C. WAVEFORMS

V'H------""""'\
ADDRESS
·VALID

OUTPUT-----------~~~------------~t_~~_(

NOTES:

1. Typical values are for TA = 25°C and nominal supply voltages.
2. This parameter is only sampled and is not 100'% tested.
3. DE may be delayed up to tAce - toE after the falling edge of CE without impact on t Ace 4. tOF is specified from DE or CE, whichever occurs first.

4·43

HIGHZ

2764A

To use these two control lines most efficiently, ,CE
(pin 20) should be decoded and used as the primary
device selecting fLinction, while'OE (pin 22) should
be made a common connection to all devices in the
array and connected to the READ line from the system control bus. This assures that all deselected
memory devices are in their low power standby mode
and that the output pins are active only when data is
desired from a particular memory device.

DEVICE OPERATION
The seven modes of operation of the 2764A are listed
in Table 1. A single 5V power supply is required in the
read mode. All inputs are TTL levels except for Vpp
and 12V on A9 for inteligent identifier mode.
Tlible 1. MODE SELECTION

(20) (22) (27) (24)

Read

VIL

Output Disable,
Standby

inteligent Identifier

Outputs,
vpp vee
(11.,13,15·
(1) (28),

System Considerations

inteligent

Programming
NOTES:
1. XcanbeVIH orV1L
2, VH ~12,OV ':O,SV

READ MODE
The 2764A has two control functions; both of which
must be logically active in order to obtain data at the
outputs. Chip Enable (CE) is the power contrciland
should be used for device selection. Output Enable
(OE) is the output control and should be used to gate
, data from the output pins, independent of device
. selection. Assuming that addresses are stable, the
, address access time (tACC) is equal to the delay from
CE to output (tCE)' Data is available at the outputs
after a delay ~tOE from the falling edge of OE,
assuming that CE has been low and addresses have
been, stable for at least tAee~toE'

The power switching characteristic~ of HMOSII-E
EPROMs reqiJire careful decoupling of the devices.
The sklpply current, Icc, has three segments that are
of interest to the,system design~r-thestandby current level, the active current level, and the transient
current peaks that are produced by the falling and
rising edges of Chip Enable. The magnitude of these
transient current peaks is dependent on the output
capacitive loading of the device. The associated transienl'voltage peaks can be suppressed by complying
with Intel's Two-Line Control, as detailed in Intel's
Application Note AP-72, Order Number 8566, and by
properly selected decoupling capacitors. It is recommended that a 0.11LF ceramic capacitor be used on
every device between Vce and GND. This should be a
,high frequency capacitor of low inherent inductance and
should be placed as plose to thed~vice as possible. In
addition, a 4.7 ILF bulk electrolytic capacitor should be
used between Vccand GND for every eight devices.
The bulk capacitor should be"located near whe're the
power supply is connected to the array. The purpose of
the bulk capaCitor is to overcome the voltage droop
caused by the inductive effect of PC board-traces.

•STANDBY MODE
The 2764A has standby mode' which reduces the
~ maximum current from 75 mA to 35 mAo The, 2764A is
, placed in the standby mode by applying a TTL-high
, signal to the CE input. When in standby mode, the
outputs are in Ii high impedance state, independent
of the OE input.

Output OR-1;'ieing
Because EPROMs are usually' used in larger memory
arrays, Intel has provided 2 control lines which accommodate this multiple memory connecti,on. The
two control lines allow for:
''
a) the lowest possible memory power dissipation,
and
b) complete assurance that output bus contention
will not occur.
"4·44

PROGRAMMING MODES
Caution: Exceeding 14V on pin 1 (V pp) will permanentiy
damage the 2764A.
'

Initially, and after each erasure, all bits of the 2764A
are in the "1" state. Data is introduced by selectively
programming "Os" into the desired bit locations. Although only "Os" will be programmed, both "1s" and
"Os" can be present in the data word. The only way to
change a "0" to a "1" is by ultravio,let light erasure.
The 2764A is in the.£!'ogram~ing ~od~ when V~p
input is at 12.5Vand CE and PGM are both at TTL low.
The data to be programmed'is,applied 8 bits in parallel to the 'data Qutputpiris.'The leve'ls required for the
address and data inputs are TTL.

inter

2764A

inteligent Programming™ Algorithm

Except for CE, all like inputs (including OE) of the
parallel 2764As may be common. A TTL low-level
pulse applied to the CE input with Vpp at 12.5V will
program the selected 2764A.

The 2764A inteligent Programming Algorithm
rapidly programs Intel 2764A EPF,lOMs using an efficient and reliable method particularly suited to the
production programming environment. Typical programming time for individual devices is on the order
of one and a half minutes. Programming reliability is.
also ensured as the incremental program margin of
each byte is continually monitored to determine
when it has been successfully programmed. A flowchart of the 2764A inteligent .Programming Algorithm is shown in Figure 3.

Verify
A verify should be performed on the programmed ",
bits to determine that they have been correctly programmed. The verify is performed with OE at VIL, CE
at VIL, PGM at VIH and Vpp at 12.5\1.

inteligent Identifier™ Mode

The inteligent Programming Algorithm utilizes two
. different pulse types: initial and overprogram. The
duration of the initial CE pulse(s) is one millisecond,
which will then be followed by a longer overprogram
. pulse of length 3X msec. X is an iteration counter and
is equal to the number of the initial one millisecond
pulses applied to a particular 2764A locat,ion, before
a correct verify occurs. Up to 25 one-millisecond
pulses per byte are provided for before the overprogram pulse is applied.

The inteligent Identifier Mode allows the reading out
of a binary code from an EPROM that will identify its
manufacturer and type. This mode is intended for
use by programming equipment for the purpose
of automatically matching ~he device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ±5°C
ambient temperature range that is required when
programming the 2764A.
To activate this mode, the programming equipment
mustforce 11.5V to 12.5V on address line A9 (pin 24)
of the 2764A. Two identifier bytes may then be sequenced from the device outputs by toggling address line AO (pin 10) from VIL to VIH. All other
address !ines 'must be held at VIL during inteligent
Identifier Mode.

The entire sequence of program pulses. and byte
verifications is performed at Vee = 6.0Vand Vpp =
12.5'1. When the inteligent Programming cycle has
been completed, all bytes should be compared to the
.
; original data with Vce = Vpp =5.0\1.

Program Inhibit

Byte 0 (AO = VIL) represents the manufacturer code
and byte 1 (AO =,VIH) the device identifier code. For
the Intel 2764A, these two identifier bytes are given in
Table 2. All identifiers for manufacturer and device
codes will possess odd parity, with the MSB (07)
defined as the parity bit.

Programming of multiple 2764As in parallel with different data is easily accomplished by using the Program Inhibit mode. A high-level CE or PGM input
inhibits the other 2764As from being programmed.

Table 2. 2764A inteligent Identifler™ Bytes

Device Code
NOTES:
'1. Ag = 12.0V ±0.5V
2. A1-Ai;, A10-A13, CE, OE
3. A14 = VIH orVIL

Figure 3. 2764A In!eUgent Programmlng™ Flowchart

.4·46

2764A

wavelength of 2537 Angstroms (A). The integrated
dose (Le., UV intensity x exposure time) for erasure
should be a minimum of 15 Wsec/cm 2 . The erasure
time with this dosage is approximately 15 to 20
minutes using an ultraviolet lamp with a 12000
/LW/cm2 power rating. The 2764A should be placed
within 1 inch of the, lamp tubes during erasure. The
maximum integrated dose a 2764A can be exposed
to without damage is 7258 Wsec/cm 2 (1 week @
12000/LW/cm2). Exposure of the 2764A to high intensity UV light for long periods may cause permanent damage.

ERASURE CHARACTERISTICS
The erasure characteristics of the 2764A are such
that erasure begins to occur upon exposure to light
with wavelengths shorter than approximately 4000
Angstroms (A). It should be noted that sunlight and
certain types of fluorescent lamps have wavelengths
in the 3000-4000A ra!1ge. Data show that constant
exposure to room level fluorescent lighting could
erase that typical 2764A in approximately 3 years,
while it would take approximately 1 week to cause
erasure when exposed to direct sunlight. If the
2764A is to be exposed to these types of lighting
conditions for extended periods of time, opaque
labels should be placed over the 2764A window to
prevent unintentional erasure.

RELEVANT INTEL LITERATURE
AR-265 Versatile Algorithm, Equipment Cut
Programming Time
RR·35B EPROM Reliability Data Summary

The recommended. erasure procedure for the 2764A
is exposure to shortwave ultraviolet light which has a

inteligent Programming™ Algorithm
D.C. PROGRAMMING CHARACTERISTICS:
TA = 25 ± 5°C, Vcc = 6.0V ± 0.25V, Vpp = 12.5V ± 0.5V
Test Conditions

Input Current (All Inputs)

V1L

Input Low Level (All Inputs)

V1H

Input Hi~h Level

VOL

Output Low Voltage During Verify

VOH

Output High Voltage During Verify

Icc2

Vcc Supply Current (Program & Verify)

rnA

IpP2

Vpp Supply Current (Program)

rnA

VID

A9 inteligent Identifier Voltage

12.5

2.4

11.5

NOTES:
1. Vee must be applied simultaneously or before Vpp and removed simulta'neously or after Vpp.

A.C. PROGRAMMING CHARACTERISTICS:
TA = 25 ± 5°C, Vee = 6.0V ± 0.25V, Vpp = 12.5V ± 0.5V
Limits
Symbol

Test Conditions'
Unit

OE High to Output Float Delay

PGM Initial Program Pulse Width

0.95

topw

PGM Overprogram Pulse Width

• A.C. CONDITIONS OF TEST

NOTES:

Input Rise and Fall Times (10% to 90%) ... 20 ns
Input Pulse Levels ................ 0.45V to 2.4V
Input Timing Reference Level ..... 0.8V and 2.0V
Output Timing Reference Level ... 0.8V and 2.0V

1. Vee must be applied simultaneously or before Vpp
and removed simultaneously or after Vpp .
'
2. The length of the overprogram pulse may vary from
2.85 msec to 78.75 msec as a function of the iteration
counter value X.
3. Initial Program Pulse width tolerance is1 msec ±5%.
4. This parameter is only sampled and is not 100%
tested. Output Float is defined as the point where
data is no longer driven-see timing diagram

4·48

2764A

inteligent Programming™ WAVEFORMS
PROGRAM

ALL TIMES SHOWN IN [ 1 ARE MINIMUM AND IN I£SEC UNLESS OTHERWISE SPECIFIED.
THE INPUT TIMING REFERENCE LEVEL IS .BV FORVIL AND 2V FOR A VIH.
tOE AND 'OFP ARE CHARACTERISTICS OF THE DEVICE BUT MUST BE ACCOMMODATED BY THE PROGRAMMER.
WHEN· PROGRAMMING THE 2764A, A O.II£F CAPACITOR IS REQUIRED ACROSS Vpp AND GROUND TO SUPRESS
SPURious VOLTAGE TRANSIENTS WHICH CAN DAMAGE THE DEVICE.

4·49

P2764

x 8) PRODUCTION EPROM

64K (8K

• Guaranteed 2 Minutes Maximum'
Programming Time

• Industry-Standard Pinout ... JEDEC
Approved

• Compatible with High-Speed 8 MHz'
iAPX 186 ... Zero WAIT State

• Low Active Current ••. 100 mA Max.

• Two-Line Control

• inteligent Programming™ Algorithmfor Reliable Programming

• Pin Compatible to 27128 EPROM

• TTL Compatible

The Intel P2764 is a 5V-only, Electrically Programmable Read-Only MemorY in a plastic package. One
time programmable, it has been designed for high volume production environments where a program,
mabie memory is required for flexibility. The standard P2764 access time is 250ns making it compati,
ble with high performance microprocessors, such as the Intel 8MHz iAPX 186. In these systems, the
P2764 allows the microprocessor to operate wi,thout the addition of WAIT states. The P2764 is also
.
compatible with the 12 MHz 8051 family.
The P2764 is ideal for volume production environments where inventory and lead time risks occur for pro:
gral1) codes. Inventoried in the unprogrammed state, the P2764 is programmed quickly and efficiently using the inteligent programming Algorithm for new codes. Costs ,incurred for new ROM masks or obsoleted ROM inventories are ,avoided. The tight package dimensional controls, inherent non-erasability,
and legible marking of the P2764 make it the ideal component for these production applications.
Additional features of, the P2764 include high reliability and fast, reliable programming. The P2764
uses Intel's inteligent Programming™Algorithm which typically eni~bles the entire 8,192 bytes to program in under 2 minutes. This algorithm also ensures that the P2764will reliably retain the programmed data throughout its effective life.
Using Intel's HMOS--f; technology, low power consumption combined with high speed data access
are achieved. The typical P2764 active current is 70mA, while standby is only 25mA. The standby mode
is selected by applyinQ a TIL-high signal to the CE inpUt.

"'o;"mlnhlI:II'
'nl.I'~nllclllnl,I ...

,
V"

...

,. X.canbeVIHorVIL
2. VH

12.0V

:!:

O.SY

-HMOS Is a patented process of Intel Corporation

A.C. TESTING LOAD CIRCUIT

A.C, TESTING: INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC "1 ,. ANDO.45V FOR
A LOGIC "0," TIMING MEASUREMENTS ARE MADE AT 2.QV FOR A LOGIC "'"
AND a.BV FOR A LOGIC "0 ..

IC"

""OUT

100 pi

-=CL = 100pF
CL' INCLUDES JIG CAPACITANCE

A.C. WAVEFORMS

V'H------,
ADDRESS
VALID

OUTPUT _ _ _ _ _ _~H~I~GH~Z_ _ _ _ _ _~f_~~_<

NOTES:
1. Typical values are forTA = 25°C and nominal supply voltages:
2. This parameter is only sampled and is not 100% tested.
3. OE may be delayed up to tACC-tOE after the falling edge of CE without impact on tACC'
4. tPF is specified from OE or CEo whichever occurs first.

4-63

HIGHZ

27128

STANDARD PROGRAMMING
D.C. PROGRAMMING CHARACTERISTICS: TA = 25.±5°C, Vcc = 5V ± 5%, Vpp = 21V ± O.5V (see Note 1)

Input Current (All Inputs)

VOL

Output Low 'I0ltage During Verify

VOH

Output High Voltage During Verify

.2.4

VIL

Input Low Level (All Inputs)

Test Conditions
VIN = VIL orVIH

Vee Supply Current (Program I'nhibit)

ICC2

Vcc Supply Current (Program & Verify)

100

IpP2

Vpp Supply Current (Program)

Vpp Supply Current (Verify)

CE = VIL PGM = VIH

IpP4

Vpp Supply Current (Program Inhibit)

CE =VIH

VIO

Ag Inteligent Identifier Voltage

12.5

11.5

A.C. PROGRAMMING CHARACTERISTICS: TA = 25 ± 5°C, VCC = SV ± 5%, Vpp = 21V ± O.SV (see Note 1)
Limits
Symbol

Output Enable to Output Fioat Deiay

tvs

Vpp Setup Time

t pw

PGM Pulse Width During Programming

·A.C. CONDITIONS OF TEST
.Input Rise and Fall Times (10% to 90%) .......... 20 ns
Input Pulse Levels ................. ,..... 0.45V to 2.4V
Input Timing Reference Level ...... : .... O.SV and 2.0V
Output Timing Reference Level .:., ...... O.SV and 2.0V
NOTES:
.1, Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer
driven-see timing diagram

4·64

27128

STANDARD PROGRAMMING WAVEFORMS
t-------:--PROGRAM-------l+----

NOTES:
1.. ALL TIMES SHOWN IN [ ) ARE MINIMUM AND IN "SEC UNLESS OTHERWISE SPECIFIED.
2. THE INPUT TIMING REFERENCE LEVEL IS .8V,FOR A VIL AND 2V FOR AVIH'
3. tOE AND' tOFP ARE CHARACTERISTICS OF THE DEVICE BUT MUST BE ACCOMMODATED BY THE PROGRAMMER.
.
4. WHEN PROGRAMMING THE 87128 A O.I"F CAPACITOR IS REQUIRED ACROSS VPP AND GROUND TO SUPPRESS SPURIOUS VOLTAGE TRANSIENTS WHICH· CAN
DAMAGE THE DEVICE.

ERASURE CHARACTERISTICS
The erasure characteristics of the 27128 are such
that erasure begins to occur upon exposure to light
with wavelengths shorter than approximately 4000
Angstroms (A). It should be noted that sunlight and
certain types of fluorescent lamps have wavelengths
in the 3000-4000 A range. Data show that constant
exposure to room level fluorescent lighting could
erase the typical 27128 in approximately 3 years,
while it would take approximately1.week to cause
erasure when exposed to direct sunlight-If the 27128
is to be exposed to these types of lighting conditions
for extended periods of time, opaque labels should
be placed over. the 27128 win.dowto prevent unintentional erasure.
The recommended erasure procedure for the 27128
is exposure to shortwave ultraviolet light which has a
wavelength of 2537 Angstroms (A). The integrated
dose (Le., UVintensity x exposure time) for erasure
should be aminimum of 15 Wsec/cm 2 .The erasure
time with this dosage is' approximately 15 to 20
minutes using an ultraviolet lamp· with a 12000
p.W/cm 2 powerrating. The 27128 should be placed
within 1 inch ofthe lamp tubes during erasure. The
maximum integrated dose a 27128 can be exposed
to without damage is 7258 Wsec/cm 2 (1. week @

12000 p.W/cm'1. Exposure of the 27128 to high intensity UV light for long periods may cause permanent
damage.

DEVICE OPERATION
The eight modes of operation of the 27128 are
listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL levels
except for Vpp and 12V on A9 for inteligent Identifier'mode.
.
Table 1. Mode·Selection

Ag vpp vee outputs
(11-13,

in!eligen! Identifier

in!aligen!
Programming

NOTES:
1. XcanbeVIHorVIL
2. VH=12.0V ±O.5V

,READ MODE
Jhe 27128 has two control.functions, both of which
must be logically active in order to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output Enable
(OE) is the output control and should be used to gate
data from the output pins, independent of device
selection. Assuming that addresses are stable,
the address access time (tAccl is equal to the
delay from CE to output (tCE)' Data is available at
the outputs after a delay of tOE from the falling
edge of OE, assuming that CE has been low and
addresses have been stable for at least tACC- tOE,

STANDBY MODE

transient current peaks is dependent on the output
capacitive loading of the device. The associated
transier)t voltage peaks can be suppressed by complying with Intel's Two-Line Control, as detailed in
Intel's Application Note, AP-72, and by properly selected decoupling capacitors. It is recommended
that a 0.1 /LF ceramic capacitor be used on every
device between Vce and GND. This should be a high
frequency capacitor of low inherent inductance and
should be placed as close to the device as possible.
In addition, a 4.7 /LF bulk electrolytic capacitor
, should be used between Vec and GND for every
eight devices. The bulk capacitor should be locatep
near where the power supply is connected to the
array. The purpose of the bulk capacitor is to overcome the voltage droop caused. by the inductive ef.
fects of PC board traces.

The 27128 has standby mode which reduces the
maximum 'active current from 100 mA to 40 mAo
The 27128 is placed in the standby mode by apply·
ing a TTL·high signal to the CE input. When in
standby mode, the outputs are in a high im·
pedance state, independent of the OE input.

Output OR·Tieing
Because EPROMs are usually used in larger memory
arrays, Intel has provided 2 control lines which accommodate this multiple memory connection. The
two control lines allow for:

PROGRAMMING MODES
Caution: Exceeding 22Von pin 1 (V pp) will permanently damage the 27128.
Initially, and after each erasure, all bits of the 27128
are in the "1" state. Data is introduced by selectively
programming "Os" into the desired bit locations. Although only "Os:' will be programmed, both "15" and
"Os" can be present in the data word. The qrly way to
change a "0" to a ,,1" is by ultraviolet light erasure.
The 27128 is in the programming mode when Vpp
input is at 21V and CE and PGM are both !It TTL low.
The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the
address a.nd data inputs are TTL.

a) the lowest possible memory power dissipation,
and
b) complete assurance that output bus contention
will not occur.
'
To use these two control lines most efficiently, CE
(pin 20) should be decoded and used as the primary
device selecting function, while OE (pin 22) should
be made a common connection to all devices in the
array and connected to the READ line from the system control bus. This assures that all deselected
memory devices are in their low power standby mode
and that the output pinsare active only wh!!n data is
desired from a particular memory device.

Standard Programming

System Considerations

For progrf\mming, CE should be kept TTL-low at all
times While Vpp is kept at 21V. When the address and
data are stable, a 50 msec, active-low, TTL program
pulse is applied to the PGM input. A program pulse
must
applied at each address location to be pro~
grammed. You .can program any location at any time
-either individually, sequentially, or at random. The
program pulse has a maximum width,of 55 msec.

The power switching characteristics of HMOS-E
EPROMs require careful decoupling of ,the devices.
The supply current, Icc, has three segments that are
of interest to the system designer-the standby current level, the active current level, and the transient
current peaks that are produced by the falling and
rising edges of Chip Enable. The magnitude of these

Programmirg of multip!e 27128s in parallel with the
same data can be easily accomplished due, to the
simplicity.of the programming requirements. Like
inputs of the paralleled 27128s may be connected
together when they are. programmed with the same
data. A lOW-level TTL pulse applied to the PGM input
programs the paralleled 27128s.
.

4·66

27128

Figure 3. 27128 Inteligent Programming™ Flowchart
programmed. The verify is performed with CE and
OE at VIL, PGM at VIH and Vpp at 21V.

Program Inhibit
Programming of multiple 27128s in parallel with different data is easily accomplished by using the Program Inhibit mode. A high-level CE or PGM input
inhibits the other 27128s from being programmed.
Except for CE, all like inputs (including OE) of the
parallel 27128s may be common. A TIL low-level
pulse applied to the CE and PGM inputs with Vpp
at 21V will program the selected 27128.

Verify
A verify should be performed on the programmed
bits to determine that they have been correctly

inteligent Programming™Algorithm
The 27128 inteligent Programming Algorithm is the
preferred programming method since it allows Intel
27128s to be programmed in a significantly faster
time than the standard 50 msec per byte programming routine. Typical programming times for 27128s
, are on the order of two minutes, which is a six-fold
. reduction in programming time from the standard
method. This fast algorithm results in improved
reliability characteristics over the standard 50 msec
4-67

intel'

27128

algorithm. A flowchart of the 27128 inteligent Programming Algorithm is shown in Figure 3. This is
compatible with the 2764 inteligent Programming
.
Algorithm.
This fast algorithm assures reliable programming
through the "closed loop" .technique of margin
checking. To ensure reliable program margin the inteligent Programming Algorithm utilizes two different pulse types: initial and overprogram. The
duration of the initial PGM pulse(s) is one millisecond, which will then be followed by a longer over-

program pulse of length 4X msec.X is an iteration
,counter and is equal to the number of the initial one
millisecond pulses applied to a particular 27128
location, before a correct verify occurs. Up to 15
one-millisecond pulses per byte are provided for
before the overprogram pulse is applied.
. The entire sequence of program pulses and byte
verifications is performed at Vee = 6.0V and v.pp =
21.0V. When the inteligent Programming cycle has
been completed, all bytes should be compared to the
original data with Vee = Vpp = 5.DV.

inteligent Programming ™Algorithm
D.C. PROGRAMMING CHARACTERISTICS: TA

= 25 ± 5°C, Vee = 6.DV ± D.25V, Vpp = 21V ± D.5V
Limits

Symbol

Parameter

III

Input Current (All Inputs)

VIL

Input Low Level (All Inputs)

VIH

Input High Level

VOL

Output Low Voltage During Verify

VOH

Output High Voltage During Verify

Vee Supply Current (Program & Verify)

109

rnA

IpP2

Vpp Supply Current (Program)

rnA

VIO

Aginteligent Identifier Voltage

12.5

A.C. PROGRAMMING CHARACTERISTICS: TA

11.5

Test Conditions
(see Note 1)

= 25 ± 5°C, Vee = 6.DV ± D.25V, Vpp = 21V ± D.5V
Limits

OE High to Output Float Delay

tvps

Vpp Setup Time

Test Conditions'
(see Note 1)

PGM/WE Initial Program Pulse Width

0.95

p's

topw

PGM/WEOverprogram Pulse Width

• A.C. CONDITIONS OF TEST

NOTES:

Input Rise and Fall Times (10% to 90%) .......... 20 ns
Input Pulse Levels ............ ; ......... 0;45V t02.4V
Input Timing Reference Level ..... ; ..... 0.8V and 2.0V
Output Timing Reference Level .......... 0.8V and 2.0V

vee

must be applied simultaneously or before Vpp and
removed simultaneously or after Vpp,
2. The length of the overprogram pulse will vary from 3.8 msec
to 63 msec as a function of the iteration counter value X.
3. Initial Program Pulse width tolerance is 1 msec ± 5%,
4. This parameter is only sampled as is not 100% tested.
OutputFloat is defined as the point where data is no longer
driven-see timing diagram on the following page.
.

4-68

27128

in1eligenl Programming™ WAVEFORMS
VERIFY

1--[0.15,1_
lopw
[3.8 mal

I--

MAX.

NOTES:
1. ALL TIMES SHOWN IN [1 ARE MINIMUM AND IN ~SEC UNLESS OTHERWISE SPECIFIED,
2. THE INPUT TIMING REFERENCE LEVEL IS .BV FOR AVIL AND 2V FOR AVIH.
3. tOE AND tDFP ARE CHARACTERISTICS OF THE DEVICE BUT MUST BE ACCOMMODATED BY THE PROGRAMMER.
4: WHEN PROGRAMMING THE 27128, A O.1,uF CAPACITOR IS REQUIRED ACROSS Vpp ANO GROUND TO SUPRESS SPURIOUS VOLTAGE TRANSIENTS WHICH ~AN

DAMAGE THE DEVICE.

4-69

27128

intellge~t Identlfler™ Mode

Byte 0 (AO = Vld represents the manufacturer code
and byte 1 (AO =VIH) the device identifier code. For
the Intel 27128, these two identifier bytes are given in
Table 2. All identifiers for manufacturer and device
codes wiil possess odd parity, with the MSB (07)
defined as the parity bit.

, The inteligent Identifier Mode allows the reading out
of a binary code from an EPROM that will identify its
manufacturer and type. This mode is intended for
use by programming equipment for the purpose of
,automatically matching the device to be programmed with its corresponding programming algorithm.
This mode is functional in the 25°C ± 5°C ambient
temperature range.

Intel will begin manufacturing 271285 during 1982
that will contain the inteligeht Identifier feature. Earlier generation devices will not contain identif,ier information, and if erased, will respond with a "one"
(VoH) on each data line when oper?ted in this mode.
Programmed, pre-identifier mode 27128s will
respond with the current data contained in locations
o and 1 when subjected to the intellgent Identifier
operation.

To activate this mode, the programming equipment
, must force 11.5V to 12.5Von address line A9 (pin 24)
of the 27128. Two identifier bytes may then be sequenced from the device outputs by toggling address line AO (pin 10) from VIL to VIH. All other
address lines must be held at VIL during inteligent
Identifier Mode.

Table 2. 27128 Intellgent Identifier Bytes

27128A
ADVANCED 128K (16Kx8) UV ERASABLE PROM
• inteligent Programming™ Algorithm
-Fastest EPROM Programming
• inteligent Programming™ Mode
-Automated Programming Operations
• Compatible with 2764A, 27128, 27256
• ± 10% Vcc Tolerance Available

• 200 nsec Typical Access Time
-HMOS II*·E Technology
• Low Power
-100 rnA Maximum Active
-40 rnA Maximum Standby
• Two Line Control

The Intel 27128 is a 5V only, 131,072-bit ultraviolet erasable and electrically programmable read-only memory
(EPROM). The 27128A is an advanced version of the 27128 and is fabricated with Intel's HMOS II-E technology
which significantly reduces die size and greatly improves the device's performance, power consumption,
reliability and producibility.
The typical 27128Aaccess time is 200 ns which is an improvement over the 27128 standard time of 250 ns. This is
compatible with high-performance microprocessors, such as Intel's 8 MHz iAPX 186 allowing full speed operation without the addition of WAIT states. The 27128Ais ~Iso directly compatible with the 12 MHz 8051 family.
Several advanced features have been designed into the 27128A that allow fast and reliable programming-the inteligent Programming Algorithm and the inteligent Identifier Mode. Programming equipment that takes advantage of these innovations will electronically identify the 27128 and then rapidly program it using an efficient programming method.
The 27128 also offers reduced power consumption compared to the 27128. The maximum active current on faster
speed parts is 60 mA while the maximum standby current is only 20 mA. The standby mode lowers power consumption without increasing access time.
Two-line control and JEDEC-approved, 28 pin packaging are standard features of all Intel higher density
EPROMs. This ensures easy microprocessor interfacing and minimum design efforts when upgrading, adding or
choosing bet weeI'! non-volatile memory alternatives.

NOTES:
1. ALL TIMES SHOWN IN [1 ARE MINIMUM AND IN "SEC UNLESS OTHERWISE SPECIFIED.
2. THE INPUT TIMING REFERENCE LEVEL IS .BV FOR A VIL AND 2V FOR A VIH.
3. tOE AND tOFP ARE CHARACTERISTICS OF THE DEVICE BUT MUST BE ACCOMODATED BY THE PROGRAMMER.
4. WHEN PROGRAMMING THE 27256 A O.I"F CAPACITOR IS REQUIRED ACROSS Vpp AND GROUND TO SUPRESS SPURIOUS
VOLTAGE TRANSIENTS WHICH CAN DAMAGE THE DEVICE.

4·81

UV ERASABLE PROM FAMILY
EXPRESS
• 0-70°C Temperature Range
Standard

• 168±8 Hour Burn-in Available
• Industry Standard Pinout ... JEDEC
Approved

• Extended Temperature Range
-40°C - +85°C Available

• Inspected To 0.1% AQL

• Two Line Control

The Intel EXPRESS EPROM family is a series of ultraviolet erasable and electrically programmable read only
memories which have received additional processing to enhance product characteristics. EXPRESS processing is available for several densities of EPROM, allowing the choice of appropriate memory size to match system
applications. Intel's JEDEC approved 28 pin Universal Memory Socket provides the industry standard upgrade
path to higher density EPROMs.
EXPRESS EPROM products are available with 168±8 hour, 125°C dynamic burn-in using Intel's standard bias
configuration,. This process exceeds or meets most industry specifications of burn-in.
The standard EXPRESS EPROM operating temperature range is O°C to 70°C. Extended operating temperature
range (-40°C to 85°C) EXPRESS products .are available. EXPRESS products plus military grade EPROMs
(-55°C to 125°C) provide the most complete choice of standard and extended temperature range EPROMs
available.
Like all Intel EPROMs, the EXPRESS EPROM family is inspected to 0.1% electrical AQL. This may allow the user
to reduce or eliminate incoming inspection testing.

Intel Corporation Assumes No Reaponsibilty for the Use of Any Circuitry Other Than Circuitry Embodied in an Inlel Product. No Other Circuit Patent Licenses are Implied .

.f' INTEL CORPORATION 1982

4-82

OCTOBER '983

ORDER NUMBER: 210322·002

EXPRESS
EPROM Product Family
Operating
Temperature
eC)

Burn-in
125°C
(hr)

168:!:8
168:!:8

Organization

Maximum
Access
. (ns)

o to 70
o to 70
o to 70

OD2732A-2
OD2732A
OD2732A-3
OD2732A-4

4096x8
4096x8
4096x8
4096x8

200
250
300
450

5V :!: 5%
5V :!: 5%
5V :!: 5%
5V :!:: 5~~

168:!:8
168:!:8
168:!:8
168:!:8

OD2732A-20
OD2732A-25
OD2732A-30

4096x8
4096x8
4096x8

200
250
300

5V:!: 10%
5V :!: 10%
5V:!: 10%

o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to.70

168:!:8
168:!:8
168:!:8

LD2732A-25
LD2732A-45

TD2732A-25
TD2732A-45

SV
5V :!:
5V:!:
5V :!:

5%
5%
5%

o to 70
o to 70
o to 70
o to 70

168:!:8
168:!:8
168:!:8
168:!:8
168:!:8
168:!:8
168:!:8

OD2764-2
OD2764
OD2764-3
OD2764-4

8192x8
8192x8
8192x8
.8192x8

200
250
300
450

OD2764-25
OD2764-30
OD2764-45

8192x8
8192x8
8192x8

250
300
450

5V:!: 10%
'5V:!: 10%
5V :!: 10%

o to 70
o to 70
o to 70

inter
EXPRESS
EPROM Product Family
(Cont.)

0027128·25
0027128·45

16384x8
16384x8

250
450

5V ± 10%
5V ± 10%

o to 70
o to 70
o to 70

168±8
.168±8

L027128
L027128·4
L027128·45

16384x8
16384x8
16384x8

250
450
450

5V ± 5%
5V ± 5%
5V ± 10%

- 46 t085
- 40 to 85
- 40 to 85

168±8
168±8
168± 8

TD27128
T027128·4
T027128·45

16384x8
16384x8
16384x8

250
450
450

5V ± 5%
5V ± 5%
5V ± ·10%

- 40 to 85
- 40 to 85
- 40 to 85

- 40 to 85
- 40 to 85

- 40 to 85
- 40 to 85

None
None.

Type

Operating
Temperature

AN
BINARY SEQUENCE FROM

to AN

Figure 1. Burn-In Bias and Timing Diagrams·

READ OPERATION
D.C. AND A.C. CHARACTERISTICS
Electrical Parameters of EXPRESS EPROM products are identical to standard data sheet parameters except
fur:
.
.
Limits
Symbol

Parameter

TD2716
LD2716
Min.

TOE

Output Enable to
Output Delay (ns)

IoF

Output Enable to
Output Float (ns)

Icc·,

Vcc Standby Current (rnA)

Icc2

Vcc Active Current (rnA)

CE ~ VIH. OE ~ VIL
OE

~ CE.~

VIL

E2 PROMs & NVRAMs .
(In Circuit Programmable
Writable Memories)

APPLICATION
NOTE

AP-100

December 1982

Based on preseniation

~t 1981Intern~tional Reliability

PhysiCs Symposium, Orlando, Florida, April 7, 1981.

©Intel Corporation, 1982.

5-1

AP-100

INTRODUCTION
Electrically Erasable Programmable Read Only
Memories (E 2 PROMs) that can be electrically erased
and written one byte at a time are new components
being used in computer systems. The E 2 PROM is particularly attractive in applications requiring field update
of program store memory or non-volatile data capture.
I.t is only recently that E 2 PROMs which operate via
Fowler-Nordheim tunneling to a floating polysilicon
gate have become available. The E 2 PROM has the data
retention requirements of earlier generations of
PROMs, but also must maintain its field-programmable
characteristics over its device life.

10.3
10.4

10.8
10·7

10·9'----':':---~----,:---,:::0--7:11---'

In this paper we shall first review the basic operation of
the Intel 2816 E 2 PROM cell. Intrinsic failure mechanisms which limit the applications of E 2 PROMs will be
examined, and then defect mechanisms will be discussed. Finally lifetest data will be presented to predict
operating failure rate·s.

Device Operation
The Intel 2816 uses the FLOTOX structure, which has
been discussed in detail in previous literature!. Basically, it utilizes an o~ide of less than 200).. thick between the floating polysilicon gate and the N + region as
shown in Figure 1.

Figure 2. Fowler-Nordheim Tunneling I-V
Characteristic

During the erase operation, approximately 20V is
applied to the top gate of each cell in the 'byte while the
drain is kept at ground potential. The electrical field in
the thin oxide region is directed from the floating gate to
the N+ region such that electrons tunnel through the
oxide and are stored on the floating gate. This shifts the
cell threshold in the positive direction causing the cell to
shut off current flow and present a logical "'" at its
. output (as seen in Figure 3a).
On the other hand, when the cell is written to logic "0";
the top gate is pulled down to ground potential and a
high voltage is applied to the drain (with the source end
floating). Electrons are depleted from, the floating gate

(
SELECT
TRANSISTOR
STORAGE
TRANSISTOR

ERASE!
WRITE
LINE

Figure 1. FLOTOX Device Structure Cross Section

ELECTRONS CHARGE
ALL GATES ON)INE

. ""

+21V

Both erase and write are accomplished by tunneling the
electrons through thin oxide using the Fowler-'
Nordheim' mechanism 2 . The I-V characteristic of
Fowler-Nordheim tunneling is shown in Figtire 2,
where the current is approximately exponentially dependent on the electric field applied to the oxide. '

Figure 3a. .Schematic of Memory Cell Operation
During Erase
.

5·2

AFN·Ol883A

AP-100

as seen in Figure 3b, and the cell is left with a negative
threshold. Since the interpoly oxide is much thicker
than'the "tunnel oxide" and the electric field across the
interpoly oxide is much smaller, the erase and write
operations are predominantly controlled by the thin
oxide region.

J,,_ _ _ _ EC
- - - - - - - EF

EC _ _ _/I
EF - - - - - -

Ev
TOP GATE

e
e
e
e

e
e

FLOATING
GATE
THIN
OXIDE

EF • FERMI LEVEL
AV • VOLTAGE DIFFERENCE BETWEEN TOP GATE AND DRAIN
IN WORST CASE READ CONDITION

+21V

Figure 4. Band Diagram During Read of
Written Cell

ERASE!
WRITE
LINE

there is a one-to-one relationship between the VT and
the stress voltage. In other words, we can stress the
device by applying a higher voltage to the top gate such
that the change of the threshold voltage can be measured. The data then will be used to predict the same
characteristics at the much lower normal read voltage.
In Figure 5, the aforementioned simulation and experimental data are shown. The cell was biased at a voltage
4V higher than the normal read condition and the
threshold voltage of the cell was monitored over a
period of a week. A simulation was also generated to
compare with the observed threshold shift and to demonstrate the technique we use to predict whether the
data retention ofthe cell is accurate. As can be seen in
the Figure 4, even under the accelerated voltage test the
cell VT still will not cross above the sense level after
more than 10 years. Similar data has also been taken by
writing the cell to a more negative initial threshold. In
this case, the shift ofthe threshold can be observed at a
stress of normal read voltage. Clearly, a IV/IV relationship holds and an extrapolation can be made that
the correct data will be retained for more than 10 years
of continuous read.

Figure 3b. Schematic of Memory Cell Operation
During Write

Read Retention
The floating gate structure is known for ,its excellent
charge retention properties. The reliability of this
structure in the case of the EPROM device has been
reported before3 . The only remaining concern of the
data retentivity of the 2816 is possible charge gain or
loss through the tunnel oxide due to Fowler-Nordheim
tunneling. The maximum electric field is built up across
the tunnel oxide for a written cell, one that has a net
positive charge on the floating gate. In this state the
positive top gate voltage creates an electric field which
adds to the field created by the positive charge on the
floating gate, and there exists the probability that e1ec. trons may tunnel to the floating gate and shift the cell
threshold. The band diagram ofthiscondition is shown
in Figure 4. However, the amount of current which may
pass through the thin oxide during read or deselect is
kept low by biasing the top gate of the memory cell at an
internally generated voltage less than Vee. The effect
on the threshold shift of the cell can only be observed
after long-term stress. Under this condition, the accel.
erated voltage test can be very useful.

,VT

r------------------,
-;;::~---------f---

If we assume Fowler-Nordheim tunneling is the
predominant mechanism governing the movement of
electrons, the threshold shift of the cell will be dependent solely on the voltage between the top gate,and the
N+ region. This has been proven to be true in both
simulations and experiments, where we found that

Figure 5. Single Cell Threshold Voltage Shift vs ..
Log Time During Read of a Written Cell

5-3

AFN-01883A

AP-100

Intrinsic Charge Trapping

charges will cause an increase in electric field at the
injection interface, i.e., Si0 2 /Siinterface, as shown in
Figure7b. This will in tum increase the tunnelingcurrent to the floating gate,· where the amount of stored
electrons is thus increased, causing the erase threshold
to increase. During the erase cycle, however; the polarity of bias voltage across the tunnel oxide will cause the
positive charge at Si02 /Si interface to be neutralized
through the reverse tunneling mechanism that forms
these charges. At the same time a new layer of positive
charges is formed near the anode 1 1, 12, i.e., poly/Si0 2
interface, as shown in Figure 7c. These charges will
then cause the write threshold to increase through the
same mechanism as that discussed for the erase
threshold. In addition to positive charge trapping, our
study also shows that there is a uniform distribution of
electron traps throughout the oxide 1 I, 12. When the cell
is erased or written, electrons are injected through the.
oxide and someofthem will be captured by these traps,

An ideal feature of a tunneling dielectric is that it should
never remember the number of electrons that passed
through it or the voltage that was previously applied
across the film .. Unfortunately, for thermally grown
Si0 2 there always exists a certain number of electron
and hole traps4-9. When these traps are occupied the
net charging state of the tunnel oxide will be changed
and thus cause the tunneling current across the film to
vary if the applied voltage
has...
remained the same.
\
Figure 6 plots the threshold voltage of a 2816 cell in
erase (charged) and write (discharged) slates as a function of erase/write cycles. The solid line is for a single
cell, while the dashed line is for a typical 2816 array. It is
seen that the threshold window, defined as the difference between the erase and write threshold, is
slightly increased in the first few E/W cycles and then
saturates and remains almost constant until 104 cycles.
From that point, the window begins to narrow
gradually until around 106 cycles where the. window is
. collapsed.
.
.

A) POSITIVE CHARGE INDUCED ATTHE SiO,-Si INTERFACE AT TlHE END
OF TlHE WRITE OPERATION.

~OISCHARGED STATE
.0'

Figure 6. Typical Cell and Device. Window vs.
Log Cycles

Our study shows that the behavior of the widening and
narrowing of the threshold window can be explained by
charge trapping in tunnel oxide. The window widening
effect is found to be caused by the following
mechanism:

B) BAND DIAGRAM OF SUBSEQUENT ERASE SHOWING LOWERING OFTHE
TUNNELING BARRIER BY THE TRAPPED POSITIVE CHARGE.

Poly

DRAIN

Assume a cell is to be erased following a write cycle.
During the preceding write cycle, the floating gate is
biased negatively relative to the substrate. A layer of
positive charge will be formed, either through the tunneling of holes from Si into. SiO z .or electrons in the
reversedirection. These positive charges are in general
at 20-30A away from the Si0 2 /Si interface, as in Figure
7a: At the beginning of the erase step, the positive

+
+
C) .POSITIVE CHARGE NEAR POL YSILICON-SiO,INTERFACEAT THE END
OF THE ERASE OPERATION.

Figure? Threshold Window Widening

5·4

AFN-01883A

AP-100

ing to occur at voltage differences between the floating
gate and the drain that would ordinarily be insufficient
to support tunneling.

causing the build-up of negative charges in the oxide, as
shown in Figure 8. The negative charges will reduce the
electric field at the injection interface, thus decreasing
the tunneling current and causing the threshold window
to narrow. It has been found that the electron traps are
not only preexisting in the oxide but also generated
during the E/W cycles ll- 12 because of the high field
stress and the accompanying high current flow. The
non-saturated build-up of negative charges, because of
the continuous generation of electrons traps will finally
cause the threshold window to collapse.

Erase/write cycling effects on data retention were studied by comparing 2SO"C retention before cycling to that
after 10,000 cycles. Figure 9 shows a plot of the cumulative % data retention failure during SOO hours 2SO"C
retention bake. Data from the Intel 2716 EPROM is
included as a comparison. From this data it is clear that
the retention failure rate closely resembles that of the
Intel 2716 EPROM.
Since the defect charge loss failure mechanism is temperature activated it is simple to construct screens on a
production basis for these types of failures similar to
those used on EPROMs.

BEGINNING OF ERASE
Poly

DRAIN

- + - + - - + - - + -

Figure 8. Negative Charges Trapped Uniformly
Across Tunnel Oxide

• 2816 E2 PROM
, 2816 AFTER 10.000 CY.
... 2716 EPROM

Defect Charge Loss

1Dyr.

EPROMs have been shown to have excellent data retention3 . In this section we will discuss data retention
studies that have been performed on the Intel 2816
E2 PROM. Since in E2 PROMs the number of Erase/
Write cycles during the device lifetime is 3 to 4 orders of
magnitude greater than in the EPROM, we will also
need to address the effects of cycling on data retention.

Figure 9. Intel 2816 Data Retention at 250"C,
Percent Fail vs. Time

Accelerated Test Results
As in the case of EPROMs the charge loss from. the
floating gate can be described as either intrinsic or
defect-related. We will discuss the defect-related
charge loss since the intrinsic charge loss on a typical
device is identical to the EPROM and has been described before3 .

An E 2 PROM has an additional reliability requirement
over standard PROMs. Besides the integrity of data
retention, an E 2 PROM must withstand up to 10,000
erase and write programming pulses per byte. Besides
the previously discussed window closing phenomenon
there are reliability considerations due to high voltage
operation. Dielectric breakdown 13 is a common MOS
failure mechanism, which has been shown to be highly
voltage accelerated. The reliability of the Intel 2816
during erase/write cycles was measured by performing
the full number of erase/write. cycles on each byte.
Erase/write cycling was done at 70°C and 2SoC with no
difference in observed failure rate between these
temperatures.

Analysis of cells exhibiting defect-related charge loss
shows that the leakage current has an exponential dependence on the potential of the floating gate. This is
different from the EPROM where defect leakage current exhibits a linear (ohmic) dependence on voltage. 3
The exponential dependence is indicative of electron
tunneling. The effect of the defect, then, is the lowering
or narrowing of the thin oxide barrier, allowing tunnel-

5·5

AFN-01883A

AP-100

The results of erase/write cycling are shown in Figure
lOA. Tpe devices under test are completely tested after
2,000, 5,000 and 10,000 total cycles on each byte. The
devices are programmed to several data patterns and
tested to data sheet specifications. In addition, the
devices are tested for high temperature data retention.
As can .be. seen from Figure lOA, the failure rate per
1000 cycles decreases .as a function of the number of
cycles, which is typical for defect mechanisms such as
dielectric breakdown. 13 From the time the initial data
was gathered in, 1981, recent data (Figure lOA) has
shown the failure rate to have been reduced by a'faCtor
of2.

-~ ,5,%
.2%
I .-'-'-----;---...:.::.:2K

10K

E/WCYCLES

A) INSTANTANEOUS PERCENT FAIL VS. NUMBER OF

Two major types offailures were found: Tunnel oxide
breakdown and oxide breakdown in the: row select circuitry. These failures were minimized by using standard
screening techniques for oxide breakdown. Figure lOB
shows the failure mode distribution found during
erase/write cycling of 549 devices.

EJW CYCLES,

, - - - - - 2 . 5 % OTHER

Tunneling oxide breakdown failures are cells which fail
either to program or to retain data following programming due to conduction through the thin oxide at low
electric fields. In the case of the programming failures,
the breakdown extends all the way through the oxide
layer. The data retention failures exhibit characteristics·
similar to those of the defect charge loss failures discussed in the previous section and are probably due to a
partially broken down oxide layer. Further cycling of
this type of retention failure has been found to result in
it becoming a programming failure.

B) FAILURE MECHANISM DISTRIBUTION.

Figure 10. Erase/Write Cycling Results

Table) shows expected failure rates in %/iooo hours at
a 60% upper confidence level based on expected device
life and the average number of cycles per byte. In a
typical system it is expected that some bytes will be
written more often than others,. so these failure rates
serve as a guideline.

Table I. Erase/Write Cycling Failure Rate
(per 1000 hours at a 60% UCL)
No. of Cycles

As can be seen in Table. II, acceptable failure rates are
achieved for the design goal of 10,000 erase/write cycles
per byte. To achieve 10,000 cycles per byte in ten (10)
years, each byte must be altered approximately three
times per day.

5 years
10 years
20 years

.035·
.017
.009

.06
.029
.017

.092
.047
.023

Table II. 125°C Lifetest Results
Cycles 48 Hrs 168 Hrs 500 Hrs 1000 Hrs 2000'Hrs
0
011422 1/1422a .1/443°
0/429
0/270

As a final verification of device!reliability a standard
high temperature lifetest at 125°C was performed on
devices programmed with a checkerboard data pattern.
The lifetest was performed on devices with no additional cycles and devices with 10,000 cycles on each

10,000 0/336
Total 0/1758

0/336 ;
1/1758

0/336
1/779

Failure Analysis:
a) = Non-repeatable charge gain, contamination, lev.
b) = Input leakage, contamination, lev.

byte. As can be seen from the data in Table II standard
MOS failure mechanisms were observed. This data is
significant in that it shows no additional defect mechanisms related to data retention or erase/write cycling of
the Intel 2816 EZPROM.
.

Failure rate predictions are made in Table III at a 60%
upper confidence level for both 55°C and 70°C operation. The .013%11000 hrs. failure rate at 55°C shows
good reliability comparable to other semiconductor
memories.

Table III. Failure Rate Predictions at a 60% U.C.L.
125°C
Device Hrs.

Activation
Energy

Lifetest
.Failures

Failure Rate
% per 1000 Hrs .

5. M. H. Woods and R. Williams, J. Appl. Phys.,
p 47, 1082, 1976.

This paper has discussed a number of EZPROM failure
mechanisms for both erase/write cycling and data retention. It has been shown that Fowler-Nordheim tunneling used for programming does not affect data retention. Erase/write cycling has been shown to degrade
device margins by only a small amount and is easily
guardbanded. Erase/write cycling does contribute to a
significant portion of the observed failure rate due to
oxide breakdown under high field operation. Finally, it
has been shown that E 2 PROMs can perform reliably in
applications requiring up to 10,000 erase/write cycles
per byte.

6. W. C. Johnson, IEEE TrailS. Nucl. Sci., p. NS-22,
2144, 1975.
7. D. J. DiMaria, Proceeding of the International Topical Conference on the Physics of SiO z and its
Interfaces, p. 160, 3/78.
8. E. Harari, Appl. Phys. Letter, p. 30,601, 1977.
9. C. S. Jenq, "High Field Generation of Interface
States and Electron Traps in MOS Capacitors,"
Ph.D. dissertation, Princeton Univ., 12/77.
10. C. S. Jenq, W. C. Johnson, "High Field Generation
of Electron Traps in MOS Capacitors," presented
in Semiconductor Interface Specialist Conference,
12m.

REFERENCES

11. C. S. Jenq,T. R. Rangarath, C. H. Huang, "Charge
Trapping in Floating Gate Tunnel Oxide"
presented in 1980 Non-Volatile Semiconductor
Memory workshop to be published.

I. W. S. Johnson, et ai, "16-K EE-PROM Relies on

Tunneling for Byte-Eraseable Program Storage,"
Electronics, February 28, 1980, p. 113-117.
2. R. Williams, Phys;

Rev., Vol. 140, p. 569, 1965.

12. D. R. Young, "Electron Trapping in Si0 2 ",
presented in 1980 Non-Volatile Semiconductor
Memory workshop.

3. R. E. Shiner, J. M. Caywood, B. L. Euzent, "Data
Retention in EPROMs," 1980 Proceedings of the
18th Annual Reliability Physics Symposium,
p.238-243.

13. D.Crook, "Method of Determining Reliability
Screen for Time Dependent Dielectric Breakdown," 1979 17th Annual Reliability Physics Symposium Proceedings, p. 1-5.

4. E. H. Nicollian, C. N. Berglund, P. F. Schmidt,I.
M. Andrews,}. Appl. Phys., Vol. 42, p. 5654,1971.

©INTEL CORPORATION, 1983.

5-8

,,\

ORDER NUMBER: 230714-001

AP-158

r=--= =-=---===--=--= - -,-1
I ;~~ I II I .
I I

POWER
UP/DOWN
WRITE
PROTECT

W~~

SHAPER
(ANALOG)

...J

ROY/BUSY ~-------~--r:~:;-,

• • •~AO-l0

I
I
I

I ,I

WE--4-------------------~~._~

ADDRESslI$lIIIIIIIIIIIIIIIIII____. .~~~~~

DO-7

2816

DATAII. .IIIIIIIIIIIIIIIIII. . . .I1~
:

2817A

I
~. --1

L_____________ ______ ~_J
Figure 1. E2PROM Evolution: Increasing Intelligence On-Chip

Advantages of an Intelligent E2PROM
The 2817 A has on-chip latches and timing which allow it to connect directly to the microprocessor data bus.
Writing a byte to the 2817 A is accomplished by sending a write pulse to the part. The timing for this pulse is the
same as the timing for a static RAM write cycle. Upon receiving this write pulse the 2817 A starts a write operation.
During a write operation.the 2817A's data lines go to a high impedance state, allowing normal processing to
continue on the microprocessor data bus. After the write operation has been completed, the system CPU is
notified via the 2817 A's.RDY /BUSY output. The RDY /BUSY signal frees the designer from having to time the
E'PROM write operation by either hardware timing logic or software time-out loops.

Not~ that while performing a write operation the 2817A will not respond to read or write requests. The 2817A's
data bus will remain in a high impedance state, regardless of the input control signals, until the write operation
has been completed.'

5-9

AP-158

APPLICATIC)NS FOR E2PROMS
Application Area #1: Firmware Remote Downloading
Remote downloading is important in any system that uses firmware to store program code. Storing software in
ultraviolet erasable EPROMs has the advantages of being non-volatile and allowing zero wait-state execution with
high-speed processors such as the 8 MHZ 8086-2. A limitation of this method of firmware storage is that system
'software usually has bugs in the first year or so and is frequently improved or upgraded. To make a firmware
change in a system with UV EPROMs a serviceperson must go to each custdmers site, partially disassemble each
system, replace the EPROMs, and re-assemble the system. Now, by storing some or all of the system software
code in E'PROMs, software changes can be made by telephone, without sending a serviceperson to the customer
.site. To make software changes in E'PROMs, the serviceperson calls the customer site, connects the' system to the
service center computer via telephone, and transfers the new code to the customer's system. In less than a minute
the system can be up and running with the new software at a minimal cost to the manufacturer or customer.
Firmware stored in E'PROM can be changed/upgraded remotely over any type of communications link.

All E2PROM or a Combination of EPROM/E2PROM?
System firmware can be completely stored in E'PROM to allow remote alterability of all code, or a combination
of E'PROM and UV EPROM can be used.
If the firmware is completely stored in E'PROM, any or all of the fi~mware can be replaced electrically. This type
of system is shown in Figure 2. When the system is prepared for shipping, the operating system software is
downloaded directly into the E'PROM memory after the E'PROMs have been installed in the system. When the
software is changed, upgraded, or expanded the entire new software package can be loaded remotely over
.
the telephone.

OPERATING
SY5rEM
FIRMWARE

CPU

OPERATING svsrEM
VARIABLES AND
BUFFERS

Figure 2. Total Firmware Storage in E2PROM

5-10

inter

AP-158

In a system with a large amount of program code, it may be desirable to use EPROM for storing most of the
firmware, and use E'PROM for the corrected portions of the code. (see Figure 3) This method, sometimes called
"firmware patching," allows a system to use high density EPROM to store a firmware package that is segmented
into a number of sections or routines. A small part of the system's E'PROM is used to store a short program that
calls each routine as it is needed (see Figure 4). When an error is found in one of the firmware routines, a corrected
version is loaded into the extra E'PROM space. The new corrected routine is then called instead of the erroneous
routine by changing the calling program (see Figure 5). The corrected routine and new call command can be sent
directly from a service center to the system at the customer site over any telephone line.

OPERATING SYSTEM
RRMWARE ROUTINES

MAIN PROGRAM
CONTROL
AND ROUTINE
REPLACEMENT
SPACE

CPU

VARIABLES AND
BUFFERS

Figure 3. Partial Firmware Storage in E2PROM

SPACE FOR
CORRECTED
ROUTINES

I
I
I

ROUTINE#N

Figure 4. Firmware Pcitching: Operating System Memory Map

Figure 5. Firmware Patching Example: Replacement of Faulty Routine with Corrected Routine in E2PROM

Easy Software Upgrades
Software corrections, upg~ades, or the addition of software options are easily done in a system using E'PROMs
for complete or partial firmware storage. The following is a typical example.
The OEM's service center calls the customer on the telephone and tells him that the center wishes to upgrade
the customer's system firmware. The center instructs the system operator to set a "download" switch on the system,
connect the phone to the system; and depress the system RESET switch. The new software is transferred from
the center to the customer system, where it is'storedin E'PROM. The new software package then tests itself and
the system. The system's CRT display keeps the operator informed of each step in the process. When the system
test is done, the CRT display instructs the operator to disconnect the phone, turn off the "download" switch, and
reset the system. The system is now up and running with the new software after only 40 seconds of down time.
(see section on Fast Array Programming on page 29.)

Hardware Implementation of Remote Downloading
As the new code is being received over the phone from the service center it is loaded into RAM. The code is
sent in blocks and a checksum is sent with each block. If a data error occurs due to a poor phone connection,
the block is re-transmitted. Once the entire program has been correctly received, it is transferred to E'PROM.

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In a system using both EPROM/ROM and E2PROM the downloading software routine is executed out of the
EPROM/ROM.ln a system with only E2PROM, the downloading routine can be executed either out of the system
RAM or out of E2PROM. With the first method the downloading routine is transferred from PPROM to RAM.'
(see Figure 6) The routine is then executed out of RAM and the new code is loaded remotely over a communications
link into E2PROM. A copy of the downloading routine is included in the new code in the E2PROM for future remote
upgrades. At the end of the transfer operation, control is passed back to the new program in E2PROM.

STEP 2
PERFORM REMOTE
FIRMWARE DOWNLOAD

STEP 1
. TRANSFER DOWNLOAD
ROUTINE TO RAM

E'PROM

.. NEW CODE
DOWNLOAD
ROUTINE·

COMMUNICATION
LINK

f--

RAM.
DOWNLOAO
ROUTINE

EXECUTEI:-l

Figure 6. Remote Downloading to an E2PROM-only System with Download Routine in RAM
In systems where there are two or more PPROMs the downloading routine can be initially executed out of the
first E2PROM. (see Figure 7) After the new program code has been loaded into the rest of the E2PROMs in the
system, execution control is passed to a copy of the download routine in E2PROM #2, as shown in Figure 7.
The remaining new code is then loaded into E2PROM #1.

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STEP 2
LOAD NEW CODE INTO
E'PROM #1

STEP 1
LOAD NEW CODE INTO
E'PROMS #2, #3, ETC

E'PROM #1

DOWNLOAD
ROUTINE

EXECUTE

COMMUNICATION
LINK
CPU

E'PROM #2

E'PROM #2
COMMUNICATION
LINK

E'PROM#3

DOWNLOAD
ROUTINE

EXECUTE
CPU

Figure 7. Remote Downloading to an E2PROM-only System with Downloading Routine in E2PROM

Demo Circuit
The 2817A/8088 stand-alone system design shown in this applications note can send data over a serial RS232
cable, as shown in the block diagram in Figure 8. This design can also send over any telephone line using an
acoustic coupler. The hookup for transmission over a phone line is shown in Figure 9. The software on the
applications demo board is set up to send text messages between boards when they are connected as shown in
Figure 8 or 9. The jIlessages are then stored in E'PROM memory where they remain unchanged until it is desired
to delete a message or clear the message array. It can be seen that program code rather than text messages can
just as easily be transferred between the two systems and stored in E'PROM memory. The downloading routine
would be transferred to and executed from the system RAM, The new program code would then be executed
'
directly out of E'PROM.

2817AI
8088
DEMO
BOARD

SERIAL
CABLE

COM·
LINE

MODIFIED
SERIAL CABLE

2817A1
8088
DEMO
BOARD

COM·
LINE

-+-

[£J
Figure 8. Remote Download Demo Hookup

MODIFIED

2817A18088
DEMO
BOARD

' 2817A/8088 '
DEMO
BOARD

Figure 9. Remote Downloading over a Telephone Line using the 2817A/8088 Demo Board

The "modified serial cable" shown in Figure 8 is an RS232 serial cable with the send and receive lines switched
as shown in Figure 10.

Figure 10. Modified RS232 Serial cable

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The 8088 software for performing a data block transfer between systems is shown on pages 42-44 in Appendix A:
Figures 11 and 12 show the flow charts for the data transfer software routines.

SEND A START-OFTRANSMISSION
CHARACTER

READ A
CHARACTER
FROM THE COM LINE

TELL OPERATOR
THAT THE OTHER
SYSTEM IS NOT
READY

READ CHAR
FROM RAM
BUFFER

YES

SEND CHAR TO
OTHER SYSTEM

INCREMENT RAM
BUFFER POINTER

Figure 11. Data Transfer Software: Transmitting System

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CHECK FOR START
OF TRANSMISSION
CHARACTER

SEND
ACKNOWLEDGE
CHARACTER

READ CHAR FROM
COM LINE

YES

STORE CHAR IN
RAM BUFFER

INCREMENT
RAM BUFFER
POINTER

Figure 12.. Data Transfer Software: Receiving System

AP-158

Since serial channel drivers in this design do not provide full spec RS232 levels, the serial cables should be kept
under 10 feet in length. The drivers are less than full spec to reduce the complexity of this system for demonstration
purposes. These drivers require only a 5Y supply to operate rather than the +12Y and :-12Y required for
standard RS232 interfaces. The circuit description for the RS232 serial channel drivers under the section, "2817 A/
8088 Applications Demo Board Circuit Operation"gives more information on the circuitry and also shows a design
example for a full spec RS232 interface.

Application Area #2: System Reconfiguration
Small Systems-User Friendly Operation
In small systems such as modems, point of sale terminals, and data terminals, hardware switches have been used
to set operation parameters such as baud rates, synchronous/asynchronous selection, and data constants (tax
rates, display attributes, and many others). It is usually necessary to' have printed tables and operation manuals
in order to understand how and when to set these switches. Wouldn't it be much easier if the CRT terminal asked
you what baud rate you wanted or drew a pricing table on the screen and asked you to fill it in? With E2PROM
this is easily done. Parameters entered by the operator can be stored in specific blocks, called "look-up tables,"
in E2PROM. Each time the system is powered up, the CPU sets all parameters based on the information stored
in the E2PROM look-up table.
E2PROM may also be used to re-define the function of any given key of a terminal keyboard. Intelligent terminals
and graphics terminals with these "soft keys" are highly flexible in that each user can define the functions he
needs for the most efficient use of the terminal.
'

Large Systems
Medium and large sized computer systems and computer system networks often have hardware switches and
jumpers to control peripheral channel assignments, data rates, and even user accessibility. E2PROMs are now
replacing these switches and allowing the parameters or assignments to be changed via software. Special access
,codes in firmware allow only restricted access to critical function controls. There is no need to have manuals on
hand to make simple peripheral channel changes. The firmware or software displays a "menu" on the terminal
:CRT screen and asks the user to fill in the desired numbers or parameter values. These numbers and values are
then stored permanently in E2PROM look-up tables, and the system's parameters and operational modes are set
according to the values stored in E2PROM each time the system is po'!Vered up.

Demo Board Circuit
For the purpose of demonstrating system re-configurati~n,jmagine a computer room with three computer systems
'
and three peripherals. The systems are identified as #1, #2, and #3. The three peripherals are:

Peripheral
Hard Disk
Printer
Mag Tape Drive

Indicated on demo board as:
.
Demo Channel A
Demo Channel B
Demo Channel C

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A peripheral. control unit is used to determine which system is connected to which peripheral, as shown in
Figure 13. More than one peripheral can be allocated to a given system. An E'PROM memory in the peripheral
control unit acts as a software switch to permanently. retain the present peripheral configuration until changed
by an operator. As the data storage requirements of each computer system changes, the various peripherals can
be re-assigned as needed. For more efficient operation a routine could be written. which would automatically
re-configure the peripheral channels based on the data storage requirements/requests of the systems. The
peripheral assignments on the 2817A/8088 demo board are changed by a software command from the operator.
The new assignments are stored in a look-up table in E'PROM as shown in Figure 14. Figure 15 shows the location
of the look-up table in E'PROM. In this manner the present system configuration remains in effect through
system power-down and power-up.

PERIPHERAL
CONTROL UNIT
WITH E'PROM
MEMORY

Figure 13.. SyStem R~configuration Demo: Computer Room

(DEMO CHANNEL A) HARD DISK

BYTE #2

SYSTEM #

(DEMO CHANNEL B) PRINTER

BYTE #3

SYSTEM #

(DEMO CHANNEL C) MAG TAPE DRIVE

The value "System #" Determines Which System has access to the Peripheral.

Figure 14. System Re-configuration Look-up Table
ADDRESS
(HEX)

1603
1602
OPERATORS INITIALS
ARRAY

5E2H

100
1503
1502

5E1H
SYSTEM RE·CONFlGURATION
LOOK·UP TABLE

MESSAGE ADDRESSEE
ARRAY

363
360
4

0
2817A MEMORY MAP

Figure 15. 2817A/8088 Applications Demo

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Further detailed information on the hardware operation of the System Reconfiguration Demo is given in the section

"2817A/8088 Applications Demo Board Circuit Operation" under "Demo Channel Display LED Ports:'

ApplicationArea #=3: Maintenance Log
When equipment is repaired or upgraded it is important to record the nature of each repair problem and to
document the revision levels. The information, usually filed at the user's site, is often lost. E2PROM can be used
to store maintenance record information and revision level numbers in the system itself, thus eliminating possible
confusion with other similiar. systems. With an E2PROM maintenance log, the information is always readily
accessible through the software. A few simple software commands can be used to enter or display maintenance
log information. Complete information about the system's optional equipment and even the serial number can
be stored in the system's E2PROM log. This information may also be read over a telephone line by the manu·
facturer's service center computer, eliminating the possibility of operator error in relaying the information.

Demo Board Circuit
The demo board has an E2PROM maintenance log. The memory space allocated for this log in the 2817 A is
shown in Figure 15. Entries are made from the keyboard, and the contents of the log can be displayed on the CRT
at any time. The entries are automatically numbered as they are entered.

Application Are~ #=4: Electronic Message Storage
E2PROM can be used to store messages in a small stand-alone system. The low cost and ease of use of the 2817A
makes it very desirable for small microprocessor-based designs. Visualize one of the numerical control systems
that supervises the various phases of production in an industrial plant. To keep shift operators informed of any
process changes, messages can be displayed on the CRT display. These messages, stored in the system's E2PROM
by a previous operator or a supervisor, inform future operators of temporary or permanent operation modifications, or warn them of any problems that should be closely monitored. No floppy disk needs to be left in the
terminal to store the message: all that is needed is the in-system E2PROM. This kind of message storage capability
is also a useful feature on personal computers, personal development systems, and intelligent modems.
Another application for PPROM message storage is re-programmable restricted access keys to computer systems.
In a system using E2PROM for security control, assess to critical data can be restricted based on specific text
strings, or "keys", that aree!1tered by the operator. In this type of system the "keys" are stored in E2PROM and
are changed as needed by an authorized company officer. For example, a data processing system using this
technique allows access to sensitive product cost tables only upon receipt of a specific text string that is determined
by. an authorized company officer. The text string can be as simple as "code table" or can be related to a product
lil}e name such as "Intel Personal Development System". The text key can also be a completely unrelated phrase
such as "Donald Duck" or anything else that is easy for an authorized operator to remember, yet prevents general
access. Such a security system is highly reliable because it does not depend upon electro-mechanical storage
device-it uses reliable, easy-to-design-in E2PROMs.

Demo Board Circuit
The demo board can accept a message destined for a given addressee. The message and the name are kept in
separate arrrays as shown in Figure 15. Whenever the board is powered up, the names in the addressee array are
listed on the CRT, thus giving notice of the names of the people who have messages. The messages for any specific
addressee can be viewed on command. Messages for any specific addressee can later be deleted, or the entire
message array can be cleared. The list of addressees can also be viewed at any time on command.

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MICROPROCESSOR INTERFACING
General Concepts
The 2817A is designed to be easily interfaced to a microprocessor. The control signals, CE, OE, and WE allow
the simple basic design shown in Figure 16 to be used. By using the two-line control concept 'incorporated in all
Intel 28-pin memories, the possibility of bus contention.with other memory devices on the same data bus is
eliminated. This is accomplished by connecting the CE inputto the output...2f the ~em memory address
decoder and by connecting the CPU's read and write command signals to the OE and WE inputs, respectively,
as shown in Fi~ 16. In single line control the data bus is driven as a function of the addresses. This causes
overlap on the CE select lines which can result in data bus contention as shown in Figure 17. Th~h two-line
control, the data bus is driven only when both the address select (CE) and the memory command (RD) are active
.
.
(see Figure 18).

Figure 16. Basic Microprocessor Interface

./V
OUTPUTS t
DESELECTING
OUTPUTS 1
ACTIVE

BUS
CONTENTION _-:-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _......'-'''-::~_=''::=_~-----

I-~VUET:L~P-I

Figure 17. Single-Line Control and Bus Contention

Figure 18. 1Wo·Line Control Architecture

X
ACTIVE

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AP-158

Interfacing ~ the ~088
Interfacing the 2817A to the 8088 8-bit processor is a simple task; The 8088 is a very powerful processor having
a one megaliyte direct addressing capability and the 8086 instructic:m set. Figure 19 shows the iIlterfllce used on
the 2817 A/8088 applications demo board. The 8288 bus controller is used to generate .various memory, I/O, and
control signals ..One of the signals is a delayed write pulse command, MWTC, which is used to write to t!J.e
2186 Integrated RAM. The 8288 also acts as abuffer for all the memory, 110, and control signals. As shown in
Figure i9, two-line control is used in connecting the 8088 commands and address selection lines to the 2817A.
The status of the RDY /BUSY line'is polled via the 8088's TEST input by using the WAIT instruction. See "How
to use the RDY /BUSYoutput" (below) for detailed operational infor~ation about the RDY /BUSY line.
..

Figure 19. 2817A Interfape,to the 8088

DESIGN CONSIDERATIONS

How to use the ROYIBUSY Output
The 2817 A has a .RDY/BUSYoutput that indicates when a write operation is in progress and when the 2817A
is ready for access. the RDY/BUSY line. goes low when a write operation starts and goes back high when the.
operation is completed. The system CPU can poll this output to determine when another byte can be written,'
or can use the output as an interrupt to notify the CPU when the current write operation has been completed.
Polled mode .is usually the easiest interface to design. It is Ii good choice as. long as the CPU can afford to wait'
while a byte is being written into the 2817A.'ln systems where the CPU must continue processing during the.
20 milliseconds it takes to complete a byte write operation, an interrupt mode should be used.

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Polled Methods
A polled mode can be used whenever it is not necessary for the CPU to be constantly processing while an
E'PROM byte write operation is taking place. An example is the remote upgrade of a system's software over the
telephone. The service center calls a customer and informs him that a new software package is available for the
customer'ssystem and is ready for transmission over the telephone. The customer connects the system to the
phone line, either via an acoustic coupler or a direct connection, and waits about 40 seconds (see section on Fast
Array Programming) while the new software package is being sent. During this time the only task the CPU is likely
to have is the supervision of the downloading operation, so it can afford to wait while data is being written into
E'PROM. The user'ssystem now has the latest firmware package, received quickly and inexpensively over the
phone, and good for another year or so until the next upgrade.
Polled mode is usually done by connecting the RDY /BUSY output to the CPU data bus via a three-state buffer
as .shown in Figure. 20. (If desired, the rising edge of the RDY /BUSY signal could be used to set a positive
edge-triggered flip-flop.) By polling the E2 RDY port the CPU can determine when the 2817A is ready for a read
cycle or another write cycle. If any of the Intel I/O port devices (8155, 8255, 8355, or 8755A) are being used
in the system, the RDY /BUSY output can be connected to one of the input ports of one of these devices.

Figure 20. Polled Mode: Using an 110 Input Port to Poll the ROYIBUSY Output

Polled mode for the 8086/8088 microprocessor family is particularly easy using the TEST input and the WAIT
instruction. This method is used on the 2817A/8088 demo board. The hardware hookup is shown in Figure 19.

5-27

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In the 2817A/8088 demo board design a polled method was chosen for its hardware and software simplicity. The
hardware consists of an inverter between the RDY /BUSY output and the TEST input of the 8088. In the software,
writing to the 2817A simply requires a MOY instruction, and a NOP and a WAIT instruction, as f()lIows:

MOV

E2PROM.AL

:THE AL REG HAS THE DATA BYTE TO
:BE STORED.

NOP

;THIS ALLOWS ENOUGH TIME FOR THE
:RDY/BUSY LINE TO BE RECOGNIZED
: BY THE "WAlT" INSTRUCTION

WAIT

;WAIT UNTIL THE WRITE OPERATION IS
: COMPLETED

The MOY instruction writes the data byte contained in the AL register to the 2817A. The 2817A latches the byte's
address on the falling edge of the WE signal and latches the data on the rising edge of WE. Inside the 2817 A the
write operation begins, while externally the RDY /BUSY output goes low. The inverted value to the 8088 TEST
input is a "high". When the 8088 starts to execute the WAIT instruction the CPU will poll the TEST input. The short
delay caused by the NOP instruction insures that the TEST input will be high when the wait instruction is executed.
Otherwise, the TEST input would be sampled immediately after the write command (MWTC) goes inactive
high. As long as the TEST input is high the 8088 will remain in wait state. When the write operation in the 2817A
has been completed, the RDY /BUSY output will go low, the TEST input to the 8088 will go high, and program
execution will continue with the next instruction after WAIT.

Interrupt Methods
Interrupt mode is desirable when data or parameters need to be stored at irregular and relatively frequent intervals,
and the CPU must be constantly processing. ("Relatively" meaning not so frequent as to exceed the write endurance of the E'PROM). With interrupt mode, as implemented in this application note, not only is the CPU's
processing time not significantly affected by the E'PROM write cycles, but the user's main program does not have
to worry about checking on the E'PROM to see if a given write cycle is done, nor do any status flags have to be
monitored. The user program need only write the data to be stored in E'PROM to a RAM buffer table. The status
and interrupt subroutines do the rest.
For the 8088, an 8259A Programmable Interrupt Controller is used to handle interrupt signals. The 8259A can
itself handle up to 8 interrupt lines: each line is separately maskable and priority handling is dynamically
programmable. The 2817 A's RDY /BUSY output can be directly connected to anyone of the 8259A's interrupt
inputs. The edge-triggered mode is used to trigger the interrrupt input to the 8259A when the RDY!BUSY output
returns high upon completion of the write operation. The schematic diagrams in Figure 21 and Appendix B show
the electrical connections for using an 8259A with 8088 CPU.

5-28

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Ap·158

5V
1K
16
SP/EN
IOWR
lORD

PROGRAMMABLE
INTERRUPT
CONTROLLER

CS
1
INTERRUPT.
CONTROLLER
PORT SELECT

.Figure 21 .. Interr~pt Mode: 8259A in an 8088 System

Interrupt Subroutine
The following is an example of how to imple':Ilent an interrupt-driven system in software.

A section,of the system RAM is organized exactly like the look-up table in the 2817A EZPROM. In this example
. .
the table consists of ten bytes. (see Figure 22)

Figure 22. E2PROM Look-up Table and RAM Buffer for Interrupt Mode

Each time the user program receives or produces data to be stored in E2PROM, all the user program has to do
is write the desired data into the corresponding locations in the RAM buffer table, then call a short status
subroutine. The transfer of data to the £2PROM and the monitoring of the write operation are done by the status
and interrupt subroutines.
The status subroutine checks if an E2PROM write operation is in progress, which would mean that the interrupt
subroutine is already in the process of trasnsferring data from RAM to E2PROM. If so, then nothing else needs
to be done. If no transfer is in progress, then the status routine will start an E2PROM write operation by looking
for the first byte of data in the RAM buffer table that is not equal to its corresponding byte of data in the E2PROM
table. When that write operation is complete, the interrupt subroutine is called, which checks for any more data
to be written to E2PROM. The interrupt subroutine is called after each write operation is completed until all
the new data in the RAM buffer table has been transferred to E2PROM.
The flowcharts for these subroutines are shown in Figures 23 and 24, and the software implementation for the
2817A/8088 demo board is on pages 44 through 47. The code to initialize the 8259A Programmable Interrupt
Controller is also given in Appendix A.

GET THE NEXT
BYTE TO BE
TRANSFERRED

INITIATE
E'WRITE
OPERATION

SET "E'BUSY"
FLAG

Figure 23. Status Subroutine .

5·31

AP-158

~NO~ .~ C_L~~_~_~_BU_S_Y_" ~
__

___ __

______ ••

GET THE NEXT
BYTE TO BE
.TRANSFERRED

INITIATE
E'WRITE
OPERATION

Figure 24. Interrupt Subroutine
When first initializing this look'up table, each byte in the E2PROM table is set equal to its corresponding byte in
the RAM buffer table. Any subsequent changes to the RAM buffer table are easily detected by· the status and
interrupt subroutines by comparing each pair gf corresponding locations in the two tables.

Combining Multiple ROY/BUSY Outputs in a 2817A Array
The 2817A's RDY /BUSY ·pin is an open-drain output, so multiple RDY /BUSY outputs can be or-tied together.
The value of the pull-up resistor for the RDY /BUSY o~tput can be calculated by the following formula:
R(pullup)

4.6V
2.lma -IiL

where hL (or ILl) is the total VIL input current of all device inputs connected to RDY /BUSY.
There is no limit to the number of RDY /BUSY outputs that can be or-tied together.

5-32

AP-158

Write Protection during Power Transitions
The 2817A has an on-chip write protection circuit that prevents a write operation from occurring when Vcc is
below4V.
All E'PROMs need inadvertent write protection, either internally or externally, when system power is being turned
on or off. Since an E'PROM can be programmed in-circuit the possibility exists that i!...SCan be~grammed
accidentally when system power is removed. This is because the same control signals, CE and WE, that can
normally initiate a write operation could also trigger the write mode as system power is failing. As the 5V supply
to the system falls, the system components will become unpredictable, and CE and WE may be spuriously driven
active low as shown in Figure 25. To prevent a write operation from accidentally occurring when system power
is dropping, an on-chip write protection circuit is needed to hold inactive at least one of the control signals. The
same protection is needed when Vcc is rising from OV to 5V as shown in Figure 25.

Figure 25. Typical TTL Driver Instability during Vee Power Transitions

Alternative ROYIBUSY Interfacing Methods
There are many ways to interface the 2817 A to a microprocessor using the RDY /BUSY output. The polled and
interrupt-driven modes discussed in this application note are the easiest and most commonly used methods. These
methods are compatible with the concept of an "intelligent" E'PROM which allows write operations to be done
without holding up the microprocessor.

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AP-158

When first looking at the 2817 A it might seem as if the RDY IBUSY line should be connected directly to a
'microprocessor's "ready" input since the signals have simi liar names. There are certain timing and operational
considerations, however,that make this method more difficult to design into a system than the interrupt or polled
modes described earlier. These considerations are discu'ssed below. .
,
It is possii:>le to use the RDY IBUSY output to hold up the microprocessor until the write operation is completed.
This involves tlie, insertion, of wait states into the microprocessor's instruction cycle. por the 808SA and the
8088/8086, wait states occur when the READY input is brought inactive low. This type of interface would be
implemented by connecting the 2817 J>:s RDY IBUSY output to the microprocessor's READY input., At first this
method might seem even simpler than polled mode, but a closer examination shows that this is not true.

The first consideration is the discrepancy between the timing of the 2817 A's RDY IBUSY signal and the "ready"
input of a microprocessor. Taking the 8088 as an example, the READY input is required to be low (if wait states
are desired) about the same time that the 8088's write signal goes low. The top three signals in Figure 26 show this
requirement. (The READY input shown is that of the 8284A clock generator. The output of the 8284A is then
normally connected to the READY pin on the 8088. The AMWC write signal is the output of the 8288 bus controller
which is used with the 8088 in MAX mode.) As shown by the bottom signal in Figure 26, the 2817 J>:s RDY IBUSY
output does not go low until after the WE input signal goes back high.

8088 CLOCK

AMWC (8288 OUTPUT)
TO WE ON 2817A

\ ......--:-----ff!--.....II

_I
8284A READY INPUT
(TIMING REQUIREMENn

2817A ROY/BUSY
OUTPUT

------------~--~-------------+--~I

Figure 26. 8088 Ready Input Timing Requirement

Although this timing discrepancy is not critical, the implications for any given system (and the microprocessor
used) must be examined carefully before this method of interfacing is used.
Another consideration that must be taken into account is the possibility of two or more sequential write cycles
being done by the microprocessor. An 8088 string operation, for example, would allow the OPU to doone bus
write cycle after another without any other intervening cycles. The 2817 A would be able to respond successfully
to the first write cycle, but not the second. The following would happen:

5·34

AP-158

Upon seeing the rising and falling edges of the write pulse during the first write cycle, the 2817A would start an
E'PROM write operation. The ROY/BUSY output would go low 75 ns after the rising edge of the write pulse
as shown in Figure 27. The ROY/BUSY signal would not hold up the CPU until the following write cycle. While
the first byte write operation is in. progress the 2817 A is not affected by any of the input signals and the data bus
is in a high impedance state. When this write operation is completed and the ROY/BUSY signal returns high,
the CPU will complete its second write cycle. The 2817 A will not have recognized the second write cycle, however;
because it did not see the WE signal fall.
DOES NOT AFFECT THE 2817A WHILE A WRITE OPERATION IS
IN PROGRESS

.
AMWC (8288 OUTPUT)
TO WE 2817A

/
\ ...._'--....J.

I_WRITE OPERATION IN-----"j

2817A ROY/BUSY - - - - - - -.......

PROGRESS

Jr------

Figure 27. Limitation if 2817A ROY/BUSY is Connected to 8088 Ready Input: Loss of 2nd Byte During liNo
Consecutive Write Cycles
The direct connection of the 2817A's ROY/BUSY to the 8088's (or any other microprocessor's) REAOY input
would thus require that no software be written that might cause two or more consecutive write cycles to occur.
The design of the 2817A's on-chip intelligence gives the 2817A maximum flexibility in interfacing to microprocessor-based systems. While the interrupt-driven and polled interface modes are two relatively simple (and
widely used) approaches, many other methods are possible. In each case the timing specifications should be
studied to insure that the timing requirements of all devices involved are met.

E2PROM Mapping Techniques
Inherent in the design of all E'PROM's is a 10,000 write cycle per byte limitation. As an example of the allowable
write cycle frequency, all 2048 bytes in one 2817A could be written three times each day, 365 days a year,
for 10 years before exceeding guaranteed limits. The E2PROM is not designed to be written to as often as RAM
memory. Mapping techniques such as the ones shown here, however, allow higher write cycle. frequencies than
normal to be used.

Electronic Message Storage Applications
A memory usage mapping technique such as the one used in the Electronic Message Storage Oemo described in
this applications note can more evenly distribute the number of write cycles to each byte in the E'PROM array,
thus stretching the usable life of the E'PROM. In message storage, if a pointer is used to indicate the location
of the next empty message block, that pointer has to be re-written into an E'PROM memory location each time
a message is stored in the E'PROM memory. That particular pointer storage location could reliably be used 10,000
titriesand still be guaranteed to remain within specification. If a system using this method had one 2817A for
message storage, it could store 3 messages per day, 365 days a year for 10 years.

5-35

inter

AP-158

,In the Electronic Message Storage Demo, no pointer is stored each time a message is stored. Instead, the 2817A is
partitioned into a number of fixed-length message block spaces. Empty blocks have the byte "FF" in theIst location,
as shown in Figure 28. Thus, whenever 11 message is to be stored, the 2817A is searched fora block with an "FF"
in the 1st location. Using this method, if the 2817A in amessage storage system is divided into 20 lOG-byte blocks
(2817A = 2K bytes), up to 60 messages can be stored each day, 365 days a year, for 10 years. In this example, for
every additional 2817A in the system, 60 more messages of this size could be stored each day.

ADDRESS IN
DECIMAL
1999
1900

8 BITS WIDE
BLOCK #20

DATA
100
99
(EMPTY)
0

---

BLOCK #1

FF
2817A MEMORY MAP

IN THIS EXAMPLE, BLOCKS 1 AND 4 ARE EMPTY WHILE BLOCKS
2,3 AND 20 HAVE MESSAGES

Figure 28. Message Storage Technique Example

Fast Array Programming,
In large memory storage applications where fast write times are important, fast array programming can provide 11
solution. The total write time of any block of data to the array is.reduced by a factor equal to the number of 2817As
in the array. For example, an 8K byte block of data can be ,stored in an array of sixteen 2817As (32K x 8 of E'PROM
memory) in 1/16 the normal time, that is, 8192 x 20 millisecond~ x 1/16,= 10 seconds, This is particularly useful in
designs that require a large amount of non-volatile memory to be used in,harsh environments. No additional hardware
or software is required: the memory address decoder is simply connected according to the schematic diagram in
Figure 29. The result is a decoding of the least significant address lines rather than the most significant address lines.

Notes: 1. Addresses Ao -AN - 1 are cannected to decoder for an
arra of 2N devices.
2. All ~DYiB[jsy outputs are
tied together.
3. 2817A address inputs
AO - A10 are connected to
system addresses
AN -

#2N

AN+ 10.

Figure 29. Fast Array Programming
To transfer data to the E2PROM memory, a series of high-speed, system write cycles are performed, one immediately after the other, to the E2PROM memory array. Each 2817 A will internally perform a write operation using one
of the successive bytes. For example, if the array in Figure 29 had 64 2817As, then 64 bytes would be written in each
burst of high-speed write cycles. The total program.ming time for each 64-byte block would be the same as for one
2817A: 20 milliseconds.
Effectively, the total time needed to write a block of data into the array shown in Figure 29 is equal to:
Total Write Time =
write time (20 ms) x # of bytes to be stored
# of 2817 A devices in the array
The more 2817As there are in the array, the shorter the write time for a given block of data. For example, writing
a block of 16K bytes to an array of 32 2817As (64K bytes ofE2PROM) would take 10 seconds (12K bits per second).
A more significant application would be a 1f4 megabyte E2PROM array (128 2817As). Writing lOOK bytes to such
an array would take only 15 seconds, which is 51K bits/second.

5-37

inter

AP-158

MULTI-DEVICE CONFIGURATION ON THE 28-PIN SITE
Intel's line of 28-pin memory devices is designed to be easily interchangeable on a single 28-pin site. The hardware
and software designer need no longer bear the risk of board re-design due to inaccurate estimations of the amount
and types of memory'required.E'PROMs, EPROMs, and RAMs can be mixed and matched in the same 28-pin site.
A small number of jumpers can be used to accommodate the different signals that use pins 1 and 27. This section
has examples of how to layout a printed circuit board memory array to accommodate any combination of 28-pin
memories, including the multi-device sites on the 2817A/8088 applications demo.
The chart in Table 1 shows the different signals for pins 1 and 27 for Intel's 28-pin memories.

Table 1. 28-Pin Memory Device Compatibility

8Kx8 32Kx 8 16Kx 8 8Kx 8 8Kx 8 2Kx 8

2Kx 8 8K x 8 8K x 8 16K x 8 32Kx 8 8Kx 8

2817A/8088 Applications Demo Multi-Device Sites
Figure 30 shows a pin matrix of nine pins that can be used to allow different types of 28-pin memory devices to be
plugged into socket U 18 on the 2817 A/8088 applications demo board. A 27128 UV EPROM is normally plugged
into socket U18 in Figure 30. A 2817A E'PROM is plugged into socket U17, and a 2186 iRAM resides in socket U19.
Figure 31 shows which jumper pairs to connect for anyone of the following devices in socket U18:
2817A
2764
27128
27256
2186

2Kx8 E'PROM
8Kx8 E'PROM
8Kx 8 UV EPROM
16K x 8 UV EPROM
32K x 8 UV EPROM
8Kx 8 iRAM

5-38

AP-158

I _0.11'1
L.
_ _ _CAP
_ _ ..JI

0.11'1CAP

L _ _ _ _ _ _ JI

10--------0
I
I
0
0
I
I
0
0
I
I
0
0
2817A
I
I
E'PROM
0
0
I
I
0
0
I
I
0
0
U16
I
I
0
0
I
I
0
0
I
I
0
0
I
I
0
0
I
I
0
0
I
I
0
0

,.------,

r------,

~------,

I __
0.11'1
L.
_ _CAP
_ _ .JI

0--------0

10-.-------0
I
I
0
0
I
I
0
0
I
I
0
0
2817A
I
I
E'PROM
0
0
I
I
0
0
I
I
0
0
U17
I
I
0
0
I
I
0
0
I
I
0
0
I
I
0
0
I
I
0
0

27128
EPROM

U18

0
0
I
I
0--------0

10---------0
I
I
0
0
I
I
0
0
I
I
. 2186
0
0
I
I
iRAM
0
0
I
I
0
0
I
I
0
0
U19
I
I
0
0
I
I
0
0
I
I
0
0
I
I
0
0
I
I
0
0
I
I
0
0
I
I
0--------0

Figure 30. 2817A/8088 Applications Demo 28-Pin Site Array

5·39

AP-158

JUMPER CONFIGURATION

·If·---~-~
'0.11" CAP '.
.
---T....:.....;..0·28
1
.
1

2817A (2K x 8)
5V ONLY
. E'PROM

2817A (8K x 8)
5V ONLY
.
E'PROM

2764 (8K x 8) .
27121i ·(16K x 8) ,
EPROM
.

27256 (32K x 8)
EPROM

Figure 31. 2817A and 28·Pin EPROMliRAM Site
.,'

If three 2817A's are plugged into the board in sockets V16, V17, and V18, anew firmware package can be remotely
downloaded via the comline interface. The program code for performing the downloading operation would reside
in the 2817A in socket U18. The routine in this E'PROM would perform most of the downloading operation. After
the 2817As in sockets V16 and U17 have been loaded, program control would be transferred tp one of the E'PROMs
in those sockets in order to load the 2817A in socket U18 (see also"Application': Firmware Remote DoWnloading"
on page 3) .

.By designing with the JEDEC-compatible 28-pin site and using a small number of jumbers as shown in the examples,
boards and systems can be designed to be highly flexible and to have a long product life.
2817A/8088 APPLICATIONS DEMO BOARD CIRCUIT OPERATION
The memory map in Figure 3i shows the organization of the memory space in this design. The i!lput/ output map in
Figure 33 shows the addresses of the I/O ports. Figure.34 shows a simple block diagi-am of the 2817A/8088 ~4~_.

10 AO
9 Al
8 A2
7 A3
6 A4

CLK __----------"------1-------1

21 Al0
23 All'
2 A12

RE5ET __________________-L__~---------l

1100
110,
1102
1103
1104
.1105
1106
1107
,U19

2186

IRAM--------------------------------------~~~~~----~~~~--~

~~.------~---------~------~--~-----~----~~

Figure 40. 2817A/8088 Applications Demo

Figure 41. 2817A/8088 Applications Demo

: 10
5V
RP1
1
·.10r----

Figure 42. 2817A/S()88 Applications Demo, Demo Ch~n~~ls A, B, C Display LED's

APPENDIX C
PRINTED CIRCUIT BOARD LAYOUT

5-63

AP-158

APPENDIX D
PARTS LIST
2817A18088

Switches
Description
D8088
D8284A
D8282
C2186-30
D27128-3
D3205
D8251A
74LS393
7407
74LS14
D8288
74LS374
74LS32
74S112
74LS08
2817A

Micro Switch #21SM284

25 Pin RS232 Connector
ITTJO-DBP-25SCA 8040
Molex Connector for Power Supply
Housing #22-01-2037 2695 Series
Peg 11'15-04-9210
Wafer #22-05-3031.7478 Series
Terminals #08-56-01102759 Series

Headers
4.7 Microfarad
0.1 Microfarad Ceramic
25 Microfarad, 25V

6 Pair Unit

Transistors
2

28 Pin Low Profile Soldertail

2.7KOhm
4.7KOhm
lK
510 Ohm
47K
5.1K
22 Ohm
330 Ohm
250 Ohm 1j2W
50 Ohm l/zW
220 Ohm R-Pak 9 Pin SIPI

5-65

inter

AP-158

APPENDIX E
FABRICATION/LAYOUT DRAWING

~ ~ 9 ~~ooM' "' . ,: :""'

~ "'"~ r~ ~"n f'~ ~""~ 0""~ ~ij'

intel'
e 2 PAOM 18088
APPLICATIONS DEMO

1_4- - - - - 6,50INCHES-------1

16-K EE-PROM relies on tunneling
for byte-erasable program storage
Thin oxide is key to floating-gate tunnel-oxide (Flotox) process
used in 2,048-by-:8-bit replacement for UV-light-erasable 2716 E-PROM
by W. S. Johnson, G. L. Kuhn, A. L.· Renninger, and G. Perlegos,

o The

erasable programmable read-only memory, or
is the workhorse program memory for micro:
processor-based systems. It is able to retain data
for years, and it can be reprogrammed, but to clear out
.its contents for new data, ultraviolet light must be made
to stream through its quartz window. This works well for
many applications, but the technique foregoes singlebyte-in favor of bulk-erasure and in-circuit 'selfmodification schemes.
Electrical erasability is clearly the next step for such
memories, but like ultraviolet erasure a few years back,
it is hard to achieve. In fact, the design of an electrically
erasable read-only memory is paradoxical. In each cell,
charge must somehow be injected into a storage node in
a matter of milliseconds. Once trapped, however, this
charge may have to stay put for years while still allowing
the cell to be read millions of times. Although these
criteria are easily met individually, the combination
makes for a design with conflicting requirements.
These demands are morethan·met in a new EE-PROM,
which is a fully static, 2-K-by-8-bii, byte- or
E-PROM,

Intel Corp.• Santa Clara. Gelif.

chip-erasable nonvolatile memory. At 16,384 bits, this
new d.esign not only meets the goal of high density, but
also has long-term retention, high performance, and no
refreshing requirement, in addition to functional
simpliCity unmatched by present nonvolatile memories .
The device' need. not be removed from a board for
alterations, and performance is consistent with thelatest
generation of l6-bit microprocessors such as the 8086.
This achievement required the development of a new
nonvolatile process technology, HMOS-E, as well as a new
cell structure, Flotox, for floating-gate tunnel oxide.
Conflicting requirements

Nonvolatile semiconductor memories generally store
informatiori in the form of electron charge. At cell sizes.
achievable today, this charge is represented by a few
million electrons. To store that many electrons in a
IO-millisecond, program cycle requires an average
current on the order of 10. 10 amperes. On the other hand,
if it is essential that less than 10% of this charge leaks
away in 10 years, then a leakage current on the order of.

Electronics/February 28, 1980

5-68

AFN-01913A

AR-119

The next memory. The 16-K electrically
erasable programmable read-only memory is
eminently suitable for microprocessor
program storage. Organized as 2,:148 by 8
bits, the EE-PROM allows full-chip or
individual-byte erasu,e using the same
supply (V pp) as for programming.

5ECONO'LEVEL
POLYSILICON

FIRSTHVEL
POLYSILICON.
IFLOATINGI

GATE OXIOE

p SUBSTRATE

lal
FI RST ·LEVEL
POLYS1L1CON
IFLOATINGI

+VG

SECONO·LeVEL
POLYSILICON

GAfE OXIDE
p SUBSfRATE

Ibl

1. Flret Famol, now Flotox. The Famos cell (a) found in all
E-PROMs stores charge on the floating gate by avalanche means.
Flotox cell (b). the heart of the EE-PROM. relies on electron tunneling
through thin oxide to charge and discharge the floating gate.

10. 21 A 'or less must be guaranteed during read or storage
operations. The ratio of these curren'ts, I: lOll, represents
a difficult design problem. Few charge-injecting
mechanisms are known that can be turned off reliably
during nonprogram periods for such a ratio.
One structure that has proven capable of meeting such
stringent reliability requirements has done so for many
millions of devices over the last nine years. This is the
floating-gate avalanche-injection MOS (Famos) device
used in the 1702,2708,2716, and 2732 E-PROM families.
In the Famos structure, shown in Fig. la, a polysilicon
gate is completely surrounded by silicon dioxide, one of
the best insulators around. This ensures the low leakage
and long-term data retention.
To charge the floating gate,electrons in the
underlying MOS device are excited by high electri<; fields
in the channel, enabling them to jump the
silicon/silicon-dioxide energy barrier between the
substrate and the thin gate dielectric. Once they
penetrate the gate oxide, the electrons flow easily toward
the floating gate as it was previously capacitively
coupled with a positive bias to attract them.
Because of Famos' proven reliability, the floating-gate
approach was favored for the EE-PROM. The problem, of
course, was to find a way to discharge the floating gate
electrically. In an E-PROM, this discharge is effected by
exposing the device to ultraviolet light. Electrons absorb
photons from the uv radiation and gain enough energy
to jump the silicon/silicon-dioxide energy barrier in the
reverse direction as they return to the substrate. This
suffices for off-board program rewriting, but ,the object
of the EE·PROM is to satisfy new applications that
demand numerous alterations of the stored data without
removing the memory from its system environment.
What evolved was the new cell structure called Flotox
(Fig. I b).,
In the quest for electrical erasability, many methods
were considered, and several potentially viable solutions
were pursued experimentally. ,one initially attractive

Electronics/February 28, 1980

2. Tunneling. For a thin enough oxide" asshown here, under a field
strength of 10" V/cm, Fowler-Nordheim tunneling predicts that a
certain number of electrons will acquire enough energy to jump the

3. Current characteristic. In Fowler-Nordheim tunneling, current

forbidden gap and make it from the gate to the substrate,

the difference between programming and reading is at least 8,8 V.

approach attempts to harness a parasitic charge-loss
mechanism discovered in the earIie~t E-PROMs. Referring
again to Fig. I a, the polysilicon grains on the top surface
of, the floating gate tend, under, certain processing
conditions, to form sharp points called asperities. The
sharpness of the asperities creates a very high local
electric field, between the polysilicon layers, shoving
electrons from the ,floating gate toward the second level
of polysilicon. This effect is purposely subdued in today's
E-PROMS by controlling oxide growth, on top of the
floating gate because this parasitic, electron-injection
mechanis,m would otherwise interfere, with proper
E·PROM programming.
It was first thought that asperity injection could be
used 'to erase the cjJip. In fact, f411y functional~
electrically erasable test devices were produced; but the
phenomenon' proved unreproducible, and the devices
tended to, wear out quickly after repeated program and
erase cycling. After over a year's effort, that approach
was a!:>andoned.

flow freely toward the positive electrode.
This posed two fundamental problems. First, it was
commonly believed that silicon dioxide breaks down
catastrophically at about 10' v/cm, and MOS EETs are
normally 'operated at field strengths 10 times below this.
Second, to induce Fowler-Nordheim tunneling at
reasonable voltages (20 v), the oxide must be less than
200 angstroms thick. Oxide thickness below about
500 A had rarely even been attempted experimentally,
and it was feared that defect densities might prove
prohibitively high.
To be weighed' against these risks, however, were
several advantages. Tunneling in general is a low-energy,
efficient process that eliminates power dissipation:
Fowler-Nordheim tunneling in particular is bilateral and
can be used for charging the gate as well as discharging
it. FinaIIy, the tunnel oxide area could be made very
small, which is of course consistent with the needs of
high-density processing.
With these motivating factors, development was
initiated to grow reliable, low-defect oxides less than 200
A thick. The success of this effort resulted in the
realization of a working cell structure caIIed Flotox.
The Flotox device cross section is pictured in Fig. lb.
,It resembles the Famos structure except for the
additional tunnel-oxide region over the' drain. With il
voltage V. applied to the top gate 'and with the drain
voltage V d at 0 v, the floating gate is capacitively
coupled 'to a positive potential. Electrons are attracted
through the tunnel oxide to sharge the floating gate. On
the other hand, applying a positive potential to the drain
and grounding the gate reverses, the process to discharge
the floatjng gate.
Flotox, then, provides a simple, rep~oducible means
for both programming and erasing a -memory cell.' But

Tun'neling solution ,

The solution turned out to be the one that initially
seemed impossible. After investigating many methods of
producing energetic electrons, it was deCided to
approach the problem from a different direction: to pass
19w-energy electrons through the oxide. This could be
accomplished through Fowler-Nordheim tunneling, a
well-known,mechanism, depicted by the band diagram in
Fig."2. Basically, when the electric field applied across
an insulator exceeds approximately I 0' volts per
centimeter, electrons from the negative electrode (the
polysilicon in Fig: 2) can pass a short distance through
the"forbidden gap of the insulator and enter the
conduction band. Upon their arrival there, the electrons

flow depends strongly on voltage across the oxide, rising an order of
magnitude for every 0,8 V, Charge retention is adequate so long as

EleCtronic8/February 28, 1980

5-70

AFN-01913A

AR·119
This value, including margins for processing
variations, is reasonable. Furthermore, data is not
disrupted during reading or storage so that no refreshing
is required under normal operating or storage conditions.
Extensive experimental testing has verified that data
retention exceeding 10 years at a temperature of 125°C
is possible.
Another important consideration is the behavior of the
electrically erasable memory cell under repeated
program erase cycling. This is commonly referred to as
endurance. The threshold voltage of a typical Flotox cell,
in both the charged and discharged states, is shown in
Fig. 4 as a function of the number of programming or
erasing cycles. There is some variation in the threshold
voltages with repeated cycling but this remains within
tolerable limits out to very high numbers of cyclessomewhere between 10' and 106 cycles.

CHARGED STATE

,..-----L.__

DISCHARGED STATE

.4. Good endul'llnce: The endurance of the EE-PROM depends on
the threshold-voltage difference between. the charged and
discharged states. Though repeated cycling degrades thresholds, the
chip should stay within tolerable limits for 10' to 10' cycles.

what about charge retention and refresh considerations
with such a thin oxide? The key to avoiding such
problems is given in Fig. 3, which shows the exceedingly
strong dependence of the tunnel current on the voltage
across the oxide. This is characteristic of
Fowler-Nordheim tunneling.
The current in Fig. 3 rises one order of magnitude for
every 0.8-v change in applied voltage. If the 11 orders of
magnitude requirement is recalled, it is apparent that the
difference between the voltage across the tunnel oxide
during 'programming and that during read or storage
operations must be in excess of 8.8 V.

Putting Flotox to work

The Flotox cell is assembled into a memory array
using two transistors per cell as shown in Fig. 5. The
Flotox device is the actual storage device, whereas the
upper device, called the select transistor, serves. two
purposes. First,. when discharged, the Flotox device
exhibi.ts a negative threshold. Without the select
transistor, this could result in sneak paths for current
flow through nonselected memory cells. Secondly, the
select transistor prevents Flotox devices on nonselected
rows from discharging when a column is raised high.
The array must be cleared before information is
entered. This returns all cells to a charged state as shown
schematically in Fig. Sa. To clear the memory all the
select lines and program lines are raised to.20 V while all
the columns are grounded, This forces electrons through
the tunnel oxide to charge the f1oatin~ gates on all of the

5. .Working, To clear a Flotox cell, select and program lines are raised to 20 V and columns are grounded (a) .. To write· a byte of'dlita, the
program line Is gro~nded and the columns of the selected byte are raised or lowered according to the data pattern (b) ..

Electronics/February 28, 1980
5-71

DATA IN
OUTPUT __
ENABLE, DE

(FOR BYTE CLEAR ALL
DATA IN = HIGH) ,

Vpp

(a)

(b)

In terms of its pinout and control functions, the
EE-PROM has evolved from the 2716 E-PROM. Both are
housed in 24-pin dual in-line packages, for instance, and
both offer a power-down standby mode. In addition; both
utilize the same powerful two-line control architecture
for optimal compatibility with high-performance
microprocessor systems. Referring to Fig. 6a, it is seen
that both control lines, chip enable (CE) and output
enable (OE), are taken low to initiate a read operation.
The purpose of chip enable is to bring the memory out 'of
standby to prepare it for addressing and sensing. Until
the output-enable pin is brought low, however, the
outputs remain in the high-impedance state to avoid
system bus conten'tion. In its read mode, the EE-PROM is
functionally identical to the 2716.
A single + 5-v supply is all that is needed for carrying
out a read. For the clear and write functions, an
additional supply (V pp) of 20 V is necessary. The timing
for writing a byte is shown in Fig. 6b. The chip is
'powered up by bringing CE low. With address and data
applied, . the write operation is initiated with a single
IO-ms, 20-v pulse applied to the V pp pin. During the

t,"~J
>C

ADDRES~......_ _ _ _' V_A_L_IO_ _ _ _.....

selected rows. An advantage of this EE-PROM over
E·PROMs is the availability of both byte- and chip-clear
operations. The byte-clear one is particularly useful fora
memory of this size. When it is initiated, only the select
and program lines of an addressed byte rise to 20 v.
To write a bite of data, the select line for the
addressed byte is raised to 20 v while the program line is
grounded as shown in Fig. 5b. Simultaneously, the
columns of the selected byte are raised or lowered
according to the incoming data pattern. The bit on the
left in Fig. 5b, for example, has its column at a high
voltage, causing the cell to discharge, whereas the bit on
the right has its column at ground so its' cell will
experience no change. Reading is accomplished by
applying a positive bias to the select and program lines of
the current. A cell with a charged gate will remain off in
this condition but a discharged cell will be turned on.
From the outside

DATA VALID

\~_______----""--Jf '

L
(e)

6. Timing. The Flotox memory's operating modes are shown for
reading·(a), writing or'clearing of bytes (b), and chip clearing (c).
Both writing and erasing require a 1D;ms program-voltage pulse. The
read mode is functionally identical to that of a 2716 E-PROM.

,write operation, OE is not needed and is held high,
A byte clear is really no more than a write operation,
As indicated in Fig, 6b, a byte is cleared merely by being
written with all 1s (high). Thus altering a byte requires
nothing more than two writes to the addressed byte, first
with the data set to all 1s and then with the desired data.
This alteration of a single byte takes only 20 ms. In other
nonvolatile memories, changing a singie byte requires
that the entire contents be read out into an auxiliary
memory. Then the entire memory is rewritten. This
process not only requires auxiliary memory; for a
2-kilobyte device it takes about one thousand times as
long (20 ms vs 20 seconds).
Chip clear timing is shown in Fig. 6c. The only
difference between byte clear and chip clear is that OE is
raised to 20 v during chip clear. The entire 2 kilobytes
are cleared with a single lO-ms' pulse. Addresses and
data are not all involved in a chip-dear operation.
0

Electronics/February 28, 1980

5-72

AFN.()1913A

2004
4K (512 x 8) NON-VOLATILE RANDOM ACCESS MEMORY
•

5 ~It Only Operation

•

Fast Static RAM ReadlWrite Cycles
2004-2, 200ns Max.
2004, 250ns Max.
2004-3, 300ns Max.

•

10-Year Data Retention for each STORE

•

Minimum 1 0,000 Non-~Iatile STORE
Cycle Endurance

•

Unlimited Endurance for Read, Write,
and RECALL Cycles

•
•

HMOS*-E FLOTOX Cell Design
Conforms to JEDEC Byte-Wide
Universal Site

•

Single Line STORE & RECALL

•

10ms Self-Timed STORE Cycles for 2004-2
and 2004 (20ms for 2004-3)

•

Automatic Recall on Power Up
Write Protect Circuit to Preserve Data
On Power-Up and Power-Down

Lower Power Standby Mode

The Intel 2004 Non-Volatile Random Access Memory (NVRAM) is a 4K device with 512 x 8 architecture. It provides
the real-time read/write functions of a static RAM together with the reliable non-volatile storage capability of an
E2PROM array to preserve its memory contents when power is removed.
Internally, the 2004 NVRAM consists of a high speed static RAM array backed up, bit-for-bit, by an E2PROM array
for non-volatile storage. The transfer of memory data between the static RAM and the E2PROM array occurs in
parallel for fast storage and recall as well as minimal system support.
Two functions are provided to transfer data between the volatile RAM and its non-volatile E2PROM counterpart.
The STORE function transfers RAM data into the E2PROM while the RECALL function fetctws E2PROM data and
places it in the RAM array. Both functions are controlled by a single NE signal which can easily be activated with
traditional circuitry in memory mapped space, through an I/O port, or from the output of a power-fail detector.
The RAM operating characteristics of the 2004 NVRAM provides high speed microprocessor performance with
unlimited endurance. In the non-volatile storage mode, data retention is specified at over 10 years for each
STORE operation. Over 10;000 STORE operations can be performed reliably.
The 2004 NVRAM is furnished in a 28-pin byte wide package with its address, data and control lines configured
according tothe standard JEDEC universal 28-pin site.
"HMOS is patent process of Intel Corporation.

r\==="i1"
ADDR
&
DATA

NON·VOLATILE ENABLE
(STORE/RECALL CONTROL)
WRITE ENABLE
NO CONNECT'

21N.C.
20 t!
19 1,10,

WAVEFORMS
WRITE
WITH SINGLE LINE CONTROL
CONDITION: NE = V,H (OUTPUT ENABLE AND DISABLE TIMES SHOWN ONLY)

2004-2
Symbol
tSOE
tsp

Parameter

DE Disable to STORE Function
STORE Pulse Width

tSTR

STORE Cycle Time

tVMIN

Vee Above Vccmin after STORE
Operation Initiated

Setup Time to WE for STORE
Initiation Cycle

Hold Time after WE for STORE
Initiation Cycle

inter

2004

WAVEFORMS (continued)
STORE INITIATION CYCLE UNDER NORMAL CONDITIONS

STORE II'jITIATION CYCLE DURING POWER FAIL

1. During a STORE initiation cycle, addresses and I/O inputs = DON'T CARE.
2. For a STORE cycle, WE TJ:)ust not go low before NE. Otherwise, a RAM write cycle will result
3. A lockout 1eature on the NE input prevents subsequent STORE cycles from occurring until NE is brought back high.
The NE input should therefore be brought back high after a non power-fail STORE operation is initiated to allow normal
read/write access after completion of the STORE operation.
4. Vccmin = 4.75V for 5% Vcc spec
5. Once a STORE operation has begun, al.: inputs are ignored and .the outputs are. in a high impedance state.

WE Disable to RECALL Command

Setup Time to RECALL Command

tRH

HoldTime after RECALL Command

AUTOMATIC RECALL DURING POWER UP2

Vee

1/0

RAM CONTAINS DATA FROM
E'PROM STORAGE ARRAY
RECALL INITIATION CYCLE UNDER NORMAL CONDITIONS

(NOTE 3)

1 - - - - - - , - - tReL
1/0

------t
l!««(
RAM CONTAINS DATA FROM
E'PROM STORAGE ARRAY

NOTES:
1. During a RECALL Initiation Cycle, the address and data inputs = DON'T CARE.
2. During Automatic Power-Up RECALL, CE = WE = OE = NE = DON'T CARE.
3. Once a RECALL operation has begun, all inputs are ignored and the outputs are in a high impedance state.
4. Vccmin = 4.75V for 5% Vcc spec

5-82

Units

Il S
ns
ns

2816A
16K (2K x 8) ELECTRICALLY ERASABLE PROM
• 5 Volt Only Operation
• fast Read Access Time:

• HMOS*-E flotox Cell Design
• Minimum Endurance of 10,000
Erase/Write Cycles per Byte

,-2816A·2,200ns Max
,-2816A, 250ns'Max
--2816A·3, 350ns Max
-2816A·4, 450ns Max

• Unlimlte,d Number of Read Cycles
., Conforms to JEDEC Universal Site
• Erase/Write Specifications
Guaranteed 0-70°C

• Byte Eras,e/Write with TTL Level WE
Signal,
'

• Write Protect Circuit to Preserve Data
on Power Up and Power Down

• 9ms Byte Erase/Write Time
• 9ms Chip Erase Time

The intel2816A is a 16,384-bit electrically erasable programmable read-only memory (E 2 PROM), The 2816A can
be easily erased and reprogrammed on a byte basis with a TTL-low level signal on WE. The 2816A operates from
Ii singlE! 5 Volt supply. External programming voltage and write pulse shaping are not required because they are
g'enerated by on-chip circuitry.
' .
The Intel 2816A is compatible with the Intel 2816 E2 PROM. Dual voltage detection logic allows the 2816A
to use an existing, externally supplied high voltage programming pulse required with the 2816 to write to
the Intel 2816A. No hardware changes are required when substituting a 2816A in an existing 2816 socket.
System upgrades to 5 volt only operation' can be implemented, however, by removing the 21Vand write
shaping circuitry. The 2816A, like the 2816, has fast read access speeds allowing zero wait state read
cycles with high'performance microprocessors such as the iAPX286.
,

The,electrical erase/write capability of the 2816A makes it ideal for a wide variety of applications requiring
in-system, ncm-volatile,erase and write,. Any byte can be erased in 9ms without affecting the data in any other
byte. Alternatively, the entire memory can be erased in 9ms allowing the total time to rewrite all2k bytes to be cut
by 50%. The 2816A'is part of the Intel E 2 PROM family that provides a significant increase in flexibility allowing
new applications (remote firmware update of program code, dynamic parameter storage) never before
possible.
'
The 2816 E2 PROM possesses Intel's 2-line control architecture to eliminate bus contention in a system
environment. ,A power down mode' is also featured; in standby mode, power consumption is reduced by over
50% without increasing access time. The standby mode is achieved by applying a TTL-high signal to the CE
input.
'
'HMOS is a patented process of Intel Corporation
DATAIflPUTSlOUTPUTS

Figure 1. 2816A Functional Block Diagram

WRln ENABLE (VPP OPTION)

DATA OUTPUTS
DATA INPUTS

10
11

~----'

Figure 2. Pin Configuration

Intel Corporation Assumes No Responsibilly for the Usa at Any ClrciJitry Other Than Circuitry 'Embodied
©INTEL CORPORATION, 1983,

in an Intel Product: No Other Circuit Patent Licenses aTe Implied.
ORDER

NUMB~~;~~O~~;~:!

2816A

DEVICE OPERATION
The 2816A has six modes of operation, listed in Table
1. All operational modes are designed to provide
maximum microprocessor compatibility and system
consistency.
Table 1 Mode Selection

, requirement because of read access time~typically
less than 250ns. Program execution directly out of
electrically erasable memory has never before been
possible; the 2816A opens this new, powerful applications segment.
.
/
The 2816A uses Intel's proven 2-line control architecture for read operation. The 2-line control function
removes bus contention from the system environment and allows low power dissipation (by deselecting unused devices).

All control inputs are TTL-compatiblewith the excep.
tion of chip erase.

Figure 3 shows the timing disadvantages of a
single-line control architecture. 2-line control,
shown in Figure 4, has been developed by Intel to
solve this bus contention and the associated system
reliability problems. Both CE and OE must be at logic
low levels to obtain information from the device. Chip
enable (CE) is the power control pin and should be
used for device selection. The output enable (OE) pin
serves to gate internal data to the output pins.
Assuming that the address inputs are stable, address
access time (tACC) is equal to the delay from CE to
output (tCE)' Data is available at the outputs after a
time delay of tOE, assuming that CE has been low and
addresses have been stable for at leasUACC-tOE'

READ MODE
Optimal system efficiency depends to a great extent
on a tightly coupled microprocessor/memory interface. The E2 PROM device should respond rapidly
with data to allow the highest possible CPU performance. The 2816Asatisfiesthis high performance

Figure 5. shows a typical system interconnection.
Here the 2816A contains program information that
the 8086 requires for system function. CE (pin 18) is
decoded from addresses as the primary device selection function. OE (pin 20) should be made a common
connection to all devices in system, and connected

Chip Erase
No Operation

-tACC----;--ADDRESSES

./
OUTPUTS t
DESELECTING

DATA BUS

"\./ OUTPUTS 1
ACTIVE
)

Figure 3. Single-Line Control and Bus Contention

Figure 4. Two-Line Control Architecture

Figure 5. iAPX 86/2816A Read Architecture

5·85

AFN-00865A

2816A

the chip erase function is performed, all 2K bytes are
returned to a logic 1 (FF) state.

to the RD line from the system control bus. This'
assures that all deselected memory devices are in
their low power standby mode and that the output
pins are only active when data is desired from a
particular memory device.

The 2816A's chip erase function is engaged when the
output enable (OE) pin is raised above 9 volts. When
OE is greater that 9 volts and CEand WE are in the
n'cirmal write mode,' the entire array is erased. This
chip erase function takes approximately 10ms. The
data input pins must be held to a TTL-high level
during this time.

WRITE MODE
'The 2816A is erased and reprogrammed electrically
as opposed to EPROMs which require ultraviolet
light for erasure. The device offers dynamic flexibility
because both byte (sil1gle location) and chip erase
are possible,

STANDBY MODE
The 2816A has a standby mode which reduces active,
power dissipation by 50% from 100ma to 50ma. The
2816A is placed in standby mode by applying a TTLhigh signal ,to the CE input. When in the standby
'mope, the outputs are in a high impedance state,
independent of ,the OE and WE input.

A close examination of the broad application spectrum for the E2 device reveals an inherent need for
single location erase capability. Program'store applk
cations can be classified in several ways. Figure 6
lists various storage modes and the required erase
function. In greater than .80% of all cases, a byte
erase feature is necessary.

APPLICATION TYPE

• STRICT PROGRAM STORE
• RELOCATABLE PROGRAM STRUCTURE
• PROGRAM STORE EXTENSION
., PROGRAM EXECUTioN CONSTANTS
• PROGRAM DEPENDENT DATA STORE
• DATA STORE APPLICATIONS

The, standby mode for the 2816A is a superset of the
standby mode for the 2816. The standby mode for the
28.16A includes the E/W Inhibit mode of the 2816.

IDEAL
'ERASE MODE

NO OPERATION MODE
This mode is frequently entered while in a read or
write cycle. In the READ cycle, CE may go low before
OE goes low because tCE(CE to Output Delay) is
longer than tOE (OE to Output Delay). While CE is low
with OE and WE at TTkhigh, no READ, ERASE, or
WRITE operation will occur. The read operation
would begin in the READ cycle when OE input also
falls'to TTL-low.

CHIP
BYTE
BYTe
BYTE
BYTE
,BYTE

Figure 6. Microprocessor Storage Types

To write a particular location, that byte must be
erased prior to a data write. Erasing is accomplished
by placing the byte address atthe address input pins,
applying logic 1 (TTL-high) to all eight data input
pins, and lowering CE, WEto VIL. The OE pin must be
held at VIH during byte erase and write operations.
The WE pulse width must be a minimum of 9ms, and '
, a maximum of 15ms. Once the location has been
; erased, the same operation is repeated for a data
write, The data input pins in this case reflect the byte
that is to be stored. The data to be programmed,
address and control signals mllst be presented to the
2816A throughout the required programming time.
Because the device is designed to be written in system, all data sheet specifications (including write
and erase operations) hold over the full operating
, temperature range (0-70"C). '
, CHIP ERASE MODE
Should one wish to erase the entire 2816A array at
once, the device offers a chip erase function. When

The No Operation mode differs from Standby Mode
in that active power is drawn by the 2816A in this
'
mode.

WRITE.TIME CHARACTERISTICS
The 2816A write time specification is 9ms (min,) and
15ms (max.). If the write pulse width applied to the
WE input is 9ms, the programmed byte is guaranteed
to be correctly and reliably programmed to any loca.,
tion in the 2816A.
The maximum pulse width to the WE input of 15ms
limits the duration of the pulse width. Exceeding this
specification may overstress'the'E 2PROM cells and
affect long term device reliability. Any write pulse
width between 9ms and 15ms will also guarantee
byte programmil1g :and chip erase over the full temperature range.
Programmed data will be retained by the Intel 2816A
for over 10 years.

5·86

AFN-00865A

2816A

Although the number of read cycles is unlimited, a
characteristic of all E2 PROMs is that the total number of erase/write cycles is not unlimited. The 2816A
has been designed and manufactured to meet applications requiring up to 1 x 10 4 erase/write cycles per
byte. The erase/write cycling characteristic is completely byte independent. Adjacent bytes are not affected during eraseiwrite cycling.

APPLICATIONS
The 2816A E2 PROM is a new and powerful addition
to the Intel non-volatile family. Like other Intel
E 2 PROMs, it offers a high degree of flexibility
through in-circuit alterability while retaining the nonvolatile characteristics of ROM.
Because of these device parameters, the device is
ideal in many applications. Some of the potential
uses are listed below:

On·Chip Write Protection on Vce Power
Up and Power Down

1. Calibration constants storage (continuous
calibration)
An erase/write of a byte in the 2816A is accomplished with input signals CE, WE =VIL. During system (Vcc) power up and power down, this condition
may be present as Vcc ramps up to or down from its
steady state value of 5 volts. To prevent the possibility of an inadvertent byte write during this power
.transition period, an on-chip sensing circuit disables
the internal programming circuit if Vcc falls below 4
volts (VLKO)·

2. Software alterable central stores (dynamic
reconfiguration)
3. Remote communication programming

.4. PC and NC Industrial Applications
5. CRT Terminal configuration and custom graphic
and font sets

6. Military replacement for core memory and fuselink PROMs

7. Point of sale terminals

VPP OPTION

8. Remote alterable look-up tables
Although the Intel® 2816A requires .only 5 volts for
programming, it was designed to be totally upward
compatible with the Intel 2816. No hardware changes
are required when substituting a 2816A into a 2816
socket. Shaping of the Vpp programming pulse is
also not required with the 2816A. Table 2 lists the Vpp
Option Modes.
. '

9. Printer communications, controllers
10. Remote data or error logging
11. Replacing CMOS RAM and battery backup
12. Remote firmware update of program code

AVAILABLE LITERATURE

Table 2. VPP Option Modes

To give the system designer an opportunity to more
thoroughly understand the device attributes and
uses, a library of E2 pROM information is available
in the Memory Component Handbook. Some of the
E2 PROM application information included is listed
below.
AR 119 -

16-K EE-PROM Relies On Tunneling for
Byte-Erasable Program Storage

. AP 100 -

Reliability Aspects of a Floating Gate
E2 PROM

5·87
AFN-Q0865A

intJ

2816A

ABSOLUTE MAXIMUM RATINGS*

·NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
Indicated in the operational sections of this specification
/s not implied. Exposure to absolute maximum rating conditions for extended periods '!'ayaffect device reliability.

Temperature Under Bias ...... ~ 10·C to + 80·C
Storage Temperature ........ - 65·C to + 100·C
All Input or Output Voltages with
Respect to Ground ............ + 6V to - 0.3V
Maximum Duration of Erase/Write Cycle ... 20ms
VOE with Respect to Ground. . . .. + 17V to - 0.1 V

D.C. AND A.C. OPERATING CONDITIONS DURING READ AND WRITE
Temperature Range

0·C-70·C

Vee Power Supply

5V ± 5%

D.C. CHARACTERISTICS
Limits
Symbol

Input Leakage Current

p.A

ILO

Output Leakage Current

Vee Current (Standby)

leew

Vee Current (Byte Erase/Write)

VIL(D.e.)

Input Low Voltage (D.C.)

-0.1

VIL(A.e.)

Input Low Voltage (A.C.)

OE Voltage for Chip Erase

VLKO

Vee Lockout Level for Data
Protection

A.C_ TESTING INPUT, OUTPUT WAVEFORM

A.C. TEST CONDITIONS
Output Load ......... 1TTL gate and CL = 100pF
Input Rise and Fall Times (10% to 90%) .... 20ns
Input Pulse Levels ............... 0.45V to 2.4V
Input Timing Referen'ce Level ...... 0.8V and 2.0V
Output Timing Reference Level .... 0.8Vand 2.0V

INPUT/OUTPUT

"=X, >
2.0

Notes:
1, This parameter is only sampled and not 100% tested,
2. IU(Max) is less than 10"a when.vIN Is less than 5.25V,

A.C. TESTING: INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC " .. AND O.4SV FOR
A LOGIC "0." TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC ." ..
AND 0 8V FOR A LOGIC "0 "'

5-88

2816A

CAPACITANCE (1)

T A = 25" C, f = 1 MHz

Test Conditions
VIN =OV

A.C. CHARACTERISTICS
READ
Parameter

. Symbol

2816A·2 limits
2816A Limits
2816A·3 Limits
2816A-4 Limit.
Test
Unit• Condition.
Min. Typ.lll Max; Min. Typ.ll1 Max. Min. Typ.ll1 Max. Min. Typ.ll1 Max.

tACC

Address to Output
Delay

n. ee ~ OE ~ Vtl
n. OE ~ V,l

OE High to Output
Float

Output Hold from
Addresses, CE or OE.
Whichever Occurred
First

Address to Write Set-Up Time

150

tcs

CE to Write Set-Up Time

150

tOS[31

Data to Write Set·Up Time

tOH[31

Data Hold Time

twp[41

Write Pulse Width for 2816A

Chip Erase Set-Up Time

Byte Erase/Write Set-Up Time

taoH

Byte Erase/Write Hold Time

tWWR[51

Cycle Delay Time Following Write Cycle

I-'S

= 10V
= 10V

NOTES:
1. This parameter is only sampled and not 100% tested.
2. tOF is measured from the point when CE or DE returns high (whichever occurs first) to the tir:ne w~en the outputs are no longer driven. This parameter
is not 100% tested.
.
3. The data is set up and hold times for chip erase are identical to those specified for byte erase.
4. Adherence to twp specification is important to device reliability.
5: Adherence to tWWA is imp~rtant for device reliability.

intJ

2816A

WAVEFORMS
READ

1..------- - - - - ---"'\1
ADDRESSES VALID

ADDRESSES

1"-_ _ _ _ _ - - - - - _ _ _JI

1'----,-1 - - - - - - - - - ' I

---------'1
ID,[21

---+-IOH~

- - - - - ---,---!nT"
OUTPUT

-----+------+H<

14-----

VALID
OUTPUT

- - - - - -'-----fJ.£U
fAce - - - - .

BYTE ERASE OR WRITE[3]

_ _ _ t w P _ ... twR'"

NOTES:
1. OE. may be delayed up to 150 ns after~lin!l..!Wge of CE without impact on teE for 2816A.
2. tOF is measured from the point when CE or DE returns high (whichever occurs first) to the time when the outputs are no longer driven.
This parameter is not 100% tested.
3. Prior to a data write, an erase operation must be performed. For a byte erase, data in ::; VrH'

5-90

2816A

WAVEFORMS (Continued)
CHIP ERASE 11 [

CE-------~

les

t - - - - l w P - - -..

NOTES:
1. In the chip erase mode DIN:::;: V 1H . '.
2. Timing reference for DE during Chip Erase 'is 90% of VOE'

5-91

AFN-00865A

2816A

WAVEFORMS (Continued)

CONSECUTIVE BYTE ERASE OR WRITE CYCLES

_ _ _ _" ' r o - - - - - - - - - 1 W P - - - - - - . , . - - l

Iwp _ _

xxxxxxx
DONTCARE

BYTE WRITE FOLLOWED BY READ CYCLE
IWWR[1]

INPUT/OU~:~~

-----{

DATA IN
VALID

~---------------------~

DATA OUT
VALID

NOTE:
1. Adherence to tWWR is important for device reI/ability.

AFN-00865A

2816A

VPP OPTION SPECIFICATIONSI11

ABSOLUTE MAXIMUM RATINGS

"NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the .
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

Vpp Supply Voltage with Respect to Ground
During Write/Erase .................. +22.5V to -0.1V
Maximum Duration ofVpp Supply at 22V
During Erase/Write Inhibit .................... 24 Hrs.
Maximum Duration of Vpp Supply at 22V
During WritelErase ........................... 20 ms

D.C. CHARACTERISTICS
Limits
Symbol

V pp Cu rrent (Byte Erase/Write)

Vpp

Write/Erase Voltage

Ipp(C)

Vpp Current (Chip Erase)

Test Conditions

Max.

/La

Cl: =VIL. Vpp =4
to 6
CE =VIL

CAPACITANCE[2] TA =25"C. f =1 MHz
Parameter

A.C. CHARACTERISTICS
Limits
Symbol

NOTES:
1. Only specifications unique to Vpp option operation are shown. All other specifications under 5 volt only operation apply to Vpp option operation
as well, except where noted.
2. This parameter is only sampled and not 100% tested.

5-93

AFN-00865A

. 2816A

BYTE ERASE OR WRITE WITH VPP OPTION[1,2]

« -51
Microcomputer and the iAPX 86/88,1861188, and
286 microprocessor families. The 2817A requires
no interface circuitry. Figure 4 shows an example of. the 2817A used. as program storage
memory in an 8031 single-chip microcomputer
system. The 8031 program code is modified or
u~graded remotely without having to remove the
E PROM from the system.

Application Note AP-158 shows a complete
schematic diagram of an 8088-based system
design example. Inclu'ded in AP-158 are various
hardware design options for different applications and a number of 8088 code software
routines for remote downloading applications,

The Intel 8282.8-bit latch shown in Figure 4 is us~
ed to de-multiplex addresses AO-A7. (The latch is

INTERFACE OPTiONS , - - - - - - - - - - - ,
FOR THE
RDY/B",SY SIGNAL
1
8259A
PROGRAMMABLE
INTERRUPT.
CONTROLLER'

Figure 5_ 2817A18088 Interface Example

5-98

E2PROM
EPROM OR E2PROM
RAM

inter

2817A

sequence and location, can be stored in the 2817 A.
Additional applications include accumulated totals
for dollars, energy consumption, volume and even
the logging of service performed on computer
boards or systems for documentation purposes.

and for using the 8259A Programmable Interrupt
Controller and the 8251A Programmable Communications Interface.
Interfacing to the Intel 8088 is similarto the 8031
interface. The difference lies in the use of the
8259A (Programmable Interrupt Controller). The
Ready line can be connected to any of the interrupt request pins in order to interrupt the processor. (See Figure 5). Alternatively, it can be
polled through an I/O port or connected through
an inverter to TEST on the Intel 8088.

USing ROY/BUSY
The ROY/BUSY pin is an open-drain output which
. allows two or more ROY/BO'SY signals to be ORtied together. To calculate the value of the pullup resistor for the ROY/BUSY output, the following formula can be used:
4.6V
R _
p - 2.1ma - IlL.
where IlL = the total VIL input current
. of all devices connected to the ROY/BUSY
line.

The Intel 2817A is cost effective for lower density
E2PROM applications and can therefore be used to
provide a lower system cost to the user. The 2817 A
user will find that tangible cost savings per system
include: board space and component reductions,
reduced assembly costs, savings in inventory
costs, handling costs and Quality Assurance.
System designers will find the 2817A reduces
design time by a sizeable factor due to the integration of timing, logic and latching .
The 2817Awill also open up new applications in
environments where flexible parameters/data
storage could not be implemented before. Applications with board space constraints are ideal
for the 2817 A due to the on-chip integration of all
functions required.
In Application Note AP-158 a c.omprehensive
discussion of four. major application areas for
E2 PROMs is given:
.

A typical pull-up resistor value for the ROY/BUSY
output is 3.0K ohms, assuming that the input
sink current (IlL,) of the input(s) being driven is
less than 0.5 mao

1. Remote Firmware Oownloading
.
2. System Re-Configuration (system parameter
storage)
.
3. Maintenance Logging
4. Electronic Message Storage

Applications
The Intel 2817A is ideal for non-volatile memory.requirenients in applications requiring storage of
user defined functions, calibration constants, configuration parameters and accumulated totals. Soft
key configuration in a character-oriented or
graphics terminal is an example where user defined
functions, such as protocol, color, screen attributes and character fonts can be keyed in by the
user. Calibration constants can be stored in the
2817A with a smart interface· for a robot's axis of
movement. Movement constants; compensation
algorithms and learned axis characteristics would
be included. In programmable controllers and data
loggers, configuration parameters for polling time,

Write Time Characteristics
The 2817 A's internal write cycle contains an
automatic erase feature. Furthermore, the 281iA.
automatically determines through its self-timer
when a byte has been written and signals the
completion via the Ready/Busy signal. The
Ready/Busy signal is. an open-drain output. The
2817 A's internal cycle consists of an automatic
10 ms erase followed by a write. The total cycle
is the time that Ready is held lowby the device.
rhe 2817A maximum specification is 20 ms for a
combined Erase/Write cycle. The 2817A-1 is
ideal for users desiring a faster erase/write cycle
time. The total cycle time for this part is 10msec.

5-99

2817A'

ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias ..... - 10·C to + 80·C
Storag,eTemperature ....... -65·Cto + 100·C
All Input or Output Voltages with
Respect to Ground ........... + 6V to - .3V

nent damage to the device. This is a stress rating
only and functional operation of the device at
these orarly other conditions above those/no
dicated in the operational sections of this
specification is riot implied. Exposure toab~
solute maximum rating conditions for extended
periods may affect device reliability.

"NOTICE: Stresses above those listed under
"Absolute Maximum Ratings" may cause perma·

D.C. AND A.C. OPERATING CONDITIONS DURING READ AND WRITE
Temperature Range

0·C·70·C

Vee Power Supply

5V ± 5%

D.C. CHARACTERISTICS
Parameter

I nput Leakage Current

p.A

Vln = Vee Max. (2)

ILO

Output Leakage Current

Vee Current (Standby)

rnA

CE = VIH, Vee = Vee Max.

Input Low Voltage (A.C.)

Vee Level for Write
Lockout

NOTE:
1. Thil'i parameter only sampled and not 100% tested.
2. IIL(max) is less than'10!,a when VIN is less than 5.25V.

WE= 1.I ,CE= VIL

2817A

CAPACITANCE (TA = 25°C, f = 1 MHz)
Parameter

A.C. TESTING INPUT, OUTPUT WAVEFORM

A.C. TEST CONDITIONS

INPUT/OUTPUT

Output Load ......... 1 TTL gate. + CL = 100pF
Input Rise and Fall Times(10% to 90%) .... 20ns
. Input Pulse Levels .............. 0.45V to 2.4V
Input Timing Reference Level .... 0.8V and 2.0V
Output Timing Reference Level ... 0.8V and 2.0V

A.C. TESTING: INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC 1" AND Q.45V FDA
A LOGIC 0.-- TIMING MEASUREMENTS ARE MADE AT 2.0V FOR A LOGIC ~
AND O.BV FDA A LOGIC 0

A.C.CHARACTERISTICS
READ
; Symbol

Parameter

2817A·1 Limits 2817A Limits 2817A·3 Limits 2817A·4 Limits
2817A·2
Units
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.

Test
Conditions

Address to Out·
. put delay.

OE High to
Output not
Driven

Output Hold..lr.om
Addresses, CE or
OE Whichever
Occurred First

CE=OE=V 1L

NOTES:
1. This parameter only sampled and not 100% tested.
2. tDF is measured from the pOint when CE or OE returns high (whichever occurs first) to the time when
the outputs are no longer driven. This parameter is not 100% tested.
'

5·101

inter··

2817A

A.C. CHARACTERISTICS (Cont.)
WRITE
2817A-1
. Symbol

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
tAS

Address to write
set-up
.., '. time

,20

tcs

CE to write
set'up time

Bytes Write Cycle
Time

Number of Writes
per byte

NOTE:
1.. tOF is measured from the point when CE ~ or OE returns high (whichever occurs first) to· the ,time when
the outputs are no longer driven. This parameter is not 100% tested"

IL ... --1
t WR - - - - "

AVAILABLE LITERATURE
The Intel E2PROM family of devices, the 2816A
and 2817A, is supported by many Application
Notes. Topics covered range from Intel E2PROM
Technology and Reliability to Design considerations and Applications support for Designers implementing large arrays of E2PROMs.

These notes and more are available in the
Memory Components Handbook (Order No.
210830) or the Intel Literature Department, 3065
Bowers Ave., Santa Clara, CA 95051. To obtain
this book contact your local Field Sales office.
Your Field Applications Engineer is available to
discuss all aspects of the Intel E2 product line
with you.

5-103

Bubble Memory

intJ

APRIMERON
MAGNETIC BUBBLE MEMORY

Magnetic bubble memory is a solid-state technology with high reliability, ruggedness,small size, light weight, and limited
power dissipation. It has applications in telecommunications, data acquisition, industrial control, terminals, and small business computers. Yet many potential users remain unsure of the nature of a bubble memory. This primer is intended to
introduce these users to the technology.

What a Magnetic Bubble Memory Is
A magnetic bubble memory stores data in the form of cylindrical magnetic domains in a thin film of magnetic material. The
presence of a domain (a bubble) is interpreted asa binary I, and absence of a domain is a O. Bubbles are created from electrical
signals by a bubble generator withinthe memory, and reconverted to electrical signals by an internal detector. Externally the
memory is TTL-compatible.
An external rotating magnetic field propels these cylindrical domain bubbles through the film: Metallic patterns or chevrons
deposited on the film steer the domains in the desired directions. Transfer rates, once started, are in the tens of thousands of
bits per second, but because the data circulates pasta pickUp point at which it becomes available to the outside world, there is
a latency averaging tens of milliseconds before data transfer can begin. In these respects, magnetic bubble memories are serial
high-density storage devices like electromechanical disk memories. However, in a disk,the stored bits are stationary on a
moving medium, whereas in the magnetic bubble memory the medium is stationary aiId the bits move.

Advantages of Magnetic Bubble Memol'ies
The principal advantage of magnetic bubble memories are their non-volatility-that is, if power fails, the stored data is
retained. Products incorporating bubble memories therefore do not require battery backups. Magnetic bubble memories
share this feature with read only memories (ROMs), erasable PROMs (EPROMS), and electrically erasable PROMs
(E2PROMS);However, unlike any of these technologies, magnetic bubble memories can have data written into them at any
time, at speeds comparable to those at which data is read. Furthermore, unlike disk memories, bubble memories are quiet
and very reliable, because they have no moving parts. They are cOrripact, and they dissipate very little power. Their support
circuits are compatible with microprocessor systems. With a million or more bits per device, a bubble memory can store 16 to
64 times the 'amount of data of alternative semiconductor memories, Providing very high storage capability in a compact'
space. Bubble memory has a wide variety of applications, some of which are listed in Table I.
.

6-1

Table 1. Bubble Memory Applications
Numerical control

Telecommunications terminals

Avionics

Point-of-sale terminals

Gasoline pumps

Private branch telephone exchanges

Personal computers

Word processors

Office equipment

Flight-line test equipment

Automatic test equipment

Data encryption

How Bubbles are Formed
Magnetic domains are found in all kinds of magnetic materials-iron bars, the coating on magnetic tape, ferrite toroids (the
most common form of computer memory in the 1960s). Each domain is a group of atoms with parallel magnetic orientations.
When the material in bulk is unmagnetized, the domains are oriented at random in three dimensions. When the material is
magnetically saturated, most of the domains have the same orientation. Magnetization to a level less than saturation orients
some of the domains to a common direction, but leaves many of them randomly oriented. When a domain orientation
changes, usually by imposing an external magnetic field, the domain itself does not physically move, but boundaries between
domains that have different orientations move or disappear altogether.

In an extremely thin film, less than 0.00 I inch thick, the domain orientations may be constrained to two dimensions. In some
kinds of material (orthoferrites and garnets), with proper crystallographic orientation, the domain orientations are always
perpendicular to the film. When these materials are not in a magnetic field, some domains are oriented upward and some
downward (north magnetic poles of some domains are on top ofthe film, and those of other domains are on the bottom). In
these materials, the magnetic domains tend to be long and snakelike in the absence of an external field (Figure I). When a
weak magnetic field is applied perpendicular to the film, the domains that are oriented opposite to the applied field become
substantially narrower. As the applied field, called a bias field, is made stronger, the length continues to decrease, until it
becomes approximately the same as the width. Each domain is now cylindrical, magnetized oppositely to the applied field,
and immersed in a much larger domain that is magnetized in the same direction as the field.

_ - - -~ =i

-',

,
,

-- .........- --- --- -NO EXTERNAL
MAGNETIC FIELD

Figure 1.

SMALL EXTERNAL
MAGNETIC FIELD

LARGER EXTERNAL
MAGNETIC FIELD

Magnetic Domains in Thin Film Under Increasing Magnetic Bias Field.

6-2

These"small domains are the bubbles, generally less than 3 micrometers (1/ 10,000 inch) in diameter (Figure 2). When they
are viewed from above, only the round shape is apparent, giving the domains the appearance of bubbles. Ifthe bias field were to
be made still stronger, all the bubbles would shrink and then disappear altogether; the entire film would be magnetized in the
same direction as the bias field. The effect is reversible':"'that is, if the bias is removed, the domains return to a snakelike form.

Magnetic Bubbles In a Thin Film.

Why a Bubble Moves
Magnetic bubbles will move if they are in a magnetic field gradient. For instance, it will move from a region of lesser
magnetic field strength to a region of greater strength. This is similar to the way a nail is pulled to the end ofa bar magnet
when it gets close the magnet.
In a bubble memory a magnetic film pattern is overlaid on the layer of bubbles. When this layer is magnetized it pulls the
bubbles to the point~ of greatest field strength (or poles) as in Figure 3. The bubbles could then be moved if the pattern
elements were moved.
A more easily controlled magnetic field is generated by two coils wrapped around the bubble layer and magnetic film pattern. With appropriate specification of the current in tw~ coils positioned at right angles, the direction of the poles on the
stationary elements can be changed in a controlled manner.

t~~. ~~~~
1L1\~ /~(~
Figure 3.

Bubble Propagation Under Asymmetric Chevrons
6-3

Photo 1. Asymmetric Chevrons Deposited on a Thin Film

Why Magnetic Bubbles are Non-Volatile
In a magnetic bubble memory system, the bias field in which the bubbles exist is generated by a pair of permanent magnets. The substrate bearing the thin film and its bubbles is mounted between these magnets and is therefore continuously
subject to the bias field.

The rotating field that propels the bubbles through the film is generated by currents in two coils wrapped around the substrate at right angles to each other. These currents are generated by electronic circuits that are part of the magnetic bubble
memory system. No mechanical motion is involved.
If power fails, the circuits stop operating, the rotating field disappears, and the bubbles stop moving. But the bias field,
generated by the permanent magnet, is not affected. Therefore the bubbles and the data that they represent are maintained
in the film. When power is restored the data is again accesible.

6-4

BUBBLE MEMORY MANUFACTURING TECHNOLOGY
Bubble memories are produced in a process that resembles semiconductor manufacturing in many ways (Figure 4).
Manufacturing begins witl). a nonmagnetic garnet wafer on which a magnetic film is deposited, using conventional tech~iques. An ion implantation process alters the magnetization of the top surface of the film, discouraging the formation of
abnormal bubbles with undesirable dynamic properties. Then nonmagnetic conductors, bubble-steering patterns of
magnetic metal, insulation, passivation; and bonding pads are deposited in much tile same way as successive layers on
semiconductor integrated circuits. Patterns in each layer are defined photolithographically,just as with semiconductors.
Magnetic bubble technology differs from semiconductor technology in the materials used and in the complexity of the
process. Semiconductor circuits use eight more layers of silicon doped with various materials that affect its electrical
characteristics, compared to about three layers of essentially pure metallic and insulating material in bubble technology.
These materials are chosen for their magnetic rather than their electrical properties.

Figure 4. Magnetic Bubble Chip Cross Secllon

Bubble Memory Functional Description
The Intel 71 I0 magnetic bubble memory unit contains the bubble chip, the coils that generate the rotating field, two permanent magnets for the bias field, and a magnetic shield that preventsdisturbances by external fields and forms a return
path for the bias field around the. bubble chip (Figure 5).

6-5

Figure 5.

PERMANENT
MAGNET

Magnetic Bubble Unit Assembly-Exploded View

Bubble lIIIemory Architecture
Data is stored in the bubble memory unit with a block-replicate architecture (Figure 6). This architecture consists of a
number' of endless storage loops around which corresponding bits of successive pages continuously circulate, and two
tracks, designated input and output, through which the controller writes and reads data in the storage loops. Exchange or
replication of data between the tracks and the loops occurs in all loops simultaneously-the key idea in this architecture.

Block-Replicate Architecture

6-6

intel'
WRITING DATA INTO THE BUBBLE MEMORY

Seed Bubble
The seed bubble, at the beginning of the input track, is generated by an electric current pulse in a hairpin-shaped loop of conductive material. The pulse is strong enough to reverse the bias field locally and thus allow a bubble domain to be created.
Once having been created, the seed bubble remains in existence as long as the external bias field is maintained.
The seed circulates under a permalloy patch, driven by the rotating field that propagates bubbles elsewhere in the memory.
This bubble is constrained to a kidney shape by interaction of the bias and rotating field with the metal patch (Figure 7).
The seed is split in two by a c.urrent pulse in the hairpin-shaped conductor. One of them remains under the patch as the seed,
quickly regaining its original size; the other one, driven by the rotating field, is transferred to the input track section of the
chip. The current.pulse that splits the seed is generated to store a binary I in the memory; to store a 0, the pulse is omitted, and
no bubble is generated.
PERMALLOY
PATCH

BUBBLE
SPLIT SEED
DIRECTION
OF CURRENT
PULSE
AL-CU
CONDUCTOR

INPUT
TRACK

Figure 7.

Seed Bubble and Bubble Generation

A seed bubble is maintained at one end of the input track. Bubbles corresponding to binary I's in the input word are split
from the seed and propagate along the input track. When the input track contains exactly one page (64 bytes) then the bubbles
exchange places with old bubbles previously circulating in the loops. This is accomplished by an operation called swapping.
Thereafter the new bubbles circulate, while the old bubbles now in the track propagate to the end and are destroyed.

Swapping
Transfer of datafrom the input track toa storage loop involves a swap, bringing the old data onto the input track fordestruction at the end of the line, while the new data takes its place in the loop. This is done when a current pulse in an associated conductor under the chevrons causes a bubble to jump from the input track to the storage loop and vice versa. The swap pulse is
essentially rectangular, preserving the bubble without cutting it in two.

Swapping and Replication Configuration in Bubble Memory

READING DATA STORED IN THE BUBBLE MEMORY
To read the stored data, the circulating bubbles are replicated, one bubble or one unoccupied bubble sitefromeach loop, onto
. the output track, after which they propagate to a bubble detector at its far end. After detection, these output bubbles are also'
destroyed. Meanwhile, the data in the loops continues to circulate, permitting a particular page to be read ()ut repeatedly
without regeneration, and protecting the stored data if power fails.

Replication
Datais transferred from the storage loop to the output track by replication, continuing to circulate in the loop after having
been read out.
..
For replication, the bubble is propagated under a large element where it is stretched out. As it passes under a hairpin shaped
conductor loop it is cut by a current pulse just as in bubble generation.
The replicating current pulse waveshape has a high, narrow leading spike for cutting the original bubble in two, anda lower and
wider trailing portion during which the new bubble moves under the output track. The entire pulse lasts about one-quarter of a
cycle of the rotating field. In this manner the data in the storage loops is replicated onto the output track, and yet retained in the
storage loops in case of a sudden power failure.
Near the end of the output track is a bubble detector-essentially a magnetoresistive bridge formed by interconnecting the
permalloy chevrons to make a continuous electrical path of maximum lengtIi (Figure 9). As bubbles pass under the bridge, the
resistance changes slightly, modulating the currents through the bridge and creating an output voltage of several millivolts.
Bubbles are stretched at right angles to the direction of propagation by adding parallel rows of chevrons; these stretched bubbles
generate larger output signals at the detector. Beyond the detector, the output track runs the bubbles into the guard rail and
destroys them.

Figure 9. Bubble Detection

Redundancy
The Intel magnetic bubble memory unit physically stores data in 320storage loops, with capacities of 4,096 bits each. Of the
.320 loops, 272 are actually used (active) and 48 are spares (inactive); the boot loop records which loops are used.

Boot Loop
Some ofthe loops of an individual memory are set aside as spares. The decision as to which loops are to be used (active) and
which are not to be used (inactive) is made after the memory unit has been assembled and is undergoing tests at the factory.
The outcome of this decisiori is stored in an extra loop included in each memory chip, in the form of a 12 bit code for each
"active" and "inactive" loop.
Whenever power is turned on in the memory system, the system must be initialized before it can be used. ~art of the initialization process includes reading the contents of this extra loop, called the boot loop, and placing this information in a bootloop
register in the formatter/ sense amplifier. From then on, as long as power is on, this register identifies the "active" loops for
both reading and writing;"inactive"loops areignored. The formatter does not attempt to store data in "inactive "loops, and
the sense amplifier ignores any data that appears from these loops.

Data Storage-Extemal Appearance
Data is stored logically as 2,048 pages of 512 data bits each. 256 data bits plus 14 error-correction check bits and 2 unused bits
are stored in ea.ch half of the bubble chip. If automatic error correction is not used, these 16 bits are available for data storage.

Error Correction
Error detection and correction can be performed in the formatter / sense amplifier, which includes a 14-bit cyclic redundancy
code that corrects a single burst error of up to five bits in each 270-bit block including the code itself. These code bits are
appended to the end of each 256-bit data block when writing into the cell, and checked when the block is read. The error correction feature can be used or not at the user's discretion, by properly setting a register in the bubble memory controller chip.
If it is not used, the loops occupied by the code bits become available for additional data.

6-9

Access Time and Data Rate '
Bubbles circulate at a rate of 50 kilohertz (the rotating field makes 50,000 complete revolutions per second). Average access
time to the first bit of the first page i~ about 41 milliseconds-half the length of time required for a bubble to make one complete circuit of the loop, plus the time to shift a bubble along the length of thr. output track.
The 320 active and spare loops are actually in four "quads" of 80 loops each (Figure 10). This arrangement shortens the
input and output tracks and thus reduces the read and write cycle times. The quads are separately addressable in pairs; in each
pair the quads store odd-numbered and even-numbered bits of a word respectively. There are four seed bubbles and four
input tracks, and four output tracks. The four output tracks share two detector bridges in such a way that there can never be
bubbles from two tracks in a single detector simultaneously. By'thismeans the four streams of output bubbles are interleaved
into two bit streams that are stored in two registers in the senseamplifier. The data in these registers is interleaved again into a
single stream transmitted serially to the controller.

~~~---------rh~
INPUT TRACK (EVEN QUAD)

INPUT TRACK (ODD QUAD)

Figure 10.

Organization of Bubble Memory (One-Half Chip)

SPECIFIC STRUCTURES OF A MAGNETIC BUBBLE MEMORY
A magnetic bubble memory system consists of a controller arid up to eight I-megabit magnetic bubble subsystems. A m'inimum system has a controller and one subsystem. The subsystem comprises one magnetic bubble unit in which the data is
actually stored, and the peripheral units listed in Table 2 and diagrammed in Figure II. These circuits are described later
in this primer.

6-10

Table 2. Components of Intel Bubble Memory System

CONTROLLER

SUBSYSTEM
Memory

7220 Bubble Memory Controller
(for I to 8 subsystems)

7110 Magnetic Bubble Unit
Peripheral Units
7242 Formatter! Sense Amplifier
7230 Current Pulse Generator
7250 Coil Predriver
7254 Drive Transistor Assembly
(2 required per subsystem)

BUBBLE
MEMORY
CONTROLLER
(BMe)

TO
ADDITIONAL

BPK70's

- Figure 11.

Minimum Magnetic Bubble Memory System, Shaded Portion is Bubble Subsystem

SUPPORT CHIPS
Five semiconductor integrated circuits are necessary to support each bubble chip. These components are described in some
detail in the following paragraphs. In addition, each bubble memory system requires a controller, a s~parate integrated circuit
described later.

FormaHer/Sense Amplifier (FSA)
Serial data to be stored in or read from the bubble memory passes through the FSA. The F~A keeps track of which loops in
the bubble memory are spares, executes the error correction coding and decoding if it is implemented, and shifts data to the
bubble memory input tracks or from the output tracks, amplifying the output si~nals from the memory.

6-11

inter
The FSA has a chip-select input, which is normally grounded (permanently enabled). However, each FSA drives the chipselect input of other circuits associated with the same bubble chip, so they are all enabled at the proper time.

Current Pulse Generator (CPG)
All signals except those that control the rotating field originate in the CPG. This device is the source of a current pulse that
cuts a new bubble from the seed bubble whenever the FSA has a binary I to be stored. Later, when this bubble reaches the
loop in which it is to reside, the CPG issues the signal that swaps it with the bubble or non-bubble previously stored in that
location of the loop. When data is to be read, the bubble is replicated on the output track by still another signal from the CPG.

Coil Preclriver (CPO)
Four digital signals (positive and negative versions of both X and Y waveforms) are sent to the CPD from the controller with
appropriate durations and phases to control the rotating field that moves the bubbles in the memory. The CPD combines and
inverts these to form eight pulsed outputs that are amplified in a separate transistor package to drive the coils surrounding the
bubble chip with a triangular current waveform.

Photo 2. The Minimum Magnetic Bubble Memory System
Including Controller

CONTROLLER
The bubble memory controller is the interface between the memory system and the equipment it serves. It converts serial data
to parallel and parallel data to serial, and generates all timing signals required by the other support circuits in the bubble
memory system. It can controf up to eight bubble subsystems, for a total of a megabyte of memory.
Internal storage on the controller includes a first-in-first-out buffer with a capacity of 40 bytes. This buffer stores data to be
sent serially to the FSA or just received from the FSA on one side, and data to or from the parallel bus served by the bubble
memory on the other. It also serves as a speed matching device between the user at the parallel bus and the FSA which must
transfer data to and from the bubble device at exactly the rotating field ratio in each channnel.

6-12

intJ
GLOSSARY
Bias field-a magnetic field perpendicular to a magnetic thin film that maintains conditions necessary to support formation
of magnetic bubbles in the film.
Boot loop-in a, magnetic bubble memory with serial! p~rallel! serial architecture and redundant loops, a special loop containing information that identifies which loops are active and which are inactive, as deterinined by factory test. This loop also
contains the information necessary to synchronize the bubble memory page locations with the controller after power up.
Bubble, magnetic-a cylindrical magnetic domain in a thin film of orthoferrite or garnet. When viewed from above', the cylindrical sqape appears spherical, hence the name "bubble." A bubble represents a binary 1 in most magnetic bubble memories.
Chevron-one of many possible shapes for a magnetic pattern deposited on a thin film to steer bubbles in a desired direction.
Asymmetric chevrons are used in Intel memories.
Detector---:-a means of distinguishing bubbles from non-bubbles (I s from Os) when a word is read from the bu~ble memory.
Domain, magnetic-a small region of a ferromagnetic substance that contains many similady oriented atoms, so that the
region as a whole is magnetized in that direction.
E2PROM-an acronym for electrica,lly erasable programmable read-only memory, which is a memory component that,
though nominally read-only, can accept changes to any work stored in it by electrical means, but at substantially slower speed
than that at which stored words are read.
EPROM~an acronym for erasable programmable read-only memory, which is a memory component that, though nominally read-only, can be completely erased, usually by exposure to ultravioletlight, and then reloaded with new information, but
at substantially slower speed than that at which stored words are read.

Ferrite-any of several compounds of iron, oxygen, and another metal, with magnetic properties that are useful in certain
microwave applications and in computer memories.
Field, magnetic-a region of space in which a magnetic force exists and can be measured.
Gamet-a naturally occurring silicate mineral sometimes used in jewelry. Synthetic garnets with the same crystal structure
can be made of oxides of iron and yttrium or one of the rare earths. Gamet is the preferred material for the thin magnetic film
ina bubble memory. ,
Input track-a series of magnetic metal patterns that control the movement pf bubbles in a thin film, and thereby lead them
from a bubble generator toward one or more storage patterns.
Ion implantation-a process involving accelerators, similar to the machines used by nuclear physicists, for depositing dopants
on and just below the surface of an electronic component; used to aiter the physical properties of the material.
I

Latency-a delay between a request to read or write data in a memory and the actual beginning of the operation, imposed by
a requirement for the address to move physically (but not necessarily mechanically) to a point ~here the data transfer can
take place.
Magnetization vector-an expression of the magnitude and direction of a magnetic field at a point in space.
Magnetoresistance-a change in electrical resistance due to the presence of a magnetic field.

6-13

inter
Major loop-in a magnetic bubble memory, an endless loop containing a bubbie generator, a bubble detector,and/ or a
bubble anirihilator, through which data is read or written, and which transfers bubbles to or from one or more minor loops
(q. v.) iii which they are stored. 'In some designs the major loop is not endless, and all bubbles not transferred (jut of it collapse
when they reach the end. In these cases the major loop becomes an input or output track (q.v.).
Minor loop-in a magnetic bubbie memory, an endless loop in which bubbles are stored, having been transferred into it fro~
a major loop or input tfiick (q.v.) and accessible by transfer into a major loop 'or output track (q.v.). '
Non-Volatility-a property ofsome memory technologies that retains the integrity of stored data when poweris turned off.
Orll1oferrite-:-oneof several oxides of iron and either yttrium or a rare earth. The molecular structure is simpler than that of
garnet (q. v.). Orthoferrites were the first materials used for the thin magnetic film in experimental bubble memories, but have
yielded' to garnets, which have more desirable properties-notably ease of preparation as thin films with the necessary
magnetic characteristics.
Output track~a series of magneiicmetal patterns that control the movement of bubbles in a thin film, and thereby lead them
from one or more storage patterns toward a bubble detector.
Permalloy-an easiiy magnetized and demagnetized alloy of nickel and iron.
PROM'-aeronym for programmable read-only memory-a read-only memory whose content is loaded by the user after
delivery, as opposed to read-only memories whose content is fixed during mamifacture. Once loaded, the data in a PROM is
not alterable.
Pseudo-random a~cess-a property of some.meinory technologies in which the time of access to blocks of stored data is
'largely (but not necessarily entirely) independent of the position of the block in the storage medium; but in which the time of
access to bits, words or other entities depends on the position 'of that entity within the block.
Random aCceSs--a property ofsome memory technologies in which the time of access to any storoo bit, word, or other entity
is wholly independent of that entity's position in the storage medium.
Saturation-a state of magnetization of a material by a field such that, if the field is increased, the magnetization of the material does not increase and the magnetic flux density increases in proportion to the field (having increased much more rapidly in
,
.
"
. .
weaker fi~lds).·
Seed-a permanent bubble in a magnetic bubble memory, from which other bubbles are cut to represent stored bmary Is.
Serial access-c-a property of some:niemory technologies in which the time of access t6 any stoied bit, word, or other' entity
'
depends strongly on that entity's position in the storage medium:
Thin film-any film of material deposited ona suitable substrate to take advantage of the ~terial's speCial properties when
dispersed as a film. Thickness ranges usually from about 10-9 to 10-6 meter, and ocCasionally to'IO-5meter 01' more, as in
bubble memories.
'
T-I bar-one of several possible shapes for a magnetic pattern deposited lln a thin film to steer bubbles in a desired direction,
consisting of shapes like the letterT and the letter I alternately along a track. This pattern was used extensively in early bubble
memory designs, but is no long~r generally employed.'
.

ORDER NUMBER: 210367-002

6-15

Ap·119
INTRODUCTION
To date, a major'obst~cle in the implementation of
bubble memories in systems has been the inherently complex control requirements imposed
by the bubble memory devices themselves. With
the advent of Intel's BPK 72 bubble memory prototype kit, a design engineer can immediately
realize the benefits of non-volatility, form factor,
density and reliability without the complex control
concerns. This application note provides
additional background on the operating

characteristics of the BPK 72 and is intended to
further ease the design effort required in the im.
plementation of bubble memory systems.

OVERVIEW
This application note provides an example of Bub·
ble Memory system implementation using the
BPK 72 and an Intel 8086 microprocessor. Before
looking at this example, some explanation is
necessary as to how this implementation was attained and how a user can take advantage of the
principles involved.

·6·16

Ap·119
As an introduction, the basic architecture of the
BPK 72 is reviewed followed by an explanation of
the operating characteristics of the BPK 72 kit as
a whole and of the 7220 Bubble Memory Con·
troller. Once the building blocks are in place, a
detailed account of the implementation of a bubble memory kit is offered. The final section, which
involves the actual implementation of the BPK 72
and an SDK-86, completes the application note.

BUBBLE SYSTEM OVERVIEW
A block diagram of the Intel Magnetics 128K-byte
system is shown in Figure 1. The support circuitry
used with one 7110 magnetic bubble memory
(MBM) in the BPK 72 kit consists of the following
integrated citcuit components: one 7250 Coil
Predriver, two 7254 Quad VMOS Drive Transistor
packs, one 7230 Current Pulse Generator, and one
7242 Formatter/Sense Amplifier. The 7220 Bubble
Memory Controller (BMC) completes the basic
system.

The 7250 and the two 7254s supply the drive currents for the in-plane. rotating magnetic field (X
and Y coils) that move the magnetic bubbles
within the MBM. The 7230 supplies the current
pulses that generate the magnetic bubbles and
transfer the bubbles into and out of the storage
loops of the MBM.
The 7242 accepts signals from the bubble detectors in the MBM dtlring read operations, buffers
the signals and performs data formatting tasks
that include the transparent handling of boot loop
information. During write operations, the 7242
enables the;current pulses of the 7230 that cause
the bubbles to be generated in the 7110 MBM.
Automatic error detection and correction of the
data can be performed by the 7242.
The 7220 provides the user interface, performs
serial-to-parallel and parallel-to-serial data conversions, and generates all timing signals necessary
for the proper operation of the MBM support circuitry.

8086 BUS

7220
BUBBLE MEMORY CONTROLLER

J,.
DRIVE
TRANSISTORS
FORMATIERI
SENSE AMP

!
7230
CURRENT PULSE
GENERATOR

l
1

Figure 1. Block Diagram of the 128K Byte Magnetic Bubble Memory System
6-17

7250 (CPO)
COIL'
PREDRIVER

....
DRIVE
TRANSISTOR
'VMOS (2·7254)

.....

FORMATTER/SENSE AMP

roo--"

INTEL
MAGNETICS
BUBBLE
MEMORY
7110

7242

'"
..'" II CURRENT
7230 (CPG)
PULSE
GENERATOR

1 MEGABIT BUBBLE STORAGE UNIT

•

1 MEGABIT BUBBLE STORAGE UNIT

1 MEGABIT BUBBLE STORAGE UNIT

.;.

Figure 2. Bubble Memory System Expansion up, to One Megabyte
'Figure ,2 shows how larger systems can ·be builL
from the basic components. A Bubble Storage
Unit consists of one 128K'byte MBM and the five
'support chips shown. The components needed for
one MBM cell are available as the BPK 70 kit.
:Larger systems can be constructed from'the components supplied with one BPK 72 kit (Illihich includes the 7220 controller) and one or more BPK
70 kits. For example, a one megabyte'system can
- be assembled from one BPK 72 kit and seven BPK
70 kits. No additional TTL parts are required when
building multi bubble systems with up to eight
MBML
''

One 7220 is capable of controlling up to eight Bub·
ble Storage Units simultaneously; Larger systems
can be configured with multiple 7220's and additional Bubble Storage Units.

Functional Organization of, the
7110 Bubble Memory
The Intel Magnetics 7110 Bubble Memory utilizes
a "major track/minorloop" architecture. With this
architecture, if a binary 1 is to be written, a "seed
bubble," ~Iways, present in the 7110, is split in
two. One bubble remail'!s at the generator as the
6-18

Ap·119
seed, and the other is propagated down· the input
(major) track. If a 0 is to be written, the seed bub~
ble is not duplicated. The data generated is .sent
down the input track, in serial, until it is aligned
with the "swap" gates at the minor loops of the
device. The. new data is then swapped into the
minor loops in par~lIel at the.same time the old
data is swapped out to the major track.

Table 1. 7110 Loop Operation

To read data from the 7110, data is rotated in the
minor loops until it is positioned at the "replicate"
gates opposite the output track. On receipt of a
replicate signal, the data in the minor loops is
duplicated by splitting the bubbles. The original
data remains in the minor loops, and the duplicate
data is clocked down tne output track where the
detector elements of the bubble memory .operate
to transform the presence or absence of a bubble
into small electrical signals that are converted into digital '1' and '0' signals in the 7242 FSA.
With the 7110, the process of reading data from
the minor loops by si·multaneously splitting all of
the bubbles in a page is known as "block
replicate:' The·advantage of the block replicate architecture is that the data currently'stored in the
minor loops is not compromised during a read
operation; the data to be read never leaves the
minor loops. This architecture can be contrasted
with earlier architectures that required the data to
leave the minor loops, be·· detected and· then
returned to the minor loops. In the event ofa
power failure, bubble systems not utilizing the
block replicate architecture could suffer a loss of
data during a read operation; the data being sensed would not be returned from the major loop to
the minor loops.

abcde

00000
00011
00000
00000
1'1111
00000
00000
·00000
10110·

00011
00000
00000
111.11
00000
00000
00000
10110·
00000

00000
00000
11111
00000
00000
. 00000
10110·
00000
00011

00000
11111
00000
00000
00000
10110'
00000
00011
·00000

The 7110 MBM actually contains 320 minor loops,
of which 272 must be good. The additional 48
loops provide 15% redundancy. This redundancy
factor allows some·of the loops in the 71·10 to be
bad while maintaining a completely functional
one megabit device. A map of the good and bad
loops is placed on the label of the 7110 and is also

~(::===.=LO;OP::272===-4j;:~.. D~:g;~R
~(

With the i110 MBM, there are 2048 positions for
the data within a minor loop. To move the bubbles
in the· MBM, a magnetic field .is induced and
rotated in the plane of the 7110. As the field is
rotated 360 degrees; every bubble is moved ahead
one position, and all of the bubbles· maintain the
same positi()n relativetci one·another~ All of the
bubbles in similar positions in the loops are referredtoas a '~page." .

By way of.illustration,suppose the bubble is made
of five minor loops(a,b,c,d;e) capabl~ of holding
nine pages of data (Table 1). During four 360
degree "rotations" of the in-plaiiemagnetic field,
the nine pages of data shift four positions
(1.1, 1:2, 1~3; 1;4):
.

BUBBLE
GENERATOR

~(,-==~L~OO;P3~==-j;::~

Figure 3. Functional' Organization of the· 7t10

6-19

Ap·119
encoded and placed in the boot loop of the device
as it is tested. This map, the bootloop, consists of
forty bytes of data. Each good loop in the 7110 is
represented bya one, each bad loop by a' zero.
When the, system is initialized, the 7220 BMC
reads the bootloop from the 7110 and decodes it.
The bootloop is then automatically placed in the
bootloop register of the 7242. The bbotloop
register serveS as aworking 'map' of the 7110 for
read arid write OpEm3.tions.
. ,
With the pages of data rotating around tne minor
loops, there must be a mechanism to orient the
device and to assign a starting address toa page.
The mechanism used to identify page zero involves the bootlqop that resides on the 7110. Page
zero (or address zero) is defined as the position of
the 7110 after the bootloop has been read by the
7220 contrpller, Thus, each time the host CPU
sends an~',initialize" command, thebootloop is
readby the 7220, and the 7110.is queued at page
zero, From this point, any desired page, in. the bub·
ble can be obtained by the ,controller.

Data Flow. Within the Bubble Memory .
System
.
To better understa'nd the relationship between the
7110 MBM and its support circuitry, the data flow
within the. bubble system during a read operation
is examined. During the read operation, bubbles
, from the storage loops arereplicated,onto an out:
put' track and then moved to detector within the
MBM. All movements within the MBM occur under
the influence of a rotating magnetic field; the
number of rotations and the rotation timing are
under :the coritrol of the 7220 BMC. The detector
outputs a' ,differential voltage according to
whether a bubble is present or absent in the
detector at any given time. This voltage is fed to
the detector input of the 7242 Formatter/Sense
Amplifier (FSA).·
,

The data path between. ,the 7110 M BMand the
7242 FSA, conSists of two channels (channel A and
channel B) connected to the two halves of· the
MBM. When data is written, the bit stream is divid·
ed with half of the data going to each side of the
MBM. During a read operation, data from each half
of the MBM goes to the corresponding channel of
the FSA. In the, FSA, the sense amplifier. performs
a sample·and-hold function on the detector input
data, and produces a digital.Oor1. The·resulting
data bit is then paired with the corresponding bit
in the FSA bootloop register.
If an incoming data bit is found to be from a good
loop (a corresponding '~1" in the FSA bootloop
register), it is stqred in the FSA FIFO; otherwise, it
is ignored. This process continues until both FSA

FIFOs (channels A and B) are filled with 256 bits.
Error 'detection and correction, if enabled by the
user, is applied to each block of 256 bits at this
point. If erro(correction is not enabled, 272 bits of
data can 'be buffered in each FIFO.
As data leaves the 7242 FSA, the bit patterns buffered in each ofthe FSA FIFOs is interhilaved and
sent to the 7220' BMC in the form of aser'ial bit
stream via a one·line bidirectional data bus (010
line). In the 7220 BMC, the data undergoes a serialto-parallel conversion and is assembled into bytes
that are buffered in the 7220 FIFO. It is from this
FIFO that the data is written onto the user inter·
face.

COMMUNICATING WITH THE 7220
The CPU views the 7220BMC as two input/output
ports on the bus. When the least-signi'ficant bit of
the address line is active (AO=1), the command/status port is selected. When the leastsignificant bit of the address .line is inactive
(AO = 0), the bidirectiohal data portis selected. In
order to defi riethe operations on these ports, it is
necessary to understand something' of the internal organization of the 7220 Bubble Memory C'ontroller.
.
',,'
'
,
For simplicity, the user need only view the 7220 as
containing a 40-byte FIFO and a collection of a:bit
registers . .The FIFO is a buffer through which data
passes on its way from the 7242,Formatter/Sense
Am plifier (FSA) to the user, orfro rn the. user to the
FSAs. The ,primary purpose of .the FIFO is to
reconcile differences in timing requirel)1el')ts between the user interface to the 7220 controller and
the controller interface to the FSAs. '
The six.a·bit registers internal to the 7220 are loaded by the user prior to any operation of, the bubble
system anp contain information, regarding the
operating ,mode of the . 72?0. ,Lo~ding the. 7220
registers before any commands are sent'is similar
to passing parameters to, a subroutine prior to invocation, hence, the regis,tersare often referred to
as "Parametric; registers.'"
.
Data transferred between the CPU and the 7220
FIFO and parametric registers takes place over an
a·bit data port. The choice as to whether,the data
is destined for the' FIFO or the'plir;lmetric
registers;. however, ,is made through the., cOrn' '
mand/status, ,port. In one case, .the"actual como.
mandsthat cause some operation, to take place,.
such as a read or write, consist of a 4·bit code sent
by the CPU to select one of 16 possible {:om·
mands. This 4·bit code occupies the low·order nibble (bits 0, 1,2, and 3) of the command byte. The
command byte must also have bit 4 set to indicate
to the 7220 that a command is being sent. In the
6-20

Ap·119
second case, another 4·bit code on the command
port (bits 0, 1, 2, and 3) is used to select either one
of the parametric registers or the 7220 FIFO. As
shown in Table 2, if bit 4 ofthe command byte is
set to zero, the value· of the low-order nibble. is
taken to be a pointer value that specifies a
parametric register or the 7220 FIFO. This pointer
is referred to as the "Register Address Counter" .
(RAC).

Table 3. Register Address Counter Assignments
Register Name

Table 2. Command Port Function
FUNCTION

07 06 05 04 03 02 01 DO

Readl
Write

Utility Register

R/W

Block Length
Register (LSB)

Block Length
Register (MSB)

Enable> Register

Address Register
(LSB)

R/W

Address Register
(MSB)

R/W

7220 FIFO

R/W

Once the FIFO has been selected, the RAC stops
incrementing and continues to pOint to the FIFO
until changed by the user software. This sequence
minimizes the number of instructions necessary
for a given transaction and aids in establishi·ng a
protocol to ensure that all of the necessary information . is sent to the controller. The user,
however, is not bound to follow this automatic sequence. Each parametric register may be selected
and loaded in any order; specific registers may be
updated where needed, but in each case, the host
software must explicitly name the register to be
loaded. Until a user is familiar with the bubble
system, it is recommended that the autoincrementing feature be used.

RAC values that may be sent out on the command
port and the corresponding register names are illustrated in Table 3. The RAC points to, or selects,
six unique registers and the 7220 FIFO. Once a
RAC value is sent by the CPU to the 7220 via the
command port, the next read or write operation to
the data port transmits data to or receives data
from the register addressed. Notice that the six
registers have values that are in ascending order
starting at OAH and that the FIFO has a value of O.
The reason for this ordering is due to the autoincrementing feature of the RAC; once the first
register is selected, each subsequent byte of data
on the data port causes the RAC to be
automatically incremented and to point to the
next register in the sequence. Once the mostsignificant byte of the Address Register has been
loaded, the RAC value automatically rolls over
from OFH to 0 and points to the 7220 FIFO. The
system is now in position to transfer data to or
from the FIFO without the user code explicitly
pointing to the FIFO.

It is important to remember that once a command

has been given to the 7220 BMC, the parametric
registers must not be updated until the Status
byte indicates that the operation. is complete. The
parametric registers are, in effect, working
registers for the controller during the execution of
a command. For example, during a Read or Write
operation, the Block Length Register, which contains the terminal page count for the operation, is
decremented by the 7220. Similarly, the Starting
Address Register; which initially contains the
starting page for an operation, is incremented by
the controller as each pa(je is transferred. Attempting to modify these registers during the operation
of a command causes the biock count and address to be incorrect.

Addressing the Bubble Memory System
One of the interesting aspects of the Intel Bubble
Memory System is its inherent addressing flexibility. The user may treat a 7220 BMC with eight
6-21

AP·119 '

bubbles as a collection of 16K pages of 64 bytes
each (addressing each bubble in turn) or as collec·
tion of 2K pages of 512 bytes each (addressing
eight bubbles in parallel). Of course, tbere are a
variety of configurations in between these two.ex·
tremes, each dictated by the user's need f.or
speed, power consumption,address space, and
cost. Control over the configuration is achieved at
run time via two of the parametric registers: the·
Block Length Register and the Starting Address
Register.
The Block Length Register (BLR) is a 16-bit value
divided into two fields: the "terminal count" field
and the "channel" field. The bit configuration for
the BLf! is as follows:

Table 4. Block Length Register

The "terminal count" field ranges over eleven bits
and defines the total number of pages requested
for a read or write operation. With eleven bits in
the field, a user may request from one to 2048
pages be transferred (eleven bits of zero indicate a
2048-page transfer). The width of the page is effectively defined in the "channel" field: This field
specifies the number of FSA channels that are to
be addressed. Recalling that each 7242 FSA has
two channels to communicate with one 7110 bubble memory, the legal combinations in this field
address one channel (one half of a 7110), two, four;
eight, or 16 channels. These combinations
translate into page sizes of 32, 64, 128,256, or 512
bytes, respectively. (The one-channel, mo.de of
operation is usually reserved for diagnostic purposes, and examples of its use. will ,be illustrated
later.)
Table 5 shows the relationship between the
"channel" field and the number of· FSA channels
selected. Notice that the channel field bits are encoded. A value of "0001" binary selects two FSA
channels: 0 and 1.

TableS. 'FSAChannel Select
Channel field (BLR MSB bits 7, 6, 5,4)
0000 0001

Number bf
channels
selected:

Thus, a BLR value of "0001" in the high:order four
bits selects one bubble through channels 0 and 1
Similarly, a BLR value of "0010" selects two bubbles in parallel with a page size 01128 bytes. This,
however, is not the complete story. For example, a
value of "0100" in the BLR selects four bubbles in
parallel through channels 0 to 7. Suppose, that
there are eight bubbles in the system and that the
user desires to arrange the eight bubbles as two
sets of four. The mechanism to communicate
through channels 0 to 7 and channels 8 to F
resides i.vith the Address Register (AR).
The Addres's Register contains a 16·bit value divided into two fields: a "starting address" field of
eleven bits and a "magnetic bubble memory
(MBM) select" field of four bits.
Table 6. Starting Address Register
MBM Select

X~'A
MSB

starting .address
A A

A A A A A A A '"

LSB

The. eleven bits ir:1 the starting address field of the
AR.are set by the user to indicate to the 7220 BMC
on which page of a bubble's 2048 pages the
transfer is to start. For example, if.a read operation is to start at page 1125 and is to continue for
16 'pages, the starting address field contains
1125, and a value of 16 is placed in the terminal
count field of the BLR. After each page is transferred, the starting address field is incremented and
the terminal count is decremented by the controller.
Continuing with the example of two banks of four
bubbles, notice in Table 7 that the MBM select
field is needed to switch between the two banks.
A value of "0000" in bits 3, 4, 5, and 6 of the highorder byte of the address register selects bank 0
or FSA channels 0 through 7; a value of "0001"
selects bank 1 or FSA channels 8 through F. Each
bank contains 2048 pages of 25~ bytes.
6-22

AP-119
To operate eight bubbles serially, a user needs only to specify a value of "0001" once in the channel
'field of the BLR and to begin with a value of
"0000" in the MBM select fh3ld. As page 2048 is
written in the first bubble, the AR, managed by the
7220 controller, rolls over to 0 and updates the
MBM select field with no additional bit manipulation. In this case, the bubble system appears as
16K pages of 64 bytes each. Power consumption
is one-eighth of that consumed by operating eight
bubbles in parallel. However, the data rate is
limited to the data rate of one bubble.

rates, respectively. (If the error correction mode is
changed, the CPU must issue an Initialize command to the 7220 controller).

INTERRUPT ENABLE (NORMAL)
INTERRUPT ENABLE (ERROR)

lJJ~~~~~~~

MFBTR
WRITE BQOTLOOP ENABLE
DMA ENABLE
ENABLE Reo
ENABLE ICD

ENABLE PARITY INTERRUPT

Table 7_ FSA Channel SelectlMBM Select
MBM SELECT "CHANNEL FIELD" (BLR MSB bits 7, 6, 5, 4)
AP. MSB BITS
(6,5,4,3)
0001
0000
0010
0100
1000

0 0 0 0
0 a a 1
a a 1 a
a a 1 1
a 1 a a
a 1 a 1
a 1 1 a
a 1 1 1
1 a a a
1 a a 1
1 a 1 a
1 a 1 1
1 1 a a
1 1 a 1
1 1 1 a
1 1 1 1

0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F

0,1.
2,3
4,5
6,7
8,9
A,B
C,D
E,F

0,1,2,3
4,5,6,7
8,9,A,B
C,D,E,F

Figure 4. Enable Register Definition
The interrupt capabilties of the 7220 are reflected
in the NORMAL, PARITY and ERROR INTERRUPT
bits of the ENABLE register byte. The 7220 controller is capable of issuing interrupts to a CPU at
the normal completion of an operation, if a parity
error is encountered between the 7220 controller
and the CPU, or if a data transfer error is found by
the 7242 FSA. Any (or all) of these conditions are
selected via the Enable register byte, and any
resultant interrupts are sent to the CPU via a
single INT line. At this point, the software must
examine the status register to determine the
cause of the interrupt. (An additional interrupt, the
FIFO half-full interrupt, is issued on the ORO pin.
and is not controlled by the Enable byte).
One of the more difficult aspects of the ENABLE
register byte to understand is the operation of the
ERROR INTERRUPT bit (bit 2). This bit normally is
not used alone, but in conjunction with the
ENABLE RCD and ENABLE ICD bits of this
register. These three bits form combinations that
gate selected 7242 error conditions to the CPU.
For example, if, while operating under error correction, a user does not wish to be bothered by an
interrupt that indicates an error has been corrected automatically by the system, a specific pattern of these three bits would be selected (100 or
010 from Table 8). If the user wishes to be notified
of all errors, another pattern would be selected
(011 or 101).

o to 7 a to F
8 to F

The Enable Register
The Enable register is the parametric register that
defines the various modes of operation of the
7220 controller. The data transfer mode (polled, interrupt driven, or DMA operation) is. selected by
setting the appropriate bit in this register.
Likewise, the type of error correction to be applied
to the data is selected, based on the bits selected
in this register.
While the function of each of the enable register
fields is described in the BPK 72.manual, some of
the finer points and implications are detailed here.
Note that it is possible to completely change the
operating characteristics of the bubble system
through software control. A system can go from
.the DMA mode with error correction enabled to a
system operating in polled I/O with no error correction enabled by altering the value of the Enable
register. Though most implementations will not
take advantage of this degree of flexibility, there
are cases where the Enable register is modified
during system operation. For example, the normal
interrupt and MFBTR bits can be modified between operations to change interrupt and read data

6-23

AP·119

Table 8. Error Correction Combinations ", .
Interrupt
Enable
(ERROR)

Interrupt Acti.on
No interrupts due to errors
Interrupt on'TE only
Interrupt on UCE orTE
Interrupt onUCE, CE or'TE
Interrupt on UCE or TE
Interrupt on UCE. CE or TE
Not used
,
Not used

The purpose of the ERROR INTERRUPT bi.t is not
to enable or disable error interrupts, but rather to
aid in selecting the type of error interrupt received
by the CPU. If any type' of .error correction is
selected, interrupts are enabled automatically.
The ENABLE RCD (read corrected data) bit causeS'
the error correction algorithm. to be applied to the
data being transferred from the 7110 MBM in an
almost transparent manner. The RCn bit allows
the 7220 controller to send its own commands to
the 7242 FSA. These commands cause the FSAtb
automatically correct -and transfer to the con- troller, any data that is found to be in error and that is considered correctable.
With only the RCD bit on, no interrupt is generat~d
if correctable error is found. HOwever, the user is
informed that'a correctable error \Nas' encountered and corrected during the data transfe'r via the 7220
status -byte at the end of the operation. Uncorrectable and timing errors cause; an interrupt tb
which the CPU mustrespond.With.both theRCD
bit and ERROR INTERRUPT bit bn, the CPU is
notified via an interrupt whenever acorrectc~ble; ,
uncorrectable or timing error is encountered,~
_

The RCD mode of oper~tion 'is s~i.'table for
transfers where. a 'GO/NO GO termination .issuffh
cient. For'example,when loading executablecode.
from the bubble to RAM, it is necessary
know
that the tra.nsfer was good (with errors correCted)
or aborted due to, an uncorrectable error. .
,

A retry of an uncorrectable page of data is. accomplished by sending another Read command
without modifying the parametric registers. It may
be the case that the errors encountered were soft
(read) errors that may not be present on a retry.
Thus, what may have been detected as an un'correctable error, may become a correctable error (or
simply vanish) on a subsequent read of the off!,!nding page. In this case, the error correction ability
of the system corrects the errors automatically
without additional user intervention.

The.-advantage of theRCD mode of operation is
that error correction can be applied transparently
to the CPU except for uncorrectable cOnditions. '
The disadvantage is that a page of uricorrectable
data.. Is passed to the controller before the interrupt is sent The softWare must have the a.bility to
clear the 7220 FIFO .prior to rereading the offeriding page from'the bubble;
,

If'a given page continues to show up" ashavil1g
correctable error aftel' a number. of retry's, it is up
to the user's protocol to determine the 'action' to.
be taken. One protocol suitable for haridling errors involves "scrubbing" the data. Suppose a
page appears with an error and, on retry, tlie error
is still present. If the error iscotrectable, the data'
should be corrected and written back' to the bubbleand then read back into RAM, The probability
of encountering an 'unc~meetable error after the
first, retry is J in 10'6; Data scrubbing after 'one'
retry maintains this level of rer'iability.
.
The ENABLE ICD (Internally correGt data) bit also '
enables the error corr-ection ,capability of the bubble system, but allows a slightly different interaction between the 7220 controller and the 7242·FSA
than defined for the RCD mode, Error interrupt
conditions are the same as defined JorRCD operation. With the ICD bit on, correctable errors are
handled.automatically, but the operation halts for
uncorrectable or timing errors. With both the .ICD
and ERROR INTERRUPT bits ,on, the,operation'
halts for' correctable, uncorrectable or timing errors. The ICD mode differs from the RCD mode in
that when an operation halts due to an error,.the
offending ,,"age is held in thih242FSA and is not
autom~ti~allytraf1sferred ',to" the .. 7220 FIFO.
Though the difference is sllbtle, the ICD'mode of
opera.tidrl allowsmoreflexi'bility i'nerr~r logging
and·recoyery. 'With data held if'!, the 7242,(he
number,o(the .b.ad. page 'can' be reCidfor logging
puh)oses;and the data cari be recycled through.
the erro'r 'correction .network or reread from the'
bubble repeatedly. When the'CPu.is i),terrupted
diJe to an error in the'leD mode, the. user' must
look a.t the 7220status byte to; determi ne the'type
of error encountered. If the error 'Is correctable,
the user's software sendS a Read Corrected' Data
command (OCH) to the controller. This command
causes the controller to iSsue it~s own commands'
to'the 7242 to correct the error and totr'ahsferthe
datato'the 7220 FIFO. (Recall thisactlonls dorie'
automaticallY'iNhenthe RCD models' selected;u~
correctable ;errors can be handled 'as described
above).
.,
,
As 'an example'o(how the;ICD'mode ca~ be ~tiliz
ed, suppose thatduring adat~ transfe.r in the RPD
mode, a correctable error cOnsistently occurs. The
&-24'

AP·119
error, of course, is automatically handled by the
7242, and the only indication that an error had
been corrected is through the status byte at the
end of the transfer. There is no information as to
how many or in what page the error or errors appear. One way to diagnose the problem is to
reread the entire data block in the ICD mode with
the ERROR INTERRUPT bit on. The transfer stops
at the appearance of any error, and the data remains in the 7242. The page number of the error
can be found by reading the Address Register
since this register is incremented automatically
after each page is read if no error is detected.
The user should then issue an RCD command to
the 7220 to allow the page to be corrected and
transferred to the 7220. Once the transfer is complete, the enable register again is changed to
disable all error correction, and the 7220 is
reinitialized. The entire block is read again arid
compared with the corrected version. (Error correction bits are appended to the data and can be
ignored.) If a bad loop is suspected, the bad loop
location could be calculated and the bootloop
modified.
It is unlikely that repeated correctable errors are
sufficient motivation to modify the bootloop.
Repeated uncorrectable errors, however, at the
same location, might be sufficient reason. Note
that modifying the bootloop is an extreme
measure and should only be performed as a last
resort and only if justified by test data.

The Status Register
The,7220's 8-bit Status register is accessed by
reading the Command port (AO = 1). This register
provides information regarding error conditions,
the termination of commands, and the readiness
of the controller to transfE!r data or accept new
commands.

lJJ~~~~~~~

Values for the Uncorrectable Error and Correctable Error fields are generated when error correction is utilized as previously defined. The PARITY
ERROR bit is set when a parity error is encountered on data sent to the controller on the
00-07 lines. The TIMING ERROR bit is set for a
number of conditions. The most frequent cause of
a timing error is when the CPU fails to keep up
with the rate at which the controller is filling or
emptying the FIFO (an overflow or underflow condition). With one bubble in the system and the
MFBTR bit of the Enable byte set to one, the controller moves data to or from the FIFO at a rate of
about one byte every 80 microseconds. With eight
bubbles operating in parallel, the rate is about one
byte every 10 microseconds. (With the MFBTR bit
set to 0, the data rate on a one page transfer or the
last page of a multipage transfer is four times
these rates.) Once a Read or Write command is
issued, if the CPU cannot meet these transfer requirements, a timing error results.
Another way in which a timing error' occurs is
when the proper number of bits is not set in the
bootloop register of the 7242 FSA. The 7242 must
have 272 loops active to operate properly (270 with
error correction enabled). If a mistake is made
either when the bootloop of the 7110 is written or
if the bootloop register is loaded incorrectly from
RAM by the user, a timing error results. A timing
error also occurs if the Write Bootloop command
is issued to the 7220 controller and the WRITE
BOOT LOOP ENABLE bit of the Enable byte is not
on. Finally, a timing error is generated if the
bootloop synch code is not found when a Read
Bootloop or Initialize command is issued.
The OP FAIL and OP COMPLETE bits of the status
register simply indicate the state of an operation
after a command is executed. If an operation fails
(OP FAIL = 1), the cause can be determined by
looking at the other error bits of ttie status byte.
When an operation (command) terminates successfully, the OP COMPLETE bit is set, and the
status register shows a 40H.
The FIFO AVAILABLE bit of the status byte is
more complex than the other bits since its meaning can change depending on the type of operation being performed as outlined below.
From an operational paint of view, the FIFO
AVAILABLE bit acts as a gate fqr the FIFOhandling software. During a write operation, if the FIFO
bit is set (1), there is room for more data; if the
FIFO bit is clear (0), the FIFO is full. During a read
operation, if the FIFO bit is set, data has been
placed in the FIFO by the controller; if it is clear,
the FIFO is empty.

FIFO AVAILABLE
PARITY ERROR
CORRECTABLE ERROR
UNCQRRECTABLE
ERROR
TIMING
ERROR
OP FAIL

OP COMPLETE
BUSY

Figure 5. Status Register Definition

6-25

AP·119
be low in order for the controller to accept a new
command (except Abort). Sometime between TO
and T1, the BUSY bit goes high. Thus, between T1
and T2, the status byte will be 80H.

Table 9. FIFO Available Bit Semantics

At T2, the FIFO is internally placed in the "write
mode," and FIFO AVAILABLE changes meaning
from "FIFO has data" to "FIFO has room". For
proper operation, the FIFO must be empty prior to
issuing the WRITE command. This condition can
be guaranteed by using the FIFO Reset command.
Assuming the FIFO is emptY,at T2 the status byte
changes from 80H to 81 H. The status byte remains
at 81 H until T6 (unless the CPU is able to fill the
FIFO in which case, the FIFO AVAILABLE bit tog·
gles between 0 and 1).

Note that it is possible to complete an operation
with data still remaining in the FIFO (indicated by
a 41 H status value). This condition is quite legal; it
is up to the software 'to remove the data or to issue
a FIFO RESET command.

At T7 (the completion of the comn;land), the status
byte should be 40H if the CPU did not load data
between T6 and T7. If data was loaded during this
interval, the status value is 41H.

The BUSY bit indicates. when the controller is in
the process of executing a command. When a
command is sent, the BUSY bit gO,es active within
a few microseconds after the command is receiv,·
ed and remains active until the operation either
completes or fails. It is important to note that the
BUSY bit remains active until all other bits in the
status byte have been set. Thus it is possible to
see logically·exclusive conditions such as BUSY
and OP COMPLETE at the same time. The key to
interpreting the status byte is to consider the
status byte valid only after the BUSY bit returns to
an inactive level. The single exception to this rule
is the FIFO AVAILABLE bit.

Notice that if ,the FIFO ,contains data when the
Write command is sent, the CPU can, by mistake,
overflow the FIFO during the "seek" portion of the
command. This condition results from the FIFO
AVAILABLE bit being a "1" due to data present in
the FIFO, not because there is room in the FIFO.
While the following diagnostic routines take ad·
vantage of the "preloading" ability of the FIFO,
the examples of operational software at the end of
this application note,do not preload ,the FIFO.

7220 Commands
The 7220 command set consists of 16 commands
identified by a 4·bit command code. The function
of most of the commands is obvious from the
command' name (e.g., Initialize, Abort, Read,
Write). These commands are' adequately describ·
ed in the BPK72 manual. There are, however,
some commands and protocols that merit addi·
tional discussion (specific examples are covered
later in this document).

The action of the controller during a write opera·
tion is one of the more complex sequences and
serves as a good illustration of the behavior of the
BUSY and FIFO AVAILABLE bits. Supp'ose a Write
command is sent to transfer an arbitrary number
of pages. Table 10 shows the activity of the con·
troller at various steps in the sequence.

Table 11. 7220 Commands

Table 10. Stages of a Write Command
wait for
2 bytes
overhead
of FIFO generate swap overhead
seek data

(time line is not to

FIFO
reset

scal~)

Before the Write command i,s sent, the FIFO is in a
general·purpose mode and remains in this mode
until T2. When the command is serit at TO,
the BUSY bit is low and, in fact, the BUSY bit must
'6·26

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0,
1
0
1
0
1
0
1
0
1

o;
0
1
1
1
1
0
0
0
0
1
1
1
1

Command Name
Write Booiloop Register Masked
Initialize
Read Bubble Data
Write Bubble Data
Read Seek
,Read Bootloop Register
Wriie Bootloop Register
Write Bootloop
Read FSA Status
Abort
Write Seek
Read Bootloop
Read Corrected Data
Reset FIFO
MBM Purge
Software Reset

Ap·119
In general, all commands sent to the 7220 controller must be preceded by the setting of the
parametric registers. While there are some exceptions as with the Abort command, it is usually
necessary to supply operating information to the
controller via the parametric registers prior to issuing any command. Since many initial problems
stem from failing to load the registers prior to issuing commands, the user software should never
assume that the regsiters contain valid data.

After the bubble system has been powered up, the
7220 controller inhibits (or ignores) all commands
except an Initialize or Abort command. One of
these commands must be sent prior to issuing
any other command. Normally, the first command
issued after loading the parametric registers is'
the Initialize command. This complex command
reads and decodes the bootloop information from
each bubble in the system and places this information in the bootloop register of the corresponding 7242 FSA. Pointers internal to the 7220
automatically are prepared for normal operation.
As described later, the combination of the Abort,
MBM Purge and Write Bootloop Register commands is functionally similar to the Initialize command. (The only time the MBM Purge command is
used is in conjunction with the Abort command).
Once the system has been initialized; the remainder of the command set can be selected.
Assuming, for example, that a Read command is
to be executed, the user selects the page number
and length of the transfer via the parametric
regisiters and then issues the Read command. If
the system uses the polled mode, the CPU reads
the status register and waits for the BUSY bit to
go active and then for the FIFO READY bit to indicate that data is being sent to the FIFO. Data
can be taken from the FIFO until the FIFO READY
bit goes inactive.

should issue a FIFO Reset command in order to
clear the 7220's FIFO counter before initiating the
data transfer. If a prior transfer is stopped with
data remaining in the FIFO or if the FIFO is partially filled, the 7220's internal FIFO counter is not
zero, and there is a danger that the subsequent
transfer count may be incorrect. If the FIFO is
reset properly, execution of a FIFO Reset command is redundant.
Although the 7220 FIFO may be treated as a
40-byte RAM buffer, the temptation to "pre-load"
the FIFO with 40 bytes of data and then to issuea
Write I command should be avoided due to the
danger of overflowing the FIFO. Prior to issuing a
Write command, a FIFO Reset command should
be sent, and the parametric registers should be
loaded. Following the Write command, the CPU
should monitor the status byte and wait for the
BUSY and FIFO AVAILABLE bits to go active.
When this status condition occurs, the user software should then send the proper number of bytes
to the 7220. The FIFO AVAILABLE bit of the status
byte should be polled prior to sending each byte.
An exception to not preloading the FIFO is when a
Write Bootloop, Write Bootloop Register, or Write
Bootloop Register Masked command is used.
Prior to issuing any of these commands, a FIFO
Reset command must be sent before preloading
the bootloop data into the FIFO. When one of the
bootloop-related commands is ,issued, the 7220
controller iml)1ediately begins taking data from
the FIFO. If the FIFO is not preloaded, incorrect
data may be transferred. The operation of the normal Write command differs from the bootloop·
related commands in that, after a Write command
is issued, the 7220 waits for at least two bytes to
be present· in the FIFO before beginning to
transfer data to the bubble.
If the FSA encounters an error condition during a
read or write operation, the status of the FSA is
reflected in the 7220 status byte. If the user
system decodes the error and decides to continue, the error flags in the 7220 controller and
FSA first must be cleared. To clear the status
bytes, the software can issue, an Initialize command. However, this command resets all of the
current operating parameters in the 7220 controller. To continue processing without resetting
the system, the software can use the Software
Reset command. This command resets any error
flags and clears the FIFO, but does not affect the
parametric register fields that define the system
configuration (e.g.,. number of FSA channels
selected).

If the page selected for the read operation is not in
position to be read (Le., the; page is not 'at the
replicate gates), additional time is required to execute the Read command as the proper page is
rotated into position. In systems where faster,
response is desired, the Read Seek command can
be used to place the. page into position in order to
free the CPU to perform other tasks. Once the
page is in position, approximately eight
milliseconds are required before the data is
available to the CPU. This latency only occurs on
the first page of a multipage transfer. Similarly,
when a page is not in a position to be written,
Write Seek can be used to position the page at the
swap gates.
If there is any doubt regarding the state of the
FIFO prior to a read or write operation, the user
6-27

Ap·119
INSTALLING THE BPK 72 BUBBLE
MEMORY KIT

7220 are communicating and that the power-up sequence is being performed by the 7220. '

This section examines the individual cpmponents
of the Bubble Memory System and how each component can be analyzed_ All elements of the bubo,
ble system need not be working before any meaningful diagnostics can be effected. In general, a
user first establishes communication between the
host CPU and the 7220 controller. Next, communication with the 7242 formatter/senseamplifier is verified via the 7220 controller. Finally,
the operation of the 7110 Bubble Memory is
checked. The software that exercises each of
these phases of implementation should be small,
well-defined device drivers that can be controlled
through a system monitor.
The procedures that follow are appl,icable to most
startup problems. The procedures are organized in
chronological fashion and address each step of
the installation process as it would normally occur. Software drivers in 8086 assembly language
are provided to illustrate the basic functions supported by the device drivers.

Powering Up for the First Time
With power removed from the IMB-72 board, insert
all of the supporting integrated circuits with the
exception of the 7110 Bubble Memory Module. Insert the "dummy module" included in the BPK 72
kit in place of the 7110. The dummy module is
electrically equivalent to the 7110 module and
allows the circuits of the BPK 72 kit to be tested
without the possibility of 'damaging the bubble.
With both the -I' 5V and + 12Vpower supplies
turned off, insert the 1MB 72 with the dummy
module into the edge connector. As power is applied to the system, monitor the RESET.OUT/pin
of the 7220 controller and verify that the signal
goes from low to,high after power is applied. The
low-to-high transition, indicates that the power-up
sequence has been completed successfully.

Table 12. Reading 7220 Controller Status
RDSTAT:
; THIS PROGRAM READS THE 1220
. STATUS BYTE
; TO READ STATUS, THE HOST CPU MUST
; READ FROM THE 7220 WITH AO = 1.
IN
MOV

AL,49H

;
;
;
STATUS, AL ;
;

COMMANDS/STATUS
PORT ADDRESS OF
7220
MOVE AL REGISTER
TO STATUS

RET

Once the power-up sequence is complete and the
72;20 status register has been read, the 7220 FIFO
can be accessed. The software drivers that write
and read the FIFO are shown in Tables 13 and 14.
Notice that' these code sequences do not send
commmands to the 7220; only data is transferred
to and from the controller. The purpose here is to
test the bus interface and timing between the CPU
and the 7220 controller_ In this case, the 7220
FIFO is used as a general purpose RAM. Any data
can be written to the FIFO, but it is best to use an
easily indentifiable sequence (e.g., an incrementing pattern) for easy recognition.
Table 13. Writing the 7220 FIFO
WTFIFO:
; THIS PROGRAM WRITES 40 BYTES FOR
; MEMORY TO THE 7220 FIFO.
; DATA IS ASSUMED TO BE ATBUFADR.
MOVE

SI,BUFADR

MOV
CX,40
WRT1:
LODSB

Communicating With the 7220 Bubble
Memory Controller
The first step in communicating with the 7220 is
to write initial values to the parametric registers
using the code sequence in Table 15_ When the
registers have been set, the code shown inTable
12 can ,be u~ed to examine the ,7220 status byte.

The status value 'returned in Table 12 should be
40H. The user should not continue until the proper
status value can be obtained repeatedly after performing the power-up seq'uence. Reading back the
correct status indicates that the host CPU and the
6-28

LOAD BUFFER
POINTER
LOAD COUNT
PUT BYTE AT SI
INTO AL, AUTO INCR
SI
OUTPUT BYTE TO
DATA PORT
DECREMENT COUNT,
LOOP IF NOT 0

Ap·119
Once forty bytes have been written to the FIFO,
the 7220 status byte should be read. The status
value should be "41H" (indicating that data is in
the FIFO). Other status values such as "parity
error" can be ignored. While status values give·
some indication of the CPU-7220 interaction, the
integrity of the data is more important here. If the
data read back is not the same as the data sent, a
fundamental timing and/or interface problem between the CPU and the 7220 is indicated.
To verify that data is being transmitted to the
7220, the code sequence shown in Table 14 can be
used to read back the FIFO data into user RAM
space for direct comparison with the original
pattern.

Under normal operating conditions an Initialize
. command is the second command sent to the
system. However, the Initialize command
assumes that the 7110 Bubble Memory is installed
and attempts to read bootloop information. Since
the dummy module is installed at this time, timing
errors result. from the attempted Initialize command. Although no harm resultsfrom using the Initialize command, an Abort command followed by
an MBM-Purge command can be used in place of
the Initialize command to eliminate timing errors.
The Abort command is sent by executing the code
sequence at label "CMND9" in Table 16. When
Abort command execution is complete, the user
should read the status byte and check for an opcomplete indication (40H).

Table 14. Reading the 7220 FIFO
RDFIFO:
; THE PROGRAM READS 40 BYTES FROM
; THE 7220 FIFO INTO MEMORY.
MOV
MOV
RD1:
iN

DI, BUFADR ;
;
CX,40
;
;
AL,48H

STOSB
LOOP

RD1.

LOAD BUFFER AD·
DRESS INTO DI
LOAD COUNT INTO
CX

; INPUT FROM DATA
; PORT
; STORE AL AT ADDR
; IN DI, AUTO INCR. DI
; DECREMENT COUNT
;. IN CX, LOOP IF NOT 0

RET

After reading the FIFO, the status byte should be
read (a value of "40H" or "42H," indicating that
the FIFO has no data, should be obtained). The
user should not proceed until the FIFO can be
written and read correctly' and until the, FIFO
status indicates the amount of data in the FIFO
(not empty or empty). These steps verify that the
CPU can communicate with the 7220. Note that no
data has been transferred to or from the 7242 Formatter/Sense Amplifier or the 7110 bubble device
(or dummy module).

Communicating With the 7242
Formatter/Sense Amplifier
The next step in verifying the BPK 72 is to ensure
that the 7220 is driving the 7242 Formatter/Sense
Amplifier properly by first setting up the 7220 for
interaction with the 7242 and then sending commands to the 7220 to exercise the 7242 functions
that can be verified easily.

6-29

AP~119

Table 15. Write Register Sequence for Two FSA Channels

WTREG2:;
WRITE REGISTERS
; 2 FSA CHANNELs SELECTED.
; THIS IS USED FOR DEBUG TO WRITE/READ THE
; BOOTLOOP REGISTERS AND CHECK FOR MISSING SEEDS, ETC.
. ; THE FOLLOWING VALUES INTO THE 7220 REGISTERS
B = 01 H
: 1 PAG'E TRANSFER
C = 10H
: SELECT 2 CHANNELS (WH·OLE BUBBLE)
: STANDARD TRANSFER RATE
D = 08H
: PAGE 0
E = OOH
: FIRST BUBBLE
F = OOH
MOV
OUT
MOV
OUT
MOV
OUT
MOV
OUT
MOV
OUT
MOV
OUT
RET

AL,OBH
49H,AL
AL,01H
48H,AL
AL,10H
48H, AL
AL,08H
48H,AL
AL,OOH
48H,AL
AL,OOH
48H,AL

; SELECT B REGISTER
; ONE PAGE niANSFERS
; WHOLE BUBBLE (2 FSA CHANNELS)
; LOW FREQ
; START ADDRESS = OOOOH
; FIRST BUBBLE

Once the op-complete status is received, the
MBM-Purge command is issued by executing the
routine labeled "CMNDE" in Table 16. This command, as described in the BPK 72 manual, clears
all of the controller registers, counters and address RAM (except the block length register), the
NFC bits, the FSA present counter and the highorder four bits of the address register. After the
command is complete, the user again should
receive an operation complete indication on
reading the status byte.

After the Abort and M BM-Purge commands are executed and is status verified, additional commands may be sent to the 7220 BMC. Since the
purpose of this section is to verify the interaction
of the 7242 and 7220, manually loading and
reading the 7242 bootloop registers canbe used
for the verification. Two,additional commands are
required to load and read the bootloop registers:
the Write Bootloop Register command and the
Read Bootloop Register command. These commands transfer data between the 7242 bootloop
registers and the 7220 FIFO. Since the ability to
transfer data between user RAM and the 7220

6-30

Ap·119

Table 16. 7220 Controller Commands

CMNDS:
; 7220 COMMANDS
; THESE 16 ROUTINES EACH SEND A SINGLE COMMAND TO THE 7220.
; FOR EXAMPLE, THE "INITIALIZE COMMAND" WILL WRITE 11H
; TO THE 7220 WITH AO = 1. THESE ARE THE 7220 COMMANDS LISTED
; IN THE BPK·72 USERS MANUAL.
CMNDO:
MOV
AL,10H
; WRITE BOOTLOOP REGISTER MASKED COMMAND
49H,AL
OUT
RET
CMND1:
MOV
AL, 11H
; INITIALIZE COMMAND
OUT
49H,AL
RET
CMND2:
MOV
AL,12H
; READ COMMAND
OUT
49H,AL
RET
CMND3:
MOV
AL,13H
; WRITE COMMAND
OUT
49H,AL
RET
CMND4:
MOV
AL,14H,
;READSEEKCOMMAN~
49H, AL
OUT
RET
CMND5:
MOV
AL,15H
; READ BOOTLOOP REGISTER COMMAND
OUT
49H,AL
RET
CMND6:
MOV
AL,16H
; WRITE BOOTLOOP REGISTER COMMAND
OUT
49H,AL
RET
CMND7:
MOV
AL,17H
; WRITE BOOTLOOP COMMAND
OUT
49H, AL
RET
CMND8:
MOV
AL,18H
; READ FSA STATUS COMMAND
OUT
49H, AL
RET
CMND9:
MOV
AL,19H
; ABORT COMMAND
OUT
49H, AL
RET
CMNDA:
' AL,1AH
MOV
; WRITE SEEK COMMAND.
OUT
49H, AL
RET
CMNDB:

6-31

Ap·119

Table 16. 7220 Controller Commands (cont.)

MOV
OUT
RET
CMNDC:
MOV
OUT
RET
CMNDD:
MOV
OUT
RET
CMNDE:
MOV
OUT

RET
CMNDF:
MOV
OUT
RET

AL,1BH
49H,AL

; READ BOOTLOOR COMMAND

AL,1CH
49H, AL

; READ CORRECTED.DATA COMMAND

; SOFTWARE RESET COMMAND

FIFO has been verified previously, these two additional commands verify the system's ability to
transfer between user RAM and the 7242 FSA.
The 1220 parametric registers must be loaded·
prior to sending the Write Bootloop Register command. The sequence of operations is important;
loading the parametric registers destroys the first
byte of data in the 1220 FIFO, If valid bootloop information is placed in the FIFO before the
parametric registers are loaded, the first byte of
bootloop register information is invalid. Accordingly, the sequence of operations must be as
follows:
(1) load the 7220 parametric registers
(2) load bootloop data into the 7220 FIFO
(3) send the Write Bootloop Register command.
As a point of interest, if a user wishes to maintain
the system bootloop in EPROM rather than to
allow automatic handling by the system,the Initialize command would not be used and would be
replaced by a sequence similar to the one described.
. After the 7220 parametric registers are loaded, the
CPU next must load the 7220 FIFO with 40 bytes
of bootloop register data using the "write FIFO"
sequence from Table 13. This sequence then is
followed by the code sequence to issue the Write
: Bootloop .Register· command. The data pattern

written to the bootloop register should be an easily identified sequence of bytes such as an incrementing pattern. Under operational conditions,
the data written to the bootloop registers
represents "loop map" information that is written
on the label of the 7110 device. Under these test
conditions, it only is necessary to ensure that the
40 bytes sent out are the same 40 bytes read back.
Once the Write Bootloop Register command has
been sent, the status byte is read (when the BUSY
bit goes low) and an operation-complete status is
verified. Any parity error indication may be ignored. Valid status at this pOint indicates that
communication with the 7242 has been established. To verify that the data has been transferred
properly, the contents of the bootloop register are
read into the 1220's FIFO. The CPU then must
transfer the data to user RAM in order to cOmpare
the data with the original pattern. To read the
bootloop register, it only is necessary to issue the
Read Bootloop Register comm·and. This cqmmand places the contents of the 1242's bootloop
register into the 7220's. FIFO. The user then must
execute the "read FIFO" sequence from Table 14
in order to transfer the data from the 7220 FIFO to
RAM. Comparing the loop map written into the
bootloop register and the loop map read from the
bootloop register should show the loop maps to
be equal.

6-32

Ap·119
Installing the 7110 MBM
Reading and writing the 7110 bubble memory re-.
quires the application of specific control signals
at the appropriate times within the read or write
cycles. These control signals originate from the
7254 and 7230 integrated circuits and are.
generated under the control of the 7220 BMC.
Prior to installing the 7110, the presence of the
control signals should be verified., While it is
unlikely that the 7110 can be seriously damaged, it
is possible for the "seeds" and bootloop
established at the factory to be lost if there are
problems with the 7254 or 7330 control signals
and, if lost, would require additional steps on the
part of the user to regenerate the seeds andbootloop data. With the dummy module installed,
the required control signals can be verified directlyon the bubble socket, and the possibility of
damaging the bubble can be avoided.
The first control signal waveform to check isJhe
coil drive on pins 9, 10, 11, and 12 of the 7110
socket. The dri.ve current can be verified by ensuring that the voltage waveform on these pins (or on
pins 1 and 7 of the 7254) conforms to Figure 6A
when the drive field is being rotated. To rotate the
drive field, the following code sequence can be
used:

1. Write the parametric registers.
2. Send the Read command.
Next, the "cut and transfer" pulses generated during a read operation should be checked. The
waveforms on pins 2 and 3' of the 7110 socket
(REPLICATE.A and REPLICATE. B), should appear
as shown in Figure 6B.
.
The cut and transfer pulses that occur during a
write operation should now be verified. The
waveforms on pins 7 arid 8 of the 7110 socket
(GENERATE. A and GENERATE. B) should appear
as shown in Figure 6C. Since a write operation is
required, a new code sequence must be used for
this test: .
·1 .. Write the parametric registers.
2. Write data (any patten) to .the FIFO.
3. Send the Write command.

bootloop register of the 7242 first must be loaded
to allow data to be written. A Write Bootloop
Register Masked command can be used to write a
bootloop register pattern of all ones; it is only
necessary to write the boot loop register once.
Finally, the SWAP pin is tested for proper operation du ri ng a. write operation. The waveforms on
pins 13 and 14 of the 7110 (SWAP.A and SWAP.B)
should appear as shown in Figure ·60. The code
sequence described for a write operation may be
used ..
One additional check of the system should be
made prior to installing the 7110 device to determine if valid status values are received after a
Read or Write command is issued to the 7220
BMC. Since the bubble is not yet installed, no data
actually is transferred; the system should,
however, execute the Read or Write command,
and valid status should be received. Since a new
command cannot be issued to the 7220 while a
command is in progress, an Abort command is
sent to cancel any command that may be pending
from the last test performed. Next, a FIFO Reset
command is sent to clear any data remaining in
the FIFO. The status byte received should indicate an OP-COMPLETE and FIFO AVAILABLE
status condition. The 7220 now is ready to execute a Read or Write command.
First, the 7220 parametric registers are loaded using the modified "diagnostic" driver shown in
Table 17. This routine selects one FSA channel
(half of a bubble) and, with ECC disabled, requires
the loading of only 34 bytes in the 7220 FIFO. By
limiting the FIFO to less than 40 bytes, FIFO
underflow/overflow conditions are eliminated, and
timing errors are avoided in the status byte. After,
the 7220 FIFO is preloaded with 34 bytes of data
(any pattern), a Write command is issued to the
7220 BMC. The 7220 status value received following command execution should reflect OPCOMPLETE .sirice the.7220 transferr!3dtl'ie' data
from its FIFO to the 7242 and executed the Write
command
as though 'the, bubble were in pi. ace ..,
.
'

PIN 2, 3
(DURING READ)

PIN 7, 8
(DURING WRITE)

12V
~

+ 10.3V

12V

PIN 14,13.
(DURING WRITE)
~

~28.75 ~s

+ 4.3V

(Noldrawn 10 scale)

Figure 6.. Control Signal Waveforms

Installing the 7110 is no differeht from installing
any other device. Remove the dummy module in
the 7110 socket and insert the 7110 Bubble
Memory~ Note that the 7110 is keyed to prevent
the device from being inserted incorrectly. When
power is applied, the system should execufe its
power-up sequence as described for the dummy
module, and the 7220 status byte should return
OP-COMP.LETE after tl:le parametric registers
have been loaded.

To.test thE! system in the read mode,the 7220
parametric registers are reloaded and a Read command is issued to the 7220. The. user software
must now read 34 bytes of "data" from the 7220'S
FIFO. Note that the data read will consist of all
zeroes since no bubble is in place.
When the system completes all of the previous
tests successfully, the 7110 bubble memory
device may be inserted. Before proceeding,
REMOVE POWER FROM THE SYSTEM.

6-34

Ap·119

Table 17. Write Register Sequence for One FSA Channel

WTREG1:;

WRITE REGISTERS (ONE HALF BUBBLE)

THIS PROGRAM WRITES THE 7220 REGISTERS "B" THROUGH "F".
DIAGNOSTIC ROUTINE WITH ONE FSA CHANNEL SELECTED
THE FOLLOWING VALUES ARE WRITTEN TO THE 7220 REGISTERS.
B =01 H :
1 PAGE TRANSFER
SELECT 1 CHANNEL (HALF BUBBLE)
C = OOH
D = 08H
LOW FREQ ,
E = OOH ..
PAGE 0
F = OOH
FIRST BUBBLE
MOV
OUT
MOV
OUT
MOV
OUT
MOV
OUT
MOV
OUT.
MOV
OUT

RET

AL,OBH
49H, AL
AL,01H .
48H, AL
AL,OH
48H,AL
AL,08H
48H,AL
AL,OH
48H, AL ..

;
;
;
. ;
;

AL,OH
48H, AL

SET REGISTER ADDRESS COUNTER (RAC) TO B REGISTER
PROT ADDRESS ·OF 7220 WITH AO = 1
SET B REGISTER TO 01H (ONE PAGE TRANSFER)
PORT ADDRESS OF 7220 WITH AO = 0
SELECT HALF BUBBLE (1 FSA CHANNEL)' ..

; SELECT LOW FREQ (NO ERROR CORRECTION)
; START ADDRESS = OOOH
; SELECT THE FIRST BUBBLE

Normal Read and Write Operations

Prior to issuing the Write command, a FIFO Reset
command is sent and then the parametric
registers are loaded to select the page address
and number of FSA channels. After the Write command is sent, the data should be output to the
7220 FIFO. When the proper number of bytes have
been t~ansferred, the 7220 status byte should
reflect OP-COMPLETE and FIFO AVAILABLE to
indicate that the data has been written into the
7110 bubble memory and can now be read. To read
back the data written, issue a FIFO Reset command and reload the parametric registers to select
the same page address in which the. data was written. Issue the Read command to move the data
from the 7110 to the 7220 FI FO and then use the
"read FIFO" routine to transfer the data to user
RAM. As always, the 7220 status byte should be
checked after the operation.

Under normal operating conditions, a user sends
an Initialize command and then proceeds to ac·
cess the bubble. The Initialize command
automatically purges the RAM area of the 7220,
reads and decodes the bootloop on the 7110, fills
the 7242 bootloop registers, and places the 7110
at page O. This very important command is the
next command to be tested before reading and·
writing data.
To verify the Initialize command, load the 7220
parametric registers to select both FSA channels
for one bubble and then send the Initialize com·
mand~ Status following execution of this command should be 40H, OP-COMPLETE. Once the
7220 is initialized, data can be transferred to and
from the bubble. For a first attempt, it is recommeded that the operations be kept simpie. That is,
avoid error correction, DMA, or interrupts and only
attempt single page transactions until reasonably
familiar with the basic operations.

6-35

AP·119
AN IMPLEMENTATION EXAMPLE
To illustrate the ease with which Intel's bubble
memory solution may be implemented, an MCS~86
System Design Kit (SDK-86) is used as a vehicle to
control a single BPK 72 bubble memory kit.
The bus interface between the 8086 CPU and the
7220 bubble memory controller requires seven integrated circuits and consists of four sections: address decode, data bus decode and buffering, a
clock circuit, and miscellaneous 'control logic.
The system requires power supply voltages of
+ 12V, + 5V, and, if a CRT is used, -12V.
The 8086 bus is expanded through two 50-pin,
wirewrap connectors, and the BPK 72 is connected to the SDK-86 by a flat cable into a 40-pin '
connector located on the SDK-86. The following
interface diagram shows how the signals required
by the bubble system are derived from the 8086.
Detailed diagrams of the address, data, clock and
control logic are in the appendix.
Either the SDK-86's Keypad or Serial monitor may
be used to write and debug the necessary software drivers to control the BPK 72. There is,
however, an EPROM-based monitor (BMDSDK) explicity designed for the BPK 72 and is available
from the Intel Insite Library. Some of the bubblespecifiC portions of this monitor are discussed in
the following text.

Monitor Software
The BMDSDK BubbleMonitor is a highly,modular
program that is written in 8086 assembly language
and that resides in two 2716 EPROMs. This
monitor'imp!ements, at the console level, most of
the standard SDK-86 monitor functions
(display/change memory, etc.) and all of the 7220
commands. The current version of the monitor
utilizes only polled I/O protocol; implementing an
interrupt-driven system on the SDK,86 is possible

using the principles outlined in this application
note. The DMA mode of operation is not available
with the hardware described.
The BPK 72 driver routines are confined to one
module; a listing of this module is included in the
appendix. To provide some feeling for the
elements of "operational" software as opposed to
the test drivers discussed earlier, the write function implemented in BMDSDK monitor is examined. The flow chart in Figure 9 shows how the
routine is constructed on a functional basis. Note
that the subroutine reflects a very "safe" ap~
proach in that the FIFO Reset command always is
sent prior to issuing the Write command. While
the FIFO Reset command is not mandatory, if
there is any a doubt regarding the state of the
FIFO prior to a read or write operation, resetting
the FIFO is a good idea. Note also that a running
byte count is maintained and that the routine exits
when the count goes to zero. Such a counter is not
actually necessary; the FIFO AVAILABLE bit
alone can be used to gate the data to the 7220.
Thecalling program supplies the BMWRIT routine
with the total number of bytes to be transferred in
the CX register. The total number of bytes written
is sent to the console at the end of the operation
as a monitor function. BMWRIT also returns the
value of the status byte to the calling program.
Note that at label WRIT01, the ,routine does not
progress after the Write command.Is sent unless
both the BUSY and FIFOAVAILABLE bits are set
by the controller. Once these values are set, the
code issues a byte of data to the controller only if
the FIFO AVAILABLE bit indicates there is room.
The remainder of the code in BMWRIT is concerned with processing special write requests for the
bootloop and bootloop register commands.

Figure 7. SOK·86/BPK 72 Implementation

6-37

Ap·119

USER
HARDWARE

SDK·86
SIGNALS
BDO - BD15
BDTIR

I 16
~

BHEI

BPK72
SIGNALS

DATA BUS
BUFFERS
AND
DECODING
lOGIC

Figure 8. SDK·86/BPK 72 Interface Diagram

DACKI
WAITI
CSI (7242)

COMPUTE
BYTES
TRANSFERRED

Figure 9. BMWRIT Flowchart

'6-39

Ap·119

Table 18. BMWRIT Procedure for the SDK·86

FUNCTION: BMWRIT· WRITE BUBBLE MEMORY DATA.
INPUTS: CX = # OF BYTES TO WRITE.
OUTPUTS: A = STATUS: F/F(C= 1: ERROR OCCURED) BX=# OF BYTES WRITTEN.
CALLS: SNDREG, BMWAIT.
DESTROYS: ALL.
DESCRIPTION:
THIS PROCEDURE PERFORMS A BUBBLE MEMORY WRITE OPERATION.
AN ERROR WILL OCCUR IF THE NUMBER OF BYTES GIVEN FOR THE
WRITE OPERATION EXCEED THE NUMBER THAT THE BMC EXPECTS
(DERIVED FROM COMMAND, BLOCK LENGTH AND NUMBER OF FSA
CHANNELS), OR IF THE NUMBER OF BYTES IS LESS THAN THAT
WHICH THE BMC EXPECTS.
BMWRIT:
XOR
MOV
MOV
MOV
OUT
CALL
MOV
MOV
OUT
WRlT01:
IN
TEST
JZ
TEST
JZ

AL, AL
STATUS,AL
BX,CX
AL,CFR
BMSTAT, AL
SNDREG
SI, BUFADR
AL, BMCMD
BMSTAT, AL
AL, BMSTAT
AL, BUSYBT
WRIT01
AL, FIFOBT
WRIT01

; CLEAR STATUS

;
;
;
;
;

FIFO RESET
SEND REGISTERS TO BMC.
SET UP SRC BFR PTR (IN DATA SEG)
GET COMMAND
.
ISSUE IT.

; WAIT FOR BUSY ...
; AND FIFO READY·

KEEP STUFFING DATA INTO FIFO UNTIL DONE OR AN .ERROR-OCCURS.
(NOTE: BMC GOING NOT BUSY IS AN ERROR).

,
WRIT03:
IN
AL, BMSTAT
; GET STATUS
AL, FIFOBT
; FIFO READY?
TEST
JZ
WRIT04
; NO, WAIT FOR IT
LODSB
; YES,GET DATA FOR IT
OUT
BMDATA, AL
; GIVE IT TO BMC
LOOP
WRIT03
; LOOP UNTIL DONE.
JMP
BMWAIT
; XFER DONE, WAIT FOR A GOOD STATUS
WRIT04:
AL,BUSYBT
TEST
JNZ
WRIT03 .
;OK IF STILL BUSY
SUB
BX, CX
; BX:# OF BYTES XFERED
JMP
CTRL99
; ERROR IF NOT BUSY AND CX NOT ZERO
SPECIAL WRITE FOR BOOTLOOP AND BOOTLOOP REG.CMNDS

,
BMWRTB:
XOR
MOV
MOV
MOV
OUT
CALL
MOV

AL,AL
STATUS,AL
BX,.CX
.
AL,CFR
BMSTAT, AL
SNDREG
SI, BUFADR

;A = 0
; CLEAR STATUS

FIFO RESET
SEND REGISTERS TO BMC.
SET UP SR<;: BFR PTR (IN DATA SEG)

; FILL FIFO WITH 20/40/41 BYTES

6-40

Ap·119

Table 19. BMWRIT Procedure for the SDK·8S (cont.)

,
WRTB01:
LODSB
OUT
BMDATA, AL
LOOP
WRTB01
IN
AL, BMSTAT
TEST
AL, BUSYBT
JZ
SHORT WAITEX
MOV
CX,OFFFFH
WAITPO:
IN
AL, BMSTAT
TEST
AL,BUSYBT
LOOPNZ WAITPO
JCXZ
'CTRL99
WAITE: '
STATUS,AL
MOV
RET

;
;
;
;
;
;
;
;
;
;
;

STICK IN FIFO.
LOOP UNTIL FILL COUNT=O.
GET BMC STATUS
CHECK BUSY BIT.
NOT BUSY, ALREADY DONE.
JUST IN CASE. ..
POLLED WAIT MODE
GET STATUS
CHECK BUSY BIT
LOOP IF STILL BUSY
PROBABLY AN ERROR IF CX=O

; A = STATUS

SUMMARY

The BPK 72 is a subsystem in itself that should be
viewed as simply one more component on the
system bus: This component-level approach, plus
the inherent flexibility of the kit, provides the user
with maximum utility and functionality. By
understanding how each of the subsystem parts
fits together and by approaching the implementation of the kit in a methodical fashion as described in this note, the development of a working
system is facilitated.

The purpose of this application note is to provide
a more clear understanding of the functions and
characteristics of the BPK 72 one-megabit bubble
memory kit. This kit has been designed specifically to rei ieve the user of the design effort that
historically is associated with implementing a
bubble memory system, and to provide a simple
interface that is compatible with a broad range of
microprocessor systems.

APPENDIX A
SDK·86/BPK 72

" ~_ARDWARE INTERFACE
"

SDK·86 EXPANSION AREA

Top View User Hardware Section

Figure 10. Parts Layout
6-43

AP·119

BOO (J1-2)

,..

B02 (J1-6)
B03 (J1-8)
B04 (J1-10)
B05 (J1-12)
B06 (J1-14)
B07 (J1-16)

B,08 (J1-18)
B09 (J1-20)

Figure·11_ Data·Bus Buffer and Decoding Logic

- 05 (J8-32)
- 06 (J8-34)

SEGMENT
EXTRN
EXTRN
EXTNN
EXTRN
EXTRN
EXTRN
EXTRN
EXTRN
EXTRN
EXTRN
EXTRN
EXTRN
EXTRN
EXTRN
EXTRN
EXTRN
ENDS

PUBLIC
RAM:BYTE.SCRBUF:BYTE.MYBUF:BYTE
DEFADR:WORD,DEFBUB:BYTE.DEFNFC:BYTE,DEFENA:BYTE
DEFMOD:BYTE,DEFPAG:WORD,DEFBLK:WORD
BUFADR:WORD,BLKLEN:WORD,ENABLE:BYTE,PAGENO:WORD
EBLNUM:BYTE,NFC:BYTE,MODE:BYTE,STATUS:BYTE.BMCMD:BYTE
INBUF:BYTE,INBUFP:WORD,INBUFC:BYTE
INBUFA:WORD,INBUFL:BYTE
OUTBUF:BYTE,OUTBFP:WORD,OUTBFC:BYTE
OUTBFA:WORD,OUTBFL:BYTE
RDLEN:WORD,WRLEN:WORD
PROMPT:BYTE,LEVMSK:BYTE
BPADR:WORD,USERRG:WORD
POPREGS:WORD,PUSHREGS:WORD
USERBX:WORD,USERDS:WORD,USERBP;WORD,USERSS:WORD
USERSP:WORD,USERIP:WORD,USERCS:WORD,USERFL:WORD
USERPC:WORD

$INCLUDE(:Fl:BMC.EQU)

THESE ARE THE COMMAND EQUATES FOR BMDS

CWBR!!
CIZ
CRD
CWD_
CRS'
CRBR
CWBR
CWB
CRFS
CAB
CW'RS
CRB
CRCD
CFR
CPURG
CSR

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

lOR
llH
12H
13H
14H
15H
16H
17H

iSH

19H

lAH
lBH
lCR
lDH
lEH
lFH

, WRITE BOOT LOOP WITH 'MASK.
;INInALIZE
;READ
;WRITE
;READ SEEK
;READ BOOT LOOP REGISTER
;WRITE BOOT LOOP REGISTER
;WRITE BOOT LOOP
;READ FIFO STATUS
;ABORT
; WRITE SEEK'.
;READ BOOT LOOP
;READ CORRECTED DATA
; FIFO RESET
'
; MBM PURGE COMMAND.
;SOFTWARE RESET

):0
"C

.:..
....
CO

LOC

0001
0002
0004
0008
0010
0020
0040
0080

0001
0002
0004
0008
0010
0020
0040
0080

PAGE

BPK-72 DRIVER ROUTINES.

MCS-86 MACRO ASSEMBLER

=1
=1
=1
=1
=1
=1
;, 1
=1 =1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1,
=1
=1
=1
,,1

51
52
53 54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77 +1

SOURCE
; 1/0 PORT ADDRESSES.

BUBBLE MEHORY DEVICE STATUS PORT.
BUBBL& MEMORI DEVICE DATA PORT.

; STATUS WORD BITS

FIFOBT
PARERR
UNCERR
COR ERR
TIMERR
OPFAIL
OPDONE
BUSIBT

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

018
028
048
088
108
20H
408
808

FIRST BIT IS FIFO STATUS
SECOND BIT IS PARITY ERROR.
THIRD BIT IS UNCORRECTABLE ERROR BIT.
FOURT8 BIT IS CORRECTABLE ERROR BIT.
FIFTH BIT IS TIMING ERROR BIT.
OPERATION FAIL BIT.
OPERATION COMPLETE BIT.
BUSY BIT.

; ENABLE REG BITS

INTENA
IERENA
DMAEHA
RSVDl
WBLENA
RCDEHA
ICDENA
RSVD2
,EJECT

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

018
028
048
088
108
20H
408
80H

INTERRUPT NORMAL
INTERRUPT ERROR
DMA
WRITE BOOTLOOP
READ CORRECTED DATA
INTERNALLY CORRECTED DATA

BPK-72 DRIVER ROUTINES.

M S-86 MACRO ASSEMBLER
LINE
78
79
80
81
82
83
84
65
86
57
86
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126 +1

SOURCE
CODE

SEGMENT PUBLIC
ASSUME DS:DATA,CS:CODE,SS:STACK

;'~'*'11.'

•• "".1'6'1'1~~".""'*"".".""".1'11 I' .. '" a

•

BPK72 DRIVER routines
The routines 1n this module constitute the routines
needed to directly drive the BPK72 bubble memory
development board.
This module 1s designed to be self
contained, and may be called by ,ANY user procedures.
The procedures in this module are

BMCTRL - Perform non-data transfer-BHe operations.
BMREAD - Perform data read BHe operations.
BHWRIT - Perform data write SHe operations.
ZAPR~G

- Set internal registers to an acceptable value
Parameter passing

All parameters are passed to the BHe driver routines via
common (PUBLIC) variables. These variables are

BUFADR - The memory addre •• of the input/output buffer
a
to be used for data transfer operations.
,ENABLE - The enable byte to be passed to the BMC before a
every- operation.
I
PAGENO - The starting blook number to be passed to the
BHC before every operation,
(NOTE: This field
has no meaning for control operations).
I
BLKL&N - The number of pages to be transfered by the BHC.·
(NOTE: This field has no meaning for oontrol
a
operations) .
•
BBLNUM - The bubble seleot to be transfered to the BMC
before everv operation,(NOTE: This field has
a
no meaning for SOME control operations).
I
NFC
- The number of FSA ohannels passed to the BMC
before every operation, (NOTE: This field has
no meaning for SOME of the control operatioNs), a

;

For,a detailed definition of the ENABLE,PAGENO.BLKLEN,
BBLNUM. and NFC fields, refer to the BPK-12 USER MANUAL a
or the Bubble Memory Design Handbook.
•
a
,

;"'~""""'I"""""""""""'.""I"""""

.EJECT

•••••••

»
"U
.:..
....
CD

H 8-86 HACRO ASSEHBLER
LOC

OBJ

BPK-72 DRIVER ROUTINES.
LINE
127
128
129

130
131
132
133

PAGE

SOURCE
;

.•....••....•...••••..••.••••.
ENTRY POlNTS

.; ••••••••••

PUBLIC

ZAPREG.BHCTRL~BHWAIT.BHREAD.BMWRIT.BHWRTB

·FIRST SMC ·REGIST·ER TO USE IS BLOCK LENGTh
·STATUS woiiD· ERROR HASK
i.iGNORE .PARITY ERR. REV D OF BHC

M S-86 MACRO ASSEMBLER
LOC

OBJ

BPK-72 DRIVER ROUTINES.
LINE

PAGE

SOURCE
; ................... !i.~ ••••••••••

i~2

MODE BY-TE DEFINITION

1~3
1.~~
1~5
1~6
1 ~.7
1~8
1~9

0001
0002
0080

If interrupts are enabled in the MODE BYTE, they must also be selected
in the ENABLE BYTE for desired operation to occur·.

150
151
152153
15~

The bits in the. MODE BYTE sDecify the tYDe of the data transmission
TO USE, AND WHETHER TO PRINT STATUS AFTER EACH OPERATION.

INTMOD
DMAMOD
DBGMOD
$EJECT

EQU
EQU
EQU

01H

02H
80H

FIRST BIT IN MODE WORD IT INTERRUPT SELECT.
SECOND BIT IN MODE WORD IS DMA SELECT.
DEBUG BIT OF MODE WORD

:I>

.:..
....
CD

LOC

0000
0000
0003
0006
0008
OOOB
OOOD
0010
0012
0013

LINE

OBJ

E8D700
AOOO·OO
E6El
E80EOO
243C
AOOOOO
7502
F8
C3

0014
0014 A20000
0017 F9
0018 C3

, E

001.9

0019 E4El
001BA880
001D 740B
001F B9FFFF
0022
0022 E4El
0024 A880
0026 EOFA
0028 E3EA
002A
002A A20000
002D C3

155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
18'2
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197

SOURCE
; f.Ii . . . . . . . . . . ._• • t; • • • • • • • • • • • • • •

FUNCTION: BMCTRL - PERFORM BMC CONTROL OPERATIONS (NON-DATA TRANSFER).
INPUTS: NONE
OUTPUTS: A=STATUS;F/F(C=l: AN ERROR OCCURED).
CALLS: SNDREG,BMWAIT
DESTROYS: ALL
DESCRIPTION: THIS PROCEDURE IS USED TO PERFORM NON-DATA TRANSFER
BMC OPERATIONS.
;

BMCTRL:
CALL
MOV
OUT
CALL
AND
MOV
JNZ
CLC
RET

LOAD BHC REGISTERS.
GET COMMAND.
INITIATE COMMAND.
WAIT FOR COMPLETION.
DO WE HAVE AN ERROR?
LOAD STATUS INTO 'A' FO~ EXIT
ERROR, RETURN WITH fLAG SET.
CLEAR CARRY(ERROR FLAG)
AND RETURN

SNDREG
AL,BMCMD
BMSTAT,AL
BMWAIT
AL,STATER
AL,STATUS
SHORT CTRL99

·WE HAD AN ERROR, RETURN WITH ERROR FLAG(CARRY FLAG) SET.
THIS IS THE GENERAL ERROR EXIT

CTRL99:
MOV
STC
RET

STATUS,AL
SET ERROR FLAG (CARRY FLAG)
AND RETURN.

; ••••••••••••••• , •••••••••••• '1

FUNCTION: BMWAIT
INPUTS: NONE
OUTPUTS: STATUS IN A
CALLS: NOTHING
DESTROYS: A,F/F
DESCRIPTION: THIS PROCEDURE WILL WAIT UNTIL THE CURRENT BMC
OPERATION COMPLETES.
BMWAIT:
CHECK CURRENT STATUS (GOOD ONLY IF RAC=O AND BSY=O)

IN
TEST
JZ
199
200
MOV
201
. WAITPO:
202
IN
TEST
203
204
LOOPNZ
205
JCXZ
206
WAITEX:
207
MOV
RET
208
$EJECT
209 +1
19is

PAGE

BPK-72 DRIVER ROUTINES.

M S-86 MACRO ASSEMBLER

AL,BMSTAT
AL, BUSYBT
SHORT WAITEX
CX,OF.FFFH
AL,BMSTAT
AL,BUSYBT
WAITPO
CTRL99
STATUS,AL

GET BMC STATUS
CHECK BUSY BIT.
NOT.BUSY, ALREADY DONE.
JUST IN CASE •••
POLLED WAIT MODE
GET STATUS
CHECK BUSY BIT
LOOP IF STILL BUSI
PROBABLY AN ERROR IF CX=O
CORRECT STATUS AND RETURN.
A = STATUS

.:..
....

MCS-86 MACRO ASSEMBLER
LOC

OBJ

002E
o 02E 32CO
0030 A20000
0033' BBD9
0035 E8A200
0038 8s3EOOOO
o 03C BCD8
003E BECO
0040 AOOOOO
0043 E6El

cp
01'
01

0045
004B
0048
004A
004C
004E
0050

0052
0052
0054
0056
0058
005A
005B
005D
005F
005F
0061
0063
0065

B9FFFF
E~El

A880
E1FA
E3C4
8BCB

E4E 1
A801
7407
£4EO
AA
E2F5
EBBA
A88e
75EF
2BD9
EBAD

E
E
E

PAGE

BPK-72 DRIVER ROUTINES.
LINE

SOURCE

210
211
212
213
214
215
216
217
21B
219
220
221
222
223
2.24
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247

; •••••

• • • • • • , • • • • • I • • • • • Q* ••

FUNCTION: BHREAD
INPUTS: CX = NUMBER OF BYTES TO READ, ES SET TO DS
OUTPUTS: A = STATUS; F/F(C=l: ERROR OCCURED)
BX = NUMBER OF BYTES READ
CALLS: SNDREG
DESTROYS: ALL
DESCRIPTION: ALL PARAMETERS ARE PASSED THROUGH COMMON(PUBLIC)
VARIABLES( SEE MODULE HEADER).
MREAD:
XOR
MOV
MOV
CALL
MOV
MOV
MOV
MOV
OUT

AL,AL
STATUS,AL
BX,CX
SNDREG
DI,BUFADR
AX. DS
ES,AX
AL.BMCMD
BMSTAT.AL

MOV

CX.OFFFFH

IN
TEST
LOOPZ
JCXZ
MOV

AL.BMSTAT
AL,BUSYBT
BHRDl
CTRL99
CX.BX

A = 0
CLEAR STATUS.
SAVE BYTE COUNT FOR LOOP
SEND REGISTERS TO BMC.
SET UP DEST BFR PTR (IN EXTRA SEG)
SET EXTRA SEG FOR BYTE MOVE DEST
GET COMMAND
ISSUE IT.

BMRDl :
WAIT FOR BUSY. BUT NOT FOREVER
CX=O PROBABLY AN ERROR

READ LOOP
BMRD2 :

2~8

249
250
251
252
253
254
255
256 +1

IN
TEST
JZ
IN
STOSB
LOOP
JMP

AL.BMSTAT
AL, FIFOBT
SHORT BMRD3
AL,BMDATA
BMRD2
BMWAIT

TEST
JNZ
SUB
JMP

AL,BUSYBT
BMRD2
BX.CX
CTRL99

BMRD3 :

$EJECT

GET STATUS
FIFO EMPTY?
YEP, GO CHECK FOR BUSY.
NOPE, GET DATA
STORE IT
AND GO FOR MORE.
XFER DONE, WAIT FOR A GOOD STATUS
NOTHING IN FIFO, IS OP COMPLETE?
CHECK BUSY BIT
STILL BUSY, WAIT.
BX <- # OF BYTES XFERED

0067
0067
0069
006C,
006E
0070
0072
0075
0079
007C
007E
007E
0080
0082
0084
0086

32CO
A20000
8BD9
BOlD
E6El
£86500
8B360000
AOOOOO
E6El

E
E

E4El
A880
74FA
A801
74F6

0088,
0088 E4El
008A ABOl
008C '7407
OOBE AC
008F, E6EO
0091 E2F5
0093 EB84
0095
0095 ABBO
0097 75EF
0099 2BD9
o 09B E916FF

009E
009E
OOAO
00A3
00A5

32CO
A20000
8BD9
BOlD

PAGE

BPK-72 DRIVER ROUTINES.

M S-86 MACRO ASSEMBLER

258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284'
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
30B
309
310
311

SOURCE
;

.................•....•••.••..
FUNCTION: BMWRIT - WRITE BUBBLE MEMORY DATA,
INPUTS: CX = # OF BYTES TO WRITE.
OUTPUTS: A = STATUS; F/F(C=l:ERROR OCCURED), BX=# OF BYTES WRITTEN.
CALLS: SNDREG,BMWAIT.
DESTROYS: ALL.
DESCRIPTION: THIS PROCEDURE PERFORMS A BUBBLE MEMORY WRITE OPERATION.
AN ERROR, WILL OCCUR IF THE NUMBER OF BYTES GIVEN FOR THE
WRITE OPERATION EXCEED THE NUMBER THAT THE BMC EXPECTS
(DERIVED FROM COMMAND, BLOCK LENGTH AND, NUMBER OF FSA
CHANNELS), OR IF THE NUMBER OF BYTES IS LESS THAN THAT
WHICH THE BMC EXPECTS.

BMWRIT:
XOR
MOV
MOV
MOV
OUT
CALL
MOV
MOV
OUT

AL,AL
STATUS,AL
BX,CX
AL,CFR
BMSTAT.AL
SN'DREG
SI,BUFADR
AL,BMCMD
-BMSTAT,AL

IN
TEST
JZ
TEST
JZ

AL,BMSTAT
AL, BUSYBT
WRITOl
AL,FIFOBT
WRITO 1

A = 0
CLEAR STATUS
FIFO RESET
SEND REGISTERS TO BMC.
SET UP SRC BFR PTR (IN DATA SEG)
GET COMMAND
ISSUE IT.

KEEP STUFFING DATA INTO FIFO UNTIL DONE OR AN ERROR OCCURS.
(NOTE: BMC GOING NOT BUSY IS AN ERROR).
WRIT03:
IN
TEST
JZ
LODSB
OUT
LOOP
JMP

BMDATA,AL
WRIT03
BMWAIT

GET STAT'US
FIFO READY?
NO. WAIT FOR IT
YES, GET DATA FOR IT
GIVE IT TO BMC
LOOP UNTIL DONE.
XFER DONE, WAIT FOR A GOOD STATUS

TEST
JNZ
SUB
JMP

AL,BUSYBT
WRlT03
BX,CX
CTRL99

OK IF STI~L BUSY
BX <- # OF BYTES XFEHED
ERROR IF NOT BUSY AND CX NOT ZERO

AL, BMSTAT
AL,FIFOBT
WRIT04

WRIT04,

SPECIAL WRITE FOR HOOT LOOP AND BOOT LOOP REGCMNDS
BMWRTB:
XOR
MOV
MOV
MOV

AL,AL
Sl'ATUS,AL
BX, ex
AL,CFR

A = 0
CLEAR STATUS

LOC

OBJ

00A7 E6El
00A9 E82EOO
OOAC 8B360000

OOBO
OOBO
OOBl
00B3
00B5
00B8
OOBA

en
cJ,

-oJ

AC
E6EO
E2FB
AOOOOO
E6E 1
E95CFF

LINE

PAGE

BPK-72 DRIVER ROUTINES.

MCS-86 MACRO ASSEMBLER
SOURCE
OUT
CALL
MOV

312
313
314
315
316
317

31~

WRTB01: ,

319
320
321
322
323
324
325 +1

BMSTAT.AL
SNDREG
SI.BUFADR

FIFO RESET
SEND REGISTERS TO SMC.
SET UP SHC BFR PTR (IN DATA SEG)

FILL FIFO WITH 20140/41 BYTES
LODSB
O~T

LOOP
MOV
OUT
JMP

BMDATA,AL
WRTBOl
AL, BMCMD
BMSTAT,AL
BMWAIT

STICK IN FIFO.
LOOP UNTIL FILL COUNT=O.
SEND CI1ND

OOBD
OOBD
OOBE
OOBF
OOCO
00C3
00C7
00C8
OOCC
OOCE
OODI
00D3
o OD6
00D7
00D8
00D9

LINE

OBJ

9C
50
5~

BBOOOO
891EOOOO
43
891EOOOO
32CO
A20000
FECO
A20000
5B
56
9D
C3

E
E
E
E

PAGE

BPK-72 DRIVER ROUTINES.

M s-86 MACRO ASSEMBLER

326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353 +1

SOURCE
;

..............................
FUNCTION: ZAPREG - ZAP ALL INTERNAL REGISTERS.
INPUTS: NONE
OUTPUTS: NONE
CALLS: NOTHING
DESTROYS: NOTHING.
DESCRIPT ION: SET ALL INTERNAL REGISTERS EXCEPT 'ENABLE' TO AN
ACCEPTABLE VALUE. NOTE: AN ACCEPTABLE VALUE M~Y
OR MAY NOT BE THE ONE DESIRED AS A DEFAULT.

ZAPREG:
PUSHF
PUSH
PUSH
MOV
MOV
INC
HOV,
XOR
HOV
INC
MOV
POP
POP
POPF
RET
$EJECT

AX
BX
BX.O
PAGENO,BX
BX
BLKLEN.BX
AL,AL
BBLNUM.AL
AL
NFC.AL
BX
AX

SAVE FLAGS
SAVE REGISTERS
STARTING PAGE NUMBER

BLOCK LENGTH = 1
BUBBLE NUMBER = 0
# OF FSA CHANNELS
RESTORE REGISTERS.

1 (2 CHANNELS)

....l'
....
CQ

BPK-72 DRIVER

H S-86 MACRO ASSEHBLER
LOC

cp
(11
(0

OBJ

OODA
OODA
.OODH
OODC
DODD
OODE
ODED

9c
50
53
51
BOOB
E6El

00E2
00E6
00E8
OOEA
ODED
OOEF
OOFl
00'3

8B lEOOOO
8AC3
E6EO
AOOOOO
Bl04
D2EO
OAC7
E6EO

E
E

00F5 AOOOOO
00F8 E6EO

OOFA
OOFE
0100
0102
0105
0107
0109
010B

8B1EOOOO
8AC3
E6EO
AOOOOO
Bl03
D2EO
OAC7
E6,EO

354
355
356
357
'358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404

FUNCTION: SNDREG - FORHAT AND SEND INTERNAL REGISTERS TO BMC.
IN PUTS: NONE
OUTPUTS: NONE
DESTROYS: NOTHING.
DESCRIPTION: FORHAT ANO SEND ALL INTERNAL REGISTERS TO THE BHC.
SNDREG:
PUSHF
PUSh
PUSH
PUSH
HOV
ODT

AX
BX
CX
AL,REGl
BHSTAT,AL

SAVE REGISTERS
GET .IRST REGISTER ADDRESS.
SELECT IT.

CONSTRUCT AND SEND BLOCK LENGTH.
HOV
MOV
OUT
HOV
HOV
SHL
OR
DOT

BX.BLKLEN
AL,BL
BMDATA,AL
AL.NFC
CL,4
AL,CL
AL,BH
BHDATA,AL

HL =
A
GIVE
A

BLOCK LENGTH
BLOCK LENGTH LSB
IT TO BHe.
NUMBER OF .SA CHANNELS.

HERGE INTO BLOCK MSB
GIVE IT TO BHC.

SEND ENABLE BYTE.
HOV
OUT

AL,ENABLE
BHDATA,AL

BX,PAGENO
AL,BL
BMDATA,AL
AL,BBLNUH
CL,3
AL.CL
AL,BH
BHDATA,AL

RESTORE REGISTERS AND RETURN,
POP
POP
POP
POPF
RET
+1

.EJECT

cx
BX
AX

:...
....

GET ENABLE BYTE
GIVE IT TO BMC

CONSTRUCT AND SEND ADDRESS REGISTER.
HOV
HOV
OUT
MOV
HOV
SHL
OR
OUT

>
'U

HL = STARTING PAGE NUMBER
ADDRESS REGISTER LSB
A
GIVE IT TO BMC,
BUBBLE NUHBER
A
HERGE INTO PAGE NUHBER HSB.
GIVE IT TO BHC.

BPK-72 DRIVER ROUTINES.

M S-86 MACRO ASSEMBLER
LOC

BPK-72 DRIVER ROUTINES.

ASSEMBL~R

PAGE

XREt SYMB-OL. TABLE LISTING'

------ --;..--

NAME

' TUE

,? ?SE'G
B'BLNUM.
BL'kLEN.
'BMCHD' •
BMCTRL.
BMDATA '.
BMRD1' •
BMRD2 •
BMRD3 •
'BHRE'AD.
BMSTAK. '
BHS!A!.
BMWAlT.
BilwRIT.
BMWRTB.
BPADR
BUFADR.
BUSYBT.
CAB ,;
CFR •
CIZ •
CODE.
CORERR.
CPURG
CRB ';
CRBR. '
CRCD;
CRD' .'
CRFS.
CRS •
CSR .'
CTRL99.
CWB •
CWBR'.
CWBRH
CWD_.
CWRS.
DATA.
DBGHOD.
DEFADR.
DEFBLK.
DEFBUB;
DEFENA.
DEFMOD.
DEFNFC.
DEFPAG.,.
OHAENA.
DHAHO'D.
ENABLE.
FIFOBT.
ICDENA.

SEGMENT
V BYTE
V WORD
V BY'!E
L NEAR
NUMBER
L NEAR
L NEAR
L NEAR
L NEAR
L NEAR
NUMBER
i. NEAR
L NEAR
L NEAR
V WOliD
V WORD
NUMBER
NUHBER
NUHBER
NUMBER
SEGMENT
NUHBER
NUMBER
NUMBER
NUMBER
NUMBER
NUMBER
NUHBER
NUMBER
NUHBER
L NUR
NUHBER
NUHBER
NUHBER
NUHBER
NUMBER
SEGHENT
NUMBER
V WORD
V WORD
V BITE
V BYTE
V 'BYTE
V BYTE
V WORD
NUHBER
ilUMBSR
V BYTE
NUH'BER
' NUMBER

VALUE
OOOOH
OOO'OH
OOOOH
OOOOH
OOEOH
00~8H

0052H
005FH
002EH
OOOOH
00E18
0019H
0067H
009EH
OOOOH
OOOOH
0080H
0019H
001DH
0011H
00088
001EH,
001BH
0015H
DOlCH
0012H
00'18H
001~H

001FH
001411
0017H
0016H
0010'H
00'13H
001AH
0080H
OOOOH
OO'OOH
OOOOH
OOOOH
OOOOH,
OOOOH
OOOOH
OOO~II

0002H
OOOOH
0001H
'OO~OH

ATTRIBUTES, XREFS
SIZE=OOOO. PARA PUBLIC
EXTRN ,161 3~6 391
EXTRN 151 3~~ 372
EXTRN 161 167 229 279 322
CODE PUBLIC 131 , 1651
5~I 2~7 296 320 37~ 379 38~ 390 395
CODE 2331 236,
CO'DE 2~31 2~9 253
CODE 2~6, 2511
CODE' PUBLIC 131 2211
EXTRN 81
53' 168 197 202 230 23~ 2~4 276 280 282 292 312 323 368
CODE PUBLIC 131 169 )931 250 298 324
CODE PUBL'IC 131'2711
CODE PUBLic 131 3071
EXTRN 23'1
15# 226 278 31~
E~TRN
651 198 203 235 252 283 300
~3#
~7# 275 311
351
SIZE=0112" PARA PUBLIC
611

CODE' 172' 179# 205 237 255 303
~11
~UI

3~#

371
4~#

SIZE=OOOOH PARA PUBLIC
1531
EXTRN 13#
EXTRN 1~#
EXTRN 13#
EXTRN 13#
EXTRN 1~1
EXTRN 13#
EXTRN J~I
71#
1521
EXTRN 15# 383,
58# 2'~5 285 293
751

".....
~

~81
~51

111 28 79

BPK-72 DRIVER ReUTINES.

MCS-86' MACRO' ASSEMBLER

lERENA.
NUMBER
OCC2H
70"
V 'BYTE
INBUF •
cceCH EXTRN
171
INBUFA.
V weRD
CCOCH
EXTRN
18'
EXTRN'
INBUFC;
V BYTE
COCCH
17#
INBUFL.
V BYTE
CCCCH
EXTRN
18'
EXTRN
INBUFP.
V weRD
CCCCH
171
CCC1H
691
INTENA.
NUMBER
CCC'lH
lNTMeD.
NUMBER
'1511
221
EXTRH
LEVMSK.
V BYTE
CCCCH
CCCCH
EXTRN
V BYTE
MeDE.' •
16'
121
MYDUF •
Y BYTE
CCCCH
BXTRN
NFC'; •
EXTRN
V BYTE
COCCH
16',348 315
CPDeNE.
NUMBER
CC4CH
641
ePFAIL;
NUMBER
CC2CH
63'
CUTBFA.
V WDRD ,CCCCH
EXTRN
20"
DUTBFC.
Y' UTE
19#
"CCCCH EXTRN
QUTBtL.
Y BYTE
DDCCH
EXTRN
20'#
CDDCH
'
EXTRN
DUTBFP;
Y WDRD
19'
,Y BITE
'DUTBUF.
C'OCDH
EXTRH
191
v,weRD
'CDCDH ' EXTRN
PAGEHe.
15# 342 '388
59"
PARERR;
HUMBER
OCC2H
EXTRH
24#
CCCDH
PDPREGS
Y weRD
CQOOH 'EXTRH 22#
PRCMPT. • V "BYTE
,CCC,CH ,EITRN
PUSHREGS. 'V',IIDRD
24'
COCDH, EXTRN ,121
RAM •
V BYTE
RCDENA. ,.' 'NUMBER
DC2CH
74'
,v WO'RD
C'CCCH
EURN
211
ilDLEN
,REG'I.
HUMBER
CCCBH
137# 367
N'UMBER
RSVDl
OCC8H
721
RSV.D2 •
NUMBER
CCaCH
16#
121,CC,CCH
SCRBUF.
V BYTE
EXTRN
,SHDREG.
L NEAR
CCDAH: ceDE' 166 225 277 313 362#
- ,
SLZB=CCCCH PARA STACK
STACK- •
SEGM'ENT
-SUTER.
N-UMBBB
CC3CH
138# 170"
S'l'A'TUS.
V BYTE
CCCCH EXTRN
16' 171 180'20'1 223 273 30'9
NUMBER62#
T tHERR.
CCICH
C'CC4H
NUMBER
60'1
UNeERR.
_ CCCOH
,v WCRD
BITRN
25#
USERBP.,
CCCCH
EXTRN 25#
US'BRBX.
Y 1i0RD
USElics.
V WCRD
CCCCH
EXTRN
26#
BXTR'N
25;
USERIiS.
V WCRD
CCCOH
-26#
•
-V
liaRD
cccoli
BXTRN
USERFL.
'OCCOH
EXTRN
lISERIP.
V weRD
26#
US-ERPe.
occe-H
V WO'RD
EXTRN
27#
USERRG.
V weRD
OCCOH
EXTRN
23#
V ,weRD
USERSP-.
COCCH
EXTRN
26#
EXTRN
USBRSS'.
V weRD
CCOCH
25#
L-NEAR
CC,2AH
ceDE
IIA1T8X.
199 20'6#
L,NEAR
20'11 20'4
CC22H
CODE
llAITPe.
NUMBER
CC1CIt
IIBLENA.
73#
C-ODE
2811 284 286
WRITCI.
L NEAR
CC7EH
CC88H
ceDE
291# 297 30'1
WRITC~ •
L NEAR
CC95-H
WRITClf •
t NEAR
CCDE
294 299#
V weRD',
-CCCCH
WRLEN ,
211
EXTRN
'L NEAR
eCBCH
318# 321
'WRTBC1.
CCDE

PAGE

.:a.
.....

BPK-72 DRIVER ~OUTINES.

MCS-86 MACRO ASSEMBLER
NAME

ASSEMBLY COMPLETE. NO ERRORS FOUND

-Intel Corporation, hie., 1982

December 1982
ORDER NUMBER: 210300-001

6·64

intJ

Ap·127

INTRODUCTION
Intei has developed a ne~,
compr~hensive
power·fail circult,that
is incorporated
into allTM'
Intei Bubble
Board, Memo'ry'pro,
,'..
TM
,'"
,
"
dl,lcts: BPK 72 Bubble M~ory Prototype Kit, iSBX,
251 !'vIULTIMODULE
board, ,and the iSB~ 254
MULTIBUS® compatible board. The use of this circuitalso is, recommended for all cuslomer-l;\esigned bubble m~mory
boards. The overall perfo'rman~e enhancements offered by this ~ircuit include improved noise immunity a~d a factor-orfour reduction in the time required to shut down the bubble system.

Scope and Organization

In~ effortt~ focus'on implementation details, this application, note is organized;o that a reader can obtains~fficient information to implement a bubble design without an intimate working knowledge-of .the powerfail circuitry. However, for
,those interested, a complete detailed explllJla~ion of the integrated powerfail circuitry and the additional ellternal circuitry is
included. Appendix A contaips a technical disc~ssion of the effects of power los,S on,al'viagnetic Bubble Chip. In addition,
the previous circuit versions (Revision 0 and Revision 1), along with the present circuit, are completely documented and
compared in Appendix B.
' '
:~

Bubble Memory Operation and the Powerfail Function
, The power-fail circuitry is partially integrated into tWO oUhe five MBM support components, and additional requiredcir, cuitry is provided by external components. Historically, several evolutionary improvements have been made in the external
circuitry (see Table i) to, further reduce the risk. of data ,loss following ,an abrupt power, failure.
An essential feature of the bubble memory (MBM) is non-volatile, data storage. This non-volatility results from.-two permanentmagnets within the bubble device that p,roduce a,magnetic field'(bias field) that maintain the magnetic dgmains, or
bubbles (representing data) in the chip even when power isremoved. Th~ bUbbles,remaln statipnary in fixedpositions,until
the data is accessed. To move the bubbles, an in-plane rotating magnetic field is induced by pulsing 'two mutuallyPerpendicular coils surrounl;\ing the bubble chip. Special conductor lines .on the bubblt;: chips provide ,all the current related
'functions for reading and writing to the bubble device. A special support IC produces, current pulses (swap, relic;lte, and
generate) to perform these functions. A complete set o~ support circuits provides the necessary timing and waveforms to
precisely maneuver the bubbles to their desired positions. To prevent bubbles from moving t9 undesired positions, certain
precautions must be observed.
As power is applied or removed, the system must prevent any current transients in the coils or bubble function conductors.
If power is removed with the coils operating, the system must ensure that the coil currents are shut .down in an orderly
fashion to guarantee that the magnetic bubbles come to rest in st~ble; known positions. The powerfail reset circuit ensures
that the system is powered up in an orderly manner and serves to alert the' system should power faii. Both the power-up and

Table 1. Powerfail Reset Circuit Product History
Powerfail Circuit Revision Level,
,

Product
BPK 72

iSBX™·25'1' Board
.'

iSBX·251C Board

, , July 1979 ,thru
" August 1982
Rev. A thru Rev.G

..
N/A:

','

September 1982

,September 1981
thru October 1982

December i 980 tliru
" July 1982' " ,
"

.. , , N'ovember 1982
"

power-down sequences require a fmite period of time to complete their functions until the sequence is complete. To allow
proper execution of a power ,down sequence, the system voltages (+5V DC, +12V DC) must not decay to a level that
prevents operation oBhe powerfail circuitry and critical bubble memory functions~ In' most power supply designs, adequate
energy storage is available toprovide enough "hold time" to complete an orderly shutdown. However; ifdc power decays
too rapidly sufficient time may not exist for a proper shutdown and ·maY cause data to be lost Within the MBM.

System Description
The basic Intel Bubble Memory system consists of one 7110 magnetic bubble memory and five integrated support com·
ponents: a 7220-1 Bubble Memory Controller (BMC), a 7230 Current Pulse Generator (CPO), a 7242 Formatter-Sense
Amplifier (FSA), a 7250 Coil Predriver (CPD), and two 7254 quad drive transistor packages. These support circuits are interfaced to the MBM as shown in Figure I to form the basic one megabit (128K byte) system. The support components pro. vide all of the functions necessary for the,storage and retrieval of data Within the MBM. In addition, two of the support
components; the 7220-1 BMC and' the 7230 CPO, contain the integrated powerfail circuitry· that facilitates proper power-up
. and power-down' operations.

OVERVIEW -

POWER UP/DOWN OPERATION

A block diagram of the power fail circuitry for the bubble ,memory system is shown in Figure 2. The folloWing paragraphs
provide an operational overview of the integrated powerfail circuit and the external circuit requirements.
During a power up sequence, the 7230 holds PWR.FAILi* active (low) until both supplies are above the minimum required
level. The 7230 contains power supply monitors ( + 5V and + 12V) that determine when either supply falls below threshold
level and activate PWR.FAILI signal aCcordingly. On power-up, the PWR.FAILIsigna! is delayed an additiona!2 msec by
an external RC network (time delay I) to allow the 7220-1 substrate bias generator to fully charge. Following this delay, the
pOsitive-going transition on the 7220-1 PWR.FAILI input initiates a 7220-1 power-up sequence. .
.
.

The .RESET.OUTI signal was deSigned to remain active during the power-up sequence and theilto go inactive at the conclusion of the 50 p.S power-up sequence; However, the RESET.OUTI signal is indeterminate during executioIi of the 7220-1
powerctip sequence. A second external RC network (time delay 2) derived from PWR:FAILI ensures that RESET .OUTI is

COIL PAEDAIVER
7250

FORMAnERI

SENSE AMP

INTEL MAGNETICS
BUBBLE
MEMORY

7242

7110

• U /"

denoteS an inactive signal.

Figure 1. System Block Diagram
6-66

I SUPPLY I
L ___ ...l

I
__ --' _______________ JI

Figure 2. Block Diagram of Powerfail
held active (:50.8V) during this time. The RESET. OUT/ signal occassionally will remain in its active state following a
power-up sequence; accordingly the first command issued to the BMC during an initialization sequence must be an Abort
command to ensure that RESET. OUT/ is deactivated.
The power-up sequence is designed to power the system up in an orderly fashion and to prevent any current transients from
reaching the bubble device. The power-down sequence ensures that the coil drivers are shut down in the proper phase and
that the support circuits are reset. When power fails, the 7230 notifies the 7220-1 by asserting the PWR.FAIL! signal. The
.7220-1 responds to a negative transition on either the PWR.FAIL! input or the RESET/ input (external circuit revision
level dependent) and initiates a power-down sequence. If the coils are active (Le., bubbles propagating), the 7220-1 first terminates the coil drive control signals during the appropriate phase and then resets the support circuits by asserting the
RESET. OUT/ signal. The two system supply voltages must not decay faster than the specified rates to ensure the RESET/
input to all the support circuits (excluding the 7220-1) reaches an active level (less than 0.8 volts).

Powerfail Reset Circuit Solution
The external circuitry shown in Figure 3, in conjunction with the integrated circuitry contained in the 7230 and 7220-1, comprises thepowerfail circuit (revision 2). This design contains six additional components compared to previous powerfail circuits and includes an 8-pin DIP IC (TI 75463).
This revised circuit has been fully developed and tested by Intel and currently is incorporated in many bubble products.
Operational details are not required for the user to implement a custom design using the circuit in Figure 3. However, for
any bubble memory designs that cannot conform to the recommended powerfail circuit, a reader must understand the
system characteristics. and requirements prior to choosing an alternative design ..
The software implementation details to ensure correct powerfail circuit operation are shown in Figure 4. This routine
should be implemented as a routine for cold start operation (application of power) and warm start operation (a RESET/
pulse applied to the 7220-1 BMC). The voltage decay rates shown in Table 2 also cannot be exceeded.
The power-up routine is based on the typical power-up timing·shown in Figure 5. This timing does not assume that a system
reset has been incorporated into the powerfail circuit. If the hardware reset line is used, the user must ensure that the 7220-1
RESET/input is inactive before issuing the first Abort command. In addition, user software always must issue an Abort
command every time the system is reset.

1-----+---1 :>1---"1\1\,---......--==--._----<1..-----1
3.9K

NOTES:
1. ALL RESISTORS 1/4 WATT, 5% TOL
2. ALL CAPACITORS 10 VDC. 10% TOL
3. 01.02 ARE IN914 OR EQUIVALENT
4. ICl IN75463
5. Cx IS OPTIONAL-RECOMMENDED FOR EXTREMELY NOISY
POWER SUPPLY SITUATIONS
6. SYSTEM RESET MAY BE USED AS SHOWN PROVIDED OUTPUT
OF INVERTER IS OPEN COLLECTOR.

Figure 3. External Powerfail Circuit Solution

Table 2. Power Supply Decay Rate Specifications During Power·down or'Power Failure
Power Down/Powerfaii Decay Rate

GUARANTEE RESET.OUT/
HAS CHANGED TO
INACTIVE STATE

ALLOW TIME FOR

~~~:i~~~ ~~ CHARGE-....._ . ; . . . - , - _......

TO ~2.0VOLTS

Figure 4. Power·up Flowchart

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7230 POWER FAIL
TRIP THRESHOLO '(..

-----

VcclVoo - - - - - - - -

0-2.0V

PWR':;lt~

-..---1....____......,_......,__...

____

I I
I I

7220·1
PWR.FAIU
INPUT
PIN

I
I I
I I

",.. .... -

7220·1
RESET.OUTI
PIN

_ _ _ _ _ _ _ _~_...."'1........

NOTES:
1. 7220·1 INPUTS SHOULD NOT LEAD Vee BY GREATER THAN 0.5 VOLTS.
2. THE ABOVE SEQUENCE APPLIES ONLY IF THE SYSTEM RESET INPUT IS INACTIVE.

Figure 5. Power·up Timing for PowerfailReset Circuit (Revision 2)

6·70

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The worst case power-down timing sequence is also included in Figure 6. The total system power-down time varies according to whether the coils are active (i.e., rotating magnetic field is on) or inactive. The worst case power-down sequence is
guaranteed to be completed provided that the above voltage decay rates are met.

INTEGRATED POWERFAIL CIRCUIT CHARACTERISTICS
Introduction
The following section provides an in-depth look at the input and output characteristics of the support circuits that contain
the integrated powerfail circuitry. A complete understanding of these characteristics establishes the groundwork necessary
for the detailed description of the overall powerfail circuit operation that follows.

VCCIVOD

SEE MAXIMUM VCCfVOD
DECAY RATE SPECIFICATION
TABLE 2.

I
--1------------...,

RESET.OUTI - -.....
PIN

~r:~--- ---------~~--_-_-_-

SIG~~~ -----I-------------+!""______
.I

I
I

I-

c=".".-r__-;;.;-=-;.;;-:;,-= -

20"8---_

Figure 6. Power·down Timing for Powerfail Reset Circuit (Revision 2)

6-71

O.BV

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7230 PWR.FAILI OUTPUT
The 7230 Current Pulse Generator PWR.FAIL! output is responsible for indicating when the system supply voltages
(+5V, + 12V) reach correct operating levels. During power up, normal operation, and power down, an internal zener
reference comparator circuit within the 7230 senses both Vee and VDD and indicates when both levels are above approximately 92 percent of their nominal values. An active state on PWR.FAIL! indicates one or both de voltages are below this
threshold. The PWR.FAIL! output is an active-low, open-collector output requiring an external pullup resistor.
The PWR.FAIL! output is asserted (active low) as power is applied until the + 5V and + 12V supplies both reach approximately their 92 percent levels at which point the 7230 output transistor switches off to allow the PWR.FAIL! signal to rise
to an inactive level governed by an external RC network. The RC networks on the PWR.FAIL! line must hold the
PWR.FAIL! signal at an active level for at least 2.0 milliseconds'to guarantee adequate time for theBMC to power up. The
7230 PWR.FAIL! output then will remain inactive until one or both system voltages fall below the threshold.
The PWR.FAIL! output is not an internally latched signal. In other words, the output responds immediately to any transition through the threshold (trip point). The disadvantage to this excellent response capability is that the output will toggle
on transitions through the threshold. Systems should be designed to avoid an extremely noisy power supply or temporary
power loss that could cause the PWR.FAIL! signal to pulse for a very short duration.
During temporary power loss in Revision 0 and Revision I circuits, the PWR.FAIL! input to the 7220-1 could pulse below
VIH (2.5 volts) and initiate a power down sequence. The 7220-1 PWR.FAIL! input should remain active until the entire
power down sequence is completed (maximum 110 f,lsec). As detailed later in the 7220-1 PWR.FAIL! input description, if
the 7220-1 PWR.FAIL! input goes inactive during execution of a power down sequence, the sequence is immediatelyterminated. This type of termination can stop the drive field in the wrong phase and compromise bubble data. The solution is
to use the 7220-1 RESET! input to initiate a power down sequence rather than the 7220-1 PWR.FAIL! input.
Two important considerations in properly designing a powerfail circuit are I) the accuracy of threshold 'trip point of
the 7230 PWR.FAIL! output and 2) the behavior of this output at low voltages (below 2 volts).
'

The worst case threshold level that the 7230 PWR.FAIL! output will trip must be above the worst case operating
limits of the support circuits with an additional mar,gin to allow for an adequate period of time to complete a power
down sequence (worst case 110 microseconds for revision levell and 2 powerfail reset circuits). In the case of the 7230
CPG and the 7110 MBM, which both have a ±5OJo voltage specification for Vee and!or VDD, special powerfail
characteristics are applicable. As shown below, (Table 3) only critical bubble memory functions are guaranteed at
these supply values and not full memory operation.

Table 3. Powerfail Characteristics for 7230 Threshold Trip Point"
Typ.

*Powerfail characteristics apply to 7110 bubble memory data integrity only and not to full memory operation.

Second, the 7230 PWR.FAIL! output cannot be guaranteed active (low) until Vee reaches about 2.0 volts since the
output transistor is not operational until that point. As Vee is applied, the output is not active and will track (f6llow
within a few tenths of a volt) Vee until Vee reaches approximately 2.0 volts. At this point, the output transistor turns
on and the output goes active (low) and remains low until the system voltages both reach the threshold trip point as
described earlier. A similar response occurs as power is removed. The output transistor turns on and pulls the output
active (low) at the threshold point and remains turned on until Vee reaches approximately 2.0 volts where the output
goes inactive (transistor not operating). This operation must be controlled on power-up and depends on the rate of rise
of system voltages. This is because the PWR.FAIL! output is indirectly connected to the RESET! input of the support
circuits (7250 and 7242 and QI reference current switch) through two RC networks in Rev. 0 and Rev. 1 power-fail circuits. These inputs can rise, to as much as l.5V before the 7230 PWR.FAIL! .output turns on, which is above VIL max6-72

Ap·127

imum (O.SV) thus potentially enabling these circuits. This could result in current transients reaching the drive .coils or
bubble function conductors and move bubbles from their rest position resulting in data loss. Observing the rate of rise
specifications Protects against this possibility. The revision 2 powerfail circuit eliminates this problem and has no rate
of rise limitation.

7220·1 PWR.FAIL/INPUT
The 7220-1 PWR.FAILI input serves a dual function; a positive transition initiates a power-up sequence while a
negative transition initiates a power-down sequence of the bubble memory system. In order for the 7220-1 to become
fully functional an on chip back-bias generator must fully charge the 7220-1 substrate. Therefore, before any sequence
can be executed, including the po'wer-up sequence a time delay is required. An external RC delay on the PWR.FAIL/
input ensures this input is held low «O.SV) at least 2.0 milliseconds after Vee has reached the 7220-1 voltage
. specification range.
The power-up sequence is initiated once the RC network charges to a point where the.7220-1 recognizes a positive transition on the PWR.FAILI input. From a cold start (application of power), a positive transition must occur or the controller will not power-up correctly. Once the power-up sequence is completed, the RESET. OUT! isdes,igned to be
released, however, two possible exceptions exist. Fir'st, if the 7220-1 RESET/is held low during power-up, the 7220-1
internal power-up sequence will be completed however RESET. OUT/ will not be released until RESET/ is inactive.
Second, the 7220-l's internal RESET. OUT/ output transistor may remain turned on dependent upon the power-up
status ofcertain internal 7220-1 flip-flops. Because of this an ABORT command is always necessary to internally reset
these flip-flops, in turn ensuring release of the RESET,OUT/ output.
If the 7220-1 BMC does not receive a positive transition on PWR.FAIL/ during power-up, a power-up sequence is not
initiated. This leaves the controller in an unknown state. In, this unknown state the controller cannot communicate
properly with the data and control inputs. This can only occur as a result of:

I. "Brown out" '-' short duration of power failure in which power drops below specified levels.
2. ,Power~tip circuit faiiure - The PWR.FAILI pin ~ever reaches VIH (minimum) of 2.S volts.
The above conditions are resolved by ensuring a positive transition occurs on the PWR.FAIL/ input during power~up
and after brownout. It is 'necessary to execute a power-up sequence even though power to the system is only interrupted momentarily in order to restore the 7220-1 to the required internal state.
Once the PWR.FAIL/ positive transition has occured, this input should remain in the inactive state (VIH > 2.SV) as
long as power is applied to the system. If power is removed, it is the negative. transition of this input which intitiates
the second function, power down. The function can also be initiated with the RESET/input of the 7220-1.
An important consideration is how the 7220-1 PWR.FAIL/ input distinguishes between positive and negative transitions. On power up (positive transition), crossing the input threshold (typically 1.6V to 1.9V) a pulse is generated internally which resets the 7220-1 to a known state and initiates a power-up sequence. On power down (negative transition), crossing the input threshold (typically 1.3SV to 1.6V with the designed- in hysteresis) the signal initiates a powerdown sequence~ If a power-down sequence has been initiated, a positive transition must not inadvertently occur on the'
7220-1 PWR.FAJLI input prior to the power-down sequence completion. A positive transition internally generates a
reset pulse (to halt any current BMC activity) and initiates a power-up sequence effectively terminating a power down
sequence. The result is a possibility of shutting the coil drives down in the improper phase resulting in 'dataloss in the
MBM.
The PWR.FAIL/ input has built in hysteresis to reduce the susceptibility to mUltiple threshold crossings orglitching.
However, the values of hysteresis range from SO mV to 400 mY. To improve noise and power fluctuation immunity,
the use of PWR.FAIL/ input for initiating a power down sequence was abandoned in Revision 1 and Revision 2 circuit designs. The 7220-1 RESET/ input is used instead to initiate power down (see next section.)

Ap·127

7220·1 RESET/INPUT
The 7220 cl RESET! input, when asserted, will terminate any current BMC activity and initiate a RESET sequence
(identical to the sequence initiated by the PWR.FAIL! input going active). After the sequence is concluded, the
RESET. OUT! is activated to reset the MBM support circuitry. RESET. OUT! will remain active until RESET! is in·
active.
.
The RESET! input is a level sensitive latched input. This is a distinct advantage over the PWR.FAIL! input; where
any fluctuations of the input once the signal was recognized could possibly terminate the power down sequence. The
RESET! input is latched on the negative edge of the BMC clock and must be active low ( < .8V) for at least one clock
. period (250ns) to guarantee recognition.

7220·1 RESET.OUT/
The RESET. OUT! output has two functions: I) to guarantee the bubble memory system is disabled during power·up
and after power down of the bubble memory system and 2) to provide a pulse (reset) to the support circuits during nor·
mal operation. Since the RESET. OUT! output is an active low open drain, it requires an external pullup resistor to
Vee·
The support circuits controlled by RESET. OUT! are the 7250 Coil Predriver, the 7242 Formatter Sense Amplifier,
and a VMOS transistor switch which enables a reference current for the 7230. These circuits must be disabled during
the entire power·up sequence arid immediately following the conclusion of apower·down sequence to prevent any cur·
rent transients or extraneous enable pulses. Data loss is a possible consequence should the support circuits not remain
.disabled during power cycling.
During power up the RESET. OUT! signal can not be guaranteed active (low) until the 7220-1 power-up sequence has
executed. Therefore, external circuitry.must assure RESET. OUT! does not rise above V1L maximum (.8V) untiJ,50!4s
after initiation of the power-up sequence. By ensuring the RESET. OUT! is active during power-up it guarantees the
support circuits are reset to a known state. The 7220" IBMC is designed with the capability to reset the support circuits
during normal operations by pulsing the RESET. OUT!750 !,-S (3 clock periods). This pulse can occur as the result of
two user issued commands to the BMC: an INITIALIZE command and an MBM PURGE command.
The external RC network on the RESET. OUT! signal prevents the RESET.OUT! pulse from going active during its
750 !4s duration. In spite of an inability to reset the support circuits by issuing the proper command, correct operation
is guaranteed since the .support circuits only require a one time reset signal at power-on.

Additional Bubble Memory Controller Inputs
The 7220-1 has several additional inputs that could indirectly affect power up operation. It is important that the user
exercise caution and adhere to all requirements to ensure proper power-up operations. The following outlines those requirements.

ClK (CLOCK)

The CLK input of the 7220-1 must be present when the positive power up transition occurs at the 7220-1 PWR.FAIL!
input. This requirement allows the BMC to properly execute a power-up sequence. The input requirements are a
precise 4MHz (±.IO/O) with a 50 percent duty cycle (±5OJo).

DACKI (DATA ACKNOWLEDGE)

The DACK! input is normally used in conjunction with an INTEL DMA controller chip (8257 or 8237) which
automatically provides drive for this input. However, if DMA is not used a 5.1K pullup resistor to Vee is required.
This requirement prevents erratic BMC operation.
6-74

Ap·127

WAITI

The WAIT / input must also be guaranteed inactive through an external 5.IK pullup resistor. It is designed to be used
in parallel controller applications to maintain synchronization between controllers should an error be detected in one
during a data transfer.

CS/, ROI, WRI, AO, 00·08

These inputs require no special considerations other than to observe the VIH minimum specification. This specification prevents an incorrect power-up sequence execution.

ENERGY STORAGE REQUIREMENTS
The data integrity and non-volatility of the MBM during power down operations is guaranteed by design provided the
voltage decay rates specifications for both Vee and VDD are observed. Most commercially available power supplies
provide enough energy storage to fulfill these requirements. However, some applications may exist where the bubble
memory could suddenly become disconnected from the dc supply; a case where the power supply energy storage is not
of value. In these special applications, the local onboard capacitance must meet the hold up time requirement.
The worst case onboard capacitance values can be determined according to the following equation:
Qmax
V min

I max .::IT max
.::lVmin

A worst case calculation must include the following considerations: I) If any additional circuitry exists on the pc board
that uses the same power supplies, the additional current drain must be accounted for and 2) the worst case (minimum)
threshold trip point of the 7230 is used.
The capacitance required on a pc board containing one / megabit bubble memory system is calculated as follows:
366 x 10 -3 amp x (110 x 10 -6 sec)

381 x 10 -3 amp x (110 x 10 -6 sec)
----------~~~----~--~
0.01
x 12 volts

Supplemental Powerfail Sensing
In many systems, additional signals are available that provide advanced warning of an imminent power failure or the
existence of an abnormal condition prior to actual loss of dc power (e.g., AC powerfail sensing, AC or DC overvoltage, ambient over/under temperature). These signals are easily incorporated into the powerfail circuit design via
an open-collector gate or inverter connected to the PWR.FAIL/ signal bus.
The advantage, of utilizing these signals is the bubble memory system can complete a power down sequence prior to
losing dc power. However, local dc powerfail sensing is always required due to the possibility of local dc power loss
'
without the loss of AC power.

Noise Effects of Powerfail Circuit Operation
The 7230's powerfail voltage monitoring function is implemented internally with two independent, 10gically-OR'ed
voltage comparators. The comparators respond quickly to a sudden loss of Vee or VDD and therefore can respond to
noise transients on the power supply lines that cross the comparator switching threshold. As much as 100 mV of noise

6·75

inter

AP·127

from coil drive switching is not uncommon. Note that the operating power supply tolerance for all INTEL Bubble
Memory products is ±51l,7o including up to 50 mV of noise on the power supply lines. This tolerance should not be confused with the operation of the powerfail circuit beyond the normal operating range during power-down operation:
To minimize "nuisance" activation of the PWR.FAILI signal bus, ample high frequency decoupling on the 7230's
Vee and VDD pins should be provided. Typically, 0.01 JLF to 0.1 JLF ceramic disk or mica capacitors are sufficient.
Another source of unwanted powerfail circuit activation is noise that is coupled directly onto the PWR.FAILI signal
bus. This noise is minimized through good printed circuit layout practices and, if required, by the inclusion of a small
capacitor directly on the PWR.FAILI bus. This capacitor slightly increases the power-down time and should be kept
as small as possible (0.01 JLF maximum).

APPENDIX A

TECHNICAL DISCUSSION OF POWER LOSS EFFECT ON 7110
The effects of power loss on an MBM are best understood by describing the way in which the device functions and the
way in which it can lose data.
A magnetic bubble memory device (See Figure 7) consists of a bubble memory chip, two mutually-perpendicular coils,
two permanent magnets, and a shield to provide protection from interference by external magnetic fields. The two
permanent magnets produce an external magnetic field (bias field) that maintains the magnetic domains, or bubbles,
in the chip even when power is removed. To move the bubbles, an in-plane rotating magnetic field is induced by pulsing the two mutually-perpendicular coils.

Figure 7. Device Break·down
6-76

BIAS
MAGNET

-;//
-------7~7/==:j/
LOWER
BIAS
MAGNET

Ap·127

The bubble memory chip itself consists of a thin magnetic garnet crystal film grown on a non-magnetic gadoliniumgallium-garnet substrate. This thin film possesses a property that magnetic moments associated with each atom in the
single crystal structure have only two p()ssible directions: an upward or downward direction perpendicular to the plane
of the film. This constraint in direction results in only two conditions of magnetization (see Figure 8). These magnetic
moments tend to group themselves together into magnetic domains, The size and shape of the domains are determined
primarily by a balancing of several forces that minimize the sum of magnetic energy.
Without an external field, the film surface area of upward domains is equal to :that of downward domains and there is no
net magnetic field within the plane of film. Application of an external magnetic field perpendicular to the film causes do- .
mains to'line up in the direction of the field. As the external field is increased,. the downward domains enlarge while the opposing (upward) domains shrink until they finally are reduced to a cylindrical shape, This microscopic magnetized cylinder
opposing the externally applied field is a magnetic bubble. Within the magnetic film, the presence of a magnetic bubble
represents a binary one and the absence of a magnetic bubble represents a Qiriary zero.
The memory function is provided by the bubble. However, an organized means is needed to propagate the bubbles
along certain paths and to provide storage sites. A soft ferromagnetic material (permalloy) is deposited on the thin
garnet film in C-shaped patterns. These patterns are arranged to form shift-register like loops that provide the means
to store and move bubbles. Each pattern is magnetized according to the rotating magnetic field, and the polarity of
each pattern changes instantaneously as the rotating magnetic field vector changes. The rotating field is generated by
driving the X and Y coils with triangular-waveform currents, one lagging the other by 90° in phase. A magnetic bubble
propagates from one storage site (permalloy pattern) to the next for every 360 ° of rotation of the rotating field. Each
storage site has a preferred position (home) for the bubble to reside corresponding to zero degrees of the rotating
.
magnetic field. All bubbles start, stop and are stored in this position.
In the event of power failure, it is important thaUhe rotating magnetic field is shut down in the proper phase (Le., 0°).
If an orderly shut down is not complete, the rotating field may be shut down in an improper phase that causes bubbles

to stop in an unstable position within the storage loops. When this type of stoppage occurs, the bubbles either will
come to rest in another, but incorrect, stable position or, will leave their original storage loop (possibly contaminating
valid data in another storage loop).
As power is applied, it.also is important that the rotating magnetic field does not move (i.e., current transients must be
prevented from reaching the coils). This function also is provided via the powerfail circuitry. Thus, the purpose of the
powerfail circuitry is twofold 1) to prevent a,ny current transients from reaching the X-Y coils or bubble function:
generators and 2) to halt the coils in proper phase should power fail.

6-77

intJ

AP:127

EPITAXIAL
.
'+_---SINGLE·CRYSTAL THIN
FILM (GARNET)

WITHOUT EXTERNAL FIELD
, APPLIED

MAGNETIC DOMAINS SHRINK
AS EXTERNAL FIELD IS
APPLIED UNTIL DOMAIN
IS CYLINDRICAL IN
SHAPE (BUBBLE)

HEXTERNAL

Figure 8. Device Magnetization

6·78

Ap·127

APPENDIX B
DETAIL POWER CIRCUIT DESCRIPTION
As discussed in the Introduction, the powerfail reset circuit actually consists of two portions - an integrated section
and several additional external components. The degree to which external disturbances (noise, power fluctuations) influepce system performance depends heavily on the system environment and configuration. Consequently, the reliable
analysis of their effect Qn system performance is difficult and generally is best accomplished by measurement. In this
Appendix, e/!.ch revision level of the powerfail reset circuit is detailed. Several timing diagrams based on measurement
and computer simulation also are included.

Powerfail
Summary

~eset

Circuit - Revision 0

The overall performance of the powerfail reset circuit (revision 0) is adequate provided that a specific set of conditions
is observed. The requirements are summarized below (Table 4). Noise is also a concern. System generated noise is
typically low level imd can usually be neglected in portions of the circuit where the signal levels are, high. Often,
however, bubble systems generate significant levels of noise i.n a system where signal levels are low. Even low-level
noise !=an degrade overall bubble memory system performance.·
.
Table 4. Power Supply Requirements for Powerfail Reset Circuit (Revision 0)
Vee
(volts/msec)

Power-Up Voltage
Rate of Rise
Pow~r-Down/Power

Noise, power fluctuations, and a rapid decay of voltage are the primary contributors to the incorrect operation of the
first powerfaiI reset circuit (revision level 0). Since noise and power fluctuations are unavoidable in most practical
systems, techniques for minimizing these effects were developed for subsequent circuits. Notethat no .bubble memory
is immune to extremely abrupt removal Qf dc power. All bubble memory systems require a minimal amount of time to
effect an orderly shutdown in order to maintain data integrity.
.
Subsequent circuit designs have been implemented to minimize system requirements by reducing the overhead required to power-down the bubble system.
The most serious fault of any powerfail reset circuit is where bubble memory data integrity is jeopardized. The first
powerfail res~t circuit design (revision 0) could not prevent data loss when:
.
.
1) Power was removed too rapidly for the system to ensure proper p~wer-down.

2) Power .was applied too slowly.
3) Multiple t\lreshold crossings or "glitches" occured on the 7220-1 PWR.FAILI input while the coils were active.
The first two conditions can be easily preverited by following the requirements shown in Table 4. The third condition
was difficult to reliably prevent and was the motivation. for the revisiori of the circuit.

intJ

Ap·127

Power·up
When power initially is applied to the system (Figure 9), the PWR.FAILI signal is designed to be asserted by the 7230
CPO until both Vee and V DD reach approximately 92 percent of their nominal values. Referring to Figures 9 and 10,
the 7230 internal PWR.FAILI output transistor cannot be guaranteed operational until Vee reaches approximately
2.0 volts. During this indeterminate state of the output transistor, the floating output lags Vee by approximately 0.7
volts. Therefore, the RC networks on the PWR.FAILI signal line (RI/CI and R2/C2) begin charging immediately
after power is applied. They continue to charge until the 7230 PWR.FAILIoutput transistor turns on. The 7230
PWR.FAILI output goes inactive (transistor off) when both supplies.have reached the power-fail trip point. Since the
RESETI input of the 7242 FSA and the 7250 CPD are tied via the RICIIR2C2 network to 7230 PWR.FAILI output,
these support circuits potentially could be enabled if the 7230PWR.FAILI output were allowed torise above VIL (0.8
volts). A current transient then could activate the MBM coils or bubble function conductors and cause bubbles to
move to an unstable position. Note that a slow power-on ramp would be the only condition that could prematurely
enable the support circuits.
Once Vee reaches approximately 2.0 volts, the PWR.FAILI output transistor turns on to pull the PWR.FAILI signal
low until both Vee and V DD reach the powerfail trip point. When the trip point is reached, the output transistor is
turned-off and the PWR.FAILI signal is allowed to rise to the inactive level. The RC networks continue to hold the
PWR.FAILI signal at an active level for at least 2.0 milliseconds after Vee and V DD have reached the trip point level.
The RC delay ensures adequate time for the 7220-1 BMC's substrate. bias generator to become fully operational and
fully charge the 7220-1 substrate to its operational bias voltage. At some time before the PWR.FAILI signal reaches
the 7220cI VIH (maximum) of 2.5 volts, the 7220-1 power-on initialization sequ·ence starts: Uplo this point, the 7220-1
is in an indeterminate state and the RESET. OUTI signal, which is derived from the PWR.FAILI signal should be active. The behavior of the RESET.OUTI signal, however, is similar to the 7230 PWR.FAILI output at low Vee (below
approximately 2.0 volts). As Vee is slowly applied to thesystem,the RESET.OUTI output transistor initially is inactive and the pullup resistor forces this output to follow 7220-1 PWR.FAIL input. Once Vee reaches approximately 1.8
volts, the output transistor should turn on (RESET .OUTI active) and remain active until completion of the power up
sequence. During the inactive period, the RESET.OUTI signal is capable of reaching the inactive level and potentially
enabling the support circuits prematurely.
Vc~ '.
Vee

Vee

VO D

R1
12K

PWR. F A 1 L l t - - - - - - - -......- - - - _ - - - ' i P W R . F A I L I

Figure 9. Revision 0 Circuit
6-80

7220·1

RESET .OUT I

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7230 POWERFAIL
TRIP THRESHOLD

0·2.0V
7230/7220·1 PWR.FAIU
PIN

!
I

.'50J.lS~

0·2.0V
7220·1 RESET.OUTI
PIN

Power-up Timing
·VCC OR VDD. WHICHEVER IS LAST TO CROSS POWERFAIL TRIP THRESHOLD.

-- -

723~~'rr~~AIU _ _ _......

...

723on220-1 PWR.FAILJ~
PIN
.

,,
I

---

--_-_-_-_-.;0~.8~V

_ _ _ _ _ _ _ _ _ _ _ __

1_
110..---l
~ (MAXIMUMI~I

I
,I

:
7220.1 RESET.OUTI
PIN

----+!---__:f-------...
,
,
,

- - - - - - - - - - - O.BV

Power·down Timing
·VCC OR VDD. WHICHEVER IS FIRST TO CRoss POWERFAIL TRIP THRESHOLD.

Figure 10. Power-up/Power·down Timing (Revision 0)

6·81

Ap·127

At the completion of the power-on initializatiOn sequence, the 7220-1's internal RESET.OUT/output transistor
should be allowed to turn off. However, depending on the power-up state of certain internal 7220-1 flip-flops, this
output may remain active. An Abort command is capable of internally resetting these flip-flops and releasing the
RESET. OUT! output to allow it to rise to the inactive leveL as determined by the R2IC2 delay network. When
RESET. OUT! reaches its inactive level, the 7242 FSA and 7250 CPD RESET! lines are deactivated and 7230 current
. reference switch Ql is turned on. The 7242ENABLE.A! line, which is' controlled by the 7220-1, may now be activated; when active, this line enables the 7230 CS! and 7250 CS! (chip select) lines. The system now is fully opera c
tional and ready to execute an Initialize command (provided the Abort command had been issued).

Power·down Operation
If either Vee or VDD falls below the 7230 powerfail trip level, the internal PWR.FAILI signal in the 7230 is asserted
immediately. However, due to the charge on capacitor Cl in the power-up delay network, the PWR.FAIL! signal is
prevented from reaching the active low level until Cl discharges to VIL (maximum 0.8V).

When the PWR.FAIL! signal level reaches the logic low-level threshold of the 7220-1 's PWR.FAIL! input, an internal power-down sequence is initiated within the 7220-1. As discussed earlier in the 7220-1 PWR.FAIL! input descrip. tion, the 7220-1 PWR.FAIL! input cannot tolerate any positive threshold crossings during the powercdown sequence.
If a positive transition should occur; a power-up sequence will be initiated taking precedence over the power-down sequence currently in progress, and this unorderly shutdown could result in the loss of data.
The execution time of 7220-1 power-down sequence varies according to whether the coils are active (i.e., rotating
magnetic field is on) or inactive. If the rotating field is off,.the power down sequence is completed in approximately 10
microseconds. If the rotating field is on and a swap operation has not been initiated, the worst-case power-down time
is increased to 26 microseconds; if a swap operation has been initiated, the power-down time sequence requires a maximum of 110 microseconds. The power-down time is shown in ,Figure 10. Note that the total system power-down time,
since the operation is not complete until the RESET. OUT! signal line is asserted, is the sum of the 7220-1 's internal
power-down sequence time .and the discharge times for capacitors Cl and C2. To ensure proper operation of the
bubble system for data integrity during power-down operations, the power supply maximum decay rates must be
observed.

Powerfail Reset Circuit -

Revision 1

Summary
The powerfail reset circuit (revision 1) was designed to reduce the requirements placed on the revision 0 powerfail reset
circuit and to further reduce the risk of data loss during power-up!down operation. Specifically, the improvements
realized were:
1. The possibility of data loss was eliminated provided that the circuit was operated within voltage decay rates
specifications.
2. Power-down time was shortened to reduce the energy storage requirements.
The power supply requirements (shown in Table 5) were relaxed with this implementation, which reduces the system
requirements and the possibility of data loss.

Power·up
The power-up operation of the circuit shown in Figure 11 is unchanged from the power-up operation of the revision 0
circuit. The characteristics associated with the operation of the powerfail reset circuit below approximately 2.0 volts
were not resolved with this circuit solution. If the voltage rise time specifications were not observed, the support cir.cuits could have been enabled prematurely and would allow current transients to reach the drive coils or bubble function conductors (resulting in data loss).
.

6-82

AP-127

Table 5. Power Supply Requirements for Powerfail Reset Circuit (Revision 1)
Vee
(volts/msec)

Power·Up Voltage
Rate of Rise

0.12

None

Power·Down/Power Failure
Deeay Rate
J

Figure 11. Revision 1 Circuit

Power-down
The simple modifications implemented in the external powerfail circuit (revision I) greatly reduced the overall powerdown operation timing (See Figure 12). This modification made use of the 7220-1 RESET I input to initiate a powerdown sequence instead of the 7220-1 PWR.FAILI input by effectively isolating the 7230 PWR.FAILI signal from
delay capacitor CI during power-down operations (eliminating an initial capacitor discharge delay). The 7220-1 BMC
initiates ali. internal power-down sequence whenever its RESET I input goes active, identical to the negative transition
of the 7220-1 PWR.FAILI input. The difference between these two 7220-1 input signals is that the RESETI input is
latched and does not recognize a low-to-high transition and power-up therefore must be initiated by the positive transition of the 7220-1 PWR.FAILI input. With this circuit, the power-up operation timing was unaltered, and the
power-down operation timing was reduced from approximately 500 microseconds in the revision 0 powerfail circuit to
approximately 200 microseconds in the revision 1 powerfail circuit.

6·83

Ap·127

The primary reason for further refining this approach was the.increased possibility for a "communication lockout"
by the 7220-1. "Communication lockout" resulted when power was temporarily lost from the system. Specifically, the
following two conditions were responsible for the "communication lockout":
1) The 7220-1 RESET/ input was activated low due to power loss (minimum pulse width must be 250 nanoseconds to
ensure that it is latched) and initiated a power-down sequence.
2) The 7220-1 PWR.FAILI discharged but not below the inactive state (0.8 to 2.5 volts, typically 1.5 volts), before
power was restored. A power-up sequence could not be initiated to reset the BMC to a known state and communication is "locked out."

VCCIVOD .........

SEE MAXIMUM VccNoo
DECAY RATE SPECIFICATION
TABLE 5

,,
,,I

7220·1 RESETI
(POWERFAIUINPUT
BUS)

R~~~~~i,
....----~-------------,
SWITCH

110""
(MAXIMUM)----....·~

------I~-------------------.....-------------------,

RESET/'

-----11--------------+..+

~-----~-t--======
95,s

,
,

,
I

,
,

"....1------------:-. 200,_. --------~___i.~1

Figure 12. Power·down Timing (Revision 1)
6-84

O.BV

AP·127

Even if the circuit is operated within the voltage decay rate specifications, this inconvenience is still possible; the only
solution is to pulse the 7220-1 PWR.FAIL/ input long enough to discharge CI to a worst case value ofO.S volt either
by power cycling or external control. This user inconvenience and special system requirement led to the development
of the next powerfail reset circuit.
I

Powerfail Reset Circuit - Revision 2
The powerfail reset circuit (revision 2) was developed to eliminate the possibility of data loss during power-up and
power-down operation provided the power supply requirements are observed. The following paragraphs describe the
principals of operation of the powerfail reset circuit. As power is applied or removed, several different signal value
combinations are possible which complicate the analysis of this circuit. For the sake of simplicity, a general overview
of a typical case is included rather than a detailed representation of each case. Throughout this discussion it is helpful
for the reader to refer to the schematic diagram (Figure 3) and the timing diagrams (Figure 5 and 6).

Power·up
The overall circuit operation is complicated by the additional component, IC1..The power-up operation of the revision 2 circuit is very similar to previous circuits, however, the possibility of prematurely enabling the support components is eliminated. Diodes D1, D2 and resistor R5 serve to prevent capacitor C2 from charging beyond a level
(O.SV) that could potentially deactivate the RESET/ signal bus to the 7242 FSA, the 7250 CPD and the VMOS transistor switch. Resistor R5 is chosen so that as Vee is applied, diodes DI and D2 will be forward biased and provide
sufficient voltage drop to prevent capacitor C2 from charging above O.SV.
Once the 7220-1 power-up sequence is complete or the first Abort command is received, the 7220-1 RESET.OUT/ is.
deactivated and capacitor C2 is allowed to fully charge. When the RESET/signal bus reaches an inactive state the
power-tip sequence is complete and the system is prepared to accept an Initialize command (provided the Abort command has been issued).
Power~down

The power-down operation of the external powerfail reset circuit (revision 2) is very similar to revision I. The fundamental difference is the ability to maintain a charge on capacitor CI throughout the-7220-1 power-down sequence.
This eliminates any glitch sensitivity or iqcorrect circuit operation during momentary power loss. The 7220-1 BMC initiates an internal power-down sequence whenever its RESET/ input goes active. The 7220-1 RESET.OUT/ signal is
gated through ICI and remains inactive during this time period preventing capacitor CI from discharging. At the completion of the 7220-1 power-down sequence RESET .OUT/ signal is pulled low which causes both of the ICI OR gate
outputs to go low. The current sinking capability of these outputs act to quickly discharge· capacitors C 1 and C2 and
complete the power_down sequence.

INTEL CORPORATION. 1982

OCTOBER 1983
ORDER NUMBER: 210849·002

6-86

AP-150

8085 TO BPK 72 INTERFACE
INTRODUCTION
Bubble Memory is quickly emerging as the preferred high density storage medium for a variety of microprocessor
applications. Considering'their size and reliability, Bubble Memory allows the designer to utilize the advantages of
microprocessors in environments that were not possible using other high density peripheral storage technologies.
Aside from portable or rugged environmental applications, bubbles also open up new design possibilities for desk-top
terminal applications. Some of the benefits that can be realized from the implementation of Bubble Storage are
increased flexibility, reduced maintenance, and non-volatility.
'
In addition to a one megabit Bubble Memory, Intel magnetics also manufactures a complete family· of integratedsupport circuits that simplify the task of designing with Bubble Memory. The family of support circuits provides an
easy-to-use microprocessor. interface via a single VLSI component, the Bubble Memory Controller (BMC). The
remaining support circuits are controlled by the Bubble Memory Controller allowing the designer total freedom from
the control signals associated with Bubble Memory technology.
'
At the component level, the BPK 72 (Bubble Memory Prototype Kit) provides the best opportunity to discover the
potential of bubble storage. The BPK 72 comes complete with all the hardware and documentation necessary to prototype a one megabit (128K-bytes) Bubble Memory System. The BPK 72.is completely assembled and tested leaving the
designer with the simple task of interfacing to a host processor.
This application note demonstrates how little effort is required to interface a BPK 72 with an 8085 microprocessor.
/ The first four sections, "Introduction, BPK 72 Overview, Constructing the Hardware Interface, Implementing the
8085/BPK 72 Software Driver," and Appendix A (software listing) provide all the information necessary to interface
a BPK 72 with an 8085 microprocessor based system. The remaining chapters describe in detail the hardware and
software considerations involved with designing and implementing a Bubble Memory Interface.
A set of generalized flowcharts describing the software driver may also be found in Appendix A to facilitate the task of
interfacing with other microprocessors.

BPK 72 OVERVIEW
The BPK 72 consists of a completely assembled and tested 10cmx lOcm printed circuit board containing a one megabit
Bubble Memory and the complete family of integrated support circuits.
A block diagram ofthe BPK 72 is presented in Figure 1. It illustrates the key components in a one megabit, 128K-byte
Bubble Memory System.

8GSfUS

I
I

7220
BUBBLE MEMORY CONTROLLER

INlEl .....GNETlC$
BUBBLE

72U

MUiORT
7110

.7230

CURR(NTPUL5E
QENEI\ATOA

Figure 1. Block Diagram of theBPK 72

6·87

DRIVE

Ap·150

The 7110 Bubble Memory Module is supported by the following integrated circuits:
7220-1 Bubble Memory Controller (BMC)
The 7220-1 provides a convenient microprocessor interface arid generates' the timing signals necessary for the
.
proper operation of the remainin& support Circuitr~. ' .
7242 Formatter Sense Amplifier (FSA)
The 7242 is responsible for detecting arid en~blingthe generation of magnetic bubbles within the 7110,The
7242 also performs data formatting tasks and the option of automatic error detection and correction.
7250 Coil Predriver and 7254 Drive Transistors
The 7250 and two 7254s supply the drive currents for the rotating magnetic field that move the magnetic
bubbles within the 7110 Bubble Memory Module.
7230 Current Pulse Generator (CPG)
The 7230 generates a set of waveforms necessary to input and output data from the ?110.

CONSTRUCTING THE HARDWARE INTERFACE
The hardware necessary to.interface a BPK n with an 8085 microprocessor consists of a few simple connections to
the system bus and the addition of only three integrated circuits; 7406-hexinverter (open coJlector), 7430~eight
input nand gate, and an 8284A-Intel clock generator.
.
A schematic is presented in Figure 2 of the interface logic between aBPKn and the demultiplexed bus from an 8085
microprocessor.
The interface uses the eight input nand gate to enable chip-select on the BPK n when an I/O instruction is executed
at ports OFEH ("H" designates hexadecimal notation) or OFFH. The address lineA8 from the microprocessor bus is
connected to AO on the BPK n to select one of two internal ports. Ifthe ports OFEH and OFFH are not available,
simply connectA8 to the input ofthe nand gate and move'a higher order address line (A9-AI5) toAO on the BPK n.
In the event that the I/O addresses are changed, the user must enter the new port locations into the software driver
(see Appendix A). The I/O port locations are initialized as equates at the beginning of the program. All system
dependent variables have been parameterized whenever possible.
.
The designer has the option of memory mapping the BPK 72 or utilizing 2 of the 256 I/O ports available on the 8085.
The I/O ports were chosen for this interface to simplify the address decoding and to provide easy access to existing
systems.

POWER SUPPLY REQUIREMENTS
The BPK 72 operates on standard + 5V and + 12V DC power within a 5% tolerance. The worst case power
consumption is a foJlows:
+ 5VDC = 2 watts maximum
+ 12V.DC = 5 watts maximum
When power is applied or removed from a Bubble Memory System, the rotating magnetic field within the 7110 Bubble
Memory is held in the proper phase to insure non-volatility. This is accompiished through the use of a power fail reset
circuit. The foJlowing power supply speCifications must be observed to effectively support the power fail Circuitry:
A. VDD = + 12V, ±5% tolerance

Power off/power fail voltage decay rate-less than 1.1 volts/millisecond
±5% tolerance
Power off/power fail voltage decay rate-less than 0.45 volts/millisecond
e. Voltage sequenCing-no restrictions
D. Power on voltage rate of rise-no restrictions
B.

vee = +5V,

AP-150

8085 TO BPK 72
HARDWARE INTERFACE

Q. D. P

BPK 72 KIT
E1 EDGE CONNECTOR

~18

U2 8

24 MHZ

8085 MICROPROCESSOR BUS

r--"
CSYNC
2
~F/C
PCLK
~~

0, PORT ADDRESS OFEH
1, PORT ADDRESS OFFH

+5VDC

(1,22,A,p'Z)

'AD WITH RESPECT TO TH E Bp.
K72

Figure 2, Hardware Interface

The interface designer should verify that the system power supply decay rates meets the specifications previously
listed. To simulate worst case conditions, connect a 2 watt load on the + 5 volt supply and a 5 watt load on the + 12
volt supply. The power supply decay rates can be easily measured during the removal of power with a standard
oscilloscope. No attempt should be made to use the BPK 72 until the power supply decay rates have been verified.

6-89

AP·150

Table 1. 8085/BPK 72 Interface Parts List
Item

IC· 7430-8 input nand gate

any

IC·8284A-clock generator

Intel
any

IC· 7406-hex inverter open collector

Crystal-24.0000MHz fundamental mode, series resonant

any

Resistor-5.IKohm, 1/4W, 5%

any

Mica Capacitor-5pf, 100VDC, 5%

Edge connector, 44 pin

any
TRW, CINCH
#50-44B-IO

IMPLEMENTING THE 8085/BPK 72 SOFTWARE DRIVER
An 8085 to BPK 72 software driver program listing is presented in Appendix A. The driver consists of a set of
subroutines that can be called to perform commonly used Bubble Memory commands. A detailed description and
flowchart of each subroutine is provided with the program listing. The software driver is relocatable and may be
linked with other programs. The name of the program is "BPK72. " It begins at 0800H and requires less than 1K bytes
of memory allocation.
.
-_N:.;;O~..

SEE APPENDIX B

Figure 3. Initializing the BPK 72

memory to no more than 255 contiguous pages. This limitation results from the need to prevent data transfers that
could exceed the addressable memory space of the 8085. The block length register LSB may be assigned any value,
between 1 and 255 depending on the size of the transfer. A detailed description of the parametric registers may be
found in the section titled, "Communicating with the 7220."
The following is an example of how to use the Read Bubble Memory subroutine, RDBUBL, to transfer the first 16
pages (OOH-OFH) of data from the BPK72 to the 8085's addressable memory, starting at location 2000H:
,8085 Addressable Memory

8085 Microprocessor,

B Reg = 'IOH

., 1000H = lOH Block Length Reg LSB
lOOIH = lOH Block Length Reg MSB
DReg = 20H E Reg = OOH~ 1002H = OOH Enable Reg*
,
1003H = OOH Address Reg LSB
"
lO04H = OOH Address Reg MSB
H Reg = XXH L Reg = XXH
A Reg

C Reg

OOH

will return t h e ,
value ,of the 7220's
status register.

2000H
243FH

=
=

start data transfer
last data transfer
(l088 byte transfer)

XX-Don't care,
No effect on the operation
of the BPK 72.
*-Assumes that the BPK 72 was
initialized without error
correction.

Call RDBUBL.

6-92

AP-150

The Write Bubble Memory subroutine, WRBUBL, can be substituted for the call to RDBUBL to transfer data from
the 8085's addressable memory to the first 16 pages in the BPK 72.
The ex~pie shown above demonstrates how to set ~p the B-C and D;-E.registers pri~r to calling a read or write
subroutine. Just as in the case of initialization, the B-C registers contain the .address of the first of five consecutive
memory locations within the 8085's addressable memory. The data contained in the memory addressed by the B-C
registers is used to load the7220's parametric registers. The D-E register pair contains the address of the first byte of
data to be transferred to or from the 8085's addressable memory.
Figure 4 illustrates how the read and write subroutines, RDBUBL and WRBUBL, should be called from another
routine. The flowchart includes a program path to handle errors· in the unlikely event that the read or write
subroutines fail to return a successful status. First time users can omit the additional program flow for preliminary
evaluation. The next section, "Checking the Status," describes the appropriate status values necessary to verify a
successful data transfer.

EXECUTE
COUNTER ~ 2'

"IN ADDITION TO 40H:
RDBUBl48H (LEVEL 1 ERROR
CORRECTION ONLy)
DECREMENT
EXECUTE
COUNTER'

WRBUBl42H

">---'-'=--'----_

SEE APPENDIX B

'MAY BE OMITTED FOR
PRELIMINARY EVALUATION

Figure 4. Reading and Writing to the BPK 72

6·93

AP-150

CHECKING THE STATUS
After calling a subroutine to initialize, read, or write Bubble Memory data, the 7220's status register should be read to
. verify that the command was successfully executed. Note that flowcharts 1 and 2 include a test of the staiusregister
to detect for any errors. In order to facilitat~ the task of verification, each of the commonly used subroutines in the
program "BPK72" return the contents of the 7220's status register to the calling routine through the 8085's "A"
register. It is the responsibility of the cailing routine to .verify the success of each subroutine. A list of acceptable
status register values for each of the subroutines in the program "BPK72" is presented in Table 2 ..
Table 2. Acceptable Status Register Values
Subroutine

Acceptable Status
Register Valu!!(s)

OP-complete
Of-complete, parity error

RDBUBL

40H
48H

OP-complete
OP-complete, correctable error'

ABORT

40H

OP-complete

'Level I error correction only
If any read errors are encountered during the transfer of data, they will almost always result from external noise
interfering with the signal path between the 7110 Bubble Memory and the 7242 formatter sense amplifier. Since the
data within the Bubble Memory is usually correct, a second attempt to transfer data should be successful. Figure 4
illustrates the use of the ABORT command to reset the Bubble Memory Controller before making another attempt to
read or write Bubble Memory data.
.
Service information is presented in Appendix B in the unlikely event thflt any of the subroutines in Table 2 do not function properly.

7220 MICROPROCESSOR INTERFACE OVERVIEW
The key to any interface incorporating a BPK 72 is the Bubble Memory Controller. The controller provides a
complete interface to a TTL level microprocessor bus that allows the designer total freedom from the intricate timing
and waveforms necessary to support a Bubble Memory System. A block diagram of the 7220 Bubble Memory
Contr~ller is presented in Figure 5.
.
The 7220 interface circuitry consists of one 8-bit bidirectional port. The port provides access to internal registers. The
address line AO is used to select either the command/ status or parametric I data registers. A command register is used
to issue instructions such as read or write Bubble Memory data. The status register provides information about the'
completion or termination of commands and the 7220's readiness to transfer d~ta. The parametric registers contain a
set of flags and parameters that determine exactly how the 7220will respond to a software command. The datllregister is actually a forty byte FIFO to buffer the timing differences between the 7110 Bubble Memory an? a host.
processor. In order to transfer data to (from) the BPK 72, the host processor must load the parametric registers
followed by issuing a read or write Bubble Memory data command.
To maintain design flexibility, the 7220 Bubble Memory Controller provides the user with three different modes of
data transfer:
.
.
.
1. DMA, direct memory access
2. Interrupt-driven
3. Polled I/O

m:A
m:I
INTERNAL
DATA
BUS 18)

BUBBLE
SIGNAL
DECODER

WAIT

REP.EN

BOOf1N
SWAP. EN
BOOT.SW.EN
SHIFT.CLK

MBM
ADDRESSING
LOGIC AND
RAM

Figure 5. Block Diagram of the 7220 Bubble Memory Controller

In the DMA data transfer mode, the 7220 operates in conjunction with a DMA controller (such as Intel's 8257) using
the DRQ (data request) and DACK (data acknowledge) lines for handshaking. With the help oia DMA controller, the
7220 transfers the data to (from) the host processor's memory. Once the data transfer begins, program interventionis
not required until the entire data transfer has been completed.
In the interrupt mode, the 7220 along with an interrupt controller (such as Intel's 8259) uses the DRQ (data request)
line to initiate a data transfer.The DRQ line becomes active when the 7220 is ready to send or receive a burst of data. A
typical data burst is 22 contiguous bytes for an interrupt-driven interface. A set of software drivers are also necessary
to service the interrupts to coordinate the transfer of data between the 7220 and the memory associated with a host
processor. One advantage to the interrupt mode is multitasking. Since the host processor is only servicing the 7220
during data transfers, dead time between data transfers can be utilized for other processor tasks.
A polled mode interface reads the 7220 status register to determine when to transfer one byte of data. Of all the
interface modes, polled I/O is the simplest configuration to implement. No special hardware or external controllers
are necessary to interface the 7220 with a microprocessor. The major portion of a polled mode design is the software.
J,ust as in the interrupt mode, a set of software drivers are required to read and write data to the 7220.

6·95

AP-150

This application rises a polled mode "configuration. The polled i/Odata transfer mode was selected over DMA and
interrupt-driven to simplify the. interface design. A polled mode interface does not require the ,use of a DMA or
.interrupt controller. Furthermore, the polled mode interface provides the most flexibility for incorporating a BPK 72
into existing 8085 systems. Since the' majority of a polled mode dc::sign consists of software, simple prograni
modifications to accommodate existing systems can be easily entered into the software driver provided inAppendixA. '
In terms of performance, the polled I/O transfer mode is the lowest compared to DMA or interrupt-driven. The DMA
and interrupt modes offer the advantage of multitasking. However, the average access time and data transfer rate
remain the same for each data transfer mode. The following formulas and examples demonstrate how to calculate the
transfer time for a one megabit Bubble Memory System:
.
'READ

WRITE

N-page transfer: .
Transfer time = seek time + 8.7 ms + 7.5 ms

(~-1)

N-page transfer:
Transfer time = seek time '+ 7.5 ms (N)'
Average seek time = 41 ms
'. Worst case seek time '" 82 ms
Average data rate = 8.5 K-bytes/sec

For Example:
A." Time to read 1 page (assuming avg seek time):
Trarisfer'time.= 41 ms +8.7 ms= 49.7 ms
B .. Time to write 1 page (assuming avg seek time):
,Tran'sfer time = 41 ms + 7.5 ms = 48.5 ms
C. TilIleto ~ead 10 contiguous pages (assuming avg seek time):
Transfer time = 41 ms + 8.7 ms t 7.5 ms (10-1) = 117.2 ms
D. Time to write 10 contiguous pages (assuming ·avg seek time): "
Transfer time = 41 ms + 7.5 ms (10) = 116.0 ms

HARDWARE INTERFACE DESCRIPTION
.To simplify the task Of interfacing a BPK n with a microprocessor, the 7220 Bubple MenlOry Controller provides a
convenient set of TTL signals that may be directly connected to a system bus. The interface signals on the BPK 72
necessary to implement a polled mode configuration are' presented' in Table :3.

PARITY BETWEEN THE 8085 AND BPK 72 .
The 7220 ·has the capability of generating and detecting .odd parity using the bidirecti9nal data line 08. The parity bit
may be used to increase the reliability of the data path between the 7220 and ahost processor. During data transfers,
odd parity is generated for read operations and tested for write operations. Th,e host processor may read the 7220
status register to determine if a parity error occurred during a write operation. Parity is typicallyimplemented when a
long transmission path exists between the host processor and the 7220. Since most-systems utilize a simple edge
connector backplane and a short transmission path (less than 18 inches), parity isnqt necessary, Parity is pot
implemented in this application to Il).inimize the hardware' complexity.
The parity bit, 08, is.~ot stored within. the 7110 Bubbl~ Me~ory module.A.s~par~te and more effective ~~ror
detection and correction f~ature is available as an option to inctease the data integrity' within the 7110. See the sec~on
titled, ""Communicating with the 7220" for further details. about the option of" automatic error detection . ami
correction.
'
r.'

6-96

AP-150

Table 3. BPK 72 Polled Mode Interface Signals
Signal

Function

Address line
AO = 0 Selects the FIFO data buffer or the parametric registers.
AO = I Selects command/status registers.

00-07

8 bit bidirectional data bus.

D8.1

Optional odd parity bit, not used in this application.

CSI

Chip select input. A logic high will tri-state the 7220 interface signals. (Slash, 001" designates a low active
signal, system ground)

RDI

Read 7220 registers or data FIFO.

WRI

~rite

DACKI

DMA acknowledge. If DMA is not used, OACKI requires an external pullup resistor to VCC (5.1 Kohm).

CLK

4 MHz TTL level clock.
Clock period = 250 ns, 0.25 ns tolerance.
Duty cycle = 50%,5% tolerance.

RESETI

A low on this pin forces the interruption of any 7220 activity. performs a controlled shut-down, and initiates a
reset sequence. The next instruction following RESETI must be an abort command.

7242 CSI

7242 chip select signal is used to select banks of 72425. 7242 CSI must be tied low (system ground) for a single
bank configuration.

7220 registers or data FIFO.

4 MHZ CLOCK
The BPK 72 requires an external 4 MHz (may be asynchronous with respect to a host processor) TTL level clock. The
specifications for the period and duty cycle are presented in Table 3. The 7220 uses the external clock to generate the
timing signals that control the rotating magnetic field within the 7110 Bubble Memory. For reliable operation, t\'le
clock tolerances must be observed to assure that the rotating field is stable and accurate.
An Intel integrated circuit, 8284A clock driver, is used to generate the 4 MHz external clock. The 8284A along with a
24MHz series resonant crystal (fundamental mode) will provide a precise and accurate clock for any interface
incorporating a BPK 72. The circuit configuration for the 8284A is illustrated in Figure 2. Other techniques of clock
generation are acceptable as long as the duty cycle and period are within the specifications listed in Table 3.

SOFTWARE INTERFACE DESCRIPTION
The software driver presented in Appendix A contains the following subroutines that may be called from another
routine:

* INBUBL
* RDBUBL
* WRBUBL
ABORT
FIFORS
WRFIFO
RDFIFO
WRBLRS
RDBLRS
MBMPRG

-Initialize the BPK 72.
-Read Bubble Memory data.
-Write Bubble Memory data.
-Abort present command, reset BPK 72.
- Reset 7220 FIFO data buffer.
- Write 7220 FIFO data buffer.
- Read 7220 FIFO data buffer.
- Write 7242 boot loop registers.
-Read 7242 boot loop registers.
-,Bubble Memory purge command.
-Read Bubble Memory boot loop.
~*RDBOOT
-Write Bubble Memory boot loop.
**BOOTUP
* Most commonly used commands.
** Diagnostic routines (see Appendix B).
6-97

AP-150

Each of the subroutines listed above is described in further detail in Appendix A. Along with each subroutine is a
generalized flowchart displaying the program flow. The user is encouraged to read the software driver to better
understand the software interaction necessary to interface a. BPK 72 with an 8085 microprocessor.

COMMUNICATING WITH THE 7220
Some additional background is necessary to understand the operation of the 7220 Bubble Memory Controller. Figure
6 illustrates the user~accessible registers that control and format the flow of data between the 71 Hi Bubble Memory
and a host processor.
The address assignments for the user-accessible registers within the 7220 are presented in Table 4. The registers are
.listed in two groups. The first group (status, command, register address couriter) consists of those registers that are
'selected and accessed in one operation. The second group contains the FIFO data blifferandtheparametric registers
(utility, block length, enable, address), they are selected according to the contents of the register address counter
(RAC).
Table. 4. Address Assignments for the User-Accessible Registers
AD

NOTES:
SSSs$sss
CCCC
, BBBB
B3B2B IBO
LSB
MSB

8-bit status information returned to the user from the STR

= 4-bit command code sent to the CMDR by the user.
= 4-bit register address sent to the RAC by the user. , ,

= 4-bit contents of RAC at the time the user makes a read or write request with AO = O.
= Least Significant Byte
= Most Significant Byte

Table 5. Parametric Registers and FIFO Data Buffer

Symbol
UR
BLRLSB
BLRMSB
ER
ARLSB
'ARMSB
FIFO

Name of Register

Utility Register
Block Length Register LSB
Block Length Register MSB
Enable Register
Address Register LSB
Address Register MSB
FIFO 'Data Buffer

Read/Write

Read or Write
Write Only
Write Only
Write Only
Read or Write
Read or Write
Read or Write

To successfully implement the hardware and software presented in'this application, certain restrictions are placed
on the contents of the user-accessible registers. Each of the user-accessible registers and any necessary restrictions will now be discussed in further detail.
"
"
,

COMMAND REGISTER
,

The 7220 command set consists of 16 commands identified by a, 4 bit command code. A list of the commands is
presented in Table 6.

6-98

AP-150

4·BIT ADDRESS

FIFO DATA BUFFER
PARAMETRIC REGS

AO - - - - - - - - - - ' - - - - - '

Figure 6. 7220 User Accessible Registers

Table 6. 7220 Commands
03

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Command Name
Write Bootloop Register Masked
Initialize
Read Bubble Data
Write Bubble Data
Read Seek
Read Bootloop Register
Write Bootloop Register
Write Bootloop
Read FSA Status
Abort
Write Seek
Read Bootloop
Read Corrected Data
Reset FIFO
MBM Purge
Software Reset

The commands listed in Table 6 are provided for reference purposes only. The software driver in Appendix A consists
of a series of subroutines that automatically issue the appropriate commands to perform a data transfer.
The function of each command is usually apparent from the command name (e.g., initialize, read bubble data, write
bubble data). Additional detail concerning the function of each command may be found in the BPK 72 user's manual.

. REGISTER ADDRESS COUNTER
The register address counter consists of a 4 bit address that points to one of the six parametric registers:
Utility register (UT)-The utility register is a general purpose register available to the user in connection with Bubble
Memory System operations. It has no direct effect on the operation of the 7220. It is provided as a convenience to the
user.

6·99

Ap·150

Block length register (BLR)-The contents of the block length register determine the system page size and the
number of pages to be transferred in response to a single bubble read or. write command. The bit configuration is as
follows:
.

BLOCK LENGTH REGISTER MSB

BLOCK LENGTH REGISTER LSB

17161514131211101

....--------~~

~'---y---'; x ~,------------v~
NUMBER OF FSA
CHANNELS (NFC)

NUMBER OF PAGES TO BE TRANSFERRED

Figure 7. Block Length Registers

The 7220 has the capability of supporting up to eight 7110 Bubble Memory modules . Each 7110 contains two channels
that are sensed by a 7242 formatter sense amplifier (FSA). In multiple Bubble Memory configurations, the BLR
allows the user to select the page size. Since the BPK 72 consists of only one Bubbk Memory module, the field
specifying the number of FSA channels in the BLR MSB must contain -OOOlB ("B" designates a binary notation).
After the FSA field is set, the page size is dependent upon the use of error detection and correction. Error correction
will be discussed in the next section describing the function of the enable register.
The BLR LSB and the first 3 bits of the BLR MSB determine the number of pages to be transferred during a single
read or write command. This application restricts the user to no more than 255 contiguous pages to prevent data
transfers that could exceed the addressable memory space of the 8085.' ..

For This Application
BLR MSB-IOH at all times.
("H" designates a hexadecimal notation)
BLR LSB-Selectable from OIH to FFH (1 to 255 pages).
CAUTION: OOH in the BLR LSB will enable a 2048 page transfer resulting in a timing error.
Enable Register (ER)-The user sets the bits in the enable register to enable or disable various functions within
the 7220. The individual bit descriptions are as follows:
.

lJJ=~~~~~~~

INTERRUPT 'ENABLE (NORMAL)
INTERRUPT ENABLE (ERROR)
MFBTR

WRITE BOOTLOOP ENABLE

DMA ENABLE
ENABLE
Reo
ENABLE ICD
ENABLE PARITY INTERRUPT

Figure 8. Enable Register

6·100

AP-150

One of the most important functions concerning the enable register is the option of automatic error detection and
correction. If error correction is enabled during a write operation, the 7242 formatter sense amplifier appends each
256 bit block of data with a 14 bit fire code. Both the data and the fire code are stored within the 7110 Bubble Memory
module. During a read operation, the 7242 compares the data with the fire code to check for any errors. With respect
to the FSA, errors are either correctable (the FSA is able to reconstruct the data using an error'correction algorithm
before transferring the data to the 7220) or uncorrectable. Additional information about the fire code is available in
the BPK 72 user's manual.
The enable register offers three levels of error correction. All three levels utilize the same error correction algorithm
but differ in their interaction with a host processor. Table 6 defines the relevant register bits for the various levels of
error correction.
Table 6. Error Correction Levels
Error Correction
Level

Bit6 (ICD)

Enable Register
Bit 5 (RCD)

Level 0 does not enable the error detection and correction algorithm. In this mode, the 7220 partitions one megabit
systems into 2048 pages consisting of 68 bytes per page.
Level I is the most popular level of error correction. If an error is detected during a read operation, the 7242
automatically cycles the data through its error correction algorithm am! transfers the data to the 7220. If the error was
correctable, the 7220 will continue to function normally i.e., correctable errors in Levell are transparent to the host
processor. If the error was uncorrectable, the 7220 will stop reading at the end of the page wherein the error was
encountered. In the unlikely event that the 7220 stops because of an uncorrectable error, the host processor should
try at least one more attempt to read the data. In most cases, errors result from random noise that can interfere with
the signal path between the 7110 and 7242. Since the data is usually correct within the 7110, anotherattempt to read
the data should yield a successful status.
Level 2 and Level 3 differ from Level I in that page-specific logging of uncorrectable errors is possible and the
transfer of erroneous data can be prevented. Level 3 differs from Level 2 in that Level 3 also allows the logging of
correctable errors.
Neither Level 2 nor Level 3 is supported by this application because the probability of an uncorrectable error is
typically one in 1016 bits read. An. error rate of this, magnitude will produce few if any uncorrectable errors
. . .
throughout the useful life of a Bubble Memory System.
It is recommended that Level I error correction be utilized to improve the integrity of the data within the 7110. In
Level. I , the 7220 assigns 64 bytes to a page in one megabit Bubble Memory Systems.

Aside from error correction, the enable register performs many.other functions.
Enable. Parity Interrupt-If this bit is set, any parity errors between the host and the 7220 during write
operations will generate an interrupt. Since parity and the interrupt mode are not used in this application, the
enable parity interrupt bit should be reset to a logical zero.
Write Bootloop Enable-This bit must be reset to prevent accidental erasure of the boot loop within the 7110.
MFBTR-The MFBTR bit should always be reset to maxirhize the data transfer rate betweenthe 7220 and 7242
during read operations.
6-101

AP-150

DMA Enable-If this bit is set, the 7220 will attempt to transfer data in the DMA mode. Since this application
utiliies a polled mode interface, this bit must be reset to a logical zero.
Interrupt Enable (Nornial)-If this bit is set, an interrupt is sent to the host processor after the successful
completion of a Bubble Memory command. Since this application us'es a polled mode interface, this bit should
be reset to a logical zero.

For This Application
Enable Reg-OOH. No error correction.
-20H. Level 1 error correction.
Address Register (AR)-The contents of the address register determine which starting address locations will be
used during a read or write command. For systems with a mUltiple Bubble Memory configuration, an additional
magnetic Bubble Memory (MBM) select field is used to specify which Bubble Memory(s) will be selected. The
bit configuration is as follows:

ADDRESS REGISTER MSB

ADDRESS REGISTER LSB

17161514131211101 17161514131 2 11101

, ______-..y_------'J'

MBM SELECT

STARTING ADDRESS WITHIN EACH MBM

Figure 9. Address Registers

Since the BPK 72 consists of only one 7110 Bubble Memory module, the MBM sdectfidd must contain -OOOOB
C'B" designates a binary notation).

For This Application
AR MSB-OOOOOXXX
, AR LSB-XXXXXXXX, X = user sdectable page address
from 0 to 2047.

STATUS REGISTER
In a polled data transfer mode, the status register provides information about error conditions, completion or
termination of commands, and the 7220's readiness to transfer data or a:ccept new commands. The bit configuration
for tl'\e status register is as follows:

lJ=b~~~~~~~

FIFO AVAILABLE
PARITY ERROR
CORRECTABLE ERROR
UNCORRECTABLE
ERROR
TIMING
ERROR
OP FAIL
OP COMPLETE
BUSY

Figure 10. Status Register

6·102

AP·150

Busy-When active (Logic 1), the Busy bit indicates that the 7220 is in the process of executing a command. Bits
1 through 6 of the status register are valid only when the busy bit is not active (Logic 0).
OP Complete-When active (Logic 1), the OP Complete bit indicates the successful completion of a command.
OP Fail-When active (Logic 1), the OP Fail bit indicates that the 7220 was unable to successfully complete the

current command.
Timing Error-When active (Logic 1), the Timing Error bit indicates that an FSA has reported a timing error to
the 7220, or that the host system has failed to keep up with the required data rate during a read or write
operation.
Correctable Error-When active (Logic I), the Correctable Error bit indicates that an FSA has detected a
correctable error in the last block of data read from the 7110.
Uncorrectable Error-When active (Logic 1), the Uncorrectable Error bit indicates that an FSA has detected
an uncorrectable error in the last block of data read from the 7110.
Parity Error-When active (Logic 1), the Parity Error bit indicates that a parity error was detected between the
7220 and the host processor. Parity errors are only detected by the 7220 during write operations. Since parity is
not used in this application, ignore all parity errors.
FIFO Ready-When the 7220 is busy, an active FIFO Ready bit (Logic 1) indicates that the FIFO has data for
reading or space for writing. When the 7220 is not busy, the FIFO Ready bit (Logic 0) indicates that the 40 byte
FIFO and the input and output latches are completely empty.

SUMMARY
This application note is intended to eliminate almost all of the development effort necessary to interface an 8085
microprocessor with a BPK 72. With the addition of only a few IC's and the software driver presented in Appendix A,
the designer is well on the way to incorporating the benefits of improved reliability, reduced maintenance, and
non-volatility into any 8085 microprocessor based system.

6-103

AP·150

APPENDIX A .
8085 TO BPK-72 INTERFACE
SOFTWARE DRIVER LISTING
AND
FLOWCHARTS

6-104

AP-150
ASl'I88 :F1: BPKHDR

LOC OBJ

PfIGE

BPK72

ISIS-II 8980/8085 MACRO ASSEMBLER, V3. 0

SOURCE STATEMENT

LINE

*********-********************--****************************

4;
5;
6;
7;
B;
9;
19 ;
11 ;

12 ;
13;
14 ;

PROGRAM: B985 TO BPK72 SOFTWARE DRIVER IIi 9
UUlONT S. SMITH JR.
mill CORPORATION
3965 BOWERS AlJalUE
SANTA CLARA, CALIFORNIA 95051

***********************-*-******-*********-*************

15 ; ABSTRACT:

16 ;
17
1S
19
29
21
22
23
24
25
26
27
28

;
THIS PROGRAM CONSISTS OF A .SET OF BUBBLE ~lEl1ORY SOFTWARE DRIVERS
.:
THAT SUPPORT A POLLED MODE INTERFACE BETWEEN A BPK72, 1t1BIT BUBBLE
;
t1EMORY PROTOTYPE KIT, AND A STANDARD BeSS tlICROPROCESSOR. THE
;
PROGRAM UTILIZES A SET OF PUBLIC DIRECTIlJES THAT CAN BE CALLED
;
TO PERFORM A BUBBLE t1E~10R'r' INITIALIZATION, REflD, HRITE, AND OTHER
;
CO~1I10NL'r' USED CO~lMAND5. IN THE UNLIKELY EvaIT THAT THE 7110 BUBBLE
;
t1EMOR'r' BOOT LOOP IS LOST, TWO ROUTINES ARE PROVIDED TO EXAMINE AND
;
REWRITE THE BOOT LOOP CODE.
;
;
;
; PROGRAM ORGANIZATION:

43.:
44 ;
45 ;
46 ;
47 ;
48;

BYTCNT
WRITE
READ
ABORT
WRBUBL
RDBUBL
INI?.l.JBL .
BOOTUP
RDBOOi
WRFIFO
RDFlFO
vlRBLRS
RDBLRS .
MB~lPRG

49 ; EXTERNAL DECLARATIONS: NONE

53;
51.:
52 $EJECT

·6·105

AP·150

ISIS-II 8888/8085 MACRO ASSEMBLER, V3. 13

5l;
54 ; PUBLIC SYMBOLS:

55;
56 ;
57 ;

FIFORS
ABORT
WRBUBL
RDBUBL
,INBUBL
BOOTUP
RDBOOT
WRFIFO
RDFIFO
WRBLR5
RDBLRS
HBMPRG

58;
59 ;

613;
61,;
62 ;
g;
64 ;

65;
66;

,,
P'
68 ;
69 ;

RESET 7228 FIFO DATA BUFFER
ABORT PRESENT CottlAND, RESET BPK72
WRITE BUBBLE ~1EMORI' DATA
READ BUBBLE t'lEt10RY DATA
INITIALIZE THE BPK72
WR ITE BUBBLE MEt10RY BOOT LOOP
READ BUBBLE MEMORY BOOT LOOP
WRITE 72213 FIFO DATA BUFFER
READ 722eFIFO DATA BUFFER
WRITE 7242 BOOT LOOP REGISTERS
READ 7242 BOOT LOOP REGISTERS
BUBBLE ~1EMORY PURGE COMMAND

71;
72

NAME BPK72

73 ;
74 ;

******************************************************************************

77 ; ***************************************************************"''*****78 ;
ORG

sa;
81 ;
82 ;

*********************************************-************.._******-*

83 ;
B4 ;
85 ;

-****************************,-********-***********************-

**********************************"'*'*-****-****************-

99 ;
91 PRTAOO EQU
92 PRTAa1 EQU
91
94
95
96
97
98
99
Hie
1131 ;
1132 $EJECT

BFEH
0FFH

; A POLLED HODE INTERFACE REQUIRES ONLY TWO I/O
PORTS DESIGNATED BY THE Ai! LINE ON THE BPK72 BOARD.
; THIS APPLIC.ATION USES:
eFEH - Afi=il FOR PRTAOO (PORT A0= a)
RDlWR BUBBLE t'1EMORI' DATA AND REGS
BFFH - A0=1 FOR PRTA01 (PORT A0= 1)
RD STAruS REG
flR BUBBLE MENORY COMMANDS

6-106

AP-150

ISIS-II 8080/8085 MACRO ASSEi'1BlER, V1

***********************************************************-********-*

0800
13801
13802
0804
0806
0808
13809

C5
D5
3E0B
D3FF
lE05
0A
D3FE

0S08 03
B80C
080D
0B10
0811
0812

1D
C20808
01
Cl
C9

103 ;
104 ;
105 ; FUNCTION: INTPAR
106; INPUTS: B-C REGS, STARTING ADDRESS OF PARANETRIC REG"S IN RAN
107 ; OUTPUTS: 722e PARAMETRIC REGS
108; CALLS:
NONE
109 ; DESTROYS: A, FIFS
110 ;
111 ; DESCRIPTION: LOAD THE 7220 PARAt1ETRIC REGS
112 ;
THE B-C REGS CONiAIN THE ADDRESS TO THE FIRST OF FIVE CONTIGUOUS
113 ; .
~1810RY LOCATIONS IN RAt1.
THE DATA ADDRESSED BY THE B-C REGS IS
114 .;
USED TO LOAD THE PARAMETRIC REGISTERS IN THE 7220 BUBBLE t'lENORY
U5 ;
CONTROLLER. INTPAR COPIES THE DATA IN RAt1 TO .THE PARANETRIC REGS.
116;
; SAVE B-C REGS
117 INTPAR: PUSH
B
; SAVE D':'E REGS
118
PUSH
D
A,0BH ; LOAD A REG WITH BlR LSB ADDRESS
119
till I
OUT
PRTAel ; LOAD 72213 RAC HITH BLR LSB ADDRESS
120
E,€iSH ; INITIALIZE LOOP COUNTER
121
~1VI
122 LOAD: LDAX
.; LOAD A REG FRON B-C REG ADDRESS
B
123
OUT
PRTA0e ; WR ITE PARAt1ETR I C REG
124
INX
B
; INCRErlENT B-C REGS TO THE HEXT ADDRESS IN RAt1
125
OCR
E
; DECRENENT LOOP COUNTER
126
JHZ
LOAD
; IF NOT ZERO, J~IP LOAD
127
POP
; RESTORE D-E REGS
D
128
POP
; RESTORE B-C REGS
B
RET
; RETURN TO CALL
129

LOAD 7220 RAC ~
BLOCK LENGTH
REG LSBADD
OBH

INITIALIZE LOOP
COUNTER ~ OSH

WRITE 7220
PARAMETRIC REG

DECREMENT LOOP
. COUNTER

COMMENTS: THE UTILITY REGISTER IS NOT USED. THE RAC IS
AUTOMATICALLY INCREMENTED AFTER EACH WRITE
~~J~~ ~~~~UTED. THE RAC WILL NOT INCREMENT

, Figure 11. INTPAR

6·108

AP-150

1515-II 898918985 MACRO ASSEMBLER, 113, B

*********************************----*''**-*******

BBB
9814
0815
€I817
081A
0B1C
0B1E
9820
9821
9824
0825
9826
9827
0828
0828
082E
0830
0m
9834
0835
0836
0837
9838
0838
083C
083D
083F

OS
C5
B64B
llFFFF
3E1D
D3FF
DBFF
07
DA2E98
18
AF
B2
B3
C21E98 ,
C33B08
DBFF
A8
CA3B98
1B
AF
B2
B3
C22E98
Cl
01
DBFF·
C9

134 ;
135 ;
136 ; FUNCTION: FIFORS
137; INPUTS: BP"'72 STATUS REG
138 ; OUTPUTS: ISSUE FIFO RE:l~T CONNAND TO BPK72
139 ;
A REG= BPK72 STATUS REG
14B ; CALLS:
N@E
141; DESTROYS: A, FIFS
142.'
143; DESCRIPTION: RESET 7220 FIFO DATA BUFFER
144 ;
A FIFO RESET CO~lMAND IS ISSUED TO THE BPK72. AFTER ISSUING THE
COHMAND, THE BPK72 STATUS REG IS POLLED UNTIL AN OP-CONPLETE.
145 .'
40H, HAS BEEN READ OR THE TIME OUT LOOP COUNTER DECREMENTS TO
146 .'
147 .
ZERO, FIFORS RETURNS THE VALUE OF THE BPK72 STATUS REG TO THE
148 .
CALLING ROUTINE VIA THE 8085'5 A REG. ONLY A ,STATUS OF 40H
INDICATES A.sUCCESSFUL E~;ECUTION OF THE FUNCTION FIFORS,
149.'
150.'
151
PUBLIC FlFORS .' DECLARE PUBLl C FUNCTI ON
. SAVE D-E REGS
152 FIFORS: PUSH
0
; SAVE 8-C REGS
153
PUSH
B
B,4BH .. LOAD 8 REG= 40H, oP-COt'lPLETE
154
Mill
D, BFFFFH.. INTIALlZE TI!'lE OUT LOOP COUNTER
155
LXI
A,iDH i LOAD A REG: FIFO, RESET COt'lNAN[)
MVI
156
OUT
PRTA01 . WRITE FIFO RESET CONMAND
157
158 BUSYFR: IN
PRTA01 ; READ STATUS REG
RLC
i TEST BUSY BIT= 1
159
160
POLi..FR ... IF BUS'~= 1, POLL STATUS REG FOR4!lH
JC
D
.' DECRENEHT TIl1E OUT LOOP. COUNTER
161
DCX
162
XRA
A
.' CLEAR A REG
; TEST D REG= WH
163
ORA
D
164
ORA
E
. TEST E REG= e0H
165
BU5'r'FR i IF NOT ZERO, CONTINUE POLLING FIFO RESET CONNAND
JNZ
166
RETFR i TIME OUT ERROR, RETURN
n'lP
167 POLLFR: iN
PRTA01 i READ STATUS REG
" TEST STATUS= 4BH, OP-CO~lPLETE
168
B
X~A
RETFR " IF OP-COI1PLETE, JMP RETFR
169
JZ
DCX
; DECREMENT TIME OUT LOOP COUNTER
170
D
:~RA
i CLEAR A REG
171
A
i TEST DREG: 00H
172
ORA
D
173
ORA
E
i. TEST E REG= 0aH
POLLFR i. IF NOT ZERO., CONTINUE POlLING FIFO RESET CmtlAND
174
JNZ
175 RETFR: POP
B
.' PESTORE B-C P.EGS
POP
176
D
" RESTORE D-E REGS
READ STATUS REG
177
IN
PRTA01
17B
RET
; RETURN TO CALL
179 i
180 .
181;
182 $EJECT

6-109

AP-150

INITIALIZE
TIMEOUT
LOOP COUNTER

ISSUE
FIFO RESET
COMMANO

READ 7220
STATUS REG

OECREMENT
TIMEOUT··
LOOP COUNTER

REA07220
STATUS REG

COMMENT: MINIMUM TIME OUT LOOP COUNT = 50"S.

Figure 12. FIFORS

AP-150
1515-II 8080/8085 MACRO ASSEMBLER; Vl. 0

LOCOBJ

LINE .
,1B3 ;
184 ;
185;
.196 ;
187 ;
199 i

199

0840 C5
0841 D5
0842 0A
0843 6F
0844 03
0845 93
0846 0A
084767
0848 1640
084A 3E6e1
084C A4
0S4D C25208
0850 1644

0852 2600
0854 lE09
0856 7D
0857 lF
0858 ~F
085910
085A CA6708
0851> 7C
... 0SSE D26288
9!l61 B2
0862 lF
8863 67
0864 C35608
0867 D1
0868 Cl
0869 C9

BPK72'

PAGE

SOURCE STATEMENT

*-**-*-****************--*************************
FUNCTION: BYTCNT
INPUTS:
OUTPUTS:
CALLS:
DESTROYS:

B-C REGS, STARTING ADDRESS OF PARAHETRIC REGS IN RAt'!
H-L REGS= BYiE .COUNTER
NONE
A, H, L, FIFS

198 j DESCRIPTION: BYTE COl»lTER
191 ;
THE IH REGS CONTAIN THE ADDRESS TO THE FIRST OF FIVE CONTIGUOUS MEi'!ORY
192 ;
LOCATIONS IN RAM. THE DATA ADDRESSED BY iHE B-C REGS IS USED TO LOAD
193 j
THE PARAHETRIC REGS IN THE 7228 BUBBLE ME~1ORY CONTROLLER. THE ENABLE
194 ; .
REG IS READ FROM RAI1 TO DETERMI.NE IF ERROR CORRECTION HAS BEEN ENABLED.
195 ;.
THE USE OF ERROR CORRECTION REQUIRES A 64 BYTE TRANSFERIPAGE - 69 BYTE
196 ;
TRANSFER/PAGE WIiHOUT ERROR CORRECTION. Th'E BLOCK LENGiH REG L5B IS
197 ;
ALSO READ FROM RAM TO DETERMINE THE NUMBER OF PAGES TO BE TRANSFERRED
199 i
DURING THE NEXT READ OR WRITE COMtlAND. THE NUMBER OF BYTES PER PAGE
199 ;
MULTIPLIED BY THE NUMBER OF PAGES IS COI1PUTED ANI) PASSED TO THE CALLING
200 ;
ROUTINE lilA THE 8085'5 H-L REGS. DATA TRANSFERS ARE LIMITED TO 16, 320
201 i
BYTES WliH ERROR CORRECTION AND 17,340 B't'TES WIiHOUT. ONLY THE BLRLSB
282 ;
IS USED TO GENERATE THE BYTE COUtiTER.
203;
204 BYTCNT: PUSH
B
i SAVE B-C REGS
295
PUSH . D
j SAVE D-E REGS
206
-LDAX
B
i LOAD A REG WITH BLRLSB
207
MOil
LA: ; MOllE BLRLSB TO L REG
20S
INX
B
209
INX
B
; INl."'REi'lENT B-C REGS TO ADDRESS THE ENABLE REG IN R~l
210
LOAX
B
; LOAD A REG WITH ENABLE REG
211
MOY
H, A ". '; MOllE ENABLE REG TO H REG
214
1M
D,40H; INITIALIZE D REG 64 BYTES/PAGE XFER, 40H
213
MyI
A,60H; ERROR CORRECTION DETECTION MASK
214
ANA
H
; LOGICAL AND MASK WITH H REG.. TEST FOR ERROR· CORRECTION
215
JNZ'
MULT
i IF ZERO, ERROR CORRECTION IS NOT ENABLED
216
Mill
D, 44H ; NO ERROR CORRECTION, 69 BYTES/PAGE XftR, 44H
; NULTIPLY (D REG) X (L REG)
217
; 64 OR 68 BYTES X NO. OF PAGES IN BLRLSB
218
; RESULT WILL BE PLACED IN THE H-L REGS
219
220
i BEGIN. MULTIPLY ROUTINE
H,0H
; INITIALIZE MOST SIGNIFICANT BYTE OF RESULT
221 MULT: Mill
E,09H ; INITIALIZE BIT COUNTER
222
1M
A,L
; MOYE LOW ORDER B\,1E INTO A REG
223 MULTO: 11011
RAR .' ....
224
; ROTATE LEAST SIGNiFICANT BIT OF NULTIPLIER
L,A
MOV
; MOllE LOP/ORDER eVTEOFRE5ULT INTO L REG
225
226
OCR
E
i DECREMENT BiT COUIHER
227
JZ
DONE
; EXIT IF COMPLETE
A,H
; HOllE HIGH ORDER BYTE INTO A REG
229
MOiJ
MULTi ; iF CARRY= 0, . JliP NULTI
.. 229.
JNC.
ADD
D
.. j ADD D REG TO nREG
230
.; . CARRY= il, SHIFt HIGH ORDER ME OF RESULT
231 MULTi: RAR
H,M
j MOVE HIGH ORDER RESULT iNTO H REG
232
MOil
'JMP
1'1ULTO ; CONTINUE LOOPING
m
j RESTORE D-E REGS
234 1)ONf:: POP
D
j RESTORE B-C REGS
235
POP
B
; RETURN TO CALL
236
RET
237 i

AP-150

READ 7220
BLRLSBREG
FROM RAM

MULTIPLIER
BLRLSB

READ 7220
ENABLE REG
,FROM RAM

MUL:rIPLlCAND =
68 DECIMAL

MUL:rIPLICAND =
64 DECIMAL

44H

40H

MULTIPLY,
MUL:rIPLICAND
MULTIPLIER

BYTE COUNTER
= RESULT

COMMENTS:, 'THE PARAMETRIC REGS-BLRLSB AND THE ENABLE REG'
CAN NOT BE READ FROM THE 7220. THEY MUST BE READ.
FROM A MEMORY IMAGE IN RAM. SINCE ONLY THE BLRLSB
IS USED TO COMPUTE THE BYTE COUNTER, DATA
TRANSFERS ARE LIMITED TO 255 PAGES.
'

***************************-1<**************_ _**_ _**-*********

238 ;
239 ;
240 ; FUNCTiON: WRITE
241; HIPUTS: D-E REGS, STARTING ADDRESS OF DATA IN RAl1
242 ;
H-L REGS, B'r'TE COUNTER
243 ;
BPk72 STATUS REG
244; OUTPUTS: WRITE DATA TO BUBBLE I1EMORY
245 ; CALLS:
NONE
246 .' DESTROYS: A, H, L F/F5
247 ;
248 ; DESCRIPTION: TRANSFER DATA FROI'1 RAM TO BUBBLE MEl-lORY
249 ;
THE D-E REGS CONTAIN THE STARTING ADDRESS IN RAM OF DATA
258 ;
TO BE WRITTEN INTO THE BI:JBBLE MEMORY. THE H-L I1EGS liUST
251 ;
CONTAIN A BYTE COUIHER INDICATING THE NUMBER OF DATA BYTES
252 ;
TO BE TRANSFERRED. THIS FUNCTION BEGINS BY ISSUING THE WRITE
253 ;
BUBBLE t-1E~lORY DATA COI'1I1AND FOLLOWED BY POLLING THE STATUS REG
254 ;
TO DETERHINE IF THE 722e FIFO DATA BUFFER IS READY TO RECEIVE
255 ;
DATA. DATA IS TmlSFERRED UNTIL THE BYTE COUNTER OR TIt1E
256 ;
OUT LOOP COUNTER DECROOITS TO ZERO. THE PARAMETRIC REGISTERS
257 ;
MUST BE LOADED WITH THE DESIRED VALUES PRIOR TO CALLING THIS
258 ;
FUNCTION.

259 ;
B86A D5 .

'8S6B C5
886C 01FFFF
986F3E13
9871 D3FF
9873 as
0874 AF
0875 B0
0876 B1
0877 CARle8
€i87A DBFF
B87C 07
087D D27308

260 WRITE: PUSH
261
PUSH
262
LXI
263
~IVI
264
OUT
265 BUSYWR: DCX
266
:iRA
267
ORA
268
ORA
269
JZ
27€i
IN
271
RLC
272
JNC
273
274 $EJECT

;
D
;
B
B,0FFFFH;
A,13H ;
PRTA01 ;
B
.'
A
;
;
B
C
;
FIN5H~1 ;
PRTA@i ..
;
BU5YWR ;
;

SAVE D-E REGS
SAVE B-C REGS
INITIALIZE TH1E OUT LOOP COUNTER
LOAD A REG: WRITE BUBBLE 11E1-lORY DATA COI1I1AND
WRITE, WRITE BUBBLE MEl-lORY DATA COMMAND
DECREMENT m1E OUT LOOP COUNTER
CLEAR A REG
TEST B REG: aSH
TEST C REG= OOH
IF ZERO, TIl1E OUT ERROR, .IMP FIN5HW
READ STATUS REG
TEST BUS',' BIT= 1
IF ZERO, CONTINUE POLLING BUSY BIT
CONTINUED ON NEXT PAGE

6-113

AP-150

BPK72

ISIS-II 898010085 MACRO ASSEMBlER, V3. B

LOC OBJ
BSSB
9882
0083
BSS6

9SSD
BBSE
008F
B899
9893 C3.sees

13896
13897
9899
B89A
009B

oose
989D
009E
BBAi
OOA2

BBAl

1A
D3FE
13

2B
AF
B4
B5
C2890S
C1
D1
C9

JNC
DCX
XRA
ORA
ORA
JZ

288
289
2913 '
291'
292
293
294
295 FINSHW:
297

SOURCE STATEMENT

275 POLLWR: IN
276
RRC

296

PAGE

XRA
ORA
ORA
JNZ
POP
POP
RET

READ STATUS REG
TL<;T FIFO READ'r' BIT: 1
WFIFO i IF FIFO READ'r': 1, JNP WFIFO
PRTA01; READ STATUS REG
; TEST BUS'r' BIT: 1
FINSHW i IF ZERO,. ERROR, JMP FINSHW
i DECREMENT TIME OUT LOOP COUNTER
B
,A'
i CLEAR A REG
B
.' TEST B REG: 9BH
; TEST C REG= 00H
C
FINSHW ;IF ZERO, TIME OUT ERROR, JMP FINSHW
POLLWR i CONTINUE POLLING FIFO' READ~' BIT
; LOAD' A REG FROM D-E REG ADDRESS
D
PRTAOO ; WRITE A REG TO 7220 FIFO DATA BUFFER
; INCREMENT D-E REGS TO NEXT ADDRESS IN RAM
D
; DECREt1ENT BYTE COUNTER
H
; CLEAR A REG
A
i TEST H REG: B0H
H
; TEST L REG: 00H
L
POLLWR ;' IF B'r'TE COUNTER NOT ZERO, JMP POLLWR
; RESTORE 8-C REGS
B
; RESTORE fJ-E REGS
D
; RETURN TO CALL
PRTA91

2.,Q8 i

299 i
3013 ;
391 $EJECT

6-114

Ap·150

INITIALIZE
TIMEOUT
LOOP COUNTER

ISSUE WRITE
BUBBLE MEMORY
DATA COMMAND

READ 7220
STATUS REG

WRITE LOOP

WRITE FIFO
1 BYTEXFER

DECREMENT
LOOP COUNTER

DECREMENT
BYTE COUNTER

RETURN
COMMENTS: MAX WRITE LOOP TIME = SOl's.
MIN WRITE LOOP TIME = 21'S.
MIN TIME OUT LOOP COUNTER = O.5aee

Figure 14. WRITE
6·115

AP-150

15IS-II 81380/8085 MACRO ASSEMBl.ER,V3. 0

LOC OBJ

LINE
3132 ;
303 ;
304 ;
3135 ,:
306 ;
387 ;
308 ,:
3139;
310 ;
311;
312.;
313.;
314 ,:
315 ,:
316 ;
317 ;
318 ;
319 ;
320 ;

0SA4
OSA5
0SA6
08fl9
OSAB
08AD
0SAE
0SAF
e88e
asS1
08B4
0.986
asB?

05
C5
fl1FFFF
3E12
D3FF
flB
AF
Sft
B1
CADB13S
DBFF
07
D2AD08

BPK72

PAGE

SOURCE STATEt1ENT

**************************************""'************************-**********
FUNCTION:' READ
INPUTS: D-E REGS, STARTING ADDRESS IN RAM
H-L REGS, BYTE COUNTER
BPK72 STATUS REG
READ DATA FROM SUBBI.£ t1E/'10RY
OUTPUTS : I~R ITE DATA TO RAM
CALLS:
NONE
DESTRO't'S.: A, H, L, F/FS

DESCRiPTION: TRANSFER DATA FROM BUBBLE t1EMORY TO RAt1
THE D-E REGS CONTAIN THE STARTING ADDRESS IN RAN USED TO STORE
DATA READ FRON THE BUBBLE t1ENORY, THE H-:L REGS MUST CONTAIN
AB'r'TE COUNTER !NO ICAYING THE HUNBER OF DATA BYTES TO BE
TRANSFERRED, THIS FliNCTION BEGINS BY ISSUING THE READ BUBBLE
NEMORY DATA COMMAND FOLLOWED BY POLLING THE STATUS REG
TO DETERMINE IF THE 72213 FIFO DATA BUFFER CONTAINS DATA
AVAILABLE FOR READ lNG, DATA IS TRANSFERRED UNTIL THE BYTE
:m ;
COUNTER OR mlE OUT LOOP COlliHER DECREMENTS TO ZERO, THE
322 ,:
PARAMETRIC REGS t'IUST BE LOADED WITH THE DESIRED VALUES PRIOR
323 ;
TO CALLING THIS miCTION,
324 ;
[)
; SAVE [l-E REGS
325 REAr,: PUSH
326
PUSH
B
; SAVE 8-C REGS
B,0FFFFH.: INITIALIZE TINE OUT LOOP COUNTER
327
LXI
A,12H .: LOAD A REG=. READ BUBBLE' t1Et'10RY DATA COMMAND
328
11'011
pRTAa1 ; ~jRITE, READ BUBBLE NEt'IORY DATA COt1t1AND
329
OUT
330 BUSI'RD: DCX
,:. DECRENENT TINE OUT LOOP, COLINTER
B
131
XRA
A
.: CLEAR A REG,
332
ORA
8
.: TEST B REG= aSH
ORA
333
C
.: TEST C REG= 00H
334
12
FINSHR ; IF ZERO,. iIt1E OUT ERROR, JIiP F1NSHR
335
PRTA01 ; REACo STATUS REG
IN
336
RLC
.: TEST BUSY BIT= 1
. :m
JNC
BU5YRD ; IF ZERO, CONTINUE POLLING BUS'r' BIT
338
; CONTINUED ON NEXT PAGE
339 $EJECT

6-116

AP·150

1515-II 8000/8085 MACRO ASSEflBLER, Vl II

LOC OBJ
08BA DBFF
118BC SF
08BD DRD011a
B8C0 DBFF
08C2 07
B8C3 D2DB08
B8C6 0B
0BC? AF
aecs B0
08C9 B1
08CA CADB08
BSCD C3BAe8
0808 OBFE
08D2 12
0803 13
9804 28
0805 AF
0806 B4 .
0SD7 B5
08D8 C2BA08
080B C1
0SDC 01
0BOO C9

340 POLLR(); IN
341
RRC
342
JC
343
IN
344
RLC
JNC
345
346
OCX
347
XRA
34B
ORA
349
ORA
350
JZ
351
JHP
352 RFIFO; IN
353
STAX
IN:':
354
355
OCX
XRA
356
ORA
357
358
ORA
359
JHZ
360 FINSHR; POP
361
POP
362
RET
363;
364 i
365 i
366 $EJECT·

PRTA01 ;
;
RFIFO i
PRTA01 ;
;
FINSHR . i
;
B
A
i
B
i
i
C
FINSHR i
POLLRD i
PRTA08 i
i
D
i
D
H
i
;
A
;
H
L
i
. POLLRD i
i
B
;
0

READ STATUS REG
TEST FIFO READY BIT= 1
IF FIFO READY= L JHP RFIFO
READ STATUS REG
TEST BUSY BiT= 1
IF ZERO, ERROR, Jt1P FINSHR
DECREMENT mlE OUT LOOP COUNTER
CLEAR A REG
TEST B REG= 00H
TEST C REG= 00H
IF ZERO, TitlE OUT ERROR, JHP FINSIR
CONTINUE POLLIt1G FIFO READY BIT
LOAD A REG WITH ONE BYTE FROM FIFO DATA BUFFER
STORE A REG IN REG O-E ADDRESS
INCREt1EI11 iH REGS TO NEXT ADDRESS IN RAM OECREflENT BYTE COUNTER
CLEAR A REG
TEST H REG= 00H
TEST L REG= OOH
IF BYTE COUNTER NOT ZERO, JtlP POLLRD
RESTORE B-C REGS
RESTORE iH REGS
i RETURN TO CALL

6·117

AP-150

INITIALIZE
TIMEOUT
LOOP COUNTER

ISSUE READ
BUBBLE MEMORY
DATA COMMAND

READ 7220
STATUS REG

READ LOOP

READ FIFO
1 BYTEXFER

DECREMENT
LOOP COUNTER

DECREMENT
BYTE COUNTER

RETURN
COMMENTS: MIN READ LOOP TIME ~ 21's.
MFBTR ~ 0:
MAX READ LOOP TIME ~ 201'5.'
MFBTR ~ 1:
MAX READ LOOP TIME ~ 801'5.
MINIMUM TIME OUT LOOP COUNTER ~ 0.S5ec
'ONLY FOR SINGLE PAGE AND LAST PAGE OF MULTI PAGE TRANSFERS.

Figure 15. READ

6·118

AP-150

1515-II S080/8085 MACRO A5SEl1BLER, V3. 0

367 ; ***1'************-***-***********-***********************"'********
368 ;
369; FUNCTI ON: ABORT
378.; INPUTS: BPK72 STATUS REG
371 ; OUTPUTS: I SSUE ABORT COMttAND TO BPI\72
.372 ;

A REG= BPK72 STATUS REG
CALLS:
NONE
374 ; DESTROYS: A, F/FS
375 ;
376.; DESCRIPTION: ABORT PRESENT COMttAN£), RESET BPK72
377 ;
AN ABORT C0I1tlAND IS ISSUED TO THE BPK72. AFTER ISSUING THE
:78 ;
cotlMAN£), THE BPI\72 STATUS REG IS POLLED UNTIL AN OP-COMPLETE,
379 i
4f)H, HAS BEEN READ OR THE TIME OUT LOOP COUNTER DECREl1ENT5
38B ;
TO ZERO. THE ABORT FUNCTION RETURNS THE VALUE OF THE BPK72
381 ;
STATUS REG TO THE CALLING ROUTINE VIA THE 8B85'S A REG. ONLY A
382 ;
STATUS OF 40H INDICATES A SUCCESSFUL EXECUTION OF THE ABORT
383 ;
FUNCTI ON.
384 ;
385
PUBLIC ABORT ; DECLARE PUBLIC FUNCTION
386 ABORT: PUSH
D
i. SAVE D-E REGS
387
PUSH
B
i SAVE B-C REGS
388
LXI
D; 0FFFFH; INITIALIZE TIME OUT lOOP COUNTER
MYI
B,40H; lORD B REG= 4f)H, OP-COMPLETE
389
~JIII
A, 19H ; lOAD A REG= ABORT CONMAND
390
OUT
PRTA01; WRITE ABORT COtiMAND
391
PRTA01; READ STATUS REG
392 BUS'fA: IN
RlC
.; TEST BUSY BIT= 1
393
394
JC
POllA; IF BUSY: L POLL STATUS REG FOR 40H
DC~:
D
; DECREMENT TIME OUT lOOP COUNTER
395
XRA
A
; CLEAR A REG
396
ORA
D
; TEST D REG= 00H
397
ORA
E
.; TEST E REG= OOH
398
399
JflZ
BUS'r'A; IF NOT ZERO, CONTINUE POLLING ABORT COMttAND
J~lP
RETA
; TH1E OUT ERROR, RETURN
400
401 POllA: IN
PRTA01 i READ STATUS REG .
;~RA
B
; TEST STATUS= 4f)H, OP-COt1PLETE
.402
403
JZ
RETA
; IF OP-GOMPLETE, JI1P RETA
404
DC~:
D
.; DECREI1ENT TII'lE OUT lOOP COUNTER
405
XRA
A
; CLEAR A REG
ORA
D
; TEST D REG= 00H
.406
407
ORA
E
i TEST E REG= B0H
JNZ
POllA; IF NOT ZERO, CONTINUE POLLING ABORT CO~1MAND
408
409 RETA: POP
B
i RESTORE B-C REGS
POP
D ; RESTORE D-E REGS
410
IN
PRTA01 , READ STATU5 REG
411
412
RET
i RETURN TO CALL
413 .;
414 .;
415 ;
416 $EJECT

:m;

08DE
08DF
B8E0
B8E:$
BSE5
eSE?
BBE9
BeEB
08EC
B8EF
08F0

D5
C5
llFFFF
0648

D:$FF

DBFF
07
DAF908
18
AF,
08F1 82
08F2 83
088 C2E908
0SF6 C30609
08F9 DBFF
08FB AS
08FC COO609
08FF lB
0900 AF
0901 B2
0902 83
0903 C2F908
0906 C1
0907 Dl
0908 DBFF
090A C9

6·119

AP-150

....

INITIALIZE
TIMEOUT
LOOP COUNTER
READ 7220
STATUS REG

ISSUE
ABORT
COMMAND,

: • .;

,', READ7220
STATUS REG

D~:=':i~~~T,
, LOOP COUNTER •

DECREMENT
TIMEOUT
LOOP COUNTER

READ 7220
STATUS REG

COMMENT: MINIMUM TIME OUT LOOP, COUNT = 1001'S.

Figure 16. ABORT

6-120

AP-150

ISIS-II 8080/8985 MACRO ASSEMBLER, 113. 0

************'!'*************-***********************-*---*******

418 )
419) FUNCTION:
420) INPUTS:'
421 ;
422 )
423 ) OUTPUTS:
424 )
425; CALLS:
426 )
427 i
428 ;'
429 ) DESTROYS:

WRBUBL
B-C REGS, STARTING ADDRESS OF PARAMETRIC REGS IN RAM
D-E REGS, STARTING ADDRESS OF DATA IN RAM
BPK72 STATUS REG
WRITE DATA TO BUBBLE MEMORY
A REG= BPK72 STATUS REG
FIFORS
INTPAR
BYTCNT
WRIiE
It FIFS

430 )
431) DESCRIPTION: WRITE BUBBLE MalOR... DATA
432 )
THE B-C REGS COflTAIN THE ADDRESS TO THE FIRST OF FIIIE
433 ;
CONTIGUOUS MalOR\' LOCATIONS IN RAM. THE DATA ADDRESSED
434 )
BY THE B-;C REGS IS USED TO LOAD THE PARA~lETRIC REGS.
435 ;
THE D-E REGS CONTAIN THE STARTING ADDRESS IN RAM OF
436 ;
DATA TO BE WRITIEN INTO THE BUBBLE t1EMORY. GIllEN THE DATA
437 j
IN RAt1 USED TO LOAD THE PARAMETRIC REGS, THIS FUNCTION
438 ;
WILL RESET THE 7220 FIFO, LOAD THE PARAMETRIC REGS,
439 j
COt1PUTE THE BYTE COUNTER, AND COpy THE DATA FROM RAM INTO
440 ;
THE BUBBLE ~lEMORY. WRBUBL RETURNS THE VALUE OF THE BPK72
441 ;
STATUS REG TO TtiE CALLING ROUTINE VIA THE 8085'5 A REG.
442 ;.
ONL if . A STATUS OF 40H OR 42H INDICATES A SUCCESSFUL
443 ;
EXECUTION OF WRBUBL.

0916 Cl
0917 COO008
091A CD4008'
0910 CD6A98
0920 C5

445
PUBLIC
446 WRBUBL: PUSH
447
PUSH
448
i1VI
449
CALL
450
XRA
451
JNZ
452
POP
453
CALL
454
CALL
455
CALL
456
PUSH

457

WRBUBL . ;
H
j
B
j
B, 40H j
FIFORS j
B
j
RETWR i

DECLARE PUBLIC FUNCTION
SAllE H-L REGS
SAVE B-C REGS
LOAD B REG= 40ft OP-COMPLETE
CALL FIFORS, WRITE FIFO RESET COMMAND
TEST FOR STATUS= 40H, OP-Cot1PLETE
IF NOT ZERO, FIFO ERROR. Jt'lP RETWR
B
; RESTORE B-C r.EGS
INTPAR j CALL INTPAR, LOAD PARA/'lETRIC REGS
B'fTCNT ; CALL BYTCNT, COt1PUTE BYTE COUNTER
WRITE ; CALL vIRITE, WRITE BUBBLE DRTR
B
;. SAllE B-C REGS
). COOINUED ON NEXT PAGE

458 $EJECT

6-121

AP-1S0

ISIS-I I 8080/8885 IfACRO ASSEHBlER, VI 0
LOC OBJ

LINE

459
LXI
469 LOOPWR: IN
461
RLC
462
JNC

892A 28
0928 AF
992C B4

469
479
471
472 ;
473 ;

0921 21FFFF
9924 DBFF
9926 07
0927 1)23109

463

BPK72

POP
IN
RET

H,0FFFFH;
PRTA91 ;
;
RETWR 'i
H
;
A
;
H
;
L
i
LOOPWR ;
B
;
H
;,
PRTA01 .'
i

INITIALIZE TIME OUT LOOP COUNTER
READ STATUS REG
TEST FOR BUSY BIT= 1
IF ZERO,' NOT BUsy, Jl'lP RETWR
DECREMENT TIME OUT LOOP COUNTER
CLEAR A. REG
TEST H REG= 00H

TEST L REG= 9eH
CONTINUE POLLING STAM REG
RESTORE B-C REGS
RESTORE H-L REGS
READ STATUS REG
RETURN TO CALL

INIT. TIME
OUT LOOP
COUNTER

READ 7220
STATUS REG

DECREMENT
LOOP COUNTER

. COMMENT: MINIMUM TIME OUT LOOP COUNTER = 5MS

Figure 17. WRBUBL

6·123

AP-150

ISIS-:rr 8080/89B5 MACRO ASSEMBLER;' V3: 9

476.; ********************--*************************~--***
477 i ,
478; FUNCTION: RDBUBL
'
479; INPUTS: B-C REGS, STARTING ADDRESS o~ PA~Ai1ETRW REGS IN RAI'l
480 ;
D-E REGS, STARiING ADDRESS IN RAI'l
481 ;
BPK72 STAM REG
482 j
READ DATA FROM BUBBLE tlEMORI' .
483 i OUTPUTS: WRITE DATA TO RAM
484 ;
A REG= BPK72 STATUS REG
485 i CALLS:
FIFORS
4B6 i
INTPAR
487 i
BI'TCNT
488 ;
READ "
489 i DESTROI'S: A, FIFS
490 ;
491 i DESCR I PHON: READ BUBBLE MEtlORY DATA
492 ;
THE B-C ,REGS CONTAIN THf ADDRESS TO THE FIRST OF FlYE
493 i
CONTIGUOUS MEtlORI' LOCATIONS IN, ,RAI'l,· THE DATA ADDRESSED
494 ,;
BI' THE B-C REGS IS USED TO LOAD. THl; PARAMETRIC REGS, THE IH
495 ;
REGS CONTAIN THE STARTING ADDRESS IN RAtl USED TO STORE
496 j
DATA PEAD FRotl THE BUBBLE MEtlORY, GIYEN' THE DATA IN RAI'l
497 i
USED TO LOAD THE PARAMETRIC REGS, ," THIS, FUNCTiON WILL RESET
498 i
THE 7220, FIFO, LOAD THE PARAMETRIC REGS, COMPUTE THE
499 i
BYTE COUNTER, AND COPY THE' DATA FROM THE BUBBLE MEMORY INTO
500 j
RAM, RD8UBL RETURNS THE VAlUE OF THE BPK72 STATUS REGISTER
501 i
TO THE CALLING ROUTINE lilA THE 8085'S.A REG" ONLY A STATUS
502 j
OF 49H OR 48H WITH ERROR CORRECTION'INDICATES A SUCCESSFUL
503 ;
EXECUTION OF RDBUBL
5134 i

50S
9936 E5
C5
9918 9649
993A CDBe8
993D A8
993E C25C09
9941 C1
0942 CD0008
0945 CD4008
0948 CDA408
094B C5

P,UBLIG 'Rb8UBL ;~. :DECLARE PUBLIC FUNCTION

5136 RDBUBL: PUSH "H"
507
PUSH . B' ,~
598
MVI
'B,,40H'
509
CALL .' FIFORS
519
XRA
B .. '..
511
JNZ' RETRD
512
POP
B
513
CALL
mTPAR
514
CALL
BI'TCNT
515
CALL
READ
516
PUSH
B .
517
518 $EJECT.·"

SAVE H-L REGS
i'SAVEB-C REGS
-;'lOAD 'B REG= 4~.OP-COMPLETE.
.
i CALL FIFORS, WRITE FIFO RESET COt1~AND
;i TEST FOR STAM= 40H. OP-COMPLETE
i IF NOT ZERO"FIF.O ERROR. Jt1P RETRD
i RESTORE B-C REGS
i CALL' INTPAR, LOAD PARAMETRIC REGS
j CALL .B'r'TCNT, CONPUTE BYTE COUNTER
i CALL REA[), READ BUBBLE DATA·
.; SAVEB-C REGS
.,'
. j CONTINUED ON NExT PAGE.
" ,','.,,: ..
i

6·124

AP-150

I5I5-II S08B/BeS5 MACRO A55E11BLER; \/3. 0

. LOC OBJ
094C
894F
0951
0952
0955
0956
0957
095S
0959
095C
095D
095E
0960

21FFFF
DBFF
07
D25C09
2B
AF
B4
B5
C24F09
(1
El
DBFF
C9

LINE
519
520
521
522
523
524
525
526
527
52S
529
530
531
532
533
534
535

BPK72

PAGE

SOURCE 5TATEHENT
LXI
LOOPRD: HI
RLC
JNC
DCX
XRA
ORA
ORA
JNZ
RETRD: POP
POP

RET

H, BFFFFH.o
PRTAB1 .'
;
RETRD ;
H
;
A
.
;
H
;
L
LOOPRD ;
.
B
H
.'
PRTA01 ..
.

INITIALIZE TItlE OUT LOOP COUNTER
READ STATUS REG
TEST FOR BUSY BIT= 1
IF ZERO, NOT BUSY., JrlP RETRD
DEeREr'lENT TU1E OUT LOOP COLINTER
CLEAR A REG
TEST H REG= B0H
TEST L REG= 00H
CONTI NUE POLLING STATLIS REG
RESTORE B-( REGS
RESTORE H-L REGS
READ STATUS REG
RETURN iO CALL

..
;
;
$EJECT

6-125

INIT. nME
OUT LOOP
COUNTER

STATUS REG

READ 7220
STATUS REG

DECREMENT
LOOP COUNTER

COMMENT: MINIMUM nME OUT LOOP COUNTER

ISIS-II 8080/B0S5 MACRO ASSEMBLER, V3. 0

;************-*------*****-----

536
537 ;
538 i FUNCTION: INBUBL

B-C REGS, 5TARTING A!>DRESS OF PARAtURIC REGS IN Rtl1
BPK72 STATUS REG
541 i OUTPUTS: A REG= BPK72 5TATUS REG
542 i CFtLLS:
ABORT
543 ,;
INTPAR
544 i DESTROYS: A" FIFS
545 ;
546 i DESCRIPTION: INITIALIZE THE BPK72
547 ;
THE B-C REGS CONTAIN THE ADDRESS TO THE FIRST OF FIVE CONTIGUOUS
548 ;
MEMORY LOCATI ONS I N RA~1. THE DATA A!>DRESSED B~' THE B-G REGS
549 i
IS USED TO LOAD THE PARAI'lETRIC REGS, THIS FUNCTION WILL WRITE
550 ;
THE PARAI1ETRIC REGS FOLLOWED BY ISSUING A BUBBLE MEI10RY
551 ;
INITIALiZATION CO~1t1AND, AFTER ISSUING THE COtlMAND, THE BPK72
552 ;
STATUS REG IS POLLED UNTIL AN OP-Cot1PLETE, 40H, IS READ OR THE
553 ;
TIl'lE OUT LOOP, COUNTER DECREliENTS TO ZERO, THIS COHtIAND MUST
554 ;
PRECEED ALL OTHER COMI'1ANDS AFTER POWERING UP THE BPK72, INBUBL
555 ;
RETURNS THE VALUE OF THE BPK72 5TATUS REG TO THE CFtLLING ROUTINE
556 i
VIA THE 8085"5 A REG, ONLY A STATUS OF 40H INDICATES A SliCCESSFUL
557 i
EXECUTION OF HIBUBL.

539; INPUTS:

540 ;

S58
9961 1>5
0962 C5
0963 0640
9965 CDDEB8
0968 AS
0969 C29709
096C C1
0960 CD0808
0970 C5
0971 0640
0973 iiFFFF

0976 3Ell
0978 D3FF

559
560 I NBUBL:
561
562
563
564
565
566

567
568
569
570
571
572
573
574 $EJECT

PUBLIC
PUSH
PUSH
MVI
CALL
XRA
JNZ
POP
CALL
PUSH
MYI
LXI
MVI
OUT

INBUBL ;
D
i
B
i
B,40H i
ABORT i
B
;
RETIN ;
B
;
INTPAR ;
B
i
8., 40H ;
D,,0FFFFH;
A"l1H ;
PRTA01 i
i

DECLARE PUBLIC FUNCTION
SAVE D-E REGS
SAVE B-C REGS
LOAD B REG= 49H, OP-COMPLETE
CALL ABORT C0I111AND
TEST STATUS= 4f)H, OP-COt1PLETE
IF ZERO, OP-CONPLETE, CONTINUE
PARAMETRIC P.EGS STARTING ADDRESS IN REG B
CALL INTPAR, LOAD PARAI1ETRIC REGS
SAllE B-C REGS
LOAD B REG: 40H, OP-COI1PLETE
INITIALIZE TIt1E OUT LOOP COUNTER
LOAD A REG= INITIALIZE Cot'1I1AN!)
WRITE INITIALIZE CO~lMAND
CONTINUED ON NEXT PAGE

6-127

AP-150

ISIS-II 8080/8085 MACRO A5SEtlllLER, V3, 0

LOG OBJ
097A
097C
097D
13980
0981
0982
e98~

0984
0987
098R
e98c.
9980
0990
0991
0992

13993
0994
0997
0998
13999
0998

DSFF
07
DA8A09
18
AF
82
83
C27A09
09709
DBFF
AS
CA9709
is
AF
82

575 BUSYIN: IN
576
RlC
577
JC
[lex
578
579
XRA
580
ORA
ORA
581
582
JNZ
583
JNP
584 POLLIN: III
585
XRA
586
JZ
DC~;
587
588
XRA
589
ORA
590
ORA
591
JNZ
592 RETIN: POP
POP
593
594
IN
595
RET
596 ;
597;
598 $EJECT

PRTA0i
POLLIN
D
A
D
E
BUSYIN
RETIN
PRTA01
B
RETIN

D
A
D
E
POLLIN

B
D
PRTI101

j "READ STATUS REG .
; TEST BUSY BIT= 1
; IF BUSY= 1, POLL STATUS REG FOR 40H
; DECREt-1ENT TIME OUT LOOP COUNTER
,; CLEAR A REG
; TEST D REG= 00H
,; TEST E REG= 00H
j. IF NOT ZERO, CONTINUE POLLING THE INITIALIZE C0I1MAND
i mlE OUT ERROR, RETURfl
; REAr, STATUS REG
; TEST STATUS= 40H, OP-CONPLETE
i IF OP-CONPLETE, JNP RETIN
; DECREt1ENT mfE OUT LOOP COLINTER
; CLEAR A REG
i TEST' D REG= 00H
; TEST E REG= 00H
;' IF NOT ZERO, CONTINUE POLLING' INITIALIZE COMNAND
; RESTORE B-C PEGS
.
; RESTORE D-"E' REGS
; 'READ STATUS REG
; RETURN TO CALL

6·128

AP-150

INITIALIZE '
TIME OUT LOOP
COUNTER

ISSUE BUBBLE
MEMORY INIT,
COMMAND,

"READ 7220
STATUS REG

READ 7220
STATUS REG

YES

DECREMENT
LOOP COUNTER

COMMENT: MINIMUM. TIN!E OUT !pOP ,COUNTER ~. 200MS

ISIS-II 8089/B0B5 I1ACRO A55E11BLER, 1,11 0

II99C C5
099D
999£
099F
09A1

D5
E5
3EBO
D3FF

99R303
99R4 03
99R5 IlA
09A6 0610
99A8 B0
99A9 D3FE
99fIB AF
99RC D3F.F
09AE 0640
99B0 CDDes
8983 AS
0984 C2238A

PAGE

SOURCE STATB1ENT

688 ;
681;
602;
603 ;
604 i
605 i
606 ;
607 ;
60S i
609 ;
610 ;
611;
612 i
613 ;
614 ;
615 ;
616 ;

619

BPK72

FUNCTI ON: BOOTUP
INPUTS: S-C REGS, STARTING ADDRESS OF PARAMETRIC REGS.IN RAM
D-E REGS, STARTING AOORESS OF BOOT LOOP CODE iN RAI1
BPK72 STATUS REG
OUTPUTS: WRITE BUBBLE MEMOR't' BOOT LOOP
A REG: BPK72 STATUS REG
CALLS:
FIFORS
.
INTPAR
DESTRO't'S: A, FIFS
DESCRIPTION: WRITE BUBBLE MOOR't' BOOT LOOP
THIS ~UNCTION WILL WRITE THE BOOT LOOP CODE INTO THE· 7110
BUBBLE HEMOR't'. THE D-E REGS PROVIDE THE ADDRESS TO THE FIRST
OF FORTY CONTIGUOUS B'r'TES IN RAM THAT CONTAIN THE BOOT LOOP
CODE. THE B-C REGS CONTAIN THE ADDRESS TO THE FIRST OF FIVE
CONTIGUOUS i'IEI1ORY LOCATIONS ALSO IN RAM. THE DATA ADDRESSED
BY THE B-c REGS IS USED TO LOA!) THE PARAHETRIC.· REGS..
NOTE THAT THE PARAf1ETRIC ENABLE REG WRITE BOOT' LOOP
BIT IS AUTotlATICALL't' SET AND A FORT't'-FIRST BYTE OF ZERO
IS WRITTEN TO THE FIFO DATA BUfFER TO AIlOID A TIMII-li ERROR
BEFORE A RETURN IS EXECUTED, THE PARAMETRIC ENABLE REG. IS
RESTORED TO ITS VALUE PRIOR TO CALLING BOOTIJP. BOOTIJP RETURNS
THE VALUE OF THE BPK72· STATUS REG TO .THE CALLING ROUTINE VIA
THE 8085'5 A REG.ONL~ A STATUS OF 40H OR 42H INDICATES
.
A SUCCESSFUL EXECUTION OF BOOTUP.

624 .;
625 ;
. 626 i'
627
.
628 BOOTuP:
629
638
631
.
. 632
633
634
635
636
637
638
639
648
641
642
643
644
645
, 64i? $EJECT

PUBLIC SOOTIJP i
pusH B
.i
PUSH
D
;
PUSH
H
;
MYI
A,OOH;
OUT
PRTA01 i
INX
B
INX.
B
i
LDAX
B.
;
MYI
B,10H .;
ORA,
B
;
OUT
PRTAOO i
;
XRA
A
OUT
PRTA01 j
B,40H i
MYI
CALL
FIFORS j
i
XRA
B
JNZ
RETBT i
)

DECLARE PUBLIC FUNCTION
SAVE B-C REGS
SAVE' D-E REGS
SAVE H-l REGS ,
,
.,
LOAD A REG: 0DH" 7220 RAe ENABLE REG AoDRESS
WRITE 7220 RAe WITH ENABLE REG ADDRESS
INCREfolENT B-c REGS TO ENABLE REG RAM A!)DRESS
.LOAD.A REG= ENABLE REG FROH RAH
LOAD S REG: BOOT LOOP ENABLE MASK '.
SET BOOT LOOP ENABLE BIT
WRITE ENABLE REG
CLEAR A REG
LOAD 7220 RAC WITH FIFO DATA. BUFFER ADDRESS
LOAD B REG: 4011, OP-CQHPLETE
CALL FIFO RESET
TEST STATUS= 4BH, OP-COHPLETE
IF NOT ZERO, ERROR, JMP RETBT '
CONTINUED. ON NEXTPAGE

6-130

AP-150

ISIS-II 8989/6085 MACRO ASSEl'IBLER, V10
lOC OBJ
09B7 0E28
89B9 3EFF
09BB D3FE
09BD 0D
09BE C2BB89
09C1 21FFFF
89C43E16
09C6 D3FF
09C8DBFF
09CA 07
09CB DAD889
09CE 2B
09CF AF
0900 B4
09D1 85
09D2 C2C8S9
09D5 C3238A
09D8 DBFF
09DA AS
090B CAES!l9
09DE 2B
09DF AF
09E0 B4
09E1 B5
09E2 CA238A
B9E5 C3D899

647
MVI
C,2BH ; lOAD C REG= 2BH, BYTE COUNTER: 40 DECIHAL
A,0FFH ; lOAD A REG= FFH
648
MIII
649 ALlFFS: OUT
PRTAOO ; WRITE A REG INTO FIFO DATA BUFFER
; DECRE~1ENT BYTE COUNTER
650
DCR
C
651
ALLFFS ; IF BYTE COUNTER: ZERO, CONTINUE
JHZ
H, 0FFFFH; INITIALIZE TIME OUT lOOP COUNTER
652
LXI
653
MVI
; lOAD A REG: WRITE BOOT lOOP REG CortlAND
A,~
654
OUT
PRTA01 ; WRITE, WRITE BOOT lOOP REG COt1MAND
PRTA01 ,; READ· STATUS REG
655 BUSI'B: IN
656
; TEST BUSY BIT= 1
RlC
657
JC
POllBR ; IF .BUSY= 1, POLL STATUS REG FOR 48H
658
DCX
H
; DECREMENT TIME OUT lOOP COUNTER
XRA . A
659
; CLEAR A REG
; TEST H REG= 0eH
660
ORA
H
; TEST l REG= 00H
661
ORA • l
662
BU5'r'B ; IF NOT ZERO, CONTINUE POLlING WRBLRS Cot11AND
JHZ
Jt1P
663
RETBT ; TIME OUT ERROR, RETURN
664 POLLBR: IN
PRTA01 ; READ STATUS REG
665
XRA
; TEST STATUS= 48H
B
jZ
; IF ZERO, CONTINUE, OP-COI'IPLETE
666
CONT
; DECREMENT mIE OUT lOOP COUNTER
667
DCX
H
668
XRA
; CLEAR A REG
A
.; TEST H REG: !l0H
669
ORA
H
670
. ; TEST l REG: 00H
ORA
l
671
JZ
RETBT ) IF ZERO, TIME OUT, ERROR
672
JHP
POllBR ; CONTINUE POLLING WRBLRS ·COHt1AND
; CONTINUED ON NEXT PAGE
673
674 $EJECT

6·131

AP-150

BPK72

1515- I I S080/8085 MACRO ASSEMBLER., III 0
LOC OBJ
09E8 CDB08
09ES A8
09EC C22313A
09EF 0E28
09F11A
09F211
.39F:; D1FE
09F5 tID
09F6 C2F109
09F9 AF
09FA C'1FE
09FC 2iFFFF
09FF 0EFD
0A01 3E1?
0A0} D3FF
eR05 DBFF
0RB? 07
0A08 DA150A
0A13B 28
0A0C AF
0A0D 84
13R0E 85
0A0F C2050A
0A120230R
ORi5 DBFF

(lAi7 Ai
0A1S AS
0A19 CADOR
eAlC 2B
0AlD AF
eRiE 84
(lAiF 85
00213 C2i50A
€IRD El
13R24 D1
0A25 C1
13A26 W0008
0A29 [JBFF
OA28 (:9

CALL
;~RA
676
677
JNZ
678
679 BLCODE: LDAX
680
INX
681
OUT
682
DCR
683
JNZ
684
XRA
685
OUT
686
LXI
687
t'lVI
688
11111
689
OUT
690 BUS','Bt.': IN
691
RLC
692
SC
693:
DCX
694
;~RA
695
ORA
696
ORA
697
1HZ
698
JHP
699 POLLBL: IN
700
ANA
701
XRR
702
JZ
10:;
DCX
704
;~RA
705
ORA
706
ORA
707
JNZ
708 REiBT: POP
709
POP
710
POP
711
CALL

712

RET

FIFORS
B
RETBT
C, 28H
r,
;
D
PRTAee ;
C
BLCODE
A
PRTA00 ;
H, 0FFFFH;
C, 0FDH ;
A,17H
PRTA01 ;
PRTAI3i
;
POLLBL
H
A
H

L
BUSYBL
RETBT
PRTA01
C
B
RETBT
H
A
H

L
POLLBL
H

D
B
INTPAR
PRTA01

CALL FIFO RESET
TEST STATUS= 40H
IF NOT ZERO, ERROR, Jt'lP RETBT
LOAr, C REG= 28H, BYTE COUNTER= 40 DEC I MAL
LOAD A REG FRot'l D REG ADDRESS
INCREMENT D REG TO THE Nm ADDRESS
vlRHE BOOT LOOP CODE INTO FIFO DATA BUFFER
DECREflENT BYTE COUNTER
IF NOT ZERO, JflP BLCODE
CLEAR A REG
vlRITE 41ST BYTE OF ZERO INTO FIFO DATA BUFFER
LORC' TH1E OUT LOOP COUNTER
t1RSK, NASK Our PARm' BIT
LOA[) A REG= WRITE 800T LOOP COMMAND
WRITE; WRITE BOOT LOOP cot-U'lAND .
REAr, STATUS REG
TEST BUSY BIT= 1
IF BUSY=1, POLL STATUS REG FOR OP-COI'1PLETE
r,ECREflENT TIME OUT LOOP COUNTER
CLEAR A REG
TEST H REG= 00H
; TEST· L REG= 00H
; IF NOT ZERO., CONTINUE POLL ING THE WRBL COMMAND
; TI NE OUT ERROR, RETURN
READ STATUS REG
RESET BIT 1, PARITI-' BIT
TEST STATUS= 40H OR 42H, OP-CO~lPLETE
; IF ZERO, CONTINUE, OP-COMPLETE
; DEeREr-lENT W1E OUT LOOP COIJNTER
; CLEAR A REG
I
TEST H REG= 00H
TEST L REG= 00H
; COmINlIE POLLING WRITE BOOT LOOP COf1t'lAND
RESTORE H-L REGS
RESTORE D-E REGS
RESTORE 8-C REGS
CALL INTPAR.. LOAD iHE PARAMETRIC REGS
; REAC, STATUS REG

714;
716 ,
717 $EJECT

INITIALIZE
BYTE COUNTER"
40 DECIMAL,
, 28H

DECREMENT
BYTE COUNTER

READ 7220
STATUS REG

DECREMENT
LOOP COUNTER

READ 7220
STATUS REG

COMMENT: MINIMUM TIME OUT LOOP COUNTER

lOOMS

Figure 20 (Con't). BOOTUP

6·134

AP-150

ISIS-I I S0S0/S0S5 MACRO ASSEl1BLER, V3. 0

LOC OBJ

LINE

002C
0A2D
6A2E
0A2F
0031
€lA33
0A36
0A37
0A3A
0A3B
0A3E
0A40
0A42
flA44
0A45
0A48
0A49
0A4A
004B
0A4C
0A4F

C5
1)5
E5
0640
eE28
COEes
AS
C26A0A
134
21FFFF
3E18
D3FF
DBFF
07
DA52flA
28
AF
B4
B5
C2420A
C36A0A

PAGE

SOURCE STATEl1EtlT

718 ;
719 ;
720;
721 i
722 ;
723 ;
724 ;
725 .;
726 ;
727 ;

728
729
730
731
732
7:53
?34
735

BPK72

*****************************-_******-******-____
FUNCTI ON: RDBOOT
INPUTS: D-E REGS, STARTING ADDRESS IN RAM
BPK72 STATUS REG
READ BUBBLE ~1EHORY BOOT LOOP
OUTPUTS: COPY BUBBLE ~IEHORY BOOT LOOP TO RAM
A REG= BPK72 STATUS REG
CALLS:
FIFORS
DESTROYS: A, FIFS

;"
i
i

.;
;

;
;

DESCRIPTION: READ BUBBLE MEt'lORY BOOT LOOP
THE D-E REGS CONTAIN THE STARTING ADDRESS TO THE FIRST OF 40
CONTIGUOUS MEMORY LOCATIONS IN RAM THAT WILL BE .LOADED WITH
A COPY OF THE BOOT LOOP CODE. RDBODT RETURNS THE VALUE OF THE
BPK72 STATUS REG TO THE CALLING ROUTINE lilA THE 8085'S A REG.
ONLY A STATUS OF 40H INDICATES A SUCCESSFUL EXECUTION OF RDBOOr.

PUBLIC
737 RDBODT: PUSH
738
PUSH
m
PUSH
740
HVI
741
HVI
742
CALL
743
XRA
744
..TNZ
745
INR
746
LXI
747
tiVI
748
OUT
749 BUSYRB: IN
750
RLC
751
JC
752
Dex

RDBOOT ;
B
i
D
i
H
;
B, 40H ;
C, 28H ;
FIFORS ;
B
.;
RETRDB ;
B
;.
H, BFFFFH;
A, iBH .;
PRTAI31;
PRTAOl ;
;
BTLPRD i
H
i
A
i
H
;
L
;
BUSYRB ;
RETRDB .;
;

DECLARE PUBLIC FUNCTION
SAllE B-C REGS
SAVE D-E REGS
SAVE H-L REGS
LOAD B REG= 4aH, OP-COMPLETE .
LOAD C REG= 28H, BYTE COUNTER= 40 DECIMAL
CALL FIFO RESET
TEST STATUS: 401-\, OP-COMPLETE
I F NOT ZERO, ERROR, JMP RETRDB
B REG= 41H, OP-COMPLETE, FIFO FULL
INITIALIZE TIME OUT LOOP COUNTER
LOAD A REG= READ BOOT LOOP COI'1MAOO
WRITE, READ BOOT LOOP COt-lMAOO
READ STATUS REG
TEST BUSY BIT= 1
IF BUSY= 1.. POLL STATUS REG FOR 41H
DECREt1ENT TIME OUT LOOP COUNTER
CLEAR A REG
TEST H REG= OOH
TEST L REG= BaH
IF NOT ZERO, CONTINUE POLLING RDBL COMMAND
TIME OUT ERROR, RETURN
CoNTINUED ON NEXT PAGE

6-135

AP-150

1515-I I 8080/8085 I1ACRO A55El'1BLER.. V3. 0

LOG 08J
0A52
BA54
BA55
BA5S
0A59
BA5A
BA5B
eAse
BA5F
8A62
0A64
0A65
0A66
8A67
0A6A
SA6e
8R6D
0A6E
0A6F

DBFF
A8
CA620A
28
AF
B4
B5
CA6A0A
C:£520A
DBFE
12

D
aD
C2620A
DBFF
E1
D1
C1
C9

76@ BTLPR!): IN
761
XRA
762
J2
76:S
DCX
764
XRA
765
ORA
766
ORA
767
12
768
Jt'lP
769 FIFORD: IN
770
STA:~
771
WX
772
OCR
773
JNZ
774 RETRDB: IN
775
POP
POP
776
POP
777
778
RET
779 i
780 $EJECT

PRTA01
B
FIFORD
H
A
H
L
RETRDB
BTLPRD
PRTA00
D
D
C
FIFORD
PRIA01
H
D
B

.: READ STATUS REG
.: TEST STATUS= 41H, OP-COtlPLETE.. FiFO FULL
.: IF ZERO, JNP TO FIFO READ
i DECREI'lENT TINE OUT LOOP COUNTER
i CLEAR A REG
i TEST H REG= 0aH
.: TEST L REG= 00H
; IF ZERO, TItlE OUT, ERROR
; CONTINUE POLLING RDBL CONI1AND
.: READ FIFO DATA BUFFER
; WRITE RAt'l AT ADDRESS IN D REG
,: INCREMENT D REG TO NEXT RAM ADDRESS
; DECRENENT B','TE COUNTER
.: IF NOT ZERO, J~lP FIFO REA[) .
'.: READ STATLIS REG
,: RESTORE H-L REGS
; RESTORE D-E REGS
RESTORE B-C REGS
i RETURN TO CALL

6-136

AP-150

INITIALIZE
BYTE COUNTER
40 DECIMAL
2BH

INITIALIZE
TIMEOUT
LOOP COUNTER

ISSUE READ
BOOT LOOP
COMMAND

READ 7220
STATUS REG

READ FIFO
1 BYTE XFER

DECREMENT
BYTE COUNTER

YES

DECREMENT
LOOP COUNTER

DECREMENT
LOOP COUNTER
YES

YES

READ 7220
STATUS REG

COMMENT: MINIMUM TIME OUT LOOP COUNTER

ISIS-II 888B/8985!1ACRO ASSEI1BLER,\l10

LDC OBJ

BA79
BA71
BA72
BA74
BA76
BA79
BA7A
BA7D
BA7E
0A89
BA81
BA82
BABS
BAB6
0A87
9AB9

C5
DS
9640
BE28
C01398
AS
C28S0A
1A
D3FE
13

781 ;*-******-------**~_
782 ;
783 ; FUNCTION: WRFIFO
784; INPUTS: O-E REGS, STARTING ADDRESS OF DATA IN RAM
7BS ;
BPK72 STATUS REG
786 ; OUTPUTS: WRITE 40 BYTES IN THE BPK72 FIFO DATA BUFFER
787 ;
A REG: BPK72 STATUS REG
7BB ; CALLS:
FIFORS
7B9 ; OESTROYS: A, FIFS
790 ;
791 ; DESCRIPTION: WRITE 7229 FIFO DATA BUFFER
.
792 ;
THE D-E REGS PROYIDE THE ADDRESS TO THE FIRST OF 40 CONTIGUOUS
mj
BYTES IN RAM rHAT CONTAIN DATA TO BE LOADED INTO THE BPK72 FIFO
794 j
DATA BUFFER. WRFIFO WILL TRANSFER THE DATA FROI1 RAM TO THE FIFO
795 ;
DATA BUFFER. WRFIFO RETURNS- THE VALUE OF THE BPK72 STATUS REG
796 j
TO THE CALLING ROUTINE VIA THE 8085'5 A REG. ON!..Y A STATUS OF
797 j
. 41H OR 43H INDICATES A SUCCESSFUL EXECliTION OF WRFIFO.·.
798 j
799
PUBLIC WRFIFO ; DECLARE PUBLIC FUNCTION
; SAVE B-C REGS
see WRFIFO: PUSH B
; SAVE D-E REGS
801 •
PUSH
0
802
l'1li1
B,40H .; LOAD B REG: 400, OP-COI1PLElE
803
MIll· C, 2BH ; LOAD C REG: 2BH, INITIALIZE LOOP COUNTER
804
CALL
FIFORS ; .cALL FIFORS, WRITE FIFO RESET COItIAND
805
. XRA
B
; TEST FOR STATUS REG: 401-1, OP-COMPLETE
806
JNZ· RETI.JF ; IF NOT zERo, FIFO ERROR, Ji'P RETWF .
; LOAD A REG FROI1 D-:-E REG ADDRESS
B07 INFIFO: LOAX
0
888.·OUT
PRTAOO jWRlTE A REG TO 7220 FIFO DATA· BUFFER
; INCREMENT D-E REGS TO NEXT ADDRESS IN RAH
~9INX
0
i DECREMENT LOOP COUNTER ' .
810.
OCR
C
811
JNZ
INFIFO j IF LOOP: COUNTER NOT ZERO, Jt1PINFIFO
; .RESTORE D-E REGS
812 RETWF: POP
0
813
POP
B
; RESTORE B-C REGS
B14
IN
PRTA01 ; READ STATUS REG
815 .
RET
; RETURN TO CALL
816 ;
B17 ;
81B j
B19 $EJECT

. ;.,
.6·138

AP-150

INITIALIZE
LOOP COUNTER ~
40 DECIMAL, 2BH

WRITE FIFO
1 BYTEXFER

DECREMENT
LOOP COUNTER

READ 7220
STATUS REG.

Figure 22. WRFIFO

6-139

AP-150

1515-II 81380/8085 MACRO ASSEMBLER, 113. 13

******************************"''''*****************-*****************

aA8A C5
0ASB 05
BA8C eE2S
BA8E OBFE
SA90 12
0A9113
0A92 eo
0fl93 C28EeA
0A96 01
BA97 C1
BA98 OBFF
0A9A C9

8213 ;
821 ;
822 ; FUNCTION: RDFIFO
823; INPUTS: DoE REGS STARTING ADDRESS IN RAM
824 ;
BPK72 STATUS REG
825 ;
READ 40 BYTES OF DATA FROM BPK72 FIFO DATA BUFFER
826 ; OUTPUTS: TRANSFER FIFO DATA BUFFER TO RAM
827 ;
A REG= BPK72 STATUS REG
828 ; CAllS:
NONE
829 ; DESTROI'S: A, FIFS
830.;
831 .; DESCRIPTION: READ 7220 FIFO DATA BUFFER
832 ;
THE D-E REGS CONTAIN THE ADDRESS TO THE FIRST OF 40 CONTIGUOUS
833 ;
BYTES IN RAN THAT WILL BE LOADED flITH THE CONTENTS OF THE BPK72
834 ;
FIFO DATA BUFFER. RDFIFO WILL TRANSFER THE DATA FRot1 THE FIFO DATA
835;
BUFFER TO RAM. RDFIFO RETURNS THE \/AWE OF THE BPI<.72 STATUS REG
836 ;
TO THE CALLING ROUTINE lilA THE 8085'5 A REG. ONLY A STATUS OF 40H
837 ;
OR 42H INDICATES A SUCCESSFUL EXECUTION OF RDFIFO.
838. ;
839
PUBLIC R[fIFO ; .DECLARE PUBLIC FUNCTION
; SAvE B-C REGS
8413 RDFIFO: PUSH
B
841
PUSH
D
; SAVE D-E REGS
842
~rv I
c, 28H ; LOAD C REG= 28H,· INITIALIZE LOOP COUNTER
843 OUTFIF: IN
PRTA00 ; LOAD A. REG WITH. ONE BYTE FROM FIFO DATA BUFFER
844
STAX
D
; LOAD A REG IN D-E REG ADDRESS
845
INX
D
.; INCPEt1ENT D-E REGS TO NEXT ADDRESS
846
[)CR
i"
.; DECR~lENT LOOP COUNTER
847
JNZ
OUTFIF ; IF LOOP COUNTER NOT ZERO, JMP OUTFIF
848
POP
; RESTORE D-E REGS
D
POP
; RESTORE B-C REGS
B
849
850
IN
PRTAe1 i READ STATUS REG .
851
RET
; RETURN TO CALL
852 ;
853 ;
854 $EJECT

INITIALIZE
LOOP COUNTER =
40 DECIMAL; 28H

READ FIFO

1 BYTE XFER

DECREMENT
L.qoP COUNTER

READ 7220
STATUS REG.

Figure 23. RDFIFO

6-141

AP,~150

ISIS-II 80801B1l85 !'IACRO AS5EI1BLER, Vl 0
LOC OBJ

LINE
855

BA9B C5
BA9C E5
BA9D 8641
IlA9F IilEFD
1lAA1 21FFFF
0AA4 CD7ellA
IilAA? Al
0AA8 AS
0AA9 C2CE0A
BAAC 05
0AAD 3E16
IilAAF D3FF
0ABl DBFF
0AB307
0AB4 DAC1BA
IlAB7 2B
0AB8 AF
eAB9 B4
eABA B5
IilABB C2B10A
BABE GCE0A
0ACl DBFF
eRC3 AS
eAC4 CACEIlA
0AC7 2B
IilAC8 AF
0Ae9 B4
BAeA B5
BACB C2Cl0A
0RCE E1
BACF Cl
8AD0DBFF
8AD2 C9

******* ___*** _ _*_ _ __

856 ;
857 ; FUNCTION: WRBLRS
858; INPUTS: D-EREGS, STARTI~ ADDRESS OF DATA IN RAM
859 i
BPK72 STATUS REG
860 ,; OUTPUTS: WRITE BUBBLE ~RY BOOT LOOP REGISTERS COI'II'IAND
861 i
A REG= BPK72 STATUS REG
862 i CALLS:
WRFIFO
863 ; D~IROYS: A, FlFS
864 i
865; DESCRIPTION: WRITE 7242 BOOT, LOOP REGISTERS
866 i
THE D-E REGS PROYIDE THE ADDRESS TO THE FIRST OF 48 CONTIGUOUS
867 ;
MEMORY LOCATIONS IN RAM THAT CONTAIN DATA TO BE LOADED INTO
868 ;
THE 7242, FORI'IAmR SENSE AHPLIFIER~BooT uiOP REGISTERS.
869 ;
WRBLR5 WILL TRANSFER THE DATA FROM RAM TO THE BOOT LOOP
870 ;
REGISTERS. WRBLRS RETURNS THE VALUE OF THE BPK72 STATUS REG,
871 ;
TO THE CALLING ROUTINE VIA THE 80SS'S A REG. ONLY A STATUS OF
972 ;
40H INDICATES A SUCCESSFUL EXECUTION OF WRBLRS.
873 ;
874
PUBLIC WRBLRS ; DECLARE PUBLIC FUNCTION
i SAVE B-C REGS
875 HRBLR5: PUSH
B
; SAVE H-L REGS
876
PUSH
H
B,41H ; LOAD B REG= 41H, OP-COHPLETE. FIFO FULL
877
MYI
MVI
C,0FDH .; MASK, MASK OUT PARITY BIT
878
H,0FFFFH; INITIALIZE TIME OUT LOOP COUNTER
879
LXI
WRFIFO ; CALL WRITE FIFO DATA BUFFER
880
CALL
C
;, RESET BIT i., PARITY BIT
881
ANA
B:
882
XRA
; TESTSTATUS= 41H OR 43H, OP-COMPLETE. FIFO FULL
RETWBL ;' IF NOT ZERO, ERROR, JMP RETWBL
883
JNZ
; B REG= 4eH, OP-C.oMPLETE
884
DCR
B
A,16H i LOAD A REG: WRITE BOOT LOOP REG COMI'IAND
885
MYI
8B6
OUT
PRTA01 ;, WRITE, WRITE BOOT LOOP REG COMI'IftID
887 B5YWBL: IN
PRTA01 i READ STATUS REG
888
RLC
; TEST BUSY BIT= 1
889
POU.IBL ; IF BUSY= 1, POLL STATUS REG FOR 4eH
JC
890
DCX
H
; DECREl'lENI TIME OUT LOOP COUNTER
891
XRA
A
; CLEAR A REG
892
ORA
H
; ,TE5T H REG= 0aH
893
ORA
L
; TEST L REG= eaH
894
.TNZ
BSYWBL ; IF NOT ZERO, CONTINUE POLLING WRBLR COItIAND
Jf1P
895
RETWBL i TIME OUT ERROR, RETURN
896 POLWBL: IN
PRTAB1 ; READ STATUS REG
; TEST STATUS REG= 40H, OP-coI'!PLETE
89?
XRA
B
898
JZ
RETWBL i IF ZERO, OP-COHPLEiE, Jt1P RETWBL
899
DCX
H
i DECRE~lENT TIME OUT LOOP COUNTER
; CLEAR A REG
900
X~.A
A
; TEST H REG= BaH
901
ORA
H
i' TEST L REG= 00H
982
ORA
L
983
JNZ
POLWBL ; IF NOT ZERO, CONTINUE POLLING WRBLR COItIANi)
H
,i RESTORE H-L REGS
9134 RETWBL: POP
,; RESTORE 8-C REGS
985
POP
B
9%
IN
PRTA01 ,i READ STATLIS REG
907
RET
; RETURN TO CALL
988 $EJECT
6-142

AP-150

INITIALIZE
TIMEOUT
LOOP COUNTER

READ 7220 .
STATUS REG.

DECREMENT
LOOP COUNTER

YES

COMMENT: MIN TIME OUT

.READ·722o
STATUS REG.

I5IS-I r 8980/8085 MACRO ASSEI'IBLER, 1'1 0 .
LOC 08J

;*****----**-****-*************** .

909
910 ;
911;
912;
913 )
914 ;
915;
.916 ;
917 ;
918 ;
919 ;
920;
921 ;
922 ;
923 ;
924 ;
925 ;
926 ;
927 ;

0ADJ C5
0AD4 E5
0AD506C1
0AD7 21FFFF
0ADA JEi5
0ADC D3FF
BADE DBFF
0AE007
0AE1 DAEE0A
BAE4 28
0AE5 AF
0AE6 B4
0AE? B-S
0AES C2DE0A
0AES CJ010B
0AEE DBFF
BAF0 A8
BAn CAFE0A
0AF4 2B
0AFS AF
0AF6 B4
0AF7 B5
0AFS CA910B
0AFB C3EE0A .
0AFE CD8A0A

0801 El
0B02 C1

0803'DBFF . '
0B05 C9

FUNCTION: RDBLRS
INPUTS: D-E REGS, STARTING ADDRESS IN RAM
BPK72 STATUS· REG
READ DATA FROI1 7242 BOOT LOOP REGISTERS '
OUTPUTS: TRANSFER BOOT LOCf REGISTER DATA TO RAM
A REG= BPK72 STATUS REG
CALLS:
RDFIFO
DESTROYS: A, FIFS
DESCRIPTION: REAl) 7242 BOOT Loop REGISTERS
THE D-E REGS CONTAIN THE ADDRESS TO ~ FJRSrOF 49 COOTIGlIOUS
MEMORY LOCATIONS IN RAt! TO BE LOADED WITH. THE CONTENTS OF tHE
7242, FORtlATTER SENSE AMPLIFIER,. BOOT LOOP REGIsTERs. RDBLRS
WILL COPY THE CONTENTS OF THE BOOT, LOOP REGISTERS TO RfII'l
RDBLRS RETURNS THE VALUE OF' THE BPK72 STATUS· ~EG TO THE
CALLING ROUTINEYIA THE 8085'S A REG. ONL'r'; A STATUS OF 400
INDICATES, A SUccESSFUL EXECUTION OF RDBLRS.

PUBLIC ~RS ; DECLARE PUBLIC FuNCTION ;
930 RDBLRS: PUSH
B,
; SAVE' B-C REGS
,. .. .
931
PUSH
~
. j SAYE H-L REGS
932
HY(
B; OCiH; LOAD B REG:, CiH, ;Cf-coKPi.ETE; FIFO·FULL )22 BYTES (BUSY BIT=1)
9J3
LXI , H,0FFFFHi INTIALIZE TIME buT LOOP COUNTER .;
934
MY!.. i A, 1~. i. LOAD.A REG: R~ BOOTLOOP REGS cat1AND
935
OUT
PRTA01 i WRITE THE READ BOOT LOOP REGS COI'IMANO
936 BSYRBL: )N ,'.. PRTftB1,;; READ. STATUS REG·'
,
937
RLC
i TEST BUSY BIT= 1
.,
.
938
JC
POLRBL· i· IF B!JSY=. L POlL STATUS REG FOR C1~
939
Dex
Ii
; DECREMENT TIME OUT LOOP COUNTER· .
940
XRA
A·,·
; CLEAR A REG
.
.'
941
ORA'· 'H
. ; TEST H REG: 00H •
942
ORA
L ' . i TEST L REG= BaH
943
JNZ
BSI'RBL; IF NOT ZERO, CONTINUE ,POLLING REAl) BOOT LOOP REG COIf1AND
944
JMP
RETRBL;' TIME (JfJTERROR, RETURN·
945 POLRBL: IN
PRTA01 i READ sniTUS REG
946
XRA
B' . j TEST STATUS= C1H, OP-COI'PLETE. FIFO FUlL
947
JZ.. ··CALLRD·; IF ZERO, OP-COI'PLETE, JHP CALLRD
948 .
OCX
H· .
; DECREMENT TIME OUT LOOP COUNTER
949
XRA
A
; CLEAR A REG
950
ORA
H
; TEST H REG: 00H
951
ORA
L
.; TEST L REG: 001l'
952
JZ
RETRBL; IF ZERO, ERROR, JI'P RETRsL
953
1MP
POLRBL; CONTINUE POLLING REAl) BOOT LOOP REG COI1I1AND
954 CALLRD: CALL
RDF IFO ; "cALL READ FIFO
955 RETRBL: POP
H
; RESTORE H-L REGS
956
POP
B
; RESTORE B-C REGS
957 · ' I N ·
PRTA01 ; READ STATUS REG
958
R E T ' ; RETURN TO' CALL ' "
959 $EJECT

·6·144

Ap·150

ENTER

INITIALIZE
TIME OUT
LOOP COUNTER

ISSUE READ
BOOT LOOP REGS
COMMAND

READ 7220
STATUS REG

READ 7220
STATUS REG.

DECREMENT
LOOP COUNTER

YES
YES

READ 7220
STATUS REG.

COMMENT: MIN TIME OUT LOOP COUNTER ~ lMS

Figure 25. RDBLRS

6·145

AP-150

1515-II 8089/8085 MACRO A5SEI'1BLER, V3. 0

LOC OB.I

LINE

0096 05
0097 C5

ooes 0640
000A llFFFF
000D
0B0F
llBll
0013
0014
0017
0B18
13B19

3E1E
D3FF

DBFF
07
DA2100

AF
B2
!lBiA B3
llB18 C211llB
BBiE C32EIilB
0021 DBFF
llB23 A8
13B24 CA2EllB
0027 18
llB28 AF
0029 B2
BB2A B3
llB2B C2210B
BB2E.C1
0B2F D1
llB39 DBFF
0032 C9

PAGE

SOURCE· STATBiENT

960 ;
961;
962 ;
963;
964 ;
965 i
966;
967 ;

968
969
970
971
972

BPK72

***********************_**_*******************************
FUNCTI ON: MB~IPRG
INPUTS: BPK72 STATUS REG
OUTPUTS: ISSUE MBN PURGE COt1l'lAND
A REG= BPK72 STATUS REG
CALLS:
NONE
DESTROYS: A, FIFS

i DESCRIPTION: NBM PURGE COMMAND
i A N NB~I PURGE COMMAND IS ISSUED TO THE BPK72. AFTER ISSUING THE
;
CO~lNAND, THE BPK72 STATUS REG IS POLLED UNTIL AN OP-COt1PLETE
;
40H, HAS BEEN READ OR THE.· TI ME OUT LOOP COUNTER DECREMENTS
973 "
TO ZERO, ~lBI'1PRG RETURNS THE VALUE OF. THE BPK72 STATUS REG TO
974 ;
THE CALLING ROUTINE VIA THE80BS'S A REG, ONLY A STATUs OF 40H
975 ;
INDICATES A SUCCESSFUL EXECUTION OF NBNPRG,
976 ;
977 .
PUBLIC MBMPRG i' DECLARE PUBLIC FUNCTION
D
i SAVE D~E REGS
978 MBNPRG: PUSH
979
. PUSH
B· ,
; SAVE B-C REGS
. 989
MVI
B, 41lH i LOAD B REG= 48H; OP-COMPLETE
D, eFFFFHi INITIALIZE TIME OUT LOop COUNTER
981
LXI
A, iEH i LOAD A. REG= .MBM PURGE COI1I1AND
982
Mill
PRTA81 i WRITE MBM PURGE COMMAND
983
WT
PRTA01 ',; READ STATUS REG
984 BSYNBM: IN
i TEST BUSY, BIT: 1
985
RLC
POLMBM ; IF BUSY= 1, POLL STATUS REG FOR 40H
986
.IC
987
[lCX
D
; DECREl'1ENT TIMEOUT LOOP COUNTER
A
,; CLEAR A REG
988
~RA
989
ORA
D
; TEST D REG=8!lH
E
i TEST E REG=' 00H
990
ORA
BSYNBM ,; IF NOT ZERO, CONTINUE POLLING THE MBMPRG COMMAND
991
JNZ
992
.IMP
RETNBM ; TIME OUT ERROR, RETURN
993 POLMSM: IN
PRTA01 ; READ STATUS REG
B
_; TEST 5TATUS= 4!lH, OP-COMPLETE
994
XRA
RETMBN ; IF OP-COMPLETE,JI'IP RmlBM
995
.IZ
996
OCX
D
; DECREl'lENT TIME out LOOP COUNTER
997
XRA
A
i CLEAR A REG
998
ORA
D '
; TEST D REG= eeH
999
ORA
E
; TEST E REG= 0aH
100e .
.INZ
POLNBt1 ; IF NOT ZERO, CONTINUE· POLLING' MBI'! PURGE COMI'IAND
1001 RETMBM: POP
B
; RESTORE B-C REGS
D
i RESTORE D-E REGS
18132
POP
1003
IN
PRTA01 ,; READ STATUS REG
; RETURN TO CALL
1004
' RET
1005 $E.IECT

AP-150

INITIALIZE
TIMEOUT
LOOP COUNTER
READ 7220
STATUS REG

ISSUE
MBM PURGE
COMMAND

READ 7220 .
STATUS. REG

DECREMENT
TIMEOUT
LOOP COUNTER

READ 7220
STATUS REG

COMMENT: MINIMUM TIME OUT LOOP COUNTER

1515-II 8080/0085 HACRO ASSEI1BLER, 113. 0
LOC OBJ

LINE
1006
1007

PUBLIC SYMBOLS
ABORT A 0SDE
RDBUBL A 0916

BOOTUP A 999C
RDFIFO A 0ABA

mORS A 0813
WRBLRS A oo9B

INBUBL A 0961
WRBUBL A 0908

MBMPRG A 0806
WRFIFO A 0070

A 99F1 . BOOTUP A 099C
BUSI'BLA 0A05
A e9C8
A 0840
CALLRD A 0AFE
A 08A1
INBUBL A 0961
A 0B136
MULT A 0852
A 0900
POlLFR A 082E
A ooCi
PRTAOO A 00FE
A 08A4
RETA A 13906
A B95C
RETRDB A BA6A
A 0A9B
WRBUsL A 090B

BSYMB~I A 0811
BU51'FR A 081E
CONT A 09E8
INFIFO A 0A7D
11ULT1 A 0862
POLL! N A 09BA
PRTA01 A OOFF
RETBT A 0A2l
RETWBL A BACE
WRFIFO A 0A70

RDBLR5 A IlADl

RDBOOT A 0A2C

EXTERNAL 51'NBOLS

USER 5'r'I1BOLS
ABORT A 08DE
ALLFFS
BTLPRD. A 0AS2
BUSYA
BUSI'RD A 08AD
BU5YWR
FIFOR5 A 0813
FINSHR
LOOPRD A 994F
LOOPWR
POLLA A 08F9
POLLBL
POU1BN A 0821
POLRBL
RDBUBL A0936
RDFIFO
RETMBM A BB2E .. RETRBL
RFIFO A 08De • WFIFO
ASSEt1BL'r' COMPLETE,

A 098B
A 08E9
A 0873
A 0800
A 13924
A BA1S
A OOEE
A 0ABA
A 0801
A 0896

BLCODE
BUSI'B
B'r'TCNT
FINSHW
MBMPRG
POLlBR
POLWBl
READ.
RETRD
WPBLRS

NO ERRORS

6-148

BSYRBL
BU51'IN
DONE
INTPAR
l1UlTO
POLLRD
RDBLRS
. RETFR

A 0ADE

A 097A
A 0867
A 0800
A 0856

A OOBA

A ooDl
A 08lS
REM A BASS
WRITE A 086A

BSI'WBL
BU51'RB
FIFORD
LOAD
OUTFIF
POlLWR
RDBOOT
RETIN
RETWR

A 13AB1
A 13A42
A 13A62
A 0800
A ooSE
A 0000
A eA2C
A 13997
A 0931

AP-150

APPENDIX B
SERVICE INFORMATION

6-149

AP-150

SERVICE INFORMATION
Typically, a Bubble Memory System will never require any special service throughout its useful life. The sequence of
program flow presented in Appendix B is not required for normal read/write operation. However, power supply
failure, socket contact problems, or component failures may inadvertently produce a BPK 72 system failure.
Note: Power supply failure is defined as any violation of the power supply specifications listed in the section titled,
"Power Supply Requirements."
A figure titled, "BPK 72 Failure Recovery" is included in Appendix C to illustrate the sequence of events necessary
to remedy a Bubble Memory System failure. The flowchart is intended as a guide for handling a Bubble Memory
System failure. A system failure is defined as continued attempts that fail to read and write data correctly. Upon
detection ofaBPK 72 system failure, the first course of action is to verify the existence of the seeds within the 7110
Bubble Memory module. Four replicating Bubble Memory generators reside in the 7110. Each generator requires
one seed from which all other bubbles are created. Under extreme circumstances such as power supply failure, one or
all of the seeds can be destroyed making it impossible to write data into the 711 O's storage loops. The" BPK 72 Failure
Recovery" flowchart requests a call to the "seed verification procedure." The "seed verification procedure" should'
be followed closely to determine if any of the seeds are missing.
In the unlikely event that some or all of the seeds are lost, the "BPK 72 Failure Recovery" figure instructs the reader
to perform the' 'procedure to reseed a 7110 Bubble Memory." The seed replacement procedure will create a seed in
each of the four generators. After completing the seed replacement procedure, the "seed verification procedure"
should be performed again to confirm that all four seeds are present in the 7110.
The next step in diagnosing a BPK 72 system failure is to verify the accuracy of the boot loop code within the 7110.
The boot loop is a map containing information about the active and inactive storage loops. The 7110 is designed with a
15% storage loop redundancy to improve the product yield during manufacture. A diagnostic subroutine named
RDBOOTcan be called to read the boot loop from the 7110. His the responsibility of the calling routine to verify that
the boot loop code read from the 7110 matches byte for byte with the code found on the label attached to the case of
the Bubble Memory module.
The following is an example of how to use the read Bubble Memory boot loop subroutine, RDBOOT:
8085 Addressable Memory

8085 Microprocessor

B REG =
DREG =
HREG=
HREG=
A REG =

r----,J~~3000H = First Byte*
C REG = XXH
XXH
E REG = OOH - - - - 1
3027H = Last Byte
30H·
XXH
LREG = XXH
*Boot Loop code read
XXH
the 7110 Bubble Memory.
Will return the value of
the status register
(acceptable status = 40H)

Call RDBOOT.
Additional detail regarding the use of the read Bubble Memory boot loop subroutine, RDBOOT, may be found in the
.
software listing presented in Appendix A.
If the boot loop is incorrect, a subroutine called BOOTUP is provided for writing the boot loop into the 7110.

6-150

AP-150

The following is an example of how to use BOOTUP to write the boot loop code into the 7110:
8085 Microprocessor

A REG = Will return the value of
the status register
(acceptable status = 40H,
42H)

8085 Addressable Memory
~

1000H = om BLR LSB
1001H = 10H BLR MSB
1002H = OOH Enable REG
1003H = OOH Add LSB
1004H = OOH Add MSB
3000H = First Byte*
3027H = Last Byte

. *Boot loop code found
on the label attached to
case of the 7110.

Call BOOTUP.

Additional detail regarding the use of the write Bubble Memory boot loop subroutine, BOOTUP, may also be found in
the software listing presented in Appendix A.
After the seeds and boot loop have been examined and replaced as necessary, the remaining step is to call the
initialization subroutine, INBUBL. See the section titled, "Initalizing the Bubble"for a description of how to call the
initialization subroutine. If the initialization subroutine returns a status of 40H, the BPK 72 is ready to be put back
into service.
Contact the local Intel field sales office in the unlikely event that the BPK 72 system failure guidelines do not
eliminate the problem.

6-151

AP-150

YES

Figure 28. BPK 72 Failure Recovery

6·152

AP-150

WRITE THE BOOT LOOP REGISTERS WITH THE 40
BYTE BOOT LOOP CODE FOUND ON THE LABEL AT·
TACHED TO THE CASE OF THE 7110 BUBBLE MEMORY.

WRITE ONE PAGE USING A DATA PATTERN OF "FF'S"
(68 BYTES). THE FOLLOWING VALUES SHOULD BE
USED TO LOAD THE PARAMETRIC REGISTERS: 01 H
(BLR LSB), 10H (BLR MSB), OOH (ENABLE), OOH (ADD
LSB), AND OOH (ADD MSB).

READ ONE PAGE WITH THE SAME VALUES LISTED
ABOVE TO LOAD THE PARAMETRIC REGISTERS.

IF ALL THE SEEDS ARE PRESENT, THE DATA READ
BACK WILL BE ALL "FPS."

SEE PREVIOUS PAGE

If one or more seeds are missing, the data read back will be a pattern with one or more bits missing from each
hex character. One example of several possible patterns is.shown below. Each pattern will typically contain a
dominant pair of hex characters (i.e., "88's" or "AA's "). ~n any case, if seeds are missing no "FF's" will be read
using the subroutine, RDBUBL.

88
88

Do not attempt to us,? the seed verification procedure without first performing the program sequence described
in Figure 28, "BPK 72 Failure Recovery."

Figure 29. Seed Verification Procedure

6·153

PROCEDURE TO RESEED A 7110 BUBBLE MEMORY
1. Remove power from circuit.
2. Remove the 7230 current pulse generator from its socket, and install the 7230 in, the socket provided on the seed
module. Be careful to'note the orientation of Pin 1.
3. Install the seed

modul~

(with the' 7230,installed) in the 7230 socket.

: 4. Apply power to the circuit.
5. Call ABORT.
6. Call MBMPRG.
: 7. Cali WRBUBL (1 page transfer, any location, data pattern is not important). Parametric register values;
, (BLR LSB), IOH (BLR MSB), OOH (ENABLE), OOH (add LSB), and OOH (add MSB).
: 8. Remove powe~ from circuit .
., 9. Remove the seed module from 'the 7230 socket.
,
10. Remove the 7230 from the seed module and reinstall the 7230 in its socket on the IMB-72 board.,
11. Apply power to the circuit.
12. Reseed procedure is now complete.

ORDER NUMBER: 230707·002

6-155

inter

AP-157

INTRODUCTION.,.
The 7220-1 is a single-chip LSI Bubble Memory Controller (BMC) that implements a bubble memory storage subsystem
(with up to eight bubble storage units (BSUs) per BMC). Each bubble storage unit consists of five support circuits in addition
to the bubble memory chip and provides one megabit (128 kbytes) of non-volatile read/write memory. This application note
examines the programmatic interface to the 7220-1 BMC and how communications between a host processor and the bubble
subsystem (i.e., 7220-1) govern all bubble system operations.
The BMC provid,es all the control and timing signals for the bubble and support circuits. All data synchronization and error
checking is automatically performed by the bubble subsystem to ensure reliable data storage. The BMC easily interfaces to
microprocessor systems and communicates via a set of high-level commands. This application note explains the operations
and functions performed by_these instructions and provides the basic programmatic interface descriptions and program
guidelines to allow you to design and implement a program module or "driver" to control all bubble system operations. In
'addition, several. possible software interface levels are defined, While the design guidelines presented are not targeted for
integration with any particular operating system, they do, however, provide conceptual information on design requirements
and serve as a foundation on which to develop a modular and flexible software driver aligned with your specific application
'
requirements,

Product Line Overview
Intel offers a complete line of bubble memory components, development kits and assembled boards.
The BPK 72 (Bubble Memory Prototype Kit) serves primarily as a means to evaluate the potential of bubble storage, The
BPK 72 comes complete with all the hardware and documentation necessary to prototype a one-megabit bubble memory
system, After the kit is asselTlbled, the desig~er is left with the simple task of interfacing to a host processor,
The BPK 70 one-megabit bubble. storage subsystem is a fully interchangablecomponent bubble memory system. Each kit
contains all the componen~s in a Bubble Storage Unit (BSU), A single 7220-1 Bubble Memory Controller (purchased
separately) can operate up to eight BPK 70,subsystems at one time. The BPK 70 is available for the production of custom
systems where high volume is required.
The iSBX" 251 Magnetic Bubble MULTIMODULE'M board is a one-megabit bubble memory mounted on a standard dual,
,width Intel MULTIMODULE memory expansion card. Completely assembled and tested, the iSBX-25I board is fully plug
compatible with all Intel iSBC Single Board Computers that have iSBX connectors.
'The iSBC® 254 Bubble Memory Board is a completely assembled Intel MULTIBUS® memory board. The board can be
configured with one bubble memory (128 kbytes) , two bubble memories (256 kbytes), or four bubble memories (512
kbytes),
The 7220-1 BMC acts as the interface to the host processor in each ofthe aforementioned products, thus simplifying system
programming. The basic programming techniques discussed in this application note will provide the system programmer
with a complete understanding of programming requirements and shorten the softwaredevelopmenf time.
'

SOFTWARE INTERFACE
Basic Driver Operation

As will become evide'nt, a basic compromise or "tradeoff' exists between the design of your application software and the
capabilities of the bubble memory controller. While you will be responsible for the development of a driver to integrate the
bubble into your system, the level of driver interaction and degree of flexibility will vary according to the needs of your
application. If an application program is small and simple, a basic bubble driver simply may be called from the main
program. At the next level of driver sophistication, the bubble system is viewed by the application program as a logical
device. At this level, the key to driver design is the mapping of the "logical bubble interface" (as viewed by the application
program) into the "physical bubble interface" (as implemented by the bubble drivers). This logical-to-physical mapping
serves to isolate application programs and system software from the idiosyncracies of the bubble memory controller. At the

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hig/lestlevel of driver sophistication 1 the application program trllats the bubble system as a collection of named data areas or
files similar to the way in which data is stored and retrieved in disk operating systems. At the file system level, an application
program can ignore the mechanics of bubble storage and access and m~rely present a "file name" to the driver to open, read
or write, and then close the desired "bubble file."
At the subsystem level (Le., "physical bubble interface"), the bubble driver is responsible for all system interaction with the
bubble and is intrinsic to the efficient and reliable operation of the bubble system. The driver accepts bubble memory
commands and command execution parameters from the application program, controls and monitors command execution,
and returns operational status information to the application program at .command completion. to' perform all of these
operations, the'bubble driver must suppoit the bit/byte level ofth~ bubble memory controller's command and status registers
and'the "parametric" registers that define the operating mode, system configuration, and extent of the transfer. Depending
on the interface level of the application software, the driver itself may be made up of a set of subroutines'that are called
individually by the host to, perfo~ specific bubble system operations.

SOFTWARE-SELECTIVE CONFIGURATIONS
Before you can begin to design a software driver, you must consider all of the selective configurations available within the
bubble system and which of these configilrations you want to support. As will be explained, the type of data transfer (Le.,
direct memory access, interrupt driven, or poiled), the data transfer rate, and the selective implementation of the bubble
system's error correction feature all are software controlled. The complexity of the driver design depends on the system
flexibility desired. For example, a driver may be designed to support only one transfer mode and may not make use of error
correction. Conversely, a more generali~ed driver can be designed to support various transfer modes, data rates, and levels
of error correction. The ensuing paragraphs define tIie driver responsibilities associated, with the available ,software
configurations and will aid you in designing a driver that satisfies your specific application.

Data Organization
, Probably the most important aspect of the bubble memory system interface is theorgani~ation of data. From a software
viewpoint, data logically is organi~ed into blocks of bytes called "pages. " During data transfer operations, one or more of
these pages are transferred between the bubble( s) and the host microprocessor. A page is the smallest increment of data that
can be transferred; single bytes cannot be transferred. Conceptually, the data organization within a bubble memory is
analogous to a disk system. Just as disk sectorsius are fixed when a disk is formatted, bubble page sizes are established,
under software control, when the bubble system is initiali~ed. For a single bubble system, the page si~e is fixed at either 64
bytes when error correction is implemented ,or 68 bytes without error correction; and the total number of pages available is
2048. In systems with multiple bubbles, page si~e can vary from 64:bytes (68 bytes without error correction) t0512 bytes
(544 bytes without error correction) depending on the number of bubble devices in the system. Page si~e is directly
proportional to the system data rate and also determines the total number of available pages (address field si~e). As an
example, consider a system consisting of two bubbles (using error correction). With two bubble~, there are two possible
ways to configure the system; paia1leling the two bubbles for a page size of 128 bytes and a total number of 2048 pages or
treating the bubbles serially for a pagesi~e of 64 bytes and a total number of 4096 pages'. The average data rate for the
128-byte page is 17.0 kbytes per second, and the average data rate for the 64-byte page is 18.5 kbytes per second.
The selection of the appropriate page si~e depends primarily on the data rate supported by the system. For file, system
implementation, an' additional consideration ,in page size selection is bubble transfer efficiency versus bubble storage
efficiency. 'Essentially,' the following' system factors must be weighed:
• Data, Rate. The higher the data rate', th~ faster'the mi~roproces~or must respond to the demands qf the bubble memory
'controller. 'Depending on the data mmsfer mode'seiected, some data rates may exceed the data transfer rate of the host
microprocessor.,
"
• Bubble Transfer Efficiency. A file consisting of a fe)'llarge pages can be transferred more effieien~ly (faster) than a file
consisting of a number of small pages.
• Bubble Storage Efficiency. For a typical file system, space must be allocated within each page to link the pages of each
file together (individual pages of a file may not necessarily be contiguous). Too large or too small a ~age si~e can waste

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bubble storage space. If most files are comprised of many small pages (e.g., 64 bytes),'a large percentage of tiubble
storage would tie required for establishing the fore/back pointer linkage~ Conversely; if most files are smallerthim a single
page, a large amount of space would remain unused at the end of each page.
'

Buffering
Buffer operation is an extremely important factor in the reliabletransfer of data between the bubble and system memory and
is a major consideration in software driver design. A buffer, ideally speaking, is a memory storage area that contains ,he
same amount of data storage as the data block to be transferred. 'The bubble system~s bubble memory coiltroller includes a
first-in, first-out (FIFO) 40 byte data buffer that reconciles timing differences between the parallel data transfer to orfrom
the host microprocessor and the serial data transfer to or from the bubble memory. Accordingly, when an application
program requests data from a bubble, the software driver is responsible for keeping up with the FIFO for the duration of the
data transfer in order to prevent the FIFO from overflowing or underflowing. The specific software driver requirements are
dependent on the method of data transfer selected.

Data Transfer Interface Modes
Three distinct software interrace techniques can be used to interrace host system memory with the bubble system for page
data transfer: DMA: interrupt driven, and polled.
'
. In the DMAtransfer mode, the BMC operates in conjunction with a DMA controller (e.g., Intel's 8257 or 8237) and ~ses the
DRQ (data request) and DACKI (data acknowledge) signal lines for establishing the liandshake protocol. Assisted by the
DMA controller, the BMCtiansfers data to or from the host system memory. Once the transfer begins, further program
intervention is not required until the entire transfer has been completed.
In the interrupt-driven data transfer mode, the DRQ line is connected to an interrupt controller (e.g., Intel's 8259A). During
non-DMA data transfers the DRQ line indicates when the BMC's FIFO is half-full (bubble read operations) or half-empty
(bubble write operations). This method of interrupting results in a data block transfer arrangement in which the software is
responsible for perrorming the appropriate transfer of data (typically 22 bytes) to or from the FIFO when the interrupt occurs.
Using this technique, the software driver only processes the FIFO buffer as needed, and program waits during II,O transfers
(polled I/O) are eliminated.
;

..'

The polled IIO mode is the most simple to implement since no special or external hardware isrequired to perrorm data
transfers; In the polled IIO rilOde, the software must determine when.to transfer data to or froin the FIFO by continually
polling a status bit in the BMC's Status Register. This status bit indicates the presence or absence of data in the FIFO on a
byte-by-byte basis. The polledIlO mode places significant demand on the, host system's processing time since the software
continuously must monitor the Status Register to 'ensure that FIFO overflow or underflow does not occur.

, .
ECC Highlights

The last software, controlled option to be considered in the design of your bubble driver is if the built-in error correction
circuitry (ECC) within the 7242 Formatter/Sense Amplifier is to be implemented and, if so, whatIevel of error correction is
best suited to your application.
.
Although tlIe ,inherent data integrity of your bubble me~ory is extr~rnely higJ.t. the incorporation of err~[ co~ection
improves the overall integrity of your system by several orders of rrjagnitude. While boosting the data integrity, the
implementation of error correction adds increased overhead to both driver design and host interaction. Since the associated
error handling routines can range from simple to complex, you must 9arefullyi weigh the software requirements before
considering the level of error correction to be supported. In balancing driver and liost responsibilities; you must understand
the following factors pertaining to ECC:
• . The type and nature of errors associated with bubble memories.
• The way in which ECC operates.
• The various levels of error correction available.
All of these factors, are explained in detail in a later section.

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COMMUNICATING WITH THE BMC
All cQmmunications between the host and the bubble memory actually are peformed through the 7220-1 BMC. The BMC
has two input/output (110) ports; an 8-bit bidirectional data port and an 8-bit command!status port (Figure I). The port
addressed is dettermined by the least-significant bit of the port address byte. Conceptually, the BMC can be thought of as a:
disk system controller in that data in the bubble memory is organized into blocks caUed"pages" that are similar to disk
sectors. Information such as starting page location, direction of transfer, and the number of pages to be transferred is passed
to the BMCbefore the desired read or write operation is initiated.

REGISTER REGISTER
ADDRESS NAME
1 0 1 0 UTILITY REGISTER
1 0 1 1 BLOCK·LENGTH·REGISTER LSB
1 1 0 0 BLOCK·LENGTH REGISTER MSB
1 1 0 1 ENABLE REGISTER
1 1 1 0 ADDRESS·REGISTER LSB
ADDRESS·REGISTER MSB
FIFO DATA BUFFER

Figure 1.

BMC Block Diagram

For simplicity, you can think of the BMC as a 40-byte FIFO (first-in first-out) buffer and a series of six user-accessible 8-bit
registers, The FIFO passes data bet\\ieen the outside world and the bubble system's 7242 Formatter/Sense Amplifier and
compensates for speed variations. The six registers are loaded prior to most operations and contain information regarding the
upcoming transfer and the operating mode of the BMC. Since these registers always are loaded before a command is sent
similar to passing parameters to a subroutine before it is inVOked, this set of registers is referred to as the "parametric
registers. " The transfer of data between the host and the BMC's FIFO and parametric registers takes place over the 8-bit data
port. The destination (FIFO or parametric register) of the data port transfer is, determined by the value in another register
called the RAe. As shown in Table I, bit 4 of the command! status port byte is used to distinguish between a BMC command
..
and either the addres~ of one of the par~metric registers or the FIFO.

Table 1. Command Port Function
Function

,0 3

Command
RAC

0
0

When bit 4 is a "one," the low-order four bits are decoded'as a BMC command, and when bit 4 is a "zero," the low-order
four bits are interpreted as a pointer to the parametric registers/FIFO. This 4-bit register pointer is referred to as the "Register
Address Counter" or simply the "RAC."
RAC values that may be written to the command/ status port and the registers selected are outlined in Table 2. The RAC points
to, or selects, one of the six registers or the FIFO. Once a RAC value is written to the command status port; the next data port
read or write operation transfers data between the host interface and the register addressed.

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Table? Register Address Counter Assignments·
Register Name

Block Length
Register (LSB)

Block Length
Register (MSB)

RfW

Enable, Register

Address Register
(LSB) ,

Address Register
(MSB)

NOTE(S):
'WithAO=}
", Write-only bit

Referring now to the table, notice that the register addresses are in hexadecimal order from "A" to "F" and that the FIFO
has an address of zero. This arrangement of addresses is due to the RAC's auto-incrementing feature. Once' a register is
selected, each subsequent data pori I/O read or 'write causes the RACto advance and to point to the next register in the
sequence. After the most significant byte of the Address Register is addressed, the RAC advances fromF to 0 to point to the
FIFO. Whe'n it reaches this point it no 100iger increments. The system now is ready to transfer data into or out of the FIFO
without further instructions from the host.
'
After the FIFO is selected, the RAe stops incrementing and continues to point to the FIFO until the RAC again is' accessed
through the command/status pori. The auto-incrementing feature minimizes the nu'mberof instructions required for a given
command sequence and ensures that all of the required parametric information is sent to the BMC.
As a user, you are not required to utilize the auto-incrementing feature; each parametric register can be selected and loaded in
any order, and specific registers maybe updated as required. When individual registers are not accessed in order, each
register must be specifically .addressed and loaded. Until you become more familiar with the bubble system, the
auto-incrementing feature is r e , c o m m e n d e d . ·
,
A point to remember is that once a command has been issued to the BMC, the parametric registers must notbe updated until
the operation is complete. The parametric registers essentially are working registers for the BMC during command
execution. When a bubble read or write operation is in progress, the Block Length Register, as ,explained later in this chapter,
contains the terminal page count and 'is decremented with each page transferred. Attempting to modify this register during
command execution would cause the final page count to be incorrect.

The Parametric Registers
Now that you have been introduced to the Register Address Counter and its operation, let's look at the individual parametric
registers addressed by the RAC in more detail. .

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Utility Register
The' Utility Register is a user-defined register that can be both written and read. This register is not incremented or
decremented by the BMC. Since the Utility Register is the first register of the RAe sequence, if the register is not used, the
least-significant byte of the Block Length Register initially can be addressed to eliminate the Utility Register from the
sequence. Note that the 4 Mbit bubble memory controller (7224) does not contain a utility register.

Block Length Register
The Block Length Register is made up of two 8-bit registers, a low-order byte register and a high-order byte register. The
contents of the block length register determine the system page size and also the number of pages to be transferred in
response to a single bubble data read or write command. The Block Length Register or "BLR" is a write-only register that is
divided into a terminal count field and a channel field as follows:
BLOCK LENGTH REGISTER MSB

BLOCK LENGTH REGISTER LSB

17 1615 14 13 12 11 I 0I I 7 161 514 131 211 I 01
~,

_____~¥~___~;

_________.......

NUMBER OF FSA
CHANNELS (NFC)

........____

",~

NUMBER OF PAGES TO BE TRANSFERRED

The terminal count field is eleven bits in length and is loaded with the total number of pages to be transferred in the ensuing
bubble read or write operation. With a field length of eleven bits, from I to 2048 pages can be transferred (all zeroes in the
field indicates a 2048-page transfer).
The page width (size) is defined by the 4-bit channel field. This field actually specifies the number of formatter/sense
amplifier channels available. Note thaI each 7242 formatter/sense amplifier has two channels to communicate with each
bubble memory; therefore the acceptable values in this field select one channel (one half of a bubble memory), two, four,
eight, or 16 channels. These field values correspond to page sizes of 32, 64, 128, 256, and 512 bytes (assuming error
correction), respectively, when the bubble memories are operated in paralleL (The one-channel mode usually is reserved for
diagnostic operations.) Table 3 shows the relationship among page size, channel field value, and formatter/sense amplifier
channel selection for parallel bubble operation.
As shown in the table, the channel. field bits are encoded and only one bit ever is set in the field.
For example, a channel field value of '~OOOJ." selects one bubble memory through channels 0 and 1.

Table 3. FSA Channel SelectlMBM Select
"Channel Field" (BLR MSB Blta 7, 6, 5, 4)

MBM Select

AP, MSB BII.
(6,5,4,3)

0000
o0 0 1
o0 1 0
00 1 1
01 00
01 0,1
01 1 0
01 1'1
1 0 0 0
1 00 1
1 01 0
1 0' 1 1
1 1,00
1 1 0 1
il 11 0
1111

0.1.2.3
4.5.6,7
8.9. A. B
C. D. E. F

NOTE(S):
'Normally reserved for diagnostic operations,

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Address Register
The Address. Register, like the Block Length Register, is made up of two 8,bit. registers; a low-order byte register and a
high-order byte register. The Address Register is divided into a starting address field and an MBM (Magnetic Bubble
Memory) select field show as follows:

ADDRESS REGISTER MSB

ADDRESS REGISTER LSB

17161.514.1 312.11 101

17 16.1514 131 211 101

¥_-.. . '-..-------.. .y,,--------./.

X '-....___

MBM SELECT

STARTING ADDRESS WITH~N EACH MBM

The Address Register's starting address field is eleven bits in length and is used to define on which page of a bubble's 2048
pages that the transfer is to start. The starting address field is incremented with each page transferred during multipage
transfers, automatically selecting the next sequential page.
.
The Address Register's MBM select field is used in conjunction with the Block Length Register's channel field to control the
serial selection of bubble memories or groups of bubble memories operated in paralIel. To better understand the function of
the MBM select field, consider a syst.em consisting of four bubble memories operated as two banks of two bubble memories
each.
. '.
Referring back to table 3, the channel field in the Block Length Register would beset to "0010" to select two.bubbles in
paralIel and a corresponding page size of 128 bytes .. To select between the two banks, the Address Register's MBM select
field would be set to "OOOO"to select the first bank (FSA channels 0 through 3). As page 2048 is transferred to or from the
first bank, the Address Register's starting address field rolIs over to "0000" and increments the MBM select field to "0001"
to select the second bank (FSA channels 4 through 7).
..
.

Enable Register
While the Address and Block Length Registersdefine the system configuration and 'data tr~nsfer, the Enable Register defines
the various modes of operation under which the data transfer is performed and defines the.conditions under which interrupts
can be generated. Several ofthe Enable Register bits are used individualIy while other bits are used in combination. Figure 3
shows the individual Enable Register bit definitions.

ENABLE REGISTER

INTERRUPT .ENABLE (NORMAL)
' - - - - - - I... INTERRUPT ENABLE (ERROR)
' - - - - -__ DMA ENABLE
' - - - - - - - - - l... MFBTR
' - - - - ' - - - - - - - - . WRITE BOOTLOOP ENABLE
' - - - - - - - - - ' - - - - - 1.. ENABLE RCD
'------------,-----I~ ENABLE ICD
'-----------~--. ENABLE PARITY INTERRUPT

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Interrupt Enable (Normal), when set (" I "), .enables the BMC to intenupt the host processor on the successful completion
of a command. Conversely, if this bit is not set, an intenupi is not generated on command completion and the host processor
~ust poll the BMC's Status Register to determine when command execution is complete.
Interrupt Emlble (Error) is used in conjunction with the Enable RCD and Enable ICD bits to select various error conditions
under which the BMC will terminate command execution and intenupt the host processor. The following table outlines the
bits combination and corresponding error conditions recognized.

Table 4. Error Correction Options
Enable
ICD
(bit 6)

Enable
RCD
(bit 5)

Interrupt
Enable
(Error)
(bit 1)

Interrupt Condition

No interrupt on error

Interrupt only on timing error

Interrupt on uncorrectable or timing error

Interrupt on uncorrectable, correctable or timing error

Illegal

*Interrupt on uncorrectable, correctable or timing error

NOTE(S):

'Normally not

u5ed~.

DMA Enable, when set, enables the BMC to operate in the DMA data transfer mode. In the DMA mode, a DMA controller
is interfaced to the BMC and DRQ-DACKIprotocol is used to perform byte transfers. Note that in the DMA mode, the BMC
activates its DRQ output each time it places a byte in the FIFO (bubble read operation) or each time there is room for at least
one byte in the FIFO (bubble write operation). When the DMA Enable bit is not set, the BMC operates in the intenupt driven
or polled mode. In either of these modes, the BMC's DRQ output goes active when 22 or more bytes are present in the FIFO
during a bubble read operation or when.there is space for 22 bytes during a bubble write operation. Note that if the DRQ is not
used (i.e., polled mode), the host processor must examine the Status Register's FIFO Ready bit to determine when data
should be taken from or written to the FIFO. '
MFBTR, (Maximum FSA to BMC Transfer Rate), determines the maximum burst transfer rate from the FSA(s) to the BMC
FIFO. This bit only applies to bubble read operations and is effective only during single-page transfers or during the transfer
of the last page of a mUltipage transfer. Table 3 shows the effect of MFTBR bit on the transfer rate for parallel bubble
operation.
Write Bootloop Enable, when set, enables the bootloop to be rewritten. Conversely, if this bit is not set and a Write
Bootloop command is received, the command is aborted immediately and the Timing Error is set iii the Status Register.
Since writing the bootloop only is performed as a diagnostic test or to recover from a system failure, this bit provides
protection against accidental rewrite of the bootloop data.

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Enable RCD (Read Corrected Data), when set, causes the BMC to issue a Read Corrected Data instruction to ali the FS;Xs
in the system in response to one or more FSAs reporting an error. On, receipt of the in'struction, each FSA cycles the
erroneous page through its error correction logic and then transfers the page to the BMC. For any FSA not reporting an error,
the data harmlessly cycles through the er:ror correction logic. When the page transfer is complete, the BMC interrogates the
FSA to determine ifthe error was correctable (if the error was uncorrectable, erroneous data would have been transfemid to
~~.

Enable ICD (Internally Correct Data), when set, causes the BMC to issue an Internally Correct Data instruction. Any
FSA reporting an error causes the instruction to be issued to all FSAs in the ~ystem.
On receipt of the instruction, each FSA cycles the data through its error ,correction logic (reg'ardless of whether it contained
an error), but does not transfer the page to the BMC. After cycling the page, each FSA reports its error Status (correctable or
uncorrectable) to the BMC. The FSA not reporting an error harmlessly cycles through the error correction logic !!lid reports a
correctable'error to the BMC. Note that both the Enable RCP and Enable ICD bits cannot be setat the same time.
;Enable Parity Interrupt, when set, enables the BMC to interrupt the host processor when it detects' a parity error on a data
'byte sent from the host processor (the BMC automatically checks for odd parity on each data byte received from the host
processor and implements odd parity on each byte sent to the host processor). When the Enable Parity Interrupt bit is not set
,and parity error is detected, no interrupt is generated (following the transfer, the Parity Error bit in the Status Register will be
s~.

~tatus

As stated at the beginning of this chapter, the host processor executes an 110 read instruction with the BMC's AO address
,input equal to" 1" to access the Status Register. As will become evident in the individual status Register bit descriptions, the
,Status Register is read in response to interrupts from 'the BMC,and, during polled data transfers, is read continually to
determine when data is to be written to or read from theBMC's FIFO.
'
The Status Register also provides information regarding error conditions, the completion or termination of cominands, and
the BMC's readiness to accept new commands. The individual Status Register bits are shown as follows.

,FIFO READY
' - - - - _ PARITY ERROR
' - - ' - - - -.... UNCORRECTABLE ERROR
' - - - - - - - - l..' CORRECTABLE ERROR,
' - - - - - - - - -. . TIMING' ERROR
' - - - - - - - - - -.... OP FAIL
'------~-------~ OP COMPLETE

L-------~---~~BUSY

Note that bits 1 through 6 are valid only when the Busy bit (bit 7) is not set and that these bits are cleared whenever a ~ew
command is received. The Status Register also can be cleared by writing to the register address counter (RAC) with bit 5 set
to~'l" ,and any valid parametric register address (OAH throug~ ooH).

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Busy. Bit 7, the Busy bit, is set ("I.") when the BMC is in the process of executing a command. The BMC sets its Busy bit
shortly after a command is received (the Busy bit must be clear in order for the BMC to accept any comniand other than an
Abort command) and keeps Busy set until the operation is complete (or until an operation is halted because an error has
occurred.)

It is important to note that the Busy bit remains set until all other status bits have been updated and that it therefore is possible
to see illogical bit combinations such as Busy and Op Complete at the same time. With the exception oftheFIFO Available
bit, all other Status Register bits should be considered valid only after .the Busy bit returns to an inactive ("0") level.
OP Complete, Bit 6, Op Complete, is set when the BMC successfully completes the execution of a command.
OP Fail, Bit 5, Op Fail, is set when the BMC is unable to complete execution of a command. In general, this bit is valid only
after the Busy bit returns to an inactive level; other error bits in the Status Register will be set to indicate why the operation
failed.
Timing Error, Bit4, Timing Error, is set for several error conditions. Themost frequent cause of timing errors is when the
host processor cannot keep up with the rate at which the. BMC fills or empties its FIFO (referred to as an overflow or
underflow condition). Timing errors also occur if the correct numbet of bits is not set in an FSA's bootloop register (to
function properly, an FSA must have either 272 loops active when error correction is not implemented or 270 loops active
when error correction is implemented). This condition occurs during a Read command if a mistake is made either when the
bubble's bootloop is written or if the bootloop register is loaded incorrectly from the user's system. Another source of timing
error is if no bootloop sync code is found during an Initialize or Read Bootloop command. The last source of a timing error is
when a Write Bootloop command is received by the BMC and the Write Bootloop Enable bit is not set in the Enable Register.
Of the preceding sources, regular or periodic occurrences of timing errors usually indicate an inherent inability of the host
processor to meet the bubble's data transfer requirements and will be most apparent during bubble read operations,
especially if the MFBTR bit is set (i.e., MFBTR=O in the Enable Register).
Correctable Error, Bit 3, Correctable Error, is set when an FSA reports that acorrectable error was detected during the last
bubble read operation. Depending on the level of error correction selected, the setting of this bit indicates a correctable error
in the current page held by the FSA, in the last page read, or in one of the pages read during a multipage transfer.
Uncorrectable Error, Bit 2, Uncorrectable Error, is set when an FSA reports an uncorrectable error during the last bubble
read operation. Like the Correctable Error bit, the setting of this bit depends on the level of error correction selected and
indicates an uncorrectable error in either the last page transferred or in the page currently held by the FSA.
Parity Error, Bit I, Parity Error, is set when the BMC detects a parity error o~ the data byte sent from the host during a
bubble write operation. If the Enable Parity Interrupt bit is set in the Enable Register, the BMC will terrninatethe write
operation and interrupt the host processor when the parity error is detected.
FIFO Available, BitO, FIfO Available, is unique in that it is the only bit the Status Register that is valid when the Busy bit is
set. During data transfer operations (i.e., when the Busy bit is set), the FIFO· Available bit acts as a gate for the host
microprocessor's data handling software. During bubble write operations, if the FIFO Available bit is set there is room for
more data in the FIFO and the host microprocessor can proceed with the transfer. Conversely, if the FIFO Available bit is not
set, the FIFO is full and the host must wait forthe BMC to "catch up" befo·re sending more data. During bubble read
operations, if the FIFO Available bit is set, data has been placed in the FIFO by the BMC and can be taken by the host
.
microprocessor; if the FIFO Available bit is not set, the data isnot yet available.

FIFO
The BMC's first-in first-out (FIFO) buffer passes data between the user interface and the FSA. The primary purpose for the
FIFO is to reconcile timing differences between both the user interface and the BMC and between the BMC and the FSAs.

6~165

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The FIFO itself is 40 bytes wide and, including the FIFO's input and output latches and the BMC's input latch, can store up to
, 43 bytes. The FIFO is "dual ported" inthat data can be written into one port while siIimltaneously being read from the other
port.
When the BMC is busy executing a command, the FIFO functions as a data buffer, and when the BMC is not busy, the FIFO
is available for use as a general-purpose FIFO. For this reason, the BMC is said to be in the'general-purpose FIFO mode
when it is not busy. During execution of commands that involve the transfer of data between the user interface and the FSAs,
the data passes through the FIFO , and the status of the FIFO is indicated by the FIFO Ready bit in the BMC's Status Register.
When the FIFO Ready bit is set ("one ") during a write operation, there is space in the FIFO for more data, and when this bit
is set during a read operation, data is present in the FIFO.
The BMC's DRQ output also indicates FIFO status. In the DMA data transfer mode; DRQ is used in conjunction with the
DACKI input from a DMA controller (e.g., in Intel 8257 or 8237) on the user interface to provide a standard DMA data
transfer protocol. In the non-DMA transfer mode (polled or interrupt-driven data transfers), the DRQ output indicates that
the FIFO is either half full or half empty according to the direction of the data transfer; during a write operation, DRQ is set
when there is space for 22more bytes;and duringread operation, DRQ is set when there are 22 bytes present in theHFO.
Accordingly, when performing non-DMA data transfers, blocks of 22 bytes should be transferred tool' from the FIFO so that
the host processor does not spend a disproportionate amount of time servicing the DRQ-initiated interrupt or polling the
BMC's Status Register.
The FIFO automatically is addressed after the last parametric register is written due to the self-incrementing nature of the
Register Address Counter. Alternatively, the FIFO can be addressed explicitly by writing to address 0 of the Register
Address Counter:'Note that since byte 0 of the FIFO is cleared whenever the Register Address Counter is addressed, writing
the parametric registers (or to the FIFO itself) must be avoided while the FIFO contains valid data; Also, when' using the
FIFO in the general-purpose mode, the host system is responsible for resetting the FIFO prior to any data transfer.
During read and write operations, the host system is responsible for keeping up with the data transfer in order to prevent a
FIFO overflow or underflow condition. If the FIFO overflows or underflows during the data transfer, the operation is aborted
and the Op Fail and Timing Error bits are set in theBMC's Status Register.
The FIFO AVAILABLE bit is also set whenever the RAC is not pointing to the BMC FIFO (RAC address = OOH). When
writing the parametric registers, for example, if the user reads the status between say the Enable Register and the Address
Register, the status byte would indicate FIFO AVAILABLE. This status value is forced by internal BMC'logic:

COMMANDS
The BMC's command set consists of 16 commands that are selected by a 4-bit command code. As previously described,
commands are passed to the BMC by writing to the. BMC's command port with .bit 4 of the command byte set to "I" (the
Register Address Counter is addressed when bit 4 is "0"). Table 5 lists the 4,-bit command codes and the corresponding
commands.
'For most commands sent)o the BMC, the parametric registers must be loaded with operating information' before the
command is sent. Also, with the exception of the Abort command, commands cannot be issued to the BMC while another
command is being executed (i.e., when the Busy bit in the Status Register is set). The remainder of this section offers brief
descriptions of the BMC's command set; descriptions of command usage are presented in succeeding sections. J'able 6 of
this section presents a summary of command execution times.
The 16 commands can be grouped into categories according to their frequency of use. The most commonly used commands
are:
•
•
•
•

Abort
Initialize
Read Bubble Data
Write Bubble Data

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Other commands used during normal bubble system. operation include:
•
•
•
•
•
•
•
•

Read Seek
Write Seek
MBM Purge
Read Corrected' Data
Reset FIFO
Software Reset
Read FSA Status
Read Bootloop

The remaining commands are related to bootloop operation and are used only for diagnostic purposes:
•
•
•
•

Read Bootloop Register
Write Bootloop Register
Write Bootloop Register Masked
Write Bootloop

Abort
The Abort command (unlike any other command), when issued while the BMC is busy executing another command, causes
the termination of the command being executed. On receipt of this command, the MBMs are stopped in an orderly manner to
prevent the loss of bubble data: Since the Abort command is the only command recognized by the BMC while it is busy, this
command is issued following power-up or whenever the BMC is' in an unknown state. The Abort command requires no prior
loading of the parametric registers .
.When an Abort command is issued while the BMCis not busy, the command functions as an FIFO Reset to clear any data
present in the FIFO. An Abort ,command issued when the MBM drive coils are active (i.e., data transfer command is
executing indicated by the Busy bit in the Status Register) must be followed by an Initialize command.

Table 5. BMC Command. Set

Write Bootloop Register Masked
Initialize
' Read Bubble Data
Write Bubble Data
Read Seek
Read Bootloop Register
Write Bootloop Register
Write Bootloop .
Read FSA Status
Abort
Write Seek
Read Bootloop
Read Corrected Data
Reset FIFO
MBM Purge
Software Reset

Table 6. 7220-1 Command Execution Times'
Four-Bit
Command
Code
(Hex)

1 FSA channel selected
2 FSA channel selected

900 J,tS
900 J,tS

Initialiie

Best case (N=#MBM)
Worst case

350+(85,200) N J,tS
350+(164,740) N p-s

Read

Single page (MFBTR=O)
Single page (MFBTR = 1)
N page transfer (MFBTR=O)
N page transfer (MFBTR=1)

tSEEK +8690 J,tS
t sEEK +12,770 J,tS
tSEEK + 8690+(7500) (N-1) J,tS
t SEEK +12,770+(7500) (N-1) J,tS

Write

1 page transfer
N page transfer

tSEEK + 7450 J,tS
t SEEK + 7450+(7500) (N -1) J,ts

Any number of FSA channels 900 J,tS

Write BLR

Any number of FSA channels 900.J,ts

Write BL

Single bubble selected

82,850J,ts

Read FSA Status'

1 bubble in system
Nbubbles in system

75 J,tS

75+40 (N-1) J,tS

Abort

1 bubble in system
N bubbles in system

100 J,ts
100+40 (N-1) J,ts

Read Corrected Data Any number of FSAs selected 1400 J,tS

Initialize
The Initialize command prepares the bubble system for subsequent operations and is used when the bubble. system is
powered up (following the Abort command) or whenever the system's error correction implementation is changed. The
Initialize command effectively performs the following BMC commands:
•
•
•
•
•

Abort
MBM Purge
FIFO Reset
Read Bootloop
Write Bootloop Register Masked

When an Initialize command is received, all internal registers within the BMC are cleared and the FIFO is reset. The BMC
then reads the bootloop from each bubble and writes the corresponding bootloop information into the bootloop registers of
each FSA. The bubble is left positioned at page zero (logically) corresponding to the values set in the BMC page address
counters. Before an Initialize command can be issued, the following information must be loaded into the parametric
registers:
• The channel field in the Block Length Register must be set to "0001" to arrange all. bubbles in the system in a serial
configuration to allow the individual bootloops to be read from each bubble and subsequently written to the bootloop
registers of the corresponding FSA channels.
• The MBM select field in the Address Register must select the last (highest numbered) bubble in the system to inform the
BMC of the number of bubbles present within the system (for a one bubble system the value would be "0000").
• The bits selecting error correction in the Enable Register must be set according to how subsequent read and write
operations are to be performed (with or without error correction) since the number of I's written to the FSA bootloop
registers is not the same with error correction implemented as when error correction is not implemented. Note that
simply switching between ECC modes (level I, 2, or 3) does not require re~initialization.

Read .Bubble Data
The Read Bubble Data command causes data to be read from the MBMs and into the BMC's FIFO. Immediately before the
Read Bubble Data command is issued, the host computer must load, with the exception of the Utility Register, all of the
parametric registers. Specifically, the following parametric information must be loaded prior to command execution:
• The channel and "number of pages to be transferred" in the Block Length Register must be set to define the page size
(number of FSA channels) and number of pages to be transferred.
• The appropriate bits must be set in the Enable Register to select the transfer mode (DMA or non-DMA) and interrupt
sources; if error correction is to be used (i.e., if the FSA bootloop registers have been initialized for error correction),
the level of error correction must be selected.
• The MBM select and starting address fields in the Address Register must be set to define the (first) MBM and page
within the MBM ':Vhere the transfer is to occur.

Write Bubble Data
The Write Bubble Data command causes data read from the BMC's FIFO to be written into the MBMs. Immediately prior
to issuing the Write Bubble Data command, the host computer must load the Block Length, Enable, and Address Registers
as described for the Read Bubble Data command. Data should not be loaded into the BMC FIFO until after the command
has been issued. Note that a write data transfer does not begin until at least two bytes of data have been loaded into the
BMC FIFO.

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Read Seek
The Read Seek command is used to reduce system access time of a subsequent Read Bubble Data command by positioning
the page to be read at the selected bubble's output track. Note that although the Read Seek command does not cause any data
to be transferred, the following information,must be loaded irtto the parametric registers before the command is issued:
• The. channel field in the Block Length Register must specify the page size (number of FSA channels).
• The error correction bits in the Enable Register must be set identical to the values used when the system was initialized.
• The MBM select field in the Address Register must be set to select the bubble containing the page to be read and the
address field must specify a page number that is one less than the (first) page to be read by the subsequent Read Bubble
Data command.

Write Seek
The Write Seek command is used to reduce the system access time for a subsequent Write Bubble command by positioning
the page to be written at the selected bubble's input track. Note that like the Read Seek command, the Write Seek command
does not cause any data to be transferred. Similarly, the following information is issued:
• The channel field in the Block Length Register must specify the page size (number of FSA channels).
• The error correction bits in the Enable Register must be set identical to the values when the systern was initialized.
• The MBM select field in the Address Register must be set to select the bubble containing the page to be written and the
address field must specify a page number that is one less than the (first) page to be written by the subsequent Write
Bubble Data command.
.

MBM Purge
The MBM Purge command is used in place of the Initialize command when the bootloop register is to· be loaded from an
external source (once a bootIoop has been identified, the bootloop register pattern can be maintained by the host andJoaded
directly from external memory with a Write Bootloop Register or Write Bootloop Register Masked command to conserve
power and increase speed during an initialization sequence). The MBM Purge command clears the BMC's internal registers
and the address field of the Address Register. The MBM select field in the Address Register and the other parametric
registers are not cleared. Like the Abort command, the MBM Purge command does not require the loading ofthe parametric
registers prior to command execution.

Read Corrected Data
The Read Corrected Data command is used only when error correction is implemented and only is applicable when error
correction level 2 or 3 is selected (the Read Corrected Data command is issued automatically by the BMC when error
correction level! is selected). When an FSA reports a correctable error, the Read Corrected Data command is issued to cause
. the corrected page in the FSA(s) to be read into the BMC's FIFO. Note that since the parametric registers previously were
loaded for the read operation in which the error was detected and since the address field is not incremented (i.e., the address
of the page in error is in the address field), it is not necessary to load the parametric registers prior to issuing the Read
Corrected Data command.

Reset FIFO
The Reset FIFO command'causes the BMC's FIFO (and its input and output latches) to be cleared. Normally, this command
is issued prior to issuing the Write Bootloop, Write Bootloop Register, or Write Bootloop Register Masked commands to
ensure that the FIFO will accept 40 bytes; the Reset FIFO command does not require loading of the parametric registers.
I.

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Software Reset
The Software Reset command clears the BMC's internal registers, and the terminal count field in the Block Length Register
and starting address field in the Address Register. Additionally, the Software Reset command causes the BMC to clear the
status register of every FSA channel in the system. Since the Software Reset command does not clear the FSA channel and
MBM select fields in the Block Length and Address Registers or any of the Enable Register bits, it is not necessary to
reinitialize the parametric registers following a Software Reset command, and no loading of the parametric registers is
required prior to command execution.

Read FSA Status
The Read FSA Status command causes the BMC to read the 8-bit status register of each FSA channel in the system (the
number of FSA channels specified in the channel field of the Block Length Register). This command is issued to determine
the number of FSAs in a system. Following command execution, the individual status register bytes will be in the BMC's
FIFO in ascending order; one byte per FSA channel. All values returned to the host will be 2QH or 28H if error correction is
enabled. This occurs because the FSA status is cleared when read. The BMC always reads the FSA status prior to
interrupting (or informing) the host of an error. Therefore, the Read FSA status command can only read the" cleared" FSA
status values (2QH or 28H). No loading of the parametric registers is necessary prior to command execution.

Read Bootloop Register
The Read Bootloop Register command' causes the BMC toread the bootloopregister of the selected FSA channel into its
FIFO. This command is used initially to ensure that the bubble system is communicating properly (bubble-to-FSA and
FSA-to-BMC communication established) and is used to transfer bootloop information to the host system for subsequent
bootloop initialization from an external source (e.g., user EPROM). Prior to command execution, the channel field in the
Block Length Register and the MBM select field in the Address Register must be loaded with the number of FSA channels
(normally two) and the corresponding bubble (FSA channel pair) to be selected. Note that since each individual FSA
channel's bootloop register contains 20. bytes, reading a pair of FSA channels fills the BMC's 40-byte FIFO; reading the
bootloop registers of more than two channels is possible but not recommended since data must be taken from the FIFO to
avoid an overflow. condition. Also, since the bootloop register data from each FSA channel pair actually is interleaved on a
bit-by-bit basis before it is assembled into bytes, reading the bootloop. register for a single channel likewise is not
recommended. Remember that a unique BMC status value (CIH or C3H) is expected with this command (see "Considerations for Polled Command Execution").

Write Bootloop Register
The Write Bootloop Register command causes the BMC to write the contents of its FIFO into the bootloop register of the
selected FSA channel(s). This command (and the Write Bootloop Register Masked command) is used during bubble system
initialization when the bootloop is written from an external source rather than from the bubble itself. In order to use the Write
Bootloop Register command, the bootloop register data must be loaded into the FIFO prior to command execution and the
channel and MBM select fields of the Block Length and Address Registers must be loaded with the numberofFSA channels
(normally two) and the corresponding bubble (FSA channel pair) to be selected. Recalling that each individual FSA
channel's bootloop register contains 20. bytes, 40. bytes normally are written into the FIFO to initialize the two FSA bootloop
registers associated with each bubble. However, a 41 st byte of zeroes must be written to ensure a successful command
execution status. Note that the parametric registers should be loaded prior to loading the FIFO.
Proper operation of the bubble system requires that each FSA bootloop register contains either 135 (error correction
selected) or 136 (error correction disabled) logic" I" bits that correspond to the 135 or 136 valid data storage loops.

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Write Bootloop Register Masked
The Write Bootloop Register Masked command is identical to the Write Bootloop Register command previously described
.with the exception that the number of "I " bits written automatically is stopped when the required 135 or 136 logic "I" bits
have been written for each channel. The parametric registers are loaded as described forthe Write Bootloop Register
command; the number of logic" I" bits written (135 or 136) is determined by the setting of the error correction bits in the
Enable Register.

Write Bootloop
The Write Bootloop command causes the existing contents of the selected bubble's bootloop to be replaced by the 40 bytes of
information currently contained in the BMC's FIFO. This command is used only after it has been determined that the
existing bootloop is invalid (i.e. , a storage loop previously identified as "good" has become defective) and typically is not
required for the life of the bubble system. Remember that the parametric registers must belo,!ded,prior to pre-loading the
FIFO with the 40 bytes of information to be written followed by a 41 st byte of zeroes.
If it should become n~cessary to use the Write Bootloop coinmand, the channel field in the Block Length Register and the
MBM select field in the Address Register must be loaded with the number ofFSA channels and the corresponding bubble to
be selected. As.an additional safeguard, the Write BootloopEnable bit in the Enable Register additionally must be set (ifthis
bit is not set, command execution immediately will be aborted and the Timing Error bit will be set in the Status Register).

Read Bootloop
The Read Bootloop command causes the BMC to read the bootloop of the selected bubble into its FIFO. This command
is used to determine if thy existing bootloop is valid by comparing the bubble bootloop information to that on the label
of the device. Remember that the parametric registers must be loaded prior to command execution. Also note that a
BMC status value of CIH or C3H is expected (see "Considerations for Polled Command Execution").
I

ERROR CORRECTION
As mentioned earlier in this application· note, several factors pertaining to error correction must be understood and
weighed according to your specific application before implementing error correction. From a software perspective, the
selection of the appropriate leve1.of error correction'is based on the host system's requirements relative to error 10ggi\1g
and data recovery. Before describing the individual levels of error correction and the associated software requirements,
thetypes·of errors that can occur within bubble memories are described as a preface to error correction,

Bubble Errors
To understand the function and implementation of error correction, the differences between bubble errors and
semiconductor device errors must be distinguished. In conventional semiconductor memory, errors are classified as either
hard (non-recoverable) or soft (recoverable). Usually, hard errors are the result of physical or irreversible damage within the
device itself (e.g., oxide breakdown or junction burnout), and soft errors are the result of transient conditions and generally
do not reappear when the data is rewritten.
Unlike semiconductor devices, bubble memory devices have no active elements and, as such, rarely experience hard
(non-recoverable) errors. Accordingly, all bubble memory errors can be considered as soft errors (for information on
irreversible failure mechanismli in bubbles, refer to the Intel711 0 Bubble Memory Reliability Report, RR-36 Order Number
210632). In order to further define the nature of soft errors in bubbles, errors are classified either as "data" errors or "read"
errors. A data error occurs when a data inversion occurs within a storage loop; the data is lost, but since no physical damage
has occurred, the data can be rewritten and the bubble can remain operational. Data errors typically occur when the bubble is
operated beyond its safe operating region and, as such, are seldom encountered during normal operation. The most common
type of soft error is a "read" error that occurs during a bubble read operation, usually as a result of noise in the
detectionlsensecircuitry. Since the data in the storage loop is unaltered during a bubble read, the data can be recovered by
simply repeating the read operation.

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Error Detection/Correction Capability
In respect to the Formatter/Sense Amplifier (FSA) , errors either are correctable (the FSA is able to reconstruct the data using'
an error correction algorithm before the data is transferred to the BMC) or uncorrectable, irrespective of the type of error
(data error or read error). The error correction code used by the FSA is a l4-bit Fire code that is appended to each 256-bit
block of data. This code is capable of correcting all single error bursts up to, and including, five bits in length and has proven
to be well suited to the error model for the7!l 0 MBM, Table 7 outlines the FSA's error correction capability and probability
of page errors; the bit error rate can be obtained by dividing the :'probability of page in error" by the number of bits per page.

ECC Options
The FSA's error correction circuitry (ECC), in conjunction with the BMC, provides three levels of error correction. Each
, level places unique demands on the host system that range from simple data recovery'to the logging of specific pages in
which the error occurs. The desired level of error correction is selected by the setting of the appropriate bit or bits within the
BMC's Enable Register. Table 8 defines the relevant Enable Register bits for the three levels of error correction available.

Table 7. FSA Error Detection/Correction C~p~bility ,
Approximate
Probability of
Page in Error

Random Double Read Error

Read Error Burst Length 5,

100

Random Triple Read Error

10 "

100

, Read Error 'Burst Length 2'
Data Error Burst Length 2
Read Error Burst Length 3/4
Random Double Data Error

Single Soft

100

Read Burst 2

Undetected/Uncorrected
Error Escape Rate :

100

NOTES:
1. Read errors are recoverable by retry or error correction.
2. Data'errors are recoverable by error cor;ecijon rr;ethods only.

, Table 8: Error Correction' Level Selection'
, Enable
Error
Correction
Level

Bit 6
ICO
,

Bit 5
RCO'

Regl8~er

Bit
Bit 1
Interrupt Enable
(Error)

In typical bubble memory systems, the prevention of the erroneous transfer of data to the host is primary concern, and the
actual location of the error (errorlogging by page) is secondary. This fact is especially true if the error is correctable. Both the
prevention of transferring erroneous data and error logging ofthe page in error, however, can be satisfied by error correction,
and you must select the error correction level that best fits your specific application.
.

ECC Operation
When error c~rrection is implemented, each page --+-_4"174SC245 16
AO
5
U5
15
OACKI
ORO
INT

7230
POWERFAIL
PIN 21

+5 Vdc

INT

+SVdc
POWER·ON INTERRUPTI
V1

OPTIONAL:
POWER·ON INTERRUPT
POWER·ON INTERRUPT

(SEE POWER
SUPPLY
SWITCHING CIRCUITRy)

R10
5.1K

-I. . .

• HIGH ACTIVE INTERRUPT IS
NOT AVAILABLE IF 114 OF Ul
IS USED TO SWITCH THE
BUBBLE MEMQRY DETECTOR_

+ 5 Vdc
FROM HOST
POWER
SUPPLY

U4:20

- - i..
~ U5:20

U6:14

'_F·1~F. U4:10
U5:10
U6:7

Figure 7. Bubble -MelTlory Power Switch CMOS Bus Isolation Circuitry Polled/DMA Mode

6·203

Ap·164

Enabling The Interface Bus
Once the power supplies are operational, the switching circuit will enable the interface bus. Figures 6 and 7 are two
possible designs for the bus transcievers; Figure 6's circuit supports polled data transfers only, Figure 7 is a modified
version of Figure 6 which supports either polled or DMA. Both designs use the open collector output of a comparator to enable the BMC .control signals; the output is tied high to 5 Vdc vhi 5;1 kohlJ1 resistors. The inputs to the
comparator are 2.5 Vdc on the positive input and the 7230 current pulse generator's powerfail output, PWR.FAILI.
(pin 21), is sent to the negative input.\Vhen PWR.FAILI is high, greater than 2.5V, the bus is enabled, and an active low PWR.FAILI signal would disable the bus.
.
The data bus lines are not enabled until the processor selects the bubble system to'do a data transfer by setting CSI
(or DACKI for DMA) active low.
As an option, bus the output signal of the PWR.FAILI comparator to the host processor 'for an .interrupt to d~tect
when the power supplies are operational. Otherwise the processor will have to delay interacting with the bubble
system until the supplies can be guaranteed operational. Invert the interrupt line with the unused fourth comparator
if your processor supports active high interrupts; PWR.FAIL( is active low on a power-down.

SOFTWARE CONSIDERATIONS
All the software information needed to successfully power switch a bubble system is presented here. Application
Note 157, Software Design and Implementation Details for Bubble Memory Systems, isa useful reference if you are
unfamiliar with the. fundamentals of bubble memory software.

Data Transfer Modes
Two data transfer modes compatible. with the switching circuit's bus interface are polled and DMA.'POlled mode is
easy and consumes the least amount of power and board space. DMA requires a DMA controller and the BMC's
DRQ, DAC~/and INT signals are added to the bus interface.
.

Initializing The Bubble Memory
An initialization procedure must be followed after every power-up to place the BMC in a known state, to load the
bootloop code into the bOOtlClOP registers and to synchronize the bubble memory to its ,first logical page of 64 bytes.
In power switched systems, power-ups will occur before each memory access and a fast initialization routine is very
desirable.
.
There are two ways to initialize a bubble memory. One is an internally generated command sequence executed by
sending the INITIALIZE command to the BMC. The other method emulates INITIALIZE by sending the com-.
mand sequence and bootloop code from the host processor to the BMC, but does not synchronize the bubble
memory. This external initialization does have the advantage of being faster; worst case execution of an INITIALIZE command is 170 ms versus 5ms fman external initialization.
Both typesof initialization should be used ina power switched configuration. Send an INITIALIZE commandilfter
every cold start to synchronize the bubble memory. At the completion of the data transfer, have the BMC execute a
WRITE SEEK to location (page) 395H or a READ SEEK to location 9BH. This will synchronize the bubble as the
INITIALIZE command did. The bubble is non-volatile so this synchronization will not be lost even when power is
removed. On the next and subsequent power-ups, use the external initialization to quickly put the BMC into a
known state and place the bootloop code into the bootloop registers. Then continue to do a seek operation on each
power-down to keep synchronization. Figure 8 flowcharts the operating sequence just described for low power bubble memory systems. Figures 9 and IO are the power-up and down sequences. Flowcharts for the internal and external initialization routines are in the appendix.

6·204

Ap·164

Comments: The sequence of events outlined in the
flowchart must be executed each time
the host processor is powered-up.
* The typical time between removing the

power from a Bubble Memory to powering back up should be approximately
one second or greater to derive the
maximum benefits from power switching .
•• An external initialization Is used to
decrease the power-up overhead time
from 235 rns with an internal initialization to less than 160 ms. However, in
all cases, an internal intitialization can
be substituted for an external intitialization to accommodate existing software.

Additional detail can be found in the
following flowcharts:
A.
B.
C.
D.

Powering·Up A Bubble Memory, Fig. 9
Powering· Down A Bubble Memory, Fig. 10
Internal Initialization, Fig. 13
External Initialization, Fig. 14

Figure 8. Low Power Bubble Memory System Flowchart

6-205

AP-164

Comments: An optional Power-On Interrupt is
available from the Bubble Memory
power supply switching circuitry to
detect when Vs and Vd have reached
their respective threshold voltage_ The
Interrupt can be omitted in place of an
additional deiay_ The amount of delay is
system and power supply dependent
but Is usually less than 5 ms.
Further detail concerning the successful
execution of the Abort command
can be found in Application Note
157, "Software Design and Implementation Details for Bubble Memory
Systems."

.. In all cases. a seco'nd ABORT command
guarantees that the BMC resets.
Total execution time Is typically less than
155 ms.

Figure 9. Power-up Flowchart for a Low Power Bubble Memory System

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AP·164

Comments: Either a Write Seek Command at ad·
dress 394H or a Read Seek Command
at 09AH Is sufficient to synchronize the
Bubble for an external 'Initialization.
Seeking prior to powering·down is not
necessary if an external initialization is
not implemented.

WRITE 1220 PARAMETRIC REGISTERS
(A) ADDRESS REG = 394H OR
(B) ADDRESS REG = 09AH

Worst case seek time is 90 ms. Average
seek time is 48 ms.

ISSUE
(A) WRITE SEEK COMMAND
(B) READ SEEK COMMAND

COMPLETE SEEK COMMAND

RESET ON/OFF
BIT
0

Figure 10. Power·down Flowchart for a Low Power Bubble Memory System

6-207

Ap·164

An easy way of keeping the bootloop code outside the bubble is to read it out of the bootloop registers, after each
cold start, into the host system's RAM. Then retrieve the code from RAM for each external initialization.
The seek commands expect their operands to be the number of the page one previous to the page you wish to seek.
For example, the page that should appear as the operand in the WRITE SEEK command for the initialization
routine above is 394H and the READ SEEK operand should be 9AH.
If speed is not a factor, you can use the INITIALIZE command after every power-up, but the total amount of time
before a data transfer can begin will still be .the time it takes for the power supplies to become operational, typically
155 ms plus the time to initialize the .bubble system,

Power-up + Internal Initialization = 325 ms (worst case)
Power-up + External Initialization = 160 ms (worst case)

Efficient Software
Every operation run on your system sets its own bubble memory needs. How efficiently your system· responds to
these needs determines how much power is dissipated. Some suggestions for energy efficient drivers and programs
follow.
If information is called in a fixed sequence, store it in that fixed sequence ..

Instead of repeatedly accessing the bubble for the same information, transfer the data into system RAM and retrieve
it from there.
Transferring many pages of data is more efficient than doing many small transfers.
Intrinsically, running multibubble systems in serial will use less power than running parallel memories since in the
former case only the coil drives of one bubble memory will be active at anyone tiIlle. For example, a system running
two bubbles in serial will have one active bubble memory and one bubble in standby mode any time the'system is ac~
cessed. This means 5.45 W, 3.9 W + 1.55 W, will typically be dissipated during the access. Run in parallel, these
same two bubbles will typically dissipate 3.9 W each or 7.8 W total during a data transfer.

DETECTOR SWITCHING
Although power switching is the primary hardware technique, the.BMC has an output signal that indicates when the
detector stacks are active. One advantage detector switching has over power switching is that the bubble system does
not need to be reinitialized when power is reapplied.
Since the stacks are only used to sense the bubbles during read operations, the DETECTOR ONI signal can be used
to switch power to the detectors. Standby power consumption can be.reduced by 200/0 per bubble memory if the
detectors are switched off and the incremental amount you gain by leaving them off during write operations depends
on the frequency and duration of your read and write operations. For example, a jet airplane's bubble memory
flight recorder (using eight one mega-bit bubbles) has data written out to it on every flight. It will only be read if
there is a problem during a flight. By switching off the detectors, four watts are saved on each flight (0.5
W/bubble).
Figure)I is the circuit diagram for a detector switch. DETECTOR ONI is inverted with a comparator; DETECTOR ONI is the negative input, 1.5 Vdc is the positive input and the output is tied high to 5 Vdc through 100 kohms.
The inverted signal is used to change an NFET's gate voltage which turns the NFET on and off. That in turn switches the detector supply on and off. Placement of the NFET is critiCal; lay it out as close to the bubble memory as
possible.

6-208

Ap·164

+ 12 Vdc
(SWITCHED)

DET.SUPPLY
7110
BUBBLE MEMORY

15 DET. COM •

.-------"y'V'lr-..,....,
S

D
Q3

+5 Vdc
• EXISTING CIRCUITRY

Rll
lOOK

**V2

---<>----__.......>----__•

>..:.1::..3

ADDITIONAL BUBBLES

DET. ON
7220, PIN 28
•• SEE BUBBLE MEMORY POWER SUPPLY SWITCHING CIRCUITRY

Figure 11. Bubble Memory Detector Power Supply Switching Circuitry

6·209

Ap·164

With a very restricted power budget, consider implementing both power and detector switching. In the sample
switch, the unused fourth comparator is available for the detector switch if it is not used to invert the optional
power-on interrupt.
Figure 12 is a graph comparing complete switching to the amount of average power dissipated.

"Detector Switched Systems

Average Power Dissipated
Standby

Case 5: Worst Case Systems
Case 6: Typical Systems
Case 7: Typical Power
Switched Systems

Power Switched Systems

6.0

• Assuming 50% Reads, 50% Writes
to the 7110 Bubble Memory

.""'--'-:-- CASE 8

5.0

CASE 1 -----I.".....
CASE5---__~~~

.,-.---- CASE 7
~~~~----CASE6

~jtL-------CASE

One Mbit Bubble Systems
Average Power Dissipated
Standby
3.0 W
1.55 W
O.OW

Max.

---s:'iW
3.9 W
3.9W
6.7W

% OF DUTY CYCLE BUBBLE IS ACTIVE

Figure

12. A Complete Comparison of Bubble Memory Activity to the Amount of Average
. Power Dissipated by the Bubble Memory System

SUMMARY
The main goal of this application note is to assist designers developing portable or other low power equipment. By
utilizing the CMOS controlled power switch, a designer can build a simple, reliable, low power bubble memory
system with a minimum of time and effort.

6-210

Ap·164

APPENDIX A
Typical Measured Values @ 25°C
Configuration -

One megabit Bubble Memory System incorporating a polled mode interface.

Case 1: Power-On = Off
Bubble Memory System Power Consumption
Case 2: Power-On = On
Bubbl.e Memory in Standby
, Total Bubble Memory System Current
, Bubble Memory System Power Consumption
Voltage Drop Across the FET Switch
Case 3: Power-On = On
Bubble Memory Actively Transferring Data
, Total Bubble Memory System Current
, Bubble Memory System Power Consumption
Voltage Drop Across the FET Switch
Power-Up Rise Time (Power-On

= 1)

Power-Down Fall Time (Power-On

'Includes an Intel 8284A clock generator to produce the required 4 MHz clock for the 7220 controller
and BPK-70 (7242 Formatter Sense Amplifier).
Clock Specifications:

Parameter
Clock Period
Clock Phase Width (High)
Input Signal Rise Time

6-211

Min.
249.75 ns
45%

Max.
250.25 ns
55%
30 ns

Ap·164

Comments: After completing the Read Boot Loop
Register Command, a copy of the Boot
Loop Register is available in the 7220's
FIFO. The .contents of the FIFO must be
stored in the host processor's RAM for
later use when performing an external initialization. Transferring a copy of the
Boot Loop Register Is not necesary if an
external Initialization is not implemented.

WRITE 7220 PARAMETRIC REGISTERS

Further detail concerning the successful
execution of Bubble Memory Commands
can be found in Application Note 157,
"Software Design and Implementation
Details for Bubble Memory Systems."

ISSUE
FIFO RESET COMMAND

Total worst case execution time 170
ms. Ayerag~ exec~tion time is 90. ms.

ISSUE
READ BOOT LOOP REGISTER COMMAND

STORE B'OOT LOOP
REGISTER'S CONTENTS IN HO.ST RAM

Figure 13. Internal Initialization Flowchart

Comments: Total execution time is less than 5 ms.
Further detail concer.ning,th~ suc'cessful execution of Bubble Memory
Commands can be found in Application
Note 157, "Software Design and 1m·'
plemeniation Details for Bubble
Memory Systems."

ISSUE·
MBM PURGE COMMAND

WRITE 7220 PARAMETRIC REGISTERS

ISSUE
, FIFO RESET COMMAND

XFER BOOT LOOP REGISTERS
FROM HOST RAM TO 7220 FIFO

ISSUE
WRITE BOOT LOOP REGISTERS
MASKED COMMAND

Figure 14. External Initialization Flowchart
6-212

ARTICLE
REPRINT

AR·243

Thin-film detectors,
X-ray lithography
deliver 4-Mbit bubble chip
Next-generation bubble memory chip is ellen smaller
than the compatible, 1-Mbit dellice; set of support
circuits takes care of memory system requirements.
Propelled by X-ray lithography and thin-film permalloy detectors, bubble memory chips
have climbed to the 4-Mbit level.
Using X-ray lithography, Intel
Corp. (S.anta Clara, Calif.) has
managed to reduce the periodicity between bubbles from 11.2
(for its 1-Mbit chip) to 5.6 I'm and
feature sizes from 1.25 to 0.75 I'm.
At the same time, thin-film permalloy detectors, replacing
thick-film versions, nearly double the signal strength of the detected bubbles (Fig. 1).
Moreover, a novel multiplexing
technique handles the outputs
from the eight on-chip detectors,
which is double the number used
on the 1-Mbit chip. This technique, which Intel is keeping under wraps, permits the higherdensity chip to fit into a 22-pin
package.
The outcome of all that is the
7114, plus it complement of six
support circuits. The 7114 retains
the basic architecture of the
1-Mbit.7110, and all the support
circuits are pin-compatible with
the chips that support the 7110.
Aside from a few software
changes to handle the larger
memory space, the upgrade is
totally transparent to the system
user, claims Mike. Eisele, bubble
memor~'product manager. Thus
in many cases the older bubble
chips c~n be removed from a system and new ones plugged in.
Dava Buraky

However, the support chips
cannot control the 1-Mbit device,
and some minor hardware
changes must be made to accommodate the smaller package used
for the 4-Mbit chip. The package's dimensions-1.46 by 1.35

1. A key element of Intel'. 4-Mbit
bubble memory i. this thin-film
permalloy detector structure, which
deliver. twice the output signal of the
previously lI.ed thick-lilm detector.
Density

2. Following Ihe same growth curve a.
UY EPROM. and dynamic RAMs,
bubble memory technology .till has. a
good way to go to reach the 18-Mbit
level projected for 1986.

in.-represent a savings Of
nearly 0.9 in.~ over the 1-Mbit
package's 1.7 by 1.68 in. In addition, the smaller package, which.
has DIP-like pins, eliminates the
need for. a: socket in many cases
and also has a lower profile to
permit board spacings as close as
0.6 in. The same package will be
used by Motorola Inc. (Phoenix,
Ariz.) :.vhen it builds the secondgeneration 1-Mbit chip as called
for in the alternative-source
agreement signed earlier this
year with Intel (EI.ECTRONIC
D~;8IGN, July 8, p. 23).
However, to bring the price of
the bubble memories down to
what Eisele feels would be attractive for systein users-about
$150 f~r a 4-Mbit chip by
1986.-lntel has turned to a
Perkiri-Elmer X-ray lithography
system in what it believes to be
the first commercial use of X-ray
systems. (Other companies,
though, are not yery far behindman~' semiconductor manufacturers have very active
research arid development programs to make X-ray systems
practical on the production line.)
The production process for the
4-Mbit chip includes 90% of the
process steps used for the 1~Mbit
device, thus sharing much of the
learning-curve experience, in the
short run.
Functionally, the 4-Mbit device will appear to. operate just
like .the l-Mbit memory. However, when the 7114 operates at the
50-kHz field rate of the 1-Mbit
device, the access time is double
that of the smaller chip, since the
loops are longer. But the data
rate is double that of the 1-Mbit
chip because more detector outputs are multiplexed and then
fed out from the chip. Also, a version of the 4-Mbit chip will opere
ate at twice the field rate (100
kHz); for an access time of 41
ms-almost the 40-ms access

Electronic Design

6-213
Reprinted with permission from Electroni.c Oesign, Volume 30, No. 22 Copyright Hayden Publishing, Inc. 1982

time of the I-Mbit chip.
current-pulse generator. the 7244
There will be a full kit of parts
formatter-sense amplifier. the
available from Intel when sam7250 coil predriver. and the 7254
ples of the memory will be availcoil drivers.
able next year. The largest'chip
Bubble memory capacity has
will be the 7224 controller. which . been quadrupling about'e~ery
duplicates the functions of the
four to five years. This follows
7220 controller out has'the inter- .very closely what happened to
nal changes lIeeded to handle the
UV EPROMs(Fig, 2) •.even
larger memory space. Simila.rly; . though EPROMs weiIt thr
~

":~\

I
.,

7520
coil
predriver

7254
VMOS
drive
transistors .'

7114
magnetic
bubble memory

,;,4.4iIbIt~""""'iIouM
,

4-Mbil bubble storage unit

• •

~
4·Mbit bubble s!orage u~it

,
1, The,key to building a 4-Mbyte bubble memory system Is
the ability of the bubble chip's support ICs to simplify the
Interlace with the host. Five such ICs plus a single 4-Mblt
chip (shaded) form the basic memory block. Up to seven
additional blocks In parallel, all governed by one memory
controller chip, complete the system.

, between the bubble and the controller. The host
system therefore need ollly moritor the controller's
status register to determine when it.is busy and to
see if a transfer operation was successful.
The bubble memory controller is the bubble chip's
link to the host. It communicates with,the host over
an 8-bit bidirectional data bus; a single address line
(AD); and a chip-selection, a read and a write control,
,and an interrupt line. In addition, a ninth data bit
line (Ds) ean be used to detect parity errors.
The remaining input and' output lines of the
controller connect the, formatter-sense amplifier,
the'coil predriver,and the current-pulse generator. These components, plus a pair of VMOS drive
transistor chips, make up a 4-Mbit bubble storage
unit (Fig. 1). Up to eight such units may be connected
to a single controller, allowing users to trade off the
number of pages against the individual page size to
fit their, data, transfer requirements.
The controller close, up

To, understand the software and hardware interface with the bubble subsystem requires and
understanding of the controller. An HMOS chip, it
is housed in a 40-pin DIP and divided into 10
functional blocks (Fig. 2).
The host processor operates the bubble memory
system by reading from, or writing to, specific
registers within the bubble memory controller. The
host selects each register by placing an ,address on
'lines Ao and Do through D4• Specifically, the status
iegister and command register are directly addressed using these ,six bits; a third register, the
register address counter, is also directly addressed
and in turn indirectly addresses the remaining registers; including the block-length register, the FIFO
,data buffer, and the enable register. These remaining
registers are called parametric registers because
they, contain the flags and parameters that determine exactly how,the"controller will respond to
commands written in the command register. The
parametric registers are located in a register file and
are selected with addresses 1011 through 1111. In
general, the parametric registers must be. loaded
before commands are issued to the controller.
Parametric registers are loaded when they are
addressed by the register address counter; The controller automatically increments the counter by one
after each data transfer between the host and a
parametric register. Thus there is no need ,to reload
~he address register in the case of multipie,register
reads and' writes.
The address register increments, starting with the
address first loaded, until it reaches binary address
1111. It then wraps around to 0000 and halts until
it is reloaded with another address. However, when
6-218

AR·250

line Ao is zero, all data transfers are with the FIFO.
In addition, any other commands or a controlled stop
sequence will reset the address counter to 0000,
which is the FIFO address.
The most commonly used commands (see the table)
are Initialize, Read Bubble Data, and Write Bubble
.Data. Others used in a typical operation are Read
Seek, Write Seek, Read Formatter-Sense Amp
Status, and Reset FIFO. In addition, two commands
-Zero Access Read Seek and Zero Access Read
Bubble Data-slash, the data access time by a factor
of more than 150. Zero Access Read Bubble Data
returns th~ first byte of data in the FIFO within 50
/lS after the command is sent, provided the address
is known in .advance of the access command.
Parameters first

Commands are written by the host into an 8-bit
write-once command register. Depending on the
command, certain parameters must already be written into their respective registers. For example, the

Initialize command musfbe preceded by the number
of formatter-sense amplifiers ip the block-length
register's first four MSB locations (Fig. 3a). Similarly, before issuing a Read Bubble Data command, the
starting address information must already be set in
the address register (Fig. 3b), as must be the number
of system pages in the block-length register. Thus
each command has its specific set of parametric
requirements that must be estahlished before it is
issued.
If the parametric conditions have been set, the
command is issued using a 5-bit command code. For
example, Initialize is 00001, Read Bubble Data is
00010, and soon.
. Information about any error condition, the completion or termination of a command, or the
controller's readiness is stored in the status register.
The host can directly address this register by setting
the Ao line and examining the eight status flags. The
status register is updated every microsecond. Bits
1 through 6 (Fig. 4a) are set durihg. command
X'
X·

VV·
Timing A

fiininiB
, Bubble
signal
,decoder

Error

Replicata Enable
Boot Loop Enable

. To bubble
memory chip

SwapEl18ble
Boot Loop Swap Enable
Shift Clock

Walt

OetectorOn

ClK

ErrorFI·g~~~::.J~~~~ii~~~~J
" '\ - •

GNO~

Bubble memory

addressing
logic and RAM

OACK ORO INT

2•. The 7224 bubble memory controller Interfaces the bubble storage units with the host
processor. It performatO functions, each represented by a block. The hosUs connacted to
an a-bit data bus with an optional parity bit, a single address line, a chip-selection line, and
Ii read anda write ~ontrol line. Interrupt and DMA handshaking also are available.

6-219

AR-2S0

execution: and are reset when a' new command is
issued. The flags in the status register indicate
whether, the controller is executing a command or
has completed one. In addition, they show whether
an uncorrectable error or a timing error has occurred. Also, using a parity bit, the controller checks
the data the host sends it and generates an odd parity
for the data it sends to the host., Any parity errors
are flagged.
The system page size and the number of pages to
be transferred in response to a single bubble memory

data read or write command are set by the blocklength register, a' 16~bit write-once register. The
system page size is proportional to the number of
bubble storage units operating in parallel during a
data read or write operation. Each bubble chip
requires two formatter-sense amplifier channels,
with bits 4 through 7 specifying the number of such
channels to be accessed. For example, in a 4-Mbyte
system, if bits 7 to 4 areOOOl, two channels will be
accessed,each page will contain 512 bits, and there
will be 65,172 pages. Setting the bits to 0100 specifies
eight charinels,2048 bits per page, and16,384 pages.
The right address

Block-length register lSBs

Block·length register MSBs

I 71s1514 13121, 10I I 71s1514 13 121, 10I

----------

Number of pages to be transferred

Numberof
formatter-sense

amplifier

ch~nnels

(0)
Address register LSBs

, Bubble storage unit selection

I 71s1514 13\2\' 10 I I 7\S\5\4 13 121, \ 0 I
----........--~-----~~-----~

Address'

Starting address within each bubble unit

(b)

3. The parametric registers set the basic conditions for
transfers between the host and the bubble memory system. '
The block.length register gives the number of
formlltter-sense amplifier channels and the number of
system pages In a block (a). The address register gives the
starting address for a read or write command (b).

Status register

1716151413121,101

FIFO Ready
Parity Error
Uncarrectable Error
Correctable Error
Timing Error

Operation Fall
Operation Complete
Busy

(0)

Which bubble memory group is accessed and what
the starting address location is within that group are
determined by the contents of the address register.
Each bubble chip has 8192 address locations for
reading or writing data. Consequently, 13 bits 'are
needed to specify an individual bubble storage unit's
starting address; Which'of the units to be read from
or written to is indicated by address register bits 5
through 7. How the controller interprets these bits
depends on the number of bubble storage units iri
a group as specified by the block-length register. For
example, if the formatter-sense amplifier channels
are numbered 0 through F is and the number of
formatter channel bits of the block-length register
are set at 0000, the address register bits will specify
channels 0 through 7. If, on the other hand, the blocklength register bits are in the sequence 0001, the
address register bits select the formatter-sense
amplifier channel pairs and address register bits
0110 select channels C andD.
The address' range for a 4-Mbytesubsystem is
0000 - FFFF, or 65,172 pages. Selecting address regis",
ter bits 0111 puts the data in the last 8192 pages of
bubble storage.
Enable register controls

Interrupt Enable (Normal)

~---- Interrupt Enable (Error)
'-----~ DMA Enable
~----,"- Reserved

' - - - - - - - - Write Bootloop Enable

' - - - - - - - - _ Enable Read Corrected Data
' - - - - - - - - - - Enable Internally Correct Data
' - - - - - - ' - - - - - Enable Parity Interrupt

(b)

4. The status raglster bits (a) tell the host about any data
errors, the state of the controller's raadlness, or whether a
command was completed properly or not. The register Is
updated every microsecond and Indicates whether a data
error was correctabla or not, In addition to pointing out parity
and timing errors. The enable register bits (b) specify several
conditions, Including Interruption on an error, DMA enabling,
and parity error Interruption.

Certain functions in the formatter-sense
amplifier and the controller are governed by setting
bits in the enable register (Fig. 4b). For example,
setting the Enable Parity Interrupt stops the host
when the controller detects a parity error on the data
bus lines (Do- D7). Also, the controller operates in
a DMA data transfer mode when the DMA Enable
bit is set. In this mode the Data Request and Data
Acknowledge interface signals become'operational;
otherwise, the controller supports interrupt-driven
or polled data transfer modes. As a result, users have
a choice of three' data transfer methods.
The Interrupt Enable (Normal) bit, when set to
a 1, allows the controller to interrupt the host system
when a command is successfully executed. The Interrupt Enable (Error) bit works in conjunction with
6·220

inter

AR-2S0

Bubbles by the block
producing the overall 400% increase, which also means an
average random access time of 40
ms. (A 50-kHz version will be introduced first that has twice the
data rate or'the 1-Mbit chip and
an 80-ms access time.)
Like the technology, the architecture of the 4-Mbit chip is an
enhanced version of the l-Mbit
design. Both use block-swapping
and replicating schemes to write
and read bubbles in parallel, to
ensure nonvolatile storage, and to
permit the use of multiplexed
replication generators to reduce
the number of external pins.
The page length is fixed at 512
bits (64 bytes), but the number of
pages has been quadrupled for the
4-Mbit part. Both chips are organized into identical halves.
Thus, from an architectural
perspective, the higher-density
chip looks like a I-Mbit part with
four times the number of pages
and either twice (50 kHz) or four
times (100 kHz) the data rate.
Actually, the 7114 is divided into
eight octants, each comprising 80
minor loops, and each loop containing 8192 bits (see the figure).
The 7110, in comparison, is split

The basic technology of the 7114
4-Mbit bubble chip-known as
field access, conductor-first permalloy-is the same as used to build
the earlier 7110, a 1-Mbit part,
except for several important refinements. These refinements
quadruple the bit density and the
data transfer rate.
The increased density is produced by halving the period of the
basic memory cell (called an asymmetric propagator) to 5.5 !Lm. The
resultant chip size is 501 by 580
mils (compared with the 1-Mbit's
512 by 614 mils). A 0.75-!Lm
minimum feature size, smaller
than that of any silicon chip, is
being printed now in development
volumes using optical contact lithography. However, X-ray lithography techniques will be used for
production volumes to achieve repeatible results despite the small
minimum-feature size.
In addition, a thin-film detector
was developed that doubles ,the
detected bubble signal compared
with the previous thick-film detectors. This makes doubling the data
rate feasible. Further, doubling
the field rotation rate from 50 to
100 kHz also doubled the data rate,

Even detector

Odd detector

..
Block replicate gale

Loopn umber

'-"

Storage area,
80 loops

into four quadrants, each with 80
minor loops, but each loop contains only 4096 bits. Also, whereas
the 7110 was designed to sense one
bit per side per field rotation, the
7114 senses two bits. In the 50-kHz
4-Mbit part, the longer loops are
compensated for by the two-bitper-rotation sensing.
Like the 1-Mbit device, the 4Mbit chip has redundant loops to
ensure a high yield of devices with
the full 4,194,304 bits of storage
capacity. Redundancy increases
yields and so lowers device cost.
During manufacture, each device
is individually tested and a record
of faulty loop locations is written
and stored in the device's bootstrap loop, known as the "bdot
loop." The boot loop's contents are
used by the 7224 bubble memory
controller during initialization,
reading, and writing to provide a
full 4-Mbit memory space to the
user while keeping redundant
loops invisible. The major-track,
minor-loop architecture used by
both the 7114 and the 7110 to
accomplish the writing, reading,
and nonvolatile storage of data
also maintains the reliability inhererit in bubble technology.

replicate gale

Btock

gate
t

Storage area,
80 loops
6192 bits/loop

Block swap gate
Bubble
generation
5 ite

the data transfer, is complete, the controller reads
the other enable register bits to support three levels
the formatter-sense amplifier's status to determine
of error correction.
At the first level, setting Enable Internally Correct
whether the error was corrected. Otherwise, faulty
Data causes the controller to send a command to a . data could be transferred to the controller and
possibly to the host:
formatter-sense amplifier when an error has been
Lastly, setting the Write Bootloop Enable bit
detected. The formatter-sense amplifier responds
by internally cycling the data through its errorpermits wdting into the bootstrap loop; called here
just the "boot .loop." Normally, the loop should only
correction network. On completion, it sends its status
to the controller, indicating whether or not the error
be read, but under special circumstances a user may
was corrected.
wish to write into it.
For the second level, the Enable Read Corrected
The FIFO as a data buffer
Data bit prompts the controller to issue a command
to the appropriate formatter-sense amplifier when
All data moving between the host and the bubble
an error has been detected. The formatter-sense
units passes through the' 40-byte FIFO buffer. As
amplifier then corrects the error if possible and
a result, the data transfer is asynchronous, with
transfers the corre'cted data to the controller. When
timing constraints relaxed' somewhat for both the
formatter'-sense amplifier and the host system.'
When the controller' is busy executing a command,
the FIFO functions as a data buffer; however,when
the controller is not busy, the FIFO is available to
the host as a general-purpose FIFO register bank.
Actually, a total of 43 bytes of data may be stored
in
the controller: 40 bytes in the FIFO, I byte each·
Write Bubble Data
in its input and output latch, and I byte in the
Read Seek
Read Boot Loop Register
controller's input latch. During execution of a comWrite Boot Loop Register
mand involving a data transfer between the host and
Write Boot Loop
Read Formatter-Sense Amp Status
the formatter-sense amplifiers, the data passes
Abort
through the FIFO and its status is indicated by the
Write Seek
FIFO Ready bit in the storage register.
Read Boot Loop
o
Read Corrected data
The FIFO is addressed automatically after the last
o
Reset FIFO
parametric
register has been written into;
o
Memory Unit Purge
alternatively, the host .can explicitly address the
o
Software Reset
FIFO by writing the address 0000 into the register
Zero Access Read Bubble Data
Zero Access Read Seek
address counter: Also, after' a Write Bubble Data,
a Write Boot-Loop Register, or a Write Boot-Loop
Register Masked command is issued, the controller
delays the data transfer until there are at least two
. More memory in less space
bytes of data in the FIFO. Furthermore, it is the
host system's responsibility to keep up with the data
Instead of a Iead less package requiring a second,
leaded socket,the 7114 4-Mbit bubble chill is housed
transfer during execution oia command; otherwise
in a leaded package that can be placed in a socket
the FIFO could underflow or overflow. If either case
or soldered directly to a PCboard. Like the I-Mbit
occurs, a Timing Error bit is set in the status register.
package, it has 20 pins. However, the distance
between pin .rows· is smaller,. making the footprint
smaller and allowing designers to incorporate more
components onto the board. Also because the
package's height is smaller, boards can be spaced
as close as 0.6 in. to one another. Thus consequently,
either more boards can be accommodated or the
overall system size can be made smaller. As a result,
a 4-Mbyte bubble memory system can be built in
less space than a I-Mbyte bubble system.

A look at data transfer

.The boot-loop register plays a key role in data
transfer both for writirtg and reading. This 160-bit
register contains information detailing the configuration of good. and bad loops in the corresponding
ohannel of each bubble chip.
Each bit of the register corresponds to a minor
loop in the bubble chip. As data passes through the
latter's I/O latches, the contents of the boot-loop
regi~ter are used during reading to remove the bits
corresponding to bad loops and during writing the
contents are used to insert Os in those bit positions
that correspond to bad loops.
6·222

AR-250

Meanwhile, the error-correction block implements
a 14-bit Fire code error-detection and -correction
process. If it has been enabled by the user, the errorcorrection circuitry appends the 14-bit code to the
end of each 256-bit block of data that passes through
the FIFO during a data write operation. When data
is being read, this circuitry checks the data block,
and notifies the controller with an error flag when
an error has been detected.
As stated earlier, a Write Bubble Data command
from the controller to the formatter-sense amplifier
permits data from the controller to be written into
the good loops of the memory unit. If the error
correction is activated, the amplifier automatically
adds the 14 error-correction bits to the end of each
256-bit data block.
Similarly, a Read Bubble Data command enables
the formatter-sense amplifier to read data from the
bubble chip, as was also mentioned previously. This
data is sensed by the sense amplifiers and screened
by'the boot-loop registers so that only data from good
loops is written into the FIFOs. If the error correction
is selected, data. to be read is first buffered. That
is, a full block (270 bits) of data is collected in the
FIFO before any bits are read out. As a result, the

error-correction circuitry detects any errors and
interrupts the controller before any data is sent. If
there are no errors, the 270-bit block is read from
the FIFO and sent to the controller while the next
block is loaded into the FIFO.
In contrast, an Internally Correct Data sequence
forces the formatter-sense amplifier to cycle the
data internally through the error-correction network
without sending any of it to the controller. At the
end of the operation, the amplifier sets a Correctable
or Uncorrectable Error bit in its status register. If
the error is correctable, the controller has the option
of -issuing a Read Corrected Data command. This
command cycles the data through the error-correc"
tion circuitry as it is being read by the cOlitroller.
After all 256 bits have been transferred to the
controller, the formatter-sense amplifier status
register indicates whether the error was found to be
correctable or not. The Read Corrected Data command is used even when the data has been previously
corrected by the Internally Correct Data command. 0
The authors wish to thank Dave Dossetter, Product Marketing Engineer, and Dick Pierce, Marketing
Applications Engineer, for their invaluable assis tance in preparing this article.

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ARTICLE
REPRINT

Reprinted wIth permIssion from Electronics Magazine, March 24. 1983: CopYright McGraw Hlfl, 1983.

6-224

April1983

ORDER NUMBER: 230&42-001

AR-271

New bubble-memory packaging cuts'
board space and manufacturing costs
Low~profile4-Mb

bubble-memory package is interchangeable with 1-Mb types
and also lets printed-circuit boards be spaced on a.6,-in. centers
by Art Thorp, Intel Corp.• Santa Clera.

o Designing a second:generation product gives an engineering team the chance to. put in all the improvements
they realized were needed after the first design was formalized. The new 7114 4-megabit magnetic-bubble memory Jrom Intel makes the most of this opportunity in
terms of its ease of both use and manufacturing.
Despite the quadrupled bit density, the 7114's leaded
package is smaller in all three dimensions than the leadless package of its loMb predecessor, the 7110. It occupies less space on a ,printed-circuit board and has a lower
profile-low enough for the boards carrying it to fit into
adjacent rather than alternate slots in standard card
cages. Moreover, chip and package are far easier and
cheaper to assemble.
Nor, is that convenience compromised by a lack of
compatibility with the 711 O. The pinouts are the same,
and the pin spacings sufficiently similar to make it simple
to upgrade from the 7110 to 7114. Also, the support
circuits essential to the control of each bubble memory

Calif.

are either identical or so alike as to be interchangeable.
More specifically, the first-generation 1-Mb bubble device is a 520-by-620-mil chip in a leadless package that
needs a socket; the assemblage has a footprint of 2_20 by
1.825 in. (Fig. 1) and an overall height of 0.430 in.
In contrast, the 4-Mb chip and a, forthcoming 1-Mb
device are smaller-580 by 500 mils-and their leaded
"thin-C" dual in-line package has a footprint of only 1.66
by 1.46 in. (Fig. 2). Also, its height is now only 0.375 in.,
so that when inserted either directly into a pc board or in
a zero-profile socket, it leaves ample clearimce for the
0.6-in. card spacing normal in commercial card cages.

Design goals
Without scaling down device geometries, it would have
been impossible to fit a garnet chip containing four times
as many, bubble domains into a package of the same size,
let alone a smaller one. Thus the first order of business
was at least to halve device geometries in both dimen-

1. Leadlesa. The lead less package of this first-generation I-megabit
magnetic-bubble memory has a footprint of 2.20 by 1.825 inches and
an overall height of 0.430 in. when socketed. Thus boards cannot be
spaced the standard 0.6 in. apart.

2. Thin and leaded. Despite its 4-Mb capacity. this bubble chip fits in a
leaded package with only a 1.66-by-l.46 in. footprint and 0.375-in.
profile. Cards carrying these packages or using zero.profile sockets
for them can be set into a card cage with the standard 0.6-in. spacing.

6-225

Electronics/ March 24, 1983

intJ

AR·271

sions. The production application of X-ray lithography,
in fact, yields 4-Mb bubble chips that are smaller than
the I-Mb one in the current 7110 leadless package.
In addition to different die dimensions" the smaller
package required smaller magnets and coils with different dimensions to help control the flow of magnetic
bubbles on the garnet chip. A program for designing
models of coil size and shape was therefore developed
and run on an IBM Personal Computer.
Either the 1- or. 4-Mb scaled-down bubble device could
have been placed in the same package 'as the original 1Mb memory if that had been desired. Instead, it was
decided not to settle for the existing package but to
produce a new one that, while compatible with the 7110,
would be more useful to the engineer-namely, by being
smaller and allowing standard pc board spacing. Equally
important, if not more so, was the decision to make the
production process more efficient and cost-effective.
, Nevertheless, there were to be no compromises in the
stiff specifications for durability, magnetic shielding, and
temperature range. In. essence, the design 'goal was. for
the new. package to be at least as· good as' the first in
some aspects· and better.in others. '

A.thinsy
One major concern in moving to a new package is its
effect on users who are already producing systems containing the first-generation version and who plan to continue manufacturing while introducing the later one. Unless pinout and spacings, are absolutely identical, the
transition toa new package cannot be totally painless.
However, in this case, maintaining the identical spacings both within and between the two rows of pins would
eliminate any benefit gained by a .smaller package. Thus,
the decision was.to keep the 7114's pinout and adjacent
pin spacings the same as on the leadless 7110 package.
Only the separation between the two rows of pins has
been made smaller on the new memories.
As a result those engineers now manufacturing equipment using the previous 7110 model can layout their pc
boards in such a manner as to accommodate either the
first-generation package or, with a minimal amount of
revision, the new one. The trick is to elongate and drill
the pin trace pads on the board for two holes per pin, as
shown in Fig 3. For new layouts, this scheme should be
used from the very start. Existing system boards can be
modified this way with little effort. If board-level diagnostic and, maintenance operations require the use of
sockets for the packages, the pc-board holes should be
dimensioned for the zero-profile-socket contacts, such as
Augat Holtite types. Otherwise, the advantage of the 0.6,in. board spacing will be, lost.

Attacking manufacturing costs
In many ways, making magnetic-bubble chips is similar to making integrated circuits, but there are significant
differences-for instance, semiconductors do not need
wire coils. Therefore, it is reasonable to assume that the
major manufacturing cost factors in the one process will
not be the same for the other.
In the original 7110, the garnet bubble chip is first diebonded to a ceramic substrate and then wire-bonded to
Electronics/March 24, 1983

conductors metalized onto the ceramic. Next, the field
and drive coils are put in place around the gamet chip,
and all the' components are potted using a liquid epoxy,
compound. Both the use of ceramic and.. the potting
process contribute heavily to memory cost.
The 7114 package design is more economical on both
counts. For the ceramic substrate, the design team substituted a special pc-board material that is thinner, lighter
in weight, and lower-cost.
Next, the designers tackled the problem of potting the
chip, substrate, and coil combination. Packages containing les often employ transfer molding of a thermoset
epoxy compound. Bu( when applied to the bubble assembly, the high pressures involved in this process-about
500 to 1,000 pounds per square inch-routinely deformed the bubble memory's wire coils and degraded
their electrical performance unacceptably.
Indeed, for the 7110, manual potting had seemed unavoidable, even though production personnel spent. an
average of 1 houron each bubble assemblage, first placing it in a mold, then pouring in liquid epoxy, placing it
in a high-temperature oven to cure, removing the mold
from the oven, and' finally extracting the assembly,
Nonetheless, for the 7114 a fast alternative was found
in the liquid injection-molding process used by some
manufacturers for high-voltage insulators. Unlike transfer
molding, it employs only low pressure" in the region of
15 psi, and it speeds up the potting process to more than
50 devices per hour.
Thus by replacing the ceramic substrate with pc-board
material and by substituting liquid injection molding for
the manual pouring of a potting compound, the package'
engineering team had a very, favorable impact on the cost
and throughput of manufacturing. An added advantage
is that, with the ceramic removed, the possibility of chip-

UNPLATED
HOLE

3. Four for one.lfthis pc board layout is followed, it is possible to plug
either a socketed 7110, a leaded 4-Mb, ora leaded 1-Mb bubblememory package into this hole pattern,The socketed 7110 goes into
the outer set of holes, while the newer packages fit the inner set

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inter

AR-271

Those support ICS that have been designed in conjunction with the new memory are the same size and have
the same pinouts as their counterparts in the 7110 loMb
subsystems. What has changed is some of the program" 4. UPlnlde.Along with the bubble chip.all the other les olthe 1: and mable parameters and the descriptions of their associated
4-Mb memory systems are mechanically and electrically interchange· registers. These are ljll involved with the new bubbleable so far as the pc board layout is concerned. The diagram shows memory controller chip---the IC that interfaces the micropr9cessor bus with the 4-Mb memory.
the chip set for a 4·Mb system in color and the 1·Mb system in black.
Examining the effect of these changes in upgrading
ping the exposed edges has been reduced. The table on from a 7110 I-Mb to a 7114 4-Mb package reveals that
this page summarizes the packaging and manufacturing the modifications are really minimal-the new support
ics can be designed into the same board layouts as their
aspects of the new and old bubble package methods.
There is always the danger that improving one aspect loMb cousins. Users will have only to make some modifi-,
of a product may inadvertently degrade another. In this cations in their software to handle minor, differences in
case, however, that has not been the result. For example, addressing and configuration initialization.
the original 7110 package was designed to offer protecIntel's bubble-memory system therefore can have the
tion from' external magnetic fields to a level of 20 oere same configuration whether working with I-Mb or 40Mb
steds. Furthermore, the 7110 is specified to operate over devices. A single bubble-memory controller acts as the
interface between the microprocssor bus and one or more
a standard temperature range of 0' to 7S'C.
, In each case, the new package offers the same or better bubble storage subsystems.
specifications than the leadless,package. In terms of meThe 7224 controller for the 4-Mb bubble-memory dechanical reliability, both the leadless and leaded ,package vice is housed in a standard 4O-pin; dual in-line package
meet and el\ceed all vibration and shock test limitsspeci- and takes up about 2 by 0.5 in. on a board. A single
fied in MIL-STD-883. The leaded package precludes controller operates up to eight storage subsystems for a
many mechanical problems since it does riot depend on a ' 'maximum capacity of 4 megaBytes.
Each bubble-memory subsystem contains a monolithic
, leadless package, socket for in~erfacing with the board.
One for one
formatter and sense amplifier in a standard 20-pin DIP; a
current-pulse-generator chip in a 22-pin DIP; a coil-preThe original loMb bubble memory was developed driver chip in a 16-pin DIP; a pair of quad v-groove MOS.
along with a set of support ICS that handled all of its driver chips, each in a 14-pin DIP; and of course the
, complex timing and drive functions and made its inter-bubble device itself. One subsystem takes up less than 3
face with a microprocessor bus indistinguishable from by 4 in., and a 4-megabyte board of eight of them plus a
that of any bona fide peripheral semiconductor. Consid- a, controller could be constrained to 6.75 by 12 in.
erable engineering effort was applied to'make these supObviously, boards laid out for the 7110 lcMb memory
port circuits interchangeable.
' a n d its, support family would be approximately the same
Consequently, any support chip works with any bubble size for one fourth the amount of memory. However, in a
, memory. This is in marked contrast to otherwise similar card cage with a standard,O.6-in. spacing, boards built
devices that need matched sets of support components.
using the original leadless packages could not be stacked
Intel's 7114 4-Mb device uses the same architecture as in adjacent slots .
. the 7110, but now has eight identical sections (called
Converting from the earlier 7110 loMb to a 40Mb sysoctants) instead of four, and each' section is enlarged to tem essentially requires modifications to the pin pads of
store double the number of bubbles it does in the current the 7110's leadless package. The 7220-1 bubble-memory
7110. The result is a fourfold increase in capacity. How- controller is the same size and has the same pinout as the
ever, all of the same pins are brought out in the same . 7224. The same is true for the 7242 formatter and sense
order on both bubble memories. Thus the pinout is ideil- I amplifier and its 7244 replacement, as well as for the
tical and allows for the use of the same new package for 7230 current-pulse generator and its 7234 substitute. Figboth the new I-Mband 40Mb devices.
' u r e 4 shows how an identical board can support either a
Those support ICS that are not affected by the in- 7114 4-Mb or a leaded or leadless 7110 loMb system.
Space limitations, interface details, and other such cricreased capacity; such as the coil predriver (7250) and
drivers (7254), are used with either memory.
' teria will typically dictate the actual board layout.
0

6·227

Electronics/March 24, 1983

ARTICLE
REPRINT

AR-272

April 1983 .

Reprinted with permission from EON, Volume 20, No.7. Copyright Cahners Publishing Company, 1983.

6-228

APRil 1983
ORDER NUMBER, '30645-001

AR-272

Bubble-memory support chips
allow tailored-system design
Using special support chips gives you flexibility in designing a
bubble-memory system. And understanding design tradeoffs
helps configure a system that best suits your needs.

Richard Pierce, Intel Corp

Designing a bubble-memory system-with its advantages of small size, high reliability and nonvolatility-is
easy when you use system support devices. Such a
family of LSI chips allows you to tailor a system to meet
requirements on specs such as access time and power
consumption and to modularly expand the system for
increased storage capacity. How you configure and use
a bubble-memory system involves tradeoffs, though,
and balancing those tradeoffs requires knowledge of the
intended system application. This article. discusses
bubble-system tradeoffs and other design considerations and presents a specific design using Ip.tel's 1M-bit
bubble-memory device and family of support chips.

its way to the 7242 formatter/sense amplifier (FSA).
This FIFO's primary purpose is to reconcile timing
differences between the user and the FSA, because the
system bus typically can transfer, data much more
rapidly than the bubble memory can.
The BMC's DMA and interrupt logic handle data
transfers. In addition, an internal register file contains
six user-accessible 8-bit registers: a command register,
a status register and four registers that store information pertaining to the system's operational mode and
configuration. The command register accepts userissued codes that initiate data transfers, and the status
register indicates the BMC's current state.
The remaining functional sections of the BMC

Interface appears as a peripheral controller
The devices available for building a 1M-bit bubblememory system are the 7110 magnetic-bubble module,
the 7220-1 bubble-memory controller, the 7242 formatter/sense amplifier, the 7230 current-pulse generator
and the 7250 coil predriver (see box, "Bubble-memory
devices"). Communication with the 7220-1 controller
(Fig 1) is the key function; because this device provides
the bubble memory's only interface with the outside
world. It allows you to interface with a bubble-memory
system through a standard I'-P bus just as with any
peripheral. Software directs the controller to choose
one of three memory-access methods: direct memory
access (DMA), interrupt or poll.
The 7220~1 bubble-memory controller (BMC) has
several functional sections. The system-bus interface
provides an asynchronous interface to a host processor,
transferring 12.5k bytes/sec with a 4-MHz system
clock. The controller also has a 40-byte first-in first-out
(FIFO) memory buffer through which data passes on

6-229

DACK:::=E§::J
DRO
INT

Fig 1-A bubble-memory controller, which interfaces to a
host JLP through a system bus, generates aI/ support-circuit
timing and control signals, maintains memory-address
information and performs data conversions for transfers to a
bubble-memory module.

· AR-272

Communicate with a bubble memory
as with a peripheral controller

generate all the support-circuit timing and control
signals, maintain memory-address information and
perform parallel-to-serial and serial-to-parallel conversions for transfers to the bubble-memory module.
Interface circuitry depends on transfer mode

The type of circuitry you design to interface with the
BMC depends on the mode of data transfer chosen. For
a polled implementation, the requirements reduce to
interfacing to a standard ,...p bus. One such interface
design, for the 8088, appears in Fig 2; it consists of
address-decode logic, data-bus-decode and buffering
logic, a clock circuit and miscellaneous control logic.
The clock circuit must provide a 4-MHz (±O.1%) system

clock with a 50% (±5%) duty cycle.
Fig 2's system operates from 12 and 5V only, and one
important part of this design is its automatic power-fail
circuitry (Fig 3), which monitors these voltages. An
important aspect of bubble-memory devices is that the
coil drive current (which moves bubbles around within
the device) must always have the proper phase and
amplitude, without transients, to ensure data integrity .. Fig 3's powor-fail circuit prevents transients
and-when voltages drop 6% below normal level-stops
the coil currents while maintaining the proper phase.
You can also expand the power-fail circuit to include
recommended features such as acpower-fail and ac or
dc overvoltage protection.

Bubble-memory devices
Several different devices (figure)
make up a bubble-memory system. At the heart of the system is
the 7110 magnetic-bubble memory (MBM), with a user data capacity of 1M bits (128k bytes).
This chip embodies a majortrack/minor-loop architecture, in
which bubbles serially propagate
into and out of the memory tracks
and get stored in minor (storage)
loops (EDN, September 1, 1982,
pg 198). This organization permits
creation of redundant storage
loops, increasing device yield by
tolerating defects in as many as
15% of the loops. Testing by the
manufacturer detects .the unusable loops and writes a marr-showing the usable loops-into
an additional storage loop called a
boot loop. The map also appears
on the 711 O's label.
Internally, the 7110 consists of
two identical 512k-bit sections.
Although these sections are essentially independent, they operate simultaneously to give a factor-of-two data-rate improvement.
User interface to· the system
occurs through a 7220-1 bubblememory controller (BMC). This
device provides the system-bus
interface, performs serial-toparallel and parallel-to-serial data
conversions, generates all timing

and control Signals necessary for
proper operation of support circuitry and interprets and executes
user requests for data transfers.
The BMC's interface makes the
bybble-memory system look like a
peripheral to a ,...P-systembus.
The 7242 formatter/sense amplifier (FSA) interfaces independently to each half of the bubble
memory. Its integrated sense am'
plifier accepts low-level voltage
signals from the MBM'sbubble
detectors during read operations,
and the device also performs
data-formatting tasks that include
the transparent handling of the
MBM's redundant loops. In addition, the FSA sends TTL-level
control.signals to the 7230 cur-

rent-pulse generator (CPG)during
write operations.
The 7230 supplies the current
pulses that generate bubbles in
the MBM and transfer them into
and out of the storage loops. The
CPG's integrated power-faildetection circuitry initiates an orderly shuidown .of the current
sources when power fails.
The 7520 coil predriver (CPD)·
interfaces the 7220-1 BMC to the
two 7254 drive transistors, which
supply. the relatively high peak
currents required Iby the 7110
MBM's X and Y coils. These
currents induce the in-plane rotating magnetic field that moves the
magnetic bubbles.

7250
COIL PREDAIVEA

Support chips allow the design of a complete bubble·memory system around Intel's
7110 magnetic·bubble memory device.

An
A"
A,
A,
AD,
AD,
AD,
AD.
AD,
AD,
AD,
AD,

BUBBlE·MEMORY
CONTROllER

'-- A,

Ali

' - - A,

' - - - A,
' - - A.
A,

O~H
Dio DO,
01,
DO, f01,
00.
DO,
0.1,
01. !Xl.
01,
DO,
01,
DO,

,.. .... f--D{~~ER
B205

FIg 2-1nterfaclng a bubble memory can be almost as simple as interfacing a standard jJl' bus. This interface connects a 7220-1
bUbble-memory controller with an 8088 jJl'.

Guaranteeing pOwer-supply requirements is an im- . requirement is
~ _ aIMAxaTMAx
portant part of the design process. The supply voltages
VMtN aVMtN
must be within 5% of their specified values, and the
. power-offlpower-fail decay rates (Table I) must allow Typical capacitance vallies for a system with one
150 (.Lsec max for an orderly shutdown and reset of all bubble-memory module, excluding any additional cure
support circuits; No restrictions apply to voltage rise rent drain from unrelated circuitry, are 805 and 350 (.LF
for the 5 and 12V supplies, respectively.
.
times or sequencing.
Another important design factor in custom bubbleA simple calculation determines your system's required storage capacitance to achieve Table I's voltage memory boards is careful circuit· layout to minimize
decay rates_ The worst-case power-supply capacitance interference from the 7110's large drive signals with

6-231

intJ

AR·272

Choose a memory-access method:
.
direct, interrupt or poll
nearby small sense signals. The pin assignments ofthe
7110 and its support devices optimize board layout and
maximize circuit density, and the package layout used
.in Intel's Bubble PrototyPe Kit\(BPK"72) helps ensure
error-free operation. As shown in Fig 4, this layout .
places all support circuits near the 7ilO; note particu. larly that the' 7110 and the 7242 FSA must not be
physically separated.
Software controls the system

Software is a vital part of bubble-memory design,
too; it's the major contributor to a system's efficient and
reliable operation. Software interface modules (often
called bubble drivers) accept processor"isstied commands and control and monitor command execution;
they also return 'status information' to the processor.
Software drivers depend on the mode of data
transfer: interrupt-driven I/O, DMA or polled. In '3'
DMA implementatiQn, the software' need only set up
the DMA controller's. memory-address and transfer
coUnts and initiate the data transfer; Intel's 8257
DMA-controller hardware automatically handshakes
with the fJ.P and BMC to perform each transfer.
In the interrupt mode, on 'the. other hand, the
software is responsible for performing memory-read
, and-writ~ operations to' transfer 22-byte data blocks to
and from the BMC's FIFO on receipt of an interrupt. A
, BMC output signal-typically wired as a second-level
interrupt-indicates when the BMC's FIFo' becomes
half full (during read operations) or half empty (during
write operations).
The third 1/0 method-pOlling-is similar' to the

Fig 4-Pro"er' component layout helPS. ensure error-ft'se bllbblememory operation: In this Intel Bubble Prototype KIt (BPK-72). all
suPPqrt circuit~ at's 'close to the 711 0 me~rymodule.

TABLE 1 , ,BUBBLE·MEMORY .
POWER·SUPPL Y REQUIREMENTS
,VOLTAGE
12V
5V

POWER·OFF/POWER.FAIL
DECAY RATE'
< 1.10 V/mSEC
< 0.45 VlmSEC

MARGIN
+5%
±5'10

interrupt-driven mode except that in it, data moves one
byte at a time. The software determines when to
. transfer data by continually polling a bit in the BMC's
status register. This status bit indicates the presence ,or

~~2~1_·__t-__~IN~9_'4__~3N·9Vk~____. -____~____~____~~
7230
CURRENT.P,ULSE
GENERATOR

7220·1
BUBBLE·MEMORY
CONTRO'LLER . 2

5.1k

RmE'f.l5IJTt=-1,,-,MI'--O 5v

t-----~~------~~--~--~---1----~~
SYSTEM
RESET

lN914

.. 5:6k

Fig 3-Power-fall circuitry monitors the 12 and 5V supplies for Fig 2's circuit and mainteins data integrity in case of power failure by
.
stopping coil currents in the proper phase.

6-232

AR·272

REGISTER
NAME
UTILITY REGISTER
BLOCK·LENGTH·REGISTER LSB
SLOCK·LENGTH REGISTER MSS
ENABLE REGISTER
ADDRESS·REGISTER LSB
ADDRESS-REGISTER MSB
FIFODATABUFFER

fig 5-&lltware accassea the bubble-memory controller through a system-bus interface consisting of two I/O ports. A ONE on
address tine Ao selects the command/status port, and a ZERO selects the bidirectional data port.

registers or the BMC's FIFO if D, is ZERO .. In the
latter case, the contents of a register-address' counter
(RAC) specify one of the seven possibilities.
The command register accepts one of 16 interface
commands. The initiation of nondata transfers occurs
merely by writing the proper command code to the
command register, while a data transfer (initialize or
read/write) requires prior loading of the' parametric
registers. Those registers specify the operating mode
and system configuration, plus ·the data transfer's
starting address andJength (in 64-byte pages). After
loading of the command register, the BMC automatically executes the command. An indication of success
'
or failure returns in the status register:
An autoincrementing feature in the RACfacilitates
loading the parametric registers before data-transfer
commands. Aft~r the processor loads a value--,specify"
ing a particular parametric register-into the RAC via
the command port, the next write' operation to the data
Understand protocols and definitions
port accesses that register. Each write operation also
Developing the software drivers for any bubble- increments the RAC, so each' subsequent operation
memory system requires a clear understanding of accesses the next register in sequence. After increcommand protocols and register definitions. The soft- menting to address 0 (the BMC's FIFO), 'however, the
ware communicates with the bubble-memory controller RAC stops incrementing and continues to point to the
through the system-bus interface, (!onsisting of two liD FIFO until modified by software.
ports selected by the state of the least significant
address line (Fig 5). When ~ is ONE (active), the Software drivers perform data transfers
command/status port gets selected; when it's ZERO
An example set of BMC software drivers (Fig 6)
shows how data-transfer operations occur in the polled
(inactive), the bidirectional data port gets selected.
The command/status port serves a dtial function; mode. The three drivers perform a power-up proceReading the port. accesses the status register, and dure, write registers, and read and write data .
The power~up procedure (Fig 6a) .enables bubble.writing to thll port accesses a register deterrnfued in
part by data bit D4.~This register is the command memory support devices in an orderly faShion and
register if D, is ONE; it's one of the six parametric permits subsequent reading 'and writing of memory
absence of data-to be read or written by the host
processor-in the BMC's FIFO.
.
Although the polling mode is simple to implement, its
software requirements are the most demanding. Because data transfers one byte at a time,' the software
must continually monitor the status register to ensure
that the FIFO doesn't underflow or overflow with' data.
Each of these data-transfer modes' has unique
advantages that must be weighed with each particular
application. The DMA mode, 'for example, permits the
processor to continue executing instructions while' a
transfer is in progress. The interrupt and polled modes,
on the other hand, offer lower ~stbut are often too'
slow in systems incorporating mUltiple bubble devices
connected in parallel. Eight 7110 bubble modules in
parallel can transfer data at rates as high as lOOk
bytes/sec, and these high-performance systems normally use the DMA mode.

6·233

AR-272

Meet power-supply requirements
. to ensure reliable. operation
pages. The first command it issues is Abort; the host
then loads the. parametric registers with appropriate
values for a 1M-bit system configuration and issues an
Initialize command. During command execution, the
host processor constantly polls the BMC's status
register to determine when the command finishes. An
additional status-register check detennines whether
the command and/or data transfer is successful.
Successful completion of the Initialize command

(b)

(e) .

, PATA READlWRIT£ IIOllTlHE

SEND REGISTER ADDRESS
SEND REGISTER VALUES
ISSUE INITIALIZE COMMAND

Fig &-Bubble-memory software drivers perform powerup (a), write registers (b) and read and write data (c).

6-234

AR-272

Proper physical layout
helps reduce errors
indicates that the system is ready to transfer data. To
initiate a data transfer, the host loads the parametric
registers (Fig 6b) with the memory-page address and
number of pages to transfer and then issues a read or
write command (Fig 6c). This command transfers data
between the system bus and the BMC's FIFO at a rate
of 80 fLsec!byte, excluding access time. The software
polls the status register to determine when to transfer
each byte and also maintains a count of the bytes
transferred. In systems operating in the DMA or
interrupt mode, however, maintaining this count is
unnecessary.
Of course, all software driver routines should contain
error-handling capabilities, but the examples shown
here ignore these capabilities for the sake of simplicity.
Numerous error-correction options exist in a bubblememory system, though, and all are selectable under
I software control. As an example, the 7242 formatterl
sense amplifier uses a 14-bit error-correction code with
each 256-bit block of data. This code can correct all
single-error bursts of five bits or less, improving the
data error rate by several orders of magnitude while
remaining user transparent.
Expand memory in modules

Having considered a bUbble-memorycsystem design,
turn to memory-expansion considerations. One BMC

can control as many as eight bubble-memory modules,
and with multiple BMCs, you can configure even larger
systems (Fig 7). A memory modul~providing expansion in increments of 128k bytes--consists of a 7110
bubble device, one 7230 current-pulse generator, one
7250 coil predriver, a 7242 formatterlsense amplifier
and two 7254 drive-transistor packages..
Expansion can occur in three ways. The first
approach uses the BMC's built-in ability to handle
multiple bubble devices. This scheme relies on the BMC
to time-slice the serial bus between the BMC and the
appropriate number of 7242 FSAs in the system and to
output appropriate control signals to the 7242, the 7230
and the 7250. Data flow in this expanded system is
similar to that in a single-module system.
A second expansion 'approach takes advantage of
provisions in the BMC for paralleling controllers. This
approach provides a greater word width at the system
bus and still allows each BMC to accommodate as many
as eight bubble devices.
A third option switches banks of bubble devices into
or out of a circuit under external control. (Switching is
possible because each support device has a chip-select
pin.) The. maximum number of devices in each bank
remains eight, but the number of banks is unlimited.
You can even multiplex entire SUbsystems of this type,
because the BMC chip itself has a chip-select input.
Nonvolatility permHs power savings

Your design of a bubble-memory system can also take
into account the system's nonvolatility in order to
minimize power consumption. Consider, for example, a
bubble system for a portable terminal that stores
inventory and sales figures and periodically transmits
them to a central computer. The bubble memory in such
a terminal requires power only during memory access,
so you can' remove power from the bubble system
during much of the time that the terminal is in use.
In some applications-forexample, systems that only
occasionally transmit a small amount of data-you can
also reduce power consumption by using a faster
initialization scheme. The usual initialization procedure, which reads boot-loop information from a bubble
device to identify redundant st.orage loops, requires as
much as 160 msec per devic~ significant percentage
of power-on time for such systems. If you store the
boot-loop information in EPROM, though, you can
download it from there much more rapidly and thus
with less power.
Design tradeoffs occur at system level
Fig 7-Bubble-memory expansion occurs in increments.
Each 7220-1 controller can handle as many as eight.
12Bk-byte modules.

Still other design considerations exist at the system
level; design tradeoffs concern such factors as memory
capacity, access time, data rate and power consump6-235

AR·272

Software interface modules
contribute to system efficiency

TABLE 2 ~
BUBBLE·MEMORY
PERFORMANCE PARAMETERS
ONEMBM

CAPACITY

FOUR MBMs

EIGHT MBMs
OPERATED IN

DATA
RATE
AVERAGE
ACCESS
TIME

POWER
DISSIPATION
(100% DUTY
FACTOR)

tion. As Table 2 shows, the 7110 bubble module's access '
time averages 48 msec (7.4 msecbest case, 80 msec
worst case), independent of the number of modules in a
system. You can increase the data rate, however, by
operating the devices in parallel. The approach requires
more power, but using eight 7110s instead of one
increases the nominal bit rate from 68 to 544 kHz.
Finally, you can' improve the overall data rate by
reducing the average time required to access a memory
page. The' access, time for any, single page, is random,
but no access delay occurs for succeeding pages. Thus,
in thue-critical applications where successive page
accesses 'aren't random, least recently used (LRU) and
lookahead algorithms can help reduce page-access
EDfi
time.

Author's biography
Richard Pierce works in
Intel's Nonvolatile Memory Div
(Santa Clara, CAl, supplying
customer support and developing new: applications. He
holds a BSEE degree from
Purdue University and previ·
ously worked for ,CinciAnati
Electronics. Dick is a member
of the IEEE, and his hobbies
include. biking, photography
and skiing.

BPK 5V74
4MBIT BUBBLE MEMORY SUBSYSTEM

~__B_P_K_5_V_74_-_4__~___1_0_0C__T_O_5_5_0C__~1
•
•

4 Mbit (512K Bytes) Non-Volatile,
Solid-state, ReadlWrite Bubble Memory
Subsystem
Interfaces to Host Microprocessor
Via Additional Bubble Memory
Controller

Bubble Memory and ICs for
• Contains
Production with4Mbit Bubble Memory
Provides Expansion Up to
• Modularity
Eight Subsystems
Controller .
P~r

•

Maximum Data Rate of 200K bit/sec
with One Subsystem

Maximum Data Rille of 1_6M bit/sec
• with
Eight Subsystems in Parallel
and Time Multip~xed
I!!I

Average Random Access Time of 88 ms

•

Bubble Memory in Leaded Package

The BPK 5V74 Bubble Memory Subsystem is a modular building block used to design bubble memory
systems. In a complete bubble memory system; an 7224 Bubble Memory Controller (BMC) interfaces the
BPK 5V74 subsystem to the host processor.
.

The modular Intel subsystem provides a path for density expansion. One BMC.can interface up to eight
4 Mbit subsystems. Thus, a 4 MBit (512 KByte) system can be expanded up to a 32 MBit system by adding subsystems. BMC's can be combined i~ parallel to further expand the system memorY capacity.
Together, the BPK 5V74 Bubble Storage Subsystem and a 7224 controller provide a reliable mass
storage system 10r any application. This bubble memory sy~tem can be c!lstomized to the particular
layouland f~rni factor of many dIfferent systems.
..

....

IU'lll
M(MO'"
CONTROLLE,.
• (aMe)

'O::~:~~:AL

Figure 1. Block Dlagran:' of a" 51~K .Byte Bubble Storage System

Intel Corporation Assumes No Responsibility for the Use of Any Circuitry Other Thari Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied.
.
..
© INTEL CORPORATION
OCTOBER 1983
ORDER NO. 210804-002

inter

BPK 5V74

FUNCTIONAL DESCRIPTION'

Data integrity is insured by the automatic error
correction designed into the BPK 5V74.

An BPK 5V74 subsystem and a 7224 controller
comprise a complete bubble memory system.
The 4 MBit BMC, the 7224, provides the interface
between the host microprocessor and the bubble memory subsystem and provides all the timing and control signals to the subsystem. The
user interface of the BMC is compatible with
microprocessor bus systems for 8080, 8085,
8086, 8088, 80186, 80286 and other standar.d
microprocessors. The BMC is a software driven
device utilizing 18 convenient commands. The
design engineer's primary responsibility is interfacing to the BMC. This is comparable to interfacing a disk drive controller.

The average random access time of a 4 MBit subsystem is 88 ms with a 200Kbit/sec maximum
data transfer rate. Operating several subsystems
in parallel, the BMC uses time division multiplexing. Therefore, the maximum data rate increases
correspondingly for the whole system.

The BPK 5V74 consists of one 4 MBit Magnetic
Bubble Memory (MBM) .and additional support
IC's (see Figure 1). These are the basic components to build a non-volatile, solid-state,
read/write military memory system utilizing 4
MBit bubble memory. The bubble memory is in a
leaded package. The complete family of LSI support circuits has been designed to handle the
complex analog interface associated with bubble devices. The immediate support circuitry for
the MBM consists of - an 7250 Coil Predriver
(CPO), eight 7264 MOS FETs Transistor Packs,
an 7234 Current Pulse Generator (CPG), and an
7244 Formatter/Sense Amplifier (FSA).

The data in the 4 Mbit subsystem is organized in
8192 pages, each wi1h 64 bytes. Conceptually,
the data organization with pages is analogous to
a disk system's sectors. In system's with multiple bubble memories, the page size can vary
from 64 bytes to 512 bytes depe.nding on the
number of subsystems and if the subsystems
are operating in parallel or serially, being accessed one at a time.

Operating subsystems serially, one MBM being
accessed at a time, the maximum qata transfer
rate is still 200Kbitisec. If low power consumption is a critical design goal, the bubble memory
subsystem can be powered down when it is not
being accessed, thus reducing the average
power consumption. '

The BPK 5V74 subsystem has matched components. Each of the components in the subsystem is described in moredetaiJ in the rest of
this data sheet.

BPK 5V74 FUNCTIONAL DESCRIPTION
Item

Description

Part Number

4 MBit Bubble Memory

20-pin leaded package which provides 4 megabit of nonvolatile storage.

7114

Current Pulse Generator

Converts digital timing signals to analog current pulses
suited to the drive requirements of the MBM. The CPG provides the replicate, swap', generate, boot replicate, and
bootswap pulses required by the MBM .. 22 Pin DIP
Package.

7234

Dual Formatter/Sense Amp

Provides direct interface to the Bubble Memory. The FSA
contains on-chip sense amplifiers, a: full FIFO data block
buffer, burst error detection and correction circuits, and
circuitry for handling of the bubble memory redundant
loops. 20 Pin DIP package.

7244

Coil Predriver.

Provides the high voltage, high current outputs to drive the
Quad VMOS transistors. 16 Pin DIP package.

7250

VMOS Coil Drive
Transistors (8)

Switches the required current to drive the X and Y coils of
the Bubble Memory. 3 Pin Discrete.

7264

For additional packaging information see the packaging information section.
6·238

""B-->T + l .."
(WX) DETAIL A

------------------------------SIDE VIEW

Figure 2. 4MBit Leaded Bubble Memory Package

BPK 5V74 TEMPERATURE RANGE
Bubble Memory
Temperature Ranges
Operating
10' to 55'C Case

Non·Volatile Storage
- 20 to

Support Circuits Min.
Operating Temperature

, Description
4 Mbit Bubble Storage
Sub-System

Data Orgallization
64 bytes per page
8192 pages per BPK 5V74

Capacity

Addressing Scheme

512K Byte per BPK 5V74
Maximum of 8 BPK 5V74 per 7224
Controller

Logical page number

Environmental
Performance
Avg. Access Time ................... 88 msec

Temperature: See Ordering Information
Operating Humidity: 0-95% Non-Condensing

6-239

BPK 5V74

OATATRANSFER RATES (Examples of System Configurations)

Parameter

One BPK 5V74
Unit

Four BPK 5V74
Operated in
Parallel 1

Eight BPK 5V74 Eight BPK 5V74
Operated in
Multiplexed
Parallel 1
One at a Time1

Average Data Rate (kilobits/sec)

Maximum Date Rate (kilobits/sec) (Burst)

NOTE:
. 1. Multiple Bubble subsystemscan be operated in parallel for maximum performance or multiplexed to conserve power.

• Voltage sequencing - no restrictions
• Power on voltage rate of rise - no restrictions.
• The power supply requirements based on rec,
om mended power fail circuitry as shown' in
Figure 3.
.
• The12V± 1 % may be supplied by:
1. Using such power supply.
2. Use voltage regulator with 5V ± 5% input
and 12V± 1% output as used in BPK 5V75
prototype kit. Circuitry ,.- See Figure 4.

BPK 5V74 POWER SUPPLY REQUIREMENTS
Margin

Power Off/Power Fail
Decay Rate

+ 12 Volt

±1%

less than 1.10 volts/msec

+5 Volt

±5%

less than 0.45 volts/msec

Voltage

BPK 5V74 POWER CONSUMPTION
(Includes 7114, 7234, 7244, 7250; 7264)
,Standby

3.7W
6.2W
+5V
Rl
lK .

POWER.
,

POWER.

FAIU I-~-"""'-Dl-~VV'----'---';:cx~---"'---------1.500----

Figure 2. 1MBit Leaded Bubble Memory Package

BPK 70A TEMPERATURE RANGE
Bubble Memory
Temperature Ranges
Part Number

Support Circuits
Operating Temperature
(TAl

64 bytes per page
2048 pages per BPK 70A

128K Byte per BPK 70A
Maximum of 8 BPK 70A·1 per 7220 Controller
Maximum of 8 BPK 70A·4 per 7220-4 Controller
Maximum of 4 BPK 70A-5 per 7220-5 Controller

1 Mbit Bubble Storage
Sub-system,
Leaded Package

Addressing Scheme
Logical page number

Environmental
Performance

Temperature: See Ordering Information
Avg. Access Time ....... : ........... 48 msec
Operating Humidity: 0-95% Non-Condensing
6-263

BPK 70A

BPK 70A POWER CONSUMPTION

BPK70A Components

Power (Watts)
Total
Total
Active
Active
+5V
' +12V
(Maximum) (Maximum) (Maximum) (Typical)

Total
Standby
(Maximum)

Total
Standby
(Typical)

For larger systems in which a 7220 is controlling several BPK 70A subsystems, the power consumption
can be estimated by using the above data. By using power switching techniques the bubble memory
system's standby power can be reduced to almost zero. For details, see AP·164, .Using CMOS to
Minimize Bubble Memory Power Consumption.
BPK 70A POWER SUPPLY REQUIREMENTS
, Power Off/Power Fail
Decay Rate

less than 1.10 volts/msec

+5 Volt

± 5%

less than 0.45 volts/msec

• Voltage sequencing - no re~trictions
., Power on voltage .rate of rise -no restrictions
. • The power supply requirements shown are
based on the recommended power fail cir·
cuitry as shown in Figyre 3.

+5V

Rl
'lK

~.:.~

t-2_1_ _~-;;>t-_-A,JRy2.....,..,......-,.."C::;;x-"'_"""'_ _ _·"'"
1 =ER.

7220·1
'-----..,..~_t

, . SYSTEM
RESET

RESETI

NOTES:
1, ALL RESISTORS 1/4 WAn; 5% TOL
2, ALL CAPACITORS 10 VOC. 10% TOL
3, 01.02 ARE IN914 OR EQUIVALENT'
4, IC1 IN75463
5, Cx IS OPTIONAL-RECOMMENDED FOR EXTF1EMELY NOISY
POWER SUPPLY SITUATIONS
6, SYSTEM REseT MAY BE USED AS SHOWN PROVIDED OUTPUT ,
OF INVERTER IS OPEN COLLECTOR.

R4
5.6K

72sORESETI

r-..,.,.,---:-..,...-:-.,..----:::--t-:- 7242RESETi
RS'

33K

Figure 3. External, PowerfailCircuit Solution
,6·264

PULSE.COM! ,'2V)
REPLICATE.S
REPLICATE.A

7110A
INTEL MAGNETICS
aUBBLE MEMORY

GENERATE.A
GENERATE.B

DE1.OUT.AOET.OUT.BDET.OUT.B-

DET.COM
SWAPS

SWAP"
y .. COIL.IN
Y -.COILIN

X--COIL.IN
X·COILIN

NOTE THAT PINS 13 AND 14 SHOULD BE
EXTERNALLY CONNECTED.

Figure 4. 7110A Pin Configuration
Table 1. 7110A Pin Description
Symbol

Two·level current pulse input for reading the boot
loop.

BOOT.SWAP

7230 CPG

Single-level current pulse for writing data into the
boot loop. This pin is normally used only in the
manufacture of the MBM.

Ground return for the detector bridge.

GEN.A and GEN.B
PULSE.COM

SourcelDestlnation

7242 FSA

Differential pair (A+, A- and B+, B-) outputs
which have signals of several mi lIivolts peak
amplitude.

7230 CPG

Two·level current pulses for writing data onto the
input track.

+ 12 volt supply pin.

3,2

7230 CPG

Two-level current pulses for replicating data from
storage loops to output track.

SWAP.A and SWAP.B 13, 14

7230 CPG

Single-level current pulse for swapping data from
input track to storage loops.
.

X-.COIL.lN.
X+COIL.lN.

9,10

7254IVMOS

Terminals for the X or inner coil.

Y - .COIL.lN.
Y + .COIL.lN.

11,12

7254IVMOS

Terminals for the Y or outer coil.

REP.A and REP.B

+ 12 volt supply pin.

6-265

inter

BPK 70A

7230
EXTERNAL RESISTOR REQUIREMENTS
Connect a 1% 3.48K ohm resistor based between pin 20 and ground or rreferenced current
'
switch as outlined in BPK72 User's Manual.

Figure 5. 7230 Pin Configuration
Table 2. 7230 Pin Description
Pin No.

An active low input enabling the BOOT. REP output
current pulse.

7110A MBM

An output providing the current pulse for bootstrap'
loop replication in the bubble memory.

7110A MBM

An output providing a current pulse which may be
used for writing data into the bootstrap loop.

BOOT.SW.EN

7220 BMC

An active I,ow input enabling the BOOTSWAP output current pulse.

7242 FSA

An active low input for .selecting the chip. The
chip powers down during deselect.

GEN.A

7110A MBM

An output providing the current pulse for writing
data into the "A" quads of the bubble memory.

GEN.B

7110A MBM

An output providing the current pulse for writing
data into the "B" quads of the bubble memory.

GEN.EN.A

7242 FSA

An active low input enabling the GEN.A output
current pulse.

GEN.EN.B

7242'FSA

An active low input enabling the GEN.B output
current pulse.

PWR.FAIL

7220BMC

An active low, open collector output indicating
that either Vee or V DD is below its threshoid value.

REFR.

External Resistor

The pin for the n~ference current generator to
which an external resistance must be connected.

REP.A

7110A MBM

An output providing the current pulse for replication of data in the "A" quads of the bubble
memory.

REP.B

711M MBM

An output providing the current pulse for replication of data in the "9" quads of the bubble
memory.

REP.EN

'7220 BMC

An active low input enabling theREP.A and REP.B
outputs:

SWAP

7110A MBM

An output providirig the current pulse for exchanging ttiedata between the input track and the' ,
storage loops in the bubble memory.

SWAP. EN

7220 BMC

An active low input enabling the SWAP output.

TM.A

7220 BMC

An active low timing signal determining the cut
pulse widths of the BOOT. REP, GEN.A, GEN.B,
REP.A and REP.B outputs.

TM.B

7220 BMC

An active low timing signal determining the
transfer pulse widths of the BOOT.REP, GEN.A,
GEN.B, REP.A and REP.B outP.uts.

Symbol

6-266

BPK 70A

7242
RESET
SHIFT. elK
ENABLE.B

Figure 6. 7242 Pin Configuration
Table 3. 7242 Pin Description
Description

Output data from the FIFO to the MBM generate
circuitry. Used to write data into the bubble device
(active low).

7110A MBM

Differential signal lines from the MBM detector.

Symbol

DATA.OUT.A,
DATA.OUT.B

DET.A + , DET.A - , 6,7,8,9
DET.B + , DET.B-

SourcelDestination

Command/Oata signal. This signal shall cause the
FSA to enter a receive command mode when high
and to interpret the serial data line as data when
low. Any previously active £.ommand will be im·
mediately terminated by C/O.
Same TTL·level clock used to generate internal
ti,ming as used for 7220.

7220 BMC

An active low signal used for multiplexing of
FSAs. The FSA is disabled whenever CS is high
(i.e., it presents a high impedance to the b.us and
ignores all bus activity).

110

7220 BMC

The Serial Bus .data line (a bidirectional active high
signal).

13, 14

7230 CPGI7250

TTL-level outputs utilized as chip selects for other
interface circuits. They shall be set and reset by
the Command Decoder under instruction of the
Controller (active low).

ERR.FLG

7220 BMC

An error flag used to interrupt the Controller to indicate that an error condition exists. It shall be an
open drain, active low signal.

RESET

SELECT.IN

7220 BMC

An input utilized for time-division multiplexing. An
active low signal whose presence indicates that
the FSA is to send or receive data from the Serial
Bus during the next two clock periods.

SELECT.OUT .

7242 FSA

The SELECT.IN pulse delayed by two clocks. It
shall be connected to the SELECT.IN pin of the
next FSA. It is delayed by two clocks because the
FSA is a dual-channel device. Channel A shall in·
ternally pass SELECT.IN to Channel B (delayed by
one clock).

SHIFT.CLK

7220 BMC

A Controller-generated clock signal that shall be
used to clock data out of the bubble 110 Output
Latch to the bubble module during a write operation and to cause bubble signals to be converted
by the Sense Amp and clocked into the Bubble 110
Input Latch on a read.

DIO
ENABLE.A,
ENABLE.B

Power Fail Circuit

6·267

An active low signal that shall reset all flags and
pointers in the FSA as well as disabling the chip
as the CS signal does. The RESET pulse width
must be 5 clock periods to assure the FSA is. properly reset.

Figure 7.7250 Pin Configuration
Table 4. 7250 Pin Description
Symbol
CS

Chip select. It is active low. When high chip is
deselected and 100 is significantly reduced.

7242 FSA

RESET

X+IN,.X-.IN
X-.OUT
X-.OUT
X+.OUT
X+.OUT
Y+.IN, Y-.IN
V-OUT
Y-.OUT
Y+.OUT
Y+.OUT

Description

Active low Input from RESET.OUT of 7220
Controller forces 7250 outputs inactive so that bubble memory is protected in the event of power
supply failure.
Active low inputs from Controller which turn on
the high·current X outputs.
High-current outputs and their complements for
driving the gates of the 7254 VMOS quad transistors which in turn drive the X coils of the bubble
memory.
Active low inputs from Controller which turn on
the high-current Y outputs.
High-current outputs and their complements for
driving the gates of the 7254 VMOS quad transistors which in turn drive the Y coils of the bubble
memory.

6-268

BPK 70A

7254

Figure 8. 7254 Pin Configuration
Table 5. 7254 Pin Configuration
Symbol

ABSOLUTE MAXIMUM RATINGS·
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

7110A
Operating Temperature ......... -20°C to +85°C Case
Relative Humidity ............................... 95%
Shelf Storage Temperature (Data
Integrity Not Guaranteed) ......... -65°C to + 150"C
Voltage Applied to DET.SUPPLY .............. 14 Volts
Voltage Applied to PULSE.COM ............ 12.6 Volts
Continuous Current between DET.COM and
Detector Outputs ........................... 10 mA
Coil Current ............................... 0.5A D.C.
External Magnetic Field for
Non-Volatile Storage ................... 20 Oersteds
Non-Operating Handling Shock ................ 200G
Operating Vibration (2 Hz to 2 kHz) .............. 20G.

SUPPORT I.C.'S·
7242

7230
Temperature Under Bias
Storage Temperature

- 0.5 to Voo + 0.5
'.

- 0.5 to + 14V

Gate Voltage
Output current
Power Dissipation 80·C

Power Dissipation 25·C

1.75W

Continuous Drain Current

'D.C. CHARACTERISTICS
7110A (T C = Range Specified in temperature range table, Voo = 12V ± 5%)
7110A·1,7110A-4
Limits

RESiSTANCE: PULSE.COM to GEN:A or GEN.B

7.5

RESISTANCE: PULSE.COM to REP.A or REP.B

7.5

ohms

RESISTANCE: PULSE.COM to SWAP.A or SWAP.B

RESISTANCE: PULSE.COM to BOOT.REP

RESISTANCE: PULSE.COM to BOOT.SWAP

3.5

4.5

RESISTANCE: DET.OUT A+ to DET.OUT.A-

RESISTANCE:DET.OUT B+ to DET.OUT B-

RESISTANCE: DET.COM to DET.SUPPLY

7230 (TA = Specified in temperature range table;'Vcc = 5.0V ± 5%, ± 5%
VDD
12V ~5%; unless otherwise specifiec;l)

VIL = 0.4V. Vcc=
5.25V
VIH = VCC = 5.25V

Output Leakage Current
(All outputs except PWR.FAIL)

1.0

Vec = 5.25V,
Voo = 12.6V

ICEX2

PWR.FAIL Output Leakage Current

/LA

VOH - Vcc5.25V

VOL

PWR.FAIL Output Low Voltage

0.4

iCCl

Current from VCC-Selected

CS = VIL· Vec' =
5.25V

1001

Current from VOo-Selected

CS = VIL. VCC =; ,
5.25V

1002

Current from Voo-Power Down

,CS = VIH. Voo ~
12.6V

6-271

IOL - 4 iliA. Vcc 4.75V

infel" ,
7242(TA

BPK70A

= Specified in temperature range table; Vcc = 5.0V + 5%, ...; 10%

Output Low Voltage (All Outputs Except
, SELECT.OUT)

~VOLSO

Output Low Voltage (SELECT.OUT)

VOH

Output High Voltage (All Outputs Except
SELECT.OUT)

2.4

VOHSO

Output High Voltage (SELECT.OUT)

O';;V'N .;;Vee
0.45 ,;;VOUT .;;Vee

1111: I

Input Leakage Current

Power Supply Current from Vee

120

100

Power Supply Current from Voo

-Minimum VIH is2.2V for the 7242-5 device.

7250 (TA = Specified in temperature range table;_VDD = 12V ± 5%; -10%; unless otherwise specified)
Symbol

Parameter
Input Current

V",~

'Low-Level Input Voltage

V,H

Typ.

IIINI

High-Level Input Voltage'

Test Conditions
V, = 0.8V

Outj>uq-iigh Voltage,

IOH= -100 mA '

VOH2
IOL,
'11oHI
1000

" Output High Voltage

Voo-2
Voo-0.2

Output Sink Current

100

Output Source Current

100

IOH =.,-10 mA
VOL =2.0V

,mA

Supply Current
Supply Current

6·272

VaH = Voo-2.0Y
! .••.•

Chip Deselected: CS = VIH.
12.6V

"'DO =

'f'" 100 kHz, Voo= 12:6V:
Outputs Unloaded

inter

BPK 70A

=specified in

7254 All limits apply for N- and P·Channel transistors, TA
temperature range table; unless otherWise specified.
Symbol

Drain·Source Breakdown Voltage

VGS = 0,10 = lOILA

VGS(th)

Gate·Source Threshold Voltage

0.8

VGS = VOS, 10 = 1 rnA,
TA = 25°C

0.65

VGS = VOS, 10 = 1 rnA,
TA= 85°C'

IGSS

Gate Leakage Current

100

VGS = 12\1, VOS = 0,
TA =. 25°C

loSS

Drain Leakage Current

500

VGS = 0, VOS = 20V.
TA = 25°C

Ros

On·Resistance for sum of
01+02,03+04 (Note 1)

3.0

VGS=11.4V,10=1A,
TA = 25°C

VFl

Parasitic Diode Forward Voltage
(Note 1)

.75

VGS = OV. 10 = 50 rnA,
TA = 25°C

VF2

Parasitic Diode Forward Voltage
(Note 1)

1.20

VGS = OV, 10 = 1000 rnA.
TA = 25°C

2.0

2.5

NOTE:
1. Pulse test-BOILS pulse. 1% duty cycle. ros increase O.B%/oC.

6·273

inter·

BPK 70A·

= Specified in temperature range ,table)

DRIVE REQUIREMENTS CHARACTERISTICS[2) (TC
,

" ' . , I

7110A
Parameter .'

Symbol
fR

Field Rotation Frequency

Ipx

X.Coil Peak Current

Ipy

Y.Coil Peak Current '

81x·

X.Coil Positive Turn-On Phase

"X.Coil. Posi'tive Turn-Off Phase

X.Coil Negative Turn-On Phase

degrees

84x

X,Coil Negative Turn-Off Phase

Y.Coil Positive Turn-On Phase

82y

Y.Coil Positive Turn~Off phase ,.

Y.Coil Negative Turn-On Phase

178

180 .. '

Y,Coil Negative Turn-Off Phase

286

288

83y
.84Y

CONTROL PULSE REQUIREMENTS (T C

','

= Specified in, temperature range table)[2)

7110A
Pulse of Leading Edge
(Degrees) .

GEN.A. GEN.B TRANSFER

REP.A. REP.B TRANSFER

NOTES:
1. Nominal values are measured at Tc = 25°C.
2. Boot.Swap is not normally accessed during operating. It is utilized at the factory to write the index address and
redundant loop information onto the b?otstrap loops before shipment.
.

6-274

BPK 70A

A.C. CHARACTERISTICS·
7230 Vee

'These parameters are sample tested, not 100% tested,

POWER FAIL CHARACTERISTICS··
7230 T A = See temperature range table,
Min.

"Power fail characteristics apply to 7110A Bubble Memory Data Integrity only and notto full memory operation,

, A.C. CHARACTERISTICS

= Specified in earlier temperature ra~ge table; VCC = 5.0V + 5%,
-10%; VDD = 12V ± 5%; Cl = 120pF; unless otherwise noted)

Clock Rise and Fail Time

tSIC

SElECT,IN Setup Time to ClK

tcoc

C/O Setup Time to ClK

tCYC

SElECTIN or SHIFT.ClK Cycle Time

010 Setup Time to Clock (Read Mode)

RESETIN Setup Time to ClK

100

tlH

Control Input Hold Time for C/O, SElECT,IN and 010

tCSOl

ClK to SElECTOUT leading Edge Delay

100

Cl - 50 pF

tCSOT

ClK to SElECT.OUT Trailing Edge Delay

tcov

ClK to 010 Valid Delay'

100

tcoH

ClK to 010 Hold Time'

tCOE

ClK to 010 Enabled from Float'

100

tSIDE

SElECTIN Trailing Edge to 010 Enabled from Float'

tCOF

ClK to 010 Entering Float'

100

tSCOO

SHIFT.ClK to DATAOUT Delay'

200

tSCWR

SHIFT.ClK Width (Read)

4tp

tSCWW

SHIFT.ClK Width (Write)

7250 (TA = Specified in earlier temperature range table;VDD = 12V ± 5%,
unless otherwise specified)
Symbol

Parameter

Unit

Propagation Delay from X+.IN,
X-.IN, Y+.IN, Y-.IN

100

500 pF Load

tp2

prOtagation Delay from CS or
RE ET
.

150

500 pF Load

Rise Time (10% to 90%)

500 pF Load

. tF

Fail Time '(90% to 10%)

500 pF Load

Skew Between an Output and
Its Complements

7254 (TA = 25°C)
Symbol

N-ChanneITurn-On Time

tON(P)

P-Channel Turn-On Time

tOFF(N)

N,Channe,1 Turn:Off Time

tOFF(P)

P-Channel Turn-Off Time

Input Capacitance
'This parameter is periodically sampled and not 100% tested. Condition of measurement is f.

1 MHz.

7242 (TA = 25°C, VCC = OV, f = 1 MHz)·
Symbol

7250 (T A = 25°C, Voo = OV, VBIAS = 2V, f'= 1 MHZ)·

-This parameter is periodically sampled and is not 100% tested.

N-Channellnput Capacitance

Parameter

175

VGS = 0, VOS = 12V,
f= 1 MHz

Ciss(P)

P-Channel Input Capacitance

190

VGS = 0, VOS = 12V,
f= 1 MHz

OUTPUT CURRENTS
7230 (TA

= Specified in earlier temperature range table; VCC = 5.0V

± 5%, Voo

12V ± 5%)
Test Conditions
Voltage Out

GEN.A, GEN.B TRANSFER

BPK 72A
1MBIT BUBBLE MEMORY PROTOTYPE KIT
BPK 72A·f
BPK 72A-4
BPK 72A-5*
and Tested 1MBit Bubble
• Assembled
Memory Prototype Kit on 4" x 4" PC
Board
Complete with Powerfail Data
Protection and Clock Circuitry
Built·in Error Detection/Correction .

•
•
Interfaces with Intel 8080/85/86/88
• 186/286
and Other Microprocessors
Software
for Bubble Memory
• Kit DisketteDriver
for Intel MDS* System

o To 75°e
10 0 e To 55°e
- 20 0 e To 85°e '
1Mbit, Non·Volatile, Read·Write,
• SOlid·State
Memory in Leaded Dense
Package

•
• Maximum Data Rate of 100K bit/sec
Operates from + 5V and + 12V Power
• Supplies
Documentation and
• Complete
Interfacing Information Included

Average Random Access' Time of 48ms

The BPK 72A prototype kit is a completely assembled and tested 1Mbit bubble memory evaluationtc:i~1.
It is ideal for the design engineer that wants the opportunity to fast evaluate how a bubble memory solu·
tion improves and adds value to an end-product by providillg a compact SOlid-state memory that also
'
,
reliably keeps the data at any powerdown_
Application information on microprocessor interfacing is included in the kit A Bubble, Memory Kit soft·
ware driver is also included on a diskette for the Intel MOS' System.
*MDS is a registered trademark 'of Mohawk Data Sciences Corp.

Intel Corporation Assumes No Responsibility for tl)e Use of Any Circuitry Other Than Circuitry Embodled'in an Intel Pro.
duct. No Other Circuit Patent Licenses are Implied. "
'6-278
OCTOBER 1983
© INTEL CORPORATION
ORDER NO. 230871-1101

inter

BPK 72A

COMPONENT TEMPERATURE SPECIFICATIONS
7110A Magnetic
Bubble Memory Temperatura
Support Circuits Min.
Operating Temperature

Description

Non·Volatile Storage

Part Number
, Operating
BPK 72A-1*

O· to 75·C Case

-40· to 90·C

O· to 70·C Ambient

1 Mbit Bubble Memory
Prototype Kit Assembled

1 Mbit Bubble Memory
Prototype Kit Assembll!d

1 Mbit Bubble Memory
Prototype Kit

(* The bubble memory prototype kit is assembled and functionally tested to facilitate the prototyping process. The
board is tested at the following ambient temperatures:
BPK 72A-1
O·C and 55·C
BPK 72A-4 10·C and 40·C)

BPK 12A BUBBLE MEMORY PROTOTYPE KIT
The BPK 72A has a compact leaded bubble
memory package and does not require a socket.

is described in more detail on the 7220 data
sheet.

The bubble memory (7110A) and the support circuits (7230, 7242, 7250, 7254) in the BPK 72A kit
are described in more detail on the, BPK70A
Bubble Memory Subsystem data stieet. The Bubble Memory Controller (7220) in the BPK 72A kit

For production purposes, the bubble memory
and the support' circuit components can be
ordered as the BPK 70A Subsystem. The 7220,
controlling up to eight BPK 70A's, is ordered
, separately.

20-pin leaded package which provides 1 megabit of nonvolatile storage.

7110A-117110A-41
7110A-5

Bubble Memory Controller

User interface, performs serial-to-parallel and parallel-toserial data conversions. Generates ,timing sig'nals.

7220-117220-417220-5

Current Pulse Generator

Converts digital timing signals to analog current pulses
suited to the drive requirerne!lts of the 7110 MBM. The
CPG provides the replicate, swap, generate, boot replicate,
and bootswap pulses required by the MBM.
'

723017230-417230.-5

Dual FormatterlSense Amp

Provides direct interface to the 7110 Bubble Memory. The
FSA contains on-chip sense arnplifiers, a full FIFO data
block buffer, burst error detection and correction circuits,
and circuitry for handling of the bubble memory redundant
loops.

724217242-5

Coil Predriver

Provides the high voltage, high current outputs to drive the
7254 Quad VMOS transistors.

725017250-5

2 Quad VMOS Coil Drive
Transistors

Switches the required current to drive the X and Y coils of
the 7110 Bubble Memory.

1254
1MB 72

Prefabricated Printed
Circuit Board
'
Additional Items
BPK 72 Bubble Memory
Prototype Kit User's Manual

Literature, User's Manual, Software Guide

Diskette

Software driver for bubble memory kit, configured for Intel
MOS.

, Memory Components
Handbook
Seed Module

121685-002

Application Notes and Data Sheets.

210830

Recreates a lost seed bubble.

64 bytes per page
2048 pages per BPK 72A

Capacity
Addressing Scheme

128K Byte per BPK 72A

Logical page number

Performance
Avg.-Access Time ................... 48 msec
Maximum Data Transfer Rate .... 100 Kbits/sec
Ave~age Data Transfer Rate ....... 68 Kbits/sec

,BPK 72A POWER SUPPLY REQUIREMENTS
Power Off/Power Fail
Voltage
Margin
Decay Rate,
"

+ 12 Volt

±5%

less than 1.10 volts/msec

+5 Volt

±5%

less than 0.45 volts/msec

. Environmental
'Temperature: Temperature specifications
Operating Humidity: 0-95% Non·Condensing

• Voltage sequencing- no restrictions
• Power ori voltage rate of rise - no restrictions

. BPK 72A POWERCONSUIVIPTION'

Power (Watts)
Total
Total
Active ','
Active
(Maximum)
(Typical)
6.72

,3.90
,

,',

Total
Standby
(Maximum)

Total
Standby
(TypiC?al)

3.03

1.55

By using power switching techniques the bubble memory system's standby power consumption can be
reduced to, virtually zero., Application Note 164: Using CMOS to Minimize Bubble Memory Power Con·
sumption. (Order Number: 230826·001)
'.
'
,

6·280

7220
CONTROLLER FOR 1MBIT
BPK 70A BUBBLE MEMORY SUBSYSTEM

Provides Interface between Host
Microprocessor and 1 Mbit
Bubble Subsystems
Interfaces to 808018518618811861286
and other Standard Microprocessors
Controls Up to Eight BPK70A-1, -4,
Subsystems (or BPK70-1, -4)
Controls up to Four BPK 70A-5 Bubble
Memory Subsystems or BPK70-5

•

16 Easy-to-Use Commands

•

Three Modes of Data Transfer
-DMA
- Polled
- Interrupt

•

Transfer of Single (64 bytes) or Multiple
Pages of Data

The 7220 is a complete 1 Mbit Bubble Memory Controller (BMC) that provides the interface between the
microprocessor host and the 1 Mbit Bubble Memory Subsystem. All communication between the host
processor and the bubble memory is performed through the controller.
The BMC interfaces easily to any Intel microprocessor or other standard microprocessor. The user has
16 easy-to-use commands available. Information such as t!1e starting page location, the number of
pages to .be transferred and a read or write command is passed to the BMC before the read or write
.
operation is initiated.
The design engineer writes a bubble memory software driver to integrate the bubble memory into his
system. This interfacing with the BMC is similar to interfacing a disk drive controller. Application notes
and manuals describe the details of interfacing to the BMC.
The BMC can transfer data in DMA, interrupt or polled mode. Data is transferred in and out of the bubble
memory subsystem via the controller in single or multiple pages. A page size may vary from 64 bytes in a
single bubble system and up to 512 bytes in aneight bubble system. (Maximum page size of 256 bytes
for 7220-5.)
The BMC has an eight bit data bus plus parity bit Word length expansion to 16 bit is possible by
operating two controllers in paralleL
.
The BMC generates all the timing and control signals to the subsystem.
r---~------------l

I
I
I
"--=----' I
I
I

I
I
I

'DDI~?oNAL
IPK10'.

.
Flgu;;'

Figure 2. 7220
Pin Configuration

BU.BLE STORAGE SUISYST£M-.l

1. ei;;ck DI~;;;'; ;;t ;128K Byte Bubble Storage System

Intel Corporation Assumes No Responsibility for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Pro·
duct. No Other Circuit Patent Licenses are Implied.
OCTOBER 1983
© IN'I"ELCORPORATION
6.281
ORDER NO. 210286·002

7220

One 7220·1 or 7220·4 BMC can control up to eight BPK
, 70A·1, ·4 subsystems. This provides an easy expansion
path to expand any 1 Mbit (128K byte) system by adding
on additional subsystems. One 7220·5 can control up to
four BPK 70A·5 subsystems.

in·line package. All inputs are directly TTL compatible and
the device uses a single + 5 Volt supply.

HARDWARE DESCRIPTION

The BMC is manufactured using Intel's high performance
HMOS process and is packaged in a standard 40'pin dual·

The 7220 Bubble Memory Controller is packaged in a
40'pin Dual In·Line Package (DIP). The following lists the
individual pins and describes their function.

Table 1. Pin Description
"

SourcelDestination
+5VDCSupply

Ground
A low forces a controlled stop sequence 'and holds
BMC in an IDLE state (similar to RESET),
An active low signal to disable external logic
initiated by PWRFAll or RESET signals, but not
active until a stopping point in a field, rotation is
reached (if the BMC is causing the bubble
memory drive field to be rotated).

7230 CPG

RESET,OUT

7250 CPD/7242 FSA
7230 Reference
Current Switch

ClK

Host Bus

4 MHz, TTl·level clock.

RESET

Host Bus

A low on this pin forces the interruption 'of any
BMC sequencer ac'tivity, performs a' controlled
shut·down, and initiates a reset sequence, After
the reset sequence is concluded, alow on this pin
causes a low on the RESET.OUTpin, furthermore,
the next BMC sequencer,command must be either
the Initialize or Abort command; all other
commands are ignored.

Host Bus

A low on this pin enables the BMC oUtput data to
be transferred to the host data bus (D o'D8)'

Host Bus

A low on this pin enables the contents of the host
da,ta bus (D o·D8) to be transferred to the BMC.

DACK

Host Bus

A lOw signal is a OMA acknowledge, This
notifies the BMC that the next memory cycle is
available to transfer data, This line should be
active only when OMA transfer is desired and the
OMA ENABLE bit has been seL CS should not be
active during OMA transfers except to read status,
If OMA is not used, OACK requires an external
pullup to Vee (5,1K ohm).

ORQ

Host Bus

A high on this pin indicates that a data transfer
between the BMC and the host memory is being
requested,

INT

Host Bus

A high on this pin indicates that theBMC hasa
new status and requires servicing when enabled
by the host CPU:

Host Bus

A high on this pin selects the command/status
registers. A low on this pin selects the data
register,

11·18

I/O

Host Bus

Host CPU data bus. An eight·bit bidirectional
port which can be read or written by using the
RO and WR strobes. Do shall be the lSB.

7220
Table 1. Pin Description (Continued)

Chip Select Input. A high on this pin shall disable
the device to all but DMA,transfers'(i.e., it ignores
bus activi,ty and goes i,nto a high impepance state).

An active loll:t output utilized to create time
division multiplexing slots in a 7242 FSA chain, It
shall also indicate the beginning of a data or
command transfer between BMC and 7242 FSA.

A bidirectional pin that shall be tied to the WAIT
pin on otherBMCswhen operated in parallel. It
shall indicate that an interrupt has been generated
and that the other BMCs should halt in
synchronization with the interrupting 'SMC. WAIT is
an open collector active low Signal. Requires an
,
external pullup resistor to Vee (5.1 K ohm).
An active lov,i"input generated externally by
7242 FSA indicating that an error condition
exists. It is an open collector input ~hich requires
an external pullup resistor (5.1K ohm).
An active low signal that indicates the system is
in the read mode and may"tie detecting~ It is useful
for'power saving in the MBM.

BOOT.SW.EN

A coiitroller generated clock that initiates data
transfer between selected FSAs and their
corresponding bubble memory devices. The timing
of SHIFT.ClK'shall vary depending upon Whether
data is being reacj or written to the bubble
memory.
An active low signal that indicates that the DIO
line is in the output mode, i.e., BMC is sending
data to FSA. It shall be used to allow off·board ex·
pansion of 7242 FSA devices.

A bidirectional active high data line that shall be
used for serial communications with 7242 FSA
devices.' .

A high on this line indicates that the BMC is
beginning an FSA command sequence. A low on
this,line indic.ates that the BMC is beginning a
data transmit or receive sequence.

7230 CPG

An,active low signal which may be used for "
enilbling the BOOT.SWAP olthe 7230 CPG.

SWAP. EN

.'31

7230 CPG

An active low signal uS'ed to create the swap
,function in external circuits.

BOOT.EN

723.0 CPG

An active low signalenabling,ihe boqtstrap loop
repHcate function in .external circuitry.

REP. EN

7230 CPG

An active low,signalused to enable the replicate
function in external·circuitry.

TM.B

7230 CPG

An active low timing signal generated by the
decoder'logic for determining TRANSFER pulse
, .... , ..
width.

TM;A

7230 CPG

Anactiv~ low timing signal generated by the
,deco,dar logic for determining CUT; "pulsEil·width ..

36·39

7250 CPD

Four active low timing signals generated by the
decoding logic and used to create coil drive
currents in'thebubble:memory device,

y.-:V+,
,X-, X+

"
·Not used in minimum (128K byte) system.

6-283

7220
MiI,roprocessor-Bus compatible interface for the
magnetic bubble memory system_

FUNCTIONAL DESCRIPTION
The 7220 Bubble Memory Controller provides the user Interface to the bubble memory system_ The BMC
generates all memory system timing and control, maIntains memory address information, interprets and executes user request for data transfers, and provides a

Figure 3 Is a block diagram of the 7220 Bubble Memory
Controller (BMC)_ The following paragraphs describe the
functior;1s of the Individual functional sections of the
BMC.

POWER FAIL.
ABORT. AND
RESET LOGIC

I
N
T
E
R
N
A
L
B
U
S

SYSTEM
BUS
INTERFACE
DATA REGISTER,
DMAAND
INTERRUPT·
LOGIC

v:.

BUBBLE
SIGNAL
DECODER
010 & BOOTLOOP
ENCODER/DECODER

DRQ
INT

i'M.li
TM:ii
REP.EN

iiOOT.EN
SViAP.EN
BOOT.SW.EN

C/D
SHiff.CIi(

SYNC
CLK

010

Figure 3. 7220 Bubble Memory Controller (BMC), Block Diagram
System Bus Interface! The System Bus Interface (SBI)
logic contains ·the timing and control logic reqiJired to
interface the BMC to a non-multiplexed bus. The logic
also contains the circuitry to cheCk and generate odd
parity on transfers across the bus. The interface has input data, output data,.and status data latches. The BMC
. can interface asynchronously to the host CPU. With a
4-MHz clock, it is capable of sustaining a 1.14 Mbyte per
second transfer rate, while.data is available in the BMC
FIFO.
FIFO....,. The FIFO consists of a 40 x8 bit .FIFO RAM for
data storage. The FIFO block also contains input and
I h
'd
d
.
t td
ou pu ata ate eS,provl ing ouble data buffering, to
improve the R/Vol cycle times seen at the system bus interface. The FIFO may. be used as a general purpose
FIFO when a command' is not being executed by the
BMC Sequencer. In this mode, the FIFO READY status
bit becomes a FIFO not·empty indicator indicating that

6-284

the RAM and input/output latches have at least one byte
of data.
DMA and Interrupt Logic-The ORO pin has two func.
tions:
(1) If the OMA enable bit in the enable register is set,
the ORO pin, in conjunction with the OACi< pin, provides a standard OMA transfer capability; i.e.; it has
the ability to handshake with an 8257 or 9517/8237
OMA controller chip.
.
(2) If the OMA enable bit is reset, the ORO pin acts as a
"ready for data transfer iriterrupt" pin. It becomes
active when 22 bytes may be read from or. written in·
to the BMC', it is reset when this condition no longer
exists.
Register File-The register file contains 7 eight-bit
registers that are access.ible by the host CPU. Refer to
the Register Section for details.

inter

7220

MBM Address Logic and RAM- The MBM address logic
consists of the block length counter, starting address
counter,adder, and MBM Address RAM. The MBM Ad·
dress RAM is used to store the n!3xt available page ad·
dress for each of up to 8 dual FSAs. The address main·
tained is the read address; the write address is generated,
when needed, by adding a constant to the stored read
address.
'

Table 2. 7220 BMC Timing (Degrees)"

The block length counter enables multiple page trans·
fers of up to 2048 pages in length.
The starting address counter is used as a register to
hold the desired start address. Once the start address is
reached, the counter is incremented on each subse·
quent page transfer so that its value is equal to the pre·
sent read address.
DIO Bootloop Decoder/Encoder- Performs parallel·to·
serial and serial·to·parallel conversions between the
FIFO data and the serial bit stream on the 010 line. This
block also generates the BUS.RO' signal, which indio
cates the direction of data transfer on the 010 line (this
is useful in situations which require external buftering
on the 010 line). This block also contains the circuitry
which decodes the bootloop data during a Read
Bootloop or Initialize operation, and encodes the boot·
loop data during a Write Bootloop operation.

x+
Y+
xYTM.A (ODD)
TM.A (EVEN)
TM.B (ODD)
TM.B (EVEN).
BOOT. EN
REP.EN
SWAP.EN
BOOT.SW.EN'
SHIFTClK (RO)

270°
0°
90°
180°,
270°
90°
270°
90°
252°
252°
180°
180°
186.75 °
72°

108°
108°
108°
108°
4°
4°
90°
90°
108°
108°
5'?"

378°
108°
198"
288°
274.5°
94.5°
360°
180°
360°
360°
697"
180°
285.75°
360°

SHIFTClK (WR)

~C'

99°
288°

eStays low for 4118 field rotation periods when writing the MBM
Bootloop,
*. All

phases relative to y'; start phase. AU entries:!: 1.20'except TM.A
width which is :c: 0.5'.

SWAP.EN, REP.EN, BOOT.SW.EN, and BOOT.EN all go
to the 7230 CPG. They are used to enable, respectively,
the data swap, data replicate, boot swap, and boot
replicate functions within the MBMs.

Sequencer-Controls the execution of commands by
decoding the contents of its own ,internal ROM in which
the BMC firmware is located. This block also sets and
resets flags and status bits, and controls actions in
other parts o/,the BMC.

SHIFT.ClK goes to the' FSAs. It is used to control the
timing of events at the interface between each FSA and
its corresponding MBM. (Refer to 7242 FSA Specifica·
tion for a description of the BMC/FSA interface.)

Power Fail and Reset- Provides a means of resetting
the bubble systems in an, orderly manner, when actio
vated by the PWR.FAIL signal, the RESET signal, or the
ABORT command. The additive noise on the PWR.FAIL pin
should be less than 150 mV for proper powerfail
operation.

SYNC and C/D control the serial communications be·
tween the BMC and the FSAs (on the 010 line).

USER·ACCESSIBLE REGISTERS

FSA Select Logic block contains the logic which con·
trois the timing of the interaction between the BMC and
the FSAs. The FSA selection is determined by the four
high·order bits iri the BlR and the four high·order bits in
the AR; both set by the,user.
Bubble Signal Decoder block. contains the logic for
creating all the MBM timing signals. The BMC to bubble
memory interface consists of active low timing signals.
The starting and stopping point of each signal is deter·
mined by the decoder logic. Each signal may occur
every field rotation or only once in a number of field rota· .
tions. The field rotation in which a timing pulse occurs
is controlled by the sequencer logic.
Figure 4 and Table 2 illustrate the typical timing signals
for the BMC. These signals are described in the following paragraphs.

X +, X - , Y + , and Y ~ go to the 7250 CPOs, and are
used to enable the coil drive currents in the MBMs.
TM.A and TM:B go to the 7230 CPGs, and are used to
determine, respectively, the pulse widths for the CUT
and TRANSFER functions used 'in ,replicating and gen·
erating the bubbles.

6·285

The user operates the bubble memory system by read·
ing from or writing to specific registers within the bub·
ble memory controller (BMC). The following paragraphs
iden'tify these registers a~d gives brief functional
descriptions, including bit configurations and address
assignments.
.

Register Addressing
Selection of the user·accessible registers depends on
register address information sent from' the user to the
BMC. This address information is sent via a single ad·
dress lirie (designated Ao) and data bus lines Do through
'
0 4,
Both COmmand Register (CMOR) and Register Address
Counter (RAG) are 4·bit registers which are loaded from
00.03' The status register is selected and read by a
single read request The command register is selected
and loaded by a single write request. The remaining
registers are accessed indirectly, and the desired register
is first selected by placing its address in the RAC, and then
read or written with a subsequent read or write request.

r_----...e('
~__~r--~--~
L

OoD

~----~~--------~~------~--~~'
BOOT,

----------..,1

DC (INACTIVE ON lBO)

.L._ _ _ _ _~-------------------------

SW,EN

1_____-'

SHIFTCLK - - - - - - - ' - - - '..
(Rol
.•

SHIFTCLK - - - ' - - ,

(Wii)

Figure 4. 7220 BMC Timing .Diagral)1
Table 3 gives a complete listing of the address asign:
ments for theuser'accessible registers. The registers
are listed in two groups, The first group (STR, CMDR,
RAG) consists of those registers that are selected and
accessed in one operation. The second group (UR, BLR,
ER, AR, FIFO) consists of thos,e registers that are
addressed indirectly by the contents of 'RAG.:

Table 3. Address Assignments for ,the
User-Accessible Registers
AO D7 D6 D5 D4 D3 D2 D1 DO Sym~ol

differences between the parallel data transfer to or from
the host microprocessor and the serial data tral)sfer to
or from the Bubble Memory Subsystem. Accordingly,
when an application program requests data from a bubble, the software driver is responsible for keeping up
with the FIFO for the duration of the data transfer in
order to prevent the FIFO from overflowing or
underflowing.

Data Transfer Mode
As described earlier in the hardware section, three data
transfer modes are available (polled, interrupt·driven or
DMA).
System performance; additional' hardware and software
overhead are all important considerations when choosing the appropriate mode for your application.

Set-up the BMC for data transfer communication
by loading specific parameters in user-accessible
registers.
Send the desired command.
Read the status register to determine if command
is accepted.
If applicable, transfer (Le., read or write) data.

Error Correction
The bubble memory system has a built·in error correc·
tion. To insure highest data integrity, the error correc·
tion should always be used. Three levels of error correction are avai lab Ie.

Read the status register until BMC is not busy (or
under some conditions "INT" pin).
Examine the status register to determine whether
ttie operation was successful.

Communication with the BMC .
All communications between the host and the bubble
memory actually are performed through the BMC. The

6-293

For all details and exceptions to this general description, see AP-157. or the BPK 72 User's Manual.

inter

7220

ABSOLUTE MAXIMUM RATINGS
Temperature under bias .............. -40 to +100·C
Storage Temperature ... ; .:.' ....... - 65'C to + 150'C
All Input or Output Voltages and
Vee Supply Voltage ..................... -0.5V to 7V

D.C. CHARACTERISTICS (TA

'NOTICE: Stresses above those 'listed under "Absolute MaxImum Ratings" may cause permanent damage to the device.
This Is a stress rating only and functional operation of the
device at these or any other conditions above those indicated
In the operational sections of this speclllcation is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. '

= see front page; Vcc = 5.0V

Output low Voltage
(All outputs except DET.ON, BUS.RD.
SHIFT.ClK. ahd SYNC

.45

10L = 3.2 mA

VOL (2)

Output low Voltage
DET.ON. BUS.RD. SHIFT.ClK, SYNC

Input High Voltage (PWR.FAll)

VOl (l)

High Voltage (all but PWR.FAIL)

Input leakage Current

Power Supply Current fromVcc

200

A.C. CHARACTERISTICS
= see front page; Vcc = 5.0V + 5%, -10%, Cl = 150pF; unless otherwise noted.)

Clock Phase Width (High Time)

.45 tp

'.55 tp

tR-tF

Input Signal Rise and Fall Time

FSA INTERFACE TIMINGS (under pin loading)
Symbol

Parameter

Min.

tCDV

ClK to 010 Valid Delay

tCDF

ClK to 010 Entering Float

tCDE

ClK to 010 Enabled from Float

tCDH

ClK to OrO Hold Time

tCSOl

ClK to SYNC, leading Edge Delay

tCSOT

ClK to SYNC Trailing Edge Delay

tDC

010 Setup Time to Clock

Under Pin loads'

tDHC

010 Hold Time from Clock

ClK to Output leading Edge

tCOT

ClK to Output Trailing Edge

SHIFTClK to Y - Trailing Edge

see front page; Vcc
5.0 ± 5%, -10%; Cl
unless otherwise noted; •• = 7220·5.)

A.C. CHARACTERISTICS (Continued) (TA
READ CYCLE (HOST INTERFACE)
Parameter

Data Delay from Address

Data Delay from DACK!

tCYCR

200

100

150(200")
(DMA Mode)
41.-t,

In non DMA mode.
t CYCR Min. = 6t.-t,

WRITE CYCLE (HOST INTERFACE)
Parameter

Request Hold from RD or WR
(Non-Burst Mode)

. Inactive Time between WRr andWRI

4tp

tOEADA

Inactive Time between RDr and RDl

150

ns
ns

MD7250·MD7230 INTERFACE TIMINGS
Max.

Unit

Test Condition

tCBl

ClK to Bubble Signal leading Edge

250(275")

Under Pin Loads'

tCBT

ClK to Bubble Signal Trailing Edge

'Bubble Pin loads Shown Below

PIN lOADINGS
Pin Names'

TM.A, TM.B, REP. EN, BOOT.EN,
SWAP.EN. BOOT.SW.EN: C/O.
ERR.FLG, WAIT, SYNC, 010

WAVEFORMS
READ (HOST INTERFACE)

i----~----tCYCA'-------_t

DACK --"""'"

CS
Ao

Jr"'....;..---+-----------'---..,.

----+-'" JI--t+---------t--"Il ,---" ,.-~-----+--' ]\---IH---------+-.....,-----J ,,--+--

DATA BUS

14---1'0,---+1
I+----IDEADR-,----~

I+----IKO'----I

WRITE (HOST INTERFACE)

i--------tCYC,.----------+i
DACK - - " " " " ' \ .

Jr-----t------------""lIL ,--" r - - t - -

CS - - - - ' "

-I!--++---------t--"'\oL ,---'" r - - t - -

Ao _ _ _ _J

1'---4+---------11-.....,- '-_ _ _J

,,--+--

1 4 - - - -lww----1
WII

DATA BUS

I...e - - - - - I O W - - - -....t--IWO

DMA (HOST INTERFACE)
1 4 - - - - t OEAO----l
DRO

~tca

1m O R W I I - - - - J I

6-296

~----~---------

7224
CONTROLLER FOR 4MBIT
BPK 5V74 BUBBLE MEMORY SUBSYSTEM
•

Provides Interface between Host
Microprocessor and 4 Mbit
Bubble Memory Subsystems

•

Interfaces to 808018518618811861286
and Other Standard Microprocessors

•

Controls up to Eight Bubble Memory
Subsystems

•

18 Easy-to-Use Commands

•

Three Modes of Data Transfer
-DMA
- Polled
- Interrupt

•

Transfer of Single (64 bytes) or Multiple
Pages of Data

The 7224 is a complete 4 Mbit Bubble Memory Controller (BMC) that provides the interface between the
microprocessor host and the 4 Mbit Bubble Memory Subsystem. All communication between the host
processor and the bubble memory is performed through the controller.
The BMC interfaces easily to any Intel microprocessor or other standard microprocessor. The user has
18 easy-to-use commands available. Information such as the starting page location, the number of
pages to be transferred and a read or write command is passed to the BMC before the read or write
operation is initiated.
The 18 commands of the 4MbitBMC is a superset of the 1Mbit BMC's 16 commands providing an easy
up-grade of software from the 1Mbit to the 4Mbit system.
The design engineer writes a bubble memory software driver to integrate the bubble memory into his
system. This interfacing with the BMC is similar to interfacing a disk drive controller. Application notes
and manuals describe the details of interfacing to the BMC.
The BMC can transfer data in DMA, interrupt or polled mode. Data is transferred in and out of the bubble
memory subsystem via the controller in single or multiple pages. A page size may vary from 64 bytes in a
single bubble system and up to 512 bytes in an eight bubble system.
.

~----------------,

I
I
I
I
I
I

........
....
....
TO

MEGABIT
IUIBtE
MEMOfl,Y
(MBM.

~ _L-_-_-_-_-_-:::~b.=~L.~<.!!!I~Y'1!.EMJ
TO
ADDITIONAL
BPK 5V74

Figure 2.
. Pin Configuration

Figure 1. Block Diagram of a 512K Byte
Bubble Storage System

Intel Corporation Assumes No Responsibility for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied.
© INTEL CORPORATION
OCTOBER 1983

The BMC has an eight bit data bus plus parity bit. Word
length expansion to 16 bit is possible by operating two
controllers in parallel.
The BMC generates all the timing and control Signals to
the BPK 5V74 subsystem.
One BMC can control up to eight BPK 5V74 subsystems.
This provides an easy expansion path to expand any 4
Mbit (512K byte) system up to 32Mbit (4Mbyte) by adding
on additional BPK 5V74 subsystems.

The BMC is manufactured using Intel's high performance
HMOS process and is packaged in a standard 40-pin dual·
in·line package. All inputs are directly TTL compatible and
the device uses a single + 5 Volt supply.

HARDWARE DESCRIPTION
The 7224 Bubble Memory Controller is packaged in a
40'pin Dual In·Line Package (DIP). The following lists the
individual pins and describes their function.

Table 1. Pin Description
PlnNo.

7234 CPG
7250 CPDI7244 FSA

7234 Reference
Current Switch

Description

A low forces a controlled stop sequence and holds
BMC in an IDLE state (similar to RESET).
An active low signal to disable external logic
..
initiated by PWR.FAIL or RESET Signals, but not
active until a stopping point in a field rotation is
reached (if the BMC is causing the bubb!e
memory drive field to be rotated).

ClK

Host Bus

2 MHz, TTL·level clock.

RESET

Host Bus

A low on this pin forces the interruption of an'y
BMC sequencer activity, performs acontrolled
shut-down, and initiates a reset sequence. After
the reset sequence is concluded, a low on this pin
causes a low on. the RESET.OUT pin, furthermore,
the next BMC sequencer command must be either
the Initialize or Abort command; all other
commands are ignored.

Host Bus

A low on this pin enables the BMC output data to
be transferred to the host data bus (Do-OS>.

Host Bus

A low on this pin enables the contents of the host
data bus (Do·DS> to be transferred to the BMC.

DACK

HostBus

A low Signal is a DMA acknowledge. This
notifies the BMC that the next memory cycle is
available to transfer data. This line should be
active only when DMA transfer is desired and the
DMA ENABLE bit has been set. CS should not be
active during DMA transfers except to read status.
If DMA is not used, DACK requires an external
pullup to Vee (5.1K ohm).

ORO

Host Bus

A high on this pin indicates that a data transIer
between the BMC and the hqst memory is being
requested.

INT

Host Bus

A high on this pin indicates that the BMC has a
new status and requires servicing when enabled
by the host CPU.

Host Bus

Ahigh on this pin selects the commandlstatus
registers. A low on this 'pin selects the data
register;'

11-18

110

Host Bus

Host CPU data bus. An eight·bit bidirectional
port which can be read or written by using the
RD and WR strobes. Do shall be the lSB ..

7224
Table 1. Pin Description (Continued)
PinNo.

Chip Select Input. A high on this pin shall disable
the device to all but OMA transfers (i.e., it ignores
bus activity and goes into a high impedance state).

010

1/0

7244 FSA

A bidirectional active high data line that shall be
used for serial communications with 7244 FSA
devices.

SYNC

7244 FSA

An active low output utilized to create time
division multiplexing slots in a 7244 FSA chain. It
shall also indicate the beginning of a data or
command transfer between BMC and 7244 FSA.

SHIFT.ClK

7244 FSA

BUS.RO

A controller generated clock that initiates data
transfer betwee·n selected FSAs and their
corresponding bubble memory devices. The timing
of SHIFT.ClK shall vary depending upon whether
data is being read or written to the bubble
memory.
An active low signal that indicates that the 010
line is in the output mode, Le., BMC is sending
data to FSA. It shall be used to allow off-board expansion of 7244. FSA devices.

WAIT

110

Signal Name

To User External
Circuit

To Alternate
Controller(s)
When User System
Uses More Than
One Controller.

A bidirectional pin that shall be tied to the WAIT
pin on other BMCs when operated in parallel. It
shall indicate that an interrupt has been generated
and that the other BMCs should halt in
synchronization with the interrupting BMC. WAIT is
an open collector active low signal. Requires an
external pullup resistor to Vee (S.1K ohm).
An active low input generated externally by
7244 FSA indicating that an error condition
exists. It is an open collector input which requires
an external pullup resistor (5.1K ohm).

A high on this line indicates that the BMC is
beginning an FSA command sequence. A low on
this line indicates that the BMC is beginning a
data transmit or receive sequence.

BOOT.SW.EN

7234 CPG

An active low signal which may be used for
enabling the BOOT.SWAP of the 7234 CPG.

SWAP.EN

7234 CPG

An active low signal used to create the swap
function in external circuits.

BOOT.EN

7234 CPG

An active low signal enabling the bootstrap loop
replicate function in external circuitry.

REP. EN

7234 CPG

An active low signal used to enable the replicate
function in external circuitry.
'

TM.B

7234 CPG

An active low timing signal generated by the
decoder logic for determining TRANSFER pulse
width.

TM.A

7234 CPG

An active low timing signal generated by the
decoder logic for determining CUT pulse width.

36;39

7250 CPO

Four active low timing signals generated by the
decoding logic and used to create coil drive
currents in the bubble memory device..

Y-,Y+,
X-,X+

7244 FSA

To User External
Circuit

6-299

An active low signal that indicates the system is
in the read mode and may be detecting. It is useful
for power saving in the MBM.

7224

Microprocessor-Bus compatible interfa,ce for the
magnetic bubble memory system.

FUNCTIONAL DESCRIPTION
The 7224 Bubble Memory Controller provides the user
interface to the bubble memory system. The BMC
generates all memory system timing and' control,
maintains memory address information, interprets and
,executes user request for dllta transfers, and provides a

Figure 3 is a block diagram of the 7224 Bubble Memory
Controller (BMC). The following paragraphs describe the
functions of the Individual functional sections of the BMC.

POWER FAIL,
ABORT, AND
RESET LOGIC

SYSTEM
BUS
INTERFACE
DATA REGISTER,
DMAAND
INTERRUPT,
LO,GIC

BUBBLE
SIGNAL
DECODER
010 & Boonoop
ENCODER/DECODER

DRQ

TM.A
TM.B
REP. EN

iiOli'i':EN
SWAP.EN
BOOT.SW.EN

Figure 3. 7224 Bubble ,Memory Controller (BMC), Block Diagram
. the RAM and input/output latches have at
of data.

,System Bus Interface-The System Bus Interface (SBI)
logic ,contains the timing and control logic r~quired to
interface the BMC to a non·multiplexed b.\ls. The log'ic
also contains the circuitry to check and generate ,odd
parity on transfers across the bus. The interface has Input data, output data, and status data latches. The BMC
can interface asynchronously to,the host CPU~ With a
'2-MHz clock, ifis capable of sustaining a 1 Mbyte per
second transfer rate while data is available in the BMC
,FIFO.

I~asf one byte

DMA and Interrupt LogiC- TheORa pin has two functions:

FIFO- The FIFO consists of a40 x 8 bit FIFO RAM for
data storage ..The FIFO block also contains in'put and
output data latches, providing double data buffering, to
improv,E1 the RlW cycle times 'seen at the system bus interface. The FIFO may.be used as a general purpose
FIFO When a command is not being executed by the
BMC Sequencer; In this mode, the FIFO READY status
bit becomes a FIFO not-empty Indicator indicating that ,

(1) 'If the DMA enable'bit in the enable register Is set,
the DRO pin, in conjunction with the DACi< pin, provides a standard DMA transfer capability; i.e., It has
the ability to handshake with an, 8257 or 9517/8237
DMA controller chip.
(2) If the DMA enable bit is reset, the DRO pin acts as a
"ready for data transfer interrupt" pin. It becomes
active when 22 bytes may be read from or written in·to tlie BMC; it is reset when this condition no loriger
exists.
Register Flle- The register file contains 6 eight-bit
registers that are accessible by the host CPU. Refer to the
Register Section for details.

6-300

7224
Table 2. 7224 BMC Timing (Degrees)··

MJ3M Address Logic and RAM- The MBM address logic
consists of the block length counter, starting address
counter, adder, and MBM Address RAM. The MBM Ad·
dress RAM is used to store the next available page ad·
dress for each of up to 8 dual FSAs. The address main·
tained is the read address; the write address is generated,
when needed, by adding a constant to the. stored read
address'.
The block length counter enables multiple page trans·
fers of up to 2048 pages in length.

Signal

X±

The starting address counter is used as a register to hold
the desired start address. Once the start address is reach·
ed, the counter is incremented on each subsequent page
transfer so that its value equal to the present read address. There are 8192 possible starting addresses.
010 Bootloop Decoder/Encoder- Performs parallel·toserial and serial-to-parallel conversions between the
FIFO data and the serial bit stream on the DIOline. This
block also generates the BUS.RDsignal, which indicates the direction of data transfer on the DIO line (this
is useful in situations which require external buffering
on the DIO line). This block also contains the circuitry
which decodes the boot loop data during a Read
Bootloop or Initialize operation., and encodes the bootloop data during a Write Bootloop operation.

is ± 0.5.

SHIFT.ClK goes to the FSAs.lt is used to control the timing of events at the interface between each FSA and its
corresponding MSM. (Refer to 7244 FSA Specification for
a description of the BMC/FSA interface.)
SYNC and C/O control the serial communications between the BMC and the FSAs (on the 010 line).

USER·ACCESSIBLE REGISTERS
The user operates the bubble memory system by reading from or writing to specific registers within the bubble memory controller (BMC). The following paragraphs
identify these registers and gives brief functional
descriptions, including bit configurations and address
assignments.

Bubble Signal Decoder block contains the logic for
creating all the M.BM timing signals. The BMC to bubble
memory interface consists of active low timing signals.
. The starting and stopping point of each signal is determined by the decoder logic. Each signal may occur
every field rotation or only once in a number of field rot~
tions. The field rotation in which a timing pulse occurs
is controlled by the sequencer logic.

used to enable the coil drive currents in the MBMs.

YTM.A (LATE)
TM.A (EARLY)
TM.B (LATE)
TM.S (EARLY)
BOOT. EN
REP. EN
SWAP.EN
BOOT.SW.EN
SHIFTClK (RD) LATE
EARLY
SHIFTCLK(WR) LATE
EARLY

SWAP.EN, REP.EN, BOOT.SW.EN, and BOOT.EN all go to
the 7234 CPG. Theyar.e used to enable, respectively, the
data swap, data replicate, boot swap, a(1d boot replicate
functions within the MBMs.

FSA Select Logic block contains the logic which controls
the timing of the interaction between the BMC and the
FSAs. The FSA selection is determined by the four highorder bits in the .BLR and the three high-order bits in the
AR, both set by the user.

TM.A and TM.B go to the 7234 CPGs, and are used to
determine, respectively, the pulse widths for the CUT and
TRANSFER functions used in replicating and generating
the bubbles.

O·
90·
180·
279·
99·
279·
99·
261"
261·
180·
180·
230.5·
40.5·
261·
81·

TM.A width which

Power Fail and Reset- Provides a means of resetting
the bubble systems in an orderly manner, when activated by the PWR.FAll signal, the RESET signal, or the
ABORT command. The additive noise on the PWR.FAIL pin
should be less than 150 mV for proper powerfail
operation.

)( +, X -, Y +, and Y - go to the 7250 CPDs, and are

Y+

X-

Width
108·
108·
108·
108·
94.5·
94.5·
90·
90·
126·
126·
153·
DC'
45··
63·
126·
126·

'Stays low for 8211 field rotation periods when writing
the MSM Bootloop.
•• All phases relative to Y + start phase. All entries ± 1.26 except

Sequencer-Controls the execution of commands by
decoding the contents of its own internal ROM in which
the BMC firmware is located. This block.also sets and
resets flags and status bits, and controls actions in
other parts of the BMC.

Figure 4 and Table 2 illustrate the typical timing signals
for the BMC. These signals are described in the following paragraphs.

Start
270·

Register Addressing
Selection of the user-accessible registers depends on
register address information sent from the user to the
BMC. This address information is sent via a single address line (deSignated Ao) and data bus lines Do through
05'
The Command Register (CMDR) is an 8-bit register which
. is loaded from Do - 0 7, Register Address Counter (RAC)
is a 4-bit register which is loaded from Do - 0 3, The
status register is selected and read by a Single read request. The command register is selected and loaded by a
single write request. The remaining registers are accessed indirectly, and the desired register is first selected by
placing its address in the RAC, and then read or written
with a subsequent read or write request.

Y+/~..- - - - -......

'---__----'r

X-I------~

r-------------------------,L---

Y-I----------------~~
'--------'

X+/--.J
TMN---~-~'Ur---------,U

TMB/--------,

1-----..,_......1

SHCLKI(WR)';'"- - - - - - - - - - ; ._ _ _ _ _ _...~..._ _ _ _ _ _......r___lL.______
'SHCLKi(RD)

-'-----.L-1r--------------,L-!

_'r'

L-Jr-----------

REPEN/-------------------,
BOOTEN/-------------------,
1l00T.S\ll.EN/-------------~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _D_C""'II_NA_CTIVE ON 180·)

SWAPEN/(START) ~_"-:_ _ _ _ _ _ _ _ _ _-,

SWAPEN/(STOP) - - - - - - - - - - - - - ' - - - - - - - - - - -....
TMN(FORREP~-------------------~ur--~---------------

TMB/(FOR REPS) ---------------------~

Figure 4. 7224·BMC Timing,Diagram
Table 3. Address Assignments for the
User-Accessible Registers (Cortinued)

Table 3 gives a complete listing of the address asign·
ments for the user-accessible registers. The registers
are listed in two groups. The first group (STR, CMDR,
RAC) consists' of those registers that are selected and
accessed in one operation, The second group (UR, BLR,
ER, AR, FIFO) consists of those registers that are
addressed indirectly by the contents of RAG.

RAe
AO 83 82 81 80

Table 3. Address Assignments for the
User~Accessible Registers '
AO 07 06 05 04 03 02 01. DO Symbol
1 0

1 C C C C

1 ,0

Name of Register ReadlWrlte

Block Length
Register LSB
Block Lenglh
Register MSB
Enable Register
Address Regisler
LSB
Address Register
MSB.
FIFO Data Buffer

AR MS'B

FIFO

ssssssss:;;
CCCCC =
BBBB =
B3B2B1BO=

ReadlWrile
WriteOnly
Write Only

Read or~rite
Read or Write
Read or Write
Read or Write

a·bit status information returned to the user from the.STR
5-bit command code sent 10 the CMDR by the user.
4·bit register address sent to the RAC by the user.
4·bit contents of RAC at the time the user makes a read or
write request with AO = O.
LSB = Least Significant Byte
MSB = Most Significant Byte
M = Modifier (When written high will clear any pending
interrupt from 7224 without destroying any data
present in the FIFO and its associated latches.

6-302

inter

7224

The register file contains the registers with address 1011
through 1111. These registers are also called parametric
registers because they contain flags and parameters that
determine exactly how the BMC will respond to com·
mands written to the CMDR.
To jacil!tate,such operations, theBMC automatic;l.lly in·
crements the RAC by one count after each transfer of
data to or from a parametric register.
The 'RAC'increments from the initially loaded value
through address 1111 and then on to 0000 (the FIFO ad·
dress): When it has reached 0000, it no longer incre·
ments. All: subsequent data transfers (with AO = 0) will
be to or from the FIFO until such time as the RAC is
loaded With a different register' address.

Commands relating to the bootioop, and used only for
diagnostic purposes, are:
Read Bootioop Register
Write Bootloop Register
Write ,Bootioop Register Masked
Read Bootioop
Write Bootloop

Status Register (STR) 8 Bits, Read Only
The user reads the BMC status register in response-to
an interrupt Signal, or as part of the polling process in a
polled data transfer mode. The status register provides
information about error conditions, completion or ter·
mination of commands, and about the BMC's readiness
to transfer data or accept new commands. The in·,
dividual bit descriptions are as follolYs:

Co;nmandRegister (CMDR) 4 Bits, Write Only
The user issues a command to the BMC by writing a 5·bit
command code to the CMDR.

STATUS REGISTER

Table 4 I,ist~ the S·bit command codes used to issue the
eighteen commands recognized by the BMC.

FIFO READY
PARITY ERROR
L-_ _~+ UNCORRECTABLE ERROR
L-_ _ _ _ _ CORRECTABLE ERROR
L-_ _ _ _ _ _+ TIMING ERROR

Table 7 is a listing of the commands and their functions.

Table 4. Command Code Definitions

' - - - - - - - - _ OP FAIL

05 03 02 01 00
1 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 11
1
0
0
1
1
0
0
1
0
1
0
1
0, 1
1 0
1 0

0
0
0
0
1
1,

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1,
,1

Command Name
Write Bootioop Register Masked
Initialize
'Read Bubble Data
Write Bubble Data
Read Seek
,Read Bootloop Register
Write BootiooP Register
Write Bootioop
Read, FSA,Status
Abort
Write Seek
,Read Bootioop
Read Corrected Data
Reset FIF;O , '
MsMPuige, ,
Software Reset'
Zero Access Read Seek
Zero Access Read Bubble Data
used cOmmands," normalopera·

0
1
0
1
0
1
0
1
,0
1
0
1'
0

1
0
0
0
0
1
1
i,
1
0
1
1,
0 0 1
0 1 0
The most commonly
tion are: , "
Initialize,
, ,;
Read Bubble Data
Write Bubbie ,Data
Reset FIFO'
Read Seek
Write Seek
Abort
Read Corrected Data
Software Reset
Read FSA Status
MBM Purge
Zero Access Read Seek
Zero Access Read Bubble Data

' - - - - - - - - - - - . OP COMPLEtE
L -_ _ _ _ _ _ _ _ _ _.... BUSY

BUSY (when = 1) indicates that the BMC is'in the
process of executing a command. When equal to
0, BUSY indicates that the BMC is ready to receive
a new command.
OP COMPLETE (when = 1) indicates the successful
completion of a command.
OP FAIL (when = 1) indicates th'at 'the BUSY bit has
gone inactive with either theTIMING ERROR.or UN·
CORRECTABLE ERROR bits active.
'
TIMING ERROR (when = 1) indicates that a FSA has
reported a timing error to the BMC, ,or that the host
system has failed to keep up with the BMC, thereby
causing the BMC FIFO to overflow or ,to underflow.
TIMING ERROR is also set if no bootloop sync word
is found during initialization, or if a Write Bootloop
command is issued when the WRITE BOOTLOOP
ENABLE bit is equal to zero in the enable register, or
the Write Bootloop Register Masked command is
sent without an adequate number of 1's present'in
data pattern.
CORRECTABLE ERROR (when = 1) indicates that
a FSA has reported to the BMC that a correctable
error has been detected in the last data block
transferred.

6·303 '

7224

, ENABLE PARITY INTERRUPT eriabl~sthe BMCtQ
interrupt the host system '(via the INT line) when
theBMC detects"a parity error on, ,the data bus
'
lines 00-07'

UNCORRECTABLE ERROR (when = 1) indicates
that at least one FSA has reported to the BMCthat
uncorrectable error has tleen detected' in the last
data block transferred.
'

PARITY ERROR (when = 1) ,indicates that the
BMC's parity check circ(iitry has detected a parity'
error on'a data'byte sent to the BMC by the user on
ttie dat~lines Do-Os.

ENAI3LE ICD enables the BMC, to, give th,e Inter- ,
, nally Correct Data command to the ,FSAswhen an
error has been detected by the FSA's error detection
and correction circuitry. Ea.ch FSA responds to such
a command by internally cycling the data through its
error correcti,on network. When, finished, the FSA',
returns status to the BMC as to whether or not the
error is correctable. The value of ENABLE ICD af- '
fects the action of INTERFiUPT ENABLE (ERROR).

, FIFO READY has, two functions. The 'FIFO READY
'
'
,functions are as follows:
NOTE: IF RAC #- FIFO, FIFO READY
STATUS BITS
FIFO READY

.....; data in FIFO - FIFO empty -

Although the status word can be read at any time"the
status information, bit rthrough 6, is not valid until the'
BUSY bit is low.
STR Bits 1through 6 are reset when a new command is
issued. They may also be reset by, making a write request'(WR=O) to the BMC with Ao=l, 0.=0, and 0.=1
(Modified bit) (that. is, writing the RAC with 0s= 1).
This operation also resets the "INT" pin to "0". NOTE:
A byte of FIFO data can be lost when using this procedure if the RAC is written to other than the FIFO ad·
dress when data is still present in FIFO. '

Enable ,Register (ER) 8 Bits, Writ,e Only
The user sets' various bits' 'of' the enable register to
enable or disable various hinctionSiNithln the BMC or
the FSAs. The individual bit descriptions are as follows:

INTERRUPT ENABLE (NORMAL)
INTERRUPT ENABLE (ERROR)

ENABLE
.'
L~===:"DMA
MAXIMUM FSA·BMC.TRANSFER RATE
~-----_WRITE

BOOTlOOP ENABLE

'-----'--~'--_ ENABLE Reo
_ _ _ _ _ _ _ ENABLE lCD'

L-_~'__~

~-----:-----.

ENABLE RCD enables the BMC to give the Read, ,
Corrected Data command the FSAs when an" error
"1
has been detected. This causes each FSA to correct
the error (if possible) and also to transfer the corrected data to theBMC:The Read Corrected Data com"
, 'mand is als,() used to read, into the BMC data,
previously corrected by the FSA in response, to an
Internally Correct Data command. In either case,
when' the data transfer has'been completed, the
BMC reads each FSA's status to determine whether,
or not the error was correctable. In the case of an
uncorrectable error, bad data may have been sentto
the user. The value of ENABLERCD affects the action of INTERRUPT ENABLE (ERROR). '

ENABLE PARITY INTERRUPT

,In the a,bove figure and In the text below, the following
abbreviations are used:
ICD = INTERNALLY CORRECT DATA
RCD = READ CORRECTED DATA
UCE =; UNCORRECTABLE ERROR
CE =CORRECTABLE,ERROR
TE = TIMING ERROR

6·304

WRITE BOOTLOOP ENABLE (when = 1) enables
the bootloop to be written: If ,this bit is equal to
zero, and a Write Bootloop command Is received
by the BMC, the command is'aborted and the TIM'
ING ERROR bit is set in the STR:'
DMA ENABLE' (when;" "IJ enables the BMC to'
op.!lrate in DMA data vansfe(m'ode,using the DRQ'
and DACK signals in i,nteraction 'with a, DMA controller. When equal to zero; DMAENABLE sets up
the controller to support interrupt driven or polled'
data transfer.
INTERRUPT'ENABLE(ERROR) selects error c,ondi-"
tions under which the BMC stops commandexe·
cution and interrupts the tiost processor'(vla the
INT line). INTERRUPT ENABLE (ERFlOR) operates
In conjunction with ENABLE ICDand ENABLE
RCD.

mand, hence the requirement for 11 bits. All 11 bits
equal to zero specifies a 2048 page transfer.

Intenupt
Enable
(ERROR)

Intenupt Action

1
0
1
0
1
0
1

Interrupt on TE only
Interrupt on UCE orTE
Interrupt on UCE, CE, orTE
Interrupt on UCE or TE
Interrupt on UCE, CE, orTE
Not used
Not used

Address Register (AR) 16 Bits, Read or Write
The contents of the address register determine which
MBM group is to be accessed, and, within that group,
what starting address location shall be used in a data
read or write operation. The bit configuration is as
follows:

TE = Timing Error, CE = Correctable Error,
UCE = Uncorrectable Error.
INTERRUPT ENABLE (NORMAL) (when 1)
enables the BMC to interrupt the host system (via
the INT line), when a command execution has been
successfully completed (OP COMPLETE = 1 in the
STR).

ADDRESS REGISTER MSB

The contents of the block length register determine the
system page size and also the number of pages to be
transferred in response to a single bubble data ~ead or
write command. The bit configuration is as follows:
BLOCK LENGTH REGISTER MSB

BLOCK LENGTH REGISTER LSB

17161514131211101

1716 15 141 31211101

NUMBER OF FSA
CHANNELS (NFC)

--::ST:-:-A::RT::':IN-:-:G:-:A~D::':DR::E:::SSC-:W::I::TH::IN::-E::-:A~C:-:-H-:-:M::BM~-

Within each MBM there are 8192 possible starting address locations for a data read or write operation, hence
the requirement for 13 biis in the starting address.

Block Length Register (BLR) 16 Bits,
Write Only
.

--~--

MBM SELECT

ADDRESS REGISTER LSB

NUMBER OF PAGES TO BE TRANSFERREQ

The selection of the MBMs to be read or written is
speCified by AR MSB Bits 57. The BMCs interpretation of
these bits depends on the number of MBMs in a group,
which is specified by BLR MSB Bits 4-7.
Table 6 shows which MBM groups are selected in response
to given values for BLR MSB Bits 4-7 and AR MSB Bits 3-6.
A 4-megabyte system (8 MBMs) is represented, with the
FSA channels numbered 0 through F:

The system page size is proportional to the number of
magnetic bubble memory modules (MBMs) operating in
parallel during the data read or write operation. Each
MBM requires two FSA channels. Bits 4 through 7 of
BLR MSB actually specify the number of FSA channels
to be accessed.
The BLR LSB, together with the 3 least significant bits
of the BLR MSB, specify the number of pages to be
transferred .. Up to 2048 pages can be transferred in
response to a single bubble data read or write com-

Table 6_ Selection of FSA Channels
BLR ,MSB Bits (7,6,5,4)

AR MSB Bits

(7,6,!;)
000
001
010
011
100
101
110
111

Table 5. 4Mbyte System Page Size, Page Address Range, and Data Transfer Performance Configuration
BLR MSB
7 6 5 4

MBM Data Transfer Rate

FIFO Data Buffer (FIFO) 40 x 8 Bits, Read or
Write
The BMC FIFO is a 40-0yte ouffer through which data
passes on its way from the FSAs to the user, or 'from the
user to the FSAs. The FIFO allows the data transfer to
proceed in an asynchronous .and flexible manner, and
relaxes timing constraints,both to the FSAs and also to
the user's equipment. The user's system must, however,
meet the data rate requirements. When the BMC is busy
(executing a command) the FIFO functionsasa data
buffer. When the BMC is not busy, the FIFO is available
to the user as a general purpose FIFO.

FUNCTIONAL OPERATION
The IC components used in the bubble memory systems
have been designed with transparency in mind-that is,
a maximum. number of operations are handled. by the
hardware and firmware of these components.
Each four Megabit Bubble Memory (MBM) operates in its
own domain, and is unaffected by the number of bubble
memories in the system. The roles piayed by the MBM's
immediate support circuitry can be described as if the
system contained only one MSM module.

Data Flow Within the Magnetic Bubble
Memory (MBM) System (Single MBM
Systems)

mine whether i.t represents data from a 'good' loop. If it
does, the data bit is stored in the FSA FIFO. Error detection and correction is applied to each .block of 256 data
bits.
From theFSA FIFO, data is sent to the bubble memory
controller (BMC) .in the form ofa serial bit stream, via a
one-line. Oidirectional data bus (010). The data is multi,
plexed onto the 010 line, with data bits coming alternately from the A and B channels of the FSA. The BMC
outputs a SYNC pulse to the SElECT.IN input of the
FSA. The FSA responds by placing a data bit from the A
channel FIFO on theDiO line; One clock cycle later, a
data bit from the B Channel FIFO is placed on the blo
line. The BMC continues to output SYNC pulses, once'
every 20 or 80 clock cycles, each time receiving two data
bits!in return.
.
,
In the BMC, the data undergoes serial-to-parallel conversion, and is assembled into bytes, which are then placed
in the BMC FIFO, which can hold 40 bytes of data. From
this FIFO, the data bytes are written onto the user interface.
During a write operation, the data flow consists of the
corresponding operations in the reverse order.

INTERFACING REQUIREMENTS

During a read operation, data flows as fOllows: The
data from the MBM is input to the Formatter/Sense
Amplifier (FSA). Data from each channel (A channel or B
channel) of the MBM goes to the corresponding channel
of the FSA. In the FSA, the data is paired up with the corresponding bit in the FSA's bootloopregister to deter-

All communicatioris 'between the host rnicroprocessor,
and the bubble memory is performed through the 7224
BMC.. Below the general prinCiples are described, for
detailed guidelines please refer to the BPK 75 Manual.
First the hardware interfacing requirements and second
the software interfacing requirements are described.

Table 7. Detailed Command Descriptions

Initialize

The BMC executes the Initialize command by first interrogating the bubble system to
determine how many FSAs are present, then reading and decoding the bootloop'from each
MBM and storing the results in the corresponding FSA's bootloop register. All the parametric
registers must be prope'rly set up before issuing the Initialize command.

Read Bubble Data

The Read Bubble Data command causes data to be read from the MBMs into the BMC FIFO.
The selection of the MBMs to be accessed and the starting address for the read operation is
specified in the address register (AR). The block length register (SlR) specifies the number of
system pages to be read. All the parametric registers must be properly set up before issuing
the Read Bubble Data command.

Write Bubble Data

The Write Bubble Data command causes data to be read from the BMC FIFO and written into
the MBMs. The selection of the MBMsto be accessed and the starting address for the write
operation is specified in the address register (AR). The block length register (BlR) specifies
the number of system pages to be written. All the parametric registeri:i'must be properly set up
before issuing the Write Bubble Data command.

Read Seek

The Read Seek command rotates the selected MBMs to a designated page address location.
No data transfer occurs. The pOSitioning is such that the next data location available to be read
is the specified (i n AR) page address plus one. The Read Seek command may be used to reduce
latency (access time) in cases where information is available for the user to predict the
location of an impending read reference to the MBMs.

6-306

inter

7224
. Table 7. Detailed Command Descriptions (Continued)

Write Seek

The Write Seek command rotates the selected MBMs to a designated page address location.
No data transfer occurs. The positioning is such that the next data location available to be
written is the specified (inAR) page address plus one. TheWrite Seek command may be used to
reduce latency (access time) in cases where information is available for the user to predict the
location of an impending write reference to the MBMs.

Abort'

The Abort command causes a controlled termination of the command currently being
executed by the BMC. The Abort command will be accepted by the BMC (and is typically
issued) when the BMC is busy.

MBM Purge

The MBM Purge command clears all BMC registers, counters, and the MBM address RAM.
Furthermore, it determines how many FSA channels are present in the system and stores this
value in the 7224. The "INITIALIZE" command uses this command as a subroutine.

Read Corrected Data The Read Corrected Data command causes the BMC to read into the BMC FIFO a 256-bit block
of data from the FIFO of each selected FSA channel, after an,error has been detected. The data
cycles through the error correction network of the FSA. After the data has been read, the FSA
reports to the BMC whether or not the error was correctable. The Read Corrected Data
command is used only when the system is in error correction mode (ENABLE ICD or ENABLE
RCD set in the ER).
S'oftware Reset

The Software Reset command clears the BMC FIFO and all registers, except those containing
initialization parameters. It also causes the BMC to send the Software Reset command to
selected FSAs in the system. No reinitialization is needed after this command.

Read FSA Status

The Read FSA Status command causes the BMC to read the a·bit status register of all FSAs,
and to store this information in the BMC FIFO, The Read FSA Status command is independent
all paral11etric registers.

Read Bootloop
Register

The Read Bootloop Register command causes the BMC to reacl the bootloop register of ttie
selected FSA channels and to store this information in the BMC, FIFO. Twenty bytes are
transferred for each FSA channel selected.

Write Bootloop
Register Masked

Proper operation of the FSAs during data transfer to or from the MBMs requires that the
bootloop register contain exactly 270 logic 1s for each FSA bootloop register: The user may
select any subset of 270 "good" loops from the total number of available loops. As an alter·
native, the Write Bootloop Register Masked command may be used. This command counts the
number qf logic 1s and masks out the remaining 1s after the proper count has been reached.
The Initialize command uses this command as a subroutine.

Read Bootloop

The Read Bootloop command causes the BMC to read the, bootloop from the se,lected MBM,
and to store the ,decoded bootloop information in the BMCFIFO. The Initialize command uses
this command as a subroutin,e.

Write Bootloop

The Write Bootloop command causes the existing contents of the selected MBM's bootloop to
'be replaced by new bootloop data based on 40 bytes of information stored in the FIFO (the
user must actually write 41 bytes, where the 41st byte is all Os). Encoding of the bootloop data
is done by theBMC hardware.

Zero Access Read
Bubble Data

The Zero Access Read Bubble Data command functions exactly the same as the Read Bubble .
Data command except it must be preceeded by the Zero Access Read Seek command. The
parametric registers are written prior to the Zero Access Read Seek command and should not
be rewritten for the Zero Access Read Bubble Data command.

Zero Access Read
Seek

The Zero Access Read Seek command operates similiarly to the Read Seek command, but it
reads the first page of data from the MBM into the FSA(s) FIFO. This eliminates the first page
overhead involved in the Read Bubble Data command. The latency for the first page data is on·
Iy the time required to read the datafrom the 7244(S). The values written into the parametric
registers prior to the i,ssuance of the Zero Access Read Seek command are identical to those
written for a Read Bubble Data command. The seeking address for the Zero Access Read Seek
command is equal to the desired read address. The Zero Access Read Seek command in·
crements the Ad and decrements the BlR. Since the Zero Access Read Bubble Data command
expects this increment and decrement, it is used for this data transfer instead of the Read
Bubble Data command.

HARDWARE INTERFACE REQUIREMENTS
User Interface Signals

System Timing

A BMC is capable of processing data and of supplying the
required timing and control Signals f<;>r operating up to
eight Bubble Storage Units (BSUs), each of which is
capable of storing 512 kbytes of user data. A BSU consists of a 512 kbyte MBM and its five immediate IC support chips (i.e. a BPK 74 Kit).

As shown on the timing diagrams in the WAVEFORM
section the typical read/write cycle timing provides sufficient tolerance to allow most currently available
microprocessors tobe easily adapted to the BMC timing
requirements.

To use the BMC, the user has to write a "bubble memory
software driver".

The source, destination and function of the user interface signals are described in Table 1 in the data sheet.

User Data Transfer Rate Requirements
The maximum data rate for the user interface is a functionof the number of MBMs operated in parallel as
outlined in table 8. The rates listed must be considered
in relation to the data transfer mode (polled, interruptdriven, or DMA) to be implemented in order to be sure
that the host system software and hardware are capable
of keeping up with the data transfer. In other words, the
BMC requires the host CPU to be able to sustain the
maximum data rate transfer rate for the minimum data
transfer (e.g., for a one bubble system keep up the
transfer rate for at least 64 bytes = one page).

Table

User Data User Transfer Rate
Requirements

SOFTWARE INTERFACE REQUIREMENTS

The bubble driver is responsible for all the system interaction with the bubble memory controller and is intrinsic to the efficient and reliable operation of the bubble system. The driver accepts bubble memory commands and command execution parameters from the application program, controls and monitors command execution, and returns operational status information to
the application 'program at command completion. To
perform all of these operations, th,e bubble driver must
support the, bit/l:;lyte level of the bubble memory controller:s command and status registers and the
parametric registers that define the operating mode,
system configuration, and extent of the transfer.
The level of the software driver complexity is a function
of the specific application needs. Regardless, a set of
basic drivers must be developed that in turn are integrated into system at the appropriate level. If an application program is small and Simple, a basic bubble
driver maysimply be called from the main program. '

Number of
MBMs
Operating
in Parallel

Maximum Data Transfer Rate
Between BMC FIFQ and the
FSAs during Write
Bubble Data Commands

12.5 kbytes/second
25 kbytes/second
50 kbytes/second
100 kbytes/second

2
4
8

At the highest leyel 'of driver sophistication, the application program treats the bubble system as a collection of
named data areas of files similar to the way in which
data is stored and retrieved in disk operating systems.
At the file system level; an application program can ignore the' mechanics of bubble storage and access and
merely present a file name to the driver to open, read, or
write, then close the desired bubble file.

Hardware Interfacing for Data Transfer
The BMC supports three data transfer modes, i.e. DMA,
interrupt-driven and polled.
To support DMA, a hardware mechanism is required for
servicing the BMC's data transfer requests. While
several hardware implementations are pOSSible, one
common configuration is the Intel 8257 DMA controller.
To support an interrupt-driven system an Intel 8259 Programmable Interrupt Controller is often used.
The polled data transfer mode relies almost exclusively
on the software interaction between the host processor
and the BMC to control the transfer of data~

6-308

Data Org,anization
From a software viewpoint, data logically is organized
into blocks of bytes called pages. During data transfer
operations, one or more of these pages are transferred
between the bubble(s) and the host microprocessor. A
page is the smallest increment of data that can be
transferred; single bytes cannot be transferred. Conceptually, the data organization within a bubble memory is
analogous to a disk system. Just as disk sector sizes
are fixed when a disk is formatted, bubble page sizes are
established, under software control when the bubble
system is initializ~d.

inter
For single bubble system, the page size is fixed at 64
bytes with error correction. The' total number of pages
avaliable Is 8092. In systems with multiple bubbles, page
size can vary from 64 bytes to 512 bytes depending on the
number of bubble, devices in the system. Page size Is
directly proportional to the system data rate and also
determines the total number of available pages (address
field size). The selection of the appropriate page size
depends primarily on the data rate supported by the
system. The higher the data rate, the faster the
microprocessor must respond to the demands of the bub·
ble mem'ory controller.,

'Buffering
The bubble memory controller includes a FIFO data buffer that, although only 40 bytes,long, reconciles timing
: difference.s between the parallel data transfer to or from
the host microprocessor and the serial data transfer to
or from th,e. Bubble Memory Subsystem. Accordingly,
when an application program requests data from a bubble, the software driver is responsible for keeping up
with the FIFO, for the duration of the, data transfer in
order to prevent the FIFO from overflowing or
underflowing_
.

Command Execution
Command execution can be performed either in an interrupt driven mode or in a polled mode irrespective of the
data transfer mode' (polled, interrupt-driven, or DMA).

Error Correction
The bubble memory has a built-In error detection. Three
levels of error correction are available.

Communication with the BMC
All communications between the host and, the bubble
memory actually are performed through the BMC. The
BMC has two input/output (I/O) ports, an eight-bit
bidirectional data port, and an eight-bit command/status
port. Conceptually, a bubble memory system can be
thought of as a disk system in that data in the bubble
memory is organized Into blocks called pages in bubble
technology that are similar to disk sectors_ Information
s,uch as starting page location, direction of transfer, and
the number of pages to be transferred is passed to the
BMCbefore the desired read or write operation is
initiated.
The general procedure for communicating with theBMC
is:
Set-up the BMC for data transfer communication
by loading specific parameters in user-accessible
registers.
Send the desired command.
Read the status register to determine if command
is accepted_
.
,
If applicable, transfer (i.e., read or write) data.

Data Transfer Mode
'As described earlier in the hardware section, three data
transfer modes are available (polled, interrupt-driven or
DMA).
System performance, additional hardware and software
overhead are all important considerations when choos'
ing the appropriate mode for your appiication.

6·309

Read the status register until BMC is hot busy (or
under some conditions "INT" pin).
Examine the status register to determine whether
the operation was successful.,
For all details and exceptions to this general description
consult the BPK 75 User's Manual. (Available 1st Quarter
1984).

intel"

7224

ABSOLUTE MAXIMUM RATINGS
Temperature under bias .............. - 40 to + 100·C
Storage Temperature ............. - 65·C to + 150·C
All Input or Output Voltages and
Vee Supply Voltage ..................... -0.5V to 7V

·NOTlCE: Stresses above those listed under "Absolute Max·
Imum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated
In the operational sections of this specification Is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

D.C. CHARACTERISTICS
(TA

= Ot070·C, Vee = 5.0V +5%, ...,10%)

Output low Voltage
(All outputs except DET.ON, BUS.RD,
SHIFT.ClK, and SYNC

.45.

I.Ol = 3:2 mA

VOL(2)

Output low Voltage
DET.ON, BUS.RD, SHIFT.ClK, SYNC·

InputHigh Voltage (PWR.FAll)

High Voltage (all but PWR.FAll)

2.4

liN

Input leakage Current

Power Supply Current from Vcc

200

A.C. CHARACTERISTICS
(TA = 0 to 70·C, VCC

= 5.0V

Symbol

+ 5%, -10%; Cl

= 150pF; unless otherwise noted.)

Clock Phase Width (High Time)

.45 tp

.55 tp

tR·tF

Input Signal Rise and Fall Time

ns'

.0'
Test Condition

FSA INTERFACE TIMINGS (under pin loading)
Symbol

ClK to 010 Valid Delay

200

Under Pin loads·

tCDF

ClK to 010 Entering Float

250

Under Pin loads·

tCDE

ClK to 010 Enabled from Float

ClK to SYNC leading Edge Delay

200

Under Pin loads·

tCSOT

ClK to SYNC Trailing Edge Delay

150

UnderPin loads·

toc

010 Setup Time to Clock

Under Pin loads·

150

tOHC

010 Hold Time from Clock

Under Pin loads·

tCOl

ClK to Output leading Edge

0
200

Under Pin loads·

tCOT

ClK to Output Trailing Edge

SHIFTCL.:K to Y - Trailing Edge

A.C. CHARACTERISTICS (Continued) (TA = 0 to 70·C,Vcc
READ CYCLE (HOST INTERFACE)
Symbol

= 5.0 + 5%, -10%; Cl = 150 pF;

.unless otherwise noted.)

Data Delay from Address

Data Delay from DACK!

In non DMA mode.
t CYCR Min. = 6tp

WRITE CYCLE (HOST INTERFACE)
Min;

Request Hold from RD or WR
(Non-Burst Mode)

Inactive Time between WRt and WRI

4tp

tOEAOR

Inactive Time between ROt and RDI

150

ns
ns

7250·7234 INTERFACE TIMINGS
Symbol

ClK to Bubble Signal leading Edge

275

Under Pin Loads'

teBT

ClK to Bubble Signal Trailing Edge

275

Under Pin Loads'

'Bubble Pin Loads Shown Below
PIN LOADINGS
Pin Names

TM.A, TM.B, REP.EN, BOOT.EN,
SWAP.EN, BOOT.SW.EN, e/D,
ERR.FlG, WAIT, SYNC, 010

100

DET.ON & SHIFT.elK
BUS.READ

6·311

7224

WAVEFORMS
READ (HOST INTERFACE)

DACK - - " " " " \ . lL"""----+-~---...,..-------_

cs ----+. . . . 1I'--++---------+~
~--...,..--+~

WRITE (HOST INTERFACE)
t----'--------"',i.-~-------.,
DACK---~~----+-~-----------~r-_.......

,.--t--

----"'JI...,.._-++--...,..------.,-+...,..-"!iI. ,------""

,----1--

~----J ~--Hr---------_+~ ~...,.._--- .'---~--WIi

DATA BUS

J---__-"--.DW----~t--

WAVEFORMS (Continued)
7244 INTERFACE TIMINGS

7250 & 7234 INTERFACE TIMINGS

eLK

BUBBLE SIG.
7250 & 7230

6·313

, ':.i:,

General Information

PACKAGING INFORMATION

All dimensions in inches and (millimeters)

NOTES:
1. All packages drawings not to scale.

2. All packages seating plane defined by .0415 to .0430 PCB holes.
3. Type P packages only. Package length does not include end flash burr. Burr is .005 nominal, can be .010 max.
4. All package drawings end view dimensions are to outside of leads.

at one end.

PLASTIC DUAL IN-LINE PACKAGE TYPE P
16-LEAD PLASTIC DUAL IN-LINE
PACKAGE TYPE P

18-LEAD PLASTIC DUAL IN-LINE
PACKAGE TYPE P

20-LEAD PLASTIC DUAL IN-LINE
PACKAGE TYPE P

IOJS1!!.l!!I.

C""'"''''

-:IlimJ.

L,0trc-rrTTTT"rn;-nTTTTm',~

'''''' Loo,..J *'"
110160)

24-LEAD PLASTIC DUAL IN-LINE
PACKAGE TYPE P

PACKAGING INFORMATION

All dImensIOns

Inches and (millImeters)

PLA~)TIC DUAL IN-LINE PACKAGE TYPE P
28-LEAD PLASTIC DUAL IN-LINE
PACKAGE TYPE P

40-LEAD PLASTIC DUAL IN-LINE
PACKAGE TYPE P

CERAMIC DUAL IN·LlNE PACKAGE TYPE D
16-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D

·79(){20.0661.~
.750 {19.050}

~~~"'I---1
.210(5.080)
MAX.

.~~;;;:::;;~a---;---T

"SE;;;:A",TI",NG,,--_+-_,,(
PLANE

MIN
.032 TYP.
(0.8131

F'A~KAGI~G INFORMATION All dimensions in inches and (millimeters)

CERAMIC DUAL IN·LINE PACKAGE TYPE D
24-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D

~~n~~L~tJ .185 (4.699)

MINJ4O(3·~!2~r ~. fa-

(.50B)

. 12513.1751,_--,,-~,
MIN.

1---·

.016 (0,406)

MAX .
(17.780)
NOTE 4.

28-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D

'.Iffi=r;=r;=r;.-- -.=·_=-=r··"FF"H"lNfl-.--O:".. '7S(4.44S)

28-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D

~ __II .....020 (0.508)

.600 (15.240J
.515113.081)

I
.OB~~~5B)
('5.748)
:-----;:===::..,1
_
Mo;~
[
::g
.
10.2.41
(' S.240)
._'85_(3_.558_)
~-=1:~nrn~~~'] .,40
(4.669)
----.-:
.010 TVP.
,.L
L.'f.~\N. 102541
'--i R~~.

.032 TVP.

L J

-I1-.~1050BI
016(04061

HERMETIC DUAL IN-LINE
PACKAGE TYPE D

·2.aBO 152.8321~
2:030 (5,.5621

---

PIN 1

f
.600 (15.240)
.515 113.0811

I-.11012.7941
.090 12.286)

PACKAGING INFORMATION

All dimensions in Inches and (mililmeiers)

CERAMIC DUAL IN·LINE PACKAGE TYPE D
.920 (23.0001

18-LEAD HERMETIC DUAL IN-LINE'
PACKAGE TYPE D

C_·:0~~3~21

.31017.8741
.265 (6.731)

~~"""""~
.210(5.080)
MAX.

(20.320)

t~-IrI;;;r;;:;r;:;r;.;

20-LEA~ HERMETIC DUAL IN-LINE
PACKAGE TYPE D

:;~f1flj1J,='ll==It :~:~:;~:~:
:.:1

'.~"'PLC;A"'N"E'--+--V
•12513.1751
MIN.

.990(25.146) ~
:950(24.1301

:=rJr~w[:i==II
'
=
1 - ,,~14.191l
.'4013.556)ti

Oll)yV~.~·" ,"":-..l~ 10
400
'!' REF•
'1-- MAX. -I

-r;,SMIN. .
10.381)
(0.254). :

. 110(2.7941

22-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D

't' (~~) j

.020 10.508)
.01.10.406)

(10.160)
NOTE 4 .

1.095127.8131 ~
1.060 (26.924)
PIN 1

. 110 (2.794)
.090 (2.286)

24-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D

-----J .
._
~~I
-1
.600 (15.240)
.515 (13.081)
(15.746)'

--;----{- .175(4.445)
~ .140(3.556)

lO2OMIN
(.506)

I .

-- ...... 020 (0.508)

.01. 10.406)

7·4

1'- . : . . l·
r(15~("

PACKAGING INFORMATION
CERAMIC DUAL IN-LINE PACKAGE TYPE C
24-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C

1.215 (30.861}

~ 1.185/30.0991
l_~__
.
-=.

.....~~~~- =
.210 (5.334)
110(2.794)

All dimensions in inches and (millimeters)

1.100 REF.
(27.940) -

±-.

.100(2.540)
.075(1.905)

+Eit2~ 1~

n~ LC"= ~="=~~~p:::~~~~:OTYP·

SEATING
PLANE

.0SO/.04OlYP.
(1.270)/(1.016)

1415(35941)
1355135179)

-=-

- =
210 (5 334)

OSO/ 040 lYP.
(1 270)/(1 016)

,090(2.2861

CERAMIC LEAD LESS CHIP CARRIERS
18-LEAD CERAMIC LEAD LESS
PACKAGE TYPE F

CERAMIC FLAT PACK PACKAGE TYPE CF
18-LEAD HERMETIC FLAT PACK
PACKAGE TYPE CF

28-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C

lSO (3 810)
090(2286)'
060 (1524)
010 TY. -.
___

PACKAGING INFORMATION

All dimensions in inches and (millimeters)

CERAMIC DUAL IN·LlNE PACKAGE TYPE C

r--

16-LEAD CERAMIC DUAL IN-LINE
PACKAGE TYPE C

1_ _ _ _

810 (2Q 574)
790 (2Q (66)

. - - - ·(17.780)' - - - , -

.110(2.794)

L JlJI

• •~:=:;:='===
SEATING

=.;PL"'A';;;NEc=-----t--)

(1.270)

1 .

.910 (23.114)
890 (22.606)

CERAMIC DUAL IN·LlNE PACKAGE TYPE C
20-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C

1.010 (25.654)
Jj9cJ(25.146)

.025 (0.635)
.~ (0.5581

.095(2.413)
.075 (1.905)

===t~:115(2.921)
~ .050 (1.270)

.165 (4:191)
.110(2.794)

.015(0.381)
.11012.794)
(2.286)

,_-----'L----' .085 (2.159)

.050 TVP.

18-LEAD HERMETIC DUAL
PACKAGE TYPE C

~ 050 (1 270)
025 (0 635)

~~~:~ ~:::

Eta

100(2.540)
075 (1.905)

PACKAGING INFORMATION
CERAMIC LEAD LESS CHIP CARRIER
20-LEADLESS HERMETIC CHIP CARRIER
JEDEC PACKAGE TYPE F

28-LEAD CERAMIC LEAD LESS
PACKAGE TYPE C

32-LEAD CERAMIC LEAD LESS
PACKAGE TYPE E

32-LEAD CERAMIC LEAD LESS
PACKAGE TYPE E
.

7-7

All dimensions in inches and (millimeters)

BUBBLE LEAD-LESS PACKAGE AND SOCKET
lQ.92;!;O.13

BUBBLE LEAD-LESS PACKAGE AND SOCKET
BUBBLE SOCKET #7905

(-----~

7-9

1MBIT LEADED BUBBLE MEMORY PACKAGE
TOP VIEW

END VIEW

/ + - - - - - 1 ·.. - - - - - · 1

SIDE ViEW

/1--'_ _ "35 _

'~
I.015RAD'+US

'~t13~;::'-::=========
-

P.C. BOARD SPACE REQUIREMENTS

.200 DIA.(4J1)
FAR SIDE OF
BOARD

p.e.

KEEP CLEAR OF TRACES

7-10

,.094 ± .003 DIA. (4xl
NON PLATED HOLE

4MBIT BUBBLE MEMORY PACKAGE
TOP VIEW

.-=-=-==-=-=-=-=-==-=-=-=-=-==---,

-t-

L
r

"-"1"'."
----------------

-----------------

END VIEW
IDENTIFICATION LABEL

=-=--=-=--=-=--=-=--=-=··~T.---'---t

L"J=I..

-SEAT'NG"'N'

-:!,'-.015(20):)

P.C. BOARD SPACE REQUIREMENTS
.031 ~ .003 OIA 120X)
PLATED THRU HOLE

7-11

PACKAGING,INFORMATION All dimensions in inches and (millimeters)
7264 (PART OF 4MBIT BUBBLE MEMORY SYSTEM)

,020 (0.51)
.055 (1.39)

PIN 1 - Gate
PIN 2& TAB - Drain
PIN 3
Source
.080

.500 (12.70)
.580 -(14.73)
CIA 0.161
0.139

EXPRESS PRODUCT FAMILY

EXPRESS PRODUCT MANUFACTURING FLOWS

HERMETICITY
QAMONITOR

OPTICAL INSPECTION:
CONTAMINATION
PARTICAL COUNT
CRITICAL DIMEIjSIONS

SOLDER DIP
QAMONITOR

TEMPERATURE CYCLE
QAMONITOR

DEFLASH,
TRIM,
FORM
QAMONITOR

OUTGOING
ACCEPTANCE

WAFERSDRT
DC, AC, FUNCTIONAL

OPTICAL INSPECTION:
SORT DEFECTS

MOLD
QA MONITOR

PLASTIC

SCRIBE AND BREAK

BURN IN FLOW:
168~8 HRS,@ 12S-·C
DYNAMIC
(N/A FOR T PRODUCTS)

PRECAP VISUAL
LOT ACCEPTANCE

WIRE BOND
QA MONITOR
LOT ACCEPTANC~
LEGEND

o MANUFACTURING

o TEST OPERATION

DIE ATTACH
QA MONITOR
LOT ACCEPTANCE

7-13

QUALITY ASSURANCE
LOT ACCEPTANCE

QUALITY ASSURANCE OPERATIONS

PACKAGE TECHNOLOGY

PROCESS TECHNOLOGY

Reliability: Process Qualification
MaterialsTest Methods
Materials Characterization

WAFER FABRICAT
, Reliability: Generate Design Rules
Generate Test Pattern
Process Qualification
Stress Testing
Failure Mode Analysis
Quality:

PRODUCT DESIGN

Incorning Inspection
. High Magnification \

Reliability: Process Qualificatio
Process Control, Me
Analytical Test Labo:

Quality: Parameter Limits, Testability
Test Program Control
Target Specification

PRODUCT VALIDATION/QUALIFICATION

Design Engineering:
Design Engineering:
Applications Engineering:
Quality/Reliability:

7·14

Design Verification
Perforrnance Verification
Systern Verification
Qualification

Quality: Incoming Inspection Gates
High/l.,ow Magnification Visual Gates
Assembly Q.A. Acceptance
External Visual
Fine/Gross Leak®
Centrifuge
Acoustic (PIND)
MarK Permanency

Open/Short Test
Bond Pull
Die Shear
X-Ray
Internal Visual

Reliability: Process Qualification
Assembly Monitor Program
:es
II Gate

rValidation
'Y

TEST AND FINISH

ASSEMBLY MONITOR PROGRAM

Quality: Final Q.A. Acceptance
Electrical Test Sample
Soiderabiiity
Mark Permanency
External Visual
Fine/Gross Leak®
Lid Torque
Temp/Humidity®.
Moisture Resistance®

Internal Visual
Temperature Cycle
Thermal Shock
Steam

Physical Dimensions
External Visual
Conformance to Sales Order

Reliability: Reliability Monitor Program

PLANT CLEARANCE
48 Hr, 125°C Dynamic Burn-In
1000 Hr, 125°C Dynamic Lifetest
NOTES:

® Hermetic packages, only.
®. Plastic packages, only.

Quality: External Visual
Sales Order Requirements

Enclosed is my check for $

payable to INTEL CORPORATION.

Please enroll me in the following workshop(s):

"",

Workshop(s)

Date(s) -'-_ _ _ _ _ _--,-_ _

Confirmation number(s): _ _ _ __
Name: _ _ _ _ _ _ _ _ _ _ _ Tel. No. _ _ _ _ _ _ _ _ _ __

II'

Please put correct mailing address on reverse:side.
, D Please keep me on your mailing list.
D Please remove my name from your mailing list.

I
.,

BOSTON AREA
Intel Customer Training
27 Industrial Ave.
'
Chelmsford, MA 01824
(617) 256"1~74 ",'
WASHINGTON D.C. AREA
Intel Customer Training
7833 Walker Dr., 5th FI.
Greenbelt, MD 20170
(301) 474-2878

CHICAGO AREA
Intel Customer Training
Gould Center, East T()wer
2550 Golf Rd., Suite 815
Rolling Meadows, IL 60008
(312) 981-7250

....

, ,SAN FRANCISCO AREA
; 'Intel Customer Training
1350 Shorebird Way
Mt. View,cA 94043,

, DALLAS AREA
Intel Customer Training
12300 Ford Road, Suite 380
Dallas,TX 75234
(214) 241-8087 '

CANADA
Intel Custon1er'Tr'aining
190 Atwell Drive
Toronto, Ontario M9W 6H8
(416) 494-6831

(415)940-~800
,'."'

LOS ANGELES
Intel Customer Training
Kilroy Airport Center
2250 Imperial Highway
EI Segundo,CA 90245
(415) 940-7800
,

, .....

Registration
To enroll, call theapptopriate Intel Training Center between the hours of 8:30-12 and 1-4:30 and
ask for Customer:Training. Since enrollment is limited, registration 4-:8 weeks in advance is .
,
'
recommended:' '
Confirmation No: _ _ _ _ _ _ _ _ _ _ _~Your confirmation number, issued upon registration, guarantees your enrollment.
Payinent:
Check' or money order payable to Intel Corporation is due before workshop begins. To ensure proper
credit, please include your enrollment confirmation 'number with your payment and send to the
appropriate training Cente"r.' .
"
"
--Workshop Hours: Workshops begin at 8:30 a.m. and end at,approximately 5:00 p.m.

The best training you can get your hands on.
,7-16

Intel Workshop Schedule 1984

iAPX 86, 88, 186
Part I P. 8
iAPX 86, 88, 186
Part II P. 9
iAPX 286 Microprocessors
P.10

Other Areas
De
M
N

Denver
Minneapolis
New York

Calgary
Ottawa
Toronto

Canada

0
T

Area

Call
312-981-7250
312-981-7250
301-474-2878

C Chicago

Call

0 Dallas

416-494-6831
416-494-6831
416-494-6831

L Los Angele.

B BOllon

S San Francisco
W Washington, DC

7-17

USA Training Center
27 Induslrial Ave.,
Chelmsford, MA 01824
2550 Golf Rd., Suite 815,
Rolling Meadows, IL 60008
12300 Ford Rd., Suite 380,
Dallas, TX 75234
2250 Imperial Hwy.,
EI Segundo, CA 90245
1350 Shorebird Way,
Mt. View, CA 94043
7833 Walker Drive, 5th FI ..
Greenbelt, MD 20770

Telephone
617-256-1374
312-981-7250
214-241-8087
415-940-7800
415-940-7800
301-474-2878

Workshop Tuition

"Ethernet is a trademark of Xerox Corp.; Ada is a Registered Trademark of the Ada Joint Program Office-US Government; XENIX is a trademark of
Microsoft Corp.

7-18

inter
DOMESTIC SALES OFFICES
ALABAMA
Intel Corp.
303 Williams Avenue, S.W.
Suite 1422
Huntsville 35801

Tel: (205) 533-9353

ARIZONA
Intel Corp.
11225 N. 28th Drive

Suite 2140

Phoenix 85029
Tel: (602) 869·4980
CAUFORNIA
Inlel Corp.

IWNOIS

NEW IIEXICO

1EXAS

Inlel Corp."
2550 Golf Road
Suile 815
Rolling Meadows 6000B

Inlel Corp.
1120 Juan Tebo N.E.

Inlel CorP,12300 Ford Road
Suite 380
Daltas 75234

~:(3~f6.6~~~5~2B~

Inlel Corp.
9100 Purdue Road
Suite 400
Indianapolis 46268
Tel: (317) 875-0623

Cedar Rapids 52402

r7~~) DJ~~35~2dl1
Intel Corp.-

2000 East 4th Street
Suite 100

Santa Ana 92705

~: (7Ji6_5~1:1~~2
Intel Corp,1350 Shorebird Way
MI. View 94043

~: (4J~6_3~~~9~~~6
910-338-0255
Intel Corp,5530 Corbin Avenue
Suite 120
Tarzana 91356

~: (2Jf6.41~~~~3
COLORADO

Intel Corp.

~J30Ans;~~nd~:~i"8rive

U .....
Intel Corp.
8400 W. l10th Street
Suite 170
OVerland Park 66210
Tel: (913) 642-8080

Industrial Digital Systems Corp.
2332 Severn Avenue
Suile 202
MetairIe 70001
'
Tel: (504) 831-8492

MARYlAND
Intel Corp."'

~~~:ra~d'16 Drive

~:{3~,~1s~~~~
Inlel Corp.
1620 Elton Road

¥~7:e\3gr,rl"231~~~3

Colorado Springs 80907

Inlel Corp."
27 Industrial Avenue
Chelmsford 01824

650 S. Cherry Street
SuUe 720
Denver 80222
Tel: (303) 321·8086
TWX: 910-931-2289

~:(6ii6_3~~:

~~5C E~T·Street

CONNECTICUT

Newton 02164
Tel: (617) 244-4740
TWX: 922531 '

Intel Corp.

MICHIGAN

36 Padanaram Road
Danbury 06810

~: (2~lJ...~~:11i:6

~J%lo?NP~westerri.' Hwy,

Suite 401
Southfield 48075

EMC Corp.
393 Center Street

~: (3Jr6_2~~4~~0

FLORIDA

Intel Corp.
3500 W, 80th Street
Suite 360

~~~li(rg3? g6~91

~~~. ~\e:

6200 Street
Suite 104
FI. Lauderdale 33309
Tel: (305) 771-()600
lWX: 510·956·9407

~nJ~ ~~altland
Suile 205
Mailland 32751
Tel: (305) 628·2393
lWX: 810-853·9219

OiEORGIA
Inlel Corp.
3300 Holcombe Bridge Road
Suite 225
Norcross 30092
Tel: (404) 449-0541

~7~~r:~~Ns~2

Intel Corp.
4203 Earth City Expressway

63045
Tel: (31,tr 291-1990

NEW JERSEY

::r!ta~~~

T.S~uared .

~:acu~di~~~~oad
~: (3ir6.~~~~~2

VlcIor Road
VICtor 14564

~: (7Jf~29~~~Od

NORTH CAROLINA
Intel Corp,
2306 W. Meadowview Road
Suite 206
Greensboro 27407
Tel: (919) 294·1541

OHIO
Inlel Corp."
6500 Poe Avenue
Dayton 45414

~:{5JrL~~~~~~O

~~~8'~Ee;nard

Bldg., 'No. 300
. ~~~la~hag~r22BOUlevard

~:(2Jf6-4~~~9~~W
OKLAHOMA
Inlel Corp.
4157 S. Harvard Avenue
Suite 123
Tulsa 74135
Tel: (918) 749-8688

OREGON
Inlel Corp
10700 S.W. Beaverton
~~:a~2 Highway

~:(58,3J..t~~B~~~6
PENNSYLVANIA
Intel Corp.510 Pennsylvania Avenue
Fort Washmgton 19034

~:(2Jr6_:,~~m?

MISSOURI

Raritan Center
EdisOfl 08837

Intel Corp."
211 White Spruce Boulevard
Rochesler 14623

4445 Northpark Drive
Suite 100

Tel: (303) 594-6622

~ug~~~~on12~~t

Tel: (914J 473·2303
TWX: 510-248-0060

Suile 300
Sacramenta 95825
Tel: (916) 9294078

NEW YORK
Inlel Corp."
300 Vanderbilt MOlar Parkway
Hauppau~e 11788
Tel: (516 231-3300
lWX: 51 -227·6236

Intel Corp,"
201 Penn Center Boulevard
Suile 301W

f~~b~U:p~ 152~31970

~/2J16-8ib'.tgN
Inlel Corp.7322 S.w, Freeway
Suite 1490
Houston 77074

~: (7Jr6-8~~~~g~6

Industrial Dlgllal Systems Corp.
5925 Sovereign
Suite 101
Houston 77036
Tel: (713)988-9421

~~~I

€,°'Xnderson Lane
Suile 314
Auslfn 78752
Tel: (512) 454-3628

UTAH
Intel
268
SaH
Tel:

Corp.
West 400 South
Lake City 84101
(801) 533-8086

VIRGINIA
Inlel Corp,
1603 Santa Rosa Road
Suite 109
RIchmond 23288
Tel: (B04) 282-5668

WASHINGTON
Intel Corp.
110 1101h Avenue N.E.
Suite 510
Bellevue 9B004

~:(28fJ4~~~~~6
WISCONSIN
Intel Corp.
450 N. Sunnyslope Road
Suile 130
Brookfield 53005
Tel:, (414) 784-9060

CANADA
ONTARIO
Intel Semiconductor of Canada, Ltd.
39 Hwy, 7, - Belt Mews
Nepean K2H 8R2
Tel: (613) 829-9714
TELEX: 053-4115
Inlel Semiconductor 01 Canada, Ltd,
50 Galaxy Boulevard
Suite 12
Rexdale M9W 4Y5
Tel: (416) 675-2105
TELEX: 06983574
Intel Semiconductor 01' Canada, Ltd.
201 Consumers Road
Sulle 200
Wittowdale M2J 4GB
Tel: (416) 494-6831
TELEX: 4946831

QUEBEC
Inlel Semiconductor of Canada, Lid.
3860 Cote Vertu Road
Suile 210
SI. Laurent H4R 1V4
Tel: (514) 334-0560
TELEX: 05-824172

Q.E.D. Electronics
III

300 N. York Road
Halboro 19040
Tel: (215) 674-9600

~:(2~N}-4~~~~~
·Fleld Application Location

DOMESTIC DISTRIBUTORS
ALAlIA""

CALIFORNIA

tArrow Electronics, Inc.
3611 Memorial Parkway So.
Huntsville 35405

tWyle Distribution Group
9525' Chesapeake Drive
San Die90 92123
Tel: (714),565-9171
l'iVX: 910-335-1590

tArro..y Electronics, Inc.
Tel: (312) 397-3440
TWX: 910-291·3544

~: (6Jf6_5~~311~~0

t~6e =i~ut~~n~~oup

tHamillon/Avnet Electronics
1130 Thorndale Avenue
Bensenville 60106
Tel: (312) 86Q.-7780
l'iVX: 910·227-0060

tHamiiton/ Avnet Electronics
10300 Bren Road East
Minnetonka 55343
Tel: (612) 932.Q600
TWX: (910) 576-2720

Tel: (205) 882·2730
tHamiiton! Avnel Electronics
4812 Commercial Drive NW.
Huntsville 35805
Tel: (205) 637-7210
TWX: 810-726-2162

tPioneer/Huntsvil1e
1207 Putnam Drive NW.

Huntsvme 35805
Tel: (205) 837·9300
TWX: 810-726-2197

ARIZONA

(Cont'd)

Santa Clara 95051
Tel: (408) 727-2500
TWX: 910-338-0296

MINNESOTA

IWHOIS

tArrow ElectroniCS, Inc;
5230 W. 73rd Street
Edina 55435

~~~u~b~~~on~~~5 Street

tWyle Distribution Group
17872 Cowan Avenue
Irvine 92714
Tel: (714) 641-1600
l'iVX: 910·595-1572

tPioneer!Twin Cities
t0203 'Bren Road East
Minnetonka 55343

tWyle Distribution Group
451 E. 124th Avenue
Thornton 80241
Tel: (303) 457-9953
l'NX: 910-936-0770

tArrow Electronics, Inc.
2718 Rand, Road
Indianapolis 46241

tArrow Electronics: Inc.
2380 Schuetz
S1. louis 63141

Wh?: ~i~5~n119

~:(3J:6_7~~~ri8~~8

Tel: (602) 249-2232
TWX: 910·951-4282

tHamiiton/Avnet Electronics
8765 E, Orchard Road
Suite 708
Englewood 80tl1

tHamiiton/Avnet Electronics
485 Gradle Drive
Carmel 46032

CALIFORNIA

fWx:{3~13~9j~~Oj~V

tHamiltonfAvnet Electronics
13743 . Shoreline Court
Earth C~' 63045 ,
Tel: (314 344·1200
TWX: 91 -762-0684

tHamillorl/Avnet Electronics
505 S. Madison Drive
Tempe 85281
Tel: (602) 231-5140
TWX: 910-950-0077

~~e N~iS%l~~~~~roup
Phoenix 85021

tArrow Electronics, Inc.
19748 Dearborn Street
Chatsworth 91311

~:(2J~6}9~~J~
tHamiiton/Avnet Electronics
350 McCormick Avenue
Costa Mesa 92626

Tel: (714) 754-6051
TWX: 910-595-1928

tHamiiton/Avnet Electronics
19515 So. Vermont Avenue
Torrance 90502

~:(2J~~3~1i.:2~

tHamilton/Avnel Electronics
1175 Bordeaux Drive
Sunnyvale 94086
Tel: (40B) 743-3300
TWX: 910-339-9332
tHamiiton/Avnet Electronics
4545 V~rldge Avenue
San Diego 92123

~:(7Jn_5S:5~i~ig
tHamihon/Avnet Electronics
~~~r ~ityw~~nton Boulevard

~:(2JiU~~~~
tHamilton Avnet/Electronlcs
21050 Erwin Street
Woodland Hills 91367

COHNEcnCUT
tArrow Electronics,' Inc.
12 Bellumont Road

~:(3~i6_2~~;~~~0

~tlli{~~;r 2~-~~41·

l'iVX: 710-476-0162
tHamltton/Avnet Electronics
Commerce Industrial Park
Commerce, Drive
Danbu
06810

~: (7Jn_5~~iJsog

tHamillon/Avnet Electronics
4103 Northgate Boulevard
Sacramento 95834
Tel: (91S) 920-3150
KlerulN Electronics, Inc.

~~ ~

smgare

Road

iWx:(~f~3=~2
14101 Franktin Avenue
Tustin 92680

~; (7Jf6_5~~~~l~J

~:(Hti:%~~~

or 7111

KAN....
tHamilton/Avnet Electronics
9219 Qulvera Road'
Overland Park 66215
Tel: (913) 888·8900
l'iVX: 910-743-0005

NEW JERSEY

MARYLAND

tArrow Electronics, Inc.
2 Industria! Road
Fairfield 07006
Tel: (201) 575-5300
l'iVX: 710·998-2206

FLORIDA

t~o~~ I~g~~~~~rivc:rporation

tArrow Electronics, Inc:
1001 N.w. 62nd Street
Suite 108
Ft. Lauderdale 33309
Tel: (305) 776-7790
l'iVX: 510-955-9456

r~:th(£~~)r~4~~fIloTWX'

tHamiMon/Avnet Electronics
1 Keystone Avenue
Bldg. 36
.'

~: (2~fJ_4~~~31~~

tArrow Electronics, Inc.
50 Woodlake Drive W.
Bldg. B
Palm Bay 32905

710-828-9702

tHamilton/Avnet Electronics
10 Industrial
Fairfield 07006
Tel: (201) 575-3390
TWX: 710-734-438B

MASSACHUSETTS
tArrow Elec.tronics,. Inc.
t Arrow Drive
Woburn 01801

tHamiiton/Avnet Electronics

~:(6ji6_3~~~~t;g

Tel: (305) ,971·2900

tHamilton/Avnet Electronics
50 Tower Office Park
Woburn 01601
.
Tel: (617).935-9700
TWX: 710-393-0382

~Ola~d'Zrd~I;1h3~O~·

TWX: 510-956-3097

tPioneer/Alta Monte Springs
221 N. Lake Blvd.
Suite 412 '

~:~glt~~~~!o 32701

tPioneer/F1. Lauderdale
1500 62nd Street N.W.
Suite 506
FI. Lauderdale 33309
Tel: (305) 771-7520
TWX: 510-955-9653

t Arrow Electronics, Inc
2979 Pacific Drive
Norcross 30071
Te!: (404) 449-8252
TWX: .810-766-0439

tPioneer/Georgia
58358 Peachtree Comers E
Norcross 30092
Norcross 30092
Tel: (404) 448-1711
TWX: 810-766-4515

~~r760~;" 4~Bf>.8{10

TWX: 710-940-0262

~: (3gf~9~~s1~~0

tHamiiton/Avnet Electronics
5825 D. Peachtree Comers
Norcross 30092
Tel: (404) 447-7500
TWX: 810·766..0432
tWyIe Distribution Group
124 Maryland Street

tArrow Electronics, Inc.
t Perimeter Road
Manchester 03103
Tel: (603) 668-6968
TWX; 7tQ.-220-1684

tHamiiton/Avnet Elo;ctronics
6822 Oak Hall Lane
Columbia 21045
Tel: (301) 995-3500
TWX: 710-862-1861

~:{27rJ.41r~~~0
tHarvey' Electronics
112 Main Street
Norwalk 06851

GEORGIA

Kierutff Electronics, Inc.

NEW HAMPSHIRE

tArrow' Electronics. Inc
Pleasant Valley AVenue
Moorestown 08057
Tel: (215) 928:1800
TWX: 710·897-0829

~:(2JiL~:2~~
tHamilton Electro Sales
3170 PLJllman Street
Costa Mesa 92626

~: (3~i6'2~~3~~~3
tPioneer/lndiana
6408 Castleplace Drive
Indianapolis 46250

tHarvey/Boston
44 Hartwell Avenue
Lexington, 02173
Tel: (617) 863-1200·
TWX: 710-32,6-6617

tHarvey Electronics
45 Route 46
Pinebrook 07058
Tel: (201) 575-3510
TWX; 710-734-4382
tMTI Systems Sales
383 Route 46 W
Fairffeld 07006
Tel: (201) 227·5552

NEW MEXICO
tAliiance Electronics Inc
11030 Cochiti S.E.
Albuquerque 87123
Tel: (505).292-3360
TWX: 910-989·1151

MlCHIGAN

i~~O A~:ity48~~ve

tHamillon/Av~et Electronics
2524 Baylor. Drive, S.E
AlbUQuerque 8710S
Tel: (505) 765·1500

Tel: (313) 971-8220

TWX:

tArrow Electronics" InC.

TWX: 810-223-6020

tArrow Electronics, Inc
900 Broad Hollow Road
Farmingdale 11735
Tel: (516) 694-6800

tHamillon/Avnet Electronics
32487 Schoolcraft Road
Livonia 48'50

~: (3Ji6_2~~~-V7~0

910~989-0614

NEW YORK

tPioneer/Michigan
13485 Stamford
livonia ,48150
Tel: (313) 525·1800
TWX: 810-242-3271

tHamilton/Avnet Electronics
2215 29th Street S.E.
Space A5
Grand Rapids 49508
Tel: (616) 243-8805
TWX: 810-273-6921

TWX:

51
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1984_Intel_Memory_Components_Handbook 1984 Intel Memory Components Handbook

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