1984_Intel_Memory_Components_Handbook 1984 Intel Memory Components Handbook

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MEMORY COMPO'NENTS
HANDBOOK

1984

Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which rnay appear in
this document nor does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local sales office to obtain the latest specifications before placing your order.
The following are trademarks of Intel Corporation and may only be used to identify Intel Products:
BITBUS, COMMputer, CREblT. Data Pipeline, GENIUS, i, ~, ICE,iCS, iDBP,
iDIS, 12 1CE, iLBX, im , iMMX, Insite, Intel, intel, intelBOS, Intelevision, inteligent
Identifier, inteligent Programming, Intellec, Intellink,. iOSP, iPDS, iSBC, iSBX,
iSDM, iSXM, Library Manager, MCS, Megachassis, MICROMAINFRAME, MULTIBUS, MULTICHANNEL, MULTIMODULE, Plug-A-Bubble, PROMPT,
Promware, QUEST, QUEX, Ripplemode, RMX/BO, RUPI, Seamless, SOLO,
SYSTEM 2000, and UPI, and the combination of ICE, iCS, iRMX, iSBC, MCS, or
UPI and a numerical suffix.
MDS is an ordering code only and is not used as a product name or trademark. MDS") is a registered trademark of Mohawk Data
Sciences Corporation .
• MULTIBUS is a patented Intel bus.
Additional copies of this manual or other Intel literature may be obtained from:
Intel Corporation
Literature Department
3065 Bowers Avenue
Santa Clara, CA 95051

© INTEL CORPORATION,

1983

Table of Contents
Alphanumeric Index ...................................................................... v

CHAPTER 1
Memory Overview . ................................................................. 1;1

CHAPTER 2
Intel Memory Technologies . ................................................. _..... "

2-1

CHAPTER 3
RAMs (Random Access Memories)
APPLICATION NOTES
. AP74 High Speed Memory System DeSign Using 2147H .......... '........... ; ... 3-1
AP131 Intel 2164A 64K Dynamic RAM DeviceDescription ........................ 3-22
AP132 Designing'Memory Systems with the 8K x 8 iRAM (2186/87) ................ 3-40
AP133 Designing Memory Systems for Microprocessors Using
the Intel 2164Aand 2118 Dynamic RAMs ................................ 3-70
AP46 Error Detecting and Correcting Codes Part 1 : .......................... 3-110
AP73 ECC#2 Memory Systems Reliability with ECC .......................... 3-123
ARTICLE REPRINTS
.
AR189 Keep Memory Design Simple Yet Cull Single-Bit Error ................... 3-168
AR197 Better Processor. Performance Via Global Memory (2164A) ................ 3-176
AR274 The Cilip that Refreshes Itself ....................................... 3-183
DATA SHEETS
2114A, 1024 x 4-Bit Static RAM ............................................. 3-192
2115A/2125A Family, High Speed 1Kx i.-Bit Static RAM ... ; .................... 3-196
2115H/2125H Family, High Speed 1K x i-Bit Static RAM ........................ 3-201
2147H, High Speed 4096 x i-Bit Static RAM .................................. 3-206
2148H, 1024 x 4-Bit Static RAM ............................................. 3-210·
2149H, 1024 x 4-Bit Static RAM ............................................. 3-215
2164A Family, 65,536 x i-Bit Dynamic RAM ................................... 3-219
2186A Family, 8192 x 8 Bit Integrated RAM ................................... 3-233
2186S7575/3/4,8192x~BitintegratedRAM ...................... : ........... 3-234
2187 A Family, 8192 x 8 Bit Integrated RAM. . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . .. 3-242
51C64 Family, 65,536 x 1 Bit CHMOS Dynamic RAM ........................... 3-251
51C65 Family, Static Column CHMOS Dynamic RAM ........................... 3-252
RAM Express Data Sheet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-253
8203 64K Dynamic RAM Controller .................................. '. . . . . . .. 3-259
8206/8206-2 Error Detection and Correction Unit .............................. 3-274
8207 Advanced Dynamic RAM Controller .............. . . . . . . . . . . . . . . . . . . . . .. 3-295
Designers Guide To iRAMs .................................................... 3-341

CHAPTER 4
EPROMs (Erasable Programmable Read Only Memories)
APPLICATION NOTE
AP154 Programming the 27256 EPROM. : ................. , .................... 4-1
ARTICLE REPRINTS
.
AR260 EPROMs Graduate to 256K Density with Scaled N-Channel Process ........ " 4-6
AR265 Versatile Algorithm Equipment Cut EPROM Programming Time ............ 4-12
DATA SHEETS
'
.
2732A, 32K (4K x 8) UV Erasable PROM ....................................... 4-17
P2732A, 32K (4K x 8) Production EPROM. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-24
2764, 64K (8K x 8) UV Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-31
2764A, Advanced 64K (8K x 8) UV Erasable PROM .............................. 4-41
P2764, 64K (8Kx 8) Production EPROM. . . . . . . . . . . . . . . . . . . .. . .. . . . . . . . . . . . . . .. 4~50
P2764A, Advanced 64K (8K x 8) Production EPROM ........... , . . . . . . . . . . . . . . . .. 4-60
27128, 128K (16K x 8) UV Erasable PROM ...................................... 4-61
27128A, Advanced 128K (16K x 8) UV Erasable PROM ........................... 4-71
27256, 256K (32K x 8) UV Erasable PROM ........ ; . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-72
Express Data Sheet .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-82
iii

CHAPTER 5
E2 PROMs & NVRAMs (Incircuit Programmable Writable Memories)
APPLICATION NOTES
AP100 Reliability Aspects of a Floating Gates E2 PROM .......................... 5·1
AP158 Designing with the System Friendly 2817 A 5V·Only E2 PROM . . . . . . . . . . . . . . .. 5·8
ARTICLE REPRINT
AR119 16K EE·PROM Relies On Tunneling for Byte Erasable
Program Storage ............................... o' • • • • • • • • • • • • • • • • • • • 5·q7
DATA SHEETS
.
2004, 4K (512 x 8) Non·Volatile Random Access Memory ......................... 5·73
2816A, 16K (2K x 8) Electrically Erasable PROM, .. : .....•...................... 5·83
2817A, 16K (2K x 8) Electrically Erasable PROM ................................ 5·95

CHAPTER 6 '
Bubble. Memory
Magnetic Bubble Primer .................................................... 6·1
APPLICATION NOTES
AP119 Microprocessor Interface for the BPK 72 . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. 6·15
AP127 Powerfail Considerations for Magnetic Bubble Memories ................. 6·64
AP150 8085 to B PK 72 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6·86
AP157 Software Design and Impleme.ntation Details for Bubble
Memory Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6·155
AP164 Using CMOS Minimizes Bubble Memory Power Consumption ............. 6·191
ARTICLE REPRINTS
AR243 Thin·film Detectors X·ray Lithography Deliver 4·Mbit
BubbleChip ........................................................ 6·213
AR250 Bubble Chip Packs 4,Mbits Into 1·Mbit Space ............. , ......... '.' .. 6·215
AR271 New Bubble Memory Packaging Cuts Board & Manufactu'ring . . . . . . . . . . . .. 6·224:
AR27.2 Bubble Memory Support Chips Allow Tailored System Design ............. 6·228
DATA SHEETS
.
BPK 5V74, 4MBit"Bubble Memory Subsystem ................................ 6·237
BPK 5V75, 4M Bit Bubble Memory Prototype Kit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6·250
BPK 70,1 MBit Bubble Memory Subsystem ................................... 6·253
BPK 70A, 1MBit Bubble Memory Subsystem ................................. 6·261
BPK 72A, 1MBit Bubble Memory Prototype Kit ........................•. ; ..... 6·278
7220 Controller for 1MBit BPK 70A Bubble Memory Subsystem .................. 6·281
7224 Controller for4M Bit. ................ : ......... ; . . . . . . . . . . . . . . . . . . . . .. 6·297

CHAPTER 7
General Information ................................................................ 7·1

iv

Alphanumeric Index
2004 4K (512 x B) Non-Volatile Random Access Memory ...................................... 5-73
2114, 1024 x4-Bit Static RAM ........................................................... 3-192
2115A/2125A Family, High Speed 1 K x 1-Bit Static RAM ...............................•..... 3-196
2115H/2125H Family, High Speed 1 K x 1-Bit Static RAM ................................. ~ ... 3-201
2147H High Speed 4096 x 1-Bit Static RAM ............................................. 3-1,3-206
214BH High Speed 1024 x 4-Bit Static RAM ................................................ 3-210
2149HHigh Speed 1024 x 4-Bit Static RAM ................................................ 3-215
2164A Family, 65,536 x 1-Bit Dynamic RAM .................................. 3-22,3-70,3-176,3-219
2.1'8!3Af',amily, B192 x B Bit Integrated RAM ............................................ 3-40,3-233
21B6S, B192 x 8-Bit Integrated RAM ............................................ 3-40,3-233,3-234
2732A, 32K (4K x B) UV Erasable PROM .................................................... 4-17
P2732A, 32K (4K x B) Production EPROM .................................................... 4-24
2764, 64K (BK x B) UV Erasable PROM ......................•...•...... , .............•...... 4-31
2764A, Advanced 64K (BK x B) UV'Erasable PROM ........................................... 4-41
P2764, 64K (BK x 8) Production EPROM .............................................. ',' .... 4-50
P2764A, Advanced 64K (8K x B) Production EPROM .......................................... 4-60
2712B, 12BK (16 x B) l!V Erasable PROM ............................ _ ....................... 4-61
2712BA, Advanced 128K (16K x B) UV Erasable PROM ........................................ 4-71
27256, 256K (32K x B) UV Erasable PROM ........................................... 4-1, 4-6, 4-72
2816A, 16K (2K x B) Electrically Erasable PROM ............................................. 5-83
2B17A, 16K(2K x 8) Electrically Erasable PROM .......................................... 5-8,5-95
51C64 Family, 65,536 x 1 Bit CHMOS Dynamic RAM ........................................ 3-251
51C65 Family, Static Column CHMOS Dynamic RAM ........................................ 3-252
7220 Controller for 1MBit BPK 70A Bubble Memory Subsystem ...................... 6-64, 6-B6, 6-2B1
7224 Controller for 4MBit ............................................................... 6-297
BPK 5V74 4MBit Bubble Memory Subsystem .............................................. 6-237
BPK 5V75 4MBit Bubtile Memory Prototype Kit ............................................. 6-27B
BPK 70 1MBit Bubble Memory Subsystem ................................................ 6-253
BPK 70A 1 MBit Bubble Memory Subsystem ............................................... 6:261 '
BPK 72A 1MBit Bubble Memory Prototype Kit ............................................. 6-27B
80B5 Microprocessor ........ _.......................................................... 6-B6
820364K Dynamic RAM Controller .......... : ................................. 3-110,3-176,3-259
B206/8206A Error Detection and Correction Unit ........................................... 3-176
8207 Advanced Dynamic RAM Controller ................................................ , 3-295

v

PREFACE
This handbook has been prepared to provide a comprehensive grouping of
technical literature covering Intel's memory products, with special emphasis
on microprocessor applications. In addition, a brief summary of current
memory technologies and basic segmentation cif product lines is provided.

Memory Overview

1

(

CHAPTER I: MEMORY OVERVIEW
Joe Altnether

I

MEMORY BACKGROUND
AND DEVELOPMENT

store important data on a non-volatile medium before
the power goes down.

Only ten years ago MOS LSI memories were little more
than laboratory curiosities. Any engineer brave enough
to design with semiconductor memories had a simple
choice of which memory type to use. The 2102 Static
RAM for ease of use or the 1103 Dynamic RAM for low
power were the only two devices available. Since then,
the memory market has come a long way, the types of
memory devices have proliferated, and more than 3,000
different memory devices are now available. Consequently, the designer has a lot to choose trom but the
choice is more difficult, and therefore, effective memory
selection is based on matching memory characteristics
to the application.
~'

Despite their volatility, RAMs have become very popular, and an industry was born that primarily fed computer
systems' insatiable appetites for higher bit capacities
and faster access speeds.

RAM Types
Two basic RAM types have evolved since 1970. Dynamic
RAMs are noted for high capacity, moderate speeds
and low power consumption. Their memory cells are
basically charge-storage capacitors with driver transistors. The presence or absence of charge in a capacitor is interpreted by the RAM's sense line as a logical
1 or O. Because of the charge's natural tendency to distribute itself into a lower energy-state configuration,
however, dynamic RAMs require periodic charge refreshing to maintain data storage.

Memory devices can be divided into two main categories: volatile and non-volatile. Volatile memories retain their data only as long as power is applied. In a great
many applications this limitation presents no problem.
The generic term random access memory.(RAM) has
come to be almost synonymous with volatile memory
in which there is a constant rewriting of stored data;

Traditionally, this requirement has meant that system
designers had to implement added circuitry to handle
dynamic RAM subsystem refresh. And at certain times,
refresh procedures made the RAM unavailable for writing or reading; the memory's control circuitry had toarbitrate access. However, there are nuw two available
alternatives that largely offset this disadvantage. For
relatively small memories in microprocessor environments, the integrated RAM or iRAM provides all
of the complex refresh circuitry on chip, thus, greatly
simplifying the system design. For larger storagerequirements, LSI dynamic memory controllers reduce
the refresh requirement to a minimal design by offering a monolithic controller solution.

a.

'In other situations, however, it is imperative that a nonvolatile device be used because it retains its data
whether or not power is applied. An example of this requirement would be retaining data during a power
failure. (Tape and disk storage are also non-volatile
memories but are not included within the scope of this
.book which confines itself to solid-state technologies in
an IC form factor.)
Thus, when considering memory devices, it's helpful to
see how the memory in computer systems is segmented.
by applications and then look at the state-of-the-art in
these cases.

Where users are less concerned with space and cost
them with speed and reduced complexity, the second
RAM type - static RAMs - generally prove best.
Unlike their dynamic counterparts, static RAMs store
ones and zeros using traditional flip-flop logic-gatel:onfigurations. They are faster and require no refresh. A
user simply addresses the static RAM, and after a very
brief delay, obtains the bit stored in that location. Static
.devices are also simpler to design with than dynamic
RAMs, but the static cell',s complexity puts these nonvolatile chips far behind dynamics in bit capacity per
square mil of silicon.

Read/Write Memory ,
First examine read/write memory (RAM), which permits
the access of stored memory (reading) and the ability
to alter. the stored data (writing) ..
Before the advent of solid-state read/write memory,
active data (data being processed) was stored and retrieved from non-volatile core memory (a magneticstorage technology). Solid-state RAMs solved the size
and power consumption problems associated with core,
but added the element of volatility. Because RAMs lose
their memory when you turn off their power,.you must
leave systems on aU the time, add battery backup or

TheiRAM
There is away, however, to gain the static RAM's
design-in simplicity but with the dynamic RAM's higher
1-1

MEMORY OVERVIEW

The first ROMs contained cell arrays in which the sequence of ones and zeros was established by a metal ization interconnect mask step during fabrication. Thus,
users had to supply a ROM vendor with an interconnect
program so the vendor could complete the mask and
build the ROMs. Set-up charges were quite high - in
fact, even prohibitive unless users planned for large
volumes of the same ROM.

capacity and other advantages. An integrated RAM or
iRAM integrates a dy_namic RAM and its control and
refresh circuitry on one substrate, creating a chip that
has dynamic RAM density characteristics, but looks like
a static RAM to users. You simply address it and collect
your data without worrying about refresh and arbitration.
Before iRAM's introduction, users who built memory
blocks smaller than 8K bytes typically used static
RAMs because the device's higher price was offset by
the support-circuit simplicity. On the other hand, users
building blocks larger than 64K bytes usually opted for
dynamic RAMs because density and power considerations began to take precedence over circuit complexity issues.
For the application area between these two limits, decisions had to depend on less straightforward tradeoffs.
But iRAMs could meet this middle area's needs (See
Figure 1).

To offset this high set-up charge, manufacturers developed a user-programmable ROM (or PROM). The first
such devices used fusible links that could be melted or
"burned" with a special programmer system.
Once burned, a PROM was just like a ROM. If the burn
program was faulty, the chip had to be discarded. But,
. PROMs fur~ished a more cost-effective way to develop
program memory or firmware for low-volume purposes
than did ROMs.

Read-Only Memory

As one alternative to fusable-link programming, Intel
pioneered an erasable MOS-technology PROM (termed
an EPROM) that used charge-storage programming. It
came in a standard ceramic DIP package but had a window that permitted die exposure to light. When the chip
was exposed to ultraviolet light, high energy photons
could collide with the EPROM's electrons and scatter
them at randorr, thus erasing the memory.

Another memory class, read-only memory (ROM), is
similar to RAM in that a computer addresses it and then
retrieves data stored at that address. However, ROM includes no mechanism for altering the data stored ,at that
address - hence, the term read only.
ROM is basically used for storing information that isn't
subject to change - at least not frequently. Unlike
RAM, when system power goes down, ROM retains its
contents.

The EPROM was obviously not intended for use in
read/write applications, but it proved very useful in
research and development for prototypes, where the
need to alter the program several times is quite common. Indeed, the EPROM market consisted almost exclusively of development labs. As the fabrication process became mature; however, and volumes increased,
EPROM's lower prices made them attractive even for
medium-volume production-system applications.

ROM devices became very popular with the advent of
microprocessors. Most early microprocessor applications were dedicated systems; the system's program
was fixed and stored in ROM. Manipulated data could
vary and was therefore stored in RAM. This application
split caused ROM to be commonly called program
storage, and RAM, data storage.

w

>

~....

w

~

~
o

o

:;:
w

~
>

J•.:...JY

TUNNEL
OXIDE

E2PROM CELL.

Figure 7. Double Poly Structure
METAL--______

After fabrication is complete, the wafers· are sent for
testing. Each circuit is tested individually under conditions designed to determine which circuits will operate
properly both at low temperature and at conditions
found in actual operation. Circuits that fail these tests
are inked to distinguish them from good circuits. From
here the wafers are sent for assembly where they are
sawed into individual circuits with a paper-thin diamond
blade. The inked circuits are then separated out and the.
good circuits are sent on for packaging.

Figure 6. Completed Circuit Jwithout passivation)
2-3

inter

MEMORY TECHNOLOGIES

Packages fall into two categories - hermetic and nonhermetic. Hermetic packages are Cerdip, where two
ceramic halves are sealed with a glass fritt, or ceramic
with soldered metal lids. An example of hermetic
package assembly is shown in Table 1 , Non-hermetic
packages are molded plastics.

frame placed on top. This sets the lead frame in glass
attached to the base. The die is then attached and
bonded to the leads. Finally the lid is placed on the
package and it is insertedin a seal furnace where the
glass on the two halves melt together making a hermetic
package.

The ceramic package has two parts, the base, which
has the leads and die (or circuit) cavity, and the metal
lid. The base is placed on a heater block and a metal
alloy preform is inserted. The die is placed on top of the
preform which bonds it to the package. Once attached,
wires are bonded to the circuit and then connected to
the leads. Finally the package is placed in a dry inert atmosphere and the lid is soldered on.

In a plastic package, the key component is the lead
frame. The die is attached to a pad on the lead frame
and bonded out to the leads with gold wires. The frame
then goes to an injection molding machine and the
. package is formed around the lead frame. After mold
the excess plastic is removed and the leads trimmed.
After assembly, the individual circuits 'are retested at an
elevated operating temperature to assure critical operating parameters and separated according to speed and
power consumption into individual specification groups.

The cerdip package consists of a base, lead frame, and
lid. The base is placed on a heater block and the lead

Table 1. 2164A Hermetic Package Assembly
Flow,

Process/Materials

Typical Item

Frequency

Criteria

Wafer
Die saw, wafer break
Die wash and plate
Die visual inspection

f-o

Passivation, metal

QA gate
Die attach
(Process monitor)

Wet out

Post die attach visual
Wire bond
(Process monitor)
QA gate

Cap align, glass
. integrity, moisture'

Temp cycle

2. _

-0

4 x/operator/
machine/shift
every lot

1/129, LTPD=3%

4 x Ifurnace/shift

0/15, LTPD=15%

lOx to mil std.
883 condo C

1/11, LTPD=20%

Hermeticity check
(Process mqnitor)

FIG leak

100% devices

Lead Trim
(Process monitor)

Burrs, etc. (visual)
Fine leak

4 x Istation/shift
2 x /station/shift

External visual

Solder voids, cap
alignment, etc.

100% devices

QA gate

All previous items

All lots

Class test
(Process monitor)

Run standards
(good and reject)
Calibrate every
system using
"autover" program

Every 48 hrs.

!

1. _

0/11 LTPD = 20%

100% devices
All previous items

Seal and Mark
(Process monitor)

0/76, LTPD = 5%

4 x/operator/shift
100% of devices

. Orientation, lead
dressing, etc.

Post bond inspection

f-o

100% of die
Every lot

Mark,and Pack
Final QA

1. Units for assembly reliability monitor:

(See attached)
2. Units for product reliability monitor.

2-4

0/15, LTPD=15%
1/129, LTPD=3%

,.
1/129, LTPD=3%·

MEMORY TECHNOLOGIES

The finished circuits are marked and then readied for
shipment.

critical for high resolution. The wafer is baked at a low
temperature to solidify the resist into gel. It is then exposed with a machine that aligns a mask with the new
pattern on it to a previously defined layer. The photoresist will replicate this pattern on the wafer.

The basic process flow described above may make
VLSI device fabrication sound straightforward, however,
there are actually hundreds of individual operations that
must be performed correctly to complete a working circuit. It usually takes well over two months to complete .
. all these operations and the many tests and measurements involved throughout the manufacturing process.
Many of these details are responsible for ensuring the
performance, quality, and reliability you expect from
Intel products. The following sections will discuss the
technology underlying each of the major process
elements mentioned in the basic process flow.

PHOTOLITHOGRAPHY
The photo or masking technology is the most important
part of the manufacturing flow if for no other reason than
the number of times it is applied to each wafer. The
manufacturing process gets more complex in order to
make smaller and higher performance circuits. As this
happens the number of masking steps increases, the
features get smaller, and the tolerance required becomes
tighter. This is largely because the minimum size of
individual pattern elements determine the size of the
whole circuit, effecting its cost and limiting its potential
complexity. Early MOS IC's used minimum geometries
(lines or spaces) of 8-10 microns (1 micron= 10 - 6 meter
== 1/25,000 inch). The n-channel processes of the mid
1970's brought this down to approximately 5 microns,
and today minimum geometries are less than 2 micrOns '.
in production. This dramatic reduction in feature size
was achieved using the newer high resolution photo
resists and optimizing their processing to match improved optical printing systems.

Negative working resists are polymerized by the light
and the unexposed resist can be rinsed off with solvents. Positive working resists use photosensitive
polymerization inhibitors that allow a chemically reactive developer to remove the exposed areas. The positive resists require much tighter control of exposure and
development but yield higher resolution patterns than
negative resistance systems.
. The wafer is now ready to have its pattern etched. The
etch procedure is specialized for each layer to be
etched. Wet chemical etchants such as hydrofluoric
acid for silicon oxide or phosphoric acid for aluminum
are often used for this. The need for ~maller features
and tighter control of etched dimensions is increasing
the use of plasma e.tching in fabrication. Here a reactor is run with a partial vacuum into which etchant gases
are introduced and an electrical field is applied. This
yields a reactive plasma which etches the required
layer.
The wafer is now ready for the next process step. Its
single journey through the masking process required
the careful engineering of mechaniCS, optics, organic
chemistry, inorganic chemistry, plasma chemistry,
physics, and electronics,

DIFFUSION
The picture of cleah room garbed operators tending furnace tubes glowing cherry red is the one most often
associated with IC fabrication. These furnace operations are referred to collectively as diffusiqn because
they employ the principle of solid state diffusion of mat·
ter to accomplish their results. In MOS processing, there
are three main types of diffusion operations: predeps,
drives, and oxidations.

A second major factor in determining the size of the circuit is the registration
oyerlay error. This is how ac l
curatelY one pattern can be aligned to a previous one.
Design rules require that space be left in all directions
according to the overlay error so that unrelated patterns
do not overlap or interfere with one another. As the error
space increases the circuit size increases dramatically.
Only a few years ago standard alignment tolerances
were ~ ± 2 microns; now advanced Intel processes
have reduced this dramatically due mostly to the use of
advanced projection and step and repeat exposure
equipment.

or

Predeposition, or "predep," is an operation where a
dopant is introduced into the furnace from a solid, liquid,
or gaseous source and at the furnace temperature
(usually 900-1200°C) a sattJrated solution is formed at
the silicon surface. The temperature of the furnace, the
dopant atom, and rate of introduction are all engineered
to give a specific dose of the dopant on the wafer. Once
this is completed the wafer is given a drive cycle where
the dopant left at the surface by the predep is driven into
the wafer by high temperatures. These are generally at
different temperatures than the predeps and are designed to give the required junction depth and concentration profile.
.

The wafer that is ready for patterning must go through
many individual steps before that pattern is complete.
First the wafer is baked to remove moisture from its surface and is then treated with chemicals that ensure good
resist adhesion. The thick photoresist liquid is then applied and the wafer is spun flat to give a uniform coating,
2-5

intel"

MEMORY TECHNOLOGIES

Oxidation, the third category, is used at many steps of
the process as was shown in the process flow. The temperature and oxidizing ambient can range from 800 to
120QoC and from pure oxyge[l to mixtures of oxygen
and other gases to steam depending on the type of oxide required. Gate oxides require high dielectric breakdown strength for thin layers (between .01 and .1 micron)
and very tight control over thickness (typically ± .005
micron or less than ± 1/5,000,000 inch), while isolation
oxides need to be quite thick and because of this their
dielectric breakdown strength per unit thickness is much
less important.

vacuum and are accomplished by vaporizing the metal
with a high energy electron beam and redepositing it on
the wafer or by sputtering it from a target to the wafer
under an eiectric field.
Chemical vapor deposition can be done at atmospheric
pressure or under a moderate vacuum. This type of
deposition is performed when chemical gases react at
the wafer surface and deposit a solid film of the reaction product. These reactors, unlike their general industrial 'counterparts, must be controlled on a microscale to provide exact chemical and physical properties
for thin films such as silicon dioxide, silicon nitride, and
polysilicon.

The properties of the diffused junctions and oxides are
key to the performance and reliability of the finished
device so the diffusion operations must be extremely
well controlled for accuracy, consistency and purity.

The fabrication of modern memory devices is a long,
complex process where each step must be monitored,
measured and verified. Developing a totally new
manufacturing process for each new product or even
product line takes a long time and involves significant
risk. Because of this, Intel has developed process
families, such as HMOS, on/which a wide variety of
devices can be made. These families are scalable so
that circuits need not be totally redesignedJo meet your
needs for higher performance. 1 They are evolutionary
(HMOS I, HMOS II, HMOS III, CHMOS) so that develo~­
ment time of new processes and products can be reduced without compromising Intel's commitment to consistency, quality, and reliability.

ION IMPLANT
Intel's high performance products require such high accuracy and repeatability of dopant control that even the
high degree of control provided by diffusion operations
is inadequate. However, this limitation has been overcome by replacing critical predeps with ion implantation.
In ion implantation, ionized dopant atoms are accelerated by an electric field and implanted directly into the
wafer. The acceleration potential determines the depth
,to which the dopant is implanted.

The 'manufacture of today's MQS memory devices requires a tremendous variety of technologies and manufacturing techniques, many more than could be mentioned
here. Each requires a team of experts to design, optimize, control and maintain it. All these people and thousands of others involved in engineering, design, testi[lg
and production stand behind Intel's products.

The charged ions can be counted electrically during implantation giving very tight control over dose. The ion
implanters used to perform this are a combination of
high vacuum system, ion source, mass spectrometer,
linear accelerator, ultra high resolution current integrator, and ion beam scanner. You can see that this important technique requires a host of sophisticated technologies to support it.

Because of these extensive requirements, most manufacturers have not been able to realize their needs for
custom circuits on high performance, high reliability processes. To address this Intel's expertise in thjs area is
now available to industry through the silicon foundry.
Intel supplies design rules and support to design and
debug circuits. This includes access to Intel's n-well
CHMOS technology. Users of the foundry can now
benefit from advanced technology without developing
processes and IC manufacturing capability themselves.

THIN FILMS
Thin film depositions make up most of the features on
the completed circuit. They include the silicon nitride for
defining isolation, polysilicon for the gate and intercon-·
nections, the glass for interlayer dielectric, metal for interconnectionand external connections, and passivation layers. Thin film depositions are done by two main'
methods: physical deposition and chemical vapor deposition. Physical deposition is most common for depositing metal. Physical depositions are performed in a

1 R. Pashley, K. Kokkonen, E. Boleky, R. Jecmen, S. Liu, and W.
Owen, "H-MOS Scales Traditional Devices to Higher Performance
Leve!," Electronics, August 18, 1977.

2-6

RAMs (Random
Access Memories)

3

I

.1
I

inter·

APPLICATION
NOTE

AP-74

March, 1980

·1

.
I

INTEL CORPORATION. 1980

3-1

I
I

AP-74
which controls the write function. Separate data
input and output are available. Logical operation
of the 2147H is shown in the truth table. The
output is in the high impedance or three-state
mode unless the RAM is being read. Power
consumption switches from standby to active
under control of CS.

MEMORY ARRAY
64 ROWS
64 COLUMNS

4096 x 1 BIT
2147H
PIN CONFIGURATION
Vee

A,

A,

A,

A,

"
A,
A,

A,

A,

A,

A6 DouT

A,

A..
Au

0,"

Vee POWER (+ 5V)

OND GROUND

...

A,

We

Ao-All ADDRESS INPUTS

WE

A,

A,

DOUI

PIN NAMES

LOGIC SYMBOL

WRITE ENABLE
CHIP SELECT

DOllT

A,

'"
A,

A..

TRUTH TABLE

OS
4>1
<1>1
<1>2
$2

Figure 2. 2147H Logic Diagram

SLOW DESelECT, FAST SELECT
SLOW DESELECT, FAST SELECT
FAST DESELECT, FAST SELECT
FAST DESELECT, FAST SELECT

Figure 3. 2147H Block Diagram

Internal structure of the 2147H is shown in the
block diagram of Figure 3. The major portions of
the device are: addresses, control (CS and WE), the
memory array and a substrate bias generator,
which is not shown.
The memory is organized into a two-dimensional
array of 64 rows and 64 columns of memory cells.
The lower-order six addresses decode one of 64 to
select the row while the upper-order six addresses
decode to select one column. The intersection of
the selected. row and the selected column locate the
desired memory cell. Additional logic in the
column selection circuit controls the flow of data
to the array and as stated in the truth table, WE
controls the output buffer.
As shown in Figure 4, the first three stages ofthe
address buffer are designed with an additional
transistor. In each stage, the lowest transistors
are the active devices, the middle transistors· are
load devices, while the upper transistors, con:
trolled by 

<::::>

[1 [1 [] ·

D
0
0
0

<::::>

<::::>

[1 [1 D •
[1 [1 D

<::::>

<::::>

0

0
D ..
0 .. . . .
0 ..

<::::>

en·

II:

•

W

>
a:
c
en
en
w

II:

C
C



<::::>

1

.• .

0 D0 ·

<::::>

••

<::::> = .11'1 CERAMIC CAPACITOR

<::::>

0
0
0
0

<::::>

r

Figure 18. Decoupling

1M

'V \

1\ ~

~

1\ / ""~ V/ ,
V

'\II N

V\

V

\

A

20 mV/DIV

II \..,.,.

,
vee

,fj

A

/V

NOISE WITHOUT GRIDDING AND ONE DECOUPLING
CAPACITOR PEA 4 RAMS

'"

1\

t-.I
V

\ { IV

VV'

V

~

fr..

rv \ j\ II
V

vee NOISE WITH

GRIDDING AND ONE DECOUPLING
CAPACITOR PER 2 RAMS

Figure 19. Vee Noise With & Without Gridding

3·9

.r\

v

20 mV/DIV

AP-74
trace will have transmission line characteristics.
A simplified circuit is shown in Figure 20.

CL

= LOAD CAPACITAN,CE

C'EFF-:=Cl

teo

Dependent on the values ofR, Land C,.there are
three cases shown in Figure 21. In case I, rise and
fall times are excessively long. In case III, the
current smoothly and clearly changes, while in
case II, the current overshoots and rings. If
ringing is severe enough, the voltage can cross the
threshold voltage of the device as in Figure 22.

'Figure 20. Signal Equivalent Circuit

MOS RAM input is essentially capacitive.
Simplifying the capacitance and writing the
differential equation.
() = Ldi +
dt

1.

~dt

CJ'

The solution of this equation is:
i = K,e-r,t+K2e-r2t
where:
'

Figure 22. Access Push·Out Due

r, = R + j R2_1.
2L
4L2 LC
r 2 =R.
- J_
R2_ 1
2L
4L2 LC
K, = constantK2 = constant
CASE

FACTOR

GRAPH

~o

Ringing

Effective access is stretched out until the wave
form settles. System access is the settling time
(~t) plus the specified device access. Case III is the
ideal case but in reality a compromise between
case I and case II is used because parameters vary
in a production environment. Enough series
resistance is inserted to prevent ringing but not
enough to significantly slow down the access. A
series resistance of 330 provides this compromise.
The exact value is determined emperically but
330 is a good first approximation.

SERIES TERMINATION/
PARALLEL TERMINATION
LC

[>o."~

UNDERSHOOT

.0 .

Arrav

SERIES TERMINATION

o

Array

R'
4L'

<

LC

OVERSHOOT

PARALLEL TERMINATION

Figure'23. S_eries,and Parallel Termination

'"

R'
4L 2

LC

CRITICALLY DAMPED

Figure 21.·Three Cases of Equation Solution

Series termination uses one resistor and consumes
little power. Current through the resistor creates a
voltage ·differential shifting the levels of input
voltage to the devices slightly. This shift is usually
insignificant because the 2147H has an extremely
high input impedance.
Termination could also oe accomplished by a
parallel termination as shown, in Figure 23.

3-10

AP-74
Parallel termination has the advantage of faster
rise and fall times but the disadvantage of higher
power consumption and increased board space
usage.

SYSTEM DELAYS
RAMs are connected to the system through an
interface, comprised of address, data and control
signals. Inherent in the interface is propagation
delay. Added to the RAM access time, propagation
delay lengthens system access time and hence system cycle time. Expressed as an equation:

Figure 24A.

tsa = tia + tpd
where:

taa = system access time

t d, = device access time
tpd = propagation delay
Device access is a fIxed value, guaranteed by the
data sheet. System efficien~y then, is a function of
system access and can be expressed as:
E ff = tda/ tsa
where: Eff = System Efficiency
This can be reduced by substitution for tsa to:
Eff = 1/(1 + tpd/tda)

o

1

2

3

<~-----_I~-START CYCLE
(REO)

M".:

I

---,

I

r---

-----'.L--.J,---

L-.....J

d-->c=

DATA OUT

Figure 27. System Timing

TIMING
GEN

12

ADDRESS
LATCH

16

ADDRESS
BUS

roATA"l_

_1~___

~

DATA
BUS

CRITICAL PATH

Figure 28. System Block Diagram

the address and control lines are perpendicular to
the data lines which minimizes crosstalk. Second,
troubleshooting is simplified. A failing row of
devices indicates a defective address or control
driver; whereas a failing column indicates a faulty
data driver.

control signals are coincident with the start of the
cycle. Access is not yet specified because it is
af:(ected by device access and the unknown
propagation delay. Access will be determined in
the design.
Figure 28 illustrates the elements of the system in
block diagram form. Addresses are buffered and
latched at the input to the printed circuit card.
Once through the latch, the addresses split to
perform three functions: board selection, chip
select (CS) generation, and RAM addressing.
Highest order addresses decode the board select,
which enables all of the board logic including CS.

SYSTEM DESIGN
Using previously discussed rules and guidelines,
the design of a typical high speed memory will be
reviewed to illustrate these techniques.
Configuration of the system is a series of identical
memory cards containing 16K words of 16 bits.
Timing and control logic is contained on each
board. System timing requires an 80 ns cycle as
shown in Figure 27. Cycle operation begins when
data and control signals arrive at the board. In
this design, addresses are shifted 30 ns to be valid
before the start of the cycle so that address, data,
and control arrive at the memory device at the
same time for maximum performance. Data and

Next higher order addresses decode CS, while the
lowest order addresses select the individual RAM
cell. Data enters the board from the bidirectional
bus through a buffer/latch, while output data
returns to the bidirectional bus via buffers. Only
two control signals - cycle request (MEMREQ)
and wnte (WR) control the activity on the board.
Figure 29 illustrates the levels of the delay in the

I

3·13

AP-74

CRITICAL PATH

I
I

BOARD
SELECTION

t
I
I

ADDRESS

CHIP
SELECT

~

•
CONTROL

DATA

I

MEMORY

I

+

I

r
Figure 29. Worst Case Delay Path

system. Data and control have only one level. But
examine .the address path, it has three levels.
Addresses are decoded to activate the logic on the
board, select the row of RAM to be accessed and
finally locate the specific memory cell. C8 is in this
address path and is crucial for access; without it
RAM access cannot begin. But this path has the
most levels of decoding with associated
propagation delays. Consequently, the address
path to C8 is the critical path and has the greatest
effect on system delay and hence must be
minimized.
Examination of the system begins with the C8
portion of the critical path, followed by addresses,
data path, and finaily timing and control.

allows addresses to pass independent of any clock.
Delay time is measured from the signal rather
than· a clock. The Intel® 3404 is a high speed, 6-bit
latch operating in a flow-through mode with 12 ns
delay. This is acceptable but a faster latch can be
fashioned using a 2-to-lline multiplexer, either a
748157 or a 748158. The slower of the two is the
748157 with 7.5 ns delay. Although the 748158 is
faster with 6 ns delay, it requires an extra inverter
iIi the feedback path as shown in Figure 30. Between the 748157 and the 748158 latches, the trade
off is speed against board space and power. Individual designers will choose to optimize their
designs.
74504

CRITICAL PATH
Analysis of the critical path begins with the
address latch. The first decision to be made is to
the latch type. Latches can be divided into. two
types: Clocked and flow-through. Clocked latches
capture the data on the leading or trailing edge of
the clock. Associated with the clock is dataset-up
or hold-time that must be included in the delay
time. Accuracy of the clock affects the transit time
of the signal because any skew in the clock adds to
the delay time. As an example, a typical 748173
latch has a data set-up time of 5 ns and a
maximum propagation delay time from the clock
of 17 ns. Total delay time is 22 ns, excluding any
clock skew.
Flow-through latches have an enable rather than
clock. The enable opens the address window and

t)UTPUT

INPUT ------+---t~

Y4 OF 745158

tpo INPUT·OUTPUT
Ipo LATCH·OUTPUT

Figure 30. Fast Latch

3-14

MIN
2 ns
4 ns

MAX
6 ns
12 ns

AP-74
In either case, care must be exercised in
constructing the latch. Output data must be fed
back to the input having the shortest internal path
-' the A input. If the latch is constructed with the
output strapped to the B input, the input could be
deselected and the feedback loop not yet selected
because of the delay through the internal inverter.
In this situation data would be lost. Additional
delay through the external inverter (74S04) aids in
preventing data loss. Inverting addresses has no
system effect - except that it's faster than the
non-inverting latch. During a write cycle,. data
will be stored at the compliment of the system
address .. When this data is to be retrieved, the
same address will be complimented, fetching the
correct word.
.

a true input, defi"ning the output from the Board
Select decoder.
.
In the Board Select decoder, the high order adresses are matched to hard-wired logic levels
generated with switches for flexibility. Changing
a switch setting shifts the 16K range of the board.
Comparison of the switch setting and the address
can be accomplished with an exclusive-OR, a
74S86. NANDing all the exclusive-OR outputs will
generate a Board Select signal. Unfortunately,
this signal is active-low, requiring an additional,
inverter as in Figure 32A, and it also consumes
22.5 ns to decode. An MSI solution to board
selection is a 4-bit comparator - 74S85 - which
+Vcc

MAX PROP DELAY = 11.5 ns

The remaining eleinents in the critical path to be
designed are board selection and CS decoding. To
minimize the CS, decode path, the easiest method
is to work backwards from CS. In this manner input sig~als to a stage are determined and the
output from the preceding stage is defined. This
saves inserting an inverter at the cost of 5 ns to "
generate the proper input to a stage.

"

"!:::::'
'\
r-:::::'
r--

~

'\.

=
===f\.
I

---4r

Starting with theCS driver, the design analyzes
several approaches to select the fastest one. With
four rows of devices, there are four CS signalsto be
generated. A 2-to-4line decoder like the 74S138 is a
possible solution. It is compact, but has two
detriments: long propagation delay and
insufficient drive capability. Propagation delay
from enable is 11 ns. Enable is driven by board
selection which arrives later than the binary
inputs. Splitting the RAMs into two 4x8 arrays
eases the drive requirement but the demultiplexer
must still drive eight devices at 5 pF each - or40
pF total- which adds 1.75 ns to the delay. More
importantly, signal drive is required to switch
cleanly and maintain levels in spite of crosstalk
and reflections. A 74S240 buffer will solve this but
in the process consumes an additional 9 ns.

=='

S04

F!:::='

'\
=LJ

BRD
SEL

540

Figure 31.

A second and preferred' approach is to use a discrete decoder to decode and drive the CS sigrlals.
Four input NAND buffers - 74S40 - fulfill this
function. AddressesAl~ 'and A13 are inverted via
74S04, providing true and compliment signals to
the buffer for decoding. ~s shown in Figure 31, the
delay is 11.5 ns.~~opagation delay for the 74S40 is
specified into a 50 pF load, eliminating the
additional loading !ielay. Left and right driversCSXL and CSXR - are in the same package to
minimize skew petween left and right bytes of
data. All of the 'decoders are enabled by Board
Select to prevent rows of devices on several boards
from being simult!lneously active. Board Select is
.(

3-15

CS Decode

~:~~g~ m~~ 1~:~!2.~6!1~:~:':~:

I 5KEW= 15.25 ns I

Figure 32A.

AN o>---,-ct>=--

/

AN-40>---ct>=---'504

~: PpRRC:;P ~EE~YY :

1.: : ! : ~;S

'5260

::

ISKEW 7.5 ns I

Figure 32B. Board Select

AP-74
consumes less board area and propagation delay
is improved at 16.5 ns.
, The best solution is attained by invertingthe high
order addresses to generate true and compliment
signals. the appropriate signal is connected into a
74S260, 5·input NOR. With an active· high output,
maximum delay is 11 ns as in Figure 32B.
Critical path timing is the sum ofthe latch, Board
Select, and CS delay times. In this example, latch
delay is 6 ns, Board Select is 11 ns and CS decode is
11.5 ns for a total of 28.5 ns. One additional delay
- trace delay - must be included for a complete
solution. Each 74S40 drives eight MOS inputs
having 5 pF/device for a load of 40 pF. Trace
capacitance is calculated on 5 in. of trace. At 1.5
pF/in., trace capacitance is 7.5 pF. Trace delay
calculated from equation 3 is 1.9 DS.
tpl = 1.8 ns x 5 in.
- f t - 12 in.lft
1 + 40 pF
tpl= 1.9 ns ' "
. ,7.5 pF
Total worst case maximum critical path delay has
been calculated to,be 30.4 ns(28.5 ns + 1.9 ns). With
the addresses shifted in time by an amount equal
to the worst case delay, device and system cycle
start are coincfdent. Start of system access and
device access differ only 0.4 ns when the addresses
are shifted 30 ns. From the system cycle start,
access is stretchid by 0.4 ns as shown in Figure 33. '
Thus, with a 35 ns 2147H-l, data is valid at the
output of the device 35.4 ns after the start of the
cycle.
'

J

From address change, the maximum delay in the
critical path is 30.4 ns while the minimum is 10.9
ns. The difference between these two times is skew
and will be important in later calculations.

ADDRESSES
Lower order addresses (Ao-Au) arrive at the devices earlier than' CS because they are not
decoded. Consequently, the address drivers do not
have a critical speed requirement. Once through
the 6 ns latch, addresses have 24 ns to arrive aUhe
devices.
While speed is not the primary prerequisite, drive.
capability is. Address drivers are located in the
center ofthe board, dividing the array into two sections of 32 devices each. For the moment, assume
one driver drives 32 devices as in Figure 34A. Each
device is rated at 5 pF linput, resulting in a load of
160 pF. In addition, there are four 5-in. traces one for each row. twenty inches of trace equates to
30 pF. Total capacitiv6load is 190 pF. A 74S04 is
specified at 5 ns delay into 15 pF. The.increased
capacitive load is 175 pF, which at 0.05 ns/pF increases the delay by 8.75 ns~ Under these conditions the worst cast driver relay is 5 ns plus 8.75 ns,
totalling 13.75 ns. It is 10 ns earlier tlian the 24ns
available.
'
I

LO

ADDRESS

LO

10.9ns

....- - _ 3 0 . 4 n 8

....- - - 3 0 " ' ---)~

Figure 33. CS Decode Time

The minimum delay also must be calculated. With
addresses valid prior to the start of the cycle, CS
decoding can start in the previous cycle. If it
occurs too soon, the previous cycle will not, be
properly completed. Minimum delay time is the
sum of the minimum propagation delays plus
capacitive loading delay plus trace delay.
Capacitive loading delay is less than 0.4 ns and
ignored. Minimum delay through the TTL is 9 ns,
and added to trace delay results in a total of 10.9
ns.

LO

Figure 34A. Address Driver .

The first impression is that this is sufficient, but
the effect of crosstalk must be considered. For
example, as shown in Figure 35, each trace has
, inductance, and parallel traces take on the

3-16

AP-74
can sink 20 rnA, inducing a transient in an
adjacent trace. If the adjacent signal is switching
to a one level, only 400 pA of a source current from
the driver is available. The induced current will
generate a negative spike, driving the signal at a
one leval negative. Additional time of! 0 to 15 ns is
required to recover and re-establish a stable one
level. This may prevent stable address at the start
of the cycle. Recall:

characteristics of transformers. When a signal
switches from a one level to a zero level, its driver

, LO

i= C ddv or dt = C d.v
t

1

where: i = itistantaneous current
C = capacitance
dv
'
- = voltage time rate of change
dt
LO

The terril dvI dt can be maximized by increasing i
or decreasing C. Current can be doubled by using a
driver like a 748240, but it draws 150mA supply
current. In a large system the increased power is a
disadvantage because it requires a larger power
supply and additional cooling.
A better alternative is to reduce the capacitance,
wh~ch results in a corresponding increase in dv/dt
for quick recovery. 8plitting the loads to i6 devices
reduces the capacitance and allows a low power
driver, like a 74804, to be used, as in Figure 34B.
This has the double effect of decreased propagation delay and providing sharp rise and fall times.
Now, there are only 10 in. of trace or 15 pF load and
16 devices, representing 80 pF for a total of 95 pF.
Again, the 804 delay is 5 ns into 15 pF, but the
stretched delay due to 80 pF is, only 4.0 ns for a
total of 9.0 ns. 8table 'addresses are guaranteed at
the start of the cycle.

Figure 34B. Address Drivers

Figure 35. Cross Talk

DATA PATH

x

ADDRESS

SLOWes

Next in line for analysis is the data path.
Reference to the system block diagram shows that
the data is latched into the board on a write cycle
and buffered out during a read cycle. Data latches
are constructed from 748158 quad two-input
multiplexers. Because the data bus is I
bidirectional, 748240 three-sta~e drivers are used
for output buffers.
All that remains to complete the board access com- ,
putation is the calculation of the output propagation delay. Output delay of the active RAM is
caused by the capacitance loading of its own output plus the three idle RAMs, the input
capacitance of the 748240 bus driver and trace
capacitance. Output capacitance of the 2147Hs is
6 pF/device for a subtotal of 24 pF; input
capacitance of the 748240 is 3 pF and trace
capacitance of a 5-in. ,trace is 7.5 pF. total load

r--

~

FAST CS

FAST

ADO~

X

--..,

lr-FIgure 36A.

\':::k-+__-----'x t
WE

~'---------',r---FI--

Figure 36B. RaCe Condition Between Address and WE

3-17

I
I

AP-74
capacitance is 34.5 pF, and access time of the
2147H is specified driving a 30 pF load. Calculated
loading is close enough to the specified loading to
eliminate any significant effect on the access
calculations. Had there been a difference, the
effect would have been included in the calculation.
As previously calculated, transit time of the trace
is 1.6 ns. Adding this to the 7 ns'delay through the
74S240 bus driver results in an 8.6 ns, output
propagation defay from the RAM output to the
bus.
, f
Total access is 35Ans plus 8.6 ns output delay for a
total access of 44 ns. The efficiency of this system
is:
35
'
Eff = 44 or 80%

Figure 36B shows the proper operation controlled
with timing.
Finally, the data output buffers, controlled by.
timing signals, are enabled only during a read
. cycle while the board is selected preventing bus
contention with two or more boards in the system.
More importantly, timing' disables the output
prior to the start of the next cycle, allowing input
data to be stabilized on the bidirectional data bus
in preparation for a write cycle.

TIMING GENERATION
Having discussed the philosophy of timing and
control, we can now focus on the specifics of
address latching, write pulse 'generation and
output-enable timing. To perform these functions
timing can be generated from one of three sources:
clock and shift register" monosta ble
multivibrator, or delay line.

TIMING AND CONTROL
Timing and control gating regulates activity on
the board to guarantee operation in an orderly
fashion. This gating latches addresses, controls
the write pulse width and enables the three·state :
bus drivers. In addition, accurately generated
timing compensates for skew, effects. .
In anti~ipation' of the next cycle, the ,latch must be
opened for the new address. When ,the current
cycle has completed 50 ns, the latch~s are again
opened~ The next cyCle might not begin 30 ns after
the latch is opened because the system may skip
one or more memory cycles. Therefore, a signal
from the next active cycle must close the latch. In
,operation, a buffered Memory Request sign~l
latches the addresses.
'
The write pulse is controlled to guarantee set-up
and hold times for data and address and to
prevent an overlap of CS and write enable from
different cycles:To understand the consequences,
consider the followinl! examole.
Assume two memory banks, one has a minimum
es and the other has a maximum delay path iIi
es, and both have a minimum address delay.
Assume that WE is a level generated fro~ a write
command as shown in Figure 36A. The,operation
, under examination is a write cycle into the bank
with fast CS followed by a read cycle into the bank,
with slow CS.
.
Both the write cycle and the read cycle have device
specification violations. In the write cycle, the ad·
dresses change prior to CS and WE becoming
inactive; that new address location may be written
into. In the read cycle, the address change is
correct but WE is still active and the fast CS .
be/rins too soon, performing a non·existent write
cycle.. Clearly, controlling the width of WE will
solve the problems.

CLOCKED SHIFT REGISTE,R
A clocked shift register' circuit is shown in Figure
.37 consisting of a D·type flip flop and an 8·bit shift
register.
. . . - - - - , MEM~L_ _ _ __

I
CLK...JIlJ"lSl.J[ ,

a

U

-I

'

I+-

LATENCY

Figure 37. D Flip.Flop and Shift Register

On the leading ed~e ofMEMREQ, the Q output of
the D flip flop is clocked to a one state, enabling, a
"one" to be propagated through the shift register.
The one is clocked into the first stage of the shift
. register on the first clock edge after the A andB
inputs are "ones". After the clock, the output QA
goes true which subsequently clears the D flip flop,
clocking zeros'into the register to create a pulse
one clock period wide.
The accuracy and repeatability depends primarily
'on the accuracy and stability of the clock. Crystal
clocks can be built with +0.005% tolerance and less
than a 1% variation due to temperature.

3·18

An inherent difficulty is the synchronization of
Memory Request and the clock. At times there will
be a latency of one clock cycle between Memory
Request and the actual start of the cycle when
Memory Request becomes active just after the
clock edge. Assuming an 80 ns cycle and 20 ns
clock, the latency can be 20 n,s or 25% of a cycle
stretching both access and cycle accordingly. A
second. difficulty of this circuit is caused by the
asynchronous nature of the clock and the Memory
Request. The request becomes act;ive.just prior to

AP-74
the clock and the set-up time of the latch is
violated, the output QA "hangs" in a quasi-digital
state and could double or produce an invalid pulse
width; this and the latency hinder effective use in
high speed design.

generators. The leading edge travels down the
delay lines. When the edge reaches the 25ns tap,
the output is inverted and fed back to the R input of
the R-S flip flop, shaping the pulse to width to 25
ns. Twenty-five nanoseconds was chosen to match
as close as possible the write pulse width. A 25 ns
pulse limits the Memory Request signal width to
less than 25 ns to insure proper operation.
Otherwise, the R-S flip flop will not' clear until
Memory Request returns to a one level. As the
pulse travels down the delay' lines, it acquires
.additional skew of ±1 ns per delay line package for
a total of 6 ns overall. Figure 38 shows several
timing pulses andthe uncertainty of each edge calculated by worst case timing analysis. The
remaining prol>lem is selection oftiming edges to
operate the device. Now that the timing chain is
completely defined, specific details of the address
latch, write 'pulse and output enable can be
completed.

MONOSTABLE MULTIVIBRATOR
The second possible timing generator is a series of
monostable multivibrators, using a device such as
the AMD Am 26S02 multivibrator. It has a
maximum delay from input to output of 20 ns and
an approximate minimum of6 ns. However, with a
delay of 20 ns, the monostable multivibrator offers
no advantage over the clocked generator. Having
a minimum pulse width of 28 ns, the one-shot
offers no improvement over the 50 MHz clock, but
in fact the performance is worse because it is more
temperature .and voltage sensitive. The pulse
width is dependent on the RC network composed
of resistors and capacitors that are temperature
sensitive. Consequently, repeatability leaves.
somethin,g to be desired.

ADDRESS LATCH TIMING
An R-S flip flop activated by MEMREQ latches
the addresses. A second signal which we will now
calculate is used to open the latch. This signal has
two boundaries. If the latch opens too late, the
access of the cycle will be extended; if it opens too
soon, the current cycle will be aborted. Skew
through the R-S flip flop is 1.75 ns to 5.5 ns and
skew in the latch from enable to output is 4 ns to 12
ns for a total skew of 6 to 17.5 ns. With this skew
added to the 30 ns address set-up time, the latch
opening signal must be valid at 36 ns best case or

DELAY LINE
The third and best choice is a delay line. This
design uses STTLDM-406 delay lines from EC2
with tapped outputs at 5 ns increments. In
operation, Memory Request activates an R-S flip
flop fabricated from cross coupled NAND gates.
The output of this circuit starts the memory cycle.
Consequently, the cycle starts 5 ns after Memory
Request compa~ed to 20 ns for the other two timing

1

T60

TlO

1

1

==x:::::

Teo

TO

1

I

T"

T"

T"

1

1

1

A::::::~
elK

---LJ

Tso
1

Teo

T70

TOO

1

1

1

TO

1

.'

TAP 25

TAP 30

",

'"

TAP40
TAP 45

TAP 10

·1
TAP 75

Figure 38. Timing Chain

3-19

I,

AP-74·
47.5 ns worst case prior to the start of the memory
, cycle. Each cycle is 80 ns long, therefore, the latch
opening signal must begin 44 ns or 32.5 ns,
respectively, in the preceding cycle. From the·
delay line timing diagram, T35 will satisfy the
worst case requirements for opening the latch and
T 25 best case. In production, each board is tuned
by selecting T25, T30, or T3p to open the latch,
guaranteeing it opens between 35 and 30 ns prior
to the start of the cycle.

to 8 ns. Subtracting 8 ns from 50, ns sets the
termination of the write timing edge at 42 ns.
Using the inversion of T25 will end the write pulse .
at 43 ns with 7 ns to spare.
Data set-up time is guaranteed because data is
valid 6 ns (the worst case delay through the latch)
after the start of MEMREQ.

OUTPUT ENABLE TIMING
There is a 5.5 ns delay through the address driver
providing minimum device cycle of 50 ns. As a
result the earliest data can disappear from the bus
is at 54 ns because of delay through the output circuit. To select the timing tap for the output enable,
the skew of the enable circuit is 'subtracted from
the system access time.

WRITE PULSE TIMING
The next timing to be calculated is the write pulse.
Figure 39 shows the three parameters which
define the write pulse timing: data set-up time,
write pulse width and write recovery time. Data
set-up is assured by having data valid through
the entire cycle.
I WR

ADDRESS

------------~------~·I~---

DA~A)·_ _ _ _....JI'-------t_---"I'--

Figure 39. WE Constraints

Subtracting the 28. ns skew of the buffer enable circuit from the 44 ns access time of the system shows
that the latest the timing edge can occur is 16 ns,
.which is satisfiEld by edge TW. -The trailing edge,
however, ends at 37 ns and with minimum propagation delays the bus would become three-stated
at 44 ns, coincident with data becoming valid.'
ORing T20 with TW will guarantee the output is
valid until 54 ns, minimum. Selecting a timing gap
between T35 and T50, depending on the
propagation delay in the enable circuit, disables
the output at 70 ns, allowing input data to be valid
for 10 ns prior to start of cycle. The complete
~chematic is shown in Figure 40.

SUMMARY

Placement of WE in the cycle is controlled by
address change to comply with tWR. From
previous calculations th~ earliest addresses· can
change is 50 ns, which defines the end of the WE
signal. Our calculations begin at the· device and
work back to the timing edge. Eight devices
constitute a 40 pF load and a 74S40 is specified for
. a 50 pF load, reducing delay by 0.5 ns when
driving 40 pF. Trace delay l'!nd 74S40 delay is 3.5

The 2147H is an easy-to-use, high speed RAM. The
problems in a memory system design are the result
of inherent limitations in interfacing. Largest of
these is skew, which the designer must strive to
minimize. In this example, skew consumed 45 ns
of an 80 ns cycle while device access time was
extended by only 10 ns, resulting in an 80%
efficiency.

3-20

,.0
AO I

I
I
I

~

A'D

AS

S40

~

AJD

A4 I

-

I
I
I

c:>------;

Al'--

W3

C
C

I
I
I

S~5B

Wi

.....--

Wi

Wo

S~58

MOO~

M01=L
MO'
"OO~
,

I--+---

524"

M015

.....--

I

S04

'---

CS3R

r==L--"

&

5158

FFD

.A

CS2R

CS1R

f=I-'

(.)

MI2

S~58

MIT

504

»

I---+---

-p

CSOR

8---'

~

""==E~

CSOL

A12

...;.,J

M"~
,

~

5158
&

MilS

>04

CS1L

t~

CS2L

BOX

elK

T50

T60

T45~r'--'I~I........,II
IIII

I

A1'D--

".~
~

MEMREQ

S04

•

MEM"R"ffi,

1'--------'_.

",,--o.....J'

5158

TO
~

Figure 40. 16K X I6-Bit High Speed Static Memory

25 ns DELAY LINES
STTLD m 406

I

APPLICATION
NOTE

AP·131

March 1982

© Intel Corporation, 1982

3-22

Ap·131

16-bit address words onto eight address input pins. The
two 8-bit address words are latched into the 2164A by
the two TTL level clocks: Row Address Strobe (RAS)
and Column Address Strobe (CAS). Noncritical timing
requirements allow the use of the multiplexing technique while maintaining high performance.

1. INTRODUCTION
The Intel® 2164A is a high performance, 65,536-word by
I-bit dynamic RAM, fabricated on Intel's advanced
HMOS-D III technology. The 2164A also incorporates
redundant elements to improve reliability and yield.
Packaged in the industry standard 16-pin DIP configuration, the 2164A is designed to operate with a single
+ 5V power supply with ± 10010 tolerances. Pin 1 is left
as a no-connect .(N/C) to allow for future system upgrade to 256K devices. The use of a single transistor cell
and advanced dynamic RAM circuitry en'ables the
2164A to achieve high speed at low power dissipation.

Data is stored in a single transistor dynamic storage cell.
Refreshing is required for data retention and is accomplished automatically by performing a memory cycle
(read, write or refresh) on the 128 combinations of RAo
through R~ (row addresses) during a 2-ms period. Address input A7 is a "don't care" during refresh cycles.

The 2164A is the first commercially available dynamic
RAM to be manufactured using redundant elements and
also features single + 5V operation, low input levels
allowing -2V overshoot, a wide tReD timing window,
low power dissipation, and pinout compatibility with
future system upgrades. These features make the 2164A
easy and desirable to use.

3. DEVICE OPERATION
3.1 A~dressing
A block diagram ofthe 2164A is shown in Figure 2. The
storage cells are divided into four 16,384-bit memory arrays. The arrays are arranged in a 128-row by 128column matrix. Each array has 128 sense amplifiers connected to folded bit lines.

2. DEVICE DESCRIPTION
The 2164A is the next generation high density dynamic
RAM from the 2118 +5V, 16K RAM. Pin 1 N/C provides for future system upgrade of 64K to 256K sockets.
The 2164A pin configuration and logic symbols are
shown in Figure 1.
.

Figure 3 depicts a bit map of the 2164A and also shows
the Boolean equations necessary to enable sequential
addressing of the 16 required address bits (Ao-AJ5)'
There is no requirement on the user to sequentially address the 2164A; the bit map and Boolean equations are
shown for information only.

Sixteen bits are required to address each of the 65,536
data bits. This is accomplished by multiplexing the

PIN
CONFIGURATION

BLOCK DIAGRAM

LOGIC
SYMBOL

IOf128

'ow
DECODERS

D.~

~

,~

CAS

WE

ill

J

'4

Duo.

Aj

4

-'l

A,

::

Ao'

,2

AJ

AD

A.

D,"

""0'"'" {}':
DOUI

10./.

II

A,

A,

AI

1

lQ

A,

~:~,

Voo

8

9

A,

WE

c-;;:;:;--===--,
~;~~:::::~:STAoaE
POWEllt+5VI

Figures 1 & 2. Intel 2164A Pin Assignments and Block Diagram
3-23

Ap·131

INPUT
ADDRESS
TOPOLOGICAL
ADDRESS
2164A

N/C 1
SPARE

SPARE

~

COL1MNS

D,N

2

1000DOOI

,
,

'''DODO'
0"00001

·

16 Vss
COLr MNS

elsa

f%

Ia::~

'"~ ~ ;
~I==

I

""'RQl'(~w

~

::0

of

MSB.

spIRE

""
""
"

1

~

"
""
"

1

'"

0

COLUMNS

.

~IDECODER

,.z

spIRE

00100001
10010001

"010001
00110001

14 Dour

*~
~~~

11000001
01000001

010'0001

15 CAS

"
WE

DECIMAL
EQUIVALENT

o

·
.
·.

1

1

COLUMNS

."

00001001
11001001
01001001
10101001
00101001
11101001
0110.001
10011001
00011001
11011001
010'1001
10111001
00111001

"",00'

10000101

"
. 2164A
ADDRESS
PIN

PROGRAMMED
ADDRESS

ROW

ROW ADDRESS
SCRAMBLING

RAO

NOTE: Bit Map can be determined
from Addre~s Map equations.

RA'
RA2
RA3
RA4
RAS
RAS
RA7
COLUMN
CAO
CA'
CA2
CA3
CA4
CAS
CAS
CA7

AOR
A'R
112R
A3R
A4R
ASR
ASR
A7R

A'R
A2R
A7R
A7R
A7R
A7R
A7R

..

,..

'""

10001101
11001101

00'01101
1110"01
0110,101

'0011101
000,,101

0111110'
100000"
00000011
11000011
01000011
00100011
,11100011
10010011
00010011
ttOl0011
01010011
00110011
11110011
00001011
"0010"
01001011

Iii! i i I
10000111
00000111
"000'11
01,000111
00100111
11100111
01100,111

01110111
10001111
00001111
11001111

".

~

'"".

A7C @ DIN

.

01110101

10010101

01010111
10110111
00110111

ACo

"
m
'"
"'"
'"
"".

11010101
01010101
10110101

01100101

000.0111

AC7
ACS
ACS
AC4
AC3
AC2
AC'

10101111
00101111
10011111
00011111
11011111
00111111
11111111
011111"

::

COLUMN!

113

ADDRESSES

'"
,'"
'"
"
'"'"
,
"
"
'"

.".
.
.

m

"'"
'"
"
"

..."'"
"'"'"
'"
'"
'""
'"
"'"
"'"
"'
'"
m

'"

1111111111111111111111111111
"'1111,1122222222223))333 333 3~ 4 4 ~ 4~ ~ ~ 1 ~ 5 5$5 5 5 5 5 558 8e~ 1116881' 1 " " 11 1 11181 '.'II~~ 9 ' 9 ' Dill DOO 00 0000 00 11' 11,11 1 1 122222222
0123451'.101231511111012345111101234511111012345618110123451111012345811'0123'II'8'0123451,.tOI234561"012345I'1110123451'1110123451'

~A1 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 000000000000000000000000000000000

INPUT
ADDRESS

"

COLUMN ADDRESS
SCRAMBLING

INTERNAL DATA=AQR

TOPOLOGICAL
ADDRESS

1$
1$
1$
1$
1$
1$
1$

"

.""
."
.

m

..'"
".
.'"

11000101
0100010.
10100101

00"1101

"

.

0111000'

10111101

."

"'"
"'"
"
.m"

°

0 0 0 00 0 0 0 0 00 0 0 0a 0 00 0 00 a a 0 0 0 0 00 0 0 0 0 0 0 00 0 a 0 0 0 0 0 00 0 0 a 00
1lA1,'1,1!I'1111'111,""11'I",'lll'"111",,',1111,,I,1111111111110000000000000000000000000000000000000000000000000000000000000000
~"$ 000000000000000000000000 DC 0 00 0 0 01 j 1 1111 1 I"
1 1111 1 , 1 11111 1 1 1 " , l I e 0 0 0 0 0 a 0 0 0 0 0 Q 00 DOC 0 0 0 0 0 0 0 0 0 0 0 0001' 1 11 1 11 1 \ 11 1 1 1 " , 11 1 1 1 1111'1 11 "

::; ~~g~~~g~~~~~~~~~ri~~~~~6~: i i::::: g~~g~~g~~~~~~~~~ ~~~~!ri~~:::::::: ~~~~~g~g~~~~~~~~~~~!~!~~::::::: :ggg~g~gg~~~~~~~~~~~~~~~~:::l::::

:! H!!l; H~n~l iHH!!i 1f~ ~~ ;!l 1HH!!ll ~ ~H!! i1HH!H 1H~ ~!! II H~~! !ll ~H~ rlll i ~H!!! 1HH!! II iH ~!!ll HH: ~ ii Hi~: ~ i1HH!!i: ii

DECIMAL
EQUIVALENT
~.r---------~------------------~--------------------------~--~~---ROWADORESSES

C835

Figure 3. Intel® 2164A Bit Map

3:24

Ap·131

ROW A D D R E S S E S - - - - - - - - - - - - - -

--

---~

",1111""'1"""'1111""",11111",\1"',1"",111111111111'1'1"111222222221122222122221222211222211222.22222222222222222222
ZI333331333S4444444444~!'lil'ISSI"'I •• a e ' 7 " " ' J , ' 7 1 " • • • • • • • • • 811 •• 111.0000DOOOOOI1111111112222222222233323U3Z.' •••• "USSISII
• I 0 1 234 S' 7., 0 I 2 Z. I . , •• 0 1 23. II r I I 0 I 2 I • S 1'1.0 I 2 I 4 S I , •• 0' 2 3. S' 7. I 0 1 2 3' S I , . t 0 1 2 3 4 5., I . Q 1 2 3' 5 I ' " 0 , ~ 3 4 I I ' I II 0 I 2 3 • 5 I ' I I 0 I 2
5 Ii , . /I 0 I Z ) I 5

J.

"'111111111111111111111111111111111111111111111111111"11111111111"111111"IIIIIIII""1111In'1I"l1""1'1III""11111111111RAl
1I0DOOOOODOOOOOOOOOOOOOOO(l"OOOOODOOOOOODOOOOOOOOOOOOOli000000000000"1""" " " " " ' " 11111111111111111111111111111111111111",1"
11M
,111""""1",1',111111",'111,000000000000000000000000000000001"1"",,11,',,1,111111,,,',1,,000000000000000OOOOOOOOOoDOooOOORAS
111',,""',111100000000000000001111111,,1111'1100000000000000001'1'1""'1"1"000000000000000011""111"111"OOOOOOOOOOOoDODORA4
'11","0000000011'111"000000001"'11'100000000"""1'00000000'111"110000000011""1'00000000""'1'10000000011111111000000UAA3
11110000111100001111000011110000111100001111000011110000'111011001111000011110000111100001111000011110000111100001I'IOOoOll"0000!l.fo2
00,11100001,1'0000,11100001',10000',',00001,,1000011,10000',"0000,1110000111100001111000011,100001111000011II00001,,10000111100RIII
0,,0011001100110011001'00110011001'001'001'00110011001100110011001'00110011001100110011001100110011001'0011001100110011001100110RAO

11111111111111111 I 11111111111,1",1111111111 I I I I 111'1111111111111 ~~~a~I~~22112111211122221~22122~~12IZ2222222l2Z22IZ~2Z2211111111
.1 • • • • • • • • • • 7 1 7 7 1 " " ' • • • • • • ' ••• 55555555445544444."'33~l3333'ZZ 5555554444444444333333332233222222221111111111 oooooOOOOOttt,IUt
•• , 0' '5.0 I 32 •• , . I 3 S .0 I •• 4 I 1 ',2 3 I 0 I 1.1 • 5 3 2 •• 1 O. 1 5'," I 32 •• 1. I 3 5 4 0 I . , 135.0 I t I 45' • Z 3 I 06' t a. 5 3 Z I . I "6 , S' 0 1 3 2 I t ' 6 Z ~ 5' a I • I , 5 , 'Z 3 1 0' , •• 45 I 2

TOPOLOGICAL
ADDRESS

INPUT
ADDRESS

DECIMAL
EQUIVALENT

INPUT
ADDRESS
TOPOLOGICAL
ADDRESS

,.".
,.,.'"
,.
'm
,.,....".
,.,.
,.,...'",
,...,
,.'"
,.".
m

'"
m

~~~~~~~~
'10000000
00000000
11000000
01000000
'0100000
00100000
11100000

m

m

COLUMN
ADDRESSES

,
"
"n.
,~

,~

H

m

'"

DECIMAL
EQUIVALENT

Wimr
10001000
00001000
11001000
01000000
10'00000
11101000
01101000
'0011000
00011000
11011000
1011.1000
00111000
11111000
01111000
10000'00
00000100
11000100
01000100
10'00100
00100100
01100100
10010100
000'0100
"010100
01010100
10110100
00110100
11110'00
10001100
00001100
01001100
10101100
00101100
11101100
01101100
10011100
00011100
"01"00
01011100
06111100
11111100
10000010
00000010
11000010
01000010
10100010
0010.0010
11100010
01100010
10010010
00010010
11010010
101100'0
00110010
11110010
01110010
'0001010
00001010
11001010
01001010
1010'010
00101010
01101010
'00110'0
00011010
11011010
0'011010
10111010
11111010
10000110
00000110
01000110
10100110
00100110
11100110
01100110
'00101'0
00010110
"010110
01010110
10110110
00110110
01110110
10001110
11001110
01001110
10101110
00101110
11101110
01101110
10011,,0
00011110
11011110
10111110
00111110

DATA MAP EQUATION
INTERNAL DATA = DATA IN <±> IAOR <±> A7e(

..,

~

,,,.
"

,.
,.
,.

AOR

A7C

m

'M
"un'

INTERNAL
DATA

DATA IN
(D'N)

N

,.'".
,~

,

N

on

,.'"
'"
...
"'"
'N

..

'M

"'"
H

2164A

NIC 1

,M

·,,,
·,.,
··,...
·,......
,....
..
·
···o.,.'"
·

1 6 Vss
SPARE

'N

SPARE
COLrMNS

~

COLrMNS

1 5 CAS

'"

·LSo
Q

~

n

0

RAS 4

on

m

"
"
.o,
"

Ao

on
3:

w

Q

~

~I~
en
zz~ on
~

5

13 A,

,

12 A,

~~~
~S~

A2

~~
~

6

At
spIRE
COLUMNS

'n

'u

U

IiO\Y ~r- ~~

'0

'"
'"

14 DouT

ffi

,M

~

MS8.

SP~RE

1o As

COLUMNS

VDD 6

9

fl.,

N

,n

"n.
'"
"..,
o.
~

·
·....
'0,

...

C836

Figure 3. Intel® 2164A Bit·Map (continued)
3-25

Ap·131

(Figure Sb). The bit sense line is precharged to Voo
when RAS is high (Figure Sc). During an active cycle,
the row select line goes high, and the charge is redistributed (shared) with the bit sense line (Figure Sd).
The sense amplifier detects the level from the cell and
then reinstates full levels into the data cell via a capacitive bit line restore circuit. At the end of the active cycle, the row select line goes low, trapping the data level
charge on the stored cell.

3.2 Active Cycles
When i l l is activated, 512 cells are simultaneously
sensed. A sense amplifier automatically restores the
data. When CAS goes active, Column Addresses CAoC~ choose one of 128 column decoders. CA7 and RA7
gate data sensed from the sense amplifiers onto one of
the two separate differential I/O lines. One 110 pair is
then gated into the Data Out buffer and valid data appears at DOUT.

3.5 Data Sensing

Because of independent RAS and CAS circuitry, successive CAS data cycles can be implemented for transferring blocks of data to and from memory at the maximum rate - without reapplying the RAS clock. This
procedure is called Page Mode operation and is described in more detail in Section 4.6. If no CAS operation takes place during the active RAS cycle, a refreshonly operation occurs: ill-only refresh.

The 2164A sense amplifier compares a stored level to a
reference level (Vss) in a special, non-add~essable storage cell called a dummy cell.

Voo STORAGE

ROW SELECT

PLATE

GATE

I~~.
. -.l

3.3 Storage Cell

j

The basic storage cell is shown in Figure 4. Note that the
2164A uses two dummy cells on each bit line to help
compensate for alignment effects. Data is stored in
single-transistor dynamic RAM cells. Each cell consists
of a single transistor and a storage capacitor. A cell is accessed by the occurrence of row select (RAS) clocks
Ao-A7 into the address pins, followed by column select
(CAS) multiplexing Ag-AJ5 into the address pins.

~ I2Z2Z]

b)

i
\ ... _ _ _

ROW

BIT/SENSE

LINE
CROSS SECTION OF BASIC

~

.'!

d)

tee -

e)

t.e~~e~e~~~e~

~

TRANSISTOR

i

STORAGE CELL

--.--:---;;---:--::---:---::-:--:---:r

SElECT

SELECT

'l

)~
a

.

CIRCUIT DIAGRAM OF BASIC

f)

!

e

e -

e e el

--------'""""-...!....

o

STORAGE CELL

BASIC CELL IS ROW SELECTED
CHARGE IN CELL REDISTRIBUTED

WITHBITLINE

CELL CHARGE IS RESTORED

ROW SELECT GATE IS DESELECTED

63 STORAGE CELLS AND
2 DUMMY CELLS
STORAGE
NODE

I

I
~

Voo 0)..----_'-----', \-,---+-~'--.......-'

Figure 5. Sensing

Figure 6 depicts a simplified schematic of the 2164A
sense amplifier. The sense amp contains a pair of crosscoupled transistors (Q 1 and Q2), two isolation transistors (Q3 and Q4), and a common node which goes low
witli SAS (Sense Amp Strobe) and activates the sense
amp. The bit-sense lines (BSL and BSL) run parallel out
from the sense amp in a folded bit line approach. Each
bit line contains 64 data cells and two dummy cells. The
double dummy cell arrangement helps litnit the effect of
mask alignment on sensing margins by having a dummy
cell oriented in the same direction as the data cells.

Figure 4. Storage Cell
~.4

Charge Storage in Data Cell

Data is stored in the 2164A memory cells as one of the
two discrete voltage levels in the storage capacitor - a
high (Voo) and a low (Vss). These levels are sensed by
the sense amplifiers and are transmitted to the output
buffer. Sensing of stored levels is destructive, so
automatic restoration (rewriting or refreshing) must
also occur.

The folded bit line approach has several advantages,
one of which minimizes the effect of interbit line substrate noise and· 110 coupling by providing common
mode noise rejection. This sense amp arrangement uses
metal bit lines and polysilicon word lines.

The charge storage sensing mechanism for a stored low
is described in Figure S. The Voo storage plate creates a
potential well at the storage node. For a stored low, the
charge is stored in the cell relative to the storage plate
3-26

-.. _r \

lilae '

Ap·131

, ROW
SELECT LINE

BSL

BIT LINE RESTORE

BIT LINE RESTORE

o

• FROM BIT LINE
ISOLATION CLOCK

DUMMY
SELECT
LINE

V

PLATE

Figure 6. Sense Amp

,To eliminate sensing problems, a three-step sensing
(Figure 7) is employed in the generation of Sense Amp
Strobe clock (SAS). Device A is triggered by the sense
strobe clock. This device pulls down slowly and when
fed back, triggers the two gates D and E. When SAS is.
low enough, device B turns on, pulling the SAS line
lower and at a later time, device epulis SAS down hard.
If sensing occurs too quickly, the sense amp. becomes
sensitive to capacitive imbalance and sensing errors
might happen. This design eliminates excessively fast
sensing which can occur when two sense strobe clocks
are being used.

precharge, the row select and dummy select lines are at
Vss, isolating the cells from the bit lines. When RAS
goes low, the precharge clock goes low, ending the pre-.
charge period. .
.

3..7 Data Sensing Operation
The row select and dummy select gating are arranged so
tbe selected data and dummy cells are on alternate bit
lines of the sense amp (Figure 6). The row select and
dummy select lines' go high simultaneously, resulting in
concurrent charge redistribution on the bit lines. The
relationship between the word select lines and the effect
of concurrent charge redistribution on the bit lines is
shown in Figure 8. An approximate 250 mV differential
results from this charge redistribution.

j.y

WORD SELECT LINES (DUMMY AND DATA)

SENSE
STROBE
CLOCK

>+_...r_

TIME (ns)

. -_.__.:~~~~~R~~~ __

vo0t-~--,.

Figure 7. Intel'" 2164A Sense Amp Clocks

-!"~

t

DUMMY DIS LINE

250 mV

............. __ .. _ _ _ _ _ _ _ ~~omv

3.6 Precharge

.

.

I

DATABISLlNE(STOREDLOW) .

-==--:-

Vss L _ _ _ _ _ _ _ _ _ _ _ _ _

A precharge period is required after any active cycle to
ready the memory device for the next cycle. This occurs
while RAS is high. The bit'lines are precharged to VDD ,
while the dummy cells are precharged to Vss. During

TIME (ns)
BIT LINES DURING CHARGE REDISTRIBUTION

Figure 8. Sensing Voltage Waveforms

3-27 '

Ap·131

After charge redistribution, the sense amp is activated.
The sense amp amplifies the,differences in the resultant
voltages on the bit lines. The line with the lower voltage
potential is driven to Vss. The other line remains at a
relatively high level, as shown in Figure 9.

lines. The I/O is a pair of opposite polarity data lines
(110 and 110) which are connected to the Data Input
(DIN) and Data Output (DOUT) buffers. Data is differentially placed on the 110 lines during read operation
and multiplexed to the final 110 lines. During a write
cycle, data is differentially placed on the final 110 lines
from DIN and decoded onto the internal 110 lines.
Stored levels are determined by CA7 column and RAo
row. exclusive-ORed product and then exclusive-ORed
again with DIN (Figure 3). Stored levels are decoded'
during DOUT operation and have no effect on device
use.

Voo
RESTORING
STORED HIGH

~

0

,~

'"zw

::;
~

ii
Vss

-

RESTORING STORED lOW

+--

3.9 Address Latches

TIME (ns)

The 8-bit row and 'column address words are latched
into internal address buffer registers by RAS and CAS.
RAS strobes in the seven low-order addresses (Ao-A7)
both to select the appropriate data select and dummy
select lines and to begin the timing which enables the
sense amps. CAS strobes in the eight high-order addresses (As-AJ5) to select one of the column decoders
and enable 110 operation.

Figure 9. Bit/Sense Line Voltage

The bit line boost circuitry is shown in Figure 10. During sense operations, the boost capacitors are isolated.
After sensing, the bit line with a "0" has the capacitor
turned off (VGS"'O) and, conversely, the bit line with a
"1" has the capacitor turned on. The boost clock will
turn on and boost the I-level up above Vm), giving
maximum charge stored in the cell.

Figure 12 shows a simplified 2I64A address buffer. As

BSL - - , - - - - - ' - - '

BSL-------'

BIT LINE
BOOST
ISOLATION
CLOCK