1984_Intel_Microsystem_Components_Handbook_Volume_1 1984 Intel Microsystem Components Handbook Volume 1
User Manual: 1984_Intel_Microsystem_Components_Handbook_Volume_1
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LITERATURE
In addition to the product line Handbooks listed below. the INTEL PRODUCT GUIDE (no charge. Order
No. 210846) provides an overview of Intel's complete product line and customer services.
Consult the INTEL LITERATURE GUIDE fora complete listing oflntelliterature. TO ORDER literature
in the United States. write or call the Intel Literature Department. 3065 Bowers Avenue. Santa Clara. C A
95051. (800) 538-1876. or (800) 672-1833 (California only). TO ORDER literature from international
locatiom. contact the nearest Intel sales office or distributor (see listings In the back of most any Intel
lIterature).
1984 HANDBOOKS
U.S. PRICE*
Memory Components Handbook (Order No. 210830)
application notes. article reprints. data sheets. and other de~ign information
on RAMs. DRAMs. EPROMs. E2PROMs. Bubble Memorie,.
$15.00
Telecommunication Products Handbook (Order No. 230730)
Contains all application note~. article reprinb. and data ,heel!> for telecommunication
products.
7.50
Microcontroller Handbook (Order No. 210918)
Contains all application notes. article reprints. data ,heet~. and de~lgn Information for the
MCS-48. MCS-51 and MCS-96 familIes.
15.00
Microsystem Components Handbook (Order No. 230843)
applicatIOn notes. article reprints. data sheets. techmcal paper, for microproces~ors and peripherab. (2 Volume~) (Individual User Manuab are abo avaIlable on the
8085. 8086, 8088. 186, 286. etc. Consult the Literature GUide for price, and order
numbers.)
20.00
Military Handbook (Order No. 210461)
Contains complete data sheets for all military products. Information on Leadless Chip
Carriers and on Quality Assurance is al~o included.
10.00
Development Systems Handbook (Order No. 210940)
Contains data sheets on development systems and software, support options, and design
kits.
10.00
OEM Systems Handbook (Order No. 210941)
Contains all data sheets, application notes, and article reprints for OEM boards and
systems.
15.00
Software Handbook (Order No. 230786)
Contains all data sheets, applications notes, and article reprints available directly
from Intel, as well as 3rd Party software.
10.00
Contain~ all
Contain~
* Prices are for the U.S. only.
MICROSYSTEM
COMPONENTS HANDBOOK
'VOLUME 1
1984
Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in
this document nor does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice.
, Contact your local sales office to obtain the latest specifications before placing your order.
The following are trademarks of Intel Corporation and may only be used to identify Intel Products:
BITBUS, COMMputer, CREDIT, Data Pipeline, GENIUS,' i, f, ICE, iCS, iDBP,
iDIS, 12 1CE, iL.,BX, im, iMMX, Insite, Intel, intal, intaiBOS, Intelevision, inteligent
Identifier, intaligent Programming, Intenec, Intellirik, iOSP, iPD~, iSBC, iSBX,
iSDM, iSXM, Library Manager, MCS, Megachassis, MICROMAINFRAME, MULTIBUS, MULTICHANNEL, MULTIMODULE, Plug-A-Bubble, PROMPT,
Promware, QUEST, QUEX, Ripplemode, RMX/SO, RUPI, Seamless, SOLO,
SYSTEM 2000, and UPI, and the combination of ICE, iCS, iRMX, iSBC, MCS, or
UPI and a numerical suffix.
MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk Data
Sciences Corporation.
"
\
• MULTI BUS is a patented Intel bus.
Additional copies of this manual or other Intel literature may be obtained from:
Intel Corporation
Literature Department
3065 Bowers Avenue
Santa Clara, CA 95051
@ INTEL CORPORATION. 1983
Table of Contents
CHAPTER 1
OVERVIEW
Introduction. . . . • . . . . . . . . . . • . • • . . . . • . . . . . • . . . . . • . . . . . . • • . • . • • . • . . • . • • . . • • • • • • • • • • • • •
1-1
CHAPTER 2
MCP-80/85 MICROPROCESSORS
DATA SHEETS
8080Al8080A-11.8080A02, 8-Bit N-Channel Microprocessor ••••.••••.••••••• '........
8085AH/8085 AH-218085AH-1 8-Bit ,HMOS MicroproceSsors ••••••••••••.•••••••••••
8085A18085A-2 Single Chip 8-Bit N-Channel Microprocessors ...•••••••.•.•••••••••
8155H/8156H/8155H-2/8156H-2, 2048-Bit Static HMOS RAM
with I/O Ports and Timer ••.••••••••••••.•••••••••••••••••.•.••.••••••••••• ".
8155/8156/8155-218156-2, 2048-Blt Static MOS RAM with 1/0 Ports and'Timer ....•...
8185/8185-2, 1024 x 8-Bit Static RAM for MCS-85 •.•••.•..••.••••.•••.••.••••.••••.
8205 High Speed 1 OlJt of 8 Binary Decoder •.•..•.••• " • • . . • • • . . • . . • • . • • . • • . • • . . . .
8212 8-Bit Input/Output Port .••.•..•.•...•.••.•• , .. ,.............................
821618226, 4-Bit Parallel Bidirectional Bus Driver •••'...............................
821818219 Bipolar Microcomputer Bus Controllers for MCs-aO and MCS-85 Family ...
8224 Clock Generator and Driver for 8080A CPU ..•••.•.•••••••..•.•••••.•••.•..•.
8228/8238 System Controller and Bus Driver for 8080A CPU .......•..••...•.••..•.•
8237A18237A-4/8237A~ High Performance Programmable DMA Controller..........
8257/8257-5 Programmable DMA Controller •..........•...••.........• ". • • . • • . . • .•
8259A18259A-2/8259A-8 Programmable Interrupt Controller .•.••..•.•.•••... ,., •....
8355/8355-2, 16,384-Bit ROM with I/O .......•.................•.....•..•..•..••.•
8755A18755A-2, 16,384-Bit EPROM with I/O ........................................
2-1
2-10
2-26
2-30
2-42
2-45
2-50
2-55
2-63
2-68
2-79
2-84
2-88
2-103
2-120
2-138
2-146
CHAPTER 3
IAPX 86, 88, 186, 188 MICROPROCESSORS
APPLICATION NOTES
AP-113 Getting Started with the Numeric Data Processor...........................
AP-122 Hard Disk Controller Design USing the Intel 8089 ...•..... ~ . . . . • . . • . •• • . • . . •
AP-123 Graphic CRT Design Using the iAPX 86/11 ..•....•..
AP-143 Using the iAPX 86/20 Numeric Data Processor
in a Small Business Computer ..........................
AP-144 Three Dimensional Graphics Application of the
iAPX 86/20 Numeric Data PrOcessor ••.••••
AP-186 Introduction to the 80186
o. o. o.
DATA SHEETS
iAPX 86/10 16-Bit HMOS Microprocessor
o.
iAPX 186 High Integration 16-Bit Microprocessor
iAPX 88/10 8-Bit HMOS Microprocessor
iAPX 188 High Integration 8-Bit Microprocessor
8089 8/16-Bit HMOS I/O Processor
~
o.
8087 Numeric Data Coprocessor
o.
~
.'
80130/8013(}'2 iAPX 86/30, 88/30, 186/30, 188/30 iRMX 86
Operating System Processors
80150/8015(}'2 iAPX 86/50, 88/50. 186/50, 188150 CPlM*-86
'
o.
Operating System Proc:essors .......
828218283 Octal Latch .
~',
82~Al8284A-1 Clock Generator and Driver for iAPX 86, 88 Processors
o.
~
8286/8287 Octal Bus Transceiver .......
8288 Bus Controller for iAPX 86, 88 Processors .
8289/8289-1 Bus Arbiter
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3-1
3-62
3-123
3-194
3-217
3-256
3-334
3-358
3-412
3-439
3-494
3-508
3-529
3-551
3-562
3-567
3-575
3-580
3-587
CHAPTER 4
IAPX 286 MICROPROCESSORS
, DATA SHEETS
iAPX 286/10 High Performance Microprocessor
•
with Memory Management and Protection ....
80287 80-Bit HMOS Numeric Processor Extension ..
82284 Clock Generator and Ready Interface for iAPX 286 Processors
82288 Bus Controller for iAPX 286 Processors o.
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4-1
4-52
4-76
4-83
CHAPTERS
IAPX 432 MICROMAINFRAME™
DATA SHEETS
iAPX 43201/43202 Fault Tolerant General, Data Processor .........•.......... ,: : .... .
iAPX 43203 Fault Tolerant Interface, Processor •.......... " ............••. ',' ...... .
iAPX 43204/43205 Fal!It''rolerant 'aus Interface and Memory Control Units .......... .
5-1
5-53
5-85
CHAPTER 6
MEMORY CONTROLLERS
APPLICATiON NOTES
AP-97A Interfacing Dynamic RAM to 'IAPX' 86/88 Using the 8202A & 8203 ..•.....•...
AP-141 8203/8206/2164A Memory Design':....... ............. ..................•.
AP-167 Interfacing the 8207 DYnamic RAM Controller to the iAPX 186 ..•............
AP-168 Interfacing the 8207 Advanced Dynamic RAM Confroller to' the iAPX 286 .....
ARTICLE REPRINTS
AR'-231 Dynamic RAM Controller Orchestrates Memory Systems ...•......•........
TECHNICAL PAPERS
'
'
System Oriented RAM Controller' .............................• : • . . . . . . . . . . . . . . . .
, NMOS DRAM Controller ............ :............................................
DATA SHEETS
8202A Dynamic RAM Controller ....................... ~ ..... ~ .. ; .... ; . . . . . . . . . . .
8203 64K Dynamic RAM Controller .... , . ',' . . . . .. . . . . . . . . . . . . . . . . . • . . . • . . . . . . . . • . .
82C03 CMOS 64K Dynamic RAM Controller ...................................•,"
8206/8206-2 Error Detection and Correction Unit .......•..........................
8207 Advanced Dynamic RAM Controller .... :. '.... , .......... : . . . . . . . . . . . . . . . . . ..
8208 Dynamic RAM Controller ...... , ... '......................................•..
USERS MANUAL
Introduction .......... : ...... '; ......... ::: .......................................
Programming the 8207 ....•. : .......... '........ .' ...........................•....
RAM Interface ............. : .............. ::'.....•.......... ; ...................
Microprocessor Interfaces ..................•..... : .........................•....
8207 with ECC (8206) .............. : ................... ,........................
Appendix, .... : ............................ : .........• '..............•...........
6-1
6-37
6-43
6-48
6-55
6-62
6-73
6-77
6-91
6-106
6-119
6-152
6-199
6-218
6-219
6-224
6-233
6-241
6-244
-VOLUME2SUPPORT PERIPHERALS
APPLICATION NOTES
, AP-153 DeSigning with the 8256 ..................................................
DATA SHEETS
' ,
8231 A Arithmetic processing Unit ................................................
8253/8253-5 ProgrammablE! Interval Timer ..............•.........................
8254 Programmable Interval Timer ............ '.. '.................................
8255A18255A-5 Programmable Peripheral Interface ................................
8256AH Multifunctional Universal Asynchronous Receiver Transmitter (MUART) .....
8279/8279-5 Programmable Keyboard/Display Interface ................ ; • . . . . . . . . .•
82285 Clock Generator and Ready Interface for I/O Coprocessors ..................
FLOPPY DISK CONTROLLERS '"
APPLICATION NOTES
AP-116 An 'Intelligent Data Base System Using the 8272 ....... , ......•.............
AP~121 Software Desigriand Implementation of Floppy Di'sk Systems ...............
DATA SHEETS
8271/8271-6 Programmable Floppy Disk Controller .....,...............•.•.........
8272A Single/Double Density Floppy Disk Controller .....................•........
HARD DISK CONTROLLERS
DATA SHEETS
,
,
82062 Winchester Disk Controller ................. : ........ '." . : : . . .. . . .. .. . . . . ..
6-248
6-321
6-331
6-342
6-358
6-379
6-402
6-414
6-421
6-455
6-524
6-553
6-572
i
I
UPI USERS MANUAL
Introduction •........................................•.................•........
Functional Description .................... ,.....................................
Instruction Set .........•........•..............................................
Single-Step, Programming, and Power-Down Modes ...............................
System Operation .....•.•..•.....•.•...•.......................................
Applications . ~ . . . . . . . . . . . • . • . . . . . . • . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DATA SHEETS
8041A18641A18741A Universal Peripheral Interface 8-Bit Microcomputer ..........•..
8042/8742 Universal Peripheral Interface 8-Bit Microcomputer •...... : ..............
8243 MCS-48 InpuVOutput Expander .............. ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8295 Dot Matrix Printer Controller .• . . . • . . • . . • . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SYSTEM SUPPORT
ICE-428042 In-Circuit Emulator ................. : ....................•..........
MCS-48 Diskette-Based Software Support Package .... . . . . . • . . . . . . . . . . . . . . . . . . . . ..
iUP-2oo/iUP-201 Universal PROM Programmers .............•...........•.........
'6-598
6-602
6-619
6-646
6-651
6-657
6-777
6-789
6-803
6-809
6-818
6-826
6-828
CHAPTER 7
DATA COMMUNICATIONS
INTRODUCTION
Intel Data Communications Family Overview ...................................•..
GLOBAL COMMUNICATIONS
APPLICATION NOTES
AP-16 Using the 8251 Universal Synchronous/Asynchrono'us Receiver/Transmitter. . . .
AP-36 Using the 8273 SDLC/HDLC Protocol Controller............................
AP-134 Asynchronous Communications with the 8274 Multiple Protocol
Serial Controller .........................................................
AP-145 Synchronous Communications with the 8274 Multiple Protocol
Serial Controller ...... '...... ... .............. .... .......... .. . .. .........
DATA SHEETS
8251A Programmable Communication Interface ........ :..........................
8273/8273-4 Programmable HDLC/SDLC Protocol Controller .......................
8274 Multi-Protocol Serial Controller (MPSC) .....................................
82530/8253-6 Serial Communications Controller (SCC) ............................
LOCAL AREA NETWORKS
ARTICLE REPRINTS
AR-186 LAN Proposed for Work Stations ............................. : . . . . . . . . . . ..
AR~237 System Level Fu!,)ctions Enhance Controller ...............................
DATA SHEETS
82501 Ethernet Serial Interface ...................................................
82586 Local Area Network Coprocessor ..........................................
OTHER DATA COMMUNICATIONS
APPLICATION NOTES
AP-66 Using the 8292 GPIB Controller ............ \ ...............................
AP-166 Using the 8291 A GPIB Talker/Listener .................. : •.................
ARTICLE REPRINTS
AR-208 LSI Transceiver Chips Complete GPIB Interface. . . . . . . . . . . . . . . . . . . . . . . . . . ..
. AR-113 LSI Chips Ease Standard 488 Bus Interfacing ...... ,........................
TUTORIAL
,
Data Encryption Tutorial ............ .'...........................................
DATA SHEETS
8291A GPIB Talker/Listener ......................................................
8292 GPIB Controller ...........................................................
8293 GPIB Tranceiver ... ; ..................•....................................
8294A Data Encryption Unit ............. :.......................................
7-1
7-3
7-33
7-79
7-116
7-155
7-172
7-200
7-237
7-266
7-272
7-276
7-287
7-322
7-375
7-407
7-414
7-424
7-425
7-454
7-469
7-481
CHAPTER 8
ALPHANUMERIC TERMINAL CONTROLLERS
APPLICATION NOTES
AP-62 A Low Cost CRT Terminal Using the 8275 .,. '" . . .. . . . . .. ... . . . . . . .. ... .. . ..
ARTICLE REPRINTS
AR-178 A Low Cost CRT Terminal Does More with Less............................
DATA SHEETS
8275 Programmable CRT Controller ..............................................
8276 Small System CRT Controller ............................... :...............
GRAPHICS DiSpLAY PRODUCTS
ARTICLE REPRINTS
AR-255 Dedicated VLSI Chip Lightens Graphic Display Design Load ................
AR-298 Graphics Chip Makes Low Cost High Resolution. Color Displays Possible ....
DATA SHEETS
82720 Graphics Display Controller ...............................................
TEXT PROCESSING PRODUCTS
ARTICLE REPRINTS
AR-305 Text Coprocessor Brings Quality to CRT Displays ..........................
AR-296 Mighty Chips ...........................................................
AR-297 VLSI Coprocessor Delivers High Quality Displays ............ '........... , ..
DATA SHEETS
82730 Text Coprocessor ............................................ : .•..........
82731 Video Interface Controller ......................................•..........
8-1
8-43
8-50
8-74
8-91
8-99
8-106
8-144
8-151
8-156
8-159
8-199
CHAPTER 9
PACKAGING
9-1
Overview
1
INTRODUCTION
replacing numerous parts, microprocessor and peripheral
solutions can contribute dramaticaUy to a lower product
cost.
Intel microprocessors and peripherals provide a complete
solution in increasingly complex application ellviranments. Quite often, a single peripheral device will replace
anywhere from 20 to 100 TIL devices (and the a:ssociated
design time that goes with them).
HIGHER SYSTEM PERFORMANCE
Intel microprocessors ,and peripherals provide the highest
system performance for the demands of today's (and'
tommorrow's) microprocessor-based applications. For
example, the iAPX 286 CpU, with its on-chip memory
management and protection, offers th~ highest performance for multitasking,' multiuser systems .
Built-in functions and,a standard Intel microprocessor!
peripheral interface deliver very real time and per/ormance advantages to the designer of microprocessorbased systems.
. REDUCED TIME TO MARKET
i
HOW TO USE THE GUIDE
When you can purchase an off-the-shelf solution that
replaces a number of discrete devices, you're also replacing aU the design, testing, and debug time that goes
with them.
'
The foJlowing application guide illustrates the range of
microprocessors and peripherals that can be used for the
applications in the vertical column on the left. The peripherals are grouped by the I/O function they control:
CRT, datacommunication, universal (user programmable). mass storage, dynamic RAM's, and CPU/bus
support.
INCREASED RELIABILITY
At Intel, the rate offailure for devices is carefuJly tracked.
Reliability is a tangible goal, and today we're measuring
field failures in terms ofparts per million/ That translates
to higher reliability for your product, reduced downtime,
and reduced repair costs. And as more and more functions are integrated on a single VLSI device, the resulting
system requires less power, produces less heat, and
requires fewer mechanical connections-again resulting
in greater system reliability.
'"
An "X" in a horizontal application row indicates a potential peripheral or CPU, depending upon the features
desired. For example, a conversational terminal could
use either of the three display controUers, depending
upon features like the number of characters per row or
font capability. A "Y" indicates a likely candidate, for
example, the 8272A Floppy Disk ControUer in a smaJl
business computer.
LOWER PRODUCT COST
By minimizing design time, increasing reliability, and
The Intel microprocessor and peripherals family provides
a broad range of time-saving, high performance solutions.
1-1
POTENTIAL CANDIDATE X-TYPICAL CANDIDATE Y
"PROCESSOR
DISPLAY
DATACOMM
UPI DISKS DRAM CONTROL SUPPORT
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Tape
Cassette
Floppy/Mini
COMMUNICATIONS
PBX
LANS
Modems
Bjsync,
SOlC/HOlC
Serial BackPlane
Central Office
Network Control
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PERIPHERALS
....
~ ;!
2'
INTE
0
Interrupt Enable: Indicates the content of the Internal interrupt enable flip/flop. ThIS fliplflop may be set
or reset by the Enable and Disable Interrupt instructions and inhibits interrupts from being accepted' by
the CPU when it is reset It is automatically reset (disabling further interrupts) at time T1 of the instruction
fetch cycle (Ml) whe~ an interrupt is accepted and IS also reset by the RESET sIgnal.
INT
I
Interrupt Request: The CPU recognizes an interrupt request on this line at the end of the current
instruction or while halted. If the CPU is in the,HOLD state or if the Interrupt Enable fllplflop is reset it will
not honor the request
RESET'
I
Reset: While the RESET sIgnal IS activated, the content of the program counter IS cleared. After RESET,
the program will start at locatIon 0 in memory. The INTE and HLDA fliplflops are also reset Note that the
flags, accumulator, stack pOinter, and regIsters are not cleared.
Vss
Voo
Gro.und: Reference.
Vee
Power: +5 ±5% Volts
Vee
<1>1.
<1>2
•
Power: +12 ±5% Volts.
Power: -5 ±5% Volts.
Clock Phases: 2 externally supplied.clock phases. (non TTL compatIble)
2-2
AFN·OO735C
· 8080Al8080A·1/8080A·2
ABSOLUTE MAXIMUM RATINGS·
-NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
d.evice. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not, implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. ,
'Temperature Under Bias . . . . . . . . . . . . O°C to +70° C
Storage Temperature " ........... _65°C to +150°C
All Input or Output Voltages
With Respect to V BB ........... -0.3V to +20V
Vcc. VD D and Vss With Respect to VBB
-0.3V to +20V
Power Dissipation . . . . . . . . . . . . . .. ....... 1.5W
D.C. CHARACTERISTICS
(TA
= O°C to
70°C. Voo
=
+12V ±5%.
Vee = +5V ±5%. Vee = "":5V ±5%, Vss =OV; unless otherwise noted)
Test Conditior
IOL ; 1.9mA on all outputs.
~--~--+-------~---------------r------+----r-----r--~ } IOH=-l50~A.
~~~-+--------------------1-~---+~-+~~1---~
f-~::::...::~:.....t--=-----------='-=--+-----t----il----t--~~~-+----------------~--1------+---+----1-----
}
Operation
Tcy;.48 f.lS~c
Vss .;; VIN .;; VCC
Vss .;; VCLOCK .;; VOD
Vss';;VIN';;Vss+O.8V
c
Vss+O.8V';;VIN';;V C
VADDR/DATA ~ VCC
VADDR/DATA
=Vss + 0.45V
'5
CAPACITANCE
Symbol
(TA = 25'C. VCC = VOO =VSS = OV. Vee = -5V)
Parameter
Typ.
Max.
Unit
Test Condition
Cq,
Clock Capacitance
17
25
pf
tc
CIN
I nput Capacitance
6
10
pt
Unmeasured Pins
COUT
Output Capacitance
10
20
pt
Returned to Vss
NOTES:
1 MHz
I
'O~~
05 0.'-----::'2::-5---+7
:----+:::75
50
AMBIENT TEMPERATURE
1. The RESET signal must' be active for a minimum of 3 clock cycles.
2.
~
I,
2 + 10 ns. If HLDA. two
= tWA = tWF·
7. tHF = tD3 + trt/>2 -50 ns).
tWF = too + tr.,,2 - IOns.
9. Data Ifi must be stable for this period during DBIN T3'
Both tOS1 and tOS2 must be satisfied ..
10. Ready signal must be stable for this period during Ta or Tw.
(Must be externally synchronized.)
11. Hold signal must be stable for this period during T2 or TW
when entering hold mode. and during T3. T4. Ts and TWH
\\(hen in ·hold mode. (External synchronization is not reqUired.)
12. Interrupt signal must be stable during this period of the last
clock cycle of any instruction in order to be recognized on the
following instruction. (Extemal synchronization is not required.)
•
13. This timing diagram shows timing relationships only; it does
not represent any spe!lific machine cycle.
READY
.av
WAIT
HOLD
...
HLDA
INT
INTE
I-
I
a.
2-6
AFN·OO735C
8080Al8080A·1/8080A·2
INSTRUCTION SET
The accumulator group instructions include arithmetic and
logical operators with direct, indirect, and immediate addressing modes_
increment and decrement memory, the six general registers
and the accumulator is provided as well as extended incre-.
ment and decrement instructions to operate on the register
pairs and stack pointer. Further capability is provided by
the ability to rotate the accumulator left or right through
or around the carry bit.
Move, load, and store instruction groups provide the ability
to move either 8 or 16 bits of data between memory, the
six working registers and the accumulator using direct, indirect, and immediate addressing modes_
Input and output may be accomplished using memory addresses as 1/0' ports or the directly addressed I/O provided
for in the BOBOA instruction set.
The ability to branch to different portions of the program
is provided with jump, jump conditional, and computed
jumps_ Also the ability to call to and return from subroutines is provided both conditionally and unconditionally_
The RESTART (or single byte call instruction) is useful for
interrupt vector operation_
The following special instruction group completes the BOBOA
instruction set: the NOP instruction, HALT to stop processor execution and the DAA instructions provide decimal
arithmetic capability. STC allows the carry flag to .be directly set, and the CMC instruction allows it to be complemented. CMA complements the contents of the accumulator
and XCHG exchanges the contents of two 16-bit register
pairs directly.
Double precision operators such as stack manipulation and
double add instructions extend both the arithmetic and
interrupt handling capability of the 8080A_ The ability to
Data and Instruction Formats
Data in the BOBOA is stored in the form of B-bit binary integers. All data transfers to the system data bus will be in the
same format.
ID7
D6 D5 D4 D3 D2 D, Dol
DATA WORD
The program instructions may be one, two, or three bytes in length. Multiple byte instructions must be stored
in successive words in program memory. The instruction formats then depend on the particular operation
executed.
One Byte Instructions·
I D7
TYP!CAl INSTRUCTIONS
Register to register, memory reference, arithmetic or logical, rotate,
return, push, pop, enable or disable
Interrupt instructions
D6 D5. D4 D3 D2 D1YDl OP CODE
Two Byte Instructions
I D7
I D7
I OP CODE
Do I OPERAND
D6 D5 D4 D3 D2 D, Do
D6 D5 D4 D3 D2 D,
Immediate mode or I/O instructions
Three Byte Instructions
I D7
I
I OP CODE
I lOW ADDRESSOR OPERAND 1
Do I HIGH ADDRESS OR OPERAND 2
D6 D5 D4 D3 D2 D, Do
D7 D6 D5 D4 D3 D2 D, Do
I D7
D6 D5 D4 D3 D2 .D,
Jump, call or direct load and store
instructions
For the B080Aa logic "1" is defined as a high level and a logic "0" is defined as a low level.
2-7
AFN·00735C
8080Al~80A.1'8080A.2
Table 2~ Instruction Set Summary
MnanIcInIc 0,.
In..ructlon Coda [1]
De Ds D4 D:! D:z Dl
MOVE, LOAD. AND STORE'
MOVr1,r2
0 1 D D 0
MOVM,r
9 1 1 1 0
MOVr,M
0
1
0
0
0
MYlr
0
0
0
0
0
MVIM
0
0
1
1
0
LXIB
0
0
0
0
0
LXI 0
0
0
0
1
0
LXIH
0
0
1
0
0
STAXB
STAXO
LDAXB
LOAXO
STA
LOA
SHLO
lHLD
XCHG
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
0
1
0
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
II
1
0
1
1
Operellons
Do
Description
Clock
CycIaa
(2)
1
0
1
PUSH 0
1
1
0
1
0
1
0
1
PUSHH
1
1
1
0
0
1 0
1
PUSH
PSW
POPB
1
1
1
1
0
1
0
1
1
1
0
0
0
0 0
1
POP 0
1
1
0
1
0
0
0
1
POPH
1
1
1
0
0
0
0
1
POPPSW
1
1
1
1
0
0
0
1
XTHL
1
1
1
0
0
0
1
1
SPHL
LXISP
1
0
1
0
1
1
1
1
1
0
0
0
0' 1
0 1
INXSP
DCXSP
0
0
0
0
1
1
1
1
0
1
0
0
1
1
JUMP
JMP
, JC
JNC
JZ
JNZ
JP
JM
JPE
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
Push register Pair B &
Con stack
Push register Pair 0 &
E on steck
Push register Pair H &
Lon steck
Puah A and Flags
on steck
Pop register Pair B &
C olf stack
Pop register Palr 0 &
Eolf steck
Pop reglst~r Pair H &
L olf steck
Pop A and FIll!/'
off steck
Exchange top of
stack, H& L
H & L to stack pointer
Load Immediate steck
pointer
"Increment stack pointer
Decrement steck
pOinter
1 Jump unconditional
0 Jump on carry
0 Jump on no carry
0 Jump on zero
0 Jump on no zero
0 Jump on positive
0 Jump on minus
0 Jump on partty even
0,.
1
1
1
1
0
0
0
1
0
0
1
0
0
1
Jump on parity ~
H & L to program
counter
10
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
1
1
1
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
Call unconditional
Call on carry
Call on no carry
Call onzaro
Call on no zarO
,Call on positive
Call on minus
Calion partty even
Call on parity odd
17
11/17
11/17
11/17
11/17
11/17
11/17
11/17
11/17
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Raturn
Ratu," on carry
Return on no carry
Return on zaro
Return on no zaro
Return on positive
Return on minus
Return on parity even
Raturn on DaritY odd
10
5/11
5/11
5/11
5/11
5/11'
5111
5111
5111
1 1 A A A 1
INCREMENT AND IlliCRIOMENl
INRr
000001
0 0 1
OCRr
0 0
INRM
0 1 1 0 1
DCRM
0 0 1 1 0 1
0 0 0 0
INxa
0
1
1
Restert
0
0
Increment register
Decrement register
Increment memory
Decrement memory
Increment B & C
registers
Increment 0 & E
registers
Increment H & L
registers
Decrement B & C
Decrement 0 & E_
Decrement H & L
Do
[2)
5
CALI.
7
CALL
7
bc
7
CZ
ONC
ONZ
CP
CM
CPE
CPO
10
10
10
0
0
1
1
0
0
0
0
0
0
0
0
RETURN
RET
RC
RNC
10
7
7
7
7
13
13
16
16
RZ
RNZ
RP
RM
RPE
RPO
0
1
1
0.0
0 0
1 1
1 1
1 0
1 0
0
0
0
1
0
RESTART
4
RST
STACKOPS
PUSHB
ClOck
Cyclea
1
1
Mnemonic
JPO
PCHL
5
,S S S Move register to register
S S S Move register to
memory
1 1 0 Move memory to register
1 1 0 Move Immedlste register
1 1 0 Move immediate
memory
0 0 1 Load Immediate register
PairB&C
0 0 1 Load immediate register
PalrO&E
0 0 1 Load Immedlste register
PairH&L
0 i 0 Store A Indirect
0 1 0 Store A indirect
0 1 0 Load A Indirect
0 1 O. Load A Indirect
0 1 0 Store A direct
0 I, 0 Load A direct
0 f 0 Store H & L direct
0 1 0 Loed H & L direct
0 1 1 Exchange 0 & E, H & L
Registers
Operation.
Daecrlpt,on
Inelrucllan Code [1)
De Ds D4 D:! D:z Dl
11
o
0
1
0
1
0
1
1
o
o
tl
0
11
I
INXO
0
0 0 1 0 0
1
1
INXH
0
0
1
0
1
1
DCXB
DCXO
DCXH
ADD
ADDr
Acer
0
0
0
0
0
0
0 0 1 0 1 1
0 1 1 0 1 1
1 0 1 0 1 1
1
1
0 0 0 0 S S S Add register to A
0 0 0 1 S S S Add register to A
ADOM
ADCM
1
1
0
AOI
ACI
1
1
1
1
0 0 0 1
0
0
1
1
1
1
OAOB
DADO
OADH
OAOSP
0
0
0
0
0
0
0
1
0
0
11
0
0
10
10
10
10
11
5
5
10
10'
"
5
5
5
5
5
5
4
4
with carry
18
0 0 0 1 1 0 Add memory to A
0 0 0 1 1 1 0 ,Add memory to A
5
10
5
5
10
10
10
10
10
10
10
10
2-8
0 0 1 1 0 0
0
0
1
1
0
1
1
1
0
0
0
0
with carry
Add immediate to A
Add immediate to A
with carry
I, AddB&CtoH&L
1 AddO&EtoH&L
1 AddH&LtoH&L,
1 AcId stack pointer to
H&L
0
0
7
7
7
7
10
10
10
10
AFN-0073SC
intJ
8080Al8080A·1/8080A·2
Summary of Procauor In_Ion. (Cont.)
Clock
Cycle.
Clock
In_Ion Code [1J
D6 Ds D4 D:l D:! D,
Mnamonlc
Dr
SUBTRACT
SUBr
,
0
0
1
SBBr
1
0
0
1
SUBM
1 0 0
1
SBBM
1
0
0
1
SUI
1 1 0
1
SBI
1
1 0
1
LOGICAL
ANAr
XRAr
1 0
ORAr
CMPr
ANAM
XRAM
DRAM
CMPM
Do
Dr
RLC
RRC
RAL
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1 1
1 1
1 1
1
1
1
7
RAR
0
0
0
1
1
1
1
1
7
SPECIALS
CMA
0 0 1 0 1
STC
0 0 1 1 0
CMC
0 0 1 1 1
OM
0 0 1 0 0
INPUT/OUTPUT
1 1 0 1 1
IN
1 1 0 1 0
OUT
CONTROL
1 1 1 1 1
EI
1 1 1 1 0
01
NOP
0 0 0 0 0
HLT
0 1 1 1 0
1 1
1 1
1 1
1 1
1
1
1
1
0
0
1
1
1 Input
1 Output
0
0
0
1
1 1
1 1
0 0
1 0
S S S Subtract register
from A
S S S Subtract register from
Awlth borrow
0 1 1 0 Subtract memory
from A
l' 1 1 0 Subtract memory from
A with borrow
0 1 1 0 Subtract Immediate
from A
1 1 1 0 Subtract Immediate
from A with borrow
4
1
4
0
4
4
1 0
1 0
1
1
1
0
0
0
0
1
1
1
1
1 0 S S
1 1 S S
0 0 1 1
0 1 1 1
1
0
1
1
1 0
1 0
1
1
1
1
1 .0
1 0
S S S And register with A
1 S S S Exclusive Or register
S
S
0
0
ANI
XRI
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
ORI
CPI
1 1
1 1
1
1
1
1
0
1
1
1
1
0
0
1
with A
Or ragister with A
Compara register with A
And memory with A
Exclusive Or memory
with A
·Or memory with A
Compare memory with
A
And immediate with A
Exclusive Or immediate
with A
Or Immediate with A
Compare immediate
Operations
Description
Instruction Code III
D6 Os D4 D:l D2 D, DC
Mnemonic
[2J
0
0
1
Cycl••
ROTATE
1
1
Operatlone
De_lpllon
7
7
4
4
7
7
,
121
Rotate A left
Rotate A right
Rotete A left through
carry
Rotate A rrght through
carry
4
4
4
Complement A
Set carry
Complement carrY
Decimal ad'ust A
4
4
4
Enable Interrupts
Disable Interrupt
No-operation
Hall
4
4
10
10
4
4
4
7
7
7
7
7
7
7
with A
NOTES:
1. DOD orSSS: B=OOO, C=OOI, 0=010, E=OII, H=I00, L=101, Memory=110, A=111.
2. l\vo possible cycle times (6/12) indicate Instruction cycles dependent on condition flegs.
"All mnemonics copyright Clntel Corporation 19n
2·9
AFN·00735C
intJ
8085AH/8085AH-218085AH-1
8-BIT HMOS MICROPROCESSORS
• Single +5V Power Supply with 10%
Voltage Margins
• On-Chip System Controller; Advanc:;ed
Cycle Status. Information Available for
Large System Control
• Four Vectored Interrupt Inputs (One is
Non-Maskable) Plus an
8080A-Compatible Interrupt
• Serial In/Serial Out Port
• Decimal, Binary and Double Precision
Arithmetic
• Direct Addressing Capability to 64K
Bytes of Memory
• Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range
• 3 MHz, S MHz and 6 MHz Selections
Available
• 20% Lower Power Consumption than
8085A for 3 MHz and 5 MHz
• 1.3 fJ-S Instruction Cycle (8085AH); O.S
fJ-s (8085AH-2); 0.67 /.LS (8085AH-1)
• 100% Compatible with 808SA
• 100% Software Compatible with S080A
• On-Chip Clock Generator (with
External Crystal, LC or RC Network)
The Intel® 8085AH is a complete 8 bit parallel Central Processing Unit (OPU) implemented in N-channel,
depletion load, silicon gate technology (HMOS). Its instruction set is 100% software compatible with the8080A
microprocessor, and it is designed to improve the present 8080A's performance by higher system speed. Its
high level of system integration allows a minimum system of three IC's [8085AH (CPU), 8156H (RAM/IO) and
8355/8755A (ROM/PROM/IO)) while maintaining total system expandability. The 8085AH-2 and 8085AH-1 are
faster versions of the 8085AH.
The 8085AH incorporates all of the features that the 8224 (clock generator) and 8228 (system controller)
provided for the 8080A, thereby offering a high level of system integration~
The 8085AH uses a multiple)80na \
4700
I C'NT
~ ~15pF
1KO
/
x,
·20 pF CAPACIYORS REQUIRED FOR
CRYSTAL FREQUENCY" 4 MHz ONLY.
a. Quartz Crystal Clock Driver
r
.J
!
'1
·X2 LEFT FLOATING
d. 1-6 MHz Input Frequency External Clock
Driver Circuit
.
I
I C'NT
...l.. -15pF
LEXT
I
..
8085AH
x,
!-----,
.....I
CEXT
I
~ ~2_ _ _ ..J
+5V
'-
.-+._470_0_/:.....
_LO..,W nME > 40 no
b. LC Tuned Circuit Clock Driver
)0
X,
8085AH
x,
4700
r
-8K
aPF
X2
e. 1-12 MHz Input Frequency External Clock
Driver Circuit
c. RC Circuit Clock Driver
Figure 5. qlock Driver Circuits
GENERATING AN 8085AH WAIT STATE
-
~
CLEAR
ALE* ......... ClK
If your system requirements are such that slow
memories or peripheral devices are being used, the
circuit shown in Figure 6 may be used to insert one
WAIT state in each 8085AH machine cycle.
CLKOUTPUT'
"0"
F/F
+5V- 0
Q
-
"0"
F/F
0
----TO
ClK
Q
READY
IN PUT
·AlE AND ClK (OUT) SHOULD BE BUFFERED IF CLK INPUT OF LATCH
EXCEEDS 8085AH 10l OR 10H.
The D flip-flops should be chosen so that
• ClK is rising edge-triggered
• CLEAR is low-level active.
Figure 6. Generation of
a Walt State for 8085AH
CPU
2-15
AFN·O'835C
..
8085AH!8085AH-2I8085AH-1
AB--15
-
A
ADO-7
<
ALE
~ r'
IIIl
I'IA
I-I--
10/lll
elK
r-r--
RESET OU1
Vee
Vee
I--
READY
I
I.
ITIMER
REseT
-
r--
I
WRRB
IN
ALE eE,
AD
07
,
101M
7:~~'
fE I~I
7~D
07
I
I·
I
ALE
Vee
1iD~ :l. STlRDY
I
Tb~~R_
_[ROM + 110]
OR
875M [PROM + VOl
815811
[RAIl + VO + COUNTERITIMER]
BB B
*NOTE OPTIONAL CONNEC-fiON
88
Figure 8. MCS-85"" Minimum System (Memory Mapped 1/0)
-----
x,
TRAP
x,
RESET IN
HOLD
RST1
RST.
-
II810_
s, Is.1-
HLDA
SOD
IIOI&AH
RST5
INTR
RESET
iN'fA.
ADDR/
OUT
DATA ALE Al)'WR 101M
RQVCLK
ADOR
18)
181
101M (es)
WR
8212
r-
liD
DATA
-
STANDARD
J-
L-
MEMORY
ADDR leS)
r
(16)
~ eLK
~ -r--
RESET
101M (es)
I/O POR TS.
¢)
WR
liD
DATA
LS
STANDARD
I/O
ADOR
~LJ.
D I IIr
v"
v"
Vee
Figure 9. MC8-85® System (Using Standard Memories)
2-16
AFN·Ol835C
8085AH/8085AH-2/8085AH-1
As in the 8080, the READY line is used to extend the
read and write pulse lengths so that the 8085AH can
be used with slow memory. HOLD causes the CPU to
relinquish the bus when it is through with it by floating the Address and Data Buses.
----
RSTIi.5
RST5,5
INTR
1l.
ADClR
The 8085AH family includes memory components,
which are directly compatibie to the 8085AH CPU.
For example, a system consisting of the three chips,
8085AH, 8156H, and 8355 will have the following
features:
-
RST7,5
=
SYSTEM "NTERFACE
r1D~x, vi'vl' I
x,
TAAP
ADOR!
OATA ALE M)
lSi
WJi
RESET IN
HOLD
HLDA
SOD
Irt-
S'Ol-
s'rs'r-
RESET
OUT
101M
ROY elK
II
lSi
I~-
POR~rN
CE
~~
:~: POR~
PORT
(8)
Rli 111811 •
AI
•
•
•
•
•
•
•
(61
-
AOOR
2K Bytes ROM
256 Bytes RAM
1 Timer/Counter
4 8-bit I/O Ports
1 6-bit I/O Port
4 Interrupt Levels
Serial In/Serial Out Ports
~t-
r-
IO/~
'N
TIMER
---- r-RESET
OUT
r
-lOw
Rli
ALE
Ihtl~
This minimum system, using the standard I/O technique is as shown in Figure 7.
PORT
~
A
Cl
Ag. 1O
8355/
8755A
DATA/
ADDR
In addition to standard I/O, the memory mapped I/O
offers an efficient I/O addressing technique. With
this technique, an area of memory address space is
assigned for I/O address, thereby, using the memory
address for I/O manipulation. Figure 8 shows the
system configuration of Memory Mapped I/O using
8085AH.
~t~.
101M
r:
RESET
~
eLK
PORT
B
ROY
iOii
vst vIc J
~
v"
...J
OD tROG
V
*NOTE
The 8085AH CPU can also ,interface with the standard memory that does not have the multiplexed
address/data bus. It will require a simple 8212 (8-bit
latch) as shown in Figure 9.
v"
v"
v,,
V
OPTIONAL CONNECTION
Figure 7. 8085AH Minimum System (Standard 1/0
Technique)
2-17
AFN·01835C '
inter
, , 80~5AH/8085AH·218085AH·1
BASIC SYSTEM TIMING
Table 3. 8085AH Machine Cycle Chart
The 8085AH has a multiplexed Data Bus. ALE is used
as a strobe to sample the lower a-bits' of add res,s on
the Data Bus. Figure 10 shows an instruction fetch,
memory read and 1/0 write cycle'(as would occur
during processing of the OUT instruction). Note that
during the 1/0 write and read cycle that the I/O port
address is copied on both the upper and lower half
of the address.
STATUS
IO/M 51
MACHINE CYCLE
OPCOOE FETCH
MEMORY REAO
MEMORY WRITE
I/O READ
I/O WRITE
ACKNOWLEDGE
OF INTR
BUS IDLE
There are seven possible type~ of machine cycles.
Which of these seven takes place is defined by the
status of the three status lines (101M, 51, So) and the
three control signals' (Rl5,
and INTA). (See Table
3.) The status lines can be used as advanced controls (for device selection, for example),' since they
become active at the T1 state, at the outset of each
machine cycle: Control lines Fm and WR' become
active later, at the time when the transfer of data is to
take place, so are used
command lines.
'
CONTROL
SO· IRD_
'~ 1NTA
0
0
1
0
1
1
I'
~
1
1
0
\1
0
1
0
1
0
1
0
1
1
1
1
0
1
1
1
0
1
1
1
1
0
1
TS
1
0
0
1
TS
1
TS
(OF)
(MR)
(MW)
1I0R)
1I0W)
0
0
0
1
1
IINA)
(BIl DAD
ACK OF
RST,TRAP
HALT
1
J
0
,
,
Table 4. 8085AH Machine State Chart
vm,
Status & Buses
I
,A machine cycle normally consists of three T states,
with the exception of OPCODE FETCH, which normally has either four or six T states (ul'!less WAIT or
HOLD states are forced by the receipt of READY or
HOLD inputs). Any T state must be one of ten
possible states, shown in Table 4.
X
X
X
X
,
T2
X
X
X
X
X
"X
0
TWA IT
X
X
X
X
X
X
0
T3
X
X
X
X
X
1
X
TS
Ot
X
TS
Te
,
,
Ot
O'
X
TS
, ,
,
,
0
T4
TRESET
X
TS
TS
TS'
"
0
TS
1
'0
THALT
0
TS
TS
TS
TS
1
X
TS I
TS
TS
TS
,
0
THOLO
0"" LogiC "0"
1 = LogiC "1"
'
Rii.WR iNTA ALE
Tl
T5
"
Control
Machine
State SUO 101M A.-A,S ADo-AD1
as
,,
X
1
,'.
0
0
0
T8" High Impedance
X = Unspecified
* ALE not generated dUring 2nd and 3rd machine cycles of DAD Instruction
t 101M" 1 during 14-Ta of INA machine cycle
eLK
T1
PC H (HIGH ORDER ADDRESS)
,
ALE
WR
101M
STATUS
s,s"
(FETCH)
Figure
10 (READ)
10~
01 WRITE
11
8085AH Basic System Timing
2-18
AFN·O,835C
8085AH/8085AH~21"085AH·1
"NOTICE: Stresses' above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in·t/:le operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias, ......... O°C to 70°C
Storage Temperature ........... , ... -65°C to +l50~C
Voltage on Any Pin
With Respect to Ground .............. -0.5V to + 7V
Power Dissipation ........................... 1.5, Watt
D.C. CHARACTERISTICS
I
8085AH. 8085AH-2: .(TA = O°C to 70°C, Vee = 5V ±10"lo. Vss =OV; unless otherwise specified)"
8085AH-l: (TA = O°C to 70°C, Vee = 5V ±5"1o. Vss = OV; unless otherwise specified)
Units
Test Conditions
Parameter
Min.
Max.
VIL
Input low Voltage
-0.5
+0.8
V
VIH
Input High Voltage
2.0
Vee +0.5
V
VOL
Output low Voltage
0,45
V
IOL = 2mA
VOH
Output High Voltage
V
IOH = -400p.A
Icc
Power Supply Current
Symbol
2.4
135
mA
8085AH, 8085AH-2
200
mA
8085AH-l (Preliminary)
IlL
Input leakage
±10
p.A
o ,,;VIN ,,;Vee
±10
!LA
0.45V '" VOUT ,,; Vee
ILO
Output leakage
VILR
Input low level, RESET
-0.5
+0.8
V
VIHR
Input High level. RESET
2.4
Vee +0.5
V
VHY
Hysteresis. RESET
0.15
V
A.C. CHARACTERISTICS
8085AH,8085AH-2: (TA = O°C to 70°C. Vee = 5V ±10"lo. vss = OV)"
8085AH-l: (TA = O°C to 70°C. vee = 5V ±5"1o. vss = OV)
Symbol
Parameter
8085AH[2)
(Final)
8085AH.2[21
(Final)
8085AH-1
(Preliminary)
Min.
Max.
Min.
Max.
Min.
Max.
2000
200
2000
167
2000
teye
ClK Cycle Period
320
tl
ClK low Time (Standard ClK loading)
80
120
40
20
ns
ns
t2
ClK High Time (Standard ClK loading)
t r • tf
ClK Rise and Fall Time
tXKR
Xl Rising to ClK Rising
20
120
20
,100
20
100
ns
tXKF
Xl Rising to ClK Falling
20
150
20
110
20
110
ns
tAe
Aa_15Valid to leading Edge of Control[l)
270
115-:
70
ns
tAeL
Ao-7 Valid to leading Edge of Control
240
115
60
ns
tAD
Ao-15 Valid to Valid Data In
tAFR
Address Float After leading Edge of
READ (INTA)
tAL
Aa-15 Valid Before Trailing Edge of ALE [11
70
Units
30
50
30
ns
30
ns
575
350
225
ns
0
0
0
ns
115
50
,25
ns
"Note: For Extended Temperature EXPRESS use M8085AH Electricals Parameters.
2-19
AF't01835C
·808SAH/8085AH"21808SAH·1
A.C. CHARACTERISTICS (Continued)
Symbol
8085AH[21
8085AH.2[21
8085AH·1
(Final)
(Final)
(Preliminary)
Parameter
Min. . Max.
tAll
Ao-7 Valid Before Trailing Edge of ALE
90
Min.
Max.
50
220
Min.
Units
Max.
25
100
ns
tARY
READY Valid from Address Valid
tCA
Address (Aa-1S) Valid After Control
120
60
30
40
ns
ns
tcc
Width of Control low (m5, WR, iN'fA)
Edge of ALE
400
230
150
ns
tCl
Trailing Edge of Control to leading Edge
of ALE
50
25
0
ns
tow
Data Valid to ~raillng Edge of wmfE
420
230
140
ns
tHABE
HlDA to Bus Enable
210
150
150
ns
tHABF
Bus Float After HlDA
210
150
150
ns
tHACK
HlDA Valid to Trailing Edge of ClK
tHOH
HOLD Hold Time
110
40
0
ns
0
0
0
ns
170
120
120
ns
0
0
0
ns
tHOS
HOLD Setup Time to Trailing Edge of ClK
tiN'"
INTR Hold Time
tiNS
INTR, RST, and TRAP Setup Time to
Falling Edge of ClK
160
150
150
ns
tLA
Address Hold Time After ALE
100
50
20
ns
tLC
Trailing Edge of ALE to leading Edge
of Control
130
60
25
ns
tLCK
ALE low During ClK High
100
50
15
ns
tLOR
ALEta Valid Data During Read
tLOW
ALE to Valid Data During Write
tLL
ALE Width
tLRY
ALE to READY Stable
tRAE
Trailing Edge of READ to Re-Enabling
of Address
tRO
REAl> (or INTA) to Valid Data
tRY
Control Trailing Edge to leading Edge
of Next Control
tRoH
Data Hold Time After REAl>
tRYH
READY Hold Time
tRYS
.
460
270
175
ns
200
140
110
ns
140
80
110
150
30
90
ns
10
ns
50
150
300
rns
50
75
J
ns
400
220
160
ns
0
0
0
ns
0
0
5
ns
READY Setup Time to leading Edge
ofClK
110
100
100
ns
two
Data Valid After Trailing Edge of WRITE
100
60
30
ns
tWOL
lEADING Edge of WRITE to Data Valid
fIiITA
40
2-20
20
30
ns
AFN-01835C
inter
8085AH/8085AH-2/8085AH-1
3. For all output timing where CL "# 150 pF use the following
correction factors:
25 pF .. CL < 150 pF: -0.10 ns/pF
150 pF < CL .. 300 pF: +0.30 ns/pF
4. Output timings are measured with purely capacitive load.
5. To calculate timing specifications at other values of teye use
Table 5.
NOTES:
1. As-A,s address Specs apply IO/f;if. So. and 5, except As-A,s
are undefined during T4 - Ts of OF cycle whereas IOtM. So. and
$, are stabl".
2. Test Conditions: teye = 320 ns (8085AH)/200 ns (8085AH-2);/
167 ns (8085AH-1); CL = 150 pF.
A.C. TESTING LOAD CIRCUIT
A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUT/OUTPUT
u=x >
2.0
0.8
045
A C TESTING
< )C
2.0
TEST POINTS
DEVICE
~C'=150PF
UNDER
TEST
0.8
INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1 AND 0 45V FOA
A LOGIC 0 TIMING MEASUREMENTS ARE MADE AT 2 ov FOR A LOGIC 1
AND 0 BV FDA A LOGIC 0
CL = 150pF
C L INCLUDES JIG CAPACITANCE
Table 5. Bus Timing Specification as a TCYC Dependent
Symbol
8085AH
8085AH~1
8085AH-2
tAL
(1/2) T - 45
(1/2) T - 50,
(1/2) T - 58
Minimum
tlA
(1/2) T - 60
(1/2) T - 50
(1/2) T - 63
Minimum
tll
(1/2) T - 20
(1/2) T - 20
(1/2) T- 33
Minimum
tlCK
(1/2) T - 60
(1/2) T - 50
(1/2) T - 68
Minimum
tlC
(1/2) T - 30
(1/2) T - 40
(1/2) T - 58
Minimum
·tAO
(5/2
+ N) T
- 225
(5/2
+ N)T
- 150
tRO
(3/2
+ N)T
- 180
(3/2
+ N)T
- 150
tRAE
(1/2) T - 10
(1/2)T-10
(1/2) T - 33
Minimum
tCA
(1/2) T - 40
(1/2) T - 40
(1/2) T - 53
Minimum
tow
(3/2
two
(1/2) T - 60
+ N) T
+ N) T
- 60
(3/2
+ N) T
- 70
(1/2) T - 40
tcc,
(~/2
tCl
{1/2)T - .110
(3/2
- 80
+ N) T
,
(5/2
+ N) T '-
(3/2
+ N) T
(3/2
192
Maximum
- 175
Maximum
+ N)T
-110
(1/2) T - 53
- 70 .
(3/2
+ N)T
-100
Minimum
Minimum
Minimum
(1/2) T - 75
(1/2) T - 83
Minimum
(3/2) T - 200
(3/2) T - 210
Maximum
(1/2) T - 83
Minimum
tARY
(3/2) T - 260
tHACK
(1/2) T - 50
tHABF
(1/2) T
+ 50
(1/2) T
+ 50
(1/2) T
+ 67
Maximum
tHABE
(1/2) T
+ 50
(1/2) T
+ 50
(1/2) T
+ 67
Maximum
. (1/2) T - 60
tAC
(2i2) T - 50
(2/2) T - 85
(2/2) T - 97
Minimum
t1
(1/2) T - 80
(1/2) T - 60
(1/2) T - 63
Minimum
t2
(1/2) T - 40
(1/2) T - 30
(1/2) T - 33
Minimum
tRY
(3/2) T - 80
(3/2) T - 80
(3/2) T - 90
Minimum
(4/2) T - 180
(4/2) T - 130
(4/2) T - 159
Maximum
tLDR
NOTE:
N is equal to the total WAIT states. T '" teye.
AFN·01835C
8085AH/8085AH-218085AH.1
WAVEFORMS (Continued)
READ OPERATION WITH WAIT CYCLE (TYPICAL) 'TO WRITE
T,
T,
SAME READY TIMING APPLIES
.
elK
AsA15
~~--+---------+---------~I~----------+-~~----
ALE
1---+----'·0---1----'
ROIINTA'-T--*---\I-~--l
~~-+--------~I~----------~
READY
NOTE 1 READY MUST REMAIN STABLE DURING SETUP AND HOLD TIMES
INTERRUPT AND HOLD
T,
T2
T,
A8-15=X========~===~-------------;
AD()"7
--<........_ - - 1
11------
BUS FLOATING·
-----o.!
ALE
RD'---------r---~----------.....;
INTA
HoLD
HlOA
*IO/M IS ALSO FLOATING DURING THIS TIME.
2-22
AFN·O'835C
8085AH/8085AH-218085AH-1
Table 6. Instruction Set Summary
Instruction Code
Mnemonic
Operations
Osscrlptlon
07 De D5 ,D4 D3 D2 D1 Do
In.....ctlon Code
Mnemonic DrDeD5D4Da~D1 Do
MOVE, LOAD, AND STOAE
MOVr1 r2
MOVM.r
MOVr.M
MVI r
MVIM
LXIB
0
0
0
0
0
0
0
0
0 0
0
0
0 0
LXI 0
0
0 0
1
0
0
0
1
LXI H
0 0
1
0
0
0 0
1
STAXB
STAXO
LOAX B
LOAX 0
STA
LOA
SHLO
LHLO
XCHG
0
0
0
0
0
0
0
0
0 0
0 0
0 0
0 0
0 1
0 1
0 '1
0 1
0
1
1
0 0
0 0
1 0
1 1 0
1 0 0
1 1 0
0 0 0
0 1 0
1 0 1 0
STACK OPS
PUSHB
1
1
0
0
0
1
0
PUSH 0
1
1
0
1
0
1
0
PUSH H
1
1
1
0
0
1 0
PUSH PSW
1
1
1
1
0
1
POPB
1
1
0
0
0
0 0
POP 0
1
1
0
1
0
0 0
POP H
1
1
1
0
0 0
0
POPPSW
1
1
1
1
0
0
0
XTHL
1
1
1
0
0
0
1
SPHL
LXI SP
1
1
1
1
1
0 0
1
1
INX SP
OCXSP
0 0
0 0
1
1
1
1
0 0 1
1 0 1
JUMP
JMP
JC
JNC
JZ
JNZ
JP
JM
JPE
JPO
PCHL
CALL
CALL
CC
CNC
1
1
1
1
1
1
r
0
1
0
0
1
0
0
0
0
S
S
1
1
1
1
0
0 0
S
S
1
1
1
0
0
0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 1
0
1
1
1
1
1
0 0 1 1 0
0 1 1 1 0
0 1 0 1 0
1
1
1
1
1
1
1
1
1
0
0
0
Move immediate register
Move Immediate memory
1
Pair B & C
I.oad immediate register
PalrO&E
Load immediate register
Pair H & L
Store A indirect
Store A indirect
Load A indirect
Load A indirect
Store A direct
Load A direct
Store H & L direct
Load H & L direct
Exchange 0 & E, H & L
Aeglsters
I~
Push register Pair B &
C on stack
1 Push register Pair 0 &
E on stack
1 Push register Pair H &
L on stack
1 Push A and Flags
on stack
1 Pop register Pair B &
Coif stack
1 Pop register Pair 0 &
E off stack
1 Pop register Pair H &
L off stack
1 Pop A and Flags
off stack
1 Exchange top of
stack, H & L
1 H & L to stack pOinter
1 Load Immediate stack
pOinter
1 Increment stack pointer
1 Decrement stack
pOinter
0
1
0
0
Move register to memory
Move memory' to register
1
1
1
1
1
1
1
1
1
1
1
1
1
1 1 0 0 1
CZ
CNZ
1 1 0 0 0
CP
1 1 1 1 0
CM
1 1 1 1 1
CPE
1 1 1 0 1
1 1 1 o 0
CPO
AETUAN
AET
1 1 0 0 1
AC
1 1 0 1 1
ANC
1 1 0 1 0
AZ
1 1 0 0 1
ANZ
1 1 0 0 0
AP
1 1 1 1 0
AM
1 1 1 1 1
APE
1 1 1 0 1
APO
1 1 1 0 0
AESTAAT
AST
1 1 A A A
INPUT/OUTPUT
IN
1 0 1 1
OUT
1 0 1 0
INCAEMENT AND OECAEMENT
INA'r
0 0 0 0 0
,0 0 0 0 0
DCA r
INAM
0 0 1 1 0
OCAM
0 0 1 1 0
INX B
0 0 0 0 0
Move register to register
0 1 Load immediate register
0 0
0 0 0
0 0
1 0
0 0
1 0
0 0
0 0
1 0
1 0
0 0
1 0
S
S
0
0
0
0
0
0
0
0
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
1 1
1
0
1
0
0
1
0
0
1
1
1
1
1
1
0
0
0
0
~ ~
Call on zero
Call on no zero
Call on positive
Call on minus
Cal: : parity even
I Can i oanty odd
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Aetum
Return
Return
Return
Return
Return
Return
Return
Aeturn
0
0
0
0
1
1
1
1
Aestart
1 ·1
1 1
Input
Output
1
1
1
1
0
0
0
0
0
1
1
1
Increment register
Decrement register
Increment memory
Decrement memory
Increment B & C
registers
Increment 0 & E
registers
Increment H & L
registers
Decrement B & C
Decrement 0 & E
Decrement H & L
0
1
0
0 0' 0
1
0 0
1
1
INXH
0 0
0
0 0
1
1
OCX B
OCXO
OCX H
ADD
AOOr
AOCr
0 0 0 0 1 0
0 0 0 1 1 0
0 0 1 0 1 0
1
1
1
1
1
1
AOOM
ADCM
1 0
1
0 0
0
AOI
ACI
1
1
1 0
1 0
DAD B
DAD 0
OAOH
OAOSP
0
0
0
0
0 0 0
0 0 1
0 1 0
0 1 1
1
1
1
1
0 0
0 0
0 0
0 0
SUBTAACT
SUB r
1
0 0
1
0
S S S
Jump on no zero
Jump on positive
Jump on minUS
SBB r
1
0
1
1
Jump on parity even
Jump on parity odd
H & L to program
counter
SUB M
1
0 0
1 0
SBBM
1
0 0
1
1
SUI
1
1
0
1
0
SBI
1
1 0
1
1
Jump
Jump
. Jump
Jump
unconditional
on carry
on no carry
on zero
Call unconditIonal
Call on carry
1
1
0 0
0 0
0 0 S S S Add register to A
0 1 S S S Add register to A
0
1
1
1
1
1
0 0 1
0 1 1
1
1
C 0
0
on carry
on no carry
on zero
on no zero
on positive
on minus
on parity even
on parity odd
0
0
INXO
1
Operations
Description
with carry
Add memory to A
Add memory to A
with carry
0 Add immediate to A
0 Add immediate to A
With carry
1 AddB&CtoH&L
1 AddO&EtoH&L
1 AddH&LtoH&L
1 Add stack pointer to
H&L
0
0
Subtract register
from A
S S S Subtract register from
A with borrow
1 1 0 Subtract memory
from A
1 1 0 Subtract memory from
A with borrow
1 1 0 Subtract immediate
from A
1
1
0 Subtract immediate
Irom A With borrow
Call on no carry
2-23
AFN·OI835C
inter
8085AH/8085AH-218085AH-1
Table 6. Instruction Set Summary (Continued)
Mnemonic
II?
Instructl... Code
Os 05 04 II:! II:! 0, 00
LOGICAL
ANA.
XRAr
1 0 1, 0 0 S S S
1 ,0 1 0 1 S S S
ORAr
CMPr
ANAM
XRAM
1 0'
1 - 0'
1 a
1 ,0
1
1
1 1
1 0
1 0
0
ORAM,
CMP~
1 0
1 0
l' t
1 j
0 1, 1 0
1 1 1 0
ANI
XRI
1 1
1 1
1 0 0 1 1 0
1 0 1 1 1 0
ORI
CPI
1 1 1 1 0 1
1 1 1 1 1 1
ROTATE
RLC
RRC
RAL
I'RAR
1
0
1
S S S
S S S
1 1 0
1 1 0
1 0
1 0
0 0 0 0 1 1 1
0 0 0 0 1 1 1 1
0 0 0 1 0 1 1 1
0
0 0 0
1 1 1
1
1
Operations
Deec.lptlon '
,
And register with A
Exclusive OR register
with A
OR register with A
Compare register with A
And memory with A
Exclusive OR memory
with A
OR memory with A
Compare
memory with A
And Immediate with A
Exclusive OR immediate
with A
OR immediate with A
Compare Immediate
with A
Rotate A
Rotate A
Rotate A
carry
Rotate A
carry
•
Operations
Instruction Code
Oeecrtptlon
Mnemonic 07 Os 05 04 03 02 0, 00
SPECIALS
CMA
0 0 1 0 1 1 1 1 Complement
"
A
Sl'C
0 0 1 1 0 1 1 1 Set carry
CMC
0 0 1 1 1 1 1 1 Complement
carry
OM
0 0 1 0 0 1 1 1 Decimal ad'ust A
CONTROL
EI
1 1 1 1 1 0 1 '1 Enable Interrupts
01
1 1 1 1 0 0 1 1 Disable Interrupt
NOP
0 0 0 0 0 0 0 0 No-operation
HLT
0 1 1 1 0 1 1 0 Halt
NEW 8085A ISTRUCTIONS
RIM
0 0 1 0 0 0 0 0 Read Interrupt Mask
SIM
0 0 1 1 0 0 0 0 Set Interrupt Mask
left
right
left through
right throug,h
NOTES;
,
1. DDS or SSS: B 000, COOl, 0010, EOl1, H 100, L 101, Memory 110, A 111.
2. Two possible cycle times (6112) Indicate ,"struction' cycles dependent on condition flags.
"All mnemonics copyrighte aOaSA is a complete a bit parallel Central Processing Unit (CPU). Its instruction set is 100% software compatible
with the 80aOA microprocessor," and it is designed to improve the present 8080A's performance by higher system speed,
Its high level of system integration allows a minimum system of three IC's [808SA (CPU), 8156 (RAM/IO) and 83S5/8755A .
(ROM/PROM/IO)] while maintaining total system expandability. The 8085A-2 is a faster version of the 8085A.
The 8085A incorporates all of the features tllat the 8224 (clock generator) and 8228 (system controller) provided for the
8080A, thereby offering a high level of system integration.
The 808SA uses a multiplexed data bus. The address is split between the 8 bit address bus and the 8 bit data bus. The
on-chip address latches of 815S/8156/8355/87S5A memory products allow a direct interface with the 8085A.
*: *:
REG
REG
STACK POINTER
•
PROGRAM COUNTER
}REG1STfR
ARRAY
1161
1161
INCREMENteR/DECREMENTER
11&1
ADDRESS LATCH
A16-Aa
AODREsseus
Flgl,lr. 1. 808SA CPU Functional Block Diagram
X,
Vee
X2
HOLD
RESET OUT
SOD
SID
TRAP
RST 7 5
RST 6.5
RSTS.5
INTR'
HLOA
elK (OUT)
RESET IN
READY
101M
81
R5
WR
INTA
ALE
ADD
So
AD,
A15
AD2
AD3
AD4
ADS
ADS
A14
A13
A12
An
A10
AD7
A9
VSS . . ._ _...r
AJ
AOt-AOo
ADDRESS/DATA BUS
Figure 2; ·8OSSA Pin
. Configuration
I
2-26
AFN-01242C
inter
808SA/808SA-2
"NOTICE: Stresses abova those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias......... OOC to 70°C
Storage Temperature ..............-65°C to +150°C
Voltage on Any Pin
With Respect to Ground ............ -0.5V to +7V
Power Dissipation. . . . . . . . . . . . . . . . . .
1.5 Watt
D.C. CHARACTERISTICS
(TA =
o·c to 700C, Vee
Parameter
=
ov ±5%, Vss =
OV; unless otherwise specified)
Min.
Max.
Units
V IL
Input Low Voltage
-0.5
+0.8
V
VIH
Input High Voltage
2.0
VCC·+O·5
V
VOL
Output Low Voltage
0.45
V
IOL
VOH
Output High Voltage
V
IOH
Icc
Power Supply Current
170
rnA
IlL
Input Leakage '
±10
/JA
0... VIN ... Vcc
ILO
Output Leakage
±10
/JA
0.45V';;; V out ';;; Vcc
VILR
Input Low Level, RESET
-0.5
VIHR
Input High Level, RESET
2.4
V HY
Hysteresis, RESET
Symbol
2.4
0.25
2-27
+0.8
V
Vcc +0.5
V
Test Conditions
= 2mA
=-400/JA
V
AFN-01242C
inter
8085A/8085A-2
A.C. CHARACTERISTICS
Symbol
(TA ==
ooe to 70oe, vee = ov
±5%,
vss = ,OV)
8085AI2J
Parameter
8085A·212J
Min.
Max•.
Min•
Max.
2000
2000
. tcvc
t1
CLK Cycle Period
(.iLK Low Time (:standard CLK Loaolng)
320
80
200
40
t2
CLK High Time (Standard CLK Loading)
120
70
t r, t f
tXKR
tVIt"'
tAC
tACL
tAO
tAFR
tAL
tALL
tARY
lel
tcc
tCL
tow
tHABE
tHABF
t HACK
t HOH
tHOS
tlNH
tiNS
tLA
tLc
t LCK
tLOR
tLow
tLL
t LRy
CLK Rise and Fall Time
X· Rilling to eLK RISing
X Rlslne to CLK Faliine
A8 _15 Valid to Leading Edge of Control llJ
Ao-7 Valid to Leading Edge of Control
AO-15 valla to valla Data In
Ao~ess F~oat ATter Leaolng Edge Of
READtiNTA}
AS- 15 Valid Before Trailing Edge of ALEI1J,
Ao-7 Valid Before Trailing Edge of ALE
HI:AUY valla from Aaaress valla
Aaaress lAa-15) valla A ter \.: ontro
Width of Control Low (RD, WR, INTA)
Edge' of ALE
Trailing Edge of Control to Leading Edge
of ALE
Data Valid to Trailing Edge of WRITE
HLDA to Bus Enable
Bus Float After HLDA
HLDA Valid to Trailing Edge of CLK
HOLD Hold Time
HOLD Setup Time to Trailing Edge of CLK
11111 H MOla lime
INTR, RST, and TRAP Setup Time to
Falling Edge of CLK
Address Hold Time After ALE
Trailing Edge of ALE to Leading Edge
of Control
ALE Low During CLK High
ALE to valla Data During Read
ALE to Valla Data Dunng write
ALI: Wldtn
ALE to READY Stable
2-28
30
30
270
240
30
120
150
30
30
115
115
575
ns
ns
ns
30
100
110
350
0
Units
0
ns
ns'
ns
. ns
ns
ns
120
60
ns
ns
ns
ns
ns
400
230
ns
50
25
230
115
50
90
50
220
100
110
0
170
0
40
0
120
0
ns
ns
ns
ns
ns
ns
ns
ns
160
100
150
50
ns
ns
130
100
60
ns
ns
ns
ns
ns
ns
420
210
210
150
150
50
460
200
140
270
120
80
110
30
AF~·01242C
intJ
8085A18085A·2
A.C. CHARACTERISTICS (Continued)
Symbol
8085A[2)
Parameter
Min.
tRAE
8085A·2[2)
Min.
Max.
150
Trailing Edge of READ to Re·Enabling
of Address
Units
Max.
90
ns
150
300
tRD
READ (or I":ITA) to Valid Data
tRV
Control Trailing Edge to leading Edge
of Next Control
400
220
ns
tRDH
Data Hold Time After READ INTA[7)
tRYH
tRYS
READY Setup Time to leading Edge
of ClK
0
0
110
0
0
100
ns
READY Hold Time
two
Data Valid After Trailing Edge of WRITE
tWDl
lEADING Edge of WRITE to Data Valid
100
ns
ns
ns
60
40
ns
20
\
ns
NOTES:
1.
As·A 15 address Specs apply to 101M, So' and S1 except As·A 15 are undefined during T4·Ts of OF cycle
whereas IOiM, So' andS1 are stable.
2.
Test conditions: teye = 320 ns (8085A)/200 ns (8085A·2); CL = 150 pF.
3.
For all output timing where Cl = 150pF use the following correction factors:
25pF .. CL < 150pF: -0.10ns/pF
150pF < CL" 300pF: +0.30ns/pF
4.
Output timings are measured with purely capacitive load.
5.
All timings are measured at output votage VL = 0.8V, VH ='2.0V, and 1.5V with 20ns rise and fall time on inputs.
To calculate timing specifications at other values of teye use Table 7.
Data hold time is guaranteed under all loading conditions.
6.
7.
A.C. TESTING LOAD CIRCUIT
A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUT/OUTPUT
"=:X ?
2.0
0.8
0.45
<
:c
2.0
TEST POINTS
0.8
.
DEVICE
. UNDER
TEST
AC TESTING INPUTS ARE DRIVEN AT 2 4V FORA LOGIC "1" AND 045V FOR
A LOGIC "0" TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A lOGIC "1"
AND
FOR A LOGIC "0 "
a.sv
'1CL~150PF
CL =150pF
CL INCLUDES JIG CAPACITANCE
2-29
A~12'2C
8155H/8,156H/8155H-218156H-2
2048-BrT STATIC HMOS RAM
WiTH 1/0 PORTS AND TIMER
• 1 Programmable 6-Bit I/O Port
• Programmable 14-Blt Binary Counter/
• Single +5V Power Supply with 10%
Voltage Margins
• 30% Lower Power Consumption than
the 8~55 and 8156
• 100% Compatible with 8155 and 8156
• 256 Word x 8 Bits
• Completely Static Operation
• Internal Address Latch
.' 2 Programmable 8-Blt I/O Ports
TIm~
~.
. I
'
,
• Compatible with 8085AH, 8085A and
8088 CPU
• Multiplexed Address and Data Bus
• Available In EXPRESS
- Standalll Temperature Range
- Extended Temperature Range
The Intele 8155H and 8156H are RAM and I/O chips implemented in N-Channel. depletion load. silicon gate technology
(HMOS). to be used in the 8085AH and 8088 microprocessor systems. The RAM portion Is designed with 2048 static cells
organized as 256 x 8. They have a maximum access time of 400 ns to permit use with no walt states in 8085AH CPU.The
8155H-2 and 8156H-2 have maximum access times of 330 ns for use with the 8085AH-2 and the 5 MHz 8088 CPU.
The 110 portion consists of three general purpose 110 ports. One of the three ports can be programmed to be status
pins. thus allowing the other two ports to operate in handshake mode.
A 14-blt programmable counter/timer is also Included on chip to provide either a square wave or terminal count pulse
for the CPU system depending on timer mode.
PC,
PC.
10 ' M
ADo 7
256
x8
STATIC
RAM
*
ALE
RD
Wii
RESET
TIMER
TIMER CLK
TIMER OUT
,.,_'l1li;2 =
B
B
PAo-,
iii, 81 _ _ _2 - CE
Figure 1. Block Diagram
TIMER IN
PC,
RESET
pc.
pc.
PB,
TIMER OUT
PBs
101M
PB.
PB.
PB".,
G
Lvcc
vee
pc.
PCO~5
(+5VI ,
V"IOV)
RD
PB,
Wii
PB.
ALE
PB,
AO.
PB.
AO,
PA,
AO.
PAs
AO,
PAs
AO.
AO.
PA.
PA,
AD.
AO,
PA,
Vss
Plio
PA.
Figure 2. Pin Configuration
Intel Corporation A.sum.. No Reaponaibilty for the Use of Any Circuitry Other Than Circuitry Embodl.d In an Intel Product. No Other Clf'Cult Patent Licenses 8f8lmplied.
© INTEL CORPOIlATION. ,~,.
2-30
8155H/8156H/8155H-2I8156H-2
Table 1. Pin Description
Type
Name and Function
I
R•••t: Pulse provided by the 8085AH to initialize the system (connect to 8085AH RESET OUT). Input
high on this line resets the chip and initializes the three I/O ports to input mode. The width of RESET
pulse should typically be two 8085AH clock cycle times.
I/O
Addr.../Data: 3-state Address/Data lines that interface with the CPU lower 8-bit Address/Data Bus.
The 8-blt address is latched into the address latch inside the 8155H/56H on the falling edge of ALE. The
address can be eltherfor the memory section or the I/O section depending on the 10/M input. The 8-blt
data is either written into the chip or read from the chip. depending on the WR or RD input signal.
CE or Cl:
I
Chip Enable: On the 8155H. this pin is CE and is ACTIVE LOW. On the 8156H, this pin is CE and is
ACTIVE HIGH.
RD
I
Read Control: Input low on this line with the Chip Enable active enables and ADO_7 buffers. If 10/M pin
is low, the RAM content will be read out to the AD bus. Otherwise the content of the selected I/O port or
command/status registers will be read to the AD bus.
WR
I
Write Control: Input Iowan this line with the Chip Enable active causes the data on the Address/Data
bus to be written to the RAM or I/O ports and command/status register, depending on lo/fi:l
ALE
I
Address Latch Enable: This control signal latches both the address on the ADo_7 lines and the state
of the Chip Enable and 101M Into the chip at the falling edge of ALE.
I
I/O Memory: Selects memory if low and I/O and command/status registers if high.
Symbol
RESET
ADo_7
10/M
PAO_7(S)
I/O
Port A: These 8 PinS are general purpose I/O pins. The in/out dlrecllon IS selected by programming
the command register.
PBO_7(8)
I/O
Port B: These 8 pins are general purpose I/O pinS The in/out direction is selected by programming
the command register
PCo_s(6}
I/O
Port C: These 6 pinS can function as either Input port, output port, or as control Signals for PA and PB.
Programming is done through the command register. When PCo-s are used as control signals, they
will provide the follOWing:
PCo - A INTR (Port A,lnterrupt)
PC 1 - ABF (Port A Buffer Full)
PC2 - A STB (Port A Strobe)
PC3 - B INTR (Port B Interrupt)
PC4 - B BF (Port B Buffer F'ull)
PC s - B STB (Port 6 Strobe)
TIMER IN
I
TIMER OUT
0
Timer Input: Input to the counter-timer.
Timer Output: This output can be either a square wave or a pulse, depending on the timer mode.
Vee
Voltage: + 5 volt supply.
Vss
Ground: Ground reference.
FUNCTIONAL DESCRIPTION
I
I
I
The 8155H/8156H contains the following:
• 2k Sit Static RAM organized as 256 x 8
• Twb 8-bit 110 ports I PA & PS I and one 6-bI! 110 port I PC)
• 14-bit timer-counter
The 101M 1I0/Memory Select I pin selects either the five
registers ICommand, Status, PAo-?, PSO-?, PCO-51 or
the memory IRAMI portion.
The 8-oit address·on the AddresslData lines, Chip Enable
input CE or CE, and I DiM ,pre all latched on-chip at the
falling edge of ALE
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
L ___ ~_
.
_________
.JI
Figure 3. 8155H/8156H Internal Registers
2-31
AFN·0196OC
8155H/8156H/8155H-218156H-2
CE(815SH)
\
/
'\
/
\
/
\
/
\
OR
CE(8l5SH)
101M
\
X
ADDRESS
X
\
DATA VALID
,
Al E
NOTE: FOR DETAILED TIMING INFORMATION, SEE FIGURE 12 AND A.C. CHARACTERISTICS.
Figure 4. 8155H/8156H On-Board Memory Read/Write Cycle
PROGRAMMING OF THE
COMMAND REGISTER
r=
ITM' TM;I 'Eel 'EAlpc,1 PC,
The command register consists of eight latches. Four
bits (0-31 define the mode of the ports, two bits 14-51
enable or disable the interrupt from port C when it acts
as control port, and the last two bits 16-71 are forthe timer.
'--.---1
pelPA]
.
The command register contents can be altered at any
time by using the 110 address XXXXXOOO dunng a WRITE
operation with the Chip Enable active and lo/liii = 1. The
meaning of each bit of the command byte is defined in
Figure 5. The contents of the command register may
never be read.
-
,
DEFINESPA..7
}
DEFINES PBO.7
0'" INPUT
1 '" OUTPUT
OQ=ALTl
,
DEFINES peO_5 {
11=ALT2
01 = AL T 3
10=AlT4
L -_ _ _ _ _ _ _ _ _ _ _ _
'-______~______•
READING THE STATUS REGISTER
The status register consists of seven latches, one for each
bit. six (0-51 for the status of the ports and one 161 for the
status of the timer.
~~~~~~~RTA
~~¢eBRLi;~RT
B
1
}
= ENABLE
0= DISABLE
00
=
NOP - DO NOT AFFECT COUNTER
6PERATION
01
=
STOP - NOP IF TIMER HAS NOT STARTED;
STOP COUNTING IF THE TIMER IS
RUNNING
10 = STOP AFTER Te - STOP IMMEDIATELY
AFTER PRESENT
~TIMER COMMAND
re
IS REACHED (NOP
IF TIMER HAS NOT STARTED)
11
=
START - LOAD MODE AND CNT LENGTH
AND STAAT IMMEDIATELY AFTER
lOADtNG !IF TIMER IS NOT PRESENTLY
The status of the timer and the 1/0 section can be polled
by reading the Status Flegister (Address XXXXXOOO).
Status word format is shown in 'Figure 6. Note that you
may never write to the status register since the command
register shares the same 1/0 address and the command
register IS selected 'when a write to that address is issued.
RUNNING) IF TIMER IS RUNNING, START
THE NEW MODE AND CNT LENGTH
IMMEDIATEl Y AFTER PRESENT TC
IS REACHED
Figure 5. Command Register Bit Assignment
2-32
AFN'Ol960C
inter
8155H/8156H/8155H-2/8156H-2
interrupt that the 8155H sends out. The second is an
output signal indicating whether the buffer is full or
empty, and the third is an input pin to accept a strobe
for the strobed input mode. (See Table 2.)
When the 'C' port is programmed to either ALT3 or AL T4,
the control signals for PAand ~Bare initialized as follows:
PORT A INTERRUPT REQUEST
L~
PORT A INTERRUPT ENABLE
CONTROL
SF
INTR
INPUT MODE
Low
Low
OUTPUT MODE
Low
High
PORr B INTERRUPT REQUEST
STB
Input Control
Input Control
PORT A BUfFER FULL/EMPTY
(INPUT/OUTPUT)
' - - - - - - - _ PORT B BUFFER FULl/EMPTY
(INPUT/OUTPUT)
' - - - - - - - - - _ PORT B IN·TERRUPT ENABLED
.
' - - - - - - - - - - - - - TIMER INTERRUPT (THIS BIT
IS LATCHED HIGH WHEN
TERMINAL COUNT IS
REACHED, AND IS RESET TO
LOW UPON READING OF THE
CIS REGISTER AND BY
HARDWARE RESET)
I/O ADDRESSSELECTION
A7 A6 AS A4 A3 A2 A1 AD
X
X
X
X
X
X
Figure 6. Status Register Bit Assignment
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
1
1
0
1
1
0
0
0
1
1
1
Interval Command/Status Register
General Purpose L'D Port A
General Purpose 1/0 Port B
Port C - General Purpose 110 or Control
Low~Order 8 bits of Timer Count
High 6 bits of Timer Count and 2 bits
of Timer Mode
X Don't Care
t
110 Address must be qualified by CE = 1 (8156H) or CE
order to select the approprrate register
'=
0 (8155H) and 101M"" 1m
INPUT/OUTPUT SECTION
The I/O section of the 8155H/8156H consists of five registers: (See Figure 7.)
• Command/Status Register (C/S) - Both registers are
assigned the address XXXXXOOO. The CIS address
serves the dual purpose.
When the CIS registers are selected during WRITE
operation, a command is written into the command
register. The contents of this register are not accessible
throug,h the pins.
When the CIS (XXXXXOOO) is selected during a READ
operation, the status information of the I/O ports and
the timer becomes available on the ADo-7 lines .
Figure 7. I/O Port and Timer Addressing Scheme
Figure 8 shows how I/O PORTS A and B are structured
within the 8155H and 8156H:
8155Hi8158H
ONE BIT OF PORT A OR PORT B
• PA Register - This register can be programmed to be
. either input or· output ports depending on the status of
the contents of the CIS Register. Also depending on
the command, this port can operate in either the basIc
mode or the strobed mode (See timing diagram). The
I/O pins assigned in relation to this register are PAO-7.
The address of this register is XXXXX001.
• PB Register - This register functions the same as PA
Register. The 110 pins aSSigned are P80-7. The address
of this register is XXXXX010 .
• PC Register - This register has the address XXXXX011
and contains only 6 bits. The 6 bits can be programmed to be either input ports, output ports or as control
signals for PA and PB by properly programming the
AD2 and AD3 bits of the CIS register.
When PCO-5 is used as a control port, 3 bits are
assigned for Port A and 3 for Port B. The first bit is an
NOTES·
(1) OUTPUT MODE }
(2) SIMPLE INPUT
(3) STROBED INPUT
(4)
MULTIPLEXER
CONTROL
= 1 FOR OUTPUT MODE
= 0 FOR INPUT MODE
READ PORT = (lO/M=l) _ (RD=O) _ (CE ACTIVE) _ (PORT ADORESS SELECTED) ,
WRITE PORT= (l0/M=1) _ (WFi:=O)_ (CE ACTIVE)- (PORT ADDRESS SELECTED)
'Figure 8. 8155H/8156H Port Functions
AFN·0196OC
81 55.H/81 56H/8155H.218156H~2
Table 2. Port Control Assignment
ALT 2.
ALT 1
Pin
PCO
PC1
PC2
PC3
PC4
, PC5
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
ALT3
ALT4
A INTR (Port A Interrupt)
A BF (Port A Buffer Full)
A STB (Port A Strobe)
Output Port
Output Port
Output Port
A INTR (Port A Interrupt)
A BF (Port A Buffer Full)
A STB (Port A Strobe)
B INTR (Port B Interrupt)
B BF (Port B Buffer Full)
B STB (Port B Strobe)
Note In the diagram that when the 1/0 ports are programmed to be output ports, the contents of the output
ports can still be read by a READ operation when approprlatelyaddressed.
TIMER SECTION
The timer is a 14-bit down-counter that,counts the TIMER
IN pulses and provides either a square wave or pulse
when terminal count (TCI is reached.
The outputs of the 8155H/8156H are "glitch-free" meaning
that you can write a "1" to a bit position that was previously "1" and the level at the output pin will not change,
The timer has the I/O address XXXXX100forthe low order
byte of the register and the I/O address XXXXX101 for
the high order byte of the register, (See Figure 7,)
Note also that the output latch is cleared when the port
enters the Input mode, The output latch cannot be loaded
by writing to the port if the port is in the input mode. The
result is that each time a port mode is changed from input
to output, the output pins will go low, Wheri the8155H/56H
is RESET, the output latches are all cleared and all 3 ports
enter the input mode,
To program the timer, the COUNT LENGTH REG is
loaded first, one byte at a time, by selecting the timer
addresses, Bits 0-13 of the high order count register will
specify the length of the next count and bits J4-15 of the
high order register will specify the timer output mode
(see Figure 10). The value loaded into the count length
register can have any value from 2H through 3FFH in
Bits 0-13.
When in the AL T 1 or AL T 2 modes, the bits of PORT C
are structured like the diagram above in the simple input
or output mode, respectively.
4
Reading from an input port with nothing connected to the
PinS will provide unpredictable results.
Mz
Figure 9 shows how the 8155H/8156H I/O ports might be
configured in a typical MCS-85 system.
Ml
I
T131 T121 Tlll T lOl T91
II
I
I
Te
I
I
I
MSB OF CNT LENGTH
TIMER MODE
T7
2
4
6
Tsl Tsl T4
I
.1
T31
Tzi
Tl
0
I I
To
I
I
LSB OF CNT LENGTH
Figure 10. Timer Format
.--r
-"
PORT A
PORT C'
OUTPUT
There are four modes to choose from: M2 and M1 define
the timer mode, as shown in Figure 11,
TO 8085AH RST INPUT
PORT A
A INTR ($'IGNALS DATA RECEIVED)
t
TIMER OUT WAVEFORMS
' ' 'DATA
' ..,,"
• He
A srB,.,""
(ACKNOWL
RECEIVED)
}
TO/FROM
• B STB (LOADS PORT B LATCH)
J
6 SF (SIGNALS BUFFER IS FULL)
B INTR (SIGNALS BUFFER
READY FOR READINGI
PORT B A
v
INPUT
PERIPHERAL
INTERFACE
1
START
COUNT
MODE
BITS
M2
'0
TO INPUT PORT (OPTIONAL)
,
M1
(TERMINAL)
COUNT
_____ l ____ _
1 SINGLE
SQUARE WAVE
3 SINGLE
PULSE ON
TERMINAL COUNT
4 CONTINUOUS
PULSES
=
COUNT
2 CONTINUOUS
SQUARE WAVE
TO eOe5AH RST INPUT
Figure 9. Example: Command Register
TERMINAL
~
00111001 '
2-34
u---.:- ---------
v
Figure 11. Timer Modes
AFN,Ol960C
inter
8155H/8156H/8155H-218156H-2
Bits 6-7 (TM2 and 'TM1) of command register contents
are used to start and stop the counter. There are four
com";1ands to choose from:
TM2
TM1
o
o
0
NOP - Do not affect counter operation.
STOP - NOP if timer has not started.;
stop countil"1g if the timer is running.
o
STOP AFTER TC - Stop immediately
after present TC is reached (NOP iftimer
has not started)
START - Load mode and CNT length
and start immediately after loading (if
timer is not presently running). If timer
is running, start the new mode and CNT
length immediately after present TC is
reached.
Note that while the counter is counting, you may load a
new count and mode into the count length registers.
Before the new count and mode will be used by the
counter, you must issue a START command to the
counter. This applies even though you may only want to
change the count and use the previous mode.
The counter in the 8155H is not initialized to any particular
mode or count when hardware RESET occurs, but RESET
does stop the counting. Therefore, counting cannot begin
following RESET until a START command is. issued via the
CIS register.
Please note that the timer circuit on the 8155H/8156H chip
is designed to be a square-wave timer, -not an event
counter. To achieve thiS, it counts down by twos twice
in completing one cycle. Thus, its registers do not contain values directly representing the number of TIMER IN
pulses received. You cannot load an initial value of 1 into
the count register and cause the timer to operate, as its
terminal count value is 10 (binary) or 2 (decimal). (For
the detection of single pulses, it is suggested that one
of the hardware interrupt pins on the 8085AH be used.)
After the timer has started counting down, the values
residing in the count registers can be used to calculate
the actual number of TIMER IN pulses required to complete the timer cycle if desired. To obtain the remaining
count, perform the following operations in order:
1. Stop the count
2. Read in the 16-bit value from the count length registers
3. Reset the upper two mode bits
In case of an odd-numbered count, the first half-cycle
of the squarewave output, which is high, is one count
longer than the second (lOW) half-cycle, as shown in
Figure 12.
4. Reset the carry and rotate right one position al116 bits
~ro~h~~
.
5. If carry is set, add 1/2 of the full original count (112 full
count - 1 if full count is odd).
Note: If you started with an odd count and you read the
count length register before the third count pulse occurs,
you will not be able to discern whether one or two counts
has occurred. Regardless of this, the 8155H/56H always
counts.out the right number of pulses in generating the
TIMER OUT waveforms.
NOTE 5 AND 4 REFER TO THE NUMBER OF CLOCKS IN THAT TIME PERIOD
Figure 12. Asymmetrical Square-Wave Output
Resulting from Count of 9
2-35.
AFN·Ol96OC
~15S.H/8156H/8155H~218156H.2
808SA MINIMUM SYSTEM CONFIGURATION
Figure 13a shows a minimum system using three chips,
.containing:
•
•
•
•
•
256 Bytes RAM
2K Bytes ROM
38 1/0 Pins
1 Interval Timer
4 I nterrupt Levels
8085 MINIMUM SYSTEM CONFIGURATION
t-..
AS-1S
v
A
AOO·7
-=
ALE
. 8085AH
RiS
;:..
-
~
-
101M
-
eLK
-
RESET OUT
READY
-
Vee
TIMER
RESET
T6~~R_
WR Ri5
IN
B
ALE
L.j
-'-CONTROL
7-
eE'(
I
LATCHES
I
'101M
~
7:~~" 7-~~
CE
Igi
ALE
RiSIKWi eLK RST
RDY
I
I
8355 I ROM + I/O I
256 x 8
RAM
8755A [PROM + I/OJ
OR
\
8158H
-
I
~~~~
,
'B BB
BB
,
Figure 13a. 8085AH Minimum System Configuration (Memory Mapped 1/0)
2-36
. AFN-01960C
inter
8155H/8156H/8155H-218156H-2
• 381/0 Pins
8088 FIVE CHIP SYSTEM
Figure 13b shows a five
~hip
• 1 Interval Timer
system containing:
• 2 Interrupt Levels
• 1.2SK Bytes RAM
• 2K Bytes. ROM
/'
I
1~t-
Vss Vee
I I
POR!~
CE
~t--'-WR
Ali
PORT
"&111-2 8
00
(8)
. ALE
PORToo
DATAl
C
(8)
ADDR
IN_
101M TIMER
OUT
r-
RESET
A8-A19
~.
I\"
lOW
V
CLKADo- AD7
Ali
h
r~
/1
,--
ADDRIDATA
ALE
.. r-..
L.:8088
RST
®
ClK
READY ~
ALE
f-
f-
Rli
I--
I-- I-
WR
1--'
101M
f'f-
.--
REli
828'
RESET
8755A-2
DATAl
ADDR
101M
I
PORT
~--' RESET
f-
00
'355-2/
'. V
MN/MX I--Vee
O
ROY'
AS _10
r--
r - READY
.,r l"
PORT
A
CE
B
READY
00·
Vee
~-'
, I II
lpROG
Vss Vee VDD
Vee
WR
......
Ali
CD
•
eel 818502
ALE
If-
11'1I~t-
Cli.
CE,
"e.'"
APo·,
! !.
Vss
,
Vee·
7
Figure 13b. 8088 Five Chip System Configuration
2-'37
AFN·Ol98OC
,
8155H!8158H18155H-218158H-2
ABSOLUTE MAXIMUM RATINGS·
TemperatureUnderBias ................ 0·Cto+70·C
Storage Temperature ..•............ -65·C to +150·C
Voltage on Any Pin
With Respectto Ground ............... -0.5V to +7V
Power Dissipat jon . .'........................... 1.5W
D,C. CHARACTERISTICS
(fA =
,
"'r:'"
0').
~
o·c to 700C. Vee = 5V ± 10%)
Parameter
Min.
Max.
Units
V'l
Input Low Voltage
-0.5
0.8
V
2.0
Vcc+O.5
V
0.45
V
Iol = 2mA
V
IoH = -4OO1tA
V'H
Input High Voltage
VOL
Output Low Voltage
VoH
Output High Voltage
I'l
Input Leakage
±10
IlO
Output Leakage Current
±10
ItA
ItA
Icc
Vee Supply Current
125
mA
l'llCE)
Chip Enable Leakage
8l55H
8l56H
+100
-100
p.A
p.A
2.4
(fA
.
'NOTICE: Stresses above those listed (/fider "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functionaloperation of the device at these or any other conditions above
those indicated in the operational sections, of this
specification is not implied. Exposure to absolute maximum rating conditions fOf extended periods may affect
device reliability.
Symbol
A.C. CHARACTERISTICS
,
Test Conditions
OV"" VIN "" Vec'
0.45V .;;; VOUT .;;; VCC
OV"" VIN "" Vec
= o·c to 700C. Vce = 5V ±10%)
8155H18156H
8155H-218156H-2
Symbol
Parameter
tAL
Address, to Latch Set Up Time
50
30
tlA
Address Hold Time after Latch
80
30
ns
tlC
Latch to READIWRITE Control
100
40
ns
tRO
Valid Data Out Delay from READ Control
Min.
Max.
Min.
170
400
Max.
Units
ns
140
ns
330
ns
tAD
Address Stable to Data Out Valid
tLL
Latch Enable Width
tROF
Data Bus Float After READ
0
tCl
READIWRITE Control to Latch Enable
20
10
ns
tcc
READIWRITE Control Width
250
200
ns
tow
Data In'to WR ITE Set Up Time
150
100
ns
two
Data In Hold Time After WR ITE
25
25
ns
tRv
Recovery Time Between Controls
300
200
twp
WR ITE to Port Output
tPR
Port Input Setup Time
70
tRP
Port Input Hold Time
50
tSBF
Strobe to Buffer Full
tss
Strobe Width
tRBE
READ to Buffer Empty
tSI
Strobe to I NTR On
100
100
0
400
80
ns
ns
300
,
ns
50
ns
10
ns
400
300
ns
400
300
' ns
400
300
hs
200
,
ns
70
ns
150
AFN-019BOC
intJ
8155H18156H/8155H-218156H-2
A.C. CHARACTERISTICS
(Continued) (TA = O·C to 70·C. Vee = 5V :t10%)
8155H/8156H
Symbol
Parameter
Min.
8155H-218156H-2
Max.
Min.
Max.
400
tRDI
READ to INTR Off
tPSS
Port Setup Time to Strobe Strobe
Units
300
50
ns
ns
0
tl'HS
Port Hold Time After Strobe
tSBE
Strobe to Buffer Empty
400
300
ns
tWBF
WR ITE to Buffer Full
400
300
ns
tWI
WR ITE to I NTR Off
400
300
ns
tTL
TIMER-IN to TIMER-OUT Low
400
300
ns
tTH
TIMER-IN to TIMER-OUT High
400
300
ns
tRDE
Data Bus Enable from READ Control
tl
t2
.120
100
ns
·10
10
ns
TIMER-IN Low Time
80
46
ns
TIMER-IN High Time
120
70
ns
A.C. TESTING INPUT, OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
INPUT/OUTPUT
"-V>-~~
TEST POINTS
O.B
0.45
<"')C
DEVICE
UNDER
TEST
O.B
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1" AND 0 45V FOR
TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC 1
A LOGIC
AND 08V FOR A LOGIC 0
o·
rr
C ':150 P F
C, = 150pF
C, INCLUDES JIG CAPACITANCE
2-44
,
AFN-00201P
inter
8185/8185-2
1024 x 8-BIT STATIC RAM FOR MCS-SS-
• Multiplexed Address and Data Bus
• Low Standby Power Dissipation
• Directly Compatible with 8085A
and IAPX 88 Microprocessors
• Single +5V Supply
• Low Operating Power Dissipation
• High Density 18·Pln Package
The Intel llD 8185 is an 8192-bit static random access memory (RAM) organized as 1024 words by 8-bits using N-channel
Silicon-Gate MOS technology. The multiplexed address and data bus allows the 8185 to, interface directly to the 8085A and
iAPX 88 microprocessors to provide a maximum level of system integration.
The low standby power dissipation minimizes system power requirements when the 8185 is disabled.
The 8185-2 is a high-speed selected version of the 8185 that is compatible with the 5 MHz 8085A-2 and the5 MHz iAPX 88.
Yee
ADo
es
CE,
~
IIIW
LOGIC
lID
WR
ALE
DATA
BUS
BUFFER
ADo-AI>,
lK . ,
RAM
MEMORY
ARRAY
AD,
lID
AD2
WR
ADa
AU:
AD,
es
AD.
CE,
AIle
CE2
AI>,
As
vss
As
ADcr-AD7 ADDIIES1I/IIATAUNES
CE,
CE2
_UNES'
CHIPIELECT
CHIP ENAIILE (10/11)
CHIP ENAIIU!
_
LATCH ENABLE
WR
WRITE ENABLE
As.Ag
cs
ALE
As.
As
=====L---=J
ALE
r
Figure 2. Pin Configuration
Figure 1. Block Diagram
Intel Corporation As.um•• No Responlibltty for the Uae of Any Circuitry Other Than Circuitry Embodied In an Intel Product No Other Circuit Patent Licene•• .,.Implled
, @INTEL'CORPORATION,
'9ao
245
A~l230C
8185/8185-2
FUNCTIONAL DESCRIPTION
The 8185 has been designed to provide for direct interface
to the multiplexed bus sfructure and bus timing of the
8085A microprocessor.
----
At the beginning of an 8185 memory access cycle, the 8bit address on ADo-7, As and As, and the status of CEl and
CE2 are all latched internally in the 8185 by the falling edge
of ALE. If the latched status of both CEl and CE2 are
active, the 8185 powers its!!1f up, but no action occurs until
the CS line goes low and the appropriate Ri5 or WR control
signal Input is activated.
CE 2
CS
8185 StatuI
1
X
X
0
Power Down and
Function Disablell]
X
0
X
0
Power Down and
Function Disablell]
III
RESET IN
HOl.D I HlOA
RST7,S
R516,5
SOD
8085A
R8T5,5
SID
' S,
INTR
RESeT
mTA
ADOR
IIfI-
Sol-
OUT
ADDR/
OAT A ALE AD WR 101M
ROY eLK
T
Vi'
181
[~-
W
CE
POR!W
WR
PORT
8
II
Ali 815s B
PORT~
ALE
DATAl
ADDR
IO/~
C
IN
TIMER
RESET
Table 1.
Truth Table for
Power Down and Function Enable
CE l
Vss Vee
X2
X,
TRAP
181
The Cs input is not latched by the 8185 In order to allow
the maximum amount of time for address decoding in
selecting the 8185 chip. Maximum power consumption
savings will occur, however, ohly when CEl and CE2 are
activated selectively to power down the 8185 when it is not
in use. A possible connection would be to wire the 8085A's
101M line to the 8185's CElinput, thereby keeping the
8185 powered down during 1/0 and interrupt cycles.
(CS*)12]'
DD~
OUT
,
f:=
'OW
Ali
ALE
[t~=
i
PORT
A
CE
-" As to
:
~
8355/
8755A
DATAl
ADDR
101M
RESET
0
1
1
0
Powered Up and
Function Disablell]
0
1
0
1
Powered Up and
Enabled
pV
ROY
...- ClK
.1 1J
t
Vss Vee Voo PROG
NOTES: •
X: Don't Care.
t: Function Disable implies Data Bus in high impedance state
and not writing.
2: CS' = (CEl = 0). (CE2 = 1),0 (CS = 0)
CS' = 1 signifies all chip enables and chip select active
WR
RD
CE,
8185
ALE
I~I~-
CS, eE2
As. Ag
Table 2.
Truth Table for
Control and Data Bus Pin Status
(CS*) RD
PORT
B
A°0-7
t vL
Vss
Vee
ADo-7 During Data
WR Portion of Cycle
8185 Function
X Hi-Impedance
Vee
No Function
0
X
1
0
1
Data from Memory Read
1
1
0
Data to Memory
Write
1
1
1
Hi-Impedance
Reading, but not·
Driving Data Bus
Figure 3. 8185 in an Me8-85 System
4 Chips:
2K Bytes ROM
1.25K Bytes RAM
38 liD Lines
1 CounterlTimer
2 Serial I/O Lines
5 Interrupt Inputs
NOTE:
X: Don't Care.
2-46
AFN-Q1230C
inter
8185/8185-2
IAPX 88 FIVE CHIP SYSTEM:
•
•
•
•
•
1.25 K Bytes RAM
2 K Bytes ROM
38110 Pins
1 Internal Timer
2 Interrupt Levels
Vss Vee
j
j
POR1~
~
I It-
~j----_WR
POR~
Rii
~
(8)
8155-2
ALE
DATAl
ADOR
PORT~
C
(6)
IN_
101M TIMER
OUT
RESET
..
As
,---
ADDR
A19
ADo- AD7
ClK
~
V
",
ADDRIDATA
,---
lOW
'Rii
~
ALE
~~
~.
~4? ' '.,
~
GND
(VSS)
GND
MANUAL
RESET
rDl
X,
, - RST
®
X,
ClK
READY
t--
8284A
ALE
f--
c--
Rii
f-- f-
WR
f-f--
101M
f--
..----
f--
8355-21
8755A·2
I
101M
PORT
RESET
B
~
Vee
READY
iOR
111
f--
RESET
RCYl
~
DATAl
ADOR
,---
RES
A e•1o
-V
READY
MNIMX -Vee
Vee
PORT
A
CE
?~
8088
I--
..J
L
pROG
Vss Vee Voo
Vee
-
....
ViR
Rii
CD
eEt.
81.2
ALE
If--
Irf-\--
es.
CE,
As. Ag
ADO_7
1 Vee1
v's
Figure 4. iAPX 88 Five Chip System Configuration
2-47
AFN-OI230C
\.
,8185/8185-2
-NOTICE: Stresses above those'listed under "Absolute
Maximum Ratings" may cause permanent' damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ...•......•... o·c to +70·C
Storage Temperature .•...•.•.••... -65·C to +150·C
Voltage on Any Pin
with Respect to Ground .............• -0.5V to +7V
Power Dissipation ..••••...••.................. 1.5W
D.C. CHARACTERISTICS
(TA =
o·c to 70·C. Vee =
5V ± 5%)
Min.
Max.
Units
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vee+0.5
V
VOL
Output Low Voltage
0,45
V
VOH
Output High Voltage
ill
Input Leak'age
±10
!,A
OV ,;;VIN .;;VCC
IlO
Output Leakage Current
±10
IJA
0.4SV ::;; VOUT ::;; Vee
Icc
Vce Supply Current
Powered Up
Powered Down
100
35
mA
mA
Symbol
Vil
Parameter
A.C. CHARACTERISTICS
(TA
Test Conditions
IOl = 2mA
2.4
IOH = - 400!,A
= o·c to 70·C. Vee = 5V ± 5%)
8185-2
8185
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
tAL
Address to Latch Set Up Time
50
30
ns
tlA
Address Hold Time After Latch
80
30
ns
tLe
Latch to READ/WRITE Control
100
40
tRO
Valid Data Out Delay from READ Control
170
140
ns
lLo
ALE to Data Out Valid
300
200
ns
. ILL
Latch Enable Width
~us
70
100
Float After READ
0
ns
0
ns
ns
Data
tel
READ/WRITE Control to Latch Enable
20
10
ns
tee
READ/WRITE Control Width
250
200
ns
tow
Data In to WRITE Set Up Time
150
150
ns
two
Data In Hold Time After WRITE
20
20
ns
tse
Chip Select Set Up to Control Line
10
10
ns
tcs ,
Chip Select Hold Time After Control
10
10
ns
tAleE
Chip Enable Set Up to ALE Falling
30
10
ns
tlACE
Chip Enable Hold Time, After ALE
50
30
ns
2-48
100
80
tROF
AFN·01230C
inter
8185/8185-2
A.C. TESTING INPUT, O~TPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
INPUT/OUTPUT
,
u~u >
TEST POINTS
OAS
0.8
<")C
DEVICE
UNDER
TEST
IJCL_nOPF
0,'
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC "I" AND 0 45V FOR
A LOGIC "0" TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC "I"
AND 0 81/ FOR A LOGIC "0 "
CL = 150'pF
CL INCWDES JIG CAPACITANCE
WAVEFORM
ALE
(CE,-O).
IC E2'"
WR,Fffi
ADo-AI>,
IA., A,)
(READ CYCLE)
~-----~c--~---'I
ADO·AD?
(WRITE CYCLE)
\'--_-.J.I_~
ISELECTED)
IDESELECTED)
2-49
AFN-0123OC
8205
HIG·H SPEED 1 OUT OF 8 BINARY DECODER
• Low Input Load Current - .25 mA
max., 1/6 Standard TTL Input Load
• Minimum Line Reflection - Low
Voltage Diode Input Clamp
• 1/ 0 Port or Memory Selector
• Simple Expansion - Enable Inputs
• High Speed Schottky Bipolar
Technology - 18ns Max. Delay
• Outputs Sink 10 mA min.
• 16·Pin Dual·ln·Line Ceramic or
Plastic Package
• Directly Compatible with TTL Logic
Circuits
The Intele 8205 decoder can be used for expansion of systems which utilize input ports, output ports, and memory
components with active low chip select input. When the 8205 is enabled, one of its 8 outputs goes "low," thus a single row
of a memory system is selected. The 3-chip enable inputs on the,8205 allow easy system expansion. For very large systems,
8205 decoders can be cascaded such that each decoder can drive.8 other decoders for arbitrary memory expansions.
The 8205 is packaged in a standard 16-pin dual in-line package, and its performance is specified over the temperature
range of O°C to +75°C, ambient. The use of Schottky barrier diode clamped transistors to obtain fast switching speeds
results in higher performance than equivalent devices made with a gold diffussion process.
AO
A,
Ao
16
Vee
A,
A,
15
00
A,
14
0,
E,
13
0,
8205
8205
ADDRESS
" " "
L
H
L
H
L
H
H
L
L
H
H
L
L
H
H
L
L
L
L
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
E,
E,
12
03
E,
E3
11
0,
E,
0,
10
°5
GRD
,.9
06
ENABLE
E, E, E,
L
L
L
L
L
L
L
L
L
H
L
H
H
L
H
L
L
L
L
L
L
L
L
L
L
H
H
L
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
a
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
,
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
2
,
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
OUTPUTS
4
G
G
I
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
.H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
Figure 1. Logic Symbol
AO A2
E 1 E3
ADDRESS INPUTS
ENABLE INPUTS
00 0,
DECODED OUTPUTS
Figure 2. Pin Configuration
2·50
8205
FUNCTIONAL DESCRIPTION
Decoder
The 8205 contains a one out of eight binary decoder. It accepts a three bit binary code and by gating this input, creates
an exclusive output that represents the value of the input
code.
...
0-;
A,
6~
A,
0,
if)
DECODER
For example, if a binary code of 101 was present on the AO,
A 1 and A2 address input lines, and the device was enabled,
an active low signal would appear on the ii5 output line.
Note that all of the other output pins are sitting at a logic
high, thus the decoded output is said ~o be exclusive. The
decoders outputs will follow the truth table shown below in
the same manner for all other input variations.
0;
0;
o~
0;
Enable Gate
ENABLE GATE
E,
r,
When using a decoder it is often necessary to gate the outputs with timing or enabling signals so that the exclusive
output of the decoded value is synchronous with the overall
system.
(f; E2 E3)
E,
Figure 3. Enable Gate
The 8205 has a bu ilt·in function for such gating. The three
enable inputs (Ei, E2, E3) are ANDed together and create
a single enable signal for the decoder. The combination of
both active "high" and active "low" device enable inputs
provides the designer with a powerfully flexible gating function to help reduce package count in his system.
ADDRESS
A, A z
Ao
L
2-51
L
L
H
L
L
H
L
L
L
H
H
L
H
L
L
L
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
X
X
X
X
X
X
X
ENABLE
OUTPUTS
E,
E,
E3
a
1
2
3
4
S
6
7
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
H
H
H
H
H
H
H
H
'i
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
L
L
L
H,
H
L
H
L
H
H
L
H
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
..,
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
AFN-Q0204C
inter
8205'
Applications of the 8205
ray of 8205s can be used to create a simple interface to a
24K memory system.
The 8205 can be used in a wide vllriety of applications in
microcomputer systems. 1/0 ports can be decoded from the
address bus, chip select signals can be generated to select
memory devices and the type of machine state such as in
8008 systems can be derived from a simple decoding of the
state lines (SO, S1, S2) of the 8OO8,CPU. .
'
I/O PORT DECODER
Shown in the figure below is a typical application of the
8205. Address input lines are decoded by a, group of 8205s
(3). Each input has a binary weight. For example, AO.is as·
signed a value of 1 and is the LSB; A4 is assigned a value of
16 and is the MSB: By connecting them to the decoders as
shown, an active low signal that is exclusive in nature and
represents the value of the input address lines, is available at
the outputs of the 8205s.
This circuit can be used to generate enable signals for 1/0
ports or any other decoder related application.
Note that no external gating is required to decode up to 24
exclusive devices and that a simple addition of an inverter
or two will allow expansion to even larger decoder net·
wor1
USing a very similar circuit to the 1/0 port decoder, an ar-
.,
.,
A,
A,
A,
0,
.,
A"
A,
Au
A,
Au
A,
E,
A,
E,
'N
E,
Au
e;
0, :>--'
V"
E,
0,
.,
0. :>--'
EN
"
E,
13
;;
14
E,
"
.,
A,
17
A,
,.
E,
.,
E,
~
0; :>--'
-A,
0, :>--'cs"
'Z05
NUMBERS
I
;;
,
I
E,
L=:A'
A,
"
8206
21
22
23
Figure 4. 110 Port DeCQder
0; :>--
E,
0;
.,
0. :>---
;;
CHIP
SELECTS
o,p---o,p---o;p---0, p----
~.,
2.
0,:>--'fS';,
0; P'-- ~
o,p---- CS;;
0; p---- es,.
o;p---- cr.,
E,
GNO
:>--'
-A,
PORT
,.
.205
EN
1.
11
=>=--,es,
~ :>--'
,
....
0;
E,
.,
A,
0; :>--'es,
0; :>--'CS,
A"
I
A,
0, :>--'cs,
0, :>--'CS,
8 ...
8206
A,
~~MORIES
., .. IL _ _ _ _ _ _ _ _
D---
0; :>---
Figure 5. 24K Memory Interface
2-52
AFN-G0204C
inter
8205
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias:
Ceramic .......................... -65°C to +125°C
Plastic ............................ -65°C to + 75°C
Storage Temperature ............... -65°C to +160°C
All Output or Supply Voltages ........ -0.5 to +7 Volts
All Input Voltages .................. -1.0 to +5.5 Volts
Output Currents ............................. 125 rnA
-NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or at any other condition above
those indicated in the operational sections of this specification is not .implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
D.C. CHARACTERISTICS (TA = O°C to + 75°C, Vee = 5V ±5%)
Symbol
Limit
Parameter
f-Mln~-
IR
INPUT LOAD CURRENT
._-----INPUT LEAKAGE CURRENT
Ve
INPUT FORWARD CLAMP VOLTAGE
VOL
OUTPUT "LOW" VOLTAGE
IF
-_.
Max.-
Unit
-025
rnA
Test Conditions
Vee = 5.25V. V F - 0.45V
10
~A
Vee = S 25V. V R = S.2SV
-10
V
Vee = 4 75V. Ie = -5.0 rnA
.---~
V
045
------V
OUTPUT HIGH VOLTAGE
24
._---------_. ------ - --- - - - - - _ . - - _ .
INPUT "LOW" VOLTAGE
V
085
-- .... - - - - - - INPUT "HIGH'" VOLTAGE
20
V
- - - - - - - f---- - - - - - -40
-120
rnA
OUTPUT HIGH SHORT
CIRCUIT CURRENT
Vee = 4.7SV. IOL = 10.0 rnA
Vox
OUTPUT "LOW" VOLTAGE
@ HIGH CURRENT
lee
POWER SUPPL Y CURRENT
..
VOH
VIL
V IH
Ise
----
Vee =4.75V.l oH = -1.SrnA
--
Vee
= 5 OV
= 5.0V
= S.OV.
----VOUT
V
Vee
= S.OV.
lox
rnA
Vee
= S 25V
Vee
Vee
"---
= OV
-------.
08
70
= 40 rnA
A.C. CHARACTERISTICS (TA = O°C to + 75°C, Vee = 5V ±5%; unless otherwise specified)
Symbol
Parameter
Max. Limit
'++
ADDRESS OR ENABLE TO
OUTPUT DELAY
t -+
t+
CIN
1
ns
18
ns
18
ns
18
t
(1)
INPUT CAPACITANCE
ns
4(typ.)
S(typ)
P8205
C820S
Test Conditions
Unit
18
pF
pF
MHz. Vee = OV
vBIAS = 2.0V. TA = 250 e
f = 1
ThIS parameter IS periodically sampled and IS not 100°'0 tested
TYPICAL CHARACTERISTICS
OUTPUT CURRENT VS.
OUTPUT "LOW" VOLTAGE
OUTPUT CURRENT VS.
OUTPUT "HIGH" VOLTAGE
DATA TRANSFER FUNCTION
50
80
10
;(
;(
.
!
.
.B
+
40
!
~ 60
~
0:
0:
20
0:
0:
"c.>
~I 40 I--+--+--t-~-It-
~
·30
20
-40
10
~
" 20 t-+--t--fJo¥+---+
"0
o
o
10
OUTPUT' lOW" VOL TAGE (VI
OUTPUT 'HIGH
2-53
VOLTAGE (VI
2
4
6
8
10
1214 16 18 20
INPUT VOLTAGE (V)
AFN.Q0204C
inter
8205
TYPICAL CHARACTERISTICS (Continued)
ADDRESS OR ENABLE TO OUTPUT
DELAY VS. LOAD CAPACITANCE
20
ADDRESS OR ENABLE TO OUTPUT
DELAY VS. AMBIENT TEMPERATURE
r----------
20 r - - - - - - - - - - - - - ,
t+_.t __
--------~~----------
'++
OL-_ _
o
~
_ _L __ _L __
50
100
150
__J
200
LOAD CAPACITANCE (PF)
AMBIENT TEMPEI1ATURE ("C)
SWITCHING CHARACTERISTICS
TEST LOAD
CONDITIONS OF TEST:
TEST LOAD:
390n
Input pulse amplitudes: 2.5V
Input rise and fall times: 5 nsec
between 1V and 2V
Measurements are made at 1.5V
All TransIstors 2N2369 or EQUivalent
CL
=
30 pF
WAVEFORMS
ADDRESS OR ENABLE
INPUT PULSE
\
----I
I ' - - - ,- - - - - - - -
-..It_+,t __ , " ' -
~--~-----------------~
OUTPUT
.
.
~ _______________ _
______________ J
2·54
AFN-00204C
8212
8-BIT INPUT/OUTPUT PORT
• Fully Parallel 8-Blt Data Register and Buffer
• Service Request Flip-Flop for
Interrupt Generation
• Low Input Load Current - .2SmA Max.
• Three State Outputs
• Outputs Sink 1SmA
• 3.6SV Output High Voltage for
Direct Interface to 8008, 80aoA, or
808SA CPU
• 'Asynchronous Register Clear
• ReplaCes Buffers, Latches and
Multlplexe,. In MicroComputer
$ystems
• Reduces System Package Count
• Available In EXPRESS
- Standard Temperature Range
- Ext~nded Temperature Range
,
The 8212 Input/output port consists of an 8-bit latch with 3-state output buffers along with control and device selection
logic. Also Included is a service request flip-flop for the generation and control of interrupts to the microprocessor.
The device Is multi mode In nature. It can be used to Implement latches, gated buffers or multiplexers. Thus, aU of the
principal peripheral and input/output functions of a microcomputer system can be implemented with this device.
SERVICE REOUEST FF
'\
liD DSZ
IL> MD ---f+-L..J
lIT> STB~--4-,-L~
[[> D IZ --------=<'""-"H
OS,
vcc
MD
INT
01,
01.
DO,
DOa
01,
01,
DO,
00,
016 .
Dl3
0°3
01.
0°6
D0.
0°5
ST8
CUi
os,
015
GND
II> D 14 ---------''""-"H
§>DIS ------~c-H
[9 DI 6 - - - - - - - : - - H
DI,-olo
DATA IN
00.·Il00
MD
DATA OUT
DEVICE SELECT
MODE
STa
STROBE
INT
CLR
INTERRUPT CACTIYE LOWI
CLEAR IACTIYE LOWI
DSi-D8z
Ill> D'e - - - - - - - - J - H
(E>CLR----- os,
@>OS2
The high-impedance state allows the designer to connect
the 8212 directly onto the microprocessor bi-directlonal
data bus.
---+H_'"
[I>
MO
[IT>
ST 8 ~-.......
--t._,/
OUTPUT
BUFFER
Control Logic
IT> 0', ---------+-+1
The 8212 has control inputs OS1, OS2, MO and STB.
These inputs are used to control device selection, data
latching, output buffer state and service request flip-flop.
DO,@>
[E> D '2 - - - - - - - - = - + 1
DS1, DS2 (Device Select)
These 2 inputs are used for device selection. When OS1 is
low and OS2 is high (OS1 • OS2) the device is selected. In
the selected state the output buffer is enabled and the
service request flip-flop (SR) is asynchronously set.
[E> D', - - - - - - - - - + . - + I
Ii§> D 's - - - - - - - - - - t - + l
MD (Mode)
This input is used to control the state of the output buffer
and to determine the source of the clock input (C) to the
data latch.
When MO is high (output mode) the output buffers are
'enabled and the source of clock (C) to the data latch is
from the device selection logic (OS1 • OS2).
When MO is low (input mode) the output buffer state is
determined by the device selection logic (DS1' OS2) and
the source of clock (C) to the data latch is the STB
(Strobe) input.
§> D'8-------~_ti
rsTBMO---iD5, D~TAOUT EauAiSl
!
0
~
i'
r
o
STB (Strobe)
This input is used as the clock (C) to the data latch for the
input mode MO = 0) and to synchronously reset the
service request flip-flop (SR).
0
~
0
~
.
3 STATE
~!~~TLEA'tCH
1
I
eLA
0
~
1
0
DATA LATCH
'1
0
,
DATA LATCH.
j
1
DATA IN
: 6 .~
L~ l,!
~
g~+: :~I"
---'
1
los, 082)
•
STB
4
0
~
0
0
; '- '
-INTERNAL SR F'LIP FLOP
eLA - RESETS DATA LATCH
SETSSR FLIP FLOP
(NO EFFECT ON OUTPUT BUFFER!
Note that the SR flip-flop is negative edge triggered.
2-56
AFN.()()731C
8212
ABSOLUTE MAXIMUM RATINGS·
"NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera.tion of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Temperature Under Bias Plastic ..••..• O·C to +70·C
Storage Temperature ••..•..•...... -65~C to +160·C
All Output or Supply Voltages •..••.•• -0.5 to +7 Volts
All Input Voltages .................. -1.0 to 5.5 Volts
Output Currents ............................. 100mA
D.C. CHARACTERISTICS
Symbol
(TA=O°C to +-75°C, Vcc= +5V ± 5%)
Limits
Parameter
Typ.
Min.
Unit
Max.
Test Conditions
IF
Input Load Current, ACK. OS2, CR,
011-01s Inputs
-.25
mA
IF
Input Load Current MO Input
-.75
mA
VF = .45V
IF
Input Load Current OS1 Input
-1.0
mA
VF - .45V
IA
Input Leakage Current, ACK, OS, CR,
011-01s Inputs
10
p.A
VA
'5,
Vce
IA
Input Leakage Current MO Input
30
p.A
VA
'5,
Vce
IA
Input Leakage Current OS1 Input
40
p.A
VA
'5,
Vee
Ve
Input Forward Voltage Clamp
-1
V
VIL
Input "Low" Voltage
.85
V
VIH
Input "High" Voitage
VOL
Output "Low" Voltage
VOH
Output "High" Voltage
3.65
Ise
Short Circuit Output Curr!!nt
-15
1101
Output Leakage Current High
Impedance State
lee
Power Supply Current
CAPACITANCE·
Symbol
.45
-75
9pF 12pF
5pF 9pF
COUT
001-00a Output Capacitance
8pF 12pF
10H = -lmA
mA
Vo - OV, Vee - 5V
20
p.A
Vo = .45V/5.25Vee
130
mA
Input Pulse Amplitude = 2.5V
Input Rise and Fall Times 5ns
Between lV and 2V Measurements made at 1.5V
with 15mA and 30pF Test Load
Typ. Max.
OS1 MO Input Capacitance
10L -15mA
Conditions 01 Test
Limits
OS2, CLR, STB, 01,-0Is
Input Capacitance
V
SWITCHING CHARACTERISTICS
(F = lMHz, VBIAS = 2.5V,
Vee = +5V, TA = 25°C)
CIN
V
4.0
90
CIN
Ie - -5mA
V
2.0
Telt
VF = .45V
NOTE:
"This parameter is sampled and not 100% tested.
1
A.C. TESTING LQAD CIRCUIT
Test
tPD. tWE, tR, ts, tc
tE, ENABLEI
-rVcc
R,
DEVICE
UNDER
TEST
CL·
R,
R2.
30pF
3000
6000
30pF
10KO
lKl)
tE, ENABLE I
. 30pF
3000
6000
tEo DISABLEI
5pF'
3000
6000
te. DISABLEI
5pF
10KO
lKO
,.
"Includes probe and JIg capacItance.
CL INCWDES JIG CAPACITANCE
~-57
AFN-<)0731C
inter
8212
A.C. CHARACTERISTICS
Symbol
(TA'" O"C to
+7o·c: vcc =
+5V ± 5%)"
Limit.
Parameter
Min.
Unit
Max.
Typ.
30
Te.t CQndltlon.
tpw
Pulse Width
tpo
Data to Output Delay
30
ns
ns
Note 1
tWE
Write Enable to Output Delay
40
ns
Note 1
tSET
Data Set Up Time
15
20
ns
ns
tH
Data Hold Time
tR
Reset to Output Delay
40
ns
Note 1
ts
Set to Output Delay
30
ns
Note 1
tE
Output Enable/Disable Time
45
ns
Note 1
tc
Clear to Output Delay
55
ns
Note 1
"Note: For extended Temperature EXPRESS use M8212 AC Electncals Parameters.
APPLICATIONS
Basic S~hematlc Symbols
Two examples of ways to draw the 8212 on system schematics-(l) the top being the detailed view showing pin numbers.
and (2) the bottom being the symbolic view showing the system input or output as a system bus (bus containing
8 parallel lines). The output to the data bus is symbolic in referencing 8 parallel lines.
OUTPUT DEVICE
INPUT DEVICE
---...,,,
~
01 STB DO
:
,.
8212
10
15
17
01
•
16
,.
16
(DETAllEDf
"
ST.
DO
8212
20
22
23
!NT
CLR
MD
4
6
10
15
17
,.
21
14
SYSTEM
OUTPUT
, (SYMBOLIC)
GND
DATA BUS
Figure 3. Basic Schematic Symbols
Gated B'uffer (3-State)
Vee - . . , . . . . - - - - - - - ,
The simplest use of the 8212 is that of a gated buffer. By
tying the mode signal low and the strobe input high. the
data latch is' acting as a strai,ght through gate, The output
buffers are then enabled from the device selection logic'
i5S1 and DS2.
STB
INPUT
DATA
(250 ,.AI
OUTPUT
DATA
("SmA)
(36SV MIN)
When the device selection logic is false. the outputs are 3state.
'
GATING
When the device selection logic is true. the input data from
the system is directly transferred to the output. The input
data load is 250 micro amps. The output data can sink 15
milli amps. The minimum high output is 3.65 volts.
CONTROL
168100821
{
- - -_ _ _ _--'
Figure 4. Gated Buffer
2-58
AFN'()()731C
8212
Bi-Directlonal Bus Driver
Interrupt Instruction Port
A pair of 8212's wired (back-to-back) can be used as a
symmetrical drive, bi-dlrectional bus driver. The devices
are controlled by the data bus input control which is
connected to OS1 on the first 8212 and to OS2 on the
second. One device Is active, and acting as a straight
through buffer the other is In 3-state mode. This is a very
useful circuit In small. system design.
The 8212 can be used to gate the interrupt instruction,
normally RESTART instructions, onto the data bus. The
device is enabled from the interrupt aCknowledge signal
from the microprocessor and from a port selection signal.
This signal is normally tied to ground. (OS1 could be used
to multiplex a variety of interrupt instruction ports onto a
common bus).
DATA
BUS
STB
STB
DATA
BUS
r-----'"
RESTART
8212
INSTRUCTION
. - - ' - - - - - , . DATA
(RST 0 -
BUS
DATA BUS
(BST)
CONTROL
10, L - A)
II" A -
AST 7)
PORT SELECTION
INTERRUPT ACKNOWLEDGE - _ - _ - - '
L)
STB
Figure 7. Interrupt Instruction Port
Output Port (With Hand-Shaking)
The 8212 can be used to transmit data from the data bus to
a system output. The output strobe could be a handshaking signal such as "reception of data" from the device
that the system is outputting to. It in turn, can interruptthe
system signifying the reception of data. The selection of
the port comes from the device selection logic.( i5S1 • OS2)
GND
Figure 5. Bidirectional Bus Driver
DATA
BUS
Interrupting Input Port
, . . - - - - OUTPUT STROBE
This use of an 8212 is that of a system input port that
accepts a strobe from the system input source, which in
turn clears the service request flip-flop and interrupts the
processor. The processor then goes through a service
routine, identifies the port, and causes the device
selection logic to go true - enabling the system input data
onto'the data bus,
STB
SYSTEM OUTPUT
SYSTEM RESET
DATA
SYSTEM
BUS
INTERRUPT
L_.c.:..___
}
PORT SELECTION
:~~;'~2~ONTAOL)
STB
Figure 8. Output Port
SYSTEM
INPUT
SYSTEM
RESET,
PORT
SELECTION
IDS'.DS2)
{
------'
+-___ T;>c~f~~RlI6~)CKT
OR
•
TO CPU
INTERRUPT INPUT
Figure 6. Interrupting Input Port
2-59
AFN·00731C
inter
8212
808A Status Latch
,1
Here the 8212 Is used as the status latch for an 8080A
microcomputer system. The input to the 8212 latch is
dlreotly from the 8080A.data bus. Timing,shows that when
the SYNC signal is true, which is connected to the DS2
input and the phase 1 signal is true, which is a TTL level
coming from the clock generator; then, the status data will
be latched into the 8212.
~
,2
SYNC
DATA
STATUS
~
_ _I-I-_
f---f-A.--1
10
9
0,
8
O2
7
03
DATA BUS
3
0,
4
d.
8080A
5
D.
6
07
SYNC
OBIN
¢1
19
r!L-
02
22
STATUS
LATCH
15
~
12Vn
~7
ovJ \..• ..L; ~
CLOCK GEN.
80 DRIVER
9
16
18
20
22
~TL)
-;i
0,
Do
~
fo-
tt"iT
8212
~
1L
CLR
OS2 MO
13 12
Note: The mode signal is tied high so that the output on the
latch is active and enabled all the time.
~
INTA
STACK
HLTA
OUT
M1
INP
MEMR
BASIC
CONTROL
BUS
OS,
"
OBIN
It is shown that the two areas of concern are the bidirectional data bus of the microprocessor and the control
bus.
2-60
AFN-00731C
inter
8212
TYPICAL CHARACTERISTICS
INPUT CURRENT VS. INPUT VOLTAGE
l00r------r------r------r----~
~~
Vee -lsov
-60
Vee· +I.OV
",I'
~ ~100
T. -O"C'
i
OUTPUT CURRENT VS. OUTPUT "LOW" VOLTAGE
.;'"
H~----_+------~------+-----~
VT. -2S"C
""vT. -7S"C
a:: -150
il
i!
-200
-250
-300-3
-2
-1
'2
"
'3
INPUT VOLTAGE (VI
OUTPUT "LOW" VOLTAGE (V)
OUTPUT CURRENT vs.
OUTPUT "HIGH" VOLTAGE
DATA TO OUTPUT DELAY
VS. LOAD CAPACITANCE
50
Vee
TA ..
40
!
>
~
...0
"'~50V
r-T
0
....
1
I
30
~
:>
...0
25~C
I
20
0(
It0
10
\-1""'",-
-
.......... 1-
~
I
so
r-r-
f-o ....
l-- ~
I
100
150
200
250
OUTPUT "HIGH" VOLTAGE (V)
LOAD CAPACITANCE (pF)
DATA TO OUTPUT DELAY
VB. TEMPERATURE
WRITE ENABLE TO OUTPUT DELAY
VS. TEMPERATURE
22
300
40
Vee
Vee =+SDV
20
!
I
):"...,."
.... ......
t--
+5 OV
I
>
~
,/',
•
=
36
1--;'
...0
30
0
0
2S
z~
20
~
...w
-.......
I
I
ST~<
OS,
w
w
......~!..
_---'
.. r--,,,.or
...."
f----
.....
~-
t+_
t __
OS;< ~
-
!:
a:
2
10
-25
~
25
50
1S
15
10
-25
100
TEMPERATURE lOCI
25
50
TEMPERATURE
2-61
1S
100
rei
AFN.()()731C
inter
8212'
WAVEFORMS
DATA
STB ••
,.5VX-- - - - - - -.- -Y,.5V
------'.
I;==tpw
·1' tH :..j'----OS,.
,.5Vl
\:.' 5._V_______
OS2
I.-- tWE-----I
-"\1,--------
'OUTPUT
OS,.
_ _ ....:... _ _ _ _ _ _ _ _
'._5V___·_______
. . . - / \...
'SV/
052
_____
~_tE-+j
OUTPUT
~
_______
\',.SV
r _______
X
.
\:::-to--:j---
~'"'==-=:------'r-
----------,-SV. ,. itpwiI, ~V
CLR
_______I,___tc_~·1 , ____ _
DO
______________
,5VX----------"'5V
DATA
-----..Jt;
STB ••
r
i?S, • 052
"0,"",
STB
JX'-'_5V______
_____
tSET ~
r
tH
-~'----
'5V\'--____________
~~~1;.;-----' -----:
_~'5V
---I ----------------
•
~ tpw
-~~---;'--,--.-'\-
2-.62
AFN·0073,C
.intel~
8216/8226
4·BIT PARALLEL BIDIRECTIONAL BUS DRIVER
• Data Bus Buffer Driver for 8080 CPU
• 3.65V Output High Voltage for Direct
Interface to 8080 CPU
• Low Input Load Current - 0.25 IT!A
Maximum
• 3·State ~utputs
• Reduces System Package Count
• High Output Drive Capability for
Driving System Bus
• Available in EXPRESS
- Standard Temperature Range
The 8216/8226 Is a 4·blt bidirectional bus driver/receiver. All inputs are low power TIL compatible. For driving MOS, the
DO outputs provide a high 3.65V Vo H, and for high capacitance terminated bus structures, the DB outputs provide a
high 50 mA 10l capability. A non·lnvertlng (8216) and an inverting (8226) are available to meet a wide variety of applica·
tlons for buffering In microcomputer systems.
'Nole: The specifications for Ihe 321613226 are ,,,nlical wilh thosa
f~r the 821618226.
8216
8226
cs
0',
O~
DB.
00.
DB,
DO,
01,
6iEN
os,
00,
O~
DB,
00,
0,>
De,
00,
DI, ,
DB,
DB,
00,
DO,
0',
DI,
DB,
00,
DB,
0',
01,
GNO
0.,
00,
D~
01,
.----<>
DB,
DB,
00,
00,
'----+_----<> CS
'-----+-~----<>cs
O'EN
Vee
00.
<>-_+-___...1
O'EN
o - _......_ _ _.-J
Figure 1. Block Diagrams
2-63
os,-oa,
I)ATAIUS
.'-DIRECTIONAL
0'0.0,>
DOo·003
DATA INPUT
OlEN
OAT A IN ENABLE
DIRECTION CONTROL
a
CHtPSELECT
DATA OUTPUT
Figure 2. Pin Configuration
8216/8226
FUNCTIONAL DESCRIPTION
Microprocessors like the 8080 are MOS devices and are
generally capable of driving a single TTL load. The same is
true for MOS memory devices. While this type of drive is
sufficient in small systems with few components, quite often
it is necessary to buffer the microprocessor and m(lmories
when adding components or expanding to a multi-board
system.
DB,
OO,o---I----+--,
DB,
DO,o---t--___~t--+~
The 8216/8226 is a four bit bi·directional bus driver specif·
ically designed to buffer microcomputer system components.
01,0---1--1.>-+.......,
Bidirectional Driver
00,0---+--< t--+-~
DB,
Each buffered line of the four bit driver consists of two
separate buffers that are tri·state in nature to achieve' direct
bus interface and bi·directional capability. On one side of
the driver the output of one buffer and the input of another
are tied together (08), this side is used to interface to the
system side components such as memories, I/O, etc., be·
cause its interface is direct TTL compatible and it has high
drive (50mA). Oli the other side of the driver the inputs
and outputs are separated 10 provide maximum flexibility.
Of course, they can be tied together so that the driver can
be used to buffer a true bi·directional bus such as the 8080
Data Bus, The DO outputs on this side of the driver have a
special high voltage output drive capability (3.65V) so that
direct interface to the 8080 and 8008 CPUs is achieved with
an adequate amount of noise immunity (350m V worst'case).
01,0---+--1 ...._-+-,
DB]
00] <>---I----Q-+---'
~---t-.----~cs
Figure 3a. 8216 LogiC; Diagram
01,
DB,
DO.
DI,
Control Gating OlEN, CS
DB,
The CS input is actually a device select, When it is "high"
the output drivers are all forced to their high·impedance
state. When it is at "zero" the device is selected (enabled)
and the direction of the data flow is determined by the
OlEN input.
The OlEN input controls the direction of data flow (see
Figure 3) for complete truth table. This direction control
is accomplished by forcing one of the pair of buffers into its
high impedance state and allowing the other to transmit its
data. A simple two gate circuit is used for this function.
The 8216/8226 is adevice that will reduce component count
in microcomputer systems and at ths same time enhance
noise immunity to assure reliable, high performance op·
eration.
DO,
01,
DB,
DO,
'OIJ
DB]
D0]
~---~~-------ocs
OlEN 0 - - -....- - - - - - - - '
OlEN
0
,
0
r-;-
cs
0
0
,
,
01
DB
DB
00
} HIGH IMPEDANCE
Figure 3b. 8226 Logic Diagram
2-64
AFN-00733C
821618226
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias ............ "
"NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
aOc to 70°C
Storage Temperature . , ....... , .. -65°C to +150°C
All Output and Supply Voltages. . . . . ..
-0.5V to +7V
All Input Voltages .. , ...... , , .... -1.0V to +5.5V
Output Currents ...... , . • . . . . . . . . . . .. 125 mA
D.q. CHARACTERISTICS
(TA
= o·e to + 70·e, Vee = +5V ±
5%)
Limits
Typ.
Max.
Unit
IF1
Inpllt Load Current OlEN, CS
-0.15
-.5
mA
VF ~0.45
IF2
Input Load Current All Other Inputs
-0.08
-.25
mA
VF =0.45
Symbol
Parameter
Min.
Conditions
IR1
Input Leakage Current OlEN, CS
80
IJ.A
VR =5.25V
IR2
Input Leakage Current 01 Inputs
40
itA
VR =5.25V
Ve
Input Forward Voltage Clamp
-1
V
Ie = -5mt\
Vil
Input "Low" Voltage
.95
V
20
100
itA
VIH
Input "High" Voltage
1101
Output Leakage Current
(3-Statel
2.0
Icc
Power Supply Current
VOL1
Output "Low" Voltage
VO l 2
Output "Low" Voltage
VOH1
Output "High" Voltage
3.65
VOH2
Output "High" Voltage
2.4
los
Output Short Circu it Current
-15
-30
-35
-75
.
V
DO
DB
8216
95
130
mA
8226
85
120
mA
0.3
.45
V
Vo = .45V/5.25Vee
DO Outputs IOl=15mA
DB Outputs 10l =25mA
8216
0.5
.6
V
DB Outputs Iol =55mA
8226
0.5
.6
V
DB Outputs 10l=50mA
4.0
V
DO Outputs 10H = -lmA
3.0
V
-65
-120
mA
mA
DB Outputs 10H = -1 OmA
DO Outputs Voi!!!OV,
DB Outputs VcC=5.0V
NOTE:
, Typical value. are for TA
= 25· C. Vec =5.0V.
2-65
AFN'()0733C
inter
821618226
CAPACITANCE'SI
(VBIAS = 2.5V, Vec = 5.0V, TA = 25°C, f = 1 MHz)
Parameter
Max.
Unit
Input Capacitance
4
8
pF
COUT!
Output Capacitance
6
10
pF
COUT2
Output Capacitance
13
18
pF
A.C. CHARACTERISTICS
Min .
Limits
Typ.!l]
C,N
.Symbol
(TA = O°Cto +70°C. Vee = +5V ± 5%)
Limits
Symbol
Min.
Parameter
Typ.!l]
Max.
Unit
CL =30pF, R,=300n
R2=600n
TpDI
Input to Output D~lay DO Outputs
15
25
ns
TpD2
I nput to Output Delay DB Outputs
8216
Te
To
Conditions
19
30
ns
CL =300pF, R , =90n
8226
16
25
ns
R2 = 180n
8216
42
65
ns
(Note 2)
8226
36
54
ns
(Note3)
16
35
ns
(Note4)
Output Enable Time
Output Disable Time
NOTE:
Input pulse amplitude of 2.5V.
Input rise and fall times of 5 ns between 1 and 2 volts.
Output loading is 5 mA and 10 pF.
Speed measurements are made at 1.5 volt levels.
NOTES:
1. TYPIcal values are for TA = 2So C, VCC = S.OV.
2. DO Outputs, CL' 30pF, Rl = 300/10 Kn, R2 = 180/1Kn; DB Outputs, CL = 3OOpF, R, = 90/10 Kn, R2 = 18011 Kr.
3. DO Outputs, CL = 30pF, R, = 300/10 Kn, R2 = 600/1K; DB Outputs, CL = 30OpF, Rl =90/10Kn, R2 = 180/1 Kn.
4. DO Outpu,s, CL = SpF, Rl = 300/10 Kn, R2 = 600/1 Kn; DB Outputs, CL = SpF, R, = 90/10 Kn, R2 = 180/1 Kn.
S. This parameter is portodtcally sampled and not 100% tested.
"
A.C. TESTING LOAD CIRCUIT
-,- Vee
R,
eli
DEVICE
UNDER
TEST
2-66
R,
-=E"
AFN·00733C
inter
8216/8226
WAVEFORM
INPUTS
OUTPUT
EN....LE
~'oj. Y
OUTPUTS
15V'X,.-----..F- ·
t
-------....
~H
~~L
5V
2-67
AFN'()()733C
8218/8219
BIPOLAR MICROCOMPUTER BUS
CONTROLLERS FOR MCS-SO®,AND MC8-85® FAMILIES
• 8218 for Use In MCS-80® Systems
• Reduces Component Count In
Multlmaster Bus Arbitration Logic
• 8219 for Use InMCS-85® Systems
• Single +5 Volt Power Supply
• Coordinates the Sharing of a Common
Bus Between Several CPU's
• 28 Pin Package
The 8218 and 8219 Microcomputer Bus Controllers consist of control logic which allows a bus master device such as a CPU
or DMA channel to interface with other masters on a common bus, sharing memory and I/O devices. The 8218 and 8219
consist of:
1. Bus Arbitration Logic which operates from the Bus Clock (SCU<) and resolves bus contention be~ween devices sharing
a common bus.
2. Timing Logic which when initiated by the bus arbitration logic generates timing signals for the memory and I/O
command lines to guarantee set-up and hold times ofthe address/data lines onto the bus. Thetiming logicals0signals
to the bus arbitration logic when the current data transfer is completed and the bus is no longer needed.
3. Output Drive Logic which contains the logic and output drivers for the memory and I/O command lines.
An external RC time constant is used with the timing logic to generate the guaranteed address set-up and hold times on the
bus. The 8219 can interface directly to the 8085A CPU and the 8218 interfaces to the 8080A CPU chip and the 8257 DMA
controller.
BCR1
{EI
RSTB
vee
BUS ARBITRATION
OVRO
lOGIC
RSTB
ADm
BeR1
OVRO
{EI
{BI
TOTHE~
BUS
BREQ
{el
OtYAOJ
BeLK
~TOTHE
XSTR
L-.y' BUS
MASTER
ANYR
ADEN
ROD
BiJSY
MROC
fi5Wc
xep
IORC
MWTC
xcv
GND
DLYADJ
§ill
ANVR
{AI
{AI
iOWA
(B) MWTR
{el IDRR
{DI MRiiFi
{BI
OUTPUT DRIVE lOGIC
(E)
{el
Bcfi2
§ill
101M
WR
AD
ASRQ
BCR2
{DI
ROD
N.C. = NO CONNECT
Figure 1. Block Diagram
Figure 2. Pin Configuration
2-68
AFN-00208C
intJ
8218/8219
Table 1. Pin Description
Signall Intertaced Directly
I
Symbol
BREQ
BUSY
BCLK
,
BPRN
to the Syltem BUI,
Type
Name end Function
0
Bu, Reque't: The Bus Request is used
with a central parallel priority resolution
circuit. It 'indicates that the device needs to
access the bus for one or more data transfers. It is synchronized with the Bus Clock.
I/O
I
I
Bus Clock: The neg alive edge of Bus Clock
is used 10 synchronize the bus conlention
resolution circuit asynchronously to the
CPU clock. It has 100ns min. period, 3S%6S% duty cycle. It may be slowed, single
stepped or stopped.
Bu, Priority In: The Bus Priority In indicates to a device that no device of a higher
priority is requesting the bus. It is synchronous with the Bus clock.
0
Bus Priority Out: The Bus Priority .out is
used with serial priority resolution circuits.
Priority may be transferred to the next lower
in priority as BPRN.
INIT
I
Initialize: The Initialize resets the 8218/
8219 to a known internal stdle.
.0
Memory Read Control: ThE! Memory Read
Control indicates that the Master is requesting a read operation from the addressed
location. It is asynchronous to the Bus
Clock.
.
Type
Name and Function
ADEN
0
Addres, end Data Enable: Address and
Data Enable indicates the Master has control of the bus. It is, often used to "mabie
Address and Data Buffers on the bus, It is
synchronous with Bus Clock.
ROD
0
Read Data: Read Data controls the direction of the bi-directional data bus drivers. It
is.asynch'ronous to the Bus Clock. Ahigh on
ROD indicates a read mode by the master.
OVRD
I
Override: Override inhibits automatic deselect between transfers caused by a higher
priority bus request. May be used for consecutive data transfers such as readmodify-write operations. It is asynchronous
.
to the Bus Clock.
XSTR
I
Transfer Start Requeat: 'Transfer Start Request indicates to the 8218/8219 that a new
data transfer cycle is requested to start. It 'is
raised for each new word transfer in a multiple data word transfer. It is asynchronous"
to the Bus Clock.
XCP
I
Transfer Complete: Transfer Complete indicates to the 8218/8219 that the data has
been received by the slave device in a write
cycle or transmitted by the slave and received by master ina read cycle. It is asynchronous to the Bus Clock.
XCV
0
Date Transfer: Indicates that a data transfer is in progress. It is asynchronous to the
Bus Clock.
I
Write, Read, 10/Memory: WRITE, READ,
10lMemory are the control request inputs
used by the 808S and are Internally decoded
by the 8219 to produc~request signals
MRDR, MWTR, 10RR, IOWR. They are asynchronous to the Bus Clock. (8219 only)
I
Asynchronous Bus Request: Can be used
for interrupt status from the 8OBS.l\cts like a
level sensitive asynchronous bus
request-no RSTB needed. It is asynchronOuSiOihe Bus Clock. (8219 only)
I
Memory Read Request, Memory Write
Reque~t, 1/0 Read Request, or 1/0 Write
Request: Indicate that address and data
have been placed on the bus and the appropriate request is being made to the addressed deVice. Only one of these inputs
should I:!e active at anyone time. They are
synchronous to the Bus Clock. (8218 only)
.0
Any Request: Any Request is the logical
OR of the active state of MRDR, MWTR,
i15RR, iOWA. It may be tied to XSTR when
the rising edge of ANYR is used to initiate a
transfer.
I
Delay Adjust: Delay Adjust is used for connection of an external capacitor and resis..
tor to ground to adjust the required set-up
and hold time of address to control signal.
Symbol
Bu, Bu,y: Bus Busy indicates to all master
devices on the bus thai the bus is in use. II
inhibits any olher device from gelling Ihe
bus. It is synchronized wilh Bus Clock.
BPRO
MRDC
Signal, Generated or Received by the Bus Master
(Continued)
MWTC
.0
Memory Write Control: The Memory Write
Control indicates that data and an address
have been placed on the bus by the Master
and the data is to be deposited at that location. It is asvnchronous to the Bus Clock.
WR,RD,
101M
,iORc
0
I/O Read Control: The 1/0 Read Control indicates that the Master is requesting a read
operation from the I/O device addressed. It
is asynchronous to the Bus Clock.
ASRQ
10WC
0
1/0 Write Control: The 1/0 Write Control indicates that Data and an I/O device address
has been placed on the bus by the Master
and the data is to be deposited to the 1/0
device. It is asynchronous to'the Bus Clock.
MRDR,
MWTR,
10RR,
IOWR
"
.
I
Signals Generated or Received by the Bus Master
BCR11
BCR2
RSTB
I
I
Bus Control Request: Bus Control Request 1 or Bus Control Request 2 indicate to
the 8218/8219 that the Master device is making a request to control the bus. BCR2 IS
active low in the 8218 (BCR2). BCR2 is active high in the 8219.
ANYR
Request Strobe: Request Strobe latches
the status of BCR1 and BCF\2 into the
821818219. The strobe is active low in the
8218 and negalive edge triggered in the
8219.
DLYADJ
2-69
AFN-00208C
8218/8219
FUNCTIONAL DESCRIPTION
BPRO is used 10 allow lower priority devices to gain the
bus 'when a serial priority resolving structure is used.
B/5J!iO would go to msmiI of the next lower priority Master.
The 8218/8219 is a bipolar Bus Control Chip which
reduces component count In the interface between a
master device and the system Bus. (Master device: 8080,
8085, 8257 (DMAU
When priority is granted to the Master (a low on BPRN and
a high on ~) the Master outputs a MmV signal on the
next falling edge of BCLR. The. BUSY signal locks the
master onto the bus and prohibits the enable of any other
masters onto the bus.
The 8218 and 8219 seNe three major functions:
1. Resolve bus contention.
2. Guarantee set~up and hold time of address/data lines
to . I/O and Memory read/wrIte control signals
(adjustable by external capacitor).
3: Provide sufficient drive on all bus command lines.
At the Same time BUSY goes active, Address and Data
Enable iADENi goes active signifying that the Master has
control of the bus. ADEN is often used to. enable the bus
drivers.
The Bus will be released only if the master loses priority; is
not in the middle of a transfer, and Override is not active
or, if the Master stops req)Jesting the bus, is not in the
middle of a data transfer, and Override is not active. ADEN
then goes inactive.
BUI Arbitration Logic
Bus Arbitration Logic activity begins when the Master
makes a request for use of the bus on BCR1 or 'EiCR2. The
request is strobed in by RSTB. FQllowing the next two
falling edges of the bus clock (BCLK) the 8218/8219
outputs a bus request (BREQ) and forces Bus Priority Out
inactive (BPRO)' See Figures 1a and 1b.
BRECi is used for requesting the bus when priority is
decided by a parallel priprity resolver circuit.
OVRIDf
BCRl
II
Iic1l2
-
\-
:1
-
Provision has been made in the 8218 to allow bussynchronous requests. This mode is activated when
BCR1, BCR2 and RS'i'B are all low. This action
·asynchronously sets the synchronization flip flop (FF2) in
Figure 3a.
=u-
~
SET
......
V"
Q
ASYNCH.
REQUEST
SET
D
Q
SYNCH.
PRIOR'ITY
REQUEST
AND
REQUEST
~QGIC
FFl
r----<=
'I
SPRN
FF2
q
CLK
' CLR
CLR
1'""'
----
BUSY
Figure 3a. 8218 Bus Arbitration Logic
2-70
AFN'()()208C
inter
·8218/8219
ADEN
OVRIDE
ASRO
1
iiiiSY
SET
BeR'
BCR2
I
J
ASYNCH.
a
0
REQUEST
a
0
SYNCH
PRIORITY
REQUEST
AND
REQUEST
BRea
BPRN
LOGIC
FF2
FF.
BPRO
iffi'ii
,---<
eLK
eLK
CLR·
eLR
I
I
. iiClK
I
INIT
Figure 3b. 8219 Bus Arbitration Logic
Timing Logic
Timing Logic activity begins with the rising edge of XSTR
(Transfer Start Request) or with ADEN going active,
whichever occurs second. This action causes XCV
(Transfer Cycle) to go active. 50-200ns later (depending on
resistance and capacitance at DLYADJ) the appropriate
Control Outputs will go active if the control input is active.
MRDC
MRDR
IOAR
OUTPUT
CONTROL
lOGIC
MWTR
lowe
IOWR
XSTR can be raised after the command goes active in the
current transfer cycle so that a new transfer can be
initiated 'immediately after the current transfer is
complete.
IO~C
MWtC
ANY A
A negative going edge on XCP (Transfer Complete) will
cause the Control Outputs (MRDC, etc.) to go inactive.
50-200ns later (depending on capacitance at DL YADJ)
XCV will go inactive indicating the .transfer cycle is
completed,
CONTROL
OUTPUT
INACTIVE
Additionallbgic within the 8218/8219 guarantees that if a
transfer cycle is started (XCY is active), but the bus is not
requested (BREQ is inactive) ana there is no command
request input (ANYR is output low), then thfl transfer cycle
will be cleared. This allows the bus to be released in
applications where advanced bus req'uests are generated
but the processor enters a HALT mode.
ROD
Figure 4a. 8218 Control Logic
IO/M-~---------I
Control Logic
DECODING
RD------~-----I
The control outputs are generated in the 8219 by decoding
the 8085 system control outputs (I.e., RD, WR, 101M) or in
the 8218 by directly buffering the control inputs 1"0 the
control outputs for use in an 8080 or DMA system (see
Figures 4a and 4b>' The control outputs may be held high
. ANYR goes high (active) if
any control requests (IOWR, etc.) are active. ROD controls
the direction of the Masters Bi-directional Data Bus
Drivers. The Bus Driver will always be in fhe Write mode
(ROD = Low) except from the start of a Read Control
Request to 25 to 70ns after XCP is activated.
INACTIVE
ROO_----/
Figure 4b. 8219 Control Logic
2-71
AFN'()()20BC
inter
8218/8219
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ...•.. ODC to 70DC
Storage Temperature ...........•.• -65 DC to +150·C
Supply Voltage (Vee) . .. . . • .• . . . • . . . . .. -0.5V to +7V
Input Voltage.................. -1.0V to Vee + 0.25V
Output Current .............................. 100mA
D.C. CHARACTERISTICS
(TA
'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure ·to absolute maximum
rating conditions for extended periods may affect device
reliability.
= ODC to 70 C; Vee = 5V ±
D
5%)
LImits
Symbol
Parameter
Min.
Ve
Input Clamp Voltage
IF
Input Load Current
MRDR/INTA/MWTR/WR
iOA'RiRD, IOWR/IOiM
Other
IA
Typ.
Input Leakage Current
VTH
Input Threshold Voltage
Icc
Power Supply Current
VOL
Output Low Voltage
0.8
200
MiffiC, MWi'C,
IORC, IOWC
BREQ, BUSY
XCY,RDD,ADEN
BPRO,ANYR
VOH
Max.
Unit
-1.0
V
-0.5
. -0.5
mA
mA
100
!J.A
= O.OV, Ie = -5 mA
Vee = 5.25V
VF = 0.45V
Vee = 5.25
VA = 5.25 .
2.0
V
Vee
240
mA
Vee
= 5V
= 5.25V
Vee = 4.75
0.45
0.45
0.45
0.45
V
V
V
V
10L = 32mA
10L = 20m A
10L = 16mA
.I0L = 3.2mA
Output High Voltage
MRiSC,
Test Conditions
Vee
= 4.75V
= -2m A
10H = -4OO!J.A
Vee = 5.25V, Vo ;" OV
Vee = 5.25V, Vo = .0.45V
Vee = 5.25V, Vo = 5.25V
Vee
MWTC, IORC, IOWC
All Other Outputs
2.4
10H
2.4
los
Short Circuit Output Current
10 (OFF)
Tri-State Output Current
-10
-90
mA
-100
!J.A
+100
!J.A
CIN
Input Capacitance Except Busy
10
20
pF
CIO
Input Capacitance Busy
25
35
pF
8218/8219 XSTR TO OUTPUT DELAY (Tsew
•••
'7S
,SO
..
,
DELAY
'00
7S
_A
. . . .F
S.
'00"
..
loopF
...
-
__~~
~
'S~~~~~~~~~~~-=~~
~
~
~
~
~
~
OHMS
One Shot Delay Versus Delay Adjust Capacitance And Resistance
AFN-00208C
8218/8219
A.C. CHARACTERISTICS
Symbol
tacy
(TA = DoC to 70°C; Vcc = 5V ± 5%)
Parameter
Min.
Bus Clock Cycle Time
100
35
25
15
tpw
Bus Clock Pulse Width
tROS
RSTB to
tcss
BCR1 and BCR2 to RSTB
Set-Up Time
tCSH
BCR1 and BCR2 to RSTB
Hold Time
tROD
BCLK to BREQ Delay
tPRNS
BPRN to BCLK Set-Up Time
BlXR Set-Up Time
taNo
BRPN to BPRO Delay
teYD
BCLK to BUSY Delay
tCAD
MRDR, MWTR, IORR, IOWR'
to ANYR Delay
Lhnlt.
Typ.
Max.
Unit
0.65 tacy
ns
ns
ns
15
ns
35
ns
23
ns
30
55
30
tsxD
XSTR to XCV Delay
tSCD
XSTR to MRDC, MWTC, IORC,
IOWC Delay
50
txsw
XSTR Pulse Width
30
tXCD
XCP to MRDC, MWTC, IORC,
IOWC Delay
txcw
XCP Pulse Width
tCCD
XCP to XCV Delay
tCMD
MRDR, MWTR, IORR, IOWR
to MR5C, MWTC, IORC, IOWC
tCRD
MRDR, MWTR, IORR, IOWR
to ROD Delay
tRW
RSTB Min. Neg. Pulse Width
tCPD
BCLK to BPRO Delay
tXRD
XCP to ROD Delay
Test Conditions
35% to 65% Duty Cycle
ns
ns
ns
ns
40
200
ns
50
ns
ns
\Adjustable by External RIC
ns
35
50
ns
200
35
ns
25
ns
40
70
ns
Adjustable by External RIC
ns
30
ns
25
ns
A.C. TESTING LOAD CIRCUIT
A.C. TESTING INPUT, OUTP.UT WAVEFORM
INPUT/OUTPUT
...,... Vl
RL
DEVICE
UNDER
TEST
-
I
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC l' AND 0 45V FOR
A LOGIC 0 TIMING MEASUREMENTS ARE MADE AT 1 5V FOR BOTH A
LOGIC 1 AND 0 .
VL -
CL
24V
~:: ~~F
ct: INCLUD~S JIG CAPACITANCE
2-73
AFN-Q0208C
intel'
8218/8219
WAVEFORMS
SYNCHRONOUS BUS TIMING (System Bus Previously Not In Use)
ilSfii-----'
leVD
~~
-
181'0--
------------------___~--------'l_+----~--
.
-"[ --f---7-1
"'0 _____________________________________________
:N] "N°d....
to"
CONTROL CYCLE (System Bus Previously Not In Use)
M'R5"R
MWTR
lORA
IOWA
~
I'----
!--tcAD_
I-tcAD-
~
ANYR
j
/
j+--'CRD_
ROD
.
-.i
- ~~1::-
XSTR _ _
I
xcv
_~ ____ ~
J
XCP --""
MWTC
lORe
lowe
H~1-
~
I
1\..,.-j+---tcCD-
)
..... ·XCD-
-'SXDMRi5C
t)(RD
'l
\
tSCD_
I-tcMO-
CPU With 8219 Using Local Memory
2-77
AFN'()()208C
"__ I"
I'.-e-.
8218/8219
TO/FROM LOWEST
PRIORITY BUS MASTER
TO/FROM HIGHEST
PRIORITY BUS MASTER
8218
8219
8218
BUS CLOCK
"DAISY CHAIN" CON FIGURATION
U
~J
1
REQUEST
ADEN
8219
iiij§V
t
BUS CLOCK
BREQ
Bl'RN
~l
f
ADEN
REQUEST
REQUEST
821B
iiC[j(
iiij§V
t
t
I
BREa
iii'Riii
ADEN
8219
iiC[j(
-f
j
BUSY
t
BREQ
'iPRN
iiC[j(
1
!
1
PRIORITY
RESOLVING
LOGIC
I
I
PARALLEL REQUEST CONFIGURATION
lWo Methods of Connecting Multiple 8218/8219's To Resolve Bus Contention Among Multiple Masters
2-.78
AFN-00208C
8224
CLOCK GENERATOR AND DRIVER
FOR 8080A CPU
Single Chip Clock Generator/Driver for
• 8080A
CPU
• Power-Up Reset for CPU
• Ready Synchronizing Flip-Flop
• Advanced Status Strobe
Oscillator
• Timing
Outp~t
for'External System
Crystal ControUed for Stable System
• Operation
• Reduces System Package Count
in EXPRESS
• '-Available
Standard Temperature Range
The Intel 8224 is a single chip clock generator/driver for the 8080A CPU, It is controlled by a crystal, selected by the
.
designer to meet a variety of system speed requirements,
Also included are circuits to provide power-up reset, advance status strobe, and synchronizlltion of ready,
The 8224 provides the designer with a significant reduction of packages used to generate clocks and timing for 8080A
RESET
§>
XIAll
asc
1!9
XTAl2
@>
TANK
.,
.,
@>
Vee
RESIN
XTAL 1
RDY1N
XTAl2
READY
IT]>
TANK
¢2 (TTL)
.,
STSTB
~,
a80
SYNC
Ii9
.,ITTLIIE>
Voo
GND
IE>
SYNC
[D
RESIN
[D
RDYIN
sms[D
AESET
IT>
AEADY~
RESIN
RESET INPUT
RESET
RESET OUTPUT
RDYIN
READY
SYNC
READY INPUT
XTAL 2
READY OUTPUT
TANK
STSTS
.,
~
Figure 1. Block Diagram
SYNC INPUT
STATUSSTB
(ACTIVE LOW)
~ 8080
CLOCKS
~-
!
CONNECTIONS
FOR CRYSTAL
USED WITH OVERTONE XTAL
asc
OSCILLATOR OUTPUT
¢2 (TTL)
¢2 eLK (TTL lEVEL)
Vee
+5V
+12V
OV
Voo
GND
Figure 2. Pin Configuration
2-79
inter
8224
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias .......... ' ..... O°C to 70°C
Storage Temperature .............. _65°C to 150°C.
Supply Voltage, Vee ................ -0.5V to +7V
Supply Voltage, Voo .............. -0.5V to +13.5V
Input Voltage ..................... -1.5V to +7V
Output Current ........•................ 100mA
D.C. CHARACTERISTICS
Symbol
,
(TA
"NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
= o·c to 70·C. Vee = +5.0V ±5%. Voo = +12V ±5%)
Parameter
Limits
Typ.
Max.
Units
IF
Input Current Loading
-.25
mA
VF = .45V
IR
Input Leakage Current
10
p.A
VR = 5.25V
Ve
Input Forward Clamp Voltage
1.0
V
le= -5mA
Vil
Input "Low" Voltage
.8
V
Vee = 5.0V
VIH
Input "High" Voltage
2.6
2.0
V
Reset Input
All Other Inputs
V1WVIl
R.ES I N I nput Hysteresis
.25
VOL
Output "Low" Voltage
VOH
Min.
Test Conditions
V
Vee = 5.0V
.45
V
VPl,tP2), Ready, Reset,STSTB
.45
V
IOl =2.5mA,
All Other Outputs
IOl = 15mA
V
V
V
IOH = -1001lA
IOH = -100p.A
IOH = -lmA
-60
mA
Vo =OV
Vee =!;i.OV
Output "High" Voltage
<1>1
, <1>2
READY, RESET
All Other Outputs
9.4
3.6
2.4
Ise[IJ
Output Short Circuit Current
(All Low Voltage Outputs Only)
Icc
Power Supply Current
115
mA
100
Power Supply Current
12
mA
-10
Note: 1. Caution, 4>1 and ¢2 output drivers do not have short circuit protection
Crystal Requirements
Tolerance: 0.005% at 0·C-70·C
Resonance: Series (Fundamental)"
Load Capacitance: 20-35 pF
Equivalent Resistance: 75-20 ohms
Power Dissipation (Min): 4 mW
·Wlth tank circuit use 3rd overtone mode.
2-80
AFN·OO732C
inter
8224
A.C. CHARACTERISTICS
Symbol
(Vee
= +5.0V
Parameter
±5%, Voo
±5%, TA
= O°C to 70°C)
limits
Typ.
Min.
tq,1
2 Delay
,
= +12.0V
Max.
Test
Conditions
9
9
ns
CL = 20pF to SOpF
9
2tcy
2tcy + 20ns
9
9
2
tPl
tfi2
tOl
Delay tPl to tP2
t./>1
Min.
Limits
Typ.
= O"C to 70"C, VOO = +5V ±5%;
,
Max.
Units
89
Pulse Width
236
ns
0
ns
t02
Delay tP2 to tPl
95
t03
Delay tPl to tP2 Leading Edges
109
tr
tf
toss
Test Conditions·
ns
Pulse Width
ns
129
ns
Output Rise Time
20
ns
Output Fall Time
20
ns
326
ns
tP2 to STSTB Delay
tP2 to tP2 (TTL) Delay
296
t04>2
tpw
Status Strobe Pulse Width
40
ns
tORS
RDYIN Setup Time to STSTB
-167
ns
tORH
RDYIN Hold Time after STSTB
217
ns
tOR
READY or RESET
to tP2 Delay
192
ns
fMAX
Oscillator Frequency
-5
+15
I-
tPl
&
tP2
Loaded to
CL = 20 to 50pF
ns
18.432
A.C. TESTING INPUT, OUTPUT WAVEFORM
tcy=488.28ns
Ready & Reset Loaded
to 2mA/l0pF
All measurements
referenced to 1.5V
unless sPl'Cified .
otherwise.
MHz
A.C. TESTING LOAD CIRCUIT
INPUT/OUTPUT
-,- Vee
U=>\: : >
8.45
<:::VA-
R,
DEVICE
UNDER
TEST
TESTPQINTS
-_ _ _ _ _ _ _ _
-
A.C.TESTlNO:INPUTSAREDRlVENAT2.4VFORA LOGIC"I"ANOO.45VFOR
A LOGIC "0." TIMING MEASUREMENTS ARE MADE AT2.OV FORA LOGIC "1"
AND 0.8V FOR A LOGIC "0" (UNLESS OTHERWISE NOTED).
.,
CL INC WOES JIG CAPACITANCE
2-82
AFN·OO732C
inter
8224
WAVEFORMS
\
SYNC
(FROM 8D8OA)
I
I--·--------·DII'--------i-~
i - - - - - - - 10 A H - - - - - - i
READVOUT__~__________________-J~
RESET OUT
VOLTAGE MEASUREMENT POINTS: 4>,.4>2 Logic "0" = ,.OV. logic ",". a.ov. Another signals m...ured at '.5V.
-,'
2-83 . ,
AFN·OO732C
8228/8238
SYSTEM CONTROLLER AND BUS DRIVER
FOR 8080A CPU
• Single Chip System Control for
MCS-801R> Systems
• User Selected Single Level Interrupt
Vector (RST 7)
• 28·Pln Dual In· Line Package
• Bullt·ln Bidirectional Bus Driver for
Data Bus Isolation
• Reduces System Package Count
• 8238 Had Advanced IOW/MEMW for
Large System Timing Control
• Allows the Use of Multiple Byte .
Instructions (e.g. CALL) for Interrupt
Acknowledge
• Available In EXPRESS
- Standard Temperature Range
The Intel· 8228 Is a single chip system controller and bus driver for MCS·80. It generates all signals required to
directly Interface MCS-80 family RAM, ROM, and I/O components.
A bidirectional bus driver is Included to provide high system TIL fan·out. It also provides isolation of the 8080 data bus
from memory and I/O. This allows for the optimization of control Signals, enabling the systems designer to use slower
memory and I/O. The Isolation of the bus driver also provides for enhanced system noise immunity.
A user selected single level Interrupt vector (RST 7) is provided to simplify real time, interrupt driven, small system
requirements. The 8228 also generates the correct control signals to allow the use of multiple byte instructions (e.g.,
CALL) in response to an Interrupt acknowledge by the 8080A. This feature permits large, interrupt driven systems to
have an unlimited number of Interrupt levels.
The 8228 Is designed to support a wide variety of system bus structures and also reduce system package count for
cost effective, reliable design of the MeS·SO systems.
Note: The speclflcallons for tho 322813238 are Identical with thos,. lor the 822818238
r-
0,_
CPU
DATA
BUS
°2°3D._
0,0,0,_
-~l
:=:
STSTS
Vco
HLOA
IIOW
-OB,
- 0 82
g:~
SYSTEM OAT A BUS
WR
-DO,
_
08.
M£Mw
iiOR
DSIN
-oB,
084
MEMR
INTA
04
l§..
=
LATCH
OB7
tmn
07
!mfW
06
OB3
i70R
03
I!OW
0.2
sfSi'i
086
OS
D.,
02
_liUmii
OBIN
BUSEN
01
WA
0.,
HlDA
If- - - - - - - - - - - - - -
VOLTAGE MEASUREMENT POINTS: 00-07 (when outputs) Logic "0" = O.BV, Logic "1" = 3.0V. All other Signals measured
at 1.5V.
"ADVANCED IOW/MEMW FOR 8238 ONLY.
2-87
AFN-00213C
8237A/8237A-4/8237A-5
HIGH PERFORMANCE
PROGRAMMABLE DMA CONT,ROLLER,
• High performance: Transfers up to 1.6M
Bytes/Second with 5 MHz 8237A·5
• Directly Expandable to any Number of
Channels
• End of Process Input for Terminating
Transfers
• Software DMA Requests
• Enable/Disable Control of Individual
DMA Requests
• Four Independent DM~ Channels
• Independent Autoinitialization of all
Channels
• Memory·to·Memory Trensfers
• Independent Polarity Control for DREQ
and DACK ~Ignals
• Available In EXPRESS
- Standard Temperature Range
• Memory Block Initialization .
• Address Increment or Decrement
The 8237A Multlmode Direct Memory Access (DMA) Controller Is a peripheral Interface circuit for microprocessor systems. It Is designed to Improve system performance by allowing external devices to directly transfer Information from
the system memory. Memory-to-memory transfer capability Is also provided. The 8237A offers a wide variety of programmable control features to enhance data throughput and system optimization and to allow dynamic reconflgura.
tion under program control.
The 8237A Is designed to be used In conjunction with an external 8-blt address register such as the 8282. It contains
four independent channels and may be expanded to any number of channels by cascading additional controller chips.
The three basic transfer modes allow programmability of the types of DMA service by the user. Each channel can be
Individually programmed to Autoinitialize to Its Qrlginal condition following an End of Process (EOP).
.
Each channel has a full 64K 'address and word count capability.
The 8237A-4 and 8237A-5 are 4 MHz and 5 MHz selected versions of the standard 3 MHz 8237A respectively.
110 BUFFEfI
""
'"IT
.
;ow
REAOY
iiEiiIi
CLOCK
IifIIW
, TIMING
.....
....
INOTE11)
ROADY
.ND
CONTROL
'IN
•
•
•
3
HLOA
iIII!W
AEN
COMMAND
RIll
...
Vcc(+6V)
HR.
CDNTRDL
lOW
ell
eLK
DR...•
0 ....
""0
...KDDACKt
.BDO'.
RISET
.
.
....'"
DAEQ3
DR'"
DREQ1
"
____--r
.1,
Figure 2.
Figure 1. Block Diagram
2-88
Pin Configuration
inter
8237A/8237~4/8237~5
Table 1. Pin Description
Symbol
Type
Vee
Vss
ClK
Type
Ground: Ground.
I
Clock Input: Clock Input controls
the Internal operiltlons of the
8237A and Its rate of data trans·
fers. The Input. may be driven at up
to 3 MHz for the standard 8237A
and up to 5 MHz for the 8237A·5.
I
Chip Salect: Chip Select Is an ac·
tlve low Input used to select the
8237A as an I/O device during the
Idle cycle. This allows CPU com·
municatlon on the data bus.
RESET
I
Reaet: Reset is an active high In·
put which clears the Command,
StatuB, Request and Temporary
registers. It also clears the
flrstllast f1iplflop and sets the
Mask register. Following a Reset
the device is in the Idle cycle.
I
Ready: Ready Is an Input used to
extend the memory read and write
pulses from the 8237A to accom·
modate slow memories or I/O per·
Ipheral devices. Ready must not
make transitions during its speci·
fied setuplhold time.
HLDA
I
Hold Acknowledge: The active
high Hold Acknowledge from the
CPU Indicates thaI it has relin·
quished control of the system
busses.
DREQO-DREQ3
I
DMA Request: The DMA Request
lines are Individual asynchronous
channel request Inputs used by pe·
ripheral circuits to obtain DMA
service. In fixed Priority, DREQO
has the highest priority and
DREQ3 has the lowest priority. A
request is generated by activating
the DREQ line of a channel. DACK
will acknowledge the recognition
of DREQ signal. Polarity of DREQ
Is programmable. Reset intlalizes
these 1.lnes to active high. DREQ
must be maintained until the corresponding DACK goes active.
I/O
Data Bus: The Data Bus lines are
bidirectional three·state signals
connected to the system data bus.
The outputs are enabled In the Pro·
gram condition during the 1/0 Read
to output the contents of an Ad·
dress register, a Status register,
the Temporary register or a Word
Count register to the CPU. The out·
puts are disabled and the inputs
are read during an I/O Write cycle
when the. CPU Is programming the
8237A control registers. During
DMA cycles the mos! significant 8
bits of the address are output onto
the data' bus to be strobea Into an
external latch by ADSTB. In memo
DBQ-DB7
SYll1bol
Power: + 5 volt supply.
CS
READY
~------~---r----------------~
Name and Function
I
2-89
lOR
I/O
lOW
I/O
EOP
I/O
AO-A3
1/0
Name and Function
ory·to·memory operations, data
from the memory comes Into the
8237A on the data bus during the
read-from-memory transfer. In the
wrlte-to-memory transfer, the data
bus outputs place the data Into the
new memory locallon.
I/O Read: I/O Read Is a bidirectional active low three-state line. In
the Idle cycle, It Is an Input control
signal used by the CPU to read the
control registers. In the Active cycle, It Is an output control signal
used by the 8237A to access data
from a peripheral during a DMA
Write transfer.
1/0 Write: I/O Write Is a bidirectional acllve low three-state line. In
the Idle cycle, It Is an Input control
signal used by the CPU to load Information Into the 8237A.ln the Aclive cycle, It Is an output control
signal used by the 8237A to load
data to the peripheral during a
DMA Read transfer.
•
End of. Proce..: End of Process III
an active low bidirectional signal.
Information concerning the com·
pletlon of DMA services Is available at the bidirectional EOP pin.
The 8237 A allows an external signal to terminate an active DMA
service. This Is accomplished· by
pulling the EOP Input low with an
external EOP signal. The 8237A also generates a pulse when the ter·
mlnal count (TC) for any'channells
reached. This generates an EciP
!!anal which Is output through the
EOP Line. The recepllon of EOP,
either Internal or external, will
cause the 8237A to terminate the
service, reset the request, and, If
Autoinitialize Is enabled, to write
the base r\lgisters to the current
registers of that channel. The mask
bit and TC bit In the status word
will be set for the currenlly active
channel by EOP unless the channel
Is programmed for Autoinitialize. In
that case, the mask bit remains unchanged. During memory-to'memory
transfers, EOP will be output wlJen
the TC for channel 1 occurs. EOP
should be tied high with a pull·up
resistor If It Is not used to prevent
erroneous end of process inputs.
Address: The four least significant
address lines are bidirectional
three·stale signals. In the Idle cy·
cle they are inputs and are used by
the CPU to address the register
to be loaded or read. In the Active
cycle they are outputs and provide
the lower 4 bits of the output
. address.
AFN·OO7890
inter
8237A/8237Ar-4/8237Ar-5 .
Table 1. Pin Description (Continued)
lYpe
Symbol
Name and Function
Symbol
A4-A7.
0
Address: The four most significant
address lines are three-state outputs and provide 4 bits of address.
These lines are enabled only during
the OMA service.
HRO
0
Hold Request: This Is the Hold Re·
quest to the CPU and Is used to reo
quest control of the system bus. If
the corresponding mask bit Is
clear, the presence of any valid
OREO causes 8237A to issue the
HRO. After HRO goes active at
least one clock cycle (TCY) must
occur before H LOA goes active.
DACKD-OACK3
0
DMA Acknowledge: OMA Acknowledge is used to notify the in·
dividual peripherals when one has
been granted a OMA cycle. The
sense of these lines is programmable. Reset initializes them to active low.
Type
AEN
0
Addre•• Enable: ·Address Enable
enables the 8-bit latch containing
~the upper 8 address bits onto the
system address bus. AEN can also
be used to disable other system bus
drivers 'during OMA transfers. AEN
is active HIGH.
AOSTB
0
Addre•• Strobe: The active high,
Address Strobe is used to strobe the
upper address byte into an "xternal
latch.
~
0
Memory Read: The Memory Read
signal is an active low three-state
output used to access data from the
selected memory location' during a
OMA Read or a memory-to-memory
transfer.
MEMW
0
Memory Write: The Memory Write
is an active low three-state output
used to write data to the selected
memory 'Iocation during a OMA
Write or a memory-to-memory
transfer.
FUNCTIONAL DESCRIPTION
The 8237A block diagram Includes the major logic
blocks and all of the internal registers. The data inter·
connection paths are also shown. Not shown are the
various control signals between the blocks. The 823711.
contain~ 344 bits of Internal memory In the form of
registers. Figure 3 lists these registers by name and
shows the size of each. A detailed description of the
registers and their functions can be found under
Register Description.
Name
Size
Number
Baae Address Registers
Base Word Count Registers
Current Address Registers
Current Word Count Registers
Temporary Address Register
Temporary Word Count Register
Status Raglsier
Command Register
Temporery Register
Mode Raglsters
. Mask Register
Request Register
16 bits
16 bits
16 bits
16bits
16 bits
16 bits
8blts
8 bits
8blts
6 bits
4blts
4 bits
4
4
4
Name and Function
be the 2 TTL clock from an 8224 or ClK from an
8085AH or 8284A. For 8085AH-2 systems above 3.9 MHz,
the 8085 ClK(OUn does not satisfy 8237A-5 clock lOW
and HIGH time requirements. In this case, an external
clock should be used to drive the 8237 A·5.
DMA Operation
The 8237A is deSigned to operate in two major cycles.
These are called Idle and Active cycles. Each device cy·
cle is made up of a number· of states. The 8237 A can
assume seven separate states,each composed of one
full clock period. State I (SI) is the inactive state. It is
el\tered when the 8237A has no valid DMA requests
pending. While in SI, the DMA controller is inactive but
may be in the Program Condition, being programmed by
the processor. State SO (SO) is the first state of a DMA
service. The 8237A has requested a hold but the pro·
cessor has not yet returned an acknowledge. The 8237A
may still be programmed until it receives HlDA from the
CPU. An acknowledge frdm the CPU will signal that
DMA transfers may begin. S1, S2, S3 and S4 are the .
working states of the DMA service. If more time is
needed to complete a transfer than is available with nor·
mal tilning, wait states (SW) can be inserted between S2
or S3 and S4 by the use of the Ready line on the 8237A.
Note that the data is transf\med directly from the I/O
device to memory (or viCE! versa) with lOR and MEMW (or
.MEMR and !OW) being active at ,the same time. The data
is not read into or driven out of the 8237A in I/O·to·
memory or memory·to·I/O DMA.transfers.
4
1
1
1
1
1
4
1
1
Figure 3. 8237A Internal Registers
The 8237A contains three basic blocks of control logic.
The Timing Control block generates internal timing and
external control signals- for the 8237A. The Program
Command Control block decodes the various com·
mands given to the 8237A by the microprocessor prior
to servicing a DMA Request. It also decodes the Mode
Control word used to select the type of DMA during the
servicing. The Priority Encoder block resolves priority
contention bj!tween DMA channels requesting service
simultaneously.
Memory·to·memory transfers require a read·from and a
write·to·memory to complete each transfer. The states,
which resemble the normal working states, use two
digit numbers for identification: Eight states are required for a single transfer. The first four states (S11,
S12, S13, S14) are used for.the read·fr9m·memory half
The Timing Control block derives internal timing from
the ~clock. input. In 8237A systems this Input will usually
2-90
AFN·OO789D
8237A/8237~4/8237~5
becomes active. Again, an Autoinitiallzation will occur
at the end of the service If the channel has been pro·
grammed for It.
and the last four states (521, 522, 523, 524) for the write·
to-memory half of the transfer.
IDLE CYCLE
When no channel Is requesting service, the 8237A will
enter the Idle cycle and perform "SI" states. In this
cycle the 8237A will sample the DREQ lines every clock
'cycle to determine If any channel Is requesting a DMA
service. The device will also sample eg, looking for an
attempt by the microprocessor to write or read the Inter·
nal registers of the 8237A. When CS Is low and HLDA Is
low, the 8237A enters the Program Condition. The CPU
can now establish, change or Inspect the Internal deflnl·
tlon of the part by reading from or writing to the Internal
registers. Address lines AO-A3 are Inputs to the device
and select which registers will be read or written. The
lOR and iOW lines are used to select and time reads or
writes. Due to the number and size of the Internal regis·
ters, an Internal fIIp·flop Is used to generate an addl·
tional bit of address. This bit Is used to determine the
upper or lower byte of the 16·bit Address and Word
Count registers. The fIIp·flop Is reset by Master Clear or .
Reset. A separate software command can also reset this
fIIp·flop.
Special software commands can be executed by the
8237A In the Program Condition. These commands are
decoded as sets of addresses with the C5 and lOW. The
commands do not make use of the data bus. Instruc·
tions include Clear First/Last Flip·FLop and Master
Clear.
Demlnd Trlnsfer Mode - In Demand Transfer mode the
device Is programmed to continue making transfers
until a TC or external EOP Is encountered or until DREQ
goes Inactive. Thus transfers may continue until the 110
device has exhausted Its data capacity. After the 110
device has had a chance to catch up, the DMA service Is
re·establlshed by means of a DREQ. During the time
between services when the microprocessor Is allowed
to operate, the Intermediate values of address and word
count are stored In the 8237A Current Address and Current Word Count registers. Only an EOP can cause an
Autoinitialize at the end of the service. EOP Is generated
either by TC or by an external signal.
Cascade Mode-This mode is used to cascade morethan one
8237 Atogether for Simple system expansion. The HRQ and
HLDA signals from the additionat8237 A are connected to the
DREQ and DACK signals of.a channel of the initial 8237A.
This allows the DMA requests of the additional device to
propagate through the priority network circuitry of the preceding device. The priority chain is preserved and the new device
must wait for its turn to acknowledge' requests. Since the
cascade channel of the initial 8237 A is used only for prioritizing the additional device, it does not output any address
or control signals of its own. These could conflict with the
outputs olthe active channel in the added device. The 8237A
will respond to DREQ and DACK but all other outputs except
HRQ will be disabled. The ready input is ignored.
ACTIVE CYCLE
Figure 4 shows two additional devices cascaded Into an
Initial device using two of the previous channels. This
forms a two level DMA system. More 8237As could be
added at the second level by using the remaining chan·
nels of the first level. Additional devices can also be
added by cascading into the channels of the second
level devices, forming a third level.
When the 8237A Is in the Idle cycle and a non·masked
channel requests a DMA service, the device will output
an HRQ to the microprocessor and enter the Active cycle. It is In this cycle that the DMA service will take
place, in one of four modes:
Single Transfer Mode - In Single Transfer mode the
device is programmed to make one transfer only. The
word count will be decremented and the address dec·
remented or incremented following each transfer. When
the word count "rolls over" from zero to FFFFH, a Ter·
minal Count (TC) will cause an Autoinitialize if the chan·
nel has been programmed to do so.
2ND LEVEL
\
1-
HRQ
DREQ
~
HLOA
DACK
8237A
DREQ
DACK
INITIAL DeVICE
Block Transfer' Mode - In Block Transfer mode the
device Is activated by DREQ to continue making trans·
fers during the service until a TC, caused by word co~nt
going to FFFFH, or an external End of Process (EOP) is
encountered. DREQ need only be held active until DACK
8237A
1ST LEVEL
MICROPROCESSOR
DREQ must be held active until DACK becomes active In
order to be recognized. If DREQ Is held active throughout the Single transfer, HRQ will go Inactive and release
the bus to the system. It will again go active and, upon
receipt of a new HLDA, another single transfer will be
performed, in8080A, 8085AH, 8088,.or 8086 system this
will ensure one full machine cycle execution between
DMA transfers. Details of timing between the 8237A and
other bus control protocols will depend upon the char·
acterlstics of the microprocessor involved.
1-
-
--
HRQ
HLDA
HRQ
HLOA
8237A
ADDITIONAL
DeVICES _
Figure 4. Cascaded8237As
2-91
AFN-00789D
8237A/8237Af.4/8237J4t.5
TRANSFER TYPES
Each of the three active transfer modes can perform three
different types of transfers. These are Read, Write and Verify.
Write transfers move data from and 110 device to the memory
by actlvetlng ~ and lOR. Read transfers move data from
memory to an 1/0 device by activating MEMR and R5W. Verify
transfers are pseudo transfers. The 8237A operates as in
Read or Write transfers generating addresses, and responding
to EOp, etc. However, the memory and 1/0 control lines all
remain inactive. The ready input is ignored in verify mode.
Memory·to-Memory-To perform block moves of data from
:)ne memory address space to another with a minimum of
program effort and time, the 8237A includes a memory-tomemory transfer feature. Programming a bit in the Command
register selects chan nels 0 to 1 to operate as memory-tomemory transfer channels. The transfer is initiated by setting
the software DREQ for channel O. The 8237A requests a DMA
service in the normal manner. After HLDA is true, the device,
using four state transfers in Block Transfer mode, reads data
from the memory. The channel 0 Current Address register is
the source for the address used and is decremented or incremented in the normal manner. The data byte read from the
memory is stored in the 8237A internal Temporary register.
Channell tben performs afour-stete transfer of the data from
the Temporary register to memory using the address in its
Current Address register and incrementing or decrementing it
In the normal manner. The channe.1 1 current Word Count is
decremented. When the word count of channel 1 goes to
FFFFH, a TC is generated causing an EQj5 output terminating
the service.
Channel 0 may be programmed to retain the same address for all transfers. This allows a Single word to be
written to a block of memory.
The 8237A will respond to external EOP signals during
memory-ta-memory transfers. Data comparators, in
block search schemes may use this input to terminate
the service when a match is found. The timing of
memory-to-memory transfers is found in Figure 12.
Memory-ta-memory operations can be detected.as an
active AEN with no DACK outputs.
AulDinltlallze-By programming a bit in the Mode register, a
channel may be set up as an Autoinitialize channel. During
Autoinitialize ini~alization, ,the original values of the Current
Address and, Current Word Count registers are automatically
restored from the Base Address and Base Word count registers
of that channel following EOI5. The base registers are loaded
simultaneously with the current registers by the miCrOProcessor and remain unchanged throughout the DMA service.
The mask bit Is not altered when the channel is in Autoinitialiie. _
Following Autoinitialize the channel is ready to perform
another DMA service, without CPU intervention, as soon as a
valid DREQ Is detected. In order to Autoninitialize both channels in a memory-to-memorytransfer, both word counts should
be, programmed identically. If interrupted externally, EQj5
pulses should be applied in both bus cycles.
Priontv-The 8237A has two types of priority encoding available as software selectable QPtions. The first is Fixed Priority
which fiXes the channels in priority order based upon the
descending value of their number. The'channel with the lowest
priority is 3 followed by 2, 1 and the highest priqrity channel"
O. After the recognition of anyone channel for service, the other channels are prevented from interferring with that service until it is completed.
The second scheme Is Rotating Priority. The last channel to get service becomes the lowest priority channel
with the bthers rotating accordlrigly.,
'
1et
Senlce
highest
lowest
2nd
.
s4n1ce '
o
1'_serylce~ 3_request
2
,0
2_servICe\3_SeivICe
,0
1
3
1
2
, With Rotating Priority In a single chip DMA system, any
device requesting service Is guaranteed to be recognized after no more than three higher priority services
have occurred. This prevents anyone channel from
monopolizing the system.
Compressed Timing - In order to achieve even greater
throughput where system characteristics permit, the
8237A can compress the transfer, time to two clock
cycles. From Figure 11 It can be seen that state S3 Is
used to extend the access time of the read pulse. By
removing state S3, the read pulse width is made equal to
the write pulse width and a transfer consists only of
state 52 to change the address and state S4 to perform
the read/write. 51 states will stili occur when A8-A15
need updating (see Address Generation). Timing for
compressed transfers is found in Figure 14.
Address Generation - In order to reduce pin count, the
8237A multiplexes the eight higher order address bits
on the data lines. State Sl Is used to output the higher
order address bits to an external latch from which they
may be placed on the address bus. The failing edge of
Address Strobe (AD5TB) Is used to load these bits from
the data lines to the latch. Address Enable (AEN) Is used
to enable the bits onto the address bus through a threestate enable. The lower order address bits are output by
the 8237A directly. Lines AO-A7 should be connected to
the address bus. Figure 11 shows the time relatklOshlps
bet~een CLK, AEN, ADSTB, DBO-DB7 and AO-A7.
During Block and Demand Transfer mode services,
which Include multiple transfers, the addresses generated will be sequenilal. For many transfers the data held
In the ex.ternal address latch will remain t,he saine. Thl,s
data need only change when a carry or'borrow from A7
to A8 takes place In the normal sequenc,e of addresses.
transfers,' the 8237A executes
To save time and
Sl states only when updating of A8-A15 in the latch is
necessary. This I)'leans for long services, Sl states and
Address Strobes may occur only onc,e every 258 transfers, a savings :of 255 clock cycles for each 258
transfers.
speed'
AFN·OO789D
8237A/8237~4/8237~
Command Register
REGISTER DESCRIPTION
7
•
5
4
3
2
1
0
~III
Num....
l I I I I I II I
Current Address Raglstsr - Each channel has a HI..blt
Current Address register. ,This register holds the value
of the address used during DMA transfers. The address
Is automatically incremented or decremented after each
transfer and the Intermediate values of the address are
stored In the Current Ad,dress register during the transfer. This register Is written or read by the microprocessor in successive 8..blt bytes. It may also be relnl·
tiallzed by an Autoinitialize back to its original value.
Autoinitialize takes place only after an EOP.
Y
0
1
Mernory·to-memory dl8eble
Memory-to-memory enable
Y
0
1
X
Channel 0 add..... hold dluble
Channel 0 eddr_ hold enable
II bll 0 .. 0
I 0
I 1
f 01
tX
Current Word Raglster - Each channel has a 16-bit Cur·
rent Word Count register. This register determines the
number of transfers to be performed. The actual number
of transfers will be one more than the number programmed in the Current Word Count register (i.e., programming a count of 100 will result in 101 transfers). The
word count is decremented after each transfer. The
Intermediate value of the word count Is stored In the reg·
Ister during the transfer. When the value in the register
goes from zero to FFFFH, a TC will be generated. This
register is loaded or read in successive 8·blt bytes by
the microprocessor In the Program Condition. Follow..
ing the end of a DMA service it may also be reinitialized
by an Autoinitialization back to its original value. Autoinitialize can occur only when an EOP occurs. If it is not
Autoinitialized, this register will 'have a count of FFFFH
after,TC.
0
j
I 1
Normal timing
Compreeaed timing
II bit 0 .. 1
Fixed priority
Rotating priority
IX
f 01
Lat. write .electlon
Extended write .electlon
II bl13" 1
I 0
I 1
DREQ 88nse active high
DREQ 88nse active low
0
DACK 88nse active low
DACK len.e active high
j
I 1
Mode Register
7
I
8
5
4
3
2
1
04--BltNumber
I II I I II
-~L{ 01
'-,-""
00 Channel 0 select
Channel'l select
10 Channel 2 select
11 Channel 3 .elect
Base Address and Base Word Count Raglsters - Each
channel has a pair of Base Address and Base Word
Count registers. These 16·blt registers store the original
value of their associated current registers. During Auto·
initialize these values are used to restore the current
registers to their original values. The base registers are
written simultaneously with their corresponding current
register in 8·bit bytes in the Program Condition by the
microprocessor. These registers cannot be read by the
microprocessor.
00
01
10
11
XX
I o
I
1
I o
Command Raglster - This 8·bit register controls the
operation of the 8237A. It is programmed by the microprocessor In the Program Condition and is cleared by
!'teset or a Master Clear instruction. The following table
lists the function of the command bits. See Figure 6 for
address coding.
Controller eneble
Controller dl8eble
Verily transler
Write trensler
Reed transfer
Illegal
II bits 8 and 7 .. 11
Autoinitialization disable
Autoinitialization enable
I
1
Address Increment select
Address decrement select
f
l
00
01
10
11
Demand mode select
Slngl. mode .elect
Block mode .elect
C8acade mode select
o
Reaat request bit
Set request bit
Request Raglster
Mods Raglster - Each channel has a 6·bit Mode regis..
ter associated with it. When the register is being written
to by the microprocessor in the Program Condition, bits
o and 1 determine which channel Mode register is to be
written.
'-----i 1
Request Register - The 8237A can respond to requests
for DMA service which are initiated by software as well
as by a DF\EQ. Each channel has a request bit associ·
ated with it in the 4-bit Request register. These are non·
maskable and subject to prioritization by the Priority
Encoder network. Each register bit is set or reset sepa·
rately under software control or Is cleared upon genera·
tion of
T,C or external E()P.The entire register is
cleared by a Reset.. To set or reset a 'bit, the software
loads the proper form of the data word. See Figure 5 for
register address coding. In order to make a software reo
quest, the channel must be in Block Mode.
a
,2·93
AFN·OO7880
intJ.
S237A/S23"A-4/S237A-S
Mask Register ... Each channel has associated with It Ii
mask bit which can be set to disable the Incoming
DREQ. Each mask bit Is set when its associated channel
produces an ,mP If the channel Is not programmed for
Autoinitialize. Each bit of the 4-blt Mask register may
also be set or cleared separately under software control.
The entire register Is also set by a Reset. This disables
all DMA requests until a clear Mask register Instruction
allows them to occur. The Instruction to separately set
or clear the mask bits Is 'similar In form to that used with
the Request register. See Figure 5 for Instruction addressing.
I,
1
Channel 0
Ohannel 1
' - - - - - 1 Channel 2
' - - - - - - 1 ,Channel 3
Channel
Channel
Channel
Channel
L{
00 Select channel 0 maek bit
01 Select channel 1 mask bit
10 Select channel 2 mask bit
11 Select channel 3 mask bit
'-----I 0
1
4,3
2
1
O.--altHumber
o
1
Clear channel 0 mask bit
Set channel 0 mask bit
o
Clear channel 1 mask bit
Set channel 1 mask bit
1
' -_ _-! 0
1
' -_ _ _-I 0
1
Register
Operation
Ccmmand
Mode
Request
Mask
Mask
Temporary
Status
Write,
Write
Write
Set/Reset
Write
Read
Read
0
0
0
0
0
'0
0
lOR
1,
1
1
1
1
0
0
Clear channel 2 mask bit
Set channel 2 mask bit
Figure 6 lists the address codes for 'the software commands:
lOW
A3
A2
A1
AD
0
1
1
1
1
1
1
1
0
0
0
1
0
1
1
0
1
1
'0
0
0
1
1
I
Clear First/Last FliP-Flop: This co'mmand is executed
prior to writing or reading new address or word count
information to the 8231A. This Initializes the flip-flop
to a known state so that subsequent accesses to regIster contents by the microprocessor will address
upper and lower bytealn the correct sequence.
Clear Mask Register: This command clears the mask
bits of all four channels, enabling them to accept
DMA requests. '
Clear channel 3 mask bit
Set channel 3 mask bit
0
'1 request
2 request
3 request
Master Clear: This software instruction has the same
effect as'the hardware Reset. The Command, Status,
Request; Temporary; and Internal First/Last Flip-Flop
registers are,cleared and the Mask register is set. The
8237A will enter the Idle cycle.
Signals
OS
0 request
commands which can be e/Cecuted in the Program Condition.
They do not depend on any speCific bit pattern on the data
bus. The three ~ftware commands are:
Clear mask bit
Set mask bit
I
5
TC
TC
TC
TC
Software Commands-These are additional special80ftware
All four bits of the Mask register may also be written
with a single command.
8
reechld
reached
reached
reached
Temporary Register - The Temporary register Is used
to hold data during memory-to-memory transfers. 'Following the completion of the trarlsfers, the last word
moved can be read by the microprocessor In the Program Condition. The Temporary register always contains the last byte transferred In the previous memoryto-memory operation, unless cleared by a Reset.
. . . ."T"'-r-r-,~r1..,..O...,~ alt Hum. .
Don't Care
has
has
has
has
0
0
1
1
0
0
0
Sign."
O·
1
1
0
Figure 5_ Definition of Register Codea
Status Regl"er - The Status register'ls available to be
read out of the 8237A by the microprocessor. It contains
infotlnation about the status of the devices at this point.
This infonnatlon Includes which channels have reached
a terminal count and which channels have pending DMA
requests: Bits 0-3 are set every time a TC is reached by
that channel or an external &lP-is applied. These bits
are cleared upon Reset and on each Status Read. 'Bits
4-7 are set whenl!ver their corresponding channel Is,
requesting service.
A3
A2
AI
AD
lOR
iOW
1
,0
a
0
0
1
1
0
0
0
1
0
Write Command Regrater
1
0
0
1
0
1
Illegal
1
0
0
1
1
0
Wnte Reque.t Regllter
1
0
1
0
0
1
11_1
1
0
1
0
1
0
1
0
1
1
0
1
1
o .
1
1
1
0
Wnt. Mode Regl.lar '
1
1
0
0
0
1
Illegal
Operation
Read Statue Register
. Write SIngle Meak Register Bd
Illegat
1
1
0
0
1
0
Clear Byte POinter Flip/FlOP
,1
1
0',
1
0
1
Read Temporary Regllttl,
1
,1
0
1
1
0,
MaaterCfMr
1
1
1.
~
0
1
III•••,
1
1
1
0
1
0
Clear Mask Register
1
'1
1
1
'0
1
Illegal
1
1
1
1
1
0
Write All Mask,Realater Ekt.a
"
Figure 6_ Software Command Code.
2-94
AFN·OO7BBil
8237 A/8237A-4/8237A-5
Slgnols
,
Chlnnel
0
Register
Base and Current Address
Current Address
Base and Current Word Count
Current Word Count
1
Base and Current Address
Current Address
Base and Current Word Count
Current Word Count
2
Base and Current Address
Current Address
Base and Current Word Count
Current Word Count
3
Base and Current Address
Current Address
Base and Current Word Count
Current Word Count
Operltlon
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
A3
A2
At
AO
Intemll Flip-Flop
Dlte Bus DBO-DB7
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
AG-A7
AS-At 5
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
0
1)
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
t
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
0
CS , lOR
.
lOW
t
t
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Ao-A7
AS-At5
WQ-W7
WS-WI5
wyJ-W7
W8-WI5
AO-A7
AS-At5
AG-A7
Ai-A15
Wo-W7
W8-Wt5
WO-W7
W8-WI5
AO-A7
AS-A15
Ao-A7
AS-At5
Wo-W7
WS-Wt5
wyJ-W7
W8-Wt5
AO-A7
AS-A15
Ao-A7
AS-A15
WO-W7
W8-W15
WtO-W7
W8-WI5
Figure 7. Word Count and Address Register Command Codes
PROGRAMMING
The 8237A will accept programming from the host processor any time that HLDA is inactive; this is true even if
HRQ ,is active, The responsibility of the host is to assure
that programming and HLDA are mutually exclusive.
Note that a problem can occur if a DMA request occurs,
on an unmasked channel while the 8237A is being pro·
grammed, For instance, the CPU may be starting to
reprogram the two byte Address register of channel 1
when channel 1 receives a DMA request. If the 8237 A is
enabled (bit 2 in the command register is 0) and channel
1 is unmaSked, a DMA service will occur after only one
byte of the Address register has been reprogrammed_
This can be avoided by disablin'g the controller (setting
bit 2 in the command register) or masking the channel
before programming any other registers. Once the programming is complete, the controller can be enabled/un·
masked,
After power·up it is suggested that all internal locations,
especially the Mode registers, be loaded with some
valid value. This should be done even if some channels
are unused.
2-95
AFN-00789D
8237A/8237~4/8237A·5
APPLICATION INFORMATION
operation comes out in two bytes - the least significant 8 bits on the eight address outpufs and the most
significant 8 bits on the data bus_ The contents of the
data bus are then latched into the 8282 8-bit latch to
complete the full 16 b,its of the address bus. The 8282 is
a high speed, 8-blt, three-state latch in a 2().pln package.
After the Initial transfer takes place, the latch is updated
only after a carry or borrow Is generated in the least significant address byte. Four DMA channels are provided
when one 8237A is used.
Figure 8 shows a convenient method for conflguril1g a
DMA system with the 8237 A controller and an 8080AI
808.5AH microprocessor system. The multi mode DMA
controller issues a HRQ to the processor whenever
there is at least one valid DMA request from a peripheral
device. When the processor replies with a HLDA signal,
the 8237 A takes control of the address bus, the data bus
and the cOl]trol bus. The address for the first transfer
)
ADDRESS BUS AO-A15
....
....
y
i"--
A8-A15
-"
....
I--
I
AO-A15
A4-A7
AO-A3
8282
STB
I
...
AEN
~
cs
8·BIT LATCH
....
ADSTB
BUSEN
HLDA
8237A
HLDA
l-
HOLD
HRQ,
~
u
CPU
w
gj
a:
iI i
I~
I )
CLOCK
RESET
MEMR
~
..,
..,
8w
."
a:
l2
u
DBODB7
,t
-.l\
,
r
i"--
"
f14
,
l~'
MEMW
BUS
iIDi
iOW
DBO-DB7
...
....
....
~
SYSTEM DATA BUS
~
)
r
Figure 8_ 8237A System Interface
2-96
AFN·OO789D
intJ
8237A/8237~4/8237~
ABSOLUTE MAXIMUM RATINGS·
'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
AmblentTemperature under Bias ••••••••• O'C to 70'C
Storage Temperature ••••••••••••• -55'Cto + 150'C
Voltage on any Pin with
Respectto Ground •••••••••••••••••••• - 0.5 to 7V
Power Dissipation •••••••••••••••••••••••• : 1.5 Watt
D.C. CHARACTERISTICS (TA = O°C to 70°C, Vee =
Symbol
VOH
Parameter
Min.
Output High Voltage
VOL
Output LOW Voltage
5.0V ±5%, GND = OV)
1IJp.(1)
Max.
Unit
Test Conditions
"A
"A (HRQ Only)
2.4
V
IOH = -200
3.3
V
IOH = -100
45
V
IOl = 2.0rnA (data Bus)EIW
IOl = 3.2rnA (other outputs) (Note 8
IOl = 2.5rnA (ADSTB) (Note 8)
V
V IH
Input HIGH Voltage
2.2
Vcc+ 0•5
V il
Input LOW Voltage
-0.5
0.8
V
III
Input Load Current
±10
OV ~ VIN ~ Vcc
ILO
Output Leakage Current
±10
"A
"A
Icc
VeeSupply Current
110
130
rnA
TA=+25°C
130
150
rnA
TA=O°C
Co
Output Capacitance
4
8
pF
C1
Input Capacitance
8
15
pF
C1Q
I/O Capacitance
10
18
pF
.
O.45V
~ VOUT ~ Vcc
Ic = 1.0 MHz, Inputs = OV
NOTES:
1 Typical values are for TA = 25°C, nominal supply voltage and nominal processing parameters
2. Input liming panimeters assume transition times of 20 ns or less. Waveform measurement pOints for both input and output signals are 2 OV for HIGH and 0 8V
for lOW. unless otherwise noted.
3. OUlput loading is 1 m gate plus 150pF capacitance, unless otherwise noted.
4. The net lOW or MEMW Pulse wtdth for normal wrHe will be TCY-1 00 ns and for extended write wtll be 2TCY-100 ns. The net lOR or MEMR pulse WIdth for
normal read will be 2TCY-SO ns and for compressed read wtll be TCY-SO ns.
5. TOQ Is specified for two different output HIGH levels TOQ1 is measured at 2.0V. TOQ2 is measured at 3.3V. The value for TOQ2 assumes an external 3.3k2
pull-up resIstor connected form HRQ to Vcc.
6. DREQ should be held active unHI DACK Is returned.
7 DREQ and DACK signals may be active high or active low. Timing diagrams assume the active high mode.
8. A revision of the 8237 A Is planned for shipment In April 1964, which wtllimprove the folloWing charactaristics.
1. VIH from 2.2V to 2.0V
2. VOL from 0.45V to 0.4V on all outputs. Test condHion IOl = 3.2 mA
Please contact your local sales office at thai time for more Information.
9. Successive read andlor write operations by the external processor 10 program or examIne the controiler must be bmed to allow at least 600 ns for the 8237A,
at least 500 ns for the 82~7 A-4 and alleast 400 ns for the 8237 A-5, as recovery time between active read or wrila pulses
10. Emi is an open collector output. This parameter assumeslhe presence of a 2.2K puilup to Vcc.
11. Pin 5 is an Input thai should always be at a logic high level An Internal puil-up resistor wtll establish a logic high when the pin is left floating. II is recommended however, thai pin 5 be tied to Vcc.
A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUT/OUTPUT
u~...>
TEST POINTS
~
~
ux=
<.
u
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC "1" AND 0 45V FOR
~~ggl~v"~~~I~[NpGG:t:E.~S,~(=~rs ARE MADE AT 2 OV FOR A LOGIC "1"
2-97
AFN·OO789D
8237A/82~7A..4/8237 A-5
A.C. CHARACTERISTICS~DMA (MASTER) lI/IODE (TA=O·C to 70·C,
Vee= +5V:t5%. GND=OV)
8237A
Symbol
,
Parameter
Min.
8237A-S
8237A-4
Max.
Min.
Max.
Min.
Max.
Unit
ns
TAEl
AEN HIGH from ClK lOW (S1) Delay Time
300
225
200
TAET
AEN lOW from ClK HIGH .(81) Delay Time
200
150
130
ns
TAFAB
ADR Active to Float Delay from ClK HIGH
150
120
90
ns
TAFC
READ or WRITE Float from ClK HIGH
150
120
120
nS
TAFDB
DB Active to Float Delay from ClK HIGH
250
190
170
ns
TAHR
ADR from READ HIGH Hold Time
TAHS
DB from ADSTB lOW Hold Time
TAHW
ADR from WRITE HIGH Hold Time
TAK
TCY-100
TCY-100
.rCY-100
ns
50
40
30
ns
TCY-50
TCY-50
TCY-50
ns
DACK Valid from ClK lOW DelayTime (Note 7)
250
220
170
ns
EOP HIGH from eLK HIGH Delay Time (Note 10)
250
190
170
ns
EOP lOW from ClK HIGH Delay TIme
250
190
170
ns
250
190
170
ns
TASM
ADR Stable from ClK HIGH
i
TA$S
DB to ADSTB LOW Setup Time
I
TCH
100 •
100
100
Clock High Time (Transitions,,; 10 ns)
120
100
80
ns
TCl
Clock lOW Time (Transillons,,;10 ns)
150
110
68
ns
TCY
ClK Cycle Time
320
TOCl
ClK HIGH to READ or WRITE lOW Delay (Note 4)
TDCTR
READ HIGH from ClK HIGH (S4) Delay Time
(Note 4)
TOCTW
WRITE HIGH from ClK HIGH (84) Delay Time
(Note 4)
TOO1
!
HROValid from ClK HIGH Delay Time (Note 5)
TOO2
TEPS
EOP lOW from ClK lOW Setup Time
ns
200
250
ns
270
200
190
ns
270
210
190
ns
200
150
130
ns
160
120
120
ns
250
190
120
60
40
45
300
225
ns
ns
TEPW
EOP Pulse Width
TFAAB
ADR Float to Active Delay from ClK HIGH
250
190
220
170
ns
ns
TFAC
READ or WRITE Active from ClK HIGH
200
150
150
ns
TFADB
DB Float to Active Delay from ClK HIGH
30~
225
200
ns
THS
HlDA Valid to ClK HIGH Setup Time
TlDH
Input Data from MEMR HIGH Hold Time
TIDS
Input Data to MEMR HIGH Setup Time
TODH
Output Data from MEMW HIGH Hold Time
TODV
Output Data Valid to MEMW HIGH
TOS
DREO to elK lOW (SI, 84) Setup Time (Note 7)
TRH
100
75
75
ns
0
0
0
ns
250
190
170
20
20
10
ns
200
125
125
ns
0
0
0
ns
elK to READY lOW Hold Time
20
20
,20
ns
TRS
READY to ClK lOW Setup Time
100
60
60
TSTl
ADSTB HIGH from elK HIGH Delay Time
TSTT
ADSTB lOW from CLK HIGH
ns
/
D~layTime
2-98
200
150
140
110
.
ns
130
ns
90
ns
AFN-00789D
intJ
8237A/8237~4/8237~5
A.C. CHARACTERISTICS-PERIPHERAL (SLAVE) MODE
= OOC to 70°C, VCC =5.0V ±5%,
= OVr
(TA
GND
8237A
Parameter
Symbol
Min.
8237A-4
Min.
Max.
8237A-5
Max.
Min.
Unit
Max.
TAR
ADR Valid or CS LOW to READ LOW
50
50
50
ns
TAW
ADR Valid to WRITE HIGH Setup Time
200
.1 SO
130
ns
TCW
CS LOW to WRITE HIGH Setup Time
200
150
130
ns
TOW
Data Valid to WRITE HIGH Setup Time
200
lS0
130
ns
TRA
ADR or CS Hold from READ HIGH
0
0
0
TRDE
Data Access from READ LOW (Note 3)
TRDF
DB Float Delay from READ HIGH
TRSTD
Power Supply HIGH to RESET LOW Setup Time
TRSTS
'"
200
100
20
ns
200
100
20
140
ns
70
ns
0
500
SOO
500
ns
,RESET to First IOWR
2TCY
2TCY
2TCY
ns
TRSTW
RESET Pulse Width
300
300
300
ns
TRW
READ Width
300
2S0
200
ns
TWA
ADR from WRITE HIGH Hold Time
20
20
20
ns
TWC
CS HIGH from WRITE HIGH Hold Time
20
20
20
ns
TWO
Data from WRITE HIGH Hold Time
30
30
30
ns
TWWS
Write Width
200
200
160
. ns
WAVEFORMS
SLAVE MODE WRITE TIMING
L
TCW
I,
TAW
AO-A3
---.J
-
'-
=:)
(NOTE I)
I
-TWA
INPUT VALID
TOW
DBO-DB7
~TWC
)
TWWS
----,.
-i
-
-TWO
(
INPUT VALID
Figure 9. Slave Mode Write
SLAVE MODE READ TIMING
cs~
AO-A3~
iliA
(
ADDRESS MUST BE VALID
H'"l
t..
TRDE
DBO-DB7
Figure 10. Slave Mode Read
2-99
~-
(NOTE I)
TRW
t
TRDF3DATA OUT VALID
___
AFN·Q0789D
intJ
8237A/8237Ao4/8237A-S
WAVEFORMS (Continued)
DMA TRA~SFER TIMING
.,
elK
-jTQS
DtiQ
HO.
m
T~_
\\ l\
F
lLLi
11
I
TFADB
\
rFAAI
t,
~
TC"
I-
TAET
r
~TT
-
- - rEPS
~
1-
ADDRESS VALID
~
DACK
I
TFAC
-
i
""\
- ~~~T'SS
f:: r-r
AI~A15"i
- 1 FfiTAi'·O
,
I-
--
lAIM
-
-
TAFAI
I-
TAHW
f-TAHW
ADDRESS VALID
-fAHA
-TAHR
1\
/
~
""-,
~
TOCTA
,----..,.
I
~
<-_
(FOR
~ENDED
TDeTW
yl~_
WRITE)
INT'"
T£PW
I
-
,\ ,\\\\\\\\\
,,,TO
m_
~
TAELI--I
Tsn
I
TCV -
(NOTE 6)
-
I,
I
r
F
T~~
.EN
010-087
!\\ \'
l\\
Sf
TCl
1TQS~
l-
THS-
""OA
..
--f ~~~~~~~~~~~~ \..J ~~~~~
.
81
54
\\\\\\\\\\\
~
TDCTA
l-
I-
r-- TAFC
Ir-,",
TDCTW
~
I-
~<\
~
-},;--~
(jIllI I I I I I I I
Figure 11. DMA Transfer
2-100
AFN-00789D
inter
B237A/B237~4/B237~5
WAVEFORMS (Continued)
MEMORY-TO-MEMORY TRANSFER TIMING
ADSTB
AD-A7
DBO-DB7
EXT EOP
Figure 12. Memory·to-Memory Transfer
READY TIMING
ClK
TDCl --+~--I
EXTENDED
WRITE
1-
TRH
TRS
TRS1
READY
\\\\\\\\\\\
Figure 13. Ready
2-101
AFN·OO7B9D
inter
8237A/8237ftr;4/8237~5
WAVE,FORMS (Continued)
COMPRESSED TRANSFER TIMING
elK
AO-A7
REAOY
Figure 14. Compressed Transfer
RESET TIMING
Vee
r--------------------------------------~I~I-----------TRSTO - - - - - - - - - - 1
------J/ll-.-------
-----TRSTW - - - )
RESET _ _ _- . . J
---~
iOIi OR row
Figure 15. Reset
AFN-007890
8257/8257·5
PROGRAMMABLE DMA CONTROLLER
• MCS-85$ Compatible 8257-5
• Single TTL Clock
• 4·Channel DMA Controller
• Single
• Priority DMA Request Logic
+ 5V Supply
• Auto Load Mode
• Channel Inhibit Logic
• Terminal Count and Modulo 128
Outputs
• Available in EXPRESS
- Standard Temperature Range
The Intel' 8257 is a 4·channel direct memory access (DMA) controller. It IS specifically designed to simplify the
transfer of data at high speeds for the Intel@ microcomputer systems. Its primary function is to generate, upon a
peripheral request, a sequential memory address which will allow the peripheral to read or write data directly to or
from memory. Acquisition of the system bus in accomplished via the CPU's hold function. The 8257 has priority logic
that resolves the peripherals requests and Issues a composite hold request to the CPU. It maintains the DMA cycle
count for each channel and outputs a control signal to notify the peripheral that the programmed number of DMA
cycles is complete. Other output control signals simplify sectored data transfers. The 8257 represents a significant
savings in component count for DMA·based microcomputer systems and greatly simplifies the transfer of data at
high speed between peripherals and memories.
DAao
A,
A,
ORO 1
A,
A,
TC
A,
A,
OAO 2
A,
A,
A,_
A,
A,
cs--_---l
ClK
00
0,
A.
RESET
0,
A,
OACK 2
0,
A.
5AcK'3
A,
0,
DACK 0
r3ACi(1
'"
0,
GND
A ••
ADSTB
TC _ _ _...J
MAAIC. _ _ _ _-.J
Figure 2. Pin Configuration
Figure 1. Block Diagram
2·103
8257/8257 ·5
FUNCTION~L
DESCRIPTION
Block'Diagram Description
General
The 8257 is a programmable, Direct Mem,ory Access
(DMA) device which, when coup,l~ with a single IntelI!')
8212 I/O port device, provides a complete four-channel
DMA controller for use in Intel 18 micro~omputer systems.
After being initialized by software, the 8257 can transfer a
block of data, containing up to 16,384 bytes, between
memory and a peripheral device directly. without further
intervention required of the CPU. Upon receiving a DMA
transfer request from an enabled peripheral, the 8257:
1. Acquires control of the system bus.
2. Acknowledges that requesting peripheral which is
connected to the highest priority channel.
3. Outputs the least significant eight bits ofthe memory
address onto system address lines Ao-A7, outputs
the most significant eight bits of the memory address
to the 8212 110 port via the data bus (the 8212
places these address bits on lines A8"A,sl. and
1. DMA Channels
The 8257 provides four separate DMA channels (labeled
CH-O to CH-3). Each channel includes two sixteen-bit
registers: (1) a DMA address register, and (2) a terminal count register. Both registers must be initialized
before a channel Is enabled. The DMA address register is
loaded with the address of the first memory location to be
accessed. The value loaded into the low-order 14-bits of
the terminal count register specifies the number of DMA
cycles minus one before the Terminal Count (TC) output
is activated. For instance, a terminal count of 0 would
cause the TC output 10 be active in the first DMA cycl!! for
that channel. In general, if N = the number of desired DMA
cycles, load the value N-l into the low-order 14-bits of the
terminal count register. The most significant two bits of the
terminal count register specify the type of DMA operation
for that channel.
4. Generates the appropriate memory, and I/O read/
write control signals that cause the peripheral to
receive or deposit a data byte directly from or to the
addressed location in memory.
The 8257 will retain control of the system bus and repeat
the transfer sequence, as long as a peripheral maintains its
DMA request. Thus, the 8257 can transfer a block of data
to/from a high speed peripheral (e.g., a sector of data on a
floppy disk) in a Single "burst". When the specified
number of data bytes ·have been transferred, the 8257
activates its Terminal Count (TC) output, informing the
CPU that the Operation is complete.
The 8257 offers three different modes of operation:
(1) DMA read, which causes data to be transferred from
memory to a peripheral; (2) DMA write, which causes
data to be transferred from a peripheral to memory;
and (3) DMA verify, which
TEST POINTS
0.8
0.45
<'")C
DEVICE
UNDER
TEST
'I
Cl ,,50 PF
0.8
A C TESTING INPUTS ARE DRIVEf'II AT 2 4V FOR A LOGIC 1 AND 0 45V FOA
A LOGIC 0 TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A lOGIC '1
AND 08V FOR A LOGIC 0
C L INCWDES JIG CAPACITANCE
Tracking Parameters
Signals labeled as Tracking Parameters (footnotes 1 and 5·7 under A.C. Specifications) are signals that follow similar
paths through the silicon die. The propagation speed of thelile signals varies in the manufacturing process but -the
relationship between all these parameters is constant. The variation is less than or equal to 50 ns.
Suppose the following timing equation is being evaluated,
T A(MIN)
+
T B(MAX) oS 150 ns
and only minimum specifications exist for TA and TB. If TA(MIN) is used, and if TA and T B are tracking parameters,
.TB(MAX) can be taken as TB(MIN) + 50 ns.
TA(MIN) + (T B(MINI* + 50 ns)
oS
150 ns
* if TA and TB are tracking parameters
WAVEFORMS-PERIPHERAL MODE
WRITE
- - - , - TAW - -
I-TWA
CHIP SELECT
READ
~
TAW
--~
>t·
,
r
._1_ Two
~
_TWAf--
DATABUS_ _ _ _ _ _
i-·
row
I/OWR---------U
-
II;.--1
-:'
RESET
-/:"---'l-I
CHIP SElECT
lRSTS
I
Tww
2-113
AFN·OI840D
825718257 ·5
WAVEFORMS-DMA
CONSECUTIVE. CYCLES AND BURST MODE SEQUENCE
8'
I
8.
I
I
SO
I
8.
82
I
S3
I
8.
S4
82
S3
S4
I
8.
8'
CLOCk
DR003 __
~
__
~+-
______
~"
____-+____
-J~
+-____________
________
~-1
____-+____________
HRO ________J.
- \._----
HLDA ____________- ' .
AEN ____________
~--~
ADR07(LOWERAOR) _ _ _
DATAO 7 (UPPER AOR)-
TSH
ADR STB
----!'
MEM/WR/IIQ WR -
READY
Te/MARK
CLOCK
NOTE
The ctock w.....foffn "
dupl~fOfCI.rtty
'The 8257 r'WtU,rtI only
ontclodl,nput
8'
so
51
52
53
I
2-114
S4
I
5.
52
53
S4
5'
5'
5'
AFN-01840D,
825718257·5
WAVEFORMS (Continued)
CONTROL OVERRIDE SEQUENCE
I
S1
I
S2
I
53
I
Sol
SI
I
SI
I
! so
S1
I
52
CLOCK
OR003 ------V+---------+- -- -HRO
-----~ ~--------..J} F HS
HLOA
AEN
T
..J
NOT READY SEQUENCE
so
I
S1
SW
I
SW
I
Sol
I
SI
i
SI
I
SI
CLOCK
DROOl
-~~----~---~--
""""Ili,fORD _____
MEM-WR,f{)WR
READY
Te/MARK
J,...--r\--+I-----+I----I-r-.......\.. _---
_-_-_-_-_-_./:_-_-:_T-R_Sr?- ."b,. . .: : -~- - +!1-'_- -'-:T~R-S:-_/T_-_~-_~" 'I\. _- - --------l-"l'''------'..... \
I
2-115
\
AFN-01840D
intJ
·8257/8257·5
A"
..
I
I
A,LE
~
t
STI
'3
052
'212
6ii
01,--01 1
,
-
ADo
Y"
iIIi
~~A'
~I,
0,
~A,
~ctr
,
,
,
8
~
~8J
,
0,
~A.
sn (81
•
7
•
'2
13 8.
--
---
R!Il
lOW
CHIP
SELECT
i5l
1
IOID
L
=>
HOLD
HLOA
CLK(OUTI
IfRn iN
RESET OUT
A,
Y"
~
erA
MO
I
I
III)
_
ADDRESS
BUS
00,--00,
AD,
....
r==> ~"
ATffi
-
U
-
'---
I·
"1
:7
82575
R!Il
DRDo
DACK o
~ M"EMW
ORO,
iOW
DACK,
ORal
OACKI
"RO
ORaJ
HLOA
DACKl
----.!!..
CLK
----!!..
RESET
TC
MARK
t---
,.
25
ORa.
OACK a
'B
2.
ORO,
,."
OR0 2
,..
,
36
•
DACK,
i5AcK 1
ORal
6ACK)
TC
M.o.RK
j"
rn
01,
,
,
STB
DO,
,
,
8212
01,
MO
DO,
Dli
tJ
Figure 13. Detailed System Interface Sche.!I1atlc
2-116
IllI'i
8
DS2
,
CONTROL
aUs
v"
'3
---v'
R!Il
ADSTa
A'N
•
~
--
.,,, f-A,
0,
MEMR
,
DATA BUS
0,
READY
CS
--l.c
--12..
.,.-!-
,
I
y
REAOY
--Lc
--l.c
0,
,
-NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specIfication is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ......... O°C to 700 e
Storage Temperature ............... -65°e to +150oe
Voltage on Any Pin
With Respect to Ground .............. -0.5V to + 7V
Power Dissipation ............................ 1 Watt
D.C. CHARACTERISTICS
(8257: TA = ooe to 70oe. Vee = 5.0V ±5%. GND = OV)
(8257-5: TA = ooe to 70oe. Vee = 5.0V ±10%. GND = OV)
Symbol
Parameter
Min.
Max.
Unit
Vil
Input Low Voltage
-0.5
O.S
Volts
2.0
Vee+· 5
Volts
VIH
Input High Voltage
Val
Output Low Voltage
VOH
Output High Voltage
VHH
HRQ Output High Voltage
Icc
Vee Current Drain
0.45
Volts
IOl = 1.6 rnA
2.4
Vee
Volts
IOH=-l50/.LA for AB,
DB and AEN
IOH =-80J.lA for other
3.3
Vee
Volts
IOH = -SO/.LA
120
rnA
III
Input Leakage
±10
/.LA
IOFl
Output Leakage During Float
±10
/.LA
CAPACITANCE
Symbol
(TA = 25°e;
Parameter
vee
= GND
Test Conditions
OV.,; VIN .,;Vee
0.45V .,; VOUT .,; Vee
= OV)
Min.
Max.
Unit
Test Conditions
CIN
Input Capacitance
10
pF
fc= lMHz
CliO
I/O Capacitance
20
pF
Unmeasured pins
returned to GND
2-117
Typ.
AFN-01B40D
825718257·5
A.C. CHARACTERISTICS-PERIPHER~L (SLAVE) MODE
=
=
=
(8257: TA O"C to 70"C, Vee 5.0V ±5%, GNO OV)
(8257-5: TA = O"C to 70"C, Vee = 5.0V ±10%, GNO = OV)
8080 "U8 paramete,.
READCYCLE·
8257·5
8257
Symbol
Min.
Parameter
Max.
Min.
Max.
Unit
TAR
Adr or CS~ Setup to RO~
TRA
Adr or
TRO
Data Access from
0
300
0
220
ns
TOF
DB-+Float Delay from ROt
20
150
20
120
ns
TRR
RD Width
250
cst Hold from ROt
Rfi ~
0
0
ns
0
0
ns,
Test Conditions
ns
250
WRITE CYCLE
8257·5
8257
Symbol
Parameter
TAW
Adr setup to WR~
TWA
Adr Hold from WRt
Tow
Data Setup to WR t
Two
Data Hold from
Tww
WR WIdth
Min.
Max.
Max.
Unit
20
ns
0
0
ns
200
200
ns
10
10
ns
200
200
ns
20
WiH
Min.
Test Conditions
OTHER TIMING
8257·5
8257
Symbol
TRSTW
Parameter
Min.
Reset Pulse W,dth
300
500
TRSTO
Power Supplyt (Vee) Setup to Reset~
T,
Signal Rise T,me
Tf
Signal Fall Time
TRSTS
Reset to FIrst IIOWR
Max.
Min.
Max.
300
IlS
ns
20
20
ns
20
2
Test Conditions
ns
500
20
Unit
2
tev
A.C. CHARACTERISTICS-DMA (MASTER) MODE
(8257: TA '= O·C to 70·C, Vee = 5.0V ±5%, GNO = OV)
(8257-5: TA = O·C to 70"C, Vec = 5.0V ±10%, GNO = OV)
TIMING REQUIREMENTS
,
Sym~1
8257
Parameter
Min.
8257·5
Max.
Min.
Mex.
TCY
Cycle Time (Period)
0.320
4
0.320
4
T,
Clock Active (High)
120
.8Tcy
80
.8TCY
Tos
ORQI Setup to ClKI (SI, S4)
120
TOH
ORQI Hold from HlOAII1]
T HS
TRs
TRH
-
120
0
0
HlOAI or ISetup to ClKI(SI, 84)
100
100
READY Setup Time to ClKI(S3, Sw)
30
30
READY Hold Time from ClKI(S3, Sw)
30
30
2-118
Unit
,.s
ns
nsns
ns
ns
ns
AFN·Ol840D
inter
825718257·5
A.C. CHARACTERISTICS-DMA (MASTER) MODE
(8257: TA = O°C to 70°C, VCC = 5.0V ±5%, GND = OV)
(8257·5: TA = O°C to 70·C, VCC = 5.0V ±10%, GND = OV)
TIMING RESPONSES
Symbol
8257
Parameter
Min.
8257·5
Max.
Min.
Unit
Max.
Too
HRQt or !Delay from CLKt (51,54)
(measured at 2.0V)
160
160
ns
T001
HRot or !Delay from CLKt (51, 54)
(measured at 3.3V)[3)
250
250
ns
TAEl
AENt Delay from CLK! (51)
300
300
ns
TAET
AEN! Delay from CLKt (51)
200
200
ns
TAEA
Adr (AB) (Active) Delay from AENt (51)[1)
TFAAB
Adr (AB) (Active) Delay from CLKt (51)[2)
250
250
ns
TAFAB
Adr (AB) (Float) Delay from CLKt (51)[2)
150
150
ns
TASM
Adr (AB) (5table) Delay from ClKt (51)[2)
250
250
ns
TAH
Adr (AB) (5table) Hold from CLKt (51
TASM-50
TASM-50
ns
TAHR
Adr (AB) (Valid) Hold from ROt (51, 51)[1)
60
60
ns
TAHW
Adr (AB) (Valid) Hold from wrt (51,51)[1)
300
300
TFAOB
Adr (DB) (Active) Delay from ClKt (51)[2)
TAFOB
Adr (DB) (Float) Delay from CLKt (52)[2)
TASS
Adr (DB) 5etup to Adr $tb! (51-52)[1)
100
100
TAHS
Adr (DB) (Valid) Hold from Adr 5tb! (52)[1)
20
20
TSTl
Adr 5tbt Delay from CLKt (51)
200
TSTT
Adr 5tb! Delay from ClKt (52)
140
Tsw
Adr 5tb Width (51-52)[1)
TASC
Rd! orWr(Ext)! Delay from Adr 5tb!
(52)[1)
20
P)
20
300
TSTT+20
250
TSTT+20
ns
ns
300
ns
170
ns
ns
ns
200
140
ns
ns
TCy-100
TCy-100
ns
70
70
ns
20
20
ns
,
TOBe
RO! orWR\Ext H Delay from Adr (DB)
(Float) (52) 1)
TAK
DACKt or! Delay from ClK! (52, 51) and
TC/Markt Delay from CLKt (53) and
'FC/Mark! Delay from CLKt (54)[4)
250
250
ns
TOCl
RD! orWr(Ext)~ Delay from ClKt (52) and
Wr! Delay from CLKt (53)[2,5)
200
200
ns
TOCT
Rdt Delay from CLK! (51, 51) and
wrt Delay fromClKt (~)[2,6)
200
200
ns
TFAC
Rd orWr (Active) from eLKt (51)[2)
300
300
ns
TAFC
Rd orWr (Active) from ClKt (51)[2)
150
150
ns
TRWM
Rd Width (52-51 or 51)[1)
2TCy+TO-50
2TCy+TO-50
ns
TWWM
WrWidth (53-54)[1)
TCy-50
TCy-50
ns
TWWME
WR(Ext) Width (52-54)[1)
2TCy-50
2TCy-50
ns
I
NOTES:
1. Tracking Parameter.
2. load
= + 50 pF. ,
3. load = VOH = 3.3V.
4:, aTAK < 50 ns,
2-119
5, aTOCl < 50 ns.
6. aToeT < 50 ns,
AFN,01640D
inter
8259A/8259A·2/8259A·8
PROGRAMMABLE INTERRUPT CONTROLLER
• IAPX 86, IAPX 88 Compatible
• Individual Request Mask Capability
• MCS-80®, MCS-85® Compatible
• Single
• Eight·Level Priority Controller
• 28·Pin Dual·ln·Line Package .
• Expandable to 64 Levels
• Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range
• Programmable Interrupt Modes
+ 5V Supply (No Clocks)
The Intel"' 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU. It is
cascadable for up to 64 vectored priority Interrupts without additional circuitry. It is packaged in a 28-pin DIP, uses
NMOS technology and requires a single + 5V supply. Circuitry is static, requiring no clock input.
The 8259A is designed to minimize the software and realtime overhead in handling multi-level priority interruptI!. It has
several modes, permitting optimization for a variety of sYl!tem requirements.
The 8259A is fully upward compatible with the Inlel'" 8259. Software originally written for the 8259 will operate the
8259A in all 8259 equivalent modes (MCS-80/85, Non-Buffered, Edge Triggered).
°,-0 0
DATA
CONTROllQGIC
BUS
BUFFER
CS
WR
iii5
IRO
IR'
IR2
iffi
ViR
IR.
cs
CASO
CAS 1
Vee
...iN'fA
0,
IR7
D.
IR6
0.
IRS
D.
IR4
OJ
IR3
O2
IR2
0,
IRI
Do
IRO
CAS 0
INT
CAS 1
~/EN
GND
CAS2
CAS2
$PIEri
~INTERNAl
BUS
Figure 2. Pin Configuration .
Figure 1. Block Diagram
Intel Corporation Assumes No Responaibllty for the Use of Any Circuitry Other Than C,rcultrv Embodied tn an Intel Product No Other Circuit Patent' License. a,. Implied,
©INTEL CORPORATION, 1980
2-120
AFN-00221C
8259A/8259A·218259A·8
Table 1. Pin Description
Pin No.
Type
Vee
Symbol
28
I
GND
14
I
Ground.
es
1
I
·Chlp Select: A low on this pin enables RD and WR communication between the CPU and the'8259A.
INTA functions are independent of CS.
WR
2
I
Write: A low on this pin when CS is low enables the 8259A to accept command words from the CPU.
RD
3
I
Read: A low on this pin when CS is low enables the 8259A to release status onto the data bus for the
CPU.
4-11
o,.-Do
Neme and FuncUon
Supply: +5V Supply.
I/O
Bidirectional Data Bus: Control, status and interrupt-vector Information is'transferred via this bus.
CASo-CAS2 12,13,15
I/O
Ca.cade Une.: The CAS lines form a private 8259A bus to control a multiple 8259A structure. These
pins are outputs for a master 8259A and inputs for a slave 8259A.
SP/EN
16
I/O
Slave ProgramlEnable Buffer: This is a dual function pin. When in the Buffered Mode it can be used
as an output to control buffer transceivers (EN). When not in the buffered mode it is used as an input
to deSignate a master (SP = 1) or slave (SP = 0).
INT
17
0
Interrupt: This pin goes high whenever a valid interrupt request is asserted. It Is used to interruptthe
CPU, thus it is connected to the CPUls interrupt pin.
18-25
I
Interrupt Request.: Asynchronous inputs. An interrupt request is executed by raising an IR input
(low to high), and holding it high until it is acknowledged (Edge Triggered Mode), or just by a high
level on an IR input (Level Triggered Mode).
INTA
26
I
Interrupt Acknowledge: This pin is used to enable 8259A interrupt-vector data onto the data bus by
a sequence of interrupt acknowledge pulses issued by the CPU.
Ao
27
I
AO Addre •• Une: This pin acts in conjunction with the CS, WR, and RD pins. It is used by the 8259A
to decipher various Command Words the CPU writes and status the CPU wishes to read. It is typically
connected to the CPU AO address line (AI for iAPX 86, 88).
IRc-IR7
2-121
AFN·00221E
.,
inter
\
8259AJ8259A-2/8259A-8
match his system requirements. The priority modes can
be changed or reconfigured dynamicall·y at any time during the main program. This means that the complete
interrupt structure can be defined as required, basecl on
the total system environment.
FUNCTIONAL DESCRIPTION
Interrupts in Microcomputer Systems
Microcomputer system design requires that 1/0 devices
such as keyboards, displays, sensors and other components receive servicing In an efficient manner so that
large amounts of the total system tasks can be assumed
by the microcomputer with little or no effect on throughput.
CPU·DRIVEN
MULTIPLEXOR
CPU
The most common method of servicing such devices Is
the Polled approach. This Is where the processor must
test each device in sequence and In effect "ask" each
one if it needs servicing. It is easy to See that a large portion of the main program is looping through this con·
tinuous polling cycle and that such a method wouid
have. a serious, detrimental effect on system throughput, thus limiting the tasks that could be assumed by
the microcomputer and reducing the cost eff.ectlveness
of using such devices.
----
--)~
, MCS-85
. This sequence Is timed by three INTA pulses. During the
first iiiifApulse the CALL opcode is enabled onto the
data bus.
Content of First Interrupt
Vector Byte
07
os
D8
CALLCODEI,
D4
03
02
01
00
Content of Interrupt Vector Byte
for IAPX 86 System Mode
DO
,I
During the second iliITA pulse the lower address of the
appropriate service routine is enabled onto the data bus.
When Interval = 4 bits As-A7 are programmed, while AoA~ are automatically inserted by the 8259A. When Interval = 8 only A6 and A7 are programmed, while Ao-As are
automatically Inserted.
Content of Second Interrupt
Vector Byte
06
05
04
03
02
01
T7
T6
T~
T4
T3
I
I
1
IR6
T7
T6
T5
T4
T3
1
1
0
00
IR5
T7
T6
T5
T4
T3
1
0
1
IR4
T7
T6
T5
T4
T3
1
0
0
IR3
T7
T6
T5
T4
T3
0
I
1
IR2
T7
T6
T5
T4
T3
0
I
0
IRI
T7
T6
T5
T4
T3
0
0
I
IRO
T7
T6
T5
T4
T3
0
0
0
Inl.",.1-4
IR
7
07
IR7
07
D8
05
A7
A6
AS
,
D4
03
02
01
DO
PROGRAMMING THE 8259A
1
1
0
0
0
The 8259A accepts two types of command words gener·
ated by the CPU:
6
A7
A6
AS
1
1
0
S
A7
.A6
AS
1
1
0
0
4
A7
A6
A5
1
0
0
0
0
0
3
2
A7
A6
A5
0
1
1
0
0
A7
A6
AS
0
A7
A6
AS
0
0
1
1
1
A7
A6
A5
0
0
0
0
0
0
0
0
0
0
07
06
05
04
03
02
01
DO
7
A7
A6
1
1
1
0
0
0
6
A7
A6
1
1
0
0
0
5
A7
A6
1
0
1
0
0
0
0
2. Operation Command Words (OCWs): These are the
command words which command the 8259A to operate in various interrupt modes. These modes are:
a. Fully nested mode
b. Aotating priority mode
c. Special mask mode
d. Polled mode
4
A7
A6
1
0
0
0
0
3
A7
A6
0
1
1
0
0
0
0
The OCWs can be written into the 8259A anytime after
initialization.
2
A7
A6
0
1
0
0
0
0
1
A7
A6
0
0
1
0
0
0
0
A7
A6
0
0
0
0
0
0
0
1. Initialization Command Words (lCWs): Before normal
operation can begin, each 8259A in the system must
be brought to a starting point - by a sequence of 2 to
4 bytes timed by WR pulses.
0
Interval='
IR
INITIALIZATION COMMAND WORDS
(ICWS)
GENERAL
During the third INTA pulse the higher address of the
appropriate service routine, which was programmed as
byte 2 of the initialization sequence (As - A, s), is
enabled onto the bus.
Whenever Ii command is issued with AO= 0 and 04= 1,
this is.interpreted as Initialization Command Word 1
(ICW1). ICW1 starts the initialization sequence during
~hich the following automatically occur.
Content of Third Interrupt
Vector Byte
07
D8
05
D4
03
02
01
DO
A15
A14
A13
A12
All
Al0
,0.9
A8
iAPX 86, iAPX 88
iAPX 86 mode is similar to MC5-80 mode except that only
two Interrupt Acknowledge cycles are issued by the processor and no CALL opcode is sent to the processor. The
first interrupt acknowledge cycle is similar to that of
MCS-80, 85 systems in that the 8259A uses it to internal!y
freeze the state of the interrupts for priority resolution and
all a master it issues the interrupt code on the cascade
lines at the end of the INTA pulse. On this first cycle it does
a. The edge sense circuit is reset, which means that 101lowing initialization, an interrupt request (IA) input
must make a low-to-high transition to generate an
interrupt.
b. The Interrupt Mask Aegister is cleared.
c. IR7 input is assigned priority 7.
d. The slave mode address is set to 7.
e. Special Mask Mode is cleared and Status Read is set to
IAA.
f. If IC4=O, then all functions selected in ICW4 are set to
zero. (Non-Buffered mode', no Auto-EOI, MCS-80, 85
system).
-Note: MasterlSlave
2-125
In
leW4 is only used In the buffered mode
AFN-00221E
inter
825,9A/8259A~218259A·8
INITIALIZATION COMMAND WORD 3 (ICW3)
INITIALIZATION COMMAND WORDS 1 AND 2
(ICW1, ICW2)
A$-A 1s: Page starting address of servIce routinas. In an
MCS 80185 system, the 8 request levels will generate
CALLs to 8 locations equally spaced ,in memory. These
can' be programmed to be spaced at Intervals of 4 or 8
memory locations, thus the 8 routines will occupy a
page of 32 or 64 bytes, respectively.
The address formal Is 2 bytes long (A o-A l s). When the
routine interval is 4, Ao-A. are automatically inserted by
the 8259A, while As-A1S are programmed externally.
When the routine Interval Is 8, Ao-As are automatically
inserted, by the 8259A, while Aa-Als are programmed
externally.
The 8·byte interval will maintain compatibility with cur·
rent software, while the 4·byte Interval is best for a com·
pact jump table.
In an iAPX86 system A1S-Al1 are inserted in the five most
significant bits of the vectoring byte and the 8259A sets
the three least significant bits according to the interrupt
level. A10-As are ignored and ADI (Address interval) has
no effeyt.
LTIM:
If LTIM=1, then the 8259A will operate In the
level Interrupt mode. Edge detect logic on the
Interrupt Inputs will be disabled.
ADI:,
CALL address Interval. ADI = 1 then interval = 4;
ADI = 0 then interval = 8.
SNGL: Single. Means that this is the only 8259A in the
system. If SNGL= 1 no ICW3 will be Issued.
IC4:
If this bit is set - ICW4 has to be read. If ICW4
,Is not needed, set IC4 = O.
, This word is'read only when there is more 'than one
8259A in the system and cascading is used, in which
case SNGL = O. It will load the 8·bit slave register. The
functions of this register are:
a. In the master mode (either when SP = 1, or in buffered
mode when MIS = 1 In ICW4) a "1" Is set for each
slave in the system, The master then will release byte
1 of the cali sequence (for MeS·80/85 system) and
will enable the corresponding slave to release bytes 2
and 3 (for iAPX 86 only byte 2) through the cascade
'
lines.
b.ln the slave mode (either when ms=O, or if BUF= 1
and MIS = 0 in ICW4) bits 2-0 Identify the slave. The
slave compares its cascade Input with these bits and,
if they are equal, bytes 2 and 3 of the call sequence (or
just byte 2 for iAPX 86 are released by it on the Data
Bus.
. INITIALIZATION COMMAND WORD 4 (ICW4)
SFNM: If SFNM = 1 the special fully nested mode Is
programmed.
BUF: if BUF = 1 the b"uffered mode is programmed. In
buffered mode SJ5/EN becomes an enable output '
and the masterlslave determination is by MIS,
MIS: If buffered mode Is selected: MIS = 1 means the
8259A Is programmed to be a master, MIS = 0
means the 8259A Is programmed to be a slave, If
BUF = 0, MIS has no function.
AEOI: If AEOI = 1 the automatic end of Interrupt mode
Is programmed.
,.PM: Microprocessor mode: !-,PM = 0 sets the 8259A for
MeS-80, 85 system operation, !-,PM = 1 sets the
8259A for iAPX 86 system operation.
NO (SINGl = 1)
NO (IC4 '" 0
Figure 6. Initialization Sequence
2-126
AFN-00221E
inter
8259AJ8259A·~8259A·8
ICW'
1 ICW" NEEDED
0: NO ICW", MU.0I0
1 = SINGLE
o = CASCADE MODE
CALL "CORfSS INTERVAL
1- INTERVAL Of"
a_INTERVAL Of.
1 = LEVEL TRIGGERED MODE
o '" EDGE TRiGGERED MODE
ICW3 CMASTER DEVICtt
'-----'--L_-'-_-'-_.L...._L-----'~
_ _I
1
~
IA 'NPUT HAS A SLAVE
0 - 1ft II"WUT DOES NOT HAVE
A SLAVE
ICWllSLAVE DEVICEI
••
7
,
,
0
1 0
a
1
1
o
1
1
1
1
1 := 8086/8088 MODE
0= MCS-80f85 MODE
1
AUTO EOI
o ~ NORMAl EOI
)(
EfHj
NON BUFfERED MODE
.,
0
- BUfFERED MOOElSlAVE
1
1
- BUfFERED MODEIMASTER
1
=~ ~~~ IS
EQUAL
19 THE CORRESPONDING
'---------01
&"
0=
SPEQAL FULLY NESTED
~g~SPECIAL FULLY
NESTED MODE
Figure 7. Initialization Command Word Format
2-127
AFN·00221E
S259A18259A-2/8259A-8
OPERATION COMMAND WORDS (OCWs)
OPERATION CONTROL WORD 1 (OCW1)
After the Initialization Command Words (ICWs) are programmed into the 8259A, the chip Is ready to accept
Interrupt requests at its input lines. However, during the
8259A operation, a selection of algorithms can command the 8259Ato operate in various modes through
the Operation Command Words (OCWs).
OCW1 sets and clears the mask bits In the interrupt "
Mask Register (IMRI. M7 - Ma represent the eight mask
bits. M", 1 indicates the channel is masked
(inhibited), M '" 0 indicates the channel is enabled.
OPERATION CONTROL WORD 2 (OCW2)
R, SL, EOI - These three bits control the Rotate and
End of Interrupt modes and combinations of the two. A
chart of these combinations can be found on the Operation Command Word Format.
OPERATION CONTROL WORDS (OCWs)
AO
[Q
07
I M7
De
OCWI
05
04
03
02
01
DO
Me
M5
M3
M2
M,
MO
M4
I
L2 , L" Lo-These bits determine the interrupt level acted
upon when the SL bit is active.
OPERATION CONTROL WORD 3 (q<:W3)
0
I
OCW2
A
SL
EOI
0
0
L2
Ll
LO
I
ESMM - Enable Special Mask Mode. When this bit is
set to 1 it enables the SMM bit to set or reset the Special
Mask Mode. When ESMM 0 the SMM bit becomes a
"don't care".
=
=
OCW3
0
a
ESMM SMM
0
P
AA
AIS
I
SMM - Special Mask Mode. If ESMM = 1 and SMM 1
the 8259A wili enter Special Mask Mode. If ESMM = 1
and SMM = 0 the 8259A will revert to normal mask mode.
When ESMM = 0, SMM has no effect.
2-128
AFN·OO221E
inter
8259A18259A-2/8259A-8
'oew,
~
~
~
~
~
~
~
~.
~
Dew,
~
01
0
R
I
I
06
Os
O.
8L
I EOI I
0
0,
03
i
I
0
Do
0,
L, I L, I L,I
IRLEVEL TOlE
AC'IED"",,"
I
0
1
0
1
0
0
0
0
,,•••
7
1
0
1
0
1
1
1
0
0
1
0
0
1
1
1
,
0
1
r
l
rtO+
Or,- 1
1~
1
r-;
NON-8PECIFIC EOICOMMAHD
SPECIFtC Eot COMMAND
1
0
ROUTE ON NO.....CtFIC EOI COMMANO
N)TI(f'£
IN AU'rOMATIC EOI MODE (8El)
oror,-
0
ROTATE IN AUTOMATIC ECIt MODE (CLEAR)
1
'ROTATE ON SHelFIC EOI COMMAND
1
0
1
hotto
"U'T PRIORITY COMMAND
N00P1!I1AT1ON
l
END OF INTERRUPT
}
AiJToMATICROTAnoN
l
SPEctFIC ROTAT-ION
"l.O-U:AR£U8ED
Dew'
A~
I
0
D,
I
0
Db
Os
IESMMISMM I
D.
0
03
I
1
02
I
p
0,
I
OR
Do
I RIS
I
IL
READ REGtSTI!R COMMAND
0
0
I
I
1
0
0
1
1
READ
READ
IR REG
ON NEXT
ISReG
ON NEXT
RD PULSE
RDPULSE
NO ACTION
1
1...POLL COMMAND
8=NO POLL COMMAND
SPECIAL MASK MODE
0
0
I
I
1
0
1
0
1
1
RESET
SPECIAL
MAS«
SET
SPECIAL
MASK
NO ACTION
F:igure 8. Operation Command Word Format
2-129
AFN·OO221E
I
"
8259A/8259A-2/8259A-8
AUTOMATIC ROTATION
FULLY NESTED MODE
This mode is entered after initialization unless another
mode is programmed. The interrupt requests are
ordered in priority form 0 through 7 (0 highest). When an
Interrupt is acknowledged the highest priority request is
determined and its vector placed on the bus. Additionally, a bit of the Interrupt Service register (ISO-7) is set.
This bit remains set until the microprocessor issues an
End of Interrupt (EOI) command immediately before
returning from the service routine, or if AEOI (Automatic
End of Interrupt) bit is set, until the trailing edge of the
last INTA. While the IS bit is set, all further interrupts of
the same or lower priority are inhibited, while higher
levels will generate an interrupt (which will be
acknowledged only if the microprocessor internal Interrupt enable flip-flop has been re-enabled through software).
(Equal Priority Devices)
In some applications there are a number of interrupting
devices of equal priority. In this mode a device, after
being serviced, receives the lowest priority, so a device
requesting an interrupt will have to walt, in the worst
case until each of 7 other devices are serviced at most
once. For example, if the priority and "in service" status
is:
B.for. Rotat. (IR4 the highest priority requiring service)
157 lSI ISS 154 IS3 152 lSI
"IS" Slatus
101
1
L_••tPrlority
PriOrity Status
After the Initialization sequence, IRO has the higneSt
priority and IR7 the lowest. Priorities can be changed, as
~i11 be explained, in the rotating priority mode.
7
f
6
ISO
101,1 0 10101 0 1
15
Hlllh••'\.rlority
4 1 3 1 2 I 11'0 I
Aft.r Rotat. (IR4 was serviced, all other priorities
rotated correspondingly)
END OF INTERRUPT (EOI)
The In Service (IS) bit can be reset either automatically
following the trailing edge of the last in sequence INTA
pulse (when /-EOI bit in ICW1 is set) or by a command
word that must be issued to the 8259A before returning ,
from a service routine (EOI command). An EOI command
must be issued twice if in the Cascade mode, once for the
master and once for the corresponding slave.
There are two forms of EOI command: Specific and NonSpecific. When the 8259A is operated in modes which
preserve the fully nested structure, it can determine
which IS bit to reset on EOI. When a Non-Specific EOI
command is issued the 8259A will automatically reset
the highest IS bit of those that are set, since in the
fully nested mOQe the highest IS level was necessarily the
last level acknowledged and serviced. A non-specific EOI
can be issued with OCW2 (EOI = 1, SL = 0, R = 0).
IS7
"IS" Stalus
lSI 155 154 IS3
IS2 151
ISO
1 0 1' 1010101010101
'Priority Status
There are two ways to accomplish Automatic Rotation
using OCW2, the Rotation on Non-Specific EOI Command
(R = 1, SL = 0, EOI = 1) and the Rotate in Automatic EOI
Mode which is set by (R = 1, SL = 0, EOI = 0) and cleared
by (R = 0, SL = 0, EOI = 0).
SPE:CIFIC ROTATION
(Specific Priority)
When a mode is used which may disturb the fully nested
structure, the 8259A may no longer be able to determine
the last level acknowledged. In this case a Specific End of
Interrupt must be issued which includes as part of the
command the IS level to be reset. A specific EOI can be issued with OCW2 (EOI = 1, SL = 1, R = 0, and LO-L2 is the
binary level of the IS bit to be reset).
.
The programmer can change priorities by programming
the bottom priority and thus fixing all other priorities;
i.e., if IR5 is programmed as the bottom priority device,
then IR,6 will have the highest one.
It should be noted that an IS bit that is masked by an
IMR bit will not be cleared by a non-specific EOI if the
8259A is in the Special Mask Mode.
Observe that in this mode internal status is updated by
software control during OCW2. However, it is independent
of the End of Interrupt (EOI) command (also executed by
OCW2). Priority changes can be executed during an EOI
command by using the Rotate on Specific EOI command
in OCW2 (R = 1, SL = 1, EOI = 1 and LO-L2 = IR level to
receive bottom priority).
AUTOMATIC END OF INTERRUPT (AEOI) MODE
If AEOI = 1 in ICW4, then the 8259A will operate in AEOI
mode continuously until reprogrammed by ICW4. In this
mode the 8259A will automatically perform a nonspecific EOI operation at the trailing edge of the last
interrupt acknowledge pulse (third pulse in MeS-80/85,
second in iAPX 86). Note that from a system-standpoint,
this mode should be used only when a nested multilevel
intern,lpt structure'is not required within a single 8259A.
The AEOI mode can only be used in a master 8259A and
not a slave.
2-1qO
The Set Priority command is issued in OCW2 where:
R = 1, SL = 1; LO-L2 is the binary priority level code of the
bottom priority device.
INTERRUPT MASKS
Each Interrupt Request Input can be masked Individually by the Interrupt Mask Register (IMR) programmed
through OCW1. Each bit in the IMR masks one Interrupt
channel if It is set (1). Bit 0 masks IRO, Bit 1 masks IR1
and so. forth. Masking an IR channel does not affect the
other channels <>peration.
AFN·00221E
intJ
8259A18259A-218259A-8
SPECIAL MASK MODE
POLL COMMAND
Some applications may require an interrupt service
routine to dynamically alter the system priority struc·
ture during Its execution under software control. For
example. the routine may wish to Inhibit lower priority
requests for a portion of its execution but enable some
of them for another portion. .
In this mode the INT output i,s not used or the microprocessor internal Interrupt Enable fllp·flop Is reset. disabling
its interrupt input. Service to devices is achieved by
software using a Poll command.
The Poll command Is Issued by setting P = "1" In OCW3.
The 8259A treats -the next FItS pulse to th~ 8259A (i.e.,
I!m = 0, e§ = 0) as an Interrupt acknowledge, sets the
appropriate IS bit If there Is a request, and reads the
to 1m.
priority level. Interrupt Is frozen from
The difficulty here is that If an Interrupt Request is
acknowledged and an End of Interrupt command did not
reset its IS bit (i.e.• while executing a service routine).
the 8259A would have inhibited all lower priority
requests with no easy way for the routine to enablethem
That is where the Special Mask Mode comes In. In the
special Mask Mode. when a mask bit is setjn OCW1. it
Inhibits further Interrupts at that level and enables Inter·
rupts from all other levels
2.0
TEST POINTS
0.8
0.45
<
20
0.8
=
=
= 100 pF
CCASC~DE = 100 pF
C'NT
A.C. TESTING LOAD CIRCUIT
x=
DEVICE
iJCL~100PF
UNDER
TEST
-=
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1 ANO 0 45V FOR
A LOGIC 0 TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC 1
AND 0 8V FOR A LOGIC 0'
Cl =100pF
C l INCLUDES JIG CAPACITANCE
WAVEFORMS
WRITE
TWLWH
\
lUI
).
T"HWL
-
I
-
-
(
-TDYWH-
OAT" lUI
TWHAX
)
!--TWHDX
r-
AFN·OO221E
8259A1B259A-2/B259A-B .
WAVEFORMS (Continued)
READ/INTA
TIILIIH
j
\
~
AODRE.. lUI
At
\
>-- TIILEL
-
-
I--TAHIIL
}
-
{TIIHEH
_TRHAX
(
. , "'--------- -------~---------....r-----T"LOV
"---TAHOV
T"HOZ
~
OTHER TIMING
III!
IJiIfA
WR
III!
INTA
WI!
AD
WR
iIDl\
\
Jf=TRHRL=t
\
~TWHWL=1\
/
/
\
C-=1
/
2-136
AFN·00221E
inter
8259A/8259A-2/8259A-8 .
WAVEFORMS (Continued)
INTA SEQUENCE
IA
INT------J
~A--------_~
-- 0--
08 _ _ _ _ _ _ _ _ _ _ _ _ _
_TCVIAl
TCYOY
c02----------------r----~Lf------~---_L_L
___________
~_
-TlAlCV~
NOTES: Interrupt output must remai~ HIGH at least until leading edge of first INTA.
1. Cycle 1 in iAPX 86, iAPX SS systems, the Data Bus is not active.
2-137
AFN·OO221E
inter
.,,'
8355/8355~2
'i
16,384-8IT ROM WITH 1/0
• Each I/O Port Line Individually
Programmable as Input or Output
• 2048 Words )( 8 Bits
• Single + SV Power Supply
• Multiplexed Address and Data Bus
• Directly Compatible with 808SA
and IAPX 88 Microprocessors'
• Internal Address Latch
.2 General Purpose 8·Blt,1I0 Ports
• 40.Pln DIP
The Intele 8355 is a ROM and 1/0 chip to be used in the 8OS5A and iAPX 88 microprocessor systems. The ROM portion is
organized as 2048 words by 8 bits. It has a maximum access time of 450 ns to permit use with no wait states in the 8OS5A
CPU.
The I/O portion consists of 2 general purpose I/O ports. Each I/O port has 8 lines and each 1/0 port line is individually pro·
grammable as input or output. '
'
The 8355-2 has a 300 ns access time for compatibility with the 8085A-2 and 5 MHz iAPX 88 microprocessors.
Vee
PB,
eLK
PBs
RESET
READY
N C (NOT CONNECTED)'
ADO-7
~,o
CE,
CE1
101M
ALE
AD
iliW
RESET
PB.
PB,
PB.
G
ROM
PBs,
G
G
PB,
PAn-,
lOW
P"
ALE
PBO- 7
ADo
AD,
PA,
iliA
PAo
AD.
CO AD7
Vee (+5V)
A,o
A.
' - - - - V.. IOV)
-For 8755A compatibility, pl,n 5 should be directly tied to
Figure 1.' Block Diagram
Vee.
Figure 2•.Pln Configuration,
\ 2-138
AFN.()0234D -
inter
8355/8355-2
Table 1. Pin Description
Type
Name and Function
ALE
I
ADO-7
I
Addre.s latch Enable: When high, ADo_7, 101M, As-10, CE2, and CEl enter the address latches. The signals
'
(AD, 110M, As-10, CE2, CEll are latched in at the trailing edge of ALE.
Addre.S/Data Bu. (Bidirectional): The lower 8-bits of the ROM or I/O address are applied to the bus lines when
ALE is high. During an I/O cycle, Port A or B is selected based on the latched value of ADo. If RD or lOA is low when
the latched chip enables are active, the output buffers present data on the bus.
Symbol
I
As-l0
eel
CE2
I
Address Bus: High order bits of the ROM address. They do not affect 1/0 operations.
Chip Eneble Inputs: CEl Is active low and CE2 Is active high. The 8355 can be accessed only when BOTH Chip
Enables are active at the time the ALE signal latches them up. If either Chip Enable Input is not active, the
ADo-7 and READY outputs will be in a high imPl'dance state.
Ri5 is low, the output data comes from an I/O port. If it is low, the out-
101M
I
1/0 Memory: If the latched 101M is high when
put data comes from the ROM,
RD
I
Read: If the latched Chip Enables are active when RD goes low, the ADo-7 output buffers are enabled and output
either the selected ROM location or I/O port. When both RD and lOR are high, the ADO-7 output buffers are 3-stated.
lOW
I
1/0 Write: If the latched Chip Enables are active, a low on lOW causes the output port pointed to by the latched
value of ADo to be written with the data on ADo-7. The state of 101M is ignored.
ClK
I
Clock: Used to force the READY into its high impedance state after it has been forced low by eel low, CE2high
and ALE high.
'
READY
0
R'EADY: A 3-state output controlled by CEl, CE2, ALE and ClK. READY is forced low when the Chip Enables are
active during the time ALE is high, and remains low until the rising edge of the next ClK.
PAo-7
I/O
Port A: General purpose I/O pins. Their inputloutput direction is determined by the contents of Data Direction
Register (DDR). Port A is selected for write operations when the Chip Enables are active and lOW is low and a
was previously latched from ADo, AD 1.
o
Read operation Is selected by either lOR low and active Chip Enables and ADo and AD1 low, or 101M high, RD
fow, ,active chip enables, and ADo and AD 1" lOW.
Port B: This general purpose I/O port Is identical to Port A except that it is selected by a 1 latched from ADo
and a 0 from AD 1 .
PBO-7
I/O.
RESET
I
Reset: An Input high causes all pins in Port A and B to assume input mode. (Clear DER Register).
lOR
I
I/O Read: When the Chip Enables are active, a low on lOR will outpulthe selected I/O port onto the AD bus. lOR low
performs the same function as the combination 101M high and RD low. When lOR is not used in a system, lOR
should be tied to Vee ("1").
'
Vee
Voltage: +5 volt supply.
Vss
Ground: Ground Reference.
2-139
AFN.(}()234D
8355/8355-2
FUNCTIONAL DESCRIPTION
8355
ONE BIT OF PORT A AND DDR A
ROM Section
The 8355 contains an 8·bit address latch which allows it
to interface directly to MCS·48, MCS·85, and iAPX 88/10
Microcompyters without additional hardware.
The ROM section of the chip Is addressed by an ll-bit
addrel!s and the Chip Enables. The address and levels on
the c:hip Enable pins are latched into the address latches
on the falling edge of ALE. If the latched Chip Enables
are active and 10/M is low when RD goes low, the contents
of the ROM location addressed by the latched address
are put out through ADo-7 output buffers.
DO
1/0 Section
The I/O section of the chip is addressed by the latched
value of ADo-1. Two 8-bit Data Direction Registers (oDR,I
in 8355 determine the input/output status of each pin in
the corresponding ports. A "0" In a particular !lIt po~itlon
of a DDR signifies that the corresponding 110 port bit is
in the input mode. A "1" in a particular bit position signifies that the corresponding 110 port bit IS in the output
mode: In this manner the 1/0 ports of the 8355 are bit-bybit programmable as inputs or outputs. The table summarizes port and DDR designation. DDR's cannot be
read.
AD1
ADD
Selection
0
0
1
0
1
0
1
Port A
Port B
Port A Data Direction Register (DDR AI
Port B Data Direction Register (DDR BI
1
When 10VY goes low and the Chip Enables are active, the
data on the ADo-7 is written Into 1/0 port selected by the
latched value of ADo-1 DUring this operation all 1/0 bits
of the selected port are affected, regardless of their 1/0
mode and the state of 10iM The actual output level does
not change until lOW returns high (glitch free output I.
~
READ PA
WRITE PA = (iOW=OJ. (CHIP ENABLES ACTIVE) • (PORT A ADDRESS SELECTED)
WRITE DOR A " (iOW=OJ. (CHIP ENABLES ACTIVE). (DDR A ADDRESS SElECTED)
READ PA = {[(I0tM"'11. (RD=O)] + (iOR=o)} • (CHIP ENABLES ACTIVE). (PORT A ADDRESS SELECTED)
NOTE WRITE PA IS NOT QUALIFIED BY 101M
Figure 3. 8355 One Bit of Port A and DDR A
SYSTEM APPLICATIONS
System Interface with 8085A and iAPX 88
A system using the 8355 can use either one of the two
1/0 Interface techniques .
• Standard 1/0
• Memory Mapped 1/0
If a standard I/O technique is used, the system can use
the feature of both CE2 and CE1, By using a combination of unused address lines A 11 - 15 and the Chip
Enable inputs, the system can use up to 5 each 8355's
without requiring a CE decoder, See Figure 5a and 5b.
if a memory mapped I/O approach is used the 8355 will
be selected by the combination of both the Chip Enables and 10iM using ADs_ 15 address lines, See Figure
4.
A port can be read out when the latched Chip Enables are
active and either RD goes low with 10iM high, or lOR
goes low. Both input and output mode bits of a selected
port will appear on lines ADo-7.
"-
A8~15
To clarify the function of the 1/0 ports and Data Dlrecllon
Registers, the following diagram shows the conflgural'on
of one bit of PORT A and DDR A. The same logic applies
to PORT Band DDR B
~
"
8085
Note that hardware RESET or writing a zero to the DDR
latch will cause the output latch's' output buffer to be
disabled, preventing the data In the output latch from
being passed through to the pin. ThiS IS equivalent to
putting the port in the input mode. Note also that the data
can be written to the Output Latch even though the Output Buffer has been disabled. ThiS enables a port to be
initialized with a value prior to enabling the output.
,~
""LE
RD
-
-
i'iI1
elK (02)
READY
101M
Vee
t
~
I
f",
AO O_7
fiR
The diagram also shows that the contents of PORT A and
PORT B can be read even when the ports are configured
as outputs.
>f~
AI _10
RD eLK • 101M
ALE iOW READY C.
8355
Figure 4. 8355 in 8085A System
(Memory-Mapped I/O)
2-140
AFN-00234D
inter
8355/8355-2
iAPX 88 FIVE CHIP SYSTEM:
•
•
•
•
•
1.25 K Bytes RAM
2 K Bytes ROM
38 I/O Pins
1 Internal Timer
2 Interrupt Levels
,A
v,s
Vee
I I
~
H--
POR!¢!(>
~~_WR
POR~
AD
¢!(>
(8)
8155-2
"
PORT~
C
(6)
ALE
DATAl
ADDR
IN_
101M TIMER
OUT
RESET
I--
Aa-A19
,-
ADo-AD7
ClK
lOW
ADDA
~
ADDR/DATA
I
,X,
READY
RST@
AD
ViR
r--
READY
101M
RES
8284A
t--
r- r-rrr. - - r-
A
AS• 10
8355-2
ADDR
101M
I
~
DATAl
PORT
..--- RESET
t--
REseT
ROYl
"
V
"
t--
PORT
CE
f---Vcc
ALE
X,
ClK
ALE
~j2:::
t=
8088
MN/MX
[OJ
AD
8 ¢!(>
READY
Vee
iDA .....J
III
LROG
Vss Vee Voo
Vee
WR
....
AD
'CD
eEl 8185-2
ALE
I
~t-
i H-
I \-t--
cs,
CE,
Ae,Ag
AD O• 7
1 1
V5S
Vee
Figure Sa. iAPX 88 Five Chip System Configuration
2-141
AFN-00234D
l
A8-15
An
80<15A
~- ALE
AD
WR
-
eLK (l/12)
-
READY
t~
Au
101M
A15
A14
A"
-
-
r-
r-
-
-
tt-
-
-
ttt-
-
-
t--
-
t--
-
-
t-
-
-
Q)
(0)
g:
"
Q)
(0)
~
~
I\)
i\
1m
lOR
Aro,_,
vee
A~1O
T
10/\ 11_ Affl~,
RD eLK
ALE iOW READY
8355
(2K BYTES)
eEl
lOR
A~1O
7'II i\ "A~"
RD eLK
101M
A~DW READY eE2
(2K BYTES)
Al°g...1
fiR
t\ " 7'II 'A~"
ROiliWCtKREADY
101MCE2
~
iOR
Affle-,
(2K BYTES)
'II
RO eLK
101M
~Ow READ.Y eE2
Vr
7-~
AIDg...l
iOii
(2KBYTES)
NOTE: Use CEl for the first 8355 in the system, aDd CEz for the other 8355's, Permits up to 5-8355's in a system without CE decoder.
Figure 5b. 8355 in 8085A System (Standard I/O)
1;;
z
~o
7
Aa..l0
RD eLK
ALE
mw
8355
(2KBYTES)
101M
READY
CE
8355/8355-2
ABSOLUTE MAXIMUM RATINGS·
'NOTICE: Stresses above those listed under "Absolute
Maximvm Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in'the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
TemperatureUnderBias ................ 0°Cto+70°C
Storage Temperature .... . . . . . . . . . .. -65°C to +150°C
Voltage on Any Pin
With Respect to Ground ............... -0.5V to +7V
Power Dissipation .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.5W
D.C. CHARACTERISTICS
(TA = o°c to 70°C; Vee = 5V ± 5%)
Min.
Max.
Unit
In put low Vo Itage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vee+O·5
V
Vee = 5.0V
VOL
Output low Voltage
0.45
V
IOL = 2mA
VOH
Output High Voltage
V
IoH = -400/lA
IlL
Input lea kage
ILO
Icc
Symbol
VIL
Parameter
2.4
Test Conditions
Vee = 5.0V
10
/lA
OV ,,; Y'N ,,; Vee
Output leakage Current
±10
JlA
0.45V ';;;VOUT .;;;vee
Vee Supply Current
180
mA
A.C. CHARACTERISTICS· (TA = o°c to 70°C; Vee = 5V ± 5%)
8355
Symbol
Parameter
Min.
8355-2
Max.
Min.
Max.
Units
tCYC
Clock Cycle Time
320
200
ns
T1
ClK Pulse Width
80
40
ns
T2
ClK Pulse Width
120
70
tf.t,
ClK Rise and Fall Time
tAL
Address to latch Set Up Time
50
30
ns
tLA
Address Hold Time after latch
80
45
ns
tLe
latch to READ/WRITE Control
100
40
tRO
Valid Data Out Delay from READ Control'
tAD
Address Stable to Data Out Valid"
tLL
latch Enable Width
tRoF
Data Bus Float after READ
30
170
450
100
0
100
0
READIWRITE Control to latch Enable
20
10
tee
READ/WRITE Control Width
250
200
tow
Data In to Write Set Up Time
150
150
30
two
Data In Hold Time After WRITE
WRITE to Port Output
tpR
Port Input Set Up Time
50
ns
ns
300
ns
85
ns
ns
ns
,
ns
ns
10
400
ns
140
70
teL
twp
ns
30
ns
300
50
ns
ns
tRP
Port Input Hold Time
50
tRYH
READY HOLD Time
0
tARY
ADDRESS (CE) to READY
tRY
Recovery Time Between Controls
300
200
ns
READ Control to Data Bus Enable
10
10
ns
tROE
50
160
0
160
ns
160
ns
160
ns
'Or TAo-('i'AL + TLc). whichever is greater.
"Defines ALE to Data out Valid in conjunction with TAL.
2-143
AFN-00234D
A.C. TESTING LOAD CIRCUIT
A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUT/OUTPUT
"=-X >
2.0
0.8
045
<
2.0
TEST POINTS
0.8
x=
DEVICE
UNDER
TEST
lCL~'50PF
-=-
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC '1" ANOO 45V FOR
A'LOGIC "0" TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC 1"
AND 0 BV FOR A LOGIC "0 "
CL =150pF
CL INCLUDES JIG CAPACITANCE
WAVEFORMS
ROM READ AND I/O READ AND WRITE
A S_10
101M
=>
=>
ADO_7
K
ADDRESS
,
tAD
)
ADDRESS
DATA
'CE 2 "'1)*
r!-
tLl
~ t--~
tLA
~
If
ALE
- tAL -
I- t RDF •
~tRDE~
l----tRD-~
1+----- t Le ~
~-
tDw
'I------i--
tRv
t WD _
I----tee
i.--tCL~
• Please note that for 8755A compatibility,
CE, should
remain low for the entire read cycle.
8355 CLOCK SPECIFICATIONS
2-144
AFN-00234D
intJ
8355/8355-2
WAVEFORMS (Continued)
INPUT MODE
d=~
ROOR
lOR
PORT:X
I,NPUT
DATA' BUS
-
-
-
-
-
-)<
-------
OUTPUT MODE
....._-------
_______1,
twp+- /
PORT
GLITCH FREE
OUTPUT
------------~
OUTPUT _ _ _ _ _ _ _ _ _ _ _ _
~
DATA'BUS
____ _
p..,.._____
.J'\______...JX"-___
'"
"DATA BUS TIMING IS SHOWN IN FIGURE 4.
WAIT STATE
•
NOTE: Ready
= O.
2-145
AFN.Q0234D
inter
8755A /8755A-2
16,384-8IT EPROM WITH I/O
• 2 General Purpose 8·Blt 110 Ports
• 2048 Words )( 8 Bits
• Single
• Each 110 Port Line Individually
. Programmable as Input or Output
+ 5V Power Supply (Vee)
• Directly Compatible with S08SA
and 8088 Microprocessors
iii Multiplexed Address and Data Bus
• 40·Pin DIP
• U.V. Erasable and. Electrically
Reprogrammable
• Available in EXPRESS
-. Standard Temperature Range
- Extended Temperature Range
• Internal Address Latch
The Intel@ 8755A is an erasable and electrically reprogrammable ROM (EPROM) and 1/0 chip to be used in the 8085A and
iAPX 88 microprocessor systems. The EPROM portion Is organized as 2048 words by 8 bits. It has a maximum access
time of 450 ns to permit l!se with ,no wait sta~es in an 8085A CPU.
The 1/0 portion consists of 2 general purpose 1/0 ports. Each 1/0 port has 8 port lines, and each 1/0 port line is individually
programmable as iriput or output.
The 8755A-2 is a high speed selected version of the 8755A compatible with the 5 MHz 8085A-2 and the 5 MHz iAPX 88
microprocessor.
PROG AND
ClK----..,
CE,
1
CE2
2
ClK
REAoV----!
A8-10~_o/
CE,---.j
IOiM---.J
2K x 8
EPROM
AlE---.j
fiij---.j
iOW---.j
G
G
PB,
PB.
lOW
ALE
P8o-,
,~-~/
PA,
RESET---,.J
AD3'
PA,
iOR----I
AD,
PA,
PA.
PAOG/CE,
VDD. - - - - '
A,.
Vee (+5V)
AD,
L---Vs~ IOVI
A,
Vss
Figure 2. Pin Configuration
Figure 1. Block Diagram
Intel Corporation Assumes No Responsibllty for the,U.8 of Any Circuitry Other Than Circuitry Embodied In an Intel Product No Other Circuit Patent Licenses afa Implied
© INTEL CORPORATION. 1980
2-146
inter
8755A18755A-2
Table 1. Pin Description
Type
Name and Function
ALE
I
Addre •• latch Enabla: When Addreee
latch Enable goes high, ADo-7, 101M,
As-l0, CE2; and CEl enier t~ addreee
latches. The signals (AD, lOlly! ADs-l0,
CE2, eel) are latched In at the trailing
,edge of ALE.
ADo-7
I
Bidirectional Addre ••/Data Bu.: The
lower 8-bits of the PROM or I/O address
are applied to the bus lines when ALE is
high.
Symbol
Symbol
~pa
READY
0
PAo-7
I/O
Port A: These are general purpose I/O
pins. Their input/output direction Is determined by the contents of Data Direction Register (DDR). Port A is selected for
write operations when the Chip Enables
are active and lOW is low and a 0 was
previously latched from ADo, AD1.
During an 1/0 cycle, Port A or B Is
selected based on the latched value of
ADo. IF RD or lOR is low when the latched
Chip Enables are active, the output buffers present data on the bus.
As-l0
I
Address Bus: These are the high order
bits of the PROM address. They do not
affect I/O operations.
PROG/CE,
CE2
I
Chip Enable Inputs: CEl is active low
and CE2 is actiVe high. The 8755A can be
accessed only when both Chip Enables
are active at the time the ALE signal
latches them up. If either Chip En!lble
input is not active, the ADo-7 and
READY outp!!.!!.will be in a high impedance state.CEl Is also used as a programming pin. (See section on
programming.)
101M
I
Read Operation is selected by either iOR
low and active C~ Enables and ADo
and AD11ow,or 101M high, RD low, active
Chip Enables, and ADo and ADl low.
PBO-7
I/O
Port B: This general purpose I/O port Is
identical to Port A except that it is
selected by a 1 latched from ADo and a 0
from AD 1,
RESET
I
Relet: In normal operation, an input
high on RESET causes all pins in Ports A
and B to assume input mode (clear DDR
register).
lOR
I
1/0 Read: When the Chip Enables are
active, a low on lOR will output the
selected I/O port onto the AD bus. R5A
low performs the same fUnction as the,
combination of 101M high and RD low,
When lOR is not used In a system, lOR
should be tied to Vee ("1").
1/0 Mamory: If the latched 101M is high
when RD is low, the output data comes
from an 1/0 port. If it Is low the output,
data comes from the PROM.
RD
lOW
I
I
Read: " the latched Chip Enables are
active when RD goes low, the ADO-7
output buffers are enabled and output
either the selected PROM location or I/O
port. When both RD and lOR are high,
the ADo-7, output buffers are a-stated.
1/0 Write: If the latched Chip Enables are
I
Vee'
Power: +5 volt supply.
Vss
Ground: Reference.
Voo
Power Supply: Voo is a programming
voltage, And mllit !2!! tillg m'tee '«hIl!l
the 8755A is being read.
For programming, a high voltage is
supplied with Voo = 25V, typical. (See
section on programming.)
active, a low on lOW ,causes the output
port pointed to by the latched value of
ADo to be writtell.wlth the data on ADo-7'
The state of 101M is ignored.
ClK
Name and Function
Ready Is a 3-state output controlled by
eel. CE2. ALE and ClK. READY Is forced low when the Chip Enables are active
during the time ALE Is high. and remains low until the riSing edge of the
next ClK. (See Figure 6c.)
Clock: The ClK Is used to force the
READY into its high impedan~ state
after it has been forced low by CEl low,
CE2 high, and ALE high.
2-147
AFN.()08430
'
87:55A18755,,-~
8755A
ONE BIT OF PORT A AND OOR A
FUNCTIONAL DESCRIPTION
PROM Section
The 8755A contains an 8-bit address latch which allows it
to interface directly to MCS-48, MCS-85 and iAPX 88(10
Microcomputers ~ithout additional hardware.
The PROM section of the chip is addressed by the 11·bit
address and the Chip Enables. The address, CE, and
CE2 are latohed into the address latches on the failing
ed~ of ALE. If the latched Chip Enables are active and
101M Is low when AD goes lOw, the cpntents of the
PROM .location addressed by the latched address are
put out on the ADO_71ines (provided that Voo is tied to
Vee·)
The I/O section of the chip is addressed by the latched
value of ADo-1. Two 8-bit Data Direction Registers (DDR)
in 8755A determine the input/outp!!t status of each pin
in the corresponding ports. A "0" in a particular bit position of a DbR signifies that the corresponding I/O port bit
is in the input mode. A "1" in a particular bit position signifies that the corresponding I/O port bit is in the output
mode. In this manner the I/O ports of the 8755A are bit-bYbit programmable as inputs or outputs. The table
summarizes port and DDR designation. DDR's cannot be
read.
Selection
ADo
0
1
0
1
CDR A
o.
---,
REAOPA
1/0 Section
AD1
0
0
1
1
WRIT~
Port
Port
Port
Port
A
B
A Data Direction Register (DDR A)
B Data Direction Register (DDR B)
When lOW goes low and the Chip Enables are active,
the data on the ADo_7 is written into I/O port selected
by the latched value o~ ADo_ 1. During this operation all
1/0 bits of the selected port are affected, regardless of
their I/O mode and the state of 101M. The actual output
level does not change until lOW returns high. (glitch free
output)
A port can be rea2.,2ut when the latch~ Chip Enables are
active and either RDgoes 10wwithJO/M high, or lOR goes
low. Both input and output mode bits of a selected port
will appear onlines ADo-?
WRITE PA" (row-O). (CHIP ENABLES ACTIVE). (PORT A ADDRESS SELECTED)
WRITE DDA A .. (jaW"Ole (CHIP ENAlLESACTN". ftlOA A ADDRESS SELECTED)
READ PA .. {[IIO.l). fKD ..OIl t (iOR.O)) • (CHIP (NAILES ACTIVE). (PORT A ADOIUSS SELECTEDI
NOTE: WRITE PA IS NOT QUALIFIED BY 101M.
. Note that hardware RESET or wrlti'ng a zero to the DDR
latGh will cause the output latch'S output. buffer to be
disabled, preventing the data in the Output Latch from
, being passed through to. the pin. This Is equivalent to
putting the port in the input mode. Note also that the data
can be written to the Output Latch even though the Output
Buffer has been disabled. This enables a port to be initialized with a' value prior to enabling the output.
The diagram also sl10ws that the contents of PORT A and
PORT B can be read eVlln when the ports are configured
as outputs.
TABLE 1. 8755A PROGRAMMING MODULE CROSS
REFERENCE
MODULE. NAME
USE WITH
UPP 955
UPP UP2(2)
PROMPT 975
PROMPT 475
UPP(4),
UPP 855
PROMPT 80/85(3)
PROMPT 48(1)
NOTES:
1. DeS9ribed on p. 13-34 of 1978 Data Catalog.
,2. Special adaptor socket.
3. Described on p. '13-39 of 1978 Data Catalog.
4. Described on p. 13-71 of 1978 Data Catalog.
To clarify the function of the I/O Ports and Data Direction
Registers, the following diagram shows the configuration'
of one bit of PORT A and OCR A. The same logiC applies
to PORT Band DDR B.
AFN'()0843D
inter
8755A18755A-2
ERASURE CHARACTERISTICS
SYSTEM APPLICATIONS
The erasure characteristics of the 8755A are such that
erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain types of
fluorescent lamps have wavelengths in the 3000-4000A
range. Data show that constant exposure to room level
fluorescent lighting could erase the typical 875SA in
approximately 3 years while it would take approximately 1
week to cause erasure when exposed to direct sunlight.
If the 8755A is to be exposed to these types of lighting
conditions for extended periods of time, opaque labels
are available from Intel which should be placed over the
8755 window to prevent unintentional erasure.
System Interface with e085A and IAPX 88
The recommended erasure procedure for the 8755A is
exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e.,
UV intensity X exposure time), for erasure should be a
minimum of 15W-sec/cm2 . The erasure time with this
dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000/LW/cm 2 power rating. The
8755A should be placed within one inch from the lamp
tubes during erasure. Some tamps have a filter on their
tubes and this filter should be removed before erasure.
A system using the 8755A can use either one of the two I/O
Interface techniques:
• Standard I/O
• Memory Mapped I/O
If a standard I/O technique Is used, t~ a system can use
the feature of both CE2 and CE1 • By IIslng a combination of unused address lines A 11 - 15 and the Chip
Enable Inputs, the 808SA system can use up to 5 each
8755A's without requiring a CE decoder. See Figure 4a
anc! 4b.
If a memory ma~ped I/O approach is used the 8755A will
be selected by.,!he combination of both the Chip
Enables and 101M using AD8 - 15 address lines. See
Figure 3.
-
A
'~>
K;8-15
PROGRAMMING
Initially, and after each erasure, all bits of the EPROM
portions of the 8755A are in the "1" state. Information is
introduced by selectively programming "0" Into the
desired bit locations. A programmed "0" can only be
changed to a "1" by UV erasure.
The 8755A can be programmed on the Intel@ Universal
PROM Programmer (UPP). and the PROMPT'" 80/85 and
PROMPT-48'" design aids. The appropriate programming
modules and adapters for use in programming both
8755A's and 8755'5 are shown in Table 1.
The program mode itself consists of programming a
single address at a time, giving a single 50 msec pulse
for every address. Generally, it is desirable to have a
verify cycle after a program cycle for the same address
as shown in the attached timing diagram. In the verify
.cycle (i.e., normal memory read cycle) 'Voo' should
be at +5V.
.
Preliminary timing diagrams and parameter values pertaining to the 8755A programming operation are contained in Figure 7:.
2-149
A
B085A
;>
~ ADo.,
'oj
ALE
-
RD
-
WR
eLK 1,,2)
READY
101M
-
r",
V
-
AID ..,
iDR
f
'"
;.
AB_10
r
RD elK
101M
ALE iOi'I READY CE
B755A
Figure 3. 87SSA In 808SA System
(Memory-Mapped I/O)
AFN·008430
inter
8755A18755A..2
IAPX 88 FIVE. CHIP SYSTEM
Figure 4 shows a five chip system containing:
• 1.25K Bytes RAM
• 2K Bytes ROM
.381/0 Pins
• 1 Interval Timer
• 2 Interrupt Levels
/'
/'
Vss Vee
I I
I ~f-
-
~ I-
POR1~
CE
ViR
'PORT~
_
RD 8155-2
.
IO/ii
RESET
As-Au
r-
r-
ADo-AD7
ClK
®
ClK
READY
f-
r--
PORT
A
CE
.J\
it::
A S_ 10
-V
~
83111-21
175fA.2
DATAl
ADDR
t--Vcc
iili
r-- r-r-- r-- r-
VIR
r--
.---
8284
IN_
TIMER
OUT
ALE
~~
101M
RES
.
il5W
iili
P',
AODRIDATA
ALE
RST
x,
X,
..~
8088
READY
MNIMX
rD1
AD OR
B
PORT~
C
(6)
ALE
DATAl
ADDR
I--I---
r--
RESET
r
101M
r--
PORT
RESET
8
~
vee
READY
il5li
!!!
-l
LROG
Vss Vee Voo
"ee
RDY1
ViR
iili
....
(j)
eE,
.,811-2
ALE
\1-
.rr-
cs.
CE,
Ae. A,
ADO_l
JJ
,
Vs.
Vee
,
Figure 48. IAPX 88 Five Chip System Configuration
2-150
AFN-00843C
(
A
"TI
I
AIOf)-l
tT
.....
~
ALE
S·
~
~
ao8"
rr-
jffi
WR
CD
elK (1/)2)
CD
UI
READY
rrr-
0
~
~
(I>
-
r-
"
CD
101M
'-"
'"
A"
a;
UI
UI
:=0
.e
AI-1S
C
c
-'-
-
r-
'"
A"
r-
r-
r-
r-
r-
r-
rrrr-
rrr-
rrrr-
r-
r-
r-
r-
V
CD
~.
en
~
CD
.....
en
en
~
Cil"
3
~.
2!
'"a.
::J
'"a.
.9
vee
f'
;.~
A/D ...,
1m.
;.
AI-"
RD
ALE
eLK
iOW
8755A
(2K BYTES)
IDIlii,
READY
eEl
II
Vt'~
iiii
AID~,
,
7
AI-..
RD eLK
IDiM,
ALE IlIW READY eE 2
II t\
AID...,
iDA
~
AI-"
RD eLK
IDIlii ,
ALE iOW READY eE 2
8755A
8755A
12K BYTES)
12K BYTES)
II
t\ ;. ,
i
iiiR
AIDI-'
'1
AI-" ALERDi1iWeLKREADY
ID,tjeEl
y
8755A
12K BYlES)
Note:'U" CE1 fo, the fi,st 8755A in the system, and CE2 for the other 8755A's. Permit. up to 5-8755A'. in a system without CE decoder.
~
z
~o
7'
AID.. ,
iiiii
AI-"
J
RD elK
101M
ALE iliW READY eE 2
8755A
12K BYTES)
8755A18755A·2
ABSOLUTE MAXIMUM RATINGS·
·NOTlCE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
.
Temperature Under !:lIas ................ 0°Cto+70°C
Storage Temperature .......... . . . .. -65'C to +150°<:;
Voltage on Any Pm
With Respect to Ground .............. , -0.5V to +7V
Power Dissipation ............................. 1.5W
D.C. CHARACTERISTICS
(TA = O°C to 70°, Vee = Voo = 5V ± 5%;
Vee = VOO = 5V ±10% for 8755A-2)
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
VIL
Input Low Voltage
-0.5
0.8
V
Vee = 5.0V
VIH
Input High Voltage
2.0
Vee+O· 5
V
Vee = 5.0V
VOL
Output Low Voltage
0.45
V
IOL = 2mA
VOH
Output High Voltage
V
IOH = -4001lA
IlL
Input Leakage
ILO
O~tPut
Icc
100
2.4
10
IlA
VSS .;; VIN .;; Vee
±10
IlA
0.45V .;; Your .;; Vee
Vee Supply Current
180
mA
Voo Supply Current
30
mA
Voo = Vee
10
pF
fe = 1p.Hz
15
pF
fe = 1p.Hz
Leakage Current
Capacitance of Input Buffer
Capacitance of I/O Buffer
CIN
CVO
D.C. CHARACTERISTICS-PROGRAMMING
Symbol
Parameter
Voo
Programming Voltage (during Write
to EPROM)
100
Prog Supply Current
2-152
(TA =0°Ct070°, Vee = 5V±50/0, vss = OV, Voo =25V±1V;
Vee = Voo = 5V ±100/0 for 8755A-2)
Min.
Typ.
24
25
26
V
15
30
mA
Max.
Unit
AFN·00843D
inter
A.C.
8755A18755A·2
C~ARACTERISTICS
(TA = O°C to 70°. Vee = 5V ± 5%;
Vee
= VOO, = 5V ±10% for 8755A-2)
8755A·2
(Preliminary)
8755A
Symbol
Min.
Parameter
Max.
Min.
Max.
Units
tCYC
Clock Cycle Time
320
200
ns
T1
ClK Pulse Width
80
40
ns
T2
ClK Pulse Width
120
70
tf. tr
ClK Rise and Fall Time
tAL
Address to latch Set Up Time
50
30
ns
tlA
Address Hold Time after latch
80
45
ns
tlC
latch to READ/WRITE Control
100
40
tRO
Valid Data Out Delay from READ Control·
170
140
ns
tAD
Address Stable to Data Out Valid··
450
300
ns
85
ns
30
ns
30
ns
ns,
70
100
ns
tll
latch Enable Width
tROF
Data Bus Float after READ
tCl
READ/WRITE Control to latch Enable
20
10
ns
tcc
READ/WRITE Control Width
250
200
ns
tow
Data In to Write Set Up Time
150
150
ns
two
Data In Hold Time After WRITE
:30
10
twp
WRITE to Port Output
tpR
Port I"'put Set Up Time
50
50
tRP
Port Input Hold Time to Control
50
50
tRYH
READY HOLD Time to Control
0
0
100
0
400
ns
ns
300
' 160
0
160
ns
ns
160
ns
tARY
ADDRESS rCEI to READY
tRV
Recovery Time Between Controls
300
200
ns
tROE
READ Control to Data Bus Enable
10
10
ns
160
ns
NOTE:
eLOAO = 150pF.
·Or TAD - (TAL + TLe!. whichever is greater.
"Defines ALE to Data Out Valid in conjunction with TAL'
A.C. CHARACTERISTICS- PROGRAMMING
Symbol
(TA = O°Cto 70°. Vee = 5V ± 5%. VSS = OV. VOO
Vee = Voo = 5V ±10% for 8755A-2)
Parameter
Min.
Typ.
Max.
= 25V ±lV;
Unit
tps
Data Setup Time
10
ns
tpo
Data Hold Time
0
ns
ts
Prog Pulse Setup Time
2
p.S
tH
Prog Pulse Hold Time
2
p's
tpR
Prog Pulse Rise Time
0.01
2
tpF
Prog Pulse Fall Time
0.01
2
P.s
tpRG
Prog Pulse Width
45
50
msec
2-153
p's
AFN.()0843D
inter
8755A18755A,·2
"
A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUT/OUTPUT
u=x, >
2.0
0.8
0.45
<
2.0
TEST POINTS
0.8
A.C. TESTING LOAD CIRCUIT
x=
DeVICE
UND'ER
reST
!JCL. ,50 PF
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1 AND 0 45V FOR
A LOGIC 0 . TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC 1
AND 0 BV FOR A LOG.lC 0
CL ", 150pF
Cl INCLUDES JIG CAPACITANCE
WAVEFORMS
CLOCK SPECIFICATION FOR 8755A
PROM READ, 1/0 READ AND WRITE
AS10
--)j
ADDRESS
ADDRESS
IO/M'AD
AD07'
ADDRESS
)
-t
~---
> - - - - - - - P R O G R A M CYCLE - - - . . . , - - -......
~_
PROGRAM CYCLE
ALE
DATAlaSE
A/DO_?
PROGRAMMED
tpo
AB·l0
IpS
+25
--
Voo
+5----____________________-{
"-1-*VERIFY CYCLE IS A REGULAR MEMORY READ CYCLE (WITH VOO '" +5V FOR 8755A)
2-156
AFN-00843D
iAPX 86, 88, 186, 188
Microprocessors
Microprocessors
Section
3
",
i ,~. .!
t
'.",
'
'.,'"
"I",:
\
l'
'\
\.'
APPLICATION
NOTE
Ap·113
February 1981
AP·1~3
INTRODUCTION
i
One alternative uses a special hardware component, the
8087 numeric processor extension, while the other is
based on software, the 8087 emulator. Both component
and software emulator add the extra numerics data
types and operations to the 8086 or 8088.
This is an'application note on using numerics in Intel's
iAPX 86 or iAPX 88 microprocessor family. The numerics implemented in the family provide instruction
level support for high-precision integer and floating
point data types with arithmetic operations like add,
subtract, multiply, divide, square root, power, log and
trigonometrics. These features are provided by members
of the iAPX 86 or iAPX 88 family called numeric data
processors.
The component and its software emulator are completely compatible.
'
Nomenclature
Rather than concentrate on a narrow, specific application, the topics covered in this application note were
chosen for generality across many applications. The
goal is to provide sufficient background information so
that software and hardware engineers can quickly move
beyond needs specific to the numeric data processor and
concentrate on the special needs of their appliaation.
The material is structured to allow quick identification
of relevant material without reading all the material
leading up to that point. Everyone should read the introduction to establish terminology and a basic
background.
Table one shows several possible configurations
of the iAPX 86 and iAPX 88 microprocessor, family.
The choice of configuration will be decided by the
needs of the application for' cost and performance
in the areas of general data processing, numerics,
and 1/0 processing.' The combination of an 8086 or
8088 with an 8087 is called an iAPX 86/20 or 88/20
numeric data Processor. For applications requiring high 110 bandwidths and numeric performance, a combination of 8086, 8087 and 8089 is ali
iAPX 86/21 numerics and 110 data processor. The
same system with an 8088 CPU for smaller size
and lower cost, due to the smaller 8-bit wide
system data bus, is referred to as an iAPX 88/21.
Each 8089 in the system is designated in the units'
digit of the system designation. The term 86/2X or
88/2X refers to a numeric data processor with any
number of 8089s.
IAPX 86,88 BASE
The numeric data processor is based c;m an 8088 or 8086
microprocessor. The 8086 and 8088 are general.purpose
microprocessors, designed for general data processing
applications. General applications need fast, 'efficient
data movement and program control instructions. Actual arithmetic on data values is simple in general applications. The 8086 and 8088 fulfill these needs in a low
cost, effective manner.
Throughout this application note, I will use the
terms NDP, numeric data processor, 86/2X, and
88/2X synonymously. Numeric processor extension and NPX are also synonymous for the functions of either the 8087 component or 8087
emulator. The term numeric instruction or
numeric data type refers to an instruction or data
type made available by tile NPX. The term host will
refer to either the 8086 or 8088 microprocessor.
However, some applications. need more powerful arithmetic instructions and data types than a general purpose
data processor provides. The real world deals in fractional values and tequires arithmetic operations like
square root, sine, and logarithms. Integer data types
and their operations like add, subtract, multiply, and
divide may not meet the needs for accuracy, speed, and
ease of use.
Table,1. Components Used In IIAPX 88,88
Conflgural/ons
Such functions are not simple or inexpensive. The
general data processor does not provide these features
due to their cost to other less-complex applications that
do not need such features!. A special processor is required, one which is easy to use and has a high level of
support in hardware and software.
The numeric data processor provides these features. It"
supports the data types and operations needed and
allows use of all the current hardware and software support for the iAPX 86/10 and 88/10 microprocessors.
System Name
8088
iAPX 86/10
iAPX 86/11
iAPX 86/12
iAPX 86/20
iAPX 86/21
iAPX 86/22
1
1
1
1
1
1
iAPX 88/10
iAPX 88111
iAPX 88/12
iAPX 88/20
iAPX 88/21
iAPX 88/22
The iAPX 86 and iAPX 88 provide two imple-,
mentations of a numeric data processor. Each offers
different tradeoffs in performance, memory size, and
cost.
3-2
8087
8088
8089
1
2
1
1
1
1
1
1
I
2
1
1
1
1
1
1
1
2
1
2
Ap·113
NPX OVERVIEW
the 8087 is a coprocessor extension available to
iAPX 86/IX or iAPX 88/IX maximum mode
microprocessor systems. (See page 7). The 8087'
adds hardware support for floating point and extended precision integer data types, registers, and
instructions. Figure I shows the register set
available to the NDP. On the next page, the seven
data types available to numeric instructions are
listed (Fig 2). Each data type has a load and store
inStruction. Independent of whether an 8087 or its
emulator are used, the registers and data I types all
appear the same to the programmer.
64-bit long integers
IS-digit packed
decimal
32-bit short real
64-bit long t;eal
80-bit temporary
real
All the numeric instructions and data types of the NPX
are used by the programmer in the 'Same manner as the
general data types and instructions of the host.
Referencing memory data types in the NDP is not
restricted to load and store instructions: Some arithmetic operations can specify a memory operand in one
of four possible data types. The numeric instructions
compare, add, subtract, subtract reversed, multiply,
divide, and divide reversed can specify a memory
operand to be either a 16-bit integer, 32-bit integer,
32-bit Peal, or 64-bit real value. As with the load and
store operations, the arithmetic instruction specifies the
address and expected format of the memory operand.
The numeric data formats and arithmetic operations
provided by the 8087 conform to the proposed IEEE
Microprocessor Floating Point Standard. All the proposed IEEE floating point standard algorithms, exception detection, exception handling, infinity arithmetic
and rounding controls are implemented. 1
The numeric registers of the NPX are provided for fast,
easy reference to values needed in numeric calculations.
All numeric values kept in the NPX register file are held
in the 80-bit temporary real floating point format which
is the same as the 80-bit temporary real data type.
The remaining arithmetic operations: square root,
modulus, tangent, arctangent, logarithm, exponentiate,
scale power, and extract power use only register
operands.
All data types are converted to the SO-bit register file
format when used by the NPX. Load and store instructions automatically convert between the memory
operand data type and the register file format for all
numeric data types. The numeric load instruction
specifjes the format in which the memory operand is expected and which addressing mode to use.
All host base registers, index registers, segment
registers, and addressing modes are available for
locating numeric operands. In the same manner, the
store instruction also specifies which data type to use
and where the value is located when stored into
memory..
15
FILE
0
u~
BX
ex
ox
51
01
BP
SP
Selecting Numeric Data Types
As figure 2 shows, the numeric data types are of different lengths and domains (real or integer). Each
numeric data type is provided for a specific function,
they are:
16-bit word integers
-Large integer general
computation
-Extended range integer
computation
-Commercial and. decimal
conversion arithmetic
-Reduced range and
accuracy is traded for
reduced memory requirements
-Recommended floating
poi~t variable type
-Format for intermediate
or high precision calculations
32-bit short integers
NPX STACK
SIGNIFICANO
R6
R8
i~1
Implementation Guide to a Proposed Standard for Floating
Point" by Jerome Coonen in Computer, Jan. 1980 or the Oct. 1979
issue of ACM SIGNUM, for more information on the standard.
EXPONENT
R7
I
-Index values, loop counts,
and small program control
values
79
R1
R2
R3
R4
R5
IP
FLAGS
I
NPXSTATUS
NPXMOOE
I
t ..An
Figure 1. NDP Register Seftor IAPX 86/20,88120
3-3
0
AP~113
The register. set of the host and BQ87 are in separate
components. Direct transfer of values between the two
register sets in one instrUction is not possible. To transfer values between the host and numeric· register sets,
the value must first pass through memory. The memory
format of a 16-bit short integer used by the NPX is identical to that of the host, ensuring fast, easy transfers.
8087 EMULATOR OVERVfEW
The NDP has two basic implementations, an 8087 coinponent or with its software emulator (E8087);"Thedeci~
SiOli'tO use the emulator or component has no'effect on
programs at the source leveL At the source level, all instructions, data types, and features are used the same
,
way.
Since an 8086 or 8088 does not provide single instruction support for the remaining numeric data types, host
programs reading or writing these data types must conform to the bit and byte ordering established by the
NPX.
The emulator requires all nu,neric instruction opcodes
to be replaced with 'an fnterrupt instruction. This
replacement is performed by the LINK86 program.' Interrupt vectors in the host's interrupt vector table will
point to numeric instruction emulation routines in the
8087 software emulator.
Writing programs using numeric instructions is as simple as with the host's instructions. The numeric instructions are simply placed in line with the host's instructions. They are executed in the same order as they appear in the instruction stream. Numeric instructions
follow the same fbrm as the host instructions. Figure 2
shows the ASM 86/88 representations for different
numeric instructions and their similarity to host instructions.
VALUE
TABLE [8X]
ST,ST(1)
FILD
FIADD
FADD
DATA
~ORMATS
PRECISION
7
01 7
1Q4
16 BITS
I"
SHORT INTEGER
10'
32 BITS
131
1019
64 BITS
I"
PACKED BCD
1018
18 DIGITS
S
SHORT REAL
10:!:38
24 BITS
INTEGER
,
MOST SIGNIFICANT BYTE
RANGE
WORD INTEGER
~ONG
When using the 8087 emulator, the linker changes all the
2-byte wait-C1scape, nop-escape, wait-segment override,
or nop-segment override sequences generated by an
assembler or compiler for the 8087 component with a
2-byte interrupt instruction. Any remaining bytes of the
numeric instruction are left unchanged.
01 7
01 7
01 7 ,
01 7
01 7
01 7
01 7
TWO'S COMPLEMENT
101
loj
- 1 0 17
0161
10:!:308
53 BITS
S
11;10
TEMPORARY REAL
10:1:.4932
64 BITS
S
IE14
TWO'S
COMPLEMENT
1 0,
S IE7 EO) F,
LONG REAL
oj
TWO'S COMPLEMENT
101
I
01 7
F231
Eol f,
Fo ,MPLICIT
,
F52)
I
Eo Fo
001
Fo IMPLICIT
F..
INTEGER: 1
PACKED BCD: (-115(017." Dol
REAL: (-1IS(2E.•JAS)(Fo.F, ... )
BIAS = 127 FOR SHORT REAL
1023 FOR LONG REAL
16383 FOR TEMP REAL
Figure 2. NPX Data Types
3-4
I
Ap·113
When the host encounters numeric and emulated instruction, it will execute the software interrupt instruction formed by the linker. The interrupt vector table will
direct the host to the proper entry point in the 8087
emulator. Using the interrupt return address and CPU
register set, the host will decode any remaining part of
the numeric instruction, perform the indicated operation, then return to the next instruction following the
emulated numeric instruction.
SOS7 BASED LINK/LOCATE COMMANDS
LlNKS6 :F1:PROG.OBJ, IO.LlB, SOS7.LlB TO
:F1:PROG.LNK
LOC86 :F1:PROG.LNK TO :F1:PROG
SOFTWARE EMULATOR BASED
LINK/LOCATE COMMANDS
One copy of the 8087 emulator can be shared by all programs in the host.
LlNKS6 :F1 :PROG.OBJ, IO.LlB, ESOS7.LlB,
ESOS7 TO :F1:PROG.LNK
LOCS6 :F1:PROG.LNK TO :F1:PROG
The decision to use the 8087 or software emulator is
made at link time, when all software modules are·
brought together. Depending on whether an 8087 or its
software emulat'Or is used, a different group of library
modules are included for linking with the program.
Figure 3. Submit File Example
If the 8087 component is used, the libraries do not add
any code to the program, they just satisfy external references made by the assembler or compiler. Using the
emulator will not increase the size of individual modules; however, other modules requiring about 16K bytes
that implement the emulator will be automatically
added.,
Isec 337™ MULTIMODULETM BOARD
Selecting between the emulator or the 8087 can be very
easy. Different versions of submit files performing the
link operation can be used to specify the different set of
library modules needed. Figure 3 shows an example of
two, different submit files for the same program using
the NPX with an 8087 or the 8087 emulator.
/
iSBC 337™ MULTIMODULETM Overview
BOARD
(ISBC 86/12A'")
The benefits of the NPX are not limited to systems
which left board space for the 8087 component or memory space for its software emulatoE. Any maximum
mode iAPX 86/1X or iAPX 88/1X system can be upgraded to a numeric processor. The iSBC 337 MULTIMODULE is designed for just this function. The
iSBC 337 provides a socket for the host microprocessor
and an 8087. A 4O-pjn plug is provided on the underside
of the 337 to plug into the original host's socket, as
shown in Figure 4. Two other pins on the underside of
the MULTIMODULE allow easy connection to the
8087 INT and RQ/GTI pins.
OPTIONAL SOLDER
MOUNT
Figure 4. MULTIMODULETM Math Mounting Scheme
3-5
Ap·113
CONSTRUCTING AN iAPX 86/2X OR iAPX
8812X SYSTEM
This section will describe how to design a microprocessor system with the 8087 component. The discussion
will center around hardware issues. However, some of
the hardware decisions must be made based upon how
the software will use the NPX. To better understand
how the 8087 operates as a local bus master, we shall
cover how the coprocessor interface works later in this
section.
Wiring up the 8087
The 8087 can be designed into any 86/IX or 88/IX
system operating in maximum mode. Such a system
would be designated an 8612X or 88/2X. Figure 5 shows
the local bus interconnections for an iAPX 86/20 (or
iAPX 88/20) system. The 8087 shares the maximum
mode host's multiplexed address/data bus, status signals, queue status signals, ready status signal, clock and
reset signal. Two dedicated signals, BUSY and INT, inform the host of current 8087 status. The 10K pull-down
resistor on the BUSY signal ensures the host will always
see a "not busy" statu~ if an 8087 is not installed.
Adding the 8087 to your design has a minor effect on
hardware timing. The 8087 has the exact same timing
and equivalent DC and AC drive characteristics as a
host or lOP on the local bus. All the local bus logic,
such as clock, ready, and interface logic is shared.
The 8087 adds 15 pF to the total capacitive loading on
the shared address/data and status signals. Like the
8086 or 8088, the 8087 can drive a total of 100 pF
capacitive load above its own self load and sink 2.0 mA
DC current on these pins. This AC and DC drive is sufficient for an 86/21 system with two sets of data
transceivers, address latches, and bus controllers for
two separate busses, anon-board bus and an off-board
MULTIBUSTM using the 8289 bus arbiter.
Later in this section, what to do with the 8087 INT and
RQ/GT pins, is covered.
It is possible to leave a prewired 4O-pin socket on the
board for the 8087.. Adding the 8087 to such a system is
as easy as just plugging it in. If a program attempts to
execute any numeric instructions without the 8087 installed, they will be simply treated as NOP instructions
by the host. Software can test for the existence of the
8087 by initializing it and then storing the control word.
The program of Figure 6 illustrates this technique.
_N"" .. "'CO .....
8282
Figure 5. System Diagram
3-6
AU'
12 AD4
13 AD3
A;
~ 000
~ 001
II!
~
A.
A;
A:
A;
A
002
003
~ DO.
o
012
3
ST8
81
~ 82
1
2
3
•
i' 83
za>
~86
t
A67
A7 8
T
87
DE
91
"
..!,j
4191S6
36 A18155
(SSOl8HElS7
37 A171S4
READY 22
RESET 21
elK 19
6 AO'0(A10}
~I!
l-g
n-il
:!
"!-
:;3.
;S"
80
AOI
AI •
A2 3
A3 •
A. 5
A5 6
A6 7
A7 8
~:
~:
a>
N
a>
a>
I 86
! B7
DE
:::::
rocK
~29
-
_
~~
;:
-
NMI 17
INTR 18
NIII
IN",
J~'
•
12 AD4
•
6
eLK AEN
13 ADa"I'
AD.
15
ADI
16 ADO
52 28
51 2;"
18 52
SO
19
26
91 " L
4Ot,
+5V
.....
~
'~
-=-
10~ ~h
+SV
MCE
171
lOB GNO Vee CEN MeEl
iiDEN
a>
N
a>
a>
3 S.
SO
Vee GND GNOMNIfi
T
.:~
3
lID
RllICTO
9 AD7
10 ADS
11 ADS
~!!
~;1
~
liD 32
AQ/CfO 31
::~::~:
4
5 A011(A11)
I
'V
~
....
~
38 AI61S3
AO'5(AI5)"
3 AOI4(AI4}
~ 81
:J>
30
23
2.
25
OSI OSOiiOJGTlmT
~
a:
(.0)
zz
°li
If.
~
Ani
AO
AI
A2
A3
~B4;'~A45
~85~"'A56
Ol!.
BUSYSO
23
"
o
01
28
~'"
6
o
D_
:~
31
017 8
tBO
~
QSO
25
.2'
016 7
T
o
2
DIS
, 007
DE
o
1
011
52
S1 j1!. f.--
_
013 4
DI4 5
a>
N
a>
N
~::
010
~ AD2
~ AD1
~ AD~S1
I=}
~AtOWC ..!
ALE DTIR DEN MRDC MWTC ~ INTA
5
•
.6
-
9
7
II
~I
••
8
II
~I
~
iiiWc"
"ifc)wc
AP·113
Clition. The host's coprocessor interface can read a
value from memory, or identify a region of memory the
coprocessor should use while perf~rming its fun~on.
All the addressing modes of the host are available to
identify memory based operands to the coprocessor.
WHAT IS THE IAPX 86, 88
COPROCESSOR INTERFACE?
The idea of a coprocessor is based on the observation
that hardware specially desi$lled for a function is the
fastest, smallest, and cheapest implementation. But, it is
too expensive to incorporate all desired functions in
general purpose hardware. Few applica~ons could use
all the functions. To build fast, small, eConomical systems, we need some way to mix and match ¢omponents
supporting specialized functions.
'
'
Purpose of the Coprocessor Interface
The coprocessor interface of the general,Purpose 8086
or 8088 microprocessor provides a way to attach specialized hardware in a simple, elegant, and efficient manner. Because the coprocessor hardware is specialized, it
can perform its job much faster than any general purpose CPU of similar size and cost. The coprocessor
interface simply requlles connection to the host's local
address/data, status, clock, ready, reset, test and request/grant signals. Being attached to the host's local
bus gives the coprocessor access to all memory and I/O
resources availabl~ to the host. '
Concurrent Execution of Host and
Coprocessor
After the coprocessor has started its operation, the host
may continue on with the program, executing it in parallel while the coprocessor performs the function started
, earlier. The parallel operation of the coprocessor does
not normally affect that of the host, unless the coprocessor must reference memory or I/O-based operands.
, When the host releases the local bus to the coprocessor,
the host may continue to execute from its internal instruction queue. However, the host must stop when it
also needs the local bus currently in use by the coprocessor. Except for the stolen memory cycle, the operatio~ of the coprocessor is transparent to the host.
This parallel ,operation of host and coprocessor is called '
concurrent eXecution. Concurrent execution of instructions requires less total time then a strictly sequential
execution would. System performance will be higher
with concurrent execution of instructions between the
host and coprocessor.
The coprocessor is independent of system configuration. Using the local bus as the connection point to the
host isolates the coprocessor from the particular system
configuration, since the timing and function of local bus
'
signals are fixed.
SYNCHRONIZATION
In exchange for the higher system performance made
available by concurrent execution, programs must provide what is called synchropization between the host
and coprocessor. Synchronization is necessary whenever
the host and coprocessor must use information available
from the otJter. Synchronization inv!>lv~ either the host
or coprocessor waiting for the,other to finish an operation currently in progress. Since the host executes the
program, and has program control instructions like
jumps, it is given responsibility for synchronization. To
meet this need, a special host instruction exists to synchronize host operation with a coprocessor.
Software's View of the CoproCessor
T~e coprocessor interface allows specialized hardware .
to appear as an integral part of the host's architecture
controlled by the host with special instructions. When
the host encounters these special instructions, both the '
host and coprocessor recognize them and work together
to perform the desired function. No status polling loops
or command stuffmg sequences are required by software to operate the coprocessor.
More information is available to a coprocessor than
simply an instruction opcode and a signal to begin exe"
;
;
,;
;
;
Test for the existenqe of an 8087 in the system. This code will always recognize an 8087
independent of the TEST' pin ,lJsage on the host. No deadlock is poss'ible. USing the 8087
emulator will not change' tHe 'function of this code since: ESC instructions are used, The word
variable control is used for communlcatio'n between the 8087 and the tlost. Note: if an 8087 is
present, it will be initialized, Register ax is not transparent aCross this code.
"
,ESC
XOR
,MOV
ESC
OR
JZ
28,bx
ax,ax
control, ax
15, contr!,1
ax, control
no_8087
;
;
;
;
;
';
FNINITif ~7 is present, The contents of bx is irrelevant
These two instructions insert delay while the 8087 initializes itself
Clear Intial control wlord value
'
,FNSTCW if 8087 Is present
Control == 03ffh if 8087 present
Jump if no 8087 is present
FigureS. Test for EXistence' ofan 6087
3-8
AP·113
would be otherwise idle. The end benefit is faster. execution time of host instructions for a given memory bandwidth.
The host coprocessor synchronization instruction,
called "WAIT", uses the TEST pin of the host. The
coprocessor can signal that it is still busy to the host via
this pin. Whenever the host executes a wait instruction,
it will stop program execution while the TEST input is
active. When the TEST pin becomes inactive, the host
will resume program execution with the next instruction
following the WAIT. While waiting on the TEST pin,
the host can be interrupted at S clock intervals; however, after the TEST pin becomes inactive, the host will
immediately execute the next instruction, ignoring any
periding interrupts between the WAIT and f9llowing
instruction.
The host does not externally indicate which instruction
it is currently executing. Instead, the host indicates
when it fetches an instruction and when, some time
later, an opcode byte is decoded and executed. To id~
tify the actual instruction the host fetched from Its
queue, the coprocessor must also maintain an instruction stream identical to the host's.
Instructions can be fetched in byte or word increments,
depending on the type of host and the destination address of jumP. instructions executed by the host. When
the host has filled its queue, it stops prefetching instructions. Instructions are removed from the queue a byte at
a time for decoding and execution. When a jump 0ccurs, the queue is emptied. The coprocessor follows
these actions in the host by monitoring the host's bus
status, q~eue status, and data bus signals. Figure 7
shows how the bus status signals and queue status
"
signals are encoded.
COPROCESSOR CONTROL
The h~st has the responsibility for overall pl,'Ogram cotttrol. Coprocessor operation is initiated by special instructions encountered by the host. These instructions
are called "ESCAPE" instructions. When the host ericounters
ESCAPE instruction, the coprocessor is
expected to perform the action indicated by the instruction. There are 576 different ESCAPE instructions,
allowing the coprocessor to perform many different
actions.
an
IGNORING UO PROCESSORS
The host is not the only local bus master capable of
fetching instructions. An Intel 8089 lOP can generate
instruction fetches on the local bus in the course of executing a chalmel program in system memory. In this
case, the status signals 82, SI, and SO generated by the
lOP are identical to those of the host. The coprocessor
must not interpret these instruction prefetches as going
to the host's instruction queue. This problem is solved
with a status signal called S6. The S6 signal identifies
when the local bus is being used by the host. When the
host is the local bus master, S6 =0 during T2 and T3 of
the memory cycle. 'All other bus masters must set S6 = 1
during T2 and T3 of their instruction prefetch cycles.
Any coprocessor must ignore activity on the local bus
when S6= 1.-·
The host's coprocessor interface requires the coprocessor to recogniie when the host has encountered an
ESCAPE instruction. Whenever the host begins executiRg a new instructiop., the coprocessor must look to see
if it is an ESCAPE instruction. Since only the host
fetches instructions and executes them, the coprocessor
must monitor the instructions being executed by the
host.
Host Queue Tracking
The host can fetch an instruction at a variable length
time before the host executes the instruction. This is a
characteristic of the instruction queue of an 8086 or
8088 microprocessor. An i1istruction queue allows prefetching instructions during times when the local bus
.
S2
S1
SO
Function
QS1
QSO
0
0
0
Interrupt Acknowledge
0
0
No Operation
0
0
1
Read I/O Port
0
1
First Byte
Decode Opcode Byte
0
1
0
Write I/O Port
1
0
Empty Queue
Empty Queue
0
1
~
Halt
1
1
SubsequeAt Byte
Flush Byte or if 2nd
1
0
0
Code Fetch
Byte of Escape
1
0
1
Read Data Memory
Decode it
1
1
0
Write Data Memory
1
1
1
Idle
Figure 7.
3-9
Host Function
Coprocessor Activity
No Queue Activity
Ap·113
They, together with the R/M field, bits 2 through 0,
determine the addressing mode and how many subsequent bytes remain in the instruction.
DECODING ESCAPE INSTRUCTIONS
To recognize ESCAPE in~truCtions, the coprocessor
must examine all instructions executed by the host.
When the host fetches an instruction byte from its internal ~ueue, the coprocessor must do likewise.
H08t'8 Re8ponse to an E8cape Instruction
The host performs one of two possible actions when
encountering an ESCAPE instruction: .do nothing or
calculate an effective address and read a word value
beginning at that address. The host ignores the value of
the word read. ESCAPE instructions change no registers in the host other than advancing IP. So, if there is
no coprocessor, or the coprocessor ignores the ESCAPE
instruction, the ESCAPE instruction is effectively a
NOP to the host. Other than calculating a memory address and reading a word of memory, the host makes no
other assumptions regarding coprocessor activity.
The queue status state, fetch opcode byte, identifies
when an opcode byte is ~ing examined by the host. At
the same time, the coprocessor will check if the byte fetched from its internal instruction queue is an ESCAPE
opcode. If the instruction is not an ESCAPE, the
coprocessor will ignore it. The queue status signals for
fetch subsequent byte and, flush queue let the
coprocessor track the host's queue without knowledge
of the length and function of host instructions and addressing modes.
The memory reference ESCAPE instructions have two
purposes: identify a memory operand and for certain instructions, transfer a word from memory to the
coprocessor.
Escape Instruction Encoding
All ESCAPE instructions start with the high-order
S-bits of the instruction being 11011. They have two
basic forms. The non~memory form, listed here, initiates some activity in the coprocessor using the nine
available bits of the ESCAPE instruction to indicate
which function to perform.
COPROCESSOR INTERFACE TO MEMORY
The design of a coprocessor is considerably simplified if
it only requires reading memory values of 16 bits or less.
The host can perform all the reads with the coprocessor
latching the value as it appears on the data bus at the
end of T3 during the memory read cycle. The coprocessor need never become a local bus master to read or
write additional information.
MOD
11111011,1,
1,5 1,4 113 1,2 I"
, I 11111
1,0
19
Is
17
IS
I I I , I 1
15
14
13
12
1,
10
Memory reference forms of the ESCAPE instruction,
shown in Figure 8, allow the host to point out a memory
operand to the coprocessor using any host memory addressing mode. Six bits are available in the memory
reference form to identify what to do with the memory
operand. Of course, the coprocessor may not recognize
all possible ESCAPE instructions, in which case it will
simply ignore them.
If the coprocessor must write information to memory,
or deal with data values longer than one word, then it
must save the memory address and be able to become a
local bus master. The read operation performed by the
host in the course of executing the ESCAPE instruction
places the 2O-bit physical address of the operand on the
address/data pins during T1 of the memory cycle. At
this time the coprocessor can latch the address. If the
coprocessor instruction also requires reading a value, it
will appear on the data bus during T3 of the memory
read. All other memory llytes are addressed relative to
this starting physical address.
Memory reference forms of ESCAPE instructions are
identified by bits 7 and 6 of the byte following the
ESCAPE opcode. These two bits are the MOD field of
the 8086 or 8088 effective address calculation byte.
MOD
11,1,0,1111
1, 5 1,4 1,3 1,2 I"
RIM
1,0
19
18
17
Is
15
14
13
12
MOD
11111011111
1,5 1,4 '13 1,2 I"
19
18
17
16
15
14
13
12
1,0
19
18
17
16
14
13
12
MOD
~ ~ ~
10
RIM
15
1,
10
RIM
111°1 0 , , I ' , ,
~
~
~
~
~
~
4
~
~
4
I I I I
~
Os
D7
08
I I I I
06
1I
, , ,
D8
a·blt displacement
II I I I' ,
D8
DS
D4
D3
02
D,
DO
I
Figure 8. Memory Reference Escape Instruction Forms
3-10
I I , I I I II
07
05
04
03
D2
D,
DO
1.·blt displacement
D,S D'4 D'3 D'2 D" D'0 D9
I
I
I I I
0,5 0 ,4 0,3 012 0" 0,0
I
I
1,
I 11°,1, I 1'1 I
11,1)01111,
~ ~
10
RIM
MOD
1111101111,
1,5 1,4 113 1,2 I"
1,
I 11110, I I I ,
1,0
II·blt direct displacement
1,1, 11 °1
, , 1°,01'
D7
I
I) I I I I
Ds
Ds
D4
D3
D2
D,
Do
I
Ap·113
The next section examines how the 8087, uses the
coprocessor interface of the 8086 or 8088.
Whether the coprocessor becomes a bus master or not,
if the coprocessor has memory reference instruction
forms, it must be able to identify the memory read performed by the host in the course of executing an
ESCAPE instruction.
8087 COPROCESSOR OPERATION
The 8086 or 8088 ESCAPE instructions provide 64
memory reference opcodes and 512 non-memory reference opcodes. The 8087 uses. 57 of the memory reference
forms and 406 of the non-memory reference forms. Figure 9 shows the ESCAPE instructions. not \lsed by the
8087.
Identifying the memory read is straightforward, requiring all the following conditions to be met:
1) A MOD value of 00,01, or 10 in the second byte
of the ESCAPE instruction executed by the host.
2) This is the frrst data read memory cycle performed
, by the host after it encountered the ESCAPE in- '
struction. In particular, the bus status signals
S2-SO will be 101 and S6 will be O.
The coprocessor must continue to track the instruction
queue of the host while it calculates the memory address
and reads the memory value. This is simply a matter of
following the fetch subsequent byte status commands
occurring on the queue status pins.
11 1 1 0 1 1 1 1 1
'15 '14 '13 '12 'II
110
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
HOST PROCESSOR DIFFERENCES
A coprocessor must be aware of the bus c~aracteristics
of the host processor. This determines how the host will
read the word operand of a memory reference ESCAPE
instruction. If the host is an'8088, it will always perform
two byte reads at sequential addresses. But if the host is
an 8086, it can either' perform a single word read or two
byte reads to sequential addresses.
The 8086 places no restrictions on the alignment of
word operands in memory. It will automatically perform two byte operations for word operands starting at
an odd address. The two operations are necessary since
the two bytes of the operand exist in two different memory words. The coprocessor should be able to accept the
two possible methods of reading a word value on the
8086.
A coprocessor can determine whether the 8086 will perform one or two memory cycles as part of the current
ESCAPE instruction execution. The ADO pin during Tl
of the first memory read 15y the host tells if this is the
only read to be performed as part of the ESCAPE instruction. If this pin is a 1 during Tl of the memory
cycle, the 8086 will immediately follow this memory
read cycle with another one at the next byte- address.
19
0
0
0
0
0
0
0
0
0
18
1
1
1
1
1
1
1
1
15
0
0
0
1
1
1
1
1
1 1
1 1 1
1 1 1
1 1 1
1 1 1
0
1
1
1
1
1
1
1
1
1
1
1
1
11 1 1 I
1
'10
'9
'8
14
1
1
1
0
0
0
1
1
13
0
0
0
0
0
1
0
1
12
0
0
1
0
1
1
1
0
'7
1
11 10
0 1
1 -
1
'4
'5
'8
I
'I
'0
1
2
4
2
2
1
1
1
1
1
1
1
1
------
2
2
8
18
----0 0 0 1
1
1 0
1 0
1 0
1 0
1 1
'2
Available code.
---
1
1
1
0
1
1 1 1 1
0 0 1 0
0 0 1 1
0 1
1
I
1
'3
32
1
1
4
8
18
0 0 1 0
0 1-1':"--
----
---
105 total
Available Non.Memo,ry Reference Escape Instrucllons
MOD
11 1 1°1 1 1 1 1
'IS '14 '13, '12 'II
11019
0 0
0 1
0 1
0 1
1 0
1 0
1 1
Coprocessor Interface Summary
The host ESCAPE instructions, coprocessor interface,
and WAIT instruction allow easy extension of the host's
architecture with specialized processors. The 8087 is
such' a processor, extending the host's architecture as
seen by the programmer. The specialized hardware provided by the 8087 can greatly improve system performance economically in terms of both hardware and
software for numerics applications.
18
1
1
1
1
1
1
1
15
0
0
1
1
0
1
0
'10
II
'9
II
'8 "7
RIM
I
I
'6
'5
I
'4
I
'3
I
1
'2
'I
14 13
0 1
0 1
0 0
1 0
0 1
0 1
0 1
Available Mem,ory Reference Escape Instrucllons
Figure 9.
3-11
'0
Ap·113
Using the 8087 With Custom
Coprocessors
Custom coprocessors, a designer may care to develop,
should limit their use of ESCAPE instructions to those
not used by the 8087 to prevent ambiguity about
whemer anyone" ESCAPE instruction is intended for" a
i1umerics or other custom coprocessor. Using any
escape instruction for a custom coprocessor may conflict with opcodes chosen for future Intel coprocessors.
Operation of an 8087 together with other custom coprocessors is possible under the following con~traints:
1) All 8087 errors are masked. The 8087 will update its
opcode and instruction address registers for the unused opcodes. Unused memory reference instruc-"
tions will also update the operand address value.
Such changes in the 8087 make software-defined
error handling impossible.
2) If the coprocessors provide a aUSY signal, they must
be ORed together for connection to the host TEST
pin. When the host executes a WAIT instruction, it
does not know which coprocessor will be affected by
the following ESCAPE instruction. In" general, all
coprocessors must be idle before executing the
ESCAPE instruction.
Operand Addressing by the 8087
The 8087 has seven different memory operand formats.
Six of them are longer than one word. All are an even
number of bytes in length and are addressed by the host
at the lowest address word.
When the host executes a memory reference ESCAPE
instruction intended to cause a rea" operation by the
8087, the host always reads the low-order word of any
8087 memory operand. The 8087 will save the address
and data read. To read any subsequent wor"s of the
operand, the 8087 must become a local bus master.
When the 8087 has the local bus, it increments the 20-bit
physical address it saved to address the remaining words
of the operand.
When the ESCAPE instruction is intended to cause a
write operation by the 8087, the 8087 will save the address but ignore the data read. Eventu~ly, it will get
control of the local bus, then perform successive write,
increment address operations writing the entire data
value.
8087 OPERATION IN IAPX 88,88 SYSTEMS
The 8087 will work with either an 8086 or 8088 host.
The identity of the host determines the width of the
local bus path. The 8087 will identify the host and
adjust its use of the data bus accordingly; 8 bits for an
8088 or 16 bits for an 8086. No strapping options are
required by the 8087; host identification is automatic.
The 8087 identifies the host each time the host and 8087
are reset via the RESET pin. After the reset signal goes
inactive, the host will begin instruction execution at
memory address FFFFO I6 •
If the host is an 8086 it will perform a word read at that
address; an 8088 will perform a byte read.
The 8087 monitors pin 34 on the first memory cycle
af~er power up. If an 8086 host is used, pin 34 will be the
BHE signal, which will be low for that memory cye1e.
For an 8088 host, pin 34 will be the SSO signal, which
will be high during Tl of the first memory cycle. Based
on this signal, the 8087 will then configure its data bus
width to match that of the host local bus.
For 88/2X systems, pin 34 of the 8087 may be tied to
Vee if not connected to the 8088 SSO pin.
The width of the data bus and alignment of data operands has no effect, except for "execution time and number of memory cycles performed, on 8087 instructions.
A numeric program will always produce the same results
on an 8612X or 8812X with any operand alignment. All
numeric operands have the same relative byte orderings
independent of the host and starting address.
The byte alignment of memory operands can affect the
performance of programs executing on an 8612X. If a
word operand, or any numeric operand, starts on an
odd-byte address, more memory cycies are required to
acces~ the operand than if the operand started on an
even address. The extra memory cycles will lower system
performance.
The 8612X will attempt to minimize the number of extra
memory cycles required for odd-aligned operands. In
these cases, the 8087 will perform first a byte operation,
then a series of word operations, and finally a byte
operation.
88/2X instruction timings are independent of operand
alignment, since byte operations are always performed.
However, it is recommended to align numeric operands
on even boundaries for maximum performance i~ case
the program is transported to an 86/2X.
3-12
Ap·113
ClK
A
~
~
V
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11
8088
r--
--
RESET
~/Gf1 OS
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8286
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TRANSCEIVER
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8284A
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elK
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GENERATOR
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8288
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Figure 10, iAPX 88/21
.3-13
AP·113
As Table 2 implies, three factors determine when the
host will release the local bus:
RQ/GT CONNECTION
.Two decisions must be made when connecting the 8087
to a system. The first is how to interconnect the RQ/GT
signals of all local bus masters. The RQ/GT decision affects the response time to service local bus requests from
other local bus masters, such as an 8089 lOP or other
coprocessor. The intertupt eonnection affects the
response time to service art interrupt request and how
user-interrupt handlers are written. The implications of
how these pins are connected concern both the hardware
designer and programmer and must be understood by
both.
The RQ/OT issue can be broken into three general ca:tegories, depending on system configuration: 86/20 or
88/20, 86/21 or 88121, and 86122 or 88/22. Remote
operation of an lOP is not effected by the 8087 RQ/OT
connection.
1) What type of host is there, an 8086 or 8088?
2) What is the current instruction being executed?
3),How is the lock prefix being used?
An 8086 host will not release the local bus between the
two consecutive byte operations performed for oddaligned word operands: The 8088, in contrast, will never
release the local bus between the two bytes of a word
transfer, independent of its byte alignment.
Host operations such as acknowledging an interrupt will
not release the local bus for several bus cycles.
Using a lock prefix in front of a host instruction
prevents the host from releasing the local bus during the
execution of thatinstruction.
8087 RQ/GT Function
iAPX 86/20, 88/20
For an 86/20 or 88120 just connect the RQ/GTO pin of
the 8087 to RQ/GTI of the host (see Figure 5), and skip
forward to the interrupt discussion on page 15.
iAPX 86/21, 88/21
For an 86/21 or 88121, connect RQ/GTO of the 8087 to
RQ/OTl of the host, connect RQ/GT of the 8089 to
RQ/OTl of the 8087 (see Figure 10, page 12), and skip
forward to the interrupt discussion on page 15.
The RQ/OTl pin of the 8087 exists to. provide one 1/0
processor with a low maximum wait time for the local
bus. The maximum wait times to gain control of the
local bus for a device attached to RQ/OTI of an 8087
for an 8086 or 8088 host are shown in Table 2. These
numbers are all dependent on when the host will release
the local bus to the 8087.
The presence of the 8087 in the RQ/OT path from the
lOP to the host has little effect on the maximum wait
time seen by the lOP when requesting the local bus. The
8087 adds two clocks of delay to the basic time required
by the host. This low delay is achieved due to a preemptive protocol implemented by the 8087 on RQ/OTl.
The 8087 always gives higher priority to a request for
the local bus from a device attached to its RQ/OTl pin
than to a request generated internally by the 8087. If the
8087 currently owns the local bus and a request is made
to its RQ/OTl pin, the 8087 will finish the current
memory cycle and release the local bus to the requestor.
If the request from the devices arrives when the 8087
does not own the local bus, then the 8087 will pass the
request on to the host via its RQ/OTO pin.
Table 2. Worst Case Local Bus Request Walt Times In
CIO~ks
System
Configuration
No Locked
Instructions
Only Locked
Exchange
iAPX86121
even aligned words
lSi
3S 1
max (lSI'
iAPX 86/21
odd aligned words
lSI
43 2
iAPX 88121
lSI
43 2
max (43 2• 0 )
max (43 2• 0 )
Notes: 1. Add two clocks for each wait state inserted per bus cycle
2. Add four clocks for each wait state inserted per bus cycle
• Execution time of longest locked instruction
Other Locked
Instructions
0)
AP·113
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(IOPA)
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IA
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8284A
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TRANSCEIVERS
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GENERATOR
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l -I-
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JIlllan
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BUS CONTROllER
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(lOPS)
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Figure 11. IAPX 86122 System
3-15
Ap·113
IAPX 86/22, 88/22
ditional clocks for an 8086 or 8088 respectively, for'the
equivalent save and restore operations. These operations appear in time-critical context-switching functions
of an operating system or interrupt hancller. This technique has no affect on the maximum wait time seen by
10PB or wait time seen by IOPA due to IOPB.
An 86/22 system offers two alternates regarding to
which lOP to connect an I/O device. Each lOP will offer a different maximum delay time to servide an I/O request. (See Fig. 11)
The second 8089 (IOPA) must use the RQ/GTO pin of
the host. With two lOPs the designer must decide which
lOP services which I/O devices, determined by the maximum wait time allowed between when an I/O device requests lOP service and the lOP can respond. The maximum service delay times of the two lOPs can be very
different. It makes little difference which of the two
host RQ/GT pins are used.
Which lOP to connect to which I/O device in an 86/22
or 88/22 system will depend on how quickly an I/O request by the device must be serviced by the lOP. This
maximum time must be greater than the sum of the
maximum delay of the lOP and the maximum wait time
to gain control of the local bus by the lOP.
If neither lOP offers a fast enough response time, consider remote operation of the lOP.
The different wait times are due to the non-preemptive
nature of bus grants between the two host RQ/GT pins.
No communication of a need to use the local bus is
possible between 10PA and the 8087/IOPB combination. Any request for the local bus by the 10PA must
wait in the worst case for the host, 8087, and 10PB to
finish their longest sequence of memory cycles. 10PB
must wait in the worst case for the host and 10PA to
finish their longest sequence of memory cycles. The
8087 has little effect on the maximum wait time of
IOPB.
8087 INT Connection
The next decision in adding the 8087 to an 8086 or 8088
system is where to attach the INT signal of the 8087.
The INT pin of the 8087 provides an external indication
of software-selected numeric errors. The numeric pro~
gram will stop until something is done about the error.
Deciding where to connect the INT signal can have important consequences on other interrupt handlers.
WHAT ARE NUMERIC ERRORS?
DELAY EFFECTS OF THE 8087
A numeric error occurs in the NPX whenever an operation is attempted with invalid operands or attempts to
produce a result which cannot be represented. If an incorrect or questionable operation is attempted bY,a program, ,the NPX will always indicate the event. Examples
of errors on the NPX are: I/O, square root of -I, and
reading from an empty register. For a detailed description of when the 8087 detects a numeric error, refer to
the Numerics Supplement. (See Lit. Ret).
The delay effects of the 8087 on 10PA can be significant. When executing special instructions (FSAVE,
FNSAVE, FRSTOR), the 8087 can perform SO or 96
consecutive memory cycles with an 8086 or 8088 host,
respectively. These instructions do not affect response
time to local bus requests seen by an IOPB.
If the 8087 is performing a series of memory cycles while
executing these instructions, and 10PB requests the
local bus, the 8087 will stop its current memory activity,
then release th~ local bus to IOPB.
WHAT TO DO ABOUT NUMERIC ERRORS
Two possible courses of action are possible when a
numeric error occurs. The, NPX can itself handle the
error, allowing numeric program execution to continue
undisturbed, or software in the host can handle the
error. To have the 8087 handle a numeric error, set its
associated mask bit in the NPX control word. Eacp
numeric error may be individually masked.
The 8087 cannot release the bus to 10PA since it cannot
know that IOPA wants to use the local bus, like it can
for IOPB.
REDUCING 8087 DELAY EFFECTS
For 86/22 or 88122 systems requiring lower maximum
wait times for IOPA, it is possible to reduce the worst
, case bus usage of the 8087. If three 8087 instructions are
never executed; namely FSA VE, FNSAVE, or
FRSTOR, the maximum number of consecutive memory cycles performed by the 8087 is 10 or 16 for an 8086
, or 8088 host respectively. The function of these instructions can be emulated with other 8087 instructions.
The NPX has a default fIXup action defined for all possible numeric errors when they are masked. The default
actions were carefully selected ,for their generality and
safety.
For example, the default fixup for the precision error is
to round the result using the rounding rules currently in
effect. If the invalid error is masked, the NPX will
generate a special value called indefinite as the result of
any invalid operation.
Appendix B shows an example of how these three instructions can be emulated. This improvment does have
a cost, in the increased execution time of 427 or 747 ad-
3-16
AP·113
NUMERIC ERRORS (CON'T)
The 8086 Family Numerics Supplement recommends
masking all errors except invalid. (See Lit. Ref.). In this
case the NPX will safely handle such errors as
underflow, overflow, or divide by zero. Only truly questionable operations will disturb the numerics program
execution.
Any arithmetic operation with an indefinite operand
will always generate an indefinite result. In this manner,
the' result of the original invalid operation will propagate throughout the program wherevC\" it is used.
When a questionable operation such as multiplying an
unnormal value by a normal value occurs, the NPX will
signal this occurrence by generating an unnormal result.
An example of how infinities and divide by zero can be
harmless occurs when calculating the parallel resistance
of several values with the standard formula (Figure 12).
If RI becomes zero, the circuit resistance becomes O.
With divide by zero and precision masked, the NPX will
produce the correct result.
The required response by host software to a numeric
error will depend on the application. The needs of each
application must be understood when deciding on how
to treat numeric errors. There are three attitudes
towards a numeric error:
NUMERIC EXCEPTION HANDLING
For some applications, a numeric error may not indicate
a severe problem. The numeric error can indicate that a
hardware resource has been exhausted, and the software
must provide more. These cases are called exceptions
since they do not normally arise.
1) No response required. Let the NPX perform the
default rump.
2) Stop everything, something terrible has happened!
3) Oh, not again! But don't disrupt doing something
more important.
Special host ·software will handle numeric error exceptions when they infrequently occur. In the~e cases,
numeric exceptions are expected to be recoverable
although not requiring immediate service by the host. In
effect, these exceptions extend'the functionality of the
NDP. Examples of extensions are: normalized only
arithmetic, extending the register stack to memory, or
tracing special data values.
SIMPLE ERROR HANDLING
Some very simple applications may mask all of the
numeric errors. In this simple case, the 8087 INT signal
may be left unconnected since the 8087 will never assert
this signal. If any numeric errors are detected during the
course of executing the program, the NPX will generate
a safe result. It is sufficient to test the final results of the
calculation to see if they are valid.
Special values like not-a-number (NAN), infinity, indefinite, denormals, and unnormals indicate the type
and severity of earlier invalid or questionable operations.
SEVERE ERROR HANDLING
For dedicated applications, programs should not generate or use any invalid operands. Furthermore, all numbers should be in range ..An operand or result outside
this range' indicates a severe fault in the system. This
situation may arise due to invalid input values, program
error, or hardware faults. The integrity of the program
and hardware is in question, and immediate action is required.
In this case, the INT signal can be used to interrupt the
program currently running. Such an interrupt would be
of high priority. The interrupt handler responsible for
numeric errors might perform system integrity tests and
then restart the system at a known,. safe state. The
handler would not normally return to the point of.error.
Unmasked numeric errors are very useful for testing
programs. Correct use of synchronization, (Page 21),
allows the programmer to find out' exactly what
operands, instruction, and memory values caused the
error. Once testing has finished, an error then becomes
much more serious.
Equivalent resistance =
Figure 12. Infinity Arithmetic Example
3-17
Ap·113
HOST INTERRUPT OVERVIEW
The host has only two possible interrupt inputs, a nonmaskable interrupt (NMI) and a maskable interrupt
.(INTR). Attaching the 8087 INT pin to the NMI input is
not recommended: The following problems arise: NMI
cannot be masked, it is usually reserved for more important functions like sanity timers or loss of power signal,
and Intel supplied software for the NDP will not support NMI interrupts. The INTR'input of the host allows
interrupt masking in the CPl], ·using an Intel 82S9A
Programmable Interrupt Controller (PIC) to resolve
multiple interrupts, and has Intel 'support.
'
NUMERIC INTERRUPT CHARACTERISTICS
Numeric error interrupts are different from regular instruction error interrupts like divide by zero. Numeric
interrupts from the 8087 can occur long after the
ESCAPE instruction that started the failing operation.
For example, after starting a numeric multiply operation, the host may respond to an external interrupt and
be in the process of servicing it when the 8087 detects an
overflow error. In this case the interrupt is a result of
some earlier, unrelated program.
From the point of view of the currently executing interrupt handler, numeric interrupts can cpme from only
two sources: the current hllndler or a lower priority program.
To explicitly disable numeric interrupts, it is recommended that numeric interrupts be disabled at the 8087.
The code example of Figure 13 shows how to disable
any pending numeric interrupts then reenable them at
the end of the handler.' This code example can be safely
placed in any routine which must prevent numeric interrupts from occurring. Note that the ESCAPE instructions act as NOPs if an 8087 is not. present in the system.
It is not recommended to use numeriy mnemonics sin<;e
they may be converted to emulator calls, which run
comparatively slow, if the 8087 emulator used.
Interrupt systems have specific functions like fast
response to external events or periodic execution of
system routines. Adding an 8087 interrupt should not
effect these functions. Desirable goals of any 8087 interrupt configuration are:
- Hide numeric interrupts from interrupt handlers that
don't use the 8087. Since they didn't cause the
numeric interrupt why should they be interrupttld?
- Avoid adding code to interrupt ,handlers that don't
use the 8087 to prevent interruption by the 8087.
- Allow other higher priority interrupts to be serviced
while executing a numeric exception handler.
- Provide numeric exception handling for interrupt
service routines which use the 8087.
- Avoid deadlock as described in a later section
(page 24)
Disable any possible numeric interrupt from the 8087. This code is safe to place in any
procedure. If an 8087 is not present, the ESCAPE instructions will act as nops. These
instructions are not affected by the TEST pin of the host. Using the 8087 emulator will not
convert these instructions into interrupts. A word variable, called control, is required to hold
the 8087 control word. Control must not be changed until it is reloaded into the 8087.
ESC
15, control
NOP
NOP
ESC 28,cx
; (FNSTCW) Save current 8087 control word
Delay while 8Q87 saves current control
register value
(FNDISI) Disable any 8087 interrupts
Set IEM bit In '8087 control register
The contents of cx Is Irrelevant
Interrupts can now be enabled
(Your Code Here)
Reenable any pending interrupts in the 8087. This instruction does not disturb any 8087 Instruction
'
currently in progress since all it does is change the \EM bit in the control registe~.
TEST control, 80H
JNZ $+4
ESC 28,ax
;. Lopk at .IE¥ bit
If IEM = 1 skip FNENI
(FNENI) reenable 8087 interrupts
Figure 13. Inhibit/Enable 8087 Interrupts
3-18
Ap·113
Recommended Interrupt Configurations
5. Case 4 holds except that interrupt handlers may
also generate numeric interrupts. Connect the 8087
INT signal to mUltiple interrupt inputs. One input
would still be the lowest priority input as in case 4.
Interrupt handlers that may generate a numeric interrupt will require another 8087 INT connection
to the next highest priority interrupt. Normally the
higher priority numeric interrupt inputs would be
masked and the low priority numeric interrupt
enabled. The higher priority interrupt input would
be unmasked only when servicing an interrupt
which requires 8087 exception handling.
Five categories cover most uses of the 8087 interrupt in
fixed priority interrupt systems. For each category, an
interrupt configuration is suggested based on the goals
mentioned above.
1. All errors on the 8087 are always masked.
Numeric interrupts are not possible. Leave the
8087 INT signal unconnected.
2. The 8087 is the only interrupt in the system. Connect the 8087 INT signal directly to the host's
INTR input. (See Figure 14 on page 19). A bus
driver supplies interrupt vector 1016 for compatibility with Intel supplied software.
All of these configurations hide the 8087 from all interrupt handlers which do not use the 8087. Only those interrupt handlers that use the 8087 are required to perform any special 8087 related interrupt control activities.
3. The 8087 interrupt is a stop everything event.
Choose a high priority interrupt input that will terminate all numerics related activity. This is a
special case since the interrupt handler may never
return to the point of interruption (i.e. reset the
system and restart rather than attempt to continue
operation) .
A conflict can arise between the desired PIC interrupt
input and the required interrupt vector of 1016 for compatibility with Intel software for numeric interrupts. A
simple solution is to use more than one interrupt vector
for numeric interrupts, all pointing at the same 8087 interrupt handler. 'Design the numeric interrupt handler
such that it need not know what the interrupt vector was
(i.e. don't use specific EOI commands).
4. Numeric exceptions or numeric programming errors are expected and all interrupt handlers either
don't use the 8087 or only use it with all errors
masked. Use the lowest priority interrupt input.
The 8087 interrupt handler should allow further
interrupts by higher priority events. The PIC's
priority system will automatically prevent the 8087
from disturbing other interrupts without adding
extra code to them.
If an interrupt system uses rotating interrupt priorities,
it will not matter which interrupt input is used.
3-19
AP·113
r--'
I
ADDRESS
rO_~
r---
READY
,----:.
RESET
CLOCK
GENERATOR
--
RESET
.-
elK
-- ..
....
STB
•
SYSTEM READY
1,1
AID
- -
l\f
t\
A
~
(218286
V
..,-;::lI
-V
DATA
TRANSCEIVERS
T
STATUS
8086
INTR
I--
fm
l-
RQfGT1
os
t
~~
RQ/GTO
=
T 8286
OE
I
Y
os
VECTOR
BUSY ' -
READY
INT
RESET
ALE
!---
~
1,1
8087
8288
~
elK
STATUS
H
,~
Dl/R
BUS
AID
CONTROLLER
V
INTA
~
STATUS
v
V
DEN
:r
elK
•
Figure 14. iAPX 86120 With Numerics Interrupt Only
•
ADDRESS
L.ATCHES
elK
READY
>--
~
-V
8284A
r-
(318282
3-20
OE
~i
i.-'I
I
I
I
I
,1 I DATA
~
~!
ISYSTEM
1
L!U~ .J
AP·113'
GETTING STARTED IN SOFTWARE
Concurrency Overview
Now we are ready to run numeric programs. Developing
numeric software will be a new experience to some programmers. This section of the application note is aimed
at describing the programming environment and providing programming guidelines for the NPX. The term
NPX is used to emphasize that no distinction is made
between the 8087 component or an emulated 8087.
With the NPX initialized, the next step in writing a
numeric program is learning about cOllcurrent execution
within the NDP.
Concurrency is a special feature of the 80S7, allowing it
and the host to simultaneously execute different instructions. The SOS7 emulator does not provide concurrency
since it is implemented by the host.
Two major areas of numeric software can be identified:
systems software and applications software. Products
such as iRMXTM 86 provide system software as an offthe-shelf product. Some applications use specially
developed systems software optimized to their needs.
The benefit of concurrency to an application is higher
performance. All Intel high'level languages automatically provide for and manage concurrency in the NDP.
However, in exchange for the added performance, the
assembly language programmer must understand and
manage some areas of concurrency. This section is for
the assembly language programmer or well-informed,
high level language programmer..
Whether the system software is specially tailored or
common, they share issues such as using concurrency,
maintaining synchronization between the host and 8087,
and establishing programming conventions. Applications software directly performs the functions of the
application. All applications will be concerned with initialization and general programming rules for ,the NPX.
Systems software will be more concerned with context
switching, use of the NPX by interrupt handlers, and
numeric exception handlers.
Whether the 80S7 emulator or component is used, care
should be taken by the assembly language programmer
to follow the rules described below regarding synchronization. Otherwise, the program may not function correctly with current or future alternatives for implementing the NDP.
Concurrency is possible in the NDP because both the
host and SOS7 have separate arithmetic and control
units. The host and' coprocessor automatically decide
who will perform any single instruction. The existence
of the SOS7 as a separate unit is not normally apparent.
How to Initialize the NPX
The first action required by the NPX is initialization.
This places the NPX in a known state, unaffected by
other activity performed earlier. This initialization is
similar to that caused by the RESET signal of the SOS7.
All the error masks are set, all registers are tagged
empty, the TOP field is set to 0, default rounding, precision, and infinity controls are set. The SOS7 emulator
requires more initialization than the component. Before
the emulator may be used, all its interrupt vectors must
be set to point to the correct entry points within the
emulator.
Numeric instructions, which will be executed by the
SOS7, are simply placed in line with the instructions for
the host. Numeric instructions are executed in the same
order as they are encountered by the host in .its instruction stream. Since operations performed by the SOS7
generally require more time than operations performed
by the host, the host can execute several of its instructions while the S087 performs one numeric operation.
To provide compatibility between the emulator and
component in this special case, a call to an external procedure should be used before the first numeric instruction. In ASMS6 the programmer must call the external
function INITS7. (Fig. 15). For PLMS6, the
programmer must call the built-in function
INIT$REAL$MATH$UNIT. PLMS6 will call INITS7
when executing the INIT$REAL$MATH$UNIT builtin function.
'
IN PLM86:
CALL INIT$REAL$MATH$UNIT;
IN ASM86:
EXTRN
•
•
•
•
The function supplied for INITS7 will be different,
depending on whether the emulator library, called
ES087.LIB, or component library, called SOS7.LIB,
were used at link time. INITS7 will execute either an
FNINIT instruction for the 8OS7 or initialize the SOS7
emulator interrupt vectors, as appropriate.
CALL
INIT87:FAR
INIT87
Figure 15. 8087 Initialization
3-21
AP·113
MANAGING CONCURRENCY
Instruction Synchronization
Concurrent execution of the host and 8087 is easy to
establish and maintain. The activities of numeric programs can be split into two major areas: program control and arithmetic. The program control part performs
activities like deciding what functions to perform, calculating addresses of numeric operands, and loop control.
The arithmetic part simply performs the adds, subtracts, multiplies, and other operations on the numeric
operands. The NPX and host are designed to handle
these two parts separately and efficiently.
Instruction synchronization is required because the 8087
can only perform one numeric operation at a time. Before any numeric operation is started, the 8087 must
have completed all activity from previous instructions.
Managing concurrency is necessary because the arithmetic and control areas must converge to a well-dermed
state when starting another numeric operation. A welldefined state means all previous arithmetic and control
operations are complete and valid.
Normally, the host waits for the 8087 to finish the current numeric operation before starting another. This
waiting is called syncb,ronization.
Managing concurrent execution of the 8087 involves
three types of synchronization: instruction, data, and
error. Instruction and error synchronization are
automatically provided by the compiler or assembler.
Data synchronization must be provided by the assembly
language progammer or compiler.
The WAIT instruction on the host lets it wait for the
8087 to finish all numeric activity before starting another numeric instruction. The assembler automatically
provides for instruction synchronization since aWAIT
instruction i~ part of most numeric instructions. A
WAIT instruction requires 1 byte code space and 2.5
clocks average execution time overhead.
Instruction synchronizati()n as provided by the assembler or a compiler allows concurrent operation in the .
NDP. An execution time comparison of NDP concurrency and non-concurrency is illustrated in Figure 16.
The non-concurrent program places aWAIT instruction
immediately after a multiply instruction ESCAPE instruction. The 8087 must complete the multiply operation before the host executes the MOV instruction on
statement 2. In contrast, the concurrent example allows
the host to calculate the effective address of the next
operand while the 8087 performs the multiply. The ex-·
ecution time of the concurrent technique is the longest
of the host's exec\1tion time from line 2 t05 and the execution time of the 8087 for a multiply instruction. The
execution time of the non-concurrent example is the
sum of the execution times of statements 1 to 5.
This code macro defines two instructions which do not allow any concurrency of execution with
; the host. A register version and memory version of the instruction is shown. It is assumed that the
; 8087 is always idle from the previous instruction. Allow space for emulator fixups.
,
R233 Record RF6:2, Mid3:3, RF7:3
CodeMacro NCMUL dst:T, src:F
RNfix OOOB
R233 (11 B, 001 B, src)
RWfix
EndM
CodeMacro NCMUL memop:Mq
RNfixM 100B, memop
ModRM 001 B, memop
RWfix
EndM
Statement
1
2
3
4
5
Concurrent
FMUL st(O), st(1)
MOV
ax, size A
index
MUL
MOV
bX,ax
FMUL A [bx]
Figure 16. Concurrent Versus Non·Concurrent Program
3-22
Non Concurrent
NCMUL st(O), st(1)
MOV
ax, size A
MUL
index
MOV
bx, ax
NCMULA [bx]
AP·113
Data Synchronization
Managing concurrency requires synchronizing data references by the host and 8087.
Figure 17 shows four possible cases of the host and 8087
sharing a memory value. The second two cases require
the FWAIT instruction shown for data synchronization.
In the first two cases, the host will finish with the
operand I before the 8087 can reference it. The
coprocessor interface guarantees this. In the second two
cases, the host must wait for the 8087 to finish with the
memory operand before proceeding to reuse it. The
FWAIT instruction in case 3 forces the host to wait for
the 8087 to read I before changing it. In case 4, the
FWAIT prevents the host from reading I before the
8087 sets its value.
'
The data synchronization purpose of any FWAIT or
. numeric instruction must be well documented. Otherwise, a change to the program at a later time may
remove the synchronizing numeric instruction, causing'
program failure, as:
FISTP
FMUL
MOV
AX,I
Case 1:
Obviously, the programmer must recognize any 'form of
the two cases shown above which require explicit data
synchronization. Data synchronization is not a concern
when the host and 8087 are using different memory
operands during the course of one numeric instruction.
Figure 16 shows such an example ofthe host performing
activity unrelated to the current numeric instruction
being executed by the 8087. Correct recognition of these
cases by the programmer is the price to be paid for providing concurrency at the assembly language level.
; I is safe to use
Case 3:
MOV
FILD
1,1
I
Case 2:
FILD
FWAIT
MOV
1,5
Case,4:
MOV A,X, I
FISTP I
FISTP
FWAIT
MOV
AX,I
Figure 17. Data Exchange Example
Automatic Data Synchronization
Two methods exist to avoid the need for manual recognition of when data synchronization is needed: use a
high level language which will automatically establish
concurrency and manage it, or sacrifice some performance for automatic data synchronization by the assembler.
This is a code macro to redefine the FIST
instruction to prevent any concurrency
whi·le the instruction runs. A wait
instruction is placed immediately after the
escape to ensure the store is done
before the program may continue. This
code macro will work with the 8087
emulator, automatically replacing the
wait escape with a nop.
When a high level language is not adequate, the
assembler can be changed to always place aWAIT instruction after the ESCAPE instruction. Figure 18
shows an example of how to change the ASM86 code
macro for the FIST instruction to automatically place
an FWAIT instruction after the ESCAPE instruction.
The lack of any possible concurrent execution between
the host and 8087 while the FIST instruction is executing
is the price paid for automatic data synchronization.
CodeMacro FIST memop: Mw
RfixM 111 B, me mop .
ModRM 010B, memop
RWfix
EndM
An explicit FWAIT instruction for data synchronization, can be eliminated by using a subsequent numeric
instruction. After this subsequent instruction has
started execution, all memory references in earlier
numeric instructions are complete. Reaching the next
host instruction after thesynchronizihg numeric instruction indicates previous numeric operands in memory are
availaole.
.
Figure 18. Non·Concurrent FIST Instruction
Code Macro
3-23
AP·113
DATA SYNCHRONIZATION RULES EXCEPTIONS
ERROR SYNCHRONIZATION FOR EXTENSIONS,
There are five exceptions to the above rules for data syn-'
. chroniiation. The 8087 automatically provides data synchronization for these cases. They are necessary to
avoid deadlock (described on page 24). The instructions
FSTSW IFNSTSW, FSTCW IFNSTCW, FLDCW,
FRSTOR, and FLDENV do not require any waiting by
the host before it may read or modify the referenced
memory location.
The NPX can provide a default flXUP for all numeric
errors. A program can mask each individual error type
to. indicate that the NPX should generate a safe, reasonable result. The default error flXUP activity is simply
treated as part of the instruction which caused the, error.
No external indication of the error will be given. A flag
in the numeric status register will be set to indicate that
an error was detected, but no information, regarding
where or when will be available.
The 8087 provides the data synchronization by prevent- .
ing the host from gaining control of the local bus while
these instructions execute. If the host cannot gain control of the local bus, it cannot change a value before the
8087 reads it, or read a value before the 8087 writes into
it.
The coprocessor interface guarantees that, when the
host executes one of these instructions, the 8087 will
immediately request the local bus from the host. This
request is timed such that, when the host finishes the
read operation identifying the memory operand, it will
always grant the local bus to the 8087 before the host
may use the local bus for a data reference while executing a subsequent instruction. The 8087 will not release
the local bus to the host until it has finished executing
the numeric instruction.
Error Synchronization
Numeric errors can occur on almost any numeric instruction at any time during its execution. Page 1S
describes how a numeric error may have many interpretations, depending on the application. Since the response to a numeric error will depend on the application, this section covers topics common to all uses of the
NPX. We will review why error synchronization is needed and how it is provided.
Concurrent execution of the host and 8087 requires synchronization for errors just like data references and
numeric instructions. In fact, the synchronization required for data and instructions automatically provides
error synchronization.
However, incorrect data or instruction synchronization
may not cause a problem until a numeric error occurs. A
further complication is that a programmer may not expect his numeric program to cause numeric errors, but
in some systems they may regularly happen. To better
understand these points, let's look at what can happen
when the NPX detects an error.
If the NPX performs its default action for all errors,
then error synchronization is never exercised. But this is
no reason to ignore error synchronization.
Another alternative exists to the NPX default fixup of
an error. If the default NPX response to numeric errors
is not desired, the host can implement any form of recovery desired for any numeric error detectable by the
NPX. When a numeric error is unmasked, and the error
occurs, the NPX will stop further execution of the
numeric instruction. The 8087 will signa). this event on
the INT pin, while the 8087 emulator will cause interrupt 1016 to occur. The 8087 INT signal is normally connected to the host's interrupt system. Refer fo page 18
for further discussion on wiring the 8087 INT pin.
Interrupting the host is a request from the NPX for
help. The fact that the error was unmasked indicates
that further numeric program execution under the arithmetic and programming rules of the NPX is unreasonable. Error synchronization serves to insure the NDP is
in a well defined state after an unmasked numeric error
occured. Without a well defined state, it is impossible to
figure out why the error occured.
Allowing a correct analysis of the error is the heart of
error synchronization.
NDP ERROR STATES
If concurrent execution is allowed, the state of the host
when it recognizes the interrupt is undefmed. The host
may have changed many of its internal registers and be
executing a totally different program by the time it is interrupted. To handle this situation, the NPX has special
registers updated at the start of each numeric instruction
to describe the state of the numeric proSram when the
failed instruction was attempted. (See Lit. Ref. p. iii)
Besides programmer comfort, a well-definedstate,is important for error recovery routines. They can change the
arithmetic and programming rules of the 8087. These
changes may redefine the default fixup from an error.
change the appearance of the NPX to the programmer,
or change how arithmetic is defined on the NPX ..
3-24
Ap·113
EXTENSION EXAMPLES
The BUSY signal will never go inactive during a numeric
instruction which asserts INT.
A change to an error response might be to automatically
normalize all denormals loaded from memory. A
change in appearance might be extending the register
stack to memory to provide an "infinite" number of
numeric registers. The arithmetic of the 8087 can be
changed to automatically extend the precision and range
of variables when exceeded. All these functions can be
implemented on the NPX via numeric errors and
associated recovery routines in a manner transparent to
the programmer.
The WAIT instructions supplied for instruction synchronization prevent the host from starting another
numeric instruction until the current error is serviced. In
a like manner, the WAIT instructions required for data
synchronization prevent the host from prematurely
reading a value not yet stored by the 801\7, or overwriting a value not yet read by the 8087.
The host has two responsibilities when handling
numeric errors. I.) It must not disturb the numeric context when an error is detected, and 2.) it must clear the
numeric error and attempt recovery from the error. The
recovery program invoked by the numeric error may
resume program execution after proper fixup, display
the state of the NDP for programmer action, or simply
abort the program. In any case, the host must do
something with the 8087. With the INT and BUSY
signals active, the 8087· cannot perform any useful
work. Special instructions exist for controlling the 8087
when in this state. Later, an example is given of how to
save the state of the NPX with an error pending. (See
page 29)
Without correct error synchronization, numeric
subroutines will not work correctly in the above situations.
Incorrect Error Synchronization
An example .of how some instructions written without
error synchronization will work initially, but fail when
moved into a new environment is:
FILD
INC
COUNT
COUNT
FSQRT
Three instructions are shown to load an integer, calculate its square root, then increment the integer. The
coprocessor interface of the 8087 and synchronous execution of the 8087 emulator will allow this program to
execute correctly when no errors occur on the FILD instruction.
Deadlock
But, this situation changes if the numeric register stack
is extended to memory on an 8087. To extend the NPX
stack to memory, the invalid error is unmasked. A push
to a full register or pop from an empty register will
cause an invalid error. The recovery routine for the error must recognize this situation, fixup the stack, then
perform the original operation.
The 8087 BUSY signal prevents the host from executing
further instructions (for instruction or data synchronization) while the 8087 waits for the host to service
the exception. The host is waiting for the 8087 to finish
the current numeric operation. Both the host and 8087
are waiting on each other. This situation is stable unless
the host is interrupted by some other event.
The recovery routine will not work correctly in the example. The problem is that there is no guarantee that
COUNT will not be incremented before the 8087 can interrupt the host. If COUNT is incremented before the
interrupt, the recovery routine will load a value of
COUNT one too large, probably causing the program to
fall. .
Deadlock has varying affects on the NDP's performance. If no other interrupts in the system are possible,
the NDP will wait forever. If other interrupts can arise,
then the NDP can perform other functions, but the affected numeric program will remain "frozen".
An \lndesirable situation may result if the host cannot
be interrupted by the 8087 when asserting INT. This situation, called deadlock, occurs if the interrupt path
from the 8087 to the host is broken.
SOLVING DEADLOCK
Finding the break in the interrupt path is simple. Look
for disabled interrupts in the following places: masked
interrupt enable in the host, explicitly masked interrupt
request in the interrupt controller. implicitly masked interrupt request in the interrupt controller due to a higher
priority interrupt in service, or other gate functions,
usually.in TTL, on the host interrupt signal.
Erro.r Synchronization and WAITs
Error synchronization relies on the WAIT instructions
required by instruction and data synchronization and
the INT and BUSY signals of the 8087. When an unmasked error occurs in the 8087, it asserts the BUSY
and INT signals. The INT signal is to interrupt the host,
while the BUSY signal prevents the host from destroying the current numeric context.
3-25
AP·113,
DEADLOCK AVOIDANCE
Application programmers should not be concerned with
deadlock. Normally" applications programs run with
unmasked numeric errors able to interrupt them. Deadlock is not possible in this case. Traditionally! Systems,
software or interrupt handlers may run with numeric interrupts disabled. Deadlock prevention lies in this do~ain. The golden rule to abide by is: "Never wait on the
8087 if an unmasked error is possible and the 8087 interrupt path may be broken."
Error Synchronization Summary
In summary, error synchronization involves protectill8
the state of the 8087 after an exception. Although not all
applications may initially require error synchronizatioll,
it is just good programming practice to follow the rules.
The advantage of being a "g~" numerics programmer is generality of your program so it can work in
other, more general environments.
Summary
Synchronization is the price for concurrency in the
NDP. Intel high level language compilers will automatically provide concurrency and manage it with synchronization. The assembly language programmer can
choose between using concurrency or not. Placing a
WAIT instruction immediately after any numeric instruction wiIJ prevent concurrency and avoid synchronization concerns.
The rules given above are complete and allow concurrency to be used to full advantage.
Synchronization and the Emulator
The above discussion on synchroniZation takes on
special meaning with the 8087 emulator. The 8087 emulator does not allow any concurrency. All numeric
operand memory references, error tests, and wait for
instruction completion occur within the emulator. As a
result, programs which do not provide proper instruction, data, or error synchronization may work with the
8087 emulator while failing on the component.
Correct programs for the 8087 work correctly on the
emulator.
Special Control Instructions of the NPX
The special control instructions of the NPX: FNINIT,
FNSAVE, FNSTENV, FRSTOR, FLDENV, FLDCW,
FNSTSW, FNSTCW, FNCLEX, FNENI, and FNDISI
remove sorne of the synchronization requirements mentioned earlier. They are discussed here since they represent exceptions to the rules mentioned on page 21.
The instructions FNINIT, FNSAVE, FNSTENV,
FNSTSW, FNCLEX, FNENI, and FNDISI do not wait
for the current numeric instruction to finish before theY
execute. Of these instructions, FNINIT,' FNSTSW,
FNCLEX, FNENI and FNDISI will produce different
results, depending on when they are executed relative to
the current numeric instruction.
For example, PNCLEX will cause a different status
value to result from a concurrent arithmetic operation,
depending on whether is is executed before or after the
error status bits are updated at the end of the arithmetic
. operation. The intended use of F:NCLEX is to clear a
known error status bit which has caused BUSY, to be
asserted, avoiding deadlock.
FNSTSW will safelY, without deadlock, repor:t the busy
and error status of the NPX independent of the NDP interrupt status.
FNINIT, FNENI, and FNDISI are used to place the
NPX into a known state independent of its current
state. FNDISI will prevent an unmasked error from
asserting BUSY without disturbing the current, error
status bits. Appendix A shows an example of using
FNDIS1.
The instructions FNSA VB and FNSTENV provide special functions. They allow saving the state of the NPX in
a single instruction when host interrupts are disabled.
Sev~ral host and numeric instructions are necessary to
save the NPX status if the interrupt status of the host is
unknown. Appendix A and B show examples of saving
the NPX state. As the Numerics Supplement explains,
host interrupts must always be disabled when executing
FNSAVE or FNSTENV.
The seven instructions FSTSWIFNSTSW, JLsave
General purpose save of NPX context. This function will work independent of the interrupt state of
the NDP. Deadlock can not occur. 47 words of memory are required by the variable save_area.
Register ax is not transparent across this code.
NP~save:
FNSTCW
NOP
FNDISI
MOV
FSAVE
ax, save_area
save_area
FWAIT
MOV
Save IEM bit status
Delay while 8087 saves control register
Disable 8087 BUSY signal
Get original control word
Save NPX context, the host can be safely interrupted while
waiting for the 8087 to finish. Deadlock is not possible since
IEM = 1.Wait for save to finish. Put original control word into
NPX context area. All done
Save the NPX context with host interrupts disabled. No deadlock is possible. 47 words of memory
are required by the variable save_area.
no_lnLN P~save:
FNSAVE
save_area
FWAIT
Save NPX context. Wait for save to finish, no deadlock
is possible. Interrupts may be enabled now, all done
N P>Lrestore .
Restore the NPX context saved earlier. No deadlock is possible if no further numeric instructions
are executed until the 8087 numeric error interrupt is enabled. The variable save_area is assumed
to hold an NPX context saved earlier. It must be 47 words long.
.
NP~restore:
FRSTOR
Load new N PX context
3-30
Ap·113
APPENDIX B
OVERVIEW
Appendix B shows alternative techniques for switching
the numeric context without using the FSAVEl
FNSAVE' or FRSTOR instructions. These alternative
techniques are slower than those of Appendix A ,but
they reduce the worst case continuous local bus usaae of
the 8087.
Only an iAPX 86/22 or iAPX 88/22 could derive any
benefit from this alternative. By replacing' all
FSAVE/FNSAVE instructions in the system, the worst
case local bus usage of the 8087 will be 10 or 16 consecutive memory cycles for an 8086 or 8088 host, respectively.
Instead of saving and loading the entire numeric context
in one long series of memory transfers, these routines
use the FSTENV/FNSTENV/FLDENV instructions
and separate numeric register load/store instructions.
Using separate load/store instructions for the numeric
registers forces the 8087 to release the local bus after
each numeric load/store instruction. The longest series
of back-to-back memory transfers required by these
instructions are 8/12 memory cycles for an 8086 or 8088
host, respectively. In contrast, the FSA VEl
FNSAVE/FRSTOR instructions perform 50/94 backto-back memory cycles for an 8086 or 8088 host.
Compatibility With FSAVElFNSAVE
This function produces a context area of the same format produced by FSAVE/FNSAVE instructionS. Other
software modules expecting such'a for-mat will not be
affected. All the same interrupt and deadlock considerations of FSAVE and FNSAVE also apply to FSTENV
and FNSTENV. Except for the fact that the numeric
environment is 7 words rather than the 47 words of the
numeric cont~t, all the discussion of Appendix A also
applies here.
The state of the NPX registers must be saved in memory
in the same format as the FSAVE/FNSAVE instructions. The program example starting at the label
SMALL-BLOCIC.NPX....8AVE illustrates a software
loop that will store their contents into memory in the
same top relative order as that of FSAVE/FNSAVE.
To save the registers with FSTP instructions, they must
be tagged valid, zero, or special. This function will force
all the registers to be tagged valid, independent of their
contents or old tag, and then save them. No problems
will arise if the tag value conflicts with the register's
content for the FSTP instruction. Saving empty registers insures compatibility with the FSAVEIFNSAVE instructions. After saving all the numeric registers, they
will all be tagged empty, the same as if an
FSAVE/FNSAVE instruction had been executed.
Compatibility With FRSTOR
Restoring the numeric context reverses the procedure
described above, as shown by the code starting at
SMALL-BLOCIC.NPXJWSTORE. All eight regissters are reloaded in the reverse, order. With each
register· load, a tag value will be assigned to each
register. The tags assigned by the register load does not
matter since the tag word will be overwritten when the
environment is reloaded later with FLDENV.
Two assumptions are required for correct operation of
the restore function: all numeric registers must be empty
and the TOP, field must be the same as that in the context being restored. These assumptions will be satisfied
if a matched set of pushes and pops were performed between saving the numeric context and reloading it.
If these assumptions cannot be met, then the code example starting at NP>L.CLEAN shows how to force all the
NPX registers empty and set the TOP field of the status
word.
3-31.
'J
,smaILbloc!LNPlLsave
;
;
;
;
Save the NPX context Jn~~pendent of NDP Interrupt state. Avoid using the, FSAVE instruction to
limit the worst case me'mol'y bus usage of the 8087. The NPX context area formed will appear the
same as If an FSAVE'lnstructlon had written Into It. 1h~ variable save_area will hold the NPX
context and must be 47 words long. The reglsters,ax, bX,and cx will not be transparent.
smaILblocILNP)Lsave:
FNSTCW save_area
NOP
FNDISI
ax, save_area
MOV
MOV
cx,8
XOR
bx, bx
FSTENV save_area'
FWAIT
XCtIIG
save_area + 4, bx
FLDENV save_area
save_area, ax
MOV
save_area 4, bx
MOV
bX,bx
XOR
; Save current IEM bit
;' Delay while 8087 saves control register
,; Disable 8087 BUSY signal
; Get original control word
; Set numeric register count
; Tag field value for stamping all registers as valid
; Save NPX environment
; Walt for the store to complete
; Get original tag value and set new tag value
; Force all register tags as valid. BUSY Is stili masked. No data
; synchronization needed. Put original control word Into NPX
; environment. Put original tag word ,Into NPX environment
; Set Inltlalreglst~r Index
+
reg_store_loop:
FSTP
saved_reg Lbxl
; Save register
,ADD
bx, type saved_reg
pointer to next register
LOOP
reg_store_l~op
; All done
; BUmp
NPlLclean
" ;
f •I
I
',!.
. , ,I,'
,
'.,
."
,~'
,
,; Force the NPX Into a clean state with TOP matching the TOP field stored In the NPX context and all
, i numeric registers tagged empt~. ,Sllve_~a must. be the NPX environment saved earlier.,:
; Temp_env Is a 7 word ~eITIPo~ry area .used to build a prototype NPX environment. Register ax will
; not be transparent.
NP)Lclean:
FINIT
~
Put NPX Into k'nown state
Get original status word
Mask out the top field
Format a temporary environment area with all registers
.
, stamped empty and TOP field O.
, Wait for the store to finish.
, Put in the desired TOP value.
'.j Sl!Itup new NPX environment.
; Now enter smalLbloclLNP)Lrestore
i'
AND
FSTENV
ax, saveJrea + 2 ,
ax,3800H"
,
temp_eny
FWAIT
OR
FLDENV
temp_env + 2, ax :
temp_env. ',"
MOV
,
',"
;
;
;
;
;
;
;'
=
,
Ap·113
smalLblocLNP>Lrastora
Restore the NPX context without using the FRSTOR instruction. Assume the NPX context Is'in the
same form as that created by an FSAVElFNSAVE instruction, all the registers are empty, and that
the TOP field of the NPX matches the TOP field of the NPX context. The variable save~~a must
; be an NPX context save area, 47 words long. The registers bx and cx will not be transparent.
smaILblocILNP)Lrestore:
MOV
cx,8
MOV
bx, type saved_reg*7
reg_load_loop:
FLO '
saved~reg [bx)
SUB
bx, type saved_reg
LOOP
reg_load_loop
FLOENV saveJrea
'; Set register count
Starting offset of ST(7)
Get the register
Bump pOinter to next register
Restore NPX context
; All done
APPENDIX C
OVERVIEW
Exception Considerations
Appendix C shows how floating point values can be
converted to decimal ASCII character strings. The function can be called from PLM/86, PASCAL/86, FORTRAN/86, or ASM/86 functions.
Care is taken inside the function to avoid generating exceptions. Any possible numeric value will be accepted.
The only exceptions possible would occur if insufficient
space exists on the numeric register stack.
Shortness, speed, and accuracy were chosen rather than
providing the maximum number of significant digits
possible. An attempt is made to keep integers in their
own domain to avoid unnecessary conversion errors.
The value passed in the numeric stack is checked for existence, type (NAN or infinity), and status (unnormal,
denormal, zero, sign). The string size is tested for a
minimum and maximum value. If the top of,the register
stack is empty, or the string size is too small, the function will return with an error code.
Using the extended precision real number format, this
routine achieves a worst case accuracy of three units in
the t6th decimal position for a non-integer value or integers greater than 1018• This is double precision accuracy. With,values having decimal exponents less than
100 in magnitude, the accuracy is one unit in the 17th
decimal position.
Overflow and underflow is avoided inside the function
for very large or very small numbers.
Special Instructions
The functions demonstrate the operation of several
numeric instructions; different data types, and precision
control. Shown are instructions for automatic conversion to BCD, calculating the value of 10 raised to an integer valuei establishing and maintaining concurrency,
data synchronization, and use of directed rounding on
the NPX.
Higher precision can be achieved with greater care in
programming, larger program size, and lower performance.
Func,tlon Partitioning
Three separate modules impletnent the conversion.
Most of the work of the conversion is done in the module FLOATING_TO-ASCII. The other modules are
provided separately since they have a more general use.
One of them, GETJOWELIO, is also 'used by the
ASCII to floating point conversion routine. The other
small module, TOS-llTATUS, will identify what, if
anything, is in the top of the numeric register stack.
Without the extended precision data type and built-in
exponential function, the double' precision accuracy of
this function could not be attained with the size and
speed of the shown example.
The function relies on the numeric BCD data type for
conversion from binary floating point to decimal. It is
3-33
AP·113
not difficult to unpack the BCD digits into separate
. ASCII decimal digits. The major work involves scaling
the floating point value to the comparatively limited
range of BCD values. To print a 9-digit result requires
accurately scaling the given value to an integer between
lOS and 109• For example, the number +0.123456789
requires a scaling factor of 109 to produce the value
+ 123456789.0 which can be stored in 9 BCD digits: The
scale factor must be an exact power of 10 to avoid to
changing any of the printed digit values.
Scaling the Value
. To scale the number, its magnitude must be determined.
It is sufficient to calculate the magnitude to an accuracy
of I unit, or within a factor of 10 of the given value.
After scaling the number, a check will be made to see if
the result falls in the range expected. If not, the result
can be adjusted one decimal order of magnitude up or
down. The adjustment test after the scaling is necessary
due to inevitable illaccuracies in the scaling value.
Since the magnitude estimate need only be close, a fast
technique is used. The magnitude is estimated by multiplying the power of 2, the unbiased floating point exponent, associated with the number by 10g102. Rounding
the result to an integer will produce an estimate of sufficient accuracy. Ignoring the fraction value can introduce a maximum error of 0.32 in the result.
These routines should exactly convert all values exactly
representable in decimal in the field size given. Integer
values which fit in the given string size, will not be
scaled, but directly stored into the BCD form. Noninteger values exactly representable in decimal within
the string size limits will also be exactly converted. For
example, 0.125 is exactly representable in binary or
decimal. To convert this floating point value to decimal,
the scaling factor will be 1000, resulting in 125. When
scaling a value, the function must keep track of where
tlie decimal point lies in the final decimal value.
Using the magnitude of the value and size of the number
string, the scaling factor can be calculated. Calculating
the scaling factor is the most inaccurate operation of the
conversion process. The relation'IOX = 2**(X*log21O) is
used for this function. The exponentiate instruction
(F2XM1) will be used. '
DESCRIPTION OF OPERATION
Converting a floating point number to decimal ASCII
takes three major steps: identifying the magnitude of
the number, scaling it for the BCD data type, and converting the BCD data type to a decimal ASCII string.
.
Due to restrictions on the range of values allowed by the
F2XMI instruction, the power of 2 value will be split into integer and fraction components. The relation
2"(1 + F) = 2**1 * 2"F allows using the FSCALE instruction to recombine the 2**F value, calculated
through F2XMI, and the 2**1 part.
'
Identifying the magnitude of the result requires finding
the value X such that the number is represented by
I*IOX, where 1.0 <= 1< 10.0. Scaling the number requires multiplying it by a scaling factor lOS, such that
the result is an integer requiring no more decimal digits
than provided for in the,ASCII string.
Inaccuracy in Scaling
The inaccuracy of these operations arises because of the
trailing zeroes placed into the fraction value when stripping off the integer valued bits. For each integer valued
bit in the power of 2 value separated from the fraction
bits, one bit of precision is lost in the fraction field due
to the zero fill occurring in the least significant bits.
Once scaled, the numeric rounding modes and BCD
conversion put the number in a form easy to convert to
decimal ASCII by host software.
Implementing each of these three steps requires atten·
tion to detail. To begin with, not all floating point
values have a numeric meaning. Values such as infinity,
indefinite, 'or Not A Number (NAN) may be encountered by the conversion routine. The conversion
routine should recognize these values and identify them
uniquely.
Up to 14 bits may be lost in the fraction since the largest
allowed floating point exponent value is 214 - 1.
AVOIDING UNDERFLOW AND OVERFLOW
Special Cases of numeric values also exist. Denormals,
unnormals, and pseudo zero all have a numeric value'
but should be recognized since all of them indicate that
precision was lost during some earlier calculations.
Once it has been determined that the number has a
numeric value, and it is normalized setting appropriate
unnormal flags, the value must be scaled to the BCD
range.
3-34
The fraction and exponent fields of the number are separated to avoid underflow and overflow,in calculating
the scaling values. For example, tei scale 10- 4932 to 108
requires a scaling factor of 104950 which cannot be represented by the NPX.
By separating .the exponent and fraction, the scaling
operation involves adding the exponents separate from
multiplying the fractions. The exponent arithmetic will
involve small integers, all easily represented by the
NPX.
'AP.113
FINAL ADJUSTMENTS
Output Format
It is possible that the Power function (OeLPower_lO)
,could produce a scaling value such that it forms a scaled
result larger than the ASCII field could allow.
For example, scaling 9.999999999999999ge4900
by 1.000OOOOOOOOOOOOlOe-4883 would produce
1.00000000000000018. The scale factor is within the
accuracy of the NDP and the result is within the conversion accuracy, but it cannot be represented in BCD format. This is why there is a post-scaling test on the
magnitude of the result. The result can be multiplied or
divided by 10, depending on whether the result was too
small or too large, respectively.
For maximum flexibility in output formats, the posit!on
of the decimal point is indicated by a binary integer
called the power value. If the power value is zero, then
the decimal point is assumed to be at the right of the
right-most digit. Power values greater than zero indicate
how, many trailing zeroes are not shown. For each Unit
below zero, move the decimal point to the left in the
string.
LINE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
211
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
The last step of the conversion is storing the result in
BCD and indicating where the decimal point lies. The
BCD string is then unpacked into ASCII decimal characters. The ASCII sign is set corresponding to the sign
of the original value.
SOURCE
$title(Convert a floating point number to ASCII)
name
floating to ascii
public floating-to-ascii
extrn
get_power_10:near,tos_status:near
This 'Subroutine will convert the floating point number in the
top of the B087 stack to an ASCII string and separate power of 10
scaling value (in binary). The maximum width of the Ascrt string
formed is controlled by a parameter which must be > 1. Unnorma1 values,
denorma1 values, and psuedo zeroes will be correctly converted.
A returned va1ue will indicate how many binary bits of
preciSion were lost in an unnormal or denorma1 value. The magnitude
(in terms of binary power) of a psuedo zero will also be indicated.
Integers less than 10**18 in magnitude are accurately converted if the
destination ASCII string field is wide enough to hold all the
digits. Otherwise the value is converted to scientific notation.
The status of the conversion is identified by the return value,
it can be:
o
1
2
3
4
conversion complete, string size is defined
invalid arguments
'exact integer conversion, string_size' is defined
indefinite
+ NAN (N<>t A Numbe r)
5
-
6
7
8
+ Infinity
- Infinity
psuedo zero found, string_size is defined
NAN
The PLM/86 calling convention is:
floating to ascii:
pro'cedure (number, denormal_ptr , str i ng _ptr , size _ptr, field _ si ze,
power-ptr) word external;
declare (denormal ptr,string ptr,power ptr,size ptr) pointer;
declare field size word, strfng size based size-ptr word;
decl.are number re,al;
declare denormal integer based denormal ptr;
declare power integer based power ptr;
end floating_to_ascii;
-
42
43
44'
45
46
47
48
The floating point value is expected to be on the top of the NPX
stack. This subroutine expects 3 free entries on the NPX stack and
will pop the passed value off when done. The generated ASCII string'
will have a leading character either '-' or '+' indicating the sign
of the value. The ASCII decimal digits will immediately follow.
The numeric value of the ASCII string is (ASCII STRING.)*10**POWER.
3-35
Ap·113
It the given number was zero, the ASCII string will contain a sign
and a single zero chacter. The value string size indicates the total
length of the ASCII string including the sign character. String(II) will
always hold the sign. It is possible for string size to be less than
field size. This occurs for zeroes or integer values. A psuedo zero
will return a, special return code. The denormal count will indicate
the power of two originally associated with the value. The power of
ten and ASCII string will be as if the value was an ordinary zero.
49
50
51
52
53
54
55
56
57
This sUbroutine is accurate up to a maximum, of 18 decimal digits for
integers. Integer values will have a decimal power of zero associated
with them. For non integers, the result will be accurate to within 2
decimal digits of the 16th decimal place (double precision). The
exponentiate instruction is also used for scaling the value into the
range acceptable for the BCD data type. The rounding mode in effect
on entry to the subroutine is used for the conversion.
~8
59
69
61
62
63
64
65
66
67
68
69
79
71
72
73
74
The following registers are not transparent:
ax bx cx dx si di flags
,
Define the stack layout. -
81
bp_save
es save
,:eturn"'ptr
power ptr
field-size
size ptr
str ing ptr
denormal_ptr
equ
equ
equ
equ
equ
equ
equ
equ
word ptr [bpJ
bp save + size bp_save
es-save + size es save
return ptr + size-return ptr
powerytr + size power ptr
field size + size fiel~ size
sizejPtr + size size_ptr
string_ptr + size string_ptr
82
83
parms_size
equ
84
&
size power ptr + size field size + size size_ptr +
size strinq_ptr + size denormal_ptr
85
86
87
;
'/5
76
77
78
79
89
88
89
99
91
92
93
94
95
96
,97
98
99
100
191
1112
1113
104
105
106
1117
1118
199
110
111
112
113
114
115
116
.111
118
Define constants used
BCD DIGITS
WORD tiIZE
BCD 1i"IZE
MINUS
NAN
INFINITY
INDEFINITE
PSUEDO ZERO
INVALiD
ZERO
DENORMAL
UNNORMAL
NORMAL
EXACT
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
18
Number of digits in bcd_value
2
HI
1
4
6
3
8
Define return values
The exact values chosen here are
important. They must correspond to
the possible return values and be in
the same numeric order as tested by
the program.
-2
-"4
-6
-8
II
2
Define layout of-temporary storage area.
status
power two
power-ten
bcd value
bcdbyte
fraction
equ
equ
equ
equ
equ,
equ
word ptr [bp-WORD I:iIZE]
status - WORD tiIZE
power two - W~RD tiIZE
tbyte-ptr power ten - BCD_tiIZE
byte ptr bed varue
bcd value
-
local size
&
-
equ
size status + size power two + size power ten
+ size bcd value
-
Allocate stack space for the temporaries so the stack will be big enough
stack
segment stack 'stack'
db
(10cal_size+6) dup (7)
3-36,
Ap·113
1211
121
122
123
124
125
126
127
128
129
1311
131
132
133
134
group
code
segment public 'code'
assume cs:cgroup
power_table:qword
extrn
cgroup
code
Constants used by this function.
; Opti~ize for 16 bits
; Adju~tment value ,for too big BCD
even
dw
constl11
111
Convert the C3,C2,Cl,CII encoding from
flags and values.
status table
db
tos_statu~
into, meanin<,ful bit
UNNORMAL, NAN, UNNORi"/lr: + "'I'lL'S, NM! + "I"'IIS,
I~FINITY,
NOR~AL
+ MINUS, INFINITY + MINUS,
135
~OR~AL.
136
ZERO, INVALiD, ZERO + MINUS, INVALID,
137
DENORMAL, INVALID, DENORMAL
+,~INUS,
INVALID
138
139
1411
call
mov
mov
cmp
jne
141
142
143
144
145
tos status
bx,ax
al,status table[bx]
al,INVALID
not_empty
Look at status of ST(II)
Get descriptor from table
Look for empty ST(II)
146
l;T(Il) is empty!
147
Return the status value.
148
149
1511
151
152
;
153
found_infinity:
Remove infinity from stack and exit.
154
fstp
jmp
155
156
157
l;tring space is too smalll
158
OK to leave fstp runninq
st(lI)
short ex! t_proc
Return invalid code.
159
1611
161
162
mov
al,INVALID
163
164
165
exit _proc:
mov
pop
pop
ret
166
167
168
169
178
171
172
173
174
Free stack space
Restore registers
sp,bp
bp
es
parms_size
ST(II is NAN or indefinite. Store the value in memory and look
at the fraction field to separate indefinite from an ordinary NAN.
;
NAN_or_indefinite:
175
176
117
178
179
fstp
test
fwait
jz
Remove value from stack for examination
Look at sign bit
Insure store is done
Can't be indefinite if positive
fraction
al,MINUS
exityroc
1811
3-37
AP·113
181
182
183
184
185
186
187
188
189
"190
1!11
192
193
194
195
196
197
198
199
2'Hl
21H
202
203
204
205
206
207
208
209
mov
sub
or
or
or '
jnz
bx,0C""IIH
bx,word ptr
bx,word ptr
bx,word ptr
bx,word ptr
exi t_proc
mov
jmp
al,INDEFINITE
exit_proc
fraction+6
fraction+4
fraction+2
fraction
Match against upper 16 bits of fiaction
Compare bits 63-48
Bits 32-47 must be zero
Bits 31-16 must be zero
Bits IS-II must be zero
Set return value for indefinite value
Allocate stack space for local variables and establish parameter
addressi bi 11 ty.
;
not_empty:
push
push
mov
sub
es
bp
bp,sp
sp,local_size
Save working register
mov
cmp
jl
cx,field size
cx,2
small_string
Check for enough string space
dec
cmp
jbe
cx
cx,BCD DIGITS
size OK
Adjust for sign character
See if string is too large for BCD
Establish stack addressibility
mov
Else set maximum string size
210
211
212
213
214
215
216
217
218
219
cmp
jge
al,INFINITY
found_infini ty
Look for infinity
Return status value for + or - info
cmp
jge
al,NAN
NAN or_indefinite
Look for NAN or INDEFINITE
Set default return values and check that the number is normalized.
2211
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
fabs
mov
xor
mov
mov
mov'
mov
cmp
jae
dx,ax
ax,ax
di,denormalytr
word ptr [dT] ,ax
bx,power ptr
word ptr-[bx] ,ax
dl,ZERO
real zero
cmp
jae
d 1 , DENORMAL
found denormal
Vse positive value only
sign bit in al has true sign of value
Save return value for later
Form II constant
Zero denormal count
Zero power of ten value
Test for zero
Skip power code if value is zero
Look for a denormal value
Handle it specially
fxtract
cmp
dl,UNNORMAL
jb
normal_value
sub
Separate exponent from significand"
Test for unnormal value
dl,UNNORMAL-NORMAL
; Return normal status with correct sIgn
Normalize the fraction, adjust the power of two in ST(l) and set
the denormal count value.
Assert: 0 <= ST(II) < 1.11
Load constant to normalize fraction
fldl
normalize_fraction:
fadd
st(l),st
fsub
flctract
Set integer bit in fraction
Form normalized fraction in ST(0)
Power of tvo field will be negative
of denormal count
Put denormal count in ST(0)
fxch
3-38
Ap·113
255
256
257
fist
faddp
word ptr [diJ
st (2) ,st
258
259
260
261
262
neg
jnz
word ptr [diJ
notJ'suedo_zero
Put negative,of denormal count in memory
Form correct power of two in stell
OK to use word ptr [diJ now
Form positive denormal count
A psuedo zero will appear as an unnormal number. When attempting
td normalize it, the resultant fraction field will be zero. Performing
an fxtract on zero will yield a zero exponent value.
263
264
265
266
267
fxch
fistp
word ptr [di J
sub
jmp ,
dl,NORMAL-PSUEDO ZERO
convert_integer -
268
269
270
Put power of two value in st(0)
Set denormal count to power of two value
Word ptr [diJ is not used by convert
integer, OK to leave runn'ng
Set return value saving the sign bit
Put zero value into memory
271
The number is a real zero, set the return value and setup for
conversion to BCD.
272
273
274
275
276
277
278
sub
jmp
dl,ZERO-NORMAL
convert_integer
; Convert status to normal value
; Treat the zero as an integer
279
280
281
282
283
284
,
The numb~r is a denormal. FXTRACT will not work correctly in this
case. To correctly separate the exponent and fraction, add a fixed
constant to the exponent to guarantee the result is not a denormal.
found_denormal:
285
286
fldl
fxch
fprem
287
288
Prepare to bump exponent
Force denormal to smallest representable
extended real format exponent
.
This will work correctly now
289
290
fxtract
291
292
293
294
The power of the original denormal value has been safely isolated.
Check if the fraction value is an unnormal.
295
fxam
fstsw
fxch
fxch
sub
test
jz
st(2)
dl,DENORMAL-NORMAL
status,441lllH
normalize fraction
See if the fraction is an unnormal
Save status for later
Put exponent in ST(0)
Put 1.0 into ST(Il), exponent in ST(2)
Return normal status with correct sign
See if C3=C2=0 impling unnormal or NAN
Jump if fraction is an unnormal
303
304
fstp
st (0)
Remove unnecessary 1.11 from st(ll)
305
Calculate the decimal magnitude associated with thi's number to
within one order. This error will always be inevitable due to
rounding and lost precision. As a result, we will deliberately fail
to consider ·the LOG10 of the fraction value in calculating the order.
Since the fraction will always be 1 c= F < 2, its LOGlll will not change
the basic accuracy of the function. To get the decimal order of magnitude,
simply multiply the power of two by LOGlll(2) and truncate. the. result to
an integer.
296
297
298
299.
3110
301
302
306
307
308
309
3HJ
311
312
313
;
314
normal value:
not_psuedo_zero:
315
316
317
318
319
3211
321
322
323
324
325
326
327
status
fstp
fist
fldlg2
fraction
power_two
fmul
fistp
power_ten
Save the fraction field for later use
Save power of two
Get LOGH! (2)
Power two is now safe to use
Form [0010(of exponent of number)
Any rounding mode will work here
Check if the magnitude of the number rules out treating it as
an integer.
CX has the maximum
numb~r
of decimal digits allowed.
3-39
•
328
329
331l
331
332
333
334
335
336
337
338
339
341l
fwaif
mov
sub
ja
The number is between 1 and lll**(field_size).
Test if it is an integer.
341
342
343
344
345
346
347
348
349
3511
351
352
353
354
355
356
357
358
359
361l
361
362
363
364
365
366
367
368
369
371!J
371
393
394
395
396
397
398
399
4Il1l
481
fUd
mov
sub
fld
fscale
fst
frndint
fcomp
fstsw
test
jnz
power two
si,dxdl,N9RMAL'-EXACT
fraction
fs~p
st(0)
dx,si
mov
Restore original number
Save return value
Convert to exact return value
Form full value, this is safe here
Copy value for compare
Test i~ its an integer
Compare values
Save status
C3=1 implies it was an integer
stell
status
status,41lliH1H
convert_integer
;
;
Remove non integer value
Restore original return value
Scale the num,ber to wi thin the range allowed by the 8CD format.
The scaling operation should produce a number within one decimal order
of magnitude of the largest decimal number representable within the
given string width.
The scaling power of ten value is in ax.
;
adjust_result:
372
373
374
375
376
377
378
379
388
381
382
383
384
385
386
387
388
389
390
391
392
Wait for power ten to pe valid
Get power of ten of value
Form scaling factor necessary in ax
Jump if number will not fit
ax,power_ten
ax,cx
adjust_result
,
mov
neg
word ptr [bx) ,ax
ax
call
get_power_lll
fld
fmul
mov
shl
shl
shl
fild
faddp
fscale
fslOp
fraction
Set initial power ot ten return value
Subtract one for each order of
magnitude the value is scaled by
Scaling factor is returned as exponent
and fr'act ion
Get fraction
Combine fractions
Form power of ten of the maximum
BCD value to fit in the string
Index in si
si,cx
si,l
si,l
si " 1
power_two
st(2) ,st
Combine powers of two
Form full value, exponent was safe,
Remove exponent
stO)
Test the adjusted value against a table of exact powers of ten.
The combined errors of the magnitude estimate and power function can
result in a value one order of magnitude too small or too large to fit
correctly in the BCD field. To handle this problem, pretest the
adjusted value, if it is too small or large, then adjust it by ten and
adjust the power ot ten value.
testyower:
fcom
fstsw
test
jnz
fidiv
, and
inc
jmp
power_table[si)+type power table; Compare against exact power
; entry. Use the next entry since cx
has been decremented by one
status
No wait is necessary
status,4lllllH
If C3 = CII = Il then too big
test for_small
-
constHJ
dl,not EXACT
word ptr [bx)
short in _range
Else adjust value
Remove exact flag
Adjust power of ten value
Convert the value to a BCD integer
power_table[si)
status
Test relative size
No wait is necessary
test _fo r_small:
fcom
fstsw
3-40
AP·113
402
403
4114
405
406
407
408
41')9
4111
411
412
413
414
415
416
417
418
status,11lJ0H
in_range
If C0 = II then st(0) )= lower bound
Convert the value to a BCD integer
fimul
dec
const10
word ptr [bx]
Adjust value into range
Adjust power of ten value
frndint
; Form integer value
Assert: " <= TOS <= 999,999,999,999,999,999
The TOS number will be exactly representable in 18 digit BCD format.
;
convert_integer:
fbstp
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
43"
437
438
439
.440
441
442
443
444
445
446
test
jz
Store as BCD format number
While the store BCD runs, setup registers for the conversion to
ASCII.
mov
mov
mov
mov
mov
mov
cld
mov
test
jz
si,BCD SIZE-2
cx,0f1J4'h
bx,l
di,string ptr
ax,ds
-
aI, '+'
dl,MINUS
positive_result·
mov
ai,
es,ax
457
458
459
460
461
462
463
464
Set autoincrement mode
Clear sign field
Look for negative value
'-'
positive_result:
stesb
and
fwa i t
~u~p strin~ pointer past sign
Turn off sign bit
Wait for fbstp to finish
dl,not MINUS
Register usage:
ah
al
dx
ch
cl
bx
si:
di:
ds,es:
447
448
449
450
451
452
453
454
455
456
Initial BCD index value
Set s~ift count and mask
Set initial size of ASCII field for sign
Get address of start of ASCII string
Copy ds to es
BCD byte value in use
ASCII character value
Return value
BCD mask = 0fh
BCD shift count = ~
ASClI string field width
BCD field index
ASCII string field pointer
ASCII string segment base
Remove leading zeroes from the number.
;
skip_leading_zeroes:
mov
mov
shr
and
jnz
ah,bcd byte lsi]
al,ah al,cl
al,ch
enter odd
Get BCD byte
Copy value
Get high order digit
Set zero flag
Exit loop if leading non zero found
mov
and
jnz
al,ah
al,ch
enter _even
Get BCD byte again
Get low order digit
Exit loop if non zero digit found
dec
jns
si
skip_leading_zeroes
Decrement BCD index
465
466
467
468
469
470
471
472
473
474
The significand was all zeroes.
mov
stosb
inc
jmp
aI, .,,.
Set initial zero
bx
short exit_with_value
Bump string length
3~41
,.
AP·113
475
476
NOW expand the BCD string into digit per byte values 0-9.
477
478
479
482
483
484
485
486
ah,bcd byte (si]
al,all al,cl
mov
mov
shr
48~
481
Get BCD byte
Get high order digit
enter_odd:
488
489
498
,;;;,.
aI, 'Il'
add
stosb
mov
and
inc
487
al,ah
al,ch
bx
Convert to ASCII
Put digit into ASCII string area
Get low order digit
Bump field size counter
491
492
493
enter _even:.
add
stosb
inc
dec
jns
494
495
496
497
498
499
bx
si
digit_loop
Conversion complete.
50~
501
502
Convert to ASCII
Put digit into ASCII area
Bump field size counter
Go to next BCD byte
al,'0 •
Set the string size and remainder.
;
exit_with_value:
5~3
504
mov
mov
mov
jmp
5~5
506
507
508
509
5H1
di ,size ptr
word Ptr (di],bx
ax,dx
.exit_proc
floating to ascii
code
--
511
Set return value
endp
ends
end
ASSEMBLY COMPLETE, NO ERRORS FOUND
LINE
1
SOURCE
Stitle(Calculate the value of 10**ax)
2
Tllis subroutine will calculate the value of 10**ax.
All 8086 registers are transparent and the value is returned on
the TOS as two numbers, exponent in STIll and fraction in ST(0).
The exponent value can be larger than the maximum representable
exponent. TIISee stack entries are used.
3
4
5
6
7
8
9
HI
11
name
public
12
13
stack
14
15
16
stack
17
18
19
20
21
22
23
cgroup
'code
get power 10
get~power~lll,power_table
segment stack 'stack'
dw
4 dup (?)
Allocate space on the stack
group
code
segment .public 'code'
assume cs:cgroup
Use exact values from 1.0 to Ie Ii.
Optimize 16 bit access
'., even
dq
1.0,lel,1e2,le3
3-42
AP·113
24
dq
le4,le5,le6,le7
25
dq
le8,le9,le10,lell
26
dq
le12,le13,le14,le15
27
dq
le16,le17,le18
28
29
30
get_power_10
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
62
63
64
65
66
67
68
69
10
71
ax,18
out_of_range
push
mov
shl
shl
shl
fld
pop
fxtract
ret
bx
bx,ax
bx,l
bx,l
bx,l
power table[bx]
bx-
Test for 0 <- ax < 19
Get working index register
I Form taMe index
Get exact value
Restore register value
Separate power and fraction
OK to leave fxtract running
Calculate the value using the exponentiate instruction.
The following relations are used:
10**x = 2**(log2(10)*x)
2**(I+F) • 2**I * 2**F
if still .. 1 and st(0) .. 2**F then fscale produces 2**(I+F)
46
47
4,8
49
50
51
52
53
54
55
56
57
58
59
60
61
proc
cmp
ja
;
out_of_range:
fldl2t
push
mov
push
push
fimul
fnstcw
bp
bp,sp'
ax
ax
word ptr [bp-2]
word ptr [bp-4]
mov
and
or
xchg
ax,word ptr [bp-4)
ax,not 0C00H
ax , 041111'H
ax,word ptr [bp-4]
fldl
fchs
fld
fldcw
,frndint
mov
fldcw
TOS .. LOG2(10)
Establish stack addres'sibility
Put power (P) in memory
Allocate space for status
TOS,X • LOG2(l0)*P .. LOG2(10**P)
Get current control word
Control word is a static value
Get control word, no wait necessary
Mask off current rounding field
Set round to negative infinity
; Put new control word in memory
old control word is fn ax
Set TOS .. -1.8
st (1)
word ptr [bp-4)
Copy power value in base two
Set new control word value
TOS" I:,-inf < I <= X, I is an integer
Restore original rounding control
word ptr [bp-4],ax
word ptr [bp-4)
3-43
AP·11'3
72
73
74
75
76
77
78
fxch
pop
fsub
pop
fscale
f2xml
pop
fsubr
fmul
ret
79
811
81
82
83
84
85
get power III
code
-
st(2)
ax
st,st(2)
ax
I
bp
st,st(II)
TOS = X, ST (l) = -loll, ST(2) = I
Remove original control word
TOS,F = X-I: " <= TOS < 1."
Restore power of ten
TOS = F/2: " <= TOS < Il.S
TOS = 2**(F/2) - 1.1l
Restore stack
Form 2** (F/2)
Form 2**F
OK to leave fmul running
endp
ends
end
ASSEMBLY COMPLETE, NO ERRORS FOUND
LINE
1
SOUHCE
$title(Determine TOS register contents)
2
3
4
5
6
7
8
9
II!
11
This subroutine will return a value from Il-15 in ax corresponding
to the contents of 81187 TOS. All registers are transparent and no
errors are possible. The return value corresponds to c3,c2,cl,cll
of FXAM instruction.
name
public
stack
segment stack "stack'
dw
3 dup (?)
12
13
tos status
tos-status
stack
ends
cgroup
code
group
code
segment public 'code'
assume cs:cgroup
proc
Allocate space on the, stack
l4
15
16
17
18
19
29
21
22
23
24
25
26
27
28
29
311
31
32
33
34
35
36
37
38
tos_status
fxam
push
push
mov
fstsw
pop'
pop
mov
and
shr
shr
shr
or
mov
ret
ax
bp
bp,sp
word ptr [bp+2J
bp
ax
al,ah
ax,4",,,,7h
ah,l
ah,l
ah,l
'al,ah
ah,lI
Get register contents status
Allocate space for status value
Establish stack addressibility
Put tos status in memory
Restore registers
Get status value, no wait necessary
Put, bit 111-8 into bits 2-0
Mask out bits c3,c2,cl,cll
Put bit c3 into bit 11
Put c3 into bit 3
Clear return value
tos st,atus
code
ASSEMBLY COMPLETE, NO ERRORS FOUND
3-44
AP·113
APPENDIX D
code simply determines ihe meaning of each character
encountered. Two separate number inputs must be recognized, mantissa and exponent values. Performing the
numerics operations is very straightforward.
OVERVIEW
Appendix D shows a function for converting ASCII
input strings into floating point values. The returned
value can be used by PLM/86, PASCAL/86, FORTRAN/86, or ASM/86. The routine will accept a number in ASCII of standard FORTRAN formats. Up to 18
decimal digits are accepted and the conversion accuracy
is the same as for converting in the other direction.
Greater accuracy can also be achieved with similar
tradeoffs, as mentioned earlier.
The length of the number string is determined first to
allow building a BCD number from low digits to high
digits. This technique guarantees that an integer will be
converted to its exact BCD integer equivalent.
If the number is a floating point value, then the digit
string can be scaled appropriately. If a decimal point oc-
curs within the string, the scale factor must be decreased
by one for each digit the decimal point is moved to the
right. This factor must be added to any exponent value
specified in the number.
Description of Operation
COllverting from ASCII to floating point is less complex
numerically than going from floating point to ASCII. It
consists of four basic steps: determine the size in decimal digits of the number, build a BCD value corresponding to the number string if the decimal point were
at the far right, calculate the exponent value, and scale
the BCD value. The first three steps are performed by
the host software. The fourth step is mainly performed
by numeric operations.
ACCURACY CONSIDERATIONS
All the same considerations for converting floating
point to ASCII apply to calculating the scaling factor.
. The accuracy of the scale factor determines the accuracy
of the result.
The exponents and fractions are again kept separate to
prevent overflows or underflows during the scaling
operations.
The complexity in this function arises due to the flexible
nature of the input values it will recognize. Most of the
LINE
1
2
3
SOURCE
$title(ASCII to floating point conversion)
Define the publicly known names.
4
5
6
7
8
'J
10
11
12
13
name
public
extrn
ascii to floating
ascii-to-floating
get-power_10:near
This function will convert an ASCII character string to a floating
point representation. Character strings in integer or scientific form
will be accepted. The allowed format is:
'
[+,-) [digit(s)] [.) [digit(s)) [E,e) [+,-:-Udigit(s)j
14
15
16
17
18
19
20
21
22
23
Where a digit 'must have been 'encountered before the exponent
indicator 'E' or'e'. If a '+', "-', or '.'was'encountered, then at
least one digit must exist before the optional exponent field. A value
will always be returned in the 8087 stack. In case of invalid numbers,
values like indefinite or infinity will be returned.
The first character not fitting within the format will terminate the
conversion. The address of the terminating character will be returned
by this subroutine.'
24
25
26
27
28
29
30
31
32
33
The result will be left on the top of· the NPX stack. This
subroutine expects 3 free NPX stack'registers. The sign of the result
will correspond to any sign characters in the ASCII string. The rounding
mode in effect at the time the subroutine was called will be used for
the conversion from b~se 10 to base 2. Up to 18 significant decimal
digits may ~ppear in the number. Lea~inn ze~o~s. t~~ilinn zeroes, or
exponent digits do not count towards the 18 digit maximum. Integers
or exactly representable decimal nu~bers of 18 digits or less will be '
exactly converted. The technique used constructs a BCD number
3-45
AP·113
34
35
36
representing the significant ASCII digits of the string with the decimal
point removed.
An attempt is made to e~actly convert relatively small integers or
small fractions. For example the values: .96125, 123456789912345678,
le17, 1.23456e5, and 125e-3 will be exactly converted to floating point.
The exponentiate instruction is ~sed to scale the generated BCD va slue
to very large or very small numbers. The basic accuracy of this function
determines the accuracy of this subroutine. 'For very large or very small
numbers, the accuracy of this function is 2 units in the 16th decimal
place or double precision. The range of decimal powers accepted is
10-*-4930 to 19**4939.
37
38
39
411
41
42
43
44
45
46
47
48
49
511
The PLM/86 calling' format is:
ascii to floating:
- procedure (string ptr,end ptr,status ptr) real external;
declare (string ptr,end ptr,status ptr) pointer;
declare end based end ptr pointer;declare status based status ptr word;
end;
!II
52
53
54
55
)6
The status value has 6 possible states:
57
58
59
611
61
62
63
64
65
9
1
2
3
4
The following registers are used by this subroutine:
ax
66
67
68
69
79
71
72
73
74
75
76
77
78
79
89
81
82
83
84
85
86
87
88
89
99
91
92
93
94
95
96
97
98
99
Hl0
191
1Il2
Hl3
194
Hl5
196
197
A number was found.
No number was found, return indefinite.
Exponent was expected but none found, return indefinite.
Too many digits were found, return indefinite.
Exponent was too big, return a signed infinity.
,
bx
dx
si
di
Define constants.
LOW EXPONENT
HIGH EXPONENT
WORD-~IZE
BCD)rIZE
,
cx
equ
equ
equ
equ
-4939
4939
Smallest allowed power of 10
Largest allowed power of 111
2
HI
Define the parameter layouts involved:
bp save
return ptr
s'tatus-ptr
endytr
string_ptr
equ
equ
equ
equ
equ
word ptr [bp)
bp save + size bp save
return ptr + size-return ptr
status-ptr + size status-ptr
endytr + size end_ptr -
parms _si ze
equ
size status_ptr + size endytr + size string_ptr
Define the local variable data layouts
power ten
'bed form
equ
equ
word ptr [bp- WORD SIZE) ; power of ten value
tbyte ptr power_ten '- BCD_SIZE; BCD representation
equ
size power_ten + size bed form
Define common expressions used
bcd byte
bcd-count
bcd-sign
bCd:sign_bi t
equ
equ
equ
equ
byte ptr bed form
(type(bcd form)-1)*2
byte ptr bcd form + 9
89H
-
Current byte in the BCD form
Number of digits in BCD form
Address of BCD sign byte
;
.
Define return values.
NUMBER FOUND
equ
NO _NUMB:ER
equ
NO EXPONENT
equ
TO~ MANY DIGITS equ
EXPONENT-TOO BIG equ
Number wa,s found
No number was found
No e,xponent was found when expected
Too many digits were found
Exponent was too big
3-46
Ap·113
Hl8
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
Allocate stack space to insure enough exists at run time.
;
stack
segment stack 'stack'
db
(local_size+4) dup (?)
stack
ends
cgroup
code
group
code
segment public 'code'
assume cs:cgroup
Define some of the possible return values.
even
dd
dd
indefinite
infinity
ascii to_floating proc
fldz
push
mov
sub
Prepare to zero BCD value
Save callers stack environment
Establish stack addressibility
Allocate space for local variables
bp
bp,sp
sp,loca1_size
Get any leading sign character to form initial BCD template.
mov
xor
cld
si,string ptr
dx,dx
-
Get starting address of the number
Set initial decimal digit count
'Set auto increment mode
Register usage:
al:
cx:
dx:
si:
14 I!
141
142
143
144
145
146
147
148
Current character value being examined
Digit count before the decimal point
Total digit count
Pointer to character string
Look for an initial sign and skip it if found.
149'
1511
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
Optimize 16 bit access
Single precision real for indefinite
Single precision real for +infinity
0FFC0",,00R
07FF81!IIIHIIR
lodsb
cmp
jz
al,I+'
cmp
jnz
aI, '_I
enter_leading_digits
Get first character
Look for a sign
\
scan_leading_digits
fchs
If not "-" test current character
Set TOS
= -0
Count the number of digits appearing before an optional decimal point.
;
scan_leading_digits:
lodsb
call
jnc
Get next character
test dig i.t
scan:leading_digits
; Test for digit
~nd
bump counter
Look for a possible decimal point and start fbstp operation.
The fbstp zeroes out the BCD value and sets the correct sign.
fbstp
mov
cmp
jnz
Set initial sign and value of BCD number
Save count of digits before decimal point
bcd form
cx,dx
aI, .•.
testJor_digits
Count the number of digits appearing after the decimal point.
;
scan_trailing_digits:
~ook
iodsb
3-47
at next character
AP~113
188
181
182
183
184
185
call
jnc
test digit
scan:trailing_digits
; Test for digit and bump counter
There must be at least one digit counted at this point.
;
test_for_digits:
186~
187
188
189
198
191
192
193
194
195
196
197
si
dx,dx
no:..number _found
Put si back on terminating character
Test digit count
Jump if no digits were found
push
dec
si ,
st.
Save pointer to terminator
Backup pointer to last digit
Check that the number will fit in the 18 digit BCD format.
CX becomes the initial scaling factor to account for the implied
decimal point.
198
199
2811
2111
282
2113
2114
285
"286
287
288
289
218 .
211
212
213
214
215
216
217
218
219
228
dec
or
jz
sub
cx,dx \
neg
dx
cmp
jb
dx,-bcd count
test_foF_unneeded_digits
For each digit to the right of the
decimal point, subtract one from the
initial scaling power
Use negative digit count so the
test_digit routine ca~ count dx up
to zero
; See i f too many digits found
Setup initial register values for scanning· the number right to left
while building the BCD value in memory.
;
form bcd val,ue:
"
-
std
mov
xor
mov
fwa i t.
jmp
Set autodecrement mode
Set initial power of ten
Clear BCD number index
Set digit shift count
Ensure BCD store is done
power ten,cx
di ,dicl,4
enter digit loop
f
-
-
No digits were encountered before testing for the exponent.
Restore the string pointer and return an indefinite value.
221
222
223
224
225
226
227
mov
fld
jmp
228
229
231l
231
232
233
234
235'
236
237
238
239
248
241
242
243
244 .
245
246
247
248
249
258
251
252
253
ax,NO NUMBER
indefrnite
exit
Set return status
Return an indefinite numeric value
Test for a number of.the form ???1I1I1l1l8.
;
test_terminat! ng_point:
lodsb
cmp
jz
aI,'.'
enter-power_zeroes
Get last character
Look for decimal point
Skip forward if found
inc
jmp
si
short enter_power_zeroes
Else bump pointer back
Too many dec,imal digits encountered. Attempt to remove leading and
trailing d'g~ts to bring the total into the boundS of the BCD format.
test_for_unneeded_digits:
std
or
cx,cx
jz
test terminatinq_point
Set autodecrement mode
See if any digits appeared to the
right of the decimal point
Jump if none exist
dec'
dx
Adjust diqit counter for loop
Scan backwards from the right skipping trailing zeroes.
If the end of the number is encountered,'dx=9, the string consists of
all zeroesl
3-48
Ap·113
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
;
skip_trailing_zeroes:
inc
jz
lodsb
inc
cmp
jz
dx
look_for_exponent
Bump digit count
Jump if string of zeroes found I
cx
Get next character
Bump power value for each :trailing
zero dropped,
aI,
I",
skip_trailing_zeroes
dec
cmp
jnz
cx
aI, •••
scan_leading_zeroes
Adjust power counter from loop
Look for decimal point
Skip forward if none found
dec
dx
Adjust counter for the decimal point
The string is, of the form: ????9900000
See if any zeroes exist to the left of the decimal point.
;
enter_power_zeroes:
dec
dx
Adjust digit counter for loop
inc
jz
dx
look_fo r_exponent
Bump digit count
lodsb
inc
cmp
jz
cx
Get next character
Bump power value for each trailing
zero dropped
dec
aI, ." I
skip_power_zeroes
cx
; Adjust power counter from loop
Scan the leading digits from the left to see if they are zeroes.
,
scan_leading_zeroes:
lea
cld
mov
lodsb
di,byte ptr [si+l]
Save new end of number pointer
Set autoinc-rement mode
Set pointer to the start
Look for sign character
cmp
aI, '+'
je
skip_leading zeroes
cmp
al,f-'
jne
enter_leading_zeroes
300
301
392
393
304
395
Drop leading zeroes. None of them affect the power value in cx.
We are guarenteed at least one non zero digit to terminate the loop.
306
,
307
308
skip_leading_zeroes:
31'19
310
311
312
313
314
315
316
317
318
319
lodsb
320
321
322
323
324
325
326
327
Get next character
enter_leading zeroes:
inc
cmp
jz
dx
a1, .".
dec
cmp
jnz
dx
a1,· . •
test_digit_count
Bump digit count
Look for a zero
~kip_Ieading_zeroes
Adjust digit count from loop
Look tor 000.??? form
Number is ot the form 001l.????
Drop all leading zeroes with no effect on the power value.
;
skip middle zeroes:
-r
inc
lodsb
dx
3-49
Remove the digit
Get next character
Ap·113
328
329
339
331
332
333
334
335
336
'337
338
339
349
341
342
343
344
345
346
347
348
349
3511
351
352
353
354
355
356
357
358
359
369
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
389
381
382
383
384
385
386
387
388
389
391t
391
392
393
394
395
396
397
398
399
41!11!1
41!11
cmp
jz
aI, 'II'
skip_middle_zeroes
dec
dx
; Adjust digit count from loop
All superflous zeroes are removed.
Check if all is well now.
;
test_digit_count:
cmp
jb
dX,-bcd count
too_many_digits_found
mov
jmp
si ,di
form_bcd_value
Rewtore string pointer
fld
mov
pop
jmp
indefinite
ax,TOO MANY DIGITS
si
exit
Set return numeric value
Set return flag,
Get last address
Build,BCD form of the decimal ASCII string from right to left with
trailing zeroes and decimal point removed. Note that the only non
digit possible is a decimal point which can be safely ignored.
Test digit will correctly count dx back towards zero to terminate
the BCD build function.
;
get_digit_loop:
lodsb
,call
jc
test d'iglt
get_digi t_Ioop
Get next character
Check if digit and bump digit count
Skip the decimal point if found
shl
or
mov
inc
or
jz
al,cl
ah,a1
bcd byte[dij ,ah
di dx,dx
look_for_exponent
Put digit into high nibble
Form BCD byte in ah
Put into BCD string
Bump BCD pointer '
Check if digit is available
enter _digi t_loop:
lodsb
ca11
jc
test digit
enter_digi t'_loop
Get next character
Check 1f diqit
Skip the de~imal point
mov
or
jnz
ah',al
dx,dx
get_digit_Ioop
Save digit
Check 1f digit is available
mov
bcd_byte [dl] ,ah
Save last odd digit
Look for an exponent indicator.
;
look_for_exponent:
pop
cld
mov
lodsb
cmp
je
si
cmp
jne
al,'E'
convert
Restore string pointer
Set autoincrement direction
Get current power, of ten
Get next character
Look for expo~ent indication
aI, 'e'
exponent_found
An exponent is expected, get its numeric value.
;
exponent..:found:
lodsb
xor
mov
Get n'ext character
Clear power variable
Clear exponent sign flag and digit f,lag
di,di
cx,di
3-50
Ap·113
402
403
4114
405
406
cmp
je
aI, '+'
skip_power_sign
Test for positive sign
cmp
jne
aI, I _ I
enter_power_loop
Test for negative sign
407
The exponent is 'negative.
408
409
410
411
412
inc
413
414
ch
Set exponent sign flag
Register usage:
415
416
417
all
bx:
ch:
cl:
dx:
si:
di:
418
419
420
421
422
exponent character being examined
return value
exponent sign flag
0 positive, 1 negative
digit flag
0 no digits found, 1 digits found
not usable since test digit increments it
string pointer
binary value of exponent
423
424
425
426
Scan off exponent digits until a non-digit is encountered.
power _loop:
427
428
429
430
lodsb
Get next character
enter _power_loop:'
431
432
433
434
mov
call
jc
ah,0
test digit
form:power_value
mov
sal
add
sal
sal
add
cmp
jna
cl,l
Set power digit flag
di ,1
01d*2
ax,di
0Id*2+digit
di,l
01d*4
di,l
01d*8
di ,ax
; old*Hl+digit
di,HIGH EXPONENT+bcd_count; Check if exponent is too big
power_loop
Clear ah since ax is added to later
Test tor a digit
Exit loop if not
435
436
437
438
439
440
441
442
443
444
The exponent is too large.
445
446
447
exponent_ verflow:
448
4511
451
mov
fld
test
452
jz
ax,EXPONENT TOO BIG
infinity
bcd sign,bcd sign bit
exit
--
fchs'
jmp
short exit
449
453
454
455
456
457
458
;
459
no_exponent_found:
460
Set return value
Return infinity
Return correctly signed infinity
JUmp if not
Return -infinity
NO exponent was found.
461
dec
mov
fld
jmp
462
463
464
si
ax,NO EXPONENT
indeffnite
short exit
Put si back on terminating character
Set return value
Set number to return
465
466
467
468
469
4711
,
The string examination is complete.
form_power_value:
dec
si
473
rcr
jnc
ch,l
positive_exponent
474
475
neg
di
471
472
Form the correct power of ten.
Backup string pointer to terminating
character
T~st exponent sign flag
Force exponent negative
3-51
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
5113
5114
505
506
5f1J7
508
5119
positive_exponent:
cl,l
no_exponent_found
add
cmp
js
di ,power_ten
di,LOW EXPONENT
exponent_overflow
cmp
jg
di,HIGH EXPONENT
inc
si
Test exponent digit flag
If zero then no exponent digits were
found
Form the final power of ten value
Check if the value is in range
Jump if exponent is too small
exponen~overflow
; Adjust string pointer
Convert the base 10 number to base 2.
Note:
l0**exp = 2**(exp*10g2(10))
di has binary power of ten value to scale the BCD value with.
convert:
dec
mov
or
js
si
ax,di
ax,ax
get_negative_power
Bump string pointer back to last character
Set power of ten to calculate
Test for positive or negative value
Scale the BCD value by a value >= 1.
call
fbld
fmul
jmp
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
rcr
jnc
get power 10
bcd-form -
Get the adjustment power of ten
Get the digits to use
Form converged result
short done
Calculate a power of ten value> 1 then divide the BCD value with
it. This technique fs more exact than multiplying the BCD value by
a fraction since no negative power of ten can be exactly represented
in binary floating point. Using this technique will guarentee exact
conversion of values like .5 and .0625.
;
get_negative_power:
neg
call
fbld
fdivr
fxch
fs:hs
fxch
ax
get power 10
bcd::form - '
Force positive power
Get the adjustment power of ten
Get the digits to use
Divide fractions
Negate scale factor
All done, set return values.
;
done:
fscale
mov
fstp
mov
mov
mov
mov
mov
pop
fwait
ret
Update exponent of the result
Set return value
Remove the scale factor
aX,NUMBER FOUND
st(l)
-
di,status ptr
word ptr Tdil,ax
di ,end ptr
word ptr [dil,si
sp,bp
bp
Set status of the conversion
Set ending string address
Deallocate local storage area
Restore caller's environment
Insure all loads from memory are done
parms size
Test if the character in al is an ASCII digit.
If so then convert to binary, bump cx, and clear the carry flag.
Else leave as is and set the carry flag.
3-52
Ap·113
548
549
558
551
552
553
554
555
556
557
558
559
568
561
562
563
564
565
566
567
568
569
578
;
test digit:
cmp
ja
aI, '9'
.not_digi t
See i f a digi t
cmp
jb
Character is a digit.
inc
sub
ret
dx
aI, '8'
Bump digit count
Convert to binary and clear carry flag
Character is not a digit.
;
not digit:
stc
ret
Leave as is and set the carry flag
ascii to floating endp
code - ends
end
ASSEMBLY COMPLETE, NO ERRORS FOUND
APPENDIX E
OVERVIEW
argument. Adding PU2 to the angle is performed by
adding Ol~ to the FPREM quotient bits identifying the
argument's octant.
Appendix E contains three trigonometric functions for
sine, cosine, and tangent. All accept a valid angle argument between - 262 and + 262 • They may be called from
PLM/86, PASCAL/86, FORTRAN/86 or ASM/86
functions.
It would be very inaccurate to add PII2 to the cosine
argument if it was very much different from PI/2,
Depending on which octant the argument falls in, a different relation will be used in the sine and tangent functions. The program listings show which relations are
used.
They use the partial tangent instruction together with
trigonometric identities to calculate the result. They are
accurate to within 16 units of the low 4 bits of an extended precision value. The functions are coded for
speed and small size, with tradeoffs available for greater
accuracy.
For the tangent function, the ratio produced by FPTAN
will be directly evaluated. The sine function will use
either a sine or cosine relation depending on which octant the angle fell into. On exit these functions will normally leave a divide instruction in progress to maintain
concurrency.
FPTAN and FPREM
These trigonometric functions use the FPTAN instruction of the NPX. FPTAN requires that the angle argument be between 0 and' PI/4 radians, 0 to 45 degrees.
The FPREM instruction is used to reduce the argument
down to this range. The low three quotient bits set by
FPREM identify which octant the original angle was in.
If the input anSIes are of a restricted range, such as from
o to 45 degrees, then considerable optimization is possible since full angle reduction and octant identification
is not necessary.
All three functions begin by looking at the value given
to them. Not a number (NAN), infmity, or empty regist~s must be specialiy treated. Unnormals need to be
converted to normal values before the FPTAN instruction will work correctly. Denormals will be converted to
very small unnqrmals which do work correctly for the
FPTAN instruction. The sign of the angle is saved to
control the sign of the result:
One FPREM instruction iteration can reduce angles of
1018 radians or less in magnitude to PI/41 Larger values
can be reduced, but the meaning of the result is questionable since any errors in the least significant bits of
that value represent changes of 45 degrees or more in the
reduced angle.
Cosine Uses Sine Code
Within the functions, close attention was paid to maintain concurrent execution of the 8087 an
VALID TAG
ZERO TAG
SPECI'AL TAG
EMPTY TAG
REGISTER MASK
equ
equ
equ
equ
equ
1
2
3
7
II
I
Tag register values
Define local var,iable areas.
;
stack
segment stack 'stack'
local_area
swl
'local_area
struc
dw
ends
stack
db
ends
code
segment public 'code'
assume cs:code,ss:stack
8987 status value
?
size local_area+4
Allocate stack space
Define local constants.
;
status
equ
[bp].swl
8987 status value location
3FFEC9"FDAA22l68C'23SR
PI/4
even
71
72
res87l:3,infinity control:l,rounding control:2,
precision control:2,error enable:l,res872:l,
precision-mask:l,underflow mask:l,overflow mask:l,
zero_divide_mask:l,denormaf_mask:l,invalidJmask:l
error-pending:l,resB73:l,precision error:l,
underflow error:l,overflow error:l;zero divide error:l,
denormal_error:l,invalid_error:l
-
&
41
42
43
44
45
46
47
48
49
59
51
52
53
S4
55
56
57
58
59
611
61
62
63
64
65
66
67
68
69
711
sine,cosine,tangent
trig_functions
public
name
4
dt
3-54
AP·113
indefinite
73
"FFC"""""R
dd
74
75
76
77
; Indefinite special value
This subroutine calculates the sine or cosine of the angle, given in
radians. The angle is in ST(II), the returned value will be in ST(II).
The result is accurate to within 7 units of the least significant three
bits of the NPX extended real format. The PLM/86 definition is:
78
79
811
81
82
83
84
sine:
85
cosine: procedure (angle) real external;
declare angle real;
end cosine;
86
87
88
89
procedure (angle) real external;
declare angle real;
end sine;
Three stack registers are required. The result of the function is
defined as follows for the following arguments:
9"
91
92
93
94
95
angle
result
valid or unnormal less than 2**62 in magnitude
zero
denormal
valid or unnormal greater than 2**62
infinity
NAN
empty
96
97
98
99
1911
lin
correct value
II or 1
correct denormal
indefinite
indefini te
NAN
empty
HJ2
1"3
;
194
HIS
1116
1117
1118
1119
1111
III
This function is based on the NPX fptan instruction. The fptan
instruction will only work with an angle of from" to P.I/4. With this
instruction, the sine or cosine of angles from" to PI/4 can be accurately
~alculated.
The technique used by this routine can calculate a general
sine or cosine by using one of four possible operations:
Let R
S
112
sin(R)
1)
= langle mod PI/41
= -lor 1, according
2) cos(R)
to the sign of the angle
3) sin(PI!4-R)
4) cos (PI/4-R)
113
114
ll5
ll6
The choice of the relation and the sign of the result follows the
decision table shown below based on the octant the angle falls in:
117
octant
sine
ll8
119
II
S*l
S*4
S*2
S*3
-S*l
-S*4
-S*2
-S*3
1211
121
122
1
2
3
4
123
124
5
125
6
126
7
cosine
2
3
-1*1
-1*4
-1*2
-1*3
1
4
127
128
129
Angle to sine, function is a zero or unnormal.
13"
131
132
;ine_zero_unnormal:
133
134
135
fstp
jnz
136
stell
enter sine _normalize
Remove PI/4
Jump if angle is unnormal
Angle is a zero.
137
138
pop
ret
139
1411
141·
142
143
144
145
,
;
.1
bp
Return the zero as the result
Angle is an unnormal.
enter sine normalize:
3-55
AP·113
call
jmp
.~6
147
148
149
15.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
cosine
Look at the value
Establish stack addresslbility
Alloeate staek spaee for status
bp
sp,size local_area
bp,sp
status
pi quarter
Store status value
Setup for angle reduee
Siqna1 cosine funetion
r Get status value
ZF • C3, PF z C2, CF • C0
Jump'if parameter is
empty, NAN, or infinity
cl~1
ax
funny.,parameter
st(0) = angle, st(l) • PI/4
Jump if normal or denormal
fxch
jpe
Angle is an unnormal or zero.
fstp
jnz
st (1)
enter_sine_normalize
Angle is a zero.
fstp
pop
fldl
ret
176
188
189
198
191
192
193
194
195
196
Entry point to cosine
Angle is unnorma1, normal, zero, denorma1.
167
168
169
170
171
172
173
174
175
187
proc
fxam
push
sub
mov
fstsw
fld
mov
pop
lahf
jc
166
177
178
179
180
181
182
183
184
185
186
normalize value
short enter_sine
, Remove PI/4
cos(8). 1.0
st(0)
bp
Remove 0
Restore staek
Return 1
All work is done as a sine function. By adding PI/2 to the angle
a cosine is converted to a sine. Of course the angle addition is not
done to the argument but rather to the program logie eontrol values.
;
sine:
Entry point for sine funetion
fxam
push
sub
mov
fstsw
fld
pop
lahf
je
bp
sp,size local_area
bp,sp
status
pi_quarter
ax
I
Look at the parameter
Establish staek addressibility
Allocate loeal space
Look at fxam status
Get PI/4 value
Get fxam status
CF • C8, PF • C2, ZF • C3
Jump if empty, NAN, or infinity
funny_parameter
Angle is unnormal, normal, zero, or denormal.
197
198
199
208
281
202
203
204
205
206
287
208
289
fxch
mov
jpo
, ST(l) • PI/4, st(0) angle
; Signal sine
; Jump if zero or unnormal
el,0
sine_zero_unnormal
ST(0) is either a normal or denormal value. Both will work.
Use the fprem instruction to aecurately reduee the range of the given
angle to within 0 and PI/4 in magnitude. If fprem cannot reduce the
angle in one shot, the angle is too big to be meaningful, > 2**62
radians. Any roundoff error in the calculation of the angle given
could completely ehange the result of this funetion. It is safest to
call this very rare case an error.
. 210
211
212
213
214
215
fprem
Redueeangle
Note that fprem will force a
denormal to a very small unnormal
Fptan of a very small unnormal
will be the same ver:y small
unnormal, which is correct.
Alloeate stack spaee for status
Check if rertuction was complet~
216
217
218
219
mov
fstsw
sp,bp
status
3-56
Ap·113
220
221
222
223
224
225
226
227
228
229
2311
231
232
233
234
235
236
237
238
239
241l
241
242
243
244
245
246
247
248
249
2511
251
252
253
254
255
256
257
258
259
2611
261
262
263
264
265
266
267
268
269
27r1l
pop
test
jnz
Set sign flags and test for which eighth of the revolution the
angle fell into.
Assert: -PI/4
< st(ll) < PI/4
fabs
Force the argument 'positive
condl bit in bx holds the sign
Test for sine or cosine function
Jump if sine function
cl,cl
sine _selec.t
or
jz
This is a cosine function. Ignore the original sign of the angle
and add a quarter revolution to the octant id from the fprem instruction.
cos(A) = sin(A+PI/2) and cos(IAI) = cos(A)
and
or
ah,not hIgh(mask condl)
bh,high(mask busy)
add
mov
rcl
xor
bh,high(mask cond3)
al,ll
al,l
bh,al
Turn off sign of argument
Prepare to add 010 to C0,C3,Cl
status value in ax
Set busy bit so carry out from
C3 will go into the carry flag
Extract carry flag
Put carry flag in low bit
Add carry to C0 not changing
Cl flag
See if the argument should be reversed, depending on the octant in
which the argument fell during fprem.
;
sine_select:
test
jz
bh,high(mask condl)
no _sine _rev'erse
Reverse angle if Cl
1
Angle was in oct ants 1,3,5,7.
fsub
jmp
Invert sense of rotation
arg <= PI/4
o<
Angle was in octants 1l,2,4,6.
Test, for a zero argument since fptan wi 11 not work if st (Il)
ftst
mov
fstsw
fstp
pop
test
jnz
271
272
273
274
275
276
277
278
279
2811
281
282
283
2!!4
285
286
287
281!
289
2911
291
292
293
Quotient in C0,C3,Cl
Get fprem status
sln(2*N*PI+x) = sin (x)
bx
bh,high(mask cond2)
ang Ie _too _big
Il
Test for zero angle
Allocate stack space
cond3 = 1 if st(ll) = 0
Remove PI/4
Get ftst st'atus
If C3=l, argument is zero
sp,bp
status
stell
cx
ch,high(mask cond3)
sine_argument_zero
Assert: Il < st(ll) <= PI/4
~o
sine_fptan:
fptan
TAN ST(Il)
ST(l)/ST(Il) = Y/X
after _Sine _fptan:
pop
test
jpo
bp
; Restore stack
bh,high(mask cond3 + mask condl); Look at octant angle fell into
X numerator
Calculate cosine for octants
1,2,5,6
Calculate the sine of the argument.
sin (A) = t~n(A)/sqrt(l+tan(A)**2)
sin (A) = Y/sqrt(X*X + y*y)
fld
jmp
st (1)
short finish sine
if tan (A) = Y/X then
Copy Y value
Put Y value in numerator
3-57
Ap·113
294
295
296
297
298
299
31111
3H
3112
393
3114
3115
3116
3117
3118
309
3111
311
312
313
314
315
316
317
318
319
3211
321
322
323
324
325
326
327
328
The top of the stack is either NAN, infinity, or empty.
;
funny-parameter:
st (ll)
return_empty
jpo
return_NAN
st(II) is infinity.
Remove PI/4
Return empty if no parm
Jump if st(II) is NAN
Return an indefinite value.
fprem
; ST/l) can be anything
return NAN:
return:empty:
pop
ret
,
bp
Simulate fptan wi th st (II)
Restore stack
Ok to leave fprem runninq
II
sine_argument_zero:
; Simulate tan(9)
; Return the zero value
fldl
jmp
The angle was to~ large. Remove the modulus and dividend from the
stack and return an indefinite result.
;
angle_too_big:
fcompp
fld
pop
fwa it
ret
329
3311
331
332
333
334
335
336
337
338
339
349
341
342
343
344
345
346
347
348
349
3511
351
352
353
354
355
356
357
358
359
3611
361
362
363
364
365
366
fstp
jz
.
indefinite
bp
; Pop two values from the stack
Return indefinite
Restore stack
Wait for load to finish
Calculate the cosine of the argument.
cos (A) = 1/sqrt(1+tan(A)**2)
if tan (A)
cos (A) = X/sqrt(X*X + y*y)
= Y/X
then
X numerator:
fld
fxch
st(II)
st(2)
Copy X value
Put X in numerator
s,t,st (II)
Form X*X + y*y
finish_sine:
fmul
fxch
fmul
fadd
fsqrt
st,st(II)
st(II)
st(II)
= x*x
+ y*y
sqrt(X*X + y*y)
Form the sign of the result. 'The two conditions are the Cl flag from
FXAM in bh and the CII flag from fprem in ah.
and
and
or
jpe
fchs
bh,high(mask condll)
ah,high(mask condl)
bh,ah
posi tive_sine
Look at the fprem CII flag
Look at the fxam Cl, flag
Even number'of flags cancel
Two negatives make a positive
Force result negative
posi tive_sine:
fdiv
ret
cosine
endp
Form final result
Ok to leave fdiv running
Ap·113
367
368
369
3711
371
This function will calculate the tangent of an angle.
The angle, in radians is passed in ST(IIl), the tangent is returned
in ST(IIl). The tangent is calculated to an accuracy of 4 units in the
least three significant bits of an extended real format number. The
PLM/86 calling format is:
372
373
374
375
376
tangent:
procedure (angle) real external;
declare angle real;
e'nd tangent;
377
378
379
3811l
381
382
383
384
385
386
387
388
389
3911l
391
392
Two stack registers are used. The result of the tangent function is
defined for the following cases:
angle
result
valid or unnormal < 2**62 in magnitude
correct value
III
III
denormal
valid or unnormal > 2**62 in magnitude
NAN
infini ty
empty
correct denormal
indefinite
NAN
indefinite
empty
The tangent instruction uses the fptan instruction.
relations are used:
Four possible
393
Let R = langle MOD Pl/41
S = -lor 1 depending on the sign of the angle
394
395
396
397
398
399
41111l
4111
4112
403
404
4115
4116
octant
II
1
2
3
4
4118
409
5
6
7
4111
411
422
423
2) tan(Pl/4-R)
4) l/tan (PI/4-R)
3) l/tan(R)
The following table is used to decide which relation to use depending
on in which octant the angle fell.
4 III 7
412
413
414
415
416
417
418
419
4211
421
tan(R)
1)
relation
S*l
S*4
-S*3
-S*2
S*l
5*4
-S*3
-S*2
;
tangent proc
fxam
push
sub
mov
fstsw
fld
pop
lahf
jc
Look at the parameter
Establish stack addressibility
Allocate local variable space
bp
sp,size local area
bp,sp
status
pi_quarter
ax
Get fxam status
Get PI/4
CF
funny_parameter
= CII,
PF
C2, ZF
= angle,
st(l)
C3
424
425
426
427
428
Angle is unnormal, normal, zero, or denormal.
fxch
jpe
st(lIl)
PI/4
429
4311
431
432
433
434
435
436
437
438
439
Angle is either an normal or denormal.
Reduce the angle to the range -PI/4 < result < PI/4.
If fprem'cannot perform this operation in one try, the magnitude of the
angle must be > 2**62. Such an angle is so large that any rounding
errors could make a very large difference in the reduced angle.
It is safest to call this very rare case an error.
tan normal:
fprem
Quotient in CII,C3,C1
Convert denormals into unnormals
440
3-59
Ap·113
441
442
443
444
445
446
447
448
449
451l
451
452
453
454
455
456
457
458
459
461l
461
462
463
464
465
466
467
468
469
471l
471
472
473
474
475
476
477
478
419
489
481
482
483
484
485
486
487
488
489
499
491
492
493
mov
- fstsw
pop
test
jnz
sp,bp
status
Allocate stack spce
Quoti~nt identifies octant
original angle fell into
tan(PI*N+x) x tan (x)
Test for complete reduction
Exit if angle was too big
bx
bh,high(mask cond2)
ang Ie _too _big
See if the angle must be reversed.
Assert: -PI/4 < st(ll) < PI/4
Il <- st(ll) < PI/4
Cl in bx has the sign flag
must be reversed
fabs
test
jz
bh,high(mask condl)
no _tan _reverse
Angle fell in octants 1,3,5,7.
fsub
jmp
Reverse it, subtract it from PI/4.
Reverse angle
short do_tangent
Angle is either zero or an unnormal.
;
tan_zero_unnormal:
fstp
jz
stIll
tan_angle_zero
Remove PI/4
Angle is an unnormal.
call
jmp
normalize value
tan normar
pop
ret
bp
Restore stack
Angle fell in octants 11,2,4,6.
Test for st(ll)
D
9, fptan won't work.
no tan reverse:
ftst
mov
fstsw
fstp
pop
test
jnz
Test for zero angle
Allocate stack space
C3 = 1 if st(ll) = Il
Remove PI/4
Get ftst status
sp,bp
status
stIll
cx
ch,high(mask cond3)
tan_zero
do_tangent:
fptan
tan ST(Il)
ST (1) /ST(9)
494
495
496
497
498
499
599
Sill
592
593
594
595
596
597
598
5119
5111
a fter _tangent:
Decide on the order of the operands and their sign for the divide
operation while the fptan instructIon is working.
pop
mov
and
test
jpo
bp
Restore stack
al,bh
; Get a copy of fprem C3 flag
ax,mask condl + high(mask cond3); Examine fprem C3 flag and
; fxtract Cl flag
bh,high(mask condl + mask cond3); Use reverse divide if in
octants 1,2,5,6
reverse_divide
Notel parity works on low
8 bits onlyl
Angle was in octants ~,3,4,7.
Test for the sign of the result.
511
512
513
or,
jpe
al,ah
positive_divide
3-60
Two negatives cancel.
AP·113
514
515
516
- 517
518
519
521l
521
522
523
524
positive_divide:
fdiv
ret
fldl
jmp
525
526
527
Forll result
Ok to leave fdiv running
Force l/Il
tan(PI/2)
a fter _tangent
Angle was in octants 1,2,5,6.
Set the correct sign of the result.
528
529
531l
531
532
533
534
535
536
537
, Force result negative
fchs
reverse_divide:
or
jpe
al,ah
positive_r_divide
fchs
Force result negative
positive_r_divide:
538
539
541l
541
542
543
544
545
546
547
Form reciprocal of result
Ok to leave fdiv running
fdivr
ret
,
tangent endp
This function will normalize the value in st(Il).
Then PI/4 is placed· into st (1) •
;
normalize value:
548
549
551l
fabs
fxtract
fldl
st(l),st
!add
fsub
fscale
fstp
stIll
fld
pi _quarter
fxch
ret
551
552
553
554
555
556
557
558
559
561l
561
code
Force value positive
Il <= st(ll) < 1
, Get normalize bit
1 Normalize fraction
Restore original value
Porm original normalized value
Rellove scale factor
Get PI/4
ends
end
ASSEMBLY COMPLETE, NO ERRORS FOUND
3-61
APpLICATION
NOTE
AP·122
September 1981
©,
INTEL CORPORATION, 1981
3-62
210202;001
AP·122
I. INTRODUCTION
circuitry which interfaces the disk drive to the host
processor's system bus. The host has complete control
over the disk drive and executes a separate command sequence for each function-such as seek, format.or read
data. The host is assisted by a DMA (direct memory
access) controller which performs the high speed transfers of read or write data between the drive interface
and the system memory. Any error processing, such as
CRC (cyclic redundancy check) error checking and initiating retries, is also performed by the host processor.
A major disadvantage of this approach is that a large
portion of the host's time and bus bandwidth is consumed by disk control overhead (command execution,
interrupt servicing, and error processing) leaving little
time for data processing.
This application note describes the design of a disk controller for a Shugart SA4008 Winchester disk drive. An
8089 I/O processor is used to offload many of the disk
control overhead tasks from the host processor. The intelligent controller maximizes system throughput by
performing the disk control tasks concurrently with
data processing by the host processor. The features of
the 8089 110 processor which make it ideal for disk control applications are also described.
As newer microprocessors provide more throughput
and address more memory, larger and more complex
microprocessor based applications are designed. Many
of these applications require high performance and high
capacity mass storage devices such as hard disk drives.
Winchester-technology (filtered air system and nonremovable platters) disk drives are cost and performance compatible with high performance microprocessors. These drives provide more performance and
reliability than floppy disk drives yet are less expensive
than removable platter disk drives of comparable performance.
A better approach is to partition the system functions
and implement an intelligent disk controller which
would perform the overhead tasks and free more host
processor time for data processing. This intelligent controller would" be able to accept a single high level command and perform multiple functions such as seek, read
data, and process errors. Here the host has more time
for data processing since it generates one high level command rather than several simple commands. It also services only one interrupt at the completion of the high
level command rather than several.
For applications requiring high performance disk
drives, a major task of the system designer is the design
of the disk controller-the interface between the high
performance processor and disk drive. The conventional approach (Fig. I) is to develop specialized control
The system configuration of an intelligent disk controller based on the Intel 8089 110 processor is shown in
r-----,
DISK CONTROLLER
A
~
HOST
PROCESSOR
A
1\
~
I'
S
Y
S
T
E
M
B
U
SYSTEM
MEMORY
A
1\
~
I'
I
I
I
I
A I
l\f
S
A
~
~
I'
PARALLEL
110
IA
l~
I
t\
:
V
) CONTROL
STATUS
I
I
~
I
-V
SERIAU
PARALLEL
CONVERTER
1\
DMA
WRITE DATA
I
I
I
L ____ .J
READ DATA
I' CONTROLLER
Figure 1. Conventional Disk Controller System Configuration
3-63
AFN02057A
AP~122
Figure 2 where it is used in conjunction with an 8086
CPU as, the host processor. This type of system configuration is called the iAPX 86/11 since it contains an
8086 IUld an 8089. The 8089 I/O processor is ideal for
implementing an intelligent controller since it provides
processing capabilities well suited for controlling a disk
,drive and high speed DMA transfers for moving data to
and from, the disjc drive. The 8089 also supports a
private local bus which provides access to the drive control circuitry, program memory, and local data buffers.
This minimizes, access to the shared system bus and
hence increases overall system throughput. It will be
seen later that local data buffering allows:
.:.. high speed burst transfers without overrun and
underrun errors
- disk controller operation at lower system bus priority
than the host to maximize host processing
- error detection and retries directly by the disk controller without host intervention
The 8089-based disk controller maximizes system
throughput. The disk control overhead tasks are offloaded from the host and performed by the 8089. This
frees host processor time for data processing and other
control processing. Host processor performance is
reduced when both the host and 8089 try to access the
system bus at the same time. These system bus conflicts
can only occur when the 8089 accesses the system
bus-during the accessing of memory-based communication blocks (used for transferring command and
status information) and during sector data transfers between the system memory buffer and the 8089's local
data buffer. For a sirigle drive, this can mean host processor performance degradation of no more than 3070.
With the conventional approach of Figure 1, the degradation can approach 10Vfo due to CPU overhead time to
control the disk operation and system bus time used by
the DMA controller. Thus the 8089-based controller
allows significantly more processing by the host, especially when multiple drives are supported.
This application note describes how basic disk control
functions are implemented with an 8089. Therefore, the
design described here does not exhibit all features possible in an intelligent controller. However, the hardware
design allows the software to be easily enhanced to provide extra features. A later section addresses software
enhancements.
The application note begins with an overview of the
8089 I/O proCessor followed by a brief description of
the SA4008 drive. Next it discussion of the implemented
functions is provided. A detailed description of the
hardware and software design is then presented. Finally,
a discussion of possible enhancements concludes the
note.
Additional information related to topics discussed in
this application note can be found in the following Intel
documents:
The 8086 Family User's Manual
r - - -DISK
- CONTROLLER
- - - ---I
8086
HOST
PROCESSOR
8089
SYSTEM
BUS
INTERFACE
UO
PROCESSOR 1-_ _ _ _ _ _ _ _...,
S
Y
S
T
E
M
LOCAL
MEMORY
B
U
S
SYSTEM
MEMORY
I
I
I
CONTROL
I
I
SYSTEM
BUS
INTERFACE " , - - "
LOCAL
BUS
INTERFACE
I
IL __________ --1
LOCAL
, MEMORY
STATUS
WRITE
DATA
READ
DATA
Figure 2. Intelligent Disk Controller System Configuration (IAPX 86111)
3-64
AFN02067A
Ap·122
Intel Multibus Specification
iSBC 86/l2A Hardware Reference Manual
iSBC 604/614 Cardcage Hardware Reference Manual
ICE-86 In-Circuit Emulator Operating Instructions for
. ISIS-II Users
RBF-89 Real-Time Breakpoint Facility Operating Instructions for ICE-86 In-Circuit Emulator Users
8089 Macro Assembler User's Guide
In addition, the following documents from Shugart
Associates provides detailed information on the disk
drive:
SA4000 Fixed Disk Drive OEM Manual
SA4000 Fixed Disk Drive Service Manual
II. INTEL@ 8089110 PROCESSOR
This section briefly describes the 8089 110 processor's
features and modes of operation. A more detailed discussion can be found in The 8086 Family User's Manual
(October 1979).
A block diagram of the 8089 110 processor is shown in
·Figure 3. The 8089 provides two independent channels.
Both channels can execute task program instructions
and perform high speed DMA transfers. Each channel
has its own register set to support these operations.
A channel starts operation by executing task program
instructions. These instructions are conceptually similar
to instructions of other microprocessors but are typically executed to prepare the channel and I/O device for
DMA transfers. Execution of the XFER (transfer) instruction switches the channel from instruction execution mode to DMA mode and high speed data transfer
cycles are performed. When the DMA transfer terminates, task program instruction execution resumes for
any post-DMA processing (e.g., status analysis, error
processing, etc.). One channel or two channels may be
operating at any given time. When two channels are active, they operate in a time-multiplexed manner sharing
a common multiplexed address/data bus. A flexible priority structure allows both channels to operate with
equal priorities or either channel to operate at a higher
priority.
The 8089's bus structure and timing are identical with
other members of the iAPX 86 and iAPX 88 families,
such as the 8086 CPU and 8087 numeric processor extension. This allows the bipolar support circuits of the
iAPX 86 and 88 families (8284A clock generator, 8288
bus controller, 8289 bus arbiter, etc.) to be used with the
8089. The 8089 generates 20 address signals and,
depending on how it is initialized, supports an 8- or
16-bit data bus. This provides compatibility with the
16-bit 8086 CPU or the 8-bit 8088 CPU.
Both channels can access a 1 megabyte system address
space and a 64 kilobyte local address space. Each address space accommodates both memory and 110
devices. This allows task program execution, memory
data access, and 110 de~ice access in both system and
local address spaces. Task program and DMA access of
the two address spaces is discussed later.
CA
ull-----:----I
I------Iul
TASK POINTER
~I----~
() 1/0 CONTROL
TASK POINTER
I----~
l1
11
ORO 1 EXT 1 SINTR·l
1/0 CONTROL
BHE
l1
..
l:
U
tt
ORO 2 EXT 2 SINTR·2
FIgt.re 3. 8089 I/O Prqcessor Block Diagram
3-65
AFN02057A
Ap·122
System Configurations
The 8288 bus' controller used with the 8089 provides
separate command signals for each address space. The
bus controller's memory read and write commands provide access to the system address space and the I/O read
and write commands are used to access the local address
space. Separate commands for each address space allow
two external buses to be implemented which promotes
concurrent processing between the 8089 and the host
processor and increases system throughput.
Systems using the 8089 may be configured in one of two
different ways-local mode or remote mode. In the
local configuration, the 8089 provides capabilities of an
intelligent DMA controller for a single CPU. In the
remote configuration, the 8089 provides capabilities of
a control processor and a DMA controller and can
operate concurrently with one or more host processors.
Local Mode Configuration
In addition, the 8089 allows these physical buses to be
either 8 or 16 bits wide. During the 8089's initialization
sequence, the widths of the system and local buses are
dermed. Although the 8089 supports two buses, a single
bus may be used which is shared with a CPU. This will
be described later when local and remote mode configurations are discussed.
In the local mode configuration, the 8089 resides on the
same local bus as an 8086 or 8088 CPU and shares the
clock generator, address latches, data transceivers, and
bus controller with the CPU. An example of a local
mode iAPX 88/11 (8088 CPU and 8089 I/O processor)
configuration is shown in Figure 4.
The interface signals used to communicate with a host
processor are also shown in Figure 3. The channel attention (CA) and select (SEL) input signals are used to start
channel operation. Both signals are activated simultaneously by the host. SEL selects channel 1 or channel
2 (0 or 1, respectively). The SINTRI and SINTR2 output signals are used to interrupt the host processor. One
of these signals is activated whenever the set interrupt
instruction, SINTR, is executed. SINTRI is activated by
channel 1 and SINTR2 by channel 2. The memorybased communication structure used to transfer command and status information between the 8089 and the
host processor is discussed in a later section.
The 8089 is a slave to the CPU in local mode configurations and access to the shared bus is controlled by the
bidirectional request/grant (RQ/GT) line. The CPU has
possession of the bus when system operation begins.
Whenever the 8089 needs access to the bus, it signals the
CPU of this need by pulsing the ru::!/GT line. The CPU
may be presently accessing the bus. As soon as the CPU
is finished with the bus, it pulses the RQ/GT line. The
8089 receives this grant pulse and accesses the bus.
When the 8089 is finished using the bus, the 8089 pulses
the RQ/GT line to notify the CPU that it has released
the bus.
Once the 8089 acquires the bus, it retains buS possession
until finished. The request/grant protocol provides no
8288
BUS
8088
CONTROLLER
CPU
R"Q/GT
LATCHES &
TRANSCEIVERS
Figure 4. Typical Local Mod~ Configuration (iAPX 88111)
3-66
AFN02057A
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mechanism for the CPU to regain the bus from the
8089. Care should be used when selecting this ConfIguration since frequent or lengthy periods of 8089 activity
can limit the CPU's use of the bus. However, the local
mode confJguration is'an economical technique for adding intelligent, high speed DMA transfer capabilities to
the system.
8089 supports two independent externally.implemented
physical buses (Fig. 6). One bus is the shared system bus
and'the other is a private local bus. The system bus
interface contains address latches, data transceivers, a
bus controller, and a bus arbiter. The host processor
uses an identical interface to access the system bus. The
8289 bus arbiter controls access to the system bus and is
responsible for acquiring and surrendering the bus
based on system priorities. The local bus interface contains address latches and data transCeivers (if required
by loading conditions).
In local mode configurations, the 8089's 1 megabyte
system address space coincides with the CPU's memory
address space and the 64 kilobyte local address space
coincides with the CPU's 110 address space. This means
that when the 8089 accesses its system space or when the
CPU accesses its memory space, the 8288 bus controller's memory read or write command is activated. When
the 8089 accesses its local space or when the CPU accesses its 1/0 space, the bus controller's 1/0 read or
write command is activated.
The 8089's 1 megabyte system address space is used to
access the shared system bus and the 64 kilobyte local
address space is used to access the private local bus. A
single 8288 bus controller provides command signals for
both the system and local buses. The memory read and
write commands are used to access both memory and
1/0 devices on the system bus. The 1/0 read and write
commands are used when accessing memory or 1/0
devices on the local bus.
The 8089's physical data bus widths must be defined the
same as the CPU's during the initialization sequence (to
be discussed later) in local mode configurations. With
an 8088 CPU the 8089's system and local physical bus
widths must be initialized as 8 bits. When used with an
8086 CPU, both buses must be initialized as 16 bits.
The physical widths of the system and local buses may
be 8 or 16,bits. The widths are defined during the initialization sequence (to be discussed later). All four bus
width combinations are available:
Although the 8089 can execute programs and access
memory and 1/0 devices from its two address spaces,
several rules should be followed to ensure compatibility
with the CPU. Data memory that is shared with the
CPU must be accessed in the 8089's system address
space. 1/0 devices which are accessed by the CPU in its
1/0 address space must be accessed in the 8089's local
address space. Other memory and 1/0 devices accessed
by the 8089 only may reside in either the 8089's system
or lo~ address space.
8-bit system bus and 8-bit local bus
8-bit system bus and 16-bit local bus
16-bit system bus and 8-bit local bus
16-bit system bus and 16-bit local bus
Remote Mode Configuration
In the remote mode configuration, a shared system bus
with memory provides communications between the
host processor and the 8089 1/0 processor (Fig. 5). The
8089
I/O
PROCESSOR
MODULE
HOST
PROCESSOR
MODULE
SHARED
MEMORY
figure 6. Typical 8089 110 Processor Module
(Remote Mote)
Figure 5. Remote Mode Configuration
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AFN02C57A
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The system bus width is typically established by the host
processor. A 16-bit system bus is usually used with a
16-bit host while an 8-bit bus with an 8-bit host. The
local bus width is typically selected based on the peripheral devices supported-8-bit bus with 8-bit peripherals and 16-bit bus with 16-bit peripherals. A 16-bit
local bus is selected when both 8- and 16-bit peripherals
are supported since it allows task program and DMA accessing of both 8- and 16-bit 1/0 devices. DMA capabilities are discussed later. Memory devices are configured so that the width of the memory's data path is
the same as the physical bus.
be in-RAM since certain parameters are updated during
8089 operation (e.g., BUSY byte).
The channel control, parameter and task blocks are
used whenever the host starts channel operation. The
host initializes certain parameters in the channel control
and parameter blocks before generating the channel
attention signal. When the 8089 receives a channel
attention signal, the proper half of the CB is accessed
depending on the value of SEL (0 for channel I and I
for channel 2). The CCW (channel control word) instructs the selected channel what action to perform,
Communications With Host Processor
Communications between the host processor and the
8089 110 processor are primarily through shared
memory. The hardwired signals (CA and SEL to the
8089 and SINTRI and SINTR2 from the 8089) are used
as startup and interrupt signals. Memory-based communication is implemented through a series of five linked
control blocks (Fig. 7). This feature provides a very flexible communication structure and aJlows the 8089 to
handle a wide variety of 1/0 functions.
HIGH MEMORY
•
"mM I
SCB SEGMENT BASE
"mMI
CB SEGMENT BASE
CONFIGURATION
POINTER
(SCP)
SCB OFFSET
I
CONFIGURATION
BLOCK
(SCB)
The first three linked blocks in the' communication
structure are used during the 8089' s initialization sequence (Fig. 8). The system configuration pointer (SCP)
and system configuration block (SCB) are used only
during initialization. Initialization is required after a
RESET signal is received by the 8089. When the first
channel attention after reset is received, the initialization sequence begins and the 8089 reads the data in the
system configuration pointer. The parameter SYSBUS
defines the physical width of the system bus (8 or 16
bits). The SCB offset and segment base point to the second block, the system configuration block (SCB). The
8089 next reads the data in the SCB. The SOC parameter defines the local bus's physical width and request/grant mode (refer to The 8086 Family User's
Manual). The CB offset and segment base point to the
channel control block (CB). The 8089 clears (zeros)
channell's BUSY byte in the CB which completes the
initialization sequence. With subsequent channel atten/ tions, the 8089 directly accesses the CB as described
below.
CB OFFSET
I
}-
SYSBUS
SOC
}-
PB2 SEGMENT BASE
PB2 OFFSET
CHANNEL
CONTROL
BLOCK
(CB)
BUSY
I
CCW
PBl SEGMENT BASE
PB10FFSET
BUSY
PARAMETER
BLOCK
(PB1)
I
CCW
I
J
TBl SEGMENT BASE
TB10FFSET
The SCP, SCB and CB must reside in shared memory
since both the host and the 8089 access them. The SCP
must begin at OFFFF6H while SCB and CB locations are'
user-defined. The SCP is typically located in ROM
while the SCB and CB are in RAM. With the SCP in
ROM, the SCB's location remains fixed once defined.
Since each 8089 must have a unique CB, the SCB (which
points to the 8089's CB) must be placed in RAM if multiple 8089' s exist in the system. This aJlows each 8089 to
be initialized and directed to its own CB. The CB must
,m/ I1
BLOCK
(TB1)
}I+--
CHANNELl
TASK PROGRAM
LOW MEMORY
}~
L
Figure 7. Memory B,ased Communication Blocks
3-68
AFN02057A
AP·122
,
HIGH SYSTEM MEMORY
FFFFEH
,
(RESERVED)
FFFFCH
SCB SEGMENT BASE
SCBOFFSET
SYSTEM
CONFIGURATION
POINTER
(FIXED LOCATION)
(RESERVED)
I
}-
FFf'FAH
FFFF8H
SYSBUS
FFFF6H
FFFF4H
8088/8088
RESET LOCATION
FFFF2H
FFFFOH
\
CB SEGMENT BASE
SYSTEM
CONFIGURATION
BLOCK
(USER·DEFINED LOCATION)
CBOFFSET
(RESERVED)
I
SOC
}I-,
C
H
A
N
N
E
L
2
\
CHANNEL
CONTROL
BLOCK
(USER· DEFINED LOCATION)
C
H
A
N
N
E
-
L
1
(RESERVED)
PB2 SEGMENT BASE
PB2 OFFSET
BUSY
I
}--
CHANNEL 2
'
- .. PARAMETER BLOCK
CCW
(RESERVED)
PB1 SEGMENT BASE
PB10FFSET
BUSY
I
CCW
}--
- ..
~~:::~;E~ BLOCK
t--
LOW SYSTEM MEMORY
,
Figure 8. Initialization Control Blocks
such as start, suspend, resume, or halt task program
execution. The BUSY byte is set to OFFH by the 8089 if
task program execution is started or resumed. The 8089
clears it to OH if task program execution is suspended or
halted. Within the channel control ,block, PBI offset
and segment base point to the parameter bloclc for channel I and PB2 offset and segment base point to the
parameter block for channel 2. From the proper parameter block, the 8089 reads the task block (TBI or TB2)
offset and segment base which point to the task program~ The task block address must be the first two
words of the parameter block. All other parameters in
the PB are user-deflned allowing parameters to be tailored to a specific I/O task.
Of all the five linked blocks, only the task block may
reside either in system or local memory. For remote
mode configurations, the task block typically resides in
local m~oty to
maximum system performance.
However, executing task programs from system
memory is advantageous for initial debugging or for executing a task program that downloads another task
program from s!stem memory to local RAM.
obtain
3-69
AFN02057A
AP-122
During destination synchronized DMA transfers, the
channel reads the data from the source device and waits
for the DMA request signal before writing the data to
the destination device. Similar to source synchronization, the DMA acknowledge signal is generated by
decoding the destination device's address. This type of
synchronization is commonly used when transferring
data from memory to an 110 device.
DMA Capabilities
The 8089's high speed DMA capability is ideal for disk
controller applications. The maximum DMA transfer
rate with a 5 MHz clock is 1.25 megabytes/sec. Conventional DMA controllers use a single bus cycle and gate
data from the source device (memory or I/O) to the
destination device. However, the 8089's DMA transfer
uses two bus cycles. The fIrst bus cycle reads the data
fFom the source device and the second bus cycle ,writes
the data to the destination device. The advantages of
two cycle DMA are discussed in a later section.
The fInal synchronization option is to specify no synchronization. Here the DMA request input is not examined and the channel transfers data' without waiting for
a request. This specifIcation is usually reserved for
memory to memory transfers. The channel runs at full
memory speed. Wait states may be used when accessmg
slow memory devices or when waiting to access the
shared system bus.
All possible combinations of source and destination
device specifIcations are available. Both source and
destination may be memory or an I/O device. This
means that memory to memory, I/O to I/O, and
memory to or from I/O DMA transfers are available. In
addition, DMA transfers between system and local address spaces or within the same address space can 'be
specifIed.
Both memory and 110 devices (source and destination) ,
are specifIed as addresses either in the system or local
address space. These address values are loaded into
source and destination pointer registers. After each
word or byte is transferred, a register used as a memory
pointer is incremented by one for byte transfers or by
two for word transfers. A register used as an I/O device
pointer is not modifIed. Registers used as DMA memory
pointers are incremented only. No provisions exist for
decrementing memory pointer registers during DMA.
DMA
Synchronlza~ion
To accommodate a wide range of I/O device transfer
rates, the 8089 allows DMA transfers to be synchronized. Each byte or word is transferred between the I/O
device and the 8089 upon receiving a DMA request
synchronizing signal from the 110 device. Each channel
,has a DMA request input: DRQl for channel 1 and
DRQ2 for channel 2. Three options exist When specifying DMA transfer synchronization. DMA transfers may
be source synchronized, destination synchronized, or
unsynchronized.
During source synchronized DMA transfers, the channel waits until the DMA request input is activated by the
source device before reading the data. External circuitry
decodes the source device's address and provides a
DMA acknowledge signal to the source device allowing
it to deactivate the DMA request signal. Immediately
after readirg the data, the 8089 writes it to the destination device. The next read and write cycles begin when
the source device activates DMA request again. Source
synchronized DMA transfers are typically used when
transferring data from an I/O device to memory.
DMA latency is the time required for the 8089 to respond to a DMA request; i.e., the time from DMA request signal activation until the synchronized bus cycle
begins. DMA latency is due to DMA request propagation through internal pipelined control circuitry. The
maximum DMA latency time when one channel is active
and waiting for DMA 'request is 6 clocks. When both
channels are active, the latency time may be up to 12
clocks.
Due to DMA latency, the DMA request signal cannot be
used to synchronize transfers when the transfer rate of
the I/O device is close (greater than 0.7 megabytes/sec
when one channel is active) to the maximum transfer
rate ofthe 8089, 1.25 megabytes/sec. F.or this case, wait
states may be used to synchronize transfers. Since hard
disk drives are in this category, the disk controller
described in this application note uses wait states to
synchronize disk transfers.
Advantages of Two Cycle DMA
The two bus cycle implementation of DMA transfers
allows enhanced DMA capabilities. Data transfers between source and destination devices with different data
widths may be specifIed. For example (Fig. 9), a DMA
transfer cycle from an 8-bit I/O device to 16-bit memory
is accomplished by reading two bytes from the I/O device (two bus cycles), assembling the bytes into a word,
and then writing a 'single word into memory (one bus cycle).' Here buses are accessed effIciently since three bus
cycles are required as compared to four bus cycles if a
single byte at a time Vl(ere read and written. In the same
eXll!11ple, since the 16-bit memory resides on the shared
system bus, 50070 fewer system bus accesses are required
and overall system throughput may be increased.
Use of this bus matching DMA feature involves specifying logical J;>MA source and destination bus widths with
3-70
AFN02057A
Ap·122
8089
a·BIT
a·BIT
MEMORY
l6·BIT
MEMORY
1/0
DEVICE
Figure 9. 8·Blt 1/0 to 16·Blt Memory DMA
the WID instruction. This allows DMA transfers to or
from 8-bit 110 devices which reside on a 16-bit bus. The
only restriction is that the logical bus width may not exceed the physical width. Thus 8- or 16-bit transfers may
be performed with a 16-bit bus while only 8-bit transfers
are permitted with an 8-bit bus (Fig. 10). Synchronized
DMA transfers between dissimilar width logical buses
may have more than one synchronized bus cycle. For example, destination synchronized transfers from 16-bit
memory to an 8-bit I/O device perform two synchronized 8-bit write bus cycles for each l6-bit fetch from
memory.
8089
l6·BIT
MEMORY
l60BIT
a'BIT
I/O
I/O
DEVICE
DEVICE
a·BIT
MEMORY
a AND l6·BIT
LOGICAL WIDTHS
-
a·BIT LOGICAL
WIDTH ONLY -
Figure 10. Logical Bus Widths for DMA Transfers
3-71
AFN02057A
AP·122
Another feature derived from the two bus cycle DMA
approach is character translation during DMA mode.
Byte data may be translated via a 256-byte translation or
lookup table. During each DMA transfer cycle, a byte
of data is read from the source device, the data byte is
translated, and then the translated byte is written to the
destination device. Three bus cycles are required here
since the translation requires a fetch cycle from
memory.
TAG
19
0
O.P.ADDRESSA (OA)
G.P. ADDRESS B (OB)
O.P. ADDRESS C (OC)
TASK POINTER
BYTE COUNT (BC)
Register Set
I
CHANCNTL
DMA Termination
The register set of the 8089 is presented in Figure 11.
Each channel has its own set of registers, except for the
(IX)
INDEX
MASK
DMA transfers can be terminated when the byte count
(BC) register, which is decremented after each byte or
word is transferred, reaches zero. The 16-bit BC register
is initialized by task program instructions before the
DMA transfer is started and permits data transfers of
up to 64 kilobytes to be terminated. Each channel has an
external terminate (EXT) input which can be activated
by external circuitry to terminate the DMA transfer.
Another condition allows termination based on masked
comparison of transferred data. As byte data is transferred, an 8-bit mask value selects which bits of the data
are compared with corresponding bits of an 8-bit compare value. Terminatioll can be specified to occur either
when a match occurs or does not occur. Examples using
this terminate condition are transferring data until an
EOF character is detected (match) and transferring data.
while bit 7 = 1 (mismatch). A final terminate condition
called single transfer allows a single byte or word to be
transferred.
t-
15
Two bus cycle DMA also allows DMA transfers to be
terminated based on masked comparison of the transferred data. This is discussed in the next section.
The 8089 allows several conditions to terminate DMA
transfers. One condition or several conditions may be
specified. When several conditions are specified, DMA
transfers are terminated when anyone condition is
detected. In addition, different task program re-entry
points may be specified for each condition. This permits
special post-DMA' processing based on the terminate
condition. Task program re-entry points are specified as
offsets which are added to the task pointer. Three offsets are available: 0, 4, or 8. These offsets permit long or
short jumps to termination routines. When more than
one terminate condition occurs simultaneously, task
program execution is resumed at the largest offset of the
simultaneously occurring terminate conditions. An exception to this rule exists. The byte count terminate condition has highest priority and its offset is used if this
terminate condition occurred.
(TP)
tt-
CMPR
(CC)
tt-
t-
a
0
!
~I~--~--~~--"
PARAMETER PNTR
(PP)
CHAN CNTL PNTR
(CP)
19
I
Figure 11. 8089 Register Set
channel control pointer register (CP) which is shared by
both channels. This register is 20 bits in size and is used
to access the channel control block whenever a channel
receives a channel attention signal. Each channel has a
20-bit parameter pointer register (PP) which provides
access to the parameter block. The common CP register
is initialized during the 8089's initialization sequence
while the PP registers are initialized whenever a channel
attention signal is received. Therefore, the CP and PP
may be read during task program execution, but cannot
be changed.
Each channel has four 20-bit registers, each with an
associated tag bit. The tag bit is used whenever the register is used as a pointer and indicates which address space
(system or local) is accessed. If the tag bit is equal to 0,
the 1 megabyte system address space is accessed using all
20 bits of the register. However, if the tag bit is equal to
1, the 64 kilobyte local address space is accessed using
the lower' 16 bits of the register. Instructions that initial- .
ize these registers either set or clear the tag bit. The load
pointer instruction clears the tag bit, the move instruction sets the tag bit, and the move pointer instruction
which moves data from memory into the register's 20
bits and tag bit either sets or clears the tag bit based on
the contents of the referenced memory location.
The task pointer register (TP) is used as a task program
counter. The remaining three 2O-bit registers (GA, GB,
and GC) are general-purpose registers. During task program execution, they may be used for data manipulation or as pointers. During DMA mode, the GA and GB
. registers point to source and destination devices and if
3-72
AFN02057A
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the translation option is specified, the GC register
points to a 2S6-byte translation table. Two source/
destination register specifications are possible: (1) GA
points to the source and GB to the destination and (2)
GB points to the source and GA to the destination.
Special Design Considerations
Most interrupt signals reCeiVed by the 8089 are used to
synchronize DMA transfers and the 8089's DMA request (DRQ) inputs support these interrupts. The 8089
also supports non-DMA related interrupt signals.
Four 16-bit registers are also included in each channel's
register set. The index register (IX) may be used by task
program instructions to access memory and I/O
devices. The address of the memory or I/O device is
computed by adding the contents of IX with the contents of the specified pointer register. The byte co.unt
register (BC) can terminate DMA transfers. The mask/
compare register (MC) may be used to perform masked
compare operations during task program execution or
masked compare DMA terminations. The channel control register (CC) specifies the details of DMA transfers
(refer to The 8086 Family User's Manual). Although
these four 16-bit registers have special functions at
times, they may also be used as general-purpose registers for data manipulation. Use of the CC register for
general-purpose functions is not recommended when
both channels are simultaneously used since the chain
bit specifies channel priority.
Most non-DMA interrupts are used to synchronize
channel program execution with some externlll event.
Here channel program execution is suspended and the
channel waits until the synchronizing signal is received
before resuming task program execution. A disk control
example is waiting for the INDEX signal before for-,
matting the track. '
A dummy DMA transfer can be used to implement this
function. This is a synchronized, externally terminated
DMA transfer where no data is actually transferred.
The DMA request (DRQ) signal is held inactive and the
channel executes idle cycles while waiting for either
DRQ or EXT (external terminate) signals.
No bus cycles are executed by the channel during idle
cycles. The channel's EXT input is used to receive the
synchronizing signal. When received, 'the dummy DMA
transfer is terminated and channel program execution
resumes. The dummy DMA transfer can also be viewed
as the iAPX 86/IO's WAIT instruction.
Instruction Set
This concept can also be applied when two channels are
operating. For example, one channel may be waiting for
a synchronizing signal while the other channel is o~
ating. Here the second channel can execute at full speed
since, the first' channel is e~ec1,Jting i~le cycles.
In addition to intelligent, high speed DMA transfers
which make the 8089 well-suited for 110 processing, the
set of S3 instructions is tailored for I/O operations
rather than data processing. Task programs are pri~arily used to prepare for and initiate DMA transfers
and to perform post-DMA status checking. Included in
the instruction set are data transfer, arithmetic, logical
and bit manipulation, program transfer, and processor
control instructions.
One application of this two channel approach is to perform two independent DMA transfers in rapid succession. After the first DMAtransfer, conditions are tested
to determine if the second DMA transfer is performed.
One channel (e.g., channel I) initialize~ its registers for
the second DMA transfer and executes'a dummy DMA
transfer. Next, the other channel (e.g., channel 2) initializ~s its registers f!Jr the first riMA transfer. Channel
2 performs the first DMA trlUlsfer, activates channell,:s
EXT input, and halts. Channell resumes task program
execution and determines whether conditions permit the
second DMA transfer. If the proper conditions are' present, the DMA transfer is performed. The two DMA
transfers are performed in rapid succession because
both channels initialized their registers before either
DM,A transfer was' performed. A single channel implementation must re-initializeits ~egisters after the first
DMA transfer beforeper(orming ~e second DMA
transfer. Therefore, the time between successive DMA
transfers is increased.
"
Data transfer instructions move information between
registers and memory or I/O devices. Movement of data
between any two devices in either address space is easily
accomplished with the MOV instruction. This includes
memory to memory and 110 to I/O trensfers. Arithmetic instructions such as' add, increment, and decrement are provided for simple computations (e.g.,
pointer manipulation) required in 110 processing. The
logical and bit manipUlation instructions are especially
'useful in the 110 environment to mask data and set or
clear ,bits.
Procedure calls and conditional and unconditional
Jumps are provided with the program transfer instruc-'
tions. Jump if masked compare equal or not equal and
jump if bit true or false instructions are also included In
this group. Finally, the processor control instructions
perform test and set while locked operations (semaphore access), define logical DMA bus widths, initiate
DMA transfers, activate the SINTR interrupt output
lines, and halt task program execution.
In the example above, channel I performs two DMA
transfers-a ,dummy DMA transfer and then the second
DMA trailsfer. Registers are initialized for the second
DMA transfer before the dummy DMA transfer is per-
3-73
AFN!)2057A
AP·122
formed. Therefore; all DMA register changes resulting
from the dummy DMA transfer must be accounted for
when initializing the registers. SYnchronized DMA
transfers between I/O and memory update the byte
count register (BC) and the memory pointer register'
(GA or GB). During each two cycle transfer, Be is
decremented during the data fetch bus cycle and GA or
GB is incremented during the data store bus cycle. Since
the dummy DMA transfer never stores the data (DRQ
remains inactive), the memory pointer is never incremented. However, Be mayor may not be decremented
,depending on whether source or destination synchronization, is selected. If source synchronization is
selected, Be is not decremented because the data is not
fetched. However, since the data is prefetched during
destination synchronized DMA transfers, Be is
decremented. This means that Be must be adjusted only
when a destination synchronized DMA transfer follows
the dummy DMA transfer. Here Be must be loaded
with the actual number of data bytes to be transferred
plus one for byte transfers or plus two for word transfers. A byte transfer is defined as the fetching and storing of a single byte. All other cases are considered word
transfers since the net result is that 16 bits of data are
transferred during the two or more bus cycles.
SURFACES
DATA TRACKS
Figure 12. SA4008 Drive with Two Heads Per Surface
cylinder 0 when the outermost track is accessed and at
cylinder 201 when the innermost track is accessed. At
each cylinder position, eight unique data tracks are
accessible, one by each head. By activating the electronics of one read/write head, a single data track is accessed. With 8 heads and 202 cylinders, the SA4008 has
a total of 1,616 tracks.
III. SHUGART SA4008 DRIVE
Sector Format
The Shugart Associates SA4008 disk drive is typical of
Winchester drives now being, used in microcomputer
systems. The unformatted drive capacity is 29 megabytes. Typical of high performance drives, the transfer
rate is 889 kilobytes/second and the average seek time is
65 milliseconds. A summary of the drive's performance
and functional specifications is included, in Appendix A.
Data is recorded on sections of the track called sectors.
The number of sectors per track is a function of the controller design. The SA4008 allows any number of sectors
per track. This design organizes each track into 30 sectors (Fig. 13). The 600 bytes of each sector is divided
into an ID field, data field and gaps. The ID field is a
unique identifier or address used to locate a particular
data record. The data field contains the 512 byte data
record that is read or written by the host processor.
Gaps containing no usable information are inserted
before and after the ID and data fields to allow the drive
and controller el~ctronics time for synchronization and
switching between, read and write modes.
Drive Organization
The Shugart SA4008 drive has two 14-inch disk platters.
The top ana bottom surfaces of these two platters provide four recording surfaces. Each recording surface
contains 404 concentric circular data paths called
tracks. The tracks on each surface are accessed by two
read/write heads which move along the radial distance
of the circular platter (Fig. 12). The two heads are rigidly connected and inovein unison. One read/write head
travels from the outermost track of the surface to the
midway point between the outermost and innermost
tracks. The other head travels from the midway point to
the innermost track. Each of the four surfaces has two
read/write heads (eight total heads). The drive's head
positioning mechanism moves all eight heads in unison
onto 202 discrete positions called cylinders (numbered 0
through 201). The head mechanism is positioned at
I
3-74
Assignment of sequential records to sectors is interleaved using an interleave code of 3 such that logical 'sec~
tors are three physical sectors apart (Fig. 14). Since a'
data record is buffered in local memory, this interleave
scheme allows two sector times to transfer the data
record to or from system memory. This allows the disk
controller to operate at lower system bus priority and
provides enough time to transfer the data record betweert the local buffer and system buffer. When the
8089 has complete use of the system bus, a 512 byte data
record can be transferred in 564 p.sec which is 840/0 of
AFN02057A
AP·122
INDEX
J
SECTOR
J
I"L
1\
n
PHYSICAL SECTOR 0
I
I
I
LOGICAL SECTOR 0
~~
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PHYSICAL SECTOR 1
I
LOGICAL SECTOR 10
I
LOGICAL SECTOR 29
I
I
I
I
I
I"L
I
PHYSICAL SECTOR 29
I
BYTES
Figure 13. Track Format
INDEX
~~
______________________________________________________~
PHYSICAL SECTOR
LOGICAL SECTOR
INDEX
\ I
20
I
1
I
21
11
2
I 12
3
22
I
11
13
23
I
12
13
14
4
14
24
Ih
~------------------------------------~~
PHYSICAL SECTOR
LOGICAL SECTOR
10
0
10
15
~
I
5
I
15
18
17
16
I
25
I
8
I
16
I
26
I
7
I
17
I
27
I
8
I
18
I
28
I
9
I
19
I
29
I )
Figure 14. Interleaved Sector Ordering
quires that the 8089 retain possession of the system bus
for the entire data record transfer after acquiring the
system bus. The 8089 can accomplish this with a LOCK
output signal which is discussed later. The 564 p.sec
data record transfer time allows 108 p.sec to set up the
DMA transfer to or from the system bus, obtl!in possession of the system bus, and prepare for a subsequent
disk sector access.
the 672 p.sec sector time. The selected interleave scheme
permits up to 10 sequential logical sectors to be accessed
per 20.2 millisecond disk revolution.
To access up to 15 sequential logical sectors 'per revolution, an interleave code of 2 could be used. For this
case, logical sectors are two physical sectors apart and
the buffered data record must be transferred to or from
system memory in one sector time (672 p.sec). This re-
3-75
AFN02057A
AP·122
,Disk Drive Interface Signals
The interface signals (Fig. 15) between the SA4008 drive
and the controller are now described. The input control
signals are first described, followed by. the output conJrol signals, and finally the data transfer signals.
The input control signals to the drive are DRIVE
SELECT, DIRECTION SELECT, STEp, HEAD
SELECT, FAULT CLEAR, WRITE GATE, and
. READ GATE. Four drive select signals,DRIVE
SELECT 1 to 4, allow selection of one drive in a multi- .
pie drive configuration of up to four drives. A jumper is
used to select one of the DRIVE SELECT signals and
allows the drive to respond to only one DRIVE
SELECT signal. The DRIVE SELECT 4/SEEK COMPLETE line can be jumper selected as the DRIVE
SELECT 4 signal or SEEK COMPLETE signal (see
DRIVE SELECT 1
DRIVE SELECT 2
DRIVE SELECT 3
DRIVE SELECT 4/SEEK COMPLETE
DIRECTION SELECT
STEP
HEAD SELECT 1
HEAD SELECT 2
HEAD SELECT 4
HEAD SELECTS
FAULT CLEAR
WRITE GATE
READ GATE
TRACK 00
CONTROLLER
INDEX
SA4008
DRIVE
READY
description below). The DIRECTION SELECT and
STEP signals are used to position the read/write heads.
DIRECTION SELECT defines an inward or outward
movement while the STEP line is pulsed. Each pulse
moves the heads one cylinder position. Four head select
signals, HEAD SELECT 1, 2, 4 and 8, are used to select
one of the SA4008.'s eight read/write heads. Four
signals are provided to allow eight optional fixed heads
to be selected. The FAULT CLEAR signal is used to
reset a write fault condition. The WRITE GATE signal
enables data to be written on the selected data track,
while the READ GATE enables reading from the track.
The output control signals from the drive are TRACK
00, INDEX, READY, WRITE FAULT, SEEK COMPLETE, and BYTE CLOCK/SECTOR. The TRACK
00 signal is activated when the read/write heads are
positioned at track 0 (cylinder 0). The INDEX signal is
pulsed once each revolution (20.2 msec) indicating the
beginning of the data track. The READY signal indicates that the driveIs ready to position the read/write
heads, read data, or write data. The WRITE FAULT
signal indicates that a condition which caused improper
writing on the disk occurred. The SEEK COMPLETE
signal is available in a single drive configuration and indicates when the read/write heads have arrived at the
desired cylinder during a seek operation. The DRIVE
SELECT 4/SEEK COMPLETE line can be jumper
selected as the DRIVE SELECT 4 signal (multiple drive
configuration) or SEEK COMPLETE (signal drive configuration). The SEEK COMPLETE signal is selected
with the controller described in this application note.
The BYTE CLOCK/SECTOR line is another jumper
selectable signal. It can be configured as the BYTE
CLOCK' signal (1.12 /Lsec period) or as the SECTOR
signal. The number of SECTOR pulses per revolution is
jumper programmable. The controller described here
requires selection of the SECTOR signal and 30 sector
pulses per revolution.
GROUND
The SA4008 provides four data transfer signals:
WRITE DATA, WRITE CLOCK, READ DATA and
PLO (Phase Locked Oscillator) CLOCK. All of these
are differential signals. The WRITE DATA and
WRITE CLOCK signals are received by the drive and
used to write data on the track. The WRITE DATA
signal provides the data while the WRITE CLOCK
signal is used to sample the data. The READ DATA and
PLO CLOCK signals are transmitted by the drive and
used to read data from the track. The READ DATA
signal provides the data while the PLO CLOCK signal is
used to sample the data. Both the WRITE DATA and
READ DATA signals are in the non-return to zero
(NRZ) format.
Figure 15. SA4008 Interface Signals
A detailed description and timing of the interface
signals can be obtained from the Shugart Associates
manuals referenced in the introduction.
WRITE FAULT
BYTE CLOCK/SECTOR
+
WRITE DATA
- WRITE DATA
+
WRITE CLOCK
- WRITE CLOCK
+
READ DATA
. - READ DATA
+
PLO CLOCK
- PLO CLOCK
.3-76
AFN02057A
AP·122
moved is also determined. The task program writes data
to an octal latch which transmits the DIRECTION
SELECT and STEP signals to the SA4008 drive. By
writing the proper data sequence to the octal latch,
DIRECTION SELECT is asserted and STEP is pulsed
the required number of times. Finally the task program
asserts the drive's head select (HEAD SELECT I, 2, 4
and 8) ~ignals to access the desired track.
Functional Operations
The SA4008 provides three functional operations: track
accessing, write data, and read data. These operations
are initiated and controlled by certain interface signals.
Track accessing (seeking from one track to another) is
accomplished by activating the DRIVE SELECT line
and deactivating the WRITE GATE line. Inward or outward movement is selected by activating or deactivating,
respectively, the DIRECTION SELECT line. The STEP
lme is pulsed once for each track that the read/write
heads are moved.
Format Track
The format track, write data record, and read data
record operations are implemented by a task program
which controls special hardware. Details of the special
hardware are described in the next section.
Writing data to the SA4008 is initiated by activating the
DRIVE SELECT line, selecting the desired read/write
head by activating the HEAD SELECT lines, and providing a clock signal on the WRITE CLOCK line. The
WRITE GATE line is then activated and the data to be
written is transmitted on the WRITE DATA line. The
WRITE GATE line is deactivated to terminate writing.
The timing overview of the format track operation is
presented in Figure 16. The INDEX, SECTOR and
READ DATA signals from the drive and the WRITE
GATE, WRITE DATA, and READ GATE signals to
the drive are shown. 8089 channel activity is also shown.
The READ GATE and READ DATA signals remain inactive during the format track operation.
Reading data from the SA4008 is initiated by activating
the DRIVE SELECT line and selecting' the desired
read/write head by activating the HEAD SELECT
lines. The READ GATE line is then activated and the
data is read on the READ DATA line using the PLO
CLOCK signal to sample the data. The READ GATE
line is deactivated to terminate reading.
Channell begins the format track operation by initializing the registers for the DMA transfer which writes sector O's ID data on the track. Serial/parallel conversion
hardware is used to convert the 8089's parallel data to
serial so that it can be received by the drive. The hardware is initialized with zeros so that when the WRITE
GATE is activated, zeros are written on the track. Next
a dummy DMA transfer is used to wait for the INDEX
pulse which indicates the beginning of the track.
IV. DISK CONTROLLER OPERATIONS
By using an 8089, the disk controller becomes an intelligent interface between the host processor and the disk
drive. The host issues a single high level command for
the desired operation and the 8089 implements the
operation through task program control.
When the INDEX pulse is received, channel I resumes
executjon. The INDEX pulse also activates the WRITE
GATE signal to the drive and zeros are written on the
track. Timing hardware which was started by the SECTOR pulse determines when to stop writing zeros and
begin the write ID field DMA transfer. A synch
character is written on the track before the ID field and
CRC word after thelD field. After the ID data for sector 0 has been written on the track, the hardware
resumes writing zeros.
The 8089-based disk controller described in this application note implements four basic disk control operations:
seek track, format track, write data record, and read
data record. The previous section described the three
functional operations of the SA4008 drive: track accessing, write data, and read data. The controller uses these
three drive operations to implement the four high level
operations. An overview of the four operations is now
presented. This serves as an introduction to the disk
controller before hardware and software details are
described.
Channel 1 next initializes the DMA registers for writing
ID data to the next sector. A dummy DMA transfer is
started to wait for the SECTOR pulse. Channel I now
idles while it waits for the SECTOR pulse. Note that
zeros continue to be written on the track' between ID
data.
Seek Track
ID data for the remaining 29 sectors is written on the
track identically to the first sector. After ID data is written for the last sector, channell deactivateHhe WRITE
GATE signal. WRITE GATE deactivation is delayed so
that zeros are written into the data field. This ensures
that after a data record has been written (in the last sector), the required zeros are present before and after the
data field.
.
The seek track operation is implemented primarily
through task program control with minimal use of
special hardware. B;;ISed on the cylinder which is presently accessed by the read/write head mechanism, the
task program determines which direction (inward or
outward) the head mechanism must be moved. The
number of cylinder positions that the beads must be
3-77
AFN02057A
AP·122
~--------------~~-----------~
INDEX
SECTOR
'--------'
L..----4~'-------~
WRITE GATE
~-----
WRITE DATA
READ GATE _______________________________________~\~\----------------------------
READ DATA
, 8089 ACTIVITY
------------~----~~-----------
..J
CHANNEL 1
CHANNEL 1
CHANNEL 1
Figure 16. Format Track Timing Overview
Write Data Record
The data transfer operations (write data record and read
data record) are implemented with both 8089 channels
(Fig. 17). Channel 2 searches for the desired sector by
comparing the ID field information read from the. track
with the desired ID field information. The comparison
is performed by a hardware comparator; One input of
the comparator accepts ID information read from the
track while the other input accepts the desired ID information transferred from channel 2 using DMA
transfers. Upon locating the desired sector, channel I
transfers the data record to or from the track using
DMA transfers. Both channels perform DMA transfers
using the technique described earlier which allows two
DMA transfers in rapid succession.
Higher data capacity is achieved with this two channel
approach than with a single channel approach. With
two channels, all DMA registers are initialized before
either DMA transfer is started. No register reinitialization is required betwen the DMA transfers for
the two channel approach. To allow for register reinitialization between DMA transfers in the single channel approach, a larger gap between the ID and
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Figure 22. Timing and Control
3-87
AFN02057A
ware and allow the8089's task program to control all
disk drive activity. The status port is implemented with
an 8286 transceiver, has 4030H as an address and allows.
the task program to monitor drive activity. The 8288
bus controller's normal I/O write command is used to
write to the control ports. This prevents the outputs
from glitching, which can occur if the advanced I/O
write command is used.
and BR7 to bit 15. The different relationships between
received and transmitted words are a result of simplified
ready circuitry (to be discussed later).
The ring counter is implemented with a 74193 binary
up/down counter and a 74154 four-to-sixteen decoder.
The drive's PLO clock is used as the count input signal.
The ring counter is reset whenever a SECTOR pulse or a
synch character is detected allowing BRO to be activated
on the next count. A ring counter provides a great deal
of design flexibility. Disk control actions can be fine
tuned with the availability of 16 outputs. Some of these
key actions are reading from and writing to the serial/
parallel conversion circuitry, generating ready and
DMA request signals, and transmitting and checking
CRC words.
Output signals from control port I are used to control
the special hardware. The FORMAT signal is active
when formatting a track. The READ signal is active
when reading an ID or data field. The WRITE signal is
active when writing an ID or data field. The
CHANIlCiiAN'2 signal enables generation of the proper DMA request (DRQ) signal. The ENB-'CCVR
signal enables transceivers when reading or writing sector data or disables them when comparing an ID field.
The SEL_INDEX signal selects the drive's INDEX or
SECTOR pulse for terminating dummy DMA transfers.
An 8254 programmable interval timer provides timing
delays. The 8254 must be used, rather than an 8253, due
to the short output pulse widths (approximately 140
n.sec) of the ring counter. The 8254 has three independent 16-bit counters which are initialized by the software to operate in the hardware triggered strobe mode
(mode 5). Each counter accepts CLK and GATE inputs
and provides a single OUr output. Each counter's
count register is initialized with a count value and when
the GATE input is activated, the count register is decremented with each CLK pulse received. When the count
register is decremented to zero, a pulse is generated on
the OUT output.
Output signals from control port 2. are transmitted
to the disk drive. The head select (HEADI, HEAD2,
HEAD4. and HEAD8), drive select (DRIVEl), seek
track
(DIRECTION
and
STEP),
and
FAULT_CLEAR signals are generated by control port
2.
The status port receives signals from the special hardware and the disk drive. From the special hardware
are COMPAREJTATUS and CRC-ERROR which
indicate the status' of the ID field compare and data
read, respectively. The SEEK_COMPLETE,
DISK-R,EADY, TRACKOO, and WRITEJAULT
signals are from the SA4008.
The three 8254 output signals are designated CNTRO,
CNTRI, and CNTR2 and are associated with their
respective counter. Details of the time delays are discussed later. In general, CNTRO signals the start of an
ID field during the forqtat track operation or the start
of a data field during the write data record operation.
CNTRI signals the end of the DMA transfer when the
format track operation writes the ID field, when the
write data record operation writes the data field, or
when the read data record operation reads the data
field. During both the read or write data record operations, CNTR2 signals the end of the DMA transfer used
to compare the ID field (sector search).
The interface with the disk drive involves both digital and analog signals. All control signals are digital
while the READ-'.DATA, WRITE_DATA,
PLO_CLOCK, and WRITE_CLOCK are differential
signals. Control signals from the drive are resistor terminated and conditioned with 7414 schmitt-trigger inverters. The control signals to the drive are driven with
7406 open-collector inverting drivers. The
READ_DATA and PLO_CLOCK inputs are received
with a 75115 dual differential receiver while the
WRITE-.-DATA and WRITE_CLOCK outputs are
.
driven with a 75114 dual differential driver.
When the 8254's counter 0 times out, the
CNTRO_DETECT flip-flop is set. The
CNTRO-.-DETECT signal enables the 8089'8 DMA
transfer (write ID field or data field) and is reset by
channell's task ,program at the completion of the.
transfer.
A 16-bit ring counter is used to provide bit resolution
timing. Only one of the sixteen outputs is active at any
time. As 16-bit words are being serially received from or
transmitted to the drive, the active ring counter output
corresponds to a bit received or transmitted. When data
is received from the drive, output 0 (BRO) corresponds
to bit 0 of the received word, BR7 to bit 7, and BRI5 to
bit 15. When data is transmitted to the drive, BR8 corresponds to bit 0 of the transmitted word, BR15 to bit 7,
A synch character (OFH for ID field and ODH for data
field) must be detected to begin comparing an ID field
or reading a data field. Only a single AND gate is required to detect the sYnch character since the
DRIVE~AD_GATE signal is activated when the
read/write heads are over a gap written with zeros.
3-88
AFtl02057A '
Ap·122
Upon detection, the SYNCILJ)ETECT flip-flop is set.
The SYNCILJ)ETECT signal enables the 8089's DMA
transfer (write desired ID information or read data
field) and is reset by channell's task program at the
completion of the transfer.
received word must be transferred from the serial/
parallel converter, to the input buffer before being read
(at data bit 0 time). The input and output buffers are
described later.
The external DMA termination signals, EXTl and
EXT2, are used to terminate dummy DMA transfers.
EXTI is generated whenever the 8254's counter 2 times
out (signifying the end of ID field comparison) or whenever the drive's SECTOR or INDEX pulse is detected.
The SEL-INDEX signal which is controlled by the task
program selects which pulse generates EXTl (0 for
SECTOR and I for INDEX). This allows the SECTOR
or INDEX pulse to terminate the dummy DMA
transfer. EXT2 is also generated by either the SECTOR
or INDEX pulse, qualified with SELINDEX.
When an I/O device's transfer ratl: approaches the
8089's maximum transfer rate (1.25 megabytes/sec), the
DMA request (DRQ) input cannot be used to synchronize each byte or word transferred due to the 1.2 ,.sec
maximum (at 5 MHz) latency of this input. The disk
controller uses the 8089's ready signal (and wait states)
to synchronize the SA4008's 889 kilobyte/sec transfer
rate with the 8089's transfer rate. The DRQ inputs are
used to enable DMA transfers while the ready signal is
used to synchronize individual word transfers. Channel
I's DMA request signal, DRQI, is activated when
CNTRO-1)ETECT becomes valid (write ID field or
data field) or 8 bit times after SYNCILJ)ETECT
becomes valid (read data field). The 8-bit delay time
allows the first word to be converted from serial to
parallel before the 8089's DMA transfer begin. Channel
2's DMA request signal,' DRQ2, is also activated 8 bit
times after SYNCILJ)ETECT becomes valid (write
desired ID information). DRQI and DRQ2 are deactivated by the task program upon completion of the
DMA transfer.
Data Transfer
The data transfer section (Fig. 23) provides serial!
parallel conversion, ID field comparison, and CRC
generation and checking functions. Serial/parallel conversion is performed with a 16-bit shift register implemented with two 74S299 8-bit shift registers. Data read
from the drive is converted from serial to parallel while
data written to the drive is converted from parallel to
serial.
The 8284A clock generator Isynchronizes ready signals
from two buses. RDYI is the ready signal from the
Multibus and RDY2 is the ready signal from the local
bus. Both ready inputs are nonnally inactive. When accessing memory or I/O devices, one ready input is activated to complete the bus transfer cycle. Depending on
when the ready input is activated, wait states mayor
may not be inserted. In the disk controller, the 8089 may
require wait states only when accessing the 16-bit disk
data port. Wait states are not required when accessing
other I/O devices or memory devices on the local bus.
For these devices requiring no wait states, RDY2 is generated by the 110 read or write command.
Accessing the disk data port may require wait states to
synchronize 8089 transfers with the drive. For this case,
BRO is used to set a flip-flop. The flip-flop's output
enables RDY2 generation by the 110 read or write command. This ensures that previous data has been transferred to or from the serial/parallel converter before
writing to the output buffer or reading the input buffer,
respectively., Using only BRO involved changing the relationships between ring counter outputs and actual data
bits transmitted to the drive. A transmitted bit 0 corresponds to BR8 while a received bit 0 corresponds to
BRO. This is required since a transmitted word must be
preloaded into the output buffer (at data bit 8 time)
before being transferred to the serial/parallel converter
(to prevent underrun errors). On the other hand, a
A double buffered technique is used here. A 16-bit input
buffer receives read data Jrorn 'the shift register and a
16-bit output buffer transmits write data to the shift
register. Each buffer is implemented with a pair of 8282
octal latches. Two 8286 octal transceivers provide the
interface between the local data bus and the input and
output buffers. These transceivers are enabled when
writing an ID field or a data field or when reading a data
field. They are disabled during the ID field comparison.
The 16-bit comparator is implemented with four 74LS85
4-bit comparators and one 4-input NAND gate. During
the ID field comparison, the transceivers are disabled
allowing the input buffer which contains the ID information read from the disk to drive one. input of the
16-bit comparator while the ID information written by
the 8089 drives the other input. The comparator output
is sampled during each 16-bit comparison. The first mismatch is latched (until reset) for channell's task program to examine later. This permits the length of the ID
field to be any mUltiple of words.
The input buffer, output buffer, and comparator are
all accessed via port 4OOOH. The CRC circuitry uses a
, 9401 CRC generator/checker strapped to use the CRCCCITT polynomial, X16 + X12 + XS + 1. Immediately
after reading the CRC word, the 9401 's error output is
latched allowing channell's task program to examine
the CRC error status later.
3-89
AFN02057A
AP-122
READ--~----------------~----------------------------------------------------------------
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PLO--------------------+---------------------------------------------t--------------_t------+----------------------------+---------------------------------------_t--------------_t------+---------CN1R2--------------+---------------------------------------_t--------------_t-----+--------
READ'" WRITE
WRITE_GATE
BRIS
MiliAo--------------------+---------------------------------+-------------+------+---------~--------------------+---------------------------------------------+--------------+-----+--------
READ + WRITE
------------------+-------------------------,,-------------------f--------------f----,
CNTRO_OET~ ------------:,--,,-c-,-1r------------------------'-----------------+--LO-.-.-.-.'-'T-_-'-'O-"-TE-'-+--'
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DETECT
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SYNCH_OeTEcT------------~------+---------~ 13
LOAD INPUT... BUFFER
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Figure 23. Data Tl'ansfer
AFN02057A
3-90
AP-122
.oK
19E
'R
8
Q"'~--------4----I-------------
WRITE_DATA
18.
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Figure 23. Data li'ansfer
3-91
AFN02051A
AP·122
VI. HARDWARE OPERATION
Now that an overview of the four disk control operations and the details of the hardware components have
been presented, the detailed disk control operations will
be discussed. The interaction of hardware components,
the relative timing of signals, and the data flow are
described for the format track, write data record, and
read data record operations. The seek track operation is
primarily implemented with software. The channel I
and 2 task programs are discussed in the section on software operation. This discussion is focused on how the
hardware operates. While reading the detailed descripbe helpful to refer to the hardware
tion, it
schematics (Figs. 21, 22, and 23).
and ENB-'CCVR signals are activated (Figs. 24 and
25). Next the destination synchronized DMA transfer is
started, the synch character word is prefetched from
memory, and charmell waits for DMA request.
When counter 0 times out, the CNTRO_DETECT flipflop is set (Fig. 25). CNTRO~ETECT is transmitteP.
to the 8089's DMA request input, DRQl. This starts the
8089 bus cycle which writes the synch character to the
output buffer. CNTRO"':'DETECT is also transmitted
to counter I's gate input, GATE I , which allows counter
I to start counting BR3 ring counter pulses. Counter 1
provides the time delay from the start to the end of the
ID field and indicates when to append a CRC word.
may
The WRO signal is activated when the 8089 writes to the
output buffer or the hardware comparator and is used
by the ready circuitry to generate RDY2A. RDY2A is
activated by BRO or WRO, whichever occurs last. This
ensures that previous data has been transferred from the
output buffer to the shift register before writing new
data to the output buffer. When RDY2A is activated,
the write bus cycle completes and the synch character is
latched in the output buffer with the rising edge of
WiW. The synch character is next loaded into the shift
register with BR7 and written to the drive.
Format Track
The format track operation is preceded by a seek track
operation where the proper cylinder is accessed and the
proper head is selected. Upon detecting the INDEX
pulse, the format track operation writes the ID data for
30 sectors and writes zeros everywhere else including the
data field areas. Channel I controls the entire operation
without assistance from channel 2.
The overall timing of the format operation is shown in
Figure 24. The INDEX and SECTOR signals from the
drive and the WRITE_GATE signal to the drive are
shown. Also presented are the signals controlled by
channell's task program-FORMAT, WRITE,
CHANlICHAN2, and ENB-'CCVR. In addition, the
activity of the 8254's counters is shown.
The DMA activity repeats until four words have been
transferred-synch character, first ID word, second ID
word, and zero word. As the zero word is being written,
counter 1 times out after counting four BR3 pulses. The
TRANSMIT_CRC flip-flop latches CNTRI with BR8
and remains active for one word time. The active
TRANSMIT_CRC signal allows a CRC word to be
serially transmitted to the drive from the 9401 CRC
generator/checker. When TRANSMIT_CRC goes inactive, zeros are shifted out of the shift register to the
drive. Zeros are written on the track until the next ID
field since WRITE_GATE is held active until all 30 ID
fields have been written.
Channel I begins the format track operation by initializing the 8254 counters and its DMA registers used to
transfer the ID data to the drive. The FORMAT signal
is activated and a dummy DMA tr~sfer is started to
wait for the INDEX pulse. When the INDEX pulse is
detected (Fig. 24), the hardware activates the
WRITE_GATE signal and zeros are written on the
track. A SECTOR pulse which coincides with the INDEX pulse starts counter O. Counter 0 provides the time
delay from the SECTOR pulse to the start of the ID
field and indicates when to start writing the ID data.
This provides the proper-sized gap between the SECTOR pulse and ID field. '
After the four word DMA transfer, channell initializes
DMA registers in preparation for writing the next sector's ID data and starts a dummy DMA transfer to wait
for the next SECTOR pulse. The same procedure is repeated until ID data has been written for all 30 sectors.
The format track operation concludes with channel 1
deactivating FORMAT, WRITE, CHANlICHAN2,
and ENB-'CCVR. The FORMAT signal deactivates
WRITE.,...GATE which stops writing zeros to the drive.
Detection of the INDEX pulse also resumes channell's
program execution and the WRITE, CHANlICHAN2,
3-92
AFN02057A
Ap·122
TRACK DATA
OH
OH
OH
OH
OH
INDEX
SECTOR
WRITE_GATE
FORMAT
WRITE
CHANt/CHAN2
ENBJCVR
CNTRO ACTIVE
CNTRI ACTIVE
CNTR2 ACTIVE
Ifj
Figure 24. Format Treck Operation
TRACK DATA
WRITE
CHANl/CHAN2
ENB_XCVR
OH
I
101
SYNCH
102
I
CRC
OH
.J
.J
.J
L
L
L
L
L
CNTRO_DETECT
DRQt
m:gT
SY~
RDY2A
LOAD OUTPUT BUFFER WRO
SYNCH
101
102
f1
f1
fl'
LOAD_SHIFT_REGISTER
GATE1
g~~:gT
CLKt~
ZEROS
ZEROS
f1
ZEROS
fl
fl
f
1
n
2
n
3
n
CNTRI
4
~
~
n
L
IL
TRANSMIT_CRC
Figure 25. Write ID Field
3-93
AFN02057A
Ap·122
Write Data Record
The write data record operation consists of two
phases-sector search and write data field. Channel I's
task program supervises this operation with assistance
from channel 2. The sector search phase begins with the
first complete sector that passes under the read/write
heads and ends either when the desired sector is located
or when all 30 sectors on the track have been compared
without a match. If no match occurs, channel I aborts
the operation and reports the error to the host pro, cessor. Upon locating the desired 'sector, the write data
field phase begins. Two types of DMA transfers are performed during the write data record operation-channel
2 transfers the desired ID field information to the 16-bit
comparator and channel 1 transfers the data record to
the drive. '
The overall timing of the write record operation is
shown in Figure 26. The drive signals (SECTOR,
READ_GATE, and WRITE_GATE), signals controlled by 8089 task programs (READ, WRITE,
CHANIICHAN2, and ENB-XCVR), and activity of
the 8254 counters are displayed.
Channell begins the write data record operation by initializing the 8254 counters and its DMA registers used to
transfer the data record to the drive. Next channel 1
starts channel 2, initiates a dummy DMA transfer, and
executes idle cycles. Channel 2 begins execution and initializes its DMA registers used to transfer the desired ID
data to the 16-bit comparator. Next channel 2 starts a
dummy DMA transfer to wait for a SECTOR pulse.
When the SECTOR pulse is detected (Fig. 26), channel 2
activates the READ signal. The destination synchronized DMA transfer is started, ID word 1 is prefetched
from memory, and channel 2 waits for DMA request.
The READ signal activates the drive's READ_GATE
signal and the synch character detection circuitry reads
data from the track. When the synch character is
detected, the SYNCH~ETECT flip-flop is set (Fig.
27). The SYNCH~ETECT signal is used to start
counters 0 and 2 (Figs. 26 and 27). Counter 2 provides
the time delay from the start to the end of the ID' field
and indicates when to check for CRC errors. Counter 0
provides the time delay from the start of the ID field to
the start of the data field and indicates when to start
writing the data field. This provides the proper-sized
gap be~ween the ID lIQd data fields.
SYNC~ETECT
also allows the DMA request
signal, DRQ2, to be activated with BR7. This starts the
8089 bus cycle which writes ID word 1 to one input of
the 16-bit comparator. BRI4 is used to generate the
LOAD-INPUT-BUFFER signal which latche~ the
drive's ID word 1 in the input buffer (from the shift
register). The input buffer drives the other comparator
input. Note that the ENB-XCVR signal is inactive and
the transceivers between the local data bus and the
double-buffered serial/parallel converter are off.,
CNTRO~ETECT is also inactive which deactivates
the output buffer.
The ready circuitry operates in an identical way as dure
ing the format operation. When RDY2A is activated,
the write bus cycle completes and the COMPARE_STATUS is latched with the rising edge of
WRO. The COMPARE_STATUS flip-flop keeps the
first mismatch latched until reset.
Counter 2 was set up to count three BR7 pulses. After
both ID words have been compared, counter 2 times
out. The CNTR2 signal allows the 9401 CRC generator/ ,
checker's error output to be latched in the CRC_ ERROR flip-flop with BR7. Channel 2 halts after the DMA
transfer. The CNTR2 signal is also used to activate
channell's external terminate input, EXTI. Channell
resumes execution, examines the COMPARE_STATUS and CRCJRROR flip-flops, and
deactivates the READ signal.
Upon detecting a match without CRC error, channel I
begins the write data field phase by activating WRITE,
CHANIICHAN2, and ENB-XCVR (Fig. 26). The
destination synchronized DMA transfer is started,. the
synch character word is prefetched from memory, and
channell waits for DMA request. When counter 0 times
out, CNTRO~ETECT is activated and counter I is
started. Counter I provides the time delay from the start
to the end of the data field and indicates when to append a CRC word. CNTRO~ETECT is also transmitted to the 8089's DMA request input, DRQI, which
starts the data record transfer to the drive (Fig. 28). The
data record is written on the track almost identically to
the way that the ID data is written on the track during
the format track operation. The only hardware operational difference -is that more words are written on the
track for the data record than for the ID field. The
earlier discussion explains the operation of Figure 28
and tIlerefore will not be repeated here. The write data
reCOrd operation concludes with channel I deactivating
WRITE, CHANI/CHAN2, and ENB-XCVR.
3·94
AFN02057A
Ap·122
o_H____~IS~Y~NC~H~I~ID_"_I~ID~'~I~c~.~c~I~___o_H____~IS~YN~C~H~F~D~.D_'I~«~~I_W~~~D~I_c~.~C~I____~OH_____
TRACK DATA ____
SECTOR
READ_GATE
..JlO"'-________________
~
11...
_!I~1_ _ _ _ _ _....
~-----~I~\--------I~I-----~L___
WRITE_GATE W_A_IT_E__________________________.....
READ
--.J
WRITE _ _ _ _ _ _ _ _ _ _ _..I-------II~I- - - - - - - , L _ _ _
CHANl/CHAN2
_ _ _ _ _ _ _ _ _ _ _-....I~----~I~I-----~L___
ENB-XCVR ____________________________
I~\-----~L___
~
CNTRO ACTIVE ______________________
CO_U_N_T_=_21______
~----------!
~
:'j
COUNT=N+~.....- - - - - - - - - - - - -
CNTRl ACTIVE
CNTR2 ACTIVE __________~
C;:OUNT=3
I'
Figure 26. Write Data Record Operation
TRACK DATA _~OH~~__~SY~N~C__L-~ID~1~_L__~ID~2~~~C~RC~~____~OH~___
READ
CHANl/CiiAN2
---.l
---------------------
ENB_XCVR ___________________________________________________
~
SYNCH_DETECT _ _ _ _ _ _ _ _ _..1
ID1
ID2
LOAD_INPUT_BUFFER _____________.......___n ..._ _......1
fI
CRC
Z~ROS
t'L-
fI
fI
~
DRQ2 ______________..J
RDY2A ____________________
~
LATCH COMPARE_STATUS WRO
GATE2 SYNCH_DETECT
+
~
2
JL..'__..In
1
CLK2 ~ _ _ _ _ _ _ _ _
CNTR2
LATCH CRC_ERROR
3
.~
~
11...
_ _ _ _ _ _ _ _ _ _ _ _ _ _-..1
fI
Figure 27. Compare ID Field
3 ...95
AFN02057A
Ap·122
TRACK DATA _ _ _'...;;O;,;.H_ _ _L-.;;.SY;.;.N.;;.CH~..LI_·...;;W;.;O.;.;RD:;..l;....!I...J(\L._ _.1-.;.;W.;;.OR.;;;D;.;.N~_~C;;;RC;,......L._.....::OH~_ _
WRITE -.lr--------------\I---------------,L
CHANliCHAN2
J.-------------·~I------------.......,L
ENB_XCVRJ.-------------------~I~I--------------------,L
.Jr-------------ll\--·------------.L
CNTRO_DETECT _ _ _
\~I----------------------~L
CNTRO_
DRQl DETECT
RDY2A _ _ _ _ _..1
LOAD OUTPUT
BUFFER ;----"1'
SVNCH
WORD 1
fI..__......f1
LOAD_SHIFT_REGISTER _ _ _ _ _ _ _...
WORD 2
~~-----------WORD N
ZEROS
ZEROS
ZEROS
~~~~fI~___~flL-___fl--.
I~\------·---------------~L
CNTRl _ _ _ _ _ _ _ _ _ _
--i1~'-1 '~----,~L_
-
.....
fL___
__
Figure 28 •• Write Data Field
Read Data Record
BUFFER signal which latches the first data word in the
input buffer (from the shift register). SYNCILDETECT also allows the DMA request signal, DRQ1,
to be activated with BR7. This starts the 8089 bus cycle
which reads the first data word from the input buffer.
The read data record operation (Fig. 29) is similar to the
write data record operation. Although counter 0 is activated, it is not used during this operation. The sector
search activity by channel 1 and 2 is identical to that of
the write record operation. Only channell's activity
after locating the desired sector is different. Channel 1
reads the data record instead of writing it.
The RDO signal is activated when the 8089 reads the input buffer and is used by the ready circuitry to generate
RDY2A. RDY2A is activated by BRO or ROO,
whichever occurs last. This ensures that data has been
loaded into the input buffer before reading it. Recall
that during the format and write record operations, the
ready circuitry used WRO instead of RDO. When
RDY2A is activated, the read bus cycle completes and
the 8089 stores the data word in memory.
After the desired sector is located without a CRC error,
channel 1 begins the read dilta field phase by activating
READ, CHANlICHAN2, and ENB~CVR. The
source synchronized DMA transfer is started and channel 1 waits for DMA request. The READ signal activates the drive's READ_GATE signal and the synch
character detection circuitry reads data from the track.
When the synch character is detected, the
SYNClLJ)ETECT flip-flop is set (Fig. 30). The
SYNClLJ)ETECT signal is used to start counter 1.
Counter 1 provides the time delay from the start to the'
end of the data field and indicates when to check for
CRC errors.
The DMA activity repeats until all data words have been
read. Counter 1 times out and ,CNTRI allows the 9401
CRC generator/checker's error output to be latched in
the CRCJRROR flip-flop with BR7. The DMA
transfer terminates and channel 1 examines the
CRCJRROR flip-flop. The read data record opera-'
tion concludes with ehannel 1 deactivating READ,
CHANl/CHA~2, and ENB~CVR.
BR14 is used to generate the LOAD-INPUT_
3-96
AFN02057A
AP·122
TRACK DATA
SECTOR
OH
ISYNCHI.D. I.D2
I CRC I
OH
jl~................................................................................~~............................__
READ_GATE ~
LJ
WRITE-GATE W~R~IT~E~............................................................................~
READ
--.J
LJ
WRITE ........................................................................................~~...................................._
CHAN1/CiiAN2 ............................................................--'
ENBJCVR
-------------',
CNTRO ACTIVE
eOUNT=21
~~~--
........,...................._
_~..
eOUNT=N+1
CNTRl ACTIVE ............................................_ ................
CNTR2 ACTIVE ...........................
COUNT=3
'''.
Figure 29, Read Data Record Operation
....~~W~O_R~D~N~'_'
TRACk DATA __~O~H....~~S~YN~C_H~~~W_OR_D_'--'__-J~<~
....
e_RC~~__....O_H...._
...................................----~L__
r---------~I~\
r - -...............---~I~I..........-
..............................~L__
r-...................................~I~I.............................................~L__
','.
WORD 1
WORD N-1
L__
WORD N
eRe
ZEROS
_______~~....--'fl'":--......fl~-fL.
I',
L
~W~~
................................__....
........................__
I~\--....................-
ClKl
, CNTRl
lATCH CRC_ERROR
~--
-,L__
..........
-__ ~~:J_N_"--_- - Jj- l'~ -::..~~:~_Il
.....
r--'
_ ....._ ..............................~,~,-----.....~fl~-~-_
Figure 30, Read Data Field
,3-97
AFN02IJ!i7A
Ap·122
VII. SOFTWARE DES-IGN
head, sector and pointers to the CB and PB2. The only
parameter passed back to the host is status.
The host processor communicates with and starts only
channel 1 and subsequently channel 1 starts channel 2.
Although the 8089's architecture and the controller
hardware permit the host processor to control and start
both channels, this design restricts the host's interactions with channel 1.
Normally the host processor starts channel 2 and is
responsible for initializing parameters in the CB and
PB2. In this design channel I starts channel 2. The CB
and PB2 pointers received from the host in PBI allow
channel 1 to initialize the proper parameters before
starting channel 2.
In a previous section, the linked blocks of the memorybased communication structure are described. The
system configuration pointer and the system configuration block are used only during 8089 initialization after
reset. The channel control block (CB) is used for 8089
initialization and to control channel operation. Before
starting channel operation, the host processor initializes
the channel control word and the parameter block offset
and segment base in the proper half of the channel control block (Fig. 8). This section describes the parameter
and task blocks used in the disk controller design.
In this disk controller design, channel 2 is essentially a
slave of channel I. Prior to starting channe12, channell
initializes channel2's CCW and PB2 offset and segment
base in the second half of the channel control block.
Next channel 1 initializes three parameters in channel
2's parameter block (Fig. 32). The first parameter is the
address of channel2's task program. The function code
and the data buffer's address are the other two parameters. Although parameter block 2's structure allows the
task program and data buffer to reside in system or
local memory, this design places them both in local
memory. Therefore, only TB2 offset and data buffer offset are initialized by channel I and the segment bases
are not used. Channel 2 provides no status information
back to channel I via parameter block 2.
Parameter Blocks
The parameter block for channel 1 is shown in Figure
31. The TBI offset points to channell's task program
which resides in local memory. If the task program
resides in system memory, such as during initial debugging, TBI segment base is also used to generate the
pointer. Note that the 8089's architecture requires that
the first parameter in the PB be the task program's address. All other parameters are user-defined allowing
parameters to be tailored for a specific 1/0 task. Other
PBI parameters that are passed to the 8089 in this application are the data buffer'S address, function, cylinder,
HIGH MEMORY
MEMORY BUFFER SEGMENT BASE
MEMORY BUFFER OFFSET '
FUNCTION CODE
TB2 SEGMENT BASE
}
1----T-B-20-F-F-SE-T---;
--+-
CHANNEL 2
TASK BLOCK
L------LO-W-M~E~M~O~R~Y----~
HIGH MEMORY
PB2 SEGMENT BASE
PB20FFSET
CB SEGMENT BASE
}
--+-
CBOFFSET
HEAD
0
I
I
CHANNEL
CONTROL
BLOCK
SECTOR
CYLINDER
STATUS
FUNCTION CODE
MEMORY BUFFER SEGMENT BASE
MEMORY BUFFER OFFSET
TBl SEGMENT BASE
T810FFSET
Figure 32. Channel 2 Parameter Block
CHANNEL2
} - - __ PARAMETER
BLOCK
CHANNEL 1
} - - - - TASK BLOCK
LOWMEMORY
Figure 31. -Channel 1 Parameter
BI~k
Software Organization
The disk controller software is organized as several
modules with a threi-Ievel hierarchy (Fig. 33). When the
8089 receives a channel attention from the host processor, module TBLKI begins execution (level I). Control is next transferred to one of the level 2 modules (INIT, SEEK, FMAT, WDATA, or RDATA) based on
which function was specified in the parameter block.
For read or write data record functions, TBLK2, which
is the lone level 3 module, -is also executed.
The details of each software module are now described.
While reading the detailed description, it may be helpful
to refer to the ASM89 assembly language source code in
'
Appendix B.
3-98
AFN02057A
Ap·122
CA 1
I
I
Figure 33. Disk Controller Software Organization
Control Program (TBLK1)
After the host processor initializes parameters in the
channel control and parameter blocks, a channel attention is generated which starts module TBLKI. Registers
GA and GC are first initialized. GA is used as a pointer
to the start of local RAM and GC is used as a pointer to
control port 1. The FORMAT, READ, WRITE,
CHANlICHAN2, ENB~CVR, and SEL_INDEX
control signals are generated by writing to control port
I. In general, the controller software uses GA as a base
pointer when accessing variables. in local memory and
GC as a base pointer when accessing I/O ports.
Next TBLKI examines the function code in the parameter block to determine which function has been specified. A unique bit in the function code is used to specify
each of the five functions. This allows the 8089"'s bit test
and branch instructions to be used. If a valid function is
specified, control is transferred to the proper level 2
module. If not, the BAD_CODE error bit in the
parameter block's status word is set, the host is interrupted, and channel 1 halts.
Initialization (lNIT)
signal. Control ports 1 and 2 are first cleared and then
the drive select line is activated. Any pending write
faults are reset. The heads are next positioned over
cylinder 0 and the three 8254 counters are initialized in
preparation for other disk drive operations. Counter 0 is
initialized to count 8 pulses, counter 1 to count 4 pulses,
and counter 2 to count 3 pulses. Finally, the host is interrupted and the channel halts.
Seek Track (SEEK)
The seek track module, SEEK, is used to position the
heads over a specified cylinder and to select one of the
eight read/write heads. TIlls module first checks if the
controller is initialized. Since INIT selects the drive, an
~ctive ready signiu from the drive indicates that the controller has been initialized. If not initialized, the
NOT~ADY error bit in the status word is set, the
host is interrupted, and the channel halts. In order to
minimize unnecessary accesses to Multibus, a status
word in local memory is updated as errors are encoun. teredo Prior to halting, a module will copy this local
status word to the parameter block i!l Multibus's shared
memory.
If the drive is initialized, execution of the SEEK module
continues. The cylinder and head values are copied from
the parameter block to local memory. These variables
The initialization module, INIT, is used to place the
controller in a known state after applying power to the
system. It is also used to reset the drive's write fault
3-99
AFN02051A
AP·122
are stored in local memory to minimize Multibus access.
The cylinder and head values are checked to determine
whether they exceed the maximum values of the drive. If
one or both does, the BAD_CYLINDER ,and/or
BAD--...HEAD error bits are set and the channel halts.
With valid input parameters, head movement is next
determined using a local variable, PRESENT_CYL,
which specifies which cylinder is presently being accessed. By subtracting the present cylinder value from
the new cylinder value, the head movement is determined. A zero result means no movement, a positive
resu~t means'inward movement, and a negative result
means outward movement. A non-zero result also specifies how many cYlinders inward or outward the set of
heads must be moved. Although the 8089 does not have
a subtract instruction, the subtract operation is easily
implemented by complementing the subtrahend before
adding it to the minuend., If head movement is
necessary, the drive's direction. line is activated (l for inward and 0 for outward) and a string ,of pulses equal to
the number of cylinders to be mQved is transmitted to
the drive.
Next the PRESENT_CYL variable is updated and a 20
msec delay loop is executed. This delay is required by
the drive to allow the head positions to stabilize.
Finally, the host is interrupted and channel 1 halts.
Format Track (FMAT)
Before information can be stored on a track, the ID
fields must be written. This is the function of the format
track module, FMAT. Similar to the SEEK module,
controller initialization is first checked. Next the count
registers for the 8254 counters 0 and 1 are initialized to 8
and 4, respectively. A format table is generated which
contains fpur words of information that are written on
the track for each of the 30 sectors. The four words contain the ID synch character, cylinder number, head and
sector numbers, and a word of zeros. The zero word is
used to write zeros on the track between ID fields. This
area contains the gap between ID and data fields, the
data field, the gap after the data field, and the gap after
the subsequent SECTOR pulse. Only one zero word is
needed since the 16-bit shift register continues to shift,
out zeros until it is reloaded.
The format table is generated in three steps: an array
containing, the 30 interleaved sector numbers is constructed, the head numbe~ is loaded into the upper half
of the MC register, and then four words for each ~ector
are assembled in the table. Loading the head number in~
to MC's upper half is effectively done by shifting the
data from MC's lower half to its upper half. Although
the 8089 has no shift instruction, the shift left operation
can be implemented by adding a number to itself. Shifting the head number left 8 bits is easily accomplished
with a loop containing just a few lines of code.
After the format table has been constructed, the information is written to the drive using high speed DMA
transfers. Channell performs the entire format operation without assistance from channel 2.. Dummy DMA
transfers are used to synchronize the format operation
with INDEX or SECTOR pulses received from the
drive. The byte count (BC) register is initialized with the
actual byte count plus two since the dummy DMA transfer decrements BC (refer to the section on Special
Design Considerations). After the synchronization
signal is received, four words from the format table are
written on the track with DMA transfers. The first sector's ID field is written after the INDEX pulse is
detected and the ID fields of the remaining 29 sectors
are written after SECTOR pulses are detected.
After each of the 30 ID fields has been written on the
track, the drive's write fault signal is examined. If a
fault is detected, the BAD_WRITE error bit is set and
the channel halts. If no faults are detected, the channel
halts after all 30 ID fields have been written.
Write Data Record (WDATA)
The WDATA module begins execution whenever a data
record is written to the drive. Channel 1 begins by
transferring the desired sector's ID information from
the parameter block to a local memory buffer. This
local buffer will be used by channel 2 during the ID field
compare. The sector number is checked to determine
whether it exceeds, the maximum value. If so, the
BAD_~ECTOR error bit is set and channell halts. If
no error is detected, the 8254's count registers for
counters 0 and 1 are initialized to 21 and 258,
respectively.
Channel 1 next enters the DMA mode and transfers the
data .record from the system memory buffer to a local
memory buffer. The data synch character is inserted into this local buffer before the data record and a zero
word is inserted after the data record'~ The zero word
causes zeros to be written after the data record and CRC
word.
Preparation, for starting channel 2 is next performed.
Channel2's half of the channel control block is loalied
with the channel control word to start t~s~ program exe-
3-100
AFN02057A
AP·122
cution in local memory and with the offset'and segment
base values of parameter block 2'saddress. Channel2's
task program address, the function code for compare
ID field, and the address of the buffer containing the
desired sector's ID information are then loaded into
channel2's parameter block. Next channell's registers
for the write data record DMA transfer are initialized, a
channel attention signal to start channell is generated,
and channel I starts a dummy DMA transfer. Note that
two must be added to BC since it is decremented durifig
the dummy DMA transfer.
Channell now idles while channel 2 detects a SECTOR
pulse and transfers the desired sector's ID information
to the 16-bit comparator. As channel 2 completes its
DMA transfer and halts, counter 2 times out which terminates channell's dummy DMA transfer. Channel I
resumes execution and examines the compare status and
CRC error flip-flops simultaneously. This is accomplished using the 8089's jump if masked compare not
equal (JMCNB) instruction which uses the MC register
to test both flip-flop outputs and jumps if a mismatch
and/or CRC error is detected. If a match without CRC
error is detected, channel I enters the DMA mode and
writes the data record ,on the disk.
If a mismatch and/or CRC error is detected, the CRC
error flip-flop is checked individually. The detection of
a CRC error causes the BAD~D_CRC error bit to be
set and the channel to halt. Detecting no CRC error
means that only a mismatch occurred. In this case, the
next sector's ID field is compared by starting channel 2
again.
Assuming that no CRC errors are detected, the sector
search is repeated until a match is found or all 30 ID
fields have been compared, whichever comes first. This
technique allows the sector search to begin with the first
complete sector encountered rather than starting at the
beginning of the track when the INDEX pulse is
detected."
After detecting a match and writing the data record on
the track, the drive's write fault signal is examined. The
BAD_WRITE error bit is set if a fault is detected.
Otherwise, channell halts. For the case where all 30 sectors have been searched and the desired sector is not
found, the BAD_SEARCH error bit is set and channel
1 halts.
Read Data Record (ROATA)
Whenever a data record is to be read from the drive the
RDATA module is executed. Much of the actions performed by this module are identical- to that of the
3-101
WDATA module. Channel 1 also begins by transferring
the desired sector's ID information from the parameter
block to a local memory buffer, checking the sector
nUplber, and initializing the 8254 count registers. Identical action continues by updating channel 2's communication blocks, initializing channell's registers for
the DMA transfer, generating a channel attention signal
to start channel 2, and starting a dummy DMA transfer.
Since the read data record DMA transfer is source
synchronized, the BC register is not modified during the
dummy DMA transfer and therefore no adjustment is
needed when initializing BC.
Channel 2 next performs the ID field compare and
halts. Channel I resumes execution when counter 2
times out. Identically with WDATA, channel I examines the compare status and CRC error flip-flop simultaneously. Detecting a match without eRC error causes
channel 1 to enter the DMA mode and read the data
record. The CRC error flip-flop is again examined and
if no error is detected, the data record just read into a
local memory buffer is transferred to the system
memory buffer with DMA transfers and channel 1
halts. If a CRC error was detected during the reading of
the data record, the BAD-DATA-CRC error bit is set
and channel I halts.
Detection of a mismatch and/or CRe error after the ID
field compare causes the eRC error flip-flop to be
checked individually. Encountering a CRC error will set
the BAD~D_CRC error bit and halt channel 1.
Otherwise channel I will repeat the sector search until a
match is found, all 30 ID fields are compared, or a CRC
error is detected. Anyone of these conditions will cause
channell to read the data record and halt or set an error
bit and halt.
'
Compare or Read 10 (TBLK2)
Channel 2's task program, TBLK2, is executed whenever the ID field is compared or read. Note that the code
to read the ID field is included in TBLK2 but is not used
in ihis version of the software. Channel 2 begins by
reading the function cpde to determine whether to compare the ID field or to read it. In either case, the major
actions are similar. Channel 2's DMA registers are initialized, a dummy DMA transfer is started to wait for
the SECTOR pulse, the data transfer DMA mode is
entered, and finally channel 2 halts. During an ID field
compare, the data transfer DMA mode writes information to the 16-bit 'Comparator while during an ID field
reaa, information is read from the serial/parallel conversion circuitry. The BC register must be adjusted during the ID compare but'not during the ID read.
AFN02057A
AP·122
VIII. POSSIBLE ENHANCEMENTS
As discussed earlier, the main purpose of this application note is to present basic design information on b;n~
plementing a disk controller with the 8089 1/0 processor. Although the design described here does not exhibit many intelligent features, the controller does allow
software enhancements to provide the desired features.
The present design requires a separate track seek operation before a read or write data record operation. Adding the capability to perform the seek operation prior
to reading or writing the data record is simple. Separate
bits in the function code word are used to specify each
function. This allows the host to select multiple functions. Recall that the function code is included in the
parameter block and is initialized by the host processor.
The SEEK software module can be modified to examine
the read and write function code bits after completing
the seek operl!tion. If only one function (read or write,
but not both) is specified, control is transferred to the
proper module, either RI>ATA or WDATA. Otherwise,
an error bit is set and the channel halts. Note that this
same technique can be used to perform a seek operation
prior to the format track operation.
Another possible enhancement is the ability to retry an
operation when a CRC error is detected. This feature
applies whenever the ID field (during sector search) or
data field (during read data record) is read. The software can be modified to reposition the heads at the failing sector (by counting SECTOR pulses) and retry the
search or read operation. If several more CRC errors
are detected, the operation is terminated, an error bit is
set, and the channel halts. The number of retries can be
preset in the task program or received as 'a variable from
the host processor via the parameter block.
created which returns the last sector number transferred
to the host. This information can be used by the host
during. an error to determine how many sectors were
successfully transferred.
The ability to perform linked operations might be
useful. For example, a track seek and the reading of five
data records can be followed by another track seek and
the writing of two data records. To include this featUre,
the parameter block could be modified to pass a set of
parameters for each operation or multiple parameter
blocks could be linked together. Variables such as function code, data buffer's address, cylinder, head, sector,
record count, status, and last sector transferred are provided for each operation. As many sets of parameters as
desired can be specified. The controller software would
sequence through these sets of parameters, perform the
required operations, and halt when a special function
code, such as one with no functions selected, is detected.
It was pointe~ out 'earlier that the controller hardware
includes provisions for reading the ID field. In addition,
the software module TBLK2, channel2's task program,
can either compare the ID field or read it, depending on
the function code that chann~l 1 provides" Therefore,
the software can be modified to read the ID field information and verify track position. The 30 ID fields can
also b~ read to verify a format track operation. In addition, sophisticated access methods which r~quire reading the ID field may be implemented.
Another enhancement is to verify a data record just
written to the drive. Here the same circuitry used to
compare ID fields is used to compare data fields. The
good data is written to one input of'the hardware comparator while data read from the drive is applied to the
other input. The first mismatch is latched in the compare status flip"flop for examination later.
The ability to transfer multiple sectors of data is another
desirable feature. A new variable called record count
Illust be added to the parameter block. Sequentiallogical sectors are transferred from the starting logical sector specified in the parameter block. As many sectors as
specified by the record count are transferred. This could
also include head switching from one track to another
(without a seek operation) to access data across track
boundaries.
The software can also be enhanced to manage a file
structure. The host processor would refer to data records by logical file,names rather than physical disk locations (cylinder, head, and sector). By maintaining a disk
directory, the software would determine where the
record is located dr will be located and perform the data
record access. The 8089's general instruction set,
although oriented towards 1/0 processing, supports
data processing of this complexity.
The transferred data is buffered in local memory and
the interleaved scheme allows two physical sector times
for the 8089 to transfer the data from system memory to
local memory (write operation) or from local memory to
system memory (read operation). Data is transferred to
or from the multiple sector system memory buffer starting at the location specified by the parameter block
variables. Another parameter block variable may be
The 8089's flexible memory-based communication
structure allows enhancements to be easily implemented. Modifying the parameter block to accommodate any additional parameters is a simple task. All
variables in the parameter block except for the task program address are defined by the user based on the 1/0
processing task to be performed.
3-102
AFN02057A
AP·122
IX. CONCLUSIONS
This application note has provided a detailed description of a hard diskcontroflel" design based on the Intel
8089 I/O processor. The features provided by the 8089
make it well suited for disk control applications. The
1.25 megabyte/sec DMA transfer rate allows interfacing
with high speed Winchester disk drives. The two channels provided in a single 4O-pin package permit back-toback DMA transfers in rapid succession to minimize
gaps between the ID and data fields .and provide a
higher formatted drive capacity. The 'bit manipulation
instructions simplify the implementation of the disk
controller software, typical of I/O processing software.
All of these features allow the design of a versatile, intelligent and high performance disk controller compatible with high performance microprocessors and disk
drives available today.
An 8089-based disk controller maximizes6verall system
throughput. The host processor and 8089 operate concurrently due to the 8089's local bus whicbis used to access the controller circuitry, task programs, and local
data variables and buffers. Shared system bus accesses
are kept to a minimum which minimizes system bus contention. System throughput is also ,maximized by offloading disk control overhead tasks from the host and
having the 8089 perform these tasks in parallel with the
host. This frees host processor time for data processing.
terfacing. The controller described here has a Multibus
interface with byte swap circuitry that permits interfacing with 8- or 16-bit system memory. Since the
system bus width is defined during 8089 initialization,
no controller hardware or software changes are necessary. Memory based communications allow both 8- and
16-bit host processors to use this controller.
Use of the 8089 promotes modular subsystem development. Memory based communication blocks provide a
simple software interface with the host processor. Once
the parameter block structure is defined, host and 8089
software development proceeds in parallel. Future
enhancements are also .easily incorporated with possible
additions to the parameter block. The hardware interface is also straightforward. A system bus interface,
such as Multibus, allows the use of address signals to
generate the CA and SEL signals received by the 8089
and the use of the interrupt lines to route interrupts
back to the host processor. Such a simple interface permits the disk controller hardware to be developed concurrently with, other hardware subsystems. Also, note
that the entire 8089 subsystem may be changed with
minimal impact, if any, to the host processor software.
For example, the subsystem could be upgraded to support higher capacity disk drives or a bubble memory
subsystem could be implemented using a similar software interface.
Finally, the 8089 allows a compact disk controller to be
implemented. The design here is constructed on a 6-3/4
by 12 inch board with 75 IC packages. By combining attributes of a CPU and an intelligent DMA controller in
a single 4O-pin package, the 8089 I/O processor allows
versatile, high performance, and compact I/O subsys'
tems to be implemented.
A versatile disk controller with many intelligent features
is easily implemented with an 8089. The host initiates a
single high level command to perform track seek, data
record transfers, error checking, and any retries. Other
controller features such as multiple sector transfers,
linked operations, and data record verification can also
be provided. The 8089 provides flexible system bus in-
3-103
AFN02057A
Ap·122
APPENDIX A
SHUGART SA4000 PERFORMANCE AND FUNCTIONAL SPECIFICATIONS
"
No. of Disk Surfaces
No. of Heads
No. of Cylinders
No. of Tracks
Gross Capacity.(M bytes)
Access Time including seek settle
of 20 ms (Milliseconds)
One Track
Average (67 Track Seek)
Maximum (201 Track Seek)
Disk Speed
Recording Mode
Recording Density
Flux Density
Track Capacity
Track Density
Transfer Rate
Sectors
Start Time
4008
4004
MODEL
.
"
..
3-104
2
4
202
808
14.S4
.
20
6S
140
2964 RPM
MFM
SS34 BPI
SS34 FCI
18000 Bytes
172 TPI
7.11 x 106 bits/sec.
889 x Uf bytes/sec.
Programmable
I.S minutes
4
8
202
1616
29.08
20
65
140
AFN02057A
Ap·122
APPENDIXB
8089 MACRO ASSEMBLER
*** 8089-BASED PISK CNTLR ***
ISIS-II 8089 MACRO ASSEMBLER X202 ASSEMBLY OF MODULE HDC89
MODULE PLACED IN :F1:HDCB9.0B~
ASSEMBLER INV,OKED BY: : F1: ASMB9 : F1: HDCB9. AB9 DATE (7-20-81 )
OB~ECT
LINE SOURCE
1
$TITLE(*** BOB9-BASED DISK CNTLR ***)
2
3
BOB9-BASED HARD DISK CONTROLLER
4
5
I
6 HDCB9
SEQMENT
7
8
I
9 $INCLUDE(:F1:EOUB9.AB9)
10
11
12
CHANNEL 1 PARAMETER BLOCK OFFSETS
13
14
15
PBl_TBl_OFF
PBl_TBl_SEQ
PBl_BUFR_OFF
PBl_BUFR_SEQ
PBl_FUNCTION
PBl_STATUS
PBl_CYLINDER
PBl_HEAD_SECTOR
PBl_CCB_OFF
PBl_CCB_SEQ
PBlJB2_0FF
PB l_PB2_SEQ
16
17
18
19
20
21
22
23
24
25,
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU'
EOU
OOH
02H
04H
06H
OSH
OAH
OCH
OEH
10H
12H
14H
16H
26
27
2B
29
CHANNEL 2 PARAMETER BLOCK OFFSETS
I
PB2_TB2_0FF
PB2_TB2_SEQ
PB2J"UNCTION
PB2_BUFR_OFF
PB2_BUFR_SEQ
30
31
32
33
34
35
36
37
38
39
EOU
EOU
EOU
EOU
EOU
OOH
02H
04H
06H
OSH
CHANNEL 2 FUNCTION CODES
EOU
EOU
40
OOH
OlH
41
42
$E~ECT
~105
AFN02OIi7A
Ap·122
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
8089 CHANNEL CONTROL REGISTER BIT MASKS
PORT_TOyORT
BLOCK_TO_PORT
PORT_TO_BLOCK
BLOCK_TO_BLOCK
EGU
EGU
EGU
EGU
OOOOOOOOOOOOOOOOB
0100000000000000B
1000000000000000B
1100000000000000B
TRANSLATE
EGU
0010000000000000B
SOURCE_SYNCH
DEST_SYNCH
EGU
EGU
00001000000000008
0001000000000000B
EGU
EGU
00000000000000008
00000 1OOOOOOOoooa
LOCKED_CONTROL
EGU
00000010000000008
62
63
CHAINED_MODE
EGU
0000000100000000B
64
65
SINGLE_XFER
EGU
0000000010000000B
66
67
68
EXT_TERM_O
EXT_TER"1_4
EXT_TERM_8
EGU
EGU
EGU
0000000000100000B
000000000 1OOOOOOB
0000000601100000B
BC_TERM_O
BC_TERM_4
8C_TERM_8
EGU
EGU
EGU
0000000000001000B
00000000000 1OOOOB
0000000000011000B
UNTIL_MC_TERM_O
UNTIL_MC_TERM_4
UNTIL_MC_TERM_8
EGU
EGU
EGU
0000000000000001B
0000000000000010B
0000000000000011B
WHILE_MC_TERM_O
WHILE_MC_TERM_4
WHILE_MC_TERM_8
EGU
EGU
EGU
00000000000001018
0000000000000110B
0000000000000111B
69
70
71
72
73
74
75
76
77
78
79
80
81
82 $E.JECT
83
·84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
I
GA_SOURCE
GB_SOURCE
i
CONTROLL.ER ADDRESSES
RAM_BASE
ROM_BASE
DATA]ORT
CNTL_PORT_l
CNTL_PORT _2
STATUS_PORT
CHAN23A]ORT
EGU
EGU
EQU
EQU
EGU
EGU
EGU
OOOOH
2000H
4000H
4010H
4021H
4030H
4070H
LD_CNTRO_54
LD3NTR1_54
LD3NTR2_54
MODE __54
EGU
EGU
EGU
EGU
4051H
4053H
4055H
4057H
3-106
AFN02057A
Ap·122
99
RD_CNTRO_54
EGU
4051H
100
RD_CNTR1_54
EGU
4053H
101
RD_CNTR2_54
4055H
EGU
102
103
104
OFFSET VALUES FROM CNTL_PORT_l = 4010H
105
106
CNTL2
EGU
011H
107
STATUS
EQU
020H
108
CA2
EGU
060H
109
110
111
8254 CONTROL WORD BIT MASKS
112
SEL_CNTRO_54
113
OOOOOOOOB
EGU
114
SEL_CNTR 1_54
01000000B
EGU
115
SEL_CNTR2_54
EQU
10000000B
116
117
RDJ-D_LATCH_54
EQU
OOOOOOOOB
118
RD_LD_MSB_54
EQU
00100000B
119
RD_LD_LSB_54
EQU
00010000B
120
RD_LD_WORD._54
EQU
00110000B
121
122
MODEO_54
OOOOOOOOB
EGU
123
MODEl_54
EQU
00000010B
124
MODE2_54
EQU
00000100B
125
MODE3_54
00000110B
EGU
126
MODE4_54
EQU
00001000B
127
MODE 5_54
EQU
00001010B
128
129
BCD_COUNT _54
EGU
00000001B
130
131 .$E-.lECT
132
133
CNTL_PORT _1 8IT MASKS
134
135
OOOOOOOOB
136
CLEAR
EGU
000000018
FORMAT
EGU
137
00000010B
138
EGU
READ
. WRITE
00000100B
139
EGlJ
0000 1 OOOB
140
CHAN1
EGlJ
EQU
000000009
141
CHAN2
00010000B
142
ENB_XCVR
EGU
SEL_INDEX
001000008
143
EGU
144
145
CNTL]ORT 2 BIT MASKS
146
.147
148
00000001B
HEAD 1
EGU
EQU
149
HEAD2
00000010B
EQ'U
150
HEAD4
00000100B
00001000B
151
HEAD8
EGU
00010000B
EGU
152
DRIVEl
00100000B
153
INWARD
EGU
OOOOOOOOB
154
OUTWARD
EGlJ
3-107
AFN02057A
Ap·122
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173 .$E.JECT
174
175
176
177
178
179
180
181
182
183
184
STEP
FAULT_CLEAR
EOU
EOU
01000000B
10000000B
STATUS-P0RT BIT POSITIONS
J
COMPARE_STATUS
CRC_ERROR
SEEK_COMPLETE
DRIVE_READY
TRACKOO
WRITE_FAULT
EOU
EOU
EOU
EOU
EGU
EGU
o
..,1
5
6
7
MASK-COMPARE (Me) PATTERNS
TEST_SECTOR FOUND
EGU
0301H
FUNCTION CODE BIT POSITIONS
INIT_CODE
SEEK30DE
FMAT_CODE·
WRITE_CODE
READ_CODE
EGU
EGU
EGU
EGU
EGU
o
LOOP _CODE
EGU
7
1
2
3
4
,
185
186
187
ERROR CODE BIT POSITIONS
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
EGU
EGU
EGU
EGU
EGU
EGU
EGU
EGU
EGU
BAD_CODE
NOT_READY
BAD_CYLINDER
BAD_HEAD
BAD_SECTOR
BAD_WRITE
BAD_SEARCH
BAD_ID_CRC
BAD_DATA_CRC
o
1
2
:3
..,
.,
6
o
OTHER CONSTANTS
MAX_CYLINDER
MAX_HEAD
MAX_SECTOR
EGU
EGU
EGU
202
8
ID_SYNCH
DATA_SYNCH
EGU
EGU
OFH
ODH
ID_SIZE
WORD_COUNT
EGl}
'I
EGU
256
3-108
30
AFN02057A
Ap·122
211
212
213
214
215
216 $E.JECT
217
218
219
220
221
EQU
WORD_COUNT + WORD_COUNT
EQU
EQU
083H
081H
i .
START_SYS_CCW
STARTJ-OC_CCW
J-------------------------------------------------J
DATA VARIABLE DEFINITIONS
;
---------------------,-----------------------------
222
223
224
ORG
RAM_BASE
225
226
227
228
229
230
231
232
233
234
235
236
237
238
CYLINDER:
HEAD:
SECTOR:
DW
DW
DW
FUN-CTlON:
DW
PRESENT 3YL:
DW
0
FIND_SECTOR:
DW
0,0,0,0
TEMP _STATUS:
DW
TEMP:
DW
°
°
DS
512
239
240
°
°
0
J
IN LOW BYTE
IN LOW BYTE
IN LOW BYTE
0
IN LOW BYTE
241
242
ORG
RAM_BASE + 05FOH
243
244
245
SECTOR_BUFFER:
246
247 $E.JECT
248
;
-----------------------------------------.---------
249
C HAN N E L l
250
251
252
253
;--------------------------------------------------
254
255
CONTROL PROGRAM
256
257
ORG
RAM_BASE + 040H
261
MOVI
MOVI
MOVI
262
MOV
LJBT·
QA,RAM BASE
i
GA = RAM BASE PTR
[GAl. TEMP _STATUS, OH
i STATUS = NO ERROR
GC,CNTL_PORT_li GC = 110 BASE PTR
[GAl. FUNCTION, [PPl.PB1_FUNCTION i GET FUNCTION
CODE
J JUMP IF INIT
[GAl.FUNCTION,INIT_CODE.INIT
L.JBT
[GAJ.FUNCTION.SEEK_CODE.SEEK
258
259 TBLK1:
260
263
264
265
266
3-109 .
JUMP iF SEEK
AFN02057A
Ap·122
267
268
L-.lBT
[GAl. FUNCTION,FMAT_CODE,FMAT
-.lUMP IF FMAT
L-.lBT
[GAl. FUNCTION,WRITE_CODE,WDATA
-.lUMP IF WR ITE
272
273
L-.lBT
[GAl. FUNCTION,READ_CODE,RDATA
.JUMP IF READ
274
SETB
MOV
SINTR
HLT
[GAl. TEMP_STATUS, BAD __CODE ; ERROR. INVALID
[PPJ. PB1_STATUS, [GAJ. TEMP ... STATUS ; FUNCTION
; SET INTERRUPT
269
270
271
275
276
277
278
279 $E-.lECT
280
281
, INITIALIZATION
282
283
284
j--------------------------------------------------
285
286 INIT:
287
288
MOVBI
MOVBI
MOVJilI
[GCl.CLEAR
[GCl. CNTL2,CLEAR
[GCl.CNTL2,DRIVEl
289
290 110:
.JNBT
[GCl.STATUS,DRIVE_ftEADY,I10
ZERO CONTROL PORTS
SELECT DRIVE
291
WAIT FOR DRIVE
READY
292
293
294
RESET WRITE FAULT (IF ANY)
295
296
297
298
-.lNBT'
MOVE I
MOVBI
[GCl. STATUS, WRITE_.FAULT. 115
[GC J. CNTL2, DR I VE 1+FAUL T_.CLEAR
[GCl.CNTL2,DRIVEl
299
300
301
POSITION HEADS OVER TRACKOO
302
303 115:
304 120:
305
306 130:
307
JET
MOVBI
MOVBI
.JNET
JNBT
[GCl. STAT.US, TRACKOO, 140
[GCl.CNTL2,DRIVE1+OUTWARD+STEP
[GCl,CNTL2,DRIVE1+OUTWARD
[GCl. STAtUS, SEEK_.COMPLETE, 130
[GCl.STATUS,TRACKOO. I20
MOVI
MOVI
MOVI
MOVI
[GAl.PRESENT_CYL,OH
[GAl. CYLINDER. OH
CGAl.HEAD,OH
[GAl.SECTOR,OH
308
309 I40:
310
311
312
313
INIT PRESENT 3YL
ZERO VARIABLES
314
INITIALIZE 8254 CNTRO, CNTR1, AND CNTR2
315
316
; ,
317
MOVI
MOVE I
MOVBI
MOVBI
MOVI
MOVBI
31.8
319
320
321
322
GA,MODE_54
[GAl, SEL_CNTRO.,,,54 + RD,.:..LD_WORD_54 + MODE5_54
[GAl. SEL_CNTR1 . . 54 + RD_LD_WORD._.54 + MODE5_54
[GAl. SEL._CNTR2~54+ RD __LD_WORD_54 + I"IODE5._54
GA, LD_CNTRO._54
.
CGAJ.07
i CNTRO "COUNT = 8 PULSES
AFN02057A
Ap·122
323
324
325
320
327
328
329
330
331
332
333
334
335
330 $E.JECT
337
338
339
MOVBI
MOVI
MOVBI
MOVBI
MOVI
MOVBI
MOVBI
[GAl,O
GA,LD3NTR1_54
[GAl,03
[GAl,O
GA,LD_CNTR2_54
[GA1,02
[GAl, 0
MOVI
MOV
SINTR
HLT
GA,RAM_BASE
; GA = RAM BASE PTR
[PPl.PB1_STATUS, [GAl. TEMP_STATUS
; SET INTERRUPT
CNTRl COUNT
CNTR2 COUNT
PULSES
=3
PULSES
SEEK TRACK
340
341
342
343
344
345
340
347
348
349
350
351
352
353
354
355
350
357
358
359
300
301
302
303
304
305
300
307
308
369
370
371
372
373
374
375
376
377
378
;-----------------------------------~--------------
CHECK IF DRIVE IS INITIALIZED
SEEK:
.JBT
SETB
L.JMP
[GCl.STATUS,DRIVE_READY,S10
[GAl. TEMP_STATUS, NOT_READY
S80
.JMP IF DRIVE RDY
SET ERROR BIT
INITIALIZE VARIABLES: CYLINDER AND HEAD
S10:
S13:
S16:
MOV
MOVB
MOV
[GAl. CYLINDER, [PPl. PB1._CYLINDER
GB, [PPl.PB1_HEAD_SECTOR+l
[GAl.HEAD,GB
MOVI
MOV
NOT
INC
ADD
.JNBT
SETB
CHECK CYLINDER PARAM
[GAJ. TEMP,MAX3YLINDER-1
SUBTRACT FROM MAX
IX, [GAl. CYLINDER
VALUE
IX
IX
[GAl. TEMP, IX
[GAl.TEMP+l,7,S13
; .JUMP IF POSITIVE
[GAl. TEMP_STATUS, BAD_CYLINDER ; SET ERROR BIT
MOVI
MOV
NOT
INC
ADD
.JNBT
SETB
.JNZ
[GAl. TEMP, MAX._HEAD-l
IX, [GAl: HEAD
IX
IX
[GAl. TEMP, IX
[GAl.TEMP+l,7,S16
[GAl. TEMP_STATUS, BAD... HEAD
[GAJ.TEMP_STATUS,S80
DETERMINE HEAD MOVEMENT:
OR NONE
3-111
CHECK HEAD PARAM
SUBTRACT FROM MAX
VALUE
.JUMP IF POSITIVE
; SET ERROR BIT
.JUMP IF ERROR
INWARD, OUTWARD,
AFN02057A
AP·122
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
MOV
MOV
NOT
INC
ADD
JZ
JBT
[GAl. TEMP. [GAl. CYLINDER
IX. [GAJ.PRESENT_CYL
IX
IX
[GAl. TEMP. IX
[GAl. TEMP.S60
[GAl. TEMP+1.7.S30
SUBTRACT PRESENT CYL
FROM NEW CYLINDER
JUMP IF 'DELTA ZERO
JUMP IF DELTA NEGATIVE
$EJECT
MOVE HEADS INWARD (POSITIVE DELTA)
S20:
MOV
MOVBI
MOVBI
DEC
JNZ
JMP
BC. [GAJ. TEMP
; GET CYL.INDER COUNT
[GCl.CNTL2.DRIVE1+INWARD+STEP i PULSE
[GCJ.CNTL2.DRIVE1+INWARD
BC
DECREMENT COUNT AND
BC.S20
REPEAT IF <> 0
850
MOVE HEADS OUTWARD (NEGATIVE DELTA)
S40:
MOV
NOT
INC
MOVBI
MOVBI
DEC
JNZ
BC, [GAl. TEMP
; GET AND COMPLEMENT
BC
CYLINDER COUNT
BC
[GCJ.CNTL2,DRIVE1+0UTWARD+STEP i PULSE
[GGJ.CNTL2,DRIVE1+0UTWARD
BC
i DECREMENT COUNT' AND
BC.840
REPEAT IF <> 0
650:
JNBT
[GC J. STATUS, SEEK .. COMPLETE. S50
830:
WA IT FOR SEEK
COMPLETE 8IG
UPDATE PRESENT.CYL VARIABLE
MOV
[GAJ. PRESENT _CYL, [GAl, CYLINDER
SELECT HEAD:
860:
MOV
ORI
MOVB
ACTIVATE HEAD SIGNALS TO DRIVE
IX, [GAJ,HEAD
IX,DRIVEl
[GCJ.CNTL2. IX
20 MSEC TIME DELAY
870:
S80:
MOVI
DEC
JNZ
IX, 3448
IX
IX,S70
MOV
SINTR
[PPJ.PB1_STATUS, [GAJ. TEMP_STATUS
; SET INTERRUPT
3-112
AFN02057A
Ap·122
435
436
437 .E,JECT
438
439
440
441
442
443
444
445
446 FMAT:
447
A48
449
450
451
452
453 F05:
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468 FlO:
469
470
471
472
473
474
475
476
477
.478
479
480
481
482
483
484
485
486
487
488 F15:
489
490
HLT
FORMAT TRACK
1-------------------------------------------------CHECK IF DRIVE IS ~NITIALIZED
,JBT
SETS
L,JMP
[GCl.STATUS,DRIVE_READY,F05
[GAl. TEMP_STATUS, NOT_READY
F50
,JMP IF DRIVE RDY
SET ERROR BIT
INITIALIZE 8254 FOR FORMAT
MOVI
MOVBI
MOVBI
MOVI
MOVBI
MOVBI
GA,LD_CNTRO_54
CGAl,07
[GAl,O
GA,LD_CNTR1_54
[GAl, 03
[GAl,O
CNTRO COUNT
8
CNTRl COUNT = 4
GENERATE BYTE ARRAY, SECTOR(30), WHICH CONTAINS
THE INTERLEAVED SECTOR NUMBERS STARTING AT
ADDRESS = SECTOR._BUFFER + lOOH
MOVI
MOVI
MOVI
MOV
MOV
ADDI
MOV
ADDI
MOV
ADOI
INC
MOV
NOT
INC
ADDI
,JNZ
GA,RAM_BASE
GB,SECTOR_BUFFER + lOOH
[GAl. TEMP,OH
BC, [GAl.· TEMP
[GBl.OH,BC
BC, 10
[GBl. 1H, BC
BC, 10
[GBl.2H,BC
GB,3
[GAl. TEMP
BC, [GAl. TEMP
BC
BC
BC, 10
BC,FIO
GA
J
= RAM
=0
BASE PTR
SECTOR(I)
,J
SECTOR(I+l)
= ,J+10
SECTOR(I+2)
,J+20
r = 1+3
,J = ,J+1
REPEAT IF J <> 10
LOAD MC REGISTER WITH HEAD DATA IN UPPER
BYTE (BITS 8-:-15)
MOVI
MOV
MOV
ADD
DEC
BC,8H
[GAl. TEMP, [GAl. HEAD
MC, [GAl. TEMP
[GAl. TEMP,MC
BC
3·113
SHIFT COUNT '" 8
GET HEAD DATA
SHIFT LEFT BY ADDING
;
TO ITSELF
DECREMENT SHIFT COUNT
AFN02057A
Ap·122
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
JNZ
MOV
$EJECT
GENERATE SECTOR'FORMAT TABLE STARTING
AT ADDRESS = SECTOR_.BUFFER
F20:
MOVI
MOVI
MOVI
MOVI
MOV
MOV
MOVB
OR
MOVI
INC
INC
MOV
NOT
INC
ADDI
JNZ
GB,SECTOR_BUFFER + lOOH
[GAJ.TEMP.OH
IX. SECTOR_BUFFER
[GA+IX+J. ID_SYNCH
[GA+IX+J. [GAl. CYLINDER
[GA+IXJ.MC
BC. [GBl
[GA+IX+J.BC
[GA+IX+J.OH
GB
SECTOR COUNT
=0
SYNCH CHARACTER
CYLINDER
HEAD / SECTOR
ZEROS
INCREMENT SECTOR NO.
POINTER
INCREMENT SECTOR COUNT
& REPEAT IF <> MAX
. [GAJ. TEMP
BC. [GAJ.TEMP
BC
BC
BC.MAX_SECTOR
BC.F20
FORMAT FIRST SECTOR AFTER INDEX PULSE
F30:
MOVI
MOVI
MOVI
MOVI
&
&
&
&
WID
XFER
Move I
SOURCE POINTER
DESTINATION POINTER
BYTE COUNT
GB.SECTOR_BUFFER
GA. DATA_PORT
BC. ID_SIZE + 6
CC.BLOCK_TO_PORT
. + DEST _.SYNCH
+ GB_SOURCE
+ EXT._TERM_O
+ BC_TERM_O
16. 16
DMA CONTROL
16-BIT TO l6--BIT DMA
INIT DUMMY DMA TO
DETECT INDEX PULSE
EXT1 = INDEX PULSE
[GCl. FORMAT+SEL_.INDEX
-------------------WAIT FOR INDEX PULSE
--------------------
XFER
MOVBI
&
&
541 !!<
542
543
544
545
546
& REPEAT IF <> .0
BC.F15
MC. [GAJ.TEMP
START ID DATA TO DRIVE
DMA
[GCl.FORMAT
+ WRITE
+ CHAN1
+ ENB_XCVR
I
OUTPUT FORMAT COMMAND
---------------------------------------
DMA OCCURS HERE
MOVBI
RESET ALL BUT FORMAT
LINE
[GCJ.FGlRMAT
3-114
AFN02057A
Ap·122
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
SEJECT
MOVI
JNBT
SETS
JMP
GA,RAM_BASE
; GA = RAM BASE PTR
CGCl.STATUS,WRITE_FAULT,F35
JUMP IF NO FAULT
[GAl. TEMP _STATUS, BAD._WRITE ; SET ERROR BIT
F50
FORMAT REMAINING SECTORS
F35:
F40:
MOVI
MOVI
MOVI
MOVI
8<
8c
8<
8c
SECTOR_COUNT = MAX-1
DESTINATION POINTER
BYTE COUNT
MC,MAX_SECTOR-1
GA,DATA_PORT
BC, ID_SIZE + 6
CC,BLOCK_TO_PORT
+ DEST.SYNCH
+ GB_SOURCE
+ EXT __TERM_O
+ BC _ TERM._O
DMA CONTROL
INIT DUMMY DMA TO
DETECT SECTOR PULSE
16-BIT TO 16-BIT DMA
XFER
WID
16,16
WAIT FOR SECTOR PULSE
START 10 DATA TO DRIVE
DMA
XFER
MOVBI
8<
8<
8<
[GCl, FORMAT
+ WRITF
+ CHAN1
+ ENB XCVR
OUTPUT FORMAT COMMAND
DMA OCCURS HERE
MOVBI
MOVI
JNBT
SETB
JMP
[GCl,FORMAT
RESET ALL BUT FORMAT
LINE
GA,RAM_BASE
GA = RAM BASE PTR
[GCl.STATUS,WRITE_FAULT,F45
JUMP IF NO FAULT
[GAl. TEMP._STATUS, BAD_,WRITE ; SET ERROR BIT
F50
DECREMENT SECTOR_COUNT AND JUMP IF
<>
0
F45:
DEC
JNZ
MC
MC,F40
F50:
F55:
MOVI
DEC
JNZ
MOVBI
IX,26
IX
IX, F55 '
[GCl,CLEAR
MOV
SINTR
HLT
[PPJ. PBl STATUS, [GAl. TEMP_,STATUS
; SET INTERRUPT
;
3-115
150 MSEC DELAY
(FOR WR ITE GATE
TURN OFF)
CLEAR FORMAT LINE
AFN02057A
Ap·122
603 $E,JECT
604
605
606
607
608
609
610
WRITE SECTOR DATA
;-------------------------------------------------CHECK IF DRIVE IS INITIALIZED
611
612 WDATA:
613
614
615
616
617
618
619 W05:
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637 WiO:
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654 &
655 &
656
657
{;I 58
,JBT
SETB
L,JMP
[GCJ.STATUS,DRIVE_READY,W05
[GA J. TEMP _STATUS, NOT _ ,READY
W50
,JMP IF DRIVE RDY
SET ERROR BIT
INITIALIZE SECTOR VARIABLES
MOV
MOV
MOV
ANDI
MOV
MOVI
MOV
NOT
INC
ADD
,JNBT
SETB
L,JMP
[GAJ.FIND_SECTOR, [PPJ.PB1_CYLINDER ; FIND_SECTOR
GB, [PPJ.PB1_HEAD_SECTOR
FIND_SECTOR + 2
CGAJ.FIND_SECTOR+2,GB
GB,OFFH
SECTOR
[GAJ.SECTOR,GB
CHECK SECTOR PARAM
[GAJ. TEMP, MAX_.SECTOR-1
SUBTRACT FROM MAX
IX, [GAJ.SECTOR
VALUE
IX
IX
[GAJ.TEMP, IX
[GAJ. TEMP+1,7,WIO
; ,JUMP IF POSITIVE
[GAJ. TEMP _STATUS, BAD_.SECTOR ; SET ERROR BIT
W50
INITIALIZE 8254 FOR WRITE DATA
MOVI
MOVBI
MOVBI
MOVI
MOVBI
MOVBI
GA,LD_CNTRO_54
[GAJ,20
[GAJ,O
GA,LD_CNTR1_54
[GAJ, 1
[GAJ, 1
CNTRO COUNT = 21
CNTRl COUNT = 258
TRANSFER DATA FROM SYSTEM BUFFER TO
LOCAL BUFFER
LPD
MOVI
MOVI
ADDI
MOVI
MOVI
XFER
WID
MOVI
GA, [PPJ.PB1_BUFR OFF
GB,SECTOR_BUFFER
[GBl. DATA_SYNCH
GB,2
BC,BYTE_CqUNT
CC,BLOCK_TO_BLOCK
+ GA_SOURCE
+ BC_TFRM_.O
16, 16
[GBJ,OH
3-116
SOURCE POINTER
DESTINATION POINTER
INSERT SYNCH CHAR
IN LOCAL BUFFER
BYTE COUNT
DMA CONTROL
INIT DMA
l6-BIT TO l6-BIT DMA
INSERT ZEROS
AFN02057A
Ap·122
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
.
$E,JECT
PREPARE CHANNEL 2'S eCB AND PB
INITIALIZE CCD
GET CCB ADDRESS
INIT CCW
; INIT PB2 OFFSET
; INIT PB2 SEGMENT
LPD
MOVBI
MOV
MOV
GA, [PPl.PB1_CCB_OFF
[GAl. 08H, START_.LOC_CCW
[GAl.OAH,[PPl.PB1_PB2_0FF
[GAl.OCH,[PPl.PB1_PB2_SEG
LPD
MOVI
MOVI
MOVI
INITIALIZE PB2
GA, [PPl.PB1_PB2_0FF
GET PB2 ADDRESS
[GAl.PB2_TB2_DFF,TBLK2
INIT TB2 ADDRESS
[GAl. PB2_FUNCTION, CMP .. ID ; INIT COMPARE CMD
[GAl. PB2_BUFR_OFF, FIND __SECTOR
INIT BUFFER
. ADDR
SEARCH FOR SECTOR SPECIFIED IN FIND_SECTOR
W20:
MOVI
IX, MAX_SECTOR
SECTOR_COUNT = MAX
W30:
MOVI
MOVI
MOVI
MOVI
GA, SECTOR._BUFFER
GB,DATA_PORT
BC,BYTE_COUNT + 6
CC,BLOCK_TO_PORT
+ DEST_SYNCH
+ GA_SOURCE
+ EXT_JERM_O
+ BC_TERM_O
16, 16
MC,TEST_SECTOR FOUND
SOURCE POINTER
DESTINATION POINTER
BYTE COUNT
8<
8<
8<
8<
WID
MOVI
XFER
MOVB
DMA CONTROL
16-BIT TO 16-BIT DMA
INIT MC
INIT DUMMY DMA TO
DETECT END OF ID
COMPARE
GENERATE CHANNEL 2
CA SIGNAL
[GCl.CA2,BC
-------------------WAIT FOR CHANNEL 2
TO COMPARE ID
,JMCNE
-------------------,JUMP JF NOT FOUND
[GCl.STATUS,W40
$E,JECT
710
711
712 8<
713
714
WRITE SECTOR DATA ON DISK
"
MOVDI
XFER
MOVBI
[GCl,CLEAR
CLEAR READ LINE
. START DMA WR ITE
[GCl, WRITE + CHANl
+ ENB ..XCVR
; OUTPUT WRITE COMMAND
i
,--------------------
; ,DMA OCCURS HERE
3-117
AFN02057A
,
Ap·122
715
716
717
718
719
720
721
722
723
724
725
726
727
NOP
NOP
NOP
NOP
NOP
, MOVBI
MOVI
JNBT
SETS
JMP
TIME DELAY
[GCl,CLEAR
i
CLEAR WRITE
L~NE
GA,RAM_BASE
i
GA = RAM BASE PTR
[GCl.STATUS,WRITE FAULT,W50 i JUMP IF NO FAULT
[GAl. TEMP_STATUS, B"AD __WRITE i SET ERROR BIT
W50
728
NO MATCH ON PRESENT SECTOR
729
730
731 W40:
732
733
734 W45:
735
736
737
738
739
740
I
i
GA = RAM BASE PTR
[GCl.STATUS,CRC ERROR,W45 i JUMP IF NO ERROR
[GAl. TEMP _STATOS, BAD_.ID.eRC i SET ERROR BIT
[GCl,ENB_XCVR
RESET COMPARE STATUS
[GCl, CLEAR
FLIP FLOP
[GAl. TEMP._STATlJS, W50
JUMP IF ERROR
MOVI
JNBT
SETB
MOVBI
MOVBI
JNZ
GA,RAM~ASE
DEC
JNZ
SETB
IX
DEC SECTOR_COUNT 8,
IX,W30
LOOP IF <> 0
[GAl. TEMP STATUS, BAD_,SEARCH i SET ERROR BIT
MOV
LJBT
SINTR
HLT
[PPJ. PB1._STATUS, [GAl. TEMP _.STATUS
[GAJ. FUNCTION+1. LOOP ..,CODE, W20
SET INTERRUPT
741
742 W50:
743
744
745
746
747 lIiEJECT
748
749
750
751
752
753
754
READ SECTOR DA1A
'i-------------------------------------------------CHECK IF DRIVE IS INITIALIZED
755
756 RDATA:
757
758
759
760
761
JBT
SETB
LJMP
[GCl. STATUS, DR IVE_,READY, R05
[GAl. TEMP _STATUS, NOT __ READY
JMP IF DRIVE RDY
SET ERROR BIT
R50
INITIALIZE SECTOR VARIABLES
762
763 R05:
767
MOV
MOV
MOV
ANDI
MOV
768
769
770
MOVI,
MOV
764'
765
766
[GAJ. FIND_SECTOR, [PPl. PBl __CYLINDER i FIND SECTOR
GB, [PPl.PB1_HEAD_SECTOR
FIND_SECTOR + 2
[GAl. FIND.__SECTOR+2, GB
GB,OFFH
SECTOR
[GAJ.SECTOR,GB
CHECK SECTOR PARAM '
SUBTRACT FROM MAX
[GAl. TEMP, MAX SECTOR-l
VALUE
IXICGAJ: SECTOR
3-118
AFN02057A
· Ap·122
771
772
773
774
775
776
777
778
779
780
781 R07:
782
783
784
785
786
787
788
789
790
791 R10:
792
793
794
795 $EJECT
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
NOT
INC
ADD
JNBT
SETB
LJMP
INITIALIZE 8254 FOR READ DATA
MOVI
MOVBI
MOVBI
GA, LD_CNTR1_54
[GA],O
[GAl, 1
CNTR1 COUNT
= 257
ZERO SECTOR BUFFER
MOVI
MOVI
MOVI
MOVI
DEC
JNZ
GA,SECTOR_BUFFER
IX,O
BC,WORD30UNT
[GA+IX+],O
BC
BC,R10
PREPARE CHANNEL 2'S CCB AND PB
LPD
MOV.BI
MOV
MOV
LPD
MOVI
·MOVI
MOVI
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
IX
IX
(GAl. TEMP, IX
[GAl. TEMP+1,7, R07
; JUMP IF POSITIVE
[GAl. TEMP_STATUS, BAD_SECTOR ; SET ERROR BIT
R50
INITIALIZE ceIl
GA, [PPJ.PB13CB.OFF
GET CCB ADDRESS
[GA].08H,START_LOC3CW
INIT CCW
INIT PB2 OFFSET
[GAl. OAH, [PPl. PB 1_..PB2 .. OFF
[GAJ. OCH, [PPJ. PB1]B2.SEG ; INIT PB2 SEGMENT
INITIALIZE PB2
GA, [PPJ.PB1]B2.0FF
GET PB2 ADDRESS
[GAJ. PB2._TB2_0FF, TBLK2
INIT TB2 ADDRESS
[GAJ.PB2_FUNCTION,CMP_ID; INIT COMPARE CMD
[GA]. PB2_BUFR OFF, FIND.. SECTOR
INIT BUFFER
.;
AD DR
SEARCH FOR SECTOR SPECIFIED IN FIND_SECTOR
R20:
MOVI
R30:
MOVI
MOVI
MOVI
MOVI
SECTOR_COUNT
GA,SECTOR_BUFFER
GB,DATA_PORT
BC,BYTE_COUNT
SOURCE POINTER
DESTINATION POINTER
BYTE COUNT
CC,PORT~TO_BLOCK
+ SOURCE_.SYNCH
+ GB_SOURCE
+ EXT_.TFRM .. O
+ BC_TERM ...O
8<
8<
8<
8<
= MAX
WID
3-119
DMA CONTROL
16-BIT TO 16-BIT OMA
AFN02057A
Ap·122
827
828
829
MOVI
XFER
MC, TEST _SECTOR_.FOUND
MOVB
[GCl.CA2.BC
830
831 ,
832
833
INIT MC
INIT DUMMY DMA TO
DETECT. END OF 10
COMPARE
GENERATE CHANNEL 2
CA SIGNAL
834
WAIT FOR CHANNEL 2
TO COMPARE 10
835
836
837
838
,839 $E,JECT
,JMCNE
[GCl.STATUS,R40
,JUMP IF NOT FOUND
840
841
842
843
844
845
846
847
848
849.
850 &
READ SECTOR DATA FROM DISK
MOVBI
NOP
NOP
NOP
XFER
MOVBI
[GCl,CLEAR
CLEAR READ LINE
TIME DELAY
START DMA READ
[GCl,READ + CHAN!
+ ENB XCVR
OUTPUT READ COMMAND
851
852
853
854
855
856
857
858
DMA OCCURS HERE
MOVI
,JNBT
MOVBI
.SETB
,JMP
GA. RAM_BASE
GA = RAM BASE PTR
[GCl. STATUS, CRCo_ERROR, R35 ; ,JUMP IF NO ERROR
[GCl,CLEAR
CLEAR READ LINE
[GAl. TEMP_STATUS+l,BAD_DATA_CRC ; SET ERROR BIT
R50
859
860
861
TRANSFER DATA FROM LOCAL BUFFER ,TO
SYSTEM BUFFER
862
863
864 R35:
865
866
867
868
869 &
MOVBI
MOVI
LPD
MOVI
MOVI
870 &
871
872
873
874
875
XFER
WID
MOVI
,JMP
.;
876
877
878
879 R40:
880
881
882 R45:
[GeJ,CLEAR'
GA,SECTOR_BUFFER
GB, [PPJ.PBl_BUFR_OFF
BC,BYTE_COUNT
CC,BLOCK_TO_BLOCK
+ GA_SOURCE
+ BC_TERM_O
; CLEAR READ LINE
SO~RCE POINTER
DESTINATION POINTER
BYTE COUNT
16, 16
GA,RAM_BASE
R50
DMA CONTROL
INIT DMA
16-BIT TO 16-BIT DMA
GA = RAM BASE PTR
NO MATCH ON PRESENT SECTOR
MOVI
,JNBT
SETB
MOVBI
GA,RAM_BASE
; GA = RAM BASE PTR
[GCl. STATUS, CRC .. ERROR, R45 ; ,JUMP IF NO ERROR
CGI>IJ. TEMP STATUS,BAD 10 CRC ; SET ERROR BIT
[GCl, ENB_XCVR
.-. --j RESET COMPARE STATUS
,
3-120
AFN02057A
\
Ap·122
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
R50:
MOVBI
JNZ
[GCl.CLEAR
.tGAl.TEMP_STATUS.R50
FLIP FLOP
JUMP IF ERROR
DEC
JNZ
SETB
IX
DEC SECTOR_COUNT 8<
IX. R30
LOOP IF <> 0
[GAl. TEMP_STATUS. BAD SEARCH; SET ERROR BIT
MOV
LJBT
SINTR
HLT
[PPl. PB1_STATUS. [GAl. TEMP_ ..STATUS
[GAJ.FUNCTION+l.LOOP30DE.R20
I
SET INTERRUPT
$EJECT
$INCLUDE(:Fl:CHAN2.A89)
;-------------------------------------------------C HAN N E L
2
IjT________________________________________________ _
DETERMINE OPERATION TO BE PERFORMED
°=
~OMPARE
ID FIELD
1 = READ ID FIELD
ORG
RAM_BASE + 0580H
i
TBLK2:
MOV
JNZ
IX. [PPJ.PB2_FUNCTION
IX. RD_ID
GET OPERATION CODE
COMPARE ID FIELD OPERATION
CP _ID:
MOV
MOVI
MOVI
MOVI
&
&
&
&
&
MOVI
XFER
WID
GA. [PPJ. PB2._BUFR OFF
GB.DATA_PORT
BC. ID_SIZE + 2
CC.BLOCK_TO_PORT
+ DEST_SVNCH
+ GA __SOURCE
+ EXT_.TERM_O
+ BC_o,TERM __O
+ CHAINED_1'10DE
GC. CNTL_PORT_l
16. 16
SOURCE POINTER
DESTINATION POINTER
BYTE COUNT
DMA CONTROL
CONTROL PORT POINTER
INIT DUMMV DMA TO
DETECT SECTOR
PULSE
16-BIT TO 16-BIT DMA
WAIT FOR
XFER
MOVBI
[GCJ.READ + CHAN2
S~CTOR
PULSE
START COMPARE ID FIELD
DMA
OUTPUT COMMAND
AFN02057A
939
940
941
DMA OCCURS HERE
HLT
942
943
944 $EJECT
945
946
947
READ ID FIELD OPERATION
948
949 RD_ID:
950
951
952
MOVI
MOV
MOVI
MOVI
953 8<
954 8<
955 8<
956 8<
957 8<
958
959
MOVI
XFER
GA,DATA_PORT
GB, [PPl. PB2_BUFR OFF
BC, ID_SIZE
CC,PORT_TO_BLOCK
+ SOURCE.SYNCH
+ GA_SOURCE
-t. EXT _.1 E:.RM ...O
+ BC._TERM_O
+ CHAINED_.I'lODE
GC,CNTL_PORT_l
960
961
962
WID
16, 16
SOURCE POINTER
DESTINATION POINTER
BYTE COUNT
DI'lA CONTROL
CONTROL PORT POINTER
INIT DUMMY DMA TO
DETECT SECTOR
PULSE
16-BIT TO 16-BIT DMA
.963
964
WAIT FOR SECTOR PULSE
965
966
967
XFER
MOVBI
968 8<
. ; START READ ID FIELD DMA
[GCl, READ
CHAN2
+ ENB XCVR
+
OUTPUT COMMAND
969
DMA OCCURS HERE
970
971
972
HLT
973
974
975 HDCB9
9·76
977
ENDS
978
979
END
AFN02057A
,
APPUCATION
AP-123
NOTE
March 1982
@INTELCORPORIITION. 1982
.
-
•
I,
,"
,
11_
MARCH 1982
ORDER_HR:
I
,
"
INTRODUCTION
This
1.
2.
3.
4.
5.
The purpose of this application note is to provide the
reader with the conceptual tools and factual information needed to apply the iAPX 86/11 to graphic CRT
design. Particular attention will be paid to the require~ents of high-resolution, color graphic applications,
SInce these tend to require higher performance than
those which do not use color.
application note is presented in five sections:
Introduction
Overview of Graphic CRT Systems
Overview of the 8089
Graphic CRT System Design
Conclusions
Section 2 discu'sses typical CRT designs, shows how
performance requirements increase when the capability for color graphics is included, and explains some of
the system bottlenecks that can arise. Section 3 describes the capabilities of the 8089, which can be
brought to bear to resolve these bottlenecks. Section 4
gives detailed information for a color graphic CRT system using the iAPX 86/11 (8086 and 8089).
The iAPX 86/11 is a microprocessor system which contains an 8086 CPU and an 8089 Input/Output Processor.
In the graphic CRT application, the 8089 performs
DMA transfers from the display memory to the CRT
controller, and also serves as a CPU for functions such
as keyboard polling and initialization of the CRT controller chips. The DMA transfers are done in such a
manner that they do not tie up the system bus.
The reader may obtain useful background information
on the 8086 and 8089 from iAPX 86,88 User's Manual.
It would also be helpful to read the data sheets on the
8086, 8089, 2118 Dynamic RAM, 8202 Dynamic Ram
Controller, 8275 CRT Controller, 8279
Keyboard/Display Interface, and 2732A EPROM.
The system is organized so that the 8086 and the 8089
can perform concurrent processing on separate buses.
Using the inherent ability of the 8089 to execute programs in its own 110 space, the 8086 can successfully
delegate many of the chores that have specifically to do
with the CRT display and keyboard, thus reducing the
8086's processing overhead. For these reasons, the capabilities ofthe 8086,8s a CPU can be more fully utilized
to perform calculations dealing with the material to be
displayed. Thus, more complex types of displays can be
undertaken, and the terminal will also be more
interactive.
. OVERVIEW OF CRT GRAPHIC SYSTEMS
Typical DeSign Technique
A typical microprocessor-based CRT terminal is shown
in block diagram form in Figure 1. The terminal consists
CHARACTER
_RA~_
CIINTIIAI.
PROCIIICIII
II
~
lIMA
DOlCE
II
~
IYIITI!II_
CIIT
CONTROLU!R
II
~
CIIT-.roR
a IIOIIITOII
ELECTIIONICS
CIIT TERIiINAL
MRAUEL INPUT/OI/TIIUT
..-
Figure 1. Typical CRT Terminal Block Diagram
8-124
AFN-02172A
AP-123
of a CRT monitor, monitor electronics, a CRT controller and character generator ROM, display memory, a
DMA device, a central processor and associated program memory, a keyboard and keyboard interface, and
serial and/or parallel communication devices.
The primary function of the non-graphic CRT controller
is to refresh the display. It does this by controlling the
periodic transfer of information from display memory
to the CRT screen, with the help of the DMA device.
The central processing unit (CPU) coordinates the
transfer of information to and from the external
devices. When information from an external device is
received by the terminal, the CPU performs character
recognition and handling functions, display memory
management functions, and cursor control functions.
The CPU also interrogates the keyboard interface
device. If a key depression is detected, the ASCII character representing that key is sent to the display
memory and/or an external device.
The design shown in Figure 1 could be implemented
using Intel LSI products. The CPU could be an 8085,
the DMA device an 82)7A DMA controller, the CRT
controller an 8275, the character generator ROM a
2708, program memory ROM a 2716, display memory
2114s (2K x 8), and the keyboard interface an 8279
keyboard controller. These choices would result in a
CRT terminal capable of displaying 25 lines of text
containing 80 characters each.
As the design is upgraded to add color and graphics
capability, performance requirements increase accordingly. The components most likely to require changing
are the CPU, the DMA device, the CRT controller, and
the display memory. Thus, it is desirable at this point to
examine the operation of these components in more'
detail to provide a foundation for graphic system operation. Later we shall give a specific example of a more
complex display, and examine the performance requirements imposed. Figure 2 is a block diagram showing only those components involved with the
non-graphic CRT' refresh function, with more detail
provided regarding the connecting signal lines .
The refresh function proceeds as follows. The 8275,
having been programmed to the specific screen format,
generates a series ofDMA request signals to the 8237 A.
This results in the transfer of a row of characters from
display memory to one of two row buffers within the
8275. From this row buffer, the characters are sent, via
lines CCO-CC6, to the character generator ROM. The
dot timing and interface circuitry is then utilized to
convert the parallel output data from the character
generator ROM into serial signals for the video input of
the CRT.
DISPLAY
MEMORY
t1
{
(
8Y8TEM_
~
At
-a
iCiW
~7
WR
iOli
iIij
aIRQ
HRQ
IIACI(
-
833710
CONTROLLER
LCo-a
ORQ
DACi
VIDEO SIGNAL
CHARACT£R
GENERATOR
127.
cRt
~.
CONTROLLER
CCLl(
OOT
TIMING
AND
INTERFACE
HORIZONTAL SYNC
VERTICAL SYNC
INTENSITY '
1----1IIDEOCONTROU
Figure 2. Components Involved In the CRT Refresh Function
AP·123
1st
Character
2nd
Character
3rd
Character
4th
Character
5th
Character
6th
Character
7th
Character
~--------------------'
00 •••• 000.0000.00 • • • • • 000000000 • • • • 0000 • • • 000.000.0
First Lina of a Character Row
---------------------"1st
CharactAr
2nd
Character
3rd
Character
4th
Character
5th
Character
6th
Character
7th
Character
00•••• 000.0000.00 • • • • • 000000000 • • • • 0000'• • • 000.000.0
o.oooo.oo •• ooo.oo.ooooooooooooo.ooo.~o.~oo.OO.ooo.o
Second Line of a Character Row
1st
Character
2nd
Character
3rd
Character
4th
Character
5th
Character
6th
Character
7th
Character
------------~-----00 ••••000.0000.00 • • • • • 000000000 • • • • 0000 • • • 000.000.0
0.0000.00 •• 000.00.0000000000000.000.00.000.00.000.0
O.OOOO.OO.[]OOO.OO.OOOOODOOOODOO.OOO.OO.OOO.OO.ODO.O
Third line of a Character Row
------------------1st
Character
2nd
Character
3rd
Character
4th
5th
Character' Character
6th
Character
7th
Character
00• • • • 000.0000.00 • • • • • 000000000 • • • • 0000 • • • 000.000.0
o.oooo.uO •• ooo.oo.ooooOOOOQOooO.ooO.OO.ODO.OO.OOO.O
O.OODO.OO.O.OO.Co.ooooooooooooo.ooo.oo.oOO.oO.ooO.O
0.0000.00.0000.00 • • •1.0000000000 • • • • 000.000.00.0.'0.0
0.0000.00.00.0.00.0000.0000'00000.0.0000.000.00.0.0.0
O.oooo.oo.ooo •• co.OOOOOODOOOOOO.OO.ODO.OOO.oo.o.owo
00 •••• 000.0000.00 • • • • • 000000000.00.0000 • • • 0000.0.00
Seventh Line ,of a Character Row
Figure 3. Character Row Display
The character rows are displayed on the CRT one line at
a time. Line count signals LCO-LC3 are applied to the
character generator ROM by the 8275, to specify the
specific line count within the row of characters. This
display process is shown in Figure 3, using a seven·line
character for purposes of illustration. The entire process is repeated for each row of characters in the
display.
At the beginning ofthe last display row, the 8275 issues
an interrupt request via the IRQ output line. This interrupt output is normally connected to the inter~upt input
of the system CPU. The interrupt causes the CPU to
execute an interrupt service subroutine. This subroutine typically reinitializes the DMA controller
parameters for the next display refresh cycle, polls the
system keyboard controller, and eJl,ecutes other appropriate functions.
Performance Requirements
In the example we have discussed thus far, a display
consisting of 25 rows, each containing 80 text charac3-126
ters, with no color or graphic capability, has been assumed. Such a screen can be represented by 80 x 25 =
2000 bytes of data. If the screen is refreshed 60 times
per second, then atotal of 120,000 bytes will need to be
transferred each second from display memory to the·
8275 CRT controller. This figure is well within the capability of the 8237A DMA controller, even allowing for
vertical retrace time and other overhead. In this application then, both the display memory and the system
bus remain available to the system CPU most of the
time, and no bottleneck occurs because of the DMA
transfer process.
The situation is quite different when a high-resolution,
color graphics capability is desired. The performance
requirements are obviously much greater. To derive a
quantitative requirement it is necessary to choose, even
if somewhat arbitrarily, a specific display method and
screen format. The display method chosen for the system described in this application note is called the
virtual-bit mapping technique. When this technique is
used, the graphic material to be displayed is handled on
a character basis. Figure 4 shows the structure of the
text and graphic characters used. The text character is a
AFN-02172A
AP·123
the remaining two bytes are not used. If it is a graphics
character, the second, third, and fourth bytes contain
the color specification for each of the twenty distinct
picture elements (pixels) within the character. Use of
the foreground color is indicated by it one in the respective bit position, while a zero specifies use of the background color.
7 x 5 character in an 8 x 5 matrix. The graphic character
is a 4 x 5 matrix.
The size of a graphic character is the same as the size' of
a text character. In addition, the text characters may be
in color. The resolution (horizontal) fora graphic character is twice as coarse as the dot spacing for a text
character. One of eight colors may be selected for foreground and for background within a particular
character.
The screen format chosen has 80 characters per row
and 48 rows. Thus the resolution (in terms of picture
elements) is 640 x 480 for text characters and 320 x 240
for graphic characters. A full screen contains 80 x 48 =
3840 characters. Thus; a single frame ofthe display can
be represented by 3840 x 4 = 15,360 bytes. If the screen
were updated 60 times per second, the CRT refresh
function would require a DMA transfer rate of 15,360 x
60 = 921,600 bytes per second.
Figure 5 shows how the display character can be specified using four bytes. The first byte determines whether
the character is a text character or a graphic character,
and specifies the colors for foreground and background. If it is a text character, the second byte
specifies the character with a seven-bit ASCII code, and
LINE COUNT (LCo-LC2)
COL3
COL2
COL1
000
1
1
I
l
001
1
I
010
1
1
1
I
I
1
I
011
100
1
I
1
I
COLO
:
ROW A
~
I
ROWB
I
I
I
ROWC
I
I
I
:
I
1
I
I
ROWD
ROWE
(B) GRAPHIC CHARACTER
(A) TEXT CHARACTER
REPRESENTING THE LETTER A.
Figure 4. Character Structure
1
0
1M
IFC21FC11FCOlBC21BC11BCoI
~ '---y---'
I
I
II
I
BACKGROUND COLOR (1 ., 8)
I
FOREG~OUND COLOR (1
MODE-O
1
~
~
01 8)
ALPHANUMERICS
GRAPHICS
COLOR CODE
000
001
COLOR
iii:ACK
010
011
RED
GREEN
YELLOW
100
aWE
101
110
111
MAGENTA
CYAN
WHITE
v-.,...--.. .I
ROW B GRAPHICS
ROW A GRAPHICS
1 = FOREGRDUND COLOR
o ~ BACKGRDUND CDLOR
(b) B,..1
NDTE: RBI IS INTE~nDNALLY MOVED TD BYTE 3 SUCH THAT REPRESENTAnDN DF A BLANK
CHARACTER FOR EITHER TEXT DR GRAPHIC IS THE SAME.
I
RDI
I R~ I RC31'RC21 I
ReI
~
RCO
RB3
, ____---._-----'I'-.,-J
I
I
I
ROW B GRAPHICS
I
RDW C GRAPHICS
I
RDW D GRAPHICS
(e)
.,..2
~-_................ . - _ - - , I ' - - . , . - /
I
I
ROW D GRAPHICS
I
I
RDW E GRAPHICS
I
ROW B GRAPHICS
(d) a,..3
Figure,5. DIsplay Character SpecIficatIon (Cont.)
AI'N-02172A
AP-123
System Bottlenecks
It can be seen from the above calculation that nearly
one megabyte of data must be transferred per second to
effect the CRT refresh function alone. Even with the
fastest available DMA controllers, this represents the
llU\ior part of the bandwidth for such devices. When the
design shown in Figure I is used, the system bus must
also be used by the CRT terminal processor for such
functions as keyboard polling and communication with
external devices. In addition, any changes made to the
material being displayed would require use of the system bus for the purpose of storing the new material in
the display memory, and possibly also for access to
system memory during the calculation process. It is
easy to see, therefore, that severe bottlenecks can occur in terms of system bus utilization. Problems involving bus contention could also be difficult to resolve.
Display underruns could become difficult or impossible
to avoid in some cases, such as when graphics com~utations require excessive use of the system bus.
The situation can be improved substantially if provision
is made for concurrent processing. One CPU can be
doing calculations on the material to be displayed,
while another CPU can be managing the CRT terminal
functions and the 110 devices simultaneously. Local
buses can be used for access to the respective program
memories, with the system bus used only for transfer of
new display data and for communication between the
two processors.
The iAPX 86111 offers a convenient and economical
way of implementing this multiprocessing approach. In
particular, the 8089 has unique capabilities that simplify
the design process.
OVERVIEW OF THE 8089
Architectural Overview
The 8089 Input/Output Processor is a complete 110
management system on a single chip: It contains two
independent 110 channels, each of which has the, capabilities of a CPU combined with a programmable DMA
controller.
The DMA functions are somewhat more flexible than
those of most DMA controllers. For example, a conventional DMA controller transfers data between an
110 device and a memory. The 8089 DMA function can
operate between one memory and another, between a
memory and an 110 device, or between one 110 device
and another. Any,device (110 or memory) can physically reside on the system bus or on the 110 bus. The bus
width for the source and destination need not be the
same. If the source, for example, is a 16-bit device,
while the destination is an 8-bit device, the 8089 will
disassemble the 16-bit word automatically as part of the
DMA transfer process. The transfer can be synchronized by the source, by the destination, or it can be free
running. The 8089 can effect data transfers at rates up to
1.25 megabytes when a 5 MHz clock is used.
Unlike most DMA controllers, the 8089 uses a twocycle approach to DMA transfer. A fetch cycle reads
the data from the source into the 8089, and a store cycle
writes the data ,from the 8089 to the destination. This
two-cycle approach enables the 8089 to perform operations on the data being transferred. Typical of such
operations are translating bytes from one code to an- ,
other (for example, EBCDIC to ASCII) or comparing
data bytes to a search value.
A variety of conditions can be specified for terminating
DMA transfers, including single cycle, byte count (up
to 64K), external event, and data-dependent conditions, such as the outcome of a masked compare
operation.
The CPU in each channel can execute programs in the
system space (from a memory on the system bus) or in
the 110 space (from a memory on a separate 110 bus).
Thus, complete channel programs can be run by the
8089 without tying up the system bus or interfering with
the operation of the system CPU. Figure 6 is a simplified block diagram of the 8089, showing how the 8089
interfaces with these two buses.
The programs that the 8089 executes may be preexisting
programs stored in ROM or EPROM, or they may be
programs prepared for the 8089 by the system CPU. In
the latter case, the programs are typically in modular
form, contained in "task blocks" that the system CPU
places in a memory location accessible to the 8089.
During normal operation, the system CPU then directs
the 8089 to the various task blocks, according to which
programs are to be executed. The details of how this is
done are given below under Software Interface.
The 8089 has an addressi,ng capability of 64K bytes in
the liD space, and thus can support multiple peripherals, as illustrated in Figure 7. In the system space,
the 8089 supports, I-megabyte addressing, and is di.
rectly compatible with the 8086 or 8088, and with Intel's
Multibus. The 8089 operates from a single +5V power
source, and is housed in a standard 4O-pin, dual in-line'
package. The instruction set for the 8089 lOP is specifically designed and optimized for liD processing 'and
controL In addition to being able to execute DMA
3-129
AFN-Cl2172A
H08TCPU
SYSTEM IUS
EXTI
CPU
"CHANNELl"
DRQ1
SINTRI
CA
SEL
SINTR2
CPU
..
,"CHANNEL 2"
EXT2
DRQI
LOCAL UO BUS AND MEMORY
/
Figure 6. Simplified Block Diagram
transfers under a wide variety of operating conditions,
the 8089 can perform logic operations, bit manipulations, and elementary arithmetic operations on the data
being transferred. A variety of addressing modes may
be, used, including register indirect, index auto. increment, immediate offset, immediate literal, and indexed.
The register set fdr the 8089 is shown in Figure 8. Each
channel has an independent set ofthese registers, not
3-130
of the 8089
accessible to the other channel. Table 1 gives a brief
summary of how these registers are used during a program execution or during a DMA transfer. Four of the
registers can contain memory addresses which refer to
either the system space or the I/O space. -These registers each have an associated tag bit. Tag = 0 refers to the
system space and tag = 1 refers to the I/O space. More
details on how the registers are used are given belovy as
part of the Sbftware Interface section.
AFN-cJ2172A
AP·123
lOP
-
DR01,EXf1
80881
CPU
1271
CRT
CONTROLLER
11271
FLOPPY
DISK
CONTROLLER
8271
KEYBOARD
CONTROLLER
Figure 7. 1/0 System with Multiple Peripherals
logic with the host CPU. They reside on the same bus,
sharing the same system address buffers,-data buffers,
and bus timing and control logic. The 8089 requests the
use of the bus by activating the request/grant line to the
host CPU. When the host relinquishes the bus, the lOP
uses all the same hardware, and the host CPU is restricted from accessing the bus until the 8089 returns
control ofthe bus to the host CPl,].
USER PROGRAMM.\BLE
•
TAG l'
B P ADDRESS A (OA)
G.P ADDRESS 8 (08)
P ADDRESS C (OC)
TASK POINTER (TP)
Q
'""'"----- 1·BIT POINTER TO EITHER UO OR SYSTEM MEMORY SPACE
"
INDEX (IX)
•
BYTE COUNT (BC)
MASt<
COMPARE (Me)
CHANNEL CONTROL teC)
The local configuration is a very economical configuration in terms of hardware cost, but it does not allow
con~urrent processing, and thus it is not able to really
take advantage of the 8089's capabilities for independent operation. In the local configuration, the 8089 acts
as a local DMA controller for the CPU, providing enhanced DMA capabilities and I-megabyte addressing.
NON USER PROGRAMIiABLE
(ALWAYS POINTS TO SYSTEM MEMORY)
1"
I
I
PARAMETER POINTER (PP)
CHANNEL CONTROL POINTER (CP)
P
I
Figure It. 8089 Register Set
,For applications such as the color graphics terminal,
where system bus utilization (and,other overhead) due
to I/O processing would clearly be excessive in the local
configuration, it is far more desiTable to use the remote
configuration, illustrated in Figure )0. The two processors both access the system bus, but each may have its
own local bus in addition. Each of the processors may
execute progI'ams from memory on its own local bus, or
System Configurations
The hardware relationship between the host -CPU and
the 8089 can take one of two basic forms-local configuration' or remote confiiuration. In local configuration (Figure 9) the lOP shares the system bus' interface
3--131
AFN-02172A
Table 1. Channel Register Summary
Register Size
Program
Access
System
or 1/0
Pointer
Use,by Channel Programs
Use In DMA Transfers
,
Update
Either General, base
GB
20
20
Update
Either General, base
Source/destination pOinter
GC
20
Update
Either General, base
'Translate table pOinter,
TP
PP
20
20
R,eference
IX
16
Update
N/A
General, auto·increment
BC
16
Update
N/A
General
Byte counter
MC
16
Update
N/A
General, masked compare
Masked compare
CC
16
Update
N/A
Restricted use recommended
Defines transfer options
GA
Update
Source/destination pOinter
Either Procedure return, instruction pointer Adjusted to reflect cause of termination
System Base
N/A
N/A
SYSTEM MEMORY
BUS
CONTROLLER
8086
OR
8088
cPU
LATCHES!
TRANSCEIVERS
PERIPHERAL
P1
PERIPHERAL
P2
I
Fi~ure
9. ,CPU and lOP in Local
3-132
Conflg~rlltion
,
AFN-02172A
AP.123
Figure 10. CPU and lOP In Remote Configuration
on the shared system bus. This creates a much more
flexible arrangement. Concurrent processing may be
used, and it is not necessary to synchronize the processors. An 8086, for example, may run at 8 or 10 MHz
while the 8089 operates at 5 MHz. The specific terminal
design described later in this application note makes
use of one additional technique to further decouple the
operation of the tWo processors. This is a ,dual-port
RAM; which is located between the system bus and the
8089, and serves as display memory and as storage for
the task blocks created by the 8086 CPU. Details on
how this dual-port RAM operates are given below in the
sections describing the terminal design itself.
Software Interf,ce
Although the 8089 is an intelligent device which· has a
great deal of ability to function independently· when
managing the course of VO operations, it typically
operates under the overall supervision of the host CPU.
Figure 11 illustrates the method of communication between the CPU and the lOP. The CPU communicates
to the lOP by placing messages in memory and activating the lOP's channel attention (CA) input. The lOP
communicates to the CPU by placing messages in system memory and making an interrupt request on one of
its system, interrupt request (SINTR-I or SINTR-2)
outputs.
The messages in memory take the form of linked
blocks. These blocks are of the following five types:
1. System Configuration Pointer (SCP)
2. System Configuration Block (SCB)
3. Channel
,
, Control Block (CCB)
4. Parameter Block (PB)
5. Task Block (TB)
The SCP and SCB blocks are.used by the CPU (only
after reset) to initialize the 8089. The CCB, PB and TB
'blocks are used when the CPU wishes to instruct th,e
AFN-G2172A
..
AP-123-
,
,~
"
'
/
CHANNEL ATTENTION
CPU
11IN
III!IIORY
lOP
INTERMWT
Figure 11. CPU/lOP Communication
lOP to perform a particular sequence of operations.
Figut:e 12 shows these five blocks and how they are
linked. The SCP, SCB, CB, and PB must be in memory
which is accessible from both the CPU and 8089 (either
system memory or for this application note, d'¥ll-port
memory). TheTB may be in either system or 8089 local
memory.
The system configuration pointer is always found at the
same location (FFFF6) in the system memory. The first
time channel attention is activated (after an lOP reset)
the 8089 reads the system configuration pointer from
this location. The SYSBUS field contains only one significant bit (Bit 0), designated by the letter W. If W = 0,
the system bus is an 8-bit bus. W = I denotes a 16-bit
system bus. The lOP first assumes an 8-bit bus and
reads the SYSBUS field. It stores the information as to
the physical width ofthe system bus, then immediately
uses this information in the process of fetching the'next
rour bytes, which contain the address of the system
configuration block.
The addresses used to link blocks are standard iAPX 86,
88 pointer variables, each occupying two word locations in system memory. The lower-addressed word
contains offset" which is added to th~ segment base
value (left-shifted four places) found in the upperaddressed word to derive the complete 20-bit physical
address in system memory. If the block is in an I/O
memory (a~ a task block might be), only the offset value
is used.
'
an'
After thus deriving the address of the system cd1lfiguration block, the lOP reads this block, starting with the
system operation command (SOC) field. Bit I of the
SOC field specifies the request/grant mode (used in
local configuration or in multiple-lOP systems). Bit 0
specifies the I/O bus width (designated!). When I = 0,
the I/O bus is an 8-bit bus. I = I denotes a 16-bit I/O bus.
The lOP then proceeds to read the double-word pointer
to the channel control block, converts it to the 20-bit
physical address, and stores it in an internal register
(the channel control pointer register). This register is
loaded only during initialization and is not available to
channel programs. For this reason the channel control
block cannot be moved unless the lOP is reset and
reinitialized.
The initialization is complete when the channel control
pointer has been stored. The lOP indicates this by clearing the busy flag in the channel I control block (which
must beset by the host CPU before the initialization
sequence began). The host CPU can monitqr this flag to
determine when initialization is complete, and then to
initialize any other 80898 ~ the system.
It is the responsibility of the host CPU to make ,sure that
the SCP and SCB have the proper contents before
issuing the channel ~ttention (CA) that begins the initialization sequence. After initialization, the host CPU
must also assure that the channel control block (CCB) ,
parameter block (PB), and task block (TB) all hav:e the
proper contents, before issuing a subsequent CA.
The CA may be issued in the form of an I/O write
command to the address of the lOP on the Multibus.
Figure 13 shows a typical decoding circuit,for this write
command. The lOP actually occupies two consecutive
address locations on this bus, because the AOline is tied
to the select (SEL) input of the 8089. A zero on the SEL
line specifies lOP channel I for the impending operation, while a one specifies 'lOP channel 2.
3-134'
AFN-02172A
AP-123
RESET
I
f'
rL
•
SYSBUS
sca
ADDRESS
sca
RELOCATION
FFFF8
FFFF8
SYSTEM
CONFIGURATION
POINTER
FFFFA
I
INITIALIZAnON
I
r-
L-
ADDRESS
CB
RELOCATION
I
BUSY
ADDRESS
Ta
RELOCATION
SYSTEM
CONFIGURATION
BLOCK
}~~a~_,~
CCW
r
PB
ADDRESS
L-
PB
RELOCATION
I
BUSY
Ta
SOC
ca
CHANNEL 1
}--,
CCW
PB
ADDRESS
PB
RELOCATION
W
lOP TASK
PROGRAM
.......
~ ....PARAMETER BLOCK
T
T
TASK BLOCK
':-
T
"':-
T
Figure 12. Lin!etween the system bus and
the 8089. This dual-port RAM contains the display
memory and also contains the Iink.ed message blocks
used for communication between the 8086 and the 8089.
The system configuration then becomes that shown in
Figure 21. The dual-port RAM pecomes'the only data
path between the 8086 and the 8089. Access to this
memory is time-shared between the 8086 and the 8089,
with the 8089 taking less than 50% of, the total time
available. Since the 8089 do~s not access the system
bus, the ,host system can enjoy complete freedom to
allocate its resources between its own local bus and the
system bus. The CPU and the lOP can operate
asynchronously, with the 8086 running on an 8 MHz
clock and the 8089 on a 5 MHz clock.
CA _ _ _ _ _ _ _ _ _ , 1 ClK MIN:LU- RECOGNIZED
Figure 18. Reset and Channel Attention Timing
The division of responsibility between the 8086 and the
8089 is then very clearly defined. The, 8086 initializes the
8089 and specifies the task parameters, storing them in
3-138
AFN-02172A
AP·123
DACK~
(DECODED
I/O ADDRESS)
YALID I/O ADDRESS
PRESENT
\\-.-------
NOTES
1) INDICATES THE NUMBER OF (OLE CLOCKS INSERTED AFTER T4 OF THE STORE CYCLE BEFORE THE NEXT TRANSFER CYCLE
BEGINS IF ORO IS RECEIVED BEFORE THE RISING EDGE OF ClK IN THE CURRENT FETCH CYCLE, THE NEXT FETCH BEGINS
IMMEDIATELY AFTER THE CURRENT STORE
2) IF THE 8089 IS IDLE WHEN ORO IS RECOGNIZED, FOUR OR FIVE MORE IDLE CLOCI( CYCLES OCCUR BEFORE THE
ASSOCIATED TRANSFER CYCLE BEGINS (ORO IS lATCHED ON THE RISING EDGE OF ClK )
3) TO PREVENT THE START OF THE I\1EXT TRANSFER CYCLE, ORO MUST BE BROUGHT lOW BY THE RISING EDGE OF ClK IN T4
OF THE CURRENT FETCH (FOR B/B~W SOURCE SYNCHRONIZED AND W~B/B DESTINATION SYNCHRONIZED IT MUST BE
lOW BY THE RISING EDGE OF ClK IN THE FOURTH CLOCK OF THE CURRENT BUS CYCLE INCLUDING WAIT STATES)
Figure 19. Source-Synchronized Transfer Cycle '
..
..
TRANSFER CYCLE 1
FETCH BUS CYCLE 2 2
STORE BUS CYCLE 1
stORE aus CYCLE 2
C~k
r--\\\\\\\ ,
DRO'
(FROM I/O DEVICE)
ID~
(DECO~D
I
DACK
I/OAI/DRE_SS,;,)_ _ _ _ _..J
CLOCKS 3
VALID 1/0
ADDRESS PRESENT
\
I'
L _ _ _ _ _ _ _ _ _- ._ _...J.
L
NOTES
1) FIRST DMA FETCH CYCLE OCCURS IMMEDIATELY AFTER THE lAST TASK PROGRAM INSTRUCTION IS EXECUTED
2) FETCH CYCLE 2 BEGINS (MMEDIATElY AFTER STORE CYCLE 1
,3) INDICATES THE NUMBER OF IDLE CLOCKS INSERTED AFTER T4 OF THE FETCH BEFORE STORE CYCLE 2 BEGINS IF ORO IS
RECEIVED BEFORE THE RISING EOGE OF ClK IN THE CURRENT STORE CYCLE, THE NEXT STORE BEGINS IMMEDIATELY
AFTER THE NEXT FETCH
4) IF THE 8089 IS IDLE WHEN ORO IS RECOGNIZED, FOUR OR FIVE MORE IDLE CLOCK CYCLES OCCUR BEFORE THE
ASSOCIATED STORE CYCLE BEGINS (ORO IS LATCHED ON THE RISING EDGE OF ClK)
5) TO PREVENT TI:IE NEXT STORE CYCLE FROM OCCURRING, ORO MUST BE BROUGHT lOW BY THE RISING EDGE OF ClK IN T4
OF THE CURRENT STORE (FOR B/B->W SOURCE SYNCHRONIZED AND W->B/B DESTINATION SYNCHRONIZED, IT MUST BE
lOW BY THE RISING EDGE OF ClK IN THE FOURTH CLOCK OF THE CURRENT STORE CYCLE INCLUDING WAIT STATES)
•Figure '20i Otistinatlon-Svnchronized TratIsfir Cycle
3-139
AFN-02172A
AP-123
32K BYTE
2732A-2
EPROM
-
8K BYTE
2141-4
SHAM
-
~
.
CPU
-
RESIDENT
BUS INTER·
FACE
8289
BUS
ARBITER
- -I
i~
I-
zw
....
Q
MULTIBUS™
INTERFACE
8259
INTERRUPT
CONTROLLER
;5
;;;
w =>
II:
'"
9
ID
CPU
,
-~--
32K BYTE
IK BYTE
2732A
2118·12
DRAM
EPROM
2K BYTE
2114AL-3
SRAM
8279
KYBO/DISPLAY
CONTROLLER
4-8275
CRT
.CONTROLLERS
--
LOCAL
I/O BUS
iNTERFACE
--
g
.~
9
1
DUAL·PORT
MEMORY
CONTROL
0
lOP
:IE
'"=>
w
I-
ID
~
'"....
;5",
Q
=>
.... ID
I.
PERIPHERAL CONTROLLER'
Flgure21. Remote Conflgwation with Qual-Port .RAM
3-140
AFN-02172A
AP·123
the 'dual-port RAM. In many cases, the 8086 also prepares the task programs and stores them in the dualport RAM, from which they may be downloaded to a
memory on the 8089's 110 bus. The 8089 executes the
task programs (from the dual-port RAM or from a local
memory on the 110 bus), while the 8086 simultaneously
executes other control or .application programs. The
application programs may encompass a wide variety of
operations, but they will always generate the display
'characters and store them in the dual-port RAM. The
8089 returns status to the 8086 when task program
execution has been completed.
BOOTSTRAP LOADER
OPERATING SYSTEM
FFFFF
APPLICATION PROGRAMS
2732"-2
EPROM
F8oo0
DISPLAY BUFFER
PROGRAM STORAGE
2118·12
(DOWN LINE LOADED)
}-~"
"-
DUAL·PORT
DYNAMIC RAM
Foooo
;:::~
NON·VOLATILE DATA
STORAGE
Figures 22 and 23 show the manner in which the
memories are organized. Figure 22, which shows the
memory configuration for the 8086, should be taken as
an example, since many different ,configurations are
possible, according to the user's application. Figure 23
shows the memory configuration for the 8089, given the
particular choices made for the application discussed in
this note. Of the memories shown in Figure 22, the 2141
static RAMs and the 2732A EPROMs are located on the
8086's local bus, while the 2816 EEPROM and the 2118
'dual-port RAM are interfaced to the Multibus. The 2816
is a non-volatile read/write memory equivalent in its
storage capacity to the 2716 EPROM.
2816
}
18K BYTES
}
8K BYTES
08000
~
INTERRUPT YECTOATABLE
STACK
SCRATCH PAD
2141·4
01FFF
CPU LOCAL
MEMORY
"'00
Figure 22. CPU Memory Organization
.... r---
~..,
SYSTEMS.....CE
I/O SPACE
, - - - - - - - - - , F1'FFF
2 PAGES
DISPLAY
BUFFER
OFfFF
EEPROM
2118·12
DYNAMIC RAM
32K BYTES
T
I/O PORTS
KEYBOARD
cooo
DACK
Aooo
CLKENA
sooo
CRT CONTROLLER 1
sooo
CRT CONTROLLER 2
~
_______
4000
~FUOO
CHANNEL
PROGRAM
2732A
EPROM
SCRATCH
PAD
2114AL-3
RAM
2000
07FF
0000
Figure 23. lOP Memory Organization
3-141
AFN-02172A
AP-123
8086/8089 Software Interface
Comparing Figures 22 and 23, it can be seen that the
2118 dynamic RAM appears in the memory cone
figurations for both the 8086 and the ~089. In the 8086's
system space, this memory occupies addresses FOOOO
through F7FFF, while in the 8089's system space, its
address range is F8000 through FFFFR
FFFFF
LlN~eD IDP CONTROL BLOCKS
}
FFFOO
258B~ES
FFEFF
Figure 24 shows the organization of the dual-port
RAM. The addresses given are those seen by the 8089.
The display data (for the CRT refresh function) is contained in the two largest blocks-Display Page 0 and
Display Page 1. Each page contains 15K bytes, enough
to refresh a color graphic screen containing 48 rows of
80 characters each. In typical operation, the 8086 and
the 8089 both access the same page of display data. In
special cases, such as animated displays, the 8089 performs repetitive DMA transfe(s from one of these
pages, while the 8086 is generating new display material
and storing it in th~ other page. The display page pointer
(DSPLY_PG-PTR) in the parameter block specifies
which of these pages is to be displayed at any given
time. This pointer may be changed by the 8086, or by a
command fro!ll the terminal keyboard.
}M_
SPARE
FFCOO
FFBFF
DISPLAY PAGE 1
15K BYTES
FCOOO
FBFFF
KEYBOARD BUFFER
}
2S6BYTES
}
258BYTES
}
258 BYTES
F8FOO
FBEFF
EEPROM BUFFER
FBEOO
FBDFF
The Command Buffer is a 256-byte area set aside for
transferring ASCII 'characters from the 8086 to the
8089. It is like a second keyboard, scanned by the 8089.
It takes precedence over any real keyboard activity.
The COM_8086 flag in the parameter block is used to
indicate when there are entries in the command block
area.
COMMAND BUFFER
FBDOO
FBCFF
SPARE
)
258BYTES
FBCOO
FBBFF
The EEPROM Buffer is a 256-byte area used in connection with the non-volatile EEPROM memory, an optional memory which may be located on the Multibus.
One use of such a memory would be to store ASCII
strings, which could then be recalled by the 8086 upon
recognition of special keyboard control code
sequences.
DISPLAY PAGE 0
The Keyboard Buffer is a 256-byte area which serves as
a storage area for ASCII characters entered from the
terminal keyboard. When this buffer becomes full, or
when a return is ,entered at the keyboard, an end-of-file
byte is placed after the last entered character, and the
keyboard buffer full (KBD_BUF-FULL) flag is set in
the parameter block. This prevents the 8089 from processing any more inputs from the keyboard, until the
8086 resets KBD-.BUF-FULL.
15~
BYTES
Figure 24. Organization of the Dual-Port RAM
The Linked lOP Control Blocks are those which have
been discussed above, as part of the 8089 overview. The
specific memory locations are as shown in Figure 25.
Note that there is only one parameter block, andno task
blocks present. Only one task block is used in this
application, and it is stored in the 2732A EPROMs on
the 8089's I/O bus.
The Spare blocks total lK (1024) bytes, and may be
used for any purpose, according to the user's
application.
3-142
AFN-02172A
AP-123
,In the above table, DB represents a one-byte quantity,
and DW represents a two-byte quantity.
FFFFF
SPARE
}
4BYTES
FFFFC
FFFFB
SYSTEM CONFIGURATION
POINTER
}
I BYTES
FFFF.
FFFF5
SYSTEM CONFIGURATION
BLOCK
TP_LSW and TP~SD are the two words making up
the task pointer. However, since in this application the
task program is in the 110 space, only the leastsignificant word (LSW) is fetched.
} IBms
FFFFO
FFFEF
CHANNEL CONTROL BLOCK
EEP-INH, when not equal to zero, indicates that the
EEPROM buffer is closed to keystrokes or 8086 ASCII
commands.
}.. ~.
EEP-BUF-FULL, when not equal to zero, indicates
that the EEPROM buffer is full.
FFFEO
FFFDF
PARAMETER BLOCK
EEP-RECALL, when not equal to zero, indicates that
the 8089 is recalling the contents of an EEPROM buffer
area.
224 BYTES
COL-CH-INH, when not equal to zero, inhibits the
color control keys on the keyboard.
KBD-INH, when not equal to zero, inhibits the processing of keystrokes (entered at the keyboard) by the
8089. Up to 6 keystrokes may be saved in the keyboard
controller and may be processed later.
FFFOO
Figure 25. Organization of the Linked
lOP Control Blocks Area
KBD_BUF_FULL, when not equal to zero, indicates
that a new line of keyboard data needs to be processed
by the 8086. The 8089 sets KBD_BUF-FULL equal to
-1 when the return key is pressed. The 8086 resets
KBD_BUF_FULL to zero after it has read this data.
As mentioned earlier, the structure of the parameter
block is very flexible. Only the first four bytes are fixed
(because of the 8089's requirements). These four bytes
contain the address of the task block. The remaining
space in the parameter block may be defined by the
user. The following list shows the parameter block
structure that is used in support of the channel program
contained in the 2732A EPROMs on the 8089's I/O bus.
TP_LSW
DW
TP_MSDc
DW
EEP-INH
DB
EEP_BUF_FULL
DB
EEP-RECALL
DB
COL-CH-INH
DB
KBD-INH
DB
KBD_BUF_FULL
DB
COM-8086
COLOR
ST~lL8086
BACK-COL_SW
MON-INH
DSPLYJG-PTR
SCROLL-REQ
MaN_HOM
MON-END
MON_LMARG
MON-RMARG
KBD_BUF-PTR
DB
DB
DW
DB
DB
DB
DB
DW
DW
DW
DW
DW
COM-8086, when not equal to zero, indicates that
there are ASCII commands in the command buffer
areas of dual-port RAM that need to be processed by
the 8089.
COLOR determines the foreground and background
colors to be used in connection with ASCII characters
entered at the keyboard, or senthy the 8086, via the
command buffer area. In the COLOR byte; bits BO-B2
determine the background color, w,hiie B3-B5 determine the foreground color. The following code is used:
·000
001 '
010
011
100
101
110
111
Black
,Red
Green
Yellow
Blue
Magenta
Cyan
White
STlLPTlL8086 is ,a two-byte quantity that serves as
, an offset address for the ASCII characters in the command buffer.
3-143
AFN-02172A
AP-123
BACK-COLSW determines whether the 8089 color
control keys will alter the foreground or the background portions of the COLOR byte. If BACK_COL_SW equals zero, the foreground color is
altered. If BACIC:COLSW is not equal to zero, the
background color is altered.
display. The first byte determines whether the character
is a text character or a graphic character, and specifies
the colors for foreground and background. If it is a text
character, the second byte specifies the character with
a seven-bit ASCII code, and the remaining two bytes
are not used. If it is a graphics character, the second,
third, and fourth bytes contain the color specification
. for each oCthe twenty distinct picture elements (pixels)
within the character. Use of the foreground color is
indicated by a one in the respective bit position, while a
,zero specifies use of the background color.
MON-INH, when not equal to zero, suspends DMA
transfers by the 8089 from display memory to the 8275s.
When MON-INH is cleared, DMA will resume.
DSPLYJ(LPI'R determines which of the two display
pages will be used to refresh the CRT. If DSPLY_PG_PI'R equals zero, page 0 will be displayed'! If
DSPLY-PG-PTR does not equal zero, page I will be
displayed ..
The structure oCthe display characters and the formats
of the individual bytes are shown in Figures 4 and 5.
The four 8275 CRT controllers on the 8089's 110 bus are
used to process the four bytes comprising each'character. Since the 8089 can t~ansfer two bytes at a time in
DMA mode, the four bytes are transferred in two
stages. In the first stage, the 8089 fetches the first two
bytes from the dual-port RAM, and transfe,s these two
bytes into the first pair of CRT controllers. In the
second stage, the 8089 fetches the second. two bytes
from the dual-port RAM, and transfers these two bytes
into the second pair of CRT controllers. This process is
repeated 80 times to transfer the 80 characters making
up each row in the display.
SCROLLREQ is set by the 8089 to indicate to the 8086
that the cursor is at the bottom of the page, and that key
entry/commandprocessing has been halted, pending a
display memory scroll operation. When the 8086 has
performed this operation, it clears SCROLLREQ.
MON_HOM, MON_END, MON_LMARG, and
MON-RMARG specify, respectively, the upper, lower,
left, and right boundaries of the region on the screen in
which keyboard entries will be displayed.
KBD_BUF-PTR is a two-byte quantity that serves as
an address for the ASCII characters in the keyboard
buffer.
The distinction between text and graphic characters is
entirely transparent to the 8089. Four bytes are transferred in every case, even though the text information
onJy requires two bytes per character.
Note that a number of these parameters' support op- '
tions (e.g., EEPROM buffer) and are not critical to the
graphic operation described in this application note.
8089 Display Hardware Interface
This section describes the hardware of the peripheral
processing module (PPM), which includes everything
between the system bus and the CRT displll-y/keyboard
unit. The overall organization of the PPM is as shown in
Figure 21. The dual-port RAM can be accessed from
either the system bus or the 8089's local bus; The 8089 is
said to be opera~ing in the system space when it is
accessing the dual-port RAM, and'in the 110 space
when it is accessing devices on the 110 bus. Included on
the 110 bus are four 8275 CRT 'controllers, an 8279-5
keyboard controller, two 2732A EPROMs, which are
used to hold channel programs, and four 2114 static
RAMs, which are used as scratch-pad RAM for the
8089.
As explained above (under OVERVIEW OF CRT
'GRAPHIC SYSTEMS;·Performance Requirements),
four bytes' are used to specify each character in the
We shall now examine the hardware schematics in
detail, to see how the various functions of the PPM are
implemented. Figure 26 shows the 8089IOP and its
associated bus controller. At the top left are the inputs
through which the 8089 is controlled. The DRQF signal
(detailed later) is the DMA request that initiates the
transfer of two bytes from the lOP to two of the four
CRT controllers. DRQF comes from the 8275s via a
one-shot, and is connected to the DRQ I input of the
8089.
IRQ is an interrupt request that comes from the 8275s.
It is activated after an entire screen's video information
has been transferred from the. dual-port RAM to the
8275s. IRQ is connected to the EXT I input of the 8089.
It is necessary to program the 8089 to terminate the
DMA transfer on an external event, iIi order for this
signal to be effective.
CA is the channel attention signal. Upon receipt of CA,
the 8089 reads the channel control word (CCW) from
the dual-port RAM. From the CCW, the 8089 determines the nature of the operation assigned to it by the
.3-144
AFN-02172A
AP-123
ORQF
IRQ
CA
lIIIR'
ROY
RST
.
AOIDO 1.
31 ORQl
33
EXTl
...... •
20
21
AOiDO-A151015
Al8/S3-All188,A
Al/0l
A21D2
A3ID3
A4ID4
15
l'
13
12
A5/DS 11
_10
CA
SEl
::~
iii
11
12
lIO
A7/07 1
lI!
--1!
....
:
2
vcc~
15
~
DIW(!
11
1
7
13
14
·At/OSI
AI/OI 7
A101010 8
5
1\11/011
4
Al2/012
3
Al31013
2
Al41014
A151D15 31
[38
All/83
37
A17/84
38
All/85
3S
Al1/S8
IIRI' 34
28
so 27
lRIR
I
3S;
11
ClK
lOB
CEN
m
RIWf
an
ilIii5C!
JlR
INTA(R EAOWOI
DTiK
ALE
DEN
4
A48
18
17
JI15!A
8288
Pl
~
28
0--
A3
SINTA.1 17
SINTR-2 18
41
42
8081
....r
ClK
Figure 26. 8089 1/0 Processor and 8288 Bus Controller
8086. CA is derived by hardware decoding of an 110
write command made by the 8086 to address OOH or
address 01H on the Multibus. The lowest-order bit of
this address is used to specify whether channel 1 or
channel 2 of the lOP is to be selected, and is connected
to the 8089's SEL input. In this application, the DMA
transfers are always performed by channell.
RDY is the ready signal that comes from the 8202
dynamic RAM controller, and is synchronized by the
8284A clock generator. RDY is low whenever the 8086
is accessing the dual-port RAM. The RDY signal is used
to establish a master/slave relationship between thl(
8086 and the 8089, with the 8086 as the master. As
mentioned earlier, the 8089 accesses the dual-port
RAM about 50% of the time during DMA transfers. It.
can be seen, referring to Figure 20, that if no idle clocks
occur, the lOP will access the dual-port RAM during
the four clock times of the DMA-fetch bus cycle, and
will access the 110 bus during the four clock times of the
DMA-store bus cycle. While the 8089 is doing the store
operation, the 8086 can access the dual-port RAM.
Once the 8086 has gained this access, the RDY signal
will remain low until the 8086 is finished. The 8089 waits
for RDY to go high before making a subsequent fetch ..
At 5 MHz, the 8089 requires 3.2 microseconds (16 clock
cycles) to transfer the four bytes representing a graphic
character from the display memory to the four 8275s,
assuming that no wait states have been inserted because of the 8086's access to the dual-port RAM, or
because of dynamic RAM refresh functions. A complete row, consisting of 80 characters, requires 80 x 3.2
= 256 microseconds. The time allowed to complete the
transfer of one row must be less than the time it takes to
display that row on the screen. This latter time is equal
to 1/50 of the total screen update time, or 1/3000 of a
second (333 microseconds). Comparing the two figures
(256 vs 333), it can be seen that there are 77 microsec, onds available for such wait states. It is the responsibility of the software designer to control the 8086's access
to dual-port 'RAM in such a mannner that the added
wait states do.not total more than 77 microseconds in
any span of 333 microseconds. Otherwise, underruns
may occur and the CRT screen will be blanked. See
System Performance (below) for further discussion on
this effect.
3-145
RST is the lOP reset signal, which comes from the
8284A clock generator. The first CA after RST causes
the lOP to access address FFFF6 in the dual-port
RAM, in order to read the system configuration pointer.
AFN-02172A
AP-123
Outputs from the lOP are the time-multiplexed address
and data lines, BHEI (bus high enable), status lines SO,
SI, and S2, and the system interrupt request lines,
SINTR-I and SINTR-2. The interrupt lines go directly
to the Multibus, and from there they become inputs to
the 8086's 8259A interrupt controller.
The DACKI signals are generated in the following
manner:
I. Both 8275 pairs are accessed by the 8089 (DMA
mode) Viii port AOOOH.
2. Hardware is used to select one pair of CRT controllers (byte~ 0 and I or bytes 2 and 3).
3. As th68089 reads (DMA) the word from the dualport memory, address bit I (SAl) is latched with
the memory read command (MRDCI).
Figure 27 shows the I/O address latches and decoder,
and the circuitry used to generate the DACKI signals
for the CRT controllers. The lOP status bit S2 indicates
whether the lOP is accessing the 1/0 sp~ce or the system space. Latched by ALE (address latch enable), S2/
generates 10 and 10/. 10 and 10/ are used to indicate
that the 8089 is not accessing dual-port RAM. 10/ goes
to the dual-port RAM controller.
4~ When SAl = 0, DACK 11 is activated.
5. When SAl = I, DACK 2/ is activated.
6. In this manner the 8089 performs alternating
writes (DMA) to the 8275 pairs.
A49
STB
010
011
01'
013
01.
DIS
016
017
11
ALE
AOiDo-AI51DI5
A1/D1
A2ID.
A3ID3
A4I04
A5ID5
A5ID8
•
3
•
5
•
7
A7/07 8
DOO
DOl
DO.
003
DO.
DOS
D06
007
0-
~
19
18
17
16
15
14
13
IClAo-IOA15
.os
"
ICA13
IOA1'
10A1S
8.82
• .,_ l~ ::
1
AO
3
A.
13
0,
~
11
10
~ 9
0. 7
6
r~
E1
4
A66
'11
1
A81D8
A91D9
A101Dl0 3
A11JDl1 4
. Al21Dl' 5
A131D13 6
,.
A14 D14 7
A15/D15 8
13
12
19
18
17
16
15
•
820S
Vee
SA1~
4
10
9
12 0 A.O Q
F
IDA
IDE
AT
AT
ClK
CAT
KEY
,.
MiiiiCp
9
74lS74
8282
A21
~DA
5---..-
ii
...... 'i3
•
10
A21
•
DA
Vee'"
•
2
~
1
,
RST
3
A19
2
A.O
0
Q "
T4lS7'!,. 6
iO
Q
10
A19
•
"T
Figure 27. Address
Latch~s,
Decoders, and DACK Generator
3-146
AFN-02172A
AP-123
Figure 28 shows the bus transceivers used between the
8089 and the I/O bus, and also shows the 2732
EPROMs.
Figure 29 shows the 2K bytes of 2114 static RAM on
the I/O bus, which are used as scratch-pad RAM for
the 8089.
Figure 30 shows the 8279-5 keyboard controller, and
also shows the 8284A clock generator that produces the
CLK, RDY, and RST signals for the 8089. For more
information on interfacing the 8279-5 to the keyboard
(Cherry Electrical Products B70-05AB), refer to the
8279/8279-5 data sheet and application noteAP-32, CRT
Terminal Design Using the Intel 8275 and 8279.
Figure 31 shows the clock generator for the character
timing and dot timing. The character clock frequency (C
CLK) is 1/8 of the dot clock frequency (D CLK), 10.8
MHz. Also shown in Figure 31 is a 9602 one-shot used
to generate the video sync pulses.
Figure 32 shows th~ CRT Controllers #0 and #1. Bit 6
of Byte 0 determines whether the display character is
text or graphic. If Bit 6 is low, the character is a text
character, and Byte 1 is used to address the 2732A
character generator ROM. Bytes 2 and 3 are ignored.
The line count outputs LCO-LC3 of an 8275 (any 8275
can be used, since they are all synchronized) are also
applied to the cliaracter generator to perform the line
select function.
10A0-10A15
A30
DTiii
11
AOiOO-AI51DI5
•
3
1
4
5
6
7
9
9
PiiEN
T
AO
19
81 18
17
82
18
83
15
1000-10015
BO
Al
A2
A3
A4
A47
B4
118
14
13
B6
12
85
AS
A6
A7
CE
8~
De
6266
8
7
6
5
4
3
2
1
IOA3
10A4
ICAS
IOAI
IOA7
10Al
10A9 '3
IOA10
10Al1 ' 19
10A12 21
..
A31
11
1
19
3
16
17
•
10Al
lOA'
I
6
7
----.L
Do
A2
A3
Oz
D:!
A4
0,
A5
A6
A7
0,
0,
Os
0.,
9
10
11
1000
13
14
15
16
1003
1006
17
1007
1001
1002
1004
1005
AI
A9
AI.
Al1
2732A
DE
120
16
15
14
I.
12
4
5
AO
AI
iOFiiAD
,'8
9
10Al
10A2
8.96
IOA3
IOA4
10A5
CE
I.
5
4
3
2
1
IOA9
23
9
10
11
7
6
10A7
10A8
IOAe
iOEPiiOi.i
8
A65
14
15
16
17
1008
1009
10010
10011
10012
10013
10014
10015
IOA10 22
10A11 19
IOA12 21
2732A
DE
A18
INTA
iORc
~3
'20
---'
2
Figure 28. Bus Transceivers and EPfJOMs on 1/0 Bus
3-147
I\FN-02172A
AP-123
10A1-10A10
1U8
5
8
7
4
3
r----;
~
~
18
~
14
VOl
13
UCla
V03 12
11
AO
Al
A2
1/04
~
M
AS
A8
A7
AI
A9
~~
lOA~
iOiiAii - '
14
13
12
11
5
8
7
4
1004
IOD8
IOD8
1007
3
2
1
17
1
AlB
18
15
214AL·3
We
10
10DO
1001
1002
1003
2114AL-3
r
WE
CS
8
10
Cs
8
11
13...........
A2
14
13
12
11
~
~
~
'----t
1001
1001
IOD10
IOD11
'----+
~
'-----+~
14
IOD12
13
12
11
10013
10014
10015
----+
~
~
r---;-
'--+
.s.
'"--F
'----'-
'-*"
~
A7.
~
~
~
2144AL·3
2144AL~3
10
I
8
10
I
8
~11
13
A21
IODO-IOD15
Figure 29. Static RAMs on 1/9 Bus
3-148
AFN-02172A
AP-123
1-
ODlI
~
1000
1001'
IOD2
1003
1004
IODS
1001
1007
,,-iOiiC
lowe
12
13
14
15
1.
17
1.
1.
10
11
22
21
~
RD
10A1
----4
......!.
"17
D80
RLO
RL1
DB1
RU
D82
ALI
D82
RU
RLS
DBI
RL8
D.
31
31
1
....
RU
DII7
RD
WR
ST"
cs
RUI
RL1
2
5
RL2
RLS
RL4
RLI
7
RL5
e
RL7
•
~
37
43
44
41
41
47
41
41
50
STRS
51
~
~
~
AD
RESET
eLK
827M
,.--.
51
~ 52
~ 61
~ 10
...
Vee
15MHI
~
P1
~
M IN914
"il>
14~
5
6 11011
",..
SACK
10
MSAW
~5IOK
>
11
~DI
f17
,
.-
iiiT
RST
eLK
103
:
110
1037
t11'F
~4
510
RDn
RDY
10
RST
8
CLK
5
RDy
7 RDY2
AlN2
r;; Wii
~
FIe
~ CSYNC
,
5214"
Figure 30. Keyboard ControUer and Clock Generator
, 3-149
AFN-02172A
AP·123
110
CCLI(
21.1 MHz 510
r----------t--~----------_4---------- UDoiIAR
A7
A27
osc
715713
12
;. 10
Ci:R
1
' -_____--<...._ _ Vcc'
A75
13 F/f
DCLK
CIYNC
P2
8284A
Vcc*
Vee*
r-------L-~>---~~ ~----~57
INTYTRC
A2
Vcc*1
HRTC
-------------------------------~
Figure 31. Character Clock Generator and Video Sync Pulse
3-150
AFN-02172A
PI
CcLK
1000
1001
1002
1003
1004
1005
100&
1007
1O[)o"'IOD15
18
,.
22
6
f
2
DCLK
ceo
eel
CC2
CC3
CC.
ee
5
CC6
OBO
OBI
OB2
0B3
OB4
OBS
Oa&
~ ClK
~
10
10
~20
~ 3D
2Q
3Q
AI1
127 11 .0
128 13 50
14 D
~
4Q
sa
2
5
7
10
12
15
8Q
cs
"
lPEN
•
BGG
6
10
1"
15
Vee·
AO
3
,.
elK
Wii
11
BGR
2
5
~
6 74LS174
AD
FOR
FGG
FOB
BGB
OB7
"_ _
OACK ORO"
.. CClK
-
GCClK
~
15
16
17
10
21
CRTi
DACi<1
VSP 1
"
•
iORC
AiOWC
IoAi
~
12
13
L
lA
IV
lB
2A
2V
2B
3A
3B
4A
3Y.
4B
s
G
"Y-
4
lIED
7
GREEN
54
II
•
BWE
51
..!!..-
A3'
k
74157
'RQl
BO-Ca&
31
A13 1RQ
8275
AS
11
CRT CONTRdiLLER #0
•
.PHMOOE
I
DCLK
118
10DB
12
1009
10010
,.
13
10012
1.
I.
10013,
17
10014
18
19
10011
IO[l15
CCO
eCl
CC2
CC3
CCO
CCS
CC.
LCO
LCI
9
10
21
lC2
LC3
22
4
2'
2.
25
26
27
28
29
•
LC1
"
"13
Fa3
FB4
11
10
9
FBS
FB.
FB7
A9
0,
0"
0,
Do
FB2
A3
AO
V
G\i
12 H
G
11 F
': E
0
:
f
2
13
1
A6
RU;-
A.O
C
B
A
VCC·~ CLR
6 A2
r
CRT
D.
AS
~
CONTROLLER
FBD
FBI
22
~
f-2.
I.
23
~Al
2
17
Os
0,
D.
4
•
AI.
8275
FE
19 A10
3D
f
A4
• A'
2 A6
1 A7
Co)
7
,.
2732A
A28
ClKINH
SRIN
7.LSI66
to
AI1_
DE
15
~20
#1
LC2
LQCHAR
~
z
FB7
RVV
-
-
§
,.
;;:j
.
~
"CI
....
N
Figure 32. CRT Controllers, Color MuHlplexer, and Character Generator
"
•
AP·123
For each character, the foreground and background
color bits are output from Byte 0 and latched into the
74LS 174, from which they are applied to the input of the
74LS157 mUltiplexer. Selection between foreground
and background is done by the output of the 74LSI66
parallel-to-serial converter, which operates from either
the text or graphic character generator, as appropriate.
The roles of foreground and background color may be
reversed by the RVV (reverse video) signal from the
8275, which is exclusive-ORed with this color select
output.
shades of color. The D eLK signal is ORed with the VSP
(video suppress) signal from the 8275, to produce complete video blanking when desired.
Figure 33 shows the CRT Controllers #2 and #3, the
decoder for the line select function, and latches for the
video control sigrials. CRT controllers #2 and #3 are
operational in graphics mode only. Synchronization of
the two pairs of CRT controllers is discussed in the 8089
Display Functions Software section.
Figure 34 shows the tri-state buffers used to handle the
color information within a graphic character. The
decoded line count outputs (ROW Of-ROW 4/) are used
to select which buffer is enabled onto the bus. The
buffer A36, enabled by the GRAPH MODE signal, is
used to "double up" the four graphic cells to produce
eight (horizontal) dot inputs to the shift register (Figure
32).
Since the RBG (red-blue-green) inputs of the color
monitor (Aydin Controls 8039D) are AC coupled,
return-to-zero type outputs are needed to pass these
signals through the input stages. This is provided by
strobing the gate input ofthe 74LSl57 multiplexer with
the D CLK (dot clock) signal. By varying the duty cycle
of the D CLK, the user can produce many different
IOOO-IOD15
IDOG
1001
1002
1003
1004
1005
1000
1007
,ORe
AiO'WC
iOif
CiiTf
12
I.
,.
,.
11
17
DB.
D88
10
21
DB7
RD
WR
AO
CS
,.
•
6ACK2
f
ceo
CCI
cca
cca
CC4
OM
18
22
6
30
GCCLK
DBO
oBI
DB2
Da.
ceo
CCI
.
2a
H
28
27
21
28
•
CB7
C87-C_
C8I
ca.
C81D
C81t
C81.
IIIIQl
ca1'
•
~
iiiiii
....
I--
DACK
CCLl<
lPeN
A'.
1275
CRT
CONTROLLER
#2
A.7
ORO'
Leo
LCO-Le3
Le1
lC2
GRAPH MODE
lOOt
1001
,.
JOD10
10011
14
15
16
IOD12
10013
10014
10015
..
12
23
25
28
27
H
29
11
18
,.
•
• ...
f!!
•
~
iii
~
CS17
1.
1.
1.
12
11
~
iiiiWo
iiiiWi'
!!!!!.!
ROW.
&4
r+~.
nEO
t205
ca,1
CS1.
CB20
35
7
8
'0
~
AO
A,
•
ca15
CB16
.
22
6
f
ca14
l
1
74175
•
•
10
21
CCiJ(
•
~
r+-
IG
~
r-
8275
A18
I
CRT CONTROLLER #3
•
A41
1Q
10
2Q
50
3D
.0
4Q
CD
2
~
7
~
~
15
RVY
1IIIP
HTRC
INTYTRC
r!L
ClK
CLR
,T'
Vee"
Figure 33., CRT Controllers, Line Decoder, and Video Control Signal. Latch
3-152
AFN-02172A
AP·123
C80-C820
ceo
CI1
C. .
ca.
C..
cao.
CBS
CB7
A73
2
•
••
11
13
I,
17
iiOii'o
,.
lYl II
lAl
lA>
'YO
w.
lA'
W. 12
lA.
2A'
2Y'
7
oAo
2YO
2A'
2Y.
2A.
2YO
nL8244
10 2G
•
,
•
T'
iiiiWT
SBO
SBO
8Bl
8.0
'83
8eo
8Bl
882
sa.
582
I-f.
C810
C811
l"
..
2
0
•
•
•
13
C815
17
15
18
SBO
10
SB'
SBO
SB.
1
A54
A7
,,.
•
••
11
CB.o
C.,'
C.,.
C81&
ca17
C818
C818:
18
••
,.
.2
11
15
-----!!.
,.••
•
,
-+•
AS.
74LS244
S
FB.
Fa7
3
'r
~82
S8.
..
r'.
a
F"
FB•
F.,
FBO-F.1
sal
SBo
74LS244
Y·
•
7
AH
Feo
FBI
F.o
74LS244
•
cB9
CBI
12
LT.-
L!!.
GRAPH MODE
10
r-.;
5.3
.,.,.
2
8.,
SB.
SBI
SU
5..
T'r
Figure 34. Tri-State Buffers for Graphic Color Information
3-153
AFN-02'72A
AP-123
The block diagram in Figure 35 shows how the text
characters are processed. The following statements apply to Figure 35:
4. The eight output signals from the text character
generator are transmitted to the para1lel-to-serial
converter.
5. The serial, horizontal dot data is transmitted to
the multiplexer and selects foreground (dot data
bit = 0) or background (dot data bit = 1) color
signals.
1. Byte 0, Bit 6 = 0 indicates text mode.
2. The six color signals from CRT Controller' #0
(three foreground and three background) are
latched and transmitted to the multiplexer.
6. The red, blue, and green color signals are trans- ,
mitted to the color monitor.
'
3. The seven character output signals and the three
line count signals from CRT Controller # 1 are
transmitted to the text character generator.
CRT
CONTROLLER
#0
7. CRT Controllers #2 and #3 are not operational in
text mode.
MULTIPLEXER
LATCH
FOREGROUND & BACKGROUND
6
CCo-CC5
6
COLOR SELECT
8275
74L5157
75L5174
--
f----.
RED
BLUE
GREEN
SERIAL HORIZONTAL
DOT DATA
CRT
CONTROLLER
CCO-CC6
#1
,
7
TEXT
CHARACTER
GENERATOR
8
PARALLEL TO
SERIAL
CONVERTER
3
LCo-LC2
L
8275
74LS166
2732A
Figure 35. Processing of Text Characters
3-154
AFN-02172A
AP-123
The block diagram in' Figure 36 shows. how graphic
characters are processed. The following statements apply to Figure 36:
1. Byte 0, Bit 6 = 1 indicates graphic mode.
2. The six color signals from CRT Controller #0
(three foreground and three background) are
latched and transmitted to the mUltiplexer.
3. The three line count signals from CRT Controller
#1 are transmitted to a one-of-eight decoder
which generates five row select signals (ROW 0ROW 4).
5. The four pixel signals of the selected row (based
on the row select signals) are transmitted to another octal buffer.
6. The octal buffer converts these four bits to eight
bits by duplicating each signal. Thus, output bits 0
and 1 are equal, 2 and 3 are equal, etc.
7. The eight output signals of the octal buffer are
transmitted to the parallel-to-serial converter.
S. The serial, horizontal dot data is transmitted to
the multiplexer and selects foreground (dot data
bit = 0) or background (dot data bit = 1) color
signals.
9. The red, blue, and green color signals are transIJ).itted to the color monitor.
4. The twenty pixel signals from CRT Controllers
#1, #2, and #3 are transmitted to three octal
buffers.
•
CRT
CONTROLLER
#.
LATCH
•
CCo-CC5
•
FOREGROUND & BACKGROUND
MULTIPLEXER
COLOR SELECT
827.
.
CRT
74LS174
LCD-LC2
,
CONTROLLER
827S
ROW.
DECODER
RED
r-
BLUE
f--
GREEN
SERIALHO RIZONTAL
DOT DATA
(1 OF 8)
ROW'
....
r-
74LS157
r-
I--
•
CRT
CONTROLLER
#2
BUFFER
i-/.-
•
•
8275
~
~
74LS244
BUFFER
•
~
74LS244
PARALLELTO
SERIAL
CONVERTER
74LS166
ROW.
ROW'
CRT
CONTROLLER
.3
+-
•
BUFFER
•
•
r-+-'
74LS244
8275
ROW'
+
,
BUFFER
+
74LS244
Figure 36. Processing of Graphic Characters
AFN-Q2172A
AP-123
cient. To-preclude this, the circuit shown in Figure '37
generates a surrogate (early) DRQ signal, DRQF, using
a one-shot triggered by the trailing edge ofDRQ (DRQ 1
ANDDRQ 2). The one-shot times out prior to the rising
edge of eLK in T4 of the DMA's store bus cycle.
Figure 37 shows the circuit used to synchronize the
8275s, and also the circuit used to generate the DRQF
signal. As mentioned earlier (see Figure 20), ifthe 8089
were to wait for a subsequent DRQ signal from the
8275s, some clock cycles_ would be allocated to idle
clocks, and the DMA transfer would become less effi-
1IlIT" _ _ _ _ _ _
~-...,
GCCLK
Vee·
Vee·
Vee·
, A7
CCLK
8.2K
Vee
DiiQ
12
11
DROF
Vee·
-
10
AI
DRQ1
10
SCaT".
ALi
Figure 37. Circuits to Synchronize CRT Controller. and Generate DRQF
3-156
AP-123
Figure 38 shows the relationship between the individual
DRQ signals from the 8275s and the DRQF signal that is
sent to the 8089. DRQ 1 is the data request representing
the 8275s #0 and #1, while DRQ 2 similarly represents
the 8275s #2 and #3. The DACK 11 and DACK 2/
signals (along with AIOWC/) are used to deactivate
DRQ 1 and DRQ 2, respectively.
Figure 39 shows the multiplexer used to control writing
of data to the dual-port RAM. When 10 and SWTCI are
both low, the 8089 data is gated to the dual-port RAM.
When BDSEll and SWTCI are both low, the 8086 data
is gated to the dual-port RAM. BDSEll may be active
only when the 8089 is in the 110 space. Note that the
address range for the dual-port RAM is F8000-FFFFF
as seen by the 8089, and FOOOO-F7FFF as seen by the
8086.
'
BYTQ 0 AND 1
FlITCH
I
12
I 12 I T4
I
BYTE82 AND 3
SfORI
T1
I
12
I 13 I T41
T1
T.a I
I 12
T41
T1
I 1 2 j : I T4/
'-----11' - - - - - - - - - - -
- - - --
DIICII
(FROM un #2 AND #3)
Ii
(FROII~
(TO _
ORQF
DRQ1INPUT)
iiACii
(TO 8Z75 #0 AND #1)
DiCKi
(TO
un #2 AND #3)
- - - - - - = LAST TRANSFER
Figure 38. Derivation of DRQF Signal
,
3-157
:'
AF'H12172A
A3
ADiii'5
.
ADIDO-Al51D15
'a--"\3
10
SWfC
IoWC
MiDC
iWTC
TciiiC
./
-.-./
.,
~U
22
11
SCSTAB_
A22
tOlD
2 011
3
01'
"20
21
ll:i
~-
A70
STB
XACK
DOG
DOl
DO'
DI.
DIS
DO'
DOS
~ iii6C
~SWTC
~ SiOii
"
,.,.
L
Io..!. 0.
~*-CA
S
SV
10
--
1_ 8
A18
10
SV
"
8282
11
A ••
00-D1i
I
13
A18
,.
MBAW
WSDO-WSD15
73
7'
71
72
c.>
:!.
8l
88
70
..
87
'-41
VCC
-
iii
iii
2
3
D2
•
1!3
IR
S
as
6
DI
7
67
_8
r--L
T
A72
AD
iii
A1
iii
A2
i2
A3
A4
B3
i4
AS
A6
-Ii
A7
87
OE
85
18
WSDO
18
WSDI
11
WSD.
18
IS
WSD3
WS04
WSDS
WSDI
WSD7
,."
13
Vee·
AOIDO
Al/D1
A2ID2
A31D3
A41D4
A5i05
A8iD8
A7ID7
8217
11
1
2
3
•
•
5
~
•
T
AO
Al
A35
BO
Bl
B2
A2
A3
B"
A.
A6
B4
BS
AI
A7
B7
B8
19 WSCO
,. WSDl
17 WS02
,. WSD3
15 WSD4
14 wSD5
13 WSD8
12 WSD7
0E8218
.
..
..
IS
.,
~
51
eo
~~
SWiC
11
""1
A71
•
DI
3
010
11'11
•
5
Dl •
013
8
'DR
1m
7
8
~
~
iDiEL
Vee·
iii"
..87
18
,.
WSDe
WS09
17
WSD10
18
WS011
,.
15
WS012
waD13
"'31013 8
14 WSD13
13
WSD14
13 WSD14
12
WSDI.
A141014
Al1/015
Vee·
Al/DI
AtID8
A101010
A11Lq11
11
1
A63
•
,. WSD8
-"'21012 5
15 WSD12
7
8
I
10 WSD8
17 WSDl0
,. WlD11
3
4
12 WSD15
8218
A22
~
10
_ _Figure 39. Multiplexer for_ Writing to DUIJI-Po_rt R~M
»-
'P
.N
-c..1
J
'
Figure 40 shows the deIItultiplexer used to control reading of data from the dual-port RAM. The internal transfer acknowledge (SACK!) signal from the dynamic
RAM controller latches this data. If MRDC/ is active,
the data is then gated to the 8089. IfBD ENAI is active,
the data is gated to the Multibus for: transmission to the
Figure 41 shows the multiplexer for the address inputs
to the dual-port RAM. If the 10 signal is high, the
address on the Multibus is gated into the dual-port
RAM. If 10 is low, the address from the 8089 is gated
into the dual-port RAM.
8086.
1Ni'iiCi(
RlDa-R&D,.
-
11
1
RIDO
I
3
AID2
AlD3
0
I
AlDO
AlDI
AIDI
AlD7
•
7
8
•
MADC
-
AM
STa
010
011
Oil
DI3
010
Dli
011
Dl7
ill
DOG
D01
DOl
D03
DOO
DOS
DOl
D07
11
AD/DO
A,1/D1
17
A21DI
11
11
MlDO
11
..
13
11
A21D2
oU/DI
AlD1
A_
1
I
3
AlDI
ABDO_
0
5
, AlDi
AlDI
AlD7
MIDI
A7/D7
....
11
•
••
7
All
STa
DlO
DI1
DlI
Oil
DIO
DII
011
DI7
OE
DOii
ii01
6iI2
Diii
DOO
i50i
IiOi
607
iii
50-61i
11
D1
MULnaul
17
D2
11
11
iii
11
04_
iii
,.
01
..
13
D7
'.83
,
11
d!I!!!L
ASDI
1
AI010
ASD1'
A801.
AlD13
I
• ABD10
A8015
AS.
•
11
11 ABlDI
11 A9IDt
ASDI
ASDI
17 .,01010
•
,. A11/011
A8010
I
I
15 A,121012
14 A,131013
1ISD1'
7
13 A14/D14
,. A'IID11
••
....
AlD1.
A8013
A8010
A801I
All
1
2
11
3
0
5
I
iii
iii
17
~
11
11
iffi'
1m'
,.
!iii
1m
10
13
7
••
11
011
1283
Figure 40. Demultiplexer for Reading from Dual-Port RAM
3-159
AFN-D2172A
AP·123
I" iiiii
ALE
-.PI
::
,=
I:in
II
/
_I
Ycc·~ IT
.!.
5
I
7
•
I
Z8
::
:
,
I
./'
I'"
0\4
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::
AI
AI
~
~
-
I
I::
~
2
3 I..
vcc·+
I:141
I.
II
: . .17
= II
IS
14
I'"
I
I:;
ASI
13
12
1117
-"
-,
SAO.
AI
AI
~
IIAI
'"0\4
IIA4
AI
AI
A7
IIAI
~
110\7
.
A50
2
3
I.
I II
11
-".
1JI
5
I
SAl.
_1IMt
SA12.
i 14
SAla.
SAl.
,SA15
12
8
SAIl
;15
.L
AI
AI
Al0
U8
A"
AU
A13
AI'
A15
.1.
2
3
4
5
•
••
7
II
1
2
3
4
5
I
8
I
8217
·+
Vcc
AI7
11
II
17
2
3
4
5
SAIl
U17
SAIl
All
~17
All
AI.
..!!. .1IMl.
~I
_B.H~
II
I
DOa
DI4
D04
Dl5
001
DIS
DI7
ill
DOG
DOl
D02
-
DOe
D07
•
ro 10
UO.
Ul.
,.
IIAI
II
14
13
12
~
IIA4
lAS
11M.
U7
13
A7
l'
l'
17
II
15
14
.13
I.
SAIl
I'
II
SAIl
110\17
SAl.
JI
15
IlAJl.
""
\10
1A...11
~
1,\13
SA.1!.
SA15
II.,.
Al0
BHi~
1187
I.
II
0\33
.2.
a
4
A7-
•
'"
1JrBDIG
OIl
Dl2
DI2
BHEN..
-
I
Figure 41. Multiplexer for Address Inputs to Dual-Port RAM
3-160
AFN-0217ZA
AP·123
8089 Display Functions Software
Figure 42 shows the 8202 dynamic RAM controller. The
inputs SAO-SA19 come from the multiplexer shown in
Figure 41. The dynamic RAM controller generates the
control signals (shown at the right of the page) for
operating the dynamic RAM.
The 8089 display functions software consists of a single
program which is executed by the 8089 on a continuous
basis. This program performs the following functions:
Initialization for the 8089 itself and for the CRT controllers and the keyboard controller.
Figures 43 and 44 show the dynamic RAM itself.
lK
~t
••
SAl
SA2
SA3
10
.11M
SAl
12
1.
l'
1.
I
4
3
2
1
~
SA7
SAl
SAl
"SAID
SAIl
SA12
SA13
SA14
SAl'
m
12...!!..
13
31
31
32
Oiffii
ALO
ALI
AL2
ALI
Oiffi
iiiRi
iiiffi
0iRi
A~
7
•
11
1.
11
17
II
ALI
ALI
AIIO
AHI
AH2
0iiTi
Oii'fi
AH3
AH.
AHS
AHI
iiAiO
Wi
2'
iIij
iiiCK
21
31
Wli
33
PCii
All
CAs
iiiiTi
ou
CIII
/iii
OU'
OU4
iiiffi
mm
27
21
WE
INT
A12
11
I
~
137
31
8AO-SA11
110
•
24
"'H' 10
81
"ii~ REFRQJSM;K
............
7
30
--
13
12 .
I
'
0\22
A4
11
1
,
2
o.e.
na
rk
8D
SAl.
SA1i
4
•
1
Ai
1
3
J
BD
f
2"-
FIgure 42. DynamIc RAM Control/er
3-161
AFN-02172A
WSDo:WSD7
RSDO-RSD7
S
OUTG-O'
AO AU
~
Al
~
A3
~
~
~
~
15
3
~
l---
A2
A4
AS
AS
AU
,.-DtN
l10uT
r2r!!-
RAS
CAS
WSDO
RSDO
i--i--i---
---'
l--l---
-
r--
WE
2118-12
A44
,.--
~
WSDI
~
.--.--.---
r---
W8D2
~
l---
r---
WSD3
I--
RSD3
r--
~
RSDI
0\41
i--i---
-
I--
RSD2
l---
i---
.
2118-12
2118-12
2118-12
.
~
:a-
!
R3
tJ
I'--:I'--
A48
l---
..--
AIO
i---
'---
wso..
'-'---.
'--
l--l---
~
i---
~
RSo.
2118-12
~
""iiSD5'
2118-12
AS2
,.-f---'
~
WSDI
..-.---
I--"
~
WSD7
,.--
iiSii6""'
2118-12
AS
WE
SAO
'~
;
~
,.-,.--
ASI
~
~,
'---
..-..--
Figure 43. Dynamic RAM (Low Data Byte)
r----RSD7
,.--
2118-12
_WSD15
IISDI-RSD15
OUTo-OUTI
~
r--r--~
r---
~
-
'---
iiAi
,.---
A63
>--l--->-->-->---
,---
A64
-f-"
Ir--
,--,---
,.--V--
An
,---
r--'
,--,---
-
r-
A78
r-r-V-r--
.~
-I-
V--
CA'"
2118-12
2118-12
2118-12
2118·12
:.
!
!
~
~
w
r--r--r--r---
r-
r--2118·12.
AS
Ir--
t------
l---V--
I'--I'---
9
r--
A60
l----
r----
We
Ir--
A79
L--
I---
V--
2118·12
v--v--v--v--v--v---
r-t------
r--2118·12
•
iHeii
10
!~
V--
A61
Figure 44. Dynamic RAM (High Data Byte)
A82
V-V-V-V-V--
~
I--2118-12
AP-123
The transfer instruction "'which causes the DMA
transfer of the CRT refresh data to begin.
Polling routines for the keyboard and the command
buffer.
Figure 45 is a simplified flowchart showing the relationships among these three main functions. The program
begins upon receipt of the second CA (channel attention) following an lOP reset. After the initialization
processes have been "completed, the program loops
continuously, alternating between DMA transfer and '
polling processes. There are 48 rows of characters on
the screen. The polling processes are carried out during
the vertical retrace time, which is the equivalent of 2
rows. Thus, it is easy to see that the DMA process uses
up 96% of the 8089's time, leaving 4% for the polling
processes.
CA
~
addresses 0000-07FF). The CRT controllers are accessed by using addresses 4000 and 6000 on the I/O
bus. Address 6000 is "CRT Controller 1" and actually
refers to the first pair of 8275s. Address 4000 is "CRT
Controller 2," the second pair of8275s.Address 8000 is
a clock enable address. Write commanc\s to this address
enable or disable the GC c1ock,which is the character
clock for the 8275s. Address AOOO is decoded to produce the DACK signal fgr the 8275s. Address COOO is
the address of the keyboard controller.
The exact manner in which the channel program executes depends" on the flag settings and parameter
values in the parameter block.
Appendix A is a flowchart for the complete channel
program·. Appendix B is the corresponding ASM-89
assembly language listing. In the paragraphs to follow, a
general overview of the channel program is given. The
reader may refer to the flowchart and listing if a more
detailed description is desired.
The first CA after lOP reset causes the 8089 to fetch the
system configuration pointer (SCP) and system configuration block (SCB) from dual-port memory. These
blocks contain certain very basic system-level information for the 8089, as explained above under Overview of
the 8089.
INITIALlZI'TION
The next CA causes the channel program to begin execution (at the point marked START on the flowchart).
The initialization portion of the channel program consists of the following operations:
,
CRT
REFRESH
(OMA)
Start and initialize the 8275 CRT controllers.
Initialize the 8279 keyboaro controller.
Initialize the dual-port variables (parameter block).
Synchronize the 8275 CRT controllers.
To initialize and synchronize the 8275s, the channel
program performs the following operations:
POLLING
Figure 45. Channel Program Simplified Flowchart
As mentioned earl~er, the channel program is stored in
the 2732A EPROMs on the I/O bus. Figure 23 (above)
shows the address" assignments for devices on the I/O
bus. The 2732As occupy addresses 2000-3FFF. The
8089 also uses a scratch-pad static RAM (2K bytes at
3-164
Enable the GC CLK to the 8275s by writing 01H to
I/O port address .8000H.
Send the Reset command to the 8275s, followed by
the four screen format parameters (all commands
sent to the 8275& are sent first to the pair of 8275s at
address 6000H and then repeated for the second pair
of 8275s at address 4000H).
Send the Preset Counters command to the 8275s.
Disable the GC CLK by writing OQH to address
8000H.
Send the Start Display com~and to the 8275s.
Enable the GC CLK again by writing 01H to address
8000H. The 8275s 'are now initialized and
synchronized.
AFN-02172A
AP-123
After the initializations have been completed, the channel program enters its main loop. The 8089 channel
control register is loaded to specify the following DMA
conditions:
A
Data transfer from memory to 110 port.
~stination-synchronized transfer.
GA register pointing to data source.
Termination on external event.
Termination offset
= O.
The source for the DMA transfer (display page 0 or 1) is
then selected according to the value of DSPLY_PG-PI'R (the display page pointer initialized by the
host CPU) in the parameter block. The CRT character
clock is then started and the DMA transfer begins.
When the entire screen has been refreshed, the 8275s
activate the 8089's EXT input.
The 8089 then executes the SINTR instruction, which
causes an interrupt to be sent to the 8086 (SINTR-lline
on the Multibus), to notify the 8086 that the page transfer has been completed. The 8089 then reads the CRT
controller status registers which causes the IRQ signal
(from the 8275s to the 8089) to be reset.
The channel program then begins the polling process
which checks for ASCII commands from the 8~ (in
the command buffer) and also for key depressions at the
keyboard. In addition to the alphanumeric characters,
the channel program recognizes the following control
'
characters:
Character
CNTRL-A
CNTRL-B
CNTRL-C
CNTRL-D
CNTRL-E
CNTRL-F
CNTRL-G
CNTRL-H
CNTRL-I
CNTRL-J
CNTRL-K
CNTRL-L
CNTRL-M
CNTRL-N
CNTRL-O
CNTRL-P
CNTRL-Q
CNTRL-R
CNTRL-S
CNTRL-T
CNTRL-U
CNTRL-V
Code
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
CNTRL-W
CNTRL-X
CNTRL-Y
CNTRL-Z
CNTRLCNTRL-/
CNTRL-DEL
Description
Monitor Inhibit
Monitor Uninhibit
EEPROM Inhibit
EEPROM Uninhibit
Turn on EEPROM Buffer
Display Page 0
Display Page 1
Backspace
TAB (Every 8 Characters)
Linefeed
EEPROM Buffer Off
Erase Page
Carriage Return
Set Background Color
Set Foreground Color
Set Color to Black
Set Color to Red
Set Color to Green
Set Color to Yellow
Set Color to Blue
Set Color to Magenta
Set Color to Cyan
17
18
19
lA
IE
lC
IF'
Set Color to White
Abort Line
Cursor Right
Cursor Down and Left
Cursor Up
Cursor Home
Recall EEPROM Buffer
The first four commands listed above are not recognized if they originate from the physical keyboard, but
are recognized if they appear as ASCII commands in
the command buffer (that is, if they come from the
8086). Refer to the flowchart (Appendix A) for more
details on how the channel program responds to the
control characters.
System Performance
The 8089 performs DMA transfers on 921,600 bytes of
display data per second. In addition, the 8089 executes
a polling routine (described above) during the vertical
retrace time (the equivalent of two display rows). The
DMA transfer (for a single frame) takes 16.000 milliseconds. This leaves .667 millisecoRl,s for the polling
routine to execute, out of a total of lI60-second CRT
refresh period. The prolvam listed in Appendix B takes
about 300 microseconds to execute, approximately half
the available time. When the polling process is finished,
the channel program goes back to DMA mode, and
waits for the first DRQ signal from the 8275s.
While the polling routine is executing, the 8089 makes
most of its memory accesses in the 110 space, and the
dual-port RAM is available to the 8086. When the 8089
returns to the DMA routine, however, it hangs' the
dual-port RAM while waiting for DRQ. This occurs
because the fetch from the dual-port RAM deactivates
the 10 signal which locks out the 8086 from the dualport RAM. The 10 signal is then not activl;lted until
DRQ is received and the data is written to the CRT
controllers. This can adversely affect system throughput. Therefore, if it is desired to increase the 8086'8
access to the dual-port RAM during this period, the
user should insert NOPs into the channel program so
that it spends more time in the 110 space before returning to DMA.
The 8086 may also access dual-port RAM during the
DMA transfer. The dual-port RAM is available to the
8086 on approximately a 50% duty cycle (during the
store portion of the DMA transfer cycle). The 8089's
store cycle is 800 nanoseconds long (assuming a 5 MHz
clock). The 8086's access to dual-port RAM (assuming
an 8 MHz clock) takes 500 mmoseconds. However,
since the two processors operate asynchronously, the
8086 may begin its access at any point during the 8089's
3-165
AFN-02172A
DMA store cycle. Since. the 8086 is the master relative
to the dual-port RAM, the ready signal for tbe 8089's
next fetch operation will not be generated until the 8086
is through. Thus, on occasion, the 8089 will have to
wait.
,High-speed DMA transfers (up to 1.25 megabytes/second) without wait states.
Cap~ilities of ~ CPU and a: DMA controller in a
single 4O-pin package.
Support of concurrent operation for the system CPU
and the 110 processor. Ability to access memory and
address devices on both a system bus and a separate
110 bus.
Flexible, memory-based communications between
the 110 processor and the system CP~.
Capabilit~ for I-megabyte addressing in the system
space.
Capability for 16-bit DMA transfer, with external
event termination.
Support of modular, subsystem development effort
due to the simple software interface (memory-based
communications, plus channel attention and inter-'
rupt signals) and the simple hardware interface (CA,
SEL, and SINTR lines).
Each row of characters requires 256 microseconds of
DMA transfer time if no such wait states occur. The
rePetition rate for rows of characters is 333 microseconds .(1/3000 second). Thus, the accumulated wait
states due to the 8086'8 access to dual-port RAM may
total 77 microseconds before any underrun occurs. The
8086 programs should be written in such a manner that
the added wait states do not total 77 microseconds
during anyone period of 333 microseconds. The most
important single factor in assuring this is to avoid making long burst transfers to or from the dual-port RAM.
If an underrun does occur, the entire screen will be
blan~ed until the beginning of the next frame.
Aside from the shared access to dual-port RAM, the
two processors may operate concurrently with no coor- .
dination necessary. Operations performed by the 8086
(such as numeric processing of display data) may be
programmed without regard to the overhead associated
with lOP operations.
The following 8089 capabilities were not used in the
design described in this note, but may be useful in other
graphic CRT systems or 110 processing systems:
Conclusions
This application note has demonstrated that a highperformance, color-graphic CRT terminal can be conveniently built using the Intel iAPX 86/11
microprocessor system. This system utilizes a highperformance 8086 CPU operating at 8 MHz and an 8089
110 processor operating at 5 MHz; .
In particular, the unique abilities of the 8089 lend themselves to the graphic CRT application by enabling a true
multiprocessing approach to be usec:i. The following list
summarizes the capabilities used in this specific design:
Two channels, each of which may execute 'instructions and perform DMA transfers.
Bit manipUlation instructions.
Support of both 8-bit and 16-bit bus width in the
system 'space and in the 170 space.
Enhanced DMA capabilities" including:
Translation (e.g., ASCII to EBCDIC code).
Termination on masked compare.
Word assembly/disassembly (8-bit word to/from 16bit word).
;
Memory-to-memory or 1I0-to-II0 transfer.
Synchronization on source, destination, or neither.
3-166
AFN~172A
APPENDIX AlAP-123
INITIALIZATION AND MAIN LOOP
f " : \ STRING-IS
V
f":\REAILKYBD
V
SET UP CURSOR
POSITION IN 1275.
INCREMENT 8081
COMMAND STRING
POINTER
GELCOM
STRING-66
CLEAR 1066
COMMAND STRING
CHANGEDMA
SDURCE POINTER
TO DISPLAY PAGE 1
POINTER
CLEAR 8081
COMMAND STRING
POINTER
CURSOILUPDATE
3-167
AFN-02172A
APPENDIX
AJAp.,123
. ".'
.
,
,
,
KEY AND COMMAND DECODE'
GET ICEY _
3271
AND_IT
COILCNT
_ASCII
CHARACTER FOR
EEPROM BUFFER
RECALL
CURBDlLUPOATE
SAVEFI
'CHAR-OUT
CHARACTER AFTER
CNTL..-E IN BUFFER
FOR USE AS
_INDEX
INCREMENT EEPROM
BUFFERPTR
r--CNTIIL-A
_
CUIIBD~UPDATE
I CNTIIL-B
I CNTIIL-C
LC~R:O
_
01H
I12H
D3H
D4H
r CN-;R'; -
08H - - - -
I
07H
CNTIIL-G
MONITOIIINHIBIT
MONITOII UHINHIBIT
EEPIIOM INHIBIT
EEPIIOM UNINHIBIT
I ~::~:
::
I CNTIIL-P 10 CNTIIL-
CHAILCII
I ~TIIL-N
CDLOR-KEY
CNTIIL...N
CNTIIL-O
CNTIIL-!!
CNTIIL-K
EEP-DUMP
CUIIBDILTAB
EIlASLMGE
CNTIIL...X
CUIIBDIL_
UP_CUIIBDII
DWlLCURSOII
RIGHT_CU_
_ I CNTIIL-O
:::;17H
-
I~~
::
I CNTIIL-DEL
lFH
:~:~~
::
I
I
I
CNTIIL-X
~:~~
II::~
CNTIIL-Z
1__
1111
:t::
:::
lAN
IlAClLsPACE
IIACIL_
AFN-Q2172A
APPENDIX AlAP-123
CONTROL KEY OPERATIONS
INHIIIT THE_
FROMDMA
OPERATIONS
SET DUAL-PORT
DSPLY_PG-PTR TO
PAGE 0 FOR DMA
CLEAR EEPROM
BUFFER PTR
AND UNINHIBIT
EEPROM OPERATION
CURSOR-UPDATE
RESUME NORMAL
_TO.27S
DMA OPERATIONS
SET DUAL-PORT
OSPLY_PG-PTR TO
.PAGE 1 FOR DMA
INHIIIT EEPROM
CONTROL WORDS
AND THEIR
OPERATION
INSERT EEPROM
BUFFER EOF AND
FLAG_WITH
EEP_BUF_FULL
CURSOR UPDATE
INCREMENT
EEPROM BUFFER
POINTER
UNINHIIIT
EEPROM OPERATION
SET THE
CURSOILUPDATE
IlACK-COL-SW
VARIABLE TO
fOREGROUND
KEY-EEP_EXIT
FLAG 1018 BY
SETTING
EEP_RECALL
TOOFFH
INTR-II (DMJLLP)
AFN-P2172A
\
\
APPENDIX A/AP-123
CONTROL KEY OPERATIONS
KEY_BIIF_UPDATE
CURSOR-UPDATE
IACILGRDUND
STRIP I4W TO A
COLOR, FROM ....7
STRIPI4WrO
A COLOR FROM ....7
ANDS"IFT
LEFT ••ITS
UPDATE
FOREGROUND
SECTION Of
COLOR BYTE
UPDATE
BACKGROUND
8ECTIONOF
COLOR BYTE
CURSOR-UPDATE
IIGNALSOII
THAT THE KEYBOARD
BUFFER 18 FULL
3-170
AFN-02172A
APPENDIX AlAP·123
CONTROL KEY OPERATIONS
SET CHARACTER
COUNT TO
THE LEFT
IIARGIN
CLIAR KEYSOAIIIi
FULL .LAG AND
KEYBOARD
BUFFER POINTER
INCIlElll!NT
LlNILCNTTO
PERFORII UNEFEED
r------,
I
SAVE KEYSTROKE I
- - -I FOR IEPROII I
IL. _____
ANDIGII
.JI
KEY_EEP_EXIT
KEY_EEP_EXIT
INCREMENT
CHARACTER COUNT
TOIIOVE
CURSOR TO RIGHT
r-----,
I
- - -J
•
SAVE KEYSTROKE
I
I
L_____ J
DECREIIENT
LlNE-CNT TO PUT
CURSOR UP
ONE SPACE
, r--:---,
-
-
: BAVE KEYSTROKE I
FOR EEPROII I
I 'ANDIGII I
-I
L ____ ..J
DECREMENT
CHARACTER COUNT
AND INCREMENT
UNECOUNTIR
KEY_EEP_EXIT
KEY_EEP_EXIT
3-171
AI'N-02172A
APPENDIX AlAP-123
CONTROL KEY OPERATIONS
DECREMENT
CHARACTER
COUNTER
CLEAR KEYBOARD
INHIBIT AND CLEAR
SCROLL REQUEST
SET CHARACTER AND
LINE COUNTERS TO
UPPER LEFT
WINDOW ~OUNDARIES
DECREMENT
KEYBOARD BUFFER
POINTER
CURSOR-UPDATE
3-172
AFN-02172A
APPENDIX A/AP-123
SUPPORT SUBROUTINES
POINT AT DUAL-PORT
MClEOORMGE1
BY USING
OSPlY_PO-PTR
CALCULATE DISPLAY
PAGE ADDRESS
USING CHARACTER
AND UNE COUNT
SAVE ASCII CODE AND
COLOR IN THE
DIBPLAYMCIE
SAVE CHARACTER IN
KEY BUFFER AND
INCREMENT KEY
BUFFER POINTER
INCREMENT
CHARACTER
COUNTER
DECREMENT BUFFER
POINTER, SET
KEYBOARD FUU FLAG.
AND INSERT EOF
CHARACTER IN BUFFER
3-173
AFN-02172A
APPENDIXA!AP·123
SUPPORT SUBROUTINES
DECREMENT EEPROM
BUFFER POINTER
AND SET BUFFER
FULL FLAG
3-174
AFN-ll2172A
APPENDIX B/AP-123
8089 MACRO ASSEMBLER
ISIS-II BOB"1 MACRO ASSEMBLER X202 ASSEMBLY OF MDDULE NB"1
OBJECT MODULE PLACED IN :Fl:N8"1.0BJ
ASSEMBLER INVOKED BY:
:F2:ASM89 :F1:N89.SRC
1
2
3
8089 DUMB TERMINAL PROGRAM
4
5
B. K.NELSON
6
4/30/80
STARTED:
LAST CHANGE: 8/12/80
7
8
9
,
THIS PROGRAM INITIALIZES FOUR 8275 CRT CONTROLLERS AND A
8279 KEYBOARD CONTROLLER.
ASCII INFORMATION FLOW MAY FOLLOW
THESE PATHS:
KEYBOARD TO 0086 COMMAND INTERPRETER
KEYBOARD TO 8086 EEPROM ROUTINE
KEYBOARD TO MONITOR
8086
TO MONITOR
EEPROM
TO 8086 COMMAND INTERPRETER
EEPROM
TO 8086 EEPROM ROUTINE
EEPROM
TO MONITOR
10
11
12
13
14
15
16
17
18
19
20
COMMAND CODES ARE:
21 iK E
22 i - 23 ;- 24 ; - -
25 i - 26 i - 27 i - 28 i - 29 ; 0 X
30 i X X
31 ; X X
X -
32 ;
33 ;
34 ;
35 ;
36 ;
37 ;
X
X
X
X
X
X
X
X
X
X
38 ; X X
39 ; X X
40 ; X X
41 ; X X
42 ; X X
43 ; X X
44 ; X X
45 ;0 X
46 ; X X
47 ; X X
48 ; X
X
49 ; X X
50 ; -
51
-
CNTRL-A
CNTRL-B
CNTRL-C
CNTRL-D.
CNTRL-E
CNTRL-F
CNTRL-G
CNTRL-H
CNTRL-I
CNTRL-J
CNTRL-K
'CNTRL-L
CNTRL-M
CNTRL-N
CNTRL-O
CNTRL-P
CNTRL-a
CNTRL-R
CNTRL-S
CNTRL-T
CNTRL-U
CNTRL-V
CNTRL-W
CNTRL-X
CNTRL-Y
CNTRL-Z
CNTRL- A
CNTRL-\
CNTRL-DEL
MONITOR INHIBIT
MONITOR UNINHIBIT
EEPROM INHI.B IT
EEPROM UNINHIBIT
TURN ON EEPROM BUFFER
DISPLAY PAGE 0 SELECTED
DISPLAY PAGE 1 SELECTED
BAC~SPACE (CURSOR LEFT)
TAB (EVERY 8 CHARACTERS)
LINEFEED (CURSOR DOWN)
TURN EEPROM BUFFER OFF
ERASE PAGE
CARRIAGE RETURN
TURN OFF B.AC~GROUND/FOREGROUND*
TURN ON BAC~GROUND/FOREGROUND*
SET COLOR TO BLAC~
SET COLOR TO RED
GREEN
YELLOW
BLUE
MAGENTA
CYAN
WHITE
ABORT LINE
MOVE CURSOR RIGHT
MOVE CURSOR DOWN AND LEFT
MOVE CURSOR UP
HOME CURSOR
RECALL EEPROM BUFFER
S:-175
AFN-02172,.
APPENDIX BO~P-123
LINE SOURCE
52
53
THE TWO COLUMNS ASSOCIATED WITH EACH CONTROL KEY REPRESENT THI
-E
54
55
56
57
58
59
APPROPRIATE KEYBOARD AND EEPROM BUFFER ACTION CONNECTED WITH 1
-THAT
KEY.
KEYSTROKE NOT STORED IN BUFFER
x KEYSTROKE STORED IN BUFFER
o OPERATION PERFORMED ON BUFFER
A CHARACTER IS STORED IN THE EEPROM BUFFER ONLY IF THE OPERATI
-ION
61
WAS PERFORMED ON THE MONITOH.·
62 DUMB TERM
SEGMENT
63
64
8275 REGISTERS
65
66 CRT_REGS
STRUC
67
CRT_PARAM:
OW
1
68
CRT _COM_STAT: DW
1
69 CRT_REGS
ENDS
70
71
8279 REGISTERS
72
73 KYBD_REGS
STRUC
KBD_DATA:
74
OW
1
KBD_COM_STAT: DW
75
1
ENDS
76 KYBD_REGS
60
77
78
8086/8089 COMMON FLAGS
:'9
80 DP_RAM_FLAGS
TP _LSW:
81
TP_MSD:
82
83
EEP INH:
84
EEP _BUF JULL:
EEP _RECALL:
85
COL_CH INH:
86
87
KBD INH:
KBD_BUF _FULL:
88
89
90
91
COM_8086:
92
COLOR:
93
STRJ'TR_8086:
BACK_COL_SW:
94
95
MON INH:
DSPL Y_PG _PTR:
96
97
SCROLL_REG:
98
NEW_CHAR_FLAG:
99
NEW_CHAR:
100
STRUC
OW
DW
DB
DB
DB
DB
DB
DB
DB
DB
OW
DB
DB
DB
DB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DB
DB
1
1
101
102
103
104
105
MON_HOM:
MON_END:
MON_LMARG:
MON_RMARG:
DW
DW
DW
OW
1
1
1
1
3-176
AFN·02172A
APPENDIX B/AP·123
LINE SOURCE
KSD __BUF _,PTR:
OW
106
DB
1
E'.2_MON - INH:
107
108
ENDS
109 DP __RAMJLAGS
110
DISPLAY CHARACTER STRUCTURE
11'1
112
STRUC
113 CHAR_DEF
DB
COLOR_MODE:
1
114
ASC I I_GRAPH1: DB
1
115
DB
1
GRAPH_2AND3:
116
GRAPH_4AND5:
DB
1
117
ENDS
118 CHAR_DEF
119
PRIVATE 8089 FLAGS
120
121
122 STAT_RAM_FLAGS STRUC
DW
1
123
STACK:
STACK_MSD:
DW
1
124
DW
1
125
OW
1
126
EEP _BUF _PTR:
DW
1
127
128
129
LINE_CNT:
DW
1
130
CHAR_CNT:
DW
1
131
132
133
DB
1
134
ASC I I:
1
ASCII _TEMP:
DB
135
DB
1
CURSOR Xl:
136
DB
1
CURSOR X"'"
137
"',
CURSOR_Vi :
DB
1
138
CURSOR_Y2:
DB
1
139
140
141
DW
1
142
LINE_TEMP:
DW
1
CHAR_TEMP:
143
DW
1
PAGE_INDEX:
144
145 STAT_RAMJLAGS ENDS
146
ADDRESS EQUATES
147
148
EQU
OOOOOH
149 STAT_RAM
EQU
06000H
150 CRTl
151 ' CRT2
EQU
04000H
EQU
08000H
152 CLK_EN
EQU
OAOOOH
153 CRT_DATA
EQU
OCOOOH
154 KYBD
155
156
EQU
OF8000H
157 DSPLY_PAGEO
EQU
OFCOOOH
158 DSPLY _PAGEl
EQU
OFBDOOH
159 COM_BUF
OFBEOOH
EQU
160 EEP_BUF
EQU
OFBFOOH
161 KEY_BUF
EQU
OFFFOOH
162 DP _PB
.
-
3-177
AFN.()2172A
APPEMDIX BlAP-123
LINE SOURCE
163
164
165
166
167
168
169
170
171
172
173
174
175
176
DATA/COMMAND EGUATES
EQU
EOF
OFFH
CRT_RSl
EQU
OOOH
EQU
CRT_PARAM1
04F4FH
EQU
CRT_PARAM2
06F6FH
CRT _PARAM3
EGU
04444H
CRT_PARAM4
EGU
00606H
EQU
CRT_CURSOR
08080H
CRT_CNTR
EGU
OEOEOH
START_DISP
EGU
02020H
END_DISP_PG
EGU
15360
KBD_STR_SET
EGU
006H
1TI KBD_PRG_CLK
EGU
034H
EQU
178 KBDjIFO_RD
050H
179 ;*************************************************
180 ;*********** INITIALIZATION ********************
181 ;*************************************************
182
183
TURN ON THE CRT CHARACTER CLOCK AND RESET THE
184
CRT CONTROLLERS
185
186 START:
187
MOVl
GB.CLK_EN
188
MOVI
[GBJ.001H
189
MOVI
GB. CRT1
190
MOVI
GC.CRT2
191
MOVI
[GCJ.CRT_COM_STAT.CRT RST
192
MOVI
. [GBJ. CRT_COM_STAT, CRT_.RST
193
194
SUPPLY THE FOUR PARAMETER BYTES THAT SPECIFY
195
80X48 CHARACTERS. TRANSPARENT ATTRIBUTES, AND
196
A BLINKING UNDERLINE CURSOR
197
198
MOVI
[GBJ.CRT_PARAM1
199
MOVI
[GBJ.CR~_PARAM2
200
MOVI
[GBJ.CRT_PARAM3
201
MDVI
[GBJ.CRT_PARAM4
202
MOVI
[GCJ,CRT_PARAMl
203
MOVl
tGCJ.CRT_PA~AM2
204
MOVI
[GCJ,CRT_PARAM3
205
MOVI
tGCJ,CRT_PARAM4
206
207
SET CURSOR TO UPPER LEFT CORNER OF MONITOR
208
MOVI
tGCl. CRT_COM_STAT,CRT_CURSOR
209
210
MOVI
[GCJ.OOOH
211
MOVI
tGCl.OOOH
MOVI
[GBJ. CRT_COM_STAT, CRT __CURSOR
212
213
MOVI
[GBJ.OOOH
214
MOVI
rGBJ.OOOH
215
216
SYNCHRONIZE 8275 CLUSTER BY RESETTING COUNTERS
217
218
MOVI
[GCJ.CRT_COM_STAT,CRT_CNTR
219
MOVI
tGBJ.CRT_COMSTAT,CRT_CNTR
3-178
AfN.02172A
APPENDIX B/AP-123
LINE SOURCE
GC, STAT _.RAM
MOVI
220
[GCJ.CURSOR Xl,OOOH
MOVBI
221
[GCl.CURSOR_X2,000H
MOVBI
222
[GCJ.CURSOR_Yl,OOOH
MOVBI
223
(GCl. CURSOR_Y2,OOOH
MOVBI
224
225
INITIALIZE B27.~ KEYBOARD CONTROLLER
226
227
MOVI
GB,KYBD
228
MOVI
(G131. KBD_COM_STAT, KBD_STR ...SET
229
MOVI
[GBl.KBD_COM_STAT,KBD_PRG_CLK
230
MOVI
[GBl. KBD30M_STAT, KBDJIFO._RD
231
232
INITIALIZE 8089 FLAGS
233
234
MOVI
GC,STATYAM
235
GA, DP _PB
LPDI
236
(GCl.LINE_CNT,OOOH
MOVI
·237
[GCl.CHAR_CNT,OOOH
MOVI
238
239
240
(GAJ.EEP INH,OFFH
MOVBI
241
(GAl.EEP=BUF_FULL,OOH
MOVBI
242
[GA1.EEP_RECALL,00H
MOVBI
243
(GAJ.KBD_INH,OOH
MOVBI
244
[GAl.KBD_BUF_FULL,OOH
MOVBI
24~
[GAl.COM_8086,OOH
246
MOVBI
(GA1.COLOR,038H
MOVBI
247
CGA1.BACK_COL_SW,00H
MOVBI
248
(GA1.COL_CH_INH,00H
MOV13 I
249
MOVBI
(GAJ.SCROLLYEQ,OOH
250
[GAl. DSPLY_PG_PTR,OOH
251
MOVBI
(GAl. MON_INH,OOH
252
MOVBI
(GA1.E2_MON_INH,0
253
MOVBI
(GAl. MON_HOM,OOH
254
MOVI
(GAl. MON_END, 048
MOVI
255
MOVI
(GAl. MON_RMARG,080
256
MOVI
[GAl. MON_LMARG,OOH
2~7
258
259
INITIALIZE 8089 POINTER
260
MOVI
[GCl.EEP~BUF_PTR,OOH
261
MOVI
[GA1.STR_PTR_B086,00H
262
MOVI.
[GAl.KBD_BUF_PTR,OOOH
263
264 i**************************************************
;265 i*********** EXECUTIVE **************************
266 i**************************************************
267
268
DMA SET-UP
269
270
LOAD CHANNEL CONTROL REGISTER TO SPECIFY:
MEMORY TO PORT
271
272
SYNCHRO ON DEST
273
GA POINTS TO ·SOURCE
TERMINATE ON EXT
274
275
TERMINATION OFFSET=O
276'
3-179
AFN-l)2172A
APPENDIX B/AP-123
LINE SOURCE
GC, CLI..<._EN
2'77
MOVI
(GC],OOH
I I~HIBIT CHAR CLOCK
278
MOVI
279
ION 827~ TO SYNCHRONIZE
GC,CRTI
280
MOVI
281
[GC] CRT ...COM._STAT, START DISP
MOVI
GC,CRT2
282
MOVI
[GCJ. CRT_COM_STAT,START.DlSP
283
MOVI
284 DMA_LP:
CC,05120H
MOVI
285
286
287
SETUP DESTINATION AND THEN
288
SOURCE ACCORDING TO DISPLAY PAGE
289
POINTER
290
GB,CRT_DATA
291
MOVI
GA,DSPLY_PAGEO
292
LPDI
GC, DP _PB
293
LPDI
(GC]. DSPLY]G]TR, SOURCE_oOK
294
-.lZB
295
LPDI
GA, DSfLY._PAGEI
296 SOURCE_OK:
(GCJ.MON_INH,DMA_BYPASS I IF THE MONITOR IS INHIBI
297
-.lNZB
-ITED
; BYPASS THE DMA
298
(GCJ. E2_MON_INH, DMA .. .BYPASS_l
299
-.lNZB
GC,CLK_EN
300
MOVI
:301
START CRT CHARACTER CLOCK AND BEGIN DMA
302
303
304
XFER
(OC],OlH
MOVI
305
SINTR
306
307
308
SIGNAL THE 8086 THAT END OF FRAME HAS OCCURED AND THE UPDATINI
-G OF THE
309
INTERRUPT DRIVEN SECONDS COUNTER MAY BEGIN
310
311
READ CRT STATUS REGISTERS IN ORDER TO RESET IRG
. 312
313
GC,CRTI
314
MOVI
GA, (GCJ.CRT_COM STAT
315
MOV
316
MOVI
GC,CRT2
317
GB, (GCJ. CRT _COM . _STAT
MOV
DMA_BYPASS
318
-.IMP
319 DMA_BYPASS_l :
. MOVI
320
GC, 120
321 E2_WAIT_LOOP:
GB,300
322
MOVI
323 E2_I NNER _LOOP:
324
GB
DEC
GB,E2_INNER_LOOP
325
-.lNZ
326
GC
DEC
GC,E2_WAIT_LOOP
327
-.lNZ
328 DMA_BYPASS:
329
330
CHECK FOR STRING FROM 8086
331
IT HAS PRIORITY OVER KEYBOARD
3-180
AFN-02172A
APPENDIX BlAP·123
LINE SOURCE
332
GC,DP PB
LPD!
333
[GC·]. COM_8086. STRING __86
334
JNZB
335
CHECK 8279 KYBD STATUS
336
337
MOVI
GB.KYBD
338
MOVB
GA. [GBJ.KBD_COM_STAT
339
ANDI
GA.OFH
340
GA. READ~KYBD
i KEY DOWN
LJNZ
34'1
342
343
UPDATE THE CURSOR POSITION
344
345 CURSOR_UPDATE:
LPDI
GC,DP_PB
346
347
348
CHECK FOR 86 COMMAND CHARACTER MODE AND PROCESS
THE NEXT BYTE
349
JZB
[GC]. COM_80B6l COM._STR __BYPASS
350
INC
CGCl.STR_PTR_8086
351
352
JMP
GET30M
353 COM_STR_BYPASS:
MOVI
GB.CRTl
354
GC.STAT_RAM
MOVI
355
[GBl.CRT_COM_STAT.CRT CURSOR
MOVI
356
GA. [GCl.CHAR_CNT
iSET UP FOR X POSITION
357
MOVB
[GCl.CURSOR_Xl.GA
iCURSOR OUTPUT
358
MOVB
[GCl.CURSOR_X2.GA
iBY DOUBLING UP
359
MOVB
GA. [GCl.LINE_CNT
MOVB
360
iSAME FOR Y POSITION
[GCl.CURSOR_Yl.GA
361
MOVB
[GCJ.CURSOR_Y2,GA
362
MOVB
[GEl, [GCl.CURSOR_Xl
363
MOV
[GBl,[GCl.CURSOR_Yl
364
MOV
GB,CRT2
iDO IT FOR ALL
MOVI
365
[GBl. CRT._.COM_STAT, CRT_CURSOR
MOVI
366
[GBl. [GCl.CURSOR_Xl
iCONTROLLERS
367
MOV
[GBl. [GCl. CURSOR_Yl
MOV
368
369 INTR_86:
370
JMP
371 STRING_86:
372
MOVI
373 GET_COM:
IX. [GCl. STR_PTR._8086
374
MOV
GB,COM_BUF
375
LPDI
376
377
GET NEXT COMMAND CHARACTER FROM THE 8086
378
AND SAVE IT AS A KEYSTROKE
379
380
MOVB
GA. [GB+IXl
381
LPDI
GC,COM_BUF
'i***TEST CODE****
382
MOVB
GA. [GB + IXl
i***
383
LPDI
GC.DP_PB
i***
MOVI
GB,STAT_RAM
384
MOVB
[GBl.ASCII,GA
385
386
387
CHECK FOR END OF COMMAND STRING
388
3-181
AFN-02172A
APPENDIX··BtAP:'1.23
LINE SOURCE
389
MOVI
MC,OFFFFH
[GB]. ASC 11, COM_CNT
390
JMCNE
391
392
END OF COMMAND STRING-RESET COMMAND FLAG
393
[GC].COM_8086,00H
394
MOVBI
CURSOR __UPDATE
395
JMP
396 READ_KYBD:
397
398
TEMPORARY GET CHAR ROUTINE
399
JNZE
[GCJ.KBD_INH,CURSO~.~PDATE
400
JNZB
[GC J. KED._EUF _FULL, CURSOR __.UPDATE
401
402
403
IF THE KEYBOARD IS INHIBITED OR THE BUFFER FULL,
DONT READ THE 8279
404
405
GA, [GB].KBD_DATA
406
MOVE
407
NOT
GA
GA,007FH
408
ANDI
409
MOVE
[GCl. NEW_CHAR, GA
[GC]. NEW CHAR FLAG,l
410
MOVEI
GE, STAT_RAM -411
MOVI
[GEl. ASCII, GA
i SAVE KEYSTROKE
412
MOVB
413 COM_CNT:
GB,DP_PB
414
LPDI
415
MOVI
GC,STAT_RAM
416
CHECK FOR FIRST CHARACTER AFTER CNTRL-DEL, THIS CHARACTER WILL
417
418
BE PLACED IN EEP_RECALL AND USED FOR SELECTING WHICH EEP BUFFI
-ER
419
IS TO BE RECALLED
420
i IF MSB OF EEP_RECALL lSI
421
MOVB
GA; [GBl.EEP_RECALL
- SET
iUSE PRESENT ASCII CHARAI
422
ANDI
GA,007FH
-CTER
iAS INDEX FOR EEPROM RECI
423
JZ
-ALL
GA, [GCl.ASCII
MOVB
424
[GEJ.EEP_RECALL,GA
425
MOVB
426
JMP
CURSOR_UPDATE
427 NO_RECALL:
428
429
CHECK FOR FIRST CHARACTER AFTER CNTRL._E
430
THIS CHARACTER WILL BE PLACED IN THE
431
EEPROM BUFFER AND NOT PROCESSED
432
JNZE
[GBJ. EEP _INH, EEP._ElYPASS
433
[GCl.EEP_BUF-PTR,EEP_BYPASS
434
JNZ
435
436
INSERT ASCII CHARACTER
437
MOV
IX, [GCl.'EEP_BUF PTR
438
439
MOVB
GA, [GCl.ASCII
440
LPD!
GB,EEP_BUF
MOVB
[GE+IXl,GA
441
3-182
AFN·02172A
APPENDIX B/AP·123
LINE
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
SOURCE
INC
JMP
EEP _BYPASS:
[GC]. EEP _BUF]TR
CURSOR_UPDATE
CHECK FOR NON CONTROL CHARACTER
MOVI
L.JMCNE
MC,06000H
[GC]. ASCII, CHAR ..,.OUT
i*********************************************************
i*************** CONTROL KEY DECODE **********************
i*********************************************************
LOOK FOR 8086 COMMAND STRING SO CERTAIN
COMMANDS WILL NOT BE AVAILABLE FROM
KEYBOARD
CHECK FOR MONITOR INHIBIT
(CNTRL-A)
MOVI
JMCNE
MOVBI
JMP
NOT _CNTRLA:
MC,07F01H
[GC].ASCII,NOT_CNTRLA
[GBJ.MON_INH,OFFH
CURSOR_UPDATE
CHECK FOR MONITOR UNINHIBIT
(CNTRL-B)
MOVI
JMCNE
MOVBI
JMP
NOT_CNTRLB:
NOT _CNTRLC:
NOT _CNTRLD:
MC,07F02H
[GC J. ASC I I, NOT., CNTRLB
[GBJ.MON_INH,OOH
CURSOR_UPDATE
CHECK FOR SET DISPLAY PAGE 0
(CNTRL-F)
MOVI
JMCNE
MOVBI
JMP
NOT_CNTRLF:
MC,07F06H
[GC]. ASCII, NOT CNTRLF
[GBJ. DSPLY PG PTR,OOH
CURSOR_UPD;t\TE-
CHECK FOR SET DISPLAY PAGE 1
(CNTRL-G)
MOVI
JMCNE
MOVBI
JMP
NOT _CNTRLG:
MC,0'7F07H
[GC]. ASCI I, NOT...CNTRLG
[GB]. DSPLY_PG_PTR,OFFH
CURSOR_UPDATE
3-183
AFN-02112A
APPENDIX B/AP·123
LINE SOURCE:
499;
THE FOLLOWING CONTROL COI"lMANDS ARE
500
AVAILABLE THROUGH THE 8089 KEYBOARD
501
502
503
LOOK FOR CARRIAGE RETURN
504
MC,07FODH
505
MoVI
[GCl.ASCII,CHAR CR
506
LJMCE
507
508
LOOK FOR BACKSPACE
509 ;
MC,07F08H
510
MOVI
511
LJMCE
[GC]. ASC I I, BACK .._SPACE
512
513
LOOK FOR COLOR CONTROL KEYS
CNTRL-PTHRU CNTRL-W
514
515
MC,07810H
516
MOVI
517
LJMCE
[GC J. ASC I I, COLOR .}<'EY
518
519
CHECK FOR SET BACKGROUND COLOR FLAG
(CNTRL-N)
520
521
MC,07FOEH
522
MOVI
[GCl. ASCII,CNTRL_N
LJMCE
523
524
525
CHECK FOR SET FOREGROUND COLOR
(CNTRL-O)
526
MoVI
MC,07FOFH
527
528
LJMCE
EGC J. ASC I I, CNTRL._o
529
530
531
532
CHECK FOR EEPROM BUFFER RECALL
(CNTRL-DEL)
533
MOVI
MC,07F1FH
534
LJMCE
[GCJ.ASCII,EEP_DUMP
535
536
LOOK FOR TAB
537
(CNTRL-I)
538
539
540
MOVI
MC,07F09H
EGC J. ASC I I, CURSOR __TAB
541
LJMCE
542
543
LOOK FOR ERASE PAGE
(CNTRL-L)
544
545
MC,07FOCH
546
MoVI
[GCJ.ASCII,ERASE_PAGE
547
LJMCE
548
549
LOOK FOR CANCEL LINE
(CNTRL-X)
550
551
552
MOVI
MC,07F18H
553
LJMCE
[GCJ.ASCII,CNTRL_X
554
555
LOOK FOR HOME THE CURSOR
3-184
AFN-02172A
APPENDIX B/AP-123
LINE
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
SOURCE
(CNTRL \)
MOVI
LJMCE
MC,07F1CH
[GC]. ASC I I, CURSOR._HOME
LOOK FOR UP CURSOR
(CNTRL .', )
MC,07F1EH
MOVI
CGC]. ASCII,UP_CURSOR
LJMCE
LOOK FOR DOWN 'CURSOR
(CNTRL J)
MOVI
LJMCE
MC,07FOAH
CGC]. ASC I I, DWN .. CURSOR
LOOK FOR RIGHT CURSOR
(CNTRL-Y)
MOVI
LJMCE
MC,07F19H
[GC).ASCII,RIGHT_~URSOR
LOOK FOR DOWN AND LEFT CURSOR
(CNTRL-Z)
MOVI
LJMCE
MC,07F1AH
CGC). ASCII,BACK_DOWN
ALL OTHER KEY INPUTS ARE IGNORED
JMP
CURSOR_UPDATE
i**************************************************
i************* CONTROL SEGMENTS *****************
i**************************************************
SET THE COLOR BACKGROUND/FOREGROUND* FLAG TO
BACKGROUND (0)
CNTRL N:
MOVI
LPDI
GB,STAT_RAM
GC, DP _PB
CHECK FOR MONITOR OR COLOR CHANGE INHIBITED
JNZB
MOVBI
[GC). COL_CH_INH, KEEP._BF
[GC]. BACK_COL. __SW, OOH
KEEP _BF:
LJMP
SET THE COLOR BACKGROUND/FOREGROUND* FLAG
TO FOREGROUND
CNTRL_O:
MOVI
LPDI
GEl, STAT._RAM
GC,DP_PB
612
\3-185
APPENOIX· B/AP·:t 23
LINE SOURCE
613
CHECK. FOR MONITOR OR COLOR CHANGE INHIBITED
614
615
[GC]. COL_CH._INH, KEEP __BF;1
JNZB
616
MOVBI
[GC]. BACK. _.COL. SW, OFFH
617 KEEP __BF2:
618
LJMP
619
620
621
622
623
624
TURN ON THE EEPROM BUFFER
(CNTRL . _El
THIS ROUTINE INITIALIZES THE EEPROM BUFFER
POINTER
625
626 CNTRL_E:
627
MOVI
628
629
630
631
632
633
634
635
LPDI
LJNZB
MOVEI
MOVI
MOVBI
JMP
641
642
643
644
645
646
647
648
649
650
[GCJ.EEP~INH,OOH
CURSOR_UPDATE
TURN THE EEPROM BUFFER OFF
636
637 CNTRL_K:
638
MOVI·
639
LPDI
640
GB,STAT_RAM
GC,DP_PB
(GC]. EEP._BUF _FULL. CURSOR UPDATE
[GCJ.EEP_BUF_FULL,OOH
i********
CGBJ.EEP_BUF_PTR,OOH
LCALL
MOVBI
MOVBI
MOV
LPDI
GB,STAT_RAM
GC, DP _PB
[GB], KEY_BUF __UPDATE
(GC]. EEP_BUF_FULL,OFFH
[GCJ.EEP_INH,OFFH
I X, [GB]. EEP __BUF _'pTR
GA,EEP_BUF
INSERT END OF FILE MARKER
MOVBI
INC
JMP
[GA+IX],OFFH
eGB J. EEP _BUF YTR
CURSOR_UPDATE
651
652
DUMP EEPROM BUFFER 0-9
653
654 EEP _DUMP:
655
MOVI
LPDI
656
657
LPDI
658
MOVBI
-UT IT
GB,STAT_RAM
GC,DP_PB
GC, DP _PB
(GCJ.EEP_RECALL,OFFH
iSET FLAG TO ALL ONES, Bf
iWILL BE REPLACED BY THEI
659
- NEXT
660
661
662
JMP
663 CHAR_OUT:
664
MOVI
Ga,STAT_RAM
LCALL
[GB]' CHAR_TO_MON
665
666
667
PASS KEYSTROKES TO 8086
3-186
lASCII CHARACTER
AFNo02172A
, APPENDIX B/AP·123
LINE
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
SOURCE.
KEY_EEP_EXIT:
MOVI
LCALL
EEP _UP _EXIT'
MOVI
LCALL
JMP
CHAR_CR:
MOVI
LCALL
GB,STAT_RAM
[GBl,KEY_BUF_UPDATE
GB,STAT_RAM
[GBl, EEP __BUF __UPDATE
CURSOR_UPDATE
GB,STAT_RAM
[GBl,CR_UPDATE
SET KEYBOARD AND EEPROM BUFr-ER FULL
FLAGS IF NOT INHIBITED
MOVI
LPDI
JNZB
GB,STAT_RAM
GC,DP_PB
[GCl. COM_8086, CURSOR_,UPDATE
i
IF IN 8086 COMMI
-AND
iMODE, DONT ALTER
686
iKEYBOARD STATUS
687
GB,STAT_RAM
MOVI
688
[GBl,KEY_BUF_UPDATE
LCALL
689
690
MOVBI
[GCl.KBD_BUF-FULL.OFFH i******
691 EEP _CHK:
JMP
692
693
ALTER BACKGROUND OR FOREGROUND COLOR ACCORDING
694
695
,TO THE 3 LEAST SIGNIFICANT BITS OF THE INPUT
696
KEY AND THE STATUS OF THE BACKGROUND/FOREGROUND*
697
FLAG.
698
699 COLOR_KEY:
GB,STAT_RAM
700
MOVI
701
GC,DPYB
LPDI
[GBl,EEP_BUF_UPDATE
702
LCALL
[GBl,KEY_BUF_UPDATE
703
LCALL
[GCl. COL_CH_INH, CURSOR __UPDATE
704
LJNZB
GA, [GCl.BACK_COL_SW
MOVB
705
706
707
CHECK B/F* FLAG
708
JNZ
GA,BACK_GROUND
709
MOVB
GA, [GBl.ASCII
710
ANDI
GA,07H
711
MOV
[GBl.ASCII,GA
712
MOVB
GA, [GCl.COLOR
713
ANDI
GA,038H
714
715
716
OR INPUT COLOR INTO FOREGROUND SECTION OF COLOR BYTE
717
718
GA, [GBl.ASCII
ORB
719
[GC]. COLOR,GA
MOVB
720
JMP
CURSOR_UPDATE
721 BACK_GROUND:
GA, [GBl.ASCII
722
MOVE
GA, [GBl.ASCII
723
ADD
3-187
AFN-02172A
APPENDIX;S/AP..128
LINE SOURCE
724
·725
726
727
728
729
730
731
732
733
734
ADD
ADD
MOVEl
ADD
GA, [GBl. ASCII
GA, WB J. ASC II
CGBJ.ASCII_TEMP,GA
GA, [GBl. ASCII TEMP
SHIFT INPUT COLOR OVER AND OR IT INTO THE BACKGROUND
SECTION OF THE COLOR BYTE
ANDI
MOV
MOVB
ANDI
ORB
MOVB
JMP
735
736
737 '
738
739
740
741
742
GA,038H
[GBl. ASCII. GA
GA, [GCl.COLOR
GA.047H
GA. [GBl.ASCII
. [GCl. COLOR. GA
CURSOR_UPDATE
TAB ROUTINE
THIS ROUTINE MOVES THE CURSOR TO THE NEXT
COLUMN WHOSE NUMBER IS A MULTIPLE OF 8.
743
744
745 CURSOR_TAB:
746
747
748
749
MOVI
LCALL
LCALL
LPDI
GB.STAT_RAM
[GBl.EEP_BUF_UPDATE
[GBl.KEY_BUF_UPDATE
GC.DP_PB
750
751
CHECK FOR CHARACTER COUNT BEING A
752
MULTIPLE OF EIGHT (3 LSB = 0)
753
754 TAB_CNT:
755
756
PLACE BLANK ON THE SCREEN
757
MOVBI
LCALL
MOV
ANDI
758
759
760
761
LJZ
JZB
JMP
762
763
764
765
766
767
773
774
CURSOR_UPD~TE
ERASE PAGE ROUTINE
THIS ROUTINE ERASES THE PAGE FROM THE CURRENT
CURSOR POSITION.
IT ENDS WITH THE CURSOR AT
THE HOME POSITION.
768
769
770
771
772
[GBl. ASCII, 020H
[GBl,CHAR_TO_MON
GA.CGBl.CHAR_CNT
GA.07H
GA,CURSOR_UPDATE
CGCl.SCROLL_REG,TAB CNT
I
UP CURSOR ROUTINE
775 UP _CURSOR:
776
·MOVI
777
LPDI
778
MOV
779
NOT
780
AND
GB.STAT_RAM
GC.DP_PB
'IX, [GCl. MON_HOM
IX
IX, CGBl.LINE_CNT
3~188
iCHECK FOR UPPER BOUNDARY
AFN-02172A
APPENDIX B/AP-123
LINE SOURCE
781
LJZ
IX. CURSOR_UPDATE
[GB J. LINE_.CNT
782
DEC
783
JMP
KEY _EEP ._EX 1T
784
785
LINE FEED (DOWN CURSOR)
786 i
787 DWN_.CURSOR:
788
MOVI
GB. STAT._RAM
789
LPDI
GC. DP._PB
790
MOV
IX. (GBl, LINE._CNT
791
INC
IX
792
NOT
IX
793
AND
IX. (GCJ.MON_END
iCOMPARE PRESENT LINE
iCOUNT + 1 TO BOTTOM
i MARGIN
i IF EQUAL ABORT CURSOR MI
-OVE
794
LJZ.
I X. CURSOR._UPDATE
795
[GB ]. LI NE_CNT
INC
796
JMP
KEY _EEP _EX IT
797
MOVE CURSOR RIGHT
798
799
800 RIGHT _CURSOR:
801
MOVI
GB.STAT_RAM
802
GC. DP _PB
LPDI
IX, [GBJ.CHAR_CNT
803
MOV
i
MOVE OK
iCOMPARE PRESENT CHARACTI
-ER
804
INC
805
NOT
806
AND
807
LJZ
808
INC
809
JMP
810 BACK_DOWN:
.811
MOVI
812
LPDI
813
MOV
814
INC
815
NOT
816
AND
IX
IX
IX. [GCJ.MON_RMARG
IX. CURSOR_UPDATE
[GBJ. CHAR_CNT
KEY _EEP _EX IT
GB.STAT_RAM
GC.DP_PB
IX. (GBJ.LINE_CNT
IX
IX
, IX. [GCJ. MON_END
iCOUNT + 1 TO RIGHT
i MARGIN
i IF EQUAL ABORT
i CURSOR MOVE
i MOV OK
iCOMPARE PRESENT LINE
iCOUNT + 1 TO BOTTOM
i MARGIN
i IF EQUAL ABORT CURSOR MI
-OVE
817
818
LJZ
MOV
-RGIN
NOT
AND
LJZ
INC
DEC
JMP
IX. CURSOR_.UPDATE
·IX. (GCJ.MON_LMARG
i
IF CURSOR IS AT LEFT MAl
819
IX
iABORT CURSOR MOVE
820,
IX. [GB]. CHAR_CNT
821
IX. CURSOR_UPDATE
822
[GBJ. LINE_CNT
823
[GBJ.CHAR3NT
824
KEY_EEP_EXIT
825
826
CANCEL THE PRESENT LINE
827
828 CNTRL_X:
829
MOVI
GB.STAT_RAM
830
LPDI
GC.DP]B
831
MOV
[GBl. CHAR_CNT. [GCl. MON._LMARG
832 i'
833
RESET THE KEYBOARp BUFFER POINTER
3-189
AFN-02172A
APPENQllt B/AP~123
LINE SOlJRCE
834 ,
MOVBI,
835
[GCl, KBD ...BUF._FllLL. OOH
MOVI
r.GCl.KBD_BUF_PTR,OOH
836
,JMP
837
KEY _EEP _EX I T
838 ERASE_PAGE:
G8,STAT_RAM
839
MOVI
840
LCALL
[GBl, EEP._BUF._UPDATE
[GBl, KEY":'BUF._UPDATE
841
LCALL
GC,DP]B
842
LPDI
843 ),
'STORE BLANKS ON THE SCREEN
844
845
[GBl. ASCII, 020H
846
MOVBI
847 ERASE_CNT:
[GBl,CHAR_TO_MON
848
LCAL.L
[GC l, SCROLL_REG, ERASE._CNT
.JZB
849
,JMP
850
CH_NTR
851
852
'HOME THE CURSOR
853
854 CURSOR_HOME:
855 MOVI
GB,STAT_RAM
856
LCALL
[GBl,EEP_BUF_UPDATE
[GBl,KEY_BUF_UPDATE
857
LCALL
858 CH_NTR:
GC,DP_PB
859
LPDI
860
[GCJ.KBD_INH,OOH
MOVBI
861
MOVBI
[GCJ.SCROLL_REG.OOH
862
MOV
[GBJ. CHAR_CNT. [GCl. MON..LMARG
\ [GBJ. LINE_CNT. [GCJ. MON...HOM
MOV
863
,JMP
CURSOR_UPDATE
864
865
PERFORM BACK-SPACE BY DECREMENTING THE DISPLAY
866
867
PAGE POINTER, KEYBOARD POINTER. EEPROM POINTER,
868 ; , AND CURSOR POSITION
869
870 BACK_SPACE:
,
871,
MOVI
GB.STAT_RAM
872
LPDI
GC,DP]B
;' IF CURSOR IS AT LEFT
873
MOV
IX. [GCJ.MON_LMARG
;MAR~IN ABORT BACKSPACE
874
NOT
IX
IX, [GBl.CHAR_CNT
875
AND
876
L,JZ,
IX. CURSOR_UPDATE
877
DEC
[GBl. CHAR_.CNT
878
879
DO BACKSPACE IF MONITOR NOT INHIBI,TED AND CURSOR, IS
880
NOT AT THE BEGINNING OF A LINE,
881
882 KYBD_UPDATE:
883
L,JNZB
884
885
IF KEY BUFFER POINTER IS ZERO. DONT BACKSPACE IT
,886
887
[.GCl. KBD_BUF _PTR, EEP ..EXJT,
JZ
888
[GCJ.KBD_BUF_PTR
DEC
889 EEP _E'XIT:
GB, STAT _RAM
890
MOVI
'3·190
AFN-02172A
APPENDIX B/AP-123
LINE SOURCE
891
JMP
;***************************************************
893 ,*************** SUBROUTINES *********************
894 ;***************************************************
892
895 CHAR_TO_MON.
896
SET UP DISPLAY PAGE POINTER AND INDEX
897
898
899
LPDI
GB,DSPLY]AGEO
GC,DP"'pB
900
LPDI
[GC].DSPLY_PG_PTR,PTR _._OK
901
JZ
GB,DSPLY_PAGE1
902
LPDI
903
904
COMPUTE BOXLINE_CNT
905
906 PTR_OK:
GC,STAT_RAM
907
MOVI
GA, [GCJ.LINE_CNT
Mdv
908
GA, [GCJ.LINE_CNT
ADD
909
GA, [GCJ. LINE __.CNT
910
ADD
GA, [GC]. LINE_CNT
911
ADD
GA, [GCl.LINE_CNT
912
ADD
[GCl. LINE.JEMP, GA
913
MOV
GA, [GC]. LINE_TEl'lP
914
ADD
2 X 5
{GCl. LINE_TEMP, GA
915
MOV
916
GA, [GCJ. LINE_TEMP
4 X 5
ADD
[GCJ. LINE_TEMP,GA
MOV
917
918
ADD
~A, [GCJ.LINE_TEMP
8 X 5
[GCJ.LINE_TEMP,GA
MOV
919
GA, [GCJ. LINE __TEMP
920
16 X :.;
ADD
921
922
MEMORY POINTER = DISPLAY PAGE POINTER +
923
4X (80XLINE._.CNT + CHAR .._CNT>
924
ADD
GA, [GCJ.CHAR_CNT
925
MOV
[GCJ.LINE_TEMP,GA
926
927
ADD
GA, [GCJ. LINE_.TEMP
928
ADD
GA, [GCl.LINE_TEMP
ADD
GA, [GCl.LINE_TEMP
929
930
MOV
[GCJ.PAGE_INDEX,GA
931
ADD
GB, [GCJ.PAGE_INDEX
932
933
SAVE ASCII CODE IN DISPLAY PAGE
934
[GBJ.ASCII_GRAPH1, [GCl. ASCII
935
MOVB
936
937
SAVE BACKGROUND AND FOREGROUND COLOR IN
938
DISPLAY PAGE
939
'LPDI
GC,DP_PB
940
[GBJ.COLOR_MODE, [GC].COLOR
941
MOVE
942
943 ;
CLEAR OTHER 2 DISPLAY PAGE BYTES
944
[GB].GRAPH_2AND3,OOH
MOVEI
945
946
[GE]. GRAPH_4AND5,00H
MOVEI
947
3-191
AFN-02172A
APPENDIX B/AP-12.3
LINE SOURCE
948
INCREMENT XCURSOR POSITION AND CHARAC1ER POINTER.
949
CHECK .FOR RIGHT MARGIN OVERRUN
950
OB,STAT_RAM
951
MOVI
952
INC
CGBJ.CHAR_CNT
CGE]. CHAR._TEMP, [(~Bl. CHAR CNT
953
MOV
954
NOT
[GBJ.Ct-!AR_TEMP
GA, CGCl. MON_RMARG
955
MOV
956
AND
GA, [GBT. CHAR._TEMP
957
.JNZ
GA,MON_UPDATE..FIN
958 CR_UPDATE:
959
IF RIGHT MARGIN WAS EXCEEDED, MOVE CHARACTER COUNT
960
TO LEFT MARGIN AND INCREMENT LINE COUNT AND Y CURSOR
961
POSITION
GC,DP_PB
962
LPDI
GB,STAT_RAM
963
MOVI
[GBl. LINE_.CNT
964
INC
965
MOV
[GB]. CHAR3NT, [GCl. MON ...LMARG
966
CHECK IF LINE COUNT WENT/PAST BOTTOM OF SCREEN
967
968
969
CGBl.LINE_TEMP. [GBl.LINE.CNT
MOV
[GBl. LINE._TEMP
970
NOT
971
GA. CGBl.LINE_TEMP
MOV
972
AND
GAd GC]. MON_END
973
GA,MON_UPDATE_FIN
.JNZ
974
975
LINE COUNT EXCEEDED BOTTOM MARGIN···
976
SET SCROLL FLAG
977
AND KEYBOARD INHIBIT AND DECREMENT LINE COUNT
978
979
MOVBI
CGCJ.SCROLL_REG.OFFH
980
MOVBI
CGCl. KBD __ INH, OFFH ; ****
981
DEC
CGBl. LINE_CNT
982 MON_UPDATE_FIN:
983
984
RETURN TO CALLING ROUTINE
985
986
MOVI
GB,STAT_RAM
987
LPDI
GC,DP_PB
988
MOVP
TP, CGBl
989
990
KEYBOARD BUFFER SUBROUTINE
991
992
TRANSFER THE ASCII. CHARACTERS OBTAINED FROM THE
993
8279 CONTROLLER INTO A BUFFER FOR LATER
994
PROCESSING BY THE 8086.
995
996 KEY _BUF _UPDATE:
997
LPDI
GC,DP_PB
998
MOVI
GB,STAT_RAM
999
1000
BYPASS IF BUFFER FULL
1001
1002
1003
1004
BYPASS IF 8086 COMMAND MODE
3-192
AFN.Q2172A
APPENDIX B/AP·123
LINE
1005
1006
1007
1008.
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
SOURCE
,
·.JNZB
[GC] COM._8086,
KBU._RETU~N
,
XFER THE CHARACTER
MOV
LPDI
MOVB
INC
MoV
ANDI
JZ
IX, [GeJ.KBD BUF PTR
GA, KEY._BUF
[GA+IXl, [GBl.ASCII
[GCl.KBD._BUF_PTR
GA, [GCl. KBD_BUF. PTR
GA,OFFOOH
GA,KBU_RETURN
POINTER OVERRUN-SET BUFFER FULL FLAG
DEC
MOVBI
MOVBI
KBU_RETURN:
MOVP
[GCJ. KBD._BUF _PTR
[GCJ. KBD_BUF_FULL,OFFH
[GA+IXl,OFFH
;SET END OF BUFFER MARKER
TP, [GBJ
EEPROM BUFFER SUBROUTINE
THIS ROUTINE TRANSFERS THE ASCII CHARACTERS OBTAINED
FROM THE 8279 CONTROLLER INTO THE DUAL PORT EEPROM BUFFER
EEP _BUF _.UPDATE:
MOVI
LPDI
G.B, STAT .:...RAM
GC,DP]B
CHECK FOR BUFFER FULL FLAG OR EEPROM INHIBITED
JNZB
JNZB
[GCl.EEP_INH,EBU_RETURN
[GC J. EEP._BUF _FULL, EBU __RETURN
XFER THE CHARACTER
MoV
LPDI
MOVE
INC
MOV
ANDI
JZ
I X, [GB J. EEP _BUF .._P TF!
GA,EEP_BUF
[GA+IXl, [GBJ.ASCII
[GBJ.EEP_BUF_PTR
GA, [GBJ. EEP _BUF ... PTR
GA,OFFOOH
GA,EBU_RETURN
POINTER OVERRUN-SET BUFFER FULL FLAG
DEC
MOVBI
EBU_RETURN:
MOVP
DUMBTERM
[GBl. EEP _BUF _PTR
[GCl.EEP~BUF_FULL,OFFH
TP, [GBJ
ENDS
END
3-193
AFN~172A
inter
APPLICATION .
NOTE
March 1982
Order Number. 21~OO1
©INTEL ~RPORATION, 1982
3-194
J
AP-143
•
INTRODUCTION
As the performance of microcomputers has improved,
the types of functions performed by these microcomputers have grown. One application filled by these
machines has been to perform typical "adding
machine" type calculations, balancing ledgers, etc. This
type of machine has come to be called a "small business
computer." To be a tru~ business computer, however,
the types of operations performed by these machines
need to be expanded beyond simple "balance the
books" types of operations. There are many algorithms
.that have been impractical for these small business computers because the number of calculations required by
the algorithms and the performance available from
these machines did not make them feasible. Such operations were available only on large mainframe or minicomputers. With the introduction of the iAPX 86120, a
microcomputer can finally perform these types of
calculations at a cost level appropriate to small business
computers.
Linear Programming. These calculations require
extensive use of floating point multiplication and
division. One of many applications for linear programming is the determination of optimum production quantities of diverse products when the
quantities of their various constituents are both
overlapping and limited.
iAPX 86/20 HARDWARE OVERVIEW
The iAPX 86120 is a 16-bit microprocessor based on the
Intel 8086 CPU. The 8086 CPU features eight internal
general-purpose 16-bit registers, memory segmentation,
and many other features allowing for efficient code
generation from high-level language compilers. When
augmented with the 8087, it becomes a vehicle for highspeed numerics processing. The 8087 adds eight 80-bit
internal floating point registers, and a floating point
arithmetic logic unit (ALU) which can speed floating
point operations up to 100 times over other software
floating point simulators or emulators.
The iAPX 86120 features the Intel 8086 with the 8087
numerics co-processor. This combination allows for
high-performance, high-precision numeric calculations.
Many types of operations require this performance to
provide accurate results in a reasonable amount of time.
This increased performance will also be particularly
welcome in the interactive user environment, typically
found in small business computer;. It is very frustrating
to wait many seconds or even minutes after hitting
"return" for the computer to generate results.
The 8086 and 8087 execute a single instruction stream.
The 8087 monitors this stream for numeric instructions.
When a numeric instruction is decoded, the 8086
generates any needed memory addresses for the 8087.
The 8087 then begins instruction execution automatically. No other software interface is required, unlike
other floating point processors currently available
where, for example, the main processor must explicitly
write the floating point numbers and commands into the
floating point unit. The 8086 then continues to execute
non-numeric instructions until another 8087 instruction
is encountered, whereupon it must wait for the 8087 to
complete the previous numeric instruction. The overlapped 8086 and 8087 processing is known as concurrency. Under ideal conditions, it effectively doubles the
throughput of the processor. However, even when a
steady stream of numeric instructions is being executed
(meaning there is no concurrency), the numeric performance of the 8087 ALU is much greater than that of
the 8086 ~Ione.
In general, if there are many methods to solving a
business computer problem, the method requiring the
largest number or calculations will. provide the best
results. In many applications, approximate methods
have been used because the speed of the hardware (or
the cost of the computer time) did not allow a more exact method to be used. Because of the high performance
of the iAPX 86120, these numeric intensive methods
may now be used in small business computer software.
The types of calculations demonstrated in this note are:
The hardware interface between the 8086 and the 8087 is
equally simple. Hardware handshaking is performed
through two sets of pins. The RQ/GT pin is used when
the 8087 needs to transfer operands, status, or control
information to or from memory. Because the 8087 can
transfer information to and from memory independent
of the 8086, it must be able to become the "bus
master," that is, the processor with read and write control of all the address, data and status lines. Only one
unit is permitted to have control of these lines at a time;
chaos would exist otherwise, like four people talking at
once with each trying to understand the others.
• Interest and Annuities. These calculations require
the use of floating point multiplication, division,
exponentiation and logarithms. These calculations
are used to determine the present or future value
of certain types of funds.
• Restocking. These iterative calculations require
extensive use of floating point multiplication and
division. They are used to determine the optimum
restocking times for a given item when the set-up
charges, holding costs and demand for the item
are known or can be estimated.
3-195
AFN.()2184A
AP-143
The TEST IBUSY pin is used to manage the concurrency mentioned above. Whenever the 8087 is executing
an instruction, it sets the BUSY pin on high. A single
8086 instruction (the WAIT instruction) tests the state
of this pin. If this pin is high, the WAIT instruction will
cause the 8086 to wait until the pin is returned to low.
Therefore, to insure that the 8086 does not attempt to
fetch a numeric instruction while the 8087 is still working on a previous numeric instruction, the WAIT, instruction needs to be executed. The 8086/87/88
assembler, in addition to all Intel compilers, automatically inserts this WAIT instruction before most
numeric instructions. Software polling can be used to
determine the state of the BUSY pin if hardware handshaking is not desired.
In addition to the 8087 hardware, the 8086 is also supported by Intel compilers for both Pascal and FORTRAN. Code generated by these compilers can easily be
combined with code generated from the other compiler,
from the Intel 8086/87/88 macro assembler ,or the Intel
PL/M compiler. In addition, these compilers produce
in line code for the 8087 when numeric operations are
required. 'By producing in line code rather than calls to
floating point routines, the software overhead of an unnecessary procedure call and return is "eliminated. The
combination of both hardware co-processors and software support for the iAPX 86120 provides for greater
performance of both the end product, and its development effort.
Most other lines (address, status, etc.) are connected
directly in parallel between the 8086 and the 8087. An
exception to this is the 8087 interrupt pin which must be
routed to an external interrupt controller. An example
iAPX 86120 system is shown in Figure 1. A more complete discussion of both the handshaking protocol between the 8086 and the 8087 and the internal operation
of the 8087 can be found in the application note Getting
Started With the Numeric Data Processor, AP-113 by
Bill Rash, or by consulting the numerics section of the
July 1981 iAPX 86,88 Users Manual.
ROUTINES IMPLEMENTED
INT
8259A
PIC
I
INTR
,--- ClK
I
L -- J
r-
IRn
CPU
iiOJGT1
QSO QS1
'--
TEST
~
+ +
QS1 BUSY
QSO
8284A
CLOCK
GENERATOR
~
\r-
8086/8088
t
ClK
lIMSL, Inc., 'Sixth Floor-NBC Building, 7500 Bellaire
Boulevard, Houston, Texas, 77036. (713) 722-1927.
...,
r
I
I
All routines implemented in this application note were
written entirely in either Pascal 86 or FORTRAN 86. In
addition, a FORTRAN program available from IMSL 1
for use in solving linear programs was used. In each
IV'
iiOJGTO
NDP
INT
\
SYSTEM BUS
J
...J
iiOJGT1
I
I
I
r
I
I
L
.II
/'-.,
'\r-~
g
8087
ClK
T
8088
FAMilY
BUS
INTERFACE
COMPONENTS
-
~t~ ...,
RQIGT
8089
~ClK
lOP
r'r--.
I
I
L..
I ,1_
-
-
...J
Figure 1. Typical 86/20 System
3-196
AFN'()2184A
AP-143
case, the routine was executed using a 5 MHz iAPX
86/20 on an iSBC86/12 board contained within an Intel
Intellec™ Series III development system. The programs
can be executed on any iAPX 86/20 (or iAPX 88/20)
with sufficient ,memory, however. In general, the
memory requirements for the programs were not
substantial. Source listings' for all routines written for
this note are la<;ated in the appendix.
All routines were run using both the S087 and the S087
software emulator. The 8087 software emulator is a
software package exactly emulating the internal operation of $e 80117 using 8086 instructions. When the
emulator is used, an 8087 is not required. The emulator
is a software product available from Intel as part of the
8087 support library. The performance of the 8087
hardware is much better than that of the software
emulator, as one would expect from a specialized floating
point unit.
.
.
In some routines, values are quoted for the various data
formats supported by the 8087. For real numbers, these
formats are short real, long real, and temporary real.
The differences among the three are in' the number of
bits allocated to represent a: given floating point
number.
In all real numbers, the data is split into three fields: the
sign bit, the exponent field and the mantissa field. The
sign bit indicates whether the number is positive or
negative. The exponent and mantissa together provide
the value ,of the number: the exponent providing tl;le
power of two of the number, and the mantissa providing the "normalized" value of the number. A "normalized" number is one which always lies within a certain range. By dividing a number by a certain power of
two, most numbers can be made to lie between the
numbers 1 and 2. The power of two by which the
number must be divided to fit within this range is the
exponent of the number, and the result of this division is
the mantissa. This type of operation will not work on all
numbers (for example, no matter what one divides zero
by, the result is always zero), so the number system must
allow for these certain "special cases."
As the size of the exponent grows, the range of numbers
representable also grows, that is, larger and smaller
numbers may be represented. As the size of the mantissa
grows, the resolution of the points within this range
grows. This means the distance between any two adjacent numbers decreases, or, to P\lt it another way, finer
detail may be represented. Short real numbers provide
eight exponent bits and 23 significand or mantissa bits.
Long real numbers provide 11 exponent bits and 52
significand bits. Temporary real numbers provide 15 exponent bits and 63 significand bits. These data formats
are shown in Figure 2. Thus, of the three data, formats
implemented, short real provides the least amount of
precision, while temporary real provides the greatest
amount of precision. These levels of precision represent
only the external mode of storage for the numbers; inside the 8087 all numbers are represented in temporary
real precision. Numbers are automatically converted
into the temporary real precision when they are loaded
into the 8087. In addition to real format numbers, the
8087 automatically converts to and from external
variables stored as 16, 32 or 64-bit integers, or SO-bit
binary coded decimal (BCD) numbers.
Memory requirements also increase as precision increases. Whereas a short real number requires only four
bytes of storage (32 bits), a long real number requires
eight bytes (64 bits) and a temporary real number 10
SIGNIFICAND
LONG REAL
lsi
J~~NT
I
I
SIGNIFICAND
~A~--------~~~'==---IA--.----------------------~o
TEMPORARY REAL
Is I
J~i~T
51
SIGNIFICAND
~n~------------~M~A~i----------------------------------~
Figure 2. Data Formats
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AFN-021_
AP-143
Table
bytes (SO bits)! In many floating point processors, processing time also increases dramatically as precision is'
increased, making this another consideration in' the
choice of precision tO'be used by a routine. The dif.ferences in 8087 processing time among short real, long
real and temporary real numbers is relatively insignificant, however. This makes the choice of which precision '
to use in an iAPX 86/20 system a function only of
memory limitations and precision requirements.
1':
Short real
Long real
Temp real
Interest Rate Calculation Results
18r
Final value'
10.5141110
10.5161110 '
10.5161110
$2,210,287.50
$2,210,311.57
$2,210,311.57
The times required to calculate these results using FORTRAN 86 with both the S087 and the 8087 emulator are
shown in Table 2.
Interest
Table 2. Interest Rate Calculation Times
Routines were written to calculate the final value of a
fund when given the annual interest and the present
value. Although the calculations required to generate individual interest values are rather short, the additional
precision of the'iAPX 86120 can be used to generate
better results. In addition, if a large number of interest
calculations are to be performed (or if an interest rate
type of calculation is used as part of an iterative model),
the speed of the single interest rate calculation is important, as it will be performed very many times.
Short 'real
Long real
Temp reaJ.
It is assumed that the interest will be compounded daily,
which requires the calculation of the yearly effective
rate. This value, which is the equivalent annual interest
rate when interest is compounded daily, is determined '
by the following formula:
np
Where:
• yer is the yearly effective rate
• i is the ~ual interest rate
8087
Emulator
1.052 ms
1.058 ms
1.041 ms
100.4 ms
100.7 ms
100.8 ms
The difference in the final value between the short real
and long real precision in this simple calculation is
$24.07: Although the difference between short and long
real precision results shown here is small, this difference
would be signficant if the principal was larger, or,if the
period over which the interest was calculated was longer
than a single year. Hence, the fong real precision
capability of the 8087 can provide most accurate results.
Indeed, since the error calculated between the long real
precision and temporary teal precision results is in the
thousandths of cents, the long'real results ·are exactly
, correct, to the penny. Note that temporary real format
allows for approximately 18 decimal digits of precision
and the full precision of the numbers used in the calculation is not printed in the above table.
• np is the number of compounding periods per
annum
Annuities
Once the yer is determined, the final value of the fund '
can be determined by:
Iv = (1 + yer)*pv
Where:
• pv is the present value
• fv is the future value
Results were obtained using short real, long real, and
temporary real precision numbers when
Values for a frequently used type or' annuity were
calculated, using routines written in both FORTRAN
and Pascal. An annuity is a type of fund which gathers
interest at the same time the principal is changing. A
mortgage is a type of annuity in which the principal is
decreasing, whereas "the sinking fund" implemented'
hete is a type of annuity in which the principal is
increasing. In both cases, the interest is added to the
principal.
THE SINKING FUND
The "sinking fund" could be characterized by an individual retirement account (IRA). In this fund, a fixed
amount is placed in a savings fund each period. This
fund also earns a certain amount of interest per period.
The problem, then, is to calculate the final value of the
• ir is set to 10070 (0.1)
• np is set to 365 (for daily compounding)
• pv is set to $2,000,000
The results are shown in Table 1.
3-1913
AFN'()2184A
AP-143
fund (after a certain number of periods). The example
given calculates the value after 20 years of a fund in
which payments of $1000 are made each month. The
annual interest rate is given at 12% (0.12), but th'e interest is compounded daily.
The first step in solving the problem is to determine the
interest rate per month. This is done in a similar manner
to .the way the effective annual rate is calculated;
however, the number of compounding periods is set to
the number of days in a month, rather than the number
of days in a year. Once this is done, the final value of
the annuity is determined by:
jv = pm!. «1 + irp)"P - 1)
irp
• fv is the final value
pmt is the amount placed in the fund each period
• irp is the interest rate per period
•
np
is·the number'ofperiods
The short, long and temporary real precision results are
shown in Table 3.
Table 3. Annuity Calculation Results
Short
Long
Temp
Tot Contrib
Final value
Rate/period
$240,000
$240,000
$240,000
$997,103·.25
$997,048.51
$997,046.51
1.00511,10
1.005%
1.005%
The times required to calculate these results using FORTRAN 86 with both the 8087 and. the 8087 emulator are
shown in Table 4. Notice that although the most significant four digits of the interest rates per period shown
are the same, the final value using short real precision
calculations is inaccurate by $56.74 compared to the
final value using long or temporary real calculations.
Table 4. Annuity Calculation Times
Short real
Long real
Temp real
•
carrying costs from month to month are known
and fixed
•
no shortages are allowed
• lead times are known and fixed
There are three methods commonly used to determine
the restocking pattern:
1) the Fixed Economic Order Quantity (EOQ)
2) the Silver-Meal heuristic
3) the Wagner-Whitin method
Where:
•
• the demand for the given product can be predicted
8087
Emulator
2.121 ms
2.139 ms
2.106 ms
222 ms229 ms
232 ms'
Restocking Algorithms
A restocking algorithm determines when a company
should replenish its stock of raw goods which make up
its products. A restocking algorithm can be used to
determine the restocking pattern if:
Of the three, the Wagner-Whitin method is guaranteed
to provide the optional restocking pattern, whil.e the
Silver-Meal heuristic may provide a good approximation to this pattern. The fixed Economic Order Quantity
will not provide good results when the demand pattern
is highly variable. Both the Wagner-Whitin method and
the Silver-Meal heuristic are iterative methods in which
many options are evaluated before the final'restocking
.
pattern is determined.
THE FIXED ECONOMIC ORDER QUANTITY
The simple Economic Order Quantity method may be
used to seillct the number of items to be restocked at a
time if the demand is constant. This number is determined by:
EQU=V
.
2AD
vr
Where:
•
A is the set-up cost
~
D is the average demand for the period
• v is the variable demand cost per item
• r is the holding cost per item
As this method dOeS not provide for period to period
variability in demand, if this demand is variable, the
performance of the· method will obviously suffer. Its
only advantage is simplicity.
THE SILVER·MEAL HEURISTIC
The Silver-Meal heuristic will provide an approximation
to the optimal restocking pattern determined by the
Wagner-Whitin method. It has been used ratber than
the Wagner-Whitin in application where better results
were required than those supplied by the EOQ metpod,
but where the available computing resoUrces did not
allow the use of the Wagner-Whitin method. This
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AFN'()21B4A
AP-143
method begins with th~ first month to be. considered,
then calculates the total replenishment and holding costs
for this month, and a certain number of following
months. As the number of months increases, the set-up
charge per unit will decrease as it is distribu~ed over
more units. Also, however, as the number of units increases, the holding costs will increase. At a certain
point, the holding costs will begin to increase at a
greater rate than the set-up cost per unit falls. At this
point, a "local minimum" of the replenishment cost
function will haye been realized. The h~uristic stops
here, and begins the process again witli the follpwing
month until all the months of the period have been considered. This method may not provide the optimal solution, since it provides only a local minimum, rather than
a global minimum. The cost function is not guaranteed
to continue to· rise once it has begun to rise. This means
. that the restocking cost may actually fall to a lower level
after an initial rise. This method requires much fewer
cost calculations than the Wagner-Whitin method,
however.
THE WAGNER·WHITIN METHOD
The Wagner-Whitin method is the most computationally
intensive method to be discussed. It also is guaranteed
to produce the optimal results. It is an application of
"dynamIc programmi~:" It starts with the last month
of the period, determining in inverse order the optimill
replenishment pattern for the given month'if the inven. tory is assumed zero at the start of the month. It does
this by calculating the.- replenishment cost for the given
month and a number of subsequen't months along with
the holding costs for the stock replenished in the given
month but carried over. The replenishment cost is the
sum of the set-up charges and the per unit cost times the
number of units acquired. The holding cost is the
number of units held but not consumed in a given
month. The total stocking costs for this option clPl then
be determined by adding the replenislUnent cost, the
holding cost and the optimal restocking cost for the
month following the last one restocked in this iteration
(since we have started from the last month of the period,
the optimal restocking cost has already been determined
for all months following the 'month being considered).
The optimal restocking cost for the last month of the
period is the restocking cost for that month alone. For
example, if we are trying to determine the optimal
restocking pattern from January tbfough DeCember of
year, the determination of the optimal restocking pattern for Nne Ulight begin like this:
a
1)
Determining restockink cost (startup cost, per part
cost, etc.) for June alone.
1>. ~i~n"the holding costs (if June 8.I~ne is being
reslock~,the halding cost will be zero).
, ~
I
3-200
3)
Determine the total cost of ~s OP'tioll. This will be
the restocking cost deteflpined in (1) IiPded to the
hplding costs determined, in (2) adsied to the optimal restocking cost from zero initial inVentory
determined previously (using this algorithm) for
July.
'
4)
Loop bapk to (1). However this time, restock for
June and July, ~lculate the holding cost for the
July stock, and ,use the optimal, rest~cking cost
from zero initial ,inventory for August.
This will continue until starting with June, requirements
for the balance of the year are being restocked. As the
algorithm continues, the cost of each new restocking
period (that month and the number of months following
it being restocked) for a particular month is compared
with a previously determined minimum cost. If it is less,
a new minimum cost has been deterinined, and this
restocking pattern will replace the Qld one as the optimal
restocking pattern for the month. As should be apparent, a "horizon" in which the stock will be known to
go to zero must be determined, in order for this
algorithm to be used. While this may at first seem
unrealistic, one can see that in any month where the demand for the product is relatively high, the stock will be
allowed to go to zero, as the holding cost to that month
will surpass the benefit _in the, restocking cost· if the requirements were restocked in the previous month.
OVERALL PERFORMANCE CONSIDERATIONS
Generally, the better an algorithm is in determining an
objective function, the greater the computer performance required to execute the algorithm. This is true here,
with the,most nunieiic intensive solution guaranteed to
realize the optimal solution to the problem, whereas the
sinipler solutions will' only provide approximations to
this solution. A more complete 'explanation of 'these
three methods can be found in Peterson 'and Silver2. '
EXAMPLE RESTOCKING PROBLEM
'
Routines were written in Pascal to show possible implementations of the Wagner-Whitin and Silver-Meal
heuristic. The EOQ method's results were solved by
hand and programmable calculator. The following
example was used to demonstrate the results of these
methods in solving a gemial stock management
problem:
.
A company manufactures video games'in
which a ROM programmed microcomputer
2Peterson, Rein, -and Edward A. Silver, ~ision Systems For
Inventory Management, And Prpduction Planning. 10hn
Wiley & Sons, New York,1279, PP. 308-3~1.
AFN.Q2184A
AP·143
This leads to an EOQ of 7418.
is used. The manufacturer from which the
company buys this microcomputer has an initial ROM set-up charge of $3000, with the
cost per part varying from $20 in quantities
of less than 500, $17.50 in quantities from
500 to 5000, and $15 in larger quantities. The
holding cost is determined to be $0.40 per
part. The company barely missed the
Christmas rush with its introduction, but has
determined that the monthly demand for the
next two years will be:
Month
January
February
March
April
May
June
Demand
500
1500
2500
2000
2000
1000
Month
The results obtained from the Wagner-Whitin method,
the Silver-Meal heuristic and the EOQ are shown in
Table 5. The performance difference between the
methods is apparent. Although using the Silver-Meal·
heuristic would save the business $12,949 over using the
EOQ method, using the Wagner-Whitin method would
save the business almost $25,000 over using the EOQ
(surely below the cost of a small business computer!).
The effect on the performance of the Silver-Meal
heuristic of choosing a local minimum rather than a
global minimum can be seen especially in the first few
months in which it replenishes stock 5 times vs. 3 times
for the Wagner-Whitin method. It should also be noted
that the execution time of the Silver-Meal heuristic using
the emulator is stilI greater than the execution time of
the Wagner-Whitin method when the 8087 is used (and
the execution time of the EOQ on the hand calculator
was much greater than the execution time of either of
the two iAPX 86/20 programs!). These results are also
interesting when one realizes that until now the
Economic Order Quantity method has been the most
commonly used method of scheduling stocking intervals.
Demand
July
August
September
October
November
December
3500 .
2500
5000
7500
9500
10000
How should the company restock the
microcomputers?
The first problem that must be solved (when using the
Wagner-Whitin method) is the horizon to which the
stock will be replenished. The criterion to be used is that
the final month should be a month in which the demand
in the subsequent month is relatively high. Choosing
December as the final month would not produce the
best results, as the requirements for January are low.
Looking at the demand function, it can be seen that the
requirements for September are relatively high, so
August would be a good choice as the horizon month. It
is assumed that the demand for the second year will be
similar to the demand predicted for the first year. This
allows extending the period of calculation beyond the
first year up to the chosen horizon month. Given the
total demand function, the part cost, the holding cost,
and the startup cost, the problem may be plugged into
the Wagner-Whitin, Silver-Meal and Economic Order
Quantity methods, and the results calculated.
Linear Programming
Linear programming methods are very powerful ways
of finding the optimal solution to operations problems.
For example, if a number of different products can be
made from a combination of limited resources as expressed by a set of equations, a linear program can be
set up to determine the optimal number of each end
product to make in order that a certain objective function is maximized. This objective function can be practically anything if it is a linear function-for example,
insuring that profit is maximized, that the use of a certain facility is maximize
4Stephen P. Bradley, Hax, Arnoldo C., and Magnanti,.
Thomas L., Applied Mathematical Programming, AddisonWesley, Reading, Massachusetts, 1977.
The problem was set up into the input tableau. The
objective function is:
y= .85*XI + .95*X2 +1.1*X3 + 1.25*X4
'IMSL, Inc.
3-203
AFN'()2184A
AP-143
Table 6. Example Problem Input Tableau
2X, +
X, +
X, +
2 X2 +
X2 +
X2
4X3 +
2X3 +
4X3
2.25 X, + 2.25 X2 + 1.25 X3
X, +
, X2
X3
12X, +
12X2
.5 X2 + .65 X.
.15 X, + .15 X2 + ,5 X3
,25 X, + .45 X2 + ,25 X3
4X.
2 X.
4 X.
+
+ 1.25 X.
+
X4
+
+
.5 X •
.45 X4
= 1000 (eggs)
600 (sugar)
200 (b. sugar)
700 (b. choc),
600 (flour)
150 (b, soda)
150 (b. powder)
1500 (c, chips)
125 (walnuts)
560 (oven time)
750 (mix time)
Where the variable Xl is the number of batches of
chocolate chip cookies without nuts, X2 is the number
of batches of chocolate chip cookies wjth nuts, X3 is the
, number of batches of brownies without nuts, and X4 is
, the number of batches of brownies with nuts. The input
,tableau is shown in Table 6. These w,ere put into the
proper input matricies of the ZX3LP program, and the
following results were generated:
profit
, batches
batches
batches
batches
of choc chips wlo
of choc
real ir,pv,fv,pmt,irp
real*8 tvd,irpd
tempreal fvt,irpt
integer*2 cwv
integer np
6
7
·i r = .12
pmt = 11190.
1
.
SOURCE TEXT: :F6:SMCT.PAS
(* This is going to try to find the optimal replacement cost
* for a rather variable demand product OVer 20 months, when
* the demand is known, an example could be a video game, using
* a single chip ROM programmed microcomputer with an initial set
* up charge of $3000.00, demand varies a lot with peak in october
* and november(for Christmas), droops in may(vacations), etc.
* The cost per part varies from $20.00 per part up to 500,
* $17.50 per part from 500 to 5000, and $15.00 above 5,000.
* The Sliver-Meal heuristic is going to be used.
*)
module silver meal,
public timers;
function rtimer:integer,
procedure stimer,
program silver meal(input,output) ,
const
I
"months = 20,
monthspl = 21,
setupcost = 3000.0;
holdcost = 0.4;
real large = 1.OelO;
reallargei = 32000;
var
repl:
(* first time stock goes to 0 for a given month *)
array[l .. months] of integer;
tomake,
(* the number of boxes to make in a month *)
require:
(* number of boxes required in a given month *)
array[l .. monthspl] of real;
trcut,
holdcos'tv:
(* holding costs *)
array[l .. months] of real.
cost,
(* calculated cost in a given situation *)
costl,
(* production cost *)
cost2,
(* holding cost *)
totalcost,
(* the total cost of it all *)
lastcost,
(* used in determining the total cost *)
totalholdcost:
(* the total hold cost *)
real.
(* counters *)
i, j, k:
integer;
(* accumulated number of boxes in a batch *)
totcnt,
(* number of boxed holding *)
holdcnt:
real.
count:
(* the 10 ms count *)
integer.
begin
require[l] := 500.
require[2] := 1500.
require[3] := 2500.
require[4] := 2000,
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AFN{)2184A
AP-143
SOURCE TEXT: :F6:SMCT.PAS
require[5] := 2000;
require[6] := 1000;
require[7] := 3500;
'require[8] := 2500;
require[9] := 5000;
require[lO] := 7500;
require[ll] := 9500;
require[12] := 10000;
require[13] := 500;
require[14] := 1500;
require[15] := 2500;
require[16] := 2000;
require[17] := 2000;
require[18] := 1000;
require[19] := 3500;
require[20] := 2500; (* stop here, because the next month is much
higher can assume will restock then *)
require[monthspl] := reallargei;
(* start the timer *)
stimer;
i := 1;
while i <= months do begin
trcut[i] := reallarge;
totcnt := 0;
(* i is the month working on *)
j := i;
while j <= monthspl do begin
totcnt := totcnt + require[j];
if totcnt < 500 then costl := 20.0 * totcnt
else if totcnt < 5000 then costl := 17.5 * totcnt
else costl := 15.0 * totcnt;
cost2 := 0.0;
holdcnt := totcnt;
for k := i to j - 1 do begin
holdcnt := holdcnt - require[k];
cost2 := cost2 + holdcnt * holdcost;
end;
cost := (setupcost + cost2 + costl)/(j - i + 1);
if cost < trcut[i] then begin
trcut[i] := cost;
tomake[i] := totcnt;
holdcostv[i] := cost2;
end
else_begin
repl[i] := j;
i := j;
j := monthspl;
end;
j
:= j
... I;
end;
end;
count := rtimer;
j := I;
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AP-143
SERIES-III Pascal-86, Vl.l
SOURCE TEXT: :F6:SMCT.PAS
writeln('month res~ock# optimal cost per period');
total cost := 0;
for i := 1 to months do begin
if i = j then begin
write(i:5,'
',tomake[i]:6,'
',trcut[i]:10:2);
writeln(' * restocking now' );
j : = repl[ j] ;
lastcost := trcut[i];
tota1cost := totalcost + lastcost;
end
else begin
total cost := totalcost + lastcost;
writeln(i:5);
end;
end;
i := 1;
j := 0;
totalholdcost := 0.0;
while i <= months do begin
totalholdcost := totalholdcost + holdcostv[i];
j
:= j
i
:=
+
1;
repl[i];
end;
write1n('the total hold cost is' ,totalholdcost:12:2);
writeln('stock gets replenished' ,j:4,' times');
writeln('replenishment cost is',j*setupcost:12:2);
writeln('the total cost thingy is' ,totalcost);
writeln('the 10 ms count is,' ,count);
end.
Summary Information:
PROCEDURE
SILVER MEAL
OFFSET
0108H
Total
CODE SIZE
05F7H 15270
DATA SIZE
OlACH
428D
06FFH
OlACH
17910
428D
STACK SIZE
OOOEH
14D
0042H
660
135 Lines Read.
o Errors Detected.
41% Utilization of Memory.
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SERIES-III Pascal-86, Vl.l
Source File: :F6:WAGCT.PAS
Object File: :F6:WAGCT.OBJ
Controls Specified: .
SOURCE TEXT: :F6:WAGCT.PAS
(* This is going to try to find the optimal replacement cost
* for a rather variable demand product over 20 months, when
* the demand is known, an example could be a video game, using
* a single chip ROM programmed microcomputer with an initial set
* up charge of $3000.00, demand varies a lot with peak in october
* and november(for Christmas), droops in may(vacations), etc.
* The cost per part varies from $20.00 per part up to 500,
* $17.50 per part from 500 to 5000, and $15.00 above 5,000.
*)
module wag with:
public timers:
function rtimer:integer:
procedure stimer:
program wag with(input,outpUt):
const
months = 20:
monthspl = 21:
(* mask set up charge *)
setupcost = 3000.00:
(* cost per part of maintaining inventory*)
holdcost = 0.4:
real large
1.Oe9:
var
require,
(* number of chips required in a given month *)
tomake:
(* the number of chips to make in a month *)
array[l •• mortths] of real:
repl:
(* first time stock goes to 0 for a given month *)
array[l •• months] of integer:
optwz:
(* optimum cost for a given month with zero stock
to start with *)
array[l •. monthspl] of real:
holdcostv:
(* holding costs *)
array[l •• months] of real:
cost,
(* calculated cost in a given situation *)
costl,
(* production cost *)
cost2,
(* holding cost *)
totalcost,
(* the total cost of it all *)
totalholdcost: (* the total hold cost *)
real:
i,j,k:
(* counters *)
integer:
(* accumulated number of chips in a batch *)
totcnt,
(* number of boxed holding *)
holdcnt:
real:
(* 10 ms count *)
count:
integer:
begin
optwz[monthspl] := 0:
require[l] := 500:
require[2] := 1500
require[3] := 2500
require[4] := 2000
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AFN.()2184A
AP·143
SERIES-III Pascal-86, VI.I
SOURCE TEXT: :F6:WAGCT.PAS
require[5] := 2000;
require[6] := 1000;
require[7] := 3500;
require[8] := 2500;
require[9] := 5000;
require[IO] := 7500;
require[ll] := 9500;
require[12] := 10000;
require[13] := 500;
require[14] := 1500;
require[15] := 2500;
require[16] := 2000;
require[17] := 2000;
require[18] := 1000;
require[19] := 3500;
require[20] := 2500;
(* stop here, because the next month is much
higher can assume' will restock then *)
stimer~
for i := months downto 1 do begin
(* i is the month working on *)
optwz[i] := reallarge;
totcnt := 0;
for j := i to months do begin
(*
is the option working on *)
totcnt := totcnt + requirce[j];
costl := setupcost+optwz[j+l];
if totcnt <= 500 then costI := costl + 20.0*totcnt
else if totcnt <= 5000 then costl := costl + I7.5*totcnt
else costl := costI + l5.0*totcnt;
cost2 := 0.0;
holdcnt := totcnt;
for k := ito j - 1 do begin
holdcnt :~ holdcnt - require[k];
cost2 := cost2 + holdcnt * holdcost;
end;
cost := costl + cost2;
if cost < optwz[i] then begin
optwz[i] := cost;
repl[i] := j + 1;
tomake[i] := totcnt;
hold,costv[i] := cost2;
end;
end;
end;
count := rtimer;
j
:= 1;
writeln( 'month restock# optimal, cost' );
for i := 1 to months do begin
write(i:5,'
',tomake[i]:6,'
',optwz[i]:10:2);
if i = j then begin
writeln(' * restocking now');
j : = rep 1 [ j] ;
end
else writeln;
end;
3-214
AFN-0218~A
Ap·143
SERIES-III Pascal-86, Vl.l
SOURCE TEXT, ,F6,WAGCT.PAS
i := 1:
j
0:
totalholdcost ,= 0.0:
while i <- months do begin
totalholdcost ,= totalholdcost + holdcostv[i]:
,=
j
i
,=
,=
j
+ 1:
repl[i]:
end:
writeln('the total hold cost is',totalholdcost,12,2):
writeln('stock gets replenished',j,4,' times'):
writeln('repleni~hment cost is' ,J*setupcost,12,2):
writeln('the 10 ms count is ',count):
end.
Summary Information,
PROCEDURE
WAG WITH
OFFSET
00E5H
Total
CODE SIZE
0576H l39SD
DATA SIZE
OlASH
424D
065BH
OlASH
1627D
424D
STACK SIZE
OOOEH
14D
0042H
66D
119 Lines Read.
o Errors Detected.
41% Utilization of Memory.
3-215
AFN-02184A
AP-143
FORTRAN-86 COMPILER
:F1:COOKIE.FOR
SERIES-III FORTRAN-86 COMPILER X023
COMPILER INVOKEO BY: FORT86.86 :F1:COOKIE.FOR
1
2
3
c
c this routine will solve a linear problem using the IMSL fortran
c
library. the IMSL routine used is "zx31p" which solves the problem
c
using the revised simplex method.
c
integer ia,n,m1,m2,iw(37),ier
rea1*8 a(13,4),b(13),c(4),rw(206),pso1(11),dso1(13),s
integer*4 rtimer,count
4
*
*
*
5
6
data .a/2. ,I. ,I. ,0.,2.25,1. ,0. ,12. ,0., .15, .25,0. ,0. ,
2.,1.,1.,0.,2.25,1.,0.,12.,.5,.15,.45,0.,0.,
4.,2.,0.,4.,1.25,0.,1.,0.,0.,.5,.25,0.,0.,
4.,2., O. ,4. ,1.25, O. ,1.,0., .65, .5, .45,0., O. /
data b/l000.,600.,200.,700.,600.,150.,150.,1500.,125.,560.,750.,0.,0./
data c/.85,.95,l.10,l.25/
c
c
c
c
c
c
n is the number of variables"
m1 is the number of inequality constraints
m2 is the number of equality constraints
ia is the declared number of columns of a
7
8
9
ml = 11
m2 = 0
10
ia = 13
11
print *,'the input tableau:'
do 100 i=l,ia-2
write(6,800)a(i,l),a(i,2),a(i,3),a(i,4),b(i)
format(4f10.4,' <= ',f10.4)
continue
n =
12
13
14
15
800
100
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
4
call stimer
call zx31p(a,ia,b,c,n,m1,m2,s,psol,dso1,rw,iw,ier)
count = rtimer () .
200
pnint *,'ier = 'tier
print *,'the final value of the objective function(profit!) is:',s
print *,'batches of chocolate chip w/o walnuts: ',pso1(1)
print *,'batches of chocolate chip with walnuts: ',psol(2)
'print *,'batches of brownies without walnuts: ',pso1(3)
print *,'batches of brownies with walnuts: ',pso1(4)
print *, 'the dual solutions follOW:'
do 200 i=l,ia-2
print *,'var',i,' = ',dsol(i)
continue
print *,'the calculation time here (in seconds .•• ) is: ',count/100.
stop
end
3-216
AFN.(J2184A
inter
APPLICATION
NOTE
Ap·144
October 1983
© INTEL CORPORATION,
1~
Order Number 210384-001
3-:m .
)
,",
AP- 144 '.'
microprocessor allowing the processor to perform other
work in parallel. In addition, since the size of the
memory used in a bit-mapped controller is constrained
(one could hardly have unlimited memory for the
refresh map), only integer math is required. This
graphics package is a much higher level type of routine,
where the inputs are three-dimensional' line drawing
commands (which could be fed into a bit map con-'
troller).
INTRODUCTION
As the performance of microcompute~s ha~ improved,
these machines have been used in many applications.
With the introduction of 16-bit microprocessors (along
with the associated CPU enhancements, especially the
integer multiply instruction) the operations required to
manipulate graphic representations of threedimensional objects were made easier. Only integer
values could be used to define figures, however, because
only integer multiplies were supported in hardware.
While software floating point routines existed, the speed
at which a general purpose microprocessor could ex-ecute even the simplest floating point operation precluded the use of these routines because of the number of
floating point operations which must be performed to
manipulate all but the simplest of objects.
The three-dimensional graphics package implemented
in this note allows for the entry of three-dimensional
figures, the manipulation of these figures, the setting of
the viewer's location, the size of the picture to be seen,
and the position of the picture on the graphics output
device. Along the way, it performs perspective transformations, window clipping and projection. All figures
are defined using floating point numbers. Thus, any
figure may be defined "real size" without pre-scaling.
This means that the size of the figure defined within the
package may be the actual size of the object, i.e. the size
of the object is not arbitrarily limited by the machine,
whether the object be a sub-nuclear particle, or a
cellestial body.
The lack of high performance floating point math or the
restriction of using only integer representations seve~ely
limits the types and sizes of objects that can be defined.
Imagine limiting everything in .the universe to be less
than 32,000 millimeters long, high, or wide! This limitation could severely impact any system that is used to
model real world objects. An example of such an application is a Computer Aided Design (CAD) system. If
real or floating poinenumbers are used, however, practically any object can be defined (after all, there are only
9,397,728,000,000,000,000 m.iIlimeters in a li~ht year(!),
well within the range of floating point numbers). With
the introduction of the iAPX 86120, the Performance
required to execute the requisite operations 'on floating
· point representations 'of three-dimensional figures has
finally been achieved in a microprocessor solution, at a
microprocessor price.
iAPX 86/20 HARDWARE OVERVIEW
The iAPX 86/20 is a 16-bit microprocessor based on the
Intel 8086 CPU. The 8086 CPU features eight internal
general purpose 16-bit registers, memory segmentation,
and many other features allowing for compact, efficient
.code generation from high-level language compilers.
When augmented with the 8087, it becomes a vehicle for
high-speed numerics processing. The 8087 adds eight
80-bit internal floating point registers, and a floating
point arithmetic logic unit (ALU) which can speed
floating point. operations by up to 100 times over other
software floating .point simulators or emulators.
The iAPX 86120 features the Intel 8086 with the 8087
numerics co-processor. This combination allows· for
high performance, high precision numeric operations.
This performanined with code generated from the other compiler,
from the Intei 8086/87188 macro assembler, or the Intel PLIM compiler. In addition, these compilers produce in-line code for the ,8087 when numeric operations
are required. By producing in-line code rather than calls
to floating point routines, the software overhead of an
unnecessary procedure call and return is eliminated.
INT
8259A
PIC
IRn
-
I
INTR
, - ClK
I
,- Ra/GTl
J
aso
aSl
TEST
aso
'--
8284A
CLOCK
GENERATOR
~
t
t. t
ClK
~
\r-
8086/8088
CPU
aSl
A
K
~
1\
SYSTEM BUS
~
K= .'"
8087
ClK
I
:::>
III
NDP
(S
g
INT
Ra/GTl
I
I
I
-=-t-
I
I
I
L
IV"
BUSY
RaJGTO
8086
FAMilY
BUS
INTERFACE
COMPONENTS
-
Ra/GT
8089
lOP
~ClK
I ,1-
r'r-- '
I "
I
I-
I
-
-
..J'
Figure 1. Example 86/20 System
AFNe plotted, the viewpoint of the
viewer must be known. This information provides the
location of the viewer in three-dimensional space, and
the direction the viewer is pointing. It is incorporated into the 4 by 4 "view" matrix. It is another rotation performed on the object in order that it is viewed from the
proper viewing angle. All points are passed through the
view matrix after they are passed through the current
matrix. What comes out of.these two transformations is
a set of points located in the proper relative positions in
three-dimensional space when the i~ is rotated,
translated, and scaled by, the operations performed on
the current matrix, and is also rotated properly by the
operations set in the view matrix.
The view matrix is set up by the viewpoint command.
This command will plac~ in the view matrix the proper
rotations in order that the image of the obiect will be
correct. The routine performing this task is the viewpn
routine.
'
"Z-clipping." Simply, it examines the Z parameter of
every point being considered and determines if it is in
front of the ·viewer. In addition, one may not wish to
display lines a great distance from the viewer. These
lines may be removed by a similar process. The only
complication of clipping is the action performed if only
part of the line is visible. In this instance, the point
where the line leaves the visible·area must be calculated.
The method used to calculate this point in this implementation is the method of "like triangles."
The Z-clipping parameters are set through the command zclip in the routine zdip. The arguments to this
command are used to determine the visible distance in
front of the viewer. The first argument sets the
minimum distance in front of the viewer before any line
will be visible. Legal values for this parameter are
anything great\ll' than zero. The second argument sets '.
the far distance beyond which no lines will be visible ..
Any value larger than the first argument may be. used
for this parameter. The clipping itself is performed in
the routine zdipp.
Z·CLlPPING
All points' passed through the current and view matrices
are located at· their proper' locations in threedimensioruiJ. space. However, only a portion of this
space is visible to the viewer. Specifically, objects
behind the viewer will not be visible. Every point of an
object has been mappC:d to the viewer's space, however,
including those behind the viewer. These "invisi~le"
points are removed by an operation ca1lell
3-229
AFN.()2185A
AP-144
PROJECTION
Projection maps the three-dimensional points previously encountered and projects them onto a twodimensional plane. Only single-point perspective is currently supported in the pac/<:age. Here, the projection is
performed by using the Z parameter to modify the X
and Y parameters. As the points get more distant, their
deviation from the center of the picture should get
smaller, if the X and Y parameters remain constant.
Most people are aware of this effect. For example, if
you look down a set of railroad tracks, the rails seem to
converge, even though the distance between the rails is
constant (see Figure 17). Two or three-point perspective
would be easy to implement; all one must do is generate ,
the projected X and Y parameters by using the nonprojected X and Y parameters in addition to using the Z
parameter.
This projection is performed in the graphic;s package by
multiplying the 1 by 4 point location vector by a 4 by 4
"projection" matrix. This matrix is simply the identity
matrix except the perspective value is placed in location
(3,4) of the matrix.
Figure 17. Two Rails, Vanishing into the Distance
This value is calculated from the viewpoint parameters.
After the matrix multiply, the only element modified in
the 1 by 4 point definition vector is the last one (the one
which is supposed to have the value of one). After the
multiplication, this location will contain the number
representing the modification which must be performed
on the X and Y parameters of the vector to exhibit the
projection. When this vector is "normalized," the point
will have been projected using the rules of single-point
perspective. This normalization is performed by
dividing every element in the vector by the last element
of the vector. Thus, the Z element of the original vector
has modified the X and Y elements. If two or threepoint perspective is desired, one, must only place
perspective values in locations (1,4) and (2,4) of the projection matrix; all subsequent processing will be iden- ,
tical. The routines performing these operations are:
vlewpn (sets up vanishing point for perspective), projct
(sets up the projection 'matrix, and performs the
perspective multiplication), and norm (normalizes the
vector).
x-v CLIPPING
Once the data is projected onto a two-dimensional
plane, X-V clipping must be performed. This operation
could also be performed on the three-dimensional data,
but by deferring it until after the data have been projected, the calculations required are simpler. This is not
true for Z-clipping, since once the, data are projected
onto a plane, the Z parameter is no longer in its original
form.
j
X-Y clipping is performed by comparing X and Y
parameters with the window values set up by the window command. This comparison is a bit more complicated than the comparison required by Z clipping,
however, as tw'o clipping parameters are involved.
There are nine possible regions in which each endpoint
of a line may reside. For example, some of these regions
are: within the X and Y window regions, less than the X
window region but within the Y region, less than the X
region and less than the Y region, etc. If one or both of
the endpoints of the line are within the visible region,
then at least part of the line will be visible. Also, even if
neither of the endpoints of the line is in the visible
region, part of the line may still be visible. One must
therefore determine whether any part of this line would
be visible. A simple wa,y of performing the task is to
assign a bit of a word for each of less than and greater
than the X Ij,nd Y window limits. This requires four bits.
The value of the X and Y parameters are then each compared with the window limits. If the value exceeds the
limit of the window, the corresponding bit of this point
descriptor is set. After this "code" has been determined
for both of the points, the codes 'for two endpoints are
bit-wise ANDed together (an extension to FORTRAN ,
'77 available in FORTRAN 86 allows this operation). If
the result of this ANDing is zero, then part of the line
would be visible. If, however, it is not zero, then the entire line lies outside the visible area. If only part of the
line is visible, th.en the point where it leaves the visible
area Iriust be calculated. The point where the line leaves
the viewing area is calculated using the same "like
triangle" method used when Z-clipping is performed.
3-230
AFN.()2185A
Af-144
The routines performing these operations are wto\'p
(calls the xycllp routine with the proper parameters),
xyclip (performs the actual clipping), code (returns the
binary code for the point position in relation to the window), and ppush (calculates the point at which line
leaves the visible area).
PERFORMANCE MEASUREMENTS
The above routines were compiled using the Intel FORTRAN 86 compiler and exeucted on an Intellec® Series
III development system. The 8086 hardware consists of
an Intel iSBC® 86/12 board with the 8087 in the
iSBC" 337 card. The iAPX 86120 (the 8086 with the
8087) operate with a clock frequency of 5 MHz. The on
board memory (64K DRAM) inserts between one and
three wait states per memory fetch. In addition, owing
to the size of the memory arrays, the program size, and
the memory reguirements of the Series III, off board
memory was required to run the program.
WINDOW TO VIEWPORT TRANSFORMATION
Finally, after the points have been processed through all
of the above, comes their day of glory. Because the lines
have been clipped, they are constrained to be within the
given window. Remember, however, that the values for
this window are in "real world" units. These sizes could
be measured in inches or miles. These are not generally
suitable for plotting on a graphics output device. In
order for the "window" to be displayed on the graphics
output device, one more transformation must be performed: the window to viewport transformation. A
viewport represents a physical location and size on the
graphics output device. The viewport command sets up
the appropriate parameters for this transformation. It
requires four arguments, which allow the viewport to be
moved around the graphics display surface, and allow
the size of the viewport to be set. Notice that the
viewport and the window are not constrained to the
same aspect ratios, that is, the ratios between the vertical sizes and ,the horizontal sizes of the window and
viewport need not be the same. If these' ratios are not the
same, the figures will be distorted. Performing this
transformation is simply a matter of scaling the windowed values to fill the viewport. The code performing
this transformation is contai~ed within the wtovp
routine.
The times shown in the table do not show the plotting
time; only the time to generate the output that would be
sent to the plotter is given. This is because the physical
speed limitation of the plotter used would not allow the
iAPX 86120 system to produce the plotting commands
at its maximum computational speed. The plotter required approximately half an hour to 45 minutes to actually draw the second demonstration picture.
For each line plotted, five 1 by 4 times 4 by 4 matrix
multiplies must be performed along with a non-trivial
amount of other floating point operations, such as
divides and compares. For example, when clipping is
performed, the line endpoint values must be compared
to the clipping parameters. If only part of the line is visible, then the point the line leaves the visible area must be
calculated. This requires twelve additional floating
point operations. Another example is in the window to
viewport transformation. For each line drawn, four
floating point multiplies, four floating point divides,
and four floating point adds must be performed.
In addition, whenever the rotation, scale, translation or
viewpoint is changed, 4 by 4 matrix multiplies must be
performed. In addition, various trigonometric routines,
such as sines and cosines. must be performed to set up'
the rotation parameters into the matrix.,
PLOTTER INTERFACE
This graphics package was written to interface to a
Hewlett-Packard 7225A flat bed plotter. Communications were performed through an RS232 serial link at
600 baud. Physically, this is done using the 8251 serial
controller on the iSBC® 86/12 board inside the Intellec@
Series III. The plotter has a smart interface. The commands it accepts are in ASCII, and are on the level of
"lower the pen," and "draw a line from the current pen
position to another pen position." The routines performing these operations are plot (determines the
characters needing to be sent to the plotter), ponum
(converts a floating point number to an ASCII representation of the integer value of the truncated floating
point number), putout (handles the interface to the 8251
serial controller chip) and plots (initializes the baud rate
generator and 8251 serial controller chip on the iSBd>
86/12 board).
The performance measurements are given in Table 1.
Table 1. Performance Measurements
number of points in picture
number of points actually plotted
execution time of the 86/2O(sec)
execution time of the 86 with 87
emulator(sec)
exection time of PDPII/45(sec)2
Picture Number
Two
One
9131
117
117
2.84
144.77
6114
188
9801
1.7
120
2A PDPI1I45 mini-computer with 256K MOS RAM, and a
FP11-B floating point unit running the UNIX operating
system during a period of light load. The program was compiled using the UNIX F77 FORTRAN compiler.
3-231
AFN.()2185A
AP·144,
Figure 18. Demonstration Picture 1
The results show that the performance of the iAPX
86/20 is close to the performance of the mini-computer.
The figures drawn are shown in Figure 17 for Picture 1
and Figure 18 for Picture 2. The graphics commands requiredto generate Picture 1 are given in Appendix B.
Picture 2 shows three views of a single shuttle. (Hint:
you are looking out the window of one of the shuttles I)
The shuttle is' defined oll1y once in the input data.
Another point to notice is that each shuttle is a conglomeration of parts. For example, the shuttle wing is
dermed only once in input data. The complete shuttle
contains two views of this same ~, translated and
rotated to attach to the appropriate location on the
fuselage of the shuttle itself. The engine nozzles take
this same approach bit further : The complete nozzle is
defined only once, and is atfached in three places on
each shuttle. In addition, each nozzle is made up of
replications of the same circle scaled and translated
through space. Each circle is, in turn, composed of four
views of one quarter-circle, each rotated a proper
amount to form one complete circle.
'
a
AFN-02185A
('
AP-144
Figure 19. Demonstration Picture 2
CONCLUSIONS
Computer Aided Design (CAD) or Computer Aided
Manufacturing (CAM) systems. In addition, the
availability of a full ANSI 77 standard FORTRAN compiler (FORTRAN 86) for the iAPX 86120 enhances the
production or transportation of existing software to the
machine. This combination of high performance hardware with high performance software allows the iAPX
86120 to fill applications never before filled by a
microprocessor.
The routines demonstrated in this note show that the
types of operations required to manipulate and display a
three-dimensional figure on a two-dimensional surface
are far from trivial, involving very many floating point
operations. With the introduction of the iAPX 86/20,
the floating point performance required by this type of
application is finally within the performance limits of
microcomputers selling for a fraction of the cost of the
previously required mini- or maxi-computers. Examples
of systems in which this performance is required are
3-233
AFN'()2185A
AP-144
APPENDIX A
Contents'
PAGE'
"
Main Routine ,............................. A· 3
get ................ : ....................... A· 4'
proe ..............::.:..................... A· 4
Ident ..............•. .':'. . . ........ ...... . .. A· 5
de#.n ......... , ............................ A· 6
printd ........ : . '.' . • . . . . . . . . . . . . . . . . . . . . . .. A· 7'
eal/lt •..................................... A· 7
prlntm .................................... A· 7
pline ...................................... A- 8
pplot ..........................•.......... A- 9
push ................................. '..... A· 9
pop ............................. " .....•.. A- 9
rotate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-10
transl ..................................... A-10
pseale ...•................................ A-11
~Indow ................................... A-11
vlewpr .................................... A-11
vlewpn .................................... A·12
zelip ...................................... A-13
zelipp . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-13.
proJet ...................................... A·14
norm ...........,..... . . . . . .... ... . .... .... A-14
wtovp ..................................... A·15
!.5 7.<; 2
'ident' /
'vieWpoint' 10 0 0 0
'cube' 0 0 0 2 2 ? /
'vie\'Iport I 7.5 7.5 2
'rotate' 30 3() 30 I
, cube I 0 0 0 2 '1 2 /
"
I en(lcie-f'
'call' 1
'end' I
:1
/
"
0 0
2
/
2
/
0 0
'2
/
/
/
I
I
3-255
,
'f,
on a single chip (see Figure 1), system construction is
simplified since many of the peripheral interfaces are integrated 'onto the device.
'
1. INTRODUCTION
As state of the art technology has increased the number
of transistors possible on a single integrated circuit,
these devices have attained new, higher levels of both
performance and functionality. Riding this crest are the
Intel 80186 and 80286 microprocessors. While the
80286 has added memory protection and management
to the basic 8086 architecture, the 80186 has integrated
six separate functional blocks into a single device.
The 80186 family actually consists oftwo processors: the
80186 and 80188. The only difference between the two
processors is that the 80186 maintains a 16-bit external
data bus while the 80188 has an 8-bit external data bus.
Internally, they both implement the same processor with
the same integrated peripheral components. ThUS, except where noted, a1180186 information in this note also
applies to the 80188. The implications of having an ,8-bit
external data bus on the 80188 are explicitly noted in appendix I. Any parametric values included in this note are
taken from the iAPX 186 Advance Information data
sheet, and pertain to 8Mhz devices.
The purpose of this note is to explain, through example,
the u.e of the 80186 with various peripheral and memory diWices. Because the 80186 integrates a DMA unit,
timer unit, interrupt controller unit, bus controller unit
and chip select and ready generation unit with the CPU
INT3IiNm
li~~LKOUT
I I
X,
X.
INT2JIIiITllI
T
'ExEcUT.oN'UN~I
I
I
I
I
1.·BIT
AW
CLOCK
GENERATOR
1.·BIT
GENERAL
PURPOSE
REGISTERS
n
t
J
SROY' AROY' -
'IUT' -
HOLD,tlLOA
......
..
NTI
INj"'
l
l
1
t
I
I
n
INTERNAL BUS
t
1.·BIT
COUNT REGISTER
U
r-r+
PROGRAMMABLE
U
RIS:~~
,~
18-BIT
SEGMENT
REGISTERS
PROGRAMMABLE
CONTROL
REGISTERS
80BYTE
PREFETCH
QUEUE
RESET'-r-
I
l~
LOCK
DT/If
II
II-IH
l~Ate
RO
IiUS7
ADOAD1S
ORQO'
ORQl
OMAUNIT
10
2O·BIT
SOURCE POINTERS
CHIP-SELECT
UNIT
BUS INTERFACE
UNIT
f
CONTROL REGISTERS
CONTROL I
REGISTERS
-1
1
PROGRAMMABLE
TIMERS
0
1
2
MAXCOUNT ~
REGISTER B :..:
MAX COUNT
REGISTER A
PROGRAMMABLE
INTERRUPT
CONTROLLER
I
I
f
TMR OUT 1 TMR OUT 0
TMR IN
TMR IN
INT1
Gr,
IJ
1
2O-BIT
DESTINATION
POINTERS
1.·BlT
TRANSFER COUNT
CONTROL
REGISTERS
kl 1 ~A2
All/S3Al91S6
LCS
V
PCS5IAl
v
Figure 1. 80188 Block Diagram
3-256·.
AFN-210973
AP·186
2.
2.1
OVERVIEW OF THE 80186
The CPU
The 80186 CPU shares a common base architecture
with the 8086, 8088 and 80286. It is completely object
code compatible with the 8086/88. This architecture
features four 16-bit general purpose registers (AX,BX,
CX,DX) which may be usedas OPerands in most arithmetic operations .in either 8 or 16 bit units. It also features four 16-bit "pointer" registers (SI,DI,BP,sP)
which may be used both in arithmetic operations and in
accessing memory based variables. Four 16-bit segment
registers (CS,DS,SS,ES) are provided allowing simple
memory partitioning to aid construction of modular programs. Finally, it has a 16-bit instruction pointer and a
16-bit status register.
Physical memory addresses are generated by the 80186
identically to the 8086. The 16-bit segment value is left
shifted 4 bits and then is added to an offset value which
is derived from combinations of the pointer registers, the
instruction pointer, and immediate values (see Figure
2). Any carry out of this addition is ignored. The result
of this addition is a 20-bit physical address which is presented to the system memory.
The 80186 has a 16-bit ALU which performs 8 or 16-bit
arithmetic and logical operations. It provides for data
movement among registers, memory and I/O ·space. In
addition, the CPU allows for high speed data transfer
from one area of memory to another using string move
instructions, and to or from an I/O port and memory using block I/O instructions. Finally, the CPU provides a
wealth of conditional branch and other control
instructions.
In the 80186, as in the 8086, instruction fetching and ill;struction execution are performed by separate units: the
bus interface unit and the execution unit, respectively.
The 80186 also has a 6-byte prefetch queue as does the
8086. The 80188 has a 4-byte prefetch queue as does the
8088. As a program is executing, opcodes are fetched
from memory by the bus interface unit and placed in this
queue. Whenever the execution unit requires ~nother instruction, it takes it out ofthe queue. Effective processor
throughput is increased by adding this queue~ since the
bus interface unit may continue to fetch instructions
while the execution unit executes a long instruction.
Then, when the CPU completes this instruction, it does
not have to wait for another instruction to be fetched
from memory.
2.2
80186 CPU Enhancements
Although the '80186 is completely object code compatible with the 8086, most of the. 8086 instructions require
fewer clock cycles to execute on the 80186 than on ~he
8086 because of hardware enhancements in the bus mterface unit and the execution unit. In addition, the
80186 provides many new instructions which simplify
assembly language programming, enhance the performance of high level language implementations, and reduce object code sizes for the 80186. These new
instructions are also included in the 80286. A complete
description of the architecture and instruction execution
of the 80186 can be found in volume I of the
iAPX86/ 186 users manual. The algorithms for the new
instructions are also given in appendix H of this note.
I·
SEGMENT VALUE
I·
I
16 BITS
-I
18 BITS
I
+
OFFSET
PHYSICAL ADDRESS
Figure 2.
=
I
I·
"I
'I
20 BITS
I
-I
Phy.lcal Address Generation In the 80186
3-257
AFN-21 0973
2.3 . DMA Unit
The 80186 includes a DMA unit which provides two
high speed DMA channels. This DMA unit will perform
transfers to or from any combination of 1/0 space and
memory space in either oyteor word units. Every DMA
cycle requires,;two to four bus cycles, one or two to fetch
the data to an internal register, and one or two to deposit
the data. This allows word data to be located on odd
boundaries, or byte data to be moved from odd locations
to even locations: This is normally difficult, since odd
data bytes are transferred on the upper 8 data bits of the
16-bit data bus, while even data bytes are transferred on
the lower 8 data bits of the data bus.
Each DMA channel maintains independent 20-bit
source and destination ppinters which are used to access
the source and destination of the data transferred. Each
of these pointers may independently address either 1/0
or memory space. After each DMA cycle, the pointers
may be independently incremented, decremented, or
maintained constant. Each DMA channel also maintains a transfer count which may be used t-o terminate a
series of DMA transfers after a pre-programmed number of transfers:
2.4
Timers
The 80186 includes a timer unit which contains 3 independent 16-bit timer/counters. Two of these timers can
be used to count external events, ,to provide waveforms"
derived from either the CPU clock or an external clock
of any duty cycle, or to interrupt the CPU after a speci- "
fied number of timer "events." The third timer counts
only CPU clocks and can be used to interrupt the CPU
after a programmable number of CPU clocks, to give a
count pulse to either or both of the other two timers after
a programmable number of CPU clocks, or to give a
DMA request pulse to the integrated DMA unit after a
programmable number of CPU clocks.
2.5 Interrupt Controller
The 80186 includes an interrupt controller. This controller arbitrates interrupt requests between all internal and
external sources. It can be directly cascaded as the master to two external 8259A interrupt controllers. In addition, it can be configu~d as a slave controller to an
, external interrupt controller to allow complete compatibility with an 80130, 80150, and theiRMX@860perating system.
2.6 Clock Generator
The 80186 includes a clock gimerator and crystal oscillator. The crystal oscillator can be used with a paTallel res"onant, fundamental moiiecrystal at 2X the desired CPU
clock speed (i.e., 16 MHz for an 8 MHz 80186), or with
an external oscillator also at 2X the CPU clock. The output of the oscillator is internally divided by two to "provide the 50% duty cycle CPU clock from which all
80186 system timing derives, The CPU clock is externally available, and all timing parameters are referenced to
this externally available signal. The clock generator also
provides ready synchronization for the processor.
2.7
Chip Select and Ready Generation Unit
The 80186 includes integrated chip select logic which
can be used to enable memory or peripheral devices. Six
output lines are used for memory addressing and seven
output lines are used for peripheral addressing.
The memory chip select lines are split into 3 groups for
separately addressing the major memory areas in a typical 8086 system: upper memory for reset ROM, lower
memory for interrUpt vectors, and mid-range memory
for program memory. The size of each of these regions is
user programmable. The starting location and ending
location of lower memory and upper memory are fixed
at OOOOOH and FFFFFH respectively; the starting location of the mid-range memory is user programmable.
Each of the seven peripheral select lines address one of
seven contiguous 128 byte blocks above a programmable
base address. This base address can be located in either
memory or 1/0 space in order that peripheral devices
may be 1/0 or memory mapped.
'
Each ofthe programmed chip select areas has associated
with it a set of programmable ready bits. These ready
bits control an integrated wait state generator. This allows a programmable number of wait states (0 to 3) to
be automatically inserted whenever an access is made to
the area of memory associated with the chip select area.
In addition, each set of ready bits includes a bit which
determines whether the external ready signals (ARDY
and SRDY) will be used, or whether they will be ignored
(i.e., the bus cycle will terminate even though a ready
has not been returned on the external pins). There are 5
total sets of ready bits which allow independent ready
generation for each of upper memory, lower memory,
mid-range memory, peripheral devices 0-3 and peripheral devices 4-6.
2.8
Integrated Peripheral Accessing
The integrated peripheral and chip select circuitry is
controlled by sets of 16-bit registers accessed using standard input, output, or memory access instructions.
These peripheral control registers are all located within
a 256 byte block which can be placed in either memory
or 1/0 space. Because they are accessed exactly as if
they were external devices, no new instruction types are
required to access and control the integrated peripheralso For more information concerning the interfacing
and accessing of the integrated 80f86 peripherals not included in this note, please consult the 80186 data sheet,
or volilme II of the iAPX86/186'users manual.
3-258
AFN-21 0973
AP-186
3.
USING THE 80186
3.1
3.1.1
I
I
I
Bus Interfacing to the 80186
~~~1
OVERVIEW
The 80186 bus structure is very similar to the 8086 bus
structure. It includes a multiplexed address/data bus,
along with various control and status lines (see Table I).
Each bus cycle requires a minimum of 4 CPU clock cycles along with any number of wait states required to accommodate the speed access limitations of external
memory or peripheral devices. The bus cycles initiated
by the 80186 CPU are identical to the bus cycles initiated by the 80186 integrated DMA unit.
In the following discussion, all timing values given are
for an 8 MHz 80186. Future speed selections of the part
may have different values for the various parameters.
Each clock cycle of the 80186 bus cycle is called a "T"
state, and are numbered sequentially T 1, T 2, T 3' Tw and
T 4. Additional idle T states (Ti ) can occur between T4
and T, when the processor requires no bus activity (instruction fetches, memory writes, I/O reads, etc.). The
ready signals control the number or wait states (Tw) inserted in each bus cycle. This number can vary from 0 to
positive infinity.
Figure 3.
I
01
I
I
I
PHASE)
(LOW
I
I
02
I
I
I
PHASE)
L
(HIGH
T-state in the 80186
The beginning of a T state is signaled by a high to low
transition of the CPU clock. Each T state is divided into
two phases, phase I (or the low phase) and phase 2 (or
the high phase) which occur during the low and high levels of the CPU clock respectively (see Figure 3). .
Different types of bus activity occur for all of the Tstates (see Figure 4). Address generation information
occurs during T 1• data generation during T 2, T 3, Tw and
T,
T,
Tn
T,
LINES
DATA
LINES
ADDRESS!
CONTROL
+ ____.;.(
p_+-__-;.___-++-_......I
t..-_ _ _ _
-r-----,.....---_
,.
SIGNALS
(RD,WR)
Figu~e
4.
Example Bus Cycle of the 80186
Table 1. 80186 Bus Signals
Function
Signal Name
ADO-AD I 5
A16/S3-AI9-S6,BHE/S7
TEST
HOLD,HLDA
ALE,RD,WR,DT /R,DEN
LOCK
SRDY,ARDY
80-S2
address / data
address/status
co-processor control
local bus arbitration
local bus control
multi-master bus
ready (wait) interface
status information
3-259
AFN-210973 '
inter
l ______________________________________________________________________
T 4' The beginning of a bus cycle is signaled by the status
lines of the processor going from a passive state (all
high) to an active state in the middle of the T-state immediately before T 1 (either a T 4 or a TJ Because information concerning an impending bus cycle occurs
during the T-state immediately before the first T-state of
the cycle itself, two different types of T 4 and T j can be
generated: one where the T state is immediately followed by a bus cycle, and one where the T state is immediatly followed by an idle T state.
During the first type of T 4 or T j , status information concerning the impending bus cycle is generated for the bus
cycle immediately to follow. This information will be
available no later than t CHSV (55ns) after the low-tohigh transition of the 80186 clock in the middle of the T
state. During the second type of T 4 or T j the status outputs remain inactive (high), since no bus cycle is to be
started. This means that the decision per the nature of a
T 4 or T j state (Le., whether it is immediately followed by
a T j or a T t ) is decided at the beginning of the T-state
immediately preceding the T 4 or T j (see Figure 5). This
has consequences for the bus latency time (see section
3.3.2 on bus latency).
3.1.2 PHYSICAL ADDRESS GENERATION
Physical addresses are generated by the 80186 during T 1
of a bus cycle. Since the a---4--- LOCK
52 ----........_-'
Figure 15. Circuit Holding Lock Active Until
Ready is Returned
The first way in which a HALT bus cycle differs from a
normal bus cycle is that since the proce~ is entering a
halted state, none of the control lines (RD or WR) will
be driven active. Address and data information will not
be driven by the processor, and no data will be returned.
The second way a HALT bus cycle differs from, a normal
bus cycle is that the SO-S2 status lines go to their passive
state (all high) during T 2 of the bus cycle, well before
they go to their passive state during a normal bus cycle.
Like a normal bus cycle, however; ALE is driven active.
Since no valid address information is, present, the information strob~d into the address latches should be ignored. This ALE pulse can be used, however, to latch the
HALT status from the SO-S2 status lines.
The processor being halted does not interfere with the
operation of any of the 80186 integrated peripheral
units. This means that if a DMA transfer is pending
while the processor is halted, the bus cycleS associated
with the DMA transfer will run. In fact, DMA latency
time will improve while the processor is halted because
the DMA unit will not be contending with the processor
for access to the 80186 bus (see section 4.4.1).
3.1.8 8288 AND 8289 INTERFACING
The 8288 and 8289 are the bus controller and multiNote that the LOCK signal does not remain active until
master bus arbitration devices used with the 8086 and
the end of the last data cycle of the locked transfer. This
8088. Because the 80186 bus is similar to the 8086 bus,
may cause problems in some systems if, for example, the
they can be directly used with the 80186. Figure 16
processor requests memory access from a dual ported , ,shows an 80186 interconnection
to these two devices.
'
RAM array and is denied immediate access (because of '
The
8288
bus
co!!!roller
generates
control signals (RD,
a DRAM refresh cycle, for example). When the procesWR, ALE, DT/R, DEN, etc.) for an 8086 maximum
sor finally is able to gain access to the RAM array, it
mode system.:.!t derives its information by decoding stamay have already dropped its LOCK signal, thus allowtus lines SO-S2 of the processor. Because the 80186 and
ing the dual port controller to give the other port ,access
the 8086, drive the same status information on these
to the RAM array instead. An example circuit which
lines, the 80186 can be directly connected to the 8288
can be used to hold LOCK active until a RDY has been
just as in an 8086 system. Using the 8288 with the 80186
received by the 80186 is shown in Figure 15.
does not prevent using the 80186 control signals directly. '
Many systems require both local bus control signals and
3.1.7 HALT TIMING
system bus control signals. In this type of system, the
, 80186 lines could be used as the local signals, with 'the
A HALT bus cycle is used to signal the World that the
3-267
AFN·21 0973
inter
AP-188'-
has acquired control of the bus, then it allows the ptocessor to drive address, data and control information onto
the system bus. The system determines when it requires
system bus resources by an address decode~ Whenever
the address ,being drive\1 coincides with the address of an
on-board resource, the system bus is not required and
thus will not be requested. The circuit shown factors the
80186 chip select lines to determine'when the system bus
should be requested, or when the 80186 request can be
~atisfied using a local resource.
'
TO MULn-MASTER BUS
ADDRESS LATCHES.
DATA BUFFEIIS
801
8288
'Slf--_-I SO-
fi
S2
ALE
DEN
DT/R
CLOCKOUT F-t--l-'" CLK
3.1.9 READY INTERFACING
HI--+!SYSB/MUi..---+
Figure 18. 80188/8288/8289 Interconnection ,
8288'lines used as the system signals. Note that in an
80186 system, the 8288 generated ALE pulse occurs later than that of the 80186 itself. In many multimaster
bus systems, the 8288 ALE pulse 'should be used to
strobe the addresses into the system bus address latches
to insure that the address hold times are met.
The 8289 bus arbiter arbitrates the use of a multi-master system bus among various devices each of which can
become the~uLinaster: This component also decodes
status lines SO-S2 of the processor directly to determine
when the system bus is required. When the system bus is
requited, the 8289 forces the processor to wait until it
ARDY
INPUT
The 80186 provides two ready lines, a' ~ynchronous
ready (SRDY) line and an asynchronous ready
(ARDY) line. These lines signal the ,processor to insert
wait states (Tw) into a CPU bus cycle. This allows sloWer,
devices to respOnd to CPU service requests (reads or
writes). Wait states will only be inserted when both
ARDY and, SRDY are low, i.e., only one of ARDY or
SRDY need be active t9 terminate a bus cycle. Any
number of wait states may be in~erted into a bus cycle.
• The 80186 will ignore the RDY inputs during any accesses to the integrated peripheral registers, and to any
area where the chip select ready bits indicate that, the
external ready should be ignored.
The timing required by the two ROY lines is different.
The AROY line is meant to be used with asynchronous
ready inputs. Thus, inputs to this line will be internally
synchronized to the CPU clock before ,being presented to
the pr~essor. The synchronization circuitry used with
the ARQY line is shown in Figure 17. Figure 18A and
188 show valid and invalid transitions ofthe ARDY line
(and subsequent wait state insertion). The first flip-fl~p
is used to "resolve" the asynchronous transition of the
ARDY \ine. It will achieve a definit,e level (either high
or low) before its output is latched into the second flip-
r--------~-------~
, '
I
I
I
I
\I
'I
I
80186
D
Q
'--L....J
..,CD",,1
TO BUS
INTERFACE
UNIT
C
CPU
, ICLOCK--~~--~------~
L..._____________
__.....l
FROM SYNCHRONOUS
READY
1. Asynchronous Resolution Flip Flop
2. Ready Latch Flip Flop
Fisiu~ 17.
Asynchronous Re/ldy Circuitry of the 80188
3-268,
AFN-21 0973
AP-186
flop for presentation to the CPU. When latched high, it
allows the level present on the ARDY line to pass directly to the CPU; when latched low, it forces not ready to be
presented to the CPU (see Appendix B for 80186 synchronizer information).
.
by any inactive going transition of the ARDY line. The
reason ARDY is implemented in this manner is to allow
a slow device the greatest amount of time to respond
with a not ready after it has been selected. In a normally
ready system, a slow device must respond with a not
ready quickly after it has been selected to prevent the
processor from continuing and accessing invalid data
from the slow device. ·By implementing ARDY in the
above fashion, the slow device has an additional clock
phase to respond with a not ready.
With this scheme, notice that only the active going edge
of the ARDY signal is synchronized. Once the synchronization flip-flop has sampled high, the ARDY input directly drives the RDY flip-flop. Since inputs to this
RDY flip-flop must satisfy certain setup and hold times,
it is important that these setup and hold times (tARYLCL
= 35ns and tcHARYX = 15 ns respectively) be satisfied
~
:
If RDY is sampled active into the RDY flip-flop at the
beginning of T3 or Tw (meaning that ARDY was sam-
~
:
~
:
~
:
OUT
"
CLOCK~
CD
ARDY
0
.
.l.l.l.l.l.Wl.U.Wl.U.Wl.U.UJJ
1. No set-up or hold times required
2. tcu.RVX: Clock low to ARDY inactive (ARDY active hold time) = 15 ns min
~
:
~
:
~
:
~
:
OUT
CLOCK~
CD
ARDY
5DtD
==~---II~1.uJJJI
1. tARYHCH: ARDY valid until clock high (ARDY inactive set-up time to clock
high) = 20 ns min
2. No set-up or hold time required ONLY if (j) is guaranteed
3. tCLARYX: Clock low to ARDY inactive (ARDY active hold time) = 15 ns min
~
:
~
:
~
:
~
:~
1. tARYLCL: AHOY low to clock low (ARDY inactive set-up time to clock low) =
35ns min
must be satisfied since synchronizing FLIP-FLOP has sampled
active
2. tARYHCH: ARDY high to clock high (ARDY active set-up time) = 20 ns min
must be satisfied ONLY to guarantee recognition at the next clock
(i.e. to guarantee synchronizing FLIP-FLOP will sample ARDY
active)
3. tCLARYX: Clock low to ARDY inactive (ARDY active hold time) = 15 ns
Figu", 18A. Valid ARDY Transitions
3-269
AFN-21 0973
AP:-188
I
. CLOCK
OUT
T2
I
T",
:'.'Q):
:.
~
------'--- I
I
I
I
.1
ARDY
I
t
I
I
•
I
I
,
1
,
I
I
CD LESS THAN 35 ns
CLOCK~:
~
T2
T.
:
?
:
OUT~0~
I
ARDY,
I
I
I
I
I
,
I
I
I
I
1. Less than 20 ns
2. Less than 35 ns
Figure 188.
Invalid ARDY Transitions
pled high into the synchronization flip-flop in the middle
of a T state, and has remained high until the beginning
of the next T state), that T state will be immediately followed by T 4 • If ROY is sampled low into the ROY flipflop at the beginning of T3 or Tw (meaning that either
AROY was sampled low into the synchronization flipflop OR that AROY was sampled high into the synchronization flip-flop, but has subsequently changed to low
before the AROY setup time) that T state will be immediately followed by a wait state (Tw)' Any asynchronous
transition on the AROY line not occurring durin~ the
above times, that is, when the processor is not "looking
at" the ready lines, will not cause CPU malfunction.
Again, for AROY to force wait states to be inserted,
SROY must be driven low, since they are internally
ORed together to form the processor ROY signal.
The synchronous ready (SROY) line requires that ALL
transitions on this line during T 2• T3 or Tw satisfy a certain setup and hold time (tSRYCL = 35 ns and tCLSRY =
15 ns respectively). If these requirements are not met,
the CPU will not function properly. Valid transitions on
this line, and subsequent wait state insertion is shown in
Figure 19. The processor looks at this line at the beginning of each T 3 and Tw' If the line is samp,le---1""'"""'"
SHE
AO
CLKOUT
WR
2188
RD
2188
CE
CE
WE
WE
OE
OE
AO-A12
AO-AU
4.7K
ARDY
ADOAD13
AD15 -----------------~~~~---_4~~--~~~-~
Figure 21. Examp!e2186/8Q186Interface
3-272
AFN-21 0973
AP-186
The 2186 internally is a dynamic RAM integrated with
refresh and control circuitry. It operates in two modes,
puls£.!!1ode and late cycle mode. Pulse mode is entered if
the CE signal is low to the device a maximum of 130ns,
and requires the command input (RO or WE) to go active within 90ns after CEo Because of these requirements, interfacing the 80186 to the 2186 in pulse mode
would be difficult. Instead, the late cycle mode is used.
This affords a much simpler interface with no loss of
performance. The iRAM automatically selects between
these inodes by -the nature of the control signals.
The 2186 is a leading edge triggered device. This means
that address and data information are strobed into the
device on the active going (high to 10!1.transition of the
command signal. This requires both CE and WR be delayed until the address and data driven by the 80186 are
guaranteed stable. Figure 21 shows a simple circuit
which can be used to perform this function. Note that
ALE CANNOT be used to delay CE if addresses are not
latched externally, because this would violate the address hold time required by the 2186 (30ns).
Because the 2186s are RAMs, data bus enables (BHE
and AO, see previous section) MUST be used to factor
either the chip enables or write enables of the lower and
upper bytes of the 16-bit RAM memory system. If this is
not done, all memory writes, including single byte
writes, will write to both the upper and lower bytes of the
memory system. The exampl~siem shown uses BHE
and AO as factors to the 2186 CEo This may be done, because both of these signals (AO and BHE) are valid
when the address information is valid from the 80186.
The 2186 requires a certain amount of recovery time between its chip enable going inactive and its chip enable
going active insure proper operation. For a "normal" cycle (a read or write), this time is tEHEL = 40ns. This
means that the 80186 chip select lines will go inactive
soon enough at the end of a bus cycle to provide the required recovery time even if two consecutive accesses are
made to the iRAMs.lfthe 2186 CEis asserted without a
command signal (WE or OE), a "False Memory Cycle"
(FMC) will be generated. Whenever a FMC is generated, the recovery time is much longer; another memory
cycle must not be initiated for 200ns. As a result, if the
memory system will generate FMCs, CE must be taken
away in the middle of the T state (T 3 or Tw) immediately
preceding T 4 ,to insure two consecutive cycles to the
iRAM will not violate this parameter. Status going passive (all high) can be used for this purpose. These lines
will all go high during 'the first phase of the next to last T
state (either T 3 or Tw) of a bus cycle (see section 3.1.5).
access coincides with an internally generated refresh cycle. This is an open collector output, allowing many of
them to be wire-OR'ed together, since more than one device may be accessed at at time. These lines are also normally ready, which means' that they will be high
whenever the 2186 is not being accessed, i.e., they will
only be dri~en low if a processor request coincides with
an internal refresh cycle. Thus, the ready lines from the
iRAM must be factored into the 80186 ROY circuit
only during accesses to the iRAM itself. Since the 2186
refresh logic operates asynchronously to the 80186, this
ROY line must be synchronized for proper operation
with the 80186, either by the integrated ready synchronizer or by an external circuit. The example circuit uses
the integrated synchronizer associated with the AROY
processor input.
The ready lines c;>f the 2186 are active unless a processor
access coincides with an internal refresh cycle. These
lines must go inactive soon enough after a cycle is requested to insert wait states into the data c~. The
2186 will drive this line low within 50ns after CE is received, which is early enough to force the 80186 to insert
wait states if they are required. The primary concern
here is that the AROY line be driven not active before
its setup time in the middle of T 2. This is required by the
nature of the asynchronous ready synchronization circuitry of the 80186. Since the ROY pulse of the 2186
may be as narrow as 50ns, if ready was returned after
the first stage of the synchronizer, and subsequently
changed state within the ready setup and hold time of
the high to low going edge of the CPU clock at the end of
T 2, improper operation may occur (see section 3.1.6).
The example interface shown has a zero wait state RAM
read access time from CE of:
3 * t CLCL - tCLCSV - (TTL delay) - t DVCL
= 375 - 66 - 30 - 20 ns
= 259 ns
where:
t CLCL = CPU clock cycle time
tCLCSV
t DVCL
=
time from clock low in T 1 until chip selects
are valid
= 80186 data in setup time before clock low in
T4
The data valid delay from OE active is less than lOOns,
. and is therefore not an access time limiter in this interface. Additionally, the 2186 data float time from RO inactive is less than the 85ns' 80186 imposed maximum.
Finally, since it is a dynamic device, the 2186 requires
The CE generation circuit shown in Figure 21 provides
refresh cycles to maintain data integrity. The circuitry
an address setup time of at least Ilns, and an address
to generate these refresh cycles is integrated within the
hold time of at least 35ns (assuming a maximum two
2186. Because of this, the 2186 has a ready line which is
level TTL delay of less than 30ns).
used to suspend processor operation if a processor RAM·
3-273
AFN-21 0973
AP.,186,
Write cycle address setup and hold times are identical to
the read cycle times. The circuit shown provides at least
Iins write data setup and lOOns data hold time from
WE, easily meeting the Ons setup and 40ns hold times
required by the 2186.
For more information concerning 2186 timing and interfacing, please consult the 2186 data sheet, or the application note AP-132, "Designing Memory Systems
with the 8Kx8 iRAM" oy John Fallin and William
Righter (June 1982).
3.2.3 8203 DRAM INTERFACE
An example 8203/DRAM interface is shown in Figure
22. The 8203 provides all required DRAM control signals, address multiplexing, and refresh generation. In
this circuit, the 8203 is configured to interface with 64K
DRAMs.
All 8203 cycles are generated off control signals (RD
and WR) pro'<'ided by the 80186. These signals will not
go active until T 2 of the bus cycle. In addition, since the
8203 clock (generated by the internal crystal oscillator
of the 8203) is asynchronous to the 80186 clock, all
memory requests by the 80186 must be synchronized to
the 8203 before the cycle will be run. To minimize this
synchronization time, the 8203 should be used with the
highest speed crystal that will maintain DRAM compatibility. Even' if a 25 MHz crystal is used (the maximum allowed by the 8203) two wait states will be
required by the example circuit when using 150ns
DRAMs with an 8 MHz 80186, three wait states if
200ns DRAMs are used (see timing analysis, Figure
23).
The entire RAM array controlled by the 8203 can be selected by one or a group of the 80186 provided chip selects. These chip selects can also be used to insert the
wait states required by the interface.
"-
~
MCS1
MCSO
A17-A1
AROY
U
-
8203
SEL WR
AOA16, WE
17/
,
eo
...0/1.
U
22!1
UPPER
BYTE WE
LOWER
BYTE WE
r--
SACK'
...--
220
DRAMS'
XACK
RO
1
/.
ADO-AD1S
010-15
000-15
8282
~
./
~
-
000-7
010-7 ~
OE
STB
8282
-
,
000-7
OE
L...-.-...,. STB
Figure 22;
010·7
-
Example 8203/DRAM/80186 Interface
3-274
AFN-21 0973
AP-186
T,
188 ___-+~~
RD
8203
RAS
-----------------:110-----.
8203
CAS ----+-----r--~~_+_,
RAM mT.mn~mT.mT.mn~mT.mT.mn~mT.mT.~mT.~mnu----t-----------DATA ~~~~~~~~~~""""""""""~~~'~__~~______~
LATCH ~mm~mmmmmmmm""mmmm""""""""""~~~~~r~~--------DATA ~~~~~~~~~~~~~~~~~~__~_______
1. tCLEL: CI0Ck low until read low
=
2. tCR: Command active until RAS
=
=
70 ns max
150 ns max·
(j)
3. tcc: Command active until CAS
245 ns max·
4. tcAC: Access time from CAS = 85 ns max
5. tISOU: Input to output delay = 30 ns max
6. tOVCL: Data valid to clock low (data in set up) = 20 ns min
Total Access Time = 70 + 245 +85 +30 +20 = 450 ns (3.6 T-states)
Figure 23.
&@ are 186 specs
® & @ are 8203 specs
@
@
is a 2164A-15 spec
is on 8282 spec
·Assumes 25MHz
8203 operation
8203/2164A-15 Access Time Calculation
Since the 8203 is operating asynchronously to the
80186, the RDY output of the 8203 (used to suspend
processor operation when a processor DRAM request
coincides with a DRAM refresh cycle) must be synchronized to the 80186. The80186 ARDY line is used to provide the necessary ready synchronization. The 8203
ready outputs operate in a normally not ready mode,
that is, they are only driven active when an 8203 cycle is
being executed, and a refresh cycle is not being run. This
is fundamentally different than the normally ready
mode used by the 2186 iRAMs (see previous section).
The 8203 SACK signal is presented to the 80186 only
when the DRAM is being accessed. Notice that the
SACK output of the 8203 is used,rather than the
XACK output. Since the 80186 will insert at least one
full CPU clock cycle between the time ROY is sampled
active, and the time data must be present on the data
bus, using the XACK signal would insert unnecessary
additional wait states, since it does not indicate ready
until valid data is available from the memory.
For more information about 8203/DRAM interfacing
and timing, please consult the 8203 data sheet, or
AP97 A, "Interfacing Dynamic RAM to iAPX86/88
Systems Using the Intel 8202A and 8203" by Brad May
(April 1982).
3.2.4 8207 DRAM INTERFACE
The 8207 advanced dual-port DRAM controller provides a high performance DRAM memory interface
specifically for 80186 or 80286 microcomputer systems.
This controller provides all address multiplexing and
DRAM refresh circuitry. In addition, it synchronizes
and arbitrates memory requests from two different ports
(e.g., an 80186 and a Multibus), allowing the two ports
to share memory. Finally,the 8207 provides a simple interface to the 8206 error detection and correction chip.
The simplest 8207 (and also the highest performance)
interface is shown in Figure 24. This shows the 80186
connected to an 8207 using the 8207 slow cycle, synchronous status interface. In this mode, the 8207 decodes the
type of cycle to be run directly from the status lines of
the 80186. In addition, since the 8207 CLOCKIN is
driven by the CLOCKOUT of the 80186, any performance degradation caused by required memory request
synchronization between the 80186 and the 8207 is not
present. Finally, the entire memory array driven by the
3-275
AFN-21 0973
AP-186
8207 may be selected using one or a group of the 80186
memory chip selects, as in the 8203 interface above.
8018
7
ClKOUT
ClK
so
WR
Sf
RD
52
PCTL
lMCS
+5
PCTC
When the 80186 recognizes a bus hold by driving
HLDA high, it will float many of its signals (see Figure
25). ADO - ADI5 (address/data 0 - 15) and DEN (data
enable) are floated within tCLAZ (35ns) after the same
clock edge that HLDA is driven active. A16-A19 (addresU6 - 19), RD, WR, BHE (B~Hl&.h Enable),
DT /R (Data Transmit/Receive) and SO - S2 (status 02) are floated within t CHCZ (45ns) after the clock edge
immediately before the clock edge on which HLDA
comes active.
PE
I
CLOCK
. I
T. OR T,
T,
T,
OUT
SRDY
HOLD - - - - ; - - - . . . . . ,.....':7------;---
Figure 24. 80186/8207/DRAM Interface
HlDA
The 8207 AACK signal may be used to generate a synchronousready signal to the 80186 in the above interface. Since dynamic memory periodically requires
refreshing, 80186 access cycles may occur simultaneously with an 8207 generated refresh cycle. When this
occurs, the 8207 will hold the AACK line high until the
processor initiated access is run (note, the sense of this
line is reversed with respect to the 80186 SRDY input).
This signal should be factored with the DRAM (8207)
select input and used to drive the SRDY line of the'
80186. Remember that only one of SRDY and ARDY
needs to be active for a bus cycle to be terminated. If
asynchronous devices (e.g., a Multibus interface) are
connected to the ARDY line with the 8207 connected to
the SRDY lille, care must be taken in design of the ready
circuit such that only one of the RDY lines is driven active at a time to prevent premature termination of the
bus cycle.
.
3.3 HOLD/HLDA Interface
The 80186 employs a HOLD/HLDA bus exchange protocol. This protocol allows other asynchronous bus master devices (i.e., ones which drive address, data, and
control infOI:ma tion on the bus) to gain control of the bus
to perform bus cycles (memory or I/O reads or writes).
3.3.1
HOLD RESPONSE
In the HOLD/HLDA protocol, a device r~CJ.uiring bus
control (e.g., an external DMA device) raises the
HOLD line. In response to this HOLD request, the
80186 will raise its HLDA line after it has finished its
current bus activity. When the external device is finislted
with the bus, it drops its bus HOLD request. The 80186
responds by dropping its HLDA line and resuming bus
operation.
---.--.....,1-/--:-'
---.---f--t:,:'+--.:.=.:.:...._---+-_--'
AD15·ADO
DEN _ _ _ _
A18·A19
RD,WR,BHE
DT/R,SO.52
Figure 25.
---:--....1
Signal Float/HLDA Timing of the 80186
Only the above mentioned signals are floated during bus
HOLD. Of the signals not floated by the 80186, some
have to do with peripheral functionality (e.g., TmrOut).
Many others either directly or indirectly control bus devices. These signals are ALE (Address Latch Enable,
see section 3.1.2) and all the chip select lines (UCS,
LCS, MCSO-3, and PCSO-6). The designer must be
aware that the chip select circuitry does not look at externally generated addresses (see section 10 for a discussion of the chip select logic). Thus, for memory or
peripheral devices which are addressed by external bus
master devices, discrete chip select and ready generation
logic must be used.
3.3.2
HOLD/HLDA TIMING AND BUS LATENCY
The time required between HOLD going active and the
80186 driving HLDA active is known as bus latency.
Many factors affect this latency, including synchronization delays, bus cycle times, locked transfer times and
interrupt acknow~edge cycles.
The HOLD request line is internally synchronized by
the 80186, and may therefore be an asynchronous signal. To guarantee recognition on a certain clock edge, it
must satisfy a certain setup and hold time to the ftilling
3-276
AFN·21 0973'
AP-186
edge of the CPU clock. A full CPU clock cycle is required for this synchronization, that is, the internal
HOLD signal is not presented to the internal bus arbitration circuitry until one full clock cycle after it is
latched from the HOLD input (see Appendix B for a dis-
cussion of 80186 synchronizer~). If the bus is idle,
HLDA will follow HOLD by two CPU clock cycles plus
a small amount of setup and propagation delay time.
The first clock cycle synchronizes the input; the second
signals the internal circuitry to initiate a bus hold. (see
Figure 26).
Many factors influ'¥lce the number of clock cycles between a HOLD request and a HLDA. These may make
bus latency longer than the best case shown above. Perhaps the most impor,tant factor is that the 80186 will not
relinquish the local bus until the bus is idle. An idle bus
occurs whenever the 80186 is not performing any bus
transfers. As stated in section 3.1.1, when the bus is idle,
the 80186 generates idle T-states. The bus can become
idle only at the end of a bus cycle. Thus, the 80186 can
recognize HOLD only after the end of its current bus cycle. The 80186 will normally insert no T j states between
T 4 and T 1 of the next bus cycle if it requires any bus activity (e.g., instruction fetches or I/O reads). However,
the 80186 may not have an immediate need for the bus
after a bus cycle, and will insert T j states independent of
the HOLD input (see section 3.1.7).
HOLD
HLDA ------------~
1. tHVCL: Hold va Id until clock low"; 25 ns min
2. tcLHAV: Clock low until HLDA active = 50 ns max
Figure 26. 80186 Idle Bus Hold/HLDA Timing
When the HOLD request is active, the 80186 will be
,CLOCK
OUT
HOLD ______oJ
HLDA ------~-----~-----~
1. Decision: No additional internal bus cycles required, idle T-states will be
inserted after T4
2. Greater than 25 ns (t HvCL)
3. Less than 50 ns (IcLHAV)
4. HOLD request internally synchronized
T.OR
:
CLOCK
OUT
Tw
:
T.
:
T,
~
l
I
I
I
I
I
HOLD
HLDA - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1. Decision: Additional internal bus cycles required. no idle T-states will be
inserted, Hold not active soon enough to force idle T-states
2. Greater than 25 ns (t HvCL): not required since it will not get recognized
anyway
3. HOLD request internally synchronized
Figure 27. HOLD/HLDATlmlng in the 80186
3-277
AFN-21 0973
AP-186
T.,T. or
T.or
Tw
Tw
T,
1. HOLD request internally synchronized
2. Decision: HOLD request active, idle t-states will be inserted at end of
current bus cycle
3. Greater than 25 ns
4. Less than 50 ns
Figure 27A.
HOLD/HLDA Timing in the 80186
forced to proceed from T 4 to T j in order that the bus may
be relinquished. HOLD must go active 3 T-states before
the end of a bus cycle to force the 80186 to insert idle Tstates after T 4 (one to synchronize the request, and one
to signal the 80186 that T 4 of the bus cycle will be followed by idle T-states, see section 3.1.1). After the bus
cycle has ended, the bus hold will be immediately acknowledged. If, however, the 80186 has already determined that an idle T-state will follow T4 of the current
bus cycle, HOLD need go active only 2 T-states before
the end of a bus cycle to force the 80186 to relinquish the
bus at the end of the current bus cycle. This is because
the external HOLD request is not required to force the
generation of idle T-states. Figure 27 graphically portrays the scenarios depicted above.
An external HOLD has higher priority than both the
80186 CPU or integrated 0 MA unit. However, an external HOLD will not separate the two cycles needed to
perform a word access when the word accessed is located
at an odd location (see section 3.1.3). In addition, an external HOLD will not separate the two-to-four bus cycles required to perform a DMA transfer using the'
integrated controller. Each of these factors will add additional bus cycle times to the bus latency of the 80186.
Another factor influencing bus latency time is locked
transfers. Whenever a locked transfer is occurring, the
80186 will not recognize external HOLDs (nor will it
recognize internal DMA bus requests). Locked transfers are programmed by preceding an instruction with,
the LOCK prefix. Any transfers generated by such a
prefixed instruction will be locked, and will not be separated by any external bus requesting device, String instructions may be locked. ,Since string transfers may
require thousands of bus cycles, bus latency time will
suffer if they are locked.
The final factor affecting bus latency time is interrupt
acknowledge cycles. When an external interrupt controller is used, or if the integril ted interrupt controller is
used in iRMX 86 mode (see section 6.7.4) the 80186 will
run two interrupt acknowledge cycles back to back.
These cycles are automatically "locked" and will never
be separated by any bus HOLD, either internal or external. See section 6.5 on interrupt acknowledge timing for
more information concerning interrupt acknowledge
timing.
3.3.3 COMING OUT OF HOLD
After the 80186 recognizes that the HOLD input has
gone inactive, it will drop its HLDA line in a single
clock. Figure 28 shows this timing. The 80186 will insert
only two T j after HLDA has gone inactive, assuming
that the 80186 has internal bus cycles to run. During the
last T j , status information will go active concerning the
bus cycle about to be run (see section 3.1.1). If the
80186 has no pending bus activity, it will maintain all
lines floating (high impedance) until the last T j before it
begins its first bus cycle after the HOLD.
3.4
Differences Between the 8086 bus and
the 80186 Bus
The 80186 bus was defined to be upward compatible
with the 8086 bus. As a result, the 8086 bus interface
components (the 8288 bus controller and the 8289 bus
arbiter) may be used directly with the 80186. There are
a few significant differences between the two processors
which should be considered.
3-278
\
AFN-21 0973 .
Ap·186
T,
T,
CLOCK
OUT
HOLD - - - . ; 0
HLDA
----~----~~
ADG-AD15
DEN------~------~----~--~~~L---.....
A18/53-A19/S8
RD,WR,BHE
----.-:------:-----'--....J(
DT/R,5O-52
1.
2.
3.
4.
'---:-----
HOLD Internally synchronized
Greater than 25 ns
Less than 50 ns
Lines come out of float only if a bus cycle is pending
Figure 28.
80186 Coming out of Hold
CPU Duty Cycle and Clock Generator
ther two synchronous ready inputs or two
asynchronous ready inputs as a user strapable
option.
The 80186 employs an integrated clock generator which
provides a 50% duty cycle CPU clock (1/2 of the time it
. is high, the other 1/2 of the time it is low). This is different that the 8086, which employs an external clock generator (the 8284A) with a 33% duty cycle CPU clock
(1/3 of the time it is high, the other 2/3 of the time, it is
low): These differences manifest themselves as follows:
6) The CLOCKOUT (CPU clock output signal)
drive capacity of the 80186 is less than the CPU
clock drive capacity of the 8284A. This means
that not as many high speed devices (e.g.,
Schottky TTL flip-flops) may be connected to
this signal as can be used with the 8284A clock
output.
1) No oscillator output is available from the 80186,
as it is available from the 8284A clock generator.
7) The crystal or external oscillator used by the
80186 is twice the CPU clock frequency, while
the crystal or external oscillator used with the
8284A is three times the CPU clock frequency.
2) The 80186 does not provide a PCLK (50% duty
cycle, 1/2 CPU clock frequency) output as does
the 8284A.
3) The clock low phase of the 80186 is narrower,
and the clock high phase is wider than on the
same speed 8086.
Local Bus Controller and CO!'trol Signals
4) The 80186 does not internally factor AEN with
RDY. This means that if both RDY inputs
(ARDY and SRDY) are used, external logic
must be used to prevent the RDY not connected
to a certain device from being driven active during an access to this device (remember, only one
RDY input needs to be active to terminate a bus
cycle, see section 3.1.6).
The 80186 simultaneously provides both local b.!!;i controller outputs (RD,..Flh..ALE, DEN and DT /R) and
status outputs (SO, Sl, S2) for use with the 8288 bus
controller. This is different from the 8086 where the local bus controller outputs (generated only in min mode)
are sacrificed if status outputs ( generated only in max
mode) are desired. These differences will manifest
themselves in 8086 systems and 80186 systems as
follows:
5) The 80186 concurrently provides both a single
asynchronous ready input and a single.synchronous ready input, while the 8284A provides ei-
1) Because the 80186 can simultaneously provide
local bus control signals and status outputs,
many systems supporting both a system bus (e.g.,
3-279
AFN-21 0973
AP-186
a Multibusl!!» and a local bus will not require two
separate external bus controUers, that is, the
80186 bus control signals may be used to control
the local bus while the 80186 status signals are
COnC1il'ently connected to the 8288 bus controller to'drive the control signals of the system bus.
2) The ALE signal of the 80186 goes active a clock
phase earlier on the 80186 then on the 8086 or
8288. This minimizes address propagation time
through the address latches, since typically the
delay time through these latches from inputs valid is less than the propagation delay from the
strobe input active.
3) The 80186 RD input must be tied low to provide
queue status outputs from the 80186 (see Figure
29). When so s.!!:!Eped into "queue status mode,"
the ALE and WR outputs provide queue status
information. Notice that this queue status information is available one clock phase earlier from
the 80186 than from the 8086 (see Figure 30).
80186'
QSO
ALE
QS1
WR
~
ample the 82586 Ethernet· controller or 82730 high
performance CRT controller/text coprocessor).
'.
Status
Inf.~rmation
The 80186 does not provide S3-S5 status information.
On the 8086, S3 and S4 provide information regarding
the segment register used to generate the physical address of the currently executing bus cycle. S5 provides
information concerning the state of the interrupt enable
flip-flop. These status bits are always low on the 80186.
Status signal S6 is used to indicate whether the current
bus cycle is initiated by either the CPU or a DMA device. Subsequently, it is always low on the 8086. On the
80186, it is low whenever the current bus cycle is initiated by the 80186 CPU, and is high when the current bus
cycle is initiated by the 80186 integrated DMA unit.
Bus Drive
The 80186 output drivers will drive 200pF loads. This is
double that of the 8086 (lOOpF). This allows larger systems to be constructed without the need for bus buffers.
It also means that it is very important to provide good
grounds to the 80186, since its large drivers can discharge its outputs very quickly causing large current
transients on the 80186 ground pins.
RD
Misc.
Figure 29. Generating Queue Status Information
from the 80186
HOLD/HLDA vs. RQ/GT
As discussed earlier, the 80186 uses a HOLD/HLDA
type of protocol for exchanging bus mastership (like the
8086 in min mode) rather than the RQ/GT protocol
used by the 8086 in max mode. This allows compatiblity
with Intel's the new generation of high performance/
high integration bus master peripheral devices (for ex-
The 80186 does not provide early and late write signals,
a.s does the 8288 bus controller. The WR signal generated by the 80186 corresponds to the early write signal of
the 8288. This means that data is not stable on the address/ data bus when this signal is driven active.
The 80186 also does not provide differentiated i/q and
memory read and write command signals. If these signals are desired, an external 8288 bus controller may be
used, or the S2 signal may be used to synthesize differentiated commands (see section 3.1.4).
"Ethernet is a registered trademark of Xerox Corp.
CLOCK
OUT
186 --------~------~~--_h~~~--h/~~~----
QS ________~------~----~'~~----~~-------8086 -----;.-----i-----~~--4~--QS __________________________~____~'L__ __ _
1. 80186 changes queue status off falling edge of elK
2. 8086 changes queue status off rising edge of elK
Figure 30. 80186 and 8086 Queue Status Generation
3-280
AFN-21 0973
AP-186
. 4.
DMA UNIT INTERFACING
Programmable generation of DMA requests by:
The 80186 includes a DMA unit which provides two indeperident high speed DMA channels. These channels
operate independently of the CPU, and drive all integrated bus interface components (bus controller, chip selects, etc.) exactly as the CPU (see Figure 31). This
means that bus cycles initiated by the DMA unit are exactly the same as bus cycles initiated by the CPU (except that S6 = 1 during all DMA initiated cycles, see
section 3.1). Thus interfacing with the DMA unit itself
is very simple, since except for the addition of the DMA
request connection, it is exactly the same as interfacing
to the cpu.
EXTERNAL ADDRESS/DATA,
CONTROL, CHIP SELECTS,
ETC.
BUS INTERFACE
4) the DMA unit itself (continuous DMA requests)
4.2
DMA Unit Programming
Each of the two DMA channels contains a number of
registers which are used to control channel operation.
These registers are included in the 80186 integrated peripheral control block (see appendix A). These registers
include the source and destination pointer registers, the
transfer count register and the control register. The layout and interpretation of the bits in these registers is given in Figure 32.
After every DMA transfer the 16-bit DMA transfer
count register it is decremented by 1, whether a byte
transfer or a word transfer has occurred. If the TC bit in
the DMA control register is set, the DMA ST /STOP
bit (see below) will be cleared when this register goes to
0, causing all DMA activity to cease. A transfer count of
zero allows 65536 (2 16) transfers.
DMA
REQUESTS
4.1
3) timer 2 (see section 5)
The 20-bit source and destination pointers allow access
to the complete 1 Mbyte address space of the 80186, and
that all 20 bits are affected by the auto-increment or
auto-decrement unit of the DMA (Le., the DMA
channels address the full 1 Mbyte address space of the
80186 as a flat, linear array without segments). When
addressing I/O space, the upper 4 bits of the DMA
pointer registers should be programmed to be O. If they
are not programmed 0, then the programmed value
(greater than 64K in I/O space) will be driven onto the
address bus (an a,rea of I/O space not accessable to the
CPU). The data transfer will occur correctly, however.
"
Figure 31.
1) the source of the data
2) the destination of the data
80186 CPU/DMA Channel
Internal Model
DMA Features
Each of the two DMA channels provides the following
features:
Independent 20-bit source and destination pointers
which are used to access the I/O or memory location
from which data will be fetched or to which data will
be deposited
Programmable auto-increment, auto-decrement or
neither of the source and destination pointers after
each DMA transfer
Programmable termination of DMA activity after a
. certain number of DMA transfers
Programmable CPU interruption at DMA termination
Byte or word DMA transfers to or from even or odd
memory or I/O addresses
The DMA control register (see Figure 33) contains bits
which control various channel characteristics, including
for each of the data source and destination whether the
pointer points to memory or I/O space, or whether the
pointer will be incremented, decremented or left alone
. after each DMA transfer. It also contains a bit which selects between byte or word transfers. Two synchronization bits are used to determine the source of the DMA
requests (see section 4.7). The TC bit determines whether DMA activity will cease after a programmed number
orDMA transfers, and the INT bit is used to enable interrupts to the processor when this has occurred (note
that an interrupt will not be generated to the CPU when
the transfer count register reaches zero unless both the
INT bit and the TC bit are set).
The control register also contains a start/stop
(ST /STOP) bit. This bit is used to enable DMA
transfers. Whenever this bit is set, the channel is
\ 3-281
AFN-21 0973
AP-186
OFFSET
DEH
DCH
DAH
x
I
D8H
D8H
15
D4H
D2H
15
DOH
CEH
15
CCH
CAH
C8H
X
I
I I I
IX I I I
'1
119
,
119
X
X
0
16
0
18
0
CONTROL WORD
TRANSFER COUNT
DESTINATION POINTER
SOURCE POINTER CHANNEL 1
I I I xl I I
Ie
Ie
Ie
119
Ie
Ie
Ie
119
15
15
15
0
18
0
18
0
t
CH~NNELOl
X
I I I
I
C6H
C4H
C2H
COH
X
CONTROL WORD
TRANSFER COUNT
DESTINATION POINTER
SOURCE POINTER
(1) CONTROL REGISTER LAYOUT:
DESTINATION
-----
. SYNCHRONIZATION
SOURCE
Figure 32.
80186 DMA Register Layout
Figure 33.
DMA Control Register
"armed," that is, a DMA transfer will occur whenever a
DMA request is made to the channel. If this bit is
cleared, no DMA transfers will be performed by the
channel. A companion bit, the CHG/NOCHG bit,
. allows the contents of the DMA control register to be .
changed without modifying the state of the start/stop
bit. The ST /STOP bit will only be modified if the
CHG/NOCHG bit is also set during the write to the
DMA control register. The CHG/NOCHG bit is
write only. It will always be read back as a I. Becaase
DMA transfers could occur immediately after the
ST /STOP bit is set, it should only be set only after all
other DMA contr911er registers have been programmed.
This bit is automatically cleared when the transfer count
register reaches zero and the TC bit in the DMA control
register is set, or when the transfer count register
reaches zero and unsynchronized DMA transfers are
programmed.
All DMA unit programming registers are directly
accessable by the CPU. This means the CPU can, for example, modify the DMA source pointer register after
137 DMA transfers have occurred, and have the new
pointer value used for the 138th DMA transfer. If more
than one register in the DMA channel is being modified
at any time that a DMA request may be generated and
the DMA ch~nnel is enabled (the ST /STOP bit in the
control register is set), the register programming values
should be placed in memory locations and moved into
the DMA registers using a locked string move instruction. This will prevent a DMA transfer from occurring
after only half of the register values have changed. The
above also holds true if a read/modify/write type of operation is being performed (e.g., ANDing off bits in a
pointer register in a single AND instruction to a pointer
.
register mapped into memory space).
.3-282
AFN-21 0973
AP-186
CLOCK
1 Tn
1
1
1
T,
T.
T,
Tw
T,
T.
Tw
T,
T.
T4
OUT~
1
I
~
1
ORO
ADO-
A015
RO
WR
I
I
I
I
I
I
1
I
1
I
1
1
1
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:\
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1. Source address
2. Source data
3. Destination address
4. Destination data
NOTE: Wait states are inserted by the bus condition during the bus cycle, not by the DMA controller
Figure 34.
Example DMA Transfer Cycle on the 80186
4.3 DMA Transfers
Every D MA transfer in the 80186 consists of two independent bus cycles, the fetch cycle and the deposit cycle
(see Figure 34). During the fetch cycle, the byte or word
data is accessed from memory or I/O space using the address in the source pointer register. The dllta accessed is
placed in an internal temporary register, which is not accessible to the CPU. During the deposit cycle, the byte
or word data in this internal register is placed in memory
or I/O space using the address in the destination pointer
register. These two bus cycles will not be separated by
bus HOLD or by the other DMA channel, and one will
never be run without the other except when the CPU is
RESET. Notice that the bus cycles run by the DMA
unit are exactly the same as memory or I/O bus cycles
run by the CPU. The only difference between the two is
the state of the S6 status line (which is multiplexed on
theA19 line): on all CPU initiated bus cycles, this status
line will be driven low; on all DMA initiated bus cycles,
this status line will be driven high.
4.4 DMA Requests
Each DMA channel has a single DMA request line by
which an external device may request a DMA transfer.
The synchronization bits in th,e DMA control register
determine whether this line is interpreted to be connected to the source of the DMA data or the destination of
the DMA data. All transfer requests on this line are synchronized to the CPU clock before being presented to in-
ternal DMA logic. This means that any asynchronous
transitions of the DMA request line will not cause the
DMA channel to malfunction. In addition to external
requests, DMA requests may be generated whenever the
internal timer 2 times out, or continuously by programming the synchronization bits in the DMA control register to call for unsynchronized DMA transfers.
4.4.1
DMA REQOEST TIMING AND LATENCY
Before any DMA request can be generated, ~he 80186
internal bus must be granted to the DMA unit. A certain
amount of time is required for the CPU to grant this internal bus to the DMA unit. The time between a DMA
request being issued and the DMA transfer being run is
known as DMA latency. Many of the issues concerning
DMA latency are the same as those concerning bus la-.
tency (see section 3.3.2). The only important difference
is that external HOLD always has bus priority over an
internal DMA transfer. Thus, the latency time of an internal DMA cycle will suffer during an external bus
HOLD.
Each DMA channel has a programmed priority relative
to the other DMA channel. Both channels may be programmed to be the same priority, or one may be programmed to be of higher priority than the other channel.
Ifboth channels are active, DMA latency will suffer on
the lower priority channel. If both channels are active
and both channels are of the same programmed priority,
DMA transfer cycles will alternate between the two
channels (Le., the first channel will perform a fetch and
3-283
AFN-21 0973
AP-186
To or
Ta or
To or
T,or
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?T ~ DEVICE CHIP SELECT
Figure 70.
8.1
80186/External Chip Select/Device Chip Select Generation
Memory Chip Selects
,The memory chip selects are <;ontrolled by 4 registers in
the peripheral control block (see Figure 72). These include 1 each for UCS and LCS, the values of which determine the size of the memory blocks addressed by
these two lines. The other two registers are used to control the size and base address of the mid-range memory
block.
The.80186 provides six discrete chip select lines which
are meant to be connected to memory components in an
, 80186 system. These signals are named UCS, LCS,
and MCSO-3 for Upper Memory Chip Select, Lower
Memory Chip Select and Midrange Memory Chip Selects 0-3. They are meant (but not limited) to be connected to the three major areas of the 80186 system
memory (see Figure 71).
~I
On reset, only l)CS is active. It is programmed by reset
to be active for the top 1K memory block, to insert 3 wait
states to all memory fetches, and to factor external
ready for every memory fetch (see section 8.3 for more
information on internal ready generation). All 'other
chip select registers assume indeterminate states after
reset, but none of the other chip select lines will be active
until all necessary registers for a signal have been accessed (not necessarily written, a read to an uninitialized
register will enable the chip select function controlled by
tha~ register).
FFFFF
STARTUP
ROM
MCS3 {
--MCS2 {
(
PROGRAM
8.2
MEMORY
The 80186 provides seven discrete chip select lines
which are meant to be connected to peripheral components in an 80186 system. These signals are named
PCSO-6. Each of these lines is active for one of seven
contiguous 128 byte areas in memory or I/O space
above a programmed base address.
--MCSl {
--MCSO {
,
INTERRUPT
=/
VECTOR
TABLE
0
Figure 71. 80186 Memory Areas & Chip Selects
As could be guessed by their names, upper memory, lower memory, and mid-range memory chip selects are designed to address upper, lower, and middle areas of
memory in an 80186 system. The upper limit of UCS
and the lower limit of LCS are fixed at FFFFFH and
OOOOOH in memory space, respectively. The other limit
of these is set by the memory size programmed into the
control register for the chip select line. Mid-range memory allows both the base address and the block size of the
memory area to be programmed. The only limitation is
that the base address must be programmed to be an integer multiple of the total block size, For example, if the
block size was 128K bytes (4 32K byte chunks) the base
address could be 0 or 20000H, but not 10000H.
Peripheral Chip Selects
The peripheral chip selects are controlled by two registers in the internal peripheral control block (see Figure
72). These registers allow the base address ofthe peripherals to be set, and allow the peripherals to be mapped
into memory or I/O space. Both of these registers must
be accessed before any of the peripheral chip selects will
become active.
A bit in the MPCS register allows PCS5 and PCS6
to become latched Al and A2 outputs. When this option
is selected, PCS5 and PCS6 will reflect the state of Al
and A2 throughoUt a bus cycle. These are provided to allow external peripheral register selection in a system in
which the addresses are not latched. Upon reset, these
lines are driven high. They will only reflect Al and A2
after both PACS and MPCS have been accessed (and
are programmed to provide Al and A2!).
8.3
Ready Generation
The 80186 includes a ready generation unit. This unit
generates an internal ready signal for all accesses to
memory or I/O areas to which the chip select circuitry of
the 80186 responds.
3-308,
AFN-210973
om_I"
II I'ell .
AP-186
OFFSET:
A2H
LOWER MEMORY SIZE
A4H
PERIPHERAL CHIP SELECT BASE ADDRESS
CD
CD
CD
ASH
MID-RANGE MEMORY BASE ADDRESS
G}
MMCS
ASH
MID-RANGE MEMORY SIZE
CD
MPCS
AOH
1.
2.
3.
4.
5.
6.
UPPER MEMORY SIZE
I~ I ~ I
UMCS
LMCS
PACS
Upper memory ready bits
Lower memory ready bits
PCSO-PCS3 ready bits
Mid-range memory ready bits
PCS4-PCS6 ready bits
MS: 1 = Peripherals active in memory space
= Peripherals active in I/O space
EX:1 = 7 PCS lines
0= PCS5 = A1. PCS6 = A2
o
Not all bits of every field are used
Figure 72_
80188 Chip Select Control Registers
For each ready generation area, 0-3 wait states may be
inserted by the internal unit. Table 6 shows how the
ready ~~trol bits should be programmed to provide this.
In additIon, the ready generation circuit may be programmed to ignore the state of the external ready (i.e.,
only the internal ready circuit will be used) or to factor
the state of the external ready (i.e., a ready will be returned to the processor only after both the internal ready
circuit has gone ready and the external ready has gone
ready). Some kind of circuit must be included to generate an external ready, however, since upon reset the
ready generator is programmed to factor external ready
to all accesses to the top lK byte memory block. If a
ready was not returned on one of the external ready lines
(ARDYor SRDY) the processor would wait forever to
fetch its first instruction.
Table 6.
80186 Wait State Programming
R2 R1
RO
Number of Wait States
0
1
0
1
0
1
0
1
o + external ready
1 + external ready
2 + external ready
3 + external ready
o(no external ready required)
0
0
0
0
1
1
1
1
0
o_
1
1'
0
0
1
1
8.4 Examples of Chip Select Usage
Many examples of the use of the chip select lines are given in the bus interface section of this note (section 3.2).
These ex~mples s?ow how simple it is to use the chip select functIOn provided by the 80186. The key point to remember when using the chip select function is that they
are only activated during bus cycles generated by the
80186 CPU or DMA units. When another master has
the ?~s, it must generate its own chip select function. In
addition, whenever the bus is given by the 80186 to an
external master (through the HOLD/ HLDA arrangement) the 80186 does NOT float the chip select lines.
8.5 Overlapping Chip Select Areas
Generally, the chip selects of the 80186 should not be
~rogrammed such that any two areas overlap. In additIOn, none of the programmed chip select areas should
overlap an~ of the locations of the integrated 256-byte
control register block. The consequences of doing this
are:
Whenever two chip select lines are programmed to
respond to the same area, both will be activated during any. access to that area. When this is done, the
ready bits for both areas must be programmed to the
same value. If thisis not done, the processor response
to an access in this area is indeterminate..
1 (no external ready required)
2 (no external ready required)
3 (no external ready required)
If any oj; the chip select areas overlap the integrated
256-byte control register block, the tinting on the
3-309
AFN-210!i73
AP-186
chip select line is altered. As always, any valuesreturned on the external bus from this access are ignored.
9.
SOFTWARE IN AN 80186 SYSTEM
Since the 80186 is object code compatible with the': 8086
and 8088, the software in an 80186 system is very similar to that in an 8086 system. Because of the hardware
chip select functions, however, a certain amount of inftialization code must be incfuded when using those func~
tions on the 80186.
9.1
System Initialization in an
80186 System
Most programmable components of a computer system
must be initialized before they are used. This is also true
for the 80186. The 80186 includes circuitry which directly affects the ability of the system to address memoryand I/O devices, namely the chip select circuitry.
This circuitry must be initialized before the memory
. areas and peripheral devices addressed by the chip select
signals ate used.
Upon reset, the UMCS register is programmed to beactive for all memory fetches within the top lK byte of
memory space. It is also programmed to insert three
wait states to all memory accesses within this space. If
the hardware chip selects are used, they· must be programmed before the processor leaves this lK byte area
of memory. If a jump to an area for which the chips are
not selected occurs, the ,microcomputer system wiII
cease to operate (since the processor will fetch garbage
from the data bus). Appendix F shows a typical initialization sequence for the 80186 chip select unit.
Once the chip selects have been properly initialized, the
rest of the 80186 system may be initializedmuch like an
8086 system. For example, the interrupt vector table
might get set up, the interrupt controller initialized, a
serial I/O channel initialized, and the main program begun. Note that the integrated peripherals included in the
80186 do not share the same programming model as the
standard Intel peripherals used to implement these
functions in a typical 8086 system, i.e., different values
must be programmed into different registers to achieve
the same function using the integrated peripherals. Appendix F shows a typical initialization sequence for an
interrupt driven system using the 80186 interrupt
controller.
9.2
model is not the same as is implemented by the 80186.
Because of this, the 80186 interrupt controller must be
placed in iRMX 86 mode after reset. This initialization
can be done at anytime after reset before jump to the
root task of iRMX 86 System is actually performed. If
need be, a small section of code which initializes both
the 80186 chip selects and the 80186 interrupt controller
can be inserted between the reset vector location and the
beginning of iRMX 86 System (see Figure 73). In this
case, upon reset, the processor would jump to the 80186
initialization code, and when this has been completed,
would jump to the iRMX 86 initialization code (in the
root task). It. is important that the 80186 hardware be
initialized before iRMX 86 operation is begun, since
some of the resources addressed by the 80186 system
may not be initialized properly by iRMX 86 System if
the initialization is done in the reverse manner.
8086
80186
FFFF:O
Figure 73.iRMX-S6 Initialization with
SOS6 & S01S6
9.3
Instruction Execution Differences
Between the 8086 and 80186
There are a few instruction execution differences between the 8086 and the 80186. These differences are:
Initialization for iRMX'" 86 System
Using the iRMX 86 operating system with the80186 requires an external 8259A and an external 8253/4 or al'ternatively an external 80130 OSF component. These
are required because the operating system is interrupt
driven, and expects the interrupt control1er and timers to
have the register moc;leI of these external devices. This
3-310
Undefined Opcodes:
When the opcodes 63H,64H,65H,66H,67H,FIH,
FEH XXlIlXXXB arid FFH XXlllXXXB
are executed, the 80186 will exeCJlte an illegal instruction exception, interrupt type 6. The 8086
will ignore the opcode.
OFH opcode:
When the opcode OFH is encountered, the 8086
will execute a pop CS, while the 80186 will execute an illegal instruction exception, interrupt
type 6.
Word Write at Offset FFFFH:
'When a word write is performed at offset
FFFFH in a segment, the 8086 will write one
byte at offset FFFFH, and the other at offset 0,
while the 80186 will write one byte at offset
AFN-21 0973
inter
AP-186
FFFFH, and the other at offset 10000H (one
byte beyond the end of the segment). One byte
segment underflow will also occur (on the 80186)
if a stack PUSH is executed and the Stack Pointer contains the value 1.
by 1 to include 8000H and 80H. These numbers
represent the most negative numbers representable using 2's complement arithmetic (equaling
-32768 and -128 in decimal, respectively).
ESC Opcode:
Shift/Rotate by Value Greater Then 31:
The 80186 may be programmed to cause an interrupt type 7 whenever an ESCape instruction
(used for co-processors like the 8087) is executed. The 8086 has no such provision. Before the
80186 performs this trap, it must be programmed to do so.
Before the 80186 performs a shift or rotate by a
value (either in the CL register, or by an immediate value) it ANDs the value with lFH, limiting
the number of bits rotated to less than 32. The
8086 does not do this.
LOCK prefix:
The 8086 activates its LOCK signal immediately
after executing the LOCK prefix. The 80186
does not activate the LOCK signal until the processor is ready to begin the data cyCles associated
with the LOCKed instruction.
Interrupted SJring Move Instructions:
If an 8086 is interrupted during the execution of·
a repeated string move instruction, the return
value it will push on the stack will point to the
last prefix instruction before the string move instruction. If the instruction had more than one
prefix (e.g., a segment override prefix in addition
to the repeat prefix), it will not be re-executed
upon returning from the interrupt. The 80186
will push the value of the first prefix to the repeated instruction, so long as prefixes are not repeated, allowing the string instruction to
properly resume.
Conditions causing divide error with an integer
divide:
The 8086 will cause a divide error whenever the
absolute value of the quotient is greater then
7FFFH (for word operations) or if the absolute
value of the quotient is greater than 7FH (for
byte operations). The 80186 has expanded the
range of negative numbers allowed as a quotient
These differences can be used to determine whether the
program is being executed on an 8086 or an 80186.
Probably the safest execution difference to use for this
purpose is the difference in multiple bit shifts. For example, if a multiple bit shift is programmed where the shift
count (stored in the CL register!) is 33, the 8086 will
shift the vafue 33 bits, whereas the 80186 will shift it
only a single bit.
.
In addition to the instruction execution differences noted above, the 80186 includes a number of new instruction types, which simplify assembly language
programming of the processor, and enhance the performance of ·higher level languages running on the processor. These new instructions are covered in depth in the
8086/80186 users manual and in appendix H of this
note.
10.
CONCLUSIONS
The 80186 is a glittering example of state-of-the art integrated circuit technology applied to make the job of
the microprocessor system designer simpler and faster.
Because many of the required peripherals and their interfaces have been cast in silicon, and because of the
timing and drive latitudes provided by the part, the designer is free to concentrate on other issues of system design. As a result, systems designed around the 80186
allow applications where no other processor has been
able to provide the necessary performance at a comparable size or cost.
3-311
AFN-21 0973
APPENDIX A . . . . . . . . . . . . . . ..
APPENDIX B . . . . . . . . . . . . . . ..
APPENDIX C· . . . . . . . . . . . . . . ..
APPENDIX D . . . . . . . . . . . . . . ..
APPENDIX E . . . . . . . . . . . . . . ..
APPENDIX F .. . . . . . . .. . . . . ..
APPENDIX G . . . . . . . . . . . . . . ..
APPENDIX H . . . . . . . . . . . . . . ..
APPENDIX I . . . . . . . . . ... . . . . ..
)
3-312
58
60
61
64
68
70
72
76
78
AP-186
APPENDIX A:
BLOCK
PERIPHERAL CONTROL
All the integrated peripherals within the 80186 microprocessor are controlled by sets of registers contained
within an integrated peripheral control block. The registers are physically located within the peripheral devices
they control, but are addressed as a single block of registers. This set of registers fills 256 contiguous bytes and
can be located begjnning on any 256 byte boundary of
the 80186 memory or I/O space. A map of these registers is shown in Figure A-I.
A.1
Setting the Base Location of the
Peripheral Control Block
In addition to the control registers for each of the integrated 80186 peripheral devices, the peripheral control
block contains the peripheral control block relocation
register. This register allows the peripheral control block
to be re-Iocated on any 256 byte boundary within the
processor's memory or I/O space. Figure A-2 shows the
layout of this register.
This register is located at offset FEH within the peripheral control block. Since it is itself contained within the
Pllripheral control block, any time the location of the peripheral control block is moved, the location of the relocation register will also move.
In addition to the peripheral control block relocation information, the relocation register contains two additional bits. One is used to set the interrupt controller into
iRMX86 compatibility mode. The other is used to force
the processor to trap whenever an ESCape (coprocessor)
instruction is encountered.
OFFSET
Relocation Register
FEH
DAH
DMA Descriptors Channel 1
DOH
CAH
DMA Descriptors Channel 0
COH
A8H
Chip-Select Control Registers
AOH
66H
Timer 2 Control Registers
60H
SEH
Timer 1 Control Registers
S8H
56H
Timer 0 Control Registers
SOH
Interrupt Controller Registers
3EH
20H.
Figure A-1. 80186 -Integrated Peripheral Control Block
3-313
AFN-21 0973
AP-186
11 . 10
9
OFFSET: FEH
8
7
6
5
4
3
2
o
Relocation Address "'its R1Q-R8
ET
MilO
RMX
= ESC Trap I No ESC Trap (1/0) ,
= Register block located In Memory 1110 Space (1/0)
= Master Interrupt Controller mode I IRMX compatible
Interrupt Controller mode (0/1)
Figure A-2. 80186 Relocation
Because the relocation register is containeQ within the
peripheral control block, upon reset the relocation register is automatically programmed with the value 20FFH.
This means that the peripheral control block will be located at the very top (FFOOH to FFFFH) of I/O space.
Thus, after reset the relocation register will be located at
word location FFFEH in I/O space.
If the user wished to locate the peripheral control block
starting at memory location 10000H he would program
the peripheral control register with the value II OOH. By
doing this, he would move all registers within the integrated peripheral control block to memory locations
10000H to 100FFH. Note that since the relocation register is contained within the peripheral control block, it
too would move to word location 100FEH in memory
space.
A.2
Peripheral Control Block Registers'
Each of the integrated peripherals' control and status
registers are located at a fixed location above the programmed base location ,of the peripheral Control block.
There are many locations within the peripheral control
block which are not assigned to any peripheral. If a write
is made to any of these locations, the bus cycle will be
run, but the value will not be stored in any internallocation. This means that if a subsequ~nt read is made to the
same location, the value written will not be read back.
The processor will run an external bus cycle for any
memory or I/O cycle which accesses a location within
the integrated control' block. This means that the address, data, and control information will be driven on the
80186 external pins just as if a "normal" bus cycle had
. been run. Any information returned by an external de~
vice will be ignored, however, even if the access was to a
location which does not correspond to any of the inte-
~egl8ter
Layout
grated peripheral control registers. The above is also
true for the 80188, except that the word access made to
theintegrated registers will be performed in a single bus
cycle, with only the lower 8 bits of data being driven by
the write cycle (since the upper 8 bits of data are nonexistant on the external data bus!)
The processor internally generates a ready signal when~
ever any of the integrated peripherals are accessed; thus
any external ready signals are ignored whenever an access is made to any location within the integrated peripheral register control block. This ready will also be
returned if an access is made to a location within the 256
byte area of the periperal control block which does not
correspond to any integrated peripheral control register.
The processor will insert 0 wait states to any access within the integrated peripheral control block except for accesses to the timer registers. ANY access to the timer
control and counting registers will incur I wait state.
This wait state is required to properly multiplex processor and counter element accesses to the timer control
registers. '
All accesses made to the integrated peripheral control
block must be WORP accesses. Any write to the integrated registers will modify all, 16 bits of the register,
whether the opcode specified a byte write or a word
write. A byte read from an even location should cause no
problems, but the data returned when a byte read is performed from an odd address within the peripheral control block is undefined. This is true both for the 80186
AND the 80188. As stated above, even though the
80188 has an external 8 bit data bus, internally it is still
a 16 bit machi'ne. Thus, the word accesses performed to
the integrated registers by the 80188 will each occur in a
single bus cycle with only the lower 8 bits of data being
driven on the external data bus (on a write).
3-314
AFN-21 0973
AP·186
APPENDIX B: 80186 SYNCHRONIZATION
INFORMATION
STROBE
INPUT
Many input signals to the 80186 are asynchronous, that
is, a specified set up or hold time is not required to insure
proper functioning of the device. Associated with each of
these inputs is a synchronizer which samples this external asynchronous signal, and synchronizes it to the internal 80186 clock.
I
--~S~EY.~-u~p~n~M~E-!·HOLD TIME
m
I
ACTUAL SAMPLING INSTANT
INVALID _ _ _- - IIII
~
INPUT
B.1
Why Synchronizers Are Required
Every data latch requires a certain set up and hold time
in order to operate properly. At a certain window within
the specified set up and hold time, the part will actually
try to latch the data. If the input makes a transition
within this window, the output will not attain a stable
state within the given output delay time. The size of this
sampling window is typically much smaller than the actual window specified by the data sheet, however part to
part variation could move this window around within the
specified window in the data sheet.
Even if the input to a data latch makes a transition while
a data latch is attempting to latch this input, the output
of the latch will attain a stable state after a certain
amount of time, typically much longer than the normal
strobe to output delay time. Figure B-1 shows a normal
input to output strobed transition and one in which the
input signal makes a transition during the latch's sample
window. In order to synchronize an asynchronous signal,
all one needs to do is to sample the signal into one data
latch, wait a certain amount of time, then latch it into a
second data latch. Since the time between the strobe into
the first data latch and the strobe into the second data
latch allows the first data latch to attain a steady state
(or to resolve the asynchronous signal), the second data
latch will be presented with an input signal which satisfies any set up and hold time requirements it may have.
Thus, the output of this second latch is a synchronous
signal with respect to its strobe input.
A synchronization failure can occur if the synchronizer
fails to resolve the asynchronous transition within the
time between the two latch's strobe signals. The rate of
failure is determined by the actual size of the sampling
RESPONSE - - - - - - , . RESOLUTION TIME .,
VALID~
INPUT
RESPONSE
-------...11
Figure B-1. Valid & Invalid Latch Input
Transitions & Responses
window of the data latch, and by the amount of time between the strobe signals of the two latches. Obviously, as
the sampling window gets smaller, the number of times
an asynchronous transition will occur during the sampling window will drop. In addition, however, a smaller
sampling window is also indicative of a faster resolution
time for an input transition which manages to fall within
the sampling window.
B.2
80186 Synchronizers
The 80186 contains synchronizers on the RES,
TEST, TmrInO-l, DRQO-l, NMI, INTO-3, ARDY, and
HOLD input lines. Each of these synchronizers use the
two stage synchronization technique described above
(with some minor modifications for the ARDY line, see
section 3.1.6). The sampling window of the latches is designed to be in the tens of pico-seconds, and should allow
operation of the synchronizers with a mean time between failures of over 30 years assuming continuous
operation.
AFN-21 0973
AP-186
APPENDIX C:
80186 EXAMPLE DMA INTERFACE CODE
$modl86
name
This file contains an example procedure which initializes the 80186 DMA
controller to perform the DMA transfers between the 80186 system the the
8272 Floppy Disk Controller (FDC). It assumes that the 80186
peripheral control block has not been moved from its reset location.'
argl
arg2
arg3
DMA.FROM_LOWER
, DMA.FROM_UPPER
DMA.TO_LOWER
DMA.TO_UPPER
DMA.COUNT .
DMA.CONTROL
DMA.TO_DISK..CONTROL
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
word ptr [BP
word ptr [BP
word ptr [BP
OFFCOh
OFFC2h
OFFC4h
OFFC6h
OFFC8h
OFFCAh
01486h
DMA.FROM.DISK..CONTROLequ
OA046h
FDCDMA
FDCJ)ATA
FDCBTATljS
equ
equ
equ
6B8h
688h
680h
cgroup
code
group
code
segment
public
seLdma..
assume cs:cgroup
+ 4]
+ 6]
+ 8]
DMA register locations
destination synchronization
source to memory, incremertted
destination to I/O
no .terminal count
byte transfers
source synchronization
source to I/O
destination to memory, incr
no terminal count
byte transfers
FDC DMA address
FDC data register
FDC status register
public 'code'
seLdma (offset,to) programs the DMA channel to point one side to the
disk DMA address, and the other to memory pointed to by ds:offset. If
'to' = 0 then will be a transfer from disk to memory; if
'to' = 1 then will be a transfer from memory to disk. The parameters to
the routine are passed on the stack.
seLdma..
proc
enter
'push
push
push
test
near
0,0
AX
BX
DX
arg2,i
set stack addressability
save registers used
check to see direction of
transfer
jz
from..disk
performing a transfer from memory to the disk controller
mov
rol
AX,DS
AX,4
get the segment value
gen the upper 4 bits of the
physical address in the lower 4
bits of the register
3-316
AFN-21 0973
II"nf_l®
1'eI .
AP-188
mov
mov
out
and
BX,AX
DX,DMA.FROM.UPPER
DX,AX
AX,OFFFOh
add
mov
out
jnc
inc
mov
mov
out
AX,argl
DX,DMA.FROM..LOWER
DX,AX
no_carryj"rom
BX
AX,BX
DX,DMA.FROM_UPPER
DX,AX
mov
mov
out
xor
mov
out
mov
mov
out
pop
pop
pop
leave
ret
AX,FDC_DMA
DX,DMA.TO_LOWER
DX,AX
AX,AX
DX,DMA.TO_UPPER
DX,AX
AX,DMA.TOJ>ISK.CONTROL;
DX,DMA.CONTROL
,.'
DX,AX
DX
BX
AX
save the result ...
prgm the upper 4 bits of the
DMA source register
form the lower 16 bits of the
physical address
add the offset
prgm the lower 16 bits of the
DMA source register
check for carry out of addition
if carry out, then need to adj
the upper 4 bits of the pointer
no_carryj"rom:
from..disk~
prgm the low 16 bits of the DMA
destination register
zero the up 4 bits of the DMA
destination register
prgm the DMA ctl reg
note: DMA may begin immediatly
after this word is output
performing a transfer from the disk to memory
mov
rol
mov
olit
mov
and
add
mov
out
jnc
inc
mov
mov
out
AX,DS
AX,4
DX,DMA.TO_UPPER
DX,AX
BX,AX
AX,OFFFOh
AX,argl
DX,DMA.TO_LOWER
DX,AX
no_carry_to
BX
AX,BX
DX,DMA.TO_UPPER
DX,AX
mov
AX,FDCJ>MA
mov
out
xor
mov
out
mov
mov
DX,DMA.FROM..LOWER
DX,AX
AX,AX
DX,DMA.FROM.UPPER;
DX,AX
AX,DMA.FROMJ>ISK.CONTROL
DX,DMA.CONTROL
no_carry_to:
3-317
AFN-210973
AP-186
seLdma_
code
out
pop
pop
pop
leave
ret
endp
OX,AX
OX
BX
AX
. ends
end
3-318
AFN-21 0973
AP·188
APPENDIX D:
80186
EX.~MPLE
TIMER INTERFACE CODE
$modlS6
name
example.SOlS6.timer.code
this file contains .example SO lS6 timer routines. The first routine
sets up the timer and interrupt controller to cause the timer
to generate an interrupt every 10 milliseconds, and to service
interrupt to implement a real time clock. Timer 2 is used in
this example because no input or output signals are required.
The code example assumes that the peripheral control block has
not been moved from its reset location (FFOO·FFFF in I/O space).
word ptr [BP + 4]
word ptr [BP + 6]
word ptr [BP + S]
19
OFF66h
OFF62h
OFF32h
OFF22h
OFF30h
argl
arg2
arg3
timer.2int
timer.2control .
timer.2malLcti
timer.inLcti
eoLregister
interrupLstat
equ
equ
equ
equ
equ
equ
equ
equ
equ
data
msec_
hour_
minute..
second..
data
segment
public
db
db
db
db
ends
cgroup
dgroup
group
group
code
segment
public
seUime.
assume cs:code,ds:dgroup
timer 2 has vector type 19
i'lterrupt controller regs
public 'data'
hour.,minute.,second.,msec..
?
?
?
?
code
data
public 'code'
seuime(hour,minute,second) sets the time variables, initializes the
SO lS6 timer2 to provide interrupts every 10 milliseconds, and
programs the interrupt vector for timer 2
;
seLtime.
proc
enter
push
push
push
push
AX
OX
SI
OS
xor
AX,AX
mov
OS,AX
mov
S1,4 * timer2int
near
0,0
set stack addressability
save registers used
set the interrupt vector
the timers have unique
interrupt
vectors even though they share
the same control register
3-319
AFN·21 0973
AP-186
seUime.
timer2Jnterrupuoutine
mov
inc
inc
mov
pop
DS: [SI] ,offset timer.2Jnterrupuoutine
SI
SI
DS:[SI],CS
DS
mov
mov
mov
mov
mov
mov
mov
AX,argi
hour.,AL
AX,arg2
minute.,AL
AX,arg3
seconci,AL
msec.,O
set the time values
mov
mov
DX,timer2.rnalLcti
AX,2oo00
set the max count value
10 ms / 500 ns (timer 2 counts
at 1/4 the CPU clock rate)
out
mov
mov
DX,AX
D X,timer2.con trol
AX, 111 000000000000 1b
out
DX,AX
mov
mov
DX,timer.inLcti
AX,OOOOb
out
sti
DX,AX
pop
pop
pop
leave
ret
endp
SI
DX
AX
proc
push
push
far
AX
DX
cmp
jae
inc
jmp
msec.,99
bump.second
msec. I
resetinLcti
see if one second has passed
if above or equal. ..
mov
cmp
jae
inc
jmp
msec.,O
second.,59
bump.minute
second.
resetinLcti
reset millisecond
see if one minute has passed
mov
cmp
jae
inc
jmp
second.,O
minute.,59
bump.hour
minute.
resetinLcti
set the control word
enable counting
generate interrupts on TC
continuous counting
set up the interrupt controller
unmask interrupts
highest priority interrupt
enable processor interrupts
bump.second:
bump.minute:
3-320.
see if one hour has passed
AFN·210973
AP-186
bump_hour:
inc
jmp
minute_,O
hour_,12
reseLhour
hour_
reseLinLcti
mov
hour_,1
mov
mov
out
OX,eoLregister
AX,8000h
OX,AX
pop
pop
iret
endp
ends
end
OX
AX
mov
cmp
jae
see if 12 hours have passed
reseLhour:
reseLinLctl:
timer2jnterrupuoutine
code
non-specific end of interrupt
$modl86
name
this file contains example 80186 timer routines. The second routine
sets up the timer as a baud rate generator. In this mode,
Timer 1 is used to continually output pulses with a period of
6.5 usec for use with a serial controller at 9600 baud
programmed in divide by 16 mode (the actual period required
for 9600 baud is 6.51 usec). This assumes that the 80186 is
running at 8 MHz. The code example also assumes that the
peripheral control block has not been moved from its reset
location (FFOO-FFFF in I/O space).
timer Lcontrol
timer LmalLcnt
equ
equ
OFFSEh
OFFSAh
code
segment
assume
cs:code
public 'code'
seLbaudO initializes the 80186 timer! as a baud rate generator for
a serial port running at 9600 baud
seLbaud.
proc
push
push
near
AX
OX
mov
mov
out
mov
mov
OX,timerl..malLcnt
AX,13
OX,AX
OX,timerLcontrol
AX, 11 0000000000000 1b
out
OX,AX
pop
pop
OX
save registers used
set the max count value
SOOns * 13 = 6.5 usee
set the control word
enable counting
no interrupt on TC
continuous counting
,
single max count register
AX
3<-321
AFN-21 0973
AP-186
set-baud..
code
$mod186
name
"ret
endp
ends
end
example.80186_count-code
this file contains example 80186 timer routines. The third routine
sets up the timer as an external event counter. In this mode,
Timer 1 is used to count transitions on its input pin. After
the timer has been set up by the routine, the number of
events counted can be directly read from the timer count
register at location FF58H in I/O space. The timer will
count a maximum of 65535 timer events before wrapping
around to zero. This code example also assumes that the
peripheral control block has not been moved from its reset
location (FFOO-FFFFin I/O space).
;
timer Lcontrol
timer LmalLcnt
timer LcnLreg
equ
equ
equ
code
segment
assume cs:code
OFF5Eh
'OFF5Ah
' OFF58H
public 'code'
set-countO initializes the 80186 timerl as an Civent counter
set-count-
set-countcode
proc
push
push
near
AX
OX
mov
mov,
OX,timerLmalLcnt
AX,O
out
mov
mov
OX,AX
OX,timerLcontrol
AX,II 000000000001 0 I b
out
DX,AX
xor
mov
out
AX,AX
OX,timerLcnueg
OX,AX
pop
pop
ret
OX
AX
save registers used
set the max count value
allows the timer to count
all the way (0 FFFFH
set the control word
enable counting
no interrupt on TC
continuous counting
single max count register
external clocking
zero AX
and zero the count in the timer
count register
endp
ends
end
3-322
AFN-21 0973
AP-186
APPENDIX E: 80186 EXAMPLE
INTERRUPT CONTROLLER INTERFACE
CODE
$mod186
name
,
example..80 186interrupLcode
This routine configures the 80186 interrupt controller to provide
two cascaded interrupt inputs (through an external 8259A
interrupt controller on pins INTO/INT2) and two direct
interrupt inputs (on pins INTI and INTJ). The default priority
levels are used. Because of this, tlie priority level programmed
into the control register is set the Ill, the level all
interrupts are programmed to at reset.
intO.control
inLm~sk
code
setinL
setinL
code
equ
equ
OFF38H
OFF28H
segment
assume
proc
push
push
CS:code
near
OX
AX
mov
AX,OIOOIIIB
mov
out
OX,intO.control
OX,AX
mov
AX,01001101B
mov
out
pop
pop
ret
endp
ends
end
OX,inLmask
OX'AX
AX
OX
public 'code'
cascade mode
interrupt unmasked
; now unmask the other external
; interrupts
$mod186
name
example..80 186interrupLcode
,
/ ; This routine configures. the 80186 interrupt controller into iRMX 86
mode. This code does not initialize any of the 80186
integrated peripheral control registers, nor does it initi~lize
the external 8259A or 80130 interrupt controller.
relocation..reg
equ
OFFFEH
segment
assume
proc
push
push
CS:code
near
OX
AX
mov
in
or
out
OX,relocation..reg
AX,OX
AX,OlooOOooooOOOOOOB
OX,AX
,
code
seLrmlL
public 'code'
3-323
read old contents of register
set the RMX mode bit
AFN.21 0973
seumx.
code
pop
pop
ret
endp
ends
end
AX
OX
3-324
AFN-210973
AP·186
A~PENDIX F: 80186/8086 EXAMPLE
SySTEM INITIALIZATION CODE
name
exampleJ!O I 86.systemJnit
This file contains a system initialization routine for the 80186
or the 8086. The code determines whether it is running on
an 80186 or an 8086, and if it is running on an 80186, it
initializes the integrated chip select registers.
restart
segment at
OFFFFh
This is the processor reset address at OFFFFOH
restart
init..hw
,
org
jmp
ends
0
far ptr initialize
extrn
monitor:far
segment at
assume CS:init..hw
OFFFOh
This segment initializes the chip selects. It must be located in the
\
top IK to insure that the ROM remains selected in the 80186
system until the proper size of the select area can be programmed.
UMCS-feg
LMCS-feg
PACS-fcg
MPCS-1"eg
UMCS_value
LMCs..vaiue
PACS_value
MPCS_value
equ
equ
equ
equ
equ
equ
equ
equ
OFFAOH
OFFA2H
OFFA4H
OFFA8H
OF800H
07F8H
72H
OBAH
initialize
proc
mov
mov
shr
test
jz
far
AX,2
CL,33
AX,CL
AX,I
noL80186
mov
mov
out
DX,UMCS-feg
AX,UMCs..value
DX,AX
progralll the UMCS register
mov
mov
out
DX,LMCS-feg
AX,LMcs..value
DX,AX
program the LMCS register
mov
DX,PACS-feg
set up the peripheral chip
chip select register locations
64K, no wait states
32K, no wait states
peripheral base at 4OOH, 2 1(I's
PCS5 and 6 supplies,
peripherals in I/O space
determine if this is an
8086 or an 80186 (checks
to see if the multiple bit
shift value was ANDed)
selects (note the mid-range
memory chip selects are not
needed in this system, and
are thus not initialized
mov
out
AX,PACs..value
DX,AX
3·325
AFN-210973
AI~·186
moy
moy
out
DX,MPC8.reg
AX,MPCS_value
DX,AX
Now that the chip selects are all set up, the main program of the
cqmputer may be ~ecuted.
noL80186:
initialize
iniLhw
• 'If
jmp
endp
ends
end
far ptr monitor
3~326.
. AFN-21 0973
AP·186
APPENDIX G: 80186 WAIT STATE
PERFORMANCE
Because the 80186 contains seperate bus interface and
execution units, the actual performance of the processor
will not degrade at a constant rate as wait states are added to the memory cycle time from the processor. The actual rate of performace degradation will depend on the
type and mix of instructions actually encountered in the
user's program.
Shown below are two 80186 assembly language programs, and the actual execution time for the two programs as wait states are added to the memory system of
the processor. These programs show the two extremes to
which wait states will or will not effect system performance as wait states are introduced.
Program 1 is very memory intensive. It performs many
memory reads and writes using the more extensive memory addressing modes of the processor (which also take a
greater number of bytes in the opcode for the instruction). As a result, the execution unit must constantly
wait for the bus interface unit to fetch and perform the
memory cycles to allow it to continue. Thus, the execution time of this type of routine will grow quickly as wait
states are added, since the execution time is almost totally limited to the speed at which the processor can run bus
cycles.
access the opcode bytes immediatly upon request, dead
clock cycles will be inserted in which the execution unit
will remain idle, thus increasing the number of clock cycles required to complete execution of the program.
On the other hand, program 2 is more CPU intensive. It
performs many integer multiplies, during which time
the bus interface unit can fill up the instruction prefetch queue in parallel with the execution unit performing the mUltiply. In this program, the bus interface unit
can perform bus operations faster than the execution
unit actually requires them to be run. In this case, the
performance degradation is much less as wait states are
added to the memory interface. The execution time of
this program is closer to the number of clock cycles calculated by adding the number of cycles per instruction
because the execution unit does not have to wait for the
bus interface unit to place an opcode byte in the prefetch
queue as often. Thus, fewer clock cycles are wasted by
the execution unit laying idle for want of instructions.
Table G-l lists the execution times measured for these
two programs as wait states were introduced with the
80186 running at 8 MHz.
Note also that this program execution times calculated
by merely su~ming up the number of clock cycles given
in the data sheet will typically be less than the actual
number of clock cycles actually required to run the program. This is because the numbers quoted in the data
sheet assume that the opcode bytes have been prefetched
and reside in the 80186 prefetch queue for immediate
access by the execution unit. If the execution unit cannot
Smod186
name
Table G-1
# of
Wait
States
0
1
2
3
Program 1
Exec
Time
Perf
(~sec)
Degr
505
595
669
752
18%
12%
12%
Program 2
Exec
Time
Perf
Degr
(~sec)
294
311
337
347
6%
8%
3%
example_waiLstate_performance
This file contains two programs which demonstrate the 80186 performance
degradation as wait states are inserted. Program 1 performs a
transformation between two types of characters sets, then copies
the transformed characters back to the original buffer (which is 64
bytes long. Program 2 performs the same type of transformation, however
instead of performing a table lookup, it multiplies each number in the
original 32 word buffer by a constant (3, note the use of the integer
immediate multiply instruction). Program "nothing" is used to measUre
the call and return times from the driver program only.
cgroup
dgroup
data
group
code
data
group
segment
public 'data'
3-327
AFN-21 0973
AP-186
Ltable
Lstring
m..array
data
db
db
dw
ends
256 dup (?)
64 dup (?)
32 dup (?)
code
segment
assume
public
proc
push
push
push
push
public 'code'
eS:cgroup,DS:dgroup
benclLl,benclL2,nothing., waiLstate-.seLtimer_
near
SI
; save registers used
ex
ax
AX
mov
mov
mov
eX,64
SI,O
BH,O
translate 64 bytes
mov
mov
mov
inc
loop
BL,Lstring[SI]
AL,Ltable[BX]
Lstring[SI],AL
SI
loop_back
get the byte
translate byte
and store it
increment index
do the next byte
pop
pop
pop
pop
ret
endp,
AX
ax
ex
SI
proc
push
push
push
near
AX
SI
ex
mov
mov
eX,32
SI,offset m..array
multiply 32 numbers
imul
mov
inc
inc
loop
AX,word ptr [SI],3
word ptr [SI],AX
SI
SI
loop_back.2
immediate multiply
pop
pop
pop
ret
endp
ex
SI
AX
bench:. 1
,{
loop_back:
benclL!
benclL2
save registers used
loop_back.2:
benclL2.
3-328
AFN-?10973
AP-186
nothing..
nothing..
proc
ret
endp
near
wait.state(n) sets the -80186 LMCS register to the number of wait states
(0 to 3) indicated by the parameter n (which is passed on the stack).
No other bits of the LMCS register are modified.
wait.state_
proc
enter
push
push
push
near
0,0
AX
BX
DX
mov
mov
BX,word ptr [BP
DX,OFFA2h
in
AX,DX
and
and
or
out
AX,OFFFCh
BX,3
AX,BX
DX,AX
pop
pop
pop
leave
ret
endp
DX
BX
AX
set up stack frame
save registers used
+ 4]
get argument
get current LMCS register
contents
waiLstate..
and off existing ready bits
insure ws count is good
adjust the ready bits
and write to LMCS
tear down stack frame
seLtimerO initializes the 80186 timers to count microseconds. Timer 2
is set up as a prescaler to timer 0, the microsecond count can be read
directly out of the timer 0 count register at location FF50H in I/O
space.
seLtimer_
proc
push
push
near
AX
DX
mov
mov
out
DX,Off66h
AX,4000h
DX,AX
stop timer 2
mov
mov
out
DX,Off50h
AX,O
DX,AX
clear timer 0 count
mov
mov
out
DX,Off52h
' AX,O
DX,AX
3-329
timer 0 counts up to 65535
AFN-21 0973
seLtimer_
code
mov
mov
out
OX,Off56h
AX,OcOO9h
OX,AX
enable timer 0
mov
mov
out
OX,Off60h
AX,O
OX,AX
clear timer 2 count
mov
mov
out
OX,Off62h
AX,2
OX,AX
set maximum count of timer 2
mov
mov
out
OX,Off66h
AX,OcOOlh
OX,AX
re-enable timer 2
pop
pop
ret
endp
ends
end
OX
AX
3-330
AFN-21 0973
AP-186
APPENDIX H: 80186 NEW INSTRUCTIONS
The 80186 performs many additional instructions to
those of the 8086. These instructions appear shaded in
the instruction set summary at the back of the 80186
data sheet. This appendix explains the operation of these
new instruclions. In order to use these new instructions
with the 8086/186 assembler, the "$modI86" switch
must be given to the assembler. This can be done by placing the line: "$modI86" at the beginning of the assembly language file.
PUSH immediate
This instruction allows immediate data to be pushed
onto the.processor stack. The data can be either an immediate byte or an immediate word. If the data is a byte,
it will be sign extended to a word before it is pushed onto
the stack (since all stack operations are word
operations).
PUSHA,POPA
These instructions allow all of the general purpose
80186 registers to be saved on the stack, or restored from
the stack. The registers saved by this instruction (in the
order they are pushed onto the stack) are AX, CX, DX,
BX, SP, BP, SI, and DI. The SP v.alue pushed onto the
stack is the value of the register before the first PUSH
(AX) is performed; the value popped for the SP register
is ignored.
This instruction does not save any of the segment registers (CS, DS, SS, ES), the instruction pointer (IP), the
flag register, 'or any of the integrated peripheral
registers.
lMUL by an immediate value
This instruction allows a value to be multiplied by an immediate value. The result of this operation is 16 bits
long. One operand for thi:> instruction is obtained using
one of the 80186 addressing modes (meaning it can be in
a register or in memory). The immediate value can be
either a byte or a word, but will be sign extended if it is a
byte. The 16-bit result of the multiplication can be
placed in any of the 80186 general purpose or pointer
registers.
This instruction requires three operands: the register in
which the result is to be plac~d, the immediate value,
and the second operand. Again, this second operand can
be anyofthe 80186 general purpose registers or a specified memory location.
.
immediate value. This is different from the 8086, where
only a single bit shift can be performed, or a multiple
shift can be performed where the number of bits to be
shifted is specified in the CL register.
All of the shift/rotate instructiohs of the 80186 allpw
the number of bits shifted to be specified by an immediate value. Like all multiple bit shift operations performed by the 80186, the number of bits shifted is the
number of bits specified modulus 32 (i.e. the maximum
number of bits shifted by the 80186 multiple bit shifts is
31).
These instructions require two operands: the operand to
be shifted (which may be a register or a memory location
specified by any of the 80186 addressing modes) and the
number of bits to be shifted.
block input/output
The 80186 adds two new input/output instructions: INS
and OUTS. These instructions perform block input or
output operations. They operate similarly to the string
move instructions of the processor.
The INS instruction performs block input from an I/O
port to memory. The I/O address is specified by the DX.
register; the memory location is pointed to by the DI register. After the operation is performed, the DI register is
adjusted by 1 (if a byte input is specified) or by 2 (if a
word input is specified). The adjustment is either an increment or a decrement, as determined by the Direction
bit in the flag register of the processor. The ES segment
register is used for memory addressing, and cannot be
overridden. When preceeded by a REPeat prefix, this instruction allows blocks of data to be moved from an I/O
address to a block of memory Note that the I/O address
in the DX register is not modified by this operation.
The OUTS instruction performs block output from
memory to an I/O port. The I/O address is specified by
the DX register; the memory location is pointed to by the
SI register. After the operation is performed, the SI register is adjusted by 1 (if a byte output is specified) or by
2 (if a word output is specified). The adjustment is either
an increment or a decrement, as determined by the Direction bit in the flag register of the processor. The DS
segment register is used for memory addressing, but can
be overridden by using a segment override prefix. When
preceeded by a REPeat prefix, this instruction allows
blocks of data to be moved from a block of memory to an
I/O address. Again note that the I/O address in the DX
register is not modified by this operation.
shifts/rotates by an immediate value
The 80186 can perform multiple bit shifts or rotates
where the number of bits to be shifted is specified by an
3-331
Like the string move instruction, these two instructions
require two operands to specify whether word or byte operations are to take place. Additionally, this determination can be supplied by the mnemonic itself by adding a
"B" or "w" to the basic mnemonic, for example: .
INSB
; perform byte input
REP,OUTSW ; perform word. block output
AFN-21 0973
AP.188
\
\
temp2:= level-I;
do while temp2 > 0
. BOUND'
The 80186 supplies a BOUND instruction to facilitate
bound checking of arrays. In this instruction, the ca:Jculated index into the:array is placed in one of the general
purpose registers of the 80186. Located in two adjacent
word memory locations are the lower and upper bounds
for the array index. The BOUND instruction compares
the register contents to the memory locations, and if the
value in the. register is not between the values in the
memory locations, an interrupt type 5 is generated. The
comparisons performed are SIGNED comparisons. A
register value equal to either the upper bound or the lower bound will not cause an interrupt.
This instruction requires two.arguments: the register in
which the calculated array index is placed, and the word
memory location which contains the lower bound of the
array (which can be specified by anyofthe 80186 memory addressing modes). The memory location containing
the upper bound of the array must follow immediatly the
memory location containing the lower bound of the
array.
ENTER and LEAVE
The 80186 contains two instructions which are used to
build and tear down stack frames of higher level, block
structured languages. The instruction used to build
these stack frames is the ENTER instruction. The algorithm for this instruction is:
PUSH BP
/*
save the previous
pointer */
iflevel = 0 then
BP:= SP;
else
tempi := SP; /* save current frame
*/
frame
pointer
.
copy down previous
frame*/
/* pointers */
/*
level
BP:= BP- 2;
PUSH [BP];
BP:= tempi;
PUSHBP;
1*
frame
1* in the save area */
SP:= SP - disp;
1*
stack
.
put current level
pointer "'/
create space on the
for */
/* local variables" /
Figure H-I shows the layout of the stack before and
after this operation.
This instruction requires two operands: the first value
(disp) specifies the number of bytes the local variables of
this routine require. This is an unsigned value and can be
as large as 65535. The second value (level) is an unsigned value which specifies the level of the procedure. It
can be as great as 255.
The 80186 includes the LEAVE instruction to tear down
stack frames built up by the ENTER instruction. As can
be seen from the layout of the stack left by the ENTER
instruction, this involves only moving the centents of the
BP register to the SP register, and popping the old BP
value from the stack.
Neither the ENTER nor the LEAVE instructions save
any of the 80186 general purpose registers. If they must
be saved, this must be done in addition to the ENTER
and the LEAVE. In addition, the LEAVE instruction
does not perform a return from a subroutine. If this is
desired, the LEAVE instruction must be explicitly followed by the RET instruction.
.
?
BP~
AFTER
BEFORE
SPBP - - - - '
,
OLDBP
I-
OLD FRAME
. PTRS.
CURRENT FRAME
PTR'
I--
LOCAL
SP-
Figure
1-1-1.
VARIABLE
AREA
ENTER Instruction Stack Frame
a:-332
AFN-21 0973
AP-186
APPENDIX I: 80186/80188 DIFFERENCES
The DMA controlle£ of the 80188 only performs
byte transfers. The B/W bit in the DMA control
word is ignored.
The 80188 is exactly like the 801 86, except it has an 8 bit
external bus. It shares the same execution unit, timers,
peripheral control block, interrupt controller, chip select, and DMA logic. The differences between the two
caused by the narrower data bus are: •
The 80188 has a 4 byte prefetch queue, rather than
the 6 byte prefetch queue present on the 80186. The
reason for this is since the 80188 fetches opcodesone
byte at a time, the number of bus cy,=
----'\
T
DE
8286
DATA
TRANSCEIVER
(2)
"HE
eSOH
}dl 1 TT II
CSOL
WE 00
2142 RAM (4)
(2'
1Kx8
CE
OE
2716·2 PROM (2)
es
lIOWli
MCS·80
PERIPHERAL
(2)
I
lKxB
2K )( 8
I
2K x 8
Figure 4b. Maximum Mode iAPX 86/10 Typical Configuration
3-340
AFN·01497D
intJ
IAPX 86/10
5tatus bits 53 through 57 are multiplexed with highorder address bits and the BHE signal, and are therefore
valid ,during T2 through T4' 53 and 54 indicate which
segment register (see Instruction 5et description) was
used for this bus cycle in forming the address, accord·
ing to the following table:
BUS OPERATION
The 86/10 has a combined address and data bus commonly referred to as a time multiplexed bus. This tech·
nique provides the most' efficient use of pins on the
processor while permitting the use of a standard 40·lead
package. This "local bllS" can be buffered directly and
used throughout the system with address latching pro·
vided on memory and 110 modules. In addition, the bus
can also be demultiplexed at the processor with a single
set of address latches if a standard non-multiplexed bus
is desired for the system.
Each processor bus cycle consists of at least four ClK
cycles. These are referred to as T 10 T2, T3 and T4 (see
Figure 5). The address is emitted from the processor
during T, and data transfer occurs on the bus during T3
and T4' T2 is used primarily for changing the direction of
the bus during read operations. In the event that a "NOT
READY" indication is given by the addressed device,
"Wait" states (T w) are inserted between T3 and T4. Each
inserted "Wait" state is of the same duration as a ClK
cycle. Periods can occur between 8086 bus cycles.
These are referred to as "Idle" states (T I) or inactive ClK
cycles. The processor uses these cycles for internal
housekeeping.
During T, of any bus cycle the ALE (Address latch
Enable) signal is emitted (by either the processor or the
8288 bus controller, depending on the MN/MX strap). At
the trailing edge of this pulse, a valid address and certain status Information for the cycle may be latched.
82
0
0
0
1 (HIGH)
1
1
1
S; So
0
0
1
1
0
0
1
1
83
0
1
0
1
0
1 (HIGH)
1
CHARACTERISTICS
Alternate Data (extra segment)
Stack
Code or None
Data
55 is a reflection of the P5W interrupt enable bit. 56=0 and
57 is a spare status bit.
1/0 ADDRESSING
In the 86/10, I/O operations can address up to a maximum
of 64K I/O byte registers or 32K I/O word registers. The
I/O address appears in the same format as the memory
address on bus lines A'5-Ao. The address lines A19 -A16
are zero in I/O operations. The variable I/O instructions
which use register OX as a pointer have full address capability while the direct I/O instructions directly address one
or two of the 256 1/0 byte locations in page 0 of the I/O
address space.
.
110 ports are addressed in the same manner as memory
5"
5tatus bits ~,
and 52 are used, in maximum mode,
by the bus controller to identify the ,type of bus transac·
tion according to the following table:
o (LOW)
84
o (lOW)
locations. Even addressed bytes are transferred on the
07-00 bus lines and odd addressed bytes on DI5-Da.
Care must be taken to assure that each register within
an 8-bit peripheral located on the lower portion of the
bus be addressed as even.
.
CHARACTERISTICS
Interrupt Acknowledge
1
Read 1/0
0 Write 110
1 , Halt
0 Instruction Fetch
Read Data from Memory
1
0 Write Data to Memory
1
Passive (no bus cycle)
0
3-341
AFN·01497D
iAPX 86/10
,.0-----T,
(4
+ NWAIT):O Tey
T2
T3
-1 •.______
______....
TWAIT
T4
T1 _
(C
+ NwAITJ:: Tey
T2
T3
-------1°1
TWAIT
T4
Cl.k
\~ADDR/
STATUS
-----8,-__D_A_TA_O_U_T_ID_"_-D_~
ADDR/DATA
...J>- ~
__
iiii,iiiii
READY
READY'
WAIT
WAIT
ortii' '
Figure 5. Basic System Timing
3-342
AFN-01497D
inter
IAPX 86/10
EXTERNAL INTERFACE
sequence, which is used to "vector". through the appropriate element to the new interrupt service program
location.
PROCESSOR RESET AND INITIALIZATION
Processor initialization or start up is accomplished with
activation (HIGH) of the RESET pin. The 8086 RESET is
required to be HIGH for greater than 4 ClK cycles. The
8086 will terminate operations on the high-going edge of
RESET and will remain dormant as long as RESET is
HIGH. The low-going transition of RESET triggers an
internal reset sequence for approximately 10 ClK cycles.
After this interval the 8086 operates normally beginning
with the instruction in absolute location FFFFOH (see
Figure3Bl. The details ofthis operation are specified in the
. Instruction Set description of the MCS-86 Family User's
Manual. The RESET input is internally synchronized to the
processor clock. At initialization the HIGH-to-lOW transition of RESET must occur no sooner than 50 I's alter
power-up, to allow complete initialization of the 8086.
NON·MASKABLE INTERRUPT (NMI)
The processor provides a single non-maskable interrupt
pin (NMI) which has higher priority than the maskable interrupt request pin (INTR). A typical use would be to activate a power failure routine. The NMI is edge-triggered
on a lOW-to-HIGH tranSition. The activation of this pin
causes a type 2 interrupt. (See Instruction Set description.)
NMI is required to have a duration in the HIGH state of
greater than two ClK cycles, but is not required to be
synchronized to the clock. Any high-going transition of
NMI is latched on-chip and will be serviced at the end of
the current instruction or between whole moves of a
block-type instruction. Worst case response to NMI
would be for multiply, divide, and variable shift instructions. There is no specification on the occurrence of the
low-going edge; it may occur before, during, or after the
servicing of NMI. Another high-going edge triggers
another response if it occurs after the start of the NMI
procedure. The signal must be free of logical spikes in
general and be free of bounces on the low-going edge to
avoid triggering extraneous responses.
NMI may not be asserted prior to the 2nd ClK cycle following the end of RESET.
INTERRUPT OPERATIONS
Interrupt operations fall into two classes; software or
hardware initiated. The software initiated interrupts and
software aspects of hardware interrupts are specified in
the Instruction Set description. Hardware interrupts can
be ClaSSified as non-maskable or maskable.
MASKABLEINTERRUPTPNT~
The 86/10 provides a single interrupt request input (INTR)
which can be masked internally by software with the
resetting of the interru~t enable FLAG status bit. The
interrupt request signal IS level triggered. It is internally
synchronized during each clock cycle on the high-going
edge of elK. To beresponded to, INTR must be present
(HIGH) during the clock period preceding the end of the
current instruction or the end of a whole move for a
blOCk-type instruction. During the interrupt response
sequence further interrupts are disabled. The enable bit
is reset as part of the response to any interrupt (INTR,
NMI, software interrupt or single-step), although the
Interrupts result in a transfer of control to a new program location. A 256-element table containing address
pointers to the interrupt service program locations
resides in absolute locations 0 through 3FFH (see
Figure 3b), which are reserved for thiS purpose. Each
element in the table is 4 bytes in size and corresponds
to an interrupt "type" An interrupting device supplies
an 8-bit type number, during the interrupt acknowledge
T,
ALE
I
T2
T3
T4
T,
T,
T3
I •
£\'---_--------./ J\'----\
\
INTA
\
ADo-AD,s
JT I \
FLOAT
J
I
i (
r
i
I
J
~>-c::.::.----------------iI
I
/
~
\
\ 'rTYPE VECTOR
Figure 6. Interrupt Acknowledge Sequence
3-343
AFN-014970
IAPX 86/10
FLAGS register which is automatically pushed onto the
stack .reflects the state of the processor prior to the
interrupt. Until the old FLAGS register is restored the
enable bit will be zero unless specifically set by an
Instruction.
During the response sequence (figure 6) the processor
executes two successive (back-to-back) interrupt
acknowledge cycl~s. The 8086 emits the LOCK signal
from T2 of the first bus cycle until T2 of the second. A
local bus "hold" request will not be honored until the
end of the second bus cycle. In the second bus cycle a
byte Is fetched from the external interrupt system (e.g.,
8259A PIC) which identifies the source (type) of the
interrupt. This byte is multiplied by four and used as a
pOinter into the interrupt vector lookup table. An INTR
signal left HIGH will be continually responded to within
the limitations of the enable bit and sample period. The
INTERRUPT RETURN instruction includes a FLAGS pop
which returns the status of the original interrupt enable
bit when it restores the FLAGS.
HALT
When a software "HALT" instruction is executed the
processor Indicates that it is entering the "HALT" state
in one of two ways depending upon which mode is
strapped. In minimum mode, the processor issues one
ALE with no qualifying bus control signals. In Maximum
Mode, the processor issues appropriate HALT status on
S~,So and the 8288 bus controller issues one ALE. The
8086 will not leave the "HALT" state when a local bus
"hold" is entered while in "HALT". In this case, the
processor reissues the HALT indicator. An interrupt
request or RESET will force the 8086 out of the "HALT"
state.
to become active. It must remain active for at least 5
CLK cycles. The WAIT instruction Isre-executed
repeatedly until that time. This activity does not consume bus cycles. The processor remains in an idle state
while waiting. All 8086 drivers go to 3-state OFF if bus
"Hold"is entere". If interrupts are enabled, they may
occur while the processor is waiting. When this occurs
the processor fetches the WAIT instr,uction one extra
time, processes the interrupt, and then re-fetches and
re-executes the WAIT instruction upon returning from
the interrupt.
BASIC SYSTEM TIMING
Typical system configurations for the processor
operating in minimum mode and in maximum mode are
shown in Figures 4a and 4b, respectively. In minimum
mode, the MN/MX pin is strapped to Vee and the processor emits bus control signals in a manner similar to
the 8085. In maximum mode, the MN/MX pin is strapped
to Vss and the processor emits coded status information which the 8288 bus controller uses to generate
MULTIBUS compatible bus control signals. Figure 5 illustrates the signal timing relationships.
AX
AH
AL
ACCUMULATOR
BX
BH
BL
BASE
CX
CH
CL
COUNT
OX
DH
DL
DATA
~~
READ/MODIFY/WRITE (SEMAPHORE)
OPERATIONS VIA LOCK
The LOCK status information is provided by the processor when directly consecutive bus cycles are required
during the execution of an instruction. This provides the
processor with the capability of performing read/modify/
write operations on memory (via the Exchange Register
With Memory instruction, for example) without the
possibility of another system bus master receiving
intervening memory cycles. This is useful in multiprocessor system configurations to accomplish "test
and set lock" operations. The LOCK signal is activated
(forced LOW) in the clock cycle following the one in
which the software "LOCK" prefix instruction is
decoded by the EU. It is deactivated at the end of the
last bus cycle of the instruction following the "LOCK"
prefix instruction. While LOCK is active a request on a
RQ/GT pin will be recorded and then honored at the end
of the LOCK.
EXTERNAL SYNCHRONIZATION VIA TEST
As an alternative to the interrupts and general I/O
capabilities, the 8086 provides a single softwaretestable input known as the TEST signal. At any time the
program may execute a WAIT instruction. If at that time
the TEST signal is inactive (HIGH), pr.ogram execution
becomes susp~nded while the processor waits for TEST
I
-
BASE POINTER
SI
SOURCE INDEX
01
DESTINATION INDEX
I.
FLAGSH
STACK POINTER
BP
I
FLAGS L
I
INSTRUCTION POINTER
STATUS FLAGS
CS
CODE SEGMENT
OS
DATA SEGMENT
SS
STACK SEGMENT
ES
EXTRA SEGMENT
Figure 7. IAPX 86/10 Register Model
SYSTEM TIMING -
MINIMUM SYSTEM
The read cycle begins In T, with the assertion of the
Address Latch Enable (ALE) signal. The trailing (lowgoing) edge of this signal is used to latch the address
information, which is valid on the local bus at this time,
into the 8282/8283 latch. The BHE and Ao signals
address the low, high, or both bytes. From T, to T4 the
M/iO signal indicates a memory or 110 operation. At T2
the address is removed from the local bus and th,e bus
goes to a high impedance state. The read control signal
is also asserted at T2. The read (RD) signal causes the
addressed device to enable its data bus drivers to the
local bus. Some time later valid data will be available on
the bus and the addressed device will drive the READY
line HIGH. When the processor returns the read signal
3-344
AFN·01497D
inter
IAPX 86/10
,to a HIGH level, the addressed device will again 3·state
its bus drivers. If a transceiver (8286/8287) is required to
buffer the 8086 local bus, signals DTiR and DEN are pro·
vided by the 8086.
A write cycle also begins with the assertion of ALE and
the emission of the address. The M/iO signal is again
asserted to indicate a memory or I/O write operation. In
the T2 immediately following the address emission the
processor emits the data to be written into the
addressed location. This data remains valid until the
middle of T4' During T2, T3, and Tw the processor asserts
the write control signal. The write (WR) si'gnal becomes
active at the beginning of T2 as opposed to the read
which is delayed somewhat into T2 to provide time for
the bus to float.
read (AD) signal and the address bus is floated. (See
Figure 6.) In the second of two successive INTA cycles,
a byte of information is read from bus lines 07-00 as
supplied by the interrupt system logic (i.e., 8259A Prior·
ity Interrupt Controller). This byte identifies the source
(type) of the interrupt. It is multiplied by four and used
as a pointer into an interrupt vector lookup table, as
described earlier.
The BHE and Ao signals are used to select the proper
byte(s) of the memoryllO word to be read or written
according to the following table:
BHE
0
0
AD
0
1
1
0
1
1
CHARACTERISTICS
Whole word
Upper byte froml
to odd address
Lower byte froml
to even address
None
I/O ports are addressed in the same manner as memory
location. Even addressed bytes are transferred on the
0 7-0 0 bus lines and odd addressed bytes on D I5-D e.
The basic difference between the interrupt acknowl·
edge cycle and a read cycle is that the interrupt
acknowledge signal (INTA) is asserted in place of the
3-345
BUS TIMING-MEDIUM SIZE SYSTEMS
Formedium size systems the MN/MX pin is connected to
Vss and the 8288 Bus Controller is added to the system as
well as an 828218283 latch for latchi ng the system address,
and a 8286/8287 transceiver to allow for bus loading
greater than the 8086 is capable of han·dling. Signals ALE,
DEN, and DT/R are generated by the 8288 instead of the
processor in this configuration although their timing remains relatively the same. The 8086 status outputs (52, 51'
and So) provide type-of-cycle information and become
8288 inputs. This bus cycle information specifies read
(code, data, or I/O), write (data or I/O), interrupt acknowledge, or software hall. The 8288 thus issues control
signals specifying memory read or write, I/O read or write,
or interrupt acknowledge. The 8288 provides t.wo types of
write strobes, normal and advanced, to be applied as required. The normal write strobes have data valid at the
leading edge of write. The advanced write strobes have
the same timing as read strobes, and hence data isn't valid
at the leading edge of write. The 8286/8287 transceiver
receives the usual T and DE inputs from the 8288's DT/R
and DEN.
The pOinter into the interrupt vector table, which is
passed during the second INTA cycle, can derive from
an 8259A located on either the local bus or the system
bus. If the master 8259A Priority Interrupt Controller is
positioned on the local bus, a TTL 'gate is required to
disable the 828618287 transceiver when reading from the
master 8259A during the interrupt acknowledge
sequence and software "poll".
AF,N-01497D
iAPl,C 86/10
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ......... O·C to 70·C
Storage Temperature ............. , - 65·C to + 150·C
Voltage on Any Pin with
Respect to Ground ............... ; .. - 1.0 to/ + 7V
Power Dissipation ........................ 2.5 Watt
D.C. CHARACTERISTICS
Symbol
"NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
(SOS6: TA = O°C to 70°C, Vcc = 5V ± 10%)
(SOS6-1: TA = O°C to 70°C, Vcc = 5V ± 5%)
(SOS6-2: TA = O°C to 70°C, Vee = SV ± S%)
Parame.er
Min.
Max.
Units
Tesl Conditions
+O.S
V
Vce + O.S
V
0.4S
V
IOL=2.~
V
10H= -400 "A
VIL
Input low Voltage
-0.5
VIH
Input High Voltage
2.0
VOL
Outputiow Voltage
VOH
Output High Voltage
lee
Power Supply Current: SOS6
SOS6-1
SOS6-2
340
360
3S0
Input leakage Current
±10
,.,A
OV .. VIN .. Vee
Output leakage Current
± 10
,.,A
0.45V .. Vour " Vee
2.4
~
'll
' LO
Vel
Clock Input loV( Voltage
-O.S
VeH
Clock Input High Voltage
3.9
C IN
CIO
mA
rnA
T A=2SoC
+0.6
V
Vee + 1.0
V
Capacitance of Input Buffer
(All input except
ADo- AD15, RQ/GT)
15
pF
fc= 1 MHz
Capacitance of 110 Buffer
(ADo- AD 15, RQ/GT)
15
pF
fc= 1 MHz
3-346
AFN·01497D
inter
iAPX 86/10
A.C. CHARACTERISTICS
(8086: TA = O°C to 70°C, VCC = 5V ± 10%)
(8086-1: TA = O°C to 10°C, Vcc = 5V ± 5%)
(8086-2: TA = O°C to 70°C, Vcc = 5V ± 5%)
MINIMUM COMPLEXITY SYSTEM
TIMING REQUIREMENTS
Symbol
Parameter
8086
8088·1 (Preliminary)
Units
8088-2
Test
Conditions
Min.
Max.
Min.
Ma...
Min.
Ma ...
TCLCL
ClK Cycle Period
200
500
100
500
125
500
TClCH
ClKlowTime
118
53
68
TCHCL
CLK'High Time
69
39
44
TGH1CH2
CLK Rise Time
10
10
10
ns
From 1.0Vto
3.5V
TCL2Cll
CLKFall Time
10
10
10
ns
From 3.5Vto
1.0V
ns
ns
ns
TDVCL
Data in Setup Time
30
5
20
ns
TCLDX
Data in Hold Time
10
10
10
ns
TRtvCL
ROY Setup Time
into 8284A (See
Notes 1. 2)
35
35
35
ns
TCLRIX
ROY Hold Time
into 8284A (See
Notes 1. 2)
0
0
0
ns
TRYHCH
READY Setup
Time Into 8086
118
53
68
ns
TCHRYX
READY Hold TIme
into 8086
30
20
20
ns
TRYlCl
READY Inactive to
CLK (See Note 3)
-8
-10
-8
ns
THVCH
HOLD Setup Time
35
20
20
ns
TINVCH
INTR. NMI. TEST
Setup TIme (See
Note 2)
30
15
15
ns
TILIH
Input R,se Time
(Except ClK)
20
Input Fall TIme
(Except ClK)
12
TIHIL
,
20
20
ns
From O.8Vto
2.0V
12
12
ns
From 2.0Vto
O.8V
-
3-347
I
AFN-01497D
intJ
IAPX 86/10
A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES
Symbol
8088
Pereme'er
8088·' (Prellmlnery)
Unit.
8088-2
Min.
Max.
Min.
Mex.
Min.
Max.
TCLAV
Address Valid Delay
10
110
10
50
10
60
TCLAX
Address Hold Time
10
TCLAZ
Address Float
Delay
TCLAX
10
10
60
TClCH-2O
10
40
TClCH-l0
TeLAX
Tes'
Conditions'
ns
ns
50
ns
50
ns
55
ns
TlHll
ALE Width
TCllH
ALE Active Delay
TCHll
ALE Inactive Delay
TlLAX
Address Hold Time
to ALE Inactive
TClDV
Data Valid Delay
10
TCHDX
Data Hold Time
10
10
10
ns
TWHDX
Data Hold Time
AfterWR
TClCH-30
TClCH-25
TClCH-30
ns
TCVCTV
Control Active
Delay 1
10
110
10
50
10
70
ns
TCHCTV
Control Active
Delay 2
10
110
10
45
10
60
ns
TCVCTX
Control Inactive
Delay
10
110
10
50
10
70
ns
TAZRl
Address Float to
READ Active
0
TCLRL
RD Active Delay
10
165
10
70
10
100
ns
TClRH
RD Inactive Delay
10
150
10
60
10
80
ns
TRHAV
RD Inactive to Next
Address Active
TClHAV
HlDA Valid Delay
TRlRH
RDWidth
2TClCl-75
2TClCl-4O
2TClCl-50
ns
TWlWH
WRWidth
2TClCl-60
2TClCl-35
2TClCl-40
ns
TAVAl
Address Valid to
ALE low
TClCH-60
TClCH-35
TClCH-4O
ns
TOlOH
Output Rise Time
20
20
20
ns
.Fro;" 0,8V to.
2,OV
TOHOl
Output Fall Time
12
12
12
ns
From 2,OV to
0.8V
80
85
TCHCl-l0
45
TCHCl-l0
110
10
50
10
ns
10
60
TClCl-4O
60
10
ns
·CL = 2G-loo pF
for all 8086 Outputs (In addltion to 8086 sailload)
ns
0
TClCl-35
160
ns
TCHCl-l0
0
TClCl-45
10
TClCH-l0
40
ns
100
ns
NOTES:
1, Signal at 8284A shown for reference only.
2. Setup requirement for asynchronous signal only to guarantee recognition at next ClK,
3. Applies only to T2 state. (8 ns into T3).
3-348
AFN,01497D
inter
iAPX 86/10
A.C. TESTING INPUT, OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
INPUTIOUTPUT
DEVICE
UNDEA
TEST
i } C ' = 1 0 0 PF
A C TESTING INPUTS ARE DR1VEN AT 2 4V FOR A LOGiC '1" AND 0 45V FOR
A LOGIC 0' TIMING MEASUREMENTS ARE MADE AT 1 5V FOR BOTH A
LOGIC '1" AND '0"
C, INCUJDES JIG CAPACITANCE
WAVEFORMS
MINIMUM MODE
T1
VCHv---'\
J
VC~
CLK (8214A oulpuQ
~ TCHCTV
MIlO
--j.1
T2
_TCLC~ TCH1CH2-i
\
I
.1::. X.
----..-
!~Il
TCLAX·
I:
TCLLH-
f
ALE
--1----tJ.
TLH~L-::::
*
I~
I- TCLCH -
~
TALL
57-S3
r--
I::~-+----~CC-----+----+--~----+--_-J'~ - -V,H ....,
- ,:;WCt,
_f-+1.--r~~C":LA:-l'l"'~-~+---+--~---
VIL - - •
TRYLCl-
-
--h
---I
,..---+...,.
__
TAVAL
_
TRYHCH-
l.- TLLAX __ _
~I
TCLAV-
-TCLAZ
_TCLAX
A15-ADo
---'------r---:-.. _
__,__ ____
DTIIl
n-
!--TLLAX
TCHLL - I
(NOTE 1)
T4
r-
ADY (8214A l.puQ
see NOTE 4
(Wli, iNfl = VOH)
1
~
TCHCL
JAI, A11-A11
AD
Tw
~~_--~------+=TC~L~D~Vr---~'----~------~----~-T-C-H-DX-_-+-x~r~-------
TCLAY-
ReAD CYCLe
T3
TCL2CL1~,
.=L r'
TAZRL-
-TCHRYX
-
TDVCL--r-TCLDX-
.I'
--------I
FLOAT
DATA IN
TCLRH-
Flo:~
1-
TRHAV
~
~--+----------r-JI
TCHCTV
TCLRLI----~r---+---- TALRH
--TCHCTV
I
\.
~--------------r-~----------r---~J
TCVCTX-
TCVCTV- {
~
3-349
I
_ _ _ _ _ _ _ _ _ _- J
AFN.()1497D
iAPX86/10
WAVEFORMS (Continued)
MINIMUM MODE (Continued)
TW
CLK (8284A OutpuQ
TCLCH
M/iO
r-I
ALE
WRITE CYCLE
,,",OTE 1)
(RD. iNTA.
DEN
DTIR'=VOH)
INTA CYCLE
OTfR
(NOTES 1 & 3)
RD, WR=VOH
JR!=Vod
SOFTWARE HALTRD. WR. INTA = VOH
DT/R = INDETERMINATE
INVALID ADDRESS
SOF.TWAAE HALT,
TeLAY
NOTES:
1. All signals switch between VOH and VOL unless otherwise specified.
2. ROY is sampled near the end of T2. T3 • Tw to determine if Tw machines states are to be inserted.
3. Two INTA cycles run back-to-back. The 8086 LOCAL AOORIOATA BUS is floating during both IN~A cycles. Control signals shown
for second INTA cycle.
4. Signals at B2B4A are shown for reference only.
5. All timing measurements are made at 1.SV unless otherwise noted.
3-350 .
AFN-01497D
inter
IAPX 86/10
A.C. CHARACTERISTICS
MAX MODE SYSTEM (USING 8288 BUS CONTROLLER)
TIMING REQUIREMENTS
Symbol
8088
Perameter
80'1-' (Preliminary)
808t-~ (Prellmlnery)
Min.
Max.
Min.
Ma..
Min.
Ma..
TClCl
ClK Cycle Period
200
500
100
500
125
500
TCLCH
ClKLowTlme
118
53
88
TCHCl
ClK j.Ugh Time
69
39
44
"Unit.
Teat
Condition.
n.
ns
no
'TCH1CH2
CLKRlseTlme
10
10
10
ns
From 1.OVto
3.SV
TCL2Cll
CLK Fall Time
10
10
10
ns
From 3.5Vto
1.OV
TDVCl
Data In Setup Time
30
5
20
TClDX
Data In Hold Time
10
10
10
no
TR1VCl
ROY Setup Time
into 8284A (See
Notasl.2)
35
35
35
ns
0
0
0
ns
TClR1X
ROY Hold Time
Into 8284A (Sea
-Nolasl.2)
ns
TRYHCH
READY Setup Time
inl08088
118
53
88
ns
TCHRYX
READY Hold Time
into 8088
30
20
20
ns
TRYlCl
READY Inacllve 10
ClK (See Note 4)
-8
-10
-8
ns
TINVCH
Setup Time for
Recognition (INTR.
NMI. TEST) (Sea
Note 2)
30
15
15
ns
TGVCH
RQJGT Setup Time
30
12
15
ns
TCHGX
Frei Hold Time Into
40
20
30
ns
8088
nLiH
Input Rise Time
(Except ClK)
20
20
20
ns
From 0.8V to
2.OV
TIHll
Input Fall Time
(Except elK)
12
12
12
ns
From 2.0Vto
0.8V
NOTES:
1. Signal at 8284A or 8288 shown for reference only.
2. Setup requirement for asynchronous signal only to guarantee recognition at next elK.
S. Applies only to TS and walt states.
4. Applies only to T2 state (8 liS into TS).
3-351
AFN.()1497D
JAPX 86/10
A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES .
'Teat
Symbol
BOB6
Parameter
. 8088-1 (PrelimInary)
8086-2 (P7e"ml,'!!.I!'
Units
MIn.
Max.
Min.
Max.
Min.
MalL
TCLML
Command Active
Delay (See Nota 1)
10
35
10
35
10
35
n.
. TCLMH
Command InactIve
Delay (See Nota 1)
10
35
10
35
10
35
n.
65
n8
TRYHSH
READY Active to
Status Passive (See
Nota 3)
110
45
Conditions
I
TCHSV
Status Active Delay
10
110
10
45
10
60
ns
TCLSH
StatU8 Inactive
Delay
10
130
10
55
10
70
ns
TCLAV
Address Valid
Delay
10
110
10
50
10
60
ns
40
TCLAX
TCLAX
Address Hold Time
10
TCLAZ
Address Float Delay
TCLAX
10
TSVLH
Status Valid to ALE
High (See Nota 1)
15
TSVMCH
Status Valid to
MCE High (See
Note 1)
TCLLH
10
ns
50
ns
15
15
ns
15
15
15
ns
CLK Low to ALE
Valid (See Nota 1)
15
15
15
ns
TCi.MCH
CLK Low to MCE
High (See Note 1)
15
15
15
ns
TCHLL
ALE Inactive Delay
(See Note 1)
15
15
15
n8
TCLMCL
MCE Inactive Delay
(See Note 1)
15
15
15
ns
60
10
TCLDV
Data Valid Delay
10
TCHDX
Data Hold Time
10
TCVNV
Control Active
Delay (See Nota 1)
5
45
5
45
5
45
ne
TCVNX
Control InactIve
Delay (See Nota 1)
10
45
10
45
10
45
ne
TAZRL
Address Float to
Read Active
0
110
10
50
10
10
60
10
ns
ns
ns
0
0
TCLRL
RD Active Delay
10
165
10
70
10
100
ne
TCLRH
RD Inac;tive Delay
10
150
10
60
10
60
n.
TRHAV
RD Inactive to
Next Address Active
TCHDTL
Dinsction Control
Active Delay (See
Notal)
50
50
50
n8
TCHDTH
Diractlon Control
InactIve Delay (See
Notal)
30
30
30
ne
TCLGL
GT Active Delay
0
65
0
45
0
50
n.
TCLGH
GT Inactive Delay
0
65
0
45
0
50
TRLRH
RDWldth
TOLOH
Output Rlsa TIme
20
20
TOHOL
Output Fall TIme
12
12
TCLCL-45
TCLCL-35
TCLCL-4O
3-352
n.
2TCLCL-50
2TCLCL-4O
2TCLCL-75
CL ~ 2O-100pF
lor all 8086 Out·
puis (In add~
tlon to 6OB6 sail·
load)
I
ns
ne
20
ns
FromO.6Vto
2.OV
12
ne
From2.OVto
0.6V
/
AFN'()1497D
inter
I~PX
86/10
WAVEFORMS
MAXIMUM MODE
CLK
QSo.QS,
1i.11.1!O (EXCEPT HALT)
. 1
ALE (8288 OUTPUT)
SEE NOTE 5
RDY (I2I4A INPUT)
READY ~ INPUT)
READ CYCLE
RD
DT/R
8288 OUTPUTS
SEE NOTES 5,1
,
1
iiiiIIe OR RlIR!
DEN
TCVNX
30353
AFN.()1497D
intJ
iAPX86/10
WAVEFORMS (Continued)
MAXIMUM MODE (Continued)
T,
T1
T,
T.
Tw
eLK
\
§2,!;,§i) (EXCEPT HAL 1)
'''''----
WRITE CYCLE
TCHDX--
AD15-ADo
DATA
TCVNX-
DEN
TClMH-
ourrurs
8288
SEE NOTES 5,6
AMWC OR
.iJOi.iiC
_-TClMH
MWi'COR lowe
INTACYCLE
AD1S-ADO
(SEE NOTES 3 I 4)
FLOAT
TSVMCH-
I
r--
MeEI
I'l>-m
o-TCHDTH
TCLMCH-
DT/A
.... 0U11'IJ1S
SEE NOTES
5,61 'NTA
DEN
SOFTWARE HALT -
___
I
-'~~-'''--:::.''::J ~
'_N_VA_L_'D_A_D_D_R_ES_S_'_ __
/r----.,.-----"T\-- -----
~
\~.---~
'-------
NOTES:
1. All signals switch between VOH and'VOL unless otherwise specified.
2. ROY is sampled near the end of T2, T3, Tw to determine if Tw machines states are to be inserted.
3. Cascade address is valid between first and second INTA cycle.
4. Two INTA cycles run back-to-back. The 8086 LOCAL ADDR/DATA BUS is floating during both INTA cycles. Control for pointer
address is shown for second INTA cycle.
S. Signals at 8284A or 8288 are shown for reference only.
6. The issuance of the 8288 command and control Signals (MRDC, MWTC; AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the
active high 8288 CEN.
.
7. All timing measurements are made at 1.SV unless otherwise noted.
8. Status inactive in state just prior to T4.
3-3~4
AFN·01497D
intJ
WAVEFORMS (Continued)
ASYNCHRONOUS SIGNAL RECOGNITION
HMI
INTR
NOTE 1 SETUP REQUIREMENTS FOR ASYNCHRONOUS SIGNALS CNL Y TO GUARANTEE RECOGNITION
AT NEXT eLK
BUS LOCK SIGNAL TIMING (MAXIMUM MODE ONLY)
Any elK Cycle
Any elK CYCle--1
RESET TIMING
_I
'co
Ct.K
CLK
N CLKCYCLES
REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)
1 THE COPROCESSOR MAY NOT DRIVE THE BUSES OUTSIDE THE REGION
SHOWN WITHOUT RISKING'CONTENTION
HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLy)
CLKLrC~~R2CYCLES
HaLO
~~,
I_THVC"
--I~
TCLHAV
HLDA i - - - - - - " - - - - - - ; , Y I - - - , L H A V
,
-l~..:.::TCL::::A2_·---i'----~
_._--I~:,..,___-',,_-
I -_ _ _ _ _ _...
3-355
COPRO;,..:-SS_OR_ _ _ _ _..J
AFN·01497D
IAPX88/10
"I,'
Table 2. Instruction Set Summary
DATA TRAISFER
.., .
HV=.",
7 85 43 Z I 0
AeOIl'er/memoryIO/lrom r89lS!er
10001 Dd
Immt4111. 10 regrster/memory
1lI0II000 "m
I I DOD 1
1011 \II
data
1010000 w
addrlaw
\II
'\II
71543Z I 0
'
".
Immedlaleto reglsltr
M.mory10 atcumulator
addrlow
Acclimulatoriornernory
1010001 w
I\eGlslerlmemory to segment reglsler 10001" 0 rnod 0 reo
Segmenl register loreglsleflmemory 10001100 mCHIOreg: "m
PUIfI
~
~
dala
7114321 D
dala Ilw 1
dalallw 1
addrhlgh
1111 t i l l
mod 1 10 rIm
01010'ttI
000 reg 11 0
1000 I 1 11
01011
Segmentreglsler
000relll11
".
Reglsler/memorywllh reglstef
Regl,terwllhaccumulalor
1000011 w mod 109
10010 rag
III-Input from
Flx,dport
I I I 0010 W
Vaflableporl
1110110 w
D
115 43 2 I.
modO 0 1
,'m
ilEa-Change sign
1I110l1w modO 11
"m
....."
"
Aeolsterlm.moryan(!rlglSta'
Immediate With reglsler/memory
ImmedlslewllhaccumulalOl
001 II 0 d w mod __f811 rim
..I ASCUad/uSllorsllblracl
IMI Decimal adJoSI lor lub\racl
MUl MuJllpJylllnslgneif)
001 I 1 I 11
UO ASCII adJusl lordlv.de
CIW Conyetl byle 10 word
CWD COnyerl word 10 double word
rclS = bd\lltt
sri
, 1 , 1 , , 1 \II
01001
UN ASCII ad,1l$1 lor multiply
OiVDIYldetun$lgnedl
IDIVlntegrrd.vtdelslgnedl
".
modO 0 0
78&4
Register
'IUllnlt1lermulllplY(Slgn8il)
PIli
Reglslerlmemory
Reglsler
DlC DlcflllllnI
Reglslef/memory
C.P
addlhlgh
,....
AlIglster/memory
Register
,Segl'l)enlreglster
POI
18543210
"m
100000 s w modl"
00'11 lOw
"m
dala
785 4 3210
dala
71141210
data IlIw 01
dalallYi t
00101111
1111011w modI 0 0 "m
11110llw modlO I "m
11010100 00001010
111101lw modI! 0 "m
1 I I 1 q 11 W modI 11 "m
11010101 00001010
10011000
10011 001
,'m
port
LOGIC
OUT=OUIPUIIO
F,uclporl
var\lbleport
JLAT-Translale byte to At
NOTlnYar!
1110011w
1110111w
11 0 101 I t
10001101
11000101
,",1=toidpol"terIOES
mod
m,'
11000100 m,'
W1F-load AH wrth flag'
IIHF·S!oreAHmtoltags
10011111
10011110
'IJIfIF-Pushliags
NPF-Popllags
10011100
10011101
LE"~Load
lI'~Load
EA 10 rlgllter
pomter 10 OS
pori
SNL/SA1 Shill logicallalllhmelic lelt
SNRSMlloglcalfighl
SAl Shltlanlhmellcflghl
109
ROLRolalelett
10,
IIOItROIale"ghl
ICLRolileltifoughcarryliaglell
IICIiRolatelhloughcaffyugh!
10,
"D-'"
lieu
Imemory With ~Ister 10 !Ither
,m_,ale 10 "Dlslerfmemory
Immedlale 10 accumulalor
Reg /mem~r~ and feglstef tOtilher
Immediate 10 rtglster/memoly
lmmedlale10 accumulalOf
dala
dala" wI
ImmedIate 10 accumulator
00010 tOw
data
Immecllaleto reglster/memolY
Immedlaletoaccumulatol
do.
datalfsw·Ol
dalallw 1
AU-ASCII Id,ust lor Idd
DU-DeClmalldJUsllorldd
00100111
SUI = MlracI
.... _"""-
RllffmemoryalHlrtllllltrlo.l1tter
Imm.cllatlfromrtOISltrlm.mory
ImlMCl'lltltomac:cumulator
IO.
0010010111
dala
00 I 0 1 Od 1'1 mod 10, "m
1000005 w modI O! "m
001011 0 w
data
Imm.dl.leto'accumulalof
..
,
dalaIf sW'OI
datallw 1
"m
100000 S w modO 11 ,'m
00011 tOw
data
dala
datallw-l ,
daladw I
data
dalallw 1
datallw 1
data
dalallw'
dall lis w·Ol
00001 Od w- mod
"m
1000000 w modO 0 I "m
0000110 w
datallw"!
0011 0 0 d w mod 10, "m
1000000 w mocl1 to rim
0011010 w
dala
data
datallw t
'"
,. ,
d8l11lw 1
STRINa MANIPULATION
AE'~R,pe'l
1111 00 It
MOV,,"Movebyte!word
10100! 0 w
1 (I I 0011 w
1 (I! 0 11 t w
CMPS=Comparebyle/word
000110 d w mod ,og
do.
dalallw 1
helm".r
RaCl/m'maryand reg,slef10 ellhef
Immedlale 10 Itglst.rlmemor~
1111111 w modO 00 11m
01000 reg
00110111
tmmecllateft'omaccumulator
00100 Od w mod 'og "m
1000000 w modI 00 f/m
O' Dr
'R =1.,....
tmmtd!ltefromrllllst.r/memory
modO 01 "m
modO 1 0 rim
modO 11 "m
datalfsw 01
Reg Imemoryandre{listerlotllller
000 tOO d w mod 109 "m
1000005111 modO 1 0 rIm
fIeg Imlmory and rlgJlIIt to elll\tr
mod 111 "m
modO 0 0 rim
'"
000000 d w mod 'og "m
1 0 0 0 0 0 5 W modO 0 0 rim
00000 lOw
do.
RIO lmemory wltb register lotltller
Immedlaleloregl.terlmemory
Regiater
I 00 v w
10 0 v w
I 00 v w
1 OOnl'
TEST AItd IUIII:IIon to 11q•• 10'111111
Reglster/memor~ and register
1000010 w mod
"m
Immed'atedalaandreglslerlmemory t I l l 0 " w mOdO 0 0 "m
Immediate dalaand accumuJalOf
tOt O! 00 1'1
data
AIIC"MtI .... arry
"'Dlster/memot~
I 10
11 0
11 0
11 0
modO I 0 "m
mod 1 00 "m
modI 0 1 "m
••0 .od
ARITHMETIC
II
111 ' 0 " w
I 1 0 '00 v ~
110 I 0 0 Y W
1 10 100 v W
SCAS"Scanbytefword
LODS-Load bytefwd to ALIAX
STDS=Slor bylt/wd I~m ALIA
101011 0 w
10 I 0 I 0' w
Mnemonics ©Intel, 1978
3-356
AFN'()1497D
IAPX 86/10
Table 2, Instruction Set Summary (Continued)
COITROl TlAllFER
CAI.L· CIII'
71143210
Direct wlttlln segment
1 1 101000
dlsp-Iow
11111111 mod 010 rIm
Indtrect wlthm segment
DI"ctiotersegment
10011010
Indlfectmtersegment
11111111
71143210
oftsll·low
seg·low
mod 0 1 1
111432 I 0
71141210
dlsp·hlgh
ottset·hlQh
seg·high
"m
Ju.,:
JM•• U.OOIIdlU,..1
dlsplow
dlsp
11111111 mod 1 00 rim
11101010
oUsel·low
11101001
11101011
OUlct wlthm segment
OI,ect .. ,lhlnsegment·short
IndtreCI Wllhm segment
Dlrectftersegment
seg·low
11111111 mod 101 rim
Indirect mterst9menl
dlsp·tllgh
11000011
Within seQ adchng _mmed to SP
11000010
11001011
11001010
Intersegment
Int.fslgment adding Immediate to SP
Jl/JZ=Jumpon equal/zero
~L/J'II .. Jumpon lesslnol grealer
or equal
JLE/JllaJump on less or aquilinot
01110100
or equal
JIE/JIA~~~~",~ below or equal I
01 1 10010
01110110
greater
"I/JlA£zJulTlp on below/nol above
01111100
01111110
JPlJPl=Jump on panty/panty even
01 I 11010
JO..Jump on overflow
.II"Jump0" Slon
JIE/JIZ..,Jump on not equal/not zero
..IUJ8E"Jumponnolless/grealer
or equal
JIU/JI:Jumpon not less orequalJ
greater
011 10000
011 11000
01110101
01111101
I) 1 1 11 1 1 1
INT
Typespecilled
Type ~
II'O-Interrupt onoverllow
IIIETlnlerruplreturn
dala·low
data·hlgh
data·low
dlsp
datahlllh
....
dlsp
dlsP
dlsp
dlsP
" mod - 11 then rIm IS traated as a REG ',eld
" mod· 00 than olSP • 0'. dlsp·low and dlsp·hlgh are absent
If mod - 01 t~en OISP - dosp·low slgn-extended to l~b1ts. dlsp-hlgh IS absent
" mod - 10 then olSP - dlsp·hlgh dlsp·low
" rIm = 000 then EA - (BX) + (SI) + olSP
" rIm = 001 then EA = (BX) + (01) + olSP
~ rIm = 010 then EA - (BP) + (SI) + OISP
if rIm = 011 then EA· (BP) + (01) + OISP
Itr/m = 100 then EA - (SI) + olSP
" rIm' 101 then'EA = (01) + OISP
" rIm = 110 then EA· (BP) + olSP'
~ rIm' 111 then EA = (BX) + OISP
OISP 'ollows 2nd byte of instruction (be'ore data " requored)
110 then EA - dlsp·hlgh. dlsp·low
01110111'
do,
01 11 1011
01 11 000 ,
dlsP
dlsp
01111001
1 11 00010
11 10000 I
dlsp
11100000
1 11 00011
dlsP
dlsp
11001101
11 001 100
type
1 10011
dlsP'
dlsp
to
t 1 00111 1
1111 1000
CMC Complement carry
aTC Sel carry
eLO Clear dlrechon
ITO Set direction
eLi Clear Interrupt
ITI Setmtarrupt
HLT Hall
WAIT Wall
E8CEscapeiloelliernaldevicel
LOCI( Bus lock prell x
dlsP
dlSP
7.6432 I 0
dlsp
Inllrrupl
PROCESSOR CONTROL
eLi: Clear carry
dlsP
dlSP
dlsp
If d = 1 then "to" reg, If d .. 0 then ''from'' reg
If w =1 then word lnatructlOn; If w· 0 then byte instruction
=
JI. Jump on not sign
LOO' Loop ex times
LDO'ZlLDOPf Loop while zero/equal
LDOI'NZILOOPNE LOOp .... hlle nol
zerofequal
Jell-Jump on ex zero
seg·hlgh
Al - 8-blt accumulator
AX - 18-blt accumulator
CX • Count ragister
OS • Data segmant
ES • Extra segmant
Abova/balow ralars to unsigned value
Greater =more positive.
Less = less positive (more negative) signed values
'except If mod -00 and rIm
01 110011
ollset·hlgh
lET • R,lIIf1IlnIm CALL
Wlthlnsqmenl
JII/JAI·Jump on nol blliowlabove
or equal
JHE/JA-Jumll on not below or
equallabove
J.PI~PO~Jump on not parlpar odd
JIG·Jump on not overflow
1 1 11 0 1 0 1
11111001
11111100
1 1 I 11 101
1 11 11 010
I 1 1 11 0 11
1 11 10 I 0 0
1001 1011
1 1011 MX II: modx x x
11110000
rIm,
" S W = 01 the,n 16 bits of Immediate data 'orm the operand
" s w= t 1 then an Immediate data byte IS soon extended to
form the 16·bot operand
d V 0 then "count"' 1. " v 1 then "count"· 10 (Cl)
x don't care
Z IS usad 'or strmg promltlves 'or comparoson with Z.F FLAG
SEGMENT OYE~RIDE PREFIX
=
=
=
10 0 1 reg 1 1 01
=
'
REG IS assigned accordmg to the 'ollowlng table
18-BIt (w -II
000 AX
001 CX
010 OX
011 BX
100 SP
101 BP
110 SI
111 01
8-81t (w - DI
000 AL
001 CL
010 oL
011 BL
100 AH
101 CH
110 oH
111 BH
SlgMent
00 ES
01 CS
10 SS
11 Os
Instructions which reference the flag register file as a 16-blt object use
Ithe symbol FLAGS to represent the fole
FLAGS
=
X X X X (OF) (OF) (IF) (Tf) (SF) (ZF) X IAF) X (PF) X(CF)
Mnemonocs©tntel, 1978
3-357
AFN.()1497D
,.
inter
iAPX 186
.HIGH INTEGRATION 16~BIT MICROPROCESSOR
• Direct Addressing Capability to
1 MByte of Memory
• Integrated Feature Set
-Enhanced 8086-2 CPU
-Clock Gem;trator
-2 Independent, High-Speed DMA
Channels
-Programmable Interrupt Controller
-3 Programmable 16-blt Timers
-Programmable Memory and
Peripheral Chip-Select Logic
-Programmable wait State Generator
-Local Bus Controller
• Available In 8 MHz (80188) and cost
effective 6 MHz (80186-6) versions.
• Hlgh·Performance Processor
-2 Times the Performance of the
Standard IAPX 86
-4 MByte/Sec Bus Bandwidth
Interface
rD~LKOUT
IX, JxCLbCK
GENERATOR
IS·BIT
AW
IS·BIT
GENERAL
PURPOSE
REGISTEAS
J
SRDY'-~
ARDY' - +
TaT' - +
HOLD,- ...
HLDA
liES::: ...
RESET
I
lJ-N
, Ll)Cj(
DT/A"
T
L
0
1 2
MAX COUNT :~
REGISTERB
..
MAX COUNTA
REGISTER
CONTROL REGISTERS
COUNTlIS-BIT
REGISTER
PROGRAMMABLE
INTERRUPT
CONTROLLER
CONTROL i
REGISTERS
..J
INTERNAL BUS
I
D
{'
PROGRAMMABLE
Rc;.~~~,:-S
f±t
~
ucs
AOO-' AI8iS3AD15
AI9/S6
LCS
..:::L
MCSO-3
DRQO
r-r- DRQl
PROGRAMMABLE
DMAUNIT1
0
SOURCE2O-BIT
POINTERS
,2Q·BIT
L) DESTINATION
POINTERS
lS·BIT
TRANSFER COUNT
CHI_LECT
UNIT
I~A!e
IIH
HE/S7
~
U
16-BIT
SEGMENT
REGISTERS
6-BYTE
PREFETCH
QUEUE
t 1t
•PROGRAMMABLE
•
TIMERS
J
l
I
I
I
I
I
I
I
TMR OUT 1 TMR OUT 0
TMRIN TMRIN
INJTO
U
BUS INTERFACE
UNIT
'-
• High Performance Numerical
" Coprocessing Capability Through
8087 Interface
NTI
'ExecUTIONiiNiT]
D
• Complete System Development
Support
-Development Software: Assembler,
PL/M, Pascal, Fortran, and System
Utilities
-In.Clrcult.Emulator (l2ICE™·188)
-iRMXTM 86,88 Compatible (80130
OSF)
INT3/1NTAI
INT2!iIi'I'Aii
TT
It
• Completely Object Code Compatible
with All Existing IAP~ 86, 88 Software
-10 New Instruction Types
I
1(1;kS6/A2
PCSSiil1
=
,
PCSO-4
Figure 1. IAPX 186 Block Diagram
Intel Corporation Assumes No Responsibility for the Use of Any Circuitry Other Than CircUitry EmbOdied In an Intel Product No Other CtrcUlt Patent licenses are Implied
InformatIon COntained Herein Supercede Previously Pubhshed Specifications On These DeVICes From Intel.
JULY 1983
,
©INTELCORPORATION,I983
,
3.358
ORDER NUMBER: ~1D461-D03
inter
IAPX 186
The Intel iAPX 186·(80186 part number) is a highly integrated 16-bit microprocessor. The iAPX 186 effectively
combines 15-20 of the most common iAPX 86 system components onto one. The 80186 provides two times
greater throughput than the standard 5 MHz iAPX 86. The iAPX 186 is upward compatible with iAPX 86 and 88
software and adds 10 new instruction types to the existing set.
TOP
BOTTOM
Som~~LJUIUL~UULJUULJUULJUU"~
51
52
ARDV
CLitOUT
RESET
X2
Xl
v••
ALflQSO
RD/QSMD
WR/QSl
BHE
Al91S6
Al8/S5
A17/S4
A16153
~~~~~~1~
"
Ort:".,n rl nln n
1
TMR IN 1
TMRINO
DRQl
DRQO
~~1~~~~~~
~
PIN NO.1 MARK
~b~!~~~gg~S~~!Qa8
~c~c~c~c> ~c~~cc c c
Figure 2. 80186 Pll;lout Diagram
Table 1. 80186 Pin Description
Symbol
Pin No.
Type
Vee,Vee
9,43
I
Vss, Vss
26,60
I
System Ground.
RESET
57
0
Reset Output indicates that the 80186 CPU if being reset, and can be used as a system
reset. It is active HIGH, synchronized with the processor clock, and lasts an integer
number of clock periods corresponding to the length of the Rrn signal.
X1,X2
59,58
I
Crystal Inputs, X1 and X2, provide an external connection for a fundamental mode
. parallel resonant crystal for the internal crystal oscillator. X1 can interface to an
external clock instead of a crystal. In this case, minimize the capacitance on X2 or
drive X2 with complemented X1. The input or oscillator frequency is internally divided
by two to generate the clock signal (CLKOUn.
CLKOUT
56
0
Clock Output provides the system with a 50% duty cycle waveform. All device pin
timings are specified relative to CLKOUT. CLKOUT has sufficient MOS drive capabilities
for the 8087 Numeric Processor Extension.
RES
24
I
System Reset causes the 80186 to immediately terminate its present activity, clear the
internal logie, and enter a dormant state. This signal may be asynchronous to the
80186 clock. The 80186 begins fetching instructions approximately 7 clock cycles
after Rrn is returned HIGH. RES is required to be LOW for greater than 4 clock
cycles and is internally synchronized. For proper initialization, the LOW-to-HIGH transition of Rrn must occur no sooner than 50 microseconds after power up. This input
is ptovided with a Schmitt-trigger to facilitate power-on Rrn generation via an RC
network. When RES occurs, the 80188 will drive the status lines to an inactive level
for one clock, and then tri-state them.
Name and Function
System Power: + 5 volt power supply.
3-359
AFN'()2217C
·N . . . . I·
I. '-e-
IAPX 186'
Table 1. 80186 Pin Description (Contlnued)
Symbol
fEST
Pin
No.
Type
Name and Function
47
I
fEST is examined by the WAIT instruction. If the TEST input is HIGH when
"WAIT" execution begins. instruction execution will suspend. TEST will be
resampled until it goes LOW. at which time execution will resume. If interrupts
are enabled whilethe80186 is waiting for TEST, interrupts will be serviced, This
input is synchronized internally,
TMR IN O.
TMR INl
20
21
I
I
Timer Inputs are used either as clock or control signals. depending upon the
programmed timer mode. These inputs are active HIGH (or LOW-to-HIGH
transitions are counted) and internally synchronized,
TMR OUTO.
TMR OUT 1
22
23
0
0
Timer outputs are used to provide single pulse or continuous waveform generation, depending upon the timer mode selected.
ORQO
ORQl
18
19
I
I
OMA Request is driven HIGH by an' external device when it desires that a
DMA channel (Channel 0 or 1) perform a transfer. These signals are active
HIGH. level-triggered. and internally synchronized.
46
I
, Non-Maskable Interrupt is an edge-triggered input which causes a type 2
interrupt. NMI is, not maskable internally. A transition from a LOW to HIGH
initiates the interrupt at the next instruction boundary. NMI is latched internally. An NMI duration of one clock or more will guarantee service. This input is
internally synchronized.
INTO.INT1.
INT2/INTAO
INT3/INTAl
45.44
42
41
I
I/O
I/O
Maskable Interrupt Requests can be requested by strobing one of these pins.
When configured as inputs, these pins are active, HIGH. Interrupt Requests are
synchronized internally. INT2 and INT3 may be configured via software to
provide active-LOW interrupt-acknowledge output signals. All interrupt inputs
may be configured via software to be either edge- or level-triggered. To ensure
recognition, all interrupt requests must remain active until the interrupt is
acknowleged. When iRMX mode is selected, the function of these pins
. changes (see Interrupt Controller section of this data sheet).
A19/S6,
A18/S5,
A17/S4,
A16/S3
65
66
0
0
0
0
Address Bus Outputs (16-19) and Bus Cycle Status (3-6) reflect the four most
significant address bits during T1. These signals are active HIGH. During T2,
T3, Tw, and T4, status information is available on these lines as encoded
below:
--
'NMI
67
68
Low
I
I
S6
High
I
Processor Cycle
S3,S4, and S5 are defined as LOW during T2-T4.
AD15-ADO
BHE/S7
DMA Cycle
I
10-17.
1-8
I/O
Address/Data Bus (0-15) signals constitute the time mutiplexed memory or I/O
address (T1) and data (T2' T3. TW, and T4) bus. The bus is active HIGH. AO is
analogous to BHE for the lower byte of the data bus, pins D7 through DO. It is
LOW during T1 when a byte is to be transferred onto the lower portion of the
bus in memory or I/O operations.
64
0
During T1 the Bus High Enable signal should be used to determine if data is to
be enabled onto the most significant half of the data bus. pins D15-D8. BHE is
LOW during T1 for read, write, and interrupt acknowledge cycles when a byte is
to be transferred on the higher half of the bus. The S7 status information is
available during T2, T3, and T4. S7 is logically equivalent to BHE. The signal is
active LOW. and is tristated OFF during bus HOLD.
BHE and AO Encodings
BHE Value
AO Value
Function
0
0
1
0
1
0
1
Word Transfer
Byte Transfer on upper half of data bus (D15-D8)
Byte Transfer on lower half of data bus (D7-Do)
Reserved
1
3-360
AFN.()2217C
inter
IAPX 186
Table 1. 80186 Pin Description (Continued)
Pin
No.
Type
Name and Function
ALE/QSO
61
0
Address Latch Enable/Queue Status 0 is provided by the 80186 to latch the
address into the 8282/8283 address latches. ALE is active HIGH. Addresses are
guaranteed to be valid on the trailing edge of ALE. The ALE rising edge is
generated off the rising edge of the CLKOUT immediately preceding T1 of the
associated bus cycle, effectively one-half clock cycle earlier than in the standard 8086. The trailing edge is generated off the CLKOUT rising edge in T1 as
in the 8086. Note that ALE is never floated.
WR/QS1
63
0
Write Strobe/Queue Status 1 indicates that the data on the bus is to be written
into a memory or an I/O device. WR is active for T2, T3, and Tw of any write
cycle. It is active LOW, and floats during "HOL.D." It is driven HIGH for one clock
during Reset, and then floated. When the 80186 is in queue status mode, the
ALE/QSO and WR/QS1 pins provide information about processor/instruction
queue interaction.
Symbol
QS1
0
0
1
1
RD/QSMD
62,
0
QSO
0
1
1
0
Queue Operation
No queue operation
First opcode byte fetched from the queue
Subsequent byte fetched from the queue
Empty the queue
Read Strobe indicates thatthe 80186 is performing a memory or I/O read cycle.
Fill is active LOWforT2, T3, and Tw of any read cycle. It is guaranteed notto go
LOW in T2 until after the Address Bus is floated. RD is active LOW, and floats
during "HOLD." RD is driven HiGH for one clock during Reset, and then the
output driver is floated. "A weak internal pull-up mechanism on the RD line hols
it HIGH when the line is not driven. During RESET ~ pin iuampled to
determine whether the 80186 should provide ALE, WR, and RD, or if the
Queue-Status should be provided. Fill should be connected to GND to provide
Queue-Status data.
ARDY
55
I
Asynchronous Reljdy informs the 80186 that the addressed memory space or
I/O device will complete a data transfer. The ARDY input pin will accept an
asynchronous input, and is active HIGH. Only the riSing edge is internally
synchronized by the 80186. This"means that the falling edge of ARDY must be
synchronized to the 80186 clock. If connected to. Vee, no WAIT states are
inserted. Asynchronous ready (ARDY) or synchronous ready (SRDY) must be
active to terminate a bus cycle.
SRDY
49
I
Synchronous Ready must be synchronized externally to the 80186. The use of
SRDY provides a relaxed system-timing specification on the Ready input. This
is accomplished by eliminating the one-half clock cycle which is 'required for
internally resolving the signal level when using the ARDY input. This line is
active HIGH. If this line is connected to Vee, no WAIT states are inserted.
Asynchronous ready (ARDY) or synchronous ready (SRDY) must be active
before a bus cycle is terminated. If unused, this line should be tied LOW.
LOCK
48
0
LOCK output indicates that other system bus masters are not to gain control of
the system bus while LO~K is active LOW. The LOCK signal is requested by the
LOCK prefix instruction and is activated at the beginning of the first data cycle'
associated with the instruction following the LOCK prefix. It remains active
until the completion of the instruction following the LOCK prefix. No prefetches will occur while LOCK is asserted. LOCK is active LOW, is driven HIGH
for one clock during RESET, and then floated. If unused, this line should be
tied LOW.
3-361
"'FN·O~17C
IAPX186
Table 1. 80186 Pin Description (Continued)
Symbol
SO,S1,S2
Pin
No.
Type
Name and Function
52-54
0
Bus cycle status SO-52 are encoded to provide bus-transaction information:
80186 Bus Cycle Status Information
S2
S1
SO
Bus Cycle Initiated
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt Acknowledge
Read I/O
Write I/O
Halt
Instruction Fetch
Read Data from Memory
Write Data to Memory
Passive (no bus cycle)
The status pins float during "HOLD."
S2 may be used as a logical M/IO indicator, and 51 as a DT/R indicator.
The status lines are driven HIGH for one clock during Reset, and then floated
until a bus cycle begins.
HOLD (input)
HLDA (output)
50
51
a
I
HOLD Indicates that another bus master is requesting the local bus. The
HOLD input is active HIGH. HOLD may be asynchronous with respect to the
80186 clock. The 80186 will issue a HLDA (HIGH) in response to a HOLD
re~uest at the end of T4 orTl. Simultaneous with the issuance of HLDA, the
80 86 will float the local bus and control lines. After HOLD is detected as
being LOW, the 80186 will lower HLDA. When the 80186 needs to run
another bus cycle, it will again drive the local bus and. control lines.
UCS
34
a
Upper Memory Chip Select is an active LOW output whenever a memory
reference is made to the defined upper portion (1 K-256K block) of memory.
This line is not floated during bus HOLD. The address range activating UCS is
software programmable.
LCS
33
a
Lower Memory Chip Select is active LOW whenever a memory reference is
made to the defined lower portion (1K-256K) of memory. This line is not
floated during bus HOLD. The address range activating LCS is software
programmable.
38,37,36,35
a
Mid-Range Memory Chip Select sign~ls are active LOW when a memory
reference is made to the defined mid-range portion of memory (8K-512K).
These lines are not floated during bus HOLD. The address ranges activating
1\ii'CSli-3 are Software programmable.
25
Peripheral Chip Select signals 0-4 are active LOW when a reference is made to
the defined peripheral area (64K byte I/O space). These lines are not floated
during bus HOLD. The address ranges activating PCSO-4 are software
programmable.
MCSO-3
1'CS1-4
27,28,29,30
a
a
PCS5/A1
31
a
Peripheral Chip Select 5 or Latched A1 may be programmed to provide a sixth
peripheral chip select, or to provide an internally latched A 1 signal. The
address range activating PCS5 is software programmable. When programmed
to provide latched A1, rather than PCS5, this pin will retain the previously
latched value of A1 during a bus HOLD. A1 is active HIGH.
PCS6/A2
32
a
Peripheral Chip Select 6 or Latched A2 may be programmed to provide a
seventh peripheral chip select, or to provide an internally latched A2 signal.
The address range activating PCS6 is softwa~ogrammable. When programmed to provide latched A2, rather than PCS6, this pin will retain the
previously latched value of A2 during a bus HOLD. A2 is active HIGH.
DT/R
40
a
Data Transmit/Receive controls the direction of data flow through the external
8286/8287 data bus transceiver. When LOW, data is transferred to the 80186.
When HIGH the 80186 places write data on the data bus.
DEN
39
a
Data Enable is provided as an 8286/8287 data bus transceiver output enable.
DEN is active LOW during each memory and I/O access. DEN is HIGH whenever
DT/R' changes state.
PCSO
3-362
AFN'()2217t.
•
inter
IAPX 186
Segment Registers
FUNCTIONAL DESCRIPTION
Four 16-bit special purpose registers select, at any
given time, the segm'ents of memory that are immediately addressable for code, stack, and data. (For
usage, refer to Memory Organization.)
Introduction
The following Functional Description describes the
base architecture of the iAPX 186. This architecture
is common to the iAPX 86, 88, and 286 microprocessor families as well. The iAPX 186 is a very high
integration 16-bit microprocessor. It combines 15-20
of the most common microprocessor system components onto one chip while providing twice the performance of the standard iAPX 86. The 80186 is object
code compatible with the iAPX 86, 88 microprocessors and adds 10 new instruction types to the existing iAPX 86, 88 instruction set.
Base and Index Registers
Four of the general purpose registers may also be
used to determine offset addresses of operands in
memory. These registers may contain base addresses or indexes to particular locations within a
segment. The addressing mode selects the specific
registers for operand and address calculations.
Status and Control Registers
Two 16-bit special purpose registers record or alter
certain aspects of the 80186 processor state. These
are the Instruction Pointer Register,. which contains
the offset address of the next sequential instruction
to be executed, and the Status Word Register, which
contains status and control flag bits (see Figures 3a
and 3b).
iAPX 186 BASE ARCHITECTURE
The iAPX 86, 88, 186, and 286 family all contain the
same basic set of registers, instructions, and
addressing modes. The 80186 processor is upward
compatible with the 8086, 8088, and 80286 CPUs.
Register Set
. The 80186 base architecture has fourteen registers
as shown in Figures 3a and 3b. These registers are
grouped into the following categories.
Status Word Description
The Status Word records specific characteristics of
the result of logical and arithmetic instructions (bits
0,2,4,6,7, and 11) and controls the operation of the
80186 within a given operating mode (bits 8, 9, and
10). The Status Word Register is 16-bits wide. The
function of the Status Word bits is shown in Table 2.
General Registers
Eight 16-bit general purpose registers used to contain arithmetic and logical operands. Four of these
(AX, BX, CX, and OX) can be used as 16-bit registers
or split into pairs of separate 8-bit registers.
SPECIAL
REGISTER
FUNCTIONS
1&-81T
REGISTER
NAME
7
BYTE
ADDRESSABLE
(8·BIT
REGISTER
NAMES
SHOWN)
07
15
0
::
1
AH
AL
DH
DL
cx
CH
CL
BX
BH
SL
CS
}
OS
DATA SEGMENT SELECTOR
)
LDOPISHIFTJREPEATICOUNT
SS
STACK SEGMENT SELECTOR
}
BASE REGISTERS
ES
BP
SP
' E X T R A SEGMENT SELECTOR
SEGMENT REGISTERS
SI
01
0
~ CODE SEGMENT SELECTOR
MULTIPLY/DIVIDE
1/0 INSTRUCTIONS
-,
}
-
)
INDEX
REGIST~RS
I
15
F
IP
STACK POINTER
15
I
0
I------~.
STATUS WORD
INSTRUCTION POINTER
STATUS AND CONTROL
REGISTERS
GENERAL
REGISTERS
Figure
3a. 80186 General Purpose Register Set
3-363
AFN'()2217C
inter
iAPX 186·
STATUS FLAGS
CARRY - - - - - - - - - - - - - - - - - - - - - - - ,
PARITY - - - - - - - - - - - - - - - - - - - ,
AUXILIARYCARRY - - - - - - - - - - - - - - - - ,
ZERO - - - - - - - - - - - - ,
CONTROL FLAGS
' - - - - - - TRAP FLAG
' - - - - - - - - - INTERRUPT ENABLE
' - - - - - - - - - - - DIRECTION FLAG
~
INTEL RESERVED
Figure 3b. Status Word Format
Table 2. Status Word Bit Functions
Bit
Position
Name
Function
0
CF
Carry Flag-Set on high-order bit
carry or borrow; cleared otherwise
2
PF
Parity Flag-Set if low-order 8 bits
of result contain an even number of
1-blts; cleared otherwise
4
AF
Set on carry from or borrow to the
low order four bits of AL; cleared
otherwise
6
ZF
Zero Flag-Set if result is zero;
cleared otherwise
7
SF
Sign Flag-Set equal to high-order
bit of result (0 if positive, 1 if negative)
8
TF
Single Step Flag-Once set, a Single step interrupt occurs after the
next instruction executes,. TF is
cleared by the single step Interrupt.
9
IF
Interrupt-enable Flag-When set,
maskable interrupts Will cause the
CPU to transfer control to iln interrupt vector specified location,
10
OF
Direction Flag-Causes string
instructions to auto decrement
the appr,opriate index register
when set. Clearing OF causes
auto' increment.
11
OF
Overflow Flag-Set if the signed
result cannot be expressed
within the number of bits in the
destination operand; cleared
otherwise
manipulation, control transfer, high-level instructions, and processor control. These categories are
summarized in Figure 4.
An 80186 instruction can reference anywhere from
zero to several operands. An operand can reside in a
register, in the instruction itself, or in memory. Specific operand addressing modes are discussed later.
in this data sheet.
Memory Organization
Memory is organized in sets of segments. Each segment is a linear contiguous sequence of up to 64K
(216 ) 8-bit bytes. Memory is addressed using a twocomponent address (a pointer) that consists of a
16-bit base segment and a 16-bit offset. The 16-bit
base values are contained in one of four internal
segment registers (code, data, stack, extra). The
physical address is calculated by shifting the base
value LEFT by four bits and adding the 16-bit offset
value to yield a 20-bit physical address (see Figure 5).
This allows for a 1 MByte physical address size.
All instructions that address operands in memory
must specify the base segment and the 16-bit offset
value. For speed and compact instruction encoding,
the segment register use,d for physical address generation is implied by the addressing mode used (see
Table 3). These rules follow the way programs are
written (see Figure 6) as independent modules that
require areas for code and data, a stack, and access
to external data areas.
Instruction Set
The instruction set is divided into seven categories:
data transfer, arithmetic, shift/rotate/logical, string
3-364
Special segment override instruction prefixes allow
the implicit segment register selection rules to be
overridden for special cases. The stack, data, and
extra segments may coincide for simple programs.
AFN'()2217C
IAPX186
GENERAL PURPOSE
MOVS
INS
OUTS
Move byte or word string
Pop word off stack
Push all registers on stack
Pop all registers from stack
Exchange byte or word
CMPS
SCAS
LODS
Compare byte or word string
Scan byte or word string
Translate byte
REP
REPE/REPZ
REPNE/REPNZ
MOV
Move byte or word
PUSH
Push word onto stack
POP
PUSHA
POPA
XCHG
XLAT
Input byte or word
Output byte or word
LES
OR
XOR
TEST
FLAG TRANSFER
Load AH register from flags
Store AH register in flags
PUSHF
POPF
Push flags onto stack
Pop flags off stack
Repeat while not equal/not zero
"Not" byte or word
"And" byte or word
"Inclusive or" byte or word
NOT
AND
Load effective address
Load pOinter using DS
Load pOinter using ES
LAHF
SAHF
Repeat
Repeat while equal/zero
LOGICALS
ADDRESS OBJECT
LEA
LDS
Load byte or word string
Store byte or word string
STOS
INPUT/OUTPUT
IN
OUT
Input bytes or word string
Output bytes or word string
"Exclusive or" byte or word
"Test" byte or word
SHIFTS
SHUSAL
SHR
SAR
Shift logical/arithmetic left byte or word
Shift logical right byte or word
Shift arithmetic right byte or word
ROTATES
ADDITION
ADD
ADC
INC
AAA
DAA
ROL
Add byte or word
ROR
RCL
Add byte or word with carry
Increment byte or word by 1
ASCII adjust for addition
CMP
AAS
DAS
FLAG OPERATIONS
Decimal adjust for addition
AAM
Set carry flag
STC
CLC
Subtract byte or word
Clear carry flag
Complement carry flag
CMC
STD
CLD
STI
Subtract byte or word with borrow
Decrement byte or word by 1
Negate byte or word
Compare byte or word
Set direction flag
Clear direction flag
Set interrupt enable flag
Clear interrupt enable flag
CLI
ASCII adjust for subtraction
Decimal adjust for subtraction
EXTERNAL SYNCHRONIZATION
MULTIPLICATION
MUL
IMUL
Rotate through carry left byte or word
Rotate through carry right byte or word
RCR
SUBTRACTION
SUB
SBB
DEC
NEG
Rotate left byte or word
Rotate right byte or word
Multiply byte or word unsigned
Integer multiply byte or word
ASCII adjust for multiply
HLT
WAIT
ESC
Halt until interrupt or reset
Wait for TEST pin active
Escape to extension processor
LOCK
Lock bus during next instruction
No operation
NO OPERATION
DIVISION
DIV
IDIV
Divide byte or word unsigned
Integer divide byte or word
NOP
AAD
ASCII adjust for division
CBW
Convert byte to word
CWD
Convert word to doubleword
ENTER
LEAVE
BOUND
HIGH LEVEL INSTRUCTIONS
Format stack for procedure entry
Restore stack for procedure exit
Detects values outside prescribed range
Figure 4. IAPX 186 Instruction Set
3-365
AFN-02217C
iAPX186
CONDITIONAL TRANSFERS
I,
UNCONDITIONAL TRANSFERS
JA/JNBE
Jump if above/not below nor equal
CALL
JAE/JNB
Jump if above or equal/not below
RET
Call procedure
Return from procedure
JB/JNAE
Jump if below/not above nor equal
JMP
Jump
JBE/JNA
Jump if below or equal/not above
JC
Jump if carry
JE/JZ
Jump if equal/zero
ITERATION CONTROLS
JG/JNLE
Jump if greater/not less nor equal
LOOP
Loop
JGE/JNL
Jump if greater or equal/not less
LOOPE/LOOPZ
Loop if equal/zero
JUJNGE
Jump if less/not greater nor equal
LOOPNE/LOOPNZ
Loop if not equal/not zero
JLE/JNG
Jump if less or equal/not greater
JCXZ
Jump if register CX = 0
JNC
Jump if not carry
JNE/JNZ
Jump if not equal/not zero
JNO
Jump if not overflow
INTERRUPTS
JNP/JPO
Jump if not parity/parity odd
INT
Interrupt
JNS
Jump if not sign
INTO
Interrupt if overflow
JO
Jump if overflow
IRET
Interrupt return
JP/JPE
Jump if parity/parity even
JS
Jump If sign
Figure 4. iAPX 186. Instruction Set (continued)
To access operands that do not reside in one of the
r - --,
four immediately available segments, a full 32-bit
pOinter can be used to reload both the base (segment) and offset values.
I
I
BiB
ODE
MODULE A
DATA
I
t[SH='F=TL=E:FT~4!,BI!!,TS{1~'='~3~4::J1 ~i~~ ENT}
1
2
3
19
t
4
! I
0
0
.."___
I
.,0
0
0
2
2
[~Iro~~o~,=Z'1-1..._~':S::5=J
~
I, ,
kgg~CE~~
CPU
IOFFSET
MODULE B
0
r,.-,--i----,
CODE
0
3
6
2
I
DATA
PHYSICAL ADDRESS
+
"
0
TO MEMORY
STACK
PROCESS
EXTRA
STACK
SEGMENT
REGISTERS
Figure 5. Two Component Address
Table 3. Segment Register Selection Rules
Memory
Reference
Needed
Segment
Register
Used
PROCESS
Instructions
Code (CS)
Stack
Stack (SS) All stack pushes and
pops; any memory references which use BP Register as a base register.
Extra (ES) All string instruction
references which use
the. 01 register as an
index.
Data (OS) All other data references.
External
Data
(Global)
Local Data
DATA
Implicit Segment
Selection Rule
BLOCK 1
Instruction prefetch and
immediate data.
PROCESSD
DATA
BLOCK 2
I
I
L ___ J
MEMORY
Figure 6. Segmented Memory Helps
Structure Software
3-366
AFN.()2217C .
inter
IAPX 186
Addressing Modes
'Data Types
The 80186 provides eight categories of addressing
modes to specify operands. Two addressing modes
are provided for instructions that operate on register
or immediate operands:,
The 80186 directly supports the following data types:
,
• Integer: A signed binary numeric value contained
in an 8-bit byte or a 16-bit word. All operations
assume a 2's complement representation. Signed
• Register Operand Mode: The operand is located in
one of the 8- or 16-bit general registers. "
• Immediate Operand Mode: The operand is included in the instruction.
•
•
Six modes are provided to specify the location of an
operand in a memory segment. A memory operand
address consists of two 16-bit components: a segment base and an offset. The segment base is supplied by a 16-bit segment register either implicity
chosen by the addressing mode or explicitly chosen
by a segment override prefix. The offset, also called
the effective address, is calculated by summing any
combination of the following three address
elements:
•
•
•
• the displacement (an 8- or 16-bit immediate value
contained in the instruction);
• the base (contents of either the BX or BP base
registers); and
• the index (contents of either the SI or 01 index
registers).
•
• Floating Point: A signed 32-, 64-, or 80-bit real
number representation. (Floating point operands
are supported using the iAPX 186/20 Numeric Oata
Processor configuration.)
Any carry out from the 16-bit addition is ignored.
Eight-bit displacements are sign extended to 16-bit
values.
In general, individual data elements must fit within
defined segment limits. Figure 7 graphically
represents the data types supported by the iAPX 186.
Combinations of these three address elements
define the six memory addressing modes, described
below.
• Direct Mode: The operand's offset is contained in
the instruction as an 8- or 16-bit displacement
element.
• Register Indirect' Mode: The operand's offset is in
one of the registers SI, 01, BX, or BP.
• Based Mode: The operand's offset is the sum of an
8- or'16-bit displacement and the contents of ,a
base register (BX or BI:').'
32- and 64-bit integers are supported using the
iAPX 186/20 Numeric Oata Processor.
Ordinal: An unsigned binary numeric value contained in an 8-bit byte or a 16-bit word.
Pointer: A 16~ or ~2-bit quantity, composed of a
16-bit Offset component or a 16-bit segment base
component in addition to a 16-bit offset
component.
String: A contiguous sequence of bytes or words.
A string may contain from 1 to 64K bytes.
ASCII: A byte representation of alphanumeric and
control characters using the' ASCII standard of
character representation.
BCD: A byte (unpacked) representation of the decimal digits 0-9.
Packed BCD: A byte (packed) representation of
two decimal digits (0-9). One digit is stored in each
nibble (4-bits) of the byte.
1/0 Space
The I/O space consists of 64K 8-bit or 32K 16-bit
ports. Sepa'rate instructions address the I/O space
with either an' 8-bit port address, specified in the
instruction, or a 16-bit port address in the OX regis-'
ter. 8-bit port addresses are zero eXtended such that
A1s-Aa arEi LOW. I/O port addresses OOF8(H) through
, OOFF(H) are reserved.
• Indexed Mode: The operand's offset is the sum of
an 8- or 16-bit displacement and the contents of an
index register (SI or 01).
• Based Indexed Mode: The operand's offset is the
sum of the contents of a base register and an index
register.
• Based Indexed Mode with Displacement: The
operand's offset is the sum of a base register's
contents, an index register's contents, and an 8- or ,
16-bit displacement.
'
3-367
Interrupts
An interrupt tranSfers, execution to a new programlocation. The old program address (CS:IP) and machine state (Status Word) are saved on the stack to
allow resumption of the interrupted program. Interrupts fall into three classes: hardware initiated, INT
instructions, and instruction exceptions. Hardware
initiated interrupts occur in response to an external
input and are' classified as non-maskable or
maskable.
ilFN·02217C
IAPX 186
7
Programs may cause an interrupt with an INT Instruction. Instruction exceptions occur when an unusual condition, which prevents further instruction
processing, is detected while attempting to execute
an instruction. If'the exception was caused byexecuting an ESC instruction with. the ESC trap bit set
in the relocation register, the return instruction will
point to the ESC instruction, or to the segment override prefix immediately preceding the ESC instruction if the prefix was present. In all other cases, the
return address from an exception will point' at the
instruction immediately following the instruction
causing the exception.
•
rrnTfTTl
U-.:..--I
SIGNED
BYTE
SIGN BIT ~I--I
MAGNITUDE
rrrrrrrn
7
UNSIGNED
BYTE
•
L-.:....-J
~MAGNITUDE
1514+ 1
0
87
0
II' iii Iii iii iii
S:~=g
j,j
SIGN BIT...J L.IL-=M'iis,;~AG;;;N;;;IT",UDn;E;---'
SIGNED 31
+3
+2
1615 +1
A table containing up to 256 pointers defines the
proper interrupt service routine for each interrupt.
Interrupts 0-31, sOlne of which are used for instruction exceptions, are reserved. Table 4 shows the
80186 predefined types and default priority levels.
For,each interrupt, an 8-bit vector must be supplied
to the 80186 which identifies the appropriate table
entry. Exceptions supply the interrupt vector internally. In addition, internal peripherals and noncascaded external interrupts will generate their own
vectors through the internal interrupt controller. INT
instructions contain or imply the vector and allow
access to all 256 interrupts. Maskable hardware initiated interrupts supply the 8-bit vector to the CPU
during an interrupt acknowledge bus sequence.
Non-maskable hardware interrupts use a predefined
internally supplied vector.
0
I li'li'! I"l Iii 'Ii i 'I'il Ii' ')
~~:~~'Ilii
SIGNBITJ ...
IL..;;M-=SB=--_ _M"'A"'G""NITU=D~£----....
+7
+6
SIGNED 63
+5
+4
48 47
w~~"if.1I
+3
+2
3~1
+1
16 15
I I 1 I I
SIGN BIT jL.,'-..::M=SB=----;::M~AG:;ON;;;ITU;;;D:;;;E,-----....J
15
+1
UN~~gli Ii
0
liill' Ii I' I 'I
,LMSB
MAGNITUDE
BINARY 7
+N
7
0
rrrrrrrn
DECIMAL~
+1
DI~C: N
(BCD)
7
+N
BCD
DIGIT 1
7
0
ASCII
CHARACTER.
+1
7
PACKED~
+1
MOST
SIGNIFICANT DIGIT
715
0
+1
0715
BYTE/WORD I
+3
+2
0
0
'I'iilii')"'j"')
•••
BYTEIWORD N
1615
BYTEIWORD 0
+1
0
Iiii I', iii iii Iii iii i i i i,1 Ii i i Iii i I
i
I
I
SELECTOR
79+9
FL~:r~
Interrupt Sources
ASCII
CHARACTER.
07
LEAST
SIGNIFICANT DIGIT
0
~
POINTER
0
l----I
l----I
31
0
liii Iilil'" I'ii I
L--L.....I
715 +N
'0
BCD
DIGIT 0
07
ASCII
CHARACTER,
+N
,STRING
0
1'"I! Ii I"'jii')
ASCII~
BCD
07
(iiiliiiJi"Jiill
CODED
+8
+7
II'I-,_A--....
SIGN BIT ....
OFFSET
+6
+5
+4
+3
+2
+1
o •
----L-........---'L...-........- - - ' _........- - ' _...
EXPONENT
MAGNITUDE
The 80186 can service interrupts generated by software or hardware. The software interrupts are
generated by specific instructions (INT, ESC, unused
OP. etc.) or the results of condition,S specified by
instructions (array bounds check, INTO, DIV, IDIV,
etc.). All interrupt sources are serviced by an indirect
call through an element of a vector table. This vector
table is indexed by using the interrupt vector type
(Table 4), multiplied by four. All hardware-generated
, interrupts are sampled at the end of each instruction.
Thus, the softWare interrupts will begin service first.
Once the service routine is entered and interrupts
are enabled, any hardware source of sufficient
priority can in~errupt the service routine in progress.
NOTE:
'SUPPORTED BY iAPX 188/20 NUMERIC DATA PROCESSOR
CONFIGURATION.
The, software generated 8Q186 interrupts are
described below.
DIVIDE ERROR EXCEPTION (TYPE 0)
Figure 7. iAPX 186 Supported Data Types
Generated when a DIV 6r IDIV instruction quotient
cal'!not be expressed in the number of bits in the
destination.
3-368
AFN.02217C
IAPX 186
Table 4. 80186 Interrupt Vectors
Interrupt Name
Divide Error
Exception
Single Step
Interrupt
NMI
Breakpoint
Interrupt
INTO Detected
Overflow
Exception
Array Bounds
Exception
Unused-Opcode
Exception
ESC Opcode
Exception
Timer 0 Interrupt
Timer 1 Interrupt
Timer 2 Interrupt
Reserved
DMA 0 Interrupt
DMA 1 Interrupt
INTO Interrupt
INT1 Interrupt
INT2 Interrupt
INT3 Interrupt
Vector Default
Type Priority
INTO DETECTED OVERFLOW EXCEPTION
(TYPE 4)
Generated during an INTO instruction if the OF bit is
set.
Related
Instructions
0
*1
1
12**2
DIV,IDIV
All
2
3
1
*1
All
INT
4
*1
. INTO
5
*1
BOUND
6
*1
7
'*1'*'*'*
Undefined
Opcodes
ESC Opcodes
8
18
19
9
10
11
12
13
14
15
2A****
28****
2C****
ARRAY BOUNDS EXCEPTION (TYPE 5)
Generated during a BOUND instruction if the array
index is outside the array bounds. The array bounds
are loc~ted in memory at' a location indicated by one
of the instruction operands. The other operand indicates the value of the index to" be checked.
" EXCEPTION (TYPE 6)
UNUSED OPCODE
Generated if execution is attempted on undefined
opcodes.
ESCAPE OPCODE EXCEPTION (TYPE 7)
Generated if execution is attempted of ESC opcodes
(D8H-DFH). This exception will only be generated if a
bit in the relocation register is set. The return address of this exception will point to the ESC instruction causing the exception. If a segment override
prefix preceded the ESC instruction, tlie return address will point to the segment override prefix.
3
4
5
6
7
8
9
NOTES:
'1. These are generated as the result of an instruction
execution .
. "2. This is handled as in the 8086.
..··3. All three timers constitute one source of request to the
interrupt controller. The Timer interrupts all have the same
default priority level with respect to all other interrupt
sources. However, they have a defined priority ordering
amongst themselves. (Priority 2A is higher priority than
2B.) Each Timer interrupt has a separate vector type
number.
.
4. Default priorities for the interrupt sources are used only if
the user does not program each source into a unique
".
priority level.
'''5. An escape opcode will cause a trap only if the proper bit is
set in the peripheral control block relocation ~egister.
SINGLE·STEP INTERRUPT (TYPE 1)
Generated after most instructions if the TF flag is set.
Interrupts will not be generated after prefix instructions (e.g., REP), instructions which modify segment
registers (e.g., POP DS), or the WAIT instruction.
NON·MASKABLE INTERRUPT-NMI (TYPE 2)
An external interrupt source which cannot be
masked.
.
BREAKPO.INT INTERRUPT (TYPE 3)
A one-byte version of the INT instruction. It uses 12
as an index into the service routine address table
. (because it is a type 3 interrupt).
.
Hardware-generated interrupts are divided into two
groups: maskable interrupts and non-maskable interrupts. The 80186 provides maskable hardware interrupt request pins INTO-INT3. In addition,
maskable interrupts may be generated by the 80186
integrated DMA controller and the integrated timer
unit. The vector types for these interrupts is shown in
Table 4. Software enables these inputs by setting the
interrupt flag bit (IF) in the Status Word. The interrupt
controller is discussed in the peripheral section of
this data sheet.
Further maskable interrupts are disabled while
servicing an interrupt because the IF bit is reset as
part of the response to an interrupt or exception. The
saved Status Word will reflect the enable status of the
processor prior to the interrupt. The interrupt flag
will remain zero unless specifically set. The interrupt
return instruction restores the Status Word, thereby
restoring the original status of IF bit. If the interrupt
return re-enables interrupts, and another interrupt is
pending, the 80186 will immediately service the
highest-priority interrupt pending, I.e., no instructions of the main line program will be executed.
Non-Maskable Interrupt Request (NMI)
A non-maskable interrupt (NMI) is also provided.
This interrupt is serviced regardless ofthe state of
the IF bit. A typical use of NMI would be to activate a
power failure routine. The activation of this input
3-369
AFN.()2217C
"m_1" .
III-e-
IAPX186
causes an interrupt with an internally supplied vector
value of 2. No external interrupt acknowledge sequence is performed. The IF bit is cleared at· the
beginning of an NMI interrupt to prevent maskable
interrupts from being serviced.
recommended with this oscillato·r. If an external oscillator is used, it can be connected directly to input pin
X1 in lieu of a crystal. The output of the oscillator is
not directly available outside the iAPX 186. The
recommended crystal configuration is shown in
Figure 8.
Single-Step Interrupt
The 80186 has an internal interrupt that allows programs to execute one instruction at a time. It is called
the single-step interrupt and is controlled by the
single-step flag bit (TF) in the Status Word. Once this
bit is set, an internal single-step interrupt will occur
after the next instruction has been executed. The
interrupt clears the TF bit and uses an internally
supplied vector of 1. The IRET instruction is used to
set the TF bit and transfer controHo the next instruction to be single-stepped.
X,r-----------~
80186
c::::::J
x MHz CRYSTAL
T
20pF
16
12
Initialization and Processor Reset
Processor initialization or startup is accomplished
by driving the RES input pin Law. RES forces the
80186 to terminate all execution and local bus activity. No instruction or bus activity will occur as long
as RES is active. After RES becomes inactive and an
internal processing· interval, elapses, the 801.86
begins execution with the instruction at physicallocation FFFFO(H). RES also sets some registers to
predefined values as shown in Table 5.
Table 5. 80186 Initial Register State after RESET
Status Word
Instruction Pointer
Code Segment
Data Segment
Extra Segment
Stack Segment
Relocation Register
UMCS
, F002(H)
OOOQ(H)
Figure 8. ·Recommended iAPX 186 Crystal
Configuration
Clock Generator
The iAPX 186 clock generator provides the 50% duty
cycle processor clock for the iAPX 186. It does this by
dividing the oscillator output by 2 forming the symmetrical clock. If an external oscillator is used, ·the
state of the clock generator will change on the falling
edge of the oscillator signal. The CLKOUT pin provides the processor clock signal for use outside the
iAPX 186. This may be used to drive other system
components. All timings are referenced to the output
clock.
FFFF(H)
OOOO(H)
OOOO(H)
OOOO(H)
20FF(H)
FFFB(H)
iAPX 186 CLOCK GENERATOR
The iAPX 186 provides an on-chip clock generator
for both internal and external clock generation. The
clock generator features a crystal oscillator, a divideby·two counter, synchronous and asynchronous
ready inputs, and reset circuitry.
.
Oscillator
The oscillator circuit of the iAPX 186 is designed to
be used with a parallel resonant fundamental mode
crystal. This is used as the time base for the iAPX 186:
The crystal frequency selected will be double the
CP\J clock frequency. Use of an LC or RC circuit is not
READY Synchronization
The iAPX 186 provides both synchronous and asynchronous ready inputs. Asynchronous ready synchronization is accomplished by circuitry which
samples ARDY in the middle of T2, T3 and again in
the middle of each Tw until ARDY is sampled
HIGH. One·half CLKOUT cycle of resolution time is
used. Full synchronization is performed only on the
rising edge of ARDY, I.e." the falling edge of ARDY
must be synchronized to the CLKOUT signal if it
will occur during T2, T3 or Tw. High-to-LOW transi·
tions of ARDY must be performed synchronously
to the CPU Clock.
A second ready input (SADy) is provided to interface with externally synchronized ready signals.
This input is sampled at the end of T2, T3 and again
at the end of each'T"" until it is sampled HIGH. By
using this input rather than the asynchronous
ready input, t.he half-clock cycle resolution time
penalty is eliminated.
AFN·02217C
IAPX 186
This input must satisfy set-up and ho.ld times to.
guarantee pro.per o.peratio.n o.f the circuit.
In additio.n, the iAPX 186, as part o.f the integrated
chip-select Io.gic, has the capability to. pro.gram WAIT
states fo.r memo.ry and peripheral blo.cks. This is discussed in the Chip Select/Ready Lo.gic descriptio.n.
RESET Logic
Transceiver Control
The iAPX 186 generates two. co.ntrel Signals to. be
cennected to. 8286/8287 transceiver chips. This capability allew's the additien ef transceivers fer extra
buffering witho.ut adding external legic. These co.ntrellines, DT/R and DEN, are generated to. contro.l the
flo.w ef data thro.ugh the transceivers. The eperatio.n
o.f these signals is shewn in Table 6.
Table 6. Transceiver Control Signals Description
The iAPX 186 pro.vides bo.th a RES input pin and a
synchro.nized RESET 'pin fo.r use with o.ther system
co.mpo.nents. The RES input pin o.n the iAPX 186 is
pro.vided with hysteresis in o.rder to. facilitate po.wero.n Reset generatio.n via an RC netwo.rk. RESET is
guaranteed to. remain active fo.r at least five clo.cks
given a RES input o.f at least six clo.cks. RESET may
be delayed up to. two. and o.ne-half clo.cks behind
RES.
•
Multiple iAPX 186 pro.cesso.rs may be synchro.nized
thro.ugh the RES input pin, since this input resets
bo.th the pro.cesso.r and divide-by-two. internal co.unter in the clo.ck generato.r. In o.rder to. insure that the
divide-by-two. ceunters all begin ceunting at the
same time, the active geing edge ef RES must satisfy
a 25 ns setup time befere the falling edge ef the
80186 clo.ck input. In additien, in o.rder to. insure that
all CPUsbegin executing in the same clo.ck cycle, the
reset must satisfy a 25 ns setup time befere the rising
edge o.f the CLKOUT signal ef all the precessers.
LOCAL BUS CONTROLLER
The iAPX 186 prevides a lecal bus ce~treller to.
generate the local bus centrel signals. In additien, it
empleys a HOLD/HLDA pretecel fo.r relinquishing
the Io.cal bus to. ether bus master!? It alse'pro.vides
centro.l lines that can be used to. enable external
buffers and to. direct the flew ef data en and eff the
lecal bus.
Memory/Peripheral Control
The iAPX 186 prevides ALE, RD, and WR bus centre I
signals. The RD and WR Signals are used to. strebe
data frem memo.ry to. the iAPX 186 er to. strebe data
frem the iAPX 186 to. memery. The .ALE line prevides
a strebe to. address latches fer the multiplexed address/data bus. The iAPX 186 lecal' bus centreller
does no.t previde a memery/l/O signal. If this is required, the user will have to. use the 52 signal (which
will require external latching), make the memery and
1/0 spaces no.no.verlapping, er use enly the integrated chip-select circuitry.
3-371
Pin Name
Function
l5E!'l (Data Enable)
Enables the output drivers of
the transceivers. It is active
LOW during memory, 1/0, or
INTA cycles,
DT/R (Data Transmit/ Determines the direction of
Receive)
travel through the transceivers.
A HIGH level directs data away
from the processor during write
operations, while a LOW level
directs data toward the processor during a read operation.
Local Bus Arbitration
The iAPX 186 uses a HOLD/HLDA system o.f lecal bus
exchange. This prevides an asynchro.neus bus exchange mechanism. This means multiple masters
utilizing the same bus can eperate at separate clo.ck
frequencies. The iAPX 186 provides a single
HOLD/HLDA pair threugh which all o.ther bus masters may gain co.ntro.l ef the lecal bus. This requires
external circuitry to. arbitrate which external device
will gain centro.l ef the bus fremthe iAPX 186 when
there is mere than ene alternate lecal bus master.
When the iAPX 186 relinquishes centro.l ef the lecal
bus, it fleats DEN, RD, WR, SO-52, LOCK, ADOAD15, A16-A19, SHE, and DT/R to. allew ano.ther
master to. drive these lines directly.
The iAPX 186 HOLD latency time, i.e., the time between HOll!> request and HOLD ackno.wledge, is a
functien of the activity o.ccurring in the pro.cesso.r
when the HOLD request is received. A HOLD request'
is the highest-prio.rity activity request which the precesser may receive: higher than instructio.n fetching
er internal DMA cycles. Ho.wever, if a DMA cycle is in
pro.gress, the iAPX 186 will co.mplete the transfer
befo.re relinquishing the bus. This implies that if a
HOLD request is received just as a DMA transfer
begins, the HOLD latency time can be as great as 4
bus cycles. This will o.ccur if a DMA wo.rd transfer
eperatio.n is taking place fro.m an edd address to. an
edd address. This is a to.tal o.f 16 clocks er mo.re,"if
WAIT states are required. In additien, if lecked transfers are performed, the HOLD latency time will be
increased by the length ef the lecked transfer.
AFN'()2217C
·nt:.....l·
III-e-
IAPX186 '
In addition to providing relocation information for
the control block, the relocation register contains
bits which place the interrupt controller into iRMX
mode, and cause the CPU tojnterrupt upon encountering ESC instructions. At RES'ET, the relocation register is set to 20FFH. This.causes the control
block to start at FFOOH in I/O space. An offset map
of the 256-byte control register block is shown in
Figure 10.
Local Bus Controller and Reset
Upon receipt of a RESET pulse from the RES input,
the local bus controller will perform the following
actions:
• Drive DEN, RD, and WR HIGH for one clock cycle,
then float.
NOTE: RD is also provided with an internal pull-up
device to prevent the processor from Inadvertently
entering Queue Status mode during reset.
The integrated iAPX 186 peripherals operate semiautonomously from the CPU. Access to them for the
most part is via software read/write of the control and
data locations in the control block. Most of these
registers can be both read and written. A few
dedicated lines, such as interrupts and DMA request
provide real-time communication between the CPU
and peripherals as in a more conventional system
utilizing discrete peripheral blocks. The overall interaction and function of the peripheral blocks has not
substantially changed.
• Drive SO-S2 to the passive state (all HIGH) and
then float.
• Drive LOCK HIGH and then float.
• Tristate ADO-15, A16-19, BHE, DT/R.
• Drive ALE LOW (ALE is never floated).
• Drive HLDA LOW
INTERNAL PERIPHERAL INTERFACE
All the iAPX 186 integrated peripherals are controlled via 16-bit registers contained within an internal 256-byte control block. This control block may be
mapped into either memory or I/O space. Internal
logic will recognize the address and respond to the
bus cycle. During bus,cycles to internal registers, the
bus controller will signal the operation externally
(i.e., the RD, WR, status, address, data, etc., lines will
be driven as in a normal bus cycle), but 0 15-0, SRDY,
and ARDY will be ignored. The base address of the
control block must be on an even 256-byte boundary
(i.e., the lower 8 bits of the base address are all
zeros). All of the defined registers within this control
block may be read or written by the 80186 CPU at any
time. The location of any register contained within
the 256-byte control block is determined by the current base address of the control block:
CI1IP-SELECT/READY GENERATION
LOGIC
The iAPX 186 contains logic which provides programmable chip-select generation for both
memories and peripherals. In addition, it can be programmed to provide READY (or WAIT state) generation. It can also provide latched address bits A1 and
A2. The chip-select lines are active for all memory
and I/O cycles in their programmed areas, whether
they be generated by the CPU or by the integrated
DMA unit.
Memory Chip Selects
The control block base address is programmed via a
16-bit relocation register contained within the control block at offset FEH from the base address of the
control block (see Figure 9). It provides the upper 12
bits of the base address of the control block. Note
, that mapping the control register block into an address range corresponding to a chip-select range is
not recommended (the chip select circuitry is discussed later in this data Sheet). In addition, bit 12 of
this register determines whether the control block
will be mapped into I/O or memory space. If this bit is
1, the control block will be located in memory space,
whereas if the bit is 0, the control block, will be located in 1/0 space. H the control register block is
mapped into I/O space, the upper 4 bits ,of the base
address must be programmed as 0 (since I/O addresses are only 16 bits wide).
.
3-372
The iAPX 186'provides 6 memory chip select outputs
for 3 address areas: upper memory, lower memory,
and midrange memory. One each is provided for upper memory and lower memory, while four are provided for midrange memory.
The range for each chip select is user-programmable
and can be set to 2K, 4K, 8K, 16K, 32K, 64K, 128K
(plus 1K and 256K for upper and lower chip selects).
In addition, the beginning or base address of the
midrange memory chip select may also be selected.
Only one chip select maybe programmed to be active for any memory location at a time. All chip select
sizes are in bytes, whereas iAPX 186 memory is arranged in wor,ds. Ihis means that if, for example" 16
64K x 1 memories are used, the memory block size
will be 128K, not 64K.
IAPX 188
15
14
13
12
11
10
o
7
Relocation AddreBS BIIII Rl9-R8
ET
- ESC Trep 1 No ESC Trap (1/0)
MIlO - Rqlater block located In Memory 1110 $pace (110)
RMX - Meater Intenupt Controller mode IIRMX competlble
Intenupt Controller mode (011)
Figure 9. Relocation Register
Table 7. UMCS'Programmlng Values
OFFSET
Relocation Register
Starting
Address
(Base
Address)
FEH
DAH
FFCOO
FF800
FFOOO
FEOOO
FCOOO
F8000
FOOOO
EOOOO
DMA Descriptor. Channell
DOH
CAH
DMA Descriptor. Channel 0
COH
cocoa
A8H
Memory
Block
Size
1K
2K
4K
8K
16K
32K
64K
128K
256K
UMCS Value
(Assuming
RO=R1 =R2=0)
FFF8H
FFB8H
FF38H
FE38H
FC38H
F838H
F038H
E038H
C038H
Chip-Select Control Register.
AOH
The lower limit of this memory block is defined in the
UMCS register (see Figure 11). This register is at
offset AOH in the internal control block. The legal
values for bits 6-13 and the resulting starting address and memory block sizes are given in Table 7.
Any combination of bits 6-13 not Shown in Table 7
will result in undefined operation. After reset, the
UMCS register is programmed for a 1K area. It must
be reprogrammed if a larger upper memory area is
desired.
'
aaH
Timer 2 Control Register.
60H
5EH
Timer 1 Control Registers
58H
56H
Timer 0 Control Registers
SOH
Interrupt Controller Register.
3EH
Any internally generated 20-bit address whose upper
16 bits are greater than or equal to UMCS (with bits
0-5 '''0'') will cause UCS to be activated. UMCS bits
R2-RO are used to specify READY mode for the area
of memory defined by this chip-select register, as
explained below.
20H
Figure 10. Internal Register Map
Upper Memory CS
Lower Memory CS
The iAPX 186 provides a chip select, called UCS, for
the top of memory. The top of memory is usually used
as the system memory because after reset the iAPX
186 begins executing at memory location FFFFOH.
The iAPX 186 provides a chip select for low memory
called LCS. The bottom of memory contains the interrupt vector table, starting at location OOOOOH.
The upper limit of memory defined by this chip select
is always FFFFFH, while the lower limit is programmable. By programming the lower limit, the size of
the select bloqJ< is also defined. Table 7 shows the
relationship between the base address selected and
the size of the memory block obtained.
The lower limit of memory defined by this c~ip select
is always OH, while the upper limit is programmable.
By programming the -upper limit, the size of the
memory block is also defined. Table 8 shows the
relationship between the upper address selected and
the,size of the memory block obtained.
3-373
AFN·02217C
IAPX 186
Table 8. LMCS Programming Values
Upper
Address
Memory
Block
Size
003FFH
007FFH
OOFFFH
01FFFH
03FFFH
07FFFH
OFFFFH
1FFFFH
3FFFFH
by bits 8-14 of the MPCSregister (see Figure 13).
This register is at location ASH in the internal control
block. One and only one of bits 8-14 must be set at a
time. Unpredictable operation of the MCS lines will
otherwise-occur. Each of the four chip-select lines is
actiye for one of the four equal contiguous divisions
of the mid-range block. Thus, if the total block size is
32K, each chip select is active for 8K of memory with
MeSO being active for the first range and MCS3
being active for the last range.
LMCS Value
(Assuming
RO=R1 =R2=O)
1K
2K
4K
8K
16K
32K
64K
128K
256K
0038H
0078H
00F8H
01F8H
03F8H
07F81'f
OFF8H
1FF8H '
3FF8H
The EX and MS in MPCS relate to peripheral
functionality as descibed a later section.
The upper limit of this memory block is defined in the
LMCS, register (see Figure 12). This register is at
offset A2H in the internal control block. The legal
values for bits 6-15 and the resulting upper address
and memory block sizes are given in Table 8. Any
combination of bits 6-15 not shown in Table 8 will
result in undefined operation. After reset, the LMCS
re~ister value is undefined. However, the [CS chip, select line will not become active until the LMCS
, register is accessed.
Table g. MPCS Programming Values
Any internally generated 20-bit address whose upper
16 bits are less than or equal to LMCS (with bits 0-5
"1 ") will cause LCS to be active. LMCS register bits
R2-RO are used to specify the READY mode for the
area of memory defined by this chip-select register.
Mid-Range Memory CS
The size of the memory block defined by the midrange select lines, as shown in Table 9, is determined
15
AOHI 1
A19
14
13
12
11
15
14
MPCS Bits
14-8
8K
16K
32K
64K
128K
256K
512K
2K
4K
8K
16K
32K
64K
128K
00000018
00000108
00001008
00010001;1
00100008
01000008
10000008
9
8
7
4
6
I 1 I uI uI u I u I uI u I uI uI
3
2
1
0
All
~Igure
OFFSET:
10
Individual
Select Size
The base address of the mid-range memory block is
defined by bits 15-9 of the MMCS register (see Figure 14). This register is at offset A6H in the internal
control block. These bits correspond to bits A19-A13
of the' 20-bit memory address. Bits A12-AO of the
base address are always O. The base address may be
set at any integer multiple of the size of the total
memory block selected. For example, if the midrange block size is 32K (or the size of the block for
which each MCS line is active is 8K), the block could
be located at 10000H or 18000H, but not at 14000H,
since the first few integer multiples of a 32K memory
block are OH, 8000H, 10000H, 18000H, etc. After
reset, the contents of both of these registers is undefined. However, none of the MCS lines will be active until both the MMCS and MPCS registers are
accessed.
The iAPX 186 provides four MC(S lines which are
active within' a user-locatable memory block. This
block can be located anywhere within the iAPX 186
1M byte memory address space exclusive of the
areas defined by UCS and LCS. Both the base address and size of this memory block are
, programmable.
OFFSET:
Total Block
Size
13
12
11
11. UMCS Register
10'
9
8
lou I u u u u u I u
6'
5
I
I
3
I
2
I
1
I
0
A2H I 0
U
1
1
1
R2
Rl
RO I
~A~1~9~~~~~~~~~~~~~~A~1~1~~~~~~~~~~
Flgu,re 12, LMCS Register
3-374
AFN~17C
inter
IAPX 186
OFFSET:
A8H
I
15
1
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1M6 1M5 1M4 I M3 I M2 I Ml 1MO 1EX 1MS 1 1 I. 1 1 1 1R2 1Rl 1RO I
Figure 13. MPCS Register
15
OFFSET:
ASH
lui u 1u 1u 1U
u
1u 1 1 1 1 1 1 1 1 I
A19
1
A13
Figure 14. MMCS Register
MMCS bits R2-RO specify READY mode of operation
for all mid-range chip selects. All devices in midrange memory must use the same number of WAIT
states.
however it can only be a multiple of 1K bytes, I.e., the
least significant 10 bits of the starting address are
alwaysO.
The 512K block size for the mid-range memory chip
selects is a special case. When using 512K, the base
address would have to be at;either locations OOOOOH
or 80000H. ·If it were to be programmed at OOOOOH
when the LCS line was programmed, there would be
an internal conflict between the LCS ready generation logic and the MCS ready generation logic.
Likewise, if the base address were programmed at
80000H, there would be a conflict with the UCS ready
generatior:llogic. Since the LCS chip-select line does
riot become active until prograi'Tlmed, while the UCS
line is active at reset, the memory base can be set
only at OOOOOH. If this base address is selected,
however, the LeS range must not be programmed.
PCS5 and PCS6 can also be programmed to provide
latched address bits A1, A2. If so programmed, they
cannot be used as peripheral selects. These outputs
can be connected directly to the AO, A1 pins used for
selecting internal registers of 8-bit peripheral chips.
This scheme simplifies the hardware interface because the 8-bit registers of peripherals are simply
treated as 16-bit registers located on even boundaries in I/O space or memory space where only the
lower 8-bits of the register are significant: the upper
8-bits are "don't cares."
Peripheral Chip Selects
The iAPX 186 can generate chip selects for up to
s!lven peripheral devices. These chip selects are active for seven contig uous blocks of 128 bytes above a
programmable base address. This base address may
be located in either memory or I/O space.
Seven CS lines called PCSO-6 are generated by the
iAPX 186. The base ~ddress is user-programmable;
15
OFFSEr:
A4H
lui u 1 u
uI uI
u
lui
The starting address of the peripheral chip-select
block is defined by the PACSregister (see Figure 15).
This register is located at offset A4H in the internal
control block. Bits 15-6 of this register correspond to
bits 19-10 of the 20-bit Programmable Base Address
(PBA) of the peripheral chip-select block. Bits 9-0 of
the PBA of the peripheral chip-select block are all
zeros. Ifthe chip-select block is located in I/O space,
bits 12-15 must be programmed zero, since the I/O
address is only 16 bits wide. Table 10 shows the
address raflge -of each peripheral chip select with
respect to the PBA contained in PACS register.
u
lui
6
u
11
Al0
A19
Figure 15. PACS Register
3-375
AFN·02217C
IAPX 186
The user should program bits 15-6 to correspond to
the desired peripheral base location. PACS bits 0-2
are used to specify READY mode for PCSO-PCS3.
each chip-select range individually or to factor external READY with the integrated ready generator.
READY control consists of 3 bits for each CS line or
group of lines generated by the iAPX 186. The interpretation of the ready bits is shown in Table 12.
Table 10. PCSAddress Ranges
PCS Line
Active between Locations
PCSO
PCS1
PCS2
PCS3
PCS4
PCS5
PCS6
PBA
-PBA+127
PBA+128 -PBA+255
PBA+256 -PBA+383
PBA+384 -PBA+511
PBA+512 -PBA+639
PBA+640 - PBA+ 767
PBA + 768 - PBA +895
Table 12. READY Bits Programming
The mode of operation of the peripheral chip selects
is defined by the MPCS register (which is also used to
set the size of the mid-range memory c~ip-select
block, see Figure 16). This register is located at offset
A8H in the internal control block. Bit 7 is used to
select the function of PCS5 and PCS6, while bit 6 is
used to select whether the peripheral chip selects
are mapped into memory or I/O space. Table 11 describes the programming of these bits. After reset,
the contents of both the MPCS and the PACS registers are undefined, however none of the PCS lines
will be active until both of the MPCS and PACS registers are accessed.
Table 11. MS, EX Programming Values
Bit
MS
EX
Description
1
0
0
1
= Peripherals mapped into memory space.
= Peripherals mapped into 1/0 space.
= 5 pes lines. A1, A2 provided.
= 7 PCS lines. A1, A2 are not provided.
R1
0
0
0
0
0
1
0
1
1
1
0
0
1
1
1
1
RO Number of WAIT States Generated
0 o wait states, exterflal ROY also used.
1 1 wait state inserted, external ROY also
used.
0 2 wait states inserted, external RDYaiso
used.
1 3 wait states inserted, external RDYaiso
used.
0 o wait states, external ROY ignored.
1 1 wait state inserted, external ROY
ignored.
0 2 wait states inserted, external RD) .
ignored.
.
1 3 wait states inserted, external RD)
ignored.~
The internal ready generator operates in parallel with
external READY, not in series if the external READY
is used (R2 = 0). This means, for example, if the
internal generator is set to insert two wait states, but
activity on the externai"READY lines will insert four
wait states, the processor will only insert four wait
states, not six. This is because the two wait states
generated by the internal generator overlapped the
first two wait states generated by the external ready
signal. Note that the external ARDYand SRDY lines
are always ignored during cycles accessing internal
peripherals.
R2-RO of each control word specifies the READY
mode for the corresponding block, with the exception of the peripheral chip selects: R2-RO of PACS
set the PCSO-3 READY. mode, R2-RO of MPCS set
the PCS4-6 READY mode.
MPCS bits 0-2 are used to specify READY mode for
PCS4-PCS6 as outlined below.
READY Generation Logic -
Chip Select/Ready logic and
The iAPX 186 can generate a "READY" signal internally for each of the memory or peripheral CS lines.
The number of WAIT states to be inserted for each
peripheral or memory is programmable to provide
0-3 wait states for all accesses to the area for which
the chip select is active. In addition, the iAI;'X 186 may
be programmed to either ignore external READY for
OFFSET:
R2
Re~et
Upon reset, the Chip-Select/Ready Logic will perform the following actions:
• All chip-select outputs will be driven HIGH .
• Upon leaving RESET,' the iJCS line will be programmed to provide chip selects to a 1K block with
the accompanying READY control bits set at 011 to
15 14 13 12 11 10 9
8
7
6
5
2
1
0
A8HI1 IM6IMslM4IM3IM2IM1IMoIExIMsI1 1111 IR21R11ROI
Figure 16. MPCSReglster
3-376
AFN·02217C
intJ
IAPX 186
allow the maximum number of internal wait states
in conjunction with external Ready consideration
(Le., UMCS resets to FFFBH).
• No other chip select or READY control registers
have any predefined values after RESET. They will
not become active until the CPU accesses their
control registers. Both the PACS and MPCS registers must be accessed before the PeS lines will
become active.
DMA CHANNELS
The 80186 DMA controller provides two independent
high-speed DMA channels. Data transfers can occur
between memory and I/O spaces (e.g., Memory to
I/O) or within the same space (e.g., Memory to
Memory or I/O to I/O). Data can be transferred either
in bytes (8 bits) or in words (16 bits) to or from even or
odd addresses. Each DMA channel maintains both a
20-bit source and destination pointer which can be
optionally incremented or decremented after each
data transfer (by one or two depending on byte or
word transfers). Each data transfer consumes 2 bus
cycles (a minimum of 8 clocks), one cycle to fetch
data and the other to store data. This provides a
maximum data transfer rate of one Mword/sec or 2
MBytes/sec.
. DMA Operation
Each channel has six registers in the control block
which define each channel's specific operation. The
control registers consist of a 20-bit Source pointer (2
words), a 2Q-bit Destination pointer (2 words), a 16bit Transfer Counter, and a 16-bit Control Word. The
format of the DMA Control Blocks is shown in Table
13. The Transfer Count Register (TC) specifies the
number of DMA transfers to be performed. Up to 64K
byte or word transfers can be performed with automatic termination. The Control Word defines the
channel's operation (see Figure 18). All registers may
be modified or altered during any DMA activity. Any
changes made to these registers will be reflected
immediately in DMA operation ..
Table 13. DMA Control Block Format
Register Address
Register Name
Control Word
Transfer Count
Destination Pointer (upper 4
bits)
,
Destination Pointer
Source Pointer (upper 4 bits
Source Pointer
Ch.O
Ch.1
CAH
CBH
C6H
DAH
DBH
D6H
C4H
C2H
COH
D4H
D2H
DOH
TIMER REQUEST
DMA
CONTROL
LOGIC
INTERRUPT
REQUEST
Figure 17. DMA Unit Block Diagram
3-377
!\FN-02217C
IAPX 186
15
Ml
10
14
13
DESTINATION
DEC
INC
x ~ DON'T CARE,
Figure 18. DMA Control Register
DMA Channel Control Word Register
INT:
Each DMA Channel Control Word determines the
mode of operation for the particular 80186 DMA
channel. This register specifies:
TC:
• the mode of synchronization;
• whether bytes or words will be transferred;
• whether interrupts will be generated after the last
transfer;
• whether OMA activity wi" cease after a pro.
grammed number of DMA cycles;
• the relative priority of the DMA channel with
respect to the other DMA channel;
• whether the source pointer will be incremented,
decremented, or maintained constant after each
transfer;
• whether the source pointer addresses memory or
I/O space;
• whether the destination pOinter will be incremented, decremented, or maintained constant after each transfer; and
• whether the destination pointer wi" address
memory or I/O space,
SYN:
(2 bits)
SOURCE:INC
M/iD
The DMA channel control registers may be changed
. while the channel is operating. However, any
changes made during operation will affect the current DMA transfer..
(1/0) .
DEC
DEST:
DMA Control Word Bit Descriptions
8/W:
Byte/Word (0/1) Transfers.
ST/STOP:
Start/stop (1/0) Channel.
CHG/NOCHG:
Change/Do not change (1/0)
ST/STOP bit. If this bit is set when
writing to the control word, the
ST/STOP bit will be programmed by
the write to the control word. If this
bit is cleared when writing the control word, the ST/STOP bit will not
be altered. This bit is not stored; it
will always be a 0 on read.
Enable Interrupts to CPU on Transfer Count termination.
If set, DMA will terminate when the
contents of the Transfer Count register reach zero. The ST/STOP bit
will also be reset at this point ff TC is
set. If this bit is cleared, the DMA
unit wi" decrement the transfer
count register for each OMA cycle,
but the DMA transfer will not stop
when the contents of the TC register
reach zero.
00 No synchronizati0l'1.
NOtE: The ST bit will be cleared
automatically when the contents
of the TC register reach zero regardless of the state of the TC bit.
01 Source synchronization.
10 Destination synchronization.
11 Unused.
Increment source pOinter by 1 or 2
(depends on S/W) after each
transfer.
Source pointer is in M/IO space
INC
M/IO
Decrement source pointer by 1 or 2
(depends on 8/W) after each
transfer.
Increment destination pointer by 1
,or 2 (S/W) after each transfer.
Destination pointer is in M/IO space
(1/0).
DEC
P
3-378
Decrement destination pointer by l'
or 2 (depending on S/W) after each
, transfer.
Channel priority-relative to other
channel.
o low priority.
1 high priority.
Channels will alternate cycles if
both set at same priority level.
AFN'()2217C
inter
IAPX 186
TDRQ
0: Disable DMA requests from timer
Bit 3
2.
1: Enable DMA requests from timer
2.
Bit 3 is not used.
If both INC and DEC are specified for the same
pointer, the pointer will remain constant after each
cycle.
DMA Destination and Source Pointer
Registers
Each DMA channel maintains' a 20-bit source and a
2o-bit destination pointer. Each of these pointers
takes up two full 16-bit reQisters in the peripheral
control block. The lower four bits of the upper register contain the upper four bits of the 20-bit physical
address (see Figure 18a). These pointers may be
individually incremented or decremented after each
transfer. If word transfers are performed the pointer
is incremented or decremented by two. Each pointer
may point into' either memory or I/O space. Since the
DMA channels can perform transfers to or from odd
addresses, there is no restriction on values for the
pointer registers. Higher transfe~ rates can be obtained if all word transfers are performed to even
addresses, since this will allow data to be accessed in
a single memory access.
DMA Requests
Data transfers may be either source or destination
synchronized, that is either the source of the data or
the destination of the data may request the data
transfer. In addition, DMA transfers may be unsynchronized; that is, the transfer will take place
continually until the correct number of transfers has
occurred. When source or unsynchronized transfers
are performed, the DMA channel may begin another
transfer immediately after the end of a previous DMA
transfer. This allows a complete transfer to take place
every 2 bus cycles or eight clock cycles (assuming no
wait states). No prefetching occurs when destination
synchronization is performed, however. Data will not
be fetched from the source address until the destination device signals that It is ready to receive it. When
destination synchronized transfers are requested,
the DMA controller will relinquish control of the bus
after every transfer. If no other bus activity is initiated, another DMA cycle will begin after two processor clocks. This is done to allow the destination
device time to remove its request if another transfer
is not desired. Since the DMA controller will relinquish the bus, the CPU can initiate a bus cycle. As a
result, a complete bus cycle will often be inserted
between destination synchronized transfers. These
lead to the maximum DMA transfer rates shown in
Table 14.
DMA Transfer Count Register
. Each DMA channel maintains a Hl·bit transfer
count register (TC). This register is decremented
after every DMA cycle, regardless of the state of
the TC bit in the DMA Control Register. If the TC bit
In the DMA control word is set or unsynchronlzed
transfers are programmed, however, DMA activity
will terminate when the transfer count register
reaches zero.
Table 14. Maximum DMA Transfer Rates
Type of
Synchronization
Selected
CPU Running
CPU Halted
Unsynchronized
Source Synch
Destination Synch
2MBytes/sec
2MBytes/sec
1.3MBytes/sec
2MBytes/sec
2MBytes/sec
1 .5MBytes/sec
HIGHER
REGISTER
xxx
xxx
xxx
LOWER
REGISTER
A1S-A12
A11-A8
A7-A4
ADDRESS
ADDRESS
A19-A18 '
A3-AO
15
0
. xxx = DON'T CARE
Figure 18a. DMA Memory Pointer Register Format
.3-379,
AFN-02217C
inter
iAPX186
are programmed, a ORO must also have been
generated. Therefore, the source and destination
transfer pOinters, and the transfer count register (if
used) must be programmed before this bit is set.
DMA Acknowledge
No explicit DMA acknowledge pulse is provided.
Since both source and destination pointers are
maintained, a read from a requesting source, or a
write to a requesting destination, should be used as
the DMA acknowledge signal. Since the chip-select
lines can be programmed to be active for a given
block of memory or I/O space, and the DMA pointers
can be programmed to point to the, same given block,
a chip-select line could be used to indicate a DMA
acknowledge.
.Each DMA register may be modified while the channel is operating. If the CHG/NOCHG bit is cleared
w~en the cOfltrol register is written, the ST/STOP bit
of the control register will not be modified by the
write. If multiple channel registers are modified, it is
recommended that a LOCKED string tran,sfer be
used to prevent a DMA transfer from occurring be- '
tween updates to the ,channel registers.
DMA Priority
DMA Channels and Reset
The DMA channels may be programmed such that
one channel is always given priority over the other, or
they may be programmed such as to alternate cycles
when both have DMA requests pending. DMA cycles
always have priority over internal CPU cycles except
between locked memory accesses or word accesses
the odd memory locations; however, an external bus
hold takes priority over an internal DMA cycle. Because an interrupt request canno~ suspend Ii DMA
operation and the CPU cannot access memory dur,ing a DMA cycle, interrupt latency time will suffer
during sequences of continuous DMA cycles. An
NMI request, however, will cause aU 'internal DMA
activity to halt. This allows the CPU to quickly
respond to the NMI request.
Upon RESET, the DMA channels will perform the
following actions:
• The Start/Stop bit for each channel will be reset to
STOP.
• Any transfer in progress is aborted.,
TIMERS
The 80186 provides three internal 16-bit programmable timers (see Figure 19). Two of these are highly
'flexible and are connected to four external pins (2
per timer). They can be used to count external
events, time external events, generate nonrepetitive
waveforms, etc. The third timer is not connected to
any external pins, and is useful for real-time coding
and time delay applications. In addition, this third
timer can be used as a prescaler to the other two, or
as a DMA request source.
DMA Programming
DMA ,cycles will occur whenever the ST/STOP bit of
the Control Register is set. If synchronized transfers
DMA
REQ.
T2
INT.
REQ.
TIMER 0
MAX COUNT VAWE
I-:::-~~A~=-:.""l
MAX COUNT VAWE
CLOCK
""MAX""""'~CO~U';~~T""\!""'I\W~E
I
TIMER 2
MAX COUNT VAWE
MODE/CONTROL
WORD
INTERNAL ADDRESS/DATA IUS
ALL 18 lIT REGISTERS
Figure 19., Timer Block Diagram
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IAPX 186
Timer Operation
Since the count registers and the maximum count
registers are all 16 bits wide, 16 bits of resolution are
provided. Any Read or Write access to the timers will
add one wait state to the minimum four-clock bus
cycle, however. This Is needed to synchronize and
coordinate the internal data flows between the internal timers and the internal bus.
The timers are controlled by 11 16-bit registers in the
Internal peripheral control block. The configuration
of these registers is shown in Table 15. The count
register contains the current value of the timer. It can
be read or written at any time independent of
whether the timer Is running or not. The value of this
register will be incremented for each timer event.
Each of the timers is equipped with a MAX COUNT
register, which defines the maximum count the timer
will reach. After reaching the MAX COUNT register
value, the timer count value will reset to zero during
that same clock, i.e., the maximum count value is
never stored in the count register itself. Timers 0 and
1 are, in addition, equipped with a second MAX
COUNT register, which enables the timers to alternate thElir count between two different MAX COUNT
values programmed by the user. If a single MAX
COUNT register is used, the timer output pin will
switch LOW for a single clock, 2 clocks after the.
maximum count value has been readhed. In the dual
MAX COUNT register mode, the output pin will indicate which MAX COUNT register is currently in use,
thus allowing nearly complete freedom in selecting
waveform duty cycles. For the timers with two MAX
-COUNT registers, the RIU bit in the control register
determines which is used for the comparison.
The timers have several programmable options.
• All three timers can be set to halt or continue on a
terminal count.
• Timers 0 and 1 can select between internal and
external clocks, alternate between MAX COUNT
registers and be set to retrigger on external events.
• The timers may be programmed to cause an interrupt on terminal count. .
These options are selectable via the timer mode/
control word.
Timer Mode/Control Register
The mode/control register (see Figure 20) allows the
user to program the specific mode of operation or
check the current programmed status for any of the
three integrated timers.
Each timer gets serviced every fourth CPU-clock
cycle, and thus can operate at speeds up to onequarter the internal clock frequency (one-eighth the
crystal rate). External clocking of the timers may be
done at up to a rate of one-quarter of the internal
CPU-clock rate (2 MHz for an 8 MHz CPU clock). Due
to internal synchronization and pipelining of the
timer circuitr,y, a timer output may take up to 6 clocks
t9 respond to any individual clock or gate input.
15
14
13
EN
I iNti
liNT
Table 15. Timer Control Block Format
Register Offset
Tmr.O Tmr.1
Register Name
Mode/Control Word
Max Count B
Max Count A
Count Register
12
11
5
I RIU I
0
1·.... 1MC 1RTG I
4
2
p
1
I EXT I ALT
56H
54H
52H
50H
5EH
5CH
5AH
58H
Tmr.2
66H
not present
62H
60H
0
ICONTI
/
Figure 20. Timer Mode/Control Register
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IAPX 186
ALT:
The ALT bit determines which o( two MAX COUNT.
registers is used for count comparison. If ALT = 0,
register.A for that timer is always used, while if ALT =
1, the comparison will alternate between register A
and register 8 when each maximum cqunt is
reached. This alternation allows the,user to ~hange
one MAX COUNT register while the other is being
used, and thus provides a method of generating nonrepetitive waveforms. Square waves and pulse outputs of any duty cycle are a subset of available
signals obtained by 'not changing the final count
registers. The ALT bit also determines the function of
the timer output pin. If ALT is zero, the output pin will
go LOW for one clock, the clock after the maximum
count is reached; If ALT is one, the output pin will
reflect the current MAX COUNT register being used
(0/1 for 8/ A).
CONT:
Setting the CONT bit causes the associated timer to
run continuously, while resetting it causes the timer
to halt upon maximum count. If' CONT = 0 and ALT
=1, the timer will count to the MAX COUNT register A
value, reset, count to the register 8 value, reset, and
halt.
INT:
P:
The prescaler bit is ignored unless internal clocking
has been selected (EXT = 0). If the P bit is a zero, the
timer will count at one-fourth the internal CPU clock
rate. If the P bit is a one, the output of timer 2 will be ,
used as a clock for the timer. Note that the user mu~t
initializ~ and start timer 2 to obtain the prescaled
clock.
If RTG = 0, the input level-gates the internal clock on
and oft. If the input pin is HIGH, the timer will count; if
EN: '
The enable bit provides programmer control over the
timer's RUN/HALT status. When, set, the timer is ,enabled to increment subject to. the inP!Jt pin CO!'lstraints in the internal clock mode (discussed
previously). When cleared, the timer will be inhibited
from counting. All input pin transitions during the
time EN is zero will be ignored. If CONT is zero .. the
EN bit is automatically cleared upon maximum
count.
INH:
EXT:
RTG:
When RTG' = 1, the input pin detects LOW-to-HIGH
transitions. The first such transition starts the timer
running, clearing the timer value to zero on the first
clock, and then incrementing thereafter.' Further
transitions on the input pin will again reset the timer
to zero, from which it will start counting up .again. If
CONT = 0, when the timer has reached maximum
count, the EN tlit will be cleared, inhibiting further
timer activity.
The Inhibit 'btt allows for selective updating of the
enable (EN) bit. If INH is a one during the write to the
. mode/control word, then the state of the EN bit will
be modified by the write. If INH is a zero during the
write, the EN bit will be unaffected by the operation.
This bit is not stored; it will always be a 0 on a read.
The external bit selects between internal and external clocking for the timer. The external signal may be
asynchronous with respect to the 80186 clock. If this
bit is set, the timer will count LOW-to-HIGH transitions on the input pin. If cleared, it will count an
internal clock while using the inp,ut pin for control. In
this mode, the function of the external pin is defined
by the RTG bit. The maximum input to output transition latency time may be as much as 6 crocks.
However, clock inputs may ~e pipelined as closely
together as every 4 clocks without losing clock
pulses.
Retrigger bit is only active for internal clocking (EXT
= 0). In this case it determines the control function
provided by the input pin.
the input pin is LOW, the timer will hold its value. As
indicated previously, the input signal may be asynchronous with respect to the 80186 clock.
When set, the INT bit enables interrupts from the
·timer, which will be generated on every terminal
count. If the timer is configured in dual MAX. COUNT
register mode, an interrupt· will be 'ge~rated each
time the value in MAX COUNT register A is reached,
and each time the value in MAX COUNT register 8 is
reached. If this enable bit is cleared after the interrupt request has'been generated, but before a pending interrupt is serviced, the interrupt request will
still be in force. (The request is latched in the Interrupt Controller.)
Me:
The Maximum Count bit is set whenever the timer,
reaches its final maximum count value. If the timer is
configured in dual MAX COUNT register mode, this
bit will be set each time the value in MAX COUNT
register A is reached, and each time the value in MAX
COUNT register 8 is reached, This bit is set regardless of the timer's interrupt-enable bit. The MC bit
gives the' user the ability to monitor timer status
through software instead of through interrupts.
Programmer Intervention is required to clear this
bit.
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IAPX 186
RIU:
The Register In Use bit indicates which MAX COUNT
register is currently being used for comparison to the
timer count value. A zero value indicates register A.
The RIU bit cannot be written, 'I.e., its value is not
affected when the control register is written. It is
always cleared when the ALT bit is zero.
Not all mode bits are provided fortimer 2. Certain bits
are hardwired as indicated below:
ALT = 0, EXT = 0, P = 0, RTG = 0, RIU = 0
Internal interrupt sources (Timers and DMA channels) can be disabled by their own control registers
or by mask bits within the interrupt controller. The
80186 interrupt controller has its own control registers that set the mode of operation for the controller.
The interrupt controller will resolve priority among
requests that are pending simultaneously. Nesting is
provided so interrupt service routines for lower
priority interrupts may themselves be interrupted by
higher priority interrupts. A block diagram of the
interrupt controller is shown in Figure 21.
Count Registers
Each of the three timers has a 16-bit co~nt register.
The current contents of this register may be read or
written by the processor at any time. If the register is
written into while the timer is counting, the new value
will take effect in the current count cycle.
Max Count Registers
Timers 0 and 1 have two MAX COUNT registers, while
timer 2 has a single MAX COUNT register. These con-,
tain the number of events the timer will count. In
timers 0 and 1, the MAX COUNT register used can
alternate between the two max count values
whenever the current maximum count is reached,
The condition which causes a timer to reset is equivalent between the current count value and the max
count being used. This means that if the count is
changed to be above the max count value, or if the
max count value is changed to be below the current
value, the timer will not reset to zero, but rather will
count to its maximum value, "wrap around" to zero,
then count until the max count is reached.
Timers and Reset
Upon RESET, the Timers will perform the following
actions:
• All EN (Enable) bits are reset preventing timer
counting.
• All SEL (Select) bits are reset to zero. This selects
MAX COUNT register A, resulting in the Timer Out
pins going HIGH upon RESET.
INTERRUPT CONTROLLER
The 80186 can receive interrupts from a number of
sources, both internal and external. The internal interrupt controller serves to merge these requests on
a priority basis, for individual service by the CPU.
The interrupt controller has a spepial iRMX 86 compatibility mode that allows the use of the 80186
within the iRMX 86 operating system interrupt structure. The controller is set in this mode by setting bit
14 in the peripheral control block relocation register
(see iRMX 86 Compatibility Mode section). In this
mode, the internal 80186 interrupt controller functions as a "slave" controller to an el(ternal "master"
controller. Special initialization software must be included to properly set up the 80186 interrupt controller in iRMX 86 mode.
MASTER MODE OPERATION
Interrupt Controller External Interface
For external interrupt sources, five dedicated pins
are provided. One of these pins is dedicated to NMI,
non-maskable interrupt. This is typically used for
power-fail interrupts, etc. The other four pins may
function either as four interrupt input lines with internally generated interrupt vectors, as an interrupt line
and an ,interrupt acknowledge line (called the
"cascade mode") along with two other input lines
with internally generated interrupt vectors, or as two
interrupt input lines and two dedicated interrupt acknowledge ouput lines. When the interrupt lines are
,configured in cascade mode, the 80186 interrupt
controller will not generate internal interrupt
vectors.
External sources in the cascade mode use externally
generated interrupt vectors. When an interrupt is
acknowledged, two INTA cycles are initiated and the
vector is read into the 80186 on the second cycle. The
capability to interface to external 8259A programmable interrupt controllers is thus provided when the
inputs are configured in cascade mode.
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IAPX 186
Interrupt Controller Modes of Operation
before the issuance of the return from interrupt instruction. If the fully nested structure has been
upheld, the next highest-priority source with its IS bit
sel is then serviced.
The basic modes of operation of the interrupt controller in master mode are similar to the 8259A.
The interrupt controller responds identically to internal interrupts in all three modes: the difference is
only in the interpretation of function of the four external interrupt pins. The interrupt controller is set into
one of these three modes by programming the correct bits in the INTO and INT1 control registers. The
modes of interrupt controller operation are as
follows:
Cascade Mode
The 80186 has four interrupt pins and two of them
have dual functions. In the fully nested mode the four
pins are used as direct interrupt inputs and the corresponding vectors are generated internally. In the
cascade mode, the four pins are configured into interrupt input-dedicated acknowledge signal pairs.
The interconnection is shown in Figure 22. INTO is an
interrupt input interfaced to an 8259A, while
INT2/INTAO serves as the dedicated interrupt acknowledge signal to that peripheral. The same is true
for INT1 and INT3/1NTA1. Each pair can selectively be
placed in the cascade or non-cascade mode by programming the proper value into INTO and INT1 control registers. The use of the dedicated acknowledge
signals eliminates the need for the use of external
logic to generate INTA and device select signals.
Fully Nested Mode
When in the fully nested mode four pins are used as
direct interrupt requests. The vectors for these four
inputs are generated internally. An in-service bit is
provided for every interrupt source. If a lower-priority
device requests an interrupt while the in-service bit
(IS) is set, no interrupt will be generated by the interrupt controller. In addition, if another interrupt request occurs from the same. interrupt source while
the inservice bit is set, no interrupt will be generated
by the interrupt controller. This allows interrupt service routines to operate with interrupts enabled without being themselves interrupted by lower-priority
interrupts. Since interrupts are enabled, higherpriority interrupts will be serviced.
The primary cascade mode allows the capability to
serve up to 128 external interrupt sources through
the use of external master and slave 8259As. Three
levels of priority are created, requiring priority
resolution in the 80186 interrupt controller, the master 8259As, and the slave 8259As. If an external interrupt is serviced, one IS bit is set at each of these
levels. When the interrupt service routine is completed, up to three end-of-interrupt commands must
be issued by the programmer.
When a service routine is completed, the proper IS
bit must be reset by writing the proper pattern to the
EOI register. This is required to allow subsequent
interrupts from this interrupt source and to allow
servicing of lower-priority interrupts. An EOI command is issued at the end of the service routine just
TIMER TIMER TIMER
o
1
2
DMA
1
INTO
INT1
INT2
INT3
NMI
INTERRUPT
REQUEST REG.
INTERRUPT
MASK REG.
DMAO
CONTRDL REG.
DMA1
CONTROL REG.
EXT. INPUT 0
CONTROL REG.
EXT. INPUT 1
CONTROL REG.
INTERRUPT
PRIORITY
RESOLVER
IN·SERVICE
REG.
PRIOR. LEII.
MASK REG.
INTERRUPT
STATUS REG.
EXT. INPUT 2
CONTROL REG.
Figure 21. Interrupt Controller Block Diagram
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IAPX 186
Special Fully Nested Mode
This mQde is entered by setting the SFNM bit in INTO
or INT1 control register. It enables complete nestability with external 8259A masters. Normally, an interrupt request from an interrupt source will not be
recognized unless the in-service bit for that source is
reset. If mote than one interrupt source is connected
to an external interrupt con,roller, all of the interrupts
will be funneled through the same 80186 interrupt
request pin. As a result, if the external interrupt controller receives a higher-priority interrupt, its interrupt will not be recognized by the 80186 controller
until the 80186 in-service bit is reset. In special fully
nested mode, the 80186, interrupt controller will allow
interrupts from an external pin regardless of the·
state of the in-service bit for an interrupt source in
order to allow multiple interrupts from a single pin.
An in-service bit will continue to be set, however, to
inhibit interrupts from other lower-priority 80186 interrupt sources.
Special procedures should be followed when resetting IS bits at the end of interrupt service routines.
Software polling of the external master's IS register
is required to determine if there is more than one bit
set. If so, the IS bit in the 80186 remains active and
the ,next interrupt service routine is entered.
Operation in a Polled Environment
The controller may be used in a polled mode if interrupts are undesirable. When polling, the processor
disables interrupts and then polls the interrupt controller whenever it is convenient. Polling the interrupt controller is accomplished by reading the Poll
Word (Figure 31). Bit 15 in the poll word indicates
to the processor that an interrupt of high enough
priority is requesting service. Bits 0-4 indicate to
the processor the type vector of the highestpriority source requesting service. Reading the
Poll Word causes the In-Service bit of the highestpriority source to be set.
It is desirable to be able to read the Poll Word ihformation without guaranteeing service of any pending
interrupt, i.e., not set the indicated in-service bit. The
80186 provides a Poll Status Word in addition to the
conventional Poll Word to allow this to be done. Poll
Word information is duplicated in the Poll Status
\(\lord, but reading the Poll Status Word does not set
the associated in-service bit. These words are located in two adjacent memory locations in the register file.
Master Mode Features
Programmable Priority
The user can program the interrupt sources into any
of eight different priority levels. The programming is
done by placing a 3-bit priority level (0-7)< in the
control register of each interrupt source. (A source
with a priority level of 4 has higher priority over all
priority levels from 5 to 7. Priority registers containing values lower than 4 have greater priority.) All
interrupt sources have preprogrammed default
priority levels (see lable 4).
If two requests with the same programmed priority
level are pending at once, the priority ordering
scheme shown in Table 4 is used. If the serviced
interrupt routine reenables interrupts, it allows other
requests to be serviced.
End-of-Interrupt Command'
The end-of-interrupt (EOI) command is used by the
programmer to reset the In-Service (IS) bit when an
interrupt service routine is completed. The EOI command is issued by writing the proper pattern to the
EOI register. There are two types of EOI commands,
specific and nonspecific. The nonspecific command
does not specify which IS bit is reset. When issued,
the interrupt controller automatically resets the IS bit
of the highest priority source with an active service
.routine. A specific EOI command requires that the
programmer send the interrupt vector type to the
interrupt controller indicating which source's IS bit is
to be reset. This command is used when the fully
nested structure has been disturbed or the highest
priority IS bit that was set does not belong to the
service routine in progress.
Trigger Mode
The four external interrupt pins can be programmed
in either edge- or level-trigger mode. The control
register for each external source has a level-trigger
mode (LTM) bit. All interrupt inputs are active HIGH.
m the edge sense mode or the level-trigger mode, the
. interrupt request must remain active (HIGH) until the
interrupt request is acknowledged by the 80186 CPU.
In the edge-sense mode, if the level remains high
after the interrupt is acknowledged, the input is disabled and no further requests will be generated. The
input level must go LOW for at least one clock cycle to
reenable the input. In the level-trigger mode, no such
provision is made: holding the interrupt input HIGH
will cause continuous interrupt requests.
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"
iAPX186,
Interrupt Vectoring
"
The 80186 Interrupt Controller will generate interrupt vectors for the integrated OMA channels and
the integrated Timers. In addition, the Interrupt Controller will generate interrupt vectors for the external
interrupt lines if they are not configured in Cascade
or Special Fully Nested Mode. The interrupt vectors
generated are fixed and cannot be changed (see
'Table 4).
Interrupt Controller Registers
The Interrupt Controller register model is shown in
Figure 23. It contains 15 registers. All registers can
both be read or written unless specified otherwise.
In-Service Register
This register can be read from or written into. The
format is shown in Figure 24. It contains the InService bit for each of the interrupt sources. The
In-Service bit is set to indicate that a source's service
routine is in progress. When an In-Service bit is set,
the interrupt controller will not generate interrupts to
the CPU when it receives interrupt requests from
devices with a lower programmed priority level. The
TMR bit is the In-Service bit for all three timers; the
DO and 01 bits are the In-Service bits for the two OMA
channels; the 10-13 are the In-Service bits for the
external interrupt pins. The IS bit is set when the
processor acknowledges an interrupt request either
by ar interrupt acknowledge or by reading the poll
register. The IS bit is reset at the end of the interrupt
service routine by an end-of-interrupt command issued by the CPU.
Interrupt Request Register
The internal interrupt sources have interrupt request
bits insi,de the interrupt controller. The format of this
register is shown in Figure 24. A read from this register yields the status of these bits. The TMR bit is the
logical OR of a/l timer interrupt requests. DO and 01
are the interrupt request bits for the OMA channels.
the state of the external interrupt input pins is also
indicated. The state of the external interrupt pins is
not a stored condition inside the interrupt controller,
therefore the external interrupt bits cannot be written. The external interrupt request bits show exactly
when an interrupt request is given to the interrupt
controller, so if edge-triggered mode is selected, the
bit in the register will be HIGH only after an inactiveto-active transition. For internal interrupt sources,
the register bits are set when a request arrives and
are reset when, the processor acknowledges the
requests.
Mask Register
This is a 16-bit register that contains a mask bit for
each interrupt source. The format for this register is
shown in Figure 24. A one in a bit position corresponding to a particular source serves to mask the
source from generating interrupts. These mask bits
are the exact same bits which are used in the individual control registers; programming a mask bit using
the mask register will also change this bit in the
individual control registers, and vice versa.
80186
IfiITO
INT
8259A
PIC
iNTA
INTAO
Figure 22. Cascade Mode Interrupt Connection
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IAPX186
Priority Mask Register
This register is used to mask all interrupts below
particular interrupt priority levels_ The format of this
register is shown in Figure 25. The code in the lower
three bits of this register inhibits interrupts of
priority lower (a higher priority number) than the
code specified. For example, 100 written into this
register masks interrupts of level five (101), s'ix (110),
and seven (111). The register is reset to seven (111)
upon RESET so all interrupts are unmasked.
OFFSET
INT3 CONTROL REGISTER
3EH
INT2 CONTROL REGISTER
3CH
INT1 CONTROL REGISTER
3AH
INTO CONTROL REGISTER
38M
OMA 1 CONTROL REGISTER
36H
DMA 0 CONTROL REGISTER
34H
TIMER CONTROL REGISTER
32H
INTERRUPT STATUS REGISTER
30H
Interrupt Status Register
This register contains general interrupt controller
status information. The format of this register is
shown in Figure 26. The bits in the status register
have the following functions:
INTERRUPT REOUEST REGISTER
2EH
DHLT:
IN-SERVICE REGISTER
2CH
PRIORITY MASK REGISTER
2AH
MASK REGISTER
28H
DMA Halt Transfer; setting this bit halts all
DMA transfers. It is automatically set
whenever a non-maskable interrupt occurs,
and it is reset when an IRET instruction is·
executed. The purpose of this bit is to allow
prompt service of all rion-maskable interrupts. This bit may also be set by the CPU.
POLL STATUS REGISTER
26H
IRTx:
POLL REGISTER
24H
EOI REGISTER
22H
These three bits represent the individual
timer interrupt request bits. These bits are
used to differentiate the timer interrupts,
since the timer IR bit in the interrupt request register is the "OR" function of all
timer interrupt requests, Note that setting
anyone of these three bits initiates an interrupt request to the interrupt controller.
Figure 23. Interrupt Controller Registers
(Non-IRMX 86 Mode)
15
o
I
14
10
8
7
0
Figure 24. In-Service, Interrupt Request, and Mask Register Formats
15
o
I
14
0
]
I
Figure 25. Priority Mask Register Format
15
I DHLT 1
14
0 1
7
0,,1 0 1 0
4
o
3
1 0
2
1
0
IIRT211RT111RTO
I
Figure 26. Interrupt Status Register Format
AFN'()2217C
IAPX 186
Timer, DMA 0, 1; Control Reglaters
These registers are the control words for all the internal. interrupt .sources. The format for these registers
is shown in Figure 27. The three bit positions PRO,
PR1, and PR2 represent the programmable priority
level of the interrupt source. 'The MSK bit inhibits
interrupt requests from ·the interrupt source. The
MSK bits. in. the· individual control registers are the
exact same bits as are in the Mask Register; modifying them in the individual control registers will also
modify them in the Mask Register, and vice versa.
INTO-oINT3 Control Registers
These registers are the control words for the four
externalJnput pins. Figure 28 shows the format of the
INTO and INTl Control registers; Figure 29 shows the
format of the INT2 and INT3 ContrQI registers. In
cascade mode or special fully nested mode, the control words for INT2 and INT3 are not used.
The bits in the various control registers are encoded
as follows:
PRO-2: Priority programming information. Highest
Priority = 000, Lowest Priority = 111
LTM:
level is preceded by an inactive-to-active
transition on the line. In both cases, the
level must remain active until the interrupt
is acknowledged.
MSK:
Mask bit, 1 = mask; 0 = non mask.
C:
Cascade mode bit, 1
SFNM:
Special fully nested mode bit, 1 = SFNM
EOI Register
The end of the interrupt register isa command register which can only be written into. The format of this
register is shown in Figure 30. It initiates an EOI
command when written to by the 80186 CPU.
The bits in the EOI register are encoded as follows:
Sx:
Encoded information that specifies an interrupt source vector type as shown in
Table 4. For example, to reset the In-Service
bit for DMA channel 0, these bits should be
set to 01010, since the vector type for DMA
channel 0 is 10. Note that to reset the single
In-Service bit for any of the three timers, the
vector type for timer 0 (8) should be written
in this register.
Level-trigger mode bit. 1 = level-triggered;
Interrupt Input levels
are active high. In level-triggered mode, an
interrupt is generated whenever the external line is high. In edge-triggered mode, an
. interrupt will be generated only when this
o = edge-triggered.
15
o
I
14
0
= cascade; 0 = direct
4
I
3
2
1
0
1
0
Figure 27. Tlmer/DMA Control Register Formats
15
o
I
14
0
7.
I
6
5
4
3
2
o ISFNMI c I LTM I MSK I PR2\
PR1 \ PRO
I
Figure 28. INTO/INT1 Control Register Formats
15
o
I
14
0
I
..
4
\0
\
3
LTM IMsKI
2
~R2\
1
0
PR1\ PRO
I
FigUre 29. INT2/INT3 Control Register Formats
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IAPX 186
NSPEC/: A bit that determines the type of EOI comSPEC
mand. Nonspecific = 1, Specific = O.
Poll and Poll Status Registers
These registers contain polling information. The format of these registers is shown in Figure 31. They can
only be read. Reading the Poll register constitutes a
software poll. This will set the IS bit of the highest
priority pending interrupt. Reading the poll status
register will not set the IS bit of the highest priority
pending interrupt; only the status of pending interrupts will be provided.
Encoding of the Poll and Poll Status register bits are
as follows:
Sx:
Encoded information that indicates the
vector type of the highest priority interrupting source. Valid only wt'len INTREQ = 1.
Because of pin limitations caused by the need to
interface to an external 8259A master, the internal
interrupt controller will no longer accept external
inputs. There are however, enough 80186 interrupt
controller inputs (internally) to dedicate one to each
timer. In this mode, each timer interrupt source has
its own mask bit, IS bit, and control word.
The iRMX 86 operating system requires peripherals
to be assigned fixed priority levels. This is incompatible with the normal operation of the 80186 interrupt controlier. Therefore, the initialization software
must program the proper priority levels for each
source. The required priority levels for the internal
interrupt sources in iRMX mode are shown in Table
16.
Table 16. Internal Source Priority Level
INTREQ: This bit· determines if an interrupt request is
present. Interrupt Request = 1; no Interrupt
Request = O.
Priority Level
0
1
2
3
4
5
iRMX 86 COMPATIBILITY MODE
'This mode allows iRMX 86-80186 compatibility. The
interrupt model of iRMX 86 requires one master and
multiple slave 8259As in cascaded fashion. When
iRMX mode is used, the internal 80186 interrupt controller will be used as a slave controiler to an external
master interrupt controller. The internal 80186 resources will be monitored through the internal interrupt controller, while the external controller
functions as the sy.stem master interrupt controller.
Up,on reset, the 80186 interrupt controller will be in
the non-iRMX 86 mode of operation. To set the controller in the iRMX 86 mode, bit 14 of the Relocation
Register should be set.
Interrupt Source
Timer 0
(reserved)
DMAO
DMA1
Timer 1
Timer 2
These level assignments must remai!,) fixed in the
iRMX 86 mode of operation.
iRMX 86 Mode External Interface
The configuration of the 80186 with respect to an
external 8259A master is shown in Figure 32. The
INTO input is used as the 80186 CPU interrupt input.
INT3 functions as an output to send the 80186 slaveinterrupt-request to one of the 8 master-PIC-inputs.
Figure 30. EOI Register Format
15
14
13,
Figure 31. Poll Register Format
3-389
AFN-02217C
IAPX 186
8259A
MASTER
INTA
80186 INT. IN
<==
11'10
INT
1
-
IR7
CASO-2
80186
t.
INTO
INT3
I
'SLAVE SELECT
JNT1
INT2
I
f--
REQUESTSFROM
OTHER SLAVES
:>
CASCADE
ADDRESS DECODER
80186 SLAVE INTERRUPT OUTPUT
Figure 32. iRMX 86 Interrupt Controller Interconnection
'Correct master-slave interface requires decoding of
the slave addresses (CASO-2). Slave 8259As do this
internally. Because of pin limitations, the 80186 slave
address will have to be decoded externally. INT1 is
used as a slave-select input. Note that the slavevector address is transferred internally, but the READY
input must be supplied externally.
INT2 is used as an acknowledge output, suitable to
drive the INTA input of an 8259A.
Specific End-of-Interrupt
In iRMX mode the specific EOI command operates to
reset an in-service bit of a specific priority. The user
supplies a 3-bit priority-level value that points to an
in-service bit to be reset. The command is executed
by writing the correct value in the Specific EOI 'register at offset 22H.
Interrupt Controller Registers
in the iRMX 86 Mode
Interrupt Nesting
iRMX 86 mode operation allows nesting of interrupt
requests. When an interrupt is acknowledged, the
priority logic masks off all priority levels except
those with equal or higher priority.
.
All control and command registers are located inside
the internal peripheral control block. Figure 33
shows the offsets of these registers.
Vector Generation in the iRMX 86 Mode
Vector generation in iRMX mode is exactly like that of
an 8259A slave. The interrupt controller generates an
8-bit vector which the CPU multiplies by four and
uses as an address into a vector table. The significant
five bits of the vector are user-programmable while
the lower three bits are generated by the priority
logic. These bits represent the encoding of the
priority level requesting service. The significant five
bits of the vector are programmed by writing to the
Interrupt Vector register at offset 20H. '
3-390
End-of-Interrupt Register
The end-of-interrupt register is a command register
which can only be written. The format of this register
is shown in Figure 34. It initiates an EOI command
when written by the 80186 CPU.
The bits in the EOI register are encoded as follows:
Lx:
Encoded value indicating the priority of the
IS bit to be reset.
In-Service Register
This register can be read from or written into. It
contains the in-service bit for each of the internal
AFN.()2217C
IAPX 186
interrupt sources. The format for this register is
shown in Figure 35. Bit positions 2 and 3 correspond
to the DMA channels; positions 0, 4, and 5 correspond to the integral timers. The source's IS bit is set
when the processor acknowledges its interrupt request.
'nterrLlpt Request Reg'''er
This register indicates. which internal peripherals
have interrupt requests pending. The formaf of this
register is shown in Figure 35. The interrupt request
bits are set when a request arrives from an internal
source, and are reset when the processor acknowledges the request.
Mask Reglst.r
This register contains a mask bit for each interrupt
source. The format for this register is shown in Figure 35. If the bit in this register corresponding to a
particular interrupt source is set, any interrupts from
that source will be masked. These mask bits are
exactly the same bits which are used in the individual
control registers, i.e., changing tFie state of a mask
bit in this register will also change the state of the
mask bit in the individual Interrupt control register
corresponding .to the bit.
Control Registers
These registers are the control words for all the internal interrupt sources. The format of these registers is
shown in Figure 36. Each of the timers and both of
the DMA channels have their own Control Register.
The bits of the Control Registers are encoded as
follows:
I:
prx:
3-bit encoded field indicating a priority level
for the source; note that 'each source must
be programmed at specified levels.
msk:
mask bit for the priority level indicated by prx
bits.
LEVEL I CONTIKII. flEQllTER
(TIMER 2)'
\.EVEL 4 CONTROL REGISTER
(TIMER')
OFFSET
3AH
38H
LEVEL 3 CONTROL REGlrrER
(aMA')
•
LEVEL 2 CONTROL REGISTER
(DMAO)
34H
LEVEL 0 CONTROL REGISTER
(TIMER 0)
32M
INTERRUPT STATUS RIiGISTER
SOH
REGISTER
2EH
INTERRUPT~EQUEST
I_RVlCE REGISTER
2CH
PRIORITY-I.EVEL MASK REGISTER
ZAH
MASK REGISTER
28H
SPECIFIC EOI REGISTER
22H
INTERRUPT VECTOR REGISTER
20H
Figure 33. Interrupt Controller Registers
(IRMX 86 Mode)
1 : 1 :1 :
I:
1: 1
~ 1 ,: I: 1
Figure 34. Specific EO' Register Format
Figure 35. In-Serv1c~ Interrupt Reque.t, and Mok Register Format
3-391
AFN.()2217C
IAPX 186"
Interrupt Vector Register
,'
This' reg!$~r provl.c;I~ t~e. upper fi~e ,bits of the interrupt vector address. The format of this register is ,
shown in Figure 37. The interrupt controller Itself,
provides ttie lower three bits of the interrupt vector
as determined by the priority level of the interrupt
request.
The fqrmat of the bits In this r8Qister is:,
,
tx:
5-blt field indicating the upper five bits 'of the
vector address.
Interrupt Controller and Reset
Upon RESET, the Interrupt controller will perform the
'
foHowlng actions: ' '
• All SFNM bits reset to 0, implying Fully Nested
Mode.
• All PR bits in the various control registers set to 1.
This places 'all sources at 'lowest priority (level
111).
Priority-Level Mask Register
,
This register indicates the lowest priority-level interrupt which will be serviced.
"
The encoding of the bits in this register is:
1'T1x:
3-bit encoded field indication priority-level
value. All levels of lower priority will be
masked.
• All LTM bits reset to 0, resulting In edge-sense
mode.
• All Interrupt Service bits reset to O.
• All Interrupt Request bits reset to O.
• All MSK (Interrupt Mask) bits Sl3t to 1 (mesk).
• All C (Cascade) bits reset to 0 (non-casc~de).
Interrupt Status Register
This register is defined exactly as in Non-IRMX
Mode. (See Fig. 26.)
• All PRM (Priority Mask) bits set to ,1, I,mplying no
levels m~ked.
• Initialized to non-IRMX 86 mode.
.,
I : I : I: 1: 1: I':'H~
H
Figure 36. Control Word r=orn:'at,
1 : 1 : 1 : 1 : 1 : I: 1 : 1 ' 1 : 1
Figure '37. Interrupt Vector Register Format
15
14
13
·1 : 1 : 1 : 1 :
I:I:I~ I:I:
1
, Figure 38., Priority Leve' Mask Reglste~
3-392
AFN-02217C ,
IAPX 186
18 MHz
r1
0
Vee
~
X1
X2
UCS
~
8282 OR
RES
ADOAD15
. ALE
"::.-
~F ~or· =::
~
I--
RESET
ROM
ADDRESS
r
STB
80188
{
t
1m
\Wi
r
~3
....
c---
BHE
SRDY
CT+
5V
ARDY
NMI
..
HOLD
PROGRAM
RAM
-
~
~
~
LOW RAM
I
~
£
TMRINO '----+5V
,
TMROUTO
8288 OR
DEN
DTlii
JiC§ij
A1
A2
....
~
8287
;:> TRANSCEIVER
CLOCK
~
."
<=>f;)1
DO-D7
SERIAL
~t
T ERMINAL
·1/0
I
INTO
DISK
INTERFACE
HARDWARE
INn
PCS4
k:=>8
DI SK
DRQO
Flgure·39. TyplcallAPX 186 Computer
3..393
AFN.Q2217C
iAPX 186
16 MHz
rD~
Vee
r1
Xl
X2
UCS
CS
AD
m
~
.~
8282 OR
8283
LATCH
STB
~
OE
liE
STB
+
ALE
LCS
Uf
G
-=
RESET
ROM
LOW
RAM
CS
BHE
Wi!
1\
l:,
ADO-AD19
-"> ADDRESS
JlUS
8282 OR
8283
LATCH
STB
OE
~~STB
lIE
+ +
80188
NMI
HOLD
~
----",
8288 OR
8287
TRANSCEIVER
~
DATA BUS
TOE·
--r+-bil-
t,
DT/R
CLK
" - - - ALE
CLKOUT
SO--S2
--
---v'
r--
:t:J
8288
S0-52 BUS
CONTROLLER
CEN
lOB
-:;-
MULTI
MAST ER
SYSTEM
BUS
BUS CONTROL
COMMANDS
AEN
1
r
~ SO-S2 8289AEN
CLKAR~ER
PCSQ
I'CS1
LOCK
SRDY
ARDY
SYSB/RESe
../
\
'> :~~I+~~~ION
lOB
,
r
~
LOCK
RESB n.+SV
'-..f
XACK
.
Figure 40. Typical iAPX 188 Multi-Master Bus Interface
3-394
AFN-02217C
inter
IAPX,186
PACKAGE
NOTE: The lOT 3M Textool 68-pin JEOEC Socket
The 80186 is housed in a 68-pin, leadless JEOEC type
A hermetic chip carrier. Figure 41 illustrates the
package dimensions.
is required for 12 ICETM_186 operation See Figure
42:for details.
I
1
,050BSC
[
TYP
tW
,039 TYP (99)
[m
PI.CS
t
I ~ Ic.OO6
Figure 41. 80186 JEDEC Type A Package
\
3-395
AFN'()2217C
I"n+,:-.f
••.;e. .
INPX 186
,1
268-5400-00
,
~-----------~:'~)SQ----------~.~II
~
GUIDE 80SS
I
3 Ples
INDEX
J
+j}
-'1.--1=.... ,1------;-\, + - - - -
PC BOARD PATTERN
~
-tSOCKET ORIENTATION PIN
I
~PINNOl
~~l:~~~~1!~ +"
iT':
:cJ
.
PIN CLR HOLE'"
FOR I .029 DIA ~
DEVICE PADS
SHOWN FOR -~7+1 (0.74)CONTACT
!+)"
-!' ~.
LOCATION ~ I
.,r;I
I
1">- -
~
~I
~fE~\TATION a. FRONT
lJ
'i-~FAONT
•
ALUMINUM LID
(HEATSINK PROVISIONS OPTIONAL)
1 DO
,..:::-'i.100('5.4)
I
(2 54) TVP
~~;~-:'~T ~~>-~~~~~~?I-+ ~
..:2.!!
illl.~'ri.~.1.."~"...
(O.38)-:J:i
l- .! 2'....)
\
1.00
TVP
OPEN
.020:=r
(20.32)
(0.51)
8 SPCSO.100TOL NON ACCUM TYP 4 PLes
CONTACT TAil
(2.")
NOTE: Physical dimensions shown are for reference only. Plea.e consult 3M 1extool for comptete mformation on the socket.
Figure 42. Textool 68 Lead Chip Carrier Socket
3-396
AFN'()2217C
IAPX 186
"NOTICE: Stresses above those listed under
"Absolute Maximum Ratings" may qause permanent
damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operationa/ sections of this speCification is not impHed.
Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature under Bias ..... O°C to 70°C
Storage Temperature ............ -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .............. -1.0V to +7V
Power Dissipation •....................... 3 Watt
=
=
D.C. CHARACTERISTICS (TA
0°-70°C, Vee
5V ±10%)
Applicable to 80186 (8 MHz) and 80186-6 (6 MHz)
Test Conditions
Min.
Max.
Units
- 0.5
+0.8
Volts
Vcc + 0.5
Volts
Vee + 0.5
Volts
0.45
Volts
Output High Voltage
2.4
Volts
Power Supply Current
550
450
rnA
Max measured at TA ~ O°C
lu
Input Leakage Current
±10
!iA
OV
ILO
Output Leakage Current
±10
~A
0.45V
VCLO
Clock Output Low
0.6
Volts
la
VCHO
Clock Output High
Volts
loa ~ -200 ~A
Veu
Clock Input Low Voltage
-0.5
0.6
Volts
3.9
Symbol
Parameter
VIL
Input Low Voltage
VIH
Input High Voltage
(All except X1 and (fiES)
VIH1
Input High Voltage (RES)
VOL
Output Low Voltage
VOH
Icc
2.0
3.0
4.0
I. ~ 2.5 rnA for SO-52
la ~ 2.0 rnA for all other outputs
loa ~ -400 ~
~
VCHI
Clock Input High Voltage
Vcc +,1.0
Volts
CIN
Input Capacitance
10
pF
CIO
110 Capacitance
20
pF
~
VIN
<
<
<
Vee
VOUT < Vee
4.0 rnA
PIN TIMINGS
A.C. CHARACTERISTICS (TA = 0°-70°C, Vee = 5V ± 10%)
80186 Timing Requirements, All Timings Measured At 1.5 Volts Unless Otherwise Noted.
Applicable to 80186 (8 MHz) and 80186-6 (6. MHz)
Symbol
Parameter
Min.
Max.
Units
TDVCL
Data in Setup (A/D)
20
ns
TCLDX
Data in Hold (A/D)
10
ns
TARYHCH Asynchronous Ready
(A READY) active setup
time'
20
ns
TARYLCL AREADY inactive setup
time
35
ns
TCHARYX AREADY hold time
15
ns
35
ns
TSRYCL
Synchronous Ready
(SREADY) transition setup
time
TCLSRY
SREADY transition hold
time
15
ns
THVCL
HOLD Setup"
25
n5
TINVCH
INTR, NMI, TEST, TIMERIN,
Setup"
25
ns
DRQO, DRQ1, Setup"
25
ns
TINVCL'
Test Conditions
I
"To guarantee recognition at next clock.
3-397
AFN·02217e
"m
...f'.
III"E!-
IAPX186
A.C. CHARACTE.RISTICS (Continued) ...
80186·Master Interface Timing Responses
. 80188 (8 MHz)
Symbol
Parameters
Min.
80188-6 (6 MHz)
Max.
Min.
Max.
44
5
63
35
TCLAX
Address Valid Delay
TCLAX
Address Hold
TCLAZ
Address Float Delay
TCHCZ
Command Lines Float Delay
TCHCV
Command Lines Valid Delay
(after float)
TLHLL
ALE Width
TCHLH
ALE Active Delay
35
44
ns
TCHLL
ALE Inactive Delay
35
44
ns
TLLAX
Address Hold to ALE Inactive
TClOV
Data Valid Delay
10
TClOOX
Data Hold Time
10
10
TWHDX
Data Hold after WR
TCLCL-40
TCLCL-50
TCVCTV
Control Active Delay j
5
70
5
87
ns
TCHCTV
Control Active Delay 2
10
55
10
76
ns
TCVCTX
Control Inactive Delay
5
55
5
76
ns
TcvDEx
DEN Inactive Delay
(Non-Write Cycle)
87
ns
TAZRL
Address Float to RD Active
0
TCLRL
RD Active Delay
10
70
10
87
ns
TCLRH
RD Inactive Delay
10
55
10
76
ns
TRHAV
RD Inactive to Address Active
TCLHAV
HLDA Valid Delay
TRLRH
RDWidth
2TcLCL·50
2TcLCL·50
ns
TWLWH
WRWidth
2TcLCL.40
2TcLCL.40
ns
TAVAL
Address Valid to ALE Low
TCLCH·25
TCLCH-45
TCHSV
Status Active Delay
10
55
10
76
ns
TCLSH
Status Inactive Delay
10
55
10
76
ns
TCLTMV
Timer Output Delay
60
75
ns
TCLRO
Reset Delay
60
75
ns
TCHQSV
Queue Status Delay
35
44
ns
Max.
Units
80
ns
5
10
TCLAX
10
45
55
TCLCL-35
10
70
10
ns
56
ns
76
ns
ns
ns
55
ns
ns
TCLCL.~O
50
10
ns
ns
0
TCLCL·40
CL = 20-200 pF all outputs
ns
TCHCL.30
44
ns
44
TCLCL·35
TCHCL·25
Test Conditions
Units
TCLAV
ns
67
ns
ns
100 pF max
r
80186 Chip·Select Timing Responses
Symbol
Parameter
Min.
Max.
Min.
66
TCLCSV
Chip-Select Active Delay
Tcxcsx
Chip-Selct Hold from
Command Inactive
35
TCHCSX
Chip-Select Inactive Delay
5
ns
35
35
5
3"398
Test Conditions
47
ns
AFN.(I2217C
IAPX 186
A.C. CHARACTERISTICS (Continued)
80186 CLKIN Requirements
80186 (8 MHz)
Symbol
Parameter
80186·6 (6 MHz)
Min.
Max.
Min.
Max.
Units
62.5
250
83
250
ns
Test Conditions
TCKIN
CLKIN Period
TCKHL
CLKIN Fall Time
10
10
ns
TCKLH
CLKIN Rise Time
10
10
ns
1.0 to 3.5 volts
TCLCK
CLKIN Low Time
25
3;3
ns
1.5 volts
TCHCK
CLKIN High Time
25
33
ns
1.5 volts
3.5 to 1.0 volts
80186 CLKOUT Timing (200 pF load)
Symbol
Parameter
Min.
.
Max.
Min.
Max.
Units
62.5
ns
500
ns
Test Conditions
TCICO
CLKIN to CLKOUT Skew
TCLCL
CLKOUT Period
TCLCH
CLKOUT Low Time
1/2 TCLCL-7.5
112 TCLCL-7.5
ns
1.5 volts
TCHCL
CLKOUT High Time
112 TCLCL-i.5
112 TCLCl-7.5
ns
1.5 volts
125
50
500
167
TCH1CH2 CLKOUT Rise Time
15
15
ns
1.0 to 3.5 volts
TCL2CL1
15
15
ns
3.5 to t. volts
CLKOUT Fall Time
3-399
AFN.Q2217C
IAPX186
WAVEFORMS
MAJOR CYCLE TIMING
VCH
T3
.
CLKOUT
v:--' ~
_TCH~
~ --,~
"U
CL
Tel
.IN_
,
.,
TCH~ :Lj~
AD,5-ADo
=
N
,~y~,y
VOH
AD,5-ADo
INTACYCLE
-
-~-{
DTIR
TA
-
iii,~=VOH
IS"I:
-1
t
1\
I'~
-
,
FLOAT
TeHCTV
1/
AI
POINTEI
~
LCS1
MCS
-
,~
\
"\
~ I
[1
t
TCVCTX-
-j
(j
I ADDRESS
3-400
j..-TCHCTV
jl.
~
'I~
._'TCLCBV
FLOAT
VI
NDTE2
I
TCLAV_
~
~1 CLDX
~;nv;.;i_
.v.v,
= YoOH
/r--
.- 1
~
N
RD, WR, INTA, DT/R
.11
I
= VOL
SOF!]!!ARE HAIl"-DE!!. =Voto
""Wt!7
-NDTE1
TCI~ I - -
DATAOU1
i+-TCLAZ
'I
'J
~
.._.
~
-
.
,
~~
1A,5~Ao
,y~,
RQ,iNTA,
DT/R
B,-So
~~
r--\
-
:=
",\,0.
I+I
WRITE CYCLE
rcLD1
f+T~ ~L";: I~
.J
=
1 - ,..v"'3)I':i'Ci:Cii:'
...~.
,........
I-rc ~LAX:::::
'II
So
ALE
•
11-
Tw
~H1~ArTCUCL6
TCXCSX-
--
AFN-02217C
IAPX 186
WAVEFORMS (Continued)
MAJOR CYCLE TIMING (Continued)
BHE/S7,A19/S8-Al81S3
r-I
ADj.-ADo
READ CYCLE
TCLRL~---'~---4---
DEN
PCS,
MC!I
~-----11-~ I
[CS,
MCS
NOTES.
1. Following a Wrile cycle, Ihe Local Bus IS floaled by Ihe 80186 only when Ihe
80186 enlers a "Hold Acknowledge" stale.
2 INTA occurs one clock later in RMX-mode.
3 Status inactive just pnor to T4
3-401
AFN·02217C
iAPX 186
WAVEFORMS (Continued)
ClKOUT
--
TClAV
_
ClKOUT
~
INTO·3
TIMERIN
3-402
AFN.()2217C
inter
IAPX 188
WAVEFORMS (Continued)
HOLD-HLDA TIMING
cutOUT
T,
CLKOUT~.
THVCL
.. -+--1--
HOLD
HlOA
iTCLAV
AD15-AIIO - - - -
)---
80188
Imil----
-- .....
__ ..J
TCHCV
A19/S6-A1&1S3, - - - -
Ii1'l, WI\,
80188
H,---:--
)---
-- .....
__ ..J
r
80188
80188
DT/A,
52-SO
3-403
AFN-02217C'
'-
~n+..;...J•.
I•• w.e-
IAPX 186
WAVEFORMS (Continued)
TIMER ON 80186
i---TCKIN---t--
ClKIN
TCKLH
TCHICH2
---+o'>l<.o---TCHCl--_....
ClKOUT
i-------TClCl - - - - - - - 1
I .
---J
TINVCH
TIMERIN
~~
. TIMEROUT _ _
~:~~~~~~~~~~~~~~~~~~~~~~~_2___6_CLO_C_KS_ _ _ _ _ _ _ _ _ _ _-I_ _~
80186 INSTRUCTION TIMINGS
• All word-data is located on even-address
boundaries.
The following instruction timings represent the minimum execution time in clock cycles for each instruction. The timings given are based on the following
assumptions:
All jumps and calls include the time required to fetch
the opcode of the next instruction at the destination
address.
• The opcode, along with any data or displacement
required for execution of a particular instruction,
has been prefetched and resides in the queue at
the time it is needed.
• No wait states or bus HOLDS occur.
All instructions which involve memory reference can
require one (and in some cases, two) additional
clocks above the minimum timings shown. This is
due to the asynchronous nature of the handshake
between the BI.U and the Execution unit .
3-404
AFN-02217C
IAPX 186
INSTRUCTION SET SUMMARY
FUNCTION
Clock
Cycles
FORMAT
Comments
DA1II TRANSFER
MOV
=Move:
Register to ReglsteriMemory
11 000100w
mod reg
rim
Reglsterlmemory to register
11 000101w
mod reg
rim
Immediate to reglsterlmemory
11 10001 1 w
modOOO
rim
Immediate to register
11 01 1 w reg
Memory to accumulator
Accumulatorto memory
data
data
datalfw = 1
11 010000w
addr·low
addr·high
addr·low
Reglsterlmemory to segment register
11 010001w
11 00 0 1 1 1 0
modO reg
rim
Segment regISter to 'registerlmemory
11 0001100
mod 0 reg
rim
addr·high
PUSH = Push:
Memory
11 11111111 mod 11 0 rim
Register
10 1 0 1 0
Segment register
10 0 0 reg
POP
I
11 0I
datalfw=1
11 00 0 1 1 1 11
reg
modOOO rim
I
16
10
9
I
20
10
8
Register
10 101 1
Segment register
10
XCHG = Exchange:
Reglsterlmemory with register
11 0OOO11wl
Register with accumulator
11 00 1 0
IN =Inputfrem:
Fixed port
11 1 1 001 0 wi
vanable port
11 1101 lOW
OUT = Output to:
Fixed port
11 1 1 001 1 wi
variable port
11 1101 11 wi
XUT = Translate byte to AL
11 101011
LEA = Load EA to register
11 00 0 1 1 0 1
mod reg
rim
LOS = Load pOIOter to OS
11 1 0 0 0 1 0 1
mod reg
rim ·1
LES = Load painter to ES
11 1000100
mod reg
rim
UHF = Load AH with flags
11 00 1 1 1 1 1
SAHF = Store AH IOto flags
11 00 1 1 1 1 0
PUSHF = Push flags
11 00 1 1 1 0 0
POPF = Pop flags
11 00 1 1 1 0 1
°
0 reg 1 1 11
SEGMENT =Sagmant OVa,flda:
CS
10 0 1 0 1 1 1
ss
10 0 1 1
°
(reg*OI)
mod reg
rim
I
reg
I
10
8
port
I
9
7
11
6
18
18
2
3
9
8
1\
I
I
(mod * 11)
(mod * 11)
°I
os
ES
1001001101
8/16-bit
8/16-bit
. 4/173
I
port
I
I
10 0 1 1 1 1 1 0 I
I
I
reg
= Pop:
Memory
I
I
I
I
2112
219
12-13
3-4
9
8
219
2/11
2
2
2
2
110
Shaded areas indicate instructions not,available in iAPX 86,88 microsystems.
3-405
AFN.Q2217C
inter
j¥)OO~[bOIi\1JOOO~OOW
IAPX186
INSTRUCTION SET SUMMARY (Continued)
FUNCTION
FORMAT
ADD = Add:
Reglmemory with register to either
10 00 0 0 0 d w I
mod reg
Immediate to reglster/memory
It 00000 s wi
mod 000 rim
data
Immediate to accumulator
10 00 0 0 lOw I
data
datalfw=f
ADC = Add with carry:
Reglmemory with register to either
10 00 tOO d wi
mod reg
Immediate to reglsterlmemory
1100000swi
modOt 0 rim
data
Immediate to accumulator
10001010wl
data
datalfw=l
INC = Increment:
Reglsterlmemory
11 111111 wi
modOOO rim
Register
10 1 0 0 0
reg
rim
Comments
3/10
4/16
3/4
8/16-bit
3/10
rim
dataifsw=Ol
4/16
3/4
8/16-bit
3/15
I
3
SUB = Subtracl:
Reglmemory and register to erther
10 0 1 0 1 0 d wi
mod reg
rim
Immediate from register/memory
1100000swl
mod 1 01
rim I
Immediate from accumulator
10010110wl
data
I
SBB = Subtract with borrow:
Reg/memory and register to either
1000110d w i
mod reg
rim
Immediate from register/memory
11 00000 s wi
modOll
rim
Immediate from accumulator
10001110wl
data
DEC= Decremenl:
RegISter/memory
datalfsw=Ot
Clock
Cycles
I
data
datarfsw=OI
data Ilw= 1
data
datalfsw=OI
datallw=1
3/10
4/16
3/4
3/10
4/16
3/4
11 111111 wi
reg
modOOl
rim
RegISter
10 1 0 0 1
3/15
3
CMP= Compar.:
Register/memory with register
10 01 1 1 01 wi
mod reg
rim
Register with register/memory
10011100wl
mod reg
rim
3/10
3/10
Immediate with reglSterlmemory
I~ 0 0 0 0 0 s wi
mod 111
rim
Immediate with accumulator
10 0 1 1 1 lOw I
data
NEG = Change Sign
11 11 1 01 1 wi
mod 0 11
AAA = ASCII adlust for add
10 0 1 1 0 1 1 11
DAA = DeCimal adlust lor add
10 0 1 0 0 1 1 11
AAS "" ASCII adjust for subtract
10 0 1 1 1 11 11
DAS = Decimal adlust lor subtract
10 0 1 0 1 1 1 11
MUL = Multiply (unSigned)
RegISter-Byte
RegISter-Word
Memory-Byte
Memory-Word
11 11 1 01 1 wi
IMUL = Integer multiply (Signed)
RegISter-Byte
RegISter-Word
Memory-Byte
Memory-Word
11
OIV = D,v,de (unSigned)
ReglSte,Byte
RegISter-Word
Memory-Byte
11 1 1 1 0 1 1
I
data
data lIs w=O 1
' datallw=1
rim
8116-bit
3/10
3/4
3
8/16-bit
8/16-bit
8
4
7
4
modl00 rim
26-28
35-37
32-34
41-43
11 1 0 1 1 wi
mod 1 01
rim
25-28
34-37
31-34
40-43
mod 11 0 rim
29
38
35
Shaded areas indicate instructions not available In iAPX 86, 88 microsystems.
3-406
AFN'()2217C
.
IAPX 186
INSTRUCTION SET SUMMARY tr' .......+; ...
Clock
Cycles
FUNCTION
FORMAT
IDIV ~ Integer divide (signed)
Register-Byte
Register-Word
MemorY'Byte
Memory-Word
AAM ~ ASCII adlust for multiply
11 1 1 1 0 1 1 w
AAD ~ ASCII adlustfor divide
11 1 0 1 0 1 0 11000010101
CBW ~ Convert byte to word
CWD ~ Convert word to double word
11 00 1 1 0 0
11 00 1 1 0 0
LOGIC
ShiftlRotate Instructions:
ReglsterlMemory,by 1
11 1 0 1 0 0 0 w
ReglsterlMemory by Cl
11 1 0 1 0 0 1 w
I
mod 111
rim
44-52
53-61
50-58
59-67
19
15
11 10101001000010101
oI
2
4
tI
I
I
Comments
mod
m
2115
5+n117 +n
rim
mod TTl rim
TTT Instruction
o0
o0
Ral
RaR
0
1
o1 0
o1 1
loa
101
111
RCl
RCR
SHLISAl
SHR
SAR
AND~And:
3/10
Reg/memory and register to either
10 0 1 0 0 0 d wi
mod reg
Immediate to register/memory
11000000wl
mod 1 00 rim
rim
data
Immediate to accumulator
10010010wl
data
datalfw~1
TEST = And function to flags, no result:
Register/memory and register
11 000010wl
mod reg
Immediate data and register/memory
11 11 1 01 1 wi
mod 000 TIm
Immediate data and accumulator
11 010100wl
data
OR=Or:
Reg/memory and T,eglSter to either
1000010dwi
mod reg
rim
Immediate to register/memory
11000000wl
modOOl
rim
Immediate to accumulator
10000110wl
data
datalfw~
1
3/4
TIm
data
datalfw~
4/16
datalfw= 1
1
8/16-bit
3/10
4/10
314
8/16-bit
3110
data
datalfw~1
datalfw~1
XOR = Exclusive or:
Reg/memory and register to either
1001100 dw i
mod reg
Immediate to register/memory
11000000wl
mod 110 rim
data
Immediate to accumulator
10011010wl
data
datalfw ~~ 1
NOT ~ Invert reglsterlmemory
11 1 1 1 0 1 1 wi
mod 0 10 rim
STRING MANIPULATION:
MOVS ~ Move byte/word
11 010010wl
CMPS ~ Compare bytelword
11
4/16
314
8/16-bit
3/10
rim
datalf w ~ 1
4/16
3/4
3
8/16-bit
14
22
15
12
SCAS ~ Scan byte/word
LOOS ~ load bytelwd to ALiAX
Shaded areas indicate instructions not available in IAPX 86, 88 microsystems.
3-407
AFN.Q2217C
intJ
IAPX 186
INSTRUCTION SET SUMMARY IcnlntlnlJAtI
FUNCTION
Clock
Cycles
FORMAT
Comments
Repeated by count In CX
MOYS ~ Move string
111001
CMPS ~ Compare stnng
111001 z 11010011wl
8+8n
5+22n
5+15n
6+11n
11010010y;]
SCAS ~ Scan stnng
lOOS = Load stnng
CAll=CaU:
Direct within segment
11 1 1 0 1 00 0
Register/memory
11 111 111 1
mdlrect within segment
Drrect Ifltersegment
dlsp-Iow
I
11 00 1 1 0 1
dlsp-hlgh
14'
13/19
mod 0 10 rim
segment offset
23
segment selector
Indirect Intersegment
11 1111111
mod 0 11 rim
JMP = Unconditional jump:
Short/long
11 1 1 0 1 0 1
dlsp-Iow
Direct within segment
11 1 1 0 1 0 0
dlsp-Iow
RegIster/memory Indirect within segment[CfTT 1 1 1
Direct Intel segment
11 1 1 0 1 0 1
(mod, 11)
38
dlsp-hlgh
13
13
11/17
mod 1 00 rim
oI
I
Indirect mtersegment
11 111111 11
RET = Retu.n ITom CALL:
WIthin segment
11 1 0 0 0 0 1
Within seg adding Immed to SP
11 1 0 0 0,0 1 01
Intersegment
[}
Intersegmentaddmg Immediate to SP
11 1 0 0 1 0 1
I
segment offset '
mod 1 01 rm-]
(mod
±
11)
11
26
data-low
data-high
16
18
22
data-low
data-high
25
1 0 0 1 0 1 11
oI
13
segment selector
Shaded areas indicate instructions not available In iAPX
86, 88 microsystems.
3-408
AFN-02217C
inter
IAPX 186
INSTRUCTION SET SUMMARY (Continued)
FUNCTION
Clock
Cycles
FORMAT
JE/Jl = Jump on equ~lrero
10 1 1 1 0 1 0 0
dlsp
JLlJNGE ~ Jump on lesslnot grealer orequ~
10 1 1 1 1 1 0 0
dlsp
JLElJNG ~ Jump on less orequallnol greater
10 1 1 1 1 1 1 0
disp
JB/JNAE ~ Jump on belowlnolabove orequal
10 1 1 1 0 0 1 0
dlsp
JBE/JNA ~ Jump on below or equallnOI abo,e
10 1 1 1 0 1 1 0
dlsp
JP/JPE ~ Jump on p,"~lpan~ even
10 1 1 1 1 0 1 0
dlsp
JO ~ Jump on ove~ow
10 1 1 1 0 0 0 0
dlSp
JS ~ Jump on sign
10 1 1 1 1 00 0
dlsp
JNElJNl ~ jump on nol equallnol rero
10 1 1 1 0 1 0 1
dlsp
JNLlJGE ~ Jump on notleSSIgreater or equal
10 1 1 1 1 1 0 1
disp
JNLElJG ~ Jump on nol less or equallgrealer
10 1 1 1 1 1 1 1
dlsp
JNB/JAE ~ Jump on not belowlabove orequal
10 1 1 1 0 0 1 1
dlsp
JNBElJA ~ Jump on nol belo. or equallabove
10 1 1 1 0 1 1 11
dlsp
JNP/JPO ~ Jump on nol parlpar odd
10 1 1 1 1 0 1 1
dlsp
JNO ~ Jump onnot11'le~ow
10 1 1 1 0 0 0 1
dlsp
JNS~Jumponnolslgn
10 1 1 1 1 00 1
dlsp
JeXl ~ Jump on eXzero
11 1 1 0 0 0 1 1
dlsp
LOOP ~ loop ex limes
11 1 1 0 0 0 1 0
dlsp
LOOPZlLOOPE ~ loop while zerolequal
11 1 1 0 0 0 0 1
disp
LOOPNZlLOOPNE ~ loop while nol rerolequal
11 1100000
dlsp
INT ~ Inlerrupt:
Type specIfied
11 1 0 0 1 1 0 1
Type 3
11 1 0 0 1 1 0 0
INTO ~ Interrupt on overflow
11
IRET ~ Interrupt return
11 1 0 0 1 1 1
I
I
10 0 1 11 0I
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
5/15
6/16
6/16
6/16
1ype
47
45
48/4
tJ
Comments
JMP not
taken/JMP
taken
LOOP not
taken/LOOP
taken
if INT. taken/
if INT. not
taken
28
Shaded areas indicate instructions not available in iAPX 86, 88 microsystems.
"3-409
AFN.022)7C
inter
iAPX 186
INSTRUCTION SET SUMMARY (Continued)
FUNCTION
PROCESSOR CONTROL
CLC ~ Clear carry
CMC ~ Complement carry
I
I
I
11 11 10 0I
11 1 1 10 1I
111 10 1 0I
11 1 1 01 1I
I 1 1 0 10 0I
00 1 1 0 1 1 I
11 1 0 0 0 0I
STC ~ Set carry
CLO ~ Clear direction
11
STD ~ Set directIOn
11
CLI ~ Clear Interrupt
11
STI ~ Set interrupt
11
HLT~Halt
11
LOCK ~ Bus lock prefix
ESC ~ Processor ExtenSion Escape
11
.11
.
Comments
2
2
2
2
2
2
2
2
11 1 1 1 1 0 0 0
11 1 1 1 0 1 0 1
11 1 1 1 1 00 1
WAIT~Walt
Clock
Cycles
FORMAT
6
if test = 0
2
11 o011TTTI mod LLL rim I
(TTT LLL are opcode to processor extenSion)
6
Shaded areas indicate instructions not available in iAPX 86, 88 mlcrosystems.
3-410
AFN'()2217C
inter
IAPX 186
FOOTNOTES
The effective Address (EA) of the memory operand is
computed according to the mod and rim fields:
if mod
REG is assigned according to the following table:
16-Bit (w = 1)
000
001
010
011
100
101
110
111
= 11 then rim is treated as a REG field
if mod = 00 then OISP = 0', disp-Iow and disp-high
are absent
if mod = 01 then OISP = disp-Iow sign-extended to
16-bits, disp-high is absent
if mod = 10 then OISP = disp-high: disp-Iow
if rim
= 000 then EA = (BX) + (SI) + OISP
AX
CX
DX
BX
SP
BP
SI
01
S-Bit(w = 0)
000
001
010
011
100
101
110
111
AL
CL
OL
BL
AH
CH
OH
BH
if rim = 001 then EA = (BX) + (01) + OISP
if rim
if rim
if rim
if rim
= 010 then EA = (BP) + (SI) + OISP
= 011 then EA = (BP) + (01) + OISP
= 100thenEA = (SI) + OISP
= 101 then EA = (01) + OISP
if rim = 110 then EA = (BP) + OISP'
if rim = 111 then EA = (BX) + OISP
The physical addresses of all operands addressed by
the BP register are computed using the SS segment
register. The physical addresses of the destination op- .
erands of the string primitive operations (those addressed by the 01 register) are computed using the ES
segment, which may not be overridden.
OISP follows 2nd byte of instruction (before data if
required)
'except if mod
= 00 and rim = 110 then EA = disp·hlgh: disp·low
NOTE:
EA CALCULATION TIME IS 4 CLOCK CYCLES FOR ALL MODES, AND IS INCLUDED
IN THE EXECUTION TIMES GIVEN WHENEVER APPROPRIATE.
SEGMENT OVERRIDE PREFIX
10 0 1 reg 1 1 01
reg is assigned according to the following:
reg
Segment
Register
00
01
10
11
ES
CS
SS
OS
3-411
AFN·02217C
iAPX 88/10
8-BIT HMOS MICROPROCESSOR
8088/8088-2
• 8·Bit Data Bus Interface
• 8·Blt and 16-Blt Signed and Unsigned
Arithmetic In Binary or Decimal,
Including Multiply and Divide
• 16-Bit Internal Architecture
• Direct Addressing Capability to 1
Mbyte of Memory
• Compatible with 8155·2, 8755A·2 and
8185-2 Multiplexed Peripherals
• Direct Software Compatibility with
IAPX 86110 (8086 CPU)
• Two Clock Rates:
5 MHz for 8088
8 MHz for 8088·2
• 14·Word by 16·Bit Register Set with
Symmetrical Operations
• Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range
• 24 Operand Addressing Modes
• Byte, Word, and Block Operations
The Intel®,iAPX 88/10 is a new generation, high performance microprocessor implemented in N-channel, depletion load,
silicon gate technology (HMOS), and packaged in a 40-pin CerDIP package. The processor has attributes of both 8- and
16-bit microprocessors. It is directly compatible with iAPX 86/10 software and 8080/8085 hardware and peripherals.
MEMORY INTERFACE
C·BltS
MIN
MODE
INSTRUCTION
STREAM BYTE
QUEUE
GND
Vee
A14
A1S
A13
A16/S3
A12
A17IS4
All
Al8/SS
A1G
CS
BUS
INTERFACE
UNIT
A19/S6
(HIGH)
A9
SSG
SS
A8
MN/MX
OS
AD7
IP
AD6
HOLD
(Ra/G'I'O)
ADS
HlDA
(Ra/em)
AD4
iNA
(LOCK)
AD3
101M
(82)
AD2
DTili
(5')
ADl
DEN
(SO)
ADO
ALE
(QSO)
NMI
1NfA
(QS1)
INTR
TEST
A·BUS
EXECUTION
UNIT
1
(MAX
MODE
AH
Al
BH
CH
Bl
Cl
Dl
DH
SP
BP
SI
01
ii1i
ClK
READY
GND
RESET
FLAas
Figure 1. iAPX 88/10 CPU Functional Block Diagram
Figure 2. IAPX 88/10 Pin Configuration
Intel Corporation Assumes No Reaponaibilty for the Use of Any Circuitry Other Than Circuitry Embodied In an Intel Product. No Other Circuit Patent Licensee 8l'e Implied,
© INTEL CORPORATION. 1980
3-412
AFN.()0826D
IAPX 88/10
Table 1. Pin Description
The following pin function descriptions are for 8088 systems in either minimum or maximum mode. The "local bus" in
these descriptions is the direct multiplexed bus interface connection to the 8088 (without regard to additional bus
buffers).
Symbol
AD7-ADO
A15-A8
A19/S6, A18/S5,
A17/S4, A16/S3
Pin No.
~pe
9-16
I/O
Address Data Bus: Thesll lines constitute the time multiplexed memory/IO
address (T1) and data (T2, T3, TW,and T4) bus. These lines are active HIGH and
float to 3-state OFF during interrupt acknowledge and local bus "hold acknowledge".
2-8,39
0
Addres. Bus: These lines provide address bits 8 through 15 for the entire bus
cycle (T1-T4). These lines do not have to be latched by ALE to remain valid.
A15-A8 are active HIGH and float to 3-state OFF during interrupt acknowledge
and local bus "hold acknowledge".
34-38
0
Address/Status: During T1, these are the four
most significant address lines for memory operations. During I/O operations, these lines are
lOW. During memory and I/O operations. status
information is available on these lines during
T2. T3. Tw. and T4. S6 is always low. The status of
the interrupt enable flag bit (S5) is updated at
the beginning of each clock cycle. S4 and S3 are
encode1 as shown.
Name and
~unctlon
53
S4
o (LOW)
0
,
1 (HIGH)
56 IS
o (LOW)
,
0
,
0
CHARACTERIST~JL.
Alternate Data
Stack
Code or None
Data
This information indicates which segment register is presently being used for data accessing.
These lines float to 3-state OFF during local bus
"hold acknowledge".
RD
32
0
Read: Read strobe indicates that the processor is performing a memory or I/O
read cycle, depending on the state of the 10/~ pin or S2. This signal is used to
read devices which reside on the 8088 local bus. RD is active lOW during T2. T3
and Tw of any read cycle. and is guaranteed to remain HIGH in T2 until the 8088
local bus has floated.
READY
22
I
READY: is the acknowledgement from the addressed memory or I/O device that
it will complete the data transfer. The ROY signal from memory or I/O is synchronized by the 8284 clock generator to form READY. This Signal is active
HIGH. The 8088 READY input is not synchrbnized. Correct operation is not
guaranteed if the set up and hold times are not met.
INTR
18
I
Interrupt Request: is a level triggered input which is sampled during the last
clOCk cycle of each instruction to determ ine ifthe processor shou Id enter into an
interrupt acknowledge operation. A subroutine is vectored to via an interrupt
vector lookup table located in sYstem memory. It can be internally masked by
software resetting the interrupt enable bit. INTR is internally synchronized. This
signal is !jctive HIGA:.
TEST
23
I
'fES'f:
NMI
17
I
Non-Maskable Interrupt: is an edge triggered input which causes a type 2
interrupt. A subroutine is vectored to via an interrupt vector lookup table located
in system memory. NMI is not maskable internally by software. A transition from
a lOW to HIGH initiates the interrupt at the end of the current instruction. This
input is internally synchronized.
This signal floats to 3-state OFF in "hold acknowledge".
inp\lt is examined by the "wait for test" instruction. If the TEST input is
LOW, execution continues, otherwise the processor waits in an "idle" state. This
input is synchronized internally during each clock cycle on the leading edge of
ClK.
3-413
AFN.(l()826D
iAPX 88/10
Table 1. Pin Description (Continued)
Pin No.
Type
Name and Function
RESET
Symbol
21
I
RESET: causes the processor to immediately terminate its present activity. The
signal must be active HIGH for at least four clock cycles. It restarts execution, as
described in the instruction set description, when RESET returns LOW. RESET
is internally synchronized.
eLK
19
I
Clock: provides the basic timing for the processor and bus controller. It is
asymmetric with a 33% duty cycle to provide optimized internal timing.
Vee
40
,GND
1,20
MN/MX
33
Vee: is the +5V ±10% power supply pin.
GND: are the ground pins.
I
Minimum/Maximum: indicates what mode the processor is to operate in. The
two modes are discussed in the following sections.
The fol/owing pin function descriptions are for the 8088 minimum mode (i.e., MN/MX = Vee). Only the pin functions which
are unique to minimum mode are described; aI/ other pin functions are as described above.
10/M
28
0
Status Line: is an inverted maximum mode S2. It is used to distinguish Ii
memory access from an 1/0 access. 101M becomes valid in the T4 preceding a
bus cycle and remains valid until the final T4 of the cycle (I/O=HIGH, M= LOW).
101M floats to 3-state OFF in local ,bus "hold acknowledge".
WR
29
0
Write: strobe indicates that the processor is performing a writememory or write
1/0 cycle, depending on the state of the 101M signal. WR is active forT2, T3, and
Tw of any write cycle. It is active LOW, and floats to 3-state OFF in local b\ls "hold
acknowledge" .
INTA
24
0
INTA: is used as a read strobe for interrupt acknowledge cycles. It is active LOW
during T2, T3, and Tw of each interrupt acknowledge cycle.
ALE
25
a
Address Latch Enable: is provided by the processor to latch the address into
the 8282/8283 address latch. It is a HIGH pulse active during clock low of T1 of
any bus cycle. Note that ALE is never floated.
DT/R
27
a
Data Transmit/Receive: is needed in a minimum system that desires to use an
828618287 data bus transceiver. It is used to control the direction of data flow
through the transceiver. Logically, DT/R is equivalent to 51 in the maximum
mode, and its timing is the same as for 101M (T=HIGH, R=LOW). This signal
floats to 3-state OFF in local "hold acknowledge".
DEN
26
0
Data Enable: 'is provided as an output ,enable for the 8286/8287 in a minimum
system which uses the transceiver. DEN' is active LOW during each memory and,
1/0 access, and for INTA cycles. For a read or INTA cycle, it is active from the
middle of T2 until the middle of T4, while for a write cycle, it is active from the
beginning ofT2 until the middle ofT4. DEN floats to 3-stateOFF during local bus
"hold acknowledge".
30,31
1,0
HOLD: indicates that another master is requesting a local bus "hold". To be
acknowledged, HOLD must be active HIGH. The processor receiving the "hold"
r,equest will",ssue HLDA (HIGH) as an acknowledgement, in the middle of a T4 or
TI clock cycle, Simultaneous with the issuance of HLDA the processor will float
the local bus and control lines, After HOLD is detected as being LOW, the
processor lowers HLDA, and when the processor needs to run another cycle, it
will again drive the local bus and control lines.
HOLD,HLDA
Hold is not an asynchronous input. External synchronization should be
provided if the system cannot otherwise guarantee the set up time.
ssa
34
0
Status line: is logically equivalent to SO in th~
maximum mode. The combination of SSO, 101M
and DT/R allows the system to completely decode the current bus cycle status.
,,"0"' ~~~
, ,
r~
'
0
,
0
' ,
j"ow' ,' ,
'
\
3-414
,
~~;;~,~'
AFN-00826D
iAPX 88/10·
Table 1. Pin Description (Continued)
The following pin function descriptions are for the 8088, 8228 system in maximum mode (i.e., MN/MX =GND.) Only the pin
functions which are unique to maximum mode are described; all other pin functions are as described above.
Symbol
52,51, SO
Pin No.
26-28
~pe
o
Name and Function
Status: is active during clock high of T4, T1,
and T2, and is returned to the passive state
(1,1,1) during T3 or during Tw when READY is
HIGH. This status is used by the 8288 bus controller to generate all memory and I/O access
control signals. Any change by 52, 51, or SO
during T4 is used to indicate the beginning of a
bus cycle, and the return to the passive state in
T3 or Tw is used to indicate the end of a bus
cycle.
"
~ (LOW)
,,
1 (HIGH)
,,
",,
,,
,,,
,
.,,
,,
,,
,,
CMARACT£RISTtCB
Inte,ruplAcknowledge
ReaclVOporl
WrlleVOport
Hell
Code.~C"'
RNdmemory
Wrllamemory
PellllV8
These signals float to 3-state OFF during "hold
acknowledge". During the first clock cycle after
RESET becomes active, these signals are active
HIGH. After this first clock, they float to 3-state
OFF.
RQ/GTO,
RQ/GT1
30,31
I/O
Request/Grant: pins are used by other local bus masters to force the processor
to release the local bus at the end of the processor's current bus cycle. Each pin
is bidirectional with RQ/GTO having higher priority than RQ/GT1. RQ/GT has an
internal pull-up resistor, so may be left unconnected. The request/grant sequence is as follows (See Figure 8):
1. A pulse of one ClK wide from another local bus master indicates a local bus
request ("hold") to the 8088 (pulse 1).
2. DUring a T4 or TI clock cycle, a pulse one clock wide from the 8088 to the
requesting master (pulse 2), indicates that the 8088 has allowed the local bus
to float and that it will enter the "hold acknowledge" state at the next ClK.
The CPU's bus interface unit is disconnected logically from the .local bus
during "hold acknowledge". The same rules as for HOLD/HOLDA apply asfor
when the bus is released.
3. A pulse one ClK wide from the requesting master indicates to the 8088 (pulse
3) that the "hold" request is about to end and that the 8088 can reclaim the
local bus at the next ClK. The CPU then enters T4.
Each master-master exchange of the local bus is a sequence of three pulses.
There must be one idle ClK cycle after each bus exchange. Pulses are active
lOW.
If the request is made while the CPU is performing a memory cycle, it will release
the local bus during T4 of the cycle when all the following conditions are met:
1. Request occurs on or before T2.
2. Current cycle is not the low bit of a word.
3. Current cycle is not the first acknowledge of an interrupt acknowledge
sequence.
4. A locked instruction is not currently executing.
If the local bus is idle when the request is made the two possible events will
follow:
1. local bus will be released during the next clock.
2. A memory cycle will start within 3 clocks. Now the four rules for a currently
active memory cycle apply with condition number 1 already satisfied.
3-415
,I
AFN·00826D
intJ·
IAPX.88/10
Table 1. Pin De.crlptlon (Contlnue.d)
Symbol
LOCK
051,050
Pin No•.
~e
29
0
LOCK: indicates that other system bus masters are not to gain control of the
system bus while LOCK is active (LOW). The LOCK signal is activated by the
"LOCK" prefix Instruction and remains active until the completion of the next
instruction. This signal is active LOW, and floats to 3-state off in "hold acknowledge".
24, 25
0
Queue Status: provide status to allow external
tracking of the internal 8088 instruction queue.
' Name and Function
as,
o(LOW)
0
The queue status is valid during the ClK cycle
after which the queue operation is performed.
-
34
0
,
1 (HIGH)
QSO
,
0
,
0
CHARACTERISTICS
No operation
Firs! byte of opcode from queus
Empty the queue
Sublsequent byte from Queue
Pin 34 is always high in the maximum mode.
3-416
AFN.00826D
intJ
IAPX 88/10
the next higher address location. The BIU will automatically execute two fetch or write cycles for 16-bit
operands.
FUNCTIONAL DESCRIPTION
Memory Organization
The processor provides a 20-bit address to memory which
locates the byte being referenced. The memory is organized as a linear array of up to 1 million bytes, addressed
as OOOOO(H) to FFFFF(H). The memory is logically divided
into code, data, extra data, and stack segments of up to
'64K bytes each, with each segment falling on 16-byte
boundaries. (See Figure 3.)
All memory references are made relative to base
addresses contained in high speed segment registers. The
segment types were chosen based on the addressing
needs of programs. The segment register to 'be selected is
automatically chosen according to the rules of the following table. All information in one segment type s/:uire the
same logical attributes (e.g. code or data), By structuring
memory into relocatable areas of similar characteristics
and by automatically selecting segment registers, programs are shorter, faster, and more structured.
Certain locations in memory are reserved for specific
CPU operations. (See Figure 4.> Locations from addresses FFFFOH through FFFFFH are reserved for
operations including a jump to the initial system initial,ization routine. Following RESET, the CPU will always
begin execution at location FFFFOH where the jump
must be located. Locations OOOOOH through 003FFH are
reserved for interrupt operations. Four-byte pOinters
consisting of a 16·bit segment address and a 16-bit offset address direct program flow to one of the 256 possible interrupt service routines. The pointer elements are
assumed to have been stored at their respective places
in reserved memory prior to the occurrence of interrupts.
Word (16-bit) operands can be located on even or odd address boundaries. For address and data operands, the
least significant byte of the word is stored in the lower
valued address location and the most significant byte in
~FFFFFH
:CD}
_-L
CODE SEGMENT
Minimum and Maximum Modes
The requirements for supporting minimum and maximum 8088 systems are sufficiently different that they
cannot be done efficiently with 40 uniquely defined
pins. Consequently, the 8088 is equipped with a strap
pin (MN/MX) which defines the system configuration.
The definition of a certain subset of'the pins changes,
dependent on the condition of the strap pin. When the
MN/MX pin is strapped to GND, the 8088 defines pins 24
through 31 and 34 in maximum mode. When the MN/MX
pin Is strapped to Vee, the 8088 generates bus control
signals Itself on pins 24 through 31 and 34.
XXXXOH
} STACK SEGMENT
RESET BOOTSTRAP
PROGRAM JUMP
r--'---t---i
SEGMENT
REGISTER FILE
0
(
MSB
•
INTERRUPT POINTER
FOR TYPE 255
DATA SEGMENT
ES
INTERRUPT POINTER
FOR TYPE 1
}EXTRA DATA S.aMENT
INTERRUPT POINTER
FOR TYPE 0
'---+----1
"'C-..--..:;("OOOOOH
Figure 3. Memory Organization
Instructions
Figure 4. Reserved Memory
Segment Register
Used
Stack
CODE (CS)
STACK (55)
Local Data
DATA (OS)
External (Global) Data
EXTRA (ES)
3FFH
3FOH
•
OS
Memory
Reference Need
FFFFOH
•
t
E~~;~~~~~=~W=;-R_D~t:':-YT:SB:Ei J
FFFFFH
7H
4H
3H
OH
Locatlon~
Segment
Selection Rule
Automatic with all instruction prefetch.
All stac"k pushes and pops. Memory references relative to BP
base register except data references.
Data references when: relative to stack, destinatibn of string
operation, or explicitly overridden.
Destination of string operations: Explicitly selected using a
segment override.
3-417
AFN.()(l826D .'
x".
IAPX 88/10
The minimum ,mode 8088 can be used with either a
multiplexed or d~multiplexed b,us. The multiplexed bus
configuration Is compatible with the MCS-85™ multiplexed bus peripherals (8155, 8156, 8355, 8155A, and
8185), This configuration (See Figure 5) provides the user
with a minimum chip count system. This architecture'
provides the 808/3 processing power in a highly integrated
form.'
,
The demultiplexed mode requires one latch (for 64K 'addressabillty) or two latches (for a full megabyte of addressing). A third latch can be used for buffering if the
address bus loading requires It. An 8286 or 8287 transceiver can also be used if data bus buffering is required.
(See Figure 6.l The 8088 provides DEN and DTiR to con-
~OO~Il..OIMIOoo~rmw
trol the transceiver, ,and ALE to latch the addresses.
This configuration of the minimum mode provides the
standard demultiplexed bus structure with heavy bus
buffeting and relaxed bus timing requirements.
, ,
The maximum mode employs the 8288 bus ,controller.
(See E!.gure 7'> The 8288 decodes status lines SO, 81,
and S2, and provides the system with all bus control
signals. Moving the bus control to the 8288 provides
better source and sink current capability to the control
lines, and frees the 8086 pins for extended large system
features. Hardware lock, queue status, and two request!
grant interfaces are provided by the 8086 ion m~imum
mode. These features allow co-processors in local bus
and remote bus configurations.
3-418
AFN·OO826D
intJ
iAPX 88/10
A
/\
vi'
~~
CE
vee
I
POR!W
WA
PORTw.
8156
B
•
RD
ALE
PORT
DATAl
C
W
16)
ADOR
Y
IO/~
RESET
"At- A1'
lOW
ADDR
Y
AD
A
ADo - AD7
~
Vee
r
XI
-
t
D1
to.
-V
W
A8-10
8355 18755A
DATA
-Vee
iiii
-V
~
~
-
10ili
~
RESET
PORT
B
iDA
W
3c
.! ! ! t
I-
RESET
ADOR
101M
-
WR
f--
PORT
A
CE
~=
8088
READY
RESET
ALE
"""'"
~~
ALE
X2
eLk
-
ADDR/DATA
~
MN/MX
READY
RlS
eLK
INTIMER
OUT f--
Vss Vee Voo PROG
WA
OND
iiii
CE
I
8185
ALE
~I-
CS,CE.
\--
AS,Ag
ADo1
~
J t
v"
~
v"
'V
Figure 5. Multiplexed Bus Configuration
3-419
AFN.Q0828D
. iAPX88110
I-
i Ul
8Z84A
CLOCK
CLK
GENERAT:OA
on
T
MN/Ili
READY
IOJM
RESEr
RI!
WI!
r-Vce
,
- 51
ROY
GND
CPU
iNTi
01'/11
r---:l
I!EII
~GNO_~
ADo-AD,
AlE
I
I
srB
OE
I
8282
LATCH
.\a-A" rDDAIDA~
ADDRESS
(1,20A3)
J
INTR
L
[):T
OE
I
I
I
DATA
8286
TRANSCEIVER
F
-1\
-V
[
I[
[
[
I
I
ill liTT III
J1l
~
INTS:~:~PT I-CONTROL
I
2142 RAM (2)WOE
001
I
2116 2 PROM
~IIB
•
•
Rl!ml
MeS 80
PERIPHERAL
INT
~
Ifl--'RO-1
IV----:-
Figure 6. Demultlplexed Bus Configuration
IT
r Dl
U
B284A
CLOCK
GENERATOR
m
~
MNIf1,X
L
C K
eLK
GND
READY
SO
S;
SO
S;
REseT
SO
SO
....
ROY
GND
r-
CPU
-
AD!)-ADr
-
MRDe
MWTC
AMWC -NC
lORe
8288
DEN
C~~~R
OTiA
lowe
Alowe
ALE
-NC
INTA
r---:l
GHD-
I
ST.
OE
8282
LATCH
(1,20R3)
A,-A" ~ODRIOA~
INT
p=
F
I
I
ADDRESS
~
I
T
OE
I
8286
TRANSCEIVER
DATA
ill
~
8259A
INTERRUPT
CONTROL
!-
I
1JJ liJf JJRl!m I
WE~II
2142 RAM (2)
•
27162 PROM
~II
B
Mes 80
PERIPHERAL
F'R.o,
~
Figure 7.• Fully Buffered System Using Bus Controller
3-420
AFN·00826D
inter
IAPX 88/10
Bus Operation
The 8088 address/data bus is broken into three parts the lower eight address/data bits (ADO-AD7), the middle
eight address bits (A8-A15), and the upper four address
bits (A16-A19). The address/data bits and the highest
four address bits are time multiplexed. This technique
provides the most efficient use of pins on the proc·
essor, permitting the use of a standard 40 lead package.
The middle eight ,address bits are not multiplexed, i.e.
they remain valid throughout each bus cycle. In addi·
tion, the bus can be demultiplexed at the processor with'
a single address latch if a standard, non·multiplexed
bus is desired for the system.
Each pro~essor bus cycle consists of at least four eLK
cycles. These are'referred to as T1, T2, T3, and T4. (See
Figure 8). The address Is emitted from the processor
during T1 and data transfer occurs on "the bus during T3
and T4. T2 is used primarily for changing the direction of
the bus during read operations. In the event that a "NOT
READY" Indication Is given by the addressed device,
-:-!
! - - - - - - ( 4 + N w A I r ) _ TCY _ _ _ _ _ _ j--_ _ _ _ _ (4+NWAIT)_TCV _ _ _ _ _
T.
13
TWAIT
I
T1
T4
T2
f3
elK
GOES INACTIVE IN THE STATE
~~\'-------'----Ll.a~//U//ffZ ~'.
\
ADDRISTATUS
ADJ)R
-----8'-__
ADORIDATA
D_AT_A_OU_T_ID_7.D_O)_ _
~>---cx=
READV
DTIR
--MEMORY ACCESS TIME
\'--_---'1
Figure 8. Basic System Timing
3-421.
AFN.()()826D
inter
iAPX8BI10
"wait" states (Tw) are Jnserted between T3 and T4. Each
inserted' "wait" state is of the same duration as a ClK
cycle. Periods can occur between 8088 driven bus cycles.
These are referred to as "idle" states (Ti), or inactive ClK
cycles. The processor uses these cycles for internal
housekeeping.
OuringT1 of any bU's cycle, the ALE (address latch enable)
signal is emitted (by either the processor or the 8288 bus
controller, depending on the MN/MX strap). At the trailing
edge of this pulse, a valid address and certain status
information for the cycle may be latched.
Status bits SO, 51, and S2 are used by the bus controller, in
maximum mode, to identify the type of bus transaction
according to the following table:
52
S;
o (lOW)
0
-
50
CHARACTERISTICS
0
Interrupt Acknowledge
Read 1/0
Write 1/0
Halt
Instruction Fetch
Read Data from Memory
Write Data to Memory
Passive (no bus cycle)
0
0
1
0
0
1
1
0
1 (HIGH)
1
1
1
0
0
0
1
1
0
1
1
1
Status bits S3 through S6 are multiplexed with high order
address bits and are therefore valid during T2 through T4.
S3 and S4 indicate which segment register was used for
this bus cycle in forming the address according to the
following table:
54
53
o (LOW)
0
0
1
1 (HIGH)
1
0
l'
CHARACTERISTICS
Alternate Data (extra segment)
Stack
Code or None
Data
S5 is a reflection of the PSW interrupt enable bit. S6 is
always equal to O.
1/0 Addressing
In the 8088, I/O operations can address up to a maximum
of 64K I/O registers. The I/O address appears in the same
format as the memory address on bus lines A15-AO. The
address lines A19-A16 are zero in I/O operations. The variable I/O instructions, which use register OX as a pointer,
have full address capability, while the direct I/O instructions directly acjdress one .Qr two of the .256 I/O .byte
locations in page 0 of the I/O address space. I/O ports are
addressed In the same manner as memory locations.
Designers familiar with the 8085 or upgrading an 8085
design should note that the 8085 addresses I/O with an
8-bit address on both halves of the 16-bit address bus. The
8088 uses a full l6-bit address on its lower 16 address
lines.
EXTERNAL INTERFACE
Processor Reset and Initialization
Processor initfalization or start up is accomplished with
activation (HIGH) of the RESET pin. The 8088 RESET is
required to be HIGH for greater than four clock cycles. The
8088 will terminate operations on the high-going edge of
RESET and will remain dormant as lorig as RESET is HIGH.
The low-going transition of RESET triggers an internal
reset sequence for approximately 7 clock cycles. After this
interval the 8088 operates normally, begiilM1jng wiltt· ~e
instruction in absolute location FFFFOH. (See Figure 4.)
The RESET input is internally synchronized to the processor clock. At initialization, the HIGH to lOW transition of
RESET must occur no sooner than 50 p.safter power up, to
allow complete initialization of the 8088.
If INTR is asserted sooner than nine clock cycles after the
end of RESET, the processor may execute one instruction
before responding to the interrupt.
All 3-state outputs float to 3-state OFF during RESET.
Status is active in the idle state for the first clock after
RESET becomes active and then floats to 3-state OFF.
Interrupt Operations
Interrupt operations fall into two classes: software or
hardware initiated. The software initiated interrupts and
software aspects of hardware interrupts are specified in
the instruction set description in the iAPX 88 book or the
iAPX 86,88 User's Manual. Hardware interrupts can be
classified as nonmaskable or maskable.
Interrupts result in a transfer of control to a new program
location. A 256 element table containing address pointers
to the interrupt service program locations resides in absolute locations 0 through 3FFH (see Figure 4), which are
reserved for this purpose. Each element in the table is 4
bytes in size and corresponds to an interrupt "type." An
interrupting device supplies an 8-bit type number, during
the interrupt acknowledge sequence, which is used to
vector through the appropriate element to the new interrupt service program location.
Non-Maskable Interrupt (NMI)
The processor provides a single non-maskable interrupt
(NMI) pin which has higher priority than the maskable
Interrupt request (INTR) pin. A typical use would be to
activate a power failure routine. The NMI is edge-triggered
on a lOW to HIGH transition. The activation of this pin
causes a type 2 interrupt.
NMI is required to have a duration in the HIGH state of
greater than
clock"cycres, but is'",o"l'"required"IG'-be
synchrOnized to the clock. Any higher going transition ot.
NMI is latched on-chip and will be serviced at the end of
the current instruction or between whole moves (2 bytes in
the case of word moves) of a block type instruction. Worst
case response to NMI would be for multiply, divide, and
variable shift instructions. There is no specification on
the occurrence of the low-going edge; it may occur
two
3-422
AFN-00826D
IAPX 88/10
before, during, or after the servIcing of NMI.
Another high-going edge triggers another response if it
occurs after the start of the NMI procedure. The signal
must be free of logical spikes in general and be free of
bounces on the low-going edge to avoid triggering ex·
traneous responses.
Maskable Interrupt
and sample period. The interrupt return instruction includes a flags pop which returns the status of the
original interrupt enable bit when it restores the flags.
HALT
When a software HALT instruction is executed, the
processor indicates th.at it is entering the HALT state in
one of two ways, depending upon which mode is
strapped. In minimum mode, the processor issues ALE,
delayed by one clock cycle, to allow the system to latch
the halt status. Halt status is available on 10iM', DT/R,
and 550. In maximum mode, the processor issues appropriate HALT status on 52, 51, and SO, and the 8288
bus controller issues one ALE. The 8088 will not leave
the HALT state when a local bus hold is entered while in
HALT:ln this case, the processor reissues the HALT in·
dicator at the end of the local bus hold. An interrupt request or RESET will force the 8088 out of the HALT
state.
(I~TR)
The 8088 provides a single Interrupt request Input (INTR)
which can be masked Internally by software with the
resetting of the Interrupt enable (IF) flag bit. The in·
terrupt request signal Is level triggered. It Is Internally
synchronized during each clock cycle on the high·going
edge of CLK. To be responded to, INTR must be present
(HIGH) during the clock period preceding the end of the
current instruction or the end of a whole move for a
block type instruction. During interrupt response se·
quence, further interrupts are disabled. The enable bit is
reset as part of the response to any Interrupt (INTR,
NMI, software interrupt, or single step), although the
FLAGS register which is automatically pushed onto the
stack reflects the state of the processor prior to the in·
terrupt. Until the old FLAGS register is restored, the
enable bit will be zero unless specifically set by an in·
struction.
Read/Modify/Write (Semaphore) Operations
via LOCK
The LOCK status Information is provided by the proc·
essor when consecutive bus cycles are required during
the execution of an instruction. This allows the processor to perform read/modify/write operations. on
memory (via the "exchange register with memory"
instruction), without another system bus master receiving intervening memory cycles. This is useful in multiprocessor system configurations to accomplish "test
and set lock" operations. The ~ signal is activated
(LOW) in the clock cycle following decoding of the
LOCK prefix instruction. It is deactivated at the end of
the last bus cycle of the instruction following the LOCK
prefix. While LOCK is active, a request on a RQ/lTI pin will
be recorded, and then honored at the end of the LOCK.
During the response sequence (See Figure 9), the processor executes two successive (back to back) interrupt
acknowledge cycles. The 8088 emits the LOCK signal
(maximum mode only) from T2 of the first bus cycle until
T2 of the seoond. A local bus "hold" request will not be
honored until the end of the second bus cycle. In the
second bus cycle, a byte is fetched from the external in·
terrupt system (e.g., 8259A PIC) which identifies the
source (type) of the interrupt. This byte is multiplied by
four and used as a pointer into the Interrupt vector
lookup table. An INTR signal left HIGH will be continually responded to within the limitations of the enable bit
T,
ALE
I
T2
T3
T..
T,
I
T2
~~_---,---,n,--
__
T,
\1...--. _ _----11
FLOAT
ADo-AOr
Figure 9. Interrupt Acknowledge Sequence
3-423
AFN·00826D
inter,
IAPX, 88/10 '
External Synchronization via TEST
a byte of information is read from the data bus, as sup
plied by the Interrupt system logic (i:e. 8259A priority Interrupt controller). This byte identifies the source (type)
of the Interrupt. It ~s multiplied by four and used as a
pointer into the Interrupt vector lookup table, as described earlier.
As an alternative to Interrupts. the 8088 provides ..
single software-testable Input pin (TEST). This Input Is
utilized by executing a WAIT Instruction. The single
WAIT Instruction Is repeatedly exeouted until the ~
,Input goes active (LOW). The execution of WAIT does
not consume bus cycles once the queue Is full.
If a local bus request occurs during WAIT execution, the
8088 3-states all output drivers. If Interrupts are enabled.
the 8088 will recognlz~ Interrupts and process them.
The WAIT Instruction Is then refetched, and reexecuted.
Bus Timing -
Basic System Timing
In minimum mode, the MN/MX pin is strapped to Vee
and the processor emits bus control signals compatible
with the 8085 bus structure. In maximum mode, the
MN/MX pin is strapped to GND and the processor emits
coded status information which the 8288 bus controller
uses to generate MULTIBUS compatible bus control
signals.
System Timing - Minimum System
(See Figure ,8'>
,
The read cycle begins in 11 with the assertion of the address latch enable (ALE) signal. The trailing (lOW going)
edge of this signal is used to latch the address information, which is valid on the address/data bus (ADO-AD7)
at this time, into the 8282/8283 latch.,Address lines A8
through A15 do not need to be 'latched because they remain valid throughout the bus cycle, From Tl to T4 the
10fM signal indicates a memory or I/O operation. At T2
the 'address is removed from the address/data bus and
the bus goes to a high impedance state. The~ad control signal is also asserted at T2. The read (RD) signal
causes the addressed device to enable its data bus
drivers to the local bus. Some time later, valid data will
be available on the bus and the addressed device Will
drive the READY line HIGH. When the processor returns
the read signal to a HIGH level, the addressed device
will again 3-state its bus drivers. If a transceiver
(8286/8287) is required to buffer the 8088 local bus,
'
signals DT/A" and DEN are provided by the 8088.
A write cycle also begins with the assertion of ALE and
the emission of the address. The 101M" signal is again
asserted to indicate a memory or I/O write operation. In
T2, immediately following the address emission, the
processor emits the data to be written into the addressed location. This data remains valid until at least
the middle of T4. During T2, T3, and Tw, the processor
asserts the write control signal. The write (Vim) signal
becomes active at the beginning of T2, as opposed to
the read, whicH is delayed somewhat into T2 to provide
time for the bus to, float.
,
The basic difference between the inferrupt acknowledge cycle and a read cycle is that the interrupt
acknowledge (lNTA) signal is asserted in place of the
read (AD) signal and the address bus is Jloated. (See
Figure 9.>:.In the second of two successive INTA cycles,
Medium Complexity Systems
'(See Figure 10'>
For medium complexity syStems, the MN/MXpin Is connected to GND and the 8288 bus controller Is added to
the system, as well as an 828218283 latch for latching
the system addres~, and an 828618287 transceiver to
allow for bus loading greater than the 8088 Is capable of
handling. Signals ALE, DEN, and DTIA are generated by
the 8288 instead of the processor in 'this configuration,
although their timing remains relatively the same. The
8088 status outputs (52, SI, and SO) provide type of
cycle Information and become 8288 inputs. This bus
cycle information speCifies read (code, data, or 110),
write (data or 110), interrupt acknowledge, or software
halt. The 8288 thus issues control slg(1als specifying
memory read or write, I/O read or write" or Interrupt
acknowledge. The 8288 provides two types of write
strobes, normal and advanced, to be applied as required.
The normal write strobes have data valid at the leading
edge of write. The advanced write strobes have the
same timing as read strobes, and hence, data is not
valid at the leading edge of write. The 828618287 trans·
ceiver receives the usual T and OE inputs from the
8288's DT/R and DEN outputs.
The pOinter into the interrUPt vector table, whi,ch is
passed during the second INTA cycle, can derive from
an 8259A located on either the local bus or the system
bus. If the master 8289A prioJity interrupt controller is
positioned on the local bus, a TTL gate is required to
disable the 8286/8287 transceiver when reading from the
master 8259A during the interrupt acknowledge sequence and software "poll".
The 8088 Compared to the 8086
The 8088 CPU Is an 8-bit processor designed arouncf the
8086 internal structure. Most Internal functions of the
8088 are identical to the equivalent 8086 functions. The
8088 handles the external bus the same way the 8086
does with the distinction of ha(1dllng only 8 bits at a
time. Sixteen-bit operands are fetched or written in two
consecutive bus cycles. Both processors will appear
Identical to the software engineer, with the exception of
execution time. The Internal register structure is identical and all instructions have the same end result. The
differences between the 8088 and 8086 are outlined
below. The engineer who is unfamiliar with the 8086 is
referred to the iAPX 86, 88 User's Manual. Chapters 2 and
4, for function description and instruction set information:
Internally, there are three differences between the 8088
and the 8086. All changes are related to the 8-bit bus intertace.
3-424
AFN.ooe26D
intJ
IAPX 88/10
• The queue length Is 4 bytes in the 8088, whereas the
8086 queue contains 6 bytes, or three words. The,
queue was shortened to prevent overuse of the bus by
the BIU when prefetching instructions. This was required because of the additional time necessary to
fetch instructions 8 bits at a time.
• To further optimize the queue, the prefetchlng algorithm was changed. The 8088 BIU will fetch a new instruction to load into the queue each time there Is a 1
byte hole (space available) In the queue. The 8088
waits until a 2-byte space is available.
• The internal execution time of the instruction set is
affected by the 8-bit interface. All 16-bit fetches and
writes from/to memory take an additional four clock
cycles. The C~U is also limited by the speed of instruction fetches. This latter problem only occurs
when a series of simple operations occur. When the
more sophisticated instructions of the 8088 are being
used, the queue has time to fill and the execution proceeds as fast as the execution unit will allow.
The 8088 and 8086 are completely software compatible
by virture of their identical execution units. Software
that is system dependent may not be completely transferable, but software that is not system dependent will
operate equally as well on an 8088 or' an 8086.
The hardware interface of the 8088 contains the major
differences between the two CPUs. The pin assignments are nearly identical, however, with the following
functional changes:
• A8-A15 - These pins are only address outputs on the
8088. These address lines are latched Internally and
remain valid throughout a bus cycle in a manner
similar to the 8085 upper address lines.
• BHE has no meaning on the 8088 and has been eliminated.
• ~ provides the S() status information in the minimum mode. This output occurs on pin 34 in minimum
mode only. Dr/R, IO/~l, and SSO provide the complete
bus status in minimum mode.
• loiM has been inverted to be compatible with the
MCS-85 bus structure.
• ALE is delayed by one clock cycle in the minimum
mode when entering HALT, to allow the status to be
latched with ALE.
,
3-425
\
,.
AFN-00B26D
"n+ -,I"
III-e-
iAPX88/10
T,
eLK
~
T,
T.
/
/
T.
H-..
Q51,Q50
'>(
52,51,SO
// / / /
8088
AI9/56-AI6/S3
A19-A16
ALE
'\
ROY
8284
READY
8088
8288
AD7-ADO
8088
A15-A8
\~-=-====
56-53
,--
/'
.
A7-AO
X
DATA IN
-C
A15-A8
RD
I
DT/R
8288
MRDe
\.
DEN
Figure 10. Medium Complexity System TImIng
3-426
AFN·00826D
iAPX 88/10
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ......... O·C to 70·C
Storage Temperature ............. -65·C to + 150·C
Voltage on Any Pin with
Respect to Ground .................. - 1.0 to + 7V
Power Dissipation ........................ 2.5 Watt
D.t. CHARACTERISTICS
Symbol
"NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended perio,ds may affect device
reliability.
(8088: TA = O°C to 70·C, Vee = 5V ±10%)"
(8088-2: TA = O·C to 70·C, Vee = 5V ±5%)
Min.
Max.
Units
Input Low Voltage
-0.5
+0.8
V
VIH
Input High Voltage
2.0
Vee +0.5
V
VOL
Output Low Voltage
0.45
V
IOl
VOH
Output High Voltage
V
IOH
Icc
340
350
250
mA
TA
III
8088
Power Supply Current: 8088-2
P8P88
Input Leakage Current
±10
/LA
OV,,;VIN,,;Vee
ILO
Output Leakage Current
"t10
/LA
0.45V ,.; VOUT ,.;
Vee
Vel
Clock Input LowVoltage
-0.5
+0.6
V
VeH
Clock Input High Voltage
3.9
Vce+ 1.O
V
CIN
Capacitance if Input Buffer
(All input except
ADo-AD7, RO/GT
15
pF
fc
= 1 MHz
CIO
(ADo-A~,
Capacitance of I/O Buffer
RO/GT
15
pF
fc
= 1 MHz
Vil
Parameter
2.4
Test Conditions
= 2.0mA
= -400 /LA
= 25°C
"Note: For Extended Temperature EXPRESS Vcc=5V±5%
3-427
AFN.Q0826D
iAPX 88/10
A.C. CHARACTERISTICS
(8088: TA = O°C to 70°C, Vee = 5V ±10%)·(8088-2: TA = O°C to 70°C, Vee =5V ±5%)
MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS
I
Symbol
Parameter
8088
,
8088-2
Min.
Max.
Min.
Max.
Units
500
125
500
ns
Test
Conditions
TClCl
ClK Cycle Period
200
TClCH
ClK low Time
118
68
ns
TCHCl
ClK High Time
69
44
ns
TCH1CH2
ClK Rise Time
10
10
ns
From 1.0V
to 3.5V
TCl2Cl1
ClK Fall Time
10
10
ns
From 3.5V
to 1.0V
TDVCl
Data in Setup Time
30
20
ns
TClDX
Data in Hold Time
10
10
ns
TR1VCl
ROY Setup Time
into 8284 (See
Notes 1, 2)
35
35
ns
TClR1X
ROY Hold Time
into 8284 (See
Notes 1, 2)
0
0
ns
118
68
ns
TRYHCH
READY Setup
Time into
8088
TCHRYX
READY Hold Time
into 8088
30
20
ns
TRYlCl
READY Inactive to
ClK (See Note 3)
-8
-8
ns
THVCH
HOLD Setup Time
35
20
ns
TINVCH
INTR, NMI, TEST
Setup Time (See
Note 2)
30
15
ns
TlLlH
Input Rise Time
(Except ClK)
20
.20
TIHll
Input Fall Time
(Except ClK)
12
12
\
ns
From 0.8V
t02.0V
ns
From 2.0V
to 0.8V
-Note: For Extended Temperature EXPRESS Vcc=5V±5%
3-428
AFN·00826D
infef
iAPX 88/10
A.C. CHARACTERISTICS (Continued)
•
TIMING RESPONSES
8088
Symbol
Parameter
8088-2
Min.
Max.
Min.
Max.
Units
10
110
10
60
ns
80
TCLAX
TCLAV
AddressValid Delay
TCLAX
Address Hold Time
10
TCLAZ
Address Float Delay
TCLAX
TLHLL
ALE Width
TCLLH
ALE Active Delay
80
50
ns
TCHLL
ALE Inactive Delay
85
55
ns
TLLAX
Address Hold Time to
ALE Inactive
TCLDV
Data Valid Delay
TCHDX
Data Hold Time
TWHDX
Data Hold Time After WR
TCVCTV
Control Active Delay 1
10
110
10
70
ns
TCHCTV
Control Active Delay 2
10
110
10
60
ns
TCVCTX
Control Inactive Delay
10
110
10
70
ns
TAZRL
Address Float to READ
Active
0
TCLRL
RD Active Delay
10
165
TCLRH
RD Inactive Delay
10
150
TRHAV
RD I nactive to Next
Add ress Active
110
10
ns
60
10
TCLCH-30
ns
10
100
ns
10
80
ns
TCLCL-40
ns
TCLHAV
HLDA Valid Delay
TRLRH
RDWidth
2TCLCL-75
2TCLCL-50
ns
TWLWH
WRWidth
2TCLCL-60
2TCLCL-40
ns
TAVAL
Address Valid to ALE Low
TCLCH-60
TOLOH
Output Rise Time
20
20
ns
From 0.8V to 2.0V
TOHOL
Output Fall Time
12
12
ns
From 2.0V to 0.8V
A.C. TESTING INPUT, OUTPUT WAVEFORM
10
CL = 20-100 pF for
all 8088 Outputs
in addition to
internal loads
ns
0
160
ns
ns
TCLCH-30
TCLCL-45
ns
ns
TCHCL-10
e10
10
50
TCLCH-10
TCHCL-10
10
ns
10
TCLCH-20
Test Conditions
100
TCLCH-40
ns
ns
A.C. TESTING LOAD CIRCUIT
INPUT/OUTPUT
DEVICE
UNDER
rEST
~CL01DDPF
~
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1 AND 0 45V FOR
A LOGIC 0 THE CLOCK IS DRIVEN AT 4 3V AND 025V TIMING MEASUREMENTS ARE MADE AT 1 SV FOR BOTH A LOGIC 1 AND 0
C L INCLUDES JIG CAPACITANCE
3-429
AFN.Q0826D
intel"
iAPX 88/10
WAVEFORMS
BUS TIMING-MINIMUM MODE SYSTEM
T1
T2
C.
I~
VCH~I---h:CTCLCL
_ _ TCH1CH21
elK (8284 Output)
101M.
SSO
~
~
TCHCTV
•
_+-_-..,:--JI'--:-__+ ____+-__+-__-4__-+___+_.-J
A1s-Aa
A15 - As (Float during INTA)
-
-+---+-J.J'-~--~----+_--+_---+--_4----~JJ
TClAV--
TCLLH-
r
:=,TfLDV
TCLAX-
TCHDX ---
TLH~L-=:
r--
ALE
/
TCHLL _ .I
c.-'-+--4-+---+_-T-R-1V-C-l+--+----+---..J- - - -
I-TAVAL-
ROY (8284 Input)
SEE NOTE 5
:r~~
~W~~~~~
I'
-::;.:
!--TCLR1X
'~R.'-+-----+J
1r-_ _-_h-TCHRyX
TRYHCHl
-TcIAZ
AD7-ADO
TAZRL-->;
'--+----+-------
CTDVCL--TCLDX-
_~FLOAT!
-I-----"""Jr--A-D-'.-A-DO+-'
-
-
DATA
r
l4----:F""L"'OA"'T::-r-{J,
IN
--i
TCLRH-
f--- TRHAV-I
-+------~--,J
READ CYCLE
(NOTE 1)
(WR. iNTA = VOH)
ri
-=_
r-~
'+--+_ _ _ _+--J~
TCHCTV
~
TCLRL 1 - - - 1 - - + - - + ; - TRLRH - - - + - - 1
_______
-{f. ______
-+~~
TCVCTV-
~
__
TCVCTX -
I
TCHCTV
1
~..J
' - - _ _ _ _- J
3-430
AFN-00826D
iAPX 88/10
WAVEFORMS (Continued)
BUS TIMING-MINIMUM MODE SYSTEM (Continued)
elK (8284 Output)
ACT-ADO
WRITE CYCLE
NOTE 1
AC7- AD o
DTIR
INTA CYCLE
NOTES 1,3
(RD, WR =VOH)
SOFTWARE HALT INVALID ADDRESS
DEN,REi,WR,INTA = VOH
. DTJii INDETERMINATE
SOFTWARE HALT
relAV
NOTES:
1 ALL SIGNALS SWITCH BETWEEN VOH AND VOL UNLESS OTHERWISE
SPECIFIED.
2. ROY IS SAMPLED NEAR THE END OF T2, T3, Tw TO DETERMINE IF Tw
MACHINES STATES ARE TO BE INSERTED.
3. TWO INTA CYCLES RUN BACK·TO·BACK, THE 8088 LOCAL ADDR/DATA
BUS IS FLOATING DURING BOTH INTA CYCLES CONTROL SIGNALS
ARE SHOWN FOR THE SECOND INTA CYCLE
4. SIGNALS AT 8284 ARE SHOWN FOR REFERENCE ONLY.
5. ALL TIMING MEASUREMENTS ARE MADE AT 1.5V UNLESS OTHERWISE
NOTED.
3-431
AFN·00826D
IAPX 88/10
A.C. CHARACTERISTICS
MAX MODE SYSTEM (USING 8288 BUS CONTROLLER)
TIMING REQUIREMENTS
8088
Symbol
Parameter
8088·2
Min.
Max.
Min.
Max.
Units
500
125
500
ns
Test Oondltlons
TClCl
ClK Cycle Period
200
TClCH
ClK low Time
118
68
TCHCl
ClK High Time
69
44
TCH1CH2
ClK Rise Time
10
10
ns
From 1.0V to 3.5V
TCL2Ct1
ClK Fall Time
10
10
ns
From 3.5V to 1.0V
TDVCl
Data In Setup Time
30
20
ns
TClDX
Data In Hold Time
10
10
ns
TR1VCl
ROY Setup Time into 8284
(See Notes 1. 2)
35
35
ns
TClR1X
ROY Hold Time into 8284
(See Notes 1, 2)
0
0
ns
TRYHCH
READY Setup Time into
8088
118
.68
ns
ns
ns
TCHRYX
READY Hold Time into 8088
30
20
ns
TRYlCl
READY Inactive to ClK (See
Note 4)
-8
-8
ns
TINVCH
Setup Time for Recognition
(INTR, NMI, TEST)
(See Note 2)
30
15
ns
TGVCH
RQ/GTSetup Time
30
15
ns
TCHGX
RQ Hold Time into 8086
40
30
ns
TILIH
Inpllt Rise Time
(Except ClK)
20
20
ns
From 0.8V te' 2.01f1
TlHll
Input
~all
12
12
ns
From 2.0V to 0.8V
Time (Except ClK)
NOTES:
1.
2.
3.
4.
Signal at 8284 or 8288 shown for reference only.
Setup requirement for asynchronous signal only to guarantee recognition at next elK.
Applies only to T2 state (8 ns into T3 state).
Applies only to T2 state (8 ns into T3 state).
3-432
AFN·OO826D
inter
IAPX 88/10
A.C. CHARACTERISTICS
TIMING RESPONSES
8088·2
8088
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
TClMl
Command Active Delay (See
Note 1)
10
35
10
35
ns
TClMH
Command Inactive Delay (See
Note 1)
10
35
10
35
ns
TRYHSH
READY Active to Status Passive
(See Note 3)
65
ns
TCHSV
Status Active Delay
10
110
10
60
ns
TClSH
Status Inactive Delay
10
130
10
70
ns
10
10
110
10
10
60
ns
ns
TClAX
80
TClAX
50
ns
TClAV , Address Valid Delay
TClAX
Address Hold Time
110
TClAZ
Address Float Delay
TSVlH
Status Valid to ALE High (See
Note 1)
15
15
ns
TSVMCH
Status Valid to MCE High (See
Note 1)
15
15
ns
TOllH
ClK low to ALE Valid (See
Note 1)
15
15
ns
TClMCH
ClK low to MCE High (See
Note 1)
15
15
ns
TCHll
ALE Inactive Delay (See Note 1)
15
15
ns
15
ns
60
ns
.
15
TClMCl
MCE Inactive Delay (See Note 1)
TClDV
Data Valid Delay
10
TCHDX
Data Hold Time
10
TCVNV
Control Active Delay (See
Note 1)
5
45
5
45
ns
TCVNX
Control Inactive Delay (See
Note 1)
10
45
10
45
ns
110
10
10
ns
-0
TAZRl
Address Float to Read Active
.0
TClRl
RD Active Delay
10
165
10
100
ns
TClRH
RD Inactive Delay
10
150
10
80
ns
TRHAV
RD Inactive to Next Address
Active
TCHDTl
Direction Control Active Delay
(See Note 1)
59
50
ns
TCHDTH
Direction Control Inactive Delay
(See Note 1)
30
30
ns
TClGl
GT Active Delay
85
50
ns
TClGH
GT Inactive Delay
50
ns
TRlRH
RDWidth
TOlOH
OUfput Rise Time
TOHOl
Output Fall Time
Titst Conditions
Ct.
= 20·100 pF for
all 8088 Outputs
in addition to
internal loads
ns
(
TClCl-40
TClCl-45
85
2 rClCl-75
\
3-433
ns
ns
2TClCL 50
20
20
ns
From 0.8Vto
2.0V
12
12
' ns
From 2.0V to
0.8V
AFN,00826D
IAPX88/10
4,
I
WAVEFORMS
BUS TIMING-MAXIMUM MODE
T,
r- --j
n
I---TCLCL-TCH1CH21
CLK
VCH,r--"\
VCL...!
~
TCLAV·
QSo,QS,
.
C
r--\
1''----
T.
i-TCL2CL1
---
I---- TCHCL
r"
Tw
•
r-\'
i
-!
I'
-..,.---t--' I
I-'
TCHSV
\-----'------
r.,I1,SO (EXCEPT HALn
_
I----i
I--TCLAV
------1-'I--..
TCLAX
SEE NOTE 5
1
TCLDV
TCHDX-
,0-
- h r.:.lr--I---+-+-+--f---+"""\Ir----
I
A,lt A'8
~ _
TSVLH
TCLLH.
ALE (8288 OUT pun
"----
_TCLCH_'
I.-
.1
TCHLL
____¥JIr-~~,I~--~--~~+--4--~~-J.~==
14
I-T~1VCL
~K '!;~~~~~\~~
ROY (8284 INPUn
TRVLCL
__
-
1
-TCHRYX
TTRYHSH-
-l.... TCLAX t---::T!::,RY"'"H""CH,.,._J
READ CYCLE.
-TCLAZ
AD7-ADo
~
I
l--±Ff('-:O~AT=--=.K.I\
ADt-ADo
TAZRL- RD
8288 OUTPUTS
SEE NOTES 5,6
I
-
TDVCL--TCLDXDATA IN
FLOAT
rI+----
,/
m_H_D_TL_l-_~,rr-r---~T~C~LR-Lr---~---------+---JI~
_ _____
\
I'
TCLAH i-----t--+rTAHAV---i
I--H----TRLRH------l-----II
TCHDTH
\
~--~-------~-~~
DTIA
-
TCLML-
TCLMH-
r;.
Y~~~-----~.f - j
MiiiiC OR Il!Iil:
TCVNVDEN
______
~
_ _ _ __ J
TCVNX-
3-434
AFN.00826D
inter
IAPX 88/10
WAVEFORMS (Continued)
r
BUS TIMING-MAXIMUM
VCH
MODE SYSTEM
CLK
(USING 8288)
VCl
r-\
f-----I
r--'I
-
J~ ~nil////I ,i--
12. ii. SOIEXCEPT ~ALT)
WRITE CYCLE
-
I-
TCLAV-
TCI..O~1::"
~
rCLSH
TCLAK
A
TCYNV-
---------_.
note 8}
-
TCHDX-
DATA
-
TCVNX-
~
DEN
8'" OUIP\IIS
see NOTES 5,8
-
TCLMH-
i-TCLML
-
_TCLMH
f=0VCL-
!-TCLDX
AMWC; OR AIOWC
_
I-
{TCL,ML
MWTC OR lowe
INTA CYCLE
A'S-Aa
FLOAT
(SEE NOTES 3,4)
RESERVED FOR
CASCADE ADDR
- /-JTrZ \
AOt·ADO
~I'
TSVMCH-
TCLMCH---
DT/R
82111 OUIP\IIS
SEe NOTES 5,6
/I
FLOAT
FLOAT
V
~
i
FLO'{)
iCLMCl-1
tJ d"= /
0-
MCEI
i'Imi
\
POINTER
/
I
\
\-
r--
----
TCHDTH
\
TCLMl-
INTA
FLOAT
TCVNV
- {1MH
DEN
TCVNX-
SOFTWARE
-HALT - (DEN =voufm,JlIU)C,mRC,MWTC,AMWC,IOWC,ATOWC,ifffA,OT/" = VOH
AD1- ADO.A,s- Aa
INVALID ADDRESS
TelAY
jr----------.. .,. . -- ----\._-----
~
\~--~
NOTES'
1 ALL SIGNALS SWITCH BETWEEN YOH AND VOL UNLESS OTHERWISE
SPECIFIED.
2. ROY IS SAMPLED NEAR THE END OF T2, f3, Tw TO DETERMINE IF Tw
MACHINES STATES ARE TO BE INSERTED.
3. CASCADE ADDRESS IS VALID BETWEEN FIRST AND SECOND INTA
CYCLES.
4. TWO INTA CYCLES RUN BACK·TO-BACK. THE 8088 LOCAL ADDRIOATA
BUS IS FLOATING DURING 80TH INTA CYCLES CONTROL FOR
POINTER ADDRESS IS SHOWN FOR SECOND INTA CYCLE.
5. SIGNALS AT 8284 OR 8288 ARE SHOWN FOR REFERENCE ONLY
6. THE ISSUANCE OF THE 8288 COMMAND AND CONTROL SIGNALS
1!I1IIll:, 1!WTl:. A'MWe. =.IOWC. ~.1liTA AND DEN) LAGS THE
'ACTIVE HIGH 8288 CEN.
7. ALL TIMING MEASUREMENTS ARE MADE AT 1 5V UNLESS OTHERWISE
NOTED
8. STATUS INACTIVE IN STATE JUST PRIOR TO T4 •
3-435
AFN-00826D
inter
iAPX88/10
WAVEFORMS (Contin'ued)
BUS LOCK SIGNAL TIMING
(MAXIMUM MODE ONLy)
ASYNCHRONOUS
SIGNAL R~OGNITION
Any elK
cycle--j
CLK
NMI
lNTR
NOTE: 1. SETUP REQUIREMENTS FOR ASYNCHRONOUS
S.oNALS ONLY TO GUARANTEE RECOGNITION AT NEXT elK
REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLy)
1_ _ ' " " " " ' ' ' - ' _ _
>o""'~
~
...JrCLGL_
1
Prirlllousgrani
A1t1StAl~'~::
1-'_ _ _ _ _ _ _ _ _ _ _ _- - - - /
....
A01-AOo
~~
COPROCESSOR
1-1- - - - - - - - - - - - - - - /
JSEE NOTE 1)
NOT( 1 THE COPROCESSOR MAY NOT DRIVE THE BUSSES OUTSIDE THE REGION
SHOWN WITHOUT RISKINQ CONTENTION
ijOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLy)
ell'.
~
~_'OR2CYCr1
_"LKCYCLE_
-
\ _I
_THVCH
HOlD~
-+----1
1__----------,I----~'·r-~T~'~lA~Z,----~I---------,
"18
COPROCESSOR
3-436
AFN-008260
inter
IAPX 88/10
IAPX 86/10, 88/10
INSTRUCTION SET SUMMARY
........
OATA TRAMBIER
~o
(1100011w!modOOO
ImmedIate 10
(!
w jmod lell ~
1 0 1 I w reg
1~9'Slef
dala ,I w 1
10 10 0 0 0 w
Accumulator 10 memory
I 1 0 1 0 0 0 1 VI
\
Q(i(i(j1-,
I mod O~
IleO,Sltfimemo,'/ 10 segmem regIster
Seijmenl reg,sIer 10 reglster/memorV
....
00
Aeglslerlmemory
11111111
01010
Segmenl regiSter
OOOreQl10
....
".
attar nIgh
add. low
add, hIgh
11m
10001111
Rtg"ler
01011
Segmenl register
OOO/egll!
I
100000 s W mod 11 I rim
001 I 1 lOw
data
~u: :::~p~~ al:I~:,~::rd~ublracl
F.:"::~:~:'i";~:::-:+-m::,,-;-,700;-0C-,:em'
11 I I I 0 \ 1 W !mod I 0 \ 'm
'1010' 0 0
D,v,de runSlgnedl
I 11
IDIV Inlegrrdtvlde ISlqnedl
CWO
Con~erl
dala Ilsw 01
0000' 010
\ I 1 10' I W mod 110 ,m
, 1011 w Imod 1 I , ,m
I
)I'OIOlOllooo~
UOASClladlusllordlvlde
Convert Oyle to WOld
~
accumulator
:m(ldO~
~
DIV
,m
hetlanD'
w.'~
w
AlSASCliadlust10rsublract
caw
Register
0 11
RegIster memory and regIster
Imme{hM~ WIth reglste' 'memory
Immedlale WIth accumulator
'"
\ 1000011 w Imod
71143%10
eM' Campau
INUl Inteller mu1hply ISlgned\
Reg'sterlmemo1ywllh regIster
IN=I~pul
Iiii::'
.16 Change slg(l
mOd~
modO 0 0
71543%10
1 1 1 1 1 w !mOdO 0 1 rim!
~
RegIster
UM ASClladluSllor multiply
ileglster/memorV
XCMS
ado! low
LiiITi_:.. 10 Imod O,~
Regls!e.
pop
~da~~~
1I50rlO
111543210
1"
Reglstel/memorv
I,m!
Memory 10 aCCymulalor
PUSN
.'111/11
IIEC
RegIster/memory lolhomre9,sler
ImmeO,31e10 reglsleflmemory
, 001 tOO 0
wora to aouolewo,d
, 001 100 ,
',m~
from
~~
POll
F'Keaport
111001 I w
pon
Vaflableporl
ILAY,TransJalebyleloAL
1 I 1011 1 w
11010111
UA·LoadEAtoreo,ster
10001101
F,ullpo!l
Vaflabttport
H
10 11 Ow
LOGIC
OUT' OulpullO
NOT
LOl'LoadpolnlertoOS
11000101
l£l·LoadpolnlerlofS
11000100
LAIiF-loadAH WIlli lIags
10011111
IIIIIF StoreAHlnlOfiaos
10011110
",1IIf"Push flailS
100111 0
P8Pf,Popllalis
10011101
mo'
I I 0 100 v w mod 1 0 1 t m
S~llI
311lhmellc IIghl
V
W moo 100 1m
I 1 0 I 0 0 v w mod 1 I 1 ,m
~
AOl Rotale lell
I 10 I 0 0 v
MOR Rotate "9"t
1 1 0 1 0 0 v W moao 0 I 1m
RCt ROlatelnrougllcMrV
Itag
lett
RCA Rolale Ihlough rarry IIgnl
a
11 ~~,~
l' 0 1 0 0
5HR Shltlloglcal IIghl
SAR
".
".".
["1'"'-'-0
Inverl
SilL/SAL Shill logIcal a"lhmell( lett
AND
modO 0 0 , m
1 10100 v w modO 1 0 ,'m
I 10100 v W modO I ,
And
Reg memo'~ and reqlSler to ellhe,
Immealate 10 'eglster . ~,emory
F[i"T~o~,:,::o~o~o~,;;w+-1m~"~"",
• .;,;;;4---,;:;:---,----,=c::-;,
1 0 0 0 0 0 0 w mOd 1 0 0 rim
data
data II w I
0010010 w
AAITKMETIC
ADD
Uci
Reo /memory Wllh reglsler to elmel
tmmed,ale 10 regIster/memory
Immedlille10 accumulalOr
100ci-o o-o-a~ilm;;;;~l
1
00000 s w mod 000 I m
~!1u_._~""l.
~ .. ~~~" _J
_~dt" II ~....!=:J
dat~ ~l""<'_W"~
OR
"
Add willi tarry
ReQ Imemory With regIster to either
~OO"~ ;rmOd-ieg"~
ImmedIate 10 rfQlste,'memory
lii 0 0 0 0 ~ w I mod 0 ~~-"-~
Immed,ate to accumulator
~.~L"_" ~l
__
aalal 1 w I ]
j~l~
t1
sW o~J
". dm"m
000010 d w
mo'
Immed,ale 10 reqlster,memory
1000000
modO 0 I
Immedlalelo accumulator
0000110 W
ReQ Imemoryand ,eglster toerlhe,
AIM:
'OR
W
data II w I
data II wI
hclu,lv"r
". dm"m
ReQ {memory and reQlster10 e,tner
001100 d w
tmmedlaleto reglsler/memory
1000000 W mOdt 1 0
0011010 w
Immedlalelo accumulato'
su. SUMrKt
lleQlmemorYlndrelO!tS!eflofltntr
00 \ 0 t 0 d W mod reg
rm
Immedlitehom register/memory
STAING MANIPULATION
tmmedlale hom accumulator
REP=Reput
MOVS=Mov~
'II. ·lIIItnctwlttl ........
1111001Z
by1e/word
tMPS=Compare byte/word
to 1001 t w
SCAS=ScanbVle/word
1010 tIl w
LOOS=LoiKl byte/wd 10 AliAX
10101 lOw
STOS='ilor bVle/wd trom ALIA
1010 I 0 1 w
MnemonICS ©Intel, 1978
3-437
AFN-Q0826D
iAPX 88/10
INSTRUCTION SET SUMMARY (Continued)
CONTROL TBAISFER
CALL· Coli.
18
DIrect wltllIn segment
11101000
IndlreclwithmSe{lmenl
1 "11111
Dlrectmtersegment
1001'010
Indirect Intersegment
JM'
=,
~"3
11543210
21 0
1 1 1 1 1 "
dlsplow
1 8 5 .. 3 21 0
18543210
J"/JAE Jump on not below/above
,
orequat
J"E/JA Jump on nOI below or
dlsphlgh
mod 010 rim
ollsel·low
otfse!-hlgh
seg-Iow
seg-hlgh
1 mod 01 ,
equal/above
JIP/JPO Jump on nol par/par odd
JIO Jump on nOloverflow
"m
JIS Jump on nOI sign
lOOP LoopCX Itrnes
UnandtttDftl1 Jail,:
Direct wlthm segment
"'101001
dlsp-Iaw
Olrecl III/llhm segmenl-short
11101011
dlsp
Indlrect.wllhmsegmenl
11"
Olfullnlersegmenl
1'1'0'0101
, 1 1 1 1 Imod 100
Indlrecllntersegment
1'1"
1
seg-Iow
seghlgh]
Wlth,nseg addmgImmedto SP
1,1000010!
Intersegment
!,1001011!
Intersegment adding Immediate to Spi'l 0010 I 0
"m
I
data low
dalahlgCl
data low
d~=:J
dlsp
01110111
dlsp
10111101'1
dlsp
1011100011
dlsp
101 11 1001 1
'1'00010
dlSp
dlsp
1,100000
dlsp
11 100011
dl5p
Typespecl'led
1 10011 0 1
type
Type 3
11001100
1'10011'0
IRn Inlerruplrelurn
~2iJ
PROCESSOR CONTROL
F'lOoJ]
ClCClealcarry
01111100
dlSp
CMC Complement carry
101 1 11 11 0 1
dlsp
STC Sel carry
011 10010
dlsP
ClDCleardllection
011 101 10
dlsp
STDSeldtreclion
[." 1 11 1
01111010
dlSP
CLiCleiHon'err upl
[~ 1 1 I 1 0 1 0
1011 1 0000
OISP
STrSellnlerrupl
~Q
dlSp
HlTHal 1
JIE/JIIIZ=Jump on nOI eQuallnOI zero 01110101
JIIIlIJII=Jump on not leSS/Qreater
01111101
or equal
J.U./J'~Jumpon nol less or equal!
!01111111
greater
dlsp
WAIT Watl
dlsp
ESC Escape {to
"'iCJ
LOCK 8us lock Dreltx
J8~Jump
on Sign
I
10" I 1000 I
!
1
!
IIilTO Interrupt eln overflow
dlsp
on overflow
]
'"terrupl
01110100
JO~Jump
I
drsp
1110000'
INT
I
1" 0 0001 1
JP/JPE:Jump on parity/panty eyen
otlse~
I
Wl1I'IInsegment,
JE/Jl'Jumpon eQuallzero
Jl/J.IIE~Jump on less/not greater
or equal
JU/J.8~Jumpon less or equal/not
greater
JI/JllAf>Jump on below/not above
or equal
JIElJ"~~~~Co~~ below or eQuall
0115ellow
1 1 , 1 mod 1 0 1
RET " Return IrDm CALL
"m
lOOPIILOOPE loopwhllezerOlequal
LOOPNZlLOOPNE Loop "'hlle not
zero/eQua'
JCXZ Jump on CX zero
dlsphlgh
7 8 5" 3 2 1;0
01110011
~~
11 1 1 1001
11111100
0 1
1'1110100
e~ternal
devlcel
i
I
li2JLiJiiiJ
L'~~d~-x~~/ffi]
U"""111oooO"l
Fatlnolll:
Al '" 8-bIt accumulator
AX '" 160M accumulator
CX '" Count register
OS ~ Data segment
ES '" Extra segment
Above/below refers to unsIgned value
Greater'" more POSItive,
less", less POSitive (more negative) Signed values
Ifd'" 1 then "to" reg,lfd =Othen"'from" reg
If w" 1 then word Instrl,lctlOn, If w '" 0 then byte mstructlon
If
If
If
11
mod",
mod'"
mod",
mod ~
If s w = 01 then 16 bits of Immediate data form the operand
If s w = 11 then an Immediate data byte IS sign ext~nded to
form the 16-bIt operand
II v -= 0 then "count" = 1. If v = 1 then -'count" 10 (el)
x = don't care
Z IS used for strtng prtmltlVes lor comparison With Z.F FLAG
SEGMENT OVERRIOE PREFIX
10 0 1 reg 1 I 01
REG
11 then rIm IS treated as a REG field
00 then DISP '" 0·, dlsp·low and dlsp-hlgh are absent
II rim ~ IJOO then EA ~ (BX) • (SI) • DlSP
II rim ~ 001 then EA ~ (BX) • (01) • OISP
11 rim ~ 010 then EA ~ (BP) • (SI) • OISP
.1 rim ~ 011 then EA ~ (BP) • (01) • OISP
II rim ~ 100 then EA ~ (SI) .0tSP
il rim ~ 101 then EA ~ (01) .OISP
11 rim ~ 110 then EA ~ (BP) • OISp·
11 rim ~ 111 then EA ~ (BX) • OISP
DISP follows 2nd byte of tnstruchon (before data If reqUIred)
°exceptl1 mod
~
00 and r 1m
~
110 then EA
~
dlSp-hlgh dlSp-low
IS
assIgned accordtng to the follOWing table
t""I· .2!
000 AX
001 CX
010 OX
011 BX
100 SP
101 BP
110 SI
111 01
01 then DISP '" dlsp-Iow slgn·extended to 16-blts, dlsp·hlgh IS absent
10 then OISP ~ dlSp-hlgh dlSp-low
Balli.· 0)
000
001
010
011
100
101
110
111
AL
CL
DL
BL
AH
CH
DH
BH
Segment
00 ES
01 CS
10 SS
lIDS
InstructIOns which reference the flag register file as a 16-blt object use the symbol FLAGS to
represent the file
FLAGS· X X X X (OF) (OF) (IF) (TF) (SF) (IF! X (AF) X (PF) X (CF)
Mnemonics© Intel, 1978
3-438
AFN·00826D
inter
iAPX 188
HIGH INTEGRATION 8-BIT MICROPROCESSOR
• Integrated Feature Set
-Enhanced 8088-2 CPU
-Clock Generator
-2 Independent, High-Speed DMA
. Channels
-Programl'flable Interrupt Controller
-3 Programmable 16-blt Timers
-Programmable Memory and
Peripheral Chip-Select Logic
-Programmable Wait State Genera~or
-Local Bus Controller
• 8-Bit Data BusJnterface; 16-bit internal
architecture
• Atailabla in 8MHz (80186) and cost
effective 6 MHz (80186-6) versions
• High-Performance 8 MHz Processor
-2 Times the Performance of the
Standard iAPX 88
- 2 MByte/Sec Bus Bandwidth
Interface
• Completely Object Code Compatible
with All Existing iAPX 86, 88 Software
-10 New Instruction Types
• Direct Addressing Capability to
1 MByte of Memory
• Complete System Development
Support
-Development Software: Assembler,
PL/M, Pascal, Fortran, and System
Utilities
-In-Circuit-Emulator (ICE™ -188)
-IRMXTM 86, 88 Compatible (80130
OSF)
• High Performance Numerical
Coprocessing Capability Through 8087
Interface
INT311NTA1
rD~LKOUT
TT
1I
X,
INT2IINTAO
'ExECUTION
!
uNiTJ
X,
TMRIN
1
INITO
Nr '
--.
1
ALU
CLOCK
GENERATOR
GENERAL
PURPOSE
REGISTERS
I)'
11
J
I
CONTROL
REGISTERSi
.J
t
REGISTERB :--
MAX COUNT
REGISTER A
CONTROL REGISTERS
I
16·BIT
COUNT REGISTER
{
(r
INTERNAL BUS
'u
;=~
Tm
HOLD.-j-oo
HLDA
ARI~f.
RESETr_
1
1.1
DEN
LOCK
DTII!
67
...BYTE
PAEFETCH
PROGRAMMABLE
CONTROL
QUEUE
REGISTERS
AD17
r±t
I
'II
SOURCE POINTERS
2O-BIT
DESTINATION
POINTERS
16·81T
TRANSFER COUNT
CONTROL
REGISTERS
PCS6/A2
1-
PCS5iAl
LCS
.AS A15
~
11
*
UCS
A1B/Si
DR01
2O-BI1
16-BIT
SEGMENT
REGISTERS
111H~
DROO
PROGRAMMABLE
DMAUNIT
0
1
UNIT
BUS INTERFACE
UNIT
.--1-
!
U
CHIP-SELECT
SRDYr-j-oo
ARDY
i
MAXCOUNT~
INTERRUPT
CONTROLLER
I
I
16·BIT,
1
TIMERS
2
0
1
PROGRAMMABLE
I
I
TMRIN
PROGRAMMABLE
,
I
16~Brr
I
TMR OUT 1 TMR OUT 0
INn
'II
Figure 1. iAPX 188 Block Diagram
Intel Corporation Assumes No ResponSibility for the use of Any CirCUItry Other Than CirCUitry Embodied In an Intel Product No Other CrrcUit Patent licenses are miphecl
©INTEL COR~ORATION, 1982
OCTOBER 1982
ORDER NUMBER, 210706-001
3-439
\ V
iAPX 188
The Intel iAPX 188 (80188 part number) is a highly integrated microprocessor with an 8-bit data bus interface and a
16-bit internal architecture to give high performance. The iAPX 188 effectively combines 15-20 of the most common
iAPX 88 system components onto one. The 80188 provides two times greater throughput than the standard 5 MHz
IAPX 88. The iAPX 188 is upward compatible with iAPX 86 and 88 software and adds 10 new instruction types to the
existing set.
BOTTOM
TOP
~m52~lJUIUlJUULJUU
S1
52
ARDY
CLKOUT
RESET
X2
Xl
vss
ALEIOSO
RD/OSMD
WR/OSl
S7
A19/S6
Al81S5
A17/S4
TMR IN 1
TMRINO
DROl
... DROO
Al61S3
/'
"
PIN NO.1 MARK .............
Figure 2. 80188 Pinout Diagram
Table 1. 80186 Pin Description
Symbol
Pin No.
~
Vcc,Vcc
9,43
I
System Power:
Vss, Vss
26,60
I
System Ground.
RESET
57
0
Reset Output indicates that the 80186 CPU is being reset, and can be used as a system
reset. It is active HIGH, synchronized with the processor clock, and lasts an integer
number of clock periods corresponding to the length of the RES signal.
X1, X2
59,58
I
Crystal Inputs, X1 and X2, provide an external connection for a fundamental mode
parallel resonant crystal for the internal crystal oscillator. XI can Interface to an
external clock instead of a crystal. In this case, minimize the capacitance on X2 or
drive X2 with complemented XI. The input or oscillator frequency is internally divided
by two to generate the clock signal (CLKOUT).
CLKOUT
56
0
Clock Output provides the system with a 50% duty cycle waveform. All device pin
timings are specified relative to CLKOUT. CLKOUT has sufficient MaS drive capabilities
for the 8087 NumeriC Processor Extension.
RES
24
I
System Reset causes the 80186 to immediately terminate its present activity, clear the
internal logic, and enter a dormant state. This Signal may be asynchronous to the
80186 clock. The 80186 begins fetching instructions approximately 7 clock cycles
after RES is returned HIGH. RES is required to be LOW for greater than 4 clock
cycles and is internally synchronized. For proper initialization, the LOW-Io-HIGH transition of RES must occur no sooner than 50 microseconds after power up. This input
is provided with a Schmitt-trigger to facilitate power-on RES generation via an RC
network. When RES occurs, the 80188 will drive the status lines to an inactive level
for one clock, and then Iri-state them.
Name and Function
+ 5 volt power supply.
3-440
AFN-01483A
iAPX 188
Table 1. 80188 Pin Description (Continued)
Pin
No.
Type
fESi'
47
I
fESi'
TMR IN 0,
TMR IN1
20
21
I
I
Timer Inputs are used either as clock or control signals, depending upon the
programmed timer mode. These Inputs are active HIGH (or LOW-to-HIGH
transitions are counted) and Internally synchrOnized.
TMR OUT 0,
TMR OUT 1
22
23
0
0
Timer outputs are used to provide single pulse or continuous waveforrh generatlon, depending upon the timer mode selected.
DRaO
DRa1
18
19
I
I
DMA Request IS driven HIGH by an external device when It desires that a
DMA channel (Channel 0 or 1) perform a transfer. These signals are active
HIGH, level-triggered, and internally synchrOnized.
NMI
46
I
Non-Maskable Interrupt IS an edge-triggered input which causes a type 2
Interrupt. NMI is not maskable internally. A transition from a LOW to HIGH
initiates the interrupt at the next instruction boundary. NMI is latched Internally. An NMI duration of one clock or more Will guarantee service. This input is
Internally synchronized.
INTO,INT1,
INT2/INTAO
INT3/INTA1
45,44
42
41
I
I/O
I/O
Maskable Interrupt Requests can be requested by strobing one of these pins.
When configured as Inputs, these PinS are active HIGH. Interrupt Requests are
synchronized internally. INT2 and INT3 may be configured via software to
provld'e active-LOW interrupt-acknowledge output Signals. All interrupt inputs
may be configured via software to be either edge- or level-triggered. To ensure
recognition, all Interrupt requests must remain active until the interrupt is
acknowleged. When iRMX mode IS selected, the function of these pins
changes (see Interrupt Controll,er section of thiS data sheet).
A19/56,
A18/55,
A,17/54,
A16/53
65-68
0
0
0
0
Address Bus Outputs (16-19) and Bus Cycle Status (3-6) reflect the four most'
Significant address bits during T1. These signals are active HIGH. During T2,
T3, Tw, and T4, status Information is available on these lines as encoded
below:
Symbol
Name and Function
IS examined by the WAIT Instruction. If the TEST Input IS HIGH when
"WAIT" execution begins, instruction ex~cution will suspend TEST will be
resampled until It goes LOW, at which time execution will resume. If Interrupts
are enabled while the 80188 is waiting for TEST, interrupts will b,e serviced. This
Input is synchronized internally.
I
Low
I
56
Processor Cycle
53,54, and 55 are defined as LOW during T2-T4
High
I
DMA Cycle
I
AD7-ADO
2,4,6,8,
11,13,15,17
I/O
Address/Data Bus (0-7) signals constitute the time mutiplexed memory or I/O
address (T1) and data (T2' T3, Tw, and T4) bus. The bus IS active HIGH.
A15-AB
1,3,5,7
10,12,14,16
0
Address-only Bus (8-15), containing valid address from T1-T4. The bus is active
HIGH.
64
0
This signal is always HIGH to indicate that the 80188 has an 8-bit data bus, and is
tri-state OFF during bus HOLD.
57
3-441
,AFN'()1483A
"""'_1'
II'I"e'i
IAPX 1"88
Table 1. 80188 Pin Description (Continued)
Pin
No.
Type
Name and Function
ALE/QSO
61
0
Address Latch Enable/Queue Status 0 is provided by the 80188 to latch the
address into the 828218283 address latches. ALE is active HIGH. Addresses are
guaranteed to be valid on the trailing edge of ALE. The ALE rising' edge is
generated off the rising edge of the CLKOUT immediately preceding T1 of the
associated bus cycle, effectively one-half clock cycle earlier than in the standard 80188 The trailing edge is generated off the CLKOUT rising edge in T1 as'
in the 80188 Note that ALE is never floated.
WR/QSl
63
0
Write Strobe/Queue Status 1 indicates that the data on the bus is to be written
into a memory or an I/O device. WR is active for T2. Ta. and Tw 9f any write
cycle. It is active LOW. and floats during "HOLD." It is driven HIGH for one clock
during Reset. and then floated. When the 80188 is in queue status mode, the
ALE/QSO and WR/QSl pins provide information about processor/instruction
queue interaction.
Symbol
QSl
QSO
0
0
0
1
1
1
1
0
Queue Operation
No queue operation
First opcode byte fetched from the queue
Subsequent byte fetched from the queue
Empty the queue
0
Read Strobe indicates that the 80188 is performing a memory or I/O read cycle.
Frn is active LOWforT2, Ta. and Tw of any read cycle. It is guaranteed notto go
LOW in T2 until after ttle Address Bus is floated. RD is active LOW. and floats
during "HOLD." RD is driven hliGH for one clock during Reset. and then the
output driver is floated. Aweak internal pull-up mechanism on the RD line hols
it HIGH when the line is not driven. During RESET the pin Is sampled to
determine whether the 80188 should provide ALE. WR. and Frn. or if the
Queue-Status should be provided. RD should be connected to GND to provide
Queue-Status data.
I
Asynchronous Ready informs the 80188 that the addressed memory space or
I/O device will complete a data transfer. The ARDY input pin will accept an
asynchronous input. and is active HIGH. Only the riSing edge is internally
synchronized by the 80188. This means that the falling edge of ARDY must be
synchronized to the 80188 cloCk. If connected to Vee. no WAIT states are
inserted. Asynchronous ready (ARDY) or synchronous ready (SRDY) must be
active to terminate a bus cycle. If unused. this line sholtld be tied low.
49
I
Synchronous Ready must be synchronized externally to the 80188. The use of
SRDY provides a relaxed system-timing specification on the Ready input. This is
accomplished by eliminating the one-half clock cycle which is required for internally
resolving the signal level when using the ARDY Input. This line is active HIGH. If thiS
line is connected to Vee. no WAIT states are inserted. Asynchronous ready (ARDY)
or synchronous ready (SRDY) must be active before a bus cycle is terminated. If
unused. this line should be tied low.
48
0
LOCK output indicates that other system bus masters are not to gain control of the
system bus while LOCK is active LOW. The LOCK signal is requested by the LOCK
prefix instruction and is activated at the beginning of the first data cycle associated
with the instruction following the LOCK prefix. It remains active until the,completion
ofthe instruetion following the LOCK prefix. No prefetches will occur while LOCK is
asserted. LOCK is' active LOW. is driven HIGH for one clock during RESET. and
then floated. If unused. this line should be tied low.
RD/QSMD
62
ARDY
55
SROY
LOCK
I
3-442
AfN~1483A
intJ
IAPX 188
Table 1. 80188 Pin Description (Continued)
Symbol
SO,81,S2
Pin
No.
Type
Name and Function
52-54
0
Bus cycle status SO-52 are ,encoded to provide bus-transaction information:
80188 Bus Cycle Status Information
'.
52
51
SO
Bus Cycle Initiated
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt Acknowledge
Read I/O
~rite I/O
alt
Instruction Fetch
Read Data from Memory
Write Data to Memory
Passive (no bus cycle)
The status pins float during "HOLD."
S2 may be used as a logical MilO indicator, and 51 as a DTIFi indicator.
The Status lines are driven HIGH for one clock during Reset, and then floated
until a bus cycle begins.
HOLD (input)
HLDA (output)
50
51
0
UCS
34
0
Upper Memory Chip Select is an active LOW output whenever a memory
reference is made to the defined upper portion (1K-256K block) of memory.
This line is not floated during bus HOLD. The address range activating OCS is
software programmable.
LCS
33
0
Lower Memory' Chip Select is active LOW wheneve'r a memory· reference is
made to the defined lower portion (1K-256K) of memory. This line is not
floated during bus HOLD. The address range activating LCS is software
programmable.
~-3
38,37,36,35
0
Mid-Range Memory Chip Select signals are active LOW when a memory
reference is made to the defined mid-range portion of memory (8K-512K).
These lines are not floated during bus HOLD. The address ranges activating
MCSO-3 are software programmable.
PCSO-4
25,27-30
0
Peripheral Chip Select signals 0-4 are active LOW when a reference is made to
the defined peripheral area (64K byte I/O space). These lines are not floated
during bus HOLD. The address ranges activating PCSO-4 are software
programmable.
PCS5/A1
31
0
Peripheral Chip Select 5 or Latched A1 may be programmed to provide a sixth
peripher.al chip select, or to provide an internally latched A1 signal. The
address range activating J5CS5 is software programmable. When programmed
to provide latched A1, rather than PCS5, this pin will retain the previously
latched value of A1 during a bus HOLD. A1 is active HIGH.
PCS61A2
32
0"
Peripheral Chip Select 6 or Latched A2 may be programmed to provide a
seventh peripheral chip select, or to provide an internally latched A2 signal.
The address range activating PCS6 is softwa!!...E!0grammable. When programmed to provide latched A2, rather than PCS6, this pin will retain the
previously latched value of A2 during a bus HOLD. A2 is active HIGH.
DT/R
40
0
Data Transmit/Receive controls the dirl!ction of data flow through the external
8286/8287 data bus transceiver. When LOW, data is transferred to the 80188.
When HIGH the 80188 places write data on the data bus.
DEN
39
0
I
HOLD indicates that another bus master is requesting the local bus. The HOLD
input is active HIGH. HOLD may be asynchronous with respect to the 80188
clock. The 80188 will issue a HLDA in response to a' HOLD request at the end of
T4 or TI. Simultaneous with the issuance of HLDA, the 80188 will float the local
bus and control lines. After HOLD is detected as being LOW, the llO188 will
lower HLDA. When the 80188 needs to run another bus cycle, it will again drive
the local bus and control lines.
Data Enable is provided as an 8286/8287 data bus transceiver output enable.
i5Eiii is active LOW during each memory and I/O access. i5Eiii h~ HIGH whenever
DTlR changes state.
3-443
'
AFN'()l483A
iAPX 188
FUNCTIONAL DESCRIPTION
Introduction
The following Functional Description describes the
base architecture of the iAPX 188. This architecture is
common to the iAPX 86, 88, and 286 microprocessor
families as well. The iAPX 186 is a very high integration
8-bit microprocessor. 'It combines 15-20 of the most
common microprocessor systel)1 components onto one
chip while providing twice tl1e performance of the
standard iAPX 88. The 80188 is object code compatible
with the iAPX 86, 88 microprocessors and adds 10 new
instruction types to the existing iAPX 86, 88 instruction
set.
iAPX 188 BASE ARCHITECTURE
The iAPX 86, 88, 186, 188, and 286 family all contain the
same basic set of registers, instructions and addressing
modes. The 80188 processor is upward compatible
with the 8086,.8088, 80186, and 80286 CPUs.
Segment Registers
Four 16-bit special purpose registers select, at any
given time, 'the segments of memory that are immediately addressable for, code, stack, and data. (For
usage, refer to Memory Organization.)
Base and Index Registers
Four of the general purpose registers may also be
used to determine offset addresses of operands in
memory. These registers m~y contain base addresses or indexes to particular locations within a
segment. The addressing mode selects the specific
registers for operand and address calculations.
Status and Control Registers
Two 16-bit special purpose registers record or alter
certain aspects of the 80188 processor state. These
are the Instruction Pointer Register, which contains
the offset address of the next sequential instruction
to be executed, and the Status Word Register, which
contains status and control flag bits (see Figures 3a
and 3b).
Register Set
The 80188 base architecture has fourteen registers
as shown in Figures 3a and 3b. These registers are
grouped into the following categories.
General Registers
Eight 16-bit general purpose registers used to contain arithmetic and logical operands. Four of these
(AX, ex, CX, and OX) can be used as 16-bit registers
or split into pairs of separate 8-bit registers.
BYTe
18·BIT
REGISTER
NAMES
SHOWN)
REGISTER
REGISTER
NAME
FUNCTIONS
I
The Status Word records specific characteristics of
the result of logical and arithmetic instructions (bits
0, 2, 4, 6, 7, and 11) and controls the operation of the
80188 within a given operating mode (bits 8, 9, and
10). The Status Word Register is 16-bits wide. The
function of the Status Word bits is shown in Table 2.
SPECIAL
16·BIT
ADDRESSABLE
Status Word Description
7
15
0
AX
AH
AL
OX
DH
DL
CX
CH
CL
BX
BH
BL
1
}
0
~ CODe SEGMENT SELECTOR
MULTIPLY/DIVIDE
1/0 INSTRUCTIONS
CS
OS
DATA SEGMENT SELECTOR
LOOPISHIFTIREPEAT/COUNT
SS .
STACK SEGMENT SELECTOR
ES
EXTRA SEGMENT SELECTOR
BASE REGISTERS
BP
SEGMENT REGISTERS
SI
}
F
)
SP
IP
STACK POINTER
o
15
I
15
INDEX REGISTERS
01
I
0
1-------1
STATUS WORD
INSTRUCTION POINTER
STATUS AND CONTROL
REGISTERS
GENERAL
REGISTERS
Figure
3a. 80188 General Purpose Register Set
3-444
AFN-01483A
IAPX 188
STATUS FLAGS
CARRY - - - - - - - - - - - - - - - - - - - - - - - - ,
PARITY
-------------~----__,
AUXILIARY CARRY - - - - - - - - - - - - - - - - - ,
ZERO - - - - - - - - - - - . - ,
SIGN - - - - - - - - - - - ,
CONTROL FLAGS
' - - - - - - - TRAP FLAG
' - - - - - - - - - INTERRUPT ENABLE
' - -_ _ _ _ _ _ _ _ _ OIRECTION FLAG
~
INTEL RESERVED
Figure 3b. Status Word Format
Table 2. Status Wo~d Bit Functions
Bit
Position
Name
Function
0
CF
Carry Flag-Set on high-order bit
carry or borrow; cleared otherwise
2
PF
Panty Flag-Set If low-order 8 bits
of result contain an even number of
1-blts; cleared otherwise
4
AF
Set on carry from or borrow to the
low order four bits of AL; cleared
otherwise
6
ZF
Zero Flag-Set If result IS zero,
cleared otherwise
7
SF
Sign Flag-Set equal to high-order
bit of result (0 If positive, 1 If negallVe)
8
TF
Single Step Flag-Once set, a single step interrupt occurs after the
next Instruction executes. TF is
cleared by the single step Interrupt
9
IF
Interrupt-enable Flag-When set,
maskable Interrupts will cause the
CPU to transfer control to an Intetrupt vector specified location.
10
OF
Direction Flag-Causes string
instructions to auto decrement
the appropriate index register
when set. Clearing OF causes
auto increment.
OF
Overflow Flag-Set if the signed
result cannot be expressed
within the number of bits in the
destination operand; cleared
otherwise
11
Instruction Set
The instruction set is divided into seven categories;
data transfer, arithmetic, shift/rotate/logical, string.
manipulation, control transfer, high-level instructions, and processor control. These categories are
summarized in Figure 4.
An 80188 instruction can reference anywhere from
zero to several operands. An operand can reside in a
register, in the instruction itself, or in memory. Specific operand addressing modes are discussed later
in this data sheet.
Memory Organization
Memory is organized in sets of segments. Each segment is a linear contiguous sequence of up to 64K
(216 ) 8-bit bytes. Memory is addressed using a twocomponent address (a pointer) that consists of a
16-bit base segment and a 16-bit offset. The 16-bit
base values are contained in one of four internal
segment registers (code, data, stack, extra). The
phYSical address is calculated by shifting the base
value LEFT by four bits and adding the 16-bit offset
value to yield a 20-bit physical address (see Figure 5).
This allows for a 1 MByte physical address size.
All instructions that address operands in memory
must specify the base segment and the 16-bit offset
value. For speed and compact instruction encoding,
the segment register used for physical address generation is implied by the addressing mode used (see
Table 3). These ruies follow the way programs are
written (see Figure 6) as independent modules that
require areas for code and data, a stack, and access
to external data areas.
Special segment override instruction prefixes allow
the implicit segment register selection rules to be
overridden for special cases. The stack, data, and
extra segments may coincide for simple programs.
3-445
AFN-01483A
iAPX' 188
GENERAL PURPOSE
,
MOVS
Move byte or word string
MOV
Move byte or word
INS
Input bytes or word string
PUSH
Push word onto stack
OUTS
Output bytes or word string
POP
Pop word off stack
CMPS
Compare byte or word string
PUSHA
Push all registers on stack
SCAS
Scan byte or word string
paPA
Pop all registers from stack
LaDS
Load byte or word string
XCHG
Exchange byte or word
STOS
' Store byte or word stnng
XLAT
Translate byte
REP
INPUT/OUTPUT
IN
Input byte or word
OUT
Output byte or word
Load effective address
LDS
Load pointer using DS
LES
Load pOinter using ES
FLAG TRANSFER
LAHF
Load AH register from flags
SAHF
Store AH register in flags
PUSHF
Push flags ont6 stack
POPF
Pop flags off stack
Repeat while equal/zero
REPNE/REPNZ
Repeat while not equal/not zero
LOGICALS
ADDRESS OBJECT
LEA
Repeat
REPE/REPZ
,NOT
"Not" byte or word
AND
"And" byte or word
OR
"Inclusive or" byte or word
XOR
"Exclusive or" byte or word
TEST
"Test" byte or word
SHUSAL
Shift logical/arithmetic left byte or word
SHR
Shift logical right byte or word
SAR
Shift arithmetic right byte or word
ROL
Rotate left byte or word
SHIFTS
ROTATES
ADDITION
ADD
Add byte or word
ROR
Rotate right byte or word
ADC
Add byte or word with carry
RCL
Rotate through carry left byte or word
INC
Increment byte or word by 1
RCR
Rotate through carry right byte or word
AAA
ASCII adjust for addition
DAA
DeCimal adjust for addition
FLAG OPERATIONS
SUBTRACTION
STC
Set carry flag
SUB
Subtract byte or word
CLC
Clear cany flag
SBB
Subtract byte or word with borrow
CMC
Complement carry flag
DEC
Decrement byte or word by 1
STD
Set direction flag
NEG
Negate byte or word
CLD
Clear direction flag
c:;MP
Compare byte or word
STI
Set interrupt enable flag
AAS
ASCII adlustfor subtraction
CLI
Clear interrupt enable flag
DAS
DeCimal adjust for subtraction
EXTERNAL SYNCHRONIZATION
HLT
Halt untit Interrupt Or reset
Multlplybyte or word unsigned
WAIT
Wait for TEST pin active
IMUL
Integer multiply byte or word
ESC
Escape to extension processor
AAM
ASCII adjust for multiply
LOCK
Lock bus during next Instruction
Nap
No operation
MULTIPLICATION
MUL
NO OPERATION
DIVISION
DIV
Divide byte or word unsigned
HIGH LEVEL INSTRUCTIONS
IDIV
Integer divide byte or word
AAD
ASCII adjust for division
ENTER
Format stack for procedure entry
CBW
Convert byte to word
LEAVE
Restore stack for procedure eXit
CWD
Convert word to doubleword
BOUND
Detects values outside prescribed range
Figure 4. iAPX 188 Instruction Set
3-446
AFN-01483A
iAPX 188
CONDITIONAL TRANSFERS
UNCONDITIONAL TRANSFERS
JAlJNBE
Jump If abovelnot below nor equal
CALL
JAE/JNB
Jump If above or equal/not below
RET
Return from procedure
JB/JNAE
Jump if below/not above nor equal
JMP
Jump
JBE/JNA
Jump If below or equal/not above
Call procedure
ITERATION CONTROLS
JC
Jump if carry
JE/JZ
Jump if equal/zero
JG/JNLE
Jump if greater/not less nor equal
LOOP
Loop
JGE/JNL
Jump If greater or equal/not less
LOOPE/LOOPZ
Loop If equal/zero
JUJNGE
Jump if less/not greater nor equal
LOOPNE/LOOPNZ
Loop If not equal/not zero
JLE/JNG
Jump if less or equal/not greater
JCXZ
Jump If register CX = 0
JNC
Jump If not carry
JNE/JNZ
Jump If not equal/not zero
JNO
Jump If not overflow
INTERRUPTS
JNP/JPO
Jump If not parity/panty odd
INT
Interrupt
JNS
Jump If not sign
INTO
Interrupt if overflow
JO
Jump If overflow
IRET
Interrupt return ,
JP/JPE
Jump If panty/panty even
JS
Jump If sign
Figure 4. iAPX 188 Instruction Set (continued)
To access operands that do nOt reside in one of the
four immediately available segments, a full 32-bit
pointer can be used to reload both the base (segment) and offset values.
r - - -,
I
§
I
ODE
MODULE A
DATA
lH'FTLEFT4BITSI
I1
2
3
19
4
: 0
I
1
2
to.
11 2
I~~~~ENT}
0
0
0
[~[I~o~O~2:!2jl .•.__~1~5::J
15
3 4
15
";'1- - - - i
2
2.
LOGICAL
ADDRESS
CPU
IOFFSET
MODULE B
0
f-------t----,
CODE
0
3
6
2
I
DATA
PHVSICAL ADDRESS
o
19
STACK
TO MEMORY
PROCESS
EXTRA
STACK
SEGMENT
Figure 5. Two Component Address
REGISTERS
Table 3. Segment Register Selection Rules
Memory
Reference
Needed
Instructions
Stack
External
Data
(Global)
Local Data
Segment
Register
Used
PROCESS
DATA
Implicit Segment
Selection Rule
BLOCK 1
Code (CS)
Instruction prefetch and
immediate data.
Stack (SS) All stack pushes and
pops; any memory references which use BP Register as a base register.
Extra (ES) All string instruction
references which use
the 01 register as an
index.
Data (OS) All other data references.
PROCESSD
DATA
BLOCK 2
I
I
l ___ J
MEMORY
Figure 6. Segmented Memory Helps
Structure Software
3-447
AFN-01483A
IAPX 188
Addressing Modes
Data Types
The 80188 provides eight categories of addressing
modes to specify operands. Two addressing modes
are provided for instructions that operate on register
or immediate operands:
.
The 80188 directly supports the following data types:
• Integer: A signed binary numeric value contained
in an 8-bit byte or a 16-bit word. All operations
assume a 2's complement reptesentation. Signed
• Register Operand Mode: The operand is located in
one of the 8- or 16-bit general registers.
32- and 64-bit integers are supported using the
iAPX 188/20 Numeric Data Processor.
• Immediate Operand Mode: The operand is included in the instruction.
• Ordinal: An· unsigned binary numeric value contained in an 8-bit byte or a 16-bit word.
• Pointer: A 16- or 32-bit quantity, composed of a
16-bit offset component or a 16-bit segment base
component in addition to a 16-bit offset
component.
Six modes are provided to specify the location of an
operand in a memory segment. A memory operand
address consists of two 16-bit components: a segment base and an offset. The segment base is supplied by a 16-bit segment register either implicity
chosen by the addressIng mode or explicitly chosen
by a segment override prefix. The offset, also called
the effective address, is calculated by summing any
combination of the following three address
elements:
• the displacement (an 8- or 16-bit immediate value
contained in the instruction);
• the base (contents of either the BX or BP base
registers); and
• the index (contents of either the 51 or 01 index
registers).
Any carry out from the 16-bit addition is ignored.
Eight-bit displacements are sign extended to 16-bit
values.
Combinations of these three address elements
define the six memory addressing modes, described
below.
• Direct Mode: The operand's offset is contained in
· the instruction as an 8- or 16-bit displacement
element.
• Register Indirect Mode: The operand's offset is in
one of the registers 51, 01, BX, or BP.
• Based Mode: The operand's offset is the sum of an
8- or 16-bit displacement and the contents of a
base register (BX or BP).
• Indexed Mode: The operand's offset is the sum of
an 8- or 16-bit displacement and the contents of an
index register (51 or 01).
• Based Indexed Mode: The operand's offset is the
sum of the contents of a base register and an index
register.
• Based Indexed Mode with Displacement: The
operand's offset is the sum of a base register's
contents, an index register's contents, and an 8- or
16-bit displacement.
• String: A contiguous sequence of bytes or words.
A string may contain from 1 to 64K bytes.
• ASCII: A byte representation of alphanumeric and
control characters using the ASCII standard of
character representation.
• BCD: A byte (unpacked) representation of the decimal digits 0-9.
• Packed BCD: A byte (packed) representation of
two decimal digits (0-9). One digit is stored in each
nibble (4-bits) of the byte.
• Floating Point: A signed 32-, 64-, or 80-bit real
number representation. (Floating point operands
are supported using the iAPX 188/20 Numeric Data
Processor configuration.)
In general, individual data elements must fit within
defined segment limits. Figure 7 graphically
represents the data types supported by the iAPX 188.
I/O Space
The I/O space consists of 64K 8-bit or 32K 16-bit
ports. Separate instructions address the I/O space
with either an 8-bit port address, specified in the
instruction, or a 16-bit port address in the OX register. 8-bit port addresses are zero extended such that
A1s-Aa are LOW I/O port addresses OOF8(H) through
OOFF(H) are reserved.
Interrupts
An interrupt transfers execution to a new program
location. The old program address (CS:IP) and machine state (Status Word) are saved on the stack to
allow resumption of the interrupted program. Inter,
rupts fall into three classes: hardware initiated, INT.
instructions, and instruction exceptions. Hardware'
initiated interrupts occur in response to an external
input and are classified as non-maskable or
maskable.
3-448
IAPX 188
7
Programs may cause an interrupt with an INT instruction. Instruction exceptions occur when an unusual condition, which prevents further instruction
processing, is detected while attempting to execute
an instruction. If the exception was caused by executing an ESC instruction with the ESC trap bit set
in the relocation register, the return instruction will
point to the ESC instruction, or to the segment override prefix immediately preceding the ESC instruction if the prefix was present. In all other cases, the
return address from an exception will point at the
instruction immediately following the instruction
causing the exception.
0
rrrrrrrrI
L.L.....!--I
SIGNED
BYTE
SIGN SIT J L..-.--..J
MAGNITUDE
7
0
('TTT1'TTT1
UNSIGNED
SVTE
L-:...-...J
~
MAGNITUDE
e1
1!:11. +1
0
II iii iii Iii iii iii
S~~:g
SIGN SIT J 1....L.;:M"iiS:r.AG"'N:;;;,TMoUn.DE;---'
SIGHED 31
+3
+2
1615
+1
A table containing up to 256 pointers defines the
proper interrupt service routine for each interrupt.
Interrupts 0-31, some of which are used for instruction exceptions, are reserved. Table 4 shows the
80188 predefined types and default priority levels.
For each interrupt, an 8-bit vector must be supplied
to the 80188 which identifies the appropriate table
entry. Exceptions supply the interrupt vector internally. In addition, internal peripherals and noncascaded external interrupts will generate their own
vectors through the internal interrupt controller. INT
instructions contain or imply the vector and allow
access to all 256 interrupts. Maskable hardware initiated interrupts supply the 8-bit vector to the CPU
during an interrupt acknowledge bus sequence.
Non-maskable hardware interrupts use a predefined
internally supplied vector.
0
II iii iii Iii II iii Iii 'I iii Iii iii iii
~~:~~
-=-==.-___--'
SIGN SITJ I..IL...;;M"'S"-S_ _
MAGNITUD~
.
+7
+6
SIGNED 63
+5
+4
48 47
w~~~11
+3
+2
3231
+1
Hi 1!)
J
I I
0
I
I
SIGN SIT J,L..'-.;:M""SS"----:M"AG';;'NW,TOOU;;;D.-E_ _ _ _- '
15
+1
0
Ii, iii iii iii Iii r I
UNS:~~g
,Lyse
MAGNITUDE
BINARY 7
+N
7
0
+1
DI~~~ N
(SCD)
7
+N
SCD
DIGIT 1
0
7
0
7
J'TTTTTTTl
PACKED
SCD
+1
SCD
DIGIT 0
07
ASCII
CHARACTER,
ASCII
CHARACTERN
+N
0
0
liil/iiill"I"r I
ASCII~
7
07
1"'111111111"11
rrrrTT"l
L-:...-...J
CODED
DECIMAL
+1
l-l
+N
LEAST
0
SVTEWORDN
POINTER
715
79+9
+1
0715
0
0
l'''liiiriiliii I
SVTE WORD 1 SVTE WORD 0
+3
Iii iii iii
The 80188 can service interrupts generated by software or hardware. The software interrupts are
generated by specific instructions (INT, ESC, unused
Op, etc.) or the results of conditions spepified by
instructions (array bounds check, INTO, Ol\/, 101\/,
etc.). All interrupt sources are serviced by an indirect
call through an element of a vector table. This vector
table is indexed by using the interrupt vector type
(Table 4), multiplied by four. All hardwar~generated
interrupts are sampled at the end of each instruction.
Thus, the software interrupts will begin 'service first.
Ol'1ce the service routine is entered and Jnterrupts
are enabled, any hardware source of sufficient
priority can interrupt the service routine in progress.
SIGNIFICANT DIGIT
c::!::J ...
31
0
l-l
MOST
SIGNIFICANT DIGIT
715
0
liiilii"lii'I"'1
'----L.....J
STR~NG
Interrupt Sources
ASCII
CHARACTERo
07
+2
iii
SELECTOR
+8
+7
EXPONENT
1615
+1
0
Iii iii i 'I i,1 iii i i i i i i I
+6
+5
OFFSET
+4
+3
+2
+1
MAGNITUDE
NOTE:
The software generated 80188 interrupts are described
below.
'SUPPORTED BY IAPX 188/20 NUMERIC DATA PROCESSOR
CONFIGURATION
DIVIDE ERROR EXCEPTION (TYPE 0) ,
Generated when a OIV or JDIV instruction quotient
cannot be expressed in the number of bits in the
destination.
Figure 7. IAPX 188 Supported Data Types
3-449
AFN-sception. The,
saved Status Word will reflect the enable status of the
processor prior to the interrupt. The interrupt flag
will remain zero unless specifically set. The interrupt
return instruction restores the Status Word, thereby
restoring the original status of IF bit. If the interrupt
return re-enables interrupts, and another interrupt is
pending, the 80188 will immediately service the
highest-priority interrupt pending, i.e., no instructions of the main line program will be executed.
NOh-Maskable Interrupt Request (NMI)
A non-maskable interrupt (NMI) is also provided.
This interrupt is serviced regardless of the state of
the IF bit. A typical use of NMI would be to activate a
power failure routine. The activation of this input
3450
AFN-01483A
iAPX 188
causes an interrupt with an internally supplied vector
value of 2. No external interrupt acknowledge sequence is performed. The IF bit is cleared at the
beginning of an NMI interrupt to prevent maskable
interrupts from being serviced.
Single-Step Interrupt
The 80188 has an internal interrupt that allows programs to execute one instruction at a time. It is called
the single-step interrupt and is controlled by the
single-step flag bit (TF) in the Status Word. Once this
bit is set, an internal single-step interrupt will occur
after the next instruction has been executed. The
interrupt clears the TF bit and uses an internally
supplied vector of 1. The IRET instruction is used to
set the TF bit and transfer control to the next instruction to be single-stepped.
Initialization and Processor Reset
Processor initialization or startup is accomplished by
driving the RES input pin LOW. RES forces the 80188 to
terminate all execution and local bus activity. No
instructionor bus activity will occur as long as RES is
active. After RES becomes inactive and an internal processing interval elapses, the 80188 begins execution
withthe instruction at physical location FFFFO(H). RES
also sets some registers to predefined values as shown
;
in Table 5.
The 80188 and 80186 are completely software compatible by virture of their identical execution units. Software that is system dependent may not be completely
transferable, but software that is not system dependent will operate equally well on an 80188 or an 80186.
The hardware interface of the 80188 contains the
major differences between the two CPUs. The pin
assignments are nearly identical, however, with the
following functional changes.
• A8-A15- These pins are only address outputs on
the 80188. These address lines are latched internally
and remain valid throughout a bus cycle in a manner
similar to the 8085 upper address lines.
• BHE has no meaning on the 80188 and has been
eliminated.
Table 5. 80188 Initial Register State after RESET
Status Word
Instruction Pointer
Code Segment
Data Segment
Extra Segment
Stack Segment
Relocation Register
UMCS'
the same end result. The differences between the
80188 and 80186 are outlined below. Internally, there
are three differences between the 80188 and the
80186. All changes are related to the 8-bit bus interface.
• The queue length is 4 bytes in the 80188, whereas
the 80186 queue contains 6 bytes, or three words.
The queue was shortened to prevent overuse of the
bus by the BIU when prefetching instructions. This
was required because of the additional time necessary to fetch instructions 8 bits at a time.
• To further optimize the queue, the prefetching algorithm was changed. The 80188 BIU will fetch a new
instruction to load into the queue each time there is
a l-byte hole (space available) in the queue. The
80186 waits until a 2-byte space is available.
• The internal execution time of the instruction is
affected by the 8-bit inte·rface. All 16-bit fetches and
writes from/to memory take an additional four clock
cycles. The CPU may also be limited by the speed of
instruction fetches when a series of simple operations occur. When the more sophisticated instructions of the 80188 are being used, the queue has
time to fill and the execution proceeds as fast as the
execution unit will allow.
F002(H)
OOOO(H)
FFFF(H)
OOOO(H)
OOOO(H)
OOOO(H)
20FF(H)
FFFB(H)
THE 80188 COMPARED TO THE 80186
iAPX 188 CLOCK GENERATOR
The 80188 CPU is an 8-bit processor designed around
the 80186 internal structure. Most internal functions of
the 80188 are identical to the equivalent 80186 functions. The 80188 handles the external bus the same
way. the 80186 does with the distinction of handling
only 8 bits at a time. Sixteen bit operands are fetched
or written in two consecutive bus cycles. Both processors will appear identical to the software engineer,
with the exception of execution time. The internal
register structure is identical and all instructions have
The iAPX 188 provides an on-chip clock generator
for both internal and external clock generation. The
clock generator features a crystal oscillator, a divideby-two counter, synchronous and asynchronous
ready inputs, and reset circuitry.
3-451
AFN-01483A
iAPX 188
Oscillator
edge of ARDY must be synchronized to the CLKOUT
signal if it will occur during T2, T3 or Tw. HIGH-to-LOW
tra'lsitions of ARDY must be performed synchronously
to the CPU clock.
The oscillator circuit of the iAPX 188 is designed to
be used with a pa~allel resonant fundamental mode
crystal. This is used as the time base for the iAPX 186.
The crystal frequency selected will be double the
CPU clock frequency. Use of an LC or RC circuit is not
recommended with this oscillator. If an external oscillator is used, it can be connected directly to input pin
X1 in lieu of a crystal. The output of the oscillator is
not directly available outside the iAPX 188. The
recommended crystal configuration is shown in
Figure 8.
A second ready input (SRDY) is provided to interface
with externally synchronized ready signals. This input is
sampled at the end of T2, T3 and again atthe end of each
Tw until it is sampled HIGH. By using this input rather
than the asynchronous ready input, the half-clock cycle
resolution time penalty is eliminated.
This input must satisfy set-up and hold times to
guarantee proper operation of the circuit.
..,...... 20pF
a
X,
-T-
::E:
X,
80188
--
In addition, the iAPX 188, as part of the integrated
chip-select logic, has the capability to program WAIT
states for memory and peripheral blocks. This is dis. cussed in the Chip Select/Ready Logic description.
x MHz CRYSTAL
20pF
':;"
x
80186 (8 MHz)
16
80186-6 (6 MHz)
12
RESET Logic
Figure 8_ Recommended iAPX 188 Crystal
Configuration
Clock Generator
The iAPX 188 clock generator provides the 50% duty
cycle processor clock for the iAPX 188. It does this by
dividing the oscillator output by 2 forming the sym- .
metrical clock. If an external oscillator is used, the
state of the clock generator will change on the falling
edge of the oscillator signal. The CLKOUT pin provides the processor clock signal for use outside the
iAPX 188., This may be used to drive other system
components. All timings are referenced to the output
clock.
READY Synchronization
The iAPX 188 provides both a RES input pin and a
synchronized RESET,pin for use with other system
components. The RES input pin on the iAPX 188 is
provided with hysteresis in order to facilitate poweron Reset generation via an RC network. RESET is
guaranteed to remain active for at least five clocks
given a RES input of at least six clocks. RESET may
be delayed up to two and one-half clocks behind
RES.
Multiple iAPX 188 processors may be synchronized
through the RES input pin, since this input resets
both the processor and divide-by-two internal counter in the clock generator. In order to insure that the
divide-by-two counters all begin counting at the
same time, the active going edge of RES must satisfy
a 25 ns setup time before the falling edge of the
80188 clock input. In addition, in order to insure that
all CPUs begin executing in the same clock cycle, the
reset must satisfy a 25 ns setup time before the rising
edge of the CLKOUT signal of all the processors.
The iAP~ 188 provides both syncbronous and asynchronous ready inputs. Asynchronous ready synchronization is accomplished by circuitry which samples ARDY
in the middle ofT2, T3 and again inthe middle of each Tw
until ARDY is sampled HIGH. One-half CLKOUT cycle
of resolution time is used. Full synchronization is performed only onthe rising edge of ARDY, i.e., the falling
3-452
AFN-01483A
inter
IAPX 188
Oscillator
The oscillator circuit of the iAPX 188 is designed to
be used with a parallel resonant fundamental mode
crystal. This is used as the time base for the iAPX 186.
The 'crystal frequency selected will be double the
CPU clock frequency. Use of an LC or RC circuit is not
recommended with this oscillator. If an external oscillator is used, it can be connected directly to input pin
X1 in lieu of a 'crystal. The output of the oscillator is
not directly available outside the iAPX 188. The
recommended crystal configuration is shown in
Figure 8.
~2OPf.
X,
x,
80188
515
-==r=~
-:r::-
MHz CRYSTAL
20 pl.
eqge of ARDY must be synchronized to the CLKOUT
signal if it will occur during T2, T3 or Tw. HIGH-to-LOW
transitions of ARDY must be performed synchronously
to the CPU clock.
A second ready input (SRDY) is provided to in,erface
with externally synchronized ready signals. This input is
sampled at the end of T2, T3 and again at the end of each
Tw until it is sampled HIGH. By Using this input rather
than the asynchronous ready input, the half-clock cycle
resolution time penalty is eliminated.
This input must satisfy set-up and hold times to
guarantee proper operation of the circuit.
In addition, the iAPX 188, as part of the integrated
chip-select logic, has the capability to program WAIT
states for memory and peripheral' blocks. This is discussed in the Chip Select/Ready Logic description:
-=RESET Logic
The iAPX 188 provides both a RES input pin and a
synchronized RESET pin for use with other system
components. The RES input pin on the iAPX 188 is
provided with hysteresis in order to facilitate poweron Reset generation via an RC network. RESET is
guaranteed to remain active for at least five clocks
given a RES input of at least six clocks. RESET may
be delayed up to two and one-half 'clocks behind
RES.
Figure 8. Recommended IAPX 188 Crystal
Configuration
Clock Generator
The iAPX 188 clock generator provides the 50% duty
cycle processor clock for the iAPX 188. It aoes this by
dividing the oscillator output by 2 forming the symmetrical clock. If an external oscillator is used, the
state of the clock generator will change on the falling
edge of the oscillator signal. The CLKOUT pin provides the .processor clock signal for use outside the
iAPX 188., This may be used to drive other system
components. All timings are referenced to the output
clock.
Multiple iAPX 188 processors may be synchronized
through the RES input pin, since this input resets
both the processor and divide-by-two internal counter in the clock generator. In order to insure that the
divide-by-two counters all begin counting at the
same time, the active going edge of RES must satisfy
a 25 ns setup time before the falling edge of the
80188 clock input. In addition, in order to insure that
all CPUs begin executing in 'the same clock cycle, the
reset must satisfy a 25 ns setup time before the rising
edge of the CLKOUT signal of afl the processors.
READY Synchronization
The iAPX 188 provides both synchronous and asynchronous ready inputs. Asynchronou$ ready synchronization is accomplished by circuitry which samples ARDY
in the middle of T2, T3 and again in ~he middle of each Tw
until, ARDY is sampled HIGH. One-half CLKOUT cycle
of resolution time is used. Full synchronization is performed only onthe rising edge of ARDY, I.e., the falling
3453
AFN-01483A
IAPX 188
INTERNAL PERIPHERAL INTERFACE
All the iAPX 188 integrated peripherals are controlled via 16-bit registers contained within an internal 256-byte control block. This control block may be
mapped into either memory or 1/0 space. Internal
logic will recognize the address and respond to the
bus cycle. During bus cycles to internal registers, the
bus controller will sigl1al the operation externally
(i.e., the RD, WR, status, address, data, etc., line~ will
be driven as in a normal bus cycle), but 07-0, SROY,
and AROY will be ignored. The base address of the
control block must be on an even 256-byte boundary
(i.e., the lower 8 bits of the base address are all
zeros). All of the defined registers within this control
block may be read or written by the 80188 CPU at any
time. The location of any register contained within
the 256-byte control block is determined by the current base address of the control block.
The control block base address is programmed via a
16-bit relocation register contained within the control block at offset FEH from the base address of the
control block (see Figure 9). It provides the upper 12
bits of the base address of the control block. Note
that mapping the control register block into an address range corresponding to a chip-select range is
not recommended (the chip select circuitry is discussed later in this data sheet). In addition, bit 12 of
this register determines whether the control block
will be mapped into 1/0 or memory space. If this bit is
1, the control block wi II be .Iocated in memory space,
whereas if the bit is 0, the control block will be located in 1/0 space. If the control register blOCk is
mapped into I/O space, the upper 4 bits of the base
address must be programmed as 0 (since 1/0 addresses are only 16 bits wide).
In addition to providing relocation information for
'the control block, the relocation register contains
bits which place the interrupt controller into iRMX
mode, and cause the CPU to interrupt upon encountering ESC instructions. At RESET, the relocation register is set to 20FFH. This causes thf3 control
block to start at FFOOH in 1/0 space. An offset map
of the 256-byte control register block is shown in
Figure 10.
The integrated iAPX 188 peripherals operate semiautonomously from the CPU. Access to them for the
most part is via software readlwrite of the control and
data locations in the control block. Most of these
registers can be both read and written. A few
dedicated lines, such as interrupts and DMA request
provide real-time communication between the CPU
and peripherals as il1 a more conventional system
utilizing discrete peripheral blocks. The overall interaction and function of the peripheral blocks has not
substantially changed. The data access from/to the
256-byte internal control block will always be 16-bit
and done in one bus cycle.
CHIP-SELECT/READY GENERATION
LOGIC
The iAPX 188 contains logic which provides programmable chip-select generation ·for both
memories and peripherals. In addition, it can be programmed to provide READY (or WAIT state) generation. It can also provide latched address bits A1 and
A2. The chip-select lines are active for all memory
and 1/0 cycles in their programmed areas, whether
they be generated by the CPU or by the integrated
DMA unit.
Memory Chip Selects
The iAPX 188 provides 6 memory chip select outputs
for 3 address areas: upper memory, lower memory,
arid midiange memory. One each is provided for up~
per memory and lower memory, while four are provided for midrange memory.
The range for each chip select is user-programmable
and can be set ~o 2K, 4K, 8K, 16K, 32K, 64K, 128K
(plus 1K and 256K for upper and lower chip selects).
In addition, the beginning or base address of the '
midrange memory chip select may also be selected.
Only one chip select may be programmed to be active for any memory location at a time. All chip select
sizes are in bytes.
AFN-Il1483A
IAPX 188
15
14
13
12
11
10
9
OFFSET: FEHI ET !AMX! X !MIlO!
I
7
Aelocatlon Add.... Bits R1B-RI
ET
= ESC Trap 1No ESC Trap (110)
MIlO = Aeglator block Iocaled In Mamory 1 ~O sto- (1/01
RMX = Normal Interrupt Conlroller mode IIAMX compatible
Interrupt Conlroller mode (11/1)
Figure 9. Relocation Register
Table 7. UMCS Programming Values
,OFFSET
Relocation Register
FEH
DAH
DMA Deocrlptoro Channell
DOH
CAH
DMA DellCrlptora Channel 0
COH
AIH
Starting
Address
(Base
Address)
Memory
Block
Size
FFCOO
FF800
FFOOO
FEOOQ
FCOOO
F8000
FOOOO
EOOOO
COOOO
1K
2K
4K
8K
16K
32K
64K
128K
256K
UMCS Value
(Assuming
RO=R:I =R2=0)
FFF8H
FFB8H
FF38H
FE38H
FC38H
F838H
F038H
E038H
C038H
Chlp-Selecl Conlrol Reglstero
AOH
The lower limit cif this memory block is defined' in the
UMCS register (s~e Figure 11). This register is at
olfset AOH in the internal control block. The legElI
values for bits 6-13 and the "resulting starting address and memory block sizes are given in Table 7.
Any combination of bits 6-13 not shown in Taple 7
will result in undefined operation. After reset, the
UMCS register is programmed for a 1K area. It must
be reprogrammed if a larger upper memory area ill
desired.
88H
Timer 2 Conlrol Reg_a
80H
5EH
Timer 1 COnirol Reglatero
58H
56H
Timer 0 Control Reglstera
SOH
Interrupt COnlroller Reg_a
3EH
Any internally generated 2Q-bit address whose upper
16 bits are greater than or equal to UMCS (with bits
0-5 "0") will cause UCS to be activated. UMCS bits
R2-RO are used to specify READY mode for' the area
of memory defined by this 'chip-select register, as
explained below.
. .
20H
Figure 10. Internal Register Map
Upper Memory CS
Lower Memory es
The. iAPX 188 provides a chip select,'called UCS, for
the top of memory. The top of memory is usually used
as the system memory because after re,set the iAPX
188 begins executing at memory location FFFFOH.
The iAPX 188 provides a chip select for low memory
called LCS. The bottom of memory contains the interrupt vector table, starting at location OOOOOH.
The upper limit of memory defined by this chip select
is always FFF'FfH, whiia the lower limit is programmable. By programming the lower limit, the size of
the select block is also .defined. Table 7 shows the
relationship between the base address selected and
the size of the memory block obtained.
The lower limit of memory defined by this chip select
is always OH, while the upper limit is programmable.
By' programming the upper limit, the size of the
memory block is also defined. Table 8 shows the
relationship between the upper address selected and
the· size Of the memory block obtained.
3-455
AFN'()I483A
iA~X
OFFSET:
ASH
I
15 ,14
1
13
12
11
10
188
9
8
7
6
I Me I M5 I M4 I M3 I M2 I Ml I MO I EX I M~ I
4
'2
1
0
1
I 1 I 1 I R2 I Rl I RO •I
1
I 1 I 1 I R2 I Rl I RO I
Figure 13. MPCS Register
9
15
OFFSET:
A6H
Iu Iu Iu Iu Iu IU
u
A19
I1I1I
1
I
0
A13
Figure 14. MMCS Register
MMCS bits R2-RO specify READY mode of operation
for all mid-range chip selects. All devices in midrange memory must use the same number of WAIT
states.
however itean only be a multiple of 1K bytes, I.e., the
least significant 10 bits of the starting address are
always O.
The 512K block size for the mid-range memory chip
selects isa special case. When using 512K, the base
address would have to be at either locations OOOOOH
or 80000H. If it were to be programmed at OOOOOH
when the LCS line was programmed. there would be
an internal conflict between the LCS ready generation logic and the MCS ready generation logic.
Likewise, if the base address were programmed at
80000H, there would be a conflict with the UCS ready
generation logic. Since the LCS chip-select line does
not beCome active until programmed, while the UCS
line is active at reset, the memory base can be set
only at OOOOOH. If this base address is selected,
however, the LCS range must not be programmed.
PCS5 and PCS6 can also be programmed to provide
latched address bits A1, A2. If so programmed, they
cannot be used as peripheral selects. These outputs
can be connected directly to the AO, A1 pins used for
selecting internal registers of 8-bit peripheral chips.
This scheme ,simplifies the hardware interface' because the 8-bit registers of peripherals are simply
treated as 16-bit registers located on even boundaries in I/O space or memory space where only the
Iqwer 8-bits of the register are significant: the upper
8-bits are "don't cares."
The starting address of the peripheral chip-select
block is defined by the PACS register (see Figure 15).
This register is located at offset A4H in the internal
control block. Bits 15-6'01 this register correspond to
bits 19-10 of the 20-bit Programmable Base Address
(PBA) of the peripheral chip-select block. Bits 9-0 of
the PBA of the peripheral chip-select block are all
zeros. If the chip-select block is located in I/O space,
bits 12-15 must be programmed zero, since the I/O
address is only 16 bits wide. Table 10 shows the
address range of each peripheral chip select with
respect to the PBA contained in PACS register.
Peripheral Chip Selects
The iAPX 188, can generate chip selects for up to
seven peripher~1 devices. These chip selects are active for seven contiguous blocks of 128 bytes above a
programmable base address. This base address may
be located in either memory or I/O space.
Seven CS lines called PCSO-6 are generated by the
iAPX 188. The base address is user-programmable;
OFFSET:
A4H
I
15
u
I u I u u1u 1u
u 1 u lui
5
u
3
0
1 1 11 I 1 1R2 1Rl I RO I
Al0
A19
Figure 15. PACS Register
3-456
AFN~l483A
IAPX 188
each chip-select range individually or to factor external READY with the integrated ready generator.
The user should program bits 15-6 to correspond to
the desired peripheral base location. PACS bits 0-2
are used to specify READY mode for PCSO-PCS3.
READY control consists of 3 bits for each CS line or
group of lines generated by the iAPX 188. The interpretation of the ready bits is shown in Table 12.
Table 10. PCS Address Ranges
PCS Line
Active between Locations
PC SO
PCS1
PCS2
PCS3
PCS4
PCS5
PCS6
PBA
-PBA+127
PBA+128 -PBA+255
PBA+256 -PBA+383
PBA+384 -PBA+511
PBA+512 -PBA+639
PBA+640 - PBA+ 767
PBA+ 768 - PBA+895
Table 12. READY Bits Programming
The mode of operation of the peripheral chip selects
is defined by the MPCS register (which is also used to
set the size of the mid-range memory ch'ip-select
block, see Figure 16). This register is located at offset
ASH in the internal control block. Bit 7 is used to
select the function of PCS5 and PCS6, while bit 6 is
used to select whether the peripheral chip selects
are mapped into memory or I/O space. Table 11 describes the programming of these bits. After reset,
the contents of both the MPCS and the PACS registers are undefined, however none of the PCS lines
will be.active until both of the MPCS and PACS registers are accessed.
MS
EX
Description
1
0
0
1
= Peripherals mapped into memory space.
= Peripherals mapped mto I/O space.
= 5 PCS lines. A1, A2 provided.
= 7 PCS lines. A1, A2 are not provided.
READY Generation Logic
15
0
0
0
1
0
1
1
1
0
0
1
1
1
.1
0 o wait states, external ROYaiso used.
1 1 wait state inserted, external ROY also
used.
0 2 wait states inserted, external ROYaiso
used.
1 3 wait states inserted, external ROYaiso
used.
0 o wait states, external ROY ignored.
1 1 wait state inserted, external ROY
ignored.
0 2 wait states inserted, external ROY
ignored.
1 3 wait states inserted, external ROY
ignored.
Chip Select/Ready Logic and Reset
The iAPX 188 can generate a "READY" Signal internally for each of the memory or peripheral CS lines.
The number of WAIT states to be inserted for each
peripheral or memory is programmable to provide
0-3 wait states for all accesses to the area for which
the chip select is active. In addition, the iAPX 188 may
be pr09rammed to either ignore external READY for
A8H
RO Number of WAIT States Generated
0
0
R2-RO of each control word specifies the READY
mode for the corresponding block, with the exception of the peripheral chip selects: R2-RO of PACS
set the PCSO-3 READY mode, R2-RO of MPCS set
the PCS4-6 READY mode.
MPCS bits 0-2 are used to specify READY mode for
PCS4-PCS6 as outlined below.
OFFSET:
R1
The internal ready generator operates In parallel with
external READY, not in series if the external READY
is used (R2 = 0). This means, for example, if the
internal generator is set to insert two wait states, but
activity on the external READY lines will insert four
wait states, the processor will only insert four wait
states, not six. This is because the two wait states
generated by the internal generator overlapped the
first two wait states generated by the external ready
signal. Note that the external ARDYand SRDY lines
are always ignored during cycles accessing internal
peripherals.
Table 11. MS, EX Programming Values
Bit
R2
14
13
12
11·
10
Upon reset, the Chip-Select/Ready Logic will perform the following actions:
• All chip-select outputs will be driven HIGH.
• Upon leaving RESET, the UCS line will be programmed to provide chip selects to a 1K block with
the accompanyi~g READY control bits set at 011 to
9
8
7
6
2
1
0
I 1 I M6 I M5 I M41 M3 I M21 M1 I MO I EX I MS I 1 I 1 I 1 I R2 I R1 I RO I
Figure 16. MPCS Register
3-457
AFN-01483A
inter
iAPX 188
SOURCE
DEC
INC
Figure 18. DMA Control Register
DMA Channel Control Word Register
INT:
Each DMA Channel Control Word determines the
mode of operation for the particular 80188 DMA
channel. This register specifies:
TC:
• the mode of synchronization;
• whether interrupts will be generated after the last
transfer;
• whether DMA activity will cease after a programmed number of DMA cycles; .
• the relative priority of the DMA channel with
respect to the other DMA channel;
• whether the source pointer will be incremented;
decremented, or. maintained constant after each
transfer;
• .whether the. source pointer addresses memory or
I/O space;
• whether the destination pointer will be incremented,decremented, or maintained constant after each transfer; and
• whether the destination pointer will address
.nemory or 110 space.
SYN:
(2 bits)
SOURCE:INC
The DMA channel control registers may be changed
while the channel is operating. However, any
changes made during operation will affect the current DMA transfer.
Mira
Start/stop (1/0) Channel.
CHG/NOCHG:
Change/D.o not change (1/0)
ST/STOP bit. If this bit is set when
writing to the control word, the
STiSTOP bit will be programmed by
the write to the control "ford. If this
bit is cleared when writing the control word, the ST/STOP bit will not
be altered. This bit is not stored; it
will always bj! a 0 on read.
Increment source pointer by 1 after
each transfer.
Source pointer is in MilO space
(1/0).
DEST:
DMA Control Word Bit Descriptions
ST/STOP:
Enable Interrupts to CPU on byte
count terminatio"n.
If set, DMA will terminate when the
contents of the Transfer Count register reach zero. The ST/STOP bit
will also be reset at this point if TC is
set. If this bit is cleared, the DMA
unit will decrement the transfer
count register for each DMA cycle,
but the DMA transfer will not stop
when the contents of the TC register
reach zero.
00 No synchronization.
NOTE: The ST bit will be cleared
automatically when the contents
of the TC register reach zero regardless of the state of the TC bit.
01 Source synchronization.
10 Destination synchronization.
11 Unused.
DEC
Decrement source pointe( by 1 after
each transfer.
INC
Increment· destination pointer by 1
after each transfer.
Destination pointer is in M/IO'space
(1/0).
M!IO
DEC
P
Decrement destination pointer by 1
after each transfer.
Channel priority-relative to other
channel.
o low priority.
1 high priority.
Channels will alternate cycles if
both set at same priority level.
3-458
AFN-01483A
iAPX 188
allow the maximum number of internal wait states
in conjunction with external Ready consideration
(i.e., UMCS resets to FFFBH).
• No other chip select or READY control registers
have any predefined values after RESET. They will
not become active until the CPU accesses their
control registers. Both the PACS and MPCS registers must be accessed before the PeS lines will
become active.
DMA Operation
Each channel has six registers in the control block
which define each channel's specific operation. The
control registers consist of a 20-bit Source pointer (2
words), a 20-bit Destination pointer (2 words), a 16bit Transfer Counter, and a 16-bit Control Word. The
format of the DMA Control Blocks is shown in Table
13. The Transfer Count Register (TC) specifies the
number of DMA transfers to be performed. Up to 64K
byte transfers can be performed with automatic termination. The Control Word defines the channel's operation (see Figure 18). All registers may be modified or
altered during any OllilA activity. Any changes made to
these registers will be reflected immediately in DMA
operation.
DMA CHANNELS
The 80188 DMA controller provides two independent
high-speed DMA channels. Data transfers can occur
between memory and I/O spaces (e.g., Memory to I/O)
or within the same space (e.g., Memory to Memory or
I/O to I/O). Each DMA channel maintains both a 20-bit
source and destination pointer whicl) can be optionally
incremented or decremented after each data transfer.
Each data transfer consumes 2 bus cycles (a minimum
of 8 clocks), one cycle to fetch data and the other to
store data. This provides a maximum data transfer rate
of one MByte/sec.
Table 13.
DMA Control Block Format
Register Address
Register Name
Control Word
Transfer Count
Destination Pointer (upper 4
bits)
Destination Pointer
Source Pointer (upper 4 bits
Source Pointer
Ch.O
Ch.1
CAH
C8H
C6H
DAH
D8H
D6H
C4H
C2H
COH
D4H
D2H
DOH
TIMER REQUEST
DMA
CONTROL
LOGIC
1 - - -__ INTERRUPT
'-_..,....._...J
REQUEST
Figure 17.
DMA Unit Block Diagram
3-459
AFN-01483A
iAPX 188
TDRQ
0: Disable DMA requests from timer
D.MA Requests.
2.
Data transfers may be either source or destination
synchronized, that is either the source of the data or
the destination of the data may request the data
transfer. In addition, DMA transfers may be unsynchronized; that is, the transfer will take place
continually until the correct number of transfers has
occurred. When source or unsynchronized transfers
are performed, the DMA channel may begin another
transfer immediately after the end of a previousDMA
transfer. This allows a complete transfer to take place
every 2 bus cycles or eight clock cycles (assuming no
wait states). No prefetching occurs when destination
synchronization is performed, however. Data will not
be fetched from the source address until the destination device Signals that it is ready to receive it. When
destination synchronized transfers are requested,
the DMA controller will relinquish control of the bus
after every transfer. If no other bus activity is initiated, another DMA cycle will begin after two processor clocks. This is done to allow the destination
device time to remove its request if another transfer
is not desired. Since the DMA controller will relinquish the bus, the CPU can initiate a bus cycle. As a
result, a complete bus cycle will often be inserted
between destination synchronized transfers. These
lead to the maximum DMA transfer rates shown in
Table 14.
1: Enable DMA requests from timer
2.
Bit3
Bit 3 is' not used.
If both INC and DEC are specified for the same
pointer, the pointer will remain constant after each
cycle.
DMA Destination and Source Pointer
Registers
Each DMA channel maintains a 20-bit source and a
20-bit destination pointer. Each of these pOinters takes
up two full 16-bit registers in the peripheral control
block. The lower four bits of the upper register contain
the upper' four bits of the 20-bit physical address (see
Figure 18a). These pOinters may be individually incremented or decremented after each transfer. Each pOinter may poi nt into either memory or I/O space. Since the
DMA channels can perform transfers to or from odd
addresses, there is no restriction on values for the pointer registers.
DMA Transfer Count Register
Each DMA channel maintains a 16-bit transfer count
register (TC). This register is decremented after every
DMA cycle, regardless of the state of the TC bit int he
DMA Control Register. If the TC bit in the DMA control
word is set or unsynchronized transfers are programmed, DMA activity will terminate when the transfer
count register reaches zero.
Table 14, Maximum DMA Transfer Rates
Type of
Synchronization
Selected
CPU Running
CPU Halted
Unsynchronized
Source Synch
Destination Synch
1MBytes/sec
1MBytes/sec
.65MBytes/sec
1MBytes/sec
1MBytes/sec
.75MBytes/sec
HIGHER
REGISTER
ADDRESS
xxx
xxx
XXX
A19-A16
LOWER
REGISTER
ADDRESS
A15-A12
All-A8
A7-A4
A3-AO
I
I
15
xxx " DON'T CARE
Figure 18a, DMA Memory Pointer Register Format
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Table 8. LMCS Programming Values
Memory
Block
Size
Upper
Address
.
003FFH
oo7FFH
OOFFFH
01FFFH
03FFFH
07FFFH
OFFFFH
1FFFFH
3FFFFH
by bits 8-14 of the MPCS register (see Figure 13).
This register is at location A8H in the internal control
block. One and only one of bits 8-14 must be set at a
time. Unpredictable operation of the MCS lines will
otherwise occur. Each of the four chip-select lines is
active for one of the four equal contiguous divisions
of the mid-range block. Thus, if the total block size is
32K, each chip select is active for 8K of memory with
MCSP being active for the first range and MCS3
being active for the last range.
LMCS Value
(Assuming
RO=R1 =R2=O)
1K
2K
4K
8K
16K
32K
64K
128K
256K
0038H
0078H
00F8H
01F8H
03F8H
07F8H
OFF8H
1FF8H
3FF8H
The EX and MS in MPCS relate to peripheral
functionality as descibed a later section.
The upper limit of this memory block is defined in the
LMCS register (see 'Figure 12). This register is at
offset A2H in the internal control block. The legal
values for bits 6-15 and the resulting upper address
and memory block sizes are given in Table 8. Any
combination of bits 6-15 not shown in Table 8 will
result in undefined operation, After reset, the LMCS
register value is undefined. However, the LCS chipselect line will not become active until the LMCS
register is accessed.
Table 9. MPCS Programming Values
Any internally generated 20-bit address whose upper
16 bits are less than or equal to LMCS (with bits 0-5
"1 ") will cause LCS to be active. LMCS register bits
R2-RO are used to specify the READY mode for the
area of memory defined by this chip-select register.
Mid-Range Memory CS
The size of the memory block defined by the midrange select lines, as shown in Table 9, is determined
15
AOHI 1
A19
14
13
12
11
10
Individual
Select Size
MPCS Bits
14-8
8K
16K
32K
64K
128K
256K
512K
2K
4K
8K
16K
32K
64K
128K
00000018
00000108
00001008
00010008
00100008
01000008
10000008
The base address ,of the mid-range memory block is
defined by bits 15-9, of the MMCS register (see Figure 14). This register is at offset A6H in the internal
control block. These bits correspond to bits A19-A13
of the 20-bit memory address. Bits A12-AO of the
base address are always O. The base address may be
set at any integer multiple of the size of the total
memory block selected. For example, if the midrange block size is 32K (or the size of the block for
which each MCS line is active is 8K), the block could
be located at 10000H or 18000H, but not at 14000H,
since the first few integer multiples of a 32K memory
block are OH, 8000H, 10000H, 18000H, etc. After
reset, the contents of both of these registers is undefined. However, none of the MCS lines will be active until both the MMCS and MPCS registers are
accessed.
The iAPX 188 provides four MCS lines which are
active within a user-locatable memory block. This
block can be located anywhere within the iAPX 188
1M byte memory address space exclusive of the
areas defined by UCS and LCS. Both the base address and size of this memory block are
programmable.
OFFSET:
Total Block
Size
9
8
7
6
5
4
3
2
1
0
2
1
I 1 I u I u I u I u I u I u I u I u I 1 I 1 I 1 I R2 I Rl I RO I
All
Figure 11. UMCS Register
15
OFFSET:
A2H
14
13
I 0 lou
12
u
·11
I iI
10
u
9
u I u I u lu I
A19
1
0
I 1 I 1 I R2 I Rl I RO I
All
Figure 12. LMCS Register
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are programmed, a ,ORO must also "'ave been,
generated. Therefore, the source and destination
transfer pointers, and the transfer count register (if
use,d) must be programmed before this bit is s~t.
DMA Acknowledge
No explicit DMA acknowledge pulse is provided.
Since both source and destination pointers a~e
maintained, a read from a requesting source, or a
write to a requesting destination, should be used as
the DMA acknowledge signal. Since the chip-select
lines ,can be programmed to be active for a given
block of memory or I/O space, and the DMA pointers
can be programmed to point to .the same given block,
a chip-select line could be used to indicate a DMA
acknowledge.
Each DMA register may be modified while the cha'loel is operating. If the CHG/NOCHG bit is cleared
when the control register is written, the ST/STOP bit
of the control register will not be modified by the
write. If multiple channel registers are modified, it is
recommended that a LOCKED string transfer be
used to prevent a DMA transfer from occurring between updates to the channel registers.
DMA Priority
DMA Channels and Reset
The DMA: channels may be programmed such that
one channel is always given priority over the other, or
they may be programmed such as to alternate cycles
when both h'ave DMA requests pending. DMA cycles
always have priority over internal CPU cycles except
between locked memory accesses or word accesses
the odd memory locations; however, an external bus
hold takes priority over an internal DMA cycle. Because an interrupt request cannot suspend a DMA
operation and the CPU cannot access memory during a DMA cycle, interrupt latency time will suffer
during sequences, of continuous DMA cycles. An
NMI request, however, will cause all internal DMA
activity to halt. This allows the CPU to quickly
respond to the NMI request.
Upon RESET, the DMA channels will perform the
following actions:
• The Start/Stop bit for each channel will' be reset to
STOP.,
• Any transfer in progress is aborted~
TIMERS
The 80188 provides three internal 16-bit programmable timers (see Figure 19). Two of these are highly
flexible and are connected to four external pins (2
per timer). They can be used to count external
events, time external events, generate nonrepetitive
waveforms, etc. The'third timer is not connected to
any external pins, and is useful for real-time coding
and time delay applications. In addition, this third
timer can be used as a prescaler to the other two, or
as a DMA request source.
DMA Programming
DMA cycles will occur whenever the ST/STOP bit of
the',Control Register is set. If synchrohized transfers
DMA
REO.
·12
INT.
REO.
TIMERO '
MAX COUNT VAWE
A
TIMER 2
CLOCK
MAX COUNT VALUE
B
MAX COUNT VAWE
MDDEICONTROL
WORD
INTERNAL ADDRESS/DATA BUS
ALL 16 BIT REGISTERS
Figure 19. Timer Block Diagram
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Since the count registers and the maximum count
registers are all 16 bits wide, 16 bits of resolution are
provided. Any Read or Write access to the timers will
add on~ wait state to the minimum four-clock bus
cycle, however. This is needed to synchronize and
coordinate the internal data flows between the internal timers and the internal bus.
Timer Operation
The timers are controlled by 11 16-bit registers in the
internal peripheral control block. The configuration
of these registers is shown in Table 15. The count
register contains the current value of the timer. It can
be read or written at any time independent of
whether the timer is running or not. The value of this
register will be incremented fo~ each timer event.
Each of the timers is equipped with a MAX COUNT
register, which defines the maximum count the timer
will reach. After reaching the MAX COUNT register
value, the timer count value will reset to zero during
that same clock, i.e., the maximum count value is
never stored in the count register itself. Timers 0 and
1 are, in addition, equipped with a second MAX
COUNT register, which enables' the timers to alternate their count between two different MAX COUNT
values programmed py the user. If a single MAX
COUNT register is used, the timer output pin will
switch LOW for a single clock, 2 clocks after the
maximum count value has been reached. In the dual
MAX COUNT register mode, the output pin will'indi- •
cate which MAX COUNT register is currently in use,
thus allowing nearly complete freedom in selecting
waveform duty cycles. For the timers with two MAX
COUNT registers, the RIU bit in the control register
dete~mines which is used for the comparison.
The timers have several programmable
These options are selectable via the timer model
control word.
Timer Mode/Control Register
The mode/control register (see Figure 20) allows the
user to program the specific mode of operation or
check the current programmed status for any-of the
three integrated timers.
'
Each timer gets serviced every fourth CPU-clock
cycle, and thus can operate at speeds up to onequarter the internal clock frequency (one-eighth the
crystal rate). External clocking of the timers may be
done at up to a rate of one-quarter of the internal
CPU-clock rate (2 MHz for an 8 MHz CPU clock). Due
to internal synchronization and pipelining of the
timer circuitry, a timer output may take up to 6 clocks
to respond to any individual clock or gate input.
15
14
13
12
EN I iNti liNT I RIU I
o~tions.
• All three timers can be set to halt or continue on a
terminal count.
• Timers 0 and 1 can select between internal and
external clocks, alternate between MAX COUNT
registers and be set to retrigger on external events.
• Tile timers may be programmed to cause an interrupt on terminal,count.
Table 15. ,Timer Control Block Format
Register Offset
Register Name
Tmr.O Tmr.1
Mode/Con.trol Word
Max Count B
Max Count A
Count Register
11
,
5
4
3
0
1····1
Me
I RTG I
p
2
1
56H
54H
52H
50H
5EH
5CH
5AH
58H
Tmr.2
66H
not present
62H
60H
0
I EXT I ALT ICONTI
Figure 20. Tlmerl Mode/Control Register
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ALT:
The ALT bit determines' which of two MAX COUNT
registers is used for count comparison. If ALT = 0,
register A for that timer is always used, while if ALT =
1, the comparison will alternate between register A
and register B when each maximum count is
reached. This alternation allows the user to change
one MAX COUNT register while the other is being
used, and thus provides a method of generating nonrepetitive waveforms. Square waves and pulse outputs of any duty cycle are a subset of available
signals obtained by not changing the final count
registers. The ALT bit also determines the function of
the timer output pin. If ALT is zero, the output pin will
go LOW for one clock, the clock after the maximum
count is reached. If ALT is one, the output pin will
reflect the current MAX COUNT register being used
(0/1 for B/ A).
CONT:
Setting the CaNT bit causes the associated timer to
run continuously, while resetting it causes the timer
to halt upon maximum count. If CaNT = and ALT
=1, the timer will count to the MAX COUNTregister A
value, reset, count to the register B value, reset, and
halt.
°
EXT:
The external bit selects between internal and exter~
nal clocking for the timer. The external signal may be
asynchronous with respect to the 80188 clock. If this
bit is set, the time( will count LOW-to-HIGH transitions on the input pin. If cleared, it will count an
internal clock while using the input pin'for control. In
this mode, the function of the external pin is defined
by the RTG bit. The maximum input to output transition latency time may be as much as 6 clocks.
However, clock inputs may be pipelined as closely
together as every 4 clocks without· losing clock
pulses.
P:
The prescaler bit is ignored unless internal. clocking
has been selected (EXT = 0). If the P bit is a zero, the
timer will count at one-fourth the internal CPU clock
rate. If the P bit is a one, the output of timer 2 will be
used as a clock for the timer. Note that the user must
initialize and start timer 2 to obtain the prescaled
clock.
RTG:
Retrigger bit is only active for internal clocking (EXT
<=0). In this case it determines the control function
provided by the input pin.
If RTG = 0, the input level gates the internal clock on
and 9ft If the input pin is HIGH, the timer will count; if
the input pin is LOW, the timer will .hold its value. As
indicated previously, the input signal may be asyn'chronous with respect to the 80188 clock.
When RTG = 1, the input pin detects LOW-to-HIGH
transitions. The first such transition starts the timer
running, tlearing the timer value to zero on the first
clock, and then incrementing thereafter. Further
transitions on the input pin will again reset the timer
to zero, from which it will stl;lrt counting up again. If
CaNT = 0, when the timer has reached maximum
count, the EN bit will be cleared, inhibiting further
timer activity.
EN:
The enable bit provides programmer control over the
timer's RUN/HALT status. When set, the timer is enabled to increment subject to the input pin constraints in the internal clock mode (discussed
previously). When cleared, tJ:le timer will be inhibited
from counting. All input pin transitions during the
time EN is zero will be ignored. If CaNT is zero, the
EN bit is automatically 'cleared upon maximum
count.
INH:
The inhibit bit allows for selective updating of the
enable (EN) bit. If INH is a one during the write to the
mode/control word, then the state of the EN bit will
be modified by the write. If INH is a zero during the
write, the EN bit will be unaffected by the operation.
This bit is not stored; it will always be a on a read.
°
I
INT:
When set, the,lNT bit enables interrupts from the
timer, which will be generated on every terminal
count. If the timer is configured in dual MAX COUNT
register mode, an interrupt will be generated each
time the value in MAX COUNT register A is reached,
and each time the value in MAX COUNT register B is
reached. If this enable bit is cleared after the interrupt request has been generated, but before a pending interrupt is serviced,. the interrupt request will
still be in force. (The request is latched in the Interrupt Controller.)
Me:
The Maximum Count bit is set whenever the timer
reaches its final maximum count value. If the timer is
configured in dual MAX COUNT register mode, this bit
will be set each time the value in MAX COUNT register
A is reached, and each time the value in MAX COUNT
register B is reached. This bit is set regardless of the
timer's interrupt-enable bit. The MC bit gives the user
the ability to monitor timer status through software
instead of through interrupts. Programmer intervention is required to clear this bit.
3-464
AFN-Ol483A
iAPX 188
RIU:
The Register In Use bit indicates which MAX COUNT
register is currently being used for comparison to the
timer count value. A zero value indicates register A.
The RIU bit cannot be written, i.e., its value is not
affected when the Control register is written. It is
always cleared when the ALT bit is zero.
Not all mode bits are provided for timer 2. Certain bits
are hardwired as indicated below:
ALT = 0, EXT = 0, P = 0, RTG = 0, RIU = 0
Internal interrupt sources (Timers and DMA channels) can be disabled by their own control registers
or by mask bits within the interrupt controller. The
80188 interrupt controller has its own control registers that set the mode of operation for the controller.
The interrupt controller will resolve priority among
requests that are pending simultaneously. Nesting is
provided so interrupt service routines for lower
priority interrupts may themselves be interrupted by
higher priority interrupts. A block diagram of the
interrupt controller is shown in Figure 21.
Count Registers
The interrupt controller has a special iRMX 86 compatibility mode that allows the use of the 80188
within the iRMX 86 operating system interrupt structure. The controller is set in this mode by setting bit
14 in the peripheral control block relocation register
(see iRMX 86 Compatibility Mode section). In this
mode, the internal 80188 interrupt controller functions as a "slave" controller to an external "master"
controller. Special initialization software must be included to properly set up the 80188 interrupt controller in iRMX 86 mode.
Each of the three timers has a 16-bit count register.
The current contents of this register may be read or
written by the processor at any time. If the register is
written into while the timer is counting, the new value
will take effect in the current count cycle.
Max Count Registers
Timers 0 and 1 have two MAX COUNT registers, while
timer 2 has a single MAX COUNT register. These contain the number of events the timer will count. In
timers 0 and 1, the MAX COUNT register used can
alternate between the two max count values
whenever the current maximum count is reached.
The condition which causes a timer to reset is equivalent between the current count value and the max
count being used. This means that if the count is
changed to be above the max count value, or if the
max count value is changed to be below the current
value, the timer will not reset to zero, but rather will
count to its maximum value, "wrap around" to zero,
then count until the max count is reached.
Timers and Reset
Upon RESET, the Timers will perform the following
actions:
• All EN (Enable) bits are reset preventing timer
counting.
• All SEL (Select) bits are reset to zero. This selects
MAX COUNT register A, resulting in the Timer Out
pins going HIGH upon RESET.
NON-iRMX MODE OPERATION
Interrupt Controller External Interface
For external interrupt so"Urces, five dedicated pins
are provided. One of these pins is dedicated to NMI,
non-maskable interrupt. This is typically used for
power-fail interrupts, etc. The other four pins may
function either as four interrupt input lines with internally generated interrupt vectors, as an interrupt line
and an interrupt acknowledge line (called the
"cascade mode") along, with two other input lines
with internally generated interrupt vectors, or as two
interrupt input lines and two dedicated interrupt acknowledge ouput lines. When the interrupt lines are
configured in cascade mode, the 80188 interrupt
'controller will' not generate internal interrupt
vectors.
External sources in the cascade mod'e use externally
generated interrupt vectors. When an interrupt is
acknowledged,two INTA cycles are initiated and the
vector is read into the 80188 on the second cycle. The
capability to interface to external 8259A programmable interrupt controllers is thus provided when the
inputs are configured in cascade mode.
INTERRUPT CONTROLLER
The 80188 can receive interrupts from a number of
sources, both internal and external. The internal interrupt controller serves to merge these requests on
a priority basis, for individual service by the CPU.
3-465
AFN-01483A
iAPX 188
Interrupt Controller Modes of Operation
before the issuance of the return from interrupt instruction. If the fully nested structure has been
upheld, the next highest-priority source with its IS bit
set is then serviced.
The basic modes of operation of the interrupt controller in non-iRMX mode are similar to the 8259A.
The interrupt controller responds identically to internal interrupts in all three modes: the difference is
only in the interpretation of function of the four external interrupt pins. The interrupt controller is set into
one of these three modes by programming the correct bits in the INTO and INT1 control registers. The
modes of interrupt controller operation are as
follows:
Cascade Mode
The 80188 has four interrupt pins and two of them
have dual functions. In the fully nested mode the four
pins are used as direct interrupt inputs and the corresponding vectors are generated internally. In the
cascade mode, the four pins are configured into interrupt input-dedicated acknowledge signal pairs.
The interconnection is snown in Figure 22. INTO is an
interrupt input interfaced to an 8259A, while
INT2/INTAO serves as the dedicated interrupt acknowledge signal to that peripheral. The same is true
for INT1 and INT3/INTA1. Each pair can selectively be
placed in the cascade or non-cascade mode by programming the proper value into INTO and INT1 control registers. The use of the dedicated acknowledge
signals eliminates the need for the use of external
logic to generate INTA and device select signals.
Fully Nested Mode
When in the fully nested mode four pins are used as
direct interrupt requests. The vectors for these four
inputs are generated internally. An in-service bit is
provided'for every interrupt source. If a lOwer-priority
device requests an interrupt while the in-service bit
(IS) is set, no interrupt will be generated by the interrupt controller. In addition, if another interrupt request occurs from the same interrupt source while
the inservice bit is set, no interrupt will be generated
by the interrupt controller. This allows interrupt service routines to operate with interrupts enabled without being themselves interrupted by lower-priority
interrupts. Since interrupts are enabled, higherpriority interrupts will be serviced.
The primary cascade mode allows the capability to
serve up to 128 external interrupt sources through
the use of external master an,d slave 8259As. Three
levels of priority are created, requiring priority
resolution in 'the 80188 interrupt controller, the master 8259As, and the slave 8259As. If an external interrupt is serviced, one IS bit is set at each of these
levels. When the interrupt service routine is completed, up to three end-of-interrupt commands must
be issued by the programmer
When a service routine is completed, the proper IS
bit must be reset by writing the proper pattern to the
EOI register. This is required to allow subsequent
interrupts from this interrupt source and to allow
servicing of lower-priority interrupts. An EOI command is issued at the end of the service routine just
TIMER TIMER TIMER
o
1
2
DMA
1
INTO
INTl
INT3
NMI
INTERRUPT
REQUEST REG.
INTERRUPT
MASK REG.
OMAO
CONTROl REG.
DMAl
CONTROL REG,
EXT. INPUT 0
CONTROL REG.
EXT. INPUT 1
CONTROL REG,
INT2
IN·SERVICE
REG.
INTERRUPT
PRIORITY
RI!SOLVER'
PRIOR. LEY.
MASK REG.
INTERRUPT
STATUS REG,
EXT.INPUT 2
CONTROL REG,
Figure 21. Interrupt Controller Block Diagram
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IAPX 188
Special Fully Nested Mode
.This mode is entered by setting the SFNM bit in INTO
or INn control register. It enables complete nestability with external 8259A masters. Normally, an interrupt request from an interrupt source will not be
recognized unless the in-service bit for that sou~ce is
reset. If more than one interrupt source is connected
to an external interrupt controller, all of the interrupts
will be funneled through the same 80188 interrupt
request pin. As a result, if the external interrupt controller receives a higher-priority interrupt, its interrupt will not be recognized by the 8.0188 controller
until the 80188 in-service bit is reset. In special fully
nested mode, the 80188 interrupt controller will allow
interrupts from an 'external pin regardless of the
state of the in-service bit for an interrupt source in
order to allow multiple interrupts from a single pin.
An in-service bit will continue to be set, however, to
inhibit interrupts from other lower-priority 80188 interrupt sources.
Non-iRMX Mode Features
Programmable Priority
The user can program the interrupt sources into any
of eight different priority levels. The programming is
done by placing a 3-bit priority level (0-7) in the
control register of each interrupt source. (A source
with a priority level of 4 has higher priority over all
priority levels from 5 to 7. Priority registers containing values lower than 4 have greater priority.) All
interrupt sources have preprogrammed default
priority levels (see Table 4).
If two requests with the same programmed priority
level are pending at once, the priority ordering
scheme shown in Table 4 is used. If the serviced
interrupt routine reenables interrupts, it allows other
requests to be serviced.
End·of-Interrupt Command
The end-of-interrupt (EOI) command is used by the
programmer to feset the In-Service (IS) bit when an
interrupt service routine is completed. The-EOI command is issued by writing the proper pattern to the
EOI register. There are two types of EOI commands,
, specific and nonspecific. The nonspecific command
does not specify which IS bit is reset. When issued,
the interrupt controller automatically resets the IS bit
of the highest priority source with an active service
routine. A specific EOI command requires that the
programmer send the interrupt vector type to the
Special procedures should be followed when resetting IS bits at the end of interrupt service routines.
Software polling of the external master's IS register
is required to determine if there is more than one bit
set. If so, the IS bit in the 80188 remains active and
the next interrupt service routine is entered .•
Operation in a Polled Environment
The controller may be used in a polled mode if interrupts are undesirable. When polling, the processor disables interrupts and then polls the interrupt controller
whenever it is convenient. Polling the interrupt controller is accomplished by reading the Poll Word (Figure
31). Bit 15 in the poll word indicates to the processor
that an interrupt of high enought priority is requesting
service. Bits 0-4 indicate to the processor the type vector of the highest-priority source requesting service.
'Reading the Poll Word causes the In-Service bit of the
highest-priority source to be set.
interrupt controller indicating which source's IS bit is
to be reset. This command is used when the fully
nested structure has been disturbed or the highest
priority IS bit that was set does not belong to the
service routine in progress.
Trigger Mode
The four external interrupt pins can be programmed
in either edge- or level-trigger mode. The control
register for each external source has a level-trigger
mode (LTM) bit. All interrupt inputs are active HIGH.
In the edge sense mode or the level-trigger mode, the
interrupt request must remain active (HIGH) until the
interrupt request is acknowledged by the 80188 CPU.
In the edge-sense mode, if the level remains high
after the interrupt is acknowledged, the input is disabled and no further requests will be generated. The
input level must go LOW for at least one clock cycle to
reenable tne input. In the level-trigger mode, no such
provision is made: holding the interrupt input HIGH
,will cause continuous interrupt requests.
It is desirable to be able to read the Poll Word information without guaranteeing service of any pending
interrupt, i.e., not set the indicated in-service bit. The
80188 provides a Poll Status Word in addition to the
conventional. Poll Word to allow this to be done. Poll
Word information is duplicated in the Poll Status
Word, but reading the Poll Status Word does not set
the associated in-service bit. These words are located in two adjacent memory 10catio'1s in the regis·ter file.
3-467
!
AFN..Q1483A
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I"mer'
,
fAPX 188
Interrupt Vectoring
The 80188 Interrupt Controller will generate inter'rupt vectors for the integrated OMA channels and
the integrated Timers. In addition, the Interrupt Controller will generate interrupt vectors'for the external
interrupt lines if they are not configured in Cascade
or Special Fully Nested Mode. The interrupt vectors
generated are fixed -and cannot be changed (see
Table 4).
Interrupt Controller Registers
The Interrupt Controller register model is shown in
Figure 23. It contains 15 registers. All registers can
both be read or written unless specified otherwise.
In-Serv1ce Register
This register can be read from or written into. The
format is shown in Figure 24. It contains the InService bit for each of the interrupt sources. The
In-Service bit is set to indicate that a source's service
routine is in progress. When an In-Service bit is set,
the interrupt controller will not generate interrupts to
the CPU when it receives interrupt requests from
devices with a lower programmed priority level. The
TMR bit is the In-Service bit for ~II three timers; th,
DO and 01 bits are the In-Service bits for the two DMA
channels; the 10-13 are the In-Service bits for the
external interrupt pins. The IS bit is set when, the
prOcessor,acknowledges an interrupt request either
by an interrupt acknowledge or by reading the poll
register. The IS bit is reset at the end of the interrupt
service routine by ah end-of-interrupt command issued by the CPU.
80188
Interrupt Request Register'
The internal interrupt sources have interrupt request
bits inside the interrupt controller. The format of this
register is shown in Figure '24. A read from this register Yields the status of theSe bits. The TMR bit is the
logical OR of all timer interrupt requests. DO and 01
are
the interrupt request bits, for the OMA channels.
,
The state of the external interrupt inp\lt pins is also
indicated. The state of the external interrupt pins is
not a stored, condition inside the interrupt controller,
therefore the external interrupt bits cannot be written. The external interrupt request bits show exactly
when an'interrupt request is given to the interrupt
controller, so if edge-triggered mode is selected, the
bit in the register :.viii be HIGH only after an inactiveto-active transition. For internal interrupt sources,
the register bits are set whena request arrives and
.are reset when the processor acknowledges the
requests.
Mask Register
This is a 16-bit register that contains a mask bit for
,each interrupt source. The format for this register is
shown in Figure 24. A one in a bit position corresponding to a particular source serves to mask the
source from generating interrupts. These mask bits
are the exact same bits which are used in the individual control registers; programming a mask bit using
the mask register will also change this bit in the
individual control registers, and vice versa.
INTO
INT
8259A
PIC
IRTXii
rNTA
Figure 22. Cascade Mode Interrupt Connection
3-468
AF~1483A
inter
IAPX 188
Pr.lorlty Mask Register
This register is used to mask all interrupts below
particular interrupt priority levels. The format of this
register is shown in Figure 25. The code in the lower
three bits of this register inhibits interrupts of
priority lower (a higher priority number) than the
code specified. For example. 100 written into this
register masks interrupts of level five (101). six (110).
and seven (111). The register is reset to seven (111)
upon RESET so all interrupts are unmasked.
OFFSET
INT3 CONTROL REGISTER
3EH
INn CONTROL REGISTER
3CH
INn CONTROL REGISTER
3AH
INTO CONTROL REGISTER
38H
DMA 1 CONTROL REGISTER
38H
DMA 0 CONTROL REGISTER
34H
TIMER CONTROL REGISTER
32H
INTERRUPT STATUS REGISTER
30H
INTERRUPT REQUEST REGISTER
2EH
IN·SERVICE REGISTER
2CH
PRIORITY MASK REGISTER
2AH
MASK REGISTER
28H
POLL STATUS REGISTER
26H
POLL REGISTER
24H
EOI REGISTER
22H
Interrupt Status Register
This register contains general interrupt controller
status information. The format of this register is
shown in Figure ,26. The bits in the status register
have the following functions:
DHLT:
DMA Halt Transfer; setting this bit halts all
DMA transfers. It is automatically set
whenever a non-maskable interrupt occurs.
and it is reset when an IRET instruction is
executed. The purpose of this bit is to allow
prompt service of all non-maskable interrupts. This bit may also be set by the CPU.
IRTx:
These thr~e bits represent the individual
timer interrupt request bits. These bits are
used to differentiate the timer interrupts.
since the timer IR bit in the interrupt re.Jest register is the "OR" function of all
timer interrupt requests. Note that setting
anyone of these three bits initiates an interrupt request to the interrupt controller.
Figure 23. Interrupt Controller Registers
(Non-iRMX 86 Mode)
15
14
10
o
0
o
I
9
8
7
0
o
)3
6
4
3
2
1
0
Figure 24. In-Service, Interrupt Request, and Mask Register Formats
15
o
14
I
0
3
I
2
1
0
2
1
0
Figure 25. Priority Mask Register Format
15
14
7
o
I
•
0
I
0
4
3
oI
0
IIRT211RTlIIRToi
Figure 26. Interrupt Status Register Format
3-469
AFN-01483A
inter
IAPX 1pa
level is preceded by an inactive-to-active
transition on the line. In both case.s, the
level must remain active until the interrupt
is acknowledged.
Timer, DMA 0, 1; Control Registers
These registers are the control words for all the internal interrupt sources. The format for these registers
is shown in Figure 27. The three bit positions PRO,
PR1, and PR2 represent the progr·ammable priority
level of the interrupt source. The MSK bit inhibits
interrupt requests from the interrupt source. The
MSK bits if! the individual control registers are the
exact same bits as are in the Mask Register; modifying them in the individual control registers will also
modify them in the Mask Register, and vice versa.
INTO-INT3 Control Registers
These registers are the control words for the four
external input pins. Figure 28 shows the format of the
INTO and INT1 Control registers; Figure 29 shows the
format of the INT2 and INT3 Control registers. In .
cascade mode or special fully nested mode, the control words for INT2 and INT3 are not used.
MSK:
Mask bit, 1 = mask; 0 = nonmask.
C:
Cascade mode bit, 1
SFNM:
Special fully nested mode bit, 1
= cascade; 0 = direct
=
SFNM
EOI Register
The end of the interrupt register is a command register which can only be written into. The format of this
register is shown in Figure 30. It initiates an EOI
command when written to by the 80188 CPU.
The bits in the various control registers are encoded
as follows:
The bits in the EOI register are encoded as follows:
PRO-2:
Priority programming information. Highest
priority
000, lowest priority
111.
Sx:
LTM:
Level-trigger ,mode bit. 1 = level-triggered;
o = edge-triggered. Interrupt Input levels
are active high. In level-triggered mode, an
interrupt is generated whenever the externalline is high. In edge-triggered mode, an
interrupt will be generated only when this
=
15
=
Encoded information that specifies an interrupt source vector type as shown in
Table 4. For example, to reset the In-Service
bit for DMA channel 0, these bits should be
set to 01010, since the vector type for DMA
channel 0 is 10. Note that to reset the single
In-Service bit for any of the three timers, the
vector type for timer 0 (8) should be written
in this register.
14
0
o
3
2
1
0
I
~----------------------------------------------------------------~
Figure 27. Timer/DMA Control Register Formats
15
o
I
14
7
0
o
6
ISFNMI
5
c
4
3
I LTMIMSKI
2
1
0
PR21 PRll PRO
I
Figure 28. INTO/INT1 Control Register Formats
15
o
I
14
4
o
0
3
I LTM I MSKI
2
1
0
PR21 PR11 PRO
I
Figure 29. INT2/INT3 Control Register Formats
3-470
AFN-Q1483A
inter
IAPX 188
NSPEC/: A bit that determines the type of EOI comSPEC mand. Nonspecific = 1, Specific = O.
Because of pin limitations caused by the need to
interface to an external 8259A master, the internal,
interrupt controller will no longer accept external
inputs. There are however, enough 80188 interrupt
controller inputs (internally) to dedicate one to each
timer. In this mode, each timer interrupt source has
its own mask bit, IS bit, and control word.
Poll and Poll Status Registers
These registers contain polling information. The format of these registers is shown in Figure 31. They can
only be read. Reading the Poll register constitutes a
software poll. This will set the IS bit of the highest
priority pending interrupt. Reading the poll status
register will not set the IS bit of the highest priority
pending interrupt; only the status of pending interrupts will be provided.
The iRMX 86 operating system requires peripherals
to be assigned fixed priority levels. This is incompatible with the normal operation of the 80188 interrupt controller. Therefore, the initialization software
must program the proper priority levels for each
source. The required priority levels for the internal
interrupt sources in iRMX mode are shown in Table
16.
Encoding of the Poll and Poll Status register bits are
as follows:
Sx:
Encoded information that indicates the
vector type of the highest priority interrupting source. Valid only when INTREO = 1.
Table 16. Internal Source Priority Level
INTREO:This bit determines if an interrupt request is
present. Interrupt Request = 1; no Interrupt
Request = O.
Priority Level
0
1
2
3
4
5
iRMX 86 COMPATIBILITY MODE
This mode allows iRMX 86-80188 compatibility. The
interrupt model of iRMX 86 requires one master and
multiple slave 8259As in cascaded fashion. When
iRMX mode is used, the internal'80188 interrupt controller will be used as a slave controller to an external
master interrupt controller. The internal 80188 resources will be monitored through the internal interrupt controller, while the external controller
functions as the system master interrupt controller.
Interrupt Source
Timer 0
(reserved)
DMAO
DMA1
Timer 1
Timer 2
These level aSSignments must remain fixed in the
iRMX 86 mode of operation.
iRMX 86 Mode External Interface
The configuration of the 80188 with respect to an
external 8259A master is shown in Figure 32. The
INTO input is used as the 80188 CPU interrupt input.
INT3 functions as an outpu~ to send the 80188 slaveinterrupt-request to one of the 8 master-PIC-inputs.
Upon reset, the 80188 interrupt controller will be in
the non-iRMX 86 mode of operation. To set the controller in the iRMX 86 mode, bit 14 of the Relocation
Register should be set.
/
15
1:;:e~1
14
0
13
I
0
Figure 30. EOI Register Format
15
14
13
. Figure 31. Poll, Register Format
3-471
AFN-Il1483A
inter
iAPX 188
8259A
MASTER
INTA
80188 INT. IN
~REQUESTSFROM
'-.....--OTHER SLAVES
IRO
INT
1
IR7
r:.
CASO-2
80188
INTO
INTI
I
L
SLAVE SELECT
1\
CASCADE
ADDRESS DECODER
INT2 I - INT3
80188 SLAVE INTERRUPT OUTPUT
l
Figure 32. iRMX 86 Interrupt Controller Interconnection
Correct master-slave interface requires decoding of
the slave addresses (CASO-2). Slave 8259As do this
internally. Because of pin limitations, the 80188 slave
address will have to be decoded externally. INT1 is
used as a slave-select input. Note that the slave vector .address is transferred internally, but the READY
input must be supplied externally.
INT2 is used as an acknowledge.output, suitable to
drive the iNiA input of an 8259A.
Specific End-of-Interrupt
In iRMX mode the specific 1;'01 command operates to
reset an in-service bit of a specific priority. The user
supplies a 3-bit priority-level value that points to an
in-service bit to be reset. The command is executed
by writing the correct value in the Specific EOI register at offset 22H.
Interrupt Controller Registers
in the iRMX86 Mode
Interrupt Nesting
iRMX 86 mode operation allows nesting of interrupt
requests. When an interrupt is acknowledged, the
priority logic masks off all priority levels except
those with equal or higher priority.
Vector Generation in the iRMX 86 Mode
Vector generation in iRMX mode is exactly like that of
an 8259A slave. The interrupt controller generates an
B-bit vector which the CPU multiplies by four and
uses as an address into a vector table. The significant
five bits of the vector are user-programmable while
the lower three bits are generated by the priority
logic. These bits represent the encoding of the
priority level requesting service. The significant five
bits of the vecto~ are programmed by writing to the
Interrupt Vector register at offset 20H. 3-472
All control and command registers are located inside
the internal peripheral control block. Figure 33
shows the offsets of these registers.
End-of-Interrupt Register
The end-of-interrupt register is a co.mmand register
which can only be written. The format of this register
is shown in Figure 34. It initiates an EOI command
when written by the 80188 CPU.
The bits in the EOI register are encoded as follows:
Lx:
Encoded value indicating the priority of the
IS bit to be reset.
In-Service Register
This register can be read from or written into. It
contjiins the in-service bit for each of the internal
AFN..Q1483A
intJ
IAPX 188
interrupt sources. The format for this register is
shown in Figure 35. Bit positions 2 and 3 correspond
to the DMAchannels; positions 0, 4, and 5 correspond to the integral timers. The source's IS bit is set
when the, processor acknowledges .its interrupt request.
prx:
3-bit encoded field indicating a priority level
for the source; note that each source must
be programmed at specified levels.
msk:
mask bit for the priority level indicated by prx
bits.
OFFSET
Interrupt Request Register
This register indicates which internal peripherals
have interrupt requests pending. The format of this
register is Shdwn in Figure 35. The interrupt request
bits are set when a request arrives from an internal
source, and are reset when the processor acknowledges the request.
Mask Register
This register contains a mask bit for each interrupt
source. The format for this register is shown in Figure 35. If the bit in this register corresponding to a
particular interrupt source is set, any interrupts from
that source will be masked. These mask bits are
exactly the same bits which are used in the individual
control registers, i.e., changing the state of a mask
bit in this register will also change the state of the
mask bit in the individual interrupt contrQI register
corresponding to the bit.
3AH
LEVEL 4 CONTROL REGISTER
(TIMER 1)
38H
LEVEL 3 CONTROL REGISTER
(DMA1)
38H
LEVEL 2 CONTROL REGISTER
(DMAO)
34H
LEVEL 0 CONTROL REGISTER
(TIMER 0)
32H
INTERRUPT STATUS REGISTER
30H
INTERRUPT REQUEST REGISTER
2EH
IN·SERVICE REGISTER
Control Registers
These registers are the control words for all the internal interrupt sources. The format of these registers is
shown in Figure 36. Each of the timers and both of
the DMA channels have their own Control Register.
The bits of the Control Registers are encoded as
follows:
LEVEL 5 CONTROL REGISTER
(TIMER 2)
2CH
PRIORrrY·LEVEL MASK REGISTER
2AH
MASK REGISTER
28H
SPECIFIC EOI REGISTER
22H
INTERRUPT VECTOR REGISTER
2DH
Figure 33. Interrupt Controller Registers
(iRMX 86 Mode)
1 : 1 : 1 : 1 : 1: 1 : 1
~
1 ,: I : ° 1
Figure 34. Specific EOI Register Format
1: 1 : 1:
H":'I ~
1
~
1 : 1":'1
Figure 35. In-Service, Interrupt Request, and Mask Register Format
3-473
AFN...Q1483A
"<, '
IAPX188
Interrupt Vector Register
This register provides the upper five bits of the interrupt vector address. The format of this register is
shown in Figure 37. The interrupt controller itself
provides the lower three bits of the interrupt veotor
as determined by the priority level of the interrupt
request.
Interrupt Controller and Reset
,
,
•
,"
!
Upon RESET, the interrupt controller \Viii perform the
following actions:
• All SFNM bits reset to 0, implying FUlly' Nested
Mode.
• All PR bits in the various control registers set to 1.
This places all sources at lowest priority (ievel
111).
. '
• All LTM bits' ~eset to 0, resulting in' ~dge-sense
The format of the bits in this register is:
tx :5-bit field indicating the upper five bits of the
vector address.
Priority-level Mask Register
This register indicates the lowest priority-level interrupt which will be serviced.
mode.
All Interrupt Service bits reset to O.
All Interrupt Request bits reset to '0.
All MSK (Interrupt Mask) bits set to 1 (mask).
All q (Cascade) bits reset to 0 (non-cascade). '
All PRM (Priority Mask) bits 'set to 1, implying no
levels masked.
..,
• Initialized to non-iRMX 86 mode.
•
•
•
•
•
The encoding of the bits in this register is:
mx:
."'
"
3-bit encoded field'indication priority-level
value. All levels of lower priority will be
masked.
.
Interrupt'Status Register
This register is defined exactly as hi non-iRMX mode
(see Figure 26).
I:I:I:I:I:I':'H ~ H
Figure 38. Control Word Formllt
Figure 37. Interrupt Vector Register Format
Figure 38. Priority' Level Mask Register
3-474
AFN.()1483A
..
IAPX 188
16 MHz
Vcr.
~
.;-
rD1
Xl
X2
UCS
~
RES
ADo-AD7, ....
All-A15
ALE
-'-<-
8282 OR
8283
f~'
~'~
STB
,
RESET
ROM
ADORESS
-
OE
80166
I
{f
{
liD
Wli
r
I
~3
SRDY
PROGRAM
RAM
tr~5V
ARDY
NMI
HOLD
h
h
~
t--
~
TMRINO
LOW RAM
II
I
f---- ~5V
TMR OUT 0
(
t
82116 OR
~
CLOCK
s;
8287
~
~ TRANSCEIVER ~ DO-D7
TERMINAL
SERIAL
m
Al
~ )-
T
OE
'liD
---1
A2
I
INTO
DISK
INTERFACE
HARDWARE
INTl
~8DISK
PCS4
,DRQa
Figure 39. TypicallAPX 188 Computer
3-475
AFN-Q1483A
inter
IAPX'188
16 MHz
~D~
Vee
f1
Xl
X2
UCS
CS
AD
uI
REI
.l
~
8282 OR
8283
lATCH
STB
OE,
DE
STB
•
ALE
LCS
RESET
ROM
-;:-
rLb
V'f'.-
lOW
RAM
CS
WR
/\
ADCl-AD7
AS-.!'15
b
~
--'
> ADDRESS
-v BUS
8282 OR
8283
lATCH
STB
OE
~~STB
i5!
,
80188
NMI
HOLD
~
'-~
t
8286 OR
8287
TRANSCEIVER
T
DATA BUS
~
1
I
,
MULTI
MAST ER
SYST EM
BUS
DTIR
ClK
' - - ALE
ClKOUT
,....,
SO-S2
--
DEN
8288
SO-82 BUS
CONTROLLER
I----- CEN
lOB
-;:-
> BUS CONTROL
COMMANDS
AEN
1
I
~
PCSo
PCSl
lOCK
SRDY
ARDY
L--f
SO-S2
AEN
8289
SYSBIRru
J
lOB
FD-r-&=
[
> ~~~T+~~~ION
ClK AR'::feR
"'\
i:OCK
RESB
;l. -5V
""l
XACK
Figure 40. TypicallAPX 18aMu"I-Maater Bua interface
3-476
AFN-Q1483A
IAPX188
PACKAGE
The 80188 is housed in aS8-pin, leadlessJEOECtype
A hermetic chip cartier. Figure 41 illustrates the
package dimensions.
NOTE: The lOT 3M Textool 68-pin JEOEC Socket
is required for ICE™ operation. See Figure 42 for
details.
~-----ilG+~~~M[OJ-----1
*
Figure 41. 80188 JEDEC Type A Package
3-477
AFN~1483A
IAPX 188
GUIDE BOSS
-I
--';:j~)so----
:-
3 !'Les ~ r-lIrre:J'lXa::HX!OIl!:B:lD!XEOIl!l::BlF"'('n
r+,
-----;-+-1------.... 4- /,
•. ~
I
_'1\:1,I
PC BOARD PATTERN
'
'
'j
•
~-
FRONT
,
SOCKET ORIENTATION PIN
JPlNNOl
INDEX
~..,...
'-
~~~t~t~t\-:'fi1.
~EK,.e;ATloN .r:I
l:/
FRONT
PIN CLR HOLE".,.--;i •
OEVICE PADS
FOR I .021 CIA .r:1
1 00
SHOWN FOR -E/7+(o'74)-.r:1-~ CONTACT
.r:1
"~.O)
LOCATION ~ I
.r:1 ~:) TVP
• •
f.-j
E>
I
ALUMINUM LID
(HEATSINK PROVISIONS OPTIONAL)
'rEST PROBE POINT
\
~::~A~~T ~)s~~)~~~~.:!-l
CO.~
1ti
L
.020:J
(0.51)
CONTACT TAIL
I
Jo --=:.r (fii)
\
TVP
OPEN
,,0.32)
spes • .J!!!.TOl NON ACCUM TVP ,
PLes
,UO)
NOTE: Phyelcal dlmenltonlMown .... for reference onlJ. PIeaIe conl.1t 3M TtxtooI tor comP.... inlonMtion on the IIOCbt.
Figure 42. Textool 68 Lead Chip Carrier Socket
3-478
AFN.QI483A
intJ
IAPX 188
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature under Bias· ..... O°C to 70°C
Storage Temperature ........... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .............. -1.0V to + 7V
Power Dissipation ........................ 3 Watt
D.C. CHARACTERISTICS (TA - 0°-70°C. Vee - 5V
Symbol
Parameter
<
*NOTlCE: Stresses above those listed under
"Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
10%)
Min.
Max.
Units
- 0.5
+0.8
Volts
Vee + 0.5
Volts
Vee + 0.5
Volts
0.45
Volts
Output High Voltage
2.4
Volts
Power Supply Current
550
450
rnA
Max measured at TA _ O°C
TA _ 70°C
VIL
Input LowVoltage
VIH
Input High Voltage
(All except X1 and (~)
VIH1
Input High Voltage (RES)
VOL
Output Low Voltage
VOH
Icc
2.0
3.0
Test Conditions
la - 2.5 rnA for 'Sl:)-~
la - 2.0 rnA for all other outputs
loa - -400 /LA
lu
Input Leakage Current
±10
~
OV
ILO
Output Leakage Current
±10
/LA
0.45V
VCLO
Clock Output Low
0.6
Volts
la - 4.0 rnA
Volts
loa - -200~
VCHO
Clock Output High
Veu
Clock Input Low Voltage
-0.5
VCHI
Clock Input High Voltage
3.9
CIN
Input Capacitance
Cia
1/0 Capacitance
4.0
0.6
Volts
Vcc+1.0
Volts
10
pF
20
pF
VIN
<
<
<
Vee
Vour
<
Vec
PIN TIMINGS
A.C. CHARACTERISTICS (TA = 0°-70°C, Vee = 5V ± 10"10)
80188 Timing Requirements All Timings Measured At 1.5 Volts Unless Otherwise Noted.
Symbol
Parameter
Min.
Max.
Units
TDVCL
Data in Setup (AID)
20
ns
TCLDX
Data in Hold (AID)
10
ns
TARYHCH Asynchronous Ready
(AREADY) active setup
time*
20
ns
TARYLCL AREADY inactive setup
time
35
ns
15
. ns
35
ns
TCHARYX AREADY hold time
TSRYCL
Synchronous Ready
(SREADY) transition setup
time
TCLSRY
SREADY transition hold
time
15
ns
THVCL
HOLD Setup'
25
ns
TINVCH
INTR, NMI, TEST, TIMERIN,
Setup'
25
ns
TINVCL
DRQO, DRQ1, Setup'
25
ns
Test Conditions.
*To guarantee recognition at next clock.
3-479
AFN-01483A
IAPX 188
A.C. CHARACTERISTICS (Continued)
,
,
'
80188iMaster Interface Timing Re$ponses
80188 (8 MHz)
Symbol
Parameters
Min.
TcLAV
Address Valid Delay
5
TClAX
Address Hold
10
TClAZ
Address Float Delay
TCHCZ
Command Unes Float Delay
TCHCV
Command Lines Valid Delay
(after float)
TLHll
ALE Width
TCHLH
ALE Active Delay
TCHll
ALE Inactive Delay
TllAX
Address Hold to ALE Inactive
TClOV
Data Valid Delay
10
TClOOX
Data Hold Time
10
80188-6 (6 MHz)
Max.
Min.
Max.
Units
44
5
63,
ns
35
TClA)(
44
ns
56
ns
76
ns
44
ns
ns
10
TClAX
45
55
TClCl-35
ns
TCLCl-35
35
35
44
TCHCl-25
10
ns
ns
TCHCl-30
44
55
ns
ns
10
TWHDX
Data Hold after WR
TCVCTV
Control Active Delay 1
5
70
5
87
ns
TCHCTV
Control Active Delay 2
10
55
10
76
ns
TCVCTX
Control Inactive Delay
5
55
5
76
ns
TCVDEX
DEN Inactive Delay
(Non-Write Cycle)
87
ns
TAZRl
Address Float to RD Active
0
TClRl
RD Active Delay
10
70
10
87
ns
10
55
10
76,
ns
50
TClCl-50
10
TCLCl-40
ns
TCLCl-50
itO
0
ns
TCLRH
RD Inactive Delay
TRHAV
RD Inactive to Address Active
TCLHAV
HlDA Valid Delay
TClCL-40
10
TRlRH
RD Width
2TclCl_50
2TCLCL-50
ns
TWLWH
WRWidth
2TCLCl-40
2TclCL-40
ns
TAVAl
Address Valid to ALE Low
TCLCH-25
TCLCH-45
TCHSV
Status Active Delay
10
55
10
76
ns
TCLSH
Status Inactive Delay
10
55
10
76
ns
TClTMV
Timer OU1Put Delay
60
75
ns
TClRO
Reset Delay
60
75
ns
TCHQSV
Queue Status Delay
35
44
ns
Max.
Units
80
ns
80188 Chip-Select Timing Responses
Symbol
Parameter
Min.
"
TCLCSV
Chip-Select Active Delay
Tcxcsx
Chip-Selct Hold from
Command Inactive
35
TCHCSX
Chip-Select Inactive Delay
5
Max.
.
Min.
66
ns
67
5
3-480
ns
ns
35
35
1est Conditions
Cl = 20-200 pF all outputs
100 pF max
Test Conditions
ns
47
ns
AFN-01483A
inter
IAPX 188
A.C. CHARACTERISTICS (Continued)
i80188 ClKlN Requirements
80188 (8 MHz)
Symbol
TCKIN
Parameters
ClKIN Period
80188-6 (6 MHz)
Min.
Max.
Min.
Max.
UniIB
62.5
250
83
250
ns
Test Conditions
TCKHl
ClKIN Fall Time
10
10
ns
3.5 to 1.0 volts
TCKLH
ClKIN Rise Time
10
10
ns
1.0 to 3.5 Yolts
TCLCK
CLKIN low Time
25
33
ns
1.5 Yolts
TCHCK
CLKIN High Time
25
33
ns
1.5 Yolts
80188 CLKOUT Timing (200 pi: load)
Symbol
Parameter
TclCO
ClKIN to ClKOUT Skew
Min.
Max.
Min.
50
Max.
Units
62.5
ns
Test Conditions
TCLCl
ClKOUT Period
TClCH
CLKOUT low Time
TCHCl
ClKOUT High Time
TCH1CH2
ClKOUT Rise Time
15
15
ns
1.0 to 3.5 Yolts
TCL2Cll ~
ClKOUT Fall Time
,15
15
ns
3.5 to 1. Yolts
125
500
\2 TClCl-7.5
\2 TCLCL-7.5
167
500
ns
\2 TClCl-75
ns
1.5 volts
\2 TCLCl-7.5
ns
1.5 volts
3-481
AFN-01483A
int..... f,,
IAPX 188
~.,'I~
WAVEFORMS
MAJOR CYCLE TIMING
VCH
T,
~J
r--\
CLKOUT
..."".
-y;;'TCHS,i-
SMO
\
Tel ~AV_
II_rc
TCH~
'T
~
At-~
WRITE CYCLE
AwAe
I
A7,100
I
A,;-Ae
I~
-'l-
DT/R
INTA
= VOH
-
-
DATAOU1
LCS,
MCS
~OX
V-
ro- TCLAZ
\
TCHCTV
~
"c1
~--
.
/
r-
A_no /'I~
~
\.
- ~. I
j
:CLDX
I FLOAT
1- .~"'"
l-
I
I
A
V
NOTE 2
[j
1-/
.
TCLAV_
-
t'I';;=-
II
,
rJ
I
-
+-.-
TCLAZ_
-
DEN
POS,
MCS
1
'I
TLLAl
,~.~
SOF'!!'[ARE HALT-DE~ =Volo
RD. WR. INTA. DT/R = VOH
f-.
I\-
FLOAT
...:::::;......,.1...
INTA CYCLE
RD. WR
-
~
r-' TCHCZ
--
.
.~,~
AD7Ao,
A15"Ae
-
I:::
DEN
,
\\.
~~
Rii.INTA.
DT/R = VOH
WIi
("-"'\
s,,-S3
A1D-A,S
:~~t~ ::
i:u~
-
rCLD1 ::::
I.AX::::
1- - T iw,
ALE
I-"W
j-
,
W'
• A,./s"-A,,/S,
.
,
:3)1~
t~7.d;
T.
T~Ii:~-
I_T,., 1"'
INVAUD ADDRESS
1-
_TCLCSV
3-482
TCXCSX-
f--
AFN-ol483A
iAPX 188
WAVEFORMS (Continued)
MAJOR CYCLE TIMING (Continued)
CLKOUT
A19/S6-Al61S3
ALE
TCHLH
AD,-ADo
READ CYCLE
DT/A
PCS,
MCS --------+_~
LCS,
MCS
'l-.OTES
1 Following a Wrtte cycle, the Local Bus IS floated by the 80188 only when the
80188 enters a "Hold Acknowledge" state
INTA occurs one clock later In RMX~mode
Status inactIve lust prtor to T4
3-483
AFN-01483A
iAPX 188'
WAVEFORMS (Continued)
ClKOUT
-
TClAV
TClAV
-
CLKOUT
TINVCl-
-
M+.
INTO-3,
TIMERIN:--_ _ _ _ _ _--.J
,
CLKOUT
QSO, QS1
3-484
AFN-Q1483A
IAPX 188
WAVEFO.RMS (Continued)
HOLD-HLDA TIMING
T,
T,
CLKOUT
ARDY
TARYLCL-
_
CLKOUT
CLKOUT
HLDA
AD7-ADO,
A15-AS
)---
80186
--~
__ J
jjHi
A19/S6-A161S3,
iiii,WR,
57,
DT/ii,
TCHCV
.
80186
}---
--,
__ J
r-
rTCLAV
80186
80186
52-SO
3-'485
AFN-014B3A
IAPX 188·
WAVEFORMS (Continued)
TIMER ON 80188
!---TCKIN---'!-
ClKIN
TCKHl
TCKlH
TCHICH2
'k'"----TClCH---+O.,j4---TCHCl----ri->\o..
ClKOUT
i--------TClCl
-------+1
I
~
TINVCH
TIMERIN
K".'~
TIMEROUT _ _
::~~~~~~~~~~~~~~~~~~~~~~~_2_-_6C_l_O_C_KS_ _ _ _ _ _-..,._ _ _ _---'l_ _~
I~cated
80188 INSTRUCTION TIMINGS
• All word-data is
boundaries.
The following instruction timings represent the minimum execution time in clock cycles for each instruction. The timings given are based on the following
assumptions:
All jumps and calls include the time required to fetch
the opcode of the next instruction at the destination
address.
• The opcode, along with any data or displacement
required for execution of a particular instruction,
has been prefetched and resides in the queue at
the time it is needed.
• No wait states or bus HOLDS occur.
All instructions which involve memory reference can
require one (and in some cases, two) additional
clocks above the minimum timings shown. This is
due to the asynchronous nature of the handshake
between the BIU and the Execution unit.
, 3486
on even-address
AFN-01483A
inter
IAPX 188
INSTRUCTION SET SUMMARY
fUNCTION
Clock
Cycle.
FORMAT
Comments
DATA TRANSFER
MOV=Mon:
Register to RegISter/Memory
1'000'00w
mod reg
rim
Reglste"memory to register
1'000'0'W
mod reg
rim
modOOO
rim
Memory to accumulator
l'
l'
I'
Accumulator to memory
1'0'000'W
Immediate to reglsterlmemory
Immediate to register
Reglsterlmemory to segment register
Segment register 10 reglste[lmemory
PUSH = Push:
Memory
l'
l'
100011 w
01 1 w reg
l'
Register
10 1 0 1 1
Segment register
10 0 0 reg
IN = Input lrom:
FIXed port
vanable port
OUT = Output 18:
FIXed port
l'
l'
l'
l'
addr·low
addr·hlgh
mod 0 reg [1m
POP = Pop:
Memory
Register wllh accumulator
addr·hlgh
00 0 1 1 0 0
10 00 reg
leHG = b1:hlnge:
Register/memory with register
addr·low '
mod 0 reg rim
Segment register
'1
modll0 rim
I
11 0I
I
I
11 1I
00 0 1 1 1 1
reg
0000,11 wi
00 1 0
modOOO [1m
[1m
mod reg
1 1 0 1 lOw
LES = Load pOinter to ES
1'1000100
mod reg
[1m
SAHF ~ Store AN Into flags
PUSHF = PuSh flags
POPF ~ Pop lIags
,
I
20
I
24
14
12
I
4/17*
10*
I
[1m
l'
l'
l'
l'
S*
S*
mod reg
LAHF ~ Load AH with flags
8116-bit
,
10 0 0 1 0 1
LEA ~ Load EA to register
8116-blt
12-13'
3-4
g*
2113
2115
I
I
LOS ~ Load pOinter to OS
ILAT ~ Translate byte to AL
I
3
port
110010 wi
datalfw~1
(reg*OI)
I
reg
I
I
I
I
14
13
l'
l'
l'
l'
l'
vanable port
2Ig'
datalfw-l
00 0 1 1 1 0
1""'"
10 1 0 1 0 reg
2112'
data
data
0 1 1i 0 00 w
Register
I
1 1 00 1 1 w
port
g*
7"
1101 11 w
10 1 0 11 1
00 0 1 1 0 1
modre!!
[1m
I ,
I (mod" 11)
I (mod" 11)
15
6
26
26
00 1 1 1 1 1
2
00 1 1 1 1 0
3
00 1 1 1 0 0
13
001110
q
12
.,"
8E8I1E11T =Segment OVerride
I
I
CS
100 1 0 1 1 1 0
55
1001 10 1 1 0
os
1001 1 1 1 1 [ ]
ES·
10 0 I' 0 0 1 1 0
I
2
2
2
,
..
,
2
"
Shaded areas Indicate Instructions nl>t available In IAPX 86, 88 mlcrbsystems,
"Note: Clock cycles shown for byte t(an'sfer, For word operations,'adci' 4 Clock cycles for all memory transfers,
.
'3-487
.
IAPX 188
INSTRUCTION SET SUMMARY (Continued)
FUNCTION
ARITlfMETIC
ADD = Add:
Reglmemory with register to either
10 00 0 0 0 d wi
Immediate to reglster:memory
1100000swi modOOO rm
Immediate to accumulator
10000010wl
mod reg
rm
data
ADC = Add with earry:
Reglmemory with register to either
10 00 tOO d wi
Immediate to reglste"memory
1100000swi mod 0 10 r:m
Immediate to accumulator
10 00 1 0 lOw
I
mod re2
rm
data
INC = Increment:
Register/memory
11 '11111 wi
reg
I
I
I
I
I
I
modOOO r'm
I
mod reg
rim
modl0l
r'm
I
I
I
I
Register
10 1 0 0 0
SUB = Sublfact:
Reg/memory and reglsterto either
10 0 1 0 1 0 d wi
Immediate from reglsterlmemory
11 OOOOOs wi
Immediate from accumulator
10010110wl
data
S88 = Sublfact with borrow:
Reg/memory and register to Mher
10 00 1 1 0 d wi
mod reg
rm
Immediate from register/memory
1100000swi
modOll
rim
Immediate from accumulator
10 00 1 1 lOw
I
data
DEC = Decrement:
Register/memory
Clock
Cycles
Comments
I
3/10'
4/16"
3/4
8116-blt
I
3/10"
4/16'
3/4
8/16-bit
FORMAT
I
I
I
data
datalfw~1
data
datalf w ~ 1
I
I
datall s W- 01
I
I
datalfsw~OI
3/15"
3
data
datalf w - 1
data
datalfw = 1
I
I
datalfsw~OI
I
I
datalfsw~OI
I
3/10'
4/16'
3/4
8116-bit
I
3/10"
4/16"
3/4
8116-bit
11 111111 wi
reg
modOOl
r:m
I
Register
10 1 0 0 1
3/15'
3
CMP = Compare:
Register/memory With register
10 01 1 1 01 wi
mod reg
r:m
Register With register/memory
10011100wl
mod reg
rim
rim
I
I
I
I
I
3/10"
3/10'
3/10'
3/4
3
8
4
7
4
I
Immediate With register/memory
1100000swl
mod 111
Immediate With accumulator
10 01 1 1 lOw
I
data
NEG = Change sign
11 11 1 011 wi
modOll
AM = ASCII adlust for add
10 0 1 1 0 1 1 1
DAA = DeCimal adlust for add
rim
I
AAS = ASCII adlust for subtract
10 0 1 0 0 1 1 11
10 01 1 1 11 11
PAS = DeCimal adlust for subtract
10 0 1 0 1 1 1 11
MUL = Multiply (unsigned)
Register-Byte
Register-WOrd
Memory-Byte
Memory-WOrd
11 t'1 1011 wi
mod 100 rim
IMUL = Integer multiply (signed)
Register-Byte
Register-WOrd
Memory-Byte
Memory-WOrd
11 11 1011 wi
mod 101
11 1 1 1 0 1 1 wi
mod 11 0 rim
rim
data
datalfw=1
I
I
I
I
dat.,fs w - 0 1
I
8116-bit
26-28
35-37
32-34
41-43"
25-28
34-37
31-34
40-43'
.'.'
DIV = Olvlde (unsigned)
Register-Byte
Register-Word
Memory-Byte
Memory-WOrd
I
29
38
35
44'
Shaded areas Indicate Instructions not available In IAPX 86,88 mlcrosystems.
"Note,: Clock cycles shown for byte transfer. For word ooerations, add 4 clock cycles for all memory transfers.
3488
AFN-oI483A
IAPX188
INSTRUCTION SET SUMMARY 'Ctlntlln ..,,"
Clock
Cycle.
FUNcnllN
FORMAT
IDi,; Integer divide (signed)
11 1 1 1 0 1 1 w
Register-Byte
Register-WOrd
Memory-Byte
Memory-WOrd
MM; ASCII adlustfor multiply
I
mod 111
r'm
Comments
44-52
53-61
50-58
59-67"
19
15
2
4
1110101001000010101
I 0 0 0 0 1 0 1 0I
I
1I
MD ; ASCII adlust for divide
\1
caw; Convert byte to word
11 00 1 1 00 0
CWO; Convert word to double word
11 00 1 1 00
1 0 1 0.1 0 1
LOGIC
SbIIllR..... lnstructlons:
Register/Memory by 1
2/15"
5+n/17+n"
Register/Memory by CL
m
Instruellon
ROL
001
"ROR
o 1 0 RCL
01 1
RCR
1 00 SHUSAL
1 01
SHR
1"1 1
SAR
o0 0
AND = AmI:
Reg/memory and register to either
10 0 1 0 0 0 d wi
mod reg
Immediate to reglsterlmemory
bOOOOOOwl
modl00 rim
data
Immediate to accumulator
I~ 01 0 0 lOw
data
datalfw-l
I
rim
datalfw~1
3/10'
4/16"
3/4
8116-bit
3/10'
4/10'
3/4
8116-bit
3/10'
4/16·
3/4
8116-bit
TEST = An.lunctlon 10 n•••. no ...ult:
Register/memory and register
11000010wl
Immediate data and reglsterlmemory
11 11 101 1 w
Immediate data and accumulator
11010100wl
OR=Or'
I
I
mod reg
rim
modOOO rim
data
data
datalfw ~ 1
Reg/memory and register to either
1000010d W
mod reg
rim
Immediate to register/memory
11000000wl
modOOl
rim
Immediate to accumulator
10 00 0 1 lOw
I
data
data
datalfw~1
datalfw= 1
datalfw-l
lOR = Exclusive or:
Reg/memory and register to BIther
1001100dwi
mod reg
Immediate to register/memory
11000000wl
modll0 rim
Immediate to accumulator
10011010wl
data
NOT = Invert register/memory
11 11 101 l' wi
modOl0 rim
rim
I
I
I
data
datalfw- 1
datalfw~
1
3/10·
4/16'
3/4
3.
8116-bit
STRING MANIPUlAnON'
MOYS; Move bytelWord
seAS ; Scan byt~/word
14*
22*
15'
LOOS ; Load byte/wd to AUAX
12*
CMPS ~ Compare byte/word
Shaded areas indicate instructions not available in iAPX 86. 88 microsystems.
"Note: Clock cy.cles shown for byte transfer. For word operations. add 4 clock cycles for all memory transfers.
,
\
3-489
iAPX 188
INSTRUCTION SET SUMMARY
FUNCTION
FORMAT
Repeated by count In ex
MOVS Move string
11 11 1 0 0 1
Ir"_.di_.
Clock
Cycles
11010010wl
CMPS
Compare strmg
11 11 1 0 0 1 zl1010011wl
SCAS
Scan stnng
11 11 1 0 0 1 z 11 0 1 0 1 1 1 wi
LOOS
Load strmg
11 11 1 0 0 1
Comments
8+8n'
5+22n'
5+15n'
6+11 n'
CONTROL TRANSFER
CALL=CaU:
Direct wlthm segment
Register memory
Indirect within segment
Direct Intersegment
11 1 1 0 1 0 0 0
11 111 111 1
11 00 1 1 0 1
I
I
I
I
dtsp·low
segment offset
11 111111 1
JMP = Uncondillonal Jump:
Short long
11 1 1 0 1 0 1 1
dlsp-Iow
Direct wlthm segment
11 1 1 0 1 0 0 1
dlsp-Iow
ReQlster memory indirect wlthm segment 11
Direct Intersegment
11
mod011rm
Indirect mtersegment
11 111111 1
RET = Return from CALL'
Wlthm segment
11 1 0 0 0 0 1 11
Within seg adding Immed to SP
11 1 0 0 0 0 1
Intersegment
11 1 0 0 1 0 1 1
Intersegmenl adding Immediate to SP
11 1 0 0 1 0 1
oI
31
(mod
= 111
dtSp-hlgh
modl00 rm
segment offset
54
13
13
11/21
13
segment selector
mod101rm
(mod = 111
data-low
dala-hlgh
data-low
data-high
I
oI
18
17/27
segment selector
Indirect mtersegment
I
I
111111
I
1 1 0 1 0 1 oI
I
dtSp-hlgh
modOl0rm
34
20
22
30
33
Shaded areas Indicate Instructions not availa.ble in IAPX 86.88 mlcrosystems_
.
'Note: Clock cycles shown for byte transfer. For word operations, add 4 clock cycles for all memory transfers.
3-490
AFN-Q1483A
iAPX 188
INSTRUCTION SET SUMMARY (Continued)
FUNCTION
Clock
Cycles
FORMAT
JLElJNG ~ Jump on less or equal not greater
I
I
10 1 1 1 1 1 1 0 I
JBIJNAE ~ Jump on llelow not above or equal
10 1 1 1 0 0 1 0
JBElJNA ~ Jump on llelow or equal,no1 above
10 1 1 1 0 1 1 0
drsp
JPIJPE ~ Jump on pa,,~ pa,,~ even
10 1 1 1 1 0 1 0
dlsp
JO ~ Jump on overlow
10 1 1 1 0 00 0
dlsp
JS ~ Jump 011 Sign
10 1 1 1 1 00 0
dlsp
JNE/JNZ ~ Jump on not equal notlero
10 1 1 1 0 1 0 1
dlsp
JNLlJGE ~ Jump on not less greater or equal
10 1 1 1'1 1 0 1
dlsp
JNLEIJG ~ Jump on no1less orequal greater
10 1 1 1 1 1 1 1
dlsp
JNBIJAE ~ Jump on not llelow ,boveorequal
10 1 1 1 0 0 1 1
dlsp
JNBElJA ~ Jumpon not below orequal ,b""
10 1 1 1 0 1 1 11
disp
JNPIJPO ~ Jumpon not par par odd
10 1 1 1 1 0 1 1
dlsp
JNO ~ Jump on not overlo.
10 1 1 1 0 00 1
dlsp
JNS ~ Jump on not sign
10 1 1 1 1 00 1
dlsp
JCXZ ~ Jump on ex lero
11 1 1 0 0 0 1 1
dlsp
lOOP ~ loop ex times
dlsp
LOOPZlLOOPE ~ loop while zero equal
11 1 1 0 0 0 1 0
11 1 1 0 0 0 0 1
LOOPNZlLOOPNE ~ loop while not zero equal
11 1100000
dlsp
INT = Inlerrupl:
Type specIfied
11 1 0 0 1 1 0 1
Type 3
11 1 0 0 1 1 0 0
INTO ~ Interrupt on overflow
11
IRET ~ Interrupt return
11 1 0 0 1 1 1 11
JElJZ =Jump on equal zelO
JLlJNGE ~ Jump on less not greater or equal
10 1 1 1 0 1 0 0
dlsp
4/13
10 1 1 1 1 1 0 0
dlsp
4/13
4/13
4/13
4/13
I
I
I
10 0 1 11 0 I
disp
, ~ and ~ lines. The pins are
, floated after reset and when the bus is not
acquired. A8-A15 are stable on transfers to a
physical 8-bit data bus (ssme bus as 8088),
and are multiplexed with data on transfers to
a 16-bit phYSical bus.
o
Addr... and Status: Multiplexed most
significant address lines and status information. The address lines are active only
when addreSSing memory. Otherwise, the
status lines are active and are encoded as
shown below. The pins are floated after reset
and when the bus is not acquired.
S8S5S4S3
1 1 0 0 DMA cycle on CH1
1 1 0 1 DMA cycle on CH2
1 1 1 0 Non-DMA cycle on CH 1
1 1 1 1 Non-DMA cycle on CH2
S3-S6
au.:
BHE
o
Bus High Enabl.: The Bus High Enable is
used to enable data operations on the most
significant half of the data bus (08-015). The
signal is active low when a byte is to be
transferred on the upper half of the data bus.
The pin is floated after reset and when the
bus is not acquired. BHE does not have to be
latched.
50.51.52
o
Status: These are the status pins that define
the lOP activity during any given cycle. They
are encoded as shown below:
mCK
0
. LocII: The lock output signal indicates to the
bus controller that the bus is needed for more
than one contiguous cycle. It is set via the
channel control register. and during the TSL
instruction. The pin floats after resel and
when the bus is not acquired. This output is
active low.
RESET
I
Re..t: The receipt of a reset signal causes
the lOP to suspend all its activities and enter
an idle state until a channel attention IS
received. The signal must be active for at
least four clock cycles.
CLK
I
Clock: Clock prOVides all timing needed for
internal lOP operation.
CA
I
Channel Attention: Gets the attention of the
lOP. Upon the falling edge of this signal. the
SEL input pin is examined to determine
Master/Slave or CH1/CH2 information. ThiS
input is active high.
SEL
I
S.lect: The first GA received after system
reset informs the lOP via the SEL line, whether it is a Master or Slave (0/1 for Master/Slave respectively) and starts the initialization sequence During any other CA
the SEL line signifies the selection of
CH1/CH2. (0/1 respectively.)
DRQI-2
I
Data Request: DMA request inputs which
Signal the lOP that a peripheral is ready to
transfer/receive data using channels 1 or 2
respectively. The signals must be held active
high until the appropriate fetch/stroke IS
initiated.
RQ/GT
I/O
Request Grant: Request Grant Implements
the communication dialogue reqUired to arbitrate the use of the system bus (between
lOP and CPU, LOCAL mode) or I/O bus when
two lOPs share....!!'e same bus (REMOTE
mode). The RQ/GT signal...!! a'£!lve low. An
internal pull-up permits RQ/GT to be left
floating if not used.
SINTRI-2
0
Signal Interrupt: Signal Interrupt outputs
from channels 1 and 2 respectively. The
interrupts may be sent directly to the CPU or
through the 8295A interrupt controller. They
are used to indicate to the system the
occurrence of user defined events.
EXT1-2
I
External Termlnata: External terminate
inputs for chamiels 1 and 2 respectively. the
EXT signals will cause the termination of the
current DMA transfer operation If the channel is so programmed by the channel control
register. The Signal must be held active high
until termination is complete.
iUiSii
o
o
o
o
0 0 Instruction fetch; I/O space
0 1 Data fetch; I/O space
1 0 Data store; I/O space
1 1 Not used
1 0 0 Instruction fetch; System Memory
1 0 1 Data fetch; System Memory
1 1 0 Data store; System Memroy
1 1 1 Passive
The status lines are utilized by the bus
controller and bus arbiter to generate all
memory and I/O control signals. The signals
change during T4 if a new cycle is to be
entered while the return to passive state in T3
or Tw indicates the end of a cycle. The pins
are floated after system reset and when the
bus is not acquired.
READY
I
Ready: The ready, signal received from the
addressed device indicates that the device is
ready for data transfer. The signal is active
high and is synchronized by the 8284 clock
generator.
Nam. and Function
Vee
Vss
3-495
VoHage: +5 vol.t power input.
Ground.
AFN'()0840E'
control. CRT control, such as cursor control and auto
scrolling, is simplified with the 8089. Keyboard control,
communication control and general 1/0 are just a few of
the typical applications for the 8089.
'
FUNCTIONAL DESCRIPTION
The 8089 lOP has been designed to remove 1/0 procestransfers from the central
sing, control and high
processing unit. Its major capabilities Include that of InItializing and maintaining peripheral components and
supporting versatile DMA. This DMA function boasts
'flexible termination conditions (such as external terminate, mask compare, single transfer and byte count expired). The DMA function of the 8089 lOP uses a two cycle approach where the Information actually flows
through the 8089 lOP. Tl1is approach to DMA vastly simplifies the bus timings and enhances compatibility with
memory and peripherals, In addition to allowing operations to be performed on the data as it Is transferred.
Operations can Include such constructs as translate,
where the 8089 automatically vectors through a lookup
table and mask compare, both on the "fly".
speed
Remote and Local Modes
The 8089 is functionally compatible with Intel's IAPX 86, 86
family. It supports any combination of 8116-bit busses. In
the REMOTE mode It can be used to complement other
Intel, processor families. Hardware and communication
architecture are designed to provide simple mechanisms
for system upgrade.
The only direct communication between the lOP and
CPU is handled by the Channel Attention and Interrupt
lines. Status Information, parameters and task programs are passed via blocks of shared memory, slmpli, fying hardware interface and encouraging structured'
programming.
)
.,
The 8089 can be u~d in applications such as file and
buffer management in' hard disk or floppy disk control. It
can also provide for soft error recovery routines and scan
·1~-~'·~N.:;::~~
_. ,ft
r- ~DY::
@
CC
O
......
iHI
Shown In Figure 3 Is the 8089 In a LOCAL configuration.
The IAPX 86 (or IAPX 88) is used In.its maximum mode. The
8089 and IAPX 88 reside on the same lOcal bus, sharing the
same set of system buffers. Peripherals located on the
system bus can be addressad by either the iAPX 86 or the
8089. The 8089 requests ~he use of the LOCAL bus by
means of the RQlGT line. This performs a similar function
to that of HOLD and HLDA on the Intel 8085A, 8080A and
iAPX 88 minimum mode, but is implemented on one
physical line., When the iAPX 86 relinquishes the system
bus, the 8089' uses the same bus control, latches and
transceiver components to generate the system address,
control and data lines. This mode allows a more
economical system configuration at the expense of
reduced CPU thruput due to lOP bus utilization.
A typical REMOTE configuration is shown in Figure 4. In
this mode, the lOP's bus Is physically separated from
the system bus by means of system buffersllatches. The
lOP maintains its own local bus and can operate out of
local or system memory. The system bus interface con'
tains the following components:
• Up to three 8282 bufferllatches to latch the address to
the system bus.
• Up .to two 8286 devices bidirectionally buffer the
system data bus.
.:K ErNe
= i6Ji!~=~=====::ti~===t:==+;==t;===
~1.:"~m~T._o'_"_·~~~r-~IN_e__t-________-jH-______r-__-jH-_It-______
fi
a!LE
liM
iIlIIIT
C lOCk
T .......TO•
•N.
....T
NOn!
~LY ONILATCH IS "UDED tF CONAGUIIID WITH" YO ONLY 14K
ADDREUING .. UIEO ONLY ONE TIItAJftIC!fYI!II .. NEEDED IF VStffG A
PHY8tCAL ...., DATA .... - .
Figure 3_ 'lYpicallAPX 86111, 86111 Configuration with 8088 In LOcAL Mode, 808i, aOas In MAX Mode
3-496
AFN.o084OE
inter
8089
• An 8288 bus controller supplies the control signals
necessary for buffer operation as well as MRDC
(Memory Read) and MWTC (Memory Write) signals.
• An 8289 bus arbiter performs all the functions
necessary to arbitrate the use of the system bus. This
is used in place of the Ra/GT logic In the LobAL
mode. This arbiter decodes type of cycle information
from the 8089 status lines to determine if the lOP
desires to perform a transfer over the "common" or
system bus.
The peripheral devices PER1 and PER2 are supported on
\heir own data and address bus. the 8OS9'communicates
with the peripherals without affecting system bus operation. Optional buffers may be used on the local bus when
capacitive lo',ding conditions so dictate. I/O programs and
RAM buffers may also reside on the local bus to further
reduce system bus utilization.
COMMUNICATION MECHANISM
Fundamentally, communication between, the CPU and
lOP is performed through messages prepared in shared
memory. The CPU can cause the 8089 to execute a pro·
gram by placing it in the 8089's memory space andlor
directing the 8089's atlenlion to it by asserting a hard·
ware Channel Attention (CA) signal to the lOP, ac·
tivating the proper 110 channel. The SEL Pin indicates to
OC.L
~
MEMORY
ROM/RAM
the lOP which channel is being addressed. Communlca·
tlon from the lOP to the processor can be performed in a
similar manner via a system interrupt (SINTR 1,2), if the
CPU has enabled interrupts for this purpose. Addition·
ally, the 8089 can store messages in memory regarding
its status and the status of any peripherals. This com·
municatlon mechanism is supported by, a hierarchial
data structure to provide a maximum amount of flexi·
bility of memory use with the added capability of handl·
ing muitiple lOP's.
.
Illustrated in Figure 5 is an overview of the communica·
tion data structure hierarchy that exists for the 8OS9 1/0
p~ocessor. Upon the first CA from RESET, if the lOP is
initialized as the BUS MASTER, 5 bytes of information are
read into the 8089 starting at location FFFFS (FFFFS,
FFFF8-FFFFB) where the type of system bus (1S-bit or 8bit) and pOinters to the' system configuration block are
obtained. This is the only fixed location the 8089 accesses.
The remaining addresses are obtained via the data struc-.
ture hierarchy. The 8089 determines addresses in the
same manner as does the iAPX 8S; i.e., a 16-bit relocation
pointer is offset left 4 bits and added to the 16-bit address
offset, obtaining a 2Q-bit address. Once these 20-bit addresses are formed, they are stored as such. as all the 8089
address registers are 20 bits long. After the system configuration pOinter address is formed. the 8089 lOP accesses the system configuration block.
____.____. __ ~·----_____fsU~t.CL~.--1_~~---
,-------+~-------li1
:uS:
so
A"lN
ARBITRATION
T
H--+-+--} :~~~::tON
SIGNALS
CPU
SYSTEM
BUS
Figure 4. Typical REMOTE Configuration
3-497
AFN-D0840E
infef
8089
the'IOP, allowing ,the lOP to operate concurrently with
the CPU, or reside in system memory.
The advantage of this type of communication between
the processor, lOP and peripheral, is that it allows for
verr clean method for llie operating system to handle
I/O routines. Canned programs or "Task B,locks" allow
for execution of general purpose 110 routines with the
status' and peripheral command information being
passed via the Parameter Block ("dafa" memory). Task
Blocks (or "program" memory) can be terminated' or
restarted by the CPU, if need be. Clearly, the flexibility
of this communication lends itself to modularity and applicability to a large number of peripheral devices and
upward compatibility to future end user systems and
microprocessor families.
LOCATION
ADDRESS
INCREASE
FFFF6
a
• SYSTEM
CONFIGURATION
BLOCK
OB RELOCATION
CONTAOl
BUSY
BLOCK
I
CCW
,
PI ADDRESS
CHANNEL
PI RELQCATION
BUSY
CCW
PB ADDRESS
PARAMETER
BLOCK
CHANNEL
2
PI RElOCATION
f------TASK BLOCK
J
Register Set
1'-'----,,..1
T
lOP TASK
PROGRAM
T
The 8089 maintains separate regillters for its two I/O channels
as well as some cOmmon registers (see Figure 6). There are
sufficient regisJers for each channel to sustain its own DMA
transfers, and process its own instruction stream. The basic
DMA pointer registers (GA, GB-20 bits each), can pointto either,
the system bus or local bus, DMA source or destination, and
can be autoincremented_ A third register set.(GC) can be used
to allow translatidn during the DMA process through a lookup
table it points to. The channel control register, which may be
accessed only by a MOV, or MOVI instruction, determines the
mode of the channel operation, Additionally, registers are provided for a masked compare during the data transfer and can
be set up to act as one of the termination conditions. Other
registers are also provided_ Many of these registers can be used
as general purpose registers during program execution, when
the lOP is not performing DMA cycles_
Figure 5. Communication Data Structure Hierarchy
I
The System Configuration Block (SCB), used only duro
ing startup, points to the Control' Block (CB) and provides
lOP system configuration data via the SOC byte. The
SOC byte initializes lOP I/O bus width to 8/16, and
defines one of two lOP RO/GT operating modes. For
Ra/GT mode 0, the lOP is typically initialized as SLAVE
and has its FiO/CIT line tied to a MASTER CPU (typical
LOCAL configuration). In this mode, the CPU normally
has control of the bus, grants control to the lOP as-needed, and has the bus restored to it upon lOP task completion (lOP request...:CPU grant-lOP done). For RO/GT
mode 1, useful ohly in remote mode between two lOPs,
MASTERISLAVE designation ,is used only to initialize
bus control: from then on, each 10,P requests and grants
as the bus is needed (IOPI request-IOP2 grant-IOP2
request-IOPI grant). Thus, each lOP retains bus con·
trol until the other requests it The completion of in·
itialization is signalled by the lOP clearing the BUSY
flag in the CB. This type of startup allows the user to
have the startup pOinters in ROM with the SCB in RAM.
Allowing the SCB to be in RAM gives the user the flex·
ibility of being able to initialize multiple lOPs.
USER PROGRAMMABl(
1A019
0
G P ADDRESS A (GA)
G P ADDRESS 8 (GB)
G.P. ADDRESS C (GC)
TASK POINTER (TP)
___ 1 BIT POINTER TO EITHER I/O OR SYSTEM MEM()RY SPACE
"
0
INDEX (IX)
BYTE COUNT (BC)
MASK
COMPARE (MC)
C:HANNEL CONTAOL ICC)
NON USER PROGRAMMABLE
(AL WAYS POINTS TO SVSTEM MEMORy)
The Control Block furnishes bus control Initialization for
the lOP operation (CCW or Channel Control Word) and
provides pOinters to the Parameter Block or "data"
memory for both channeis 1 and 2, The CCW is retrieved
and analyzed upon all CA's other than ,the first after a
reset. The CCW byte is decoded to determine channel
operation.
19
I
I
1
PAAAMETER POINTER (PP)
CHANNEL CONTROL POINTER (CP)
P
I
Figure 6. Register Model
The Parameter Block contains the address of the, Task
Block and acts as a messge center between the lOP and
CPU. Parameters or variable information is passed from
the CPU to its lOP in this block to customize the soft·
ware interface to the peripheral device, It is also used
fot transferring data and status information between the
lOP and CPU.
The Task Block contains the instructions for the respec·
tive channel. This block can reside on the local bus of
Bus Operation
The 8089 utilizes the same bus structure as the
iAPX 86, 88 in their maximum mode configurations (see
Figure 7). The address is time multiplexed with the data
on the first 16/8 lines. A16 through A19 are time multiplexed with four status lines S3-S6. For 8089 cycles, 54
and S3 determine what type of cycle (DMA versus nonDMA) is being performed on channels 1 or 2. S5 and S6
3-498
AFN-00840E
8089
are a unique code assigned to the 8089 lOP, enabling
the user to detect which processor Is performing a bus
cycle In a multiprocessing ~nvlronment.
18-blts wide with either an 8-blt peripheral (under byte
coluRln) or 16·blt peripheral (word column) being shown.
•
The latency refers to the worst case response time by
the lOP to a DMA request, without the bus arbitration
times. Notice that the word transfer allows 50% more
bandwidth. This occurs since three bus cycles are re-'
qulred to map 8-blt data Into a 18-blt location, versus two
for a 16·blt to 16-blt transfer. Note that It Is possible to
fully saturate the system bus In the LOCAL mode
whereas In the I3EMOTE mode this Is reduced to a max·
.
Imum of 50%.
The first three status lines, 50-52, are used with an 8288
bus controller to determine If an Instruction fetch or
data transfer Is being performed in 1/0 or system
memory space.
DMA transfers require at least two bus cycles with each
bus cycle requiring a minimum of four clock cycles. Ad·
ditlonal clock cycles are added If walt states are required. This two cycle approach simplifies considerably
the bus timings In burst DMA. The 8089 optimizes the
transfer between two different bus widths by using
three bus cycles versus four to transfer 1 word. More
than one read (write) Is performed when mapping an
8-bit bus onto a 18-blt bus (vice versa). For example, a
data transfer from an 8-bit peripheral to a 16·blt physical
location In memory is performed by first doing two
reads, with word assembly within the lOP assembly
register file and then one write.
Table 2. Achievable 5 MHz 8089 Operations with
a 16-Blt System Bus
.
Local
Bandwidth
i-----,
T,
T,
Word
8yte
Word
830KBIS
t250 KBIS
830 KBIS
12!iO KBIS
1.012.4,.sec' 1.012.4 ,.sec' 1.0/2.4,.sec' I .012.4 ~eec'
Latency
2.4~c
System Bu.
Ut,lization
As can be expected, the data bandwidth of the lOP is a
function of the physical bus width of the system and 1/0
busses. Table 2 gives the bandwidth. latency and bus
utilization of the 8089. The system bus is assumed to be
PER
TRANSFER
Ts
tWA"
I
1.6,.sec
PER
TRANSFER
0.8 ,.sec
PER
TRANSFER
0.8~.ec
PER
TRANSFER
'2.4 ~ec If interleaving with olher channel and no walt stale•• 1~sec If
channel Is waiting for raquest.
(01 + N w M ' f ) . T a r - - - - + - - - - ( o 1
I
IIemoIe
8yt.
T.
Tl
+Nwfun-'Of-----I
Ta
"
t....
I
T.
eLK
"\
ADDMTATU'
HI...,..
II
'D'
DTli
iii_
-
I
x~:\\:!
.
WAR
r
flE"DY
\ \.
/~T
.NT
'-+-----'--+-~/
L
/
'\'-----t--'j
,'-----'/
fitOTl' HIS SfMLI (I •• NON IIUUlI'LEXIDI THROUGHOUT lEACH TMMIflfI,
CYCLE "·~I MI. ALIO I'AILE Ott TUNSfPl TO A pttYltCAl • In"
Flg~re 7. 8089 Bus Operation
3-499
AFN-OC84OE
8089
ABSOLUTE MAXIMUM RATINGS'"
*NOTICE: Stresses above those listed under "Absolute
MaKimum Ratings" may cause permanent damage to the
device, This is a stress rating only and functional operation of the device at these or any other. conditions above
those indicated iiI the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
.
Ambient Temperature Under Bias ......... O·C to 70·C
Storage Temperature .......... , .. -65·C to + 150·C
Voltage on Any Pin with, Respeci to Ground. . . . . . . . . . . . . . . .. - 1.0 to
7V
Power Dissipation ........................ 2.5 Watt
+
D.C. CHARACTERISTICS
Symbol
V 1l
(TA =
o·c to 70·C. Vee = sv :!:10%)
Parameter
Input Low Voltage
Min.
Max.
Units
-0.5
+0.8
V
Vcc+ 1.0
V
Test Co.nditions
VIH
Input High Voltage
VOL
Output Low Voltage
V OH
Output High Voltage
Icc
Power Supply Current
3S0'
rnA
T A =2S·C
III
Input Leakage Current(l)
:!: 10
/AA
OV
± 10
/AA
0.4SV .;; VOUT '" Vee
+0.6
V
2.0
0.45
V
2.4
IOl=2.0 mA
V
IOH = -400",A
<
VIN
<
Vee
ILO
Output Leakage Current
VCl
Clock Input Low Voltage
V CH
Clock Input High Voltage
Vcc+ 1.0
V
C IN
Capacitance of Input Buffer
(All input except
ADo- AD , 5. RQ/Gf)
15
pF
fc = 1 MHz
Cia
Capacita[lce ~I~Buffer
(ADo - AD ,5• RQ/GT)
15
pF
fc = 1 MHz
A.C. CHARACTERISTICS
(TA
= o·c to
-O.S
3.9
70·C. Vee
= sv
±10%)
8089/8086 MAX MODE SYSTEM (USING 8288 BUS CONTROLLER) TIMING REQUIREMENTS
Symbol
Parameter
Min.
Max.
Units
200
500
ns
T••I Condilions
TClCL
ClK Cycle Penod
TClCH
ClK low Time
('/, TClCl) - 15
TCHCl
CLK High Time
('hTClCl)+ 2
TCH1CH2
CLK Rise Time
10
ns
From 1 OV 103 5V
TCl2Cll
ClK Fall Time
10
ns
From35Vtol0V
TDVCL
,eata In Setup Time
TClDX
TI31VCl
Data In Hold Time
ROY Selup Time Into 8284 (See Notes 1. 2)
TClR1X
ROY Hold Time Into 8284 (See Notes 1. 2)
TRYHCH
READY Setup Time Into 8089
TCHRYX
READY Hold Time Into 8089
30
TRYlCL
READY Inactive to ClK (See Note 4)
-8
TlNVCH
Setup Time Recognition (ORO 1.2 RESET. Ext 1.2) ISee Note 21
TGVCH
ROIGT Setup Time
30
TCAHCAl
CA Width
95
TSlVCAl
SEl Setup Time
75
TCAlSlX
SEl Hold Time
0
TCHG?<
GT Hold Time Into 8089
TlllH
Input Rise Time (Except ClK)
20
ns
~rom
TIHll
Input Fall TII1)8 (Except CLK)
t2
ns
From 2.0V to O.BV
-- r---o'
ns
ns
ns
30
10
35
0
I
ns
ns
-
ns
ns
1'/,TClCl) - t5
ns
'
.
ns
ns
<15
-'
ns
ns
40
3-500
ns
. ns
1.-
30
O.BV to 2.0V
AFN.fJOa40E
8089
A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES
Parameler
Min,
Max.
Units
TCLML
Command 'Active Delay (See Note 11
10
35
ns
10
35
ns
ns
ns
ns
Symbol
TCL'MH
Command InactIVe Delay (See Note 1)
TRYHSH
READY Active to Status PaSSive (See Note 31
TCHSV
Status Active Delay
10
110
110
TCLSH
Status Inactive Delay
10
130
TClAV
Address Valid Delay
10
110
TCLAX
Address Hold Time
10
TClAZ
Address Float Delay
TCLAX
80
ns
TSVLH
Status Valid to ALE High (See Note 11
15
ns
TCLlH
ClK low to ALE Valid (See Note 11
15
ns
TCHlL
ALE Inactive Delay (See Note 11
15
ns
TCLDV
Data Valid Delay
10
110
ns
TCHDX
Data Hold Time
10
TCVNV
Control Active Delay (See Note 1)
TCVNX
Control Inactive Delay (See Note 11
TCHDTl
DifectlOn Control Active Delay (See Note 11
--
:----.
,
-
ns
ns
CL=
150pF
CL =
100 pF
ns
----
~.
T.st Conditions
10
45
ns
45
ns
50
ns
-~-------------~~-------+-----+---~
r-------~------------------------~----_+_--_+--_4
~;:H-T-;:;~;c;~~:ct::::
(:~:=-------------1.-------0--------1r------~RQ
+ ______---+______
30
TCLGH
InactIVe Delay
__
I-TCLsRV_---L-SlNTR val;;JD,;i;---------------
r--rOLOH
ns
85
ns
85
ns
----I__N
__
ot_e_5_:_C-=L_=_30----'P_F__~
T-OutP~; RlseT;;;;;-- ----- - - - - - -----------+'------------t--------f-------/---20
150
12
NOTES: 1 Signal at 8284 or 8288 shown tor reference only
2 Setup requirement for asynchronous signal only to guarantee recogmtlon at next elK
3 Aphes only to T3 and TW states
A.C. TESTING INPUT, OUTPUT WAVEFORM
ns
ns
CL = 100 pF
From' 0.8V to 2.0V
ns
4 Applies only to T2 State
5 Applies only If RQ/GT Mode 1 Cl'=3Opf. 2 7 Kn pull up t~ Vee
A.C. TESTING LOAD CIRCUIT
INPUT/OUTPUT
DEVICE
UNDER
TEST
~C'=100PF
':"
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOA A lOGIC 1 AND 0 45V FOR
A lOGIC 0 THE CLOCK IS DRIVEN AT 4 3V AND 025V TIMING MEASURE"
MENTS ARE MADE AT 1 5V FOR 80TH A LOGIC 1 AND 0
C L ,,- l00pF
C L INCLUDES JIG CAPACITANCE
3-501
AFN-oo&IOE
inter
"J
WAVEFORMS
8089 BUS TIMING USING 8288
ClK
SEE NOTE 7
I
At-A, ON TRANSFERS
TO AN ..IMT "HYSICAl IUS
ANDBHl
1i.I1.SO (EXCEPT HALTI
~--~---+---~----+--1-+vnn//!J~~nr//+----r\\-
J-
----1t-~1
X
TellH
~
TClAV'
flTClDV
TCHDXTClAX r-+--+--!--+---+-----Ir-"II
---=TS=V:-'::-H-it-"7:"r I •
I
C
S.~s,
A'9 A'6
-
{
-----.:.-
Lr
I.~
(SEE NOTE 3)
TCHll
r--
~----~---+~---r---f-----t--~J~---
ALE (8288 OUTPUTI
illlk'!w-~-~
SEE NOTE 4
\
FLOAT
(SEE NOTE 3)
.. reLSH
- - _ TCHSV
RDY (8284 INPUTI
TCHRYX
READY (8089 INPUT)
TRYHSH -Ir-f-'---t--.
-
t.r_+__
~
READ - (MWTC,AMWC,IOWC,AIOWC = YOH)
SEE NOTE 7
AND ABOVE
I
_ _T_C_lA_V_-+-Ilr-.
AIS Ao
AOn ADO
(IHE)
TClAX -
-+T_C_l_AZ",1-
,
----t-T...,CI'HDTL _
r
Tbd
FLOAT
l
_
-TDVCl--
TClDX-I
Jkr---~DA~T~A~,Nj---.'!l---:F::-L'::OA~T=--4c'
_
-
t.lCHDTH
y--+-~ _ _-+_~J
_ _ _ _ _r-~-_1-TC-l-M-l-_1-""\~
TCLMH-
8211 OUTPUTS
SEE NOTES ., 5
l'CYNV-
r.-
---+-+-----I---t----tJ'
TCVNX-
-TClAXI-WAITE - (AD,MRDC,iORC,DTIA - YOH)
TClAV-
SEE NOTE 7 ,
AND A~~ \ AD,s ADo
rr-
TCHDX-
ll-r-_+-_--I-I-TC_l_D,II-r-'-,+ - - - + - - - - - - - t - - - + - , . ' FLOAT
A,sAo
~
DATA OUT
NOTE 3)
TCVNX-
TCVNV-
DEN
_-+-+--'---+-----j-'.l
-~
I
_1-TClMl
\
TClMH~
I-
----t-t----t--hl\
. _ OUTPIIIS
SEE NOTES 4,5
.1
r.::::.lr--+---+------+----t-,I
A'iWc OR AiOWC
~~--4-------_4JI
-TClMH
___--I--I__-+__-t___i-__-~~TClMl
I
I,o\USlGI< has a HOLD,
HLDA bus exchange protocol, an Interface Is needed
which will translate R'QIGT signals to corresponding •
HOLD, HDLA signals and visa versa. Ol)e of the funtlons
. of the 82188 ABC Is to provide this translation. R'QIGTO
Is translated to HOLD, HLDA signals which are then
directly connected to the IAPX 186. The R'Q1GT1 line Is
also translated Into HOLD, HLDA signals (referred to as
SYSHOLD, SYSHLDA signals) by the 82188 ABC. This
allows a third processor (using a HOLD, hiLDA bus
exchange protocol) to gain control of the bus. Unlike an
IAPX 86/20 system, R'Q1GT1 Is only used when the
8087 has bus control. If the third processor requests
the bus when the current bus master Is the 186, the
82188 ABC will directly pass the request onto the 186
without going through the 8087. The third processor
has the highest bus priority In the system. If the 8087
requests the bus while the third processor has bus
control, the grant pulse will not be Issued until the
third processor releases the bus (using SYSHOLD).
In this configuration, the third processor has the highest
priority, the 8087 has the next highest, and the 186
has the lowest bus priority.
liIble 2. 8Q87 Data ~pes
Data
Formats
Range
Precision
7 ___£ili~ 017
Byte Integer
102
8 Bits'
17
Word Integer
104
16 Bits
115
Short Integer
109
32 Bits
131
Long Integer
1018
64 Bits
163
Pa'cked BCD
1018
18 Digits
Short Real
10±38
24 Bits
SI E7
Long Real
10±308
53 Bits
5 lEla
10±4932
64 Bits
sIE14
Temporary Real
--
Most Significant Byte
017 017 017 017 017 01
101 Two's Complement
101
T~o's Complement
101 Two's Complement
11
Two's
10 Complement
5·1- 0 17 0,.1
10 1 Dol
F231 Fa Implicit
EolFl
F5~ Fa Implicit
EoTFl
EolFo
F631
Real: (_1)S(2E-BIAS)(FooFl" .)
Integer: I
Bias;127 for Short Real
1023 for Long Real
16383 for Temp Real
Packed BCD: (-l)S(017" .00)
3-512
AFN'()18l!OE
inter
8087
Bus Operation
The 8087 bus structure, operation and timing are
identical to all other processors in the iAPX 86, 88
series (maximum mode configuration). The address is
time multiplexed with the data on the first 16/8 lines
of the addressldata bus. A16 through A19 are time
multiplexed with four status lines S3-S6. S3, S4 and
S6 are always one (HIGH) for 8087 -driven bus cycles
while S5 is always zero (LOW). When the 8087 is
monitoring CPU bus cycles (passive mode) S6 is also
monitored by the 8087 to differentiate 8086/8088 activity
from that of a local 1/0 processor or any other local
bus master. (The 8086/8088 must be the only processor
on the local bus to drive S6 LOW.) S7 is multiplexed
with and has the same value as SHE for all 8087
bus cycles.
The first three status lines; SO-~, are used with an
8286 bus controller or 82188 Advanced Bus Controller
to determine the type of bus cycle being run:
SO
1
Sf
X
0
0
1
1
1
1
0
S2
0
1
X
0
1
1
Unused
Unused
Memory Data Read
Memory Data Write
Passive (no bus
cycle)
Table 2 lists the eight data types the 8087 supports
and presents the format for each type. Internally, the
8087 holds all numbers in the temporary real format.
Load and store instructions automatically convert
operands represented in memory as 16-, 32-, or 64-bit
integers, 32- or 64"bit floating point numbers or 18digit packed BCD numbers into temporary real format
and vice versa. The 8087 also provides the capability
to control round off, underflow, and overflow errors
in each calculation.
Computations in the 8087 use the processor's register
stack. These eight 80-bit registers provide the equivalent
capacity of 20 32-bit registers. The 8087 register set
can be accessed as a stack, with instructions operating
on the top one or two stack elements, or as a fixed
register set, with instructions operating on explicitly
designated registers.
Table 5 lists the 808Ts instructions by class. All appear
as ESCAPE instructions to the host. Assembly language
programs are written in ASM-86, the iAPX 86, 88 assembly language.
Table 3. Execution Times for Selected iAPX 86/20
Numeric Instructions and Corresponding
iAPX 86/10 Emulation
Approximate Execution
Time (/Ls)
Programming Interface
Floating Point
Instruction
The 8087 includes the standard iAPX 86/10, 88/10
instruction set for general data manipulation and program control. It also includes 68 numeric instructions
for extended precision integer, floating point, trigonometric, logarithmic, and exponential functions. Sample
execution times for several 8087 functions are shown
in Table 3. Overall system performance is 100 times
that of an iAPX 86/10 class processor for numeric
instructions.
Add/Subtract
Multiply (single
preciSIOn)
Multiply (extended
precision)
Divide
Compare
Load (double precision)
Store (double precision)
Square Root
Tangent
Exponentiation
Any instruction executed b, the 8087 is the combined
result of the CPU and 8087 activity. The CPU and the
8087 have specialized functions and registers providing
fast concurrent operation. The CPU controls Overall
program execution while the 8087 uses the coprocessor
interface to recognize and perform numeric operations.
3-513
iAPX 86/20 iAPX 86/10
(5 MHz
Clock)
Emulation
17
1.600
19
1.600
27
39
9
10
21
36
90
100
2,100
3,200
1,300
1,700
1,200
19,600
13,000
17,100
AFN'()1820E
8087
NUMERIC PROCESSOR
EXTENSION ARCHITECTURE
with the CPU while the NEU is busy processing a
numeric instruction.
As Shown in Figure 5, the 8087 is internally divided
into two processing elements, the control unit (CU)
and the numeric execution unit (NEU). The NEU executes all numeric instructions, while the CU receives
and decodes instructions, reads and writes memory
operands and executes 8087 control instructions. The
two elements are able to operate independently of one
another, allowing the CU to maintain synchronization
Control Unit
The CU keeps the 8087 operating in synchronization
with its host CPU. 8087 instructions are intermixed with
CPU instructions in a single instruction stream. The CPU
fetches all instruCtions from memory; by monitoring the
status (SO-S2, S6) emitted by the CPU, the control unit
determines when an instruction is being fetched. The
Figure 4. iAPX 86/20, 88/20 System Configuration
INT
--~"ljNTR
1-1
82!i9A
PiC
IAPX86
BUS
INTERFACE
COMPONENTS
MUL TIM ASTER
SYSTEM
BUS
8284A
CLOCK
GENERATOR
elK H - - -......--lcLK
~o::
'------,.-+--~INT
i-
_
-.
elK
.....
~~8~
_ _ ....J
Figure 5. iAPX 186, 188 System Configuration
1
:OOSOIlUSYINT
..,," ..,'" : : ----1
1
II
TEST
INTO
0 & 1 1 _ 0 S1
",P~186
OSOI""-OSIl
.~
INTERFillCE
COr.lPONE"ITS
HUI,l,_HlOA
HOlO_HOlJ)
L -_ _---'
"
I ;
\
L
L ___
____
r----------~
..JSVSHOlD
I
~SVSMlDA
I
:
I1
I '.;-v'
IL __________ ...JI
3-514
AFN'()1820E
8087
CU monitors the Data bus in parallel with the CPU tQ
obtain instructions that pertain to the 8087.
The CU maintains an instruction queue that is identical
to the queue in the host CPU. The CU automatically
determines if the CPU is an 8086/186 or an 8088/188
immediately after reset (by monitoring the SHE/S7 line)
land matches its queue length accordingly. By monitoring the CPU's queue status lines (OSO, OS1), the CU
obtains and decodes instructions from the queue in
synchronization with the CPU.
A numeric instruction appears as an ESCAPE instruction
to the CPU. Both the CPU and 8087 decode and execute
the ESCAPE instruction together. The 8087 only
recognizes the numeric instructions shown in Table 5.
The start of a numeric operation is acomplished when
the CPU executes the ESCAPE instruction. The instruction mayor may not identify a memory operand.
The CPU does, however, distinguish between ESC
instructions that reference memory and those that
do not. If the instruction refers to a memory operand,
the CPU calculates the operand's address using any
one of its available addressing modes, and then performs a "dummy read" of the word at that location.
(Any location within the 1M byte address space is
allowed.) This is a normal read cycle except thaUhe
CPU ignores the data it receives. If the ESC instruction does not contain Ii memory reference (e.g. an
8087 stack operation), the CPU simply proceeds to
the next instruction.
An 8087 Instruction can have one of three memory
reference options; (1) not reference memory; (2)
load an operand word from memory into the 8087; or
. (3) store an operand word from the 8087 jnto
memory. If no memory reference is required, the
8087 simply executes its instruction. If a memory
reference is required, the CU uses a "dummy read"
cycle initiated by the CPU to capture and save the
address that the CPU places on the bus. If the instruction is a load, the CU additionally captures the
data word when it becomes available on the local
data bus. If data required 'is longer than one word,
the CU' immediately obtains the bus from the CPU
using the request/grant protocol and reads the rest
of the information in conseq.ltive bus cycles. In a
store operation, the CU captures and saves the store
address as in a load, and ignores the data word that
follows in the "dummy read" cycle. When the 8087 is
ready to perform the store, the CU ob,tains the bus
from the CPU and writes the operand starting at the
specified address.
Numeric Execution Unit
The NEU executes all instructions that involve the
register stack; these include arithmetiC, logical,
transcendental, constant and data transfer instructions. The data path in the NEU is 84 bits wide (68
fraction bits, 15 exponent bits and a sign bit) which
allows internal operand transfers to be performed at
•
very high speeds.
When the NEU begins executing an instruction, it
activates the 8087 BUSY signal. This Signal can be
used in conjunction with the CPU WAIT instruction
to resynchronize both processors when the NEU has
completed its current instruction.
Register Set
The iAPX 86/20 register set is shown in Figure 3. Each
of the eight data registers in the 8087's register stack
is 80 bits and is divided into "fields" corresponding
to the 8087's temporary real data type.
At a given point in time the TOP field in the control word
identifies the current top-of-stack register. A "push"
operation decrements TOP by 1 and loads a value into
the new top register. A "pop" operation stores the value
from the current top register and then increments TOP
by 1. Like CPU stacks in memory, the 8087 register
stack grows "down" toward lower-addressed registers,
Instructions may address the data registers either
impliCitly or explicitly. Many instructions operate on
the register at the top of the stack. These instructions implicitly address the register pointed to by the
TOP. Other instructions allow the programmer to
explicitly specify the register which is to be used.
Explicit register addressing is "top-relative." .
Status Word
The status word shown in Figure 6 reflects the overall state of the 8087; it may be stored in memory and
then inspected by CPU code. The status word is a
16-bit register divided into fields as shown in Figure
6. The busy bit (bit 15) indicates whether the NEU is
either executing an instruction or has an interrupt
request pending (B 1), or is idle (B 0). Several
instructions which store and manipulate the status
word are executed exclusively by the CU, and these
do not set the busy bit themselves.
=
3-515
=
AFN'()1820E
intJ
8087
15
I
B IC.' TOP IC,IC,IC.I'RI X IPEIUEIOEIZEIOEI'E
I
I
EXCEPTION FLAGS (1 • EXCEPTION HAS OCCURRED)
INVALID OPERATION
DENORMALIZED OPERAND
ZERO DIVIDE
OVERFLOW
UNDERFLOW
PRECISION
(RESERVED)
INTERRUPT REQUEST'"
CONDITION CODEII !
TOP OF STACK POINTER'"
NEU BUSY
(l)IR IS set If any unmasked exception bit 18 set. cleared otherwise
(2)See Table 3 for condition code interpretation
(S)Top Values
000 :: Register 0 IS Top of Stack
001 = Register! IS Top of Stack
111
=Register 7 IS Top of Stack
Figure 6. 8087 Status Word
The four numeric condition code bits (Co-C3) are similar
to flags in a CPU: various instructions update these bits .
to reflect the outcome of 8087 operations. The effect of
these instructions on the condition code bits is summarized in Table 4.
Bits 14-12 of the status word point to the 8087 register that is the current top-ot-stack (TOP) as
described above.
Bit 7 is the interrupt request bit. This bit is set if any
unmasked exception bit is set and cleared otherwise.
word can be used, however, to interpret the contents
of 8087 registers.
Instruction and Data Pointers
The instruction and data pointers (see Figure 8) are
provided for user-written error handlers. Whenever
the 8087 executes an NEU instruction, the CU saves
the instruction address, the opera'nd address (if
present) and the instruction opcode. 8087 instruc,tions can store this data into memory.
Bits 5-0 are set to indicate ,that the NEU has
detected an exception while executing an instruction.
TAG VAlUES!
Tag Word
00 '" VALID
01 ;: ZERO
10 ., SPECIAL
.11 :: EMPTY
The tag word marks the content of each register as
shown in Figure 7. The principal function of the tag
word is to optimize the 8087's performance. The tag
Figure 7. 6087 Tag Word
3-516
AFN'()1820E
8087
Table 4a.
Instruction
Type
Compare, Test
C3
~
C1
Co
0
0
0
0
0
0
1
X
X
X
X
C1
0
90
C2
U
1
U
U
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
1
Remainder
Examine
Condition Code Interpretation
,
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
0
1
0
1
Interpretation
> Source or 0 (FTST)
ST
ST
ST
ST
< Source or 0 (FTST)
= Source or 0 (FTST)
is not comparable
Complete reduction with
three low bits of quotient
(See Table 4b)
Incomplete Reduction
Valid, positive unnormalized
Invalid, positive, exponent =0
Valid, negative, unnormalized
Invalid, negative, exponent =0
Valid, positive, normalized
Infinity, positive
Valid, negative, normalized
,Infinity, negative
Zero, positive
Empty
Zero, negative
Empty
Invalid, positive, exponent = 0
Empty
Invalid, negative, exponent = 0
Empty
NOTES:
1. ST = Top of stack
2. X = value is not affected by instruction
3. U = value is undefined following instruction
4. Qn = Quotient bit n
MEMORY
OFFSET
15
CONTROL WORD
Table 4b.
+0
Condition Code Interpretation after
FPREM Instruction As a Function of
Dividend Value
Dividend Range
Dividend < 2 • Modulus
Dividend < 4 • Modulus
Dividend;;. 4 • Modulus
I
+2
TAG WORD
+4
INSTRUCTION POINTER (15-0)
+6
STATUS WORD
Q2
Q1
00
C3l
C3l
C2
Cl l
Cl
Cj
Co
Co
Co
.)1 I
INSTRUCTION
1
POINTER (19-16) 0
INSTRUCTION
OPCODE (10-0)
DATA POINTER (15-0)
DATA POINTER
(19-16)
15
NOTE:
1. Previous value of indicated bit, not affected by FPREM
instruction execution.
I
0
+8
+10
+12
1211
Figure 8. 8087 Instruction and Data Pointer
Image in Memory
3-517
AFN'()l82OE
intJ
8087
Exception Handling
Control Word
The 8087 provides several processing options which
are selected by loading a word from memory into the
control word. Figure 9 shows the format·and encoding of the fields in the control word:
. The 8087 detects six different exception conditions
that can occur during instruction execution. Any or
all exceptions will cause an interrupt if unmasked
·and interrupts are enabled.
The low order byte of this control word configures
8087 Interrupts and exception masking. Bits 5-0 of
the control word contain individual masks for each
of the six 'exceptions that the 8087 recognizes and
bit 7 contains a general mask bit for all 8087 interrupts. The high order byte of the control word
configures the a087 operating mode including
precision, rounding, and infinity controls. The precision. control bits (bits 9-8) can be used to set the
8087 internal operating precision at less than the
default of temporary real precision. This can be useful in providing compatibility with e/irlier generation
arithmetic processors of smaller precision than the
8087. The rounding control bits (bits 11-;10) provide
for directed rounding and true chop as well as the
unbiased round to nearest mode specified in the
proposed IEEE standard. Control over'closure of the
number space at infinity is also provided (either
affine clOSUre, ±oo, or projective closure, 00, is treated
as unsigned, may be specified).
If interrupts are disabled the 8087 will Simply continue execution regardless of whether the host
clears the exception. If a specific exception class is
masked and that exception occurs, however, the
8087 will post the exception in the status register
and perform an on-chip default exception handling
procedure, thereby allowing processing to continue.
The exceptions that the 8087 detects are the
following:
15
I xxx
Ilcl RC
I PC
I
1. INVALID OPERATION: Stack overflow, stack' underflow, indeterminate form (0/0, 00- 00, etc.) or
the use of a Non-Number (NAN) as an operand.
An expon!3nt value is reserved and any bit pattern
with this value in the exponent field is termed a
Non-Number and causes this exception. If this
exception is masked, the 8087's default response
is to generate a specific NAN called INDEFINITE,
or to propagate already existing NANs as the calculation result.
M I X IPMluMIOMIZMIDMllM
I
I
EXCEPTION MASKS (1 = EXCEPTION IS MASKED)
INVALID OPERATION
DENORMALIZED OPERAND
, %ERO DIVIDE
OVERF~OW.
UND~RFLOW
PRECISION
(RESERVE!!)
-
INTERRUPT MASK (1
,
=INTERRUPTS ARE MASKED)
PRECISION CONTROL(1 )
ROUNDING CONTROLla )
INFINITY CONTROL (0 = PROJECTIVE. 1 = AFFINE)
(RES~RVED)
(1)Preclslon Control
00= 24 bits
01 '" Reserved
10 =53 bits '
11 =64 bits
(2lRoundtng Control
,00 = Round to Nearest or Even
01 Round Down (toward - to)
10 Round Up (toward + to)
11 = Chop (truncate toward zero)
=
=
Figure 9. 8087 Control Word
3-518
AFN'()1820E
8087
2. OVERFLOW: The result is too large in magnitude
to fit the specified format. The 8087 will generale
an encoding for infinity if this exception is
masked.
3. ZERO DIVISOR: The divisor is zero while the dividend is a non~infinite, non-zero number. Again,
the 8087 will generate an encoding for infinity if
this exception is masked.
4. UNDERFLOW: The result is non-zero but too
small in magnitude to fit in the specified format. If
this exception is masked the 8087 will
denormalize (shift right) the fraction until the ex-
ponent is in range. This process is called gradual
underflow.
5. DENORMALIZED OPERAND: At least one o~ the
operands or the result is denormalized; it has the
smallest exponent but a non-zero signiflcand.
Normal processing continues if this exception is
masked off.
6. INEXACT RESU.LT: If the true result is not exactly
representable in the specified format, the. r~sult
is rounded according to the rounding mode, and
this flag is set. If this exception is masked, proceSSing will simply continue.
3'-519
AFNo0182OE
8087
*NOTIC~: S~ress88 above those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating'condltions for extended periods may affect
device reliability.
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ..........•O"C to 7IrC
Storage Temperature •................ -65·C to +150"C
Voltage on Any Pin with
Respect to Ground ......... '.......•... -1.0V to + TV
Power Dissipation ............ '................3.0 watt
D.C. CHARACTERISTICS
(TA = O"C to 70"C, Vee =+5V :t5%)
Min.
Max.
Units
Input low Voltage
-0.5
+0.8
V
VIH
Input High Voltage
2.0
Vee +0.5
V
VOL
Output low Voltage
VOH
Output High Voltage
Icc
Power Supply Current
475
rnA
TA = 25°C
Symbol
VIL
Parameter
V
0.45
2.4
Test Conditions
IOL = 2.0 rnA
V
IOH = -400 p.A
III
Input leakage Currel!t
:t10
p.A
OV ... VIN'" Vee
ILO
Output leakage Current
:t10
p.A
0.45V ... VOUT'" Vee
VeL
Clock Input low Voltage
-0.5
+0.6
V
VeH
Clock Input High Voltage
3.9
Vee + 1.0
V
CIN
Capacitance of Inputs
10
pF
fc = 1 MHz
CIO
CapaCitance of I/O Buffer
(ADO-15, A16-A19, BHE, S2-80,
RQfGT) and ClK
15
pF
fc = 1 MHz
10
pF
fc = 1 MHz
GoUT
Capacitance of Outputs
BUSY,INT
A.,C. CHARACTERISTICS
(TA
"
= O"C to 70"C, Vee = +5V :t5%)
TIMING REQUIREMENTS
Symbol
Parameter
8087
Min.
Max.
500
8087·2
Min. Max.
Units
Test Conditions
TClCl
ClK Cycle Period
200
TClCH
ClKlowTime
118
TCHCl
ClK High TIme
69
TCH1CH2
ClK Rise Time
10
10
ns
From 1.0V to 3.5V
TCl2Cl2
ClKFall Time
10
10
ns
From 3.5V to 1.0V
TDVCl
TClDX
TRYHCH
Data In Setup TIme
Data In Hold Time
READY Setup Time
READY Hold TIme
READY Inactive to OlK"
TCHRYX
TRYlCl
TGVCH
125
500
68
ns
44
20
10
30
10
118
30
ns'
ns
ns
ns
ns
68
20
-8
-8
ns
ns
RQfGT Setup TIme
30
15
ns
TCHGX
TaVCl
RQfGT Hold Time
as()'1 Setup TIme
40
ns
ns
TClQX
as()'1 Hold TIme
30
30
10
TSACH
Status Active Setup Time
30
ns
TSNCl
Status Inactive Setup TIme
Input Rise Time (Except ClK)
Input Fall Time (Except ClK)
TILIH
TIHll
30
10 ,
30
30
ns
30
20
12
20
12
ns
ns
From O.8V to 2.0V
ns
From 2.0V to O.8V
"See Note 3
3-520
AFN.()182QE
8087
A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES
Symbol
8087
Parameter
Min.
TClMl
Command Active Delay (See Note 1)
10
TClMH
Command Inactive Delay (See Note 1)
10
TRYHSH
Ready Active to Status Passive
. (See Note 2)
8087·2
Min.
Max.
Units
35
10
35
ns
35
, 10
35
ns
65
ns
Max.
110
TCHSV
Status Active Delay
10
110
10
60
ns
TClSH
Status Inaetive Delay
10
130
10
70
ns
TClAV
Address Valid Delay
10
110
10
60
ns
TClAX
Address Hold Time
10
TClAZ
Address Float Delay
TClAX
TSVLH
Status Valid to ALE High (See Note 1)
15
15
ns
TClLH
ClK low to ALE Valid (See Note 1)
15
15
ns
15
ns
60
ns
TCHll
ALE Inactive Delay (See Note 1)
TClDV
Datil Valid Delay
10
TCHDX
Data Hold Time
10
TCVNV
Control Active Delay (See Note 1)
TCVNX
ns
10
80
TCLAX
15
110
Test Conditions
CL=20-100pF for all
8087 Outputs (In addl·
to 8087 self·load)
10
50
10
ns
ns
5
45
5
45
ns
Control Inactive Delay (See Note 1)
10
45
10
45
ns
TCHBV
BUSY and INT Valid Delay
10
150
10
85
ns
TCHDTl
Direction Control Active Delay
(See Note 1)
50
50
ns
TCHDTH
Direction Control Inactive Delay
(See Note 1)
30
30
ns
TClGl
RO/GT Active Delay
0
85
0
50
ns
TClGH
RO/GT Inactive Delay
0
85
0
50
ns
TOlOH
Output Rise Time
20
20
ns
From 0.8V to 2.0V
TOHOl
Output Fall Time
12
12
ns
From 2.0V to 0.8V
Cl = 40pF (in addi· .
,ion to 8087self·load)
NOTES:
1. Signal at 8284A or 8288 shown for reference only.
2. Applies only to T3 and wait states.
3. Applies only to T2 state (8 ns into T3).
A.C. TESTING LOAD CIRCUIT
A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUT/OUTPUT
2.4
J5--TESTPOINTS_1~
DEVICE
UNDER
TEST
0.45
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1" AND 0 45V FOR
A LOGIC"O"
IC'-="'00'.
C L INCLUDES JIG CAPACITANCE
(
3-521
AFN'()I820E
inter
8087
WAVEFORMS
MASTER MODE
T'o
T,
I
::c
v
CLK
VCL
S;,s,.S;
TCLAV
I--;- TCLCL ~H1CH2 - '.
t
-\
r--1
1""1
';;;';;' ___
~CHCL
l::I
~DV
.I
TSYLH-I
TCLLH_
T,
I-~
I
04-TCL2CLl
Tw
d~~~
..
V!~ flllSEE NOTE 5)
TCLAX_
BHE, At.-A.,.
.X
--
S,-S,
.I~
l ' FLOAT
(SEE NOTE 3)
~TCHLL
I::""
Y
, CHDX
,,,..--
'\
-
• TRYLCL
(aa17
READY
INPUT) {
(BUNDTE!)
----
04-
!o-TCHRYX
. . . -10
TRjSH-I
'(
TCLAV--
READ CYCLE
,---
f
fTLAZ
TRYHCH ~
t+-TDYCL
Au-Ao
TCHDTL_
TCLDX
\I
DATA IN
FL7
.\'+
'\
.r-
TCLML __
8288 0U11'UTS
(SEE NOTES 6, 7, 9)
\
TCYNY .....
FLOAT
TCHDTH-+
,.
~
II--
•
TCYNX __
WRITE CYCLE
TCLAV
!:::.::1
X
TCLDV
--
:j
A"-A,,
X
DATA OUT
TCYNX
TCVNV_
8288 OUTPUTS
(SEE NDTES .. 7)
{~::
11=
F -;\
TCLMH_
TCLML-+
TCLMH
'\
TCLML
::l
\.
MWTC
TCLMH
::::l
TCHDX
LOAT
(SE,E NOTE 3)
~
~
NOTES:
1 ALL SIGNALS SWITCH BETWEEN VOl AND VOH UNLESS OTHERWISE SPECiRED
2 READY IS SAMPLED NEAR THE END OF T2. T3 AND TW TO DETERMIN~ IF TW MACHINE STATES ARE TO BE INSERTED
3 THE lOCAL BUS FLOATS ONLY IF THE 8087 IS RETURNING CONTROl TO THE 8086/8088
4 ALE AlSES AT LATER OF (TSVLH. TCLLH)
5 STATUS INACTIVE IN STATE JUST PRI()R TO T4
6 SIGNALS AT 8284A OR 8288 ARE SHOWN FOR REFERENCE ONLY
7 THE ISSUANCE OF 8?88 COMMAND AND CONTROl SIGNALS (MRDC.
MWTc. AMWC AND DEN) LAGS THE ACTIVE HIGH 8288 CEN
8 ALL TIMING MEASUREMENTS ARE MADE AT 1 5V UNLESS OTHERWISE NOTED
9 REFER TO THE 82188 ADVANCE BUS CONTROLLER FOR 186. 188 SYSTEMS
3-522
AFN.fJ1S20E
8087
WAVEFORMS (Continued)
PASSIVE MODE
T,
ClK
AO'!I-ADo
IN~~
READY
I
RESET TIMING
r~o---->50~sec'-----t
1
VCC
~---- ~2G
ClK CYCLES - - - - I
ClK
RESET
8087 TRACKS
=::4 elK CYCLES
CPU ACTIVITY
8087 READY TO
EXECUTE INSTRUCTIONS
REQUEST/GRANT0 TIMING
ClK
AD,s-AO o
A,g/Se-A"/S 3
52 ,5,,8 0
CPU
SHE/S7
NOTE THE CPU PROVIDES ACTIVE PULLUP OF ROIGTO, SEE TCLGH SPEC
3-523
AFN'()1820E
intJ
8087
WAVeFORMS (Continued)
REQUEST/GRANT1 TIMING
CLK
AD 1s-AD o
A1I/S.-A 1,1S,
82 .51 .10
~S7
---------------~----~: ~:--------
ALTERNATE MASTER
(SEE NOTE)
NOTE ALTERNATE MASTER MAY NOT DRIVE THE BUSES OUTSIDE OF THE REGION
SHOWN WITHOUT RISKING BUS CONTENTION
BUSY AND INTERRUPT TIMING
CLK
BUSY, INT
~~------------£f
.....- - - - - - - - - - -
TCHBV
3-524
"------------
AFN.()11!2OE
inter
8087
Table 5. 8087 Extanei0n81D the 86/1861~ctions Sets
Opllonal
Data Transfer
FLD
= LOAD
Inleger/Real Memory 10 ST(O)
Long Inleger Memory 10 ST(O)
ESCAPE MF
11 MOD 0 0 0
32 all
64 811
18811
Real
Inleger
Real
Integer
00
01
10
11
36-56
+EA
52-60
+EA
40-60
+EA
46-54
+EA
96-104
+EA
80-90
+EA
96-106
+EA
82-92
+EA
65-75
+EA
72-86
+EA
67-77
+EA
74-88
+EA
R/M[==~I~P==:
L.E_S_C_A_P_E_~_1_1--,I>--M_O_D_1_0_1__Rl_M--,[
ESCAPE 0 1 1 I
BCD Memory 10 ST(O)
ESCAPE
ST(,) 10 ST(O)
ESCAPE 0 0 1 1 1 1
1 1 1 1 MOD
1 0 0 RIM
IESCAPE
MF
ST(O) 10 ST(,)
1 ESCAPE
1 0 1 1 1 1
1 1 MOD 0 1 0 RIM
==
290-310 +EA
17-22
1= ==~I~P =J
11 MOD 0 1 1
R/M[::~I~P:J
ST(O) 10 Temporary Real
Memory
L.E_S_C_A_P_E_0_1_1---1I>--M_O_D_1_1__
' _R/_M.....[
ST(O) 10 BCD Memory
~E=S=C=A=P=E=1=1=1~1=M=O=D=1=1=0=R=/M~[ : ~ '~I~ ~ ]
FXCH = Exchange ST(,) and
ST(O)
66-92
+EA
I_ = = ~I~P = :
L.E_S_C,.-A_P_E_1_1_1---1I_M_O_D_l_1__
1 _R/_M.....
ESCAPE
1 0 1 11
1
0 1 1 ST(,)
I
,
1
0 0 ,
I
I
ESCAPE 0 0 1
ST(,)
82-92
+EA
15-22
ST(O) to Long Inleger Memory
ST(O) 10 ST(,)
84-90
+EA
0 1 0 ST(I) 1
= STORE AND POP
MF
1_
0 0 0 ST(I) 1
FST = STORE
ESCAPE
60-68 +EA
= =
53-65 +I;A
ST(O) to Integer/Real Memory
FSTP
32 811
1 MF
Temporary Real Memory 10
ST(O)
ST(O) 10 Integer/Real Memory
Clock Count Ranga
8,18811
Dleplacement
:
:
~I~:
84-94
+EA
94-105 + EA
52-58 +EA
:
520-540 +EA
17-24
~
10-15
Comparison
FCOM = Compare
Inleger/Real Memory 10 ST(O)
ST(i) 10 ST (0)
FCOMP
=
I
ESCAPE MF
0
I
MOD
0 1 0 RIM [
~ ~ ~I~P ~
J
,
I
ESCAPE 0 0 0 1 1 1
0 1
ci
60-70
+EA
16-91
+EA
)
40-50
ST(,) 1
Compare and Pop
Inleger/Real Memory to ST(O)
ST(,) to ST(O)
FCOMPP = Compare ST(') to
ST<,O) and Pop Twice
FTST = Test ST(O)
FXAM = Examine ST(O)
I
63-73 • 80-93
+EA
+EA
45-52
0
1 1 0 0 1
I
45-55
1
1 0 0 1 0 0
1
38-48
0 0 1 I 1 1
1 0 0 1 0 1
1
12-23
0 0 0
I ESCAPE
1 ,
, I ESCAPE
IESCAPE
-DI~P==:
0 1 1 ST(,)
E=S=C=A=PE=M=F==O=o4'1=M=O=D=0=1=1=R=/M===jI_
:=1
IESCAPE
I1
1
0 I 1 ,
0 0 1
I1
MnemonICs@ln'''1982
3-525
AFN-01820E
inter
8()87
'llble 5. 8087 ElmInslons to the 86/1,6 Instruction Sets (cont.)
I
Const,nts
I
FLDZ
= LOAD
FLD1
= LOAD +
FLDPI
+ 0 0 onto ST(O) ,
1 0 into ST(O)
= LOAD 1T Into ST(O)
FlOUT
ST(O)
= LOAD 1092 10 onto
FLDL2E
ST(O)
= LOAD 1092 e onto
FLDLG2
ST(O)
= LOAD 109'0 2 onto
FLDLN2
ST(O}
= LOAD 109.2 onto
=
MF
I
I
I
32 Bit
Re.1
Clock Count Range
32 Bit
84 Bit
Integer
Re.1
00
11-17
1 0 1 0 0 1
I
16-22
1
1 0 1 0 1 0
I
15-21
1 1
1 0 1 1 0 0
1 1
1 0 1 1 0 1
I
MOD
0 0 0 RIM
I
1,1
ESCAPE
0 0 1
I
ESCAPE
0 0 1
ESCAPE
0 0 1
ESCAPE
0 0 1 11
1
ESCAPE
0 0 1 11
I
ESCAPE
0 0 1
I
ESCAPE
0 0 1
I
ESCAPE
MF . 0
I
ESCAPE
d
I
I
ESCAPE
MF
I
I
1 1
1 0 1 1 1 0
1 1
1 0 1 0 0 0
1 1
1 0 1 0 1 1
10
01
I
I
I
I
I
I
I
Optional
8,18 Bit
DI.placamant
18 Bit
Intager
11
15-21
16-22
I
I
18-24
17-23
Arithmetic
FADD ~ Add Ilion
Integer/Real Memory With ST(O)
ST(I) and ST(O)
FSUB
0 0 0 ST(I)
I
1 0 R RIM
- - -,
[ --DISP
--
= Subtraction
Integer/Real Memory With ST(O)
ST(i) and ST(O)
FMUL
P 0
ESCAPE
d
0
P 0
I
I1
MOD
1 1 0 R R/M
= Multlpllcallon
Integer/Real Memory With ST(O)
I
ESCAPE
MF
ST(I) and ST(O)
I
ESCAPE
d
ESCAPE
MF
ESCAPE
d
FDIV = DIVISion
Integer/Real Memory With ST(O)
ST(I) and ST(O)
FSQRT
= Square Root of ST(O)
FSCALE
= Scale ST(O) by ST(I)
FPREM = Partial Remaonder of
ST(O) -ST(I)
FRNDINT
Integer
= Round ST(O) to
I
I
I
I
I
I
0
I
MOD
0 0 1 RIM
P 0
I
1 1
0 0
0
I
MOD
1 1 R RI~
P 0
I
1 1 1 1 R RIM
ESCAPE
0 0 1
1 1
1 1 1 0 1 0
ESCAPE
0 0 1
I
I
1 1
1 1 1 1 0 1
ESCAPE
0 0 1 1'1
1 R/M
1
1 1 1 0 0 0
1 1
1 1 1 1 0 0
,
ESCAPE
0 0 1
I
- - -,
[ --DISP
- - .!
+EA
+EA
+EA
102-137
+EA
70-100 (Note 1)
.J
I
90-120 108-143 95-125
+EA
+EA
+EA
102-137
+EA
70-100 (Note 1)
---
-,
[ -DISP
- - ..!
I
- -DISP
- - -,
I- I
I
I
I
I
90-120 108-143 95-125
I
110-125 130-144 112-168 124-138
+EA
+EA
+EA
+EA
90-145 (Note 1)
215-225 230-243 220-230 224-238
+EA
+EA
+EA
+EA
193-203 (Note 1)'
180-186
32-38
15-190
,
,16-50
NOTE:
1. If P= 1 then add 5 clocks'.
3-526
AFN-OI820E
8087
'IlIble 5. 8087 Extensions to the 86/186 Instructions Sets (cant.)
Optional
8,16 Bit
Displacement
= Extract
Components 01 5t(0)
Clock Count Range
27-55
ESCAPE
0 0 1
= Absolute Value 01
ESCAPE
0 0
o
0 0 0
10-17
= Change 51gn 01 5T(0)
ESCAPE
0 0
o
0 0 0 0
10-17
ESCAPE
0 0
FPATAN = Partial Arctangent
olST(O) -ST(I)
ESCAPE
0 0
o
0
250-800
F2XMl = 2STtOI _l
ESCAPE
0 0
o
000
310-630
ESCAPE
0 0
000
gOO-lIDO
ESCAPE
0 0
o
700-1000
ESCAPE
0
000
2-8
FENI = Enable Interrupts
ESCAPE
0
o
0
2-8
FOISI = Disable Interrupts
ESCAPE 0
o
°°
FXTRACT
FABS
1 1
1 1 0 1 0 0
5T(0)
FCHS
Transcendental
= Partial Tangent 01
FPTAN
FYL2X
= ST(I)· Log2
1 1
1
1 1 0 0
1 0
30-540
----~--------------~
5T(0)
[ST(O))
FYL2XPl = ST(1)· Log2
0
[ST(O) +11
Processor Control
FIN IT
Initialized 8087
=
FLOCW
= Load Control Word
FSTCW ~ Store Control Word
FSTSW
= Store Status Word
FCLEX
= Clear Exceptions
°°
LESCAPE
-_ _ _ _ _ _ _ _ _ _
~ESCAPE
= Restore State
°
°°
°°
LESCAPE
-_ _ _ _ _ _ _ _ _ _
FLOENV = Load EnVironment
FRSTOR
~
°°° °
°
°°
_
_ _ _ _ _ _ _ _ _ _1_ _
1 _1
MOD
MOD
L-E_S_C_A_PE_ _
FINCSTP = Increment Stack
~ ~I~~ ~ J
RIM
FDECSTP = Decrement Stack
ESCAPE
°
0
3-52.7
12-18 +EA
12-18 +EA
------1 __
RIM
°
°
7-14 + EA
2-8
1
_-'-,_M-O-D---O-O-R-I-M------'L
°°
h
~
°
ESCAPE
~I~~
~ ~ ~I~~ ~ ~:
MOD
_
_ _ _ _ _ _ _ _ _RIM--=:]
_
L-E_S_C_A_P_E_ _O
_ _'-M_O_D
_ _ _ _O
__
R/_M_ _.JI- -
POinter
POinter
~
L-E_S_C_A_P_E_ _O
_ _L-M_O_D
_ _ _ _ _R_I_M_--J[
ESCAPE
= Save State
2-8
0
L-E_S_C_AP_E__
O_O_---'-_M_O_D
___
O_ _R_/M_--'I __
FSTENV = Sto,e EnVironment
FSAVE
0 0 0
h:
40-50 + EA
DISP:
35-45 +EA
DiSp - :
197-207+EA
~~~ =~
197-207+EA
~~~
6-12
°
6-12
AFN'()l820E
8087
'!lIble 5. 8087 Extensions to the 861186 Instructions Sets (cont.)
Clock Count Range
ESCAPE
1 0 1
I
FNOP = No Operallon
ESCAPE
o
1
l'
1
0 1 000
FWAIT =CPU Walt lor 6067
1 ' 0
1
0
1
1
FFREE
'n
= Free ST(I)
0
0
1
1 1
0 0 0 ST(I)
!H6
o
I
I
10-16
3+5n'
= number of times CPU examines TEST line before 6067 lowers BUSY.
NOTES:
1. if mod=OO then OISP=O', disp-Iow and disp-high are absent
if mod =01 then DISP=disp-low sign-extended to 16-bits, disp-high is absent
if mod=10 then OISP=disp-high; disp-Iow
if mod = 11 then rIm is treated as an ST(i) field
2. if rIm =000 then EA=(BX) + (SI) +DISP
if r/m=001 then EA=(BX) + (01) +OISP
if r/m=010 then EA=(BP) + (SI) +OISP
if r/m=011 then EA=(BP) + (01) +OISP
if r/m=100 then EA=(SI) + OISP
if r/m=101 then EA=(OI) + OISP
if r/m=110 then EA=(BP) + OISP
ifr/m=:111 then EA=(BX) + OISP
'except if mod =000 and r/m=110 then EA =disp-high; disp-Iow.
3. MF= Memory Format
00-32-bit Real
01-32-blt Integer
10-64-bit Real,
11-16-bit Integer
4. ST(O)= Current stack top
ST(i)
ith register below stack top
5. d= Destination
O-Destination is ST(O)
1-Destination is ST(i)
6. P= Pop
O-No pop
1-PopST(0)
7. R= Reverse: When d=1 reverse the sense of R
O-Destination (op) Source
1-Source (op) Destination
8.
For FSQRT:
-0 "" ST(O) "" +x
For FSCALE:
_2'5 "" ST(1) < +2'5 and ST(1) integer'
For F2XM1:
0"" STiO) "" 2- 1
For FYL2X:
0 < ST(O) -80 THEN DD;
AC$CYCLE$COUNT -0;
CALL RO$SIGNALSINTERRUPT(AC$INTERRUPT$LEVEL.,@AC$EXCEPT$CODEI;
END,
END AC$HANDLER;
r
r
r
r
Figure 5. OSP Examples
NO
INTERRUPT
HANDLER CALLS
INTERRUPT
HANDLER CALLS
SIGNALSINTERRUPT
EXIT$INTERRUPT
INTERRUPT TASK
COMPLETES INTERRUPT
SERVICING
INTERRUPT TASK
CALLS
. WAIT$INTERRUPT
CONTROL RETURNS TO AN
APPLICATION TASK
Figure 6, Interrupt Handling Flowchart
3-536
AFN·O:!059B
inter
_80130/80130-2
iAPX 86/30, 88/30,186/30,188/30
BUFFERS~
,
~~@"OBTAINS
~
~U~~~::R
=
I
[:]
--
J
........ ,
/
/
,,
~
~
INTERRUPT
TASK
,-....
" '--- ./ "- "\
/
....
\
,...,~
,@
I
I
PROCESSES
FULL BUFFER
/,
--,
Figure 7. Multiple Buffer Example
SIGNAL INTERRUPT
Used by an INTERRUPT
HANDLER to activate an Interrupt Task.
WAIT INTERRUPT
Suspends the calling Interrupt Task until the INTERRUPT HANDLER performs a
SIGNAL INTERRUPT to invoke it. If a SIGN.AL INTERRUPT for the task has
occurred, it is processed.
FREE MEMORY MANAGEMENT
The OSP Free Memory Manager manages the
memory pool which is allocated to each JOB for its
execution needs. (The CREATE JOB primitive allocates the new JOB's memory pool from the
memory pool of the parent JOB.) The memory pool is
part of the JOB resources but is not yet allocated
between the tasks of the JOB. When- a TASK, MAILBOX, or REGION system data type structure is
created within that JOB, the OSP implicitly allocates
memory for it from the JOB's memory pool, so that a
separate call to allocate memory is not required. OSP
primitives that use free memory management .implicitly include CREATE JOB, CREATE TASK"
DELETE TASK; CREATE MAILBOX, DELETE MAILBOX, CREATE REGION, and DELETE REGION. The
CREATE SEGMENT primitive explicitly allocates a
memory area when one is needed by the TASK. For
example, a TASK may explicitly allocate a SEGMENT
for use as a memory buffer. The SEGMENT length
can be any multiple of 16 bytes between 16 bytes and
64K bytes in length. The programmer may specify
any number of bytes from 1 byte to 64 KB, the OSP
will transparently round the value up to the appropriate segment size.
The two explicit memory allocation/deallocation
primitives are:
CREATE SEGMENT
Allocates a SEGMENT of specified length (in 16-byte-long
paragraphs) from the JOB
Memory Pool.
DELETE SEGMENT
Deallocates the SEGMENT's
memory area, and returns-it
to the JOB memory pool.
-
Intertask Communication
The OSR has built-in intertask synchronization and
communication, permitting TASKs to pass and share
information with each other. OSP MAILBOXes contain controlled handshaking facilities which guarantee that a complete message will always be sent from
a Sending TASK to a receiving TASK. Each MAILBOX
consists of two interlocked queues, one of TASKs
3-537
AFN·02059B
80130/80130.2 \
,
iAP~ 86/30, 88/30, 186/30, 188130
and the other of Messages. Four OSP primitives for
intertask synchronization and communication are
'provided:
There are five OSP primitives for mutual exclusion:
CREATE REGION'
Create a REGION (lock).
SEND CONTROL
Give up the REGION.
CREATE MAILBOX
Creates intertask message
exchange.
ACCEPT CONTROL
pELETE MAILBOX
Deletes an intertask message exchange.
Request the REGION, but do
not wait if it is not available.
RECEIVE CONTROL
RECEIVE MESSAGE
CallingTASKreceivesamessage from the MAILBOX.
Request a REGION, wait if
not immediately availlible.
DELETE REGION'
Delete a REGION.
SEND MESSAGE
Calling TASK sends a
message to the MAILBOX.
The CREATE MAILBOX primitive allocates a MAILBOX for use as an information exchange between
TASKs. The OSP will post information at the MAILBOX in a FIFO (First-In First-Out) manner when a
SEND MESSAGE instruction is issued. Similarily, a
message is retrieved by the OSP if a TASK issues a
RECEIVE MESSAGE primitive. The TASK which
creates the MAILBOX may make it available to other
TASKs to use.
The OSP also provides dynamic priority adjustment
for TASKs within priority REGIONs:, If a higherpriority TASK issues a RECEIVE CONTROL primitive,
while,a (lower-priority) TASK has the use of the same
REGION, the lower-priority TASK will be transparently, and temporarily; elevated to the waiting
TASK's priority until it relinquishes the REGION via
SEND CONTROL. At that point, since it is no longer
using the critical resource. the TASK wjll have its
normal priority restored.
OSP Control Facilities
If no message is available, the TASK attempting to
receive a message may choose to wait for one or
continue executing. •
The OSP also includes system primitives that provide
both control and customization capabilities to a mUltitasking system. These primitives are used to control
the deletion of SOTs and the recovery of free memory
in a system, to allow interrogation of operating system status, and to provide uniform mean, of adding
user SOTs and type managers.
The queue management method for the task queue
(FIFO or PRIORITY) determines which TASK in the
MAILBOX TASK queue will receive a message from
the MAILBOX. The method is specified in the
CREATE MAILBOX primitive.
DELETION CONTROL
Deletion of each OSP system data type is explicitly
controlled by the applications programmer by setting a deletion attribute for that structure. For example, if a SEGMENT is to be kept in memory until DMA
activity is completed, its deletion attribute should be
disabled. Each TASK, MAILBOX, REGION, and SEGMENT SOT is created with its deletion attribute enabled (i.e., they may be deleted). TwoOSP primitives
control the deletion attribute: ENABLE DELETION
and DISABLE DELETION.
Intertask Synchronization and Mutual
Exclusion
Mutual exclusion is essential to multiprogramming
and multiprocessing systems. The REGION system
data type implements mutual exclusion. A REGION is
represented by a queue of TASKS waiting to use a
resource which must be accessed by only one TASK
at a time. The OSP provides primitives to use
REGIONs to manage mutually exclu!!5ive' data and
resources. Both critical code sections and shared
data structures can be protected by these primitives
from simultaneous use by more than one task.
REGIONs support both FIFO (First-In Fir!!5t-Out) or
Priority queueing disciplines for the'TASKS seeking
to enter the REGION. The REGION SOT can also be
used to implement software locks.
., .
.
ENVIRONMENTAL CONTROL,
The OSP provides 'inquiry and control operations
which help the user interrogate the application envirO,nment and implement flexible exception har;Jdling.
These features aid in run-time decision mak'ing and
In application err!,r processing and rec()yery. There
are five OS~ environmental con,trol primitives. ,
!
Multiple REGIONs are allowed, and are automatically
exited in the reverse order of entry. While i,n a
REGlqN; a TASK ca,nnot be suspended by its~1f or
any other TASK, and the~by avoids de~dlock. '
3-538
OS~ENSIONS
The OSP architecture.is defined to allow new userd~fined System Da,a Types' and the primitives tp ma7
nipulate them to be ~dded to o,SP capabili~ie~
AFN·02059B
inter
80130/80130·2
iAPX 86/30, 88/30, 186/30, 188/30
provided by the built-in System Data Types. The type
managers created for the user-defined SDTs are
called user OS extensions and are installed, i{l the
system by the SET OS EXTENSION primitive. Once
installed, the functions of the type manager may be
invoked with user primitives conforming to the OSP
interface. For well-structured extended architectures, each OS extension should support a separate
user-d~ined system data type, and every OS,extension should provide the same calling sequence and program interface for the 'user as is provided for a
built-in SDT. The type manager for the extension
would be written to suit the needs of the application.
OSP interrupt vector entries (224-255) are reserved
for user OS extensions and are not used by the OSP.
After assigning an interrupt number to the extension,
the extension user may then call it with the standard
OSP call sequence (Figure 4), and the unique
software interrupt number assigned to the
extension.
ENABLE DELETION
Allows a specific SEGMENT,
TASK, MAILBOX, or REGION
SDT to be deleted.
DISABLE DELETION
Prevents a specific SEGMENT, TASK, MAILBOX, or
REGION SDT from being
deleted.
GET TYPE
Given a token, for an instance of a system data type,
returns the type code.
GET TASK TOKENS
Returns to the caller information about the current
task environment.
GET EXCEPTION
HANDLER
Returns information about
the calling TASK's current information handler: its address, and when it is used.
SEl EXCEPTION
HANDLER
PrOVides the address and
usage of an exception
handler for a TASK.
SET OS EXTENSION,
Modifies one of the interrupt
vector entries reserved for
OS extensions (224-255) to
point to a u'ser OS extension
SIGNAL.. EXCEpT!ON
For use in OS extension error procesSing.
allow the OSP primitives to report parameter errors
in primitive calls, and errors in primitive usage. Exception handling procedures are flexible and can be
,individually programmed by the application. In general, an exception handler if called wiH perform one
or more of the following functions:
-Log the Error.
-Delete/Suspend the Task that caused the
exception.
-Ignore the error, presumably because it is not
serious.
An EXCEPTION HANDLER is written as a procedure.
If PLM/86 is used, the "compact," "medium" or
"large" model of computation should be specified for
the compilation of the program. The mode in which
the EXCEPTION HANDLER operates may be specified in the SET EXCEPTION HANDLER primitive. The
return information from a primitive call is shown in
Figure 4. CX is used to return standard system error
conditions. Table 7 shows a list of these conditions,
using the default EXCEPTION HANDLER of the OSP.
HARDWARE DESCRIPTION
The 80130 operates in a closely coupled mode with
the iAPX 86/10 or 88/10 CPU. The 80130 resides on
the CPU local multiplexed bus (Figure 8). The main
processor is always configured for maximum mode
operation. The 80130 automatically selects between
its 88/30 and 86/30 operating ,modes.
The 80130 used in the 86/30 configuration, as shown
in Figure 8 (or a similar 88/30 configuration),
operates at bQth 5 and 8 MHz without requiring processor wait states. Wait state memories are fully supported, however. The 80130 may be configured with
both an 8087 NPX and an 8089 lOP, and provid~s
full context control over the 8087.
The 80130 (shown in Figure 3) is internally divided
into a control unit (CU) and operating system unit
(08U). The OSU contains facilities for OSP kernel
support including the system timers for scheduling
and timing waits, and the interrupt controller for
interrupt management support.
procedu~e.
EXCEPTION HANDLING
The OSP supports exception handlers. These are
similar to CPU exception handlers such as OVERFLOW alrd ILLEGAL OPERATION. Their purpose is to
iAPX86130, iAPX 88/30 System
Configuration
The 80130 is both I/O and memory mapped to the
local CPU bus. The CPU's status 80/·S2I Is
decOded along with 10CSI (with BHE' and AD3ADo) or MEMCs/ (with AD13-ADo). The pins are
Internally latched. See Table 1 for the decoding of
these lines.
'
AFN-0205llB
intJ
80130/80130-2 .
iAPX 86/30, 88/30, 186/30, 188/30
Memory Mapping
RAM Requirements
Address lines A19 -A14 can be used to form MEMCS/
since the 80130's memory-mapped portion is aligned
along a 16K-byte boundry. The 80130 can reside on
any 16K-byte boundry excluding. the highest
(FCOOOH-FFFFFH) and lowest (OOOOOH-003FFH). The
80130 control store code is position-independent except as limitecj above, in order to make it compatible
with many decoding logic designs. AD13-ADo are
decoded by the 80130's kernel control store.
The OSP manages its own interrupt vector, which is
assigned to low RAM memory. Working RAM storage
is required as stack space and data area. The
memory space must be allocated in user RAM.
I/O Mapping
The I/O-mapped portion of the 80130 must be aligned
along. a 16-byte boundry. Address lines A15-~
should be used to form 10CS/.
System Performance
The approximate performance of representitive OSP
primitives is given in Table 5. These times are shown
for a typical iAPX 86/30 implementation with an 8
MHz clock. These execution times are very comparable to the execution times of similar functions in
minicomputers (where available) and are an orner of
magnitude faster than previous generation
microprocessors.
OSP interrupt vector memory locations OH-3FFH
must be RAM based. The OSP requires 2 bytes of
allocated RAM. The processor working storage is
dynamically allocated from free memory. Approximately 300 bytes of stack should be allocated for
each OSP task.
TYPICAL SYSTEM CONFIGURATION
Figure 8 shows the processing cluster of a "typical"
iAPX 86/30 or iAPX 88/30 OSP system. Not shown are
subsystems likely to vary with the application. The
configuration includes an 8086 (or 8088) operating in
maximum mode, an 8284A clock generator and an
8288 system controller. Note that the 80130 is located
on the CPU side of any latches or transceivers. See
Intel Application Note 130 for further details on
configuration.
OSPTimers
Initialization
Both application system initialization and OSPspecific initialization/configuration are required to
use the OSp. Configuration is based on a "database"
provided by the user to the iOSP 86 support package.
The OSP-specific initialization and configuration information area is assigned to a user memory address
adjacent to the 80130's memory-mapped location.
{See Application Note 130 for further details.) The
configuration data defines whether 8087 support is
configured in the system, specifies if slave 8259A
interrupt controllers are used in addition to the
80130, and sets the operating system time base (Tick
Interval). Also located in the configuration area are
the exception handler control parameters, the address location of the (separate) application system
configuration area and the OSP extensions in use.
The OSP application system configuration area may
be located anywhere in the user memory and must
include the starting address of the application instruction code to be executed, plus the locations of
the RAM memory blocks to be managed by the OSP
free memory manager. Complete application system
support and the required 80130 configuration support are provided by the iAPX 86/30 and iAPX 88/30
OPERATING SYSTEM PROCESSOR SUPPORT
PAcKAGE (iOSP 86).
The OSP Timers are connected to the lower half of
the data bus and are addressed at even addresses.
The timers are read as two successive bytes, always
LSB followed by MSB. The MSB is always latched on
a read operation and remains latched until read.
Timers are not gatable.
Baud Rate Generator
The baud rate generator is 8254 compatible (square
wave mode 3). Its output, BAUD, is initially high and
remains high until the Count Register is loaded. The
first falling edge of the clock after the Count Register
is loaded causes the transfer of the internal counter
to the Count Register. The output stays high for N/2
[(N+1)/2 if N is odd] and then goes low for N/2
[(N -1 )/2 if N is odd]. On the fall ing edge of the clock
which signifies the final count for the output in low
state, the output returns to high state and the Count
Register is transferred to the internal counter. The
whole process is then repeated. Baud Rates are
shown in Table 6.
The baud rate generator is located at OCH (12), relative to the 16-byte boundary in the I/O space in which
the 80130 qomponent is located ("OSF" in the following example), the timer c.ontrol word is .located at
3-540
AFN-020598
inter
80130/80130·2
iAPX 86/30, 88/30, 186/30, 188/30
8
f-
iIO
Ill!e--
ClK
+.
1'-
I"'"
CONTROL
8288
PEN
'---
8088
~
BHE
A"
.
INTR
~RESS/~~
BHE
AI.
..
8282
ADDRESS
~
ADO
-=8286
~OE
~
iIOvt
INT
AD~~
eLK
AOO
NiCs
,
I-Y------
MEMCs
r-
DECODE
lOGIC
----
,
~
LlR
IRO
DO
~
I
/I .
INTERRUPT REQUESTS
IR7
SYSTICK
DIS
"
ill
.
I
AND
RESOURCES
AO
'---
L.
LOCAL
SYSTEM
,
~ IR2
Figure 8. Typical OSP Configuration
relative address, OEH(14). Timers are addressed with
IOCS=O. Timers 0 and 1 are assigned to the use by
the OSp, and should not be altered by the user.
For most baud-rate generator applications, the command byte
OB6H
ReadlWrite Baud-Rate Delay Value
will be used. Atypical sequence to set a baud rate
of 9600 using a count value of 52 follows (see
Table 6):
;Prepare to Write Delay to
Timer 3.
OUT OSF+14,AX ;Control Word.
MOV AX,52
OUT OSF+12,AL ;LSB written first
XCHG AL,AH
OUT OSF+12,AL ;MSB written after.
MOV AX,.OB6H
The 80130 timers are subset compatible with 8254
timers.
3-541
Interrupt Controller
The Programmable Interrupt Controller (PIC). is also
an integral unit of the 80130. Its eight input pins
handle eight vectored priority interrupts. One of
these pins must be used for the SYSTICK time function in timing waits, using an external connection as
shown. During the 80130 initialization and configuration sequence, each 80130 interrupt pin is individually programmed as either level or edge sensitive.
External slave 8259A interrupt controllers can be
used to expand the total number of OSP external
interrupts to 57.
In addition to standard PIC funtions, 80130 PIC unit
has an LlR output signal, which when low indicates
an interrupt acknowledge cycle. LlR =0 is provided to
control the 8289 Bus Arbiter SYSB/RESB pin. This
will avoid the need of requesting the system bus to
acknowledge local bus non-slave interrupts. The
user defines the interrupt system as part of the
configuration.
AFN·02059B
inter
80130/8013d~2
iAPX '86/30, 88130, 186/30, 188/30
INTERRUPT SEQUENCE
The OSP interrupt sequence is as follows:
1. One or more of the interrupts is set by a low-tohigh transition on edge-sensitive IR inputs or by a
high input on level-sensitive IR inputs.
I
2. The 80130 evaluates these requests, and sends an
INT to the CPU, if appropriate.
3. The CPU acknowledges the INT and responds
with an interrupt acknowledge cycle which is encoded in S2-S0'
4. Upon receiving the first inter~upt acknowledge
from the CPU, the h,ighest-priority interrupt is set
by the 80130 and the corresponding edge detect
latch is reset. The 80130 does not drive the address/data bus during this bus cycle but does
acknowledge the cycle by making ACK=O and
sending the LlR value for the IR input being
acknowledged.
/
5. The CPU will then initiate a second interrupt acknowledge cycle. During this cycle, the 80130 will
supply the cascade address of the interrupting
input at T1 on the bu~ and also release an 8-bit
pointer onto the bus if appropriate, where it is
read by the CPU. If the 80130 does supply the
pointer, then ACK will 'be low for the cycle. This
cycle also has the value LlR for the IR input being
acknowledged.
6. This completes the interrupt cycle. The ISR bit
remains set until an appropriate EXIT INTERRUPT
primitive (EOI command) is called at the end of
the Interrupt Handler.
OSPAPPLICATION EXAMPLE
Figure 5 shows an application of the OSP p~imitives
to keep track of time of day in a simplified example.
The system design uses a 60 Hz A.C. signal as a time
base. The power supply provides a TTL-compatible,
signal which drives one of 80130 edge-triggered in~
terrupt request pins once each AC. cycle. The Interrupt Handler responds to the interrupts, keeping
track of one second's AC. cycles. The Interrupt Task
dounts the seconds and after a day deletes itself. In
typical systems it might perform a data logging operation once each day. The,lnterrupt Handler and InterruptTask are written as separate modular programs.
The Interrupt Handler will actually service interrupt
59 when it occurs. It simply' counts each interrupt,
and at a count of 60 performs a SIGNAL INTERRUPT
to notify the Interrupt Task that a second has elapsed.
The Interrupt Handler (ACS HANDLER) was assigned
to this level by the SET INTERRUPT primitive. After
doing this, the Interrupt Task performed the Primitive
RESUME TASK to resume the application task (IN ITS
TASKS TOKEN).
The main body of the task is the counting loop. The
InterruptTask is signaled by the SIGNAL INTERRUPT
primitive in the Interrupt Handler (at interrupt level
ACS INTERRUPTS LEVEL)" When the task is signalled by the Interrupt Handler it will execute the
loop exactly one time, increaSing the time count
variables. Then it will execute the WAIT INTERRUPT
primitive, and wait until awakened by the Interrupt
Handler. Normally, the task will now wait some period
of time for the next signal. However, since the interface between the Handler and the Task is asynchronous, the handler may have already queued the
interrupt for servicing, the writer of the task does not
have to worry about this possibility.,
At the end of the day, the task will exit the loop and
, execute RESET INTERRUPT, which disables the, interrupt level, and deletes the interrupt task. The OSP
now reclaims the memory used by the Task and
schedules another task. If an exception occurs, the
coded value for the exception is available in TIMES
EXCEPTS CODE after the execution of the primitive.
A typical PL/M-86 calling sequence is illustrated by
the call to RESET INTERRUPT shown in Figure 5.
'3-542
AFN,02059B
inter
80130/80130·2
iAPX 86/30, 88/30, 186/30, 188/30
Table 2. OSP System Data 'tYpe Summary
!
Job
Jobs are the means of organizing the program environment and resources. An application consists of
one or more jobs. Each iAPX 86/30 system data type is contain!ld in some job. Jobs are independent of
each other, but they may share access to resources. Each job has one or more tasks, one of which is an
initial task. Jobs are given pools of memory, and they may create subordinate offspring jobs, which
'
may borrow memory from th'eir parents.
Task
Tasks are the means by which computations are accomplished. A task is an instruction stream with its
own execution stack and private data. Each task is part of a job and is restricted to the resources
provided by its job. Tasks may perform general interrupt handling as well as other computational
functions. Each task has a set of attributes, which is maintained for it by the iAPX 86/30, which
characterize its status. These attributes are:
its
its
its
its
its
its
its
containing job
register context
priority (0-255)
execution state (asleep, suspended, ready, running, asleep/suspended).
suspension depth
user-selected exception handler
optional 8087 extended task state
Segment
Segments are the units of memory allocation. A segment is a physically contiguous sequence of
16-byte, 8086 paragraph-length, units. Segments are created dynamically from the free memory
space of aJob as one of its Tasks requests memory for its use. Asegment is deleted when it is no longer
needed. The iAPX 86/30 maintains and manages free memory in an orderly fashion, itobtains memory
space from the pool assigned to the containing job of the requesting task and returns the space to the
job memory pool (or the parent job pool) when it is no longer needed. It does not allocate memory to
create a segment if sufficient free memory is not available to it, in that case it returns an error
exception code.
Mailbox
Mailboxes are the means of intertask communication. Mailboxes are used by tasks to send and
receive message segments. The iAPX 86/30 creates and manages two queues for each mailbox. One
of these queues contains message segments sent to the mailbox but not yet received by any task. The
other mailbox queue consists of tasks that are waiting to receive messages. The iAPX 86/30 operation
assures that waiting tasks receive messages as soon as messages are available. Thus at any moment
one or possibly both of two mailbox queues will be empty.
Region
Regions are the means of serialization and mutual exclusion. Regions are, familiar as "critical code
regions." The iAPX 86/30 region data type consists of a queue of tasks. Each'task waits to execute in
mutually exclusive code or to access a shared data region, for example to update a file record.
Tokens
The asp interface makes use of a 16-bitTOKEN data type to identify individual OSF data structures.
Each of these (each instance) has its own unique TOKEN. When a primitive is called, it is passed the
TOKENs of the data structures on which it will operate.
3-543
AFN·02059B
80130/80130·2
iAPX 86/30, 88/30, 186/30, 188/30
Table 3. System Data ~pe Codes and Attributes
S.D.T.
Code
Jobs
1
Tasks
Memory Pool
S.D.T. Directory
Attributes
Tasks
2
Priority
Stack
Code
State
Except!on Handler
Mailboxes
3
Queue of S.D.T.s
(generally segments)
Queue of Tasks
waiting for S.D.T.s
Region
5
Queue of Tasks
waiting for mutually
exclusive code or
data
Segments
6
Buffer
Length
Table 4. OSP Primitives
Class
J
0
B
T
A
S
K
I
N
T
E
R
R
U
P
T
S
E
G
M
E
N
T
OSP
Primitive
....
_-
Parameters
On Caller's Stack
Interrupt
Number
Entry Code
In AX
CREATE JOB
184
0100H
'See 80130 User Manual
CREATE TASK
184
0200H
DELETE TASK
SUSPEND TASK
RESUME TASK
SET PRIORITY
SLEEP
184·
184
184
184
184
0201H
0202H
0203H
0209H
0204H
Priority, IP Ptr, Data Segment, Stack
Seg, Stack Size Task Information,
ExcptPtr
TASK, ExcptPtr
TASK, ExcptPtr
TASK, ExcptPtr
TASK, Priority, ExcptPtr
Time Limit,ExcptPtr
DISABLE
ENABLE
ENTER INTERRUPT
EXIT INTERRUPT
GET LEVEL
RESET INTERRUPT
SET INTERRUPT
190
184
184
186
188
184
184
0705H
0704H
0703H
NONE
0702H
0706H
0701H
SIGNAL INTERRUPT
WAIT INTERRUPT
185
187
NONE
NONE
Level, ExcptPtr
Level #, ExcptPtr
Level #, ExcptPtr
Level # ,ExcptPtr
Level #, ExcptPtr
Level #, ExcptPtr
Level, Interrupt Task Flag Interrupt
Handler Ptr, Interrupt Handler DataSeg
ExcptPtr
Level, ExcptPtr
Level, ExcptPtr
CREATE SEGMENT
DELETE SEGMENT
184
184
0600H
0603H
Size, ExcptPtr
SEGMENT. ExceptPtr
3-544
-.---
AFN·02059B
80130/80130-2
iAPX 86/30, 88/30, 186/30, 188/30
Table 4. OSP Primitives (Continued)
OSP
Primitive
Interrupt
Number
Entry Code
In AX
CREATE MAILBOX
DELETE MAILBOX
RECEIVE MESSAGE
184
184
184
0300H
0301H
0303H
SEND MESSAGE
184
0302H
Mailbox flags, ExcplPlr
MAILBOX, ExcplPtr
MAILBOX, Time Limit ResponsePtr,
ExcptPtr
MAILBOX,Message Response, ExcptPtr
R
E
G
I
,0
N
ACCEPT CONTROL
CREATE REGION
DELETE REGION
RECEIVE CONTROL
SEND CONTROL
184
184
184
184
184
0504H
0500H
0501H
0503H
0502H
REGION, ExcptPlr
Region Flags, ExcptPtr
REGION, ExcptPtr
REGION, ExcptPtr
ExcptPtr
E
N
V
I
R
0
N
M
E
N
T
A
L
DISABLE DELETION
ENA'BLE DELETION
GET EXCEPTION
HANDLER
GET TYPE
GET TASK TOKENS
SET EXCEPTION
HANDLER
SET OS EXTENSION
SIGNAL
EXCEPTION
184
184
0OO1H.
0OO2H
TOKEN,ExcptPtr
TOKEN,ExcptPtr
184
184
184
0800H
OOOOH
0206H
Ptr,.ExcptPtr
TOKEN,ExcptPtr
Request, ExcptPtr
184
184
0801H
0700H
Ptr, ExcptPtr
Code,lnstPtr, ExcptPtr
184
0802H
Exception Code, Parameter Number,
StackPtr,O,O,ExcptPtr
Class
M
A
I
L
B
0
Parameters
On Caller's Stack
X
\
,
NOTES:
All parameters are pushed onto the OSP stack. Each parameter is one word. See Figure 3 for Call Sequence.
Explanation 01 the Symbols
JOB
TASK
REGION
MAILBOX
SEGMENT
TOKEN
OSP JOB SOT Token
OSPTASK SOT Token
OSP REGION SOT Token
OSP MAILBOX SOT Token
OSP SEGMENT SOT Token
Any SOT Token
Level
ExcptPtr
Message
Ptr
Seg
Interrupt Level Number
Pointer to Exception Code
Message Token
Pointer to Code,Stack etc. Address
Value Loaded into appropriate Segment Register
Value Parameter,
'-.
3-545
AFN·02059B
80130/80130·2
iAPX 86/30, 811/30, 186/30, 188/30
'Table 5. OSP Primitive Performance Examples
Primitive Execution Speed"
(microseconds)
Datatype Class
JOB
CREATE JOB
CREATE TASK (no preemption)
CREATE SEGMENT
SEND MESSAGE (with task switch)
SEND MESSAGE (no task switch)
RECEIVE MESSAGE (task waiting)
RECEIVE MESSAGE (message waiting)
SEND CONTROL
RECEIVE CONTROL
TASK
SEGMENT
MAILBOX
REGION
2950
1360
700
475
265
540
260
170
205
'8 MHz iAPX 86/30 OSP Configuation,
Table 6. Baud Rate Count Values (16X)
Baud
Rate
8 MHz Count
Value
5 MHz Count
Value
300
600
1200
2400
4800
9600
1667
833
417
208
104
52
1042
521
260
130
65
33
AFN·0205QB
80130/80130·2
iAPX 86/30, 88/30, 186/30, 188/30
Table 7a. Mnemonic Codes for Unavoidable Exceptions
E$OK
Exception Code Value = 0
the operation was successful
E$TIME
Exception Code Value = 1
the specified time limit expired before completion of the operations was possible
E$MEM
Exception Code Value = 2
insufficient nucleus memory is available to satisfy the request
E$BUSY
Exception Code Value - 3
specified region is currently busy
E$LlMIT
Exception Code Value - 4
attempted violation of a jOb, semaphore, or system limit
E$CONTEXT
Exception Code Value = 5
the primitive was called in an illegal context (e.g., call to enable for an already enabled
interrupt)
E$EXIST
Exception Code Value = 6
a token argument does not currently refer to any object; note that the object could have
been deleted at any time by its owner
E$STATE
Exception Code Value = 7
attempted illegal state transition by a task
E$NOT$CONFIGURED
Exception Code Value - 8
the primitive called is not configured in this system
E$INTERRUPT$SATURATION Exception Code Value - 9
The interrupt task on the requested level has reached its user specified saturation point
for interrupt service requests. No further interrupts will be allowed on the level until the
interrupt task executes a WAIT$INTERRUPT. (This error is only returned, in line, to
interrupt handlers.)
E$INTERRUPT$OVERFLOW
Exception Code Value = 10
The interrupt task on the requested level previously reached its saturation point and
caused an E$INTERR\.JPT$SATURATION condition. It subsequently executed. an
ENABLE allowing further interrupts to come in and has received another SIGNAL$INTERRUPTcall, bringing it over its specified saturation point for interrupt service
requests. (This error is only returned, in line, to interrupt handlers).
Table 7b. Mnemonic Codes for Avoidable Exceptions
E$ZERO$DIVIDE
Exception Code Value = 8000H
divide by zero interrupt occurred
E$OVERFLOW
Exception Code Value = 8001 H
overflow interrupt occurred
E$TYPE
Exception Code Value - 8002H
a token argument referred to an object tha was not of required type
E$BOUNDS
Exception Code Value - 8003H
an offset argument is out of segment bounds
E$PARAM
Exception Code Value - 8004H
a (non-token,non-offset) argument has an illegal value
E$BAD$CALL
Exception Code Vallie - 8005H
an entry code for which there is no corresponding primitive was passed
.
E$ARRAY$BOUNDS = 8006H Hardware or Language hilS detected an array overflow
E$NDP$ERROR
Exception Code Value = 8007H
,
an 8087 (Numeric data Processor) error has been detected; (the 8087 status information
is contained in a parameter to the exception handler)
3-547
AFN·02059B '
I-n+_r
••,'e'· '
80130/~0130·2
iAPX 86/30,88/30,186/30,188/30
ABSOLUTE MAXIMUM RATINGS*
·NOTlCE: Stresses above those listed under Absolute
Maximum Ratings may cause permanent damage'to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended period may affect df!vice reliability.
Ambient Temperature Under Bins ...•..... O°C to 70°C
Storage Temperature ................. -65°C to 150°C
Voltage on Any PJn With
Respect to Ground .......•.......... :"'1.0V to + 7V
Power Dissipation .......................... 1.0 Watts
D.C. CHARACTERISTICS
Symbol
V,L
V,H
VOL
VOH
(TA = O°C to 70°C, Vee = 4.5 to 5.5V)
Parameter
Input low Voltage
Input High Voltage
Min.
Max.
Units
- 0.5
0.8
V
Vcc +.5
0.45
V
2.0
Output low Voltage
Output High Voltage
V
V
2.4
Test Conditions
10L
=
2mA
10H = - 400"A
TA = 25 C
Icc
III
Power Supply Current
200
mA
Input leakage Current
10
"A
0< Y'N < Vcc
ILR
IR Input load Current
10
-300
"A
JlA
Y'N
Y'N
=
10
0.6
!lA
.45
=
pF
Y'N
Y'N
Y'N
=
ILO
Output leakage Current
Clock Input low
Input CapaCitance
10
1/0 Capacitance
15
pF
ICLI
Clock Input leakage Current
10
150
10
"A
"A
A.C. CHARACTERISTICS
Symbol
3.9
(TA
=
O-WC, Vcc
Parameter
=
V
4.5-5.5 Volt, Vss
80130
Min.
Max.
=
!lA
80130-2
Min.
Max.
Units
ClK low Time
ClK High Time
90
55
-
69
2000
44
2000
ns
TSVCH
TCHSV
TSHCL
Status Active Setup Time
80
-
65
-
'ns
TCHCL
ClK Cycle Period
200
Status Inactive Hold TIme
10
Status Inactive Setup Time
55
TCLSH
Status Active Hold TIme
10
-
TASCH
Address Valid Setup Time
TCLAH
Address Hold Time
8
10
TCSCL
TCHCS
TDSCL
Chip Select Setup Time
20
Chip Select Hold Time
0
Write Data Setup Time
80
-
TCHDH
TJWH
TCLDV
Write Data Hold Time
10
TCLDH
TCLDX
TCLCA
-
125
10
55
10
8
10
20
0
-
ns
ns
-
100
-
100
Read Data Valid Delay
-
140
-
105
Read Data Hold TIme'
10
-
10
-
Read Data to Floating
10
100
10
100
-
85
-
65
IR low Time
Cascade Address Dalay Time
=
Vee
2.5V
OV
60
10
Test Conditions
,ns
ns
-
-
-
=
Ground)
-
TCLCL
TCLCH
Vcc
0
Y'N = Vcc
V
VCLI
VCHI
C'N
C,O
Clock Input High
=
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CL = 200pE
intJ
80130/80130-2
iAPX 86/30, 88/30, 186/30, 188/30
A.C. CHARACTERISTICS (Continued)
80130
Symbol
TCLCF
T,AVE
Parameter
Cascade Addresse Hold Time
TCHEH
INTA Status t Acknowledge
Acknowledge Hold Time
TCSAK
Chip Select to ACK
TSACK
TAACK
TClOO
Status to ACK
Address to ACK
TClaoi
TJHIH
T'RCl
Max.
Min.
Max.
10
-
10
-
80
-
-
-
0
-
110
-
140
90
-
Timer Output Delay Time
200
-
Timer1 Output Delay Time
INT Output Delay
IR Input Set Up
80130-2
Min.
200
200
0
-
-
-
-
Units
80
ns
-
Notes
ns
110
ns
ns
140
ns
90
ns
200
ns
Cl
200
200
ns
Cl~100pF
20
~
100pF
ns
ns
WAVEFORMS
A.C.
elK
~-~/
1• •_ 'T_C_LO_D_-.;·
..
.
SYSTICK,
DELAY, BAUD
I
______________ _____
~x~
CLK
IR
TJLJH
....-
INT
3-549
AFN-02059B
inter
80.130/80130·2
iAPX 86/30, .88/30,t8~/30, 188/3.0
WAVEFORMS
A.C.
I~~
ClK
I
TelCH
TSVCH
TW
\
~X-----
H
I
I:SHC~
I
I
T4
,
/
TClSH
TCLCL
1
52, $1, S 0
I
T3
/
..,j
.TCHSV_
I
T2
T1
T4
I
I
SHe: A, ,,-A(, VAllO
BHE,AD
'T'
s"T
TCSCl
/
S
I
ADDRESS VALID
~l
r-TCSAK
TAACK
I
f4-I
ADDRESS VALID
I
I~
--I
FLOAT
\
TelDx
~H-
reLDV
READ DATAVAUD
I
TSACK
2ND IN TACVCLE
AO'5-AD,
H
I
I
WRITE OATAVALfO
G)
,.---
~
REA o CYCLE
K
TCHOH
'f.J1f.J.IX
-j
J
rosel
I
WR' TE CYCLE
AD
~s
a
.F9
FLOAT
~
\
FLOAT
CASCADE ADDRESS
W.
flOAT
®
POINTER
TIAVE
I
®
K
--1
f--rCHEH
I
'R
TlAVE
@
\
I
-.j I-- TCHEH
NOTES
1 CASCADE ADDRESS PRESENTED ON ADa, AD9 AND AD10 CORRESPONDING TO CASO, CAS1
AND CAS2 RESPECTIVELY AD11 "AD15 LINES ARE ACTIVE AND HAVE UNKNOWN VALUES ADO-AD7
ARE TRISTATE
2 POINTER VALUE IS ACTIVE ONLY If POINTER IS GENERAiED FROM THE 80150 AND NOT FROM
EXTERNAL SLAVE UNIT
ACTIVE lOW ONLY WHEN POINTER DATA IS BE!NG SUPPliED BY THE 80150
LOW ONLY FOR LOCAL INTERRUPT
3:550 '
AFN·02059B
80150/80150·2
iAPX 86/50, 88/50, 186/50, 188/50
CP/M-86* OPERATING SYSTEM PROCESSORS
• High·Performance Two·Chip Data
Processors Containing the Complete
CP/M·86 Operating System
• Memory Disk Makes Possible Diskless
CP/M·86 Systems
• No License or Serialization' Required
• Standard On· Chip BIOS (Basic
Input/Output System) Contains Drivers
for 8272A, 8274, 8255A, 8251A
• Built·in Operating System Timers and
Interrupt Controller
• 8086/80150/80150·2/8088/80186/80188
• BIOS Extensible with User· Supplied
Peripheral Drivers
Compatible At Up To 8 MH% Without
wait States
• User Intervention Points Allow Addition
of New System Commands
The Intel iAPX 86/50, 88/50, 186/50, and 188/50 are two-chip microprocessors offering general-purpose
CPU instructions combined with the CP/M-86 operating system. Respectively, they consist of the 8- and
16-bit software compatible 8086,8088, 80186,"and 80188 CPU plus the 80150 CP/M-86 operating system
extension.
CP/M-86 is a single-user operating system designed for computers based on the Intel iAPX 86, 88, 186,
and 188 microprocessors. The system allows full utilization of the one megabyte of memory available for
application programs. The 80150 stores CP/M-86 in its 16K bytes of on-'chip memory. The 80150 will run
third-party applications software written to run under standard Digital Research CP/M-86.
The 80150 is implemented in N-Channel, depletion-load, silicon-gate technology (HMOS), and is housed
in a 40-pin package. Included on the 80150 are the CP/M-86 operating system, Version 1.1, plus hardware
support for eight interrupts, a system timer, a delay timer, and a baud rate generator.
·CPfM-8a IS a trademark of Digital Research, Inc
1-' - - - - - - 1
I
I
8088
CLOCK
OR
INTERRUPT
PROGRAM
MEMORY
I
8086
DATA
MEMORY
I
STATUS
I
8284A
BUS
INTERFACE
CLOCK
DRIVER
ROY
INTERRUPT
STATUS
CS LIR
1_-----'
INTERRUPT
REOUESTS
_J~
BAUD RATE
TIMER
DELAY
SYSTEM
TIMER
TIMER
LAPX 86150, 88150
Figure 1. iAPX 86150, 88/50 Block Diagram
Thefallowlng are trademarks of Intel Corporation and Itsaffll18tesand may be used only to Identlfylntel products BXp, CREDIT, I, ICE, le$, 1m, Inslte, Intel, INTEL, InteleVISlon,
Intelllnk,
~~e~II~~'~~~~: ~~~~:~O~~~~P~: ~~~~h~5c~~~:~~~lrJn~~~~g~lrR~~~;:e~~;~~~,~~~~2~e~~g~~~~u~:~~::~n~~:~~~u~~:~y~~~~~t:~~~;t~~~' =~~~~~~~~b~~::a~~:~'t~~~~t~:r:~e
of Any Circuitry Other Than Circuitry Embodied In an Intel Product No Other Patent Licenses are Implied ©INTEL CORPORATION, 1982
"
3-551
SEPTEMBER 1982
ORDER NUMBER: 210705-002
inter
80150/80150-2 ~
iAPX 86150,88/50,186/50,188/50
b.\@Wb.\OO©~ OOOIF@mU~b.\'iiO@OO
- I:EI
MAX
MODE
Vss
Vee,
,Yss
AD14
AD15
AD14
AD13
iHE
AD13
AII113
AD12
IAT
AD12
AD17/84
Vee
AD15
AD11
IAt
AD11
A11185
AD10
lAS
AD10
AI_
IA4
AD9
.HEIST (HIGH}
01.08
1A3
A08
MNlMX
ADT
IA2
ADT
AD
AD6
IAI
AD6
lmIiTi
iiOiCffi
ADS
lAO
ADS
AD4
INT
ADO
LOCK
AD3
iii
AD3
H
AD2
51
' AD2
il
ADI
iii
ADI
!Ill
ADO
ACK
ADO
OSO
MEMCs
IiA
NMI
OSI
INTA
fEST
IOCS
SYSTICK
ClK
DELAY
ClK
READY
V,,
SAUD
Vss
AESET
Figure 2. IAPX 86150, 88/50 Pin Configuration
Table 1. 80150 Pin Description
Symbol
AD 1s-ADo
imEfS7
S2,S1,SO
Type
Name and Function
/\',
I/O
Address Data: These pins constitute the time multiplexed memory address (T1) and
data (T2, T3, Tw, T4) bus. These lines are active HIGH. The address presented during
T1 of a bus cycle will be latched internally and interpreted as an 80150 internal
address if MEMCS or 10CS is active for the invoked primitives. The 80150 pins float
whenever it is not chip selected, and drive these pins only during T2- T4 of a read
cycle and T1 of an INTA cycle.
I
Bus High Enable: The 80150 uses the BHE signal from the processor to determine
whether to respond with data on the upper or lower data pins, or both. The signal is
active LOW. BHE is latched by the 80150 on the trailing edge of ALE. It controls the
80150 output data as shown.
I
BHE
Ao
0
0
1
1
0
1
0
1
Status:
..
Word on AD1s-ADo
Upper byte on AD15 - ADs
Lower byte on AD7-ADo
Upper byte on-AD7-ADo
F~r the 80150, th'e status pins are used as inputs only. 80150 encoding follows:
S2
S1
So
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
'1
X
0
1
INTA
lORD
10WR
Passive
Instruction fetch
MEMRD
Passive
"
3-552
.
AFN·OI48TA
80150/80150-2
iAPX 86150,88/50,186/50,188/50
Table 1. 80150 Pin Description (Continued)
Symbol
Type
Name and Function
ClK
I
Clock: The system clock provides the basIc timing for the processor and bus controller.
It is asymmetric with a 33% duty cycle to provide optimized internal timing. The 80130
uses the system clock as an input to the SYSTICK and BAUD timers ancj to synchronize
operation with the host CPU
INT
0
Interrupt: INT is HIGH whenever a valid interrupt request is asserted. It is normally used
to interrupt the CPU by connecting It to INTR.
IR7-IRo
I
Interrupt Requests: An Interrupt request can be generated by raiSing an IR input (lOW
to HIGH) and holding ii HIGH until it is acknowledged (Edge-Triggered Mode), o.r just by a
HIGH level on an IR input (level-Triggered Mode).
ACK
0
Acknowledge: This line is lOW whenever an 80150 resource is being accessed. It is
also lOW during the first INTA cycle and second INTA cycle if the80150 IS supplYing
the interrupt vector information. This signal can be used as a bus r.eady acknowl·
edgement and/or bus transceiver control.
MEMCS
I
Memory Chip Select: This input must be driven lOW when a kernel primitive is being
fetched by the CPU AD,3-ADo are used to select the Insfrucllon.
IOCS
I
Input/Output Chip Select: When this input is low, during an lORD or IOWR cycle, the
80150's kernel primitives are accessing the appropriate peripheral function as speci·
fied by the following table:
LlR
0
BHE
A3
A2
A,
Ao
0
X
X
X
1
1
1
1
1
0
1
1
1
1
X
X
X
X
0
X
X
X
X
0
1
0
0
0
1
1
Passive
Passive
Passive
Interrupt Controller
Systlck Timer
Delay Counter
Baud Rate Timer
Timer Control
1
X
0
0
0
0
0
1
0
1
Local Bus Interrupt Request: This Signal IS lOW when the Interrupt request IS for a
non-slave Input or slave Input programmed as being a local slave.
Vee
Power: Vee IS the +5V supply Pin.
VSS
Ground: VSS is the ground Pin
SYSTICK
0
System Clock Tick: Timer 0 Output.
DELAY
0
DELAY Timer: Output of timer 1
BAUD
0
Baud Rate Generator: 8254 Mode 3 compatible output. Output of 80150 Timer 2.
The 80150 breaks new ground in operating system
software-on· silicon components. It is unique
because it is the first time that an industry·
standard personal/small business computer
operating system is being put in silicon. The
80150 contains Digital Research's CP/M-86
operating system, which is designed for Intel's
line of software· and interface-compatible iAPX
86, 88, 186, and 188 microprbcessors. Since the
entire CP/M-86 operating system is contained on
the chip, it is now possible to design a diskless
computer that runs proven and commonly
available applications software. The 80150 is a
true operating system extension to the host
microprocessor, since' it also integrates key
operating system·related peripheral functions
onto the chip.
. MODULAR DESIGN
Based on a proven, modula.r design, the system in·
cludes the:
• CCP: Console Command Processor
The CCP . is the human interface to the
operating system and performs decoding and
3-553
AFN-01467A
'80150/80150..2
iAPX 86150,88/50, 186/50;188/50
execution of user commands.
creased significantly. Since CP/M-86 is now
always in the system as a standard hardware
operating system, a properly functioning
system diskette is not, required. CP/M-86 in
hardware can no longer be overwritten accidentally by a runaway program. System reliability
is enhanced by the decreased dependence on
floppy disks and fewer chips a'nd interconnections required by the highly integrated 80150 .
• BOOS: Basic Disk Operating System
The BOOS is the logical, invariant portion of the
operating system; it supports a named file
system with a maximum of 16 logical drives,
containing up to 8 megabytes each for a potential of 128 megabytes of on-line storage.
• BIOS: Basic Input/Output System
4. The microcomputer system boots up CP/M-86
on power-on, rather than requiring the user to
go through a complicated boot sequence, thus
lowering the user expertise required.
The physical, variant portion of the operating
system, the BIOS contains the. systemdependent input/output device ~andlers.
CP/M* COMPATIBILITY
5. Diskless CP/M-based systems are now easy to
deSign. Since CP/M is already in the microcomputer hardware, there is no need for a disk drive
in the system if it i~ not desired. Without a disk
drive, a system is more portable, simpler to use,
less costly, and more reliable.
CP/M-86 files are completely compatible with
CP/M for 8080- and 8085-based microcomputer
systems. This simplifies the conversion of soft·
ware developed under CP/M to take full advantage
of iAPX 86, 88, 186, 188~based systems.
6. The administrative costs associated with
distributing CP/M-86 are eliminated. Since
CP/M-86 is now resident on the 80150 in the
microcomputer system, there is no end-user
licensing required nor is there any serialization
requirement for the 80150 (because no CP/M
diskette is used).
The user will notice no significant difference between CP/M and CP/M-86. Commands such as
DIR, TYPE, REN, and ERA respond the same way
in both systems.
CP/M-86 uses the iAPX 86, 88, 186, 188 register~
corresponding to 8080 registers for system call
and return parameters to further simplify software
transport. The 80150 allows application code and
data segments to overlap, making the mixture of
code and data that often appears in CP/M applications acceptable to the iAPX 86, 88, 186, 188.
7. End-users will value having their CP/M
operating system resident in their computer
rather than on a diskette. They will no longer
have to back up the operating system or have a
diskette working properly to bring the system
up in CP/M, increasing their confidence in the
integrity, reliability, and usability of the system.
Unique Capabilities of CP/M·8S in Silicon
1. CP/M-86 'on- a-chip reduces ·software development required by the system designer. It can
change the implementation of the operating
system into the simple linclusion of the 80150
on the CPU board.
80150 FUNCTIONAL DESCRIPTION
As described. later, the deSigner can either
simply incorporate the Intel chip without the
need for writing even a single line of additional
code, or he can add additional device drivers by
writing only the small amount of additional
code required.
2. The 80150 is the most cost-effective way to implement CP/M-86 in a microcomputer. The integration of CP/M-86 with the 16K bytes of
system memory it requires, the two boot ROMS
, required in a diskette-basedCP/M-86, and the,!
on-chip peripherals (interrupt controller and
timers) lead to s~vings in software, parts cqSt,
board space, and interconnect wiring.
;'
3. The reliability of the microcomputer i~ in-
L!\[Q)WL!\[);!)(Q:~ D[);!)IF@~~L!\m@[);!)
The 80150 is a processor extension that is fully
compatible with the 8086, 8088, 80186, and 80188
microprocessors. When the 80150 is combined
with the microprocessor, the tWO-chip set is
called an Operating System Processor and is
denoted as the iAPX 86/50,88/50, 186/50, or 188/50.
The basic system configuration is shown in
Figure 1. The 80150 connects directly to the multiplexed address/data bus and runs up to 8 MHz
,Without wait states.
, A. Hardware. Figure 3 is a functional diagram of
the 80150 itself. CP/M-86 is stored in the
16K-bytes of control store. The timers are compatible with the standard 8254 timer. The interrupt controller, with its eight programmable.interrupt inputs and one interrupt output, is
compatible with the 8259A Programmable Interrupt Controller. External slave 8259A inter·CP/M IS a regIstered trademark of
3-554
Dlglt~1 Research, Inc
AFN·01467A
, inter,
80150/80150-2
iAPX 86150,88/50,186/50;188/50
I-----------~----------------------,
I
I
OPERATING SYSTEM UNIT
I
I
DO-7
I
I
I
I
I
I
I
r
I
8,
I
PROGRAMMABLE
INTERRUPT
LOGIC
/
I
I
INTERRUPT INPUTS
I
I
I
I
I
CONTROL
:
STORE
~
i
:
~
I
I
I
:
:
:f-------- -
<
Z
'.
ADDRESS
DATA BUS
I
I
I
I
I
I
I
I
I
I
I
1d
08-15
~
I
I
I
SYSTEM
TIMER
--
~
I
SYSTEM
I'
I
I
DELAY
TIMER
I
DELAY
I
I
I
I.
BAUD RATE
GENERATOR
.::I
----- - - - - - - -
INTE"RRUPT OUT
I
~
BAUORATE
I
I
I
- -- - - --------'-j
I
<--
I
~
DATA
BUFFER
BUS
INTERFACE
I
•
ADDRESS
LATCH
{ AND
CONTROL
I
~
STATUS
~BUSCON TROl
~
CONTROL UNIT
L __________________________________
CLOCK
3
I
LOCAL
INTERRU PT
I
iORl
~
Figure 3. 80150 Internal Block Diagram
rupt controllers can be cascaded with the
S0150 to expand the total number of interrupts
to 57.
B. Software. Digital Research's version 1.1 of
CP/M·S6 forms the basis of the ·S0150'. CP/M
consists of three major parts: the Console
Command Processor (CCP), the Basic Disk
Operating System (BOOS), and the Basic In·
put/Output System (BIOS). Details on CP/M·S6
are provided in Digital Research's CPIM·86
Operating System User's Guide and CPIM·86
Operating System System Guide.
CCP - Console Command Processor
The CCP provides all of the capabilities provided
by Digital Research's CCP. Built·in commands
have been expanded to include capabilities nor·
mally included as transient utilities on the Digital
, Research CP/M~86 diskette.' Commands are pro·
vided to format diskettes, transfer files between
devices (based on Digital Research's Peripheral
Interchange Program PIP), and alter and display
I/O device and file status (based on Digital
Research's STAT).
·Through User Intervention POints, the standard
CP/M-S6 CCP is enhanced to allow the user to add
new built·in commands to· further customize a
CP/M·B6 system.
BOOS - Basic Disk Operating System
Once the CCP has parsed a command, it sends it
to the BOOS, which performs system services
such as managing disk directories and files.
Some of the standard BOOS functions provide:
Console Status
Console Input and Output
List Output
Select Drive
Set Track and Sector
',,3~555
AFN 01467B
!
80150/80.150·2
iAPX 86150,88/50,186/50,188/50
fered on the 80150 or substitute or add any additional device drivers of his choice.
Read/Write Sector
Load Program
The BOOS in the 80150 provides the Same functions as, the standard Digital Research CP/M-86
BOOS.
BIOS - Basic Input/Output System
The BIOS contains the system-dependent I/O
drivers. The 80150 BIOS offers two fundamental
configuration options:
'
These two options negate the potential softwareon-silicon pitfall of inflexibility in system design.
The OEM can customize the end system as
desired.
The predefined configuration offers a choice
among several peripheral chip drivers included on
the 80150. Drivers for the following chips are included in the 80150 BIOS:
Universal Synchronous/
Asynchronous Receiver/Transmitter (USART)
Multi-Protocol Serial Controller
(MPSC)
Programmable Parallel Interface
(PPI)
Floppy Disk Controller
8251A
1. A predefined configuration which supports
minimum cost CP/M-86 microcomputer
systems and which requires no operating
system development by the system designer.
8274
2. An OEM-configurable mode, where the
designer can choose among several drivers of-
8272A
8255A
FLOPPY DISK
I
8088/8086180186180188
I--CPU
801bO
8272A
ADDRESSIDATA BUS
8251A
I
CONSOLE
8255A
I
PRINTER
Figure 4_ Predefined' Configuration
3-556
AFN 014678
80150/80150-2
iAPX 86150,88/50,186/50,188/50 ~@'¥l~OO©~ OOO!p@OO~~ii'O@~
•
Even in the predefined configuration, the system
designer (or end user, if the system designer
desires) may select parameters such as the baud
rates for the console and printer, and the floppy
disk size (standard 8" or 51A" mini-floppy) and
format (FM single density or MFM double density,
single-sided or double-sided).
peripheral chips, such as bubble memories or
more complex CRT controllers. These drivers
would be stored in memory external to the 80150
itself. By providing the configl,lrability option, the
80150 is applicable to a far broader range of
designs that it would be with an inflexible BIOS.
Drivers for the 80150 on-chip timers and interrupt
controller are also included in the BIOS.
MEMORY ORGANIZATION
When using the predefined configuration of the
80150. BIOS, the 80150 must be placed in the top
16K of the address space of the microprocessor
(starting at location FCOOOH) so that the 80150
gains control when the microprocessor is reset.
Upon receipt of control, the 80150 writes a configuration block into the bottom of the microprocessor's address space, which must be in
RAM. The 80150 uses the area after the interrupt vectors for system configuration information
, and scratch-pad storage.
The 80150 takes advantage of the 80186 and 80188
on-chip peripherals in an iAPX 186/50 or 188/50
system. For example, the integrated DMA controller is
used. Also fully utilized are the integrated memory chip
selects and I/O chip selects.
Since all microcomputer configurations cannot
be anticipated, the OEM-conflgurable mode
allows the system designer to use any set of
peripheral chips desired. This configuration is
shown in Figure 5.
'
By simply changing the jump addresses in a configuration table, the designer can also gain the
flexibility of adding custom BIOS drivers for other
When using the OEM-configurable mode of the
80150.BIOS, the 80150 is placed on any 16K boun-
FLOPlDISK
80881808~':."J86180188 f - -
80150
OTHER
PERIPHERALS
8272A
ADDRESS/DATA BUS
8251A
8255A
I
ASYNCHRONOUS _
COMMUNICATIONS,
CONSOL~
I
KEYBOARD,
PARALLEL PRINTER
8274
I
SYNCHRONOUS UNE,
SERIAL PRINTER,
CONSOLE
SERIAL PRINTER
Figure 5. OEM Configurable System
3-557
AFN 014678
inter
80150/80150.~2
iAPX 86150,88/50,186/50,188/50. L!),[Q)WL!),OO©rg UOOI¥@iruli'!.iJL!),1rO@OO
daryof memory except the highest (FCOOOH) or
lowest (OOOOOH). The user writes interface code (in
the form of a simple boot ROM) to incorporate and'
link additional features and changes into the
standard 80150 environment. The configuration
block may be located as desired in the address
space, and its size may vary widely depending on
the application.
Memory Disk
A unique capability offered by the 80150 is the
Memory Di,sk. The Memory Disk Consists of a
block of RAM whose Size can be selected by the
designer. The Memory Disk is treated by the
BOOS as any standard floppy disk, and is one of
the 16 disks that CPIM can address. Thus files can
be opened and closed, programs stored, and
statistics gathered on the amount of Memory Disk
space left.
The Memory Disk opens the possibility of a par-'
table low-cost diskless microcomputer or network
station. Applications software can be provided in
a number of ways:
a. t.elephone lines via a modem.
b.ROM-based soft,ware.
c. a network.
d. bubble memory based software.
e. low-cost cassettes.
TYPICAL SYSTEM CONFIGURATiON
figure 6 shows the processing cluster of a
"typical" iApX 86/50 or iAPX 88/50 OSP system.
Not shown are subsystems likely to vary with the
application. The configuration includes an 8086
(or 8088) operating in maximum mode, an 8284A
clock generator and an 8288 system controller.
Note that the 80150 is located on the CPU side of
any latches or transceivers.
Timers
The Timers are connected to the lower half of the
data bus and are addressed at even addresses.
The timers are read as two successive bytes,
I
61
eLK
CONTROL
52
eLK
so
8086
I
BHE
SHE
A19
,
A19
LOCAL
AND
I
, I
!NT
SYSTEM
RESOURCES
ADO
AO
015
8286
00
INT
eLK
52
so
Figure 6. Typical OSP Configuration
3-558
AFN 01467B
80150/80150-2
iAPX 86150,88/50,186/50,188/50
always LSB followed by MSB. The MSB is always
latched on a read operation and remains latched
until read. Timers are not gatable. An external
8254 Programmable Interval Timer may be added
to the system.
Baud Rate Generator
The baud rate generator operates like an 8254
(square wave mode 3). Its output, BAUD, is initially
high and remains high until the Count Register is
loaded. The first falling edge of the clock after the
Count Register is loaded causes the transfer of
the internal counter to the Count Register. The
output stays high for N/2 [(N + 1)/2 if N is odd] and
then goes low for N/2 [(N - 1)/2 if N is odd]. On the
falling edge of the clock which signifies the final
count for the output in low f state, the output
returns to high state and the Count Register is
transferred to the internal counter. The baud rates
can vary from 300 to 9600 baud.
The baud rate generator is located at OCH (12),
relative to the 16-byte boundary in the I/O space in
which the 80150 component is located. The timer
control word! is located at relative address,
OEH(14). Timers are addressed with lacs = O.
Timers 0 and 1 are assigned to use by the aSP,
and should not be altered by the user.
The 80150 timers are subset compatible with 8254
timers.
Interrupt Controllet
The Programmable Interrupt Controller (PIC), is
also an integral unit of the 80150. Its eight input
pins handle eight vectored priority interrupts. One
of these pins must be used for the SYSTICK time
function In timing walts, using an external con·
nection as shown. During the 80150 initialization
and configuration sequence, each 80150 interrupt
pin is individually programmed as either level or
edge sensitive. El(ternal slave 8259A interrupt
controllers can be used to expand the total
number of interrupts to 57.
In addition to standard PIC functions, the 80150
PIC unit has an LlR output signal, which when low
indicates an interrupt acknowledge cycle. LlR = 0
is provided to control the 8289 Bus Arbiter
SYSB/RESB pin. This wi" avoid the need of requesting the system bus to acknowledge local
bus non-slave interrupts. The user defines the interrupt system as part oUhe configuration.
INTERRUPT SEQUENCE
The interrupt sequence is as follows:
1. One or more of the interrupts is set by a lowto-high transition on edge-sensitive IR inputs
or by a high input on level-sensitive IR inputs.
2. The 80150 evaluates these requests, and
sends an INT to the CPU, if appropriate.
3. The CPU acknowledges the INT and responds
with an interrupt acknowledge cycle which is
encoded in S2 - SO.
4.
Upon receiving the first intefrupt acknowledge
from the CPU, the highest-priority interrupt is
set by the 80150 and the corresponding edge
detect latch is reset. The 80150 does not drive
the address/data bus during this bus cycle but
does acknowledge the cycle by making
ACK = 0 and sending the LlR value for the IR
input being acknowledged.
5. The CPU wi" then initiate a second interrupt
acknowledge cycle. During this cycle, the
80150 wi" supply the cascade address of the
interrupting input at T 1 on the bus and also
r.elease an 8-bit pOinter onto the bus if appropriate, where it is read by the CPU. If the
80150 does supply the pointer, then ACK wi"
be low for the cycle. This cycle also has the
value LlR for theiR input being acknowledged.
6. This completes the interrupt cycle. The ISR bit
remains set until an appropriate EXIT INTERRUPT primitive (EOI command) is called at the
end of the Interrupt Handler.
AFN 014678
&.@\Vl&.~(\;~ O~IP@IruIMl&''ii'O@~
80150/80150-2
iAPX 86150,88/50,186/50,188/50
ABSOLUTE MAXIMUM RATINGS·
'NOTICE: Stresses above those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. ThIs is a stress rating only and functional operation
of the device at these or any other condItions above those
indicated in the operational seciions of this specIficatIOn
is not implied. Exposure to absolute maxImum rating conditIons for extended penod may affect devIce reliabIlity.
, Ambient Temperature Under Bias ........ O·C to 70·C
Storage Temperature ................. -65°C to 150'C
Voltage on Any Pin With
Respect to Ground ......... ~ .
- 1.0V to + 7V
Power Dissipation .........
. 1 OWatts
D.C. CHARACTERISTICS
(TA =O°C to 70°C Vcc =4.5 to 5.5V)
Test Conditions
Min.
Max.
Units
V'L
V,H
Input Low Voltage
- 0.5
0.8
V
Input High Voltage
2.0
Output Low Voltage
Vcc +.5
0.45
V
VOL
VOH
Icc
Power Supply Current
200
rnA
T,
III
Input Leakage Current
10
MA
IlR
IR Input Load Current
10
-300
MA
MA
ILO
Output Leakage .Current
10
~A
0"" Y'N < Vce
Y,N - Vcc
Y'N = 0
.45 "" Y'N <0 VCC
Clock Input Low
0.6
V
pF
Symbol
Vcu
VCHI "
Parameter
2.4
Output High VoHage
Clock Input High
V
10l
V
10H = -400MA
Input Capacitance
10
1/0 Capacitanc;e
15
pF
ICLI
Clock Input Leakage Current
10
150
10
MA
MA
MA
Symbol
(T, - 0-70°C Vec
Parameter
= 4 5-5 5 VoH Vss = Ground)
80150-2
Min.
80150
Max.
Min.
Max.
200
-
125
ns
55
44
200.0
ns
UnitS
CLK Cycle Period
CLKLowTime
90
-
TCHCl
CLK High Time
69
2000
TSVCH
TCHSV
Status Active Setup Time
-
65
10
ns
Status Inactive Setup Time
-
-
TSHCl
TClSH
55
ns
-
10
-
TASCH
Address Valid Setup Time
TCSCl
TCHCS
Chip Select Setup Time
20
-
0
-
ns
Address Hold Time
-
8
TCLAH
80
10
55
10
8
10
20
0
80
10
100
-
60
-
ns
10
-
ns
100
TOSCl
TCHOH
TJlJH
Status Active Hold Time
Chip Select Hold TIme
Write Data Setup TIme
Write Data Hold Time
IRLowTIme
10
Test Conditions
ns
ns
ns
ns
ns
".
ns
ns
Read Data Valid Delay
-
140
-
105
ns
Read Data Hold TIme
10
-
10
-
ns
TCLDX
Read Data to Roating
10
100
10
100
ns
TCLC'
Cascade Address Delay Time
-
85
-
65
ns
TCLDV
TCLOH
25 C
Y'N = Vee
Y'N = 2.5V
Y,N = OV
TClCl
TClCH
Status Inactive Hold Time
=
2mA
V
3.9
C'N
C,O
A.C CHARACTERISTICS
=
CL - 200 pF
AFN 014678
inter
80150/80150-2
iAPX 86150,88/50,186/50,188/50 &'IQ)W&'OO©[g ~OOIF©OO~&'ii~©OO
WAVEFORMS
A.C.
T2
T1
T4
T4
TW
• TCHCL
TelCH
ClK
TCHSV
52.51
TCLCl=--_ _--l
TSVCH
so-+----~--4_+-----~--------~------------------+_--~------~----+_------~-------------
I
BriE A
F~-----
A VALID
SHE. Ao"-ro.
lCSCl
'"
MEMCS"TS
WAITE CYCLE
I
~~T
ADDRESS VALID
-I
r-
TCHCS
TOSCL __
I. . . .
WRITE DATA VALID
TCSAK
TAACK
READ CYCLE
I
AD,!>-AD o
AC,K
I
TSACK
TClCF
2ND INTA CYCLE
I~
AD'5-AD o
FLOAT
ADDRESS VALID
FLOAT
CD CASCADE ADDRESS
TIAVE
TIAVE
NOTES
1 CASCADE ADDRESS PRESENTED ON ADS, AD9 AND A010 CORRESPONDING TO CASO. CASt
AND CAS2 RESPECTIVELY ADt 1-AOtS LINES ARE ACTIVE AND HAVE UNKNOWN VALUES ADO·AC7
ARE TRISTATE •
/"
2 POINTER VALUE IS ACTIVE ONLY IF POINTER IS GENERATED FROM THE 80150 AND NOT FROM
EXTERNAL SLAVE UNIT
ACTIVE LOW ONLY WHEN POINTER DATA IS BEING SUPPLIED BY THF 80150
LOW ONLY FOR LOCAL INTERRUPT
.,
POINTER
CD
FLOAT
inter
8282/8283
OCTAL LATCH
• Address Latch for'iAPX 86, 88, 186,
188, MCS·80®, MCS·85®, MCS·48®
Famlies
•
3·State Outputs
•
20·Pin Package with 0.3" Center
•
High Output Drive Capability for
Driving System Data Bus
•
No Output Low Noise when Entering
or Leaving High Impedance State
•
Fully Parallel 8·Bit Data Register and
Buffer
•
•
Transparent during Active Strobe.
Available in. EXPRESS
- Standard Temperature Range
- Extended Temperature Range
The 8282 and 8283 are 8·bit bipolar latGhes with 3·state output buffers. They can be used to Implement latches, buffers,
or multiplexers. The 8283 invertll the input data at its outputs while the 8282 does not. Thus, all of the principal periph·
eral and input/output functions of a microcomputer system can be implemented with these devices.
DIS
Ole
Figure. 1. Logic Diagrams
7
Figure 2. Pin Configurations
3-562
inter
8282/8283
Table 1. Pin Description
Pin
STB
5E
010- 01 7
000-00 7
(8282)
DOO-~7
(8283)
FUNCTIONAL DESCRIPTION
Description
STROBE (Input). STB Is an Input control
pulse used to strobe data at the data Input
pins (Ao-A7) into the data latches. This
signal Is active HIGH to admit input data.
The data is latched at the HfGH to LOW
transltl6n of STB.
OUTPUT ENABLE (Input). 5E is an input
control signal which when active LOW
enables the contents of th'e data latches
onto the data output pin (Bo-B7)' OE being
Inactive HIGH forces the output buffers to
their high Impedance state,
DATA INPUT PINS (Input). Data presented
. at these pins satisfying setup time reo
quirements when STB is strobed and
,latched Into the data input latches.
The 8282 and 8283 octal latches are 8·blt latches with
3·state output bUffers. Data having satisfied the setup
time requirements is latched into the data latches by
strobing the STB li'1e HIGH to LOW. Holding the STB
line in its active HIGH state makes the latches appear
transparent. Data is presented to the data output pins by
activating,the OE input line. When OE is Inactive HIGH
the output buffers are in their high impedance state.
Enabling or disabling the output buffers will not cause
negative·golng transiepts to appear on the data output
bus.
'
DATA OUTPUT PINS (Output). When OE Is
true, the data in the data latches is presented as Inverted (8283) or non·inverted
(8282) data onto the data 0l!tput pins.
3-563
AFN·OO727E
..
inter
828218283
ABSOLUTE MAXIMUM RATINGS·
F
.:
<'
'NOTICE: StresseS above those listed IInder "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functlQnal opere·
tlon of the device at these or any.othe,.corditlons above
tho,se indicated in the op.e.rational sections of this specifIcation Is not Implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
.
reliability.
Temperatura Under Bias ....•.. ; .... , .• : .O·C to 70·C
Storage Temj:lerature •............ "-65·C to + 150·C
All Output and Supply Voltages ......•• - 0.5V to + 7V
All Input Voltages ................... - 1.0V to + 5.5V
Power Dissipation.'.. ; •..................•.. 1 Watt
,
':
'
D.C. CHARACTI:RISTICS
Symbol
(Vcc = 5V ±10%. TA = O"C to 70"C)
Parameter
~ax.
Min.
Unit.
Test Condition.
Ve
Input Clamp Voltage
_1
V
Icc
Power Supply Current
160
mA
IF
Forward Input Current
-0.2
IR
Reverse Input Current
50
',.A
VR
VOL
Output low Voltage
.45
V
IOL
VOH
Output High Voltage
IOFF,
Output Off Current
V IL
Input low Voltage
VIH
Input High Voltage
C IN
VF = 0.45V
= S.25V
= 32mA ,'.
IOH = -5 mA
V
±50
,.A
0.8
V
Vee = 5.0V
See Note 1
V
Vee=5.0V
See Note 1
2.0
Input CapaCitance
mA
.
2.4
Ie = -5 rnA
12
VOF F = 0.45 to 5.25V
F= 1 MHz
V alAs = 2.5V. Vee = 5V
TA=25°C
pF
NOTE:
1. Output loading ioL = 32 mAo 10H
~
A.C. CHARACTERISTICS
Symbol
TIVOV
TSHOV
-5 mAo CL = 300 pF.'
(Vcc = 5V ±10"/o. TA = o·c to 70·C (See Note 2)
loading: Outputs-IOl = 32 mAo IOH = -5 mAo Cl
Parameter
= 300 pP)
Min.
Max.
Units
Input to Output Delay
-Inverting
-Non-Inverting
5
5
22
30
ns
ns.
STB to Output Delay
-Inverting
-Non-Inverting
10
10
40
45
ns
'ns
Test Conditions
(See Note 1)
TEHOZ
Output Disable Time
5
18
ns
TELOV
Output Enable Time
10
30
,ns
TIVSl
Input to STB Setup Time
0
ns
TSLIX
Input to.STB Hold Time
25
ns
TSHSl
STB High Time
15
ns
TOlOH
Input. Output Rise Time
20
ns
TOHOl
Input. Output Fall Time
12
ns
NOTE: .
1. See waveforms and test load circuit on following page.
2. For Extended Temperature EXPRESS the Preliminary Maximum Values are TIVOV
TSHOV = 45, 55; TEHOZ = ~5; TElOV = 50.
3-564
From O.BV to 2.0V
From 2.0V to O.BV
'Ct. = 200 pF for plastiC 8282/8283.
= 25 vs 22, 35 vs 30;
AFN'()0727E
8282/8283
A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUT/OUTPUT
2.4
=>(. __
TESTPOINTS_"''C
0.4'
A.C. TESTING. INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC "'" AND O.4SV FOR
A LOGIC "0" TIMING MEASUREMENTS ARE MADE AT '.5V FOR BOTH A
LOGIC "'" AND "0." INPUT RISE AND FALL TIMES ARE MEASURED FROM
O.8V TO 2.OV AND ARE DRIVEN AT 5ns ::t 2ns
OUTPUT TEST LOAD CIRCUITS
1.5V
1.5V
3312
r
OUT 0 - - -
300pF*
3-STATE TO VOL
2.14V
1802
r
OUT 0-----..
3OOpF*
3·STATE TO VOH
52.72
OUT 0 - -
r300PF*
SWITCHING
*200 pF for plastic 828218283.
3-565
, AFN·00727E
828218283
WAVEFORMS
STB
1\.
"-
•If
:....J'
OUTPUTS
V
\I
INPUTS
_nVSL _ _ f.TSLIX •
\
TSHSL~I\
)
.
V
\
I
\V
----C=
\
-~~"-VOH-.1V
f.TIVOV-
~------
.<\
SEE NOTE 1.
VOL +.1V
!---TSHOV-
NOTE: 1. OUTPUT MAY BE MOMENTARILY INVALIO FOLLOWING THE HIGH GOING STB TRANSITION.
2. ALL TIMING MEASUREMENTS ARE MADE AT 1.5V UNLESS OTHERWISE NOTED.
10
pFLOAD
pF LOAD
Output Da"y va. CapaCitance
AFN·00727,E
8284A/8284A·1
CLOCK GENERATOR AND DRIVER FOR
iAPX 86, 88 PROCESSORS
• Single +5V Power Supply
• Generate. the System Clock for the
IAPX.86, 88 Processors:
5 MHz, 8 MHz with 8284A
10 MHz with 82a4A-1
• Uses a.Crystal or a TTL Signal for
Frequency Source
• Generates System Reset Output from
Schmitt Trigger Input
•. Capable of Clock Synchronization with
Other 8284As
• Provides Local READY and Multibus™
READY Synch~nizatlon
• Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range
• 18·Pin Package
0
RES
D
RESET.
X1
X2
XTAl
OSCilLATOR
OSC
Fie
+3
PClK
SYNC
EFI
CSYNC
RDY1
READY
EFI
RDY1
ClK
AEN1
RDY2
AEN2
READY
FF1
ASYNC
·8284A/8284A-1 Block Diagram
3-567
8284A18284A-1 Pin
Conflguratl.on
intef
8284A18284A-1
Table 1. Pin Description
Name and Function
Symbol 'IftIe
Addre•• Enable: AEN Is an active lOW
I
signal. AEN serves to qualify its respective
Bus Ready Signal (RDYl or RDY2). AENl
validates RDVl while AEN2 validates RDY2,
Two AEN signal inputs are useful in system
configurations which permit the processor to
acc'ess two Multi-Master System, Busse~
non Multi-Master configurations the AEN
signal inputs 'are tied true (lOW).
RDY1,
RDY2,
I
BUI Ready: (Transfer Complete). RDY Is an
active HIGH signal which Is an indication from
a device located on the system data bus that
data has been received, or is available. RDYl
is qualified by AENl while RDY2 is qualified
CLK
0
Prace.lor Clock: ClK Is the clock output
used by the pro~r and all devices which
directly connect t the processor's local bus
(i.e., the bipolar support chips and other MOS
devices). ClK hes an output frequency which
Is 'AI pf the crystal or EFllnput frequency and a
'AI duty cycle. An output HIGH of 4.5 volts
(Vcc= 5V) Is provided on this plri to drive MOS
deviceS.
,
PClK
0
Peripheral CIocIl: PCLK Is a TTL level pe- ,
rlpheral clock signal whose output frequency
is 'h that of CLK and has a 50% duty cycle.
OSC
0
Oscillator Output: OSC is the TTL level output of the internal oscillator circuitry. Its frequency Is equal to that of the crYstal.
RES
I
Reset In: ~ Is an active lOW signal which
is used to generate RESET. The 8284A
provides a Schmitt trigger input so that an RC
connection can be used to establish the
power-up reset of proper duration.
RESET
0
Reaet: RESET Isan active HIGH signal which
is used to reset the 8086 family processors. Its
timing characteristics are determined by
RES.
CSYNC
I
Clock Synchronization: CSYNC is an active
HIGH signal which allows multiple 8284A8 to
be synchronized to provide clocks that are in
phase. When CSYNC is HIGH the internal
counters are reset. When CSYNC goes lOW
the internal counters are allowed to resume
counting. CSYNC needs to be externally synchronized to EFI. When using the internal oscillator CSYNC:: should be hardwired to
ground.
by~.
ASYNC
READY
I
0
Ready Synchronization Select: ASYNC is an
input which defines the synchronization
mode of the READY logic. When ASYNC Is
low, two stages of READY synchronization
are provided. When A~YNC IS left op'en
(internal pull-up resistor is provided) or HIGH
a single stage of READY syncl;lronization is
provided.
Ready: READY Is an active HIGH Signal
which is the synchronized RDY signal Input.
READY is cleared after the guaranteed hold
time to the processpr has been met.
Xl, X2
I
Cryatalln: Xl and X2 are the pins to which a
crystal is attached. The crystal frequency is 3
times the desired processor clock frequency.
F/C
I
Frequency/Cryatal Select: F/C Is astrapping
option. When strapped lOW, Fie permits the
processor's ,!:!ockto be generated by the crystal. When F/C is strapped HIGH, ClK is generated from the EFI Input.
EFI
I
External Frequency: When F/C is strapped
HIGH, CLK Is generated from the Input frequency appearing on this pin. The input
signal is a square wave 3 times the frequency
of the desired CLK output.
FUNCTIONAL DESCRIPTION
General
The 8284A Is a single chip clock generatorldriver for the
IAPX 86, 88 processors. The chip contains a crystalcontrolled oscillator, a divlde-by-three counter, complete MULTIBUSTM "Ready" synchronization and reset
logiC. Refer to Figure 1 for Block Diagram and Figure 2
for Pin Configuration.
Oscillator
The oscillator circuit of the 8284A is designed primarily
for use with an external series resonant, fundamental
mode, crystal from which the basic operating frequency
Is derived.
Name and Function
SYmbol 'IftIe
AE;\h,
AEN2
GND
Ground.
Vcc
Power: +5V supply.
The crystal frequency should be selected at three times
the required CPU clock. Xl and X2'are the two crystal
input crystal connections. For the most stable operation
of .the oscillator (OSC) output circuit, two series resistors ,
(Rl = R2 = 510 0) ~s shown in the waveform figures are
recommended. The output of the oscillator is buffered and
brought out on OSC so that ,other system timing signals
can be derived from this stable, crystal-controlled source.
For systems which have aVec ramp time ;;..lV/ms andlor
have inherent board capacitance between Xl or X2, exceeding 10 pF (not including 8284A pin capacitance), the
two 5100 resistors should be used. This circuit provides
optimum stability for the oscillator in such extreme conditions. It is advisable to limit stray capacitances to less than
10 pF on Xl and X2 to minimize deviation from operating
at the fundamental frequency.
3-568
AFN'()1472D
I
intJ
8284A/8284A~1
Master system Is not being used" the AEliI, pin should' be
tied lOW.
Clock Generator
The clock generator consists of a synchronous divideby-three counter with a special clear input that inhibits
the count,lng_ This clear Input (CSYNC) allows the output clock to be synchronized with an external event
(such as another 8284A clock). It is necessary to synchronize the CSYNC input to the EFI clock external to
the 8284A. This Is accomplished with two Schottky flipflops. The counter output is a 33% duty cycle clock at
one-thin! the input frequency.
Synchronization is required for all asynchronous activegoing edges of either RI?Y input to guarantee that the
ROY setup and hold times are met. Inactive-going edges
of ROY In normally ready systems do not require synchronization but must satisfy ROY setup lind hold as a
matter of proper system design ..
The ASYNC input defines two modes of. READY syn·
chronization operation.
The FIe input is a strapping pin that selects either the
crystal oscillator or the EFI input as the clock for the +3
counter. If the EFI input is selected as the clock source,
the oscillator section can be used independently for
another clock source. Output is taken from OSC.
When ASYNC is lOW, two stages of synchronization
are provided for active READY input signals. Positivegoing asynchronous READY inputs will first besynchronized to flip-flop one at the riSing edge of ClK
and then synchronized to flip-flop two at the next falling
edge of ClK, after which time the READY output will go
active,{HIGH). Negative-going aSynchronous READY inputs will be synchronized directly to flip-flop two at the
falling edge of ClK, after which time the READY output
will go inactive. This mode of operation is intended for use
by asynchronous (normally not ready) devices in the system which cannot be guaranteed by design to meet the
required ROY setup timing, TR1VCL, on each bus cycle.
Clock Outputs
The ClK output is a 33% duty cycle MOS clo~ driver
designed to drive the iAPX 86, 88 processors directly.
PClK is a TTL level peripheral clock signal whose output frequency is 1;2 that of ClK. PClK has a 50% duty
cycle.
Reset Logic
The reset logic provides a Schmitt trigger input (FiES)
an'd a synchronizing flip·flop to generate the Jeset
timing. The reset signal Is synchronized to the falling
edge of ClK. A simple RC network can be used to
provide power-on reset by utilizing this function of the
8284A.
READY Synchronization
When ASYNC is high or left open, the first READY flipflop is bypassed in the READY synchronization logic.
READY inputs are synchronized by flip-flop two on the
falling edge of ClK before they are presented. to t~e
processor. This mode is available for synchronous
devices that can be guaranteed to meet the required
ROY setup time.
Two READY Inputs (RDY1, RDY2) are provided to accommodate two Multi-Master system busses. Each input
has a qualifier (AEN1 and AEN2, respectively). The AE1ii
signals validate their respective, ROY signals. If a Multi-
ASYNC can be changed.on every bus cycle to select the
appropriate mode of synchronization for each device in
the system.
CLOCK
SyNCHRONIZE
~
>--+---+-1 0
EFI >-.....-I>c-~ >
t
Q
o
Q
~------
Figure 3_ CSYNC Synchronization'
AFN·01472D
8284A/8284A-'
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias ................. O·C to 70·C
storage Temperature .............. -65·C to + 150·C
All Output and Supply Voltages ......... - 0.5 V to + 7V
AI/Input Voltages ................... -1.0V to + 5.5V
PO,wer Dissipation ......... : .. '........ " .... 1 Watt
'NOTlCE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional oper~tion of the device at these or any other conditio;1s above
those indicated i~ the operational sections of thissPecification is not implied. Exposure ~o, absolute maximum
rating conditions for extended periods may affect device
reliability.
.
.
D.C. CHARACTERISTICS (TA= O·Cto 70·C, Vcc';'" 5V ± 10%)
Test' Conditions
Mai.
Units
IF
Forward Il'lput Current (ASYNC)
Other Inputs
-1.3
-0.5
mA
mA
, VF=0.45V
VF=0.45V
IR
Reverse Input Current (ASYNC)
Other Inputs
50
50
~
~
VR=Vcc
VR=5.25V
Ic= -5mA
Parameter
Symbol
Min.
Vc
Input Forward Clamp Voltage
-1.0
V
Icc
Power Supply Current
162
mA
VIL
l(lput LOW Voltage
VIH
Input HIGH Voltage
0.8
V
2.0
V
VIHR
Reset Input HIGH Voltage
VOL
Output ,LOW Voltage
.2.6
V
V
5mA
VOH
Output HIGH Voltage CLK
Other Outputs
4
2.4
V
V
-1mA
-1mA
VIHR- VILR
RES Input Hysteresis'
0.25
V
0.45
A.C. CHARACTERISTICS (TA=O·C to 70·C, Vcc=5V± 10%)
,
TIMING REQUIREMENTS
Symbol
Parameter,
Min.
Max.
Units
Test Conditions
tEHEL
External Frequency HIGH Time
13
ns
tELEH
External Frequency LOW Time
13
ns
10% -10% VIN
EFI Period
33
ns
(Note 1)
tELEL '
90% -90% VIN
XTAL Frequency
12
tRlVCL
RDY1, RDY2 Active Setup to CLK
35
ns
ASYNC=HIGH
tRlVCH
RDY1, RDY2 Active Set4P to CLK
35
ns
ASYNC=LOW
tRlVCL
RDY1, RDY2 Inactive Setup to CLK
35
ns
tCLR1X
RDY1, RDY2 Hold to CLK
tAYVCL
ASYNC Setup to CLK
tCLAYX
ASYNC Hold to CLK
tAlVRlV
AEN1,
tCLA1X
tYHEH
25
t-AHz
0
ns
50
ns
0
ns
15
ns.
AEN1, AEN2 Hold to.CLK
0
ns
CSYNC Setup to EFI
20
ns
tEHYL
CSYNCHold to EFI
10
ns
tYHYL
CSYNC Width
2·tELEL
ns
65
ns
(Note 1)
20
ns
(Note 1)
A'E'N2 Setup to
tl1HCL
m
tCLllH
RES Hold to CLK
RDY1, RDY2
Setup to CLK
3-570
AFN'()1472D
inter
8284A/8284A-1
A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES
Symbol
Min. 8284A·1
Min. 8284A
Parameter
Max.
Un".
125
100
ns
CLK HIGH Time
(Y3 tCLcLl+2
39
ns
tCLCH
ClK lOW Time
(% tCLcLl-15
53
ns
tCH1CH2
tCL2CL1
ClK Rise or Fall Time
tpHPL
PClK HIGH Time
tCLCL -20
tcLCL-20
tpLPH
PClK lOW Time
tCLCL -20
tcLCL -20
ns
tRYLCL
Ready Inactive to ClK (See Note 3)
-8
-S'
ns
tRYHCH
Ready Active to ClK (See Note 2)
(% t cLcLl-15
53
ns
tCLCL
Ct,.K Cycle Period
tCHCL
10
Test Conditions
. 1.0V to 3.5V
ns
ns
ns
tCUL
ClK to Reset Delay
40
t CLPH
ClK to PClK HIGH DELAY
22
ns
tCLPL
ClK to PClK lOW Delay
22
ns
t OLCH
OSC to ClK HIGH Delay
-5
-5
22
ns
tOLCL
OSC to ClK lOW Delay
2
2
35
ns
tOLoH
Output Rise Time (except ClK)
20
ns
From O.SV to 2.0V
tOHoL
Output Fall Time (except ClK)
12
ns
From 2.0V to O.8V
NOTES:
1. Setup and hold necessary only to guarantee recognition at next clock.
2. Applies only to T3 and TW states.
3. Applies only to T2 states.
A.C. TESTING INPUT, OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
INPUT/OUTPUT
..., VL
= '.oav
~l == 3~5n
DEVICE
UNDER
rEST
,..--------1
I
CL
a
A C. TESTING. INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC "1" AND 45V
FOR A LOGIC "0." TIMING MEASUREMENTS ARE MADE AT 1.5V FOR
BOTH A LOGIC "1" AND "0." INPUT RISE AND FALL TIMES (MEASURED
BETWEEN a.sv AND 2 av) ARE5 ± 2 NS.
CL
= 100pF FOR CLK
CL =
3-571
30pF FOR READY
AFN-01472D
8284A18284A.1
"I", '
WAVEFORMS
CLOCKS AND RESET'SIGNALS
NAME
EFI
OSC
ClK
0
PClK
0
CSYNC
I
RESET
0
______~,~--~------~--~~~t:
NOTE: All TIMING MEASUREMENTS ARE MADE AT 1.5 VOLTS, UNLESS OTHERWISE NOTID.
READY SIGNALS (FOR ASYNCHRONOUS DEVICES)
ClK
RDY1,2
READY
tRYHCH
3-572
AFN.o1472D
intJ
8284A/8284A-1
WAVEFORMS (Continued)
READY SIGNALS (FOR SYNCHRONOUS DEVICES)
eLK
RDY1,2
IA1AtV
MYNe _ _ _ _ _ _J'
READY
tRYLCL
24 MHz
""
Rl
":"
":"
X1
$
I
ClK
L
.
X2
lOAD
(SEE NOTE 1)
.1
FIe
I
CSYNC
..1:
R1 = R2 = 5100.
Clock High and Low Time (Using X1, X2}.
PULSE
1 GENERATOR
I
I
EFI
VL
I
lOAD
L (SEE NOTE 1)
elK
I
F/C!
/
r
CSYNC
-
Clock High and Low Time (Using EFI)
3-573
AFN.Q1472D
8284A/8284A~1
inter
VCC
AEm
ClK
X1
READY
24MHz CJ
X2
RDY2
OSC
FIC
AEN2
CSYNC
Ready to Clock (Using X1, X2)
~~--~EFI
ClK~----~
FIC
Al:J'fj
r------t RDY2
AEN2
CSYNC READYi--------f
NOTES:
Ready to Clock (Using EF,I)
1 CL=l00pF
2 CL=30pF
3-574
AFN·01472D
8286/8287
OCTAL BUS TRANSCEIVER
•
Data Bus Buffer Driver for iAPX
86,88,186,188, MCS·80™, NlCS·85™,
and MCS·48™ Families
•
High Output Drive Capability for
Driving System Data Bus
•
Fully Parallel 8·Bit Transceivers
•
3·State Outputs
•
20·Pln Package with 0.3" Center
•
No Output Low Noise when Entering
or Leaving High Impedance State
•
Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range
The 8286 and 8287 are 8-bit bipolar transceivers with 3-state outputs. The 8287 inverts the input data at its outputs
while the 8286 does not. Thus, a wide variety of applications for buffering in microcomputer systems can be met.
AO
vcc
AO
vce .
A1
BO
A1
110
ifi
52
IJ3
ii4
B1
B2
B3
B4
Bs
as
B6
lIS
B7
B7
GND
T
GND
Figure 2. Pin Configurations
Figure 1. Logic Diagrams
3-575
T
8286/8287
Table 1. Pin Description
Symbol
lYPe
Name and Fu"ctlon
T
I
Transmit: T Is an input contr~1 signal used to control the direction of the transceivers. When HIGH,
it configures the transceiver's 80-8;- as outputs with Ao-A7 as inputs. T LOW configures Ao-A7 as
the outputs with Bo-8;- serving as the Inputs.
OE
I
Output Enable: OE is an input control signal used to enable the appropriate output driver (as
selected by
onto its respective bus. This Signal is active LOW.
Ao-A7
I/O
Local Bus Da.. Pins: Thase pins serve to either present data to or accept data from the processor's
local bus depending upon the state of the T pin.
80-8 7(8286)
B;i-B7(8287)
1/0
System Bus Da.. Pins: These pins serve to either present data to or accept data from the system
bus depending upon the state of the T pin.
n
FUNCTIONAL DESCRIPTION
The 8286 and 8287 transceivers are 8-bit transceivers with
high impedance outputs. With T active HIGH and DE active LOW, data at the Ao-A7 pins is driven onto the Bo-B7
pins. With T inactive LOW and Of active LOW, data at the
Bo-B7 pins is driven onto the Ao-A7 pins. No output low
glitching will occur whenever the transceivers are entering or leaving the high Impedance state.
3-576
AFN·Ol5060
inter
8286/8287
TEST LOAD CIRCUITS
1.5V
OUT
~=
I
2.14V
1.SV
300PF
~n~
680
r
OUT
OUT
300pF'
'
3·STATE TO VOL
3·STATE TO VOL
SWITCHING
B OUTPUT
A OUTPUT
B OUTPUT
1.SV
1.SV
2.28V
1802
OUT
900Q
OUT
OUT
~"~
r
OOPF
3-STATE TO VOH
3·STATE TO VOH
B OUTPUT
A OUTPUT
SWITCHING
A OUTPUT
'200 pF for plastic 8286/8287
;
3-577
AFN.()1506D
intJ
8286/8287
ABSOLUTE MAXIMUM RATINGS·
*NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause perm,anent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not Implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Temperature Under Bias .•...•...•..••..• O·C to 70·C
Storage Temperature ....•........ - 65·C to + 150·C
All Output and Supply V,oltages ...•...• - 0.5V to + 7V
All Input Voltag~s .................. - 1.0V to + 5.5V ,
Power Dlsslp~tlon ..•.•••..••..••.•.•.•••.•. 1 Watt
D.C. CHARACTERISTICS
(Vcc = +5V ±10%, TA= O"C to 70"C)
Max
Units
Vb
Input Clamp Voltage
Min
-1
V
Icc
Power Supply Current-8287
-8286
130
160
mA
mA
IF
Forward Input Current
-0.2
mA
VF=0.45V
IA
Reverse Input Current
50
~
VA= 5.25V
VOL
Output Low Voltage -BOutputs
-A Outputs
.45
.45
V
V
IOL =32 mA
IOL = 16 mA
VOH
Output High Voltage -B Outputs
-A Outputs
V
V
IOH=-5 mA
IOH=-l mA
IOFF
IOFF
Output Off Current
Output Off Current
VIL
Input Low Voltage
VIH
Input High Voltage
CIN
Input Capacitance
Parameter
Symbol
-
2.4
2.4
VO FF=0:45V
VQFF=5.25V
IF
IA
-A Side
-8 Side
Test Conditions
Ic=-5 mA
0.8
0.9
2.0
12
V
V
Vee = 5.0V, See Note 1
Vee = 5.0V, See Note 1
V
Vee = 5.0V, See Note 1
pF
F= 1 MHz
V BIAS =2.5V, Vee=5V
TA =25·C
NOTE:
1. B OutpUts-IoL = 32 mA, IoH = -'5 mA, Or.. = 300 pP: A OutPUts-IoL = 16 mA, IoH = -1 mA, Or.. = 100 pF.
A.C. CHARACTERISTICS
(Vee = +5V ±lO%,TA = O"C to 70·C) (See Note 2)
Loading: B Outputs-loL = 32 mA, IOH = -5 mA, C L "" 300 pP
A Outputs-IOL = 16 mA, IOH = -1 mA, CL = 100 pF
Sy",bol
Parameter
TIVOV
Input to Output Delay
Inverting
Non-Inverting
Mex
Unite
5
5
22
'30
ns
ns
TEHTV
Transmit/Receive Hold Time
TTVEl
Transmit/Receive SetuD
TEHOZ
Ojjtput Disable Tlme
5
16
ns
OutDut Enable Time '
10
TElOV
TOlOH
.
Min
TOHOl
I
5
Test C:ondHlons
(See Note 1)
ns
10
ns
30
ns
Input, Output Rise Time
20
ns
From 0.6 V to 2.0V
Input, Output Fall Time
12 '
ns
From 2.0V to 6.0V
Or.. - 200 pF for plastiC 6266/6287
'NOTE:
•
1. See waveforms and test load circuit on following pagll.,
2. For Extended Tllmparature El(PRESS the Preliminary Maximum Values are TIVOV
TEHOZ
25; TElOV
50.
. '
=
= 25 vs 22, 35 vs 30;
=
I
3-578
AFNoQl506D
inter
8286/8287
WAVEFORMS
'W
INPUTS
11\
V,
\
J
-TiyOY_
I\,
-
'TEHOZ -
TELOY-'VOH - .W
\V
OUTPUTS
.
JI\
~-----VOL +.W
C
T----~r----f---TEHTY-
I--TTVEL
NOTE:
1. All timing measurements are made at 1.5V unless otherwise noted.
8287
8286
40
10
200
pF LOAD
400
soo
800
1000
pF LOAD
Output Delayver.u. Capacitance
a-:S79
AFN·OI506D
inter "
..
."
,'.
:
8288
BUS CONTROLLER
FOR iAPX 86, 88 PROCESSORS
• Bipolar Drive Capability
',I
• Conflgurable for Use with an I/O Bus
• Facilitates Interface to One or TWo
Multl~Master Busses
• Provides Advanced Commands
• Provides Wide Flexibility In System
Configurations
• Available In EXPRESS
- Standard Temperature Range
- Extended Temperature Range
• 3-State Command Output Drivers
The Intell!> 8288 Bus Controller is a 20-pin bipolar component for use with medlum-ta-Iarge iAPX 86, 88 processing
, systems. The bus controller provides command and control timing generation as well as bipolar bus drive capability while
optimizing system' performance.
'A strapping option on the bus controller configures it for use with a,multi-master system bus and separate VO bus.
STA~: {~!!--
iii1Ii5!:
STATUS
DECODER
S2
lOB
-. MWfC
COM·
MAND
SIGNAL
GENER·
ATOR
AMWC
10RC
iOWC
MULTIBUS'M
COMMAND
SIGNALS
iNTA
CDNTROL
INPUT
{CLK- •
AEN
CEN-
CONTROL
LOGIC
CONTROL
SIGNAL
GENER·
ATOR
108-
+5V
so
51
52
DT/R
AIOWC
DT/R}
DEN
MCElPDEN
ALE
,
ADDRESS LATCH.
DATA
TRANSCEIVER, AND
INTERRUPT CONTROL
SIGNALS
VCC
ClK
MCElPDEN
ALE
DEN
AEN
CEN
MRD~
INTA
AMWC
10RC
MWTC
GND
AIOWC
iOWC
GND
Figure 2.
Pin Configuration
Figure 1. Block Diagram
"
3-580
8288
Teble1. Pin Description
Symbol
1P
GND
So. s,. S2
~e
Stetul Input Plnl: These pins are tha
status input pins from the 8086. 8086 or
8089 procaseors. The 8288 decodes thess
Inputa to generate command and control
Signals at the appropriate time. When
thess pins are not In use (passive) they ara
all HIGH. (See chart under Command and
Control logic.)
l
Clock: This Is a 'clock signal from the
8284 clock generator and serves to establish when command and control signals
ara generated.'
ALE
0
Addre.. Latch Enable: This signal
serves to atrobe an address Into the
address latches. This signal Is active HIGH
and latching occurs on the tailing (HIGH
to LOW) transition. ALE Is intended for
use with transparant 0 type latches.
DEN
0
Da. Enable: This Signal serves to enable data transcelvars onto either the
local or syatem data bus. This Signal Is
active HIGH.
DT/R
0
Data "InInllllltJR_lve: This signal ....
tabllshes the direction of data flow
through the transceivers. A HIGH on this
,line indicates Transmit (write to 110 or
memory) and a LOW indicates Receive
(Read).
I
Addre81 Enable: AEN enables command
outputs of the 8288 Bus Controller et least
115 ns sfter it becomes active (LOW). AEN
going inactive immedlatell2:.Btates the
command output drivers. AEN does not
affect the I/O command lines If the 8288 is
In the 110 Bus mode (lOB tied HIGH).
CEN
I
Command Enable: When this Signal Is
LOW all 8288 command outputs and the
DEN and PDEN control outputs ara forced
to their Inactive state. When this Signal is
HIGH. thess same outputs are enabled.
lOB
I
Input/Outpul aul Mode: When the lOB is
strapped HIGH the 8288 functions In the
I/O Bus mode. When it Is strapped LOW.
the 8288 functions in the System Bus
mode. (See sections on 110 Bus and System Bus modes).
Advanced I/O Write Command: The
AIOWC Issues an 110 Write Command
earlier In the machine cycle to give 116
devices an early Indlcstlon of a write Instruction. Its timing Is the sema as a read
command signal. AIOWC is active LOW.
'IOWC
0
110 Write Command: This command line
'instructs an I/O device to read the data on
the data bus. This signal Is active LOW.
10RC
0
110 Read Command: This command line
instructs an I/O device to drive Its data
onto the data bus. This Signal Is active
LOW,
AMWC
, 0
Advanced Memory Write Com·
mand: The AMWC Issues a mamo,ry write
command earlier In the machine cycle to
give memory devices an early Indication
of a write Instruction. Ita tlmlnMc
the
same. a read command Signal.
II
active L O W . '
,
MWTC
0
Memory Write Command: Thil' command line instructs the memory to record
the data pressnt on the data bUI. This
8ignal Is active LOW.
MRDC
0
Memory Read Command: This com·
mand line Instructs the memory to drive
Its data onto the data bus. This signal ia
active LOW.
INTA
0
Interrupt ADIen_ledge: This command
line tells an interrupting device that Its
interrupt has be'en acknowledged and
that it should drive vectoring informatIOn
onto the data bus. This signal is active
LOW.
M9E1PDEN
0
This Is a dual function pin.
MCE (tOB II tied LOW): Master Cascade
Enable occurs during an interrupt sequence and serves to read a Cascade
Address from a master PIC (Priority Interrupt Controller) onto the data bus. The
~ignal'is active HIGH.
PDEN (lOB II tied HIOH): Peripheral
Data Enable enables the data bus transcelver for the 110 bus that DEN performs
for the system bus. POEN is active LOW.
,
3-581
N..... and Funcllon
0
AlOWC
Gtound.
I
CLK
AEN
Symbol
Name and Funcllon
Power: +5V supply.
Vcc
AFN'()1504C
intel
8288
FUNCTIONAL DESCRIPTION
Command and Control Logic
The command logic decodes the three 8086, 8088 or 8089
CPU status lines (So. 81, S2l to determine what command
is to be issued.
This chart shows the meaning of each status "word".
INTA (Interrupt Acknowledge) acts as an I/O read during
an interrupt cycle. Its purpose is to inform an interrupting device that·its Interrupt is being acknowledged
and that it should place vectoring information onto the
datil bus.
CO,NTROL OUTPUTS
s;
S; SO
0 0
0 ,,0
0 1
0 1
1 0
1 0
1
1
1
1
0
1
0
1
0
1
0
1
Processor Siale
InterruotAcknowledae
Read I/O Port
Write I/O Port
Halt
Code Access
Read Memory
,
Write Memorv '
Passive
8288Command
INTA
iORc
iOWc,AIOWC
None
MRoC
MRDC
MWTC;AMWC
None
The command is issued in one of two ways dependent
on the nnode of the 8288 Bus Contrqller.
I/O Bus Mode - The 8288 is fn the I/O Bus mode if the
lOB pin is strapped HIGH. In the 1/0 ,Bus mode all I/O
command lines (IORC, 10WC, AIOWC, INTA) are always
enabled (i.e., not dependent on AEN). When an I/O com·
mand is initiated by the processor, the 8288 immediately
activates the command lines using PDEN and DTIR to
control the I/O bus transceiver. The I/O command lines
should not be used to control the system bus in this
configuration because no arbitration is present. This
mode allows one 8288 Bus Controller to handle two ex·
ternal busses. No waiting is involved when the CPU
wants to gain access to the I/O bus. Normal memory ac·
cess requires.a "Bus Ready" signal (AEN LOW) before it
will proceed. It is advantageous to use the lOB mode if
I/O or peripherals dedicated to one processor exist in a
multi·processor system.
System Bus Mode - The 8288 is in the System Bus mode
if the lOB pin is strapped LOW. In this mode no command
is issued until 115 ns after the AEN Line is activated
(LOW). This mode assumes bus arbitration logic will inform the bus controller (on the AEN line) when the bus is
free for use. Both memory and I/O commands wait for bus
arbitration. This mode is used when only one bus exists.
Here, both I/O and memory are shared by more than one
processor.
COMMAND OUTPUTS
The advanced write commands are made available to initiate write procedures early in the machine cycle. This
signal can be used to prevent the processor from entering an unnecessary wait state.
The command outputs are:
MRDC
MWTC
10RC
10WC
AMWC
AIOWC
INTA
-
Memory Read Command
Memory Write Command
I/O Read Command
I/O Write Command
Advanced Memory Write Command
Advanced I/O Write Command
Interrupt Acknowledge
The control outputs 01 the 8288 are Data Enable (DEN),
Data Transmit/Receive (DTii'i) and Master Cascade
Enable/Peripheral Data Enable (MCE/PDEN). The DEN
signal determines wherr the external bus should be
enabled onto the local bus and the DT/R determines the
direction of data transfer. These two signals usually go
to the chip select and direction pins of a transceiver.
The MCE/PDEN pin changes function with the two
modes of the 8288. When the 8288 is in the lOB mode
(lOB HIGH) the PDEN signal'serves as a dedicated data
enable signal for the I/O or Peripheral System bus.
INTERRUPT ACKNOWLEDGE AND MCE
The MCE signal is used during an interrupt acknowledge cycle if the 8288 is in the System Bus mode (lOB
LOW). During any interrupt sequence there are two interrupt acknowledge cycles that occur back to back. During the first interrupt cycle no data or address transfers
take place. Logic should be provided to mask off MCE
during this cycle. Just before the second cycle begins
the MCE signal gates a master Priority Interrupt Controller's (PIC) cascade address onto the processor's
local bus where ALE (Address Latch Enable) strobes it
into the address latches. On the leading edge of the
second interrupt cycle the addressed slave PIC gates an
interrupt vector onto the system data bus where it is
read by the processor.
If the system contains only one PIC, the MCE signal is
not used. In this case thesecooo Interrupt Acknowledge
signal gates the interrupt vector onto the processor bus.
ADDRESS LATCH ENABLE AND HALT
Address Latch Enable (ALE) occurs during each machine
cycle and serves to strobe the current address into the
~d~ss latches. ALE also serves to strobe the status (So,
51, S2l into a latch for halt state decoding.
COMMAND ENABLE
The Command Enable (CEN) input acts as a command
qualifier for the 8288. If the CEN pin is high the 8288
functions normally. If the CEN 1Jin is pulled LOW, all
command lines are held in their inactive state (not
3'state). This feature can be used to implement memory
partitioning and to eliminate address conflicts between
system bus devices and resident -bus devices.
AFN·01504C
8288
ABSOLUTE MAXIMUM RATINGS*
·NOTlCE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at th.ese or any other conditions above
those indicated in the operational sections of thisspecification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect'device
reliability.
Temperature Under Bias .................. O·C to 70·C
Storage Temperature ............... -65·C to +150·C
All Output and Supply Voltages ......... -0.5V to + 7V
All Input Voltages .................... -1.0V to +5.5V
Power Dissipation ........................... 1.5 Watt
D.C. CHARACTERISTICS
Symbol
Ve
(Vee = 5V ± 10%, TA = O·C to 70·C)
Parameter
Input Clamp Voltage
Min.
Max.
-1
Unit
V
Test Conditions
Ie = -5 mA
Icc
IF
IR
Power Supply Current
Forward Input Current
:!30
-0.7
mA
mA
VF = 0.45V
Reverse Input Current
50
/LA
VR = Vee
VOL
Output low Voltage
Command Outputs
Control Outputs
Output High Voltage
Command Outputs
Control Outputs
0.5
0.5
V
V
IOL = 32 mA
IOL=16mA
2.4
2.4
10H =-5mA
10H = -1 mA
V1L
VIH
Input low Voltage
Inp_ut High Voltage
2.0
V
V
V
V
10FF
Output Off Current
VOH
A.C. CHARACTERISTICS
0.8
100
VOFF = 0.4 to 5.25V
/LA
(Vee = 5V ± 10%, TA = O·C to 70·C)*
TIMING REQUIREMENTS
Parameter
Min.
Symbol
TClCl
ClK Cycle Period
TClCH
TCHCl
TSVCH
TCHSV
ClK low Time
ClK High Time'
Status Active Setup Time
Status Inactive Hold Time
50
30
35
10
TSHCl
TClSH
Status Inactive Setup Time
Status Active Hold Time
35
10
100
Max.
Unit
Test Conditions
ns
ns
ns
ns
ns
ns
ns
• Note: For Extended Temperature EXPRESS the Preliminary Values are TClCl= 125; TClCH =50; TCHCl=30;
TCVNX=50; TCllH, TClMCH=25; TSVlH, TSVMCH=25.·
.
3-583
AFN-01504C
8288
A.C. CHARACT.ERISTICS (Continued)
TIMING RESPONSES
-'
Parameter
Control Active Delay ,
Min.
TCVNX
Control Inactive Delay
10
TCLLH,
TCLMCH
Symbol
Max.
Unit
45
45
ns
ALE MCE,Active Delay (from CLK)
20
ns
TSVLH,
TSVMCH
ALE MCE Active Delay (from
Status)
20
ns
TCHLL
ALE Inactive Delay
4
15
ns
TCLML
Command Active Delay
10
35
ns
lORd
TCLMH
Command Inactlve'Delay
10
35
ns
MWTC
TCHDTL
Direction Control Active Delay
50
ns,
IOWC
IOL = 32 rnA
IOH = -5mA
CL = 300pF
TCVNV
5
Teat CondHlona
ns
.MRDC
TCHDTH
Direction Control Inactive Delay
30
ns
INTA
TAELCH
Command Enable Time
40
ns
AMWC
40
ns
~
200
ns
ns
~ho,
ns
ns
From 0.8V to 2.0V
ns
From 2.0V to 0.8V
TAEHCZ
Command Disable Time
TAELCV
Enable Delay Time
TAEVNV
TCEVNV
AENto DEN
CEN to DEN, PDEN
TCELRH
TOLOH
CEN to Command
Output, Rise Time
TOHOL
OutPut, Fall Time
115
ns
20
25
' TCLML
20
12
'I
IOL = 16 rnA
IOH = -1 rnA
CL=80pF
A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUTIOUTPUT
A C TESTING'INPUTS ARE DRIVEN AT 2,4V FOR A LOGIC "I" AND 0 45Y
FOR A LOGIC "0" THE CLOCK IS DRIVEN AT 4 3V AND 02SV TIMING
MEASUREMENTS ARE MADE AT 1 5V FOR BOTH A LOGIC "I" AND "0,"
~N~1~~SE AND FALL TIMES ARE S±2 NS. MEASURED BETWEEN OBV
TEST LOAD CIRCUITS-3-STATE COMMAND OUTPUT TEST LOAD
1.SV
oo'~'~
r~PF
3-STATE TO HIGH
15V
J
33Q
OUT~
I
2.14V
-~."
300PF
3-STATE TO LOW
300PF
228V
1,,42
OUT~
r~PF
r
COMMAND OUTPUT
TEST LOAD
CONTAOL OUTPUT
TEST LOAD
~FN-OI504C
inter
8288
WAVEFPRMS
STATE
_--T4~
CLK
_--T,
n
/
-TCLCL
r-..
-
i-
TCHSV1,0
/
\
TSVCH
3'>
n
-
- 13-
T,
Io--TCLCH-V""""\
~
LF-
~
-
TCHCl.-
ADDRESSIDATA
r
ADDR
M
TCLLH_
SO'itA
IaeQ
CD
i..-TCHLL
'
,
-
r-TCLMH
\
V,
~
-
/
-
-TClMl
I--TCLML
V
\
r\
-
/
-TCVNV
\
I
I
~
/
I--
TCVNX-
V
\
I
I
/
i-
TCVNV-
V
DEN (WRITEI
\
J
!\
-
I--TCVNX
:;
\
POEN (WRITEI
1\
-------
TCHDTH-
DT/R (READI
(INTAI
3-? VL<;
10 ~.,
TSVLH
Ir
ALE
'---
J /
WRITE
DAlA VAliD
VALID
V""\
-I-ig,;; TSHCl
~~
~
1\
T4-
0-
J
.1:='
[J
-
-I 1
V
TCHDTL
MeE
IiI- 11°
TCLMCH-
-+j
TCHOTH-
LTsvMeT
~
I-(
TCVNX
NOTEI<
1 ADQRESSIDATA BUS IS SHdwN ONLY FOR REFERENce PURPOSES
2 LEADING EDGE OF ALE AND MCE IS DETERMINED BY THE FALLING EDGE OF eLK
3 AU. TIMING MEASU~MENTS ARE MADE AT 1 5V UNLESS SPECIFIED OTHE~lse
~
STATUS GOING ACTIVE. WHICHEVER OCCURS LAST
AFN-01504C
inter
8288
WAVEFORMS (Continued)
DEN, PDEN QUALIFICATION TIMING
\V
CEN
Jr\
\11
II\.
I---rAEV~
~-
DEN
\
\11
Ir\
II\.
!+----rCEVNV_
,
\1{
jl\.
ADDRESS ENABLE (AEN) TIMING (3·STATE ENABLE/DISABLE)
VOH
CO~':::~~-------------'I
CEN--------------,=-::;:-~I
NOTE: CEN must be I,!w or valid prior to T2 to prevent the command from being generated.
3-586
AFN.()l504C
inter
8289/8289·1
BUS ARBITER
• Provides Multl·Master System Bus
Protocol
• Four Operating Modes.for Flexible
System Configuration·
• Synchronizes IAPX 86, 88 Processors
with Multl·Master Bus
'
• Compatible with Intel Bus Standard
.10MHz Version, 8289-1, Fully Compatible
with 10MHz iAPX 86 or 8MHz iAPX 186
Based Systems
• Provides System Bus Arbitration for
8089 lOP in Remote Mode
~ULTIBUSTM
,
• Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range
• Provides Simple Interface with 8288
Bus Controller
The Intel 8289 Bus Arbiter is a 20-pin, 5-volt-only bipolar component for use with medium to large iAPX 86, 88 multimaster/multiprocessing systems. The 8289 provides system bus arbitration for systems with multiple bus masters, such as
an 8086 CPU with 8089 lOP in its REMOTE mode, while providing bipolar buffering and drive capability.
8088/8088/8089 {
STATUS
PROCESSOR
. CONTROL
BCLK
INIT
BREO
12
I
1
BPRN
BPRO
Ii
Iii
1
MULTlBUSTM
COMMAND
SIGNALS
BUSY
CBRO
LOCK
eLK
CiIllLCK
REsa
ANYROST
.
loa
AEN
L~=~~=~~~~~~ SYSBliiHi
} SYSTEM
SIGNALS
+5V
,
Figure 1. Block Diagram
VCC
GND
VCC
REsa
iCLR
MULTIBUS
INTERFACE
jji/if
CONTROU
STRAPPING
OPTIONS
• SYSB/IInB } SYSTEM
J:EN
SIGNALS
GND
Figure 2. Pin Diagram
Figure 3. Functional Pinout
3-587
8289/8289-1
.(
Table .1. Pin Description
Symbol
Power: +5V supply ±10%.
GND
Ground.
I
Status Input Pins: The status input pins
from an 8086, 8088 or 8089 processor. The
8289 decodes these pins to initiate'bus request and surrender actions. (See Table 2.)
ClK
I
Clock: From the 8284 clock chip and
serves to establish when buS arbiter actions are initiated.
lOCK
I
Lock: A processor generated signal which
when activated (low) prevents the arbiter
from sUrrendering the multi-master system
bus to any other bus artiter, regardless of
its priority.
CRalCK
I
Common Request Lock: An active low
signal which, prevents the' arbiter from surrendering the multi-master system bus to
any other bu~ter requesting the bus
through the CBRa input pin.
RESB
I
Resident Bus: A strapping option to configure the arbiter to operate in systems having both a multi-master system bus and a
Resident Bus. Strapped high, the multimaster system bus is requested or s~
dered as a function of the SYSB/RESB
input· pin. Strapped low, the SYSB/RE;SB
input is ignored.
ANYRaST
I
Any Request: A strapping option Which
permits the multi-master system bus to be
surrendered to a lower priority arbiter as if
it were an arbiter of higher priority (i.e.,
when a lower priority arbiter requests the
use of the multi-master system bus, the bus
is surrendered as soon as it is possible).
When ANYRaST is strapped low, the bus is
surrendered according to Ta~f ANYRaST is strapped high and CBRa is activated, the bus ispurrendered at~d of
the present bus cycle. Strapping CBRa low
and ANYRaST high forces the 8289 arbiter
to surrender the multi-master system bus
after each transfer cycle. Note that when
surrender occurs BREQ is driven false
(high).
lOB
I
TYpe
Name and Function
AEN
0
Address Enable: The output of the 8289
Arbiter to the proces~or's address latches,
to the 82M Bus Controller and 8284A
Clock Generator. AEN serves to instrucfthe
Bus Controller and address latches when
to tri-state their output drivers.
SYSB/
RESB
I
System Bus/Resident Bus: An input
sign,al when the arbiter is configured in the
S.R. Mode (RESB is strapped high) which
determines when· the multi-master system
bus is requested and multi-masier system
bus surrendering is permitted. The signal
is intended to originate from a form of
address-mapping circuitry, as a decoder or
PROM attached to. the resident address
bus. Signal transitions and glitches are
permitted on this pin from <1>1 ofT4 to 1 of
T2 of the processor cycle. During the
period from tofT2 to 1 ofT4,onlyclean
transitionslare permitted on this pin (no
glitches). If a glitch occurs, the arbiter may
capture or miss it, and the· mUlti-master
system bus may be requested or surrendered, depending upon the state of the
glitch. The arbiter requests the multimaster system bus il'\ the S.A. Mode when
the state olthe SYSB~ pin is high and
permits the bus to be surrendered when.
this pin is low.
CBRa
I/O
Common Bus Request: An input signal
which instructs the arbiter if there are any
'other arbiters of lower priority requesting
the use of the multi-master system bus.
,
SO,SI,$2
\
Symbol
Name and Function
TYpe
Vcc
The CBRa pins (open-collector output) of
all the 8289 Bus Arbiters which surrender
to the multi-master system bus upon request are connected together.
The Bus Arbiter running the current transfer cycle will not itself pull the CBRa line
low. Any other arbiter connected to the
CBRa line can request the mUlti-master
system bus. The arbiter presently running
the current transfer cycle drops its BREa
signal and surrenders the bus whenever
the proper surrender conditions exist.
StrappIng CBRa low and ANYRaST high
allows the multi-master system bus to be
surrendered aft~r each transfer cycle. See
the pin definition of ANYRaST.
10 Bus: Pi strapping option which configures the 8289 Arbiter to operate In systems having both an .10, Bus (Peripheral
Bus) and a multi-master system bus. The
arbiter requests and surrenders the use of
the multi-master system bus as a function
of the status line, 82. The multi-master system bus is permitted. to be slll'rendered
w,hile the processor is performing 10 commands and is requested whenever the processor performs a memory command.
Interrupt cycles are assumed as· coming
from the peripheral bus and are treated as
an 10 command.
INIT
3-588
I
Initlall~e: An active low mUlti-master system bus input signal used to reset all the
bus arbiters on the multi-master system
bus. After initialization, no arbiters have
the use of the multi-master system bus.
AFN-00839D
inter
8289/8289-1
Table 1. Pin Descriptions (Continued)
Symbol
1P
Name and Funcllon
BClK
I
Bu. Clock: The multi-master system bus
clock to which all multl-master system bus
interface signals are synchronized.
BREQ
0
Bua Requeat: An active low output signal
In the parallel Priority Resolving Scheme
Which the arbiter activatas to requast the
use of the multi-master system bus.
BPRN
I
Symbol
Bu. Priority In: The active low signal returned to the arbiter to Instruct itthat it may
acquire the multi-master system bus on the
next falling edge of BelK. BPRN indicatas
to the arbiter that It is the highest priority
requesting arbiter presently on the, bus.
The loss of BPRN instructs the arbiter that
it has lost priority to a higher priority
arbiter.
'FUNCTIONAL DESCRIPTION
The 8289 Bus Arbiter operates in conjunction with the
8288 Bus Controller to interface iAPX 86, 88 processors to
a mlliti-master system bus (both the iAPX 86 and iAPX 88
are configured in their max mode). The processor is unaware of the arbiter's existence and issues commands as
though it has exclusive use of the system bus. If the processor does not have the use of the multi-master system
bus, the arbiter prevents the Bus Controller (8288), the
data transceivers and the address latches from accessing
the system bus (e.g. all bus driver outPllts are forced into
the high impedance state). Since the command sequence
was not issued by the 8288, the system bus will appear as
"Not Ready" and the processor will enter wait states. The
processor will remain in Wait until the Bus Arbiter acquires the use of the mUlti-master system bus whereupon
the arbiter will allow the bus controller, the data transceivers, and the address latches to access the system. Typi'cally, once the command has been issued and a data
transfer has take~ place, a transfer acknowledge' (XACK)
is returned to the processor to indicate" READY" from the
accessed slave device. The processor then completes its
transfer cycle. Thus the arbiter serves to multiplex a processor (or bus master) onto a multi-master system bus and
avoid contention problems between bus masters.
1P
Name and FunClion
BPRO
0
BUll Priority Out: An active low output
signal used in the serial priority resolving
scheme where BPRO Is dalsy-chalned to
BPRN of the next lower priority arbiter.
BUSY
I/O
BU8Y: An active low open collector
mUlti-master system bus interface signal
used to Instruct all the arbiters on the bus
when the mUlti-master system bus is available. When the mUlti-master system bus Is
available the highest requesting arbiter
(dete!!!!!!!!,d by BPRN) seizes the bus and
pulls BUSY low to keep other arbiters off of
the bus. When the arbiter is done with the
bus, it releases the BUS'YSignal, permitting
it to go high and thereby allowing another
arbiter to acquire the multi-master system
bus.
the HALT State. The arbiter will not voluntarily surrender
the system bus and has 10 be forced off by another
master's bus request, the HALT State being the only exception. Adpltional strapping options permit other
modes of operation wherein the mUlti-master system
bus is surrendered or requested under different sets of
conditions.
Arbitration Between Bus Masters
In general, higher priority masters'obtaln the bus when a
lower priority master completes its present transfer
cycle. Lower priority bus masters obtain the blls when a
higher priority master is not accessing the system bus.
A strapping option (ANYRaST) is provided to allow the
arbiter to surrender the bus to a lower prlortw master as
though It were a master of higher priority. If there are no
'other bus masters requesting the bus, the arbiter maintains the bus so. long as its processor has not entered
3-589
Priority Resolving Techniques
Since there can be many bus masters on a multi-master
system bus, some means of resolving priority between
bus masters simultaneously requesting the bus must be
provided. The 8289 Bus Arbiter provides several resolving techniques. All the techniques are based on a priority concept that at a given time one bus master will have
priority above all the rest. There are provisions for using
parallel priority resolving techniques, serial priority
resolving techniques, and rotating. priority techniques.
PARALLEL PRIORITY RESOLVING
The parallel priority resolving technique uses a separate
bus request line (EmEt\') for each arbiter on the multimaster system bus, see Figure 4. Each BREa line enters
Into a priority encoder which generates the binary address of the highest priority BREa line which is active.
The binary address is decoded by a decoder to select
the corresponding Ei'i5Riii (Bus Priority In) line to be
returned to the highest priority requesting arbiter. The
arbiter receiving priority (EiPRN true) then allows its
associated bus master onto the mUlti-master system
bus \l.s soon as it becomes available (i.e., the bus is no
longer busy). When one bus arbiter gaiQS priority oller
another arbiter it cannot immediately seize the bus, it
must ~alt unti' the present.bus transaction is complete.
AFN-00839D
inter
8289/8289'·1
Upon completing its transaction the present bus occupant recognizes that it no longer has priority and surrenders the bus by releasing BUSY. BUSY is an active
low "OR" tied signal line which goes to every bus arbiter
on.the system bus.When BDSY goesinactive{high), the
arbiter whlph presently has bus priority (EiPFiN true) then
seizes the bus and pulls BUSY low to keep other arbiters
off of the bus. See waveform timing diagram, Figure 5.
Note that all'multl-master system bus transactions are
synchronized to the bus clock (BClK). This allows the
parallel priority resolving circuitry or any other priority
resolving scheme employed to settle.
74148
74138
PRIORITY
ENCOOER
DECODER
HOB
Figure 4. Parallel Priority Resolving Technique
CD
®
HIGHER PRIORITY BUS ARBITER REQUESTS THE MUL TI·MASTER SYSTEM BUS.
ATTAINS PRIORITY'
_
.
@
@)
HIGHER PRIORITY BUS ARBITER THEN ACQUIRES THE BUS AND PULLS BUSY DOWN.
LOWER PRIORITY BUS ARBITER RELEASES BUSY.
Figure 5. Higher Priority Arbiter obtaining the Bus from a Lower Priority Arbiter
3-590
AFN·00839D
, intJ
.8289/8289-1
SERIAL PRIORITY RESOLVING
The serial priority resolving technique eliminates the
need for the priority encoder-decoder arrangement by
daisy-chaining the bus arblteFs together, connecting the
higher priority bus arbiter's Ei'i5RO (Bus Priority Out) output to the BPRN of the next lower priority. See Figure 6.
caRa:
8289 MODES OF OPERATION
There are two types of processors in the iAPX 86 family. An
Input/Output processor (the 8089 lOP) and the iAPX 86/1 0,
88/10 CPUs. Consequently, there are lwo basic operating
modes in the 8289 bus arbiter. One, the lOB (I/O Peripheral
Bus) mode, permits the processor access to both an I/O
Peripheral Bus and a multi-master system bus. The second, the RESB (ReSident Bus mode), permits the processor to communicate over both a Resident Bus and a
multi-master system bus. An I/O Peripheral Bus is a bus
where all devices on that bus, including memory, are
treated as I/O devices and are addressed by I/O commands. All memory commands are directed to another
bus, the multi-master system bus. A Resident Bus can
issue both memory and I/O commands, but it is a distinct
and separate bus from the multi-master system bus. The
distinction is that the Resident Bus has only one master,
providing full availability and being dedicated to that one
master.
.
: BUSY
THE NUMBER OF ARBITERS THAT MAY BE DAISY CHAINED TOGETHER IN THE
SERIAL PRIORITY RESOLVING SCHEME IS A FUNCTION OF BCLK AND THE PROPA
GATION DELAY FROM ARBITER TO ARBITER NORMALLY, AT 10 MHz ONLY ,ARBI·
TER MAY BE DAISY·CHAINED
Figure 6. Serial Priority Resolving
ROTATING PRIORITY RESOLVING
The rotating priority resolving technique Is similar to
that of the parallel priority resolving technique except
that priority is dynamically re-asslgned. The priority encoder Is replaced by a more complex circuit which rotates priority between requesting arbiters thus allowing
each arbiter an equal chance to use the multi-master
system bus, over time.
Which Priority Resolving Technique To
Use
There are advantages and disadvantages for each of the
techniques described above. The rotating priority
resolving technique requires substantial external logic
to Implement while the serial techniql!e uses no external logic but can accommodate only a limited number of
bus arbiters before the daisy-chain propagation delay
exceeds the multl-master's system bus clock (BCLK).
The parallel priority resolving technique is in general a
good compromise between the other two techniques. It
allows for many arbiters to be present on the bus while
not requiring too mUCl:h logic to Implement.
The lOB strapping option configures the 8289 Bus Arbiter into the lOB mode and the strapping option RESB
configures it into the RESB mode. It might be noted at
this point that if both strapping options are strapped
false, the arbiter interfaces the processor to a multimaster system bus only (see Figure 7). With both options strapped true, the arbiter interfaces the processor
to a multi-master system bus, a Resident Bus, and an 1/0
Bus.
In the lOB mode, the processor communicates and controls a host of peripherals over the Peripheral Bus. When
the 110 Processor needs to communicate with ·system
memory, it does so over the system memory bus. Figure
8 shows a possible 110 Processor system configuration.
The iAPX 86 and iAPX 88 processors can communicate
with a Resident Bus and a multi-master system bus. Two
bus controllers and only one Bus Arbiter would be needl'ld
in such a configuration as shown in Figure 9. In such a
system configuration the processor would have ~ccess to
memory and· peripherals of both busses. Memory mapping techniques are applied to select which bus is to be
accessed. The SYSB/RESB input on the arbiter serves to
instruct the arbiter as to whether or not the system bus is
to be accessed. The signal connected to SYSB/RESB also
enables or disables commands from one of the bus
controllers.
A summary of the modes that the 8289 has, along with
its response to Its status lines inputs, is summarized in
Table 2.
*In some system configurations it is possible for a non-I/O Processor to
have
access~to
more than one Multi·Master System Bus, see 8289
Application Note.
3-591
AFN'()0839D
inter
8289/8289-1
Table 2. Summary of 8289 Modes, Requesting and Relinquishing the Multl·Master System Bus
Single
~
Stalus Lines From
8086 or 8088 or 8089
~
Only
S2
iii
Sci
1/0
COMMANDS
0
0
0
0
0
0
1
0
x
x
x
HALT
0
1
1
X
MEM
COMMANDS
1
1
1
0
0
0
1
,0
IDLE
1
1
1
RESB (Mode) Only
lOB = High RESB - High
lOB;' Low SYSB/RESB = High SYSB/RESB = Low
1
x
1
SYSB/RESB = High SYSB/RESB = Low
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
lOB = High
RESB = Low
lOB Mode RESB Mode
lOB - Low RESB - High
x
x
NOTES:
1, X = Multi·Master System Bus is allowed to be Surrendered.
2.
~
= Multl·Master System Bus is Requested.
Multi·Master System Bus
--
Pin
Strapping
Requested"
Single Bus
Multi·Master Mode
10B= Hig.h
RESB= Low
Whenever the processor's
status lines go active
HLT + TI' CBRO+ HPBROt
RESB Mode Only
10B= High
RESB=High
SYSB/FfESIi = High'
ACTIVE STATUS
(SYSB/FfESIi = Low + TI) •
CBRO+ HLT + HPBRO
lOB Mode Only
10B=low
RESB=Low
Memory Commands
(110 Status + TI) • CBRO +
HLT+HPBRO
lOB Mode·RESB Mode
10B=Low
RESB= High
(Memory Command) •
(SYSB/RESB= High)
«110 Status Commands) +
SYSB/FfESB = LOW» • CBRO
+ HPBROt + HLT
Mode
Surrendered'
NOTES:
• LOCK prevents surrender of Bus to any other arbiter, CRQlCK prevents surrender of Bu,s to any lower priority arbiter.
"Except for HALT and Passive or IDLE Status.
t HPBRQ, Higher priority Bus request or iiPRN = 1.
1. lOB Active low.
2. RESB Active High.
3. + is read as "OR" and. as "AND."
4. TI = Processor Idle Status 52, 61.]0 = 111
5. HLT= Processor Halt Status 52,51, m1=OII
3-592
AFN·00839D
inter
8289/8289-1
rD~
.....
RDy'bJ
CLOCk
AEN2
JREADY
ClK
":'
ROY1
< XACK MULTI MASTER SYSTEM 8US
AEN1
8289
.us
MULTI MASTER
CONTROL BUS
ARBITER
~~-I31"
READY
ClK
....
CPU
J~~
A::~~: ~
AEN
8288
BUS
STATUS 150,81,&2)
I
.--
CS
STB
ALE
DEN
I
~
(2
OR 3) I
C3
COMMAND
BUS
ClK
ADDRESS
LATCH
LOCA I, BUS
MULTI MASTER
SYSTEM
CONTROLLER
!
PRoeESSOR
Vce
11ii·Sl!AEN,RES'~
"
I 11-
108
DTIA
I
I
MULTI·MASTER
SYSTEM BUS
_
MUL Tt·MASTER
SYSTEM
ADDRESS
'US
XCVR
DiIABLE
DflR
MULTI-MASTER
SYSTEM
DATA
TRANSCEIVER
828618287
.us
I~
Figure 7. Typical Medium Complexity CPU System
XACK (liD
BUS~
>-
.....
CLOCK
-----RDY1
1 - - - - - -_ _ _ _ _ _'--_ _ _-( XACK MULTI MASTER SYSTEM BUS
6289
'us
READY
eLK
READY CLK
ARBITER
MULTIMASTER
~ CONTROL
BUS
--
''''
808!!
'0'
'0
COMMAND
BUS
~
".
'0
ADDRESS
'us
________==;>
'0
DATA
'us
____________
MULTI MASTER
SYSTEM
DATA
'us
Figure 8. Typical Medium Complexity JOB System
3-593
AFN·QQ839D
inter
8289/8280.1
o
.....
M"'I>--------,
.=
~~ENTIUS--------IRDY2
R D Y 1 i - - - - - - - t - - - - - - - - XACK MPf,.'t-MASTERSYSTEM IUS
MULTI MAS115R svmM
IUSCONTRCH.
RIII--+--ycc
RESIDENT COMMAND "::===:;::===l
BUS
Mum MAlTER SYSTEM
COMMAND IUS
\
MULTi MASTER
RESIDENT BUS
SYSTEM IUS
RESIDENT ADDRESS 1 ' - - - - '
, BUS
MULTI MASTEa smlM
\--------i
ADDRES8IUS
RESIDENT DATA"::====:::::=~
IUS
MULTI·MASTIR 8Y~
DAT.aus
'\
ACe_
·IY ADDHfQ ANOTtlER 1211 ARMER AND CONNlcnNCI ITS AlN TO THI till
WHOIlAR 18 PAEII!NTU GROUNDm, THI! PROCE8IOR COULD HAve:
TO TWO MULTI-MASTER lUBES.
Figure 9. 8289 Bus Arbiter Shown In System-Resident Bus Configuration
3-594
AFN·00839D'
intJ
8289/8289-1
'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional ciperation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ....... '" .. , ... O·C to 70·C
Storage Temperature .............. - 65·C to + 150·C
All Output and Supply Voltages ........ - 0.5V to + 7V
All Input Voltages .................. - 1.0V to + '5.5V
Power Dissipation ......................... 1.5 Watt
D.C. CHARACTERISTICS
(TA =
o·c to 70·C, Vee =
Parameter
Symbol
+5V ±10%)
Min.
Test Condition
Units
Max.
Vc
Input Clamp Voltage
-1.0
V
IF
Input Forward Current
-0.5
mA
Vee = 5.50V, VF = 0.45V
IR
Reverse Input Leakage Current
60
".A
Vee = 5.50, VR = 5.50
VOL
Output Low Voltage
BUSY, CBRO
AEN
BPRO,BREO
0.45
0.45
0.45
V
V
V
IOL= 20 mA
IOL= 16 mA
IOL= 10 mA
V
IOH=400 ".A
Output High Voltage
BUSY,CBRO
VOH
Open Collector
All Other Outputs
2.4
165
mA
.8
V
Input Capacitance
25
pF
Input Capacitance
12
pF
Icc
Power Supply Current
V1L
Input Low Voltage
V1H
Input High Voltage
Cln Status
Cln (Others)
A.C. CHARACTERISTICS
Vcc=4.50V, Ic= -5 mA
V
2.0
(Vee = +5V ±10%, TA = O·Cto 70·C)
TIMING REQUIREMENTS
Symbol
.
Parameter
8289 Min.
8289·1 Min.
125
100
ns
CLKLowTime
65
53
ns
CLK High Time
35
26
TSVCH
Status Active Setup
65
55
TCLCL-10
ns
TSHCL
Status Inactive Setup
50
45
TCLCL-10
ns
THVCH
Status Active Hold
10
10
ns
THVCL
Status Inactive Hold
10
10
ns
TSYSBL
BUSyt,tSetup to BCLK,t
20
20
ns
TCBSBL
CBROt ,tSetup to BCLK,t
20
20
ns
TBLBL
BCLK Cycle Time
100
100
TBHCL
BLCK High Time
30
30
TCLLL1
LOCK Inactive Hold
10
10
ns
TCLLL2
LOCK Active Setup
40
40
ns
TPNBL
BPANt,t to BCLK Setup Time
15
15
ns
TCLSR1
SYSB/RESB Setup
0
0
ns
TCLSR2
SYSB/RESB Hold
20
20
ns
TIVIH
Initialization Pulse Width
3TBLBL+
3 TCLCL'
3TBLBL+
3 TCLCL
ns
TCLCL
CLK Cycle Period
TCLCH
TCHCL
3-595
Max.
Unit
Test Condition
ns
ns
.65[TBLBL]
ns
AFN-00839D
8289/8289-1
A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES
Min.
Max.
Unit
35
ns
BCLK to BPROH (See Note 1)
40
ns
BPRN~ tto BPRO~ tDelay
25
ns
Symbol
Parameter
TBLBRL
BCLK to BREq D~lay~ t
T8LPOH
TPNPO
Test Condition
(See Note 1)
TBLBYL
BCLK to BUSY Low
60
ns
TBLBYH
BCLK to BUSY Float (See Note 2)
35
ns
TCLAEH
CLK to AEN High
65
ns
TBLAEL
BCLK to AEN Low
40
ns
TBLCBL
BCLK to CBRO Low
60
ns
TRLCRH
BCLK to CBRO Float (See Note 2)
35
ns
TOLOH
Output Rise Time
20
ns
From O.BV to 2.0V
TOHOL
Output Fall Time
12
ns
From 2.0V to O.BV
t
~ Denotes that spec applies to both transitions of the signal.
NOTES:
1. BCLK generates the first BPRO wherein subsequent BPRO changes lower in the chain are generated through BPRON.
2. Measured at .5V above GND.
.
A.C. TESTING INPUT, OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
INPUT/OUTPUT
2.4 J S _ T E S T
0.45
POINTS~'X=
OEVICE
UNDER
TEST
,
A,C. TESTING INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC "1" AND 045V
FOR A LOGIC "0" THE CLOCK IS DRIVEN AT 4 3V and 025V TIMING
MEASUREMENTS ARE MADE AT , 5V FOR BOTH A LOGIC "'" AND "0"
INPUT RISE ANtlFALL TIMES (MEASURED BE1WEEN 0 8V AND 2 OV) ARE
DRIVEN AT 5 ± 2 NS
~CL~'OOPF
CL ", 100pF
CL INCLUDES JIG CAPACITANCE
3.596
AFN-00839D
8289/8289-1
WAVEFORMS
eLK
~
(lEE NOTE t)
SYSllJi!IIii
.iEN
(SEE NOn: 3)
PROCESSOR eLK RELATED
IUS eLK RELATED
.......
(IISIm'1)
1IP1I1l
#2
(1PlIR #3)
NOTES:
1
LOCK
ACTIVE CAN OCCUR DURING ANY STATE. AS LONG AS THE
RELATIONSHIPS SHOWN ABOVE WITH RESPECT TO THE ClK ARE MAINTAINED
lOCK INACTIVE HAS NO CRITICAL TIME AND CAN BE ASYNCHRONOUS
:cFiQCCK HAS NO CRITICAL TIMING AND IS CONSIDERED AN ASYNCHRONOUS
~~~~G~
SYSB/RESB PIN IS PERMITTED DURING THIS TIME AFTER 2 OF
T1, AND BEFORE 1 OF T4, SYSBIReSBSHOUlD BE STABLE.
3 AEN lEADING eDGE IS RELATED TO BClK, TRAILING EDGE TO CLK THE
TRAILING EDGE OF AEN OCCURS AFTER BUS PRIORITY IS LOST
ADDITIONAL NOTES:
The signals related to ClK are typical processor signals, and do not relate to the depicted sequence of events of the
signals referenced to BClK. The signals shown related to the BClK represent a hypothetical sequence of events for
illustration. Assume 3 bus arbiters of priorities 1, 2 and 3 configured m serial priority resolving scheme as shown m
Figure 6. Assume arbiter 1 has the bus and is holding busy low. Arbiter #2 detect~rocessor wants the bus and
pulls· low BREQ#2. If BPRN#2 is high (as shown), arbiter #2 will pull low CBRQ Ime. CBRQ signals to the higher priority
arbiter #1 that a lower priority arbiter wants the bus. [A higher priority arbiter would be granted BPRN when It makes
the bus request rather than having to wait for another arbiter to release the bus through CIm'O]." Arbiter #1 will relinquish the multi-master system bus when it enters a state not requiring it (see Table 1), by lowering its iiPROO (tied to
~ and releasing BUSY. Arbiter #2 now sees that it has Priority from BPAiiili2 being low and releases CBRQ' As
soon as BUSY signifies the bus is available (high), arbiter #2 pulls BUSY low on next falling edge of BClK. Note that if
arbiter #2 didn't want the bus at the time it received priority, it would pass priority to the next lower priority arbiter by
lowering its BPRO #2 [TPNPOj .
• *Note that even a higher pnorlty arbiter which IS acqumng the bus through
3-597
SPAN Will
momentarily dtop
CEiRQ until It has acqUired the bus
AFN·00839D
iAPX286
'Microprocessors
Microprocessors
Section
4
"nt_II!>
I•• ~
iAPX 286/1 0
~[Q)W~OO©~ DOO~@OOIiYil~'iJD@OO
HIGH PERFORMANCE MICROPROCESSOR
WITH MEMORY MANAGEMENT AND PROTECTION
(80286,80286-6,80286-4)
• High Performance
Processor (Up to six times iAPX 86)
• Large Address Space:
-16-Megabytes Physical
-1 Gigabyte Virtual per Task
• Integrated Memory Management, FourLevel Memory Protection and Support
for Virtual Memory and Operating
Systems
• Two iAPX 86 Upward Compatible
Operating Modes:
-iAPX 86 Real Address Mode
-Protected Virtual Address Mode
• Range of clock rates
-8 MHz for 80286
-6 MHz for 80286-6
-4 MHz for 80286-4
• Optional ProCessor Extension:
-iAPX 286/20 High Performance 8O-blt
Numeric Data Processor
• Complete System Development
Support:
-Development Software: Assembler,
PLlM, p",scal, FORTRAN, and System
Utilities
-In-Circuit-Emulator (ICE T. -286)
• High Bandwidth Bus Interface
(8 Megabyte/Sec)
• Available In EXPRESS:
-Standard Temperature Range
The iAPX 286/10 (80286 part number) is an advanced, high-performance microprocessor with specially optimized
capabilities for multiple user and multi-tasking systems. The 80286 has built-in memory protection that supports
operating system and task isolation as well as program and data privacy within tasks. An 8 MHz iAPX 286/ 10 provides
up to six times greater throughout than the standard 5 MHz iAPX 86/10. The 80286 includes memory management
capabilities that map up to 230 (one gigabyte) of virtual address space per task into 224 bytes (16 megabytes)
of physical memory.
The iAPX 286 is upward compatible with iAPX 86 and 88 software. Using iAPX 86 real address mode, the 80286 is
object code compatible with existing iAPX 86, 88 software. In protected virtual address mode, the 80286 is source
code compatible with iAPX 86, 88 software and may require upgrading to use virtual addresses supported by the
80286's integrated memory management and protection mechanism. Both modes operate at full 80286 performance
and execute a superset of the iAPX 86 and 88's instructions.
The 80286 provides special operations to support ihe efficient implementation and execution of operating systems.
For example, one instruction can end execution of one task, save its state, switch to a new task, load its state, and
stflrt execution of the new task. The 80286 also supports virtual memory systems by providing a segment-not-present
exception and restartable instructions.
; ADDRESSUNrr(AU) - - - - - - - - - - - - - - - - - - -,
A23 - Ao,
I
I
I
I
SHE, MilO
I
PEACt\.
PEREa
SEGMENT
BASES
I
READY, HOLD
S1, so, CODJINTA
LOCK, HLDA
I
I
SEGMENT
I
I
SIZES
I
I
I
I
IL __
I
I
I
RESET
I
, elK
_
I EXECUTION UNIT (EU)
,
__
__-_-__-_-_-__· __
~_._~_=_--_-_-_-~-_-_- -_-_-_-_-_-~-~-~-~-~-~-_-
~~~~
____
vee
~~~~~~~~r_-CAP
Figure 1. 80286 Internal Block Diagram
ThefollowlngaretrademarkSof Intel Corporation and Its affiliates and may be used only to Identify Intel products exp, CREDIT, I, ICE. leS, 1m, InSlte, Intel, INTEL, Intelevlslon, Intelhnk,
~~~~~~'~~~.' ~~~~:~~~~~P~.' ~~~~h~SC~~~:~~~;Jn~~~~~~lrR~;~;~~~~~~~,~~i~2i6e~~~~~~~u~;C:~:;:~~;:::;~::~u~~:~Y~~~~~:~~~;;':~' =~~~~~~~~b~~:;~~:'~t~~~~t::~~e
of Any Circuitry Other Than Circuitry Embodied
In
an Intel Product No Other Patent LlcenSf:lS are Implied @INTEL CORPORATION,
4-1
1983
NOVEMBER 1983
ORDER NUMBER: 210253·006
IAPX286/10
Component Pad View-As viewed from
underside of component when mounted on
the board.
P.C. Board View-As viewed from the
component side of the P.C. board.
:&I~g5Id:Bg&&&4&'
L.JLjLJL.JLJUlJLJLJLJLJL.JU L.,J L..JLJ L:
A,
CAP
A,
A,
mIl5iI
ClK
N.C.
Vee
RESET
NC.
,INTR
NMI
0
Vss
PEREQ
[
Vee
II!A5'I
HOLD
L
"
"
L
J
r
r
"
"
"
"
"
"
A,
ClK
Vee
RESET
A3
r
J
[
r
J
L
J
L
r
"
~""""'nr"n'nr'nr'...,
A,
"r
"
"
J
18
..
r
J
"
"
Au
r
r
L
r
r
Irn§V
N.C
A3
5~
,r lr1r1f lr lrlr lr1rlr lr lrlr, rlr, r
9,
An
f1
.•
PIN NO 1 MARK\
IiUUJ!;/a1~99~
tD Z Z
>
~
..
I
liO
I
1
NOTE: N.C. pads must not be connected.
Figure 2. 80286 Pin Configuration
Table 1. Pin Description
The following pin function descriptions are for the 80286 microprocessor:
Symbol
elK
Type
I
Name and Function
System Clock provides the fundamental timing for iAPX 286 systems. It is divided by two Inside
the. 80286 to generate the processor clock. The internal divide-by-two circuitry can
be synchronized to an external clock .generator by a lOW to HIGH transition on the RESET
Input.
.
015-0 0
I/O
Data Bus inputs data during memory, 1/0, and interrupt acknowledge read cycles; outputs data
during memory and 110 write cycles. The data bus is active HIGH and floats to '3ostate OFF during
bus hold acknowledge.
A23-Ao
0
Address Bus outputs physical memory and 1/0 port addresses. AO is lOW when data is to be
transferred on pins 07-0' A23-A16 are lOW during 1/0 transfers. The ac;ldress bus is active HIGH
and floats to 3-state OFF during bus hold acknowledge.
SHE
0
Bus High Enable indicates transfer of data on the upper byte of the data bus, D15d1.:...Eight-bit
oriented devices assignec!..!Q..the upper byte of the data bus would normally use SHE to condition chip select functions. SHE is active lOW and floats to 3-state OFF during bus hold acknowledge.
BHE and AO Encodlngs
BHEValue
AD Value
0
0
1
0
1
1
0
1
Function
Word transfer
Byte transfer on upper half of data bus (015-8)
Byte 1ransfer on lower half of data bus (07-0)
Reserved
I
4-2
.
AFN-020600
IAPX 286/10
Symbol
81.S0
Table 1 Pin Description (Cont )
Name and Function
'TYPe
0
Bus Cycle Status Indicates Initiation of a bus cycle anCi. along with M/lO and CODjI'm'A. defines
the type of bus cycle. The bus Is In a Ts state whenever one or both are LOW. ST and SO are
active LOW and float to 3-state OFF during bus hold acknowledge.
80286 Bus Cycle Status Definition
COD/INTA
o (LOW)
0
0
0
0
0
0
0
1 (HIGH)
1
1
1
1
1
1
1
M/IO
0
COD/INTA
0
LOCK
0
READY
I
HOLD
HLDA
0
INTR
I
NMI
I
I
MilO
S1
SO
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
'0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
Bus cycle Initiated
Interr,up! acknowledge
Reserved
Reserved
None; not a status cycle
IF A1 = 1 then halt; else shutdown
Memory data read
Memory data write
None; not a status cycle
Reserved
110 read
1I0wnte
None, not a status cycle
Reserved
Memory instruction read
Reserved
None; not a status cycle
Memory/IO Select distinguishes memory access from I/O access. If HIGH during T$. a memory
cycle or a halt/shutdown cycle is in progress. If LOW. an 1/0 cycle or an interrupt acknowledge cycle
is in progress. M/iO floats to 3-state OFF during bus hold acknowledge.
Code/Interrupt Aeknowledge distinguishes instruction fetch cycles from memory data read cycles,
Also distinguishes interrupt acknowledge cycles from 1/0 ;gcles. COD/W' floats to 3-state OFF'
during bus hold acknowledge. Its timing is the same as MI ,
.
.
Bus Loek indicates that other system bus masters are not to gain control· of the system bus following
the current bus cycle. The LOCK signal may be activated explicitly by the "LOCK" instruction prefix
or automatically by 80286 hardware during memory XCHG instructions. interrupt acknowledge. or
descriptor table access. LOCK is active LOW and floats to 3-state OFF during bus hold acknowledge.
Bus Ready terminates a bus cycle. Bus eycles are extended without limit until terminated by READY
LOW. READY is an active LOW synchronous input requiring setup and hold times relative to the
system clock be met for correct operation. READY is ignored during bus hold acknowledge.
Bus Hold Request and Hold Aeknowledge control ownership of the 80286 local bus. The HOLD
input allows another local bus master to request control of the local bus. When control is granted. the
80286 will float its bus drivers to 3-state OFF and then activate HLDA. thus entering the bus hold
acknowledge condition, The local bus will 'remain granted to the requesting master until HOLD
becomes inactive which results in the 80286 deactivating HLDA and regaining control of the local
bus. This terminates the bus hold acknowledge condition. HOLD may be asynchronous to the system
clock. These signals are active HIGH,
Interrupt Request requests the 80286 to suspend its current program execution and service a
pendjng external request. Interrupt requests are masked whenever the interrupt enable bit in the
flag word is cleared. When the 80286 responds to an interrupt request. it performs two interrupt
acknowledge bus cycles to read an 8-bit interrupt vector that identifies the source of the interrupt. To
assure program interruption. INTR must remain active until the first interrupt acknowledge cycle is
completed. INTR is sampled at the beginning of each processor cycle and must be active HIGH at
least two processor cycles before the current Instruction ends in order to interrupt before the next
instruction. INTR is level sensitive. active HIGH. al)d may be asynchronous to the system clock.
Non-maskable Interrupt Request interrupts the 80286 with an internally supplied vector value of
2. No interrupt acknowledge cycles are performed. The interrupt enable bit in the 80286 flag word
does not affect this input. The NMI input is active HIGH. may be asynchronous to the system clock.
and is edge triggered after internal synchronization. For proper recognition. the input must have
been previously LOW for at least four system clock cycles and remain HIGH for at least four system
clock cycles.
~-3
AFN-02060D
inter
I,~
','
,' ,
~,
Symbol
PEREQ
"IYpe
I
, PEACK,
0
BUSY
ERROR
I
I
RESET
I
~. ~
IAPX, 2$6,( 10
, : . ':
Table1. Pin Description (COnI)
'"
Name and FUnction
PrCICeIIOr Extenlloll,O/Ierand Rlqulltiand ,AcknowlWge extend the memory management and protection
capabilities ,of, the 80286 to processor extensions. The PEREQ input requests the 80286 to perform a daIP
operand transfer ,for a processor extension. :rne ~'outliut signals the processor extension when the
requested operand is being transferred. PEREQ is active HIGH and HOlts to 3-state OFF during bus hold
e.c:I
P= 1
P=O
Segment is mapped into physical memory.
,
No mapping to physical memory exists, ba~ and limit are not used.
Segment privilege attribute used in privilege tests.
5 = 1
5=0
Code or Data (includes stacks), segment descriptor
System Segment Descriptor or Gate Descriptor
E=O
EO = 0
ED;' 1
Data segment descriptor type is:
Expand up segment, offsets must be ~ limit.
Expand down segment, offsets must be > limit.
Data segment may not be written into.
Data segment may be written into.
W= 0
W= 1
2
Executable (E)
Conforming (C)
E= 1
C = 1
1
Readable (R)
R=O
R-1
0
Accessed (A)
A=O
A=1
Codo Sogm"" """lpIo<
typo.,
}"
J"
=ment
(S = 1,
E = 0)
Code segment may only be executed when CPL ~ DPL' gocte ant
and CPL remains unchanged.
'
"
egm
'
Cd'
(S=1,
o e segment may notb
• e read .
'E
_ 1)
'Code'segment may be read.
Segment has not been accessed.
Segment selector has been loaded into segment register or used
by selector test instructions,
Figure 11. Code, and Data Segment Descriptor Formats
4-15
AFN·02060D
IAPX286'i10
System Segment DeSCriptor
Code and data (including stack data) are stored in two
types of segments: code segments and data segments.
Both types are identified and defined by segment descriptors (S = 1). Code segments are identified by the executable (E) bit set to 1 in the descriptor access rights byte. The
!}ccess rights byte of both code and data segment descriptor types have three fields in common: present (P) bit,
Descriptor Privilege Level (DPL) , and accessed (A) bit.
If P = 0, any attempted use of this segment will cause
a not-present exception. DRL specifies the privilege level
of the segment descriptQr. DPL controls when the descriptor may be used by a task (refer to privilege discussion
below). The A bit shows whether .the segment has been
previously accessed for usage profiling, a necessity for
virtual memory systems. The CPU will always set this bit
when accessing the descriptor.
• 7
INTEL _ERYED"
+7
+5
plDPLJol i nr~l
+3
BAS~15-0
, +1
UMIT, ....
,.
BASEoo-..
+6
+4
+2
• 7
"Muot be HI to a lor _,"bUlly wtth IAPX 318.
System Segment Descriptor Fields
Description
Value
Available Task State Segment (TSS)
TYPE
1
Local Descriptor Table
2
Busy Task State Segment (TSSI
3
Name
Data segments (S = 1, E =0) may be either read-only or
read-write as controlled by the W bit of the access rights
byte. Read-only (W = 0) data segments may not be written into. Data segments may grow in two directions, as
determined by the Expansion Direction (ED) bit: upwards (ED = 0) for data segments, and downwards
(ED =1) for a segment containing a stack. The limit field
for a data segment descriptor is interpreted differently
depending on the ED bit (see Figure 11).
Descriptor contents are not valid
DeSCriptor contents are valid
DeSCriptor Privilege Level
DPL
BASE
24-bit Base Address of special system data
number segment in real memory
LIMIT 16-bit Offset of last byte in segment
number
P
0
1
0-3
Figure 12. System Segment Descriptor Format
A code segment (S=1, E=1) may be execute-only
or execute/read as determined by the Readable (R)
bit. Code segments may never be written into and
execute-only code segments (R=O) may not be read.
A code segment may also have an attribute called
conforming (C). A conforming code segment may be
shared by programs that execute at different privilege levels. The DPL of a conforming code segment
defines the range of privilege levels at which the
segment may be executed (refer to privilege discussion belOW). The limit field identifies the last byte of
, a code segment.
SYSTEM SEGMENT DESCRIPTORS (S = 0, TYPE = 1-3)
In addition to code and data segment descriptors, the protected mode 80286 defines System Segment Descriptors.
These descriptors define speCial system data segments
which contain a table of descriptors (Local Descriptor
Table Descriptor) or segments which contain the execution state of a task (Task State Segment Descriptor).
Rgure 12 gives the formats for the special system data
segment descriptors. The descriptors contain a 24-bit
base address of the segment and a 16-bit limit. The
access byte defines the type of descriptor, its state and
privilege level. The descriptor contents are valid and the
segment is in physical memory if P = 1. If P = 0, the
segment is not valid. The DPL field is only used in Task
State Segment descriptors and indicates the privilege
level at which the descriptor may be used (see Privilege).
Since the Local DescriptorTable descriptor may only be
used by a special privileged instruction, the DPL field is
not used. Bit 4 of the access byte is 0 to indicate that it
is a system control descriptor. The type field specifiee
the descriptor type as indicated in Figure 12.
GATE DESCRIPTORS (S = 0, TYPE = 4-7)
Gates are used to control access to entry points within
the target code segment. The gate' descriptors are call
gates, task gates, interrupt gates and ~ gates. Gates
provide a level of indirection between the source and
destination of the control transfer. This indirection allows
the OPU to automatically perform protection checks and
control entry point of the destination. Call gates are used
to change privilege levels (see Privilege), task gates are
used to perform a task switch, and interrupt and trap
gates are used to specify interrupt service routines. The
interrupt gate disables interrupts (resets IF) while the
trap gate does not.
Figure 13 shows the format of the gate descriptors. The
descriptor contains a destination pointer that pOints to
the descriptor of the target segment and the entry point
offset. The destination selector in an interrupt gate, trap
gate, and call gate must refer to a code segment descriptor. These gate descriptors contain the entry pOint
to prevent a program frotn constructing and using an
illegal entry pOint. Task gates may only refer to a task
state segment. Since task gates invoke a task switch,
the destination offset is not used in the task gate.
Exception 13 is generated when the gate is used if a
destination selector does not refer to the correct de-
4-16
AFN-020600
IAPX 286/10
ception 11 if referenced. DPL is the descriptor privilege
level and specifies when this descriptor may be used by
!l task (refer to privilege discussion below). Bit 4 must
equal 0 to indicate a system control descriptor. The type
field specifies the descriptor type as indicated in Figure
13.
Gate Descriptor
07
+5
PIDPLIOI
+3
+1
'Mull be
+6
INTEL RESERVED'
+7
TYPE
Ix x xl
~g~,\;4-0
DESTlNAnON SELECTOR'5-'
,.
DESnNATION OFFSET
IXX
+4
+2
,5-0
SEGMENT DESCRIPTOR CACHE REGISTERS
A segment descriptor cache register is assigned to each
of the four segment registers (CS, SS, OS, ES). Segment
descriptors are automatically loaded (cached) into a segment descriptor cache register (Figure 14) whenever the
associated segment register is loaded with a selector.
Only segment descriptors may be loaded into segment
descriptor cache registers. Once loaded, all references
to that segment of memory use the cached descriptor
information Instead of reaccessing the descriptor. The
descriptor cache registers are not visible to programs.
No instructions exist to store their contents. They only
change when a segment register is loaded.
• 7
.ot to 0 lor _"'bliity wllt1lAPX 388.
(X I. don'\ clrl)
Gate Descriptor Fields
Value
Description
4
-Call Gate
5
-Task Gate
TYPE
-Interrupt Gate
6
7
-Trap Gate
P
-Descriptor Contents-are not
0
valid
1
-Descriptor Contents are
valid
DPL
0-3
Descriptor Privilege Level
WORD
Number of words to copy
COUNT
from callers stack to called
0-31
procedures stack. Only used
with call gate.
Selector to the target code
segment (Call, Interrupt or
DESTINATION
16-bit Trap Gate)
SELECTOR
selector
Selector to the target task
state segment (Task Gate)
DESTINATION
16-bit Entry point within the target
OFFSET
offset code segment
Name
SELECTOR FIELDS
A protected mode selector has three fields: descriptor
entry index, local or global descriptor table indicator (TI),
and selector privilege (RPL) as shown in Figure 15. These
fields select one of two memory based tables of descriptors, select the appropriate table entry and allow high·
speed testing of the selector's privilege attribute (refer
to privilege discussion below).
SELECTOR
II
Figure 13. Gate Descriptor Format
BITS
scriptor type. The word count field is used in the call gate
descriptor to indicate the number of parameters (0-31
words) to be automatically copied from the caller's stack
to the stack of the called routine when a control transfer
changes privilege levels. The word count field is not used
by any other gate descriptor.
The access byte format is the same for all gate descriptors. P = 1 indicates that the gate contents are valid. P
= 0 indicates the contents are not valid and causes ex-
I
~~g~~
I
SEGMENT SELECTORS
0
SEGMENT REGISTERS
(LOADED BY PROGRAM)
I
I
47
,
!
,
3 2 1 0
FUNcnON
NAME
1-0
REQUESTED
PRIVILEGE
LEVEL
(RPL)
INDICATES SELECTOR PRIVILEGE
LEVEL DESIRED
2
TABLE
INDICATOR
(TI)
n
15-3
INDEX
SELECT DESCRIPTOR ENTRY IN TABLE
= 0 USE GLOBAL DESCRIPTDR TABLE
(GDT)
TI = 1 USE LOCAL DESCRIPTOR TABLE
(LDT)
";.R'oGR;M;V-;;I;Li" -
-
-
-
-
-
-
---,
I
SEGMENT PHYSICAL BASE ADDRESS
~~ i I I
15
!
Figure 15. Selector Fields
r - - -- - - - - -
PRoGRAM VISIBLE
INDEX
!
15
40 39
SEGMENT SIZE
I
16 15
SEGMENT DESCRIPTOR CACHE REGISTERS
L ______ (~~~~CA~L:~~~B~c~_________ J
I
Figure 14. Descriptor Cache Registers
4-17
AFN-02060D
IAPX 286/10
LOCAL AND GLOBAL DESCRIPTOR TABLES
Two tables of descriptors. called descriptor tables. contain all descriptors accessible by a task at any given time.
A descriptor table is a linear array of up to 8192 descriptors. The upper 13 bits of the selector value are an index
into a· descriptor table. Each table has a 24-bit base register to locate the descriptor table in physical memory
and a 16-bit limit register that confine descriptor access
to the defined limits of the table as shown in Figure 16. A
restartable exception (13) will occut if an attempt is made
to reference a descriptor outside the table limits.
o7
+5
MEMORY
BASE23-16
I
+3
BASE15-o
+1
LlM1T'5-0
15
+4
+2
• 7
*Must be s.t to 0 for compatibility with IAPX 386.
Figure 17. Global Descriptor Table and Interrupt
Descriptor Table Data Type
INTERRUPT DESCRIPTOR TABLE
The protected mode 80286 has a third descriptor table,
called the Interrupt Descriptor Table (IDT) (see Figure
18), used to define up to 256 interrupts. It may contain
only task gates. interrupt gates and trap gates. The IDT
(Interrupt Descriptor Table) has a 24·bit physical base
and 16-bit limit register in the CPU. The privileged LlDT
instruction loads these registers with a six byte value, of
identical form to that of the LGDT instruction (see Figure
17 and Protected Mode Initialization).
One table. called the Global Descriptor Table (GOT).
contains descriptors available to all tasks. The other table. called the Local Descriptor Table (LOT). contains
descriptors that can be private to a task. Each task may
have its own private LOT. The GOT may contain all descriptor types except interrupt and trap descriptors. The
LOT may contain only segment. task gate. and call gate
descriptors. A segment cannot be accessed by a task if
its segment descriptor does not exist in either descriptor
table at the time of access.
"V
INTEL RESERVED'
"V
"\..
r
MEMORY
'\,
t"
GATE FOR
INTERRUPT #n
GATE FOR
INTERRUPT #n·1
CPU
15
0
..--IIDTLIMIT
I
···
J
INTERRUPT
DESCRIPTOR
TABLE
(lOT)
GATE FOR
. INTERRUPT #1
GATE FOR
INTERRUPT #0
lOT BASE
23
0
~
~
Figure 18. Interrupt Descriptor Table Definition
References to lOT entries are made via INT instruc-'
tions, external interrupt vectors. or exceptions. The lOT
must be at least 256 bytes in size 40 allocate space for
all reserved interrupts.
Figure 16. Local and Global Descriptor
Table Definition
The LGDT and LLDT instructions load the base and limit
of the global and local descriptor tables. LGDT and LLDT
are privileged, i.e. they may only be executed by trusted
programs operating at level O. The LGDT instruction loads
a six byte field containing the 16·bit table limit and 24·bit
physical base address of the Global Descriptor Table as
shown in Figure 17. The LDT instruction loads a, sele,ctor
which refers to a Local Descriptor Table descriptor con·
taining the base address and limit for an LDT, as shown
in Figure 12.
4-18
Privilege
The 80286 has a four-level hierarchical privilege system
whiCh controls the use of privileged instructions and access to descriptors (and their associated segments) within
a task. Four-level privilege, as shown in Figure 19. is an
extension of the user/supervisor mode commonly found
in minicomputers. The privilege levels are numbered 0
through 3. Level 0 is the most privileged level. Privilege
AFN-02060D
IAPX 286/10
lege Level (DPL) field of the descriptor access byte. DPL
specifies the least trusted task privilege level (CPL) at
which a task may access the descriptor. Descriptors with
DPL = 0 are the most protected. Only tasks executing
at privilege level 0 (CPL = 0) may access them. De~
scriptors with DPL = 3 are the least protected (i.e. have
the least restricted access) since tasks can access them
when CPL = 0, 1,2, or 3. This rule applies to all descriptors, except LOT descriptors.
HIGH SPEED
OPERATING
SYS1Ell
INTeRFACE
SELECTOR PRIVILEGE
Selector privilege is specified by the Requested Privilege Level (RPL) field in the least significant two bits of a
selector. Selector RPL may establish a less trusted privilege level than the current privilege level for the use of a
selector. This level is called the task's effective privilege
level (EPL). RPL can only reduce the scope of a task's
access to data with this selector. A task's effective privilege is the numeric maximum of RPL and CPL. A selector with RPL = 0 imposes no additional restriction on its
use while a selector with RPL = 3 can only refer to segments at privilege Level 3 regardless of the task's CPL.
RPL is generally used to verify that pointer parameters
passed to a more trusted procedure are not allowed to
use data at a more privileged level than the caller (refer
to pointer testing instructions).
NarE: PI. BECOMES NUMERICALLY LOWER AS PRMLEGE LEVEl
INCRUSESI
Figure 19. Hierarchical Privilege Levels
levels provide protection within a task. (Tasks are isolated
by providing private LOT's for each task.) Operating
system routines, interrupt handlers, and other system software can be included and protected within the virtual
address space of each task using the four levels of privilege. Each task in the system has a separate stack for
each of its privilege levels.
Tasks, descriptors, and selectors have a privilege level
attribute that determines whether the descriptor may be
used. Task privilege effects the use of instructions and
descriptors. Descriptor and selector privilege only effect
access to the descriptor.
TASK PRIVILEGE
Descriptor Access and Privilege Validation
Determining the ability of a task to access a segment
involves the type of segment to be accessed, the instruction used, the type of descriptor used and CPL,
RPL, and DPL. The two basic types of segment accesses are control transfer (selectors loaded into CS)
and data (selectors loaded into OS, ES or SS).
A task always executes at one of the four privilege
levels. The task ptivilege level at any specific instant
is callep the Current Privilege Level (CPL) and is
defined by the lower two bits of the CS register. CPL
cannot change during execution in a single code segment. A task's CPL may only be changed by control
transfers through gate descriptors to a new code
segment (See Control 'Transfer). Tasks begin executing
at the CPL value specified by the code segment selector within TSS when the task is initiated via a task
switch operation (See Figure 20). A task executing at
Level 0 can access all data segments defined in the
GOT and the task's LOT and is considered the most
trusted level. A task executing a Level 3 has the most
restricted access to data and is conSidered the least
trusted level.
DESCRIPTOR PRIVILEGE
Descriptor privilege is specified by the Descriptor Privi-
4-19
DATA .SEGMENT ACCESS
Instructions that load selectors into OS and ES must
refer to a data segment deSCriptor or readable code segment descriptor. The CPL of the task and the RPL of the
selector must be the same as or more privileged (numerically equal to or lower than) thap the descriptor DPL.
In general, a task can only access data segments at the
same or less privileged levels than the CPL or RPL
(whichever is numerically higher) to prevent a program
fro~ accessing data it cannot be trusted to use.
An exception to the rule is a readable conforming code
segment. This type of code segment can be read from
any privilege level.
If the privilege checks fail (e.g. DPL is numerically less
than the maximum of CPL and RPL) or an incorrect type
of descriptor is referenced (e.g. gate descriptor or execute only code segment) exception 13 occurs. lithe segment is not present, exception 11 is generated: '
AFN-020600
..
'w_r
.~
lAPX286/10
Instruotions that load selectors into SS must refer to data
segrnent descriptors for writable data segments. The
descriptor privilege (D~L) and RPL must equal CPL. All
other descriptor types or a privilege level violation will
cause exception 13. A not present fault causes exception 12.
State Segm,ent descriptor causes a task switch (see Task
Switch' Operation). Reference to a Task State Segment
descriptor at a more privileged level than the task's CPL
generates exception 1:3~
When an instruction or interrupt references a gate descriptor, the gate DPL must have the same' or less privilege than the task CPL. If DPL is at a more privileged
level than CPL, exception ,13 occurs, If the destination
selector co,ntained in the gate references a code segment descriptor, the code segment descriptor DPL must
be the same or more privileged than the task CPL. If not"
Exception 13 is issued. After the control transfer, the
code segment descriptors DPL is the task's new CPL. If
the destination selector in the gate references a task
state segment, a task switch is automatically performed
(see Task Switch qperation).
CONTROL TRANSFER
Four types of control transfer can occur when a selector
i,; loaded into CS by a control transfer operation (see
Table 10). Each transfer type can only occur ifthe o~er
ation which loaded the selector references the correct
descriptor type. Any violation of these descriptor usage
rlJles (e.g. JMPthrough a call gate or RETto a Task State
Segment) will cause excep!ion 13.
llhe ability to reference a descriptor for control transfer
il; also subject to rules of privilege. A CALL or JUMP
instruction may only reference a code segment descriptor with DPL equal to the task CPL or a conforming segment with DPL of equal or greater privilege than CPL.
The RPL of the selector used to reference the code descriptor must have as much privilege as CPL.
The privilege rules on"control transfer require:
-JMP or CALL direct to a code segment (code segment descriptor) can only be to a conforming segment
with DPL of equal or greater privilege than CPL or a
non-conforming segmel')t at the same privilege level.
-interrupts within the task or calls that may change
privilege levels, can only transfer control through a
gate at the same or a less privileged level than CPL to
a code segment at the same or more privileged level
thanCPL.
RET and IRET instructions may only reference code
segment descriptors with descriptor privilege equal to or
less privileged than the task CPL. The selector loaded
into CS is the return address from the stack. After the
return, the selector RPL is the task's new CPL. If CPL
changes, the old stack pOinter is popped after the return
address.
-return instructions that don't switch tasks can only return control to a code segment at the same or less
privileged level.
When a JMP or CALL references a Task State Segment
descriptor, the descriptor DPL must be the same or less
privileged than the task's CPL. Reference to a valid Task
-task switch can be performed by a call, jump or interrupt which references either a task gate or task state
segment at the same or less privileged level.
Table 10. Descriptor Types Used for Control Transfer
Control Transfer lYpes
Operation lYpes
Intersegment within the same privilege level
JMP, CALL, RET, IRET'
CALL
Intersegment to the same or higher privilege level Interrupt
within task may change CPL.
Intersegment to a lower privilege level (changes task CPL)
Task Switch
I
Interrupt Instruction,
Exception, External
Interrupt
RET,IREr
CALL,JMP
CALL,JMP
IRET"
Interrupt Instruction,
Exception, External
Interrupt
Descriptor
Referenced
Code Segment
Call Gate
Trap or
Interrupt
Gate
Code Segment
Task State
Segment
Task Gate
Descriptor
Table
GOT/LOT
GOT/LOT
lOT
Task Gate
lOT
GOT/LOT
GOT
GOT/LOT
'NT (Nested Task bit of flag word) = 0
"NT (Nested Task bitofflag word) = 1
4-20
AFN·02060D
)
-
IAPX288/10
PRIVILEGE LEVEL CHANGES
Any control transfer that changes CPL within the task,
causes a change of stacks as part ofthe operation. Initial
values of 55:5P for privilege levels 0, 1, and 2 are kept
in the task state segment (refer to TaSk Switch Operation). During a JMP or CALL control transfer, the new
stack pointer is loaded into the 55 and 5P registers and
the previous stack pOinter is pushed onto the new stack.
Table 11
Segment Register Load Checks
Exception
Error Description
Number
Descriptor table limit exceeded
13
Segment deSCriptor not-present
11 or 12
Privilege rules violated
13
When returning to the original privilege level, its stack is
restored as part of the RET or IRET instruction operation. For subroutine calls that pass parameters on the
stack and cross privilege levels, a fixed number of words,
as specified in the gate, are copied from the previous
stack to the current stack. The inter-segment RET instruction with a stack adjustment value will correctly restore the previous stack pOinter upon return.
Invalid descr'iptorlsegment type segment register load:
-Read only data segment load to
SS
-Special control descriptor load to
OS,ES,SS
-Execute only segment load to
OS, ES, SS
-Oata segment load to CS
-Read/Execute code segment
loadtoSS
13
Protection
The 80286 includes mechanisms to protect critical instructions that affect the CPU execution state (e.g. HLn
and code or data segments from improper usage. These
protection mechanisms are grouped into three forms:
Restricted usage of segments (e.g. no write allowed
to read-only data segments). The only segments
available for use are defined by descriptors in the Local Descriptor Table (LOT) and Global Descriptor Tac
ble(GDT).
.
Restricted ~ to. segments via the rules of privilege and descriptor usage.
Privileged instructions or operations that may only be
executed at certain privilege levels as determined by
the CPL and 110 Privilege Level (IOPL). The 10PL is
- defined by bits 14and 130ftheflag word.
These checks are performed for all instructions and can
be split into three categories: segment load checks (Table 11), operand reference checks (Table 12), and privileged instruction checks (Table 13). Any violation of the
rules shown will result in an exception. A not-present
exception related to the stack segment causes exception 12.
The IRET and POPF instructions do not perform some of
their defined functions if CPL is noJ of sufficient privilege
(numerically small enough). Precisely these are:
• The IF bit is not changed if CPL > IOPL
• _The IOPL field ofthe flag word is not changed if CPL > O.
No exceptions or other indication are given when these
conditions occur.
Table 12 Operand Reference Checks
Exception
Error Description
Number
Write into code segment
13
Read from execute-only code
segment
13
Write to read-only data segment
13
Segment limit exceedEld'
120r13
Note 1: Carry out in offset calculations is ignored.
Table 13. Privileged Instruction Checks
Exception
Error Description
Number
CPL oF 0 when executing the following
instructions:
13
LlOT, LLOT, LGOT, LTR, LMSW,
CTS,HLT
CPL > IOPL when executing the following instructions:
13
INS, IN, OUTS, OUT, STI, CLI,
LOCK
EXCEPTIONS
The 80286 detects several types of exceptions and interrupts, in protected mode (see Table 14). Most are restartable after the exceptional condition is removed. Interrupt
handlers-for most exceptions can read an error code,
pushed on the stack after the return address, that identifies the selector involved (0 if none). The return address
normally points to the failing instruction, including all
leading prefixes. For a processor extension segment overrun exception, the return address will not point .at the
ESC instruction that caused the exception; however, the
processor extension registers may contain the address
of the failing instruction.
! .
4-21
AFN-Q2060D
- - - ' - _...
_-_... .
.--. _.-._ ..
...........,._P..
Interrupt
Vectqr
8
9
10
11
12
13
IAPX '2861 10
Table 14 Protected Mode Exceptions
Return
Address
Function
. Atr=alUng
Instruction?
Double exception detected
Yell
Processor extension segment oVerrun
No
Invalid task state segment
'Yes
Segment not present
Yes
Yes
Stack segment overrun or stack segment not present
Yes
General protection
Always
Restartable?
Error
Code
on Stack?
N02
N02
Yes
Yes
Yes 1
N02
Yes
No
Yes
Yes
Yes
Yes
NarE 1: When a PUSHA or POPA instruction attempts to wrap around the Slllck segment, the machine state after the
exception JNiIl not be restartable because stack segment wrap around is not permitted. This condition is identified
by the value of the saved SP being eighe[ OOOO(H), 0001 (H), FFFE(H),. or FFFF(H).
.'
HarE 2: These exceptions Indicate a violation to privilege rules or usage rules has occurred. Restart is generally not
attempted under those conditions.
These exceptions indicate a violation to privilege rules
or usage rules has occurred. Restart is generally not
attempted under those conditions.
All these checks are performed for all Instructions and
can be split into three categories: segment load checks
(Table 11), operand reference checks (Table 12), and
privileged instruction checks (Table 13). Any violation
of the rules shown will result in an exception. A
not-present exception causes exception 11 or 12 and
is restartable. .
.
NT = 1, IRET performs a task switch operation back
to the previous task. When a CALL, JMP, or INT instruction initiates a task'
switch, the old and new TSS will be marked busy and
the back link field of the new TSS set to the old TSS
selector. The NT bit of the new task is set by CALL or
INT initiated task switches. An interrupt that does not
cause a task switch will clear NT. NT may also be set
or cleared by POPF or IRET instructions.
The task state segment is marked busy by changing,
the descriptor type field from Type 1 to Type 3. Use
of a selector that references a busy task state segment
causes Exception 13.
Special Operations
TASK SWITCH OPERATION
The 80286 provides a built-in task switch operation which
saves the entire 80286 execution state (registers, address space, and a link to the previous task), loads a
new execution state, and commences execution in the
new' task. Like gates, the task switch operation is invoked by executing an inter-segment JMP or CALL instruction which refers to a Task State Segment (TSS) or
task gate descriptor in·the GOT or LOT. An INT n instruction, exception, or external interrupt may also invoke the
task switch operation by selecting a task gate descriptor
in the associated lOT descriptor entry.
The TSS descriptor points at a segment (see Figure 20)
containing the entire 80286 execution state while a
task gate descriptor contains a TSS selector. The limit
field of the descriptor must be >002B(H).
Each task must have a TSS associated with it. The current TSS is identified by a special register in the 80286
called the Task Register (TR). This register contains a
selector referring to the task state segment descriptor
that defines the current TSS. A hidden .base and limit
register .associated with TR are loaded whenever TR is
loaded with a new selector.
PROCESSOR EXTENSION CONTEXT SWITCHING
The context of a processor extension (such as the 80287
numerics processor) is not changed by the task switch
operation. A processor extension context need only be
changed when a different task attempts to use the processor extension (which still contains t~e context of a
previous taSk). The 80286 detects the first use of a processor extension after a task switch by causing the processor extension not present exception (7). The interrupt
handler may then decide whether a context change is
necessary.
Whenever the 80286 switches tasks, it sets'the Task
Switched (TS) bit of the MSW. TS indicates that a pro~
cessOr extension context may belong to a different task
than the current one. The processor extension not present exception (7) will occur when attempting to execute
an ESC or WAIT instruction if TS = 1 and a processor
extension is present (MP = 1 in MSW).
The IRET instrLiction is used to return c6ntrol to the
task ~hat called the current task or was interrupted.
Bit 14 in the flag egister is called the Nested Task (NT)
bit. It controls the function of the IRET instruction. If
NT = 0, the IRET iostruction performs the regular current task return by popping values off the stack; when
4-22
POINTER TESTING INSTRUCTIONS
The iAPX 286 provides several instructions to speed
pdinter testing and consistency checks for maintaining system integrity (see Table 15). These instructions use the memory management hardware to
verify that a selector value refers to an appropriate
segment without risking an exception. A condition
flag (ZF) Indicates' whether use of the selector or
segment will cause an exception.
AFN-02060D
IAPX 286/10
~
CPU
INTEL RESERVED
plrHTYp~1
TASK REGISTER
TRD--.. •
SYSTEM
. . . SEGMENT
DESCRIPTOR
..
PROGRAM INVISIBLE
I
I
I
:I I..
I
•
UMIT
BASE
11..---
---•
TYPE
}
BASE....,.
BASE, ...
r---------.,
I
'"
I
I
U!'IIT,...
H
------------
-----~
I
--'
DESCRIPTION
1
AN AVAILABLE TASK STATE
SEGMENT. MAY BE USED AS
THE DESTlNAlION OF A TASK
SWITCH OPERATION •
3
A BUSY TASK STATE SEGMENT.
CANNOT BE USED AS THE
DESTINATION OF A TASK
SWITCH.
I
_...J
~~.
15
TASK LDT SELECTOR
42
DSSELECTOR
40
SSSELECTOR
38
CSSELECTOR
I
BYTE
OFFSET
0
,
ESSELECTOR
38
34
DI
32
$I
30
BP
28
SP
26
BX
24
DX
22
CX
20
J
TASK
STATE
SEGMENT
P DESCRIPTION
1 BASE AND LIMIT FIELDS ARE VALID
0 SEGMENT IS NOT PRESENT IN
MEMORY, BASE AND LIMIT ARE NOT
DEFINED
AX
18 .
FLAG WORD
18
IP (ENTRY POINT)
14
SSFOR CPL 2
12
SPFORCPL2
10
sS FOR CPL 1
8
SP FOR CPL 1
6
SSFORCPLO
4
SP FOR CPLO
2
BACK LINK SELECTOR TO TSS
0
CURRENT
TASK
STATE
INITIAL
STACKS
FOR CPLO,1,2
~
~
Figure 2Q. Task State Segment and TSS Registers
4-23
AFN-02060D
IAPX 286/10
Table 15. 80286 Pointer Test Instructions
.
To force the 80286 CPU registers to match the initial
protected mode state assumed by software, execute
a JMP instruction with a selector referring to the
initial TSS used in the system. This will load the task
register, local descriptor table register. segment
registers and initial general register state. The TR
should point at a valid TSS since any task switch
operation involves saving the current task state.
Function
Instruction
Operands
ARPL
Selector,
Register
Adjust Requested Privilege Level: adjusts the RPL
of the selector. to the numeric maximum of current
selector RPL value and the
RPL value in the register.
Set zero flag if selector RPL
was changed by ARPL.
VERR
Selector
VERW
Selector
LSL
Register,
Selector
VERify for Read: sets the
zero flag if the segment referred to by the selector can
be read.
VERify for Write: sets the
zero flag if the segment referred to by the selector can
be written.
Load Segment Umit: reads
the segment limit into the
register if privilege rules and
descriptor type allow. Set
zero flag if successful.
LAR
Register,
Selector
SYSTEM INTERFACE
The 80286 system interface appears in two forms: a
local bus and a system bus. The local bus consists of
address, data. status. and control signals at the pins of
the CPU. A system bus is any buffered version of the
local bus. A system bus may also differ from the local
bus-in terms of coding of status and control lines and/or
timing and loading of signals. The iAPX 286 family includes several devices to generate standard system
buses such as the IEEE 796 standard Multibus'" .
Load Access Rights: reads
the descriptor access rights
byte into the register if privilege rules allow. Set zero
flag if successful.
Bus Interface Signals and Timing
The iAPX 286 microsystem local bus interfaces the 80286
to local memory and 110 components. The interface has
24 address lines, 16 data lines, and 8 status and control
signals.
DOUBLE FAULT AND SHUTDOWN
If two separate exceptions are detected during a single
instruction execution. the 80286 performs the double
fault exception (8). If an exception occurs during processing of the double fault exception. the 82086 will enter shutdown. Ouring shutdown no further instructions
or exceptions are processed. Either NMI (CPU remains
in protected mode) or RESET (CPU exits protected mode)
can force the 80286 out of shutdown. Shutdown is externally signalled via a HALT bus operation with AI HIGH.
The 80286 CPU, 82284 clock generator, 82288 bus
controller, 82289 bus arbiter, 8286/7 transceivers,
and 8282/3 latches provide a buffered and decoded
system bus interface. The 82284 generates the
system clOCk and synchronizes REAOY and RESET.
The 82288 converts bus operation status encoded
by the 80286 into command and bus control signals.
The 82289 bus arbiter generates Multibus bus
arbitration signals. These components can provide
the timing and electrical power drive levels required
for most system bus interfaces including the Multibus.
PROTECTED MODE INITIALIZATION
The 80286 initially executes in real address mode
after RESET. To allow initialization code to be placed
at the top of physical memory. A 23-20 will be HIGH
when' the 80286 performs membry references
relative to the CS register until CS is changed. A 23-20
will be zero for references to· the OS. ES, or SS
segments. Changing CS in real address mode will
force A23-20 LOW whenever CS is used again. The
initial CS:IP value of FOOO:FFFO provides 64K bytes
of code space for initialization code without changingCS.
Protected mode operation requires several registers to be initialized. The GOT and lOT base registers must .refer to a valid GOT and lOT. After
executing the LMSW instruction to set PE. the 80286
must immediately execute an intra-segment JMP
instruction to clear the instruction queue of instructions decoded in real address mode.
PhYSical Memory and 1/0 Interface
A maximum of 16 megabytes of physical memory can
be addressed in protected mode. One megabyte can be
addressed in real address mode. Memory is accessible
as bytes or words. Words consist of any two consecutive
bytes addressed with the least significant byte stored in
the lowest address.
Byte transfers occur on either half of the 16-bit local data
bus. Even bytes are accessed over 07..,0 while odd bytes
are transferred over 015-8. Even-addressed words are
transferred over 0 15-0 in one bus cycle, while odd-addressed words require two bus operations. The first
transfers data on 0 15-8. and the second transfers data
on 07-0. Both byte data transfers occur automatically,
transparent to software.
Two bus signals. Ao and SHE. control transfers over the
lower and upper halves of the data bus. Even address
.4-24
AFN-02060D
IAPX286J10
byte transfers are indicated by Ao LOW and BRE' HIGH.
Odd address byte transfers are indicated by Ao HIGH
and SHE LOW. Both Ao and SHE are LOW for even address word transfers.
RESET
The I/O address space contains 64K addresses in both
modes. The I/O space is accessible as either bytes or
words, as is memory. Byte wide peripheral devices may
be attached to either the upper or lower byte of the data
bus. Byte-wide I/O d,vices attached to the upper data
byte (015-8) are accessed with odd I/O ac.idresses. Devices on the lower data byte are accessed with even 1/0
addresses. An interrupt controller such as Intel's 8259,A
must be connected to the lower data byte (D,.-() for proper
return of the interrupt vector.
Figure 22. 80286 Bus States
Bus States
Bus Operation
The 80286 uses a double frequency system clock (CLK
input) to control bus timing. All signals on the local bus
are measured relative to the system CLK input. The CPU
divides the system clock by 2 to produce the internal
prOCessor clock, which determines bus state. Each pro~
cessor clock is composed of two system clock cycles
named phase 1 and phase 2. The 82284 clock generator
output (PCLK) identifies the next phase ofthe propessor
clock. (See Figure 21.)
After Ts,the perform command· (Tc> state is entered.
Memory or I/O devices respond to the bus Operation
during Tc, either transferring read ·data to the CPU or
accepting write data. Tc states may be repeated as
often as necessary to assure sufficient time for the
memory or I/O device to respon~. The READY signal
determines whether Tc is repeated. A repeated Tc
state is called a wait state.
CLK
_ONESYSTEM~
CLKCYCLE ~
PCLKy
The idle (Tj) state indicates that no data trans~rs are
in progress or requested. The first active state Ts is
signaled by status line "Sf or SO going LOW and identifying phase 1 of the processor clock. During Ts, the
command encoding, the address, and data (fpr a write
operation) are available on the 80286 output pins. -The
82288 bus controler decodes the status signals and
generates Multibus compatible read/write command
and local transceiver contrOl. signals.
V
, \ -_ _---:l
Figure 21. System and Processor
Clock Relationships.
.
Six types of bus operations..are supported; memory read,
memory write, I/O read, I/O write, interrupt acknowledge, and halt/shutdown. Data can be transferred at a
maximum rate of one word pertwo processor clock cycles.
The iAPX 286 bus has three basic states: idle (Tj), send
status (Ts), and perform command (Td. The 80286 CPU'
also has a fourth Iocal·bus state called hold'(Th). Th indicates that the '80286 has surrendered contr61 of the
local bus to another bus master in response to a' HOLD
request.· .
Each bus state is one processor clock long. Figure 22
shows the four 80286 local bus states and allowed
transitions.
During hold (Th), the 80286 will float all address, data,
and status output pins enabling another bus master
to use the local bus. The 80286 HOLD input signal
is used to place the 80286 into ~he Th state. The
80286 HLDA output signal indicates that the CPU has
entered Th;
..
.
.
Pipelined Addressing
The 80286 uses.a local bus interlace with pipelined
timing to. allow as much time as possible. for data
access. Pipelined timing. allows a new bus operation
to be initiated eV9fY two processor cycles,while allowing each individual bus operation to last for three
processor .cYcles.
.'
.
The timing of the address outputs is pipelined such that
the address of the next bus oper~tion be<¥omes available
.. during the current bu~ ope~ation. Or in other words, the
first clock of the next bus operation is overlapped with
the last clock of the current bus operation. Therefore,
address decode and routing logic can operate in ad-
i\FN-02060D
, IAPX 286/10
T,
F
""
READ BUS CYClE N'
-~Tc
l~
T5
-- -
------------------c::>VALID READ
DATA(N)
PtPeuNING: VALID ADDRESS (N
VALlO REAO
DATA (N+1.
+ 1) AVAILABLE IN LAST PHASE OF BUS CYCLE (N),
Figure 23. Basic Bus Cycle
, vance of the next bus operation. External address latches
may'hold the address stable for the entire bus operation,
and provide additional AC and DC buffering.
The 80286 does not maintain the address of the current
bus operation during all Tc states. Instead, the address
for the next bus operation may be emitted during phase
2 of any Tc' The address remains valid during phase 1
of the first Tc to guarantee hold time, relative to ALE, for
the address latch inputs.
Bus Control Signals
The 82288 bus controller provides control signals; address latch enable (ALE), ReadlWrite commands, data
transmit/receive (DTIR) , and data enable (DEN) that
control the address latches, data transceivers, write enable, and output enable for memory and I/O systems.
The Address Latch Enable (ALE) output determines when
the address may be latched. ALE provides at least one
system CLK period of address hold time from the end of
the previous bus operation until the address for the next
bus operation appears at the latch outputs. This address
hold time is required to support tI('Iultibus® and common
memory systems.
The data bus transceivers are controlled by 82288 outputs Data Enable (DEN) and Data Transmit/Receive (DT/
R). DEN enables the data transceivers; while DT/R controls transceiver direction. DEN and DT/R are timed to
prevent bus contention between the bus master, data
bus transceivers, and system data bus tranceivers.
Command Timing Controls
Two system timing customization options, command extension and command delay, are provided on the iAPX
286 local bus.
Command extension allows additional time for external
devices to respolJd to a command and is analogous to
inserting wait states on the 8086. External logic can control the duration of any bus operation such that the operation is only as long as necessary. The REJmV' input
signal can extend any bus operation for as long as
necessary.
Command delay allows an increase of address or wrjte
data setup time to system bus command active for any
bus operation by delaying when the system bus command becomes active. Command delay is controlled by
the 82288 CMDLY input. After Ts, the bus controller
samples CMDLY at each failing edge of CLK. If CMDLY
is HIGH, the 82288 will not activate the command signal.
When CMDLY is LOW, the 82288 will activate the command signal. After the command becomes active, the
CMDLY input is not sampled.
When a command is del;:tyed, the available response
time from command active to return read data or accept
write data is less. To customize ~ystem bus timing, an
address decoder can determine which bus operations
require delayingtM command. The CMDLY input dotTS
not affect the timing of ALE, DEN, or DTIR.
4-26
AFN-02060D
IAPX 286/10
1 + - - - - - - - READ BUS CYCLE N -1'-'- - - - - - . \ + - - - - 1 READ BUS CYCLE Nil1-- - - . I
ClK
PROC----'
ClK
ALE _ _ _J
EX1
~
Rl)
COMMAND
CMOLY _ _ _oJ
EX2
~
Rl)
'COMMANDi
CMDlV
•
Figure 24. CMDLY Controls the Leading Edge of Command Signal.
Figure 24 illustrates four uses of CMDlY. Example 1
shows delaying the read command two system ClKs for
cycle N-1 and no delay for cycle N, and example 2 shows
delaying the read command one system ClK for cycle
N-1 Flnd one system ClK delay for cycle N.
Bus Cycle T-ermination
At maximum transfer rates, the iAPX 286 bus alternates
between the status and command states. The bus status
signals become inactive after Ts so that they may correctly signal the start of the next bus operation after the
completion ofthe current cycle. No external indication of
TC exists on the iAPX 286 local bus. The bus master and
bus controller enter Tc directly after Ts and continue executing Tc cycles \:Intil terminated by READ'?
READY Operation
The current bus master and 82288 bus controller terminate each bus operation simultaneously to achieve
maximum bus operation bandwidth. Both are informed
in advance by READY active (open-collector output
from 82284) which identifies the last Tc cycle of the
current bus operation. The bus master and bus controller must see the same sense of the ~ signal,
thereby requiring R'EAl5? be synchronous to the
system clock.
Synchronous Ready
The 82284 clock generator provides READ'? synchronization from both synchronous and asynchronous
sources (see Figure 25). The synchronous ready input
(SROY) of the clock generator is sampled with the falling
edge of ClK at the end of phase 10f each Tc. The state
ofSROY is then broadcast to the bus master and bus
controller via the READ'? output line.
Asynchronous Ready
Many systems have devices or subsystems that are
asynchronous to the system Clock. As a result; their
SR~ outputs cannot be guaranteed to meet the 82284
setup and hold time requirements. But the
82284 asynchronous ready input (AROYl is designed
.to accept such signals. The ARn'Y input is sampled at
the beginning of each Tc cycle by 82284 synchronization logic. This provides one system ClK cycle time to
resolve its value before broadcasting it to the bus
master and bus controller.
.
4-27
AFN·02060D
.... .
....
'-
IAPX 286/10
' ,
•
CLK
PROCCUC
IIDIIY
(SEE NOTE 1.)
(SEE NOTE 2.)
-~\1i\\1i'i%\W> ~
(SEE NOTU.)
NOTES:
,
1. ~isactivelow
2. Ifsm5'i'EN is high. the state of IDIDVwill not effect READY
3. AFiDYEN is active low
. Figure 25. Synchronous and Asynchronous Ready
ARDY or ARDYEN must be HIGH at the end of Ts.
ARDY cannot be used to terminate bus cycle with
no wait states.
The data bus is driven with write data during the second
phase of Ts. The delay in write data timing allows the
read data drivers, from ,a previous read cycle, sufficient
time to enter 3-state OF,F before the 80286 CPU begins
driving the local data bus for write operations. Write data
wilt always remain valid for one system clock past the
last Tc to provide sufficient hold time for Multibus or other
similar memory or 1/0 systems. During write-read or write, idle sequences the data bus enters 3-state OFF during
the second phase of the processor cycle after the last
Tc' In a write-write sequence the data bus does not enter
3-state OFF between Tc and Ts.
Each ready input of the 82284 has an enable pin
(SRDYEN and ARDYENj to select whether the current
bus operation will be terminated .by the synchronous or
asynChronous ready. Elther,of the ready inputs may terminate a bus operation. These enable inputs are active
low and have-the same timing as their respective 'ready
inputs. Address decode logic usually selects Whether
. the current bus operation should be terminated byARDY
orSRO'?
Bu~Usage
Data Bus,Control
Figures 26, 27, and 28 show, how the DTIR, DEN. data
bus, and address signals operate for different combinations of read, write, and idle bus operations. DT/R goes
active (LOW) for a read ·operaton. DT/R remains HIGH '
before, durihg, and between write operations.
. The 80286 local bus may be used for several functions:
instruction data transfers, data transfers by other bus
masters, instruction fetching, processor e~en~i9n data
transfers, interrupt acknowledge, and hait/shutc:!oWri. This
section describes local bus activities which have special
signals or requirements.
.
4-28
.
.
AFN-020600
ner ------------------------------------------------------IAPX 286/10
~
,~1
'I'
~
......____T,
dI2
<111
READ BUS-+--CYCLE, Tc------" 4 - - 1 5
WRITE
CYCLE
- - T . ______ 4 - - - - - T5-----'
- - BUS
"+
- - -Te
I
d>2
11
I
tb2
<1>'
1-" - - - - - - - -
::~~E~~Y,f//J$~~
NOT READY
NOT READY
'...._-------'
Mwfc
~H - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - iOTiR
' _---
DEN
.....
AlE _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~,_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _
15
Te
~
=
STATUS CYCLE
CqMMAND CYCLE
NOTES:
1. Status lines are not driven by 80286, yet remain high due to pullup resistors In 82288 and 82289 dUring HOLD state
2. Address, M/iO and COD/INTA may start floating dUring any TC depending dn when Internal 80286 bus arbiter deCides to release bus to
external HOLD. The float starts In ",2 of TC
3.
i3RE and LOCK may start floating after the end of any TC depending on when mternal 80286 bus arbiter deCides to release bus to external
HOLD. The float starts In ",1 of TC
4. The minimum HOLD
5 The earhest HOLD
6. The minimum HOLD
to HLDA
time IS shown. Maximum IS one TH longer
time IS shown It Will always allow a subsequent memory cycle If pending IS shown
to HLDA
In/errupts, Walts, Lock, etc.)
time IS shown. Maximum IS a funcllon of the Instrucllon, type of bus cycle and other machine status (I e ,
7 Asynchronous ready allows termination of the cycle SynChronous ready does not signal ready
IS Ignored after ready IS signaled via the asynchronous "'put
In
thiS example Synchronous r~ady state
Figure 29. Multibus Write Terminated by Asynchronous Ready with Bus Hold
4-31
AFN-02060D
IAPX 286/10
Processor Extension Transfers
Local Bus Usage Priorities
The processor extension interface uses I/O port
addresses 00F8(H), OOFA(H), and OOFC(H) which are
part of the 1/0 port address range reserved by Intel.
An ESC instruction with Machine Status Word bits
EM = 0 and TS = 0 will perform 1/0 bus operations to
.one or more of these 1/0 port addresses independent
of the value of 10PL and CPL.
ESC instructions with memory references enable the
CPU to accept PEREa inputs for processor extension
operand transfers. The CPU will determine the operand
starting address and read/write status of the instruction.
For each operand transfer, two or three bus operations
are performed, one word transfer with I/O port address
OOFA(H) and one or two bus operations with memory.
Three bus operations are required for each word operand aligned on an odd byte address.
The 80286 local bus is shared among several internal
units and external HOLD requests. In case of simUltaneous requests', their relative priorities are:
(Highest) Any transfers which assert mcK either ex,
plicitly (via the LOCK instruction prefix) or
implicitly (I.e. segment descriptor access,
interrupt acknowledge sequence, or an
XCHG with memory).
.
The second of the two byte bus operations
required for an odd aligned word operand.
The second or third cycle of a processor
extension data transfer.
Local bus request via HOLD input.
Processor extension data operand transfer
via PEREa input.
Data transfer performed by EU as part of an
instruction.
Interrupt Acknowledge Sequence
Figure 30 illustrates an interrupt acknowledge sequence
performed by the 80286 in response to an INTR input.
An interrupt acknowledge sequence consists of two
INTA bus operations. The first allows a master 8259A
Programmable Interrupt Controller (PIC) to determine
which if any of its slaves should return the interrupt
vector. An eight bit vector is read on 00-07 of the
80286 during the second INTA bus operation to select
. an interrupt handler routine from the interrupt table. '
(Lowest)
The Master Cascade Enable (MCE) signal of the 82288
is used to enable the cascade address drivers, during
INTA bus operations (See Figure 30), onto the local address bus for distribution to slave interrupt controllers via
the system address bus. The 80286 emits the mcK
signal (active LOW) during Ts of the first INTA bus operation. A local bus "hold" request will not be honored until
the end of the second INTA bus operation.
An instruction prefetch request from BU. The
EU will inhibit prefetching two processor
clocks in advance of any data transfers to
minimize waiting by EU for a prefetch to finish.
Halt or Shutdown Cycles
The 80286 externally indicates halt or shutdown conditions as a bus operation. These conditions occur due to
a HLT instruction or multiple protection exceptions while
attempting to execute one Instruction. A halt or shut.
down bus operation is signalled when ST, SO and COOt
rnTA are LOW and MIID is HIGH. Al HIGH indicates
halt, and Al LOW indicates shutdown. The 82288 bus
controller does not issue ALE, nor is READY required to
terminate a halt or shutdown bus operation.
Three idle processor clocks are provided by the 80286
between INTA bus operations to allow for the minimum
INTA to INTA time and CAS (cascade address) out delay
of the 8259A. The second INTA bus operation must always have at least one extra Testate added via logiC
controlling READY. A23-Ao are in 3-state OFF until after
the first Te state of the second INTA bus operation. This
prevents bus contention between the cascade address
drivers and CPU address drivers. The extra Testate allows time for the 80286 to resume driving the address
lines for subsequent bus operations.
During halt or shutdown, the 80286 may service PEREa
or HOLD requests. A processor extension segment
overrun exception during shutdown will inhibit further
service of PEREa. Either NMI or RESET will force the
80286 out of either halt or shutdown. An INTR, if interrupts are enabled, or a processor extension segment
overrun exception will also force the 80286 out of halt.
4-32
AFN-020600
IAPX 286/10
BUS CYCLE TYPE
I
~
Tc
I
I
4-----INTA CYCLE
T8
Tc
_ I ~
~
I ~
1
~
I1~
~
Tc
I
~
,
~
TI
t
~
I
To
~
J
~
ClK
Mlill, CODIINTA
I!RE
015 -
DO
»»»>>>>- ------ ---- -<. . .__
DO_N_'T_CA_RE_-J>- -
w~~V~~1E} -
------
- - -
-- -- -
-
-c:::=
0 -- --- -- - -- --- - - --- - - {VECTOR}- - (SEE NOTE 1,)
-
ON D7·DO
(SEE NOTE 2.)
REAllY
S%\\\ mZ7IOVO/l \\\\\\ mmliOlOlOllOlVOOlmmlW \\\\\\ nnm
NOT READY
I
(SEE NOTE 3.)
NOT READY
READY
I
r-
\
INTA
\
MCE
1\
1\
ALE
n
n
DTIIi
DEN
/
I
\
/
\
/
\
READY
L-
NOTES:
1. Data is ignored.
2. First INTA cycle should have at least one wait state inserted to meet 8259A minimum INTA pulse width.
3. Second INTA cycle must have at least one wait state inserted since the CPU will not drive A23
TCstate.
-
Ao, BHE, and LOCK until 'after the first
t
The CPU imposed one/clock delay prevents bus cQntention between cascade address buffer being disabled by MCE and address
outputs.
Without the wait state, the 80286 address will not be valid for a memorr cycle started immediately after the second INTA cycle. The
8259A also requires one wait state for minimum INTA pulse width.
"
,
4. LOCK is active for the first INTA cycle to preventthe 82289 from releasIng the bus between INTAcycles in a multi·master system.
5. A23 -
Ao eXi,ts 3·state OFF during 4>2 of the second Tc in the INTA cycle.
Figure 30. Interrupt Acknowledge Sequence
AFN·02060D
IAPX286/10
Vee
VCC
91011
rDfl
X,
±S%
X,
::I~
READV
eLK
PCLK
EFI
FIC
4-
-
-
~_
VCC
~iC
~
.~
N
~~ 1-'-----1H--..J
RES
REseT
I
r--IH-"t-..J
TI
:
SYNC READV ENABLE _
SRDV
SADVEN
ASVNC READV _
ENABLE _
AADV
AROVEN
Vee
J
I'
20Kn
~I
I
82284
I I
CLOCK
GENERATOR::
.... eLK
CODIINTA
READY
t-:-- 51
A23_ Ao
I
I
RESET
r--
,-j- NMI
so
I
I
I , ; ............
I
I
I
"
I I
r,.I -["" ----+++-...1-'1I
I
L--~~--t--tl-:--
'
I
I
I
I
I
I
I
I
I
I
I,
I I
I
I_
'
r - - - 1-'-,
I
I
MilO
LOCK
r - - _ _ _ _ _ .J
I
r---
t _J
,r-
I I
I,
I
f----+ .......
f----+-+-..-----.
1
I r-------J
t
M8
MilO
I I
RESET
MADe r - - - - - - - - - -. . MEMORV READ
MWTe r - - - - - - - - - -. . MEMORY WRITE
IOAC r---~------.lfOREAD
CMDlY
lowe
-----.lfOWRITE
INTA
INTERRUPT ACKNOWLEDGE
ALE
SO
MCE
S1
~----,
DEN
rREADY
- - ~
t- .... ADVANCED,MEMORY
elK
DTIR
- - ~
DECODE t- .... AND 110 CHIP SELECTS
I r
82288 BUS
_
r - .1'..,) IOPTIONALI,
..J I
CONTROLLER
~
'IL _ _ _ _ .II
.JI ,.."
I
AEN
I
I
I
II
...I
I
I
r
I
I,
I
I
-
-
..J
I--.
I
I
,L.
I
PROCESSOR
EXTENSION
IOPTIONALI
,
I
I
I
I
~ ADDRESS BUS
I
f-''--'-.........-'-.L.-L-'-.L-.-"'\.
O~:~!3
~
LATCH
,
I
~~~~R'
I
#=:
!.L +
-=
0,,-00
I
J'
!.- -t.. -
- -
,.. ... JI
-
l
CAS...,
INTR I - - ' ' - - + H - + - + - - - - - - I I N T ,
PEACK'
PEREa
CAPt-;1
80286
CPU
,----
____________
I
L ~ ....J
BHE
8USV
,
80287
I r
I I
I I
I
._U_:_:_UJ_UJ_ -,
I
-"
r-
HOLD
I rI
~
I
Ao
es
I-I-- CHIP SELECT
INTA
'------+tWA
'----,----~AD
, - - - - - - \ SPIEN
~Do-~~59A
INTERRUPT
CONTROLLER
---
---:: oe
, .,
-
8286
8287
TRANSCEIVER
~DATA
f"r-YBUS
'-------~T
Figure 31. Basic iAPX 286 System Configuration
SYSTEM CONFIGURATIONS
The versatile bus structure of the iAPX 286 microsystern, with a full complement of support chips, allows flexible configuration of a wide range of sy!\tems. The basic
configuration, shown in Figure 31, is similar to an iAPX
86 maximum mode system. It includes the CPU plus an
8259A interrupt controller, 82284 clock generator, and
the 82288 Bus Controller. The iAPX 86 latches (8282
and 8283) and transceivers (8286 and 8287) may be
used in an iAPX 286 microsystem.
As indicated by the dashed lines in Figure 31 , the ability
to add processor extensions is an integral feature of iAPX
286 microsystems. The processor extension interface
allows external hardware' to perform special functions
and transfer data concurrent with CPU execution of other
instructions. Full system integrity is maintained because
the 80286 supervises all data transfers and instruction
execution for the processor extension.
The iAPX 286/20 numeric data processor which in.cludes the 80287 numeric processor extension (NPX)
4-34
uses this interface. The iAPX 286/20 has alf the instructions and data types of an iAPX 86/20 or iAPX 88/20.
ThEl80287 NPX can perform numeric calculations and
data transfers concurrently with CPU program execution. Numerics code and data have the same integrity as
all other information protected by the iAPX 286 protection mechanism.
The 80286 can overlap c.hip select decoding and address propagation during the data transfer ·for the previous bus operation. This information is latched into the
8282/3's by ALE during the middle of a Ts cycle. The
latched chip select and address information· remains
stable during the bus operation while the next cycles
address is being decoded and propagated into the system. Decode logic can be Implemented with a high speed
bipolar PROM.
The optional decode logic shown in Figure 31 takes advantage of the overlap between address and data of the
80286 bus cycle to generate advanced memory and 10select signals. This minimizes system performance
AFN-02060D
IAPX 286/10
2Ol(r"-++--l>--+f::T
910n
±
.%
~
I
---~
~
RESB
~~~~YS
CROLet(
SO
51
=== )
MULTIBUS
aus ARBITRATION
BUSY 4-------+
'-----+--t-t-.~READY
~
B~~~
aREO BPRO ~
BfflN _ _
CBRO -
ell(
LOCK_
M10 t--
r+-II-t-H-lAEN
82289 SLOCK
t-- f-
BUS ARBITER
V"
AE"
M.
MRDe
MWTC
10RC
lowe
INTA
so
ALE
-
Figure 32. Multibus System Bus Interface
degradation caused by address propogation and decode delays. In addition to selecting memory and 110,
the advanced selects may be used with configurations
supporting local and system buses to enable the appropriate bus interface for each bus cycle. The COD/Tf\!TA
and MOO signals are applied to the decode logic to distinguish betWeen interrupt, 110, code and data bus cycles.
By adding the 82289 bus arbiter chip the 80286 provides
a Multibus system bus interface as shown in Figure 32.
The ALE output of the 82288 for the Multibus bus is
connected to its CMDlY input to delay the start of c.ommands one system ClK as required to meet Multibus
address and write data setup times. This arrangement
will add at least one extra Testate to each bus operation
which uses the Multibus.
A second 82288 bus controller and additional latches
and transceivers could be added to the local bus of Figure 32. This configuration allows tlie 80286 to support
an on-board bus for local memory and peripherals, and
the Multibus for system bus interfacing.
4-35
AFN·02060D
IAPX286/10
8287
DATA D1. -
Do
DRAM
2118.2184
eo_
CPU
MULTlBUS SELECT
I elK
r.--r-XACK
STATUS iiO. ii. M/iO
1lU..T18US
COIIMAJiI)
(IIRDC. MWTC)
DECODE
LOCAL
SELECT L.-':-_-{ I-+---:SELE=CT~
'--_ _ _ _ ADiiiiESS
ADDRESS An -
Ao. BHE. LOCK
Figure 33. IAPX 286 System Configuration with Dual-Ported Memory
Figure 33 shows the addition of dual ported dynamic
memory between the Multibus system bus and the iAPX
286 local bus. The dual port interface is provided by the
8207 Dual Port DRAM Controller. The 8207 runs synchronously with the CPU to maximize throughput for local memory references. It also· arbitrates between
r~quests from the local and system buses and performs
functions such as refresh, initialization of RAM, and read!
modifylwrite cycles. The 8207 combined with the 8206
Error Checking and Correction memory controller provide for single bit error correction. The dual-ported
memory can be combined with a standard Multibus system bus interface to maximize performance and protection in multiprocessor system configurations.
'lible 16. 80286 Systems Recommended Pull up Resistor Values
80286 Pin and Name
Purpose
Pullup Value
4-~
5-80
6-PEACK
53 ...:.ERRC.5R
20KO ± 10%
Pull 50, ~, and PEACK inactive during 80286 hold perlo~s
20KO ± 10%
Pull ERFIDR and BO§Y inactive when 80287 not p~sent
(or temporarily removed from socket)
"
54-BO§Y
63-READY
9100 ± 5%
Pull READY inactive wilhin raquired minimum time (eL
IR:5 7mA)
4-36
= 150pF,
AFN-02060D
IAPX 286/10
PACKAGE
The 80286 is packaged in a 68-pin, leadless JEDEC
type A hermetic leadless chip carrier. Figure 34 illustrates the package, and Figure 2 shows the pinout.
PIN NO. 18
[
"~_
' _ _......j"'--PIN N01 MARK
130
(3.30)
18CHES
(MIWMElERS)
(24.38)
Figure 34. JEDEC Type A Package
ABSOLUTE MAXIMUM RATINGS*
"NOTICE: Stresses above those listed under "Absolute Max·
imum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the de·
vice at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to. absolute maximum rating conditions for ex·
tended periods may affect device reliability.
Ambient Temperature Under Bias .......... O°C to 700C
StorageTemperatur!il·.........•... -65°Cto + 150°C
Voltage on Any Pin with
Respect to Ground . . . . . . . . . . . . . . .. -1.0 to +7V
Power Dissipation .... ;'................. 3.6 Watt
D.C. CHARACTERISTICS
(TA = oDe to 55°e. Vee = 5V. ± 5%)
4 MHz
-4
$yin
Vll
VIH
Vile
VIHC
VOL
VOH
III
ILO
lee
CCLK .
CIN
Co
Parameter
Input LOW Voltage
Input HIGH ,Voltage
ClK Input lOW Voltage
CLK Input HIGH Voltage
Output lOW Voltage
Output HIGH Voltage
Input leakage Current
Output leakage Current.
Supply Current (turn on, O°C)
ClK Input CapaCitance
Other Input Capaqitance
InpuUOulput Capacitance
Min
-.5
2.0
-.5
3.8
-4
Max
.8
Vr.c+ .5
.6
Vcc +·5
.45
2.4
+-10
+-10
600
12
10
20
6 MHz
-6
-6
Min
Max
-.5
.8
2.0 Vrr. +.5
-.5
.6
3.8 Vcc+~5
.45
'2.4
+-10
+-10
600
12
10
20
8 MHz
Min
-.5
2.0
-.5
3.8
Max
.8
Vrr. +.5
.6
Vrr.+ .5
.45
2.4
+-10
+-10
600
12
10
, 20
Unit Test Condition
V
V
V
V
V
V
IOl =2.0mA
IOH = -4oo"A
"A OVSVIN IOPL.
The IF field of the flag word is not updated if
CPL > IOPL. The IOPL field is updated only if
CPL = O.
Any violation of privilege rules as applied to the selector operand do not cause a protection exception;
rather, the instruction does not return a result and
the zero flag is cleared.
If the starting address of the memory operand violates a segment limit, or an invalid acc,ess is attempted, a general protection exception (13) will
occur before the ESC instruction is executed. A stack
segment overrun exception (12) will occur if the stack
limit is violated by the operand's starting address. If
a segment limit is violated during an attempted data
transfer then a processor extension segment overrun exception (9) occurs.
18. The destination of an INT, JMP, CALL, RET or
IRET instruction must be in the defined limit of
a code segment or a general protection exception (13) will occur.
10. For segment load operations, the CPL, RPL, and
OPL must agree with privilege rules to avoid an exception. The segment must be present to avoid a
4-43
AFN-020600
£1WMCI OOOrF@OOli'iJA1(I1COO
, lAPX ~86/ 1()
"],1 1
80286 INSTRUCTION SET SUMMARY
CUlCKCDUNT
Real
FUNCTION
=~':~R
Add....
Mo••
FORMAT
rim
rim
modOOO rim
data
dsta
datalfw=1
ReQlster/memory to register
11 00 0 1 00 w 'mod!:!i
11 00 0 1 01 w mod reg
Immedlsta 10 regl,ster/memory
11 100011 w
, Immedlatelo,register
RnI
MIl....
Add....
Modi
11 01 1 w reg
I
datalfw=1
I
,
'='
Add....
' IIIdI
lIiMIt '
,
ReQisterto ReQlsterlMemory
I'nIIIIIId
VI_I
2,3-
2)-
2
9
2,5-
2,5-
2
9
2,3-
2,3-
2
9
9
2
2
addr-hlgh '
I
I
5
5
2
addr-hlgh
I
3
2
9
2
9,10,11
2
9
9
Memory 10 accumulator
11 0'1 0 000 w
:"addr-Iow
Accumulator 10 memory
11 01 000 1 w
addr-Iow
ReQister/memory to segment register
'II 0001 11 0
mod 0 reg rim
2,5-
3
17,19-
Segmenl register to registerlmemory
11 000 1 1 0 0
mod 0 reg rim
2,3-
2,3-
PUSH = Po...:
Memory
'11 1 1 1 1 11 1
5-
5-
2
RegIster
10 101 0
3
,3
2
9
3
3
2
9
5-
5-
2
9
5
5
2
9
5
20
2
9,10,11
3,5-
3,5-
2,7
7,9
3
3
5
5
14
5
5
14
Segmenl register
I
pop = Pop:
Memory
11 0001 1 1 1
I
RegIster
10 101 1
I
Segment regIster
XCHG = ExchIftIe:
Register/memory with register
RegISter wrth accumulator
'IN = Input lroll!:
Fixed port
variable port
modll0 rim
I
reg I
(0 00, reg liii1
!!I!
,10 0 0 reg 1 1 1
I'
11000 01'1 wi
11 001 0 reg
modOOO rim I
(reg.,OI)
mod reg
I
11 110010 wi
11 1101 lOw
rim I
I
port
I
=
OUT Output to:
FIXed port
11 110011 wi
3
3
14
vartable port
11 1101 1 1 wi
3
3
14
XlAT = Trenslate byte 10 AL
11 101 01 1 1
I
5
9
LEA = Load EA to register
11 0001 1 0 1
mod reg
rim
5
3-
LDS=i.oad polnterlo OS
11 1 0 0 0 1 0 1
mod reg
rim I
(mod., 11)
7-
21-
2
9,10,11
LES = Load poInter 10 ES
1110 00100
mod reg
rim
I
(mod., 11)
7-
21-
2
9,10,11
lAHF = Load AH with flags
11 001 1 1 1 1
2
2
SAHF = Store AH Into flags
11 00 1 1 1 1 0
2
2
PUSHF = Posh flags
11 001 1 1 0 0
3
3
2
9
POPF = Pop flags
11 0 (11 1 1 0 1
5
5
2,4
9,15
I
port
I
3-
Shaded areas indicate instructions not aval able in iAPX 86, 88 microsystems.
4-44
AFN-02060D I
infer
£lWAOO©~ OOOIF@~IMI£"ii'O@OO
IAPX 286/10
80286 INSTRUCTION SET SUMMARY
Raal
Addreu
Moda
FUNCTION
FORMAT
ADD = Add:
Reglmemory willl regi&ter to eilller
10 000 0 0 d wi
Immediate to regi&ter/memory
l' 0 0 0 0 0 s w
Immediate to accumulator
10000010wl
ADC = Add wl\ll ceny:
Reglmemory with register to either
10 00 1 00 d wi
I
mod reg
rim
mod OM rim
data
data
dataffw=1
mod reg
rim
Immediate to accumulator
l' 000 0 0 s wi modOl0 rim
data
10 00 1 0 lOw
INC = Incremant:
Registerlmemory
l'
Immediate to reglsterlmemory
I
data
111111 wi
10 1000 reg
SU8 = Subtree!:
Reglmemory and register to eilller
10 01 0 1 0 d wi
mod reg
madl01
rim
rim
data
Immediate from accumulator
1000110d w i
mod reg
Immediate from registerlmemory
l' OOOOOs wi
modOll rim
data
Immediate from accumulator
10 00 1 1 lOw
data
dataifw=1
I
I
l'
data
modOOl rim
CMP = Compare:
Register/memory with register
1001 1 101 wi
mod reg
Register with registerlmemory
10011100wl
mod reg
Immediate with registerlmemory
l'
modlll rim
data
Immediate with accumulator
00000 s wi
10 01 1 1 lOw
data
datalfw=1
NEG = Change sign
l'
modOll
AAS = ASCII adjust for subtract
MUL= Multiply (unsigned)'
Register-Byte
Register-Word
Memory-Byte
Memory-Word
IMUL = Integer muttiply (Signed):
Register-Byte
Register-Word
Memory-Byte
Memory-Word
DIY = Divide (unsigned):
Register-Byte
Register-Word
Memory-Byte
Memory-Word
3
2,7·
2,7·
3,7·
3,7·
2,7·
2,7·
2.7.
2,7·
datailsw=OI
3,7"
3,7"
datalfsw=OI
2,r
3,7·
3.7"
rim
111111 wi
10 1001 reg
PAS = Decimal adjust for subtract
3
9
2
dataifw=1
Register
IIAA = Decimal adjust,for add
2,7"
3,7·
I
S88 = Subtree! wllb borrow:
Reglmemory and register to erther
AM = ASCII adlustfor add
2,7·
3,7·
dataifw=1
l' 00000 s wi
10 01 0 1 lOw
DEC = Decrement: .
Registerlmemory
data ils w= 01
modOOO rim
Register
Immediate from registerlmemory
dataifsw=OI
ProIICI8d
Vlrlual
Addrea
Mode
3
I
I
11 1 011 wi
10 01 1 0 1 1 1
I
10 01 001 1 '1
10 01 1 1 1 1 1 I
10 01 0 1 1 1 1 I
l' 11 1 011 wi
l' 11 1 011 wi
2,r·
rim
rim
datalfsw=OI
rim
2,r
2,7·
2
2
2,6·
2,6·
2,r
3,S·
3,S·
2,7"
3
2
r-
13
21
16·
24·
13
21
IS·
24·
13
21
16·
24·
13
21
IS·
24·
14
22
lr
25'
14
22
17·
25'
modl00 rim
madl01 rim
modl10 rim
6
6
2,S
2,S
S
6
S,9
,6,9
Shaded areas indicate instructions not available in iAPX 86, 88 microsystems,
4-45
AFN-020600
..
.\,
IAPX 286/10
SETSUMMARYI"~'nTII~IIAnl
80286
FUNCTION
Real
Add,.sa
Mode
FORMAT
Real
Add,.sa
Mode
Protected
VlrlQal
Add,.sa
Mode'
6
6
2,6
2,6
6
6
6,9
6,9
(Conllnuedl:
I
IDIV ~ Integer divide (signedl:
Register-Byte
Register-Word
Memory-Byte
Memory-Word
AAM ~ASC!I adlust/or multiply
11 1 1 1 0 1 1 w
11 101 01 0 0
I 00001
AAD =ASCII adlustfor divide
111 0 1 ()'1 0 1
CBW = Convert byte to word
11001110001
CWD = Convert word to double word
11 00 1 1 00 1
LOGIC
ShlftJRlllate InllrucHona:
RegisterlMemory by 1
RegisterlMemory by CL
mod 111
0 1 0I
17
25
2028IS
17
25
2028IS
I 0 0 0 0 1 0 1 0I
14
14
2
2
I
'11 101 000 w I
mod
I
mod
11 101 001 w
rim
m rim
m rim
2,7-
2,7-
5+n,8+n'
5+0,8+n*
m Instruction
o00
ROL
1
ROR
o 10
RCL
o11
RCR
1 00 SHUSAL
1 01
SHR
111
SAR
o0
A/tD=And:
Reglmemory and register to either
2,r
2,7-
Immediate to reglster/mamory
3,7-
3.7'
Immediate to accumulator
3
TEST =And lunction to flags, no result
Reglsterlmemory and register
11000010wl
I
mod reg
data
data
datalfw~l
11 11 1 011 w
Immediate data and accumulator
11010100wl
DR = Or:
Reg/memory and register to either
loaool0dwl
mod reg
Iminedlate to reglsterlmemory
11000000wl
mod 00 1 rim
data
data
datalfw~l
Immediate to accumulator
10000110wl
1001100 dw i
mod reg rim
Immediate to reglsterlmemory
11000000wl
modl10 rim
Immediate to accumulator
1001fOl0wl
data
NOT = Invert reglsterlmemory
11 1 1 1 01 1 wi
modOl0 rim
STRING MANIPULATION:
MOYS = Move bytelword
11 010010wl
CMPS ~ Compare byteJword
11 01 00 1 1 wi
11 0101 11 wi
LODS"; Load byteJwd to AUAX
11 01 0 1 lOw
2,S-
3,S-
3,6-
2,7<
2,r
dataifw~l
3,7<
3,7<
3
3
rim
XOR = Exclusive or:
Reglmemory and register to either
SCAS = Scan byte/word
2,Sdataifw=l
rim
modOOO rim
Immediate data and registerlmemory
dataifw~l
data
dataifw~
1
2,7-
2,7<
3,7<
3,7<
3
3
2,7<
2,r
I
Shaded ar~as indicate instr~ctions not available in iAPX 86,88 microsystems,
4-46,
AFN-02060D
IAPX 286/10
80286 INSTRUCTION SET SUMMARY
Pnltected
Virtual
Addren
Mode
Repeated by count in ex
MOVS ~ Move string
5+4n
5+4n
2
9
eMPS ~ Compare stnng
5+9n
5+9n
2,8
8,9
SCAS ~ Scan string
5+8n
5+8n
2,8
8,9
LODS ~ Load string
5+4n
5+4n
2,8
FORMAT
Real
Address
Mode
Protected
VlrIuIl
Addre..
Modi
Real
Address
Mode
FUNCTIIIN
CONTROL TRANSFER
=
CALL Call:
Direct within segment
ReQlster/memoty
indirect within segment
D!rect intersegment
11 1 1 a 1 a a a
11 111111
dlsp-Iow
dlsp-high
modal a rim
11 a a 1 1 a 1
segment offset
13+m
2
18
2,8
8,9,18
26+m
11,12,18
41+m
82+m
86+4xtm
177tm
182+m
8,11,12,18
8,11,12.18
8,11,12,18
8,11,12,18
8,11,12,18
29+m'
8,9,11,12,18
44+m"
83+m'
9O+4x+m'
180+m'
185+m'
8,9,11,12,18
8,9,11,l2,18
8,9,11,12,18
8,9,11,12,18
8,9,11,12,18
segment selector
Protected Mode Only (Direct inllnegment):
Via call gate to same privilege level
Via call gate to different privilege level, no parameters
Via call gate to different privilege level, x parameters
ViaTSS
Via task gate
Indirect intersegment
modOll rim
11 111111
(mod" 11)
16+m
Pro\8cted Mode Only (Indirect Intenegment):
Via call gate to same privilege level
Via call gate to different privilege level, no parameters _
Via cal.1 gate to different privilege level, x parameters
ViaTSS
Via task gate
=
JMP Unconditional jump:
Short/long
Direct within segment
11 1 1 a 1 a 1 1
11 1 1 a 1 a a 1
dlsp-Iow
dlsp-Iow
mod 100 rim
Reglsterlmemory indirect within segment 11 111111
Direct Intersegment
11 1 1 a 1 a 1 a
Pnlllcted Mode Only (Direct intenegment):
Via call gate to same pnvilege level
ViaTSS
Via task gate
Indirect Intersegment
disp-high
I
I
7+»>
18
7+m
7+m
18
7+m,ll+m' 7+m,11+m'
segment offset
9,18
23+m
11,12,18
38+m
175+m
t80+m
8,11,12,18
8,11,12,18
8,11,12,18
2i+m'
8,9,11,12,18
41+m'
178+m'
183+m'
8,9,11,1 18
8,9,11
8,9,11,
11+m
II+m
8,9,18
II+m
l1+m
8,9,18
15+m
25+m
8,9,11,12,18
II+m
segment selector
modl01 rim
11 111111
7+m
(~od"
11)
15+m'
Pnlllcted Mode Only (Indirect Intenegment):
Via call.oate to same privilege level
ViaTSS
Via task gate
=
RET Retum 110m CALL:
Within segment
Intersegment
11 1 a a a a 1 11
11 1 a a 0 0 1 01
11 100 1 01 11
Intersegment adding Immediate to SP
11 1 a 0 1 0 1 a
Within seg adding Immed to SP
I
data-low
data-low
data-high
data-high
Protected Mode Only (RET):
To different
level
IS+m
8,9,11,12,18
55+m
9,11,12,18
Shaded areas indicate instructions not available in iAPX 86,88 microsystems,
4-47
AFN-02060D
Her·
'II\PX 286/10.
£@W£OO©~
DOOIF(Q)OOU1i"IJ(9)OO
80286 INSTRUCTION SET SUMMARY
Add.....
FUNCTION
FORMAT
JElJZ =Jump 00 equaVlero
10 1 1 1 0 1 0 0
dlsp
7+mor3 7+mor3
18
JUJNGE =Jump on lesS/llotgrearer or equ~
10 1 1 1 1 1 0 0
disp
7+mor3 7+mor3
18
disp
7+mor3 7+mor3
18
disp
7+mor3 7+mor3
18
disp
7+mor3 7+mor3
18
18
Mode
JB/JNAE =Jumpon bitowmotabove orequ~
I
I
10 1 1 1 1 1 1 0 I
10 1 1 1 0 0 1 0 I
JBElJNA =Jump on beloworequavnotabove
10 1 1 1 0 1 1 0
JP/JPE =Jurnpon panty/parityeven
10 1 1 1 1 0 1 0
disp
7+mor3 7+mor3
JO =Jump oooverflow
101110000
disp
7+mor3 7+mor3
18
JS =Jump 00 s~n
10 1 1 1 1 00 0
disp
7+mo,3 7+mor3
18
JLElJNG =Jump on less orequaVllotgreater
I
JNElJNZ =Jump on notequallnotztrO
10 1 1 1 0 1 0 1
disp
7+mor3 7+mor3
18
JNUJGE =Jumpon not ~sslgreaterorequ~
10 1 1 1 1 1 0 1
disp
7+mor3 7+mor3
18
JNLElJG =Jump onnotless or equaligreater
10 1 1 1 1 1 1 1
disp
7+mor3 7+mor3
18
JNB/JAE =Jumpon not below/aboiloreq~
10 1 1 1 0 0 1
disp
7+mor3 7+mor3
18
JNBElJA =Jumpoo not below orequali!bove
10 1 1 1 0 1 1
disp
7+mor3 7+mor3
18
JNPIJPO =Jump 00 not pal/par odd
10 1 1 1 1 01 1
disp
7+mor3 7+mor3
18
JNO =Jump onnotove~ow
10 1 1 1 0 00 1
disp
7+mor3 7+morS
18
JNS =Jumpon not sign
10 1 1 1 1 00 1
disp
7+morS 7+morS
18
LOOP =loop ex times
11 1 1 0001 0
11 1 1 0 0 0 0 1
11 1100000
disp
8+mor4 8+mor4
18
disp
8+mor4 8+mor4
18
disp
8+mor4' 8+mor4
18
11 11 0001 1
disp
8+mor4 8+mor4
18
LOOPZlLOOPE =loopwhHezeroiequal
LOOPNZlLOOPNE =loopwhi. not ztrOIeq~
, JCXZ =Jump on CXzero
INT = Interrupt:
Type specified
TypeS
INTO =Interrupt on overflow
11 1 0 0 1 1 0 1
I
I
I
type
11 1 0 0 1 1 0 0
11 1 POll 1 01
2,7,8
23+m
2,7,8
24+mor3
13Hno
IntIIru~1
Protected Mode Only:
Via interrupt or trap gate to same pnvllege level
Via interrupt or trap gate to fit different privilege level
Via Task Gate
II\ET =Interrupt return
23+m
2,6,8
1311no
Interrupti
40+m
78+m
167+m
11 1 0 0 1 1 1 11
17+m
Protected Mode Only:
To different privilege level
To different task INT =1)
SI+m
55+m
169+m
7,8,11,12,18
7,8,11,12,18
7,8,11,12,18
2,4
8,9,11,12,15,18
8,9,11,12,15,18
8,9,11,12,18
Shaded areas indicate instructions not available in iAPX 86, 88 microsystems.
4...48
AFN-02060D
IAPX 286/10
80286 INSTRUCTION
FUNCTION
PROCESSOR CONTROL
CLC = Clear carlY
CMC = Complement carlY
I
STC=SetcarlY
CLD = Clear direction
STD = Set direction
CU = Clear interrupt
sn = Set interrupt
HLT=Halt
Real
Address
Mode
FORMAT
Protected
Virtual
Address
Mode
11 1 1 1 1 00 0
11 1 1 1 010 1
11 1 1 1 1 00 1
11 1 1 1 1 1 0 0
11 1 1 1 1 1 0 1
11 1 1 1 1 01 0
14
14
11 1 1 1 1 01 1
1110 10 0
13
WAIT =Walt
LOCK = Bus lock prefiX
14
ESC = Processor Extension Escape
9-20'
9-20'
5,8
8,17
11.13
1I
9,13,
, ,lI
$;11,1& ,
•
9.11.13
$
, ..13 '
,9
, 1M'l.1$
9'.11,1$
8,9
9.11,16
.,1M$.
Shaded areas indicate instructions not available in iAPX 86, 88 microsystems.
4-49
AFN-02060D
W ...J~ ..
• '''ttl , ~,'
IAPX.286/10 ,
Footnotes
The effective Address (EA) of the memory operand is
computed according to the mod and rIm fields:
REG is assigned according to the following table:
16-Blt(w = 1)
000 AX
001 CX
010 OX
011 BX
100 SP
101 BP
110 SI
111 01
if mod = 11 then rIm is treated as a REG field
if mod = 00 then OISP = 0·, disp-Iow and disp-high
are absent
.;
if mod = 01 'then OISP = disp-Iow sign-extended to
16-bits, disp-high is ab~ent
if mod = 10thenOlSP = disp-high:disp-Iow
if rIm = 000 then !=A = (BX) + (SI) + OISP
if rIm = 001 then EA = (BX) + (01) + OISP
if rIm = 010 then EA = (BP) + (SI) + OISP
if rIm = 011 then EA = (BP) + (01) + OISP
if rIm = 100 then EA = (SI) + OISP
itrlm = 101 then EA = (01) + OISP
if rIm = 110 then EA = (BP) + OISp·
if rIm = 111 then EA = (BX) + OISP
8-Blt(w = 0)
000 AL
001 CL
0100L
011 BL
100 AH
101 CH
110 OH
111 BH
The physical addresses of all operands addressed by
the BP register are computed using the SS segment
register. The physical addresses of the destination operands of the string primitive operations (those ad- .
dressed by the 01 register) are computed using the ES
segment, which may not be overridden.
OISP follows 2nd byte of instruction (before data if
required)
*exceplifmod
= 00 and rim = 110thenEA = disp-hlgh:disp-Iow:
SEGMENT OVERRIDE PREFIX
100 1 reg 1 1 01
reg is assigned according to the following:
reg
Segment
Register
00
01
10
11
ES
CS
SS
OS
4-50·
AFN-Q2060D
IAPX 286/10
QUIDEIOSS
3 PLCS
INDEX
J
-i~~~I-_-I-_----+'1'+I-------~SOCKET
PC BOARD PATTERN
~
ORIENTATION PIN .....
I
'-
I
'G.
I
ALUMINUM LID
(HEATSINK PROVISIONS OPTIONAL) ,
\
OPEN
Figure 36. Textool 68 Lead Chip Car,rier Socket
4-51
AFN-02060D
*ri+...:.r
I.~'~'
80287
80-Bit HMOS
NUMERIC PROCESSOR EXTENSION
80287-3
• High Performance 80-Blt Internal
Architecture
-
• Implements Proposed IEEJE Floating
Point Standard 754
• Protected, ,Mode Operation Completely
Conforms ,to the IAPX '2,a6 Memory
Manage,ment and Protection
Mechanisms '
• ExpandslAPX 286/10 Datatypes to
Include 32-, 64-, 80-Bit Floating Point,
32-, 64-Blt Integers and 18-Di91t BCD
Operands
• Dlrectiy ExtendslAPX 286/10 Instruction
Set to TrigonometriC, Logarithmic,
Exponential and Arithmetic Instructions
for All Datatypes
• Object Code Compatible with 8087
• Built-in Exception, Handling
)
• Operates iri Both Real and Protected
'
Mode IAPX 286 Systems
• 8x80-BU, Individually Addressable,
Numeric Register Stack
• Available In EXPRESS-Standard
Temperature Range
Th~ Inte~ 80287 is a high performance numerics processor extension that extends the iAPX 286/10 '
architecture with floating point, extended integer and BCD data types. The iAPX,286/20 computing system
(80286 with 80287:> fully conforms to the proposed IEEE Floating Point Standard. Using a numerics
oriented architecture, the 80287 adds over fifty mnemonics to the iAPX 286/20 instruction set, making the
iAPX 286/20 a complete sQlution for high performance numeric processing. The 80287 is implemented in
N-channel, depletion load, silicon gate technology (HMOS) and packaged in a 40-pin ceramic package.
The iAPX 286/20 is object code compatible with the iAPX 86/20 and iAPX 88/20.
CKM
BUS INTERFACE UNIT
NUMERIC exEcUTION UNIT
r-~---T~-------------~
'I
FAACT~~~
I
N.C.
j
I
I
013
012
Vee
Vss
MiCROCODE
1-------1:::
I
STATUS
.L
I
____ --;- L _____-_
iiJil
H_
CLK
CMD1
D11
\Iss
D10
CMDO
N.C.
Dt
iiPiiii
iiPiiii
De
IRROR
07
iiiiY
De
PlMQ
Dt
1M
DO
os
I
~
~BI~ _-~
HLOA
CLK2N
PUCK
R_T
____
.J
NOTE:
N.C. PINS MUST NOT BE CONNECTED.
Figure 2. ,80287 Pin Configuration
Figure 1. 80287 Block Diagram
Intel Ccrporation Assumes No Responsibility for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit
'
,
OCTOBER 1983
, Patent Licenses are Implied.
© INTEL CORPORATION, 1983.
ORDER NUMBER: 210920-002
4-52, ,
80287
Table 1. 80287 Pin Description
·Type
Name and Function
ClK
I
Clock input: this clock provides the basic timing for internal 80287 operations. Special MOS level inputs are required. The 82284 or 8284A ClK
outputs are compatible to this input.
CKM
I
Clock Mode signal: indicates whether ClK input is to be divided by 3 or
used directly. A HIGH input will cause ClK to be used directly. This input
may be connected to Vcc or Vss as appropriate. This input must be either
HIGH or lOW 20 ClK cycles before RESET goes lOW.
RESET'
I
System Reset: causes the 80287 to immediately terminate its present activity and enter a dormant state. RESET is required to be HIGH for more than
480287 ClK cycles. For proper initialization the HIGH-lOW transition must
occur no sooner than 50 itS after Vee and ClK meet their D.C. and A.C.
specifications.
015-00
1/0
Data: 16-bit bidirectional data bus. Inputs to these pins may be applied
asynchronous to the 80287 clock.
BUSY
0
Busy status: asserted by the 80287 to indicate that it is currently executing
a command.
ERROR
0
Error status: reflects the ES bit of the status word. This signal indicates
that an unmasked error condition exists.
PEREa
0
Processor Extension Data Channel operand transfer request: a HIGH on
this output indicates that the 80287 is ready to transfer data. PEREa will be
disabled upon assertion of PEACK or upon actual data transfer, whichever
occurs first, if no more transfers are required.
PEACK
I
Processor Extension Data Channel operand transfer ACKnowledge: acknowledges that the request signal (PEREa) has been recognized. Will
cause the request (PEREa) to be withdrawn in case there are no more
transfers required. PEACK may be asynchronous to the 80287 clock.
NPRD
I
Numeric Processor Read: Enables transfer of data from the 80287. l'his
input may be asynchronous to the 80287 clock.
NPWR
I
Numeric Processor Write: Enablestransfetof data to the 80287. This input
may be asynchronous to the 80287 clock.
NPS1, NPS2
I
Numeric Processor Selects: indicate the CPU is performing an ESCAPE instruction. Concurrent assertion of these signals (i.e., ~ is lOW and NPS2 is
HIGH) enables the 80287 to perform floating point instructions. No data transfers involving the 80287 will occur unless the .device is selected via these
lines. These inputs may be asynchronous to the 80287 clock.
CMD1, CMDO
I
Command lines: These, along with select inputs, allow the CPU to di rect the
operation of the 80287.
These inputs may be asynchronous to the 80287 clock.
Symb"ols
,.
4-53
210920-002
"nt_I@>
I••'e'
80287
Table 1. 80287 Pin Description (cont.)
Type
Name and Function
ClK286
I
CPU Clock: This input provides a sampli ng edge for the 80287 inputs S1, SO,
COD/iNTA, READY, and HlDA. It must be connected to the 80286 ClK input.
S1,SO_
COD/INTA
I
Status: These inputs must be connected to the corresponding 80286 pins.
HlDA
I
Hold Acknowledge: This input informs the 80287 when the 80286 controls
the local bus. It must be connected to the 80286 HlDA output.
READY
I
Ready: The end ota bus cycle is signaled by this input. It must be connected
to the 80286 READY input.
I
System gtound, both pins must be connected to groun~.
I
+5V supply
Symbols
Vss
.
Vee
effectively extends the register and instruction set
of an iAPX 286/1.0 system for existing iAPX 286
data types and adds several new data types as well.
Figure 3 presents the program visible register
model of the iAPX 286/20. Essentially, the 80287
can be treated as an additional resource or an
extension to the iAPX 286/1 0 that can be used as a
single unified ,system, the iAPX 286/20.
FUNCTIONAL DESCRIPTION .
The 80287 Numeric Processor Extension (NPX)
provides arithmetic instructions for a variety of
numeric data types in iAPX 286/20 systems. It also
, executes numerous built-in transcendental functions (e.g., tangent and log functions). The 80287
executes instructions in parallel with a 80286. It
80287
STACK:
80288
15
oI
FILE:
I
AX
8X
CX
DX
SI
DI
8P
SP
R1
R2
I
I
I
I
RS
I
R8
R7
I
I
SIGN
EXPONENT
I
IP
FLAGS
)
SS
0
R3
R8
o
15
I!
~_:
C S,§
L _5
_
'
DS,
ES
1
SIGNIFICAND
R~
I
L_O',
15
TAG FIELD
79
~~~7~8~~~~M~"~
____~~~~____~0
I
I
'I
.
CONTROL REGISTER
STATUS REGISTER
TAO'WORD
f- ,INSTR,:!CTION POINTER_
~
DATA POINTER
-
Figure 3. IAPX 286/20 Architecture
\
.
4-54
210920.002
80287
HARDWARE INTERFACE
The 80287 has two operating modes similar to the
two modes of the 80286. When reset, 80287 is in
the real address mode. It can be placed in the
protected virtual address mode by executing the
SETPM ESC instruction. The 80287 cannot be
switched back to the real address mode except by
reset. In the real address mode, the iAPX 286/20 is
completely software compatible with iAPX 86/20,
88/20.
Once in protected mode, all references to memory
for numerics data or status information, obey the
iAPX 286 memory management and protection
rules giving a fully protected extension of the
80286 CPU. In the protected mode, iAPX 286/20
numerics software is also completely compatible
with iAPX 86/20 and iAPX 88/20.
SYSTEM CONFIGURATION
Communication of instructions and data operands
between the 80286 and 80287 is handled by the
CMDO, CMD1, FJI5ST, NPS2, f\lI5RO, and f'1FIWR signals. 1/0 port addresses 00F8H, OOFAH, anc;l OOFCH
are used by the 80286 for this communication. When
any of these addresses are used, the FJI5Sl input
must be LOW and NPS2 input HIGH. The IORC" and
JOWC outputs of the 82288 identify 1/0 space transfers (see Figure 4). CMDO should be connected to
latched 80286 A1 and CMD1 should be connected to
latched 80286 A2. The
SO, CODIifiITA,READY,
HlDA, and eLK pins of the 80286 are connected to
the same named pins on the 80287.
.
sr,
1/0 ports OOF8H to OOFFH are reserved for the
80286/80287 interface. To guar.antee correct operation of the 80287, programs must not perform any
1/0 operations to these ports.
As a processor extension to an 80286, the 80287
can be connected to the CPU as shown in Figure 4.
The data channel control signals (PEREQ,
PEACK), the BUSY signal and the NPRD, NPWR
signals, allow the NPX to receive instructions and
data from the CPU. When in the protected mode, all
information received by the NPX is validated by the
80286 memory management and protection unit.
Once started, the 80287 can process in parallel
with and independent of the host CPU. When the
NPX detects an error or exception, it will indicate
this to the CPU by asserting the ERROR. signal.
The PEREQ, PEACK, BUSY, and ERROR signals of
the 80287 are connected to the same-named 80286
input. The data pins of the 80287 should be directly
connected to the 80286 data bus. Note that all bus
drivers connected to the 80286 local bus must be
. inhibited when the 80286 reads from the 80287.
The use of COD/INTA and M/iQ in the decoder·
prevents INTA bus cycles from disabling the data
transceivers.
The NPX uses the processor extension request and
acknowledge pins of the 80286 CPU to implement
data tram,fers with memory under the protection
model of the CPU. The full virtual and physical
address space of the 80286 is available. Data for
the 80287 in memory is addressed and represented
in the same manner as for an 8087.
Table 2 lists the seven data types the 80287 supports and presents the format for each type. These
values are stored in memory with the least significant digits at the lowest memory address. Programs retrieve these values by generating the
lowest address. All values should start at even
addresses for maximum system performance.
The 80287 can operate either directly from the CPU
clock or with a dedicated cloc.k. For operation with
the CPU clock (CKM=O), the 80287 works at onethird the frequency of the system clock (Le., for an
8 MHz 80286, the 16 MHz system clock is divided
clown to 5.3 MHz). The 80287 provides a capability
to internally divide the CPU clock by three to pro. duce the required internal clock (33% duty cycle).
To use a higher performance 80287 (8 MHz), an
8284A clock drJver and appropriate crystal may be
used to directly drive the 80287 with a 1/3 duty
cycle clock.on the ClK input (CKM=1).
Internally the 80287 holds all numbers in the temporary real format. load instructions automati~
cally convert operands represented in memory as
16-, 32-, or 64-bit integers, 32- or 64-bit floating
point number or 18-digit packed BCD numbers
into temporary real format. Store instructions perform the 'reverse type conversion.
PROGRAMMING INTERFACE
80287 computations use the processor's register
stack, These eight 80-bit registers provide. the
equivalent capacity of 40 16-bit registers, The
80287 register set can be accessed as a stack, with
4-55
210920-002
80287
VCc
2OKo
RESET I-H--,
Vee
iiiiDv Ht-+--,
I
CLK r- ~ .51 r- .
82284
~:
20Kn
20Kn
I
SOf--<
ADDRESS
r--~J~.::.--+-----~~~~~~~~~~~5~l:~~~~~IT~~~~~~~I·~c~~~rc~t--++--I RESET
A15-Ao
~I-H-r~-+-I-;~
ClK
ClK
51
SO
51
80286
So
DwOo
-r--
MliO
M/iO
t- ERROR PEREQ-r-
r- iUlW
8.2288
PEAcK
~
COD/iii'i'A HlDA
A2 Al AO El
I - - fi
DEN~~~+-~-+-+---+-----T---+-~
D~RI-~-r+-I--I-+---+-----t---+-r-I
AlEI-~-r+-I--I-+---+-----t---+-r-I
iORC
8205
r-- .......Er3_ _O'+-....
~+-~I
r-----~
1-r--+-+-_--IICl~
COD/INTA_ HlDA
'---I-I-IRESET PEACK -
D D
IQ Q Q
~
L---+-IHiiEAoY PEREQ t----t-+--IClK286
4-----+-1--151
L--I---+-I--ISO
r-ERROR
r---,I
C'
:i:_JL
8284A
------<>~
~
8::
t_,....---------------r-r-""""'8287
80287
L-----------t-----I-+-iNPWR
:r:--I
T
915-00 -DATA
'-----+---+-I......-fiiiPiiD
~
r--.
;==n
iUlW
ClK
NPS2 -Vee
-
~t_----------------~
CMDlt_------------------~
CMDO~--------------------~
CKM
/
___ .JI
Figure 4. iAPX 286/20 System Configuration.
4-56·
210920-002
I"n+._1
•• ~
II!>
80287
Table 2. 80287 Datatype Representation In Memory
Data
Formats
HIGHEST ADDRESSED BYTE
Most Significant Byte
Range
Precision
7
104
Word Integer
16 Bits
01 7 017 01 7 01 7 017 017 017 017 017
109
32 Bits
0
sj
I (TWO'S
COMPLEMENT)
MAGNITUDE
0
31
1019
Long Integer
64 Bits
51
I(TWO'S
COMPLEMENT)
MAGNITUDE
0
63
1018
Packed BCD
18 Digits
5\
79
10±38
Short Real
24 Bits
5
x
I
72
1o±308
53 Bits
64 Bits
51
SIGNIFICAND
23'-
=
=
dg
dB
,d,
d6
ds
d,
d3
d,
d,
Ii
BIASED
EXPONENT
I
0
I.
ill
I
SIGNIFICAND
0
64 ·63'
(1) S Sign bit (0 positive. 1 negative)
(2) d n = Decimal digit (two per byte)
(3) X Bits have no significance; 8087 ignores when loading, zeros when storing.
(4) 1 = Position of implicit binary point
(5) I '" Integer bit of significand; stored in temporary real,
implicit in short and long real
(6) Exponent Bias'(normalized values):
Short Real: 127 (7FH)
Long. Real: 1023 (3FFH)
Temporary Real: 16383 (3FFFH)
s
.
(7) Packed BCD: (-1) (017" .00)
(8) Real: (-1 )S(2E-BIAS)(Fo F1. , .)
instructions operating onlhe top one or two stack
elements, or as a fixed register set, with instructions operating on explicitly designated registers,
and appropriate high level languages. All iAPX
86/88 development tools .which support the 8087
can also be used to develop software for the iAPX
286/20 in real address mode.
=
Table 6 lists the 80287"s instructions by class. No
special programming tools are necessary to use
the 80287 since all new instructions and data types
are direQtly Suppo(ted by the iAPX 286 assembler
I
I
SIGNIFICAND
52'-
=
do
0
I
BIASED
EXPONENT
79
NOTES:
dlO
0'
.
63
Temporary Real 10±4932
d 16 d 15 d'4 d'3 d 12 d'l
;\ EXPONENT
BIASED \
51
.
MAGNITUDE
d17
31
Long Real
I
5;1 MAGNITUDE J (TWO'S
COMPLEMENT)
15
Short Integer
o
.
.
Table ~ gives the execution times of SO{T1e typical
numeric instructions. ,
4-57
210920-002
80287
Table 3. Execution Time for Selected 80287 In.tructlons
Approximate Execution
Time (MS)
Floating Point Instruction
80287
(5 MHz Operation)
Add/Subtract
14/18
Multiply (single precision)
19
Multiply (extended precision)
27
Divide
39
Compare
9
Load (double precision)
10
Store (double precision)
21
Square Root
36
Tangent
90
,
Exponentiation
100
SOFTWARE INTERFACE
PROCESSOR ARCHITECTURE
The iAPX286/20 is programmed as a single processor. All communication between the 80286 and
the 80287 is transparent to software. The CPU automatically controls the 80287 whenever a numeric
instruction is executed. All memory addressing
modes, physical memory, and virtual memory of
the CPU are available for use by the NPX.
As shown in Figure 1, the NPX is internally divided
into two processing elements, the ,bus interface
unit (BIU) and the numeric execution unit (NEU).
The NEU executes all numeric instructions, while
the BIU receives and decodes instructions, requests operand transfers to and from memory and
executes processor control instructions. The two
units are able to operate independently of one
another allowing the BIU to maintain asynchronous communication with the CPU while the NEU
is busy processing a numeric instruction.
Since the NPX operates in parallel with the CPU,
any errors detected by the NPXmay be reported
after the CPU has executed the ESCAPE instruction which caused it. To allow identification of the
failing numeric instruction, the NPX contains two
pointer registers which identify the address of the
failing numeric instruction and the numeric
memory operand if appropriate for the instruction
encountering this error. .
INTERRUPT DESCRIPTION
Several interrupts of the iAPX 286 are used to
report exceptional conditions while executing
numeric programs in either real or protected
mode. The interrupts and their functions are
'shown in Table 4.
BUS INTERFACE UNIT
The BIU decodes the ESC instruction executed by the
CPU. If the ESC code defines a, math instruction, the
BIU transmits the formatted instruction to the NEU. If
the ESC code defines an administrative instruction,
the BIU executes it independently of the NEU. The
parallel operation of the NPX with the CPU is normally
transparant to the user. The BIU generates the BUSY
and ERROR signals for 80826/80287 processor synchronization and error notification, respectively.
4-58
The 80287 executes a single numeric instruction at
a time.' When executing most ESC instructions, the
210920.002
80287
-'ble 4. 80286 Interrupt ~rs Reserved for NPX
Interrupt Number
Interrupt, Function
7
An ESC Instruction was encountered when EM or TS of the 80286 MSW was set.
EM=1 indicates that softw'are emulatlon'of the instruction is required. When TS is
set, either an ESC or WAIT instruction will cause interrupt 7. This indicates that the
current NPX context may not belong to the current task.
9
The second or subsequent words of a numeric operand in memory exceeded a
segment's limit. This interrupt occurs after executing an ESC instruction. The saved
return address will not point at the numeric instruction causing this interrupt. After
processing the addressing error, the iAPX 286 program can be restarted at the
return address with IRET. The address of the failing numeric instruction and
numeric operand are saved in the 80287. An interrupt handh!r 10r this interrupt must
execute FNINIT before any other ESC or WAIT instruction.
13
The starting address of a numeric operand is not in the segmenfs limit. The return
address will pOint at the ESC instruction, including prefixes, causing this error. The
80287 .has not executed this instruction. The instruction and data address in 80287
refer to a previous, correctly executed, In~ruction.
16
The previous numeric instruction ca,used an unmasked numeric error. The address
of the faulty numeric instruction or numeric data operand is stored in the 80287.
Only ESC or WAIT instructions can cause this interrupt. The 80286 return address
will point at a WAIT or ESC instruction, including prefixes, which may be restarted
after clearing,the error condition in the NPX.
80286 tests the BUSV pin and waits until the 80287
indicates that it is not busy before initiating the command. Once initiated, the 80286 continues program
execution while the 80287 executes the ESC instruction. In iAPX 86/20 systems, this synchronization is
achieved by plaCing a WAIT instruction before aoESC
instruction. For most ESC instructions, the iAPX 286/20
does not require a WAIT instruction before the ESC
opcode. Hgwever, the iAPX 286/20 will operate correctly with these WAIT instructions. In all cases, a WAIT
or ESC instruCtion should be inserted after any 80287
store to memory (except FSTSW and FSTCW) or load
from memory (except FLDENV or FRSTOR) before the
80286 reads or changes the value to be sure the
numeric value .has already been written or read by
the NPX.
Data transfers between memory and the 80287,
when needed, are controlled by the PEREQ
PEACK, NPRD, NPWR, NPS1, NPS2 signals. The
80286 does the actual data transfer with memory
through its processor extension data channel.
Numeric data transfers with memory performed by
the 80286 use the same timing as any other bus
cycle. Control signals for the 8Q287 are generated
by the 80826 as shown in Figure 4, and meet the
ti,ming requirements shown in the AC requirements section.
NUMERIC EXECUTION UNIT
The NEU executes all instructions that 'involve the
register stack; these include arithmetic, logical, transcendental, constant and data transfer instructions.
The data path in the NEU is 84 bits wide (68 slgniflcand bits, 15 exponent bits and a sign bit) which
allows internal operand transfers to be performed at
Very high sPeeds.
When the NEU beaing executing an instruction, it
activates the BIU U Y-signal. This signal isused
in conjunction with the CPU WAIT instruction or
automatically with most of the ESC instructions to
synchronize both processors.
REGISTER SET
The 80287 register set iSShown in Figure 5. Each of
the eight data regist~rs in the 8087's register stack
4-59
210920-0~
inter
80287
DATA FIELD
79
SIGN
o
6483
78
TAG FIELD
1
0
SIGNIFICAND
EXPONENT
.
o
15
CONTROL REGISTER
STATUS REGISTE.R
TAG WORD
I- INSTRUCTION POINTER ...
I-
DATA POINTER
-
Figure 5. 80287 Register Set
is 80 bits wide and is divided into "fields" corresponding to the NPX's temporary real data type.
At a given point in time the TOP field in the status
word identifies the current top-of-stack register. A
"push" operation decrements TOP by 1 and loads a
value into the new top register. A "pop" operation
stores the value from the current top register and
then increments TOP by 1. Like 80286 stacks in
memory, the 80287 register stack grows "down"
toward lower-addressed registers.
Instructions may address the data registers either
implicitly or explicitly. Many instructions operate on
the register at the TOP of the stack. These instructions
implicitly address the register pOinted by the TOP.
Other instructions allow the programmer to explicitly
specify the register which is to be used. This explicit
register addressing is also "top-relative."
The instructions FSTSW, FSTSW AX, FSTENV, and
FSAVE which store the status word are executed
exclusively by the BIU and do not set the busy bit
themselves or require ,the Busy bit be cleared in
order to be executed.
The four numeric condition code bits (C O-C 3) are
similar to the flags in a CPU: instructions that perform
arithmetic operations update these bits to reflect the
outcome of NPX operations. The :effect of these
instructions on the condition code bits is summarized
in Tables 5a and 5b.
Bits 14-12 of the status word point to the 80287 register that is the current top-ol-stack (TOP) as described
above. Figure 6 shows the six error flags in bits 5-0 of
the status word. Bits 5-0 are set to indicate that the
NEU has detected an exception while executing an
instruction. The section on exception handling explains
how they are set and used.
STATUS WORD
The 16-bit status word (in the status register)
shown in Figure 6 reflects the overall state of the
80287. It may be read and inspected by CPU code.
The busy bit (bit 15) indicates whether the NEU is
executing an instruction (B = 1) or is idle (B = 0).
4-60
Bit 7 is the error summary status bit. This bit is set if
any unmasked exception bit is set and cleared otherwise. If this bit is set, the ERROR signal is asserted.
210920-002
80287
o
15
I B Ic.d TOP I ~ I c,j eoll;sl x I pEluEloElzEIDEllE I
I
EXCE PTION FLAGS (1
= EXCEPTION HAS OCCURRED)
I
INVALID OPERATION"
DENORMALIZED OPERAND"
ZERO DIVIDE"
OVERFLOW"
UNDERFLOW"
PRECISION"
(RESE RVED)
ERROR SUMMARY STATUS(')
COND ITION CODel 2l
TOP OF STACK POINTER(3)
NEU BUSY
g:ES IS SET IF ANY UNMASKED EXCEPTION BIT IS SET, CLEARED OTHERWISE.
(3)~~~ ~~~~~: FOR CONDITION CODE INTERPRETATION.
..
000 = Regiater 0 la Top 01 Stack
001 = Regiater 1 ia Top 01 Stack
.
111 ='Reglster 71s Top 01 Stack
"For definitions, see the section on exception handling
Figure 6. 80287 Status Word
TAG WORD
The tag word marks the content of each register as
shown in Figure 7. The principal function of the tag
word is to optim~e the NPX's performance. The eight
two-bit tags in the tag word can be used, however. to
interpret the contents of 80287 registers.
INST.RUCTION AND DATA POINTERS
The instruction ,and data pointers (See Figures 8a
and 8b) are provided for user-written error handlers. Whenever the 80287 executes a new instruction, the BIU saves the instruction address, the
operand address (if present) and the instruction
opcode. 80287 instructions can store this data into
memory.
The instruction and ~ata pointers appear in one of
two formats depending on the operating mode of
the 80287. In real mode, thes,e values are the 20-bit
physical address and 11-bit opcode formatted like
the 8087. lri p~otected mode, these values are the
3~-bit virtual addresses used by the progra&n
4-61
which executed an ESC instruction. The' same
FLDENV/FSTENV/FSAVE/FRSTOR instructions as
those of the 8087 are used to transfer these values
between the 80287 registers and memory.
The saved instructi'on address in the 80287 will
point at any prefixes which preceded the instruc-'
tion. This is different than in the 8087 which only
pointed at the ESCAPE instruction opcode.
CONTROL WORD
The NPX provides several processing options
which are selected by loading a word from memory
into the control word. Figure 9 shows the format
and encoding of ffelds in the control word.
The low order byte of this control word configures
the 80287 error and exception masking. Bits 5-0 of
the controi word contain individual masks for each
of the six exceptions that the 80287 recognizes.
The high order byte of the control w,ord configures
the 80287 operating mode including, precision,
210920-002
".'
Table Sa. Condition Code Interpretation
Instruction
Type
;
Compare, Test
Remainder
Examine
Co,
~
C1
0
0
0
l'
X
X
X
X
0
1
0
1
01
0
Oq
~
U
1
U
U
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
: 1
0
0
1
1
0
0
1
1
0
0
1
',1
0
0
1
'1
0
1
0
1
0
1
0
1
0
1
0
Ca
0
0
1
1
"
"
.
.
"
1
0
1
0
1
Interpretation,
ST > Source or 0 (FTST)
ST < Source or 0 (FTST)
,ST = Source or 0 (FTST)
ST is not comparaole
Complete reduction with
three low bits of quotient
(See Table 5b),
Incomplete Reduction
Valid, positive unnormalized
Invalid, ,positive, exponent =0
Valid .. negative, unnormalized '
Invalid, negative, exponent =0
Valid, positive, normaiized
Infinity, positive
Valid, negative, normalized
Infinity, negative
Zero, positive
Empty
Zero, negative
Empty
Invlllid, positive, exponent = 0
Empty
Invalid, negative, exponent = 0
Emp,ty
"
NOTES:
1. ST = Top of stack
2. X = value is not affected by instruction
3. U = vlllue is undefined following instruction
4. Qn' = QUotient bit n
Table 5b. Condition Code Interpretation after
FPREM Instruction Aa a Function of
Dividend Value
"
Dlvlilend Range '
Dividend < 2 • Modulus
,Dividend < 4, • Modulus'
,. Dividend ... 4 • Modulus
~
Q,
C:l C1
C:l ,01
~, '01 '
.'00
00
00
00
NOTE:'
1. Previous vallie ot indicated bit, not affected by F,PREM.
, Instruction execution'. '
rounding, ,and infinity control. Th~ precision control bits (bits ,9-8) can be, used to set the 80287
in~ernal, operating pr.ecision 'at less, than the
~efault of temporary real (SO-bit) precision. This
qan I>e uS,eful in Pfoviding comp$tibility with, the
early generation arithmetic processors of small';II:
preciSion than the 80287. The rounding 'control
bits (bits 11-10) provide for directed rounding and
tl'uechop as well'as'the'unbiased roiJnd to nellrest
even mode specified in the IEEE'standafd~' C,ontrol
over closure'of the numbar space at infinity is also
provided '(either affine closure: ± 00, or projective
clOSUre: 00, is traatedas' unslgned, mily be
specified). '
",'. , "
"
, 4-62
21092Il-002
80287
TAG VALUES:
00 = VALID
01 = ZERO
10 = INVALID or INFINITY
11 = EMPTY
NOTE: The index i of tag (i) is D.21 top-relative. A program
typically uses the "top" field of Status Word to determine which tag(i) field refers to logical top of stack.
Figure 7. 80287 Tag Word
MEMORY OFFSET
o
15
CONTROL WORD
+0
STATUS WORD
+2
TAG WORD
+4
IPOFFSET
. +6
CS SELECTOR
DATA OPERAND OFFSET
+10
DATA OPERAND SELECTOR
+12
Figure 8a. Protected Mode 80287 Instruction and Data Pointer Image in Memory
EXCEPTION HANDLING
The 80287 detects six different exception conditions
tHat can occur during instruction execution. Any or
all exceptions will cause the assertion of external
ERROR Signal and ES bit of the Status Word if the
appropriate exception masks are· not set.
The exceptions that the 80287 detects and the 'default'
, procedures that will be carried out if the exception is
masked, are as follows:
INDEFINITE, or to propogate already existing. NANs
as the calculation result.
Overflow: The result is too large in magnitude to
fit the specified format. The 80287 wi II generate an
encoding for infinity if this exception is masked.
Zero Divisor: The divisor is zero while the dividend is a non-infinite, non-zero number. Again, the
80287 will generate an encoding for infinity if this
exception is masked.
Invalid Operation: Stack overflow, stack underflow,
indeterminate form (0/0, 00, -00, etc) or the use of a
Non-Number (NAN) as an operand. An exponent value
of all ones and non-zlilro significand is reserved to
identify NANs. If this exception is masked, the 80287
default response is to generate a specific NAN called
4-:63
Underflow: The result is non-zero but too small in
magnitude to fit in the specified format. If this
exception is masked the 82087· Will denormalize
(shift right) the fraction until'the exponent is in
range. The process is called gradual underflow.
2109~o-002
"nt_Ie
I••'e"
80287
MEMORY
o
15
,
,
CONTROL WORD
+0
STATUS WORD
+2
TAO WORD
+4
INSTRUCTION POINTIER (15-0)
+8
I
INSTR~CTIOt\1
POINTE (111-18) 0
INSTRUCTION
OPCODE (10-0)
+8
DATA POINTER (15-0)
DATA POINTER
(111-18)
15
OFFSet.
I'
+10
+12
0
o
1211
Figure 8b. Real Mode 80287 In8tructlon and Data Pointer Image In Memor,
~
~
I x x x I ICI
RC
I
PC
I x I xjPMJuMI0MlzMIDM[ 1a.U
I
EXCEPTION MASKS (1 =EXCEPTION IS MASKED)
INVALID 'OPERATION
DENORMALIZED OPERAND
ZERO DIVIDE
OVERFLOW
UNDERFLOW
PRECISION
(RESERVED)
L-.L_ _ _ _ _ _ _ _ _ _ _ _ _ _
(RESERVED)
PRECISION CONTROL (1)
L...L_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ROUNDING CONTROL(,21
L-.L~
1..-_ _ _ _ _ _ _ _ _ _ _ _ _. , -_ _ _ _
_ _' - -_ _ _ _ _ _ _ _ _ _ ___"""_ ___:"-
(11~CONlRol
=
00 24 BITS (SHORT REAl.)
01 = RESERVED
10 = 53 BITS (lONG REAL)
11 84 BITS (TEMP REAL)
=
, 12l!!Q!!!!llm!!i CONTROL
00
01
10
11
=
=
=
=
'
INFINITY CONTROL (0 = PROJECTIVE, 1 =
(I:IESERVED)
~FFINE)
,
ROUND TO NEAREST OR EVEN
ROUND DOWN (TOWARD -x)
ROUND UP (TOWARD +x)
CHOP (TRUNCATE TOWARD ~RO)
Figure 9. 80287 Control Word
4-64
,
"
21092O-OOl!
80287
. Therefore, any interrupt controller oriented instructions for the iAPX 86/20 may have to be
deleted. -
Denormallzed Operand: At least one of the
operands is denormalized; it has the smallest exponent but a non-zero significand. Normal processing continues if this exception is masked off.
Inexact Result: The true result is not exactly representable in the specified format, the result is rounded
according to the rounding mode, and this flag is set.
If this exception is masked, processing will simply
continue.
If the error is not masked, the corresponding error
bit and the error status bit (ES) in the control word
will be set, and the ERROR output signal will be
asserted. If the CPU attempts to execute another
ESC or WAIT instruction, exception 7 will occur.
The error condition must be resolved via an interrupt service routine. The 80287 saves the address
of the floating point instruction causing the error
as well as the address of the lowest memory location of any memory operand required by that
instruction.
2. Interrupt vector 16 must pOint at the numeric
error handler routine.
3. The saved floating point instruction address in
the 80287 includes any leading prefixes before
the ESCAPE opcode. The correspo~ding saved
address of the 8087 does not include leading
prefixes.
'
4. In protected mode, the format of the saved instruction and operand pointers is different than
for the 8087. The instruction opcode is not
saved-it must be read from memory if needed.
5. Interrupt 7 will occur when executing ESC instructions with eitherTS or EM of MSW=1.lfTS
of MSW=1 then WAIT will also cause interrupt
7. An interrupt handler should be added to handle this situation.
IAPX 86/20 COMPATIBILITY:
iAPX 286/20 supports portability of iAPX 86/20
programs when' it is in the real address mode.
However,. because of differences in the numeric
error handing techniques, error handling routines
may neE!d to be changed. The differences between
an iAPX 286/20 and iAPX 86/20 are:
1. The NPX error signal does not pass through an
interrupt controller (8087 INT signal does).
4-65
6. Interrupt 9 will occur if the second or subsequent words of a floating point operand fall
outside a segment's size. Interrupt 13 will occur
if the starting address of a numeric operand
falls outside a segment's size. An interrupt
handler should be added to report these programming errors.
In the protected mode, iAPX 86/20 application
code can be directly ported via recompilation if the
286 memory protection rules are not violated.
21092Q:-002
802.87
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ... O°C to 70°C
Storage Temperature ........ -65°C to +150°C
'.
Voltage on Ahy Pin with
Re,'pectto Ground ............... -1.0 to +7V
Power Dissipation .................... 3.0 Watt
·NOTlCE: Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the deviGe. This is a stress rating 'only
and functional operation of the device at these or
any pther conditions above those indicated in the
operational sections of. this specification, is not
implied. Exposure to absolute maximum, rating
conditions for extended periods may affect device
reliability.
,
D.C. CHARACTERISTICS TA = O°C to 70°C, Vee = 5V, +/-5%
5 MHz
Parameter
·3 Min
-3 max
Unit
Input lOW Voltage
-.5
.8
V
VIH
Input HIGH Voltage
2·0
Vcc +.5
V
VllC
Clock Input lOW Voltage '
. CKM=1:
.
CKM=O:
-.5
-.5
.8
V
V
Clock Input HIGH Voltage
CKM=1:
CKM=O:
2.0
3.8
Symbol
Vil
VIHC
VOL
Output lOW Voltage
.6
Vee + 1
Vcc + 1
Test Conditi()ns
,
V
V
.45
V
IOl =3.0mA
V
' IOH = -400 pA.
pA.
OV :::;VIN :::;Vee
.45V :::; VoUT
2.4 .
VOH
Output HIGH Voltage
lu
Input leakage Current
±10
!LO
Output leakage Current
±10
pA.
Icc
Power Supply Current
475
mA
CIN
I~put CapaCitance
10
pF
Fc= 1 MHz
Co
Input/Output Capacitance
(00-015)
20
pF
Fc= 1 MHz
CClK
ClK Capacitance
12
pF
Fc= 1 MHz
4456
: :; Vcc
210920-002
80287
A.C. CHARACTERISTICS (TA= O°C to 70°C, Vcc + 5V,=/-5%)'
TIMING REQUIREMENTS
A.C. timings are referenced to 0.8V and 2.0V points on signals unless otherwise noted.
.
5 MHz
Symbol
Parameter
-3 Min
TCLCL
ClK Period
CKM=1:
CKM=O:
200
62.5
TCLCH
ClKlOWTime
CKM=1:
CKM=O:
118
15
ClK HIGH Time
CKM=1:
CKM=O:
69
20
TCHCL
-3 max
Unit
500
250
ns
ns
230
ns
ns
235
ns
ns
At 2.0V
At 3.8V
.
Test Conditions
\
At 0.8V
At 0.6V
TCH1CH2
ClK Rise Time
10
ns
1.0V t03.5V if CKM = 1.
TCL2CL1
ClK Fall Time
10
ns
3.5V to 1.0V if CKM = 1.
TOVWH
Data Setup to NPWR Inactive
75
ns
TWHOX
Data Hold from J\I15iiiVR Inactive
30
ns
J\I15iiiVR, msFID Active Time
Command Valid to f\JI5WR or
95
ns
0
ns
130
ns
85
ns
AtO.8V
250
ns
At 2.0V
50
ns
-30
ns
30
ns
50
ns
62.5
ns
TWLWH ,
TRLRH
TAVRL,
TAVWL
msFID Active
At 0.8V
TMHRL
Minimum Delay from PEREQ
Active to msFID Active
TKLKH
PEACK Active Time
TKHKL
PEACK Inactive Time
TKHCH
J5EACI( Inactive to f\JI5WR,
TCHKL
i'lPWR, NJ5Fit5 Inactive to PEACK
TWHAX,
TRHAX
Command Hold from f\JI5WR,
.fiIJ5RO Inactive
TKLCL
J5EACR .Active
T2CLCL
ClK286 Period
T2CLCH
ClK286 lOW Time
15
ns
AtO.8V
T2CHCL
ClK286 HIGH Time
20
ns
At2.0V
T2SVCL
'SO, 'ST Setup Time to ClK286
22.5
ns
T2CLSH
'SO, 'ST Hold Time from ClK286
0
ns
fiIJ5RO
Inactive
Active
fiIJ5RO Active
Setup to ~,
.
"
4-67
210920-002
80287
A.C. CHARACTERISTICS, continued
nMING REQUIREMENTS
5 MHz
Symbol
-3 Min
Param.....
-3 max
Unit
TCIVCL
COD!INTA Setup Time
to COO86
0
ns
TCLCIH
COD/INTAHoldTimefromClK286
0
ns
TRVCL
READY Setup Time to CLK286
38.5
ns
TCLRH
READY Hold Time from ClK286
25
ns
THVCL
HlDA Setup Time to CLK286 '
0
ns
Test Conditions
!
0
/
TCLHH
HlDA Hold Time from CLK286
O·
ns
Tlvct,
NPWR, NPRD to ClK Setup Time
70
ns
NOTE 1
TCUH
' NPWR, NPRD from ClK Hold Time
45
ns
NOTEt
RESET to ClK Setup Time
20 '
ns
NOTE 1
RESET from ClK Hold Time
20
ns
NOTE 1
TRSCL
, TCLRS
A.C. CHARACTERISTICS,
nMING RESPONSES
5 MHz
Symbol
TRHQZ
TRLQV
TILBH ,
TWLBV
TKLML
TCMDI
TRHQH
Parameter
-3 Min
RJ5RD Inactive to Data Float
RJ5RD Aqiive to Data Valid
EmmA Active to lIDS\' Inactive
RPWR Active to lIDS\' Active
~ Active to J5'E'Rm Inactive
100
Command Inactive Time
Write-to-Write
Read-to-Read
Write-to-Read
Read-to-Write
95
250
105
95
Data Hold from NPRD Inactive
5
-3 max
Unit
37.5
ns
NOTE 2'
60
ns
NOTE 3
ns
NOTE 4
100
ns
, NOTE 5
127
' ns
NOTE 6
ns
ns
ns
ns
At2.0V
At2.0V
At2.0V
At2.0V
ns
NOTE 7
.'
\
Test Conditions
,
NOTES:
1. This is an asynchronous input. ,,(his specification is given for testing purposes only, to assure recognition at a specific eLK edge:
2. Roat condition occurs when output current is less than ILO on DO-015.
3. 00-015 loading: CL = 100pF.
4. BUSY loading: CL = 100pF.
5. SiJSY loading: CL 100pF.
6. On last data transfer of numeric instruction.
, 7. 00-015 loading: CL 100pF.
=
=
4~8
210920-002
"
80287
WAVEFORMS (conl)
DATA TRANSFER nMING (INITIATED ~ 80288)
c:Mt!It CMD1
}.
II/JIIf,NPS2
-
TAVRL \
.. -:l
TRLQV
I-
/. ///V
Do-D, 5
\.
TAVWL
_TWLW~
\
-:I
!D~'!I!
DATA MAY CHANGE
-
'J.
TWLBN
/
\
}
TRHQZ_
_TRHQH_
DATA OUT
VALID
\.\.\.'\
•
TRHAX
I+--TRLRH
NPRD
Do-D, 5
~
VALID
..
-'
-:I
I
DATA
TRANSFER
TO
TWHDX
I::::
80287
TWHAX
/
DATA IN
VALID
DATA
TRANSFER
FROM
K
80287
DAtA MAY CHANGE
I
~ __________________-J~~_______________________ _
,
DATA CHANNEL TIMING (INmATED BY 80287)
C~~==:~
I
PEREQ
~_TM_H_R_L
fi-' ,--
VALID
TAVWL
TAVRL
______
TKLCL
-.. y"",-,-----~
TWHAX
~
__________
~~~------~~----------~~----
-
r------TKLKH-----I~
210920-002
•
I
80a87
J'
c.
WAVEFORMS (conl)
. ERROR OUTPUT TIMING
:~----------l...,c-=1
80288 STATUS TIMING
~---- T•
..,.....----.j..-----
'Tc -----I~
CLK286
. CODliN'!'A
HLDA
-----llf-'l- - NOTES:
1. This input transition occurs before TS.
2. This input transition. occurs after Te.
210920-002
80287
WAVEFORMS
'(Reset,~, RJ5RDare Inputsasynchronousto ClK. Timing requirements on this page
are given fortesting purposes only, to assure recognition ata specific CLKedge.)
, ClK, RESET TIMING (CKM = 1)
, 1
Cl~L
. $1
1
$2·1
\,
I
$1
$2
1
1
_ _---.......---1
(lFCKM = 1 ) -
RESET
\ elK, NPRD, NPNR TIMING (CKM = 1)
ClK
(IFCKM 1)
=
NPRD,
NPNR
1\---
-
\\\\\\\\\
CLK, RESET TIMING (CKM = 0)
NOTE: Reset must meet timing shown to guarantee known phase of Internal + 3 circuit
CLK, NPRD, NPWR TIMING (CKM
11>2
.
I
=0)
NPRD,
NPWR
4-71
21CJ920.002 ,
I.
inteI-' "
802117
T!lble 6. 80287 Extensions to the 80286 Instruction Set
---_.
I
,.
Optional
.,1881t
D,lapI_ment
Data Tranaf.r
FLD = LOAD
1 MF
I
Intager/Real Memory to ST(O)
Long Integer Memory to ST(O)
Temporary Real Memory to
ST(O)
BCD Memory to ST(O)
ST(I) to ST(O)
,
ESCAPE MF
~~APE
I
'ESCAPE
=
1
1 1 1
0 1 1
I
I
I
MOD 0 0 0 RIM [
MOD 1 0 1 RIM
~I~P=.=:
~i~p=
I
MOD 1 0 0 RIM [=.=
1 ESC"PE' 0 0 1
I
1 1
0 0 0 ST(i)
1
MOD 0 1 0
ST(O) to Integer/Real Memory
1 ESCAPE MF
ST(O) to STeil
'I ESCAPE
1 0 1
,ST(O) to Integer/Real Memory
I ESCAPE
MF
ST(O) to Long Integer Memory
I
1 1 1 1 MOD 1 1 1 RIM
F6TP = STORE AND POP
ESCAPE
1
IESCAPE 0 11
-ECAPE .. :
I
1
I
I
1 1
R/M
0 1 0 STeil
MOD 0,1
lilMOD.l
I
C=.=.~·I~P=:J
I
1 0 RIM
1 0 1 11
I
0 0 1
I
1 1
Integer/Real Memory to ST(O)
I
~
I
MOD 0 1 0 RIM [
ST(I) to ST (0)
I
ESCAPE' 0 0 0
I
1 1
FXCH - Exchange STeil and
ST(O)
ESCAPE
1
0 1 1
=.EI~P=.J
= =
~I~ =J
[='=:'~i~=
~-
ST(O) to ST(,)
J
ST(I)I
0 0 1 5":(1)
01
10
11
38-56
52-60
40-60
48-54
96-104
SO-90
60-66
,
53-65
2~10
64-90
62-92
15-22
I~ = = ~i~p~.J
~=
1181t
Integ.,
17-22
1 R/M [ =
MOD 1 1 1
J
Clock Count Range
328It· ,1481t
Integer
R.al
GO
::
MOD 1 0 1 RIM [=.=
FST= STORE
ST!O) to BCD Memory
I: =:=:PI~P=
1 ESCAPE 1 1 1
"'
, ST(O) to Temporary Real
Memory
=.=.~I~P=.j
328"
R.al
86-92
84-94
,
98-106
82-92
65-75
72-86
94-105
52-58
520-540
17-24
I
10-15
Comparison
FCOM = Compare
ESCAPE MF
0 1 0 ST(I)
FCOMP = Compare and Pop
0 0 0
FTST = Test ST(O)
IESCA~E
0
FXAM = Examine lIT(O)
I ESCAPE
0 0 1
ST(I) to ST(O)
FCOMPP = Compare ST(I) to
ST(O) and Pop lWlce
J
s0-10
78-91
40-50
"
IESCAPE
IESCAPE
IESCAPE
Integer/Real Memory to SilO)
I
~ ~. ~I~~~
MF
0
1 1 0
P1
I
I1
I1
MOD 0 1 1 RIM
I
1
0 1 1 ST(I)
1
0 1 1 0 0 1
1 1
1 0 0 1 0 0
38-48
1 0 0 1 0 1
12-23
I1
I
1
,
45-55
'"
Mnemonlcs@
Intel 1982
,4-72
I
2109204102
80287
Table 6. 80287 Extensions to the 80286 Instruction Set (cont.)
I
Constants
I MF
FLDZ
= LOAD + 0.0 into ST(O)
FLDI
= LOAD + 1.0 into ST(O)
= LOAD" Into ST(O)
FLDPI
FLDL2T
ST(O)
= LOAD log2 10 Into
FLDL2E
ST(O)
= LOAD log2 e into
FLDLG2
ST(O)
= LOAD log,o 2 into
FLDLN2
ST(O)
= LOAD log.2 into
I
I
I
I
I
=
0 0
1
I
1 0
ESCAPE 0 0 1
1 1
1 0 1 0 0 0
ESCAPE 0 0
1
1 1
1 0 1 0
ESCAPE 0 0
1
1 1
1 0 1 0 0 1
ESCAPE 0 0
1
1 1
1 0
1 0
ESCAPE 0 0
1
1 1
1 0
1 1 0 0
ESCAPE 0 0
1
1 1
1 0
1 1 0
I
ESCAPE
0
I
ESCAPE
d
I
ESCAPE
MF
ESCAPE
d
ESCAPE
MF
I
I
32 Bit
Raal
Clock Count Range
32 Bit
84 Bit
Integer
Real
00
1 1
I
I
ESCAPE
Optional
B.18 Bit
Displacement
1 1 1 0
1 1
1 0
1
I
I
I
I
I
01
10
111 Bit
Integer
11
11-17
15-21
16-22
16-22
15-21
I
I
18-24
17-23
Arithmetic
FADD
= Addition
IntegerlAeal Memory with ST(O)
ST(i) and ST(O)
FSUB
1
P 0
I
0
I
MOD 0 0 0
,
r
RIM
ST(i) and ST(O)
1
P 0
1
~emory
with ST(O)
ST(i) and ~T(O)
FDIV = Division
IntegerlAeal Memory With ST(O)
ST(i) and ST(O)
1
I
I
I
ESCAPE
d
ESCAPE
MF
ESCAPE
d
I
MOD
1 0
- _.- -,
[ -DISP
- - .!
1 1 1 0
A
AIM
A RIM
90-120 108-143 95-125
-DISP
- - -,
- - - -'
0 0 1 RIM
I
0
I
MOD
1 1 A RIM·
P 0
I
r
1 1 1 1 A RIM
I
1 1
1 1 1 0 1 0
1 1
1 1 1 1 0
1 1
1 1 1 0 0 0
I
15-190
1 1
1 1 1
I
16-50
1
I
ESCAPE 0 0
1
ESCAPE 0 0
1
ESCAPE
0 0
1
I
I
I
AIM
1-
1
1 0 0
110-125 130-144 112-168 124-138
90-145 (Note 1)
-
-
-
DISP
._.-
I
I
102-137
70-100 (Note 1)
1
1
102-137
70-100 (Note 1)
1 1
ESCAPE 0 0
= Aound ST(O) to
90-120 108-143 95-125
I
I
FRNDINT
Integer
i
_I
P 0
FPREM = Partial Aemainder of
ST(O) +ST(I)
FSCALE
-
MOD 0 0 1
= Scale ST(O) by ST(I)
= Square Aoot of ST(O)
-
I
0
I
I
FSQRT
DISP·
0 0 0 ST(i)
= Multiplication
IntegerlAeal
-
1 1
= Subtraction
IntegerlAeal Memory with ST(O)
FMUL
MF
-1
,
215-225 230-243 220-230 224-238
193-203 (Note 1)
180-186
32-38
NOTE:
1. If P=1 then add 5 clocks.
4-73
210920-002
80287
Table 6. 80287 Extensions to the 80286 Instruction Set (cont.)
,Optional
8,16 Bil
Displacement
FXTRACT ~ Extract
Components of St(O)
FABS
ST(O)
~
1
1 1
Clock Count Range
1 1 0 l' 0 0
27-55
1
10-17
~
10-17
1 0
30-540
ESCAPE
0 0
ESCAPE
0 0
0 0 0 0
ESCAPE
0 0
0 0 0
ESCAPE
0 0 1
ESCAPE
0 0
ESCAPE
0 0
0
0 0
310-630
ESCAPE
0 0
0
0
900-1100
ESCAPE
0 0
0
700-1000
ESCAPE
0
0 0 0
[ESCAPE
0
0 0
Absolute Value of
FCHS ~ Change Sign of ST(O)
Transcendental
~
FPTAN
ST(O)
Partial Tangent of
•
FPATAN ~ Partial Arctangent
of ST(O) -ST(I)
F2XM1 ~ 2STlO )_1
FYL2X
[ST(O)l
~
I
ST(I) • Log2
FYL2XP1,~
ST(I)' L092
1 1
1 1 0 0
0
250-800
rST(O) +1]
ProceSSOr Control
FINIT ~ Initlahze NPX
~
FSETPM
Mode
Enter Protected
~
I
Store Control
ESCAPE
Load Control Word
ESCAPE
0 0
MOD
FSTCW ~ Store Control Word
ESCAPE
0 0
MOD
FSTSW AX
Word
FLDCW
~
., I
I.
2-8
2-8
0 0
0
0 0 0 0
0
RIM
10-16
~ ~I~~ ~J
7-14
R/M~ _ ~ ~I~~~ ~:
12-18
[
-------
FSTSW "" Store Status Word
FCLEX
~
Clear Exceptions
ESCAPE
1 0
MOD
1 1 RIM
ESCAPE
0
1 1
0 0 0
DISP
1 0
FSTENV
~
Store Environment
ESCAPE
0 0
MOD
0 RIM
FLDENV
~
Load EnVironment
ESCAPE
0 0
MOD
0 0 RIM
I
I
I-------
I-
12-18
2-8
-
- - - _.-I
I-------i
------I______ J
DISP
DISP
I
40-50
35-45
-------
FSAVE
~
Save State
FRSTOR ~ Restore State
FINCSTP
~
0
MOD
0 RIM
ESCAPE
0
MOD
0 0 RIM
ESCAPE
0 0
0
I ESCAPE
0 0
0
I
I
__DISP
__ ._ J
205-215
I~~~~~J
205-215
Increment Stack
POinter
FDECSTP ~ Decrement Stack
POinter
ESCAPE
4-14
l' 1
1
6-12
1---0]
6-12
210920-002
80287
Table 6. 80287 Extensions to the 80286 Instruction Set (cont)
Clock Count Range
I1
1 I 1
FFREE = Free ST(i)
ESCAPE
1. 0 1
1 0 0 0 ST(i)
FNOP = No Operation
ESCAPE
0 0
l'
NOTES:
1. If mod =00 then
If mod=01 then
If mod=10 then
If mod=11 then
2. If rIm =000 then
if r/m=001 then
if r/m=010 then
if r/m=011 then
If r/m=100 then
If r/m=101 then
if r/m=110 then
If r/m=111 then
0 1 0 0 0 0
9-16
I
DISP=O·, dlsp-Iow and dlsp-hlgh are absent
DISP=dlsp-low sign-extended to 16-blts, dlsp-hlgh Is absent
DISP=dlsp-hlgh; dlsp-Iow
rIm Is treated as an ST(I) field
EA=(BX) + (51) +DISP
EA=(BX) + (01) +DISP
EA=(BP) + (51) +DISP
EA=(BP) + (01) +DISP
EA=(SI) + DISP
EA=(DI) + DISP
EA=(BP) + DISP
EA=(BX) + DISP
·except If mod=OOO and r/m=110 then EA =dlsp-hlgh; dlsp-lolI\(.
3. MF= Memory Format
00-32-blt Real
01-32-blt Integer
10-64-blt Real
11-16-blt Integer
4. ST(O)= Current stack top
ST(I)
ith register below stack top
5. d= Destination
O-Destlnatlon Is $T(O)
1-Destinatlon Is ST(I)
6. P= Pop
O-No pop
l-PopST(O)
7. R= Reverse: When d=1 reverse the sense of R
O-Destlnatlon (op) Source
1-Source (op) Destination
8.
For FSQRT:
-0 .,;; ST(O) .,;; +00
For FSCALE:
_215 .,;; ST(1) < +215 and ST(l) integer
For F2XM1:
0'.,;; ST(O) of; 2- 1
0 < ST(O) <00
For FYL2X:
-00 < ST(1) < + 00
For FYL2XP1:
0.,;; IST(O)I < (2 -V2)/2
-00 < ST(1) < 00
For FPTAN:
0.,;; ST(O) ";;'TT/4
For FPATAN:
0.,;; ST(O) < ST(1) < +00
9. ESCAPE bit pattern Is 11011.
4-75
10-16
82284
CLOCK GENERATOR AND READY INTERFACE
FOR iAPX 286 PROCESSORS
. (82284, 82284-6)
• Generates System Clock for iAPX 286
Processors
• 18-pin Package .
• Single
• Uses Crystal or TTL Signal for Frequency
Source
+ 5V Power Supply
• Generates System Reset Output from
. Schmitt Trigger Input
• Provides Local READY and MultiblJs*
READY Synchronization
• Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range
~
The 82284 is a clock generator/driver which provides clock signals for iAPX 286 processors and support components. It also contains logic to supply READY to the CPU from either asynchronous or synchronous sources and
synchronous RESET from an asynchronous input with hysteresis.
RESET
D
RESET
SYNCHRONIZER
X1
--l--r-::--,
I L=-J
ClK
X2-
EFI-+-----'
Fie
-+--------'
ARDYEN -+--or~
ARDY -+--d.~
SRDYEN
-+--us is a patented bus of Intel
Intel Corporation Assumes No Responsibility for the Use of Any CircUItry Other Than CircUitry Embodied In an Intel Product. No Other CirCUit Patent Licenses are Implied
© INTEL CORPORATiON 1982
4-76
NOVEMBER 1983
Order Number 210453 002
M
intJ
'82284
Table1. Pin Description
The following pin function descriptions are for the 82284 clock generator.
Typtl
Symbol
ClK
a
Fie
I
X1,X2
I
EFI
I
PClK
a
ARDYEN
I
ARDY
I
SRDYEN
I
SRDY
I
READY
a
SO,'S1
I
RESET
a
RES
I
",
Vee '
GND ~
Name and Function
SYltem Clock Is the signal used by the processor and support.devlces which must be synchronous with the processor. The frequenby ,of the ClK output, has twice the desired Internal processor clock frequency. CLK can drive both TIL and MaS level inputs.
_
FrequencyiCrylle1 Select Is a strapping option to select the source for the ClK output. When
F!C is strapped lOW, the Internal crystal oscillator drives CLK. When FIC Is strapped HIGH,
the EFllnput drives the CLK output.
.
Cry,talln are the pins to "1'hlch a parellel resonant fundamental mode crystal]s attached for
the Internal oscillator. When FIC Is lOW, the internal oscillator will drive the ClK output at the
crystal frequency. The crystal freq~ency must be twice the desired Internal processor clock'
frequency.
External Frequency In drives ClK when the FIC Input Is strapped HIGH. The EFllnput frequency must be twice the desired internal processor clock frequency.
Pertpheral Clock Is an output which provides a 50% duty cycle clock with 1/2 the frequency of '
CLK. PlCK will be in phase With the internal processor clock following the first bus cycle after
the processor has been reset.
'
A~ynchronous Ready Enable is an active lOW Input which qualifies the ARDY InPt.
A DYEN selects ARDY as the source of ready for the current bus CYCle. Inputs to ARDY N
may be applied asynchronously to ClK. Setup and hold times are given to assure a guaranteed
response to synchronous inputs.
Asynchronous Ready is an active lOW input used to terminate the current bus cycle. The
ARDY input 1$ qualified by ARDYEN. Inputs to ARDY may be applied asynchronously to ClK.
Setup and hold times are given to assure aguaranteed response to synchronous Inputs.
:~nchronous Ready Enable is an active lOW input which qualifies SRIDY. SRDYEN selects
DY as the source for READY to the CPU for the current bus cycle. Setup and hold times
must be satisfied for proper operation.
Synchronous Ready is an active lOW Input used to terminate the current bus cycle. The SRDY
input is qualified by the SRDYEN input. Setup and hold times must be satisfied for proper operation.
R~adY is an active lOW output which ~nals the current bus cycle is to be completed'., The
S DY, SRDYEN, ARDY, ARDYEN, Sf, S and RES inputs control REAdy as explained later in
the READY generator section. READY is an open collector output requiring an external.300
ohm pullup resistor.
Status inputs prepare the 82284 for a su~t bus cycle. 'SO and S1 synchronize PClK to
the internal processor clock and control READY. These inputs have pullup resistors to keep'
them HIGH if nothing is driving them. Setup and hold times must be satisfied for proper oper"
ation.
R'set is an active HIGH output which is derived from the RES input. RESET is used to force the
system into an initial state. When RESET is a,ctive, READY will be active (lOW).
'
Reset In Is an active lOW Input which generates the system reset signal RESET. S~s to
RES may be applied asynchronously to ClK. A Schmitt trigger input is provided on E, so
that an RC Circuit can be used to provide a time delay. Setup and hold times are given to assure
a guaranteed response t9 synchronous inputs .
\,
. System Power: +5V power supply
System Ground: 0 volts
FUNCTIONAL DESCRIPTION
ready synchr.onization logic and system reset generation 10flic.
'
Introduction
Clock Generator
The 82284 generates the clOCk, ready, and reset signals required for iAPX 286 processors and support
components. Th~ 82284'is p'aekaged 'in an 18-pin DIP .
and contains a cry:stal controlled oscillator, MqS
clock generator, peripheral clock generator; Multlbus
The plK outPut provides the basic timing control for'
an'iAPX 286 system. ClK has output characteristics
sufficient to. drive MOS devices. ClK is generated' by
either an 'internal crystal oscillator or an external
source as selected by the Ftc strapping option. When
,
4-77
210453-003
• AFN-007866
intJ
82284.
F(C is lOW, the crystal oscillator drives the ClK output. When FIe is HIGH, the EFI input drives theClK
output.
The 82284 provides a second clock output (PClK) for
peripheral devices. PClK is CL.K divided by two.
PClK has a duty cycle of 50% and TIL output drive
characteristics. PClKis normally synchronized to the
internal processor clock.
After reset, the PClK signal may be out of phase with
the internal processor.cloc:k. The ST and SO signals of
the first bus cycle are used to synchronize PClK to
the internal processor clock. The phase of the PClK
output changes by extending its HIGH time beyond
one system clock (see waveforms). PCLK is forced
HIGH whenever either SO or ST were active (lOW) for
the two previous ClK cycles. PClK continues to oscillate when both SO and ST are HIGH.
Reset Operation
The reset logic provides the RESET output to force
the system into a known, initial state. Whent~e FfES
input is active (lOW), the RESET output becomes active (HIGH).
is synchronized internally at the failing edge of ClK before generating the RESET output
(see wavefon:ns). Sync~ronization of the RES
input introduces a one Or two ClK delay before affect. ing the RESeT output.
m
At power up, a system does not have have a stable Vee
and ClK. To prevent spurious activity, RES should be
asserted until Vee and ClK stabilize at their operating
values. iAPX 286 processors and support components
also require the.ir RESET inputs be HIGH a minimum of
16 ClK cycles. An RC network, as shown in Figure 4,
will keep RES lOW long enough t'1 satisfy both needs.
Since the phase of the internal processor clock will
not change except during reset, the phase of PClK
will not change except during the first bus cycle after
reset.
·vcc
Oscillator
10Kn
l r
The oscillator circuit of the 82284 is a linear Pierce oscillator which requires an external parallel resonant,
fundamental mode, crystal. The output of the oscillator is internally buffered. The crystal frequency choSen should be twice the required internal processor
clock frequency. The crystal should have a typical
load capacitance of 32 pF.
• ClK
10
Vee
CJ
X2 82284
1O F
•
Figure 4. lYpical RC RES Timing Circuit
A Schmitt trigger input with hysteresis on "FiE"S assures a single transition of RESET with an RC circuit
on RES. The hysteresis separates the input voltage
level at which the circuit output switches between
HIGH to lOW from the input voltage level at which the
circuit output switches between lOW to HIGH. The
FfES HIGH to lOW input transition voltage is lower
than the "FiE"S lOW to HIGH input transition voltage.
As long as the slope of the RES input voltage remains
in the same direction (increasing or decreasing)
around the "FiE"S input transition voltage, the RESET
output will make a single transition.
ClK
iAPX286
CPU or
SUPPORT
910,
COMPC;>NENT
II
Ready Operation
The 82284 accepts two ready sources for the system
ready signal which terminates the current bus.cycle.
Either a synchronous (SRDY) or asynchronous ready
(ARDY) source may be used. Each ready input has an
enaple (SRDYEN and ARDYEN) for selecting the type
of ready source required to terminate the current bus
! cycle. An address dec:ode~ would normally select one
of the enable inputs.
READY
READY
18
Vcr;
SEE TABLE
2 FOR
CAPAClmR
VALUES
I
82284
RES
+
X1 and.x2 are the oscillator crystal connections. For
stable operation of the oscillator, two loading capacitors
are recommended, as shown in Table 2. The .sum of
the board capacitanceand loading capacitance should
equal the values shown. It is advisable to limit stray
board capacitances (not including the effect of the
loading capacitors or crystal capacitance) to less than
10 pF between the X1 and X2 pines. Decouple Vec and
GND as close to the 82284 as possible.
Xl
11
DECQUPLlNG·
CAPACITOR
Figure 3. Recommended Crystal and mDV
Connectio~s
4-78
210453·003
AFN-007B6B
intJ
82284
READY is enabled (lOW), if either SFfi5'Y +
SRDYEN. These inputs are sampled on the falling
edge of ClK when 'Sf and 'SO are inactive and PClK is
HIGH. READY is forced active when both
and
SRDYEN are sampled as lOW.
SRDYEN = 0 or ARDY + ARDYEN = 0 when sampled by the 82284 'AEAi5Y generation logic. READY
will remain active for at least two ClK cycles.
smw
The READY output has an open-collector driver allowing
other ready circuits to be wire or'ed with it, as shown in
Figure 3. The ~ signal of an iAPX 286 system
requires an external 910 ohm ± 5% pull-up resistor. To
force the R"EADY signal inactive (HIGH) at the start of a
bus cycle, the READY output floats when either ST or 'SO
are sampled lOW at the falling edge of ClK. Two system
clock periods are allowed for the pull-up resistor to pull
the R"EADY signal to V1H • When RESET is'active, R"EADY
i,s forced active one ClK later (see waveforms).
Figure 6 shows the operation of ARm and ARDYEFJ.
These inputs are sampled by an internal synchronizer
at each falling edge of ClK. The output of the synchronizer is then sampled when PClK is HIGH. If the synchronizer resolved both the AROY and ARDYEFJ have
been resolved as active, the SRD'Y and SRDYEN' inputs
are ignored. Either ARDV or ARDYEFJ mustbe HIGH at
end of Ts (see figure 6).
READY remains active until either Sf or 'SO are sampied lOW, or the ready inputs are sampled as inactive.
Figure 5 illustrates the operation of SRIW and
liIIble 2
Crystal Frequency
82284 Crystal Loading Capacitance values
C2 Capacitance
(pin 8)
40pF
15pF
C1 Capacitance
(pin 7)
60pF
25pF
1 to8MHz
,8to16MHz
NOTE: Capacitance values must include stray board capacitance.
To
To
T,
CLK
PCLK
VI. -------.l~-----~f_--------t_--r---
ARDYEN
:;:---~---~~
READY
-~-----~
, Figure 5. Synchronous Ready Operation
4-79
210453·003
AFN-007868
82284
T,
, eLK
PCLK
READY - -_ _ _ _ _ _
~
Figure 6.
Asynchronous Ready Operation,
ABSOLUTE MAXIMUM RATINGS*
*Notice: Stresses above those listed under "Absolute
Maxmum Ratings" may cause permanent damage to
the device, This iS,a stress rating only and functional
operation of the device at these or any other conditions above those indica.ted in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device relia~ility.
ooe to 70°C
.......... -65°C to +150 o e
Temperature Under Bias ............
Storage Temperature
All Output and Supply Voltages ...... -0.5V to + 7V
All Input Voltages ............... -1.0V to + 5.5V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 1 Watt
D.C. CHARACTERISTICS
(TA =
ooe to 70°C, Vee =5V, ± 10%)
6.MHz
Sym
V1L
. V1H
V1HR
Parameter
-6
Min
8 MHz
-6
Max
Min
.S
Input lOW Voltage
Max
.S
Unit ll!st Condition
V
jnput HIGH Voltage
2.0
2.0
V
~ and EFllnput HIGH Voltage
2.6
2.6
V
VHYS
RES Input hysteresis
0.25
0.25
VOL
VOH
RESET, PClK Output lOW Voltage
" VOlR
. VOlC
·VOHC
R/::SET, PClK Output HIGH Voltage
.45
2.4
V
.45
V
2.4
READY, Output lOWVoltage
.45
.45
V
V
ClK Output lOW Voltage
.45
.45
V
ClK Output HIGH Voltage
4.0
4.0
Vc
IF
Input Forward Clamp Voltage
Forward Input Current
-1.0
IR
Reverse Input Current
50
50
Icc
C1
Power Supply Current
145
145
10
Input Capacitance
-.5
10
-1.0
-.5
IOl-5mA
IOH=-lmA
IOl-7mA
IOL -5mA
V IOH = -SOO!LA
. V' Ic--5mA
mA VF-·45V
uA VR=VCC'
mA
pF Fc -lMHz
210453-003
·4-80
,AFN-00186B
82284
A.C. CHARACTERISTICS
(TA = O°C to 70°C. Vee = 5V, ± 100/0)
to O.8V and 2.0V points of signals as Illustrated in datasheet
waveforms, unl_ oth_1se noted.
It; timings are referenced
6 MHz
-8
Peralll8ler
Sym
Min
8 MHz
-8
Max
Min
Max
Unit Test Condition
1
EFI to ClK Delay
2
EFI lOW Time
35
32
3
4
EA HIGH Time
35
eLK Period
83
28
62
5
CLKlOWTime
20
15
6
7
CLK HIGH Time
25
20
ClK Rise Time
8
ClK Fall Time
9
Status Setup Time
28
22.5
ns
Note 1
10
Status Hold Time
0
0
ns
Note 1
11
12
S'RiW or mmYEIiI Setup Time
S'RiW or SRDYEN Hold Time
ARDV or ARDYEIiI Setup Time
ARDY or ARDYEIiI Hold Time
RES Setup Time
RES Hold Time
REiIiDY Inactive Delay
25
15
ns
Note 1
0
0
ns
Note 1
5
ns
Note 1 Note 3
30
0
16
ns
Note 1 Note 3
25
16
ns Note 1 Note 3
10
0
5
5
ns Note 1 Note 3
ns at 0.8V Note 4
13
14
15
16
17
18
35
'500
30
10
10
ns at 1.5V Note 1
ns at 0.8V Note 1
ns at 2.0V Note 1
500
ns
ns at 0.6V Note 1 Note 2
10
ns at 3.8V Note 1 Note 2
ns 1.0Vto,3.5V'Note 1
10
ns 3.5V to 1.0V Note 1
READY' Active Delay
0
33
0
24
ns at 0.8V Note 4
19
PClKDelay
0
45
0
40
ns Note 5
20
RESET Delay
0
50
0
40
21
PClK lOW Time
t4-20.
22
PCLK HIGH Time
t4-20.
t4-13.
t4-13.
ns
Note 5
ns Note 5 Note 6
ns Note 5 Note 6
=
NOTE 1: ClK loadin9: C1 150pF.
NOTE 2: With the internal crystal oscillator using recommended crystal and capacitive loading, or with the EA input meeting specifications
t2, and t3. Use a parallel-resonant; fundamental mode crystal. The recommenQed crystal loading for ClK frequencies of 816MHz !'Ire 25pF from pin X1 to ground, and 15pF from pin X2 to ground. These recommended values are ± 5pF and include
all stray capacitance. Decouple Vco and GND as close to the 82284 as possible.
NOTE 3: This Is an asynchronous input. This specification Is given for testing purposes only, to'assure recognition at specific ClK edge.
NOTE 4: READY loading: 10L =7mA, CL =150pF. In system application, use 910 ohm ±5% pullup resistor to meet 80286,80286-6 and
80286-4 timing requirements.
NOTE 5: PClK and RESET loading: Q = 75pF.
NarE 6: t4 refers to any allowable ClK period.
4-81
\
210463-003
AFN-007BB8
82284
Waveforms
ClK as a Function of EFI
EFI
elK
NOTE: The EFI input LOW and HIGH times as shown are required to
guarentee the elK lOW and HIGH times shown.
RESET and READY Timing as a Function of RES
with S1 and SO HIGH
NOTE 1: This is an asynchronous Input. The setup and hold times
shown are required to guarantee the response shOwn.
NOTE 2: Tie 910 ohm ±5% pullup resistor to the READY output
READY and PClK Timing with RES HIGH
NOTE 1: This is an asynchronous input. The setup and hold times
shown are required to guarantee the response shown.
NOTE 2: Tie 910 ohm ±5% pullup resisior to the READY output
4-82
210453-003
AFN-007868
82288
BUS CONTROLLER
FOR iAPX 286 PROCESSORS
(82288, 82288-6)
• Provides Commands and Control for
Local and System Bus
• Optional Multibus· Compatible
Timing
• Offers Wide Flexibility In System
Configurations
• Control Drivers with 16 rna IOL and
3·State Command Drivers with
32 rna IOL
• Flexible Command Timing
• Single
+ 5V Supply
The Intel 82288 Bus Controller is a 20-pin HMOS component for use in iAPX 286 microsystems. The bus
controller provides command and control outputs with flexible timing options. Separate command outputs are used for memory and 1/0 devices. The data bus is controlled with separate data enable and direction control Signals.
Two modes of operation are possible via a strapping option: Multibus compatible bus cycles, and high
speed bus cycles.
3-STATE
COMMAND
STATUS
So
[
51
READY·
OUTPUTS
r;::::::::::::::;-----;::==:=:::;,
STATUS
DECODER
. M/iO
COMMAND
OUTPUT
LOGIC
VCC
eLK
INTA]
IORC
19
51
So
18
M/iO
MCE
17
DT/R
ALE
16
DEN
MB
15
CEN/AEN
CMDLY
14
CENL
MRi5C
13
INTA
MWTC
12
iOiiC
GNO
11
IOWC
Figure 2.
88228 Pin Configuration
iOWC
82288
MRDC
MWTC
CLK-+-......
CONTROL
INPUTS
CEN/AEN
CENL
CMDLY
READY
MB
Figure 1.
82288 Block Diagram
*Multibus is a patented bus of Intel.
Intel Corporation Assumes No Responsibility for the Use of Any Circuitry Other Than Circuitry Embodied tn an Intel Product. N? Other CIrcuit Patent Licenses are Implied.
©INTElCORPORATlON,1982
4-83
NOVEMBER 1983
Order Number 210471-003
82288
Table 1. Pin Description
The following pin function descriptions are for the 82288 bus controller.
'.
,Type
Name and Function
ClK
I
System Clock provides the basic timing control for the 82288 in an IAPX 286 micrO.
system. Its frequency is twice the Internal processor clock frequency. The falling edge
of this i",put Signal establishes when inputs are sampled and command and control
outputs change.
SO, S1
I
Bus Cycle Status starts a bus cycle and, along with MilO, defines the type of bus cycle.
These Inputs are active lOW. A bus cycle is started when either S'i or SO Is sampled
lOW at the falling edge of ClK. These Inputs have pullups sufficient to hold them HIGH
when nothing drives them. Setup and hold times must be met for proper operation.
Symbol
iAPX 286 Bus Cycle Status Definition
MilO
S1
SO
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
1
1
1
1
Type 01 Bus Cycle
Interrupt acknowledge
I/O Read
I/O Write
None; Idle
Halt or shutdown
Memory read
Memory write
None; Idle
M/iO
I
Memory or 110 Select determines whether the current bus cycle is in the memory space or I/O
space. When LOW, the current bus cycle is in the I/O space. Setup and hold times must be met
for proper operation.
MB
I
Multibus Mode Select determines timing of the command and control outputs. When HIGH, the
bus, controller operates with Multibus-compatible timings. When LOW, the bus controller optimizes
thEl command anp control output timing for short bus cycles. The function of the CEN/AEN input
pin is selected by this Signal. This input is intended to be a strapping option and not dynamically
changed. This input may be connected to Vee or GND.
CENL
I
Command Enable Latched is a bus controller select signal which enables the bus controller to
respond to the current bus cycle being initiated. CENL is an active HIGH input latched internally
at the end of each Ts cycle. CENL is used to select the appropriate, bus controller for each bus
cycle in Ii system where the CPU has more than one bus it can use. This input may be connected
to Vce to select this 82288 for all transfers. No conlrol inputs affect CENL Setup and hold times
must be met for proper operation.
CMDLY
I
Command Delay allows delaying the start of a command. CMDLY is an active HIGH input. If sampled
HIGH, the command output is not activiated and CMDLY is again sampled lit the next CLK cycle.
When sampled LOW the selected command is enabled. If READY is detected LOW'be'ore the
command output is activated, the 82288 will terminate the bus cycle, even If AO command was
issued. Setup and hold times must be satisfied for proper operation. This input may be connected
to GND if no delays are required before starting a command. This input has no effect on 82288
control outputs.
F!EADV
I
READY' indicates the end 01 the current bus cycle. READY is an active lOW input. Multibus mode
requires at least one wait state to allow the command outputs to become active. REAO"i' m.ust be
LOW during reset, to force the 82288 into the idle state. Setup and hold times must be met for
proper operation. The 82284 drives REiiOY LOW during RESET.
.
4-84
210471-003
AFN-00787A
82288
Table 1. Pin Description (Cont.)
Symbol
Type
Name and Function
CEN/AEN
I
Command Enable/Address Enable controls the command and DEN outputs of the bus
controller. CEN/AEN inputs may be asynchronous to CLK. Setup and hold times are
given to assure a guaranteed response to synchronous inputs. This input may be con·
nected to VCC or GND.
When MB is HIGH this pin has the A8ii function. AEN is anactive LOW input which In·
dlcates that the CPU has been granted use of a shared bus and the bus controller com·
mand outputs may exit 3-state OFF and become ipactive (HIGH). AEN tilGH indicates
that the CPU does not have control of the shared bus and forces the command outputs
into 3·state OFF and DEN inaCti~OW). AEN would normally be controlled by an
82289 bus arbiter which activates
N when that arbiter owns the bus to which the bus
controller is attached.
When MB is LOW this pin has the CEN function. CEN is an unlatched active HIGH input which
allows the bus controller to activate its command and DEN outputs. With MB LOW, CEN LOW
forces the command and DEN outputs inactive but does not tristate them.
ALE
0
Address Latch Enable controls the address latches used to hold an address stable duro
ing a bus cycle. This control output Is active HIGH. ALE will not be issued for the halt
bus cycle and is not affected by any of the control inputs.
MCE
0
Master Cascade Enable signals that a cascade address from a master 8259A interrupt
,controller may be placed onto the CPU address bus for latching by the address laiches
under ALE control. The CPU's address bus may then be used,to broadcast the cascade
address to slave interrupt controllers so only one of them will respond to the interrupt
acknowledge cycle. This control output is active HIGH. MCE is only active during interrupt acknowledge cycles 'and is not affected by any control input. USing MCE to enable
cascade address drivers requires latches which save the cascade address on the falling
edge of ALE,
DEN
0
Data Enable controls when data transceivers connected to the local data bus should
be enabled. DEN is an active HIGH control output. 'DEN is delayed for write cycles kn
the Multibus mode.
DTiR
0
Data Transmit/Receive establishes the direction of data flow to or from the local data
bus. When HIGH, this control output indicates that a write bus cycle i~being performed.
A LOW indicates a read bus cycle. DEN is always inactive when DT/R changes states.
This output is HIGH whIm no bus cycle is active. DT/R is not affected by any of the control inputs.
10WC
0
110 Write Command il'1structs an I/O device to read the data on the data bus. This command output is active LOW. The MB and CMDLY inputs control when this output
becomes active. READY controls when it becomes inactive.
10RC
0
110 Read Com'mand instructs an I/O device to place data onto the data bus. This command output is active LOW. The MB and CMDLY inputs control when this output
becomes active. READY controls when it becomes inactive.
MWTC
0
Me~ory
Write Command instructs a memory device to read, the data on the data bus.
This command output is active LOW. The MB and CMDLY inputs control when this output becomes active. READY controls when it becomes inactive.
MRDC
0
Memory Read Command instructs the memory device to place data onto the data bus.
This command output is active LOW. The MB and CMDLY. inputs control when this output becomes active. READY controls when it becomes inactive.
INTA
0
Interrupt Acknowledge tells an interrupting device that its interrupt request is being
acknowledged. This command output is active LOW. The MB and CMDLY inputs control when this output becomes active. READY controis when it becomes inactive.
,
,
VCC
GND
System Power:
+ 5V
,
power supply
,
System Ground: 0 volts
210471-003
4-85
AFN.Q0787A
inter
82288
from driving the shared bus command and data'
signals except when enabled by anex~e,nal bUS
. arbiter such as the 82289.
FUNCTIONAL DESCRIPTION
'Introduction
The 82288 bus' controller is used in iAPX 286
systems to provide 'address latch control, data
transceiver control,' and standard level·type com·
mand outputs. The command outputs are timed
,and have sufficient drive capabilities for large TTL
buses 'and meet' all IEEE·796 requirements for
Multibu8. A special Multibus mode is provided to
'statisfy all address/data setup and hold time reo
quirements. ,Command timing may be tailored to ,
special needs via a CMDlY input to determine the
start of a command and READY to determine the
end of a co.mmand.
_ Connection to multiple buses are supported with'
a late !led enable input (CENl). An, address
decoder can determine which, If any, b,us con·
troller should be enabled for the bus cycle. This
input is latched to allow an address decoder to
take full /ldvantage of the pipelined timing on the
iAPX 286 local bus.
Buses sha'red by several bus controllers are supported. An AEN input prevents the bus controller,
Separate DEN and OT/R outputs control the data
transceivers, for all, buses. Bus c,ontention is
eliminated by disabling DEN before changing
DT/R. The DEN ~Iming allows sufficient time for
tristate bus drivers to enter 3·state OFF before
enabling other drivers onto the same bus.
The term CPU refE/rs to. any iAPX 286 processor or
iAPX 286 support component which may become
an iAPX286 local bus master and thereby drive the
82288 status inputs.
Processor Cycle Definition
Any CPU which drives the local bus uses an. internal
clOCk which is one half the frequency of the system
clock (ClK) (see Figure 3). Knowledge of the phase
of the local ,bus master internal clock is required for
proper operation of,the 'iAPX 286 local bus. The local
bus master informs the bus controller of its internal
clock phase when it: asserts the status signals. Status
signals are always asserted beginning in Phase 1 of
. the local bus master's internal clock.
ONE PROCESSOR CLOCK CYCLE
I - - - - O N E BUS T STATE--,---.-+l
VeH
VeL
CLK
11
...-...----+""
82284
(FOR REFERENCE)
Figure,3.
POLK
'
ClK Relationship to the Processor,Clock and Bus T·States
4-86
210471-003
AFN.()Q78,7A
intJ
82288
Bus State Definition
Bus Cycle Definition
The 82288 bus controller has three bus states (see
Figure 4): Idle (TI) Status (Tsl and Command (Td.
Each bus state is two ClK cycles long. Bus state
phases correspond to the internal CPU processor
clock phases.
The 51 and SO inputs signal the start of a bus cycle. When either input becomes lOW, a bus cycle
is started. The T5 bus state is defined to be the two
ClK cycles during which either 51 or 50 are active
(see Figure 5). These inputs are sampled by the
82288 at every failing edge of ClK. When. either 51
or stl are sampled lOW, the next ClK cycle is considered the second phase of the internal CPU clock
pycle.
The TI bus state occurs when no bus cycle Is currently active on the iAPX 286 local bus. This state
may be repeated indefinitely. When contro,! of the
local bus is being passed between masters, the
bus remains In the TI state.
The local bus enters the Tc bus state after the T5
state. The shortest bus cycle may have one T5 state
and one Tc state. longer bus cycles are f9rmed by
repeating Tc states. A repeated Tc bus state is
called a wait state.
The READY input determines whether the current
Tc bus state is to be repeated. The. Rt:AuY input
has the same timing and effect for all bus cycles.
READY is sampled at the end .of each Tc bus state
to see if it is active. If sampled HIGH, the Tc bus
state is repeated, This is called inserting a wait
state. The control and command outputs do. not
change during w/!-it state~
When READY is sampled lOW, the current bus cycle is terminated. Note that the bus controller may
enter the T5 bus state directly from Tc if the status
lines are sampled active at the next falling edge of
CLK.
.
READY
NEW CYCLE
Figure 4.
82288 Bus states
veH
ClK
Vel
51-Sli V'H
FROM
CPU VIL
Figure 5.
Bus Cycle Definition
4-87
210471-003
AFN-Q0787A
$2288
Ta~le
2. Command and Control Outputs for
Type of
Bus Cycle
MIlO
S.1
SO
Interrupt Acknowledge
Memory Write
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
None; idle,
1
1
1
I/O Read
1/0 Write
None; idle
Halt/Shutdown
Memory Read
Operating Modes
Two types of buses are supported by the 82288:
Multibus and non·Multibus.. When theMS input is
strapped HIGH, Multibus timing is used. In
Multibus mode, the 82288 delays command and
data activation tq meet IEEE·796 requirements on
address to command active and write data to com·
mand active setup timin'C. Multibus mode requires
at least one wait state in the bus cycle since the
command outputs are delayed. The non·Multibus
mode does not delay any outputs and does not require wait states. The MS input affects the timing
of the command and DEN outputs.
Eac~
Command.
Activated
Type of Bus Cycle
DT/R
State
ALE,DEN
Issued?
MCE
Issued?
INTA
LOW
YES
10RC
10WC
LOW.
HIGH·
HIGH
YES
YES'
YES
NO
NO
NO
NO
HIGH
LOW
NO
NO
YES
HIGH
HIGH
YES
NO
NO
NO
NO
None
None
MRDC
MWTC
'None
•
Sus cycles come in three forms: read, write', and
halt. Read bus cycles include memory read, 110
read, and interrupt acknowledge. The timing of the
associated read command outputs (MRDC, 10RC,
and INTA), control outputs (ALE, DEN, DT/R) and
control inputs (CEN/AEN, CENL, CMDLY, MS, and
READY) are identical for all read bus cycles. Read
, cycles differ only in which command output is activated. The MCE control output is only asserted
. during interrupt acknowledge cycles.
Write bus cycles activate different control and
command outputs with different timing than read
bus cycl·es. Memory write and ~O write are write
bus cycles whose timing for ~ommand outputs
(MWi'C and iOWC), control outputs (ALE, DEN,
DT/R) and control inputs (CEN/AEN, CENL, CMDLY,
MS, and READY) are identical. They differ only in
which command output is activated.
Command and Control Outputs
The type of bus cycle performed by the local bus
master is encoded in the M/iO, 51, and SO inputs.
Different command and control outputs are activated depending on the type of bus cycle. Table 2
indicates the cycle decode done by the 82288. and
the effect on command, DT/R, ALE, DEN, and MCE
outputs.
Halt bus cycles are different because no command
or control output is activated. All control inputs are
ignored until the next bus cycle is started via 51
and SO.
210471-003
4-88
AFN-00787A
intJ
82288
I
Figures 6-10 show the basic command and control
output timing for read and write bus cycles. Halt
bus cycles are not shown since they activate no
outputs. The basic idle-read-idle and idle-write-idle
bus cycles are shown. The signal label CMD
represents the appropriate command output for
the bus cycle. For Figures 6-10, the CMDLY input is
connected to GND and CENL to Vee. The effects of
CENL and CMDLY are described later in the section on control inputs.
I----READ BUSCYCLE----+j
T,
I
T.
I
Te
I
T,
ClK
AlE _ _ _ _--J
Figures 6, 7 and 8 show non-MuJtibus cycles. MB is
connected to GND while CEN is connected to Vee·
Figure 6 shows a read cycle with no wait states while
Figure 7 shows a write cycle with one wait state. The
READY input is shown to illustrate how wait states
are added.
DEN
_ _ _ _ _ _+---J
CMD-------~
Figure 6_
T,
I"
WRITE BUS CYCLE
Te
Ts
Idle-Read-Idle Bus Cycles with MB = 0
IWAIT~ATE
::::::I
I
T,
ClK
AlE _ _ _ _ _1"
DEN _ _ _ _ _J
VOH
DTIR
-------i------+------;-------
CMD ------~~
Figure 7_
lelle-Write·ldle Bus. Cycles with MB
4-139
=0
210471-003
AFN'()0787A
,
82288
. Bus cycles can occur back to back.wlth no T, bus
states between Te and Ts. Back to back cycles do
not affect the timing of the command and control
outputs. Command and control outputs always
reach the states shown for the same clock edge
(within Ts, Te, or following bus state) of a bus cycle.
.. ~IQ)W~OO©~ DOOIP@OOIMl~il'D@OO
. 1ST WRITE CYCLE
-1-
2ND WRITE CYCLE
I
Tc
T.
I.
To
CLK
A special case in control timing occurs for back to
back write cycles with MB = O. In this case, DTtR
al1d DEN remain HIGH between the bus cycleS'(see
Figure 8). The command and ALE output timing
does not change.
i1.i!ii---f"""'\
Figures 9 and 10 show a Multibus cycle with
MB=1. Ael and'CMDLY are connected to GND.
The effects of CMDLY and AEN ate described later
in the section on control inputs. Figure 9 shows a
read cycle with one wait state and Figure 10 shows
a write cycle with two. wait states. The second wait
state of the write cycle is shown only for example
purposes and Is not required. The READY input is
shown to Illustrate how wait states are added.
V~
+-_______4-
__
DEN
v~
_.....,.+-_______+_
DT/iii
CMD _ _ _.J
Figure 8.
Tc
To.
Write·Wrlte Bus Cycles with MB
=0
T,
Tc
elK
• AlE _ _ _ _.....J
DEN
-------\--1-'
DT/II-------T"""\.\
Figure 9. . Idle·Read·ldle Bus Cycles with MB
4-90
=1
210471-003
AFN.Q0787A
inter
82288
T,
To
Tc
Tc
Tc
T,
ClK
!1.§lj--""'\
AlE _ _ _ _ _.J
DEN _ _ _ _ _ _ _ _
~
Figure 10.
Idle-Write-Idle Bus Cycles with MB = 1
The MB control input affects the timing of the command and DEN outputs. These outputs are
automatically delayed in Multibus mode to satisfy
three requirements:
Back to back bus cycles with MB = 1 do not
change the timing of any of the command or control outputs. DEN always becomes inactive between bus cycles with MB = 1.
1),,5G ns minimum setup time for valid address
before any command output becomes active.
Except for a halt or shutdown bus cycle, ALE will
be issued during the second half of Ts for any bus
cycle. ALE becomes inactive at the end of the Ts
to allow latching the address to keep it ,stable during the entire bus cycle. The address outputs may
change during Phase 2 of any Te bus state. ALE is
not affected by any control input.
2) 50 ns minimum setup time for valid write data
before any write command output becomes ac·
tive.
3)65 ns maximum time from when any read command becomes inactive until the slave's read
data drivers reach 3-state OFF.
Figure 11 shows how MCE is timed during interrupt acknowledge (INTA) bus cycles. MCE is one
CLK cycle longer than ALE to hold the cascade
address from a master 8259A valid after the falling
edge of ALE. With the exception of 'the MCE con·
trol output, an INTA, bus cycle is identical in timing to a read bus cycle. MCE is not affected by any
control input.
Three signal transitions are delayed by MB = 1 as
'
compared to MB = 0:
1)The HIGH to LOW transition of the read command 'outputs (IORC, MRDC, and INTA) are
delayed one CLK cycle.
2) The HIGH to LOW transition of the write command outputs (IOWC and MWTC) are delayed
two CLK cycles.
3)The LOW to HIGH transition of DEN for write
cycles is delayed one CLK cycle.
4-91
210471-003
AFN-00787A
82288
T.
Tc
ClK
ALE - - - - ' t -....
Figure 11.
MCE Operatl,on for an INTA Bus Cycle
Control Inputs
The control inputs can alter the basic timing of
command outputs, allow interfacing to multiple
buses, and share a bus between different
masters. For many iAPX 286 systems, each CPU
will have more than one bus which may be used to
perform a bus cycle. Normally, a CPU will only
have one bus controller active for each bus cycle.
Some buses may be shared by more than one CPU
~i.e. Multibus) requiring only one of them use the
bus at a time.
Systems with multiple and shared buses use two
control input signals of tbe 82288 bus controller,
CENL and AEN (see Figure 12). CENL enables the
bus controller to control the current bus cycle.
The AEN input prevents a bus controller from driving its command outputs. AEN HIGH means that
another bus controller may be driving the shared
bus.
In Figure 12, two buses are shown: a local bus and
a Multibus. Only one bus is used for each CPU bus
cycle. The CENL inputs of the bus controllers
select which bus controller is to perform the bus
cycle. An address decoder determines which bus
to use for each bus cycle. The 82288 connected to
the shared Multibus must be selected by CENL
and be given access to the Multibus by AEN.
before it will begin a Multibus operation.
CENL must be sampled HIGH at the end of the Ts
bus state (see waveforms) to enable the bus controller to activate its command and control outputs. If sampled LOW t~ commands and DEN
will not go active and DT/R will remain HIGH, The
bus controller will ignore the CMDLY, CEN, and
READY inputs until another bus cycle is started
via S1 and ~. Since an address decoder is commonly used to identify which bus is required for
each bus cycle, CENL is latched to avoid the need
for latching its input.
The CENL' input can affect the DEN control output. When MB=O, DEN normally becomes active
during Phase 2 of Ts in write bus cycles. This transition occurs before CENL is sampled. If CENL is
sampled LOW, the DEN output will be forced LOW
during Tc as shown in the timing waveforms.
When MB = 1, CEN/AEN becomes AEN. AEN controls when the bus controller command outputs
enter and exit 3-state OFF. AEN is intended to be
driven by a bus arbiter, like the 82289, which
assures only one bus controller is driving the
shared bus at any time. When AEN makes a LOW
, to HIGH transition, the command outputs immediately enter 3-state OFF and DEN is forced Inactive. An inactive DEN should force the local
data transceivers connected tei the shared data
bus into 3-state OFF (see Figure 12). The LOW to
HIGH transition of AEN sho~ld only occur during
T" or Ts bus states.
The HIGH to LOW transition of AEN signals that
the bus controller may now drive the shared bus
command Signals. Since a bus cycle may be active or be in the process of starting, AEN can
become active during any T-state. AEN LOW immediately allows DEN to go to the appropriate
, state. Three CLK edges later, the command outputs will go active (see timing waveforms). The
Multibus requires this delay for the address and
data to be'valid on the bus before the commands
become active.
When M B = 0, CEN/AEN becomes CEN. CEN is an
asynchronous input which immediately affects
the command and DEN outputs. When CEN
makes a HIGH to LOW transition, the commands
4-92
210471-003
AFN.Q0767A
inter
82288
and DEN are immediately forced inactive. When
CEN makes a LOW to HJGH transition, the com·
mands and DEN outputs immediately go to the
appropriate state (see timing waveforms). READY
must stili become active to terminate a bus cycle
if CEN remains LOW for a selected bus controller
(CENL was latched HIGH).
Some memory or 1/0 systems may require more
address or write data setup time to command ac·
tive than provided by the basic command output
timing. To prQvide flexible command timing, the
CMPLY input can delay the activation of com'·
mand outputs. The CMDL Y input must be
sampled LOW to activate the command outputs.
CMDLY does not affect the control outputs ALE,
MCE, DEN, and DT/A.
rD~
XI
READY
X2
8RDY
~
ClK
XACK
ARDY
SiiiiYeN
82284 - ARDYEN
9100",~
iiEAiiY ii, so
READY
CMD
¢::: CMD 82288
ClK 82288
MIlo
51,SO
CENl
MB
CEN
J,
+!v
COMM ANDS
READY
ClK
\
I-
,.
so
V-
DTIR
ALE
CENl
AEN
!
Jv
READY
~
-)
DEN
MIlo
81.
MB
I
CMD
AEN
CONTROl
ClK 82289
ADDRESS
MIlo
81,SO
DECODER
CNTl
SYSlRE8B
ADDRESS
DATA
n
MIlO
so
ii
/sTi"
2OKO
J'O
+5V
I
~
ADDRESS
t8283
II
A...
,...,
L
V
II
ClK
READY
MIlO
51,SO
/
l~
OE
r---
80288
!-- ~
D,..
DATA
)
8287
V
Figure 12. System Use of AEN and CENL
4-93
210471-003'
AFN.Q0787A:
82288
CMDLY is first sampled on the falling edge of the
CLK ending Ts. If sampled HIGH, the command
output is not activated, and CMDLY is again
sampled on the next falling edge of CLK. Once
sampled LOW, the proper command output
becomes active immediately if MB = O. If MB = 1,
the proper command goes active no earlier than
shown in Figures 9 and 10.
To find the timing specification for a signal transition in a particular mode, first look for a special
case in the waveforms. If no special case applies,
then use a timing specification for the same or
related fUnction in another mode.
ABSOLUTE MAXIMUM RATINGS·
READY can terminate a bus cycle before CMDLY
allows a command to be isSued. In this case no
commands are issued and the bus controller will
deactivate DEN and DTfR in the same manner as if
a command had been issued.
Ambient Temperature Under Bias .... O·C to 70·C
Storage Temperature ......... - 65·C to + 150·C
Voltage on Any Pin with
Respect to GND ........ : ...... - O.5V to + 7V
Power Dissipation ...................... 1 Watt
Waveforms Discussion
'NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only
and functional operation of the device at these or
any other conditions above those indicated in the
operational sections of this speeification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
The waveforms show the timing relationships of inputs and outputs and do not show all possible transitions of all Signals in all modes. Instead, all
Signal timing relationships are shown via the
general cases. Special cases are shown when
needed. The waveforms provide some functional
descriptions of the 82288; however, most functional descriptions are provided in Figures 5
through 11.
D.C. CHARACTERISTICS (TA ~ DOC 10 lO°C, Vee ~ 5V, ±10%)
6 MHz
8MHz
Parameter
-6
Min.
VIL
Input LOW Voltage
-.5
.8
V,IH
Input HIGH Voltage
2.0
Vee +.5
2.0
Vee +.5
VILe
ClK Input lOW Voltage
-.5
.6
-5
.6
V
VIHC
ClK Input HIGH Voltage
3.8
Vce +.5
3.8
Vee +.5
V
VOL
Output lOW Voltage
Command Outputs
Control Outputs
.45
.45
V
V
IOL
IOL
~
V
V
IOH
IOH
~
-5
rnA
VI
Symbol
VOH
Output HIGH Voltage
Command Outputs
Control Outputs
-6
Max.
Min.
Max.
Units
-.5
.8
V
V
.45
.45
2.4
2.4
2.4
24
Test Conditions
32mA Note 1
16mA Note 2
~
~
- 5mA Note 1
-lmA Note 2
If
Input Current (SO and Sl inputs)
-5
IlL
Input leakage current (all
other inputs)
±10
±10
"A
OV:s VIIN:s Vee
ILO
Output leakage Current
±10
±10
~A
.45V :s VOUT :s Vee
Icc
Power Supply Current
100
100
rnA
CeLK
ClK Input Capacitance
12
12
pF
Fe
~
1 MHz
CI
Input CapaCitance
10
10
pF
Fe
~
1 MHz
Co
InpuVOutput CapaCitance
20
20
pF
Fe
~
1 MHz
~
.45V
NOTE: 1. Command Outputs are INTA, IORC, IOWC, MRDC, MWRC.
2. Control Outputs are DT/A, DEN, ALE and MCE.
4-94
210471-003
AFN·00787A
inter
82288
A.C. CHARACTERISTICS
(TA = O°C to 70°C, Vcc = 5V, ±10%)
AC timings are referenced to O.BV and 2.0V points of signals as illustrated in data sheet waveforms, unless otherwise noted.
6 MHz
Sym
Parameter
BMHz
-6
Min.
-6
Max.
Min.
Max.
Unit
Test Condition
1
ClK Period
83
250
62
250
ns
2
ClK HIGH Time
25
235
20
235
ns
at 3.8V
3
ClKlOWTime
20
225
15
230
ns
at 0.6V
4
ClK Rise Time
10
10
ns
1.0Vto 3.5V
5
ClK Fall Time
10
10
ns
3.5Vto 1.0V
6
MilO and Status Setup Time
28
225
7
MilO and Status Hold Time
0
0
ns
8
CENL Setup TIme
30
20
ns
9
ns
CENl Hold TIme
0
0
ns
10
READY Setup Time
50
38.5
ns
11
READY Hold Time
35
25
ns
12
CMDlY Setup Time
25
20
ns
13
CMDlY Hold Time
0
0
ns
14
AEN Setup Time
30
25
ns
Note 3
15
AEN Hold Time
0
0
ns
Note 3
16
ALE, MCE Active Delay from ClK
3
15
ns
Note 4
17
ALE, MCE Inactive Delay from ClK
35
20
ns
Note 4
18
DEN (Write) Inactive from CENl
35
35
ns
Note 4
19
DTIR lOW from ClK
40
20
ns
Note 4
20
DEN (Read) Active from DT/R
10
50
10
40
ns
Note 4
21
DEN (Read) Inactive Diy from ClK
3
40
3
35
ns
Note 4
22
DTIR HIGH from DEN Inactive
5
45
10
40
ns
Note 4
23
DEN (Write) Active Delay from ClK
30
ns
Note 4
24
DEN (Write) Inactive Diy from ClK
30
ns
Note 4
25
DEN Inactive from CEN
40
25
ns
Note 4
26
DEN Active from CEN
35
25
ns
Note 4
27
DT/R HIGH from ClK
(when CEN = lOW)
50
50
ns
Note 4
28
DEN Active from AEN
35
30
ns
Note 4
29
CMD Active Delay from ClK
3
40
3
20
ns
Note 5
30
CMD Inactive Delay from ClK
3
30
3
20
ns
Note 5
31
CMD Inactive from CEN
35
25
ns
Note 5
32
CMD Active from CEN
45
25
ns
Note 5
33
CMD Inactive Enable from AEN
40
40
ns
Note 5
34
CMD Float Delay from AEN
40
40
ns
Note 6
NOTE: 3.
4.
5.
6.
25
3
35
3
35
3
I
AEN and MB are asynchronous inputs. This specification is for testing purposes only, to assure recognition at a specific ClK edge.
Control output load: CI = 150pF.
Command output load: CI = 300pF.
Float condition occurs when output curre~t is less then ILO in magnitude
.4-95
210471-008
AFN'()0787A
I
•
82288
WAVEFORMS
•
ClK CHARACTERISTICS
ClK
STATUS, ALE, MCE, CHARACTERISTICS
14---- Ta-_of+----Tc-CLK
MliO,ii,so - - - + = . I
AlE _ _--....,_ _ _+.:!
MCE _ _ _ _ _ _- - I
CENl, CMDlY, DEN CHARACTERISTICS WITH MB = 0 AND CEN = 1 DURING WRITE CYCLE
ClK
DEN_...,......_ _+-'
CENl
4-96
210471-003
AFN-007lI7A
82288
WAVEFORMS (Continued)
READ CYCLE CHARACTERISTICS WITH MB = 0 AND CEN = 1
ClK
DT/ii---+~
DEN _ _-+=--J
CENl
WRITE CYCLE CHARACTERISTICS WITH MB=O AND CEN=1
ClK
DEN._ _ _ _ _ _J
vOH---------+f--+----II~-__t.......- - - - -
DT/ii
CENl
4-97
210471-003
AFN.Q0787A
82288 '
WAVEFORMS (Continued)
CEN CHARACTERISTICS WITH MB =0
ClK
CEN
DEN
-+-J
DT/R _ _ _ _ _ _ _ _ _ _ _ _ _ _
II
KEN CHARACTERISTICS WITH
MB = 1
CLK
m
DEN _ _ _J
'NOTE 1:
AErii
Is an asynchronous input. ill setup and hold time Is specified to guarantee the response shown in the waveforms.
\,
4-98
210471-003
iAPX432
Micromainframe™
Microprocessors
Section
5
I'{
0"
r
,.
I
,t.
/
intJ
iAPX 43201/iAPX 43202
FAULT TOLERANT GENERAL DATA PROCESSOR
• Memory Management Support On-Chlp
• Symmetrical Instruction Set for all 8-,
18-, and 32-b1t Data Types
• Range of Performance
- Adding Processors Increa...
Performance
- No Software Changes Required
• IEEE Standard 32-, 64-, and 8O-Bit
FIoaUng-Polnt Operations
• Large Add,... Space:
- 16 Megabytes Physical Memory
- 1 Terabyte Virtual Memory
• Master/Checker Pairs Detect Hardware
Errors Automatically
• Capability-Based Addressing for
Maximum Dependability
- Most Software F~ults Trapped
Before Damage Occurs
- Debugging nme Reduced
- Leads to Highly-Reliable, Robust
Systems
• Quad Modular Redundancy Ensures
Immediate Recovery From Hardware
Faults
The iAPX 432 Micromainframe is a 32-bit multiprocessor specifically designed for those critical applications
which demand absolute software reliability or hardware fault tolerance. At the heart of the system is the iAPX
432 General Data Processor (GOP) consisting of two VLSI components, the iAPX 43201 and iAPX 43202.
Together with the other members of the iAPX 432 component family (i.e., the 43203 Interface Processor, the
43204 Bus Interface Unit, and the 43205 Memory Control Unit) the GOP can be used to build a fault-tolerant
computer system that sustain any single-point failure and yet continue to operate correctly, without interrup-
tion.
Intel 432 systems offer a range of performance: by adding or removing GOPs, the throughput of a 432-based
product can be increased to support more users or reduced to save hardware cost with no change to software.
Thus, a family of end products with differing levels of performance can be developed from identical hardware
modules using the same software.
The iAPX.43201 and iAPX 43202 are fabricated with Intel's highly reliable +5-Volt, depletion load, N-channel,
silicon gate HMOS technology and each is housed in a 68-pin JEOEC Type A package. See Figures 1 and 2.
....
-
....
~~!¥9~~!lllilll!~
-
,hllil!!lua
~9h!~¥
IOC,
m
IOC
He
OOUT
ICS
IOC
-].
vee
¥IS
..,
I
pUI~n¥¥
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i
¥HU¥!g'
PlUO.'......
II01E: N.C. podo ..... not be comocIad.
171873-1
L . . I_ _ _
,
Figure 1. 43201 Pin AssIgnment, Instruction
DecoderIMlcroinstructlon Sequencer
Figure 2.
I!¥
PtN NO.1
,I
~
171873-2
43202 Pin Assignment, Execution Unit
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied.
November 1983
@1nt8lCorporation, 1983.
Order Number: 171873-002
5-1
IAPX 43~1I1APX 43202
.'.,
"
Table 1 summarizes all signal groups, signal names and their active states, and whether br not they are
monitored by the Hardware Error Detection circuitry.
.
, Table 1. Pin Description
.
Type
Name and Function
Symbol
Processor Packet Bus Group
Add...../Control/Data Un..: These 16 bidirectional
I/O
AC015
signals carry physical memory addresses, control information
ACOo
(access length and type), and data to and from the memory bus.
PRO
0
,
ICS
I
BOUT
0
Whe~ the GOP is in checker mode, the ACO pins are monitored by
the hardware error detection logic and are in the high impedance
state.
Processor Packet Bus Request: is issued to gain access to the
bus. Normally low, the PRO pin is brought high during the same
cycle as when the first double-byte of address information appears
on the ACO pins. PRO remains high for only one cycle during the
access, unless an address development fault occurs. In that case,
the GOP leaves PRO high for a second cycle to indicate it has
detected an addreSSing or segments rights fault in completing the
, address generation.
,PRO is checked by the hardware detection logic and remains in a
high impedance mode when the GOP is in checker mode.
Interconnect Status: carries information on errors" data
synchronization, and interprocessor communication. The
interpretation of this signal depends on the current cycle of the bus
transaction. See page 39 for a complete description.
Enable Buffers for Output controls the direction of external
buffers, if any are used. When BOUT is assert9d, it indicates that the'
buffers must be directed to carry information outbound from the
. GOP.
System Group
Vee
I
Vss
I
Ar:AFm
I
FATAL
0
Pro<
I
Power: These four pins supply 5-volt pow~r to the GOP, and all
must be connected; the pins are not connected together within the
GOP.
Ground: These five pins provide the ground reference for the GOP,
and all must be connected; the pins are not connected together
within the GOP.
Alarm: monitors the condition of an unusual, system-wide condition
such as power failure. Alarm is sampled on the rising edge of CLKA.
Fatal: is asserted by the GOP under microcode control when the
GOP is unable to continue due to various error or fault conditions.
Once FATAL is asserted, it can only be reset by the assertion of
INIT.
' "
Processor Clock: The assertion, of PCIJ< for one cycle causes the
system timer within the GOP to decrement. Assertion of J5C[j( fQr
two or more cycles causes the system timer to be reset. PrnJ( must
remain unasserted for at least 10 clock ~cles before being
asserted again. The GOP samples PrnJ( on the rising edge of
CLKA·
>
5-2
171873.002
inter
IAPX 43201/1APX 43202
Table 1. Pin Description (Continued)
Symbol
Type
System Group (Continued)
CLR
I
Name and Function
Clear: Assertion of CLR results in a microprogram trap causing the
GOP to immediately terminate any bus transactions or internal
operAtions in progress. The GOP resets to a known state, asserts
FAT L, and awaits an IPC for initialization. The IPC is not serviced
for at least four clock cycles following the assertion of ~.
Response to CLR is disabled by the first CLR assertion and is
reenabled when the GOP receives the first IPC (or INIT assertion).
INIT
I
MASTER
I
HERR
0
,
The GOP samples CLR on the rising edge of CLKA.
Initialize: Assertion of INIT resets the internal state of the GOP and
starts execution of the initialization microcode. INIT must be
asserted for a minimum of 10 clock cycles. After the INIT pin returns
to its nonasserted state, the GOP initializes all of its internal
registers and windows, and waits for a 10ca11PC. INIT is sampled on
the rising edge of CLKA.
Master: This signal determines whether the 43202 is to function as'
a master or a checker. In master mode, the 43202 functions
normally and drives all of its outputs. In checker mode, AC015ACOo and PRO enter a high impedance state and BOUT is
unconditionally low. A 43202, whether master or checker, monitors
the AC015-ACOo and PRO lines and compares the data on them to
its internally generated result, signaling disagreement on the HERR
line. For normal operation, MASTER .should be left unconnected or
tied high.
\
CLKA
I
CLKs
I
Hardware Error: This. signal is asserted by the GOP to indicate
disagreement between data appearing on the AC015-AC~Q and
PRO pins and the internally generated result of the GOP. ERR is
valid duringCLKA and can normally be asserted~ GOP and
every clock cycle, except immediately following CLA. HERR
requires an external 2.2 k!l nominal pullup resistor.
Clock A:. is a square-wave clock which must operate continuously
to preserve the operating state of the GOP.
Clock B: is a square-wave clock whjch operates at the same
frequency as CLKA, but lags it by 90 degrees. CLKs must operate
contim,tously to preserve the operating state of the GOP.
Intra-GOP Group
156- 150
N/A
,...10-,...115
N/A
ROROM
I
Interchlp Status Lines: carry microprogram information from the
43202 back to the 43201. The lines are not checked by the
hardware detection logic.
. Microinstruction Bus Lines: carry microinstructions from the
43201 to the 43202. They are not checked by hardware detection
logic.
Read ROM: This Sign~ is used to read the microprogram from the
43201 ROM. If RORO is h.eld low when INIT goes high, the 43201
enters a diagnostic mode, and the microinstruction sequencer steps
through the microprogram ROM, sequentially displaying (but not
executing) the microinstrucvons on the ,...115-,...10 lines. While
ROROM is useful for testing, it should be tied to Vee for normal
operation.
5-3
171873.002
IAPX 432011IAPX43202
FUNCTIONAL DESCRIPTION
I
Introduction
The iAPX 432 Micromainframe is a 32-bit multiprocessor eapecially design8d for those critical applications which demand absolute software reliability or
hardware fault tolerance. By developing the 432, Intel has broken with three decades of, tradition that
have defined how computers operate, and redrawn
the line separating functions of hardware and software. Many operations that 432 processors perform
automatically Would be done by the operating system in conventional machines. The development of
the :432 was driven by two major objectives: to reduce the cost of software over the life cycle of the
product, and to develop a computer with unprecedented reliability. From any perspective,the 432 is
an uncommon machine.
Similar to many mainframe computers, processing in
the 432 is divided between a central system, which
handles data processing, and one or more peripheral subsystems, which transfer data to and from 110
devices. There are two types of processors, General
Data Processors (GOPs) and Interface Processors
(IPs), and two types of support components, Bus Interface Units (BIUs) and Memory Control Units
(MCUs). Together, these VLSI components can be
used to build a fauH-tolerant-computer system that is
able to sustain any single-point failure of a component or bus, and yet continue to operate correctly,
without program interruption and without software intervention.
This concem for reliability in the 432's design is not
limited to automatic recovery from hardware fauHs,
but extends to software as well. The 432 processors
can detect hundreds of different software fauH conditions from an attempt to divide by zero or execute
data, to complex faults involving several independent processes. While most computers do not detect these faults at all, the 432 is able to tr;ap and
identify most fauHs before serious damage can 0ccur. As a consequence, 432-based systems are easier to debug, and systems shipped to end-users will
prove substantially more reliable.
'
Another important advantage of the 432 is the ability
to tailor the throughput of the system to meet the
price/performance requireme,nts of each application
or end-user. A family of products, for example, can
be developed using' the- same hardware modules,
Simply adding or removing boards as the application'
requires. The end-user, for example, could buy an
entry-level system with only two processors. The'
system would run more slowly than the high-end
system, but it would also cost much less. Later,
when the user's needs grew, additional General
Data Processors could be installed 'to h~le the
heavier load on the system. No n8Eid to change software; all the programs that the user had developed
would still be compatible. In fact, if at any time, one
of the processors failed, the user could remove it,
and the remaining processors in the system would
continue to execute programs correctly while a replacement was sought.
'
This unprec8dented flexibility is possible only because the 432 takes a unique approach to architecture, one clO$ely tied to the structure of programs.
The processors are no longer passive entities, responding only to software, but they can execute
many functions automatically to keep the system
working efficiently and reliably.
ARCHITECTURE
This section describes the architecture of the iAPX
432; thet is, the 'machine-level programmer's view of
the computer. As a rule, only compiler writers actual-,
Iy deal with the 432 at this level; however, many applicatiEln programmers-wllo typically code in Adawill find this discussion valuable for getting a "feel"
for the operation of the underlying machine. Bear in
mind that this 'discussion does not cover all programming facilities and some of the concepts have
been simplified for the sake of clarity and space; a
complete description of the architecture can be
found in the IAPX 432 General Data Processor ArchHecture Reference Manual.
Since the 432 Is a muHiprocessor system, with specialized typ8s of Processors optimized for different
kinds of work, the architecture of the GOP is different from the Interface Processor. At the same time,
these dive,rse processors (and their associated software) must cooperate with each other to accomplish
the overall task of the 'system. Therefore, the designs of the GOP and IP share an architectural foundation, the 432' com~on base architecture. The
overall arrangement is illustrated in Figure 3.
Common Base Architecture
The common base architecture of the 432 is the
glue that binds multiple processors, of the same and
different types, together in a coherent system.
Therefore, the common base architecture defines
"global" facilities used by all processors, software,
and support components (i.e., iAPX 43204 Bus Interface Unit and iAPX 43205 Memory Control Unit).
These facilities include addressing, protection, object management, communication, timekeeping, and
exception processing.
5-4
171873-002
IAPX 43201/1APX 43202
dure-in fact, any logical entity which should be
uniquely identified and protected.
Objects
Memory protection systems can be considered in
terms of boxes into which information can be locked
and keys which can open the boxes. The 432's boxes and keys correspond to the logical units found in
many high-level programming languages (e.g., Ada,
Pascal); in other words, programming units and protection units match. Boxes are variable in size, each
box containing one obJect; the object may be an
array, a record, a list element, the text of a proce-
'
Keys in the 432 are called access descriptors and
are manifested in high level languages as pointers
(instances of access variables in Ada). Whenever
storage for a new object is allocated, whether by the
linker or program statements, the processor automatically boxes the object (in its own segment),
manufactures a unique key (access descriptor), and
returns the key to the creating procedure. A brief
introduction to objects can be found in Table 2.
t.. _ _ _ _ _ _ _ .A
ACD
ACD
IUS
Figure 3.
IUS
171873-3
A typical 432 system with two memory buses, two General Data Proceuors,
and a single peripheral subsystem for 1/0
Table 2.
Introducing Objects
1. All Information In an IAPX 432 system Is contained In objects.
_
, Even the instruction pointer, status flags, and other information used by the GOP are contained
in objects.
. 2. Each obJect can have two parts, a data part and an ace... part.
The data part can contain any information except accesses. Data in the data part can be added,
assigned, manipulated as bit fields, or used for any purpose other than accessing an object. The
access part can contain only acceaa descriptors (ADs). ADs are used for referencing objects
and can only be modified in caref~JIy controlled ways.
3~ ObJects can be created with different lengths.
An object can have from 0 to 65,536 bytes in its data part, and from 0 to 16,384 ADs in\ its access
part. Any. reference, to an object is automatically checked to ensure that it falls within the bounds
of the object.
5-5
171873-002
'\
IAPX 43201/1APX 43202
Table 2. Introducing Objects (Continued)
ty.,..
4. t:;ach object has a fixed
The type of an object is determinec;l when the object is created. An objecfs type can be used to
define the operations allowed on thfit object. Sofuv8re can define new object types at run-time.
5. Objects ,:an be local to a program or subprogram call.
,Each object is created at a particular level that specifies whether the object is global, or limited in'
scope to a particular program or subprogram activation.
6. Objects' can Qnly ,be read or written via aceess descriptors.
To acCeSs data in an object, you must speCify an AD that references the object and also specify
the offset within the objects data part to the field accessed.
7. A procedure call can only access those objects It has ADs for.
Each activation of a program or procedure is itself represented by a context object. The
instructions executed by the context can only access those objecfs for which the context has
ADs or can obtain ADs.
8. Access deScriptors can provld~ restricted access to objects.
Each AD specifies several rights bits, including read rights and write rights. To read from an
object requires read rights set on the AD used;'to write to an object requires write rights on the
AD used. Different module activations can have ADs for the same object, but with different rights.
Storage
Address Spaces There are several distinct address
spaces in a iAPX 432 system. Each peripheral subsystem, for example, has a local memory space, and
typically, a local 110 space. A portion of each Aeripheral subsystem memory space is mapped by an Interface Processor into the central system. Processors (and DMA controllers) in a peripheral subsystem can gain access to central system data by reading and writing these local mapped address spaces.
Logical addressing To operate on a data item, a
GOP instruction (or IP command) presents a logical
address as shown in Figure 4. For a GOP, a data
item is an integer, character, or real number. In the
case of an IP data transfer, such data items are simply bytes or double bytes. The logical address of a
data item consists of an access descriptor and a
displacement (offset) into that object. The several
ways of specifying these components, particularly
the displacement, give rise to the GOP's addressing
modes, Which are described in a later section.
The central' system is divided into two 16-Megabyte
physical address spaces, the mem(jrY space and
the Interconnect space. For the most part, the interconnect space consists of hardware registers
used by the Bus Interface and Memory Control Units
to maintain fault-tolerant systems. The MCU, for example, logs the number of memory errors it has detected and corrected in a register that processors
are able to read by addressing the interconnect
space.
Physical Translation GDPs translate logical addresses into 24-bit physical address; programs have
no way to generate physical addresses directly. As
shown in FigUre 5, the essence 9f the translation is
finding the physical base address of the target object ahd adding the displacement component to it.
As you'll recall, associated with each 432 prQCedure
(or function) is an object reference Ii!lt (set of keys)
called access descriptors;, this array of access de-'
scriptors defines the objects that are currently addressable by the procedu(e. The access descriptor
in tum selects an entry in an object table. This entry,
called an object deSCriptor, ,oontains the ,base address of the target Qbject.
GDPs use the instruction MOVE FROM INTERCONNECT SPACE to read these registers and MOVE TO
INTERCONNECT SPACE to write to them. Peripheral subsystem software can gain access to the interconnect space through Window 1. All other 432 instructions and commands reference, the, memory
space.
5-6
171873-002
intJ
lAP X 43201/1APX 43202
LOGICAL ADDRESS'
I
OPERAND
OFFSET
ACCESS
DESC,RIPTOR
OBJECT
ADDRESSING
r "\
SELECTED
DATA
OBJECT
171873-4
Figure 4.
Simplified View of Logical Addressing
The focal point of the translation procedure is the
object table. (Naturally, only the operating system's
memory manager has a reference to the object table
itself.) Every object in a system is represented by a
single object descriptor, which contains its base address and other descriptive information. Conversely,
there may be many access descriptors for a single
object scattered among the access descriptor lists
of all programs that have access to that object. Moving an object (to compact physical memory, for example), only requires updating its object descriptor,
regardless of how many programs hold references
to it.
Virtual Memory Support Three' fields in object descriptors aid a 432 executive's virtual memory manager. The allocated bit indicates whether real memory is associated with the object. When the virtual
memory manag,er swaps an object out to external
storage, it clears this bit first. The hardware checks
the allocated bit during address translation; if it is
clear, the hardware faults, and control, passes to the
memory manager. The memory marriager can then
swap the object back into physical rhemory, set the
allocated bit, and return control to the instruction
that faulted.
The accessed bit is set by the hardware when an
object is referenced by an instruction. By periodically
checking and clearing this bit in all object descriptors, the virtual memory manager can gain insight
into the frequency with, which each object is being'
used. This information can then be used to select
objects to be swapped out, for example, on a leastrecently-used basis.
Note that to improve performance, 432 processors
automatically maintain two groups of physi~1 addresses on chip. The addresses of frequently used
System objects, such as the object table, are always
immediately available. In addition, the processors
cache exploits the tendency of most programs to
clustertheir references to a few objects at a time.
5-7
171873-002
inter
IAPX 43201/1APX 43202
Protection and Access Control The services provided by modern operating systems typically take
the form of procedures that can be called by user
ptocesses. Since most computers do not provide
procedure-level protection as a matter of course, a
special arrangement is necessary 10 protect operating system procedures from their callers
READ RIGHTS
WRITE RIGHTS
DIRECTORY INDEX
171873-10
Figure 8. Access Descriptor Format
A type manager may define up to five rights for the
dynamic-typed object it manages. It may selectively
grant rights to a user when it creates an object and
returns the reference for it. When a type manager
receives a reference. for an object, it may compare
the rights in the reference to the operation requested by the user. The manager of a "bank account"
object, for example, may permit all users to credit
and debit bank accounts, but only a few may be
granted the >right to close an account.
Finally, the hardware performs a bounds check to
insure that the displacement component of a logical
address in fact falls within the target object. This is
done by simply comparing the displacement to the
object's length (contained in the object descriptor).
For improved performance, the hardware holds
length and rights information for frequently-used objects, as well as their physical base addresses, and
virtual memory control information, on chip.
Object Management
Reference Manipulation A procedure sometimes
needs to manipulate the entries in its access descriptor list (as opposed to the objects the list references). The common base architecture defines operations that permits copying an access descriptor
from one "slot" to another, and for nulling an access
descriptor. This last operation is used to delete the
reference to an object that is no longer needed. Another ,operation permits a procedure to inspect an
access descriptor, for example, to examine the
rights bits. A procedure may similarly inspect the object table entry indexed by an access descriptor to
see, for example, if the object is dynamic-typed (i.e.,
the entry is for a type control object, rather than an
object descriptor).
Object Cr~atlon and Deletion Free storage in central system memory is accounted for in system objects called storage resource objects, or SROs.
SRCs are lists of unallocated blocks of memory.
Given a, reference to an SRO, a procedure can create a new object dynamically; the instructions that
create new objects automatically update the SRO
from which storage is obtained.
Objects have "lifetimes": they come into being and
occupy storage, and they also disappear, giving up
their storage. The 432 common. base architecture
distinguished between short-term and long-term objects. A short-term object exists for the lifetime of
the procedure that creates it; that is, it is allocated
when the procedure is called and it is deallocated
when the procedure returns. An operand stack, for
example, is automatically created when a procedure
is called, and a procedure may create an object to
pass as a parameter to another procedure. A longterm object exists after its creating procedure retlo!rns; in fact, it lives indefinifely, until there are no
object references left for it. A type manager "create"
operation will create a long-term object.
As mentioned, short-term objects are deallocated
automatically by the hardware when the creating
procedure returns to its caller. Long-term objects are
deallocated by a software routine called a garbage
collector. This operating system routine sweeps
through memory looking for objects that no longer
have references left to them. When such an object is
found, the garbage collector reclaims the storage
occupied by the object by removing the object's descriptor from the object table and returning the storage block(s) occupied by the object to the SRO from
which it was allocated.
171873'()02
IAPX 43201/1APX 43202
Garbage collection is a complex operation; most
conventional systems let garbage accumulate until a
request for memory allocation cannot be satisfied.
Then they halt normal execution, collect garbage,
.and resume operation. To avoid this suspension of
service, the 432 architecture defines a reclamation
bit in each object descriptor. By setting the reclamation bit whenever it copies an object reference, the
hardw,are permits garbage to be collected on-the-fly,
in parallel with normal execution. The operating system performs garbage collection automatically, relieving programmers of much of the burden of storage management.
Mutual Exclusion It is perfectly possible for two
, processes to hold references for the same object
(see Figure 9, for example). If both processes only
read the object they need not coordinate their operations. Consider, however, an object that accumulates ·the total number of transactions handled by
several processes. Every so often each of these
processes adds the number of transactions it has
handled in the preceding time period to a field in this
object. Although the addition is performed in a Single
machine instruction, at least three memory accesses are required to complete the operation: 1) read
the old total; 2) read the increment; 3) write the new
total. The integrity of the total is in jeopardy when
two processes update it at nearly the same time.
The 432 has three classes of mutual exclusion
mechanisms: 110 locks, object locks, and indivisible
operations. Each object's storage descriptor contains a bit called the 110 lock.. When an Interface
Processor opens a window on the object, it checks
to see that the object is not already liD-locked, and
then it locks it for the duration of the 110 transfer.
Software running on a GOP may check for an 110
lock by inspecting an object's storage descriptor.
An object lock field may be defined for any data
object. Processes that update such an object agree
by convention not to update the object without first
locking it, and further agree to unlock the object as
soon as exclusion is no longer required. The LOCK
OBJECT is conditional: it returns a value that indicates if the object was successfully locked (i.e., was
not locked by another process). A process should
refrain from accessing the object until it successfully
locks it. In general, an object's type manager will
take care of locking and unlocking the objects it
manages, eliminating the need for object users to
know anything about locks.
Note that a processor locks a 432 system object
when it needs exclusive access to it during the execution of a high-level operation. This prevents another processor, or. an executive routine, from interfering with a critical operation on the object.·
PROCESS
A
PROCESS
B
1
1
1
DATA
OBJECT
DATA
OBJECT
DATA
OBJECT
DATA
OBJECT
1
2
3
4
!!
171873-11
Figure 9. Two processes can share access to the same object. In the figure,
both Processes A and B can access Data Object 3. In .these cases,
some mutual exclusion mechanism must be used to prevent Inconsistent updating.
5-17
171873-002
IAPl( 43201/1APX 43202
Often an object only needs to be locked for the duration of one instruction. The common base architecture defines o,*,rators that permit addition and bit
field insertion (1 to 32 bits) to be performed IndIvIsIbly. When an indivisible operator is executed, the
processor signals a read-modify-write bus cycle; the
system memory controller must not permit a second
RMW-write access to the target memory until the
updated value has been written back into memory.
Thus, the integrity of a shared value is guaranteed
so long as programs that update it do so with indivisible operations.
satile facility; it provides the basis for 1/0 operations
and process dispatching in. addition to more traditional message passing. Process communication
can also be used to implement another form of mutual exclusion.
.
A complete transmission' consists o,f' a send and a
corresponding receive. Since processes execute
asynchronously with' respect to each other, the
time at which a process desires to send a message
is unrelated to the time at which another process is
ready to receive a message. Further, the rates at
which processes send and receive are, for the most
part, unpredictable. This is in contrast to the synchronous communicatioh of procedures within the
same process, which may pass object references as
parameters in ordinary call and return operations. A
call effectively suspends execution of the caller and
starts execution of the called procedure; a return terminates the called procedure and resumes the caller. 432 interprocess communication, on the other
hand, allows the communicating processes to run
concurrently.
While a refinement is effectively a new object that is
a contiguous subset of an existing one, it actually
requires only a new access descriptor, thereby saving storage and execution time. A process with a
reference to a refinement has no knowledge of the
"underlying" refined object. The process that created the refinement, however, can "retrieve" the refined object from a reference to the refinement.
Process Communication
Except as they hold references to the same objects,
432 processes are completely independent of one
another. Two processes may execute alternately on
the same processor, or they may execute simultaneously on different processors. The 432 interprocess communication facility enables processes to '
communicate with each other by transmitting access
descriptors (as messages) through memory during
execution.
Since any object reference can be transmitted, process communication is an extremely efficient and ver-
PROCESS A
The 432 port object provides the synchronization
and buffering needed for asynchronous process
communication. Conceptually, a port is a queue; two
processes with references to the same port have a
channel over which they can communicate. A process wishing to transmit a message executes a SEND
operator, which copies the access descriptor to the
port (see Figure 10). A processes ready to obtain the
message executes a RECEIVE operator, which
moves the access descriptor at the head of the
queue to the receiver's object reference list, thereby
making the object accessible and deleting it from the
queue.
PORT
PROCEsSB
~)
§
ACCESS
DESCRIPTORS
:J
171873-12
1)
Both Process A and Process B have an access descriptor for the port. while A has an access
deSCriptor for the target object.
Figure 10. Simple Message Transmission
5-18
171873-002
inter
IAPX 43201llAPX 43202
171873-13
acce~s
2)
A sends message to port; an
descriptor for the target object is queued.
3)
B receives message from port; Processes A and B now have access to the target object.
171873-14
Figure 10. Simple Message Transmission (Continued)
When a port is created, it is given a queuing discipline, which may be first-in-first-out (FIFO), or priority/deadline. A send to a FIFO port inserts the message at the back of the queue. A send to a priority/
deadline port inserts the message according to priority and deadline parameters associated with it
(and the messages already enqueued, if any). Insertion is done so that the highest priority messages
are at the front of the queue; within a priority level,
messages with the shortest (least) deadline are
placed in front. A receive operation always takes the
message at the front of the queue.
when another process SENDs a message to that
port.
.
The simple SEND and RECEIVE operators are unconditional: they imply that the executing processes
is willing to block if the port is full (or empty). A
SEND to a full port or a RECEIVE at an empty port
enqueues a reference to the sender's process object at the port; further execution of the process is
blocked while it effectively waits at the port. When
SENDs and RECEIVEs executed by other processes
make it possible to complete the original operation,
the process is automatically unblocked and execution may resume. A process waiting at a port due-to
a blocked RECEIVE, for example, is unblocked
A port is also useful as a mutual exclusion mecha-_
nism. Processes that periodically require exclusive
access to a shared object can designate a port to
hold a single "key" to the object; the key can simply
be a null access descriptor. When a process needs
to obtain exclusive access; it does a receive operation on the port to pick up the key. (If the key is in
use, the process blocks at the port.) When it actually
receives the key, the process has' exclusive access
to the shared object. As soon as it has finished with
the object, the process sends the key back to the
port, making it available to other proces~es.
The CONDITIONAL SEND and CONDITIONAL RECEIVE operators, in contrast, never block: these operators return a value that indicates whether the operation was "successful." This signal gives the process the option of doing some other work and attempting the send or receive later. Other operators,
called SURROGATE SEND and SURROGATE RECEIVE enable even more sophisticated forms of interprocess communication.
5-19 I
171873-002
IAPX 43201/1APX 43202
Interprocessor Communication
To coordinate the actiVities of multiple processors,
all 432 processors can receive and respond to a set
of predefined messages (see Table 4). For the most
part, these messages are sent by processors on
their own initiative. System software may also send
a message to a particular processor, or may broad-'
cast a message to all processors in the system.
When a system's memory manager moves an object
or swaps it out of memory, for example, it will broadcast a "flush cache" message to all processors.
This eliminates the possibility that a GOP will reference the object with an on-chip cache address
whiCh has been made invalid by the action of the
memory manager. Sending a message to a processor requires a reference (with proper system rights)
to that processor's process object; by controlling
distribution of process object references, system
software can likewise limit the ability to send processor messages.
Table 4 contains the Interprocessor Communication
message codes in decimal along with a short description of the message:
0
Table 4.
Wakeup
1 Start
Stop
3 Accept Global IPCs
4 Ignore Global IPCs
5 Requalify Object Table Cache
Reset Processor
7 Requalify Processor
8 Requalify Process'
9 Requalify C.ontext
10 Requality Data Object Cache
11
Each GOP process object contains a clock field that
is automatically maintained by the hardware. A process clock indicates the number of system time units
that the process has been bound to a processor (i.e,
how long it has been executing). Using a 200 microsecond clock, a process clock can accumUlate over
236 hours before turning over. Process clocks can
be read by software and provide the basis for execution-time charging algorithms and for adaptive process scheduling.
Exceptions
, Software Faults Most modern computers provide a
facility for detecting errors during execution; for example, many CPUs detect arithmetic overflow or an
application program's attempt to execute a "privileged" instruction. The 432 extends this concept
into a comprehensive, structured software fault system (see Table 5).
IPC Message Codes
2
6
PClK's frequency, at thus the duration of one system unit, is set according to the resolution required
by the application; 200 microseconds is a typical value. As discussed later, the system unit provides the
basis for GOP processing and dispatching.
Enter Normal Mode
12 Enter Alarm Mode
13 Enter Reconfiguration Mode .
14 Enter Diagnostic Mode
Timekeeping
The central system runs on a Single time standard
which is reflected in the on-chip clock of every 432
processor. The on-chip clock is a 16-bit accumulator
which is driven by the PClK signal. All 432 processors are tied to PClK, which is independent of the
,component (ClKA, ClKB) clocks. When PClK is asserted by an external timing source, all processor
clocks inctement ("tick") in unison.
A software fault is an exceptional condition uncovered by a processor during execution. It may be a
simple computational error (e.g., square root of a
negative number), an attempted protection violation,
or a condition that requires off-line handling though
,not an error or violation. Whatever the source, the
architecture recognizes that normal computation
cannot continue until the exceptional condition is resolved.
The architecture defines software fault detection
and fault reporting; that is, the notification that a
fault has occurred and provision of information describing it. Software fault handling, which may include fault recovery in many cases, is the province
of application or-more frequently-system soft• ware. A software fault may be detected at any time:
dunng the execution of an instruction or command,
while a processor is performing an operation on its
own initiative, during an IP data transfer, and, so
forth. A processor reports a software fault by first
recording descriptive information in the predefined
fault Information area of a system object. This information describes the nature of the fault and provide additional information that may assist software
in recovering from it The fault handler examines the
fault information and takes "appropriate action," as
defined by the application.. This may vary considerably according to the application and the nature of the
fault.
5-20
1718730()()2
.IAPX 43201/1APX 43202
Table 5.
Detectable Software Faults
General Fault Groups
Object Operator Faults
Memory Reference Faults:
Segment Overflow Fault
Memory Overflow Fault
Read Rights Fault
Write Rights Fault
Bus Error
Branch
Branch True
Branch False:
Instruction POinter Overflow Fault
Instruction Object Displacement Fault
Instruction Fetch Fault
Data Part Cache Qualification Faults
Data Part Access Faults: '
Access Descriptor Validity Fault
Object Descriptor Type Fault
Object Table Qualification Faults:
Object Descriptor Type Fault
Object Type Fault
Access Environment Altered Faults:
Access Descriptor Validity Fault
Object Descriptor Fault
Data Operator Fault Groups
Domain Error Fault
Overflow Fault
Underflow Fault
Inexact Fault
Non-Instruction Interface Faults
Initialization:
Object Qualification Faults (Processor)
Object Qualification Faults
(Object Table Directory)
IPC Faults
Object Qualification Faults (PCO)
PCO Response Count Fault .
PCO Lock Fault
Idle:
Delay Port Service Faults
Process Binding:
Object Qualification Faults (Carrier)
PrOcess Lock Faults
Process Qualification Faults
Port Operation Faults
Process Selection:
Delay Port Service Faults
Object Qualification Faults
Port Operation Faults
Branch Indirect:
Instruction Object Displacement Fault
Branch Intersegment
Branch Intersegment without Trace
Branch Intersegmenf and Link:
Object Qualification Faults (Instructions)
Instruction Object Displacement Fault
Copy Access Descriptor:
Store Access Descriptor Faults
Null Access Descriptor:
Destination Delete Rights Fault
Amplify Rights:
TCO Type Rights Fault
Object Qualification Faults (TCO)
Type Fault
Race Condition Fault
Retrieve Type Definition:
Source AD Validity Faults
Store Access Descriptor Faults
Create Refinement:
Source AD Validity Fault
Object Descriptor Type Fault
Offset and Length Compatibility Fault
Refinement Overflow Fault
Level Fault
Create Typed Refinement:
TCO Type Rights Fault
Source AD Va.lidity Fault
Object Descriptor Type Fault
Type Fauit
Offset and Length Compatibility Fault
Refinement Overflow Fault
Level Fault
Create Typed Object:
Descriptor Allocation Faults
Object Qualification Faults (TeO)
TCO Type Rights Fault
Level Fault
Segment Allocation Faults
Store Access Descriptor Faults
5-21
171873-002
IAPX 4320111APX, 43202
Table s.. Detectable.Software Faults (Continued)
Inspect Object:
.
Access Path Object Descriptor Fault
Lock Object:
Source Representation Rights Fault
Unlock Object:
Source Representation Rights Fault
Object Lock ID/Type Fault
Call
Call through Domain:
Object Qualification Faults (Domain)
Domain Access Index Over'flow F'ault
Instruction Object Type Rights Fault
Object Qualification Faults (Instructions)
Context Parameters Size Fault
Context Type Rights Fault
Object Qualification Faults. (Context)
Instruction Object Displacement Fault
Return:
Context Type Rights Fault
Context Qualification Faults
Object Qualification Faults (PSO)
Object Qualification Faults (Object Table)
PSO Lock Fault
Instruction Object Displacement Fault
Block Move:
Offset Overflow
Return and Fault:
Return Fault
Send
Receive
Conditional Send
Conditional Receive
Delay Process
. Send Process:
Port Type Rights Fault
Level Fault
Surrogate Send
Surrogate Receive:
Surrogate Carrier Validity Fault
Surrogate Carrier Type Rights Fault
Destination Port Type Rights Fault
Port Type Rights Fault
Level Fault
Sell Process Mode:
Process Object Type Rights Fault
Process Object Access Mismatch Fault
Send to Processor:
PCO Type Rights Fault
Object Qualification Fau1'ts (PCO)
Move to' Interconnect
Move from Interconnect:
Odd Displacement Fault
Odd Interconnect Descriptor Base Address Fault
Object Qualification Faults (Interconnect)
The common base architecture recognizes that
some faults are more serious than. other~; indeed
certain faults, such as "not allocated" (i.e., an object
needs to be swapped in from external. storage) will
be routine in many systems. Accordingly, software
faults are divided into levels based on their impact
on the system and the amount of information required to resolve them. This permits software to provide a response that is appropriate to the severity of
the problem and to minimize the disruption that handling the fault may have on the rest of the system.
write exception handlers that will respond to GDP
context-level faults.
In general, the philosophy is to keep the unaffected
parts of the system running while the fault is handled
outside the normal flow of execution. Processors
record fault information in the system object that
corresponds to the fault-level; for example, information describing a process-level. fault is recorded in
the process object.
. ,
Each process is associated with a fault port; a fault
port is an ordinary port that queues messages that
happen to be references to "broken" processes. An
operating system fault process can receive these
process objects and attempt to "repair" them, that
is, recover from the fault. For example, if the fault
process determines that the fault is "object not allocated," it can notify tl;le system's virtual memory
manager to swap in the needed object. When this
has been done, the fault process can send the process off to its dispatching port (see "Scheduling and
Dispatching").
A context is a single instance of a prQcedure in execution. A context-level fault is one that can normally be handled within the process (i.e., by application
code). Ada, for example, permits programmers to
A process-level fault prevents the current process
from continuing until the fault is handled, but does
not affect other processes. GDPs and IPs respond
to this situation similarly. Generally, the procedure is
to remove the offending pr.ocess from the set of active processes by sending its process object to a
fault po'Pt and then dispatching the next ready process.
5-22
171873-002
IAPX 43201/1APX 43202
A proceuor.lievel fault threatens (but might not absolutely prevent) continued execution by the processor. The GOP and IP respond to this situation differently, but the basic procedure is to run a processor
diagnostic program.
. ALARM has been asserted, the GOP will complete
its current instruction and then invoke a designated
software process (waiting at the ALARM port).
Data Types
At the final level, the processor cannot do anything,
not even record fault information. It therefore halts
and asserts its FATAL pin. Software on some other
processors might monitor this pin; for example, it
could be routed to an interconnect register and periodically sampled. A halted processor can be restarted by hardware (asserting its INIT pin) or software
(sending a START IPC).
The memory formats of the GOP's eight basic data
types are illustrated in Figure 11. Any data type may
be stored on any byte boundary (performance is improved, however, when data is aligned on physical
memory boundaries). The types are divided into four
classes: character, 9rdinal (unsigned integElr), integer, and real. These data types corrEtspond directly
to the "primitive" types defined in most high level
languages. Implementing the essential types in hardware, with a choice of storage requirements for each
class, helps ensure that compiler-generated code
sequences are both compact and fast.
Interrupts. Each 432 processor has an ALARM pin
which can be asserted to signal the occurence of an
extremely high priority external event. A typical example is imminen. power failure. In general, when
D
CHARACTER
TEXT CHARACTERS
BOOLEANS
(8 bltsj
. . SHORT ORDINAL
(16 bltsj
L.L...-.J
_ _ _......_
UNSIGNED
INTEGERS
I
ORDINAL
......-'_ (32 bits)
. . SHORT
(16 bits)
L.J---1
-
I~TEGER
,
I
SIGNED
INTEGERS
INTEGER
(32 bits)
.......- - ' -.........
I
SHORT REAL
_ _- - ' _........11 (32 bits)
_....jII........._
......_
I
......_L-...._..L--I
REAL
(84 bits)
FLOATING
POINT
NUMBERS
I
TEMPORARY 'REAL
- - -__....._ ............L--'_....._.L._L..-...I.
(80 bits)
171873-15
Figure 11. IAPX 432 GOP Computational Data Types
5-23
17187~2
IAPX 43201/1APX 43202
Table 6 give~ the attributes of the numeric data,
types. Of particular note is the temporary-real data
type. The extra range and pr8cision of this type contributes to the production of consistently safe, reliable floating-point algorithms. As its name implies,
the temporary-real type is intended for holding intermediate computational results. The inputs and outputs of a calculation should be defined
short-real
or real, according to the range and' accuracy of the
available data. All intermediate results should be
held in temporary-real, with the final conversion to
the output' at the end o~ the computation.
as
Extremely large and small values are most likely to
occur in intermediate computations; .using temporary-real for these makes overflow and underflow exceedingly unlikely in most applications. 'Temporaryreal's extended precision also prevents round-off errors from accumulating during long computations;
the only significant round-off occurs at the conversion from temporary-real to the real or short-real format of the final result.
·Instructlon Set
with respect to data types. simplifies compilercade
generation.
In the data transfer group, the ZERO and ONE instructions write a constant into an operand. MOVE
copies a variable, popping the stack if it is the
source, pushing it if it is the destination. SAVE copies the stack top without popping the stack;. it can be
used to duplicate the stack top.
The logical instructions perform the customary operations. XNOR is the complement of XOR (exclusive
OR): where XOR returns 1-bits when corresponding
bits are unequal, XNOR returns 1-bits when corresponding bits are equal. It is thus the Boolean equivalent of "equals."
In the arithmetic group, the REMAINDER instruction
performs exact modulo division; it is very useful for
reducing an argument to a periodic transcendental
function (e.g. tangent) to the range accepted by the
function without !ntroducing round-off error.
SQUARE ROOT executes in about the same time as
ordinary division; programmerS need not contort algorithms to eliminate time-consuming square roots.
Table 7 shows the instructions the GDP provides for
its data types. The symmetry of the instruction set
Data Type
Character
Short-Ordinal
Ordinal
Short-Integer
Integer
Short-Real
Real
Temporary-Real
• Decimal equivalent
Table 6. Numeric Data Type.
SIgnificant
Approximate Range
Dlglts*
0s:xS:255
o s: x s: 65,535
o s: x s: 4,294,967,295
-32,768 s: x s: 32,767
-2,147,483,648 s: x s: 2,147,483,647
8.43 x 10- 37 s:lxls: 3.37 X 1038
.
4.19 X 10- 31)7 s:/x/s: 1.67 X 10308
3.4 X 10- 4932 s: X s: 1.2 X 104932
2
4
9
4
,9
6-7
15-17
19
, 5-24
1718f'3-002
IAPX 43201/1APX 43202
Table 7. IAPX 432 Operators and Computational Data Types
DataTypee
Operaton
MOVE
.{
OPERATORS.
LOGICAL
{
OPERATORS
ARITHMETIC
OPERATORS
BIT-FIELD
INSERT
Ch8r_
X
X
X
X
X
X
X
X
X
X
X
X
AND
INCLUSIVE OR
EXCLUSIVE OR
EQUIVALENCE
NOT
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ADO
SUBTRACT
MULTIPLY
DMDE
REMAINDER
INCREMENT
DECREMENT
NEGATE
ABSOLUTE VALUE
SQUARE ROOT
INDEX
X
X
X
X
X
X
X'
X
X
X
X
X
X
X
X
X
EQUAL
NOT EQUAL
EQUAL ZERO
NOT EQUAL ZERO
LESS THAN
LESS THAN OR EQUAL
POSITIVE
NEGATIVE
MOVE IN RANGE
RELATIONAL
OPERATORS
X
X
-
-
-
-
-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
-
X
X
X
X
X
X
-
-
CONVERSION
OPERATORS
WHERE:
.
X
(BLANK)
OrdInal
0rdInI01
MOVE
SAVE
ZERO
ONE
EXTRACT
INSERT
SIGNIFICANT BIT
{
Short
Short
Integer
X
X
X
X
-
-
5-25
X
X
X
X
-
-
-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
-
-
X
X
X
X
X
X
X
X
X
X
X
.X
X
X
X
X
X
X
-
TO CHARACTER
TO SHQRT ORDINAL
X
TO ORDINAL
TO SHORT INTEGER
X
.:ro INTEGER
X
X
X
TO SHORT REAL
TO REAL
X
X
TO TEMPORARY REAL
X
Means the operator IS available for the given date type.
Means the operator is available for the given date type and for instructions
in which one Of the operaods is a temporary real.
Means the operator is not available and would be of little or no use Hit were.
Means the operator Is not availabte.
-
Integer
-
-
X
X
X
It
X
X
Temp.
Real
X
X
X
-
-
-
Short
Reel
-
-
Real
-
-
*
.
*
*
*
*
*
*
-
-
-
X
X
X
X
X
-
-
-
-
X
X
X
X
X
X
X
-
-
-
-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
/
X
,
X
-
-
X
X
X
X
X
-
171873-002
IAPX 4320MAPX43202
/
,
The bit field instructions, EXTRACT,and INSERT BIT
FIELD, make the manipulation of packed bit field
re~rds simple and rapid. The SIGNIFICANT BIT instruction returns the position of the "leftmost" 1-bit
in an ordinal or short-ordinal. Note that the INSERT
BIT FIELD is an indivisible operation; once the instruction starts to run, no other processor can perform an indivisible operation on the field until its new
value has been written into memory.
The instructions in the comparison group assert a
condition existing in a single variable (e.g., EQUAL
ZERO) or between two variables (e.g., GREATER
THAN). These in,structions return a Boolean value
TRUE or FALSE according to the truth of the assertion. Conditional branching is effected by following a
comparison with BRANCH TRUE or BRANCH
FALSE instruction.
The GOP has the full complement of 432 common
base instructions plus addition data processing operations. Some of these permit changing the flow of
control in a program by conditibnal and unconditional, and by calling a procedure. Others facilitate the
manipulation of composite objects (objects made up
of other objects), access to data declared global to
all procedures in a process, and setting precision
and rounding modes for real number computations.
Finally, two of the instructions give a GOP program
acr.ess to the interconnect space.
Instruction Formats
'The 432's instruction codes have been designed to
minimize the space the instructions occupy in memory and still allow,for efficient encoding. In order to
achieve the best efficiency in storage, the instructions are encoded without regard for byte, word, or
other artificial bOOndaries. The instructions may be
viewed as a linear sequence of bits in memory, with
each' instruction occupying exactly the number of
bits required for its complete specification.
Processors view these instructions as composed of
fields of varying numbers of bits that are organized
to present information to the Instruction Decoder in
the sequence required for decoding. A unified form
for all instructions allows instruction decoding of all
instructions to proceed in the same manner.
The class field is either 4-01' 6-bits long, depending
on its encoding. The class field speqifies the number
of ~perands required by the instruction and the primitive types of the operands. The class field may indicate 0, 1, 2, or 3 operands. If the class field indicates
one or more references, a format field is required to
specify whether the references are implicit or explicit
and their uses.
'
In the case of explicit references, the format field
can indicate whether or not the reference is direct or
indirect. Further, the format field may indicate that a
single operand plays more th~n one role in the execution of the instruction. As an exampl~, consider an
instruction to increment the value of an integer in
memory. The instruction begins with a class field
specifying that the operator is of order two and that
the two operands occupy a word of storage; next,
the format field indicates that a single referenpe
specifies a logical address to be used both for fetching the source operand and for storing the result; it is
followed by an explicit data reference to the integer
to be incremented; and finally the instruction ends
with an opcode field for the order-two operator INCREMENT INTEGER.
It is possible for a format field to indicate that' an
instruction contains fewer explicit data references
than are indicated by the instruction's class field. In
this case, the other data refefences are implicit, and
the corresponding source or result operands are ob,tained from (or returned to) the top of the operand
stack. Consider the following statement:
A = A +B*C
The instruction fragment for this statement consists
of two instructions and has'the following form:
\ Iopcode Ireference I format Iclass I \
-
Increasing address
171873-16
Assume that A, B, and C are integer operands. The
first class field (the rightmost field shown above)
sp~cifies that the operator requires three references
and that all three references are to word operands.
The first format field contain$ a code specifying two
explicit data referen¢es supplying only two source
In general, GOP instructions consist of four main
operands. The destination is referenced implicitly so
fields. These fields are called the class field, the for" that the result ot'the multiplication is pushed on the
mat field, the reference field, and the opcode field. , operand stack, The second class field is identical to
The reference field, in turn, may contain several oththe first and specifies three required references by
er fields, depending upon the number and the comthe operator, all to word operands. The second forplexity of the operand references in the instruction.
mat field specifies one explicit data reference to be
The fields of a GOP instruction are stored in memory
used for both the first source operand and the destiin the following formal
nation. The second source operand is referenced
implicitly and popped from the operand stack when
the instruction is executed.
5-26
171873-002
IAPX 43201/1APX 43202
The reference fields themselves can be of various
lengths and can appear in varying numbers (consistent, of course, with the specifications in the class
and format fields. If implicit references are specified,
reference fields for them will not appear. Direct references will require more bits to specify than indirect
references.
number to be accessed. The hardware automatically
scales the index according to the data type being
manipulated by the instruction to cal~late the actual
byte displacement. For example, to address the third
element of a vector, the indirect index variable would
contain the value 3 for any type of vector-character, integer, real, etc.
Following the class, format, and reference fields, the
opcode field appears. The opcode fi8ld specifies the
operator to be applied to the operands specified in
the preceding fields.
A fifth addressing mode is implicitly specified when a
data reference is expected (according to the "number of references" field), but none is encoded in the
instruction. The data reference in this case is the
operand on top of the stack. If the operand is the
source, it is automatically popped from the stack; if
the operand is the destination, the result of the operation is pushed onto the stack.
Addressing Modes
The operands (data items) that a GDP instruction is
to operate on are encoded in the instruction as data
references conSisting of two parts: a base part and
an Index part. The entire data reference can therefore be viewed as having three components: an access selection component, Which selects an object;
a base part of the operand offset, which provides a
byte displacement to the base of the area of memory within the selected object; and an index part of
the operand offset, which specifl9s a particular operand within that area.
The addressing is very flexible since each part of the
operand offset can be specified directly or indirectly.
A direct base or direct index has its value specified
directly in the data reference encoding. When indirection is used, however, the value of the base or
index is given by a short-ordinal value located within
the currently. accessible object.
There are four possible combinations of direct and
indirect base and index parts, and'each combination
results in a different mode of reference (see Figure
12). Each of the four combinations has been used to
name a data reference mode indicating the kind of
data strllcture for which the reference would usually
be used. The scalar, record, static array, and dynamic array modes correspond roughly to the direct,
base, indexed, and base-plus-index modes found in
~. 'ny compuf"'s; aI' ,-... ~,,~ - _." indepenr.' '~!y
available for any operand specified in an instruction.
As shown in Figure 13, the displacement component
.. , _""'~' L.....
""I~...,ded d~"~';'&'J"'"
:::.!c~:..
. ..
collie from base and index variables in memory (including the stack), or may consist of one direct and
one indirect value. Choosing' between direct and inj!r£':.~ .:;: .. , '''':.:::.t:on: ;~:~:.~:!~ ~:;:_ .. ~~ . . ::1 t".t~.':': ::-'
mation is fixed at compile-time and what may ,be
computed during ex~ution.
Large Array Indexing
The maximum size of the data part of an object is
65,636 (64K) bytes, but of course, some applications
require arrays that are larger. The INDEX ORDINAL
operator is used to access these large .arrays.
The large array is mapped (at compile-time) into a
series of objects, each with data parts that are 2,048
bytes (2K) long. All these objects are directly acces':
sible in the current logical access environment. The
INDEX ORDINAL operator works as follows:
Given:
• The size of each element in the array (i.e., a
scale factor)
• The access selector for the base segment of
the array
• the ordinal index for the desired array element
The operator computes:
• The access selector for the appropriate 2K
data object that contains the indexed array ele- .
ment
• The displacement into the data part of that object in the array element
.1
·N-:.~v ;;~..~
The resulting short-6rdinal values can then be used
with-the indirect acceSs selection mode and the record, statiC· array, or dyn,mic array data reference
mo~:;s to .::.~cess t~~ ;;::ray e~:::"".·ont. Of course, this
whole process is invisible, to the typical 432 programmer who uses Ii high-level language and leaves
the choice of machine instructions to the compiler.
':, ... "::._.:.. ;ndex value (used to sell..';; an
array element) is expressed naturally as the element
5-27
171873-002
IAPX 43201/iAPX 43202
...-
. - - - - - - - - - - - - - "...
-.~
BAS!S
.&
(
\
DIHECT
INDIRECT
DIRECT
SCALAR
RECORD
ITEM
INDIRECT
STATIC
ARRAY
DYNAMIC
ARRAY
INDEX
171873-17
INDEX
(DIRECT)
DISPLACEMENT
(BASE AND
INDEX ARE SAME
DIRECT VALUE)
BASE
(INDIRECT)
SCALAR
RECORD ITEM
INDEX
(INDIRECT AND SCALED)
INDEX
(INDIRECT AND SCALED)
BASE
SASE
(DIRECT)
(INDIRECT)
STAnc ARRAY ELEMENT
DYNAMic ARRAY ELEMENT
111873-18
Figure 12. Addressing Modes
5-28
171873'()()2
IAPX 43201/1APX 43202
DATA ITEM INDEX LENGTH
X
DISPLACEMENT (7 OR 18 BITS)
DATA SEGMENT
70R.ll
V///////////////-
I
SELECTOR
(MAV BE DIRECT OR IN,?IRECTI
171873-19
A. SCALAR DATA REFERENCE MODE
DISPLACEMENT LENGTH
BASE DISPLACEMENT
(SPECIFIED
INDIRECTLV)
I-S8BITS
,
:
DATA ITEM OFFSET
(7 OR 16 BITS)
IX
i
70RlniTS
DATA SEGMENT
TOP OF
OPERAND STACK
OR
VARIABLE IN SAME
DATA SEGMENT
OR
VARIABLE IN ANOTHER
DATA SEGMENT
'l///////////////.
REC ORO
REFER ENCED
'" ~
DISPLACEMENTTO BASE
OF RECORD REFERENCED
MENT
OFRECORD
REFERENCED
I
SELECTOR
171873-20
B. RECORD ITEM REFERENCE MODE
Figure 13. Modes of Displacement Generation' .
5-29
171873-002
IAPX 43201/1APX 43202
BASE LENGTH
ELEMENT I~DEX
(SPECIFIED
INDIRECTLY
X
BASE DISPLACEMENT
1-368ITS
OOR 16 BITS
DATA SEGMENT
TOPOF
OPERAND STACK
OR
VARIABLE IN SAME
DATA SEGMENT
OR
VARIABLE IN ANOTHER
DATA SEGMENT
IV/////////////,
I
ELEMENT OF
ARRAY
~ REFERENCED
SCALlNGBt@
DATA TYPE
I
ELEMENT
DISPLACEMENT
SELECTOR
171873-21
C. STATIC ARRAY ELEMENT REFERENCE MODE
BASE DISPLACEMENT
(SPECIFIED
INDIRECTLY)
1-36 BITS
,
TOPOF
OPERAND STACK
OR
VARIABLE IN SAME
DATA SEGMENT
OR
VARIABLE IN ANOTHER
DATA SEGMENT
,
ELEMENT INDEX
(SPECIFIED
INDIRECTLY)
i
1-36B11S
DATA SEGMENT
TOPOF
OPERAND STACK
OR
VARIABLE IN SAME
DATA SEGMENT
OR
VARIABLE IN ANOTHER
DATA SEGMENT
SCALIN~~J
'-'/ / / / / / /\I
DATA TYPE
ARRAY
REFERENCED
~ ELEMENT OF
ARRAY
REFERENCED
I
SELECTOR
171873-22
D. DYNAMIC ARRAY ELEMENT REFERENCE MODE
Figure 13. Modes of Displacement Generation (Continued)
5-30
171873-002
inter
IAPX 43201/1APX 43202
SCheduling and Dispatching
In most systems there 'will be more processes to run
than there are processors. The procedure by which
- processes "take turns" running on GDPs is called
dispatching and scheduling. Each processor is assigned to a dispatching port, from which it obtains
its work, that is, the processes it executes. A dispatching port is an ordinary port object; it so happens that the access descriptors queued there are
for process objects and processor objects. The assignment of processors to dispatching ports is defined by the application; usually all processors share
one port, but each may have its own, or a processor's dispatching port may be changed by operating
system software during execution.
Scheduling and dispatching are performed in two
loops as shown in Figure 14. To maximize processor
utilization, low-level scheduling and dispatching are
performed automatically by the processor with no
software intervention. Every process has four SCheduling parameters; these are initially set by the operating system when a process is created. The parameters are:
1) priOrity, the relative urgency of the process;
2) deadline, the amount of time that may pass
before the process must have a turn on the
processor; ,
3) service period, the duration of one turn;
4) pertod count, the number of turns the process should be given before examining its
scheduling parameters.
PROCESSOR DISPATCHING
PROCESS SCHEDULING
,
NORMAL
, DISPATCH.
PORT
DISPATCH.PORT
BINDING
PROCESS
EXECUTION
TIME SLICE
EXHAUSTED
GET NORMAL
WORK
GET NORMAL
WORK
SHORT·TERM SCHEDULING
GET WORK AT A SPECIAL
DISPATCHING PORT
k
SCHEDULER
PROCESS
SCHED.PORT
r--
.
PROCESSORLEVEL FAULT
DIAGNOSTIC
PROCESS
EXECUTION
ALARM SIGNAL
ALARM PROCESS
EXECUTION
LONG·TERM SCHEDULING
FAULT
PROCESS
rl
FAULT.PORT
I
RECONFIGUAATION
SIGNAL
FAULT PROCESSING
-
I
RECONFIGUAATION
PROCESS
EXECUTION
10-
"
.- I
, I
COMIlUNICATlON.PORT
,-
~
INTERPROCESS COMMUNICATION
171873-23
Figure 14. Process scheduling and processor dispatching: The left half of the diagram describes
~Ible states of a process, while the right half describes possible states of a processor.
5-31
171873-002
, ,1
IAPX ,43201/IAPX' 43202
All time values are based on the system time unit.
These parameters give operating system software
great flexibility in setting system scheduling policy
(or policies), and even altering a policy during execution.
Like the messages at any priority/deadline port,
processes waiting for service at a dispatching port
are ordered by deadline within priority; the highestpriority-least-deadline process is at the front of its
queue. A GOP dispatching operation consists simply
of "receiving" this process. The processor loads its
on-chip service timer with the process's service period value and runs the processor for one service period. (Assertion of the PCLK pin increments the
processor clock and decrements the service period
as well.) At the end of the service period, the GOP
decrements the process's period count, updates the
process's process clbck with the number of time
units given to it, and schedules the process for another turn. If the period count has not yet expired,
this is done by sending the process to its dispatching
port. The send operation inserts the process into the
queue according to its scheduling parameters.
If the process blocks before its period expires (before the service timer goes to zero), the,period count
and the process clock are also updated (with the
number of actual units received), but the process is
sent to a communication port instead of a dispatching port.
High-level scheduling is performed by the operating
system; it gives the executive the opportunity to examine the system's performance and perhaps adjust
its scheduling algorithms. When a process has exhausted all its service periods, the processor sends
the process to a scheduling port instead of a dispatching port. The operating system scheduler receives the process, sets its scheduling and service
parameters -again, and sends the process back to
the dispatching port, where the low-Ie",el cycle begins again.
When a GOP attempts to dispatch a process and
none is available, the processor queues itself (that
is, its processor object) at the dispatching port and
"sleeps" until a proce~s arrives. (A sleeping processor is almost completely idle; in It multiprocessor
configuration this helps to reduce contention for use
of the memory bus.) The processor that sends a
process to the dispatching port also "wakes up" the
sleeping processor (by means of an IPC); the awakened processor then dispatches the newly-arrived
process. Operating system software may periodically check dispatching ports for idle processors and
reassign them to dispatching ports that are more
heavily loaded.
Designing Fault-Tolerant Systems
When used together, the five components in the
iAPX 4.32 family provide all the logic necessary to
build a system that will tolerate the failure of any
single component or bus, yet continue to execute
programs without error and without interruption. No
software intervention is required: fault detection, isolation, and reconfiguration of the .system is performed entirely by the hardware.
Each GOP is able to detect hardware errors automatically because of a capability known as Functional Redundancy Checking. (FRC),so called because
a second or redundant GOP checks the operations
of the first or master GOP. Functional Redundancy
Checking .provides the low-level hardware support
upon which hardware fault-tolerant modules are
constructed.
During initialization, each GOP is assigne,d to operate as either a master or a checker (see Figure 15).
While a master operates in a conventional manner, a
checker' places all output pins that are being
checked into a high-impedance state. Those pins
which are to be checked on a master and checker
are parallel-connected, pin for pin, such that the
checker is able to compare its master's output pin
values with its own. If on any cycle, the values differ,
the checker asserts HERR and the faulty components can be immediately disabled. Thus, any hardware errors can be detected as they occur and before they have had the opportunity to corrupt the
operation of other components in the system.
MASTER
--r-
INPUTS
OUTPUTS
'-+
INPUTS
CHECKED
,OUTPUTS
I----'r-
IHEiiR
CHECKER
171873-24
Figure 15. Function redundancy checking
detects hardware errors a~omatlcally.
WhileFRC can be used alone to provide automatic
error detection, a completely fault-tolerant system
must also be able to reconfigure itself, replacing the
set of failed components with another pair that is still
working .. In order to do so, the 432's architecture
enables two pairs of master/checker components to
be combined to form primary and shadow processors in a configuration known as Quad Modular Redundancy (QMR). See Figure 16.
5-32
171873-002
IAPX 43201/IAPX 43202
r - - - - - - - - - - - --.,
QMR
PROCESSOR
MODULE
HARDWARE
RECOVERY
r- - - - - - - ,
I
I
I.
I
I
I
I
FAe
PROCESSOR
MODULE
HARDWARE
SELF·CHECKING
I
I
I
______ .JI
MEMORYBUS
,.------,
BASIC -
PROCESSOR
MODULE
SOFnlAR~PROGRAMMABLE
flECONFIGURATION
MEMORY
L _
_ _ _BUS
_ :...J
171873-25
figure 18. Fault Tolerant AHemativ..
5-33
171873-002
I
, IAPX 43201/1APX 43202
Every module in a QMR system is paired with another self-checking module of the same type. The pair
of self-checking modules operates in lock step and
provides a complete and current backup for a/l state
information 1n the module. The mechanism is known
as module shadowing because a shadow is ready to
fill in if the primary fails (or vice versa). Fault detection and recovery occurs transparently to both application and system software. When a fault is detected, the faulty pair is automatically disabled, and the
remaining pair takes over. Only then is system software notified that a failure has occured.
ond the Microinstruction Sequencer, and the third
the Execution Unit. The first two stages of the pipeline are physically located on the iAPX 43201 with
the third stage on the iAPX 432Q2. Each stage, however, can be consider-ed an independent subproces- '
sor that operates until the pipeline is full, and then
h,,1ts and waits for more work to do.
Instruction Decoder
The general task facing the Instruction Decoder (see
Figure 17) is to interpret the macroinstruction stream
both to extract logical addresses and to determine
the next microinstruCtion sequence to be initiated. In '
dOing so, it performs the following functions:
• Receives macroinstructions
• Processes variable length fields
• Extracts logical ad~resses
• Generates sta~ng addresses for the micro-instruction procedures
• Generates microinstructions for simple operations
A more complete discussion of the fault-tolerant capabilities of the iAPX 432 can be found in the IAPX
43204·IAPX 43205 Fault Tolerant Bus Interface
and Memory Control Units data sheet (Order Num-
ber 210963).
HARDWARE IMPLEMENTATION'
The iAPX 432 General Data Processor is organized
as a three-stage microprogram-controlled pipeline.
The first stage is the Instruction Decoder, the sec-
MASTER
}IIIUI
BUFFER
AND
HARDWARE
CHECKING
LDGIC
.115
.10
r;::=====~>lINSTRUCTION
DECODER
I<~====::=I"
ISo
.
i
_____~______.l
ACOIS.. ,ACDo PRO
ICS
171873-26
Figure 17. 43201 Block Diagram
5;'34
, 171873-002
lAP X 43201/1APX 43202
The Instruction Decoder requests words from memory as they are needed, from one to ten bytes in a
single access. Depending upon the complexity of
the instruction, a 432 instruction may range from a
few bits long to several hundred bits long, extending
over many words.
A GOP instruction is composed of a variable number
of fields and each field may contain a variable number of bits. In most cases, the encoding of a field
specifies its length. The 10 determines when an instruction boudary has been reached so it can properly begin decoding the nel(t instruction.
In some cases, the interpretation of one field may
depend upon the value of some previous filed. The
intrepretation of the opcode (the last field in an instruction), for instance, depends on the value of the
class field (the first field) in the instruction. The 10
therefore saves enough information about each instruction to properly interpret each filed.
, Since a GOP instruction may contain an explicit reference to some location in memory, the logical address information must be transfered to the Refer-,
ence Generation Unit in order to generate the correct physical address of the operand. As with all
fields in of a GOP instruction, the length of logical
address fields is variable. Consequently, the 10 formats the logical addrt:lss and stores it until needed
by the Reference Generation Unit.
Since branch instructions occur frequently, it is important to minimize the startup time for the GOP after a branch has occurred. Since an instruction may
r---------------
begin on any bit, the GOP is able to begin decoding
at any point in a segment.
Microinstruction' Sequencer
The Microinstruction Sequencer (MS) decides which
microinstruction should be sent to the Execution
Unit (EU) for each cycle. In doing so, it per:forms the
following functions:
• Executes microcode sequences out of an onchip, 4k by 16-bit ROM
•
•
•
•
Responds to bus control Signals
Invokes macroinstruction fetches
Issues microinstructions to the EU
Initiates interprocessor communication and
fault handling sequences
The MS chooses from two sources of microinstructions: they may come from either the 10 or from the
ROM in the MS. After issuing one microinstruction,
the MS then computes the address in ROM (if any)
for the next microinstruction. Since the EU may require differing lengths of time to complete some microinstructions, the MS waits for the requested operation to be completed before issuing the next one.
Execution Unit
The iAPX 43202 contains the third stage of the GOP
pipeline-the Execution Unit (see Figure 18). The
EU receives microinstructions from the 43201 and
routes them to one of the two independent subpro-
-------~-------~
I
1
1
r---...;;01:"""-l-_...!._MASTER
PROCESSOR
PACKET BUS
~_~CO:N~TR:OL~~~____~~
I
I
IL _________________________________
BOUT
Flgur~
les
PRQ
ACD 15 ACD o
~
171873-27
18. 43202 Block Diagram
5-35
171873-002
IAPX 43201/1APX 43202
cessors that comprise it: the Data Manipulation Unit
(DMU) and the"Reference Generation Unit (RGU).
While the EU executes most microinstructions in
one clock cycle, each of the subprocessors has an
associated sequencer that may run for many cyc;les
in response to certain microinstructions. These sequencers are invoked, for example, for floating operations in the OMU and Processor Packet bus transactions in the RGU.
The OMU contains the registers and arithmetic logic
to perform the following functions:
•
Hardware recognition of nine data types
•
16- and 32~bit multiply, divide, and remainder
through a built-in state machine
•
Control functions for 32-, 64-, and BO-bit floating point arithmetic.
The RGU performs the following functions:
•
Translates 40-bit virtual addresses into 24-bit
physical addresses
•
Enforces the capability-based protection system
-
When a reference to a given memory segment has
been translated from its logical representation to a
physical address, a cache in the RGU maintains the
physical base address as· well as tbe length of the
segment. Further references to the same segment
reuse this information for additional address translations. A least-recently-used algorithm is implemented in hardware to determine which segment basele!'lgth pair to replace when a new segment is referenced. To further increase performance, the top 16bit element in the operand stack is cached in the
OMU.
In enforcing capability-based addressing, every
memory reference is checked by the RGU to see if it
is within the -length of its segment, and the type of
access (read, write, etc.) is verified to make certain
that the object has the proper rights to perform the
operation.
The iAPX 43201 and iAPX 43202 components together form a GOP. Figure 19 shows a logical representation with both units interfacing to the Processor
Packet bu~ as a single processor. Figure 20, in turn,
shows the physical layout.
•. Sequences B-, 16-, 32-, 64-, and BO-bit memory accesses
•
Controls on-chip top-of-stack register
.
CLOCK GROUP
VCC
vss
'CLKA ClKB'
.
ALARM
BOUT
FATAL
PCi:K
PRQ
PROCESSOR
PACKET BUS
GROUP
GOP
lOGIC
SYMBOL
iNI'i'
,
ClR
SYSTEM
GROUP
ICS
MASTER
ACO.....
ACO,
REJiR
I
171873-28
Figure 19. GOP Block Diagram
5-36
171873-002
IAPX 4320111APX 43202
I11III111
111111111. (
~~I~~~~lllgillil~
1;llig;I¥~~d~ I~
NC 1=
"IISH"IIOI=
NC~
1=
;nil 1=
ICSI-
PRO 1=
vee
~
VlIO ~
VIIO
vee
vee
HC
9"HC
NC
lOUT
ICS
PRO
NC
vee
ACDIS
PIN NO. I MARK
ACD
171873-29
Figure 20. GDP Interconnect
PROCESSOR PACKET
BUS DEFINITION
Processors sharing the same memory must contend
for access to that memory over one or more system
buses. Therefore, efficient bus utilization is essential
in a multiprocessing system. A simple and efficient
approach to building a 432 interconnect system is to
use the iAPX 43204 Bus Interface Unit; the VLSI
component provides the necessary circuitry to interconnect 432 processors with from one to eight
memory buses. Some system deSigners, however,
may prefer to take other approaches to the intercpnnect design to optimize the cost/performance ratio
of the hardware for their specific application. With
that requirement in mind, Intel formulated an iAPX
432 packet bus protocol which supports a wide
range of system bus architectures.
To reduce bus occupancy and increase the performance range of 432 systems, the packet bus protocol
separates processor requests and replies into separate packets. A pfocessor can issue a request packet and leave the system bus free until the reply packet is returned from memory.
As a second method of maximizing the efficiency of
bus utilization, the packet bus protocol allows varaible length packets of data. If a processor wishes to
read a 64-bit operand, it can be done with a single
request and reply packet. Thus, fewer individual
storage requests are required to process long operands. This aspect of the protocol enables processors to interface easily to 16-bit, 32-bit, or even 64bit system buses.
This section de$cribes the 19 signal lines that compose the Processor Packet bus and their timing relationships. While this section defines all valid bus activities, the processors do not necessarily perform all
allowed activities; nevertheless, slaves to the Processor Packet bus must aupport all state transitions
to ensiJre compatibility (see Figure 21).
The Processor Packet bus consists of three control
lines:
• PRQ (Processor Packet bus request)
'. BOUT (Enable Buffers for Output)
• les (Interconn~t Status)
5-37
171873-002
inter
IAPX 43201/1APX.43202
171873-30
• Note that the broken transitions in the GOP state diagram are
not generated by the GOP component pair.
Initial State
Next State
Ti
T1
Ti
T1
T2
Unconditional
T2
T3
Tw
ICShigh
ICSlow
Canceled, Access Pending
Canceled, No Access Pending
T1
Ti
T3
T3
Tw
Tv
Tvo
Tv
Trigger
Bus cycle desired
No bus cycle desired
Ti
Additional transfer rE;lquired, ICS high
Additional transfer required,.ICS low
All transfers completed, no overlapped access
Current write with overlapped access
T1
No access pending
Access pending
Tvo
T2
Unconditional
Tw
Tw
T3
ICSlow
ICShigh
Figure 21.
Proc,ssor Packet Bus State Diagram
5-38
171873-002
IAPX 43201/1APX 43202
During the next cycle (T2), the remainder of the ad·
dress is presented on the ACD pins, aligned so that
the most significant byte of the address is on
ACD1S-ACDs while the mid-significant byte is on
ACD7-ACDo. If PRO, is asserted during T2, the access is cancelled and the ACD lines are not defined.
PRO has two functions whose use depends upon
the application; for example, PRO either indicates
1\'Ie first cycle of a transaction on the bus or the cancellation of a transaction initiated during the previous
cycle. Of the three control lines, BOUT has the simplest function, serving as a direction control for buffers in larger systems which require more electrical
drive than the processor components can provide.
The ICS signal has three different interpretations depending on the state of the Processor Packet bus
transaction. It may indicate whether or not:
During the third bus cycle (T3 or Tw) of a Processor
Packet bus transaction, the processor presents a
high impedance to the ACD lines for read transactions and asserts data for write transactions.
• An interprocessor communication (IPC) is waiting,
Once the bus has entered T3 or Tv, the sequence of
state transactions depends. on the type of cycle requested during the preceding T1 or Tvo. Accesses
ranging in length from 1 ,to 10 bytes may be request·
ed (see Table 8). If a transfer of more than one double byte has been requested, T3 must be entered for
every double byte that is transferred. ICS dictates
whether the processor simply enters T3 or first enters Tw to wait.
• A slave requires more time to service the processor's request, or
• A bus error has occurred.
The bus also includes 16 three-state Address/Control/Data lines (ACD1S-ACDo). These lines emit information to specify the type of cycle being initiated;
transmit addresses, data to be written, and control
information; and during a read operation, receive
data returned to the processor. Details of the ACD
operation are summarized below.
After all data is transferred, the processor enters either Tv or Tvo. Tvo can be entered only when the
processor is prepared to accomplish an immediate
write transfer (overlapped access). During Tvo, the
ACD lines contain address and specification information aligned in the same fashion as T1. If the
processor does not require an overlapped access,
the bus state move to Tv (the ACD lines will be high
impedance). After Tv, a new bus cycle can be initiated with T1, or the processor may enter the idle state
(Ti).
Address/Control/Data Lines
In the first cycle (T1 or Tvo) of a Processor Packet
bus transaction (indicated by the rising edge of
PRO), the eight high-order ACD bits (ACD1S-'
ACDs)specify the type of the current transaction. In
this first cycle, the low-order ACD bits (ACD7-ACDo)
contain the least significant eight bits of the 24-bit
address.
Table 8.
ACD Specification Encoding
ACD
ACD
ACD
ACD
ACD
ACD
ACD
ACD
15
14
Op
13
12
11
10
9
8
RMW
Length
0Read
0Normal
1Write
1RMW
000- 1 Byte
001- 2 Bytes
010- 4Bytes
011- 6 Bytes
100- 8 Bytes
101-10 Bytes
110-16 Bytes*
111-32 Bytes*
Access
0Memory
1, Interconnect
Space
*Not implemented
5-39
Modifiers
ACD15=0:
OO-Inst Seg
Access
01-Stack Seg
Access
1O-Context Ctl
SegAccess
11-0ther
ACD15= 1:
OO-Reserved
01-Reserved
10-Reserved
ll-Interconn
Register
171873'()02
/
IAPX43201/iAPX 43202
Interconnect Status (ICS)
Processor Packet Bus Request (PRQ)
As discussed earlier, ICS has three possible interpretations depending on the current state of the bus
transaction (see Table 9). Even so, under most conditions ICS indicates whether or not an IPC is pending; a valid low during any of these cycles with IPC
significance signal the processor that an IPC has
been received. While an iAPX 432 processOr is only
required to record and service one IPC or reconfiguration request at a time, logic in the interconnect
system must record and sequence multiple (and
possibly simultaneous) IPC occurrences and reconfiguration requests. Thus, the logic that implements
ICSmust accommodate global and 10caliPC arrivals
and requests for reconfiguration as individual
events:
PRQ is normally low and goes high only during T1,
T2. and Tvo. High levels during Tvo and T1 indicate
the first cycle of an access. A high level during T2
indicates that the current cycle is to be cancelled.
See Table 10.
Table 9.
State
Table 10. PRQ Interpretation
State
Ti
Tl
T2
T3
Tw
Tv
Tvo
PRQ
CondHlon
0
1
0
1
0
0
0
1
Always
Initiate access
Continue access
Csncel access
Always
Always
Always
Initiate overlapped access
les Interpretation
Significance
Enable Buffers for Output (BOUT)
Level
High
Low
Ti. Tl, T2
IPC
NolPC
Waiting
IPC
Waiting
T3,Tw
Stretch
Don't
Stretch
Stretch
Tv, Tvo
Err
Bus. Error
No Error
BOUT is provided to control external buffers· when
they are present. Table 11 and Figures 22 through
27 show its state under various conditions.
Processor Packet Bus Timing
1. Assert IPC significance on ICS for the arrival of an
IPC or reconfiguration request.
Each timing diagram shown on the following pages
illustrates the timing relationships on the Processor
Packet bus during various types of transactions. This
approach to transfer timing allows maximum time for
the transfer to occur and yet guarantees hold time.
2. When the iAPX 432 processor reads interconnect
address register 2, .it will respond to one of the
status bits for the IPC or reconfiguration request signalled on ICS in the following order:
Any agent connected to the Processor Packet bus is
recognized as either a processor (a GDP or IP) or a
slave (e.g., the memory subsystem).
BIT 2 (1 = reconfigure, 0';' do. not reconfigure)
BIT 1 (1 =globallPC pending, O=no global IPC)
\
BIT 0 (1 = local IPC pending, 0 = no local IPC)
3. The logic in the interconnect system must clear
the highest order status bit that was serviced by the
iAPX 432 processor, and if an additional IPC mes- .
sage has arrived, the interconnect logic must signal
an additional IPC to the processor bY setting ICS
high for at least one cycle and then setting ICS low
for at least one cycle, while ICS has IPC significance.
Table 11.
BOUT
Always High
Write
Read
T1, T2, T3, Tw, Tvo
T1, T2
In all transfers between a processor and a slave, the
data to be driven is clocked for three-quarters of a
cycle before it is sampled. This allows adequate time
for the transfer and ensures sufficient hold time after
sampling. The BOUT timing is unique because BOUT
functions as a direction control for external buffers.
Detailed set-up and hold times can be found in the
AC Characteristics section.
BOUT Interpretation
Low-to-Hlgh
Transition
or Low
High-to-Low
Transition
or Low
High-to-Low
Transition
or High
Ti
Ti, Tv
None
T3,Tw
Tv
None
5-40
171873·002
inter
IAPX 43201/1APX 43202
.,
NOMINAL WRITE CYCLE
5 eLKA CYCLES
,
T,
T.
T~
T2
T,
T,
Tv
"
eLKA
ACD"..•ACDt
.oooo.oo•• oo{ ADDR/II'EC >{
/
PRO
ICS
IPC
X
ADDR
>{ WRITE DATA }
••••
oooooo.oooooo ••••{ ADDRISPEC}{
\
X
H'C
/
IPC
Y
STRETCH
~
ERR
\
lOUT - - '
X
IPC
X
ADDR
}ooo••
IPC
x::
\IPC
X
/
171873-31
ACDfIACD. ACDrACDo State
Hi-Z
Spec
Hi-adr
Hi-c:tata 1 *
Hi-Z
Hi-Z
Spec
Hi-adr
Hi-Z
Lo-adr
Mid-adr
Lo-data1
Hi-Z
Hi-Z
Lo-adr
Mid·adr
n
T1
T2
T3
Tv
n
T1
T2
ACD1SACDa ACDrACDo Stata
Hi-Z
Hi-Z
Tv"
Spec
Lo-adr
T1
Hi-adr
Hi-data1*
Mid-adr
Lo-data1
Spec
Lo-adr
Hi-adr
Hi-da,,1
Mid-adr
Lo-data1
T2
T3
Tvo
T2
T3
*Undefinad if SIngle byte write
·*(Preaeded by read cycle),
Figure 23. Minimum Write Cycle Timing
5-41
I
171873-002
IAPX "3201/1APX 43~a
T,
T,
TZ
T,
T,
Tw
T,
Tv
CL~A
ACD .....ACD. ___ ______ _
~
PRO _ _ _J
ICS
lOUT
IPC
''---
--.l
171873-33
Stille
Hi-Z
Spec
Hi-adr
Hi-datal
Hi-data2
Hi-data2
Hi-Z
Hi-Z
Hi-Z
La-adr
Mid-adr
Lo-datal
Lo-data2
Lo-data2
Hi-Z
Hi-Z
Ti
T1
T2
T3
Tw
T3
Tv
TI
Figure 24. Stretched Write Cycle Timing
I
\.
T,
-\
MINIMUM READ CYCLE
5 CLKA CYCLES
T,
TZ
T.
Tv
T,
T,
CLKA
ACD1S···ACDo ••• -._----
_ _ _....J --------.;-------{ ADDA/SPEC
>C
PRO
ICS
BOUT
IPC
AC~lJACDe
Hi-Z
Spec
Hi-adr
Hi-data*
Hi-Z
Hi-Z
Spec
,'------,
--1
171873-34
ACDrACDo State
Hi-Z
LcHdr
Mid-adr
Lo-datal
Hi-Z
Hi-Z
La-adr
·UndefilJ4ld H $Ingle byte read
Ti
Tl
T2
T3
Tv
Ti
T1
Figure 25.. .Minimum Read. Cycle Timing
5-42
171873-002
IAPX 4320111APX 43202
\.
IIINIIIUIi READ CYCLE ,IUFFERED SYSTEIII
• CLM CYCLES
T,
T,
t.
T,
Ta
T,
Tv
CLKA
ACD1I ... ACDo
------------< .
DOR/.PEC
I
PRO
IcaX
fPC
X
ADOIIII
~----------------{
fllUODATA
).----------------<
\
X
fPC
X
IPC
~
STRETCH
/
STRETCH
'<
ERR
fPC
rx::
I
\
IOur-../
X
ADH
171873-35
ACDllACDa ACD7ACDo State
Hi-Z
HI-Z
Spec
UMIdr
Hi-adr
~
Hi-Z
HI-z
H1-dala1*
Lo-data1
HI;"Z
HI-Z
HI-Z
HI-Z
'Undeflned if single byte read
Ti
T1
T2
Tw
T3
Tv
Ti
Figure 26. Stretched Read Cycle Timing
I·
T,
2 CLKA CYCLES
T,
'2
T,
T,
Ty
T,
T,
elKA
ACo,
ACO" ______
.•
_ __________________________ _
~_ __J~~~~~~~~~~~~
•
CANCEL
PRO--i
\~-------------------------171873-38
ACD
HI-Z
Hi-Z
TI
T1
T2·*
Spec
L.o-adr
Tt
Hi-adr
Mid-adr
T2
HI-daIa*
Lo-data
T3
HI-Z
Hi-Z
Tv
HI-Z
HI-Z
TI
·UndefIned if single byte write
* *Acceea Cancelled
tHew Acceea Started (Slave must support IhI8 aub8equent
IICC8IIe even though all proc8II8O!'8 may not Implement Il)
Spec
UMIdr
UndefInad
Undefined
Figure 27. Minimum Fau~ Acceu Cycle
5-43
171873-002
IAPX 43201/1APX 43202
Package
The iAPX 43201 and iAPX 43202 are both packaged in a 68-pin, leadless JEDEC type A hennetic chip carrier.
Figure 28 illustrates the package, and Figures 1 and 2 show the pinol.!ts.
_.084
(2.3')
\
.0lI0
. ,-__(lr
-:-~
f
1
.100
T
.038
(0.18)
.ou
-(1.81)
~
1
I
D
1 ~~
t _ _ Eo~~
PIN NO. 11
(24.38)
I
PlNNO'l~'
.
" ' - PIN NO. 1 MARK
I
.
.130
(3.38)
.880
171873-37
Figure 28. JEDEC Type A Package
5-44
171873-002
IAPX 43201/1APX 43202
stresses
*Notics:
sbov8 thosslisted under "Absolute Msximum Ratings" may causs permanent dsmage to the device.
This is a stress rating only and functional operation of the
device at thess or any other conditions above thoss indicated in the operational ssctions of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ...... O"C to 70·C
Storage Temperature .......... - 65·C to + 150·C
Voltage on Any Pin with
Respect to Ground ................ -1 to + 7V
Power Dissipation .......................... 2.5W
DC ELECTRICAL CHARACTERISTICS (y'55. = OV, V'-CC_=
Symbol
5V ± 10%)
Min
Max
Units
VllC
Input Low Voltage Clocks
-0.3
+0.5
V
VIHC*
Input High Voltage Clocks
3.5
Vcc+0.5
V
VILI
Input Low Voltage Intra-GOP Bus
-0.3
0.7
V
VIHI
Input High Voltage Intra-GOP Bus
3.0
Vee+ 0.5
V
Vll·
Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage
2.0
Vcc+0.5
V
VOLI
Output Low Voltage Intra-GOP Bus
(lOll = 0.1 mA)
-
0.35
V
VOHI
Output High Voltage Intra-GOP Bus
(IOHI = 0.1 mA)
3.25
Vee
V
VOL
Output Low Voltage
(IOl ** = 2.0 mA)
-
0.45
V
VOH
Output High Voltage
(IOH = -400 p.A: 43201
- 800 p.A: 43202)
2.4
Vee
V
lee
Power Supply Current
(sum of aU Vee pins)
-
500
mA
III
Input Leakage Current
-
±10
p.A
Oll
Output Leakage Current
±10
p.A
Parameter
-
*For operation at 5 MHz or slower, the GOP may be operated with VIHC minimum of 2.7V.
**IOL for FI'EFiR" = 0.4 mA; for FATAL = 4 mA
.
5-45
171873-002
IAPX '43201/1APX 43202
IAPX 43201 AC CHARACTERISTICS (Vee = 5V ±
,Symbol
.
10% , T A
Descrlptlo,n
= O"C to 70"C)
7MHz
5 MHz
8 MHz
Units'
Min
Max
Min
Max
Min
Max
500
ns
10,
ns
tcv
Clock Cycle Time
200
500
143
500
125
t r, tf
Clock Rise and Fall Times
0
10
0
10
0
t1, t2,
ta, t4
Clock Edge Delay Times
45
250
32
250
26
250
ns
toe
Input Signal to Clock Setup
5
35
30
teo
Clock to Output Signal Delay Time
-
-
ns
Clock to Input Signal Hold Time
-
5
toH
55
ns
toH
Clock to Output Signal Hold Time
20
TIE
Input Enable Time
10
151
Input Signal to Init Setup Time
10
tiS
Init to Input Signal Hold Time ,
20
-
5
-
85
-
65
-
17
-
10
-
10
-
25
-
-
10
10
-
17
-
15
15
ns
ns
tcv
ns
ns
The above specifications are subject to the following, definitions and test conditions:
1. Note that
tcy=t1
+ 12 + t3 + t4 + 2*tr + 2*tf.
2. Pins under consideration were subjected to the following purely capacitive loading:
C1 = 25pF on HERR
C1 = 50pF on uI15... u110, IS6... ISO
C1 = 70pF on all remaining pins.
3. All timings are measured with respect to the switching level of 1.5 Volts. The switching point of ClKA and
ClKs is referenced,. to the 1.8 Volt level.
4. ClKA and ClKs must be continuously applied for the 43201 to retain its state.
iAPX 43202 AC CHARACTERISTICS (Vee = 5V ±
Symbol
tcv
tr, tf
t1,12,
t3, t4
10% , T A
5 MHz
Description
= O"C to 70" C)
8 MHz
7MHz
Units
Min
Max
Min
Max
Min
Max
Clock Cycle Time
(teV=t1 +t2+la+4 + 2tr+2tt>
Clock Rise and Fall Times
200
500
143
500
125
500
ns
0
10
0
10
0
10
ns
Clock Pulse Widths
45
250
32
250
26
250
ns
-
5
-
,5
-
ns
30
-
25
-
65
-
55
ns
15
-
ns
-
55
ns
toe
Signal to Clock Setup Time
5
tOH
Clock to Signal Hold Time '
35
te~
Clock to Signal Delay Time
-
toH
Clock to Signal Output Time
20
tOF
Clock to Signal Data Float Tllne
-
5-46
85
75
17
-
75
-
ns
inter
IAPX 43201/1APX 43202
The timing characteristics given below assume the following loading on ouput pins. loading is given in'terms of
a fixed capacitance plus a DC current load.
Loading
Pins
HERR
90 pF 101 = 8 mA., Open Drain
70 pF 101=8 mA.,loh=800 /JoA
BOUT
PRC
70 pF 101 = 4 mA., loh = 800 /JoA
50 pF MOS only
ISs··.ISo
70 pF 101=4 mA.,loh=800 /JoA
~CD15...ACDo
All output delays are measured with respect to the falling edge of ClKA except for BOUT. BOUT output delays
are measured with respect to the rising edge of ClKA.
All timings are measured with respect to the switching level of 1.5 Volts. The switching point of ClKA and
ClKs is referenced to the 1.8V level.
The 43202 is not capable of DC operation. For continuous data and logic state retention the ClKA and ClKs
signals must be present.
IAPX 43201/43202 Capacitance
Typical
Symbol
Parameter
Input CapaCitance
CIN
Output Capacitance ,
COUT
Conditions:fc=1 MHz, VIN=OV, Vcc=5V, TA=25°C
Outputs in High Impedance State
Unit
pF
pF
6
12
WAVEFORMS:
ClKA
ClKA
ClKS
171873-38
171873-39
.43201 Clock Input Specification
43201 Output Timing Specification
ClKA
ClKS
ACD15 ••• ACDO
(FROM MEMORY) _ _..I~~:I::;~'-I
______
ACD1S",ACDO - - - - - "
IFROM 43202),
INVALID
~t::...!!L.
CLA.ALAAM
ICS
r....,r--... r - - INVALID
PRO
tDC
'ac
'OH
tDH
171873-47
171873-40
IAPX 43201' Input Timing (CLKAl
IAPX 43201 Input Timing (CLKB)
, 5-47
171873-002
IAPX 43201/1APX 43202
WAVEFORMS (Continued):
,115-,10 _ _ _ _ _- ' _....._
.....~---"----""'----+--..n._+--J'o-----
lSI
HEAA
_______~\~\-------------'C-D-~~~_______f~IOH
171873-41
43201 Hardware Error Detection Timing
ClLKA
INIT
171873-42
43201 Initialization Timing
171873-43
43201 Microcode Interrogate Timing
5-48
171873-002
IAPX 43201/1APX 43202
WAVEFORMS (Continu8d):
ClKA
ClK8
171873-44
43202 Clock Input Specification
ClKA
All OUTPUT PINS
EXCEPT BOUT
80UT
171873-45
43202 Output Timing Specification
ClKA
ACD15••• ACOO
(READ TIMING I
-----JI~-'r~~------
HARDWARE ERROR DETECTION
INPUT TIMING AND INPUT TIMING
FOR All INPUTS EXCEPT ACD15 .••ACDO_ _ _ _ _ _-'II'-iI-"Ilo___
171873-48
43202 Input Timing Specification
5-49
171873-002
inter
IAPX, 4320'111APX 432.02
iAPX 432.
General Data Processor Operator Set Summary
Character Operators
Move Character
Zero Character
One Character
Save Character
Short-Integer Operators
I
AND Character
OR Character
XOR Character
XNOR Character
Complement Character
Add Character
Subtract Character
Increment Character
Decrement Character
Equal Character
Not Equal Character
Equal Zero Character
Not Equal Zero Character
Less Than Character
Less Than or Equal Character
Convert Character to Short Ordinal
Move Short Integer
Zero Short Integer
One Short Integer
Save Short Integer
Add Short Integer
Subtract Short Integer
Increment Short Integer
Decrement Short Integer
. Negate Short Integer
. Multiply Short Integer
Divide Short Integer
Remainder Short Integer
Equal Short Integer
Not Equal Short Integer
Equal Zero Short Integer
Not Equal Zero Short Integer
Less Than Short Integer
Less Than or Equal Short Integer
Positive Short Integer
Negative Short Integer
Move in Range Short Integer
Convert Short Integer to Integer
Short-ordlnal Operators
Move Ordinal
Zero Ordinal
One Ordinal
Save Ordinal
AND Short Ordinal
OR Short Ordinal
XOR Short Ordinal
XNOR Short Ordinal
Complement Short Ordinal
AND Ordinal
OR Ordinal
XOROrdinal
XNOR Ordinal
Complement Ordinal
Extract Short Ordinal
Insert Short Ordinal
Significant Bit Short Ordinal
Extract Ordinal
Insert Ordinal
Significant Bit Ordinal
Add Short Ordinal
Subtract Short Ordinal
Increment Short Ordinal
Decrement Short Ordinal
Multiply Short Ordinal
Divide Short Ordinal
Remainder Short Ordinal
Add Ordinal
Subtract Ordinal
Increment Ordinal
Decrement Ordinal
Multiply Ordinal
Divide Ordinal
Remainder Ordinal
Index Ordinal
Equal Ordinal
Not Equal Ordinal
Equal Zero Ordinal
Not Equal Zero Ordinal
Less Than Ordinal
Less Than or Equal Ordinal
Equal Short Ordinal
Not Equal Short Ordinal
Equal Zero Short Ordinal
Not Equal Zero Short Or1''',11
Greater Than Short Ordinal
Greater Than or Equal Short Ordinal
i
Ordinal Operators
Move Short Ordinal
Zero Short Ordinal
One Short Ordinal
Save Short Ordinal
Convert Short Ordinal to Integer
Integer Operators
Move Integer
Zero Integer
One Integer
Save Integer
Add Integer
Subtract Integer
Increment Integer
Decrement Integer
Negate Integer
Multiply Integer
Divide Integer
Remainder Integer
Equal Integer
Not Equal Integer
Equal Zero Integer
Not Equal Zero Integer
Less Than Integer
Less Than or Equal Integer
Positive Integer
Negative Integer
Move in Range Integer
Convert Integer to Short Integer
Convert Integer to Ordinal
Convert Integer to Temporary Real
Convert Integer to Ch, :"acter
'Co(lvert Integer to Short Ordinal
Short-Real Operators
Move Short Real
Zero Short Real
Save Shol1 Real
Add Short Real-Short Real
Add Short Real-Temporary Real
Add Temporary Real-Short Real
Subtract Short Real-Short Real
Subtract Short Real-Temporary Real
Subtract Temporary Real-Short Real
Multiply Short Real-Short Real
Multiply Short Real-Temporary Real
Multiply Temporary Real-Short Real
Divide Short Real-Short Real
Divide Short Real-Temporary Real
Divide Temporary Real-Short Real
Negate Short Real
Absolute Value Short Real
,
Convert Ordinal to Integer
Convert Ordinal to Temporary Real
5 ..50
I
171873-002
IAPX 43201/1APX 43202
IAPX 432. General Data Processor Operator Set Summary (Continued)
Short-Real Operators
Equal Short Real
Equal Zero Shor,t Real
Less Than Short Real
Less Than or Equal Short Real
Positive Short Real
Negative Short Real
Convert Short Real to Temporary Real
Real Operatqre
Tempo~ry-Real Operatore
Move Real
Zero Real
Save Real
,Move Temporary Real
Zero Temporary Real
Save Temporary Real
Add Real-Real
Add Real-Temporary Real
Add Temporary Real-Real
Subtract Reai-Real
Subtract Real-Temporary Real
Subtract Temporary Real-Real
Multiply Real-Real
Multiply Real-Temporary Real
Multiply Temporary Reai-Real
Divide Real-Real
Divide Real-Temporary Real
Divide Temporary Real-Real
Negate Real
Absolute Value Real
Add Temporary Real
Subtract Temporary Real
Multiply Temporary Real
Divide Temporary Real
Remainder Temporary Real
Negate Temporary Real
Squara Root Temporary Real
Absolute Value Temporary Real
Equal Real
Equal Zero Real
Less Than Real
Less Than or Equal Real
Positive Real
Negative Real
Equal Temporary Real
Equal Zero Temporary Real
Greater Than Temporary Real
Greater Than or Equal Temporary Real
Positive Temporary Real
Negative Temporary Real
Convert Temporary Real to Ordinal
Convert Temporary Real to Integer
Convert Temporary Real to Short Real
Convert Temporary Real to Real
Convert Real to Temporary Real
Access Descriptor Movement
Operatore
Copy Access DesCriptor
Null Access Descriptor
Refinement Operatore
Create Generic Refinement
Create Typed Refinement
Access Interlock Operetore
Lock Object
Unlock Object
Indivisibly Add Short Ordinal
Indivisibly Add Ordinal
Indivisibly Insert Short Ordinal
Indivisibly Insert Ordinal
Process Communication
Operatore
Send
Receive
Conditional Send
Conditional Receive
Surrogate Send
Surrogate Receive
Delay Process
Read Process Clock
Send Process
Set Proooss Mode
Type and
Rights Manipulation Operatore
Amplify Rights
Restrict Rights
Retrieve Type Definition
Object Creation Operetore
Create Object
Create Typed Object
Branch Operatore
Branch
Branch True
Branch False
Branch Indirect
Branch Intersegment
Branch Intersegment without Trace
Branch Intersegment and Link
Breakpoint
Processor Communication
Operatore
Reed Processor Status and Clock
Send to Processor
5-51
Access Path Inspection Operatore
Inspect Access Descriptor
Inspect Object
.Equal Access
Move to Embedded Data Value
Move from Embedded Data Value
Interconnect Operatora
Move to Interconnect
Move from Interconnect
Context
Operatore
Enter Environment
Copy Process Globals
Set Context Mode
Call
Call through Domain
Return
Return and fault
Adjust Stack Pointer
Block Move
171873'()()2
iAPX 4320ViAPX 43202
Additional Information .
M9re information about the iAPX 432 Micromain".
frame architecture can be found in the following publications:
• iAPX 432 General Data Processor Architecture Reference Manual (Order Number
171860)
.
• iAPX 432 Interface Processor Architecture
~eference Manual (Order Number 171863)
• iAPX 432 Interconnect Architecture Reference Manual (Order Number 172487)
Information on the electrical characteristics of other
432 components can be found in the following publications:
• iAPX 43203 Interface Processor Data Sheet
(Order Number 171874)
• iAPX 43204/43205 Fault Tolerant Bus Interface and Memory Control Units (Order Number 210963)
• iAPX 43204/43205 BIUlMCU Electrical
Specifications (Order Number 172867)
5-52
171873-002
intJ
iAPX 43203
FAULT TOLERANT INTERFACE PROCESSOR
• Multiple Interface Processors Expand
I/O Capacity
• Master/Checker Pairs Detect Hardware
Errors Automatically
• Quad Modular Redundancy Ensures
Immediate Recovery From Hardware
Faults
• Multiprocessor Architecture Offers
Fully Independent I/O
• High-Speed Data Channel Buffers
Burst-Mode Transfers
• Software-Controlled Windows Provide
Protected Access to 432 Memory
• 16-Blt Data Bus Interfaces Easily to
MULTIBUS~ Systems
The Intel 43203 Interface Processor (IP) provides an independent and decentralized 1/0 channel for iAPX 432
Micromainframe systems by mapping a portion of a peripheral subsystem's address space onto central system
memory. The 43203 IP can be used with the other members of the iAPX component family (i.e., the
43201/43202 General Data Processor, the 43204 Bus Interface Unit, and the 43205 Memory Control Unit) to
design a completely fault-tolerant computer system.
The 43203 is a VLSI device, fabricated with Intel's highly reliable + 5 volt, depletion load, N-channel, silicon
gate HMOS technology, and is packaged in a 68-pin, leadless JEDEC hermetic chip carrier. Refer to Figure 1
for the JEDEC chip carrier representation of the 43203 pin configuration.
PAD VIEW
V~r-~L~L~~J~~L~~JWI~I~L~L~~I~
AD7
HDA
SYNC
AD6
NAK
AD5
BOUT
AD4
ICS
AD3
PAQ
AD2
ADO
N.C.
VCC
ACD15
VSS
ACD14
PSA
ACD13
ACD12
ADI
iiiiiN
N.C.
ACDll
ACD10
ACD6
ACD8
VSS
NOTE: N.C. _
must not be _
'
Figure 1.
IAPX 43203 Interface Processor Pin Configuration
Intel Corporation assumes no respon8lblli1y for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are Implied.
November 1983
@)Intel Corporation, 1983.
Order Number: 171874-002
5-53
IAPX43203
Table 1 lists a summary of aU signal groups, signal names and their active states, and whether or not they are
monitored by the Hardware Error Detection circuitry.
Table 1. Pin Description
Symbol
Pin No.
Type
Processor Packet Bus Group
\ ACD15
1-8
1/0
60-69
ACDo
PRO
57
0
ICS
56
I
BOUT
55
0
System Group
12,34,59
Vee
Vss
9,48,68
ALARM
19
I
FATAL
16
0
I
Name and Function
Address/Control/Data Lines: These 16 bidirectional
signals carry physical memory addresses, control information
(access length and type), and data to and from the memory
bus.
When the IP is in checker mode, the ACD pins are monitored
by the hardware error detection logic and are in the high
impedance state.
Processor Packet Bus Request: is issued to gain access to
the bus. Normally low, the PRO pin is brought high during the
same cycle as the first double-byte of address information
appears on the ACD pins. PRO remains high for only one
cycle during the access, unless an address development
fault occurs. In that case, the IP leaves PRO high for a
second cycle to indicate it has detected an addressing or
segments rights fault in completing the address generation.
PRO is checked b~ the hardware detection logic and remains
in a high impedance mode when the IP is in checker mode.
Interconnect Status: carries information on errors, data
synchronization, and interprocessor communication. The
interpretation of this signal depends on the current cycle of
the bus transaction. See page 21 for a complete description.
Enable Buffers for Output: controls the direction of
external buffers, if any are used. When BOUT is asserted, it
indicates that the buffers must be directed to carry
information outbound from the IP.
Power: These three pins supply 5-volt power to the IP, and
• all must be connected; the pins are not connected together
within the IP.
Ground: These three pins provide the ground reference for
the IP, and all must be connected; the pins are not
connected together within the IP.
Alarm: monitors the condition of an unusual, system-wide
condition such as power failure. Alarm is sampled on the
rising edge Of CLKA.
Fatal: is asserted by the IP under microcode control when
the IP is unable to continue due to various error or fault
conditions. Once FATAL is asserted, it can only be reset by
the a,ssertion of INIT.
When INIT is asserted, the FATAL pin functions as an input.
During initialization, the IP samples the state of FATAL to
determine if the 432 system side should be placed in
. MASTER or CHECKER mode. See INIT description.
5-54
171874-002
IAPX43203
Table 1. Pin Description (Continued)
Type
Symbol
Pin No.
SyMem Group (Continued)
15
PcrK
I
-'
QR
18
I
Name and Function
Proceuor Clock: The assertion of i5CiJ( for one cycle
causes the system timer within the IP to decrement Assertion
of PcrK for two or more cycles causes the system timer to be
reset.l5CD< must remain unasserted for at least 10 clock
cycles before being asserted again. The IP samples PCLK on
the rising edge of CLKl'.
Clear: Assertion of rn::Fi results in a microprogram trap
causing the IP to immediately teiminate any bus transactions
or internal operations in progress. The IP resets to a known
state, asserts FATAL, and awaits an IPC for initialization. The
IPC is not seNiced for at least four clock cycles following the
.
assertion of rn::Fi.
Response to CLR is disabled by the first CLR assertion and is
reenabled when the IP receives the first IPC (or iNiT
assertion).
INIT
Hi:RR
,
13
17
I
0
The IP samples CLR on the rising edge of CLKA.
Initialize: Assertion of INIT resets the internal state of the IP
and starts execution of the initialization microcode. iNiT must
be asserted for a minimum of 8 clock cycles. After the INIT pin
returns to its nonasserted state, the IP initializes all of its
internal registers and windows, and waits for a locallPC. INIT
is sampled on the rising edge of CL,KA.
During iNiT assertion, the IP samples the FATAL and HERR
pins to establish the mode (MASTER or CHECKER) for each
of the bus interfaces to the IP. See accompanying table;
Representation of MASTER/CHECKER
Modes at Initialization
Peripheral
IAPX432
FATAL
HERR
Subsystem Side
Side
MASTER
MASTER
0
0
CHECKER
0
1
MASTER
MASTER
1
0
CHECKER
1
CHECKER
1
CHECKE,R
Hardware Erron This line is used to signal a discrepancy
between a value internally computed by a checker and that
output by the master. The sampling for errors occurs at the
most appropriate time for each of the pins being checked.
, HERR iS,an oi1en drain output and requires an external pullup
resistor. Nominally, the output is held low, but released upon
the detection Qf a discrepancy. The timing of HERR depends
on the source of the error. Once HERR is high, it remains high
until external logic forces it low again; When HERR goes low,
the present error condition is cleared and HERR is
immediately capable of detecting and signalling another error.
I
When iNiT is asserted: the HERR pins becomes an input.
During initialization, the IP samples HERR to establish the
mode (MASTER or CHECKER) of thS bus interface to the
peripheral subsystem. See the discussion of INIT.
5-55
171874-002
.
\.
IAPX43203
Table ,1. Pin DescrlRtion (Continued)
,Symbol
Type
Pin No.
System Group (Continued)
11
I
CLKA
CLKs
10
I
Peripheral Subsystem Bus Group
26·42
I/O
AD1S·
ADo
Name and Function
Clock A: is a square-wave clock which must operate
continuously to preserve the operating state of the IP.
Clock B: is a square-wave clock which operates at the same
frequency as CLKA, but lags it by 90 degrees. CLKs must
operate continuously to preserve the operating state of the IP.
Address/Data: These pins constitute a multiplexed address
and data input!output bus. When the Attached Processor bus
is idle or during the, first part of an access, these pins normally
view the bus as an address. The address is checked
asynchronously to see if it matches anyone of the five window
address ranges. The address is latched on the falling edge of
ALE, thereby maintaining the state of match or no match for the
remainder of the access cycle. The addresses are unlatched on
the falling edge of OE.
Once SYNC has pulsed high, the AD1S-ADo pins become data
input and output pins. When WR is high (read mode) and OE is
asserted, data is accessed in the IP and the output buffers are
enabled onto the AD pins. When WR is low (write mode), data
. is sampled by the IP after the rising edge of SYNC and while
CLKAis high.
The address is always a 16·bit unsigned number. Data may be
either a or 16 bits as defined by BHEN and ADo. The a-bit data
may be transferred on either the high-(AD15"ADa) or the low
(ADo·AD7) byte, while the opposite byte is tristated.
During the clock in which write data is sampled, data must be
set up before the rising edge of CLKA and must be held until
the falling edge of that clock cycle. Read data is driven out from
a CLKA high and should be sampled on the next rising edge of
C~KA.
BFiEFJ
23
I
,
Hardware error detection is not done synchronously to CLKA;
rather, it is sampled on the falling edge of OE. The internal AD
pin hardware error detection signal is then clocked and output
as HERR. Even at this point, it may !lot be synchronous with
CLKA and so should.be externally synchronized.
B~e High Enable: This pin, together with ADo, determines
wether a or 16 bits are to be accessed, and if it is a bits,
whether it is to be accessed on the upper or lower byte
position. BHEN is latched by the falling edge of ALE and
unlatched by the falling edge of OE. See accompanying table
for decodir;lg.
Bus Data Controls
iREN
Description
ADo
0
0
16·bit access
,0
1
a bits on upper byte, lower byte tristated
a bits on lower byte, upper byte tristated
1
0
1
1
a bits on lower byte, upper byte tristated
,
5-56
171874-002
IAPX43203
Table 1. Pin Description (Continued)
Name and FuncUor'l
Symbol
Pin No.
Type
PerIpheral Subsystem Bus Group (Continued)
CS
20
I
Chip select: specifies that this IP.is selected and that a read or write
cycle is requested. CS is latched by the falling-edge of ALE and
. unlatched by the falling edge of OE.
WR
21
I
Write: specifies whether the access is to be a read or a write. iiVR" is
asserted high for a read and low for a write. The pin is latched by the
falling edge of ALE and unlatched by the falling edge of OE.
PS Timing Group
ALE
.45
Address Latch Enable: The rising edge of ALE sets a flip-flop that
I
enables XACK to become active. The fallin~gBH~ALE latches the
address on the AD15-ADo pins and latches W,
N, and C!.
Data Output Enable: During a read cycle OE enables read data on the
OE
46
I
AD15-ADo pins when it is asserted. The falling edge of OE signifies the
end of an access eyclliP (for either a read or a write) by:
1. Resetting the XACK ernlble flip-flop, thereby terminating XACK.
2. Terminating i5ER (if a read cycle).
SYNC
53
I
3. Opening address latches Wit BHEN, and CS.
Synchronized Qualifier Signal: A rising edge on this signal must be
=ronized to the IP CLKA falling edge. SYNC qualifies the address,
BH , CS, and WR, indicating a valid condition. SYNC also initiates any
intemallP action to process an access.
In a read access, SYNC starts the request for data to the IP, and in a
. write access, data is expected one or two CLKA cycles after SYNC
pulses high. At initialization time, IP microcode sets the write sample
delay to the slowest operation, two CLKA cycles after SYNC, but this
can be changed to one clock cycle by making a function request to the
IP to change the write sample delay.
When the hoIdlhoid-acknowledge mechanism of the IP is used, and
once HDA has pulsed high, a SYNC pulse is required to qualify the hold
acknowledge, since the HDA pin can be asynchronous..
PS SynchronIZatIon Group
49
0
XAeK·
,Transfer Acknowledge: Thi,s signal is used to acknowledge that a data
transfer has taken place.
For random or local accesses, XACK indicates that a transfer to or from
432 system memory has been completed.
For buffered accesses where the XACK-Delay is not in the advanced
mode, XACR signifies that the transfer from/to the prefetch/postwrite
buffer in the IP has been completed.
For bt,.Iffered accesses which use advanced acknowledge mode
(XD =0) the formation of an advanced XAeK Signal is requested. This
enables the IP to interface with a peripheral subsystem without wait
states. The acknowledge will be advanced if the access is a read
operation and the buffer contains the required data, or the access is a
write operation and the buffer contains sufficient space to accept the
write data. Of course, tt'le access must also be valid.
q-57
171874-002
IAPX43203
Table 1. Pin Description (Continued)
Symbol
Pin No.
Type
Name and Function
PS Synchronization Group (Continued)
If XACK is preceded by a low pulse on NAK, then XACK signifies that
the access encountered a fault. If the access was a random access,
other than window 4, the window is placed in a faulted state and any
further attempts to access the window are ignored by the IP.
If the .IP is programmed to be in advanced acknowledge mode (XD = 0)
and XACR is not returned before the peripheral subsystem issued
SYNC, then XACK will be postponed until valid data has been
established on the AD15-ADo bus.
Five conditions affecting XACK behavior are:
1. XACK-Delay, user-programmable through an IP function request.
This parameter establishes the minimum operating XACK-delay with
respect to the SYNC signal. See accompanying table.
2. XACK-enable-flip-flop, set by the rising edge of the ALE signal and
reset by the falling edge of the OE signal.
3. InternallP registers. These are used to determine validity of the
peripheral subsystem acCess and establish access modes.
4. Type of access behavior: Random or Buffered, Memory or
Interconnect.
5. Bus faults, nonexistent memory, etc.
NAK
o
54
\
Hardware error detection occurs during the first clock of SYNC
assertion.
XACK Timing Parameters
Inhibit
XACK Formation
WR
XD1
XDo
Mode
0
X
0
0
Advanced Acknowledge
(XACK can occur before SYNC).
0
1
0
1
Rising edge of SYNC
0
0
0
1
Rising edge of SYNC plus 1 Clock
1
1
Rising edge of SYNC plus 1 Clock
0
0
1
0
Rising edge of SYNC plus 2 Clocks
0
0
1
X
1
Rising edge of SYNC plus 2 Clocks
0
X
1
0
1
Rising edge of SYNC plus 2 Clocks
X
X
1
1
Illegal condition
Note: X = don't care condition
Negative Acknowledge: This signal precedes XACK b~east onehalf clock cycle, indicating that Ii transfer did not occur. NAK pulses low
for only one clock period.
When the IP is in physical mode and making an, interconnect access,
negative acknowledge may be used to indicate that the access was
made to a nonexistent interconnect address. This will allow a
subsystem processor to determine the system configuration at system
initialization .
. 5-58
'171874-002
IAPX43203
Table 1. Pin Description (Continued)
Type
Symbol
Pin No.
Name and Function
PS Synchronization Group (Continued)
\
NAK can also be used to set a status bit and cause a special interrupt to
transmit the information back to the system.
INH1
47
0
NAK is driven synchronously from the falling edge of CLKA. Hardware
error defection occurs while CLKA is high.
Inhibit: can be used to override other memories in the peripheral
subsystem whose address space is overlapped by an IP window. INH1
is asserted asynchronously by nonclocked logic when a valid mappable
address is detected.
,
After initialization, the IP microcode sets the INH1 mode for each
window by loading registers in the IP for each window. Once the
subsystem is allowed to make a function request, it can selectively
enable or disable the inhibit'mode on each winaow. INH1 is gated off by
OS.
,
>
The selection of inhibit mode for window 0, when in buffered mode,
causes a built-in XACK-delay which delays the acknowledge from going
active until two clock periods after the rising edge of SYNC. This was
done to facilitate the use of most MULTIBUS systems using INH1, as
require that the acknowledge be delayed. When the Advanced
K mode is programmed, the inhibit mode should not be used on
window 0 when in buffered mode, since the acknowledge will not be
effectively delayed.
\
rAe
Hardware error detection occurs during the first clock of SYNC
assertion.
PS Control Group
DEN
50
HLD
51
0
0
Data Enable: This signal enables the external data buffers used in
systems where the address and data are not multiplexed (e.g., a
MULTIBUS system). DEN assertion begins no sooner than the first
clock of SYNC assertion while CLKA is high, givEn that a valid,
mappable address range has been detected. D N is terminated either
with the falling $ige of OE or after XACK assertion. .
Hardware error detection occurs during the first clock of SYNC
assertion.
Hold Requast: The hold/hold-acknowledge mechanism is an
intelocking mechanism between the peripheral subsystem and the IP.
HLD is used by the IP to gain control of the subsystem bus to ensure
that no subsystem processors will make an access to the IP while it
alters internal registers.
HLD is put out synchronously with the rising edge of CLKA. Hardware
error detection sampling occurs while CLKA is low.
In certain systems, it may not be necessary to use the HLD function
interlocking. In those cases, HDA can be tied high and no SYNC pulse
will be required for HDA qualification. The hardware detects this
condition by noting that the HDA pin was high a half~clock before HLD
requests a hold. In this mode, the HLD output still functions and can be
monitored if desired.
'
5-59
171874-002
IAPX43203
Table 1. Pin Description (Continued)
Symbol
PinHo.
Type
Name and Function
PS Control Group (Continued)
HDA
52
I
Hold Acknowledge: When the IP1s request for a hold has been granted
by the peripheral subsystem, HDA is asserted. The signal need only be
a high pulse and can be asynchronous to ClK", but must be followed by .
a SYNC pulse in order to qualify it synchronously.
INT
44
0
Interrupt:This signal is used to interrupt the Attached Processor to
request servicing. The output is a pulse two ClKA'S wide, and is driyen
synchronously from the rising edge of ClKA. Hardware error detection
occurs while ClKA is low.
PSR
24
0
Peripheral Subsystem Re. .t: is asserted by the IP under microcode
control. When asserted, the peripheral subsystem should be reset.
When used for debugging, it may be desirable to use this pin to set a
status bit in an external register or perhaps to cause a special interrupt.
PSR is normally asserted by the IPwhen the peripheral subsystem is
believed to be faulty and will not respond to other means o1.control.
PSR is issued synchronously with the rising edge of ClKA. Hardware
error qetection sampling occurs while ClKA is low.
FUNCTIONAL DESCRIPTION
As its name implies, the 43203 Interface Processor
is a logical and physical interface which links a peripheral subsystem to the iAPX 432 central system.
(The internal architecture of the IP is illustrated in
Figure 2.) The peripheral subsystem functions as an
independent and decentralized 110 channel much in
the same way as 110 channels in traditional mainframes.
The diagram in Figure 3 represents the IP as a logi-·
cal device and illustrates the signal interface to the
Processor Packet Bus (left side) and the peripheral
subsystem (right side). The IP is connected to the
peripheral subsystem bus so that it ocqupies a contiguous range of memory addresses, up to 64k bytes
in length. A peripheral subsystem reference to one
of these addresses is a reference to the IP, and
PERIPHERAL
SUBSYSTEM
iAPX432
SYSTEM
AC015
ACOO
<===--==::.')1
DATA
ACQUISITION
UNIT
1<:===:=:::>
A015
ADO
EXECUTION
UNIT
~----''--'---IIREIj.C!l.WII
ALE, OE, SYNC
IAPX
.32
CONTROL
PERIPHERAL
SUBSYSTEM
CONTROL
HlO, HOA
INH1, XACR, RAR:
r-r--
L - - _.......
INT
PS~
eLKA, elKB
Figure 2.
171874-2
iAPX 43203 IP Functional BI~k Diagram
5-60
171874-002
intJ
IAPX43203
the IP responds to tile address like a memory. The
IP also provides an interrupt request line which is
routed to its Attached Processor (AP) in the peripheral subsystem. The "other side" of the IP is connected to the' central system in exactly the same
manner as an iAPX 432 General Data Processor
(GDP). By means of these connections, the IP links
the peripheral subsystem physically to the central
system; at the same time, it is positioned to monitor
all data flow across the system boundary.
a common memory shared by the processors. In
rnost 432 systems, including all fault-tolerant systems, the prQcessors and memory are interconnected through multiple iAPX 43204 Bus Interface Units
(BIUs) and iAPX 43205 Memory Control Units
(MCUs). (See Figure 4B.)
Software in a 432 system can be viewed as a collection of one or more processes that execute on the
GDPs. A fundamental principle of the 432 architecture is that the 432 environment is self-contained;
neither processors nor processes have any direct
contact with the "outside world." In concept, the
432 system is enclosed by a wall that protects objects in memory from possible damage by uncontrolled I/O operations.
It is important to recognize that the lP is an Interface mechanism, not an active device in the sense
of a CPU. The IP does not fetch instructions; instead, it executes commands issued by AP software.
Although physically connected only by a bus and interrupt line, the relationship of the IP and AP is very
close. Indeed, it is often convenient to think of them
as constituting a logical I/O processor.
In a 432-based system, the bulk of processing required to support input/output operations is delegated to peripheral subsystems; this includes device
control, timing, interrupt handling, and buffering. A
peripheral subsystem is an autonomous computer
system with its own memory, I/O d,evices and controllers, at least one processor, and software. The
number of peripheral subsystems employed in any
given application depends on how I/O-intensive the
application is: the number may be varied as needs
change and is independent of the number of GDPs
in the system.
Peripheral Subsystems
A computer system based on the iAPX 432 Micromainframe consists of a 432 central system and one
or more peripher~1 subsystems. Figure 4A illustrates
a hypothetical configuration, which employs two peripheral subsystems. The 432 system hardware is
composed of one or more General Data Processors
(GDPs), one or more Interface Processors (IPs), and
VCC VSS (GND)
-{
PACKET
BUS GROUP
A
ACDl5-11
PRQ
ICS
BOUT
<"
~
.
A
'"
Jo
.
BHEN
cs
iNiT
CiJi
}~
BUS
GROUP
Wli
ALE
OE
SYNC
ALARM
FATAL
;;c[j(
SYSTEM
GROUP
ADl5-0
43203
IP
LOGIC
SYMBOL
INH1
lCACK
} PS TIMING
GROUP
} PS SYNCHRONIZATION
'
GROUP
NAK
ClKA
ClKB
I5'EFi
HLD
HERR
HDA
} Noomoc
GROUP
INT
PSR
PERIPHERAl SUBSYSTEM
IAPX 432 SYSTEM
171874-3
FIgure 3. IAPX 43203 IP Logic Symbol
5-61
171874-002
IAPX43203
~32/PS, BOUNDARY
432/ps' BOUNDARY
171874-4
Figure 4A. A Logical View of a 432 System and 2 Peripheral Subsystems
--------,
PROCESSOR
MODULE
I
I
1.---....,
I
GDP
1
GDP
I
1'--...,..........
I
~---+---r--~~~--~------~--~------~----------~--_~t~D
,
.J
, II.. ________
,
ACD
BUS
ACD
BUS
171874-5
wlt~
Figure 4B. A Physical View of a 2 Bus System
2 General Data Processors and 1 Peripheral Subsystem
,5-62
171874'()02
inter
IAPX43203
A peripheral subsystem resembles a conventional
mainframe channel in that it assumes responsibility
for low-level 110 device support and executes in parallel with system processors. Unlike a simple channel, however, each peripheral subsystem can be
configured with a complement of hardware and software resources that precisely fits application cost
and performance requirements.
The IP is driven by peripheral subsystem software.
To support the transfer of information through the
wall that separates a peripheral subsystem from the
432 central system, the IP provides a set of software-controlled windows. A window is used to expose a single object (typed data structure) in 432
system memory so that its contents may be transferred to or from the peripheral subsystem. To preserve the integrity of the capability-based protection
mechanisms in the 432 central system, the IP provides the peripheral subsystem with windowed access only to the data part of 432 objects.
In addition, an IP provides a set of functions Which
are also invoked by peripheral subsystem software.
While their operations vary considerably, these functions (and the returned results) generally petmit ob-
. . . - 432 SYSTEM -
jects in 432 memory to be manipulated as entities,
and they enable communication between system
processes and software executing in a peripheral
subsystem.
It is important to note that both the window and function facilities utilize and strictly enforce 432 addressing and protection systems. Thus, a window provides protected access to an object and a function
provides a protected method by which peripheral
subsystem software can interact with the 432 system.
Basic 1/0 Model
As Figure 5 illustrates, input/output operations in a
432 system are based on the notion of passing messages between processes executed within the
432's central system and device tasks executed in
a peripheral subsystem. A device task can be
thought of as the operation of peripheral subsystem
hardware and software responsible for managing an
110 device. In contrast, the 1/0 device itself either
produces or consumes data. For example, an 110
device may be a real device (e.g., a terminal), a file,
or a pseudo-device (e.g., a spooler) .
....M.---PERIPHERAL SUBSYSTEM - - -••~
(1)
(3)
(0)
DEVICE
TASK
PROCESS
(5)
I/O
DEVICE
(4)
171874-6
(0)
(1)
(2)
(3)
(4)
(5)
Process running on GOP needs 110 service.
Process formulates message describing .service, sends it to device tasks.
Device task receives service order, interprets it.
Device task transfers date according to service order parameters.
Device task formulates reply message Containing result of transfer operation, sends it back to originating process.
Originating process receives reply, interprets it, executes accordingly.
Figure 5.
Basic 1/0 Service Cycle
5-63
171874-002
iAPX43203
A message sent from a GDP process requesting 1/0
service contains information that describes the requested operation (e.g., "read file XYZ") ..The device
task interprets the message and carries out the operation. If an operation generates input data, the device task returns the task as a message to the originating process. (The device task may also return a
message to positively acknowledge completion of a
request.)
The IP connects to the 432 central system in exactly
the same way as a 432 GOP. Thus. in addition to
being able to access 432 system ,memory, the IP
supports other 432 hardware"based facilities, including interprocessor communication (IPC), alarm signaling, and functional redundancy checking.
On the peripheral subsystem side, the IP provides a
very general bus interface that can be adapted to
any standard microprocessor bus, including Intel's
MULTIBUS and MULTIBUS II architectures, as well
as the component buses of the MCS-85 and iAPX
86 families. The IP is connected to the peripheral
subsystem bus as if it were a memory component; it
occupies a block of memory addresses up to 64k
bytes long. Like memory, the IP usually behaves
passively within the peripheral subsystem and is
driven by peripheral subsystem memory references
that fall within its address range.
The'432's object-based architecture provides a very
general and powerful mechanism for passing messages between processes. While a given peripheral
subsystem mayor may not have its own message
facility, there is no requirement that it be inherently
compatible with the 432. By interposing a peripheral
subsystem interface through the IP, the standard
432 interprocess communication system can func-!
tion with any device task (see Figure 6).
While the IP generally responds like a memory component, the IP's interrupt signal notifies its AP that
an event requiring attention has occurred. Interrupthandling software on the AP then reads the status
information provided by the IP to determine the nature of the event.
. Attached Processor
Almost any general-purpose processor, such as the
iAPX 86, iAPX 186, or iAPX 286, can be used as an
Attached Processor in an iAPX 432 system, and it
need not be dedicated exclusively to working with
the Interface Processor. It might, for example, also
execute device task software or user applications.
Although multiple IPs can service a single AP for
increased 1/0 throughput, only one processor (if a
peripheral subsystem uses multiple processors)
should be designated to serve as the AP. Other
processors (or active agents, such as OMA controllers) may be given access to IP windows, but control of the IP should be centralized with the AP.
To summarize, the Attached Processor and the Interface Processor interact with each other by means
of address references generated by the AP and interrupts generated by the IP. Since the IP responds
to memory references, other active peripheral subsystem agents (bus masters), such as OMA controllers, may obtain access to 432 system memory via
the IP's windows.
As Figure 7 shows, the AP is "attached" to the IP in
a logical sense only. The physical connections are·
standard bus signals 'and one interrupt line (which
would typically be routed to the AP via an· interrupt'
controller).
Continuing the concept of the logical 110 processor,
the AP fetches instructions, provides the instructions
needed to alter the flow of execution, and performs
arithmetic, logiC, and data transfer operations within
the peripheral subsystem.
The IP completes the logical 110 processor by providing data paths between the peripheral subsystem
and the central 432 system. In effect, the IP also
extends the AP's instruction set so that software
running on the logical 1/0 processor can operate in
the 432 system.
As shown in Figure 7, the IP provides both a peripheral subsystem bus interface and a standard 432
processor packet bus interface. By bridging the two
buses, the IP provides the hardware link that permits
data to flow between the 432 central system and .the
Peripheral Subsystem Interface
A peripheral subsystem interface is a combination of
hardware and software that acts as an adaptor, enabling . message-based communiqation between a
process in the 432 system and a device task in a
peripheral subsystem.
'
The peripheral subsystem interface is managed by
software, known generically as the I/O controller.
The 1/0 controller executes on the Attached Processor and uses the facilities of the AP and IP to control
the flow of data between the 432 central system and
the peripheral subsystem.
The 432· hardware imposes no constraints on the
structure of the 1/0 controller. To help simplify the
organization and modification of software, implementers may wish to consider arranging it asa collection of tasks running under the control of a multi- "
tasking operating system. Intel's iMAX operating
system for the 432, for example, provides interfaces,
to either the iRMX-86 or iRMX-88 operating systems.
.
5-64
171874-002
IAPX43203
........_ _ _ _ _ 432 SYSTEM
------..j..........______
PERIPHERAL SUBSYSTEM _ _ _ _ _ _.....
~
PROCESS
171874-7
Figure 6. Peripheral Subsyst,m I~terface
.....1 - - - - - - - 4 3 2 SYSTEM - - - - - -........1 - - - - - PERIPHERAL
SUBSYSTEM -----4.~
....
OPTIONAL
DMA
r--..,...~ CONTROLLER
UJ
:>
r------- -----------
I
I
432
MEMORY'
INTERFACE
PROCESSOR
__________
ID
!
:Ii - - - - - - - - - - - - - - - , LOGICALVO ,
~
iil
a
:r:
~
~1J~~=R
;
' - - - r -....
l
PROCESSOR
______________
JI
INTERRUPT
II:
~
PS
MEMORY
171874-8
Figure 7. Peripheral Subsystem Interface Hardware
5-65
171874-002
IAPX43203
This type of organization supports an asynchronous
message-based communication faCility. Extending
this approach to the device task results in a consistent, system-wide communication model. However,
communication within the I/O controller and between the I/O controller and device tasks is completely application-defined. It might be implemented
via synchronous procedure calls with "messages"
passed in the form of parameters.
However it is structured, the I/O controller interacts
with the 432 central system through three major facilitiesprovided by the Interface Processor: execu, tion environments, windows, and functions.
Execution Environments
Within the 432 system the Interface Processor provides a process addressing environment supporting
the operation of the I/O controller. This environment
is embodied as a set of system objects that are
used and manipulated by the IP. At any time, the 1/0
controller is represented in 432 memory by IP process objects and their associated context objects.
Like a GOP, the IP is itself represented by a processor object. Representing the IP and its. controlling
software in this way creates an, execution environment analogous to the environment of a process
running on a GOP. This environment provides a
standard framework for addressing, protection, and
communication within the 432 system.
Like a GOP, an IP supports multiple process environments. The 1/0 controller selects the environment in
which a function is to be executed. This permits, for
example, the establishment of separate environments corresponding to the individual device tasks
, in the peripheral subsystem. If an error occurs while
the IP controller is executing a function on behalf of
one device task of the 1/0 controller, that error is
confined to the associated process, and processes
associated with other device tasks are not affected.
Windows
Every transfer of data between the 432 central system and a peripheral subsystem is performed
through an IP window. A window defines a correspondence, or mapping, between a subrange of
consecutive peripheral subsystem memory addresses (within the range of addresses occupied by the
IP) and the data part of an object in 432 system
memory (see Figure 8). When'an agent in the peripheral subsystem (e.g., the 1/0 controller) reads a
windowed address, it obtains data from the associat, ed object; writing into a windowed address transfers
data from the peripheral subsystem to the windowed
object. The action of the IP, in mapping the peripheral subsystem address to the systemobjeot, is transparent to the agent ml!oking the reference. As far as it
is aware, it is simply reading or writing memory.
Since a window is referenced as memory, any individual transfer may be made between an object and
peripheral subsystem memory, an object and a peripheral subsystem register, or an object and an 1/0
device. While the latter might be appealing from the
standpoint of efficiency, it should be used with caution.
Using a window to connect an I/O device and an
object in 432 memory directly has the undesirable
effect of propagating real-time constraints imposed
by the device beyond the subsystem boundary into,
the 432 central system and may seriously complicate error recovery. Then too, there is only a finite
number of windows and most applications will need
to manage them as scarce resources not always instantly available. This means that at least some 1/0
device transfers may need to be buffered in peripheral subsystem memory until a window becomes
available. It may be simplest to buffer all 1/0 device
transfers in memory and use the windows to transfer
data between the peripheral subsystem memory and
432 system memory at regular intervals.
There are four IP windows that can be mapped onto
four different objects. The 1/0 controller may alter
the windows during execution to obtain access to
different objects, References to windowed subranges may be interleaved in time and may be driven by
different agents in tlie peripheral subsystem. For example, the AP and a OMA controller may be driving
transfers concurrently, subject to the same bus arbitration constraints that would apply if they were accessing memory.
Functions
A fifth window, the control window, provides the 1/0
controller with access to the Interface Prooessor's
function request faCility. The 1/0 controller requests the execution of an IP function by writing operands and an opcode into predefined locations in
the control window's subrange. This procedure is
very similar to writing commands and data to a memory-mapped peripheral oontroller (e.g., a floppy disk
controller), Upon completion of the function, the IP
interrupts the AP and provides status information
that the IP controller can read through the control
window: The IP can respond concurrently to transfer
requests to the other four windows while it is exe~ut
ing a function. In addition, data transfers through
windows 0 through 3 may be interleaved with function request sequences through the control window.
5-66
171874-002
IAPX43203
-
PERIPHERAL SUBSYSTEM MEMORY SPACE
_1_
MAIN SYSTEM MEMORY SPACE_
-ro-
LOCAL ME MORY ADDRESSES
~
NORMAL MEMORY
I
,~,oo",u1
~
IP WINDOW MAPS SUBRANGE OF
{PERIPHERAL SUBSYSTEM ADDRESS
ONTO AN OBJECT IN MAIN MEMORY.
:
INTERFACE PROCE
----OBJECT
I
SUBRANGE
WINDOWED MEMORY REFERENCE
I
«'h
!
-
-'--
Figure 8.
171874-9
Interface Processor Window
The IP'S function set permits the 110 controller to:
• Alter windows
• Exchange messages with GOP processes
• Manipulate objects
These functions can be viewed as extensions to the
Attached Processor's instruction set that enable the
lID controller to operate in the 432 central system.
The combination of the IP's function set and windows, the AP's instruction set, and possibly additional facilities provided by a peripheral subsystem Qperating system, permits greater flexibility in designing
lID systems. By using the more sophisticated IP
functions, powerful 110 controllers capable of relieving the .432 system of much I/O-related processing
can be built.
5-67
171874·002
IAPX43203
"
1/0 Data Flow Summary
Other IP Facilities
Figure 9 summarizes the relationship of hardware
and software components that cooperate to move
data between an 1/0 device and 432 system memo,ry. Notice how the peripheral subsystem interface
not only ~es the 432 central systemlperipheral
subsystem boundary, but also hides the characteristics of one system from the other. As far as a device
task is concerned, its job is to move data between
memory and an 110 device; ij may be Completely
unaware that it is connected to a 432 system.
The preceding sections have described the Interface Processor as it is used most of the time. The IP
also has two additional capabilities that are used in
special circumstances: physical reference mode and
interconnect access.
Physical Reference Mode
"
Normally, an IP operates in logical reference mode
using capability-based addressing. In other words, it
utilizes an access descriptor to specify a particular
432 object rather than a physical locatiOn In memo, ry. Thera are times, however, when logical referencing is impossible because the objects used by the
hardware to perform logical-to-physical address
translation are absent (or, less likely, damaged). In
these situations, the IP can be used in physical reference mode.
This means that existing device tasks may be utilized in a 432 system with little or no modification,
and that programmers working on device tasks need
not be trained in the operation of the 432. Similarly,
a GOP process that needs an 1/0 service need have
no knowledge of the details and characteristics of
the target 1/0 device. As far as it is concerned, it
"performs" 1/0 in the same way that it communicates with a cooperating process--by sending and
receiving messages through the 432 interprocess
communication facility.
An IP operating in physical reference mode circumvents the protection mechanisms of the 432 system.
The IP provides a, reduced set of functions, and
makes no distinction between the data part and the
access part of an object. In physical mode, a window
maps directly onto a range of contiguous physical
_I_
.PERIPHERAL SUISYSTEMiPEIUPHERAL SUBSYSTEM INTERFACE,
.
(1)
I -
INPUT _
MESSAGE
I/O
DEVICE
~ON
LOCA~:
I
I
SUPPORTING
I
8U~R
II
COPY DATA
Ips I/O SPACE I I
CONTROLUNG
SOFTWARE
HARDWARE
....
PI MEMORY
DEVICE TASK
DlVlCI! COI'fflIO[[P 121
NOTES:
1.1
II
432 SYSTEM---+-
OBJECT
OBJECT
II
COPY DATA
OUTPUT
OBJECT
(11--
COPY REFERENCE
II
II
COPY REFERENCE
432 SYSTEM MEMORY
IP CONTROUER
.toP + IP C3I
II
II
GDP
PIIOCEBS
GDP
(1) ONLY OBJECT REFERENCE IS MOVED TO AND FROM PORT.
(2) SUPPORTING PROCESSOR IS DEFINED BY APPUCATION;MAY BE
AP,ASEPARATE PROCESSOR; MAY INCLUDE A ow. CONTROll.ER.
(3) MAY ALSO INC~UDE A DMA CONTROLLER.
171874-10
figure 9. I/O Data Flow Summary
!
;
'.
5-68,
'~
'
171874-002 '
IAPX43203
memory addresses (rather than object structures in
432 system memory). The IP selects a segment by
specifying a 24-bit physical address when it establishes a: window, and interprets subsequent subrange references as 16-bit displacements (there is
no length checking) from the segment's base address. This simple base-plus-displacement addressing is similar to traditional computer addressing techniques.
Physical reference mode is used most often during
system initialization to load images of objects from a
peripheral subsystem into 432 system memory.
Once the required objects are available, processors
can begin normal logical reference mode operations. Logical mode cannot be us~ until the object
tables required for logical-to-physical address translation have been constructed and 'loaded into 432
system memory.
Interconnect Access
In addition to memory, the iAPX 432 architecture defines a second, independent address space called
the processor/memory Interconnect address
apace. The interconnect space allows interconnect
objects containing one or more interconnect registers to be maintained. Interconnect registers are
double-byte quantities aligned on double-byte
boundaries. With the exception of a few reserved
addresses, thE:! definition and use of interconnect locations is not predefined for the IP.
The IP (like the GOP) requires two register locations
in the interconnect space to be defined for any system: '
•
The processor 10 register (interconnect address
Or
• The interprocessor communication register
(interconnect' address 2)
The remainder of the interconnect address space
may be used to store or acquire other information
such as configuration parameters, error logs, and
other application-specific quantities.
Window 1 is software-switchable between the memory and the interconnect spaces. In logical reference
mode, the interconnect space is addressed in the
same 6bject-oriented manner as the memory space
with the ,IP. automatically, performing the logical-tophysical address translation.
"
To access the interconnect space,4he I/O controller
must specify an accesS selector for an interconnect
object'that exposes a segment of the interconnect
space to the IP. The normal window addreSSing
scheme is then used to locate individual intercon-
nect registers within an object. Switching window 1
to interconnect access mode gives the IP access to
interconnect objects. Writing or reading window 1
then is equivalent to the MOVE TO INTERCONNECT and MOVE FROM INTERCONNECT operators of the GOP.
In physical reference mode, the interconnect space
is addressed as a linear' array of even-addressed,
double-byte interconnect registers. As with physical
reference mode memory accesses, the switchable
window is established with a 24-bit address. Peripheral subsystem references to the corresponding
subrange are likewise interpreted by the IP as 16-bit
displacements from the base address to individual
interconnect registers.
Memory Structure
The architecture of the iAPX 432 defines a two-level
memory space. Software operates in a segmented
environment in which a logical address specifies the
location of an object (data structure), and the processor automatically translates this logical address
into a physical address. A physical address is'24 bits
long, allowing a maximum physical memory 6f 1~
Megabytes. When requesting access to either read
or Write memorY, a 432 processor transmits the beginning byte of the memory byte to be referenced
along with the length of the access. An Interface
Processor can request to read or write up to eight
byt~s in a single memory access.
.
, The multiprocessor architecture of the iAPX 432
places requirements on the ,memory system to ensure·the integrity of data. If several processor were
permitted to read and modify the same data structure without coordination, the data could become inconsistent or erroneous. Therefore, indivisible readmodify-write operations are necessary to manip41ate
syStem objects.
When an RMW-read is' processed for a location in
memory, any other RMW-reads to that location must
/ be delayed to that location until a RMW-write to that
location has been received (or until an RMW timeout
has occurred). While the meniory system is awaiting, '
the RMW-write, however, other types of reads and
writes are permitted.
Even so, if an operand is a double-byte or longer,
the memory system must,still ensure that the entire
operand has been read or written before once again
allowing access to the same location. For example,
if two simultaneous writes to the same location 0ccur, the memory system 'mus,\ guarantee that the set
of locations used tel store 1he operand does not get
changed to some interleaved combination of the two
written values.
5-69
\
.I
1718740002
inter
IAPX43203
Designing Fault-Tolerant Systems
When used together, the five' components in the
iAPX 432 family provide all the logic necessary to
build a system that will tolerate the failure of any
single component or bus, yet continue to execute
programs without error and without interruption. No
software intervention is required: fault detection, isolation, and reconfiguration of the system is performed entirely by the hardware.
Each Interface Processor is able to detect hardware
errOrs automatically because of a capability known
as Functional Redundancy Checking (FRC), so
called because a second or redundant IP checks the
operations of the first or master IP. Functional Redundancy Checking provides the lOW-level hardware
support upon which hardware fault-tolerant modules
are constructed.
During initialization, each IP is assigned to operate
as either a master or a checker (see Figure 10).
While a master operates in a conventional manner, a
checker places all output pins that are being
checked into a high-impedance state. Those pins
which are to be checked on a master and checker
'are parallel-connected, pin for pin, such that the
checker is able to compare its master's o!Jtput pin
values with its own. If on any cycle, the values differ,
the checker asserts HERR and the faulty components can be immediately disabled. Thus, any hardware errors can be detected as they occur and before they have had the opportunity to corrupt the
operation of other components in the system.
MASTER
-r--"
OUTPUTS r--:--
INPUTS
..........
,
......
CHECKED
OUTPUTS
INPUTS
I-
-
HERR
CHECKER
171874-11
Figure 10. Function redundancy checking
detects hardware errors automatically
,
,
While FRC can be used alone to provide automatic
error detection, a completely fault-tolerant system
must also be able to reconfigure itself, n'!placing the
set of failed components witl;i another pair that is still
working. In order to do so, the 432's architecture
enables two pairs of masterI checker components to
be combined to form primary and shadow proces-
sors in a configuration known as Quad Modular Redundancy (QMR). See Figure 11.
.
•
Every module in a QMR system is paired with another self-checking module of the' same type. The pair
of self-checking modules operates in lock step and
provides a complete and current backup for all state
information in the module. The mechanism is known
as module shadowing because a shadow is ready to
fill in if the primary fails (or vice versa). Fault detection a~d recovery occurs transparently to both application and system software. When a fault is detected, the faulty pair is automatically disabled, and the
remaining pair takes over. Only then is system software notified that a failure has occurred.
A more complete discussion of the fault-tolerant capabilities of the iAPX 432 can be found in the IAPX
43204-IAPX 43205 Fault Tolerant Bus Interface
and Memory Control Units data sheet (Order Number 210963).
Processor Packet Bus Definition
Processors sharing the same memory must contend
for access to that memory over one or more system
buses. Therefore, efficient bus utilization is essential
in a multiprocessing system. A simple and efficient
approach to building a 432 interconnect system is to
use the iAPX 43204 Bus Interface Unit; the VLSI
component provides the necessary Circuitry to interconnect 432 processors with from one to eight
memory buses. Some system deSigners, however,
may Plefer to take other approaches to the interconnect design to optimize the cost/performance ratio
of the hardware for their specific application. With
that requirement in mind, Ihtel formulated an iAPX
432 packet bus protocol which supports a wide
range of system bus architectures.
To reduce bus occupancy and increase the performance range of 432 systems, the packet bus protocol
separates processor requests and replies into separate packets. A processor can issue a request packet and leave the system bus free until the reply packet is returned from memory.
As a second method of maximizing the efficiency of
bus utilization, the packet bus protocol allows variable length packets of data. If a processor wishes to
read a 64-bit operand, it can be done with a single
request and reply packet. Thus, fewer individual
storage requests are required to process long operands. This aspect of the protocol enabtes processors to interface easily to 16-bit, 32-bit, or even 64bit system buses.
5-70
171874-002
inter
IAPX43203
r-----------------~
I
I
I
I
I
I
I
QMR
PROCESSOR
MODULE
HARDWARE
RECOVERY
FRC
PROCESSOR
MODULE
HARDWARE
SELF·CHECKING
BASIC
PROCESSOR
MODULE
SOFTWARE·PROGRAMMABLE
RECONFIGURATION
I
I
I
I
I
I
________________
JI
MEMORY BUS
i------- j
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
MEMORY BUS JI
lI _______
r--------
MEMORY BUS
171874-12
Figure 11. Fault·Tolerant Alternatives
This section describes the 19 Signal lines that compose the Processor Packet bus and their timing'relationships. While this section defines all valid bus activities, the processors do not necessarily perform all
allowed activities; nevertheless, slaves to the Proces~r Packet bus must support all state transitions
to ensure compatibility.
PRQ has two functions whose use depends upon
the application; for example, PRO either indicates
the first cycle of a transaction on the bus or the cancellation of a transaction initiated during the previous
cycle. Of the three control lines, BOUT has the simplest function, serving as a 'direction control for buffers in larger systems which require more electrical
drive than ~he processor components can provide.
The ICS signal has three different interpretations depending on the state of the Processor Packet bus
transaction. It may indicate whether or not:
The Processor Packet bus consists of three control
lines:
• PRO (Processor Packet bus request)
•
• BOUT (Enable Buffers for Output)
• ICS (Interconnect Status)
•
•
5-71
An interprocessor communication (IPC) is
waiting,
A slave requires more time to service the
processor's request, or
A bus error has occurred.
171874·002
iAPX43203
The bus also includes 16 three-state Address/Control/Data lines (ACD15':'ACDo). These lines emit information to specify the type of cycle being initiated;
transmit addresses, data to be written, and control
information; and during a read operation, receive
data returned to the processor. Details of the ACD
operation are summarized in Figure 12.
. first cycle, the low-order ACD bits (ACD7-ACDo)
contain the least significant eight bits of the 24-bit
address.
Address/Control/Data Lines
During the next cycle (T2), the remainder of the address is presented on the ACD pins, aligned so that
the most significant byte of the address is on
ACD15-ACDa while the mid-significant byte is on
ACD7-ACDo. If PRO is asserted during T2, the access is cancelled and the ACD lines are not defined.
In the first cycle (T1 or Tvo) of a Processor Packet
bus transaction (indicated by the rising edge of
PRO), the eight high-order ACD bits (ACD15-ACDa)
specify the type of the current transaction. In this
During the third bus cycle (T3 or Tw) of a Processor
Packet bus transaction, the processor presents a
high impedance to the ACD lines for read transactions and asserts data for write transactions.
171874-13
Initial State Next State
Ti
T1
Ti
T1
T2
T2
T3
Tw
T1
n
T3
Tv
T3
Tw
Tv
Tvo
Ti
T1
Tvo
TW .
T2
Tw.
T3
. Trigger
Bus cycle desired
No bus cycle desired
Unconditional
ICShigh
ICSlow
Cancelled, Access Pending (Not generated by IP)
Cancelled, No Access Pending
Additonal transfer required, ICS high
Additional transfer required, ICS low
All transfers completed. no overlapped access
Current write with overlapped access
No access pending
Access pending
Unconditional
ICSlow
ICShigh
Figure 12. Processor Packet Bus State Diagram
5-72
171874-002
IAPX4320S
Once the bus has entered T3 or T¥, the sequence of
state transactions depends on the type of cycle requested during the preceding T1 or Tvo. Accesses
ranging in length from 1 to'32 bytes may be requested, although the IP will request no more than 8 bytes
in a single access (see Table 2). If a transfer of more
than one double byte has been requested, ;f3 must
be· entered for every double byte that is transferred.
ICS dictates whether the processor simply enters T3
or first enters Tw to wait.
significance signals the processor that an IPC has
been received. While an iAPX 432 processor is only
required to record and service one IPC or reconfiguration request at a time, logic in tt)e interconnect
system must record and sequence multiple (and
possibly simuJtaneous) IPC occurrences and reconfiguration requests. Thus, the logic that implements
ICS, must accommodate global and locaIlPC arrivals
and requests for reconfiguration as individual
events:
After all data is transferred, the processor enters either Tv or Tvo. Tvo can be entered only when the
processor is prepared to accomplish an immediate
write transfer (overlapped access). During Tvo, the
ACD lines contain address and specification information aligned in the same fashion as T1. If the
processor does not require an overlapped access,
the bus state move to Tv (the ACD lines will be high
impedance). After Tv, a new bus cycle can be initiated with T1, or the processor may enter the idle state
(Ti).
1. Assert IPC significance on ICS for the arrival of an
IPC or reconfiguration request.
Interconnect Status (ICS)
As discussed earlier, ICS has three possible, interpretations depending on the current state of the bus
transaction (see Table 3). Even so, under most conditions ICS indicates whether or not an IPC is pending; a valid low during any of these cycles with IPC
2. When the iAPX 432 processor reads interconnect
address register 2, it will respond to one of the
status bits for the IPC or reconfiguration request signalled on ICS in the following order:
BIT 2 (1 = reconfigure, 0 = do not reconfigure)
BIT 1 (1 =globallPC pending, O=no globallPC)
BIT 0 (1 = local IPC pending, 0 = no local 1pC)
3. The logic in, the inte{COnnect system must clear
the highest order status bit that was serviced by th8
iAPX 432 processor, and if an additionallPC message has arrived, ttle interconnect logic must signal
an additional IPC to the processor by setting ICS
high for at least one cycle and then setting ICS low
for at least one cycle, while ICS has IPC significance.
Table 2. ACD SpecIfIcatIon Encoding
ACD'
ACD
ACD
ACD
ACD
ACD'
15
14
13
12
10
Acceaa
Op
RIIW
11
Length
000-1 Byte
001·2 Bytes
010-4 Bytes
011-8 Bytes
100-8 Bytes
101·10 Bytes·
110-16 Bytes.
111-32 Bytes·
0Memory
0Read
1Interconnect Space
1Write
0Nonnal
1RMW
State
IPC
T3,Tw
Stretch
TV,Tvo
Err
ACD
8
ACD15 - 0:
OO-lnstSag
Access
01-Stack Sag
Access
10-Context CU
SegAccess
i
11-Other
ACD15 = 1: ,
OO-Reserved
01-Reserved
10-R8eerved
11-lnterconn
Register
ICS InterpretaUon
Level
Slgnlllcance
TI, T1, T2
•
lIocIfIenI
• Not implemented
Table 3.
ACD
High
NolPC
writing
Don't·
Stretch
Bus Error
5-73
Low.
IPC
writing
Stretch
No Error
171874-002
inter
IAPX4320S
Processor Packet Bus Request (PRQ)
Processor Paeket Bus Timing
PRO is normally low and goes high only during T1,
T2, and Tvo. High levels during Tvo and T1 indicate
the. first cycle of an access. A high level during T2
indicates that the current cycle is to be cancelled.
See Table 4.
Eabh timing diagram shown on the following pages
illustrates the timing relationships on the Processor
Packet bus during various types of transactions. This
approach to transfer timing allows maximum time for
the transfer to occur and yet guarantees hold tim.e.
Table 4.
PRQ Interpretation
PRQ
0
State
n
n
Always
Initiate access
Continue access
Cancel access
Always
Always
Always
Initiate overlapped access
1
T2
0
T3
Tw
Tv
Tvo
1
0
0
0
1
Any agent connected to the Processor Packet bus is
recognized as either a processor (a GOP or IP) or a
slave (e.g., the memory subsystem). '
Condition
In all transfers between a processor and a slave, the
data to be driven is clocked for three·quarters of a
cycle before it is sampled. This allows adequate time
for the transfer and ensures sufficient hold time after
sampling. The BOUT timing is unique because
BOUT functions as a direction control for external
buffers.
Enable Buffers for Output (BOUT)
BOUT is provided to control external buffers when
they are present. Table 5 and Figures 13 through 18
show its state under various conditions.
Table 5.
Detailed set·up and hold times can be found in the
AC Charcteristics section.
BOUT Interpretation
Low·to-Hlllh High-to-Low Hlllh·to-Low
Transition
Traneltlon
orL_
or Low
AIwe,aHlgh
BoU1
Write n, T2, T3, Tw, Tvo Ti
n,Tv
Read T1,T2
Transition
or High
' Tv
None
None
T3,Tw
NOMINAL WAITE CYCLE
5 CLKA CYCLES
T,
T,
Tv
CLKA
AeD15··
ACDo
,_uuuuu{ ADDA/SPEC >{
I
PRQ
ICS
IPC
X
ADDA
>.{ WRITE DATA }_u'-_uuuu_u_____ {
l
\
IPC
ADDRISPEC
X
IPC
Y
STRETCH
'<
ERR
\
BOUT - - - '
X
IPC
X
>{
ADDA
}-
IPC
x:
\
IPC
X
I
171874-14
ACD15 ACD. ACDrACDo State
Hi-Z
Spec
Hi·ad,
Hi-data 1·
Hi-Z
Hi-Z
Spec
Hi-ad,
• Undefined
Hi-Z
Lo-ad,
Mid-ad,
Lo-data1
Hi-Z
Hi-Z
Lo-adr
Mid-ad,
~
Ti
T1
T2
T3
Tv
Ti
T1
T2
slngl!J byte write
, Figure 13. Nominal Write Cycle Timing
5-74
171874-002
ACD1SACD. ACD,ACDo StIlle
Tv··
Hi-Z
Hi-Z
Spec
T1
Lo-adr
Hl-adr
Mid-adr
T2
HI·data1'
Lo-data1
T3
Spac
Lo-adr
Tvo
HI-adr
T2
MId·adr
Hi-data1
Lo-data1
T3
'Undefined if single byte write
"(Preceded by read cycle)
Figure 14. Minimum Write Cycle Timing
CLKA
ACD" .••ACDO -----------
PRQ
lea
IPC
BOUTJ
171874-16
HI-Z
Spec
Hi-adr
Hi-data1
Hi-data2
Hklata2
Hi-Z
Hi-Z
HI-Z
Lo-adr
Mid-adr
Lo-data1
Lo-data2
Lo-data2
HI-Z
Hi-Z
Ti
T1
T2
T3
Tw
T3
Tv
Ti
Figure 15. Stretched Write Cycle Timing
,
-',
~,
5-75
"
171874-002
IAPX43203
MINIMUM READ CYCLE
I·
"I
I
5 ClKA CYCLES
T,
T,
T.
, T,
Tv
T,
ClKA
ACD .....ACDo _________ _
PRO
ICS
'-----
_ _ _ _"
- - - - - - - - - - - - - - - - { ADDR/SPEC
>C
---IPC
\\....---_...1/
BOUT - - - '
171874-17
AC01SACDa A~ACDo
State
Hi-Z
Ti
Spec
Hi-adr
Hi-data"
HI-Z
Hi-Z
Spec
Hi-Z
Lo-adr
Mid-adr
Lo-datal
Hi-Z
Hi-Z
Lo-adr
Tl
T2
T3
Tv
Ti
Tl
"Undefined if SIngle byte read
Figure 16. Minimum Read Cycle Timing
MINIMUM READ CVClE (8UFFERED SVSTEM)
I·
"I
6 ClKA CVClES
ClKA
ACDIS ... ACDoo ___________ {
/
PRO
ICSX
"DDR/SPEC
IPC
X
X
"DDR
}-------------,--{
RE"DDAT" } - - - - - - - - - - - - - - - - { "DDR
.\
IPC
X
IPC
~
STRETCH
/
STRETCH
~
\
80UT--1
ERR
X
.PC
"x::::
/
171874-18
ACD15ACDa
Hi-Z'
Spec
Hi-adr
Hi-Z
Hi-datal"
HI-Z
Hi-Z
A~ACDo State
Hi':'Z
Ti
Lo-adr
Tl
Mld-adr
T2
Hi-Z
Tw
Lo-datal
T3
HI-Z
Tv
Hi-Z
Ti
'Undefined if SIngle byte read
Figure 17. Stretched Read Cycle nmlng
5-76
17187.4-002
inter
IAPX43203
IT,
·1
2 CLKA CYCLES
T,
1
T,
T,
1
T,
T,
Tv
T,
CLKA
AC0 15 ..
ACD. _____ _
•
\~------------------------------------------------------------------
CANCEL
PRO--i
NO
SIGNIFICANCE
IPC
IPC
IGNORE
COMPLETE~Y
171874-19
ACD15 ACDa
ACIl?ACDo
State
Hi-Z
Spec
Undefined
Spec
Hi-adr
Hi-data'
Hi-Z
Hi-Z
Hi-Z
La-adr
Undefined
Lo-adr
Mid-adr
Lo-data
Hi-Z
Hi-Z
To
T1
T2 u
Tt
T2
T3
Tv
Ti
'Undefined if single byte writa
"Access Cancelled
tNew Access Started (Slave must support this subsequent
access even though all processors may not implement it.)
Figure 18. Minimum Faulted Access Cycle
ELECTRICAL CHARACTERISTICS
Tables 6 through 8 and Figure 19 through 24 provide electrical specifications and include 1/0 timing, readl
write timing, and the maximum ratings for the IP.
Tabl e 6
43~03
Abso ute Max mum Ratngs
I
AbllOlute Maximum Ratln".
O"Cto 70"C
-55'Cto +15O"C
-1Vto +7V
2.5 Watts
Ambient Temperature Under Bias
Storage Temperature
Voltage on Any Pin with Respect to GND
Power Dissipation
Table 7
Vee
= 5V ±
IAPX 43203 DC Characteristics
10%
T.
= O"C to 70'C
Spec
De8Crlptton
Min
Max
Unlta
VILe
VIHC"
VIL
VIH
VOL
VOH
Icc
IlL
10
IOL
Clock Input Low Voltage
Clock Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Power Supply Current
Input Leakage Current
Outut Leakage Current
@O.45Vol
HERR
-0.3
3.5
-0.3
2
+0.5
Vcc+ O.5
0.8
VCC+ 0.5
0.45
Vcc
450
±10
±10
V
V
V
V
V
V
mA
8
4
4
2
-0.1
mA
mA
mA
mA
mA
10H
-
2.4
FATA[
AD15" . ADo
OTHER
@2.4VQH
vA
vA
'For operation at 5 MHz or slower, the 43203 may be. operated with a VIHC minimum of 2.7 volts.
5-77
171874-002
IAPX43203
Table 8. IAPX 43203 AC Characteristics
Vee = 5 ± 10%
TA = O"C to 70"C
Symbol
Loading: AD15 ... ADo ............... 20 to 100 pF
Other ....................... 20 to 70 pF
Description
Min
,
8 MHz
Max
Global Timing Requirements
Clock Cycle Time
125
lov
tr, t1
Clock Rise and Fall Time
T1, T2
T3,T4
Clock Pulse Widths
26
INIT to Si9!!!! Hold Time
15
tiS
~al to INIT- Setup Time
10
tSI
INIT Enable Time
8
tiE
System Side Timing Requirements
Signal to Clock Setup Time ,
5
toe
Clock to Signal Delay Time
te~
Clock to Signal Hold Time
25
tOH
Clock to Signal Output Hold Time
15
toH
Clock to Signal Output Enable Time
15
tEN
Clock to Signal Data Float Time
tOF
Peripheral Subsystem Side Timing Requirements
tAS
teH
tss
tSH
tsw
tos
tox
tOHX
tASV
AD15 ... ADo, CS, WR, BHEN
Setup Time to ALE Low
AD15 ... ADo, CS, WR, BHEN
Hold Time to ALE Low
SYNC High Setup Time to
CLKAHigh
SYNC Low Hold Time to
CLKAHigh
SYNC High Pulse Width
Write Data Setup to
Sampling CLKA High
Write Data Hold to Sam~
CLKA Low (Advanced XACK)
Write Data Hold to XACK
AD15 ... ADo, CS, WR, BHEN
Setup to SYNC
Min
143
5QO
10
,250
-
200
30
20
10
8
250
45
20
10
8
5
-
55
-
35
15
20
55
-
0
-
0
32
-
35
50
-
60
-
40
80
30
50
10
10
5
120
5-78
tsS+
1.5 lov
-
Min
500
10
-
•
7 MHz
Max
-
20
20
5
160
--
85
-
5
500
10
250
-
-
-
85
75
-
35
20
20
75
-
-
0
tSS+
1.5 lov
5 MHz
Max
35
60
40
60
-
tSS+
1.5 tev
Unit
ns
ns
,
ns
ns
ns
lov
ns
ns
ns
ns
ns
,ns
, ns
ns
ns
ns
ns
-
20
-
ns
-
20
5
-
ns
ns
-
160
-
ns
171874·002
inter
IAPX43203
Table 8.
Symbol
IAPX 43203 AC Characteristics (Continued)
Description
8 MHz
Min
Max
7 MHz
Min
Max
-
80
-
·80
-
5MHz
Min
Max
Unit
Peripheral Subsystem Timing RespOnses
tsDH
tAIH
tEDE
tEND
tDAD
teED
teVD
tax
tDDs
tXDE
CLKA High to HLD, INT, PSR
Valid AD15 ... ADo, CS
to ChiP WH1 Valid Delay
DE to D N Delay
DE to Enable AD15 ... ADo
Buffers Delay (Read Cycle)
DE to Disable AD15 ... ADo
Buffers Delay (Read Cycle)
CLKA High to Enable
AD15 ... ADo Buffers Delay
CLKA High to Valid
Read Data D~ .
DE Inactive to A K
Inactive Delay
AD15 ... ADO Disable
Setup to DE~High
XACK Low to EN High
(Write Cycle)
CLKA High to DEN Low
g
teDE
XACK Timing Characteristics
tAX
tDSX
tADX
tDSX
tSDl
tSNX
Buffered Accesses with XD = 0
ALE High to XACK Valid
AD15'" ADo Read Data Valid
Setup to XACK Valid
(When internal state does not
allow XACK before SYNg)
Valid AD15.' . ADo to XA K
Valid (When Internal State
allows XACK before SYNC)
Buffered Accesses (with XD = 1 or
XD = 2) or Random Accesses
AD15·· . ADS Read Data Valid
SetuptoXA K
Faulted Accesses
CLKA Low to NAK
Setup of NAK"to XACK
~
75
80
65
70
52
70
90
-
90
ns
85
70
-
85
70
ns
ns
75
75
ns
52
ns
75
ns
90
ns
90
-
90
ns
52
75
90
0
-
0
-
0
-
ns
-
35
70
-
40
75
-
40
75
ns
ns
0
65
0
70
0
70
ns
20
-
20
-
20
-
ns
-
120
-
140
-
140
ns
20
-
20
-
20
-
ns
-
75
-
-
90
50·
-
50
-
50
ns
ns
-
NOTES:
1. All timing parameters are measured at the 1.5V level except for ClKA and ClKs which are measured at the 1.8V level.
2. 5 MHz components are marked CR43203-5; 7 MHz components are marked CR43203-7, and 8 MHz components
CR43203-8.
3. Write data is sampled for only one clock cycle. The PS must meet tOHx speCification. thereby guaranteeing tox.
5-79
171874-002
'",.'
IAPX43203
CLKA
CLKA
ACD1S",ACDO'
iREADDATA
INVALID
TIMINGI
loe
CLK_
INValiD
INVALID
IDC
171874-20
tDN
171874-22
figure 18: 43203 Clock Input SpecItIcetIon
Figure 21. 43203 Input 1:1mlng SpecIfIcation
CLKA
CLKA
-
... IDC
ALL OUTPUT
PINS
EXCEPT lOUT
ION _SIDE) --+---I-'I'--If---I-~lSI
80UT
MASTER/CHECKER
171874-23
171874-21
figure 20. 43203 Output nmlng SpecIfication
Figure 22. 43203 Inltbllizatlon nmlng
'5-80
171874-002
IAPX43203
-
r-\
VALIDAOU
~
VALID WRITE OA'A
.....
WOO ••
.
-d ~~~r--Ft--~
.....
-I=.;; ::!j'1
1--+,
~.
=
..... ""
-:-~-=±;~
~'w.
....
~
liD.'
1I0.'I11I!AD
lID.IWIII
:.:,11
I-- '---1
1-""-1
I-
....--==:1.
r>.-·"
~~
.,ALlDWIUTEOA'..
VAUDAGOfI
~
~
~-
t-~.,
f--IO_0-r-IDOS~
Vall. RlAD OA'A
'll'AUDAODR
r---""- r--
~"-j
171874-24
Figure 23.
I
cc"
'"
·il
10
o·
I
iii
j
~
~--r-l--~~IL-
~
I - - f-.... ~
SYNC
~
{
Local Processor Bus Timing
.~
~
...
1-101
~
om
:;:i i
"'41
I-~
n
!I
'. '"
. ".,......
~
!-'-1
_....1-"-
~".
..1
VAUOAOO_
~~~.
VAlIOWRITEOAlA
-"'''-I
~
e:
""
I-
YAUOAOORESS
IO~~
IEMl
-""'-I
1---..
VALlO.U.ODA'A
_.,,,:3=
171874-25
NOTES:
1.
2.
@ and @ could be the same clock edge for a buffered mode read.
lID Clock edge ~Id be one or two clocks after clock edge @. depending on the value of the write sample delay.
Figure 24.
Multlbusl8l Interface Timing
5-81
171874-002
IAPX43203
'INSTRUCTION SET
Table 9 compare$ the operators available in the IP's
plex (multi-segment)' obJ~, gaining acCess to its
component. segments. It can also perform amplificafunction set to those provided in the GDP's instruction on both hardware-recognized typed objects and
tion set. Since windows are unique to Interface Proc. software-recognized types. When manipulating obessors, the ALTER MAP AND SELECT OBJECT
jects of a protected type, an I/O controller is acting
function has no counterpart in the GDP. Conversely,
the IP has no functions for performing arithmetic op- " as a type manager, and its objects must be coordinated with the 432 type manager for the qbJect.
erations (except for the atomic function INDIVISIBLY ADD SHORT ORDINAL) or logical operations
The Interface Processor provides the I/O controller
on numeric (lr character data types, nor does it have
with both process and processor communication faany operators .to alter the flow of execution (e.g.,
cilities. Interprocess communication is asynchrobranch or call fU!1ctions).
nous and is performed with the aid of ports, system
objects that provide synchronization and message
To the extent that these classes of operators are
needed in a peripheral subsystem interface, they
queues. Any object may be sent as a message from
can be provided by a combination of the AP's ina process to a port.
struction set and the IP's window faCility. By opening
a window, for example, on a message received from
Interprocessor communication messages arepredea GDP process, the I/O controller can use AP infined (see Table 10). The I/O controller can send
structions to test and branch on the value of a mesone of these messages to an individual processor,
sage filed read through the window.
or it can broadcast the message to all processors in
the system.
Through i,ts windows, an IP provides the basic ability
The IP also provides an optimized data passing facilto read and write the contents of the data parts of
objects. Using its function 'request facility, however,
ity by using objects of type IP-Message and the
an IP can manipulate Access Descriptors (ADs),
OPEN MESSAGE and CLOSE MESSAGE operawhich reference objects. The IP can examine a comtors.
Table 9. IP/GDP Operator Comparison
Operator
Implementation
WINDOW DEFINITION OPERATOR
~Iter Map and Select Object
IP
, ACCESS DESCRIPTOR MOVEMENT OPERATORS
Copy Access Descriptor
Null Access Descriptor
Move to Embedded Data Value
GDP+IP
GDP
. Similar
RIGHTS MANIPULATION OPERATORS
Amplify Rights
Restrict Rights
GDP+IP
GDP
l)'PE PEFINITION MJ\NIPULATION OPERATORS
. Retrieve Type Definition
GDP
REFINEMENT OPERATORS
Create Refinement
Create Typed Refinement
GDP
GDP
.
, OBJECT CREATION OPERATORS
Create Object
Create Typed Object
GDP
GDP
ACCESS INSPECTION OPERATORS
Inspect Access Descriptor
Inspect Object
Equal. Access
GDP+IP
GD,~+lP
GDP
5-82
,.'
171874-002
inter
IAPX43203
Table 9.
IP/GOP Operator Comparison (Continued)
Operator
Implementation
ACCESS INTERLOCK OPERATORS
Lock Object
Unlocked Object
,
Indivisibly Add Short Ordinal
Indivisibly Add Ordinal
Indivisible Insert Short Ordinal
Indivisible Insert Ordinal
CONTEXT OPERATORS
Enter Environment
Enter Global Environment
Set Context Mode
Adjust Stack Pointer
Call
Call through Domain
Return
Return and Fault
PERIPHERAL SUBSYSTEM,MODE OPERATOR
Set Peripheral Subsystem Mode
PROCESS COMMUNICATION OPERATORS
Send
Receive
Conditional Send
Conditional Receive
Surrogate Send
Surrogate Receive
Delay Process
Send Process
Dispatch
Set Process Mode
Read Process Clock
Open Message
Close Message
PROCESSOR COMMUNICATION OPERATORS
Send to Processor
Read Processor Status
INTERCONNECT OPERATORS
Move to Interconnect
Move from Interconnect
BLOCK-MOVE--oPERATORS
BRANCH OPERATORS
CHARACTER OPERATORS
SHORT-ORDINAL OPERATORS
SHORT-INTEGER OPERATORS
ORDINAL OPERATORS
INTEGER OPERATORS
SHORT-REAL OPERATORS
REAL OPERATORS
TEMPORARY REAL OPERATORS
.
GDP+IP
. GDP+IP
GDP+IP
GOP
Similar
GOP
GDP+IP
GDP+IP
GOP
GOP
GOP
GOP
GOP
GOP
,
IP
GDP+IP
GDP+IP
GDP+IP
GDP+IP
GDP+IP
GDP+IP
GOP
GOP
IP
GOP
GOP
IP
IP
GDP+IP
GDP+IP
.,
GOp·
GOp·
GOP
GOP
GOP
GOP
GOP
GOP
GOP
GOP
GOP
GOP
Legend:
GDP+IP
IP
GOP
similar
.
IP and GOP implementations are identical.
IP implements operator, GOP does not.
GOP implements operator, IP does not.
While conceptually similar, IP implements operator differently than GOP.
Window 1 of IP provides equivalent interconnect access.
5-83
171874-002
'IAPX43203
Table 10. IPC Mesaaae Codes
The following list contains the Interprocessor Communication message codes in decimal along with a
short description of the message:
o Wakeup'
5 Requalify Object Table Cache
6- Reset Processor
7 Requalify ProceS$Or
8-14 Defined for GOP but ignored by IP
1 Start
2 Stop
3 Accept Global IPCs
4 Ignore Global IPCs
package
The 43203 is packaged in a 68-pin. leadless JEDEC type A hermetic chip carrier as shown below.
•050
~___(1~i __~IEnaIm~mornI~--------'
T---
1
I
.800
(2Q.32)
·03I==R
(0.191
1
F
E-
D
.960
(2'.31)
~:'~FP1NNO"
PIN NO. 11
MARK
1-----(24.31)
•
.130
(3.30)
171874-26
Additional Information
More information about the iAPX 432 Micromain,frame architecture can be found in the following publications:
•
•
•
Information on the electrical characteristics of other
432 components can be found in the following publications:
iAPX 432 Interface Processor Architecture,
Reference Manual (Order Number 171863)
iAPX 432 General Data Processor Architecture Reference Manual (Order Number
171860)
iAPX 432 Interconnect Architecture Reference Manual (Order Number 17:2487)
5--84
iAPX 43201/43202 General Data PrOcessor
Data Sheet (Order Number 590125)
• iAPX 43204143205 FauH Tolerant Bus Interface and Memory ep-ntrol Units (Order Num. ber 210963)
• iAPX 43204/43205 BIUlMCU ElectriCal Specifications (Order Number '172867)
•
171874-002
inter
IAPX 43204, iAPX 43205
FAULT TOLERANT
BUS INTERFACE AND MEMORY CONTROL UNITS
•
Software Transparent Dete~on And
Recovery From Any Single Point Failure
•
S~pports Up To 31 Processors For A
,
Large Performance Range
•
Configure From 1 To 8 Buses For High
Bandwidth And Fault Tolerance
•
Single, Dual, and Quad Redundant
Configurations Tailor System Designs
to Meet A Spectrum of Fault Tolerance
And Cost Objectives
•
VLSI System Simplifies Design With
Low TTL Count
•
Dynamic RAM Refresh with Error
Correction and Scrubbing
The 43204 Bus Interface ""nit (BIU) and 43205 Memory Control Unit (MCU) are two VLSI devices that support
the construction of fault tolerant, multiple processor 432 systems. Together they support: multlprocessQr arbitration, dynamic RAM control, and ECC with a minimal amount of TTL. Fault tolerant systems can be built
that,tolerate the failure of any single component or bus. The BIU and MCU detect thEi failure and automatically
switch to a redundant processor, bus, or memory. Hardware failures are completely masked from application
, '
software.
r-------l
PROCESSOR
MODULE
GDP
r-----'
I
I
I
I
I r----,
I
I
I
I
I
I
GOP
IP
'---r-~
MEMORY
MODULE
:
I
I
I
I
I
I
I
I
I
I
I
r
I
MACD
BUS
MACD
BUS
I
I
I
IL
_ _ _ _ _ _ _ .J
ACD
BUS
ACD
BUS
Figure 1. A 2 Bus System with 2 General Data Processors and 11/0 Subsystem.
Intel Corporation Assumes No Responsibility forthe Use of Any Circuitry Other Than Circuitry Embodied in an Intel'Product. No Other Circuit
Patent Licenses are Implied. Information Contained Herein Supercedes Previously Published Specifications On These Devices From Intel.
@> INTEL CORPORATION. 1983
October 1983
ORDER NUMBER: 210983-002
5-85
.,
..
,
---~~--.--
.
IAPX 43204, 43205
INTRODUCTION
The first phase'of the iAPX 432 program introduced
two processor types: the General Data Processor
(GOP) and the Interface Processor (IP). The GOP
was implemented with twoVLSI components: iAPX
43201 and iAPX 43202. The IP was Implemented as
a single VLSI component: the iAPX 43203. These
three VLSI components Implement the processor
architecture for the,iAPX 432. System builders have
constructed multiple processor systems by surrounding the VLSI processors with discrete logic.
which provided the interface to shared memory and
the interprocessor communication paths. The method for interconnecting IAPX 432 processors and
memories was unique for each system. since no
standard had been defined.
This data sheet describes ,a pair of VLSI components: the iAPX 43204 Bus Interface Unit (BIU) and
the iAPX 43205 Memory Control Unit (MCU) that
form a unifying interconnect architecture for building iAPX 432 systems. Together. these components
form the basis for constructing multiple-processor
fault-tolerant iAPX 432 systems.
The iAPX 432 together with the BIU/MCU interconnect architecture provide:
• Integrated fault tolerance. The VLSI interconnect
components (BIU/MCU) integrate all the detection and recovery logic required to build a system
that can tolerate any single component failure.
• Software transparent fault toler(!lnce. Hardware
performs all fault detection and recovery functions transparent to application software. The
machine never stops.
• Configurability. The BIU and MCU support a
range of fault tolerance and performance options
to meet a diverse set of cost. performance. and
reliability needs,
• Reliable software. The iAPX 432 system's "need
to know" (capability) addressing confines errors.
prot~ing the system from errant software.
The object-based architecture of the iAPX 432 provides a robust and flexible environment for cooperating. concurrent software systems. The iAPX 432
processors use a cooperating. self-dispatching
mechanism to automatically share the workload between the available processors. The number of processors available In the system is transparent to
software.
The BIU and the MCU extend the logical flexibility
and robustness of the iAPX 432 processors into the
physical implementation of iAPX 432 systems. The
BIU and MCU allow the iAPX 432 hardware to modularly and transparently extend the processing power
(from 1 to 63 modules of processors or memories).
bus bandwidth (1 to 8 backplane buses). and faulttolerant capabilities of the system. Figure 1 shows
an example of a two bus three processor (2 GOPs +
1 IP) system.
As Figure 2 shows. an iAPX 432 system based on
the i~terconnect architecture may be exp~nded
gracefully. A system with one processor and one
memory may be built with a single memory bus.
Transparent multiprocessing may be achieved by
simply adding processor modules. When additional
memory is required. memory modules may be added onto the single memory bus. When more memory
bandwidth is required. an additional ·memory bus, (es) can be added. None of these alternative systems require any change to application software.
In an iAPX 432 system. each processor is unaware
of the manner in which the memory address space is
actuailY implemented. Hardware located in the BIUs
determines how processor addresses are mapped
to buses and memory systems.
• Standard VLSI solution. Very little external logic is'
required.
210963-002
"!
inter
iAPX 43204, 43205
ONE PROCESSOR MODULE
ONE MEMORY MODULE
EXPANDED NUMBER
OF MODULES
EXPANDED NUMBER
OF BUSES
Figure 2.
Modular Expansion
BUS INTERFACE UNIT
The Bus Interface Unit or BIU provides the switching
function of the IAPX 432 interconnect system. That
is, it accepts access requests from an iAPX 432 processor and, based on the physical address, it decides which memory bus(es) will be used to perform
the access. The BIU is also responsible for arbitrating the usage of the memory bus. Finally, the BIU is
responsible for propagating error information
throughout the sytem.
MEMORY CONTROL UNIT
The Memory Control Unit or MCU interfaces memorv storage arrays to the memory bus. The 'storage
arrays will typically be constructed with high-density
5-87
dynamic RAM (DRAM) components. All types of
DRAMs are supported: 16K, 64K, 256K, even partially good components. The ~CU manages. the
stf>rage array as a logical collection of 32 data b~ts, 7
bits of error correcting code (ECC), and an optional
spare bit. The'MCU can automatically refresh the
dynamic storage array. In addition, the MCU can
scrub single-bit errors from the storage array as a
background task. Scrubbing is accomplished ~y periodically reading the storage array, correcting all
single-bit errors, and detecting and reporting all
double-bit errors. The MCU accepts variable length
data requests from the memory bus and performs
the necessary access sequencing to read or write
the data into the storage array. A modest amount of
external logic is required to interface the MCU to the .
storage array RAMs - for simple configurations, as
few as 12 external TTL packages are required.
210963-002
iAPX 43~,.43205
dancy Checking (FRC) provides the low-Ie~el I1ardware support on which hardware fault-tolerant
modules are constructed. In Figure 3, notice that a
redundant processor module is formed by replication of the VLSI GOP and BIUs. A redundant memory module is formed by duplicating the VLSI MCU .
The unshaded GOPs, BIUs, and MCUs act as masters. The shaded oomponents act as checkers,
which observe their master arid report any disagreement they detect in the values the master produced.
MEMORY BUS
The memory bus (sometimes referred to as the
MACO bus) provides the principal communication
path, carrying all memory 'access requests and interprocessor cornmunication. The memory bus con.nects BIUs to MCUs. Each node in the interconnect
system tracks each operation on the memory bus to
·which it is attached. Thus, unlike most bus protocols, each BI U and MCU keeps track of all outstanding requests on the bus - not just the ones made by
the BIU or MCU itself. Control for the bus is fully
distributed; there is no centralized bus controller.
When any error occurs, a special error reporting
network notifies all'nodes in the system of the discrepancy. Figure 4 illustrates the flow of error information in the interconnect system. In phase 1, an
error is -detected at a node in the interconnect system. The example illustrates an error detected at
BIU(2,1); I.e., the BIU on memory bus 2 in processor
INTEGRATED FAULT TOLERANCE
BIUs and MCUs ,also form the basis for building
fault-tolerant iAPX 432 systems. Functional Redun-
r----
- - - - - - - - - - - - - --,
,-----
-- - --- ------.,
REDUNDANT MEMORY MODULE
REDUNDANT PROCESSOR MODULE
MASTER
CHECKER
GDP
L __________
~
____
J
I
I
I
I
I
I
I
~
-CHECKER
L~---------~~-----~
Figure 3. . FRCConfiguratlon pairing
5:aB
210963-002
iAPX 43204, 43205
MODULE 0
MODULE 1 .
MODULE 0
MODULE 1
MODULE 0
+-__
MODULE 1
BUSO
-.j....!..--.---+---.--
BUS 0
--1--.,---1---.--
BUSO __
BUS1
--+--.,--~-_r-
BUS 1
---1--.,---1-----.--
BUS1 __
BUS2
_+-___---+---_-
BUS2
---1--,_--1-----.--
BUS2-~--_r--~--~---
BUS3-~-,_-~-_r-
BUS3--~--_r--~--~---
BUS3 --+---.--~-_r-
PHASE 1
81U (2,1) DETECTS AND
REPORTS AN ERROR
PHASE 2
ALL NODES ON BUS 2
KNOW ABOUT THE ERROR
~--~--_,---
+-__
~--~--~--
PHASE 3
ALL NODES
KNOW ABOUT THE ERROR
Figure 4. Three Phase Error Reporting Mechanism
module 1. The detecting component reports the error to all components attached to the same bus (a
bold line indicates a!1 active error reporting path). At
this point, if all error reporting nodes are intact, all
nodes have received the error message. In phase 2,
all components that received the phase 1 error message rebroadcast the message along their module
paths. Finally, in phase 3, each component that has
received an error message rebroadcasts the message along its bus path. This second rebJoadcast
ensures that all nodes receive the error message
even if a single module or bus error report line has
failed. At the end of phase 3, all interconnect components in the system have been informed of the error.
The actual error reporting paths are separate from,
but run parallel to, the MACD and ACD busses so
that error reports may propagate even if a bus is inoperative. In addition, the reporting paths may be
duplicated to remove any single-point dependency
in delivering an error report.
RECOVERY
The recovery process .begins after an error report
message has been broadcast iiround the system.
5-89
Recovery is a distributed operation -- each node in
the system reads the error report message and decides what recovery actions need to be taken.
For recovery to be successful, there must be redundant resources available in the system. There are
three redundancy mechanisms in the BIU and MCU:
bus retry buffers, ECC, and module shadowing. The '
first two are useful in recovering from transient errors, while module shadowing allows recovery from
permanent errors.
Figure 5 illustrates how every module in the system
may be paired with another seft-checking module of
the same type. This pair of self-checking modules
operates i~ lock step and provides a complete and
current backup for all state information in the module. This mechanism is known as module shadowing because a shadow is ready to fill in if the primary
fails, or vice versa. Fault detection and recovery is
performed totally transparent to both application
and system software. When the recovery is complete, system software is notified that a failure occurred. Figure 6 shows sample module failures and
automatic hardware recovery.
. 210963-002
IAPX 43204, '432051
r----------- ----------..,
REDUNDANT PROCESSOR MODULE
PRIMARY
r- - - - - --- -- - --------,
REDUNDANT MEMORY MODULE
I
I
I
I
I
PRIMARY
SHADOW
:
I
SHADOW
I
GDP
GDP
L ______________
J
I
I
I
IL
________ _
______ J
I
I
~
=CHECKER
Figure 5. QMR Configuration Pairing
I
I
I
I
PRIMARY
lI=======:::::!I LI __ ,_______
JI
==___==
SHADOW
Figure SA. Module Failures Are Detected ,
210963-002
". . _I"
, III-e-
IAPX 43204, 43205
Figure 68.
Failed Modules Are Disabled
Figure 7.
Bus Reconfiguration
cally connected to both buses although logically
they are attached to only one ,bus at a time. During
normal operation the buses run independently. Both
contribute to the total memory bandwidth available
in the system. If a bus fails, the memory modules attached to that bus will automatically switch to the
other bus which is still operating. Figure 7 illustrates
how the BIU and MCU reconfigure the system when
a bus fails.
A fault-tolerant module is also called a QMR module
(Quad Modular Redundant) because most components (except memory) are replicated four times.
There are two self-checking modules and each of
these has a master and a checker.
Each memory bus in the system may be paired with
anothen memory bus. Memory modules are physi-
5-91
210963-002
iAPX 43204, 43205
CONFIGURABLE FAULT TOLERANCE
Figure 8 illustrates the range of alternatives available to system designers when they· build iAPX 432
systems. The most fault-tolerant systems are built'
from a OMR configuration of processors that can
tolerate any single component failure without crashing the system. BIUs and MCUs provide full hardware error detection and recovery transparent to
software.
The lowest cost configurations can be built using
basic processor modules without FRC or OMR. This
type of configuration will crash if a component fails,
but can be made "self-healing" by adding intelligent
software to the I/O subsystem. Unlike OMR, selfhealing does not protect against system crashes,
but it does allow the system to recover from a failure
in a short period of time. The "healing" takes place
in 3 steps. First, a watchdog timer in an I/O subsystem alerts I/O subsystem software that the central
system has failed. Second, the I/O subsystem
checks BIUlMCU error logging registers and runs
diagnostics to identify which resource (e.g., processor, bus or memory) has failed. Third, the I/O subsystem re~nitializes the system using the
configuration control within the BIU and MCU to
configure out the failed resource. The system is up
and running without human intervention after only a
short period of down ttme.
,
"",'
a very high degree of confidence that calculations
are performed correctly. A OMR system will do this
since all components have a checker that alerts the
system whenever a mistake is made. However, a
OMR configuration may be overkill for some applications that can tolerate an occasional system failure, as long as the computations are correct when
they do complete. FRC configurations offer an alternative in between the basic and OMR approaches.
Adding a second set of checker components to each
module improves the error detection capabilities of
the system providing "high confidence" computing.
No single hardware failure will, go undetected and
corrupt the results of a critical computation. FRC insures that any error is caught before it can propagate to another/module in the system. FRC alone
does not provide automatic hardware recovery like
a OMR system, but it does detect errors as soon as
they occur so that the system does not become corrupted. It is then the responsibility of system software to implement a "self-healing" strategy where
the faulty resource is disabled and the system reinitialized.
The software configurability of a BIU/MCU system
allows a system to use a combination of the above
strategies. For example, software can configure a
sy,stem as a full OMR system in the morning for critical applications, and then switch to an FRC only system in the afternoon. This doubles the system
throughput (twice as many processors are working
in parallel) without making any hardware changes.
The basic configuration is the lowest cost alternative, but for some applications it is desirable to have
5-92
210963-002
iAPX 43204, 43205
- - --,.
QMR
PROCESSOR
MODULE
HARDWARE
RECOVERY
MEMORY BUS
L ____________
JI
r-------,
I
I
I
I
I
I
III
()
Z
c
I
I
I
FRC
PROCESSOR
MODULE
I
I
I
I
fi
CJ
z
t
III
II:
U
III
CI
I
I
II:
III
oJ
~
!:i
~
HARDWARE
SELF-cHECKING
CJ
Z
!
II:
U
!
I
L
MEMORY
_
_ _ _BUS
_ _ JI
r------..,
I
I
I
I
I
I
BASIC
PROCESSOR
MODULE
SOFTWARE-PROGRAMMABLE
RECONFIGURATION
MEMORY BUS JI
L ______
Figure 8.
Fault-Tolerant Alternatives
210963-002
iAPX 43204, 43205
FAULT·TOLERANT SYSTEM DESIGN
RESPONSIBILITIES
SUMMARY
The iAPX 432 interconnect architecture provides a
standard VLSI method for constructing multiple processor VLSI computer systems. The iAPX 432 interconnect architecture is implemented by a pair of
VLSI components, the Bus Interface Unit (BIU) and
the Memory Control Unit (MCU). Together with iAPX
432 processors, these components permit the construction of modular, extensible, multiprocessor
computer systems. The components are designed
to support the construction of fully fault-tolerant
iAPX 432 systems. However, there is no penalty in
performance or in cost for those applications that do
not require fault tolerance.
The interconnect architecture and the VLSI components provide a stable base for developing faulttolerant iAPX 432 systems. The iAPX 432 interconnect components address the issues concerning
fault tolerance which are encountered when constructing the iAPX 432 central system. A number of
system-wide issues remain the responsibility of the
iAPX 432 system designer. These issues include:
• A fault-tolerant I/O system
• Fault-tolerant power supplies and distribution
method
The 432 fault-tolerant mechanisms are designed to
provide a flexible and complete solution to the problems of fault-tolerant hardware. For basic systems
(those without checkers for error detection or QMR
for recovery), a user may decide to use only a few
detection mechanisms and provide recovery only
for transient errors. This fUnctionality comes at no
additional cost in the VLSI interconnect system. To
reduce maintenance cost and increase system
availability, a system may use all of the detection
mechanisms (Le. may add checker components) but
may not add any extra recovery capability (Le. may
not marry self-checking modules into a fault-tolerant
QMR module). Continuous operation is available to
the user who adds the extra recovery capabilities.
• A fault-tolerant method for clock generation and
distribution '
• The electrical and physical provisions for on-line
repair
None of the fault-tolerant mechanisms reduce system performance. Systems that do not require the
highest level of fault tolerance are not penalized in
any way (cost, size, or performance) for the unused
fault-tolerant capabilities. Increased levels of fault
tolerance are achieved by replicating the iAPX 432
VLSI components. The hardware fault tolerance in
the iAPX 432 is transparent to application software.
The system's fault-tolerant capabilities may be
changed without any changes to the application
software system.
5-94
,
. 210963-002
•
iAPX 43204, 43205
8
N.C.
VSS
MBOUT
CTL2
CTL1
CTLO
MACD15
MACD14
MACD13
MACD12
MACD11
MACD10
MACD9
MACD9
MACD7
MACD8
.. N.C.
vee
ACD15
ACD14
ACD13
ACD12
,43204
MACD5~'~"rlnr'n
ACD11
ACD10
ACD9
ACDe
ACD7
ACD8
ACD5
ACD4
ACD3
ACD2
ACD1
r
1:I:I:I:I:OOO
l:5:ll!:IIZI, ' - PIN NO
l;l;~l;l;Ui ~:l:8i11iUlp§
2fh:'~8"c",
";SO
~
NOTE: N.C. pads must not
be connected.
.1
MARK
Figure 9. 43204 Pin Configuration
ACD(15 ..0)
ffilL-
ICSOUT
ICS
CLRPUOUT
VCC(2..0)
VSS(2..0) ,
CLKA
CLKB
INIT
MERL
MiBl..0UT
MMAL
MMAH
-------++
ACD
BUB
Group
Memory
auB
Group
iAPX43204
BtU
System
Group
Memory
Bus
Arbitration
Group
----
_BCHK
_
gQNT
RQ
_ROOUT
_
NR
++~
Module
Group
Figure 10. iAPX 43204 BtU Logic Symbol
210963-002
I
inter
iAPX 43204, 43205
Table 1.. IAPX 43204 BIU Pin Description
Symbol
Type
Name and Function
Memory Bus Group
MACD15
.. MACDO
I/O·
These 16 bidirectional signals carry physical memory addresses, control information (access length and type), and data to and from the memory bus.
CHK1 .. CHKO
I/O·
These 2 bidirectional signals carry parity bit check information which de- ,
tects errors in transfers on MACD15 .. MACDO and CTL2 .. CTLO. The 2
parity check bits are computed to satisfy the following equations (X = Exclusive OR):
MACD15 X MACD13 X MACD11 X MACD9 X MACD7
X MACD5 X MACD3 X MACD1 X CTL 1 X CHK1 =;' 0
MACD14 X MACD12 X MACD10 X MACDa X MACD6
X MACD4 X MACD2 X MACDO X CTL2 X CTLO X CHKO = 1
The BIU and MCU generate and check even parity (an even number of ones)
across the 10 odd-numbered MACD; CTL, and CHK signals, and odd parity
(an odd number of ones) across the 11 even-numbered MACD, CTL, and
CHK signals.
CTL2 .. CTLO
I/O·
The 3 MACD bus control signals carry a code that controls the sequencing
of the memory bus.
MBOUT
I/O··
MBOUT controls the direction of external buffers for th,e MACD, CHK, and
CTL signals. When MBOUT is asserted, it indicates that the buffers must be
directed to carry information outbound from the component to the memory
bus.
BERLOUT
0
BERLOUT supplies bit-serial bus error messages when the component detects a memory bus error, a storage array error, or a memory module error.
BERL1,
BERL2,
I
I
BERL 1 and BERL2 are duplicate paths on which the component receives
bit-ser!al bus error messages from the memory bus. When duplicated paths
are not required, these two pins must be supplied with the same bus error
report information.
BCHK
I/O·
,
BCHK provides a mechanism which checks that external buffers are operating. BCHK is toggled once each clock cycle by the component that is driving
it. In an FRC pair, the master component drives BCHK. The checker component in the FRC pair receives BCHK. Routing BCHK from the master component, through one' buffer in each external buffer package, and to the
checker component, forms a serial network. If the oscillating BCHK signal
fails to traverse the external buffer network, the buffer path is suspect and a
bus error will be signalled. Buffer checking can be disabled by interconnect
register programming.
5-96
210963-002
•.... _I
1
••'eI .
e
iAPX 43204, 43205
Table 1. iAPX 43204 BIU Pin Description (Continued)
Symbol
.
Type
Name and Function
Memory Bus Arbitration Group
CONT
I
The CONT input indicates if the external arbitration network has detected
that.two or more simultaneous requests have been made for the use of the
memory bus. When contention is indicated, all contending components will
perform a binary arbitration sequence (based on each component's unique
6-bit module 10) to decide which component will be granted first use of the
memory bus.
RQ
I
T~
~
RQ input indicates if any agent is requesting the use of the memory bus.
There are three valid combinations for RQ and CONT:
RQ
1
0
0
CONT
1
1
0
Interpretation
No request
One BIU is making a request
Two or more BIUs are making a request
The MCU does not generate any memory bus requests. The MCU tracks the
action of RQ and CONT, and the CTL(2 .. 0) signals to determine when it is
allowable to use the memory bus to reply to a request.
RQOUT
I/O··
When asserted, ROOUT signals that the component requires the use of the
memory bus. ROOUT is intended to drive an external open-collector inverter which is wire-ORed to form a combined RQ line. The ROOUT signal from
all BIUs attached to a memory bus must be logically combined to form a contention signal. (Contention occurs when tWo or more BIUs issue RQOUT simultaneously). The logic to detect contention among BIUs must be supplied
by the customer.
NREQOUT
I/O·
The NREOOUT signal indicates that the component has received a new request from its associated processor. NREOOUT is intended to 'drive an external open-collector inverter, which i$ wire-ORed (with the same signal
from other BIUs on the memory bus) to form NREQ.
NREQ
I
I
NREQ is ,an input that signals the beginning of a new time-ordered request
cycle in which a request from one or more processors must be managed. -
5-97
21Il963-002
iAPX 43204, 43205
Table 1.
Symbol
iAPX 43204 BIU Pin Description (Continued)
Type
Name and Function
MERL
I
The MERL input accepts bit-serial module error messages. See the
BERLOUT pin description for the format of the serial error messages.
MERLOUT
0
The MER LOUT output broadcasts bit-serial module error messages to all
BIUs contained within the same module (attached to the same processor).
1/0+
MMAL operates in the same manner as MMAH except that when MMAL is
asserted it indicates that the lower addressed portion of a multipl~ module
access is in progress on the memory bus.
Module Group
MMAL
The two BIUs that are cooperating in a multiple module access observe both
MMAH and MMAL. Both signals are deasserted .after each BIU has completed its portion of the access on the memory bus to which it is connected.
In read accesses, after both signals are deasserted, the BIU with the lower
addressed portion of the access presents data to the processor first. The
BIU with the higher addressed portion of the access tracks th~ other BIU by
counting the number of bytes returned to the processor (noting ICS, Interconnect Status, see below). When the BIU with the lower-addressed portion
of the access completes its transfer, the next BIU begins automatically. Multiple module read accesses which begin at an odd addressed byte boundary
cause the two cooperating BIUs to simultaneously return data to the processor. At the address boundary for which they share access responsibility,
the low BIU returns its last byte on ACD7 .. ACDO, and the high BIU returns
its first byte on ACD15 .. ACD8.
After MMAH and MMAL have been deasserted, one (or both) of the BIUs
may reassert the signals, each to indicate that its portion of the multiple
module access encountered an error. This indication will be returned to the
processor during error significance time for ICS.
MMAH
1/0+
When a~serted, MMAH indicates that one of the BIUs in a module is performing the high order address part of a multiple module access. A multiple
module access occurs when a processor request spans an address range
such that two memory buses, each connected via a different BIU must be
engaged. When it is deasserted, MMAH indicates that the high portion of the
access has been completed on the memory bus.
5-98
210963-002
iAPX 43204, 43205
Table 1. IAPX 43204 BIU Pin Description (Continued)
Symbol
Type
ACD Bus Group
ACD15
.. ACDO
Name and Function
The ACD Bus Group contains the set of signals with which a compatible
iAPX 432 processor connects to the BIU. See the iAPX 43201/43202 General Data Processor Data Sheet (Order Number 590125) and the iAPX 43203
Interface Processor Data Sheet (Order Number 590130) for information
about compatible iAPX 432 processors.
I/O
These 16 signals form the processor-to-BIU communication path that carries all memory and interconnect accesses.
PRO
I
PRO indicates the start of a processor request to the BIU.
ICSOUT
0
ICSOUT is intended to drive an external open-collector inverter to form ICS.
All BIUs in a processor module contribute to the wired-OR ICS signal.
ICS
I
ICS supplies interconnect status to both the BIU and its associated iAPX
432 processor. ICS carries information on errors, data synchronization, and
interprocessor communication to the processor. It is also monitored by
each BIU for coordinating multiple module accesses.
ClRPUOUT
0
ClRPUOUT is intended to drive an open collector inverter and form a wiredOR ClR signal to. the associated iAPX 432 processor. All BIUs in a processor module contribute to the wired-OR ClR signal. Using ClRPUOUT, a
BIU can synchronize the FRC master and checker processor components.
System Group
VCC2 .. VCCO
Three VCC pins supply 5-volt power to the BIU/MCU. All three pins must be
connected. The three VCC pins are not connected together inside the
component.
VSS2 .. VSSO
Three VSS pins provide ground to the BIU/MCU. All three pins must be
connected. The three VSS pins are not connected together inside the
component.
ClKA
I
ClKA is a square-wave clock for the SIU/MCU. CI:.KA must operate
continuously to preserve the operating state of the component.
ClKS
I
ClKBis a square-wave clock for the BIU/MCU. ClKB is the same frequency as ClKA but lags ClKA by 90 degrees. ClKS must operate continuously
to preserve the operating state of the component.
INIT
I
INIT is a signal that causes the BIU/MCU to initialize. In addition,lNIT is used
to enable external logic which provides configuration information to the
component.
.
Legend:
I
o
I/O
±..
Input signal
Output signal
Input/Output signal
FRC errors cause module error
FRC errors cause bus error
External passive pull up required (10K Ohms)
Asserted low
5-99
210963-002
intef··
iAPX:43204, 4320~ -
~~!.G=I!_~i
hoIl II II
111111111111111111111111
~ &LAD18
&LAD17
&LAD18
~ SLAD15
~ &LAD14
SLAD13
~ SLAD12
SLADll
SLADl0
~·F
~
~F
M80IIT
crrLO
MACD15
MACD14
MAC013
G
~
~
=~~~
~
MACD10
MACDII
MACDII
MACD7
MACD8
MACDS·
~
=
~
~
~
.-§
~111111111111.
SLAD9
SLAD8
SLAD7
SLADII
SLAD5
SLAD4
SLAD3
SLAD2
~11§~~!~~~;I;i;;
.8 ~
~~.
PIN NO. 1 MARK
i
NOTE: N.C. pads must not
be connected.
B:
I
Figure 11. 43205 PI" Configuration
§!,AD(19..0)
RAS
r
DEIN
REFRESH
VCC(2••0)
VSS(2••0)
CLKA
!mponent switches to an alternate bus (changes the bus
state code), BUSSEL is changed accordingly.
Memory Bus Arbitration Group
CONT
I
The CO NT input indicates if the external arbitration network has detected
that two or more simultaneous requests have been made for the use of the
memory bus. When contention is indicated, all contending components will
perform a binary arbitration sequence (based on each component's unique
6-bit module ID) to decide which component will be granted first use of the
memory bus.
I
The RQ input indicates if any agent is requesting the use of the memory bus.
..
RQ
There are three valid combinations for RQ and CO NT:
RQ
1
0
0
CONT Interpretation
1
No request
1
One BIU is making a request
0
Two or more BIUs are making a request
The MCU does not generate any memory bus requests. The MCU tracks the
action of RQ and CONT, and the CTL(2 .. 0) signals to determine when it is
allowable to use the memory bus to reply to a request.
Storage Array Group
SLAD19 ..
SLADO
I/O·
The 20 SLAD signals form the communication path between the MCU and
its associated storage array. The SLAD bus multiplexes addresses to the
storage array with data (32 bits) and ECC (7 bits) which are to be read from
or written to the array.
RAS
O·
When RAS is asserted, it ihdicates the start of a storage array cycle. RAS
may combine with external sequencing logic to control the operation of the
storage array.
I
ABCH.K is an input used to verify the external RAM control logic. WE and
CAS are used to generate the ABCHK signal. In addition, the functionality
of the external buffers associated with the storage array may be validated by
routing the oscillating BCHK signal through each of the buffers in a similar
manner as on the MACD bus side of the MCU. If an error is detected,
ABCHK can be corrupted and in this fashion report the error. An alternate
method of checking the storage array buffers is to use buffer packages with
no more than four buffers per package so that the special ECC protection in
the MCU may detect buffer failures.
O·
When WE is asserted, the MCU indicates that a write operation is to be performed in the storage array.
ABCHK
WE
5-102
210963-002
iAPX 43204, 43.205
Table 2.
Symbol
IAPX 43205 MCU Pin Description (Continued)
Type
Name and Function
Memory BUB Arbitration Group
DEIN
O·
When DEIN is asserted, the MCU indicates that the SLAD19 .. SlADO signals are ready to accept information from the storage array into'the MCU.
REFRESH
O·
When REFRESH is asserted the MCU indicates that the storage array cycle
is a refresh cycle. In systems with multiple bank dynamic RAM storage arrays, the REFRESH signal may be used to command the storage array
sequencing logic to perform an appropriate cycle (e.g., RAS-only refresh for
all banks). In a storage array with a single bank of dynamic RAMs the
REFRESH signal need not be used.
System Group
VCC2 .. VCCO
Three VCC pins supply 5-volt power to the BIU/MCU. All three pins must be
connected. The three VCC pins are not connected together inside the
component.
VSS2 .. VSSO
Three VSS pins provide ground to the BIU/MCU, All three pins must be
connected. The three VSS pins are not connected together inside the
component.
ClKA
I
ClKA is a square-wave clock for the BIU/MCU. ClKA must operate continuously to preserve the operating state of the component.
ClKB
I
elKB is a square-wave clock for the BIUlMCU. ClKB is the same frequency as ClKA but lags ClKA by 90 degrees. ClKB must operate continuously
to preserve the oPerating state of the component.
INIT
I
INIT is a signal tt)at dauses the BIU/MCU to initialize. In addition, INIT is used
to enable external logic which provides configuration information to the
component.
Legend:
I
o
I/O =
Input signal
Output signal
Input/Output signal
FRC errors cause module error
FRC errors cause bus error
Asserted low
5-103
210963-002
IAPX 43204, 43205
IAPX 43204 FUNCTIONAL DESCRIPTION
This section describes how the iAPX 43204 Bus
Interface Unit operates through a set of functional
diagrams that trace the operation of the pins clockby-clock. To understand the notation on the various
waveforms, refer to Figure 13. It illustrates thegeneral operation of the BIU as it accepts a memory
read request from a processor, forwards the request
to a Memory Control Unit (MCU), and returns the
reply data to the processor.
Once the processor has presented the request to
the BIU, the BIU presents ICS (Interconnect Status)
to the processor indicating that the processor is to
wait for the data to be returned by the BIU and the
memory system. In cycle 4, the BIU .issues the
NREOOUT signal (not shown) and observes NREO
and RO immediately. Though not shown, no contention with any other processor isobser.ved an the
CO NT pin. In cycle 5, the BIU asserts MBOUT to
control its external TTL buffers to drive the memory
bus and presents a two-cycle memory read request
message. The MACD bus carries the memory bus
specification code (high-order byte) and the physical memory address bits (A7 ... AO) in cycle 5, and
the remaining 16 address bits (A23 ... A8) in cycle
6. Referring to the Memory Bus appendix of the
Interconnect ARM, the memory bus specification
field of 03H is decoded as follows:
The cycle numbers (0, 1,2, ... ) at the top of each
diagram enumerate the clock cycles. When a common group' of signals is plotted, its value is displayed inside a data waveform. For example, the
BIU signals MACD15 ... MACDO are all high in
cycles 0 th rough '4. In cycle 5, the MACD bus carries
the value 0300H and in cycle 6 the value OOOOH.
Notice that in Figure 13, the BIU receives a processor request (PRO) in,cycle 0, The ACD bus carries
the information O,BOOH in cycle 1 (the specification
field on the high-byte and addresses A7 ... AO on
the low-order byte) and OOooH in cycle 2 (the
address bits A23 ... A8) for the access. Reorganizing the information, it is apparent that the BIU has
been provided a processor request with a specification field 6f OBH and a 24-bit physical address of
OOOOOOH. Referring to the GDP or IP data sheets, the •
specification field can be decoded as follows:
000010 11
III, I I
0000 0011
L!:::
Binary version of 03H
LLLL code for length of 4 bytes
Memory read operation
In cycles 10 and 11, the MCU that serviced the
request presents the data that it read from thestorage array, least significant bytes first. The returned
bytes in the example are: 2AH, 03H, 9AH, 8CH. In
Unclassified memo.ry access (other) cycles 15 and 16, the BIU presents the same data to
Length (4 Bytes)
the processor and indicates the availability of each
Not a read-modify-write operation
byte with ICS.
Read operation
Memory access
Binary version of OBH
'
ili~~~~~~~~ ~rw rw r10
CLKA
ACD
PRQ
IC$
000
Jt OBoo
11
12
13
'\
V-h
\.J
'---'
~
MBOUT
MACD
CHK
032A
0300
CTL
8C9A
1
2
2
Figure 13. 4-Byte Memory Read
5-104
210963-ClO2
inter
IAPX 43204, 43205
11
14
11
17
~ ~ ~ """"\.....
-
'-
.
en
CHI(
FlguN 13. 4-Byte Memory Reed (continued)
Figure 15 illustrates the steps that occur when a
processor requests a 4-byte write at physical memory address O. The hardware system for this examMEMORY
ple includes one processor, one BIU, one memory
ARRAY
""""...bus, one MCU, and one storage array (see Figure
~
15). In cycle 0, the processor emits the processor
request signal (PRQ=1) along with the specification
field and the low-order address byte on the ACD
signals. The specification field (high-byte ofthe fi rst
PRO
double-byte) in this example is 4BH and the loworder address byte (low-byte of the first doublebyte) is OOH. In cycle 1, the processor emits the
high- and mid-order address bytes on the ACD
signals. In this example, the high- and mid-order
MCU
address ;bytes are OOH. The BIU deasserts ICSOUT
r-~
(not shown) which, after an external logical inversion, provides the ICS Signal (Interconnect Status)
to the processor. The deasserted ICS is used to
_en.
_en.CHK
"""
stretch the processor access cycle (generate wait
states). The processor presents the first doubleL.L
L.L BUFFERS
. 'byte of data to be written,in cycle 4, but because ICS
is deasserted, the processor must stretch the data
into cycle 5 before the BIU will accept it. In cycle 5,
"'-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-' '- the processor provides the second double byte of
data to be wirtten (OOOOH). Notice that the BIU
deasserts ICS to hold the processor until the entire
FIgUN 14. Herdwere Conftguration for Memory
request is actually satisfied by the MCU and
ReedIWrHe ExMIpIee
memory array.
....
...
--
-
.
--
5-105
inter
iAPX 43204, 43205
In cycle 4, the BIU presents the request to the
memory bus arbitration logic. Since only one processor is in the system, the NREQ (output) and RQ
input signals are asserted but no contention (CONT
signal is not shown) is detected. Thus, the write
access proceeds immediately to the memory bus
(MACD,'CTL, and CHK signals). In cycles 5 through
8, MBOUT is asserted by the BIU to direct external
buffers to pass the BIU request to the memory bus.
The first two double-bytes of the request contain a
specification byte and three address bytes. The
information in these two double-bytes is a modified
version of that received from the processor ACD
bus. The high-order byte of the memory address is
0
CLKA
. 1
_
ICS
3
4
•
5
7
8
9
10
11
12
13
~ h-- "'-... "'-... "'-... ~ ~ ~ ~ ~ ~ "'-... ~ ~
4BOO'\.
ACD
PRQ
2
contained in the low-order byte of the first doublebyte. The mid- and low-order bytes of the memory
address are contained, respectively, in the highorder and low-order bytes of the second double
byte. MBOUT remains asserted While the two
double-bytes 01 the write request are provided by ,
the BIU. The MCU performs the access and returns
a write reply (CTL=6) in cycle 10. The BIU asserts
ICS for the processor in cycle 14, allowing the processor to escape from the stretched write cycle that
it had entered earlier. In this case, no error occurred
during the access. However, had there been an
error, the level of ICS in cycle 15 would indicate the
error to the processor.
AAAA
I
~~
~
\..
..r
"
~
~
'--MBOUT
MACD
2300
• AAAA
CTL:
CHK
1
~
1
--.!......
'--.!......
Figure 15. 4-Byte Memory Write
5-106
210963-002
IAPX 43204, 43205
-
CLKA
,.
'1
;"""\.... "-
PRQ
ICS
-.r ~
MIOUT
en.
CHK
Figure 15. 4-Byte Memory Write (continued)
MULTIPLE MODULE ACCESS READ2-WAY INTr;RLEAVING
The Figures 16 and 17 illustrate the interconnect
system's ability to support interleaving of memory
requests among two memory busses. The hardware
configuration pictured in Figure 16 contains one
processor, two BIUs, two memory busses, two
MCUs, and two storage arrays. The two BIUs are
initialized to perform 2-way interleaving of memory
requests based on bit 6 of the physical address that
the processor provides. Specifically, that portion of
a request with bit 6 of the physical address equal to
zero is serviced by memory bus O. That portion of a
request with bit 6 of the physical address equal to
one is serviced by pus 1.
I n the example that follows, an 8-byte read at physical memory address 00003DH is requested. As Figure 16 indicates, the two BIUs each recogn,ize the
,portion of the request that is supported by the bus to
which they are connected. The BIU on bus 0 (BIUO)
services the first 3 bytes of the access (03DH ...
03FH) and the BIU on bus 1 (BIU1) services the
remaining 5 bytes (040H ... 044H). In the interleaving process, the BIUs reorder the physical address
bits, based on the selected interleaving, to present
requests to the MCU in a linear address space. A
BIU transforms its portiQn of the request by replacing address bit 23 of the physical address with
5-107
address bit 6, and shifting original address bits
23 ... 7 to the right by one position. Jhe reordered
result (6,23 ... 7,5 ... 0) is forwarded to the respective memory bus. The BIU1 translation of physical
address 000040H to memory bus 2 address 8OO000H
illustrates the address interleaving operation.
~
........
...
"l
I-~------~~~--+-------r------'I:
'" ..,
--------~~~~~-------+------~
Figure 16.
Hardware Configuration for MMA Read
210963-002
inter
IAPX 43204, 43205
ReferrinQ to Figure 17 for this operation, notice that
the processor emits its request just as in earlier
examples. However, in this case, two BIUs recognize that they each must participate in the request.
Thus, BIUO asserts MMAL and BIU1 asserts MMAH
indicating that a multiple module accel!S is required
to complete this access. The two BIUsthen present
their requests to their respectiv.e memory busses
after performing the address interleaving as described above and each access continues independ-
"
\'
ently. Once both accesses have completed, the
BI Us cooperate to return the data to the processor.
BIUO provides the first 3 bytes and BIU1 returns the
final 5 bytes. Notice, in cycle 23, that BIUO provides
the low byte (25H) and BIU1 provides the high-byte
(F5H). Thereafter, BIU1 provides its remaining bytes
with the byte significance that is required by the
processor. By this cooperation, the processor is
unaware that two BIUs were involved in the operation .
•
0
- -
1
2
3
~ ~ ~~
....r
ICS
4
5
•
7
•
8
10
11
12
13
'"""'--' '"""'--' ~ ~ """"'-.. ~ ~ ~ ~ ~
'\.
r-"\.
u
~
1
-
1
,
2
Figure 17. Multiple Module Access Read-2-Way Interleaving
5-108
210963-002
IAPX 43204, 43205
14
CUCA
15
11
17
11
1.
21
20
22
h-- ~ ~ ~ h--h-- ~ ~ h-_1
PRQ
r
ICS
;--"'\.
V
zi
1&
14
~
-
1&
-
h-- r-'-' t-'-~
~
-"'\. ~
'-
MACD.IIUBO
en.BUBO
MACD.BUl1
CTLBUl1
, Figure 17. Multiple Module Access Read-2-Way Interleavln9(cont)
MULTIPLE MODULE ACCESS WRITE2-WAY INTERLEAVING
The following multiple module access is also performed on the same hardware configuration shown
in Figure 16 with modified interleaving characteristics. jn this case, the system is initialized with 2-way
interleaving on address'bit 7 (see Figure 19). Therefore, the 8-byte multiple module access write to
physical address 0OOO7DH is transformed into two
memory bus requests: bytes 000040H ... 000044H
on bus 0 and bytes 80003DH ... 80003FH on bus 1.
Again, the MMAH and MMAL signals coordinate the
multiple module access and each bus' operates
independently (see Figu~e 20).
. ...
--r-----~~~--~--~---+-----:=
"" ,.,
--------~==~~
________
4-_____
==
~Igure 18. Hardware Configuration for MMA WrIte
,
5-109
210963-002
inter
IAPX 43204, 43205
0
1
2
4
3
5
8
7
CLK4
9
8
"-' ~ ~ ~ ~ ~ ~ '""""\......
11
10
12
13
"--' ~ ~ "-' ~ r-'---
ACD
V- h
PRO
'- f-'
~
ICS
'\
MACD.BUSO
CTL.BUSO
MACD.BUS1
,..-,-
CT\,.BUS1
Figure 19. Multiple Module Access Wrlte-2-Way Interleaving
14
CLKA
15
18
17
18
19
20
21
22
23
24
~ '""""\...... "'""\...:. ~ ~ ~ '""""\...... """"LJ ~ '""""\...... "-'
ACD
PRO
,- ~
ICS
iiiWi
MACD.IUSO
CT\,.BUSO
'r-1
8
MACD.IUS1
I-L...
Figure 19. Multiple Module Aceess Wrlte-2-Way Interleaving (Continued)
5-110
210963.002
IAPX 43204, 43205
GLOBALINTERPROCESSOR
COMMUNICATION (IPC) BUS BLURB
Figure 20 illustrates the signaling of a global interprocessor communication message (IPC). The IPC
is called a bus blurb since it is broadcast to all BIUs
on the memory bus but does not require that any
replies be generated. The delivery of the message is
guaranteed by. a memory-based communication
object; the bus blurb only serves as the low-level
notification. A programmer invokes a globallPC by
the instruction BROADCAST TO PROCESSORS.
The processor performs the instruction by writing a
0
CLKA
~
ACD
0008 C7
PRO
~
ICS
MBOUT
---'
I'
2
r-u h--
'"
3
~
4
value (OOH) tothe IPC interconnect register (address
02H) in the associated BIU. In cycle 0, the processor
emits a specification field (C7H). In cycles 0 and 1,
the processor provides the interconnect address
(000002H). In cycle 2, the processor provides the
destination processor ID (OOOOH represents all processors, the global I D). Notice thatthe BI U stretches
the processor (ICS=O) until the delivery ofthe global
IPC is completed (cycle 10).
8
5
8
9
10
11
h-- ~ ~ ~ "\......, ~ "\......, ~
r
--
h-
Ir----.
MACD
~
CTL
I-i--
CHK
7
.
~
Figure 20. Global Interprocessor Communication (IPC) Bus Blurb
5-111
210963-002
inter.
. IAPX 43204, 43205
MACD CORRUPTION AND PARITY ERROR
Figure 22 illustrates the process of detecting and
reporting- a memory bus parity error to the serial
error reporting network. This reporting method is
common to' all errors that are detected by the interconnect system. The error reporting paths for this
example are illustrated in Figure 21.
iiEiii.MTH1
--~----+----4~~------+---~~---+~--------~~------_r+----BERL.MT~
-----4----_r----+----------+----4-----~--------~----------~-BU"
-------------4......-------------------+~------------------_r---- iEiii..MTH1
----------------~--------------------~------------------~~B~1
Figure 21. Hardware Configuration for Error RepOrting
5-112
210963-{)02
J
IAPX 43204, 43205
PHASE 1-DETECTING AND REPORTING
THE PARITY ERROR ON BERL
In cycle 3, bit 1 ofthe memory bus (MACD signals) is
corrupted with a zero causing the MACD data to
change from FFFFH to FFFDH. This causes a parity
error on the memory bus that must be reported to
the interconnect system. The reporting process
begins in cycles 5 and 6 when the BERL1 signal
(driven by BERLOUT) carries the start code of the
serial error report. In cycles 7 through 21, ¢Ie message is propagated along the bus error report pa~h
associated with bus O. The message sent is (complement of the levels on the BERL1 signals):
2
1
7
Cycle numbers
Binary serial error message on BERL tPATHO
010000000000101
s
eeee
3210
bbb
210
mmmmmm
543210
o
1000
000
000010
p
Reformatted serial error report message
11,---1I_L
Parity bit
Module number
Bus number
Error code
Sequence
The error report codes are described in the iAPX 432
Interconnect Architecture Reference Manual, order
no. 172487 (see BIU Register OO-Error Report
Log).
.
PHASE 2-BROADCASTING THE ERROR
ONMERL
Once the fuJI serial message has-propagated along
the memory bus, each BIU that received it repeats.
2
5
the message along the module error report line path
(MERL 1 and MERL2). This time, the error report
message is:
3
Cycl~
9
Reformatted serial error report message
110000000000100
s
eeee
3210
bbb
210
mmmmmm
543210
p
0
1000
000
000010
o
I
1
I
numbers
L
Reformatted serial error report message
Parity bit
Module humber
Bus number
Error code
Sequence
5-113
210963-002
IAPX 43204, 43205
PHASE 3-REBROADCASTING THE ERROR
ON ALL BERL PATHS
In cycle 42, the message is again rebroadcast, this
time along all the bus error report line paths. The
message sent is:
4
5
4
8
Cycle numbers
Binary serial error message on BERL 1. PATH 0
110000000000100
s
eeee
3210
bbb
210
mmmmmm
543210
p
1000
000
000010
o
II
_L
L----
Reformatted sedal error report message
Parity bit
Module number
Bus number
Error code
Sequence
Once this three-step reporting process is completed, all modules have been informed of the error.
ClKA
ACD
MACD
~
CTl
CHK
\
MERL.MODULE1
MERL.MODULE2
BERL1.BUSO
~
i-I
\ - !---J
iffiii:1.BUS1
F.igure 22. MACD Corruption Causing Parity Error·
5-114
210963-002
inter
IAPX 43204, 43205
CLKA
ACD
0008
MACD
CTL
CHK
V h.
'-- f.....r h
iiEiii:..MODULE1
'--
iiEiiL.MODULE2
'-- ~
BeRL1.BUSO
I\-f-J
BERLt.BUSt
Figure 22.
MACD Corruption Causing Parity Error (continued)
CLKA
ACD
MACD
CTL
CHK
iiE'ALMODULE1
'-- --J
iiE'ALMODULE2
'-- f-1
iiERU.BUSO
iiERU.BUS1
Figure 22.
MACD Corruption Causing Parity Error (continued)
5-115
210963·002
inter
IAPX 43204, 43205
CUCA
ACD
en.
CHK
.-RLMOOULE1
ILV
,
iiiiLi.BUS1
"'-
I'--Lr"'Figure 22. MACD Conuptlon Causing Parity Error (continued)
0008
en.
CHK
MERLMOOULE1
iiEAL.MODULE2
iiEiiUBUSO
""""'- --'
iiiiit1.BUS1
""""'- --'
Figure 22. MACD Conuption Causing Parity Error (continued)
5-116
210963-002
inter
iAPX 43204, 43205
TEST DETECTION COMMAND
The Test Detection command is a special command
that requests a BIU to test the detection hardware
contained inside the component. It checks all the
FRC circuitry, memory bus parity generator/checkers, and buffer checking logic. The hardware configuration for this example is the same as that for the
pr!9vi9uS example (see Figure 21). When the command has been performed an error report message
CLKA
is generated, just as in the previous example. When
the test is successful, the message indicates "no
error." When any ofthe detection circuitry has failed,
the message indicates "module error." In this example, the detection circuitry is operating properly and
phase 1 of the serial error reporting sequence contains the "no error" ,message starting in cycle 5 (see
Figure 23).
~
ACD
MACD
41 0
CTL
&CO2
1
CHK
2
C69
2
r--L-
MERL,MODULE1
MEiiL.MODULE2
BERL1.BUSO
BeiiL1.BUS1
Figure 23. Test Detection Command
5-117
;110963-002
iAPX43204, 43205
CLKA
ACD
•
06C
MACD
CTL
CHK
iERi.MODULE1
MERL.MOOULE2
BERL1.BUSD
I'-~
'-- --.r
t"L --f
Ei'ERiJ.BUSl
Figure 23.
Test Detection Command (continued)
CLKA
ACD
MACD
cn
CHK
MERl.MODULE1
'-- -F" h
MERL.MODULE2
'-- -F" k
BERL1.BUSO
r- ' - f-I
r- """'"'\...- 1-1
'-- f-I
BERTI.BUS1
Figure 23.
Test Detection Command (continued)
5-118
210963-002
inter
IAPX 43204, 43205
eLKA
ACD
MACD
•
eTL
eHK
MERL.MODULE1
MEALMODULE2
BERL1.8USO
~
~~
~L.r"~
iiEFiU,BUS1
Agure 23. Test Detection ~ommand (continued)
eLKA
ACD
MACD
eTL
eHK
MERLMODULE1
MERl.MOOULE2
BERL1.BUSO
BERL1.BUS1
Agure 23. Test Detection Command (continued)
5-119
210963-002
1APX 43204, '43205
MACD BUS ARBITRATION
Figure 24 illustrates two processors as they simultaneously issue memory requests. Since the ra'quests are both'serviced by the same memory bus
and MCU, arbitration is performed to select the first
request that should be presented. The hardware
configuration consists of two processors (processormodules 2 and 6), two BIUs, one mein9rY bus,
one MCU, and one storage array (see Figure 25).
'In cycle 0, both processors issue a request indicateEi
by the respective process9r request signals,
PRQ.PROC2 and PRQ.PROC6. In cycle 4, the asso..
ciated BIUs present their requests to the memory
bus (NREQ=O, RQ=O) and each notes that another
BIU is also contending (CONT=O) for the use of the
PROC
memory bus. The BIUs resolve the contention by
examining the individual bits of their respective logicallDs, beginning with the most significant bit. Iri
this case, the default logical 10 is a bit-reversed
version of the module 10. In ,cycle 4, each BIU notes
contention. In cycle 5, each BIU still notes contention. In cycle 6, the BIU serving module 2 wins the
arbitration and issues its request to the memory bus.
Overlapped with the first request, the BIU in module
6 reissues its request for the memory bus (RQ=O in
cycle 9) and detects no contention. However, each
BIU monitors the memory bus and the BIU in
. module 6 waits for the current bus activity to complete before its request can be placed on the bus.
STORAGE
ARRAY.
PROC
BIU
BIY
1
1
PROCESSOR
MCU
MEMORY
i
BUS
PROCESSOR
MODULES
MODULE 2
Figure 25.
Hardware Configuration for Memory Bus Arbitration
5-120
210963-002
inter
IAPX 43204, 43205
0
1
2
4
3
r\.... r\.... ~ ~
6
5
..
7
9
10
ICS.PAOC2
13
f-I!2tIi-
r--r-
1
f.-r h
~
r-- ~
r-r-
CHI(
PAO.PR0C8
12
~ f\--. r- I'r- ~ ~ r- h- r- t-&ir
en
PRO.PR0C2
11
V- h
'-
I-'
,
IC5.PROCI
MBOUT
"---
Jr----, _ _ Jr----, ____
lAO
Figure 24. MACD Bus Arbitration
I.
CLKA
MACD
en
15
16
17
18
19
20
2t
22
2'
24
I'- I'- ~ ~ ~ n..... ~ ~ ~ I'- I'~
~
•
CHK
PRQ,PROC2
PRO.PROC6
ICS.PAOC2
J
~~
ICS.PROC6
'-
MBOUT
Figure 24. MAcD Bus Arbitration (continued)
5-121
210963-{102
IAPX 43204,43205
Table 3.
IAPX 43204 Clock Edge Table
Input Sample
Signal
,
Output Drive
Pln(s)
Clock
Edge
Clock
44
Rising
Rising
Rising
Rising
Rising
Falling
Falling
Falling
Rising
nfl!
Inputs
MERL
BERL1
BERL2
ICS
INIT
RO
CONT
NREO
PRO
38
39
48
37
9
10
5
49
CLKA
CLKA
CLKA
CLKA
CLKA
CLKA
CLKA
CLKA
CLKS
Outputs
MERLOUT
SERLOUT
ICSOUT
CLRPUOUT
46
40
47
45
nfa
nfa
nfa
nfa
. InputfOutput
MMAH
MMAL
ACD15 ... 0
MACD15 ... 0
CTL2 ... 0
CHK1 ... 0
MSOUT
NREOOUT
ROOUT
BCHK
50
51
1,54-68
13-28
29-31
11, 12
32
4
6
7
CLKA
CLKA
CLKS
CLKA
CLKA
CLKA
CLKA
CLKA
CLKA
CLKA
Edge
nfa
nfa
nfa
nfa
nfa
nfa
nfa
nfa
I
"
Rising
Rising
Rising
Rising
Rising
Rising
Rising
Falling
Falling
Rising
5-122
CLKA
CLKA
CLKS
CLKS
Rising
Rising
Rising
Rising
CLKA
CLKA
CLKS
CLKS
CLKB
CLKS
CLKA
CLKA
CLKA
CLKS
Rising
Rising
Falling
Rising
Rising
Rising
Rising
Falling
Falling
Rising
210963-002
IAPX 43204, 43205
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Range ....... O°C to 70°C
Storage Temperature •....... -65°Cto +150°C
Voltage on Any Pin with
Respect to Ground ........... -1.0V to + 7V
Power Dissipation ................... 2.2Watt
"NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent dam~
age to the. device. This is a s.tress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification /s not Implied.
Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
iAPX 43204 DC Characteristics
Symbol
Description
Min
. Max
Units
Vilc
Clock input low voltage
-0.5
+0.8
V.
Vihc
Clock input high voltage
3.2
Vcc+0.5
V.
Vii
Input low voltage
-0.5
+0.8
V.
: Vih
Input high voltage
2.0
VCC+0.5
V.
Vol
Output lOw voltage
-I
0.45
V.
Voh
Output high voltage
2.4
VCC
V.
-
±10
/LA.
±10
/LA.
iii
Input leakage current (measured at Vin=VCC)
110
Output leakage current (measured at 0.45 V. =:; Vout
=:; VCC)
loh
Output high current (measured at 2.6 V.)
101
Output low current (measured at 0.45 V.)
Icc
Power supply current (sum of VCCO. VCC1. VCC2)
rnA.
4
-
-
400
mAo
-2
mAo
All DC parameters are guaranteed over the following conditions:
VSS2 ..VSSO = 0 Volts
VCC2 .. VCCO = 5.0 Volts ± 5%
The absolute value of the differential DC voltage between any of the vec pins (VCC2 ..VCCO) must be less than 0.1
Volts. This is normally guaranteed by connecting the three VCC pins to the same printed circuit power trace .
•
5-123
210963-002
inter
.iAPX 43204. 43205
iAPX.43204 AC Characteristics
AmbienUemperatrue range of O~C to 70°C
5 MHz
Symbol.
Description
Min
tr·tf
Clock rise and fall times
-
t1.t2' t3' t4
Clock pul~e width
37
tcy
Clock cycle time
200
ted
Clock to signal delay time
. Clock to signal hold time
tdh
Clock to signal output enable time
ten
Min
8 MHz
Min
Max
10
nSec
250
nsec
-
11
0
250
25
250
24
1000
143
1000
125
-
-
70,
-
60
20
-
17
-
15
17
Unit
Max
13
20
.,
7 MHz
Max
1000 • nsec
55
nsec
nsec
15
-
nsec
Clock to signal data float time
-
50
-
44
-
40 . nsec
tdc
Signal to cl,ock setup time
30
-
26
-
24
-
tie
Initialization period
20
100
20
100
20
100
. tdf
~II
nsec
tcy~
AC parameters are guaranteed over the following conditions;
Ambient temperature range of 0 degrees Centigrade to 70 degrees Centigrade
VSS2 ... VSSO '" 0 Volts
VCC2 ... VCCO = 5.0 Volts ± 10%
100 picofarad external load capacitor on all output pins
iAPX 43204 Capacitance Data
Conditions:
Ta = 25°C
VCC = 5.0 Volts. GND = 0.0 Volts
f(test) ~ ,1.0 MHz
Inputs held at 0.0 Volts
All outputs in high Impedance state
All input/output pins are classifieda~ outputs
Description
Symbol
Cin
Input Capacitance
Cout
Output Capacitance
.
5-124
Max
Units
6
pF
12
pF
210963-002
iAPX 43204, 43205
WAVEFORMS
iAPX 43204 Clock Input Specification
~-----~ ------~
ClKA
ClKB
iAPX 43204 Initialization Timing
ClKA
I
~'
5-125
210963-002
iAPX, 43204, 43205
WAVEFORMS (Continued)
,
iAPX 43204 Input Timing Specification
CLKA
\
.
1\
J
MERL, aERL 1, iiEiiil
R 2,
iiiiE, MMAH, MACD(15-0)
CTL(2-0), CHK(l-10)
MBOUT,BCHK'
ICS
INVALID
DATA
Ide
RQ, CQNf, NREQ ,
NREOOUT, RQOUT
INVALID
Idh
INVALID
DATA
J
Ide
INVAUD
Idh
/
CLKB
r
J
PRQ
ACD(lS-G)
INVALID
\I
DATA
I
INVAUD
J
lcie
5-126
Idh
210963-002
iAPX 43204, 43205
WAVEFORNIS (Continued)
iAPX 43204 Output Timing Specification
I
~
\-
ClKA
~
1\
\
I
NREOOUT. 3-STATE OR PREVIOUS
RQOUT
DATA
DATA'
I
--
I--led
Idf
'MERlOUT
BERlOUT
MMAH
MMAl
MBOUT
\
11\
DATA
f--;cd
!+--+
Idf
I
CLKB
I
ACD(15-0)
3-STATEOR
PREVIOUS DATA
I
ACD
DATA
--
CHK(1-0). CTl(2-0).
MACD(15-0). BCHK
ICSOUT, ClRPUOUT
/
3-STATEOR
PREVIOUS DATA
f-tcd
5-127
-I df
l ed
I
MACD
DATA
1\
1----0tdf
210963-002
inter
( iAPX 43204, 43205
IAPX 43205 FUNCTIONAL DESCRIPTION
This section describes how the iAPX 43205 Memory
Control Unit (MCU) operates. It contains a set of
diagrams that present the clock-by-clock activity of
'the pins on an MCU component. To understand the
notation on the waveforms, refer to Figure 26. It
illustrates a 32-bit memory read operation of physical memory array address OOOOOH.
Cycle 5 contains the least significant information,
and cycle 6 contains the most signifiqmt information. The least significant bit of cycle 5, the spare bit,
is not used in this case. Thus, the actual data and
ECC information transferred on the SLAD Signals is
formed by concatenating the low- and high-order
SLAD data groups and deleting the low-order spare
bit. The 7 ECC bits occupy the high-order 7 bits of
the result, and the 32 data bits occupy the low-order
portion.
The cycle numbers (0,1,2, ... ) at the top of each
waveform enumerate the clock cycles. When a
common group of Signals is plotted, its value is
displayed inside a data waveform. For example, the
MACD signals (MACD15 ... MACDO) are all high in
cycle 0, carry the hexadecimal value 0300H in cycle
1, and are all low in cycle 3. The MACD signals
(MACD15 ... MAC DO) carry the values 0300H in
cycle 1 and OOOOH in cycle 2. The first double byte of
the access contains the specification field (03Hthe high byte of the first double byte) and the loworder address byte (OOH-the low byte of the first
double byte) of the memory address. The second
double byte of the access contains the high- (OOH)
and mid-order (OOH) address bytes. This example
illustrates a double byte read performed at physical
memory address OOOOOH. Also, notice that the
SLAD pins (SLAD19 ... SLADO) are represented
with a 5-digit hexadecimal value.
Onglnal SLAD Information
DC66442200
1101 1100 0110 0110 0100 0100 0010 0010 0000 0000
I
o
ECC
,
Cycle 6
C
6
6
4
1101 1100 0110 0110 0100
D
Spare bIt
Data
Spare 8'lt Removed
6,E
3
3
221100
110 1110 0011 0011 0010 001(1 0001 0001 0000 0000
o
ECC
31
Data
The 32-bit value 33221100H is returned to the MACD
bus with the low-order 16 bits in cycle 7 and the
high-order 16 bits in cycle 8. The 7-bit ECC value is
checked by the MCU and is not transferred to the
MACD signals.
Consider the SLAD group in the examRle. In the last
half of cycle 3 and during cycle 4, the SLAD group
carries the value OOOOOH, the storage array address
for the access. In cycle 5 the array returns read data
of 42200H, and in cycle 6 the array responds with
DC664H. In this example, the storage array is phYSically 20-bits wide, and the least significant physical
bit is a spare bit. Thus, to interpret the actual data
present on the SLAD wires, a logical shift is necessary to align the data as it will be presented on the
MACD Signals.
Original SLAD Information
4
2
2
0
0
Cycle 5
0100 0010 0010 0000 0000
o
31
Hexadecimal
Binary
Spare Bit
HexadeCimal
Binary
These waveforms are accurate cycle-to-cycle representations of MCU function. They are.not meant to
serve as diagrams of exact component timing. For
example, the diagrams depict MACD data being
issued from the MCU at the functional clock boundaries for the rising edge of CLKA. The MCU actually sources MACD information on the rising edge
of CLKB. Always refer to the precise electrical specifications, AC specifications, and timing diagrams
when detailed timing information is required. The
funcfional diagrams are intended to succinctly summarize the functions of the MCU.
5-128
210963-002
inter
IAPX 43204, 43205
,
,D~ICRAM
SlOIIAGE ARRAY 112
Figure 27. MCU and External Hardware Configuration
.HARDWARE CONFIGURATION FOR
MEMORY READ AND WRITE OPERATIONS
Figure 27 is the basis for demonstrating MCU
memory read and write operations. In each memory
read and memory write example, the appropriate
command is presented to the MCU from the MACO
(memory) bus and the MCU performs the operation
to completion. Each memory operation as;sumes
,the following hardware configuration for the logic
.external to the MCU. Notice. that external logic
accepts the RAS, WE, and OEIN signals and produces the precise timing signals which are required by
.the associated dynamic RAM storage array. In the
diagrams which follow, only signals which are present on the MCU Signal pins are displayed.
MEMORY READ OPERATIONS
Figure 26 (Normal Aligned Read) illustrates a mempry read operation that returns two double bytes (4
bytes) from the memory subsystem, typical for iAPX
~2 GOP instru~tion fetch cycles.
Figure 28 (Normal 2-byte Read) illustrates a memory read operation that returns a single double byte
operand.
Figure 29 (Normal Nonaligned Read) illustrates a
4-byte memory read operation that is not aligned to
a 4-byte boundary, the natural boundary for instruction fetches and 32-bit operands. In this case, the
MCU must perform two/separate storage array
accesses to acquire the 4 bytes.
Figure 30 (4-byte Read with Extended Access) illustrates a programmable option on the MCU that
accommodates storage arrays that require longer
memory access cycles. With the extended access
option, the MCUextends RAS one cycle and delays
OEIN one cycle to allow the external array sequencing logic to extend the storage array cycle .
Figure 31 '(Staged Read with Correctable Error)
demonstrates how an MCU can stage (hold) memory data until all ECC detection and correction is
performed. Without selecting the staging option, a
MCU would normally present the memory data it
acquired to the MACO bus as in other memory read
cycles. However, should an error be detected, the
MCU would signal (BERLOUT) to inform a BIU that
data it had been given was invalid, and the BIU
would retry the access.
210963-002
IAPX 43204, 43205
0
Cuu.
1
~~
2
3
~
5
4
f\..-. n-
~
8
1."
7
,
9
8
n- n- ~ ~
,............
MACO
r---,
CHK
r-----
-.!.-
~
-J
Figure 28. Normal. 2-byte Read
'.
h- f\..-. n- n- n0
CLKA
1
2
3
5
•
7
9
~ t"""-- ~ ~ ~
\otACD
CTL
8
1
r---,
1
CHK
-.!.-
SLAD
'\.- - J
,
AllCHK
Figure 26. Normal Aligned .Read
210963-002
inter
IAPX 43204, 43205
•
•
~ ~ ~ ~ ~ ~ h.- h.- I'\....... r-L. I'\....... ~ ~ r"'0
CUCA
2
1
3
4
5
9
7
10
11
12
13
MACD
~
CHK
I--'~
'-~
'-~
AllCHK
Figure 29. Normal Nonaligned Read
0
CLKA
1
2
3
4
5
•
7
•
9
10
~ h- h.- ~ ~ t-""-- h.- ~ ~ t-""--t-""--
MACD
CTL
CHK
SLAD
~
1
2
I--l--
1
ME C
0000I
' - -J
ABCHK
Figure 30. 4-8yte Read with Extended Access
5-131
210963-002
IAPX 43204, 43205
•
~ ~ ~ V V --r- V V V V ....r- ~ V W0
CL~
1
2
3
4
5
8
7
8
10
11
,12
13
MACD
en
'"""'"
CHK
1
~
suo
,
~
to--
ABCHK
Figure 31.
Staged Read with Correctable Error
MEMORY WRITE OPERATIONS
Figure 32 (Normal 2-byte Write) illustrates a memory write operation that stores a single double byte
operand.
Figure 33 (Normal Aligned Write) illustrates a memory write operation that stores a 4-bYte operand
aligned to a 4-byte boundary.
Figure 34 (Normal Nonaligned Write) illustrates a
4-byte memory write operation that is not aligned to
a 4-byte boundary. In this case, the MCU must perform two separate storage array accesses to store
the 4 bytes.
Figure 35 (4-byte Write with Extended Access) illustrates a programmable option on the MCU that
accommodates storage arrays which require longer
memory access cycles. With the extended access
option, the MCU extends RAS one clock cycle and
delays DEIN one clOck cycle to allow the external
array sequencing logic ,to extend the storage array
cycle.
5-132
210963-002
inter
IAPX 43204, 43205
•
CLIIA
1
V V
2
IUCD
•
•
~
....r~ ~ f.....r" V
V"' .....r-'V
3
~
5
8
7
8
11
I'
12
13
~
V-
I
CT\.
'--' f-'
CHK
'-' f--'
SLAD
~E
-
~
ABCHK
'---
Figure 32.
•
CLIIA
M~D
1
V V-
2
~
3
4
Normal 2-byte Write
5
f-..I' V"' ~ V
CT\.
•
7
....r-
•
•
I'
11
12
13
.......r-' ~ .....r-' ......r- .......r-'V
.
' - '-J
CHK
'\..... I.....J
SLAD
~
r-
ABCHK
Figure 33.
'--
Normal Aligned Write. .
5-133
210963-002
IAPX 43204,'43205
0
2
1
3
h-h--h-
CLKA
•
h- ~ ~ h-h- r""\..... h- r""\..... h- ~
6
5
""'"\.....J
8
7
8
10
11
12
13
MACD
CTL
1
CHK
SLAD
i
'-~
' - -F
'--L r -
ABCHK .
Figure 34. Normal Nonaligned Write
,.
CLKA
15
16
18
17
,.
22
21
20
23
24
h..... ""'"\.....J """"\....... ""'"\.....J """"\....... r""\..... ""'"\.....J h- r""\..... ""'"\.....J r""\.....
MACD
CTL
.....J......
CHK
SLAD
....:.J....,;,;
00001
C
E
E
'-- ....J
\:.- i--J
ABCH~
'
'--LJ
Figure 34.
Normal Nonaligned Write (continued)
5-134
210963'()02
inter
IAPX 43204, 43205
0
2
1
3
•
•
5
7
•
•
10
11
,12
13
~ '""'"\.... ~ ~ ~ """'\...... ~ ~ r-\.... """'\...... ~ '""'"\.... """'\...... ~
en
1
I
CHI!
&LAD
~
....J
~.
' - r-'
' - -F"
Figure 35. 4-byte WrIte wHh Extended Access
M
CLKA
15
18
~ '""'"\.... ~
MACD
en
CHI(
--L....
~
SLAD
Figure 35.
4-b,.. WrIte with Extended Access (continued)
5-135
210963-002
inter
"IAPX 43204, 43205
.
,
described earlier. However, the MCU performs the
refreshing operations independently of any commands from the MACD bus~
MEMORY REFRESHING OPERATIONS
Figures 36 and 37 illustrate an MCU performing,two
types of storage array refreshing operations, The
MCU performs a Normal Refresh Cycle to satisfy
standard, dYl'larnic RAM refresh requirements.
External logic must use the REFRESH Signal, to
generate the appropriate storage control signals
(e,g., RAS-only refresh). The MCU performs· a
Scrub Refresh Cycle to cleanse the memory array of
latent,ECC errors by periodically reading the storage array and writing back a corrected version of
data for any correctable errors it detects. Each of
these diagrams utilize the same hardware configuration as the memory read and write operations
INTERCONNECT REGISTER OPERATIONS
Figures 38 and 39 illustrate the' reading and writing
of interconnect registers that are located on the
MCU. Refer to the iAPX 432 Interconnect Architecture Reference Manual for a detailed description of
specific interconnect registers, These diagrams
illustrate general interconnect register operations.
Later, specific commands are demonstrated that are
invoked by interconnect register operations.
• 1 2 3 • 5
• •
......r- V ......r- ~ .....r- ......r- V .....r- .....r- .....r8
CHI(
-
-
7
.....
'"
ABCHK
....
REFRESH
""--
Figure 38. Norm.I RefreSh Cyete
5-136
210963;002
inter
IAPX 43204, 43205
0
CLIIA
1
Z
•
• •
V V ~ V W- ~ ~ ~ ~
3
.....j"! ~ ~
•
I
7
10
11
IUCD
CTL
CHIC
-
r---.
-
"--
l--
-
~
REFRESH
'---
FIgure 37. Scrub R.....h Cycle
0
."'""'-..
1
2
h- h--
3
•
~~
5
•
7
•
•
10
~ h.... ~ ~ ~ h--
.,ED
CTL
CHK
~
............ " - -
•
3
•
II.AD
,
FIgure 38. Interconnect Regls~r Read
5-137
210963-002
. I~PX 43~04; 43205
C-l~-~~~~~~~~C- ~
11
CLKA
MACO
CTL
CHK
0
I.
~
1 0
' - p-
1
-,- ~
•
SLAO
,
ABCHK
REFRESH
Figure 39.
Interconnect Register Write
TEST DETECTION COMMAND
The Test Detection command is used to check that
the detection circuits in the MCU are operating correctly. The command is invoked by an interconnect
register write to the Test Detection register address
(see the iAPX 432 Interconnect Architecture Reference Manual). The iAPX 432 instruction MOVE TO
INTERCONNECT, executed on a GDP, causes the
interconnect write cycle. The MCU reports the status of the test via the three-phase error report
method described earlier. (See BERLOUT pin description.) If the test found no errors, the "no error"
message is sent. If the test encountered an error, the
. "module error" message is sent.
1
Two Test Detection executions are shown in Figures
40 and 41, one each for the master and checker
components in a FRC pair. Each of the. diagrams
consist of five parts. The two components operate
identically except for the manner in which they
check the BUSSEL signal (see cycles 10 and 11).
The master operates the memory bus detection cir~
cuits with BUSSEL=O. The checker issues the complement, BUSSEL=1. External logic checks the two
BUSSEL signals and reports the disagreement on
the BCHKIN/M input.
5~138
210963-{)02
inter
IAPX 43204, 43205
•
~ ~ ~ t"":'- ~ h- h- i'--' h- h- h-h-h- h0
CLICA
1
2
3
5
4
7
10
9
8
11
12
13
•
MACD
CTI.
CHK
1
8LAD
'-- ...J
ABCHK
BU88EL
BCHK
BCHKIN/M
--
,..........
r---.
,..........
Ir-----o
---..
......-r---.
I'---'
I'---'
~
. Figure 40.
1.
CLICA
15
18
17
I'----'
I'----'
......-......--.
~
Ir--
~
Ir-- ~ Ir--
I'----'
Ir--
Test Detectlon...,.Master
18
20
18
22
21
25
l!4
23
28
27
h-. '"""\...J h- '"""\...J """"\....J ~ """"\....J r-w """'"\..... """'"\..... ~ '"""\...J h- -"\..-
MACD
cn
CHK
8LAD
......a.....
DCIIH
"
ABCHK
BUS8EL
,BCHK
~
BCHKIN/M
~
roo-I--
~
~
It---
Ir-----o
I'---'
I'----'
......-- I'--
Ir--
~
,..........,
,..........
~
r-- I'----r-- ~ Ir-- I'---- Ir-,
''---
Figure 40.
I'---<
~
~
.
____ I r - - , - -
rest Detection-Master (con~lnued)
5-139
210963-002
"
IAPX 43204, 43205
a
a
CUCA
30
31
32
:13
34
3S
31
31
37
'"""\..." ~ ~ ~ "'""'\..... ~ '"""\..." ~ ~ f\-.
'.
I"-'
MACD
en
CHK
AIICHK
BUSSEL
BCHK
~
BCHklNIM
I'----'
r-~
~
~
r-~
I'---'
~
r-- I'----'r-~
r--
I'-----"
~
~
r-~
I'-I'-~
figure 40.,.. Detection-Master (continued) ,
0
CLKA
MACD
I
2
3
4
8
5
•
10
11
12
13
41EO
I
CHK
1
' - I--'
-
BU8BEL
BCHICINIM '
•
~ h- ~ t-"-- h- ~ h- h- h- ~ h- h- h- t"""'-
en
BCHK
7
,--~
,---
~
....--. ~ ,.-- ......... ,--- ~
~
I'----'
~
,.--
~
......... ,---
~
~
r---:-
Io.-...j
...--
-
"""-
f'-----I
"
Figure 41. , . . DeiectIon-Checker
5-140
210963.Q02
inter
IAPX 43204, 43205
15
14
CLKA
18
17
1.
21
20
19
22
23
25
24
II
27
f'-- f'-.. ~ f'-.. f'-- r'--' ~ h-- ~ f'-- "--' ~ f'-.. t""'-
MAC\)
CTL
CHK
.LAD
t---L".....
,
ABCHK
BUa.L
BCHK
8CHKINIM
r---.... ~ '---" ~ I""-"'- r-- ' - - ~ '----' ~ '----' ~
r---r---i
t
r----'"
r-r--r'---'
'-'---'
'---"
~
~
--
-
\
'----'
'----'
..---
--
Figure 41. Teat Detection-Checker (continued)
II
CLKA
MACD
29
30
31
32
33
34
35
36
·37
38
~ I"""- ~ r'- r'- h...... ~ t""'- t""'- f'-- ~
ClL
CHK
SLAD
ABCHK
BUSSI!L
BCHK
BCHKINIM
,.....-..--- r-----~
r--r-'-I\---'
1\---1
rr - --.... ..--- I\----' ..--- I\----' ~ ' - '---"
~
~
1'----1
--
,.....--
Figure 41. Teat Detectlon..!.Checker (continued)
5-141
210963-002
. iAPX 43204, 43205
CLEAR MEMORY COMMAND
The Clear Memory command is invoked by an interconnect register write to the Clear Memory register.
The MCU performs the command by writing zero
data and appropriate ECC information to all storage
array locations. The same hardware configuration
that was used for memory read and write cycles is
assumed. The MCU returns a reply to the requester
as soon as it accepts the command but will not
perform any further requests until it has cleared the
memory. As seen in Figure 42, the MCU issues
0
CLKA
MACD
cn
1
2
3
4
storage array write cycles beginning at the highest
storage array address (in this case, 03FFFH) and
decrements through remaining addresses (03FFEH,
03FFDH, ... ). Notice that the ECC and zero data
information changes for each successive cycle
(BOOOOOOOOOH, D200000000H, A600000000H, etc.).
This occurs because ECC is computed across data
and address information. This process continues
until all storage locations have been cleared. Only
the first few cycles of the p,rocess are demonstrated.
6
5
7
•
9
10
11
12
13
"--' ~ ~ "--'rG ~ "--' """""\..:.., ~ "-.,.... ~ ~ ~ '""""'.
'IIEO
1
600E
1
......i...
"---
.....!.-
CHK
SLAD
ABCHK
Figure 42.
Clear Memory Command
5·142
210963-002
inter
IAPX 43204, 43205
15
14
18
17
18
19
20
~ ~ ~ ~ ~ ~ f""""\..-.
CLKA
MACD
21
22
23
as
24
"-" r-'- ~ ~
~
28
~'
~~
CTL
CHK
03FFf
-
8l1000
' - ....J
03FFE
"
D2000
'-- ~
'-L-.I
'-- L-.I
FIgure 42. Clear Memory Command (continued)
I
28
CLKA
21
30
h- ~ h-
IIACD
CTL
CHK
SLAD
oM'\.
iiiS
DEIN
WE
ASCHK
h- ~
\.....Lr
,
figure 42. Clear Memory Command (continued)
5-143
03F1'D
JAPX 43204, 43205
Table 4. IAPX 43205 Clock Edge Table
Input Sample
Signal
Inputs
INIT
BERl1
BERl2
RQ
.CONT
BCHKIN/M
ABCHK
Outputs
RAS
DEIN
WE
REFRESH
BERlOUT
BCHK
BUSSEl
Input/Output
MACD15 ... 0
CTl2 ... 0
CHK1 ... 0
MBOUT
SlAD19 ... 0
,
Pln(s)
Clock
37
38
39
9·
10
4
45
' ClKA
ClKA
ClKA
ClKA
Cl-KA
ClKA
ClKA
48
47
46
44
40
6
5
n/a
n/a
n/a
n/a
n/a
n/a
n/a
13-28
29-31
11-12
32
1-2,51-68
ClKA
.ClKA
ClKA
ClKA
ClKA
.
Output Drive
Edge
Clock
Rising
Rising
Rising
Falling
Falling
Rising
Rising
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Rising
Rising
Rising
Rising
Rising
5-144
Edge
ClKA
ClKA
ClKA
ClKA
ClKA
ClKB
ClKA
Falling
Falling
Falling
Falling
Rising
Rising
Rising
ClKB
ClKB
ClKB
ClKA
ClKA
Rising
Rising
Rising
Rising
Falling
210963-002
IAPX 43204, 43205
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Range •...... OOC to 70°C
Storage Temperature ........ -65°Cto +150°C
Voltage on Any Pin with
Respect to Ground .••........ -1.0V to +7V
Power Dissipation ....•.............. 2.5 Watt
"NOTICE: Stresses abOve those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those Indicated in the operational sections of this specification is not Implied.
Exposure to absolute maximum rating conditions
for extended periods l1Jay affect device reliability.
IAPX 43205 DC Characteristics
Symbol
Min
Description
Max
Units
Vile
Clock input low voltage
-0.5
+0.8
V.
Vihc
Clock input high voltage
3.2
Vcc+0.5
V.
Vii
Input low voltage
Vlh
Input high voltage
Vol
Voh
-0.5
+0.8
2.0
VCC+0.5
V.
Output low voltage
-
0.45
V.
Output high voltage
SLAD19 ..0
Other outputs
2.6
2.4
VCC
VCC
V.
V.
.,
. V.
iii
Input leakage current (measured at Vln=VCC Volts)
-
±10
JAA,.
110
Output leakage current (measured at 0.45 Volts S Vout
S VCCVo!ts)
-
±10
JAA,.
loh
Output high current (measured at Vout=2.6 V.)
-2
101
Output low current (measured at Vout=0.45 V.)
Icc
Power supply current (sum "Of VCCO. VCC1. VCC2)
mAo
4
-
-..
450
mAo
mAo
All DC parameters are guaranteed over the following conditions:
VSS2..VSSO - oVolts
VCC2 ..VCCO ~ 5.0VoHs ±10%
The absolute value of the differential DC voltage between any of the vee pins (VCC2..VeeO) must be less than 0.1
VoHs. This is normally guaranteed by connecting the three VCC pins to the same printed circuit power trace.
"
5-145
210963-002
"rd_l®
111'eI
iAPX43204, 4'3205
iAPX 43205 AC Characteristics
Ambient temperature range of O°C to 70°C
5 MHz
Max
Min
Symbol
Description
t r • tf
Ciock rise and fall times
-
t1' t 2• t3' t4
Clock pulse width
37
tcy
Clock cycle tim~
200
tcd
Clock to signal delay time
-
70
-
60
tdh
Clock to signal hold time
20
17
ten
Clock to signal output enable time
20
-
Clock ,to signal data float time
-
tdc
Signal to clock setup time
t mc
tie
, tdf
Min
:SMHz
7 MHz
Max
Min
-
11
-
250
25
250
1000
143-
1000
13
Unit
Max
10
nsec
24
250
nsec
125
1000
nsec
-
55
nsec
-
15
nsec
17
-
15
-
50
-
44
-
40
nsec
30
-
26
24
-
nsec
MACD input setup time
30
-
26
-
24
-
nsec
Initialization period
40
100
40
100
40
100
tcy
nsec
All AC parameters are guaranteed over the following conditions:
Ambient temperature range of 0 degrees Centigrade to 70 degrees Centigrade
VSS2 , , , VSSO = 0 Volts
VCC2 , , ,VCCO = 5,0 Volts ± 10%
100 picoFarad external load capacitor on all output pins
iAPX 43205 Capacitance Data
Conditions:
Ta = 25°C
VCC = 5,0 Volis. GND = 0.0 Volts
f(test) = 1.0 MHz
Inputs held at 0.0 Volts
All outputs in high impedance state
All input/output pins are classified as outputs
Description
Symbol
Cin
Cout
Input Capacitance
Output Capacitance
• 5-146
Max
Units
6
pF
12
pF
210963-002
· iAPX 43204, 43205
WAVEFORMS
Clock Input Timing Specification
~y ------------~
I,
CLKA
CLKS
1,
Initialization Timing Specification
CLKA
~------------ I~ ------------~
5-147
210963-002
IAPX ~204. 43205
WAVEFORMS (Continued)
IAPX 43205 Input nmlng Speclftcatlon
BERL1,8ERL2,
BCHKINIM,ABCHK,
, INVALID
INVALID
MBOUT
INVAUD
RQ,CONT,
MACD(1~),
CTL(2-0)
CHK(1-G)
INVALID
INVALID
5-148
210963-002
inter
iAPX 43204, 43205
WAVEFORMS (Continued)
IAPX 43205 Output Timing Specification
CLKA
CLKB
MACD(1S·0)
CTL(2·0)
DATA
CHK(1-CI)
DATA
DATA
BCHK
DATA
BERLOUT,
MBOUT,
DATA
BUSSEL
5-149
~10963-o02
iAPX 43204, 43205
WAVEFORM,S (Continued)
S~orage
Array Bus Output Timing Specification
CLKA
SLAD(19-0)
DATA
DATA
---
DATA
1.,
RAS, WE,
DEIN,
REFRESH
DATA
DATA
DATA
Storage Array Bus Input Timing Specification
CLKA
SLAD(19-0)
5-150
210963-002
inter
iAPX 43204, 43205
HARDWARE INTERFACING
This section presents examples of hardware that
interfaces iApX 432 processors (the iAPX 43201/
43202 General Data Processor (GOP) and the iAPX
43203 IMerface Processor (IP), the iAPX 43204 Bus
Interface Unit (BIU), and the iAPX 43205 Memory
Control Unit (MCU) to one another (see Figure 44).
These examples present some alternatives for building iAPX 432 systems using the interconnect components. A wide variety of systems may be built with
the interconnect components and this list of examples explores only a few dimensions of the design
space.
Figure 45 illustrates the connection of a BIU to the
serial error reporting networks. Here, the BIU connects to the module error report line (MERL) and
has a duplicated bus error report line (BERL 1 and
BERL2). Each error report line is driven by open
collector inverters so that the BIUs along either the
module or bus axes may contribute error messages
in wired-OR fashion. Two inverters are required to
drive each error report line, one is a standard
inverter and the other is an open collector version.
The example shown also duplicates the bus error
report lines so that bus error messages may be
delivered even if one of the inverter paths fails.
Should duplicated bus error report lines not be
required, one of the two inverter groups could be
deleted and the BERL 1 and BERL2 signals connected together.
MEAl
.,U
......
""
DC
•
A_
""
MERLOUT
STD
BEJit:6Ur
I
•
T
iERU iiE'iii:2
1
~7
s:ro
~7
~7
DC
,\7
.•
ERL1
ERl2
Figure 45.
Figure 44.
Interfacing IAPX 432 Processors to
the BIU
5-151
Interfacing a BIU to Error Reporting
Network
210963-002
inter
IAPX 432.04,43205
The 432 hardware system designer must provide an
external arbitration network which examines the
BIU's arbitration signals, along with other BIUs in
the system, to determine when it is permissible to
use the memory bus. Two 'alternatives for this
function are presented in Figures 46 and 47. The first
method requires the fewest backplane signal lines
since it utilizes multilevel analog Signalling to arbitrate forthe bus. The second method requires more
backplane signals and unique wiring for each arbitrating unit but is fully digital.
RQ
With either method, each BIU produces two output
signals, RQOUT and NREQOUT, which are activated
to indicate that the BIU requires the use of the
memory bus. Each BIU requires that an external
logic network examine all the NREQOLlTs and
RQOUTs to identify when a request is being made
by one or more Bills." Three inputs to the BIU
(NREQ, RQ and CO NT) are generated by the'
external logic. NREQ (New Request) is activated to
signal that a new time-ordering cycle has occurred,
RQ (request) signifies that one or more RQOUTs
are active and CaNT (contention) signifies that
more than one RQOUT is actilie.
BIU
MASTER
CONT
CONi'
I
NREQOUT
I
~NE521
RQOUT
T.
ft
[
~,
RQ
BIU
CHECKER
1
'7
u
¢
~
¢
~
T
NREQM
NREQC
ARBM
ARBC
T
Figure 46.
Interfacing the BIU to the MACD Bus Arbitration Network
(Analog Method)
5-152
210963-002
IAPX 43204, 43205
RQ1
•
•
•
PROM
OR
PLA
~----~r-----------+-----~------------------~RQ
!
~----~t------------+--~~t-----------~-------iCONT
CONTI
RQ
RQOUT
BIU
BIU
•••
I
NREQOUT
Y
Figure 47.
NAEQ
Interfacing the BIU to the MACD Bus Arbitration Network
(Digital Method)
Figure 48 shows the required bus transceivers
which connect a BIU to a memory bus. In addition,
the drawing suggests how the oscillating BCHK
signal may be used to check that the external
buffers are operating correctly.
.,U
.'U
CHECKER
MASTER
OCTAL
TRANSCEIVER
""'....,..
........ MACD(1o-a)
BUStO ....<-<~
INIT
.. MAC.
3CTL
...!£!!!L
2t BUSUNES
Figure 48. Interfacing the BIU to the MACD BUS
5-153
21 9963-002
IAPX 43204~ 43205
MCU. provides the precise signals required to manage the arrays. Figures 50 and 51 detail the array
sequencing logic and the timing of signals which
coordinate the actions of the storage array.
Figure 49 illustrates how an MCU. an external RAM
storage array. and external sequencing logic form a
memory subsystem. In this example. economical
dynamic RAM components form the storage arrays
and the array sequencing logic. under control of the
L
~----~~-----------4----~--------~~C
H
~.
....W"'E"'l__- I
AOR
S~~E 1-£!~:~2__.:../
SE~g~~gER
01
DYNAMIC RAM
STORAGE ARRAY #2
I-'!W.!:OE2L---I.t
01
INIT
DATA
MCU
Figure 49. Interfacing the MCU to the Storage Array
5-154
210963-002
inter
IAPX 43204. 43205
,
Loa
ClKB
1....-
74S74
----0
0
CAS2
--
0
MUX1
----
MUX2
0
ClKA
.-0
-
RAS
-
WE
CAs1
0
RAs1
0
0
0
0
0
0
'--- 0
,0
_0
_0
0
_0
0
DO
RAS2
WE1
WE2
L-D
-
.,
I
74S374
A
I~
__ r
0 -0
1
0E1
74574
DELAYED
0E2
ClKA
ClKB
·OPTIONAl DELAY TO
AVOID BUFFER CONTENTION
Figure 50. Sequencing Logic for the Storage Array
5~155
210963-002
IAPX43204; 43205·
CLKA
CLKB
/
RAS1\
RAS2
/
\
MUX1,
/
MUX2
\
CASt
\
/
CAi2
ADDRESS
TOARAY#1
ADORESS
TO ARRAY #2
0Ei
\
ROW
X
/
X
COLUMN
X
ROW
\
X
COLUMN
/
0E2
~t9 ••• 0
/
-'"\
3---{
DATA
\~
X~
/ I
0E2
7
}:j------------------_J
DATA
DELAYED
-~
Figure 51. Timing Diagram for the Storage Array Interface
5-156
210963-002
inter
IAPX 43204, 43205
External hardware must be employed to permit an
MCU to attach to its normal or backup memory bus.
There are several facets to this requirement. Naturally, individual bus transceivers must be used to
allow the MCU, throug!l its BUSSEL (bus select)
output Signal, to choose which memory bus will
carry its address, control, data, and check information. In addition, the MCU must access error report
information and arbitration information from the
correot memory b~., These requirements are met
by the I!ort of network illustrated in Figure 52. Notice
that these requirements are unique to the MCU. One
BIU is required for each bus that a processor wishes
to attach to, no such,steering is required for a BIU.
The next example highlights some of the considerations when extending these requirements to fault
tolerant systems.
...
.......
TOLEIIANT
.....cr
LDOIC
_
.....
Figure 53. Fault lblerant Bus Select Network
logic which enables only one of the two sets of
memory bus transceivers when the BUSSELs are
both active. If there is any discrepancy in the BUSSELs, the external logic must disable both of the bus
transceiver sets so that the malfunctioning MCU
cannot corrupt either memory bus.
:::j::=::=::=::=::=::==::=:::=::=::=t :~I~T'ON ERROR
Figure 52. Interfacing the MCU to ~o Memory
8uuea
Fault tolerant MCU configurations require that special external logic enable the transceivers which
connect the MCU to"its assigned memory bus. This
may be done with a scheme illustrated in Figure 53.
Two MCUs are employed in a FRC configuration. At
their FRC interface, all the MACD, CTL, CHK signals
as well as the MBOUT direction signal are compared for error. The master and checker MCUs each
develop a version of the BUSSEL signal. Since it is
not possible to FRC the BUSSEL signal and guarantee a correctly operating version, external hardware
must be employed to develop a fault tolerant version
of the bus selection function. The individual BUSSELs must be checked by external fault tolerant
This same technique must also be applied to other
signals which must be routed to/from the currently
assigned memory bus. The BERLOUT error report
signal must onlegeFJt.uWE~t01the correctly selected
bus. The RO,
,
L , and 'B'ERD signals
must only be received from the correctly selected
bus.
Special logic is also required to check those Signals
which are not FRCed in a fault tolerant configuration. The BCHK output pins and the BCHKIN/M
input pins of the master and checker MCUs may be
used to detect errors in the external logic. In Figure
54, a PROM is used as the error detector. The inputs
to the PROM may come from a variety of sources,
depending on ·the particular hardware configuration. In this example, the PROM observes two sets of
Signals, one set from the master and another from
5-157
210963.(JO~
IAPX 43284, 43205
, , \ ,!
the checker. Notice that the oscillating BCHK signal
is routed through the bus transceivers in different
directions depending on the value of the MBOUT
signal. The fault tolerant versions of the BUSSEL
sign'!!.!!lect collection of signals to be checked.
The INIT input to the PROM provides a convenient
way to establish master/checker roles during initialization since BCHKIN/M carries mastership information at that time.
PACKAGE
BUS
TRANSCEIVERS
Figure 54. DetectIng Erro... In External MCU logic
The 43204 and 43205 are packaged in S8-pin. leadless JEDEC type A hermetic chip carriers. Figure 55
illustrates the package. and Figures 9 and 11 show
the pinouts.
F
·094
(2.39)
.088
(1.88)
.050
it:·D n
.800
(ZO.32)
.980
(24.38)
I {:'::)r
L.
~.,,,~
PIN NO. 1
PIN NO. 1 MARK
J~
.130
(3.30)
.980
(24.38)
Figure 55. 43204 and 43205 JEDEC Ty~ A Package
. &-158
210963-002
Peripherals
Peripherals
Section
6
".,',",
',i,. :
,i,'"
'.\:
'
'-"
"
•
inter
APPLICATION
NOTE·
AP·97A .
April 1982
' - - -_ _ _ _ _ _ _ _ _ _-----1
6-1
OROER NUMBER: 21038Bm1
,
'
I
INTRODUCTION
Table 1. Comparison of Intel Static and
Dynamic RAMs Introduced during 1981
The designer of a microprocessor-based system has two
basic types of devices available to implement a random
access read/write memory- static or dynamic RAM.
Dynamic RAMs offer many advantages. First, dynamic
RAMs have four times the density (number of bits per
device) of static RAM~, and are packaged in a 16-pin
DIP package, as opposed to the 20-pin or larger DIPs
used by static RAMs; this allows four times as many
bytes of memory to be put on a board, or alterllatively,
a given amount of memory takes much less board space.
Second, the cost per bit of dynamic RAMs is roughly
one-fourth that of statics. Third, static RAMs use about
one-sixth the power of static RAMs, so power supplies
may be smaller and less expensive. These advantages are
summarized in Table I.
2167·70
(Static)
Density
(No. of bits)
No. of pins
Access time (ns)
Cycle time (ns)
Active power (rna)
Standby power (rna)
Approx. cost per bit
(millicents/bit)
64K
16
150
300
60
5
45
16K
20
70
70
125
40
250
In addition, dynamic RAMs may not always be able to
transfer data as fast as high-performance
microprocessors require; wait states must be generated
in this case. The circuitry required to perform these
functions takes up board space, costs money, and consumes power, and so detracts from the advantages that
make dynamic RAMs so appealing. Obviously, the
amount of support circuitry should be minimized.
On the other hand, dynamic RAMS require 'complex
support functions which static RAMs don't, including
•
•
•
•
2164·15
(Dynamic)
address multiplexing
timing of addre,sses and control strobes
refreshing, to prevent loss of data'
arbitration, to decide when refresh cycles will be
performed.
The Intel 8202A and 8203 are LSI dynamic RAM controller components. Either of these 4O-pin devices alone
does all of the support functions required by dynamic
RAMs. This results in a minimum of board space, cost,
and power consumption, allowing maximum advantage
from the use of dynamic RAMs.
LOG21COST)
CONTROLLER
CS LOGIC
4K
8K
16K
32K
64K
128~
LOG21RAM SIZE) (K BYTES)
Figl,lre 1. Implemented Cost of Static vs. Dynami~RAM
6-2
A~N:
02200A
AP·97A
Addressing
Figure 1 shows the relative cost of static and dynamic
RAM, including support circuitry, as a function of
memory size, using the Intel ~202A or 8203. For any
memory larger than 16KBytes, the dynamic RAM is less
expensive. Since the cost of the dynamic RAM controller is relatively independent of memory size, the cost
advantge for dynamic RAM increases with increasing
memory size.
Each bit of a dynamic RAM is individually addressable.
Thus, a 2164A, which contains 216 (or 65,536) bits of information, requires 16-bit addresses; similarly, the
2118, which contains 214 (or 16,384) bits, requires 14-bit
addresses.
In order to reduce the number of address pins required
(and thus reduce device cost), dynamic RAMs timemultiplex addresses in two halves over the same pins.
Thus a 2164A needs only 8 address pins to receive 16-bit
addresses, and the 2118 needs only 7 for its 14-bit addresses. The first address is called the row address, and
the second is called the column address. The row -address is latched internal to the RAM by the falling edge
of the RAS (Row Address Strobe) control input; the column address is latched by the falling edge of the CAS
(Column Address Strobe) control input. This operation
is illustrated in Figure 3.
This Application Note will describe the techniques of interfacing a dynamic RAM memory to an iAPX-86 or
iAPX-88 system using either the 8202A or 8203 dynamic
RAM controller. Various configurations of the 8086
and 8088 microprocessors, and those timings which they
satisfy, are described. The Note concludes with examples of particular system implement(ltions.
" DYNAMIC RAMS
This section gives a brief introduction to the interfacing
requirements for Dynamic RAMs. Later sections will
describe the operation of the Intel 8202A and 8203
Dynamic RAM Controllers.
Dynamic RAMS may be visuallized as a twodimensional array of single-bit storage cells arranged
across the surface of the RAM's die. In the case of the
2164A, this array would consist of 28 (or 256) rows and
28 (or 256) columns, for a total of 2 16 (or 65,526) total
bit cells (Figure 4). This is the source of the "row address" and "column address" terminology. Bear in
mind that any given RAM may not be physically implemented as described here; for instance, the 2164A actually contains four arrays, each one 27 rows by 27
columns.
Device Description
The pinout of two popular families of dynamic RAMs,
the Intel 2118 and 2164A, are shown in Figure 2. The
2118 is a 16,384 word by I-bit dynamicMOS RAM. The
2164 is a 65,536 word by I-bit dynamic MOS RAM.
Both parts operate from a single + 5v supply with a
± 10070 tolerance, and both use the industry standard
16-lead pinout.
The two parts are pinout-compatible with the exception
of the 2164 having one extra address input (A7, pin 9);
this pin is a no-connect in the 2118. Both parts are also
compatible with the next generation of 256K dynamic
RAMs (262,144 word by I-bit), which will use pin 1
(presently a no-connect on both the 2118 and 2164A) for
the'required one extra address input (J\S>. This makes it
possible to use a single printed circuit board layout with
any of these three types of RAM.
v••
v••
DIN
CAS
DIN
CAS
WE
DOUT
At;
WE
RAS
DOUT
Ac
RAS
Ao
'A2
A1
A3
A4 ,
As
Voo
CAS
WE
DOUT
Aa
A3
' RAS
A3
Ao
A1
A4
As
A1
A7.
v..
1
DIN
Ao
Voo
16K
.Aa
A4
As
A7
Voo
64K
256K
Figure 2. Dynamic RAM Pinout Compatibility
6-3
AFN.022OOA
AP.97A
ADDR'ESS
COLUMN
Figure 3. Dynamic RAM Addressing
COLUMNS
°H
1H
ROWS
°H
100H
1H
2H
3H
101H
102H
103H
2H
200H
201H
202H
2031l1t
3H
300H
301H
302H
4H
400H
401H
402H
303 (
403~
500H
501H
502H
5H
soy
l
1~
~HI
FEH
FFH
\1
IFEH
IFFH
2FEH
2FFH
\3FEH
3FF H
/
,
..........
'\
BIT CELL ADDRESS
11M,
~
~
FDooH
fi
F
FEoo H
H
FE01 H
FE02H'
FFoo H
FF01H
FF02H
~H
II FEFEH
II FFFEH
1\
--=
FCFF
H
FDFEH FDFFH
FEFFH
FFFFH
Figure 4. Bit Cell "Array"
CAS or WE, whichever oCcurs last. If WE goes active
before CAS (the usual case, called an "early write"),
write data is latched by the falling edge of CAS. If WE
goes active after CAS (called a "late write"), data is latched by the falling edge of WE (see Figure 5).
Memory Cycles
In this Application Note, we will discuss three types of
memory cycles - read, write, and RAS-only refresh.
Dymanic RAMs,may perform other types of cycles as
well; these are described in the dynamic RAM's data
sheet.
Late writes are useful in some systems where it is desired
to start the memory cycle as quickly as possible, to maximize performance, but the CPU cannot get the write
data to the dynamic RAMs quickly enough to be latched
by CAS. By delaying WE, more time is allowed for
write data to arrive at the dynamic-RAMs.
Whether data is read or Written during a memory cycle
is determined by the RAM's WE control input. Data is
written only when WE is active.
Note that when "late write" is performed, CAS goes active while WE is still inactive; this indicates a read cycle,
so the RAM enables its data output. So, if "late write" ,
cycles are performed by a system, the RAM data inputs
and data outputs must be electically isolated from each
other to prevent contention. If no "late writes" are performed, the RAM data inputs and data outputs may be
tiCjd'together at the RAM to 'reduce the ~umber of board
traces.
During a read Cycle, the CAS input has a second function, other than latching the column addr~s. CAS also
enables the RAM data output (pin 14) when active,
assuming RAS is also active. O~erwise, the data output
is 3-stated. This allows multiple dynamic RAMs to have
their data outputs tied in common.
- During write cycles, data on the RAM data input pin is
latched internally to the RAM by'th~d8lling edge of'
6-4
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Ap·97A
,---
~
~
~
DIN
DOUT
--------------------------~~
tOH
VALID
~
-J:>--------------
_________
IN_D_ET_E_R_M_IN_A_T_E________
B. "LATE WRITE"
\
~
DIN
>
tOH
VALID
K
)
DOUT ---------------------------------------------------------------------------A. "EARLY WRITE"
Figure 6. Dynamic .RAM Write Cycles
Access Times
Each dynamic RAM has two different access times
quoted for it -- access time from RAS active (tRAd and
access time from CAS active (tcAd; these are illustrated
in Figure 6. How do you know which to use? This
depends on the timings of your RAM controller. First,
the worst case delay from the memory read command
active to RAS active (tcRl and CAS active (tcd must be
determined. Then the read data access time is the larger
of the tCR(Controller) + tRAdRAM) or tcdController) .
+ tCAdRAM). An alternative way to deter~ine
whether to use tRAC or tCAC is to look at the dynamic
RAM parameter for RAS active to CAS active delay,
tRCD. tRcf)I1lax is a calculated value, and is shown on
dynamic RAM data sheets as a reference point only. If
the delay from RAS to CAS is less than or equal to
tRcDIlIax, then tRAC is the limiting access time parameter; if, on the other hand, the delay from RAS to
CAS is greater than t RcDIlIax, then tCAC is the limiting
parameter. tRcDIlIax is not an operating limit, and this
spec may be exceeded without affecting operation of the
RAM. tRcf)I1lin, on the other hand, is an operating
limit, and the RAM will not operate properly if this spec
. is viglated.
6-5
AFN: 02200A
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\
DOUT
Figure 6. Dynamic RAM Access Times
Refresh
Unfortunately, if left for very long, the charge will leak
out of the capacitor, and the data will be lost. To prevent this, each bit-cell must be periodically read, the
charge on the capacitor amplified, and the capacitor
recharged to its initial state. The circuitry which does
this amplification of charge is called a "sense amp".
This must be done for every bit-cell every 2 ms or less to
prevent loss of data.
One unique requirement of dynamic RAMs is that they
be refreshed in order to retain data. To see why this is
so, we must look briefly at how a dynamic RAM is
implemented.
Dynamic RAMs achieve their high density and low cost
mostly because of the very simple bit-storage cell they
use, which consists only of one transistor and a
capacitor. The capacitor stores one bit as the presence
(or absence) of charge. This capacitor is selectively accessed for reading and writing by enabling its associated
tra:nsistor (see Figure 7).
Each column in a dynamic RAM has its own sense amp,
so refresh can be performed on an entire row at a time.
Thus, for the 2118, it is only necessary to refresh each of
its 128 rows every 2 ms. Each row must be addressed via
the RAM's address inputs to be refreshed. To simplify
ONE COLUMN
~
}
ONE
ROW
BIT SELECT
LINES
(FROM ROW
ADDRESS
DECODER)
T
v+
T
v+
~
BIT SENSE LINES
(TO SENSE AMPS)
Figure 7. Dynamic RAM Cell
6-6
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ADDRESS
RAS
X
X
ROW
/
\
CAS
DON'T CARE
DOUT
Figure 8. RAS·only Refresh
refresh, the 2164A is implemented in such a way that its
refresh requirements are identical to the 2118; 128 rows
every 2 ms. Some other 64K RAMs require 256 row
refresh every 4 ms.
microseconds for 128 rows) no read or write cycles can
be performed. This severely limits the worst case
response time to interrupts and makes this approach unsuitable for many systems.
Refresh can be performed by a special cycle called a
RAS-only refresh, shown in Figure 8. Only a row address is sent; that row is refreshed. No column address is
sent, and no data is read or written during this cycle. Intel dynamic RAM controllers use this technique.
As long as every row of the RAM is refreshed every 2
ms, the distribution of individual refresh cycles is unimportant. Distributed refresh takes advantage of this fact
by performing a single refresh cycle every 2 ms/128, or
about every 15 microseconds. In this way, the refresh requirements of the RAM are satisfied, but the longest
time that read and write cycles are delayed because of
refresh is minimized. Those few dynamic RAMs which
use 256 row refresh allow 4 ms for the refresh to be completed, so the distributed refresh period is still 15
Any read, write, or read-modify-write cycle also
refreshes the row addressed. This fact may be used to
refresh the dynamic RAM without doing any special
refresh cycles. Unfortunately, in general you cannot be
sure that every row of every dynamic RAM in a system
will be read from or written to every 2 ms, so refresh
cannot be guaranteed by this method alone, except in
special applications.
microsecon~s.
The third technique is called transparent (or "hidden"
or "syncronous") refresh. This takes advantage of the
fact that many microprocessors wait a fixed length of
time after fetching the first opcode of an instruction to
decode it. This time is necessary to determine what to do
next (i.e. fetch more opcode bytes, fetch operands,
operate on intern!!l registers, etc.); this time may be
longer than the time required for a RAM refresh cycle.
If the status outputs of the CPU· can be examined to
determine which memorY cycles are opcode fetches, a
refresh cycle may be performed immediately afterward
(Figure 9). In this way, refresh cycles will never interfere
with read or write cycles, and so .appear "transparent"
to the microprocessor.
A third technique for refresh is called hidden refresh.
·This method is not popular in microprocessor systems,
so it is not described here, but more information is
available in the dynamic RAM's data sheet.
Three techniques for timing when refresh cycles are performed are in common use: burst refresh, distributed
refresh, and transparent refresh.
Burst refresh means waiting almost 2 ms from the last
time refresh was performed, then refreshing the entire
memory with a "burst" of 128 refresh cycles. This
method has the inherent disadvantage that during the
time refresh .is being performed (more than 40
Transparent refresh has the disadvantage that if the
microprocessor ever stops fetching opcodes for very
6-7
AFN 0220QA
AP·97A
INSTRUCTION
DECODE TIME
~
I
FETCH
OPCODE
FETCH
OPERAND
FETCH
OPERAND
I
•
TIME
TIME
•
B. REFRESH INTERFERES WITH OPERAND FETCH
r----------,
I
I
REFRESH
CYCLE
II
FETCH
OPERAND
L__________ .J
•
TIME
C. TRANSPARENT REFRESH
Figure 9. Transparent Refresh
ternal refresh request input (REFRQ) allows the
microprocessor's status to be decoded to generate a
refresh-cycle for transparent refresh. If, for whatever
reason, no external REFRQ is generated for 15
microseconds, the internally generated refresh will take
over, so memory integrity will be guaranteed.
long, due to a HOLD, extended DMA transfers, or
when under hardware emulation, no refresh cycles will
occur and RAM data will be lost. This pu~s restrictions
on the system design. Also, high speed microprocessors
do not allow sufficient time between opcode fetches and
susequent bus cycles for a complete RAM refresh cycle
to be performed, so they must wait for the refresh cycle
to complete before they can do a subsequent bus cycle.
These microprocessors cannot use transparent refresh to
any advantage. Transparent refresh is useful for
microprocessors like the Intel 8085 operating at low
clock frequencies.
Arbitration
Because RAMs cannot do a read or write cycle and a
refresh cycle at the same time, some form of arbitration
must be provided to determine when refresh cycles will
be performed.
The 8086 and 8088, 'however, prefetch opcodes into a
queue which is several bytes long. This prefetching is independent of the actual decoding and execution of the
opcodes, and there is no time at which it can be
guaranteed that the 8086 or 8088 will not request a
memory cycle. So transparent refresh is not applicable
to these microprocessors.
Arbitration may be done by the microprocessor or by
the dynamic R~ controller. Microprocessor arbitration may be implemented as follows:
A counter, 'running from the microprocessor's clock, is
used to time the period between refresh cycles. At terminal count, the arbitration logic asserts the bus. request
signal to prevent the microprocessor from performing
any more memory cycles. When the microprocessor
responds with a bus grant, the arbitration logic
generates a refresh cycle (or' cycles, if·burst refresh is
The 8202A and 8203 perform distributed and/or
transparent refresh. Each device has an internal timer
which automatically generates a distributed refresh cy-,
cle every 15.6 microseconds or less. In addition, an ex6-8
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02200A
AP·97A
used). After refresh is complete, the arbitration logic
releases the bus. This method has several disadvantages:
First, time is wasted in exchanging bus control, which
would not be required if the RAM controller did arbitration. Second, while refresh is being performed, al/
bus activity is stopped; for instance, even if the
microprocessor is executing out of ROM at the time, it
must stop until refr~sh is over. Third,. bursts of DMA
transfers must be kept very short, as refresh cannot be
performed while DMA is in progress.
before it can complete the read or write cycle. This
means that from when the microprocessor activates the
read or write signal, the time until the cycle can be completed can vary over a range of roughly 200 to 700 ns.
Because of this, an acknowledge signal from the
dynamic RAM controller is required to tell the
microprocessor the memory cycle it requested is complete. This signal goes to the microprocessor's READY
logic.
Memory Organization
Some microprocessors, such as the Zilog Z-80, generate
refresh cycles themselves after instruction fetches. This
removes the need for external arbitration logic, but still
has several disadvantages: First, DMA bursts still must
be kept short to allow the CPU to do refresh. Second,
this method adds to the complexity of the microprocessor, without removing the need for the RAM controller which is still required to do address multiplexing
and RAS, CAS and WE timing. Microprocessor refresh
can cause problems of RAM compatibility; for instance,
the Z-80 only outputs a 7-bit refresh address, which
means some 64K RAMs which use 256 row refresh cannot be used with the Z-80. Also, since the Z-80 refresh
cycle is Ii fixed length (no wait states), faster speed selections of the Z-80 are not compatible with slower
dynamic RAMs. Third, systems employing multiprocessing or DMA are harder to implement, .because of
the difficulty in insuring the microprocessor will be able
to perform refresh.
A single bank of -RAM will provide 64K words of
memory in the case of the 2164A, or 16K words in the
case of the 2118. To provide more memory words,
multiple banks of RAM are used. In this case, all address, CAS, and WE lines are tied to all RAMs, but each
bank of RAM has its own RAS. Each bank knows
whether it is being addressed during a read or write
operation by whether or not its RAS input was activated
- if not, then all other inputs are ignored during that
cycle.
It is preferable to have arbitration performed by the
dynamic RAM controller itself. This method avoids all
the problems described above, but introduces a complication. If the microprocessor issues a read or write
command while the dynamic RAM is in the middle of a
refresh cycle, the RAM controller must make the
microprocessor wait until it is done with the refresh
Data outputs for RAMs in corresponding bit positions
in each of the banks may be tied in common, since they
are 3-state outputs; even though 00 is connected to all
banks of RAM, only that bank whose RAS is active will
enable its data outputs in response to CAS going active.
Data inputs for RAMs in corresponding bit positions in
each of the banks are also tied in common.
INTEL DYNAMIC RAM CONTROLLERS
and 16K dynamic RAMs, including the Intel 2104A,
2117, and 2118. Tl1e pinout and simplified logic
diagram of the 8202A are shown in Figures 10 and 11.
As each dynamic RAM operates on only one bit at a
time, multiple RAMs must be operated in parallel to
operate on a word at a time. RAMs operated in this way
are called a bank of RAM. A bank consists of as many
RAMs as there are bits in the memory word. When used
in this way, all address and control lines are tied to all
RAMs in the bank.
The Intel 8202A and 8203 Dynamic RAM Controllers
each provide all the interface logic needed to use
dynamic RAMs in microprocessor systems, in a single
chip. Either the 8202A or 8203 allow a dynamic RAM
memory to be implemented using a minium of components, board space, and power, and in less design
time than -any other approach.
The 8202A is always in one of the following states:
a)
b)
c)
d)
e)
The following sections will describe each of these controllers in detail.
IDLE
TEST cycle
REFRESH cycle
READ cycle
WRITE cycle
The 8202A is normally in the idle state. Whenever a cycle is requested, the 8202A will leave the idle state to
perform the desired cycle; if no cycle requests are pending, the 8202A will return to the idle state. A refresh
cycle request· may originate internally or externally to
8202A
FUNCTIONAL DESCRIPTION
The 8202A provides total dynamic RAM control for 4K
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AH.
, AHS
Vee
AHs
AHa
X11CLK
XdOP2
N.C.
REFRQ ALE
~
liIlS1
WR
AH2
'AH1
AHo
ALo
'OUTo
AL1
OUT1
AL2
OUT2
ALs
OUTs
AL.
OUT.
ALs
OUTs
ALslOPs
OUTe
GND
SACK
XACK
WE
CAS
RASs
B1IO,P1
Bo
RAS2
RAS1
'RASo
Figure 10. 8202A Pinout
the 8202A; all other requests come only from outside
the 8202A.
A test cycle is requested by activating the RD and Wi
inputs simultaneously, independent of PCS (Protected
Chip Select). The test cycle will reset the refresh address
counter to zero and perform a write cycle. A test cycle
should not be allowed to occur in normal system operation, as it interferes with normal RAM refresh.
A refresh cycle performs a RAS-only refresh cycle of the
next lower consecutive row address after the one
previously refresh~d. A refrllSh cycle may be requested
by activating the REFRQ input to the 8202A; this input
is latched on the next 8202A clock. If no refresh cycles
are requested for a period of about 13 microseconds, the
8202A will generate one internally. By refreshing one
rowevery 15.6 microseconds or sooner, all 128 rows will
be refreshed every 2 ms. Because refresh requests are
generated',by the'8202A itself, memory integrity is insured, even if the rest of the system should halt operation for an extended period of time.
The arbiter logic Will allow the refresh cycle to take
place only if there is not another cycle:in progress at the
time.
A read cycle may be requested by activating the RD input, with PCS (protected Chip Select) active. In the Advanced Read mode, a read cycle is requested if the
microprocessor's SI status line is high at the 'falling edge
of ALE (Address Latch Enable) and PCS is active. If a
dynamic RAM cycle is terminated prematurely, data
loss may result. The 8202A chip select is "protected" in
that once a memory cyCle is started, 'it will go to completion, even if'the 8202A becomes de-selected.
A write cycle may be requested by activating the WR input, with PCS active; this is the same for the normal and
Advanced Read modes.
BLOCK DIAGRAM
Let's look at the detailed block diagram in Figure 12 to
see how the 8202A satisfies the interface requirements
of the dynamic RAM.
Address Multiplexing
Address multiplexing is achieved by a 3-to-l multiplexer
I
AHo·s - - - - - - - - - . / 1
ADDRESS
MUX
REFRQIALE
RDIS1
WR
PCS
RASo
RAS1
RAS2
RAS3
CAS
WE
SACK
XACK
B,10P1
Bo
/
Figure 11. 8202A Slm'pllfied Block Diagram
6-10
J
AFN,1l2200A
Ap·97A
AHo-e
ALo.e
OUTQ.6
Bo
Bl
XoIOP2
OSCillATOR
RASo
XllClK
RASl
RAS2
RAS3
REFRQ
RAS
RIC
~~~~ CAs
START
ALE
RDISI
GEN'R
I\'HIFT
EG.&
lOGIC)
EOC
CAS
WE
WE
SACK
SACK
XACK
XACK
OPl
Figure 12. 8202A Detailed Block Diagram
internal to the ,8202A; the three inputs are the row address (ALo.@, column address (AHa-c;), and refresh row
address (generated internally). When the 8202A is in the
Idle state, the multiplexer selects the row address, so it is
prepared to start a memory cycle. If a refresh cycle is requested either internally or externally l the address
multiplexer will select the refresh row address long
enough before RAS goes active to satisfy the RAM's
tASR parameter.
This has no effect on RAM operation; inverters are not
needed on the address outputs.
Doing this multiplexing internally mlrumlzes timing
skews between the address, RAS, and CAS, and allows
higher performance than would otherwise be possible.
Refresh Counter
The next row to be refreshed is determined by the.
refresh counter, which is implemented as a 7-bit ripplecarry counter. During each refresh cycle, the counter is
To minimize propagation delays, the 8202A address
outputs (OUTa-~ are inverted from. the address.inputs.
r---FROM MICROPROCESSOR ADDRESS BUS
Alo·&
REF. ADDR.·'
REF. AD DR.
Alo·6
l_'RAH_ _I
(
Figure 13. Detailed 8202A Refresh Cycle
6-11
AFN: 02200A
AP·97A
incremented by one in preparation for the next refresh
cycle (a refresh cycle is shown in detail in Figure 13).
When the 8202A enters TEST mode, the refresh counter
is cleared. This feature is useful for automatic testing of
the refresh counter function. Because the address outputs are inverted, the first refresh address after clearing
the counter in test mode is 7FH, and the addresses
decrease for subsequent refresh cycles.
RAS Decoding
Which bank of RAM is selected for a memory cycle is
determined by the RAS decoder from the BO.I inputs,
which normally come from the microprocessor address
bus. The 8202A Timing Generator produces an internal
RAS pulse which strobes the RAS decoder, generating
the appropriate external RAS pulse. The Bo.! inputs are
not latched, so they must be held valid for the length of
the memory cycle. During a refresh cycle, all the RAS
outputs are activated, refreshing all banks at once.
Oscillator .
The 8202A operates from a single reference clock with a.
frequency between 18.432 MHz and 25 MHz; this clock
is used by the synchronization, arbitration, and timing
generation logic. This clock may be generated by an onboard crystal oscillator, or by an external TTLcompatible clock source. When using the internal
oscillator (available only on part number D8202A-l or
Xo 36
X, 37
8202A
•. CRYSTAL MODE
12 v
±10%
1 K.n.
±s%
8202A
~
D8202A-3), a fundamental-mode crystal is attached to
pins.36 and 37 (Xo and XI), as shown in Figure 14. The
external TTL clock option is selected by pulling pin 36
(OP:z) to + 12v through lK ohm resistor, and attaching
the clock input to pin 37 (eLK).
Command Decoder
•
The command decoder takes the commands from the
bus and generates internal memory request (MEMR),
and TEST signals.
The 8202A has two bus interface modes: the "normal"
mode, and the "Advanced Read" mode. In the normal
mode, the 8202A interfaces to the usual bus RD and
. WR signals.
In the Advanced Read mode, the 8202A interfaces to
the Intel microprocessor bus signals ALE, SI, and WR.
SI must be high on the falling edge of ALE for read
cycles, and WR must be low for write cycles (write
cycles are the same as for normal read mode). The
8085A SI may be used directly by the 8202A; the 8086
and 8088 SI must be inverted. ALE and WR'must be
qualified by pes.
The Advanced Read mode is useful for reducing read
data access time, and thus wait states. This mode is used
mainly with 8085A systems.
If both RD and WR are active at once (regardless of the
state of peS), the internal TEST signal is generated and
the 8202A performs a test cycle as described above. One
or both of RD and WR should have pull-up resistors to
prevent the 8202A from inadvertantly being put into test
mode, as the RD and WR signals are 3-stated by the
microprocessor when RESET or HOLD are active.
Since the test mode resets the refresh address counter,
the refresh sequence will be interrupted; and data loss
may result.
Refresh Timer and REFRQ
The 8202A contains a counter, operated from the internal clock to time the period from the last refresh cycle.
When the counter times out, an internal refresh request
is generated. This refresh period is proportional to the
8202A's clock period, and varies from 10.56 to 15.625
microseconds. Even at the lowest refresh rate, all the
rows of the dynamic RAM will be refreshed every 2 ms.
ClK 37
I
b. EXTERNAL CLOCK MODE
7-----~--------------~--~
Figure 14. 8202A Clock Options
The 8202A has an option of reducing the refresh rate by
a factor of two, for use with 4K RAMS. These RAMs
have only 64 rows to refresh every 2 ms, so need refresh
cycles only half as often. This option is selected by puIlAFN: 02200A
Ap·97A
ing pin 18 (AL6"OP3) to + 12v through a S.IK ohm
resistor. This pin normally serves as the high-order row
address input for the address multiplexer, but it is no
longer needed for this function, as 4K RAMs have one
less address input.
A refresh cycle may also be requested externally by activating the REFRQ input. This input is latched, so it
only needs to be held active a maximum of 20 ns. If the
8202A is currently executing a memory cycle, it will
complete that cycle, and then perform the refresh cycle.
The internal and external refresh requests are ORed
together before going to the arbiter.
The REFRQ input cannot be used in the Advanced
Read mode, as the REFRQ pin is used for ALE in this
mode.
REFRQ is most often used to implement transparent
refresh, as explained in the section Dynamic
RAMS - Refresh. This technique is not useful in iAPX
86 and iAPX 88 systems, so REFRQ is normally tied to
ground.
The refresh timer is reset as soon as a refresh cycle is
started (whether it was requested internally or externally). The time between refresh cycle (tREF) is measured
from when the first cycle is started, not when it was requested, which occurs sometime earlier. Of course,
tREfiIrln does not apply if REFRQ is used - you may
externally request refresh cycles as often as you wish.
Arbiter
This is the hardest section of a dynamic RAM controller
to implement. If a read or write arrives at the same time
as a refresh request, the arbiter must decide which one
to service first. Also, if a read, write, or refresh request
arrives when another cycle is'already in progress, the arbiter must delay starting the new cycle, until ,the current
cycle is complete.
Both of the internal signals REFR (refresh request) and
MEMR (memory cycle request) are synchronized by
D-type master-slave lip-flops before reaching the arbiter. these circuits have been optimized to resolve a
valid logic state in as short a time as possible. Of course,
with any synchronizer, there is a probability that it will
fail - not be able to settle in one logic state or the other
in the allowed amount of time, resulting in a memory
failure - but the 8202A has been designed to have less
than one system memory failure every three years,
based on operation in the worst case system timing
environments. '
Both synchronizers and the arbiter are operated from
the 8202A's internal clock. Assuming the 8202A is initially in an idle state, one full clock period after the synchronizers sample the state of the MEMREQ and
REFREQ signals, the arbiter examines the REFR and
MEMR outputs of the synchronizers. If MEMR is active, the arbiter will activate START to begin the
memory cycle (either read or write) on that clock. If
REFR is active (regardless of the state of MEMR), the
arbiter will activate START and REF to begin a refresh
cycle on that clock. Once the cycle is complete, the Cycle Timing Generator will generate an end-of-cycle
(EOC) signal to clear the arbiter and allow it to respond
to any new or pending requests on the next clock.
Once a memory cycle is started, it cannot be stopped,
regardless ofthe state of the RD/SI, WR, ALE, or pes
inputs. This is necessary, as ending a dynamic RAM
cycle prematurely may cause loss of data. Note,
however, that the RAM WE output is directly gated by
the WR input, so if WR is removed prematurely, the
RAM WE pulse-width spec (twp) maY be violated, caus'ing a memory failure.
What happens if a memory request and refresh request
occur simultaneously?
If the 8202A is in. the idle state, the memoT;Y request
will be honored first.
'
If the 8202A is not in the idle state (a memory or
refresh cycle is in progress) then the memory cycle
will lose priority and the refresh cycle will be honored
first.
Remember, if the 8202A is performing a cycle, the arbiter doesn't arbitrate again until the end of that cycle.
So the memory and refresh cycles are "simultaneous" if
they both happen early enough to reach the arbiter
before it finishes the current cycle. This arbitration arrangement gives memory cycles priority over refresh
cycles, but insures that a refresh cycle W1~1 be delayed at
most one RAM cycle.
Refresh Lock-Out
As a result of the 8202A operation, transparent refresh
circuits iike the one shown in Figure IS should not be
used. This circuit uses the RD input, with some qualifying logic, to activate REFRQ whenever the microprocessor does an opcode fetch. This circuit will work fine,
as long as the 8202A never has to generate an internal
refresh request, which is' unlikely (if nothirtg else, the
system RESET, pulse is probably long enough that the
8202A will throw in' couple of refreshes while the
microprocessor is reset). If the S202A ever does generate
its own refresh, there' is a ptobability that the
microprocessor will try to fetch an opcode while the
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When the cycle is complete, the Cycle Timing Generator
sends anend-of-cycle (EOC) pulse to the arbiter to
enable it to respond to new or pending cycle requests.
refresh is still in progress. If that happens, the 8202A
will finish the refresh, see both the RD andREFRQ inputs active, honor the REFRQ first, and start a second
refresh. In the meantime, the microprocessor is sitting
in wait states, waiting for the 8202A to complete the opcode fetch. When the 8202A finishes the second refresh,
it will see both RD and REFRQ active again, and will
start a third refresh, etc. The system "locks up" with
the microprocessor sitting in wait states ad infinitum,
and the 8202A doing one refresh cycle after another.
Minimum and maximum values for the 8202A
parameters tCR (Command to RAS active delay) and tcc
(Command to CAS active delay) differ by one 8202A
clock period. This is because the commands (RD, WR,
ALE) must be synchronized to the 8202A's clock; this
introduces a ± one clock period (tp) uncertainty due to
the fact that the command mayor may not be sampled
on the first clock after it goes active, depending on the
set-up time. If RD or ALE and WR are synchronous to
the 8202A's clock, and the set-up time (tsd is met, the
smaller number of clock periods will apply.
All 8202A output timings are specified for the
capacitive loading in the data sheet. Typical output
characteristics are shown in the data sheet for capacitive
loads ranging from 0 to 660 pF, these can be used to
calculate the effect of different loads than those
specified in the data sheet on output timings. All address, RAS, CAS, and WE drivers are identical, so these
characteristic curves apply to all outputs.
Figure 15. Improper Transparent
Refresh Generation
To prevent this from happening, the transparent refresh
circuit should be modified as shown in Figure 16. In this
circuit, REFRQ cannot be activated until the opcode
fetch is already in progress, as indicated by SACK being
active (remember, SACK is never active during a
refresh), If the microprocessor tries to do an opcode
fetch while the 8202A is doing a refresh, REFRQ will
not be active; the 8202A will finish the refresh and see
only RD active, and will start the opcode fetch; only
then will REFRQ be activated.
8085A
Because refresh cycles are performed asynchronously to
the microprocessor's operation (except during
transparent refresh), the microprocessor cannot know
when it activates RD or WR if a refresh cycle is in progress, and therefore, it can't know how long it will take
to complete the memory cycle.
This added consideration requires an acknowledge or
"handshake" signal from the 8202A to tell the
microprocessor when it may complete the memory
cycle. This acknowledge would be used to generate the
microprocessor's READY input - the microprocessor
will sit in wait states until the 8202A acknowledges the
memory cycle. Two signals are generated for this purpose by the 8202A; they are called system acknowledge
(SACK) and transfer acknowledge (XACK). They serve
the same purpose but differ in timing.
8202A
5,
So
SACK AND XACK
REFRQ
SACK
AD
RD
Figure 16. Generating Transparent
Refresh For SOS5A Systems
XACK is a Multibus-compatible signal, and is not activated. until the rea,d or write cycle has been completed
by the RAMs. In a microprocessor system, however,
there is. a considerable delay from when the 8202A
acknowledges the memory cycle until the microprocessor actually terminates the cycle. This delay is due
to the time required to combine this acknowledge with
other sources of READY in the system, synchronize
READY to the microprocessor's clock, sample the state
of READY, and respond to an active READY signal.
As a result, more wait states than necessary may actual-
Cycle Timing Generator
The Cycle Timing Generator consists of a travellingones shift register and combinational logic required to
generate all the RAM control signals and SACK and
XACK.All timings are generated from the 8202A's internal clock; no external delay lines are ever needed. The
timing of these. signals relative to CLK is illustrated in
Figure 17.
6-14
AFN· 02200A
·1
ClK
r-\
Ir-\
0
2
4
6
7
9
I.
RD
WR
ALE
PCS
...
ADDRESS
ROW
COLUMN
ROW
J>
RAS
'U
en
~
.!..
01
CAS
READ CYCLE
WE
SACK
WRITE CYCLE
---------..,1",-
----------~~~~~~.£~----------------NORMAL SACK
XACK
(EOC)
,.
~
~
g
8
~
Figure 17. 8202A Timing Relative To elK
Ap·97A
ly be generated by using XACK. SACK is activated
earlier in the cycle to improve performance of
microprocessors by compensating for the delays in the
microprocessor responding to XACK, and thus
eliminating unneeded wait states which might be
generated as a result of XACK timing. The system
designer may use one or the other acknowledge signal,
or use both in different parts of the system, at his
option.
SACK and XACK are activated by the Cycle Timing
Generator, but they can be de-activated only by the
microprocessor removing its RD or WR request, or by
activating ALE when in the advanced read mode. As the
SACK and XACK signals are used to generate READY
for the microprocessor, this is necessary to give the
microprocessor as much time as it needs to respond to
its READY input.
8202A memory cycle will have SACK delayed, even if
that cycle was not actually delayed due to a refresh cycle
in progress, The delayed SACK flip-flop will be reset at
the end of that cycle, and the 8202A will return to normal SACK operation. The same thing happens in Advanced Read mode if S1 is high at the falling edge of
ALE during a refresh cycle, once again regardless of the
state of PCS.
8203
The 8203 is an extension of the 8202A architecture
which allows the use of 64K dynamic RAMs. It is pinout
compatible with the 8202A and shares identical A.C.
and D.C. parameters with that part. The description of
the 8202A applies to this part also, with the modifications below.
ENHANCEMENTS
Delayed SACK Mode
SACK may be activated at one of two different times in
the memory cycle; the earlier case is called "normal
SACK" and the later is called "delayed SACK" (Figure
18). Delayed SACK occurs if the memory request was
received by the 8202A while it was doing a refresh cycle.
In this case, the memory cycle will be delayed some
length of time while the refresh cycle completes; SACK
is delayed to ensure the microprocessor will generate
enough wait states. This is a concern mostly for read
cycles.
Because of the way the delayed SACK mode is implemented in the 8202A, if the RD or WR input is. activated while a refresh cycle is in progress, regardless of
whether or not the 8202A is chip-selected, the internal
delayed SACK mode flip-flop will beset. The next
RAS
\~
1.
Supports 16K or 64K dynamic RAMs. 4K RAM
mode, selected by pulling AL6"OP3 (pin 18) to
+ 12v, is not supported.
2.
Allows a single board design to use either 16K
or 64K RAMs, without changing the controller,
and only making between two and four jumper
changes to reconfigure the board.
3.
May operate from external TTL clock without
the + 12v pull-up which the 8202A requires (a
+ 5v or + 12v pull-up may be used).
The pinout of the 8203 is shown in Figure 19. This
pinout is identical to the 8202A, with the exception of
the five highlighted pins. The function of these is
described below. The simplified block diagram is similar
to the 8202A's, in Figure 1i.
----J/
_ _
Figure 18. Delayed SACK Mode
6-16
AFN" 02200A
AP·97A
8202A's pins are already used, this is clearly a challenge
- some functionality must be sacrificed to gain 64K
RAM support. The 8203 reduces the maximum number
of banks supported from four to two for 64K RAMs.
AH.
AHa
AH2
AH,
AHo
ALo
Pin 35 (16K164K) is used to tell the 8203 whether it is being used to .control 16K RAMs or 64K RAMs. When
tied to Vcc or left unconnected, the 8203 operates in the
16K RAM mode; in this mode all the remaining pins
function identically to the 8202A. When tied to ground,
it operates in the 64K RAM mode, and pins 23 through
26 change function to enable the 8203 to support 64K
RAMs. Pin 35 (16K/64K) cpntains an internal pull-up
-when unconnected, this input is high, and the 8203
operates identically to the 8202A. This maintains pinout
compatibility with the 8202A, in which pin 35 is a noconnect, so the 8203 may be used in 8202A sockets with
no board modifications.
!roTo
AL,
OUT,
AL2
!roT2
~3
OUTa
AL.
OUT.
AL5
!roT5
ALe
OUT.
v..
.
16K Mode and 64K Mode
The goal of the 8203 is to provide a pin- and timingcompatible upgrade of the 8202A for use With 64K
RAMs. The difficulty in dOing this is that 64K RAMs require an additional address input compared to 16K
RAMs, and thus the 8203 needs three more pins (one
more RAM address output, and two more inputs to its '
internal address multiplexer). Since all but one of the
ALo·.
ALo-e
Au-A,3
RASo 2,
A,.
24 Bo(AL7)
A'5
25 B, (AH7)
J1
CS (32K WORDS) ~
~ (64K WORDS) -0
~ (128K WORDS)·---.:8
J5
.1-=A, •
..:g
~ PCS
'
~
.
4 RAS
RAS, 22
2118
(2164)
RAS2 23
(OUT7)
9 N.C. (A7)
RASa(Bo)
J4 33
.
When the 8203 is in the 64K RAM mode, four pins
change function, as shown in Table 2. The pins change
function in this particular way to allow laying out a
board to use either 16K or 64K RAMs with a.minimum
of jumpers, as shown in Figure 20. This figure shows the
8203 with two banks of RAM. Banks 0 and 1 may be
either 16K RAMs or 64K RAMs; banks 2 and 3 mayonly be 16K RAMs, as the 8203 supports two banks of 64K
RAM. For clarity, only those connections which are im-.
portant in illustrating. the 8203 jumper options. are
shown.
. Fig. 19 8203 Pinout
BANK 0
~
8203
,
~ RAS
16K164K
2118
(2164)
J8
~
16K f,~~ t~:i~~~~tJ;ION
J1·J2 (64K WORDS)
L.
~
64K RAM JUMPER OPTION
J2·J4 (64K WORDS)
J3·J4 (128K WORDS)
J5.J6
J7·J8
BANK 1
N.C. (A7)
TO RAS OF BANK 2
(2118 ONLy)
TO RAS OF BANK 3 •
(2118 ONLY)
;
"
-
,
Figure 20.1 8203 Jumper Options
6-17
AFN 02200A
AP·97A
Table 2. 16K164K Mode Selection
Pin #
23
24
25
26
16K Function
64K Function
RAS2
Bank Select (BO)
Bank Select (B 1)
RAS3
Address Output (OUT7)
Address Input (AL7)
Address Input (AH7)
Bank Select (BO)
Jumpers JI-J4 may be used to chip select the 8203 over
various address ranges. For example, if two banks of
16K RAMs are replaced with two banks of 64K RAMs,
the address space controlled by the 8203 increases from
32K words to 128K words. If four banks of 16K RAMs
are replaced with one bank of 64K RAMs, no chip select
jumpers are needed.
In the 64K RAM mode, pins 24 and 25 (Bo(AL7) and
Bl(AH7» change function from bank select inputs to
address inputs for the 64K RAM. Since the bank select
inputs normally come from the address bus anyway, no
jumper changes are required here. The bank select function moves to pin 26 (RAS 3(BQ»; since only two bank of
64K RAM is supported, only one bank select input is
needed in this mode, not two. Jumpers J6 and J7 are
shorted in the 64K RAM mode to connect pin 26 (Bo) to
the address bus. In the 16K RAM mode, these jumpers
must be disconnected, as pin 26 junctions as the RAS3
output; in the 64K RAM mode, this bank is not populated, so RAS 3 is not needed.
Pin 23 serves two functions: in the 16K RAM mode it is
the RAS output for bank 2 (RAS~, in the 64K RAM
mode is the high order RAM address output (OUT7),
which goes to pin 9 of the 64K RAMs. This requires no
jumpers as when using 16K RAMs, pin 9 is a noconnect, and when using 64K RAMs, bank 2 is
depopulated, so RAS2 is not used.
This arrangement allows converting a board from 16K
RAMs to 64K RAMs with no change to the controller
and changing a maximum of three jumpers.
+ 5v External Clock Option
Just as with the 8202A, the user has the option of an external TTL clock instead of the internal crystal
oscillator as the timing reference for the 8203; unlike the
8202A, he does not need to tie pin 36 (XolOP~ to + 12v
to select this option-this pin may be tied to either + 5v
or + 12v. If pin 36 is tied to + 12v, a lK ohm (± 5Ofo)
series resistor must be used, just as for the 8202A. If pin
36 is tied to + 5v, it must be tied directly to pin 40 (V cJ
with no series resistor. This is because pin 36 must be
within one Schottky diode voltage drop (roughly 0.5v)
of pin 40 to select the external TTL clock option; a
series resistor may cause too great a voltage drop for the
external clock option to be selected. For the same
reason, the trace from pin 36 to 40 should be kept as
short as practical.
Test Cycle
An 8203 test cycle is requested by activl\ting the RD.
WR, and PCS inputs simultaneously. By comparison,
an 8202A test cycle requires activating only the RD and
WR inputs simultaneously, independent of PCS. Like
the 8202A, and 8203 test cycle resets the address counter
to zero and performs a write cycle.
AHQ.• _ _ _ _ _ _ _ _--./
ADDRESS
MUX
RASa
REFRQIALE
RDIS1
RAS,
RAS2
TIMING.
B"OP,_......_ _ _ _ _ _--IGENERATOR
Bo---------~
RAS3
CAS
WE
SACK
XACK
16KI64R:-----'"
Figure 21.8203 Simplified Block Diagram
AFN.02200A
Ap·97A
BLOCK DIAGRAM
it to support RAMs which use either the 128-row
or 256-row refresh schemes. Regardless of which'
type of RAM is used, the refresh counter cycles
through 256 rows every 4 ms. RAMs which use
128-row re-fresh treat the eighth address bit as a
"don't care" during refresh, so they see the
equivalent of 128-row refresh every 2 ms. In
either case the rate of internally-generated
refresh cycles is the same-at least one every
15.6 microseconds.
A simplified block diagram of the 8203 is shown in
Figure 21. It is identical to the 8202A except for the
following differences:
1. The 3:1 address multiplexer is 8 bits wide, instead
of 7 bits wide, to support the addressing
requirements of the 64K RAM.
2.
The refresh address counter is 8 bits. This allows
INTEL iAPX·86 AND iAPX·88
In the minimum mode, the microprocessor supports
small, single-processor systems using a minimum of
components. In this mode, the 8086 or 8088 itself
generates all the required bus control signals (Figure
22).
Device Descriptions
The iAPX-86 and iAPX-88 are advanced 16-bit
microprocessor families, based on the 8086 and 8088
microprocessors, respectively. While both have a similar
architecture and are software compatible, the 8086
transfers data over a 16-bit bus, while the 8088 uses an
8-bit data bus (but has a 16-bit internal bus).
In the maximum mode, the microprocessor supports
larger, higher performance, or multiprocessing systems.
In this mode, the 8086 or 8088 generl;ltes status outputs
which are decoded by the Intel 8288 Bus Controller to
provide an extensive set of bus control signals, and
Multibus compatibility (Figure 23). This allows higher
performance RAM operation because the memory read
and write commands are generated more quickly than is
possible in the minimum mode. The maximum mode is
the one most often used in iAPX-86 and iAPX-88
systems.
Min and Max Modes
In order to support the widest possible range of applications, the 8086 and 8088 can operate in one of two
modes, called minimum and maximum modes. This
allows the user to define certain processor pins to
"tailor" the 8086 or 8088 to the intended system. These
modes are selected by strapping the MN/MX
(minimum/maximum) input pin to Vee or ground.
MilO
READY
ClK
CPU
ALE
8282
A16·191 /L-----'"
ADD15
8284A
GEN'R
8086
lATCH
SHE
ClK
TO
TOCPU
READY
lOGIC
. Figure 22. 8086 Minimu.m Mode
6-19
AFN: 02200A
AP·97A
. READY
8284A
CLK
GEN'R
CLK
TO CPU
READY
LOGIC
Figure 23. 8086 Maximum Mode
control signal using the min or max mode in the normal
configuration.
Alternate Configurati(m
The Alternate Configuration is not an operating mode
of the 8086 or 8088 per se, but uses TTL logic along with
the status outputs of the microprocesor to generate the
RAM read and/or write control signals (Figure 24). The
alternate configuration may be used with the
microprocessor in either minimum or maximum mode.
This configuration is advantageous because it activates
the memory read and write signals even earlier than the
maximum mode, leading to higher performance. It is
possible to generate either the RAM read or write signal
using this configuration, and generate the other RAM
Each of the three system configurations may be used
with buffers on the address, data, or control bus for increased electrical drive capability.
Performance VS. Wait States
Before starting a discussion of timing analyses, it's
worthwhile to look at the effect of wait states on the
iAPX-86 and iAPX-88.
Vee
8284A {
CLK - - - - - - - - - - - - ,
CLOCKED AMWC
8086
8088
{STATUS
. (S0.2)
--,..-------.1'1
I
TO
8202AI
8203
ALE
8288
~~~~
Figure 24. Alternate Configuration Logic
6-20
AFN:02200A
Ap·97A
'For most microprocessors, the effect of, say, one wait
state on execution times is straightforward. If a bus
cycle normally is three clocks long, adding a wait state
to every bus cycle will make all bus cycles four clocks,
decreasing performance by 331170. This is multiplied by
the percentage of time that the microprocesor is doing
bus cycles (some instructions take a long time to execute, so the microprocessor skips a few bus cycles).
which don't use an instruction queue. The effect of wait
states on 8086 execution time compared to the Motorola
68000 and Zilog Z8000 for a typical mix of software is
summarized in Table 3.[11
Table 3. Effects of Walt States on Execution Time
Execution Time Increase
Over 0 Wait State
Execution Time
The effect of wait states on the iAPX-86 and iAPX-88 is
not so straightforward, however.
The 8086 and 8088 microprocessors consist of two processing units: the execution unit (EU) executes instructions, and the bus interface unit (BIU) fetches instructions, reads operands, and writes results. During
periods when the EU is busy executing instructions, the
BIU "looks ahead" and fetches more instructions from
the next consecutive addresses in memory; these are
stored in an internal queue. This queue is four bytes
long for the 8088 and six bytes long for the 8086; under
most conditions, the BIU can supply the next instructions without having to perform a memory cycle. Only
when the program doesn't proceed serially (e. g. a Jump
or Call instruction) does the EU have to wait for the
next instruction to be fetched from memory. Otherwise,
the instruction fetch time "disappears" as it is proceeding in parallel with execution of previously fetched
instructions. The EU then has to wait for the BIU only
when it needs to read operands from memory or write
results to memory. As a result, the 8086 and 8088 are
'less sensitive to wait states than other microprocessors
i
Processor
1 Walt
State
2 Wait
States
3 Walt
States
26.3"70
8.3"70
16.3"70
iAPX 86/10 (measured)
38.2"70
57.3"70
Z8000 (computed)
19.1"70
47.8"70
68000 (computed)
31.9"70
15.9"70
The BIU can fetch Instructions faster than the EU can
execute them, so wait' states only affect performance to
the extent that they make the EU wait for the transfer of
operands and results. How much this affects program
execution time is a function of the software; programs
that contain many complex instructions like multiplies
and divides and register operations are slowed down less
than programs that contain primarily simple instructions. The effect of wait states on the 8086 and 8088 is
always less than on other microprocessors which don't \
use an instruction queue.
[I]
From 16-Bit Microprocessor Benchmark Report:
iAPX-~6, Z8OOO, and 68000, pub!. by Intel Corp.
1980
Figure 25. 8086 Max Mode System
6~21
AFN 02200A
AP·97A
,t
AL:~~~;r
AHO-AH6 --/ 12==--------------------' ~----------~~-
~~~-
\
'I
lASH
i---IAC
I
ICAS
V
1\
-IASA_
;.
I-IAAH- ' i:'--IASC-
ROW
,~
! - - I C A_ _
COLUMN
~
Figure 26. Memory Compatibility Timing
Timing Analysis
This section will look at two specific system configurations to show how the 8203 timing requirements are
satisfied by the 8086. Methods of determining the worst
case number of wait states for the various configurations are also given.
The timings of the 8202A and 8203 are identical; only
the 8203 is referred to for the remainder of this note, but
all comments apply equally to the 8202A. All timings
are worst case over the range of T A = 0 - 70·C and
Vcc = + 5v ± 10070 for the test conditions given in the
devices' data sheets.
I
Example 1. 8086 Max
Mode System (5 MHz)
This example (Figure 25) is representative of a typical
medium-size microprocesor system. Example I requires
one wait state (worst case) for memory cycles: Example
2 also uses an 8086 in Max'mode at 5 MHz, but uses externallogic to reduce the number of wait states to zero
for both read and ,write cycles.
Table 4. Memory Compatibility Timings
(all parameters are minimums)
Symbol
tASC
tASR
teAH
teAS
tRAH
tRCDU)
tRSH
Parameter
Value
Column Address Set-Up Time
tp-30
Row Address Set-Up Time
!p-30
Column Address Hold Time
S!p-30
CAS Pulse Width
S!p-IO
Row Address Hold Time
!p-IO
RAS to CAS Delay Time
2!p-40
RAS Hold Time from CAS Stj,-30
(l]tRcomin = tRAHmin + tASCmin = 2p - 40
.
This parameter is the minimum RAS active to CAS
active delay.
These timings are all a function of the 8203's clock
period (tp); they may be adjusted to be compatible with
'slower dynamic RAMs by slowing the 8203's clock (increasing tp). The frequqncy of the 8203's clock may be
varied from 18.432 MHz to 25 MHz; for best performance, the 8203 should be operated at the highest possible frequency compatible with the chosen dynamic
RAM. In most cases, 1RAH or teAS will be the frequency
limiting parameter, but the 8203 can operate at its maximum frequency with most dynamic RAMs available.
DYNAMIC RAM INTERFACE
First, look at the timing requirements of the aynamic
RAM to ensure they are satisfied by the 8203. Memory
compatibility timings are shown in the 8203 data sheet
(Figure 26). Seven 8203 timings are given, not counting
tAD, which will be discussed in the next section. Tliese
timings are summarized in Table 4.
tASR applies only to refresh cycles. When the 8203 is in
the ItHe state (not performing any memory or refresh
cycles) the address multiplexer allows the AL0-7 inputs
.(the RAM row address) to propagate through to the
8203 OUT0-7 pins, which are connected to the RAM address pins. So in read or write cycles, the row address
will 'propagate direcfly from the address bus t6 the
AFN' 02200A
Ap·97A
RAM; the row address set·up time in this case is determined by the microprocessor's timing (see the next section). At the beginning of a refresh cycle, the 8203 has
to switch its internal multiplexer to direct the refresh
row, address to the RAMs before activating RAS; the
tASR parameter in Table 4 refers to this case only.
Assume the Intel 2164A-20 RAM (200 ns access time) is
used. Equations l(a)-(h) show that this RAM is compatible at the 8203's maximum operating frequency of
25 MHz (tp = 1/(25 MHz) = 40 ns). This frequency
will be used for now; once the rest of the system timings
are calculated, the minimum 8203 frequency which will
provide the same system performance can also be determined.
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
tASC
tASR
tCAH
tCAS
tRAH
tRCD[I]
tRP
tRSH
= tp - 30 =
= tp - 30 =
= 5tp - 30 ::,
5tp - 10
= tp - 10
= 2tp - 40
10 (Equation 1.)
10
170'
190
=
30
40
130
= 4tp - 30
= 5tp - 30 = 170
[IJ May be calculated as
tRcomin = tRAHmin + tASCmin
= 2tp - 40
ADDRESS SET·UP AND HOLD TIME MARGINS
The microprocessor must put the memory address on
the address bus early enough in the memory cycle for it
to pass through the 8203 and meet the row address setup tirhe to RAS (tASR> requirement of the dynamic
RAM (Figure 27). Since the address propagates directly
through the 8203, this set-up time is a function of how
long the microprocessor holds the address on the bus
before activating the RD or WR command, the address
delay through the 8203 (tAomax), and how long the
8203 waits before activating RAS (tcRmin). This is
shown in Figure 28, and calculated in Equation 2. This
and all follo~ equations show timing margins; a
positive result mdicates extra margin, a zero result says
the parameter is just met, and a negative result indicates
it is not met for worst-case conditions.
Row Address Set-Up Time Margin .
(Equation 2.)
CPU Address to RD Delay+ RAS
Activ,e Delay, - Addrc;ss Delays
TCLCL(5MHz) + TCLML min (8288) +
tCRmin(8203) - [Greater of
TCLAVmax(8086) + TIVOVmax (8282) or
TCLLHmax(8288) + TSHOVmax(8282)] tAomax(8203) - tASR(2164A-2O)
200 + 10 + [40 + 30] ~
[Greater of (110 + 30) or (15 + 45)] - 40 - 0
100
Figure 27. Address Set·Up and Hold Time-Margins
6-23
AFN 02200A
T1
CLK(8284A)
T2
~
\
\
!\
1\
1"'--
!---TCLAV-
\V
BHEI(8086)
/1\
AO-19
BHE. Ao ,.VA·LlD
!-+-TCLLH-
ALE(8288)
V
/
.
TIVOV
TSHOV
0>
N
.j>.
ADDRESS BUS
\V
:J>
'V
cD
VALID
/I\'
~
I--tAO--
)
OUT 0.7(8203)
== Ao·7(2164·20)
VALID
!--tASR-
\
MRDC 1(8288)
AMWC
1\
1\
RAS(8203)
i-TCLML
,....
;;:
~
Figure 28. Address Set· up Time Margin
tCR-
-<.
T2
T3
TW
T4
T1
CLIq8284A)
ALE(8288)
•
~
ADDRESS BUS
CJ)
I
I\)
U1
:=1(/as(8203)
CAS(8203)
;
i
tRSI!
/
~
I
--_ ... _ - - - - - - - - -
Figure 29. Address Hold Time Margin
AP·97A
READ DATA ACCESS TIME MARGIN
Similarly,' the microprocessor must maintain the
memory address long enough to satisfy the column address hold time (teAH> of the RAM; the 8203 TAJ)Il1in
parameter should be used for this calculation.
Read data access times determine how many wait states
are required for read cycles. Remember that dynamic
RAMs have two access time parameters, RAS access
time (!RAd and 00 access time (leAd. Either on~ may
be the limiting factor in det(lrmining RAM access time,
as explained in the section Dynamic RAM - Acce.s:s
Times, above. Here teAC is the limiting factor, as
More importantly, the 8203 bank select (80-1) inputs are
also not latched; these are used directly to decode which
RAS output is activated during read or write cycles, so
these inputs must be held valid until RAS goes inactive.
Since BO-I are usually taken directly from the address
bus, this determines the address hold time required of
the system (Figure 29). These are easily satisfied by the
8086 as shown by Equation 3. N represents the number
of wait states. This equation can be tried with various
values for N (starting with 0 and increasing) until the
equation is satisfied, or it can be set equal to zero
(meaning no excess margin remru.ns) and solved for N
directly; the fractional value for N that results must be
rounded up to get the worst-case number of wait states
to satisfy this particular parameter. No wait states are
required to meet address hold times.
tecmax + teACmax
~
teRmax + tRACmax.
This timing is shown in Figures 30 and 31, and is
calculated in Equation 4. In this system, one wait state is
required to satisfy the read data access time requirements of the system; the margin is -50 ns, which is
too large a difference to be made up by using a faster
RAM.
Address Hold Time Margin (N = 0)
(Equation 3.)
CPU Address Hold Time, from
RD Active - RAS Inactive Delays
(3 + N)TCLCL(SMHz) +
TCLLHmin(8288)[I) + TSHOVmin(8282)TCLMLmax(8288) - tccmas(8203) tRSHmax(8203) [2)
3(200) + 2 + 10 - 3S - [4(40) + 8S] [5(40) + 30]
102
[I)
Not specified - use 2 ns
[2)
Not specified in 8203 data sheet;
tRsHmax(8203) = Stp + 30
A
8086
, 0
~
8282
RAM
8284
01100
Si. 51.Sot--tllII-"V' J
elK
8286
OE
T
, Figure 30. Read Data Acce~s Time Margin
'6-26
I
AFN: O22OOA
T2
T3
T4
TW
CLK(8284A)
MRDC(8288)
1-1.-----
. ICC
-I
~
CAS(8203)
"V
0>
cD
N
-..t
~
. Doun2184·20)
VALID
VALID
DATA BUS
ADO·1s(8086)
>
."
?!'
i
Figure 31. Read Data Access Time Margin
AP·97A
Read Data Access
(Equation 4.)
Time Margin (N = 0)
CPU lID Active to Data Valid Delay CAS Active Delay - Data Delays
(2 + N)TCLCL(SMHz) - TCLMLmax(8288)
tccmax(8203) - tCAcmax(2164A-20) - ,
tpmax(74S373)[I) - TIVOVmax(8286) TDVCLmin(8086)
2(200) - 3S - (4(40) + 8S] - 11030(1) - 30 - 30
- 80=>1 wait state needed (N = 1)
WRITE DATA SET·UP AND HOLD TIME MARGINS
In write cycles, the write data must '
1.
reach the dynamic RAMs long enough before
CAS to meet the RAM's data set-up time ,
parameter" tos (Figures 32 and 33), and
2. ,be held long enou8h after CAS to meet the
RAM's data hold time' parameter (tow (Figures
32 and 34.)
Data set-up time margin is calculated in Equation S, and
data hold time margin is given in Equation 6. Again,
these are margins, so a positive number indicates that
system timing requirements are met for worst-case timings. Data hold time is a function of the number of 8086
wait states, represented as N, as is the read data access
time margin. No wait states are required to meet this
parameter.
,(Equation S.)
'Write Data Set-Up Time Margin
CPU WR Active to Data Valid Delay +
CAS Delay - Data Delay
TCLMLmin(8288) + tccmin(8203) TCLDVmax(8086) - TIVOVmax(8286) tosmin(2164A-20)
- 10 + (3(40) + 2S]-110 - 30 - 0
,IS
'
Write Data Hold Time
(Equation 6.)
Margin (N = 0)
CPU Data Hold Time, from AMWC
Active + Data Delays - CAS Active Delay
(2 + N)TCLCL(SMHz) + TCLCHmin(8284A)
+ TCHDXmin(8086) + TIVOVmin(8286)
- TCLMLmax(8288) - tccm8x(8203) tDHmin(2164A-20)
2(200) + (~(200) - IS] + 10
+ S - 3S - (4(40) + 8S] - 4S
308
(I) tp(74S373) is the greater of tpHL (from data) or
tpLH (from data) and is compensated for Vee and
, temperature variations, and is derated for a
300pF load (T.I. spec is at ISpF).
tP(74S373) = 13n8 + O.OSns/pF(300 - IS)pF
+ 2.7Sns = 3Ons.
Where 13ns is T.I. spec value
O.OSns/pF is deratingiactor
for excess capacitive load
(300 - 1S) is excess capacitive
load 2.7S is compensation for
T A and Vee variation
Figure 32. Write Data Set·Up and Hold Time Margins
6-28 .
AFN:022OOA
AP·97A
11
CLK(8284A)
T2
\
\
1\
r\.
TCLML
\
AMWC(8288)
1\
ICC
\
CAS(8203)
!--TCLDV-
ADO·le(8088)
ADDRESS
\If
DATA
J\
g~;:l~:'~)I------------------~. . _____...
-TIVOV
los_
*,--_V_A_L_ID_ __
Figure 33. Write Data Set·Up Time Margin
SACK SET·UP TIME MARGIN
As explained earlier, SACK (and XACK) are "handshaking" signals used to tell the microprocessor when it
may terminate the bus cycle in progress. Thus, SACK
timing determines how many wait states will be
generated, as opposed to how many wait states are actually required for proper operation, which is determined by the read data access ·time for read cycles and by
the write data hold time for write cycles. If SACK
causes more wait states than are required, there is a per·
formance penalty, but the system operates; if too few
wait states are generated, the system will not function.
SACK and XACK serve the same function; they differ
only in timing. XACK is Multibus compatible, and is
activated only when the read data is actually on the bus
(in a read cycle) or when the write data .has been latched
into I the RAM (in a write cycle). SACK is activated
earlier in the memory cycle than XACK to compensate
for delays in the microprocessor responding to this
signal to terminate the cycle. Use of SACK is normally
preferable, as it results in the fewest possible wait states
being generated. But in some systems, SACK will not
generate a sufflCient number of wait states, so XACK or
a delayed form of SACK must be used. Note that the
number of wait states generated by SACK and XACK
will vary, depending on whether a refresh cycle is in pro·
gress when the memory cycle was requested, and if
refresh cycle is in progress, how near it is to completion.
SACK is sampled by the 8284A Clock Generator Chip's
RDYI or RDY2 input. The 8284A can be programmed to treat these inputs as either synchronous or asynchronous inputs by tying its ASYNC input (pin 15)
either high or low, respectively. SACt must be treated
as asynchronous unless it has been synchronized to the
microprocessor's clock with an external flip-flop.
SACK set·up time is shown in Figures 35 ~nd 36, and is
calculated in Equation 7. This equation indicates that,
at worst case, one wait state will be generated (n = 1).
This satisfies ·the requirements of the systeln, namely
one wait state for reads and zero (or more) wait states
for writes.
'
SACK Set-Up Time Margin (N = 0)
(Equation 7.)
RD or WR Active to SACK Active Delay
(N)TCLCL(5MHz) + tpLHmin(7404)[11 TCLMLmax(8288) - tCAmax(8203)
- tsumin(74S74)
o + 1 - 35 - [2(40) + 471 - 3
-164 => 1 wait state wil be generated (N = 1)
We have only looked at '/worst case" SACK set-up time
so far, to determine the maximum number of wait states
that will be generated (assuming no delays due to a
refresh cycle in progress). We should look at "best
[II Not specified - use 1 ns.
6-29
AFN 02200A
12
T3
~'
CLK(8284A)
T4
V
\
\
1\
1\
~
\
I
\
1\
,
\
AMWC(8288)
1\
tcc
\
CAS(8203)
~l>
1:»
'1J
TCHDX
I
cD
IN
):
o
ADo-1s(8086)
~
\
I
DATA VALID
,
+-TCVNlI
DEN(8288)
,
I
,~
DATA BUS
>
;l!
Figl,lf8 34. Write Data Hold Time Margin
"------
,",,::TELOZ:-:--TlVOV)--
VALID
tDH
,I
\
"
intJ
AP·97A
~
ClK
Figure 35. SACK Set·Up Time Margin
T3
T2
TW
ClK(8284A)
MRDC )(8288)
AMWC
.
8ACK(8203)
ClK(74S74)
Q(74874)=
RDY1(8284A) ,
READY(8284A, 8086)
Figure 36. SACK Set·Up Time Margin
6-31
AFN: O22OOA
Ap·97A
case" SACK timing also, to make sure enough wait
states are always generated. Note that in Figure 35,
SACK goes through an external 74S74 flip-flop; this
samples SACK on-half. clock cycle earlier than th\l
8284A does (on the same clock edge that activates
MRDC or AMWC), effectively reducing SACK set-up
time by one-half clock period. This guarantees the proper number of wait state will be generated for "best
case" SACK timing. Adding this flip-flop does not increase the worst case number of wait states generated by
SACK.
In the case where a memory cycle is requested while a
refresh cycle is in progress, the memory cycle will be
delayed by a variable amount of time, depending Q11
how near the refresh cycle is to completion. This delay
may be as long as one full memory cycle if the refresh
was just starting; this time is about 650 ns, depending on
the 8203's clock frequency. SACK set-up, read data setup, and write data hold times to the microprocessor's
clock are not the same as in the usual case where there is
no refresh interference. In this case, SACK is delayed
until the read or write cycle has been completed by the
RAM, so that there is no possibility of terminating the
cytie too soon.
PCS SET·UP TIME MARGIN
The 8203:s RD, WR. and ALE inputs must be qualified
by PCS in order to perform a memory cycle. If the PCS
active set-up time parameter (tpcS> is violated, the
memory cycle will be delayed. In this case all maximum
delays normally measured from command (teR, tec,
tcA> will be measured instead from PCS active and will
be increased by tpcs (20 ns). Minimum teR, tec, teA
delays remain the same, but are measured from command or PCS whichever goes active later. If tpcs is
violated, care must be taken that PCS does not glitch
low while RD. WR, or ALE is active, erroneously triggering a memory cycle. tpcs is not violated in this
system. however (Equation 8).
PCS Set-Up Time Margin
(Equation 8.)
CPU Address Valid to Command Active
Delay - PCS Decode Time
TCLCL(5MHz) + TCLMLmin(8288)[Greater of TCLAVmax(8086) +
TIVOVmax(8282) or TCLLHmax(8288) +
TSHOVmax(8282)]
- tplllax(8205) -tpcsmin(8203)
200 + 10 - [Greater of (110 + 30) or
(15 + 45») - 18 - 20
32
RAM DATA OUT HOLD TIME MARGIN
The 8203 CAS output is only held valid for a fIXed
length of time during a read cycle, after that the RAM
data outputs are,3-stated. This time is not long enough
to allow the 8086 to read the data from the bus. so the
data must be latched externally. This latch should be a
transparent type and should be strobed by XACK from
, the 8203. Because the minimum time from XACK active
to CAS inactive is only 10 ns, a latch with a data hold
time requirement of 10 ns or less (such as a 74S373)
should be used (see Equation 9).
RAM Data Out Hold Time Margin,
(Equation 9.)
from XACK Active
tAcKmin(8203) + tOFFfIIln(2164A - 20)
- tHffiin(74S373)[1)
10 + 0 - 10
o
OTHER CALCULATIONS
Equations 3, 4, 6 and 7, may be solved directly for N,
where N is the number of wait states, to find how many .
wait states are required at a given frequency. Alternatively, a number may be substituted for N and these
equations solved for the 8086's clock period, TCLCL,
to find the maximum microprocessor frequency possible
with N wait states. Note that the clock high and low
times (TCHCL and TCLCH) are also a function of
TCLCL. Be sure to use the proper speed selection of the
8086 in this calculation, as various A.C. parameters are
different and the result may, be different for different
speed selections of the 8086, even at the same frequency.
Be sure to check the other equations at this frequency to
make sure they are OK, too.
Finally. for given values of TCLCL and N, Equations 3,
4. 6, and 7 may be checked to find the lowest 8203 clock
frequency which will aliow the same system performance, if it is desired to operate at some frequency
other than the 25 MHz we assumed.
CONCLUSION
This design will operate with, at worst case, one wait
state (except for refresh) at microprocessor frequencies
up to 6 MHz, using slow (200 ns access time) dynamic
RAMs. At 6 MHz, it is limited by a lack of SACK set-up
[1)
6-32
A 74S373 must be used to meet this timing requirement. Even though worst case margin is 0 ns,
this is not a critical timing; as valid data will hold
on the latch inputs for a considerable time after
the RAM outputs 3-state.
AFN:022OOA
AP·97A
delayed so long that there is no longer enough data hold
time, measured from when WE goes active; or that the
WE active to CAS inactive delay spec or the RAM
(tRWL> is violated. None of the control signals from the
8086 or 8288 bus controller satisfy both of these timing
constraints, so such a signal is generated by flip-flop
Al1.1, which serves to delay AMWC from the bus controller by an amount of time equal to TCLCH (the low
time of the 8086's clock). AIl.l is also preset by AIO.I
at the end of the memory cycle. The Q output of AII.I
is ANDed with WE from the 8203 by A14.1 to form a
delayed RAM WE. As in the previous example, this
signal is then ANDed. with BHE and AO to form the
WE for the high and low bytes of RAM, respectively.
time. At 5 MHz, the 8203 can be operated at any clock
frequency from 18.432 MHz to 25 MHz, still with only
one wait state.
Example 2. 8086 Alternate
Configuration System (5 MHz)
Figure 37 shows another 8086 Max mode system at 5
MHz, but this time using the Alternate Configuration,
which allows it to operate with no wait states (except for
refresh).
The system if) the previous example was limited by
SACK set-up time. SACK set-up time can be improved
by sampling SACK later; this has been done by changing
the clock edge used to sample SACK, allowing roughly
213 clock period longer. SACK set-up time (and read data
access time and write data hold time) margin can also be
improved by activating the RD or WR inputs of the 8203
earlier in the 8086's bus cycle; this is the purpose of the
extra logic in Figure 37 (I.C.s A8 - All). These generate
advanced RD and WR signals timed from the falling
edge of ALE, which occurs roughly 'h clock period
sooner than the MRDC and AMWC are generated by the
8288 BlJs Controller. Altogether, ,these changes allow
about one 8086 clock period more set-up time for SACK.
A total of four packages (three 14-pin and one 16-pin)
of TTL logic are required.
The dynamic RAM interface timings are identical to the
last example (Equations I (a)-(h»; 2164A-20 RAMs will
be used again.
ADDRESS SET·UP AND HOLD TIME MARGINS
Let's look at this logic in more detail. An Intel 8205
(AS) is used to decode the 8086's status outputs S0-2' An
opcode fetch, memory read, or memory write decode to
8205 outputs 4,5, and 6, respectively. These outputs go
to the D inputs of two 74S74 flip-flops. The Q output of
flip-flop AIO.2 is'an advanced memory read signal and
the Q output of Al1.2 is an advanced memory write
signal. As shown in Figure 37, the 8203 is not activated
for opcode fetches, but it can be if 8205 outputs 4 and 5
are ORed with the unused 74SOO gate (A9.4) and the Q
output of AIO.2 used instead of Q. Both flip-flops are
clocked by the falling edge of ALE to generate the advanced commands. Flip-flop AIO.I is clocked by the
trailing edge of either AMWC (Advanced Memory
Write Command) or MRDC (Memory Read Command)
from the 8288 bus controller (A6), indicating that the
8086 has completed the memory cycle. AIO.I, in turn,
presets both the AIO.2 and All.2 flip-flops to terminate·
the advanced memory read and write signals to the
8202A. AIO.I is then preset to its initial state by ALE
going active at the start of the next bus cycle.
Because RAM write cycles are started very early in the
8086's bus cycle using this logic, the 8203 will activate
CAS to the RAMs (latching write data) before the data
is valid from the 8086. This requires delaying WE to the
RAMs and performing a "late write" (explained earlier
under Dynamic RAMs) in ()rder to allow more time for
the write data to arrive. But the WE signal must not be
Address set-up and hold time margins. are given in
Equations 10 and 11, respectively. An 8086-2
microprocessor has been used instead of the standard
8086, as this speed-selected part gives better address setup to RD or WR times, which this design needs since it
uSeS advanced RD and WR commands.
(Equation 10.)
Row Address Set-Up Time Margin[l)
CPU Address to Adv. RD Delay
+ RAS Delay - Address Delays
TCLCHmin(8284A) + TCHLLmin(8288)[21
+ tpLHmin(74S00)[31 + tpHLmin(74S74)[21
+ tCRmin(8203) - [Greater of
TCLAVmax(8086 - 2) + TIVOVmax(8282)
or TCLLHmax(8288) + TSHOVmax(8282»)
- tAomax(8203) - tAsRmin(2164A-20)
[¥3(200) - 15) + 2 + 1 + 2 + [(40) + 30)
- [Greater of (60 + 30) or (IS + 45») - 40 - 0
63
Read or write cycles only. Eq. Ib gives this timing
for refresh cycles.
[2) Not specified - use 2 ns.
[31 Not specified - use I ,ns.
[I)
6-33
AFN: O22OOA
Ap·97A
Address Hold Time Margin (N = 0)
(Equation 11.)
CPU Address Hold Time from Adv. RD
Active· RAS Inactive Delays
(3 + N)TCLCL(5MHz) + TCHCLmin(8284A)
+ TCLLHmhi (8288)
+ TSHOVmin(8282) • TCLMLmax(8288)
- tccmax(8203) - tRsHmax(8203)
(3)200 + [Y3(200) + 2] + 2 + 5 - 35
, - [4(40) + 85] - [5(40) + 20J
...., 175
READ DATA ACCESS TIME MARGIN
R,ead data access time margin is shown in Equation 12;
no wait states are required for read cycles, even with 200
ns access time RAMs.
Read Data Access Time
(Equation 12.)
Margin (N = 0)
Adv. RD to Data Valid Delay - CAS Delay
- Read Data Delays
(2 + N)TCLCL(5MHz) + TCHCLmin(8284A)
- TCHLLmax(8288) - tpLHmax(74S00)
- tpHLmax(74S74) - tccmax(8203)
- tCAcmax(2164A-20) - tpl1lax(74S373)
- TIVOVmax(8286) - TDVCLmin(8086-2)
(2)200 + [Y3(200) + 2] -' 15 - 5 - 10
- [4(40) + 85] - 110 - 30 - 30 ~ 20
3
WRITE DATA SET·UP AND HOLD TIME MARGINS
Write data set-up and hold times are shown in Equations 13 and 14, 'respectively. No wait states are required
during write cycles. Note that write data set-up has been
guaranteed by delaying WE from the 8203 with clocked
AMWC from the bus controller and performing "late
write" cycles; write data set-up time would not be
satisfied otherwise. Equation 15 verifies that WE has
not been delayed too long to meet the RAM's WE active
to RAS inactive set-up time (tRWU' The RAM's WE active to CAS inactive set-up time (tcwu is also satisfied,
since CAS does not go inactive until at least 20 ns after
RAS.
Write Data Set-Up Time Margin
(Equation 13.)
CPU Data to Clocked AMWC Set-Up
+ WE Delays - Data Delays
TCLCHmin(8284A) + tpHLmin(74S74)[IJ
+ (2)tpHLmin(74S32)[IJ
~
- TCLDVmax(8086-2) - TIVOVmax(8286)
" tDsmin(2164A-20)
[¥3(200) - 15] + 2 + (2)2 - 60 - 30,-0
34
Write Data Hold Time
(Equation 14.)
Margin (N = 0)
CPU Data Hold Time from Clocked AMWC
+ Data Delays - WE Delays
(2 + N)TCLCL(5MHz)
TCHDXmin(8086-2) + TIVOVmin(8286)- tpHLmax(74S74) - (2)tpHLmax(74S32)
- tOHmin(2164A-20)
(2)200 + 10 + 5 - 10 - (2)7 - 45
346
WE Active Set-Up Time Margin
(Equation 15.)
to RAS Inactive
TCHLLmin(8284A)[IJ + tpLHmin(74S00)[2J
+ tccmin(8203) + tRsHmin(8203)
- tSKEw(74S74)[3J -(2)tpHLmax(74S32)
- tRwLmin(2164A-20) - TCLCL(5MHz)
2 + 1 + [3(40) + 25] + [5(40) - 30]
- 2 - (2)7 - 50 - 200
52
SACK SET·UP TIME MARGIN
Equation 16 shows that SACK set-up time is satisfied;
no wait states will be generated for read or write cycles
(except for refresh).
SACK Set-Up Time Margin (N = 0)
(Equation 16.)
(1 + N)TCLCL(5MHz) - TCHLLmax(8288)
" tpLl.jmax(74S00) - tpHLmax(74S74)
- tCAmax(8203) - tsumin(74S74)
200 - 35- 5 - 10 [2(40) + 47] - 3
20
PJ Not specified - use 2 ns.
[2J Not specified - use 1 ns.
[3J tSKEw(74S74) is max. skew between
tpHL(Q output, from CLK) of two Q outputs in
same package - use = 2 ns.
'
AFN
02200~
A1819
A'6·'9
Al
8284A
ASYNC
"'I'"
>z
Ow
0:..:
>
A12 00'15
ADDRESS BUS
ADo·, 5
A2
8086·2
~I
w'
0:1
READY
~I
CLK
50.2
8205
06 9
1
0510
04
WE
8203
A13
OUT
CJ)
I
Ul
(]I
2~:A
I
DOUT
x
,,
,L________
L_
DOUT
DIN
DATA BUS
8286
Symbol 'to Indicates connection to Vee through 1K.I\-pull·up
---indicates additional Circuitry 10 zero walt states
,.
~
~
RAM
! - - - - -....-t!c'AS
ALE AMWC
Notes
WE
~
RASI,<
74S00
Figure 37. 8086 Alternate Configuration System
D'N
x
J>
'U
~
J>
AP·97A
pes Set-Up TIme Margin
=
(Equation 17.)
CPU Address Varid to Adv. iID or Adv.
Wi Delay Decode Time
TCLCHmin(8284A) + TCHLLmin(8288)[11
+ tpLHmin(74S00) + tpmmin(74S74)[11
- TCLAVmax(8086-2) - TIVOVmax(8282)
- tpmax(74S138[31 - tpcsmin(8203)
(%(200) - 1S] + 2 + 1 + 2 - 60 - 30 - 12 - 20
1
Pes
PCS SET·UP TIME MARGIN
PCS set-up time for the 8203 (tpcS> is satisfied. but not
with as much margin in the last example (Figure 17).
[II Not specified - use 2 ns.
(2) Not specified - use 1 ns.
(3) Must use 74S138 to maintain PCS Set-Up
Time Margin.
This is because the RD and WR commands are activa~
earlier in the microprocessor's bus cycle. leaving less
time to decode PCS from the address bus.
CONCLUSION
This design will operate with a guaranteed zero wait
states up to S MHz using slow (200 ns access time)
RAMs. At this frequency. it is limited by both read and
write data set-up times. and to a lesser extent, by SACK
set-up time. Using faster RAMs will not raise the maximum frequency, as write data and SACK set-up times
are not affected by the RAM speed. The 8203 operating
frequency must be 25 MHz.
This design can be used (with some modifications) to
allow one wait state performance up to 8086 clock frequency of 8 MHz.
6-36
AFN:022OOA
inter
Ap·141
APPLICATION
NOTE
,
6-37
'
October 1981
order number:2111316.001
8203/8206/2164A
Memory Design
Contents
ABSTRACT .................................... 1
DESiGN ...................................... 1
CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4
6-38
AFN02114A
Ap·141
ABSTRACT
DESIGN
This Application Note shows an error corrected
dynamic RAM memory design using the 8203 64K
Dynamic RAM Controller, 8206 Error Detection and
Correction Unit and 150 ns 64K Dynamic RAMs with a
minimum of additional logic.
Figure 1 shows a memory design using the 8206 with
Intel's 8203 64K Dynamic RAM Controller and 150 ns
64K Dynamic RAMs: As few as three additional ICs
complete the memory control function (Figure 2).
For simplicity, all memory cycles are implemented as
single-cycle read-modify-writes, shown in Figllre 3. This
cycle differs from a normal read or write primarily when
the dynamic RAM write enable (WE) is activated. In a
normal write cycle, WE is activated early in the cycle; in
a read cycle, WE is inactive. A read-modify-write cycle.
consists of two phases. In the first phase, WE is inactive, and data is read from the dynamic RAM; for the
second phase, WE is activated and the (modified) data is
written into the same word in the dynamic RAM.
Dynamic RAMs have separate data input and output
pins so that modified data may be written, even as the
original data is being read. Therefore data may be read
and written in only one memory cycle.
The goals of this design are to:
1. Control 128K words x 16 bits ·(256 KB) of 64K
dyna~c RAM.
2. Support 150 ns dynamic RAMs.
3. Write corrected data back into dynamic RAM when
errors are detected during read operations.
4. To use a minimum of additional logic.
It is not the goal of this design to:
1. Provide the maximum possible performance.
2. Provide features like error logging, automatic error
scrubbing and dynamic RAM initialization on
power-up, or diagnostics, although these features
can be added.
~
~
WR
Bo AH AL OUT r-----' A7'Ao
• •
~GH
RD
RASO
r RAS BYTE
WR 8203 RASl
RAS RAM
Cs
CS
iffi
r
CAS
CAS
r-c ~~
."'" ::,.
XACK
r
L-.c RO
_WR
CS
Ao
BHE
BMo
BM1
T
OEBO
OEBl
-< RAS BYTE
i~~A
DO
-c
RAS
-c CAS
-c ~~
DO
I~
-
~
@
INTERFACE
LOGIC
.~~
I OE T
8~86
A
-c W~CDL
...::
"<
01
p-
-<
RAM
RAS (12)
-< CAS 2164A
RAM
(16)
2184A
-<..1.
L~l_
f----l\ A7.Ao
:--II
CHECK
-< RAS BIT
- - " MAo
--y
LOW
~
STB
RIW
BMo
BM1
;:.-
i,
"<
>
;:.CBI
8206
CBO
MIS
WZ
~"'9
CRCT
DOIWOI
;:...
J
.
-=
~
10ET
8286 AI
B
.
I
\
'SYSTEM DATA BUS
Figure 1.' 820318206 Memory System
6-39
AFN02114A
inter
AP·141
In order to do read-modify-writes in one cycle, the
dynamic RAM's CAS strobe must be active long enough
for the 8206 to access data from the dynamic RAM, cor.rect it, and write the corrected data back into the
dynamic RAM. CAS active time is an 8203 spec (tCAS),
and is dependent on the 8203's clock frequency. The ./
clock frequency and dynamic RAM must be chosen to
satisfy Equation 1.
R/W is generated by delaying CAS from the 8203 with a
TTL-buffered delay line. This allows the 8206 sufficient
time to generate the syndrome; this delay, tDELAY I,
must satisfy Equation 2.
. ,
(Eq.2)
Dynamic
RAM
tDELAY I 2:
(Eq. 1)
Dynamic
RAM
8203
tcAsmin
2<
5(54)-10 2<
260
2<
tCAe
85
8206'
8206
Dynamic Dynamic
RAM
RAM
+TDVQV+ TQVQV +tos+
+
67
+
59
+ 0 +
tcwL
40
251
The 8203 itself performs normal reads and writes. In
order to perform read-modify-writes, all that is needed
is to change the timing of the WE signal. In this design,
WE is generated by the interface logic in Figure 2-the
8203 WE output is not used. All other dynamic RAM
control signals come from the 8203. A 20-ohm damping
resistor is used to reduce ringing of the WE signal. These
resistors are included on-chip for all 8203 outputs.
The interface logic generates the R/W input to the 8206.
This signal is high for read cycles and low for write
cycles. During a read-modify-write cycle, R/W is first
high, then low. The falling edge of R/W tells the 8206 to
latch its syndrome bits internally and generate corrected
check bits to be written to dynamic RAM. Corrected
data is already available from the DO pins. No control
signals at all are required to generate corrected data.
8203
tCAC
8206
+ TDVRL
150
2<
8S
+
150
2<
119
""
34
The 8206 uses multiplexed pins t~ output first the syndrome word and then check bits. This same R/W signal
may be used to latch the syndrome word externally for
error logging. The 8206 also supplies two useful error
signals. ERROR signals the presence of an error in the
data or check bits. CE tells if the error is correctable
(single bit in error) or uncorrectable (multiple bits in
error).
'
In the event that an uncorrectable error is detected, the
8206 will force the Correctable Error (CE) flag low; this
may be used as an interrupt to the CPU to halt execution and/or perform an error service routine. In this
case the 8206 outputs data and check bits just as they
were read, so that the data in the dynamic RAM is left
unaltered, and may be inspected later.
After R/W goes low, sufficient time is allowed for the
8206 to generate corrected check bits, then the interface
logic activl/-tes WE to write both corrected data and
check bits into dynamic RAM. WE is generated by
delaying CAS from the 8203 with the same delay line
TTL
DELAY LINE
CAS
' -____2"'0"'0_ WE
RAM
R/W] ARRAY
SYSTEM {
ADDRESS
BUS
Ao
BMo
BHE-+------------~_r--~-'
DEL~~~
cgYSTET
NT:~S {
cs---,---........-,
~~~TROL
BM,
-]
WR
Rii -;-_-q,_
'-------------------:T:::
~~~TROL
Figure 2. Interface Logic
.6-40
AFN02114A
intJ
Ap·141
A~~~
:><:~
ROW
\~
___
C_O_LU_M_N__-J:><:~
__________________________________
_ _ _ _ _----II
\'---_ _ _----'1
\'-----11
00- -
-
-
-
-
-
-
<
X
01
)-
VALID
VALID
x__
Frgure 3. Single·Cycle Read·Modlfy·Wrlte
used to generate RlW. This delay, tOELAY 2, must be
long enough to allow the 8206 to generate valid check
bits, but not so long that the tcwL spec of the RAM is
violated. This is expressed by Equation 3.
whole word plus check bits into dynamic RAM. A byte
write is implemented as a Read-Modify-Write.
Why bother with error correction on the old word? Suppose a bit error had occurred in the half of the old word
not to be changed. This old byte would be combined
with the new byte, and new check bits would be generated for the whole word, including the bit in error. So
the,bit error now becomes "legitimate"; no error will be
detected when this word is read, and the system will
crash. You can see why it is important to eliminate this
bit error before new check bits are generated. Byte
writes are difficult with most EDC chips, but easy with
the 8206.
(Eq.3)
Dynamic
1IlO3
8206
tDELAY I
150
+ TRVSV"
+
42
"
192
~
tDELAY 2 "
RAM
tCASmin -
200
~
260
200
~
220
tcwL
-
40
"
Unlike other EDC chips, errors in both data and check
bits are automatically corrected, without programming
the chip to a special mode.
~ince the' 8203 terminates CAS to the dynamic RAMs a
fixed length of time after the start of a memory cycle, a
latch is usually needed to maintain data on th~ bus until
the 8086 completes the read cycle. This is conveniently
done by connecting XACK from the 8203 to the STB input of the 8206. This latches the read data and check
bits using the 8206's internal1atches.
Referring again to Figure 2, the 8206 byte mark inputs
(BMo, BMI), are generated from AO and BHE, respectively, of the 8086's address bus, to tell the 8206 which
byte is being written. The 8206 performs error correction on the entire word to be modified, but tri-states its
DO/WDI pins for the byte to be written; this byte is
provided from the data bus by enabling the corresponding 8286 transceiver. The 8206 then generates check
bits for the new word.
The 8086, like all 16-bit microprocessors, is capable of
reading and writing single byte data to memory. Since
the Hamming code works only on entire words, if you
want to write one byte of the word, you have to read the
entire word to be modified, do error correction on it,
merge the new byte into the old word inside the 8206,
generate check bits for the new word, and write the
During a read cycle, BMo and BMI are forced inactive,
i.e., the 8206 outputs both bytes even if 8086 is only
reading one. This is done since all cycles are implemented as read-modify-writes, so both bytes sf data
(plus check bits) must be present at the dynamic RAM
data input pins to be rewritten during the second phase
of the read-modify-write. Only those bytes actually be6-41
AFN02114A
Ap·141
ing read by the 8086 are dtiven on the data bus by enabling the corresponding 8286 transceiver.
The output enables of the 8286 transceivers (OEBO,
OEBl) are qualified by the 8086 RD, WR commands
and the 8203 CS. This serves two purposes:
1. It prevents data bus contention during read cycles.
2. It prevents contention between the transceivers and
the 8206 DO pins at the beginning of a write cycle.
CONCLUSION
Thanks to the use of a 68-pin package, the 8206 Error
Detection and Correction Unit is. able to implement an
architecture with separate 16 pin input and output
busses. The resulting simplification of control requirements allows etror correction to be easily added to an
8203 memory subsystem with a minimal amount of
interface logic.
6-42
AFN02114A
inter
APPLICATION
NOTE .
AP-167
August 1983
©Intel Corporation, 1983. '
ORDER NUMBER: 230809-001
NOVEMBER 1983
6-43
AP-167
This Application Note will illustrate an iAPX design
with the 8207 controlling the dynamic RAM array. The
reader should be familiar with the 8207 data sheet, the
80186 data sheet, and a RAM data sheet·.
INTRODUCTION
Most microprocessor based workstation designs today' use large amounts of DRAM for program storage.
A drawback to DRAMs is the many critical timings
that must be met. This control function could easily
equal the area of the DRAM array if implemented with
discrete logic.
DESIGN GOALS
The main objective of this design is for the 80186 to
run with no wait states with a Dynamic RAM array.
The design uses one port of the 8207. The dual port
and error correcting interfaces of the 8207 are covered
in separate Application Notes.
The VLSI 8207 Advanced Dynamic RAM Controller
(ADRC) performs complete DRAM timing and control. This includes the normal RAM 8 warm-up cycles,
various refresh cycles and frequencies, address
mUltiplexing, and address strobe timings. The 8207's
system interface and RAM timing and control are programmable to permit it to be used in most
applications.
The size of the RAM array is 4 banks of 64k RAMs
or 512k bytes. The memory is to be interfaced locally
to the 80186.
Integrating all of the above functions (plus a dual port
and error correcting interfaces) allows the user to
realize significant cost savings over discrete logic. For
example, comparing the 8207 to the iSBCO 12B 512K
byte RAM board (where the DRAM control is done
entirely with TTL), an 8207 design saved board space
(3 in 2 vs 10 in2); required less power (420 rna vs
1220 rna); and generated less heat. Moreover, design
time was reduced, and increased margins were achieved due to less skewing of critical timings. This
comparison is based on a single port design and did
not include the 8207's RAM warm-up, dual-port and
error correcting features. If these features were fulJy
implemented, there would be no change to the 8207
figures, listed above, while the TTL figures would easily double.
SYSTEM \.
USING THE 8207
The three areas to be considered when designing in
the 8207 are:
•
•
•
8207 programming logic
Microprocessor interface
RAM array
8207 Programming
The 8207 requires up to two 74LS165 shift registers
for programming. This design needs one 8 bit shift
register, as shown in Figure I. The 16 bits in the Program Data Word are set as shown in Figure 2. Refresh
is done internally, so the REFRQ input must be tied
high. The memory commands are iAPX 86 status, so
,----------,, - - - - - - - - ,
I
r------i~
I
I
Y
:
I
lOAD
RESET/i·
I
l
I
II
QH
G
H
~... t t t
*:
lOAD
I
ClK
PUSO SHIFT REG
!!
PClKlMUX
I
L..J--t--r.TA IN
I
RESET
~
i..L
rv
SERIAL
A
8207
ClK
PUSO SHIFT REG.
B
DATA IN
G
QH H
t t t..~ t t t
-+!--"1:----.1-:-1;-....._·-_ I !
-=~"""·~~l-"'"
POlS
PD8
I
L__ ~T~~
:
PO I
.
JUMPER OPTIONS
Po7·PD~
I
____
J
Figure 1. 8207 programming shift registers
-All R'AM references in this Application Note are based on Intel's 2164A 64k Dynamic RAM.
6-44
230809-{J01
inter
AP-167
+5
74830
SRDyCLK
il---~I-'---+--t
80186
S°t-"""",,;::::;~~:::;--T--1
ALE
ADDRESS
BUS
DATA
BUS
NOTE: THE 8207 REQUIRES SERIES RESISTORS ON ALL 'OUTPUTS TO RAM.
Figure 3. 80186 to 8207, non-ECC, synchronous system single port.
based upon the' CAS access period minus buffer,
..
clock, setup requirements.
the timing of EAACK will always guarantee 2 clocks
of address hold time from RAS.
Acknowledge Setup Time
2 TCLCL - 8207 TCLCSL @ 150 pf (t34) DRAM tCAC - 74S24O propagation delay @
50 pf - additional bus loading delay
(250 pf)(l) - 74S24O delay @ 50 pf :.. 801~6
TDVCL ~ 0
.
The margin between the 8207 issuing BAACK and the
80186 ready input for no wait states minus delays from
clock edges, logic delays, and setup time is calculated
as follows.
1 clock - 8207 TCLAKL max -74S30 tPLH @
15 pf - 80186 TSRYCL ~ 0
250 ns - 122 - 85 - 7 - 7 - 7 - 20
= 2 ns
Write Data Setup and Hold Margin
Data from the processor must be valid when WE
is issued by the 8207 to meet the RAM specification tDS (2164A = 0 ns), and then held for a
minimum of 30 ns ..
(1) 74STTL logic derated by .05 ns/pf. 74STTL
buffers (240, 37) derated by .025 ns/pf.
125 ns - 35 - 22 - 35 = 33 ns
Read' Access Margin
The 8207 start~ a 'memory cycle on the f;Uling clock
edge between the 80186's Tl and T2. Data must be
valid within 2 clocks. Valid data from the RAMs is
6-45
230809-001
inter
AP-167
o
I0
0
00000000
,~1~5____________________8~1
000
_____________________0~1
~17
Figure 2. Program data word
the PCTLA input must be high when RESET goes
inactive.
The command timing is determined by the period'between the status being issued and the first rising clock
edge of the 8207, minus setup and delays.
The differential reset circuit shown in the Data Sheet
is necessary only to ensure that memory commands
are not received by the 8267 when Port A is changed
from synchronous to asynchronous (vice versa for
Port B). This design keeps Port A synchronous so no
differential reset circuit is needed.
Microprocessor Interface
To achieve no wait states, the 8207 must connect
directly to the microprocessor's CLKOUT and status
lines. The 8207 Acknowledge (BAACK) must connect
to the SRDY input ohhe 80186.
80 186 status valid to 8207 rising clock :- status from
clock delay - 8207 'setup to clock ;;. 0
1 TCLCL - 80186 TCHSV max - 8207 TKVCH
min;;' 0
125 ns - 55 - 20 '" 50 ns
PE is a chip select for a valid address range. It can
,be generated from the address bus or from the 80186's
programmable memory selects. This design uses an
inverted A19. The timing is determined by the interval between the address becoming valid and the falling clock edge, minus setup and delays.
When the 80186 is reset, it tristates the status lines.
The 8207 PCTLA input requires a high to decode the
proper memory commands. This is !lccomplished by
using a pull-up resistor or some component that
incorporates a pull-up on S2.
,
. The 8207 address inputs are connected directly to the
latched!demultiplexed address bus.
80186 address valid to 8207 falling clock ed!e
- 80186 address from clock delay - 8283 latch
delays - 8207 PE setup ;;. 0
1 TCLCL - 80186 TCLAV max - 8283 IVOV @
300 pf - 8207 TPEVCL ;;. 0
125 ns - 44 - 22 - 30 '" 29 ns
The hold times are 0 ns and are met.
RAM Array
Address Setup
The 8207 provides complete control of all RAM timings, warm up cycles, and refresh cycles. All write
cycles are "late writes." During write cycles, the data
out lines go active. This requires separate data in!out
lines in the RAM array.
'
For an 80186 design, the 8207 requires the address to
be stable before RAS goes active, and to remain stable
for 2 clocks. Unused 8207 address inputs should be
tied to Vcc.
tASR is a RAM specification. If it is greater than zero,
this must be added to the address setup time of the
8207. Address setup is the interval between addresses
being issued and, RAS going active, minus appropriate
delays.
To ,operate the 80186 with no wait states, it is necessary
to chose sufficiently fast DRAMs. The 150 ns version
of the 2164A allows operating the 80186 at 8 MHz,
and the 200 ns version up to 7 MHz.
HARDWARE DESIGN
80186 address valid to 8207 RAS active .:
80186 address from clock delay - bus delays (8207 setup + RAM t ASR) ;;. 0
TCLCL + 8207 TCLRSL min @ 150 pr( 1) 80186 TCLAV max - 8283 IVOV max @ 300 pf
-(8207 TAVCL min + DRAM tASR);;' 0
Figure 3 shows a block diagram of the design, and
Figure 4 is a timing diagram showing the relationship
between the 8207 and the 80186.
8207 Command Setup
Two events'must occur for a command to be recognized by the 8207. The 80186 status outputs are sampled by a rising clock edge and Port Enable (PE) is
sampled by the next falling clock edge (refer to the
Data Sheet wave forms).
125 ns + 0 - 44 - 22 - (35 + 0) '" 24 ns
, The address hold time of 2 clocks + 0 ns is always'
met, since the addresses are latched by the 828213.
Even when the processor is in w.iit states (for refresh),
(1) Not specified-use 0 ns. '
6-46
230809-001
AP-167
TCLCL + TCLCH + 8207 TCLW min(l) +
74S'37'delay tPHL min @ 50 pf + additional
loading (142 pf) - 80186 TCVCTV 74S24OtPZL - bus delays (250 pf) - 74S240 .
delay - 2164A tDS ~ 0
62.5 ns + 10 + 2 + 3 + 7 + 3.5 - 35 3.5 - 30 = 19.5 ns
All margins are actually better by about 10-20 ns. No
improvement in timing was allowed for lower
capacitive loads when additional buffers are used (i.e.
the 80186 address out delay is at 200 pf, but the 8283
latch only loads these lines with about 20 pf).
125 + 62.5 + 0 + 6.5 + 3.5 - 70 - 15 - 7 - 7 -
o = 98.5 ns
The hold time,tDH, is from WE going low to the
80186 DEN going high plus buffer delays minus
WE from clock delays.
SUMMARY
TCLCL - 80186 TCVCTX min + 74S32
tPD(2) min + 74S24O tPHZ (min)(2) + 250 pf
bus delays + 74S240 propagation delay min 8207 TCLW max - 74S37 tPHL @ 50 pf 142 pf loading delays - DRAM tDH ~ 0
The 8707 supports the 80186 microprocessor running with no wait states. The 8207 interfaces easily between the microprocessor and dynamic RAM.
There are no difficult timings to be resolved by
the designer using external logic.
8 MHz
ALE
SO-S2
8207 RASO
8207
AAs1
8207"CASO
8207 CAS1
+_.....
8207 WE _ _ _
8207 EAACK _ _...J
80186 (SRDY)
WRITE
CYCLE
REFRESH
CYCLE
READ
CYCLE
READ CYCLE
NOTES:
1. COMMAND SETUP MARGIN
2. PE SETUP MARGIN
3. EAACK SETUP MARGIN
4. DATA SETUP MARGIN
5. READ ACCESS MARGIN
Figure 4. 8207/80186 timing relationship
(1) Not specified, use 0 ns.
(2) Not specified, use one half of typical value.
6-47
230809-001
intJ
APPLICAliON
NOTE'"
AP~1,68
August 1983
ORDER NUMBER: 230862-001
©Intel Corporation, 1983.
NOVEMBER 1983
6-48
inter
AP·l68
INTRODUCTION
8207 INT~RFACE
The 80286 high speed microprocessor pushes
microprocessor based systems to new performance
levels. However, its high speed bus requires special
design considerations to utilize that performance. Interfacing the 80286 to a dynamic RAM array require
many timings to be analyzed, refresh cycle effects on
bus timing examined, minimum and maximum signal
widths noted, and the list continues.
.
The 8207 ~emory design can be subdivided into three
sections:
The 8207 Advanced Dynamic RAM Controller was
specifically designed to solve all interfacing issues for
the 80286, provide complete control and timing for
the DRAM array, plus achieve optimum system performance. This includes the normal RAM 8 warmup cycles, various refresh cycles and frequencies, address multiplexing, and address strobe timings. The
8207 Dynamic RAM Controllj:r's system interface and
RAM timing and control are programmable to permit it to be used in most applications.
Integrating these functions (plus dual port and error
correcting interfaces) allows the user to realize significant savings in both engineering design time, PC board
space and product cost. For example, in comparipg
the 8207 to the ISBCOl2B 512k byte RAM board
(where the DRAM timing and control is done entirely with TTL), the 8207 design saved board space (3 in2
vs 10 in2); used less power (420 ma vs 1220 ma);
reduced the design time; and increased margins due
to less skewing of timings. The comparison is based
upon a single port 8207 design and does not include
its RAM warm-up, dual port, error correcting, and
error scrubbing or RAM interleaving features.
• Programming the 8207.
• The 80286/8207 interface.
• The Dynamic RAM array.
Programming the 8207
The RAM timing is configured via the 16 bit program
word that the 8207 shifts-in when reset. This can require two 74LS165 shift registers to provide complete
DRAM configurability. The 8207 defaults to the configuration shown in Table 1 when POI is connected
to ground. This design does not need the flexibility
the shift registers would allow since standard
8207/80286 clock frequencies, DRAM speeds and
refresh rates are used. Table 1 details the 8207/80286
configuration and Table 10 in the Data Sheet identifies "CO" as the configuration of the 8207 all timings will be referenced to (80286 mode at 16 MHz using fast RAMs = CO).
Table 1. Default Non·ECC programming, POl
pin (57) tied to ground.
Port A is Synchronous (EAACKA and XACKA)
Port B is Asynchronous (LAACKB and XACKB)
Fast-cycle Processor Interface (10 or 16 MHz)
Fast RAM 100/120 ns RAM
Refresh Interval uses 236 clocks
128 Row refresh in 2 ms; 256 Row refresh in
4 ms
This Application Note will detail an 80286 and 8207
dl=Sign. The 'reader should have read the 8207 and the
80286 data sheets, a DRAM data sheet·, and have them
available for reference.
Fast Processor Clock Frequency (16 MHz)
"Most Recently Used" Priority Scheme
4 RAM banks occupied
DESIGN GOALS
The main objective of this design is to run the RAM
array without wait states, to maximize the 80286's performance, and to use as little board space as possible. The 80286 will interface synchronously to Port
A of the 8207 and the 8207 will control 512k bytes
of RAM (4 baJlks using 64k DRAMs). The dual port
and error correcting features of the 8207 are covered
in separate Application Notes.
The 8207 will accept 80286 status inputs when the
PCTLA pin is sampled low at reset. This pin is not
necessary for an 80286 design (besides programming)
and is tied to ground.
Refresh is the final option to be programmed. If the
Refresh pin is sampled high at reset, an internal timer
"All RAM references In Ihis Application Note are based upon Inlel"s CMOS 51C64-12 64k Dynamic RAM. Any DRAM wilh simHar limings will function. Reier Ie section 4.4.
\
6-49
230662-001
intJ
AP·168
is enabled, and if low at reset, this timer is disabled.
The first method is the easiest to implement, so the
RFRQ pin is tied to Vcc.
The differential reset circuit shown in the Data Sheet
is necessary only to ensure that memory commands
are not received by the 8207 when Port A is changed
from synchronous to asynchronous (vice versa for
Port B). This design keeps Port A synchronous so no
differential reset circuit is needed.
start. LEN will then go high two clocks after RAS
starts, since addresses are no longer needed for the
current RAM cycle. Thus the low period of LEN could
be much longer than listed in the Data Sheet.
DESIGNING THE H,ARDWARE
Figure 1 shows a detailed block diagram of the design
and Figure 2 shows the timing relationship between
the 8207 and the 80286.
The following analysis of six parameters will confirm
that the design will work. These six system parameters
are generally considered the most important in any
microprocessor-Dynamic RAM design.
RAM Array
The 8207 completely controls all RAM timings, warmup cycles, and refresh cycles. To determine if a par-,
ticular RAM will work with the 8207, calculate the
margins provided by the 8207 (Table 15, 16-8207
Data Sheet) and ensure they are greater than the RAM
requirement. An additional consideration is the access times of the RAMs. The access time of the system
is dependent upon the number of data buffers between
the 80286 and the DRAMs. To operate the 80286 at
zero wait states requires access times of 100-120 ns.
Slower RAMs can be used (150 ns) by either adding
a wait state (programming the 8207 for "Cl ") or
reducing the clock frequency (to 14.9 MHz approximatelyand maintaining the CO configuration.)
All write cycles are "late writes" and the data out lines
of the RAM will go active. This will require separate
data in and out lines in the RAM array. Another consideration for the RAM array is the proper layout of
the RAM, and impedance matching resistors on the
8207 outputs. Proper layout is covered in Intel's RAM
Data Sheets and Application Notes.
Microprocessor Array
To achieve no wait state operation, the 8207's clock
input must be connected to the 80286' s clock input.
The EAACK (early acknowledge) output of the 8207
must connect to the SRDY input of the 82284. The
8207' s address inputs connect directly to the 80286
address outputs and the addresses are latched internally. This latch is strobed by an ,internal signal with
the same timing as LEN (which is for dual port 80286
designs). Figure 2 shows the timing relationship between LEN and the 80286.
8207 Command Setup Margin
Two events must occur for the 8207 to start a memory
cycle. Either RD orWR active (low) andPE must be
low when the 8207 samples these pins on a falling clock
edge. If PE is not valid at the same clock edge that
samples RD or WR active, the memory cycle will be
aborted and no acknowledge will be issed.
The command setup time is based upon the status being valid at the first falling clock edge.
80286 status valid to 8207 falhng ,clock 80286 status from clock delay - 8207
command setup to ciock ,.; 0
TCLCL - 80286 t12 (max) - 8207 TKVCL
(min) ,.; 0
62.5 - 40ns - 20ns = 2.5ns
PE is decoded from the address bus and must be set
up to the same falling clock edge that recognizes the
RD, WR inputs. This margin is determined from the
clock edge that issues the address and the clock edge
that will recognize RD or WR, minu,s decoding logic
delays.
There are 2 clocks between addresses being iss]led by
the 80286 and PE being sampled by the 8207. Then
the 80286 address delay from the clock edge' and
decoding logic delays are subtracted from this interval. This margin must be greater than O.
2TCLCL - 80286 t13 (max) - 8207 TPEVCL
(min) ,.; 0
125 - 60 - 30 = 35ns
The address decode logic must use no more than 35 ns
(and less is better). Figure 3 shows an easy implementation which uses a maximum of 12 ns.
LEN will fall from high to low, which latches the bus
address internitlly; when a valid command is received. LEN can go high in two clock cycles if the RAM
cycle started (RAS going low) at the same time LEN
went low. If the 8207 is doing a refresh cycle, the 80286
will be put into wait states until the memo'ry cycle can
The 8207 requires a zero ns hold tim!! and is always
met.
6-50
230862-001
inter
AP-168
82284
r--------;~
\
SR5Vt--------------,
CLK
•
CLK
ALE
+-----..,
82288 DE,-,!_
OM
DT/R
I
+5
t--:-l~~~
....c
LK
AACK
ADD"'R.J:==::::~
MilO S1' SO
FiEADv CL~
Y
MilO - - l
S1
!AFRQ STROBE':
PCTL.
PDI ~
- RD 8207 WE
V
.,z:;V
SO
..
r-
WR
PSEN
ADDR IN LEN
80286
MEMORY
(UPPER)
WE
01
MEMORY
(LOWER)
DO
WE
DI
DO
DA~:DRt=====;-;::::~~;::!::====::Jr" ~ ~_~==~!~if~
J
...----1 -
r--~=tJ ~o
L..-..;;.;"..;...,..-_
...._ _ _---i
AO
Q
r-_':.~+--'B;;.;.H-E_~D
Q
-
k
y
ST8
'+---40
-AACK
7474
BO
~
~
OE
I
74S240
1
T
OE
8287
L-r""l>I '--"-
STB
OE
8283
OE
{t
{}
DATA
ADDR
ACCK
DBM
~
...
74S240
NOTE: THE 8207 REQUIRES SERIES RESISTORS'ON ALL OUTPUTS.
Figure 1. 80286 to 8207, non-ECC, Synchronous System Single Port
,
6-51
230862-001
intJ
AP-168
Ts
Te-
I
I
Te
I
T1
Ts
I
I
Te
I
Te
Te
I
16 MHz
CLOCK
SO-S1
60286
ADDR.
LEN
RASa
RAS1
CAsO
CAs1
DRAM
WE
J
EAACK
Figure 2. 80286/8207 Timing-utO".
+5
74S04
A23
A22
8207
PE
A21
74830
A20
A19
Figure 3. Address Decode Logic
6-52
230862-001
inter
AP-168
Address Setup Margin
Acknowledge Setup Margin
The 8207 must have stable addresses up to two clocks
after RAS goes active. This is of no concern to the
user, since LEN latches the address internally and will
not admit a new address until two clocks after RAS
goes active.
The 8207 acknowledge (EAACK) can be issued at any
point in the 80286 bus cycle (end of ,1 or ,2 of Ts
or Tc). If EAACK is issued at the end of ,2 (Ts or
Tc), the 80286 will complete the current bus cycle. If
EAACK is issued at the end of'l of Tc, the 82284
will not generate READY to the 80286 in time to end
the current bus cycle. A' new Tc would then be
generated and EAACK would now be sampled in time
to terminate the bus cycle. EAACK is 3 clocks long
in order to meet setup and hold times for either
condition.
Addresses must be stable at least 35 ns (tAVCL) before
RAS goes active to allow for propagation delays
through the 8207, if a RAM cycle is not delayed by
the 8207.
tASR is a RAM specification. If it is greater than zero,
tASR must be added to the address setup time of the
8207. Address setup is the interval between addresses
being issued, by the 80286, and RAS going active,
minus appropriate delays.
We need the margin between the 8207 issuing EAACK
and the 82284 needing it. Figure 4, shows a worst case
example.
TCLCL - 8207 TCLAKL max - 82284 tIl
62.5 - 35 -' 15 = 12.5ns
The margin is determined from the number of clocks
between addresses being issued from the 80286 to RAS
going active. Exactly when RAS goes active is unimportant, since here we are interested only in the clock
edge.
2TCLCL - 80286 tl3 (max) - 8207 TAVCL
(min) ~ 0
125 - 60ns - 35ns = 35ns
~
0
Read Access Margin
The 8207 will typiCally start a memory cycle (Le. RAS
goes low) at the end of ,1 of Ts. But if the start of
a memory cycle is delayed (by a refresh cycle for instance), then RAS will be delayed. In the first case,
Figure 4. Acknowledge to the 82284
6-53
230862-001
inter
AP-168
this represents 3 clocks and the second case could require 4 clocks to meet th~ data setup requirements of
the 80286. In either case, data must be valid at the
end of Tc. The 820.7 holds CAS active long enough
to ensure valid data is received by the 80286 in eith~r
case.
So any DRAM that has a RAS access period less than
135 ns, a CAS access period less than 73 ns, and meets
all requirements in the DRAM InterfaCe Timing (Table
15, 16-8207 Data Sheet), 'YiJI work ..
DRAMs specify two access times, RAS access (tRAC)
and CAS access (tCAC) Both access periods must be
calculated and the one with the least margin used. Also
the number of data buffers should be kept to a
minimum. Too many buffers would require either
faster (more expensive) DRAMs, or a reduction in the
performance of the CPU (by adding wait states).
Write data from the processor must be valid when the
8207 issues WE to meet the DRAM specification tDS
and then held to meet the tDH requirement. Some
write cycles will be byte writes and the information
I to determine which byte is decoded from AO and
BHE/. Since the 80286' s address bus is pipelined, these
two signals can change before the RAM cycle starts,
hence they must be latched by LEN. PSEN is used
in the WE term to shorten the WE pulse. Its use is
not essential.
.
\
RAS Access Margin
Write Data Setup and Hold Margin
Data must be set up to the falling edge of WE, since
WE occurs after CAS. The 2 clocks between valid
write data and WE going active (at the RAM's) minus
propagation delays determines the margin.
3TCLCL - 8207 TCLRSL max @ 150 pf DRAM tRAC - 74S240 propagation delay max
@ 50 pf - 80286 t8 ~ 0
187.5 - 35 - 120 - 7 - 10 = 15.5ns
2 TCLCL - 80286 t14 (max) @ 100 pf .;..
74S24O tplh + 8207 TCLW (min)l + 74S10 tphl @
192 pf2 - DRAM tDS = 0
CAS Access Margin
2TCLCL - 8207 TCLCSL max @ 150 pf - DRAM .
tCAA (or tCAC - 74S240 tplh max @ 50 pf 80286 t8 ~ 0
125 - 35 - 60 - 7 - 10
= 13ns
125 - 50 - 7
+ 0 + 14 -
0 = 82ns
The timing of the 8207's acknowledge is such that data
. will be kept valid by the 80286, for more than two
clocks after WE goes active. This easily meets all RAM
tDH specifications.
By solving each equation for tRAC and tCAC, the
speed requirement of the RAM can be determined.
SUMMARY
The 8207 c0rr4>lements the 80286's performance and
high integration with its own performance, integration and ease of use. No critical timings or lOgic design
has been left to the designer. The 80286/8207 combination allows users to realize maximum performance
from their simpler design.
DRAM tRAC = 3,TCLCL - 8207 TCLRSL 74S240 tplh - 80286 t8 = 135.5ns
DRAM tCAC = 2 TCLCL - 8207 TCLCSL 74S240 tplh - 80286 t8 = 73ns
no
1. Not specified. Assume
delay for worst case analysis.
2. STIL derated by .05ns/pf.
6-54
230862-001
AR-231
ARTICLE·
REPRINT
October 1982
"Reprmted from ELECTRONICS, Sept. 8, 1982 Copynght(c) McGraw-HIli, Inc. 1982 All fights reserved"
/
OCTOBER 1982
ORDER NUMBER: 210758-001
6-55
AR-231
Dynamic-RAM controller
orchestrates memory systems
Up to 88 chips take their cues from an n-channel MOS Ie
that both housekeeps and supports error-corrected dual-port memories
by Jim Nadir and Mel Bazes,
Intel Corp, Sants Clara,
cant.
o
Designing a dynamic-random-access-memory system data is available or no 10\lger needed. But, beyond those
means balancing the goals of high performance, reliabili- local housekeeping chores, the controller can also go a
ty, and versatility against the often contrary aims of long way to solving more global design problems, like
economy, simplicity, and compactness, In the last five or sharing memory between two processors, not to mention
so years, the advent of dynamic-RAM controller chips detecting and correcting errors.
reiieved designers of some of the onus of tending to the
To realize this potential for a highly integrated soluneeds of dynamic chips: standard supportive integrated tion, the 8207 has a dual-port interface and, when used
circuits brought together the counters, timers, multiplex- with the 8206 error-checking and -correction unit,
ensures data integrity in large dynamiC-RAM systems. In
ers, and other elements needed.
But controllers diverged into two types. One bought addition to doing the jobs of refreshing, address multithe high performance to ride with fast memory systems plexing, and control timing, the unit supports memoryat the expense df functionality, while the other took on bank interleaving for pipelined accesses, overlaying RAM
more and more functions to 'do 'a complete but slower and read-only-memory locations, and initializing RAM.
job. The 8207-an ~dvanced dynamiC-RAM controllerThe exact implementation of most of these functions is
blunts the horns of that dilemma and also solves a programmable, letting designers tailor their systems in
variety of less severe design problems.
detail. Systems containing up to 88 dynamiC-RAM
A dynamic-RAM controller is charged with making Ii chips-whether 16-,64-, or 256-K versions-in one, two,
dynamic memory system appear.-'static to the -host pro- 'or four banks need only a single 8207 and no external
cessor. At a minimum, therefore, the controller takes buffering. Attesting to the high performance claimed,
over refreshing the memory chips, multiplexing 'the row the 8207 mates dynamic RAMs having 100-nanosecond
and column addresses, generating control signals, timing access times to the iAPX-286 processor operating at 8
the precharge period, and signaling the processor when - megahertz without introducing any wait states.
DYNAMIC
RANDOM'ACCESS
MEMORY
8207
DYNAMIC·
'RAM
CONTROLLER
PROCESSOR
VIDEO'DISPLAY . . . . . . .
CONTROllER II
DATA
TABLE
WORKING
REGISTERS
. . . . . . . . DISPLAY
6-56
1. Window on .. mlcl'/l. One ~se for a dualport memory shared by Independent processors is the development system shown. Add,ng a video display to the prototype itself
gives a window on the system memory.
AFN-02236A
intJ
AR·231
To achieve that speed and include all those functions,
the 8207 'relies on a dense, high-speed n-channel MOS
process (H-MOS II) and requires a chip some 230 by 200
mils in area. To meet the rigors of operation with even
faster processors, novel logic and integrated-circuit
designs are employed. Replacing the two-phase logic
common in n-MOS les, single-phase edge-triggered logic
simplifies logic and circuit design, precludes problems of
clock-pulse overlap, and reduces the sensitivity to clock
high and low times. Voltage-controlled capacitive loads
form the delay elements that time critical output pulses,
such as the address strobes, and compensate the outputswitching delays for variations in power-supply voltage,
temperature, and processing.
A low 20-ns setup time for input signals is achieved by
cutting the RC delay of input-protection devices and
moving the TTL-tO-MOS signal buffering from the input
pads to the pulse generators. A short 35-ns delay from
input to output switching is achieved by triggering the
output generators directly from the external clock, saving a buffer delay time. With the resulting high-speed
performance and a high level of integration, the 8207
successfully attacks the stringent requirements of today's
memory systems.
One system feature gaining popularity currently is the
use of multiple processors operating on shared data to
obtain higher performances and reliability. For example,
a separate processor dedicated to input/output tasks
frees the main processor for full-time data processing.
Alternatively, multiple main processors can execute different tasks simultaneously. In all such cases, sharing a
common memory space among the cooperating processors is the key to effective operation.
Unfortunately, when more than one processor accesses
shared memory through a single bus, the limited bus
bandwidth and the time spent in exchanging bus control
slow down, data transfers. Dual-port memory systems
overcome this limitation by giving two processors access
to a common memory through two independent buses.
The 8207 includes a dual-port interface to simplify the
design of shared memory systems.
Two-port memories can be used with multiprocessing
or multitasking architectures. In the former, independent processors run independent programs, sharing only
a common memory. Multitasking processors cooperate
on different parts of the same task.
~n example of a multiprocessing architecture is the
dynamic video display (Fig. I) that provides a window
on a processor's memory. Centering the display over a,
data table, for example, immediately reveals how program execution affects the data, which aids in debugging
programs. If a microcomputer is implemented with a
dual-port memory-the second port for a dynamic video
display-then the prototype itself cart serve as a development and debugging system, reverting to single-port
operation in the final version.
A dual-port architecture in a multitasking environment, on the other hand, adds a margin of safety to a
shared-resource bus, such as Intel's Multibus. Although
one of the biggest benefits of such a bus is the sharing of
expensive peripherals among several users' programs, an
intimidating problem is that a single program gone haywire can easily cor",pt the entire system. A two-port
memory, properly configured, circumvents this occurrence. Because each port has its own address, data, and
control lines, problems on one side are confined by
hardware to that side.
Portoleall
As, a general rule for multitasking architectures, one
port of a two-port memory operates in a local environment, and the other port runs remotely, off the expandable shared-resource bus. The local processor is likely to
require a synchronous port to reap the benefit of higher
performance. Remote buses, in contrast, are usually
configured asynchronously. Unless programmed other-
Dynamlc,-RAM controllers get In step
Synchronous and asynchronous signals have' different
requirements for Interfacing with a controller. The terms
synchronous and asynchronous are cpnventionally applied to dynamic random-access memory depending on
whether it exists in a local or a remote environment,
respectively. However, they more properly characterize
the dynamic-RAM controllers, for the RAMs themselves
need no clocks - the only restrictions as to the start of a
memory access cycle involve ensuring that the refresh and
, precharge requirements are satisfied.
,
Because the controller decides both when to refresh
and whether or not precharge and other timing requirements have been met, it does need a clock. Incoming,
commands ,can either always arrive with a, fixed relationship to tHe controller's clock dr, have no particul/ir relationship to it. The former ar,e, of 'course, synchronous operations, the latter asynchronous.
The major difference between an asynchronous and a
synchronous controller (or port of a controller, in the case
of the dual-port 8207) is that the asynchronous controller
must first synchronize the incoming commands to its own
internal clock. From that point on, the asynchronous controller looks just like a synchronous device.
Whereas variOUS techniques for 'synchronization are
available off chip, on-chip synchronization is restricted to
the res~lution and sampling of states of a flip-flop. The
Incoming command is clocked into a resolving flip-flop.
After a predetermined time, a sampling flip-flop reads the
state of the resolving flip-flop, thereby synchronizing the
command. Assuming that both flip-flops are triggered bn
the sarna edge of the controller'S internal clock, the fastest
that an asynchronous signal can be synchronized is one
clock period. The siowest synchronization takes two clock
periods; on the average, getting the signals in step takes
one and a half clock cycles.
B8cause the processor typically requires four or fewer
clock periods to complete a cycle, adding a cycle and a
half for synChronizing increases the' access time by
approximately 25%. Synchronous controllers are therefore
always preferred when the environment permits them. and
local Bl'!vironrnant!/, such as single-board computers, generallydoso.
6-57
AfN.02236A
AR-231
wise, the 8207 configures one port synchronously, and
the other asynchronously. For specific applications, both
ports may be programmed as either synchronous or
asynchronous (see "Dynamic-RAM controllers get in
step," p. 129).
Whether the ports are programmed for synchronous
or asynchronous operation, some mechanism must
decide which processor will gain access to memory when
both request it almost simultaneously. That mechanism
consists of arbitration logic that controls access and
always leaves one port selected. When a port is selected,
its associated control and interface signals are passed
directly to the RAM timing logic by the command multiplexer (Fig. 2). Both ports' command and control lines,
after being synchronized, go into both the command
multiplexer and the arbitration logic.
However, the arbitration logic enables the command
multiplexer to pass only commands that appear at the
selected port. At the same time as a command appears at
a selected port, arbitration logic initiates the cyclecontrol logic that completes the timing of the RAM cycle
that ensues. If a command appears on the unselected
port, it will not get through the multiplexer_ to initiate a
RAM cycle but will instead wait in the status-command
decoder until the current command is completed, at
which time the command mUltiplexer switches to the
unselected port. The arbitration logic will then service
this queued access request by starting a new cycle.
The arbitration logic examines all port requests,
including the internal refresh port. The refresh-request
port is subject to arbitration like the other two ports,
except that it is always assigned a higher priority than an
unselected external access port. Thus, refreshing can be
delayed, at most, one RAM cycle.
While the current RAM cycle is running, the arbiter
determines the next cycle to be initiated. Thus, the
arbitration time of two or more simultaneous port
requests is hidden by the memory cycle tim~_ In other
words, in cases where both a selected and an unselected
port request access simultaneously, the arbitration time
for the unselected port does not extend that port's access
time, which is delayed by one memory cycle anyway.
Only when an unselected port requests a free memory
does the arbitration time slow access, because then the
command must pass through the arbitration logic before
a RAM cycle can be initiated. To minimize such delays in'
most cases, there are two arbitration algorithms to be
selected by the user.
The first algorithm, intended for mUltiprocessing environments, automatically returns the arbiter to a designated preferred port, generally the higher-performance,
synchronous port. Thus any command on the selected
port generally has immediate access, whereas any command arriving at the unselected port must wait.
The second, or last-accessed-port, algorithm, which is
applicable in multitasking environments, leaves the most
recently accessed port as the selected port. This algorithm optimizes port selection for task passing in a
multitasking environment. In task passing, the host processor sends a task to an execution processor; until the
task is received, the execution processor seldom accesses
memory. Conversely, once the task is passed, the host
processor seldom accesses memory until the task is com•
pleted. Thus, the ports are used in spurts.
Because timely refreshing is needed to preserve
dynamic-RAM data, a refresh request is always serviced
on the next available cycle. The refresh algorithm, however, may be selected by the user. The options available
are: no refresh, user-generated single refresh, automatic
refresh, or user-generated burst refresh.
No refresh would be selected for applications like
bit-mapped-video displays, where continuous, sequential
access of all RAM locations itself refreshes every cell
periodically. User-generated refresh modes allow the
designer greater control over power, dissipation, for
example, in large memory systems. Automatic refreshing, in which the controller itself times the refresh interval and initiates 'the operation, lets the designer ignore
the refres4 requirements entirely. As mentioned, the
refresh req'uests are subject to arbitration just like other
access requests. However, once a burst refresh is selected, it remains active until completed.
Cleaning up errors
Ensuring data integrity is a major concern in large
dynamic-RAM systems, particularly because of their susceptibility to soft errors caused by alpha-particle radiation. Various parity encoding techniques have been
developed to detect and correct memory-word errors
[Electronics, June 2, 1982, p. 153]. The parity bits, called
check bits when used for correction as well as detection,
are stored in the memory array along with their associated data word. When the data is read, the check bits
are. regenerated and compared with the stored check
bits. If an error exists, whether in the retrieved check bits
or in the retrieved data word, the result of the comparison-called the syndrome-gives the location in the
group of the bit in error.
Tw~ drawbacks surface in the design 'of any memory
system that is to be protected by error-correction circuitry. First, the memory-word width must be increased to
store the check bits; second, extra time must be allotted
for the error-correction circuitry to generate the check
bits on write cycles, plus more time to regenerate and
cOmpare the check bits on read cycles. The 8207 provides several ways to minimize both-problems.
Error-correction schemes require a smaller proportion
of check bits to protect wider memory words. For example, an 8-bit word needs 5 check bits, for a 63% increase
in memory. Put the other' way around, 38% of the
available memory would be dedicated to the chec,k bits.
Six check bits are required to protect a 16-bit data
word-only a 27% overhead. Clearly, the wider the
memory array, the more economical the error correction.
The 38% overhead necessary to protect such 8-bit-bus
machines as the 8088 or 8085 makes error correction an
unattractive proposition. However, if the memory width
could be doubled, with the 8088 accessing only half a
word at a time, the overhead would drop to 27%.
Reading a douQle-width word, checking for soft errors,
and then sending the desired portion of the word to the
JXocessor presents no major problems, unlike writing to
such an array. The check bits cannot be calculated from
only a portion of the word-they must be calculated for
6-58
AFN-02236A
AR·231
PORTA
COMMANDS
SYNCHRO·
NIZER
ROW·ADDRESS
STROBE 0
COLUMN'ADDRESS
STROBE 0
PORT B
COMMANDS
SYNCHRO'
NIZER
RAS1/CASt
PROGRAM·
MING OATA
INPUT
SERIAL·
PROGRAM
COLLECTOR
RAS2/CAS2
RAS3/CAS3
CONTROL AND
TIMING STROBES
ERROR'CORRECTION'
CONTROL INPUTS
CONTROL
OUTPUT
PORT
CONTROL
ROW/
COLUMN
MULTI·
PLEXER
ADDRESS OUTPUTS
2. Arbiter's labor. Two external ports plus the internal 'refresh port can request access to the memory system at. once Arbitration logic
decides which to service, based on programmable algorithms. High-speed logic design cuts the delay from input to owtput switching to 55 ns
the entire word at once. Whenever the proces~or writes a the 8206 to read the data from the processor and calcupartial word to memory, it must first read' the entire late new check bits.
word, check it, substitute for that portion of the word to
The ability of the 8207 to handle memories organized
be rewritten, and recalculate the check bits. Only then as one, two, or four banks allows tradeoff's between the
can the entire word be written to memory. The 8207, cost and performance of an 'error-correction system. For
working in conjunction with the 8206 error-checking and maximum performance, memory would be organized in
-correction unit, contains mechanisms to expedite this four banks, each 16 bits wide. In applications requiring
error correction, but where maximum performance is not
potentially arduous process.
Whenever the 8207 performs a partial-write cycle, it critical, concatenation of RAM banks into two banks of
initiates a read-modify-write cycle wherein the entire 32-bit words, or even one bank of 64-bit words, can make
memory word is first read and latched into the 8206 error correction very ecoriomical.
(Fig. 3). After the retrieved data has been verified as
correct, new data is supplied to the RAM, half from the Holding to high performance
Even though the cost of error correction has thus been
processor and half from the 8206, which also generates
the check bits for the entire new word.
reduced to where it becomes an attractive solution, the
Control'signals-called byte marks-specify which problem remains of minimizing performance degradaportion of the new data word is coming from the proces- tion. Tackling that challenge depends or the particulars
sor and which from the 8206. The byte marks determine of the configuration, such as whether the memory is to
whether the processor or the 8206 drives the RAM data be used with a high-performance local processor, as
bus-for example, if the 8206 is driving one portion of system memory on a shared-resource bus, or is to be
the data bus, the processor is prevented from driving the shared between a local high-performance processor and
same portion. The byte-mark signals simply disable the a shared-resource bus.
appropriate transceivers. If, on the other hand, the proThe method chosen to handle errors depends on the
cessor is driving a portion of the RAM data bus, the byte type of bus, Intel's Multibus is the kind that requires
marks change the 8206 data outputs to inputs, allowing data to be valid prior to the issuance of a transfer6-59
AFN.Q2236A
intJ
AR-231
UPPER
MEMORY
LOWER
MEMORY
BYTEMARK
INPUT
3. Teemwork. The 8206 error-correction
chip joins forces with the random-access,rnernory controller so that an 8-bn-bus processor rnay utilize the 18-bn-wida rnernory
that Is rnore aconornical tor error-correction
schernes, Byte rnarks conbgure the data
buses for partial-word transfers,
, 8206
ERROR-DETECTION
AND -CORRECTION UNIT
acknowledge signal, in contrast to the local buses of the
iAPX-86, -186, and -286 processors. A local bus will
,usually be synchronous, with a single processor or coprocessor group attached to it; the processor characteristics
are known, as is the processor's response to a transferacknowledge signal.
With Multibus and other shared-resource buses, the
processor types that will eventually be connected are not
known in advance, and the buses themselves are generally asynchronous. Hence the time between the transferacknowledge signal and data becoming valid is not
known. 'Therefore, the rule with such buses is to
acknowledge a transfer only when data is valid. (On
some asynchronous buses, the acknowledgment is issued
earlier to' compensate for synchronization delay at the
receiving processor.)
Two basic configurations for checking and correcting
errors derive from these system considerations and the
fact that it takes longer to correct data than to detCCl an
error. One is for buses that connect to processors and
coprocessors receiving a transfer acknowledge prior to
data becoming valid, and the other for buses that connect to processors receiving a transfer acknowledge after
data is valid. Both configurations are supported by the
8206-8207 team.
Buses among the former type of processors always get
corrected data from the 8206, whether an error exists or
not, and will carry a transfer acknowledge from the 8207
before data becomes valid on the bus. Though this means
data is delayed for error correction on every transaction,
the extra delay is immaterial, since it is hidden behind
the processor's response time' ,to the transfer-acknowledge ,signal. By the time the processor requires data, it is
already corrected and on the bus. As a result, system'
performance is not degraded at all because of single-bit
errors.
For buses among processors that receive the transfer
acknowledge after the data is valid, the 8206 always
checks for errors but does not routinely correct data. In
this mode, RAM data passes through faster, because the
8207 will issue an acknowledgment sooner. If, however,
an error is found, the 8207 will lengthen the cycle,
command the 8206 to correct the data, and delay the
transfer-acknowledge signal until the corrected data can
be placed on the bus. For those buses with an acknowledge-synchronization delay, the 8207 can be programmed to issue the acknowledgment earlier to compensate for the delay.
Power-up problem.
Another problem with memories protected by ECC
circuits crops up when the (lOwer is turned on. At
power-up, the data stored in memory is completely random; any attempt to read or perform a partial write will
be aborted because the check bits will indicate multiple,
and therefore uncorrectable, errors. For processors
whose word width is the same as that of the'memory
array, the processor could simply initialize t'he entire
memory array, taking some additional time and software. For memories whose word width is greater than
that of, the processor, however, initiali~tion of the memory is not possible unless the error-checking or -correction circuitry is disabled by hardware, for example, by
gating off the error flags.
The 8207 is equipped to ,deal with the initialization
problem by itself. At system reset; the 8207 performs
6-60
AFN-02238A
AR-231
4. Interle.vlng. Overlapping accesses 10 dlfferenl banks increases memory Ihroughput.
Once the column-address hold lime is satisfied, the 8207 slarts a second cycle, pulling
Ihe second row-address strobe low.
,-
FIRST
RANDOM'ACCESS'MEMORY CYCLE
~I
SECOND
RAM CYCLE
ROW·ADDRESS
STROBE t
COLUMN'ADDRESS
STROBE 1
--If---""\
PRECHARGE
RAS2
CAS2
--+---+-----+---1-"'\
8207
ADDRESS
OUTPUTS
MEMORY
DATA
OUTPUTS
eight cycles on all bann at once to warm up the dynamic
RAMs, a typical RAM requirement for stable operation.
The chip then individually initializes all memory locations to 0, adding the proper check bits. Though all
memory banks could be initialized in parallel, that would
require more power than any other memory operation,
calling for a heftier and more expensive power supply
needed only at system reset.
One final problem associated with memories protected
by error-correction circuitry stems from the fact that
only data that is accessed by the processor is corrected.
If the processor continually accesses one particular segment.of memory, the rest of the ar~ay may be accumulating soft errors. The possibility of two soft errors
accumulating in a word of seldom accessed memory now
becomes significant-and not all double-bit errors are
correctable in simple ECC schemes. The 8207 scrubs
memories to clean up this problem. During each refresh
cycle, one word of memory is read, checked for errors,
and if necessary, corrected befote data is written back to
memory. Because scrubbing occurs during refresh cycles
with a read cycle replacing a row-address-strobe-only
refresh cycle, no performance penalty is incurred. Scrubbing rids the entire memory of errors at least once every
16 seconds, reducing the probability of two soft errors
accumulating in the same word almost to nil.
instruction, raises the probability that the same bank
may be immediately re-accessed. This probability is less
in four-bank memories than in two-bank configurations.
Further performance advantages are gleaned by
organizing memory into multiple banks. For example,
the 8207 can speed throughput by pipelining cycles.
Once the row and column addresses to one bank have
been latched, the controller sends the row address for the
next cycle to the next bank (Fig. 4).
The 8207's manifold features can be tailored to a
given system with the use of a serial programming pin.
This pin can either be strapped high or low to select one
of two default modes or be programmed by means of a
shift register. The external register is completely controlled by the 8207, eliminating any local processor
support. Sixteen bits are shifted into the 8207 to configure up to nine different features. The bits are arranged in
order of increasing importance; using a shift register
with less than 16 bits permits just those features needed
to be programmed.
Programmable features of the processor interface
include the choice of arbitration algorithm, clock compensation, and preferred port. At the RAM interface, the
user can specify fast or slow memory chips, indicate
bank configuration, and select the optimal refreshing
scheme. In anticipation of the next generation of 2S6-K
dynamic RAMs, the 8207 can support a 2S6-row-lBells and whistles
millisecond refresh convention, in addition to the 128All dynamic RAMS require a recovery period for pre- . row-2-ms one for current 16- and 64-K parts.
charging internal lines after each access. If the processor
Helping facilitate system design is a self-programming
were immediately to reaccess the RAM,. the controller processor interface. By decoding the command input
would have to delay it until the precharge time was over. pins at power-up, the 8207 automatically determines
By automatically organizing memory into banks so that whether it is connected to the status lines of an 8086,
sequential addresses are in different banks, the 8207 is iAPX-286 or to the command lines of the Multibus.
usually able to hide the prech~rge time of one bank Because the 8207 can directly decode the status lines of .
behind the access time of another. That organization Intel microprocessors, it can anticipate the next memory
follows· from using the 2 least significant bits of the cycle and start a new cycle before actually receiving a
address to select the bank. Of course, a break in the command. This extra' pipe lining enables the designer to
program flow, such as would be caused by a jump or call specify slower RAMS then would otherwise be required. 0
6-61
AFN·02236A
A SYSTEM-ORIENTED RAM
CO~TROLLER
Mel Bazes
James Nadi,r
. Bradley A. May
INTEL Corporation
3065 Bowers Avenue
Santa Clara, CA 95051
INTRODUCTION
Microprocessor-based systems are
making increasing use of dynamic RAM
over static RAM, as this is the most
cost-effective device for implementing
a large random access read/write memo-'
ry.
Dynamic RAM requires complex control circuitry which static RAMs ~o
not, bu't the cost of this control cir-,
cuitry is outweighed for memory of
more than 16K bytes by the lower cost
per bit and hi gher dens ity of dynami c
RAM.
However,
successive
generations
of
ml croprocessors
are
demandi ng
higher performance of dynamic RAMs, as
shown in Table 1 for se./eral families
of Intel microprocessors:
Some previously available controllers have provided. all the required
dynamic RAM support functions on a
single chip, but have not been fast
enough to provide no wait state performance wi th today I s faster mi croprocessors.
Other recent 1 y
introduced
dynamic RAM controllers have offered
higher performance, but required several additional shipe to complete the
control function. ,The 8207 is the
first dynam)c RAM controller to integ'
rate all RAM control functions ane
also provide no wait state performance
with all Intel microprocessors, inclu·
ding the iAPX-286 (80286 CPU).
Another factor of concern to c
memory system designer is soft errors.
Soft errors are random, nonpermanent
errors, usually of a single bit.
The
primary mechanism of these errors in
dynamic RAMs was discovered in 1978 to
be loss of stored charge in the dynamic RAM cells caused by alpha particles. l
These
result
chiefly
from
the radioactive decay of trace uranium
and thorium in the packaging material.
The rate of these errors increased as
shrinking
geometries
made
storage
cells more susceptible to the effects
of alpha particles. These ,soft errors
have been reduced by packaging innovations, but residual errors remain 2 ,
and so are still a concern. Since the
error rate of a memory system is the
sum of the error rates of all the memory components. the trend to 1 arger
RAM capacities in microprocessor systems will result in a higher system
error rate even if RAM soft error
rates remain constant.
Tabl e 1.' Required Memory Performance
for No Wait State Operation
Year
Introduced
1976 '
1978
1979
1982
Part
Number
8085
8086
8086-2
80286
Notes:
[ a]
The 80286
address is
[b] The 80286
,state is
cycle~ for
34/2
Clock
Freq.
3 MHz
5
8
8
Access Time
from Address
Access Time
from Command
430
265
117 a
335
195
90
----------------------545 ns
330 ns
Bus Cycle
Time
960 ns
800
500
250 b
uses pipelined addresses.
Access time fro~222 ns for interleaved ~emories.
bus cycle has three clock states, but the first
overlapped, with the third state of the last
an effective bus cycle of two clocks, or 250 os.
(
,
Coupled to these facts are the
ncreas i ng
rel i ab 1 il ity
requ irements
,f many microprocessor applications.
, single soft error in an automatic
,ank teller machine, for example, can
:ause an account balance error resul;ing
in
many
dollar's
worth
of
;lerical work finding and correcting
:he error, as well as possible down
;ime
for
the
teller
machine
and
Frustration for the customer.
microprocessor-based systems are:
1.
A separate microprocessor may be
used to control all I/O activities, leaving the main microprocessor free to do data processing
tasks full time.
If the program
being executed by the main processor generates any I/O requests,'
these requests (read a disk file,
send a file to a line printer,
etc.) are formatted as a message
to the I/O processor, containing
the desired activity and where
the input or output file is located is shared memory, and the message is placed in a reserved
area of shared memory, to be read
and executed by the I/O processsor.
All the mechanical activities of I/O (polling disk status,
spooling print files, etc.) are
handled
by the
I/O
processor,
while the main processor executes
the
main
program.
The
I/O
processor
may be on
the same
board or another board connected
by a global bus, such as the
Intel Multibus.™
2.
Separate processors may execute
different real-time tasks simultaneously, as in a process control
application.
Various process parameters will be stored in
sh ared memory, where it may be.
sampled and/or updated as necessary by each of the processors to
control the process in real time.
Again these processors may be on
the same or different boards.
Error checking and correction, or
:CC, as implemented by modified HamTl1ng codes uses redundant memory bits
to encode the data.
This code allows
detection and correction of all single
Jit errors in any memory word, and detection (but not correction) of all
double bit and some higher-number-ofbit errors.
The effect of ECC of !"emory system reliability is shown ln Table 2.
These figures are based on the analysis of all types of errors (hard and
soft) as measured for the Intel 2117
dynamic RAM, and shows an improvement
in reliability as measured by the mean
time between failures (MTBF) of between 24 and 301 times for the memory
configurations shown. 3 ,4
Clearly, for the assumed error
rates, soft errors become unnacceptab1e for large RAMs, and ECC is desirable.
The 8207 facilitates the addition of ECC by directly controlling
the companion 8206 Error Detection and
Correction Unit, and adjusting memory
cycle timings as required for ECC
operation automatically.
In thes~ and other appl ications,
this multiprocessing is facilitated by
dual-port memory.
A dual-port memory
is one in which two processors, each
on its own separate bus have independent access to the same physical mem-
Lastly, architectural factors are
important to des i gners of memory systems.
Hi gher performance mi croprocessor' systems can be obtained by the use
of multiple processors operating on
shared data. Common examples in
Tabl e 2.
Improvement in Memory
Reliability with ECC
Memory Size an d
Organization
------------------------32
64
128
4
8
16
Kbyte (16K x 16 bits)
Kbyte (16K x 32 b its ~
Kby'te (16K x 64 bits
Mbyte (2M x 16 bits)
Mbyte (2M x 32 bits)
Mbyte (2M x 64 bits)
MTBF
(no ECC)
---------
5.6 yrs
2.7 II
1.4
16.3 days
8.1 II
4. 1
6-63
MTBF
(with ECC)
----------
133.6 yrs
75. 1 II
40.5
10.8 II
6.1 "
3.3 "
Improvement
Ratio
----------24
28
29
246
278
301
34/2
The 8207 has a dual port memor
interface.
Port arbitration is don
on-ch i p.
Semaphores are supported i
hardware by a LOCK input which may b
activated by one port to prevent memo
ry accesses by the other port.
ory.
Since the processors are independen-t, the dual p,ort memory itself
must resolve the conflict that arises
if each processor tries to access the
memory simultaneously.
If multiple processors are used
on
single bus,. performance will be
limited by the bandwidth of the bus,
and the time spent exchanging bus control.
A dual-port RAM allows each
processor full use of its own bus. . To
prevent the bandwidth of the dual-port
RAM from limiting system performance,
at least one processor should have its
own (single-port) RAM, and only those
memory segments shared between processors should be placed in dual-port RAM.
a
, DEVICE DESCRIPTION
The 8207 Advanced
Dynamk
RAI
Controller
(described
by
Figure 1
provides all required dynamic RAM can·
trol functions in a single chip,
including:
Also,
some
method
(called
a
"semaphore") must be provided to control access to the memory so' that one
processor can modify sections of data
without the other processor being able
to see that section while it is being
modified.
As an example, if a shared
memory contained a 1 ist of passengers
on an, airline flight, an error would
result if two processors'at almost the
same time found an empty spac'e on the
passenger 1 ist, and each wrote a new
passenger's name into that same space.
One processor must prevent the other
from
accessing
the
passenger
1 ist
before it 'can look to see if there are
empty places.
1.
The
820;
Address
multiplexing
generates
the
row
and
col umr
addresses
used
by the dynamic
RAMs.
2.
Refresh
The
8207
internally
generates
refresh
cycles
when
necessary;
an
external
input
allows the user's system to generate refresh cycles when desired.
An 8-bit counter determines the
row to be refreshed.
3.
Arbitration
Since read, write,
and refresh cycles cannot be done
simultaneously, the 8207 determines which will
be performed,
and when.
The 8207 arbitrates
between memory requests from each
of the two ports, and the refresh
logic.
Because a requested mem
CLOCK SOURCE
,.-:-,
CLK
CPU ADDRESS {
BUS
(MULTIPLEXED
BETWEEN PORTS)
MJ'J-~f~~
AOo-8
oo:\'I.l,:~ {
8207
ADVANCED
DYNAMIC
RAM
CONTROLLER
{
8207 {
PROGRAMMING
INFORMATION
CAS
WE
DBM
wz
oo=~~{
~~~~S~Lg:i~
R/W
!1UimI
CE
ESTB
J~O:OR
DETECTION
AND CORRECTION
UNIT CONTROL
}
~:g:ELOGGING
}
DATABUS
CONTROL
(PORT SELECT)
REFRQ
PSEL
PDI
PCKL
Plmi
Figure 1. 8207 Logic Symbol
34/2
DYNAMIC
RAM
CONTROL
iW
(
6-64
L
ory cycle may be delayed by a
cycle in progress. the 8207 provides separate acknowledge signals to each port to indicate
when the requested cycle has been
completed.
access priority should be resolved,
etc.
The 8207 uses one pin (POI)
forprogramming,
through
which
programmi ng data is seri all y shifted,
with another pin (PCLK) used as a
shift clock. as shown in Figure 2.
Cycle timing
Timing of the RAM
addresses
and
control
strobes.
ECC
and
error
strobes.
port
multiplexing signals. and memory
cycle acknowledge signals are all
generated internally by the 8207.
Refresh timing. arbitration. and
cycle timing are all done from a
single
clock
input.
Timing
changes
may
be
made
by
programmi ng opt ions on the 8207.
or
by
adjusting
the
clock
frequency.
Tyi ng POI to ground programs the
8207
to
operate
in
non-.error-correcting mode; tying POI high puts the
8207 in error-correcting mode.
All
other programming options default to
values optimized for those configurations. If it desired to change any options from their default val~es. a
parallel-in-serial-out
(PISO)
shift
register, such as the 74LS165. may be
at t a c he d t o t h e pro g r a mm i n g pin.
The
system reset input loads this shift
register with the jumper-selected programming
options.
which
are
then
clocked into the 8207.
One or two
shift registers may be used to provide
up to 16 bits of programmabi 1 ity'.
The 8207 directly addresses and
drives up to 88 RAMs (16K. 64K. or
256K). with no external drivers.
The
8207 Advanced Dynamic RAM Controller.
like its companion, the 8206 Error
Detection
and
Correction
Unit.
is
implemented in HMOS II. a production
proven NMOS process. and is packaged
in a 68-pin JEOEC Type A chip carrier.
Microprocessor Interface
Programming
The 8207 can operate in singleported or dual-ported memory configurations.
Each port is individually
programmable to operate in a variety
of system configurations.
In order to optimize its performance in as many system environments
as possible. the 8207 programs itself
at system reset with information about
the application system; what type of
microprocessor it is interfaced to.
whether ECC is used or not, how port
Each port may respond to standard
demultiplexed read and write command~
as shown in Figure 3b.
The IfD and WI{
inputs are internally qualified by a
port enable (Pf) signal. which is normally decoded from the address _bus.
No memory cycle can start unless PE is
s~:rr-----"--------~RESET
r-----~PCLK
PISO SHIFT REG.
8207
'::'J-f t - -.... PDI
.---_-+--+_ _~--+-_+l_J-UMPER OPTIONS
10
Figure 2. Programming Interface
6-65
34/2
once the system is up and ru-nn ing.
PCTL may also be used for those microprocessors which have a separate memory management unit which generates an
inhibit signal if a program attempts
to access protected memo;y.
active.
A port control (peTL) signal
is provided, which qualifies the start
of a memory cycle, anq can also inhibit a memory cycle that has already
been started.
If peTL is deactiv.ated
before the memory cycle starts, no cycle will be performed.
If it is deactivated after the RAM cycle starts,
the memory cycle will complete, but
the RAM write enable, memory cycle
acknowledge, and error logging strobes
will be disabled; no data will be wri·tten to memory.
The user must use
peTL to disable data transceivers to
prevent data from being read.
Each port may also be programmed
to directly decode the status outputs
of Intel's iAPX-86, 88, 186, and 286
families of microprocessors, as shown
i n Fig u r e 3 b •
I nth i s mo de, the RD.
WR, PE, and pen inputs are redefined
to be the apporpriate status inputs.
When used in this way. the 8207 is
normally operated synchronously to the
microprocessor, from the same clock
generator,
as
shown
in Figure 3a.
Because the 8207 must be able to operate syncronously with several different microprocessors with clock rates
from 5 MHz to 16 MHz and with different bus cycle timings, the 8207 varies
memory cycle timings so as to be compatible with the microprocessor it is
interfaced to.
peTL is useful if RAM and ROM are
overlaid in the same address space,
and it is desired to de-select the RAM
in
those
addresses
where
ROM
is
present.
Th i s i s often the case at
system reset, where a "boot-strap" ROM
is selected in part qf the RAM address
space to start the system.
RAM is
select~d in this same address space
l
CLOCK
.1
I
~
t
ClK
8088
~
WR
S1
S2
iii)
ADDRI
DATA
PCTl
'"
ADDRESS
DECODE
"
L
I
ClK
8207
PE
A. SYNCHRONOUS
8207
8086
B. ASYNCHRONOUS
Figure 3. 8086 Interface
34/2
6-66
One of two arbitration algorithms
may be selected to "tailor" the 8207
to the application.
In one method.
Port A is the preferred port. so whenever the 8207 is
idle. Port A is
selected. minimizing access time for
that port.
In the other method. the
most recently used port is selected.'
When used asynchronously to the
nicroprocessor, all inputs are interla11y synchronized by the 8207.
When
Jsed synchronously, these synchronizars are bypassed, eliminating
synchronization delays.
II.rbitration
Each port has physically separate
RD, WR. PE, and PCTL inputs. as shown
in Figure 4.
In this application. the
8207 interfaces synchronously to Port
A (8086) and asynchronously to Port B
(Mul tibus); all Port B inputs are synchronized.
but
synchronizers
are
bypassed on Port A.
As
an exampl e. if Port A was
attached to a high-speed microprocessor used in for data processing. and
Port B was attached to an I/O processor. it would probably be better to
make Port A the preferred port. to
minimize its average access time and
maXlmlze processing throughput. especially since the I/O processor on Port
B is 1 imit,ed by the slow speed of the
mechanical peripherals to which it is
attached, not memory access time.
The abitration logic arbitrates
between three ports; Port A. Port B.
and Port C (the refresh port).
Any
port may request memory at any time.
A LOCK input is provided which
allows either port to lock out the
other and gain sole access to the
memory.
This, is useful for testing
and setting semaphores in shared memory segments.
It may also be used to
allow one port to transfer bursts of
data to or from memory at maximum
bandwidth.
without
the
other
port
stealing any memory cycles.
Once Port A or B is selected. it
ha's
immediate access to the cycle
timing generators and the arbitration
logic is bypassed for subsequent memory cycles.
The arbitration delay in
this case is zero.
If the unselected
port requests a memory cycle, the arbiter must first select it.
Arbitration for the next memory cycle is done
in parallel with a memory cycle in
p.rogress, so usually this arbitration
time is hidden. and the new cycle
starts as soon as the cycle in progress to the previously selected port
is complete.
8086
Due
to
pin
limitations.
the
address. RAM bank select. and LOCK
inputs are multiplexed between Ports A
and B.
The arbiter generates a MUX
output which is used for this purpo!je,
as shown in Figure 4. This figure
SOt-----I-.tWRA
CLK
WRB ....- - - - - W R
Sf
8207
Jmi
RDA
im
....- - - - - I N H
FROM
MULTIBUS
ADDR
Figure 4. 80861Multlbus Dual-Port Interface
6-67
34/2
shows
multiplexing
being
done
by
alternately enabling 3-state latches;
cross-coupled NAND gates are used to,
create non-overlapping enable signals.
RAM Interface
Nine RAM address outputs !Jlll four
pairs of Row Address StroJ2.g,. (RAS) and
Column Address Strobe (CAS) signals
allow the 8207 to interface to four
banks of either 16K, 64K, o~ 256K RAMs.
m
Novel circuit design techniques
were used to allow R·AM outputs to be
generated with less than 35 ns propagation delay from the 8207 clock input,
while
requlrlng
input
set-up
times of only 20 ns 5
rn/m
m
m
rn
Separate
and rnoutputs also
allow the 8207 to interleave memory
cycles to alternate banks of RAM,. as
shown in Figure 5. In this way, the
RAM's precharge time (tRP)' which is
normally part of the RAM cycle time,
may be hidden in the following memory
cycle.
If consecutive cycles are to
the same bank, the second cycle must
be delayed,. as shown by the dotted
line in Figure 5.
Refresh
The 8207 supports both the 128
row/2 ms or the 25q row/4 ms refresh
conventions.
A 256 row/2 ms option
may also be programmed for possible
use with 256K RAMs.
The 8207 generates. one refresh
cycle approximately every 15 )Js, thus
executing 128 refresh cycles in 2 ms,
or 256 cycles in 4 ms.
If the 256
row/2 ms option 'is used, one refresh
cycle is generated approximately every
7.5 us.
An 8-bit counter keeps track
of the row to be refreshed;
this
address is prov i ded to the RAM by the
8207 address outputs.
If only one or two banks of RAM
are occupied, the
output drivers
re-a1locate
themselves
to
increase drive capacity.
If only two
banks here are occupied, ~ 0 and
1 work in. tandem to drive Bank 0,
and
0 and rn 1 do s imil arly;
2 and
3; and
2 and
3
work in tandem to drive Bank 1. In
m
m
rn
Output drivers with high capacitive drive capability allow the 8207
to. drive up to 88 dynamic RAMs, arranged as four banks of 22 RAMs ea<;.h (16
data bits plus 6 ECC check bits) without external drivers.
A.C. timings
are specified at a load of 55Q...RF on
Address olftputs and 250 pF on RAS and
outputs.
With this large a load,
the transient currents are
in
the
ampere range; because of this, the
output drivers are isolated from the!
rest of the circuitry with separate
Icc and ground pins for each.
The
driver circuitry was also designed to
prevent
any
"boot-strapping"
effect
and to limit volt~ge overshoot.
m
m
rn
this way, the two banks may conS'i,st of
up to 44 RAMs
(twice as many as
before) without ,increasing the loading
on the ~ and
drivers. Since the
total nu·mber of RAMs remains the same,
the loading on the Address outputs,
which go to all RAMs also remains the
same.
If lliY one bank is occupied,
all
four
and
driver ,work
together to allow. driving a single
bank of 88 RAMs.
An external refresh request input
(REFRQ) is provided so the system may
cause refreshes to be perfomed whenever desired.
If no refreshes are
m
i-+---NORMAL CYCLE TIME---+-\
INTERLEAVED
CYCLE TIME
RASO
________J
....J/
R A S 1 - - - - - - - -.....,\.._ _ _ _ _
Figure S. 8207 Bar:'k Interleaving
34/2
6-68
The 8206 (described in Figure 7)
can correct single bit errors ·in any
memory word, and detect (but not .correct) all double bit errors, and some
errors of more than two bits.
Each
8206 does error correction on a 16-bit
sl ice of the memory word, and up to
five 8206s may be cascaded for 80-bit
data words.
equested in
15 ps,
the 8207
may
enerate
an
internal
"failsafe"
efresh.
The internal re'fresh may be
urned off entirely, so that the only
efresh cycles are those externally
enerated. In this case, bursts of 128
'efresh cycles
(internally counted)
'ill also be performed by activating
;he REFRQ for a slightly longer period
)f time.
Since
the
refresh
cycles
timed from the 8207 clock input,
1umber of clocks between refresh
:les may be programmed, to allow
~ifferences in clock frequencies
between 3.5 MHz and 16 MHz.
The 8206 generates modified Hamming code check bits on write cycles,
checks for and corrects errors on read
cycles, and generates an error flag, a
correctable/uncorrectable error flag,
and syndrome outputs which may be used
to pinpoint the bit in error for error
loggil)g.
Both data and check bit errors
are
corrected
automatically,
without changing ttle mode of the 8206.
Control inputs are provided for byte
writes.. A data/check bit input 1 atch
is
provided.
Unique
separate
data/check bit input and data/ check
bit output busses reduce the amount of
control required to implement an ECC
memory system.
are
the
cyfor
ECC Interface
The 8207 may also be programmed
to support error checking and correction (ECC).
When in this mode, cycle
timings are adjusted and several pins
change function to support the companion 8206 Error Detection and Correction Unit, as shown in Figure 6.
ADDR
8207
!Wi
CAS
9
DATA
4
RAM
4
CHECKBIT
RAM
WE
TO
BYTE
LOGIC
FROM
BYTE
LOGIC
Figure 8. ECC Interface
6-69
34/2
RAM DATA INPUT
CHECK BIT I/O
~~
Dtl~HHi¥~o~~
(
SYO
WRITE ZERO
(FORCES DATA (
OUT "'0)
READIWI'ii'i'E (
ERROR! {
CORRECTABLE
ERROR FLAGS
CE
PPO
PARTIAL PARITY OUT {
MAJ~~=~
FROM SLAVES
IN MULTI·8208
SYSTEMS)
8208
ERROR
DETECTION
AND
CORRECTION
UNIT
ERROR
8
8
}
J
PROGRAMMING
INFORMATION
}
(SLAVE
ONLy)
'---....,---.J
'Wsi ~g=~~'ES
WRITE CYCLES)
SYNDROME
OUTPUT
(FOR ERROR
LOGGING)
PARTIAL PARITY IN
(USED BY MASTER
TO GENERATE
CHECK BITS!
SYNDROMES
IN MULTI·8206
SYSTEMS
'---....--J
DATA INPUT (WRITE CYCLES)
DATA OUTPUT (READ CYCLES)
Figure 7. 8206 logic Symbol
All correctabl e errors di csovered
during read
cycles
are
immediately
corrected in RAM. The 8207 monitors
the 8206
flag during read cycles.
If it is active, the read cycle
is lenghtened to become a read-modifywrite cycle; the 8207 also activates
an Error Strobe which can be used to
latch
the
8206
error
flags
and
syndrome outputs for error loggging,
or to interrupt the microprocessor.
During
byte
write
cycles,
error
correction is automatically done on
the byte(s) of the word not being
ch an ged .
written back into RAM.
By this process, the entire memory is scrubbed of
errors
every
30
seconds
or
1 ess,
making the possibility of two soft
errors accumulating in the same word
(an uncorrectable error) virtually nil.
rrnnm
RAM Initialization
Upon system reset, the 8207 resets its refresh counter and performs
eight cycles to all four banks at once
to "warm up" the dynamic RAMs (many
dynamic
RAMs
require this warm up
period after power up for stable
operation).
To further .i ncrease memory rel iab i 1 i ty, the 8207 does memory scrubbing during RAM refresh, as shown in
Figure 8.
During a refresh cycle, the
8207 refreshes one row in all banks.
It also outputs a col umn address and
activates one of the four ~ outputs,
to read one word of memory.
That word
is checked for errors by the 8206; if
any are found, the corrected data is
14/2
I nEe C mo de, the 8207 a 1 so i n i tializes all of memory to zero data
and the corresponding check bits.
It
does th i s by act i vati ng the 8206 Wri te
Zero input and performing consecutive
write cycles to each memory location.
This is done because on power up the
contents of the RAM are undefined, and
subsequent byte writes may cause false
"errot's" due to the undefined data in
memory.
Because the time to do this
6-70
-:::y.
ADDR
ADDRES!I TO,!E SCRUBBED
REFR ROW
X
COLUMN
X\.._______
F--------r--
m(ALLFOURI~
(
\
!:AS (ONE ONLY)
I
,r-------,
RAM DATA OUT
(GOES TO 8208)
(
VALID
)-
\
ERROR
--)--
-----~
VALID
X
CORRECTED DATA
(GOES TO RAM DATA INI
RAM
NOTE:
_-..J
:>=---------r
,-------(
WE
DOT~ED LINES SHOW CASE WHERE NO
ERROR IS DETECTED.
FIGURE
8. SCRUB CYCLE (ERROR DISCOVERED
AND CORRECTED IN
RAM)
first dynamic· RAM controller to provi de comp1 ete dynami c RAM control on a
single chip and no wait state performance with all Intel microprocessors,
including the iAPX-286.
is fairly long, about 1 second, the
8207 may be programmed to skip initialization on reset.
Any memory requests during the
warm up/initialization sequence will
be latched internally and responded to
as soon as the sequence is complete.
By having the 8207 do these "housekeeping" tasks, they are no longer a
burden on the system software, and
they are done faster than would be
possible by software.
In
addition, the
8207
offers
other advanced features, such as ECC
·contro1,
automatic
error
scrubbing,
and a dual-port RAM interface.
SUMMARY
The authors wish to thank Moti
Mebe1, David Perlmutter, Beni Mantel,
and Omer Zak, for their contributions
to the design of the 8206 and 8207.
ACKNOWLEDGEMENTS
Previous dynamic RAM controllers
have offered either integrated control
or high performance.
The 8207 is .the
6-71
34/2
REHRENCES
[1]
"A New Physical Mechanism for Soft Errors in Dynamic Memories"
Timothy C. May, Murray H. Woods, INTEL Corp.
IEEE Proceedings of the Int'l Reliability Physics Symposium, April 1978.
[2]
"Alpha-Particle-Induced Soft ErrDr Rate Modeling"
George A. Sai~Halasz, IBM Research Center
IEEE Int'l Solid S~ate Circuits Conference, Feb. 1982.
[3J
"Keep Memory Design Simple Vet Cull Single-Bit Errors"
M. Bazes, L. Farrell, B. May, M. Mebel, INTEL Corp.
Electronic Design, Sept. 3D, 1981.
[4J
"Memory System'Reliability with ECC"; Intel Ap Note 73
Dennis Marston, INTEL Corp.
[5J
"An NMOS DRAM Controller"
M. Bazes, J. Nadir, D. Perlmutter, B. Mantel, O. Zak, INTEL Corp.
IEEE Int'l Solid State Circuits Conference, Feb. 1982.
34/2
6-72
intel"
TECH
PAPER
August 1982
((-1
1982 IEEE. Reprinted. with permISSIOn, from 1982 IEEE Internltion-' SOlid-States ClrcUIf$ Conference. Digest of Techntcal Pipers. Feb
10-12. ,9821Sa" FrancIsco. CA.
AUGUST 1982
ORDER NUM_":
6-73
2'05_'
TECH PAPER
SESSION VII: DYNAMIC RAMs
WPM 7.4:
An NMOS DRAM Controller
M.I SlIr••, h",.. Nadi" Onid "."""",.'. Sanl' Man,.'. Om", Z.
Int.'Corp.
S.ntll ClllfII. CA
de.ign. Instead of usi", two-ph ... logic, mo.t common in NMOS
design, the ORC WI. implement.d ....i ....i ...le·phaoe edge
triqe .. d Oipnopo. Th. use of only on. clock pha.. inherently
pr.clud•• the probl.m of clock overlap. whIle sequencIng lottic on
a 8i",le clock edge provid•• seyeral important b",dits. F, .. t. th'
sensitivity to clock low and hIgh time. is greatly .. duced. Second.
lottic design is signIficantly simplifi.d. Third. overaU 10lllc
throughput can be mlde mo .. efficIent thin with two.pha ..
logoc. Finally.th. straightforward logic drsign ..suits on Slmphfi.d
cirCUIt drsign. u evidenced by the fact that th. first ,teralion of
the ORC that wao fabrocaled was functional at tbe full 16MHz
clock f.. quency.
The ORC output pulse timings have been selected for optomal
performance withon atlr .. t the 62.5n8 re.oluhon prOVIded by the
clock. In the case of the erotical Row Addre .. Select (RAS).
Column Add",ss Select (CAS), and addre .. outputs. the resolu.
tlon obtaln~ IS down to only a rew nanost'conds and 1.8 provldr-d
ontrmally by sprdally d.sognrd delay elements. The .. delay ele·
ments art Implt'mentrd u voltage controllf'd capacItive loacb
wh;ch comprnsatethe chip output switchlnR delays agaonst ,uoplj.
teinperatu ... and process!", variations.
In asynchronous environmf"nts, access time ill Impro""d bv
requiring an overhead of only one 62.5ns clock period In synch.
ronizing up asynchronous inputs.
An important f.ature of the ORC is Its abillly 10 .. mple a
singl. input WIth a .etup time of only 20ns and to clock out
..~.rai different output signals from that ,ingle onput in under
35ns. Thos low setup lime IS obtaIned by using .. ro·r"i.tan«
input protrctlon devices to ,.due. RC delay •• and to provldr TTL·
to·MOS bufferiR$[ dirertly at the Jlent'ntor cirCUits. rather than at
the input pad.:. The .hort oulput d.lay is obtam.d by tnlllt"i",
the output •• nrrators di .. ctly off of th. unbuff... d rxternal
clock. the .. by saving the buffer drlay tim. prrsent in thr buff..rd
clock. Figure 30 Illusthl"s an examplr of a h,gh.spred pulse
grn.rator CIrCUIt which is triRl!erable off of eoth .. the clock riSIng
.dge or the clock falling .dge. Th. pul .. gen ..ator tlmong beha·
vior, is shown in Ftgu1'e' 3b. "
Th. object ... of cruhng a highly.integrated dynaml. RAM
controll.. has ....sult.d In a ne.,ble devicr WIth .oph.. ticatrd
arbItration between ports. optimizrd output pul.. timings. and
minImal Input setup and output delay time•• and which allows
designillll higher performance memoti.s using' slow .. speed
dyna mic RAMs.
TO DATE. Integrated dynanuc RAM controUero have been eith.r
optuni..d for speed or for fe.ture •• with one usually at the ex·
prn.e of the other. ControUe .. d~.ill""d to give no wait otat••
have rtqu".d severll addihonll TTL device. and delay Unes to
("()mpiete the basic dynamIC RAM control functiono. ·Int.grated
controlle~ have slowrd today's mocroprott"""" by adding wait
,tat,•. The chIp to be ducnbed. the ORe (Dynamic RAM Con.
troU,,). WIth Its h,l!h level of Integration. can support 8MH.
CPU, with I jOns DRAMs WIthout wait ,tate,. The controller.
oJ)f'ratm,; In both slh5t:le-port and dual-port confi~rations and in
~ynchronoWl and asynchronous f'nVl~ronments. supports error
correction Circuitry. and proYldf"8 all of' the timing and control
signals necessary ror a mf'mory module. Two mlcroproces.'mr
bus port1! are mdept:ndently programmable for e'ither synchronous
or asynchronou.'I o~ration. and tach IS capable of supporting
srvf'ral pOIt.'ilble bus strucluretll.
Thr OOTO-Ms
AH.
ALO- Al6
AHa
AH,
AH,
ROW
ADDRESS
AHO
ALo
RASa
BO
RAS1
REFRESH
COUNTER
RO/S1
""
RAS2
...........
~-----t
------I
RAS3
CAS
TIMING
GENERATOR
ARBITER
AL,
0UT1
AL,
00r2
ALa
f-.
PCS~-----t
. Mo
WE
M3
AL4
0iIT4
REFRQ/ ALE
SACK
-----''-----I
XACK
ALs
OOTs
Ale
0iJf6
GND,
tXt)CLK
Figure 1. 8202A Block Diagram
Figure 2. Pin Configuration
6-77
8202A
'Table 1. Pin Descriptions
Symbol
Pin
No. Type Name and Function
ALO
ALl
AL2
AL3
AL4
AL5
AL61
6
8
10
12
14
16
18
I
I
I
I
I
I
I
Address Low: CPU address in·
puts used to generate memory
row address.
AHa
AH1'
AH2
AH3
AH4
AH5
AHa
5
4
3
2
1
39
38
I
I
I
I
I
I
I
Address High: CPU address in·
puts used to generate memory
column address.
BO
Bl /OP l
24
25
I
I
Bank Select Inputs: Used to
gate the appropriate RASO·
RAS3 output for a, memory cy·
cle. Bl/OPl option used to se·
lect the Advsnced Read Mode.
PCS
33
I
Protected Chip Select: Used to
enable the memory read and
write inputs. Once a cycle is
started. it will not abort even if
J5CS goes inactive before cycle
completion.
31
I
Memory Write Request.
RD/Sl
32
I
Memory Read Request: 51
function used in Advanced Read
mode selected by OP 1 (pin 25).
34
OUTO
7
9
11
13
15
17
19
OiJf l
OUT2
OUT3
0iJf4
0iJf5
0iJf6
I
0
0
0
0
0
0
0
0
RAS3
~~
21
22
23
26
0
XACK
29
0
Transfer Acknowledge: This
output is a strobe indicating val·
id data during a read cycle or
data written during a write cycle.
XACK can be used to latch valid
data from the RAM array.
SACK
30
0
System Acknowledge: This
output indicates the beginning of
a memory access cycle.' It can
be used as an advanced trans·
fer acknowledge to eliminate
wait states. (Note: If a memory
access request is made during a
refresh cycle. SACK is d~layed
until. XACK in the memory ac·
cess cycle).
(XO) OP2
(Xl) CLK
36
37
110
110
OSCillator Inputs: These inputs
are designed for a quartz crystal
to control the frequency of the
oscillator. If XO/OP2 is connect·
ed to a 1KO resistor pulled to
+12V then Xl/CLK becomes a
TTL input ,for an external clock.
RASa
Row Address Strl;)be: Used to
latch the Row Address into the
bank of dynamic RAMs. select·
ed by the 8202A Bank Select
pins (BO. Bl/OP1).
0
0
' ,
WR
REFRQI
ALE
Pin
No. Type Name and Function
Symbol
...
I;xternal Refresh Request: ALE
function used in Advanced Read
mode. selected by OP 1 (pin 25).
N.C.
35
Reserved for future use.
VCC
40
Power Supply:+5V.
GND
20
Ground.
NOTE: Crystal mode for the 8202A-l or 8202A-3 only.
Output of the Multiplexer:
These outputs are designed to
drive the addresses of the Dynamic
RAM array, (Note that the OUT0-6
pins do not require inverters or
drivers for proper operation.)
i--
,..
CAl
cs..L.
'KO
±5%
I
I
8202A-l
or
oeoo
WE
CAS
28
27
0
8202A-3
± ...
":"
Write Enable: Drives the Write
Enable inputs of the Dynamic
RAM array,
Cs
<
10pF
FUMlAMENTAL XTAL
Column Address Strobe: This
output is used to latch the Col·
umn Address into the DynamiC
RAM array.
IlUo
x,
I
":"
0'
WE
Xo
I
lin,
m.
iiAI3
mK
mR
Figure 3. Crystal Operation for the 8202A-1
, and the 8202A-3
6-78
AFN 01838A
8202A
Functional Description
the memory's rows. The 8-bit counter is incremented after
every refresh cycle.
The 8202A provides a complete dynamic RAM controller
for microprocessor systems as wen ss expenaion memory
boards. All of the necessary control signals are provided for 2117 and 2118 dynamic RAMs.
Address Multiplexer
The address multiplexer takes the address inputs and the
refresh counter outputs, and getes them onto the address
outputs at the appropriate time. The add~s outputs, in
'conjunction with the RAS and Ci£ outputs, determine the
address used by the dynamic RAMs for read, write, and
refresh cycles. During the first pert of a read or, write cycle, ALe-Ala are gated to OUTo-OOTa, then AHo-AHa
are gated to the address outputs.
All 8202A timing is generated from a single reference
clock. This clock is provided via an external oscillator or
an on chip crystal oscillator. All output signal transitions
are synchronous with respect to this clock reference, except for the CPU handshake signals SACK and XACK
(trailing edge).
CPU memory requests normally use the RD and WR inputs. The advanced READ mode allows ALE and S1 to be
used in place of the RD input.
During a refresh cycle, the refresh counter is gated onto
the address outputs. All refresh cycles are RA8-0nly refresh (Ci£ inactive, RAS active).
Failsafe refresh is provided via an internal refresh timer
which generates internal refrsah requests. Refresh requests can also be generated via the REFRQ input.
To minimize buffer delay, the informetion on the address
outputs is inverted from thet on the address inputs.
An on-<:hip synchronizer I arbiter prevents memory and refresh requests from affecting a cycle in progress. The
READ, WRITE: and external REFRE~H requests may be
asynchronous to the 8202A clock; on-<:hip logiC will synchronize the requests, and the arbiter will decide if the requests should be delayed, pending completion of a cycle in
progress.
OUTo-ooT6 do not need inverters or buffers unless additional drive is required.
Synchronizer / Arbiter
The 8202A has three inputs, REFROI ALE (pin 34), RD
(pin 32) and WR (pin 31). The RD and WR inputs allow an
external CPU to request a memory read or write cycle,
respectively. The REFRQI ALE allows refresh requests to
be requested external to the 8202A.
Option Selection
The 8202A has two strapping options. When OP 1 is selected (16K mode only), pin 32 changes from a RD input to
an S 1 input, and pin 34 changes from a REFREO input to
an ALE input. See "Refresh Cycles" and "Read Cycles"
for more detail. OPl is selected by tying pin 25 to
+ 12V through a 5.1 K ohm resistor on the 8202A-1 or
8202A-3 only.
All three of these inputs may be asynchronous with respect to the 8202A's clock. The arbiter will resolve conflicts between refresh and 'memory requests, for both
pending cycles and cycles in progress. Read and write requests will be given priority over refresh requests.
System Operation
When OP2 is selected, by connecting pin 36 to +12V
through a 1K ohm rI~sistor, pin 37 changes f~om a crystal
input (X 1) to the CLK input for an external TIL clock.
The 8202A is always in one of the following states:
a)
b)
c)
d)
e)
Refresh Timer
TIle refresh timer is used to monitor the time since the last
refresh cycle occurred. When the appropriate amount of
time has elapsed, the refresh timer will request a
refresh cycle. External refresh requests will reset the
refresh t i m e r . '
'
IDLE
TEST Cycle
REFRESH Cycle
READ Cycle
WRITE Cycle
The 8202A is normelly in the IDLE state. Whenever one of
the other cycles is requested, the 8202A will leave the
IDLE state to perform the desired cycle. " no other cycles
are pending, the 8202A will return to the IDLE state. '
Refresh Counter
The refresh counter is used to sequentially refresh all of
Description
Pin #
Normal Function
Bl/0Pl
25
Bank (RAS) Select
XO/OP2
36
, Crystal OSCIllator (8202A-l or 8202A-3)
Option Function
Advanced-Read Mode (see text)
External Oscillator
Figure 4. 8202A Option Selection
,6-79
AFN01838A
8202A
Test Cycle
.
The TEST Cycle is used to check operation of several
8202A internal functions. TEST cycles are requested
by'activating the RD and WR inputs, independent of
PCS. The TEST Cycle will reset the refresh address
counter. It will perform a WRITE Cycle if PCS is low.
The TEST Cycle should not be used in normal system
operation, since it would affect the dynamic RAM
refresh.
SO~
- - - - REFRO
-'.
-
8202A
SACK or
CAS
Refresh Cycles
Figure 5.
The 8202A has two ways of providing dynamic RAM reo
fresh:
Hidden Refresh
Read Cycles
The 8202A can accept two different types of memory
Read requests:
1) Internal (failsafe) refresh
2) External (hidden) refresh
1) NormalRead, via the RD input
2) Advanced Read, using the 81 and ALE inputs
Both types of 8202A refresh cycles activate all of the RAS
outputs, while CAS, WE, SACK, and XACK remain inactive.
The user can select the desired Read request configuration via the Bl /OPl hardware strapping option on pin 25.
Internal refresh is generated by the on-Chip refresh timer.
The timer uses the 8202A clock to ensure that refresh of
all rows of the dynamic RAM occurs every 2 milliseconds.
If REFRQ is inactive, the refresh timer will request are·
fresh cycle every 10-16 microseconds.
,
Pin 25
Pin 32
Pin 34
# RAM banks
Ext. Refresh Req.
External refresh is requested via the REFRQ input (pin 34).
External refresh control is not available when the Advanced-Read mode is selected. External refresh requests
are latched, then synchronized to the 8202A clock.
Normal Read
Advanced Read
Bl input
RD input
REFRQ input
4 (RAS 0.3)
Yes
+12 Volt Option
SI input
ALE input
2 (RAS 2.3)
No
Figure 6. 8202A Read Options
The arbiter will allow the refresh request to start a refresh
cycle only if the 8202A is not in the middle of a cycle.
Normal Reads are requested by activating the RD input,
and keeping it active until the 8202A responds with an
XACK pulse. The RD input can go inactive as soon as the
command hold time (tCHS) is met.
Simultaneous memory request and external refresh request will result in the memory request being honored first.
This 8202A characteristic can be used to "hide" refresh
cycles during system operation. A circuit similar to
Figure 5 can be used to decode the CPU's instruction
fetch status to generate an external refresh request. The
refresh request is latched while the 8202A performs the
instruction fetch; the refresh cycle will start immediately
after the memory cycle is completed, even if the RD input
has not gone inactive. If the CPU's instruction decode time
is long enough, the 8202A cal'! complete the refresh cycle
before the next memory request is generated.
Advanced Read cycles are requested by pulsing ALE
while S 1 is active; if S 1 is inactive (low) ALE is ignored.
Advanced Read timing is similiar to Normal Read timing,
except the falling edge of ALE is used as the cycle start
reference.
If a Read cycle is requested while a refresh cycle is in
progress, then the 8202A will set the internal delayedSACK latch. When the Read cycle is eventually started,
the 8202A will delay the active SACK transition until XACK
goes active, as shown in the AC timing diagrams. This delay was designed to compensate for the CPU's READY
setup and hold times. The delayed-SACK latch is cleared
after every READ cycle.
Certain system configurations reqlJire complete external
refresh requests. If external refresh is requested faster
than the minimum internal refresh timer (tREF), then, in effect, all refresh cycles will be caused by the external reo
fresh request, and the internal refresh timer will never
generate a refresh request.
Based o~ syst~m requirements, eith~r SACK or XACK can
be used to ge1terate the CPU READY signal. XACK will
6-80
AFN Ot838A
8202A
A microprocessor system is concerned with the time data
is valid after RD goes low. See Figure 7. In order to calculate memory read access times, the dynamic RAM's A.C.
specifications must be examined, especially the RAS-access time (tRAC) and the CAS-access time (tCAc). Most
configurations will be CAS-access limited; i.e., the data
from the RAM will be stable tcc,max (8202A) + tCAC
(RAM) after a memory read cycle is started. Be sure to
add any delays (due to buffers, data latches, etc.) to calculate the overall read access time.
normally be used; if the CPU can tolerate an advanced
READY, then SACK can be used, but only if the CPU can
tolerate the amount of advance provided by SACK. If
SACK arrives too early to provide the appropriate number
of WAIT states, then either XACK or a delayed form of
SACK should be used.
Write Cycles
Write cycles are similiar to Normal Read cycles, except
for the WE output. WE is held inactive for Read cycles, but
goes active for Write cycles. All 8202A Write cycles are
"early-write" cycles; WE goes active before CAS goes active by an amount of time sufficient to keep the dynamic
RAM output buffers turned off.
Since the 8202A normally performs "early-write" cycles,
the data must be stable at the RAM data inputs by the time
CAS goes active, including the RAM's data setup time. If
the system does not normally guarantee sufficient write
data setup, you must either delay the WR input signal or
delay the 8202A WE output.
General System Considerations
All memory requests (Normal Reads, Advanced Reads,
Writes) are qualified by the PCS input. PCS should be stable, either active or inactive, prior to the leading edge of
RD, WR, or ALE. Systems which use battery backup
should pullup PCS to prevent erroneous memory requests,
and should also pullup WR to keep the 8202A out of its
test mode.
Delaying the WR input will delay all 8202A timing, including
the READY handshake signals, SACK and XACK, which
may increase the number of WAIT states generated by the
CPU.
If the WE output is externally delayed beyond the CAS active transition, then the RAM will use the falling edge of WE
to strobe the write data into the RAM. This WE transition
should not occur too late during the CAS active transition,
or else the WE to CAS requirements of the RAM will not be
met.
In order to minimize propagation delay, the 8202A uses an
inverting address multiplexer without latches. The system
must provide adequate address setup and hold times to
guarantee RAS and CAS setup and hold times for the
RAM. The 8202A tAD AC parameter should b~ used for
this system calculation.
The BO-B 1 inputs are similiar to the address inputs in that
they are not latched. BO and B 1 should not be changed
during a memory cycle, since they directly control which
RAS output is activated.
AD
~,---------:-~I
I
I
.:
.~--tRLDV
B-
1--:
DATA------1(
The 8202A uses a two-stage synchronizer for the memory
request inputs (RD, WR, ALE), and a separate two stage
synchronizer for the external refresh input (REFRQ). As
with any synchronizer, there is always a finite probability
of metastable states inducing system errors. The 8202A
synchronizer was designed to have a system error rate
less than 1 memory cycle every three years based on the
full operating range of the 8202A.
I
:
"----tRAC~
I
I
i /
RAS - - - " " " " ' ' (
I
I
tCAC
I
'----+t
-----------. I
CAS'"
I
!/
r-
Figure 7. Read Access Time
6-81
AFN 01838A
inter
8202A
2118
DYNAMIC RAM ARRAY
.
AS-1S
ALE
8088
~~
8282
ALO_6
QUTO-6
AHa-6
80-1
8202A
(16K MODE)
ADO-7
RD
WR
,..--
,
t-p
WE
CAS
~
WE
WR
RAS,
-<
AO •
I----
RASa
RD/S,
r
RAS2
SACK
RAS3
~
~
XACK
~
f----
~
BAL
I
CAS
MS
DIN DOUT
1
AO-6
WE
CAS
RAS
I---
DIN DOUl
it 1
AO-.
L-,\
~
I ~S';;- It~DATA BUS
DATA
LATCH IN
II
C=:::
TT.
AO-6
WE
CAS
RAS
DIN DOUT
D'N
DOUT
D'N
DOUT
~.
-- --
J
+
+
--'
-
J
I
I
!
D'N
n:
DOUT
D'N
,ID'NDour
DIN
DOUT
J j
!
---
!\
-
D'N
DOUT
.13
.
l' T
'----
-
CAS
f--oRAli
DIN OOUT
~
:u
1
f---oWE
I----
o,N
DOUT
o,N
DouT
oOUT
Dour
.--
1
I]
Figure 8. Typical 8088 System
6-82
AFN01838A
8202A
ABSOLUTE MAXIMUM RATINGS'
'NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for. extended periods may affect device reliability.
Ambient Temperature Under Bias ............ O°C to 70°C
Storage Temperature ................ -65°C to +150°C
Voltage On any Pin'
With Respect to Ground ................ -0.5V to +7V4
Power Dissipation . . . . . . . . .
. ............ 1.5 Watts
D.C. CHARACTERISTICS
TA
= ooe to 70oe; VCC = ·5.0V
Min
± 10%, VCC
= 5.0V ±
Symbol
Parameter
Vc
Input Clamp Voltage
-1.0
V
ICC
Power Supply Current
270
mA
IF
Forward Input Current
ClK
All Other Inputs 3
-2.0
-320
IR
Reverse Input Current 3
VOL
Output low Voltage
SACK,XACK
All Other Outputs
VOH
Output High Voltage
SACK,XACK
All Other Outputs
Vil
Input low Voltage
VIHl
Input High Voltage
VIH2
Option Voltage
CIN
Input Capacitance
Max
Units
5% for 8202A-3, GND
IC
= -5mA
mA
/lA
VF
VF
= 0.45V
= 0.45V
40
/lA
VR
=Vee (Note 1)
0.45
0.45
V
V
V
V
2.4
2.6
0.8
2.0
V
V
30
= OV
Test Conditions
= 5 mA
= 3 mA
Vil = 0.65V •
10H = -1 mA
'IOH = -1 mA
VCC = 5.0V (Note 2)
VCC = 5.0V
10l
10l
V
(Note 4)
pF
F = 1 MHz
VBIAS = 2.5V, VCC
TA = 25°C
= 5V
NOTES:
1
2.
3.
4
IR = 200l'A for Pin 37 (eLK) for exlernal clock mode
For lesl mode RD & WR musl be held al GND.
Excepl for pin :t6.
8202A-l and 8202A-3 supports bolh OP, and OP 2. 8202A only supports OP 2
+12 Volt
' K
36
±10%
OP2
8202A
5.1 K
25
OP,
Resistor Tolerance ±5%
6-83
AFN 01838A
·S202A
A.C. CHARACTERISTICS
TA = O°C to 70°C, Vee
= 5V
± 10%, Vee = 5V ± 5% for 8202A-3
Measurements made with respect to RASO-RAS3, CAS, WE,OUTO-OUTS are at 2.4V and 0.8V. All
other pins are measured at 1 5V All times are in nsec
'
Symbol
Parameter
Min
Max
tp
Clock Period
40
54
20
tpH
External Clock High Time
tpL
External Clock Low Time-above (» 20 mHz
17
tpL
External Clock Low Time-below
«) 20 mHz
20
tRC
Memory Cycle Time
IREF
Refresh Time (128 cycles-16K mode)
lotp - 30
12tp
264tp
288tp
Notes
4,5
tRP
RAS Precharge Time
4tp - 30
tRSH
RAS Hold After CAS
5tp - 30
3
tASR
Address Setup to RAS
tp - 30
3
tRAH
Address Hold From RAS
tp - 10
3
tASC
Address Setup to CAS
tp - 30
3
ICAH
Address Hold from CAS
5tp - 20
3
tCAS
CAS Pulse Width
Sip - 10
twcs
WE Setup to CAS
tp - 40
tWCH
WE Hold After CAS
5tp - 35
tRS
RD, WR, ALE, REFRO delay from RAS
IMRP
RD, WR setup 10 RAS
IRMS
REFRO selup 10 RD, WR
21p
0
tRMP
REFRO selup to RAS
21p
tpcs
PCS Setup to RD, WR, ALE
20
tAL
S 1 Setup to ALE
15
tLA
S 1 Hold from ALE
30
+ 30
+ 25
tCR
RD, WR, ALE to RAS Delay
tp
tcc
RD, WR, ALE 10 CAS Delay
3tp
tsc
CMD Setup 10 Clock
15
tMRS
RD, WR setup to REFRO
5
tCA
RD, WR, ALE to SACK Delay
tcx
CAS to XACK Delay
5tp - 25
tcs
CAS to SACK Delay
5tp - 25
tACK
XACK to CAS Setup
10
txw
XACK Pulse W,idth
ICK
SACK, XACK turn-off Delay
CMD Inactive Hold after SACK, XACK
10
20
30
REFRO to RAS Delay
tww
WR tp WE Delay
tAD
CPU Address Delay
2tp
4tp
+ 70
+ 85
2
2
1
+ 47
+ 20
5tp + 40
2,9
5tp
2,10
7
35
REFRO Pulse Width
CMD Hold Time
5
tp - 25
tLL
tCHS
5
2tp
tKCH
tRFR
8
Sip
11
+ 100
6
0
50
8
0
40
3
4tp
6-84
AFN 01838A
inter
8202A
WAVEFORMS
Normal Read or Write Cycle
Fffi,WR
Advanced Read Mode
ALE
tee
-MAX
-tCA-
6-85
AFN 0183BA
8202A
WAVEFORMS (cont'd)
Memory Compatibility Timing
~ ~~
VA_L_"D_A_D _~E_S_S
______________
~~ ~
__________________
-~?&~
__
________________________
-::'R-
\
'I
tRSH
1
tCAS
V
1\
-'RAH-
I--'ASR-
~
I--'ASC-OO
X
ROW
_'CAH_
K
COLUMN
Write Cycle Timing
\
J
\
/
.1
-~c~--2I\
MIN
t.
-
...--~c,.~---..
/
\
.
.
--'wcstec
MIN
tWCH
.,
.
tww
-
J
·CC
MAX
6-86
AFN 0183BA
inter
8202A
WAVEFORMS (cont'd)
Read or Write Followed By External Refresh
RD, WR
\
~
....-.tMRS~ ~tLL'--"
REFRQ
/
V
\
.
~
IRMP
tCR
I - t o s - - - - - MAX
------
-tRP-
\
.
.
.
tRe
"-
.\
.1
~
tcc
MIN
tee
MAX
External Refresh Followed By Read or Write
_tRMS ---1----.. REFRQ
1+------ tRe -----~
\---
6-87
AFN 01838A
intJ
8202A
WAVEFORMS (cont'd)
Clock And System Timing
ClK
RD, WR,ALE
Table 2 8202A Output Test
Loading.
A.C. TESTING LOAD CIRCU.IT
Test Load
Pin
SACK.XACK
OUTO-OUTs
RASo-RAS3
...
WE
CAS
CL = 30 pF
CL
ISO pF
CL
SO pF
CL;
224 pF
CL
320 pF
DEVICE
UNDER
TEST
=
=
=
=
'Icc
NOTES:
1. tsc is a reference point only. ALE. RD. WR. and REFRQ inputs do
not have to be externally synchronized to 8202A clock.
2. If .tRS min and tMRS min are met then. tCA. tCR. and tcc are
valid. otherwise tcs is valid.
3. tASR. tRAH. tASC. tCAH. and tRSH depend upon BO-Bl and CPU
address remaining stable throughout the memory cycle. The ad·
dress inputs are not latched by the 8202A.
4. For back·to·back refresh cycles. tRC max = 13tp
5. tRC max is valid only If tRMP min is met (READ. WRITE followed
by REFRESH) or tMRP min is met (REFRESH followed by READ.
WRITE).
6. tRFR is valid only if tRS min and iRMS min are met
7. txw min applies when RD. WR has already gone high. Otherwise
XACK tollows RD. WR.
8. WE goes high accQrding to tWCH or tWW. whichey-er occurs
CL INCLUDES JIG CAPACITANCE
9. tCA applies only when in normal SACK mode.
10. tcs applies only when in delayed SACK mode.
11. tCHS must be met only to ensure a SACK active pulse when in
delayed SACK mode. XACK will always be activated for at
least txw (tp- 25 nS). Violatong tCHS min does not otherwise
affect device operatIon.
first.
6-88
AFN 01836A
inter
8202A
The typiCliI rising and falling characteristic curves .for the
OUT, RAS. CAS and WE output buffers can be used to
determine the .effects of capacitive loading on the A.C.
Timing Parameters. 4sing this design tool in conjunction
with the timing, waveforms. the designer can !=letermine
typical timing shifts based on system capacitive load.
A.C. CHARACTERISTICS FOR DIFFERENT CAPACITIVE LOADS
ur-----,_-----+------r_----~----,_----_r----_;r_----~--~~=r====:~~
u~----~----i------L-----L
Ur-____- r______~-----r----~
____
_ L_ _ _ __ i_ _ _ _~_ _ _ _~~_ _ _ _~--~
5_-/
__----~----~------T_----_r----~~~M~c~n~~~Nc~E~:~;
NOTE:
Use the Test Load as the base capacitance for astlmating timing
shilts for system critical timing parameters.
'
MEASUREMENT CONDITION.:
Pin.! not measured are loaded with the
TA = 25"C
Vee": +5V
tp = 50 ns
Test Load capacitance.
AFN..()1838A
inter
8202A
Example: Find the effect on teR and tee using 84
2118 Dynaml~ RANIs cC?nflgured in 4 banks.
1. Determine the typical RAS and CAS capacitance:
From the data sheet RAS = 4 pF and CAS = 4 pF.
:. RAS load = 64 pF + board capacitance. .
CAS load = 256 pF + board capacitance.
Assume 2 pF/ln (trace length) for board
capacitance.
:
\
2. From the waveform diagrams, we determine that
the fallin~ edge timing is needed for teR and tee.
Next find the curve that best approldmates the
test load; I.e., 68 pF for RAS and 330 pF for CAS.
'teR
3. If we use 72 pF for RAS loading, then the
(max.) spec should be increased by about 1 ns.
Similarly If we use 288 pF for CAS, then tee (min.)
and (max.) should decrease about 1 ns.
AFN-ll1838A
6-90
8203
64K DYNAMIC RAM CONTROLLER
• Provides All Signals Necessary to
Control 64K (2164) and 16K (2117,2118)
Dynamic Memories
• Fully Compatible with Intel(§) 8080A,
808SA, iAPX 88, and IAPX 86 Family Microprocessors
• Directly Addresses and Drives Up to 64
Devices Without External Drivers
• Decodes CPU Status for Advanced Read
capability In 16K mode with the 8203-1 and
the 8203-3.
• Provides Address Multiplexing and
Strobes
• Provides System Acknowledge and Transfer Acknowledge Signals
• Provides a Refresh Timer and a Refresh
Counter
• Refresh Cycles May be Internally or Externally Requested (For Transpar~nt Refresh)
• Provides Refresh/Access Arbitration
• Internal Series Damping Resistors on All
RAM Outputs
• Internal Clock Capability with the 8203-1
and the 8203-3
The Intel® 8203 is a Dynamic Ram System Controller designed to provide all signals necessary to use 2164, 2118
or 2117 Dynamic RAMs in microcomputer systems. The 8203 provides multiplexed addresses and address
strobes, refresh logic, refresh/access arqitration. Refresh cycles can be started internally or externally. The
8203-1 and the 8203-3 support an internal crystal oscillator and Advanced Read Capability. The 8203-3 is a ±5% Vee
'
part.
....
&i'fo-&ii'7
AH3
AM.
AH,
-...
.
.
,
........
It/0f'1
c"""'
.......
-I
i l i / S 1 - -_ _ _
':=====1
,...
........"'"
CD
...
....
OUT•
AL,
OUT,
AL2
Wf.
ALa
M3
....
M4
""'"
Me
....
Figure 1. 8203 Block Diagram
Figure 2. Pin Configuration
Intel Corporation Assumes No Responslblhty for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product No Other Circuit Patent Licenses are Implied.
©INTELCORPORATION.1982
JULY 1982
6-91
ORDER NUMBER: 21044-002
inter
8203
Table 1.'Pin Descriptions
Symbol
Pin
No. Type Name and Function
ALO
ALI
AL2
AL3
A,L4
AL5
AL6
6
I
8
I
10 ' I
12
I
14
I
"
16
I
18
I
Address Low: CPU address inputs used to generate memory
row address.
AHO
AHI
AH2
AH3
AH4
AH5
~H6
5
4
3
2
1
39
38
I
I
I
I
I
I
I
Address High: CPU address inputs used to generate memory
column address.
Bo/ AL 7
Bl/ 0P l/
AH7
24
25
I
I
Bank Select Inputs: Used to
gate the appropriate RAS output
for a memory cycle. Bl/0Pl option used to select the Advanced
Read Mode. (Not available in
64K mode.) See Figure 5.
When in 64K RAM Mode, pins 24
and 25 operate as the AL 7 and
AH7 address inputs.
PCS
33
I
Protected Chip Select: Used to
enable the memory read and
write inputs, Once a cycle is
started, it will not abort even if
PCS goes inactive before cycle
completion.
Symbol
Pin
No. Type Name and Function
RASO
RASI
RAS2/
OUT7
RAS3/BO
21
22
23
0
0
0
Row Address Strobe: Used to
latch the Row Address into the
bank of dynamic RAMs. selected by the 8203 Bank Select pons
' (BO, Bl/0Pl)· In 64K mode,
only RASO and RASI are available; pin 23 operates as OUT 7
and pin 26 operate!! as the BO
bank select input.
26
I/O
XACK
29
0
Transfer Acknowledge: This
output is a strobe indicating valid data during a read cycle or
data written during a write cycle.
XACK can be used to latch valid
data from the RAM amw
SACK
30
0
System Acknowledge: This
output indicates the beginning of
a memory 'access cycle, It can
be used' as an advanced transfer acknowledge to eliminate
wait states. (Note: If a memory
access request is made during a
refresh cycle, SACK is delayed
until XACK in the memory access cycle).
XO/OP2
Xl/ CLK
36
37
I/O
I/O
Oscillator Inputs: These inputs
are designed for a quartz crystal
to control the frequency of the
oscillator. If XO/OP2 is shorted
to pin 40 (VCC) or if XO/OP2 is
connected to + 12V through a
1K{l resistor then XI/ CLK becomes a TTL input for an external clock. (Note: Crystal mode
for the 8203-1 and the 8203-3
only).
I
Mode Select: This input selects
16K mode (2117, 2118) or 64K
mode (2164). Pins 23-26
change function based on the
mode of operation.
WR
31
I
Memory Write Request.
RD/Sl
32
I
Memory Read Request: S 1
function used in Advanced Read
mode selected by OPI (pin 25).
REFRQ/
ALE
34
I
External Refresh Request: ALE
function used in Advanced Read
mode, selected by OPI (pin 25).
16K/64K
35
OUTO
OUTI
OUT2
OUT3
OUT4
OUT5
OUT6
7
9
11
13
15
17
19
0
0
0
0
0
0
0
Output of the Multiplexer:
These outputs are designed to
drive the addresses of the Dynamic RAM array. (Note that the
OUTO-7 pins do not require in,verters or drivers for proper operation.)
VCC
40
Power Supply: +5V.
GND
20
Ground.
WE
28
0
Write Enable: Drivea the Write
Enable inputs of the Dynamic
RAM array.
CAS
I
27
0
Functional Description
The 8203 provides a complete dynamic RAM controller for microprocessor systems as well as expansion
memory boards. All of the necessary control signals.
are provided for 2164,2118 and 2117 dynamic RAMs.
Column Address Strobe: This
output is used to latch tha Column Address into the Dynamic
RAM array.
The 8203 has two modes, one for 16K dynamic RAMs
and one for 64Ks, controlled by pin 35.
6-92
AFN-02144B
8203
Other Option Selections
,--
I
cs*
I
I
1_-
Cili
C
1KU
.5%
X,
Cs..L.
T
I
8801l
':"
±5'"
iiiIo
82OG-'
or
82OG-3
...I
!iii,
mz
!iii3
':"
cs <
The 8203 has three strapping options. When OP1 is sa-.
Iected (16K mode only), pin 32 changes from a RD input to
an S1 input, and pin 34 changes from a REFRQ input to an
ALE input. See "Refresh Cycles· and "Read Cycles· for
more detail. OP1 Is selected by tying pin 25 to +12V
through a 5.1 K ohm resistor on the 8203-1 or 8203-3
only.
WE
>Co
im(
'OpF
FUNDAMENTAL XTAL
When OP2 is selected, the internal oscillator is disabled
and pin 37 changes from crystal input (X 1) to a ClK
input for an external TTL clock. OP2 is selected by shorting pin 36 (XO/OP2) directly to pin 40 (Vcc). No current
limiting resistor should be used. OP2 may also be selected
by tying pin 36 to +12V through a 1Kn resistor.
a:
iAl:K
Figure 3. Crystal Operation for the 8203-1 and
8203-3
All 8203 timing is generated from a single reference clock.
This clock is provided via an external oscillator or an onchip crystal oscillator. All output signal transitions are synchronous with respect to this clock reference, except for
the trailing edges of the CPU handshake signals SACK and
XACK.
Refresh Timer
The refresh timer is used to monitor the time since the last
refresh cycle occurred. When the appropriate amount of
time has eiapsed, the refresh tjmer will request a refr~sh
cycle. External refresh requests will reset the refresh
timer.
CPU memory requests normally use tl1e RD and WR inputs. The Advanced-Read mode allows ALE and S 1 to be
used in place of the RD input.
Refresh Counter
The refresh counter is used to sequentially refresh all of
the memory's rows. The 8-bit co,unter is incremented after
every refresh cycle.
Failsafe refresh is provided via an internal timer which generates refresh requests. Refresh requests can also be
generated via the REFRQ input.
An
on-chip synchronizer I arbiter prevents memory and refresh requests from affecting a cycle in progress. The
READ, WRITE, and external REFRESH requests may be
asynchronous to the 8203 clock; on-chip logic wHI synchronize the requests, and the arbiter will decide if the requests should be delayed, pending 'completion of a cycle in
progress.
Pin
tt
23
24
25
26
16K Function
64K Function
RAS2
Bank Select (BO)
Bank Select (B 1)
RAS3
Address Output (OUT7)
Address Input (AL7)
Address Input (AH7)
Bank Select (BO)
Figure 4. 16K/64K Mode Selection
16K/64K Option Selection
Outputs
Inputs
Pin 35 is a strap input that controls the two 8203 modes.
Figure 4 shows the .fdur pins that are multiplexed., In 16K
mode (pin 35 tied to Vee or left open), .the 8203 has tWo
Bank Select inputs to select one of four RAS outputs. In
this mode,_the 8203 is exactly compatible with the Intel
8202A Dynamic RAM Controller. In 64K mode (pin 35 tied
to GND), there is only one Bank Select input (pin '26) to
select the two RAS outputs. More than two banks of 64K
c;lynamic RAM's can be used with external logic.
16K
M,ode
64K
Mode
B1
BO
RA§o
m1 m2RA§s
0
0
1
0
I'
0
1
0
1
1
1
1
0
1
1
-
0
1
0
1
1
0
1
1
1
0
1
1
1
1
0
-
-
-
Figure 5. Bank Selection
D~scriptlon
Pin #
Normal Function
Option Function
Bl IOPl (16K only)1 AH7
25
Bank (RAS) Select
Advanced-Read Mode (8203-1. -3)
XO/OP2
36
Crystal Oscillator (8203·1 •and 8203-3)
External Oscillator
Figure 6. 8203 Option Selection
6-93
AFN·02,44B
8203
Address Multiplexer
Refresh Cycles
The address multiplexer takes the address inputs and·the
refresh counter outputs, and gates them onto the address
outputs at the appropriate time. The address outputs, in
conjunction with the RAS and CAS outputs, determine the
address used by the dynamic RAMs for read, write, and
refresh cycles. During the first part of a read or write cycle, ALO-AL7 are gated to OUTO-OUT7, then AHO-AH7
are gated to the address outputs.
The 8293 has two ways of providing dynamic RAM
refresh: .
,
1) Internal (failsafe) refresh
2) External (hidden) refresh
Both types of 8203 refresh cycles activate all of the RAS
outputs, while CAS, WE, SACK, and XACK remain
inactive.
During' a refre.sh cycle, the refresh counter is gated onto
the address outputs. All. refresh cycles are RAS-only refresh (CAS inactiv!,!, RAS active).
Internal refresh is generated by the on-chip refresh timer.
The timer uses the 8203 clock to ensure that refresh of all
rows of the dynamic RAM occurs every 2, milliseconds
(128 cycles) or every 4 milliseconds (256 cycles). If
REFRQ is inactive, the refresh timer will request a refresh
cycle every 10-16 microseconds:
To minimiie buffer delay, the information on the address
outputs is inverted from that on the address inputs.
OUTO-OUT7 do not need inverters or buffers unless addi,
tional drive is required.
External refresh is requested via the REFRQ input (pin 34).
External refresh control is not available when the Advanced-Read mode is selected. External refresh requests
are latched, then synchronized to the 8203 clock.
Synchronizer / Arbiter
The 8203 has three inputs, REFRQI ALE (pin 34), RD (pin
32) and WR (pin 31). The RD and wFi inputs allow an external CPU to request a memory read or write cycle, respectively. The REFRQ I ALE input allows refresh requests
to be requested external to the 8203.
The arbiter will allow the refresh request to start a refresh
cycle only if the 8203 is not in the ~iddle of a cycle ..
When the 8203 is in the idle state a simultaneous memory
request and external refresh request will result in the memory request being honored first. This 8203 characteristic
can be used to "hide" refresh cycles during system operation. A circuit similar to Figure 7 can be used to, decode
tne CPU's instruction fetch status to generate an external
refresn request. The refresh request is latched while the
8203 performs the instruction fetch; the refresh cycle will
start immediately after the memory cycle is completed,
even if tlie RD input has not gone inactive. If the CPU's
instruction decode time is lorig enough, the 8203 can complete the refresh cycle before the next memory request is
generated.
All three of these inputs may be asynchronous with respect to the 8203's clock. The arbiter will resolve conflicts
between refresh and memory requests, for both pending
cycles,and cycles in progress. Read, and write requests
will be given priority over refresh requests.
System Operation
The 8203 is always in one of the following states:
a)
b)
c)
d)
. e)
IDLE
TEST Cycle
REFRESH Cycle
READ Cycle
WRITE Cycle
If the 8203 is not in the idle state then a simultaneous memory request and an external refresh request may result in
the refresh request being honored first.
' ,
The 8203 is normally in the IDLE state. Whenever one of
the other cycles is requested, the 8203 will leave the IDLE
state to perform the desired cycle. If no other cycles are
pending, the 8~03 will return to the IDLE state.
'
Test Cycle
The TEST Cycle is. used to check operation of several
8203 internal functions. TEST cycies are requested by activating the PCS, RD and WR inputs. The TEST Cycle will
reset the refresh address counter and perform a WRITE
Cycle. The TEST Cycle should not be used in normal system operation, since it would atte'lt the dynamic RAM refresh.
Figure 7. Hidden Refresh
6-94
AFN-02144B
inter
8203
Certain system configurations require complete external
refresh requests. If external refresh is requested faster
than the minimum internal refresh timer (tREF), then, in effect, all refresh cycles will be caused by the external refresh request, and the internal refresh timer will never
generate a refresh request.
Read Cycles
The 8203 can accept two different types of memory Read
re"
AHO-6
AO-S
+
+
+
80-1
82C03
(16K MODE)
~
f---.
WE
CAS
~
RD/S,
RASa
1
WR
RAS,
-1
WE
CAS
RAS
DIN DOUT
RAS2
SACK
g::-
RAS3
XACK
~
~
f---.
~
AO-6
WE
CAS
RAS
n
-
e---.
~
~A
DATA BUS
DATA
LATCH IN
~
----I:
AO-6
CAS
n
RAS
AO-6
DIN
Dour
1" "T
V
r'\.
Ll
D'N
DOUT
1
D'N
~
1...1
, BAL
WE
CAS
RAS
DOUT
-
DIN DOUT
_WE
_
D'N
D'N
DOUT
!
DIN
DT
DtN
,I
1
DOUT
DtN
D'N
Dour
D'N
DoUT
DoUT
~T
1
~
'---
\
Figure 10. Typical 8088 System
6-111
AFIIo02144B
infel"
82C03
MULTIBUS"
TYPE
I.
82ea8
82C84A
READ
1
WRITE
SYSTEM
aus
MRDe
MWTC
READ
1
~
WRITE
-
•
CMOS
[-£ :'-
82C86
HIGH BYTE
BHEN
WRITE
ADRO
1 "'lRI
OTHER
AEADY
INPUTS
ADO-AD15
A17-A 19
I ADRF
A16-A19
aHE
1
1
1
00-15
51eM
"OK
BYTES
I
DATA
DI
16
DATA
00-15
Figure 11. 80C86/256K Byte System '
6-112
AFN.Q2144B
82C03
ABSOLUTE MAXIMUM RATINGS'
Ambient Temperature Under Bias. . .
Storage Temperature "
Voltage On any Pm
With Respect to Ground
Power Dissipation ..
.O°C to 70°C
-65°C to +150°C
.. -0.5V to + 7V4
. ... 0.2 watts
'NOTE: Stresses above those listed under "Absolute MaxImum Ratings" may cause permanent damage to the deVice.
This is a stress rating only and functional operation of the deVice at these or any other conditions above those mdicated m
the operational sections of this specification IS not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
-
D.C. CHARACTERISTICS
TA = O°C to 70°C' VCC = 50V ± 10%' GND - OV
Min
Symbol
Parameter
Vc
Input Clamp Voltage
Max
Units
-1.0
V
ICC
Power Supply Current
25
mA
III
Input Leakage Current
±10
/lA
VOL
Output Low Voltage
SACK,XACK
All Other Outputs
0.45
0.45
'V
V
Output High Voltage
SACK,XACK
All Other Outputs
VOH
VIL
Input Low Voltage
VIHI
Input High Voltage
VIH2
Option Voltage
2.4
2.6
Y
V
2.0
0.8
V
VCC
V
VCC
V
Test Conditions
IC = -5 mA
VSS::5 VIN::5 Vee
IOL=5mA
10L = 3 mA
10H = -1 mA
IOH=-lmA
(Note 4)
F=;IMHz
Input Capacitance
CIN
30
pF
VBIAS = 2.5V, VCC = 5V
TA - 25°C
NOTES:
1. For test mode RD & WR must be held at GND.
2 Except for pin 36 in XT AL mode.
3
2.
5.1KU
+12 Volt
±10%
OPl
82C03
N.C.
\
~ 01':1
Reeiltor Toterance:
:!:
S%
&:113
AFt+«!l44B
82C03
A.C. CHARACTERISTICS
TJ = o·c to 70·C; VCC = 5V ± 10%; GND =
OV
Measurements made with respect to RASO-RAS3, CAS, WE, aUTO-aUTe are at 2.4V and O.BV. All
other pins are measured at 1.5V. All times are in nsec.
Symbol
Parameter
Min
Max
tp
Clock Penod
33
54
tpH
External Ctock High Time
15
tPL
External Ctock Low Time-above (» 20 mHz
15
Notes
l1tp - 20
l1tp + 20
273tp
288tp
tRC
Memory Cycle Time
tREF
Refresh Time (128 cycles)
4,5
tRP
RAS Precharge Time
4tp + 3
tRSH
RAS Hold After CAS
Stp - 30
3
tASR
Address Setup to RAS
tp - 25
3
tRAH
Address Hold From RAS
tp - 8
3
tASC
Address Setup 10 CAS
tp - 30
3
tCAH
Address Hold from CAS
5tp - 20
3
tCAS
CAS Pulse Width
Stp - 10
'WGS
WE Setup to CAS
tp - 40
tWCH
WE Hold After CAS
Stp - 35
8
'RS
RD, WR, ALE, REFRO delay from RAS
3tp
2,6
I
'MRP
RD, WR setup to RAS
-1tp
5
tRMS
REFRO setup 10 RD, WR
2tp
6
tRMP
REFRO setup to RAS
21p
5
tpcs
PCS Selup 10 RD, WR, ALE
20
'AL
S 1 Setup to ALE
15
tLA
S 1 Hold from ALE
30
'CR
RD, WR, ALE 10 RAS Delay
Ip
tcc
RD. WR, ALE 10 CAS Delay
3tp
tsc
CMD Setup to Clock
IS
1
'MRS
RD, WR setup to REFRO
5
2
'CA
RD,
1tp
21p
'CX
CAS 10 XACK Delay
Sip - 25
Sip
ICS
CAS 10 SACK Delay
Sip - 25
tACK
XACK 10 CAS Selup
10
IXW
XACK Pulse W,dlh
ICK
SACK, XACK lurn-off Delay
WR, ALE 10 SACK Delay
+ 30
+ 25
21p
+ 70
2
41p + 80
2
+ 47
+ 20
Sip + 40
2,9
2,10
tp - 25
7
35
tKCH
CMD Inaclive Hold after SACK, XACK
10
'LL
REFRO Pulse W,dlh
20
'CHS
CMD Hold Time
30
'RFR
REFRO to RAS Delay
'WW
WR to WE Delay
0
50
tAD
CPU Addre,ss Delay
0
35
tCOF
CAS'Turn-Off Delay
11
4tp
+
100
6
8
-
3
70
tPCH
PCS Hold From RD, WR, ALE
30
tRRH
80, 81 Hold From AAS
0
tBS
BO, Bl Setup to RD. WR, ALE
0
AF_,44B
82C03
WAVEFORMS
Normal Read or WrIte Cycle
iii, Wli
Advanced Read Mode
S, _ _ _ _ _
~{
tAL
-.LAJ-------------
ALE
6-115
AFN-02144B
WAVEFORMS (cont'd)
Memory Compatibility Timing
110-8,
'V
1\
~~
~~
VAUD_
.J~
-~-
J~
f-::II-
~taRH-
-
!\
I
ICAS
V
1\
~IASR-
~
!-IRAH'"
i-!!'8C-
~
ROW
!-1CAH_
COLWN
K
Write Cycle Timing
,
I
,/
1\
~
.. I
1-:liIl~
....--2,-.....
/
\
/
-
tww
MAX
-Ci
tww
'I
tWCH'
!-twcs_
tcc
MIN
~
,6-116
-
82C03
WAVEFORMS (cont'd)
Read or Write Followed By External Refresh
REFRQ
1---------- IIlMP ----------1---
-------------- ~c------------·I
I.-------~~--------·~
I.--------~~l--------~------J
External Refresh Followed By Read or Write
---~--REFRQ
\'----
6-117
82C03
WAVEFORMS (cont'd)
Clock And System Timing
Table 2.
82C03 Ouptut Loading.
All specifications are for
the Test Load unless
otherwise noted.
Pin
Test Load
SACK,XACK
QUTo-OUTS
RASo-RAS3
~
CAS
CL=30pF
CL = lS0 pF
CL=SOpF
CL = 224 pF
CL = 320 pF
A.C. TESTING LOAD CIRCUIT
DEVICE
UNDER
TEST
NOTES:
1, tsc is a reference point only, ALE. RD. WR. and REFRQ inputs
do not have to be externally synchronized to 82C03 clock
2, If tRS min and tMRS min are met then tCA' tCR' and tcc are
valid. T CS is valid when delayed SACK is generated,
NOTE:
CL includes Jig capacitance
3, tASR' tRAH' tASC' tCAH. depend upon CPU address remaining
stable throughout the memory cycle, The address inputs are not
latched by the 82C03,
4, For back-to-back refresh cycles. tRC max = 12tp
5, \RC max ;. valid only if tRMP min is met (READ. WRITE followed
by REFRESH) or tMRP min is met (REFRESH followed by READ.
WR!TE),
6, tRFR is valid only if tRS min and tRMS min are met.
7, txw min applies when RD. WR has already gone high, Otherwise
XACK follows RD. WR,
8, WE goes high according to tWCH or tWW. whichever occurs
first.
6-118
AFN-021448
intJ
8206/8206-2
ERROR DETECTION AND CORRECTION UNIT
• Separate Input and Output
Busses-No Timing Strobes Required
• Detects and Corrects All Single Bit
Errors
• Detects All Double Bit and Most
Multiple Bit Errors
• Expandable to Handle 80 Bit Memories
• Supports Reads With and Without
Correction, Writes, Partial (Byte)
Writes, and Read-Modlfy-Wrltes
• 52 ns Maximum for Detection; 67 ns
Maximum for Correction (16 Bit
System)
• Syndrome Outputs for Error Logging
• HMOS Technology for Low Power
• 68 Pin Leadless JEDEC Package
• Single +5V Supply
• 8206-2 Timing OpUmlzed for 8MHz' IAPX
186, 188, 86, 88 and 8207-2 Systems
The HMOS 8206 Error Detection and Correction Unit is a high-speed device that provides error detection and
correction for memory systems (static and' dynamic) requiring high reliability and performance. Each 8206
handles 8 or 16 data bits and up to 8 check bits. 8206's can be cascaded to provide correction and detection for
up to 80 bits of data. Other 8206 features Include the ability to handle byte writes, memory initialization, and
error logging.
01 0 _15
DATAIN
LATCH
,.
L
Tit
tb
•
5Ta
CB1/SV1 0_7
U
pos,.,
READ
PARTIAL PARITY
C;ENERATOR
CE
t
CHECK BIT
LATCH
SYNDROMEI
.--/-
PPllPaS/NSL
PARTIAL PARITV
GENERATOR
•
V
I
4
POSo.,
NSLo-,
:(: SYNDROME
LATCH
I
t
-L-
CHECKSITI
SYO/CBO/PPOO_7
ERR
,
SYNDROME
t;
~
DECODER
AND
ERROR
DETECTION
,I t
U·'
WRITE
'll{
,.
---
l
. 'DIble 5. Modified Hamming Code Check 81t Generation
Check bits are generated by XOR'ing (except for the CBO and CB1 data bits, which are XNOR'ed in the Master) the data
bits in the rows corresponding to the check bits. Note there are 6 check bits,in a 16-bit system, 7 in a 32-bit system, and
8 in 48-or-more-bit systems.
'
BYTE NUMBER
BIT NUMBER
eso =
CB1 =
CHECK CB2 =
CB3 =
CB4';'
BITS
CB5 =
CB6=
CBi' =
DATA BITS
o1
1
0
OPERATION
234 567 01234567
xx'-x-xxx-x-~x-x
x--x-x--
- x .. x x .. x ..
- x x - x - x x --x·x--x
x-x x x x ...... x x x - - - - -
- - - x x x x x -----xxx
x x x x Xx x x
----"'--.. .. .. .. .. .. .. .. .. .. .. .. ... .. .. ..
.. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
o0 0 0 0 0 0 0 o 0 1 1 1 1 1 1
o 1 2 3 4 5 6 7 890.12345
0)
.!.
XNOR
XNOR
XOR
XOR
XOR
XOR
XOR
XOR
o1
2
2 3 4 5 6 7
BYTE NUMBER
BIT NUMBER
CBO =
CBl =
'CHECK CB2 =
CB3 =
BITS
CB4 =
CB5 =
CB6 =
CB7=
DATA BITS
3
OPERATION
2 3 4 5 6 7
- x x x - x x - -xx--x-XOR
xxx--x-x x x - - - - - x
XOR
.. x x x .. x x x - - x x - - - - '. XOR
xx--x-xx x - - x x - - XOR
.xx--xxxx - - - - x - x XOR
- - - it x X x x - - - - - x x x
XOR
.. .. .. .. .. .. .. .. x x x x x x x x
XOR
.. .. .. .. .. .. .. ... .. . .. .. .. .. ... ..
XOR
I
1 1 1 1 222 2 2 222 2 2 3 3
67890123 45678901
---
16 BIT OR MASTER
~
o1
SLAVE #1
!
5
6
7
4
8
9
OPERATION
01234567 o 1 2 3 4 56 7 o 1 2 3 4 5 6 7 o 1 2 3 4 5 6 7 o 1 2 3 4 5 6 7 o 1 2 3 4 5 6 7
x x .. x .. x x ~ x - - x - x - x - x - x x - - x - x x - - x - - x.x x - x x - - x x - - x XOR
- x x x x x XOR
- x - .. x i x .. x x x - - x x x - x - - x - x - x - x x - x - - x x -
-
- x x - x - x x --x-x- - x
x x x x x - - - x x x - - - - - - .. x x x x x .. - - - .. x x x
x x x x x x x x - ----x x x x x x x x - ----- - - - - - - x x X,x x x.x.x
--
-
-
-
- x x x - x x - - x x - - x - - x - - x - x
x - x - - x x - x x - - x x - --xxxx- - .. x x x x x - - - - - x x x - x x - - - - - - - - - - x x x x x x x x x - x x x x
x x x x x x x x - - - - - - - - x x - - x x
- - - - - - - -xxxxxxxx- - - - - -
x
x
x
x
x
x
x
--
- x x - x x - - x
x x x - - - - x ---- x
x x x x x
---
x - x
- - - x -- x
- x x x x
333 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 555 5 6 6 6 6 6 6 6 6 6 6 7 7 777 7 7 7 7 7
4 5 6 7 8 901 2 3 4 5 6 789
2345678 9 o 1.2 3 4 5 6 7 8 9-0 1 2 3 4 5 67890123
._-----SLAVE #2
I I'
SLAVE #3
II
SLAVE #4
XOR
XOR
XOR
XOR
XOR
XOR
'@
aID
IiiiiJ
IF'
=
~
=
i
~
~
~
inter
8206/8206-2
'DIble 6. 8206 Syndrome Decoding
Syndrome
B1t8
5
8
0
0
0 ,,0
0
1
1
0
1
o·
1
0
1
1
1
1
0
0
0
0
0
1
1
0
1
0
1
0
1
1
1
1
7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
l'
0
1
2
3
1
0
0
0
0
0
0
0
CBO CBl
0
0
0
0
13 14
0
0
62 55
29 31
0
0
0
0
45 46
59 " 75
0
0
N
CB4
CB5
0
CB6
0
0
30
CB7
0
0
63
0
78
U
0
1
1
0
0
0
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
0
0
1
1
0
0
1
0
1
0
1
1
1
0
1
0
0
1
1
1
0
1
1
0
1
1
1
0
5
11
0
25
0
0
37
43
0
0
62
0
CB2
0
0
15
0
51
64
0
0
47
79
0
0
6
19
0
26
0
0
38
77
0
0
18
0
0
21
0
70
69
0
0
74
58
0
0
16
9
0
24
0
0
71
41
0
0
'0
2
0
0
23
0
54
34
0
0
u
u
56
0
0
0
u
0
4
10
0
27
0
0
36
42
0
0
61
0
1
0
0
22
0
53
33
0
0
73
U
0
0
u
u
0
u
u
0
0
U
u
u
u
u
0
0
CB3
0
0
20
0
28
68
0
0
72
60
0
76
0
0
0
3
8
0
49
0
0
35
40
0
0
u
0
7
12
0
49
0
0
39
44
0
0
U
0
u
u
u
u
0
0
u
u
0
0
0
0
U
0
0
u
u
0
0
u
0
u
u
0
1
0
0
u
u
0 .0
0
0
U
1I
'0
U
N = No Error
CBX = Error in Check Bit X
X = Error in Data Bit X
o = Double Bit Error
U = Uncorrectable Multi-Bit Error
DATA MEMORY
18 BITS
OE
....L
DI
U
0
0
86
0
65
32
0
0
u
BUS
T
C
V
R
CHECK BITS
7 BITS
DO
DI
== ~
T
,
DO/WDI
DI
STB
DI
11208
MASTER
"
MIll
Riiiro
~l
SY1o-e
~l
ERROR
SIGNALS
DO
DO/WDI
DI
PPO...
r-
~
:JW
liiio
11M,
U
0
I
--
CBI,
R/W
U
,
DO
PPI,
ft
0
0
57
0
18 BITS
PPl0-8
CONTROL {
UNES
U
U
DATA MEMORY
SYO/CBO CBI...
CIICT
U
The 8206 interface to a typical 32 bit memory system
is illustrated in Figure 5. For larger systems. the
partial parity bits from slaves two to four must be
x
~
17
87
0
50
0
0
SYSTEM ENVIRONMENT
{
32Brr
DATA
1
1
1
1
0
r-
rr-
wz
STB
11208
SLAVE
PO~
POS,
~f¢
NSLo
ff-
NSL1
MIS ~
R/W
PPls-7
Ir
r---+
mmJI
CliCf
no
11M,
J
ftIR:U
SVI7
CE
8-0
+5V'
I
Figure 5. 32·Blt 8206 System Interface
6-127
AFN-cJ20088
820618206-2
XOR'ed externally, which calls for one level of XOR',
gating for three 8206's and two lev,els for four or five
8206's.
RAM implementation using the 8206 and 8207. The
8206/8207 combination permits such features as automatic scrubbing (correcting errors in memory during refresh), extending RAS and .CAS timings for
Read-Modify-Writes in single memory cycles, and
automatic memory initialization upon reset. Together these two chips provide a complete dualport, error-corrected dynamic RAM subsystem.
I
The 8206 is designed for direct connection.to the Intel
8207 Advanced Dynamic RAM Controller. The' 8207
has the ability to perform dual port memory control,
and Figure 6 illustrates a 'highly integrated dual port
I
ACKa
ACKa
ADDR
AU
CD
CMDlPEA
CMDIPEB
1207
MUX
ADORa
ClK>---- ClK
MUX
CMDIPEA
ADORA
ACKA
ADRC
-
-
--,; ADDR
ACKA
r---v
P>-<
wz
-
'WE
CMDIPEa
DYNAMIC
RAM
32 BITS +
f----"
7 CHECK alTS
WE
cal DOICaO
01
th
PSEN
CE
ERROR
DaM
L
IIIW
PSEl
IL
F
ERLR SVOIDI/Cal
caD
IIJW
-
+5Y- STa
~
8208
CRCT MASTER
wz
BM
-
BVTE
MARK
DECODER
-
~r
SVI
01
PPO
f
STB
CRCT
f- +5Y
8206
SLAYE
W2
DOIWDI
QJ
lit:
"-
L)
PPI
BM
DOIWDI
Q
I-t>o- ~ r-
-
tl1
XCVR
PORTA
Figure 8. Dual
RD
STa
DEI
LATCH' ,
PORTa
Port RAM Subsystem with 820&18207 (32-1)" bus)
6-128
AFt«lIOO8B
,
intJ
8206/8206-2
'nIbie 7. 8206-2 Syndrome Decoding
Syndrome 0
Bits
1
5 4 3 2
0
0
0
0
0
0
N
1
0
0
0
1
0
CBO CB1
1
1
0
1
0
1
0
1
1
1
1
1
0 CB2 0
0
0
0
0
1
0
0
1
CB3
0
0
0
0
1
2
0
0
1
0
CB4
0
0
5
0
6
7
0
0
1
1
0
3
0
0
4
0
0
0
1
0
0
CBS
0
0
11
0
0
12
0
1
0
1
0
8
9
0
10
0
0
0
1
1
0
0
13
14
0
15
0
0
0
1
1
1
0
0
0
0
0
0
0
0
N=
CBX =
X=
0=
The' 8206-2 handles 8 or 16 bits of data. For 8 bit
8206-2 systems, the D1a-15, DOIWDIa-15 and BM1 inputs are grounded.
The 8206-2 is designed for direct connection to the
Intel 8207-2 Advanced Dynamic RAM Controller. The
8207-2 has the ability to perform dual port memory
control, and Figure 7 illustrates a highly integrated
iAPX 186 RAM implementation using the 8206-2 and
8207-2. The 8206-218207-2 combination permits such
features as automatic scrubbIng (correcting errors in
memory during refresh), extending RAS and CAS timings for Read-Modify-Writes in single memory cycles,
and automatic memory initialization upon reset.
Together these two chjps provide a complete dual-port,
error-corrected dynamic RAM subsystems.
No Error
Error in Check Bit X
Error in Oatll Bit X
Double Bit i:rror
OTHERW
INPUTS
eLK
iiCii A00-8 Wo-3
CASo-3
ARDVCLK
!lillmii-------I
CEi------,
,~------------------~~U
r-----------------~~
A/W
w.z
10188
IIlIii
iiiii5ili
Dlo-15
SYOJ
CBO~.
CBlc-1>
eIiCT
STB
+SV
figure 7. iAPX 186 RAM Correct Always Subsystem with the 8206-2 and the 8207-2
,
6-129
.
AFN-Q20091 B
8206/8206-2
ciously choosing the proper data word to
generate the desired check bits, through
the use of the 8206 Hamming code. To
read out the check bits it is first necessary
to fill the data memory with all zeros,
which may be done by activating WZ and
incrementing memory addresses with WE
to the check bits memory held inactive,
and then performing ordinary reads. The
check bits will then appear directly at the
SYO outputs, with bits CBO and CB1
inverted.
MEMORY BOARD TESTING
The 8206 lends itself to straightforward memory
board testing with a minimum of hardware overhead. The following is a description of four common
test modes and their implementation.
Mode O-Read and write with error correction.
Implementation: This mode is the normal
8206 operating mode.
Mode 1-Read and write data with error correction
disabled to allow test of data memory.
Implementation: This mode is performed
with CRCT deactivated.
Mode 2-Read and write check bits with error correction disabled to allow test of check bits
memory.
Implementation: Any pattern may be written into the check bits memory by judi-
Mode 3-Write data, without altering or writing
check bits, to allow the storage of bit
combinations to cause error correction
and d.etection.
Implementation: This mode is implemented by writing the desired word to
memory with WE to the check bits array
held inactive.
,!
6-130
AFN'()2009B
820618206-2
BOTTOM
is
f
TOP
~
I
t;
§~
li!
"
1
iu
II
i
u
18
zc.!
NOTE:
The 8206 and 8206-2 is packaged in a 68 pin JEDEC TYPE A hermetic chip carrier
Figure 8. 8206 and 8206-2 Pinout Diagram
6-131
AFN-02009B
8206/8206-2
"NOTE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ......... O"C to 70"C
Storage Temperature ............... -65°C to + 15O"C
Voltage On Any Pin
With Respect to Ground ............ -0.5V to + 7V
Power Dissipation .......................... 1.5 Watts
Q.C. CHARACTERISTICS
Symbol
Parameter
1
VIH
Min.
Power Supply Current
-Single 8206, 8206-2 or
Slave #1
-Master in Multi-Chip
or Slaves #2, 3, 4
Icc
VIL
(TA = O°C to 70"C, Vee = 5.0V ± 10%, Vss= GND)
1
Unit
270
rnA
230
rnA
Test Cc\ndltlons
Input Low Voltage
-0.5
0.8
V
Input High Voltage
2.0
Vee+
0.5V
V
0.45
0.45
V
V
10L = 8mA
10L =2.0mA
V
V
IoH = -2m A
IoH = -0.4mA
± 20
± 10
",A
0.45V .,; VI 10
± 20
± 10
",A
",A
VOL
Output Low Voltage
-DO
-All Others
VOH
Output High Voltage
-DO,CBO
-All Other Outputs
ILO
I/O Leakage Current
-PPI4/CE
-DO/WDI0_15
2.6
2.4
Input Leakage Current___ 2
-PPlo-~, 5-7, CBIS-7' SEDCU
III
Max.
-All Other Input Only Pins
.,; Vee
/LA
OV ,,;VIN .,;Vee
NOTES:
1. SEDeU(pin 3) and MIS (pin4) are device strapping options and should be tied to Vee orGND. V1H min = Vee -O.5VandVIL max =0.5V.
2. PPIo-7 (pins 13-20) and CBIS_7 (pins 11, 12) have internal pull-up resistors and if left unconnected will be pulled to Vee.
A.C. TESTING INPUT, OUTPUT WAVEFORM
u=x
20
0.45
0.8
>
TEST POINTS
2.0
~
0.8
A.C. TESTING LOAD CIRCUIT
x==
DEVICE
UNDER
TEST
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOA A LOGIC 1 AND 0 45V FOR
/l LOGIC ~o TlM!NG MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC 1
AND 0 SV FOR A LOGIC 0
'le,
RL
CL INCLUDES JIG CAPACITANCE
6-132 .
AFN-02009B
inter
820618206-2
WAVEFORMS
READ,
:
~--~vr
I I
I
iii
om
I I
I I
I
~
----i-!-¥~:
I I
!--TBHQV-I
I I
I
~i
I
~'-I I
I I
I TRHQV
I,
I
'
, .
I I
I
!.--TBLOZ -
I
. _I
!--'-TOXQX - .
@&'i'a~
i:
1 I,
'I
TRVBV
k=
I
I
+----i
' I'
EiiiiOii
TOYSV
aI
,
I
TRHEV~
>WW$//A
r
TOVEV
'
VAUO
"I
I
I
al
TDVCV
x=
x=
I
:
--+1--+--1
I.. I
I.. I
I
I
'1
TOVQ"
I
I
~
syo--r--; >W#~4 j~,
I" I
I .. I
____
!~,' ~>-'-:- - -
I I
DO
,I,
_~I~I'~~~~TRH~~~~~~a~1________ I
CE_~X7~
6-133
VALID
AFN-02008B
inter
8206/8206-2
WAVEFORMS (Continued)
READ-MASTER/SLAVE
STB
7r
t'i'------
I
I
!--ITSHIV
I I
8M
I :
I I:SLl; I
i7If
i I
I
_---I.i--I-J:;t :
I
R/W - -_ _
nW'ri
~
II
cg:---<~!,
:
.:'~= ------/'V/
':L_____It-
~". ~'~~l<:1
w~~
I
I
~
DO(MASTERl_--';"':- ,
I
:---:
I
~'" I
i
I
VALID
I
~
I
~~~~~~~~z~~~z~:--~LlD---X~
---'
l:sVC~,
~1'~~~~TR~HC~V~~~~.Ir~A
>W
CE _ _ _ _ _ _
6-134
____
VALID
I
~~1
X_
AFN-02009B
8206/8206-2
WAVEFORMS (Continued)
FULL WRITE
/ - - - TRVSY - I
\
I
I
I
I
I
I
TRLSX
I
I
I
I
I
i
R/W
~
i!M
r---I
I
I
I
I
\
\
\
\
~
I
\
\
I
I
I
I
I
\
I
H
I
I
I
I
1
1
I
\
-I
I
I
Taxaxi
I
I
>0//(
SYN
I
I
I
1:
t-!
WRITE DATA IN
1
I
I_Tavav
SYO/CBO
\ TRHSX \
\
I
DATA OUT
A
W
I TBLaz
DO/WDI
I
X
CB
SYN
FULL WRITE-;-MASTERISLAVE
f.---TAVSV ---+-I
RJW
\
I
~LO~ I
I:
DO/WDI
DATA OUT
1
: ,YRH", 1
1
:
IM~:
_ _ _ _----1
: •
I
I
1
1
r1
1
-------..~
I
:
I
I
:
I
I-(-Tovov-l
!
\
\
!
:
r
I
1
I
WRITE DATA IN
1
I
TOXOX\
)05RZzt
-----------t-'I
\
VALID
I
:.- TRLSX
SyO/CBo _ _
SyN _ _
;c=
1
PPO(SLAVEI-----t....,1
PPI(MASTERI
;?
-;------'-\-------- W.
}---{
-I
\.
I
TPVSV
_I
--J~~
6-135
:
CB
k=
AFN·02009B
8206/8206-2
WAVEFORMS (Continued)
READ MODIFY WRITE
~t
tl,...1- - - - - - - - - -
TS,IVI4-I'------TIVSL-""""""'---+l.1 ,_
.. ---TSLlX---!"
II
I
I I
I
---tr-
~W
Y!
I
A--i-:-
'{
I
I'------;-I....J
14-1'........
1 -----'TDVRL---....,I_TRVSV---I
!
8M
I
: :1
1
I
I
I
I
1
I
I
"
X-------VAL-t-ID:- - - - - - . - :-:~;c
I
I
I_TBHQV--I
I
I
I~RHSX : ,kBL~i '11
I
C~: -i+-:___,. .-:_VALID+-:----+----J1
I
I
I
I
: II
I
:_.---'TRHQV'---+-----o-l"I I
-l I
..;.-1----TDVQV-t
~I.+_ _ __+_ _'T_DX_QX_ t-I
l ::;::-:;...
, .•. 1
:1------0.2;!
II
It+.. ---TRVSV---t",
1
I
~
DOiWDI --L-..:
1
I
TQXQ~L
I
II
I-TRLSX
I I I I
M
1
SYO/CBD~:--JXVffL(: SYN~~/0~Z~CB_ _PC
I
I I
I
I
II-'----'TDVSV'---!
.. I !-TQVQV-!
6-136
AFN- TEST POINTS
0.8
V
V
IOL = SmA
IOL = 2.0mA
V
V
IOH = -2mA
IOH = -O.4mA
Vl/o "" Vee
A.C. TESTING LOADCI~CUIT
A.C. TESTING INPUT, OUTPUT WAVEFORM
,. =X.
.
0.45
0.45
<
OEVICE
UNDER
2o)C
TEST
RL
~CL
,I
08
A C TESTING INPUTS ARE DRIVEN AT2 4V FOR A LOGIC "1" ANDO 45V FOR
A LOGIC "0" TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC "1"
AND 0 8V FOR A LOGIC "0"
C L INCLUDES JIG CAPACITANCE
6-146
ilFN,02009C
8206·2
A.C. CHARACTERISTICS (TA
= O°C to 70°C, Vee = +5V ± 10%, VSS = OV, RL = 220 CL = 50pF;
all times are in nsec.)
<
8206-2
Symbol
Parameter
Min.
Max.
TRHEV
ERROR Valid from R/Wl
40
TRHCV
CE Valid from R/Wl
49
Notes
TRHQV
Corrected Data Valid from R/Wl
66
1
TRVSV
SYO/CBO Valid from R/W
46
1
TDVEV
ERROR Valid from Data/Check Bits In
57
TOVCV
CE Valid from Data/Check Bits In
76
TDVQV
Corrected Data Valid from Data/Check Bits In
74
TDVSV
SYO Valid from Data/Check Bits In
65
TBHQV
Corrected Data Access Time
TOXQX
Hold Time from Data/Check Bits In
0
TBLQZ
Corrected Data Float Delay
0
TSHIV
STB High to Data/Check Bits In Valid
TIVSL
Data/Check Bits In to STB! Set-up
5
TSLIX
Data/Check Bits In from STB! Hold
25
TQVQV
Check Bits Out from Write Data In
37
1
28
69
TRHSX
Check Bits Out from R/W, WZ Hold
0
TRLSX
Syndrome Out from R/W Hold
0
TQXQX
Hold Time from Write Data In
0
TDVRL
Data/Check Bits In to R/W Set-up
41
TOVQU
Uncorrected Data Out from Data In
38
TTVQV
Corrected Data Out from CRCn
33
TWLQL
WZ! to Zero Out
TWHQX
Zero Out from WZi Hold
,
1
2
30
1
1
1
1
34
0
NOTES:
1. A.e. Test Levels for eeo and DO are 2.4Vand 0.8\1
2. TSHIV is required to guarantee output delay timings: TOVEV, Tovev. TOVQV. Tovsv. TSHIV + TIVSl guarantees a min STe pulse
width of 35 ns.
6-147
AFN·02009C
WAVEFORMS
READ
'STB;;:
ri _ _
~!~____
!
I:'H'~ 1•
N,......'
•I I:L': 1
TlVSL
~~
:
1 1
1 1
1 1
iii
1
_--+-!-Jll0W/#w.4 ! ~
1-1"+-1- - - T D V S V - - - - ! . I
I
K=
1
1
-----t.1
_ _--'~DYQ·_.
t-I
.. +1-
1
~I!
! ~TRHEV~~r----_I
EiiiiOii--+i--+---i~Z7//Wa
I. 1
TDYEY
I .. 1
.:
1
'
"I
TDVCV
x=
VAUD
-~I~I~.~~~T~~Y~~rrrr~"~1_____
CE_---.;)@///7&h///AVAUD
\
6'"148
1
x=
I
AFN-02OO8C
8206-2
WAVEFORMS (Continued)
READ MODIFY WRITE
~t
tt,...1- - - - - - - - - -
TSj'vi+I'------T'vsL----.j.1 1_'---TSLlX---J·1
- j r1 I
I
I I
I
'i
~W =:JIf
I I
A:
I
1'------;-1- J
1+1'~I----·TDVRL.---......I_TRVSV----!
~
I
l l
i
1:
1
1
1
I
I--TBHQV-l
1
1
I T.RHSX
.-
1
I
1
1
II
TQXQ~L
1
I
WZl
~>e""'--~r-r-/j-r-r7b""7"'-T7Z~:
SVN
SVO/CBO ---1-1
I I
TDVSV
I
m
___
II
t-I.---+RVSV----J"I 1-1 I-TRLsx
II I I
I .
I
-II
-+__T_DX_QX_ t-I
02;:
IiII
1I
i,~BL~i '1
+--_--J* ::
l ::;:;":1,1+
14-1.-=--1----TDVQV-t
I'
I I
--..:_V_"LlD+-: _ _
I ...---TRHQV---+--!"I I
I
1
1
><--------~LI~D:----~:~I~~
c~: -i+-:___
-
1
1
I
I
CB
,
PC
I
"I !----TQVQv-----':"1
6-149
AFN-02OO9C
inter
WAVEFORMS (Continued)
------1
NON-CORRECTING READ
CRCT------------~~~:
BMJ:
I
I
,
I
I
I
I
1 4 I O - - T D Y Q U - -...... 1
I
I
I
~
I
TTVQV
~
I"
I
TBLQZ
I" TDXQX~
---..~
I
I......TTVQV.....'
-----i-:------i-:
I
,
,i
i
)I
I
I
I
1
1
1
i--TBHQV---+j
I
I
I
I
-------WA
WRITE ZERO
I"
~
TWLQL
I
~
~
'I
I
UNCORRECTED
______
~I
1
I
I
,
t
I
I
wz
t=
i
, }r------:-
DI
CBI
DD/WDI
,
}
D1
I
CORRECTED
UNCORRECTED
I
~I
,
,I
,
~~
A
_ _- - J
I
I
I
'_TQVQV-I
,
I
I
,
,I
I
I
I
,
Do~mff//$M
1
I~WHQ!
I
I
I
I
I
,
: k7Zi
i
I
,~
k
SYOICBOW~~----VAL-'D
6-150
AFN-02009C
inter
8206·2
6-151
AFN·02009C
8207
ADVANCED DYNAMIC RAM CONTROLLER
• Provides All Signals Necessary to
Control 16K (2118), 64K (2164A) and
256K Dynamic RAMs
• Supports Intel iAPX 86, 88, 186, 188, and
286 Microprocessors
• Directly Addresses and Drives up to 2
Megabytes without External Drivers
• Data Transfer and Advance' Acknowledge
Signals for Each Port
• Supports Single and Dual·Port
Configurations
• Automatic RAM Initialization in All
Modes
• Provides Signals to Directly Control the
8206 Error Detection and Correction Unit
• Four Programmable Refresh Modes
• Transparent Memory Scrubbing in
ECC Mode
• Supports Synchronous or
Asynchronous Operation on Either Port
• +5 Volt Only HMOSII Technology for
High Performance and Low Power
The Intel 8207 Advanced Dynamic RAM Controller (ADRC) is a high-performance, systems-oriented, Dynamic
RAM controller that is designed to easily interface 16K, 64K and 256K Dynamic RAMs to Intel and other
microprocesso~ systems. A dual-port interface allows two different busses to independently access memdry. When
configured with an 8206 Error Detection and Correction Unit the 8207 supplies the necessary logic for designing
large error-corrected memory arrays. This combination provides automatic memory initialization and transparent
memory error scrubbing.
•So.'C==~
Figure 1. 8207 Block Diagram
Intel Corporation Assumes No Responsibility fllr the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product No Other Circuit
Patent Licenses are Implied. Information Contained Herein Supercedes Previously Published SpecificatIons. On These Devices From Intel.
@INTELCORPORATION, 1983
6-152
JULY 1983
ORDER NUMBER: 210463·003,
8201
Table 1, Pin description
Symbol
Pin
Type
Name and Function
LEN
1
0
AoPAESS LATCH ENABLE: In two-port configuralions, when Port A is running w~h iAPX 286 Status
interface mQde, this output replaces the ALI;: signal from tile system bus .controller of port A and
generates an llddress latch enable signal which provides optimum setup and hold timing for the 8207.
This signal is used in Fast Cycle operation only.
XACKAI
ACKA
2
0
TRANSFER ACKNOWL~DGE ~AlACKNOWLEDGE PORTA: In non-ECC mode, this. pin is
XACKA and inideates that data on the bus is valid during a read cycle or that data may be removed
from the bus during a write cycle for Port A. ~CKA is a MultibulHlOmpatibie signal. In ECC mode,
this pin Is ~ which can be configured, depending on the programming of th~Ogram bit,
as an XACK or MCK strobe. The SA programming bit 'determines whether the ,M K will be an
early EMCKA or a late LAACKA interface signal.
XACKBI
3
0
TRANSFER ACKNOWLEDGE PORT B/ACKNOWLEDGE PORT B: In non-ECC mQde, this pin
is XACKB and indicates \hat data on the·bus is valid during a read cycle or that data may be removed from the bus during a write cycle for Port B. XACKB is a MultibulHlOmpatible signal. In ECC
mode, thi5BIC~ ACKB which can be c;onfigured, depanding on the programming of ~ram
bit, as an
or MCK strobe. The SB programming bit determines whether the
will be
an early EAACKB, or a late LAACKB interface signal. '
4
0
ADVANCED AC\
.!.
01
8207
RDA
so
~
WRA
A,DDR/OATA
,
..
lI
~ .Y
k-;>
CXI
L~
-
.
DO
ll~
-
~~
i2!5
~
I;
MARK
----
....
~
~~
~
LATCH
ALE
-ClJ(
~~
t-- t-
.
.
BO
81
SO
,
-
.....
DE S1B
'::'iT r./
I
-I
8283
....
LATCH
I
ADDWDATA
USING STATUS-
S1B
1009;
I--I---
IRDNOUS
'--
-
,.
-
,.
....
LATCH
I---
'---
"@--
dg)
,.
ffi
~
'---
I
I
DE S1B
Lr-..,
.... Ie
DTtRl--
CLR
S1B .DE
S1B OE
...*
DEN
51
BYTE
LATCH
CLK
ROB
CLR
~
...=::-
-*
I~-':'-
52
PSENPSEI
.A
.-
DI
PCTLB(4
t-
,
WE
(
SOS152
WRBI>-
MUX
AHo-aAl.cJ_e
8086/
80186
.--
~
(LdWER)
AACKII
PCTLA,
J
S1
T'-"r----'
AGo.. 1IDo-,
CASo.3
WE
1
T
DO
~II
t----.t-
Mill
DI
P ME_
:NOTE:
*These components are not necessary when using the 80186 components. These functions are provided directly by
the 80186.
Figure 3. 8086/80186 Dual Port System
~
=
~
~2QJ.
~'
8207
A12-A20
8207
8207
8207
A3-A11
A1,A2
16K RAM INTERFACE
64K RAM INTERFACE
256K RAM INTERFACE
NOTES:
(1) Unassigned address input pins should be strapped high or low.
(2) AO along with BHE are used to select a byte within a processor word.
(3) Low order address bits are used as bank select inputs so that consecutive memory access requeSts
are to alfernatebanks -allowing bank interleaving of memory cycles.
Figure 4. Processor Address Interface to the 8207 Using 16K, 64K, and 256K RAMS
Table 2.
Bank Selection Decoding and
Word Expansion
If not all RAM banks are occupied, the 8207 reassigns
the RAS and CAS strobes to allow using wider data
words without increasing the loading on the RAS and
CAS drivers. Table 2 shows the bank selection
decoding and the word expansion, including RAS and
CAS assignments. For example, if only two RAM banks
are occupied, then two RAS and two CAS strobes are
activated per bank. Program bits RB1 and RBO are not
used to check the bank select inputs BS1 and BSO. The
system design must protect from accesses to "illegal",
non-existent banks of memory, by deactivating the
PEA, PEB inputs when addressing an illegal bank.
Program
Bank
Bits
Input
RB1 RBO BS1 BSe
RAS/CAS Pair Allocation
0
0
0
0
RASo-3. CASO_3 to Bank 0
0
0
0
1
Illegal
0
0
1
0
Illegal
0
0
1
1
Illegal
0
1
0
0
RASo.1. CASO.1 to Bank 0
The 8207 can interface to fast (e.g., 2118-10) or slow'
(e.g., 2118-15) RAMs. The 8207 adjusts and optimizes
internal timings for either the fast Of slow RAMs as
programmed~ (See RAM Speed Option).
b
1
0
1
RAS2.3. CAS2.3 to Bank 1
0
1
1
0
Illegal
0
1
1
1
Illegal
Memory Initialization
1
0
0
0
RASo. CASo to Bank 0
After programming, the 8207 performs eight RAM
"warm-up" cycles to prepare the dynamic RAM for
proper device operation. During "warm-up" some
RAM parameters, such as tRAH, tASC, may not be
met. This causes no harm to the dynamic RAM array. If configured for operation with error correction,
the 8207 and 8206 EDCU will proceed to initialize
all of memory (memory is written with zeros with
corresponding check bits).
1
0
0
1
RAS1. CAS1 to Bank 1
1
0
1
0
RAS2. CAS2 to Bank 2
1
0
1
1
Illegal
1
1
0
0
RASo. CASo to Bank 0
1
1
0
1
RAS1. CAS1 .to Bank 1
1
1
1
0
RAS2 •. CAS2 to Bank 2
1
1
1
1
RAS3. CAS3 to Bank 3
6-159
/'
210483-003
8207
Because the time to initiaiize memory is fairly long,
the 8207 may be programmed to skip initialization in
ECC mode. The time required to initialize all of
memory is dependent on the clock cycle time to the
8207 and can be calculated by the foflowing
equation:
eq.1
Figure 6 illustrates the interface required to drive the
CRCT pin of the 8206, in the ca~e that one port (PORT
A) receives an advanced acknowledge (not Multibuscompatible), while the other port (PORT B) receives
XACK (which is Multibus-compatible).
TINIT = (~3) TCLCL
Err~r Scrubbing
if TCLCL = 125 ns then TINIT = 1 sec.
The 8207/8206 performs error correction during
refresh cycles (error scrubbing). Since the 8207 must
refresh RAM, performing error scrubbing during
refresh allows it to be accomplished without additional performance penalties.
8206 ECC Interface
For operation with Error Checking and Correction
(ECC), the 8207 adjusts its internal timing and
changes some pin functions to optimize performance and provide a clean dual-port memory interface between the 8206 EDCU and memory. The 8207
directly supports a master-only (16-bit word plus 6
check bits) system. Under extended operation and
reduced clock frequency, the 8207 will support any
ECC master-slave configuration up to 80 data bits,
which is the maximum set by the 8206 EDCU. (See
Extend Option)
Upon detection of'a correctable error during refresh,
the RAM refresh cycle is lengthened slightly to permit the 8206 to correct the error and for the corrected
word to be rewritten into memory. Uncorrectable errors detected during scrubbing are ignored.
Refre,sh
The 8207 provides an internal refresh interval counter and a refresh address counter to allow the 8207 to
refresh memory. The 8207 will refresh 128 rows every
2 milliseconds or 256 rows every 4 milliseconds,
which allows all RAM refresh options to be supported. In addition, there exists the ability to refresh
256 row address locations every 2 milliseconds via
the Refresh Period programming option.
Correctable errors detected during memory read
cycles are corrected immediately and then written
back into memory.
In a synchronous bus environment, ECC system performance has been optimized to enhance processor
throughput, while in an asynchronous bus environment (the Multibus), ECC performance has been optimized to get valid data onto the bus as quickly as
possible. Performance optimization, processor
throughput or quick data access may be selected via
the Transfer Acknowledge Option.
The main difference between the two ECC implementations is that, when optimized for processor
throughput, RAM data is always corrected and an
advanced transfer acknowledge is issued at a point
when, by knowing the processor characteristics,
data is guaranteed to be valid by the time the processorneeds it.
When optimized for quick data access, (valid for Multibus) the 8206 is configured in the uncorrecting
mode where the delay associated with error correction circuitry is transparent, and a transfer acknowledge is issued as soon as valid data is known to exist.
If the E'R'RC5R flag is activated, then the transfer acknowledge is delayed until'after the 8207 has instructed the 8206 to correct the data and the corrected
data becomes available on the· bus. Figure 5 iI-'
lustrates Ii dual-port ECC system.
The 8207 may be programmed for any of four different
refresh options: Intemal refresh only, Extemal refresh
with failsafe protection, External refresh without failsafe
protection, Burst Refresh mode, or no refresh. (See
Refresh Options)
It is possible to decrease the refresh time interval by
10%,20% or 30%. This option allows the 8207. to
compensate for reduced clock frequencies. Note
that an additional 5% interval shortening is built-in in
all refresh interval options to compensate for clock
variations,and non-immediate response to the iriternally generated refresh request. (See Refresh Period
Options)
'6-160
External Refresh Requests after RESET
External refresh requests are not recognized by the
8207 until after it. is finished programming and preparing memory ,for access. Memory, preparation includes 8 RAM cycles to prepare and ensure proper
210463-003
l
DTIRB
DENB
A"CKI
J:_ ;:1
JII~
I,
CMD/PEB
ADDRB
r-- rV
0)
.!.
~
CMliIPEA
-
ADDRA
ACKA
DI'NA
DTIRA
"-
v
-
-
V
MUX
ClK
8207
-
1WE
DI
WZ
PSEN
ADDR
RIW
7
~~
BM
~
SYICB DII
CBI
ECC
PPI
MASTER
8206
\iii
WDliDO
PPO
<5
eRCTWR
t=:
Ir-
:::c:>--.-t
)P1~
DTIR
XCVR
7
I~
-rE
g
DI
WDliDO
I
r---
-
PORTA
SYNC
ECC
SlAYE
8206
~j
R
-
CE
RIW
...
-<~1:IDE
-
I
L~EI{RD~
-<{J:::
-'STB
BYTE
MARK
lATCH
h
l-
RIIii
~J
I-
L I-~
iiiiii
II
~I
CBI CBD
CE
ERRDR
ACKA FWR PSEl
BYTE'
MARK
DECODER
DYNAMIC
-
CMDIPEB
~
ADDR
7
1
-
PORTB
·1
I
"@
~
ffi
F
~
i
=
~
.~
2!?l
Figure 5. Two-Port ECC Implementation Using the. 8207 and the 8206
~
inter
8207
8207
The differentiated reset pulse would be snorter than
the system reset pulse by at least the programming
period required by the 8207. The differentiated reset
pulse first resets the 8207 •.and system· reset would
reset the rest of the system. While the rest of the
system is still in reset. the 8207 completes its programming. Figure 7 illustrates a circuit to accomplish this task.
8206
PSELt--------,
R/W
Within four clocks after RESET goes active. all the 8207
outputs will go high. except for PSEN, WE, and AOO-2,
which will go low.
Figure 6. Interface to 8206 CRC'i' Input When Port
A Receives AACK and Port B Receives
XACK
OPERATIONAL DESCRIPTION
dynamic RAM operation. and memory initialization if
error correction is used. Many dynamic RAMs require this warm-up period for proper operation. The
time it takes for the 8207 to recognize a request is
shown below.
eq.2
Non-ECC Systems: TRESP = TpROG +
TpREP
eq. 3
where: TPROG = (66) (TCLCL) which is
programming time
eq. 4
TPREP = (8) (32) (TCLCL) which is
the RAM warm-up time
Programming the 8207
The 8207 is programmed after reset. On the falling
edge of RESET, the logic states of several input pins
are latched internally. The falling edge of RESET
actually performs the latching. which means that the
logic levels on these inputs must be stable prior to
that time. The inputs whose logic levels are latched at
the end of reset are the PCTlA. PcrlB. REFRO. and
POI pins. Figure 8 shows the necessary timing for
programming the 8207.
if TCLCL = 125 ns then TRESP '" 41 us
eq.5
ECC Systems: TRESP = TpROG + TpREP +
;
TINIT
SVST!!!j
RESET
if TCLCL = 125 ns then TRESP '" 1 sec
I'
l.-
11
82llifl
RESET I
RESET
L-
"I
t, PROGRAMMING TIME OF 8207
RESET is an asynchronous input. the falling edge of
which is used by the 8207 to directly sample to logic
levels of the PCTlA. PCTlB. RFRO. and POI inputs.
The internally synchronized falling edge of RESET is
used to begin programming operations (shifting. in the
contents of the external shift register into the POI input).
Until programming is complete the 8207 registers
but does not respond to command or status inputs. A··
simple means of preventing commands or status
from occurring during this period is to differentiate
the system reset pulse to obtain a smaller reset pulse
for the 8207. The total time of the reset pulse and the
8207 programming time must be less than the time
before the first command in systems that alter the
default port synchronization programming bits
(default is Port A synchronous. Port B asynchronous). Differentiated reset is unnecessary when the
default port synchronization programming is used.
6-162
SYSTEM
RESET
IV"- 2:rJ........
">----I"'>
V
"¢
8207
RESET
J
DIFFERENTIATED RESET
NOTES:
(1)Required only when the port synchronization options (SA & SB) are altered from
their initial default values.
(2)Vcc must be stable before system reset
is activated when using this circuit.
Figure 7. 8207 Differentiated Reset Circuit
210463·003
8207
NOTES:
TRTVCL - Reset is an asynchronous input, if reset occurs before 1;, then it is
.
guaranteed to be recognized.
.
TPGVCL - Minimum POI valid time prior to reset going low.
TCLP'C - MUXlPCLK delay.
TLOAO - Asynchronous load data propagation delay.
Figure 8. nmlng illustrating External Shift Register Requirements for Programming the 8207
Status/Command Mode
Table 3A. Status Coding of 8086, 80186 and 80286
The two processor ports of the 8207 are configured
by the states of the PCTLA and PCTLB pins. Which
interface is selected depends on the state of the
individual port's PCTL pin at the end of reset. If PCTL
is high at the end of the reset, the 8086 Status inte ....
face is selected; if it is low, then the Command interface is selected.
-Function
Status Code
The status lines of the 80286 are similar in code and
timing to the Multibus command lines, while the status
code and timing of the 8076 and 8088 are identical to
those of the 80186 and 80188 Ognoring the differences
in clock duty cycle). Thus there existS two interface configurations, one tor the 80286 status or Multibus
memory commands, which is called the Command interface, and one for 8086,8088,80186 or 80188 status,
called the 8086 Status interface. The Command interface can also directly interface to the command lines
of the bus controllers tor the 8086, 8088, 80186 and
the 80286.
!2
8'i
SO
0
0
0
0
0
0
1
0
1
1
_6180186
INTERRUPT
1
I/O READ
I/O READ
0
I/O WRITE
I/O WRITE
1
HALT
IDLE
0
0
INSTRUCTION
FETCH
HALT
1
0
1
MEMORY READ MEMORY READ
1
1
0
MEMORY WRITE MEMORY WRITE
1
1
1
IDLE
IDLE
3B.
8207 Response
Table
8207
Command
The 8086 Status interface allows direct decoding of
the status of the iAPX 86, iAPX 88, iAPX 186 and the
iAPX 188. Table 3 shows how the status lines are
decoded. While in the Command mode the iAPX 286
status can be directly decoded. Microprocessor
bus controller read or write. commands or Multibus
commands can also be directed to the 8207 when in
Command mode.
80286
INTERRUPT
Function
P.CTL RD WR
8086/80186
Status
Intarface
80286/Statuior
Command
Interface
0
0
0
IGNORE
0
0
1
IGNORE
IGNORE
READ
0
1
0
IGNdRE
WRITE
Refresh Options
0
1
1
IGNORE
IGNORE
Immediately after system reset, the state of the
REFRQ input pin is examined. If REFRQ is high, the
8201 provides the user with the choioe between selfr~fres~ or user-generate~' refresh with failsafe protection. Failsafe protection guarantees that if the
1
0
0
READ
IGNORE
1
0
1
READ
INHIBIT
1,
1
0
WRITE
INHIBIT -
1
1
1
IGNORE
IGNORE
6-163
inter
8207
Option PrOgram Data Word .
user does n6t come back with another refresh request 'before the internal refresh interval counter
times out, Ii refresh request will' be automatically
generated. If the REFRQ pin is low immediately after'
a feset, then the user has the choice of a single
externai refresh cycle without failsafe, burst refresh
or no refresh.
The program data wo[d consist!! of 16 program data
bits, PO()"-P015. If the first progr!im data bit POO is
set to 'logic 1, the 8207 is configured to support ECC.
If it is logic 0, the 8207 is configured to support a nonECC system. The remaining bits, P01-P015, may
then be programmed to optimize a selected·configuration, Figures 9 and 10 show the Program words for nonECC and ECC operation.
Internal Refresh Only
For the 8207 to'generate internal refresh requests, it
is necessary only to strap the REFRQ ,input pin high.
Using an External ~hlft Register
External Refresh with Failsafe
To allow user-generated refresh .requests with failsafe protection, it is necessary fo hold the REFRQ
. input high until after reset. Thereafter, a low-to-high
transition on this inp4t causj!s a r,efresh request to be
generated and the internal refresh interval counter /
to be reset. A high-to-Iow transition has no effect on
the 8207. A refresh request is not recognized until a
previous request has been serviced.'
The 8207 may be configured to use an external shift
regil!ter with asynchronous load capability such as a
74LS165. The reset pulse serves to parallel load the
. shift register and the 8207 supplies the clocking signal to shift the data in. Figure 11 shows a sample
circuit diagram of an external shift ~egistE!r' circuit.
To generate single external refresh requests without
failsafe protection, it is necessary to hold REFRQ low
until after reset. Thereafter, bringing REFRQ high for
one clock period causes a refresh request to be
generated. A refresh request is not recognized until a
previous request has been serviced.
Serial data is shifted into the 8207 via the POI pin (57),
and clock is provided by the·MUXlPCLK pin (12), which
generates a total of 16 clock pulses. After programming is complete, data appearing at the input of the
POI pin is ignored. MUXlPCLK is a dual-function pin.
Ouring programming, it serves to clock the external shift
register, and after pl'QQramming is completed, it reverts
to a MUX control pin. As the pin cl)anges state to select
different port addresses, it continues to clock the shift
register. This does not presi,nt problem because data
at the POI pin is ignored after programming. Figure 8
illustrates the timing requirements of the shift register
circuitry.
Burst Refresh
ECC Mode (ECC Program Bit)
Burst refresh [s implemented tl)rough the same procedure
a single external refresh without failsafe (i.e.,
REFRQ is kept low until after reset). Thereafter, bringing REFRQ high for at least two clock periods causes
a burst of up to 128 row address locations to be
refr.e~hed; , . .
The.state of POI (Program Data In) pin at reset determines whether the system is an fCC or non-ECC
configuration. It is used internally by the 8207 to
begin configuring timing circuits, even before progrflmmirig is completely finished. The 8207 then
begilis programming the rest of the options.
External Refresh without Failsafe
as
In E~figured systems, 128 locations are' scrubbed.
Any refresh request is not recognized until a previous
request has been serviced (i.e., burst completed).
No Refresh
,
.
It is necessary to hold R~FRQ low until after reset.
This is the same as programming External Refresh
without Failsafe. No refresh is accomplished by
.keeping REFRQ low. I ,.
a
Defau~iProgrammlng Options
After reset, the 8207 serially shifts in a program data
word via the POI pin: This pin may be 'strapped either ~
high or low, or connected to an external shift register.
Strapping POI high . cau~s the 8207 to defl?ult to a
partlcl,llar system configuration with error correction; andlitrapRing it low cau~s the 8?07 to default
to. Ii p'a~ticular system configuration without 'error
correction; Table 4 shows th~' defaultconfigurations.
6-164
inter
PDO
POB PD7
PD15
I
ITM11~lmIEXTIPLSI CIOI ClllA111IRDl m
,
PROGRAM
0 I 0
DATA BIT
PDO
POI
NAME
ECC
SA
PD2
SI
PD3
CFS
PD4
RFS
PDS
PDe
=
Cll
CIO
PD7
PDe
PDB
PLS
POlO
EXT
PD11
FFS
PD12
PPR
PD13
TMl
P014
POlS
0
0
lml SB I nl
o
I
,
POLARITYIFUNCTION
ECC=O FOR NON-ECC MODE
0 PORT A IS SYNCHRONOUS
PORT A IS ASYNCHRONOUS
=1
SI-O
88=1
~~::: :v~~W'~~
CFS-O FAST·CYCLE IAPX 288 MODE
eFS=l SLOW-CYCLE fAPX 86 MODE
JU!li=0 FAST RAM
fiI!i=l SLOW RAM
RAM BANK OCCUPANCY
SEETAlLE2
COUNT INTERVAL liT 1; SEE TAlLE 6
COUNT INTERVAL lIT 0; SEE TABLE 6
8-
KS=o LONG REFRESH PERIOD
SHORT REFRESH PERIOD
EXT-O NOT EXTENDED
EXT=l EXTENDED
FFS=O FAST CPU FREQUENCY
, FFS=l SLOW CPU FREQUENCY
PPR=O MOST RECENTLY USED PORT
PRIORITY
jij5jj=1 PORT A PREFERRED
PRIORITY
TM1=0 TEST MODE 1 OFF
TM1=1 TEST MODE 1 ENABLED
RESERVED MUST IE ZERO
RESERVED MUST IE ZERO
m=l
Figure 9. Non-ECC Mode Program Data Word
POlS
PDB PD7
PDO
1~1~IR~lp~~lml~sl~I~lelnIRFSICFSlgISAI'
1
p
,
PROGRAM
DATA lIT
PDO
POl
NAME
ECC
SA
PD2
SI
PD3
CFS
PD4
RFS
PD5
XA
PD8
XI
P07
PDB
PDB
Ciii
POlO
00
Cll
PLS
POll
FFS
PD12
PPR
PD13
PD14
POlS
RBO
Rll
TM2
I
.
POLARITYIFUNCTION
ECC-l ECCMODE
SA=O PORT A ASYNCHRONOUS
PORT A SYNCHRONOUS
SA=l
D-O PORT B SYNCHRONOUS
SI=l PORT I ASYNCHRONOUS
CFS=O SLOW-CYCLE IAPX 86 MODE
CFS=l FAST-CYCLE IAPX 286-MODE
RFS=O sLOW RAM
RFS=l FAST RAM
XA=O MULTIBUS-cOMPATIILE
ACKA
Xli =1 ADVANCED ACKA NOT
MULTIBUS-COMPATllLE
XI=O ADVANCED ACKI NOT
MULTIBUS COMPATllLE
XI=l
MUL:r1IUS-COMPATllLE
ACKI
COUNT INTERVAL lIT 1; SEE TAILE 8
COUNT INTERVAL BIT 0; SEE TAlLE 6
PLS=O SHORT REFRESH PERIOD
PLS=l LONG REFRESH PERIOD
EXT=O MASTER AND'SLAVE EDCU
EXT=l MASTER EDCU ONLY
FFS=O SLOW CPU FREQUENCY
FFS=l FAST CPU FREQUENCY
PPR-O PORT A PREFERRED
PRIORITY
PPR=l MOST RECENTLY
, USED PORT
PRIORITY
RAM lANK OCCUP4NCY
SEE TAlLE 2
~=O TEST MODE 2 ENAILED
=1 TEST MODE 2 OFF
\
-
Figure 10. ECC Mode Program Data Word
ti-165
21_3
If further system flexibility is needed, one or two
external shift register/! can be used to tailor the 8207
S:J~r >---.......-~----J RESET
to
.-------1 PCLK
i~S operating environment.
Synchronous!Asynchronous Mode
(SA and SB Program Bits)
8207
Each port of the 8207 may be independently configured to accept synchronous or asynchronous port
commands (RD, WR, PCTl) and Port Enable (PE) via
the program bits SA and S8. The state of the SA and
S8 programming bits determine whether their asso-:
ciated ports are synchronous or asynchronous.
~_.lJ,-,-UMPER OPTIONS
Figure 11. External Shift Register Interface
Table 4A.
Default Non-ECC Programming, POI Pin (57)
Tied to Ground.
Port A is Synchronous (EAACKA and XACRA)
Port B is Asynchronous (LAACKB and XACKB)
Fast-cycle Processor Interface (10 or 16 MHz)
Fast RAM
Refresh Interval uses 236 clocks
While a port may be configured with either the Status
or Command interface in the synchronous mode,
certain restrictions exist in the asynchronous mode. An
asynchronous Command interface using the control
lines of the Multibus is supported, and an asynchronous
8086 interface using the control lines of the 8086 is
supported, with the use of TIL gates as illustrated in
Figure 2. Ir;! the 8086 case, the TIL gates are needed
to guarantee that status does not appear at the 8207's
inputs too much before address, so that a cycle would
start before address was valid.
Microprocessor Clock Frequency Option
(CFS and FFS Program Bits)
128 Row refresh in 2 ms; 256 Row refresh in 4 ms
Fast Processor Clock Frequency (16 MHz)
The 8207 can be programmed to interface with slowcycle microprocessors like the 8086, 8088, 80188 and
80186 or fast-cycle microprocessors like the 80286. The
CFS bit configures the microprocessor interfa:ce to
accept slow or fast cycle signals from either microprocessor group.
"Most Recently Used" Priority Sc,heme
4 RAM banks occupied
Table 4B.
Default ECC Programming, POI Pin (57)
Tied to Vee.
This option is used to select the speed of the microprocessor clock. Table 5 shows the various
microprocessor clock frequency options that can be
programmed.
Port A is Synchronous
, Port B is Asynchronous
Fast-cycle Processor Interface (10 or 16 MHz)
Table 5.
Microprocessor Clock Frequency Options
Fast RAM
, Port A has EAACKA strobe (non-muHibus)
Program Bits
Port B has XACKB strobe (multi bus)
Processor
CI~~k
Frequency
CFS
FFS
0
0
iAPX 86,
88, 186, 188
5 MHz
0
1
iAPX86,
88,186,188
8 MHz
"Most Recently Used" Priority Scheme
1
0
iAPX 286
10 MHz
4 RAM banks occupied
1
1
iAPX 286
16 MHz
Refresh interval uses 236 clocks
128 Row refresh in 2 ms; 256 Row refresh in 4ms
Master EDCU only (16-bit system)
Fast Processor Clock Frequency (16 MHz)
IJ
210463·003
8207
at reduced frequencies. The interval between refreshes is decreased by 0%, 10%, 20%, or 30% as a
function of how the count interval bits are programmed. A 5% guard band is built-in to allow for any
clock frequency variations. Table 6 shows the refresh
period options available.
The external clock frequency must be programmed
so that the failsafe refresh repetiti'on circuitry can
adjust its internal timing accordingly to produce a
refresh request as programmed.
RAM Speed Option (RFS PrQgram Bit)
The numbers tabulated under Count Interval repre~ent
the number of clock periods between internal refresh,
requests. The percentages in parentheses represent
the decrease inthe interval between refresh requests.
Note that all intervals have a built-in 5% (approximately) safety factor to compensate for minor clock frequency deviations and non-immediate response to internal
refresh requests,
The RAM Speed programming option determines
whether RAM timing will be optimized for a fast or
slow RAM. Whether a RAM is fast or slow is measured relative to the 2118-10 (Fast) or the 2118-15
(Slow) RAM specifications.
Refresh Period Options
•(CIO, C11, and PLS Program Bits)
Extend Option (EXT Program Bit)
The 8207 refreshes with either 128 rows every 2 milliseconds or 256 rows every 4 milliseconds. This
translates to one refresh cycle being executed approximately once every 15.6 microseconds. This rate
can be changed to 256 rows every 2 milliseconds or a
refresh approximately once every 7.8 microseconds
via the Period Long/Short, program bit PLS, programming option. The 7.8 microsecond refresh request rate is intended for those RAMs, 64K and
above, which may require a fastElr refresh rate.
The Extend option lengthens the memory cycle to
allow longer access time which may be required by
the system. Extend alters the RAM timing to compensate for increased loading on the Rowand Column
Address Strobes, and in the multiplexed Address
Out lines,
Port Priority Option and Arbitration
(PPR Program Bit)
In addition to PLS program 'option, two other programming bits for refresh exist: Count Interval 0 (CIO)
,and Count Interval 1 (CI1). These two programming
bits allow the rate at which refresh requests are
generated to be increased in 'order to permit refresh
requests to be generated close to the same 15.6 or
7.8 microsecond period when the 8207 is operating
The 8207 has to internally arbitrate among three
ports: Port A, Port B and Port C-the refresh port.
Port C is an internal port dedicated to servicing
refresh requests, whether they are generated internally by the refresh inverval counter, or externally by
the user, Two arbitration approaches are available via
Table 6 Refresh Count Interval Table
Count Interval
C11, CIO
(8207 Clock Periods)
Freq.
(MHz)
Ref.
Period
(J.LS)
CFS
16
15.6
1
1
1
236
7.8
1
0
1
118
15.6
1
1
0
148
,7.8
1
0
0
15.6
0
1
1
7.8
0
0
1
59
10
8
5
PLS
FFS
~(20%)
11
(30%)
212
188
164
106
94
82
132
116
100
74
66
58
50
118
106
94
82
53
47
41
00
(0%)
01
(10%)
10
15.6
0
1
0
74
66
58
50
7.8
0
0
0
37
33
29
25
6-167
210483·003
8207
the Port Priority programming option, program bit
PP~. PPR determines whether the most recently
used port will remain selected (PPR = 1) or whether
Port A will be favored or preferred over Port B
(PPR = 0).
A port is selected if the arbiter has given the selected
port direct access to the timing generators. The
front-end logic, which includes the a~biter, is designed to operate in parallel with the selected port.
Thus a request on the selected port is serviced immediately. In contrast, an unselected port only has acc~ss to the timing generators through the front-end
logic. Before a RAM cycle can start for an unselected
port, that port must first become selected (Le., the
MUX output now gates that port's address into the
8207 in the case of Port A or B). Also, in order to allow
its address to stabilize, a newly selected port's first
RAM cycle is started by the front-end logic. Therefore, the selected port has direct access to the timing
generators. What all this means is that a request on a
selected port is started immediately, while a request
on an unselected port is started two to three clock
periods after the request, assuming that the other
two ports are idle. Under normal operating conditions, this arbitration time is hidden behind the RAM
cycle of the selected port so that as soon as thf;l
present cycle is over a new cycle is started. Table 7
lists the arbitration rules for both options.
Port LOCK Function
The LOCK function provides each port with the
ability to obtain uninterrupted access to a critical
region of memory and, thereby, to guarantee that the
opposite port cannot "sneak in" and read from or
write to the critical region prematurely.
Only one LOCK pin is' present and is multiplexed
between the two ports as follows: when MUX is high,
the 8207 treats the LOCK input as originating at
PORT A, while when MUX is low, the 8207 treats
LOCK as originating at PORT B. When the 8207
recognizes a LOCK, the MUX output will remain
pointed to the locking port until LOCK is deactivated.
Refresh is not affected by LOCK and can occur during a locked memory cycle.
Table 7. The Arbitration Rules for the Most Recently Used Port Priority and for
Port A Priority Options Are As follows:
1.
If only one port requests service, then that port-if not already selected-becomes selected.
2a.
When no service requests are pending, the last selected processor port (Port A or B) will remain selected.
(Most Recently Used Port Priority Option)
2b.
When no service requests are pending, Port A is selected whether it requests service or not. (Port A Priority
Option)
3.
During reset i'ni!ialization only Port C, the refresh port, is selected.
4.
If no processor requests are pending after reset initialization, Port A will be selected.
5a.
If Ports A and B simultaneously'(') request service while Port C is being serviced, then the next port to be
selected is the one which was not selected prior to servicing Port C. (Most Recently Used Port Priority
Option)
,
5b.
If Ports A and B simultaneously(') request service while Port C is selected, then the next port to be selected
is Port A. (Port A Priority Option)
6.
If a port simultaneously requests service with the currently selected port, service is granted to the selected
port.
.
7.
The MUX output remains in its last state whenever Port C is selected.
8,
If Port C and either Port A or Port B (or both) simultaneously request service, then service is granted to the
requester whose port is already selected. If the selected port is not requesting service, then service is
g ranted to Port C.
9.
If during the servicing of one port, the other port requests service before or simultaneously with the refresh
port, the refresh port is selected. A new port is not selected before the presently selected port is
deactivated.
10.
Activating LOCK will mask off service requests from Port B if the MUX output is high, or from Port A if the
MUX output is low.
, By "simUltaneous" it is meant that two or more requests are valid at the clock edge at which the intElrnal arbiter
samples them.
6-168
210463.003
intJ
8207
Dual-Port Considerations
For both ports to be operated synchronously, several
conditions must be met. The processors must be the
same type (Fast or Slow Cycle) as defined by Table 8
and they must have synchronized clocks. Also when
processor types are mixed, even though the clock~ ,
may be in phase, one frequency may be twice that of
the other. So to run both ports synchronous using
the status interface, the processors must have
related timings (both phase and frequency). If these
conditions cannot be met, then one port must run
synchronous and the other asynchronous.
Figure 3 illustrates an example of dual-port operation
using the processors in the slow cycle group. Note the
use of cross-coupled NAND gates at the MUX output
for minimizing contention between the two latches, and
the use of flip flops on the status lines of the asynchronous processor for delayi ng the status and thereby
guaranteeing RAS will not be issued, even in the worst
case, until address is valid.
Processor Timing
In order to run without wait states, AACK must be
used and connected to the SRDY input of the appropriate bus controller. AACK is issued relative to a
point within the RAM cycle and has no fixed relationship to the processor's request The timing is such,
however, that the processor will run without wait states,
barring refresh cycles, bank precharge, and RAM
accesses from the other port. In non-ECC fast cycle,
fast RAM, non-extended configurations (80286), AACK
is issued on the next falling edge of the clock after the
edge that issues RAS. In non-ECC, slow cycle, nonextended, or extended with fast RAM cycle configurations (8086, 80188, 80186), AACK is issued on the
same clock cycle that issues RAS. Figure 14 illustrates
the timing relationship between AACK, the RAM cycle,
and the processor cycle for several different situations.
Port Enable (PE setup time requirements depend on
whether the associated port is configured for synchronous or asynchronous fast or slow cycle operation.
In a synchronous fast cycle configuration, PE is required to be setup to the same clock edge as the status
or commands. If PE is true (low), a RAM cycle is started;
if not, the cycle is aborted. The memory cycle will only
begin when both valid signals (PE and RD or WR) are
recognized at a particular clock edge. In aynchronous
operation, PE is required to be setup to the same clock
edge as the internally synchronized status or commands. Externally, this allows the internal synchronization delay to be added to the status (or command)-toPE delay time, thus allowing for more external decode
time that is available in synchronous operation.
The minimum synchronization delay is the additional
amount that PE must be held valid. If PE is not held
valid for the maximum synchronization delay time, it
is possible that PE will go invalid prior to the status or
command being synChronized. In such a case the 8207
aborts the cycle. If a memory cycle intended for the
8207 is aborted, then no acknowledge (AACK or XACK)
is issued and the processor locks up in endless wait
states. Figure 15 illustrates the status (command)
timing requirements for synchronous and asynchronous systems. Figures 16 and 17 show a more
detailed hook-up of the 8207 to the 8086 and the 80286,
respectively.
6-169
210463-003
8207
CLK
I
I
I
ADDRESS
~
VALID
:
~I
I
PSEN
I
I
~
~I
.
LEN
I
I
I
I
I
I
I
I
I
I
~
VALID
\
\
I
I
I
I
I
I
I
I
I
I
I
VALID
\
\
Yllli
rr-
I
PSEL
RAM DATA
!
I
I
I
I
I •
I
CYCLE DELAYED BY
ACCESS ON OTHER
NOTE:
r:,oRR~A:~":~~~H'i~1l"i
1. The RAS and CAS shown in figure are different banks being accessed.
Figure 14. iAPX 286/8207 Synchronous-Status Timing Programmed in non-ECC Mode, CO
Configuration (Read Cycle)
6-170
210463.Q03
8207
8207CLK
(A) liE SET·UP AND HOLD TIME REQUIREMENTS FOR FAST .CYCLE,
SYNCHRONOUS OPERATION (80288 CMD/STATUS)
8207CLK
~/STATUS - - - - - - - - " " " '
~ ---------~~~~
(B)
PE TIMING REQUIREMENTS FOR FAST OR SLOW CYCLE
ASYNCHRONOUS OPERATION
Figure 15.
Memory Acknowledge
(AACK, XACK)
removed asynchronously by, the command going inactive. Since in asynchrono~s operation the 8207
removes read data before late AACK or XACK is
recognized by the CPU, the user must provide for
data latching in the system until the CPU reads the
data. In synchronous operation, data latching is unnecessary since the 8207 will not remove data until
the CPU has read it.
In system configurations without error correction,
two memory acknowledge signals per port are supplied by the 8207. They are the Advanced Acknowledge strobe (AACK) and the Transfer Acknowledge
strobe (XAcR). The CFS programming bit determines for which processor AACKA and AACKB are
optimized, either 80286 (CFS = 1) or 8086/186 (CFS
= 0), while the SA and 5B programming bits optimize
AAcK for synchronous operation ("early" AACK) or
asynchronous operation ("late" AACK).
In ECC-based systems there is one memory acknowledge (XACK or AACK) per port and a programming bit
asspciatedwith each acknowledge. II the X programming bit is high, the strobe is configured as XACK, while
if the bit is low, the strobe is configured as AACK. As
in non-ECC, the SA and SB programming bits determine whether the AACK strobe is early or late (EAACK
or LAACK).
Both the early and late AACK strobes are three
clocks long for CFS = 1 and two clocks long for CFS
= O. The XACK strobe is asserted when data is valid
(for reads) or when data may be removed (for writes)
and meets the Multibus requirements. XACK is
Data will always be valid a fixed time after the occurrence of the advanced acknowledge. Table 9 summarizes the various transfer ackhowledge options.
6-171
210"*003
inter '
8207
UI4A'
ROY 1
READY
CUI:
i----<'l'; I OTHER _INPUTS
-
t
CLK
IHI'
DIN f - -
CLK
DrIll I--
sa S1SOALE
READY CUI:
\7l
I--
rv
LATCH
T
OE
8287
F>
MEMORY
WE
DI
DO
"
Lkp--
~
Y
l!!!.
MEMORY
!LOWER)
~
(UPPER)
AOo.a
WE I-
{r
DI
WE
-l
~
I
I
DO
I
STI
AG
TV~
...
AH... ALo.. PSEN
STB
11283
~
~
RD
WR
,
OE
..
PCTL8207
1
8CIIII
801.
ADDA/
DATA
,
1T
iI
Ii
iii
\'
IiJCK
Q ...!!..
8213
,.
~~
/
/
,~
OE
-T
11/
'--
'---
8287
,
,
NOTE:
·These components are not necessary when using
provided directly by the 80186.
the 80186. These functions are
Figure 18. 8088/80188, 11207 Single Port Non-ECC Synchronous Systems
&:-172
21Il463-003
inter
8207
82284
) OTHER lCR INPUTS
READY SROY
eLK
"
+
eLK
.-
82288
DEN
DTIli
READY
-
eLK
M/Rl S1 so
eLK
MliO
51
~I
.~
PCTL
AACK
ST::e"s
8207
RO
WR
so
80286
WE
WE
't U::jp--
DATA
'
.'i7
AD
+5V
T\71
T
Iii'f
STaQ
MEMORY
(UPPER)
ADDRIN PSEN
ADDR
~
MEMORY
~
01
(LOWER)
WE
II
I 1r
1
1-1
I
~
8283
-r!!Q
DE
16
8287
.~
g--
T
~
DE
16
.
8287
Figure 17. 80286 Hook-up to 82~7 Non-ECC Synchronous System-Single Port.
6-17'3
DI
DO
.
DO
8207"
Table 8. Processor Interface/Acknowledge Summary
CYCLE
,
FAST
CYCLE
CFS=1
S1...0W
CyCLE
CFS=O
PROCESSOR
REQUEST TYPE
SYNC/ASYNC
INTERFACE
ACKNOWLEDGE TYPE
80286
STATUS
SYNC
80286
STATUS
ASYIiIC
LAACK
80286
COMMAND
SYNC
EAACK
80286
EAACK
COMMAND
ASYNC
LAACK
8086/80186
STATUS
ASYNC
LAACK
8086/80186
COMMAND
ASYNC
LAACK
MULTIBIJS
COMMAND
ASYNC
XACK
8086/80186
STATUS
SYNC
EAACK
8086/80186
STATUS
ASYNC
LAACK
8086/80186
COMMAND
SYNC
EAACK
8086/80186
COMMAND
ASYNC
LAACK
MULTIBUS
COMMAND
ASYNC
XACK
Table 9. Memory Acknowledge Option Summary
Synchronous
Asynchronous
XACK
Fast Cycle
AACK Optimized
for Local 80286
AACK Optimized for
Remote 80286
Multibus Compatible
AACK Optimized
for Local 8086/186
AACK Optimized for
Remote 8086/186
Multibus Compatible"
Slow Cycle
Test Modes
Two special test modes exist in the 8207 to facilitate
testing. Test Mode 1 (non-EGG mode) splits the
refresh address counter into two separate counters
and Test Mode 2 (EGG mode) presets the refresh
address counter to a value slightly less than rollover.
8207 will normally be set in Test Mode 2. Test Mode 2
eliminates memory initialization in EGG mode, This
allows quick examination of the circuitry which
brings the 8207 out of memory initialization and into
normal operation.
Test Mode 1 splits the address counter into two, and
increments both counters simultaneously with each
refresh address update. By generatirig external
refresh requests, the tester is able to check for
proper operation of both counters. Once proper individual counter operation has been established, the
8207 must be returned to normal mode and a second
test performed to check that the carry from the first
counter increments the second counter. The outputs
ofthe counters are presented-on the address out bus
with the same timing as the roW and column addresses of a normal scrubbing operation. During
Test Mode 1, memory initialization is inhibited', since
the 8207, by definition, is in non-EGG mode.
General System Considerations
Test Mode 2 sets the internal refresh counter to a
value slightly less than rollover, During functional
testing other than that covered in Test Mode 1, the
6-174
The RASo_3, GAS O_3, AOO-8, outp!Jt buffers were
designed to directly drive the heavy capacitive loads
associated with dynamic RAM arrays. To keep the RAM
driver outputs from ringing excessively in the system
environment and causing noise in other output pins it is
necessary to match the output impedance of the RAM
output buffers with the RAM array by using series
resistors and to add series resistors to other control
outputs for noise reduction if necessary. Each applica"
tion may have different impedance characteristics and
may require different series resistance values. The
series resistance values should be determined for each
application. In non-EGG systems unused EGG input
pins shoul~ be tied high or low to improve noise
immunity,
The 8207 is packaged in a 68-pin, leadless JEDEG type
A hermetic chip carrier.
210463-003
intJ
-
8207
TOP
BOTTOM
52 AH4
53 AH5
54 AH6
55 AH7
56 AH8
57 POI
56 RFRQ
59 eLK
60 Vss
611mB
62 WRII
63PEi1
54 PCTLB
65 l'IDA
66 WIIA
67
PEA
66 PCTLA'
NOTE:
,
8207 is packaged in a 68 pin JEDEC Type A hermetic leadless chip carrier.
Figure 19. 8207 Pinout Diagram
, 6-175
210463-003
"',
,
•.... _Ie
III-e-
[P)~~IlJ Ii¥1l ~ [N]~!PrtW
8207
ABSOLUTE MAXIMUM RATINGS
NOTICE: Stress above those listed under ':Absolute
Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and
functional operation of the device at these 'or any
other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Ambient Temperature ,
,
Under Bias .............. i • . . . -0" C to +70" C
Storage Temperature ..•....... ' -65°C to +150"C
Voltage On Any Pin With
Respect to Ground •..•. , .•...... -.5V to +7V
Power Dissipation ........ ; ............ 2.5 Watts
D.C. CHARACTERISTICS
(1A = ooe
to
+ 70 oe,
Vec
"
Symbol
= .5.0V ± 10% for 8207; ,± 5% for 8207·2 and 8207·5, "ss = GND)
Min.
Parameter
Max.
Units
Comments
VIL
Input Low Voltage
-0.5
+0.8
V
VIH
Input High Voltage
2.0
Vcc+ 0.5
V
VOL
Output Low Voltage
0.45
V
Note,1
VOH
Output High Voltage
V
Note 1
VROl
RAM Output
Low Voltage
V
Note 1
VROH
RAM Output
High Voltage
V
Note 1
lee
Supply Current
2.4
0.45
2.6
..
400
rnA
TA= 25°C
+10
f.J.A
OV:5 VIN :5 Vee
III
Input Leakage Current
VCl
Clock Input
Low Voltage
-0.5
+0.6 -
V
VCH
Clock Input
HiQ.h Voltage
3.8
Vee + 0.5
V
CIN
Input Capacitance
20
pF
fc= 1 MHz
NOTES:
IOL
=8 rnA and IOH =-0.2 rnA (Typically IOL = 10 rnA and IOH =-0.88 rnAJ
A.C. Testing Input, Output Waveform
A.C. Testing Load Circuli
L..-_ _ _ _~RL
RRAS = 392
RCAS = 392
RAO = 222
RL = 392
::. x:": :::x\-__
at
A.C. Testing inputs (except clock) are driven
2.4V for a logic "1" and O.45V for a logic "0"
(Clock': is driven at 4.0V and 0.45V for logic '.'1"
and "0" respectively). Timing measurements are
made at 2.0V, 2.4V for logic "1" and 0.8 V for logic
"0".
6-179
210463-003
8207
A.C. CHARACTERISTICS
(TA = OOC to 70°C; Vee = +5V ± 10% for 8207; ± 5% for 8207-2, 8207-5; Vss = OV)
Measurements made with respect ID RASo.a , C~ , AO~ , are at 2.4V and O.SV. All other pins are measured
at2.0V and 0.8V. All times in nsec unless otherwise indicated. Testing done with specified test load.
CLOCK AND PROGRAMMING
8207
Ref.
Panuneter
Symbol
a 8207-2
Min.
Mu.
8207-5
Min.
Mu.
Unite Notes
-
IF
Clock Fall Time
10
10
ns
35
-
IR
Clock Rise Time
10
10
ns
35
TCLCL
Clock P8r1od
250
ns
500
500
ns
1
2
ns
3
ns
ns
1
2
ns
3
1
2
3
TCL
TCH
8207
8207
8207·2
82f1T
Clock Low Time
15
8207
TCLCU2·12
8207·2 TCLCU2·12
Clock Hgh Time
CLf(~
8207
20
8207
TCLCLJ3.3
8207·2
TCLCL13-3
40
4
TRlVCL
Reset 10
5
TRTH
Resel Pulse WId1h
6
TPGVRTL
PCTL, POI, RFRO to RESEn Setup
7
TRTLPGX
PCTL,RFRQtoRESET~H~
Setup
CLf(~
8
TCLPC
PCLf( from
9
TPOVCL
POln to CLK~ Setup
10
TCLPOX
POln 10
CLf(~
62.5
125
125
500
TCLCU2·12
ns
1
ns
2
TCLCUa.-3
ns
3
65
ns
4
4 TCLCL
4 TCLCL
ns
125
200
ns
10
10
ns
Ostay
Hold
200
230
235
65
45
ns
60
100
ns
40
65
ns
6-177
5
6
210463-003
8207
A.C. CHARACTERISTICS (Continued)
RAM WARM-UP AND INITIAUZATION
I
,64
I
TCl\l\(Zl
I
WZ from
9LK~ Delay
7
40
SYNCHRONOUS 'IAP PORT INTERFACE
11<
TPEVCl
PE to
12
TKVCl
RD, WR, PE, PCTl to
13
TClKX
t4
TKVCH
CLK~
Setup
30
50
20
30
ns
RDi WR, PE, PCTL to ClK+. Hold
0
0
ns
RD, WR,PCTL to ClK1 Setup
20
30
ns
2
30
30
ns
8,9
2TClCl+30
2TClCl+50
ns
ClK~
Setup
2
1
ASYNCHRONOUS lAP PORT INTERFACE
ClK~
15
TRWVCl
RD, WR to
16
TRWl
RD, WR Pulse Width
17
TRWlPEV
PE from RD,
t8
TRWlPEX
PE to RD,
WR~
Hold
19
TRWLPTV
PCTl from RD,
WR~
20
TRWlPTX
PCTl to RD,
21
'TRWLPTV
22
TRWlPTX
WR~
WR~
PCTl from RD,
PqTL to RD,
Setup
Delay
WR~
Delay
TClCl·30
2TClCl+30
Delay
Hold
TCLCl·50
2TClCl+50
2TClCl+30
Hold
WR~
TClCl·20
TCLCl·30
TClCl·30
8207
8207
8207·2
2TClCl·20
3TClCl+30
6-178.
1
2
3
ns
TClCL·50
2TClCl+50
ns
ns
ns
ns
2
ns
2
ns
1
ns
1
8207
A.C. CHARACTERISTICS (Continued)
RAM INTERFACE
Ref.
,
8207 & 8207·2
Parameter
Symbol
MIn.
Max.
8207·5
MIn.
Max.
UnIts
Notes
10
23
TAVCl
Al, AH, BS to ClK~ Setup
35 + IASR
55 + IASR
ns
24
TCLAX
Al, AH, BS TO ClKI Hold
0
0
ns
25
TCllN
LEN from ClK~ Delay
35
55
ns
26
TClRSl
RA~
from
ClK~
Delay
35
55
ns
28
TClRSH
RASt from
ClK~
Delay
50
70
27
tRCD
RAS to CAS Deley
29
tRAH
Row IC to RAS~ Hold
RAS~
30
IASR
Row AO to
31
IASC
Column AO to CAS~ Setup
32
tCAH
Column AD to CAS Hold
TClCSl
CAS~
ClK~
Delay
11,13,14
12,13,14
1,13,14
TClCU4-10
40
TClCU2-10
30
90
ns
ns
ns
ns
11,13,15
12,13,15
1,13,15,16
13,15,17
5
5
TClCLJ2-26
ns
ns
ns
11,13,19,20
12,13,19
1,13,19
10,18
5
(See DRAM Interface Tables)
TClClt
4+30
TClCLJ1.8+53
TClCLI
'4+30
21
TClCLJ1.6+78
ns
ns
11
12
ns
1
34
TCLCSl
CAS~
Delay
35
35
TClCSH
CASt from ClK. Delay
50
70
. ns
36
TClW
WE from
37
TCLTKl
XACK~
38
TRWLTKH
39
from
CLK~
60
ns
ns
ns
ns
Setup
33
from
TClCU2-25
75
TClCl-25
CLK~
35
55
ns
35
55
ns
XACKf from Rot, WAf Delay
50
60
ns
TCLAKl
AACK~
Delay
35
55
ns
40
TCLAKH
AACKt from CLK~ Delay
50
70
ns
41
TClDl
DBM from
ClK~
35
55
ns
FWR from
WR~
2TClCl-40
TClCl+
TCl-40
TClCl+
TCl-65
from
from
Delay
ClK~
ClK~
Delay
Delay
ECCINTERFACE
42
TWRlFV
Delay 8207
8207-2
ns
ns
1,22
2,22
43
TFVCL
FWR to
ClK~
Setup
40
65
ns
23
44
TClFX
FWR to
ClK~
Hold
0
0
ns
24
25,26
45
TEVCl
ERROR to
ClK~
Setup
20
30
ns
46
TClEX
ERROR to
ClK~
Hold
0
0
ns
47
TClRl
R/W from ClKI Delay
46
TClRH
RlWf from
49
TCEVCl
CE
50
TClCEX
CE to ClK~ Hold
51
TClES
ESTB from
CLK~
toClK~
Delay
Setup
ClK~
40
55
50
70
ns
ns
20
30
ns
0
0
ns
Delay
35
,6-179
55
25,27
ns
210463·003
8207
A.C. CHARACTERISTICS (Continued)
PORT SWITCHING AND LOCK
Symbol
Parameter
CLK~
52
TClMV
MUX from
53
TClPNV
PSEN from
ClK~
ClK~
Min.
Max.
Tel
TCl
60
TCL+35
Delay
Min.
45
Delay
-
8207-5
8207 8. '207-2
Ref.
TCl
TCl
Max.
Units Notes
65
ns
60
TCl+35
ns
ns
28
28
54
TClPSV
PSEl from
55
TlKVGl
lOCK to
ClK~
Setup
30,
50
ns
30,31
56
TCllKx
LOCK to
ClK~
Hold
10
10
ns
30,31
57
TRWllKV
lOCK from
58
,TRWHLKX
RD~, WR~
55
35
ns
31,32
3TClCl+3O
3TClCL+50
ns
31,32
2TCLCl-3O
Delay
lOCK to ROt, WRf Hold
ns
2TClCl-50
REFRESH REQUEST
59
TRFVCl
RFRO to
CLK~
Setup
20
30
ns
60
TCLRFX
RFRO to
ClK~
Hold
10
10
ns
61
TFRFH
Failsafe RFRO Pulse Width
TCLCl+30
TClCl+50
ns
33
62
TRFXCl
Single RFRO Inactive to
20
30
ns
34
63
TBRFH
Burst AFRO Pulse Width
2TClCl+3O
2TClCl+50
ns
33
ClK~
Setup
NOTES:
1
2
3.
4.
5
6
7
a.
9.
10.
11.
Specification when p-OQrammed in the Fast Cycle processor mode (iAPX 286 mode).
Specification when p-OQrammed tn the Slow Cycle processor mode (IAPX 186 mode).
Must be programmed in SJow Cycle prOCBSsa mode.
RESET IS internally synchronized to elK. Hence a set-up time IS required only to guarantee its recognition at a particular cJock edge.
The first programming brt (Poo) is also sampled by RESET going low,
TClPDX IS guaranteed if programming data Is shifted uSing PCLK.
WZ is issued only In ECC mode.
TRWVCL is not required for an asynchronous command except to guarantee Its recognition at a particular clock edge.
Valid when programmed in either Fast or Slow C)Cfe mode.
tASR is a user specified patameter and Its value should be added accordngly to TAVCL.
When programmed in Slow Cycle mode and 125 ns .;;; TCLCL < 200 ns.
12, When programmed in Slow Cycle mode and 200 ns .. TCLCL,
13 Specification tor Test Load conditions.
=
14. tRCO (actual) tRCD (specibcatlon) +0,06 (ACRAsl- 0,06 (ACSAfll where AC = C (test load) - C (actual) in pF, (These are first order approxImations,)
15, tRAH (actual) - tRAtI (specifIcatIon) + 0,06 (ACRAsl- O,0~2IA A~ where AC = C (test load) - C (actual) in pF, (The" are first order approximations,)
< 200 ns.
I
17 When programmed in Fast Cycle mode (8207 only) and 200 ns .. Ta.CL.
18, tASR (actual) = tASR (specification) +0 06 (ACAO) - 0,025 (ACRAsl where AC = C (test load) - C (actual) in pF, (These are first ador apprOXImatIons,)
19, tASC (actual) = IASC (specification) +0,06 (AC",y - 0.025 (ACCAsl where AC = C (test loed) - C (actual) In pF, (These are firllt ordor approxImatIons,)
20. lASC IS a function of clock frequency and thus vanes with changes in frequency A mimmum value is specified.
21. See 8207 DRAM Interface Tables 14 - 18,
22. TWRLFV is defined for both synchronous and asynchronous FWJf.lh systems in which ~ IS decoded directly fran the address inputs to the 8207. TCLFV IS
automaticaUy guaranteed by TeLAV.
23. TFVCL is defined for syncl1ronous FWft'
24. TCLFV IS defined for both synchronou~ and asynchronous FWR 1n systems in which FWRis decoded directly from the address inputs to the 8207.
TClFV IS automatically guaranteed by TCLAV.
25 ERROR and CE are set-up to CLK~ in fast cycle mode and ClKt in sJow cycle mode.
26. EiiiOA is set-up to the same edge as RIW is referenced to. in RMW cycles
27. CE is set-up to the same edge as WE is referenced to in RMW cycles.
28. Speclftca$ion when TCL < 25 ns.
29 Specification when ~CL $I< 25 ns.
30. Synchronous operation only. Must arrive by the second clock failing edge after the clock edge which ,recognizes the command In order to be effective I
31. LOCK must be held active for the entire period the opposite port ITlJst be locked out. One c;tock after the release of LOCK the opposite port will be able to obtain
access to memory.
32. Asynchronous mode only. In this mode a synchronizer stage IS used internally in the 8207 to synchromze up LOCK. TRWLLKV and TRWHlKX are only
required for guaranteeing that LOCK will be recognized· for the reCJ.Iesting pqrt. but these parameters are not reql.ired for correct 8207 operation
33. TFRFH and TBRFH pertain to asynchronous operation only.
34. SIOgie RFRO cann~ by supplied asynchronously
35. tR and tF are referenced from the 3.5V and 1.0V levals.
16. When programmed in Fast Cycle mode (8007 only) and 62.5 ns -~>-+--AJv-.....~>>-tL.J
RESET
External Refresh Requests after RESET
External refresh requests are not recognized by the
8208 until after it is finished programming and prepar·
ing memory for access. Memory preparation includes
8 RAM cycles to prepare and ensure proper dynamic
RAM operation. The time it takes for the 8208 to
recognize a request is shown below.
DIFFERENTIATED RESET
NOTES:
1. Required only when the port synchronization option(s) is altered from its initial default value.
2. Vcc must be stable befor.esystem reset is activated when using this circuit.
eq. 8208 System Response: TRESP = PROG + TPREP
where: TPROG = (40) (TCLCL) which is programming
,
time
TPREP = (8) (32) (TCLCL) which is the RAM
warm-up time
if TCLCL = 125 ns then TRESP = 37 us
Reset
RESET is an asynchronous input, the falling edge of
which is used by the 8208 to directly sample the logic
levels of the PCTl, RFRQ, and PDI inputs. The
internally synchronized falling edge of reset is used
to begin programming operations (shifting in the
contents of the external shift register, if needed, into
the PDI input).
Differentiated reset is unnecessary when the default
synchronization programming is used. (S=O)
Until programming is complete the 8208 registers but
does, not respond to command or status inputs. A
Simple means of preventing commands or status from
occurring during this period is to differentiate the
system reset pulse to obtain a smaller reset pulse for
the 8208. The total time of the 8208 reset pulse and
the 8208, programming time must be less than the
time before the first command the CPU issues in
systems that alter the default port synchronization
programming bit (default is synchronous interface).
The differentiated reset pulse would be shorter than
the system reset pulse by at least the programming
period required by the 8208. The differentiated reset
pulse first resets the 8208, and system reset would
resetthe rest of the system. While the rest of the
system is still in reset, the ,8208 completes its
programming. Figure 4 illuStrates a circuit to ac-,
complish thistas~.
'
8208
RESET
Figure 4. 8208 Differentiated Reset Circuit
Within four clocks after RESET goes active, all the
8208 outputs will go high, except for AOO-2, which
will go low.
OPERAnONAL DESCRIPTION
Programming the 8208,
The 8208 is programmed after reset. On the falling
edge of RESET, the logic states of several input pins
are latched internally. The falling edge of RESET
actually performs the latching, which means that the
logic levels on these inputs must be stable prior to
that time. The inputs whose logic levelS are latched
at the end of reset are the PCTl, REFRQ, and POI
pins.
Status/Command Mode
The processor port of the 8208 is configured by the
states of the PCTl pin. Which interface is selected
depends on the state the PCTl pin at the end of
reset. If PCTl is high at the end of reset, the 80186
Status interface is selected; if it is low, then the
MUlTIBUS or Command interface is selected.
or
There exist two interface configurations, one for
MUlTIBUS memory commands, which is called the
Command interface, and one for 8086,8088,80186
or 80188 status, called the 80186 Status interface.
The Command interface also directly interfaces to the
command lines of the bus controllers for the 8086,
'
"
.
8088.
6:.204 '
230734-001
inter
8208
The 80186 Status interface allows direct decoding of
the status lines for the iAPX 86, iAPX 88, iAPX 186
and the iAPX 188. Table 3 shQws how the status lines
are decoded., Microprocessor bus controller read or
write commands or MUlTIBUS commands can also
be directeo10 the 8208 when in Command mode.
ITable 3. 8208 Response '
Function
820a·Command
8086/80186
Status
Interface
Multlbus or
Command
Interface
PCTL
RD
WR
0
0
0
IGNORE
0
0
1
IGNORE
RE!A.O
0
1
0
IGNORE
WRITE
IGNORE
0
1
l'
IGNORE
IGNORE
1
0
0
READ
IGNORE
1
0
1
READ
INHIBIT
1
1
0
WRITE
INHIBIT
1
1
1
' IGNORE
IGNORE
Refresh Options
Immediately after system reset, the state of the
REFRQ input pin is examined. If REFRQ is high, the
8208 provides the user with the choice between selfrefresh and user-generated refresh with failsafe
protection. Failsafe protection guarantees that if the
user does not come back with another refresh request
before the internal refresh interval counter times out,
a refresh request will be automatically generated. If
the REFRQ pin is low immediately after a reset, then
the user has the choice of a singh:! external refresh
cycle witho~t failsafe, burst refresh or no refresh.
External Refresh without Failsafe
To generate single external refresh requests without
failsafe protection, it is necessary to hold REFRQ low
until after reset. Thereafter, bringing REFRQ high for
one clock period will cause a refresh request to be
generated. A refresh request is not recognized until
a previous request has been serviced.
Burst Refresh
Burst refresh is implemented through the same
procedure as a single external refresh without failsafe
(Le., REFRQ is kept low until after reset). Thereafter,
bringing REFRO high for at least two clOCk periods
will cause a burst of up to 128 row address locations
to be refreshed. Any refresh request is not recognized until a previous request has been serviced (Le.
burst is completed).
No Refresh
It is necessary to hold REFRQ low until after reset.
This is the same as programming External Refresh
without Failsafe. No refreSh is accomplished by
keeping REFRQ low.
Option Program Data Word
The program data word consists of 9 program data
bits, POO-P08. If the first program data bit, PD~ is
set to logic 0, the 8208 is configured to support iAPX
186, 188, 86, or 88 systems. The remaining bits,
P01-P08, may then be programmed to optimize a
selected system configuration. A default of all zeros
in the remaining program bits optimizes the 8208
timing for 8 MHz Intel CPUs using 150 nS (or faster)
dynamic RAMs with no performance penalty. Figure
5 shows the various options that can be programmed
into the 8208.
Internal Refresh Only
Using an Extemal Shift Register
For the 8208 to generate internal refresh requests,
it is necessary only to strap the REFRQ input pin high.
The 8208 may be programmed by using an external
shift register with asynchronous load capability such
as a 74lS165. The reset pulse serves to parallel load
the shift register and the 8208 supplies the clocking
signal (PClK) to shift the data into the~O~ pr?gramming pin. Figure 6 showl! a sample circuit diagram
of an external shift register Circuit.
External Refresh with Failsafe
To allow user-generated refresh requests with failsafe
protection, it is necessary to holCl the REFRQ input
high until after reset. Thereafter, a low-ta-high transition on this input causes Ii refresh request to be
generated and the internal refresh interval counter
to be reset. A high-to~low transition'has no effect on
the 8208. A refresh request is not reCognized until
a ,previous request has been serviced.
Serial data is shifted into the 8208 via the POI pin (33),
and clock is provided by the WE/PClK pin (23), which
generates a total of 9, clock pulses. After programming is complete, data appearing at the input of the
POI pin is ignored. WE/PClK is a dual function pin.
6-205
230734-001
8208
During programming, it serves to clock the external
shift register, and after programming is completed,
it reverts to the write enab,le RAM control output pin.
As the pin changes state to provide the write enable
signal to the dynamic RAM alTay, it continues to clock
the shift register. This does not present a problem
beca,use data at the POI pin is ignored after program· ,
mingo Figure 7 illustrates the timing requirements of
the shift register.
PD~
PD8 PD7
Default Programming Options
After reset, the 8208 serially shifts in a program data
word via the POI pin. This pin may be strapped low,
or connected to an external shift register. Strapping
POI low causes the 8208 to default to the iAPX 186
system configuration. Table 4 shows the character·
istics of the default configuration. If further system
flexibility is needed, one external shift register, like
a 74LS165, can be used to tailor the 8208 to its
operating environment. Figure 8 illustrates an iAPX
186 and 8208 system.
Table 4. Programming, POI Pin Tied to Ground.
PROGRAM
DATA BIT
NAME
POI,.ARITYIFUNCTION
PD~
CFS
MUST BE ZERO
S
'S' =
S=
PD2
RFS
RFS = 0 FAST RAM
RFS = 1 SLOW RAM
Fast processor clock frequency (8 MHz)
PD3
RB
RAM BANK OCCuPANCY
SEE TABLE 2
Fast RAM (Note 1)
PD4
CI1
COUNT INTERVAL BIT 1; SEE TABLE 6
PDS
CIO
COUNT INTERVAL BIT 0; SEE TABLE 6
PD6
PLS
PLS = 0 LONG REFRESH PERIOD
PLS = 1 SHORT REFRESH PERIOD
PD7
FFS
FFS = 0 FAST CPU FREQUENCY
= 1 SLOW CPU FREQUENCY
poe
x
'PD1
Synchronous 80186 interface
,
0 SYNCHRONOUS
1 ASYNCHRONOUS
2 RAM banks occupied
Refresh interval uses 118 clocks
128 row refresh in 2 ms; 256 row refresh
in 4 ms
m
X=OAACK
x,= 1 XAcK
"
Figure 5. Program Data Word
Advanced ACK strobe
NOTE:
1. For iAPX 186 systems either slow or fast (150 or 100 ns)
RAMS are ok t9 use.
ClK
~~~ x::
~ ,TLOAD, . :
6
POI ==::)(~---'='---'--::-:PO:-:'o------"""X
P01 ,
X
P02
NOTES:
TRTVCL
TPGVCL
TCLPC
TLOAO
- ' Reset is an asynchronous input, if reset occurs before'TRTVCL, then it is guaranteed to be recognized.
- Minimum POI '(aJid time prior to reset going low.
- MUx/PCLK delay.'
- Asynchronous load data propagation delay.
« Figure 6. Timing Illustrating External Shift Register Requirements for Programming the 8208.
6-206
230734.()()1
intJ
8208
+5V
0---41'~'-o-o-.o O~~~
, •
I
I
I
I
8208
8208
RESET
......-----1 PD.
WElPCLK
t--~~
ClK
~-------+----------~------------------~RESET
Figure 7. External Shift, Register Interface
+5V
REFRQ
WR
SRDY ClKOUT
X,
·x
. 2
so
§1
ClK
8208
80186 !i2
AACK
~
0, ,
( MEMORY
LOWER)
UPPER)
.( ~EMORY
401).8
2164A-15
2164A-15
en0,1
WE
ALE
WE DilDO
WE D'~DO
8283
ADDRESS
lATCHES
Figure 8. 8208 Interface to an 80186
6-207
230734-001
inter
, 8208
Synchronous/Asynchronous Mode
(S program bit)
Table ,5. Microprocessor Clock'
Frequency Options.
,
Program Bits
The 8208 may be independently configured to ac~t
syl'lchronoufj or asynchronous commands (RD, WR,
PCTL) and Port Enable (PE) via the S program bit.
The state of the S programming bit determines
whether the interface is synchronous or
asynchronous.
While the 8208 may be configured with either the
80186 Status or Command (MULTIBUS) interface in
the Synchronous mode, certain restrictions exist in
the Asynchronous mode. An Asynchronous-Command
interface using the, control lines of the MULTIBUS is
supported, and an Asynchronous-80186 Status interface using tile status lines of the 80186 is supported,
with the use of TIL gates as illustrated in Figure 2. '
In the 80186 case, the TIL gates are needed to .
guarantee that status does not appear at the 8208's
inputs too much before address, so that a cycle would
start before address was valid.
Processor
Clock
Frequency
0
iAPX 86,,88,186
5 MHz
0
1
iAPX 86,88,186
8 MHz
RAM
S~eed
CFS
FFS
0
Option (RFS program bit)
The RAM Speed programming 'option determines
whether RAM timing will be optimized for a fast or
slow RAM. Whether a RAM is fast or slOvV is measured
relative to the 2118-10 (Fast) or the 2118-15 (Slow)
RAM specifications.
Refresh Period Options
(CIO CI1 and PLS program bits)
The 8208 refreshes with either 128 rows every 2
milliseconds or the 256 rows every 4 milliseconds.
This translates to one refresh cycle being executed
approximately once every 15.6 microseconds. This
rate can be changed to 256 rows every 2 milliseconds
or a refresh approximately once every 7.8 microseconds via the Period Long/Short, program bit PLS,
. programming option.
Microprocessor Clock Cycle Option
(CFS and FFS program bits
The 8208 can be programmed to interface with
microprocessors with slow cycle microprocessors like
the 8086, 8088, 80186, and 80188 cycle timing. The
CFS bit configures the microprocessor interface to
accept signals from either microprocessof group or
commands from MULTIBUS. The CFS programming
bit must be programmed to logiC O.
The Count Interval 0 (CIO) and Count Interval 1 (CI1)
programming options allow the rate at which refresh
requests are generated to be increased in order to
permit refresh requests to be generated close to the
15.6 or 7.8 miorosecond period when the 8208 is
operating at reduced frequencies. The interval between refreshes is decreased by 0%,10%,20%, or
30% as a function of how the count interval bits are
programmed. A 5% guardband is built-in to allow for
any clock frequency variations. Table 6 shows the
refresh period options available.
'
The FFS option is used to select the speed of the
microprocessor clock. Table 5 shows the various
microprocessor clock frequency options that can be
programmed. The external clock frequency must be
, programmed so that the failsafe refresh repetition
circuitry can adjust its internal timing accordingly to
produce a refresh request as programmed.
Table 6. Refresh Count Interval Table
Count Interval C11, CIO (8208 Clock Periods)
Freq.
(MHz)
8
5
Ref.
Period
PLS
FFS
00
(0%)
01
(10%)
10
(20%)
11
(30%)
0
1
1
118
106
94
82
0
0
1
59
53
47
41
15.6
0
1
0
74
66
58
50
7.8
0
0
0
37
33
29
25
(~)
CFS
15.6
7.8
6-208
230734-001
8208
The numbers tabulated under Count Interval represent the number of clock periods between internal
refresh requests. The percentages in parentheses
repr~nt the decrease in the interval between refresh
requests. Note that all intervals have a built-in 5%
(approximately) safety factor to compensate for minor
clock frequency deviations and non-immediate
response to internal refresh requests.
Processor Timing
In order to run without wait states, AACK must be
used and connected to the SRDY input of the
appropriate bus controller. AACR is issued relative
to a P9int within the RAM cycle and has no fixed relationship to the processor's request. The timing is
such, however, that the processor will run without wait
states, barring refresh cycles, and bank precharge.
In slow cycle, fast RAM configurations (8086,80186),
AAa
AO o.s
Other Outputs
Ic = 1 MHz
'---.oJ""
Co.s
=
=
::::c.
c,-
::' 24)~. .
A.C. Testing inputs (except clock) are driven at
2.4V for a logic ".1" and 0.45V for a logic "0"
(clock is driven at 4.0V and 0.45V for logic" 1"
and "0" respectively). Timing measurements are
made at 2.0V, 2.4V for logic "1" and 0.8 V for logic
= 150 pF
150 pF
= 200 pF
RRAS 390 -::- CRAS
RCAS = 390
CCAS =
RAO
220
CAO
RL :: 390
CL ::
:_::--JX,",,__
0_2:_:_ _ _
.150 pF
"0",
6-211
230734-001
,
I
inter
"
8208
A.C. CHARACTISTICS
=0 to 70 C 'E:c = + 5V ± 5%) •
-
A19
A18
______ ______________________
~
~
~l
~>-----1-~----------------------~ ~o
8207
7485
Figure 6. Non-Interleaved 8207 Selection Ci~cuit
With designs using interleaving, the least significant word address lines are connected to the BSO, BSI
inputs. With two banks of RAM, At from the Intel processor is connected to BSO. A2 is connected
to 'BSt, but not allowed to function witil four banks are present. However, A2 must still be used
since addresses increase sequentially. Two possible ways of implementing this are shown in Figure
7 below.
240
A19
, A19'
AH7
A18
8207
8207
A2
A2
BSl
~
Al
Al
A18
A
~--
PE
F
7485
Figure 7. Interleaved 8207 Selection Circuits
6..230
230822-{JOl
8207
The final consideration is for the RAS/CAS outputs. Remember that when the RBO, RBI bits are
programmed for two banks, then RASQ, 1 operates in tandem (non-ECC mode/ECC mode - the 00
outputs also work in tandem). Figure 8 shows the proper layout.
RAM BANK
RASO/CASO
RAS2ICAS2
OPTIONAL BANK
8207
2
RASlICAS1
OPTIONAL BANK
RAS3ICAS3
OPTIONAL BANK
Figure 8. RAM Bank Layout
Write Enables - Byte Marks
The write enable supplied by the 8207 cannot drive the RAM array directly. It is intended to be
NAND with the processor supplied byte marks in a non-ECC system. In error-corrected systems, the
write enable output should be inverted before being used by RAMs. Only full word read/writes are
allowed in ECC systems. The changing of byte data occurs in the 8206 EDCU.
For single and dual port systems, the byte mark data (AO, BHE) must be latched. The 8207 can (and
will) change the input addresses midway through a RAM cycle.
Memory Warm-up and Initialization
After programming, the 8207 performs 8 RAM warm-up cycles. The warm-up cycles are to prepare
the RAMs for proper operation. If the 8207 is configured for ECC, it will then prewrite zeros into
the entire array.
All RAS outputs are driven active for these cycles, once every 32 clock periods. The prewrite cycles
are equivalent to write cycles, except all RAS and GAS will go active, data is generated by the 8206,
and the address is generated by the 8207.
RAM Cycles/Timings
Tables 12 and 13 of the 8207 Data Sheet show on what clock edge each of the 8207 outputs are generated.
This, together with the timing waveforms and A.C. parameters, allows the user to calculate the
timings of the 8207 for each of its configurations. To make the job easier, Tables 14-18 of the 8207
Data Sheet precalculate dynamic RAM timings for each 8207 configuration and type of cycle. All
that is required is to plug in numerical values for the 8207 'parameters.
6-231
230822-001
Write Cycles.
The 8207 always issues WE after CAS has gone valid. These types of cycles are known as "late writes."
The 8207 does this primarily to interface to the iAPX286 processor bus timings. Late writes require
separate data in and data out traces to the RAM array, plus the additional drivers.
Data Latches
The 8207 is designed to meet data setup and hold times for the iAPX86 family processors when using
a synchronous status interface (see Microprocessor Interface section). Other types of interfaces will
require external data latches. This is because the CAS pulse is a fixed length - the user has no control
(besides programming options) over lengthening CAS; When CAS goes inactive, data out of the RAMs
will disappear. Asynchronous interfaces should use XACK or LAACK to latch the data.
6-232
230822'{)01
inter
8207
CHAPTER 4
.MICROPROCESSOR INTERFACES
The 8207 is designed to be directly compatible with all Intel iAPX86, 186, 188, and 286 processor",.
For maximum performance, the 8207 will directly decode the status lines and operate off of the processor's clock. Additionally, the;. 8207 interfaces easily to other bus types that support demultiplexed
address and data with separate read and write strobes.
Bus interfaces
The 8207 easily supports either an asynchronous or synchronous command timing. The command
'.
timing can also bel adjusted for various processors via the PCTL pin.
MEMORY COMMANDS
There are four inputs for each port of the 8207 that initiate a memory cycle. The input pins are W.!,
· RD, PCTL, and PE. Th~ first three inputs connect directly to the iAPX 86. 88, 186, 188 SO-S2
outputs, respectively. For the 80286, the same connections are used except that PCTL is tied to ground.
In all configurations PE is decoded from the address bus. Multibus type commands use the same
input setup as the 80286.
.,
COMMAND/STATUS INTERFACE
·The status interface for the 80186 and the 80286 differ both in timing and meaning. The 8207 can
be optimized for either processor by programming the PCTL input pin at RESET time. S2 in 80186
systems, connects directly to PCTL. When the processor is reset it drives Si high for one clock, then
tristates it. A pullup resistor to +S will program the PCTL input: for the 80186 status interface when
RESET goes inactive. A pullup is required only if no component has this pullup internally.
To optimize the 8207 for the 80286 interface, pcn is tied to ground and not used in 80286 systems.
Multibus commands are similar in meaning to the 80286 status interface, and are programmed the
same way. In Multibus type systems, PCTL can be used as an inhibit to allow shadow memory. PCTL
would be driven high, when required, to prevent the 8207 from performing a memory cycle. It would
be connected to the Multibus INH pin through an inverter.
.
SYNCHRONOUS/ASYNCHRONOUS COMMANDS
Each port of the 8207 can be configured to accept either a synchronous or asynchronous (via
programming bits) memory request. Minimum memory request decode time .(and maxjmum performance) is achieved using a synchronous status interface. This type of interface to t\le processor
requires no logic for the user to implement.
· An asynchronous interface is used with Multibus bus interfaces when the setup and hold times of
the memory commands cannot be guaranteed. Synchronizers are added to the inputs and will require
up to two clocks for the 8207 to recognize the command. It should be obvious that better performance
will result if the 8207's clock is run as fast as possible.
Figure 2 of the 8207 Data Sheet shows various combinations of interfaces. The additional logic for
the asynchronous interfaces is used to either lengthen the command width, to meet the minimum 8207
spec, or to make sure the command does not arrive too soon before the address has stabilized.
PORT ENABLE
.. i
. The FE inputs serve t2..9.ualify a metnory·request. A RAM cycle, once started, Cannot be stopp~.d.
A RAM cYcle starts if PE is seen active at the proper clock edge and a valid coinmand is recognized.
If FE is activated after a command has gone active and iI).active, no Cycle will start. ..
. .
·6-233
230822-_K
Q
-- -1>
80286
LOCK
Figure 12a. Synchronous interface
6-236
230822"()01
inter
8207
80288
LOCK ~
rl> 1
0
82288
PR
1
Q
cLFi Q
ALE
L:r
0
rl>
PR
CLR
Q
Q
1
82284
RESET
Rm5Y'
Figure 12b. Asynchronous interface
Multibus LOCK can be used if it meets the 8207 requirements. If the LOCK timing cannot be guaranteed,
then additional logic is necessary. The logic would issue LOCK whenever a Multibus command is
recognized. The drawback t6 this is that MUX cannot switch during the RAM cycle. This would delay
the other port's memory access by one or two clocks.
DEADLOCK
The designer should ensure that a deadlock hazard has not been created in the design. The simple
interfaces shown previously will not create a deadlock condition when the 8207 controls all system
memory. If LOCK is issued by both ports, then the above logic would need to be modified t6 remove
'
LOCK.
Figure 13 shows an illustration of the problem with a single LOCK input.
LOCK
MUX
I-'---f
LOCK
8207
lOP
Figure 13. Single LOCK Input Circuit
6-237
230822'()01
8207
Suppose the 8207- starts a locked string transfer for the processor". The Multibus bus port requests
-a memory cycle but must wait for the processor to remove LOCK. But the processor must access
Multibus as part of the locked string transfer. We now have a deadlock. The solution is to force LOCK
inactive whenever an access is made to non-8207 memory by the processor. By doing this we have
now violated the purpose of LOCK, since the Multibus port could change data. Another solution is
to ensure that locked data does not exist in physically separate memory.
8207 Acknowledge's
The 8207 in non-ECC mode has two active acknowle~er port, AACK and XACK. The AACK
output is configured into either an "early" or ")ate" AACK based on the SA, SB bits in the program
data word. In EeC systems there is on~ Acknowledge per port, and it is configured to anyone of
the three (EAACK, LAACK or XACK) by the programming bits.
The AACK pin is optimized for either the 80286 or the 8086, based upon the CFS programming bit
(fast = 80286; slow = 8086). XACK conforms to the Multibus bus specification. XACK requires a
. tri:state buffer and must not drive the bus directly.
In synchronous systems, XACK will not go active if the memory command is removed prior to the
clock period that issues XACK. In asynchronous systems, the AACK pin can also serve as an
advanced RAM cycle timing indicator.
Data out, in synchronous systems, should not have to be latched. The 8207 was designed to meet the
data setup and hold times of Intel processors, the 8086 family, and the 80286. In asynchronous systems,
the 8207 will remove data before the processor recognizes the Acknowledge (LAACK or XACK). In
these systems, the data should be latched with transparent type latches (Intel 8282/8283).
Output Data Control
Non-ECC
In single port systems, Intel processors supply the necessary timing signals"to control the input or
output of data to the RAMs. These control signals are DEN and DTlit Refer to the microprocessor
handbook for their explanation. If these signals are not available, then PSEN and DBMprovide the
same function. They can be used directly to control the 8286/8287 bus drivers of the 8207 ..
Because of the single set of data inlout pins of the RAMs, data must be multiplexed between the
two ports in dual port systems. The 8207 provides two outputs for contention-free switching. PSEL
operates the same as the MUX output, in that a high selects Port A and a low selects Port B. PSEN
acts to enable the selected port. The timing is shown in the 8207 Data Sheet, Port SwitChing Timing
section.
The easiest means' of using PSEL and PSEN is shown in Figure 14. At no time will both ports ,be
enabled simultaneously.
PSEL
PSEN
I
1
g
I~
:
OE
DOE
PORTA
I
PORTS
1
Figure 14.PSEL and PSENlnterface Circuit
6-238
230822-001
8207
Data Bus - Single Port.
Recall that the 8207 always perforrr,s a late write cycle and that this· requires separate data in and
out buses. One option for the data bus is shown in Figure 3 of the 8207 Data Sheet. It requires separate
data in and out traces on the processor board.
The second option is to keep the processor's combined data, bus but separate the data at the 8207
RAM. This is shown in Figure 15.
RAM
ARRAY
PE
'DBM
TO;tP DATA
BUS
Figure 15. Data Bus Circuit
Data Bus - Dual Port
Non-ECC
The multiplexed data of the 8207 RAM must be kept.isolated so that an access by one port does not
affect another port. Figure 16 illustrates the control logic.
6-239
230822-001
inter
8207
RAM
ARRAY
PORTB
PORTA
S
Y
S
Y
S
S
T
E
M
T
E
M
B
U
B
U
S
S
OBM ........~
PE~"""'_
PSEL
PSEN
D - - -.......+-t A
c::----.....
-4..,-/
Figure 16. Dual Port Data Bus Control Circuitry
6-240
\
230822-001
8207
CHAPTER 5
~207 WITH ECC (8206)
This section points out the proper control of the 8206 EDCU by the 8207.
The 8207 performs error correction during read and refresh cycles (scrubbing), and initializes memory
after power up to prevent false errors from causing interrupts to the proceSsor. Since the 8207 must
refresh RAM, performing scrubbing during' refresh allows it to be accomplished without any
additional performance penalty. Upon detection of a correctable error during scrubbing, the RAM
refresh cycle is lengthened slightly to permit the 8206 to correct the error and for the corrected word
to be rewritten into memory. Uncorrectable errors detected durJng scrubbing are ignored, since the
processor may never access that memory location.
Correctable errors detected during a memory read cycle are corrected immediately and written back
into memory.
Synchronous/Asynchronous Buses
The many types of configurations that are supported by the 8207/8206 combination can be broken'
down into two classes: ECC for synchronous or for asynchronous buses.
In synchronous bus systems, performance is optimized for processor throughput. In asynchronous
buses, performance is optimized to get valid data onto the bus as quickly as possible (Multibus). While
possible to optimize the 8207/8206 for processor throughput in Multibus systems, it is not Multibus
compatible. The performance optimization is selected via the XA/XB and SA/SB programming bits.
When optimized for processor throughput, an advanced acknowledge (AACK - early or late) is issued
at some point (based on the type of processor) so that data will be valid when the processor needs it.
When optimized for quick data access, an XACK is issued as soon as valid data is known to exist.
If the data was invalid (based on the ERROR flag), then the XACK is delayed until the 8206 corrects
the data and the data is on the bus.
The first example is known as "correct always" mode. The 8206 CRCT pin is tied to ground and
the 8206 requires time to do the correction. Figure 17 shows this implementation. The quick data
access method is known as "correct on error." The CRCT pin is tied to the RIW output of the 8207.
When CRCT is high, the 8206 does not do correction, but still checks the data. This delay is typic~lly
half of the first. If an error happens, the cycle becomes a RMW and XACK is delayed slightly' so
.
that data can be corrected.
The correct on error mode is of no real benefit to non-Multibus users. The earliest acknowlege (BAACK)
is delayed by one clock to allow for the delays thrQ.ugh the 8206. This imposes a 1 wait state delay.
Byte Marks
The only real difference to the 8207 system when adding the 8206 is the treatment of byte writes. Because
the encoded check bits apply only to a whole word (including check bits), .byte writes must not be
permitted at the RAM. Instead, the altering of byte data is done at the 8206. The byte marks
previously sent to RAM are now ,sent to the 8206. These byte marks must also qualify the output
enables of the data drivers.
The DBM output of the 8207 is meant to be nanded with the processors byte,marks. This output is
activated only on reads or refreshes. On write cycles, this output stays high which would force the
8206 byte mark input low. When low, the internal 8206 data out buffers are tristated so that new
data may be gated into the device:
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230822-001
8207
.
RTs:~
RAM
AD DR
WE
ARRAY
+5
DI
8207
CBI DO
DBM
WZ
ERROR
-,CE
Rm
PSEN
16
FWR
AO
BHE
Figure 17. 8206 Interface to the 8207
Read Modify Writes - ECC
A RMW cycle occurs whenever a processor wants to do byte writes or when the 8207 has detected
an error during read or refresh (scrubbing) cycles. A byte write is detected by the FWR input to the
8207 and is based on the processor supplied byte marks.
At the start of a RMW cycle, DBM stays high, which, when qualified with the byte marks, will enable
the..:!!ata out buffer of the 8206 for the unmodified byte, and tristates the buffer for the new byte;
R/W is high, which tells the 8206 to do error detection and correcting (if CRCT is low). The 8206
can latch data and check bits from the RAM via the STB input, but the 8207 does not use this feature.
Instead,the 8207 keeps CAS active the entire length of the,RMW cycle to hQld data at the 8206. The
new byte data from the processor goes to the 8206 and to the RAM, The 8207 would have corrected
any errors just read, so the old and new bytes of data, plus their check bits, are available at the RAM,
and the 8207 generates a write pulse. The data driver for the unmodified byte must not have been
enabled, otherwise erroneous data would be written to RAM and possibly made valid (if it was stable)
by the 8206.
'
,
Data Buffer Control - ECC
The control of the data buffers i~ essentially the same as in non-ECC systems, with a few exceptions.
230822-001
8207
.
,
The processor's byte marks must now qualify the output enable logic. The reason was described earlier
in the RMW section. This applies to both single and dual Port configurations. A refresh cycle outputs
all the control signals that a read cycle will, except for an.acknowledge. If complete buffer control
is left to the 8207, then it would occasionally (during refreshes) put data on the processor bus. The
DEN and DTiR signals must be qualified by the PE input.PE would have to be latched for the entire
cycle by PSEN.
.
Test Modes
Neit~er
of the two test mocles of the 8207 are to be ,us~d in a design. Both test modes reset the refresh
address counter to a spc;cific value, which interrupts the refresh sequence and causes loss of data.
In error corrected systems, a reset pulse causes the 8207/8206 to write over the entire RAM array.
Test Mode 2 appears to bypass theprewrite sequence. But, the refresh counter is reset to a value of
IF7 (H). So, besides interrupting the refresh sequepce, the 8207 still prewrites the 8 locations specified
by the counter.
To not overwrite the RAM data, the 8207 RESET will have to be isolated from the system reset logic
in ECC systems.
230822-001
','"
APPENDIX I
8207/8208
Performance, ,
,
The following performance charts were based upon Figure 3 in the 8207 Data Sheet, and apply to
the 8208 as well. All RAM access delays are based upon Intel dynamic RAMs. The charts show the
performance of a single cycle with no precharge, refresh, port switching, or arbitration delays.
Th~ read access catculations are: the margin'between'the 8207 'starting a memory cycle to ~ata valid
at the processor - 8207 RAS or CAS from clock delaY--'DRAM RAS or CAS access - 8286 propagation delay - processor setup.
,Assume the RAS/CAS drivers are loaded with ISO pf, and'the 8286 is driving a 300 pf data bus.
80286 (example)
,RAS Access:
3TCLCL - 8207 TCLRSL - 2118 tRAC 8286 TIVOV - 80286 t8
= (3)62.5 - 35 max - 100 max '- 22 - 10
= 20 ns
CAS Access:
2 TCLCL - 8207 TCLCSL - 2164A tCAC 8286 TIVOV - 80186 TDVCL
= (2)125 - 115 max - 85 max - 22 - 20
= 8 ns
80186 (example)
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inter
8207
,8207 Performance (EDC synchronous status Interface)
Table 5a. Walt States for Different fJP and RAM Combl,natlons
Walt
stet.. at full CPU speed
CPU
80286
80186,
8086/88-2
8086/88
RAM speed
Freq
8 MHz
8 MHz
5 MHz
100 ns
120 ns
150 ns
1-RD~ WR
3-Byte WR
CO (3)
1-RD, WR
3-Byte WR
CO
2-Read
1-Write
3-Byte WR
" C2
1-RD, WR
3-Byte WR
C4
1-RD,WR
;3-Byte WR
1-RD,WR
3-Byte WR
C4
1
1
C4,
200 ns
Not (1)
compatible
with RAM
parameters
1
C6
C6
C6
1-RD, WR
3-Byte WR
C4
8207 Performance (EDC synchronous status Interface)
Table 5b. fJP Clock Frequency for Differenc
Maximum frequency for
one walt-atate (4)
CPU
80286
80186,
8086/88-2
8086/88
Freq
RAM speed
100 ns
I
120 ns
150 ns'
7.3 MHz
CO
8 MHz
8 ty1Hz
f.IP and "RAM Combinations
FULL SPEED
200 ns
6 MHz
CO
7 MHz
C4
5 MHz
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230822-001
8207
I
8207 Performance (Non-EDC synchronous status interfaCe)
Table 6a. Walt States for DI~erent lAP and RAM Combinations
~alt states at full CPU speed
CPU
80286
Freq
8 MHz
80186,
8086/88-2
8086/88
RAM speed
8 MHz
5 MHz,
100 ns
120 ns
150ns
200 ns
CO(3)
1-Read
O-Write
C1
1-Read
O-Write
C1
Not(1)
compatible
with
0
0(2)
RAM
parameters
0
0
C3
0
C3
C3
0
0
0
C3
C3
C3
C3
Table 6b., lAP CIC)ck Frequency for Different lAP and RAM Combinations
Maximum frequency for
no walt-state (4)
CPU
Freq
80286
8 MHz
80186,
8086/88-2
8 MHz
8086/88
5 MHz
RAM speed
100 ns
120 ns
7 MHz
150 ns
6 MHz
200 ns
5.3 MHz
7 MHz
FULL SPEED
(1) The 2164A tRAH parameter is not satisfied.
(2) 150 ns 64K DRAMs with tCAC = 100 ns won't run with 0 wait-states, because they have a longer CAS
access time than the 2164A-15 (tCAC = 85 ns).
(3) Numbers in lower right corners are the programmed configurations of the 8207.
(4) To meet read access time.
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8207
8207 Performance (multibus interface)
This is an asynchronous, command interface. Worst case data and transfer acknowledge
(XACK#) delays. Including synchronization and data buffer delays, are:
Table 7a. Non·EDC system
,
Data access time
RAM speed
100 ns
120 ns
150 ns
200 ns
289ns
299ns
322ns
380ns
XACK# access time
333ns
450ns
Table 7b. EDC system
RAM speed
100 ns
Data access time (read)
XACK# access time
359ns
(324 ns)(1]
150 ns
200 ns
369ns
392ns
(334 ns) (357 ns)
450ns
(415 ns)
120 ns
400 ns-RD, WR
588 nS-Byte Write
520 ns-RD, WR
806 ns-Byte WR
(1) Numbers in parentheses are for when 8206 is in check-only mode (8206 doesn't do error correction
until after an error is detected.
230822-001
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