1984_Intel_Microsystem_Components_Handbook_Volume_2 1984 Intel Microsystem Components Handbook Volume 2
User Manual: 1984_Intel_Microsystem_Components_Handbook_Volume_2
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LITERATURE
In addition to the product line Handbooks listed below. the INTEL PRODUCT GUI DE (no charge. Order
No. 210846) provides an overview of Intel's complete product line and customer services.
Consult the INTEL LITERATURE GUIDE fora complete listing of Intel literature. TO ORDER literature
in the United States. write or call the Intel Literature Department. 3065 Bowers Avenue. Santa Clara. CA
95051. (800) 538-1876. or (800) 672-1833 (California only). TO ORDER literature from international
10catlOm. contact the nearest Intel sales office or di;tributor (see listings in the back of most any Intel
literature).
1984 HANDBOOKS
U.S. PRICE*
Memory Components Handbook (Order No. 210830)
Contain; all application notes. article reprints. data sheets. and other de;ign information
on RAMs. DRAMs. EPROMs. E2PROM;. Bubble Memone;.
$15.00
Telecommunication Products Handbook (Order No. 230730)
Contain; all applicatIOn note,. article reprint;. and data ;heet; for telecommunIcatIOn
products.
7.50
Microcontroller Handbook (Order No. 210918)
Contains all application notes. article reprints. data ;heet;. and de;lgn information for the
MCS-48. MCS-51 and MCS-96 families.
15.00
Microsystem Components Handbook (Order No. 230843)
Contains application notes. article reprint;. data sheets. technical paper; for microproces;ors and penpherals. (2 Volumes) (Individual User Manuab are abo available on the
8085. 8086. 8088. 186. 286. etc. Consult the Literature GUide for prices and order
numbers.)
20.00
Military Handbook (Order No. 210461)
Contains complete data sheets for all military products. InformatIOn on Leadless Chip
Carriers and on Quality Assurance is also included.
10.00
Development Systems Handbook (Order No. 210940)
Contains data sheets on development systems and software. support options. and design
kits.
10.00
OEM Systems Handbook (Order No. 210941)
Contains all data sheets, application notes, and article reprints for OEM boards and
systems.
15.00
Software Handbook (Order No. 230786)
Contains all data sheets, applications notes, and article reprints available directly
from Intel, as well as 3rd Party software.
10.00
* Prices are for the U.S. only.
intJ
MICROSYSTEM
COMPONENTS
HANDBOOK
.
VOLUME 2
1984
Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in
this document nor does it make a commitment to update the Information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local sales office to obtain the latest specifications before placing your order.
The following are trademarks of Intel Corporation and may only be used to identify Intel Products:
BITBUS, COMMputer, CREDIT, Data Pipeline, GENIUS, i, ~, ICE, iCS, iDBP,
iDIS, 12 1CE, iLBX, im , iMMX, Insite, Intel, intel, intelBOS, Intelevision, inteligent
Identifier, inteligent Programming, Intellec, Intellink, iOSP, iPDS, iSBC, iSBX,
iSDM, iSXM, Library Manager, MCS, Megachassis, MICROMAINFRAME, MULTIBUS, MULTICHANNEL, MULTIMODULE, Plug-A-Bubble, PROMPT,
Promware, QUEST, QUEX, Ripplemode, RMX/SO, RUPI, Seamless, SOLO,
SYSTEM 2000, and UPI, and the combination of ICE, iCS, iRMX, iSBC, MCS, or
UPI and a numerical suffix.
MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk Data
Sciences Corporation.
* MULTIBUS is a patehted Intel bus.
Additional copies of this manual or other Intel literature may be obtained from:
Intel Corporation
Literature Department
3065 Bowers Avenue
Santa Clara, CA 95051
© INTEL CORPORATION. 1983
Table of Contents
CHAPTER 1
OVERVIEW
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . • . . . . . . . . . . . . .
1-1
CHAPTER 2
MCP-80/85 MICROPROCESSORS
DATA SHEETS
8080Al8080A-1/8080A02, 8-Bit N-Channel Microprocessor ...•.....•...............
8085AH/8085 AH-2/8085AH-1 8-Bit HMOS Microprocessors .........................
8085A18085A-2 Single Chip 8-Bit N-Chanhel Microprocessors .............•.......•
8155H/8156H/8155H-2/8156H-2, 2048-Bit Static HMOS RAM
with 1/0 Ports and Timer ........•..•.................... ',' . . . . . . . . . . . . . . . . . ..
8155/815618155-218156-2, 2048-Bit Static MOS RAM with 1/0 Ports and Timer .,......
8185/8185-2, 1024 x 8-Bi\ Static RAM for MCS-85 .•..........•.•...................
8205 High Speed 1 Out of 8 Binary Decoder ......................................
8212 8-Bit InpuVOutput Port .....................................................
8216/8226, 4-Bit Parallel Bidirectional Bus Driver ..................................
8218/8219 Bipolar Microcomputer Bus Controllers for MCS-80 and MCS-85 Family ...
8224 Clock Generator and Driver for 8080A CPU ..................................
8228/8238 System Controller and Bus Driver for 8080A CPU ...................... :.
8237A18237A-4/8237A-5 High Performance Programmable DMA Controller ..........
8257/8257-5 Programmable DMA Controller ................................... ',' ..
8259A18259A-2/8259A-8 Programmable Interrupt Controller ........................
8355/8355-2, 16,384-Bit ROM with 1/0 .....................•.•....•.•.............
8755A18755A-2, 16,384-Bit EPROM with I/O .......................................
2-1
2-10
2-26
'2-30
2-42
2-45
2-50
2-55
2-63
2-68
2-79
2-84
2~8
2-103
2-120
2-138
2-146
CHAP:TER3
IAPX 86, 88, 186, 188 MICROPROCESSORS
APPLICATION NOTES
AP-113 Getting Started with the Numeric Data Processor .....•.......•...... :......
AP-122 Hard Disk Controller Design Using the Intel 8089 ...........................
AP-123 Graphic CRT Design Using the iAPX 86/11 .................................
AP-143 Using the iAPX 86/20 Numeric Data Processor
in a Small Business Computer ...........................................•
AP-144 Three Dimensional Graphics Application of the
iAPX 86/20 Numeric Data Processor .......................•.••............
AP-186 Introduction to the 80186 ............................................•....
DATA SHEETS
iAPX 86/10 16-Bit HMOS Microprocessor ..............•..•....•...•.•......•.•...
iAPX 186 High Integration 16-Bit Microprocessor ....•.............................
iAPX 88/10 8-Bit HMOS Microprocessor .................................•......•.
iAPX 188 High Integration 8-Bit,Microprocessor ........ .' .....•..... ~ ..............
8089 8/16-Bit HMOS 1/0 Processor .......•.......................•••••.•••.......
8087 Numeric Data Coprocessor ...........•.......••...•..•....•................
80130/80130-2 iAPX 86/30, 88130 iRMX 86 Operating System Processors .............
80150180150-2 iAPX 86/50, 88/50, 186/50 CP/M*-86 Operating System Processors •...
8282/8283 Octal Latch ..............................•....•.•..•••..•..••.•......
8284A Clock Generator and Driver for iAPX 86, 88 Processors •.•.•...•...••...••..•
8286/8287 Octal Bus Transceiver ......... ~ ....................•.... '" • . . . • . • • . • ..
8288 Bus Controller for iAPX 86, 88 ....•.......•.......•........•..••.•...•......
8289 Bus Arbiter ..........•........................................,....•.. ,•..•..
3-1
3-62
3-123
3-194
3-217
3-256
3-334
3-360
3-412
3-439
3-494
3-508
3-529
3-551
3-562
3-567
3-575
3-580
3-587
CHAPTER 4
IAPX 286 NUCROPROCESSORS
DATA SHEETS
iAPX 286/10 High Performance Microprocessor
with Memory Management and Protection ............ ,.......................
80287 80-Bit HMOS Numeric Processor Extension ..............................••.
82284 Clock Generator and Ready Interface for iAPX 286 Processors .. . . . . . . . . . • • .• .
82288 Bus Controller for iAPX 286 Processors .. . . . . . . . . • . . . • . • . . . . . • . . . . . . . . . . . . . .
'CPlM-86 is a Trademark of Digital Research, Inc,
4-1
4-52
4-76
4-83
CHAPTERS
IAPX 432 MICROMAINFRAMET•
DATA SHEETS
iAPX 43201/43202 General Data Processor .•..........•••...............•..•....• :
iAPX 43203 VLSI Interface Processor ...........................•...........•••...
iAPX 43204/43205 .....•............•............... " .•.•.........•.•..•..•....•
5-1
5-53
5-85
CHAPTER 6
MEMORY CONTROLLERS
APPLICATION NOTES
6-1
AP-97A Interfacing Dynamic RAM to iAPX 86/88 Using the 8202A & 8203 ..........•.
AP-141 8203/8206/2164A Memory DeSign ......... : .............................. ; 6-37 •
AP-167 Interfacing the 8207 Dynamic RAM Controller to the iAPX 186 ••............. 6-43
AP-168 Interfacing the 8207 Advanced Dynamic RAM Controller to the iAPX 286 ..... 6-48
ARTICLE REPRINTS
AR-231 Dynamic RAM Controller Orchestrates Memory Systems ................... . 6-55
TECHNICAL PAPERS
System Oriented RAM Controller ............................................... . 6-62
NMOS DRAM Controller ..............•....•....................•............... 6-73
DATA SHEETS
8202A Dynamic RAM Controller ...................................•............. 6-77
8203 64K Dynamic RAM Controller ..........................................•.... . 6-91
82C03 CMOS 64K Dynamic RAM Controller ..................................... . 6-106
8206/8206-2 Error Detection and Correction Unit ..................•....... , ...... . 6-119
8207 Advanced Dynamic RAM Controller .......................•................. 6-152
8208 Dynamic RAM Controller .........................................•......... 6-199
USERS MANUAL
Introduction ......' ..•................................................•...•...... 6-218
Programming the 8207 ...•......................................•.•.............. 6-219
RAM Interface ................. '.•...... '." .....•..........................•...... 6-224
Microprocessor h'lterfaces .... ; ................................•......•.......•.. 6-233
8207 \:"lith ECC (8206) ...........•....•..•. :..................................... 6-241
Appendix .....•....................... : ......•......................•.......... 6-244
-VOLUME2SUPPORT PERIPHERALS
APPLICATION NOTES
AP-153 DeSigning with the 8256 ..................................................
DATA SHEETS
8231 A Arithmetic Processing Unit ................................................
8253/8253-5 Programmable Interval Timer ..•......................•.....•........
8254 PrograrT)mable Interval Timer ........................................•......
8255A18255A-5 Programmable Peripheral Interface ......................... : ......
8256AH Multifunctional Universal Asynchronous Receiver Transmitter (MUART) .....
8279/8279-5 Programmable Keyboard/Display Interface .'...............•... ; .......
82285 Clock Generator and Ready Interface for I/O Coprocessors .•................
FLOPPY DISK CONTROLLERS
APPLICATION NOTES
AP-116 An Intelligent Data Base System Using the 8272 ..........................••
AP-121 Software Design and Implementation of Floppy Disk Systems .........•.....
DATA SHEETS
8271/8271-6 Programmable Floppy Disk Controller ........•.......................
8272A Single/Double Density Floppy Disk Controller ..............................
HARD DISK CONTROLLERS
DATA SHEETS'
82062 Winchester Disk Controller ................................................
6-248
6-321
6-331
6-342
6-358
6-379
6-402
6-414
6-421
6-455
6-524'
6-553
6-572
UPI USERS MANUAL
,
'
Introduction .....................................•......•.•..••........•....••..
Functional Description .......................•..................................
Instruction Set .................................................................
Single-Step, Programming, and P.ower-Down Modes .................•..•..•..•... ,
System Operation ...............•.....................................•.....•..
Applications ...................................................................
DATA SHEETS •
8041 Al8641Al8741 A Universal Peripheral Interface 8-Bit Microcomputer .............
8042/8742 Universal Peripheral Interface 8-Bit Microcomputer .....•..•..•..•.....•.
8243 MCS-48 InpuVOutput Expander ..........................................•..
8295 Dot Matrix Printer Controller .....•..... : ............. , ..•...................
SYSTEM SUPPORT
ICE-428042 In-Circuit Emulator ............. ,'...................................
MCS-48 Diskette-Based Software Support Package ................................
iUP-200/iUP-201 Universal PROM Programmers ........•...... ~' .................•.
6-598
6-602
6-619
6-646
6-651
6-657
6-777
6-789
6-803
6-809
6-818
6-826
6-828
CHAPTER 7
DATA COMMUNICATIONS
INTRODUCTION
Intel Data Communications Family Overview ......................................
GLOBAL COMMUNICATIONS
APPLICATION NOTES
AP-16 Using the 8251 Universal Synchronous/Asynchronous Receiver/Transmitter. . . .
AP-36 Using the 8273 SDLC/HDLC Protocol Controller ...........................•
AP-134 Asynchronous Communications with the 8274 Multiple Protocol
Serial Controller .........................................................
AP-145 Synchronous Communications with the 8274 Multiple Protocol
Serial Controller ................... '" ................... ,. ........ .. .. ..
DATA SHEETS
8251A Programmable Communication Interface ...................................
8273/8273-4 Programmable HDLC/SDLC Protocol Controller. . . . . . . . . . . . . . . . . . . . . ..
8274 Multi-Protocol Serial Controller (MPSC) ....................... '•.............
82530/8253-6 Serial Communications Controller (SCC) .............•..............
LOCAL AREA NETWORKS
ARTICLE REPRINTS
AR-186 LAN Proposed for Work Stations ..........................................
AR-237 System Level Functions Enhance Controller .•.............................
DATA SHEETS
82501 Ethernet Serial Interface ...................................................
82586 Local Area Network Coprocessor ..........................................
OTHER DATA COMMUNICATIONS
APPLICATION NOTES
.
AP-66 Using the 8292 GPIB Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AP-166 USing the 8291 A GPIB Talkerl.Listener .....................................
ARTICLE REPRINTS
'
AR-208 LSI Transceiver Chips Complete GPIB Interface. . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-113 LSI Chips Ease Standard 488 Bus Interfacing ..............................
TUTORIAL
Data Encryption Tutorial ........................................................
DATA SHEETS ,
8291 A GPIB Talker/Listener . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8292 GPIB Controller ...........................................................
8293 GPIB Tranceiver .......................•...................................
8294A Data Encryption Unit .....................................................
7-1
7-3
7-33
7-79
7-116
7-155
7-172
7-200
7-237
7-266
7-272
7-276
7-287
7-322
7-375
7-407
7-414
7-424
7-425
7-454
7-469
7-481
CHAPTER 8
ALPHANUMERIC TERMINAL CONTROLLERS
APPLICATION NOTES
AP-62 A Low Cost CRT Terminal Using the 8275 ...................................
ARTICLE REPRINTS
AR-178 A Low Cost CRT Terminal Does More with Less ................. ~..........
DATA SHEETS
8275 Programmable CRT Controller ............................'..................
8276 Small System CRT Controller ...............................................
GRAPHICS DISPLAY PRODUCTS
ARTICLE REPRINTS
AR-255 Dedicated VLSI Chip Lightens Graphic Display Design Load ................
AR-298 Graphics Chip Makes Low Cost High Resolution, Color Displays Possible....
DATA SHEETS
82720 Graphics Display Controller ................................. , •............
TEXT PROCESSING PRODUCTS
ARTICLE REPRINTS
AR-305 Text Coprocessor Brings quality to CRT Displays ..........................
AR-297 VLSI Coprocessor Delivers High Quality Displays ..........................
AR-296 Mighty Chips ...........................................................
DATA SHEETS
82730 Text Coprocessor .........................................................
82731 Video Interface Controller .................................................
8-1
8-43
8-50
8-74
8-91
8-99
8-106
8-143
8-151
8-156
8-159
8-199
CHAPTER 9
PACKAGING ............................................................................
9-1
Peripherals
(continued)
(
.Peripherals
Section
6
inter
APPLICATION.
NOTE
Ap·153
June 1983
© Intel Corporation, 1983.
6-248
ORDER NUMBER: 210907·001
Ap·153
INTRODUCTION
Address/Data Bus
The INTEL 8256 MUART is a Multifunction Universal Asynchronous Receiver Transmitter designed to be
used for serial asynchronous communication while
also providing hardware support for parallel 1/0, timing, counting and interrupt control. Its versatile
design allows it to be directly connected to the
MCS~85, iAPX-86, iAPX-88, iAPX-186, and
iAPX-188 microcomputer systems plus the MCS-48
and MCS-51 family of single-chip microcomputers.
The MUART contains 16 internal directly addressable
read/write registers. Four of the eight address/data
lines are used to generate the address. When using
8-bit microprocessors such as MCS-85, MCS-48 and
MCS-51, ADO - AD3 are used to address the 16 internal registers while Address/Data line 4 (AD4) is not
used for addressing. For 16-bit systems, ADI - AD4
are used to generate the address for the internal data
registers and ADO is used as a second active low chip
select.
The four commonly used peripheral functions contained in the MUART are:
RD, WR,CS
I) Full-duplex, double-buffered serial asynchronous
Receiver/Transmitter with an on-chip Baud Rate
Generator
2) Two - 8-bit parallel I/O ports
3) Five - 8-bit counters/timers
4) 8-level priority interrupt controller
The 8256 bus interface uses the standard bus control
signals which are compatible with all Intel peripherals
and mi<;roprocessors. The chip select signal (CS).
typically derived from an address decoder, is latched
along with the address on the falling edge of ALE. As
a result, chip select does not have to remain lc;>w for
the entire bus cycle. However, the data bus buffers
will remain tristated unless an tIT> or a WR signal
becomes active while chip select has. been latched in
low.
This manual can be divided into two parts. The first
part describes the MUART in detail, including its
functions, registers and pins. This section also
describes the interface between the MUART and Intel
CPUs plus a discussion on programming considerations. The second section provides an application example: a MUART-based line printer multiplexer. The
Appendix contains software listings for the line
printer multiplexer and some useful reference information.
The INT and INTA signals are used to interrupt the
CPU and receive the CPU's acknowledgment to the
interrupt request. The MUART can vector the CPU to
the appropriate service routine depending on the
source of the interrupt.
DESCRIPTION OF THE MUART
RESET
The MUART can be logically partitioned into seven
sections:' the miCroprocessor bus interface, the command and status registers, clocking circuitry, asynchronous serial communication, parallel I/O, timer/event counters, and the interrupt controller. This can
be seen from the block diagram of the 8256 MUART
as shown in Figure 1. The MUART's pin configuration can be seen in Figure!' 2.
When a high level occurs on the RESET pin, the
MUART is placed in a known initial state. This initial
state is describe.d under "Hardware Reset." ,
Microprocessor Bus Interface
The microprocessor' bus interface is the hardware
section of the MUA.RT which allows a liP to communicate with the MUART. It consists of tristate
bi-directional data-bus buffers, an address latch, a
chip select (CS) latch and bus control logic. In order to
provide all of the MVA.RT's functions in a 4O-pin DIP
while retaining direct register addressing, a multiplexed address/data bus is used.
'
INT,INTA
Command and Status Register
There are three command registers and one status
register as shown in Figure 1. ,The three command
registers are read/write registers while the status
register is a read only. The command registers configure the MUART for its operating environment (i.e.,
8 or 16 bits CPU, system clock frequency). In addition, they direct its higher level functions ,s~ch as controlling the UART, selecting modes of operation for
the interrupt controller, and choosing the fundamen.
tal frequency for the timers. Command Register 3 is
the only register in the MUART which is a bit set/reset
register, allowing the programmer to simply perform
one write to set or reset any of the bits.
6-249
210907·001
Ap·153
11'"."
AD,oAo.
D8,·DB,
p. .,
Co
RxD
iiii
iii
ALE
RESET
iNrA
TiC
RiC
.NT
Figure 1. Block Diagram of the 8258 MUART
r-------------=....-------,
ADO
Vce
AD1
P10
AD2
P11
AD3
P12
AD4
P13
DBS
P14
DB6
P16
DB7
P18
ALE
P17
ii6
P20
WR
RESET
P22
P21
9
P23
~
P24
INT,
P25
'EXTINT
, eLK
P28
P27
IfxC
TxD "
RxD
~
GND
eft
FIgure 2. MUART Pin Configuration
The status register provides all of the information
about the status of the UART's transmitter and
receiver as well as the status" of the interrupt pin. The
status register is the only read only register in the
MUART.
CLOCK CIRCUITRY
The, clock for the five timers and baud rate generator
is derived from the system clock. the system clock,
pin 17 (CLK), is fed into system clock prescaler
wJ:li,ch, in turn feeds the five pmers and the baud rate
generator. The MUART's system clock can be asynchronous to the microprocessor's.cl~ck.
a
System Clock Prescaler
The system clock prescaler is a programmable divider
which, normalizes the, internal clocking frequency for
th~ t~ers and baud rate generatc;>r to 'l.024MHz. It
divides the system clock(CLK) by 1, 2, 3, or S,'allowing clock frequencies of' 1.024MHz, 2.048MHz,
3.072MHz or S.12MHz. (The commonly used
6: 144MHz crystal frequency' for the 808S results in a
3.072MHz frequenCy from the 808S's Cl;K pin.) If the
system clock is not one of the four frequencies mentioned above, then the frequency of the baud rate
generator and the timers will be nonstandard;
6-250
210907-001
AP·15.3
however, the MUART will still run as long as the
system clock meets the data sheet tcy spec.
Tlm.er Prescaler
The timer prescaler permits the user to select one of
two fundamental timing frequencies for all of the
MUART's timers, either 1KHz or 16KHz. 'The frequency selection is made via Command Register O.
Asynchronous Serial Interface
The asynchronous serial interface of the MUART is a
full-duplex double-buffered transmitter and receiver
with separate control registers. The standard asynchronous format is used as shown in Figure 3. The
operation of the UART section of the MUART is very
similar to the operation of the 8251A USART.
Receiver Section of the UART
The serial asynChronous receiver section contains a'
serial shift register, a receiver buffer register and
receiver control logic. The serial input data is clocked
into the receive shift register from the RxD pin at the
specified baud rate. The sampling actually takes place
at the rising edge of RxC, assuming an external clock,
GENERATED
0001----011
BY 8258
STO~
BrrS
L
DOES NOT APPEAR
DO 0, ----011 ON THE DATA BUS
RECEIVER INPUT
I
I
I
R.O
8ft.:!
erTs L
PROGRAMMED
CHARACTeR
LENGTH
TRANSMISSION'FORMAT
CPU BYTe f5 8 SITS/CHAR)
DATA
C~~RACTER
ASSEMBL.ED SERIAL. DATA OUTPUT (T.O)
START
[lATA CHARACTER
STOt;'!
L....;B:;;,IT:......J_ _--< ......_ _...L.....:;.;'-'L....;"iBITt-J
RECEIVE FORMAT
SERIAL DATA INPUT (AxO)
STARr
SlOO .
DATA CHARACTER
Io-B_'T_'--'-_ _ _-4 ~-'--.l.-..:;;;......I_B::.ITS
CPU BVTElS:' fBITS/CHAR"
.
, DATA CHARACTER
.
· 1 - 1 - -......
"NOTE IF CHARACTER LENGTH IS DEFINED AS 5, 6 OR 7
BITS THE UNUSED BITS ARE SET TO "ZERO"
Figure 3. Asynchronous Format
or at the rising edge of the internal baud clock. When
the receiver is enabled but inactive, the receive logic is
sampling RxD at either 32 or 64 times the bit rate,
looking for a change from the Mark (high) to the
Space (low) state. This is commonly referred to as the
start bit search mode. When:· this state change occurs,
the receive logic waits one half of a bit time and then
samples RxD again. If RxD is still in the Space state,
the receive logic begins to clock in ,the receive data
beginning one bit period later. If RxD has returned to
the Mark state (Le., false start bit), the receive logic
will return to the start bit search mode.
Normally~the received data is sampled in the center of
each bit, however it is possible to .adjust the location
where the bit is sampled. This feature is controlled by
the modification register.
The bit rate of the serial receive data is derived from
either the internal baud rate generator or an external
clock. When using an external clock, the programmer
has a choice of three sampling rates: lx, 32x, or 64x,
Using the internal baud rate generator, the sampling
rates are all 64x except for 19.2 Kbps which is 32x.
When the serial shift register clocks in the stop bit, an
internal load pulse is generated which transfers the
contents of the shift register into the receive buffer.
This transfer takes place' during the first half of the
firststop bit. The load pulse also triggers several other
signals relevant to the receive section including
Receive Buffer Full (RBF), Parity Error (PE), Overrun Error (OE), and Framing Error (FE). These four
status bits are updated after the middle of the first
stop bit when the receive buffer has already been
latched. Each one of these four status bits are latched.
They are reset on the rising edge of the first read pulse
(RD) addressed to the status register. A complete
description of the status register is given in the section
"Description of the Registers."
When the serial receiver is disabled (via bit 6 of Command Register 3) the load pulse is suppressed. The
result is that the receive buffer is not loaded with the
contents of the shift register, and the RBF, PE, OE,
and FE bits in the status register are not updated.
Even though the receiver is disabled, the serial shift
register will still be clocking in the data from RxD, if
any. This means that the receiver. will still be synchronized with the start and stop bits. For example, if
the receiver is enabled via: Command Register 3 in the
middle of receiving a' serial character, the character
will still be assembled correctly. When the receiver is
disabled the last character received will remain in the
receive buffer. On power-up the value'in the receive
buffer is undefined.
6-251
21090]'()01
_IOll ,
I•....
•• ~
Ap·153
Whenever a character length of fewer than 8 bits' is
programmed, the most significant bits of a reCeived
character will read as zero. Also, the receiver will only
check the first stop bit of any character, regardless of
how manY stop bits are programmed into the device.
,
'
•
;
I
Receive Break Detect
A Receive Break occurs when RxD remains in the
space state for one character time, including the,parity
bit (if any) and the first stop bit. The MUART Will set
the Break, Detect status bit (BD) when it receives a
break. The Break Detect status bit ,is set after the mid·
dIe ofthe-il1"st st~p bit. Iftlte MUART detects a break
it will inhibit the receive buffer load pulse, thus the
receive buffer will not be loaded with the null
character, and none of the four status bits (PE, OE,
FE, and RBP) will be updated. The last character
received will remain in the receive buffer. A break
deteCt state haS the same effect as disabling the'
receiver-they both inhibft the load pulse-therefore
one can think of the break status as disabling ,the
receiver.'
The Break Detect status bit is latched. It is cleared by
the riSml edge, of $e read pulse addr.essed to the status
register. If a break occurs, and then the RXD data lin\,
returns to the Mark state before the status register is
read, ,the BD status bit will remain set until it is read.
If RxD returns to the Mark state after the BD status '
bit has been read true, 'the BD status bit will be reSet
automatically without readillg the statu,s register.
The receive break detect logi~~of the MUART is,independent of whether, the r~iver is enabled or disabled; therefore even if the receiver is disab.ed the
MUART will recognize a break. When, the RxD I~ne
returns to the Mark state after a break, the 8256 will
be in the start bit search mod¢.
'
If the receiver interrupt level is enabled. break will
generate an interrupt'request regardless of whether the
receiver.is enabled. Another receive interrupt will not
be 'generated until the RxD pin returns to the Mark
state.
Tran8mltter ~ctjOn of the UART
The seri8I asynchronous transmitter section of the
MUART co~ists of a transn¥t bJlffer; a transmit
(shift),r~gister, and the asso.ciated cOl\trollogic. There
are two bit~ in the status register which indicate the
status of tIie transmit buff~r and' tranSJW.t regi,ster:
TBE (transmit buffer empty) and TRE (transmit
"
register empty).
a
To transmit a clu\racter,
byte is written to the
transmit buffer. The transmit buffer Should only be
written to when TBE = 1. When the transmit register is
empty and Cf§ = 0, the character will be automatically transferred from the transmit, buffer into the
transmit register. The data transfer from the transmit
buffer, to the transmit register takes place during the
transmission of the start bit . .After this transfer takes
place, sometime at the beginning of the transmission
of the, il1"st data bit. TBE is set to 1.
When the transmitter is idle, both TBE and TRE will
be set to 1. After a character is written to the transmit
buffer, TBE = 0 and TRE = 1. This state will remain
for a short Period of time, then the character will be
transferred into the transnnt register and the status
bits, will rea4 TBE = 1 and TRE = At this point a second character may be written to the transmit buffer
after which TBE=O and :rRE=O. TBE will not beset
to 1 again until the transmit register becomes empty
and is reloaded ,with the byte in the transmit buffer.
0:
I
The transmitter can be disabled only one way-using
the CTS pin. When CTS = 0 the transmitter is enabled,
and when CTS = 1 the transmitter is disabled. If the
transn1itter is idle and ~ goes from 0 to 1, disabling
the transmitter, TBE and TRE will remain set to 1.
Since TBE = 1 a' character can be written into the
transmit buffer. The character will be stored in the
transmit buffer but it will not be transferred to the
transmit register until ffi goes low.
a
If ffi goes from low to high during transmission of
character, the character in transmission will be completed and TxD will return to the Mark state. If the
transmitter is full (i.e., TBE and TRE = 0), the
transmit shift register will be emptied but the transmit
buffer will not; therefore TBE = 0 and TRE = 1.
Tran8mltter Break Fe.ture8
The MUART has three transmit breat features:
Break-In Detect, Transmit ,Break O:BRK). and Single
Character Break (SBRK).
Break-In Detect - A Break-In condition occurs when
the MUART is sending a serial message and the
trans~ission line is forced to the space state by the
recei~ing station. Break-In is usually used' with halfduplex transmission so that the receiver can signal' a
break to the tr!Ulsmitter. Port 16 ,must be connected
externally to the transmission line in order to detect a
Break·In. If transmission voltage levels\ other than
TTL are used, then proper buffering must be provided
so that Port 16 on the MUART will receive the correct
polarity and voltage Ie,vels.
6-252
210907'()()1
Ap·153
When Break-In Detect is enabled, Port 16 is polled internally during the transmission of th!= last or only
stop· bit of a character. If this pin is low during
transmission of the stop bit, the Break Detect status
bit (BD) will be set. Break-In Detect and receive Break
Detect are OR-ed to set the BD status bit. (Either one
can set this bit.) The distinction can be made through
the interrupt controller. If the transmit and receive interrupts are enabled, a Break-In will generate an interrupt on level S, the transmit interrupt, while Break will
generate an interrupt oli level 4, the receive interrupt.
If RxC and TxC are used for the serial bit rates,
Break-In cannot be detected.
Transmit Break - This causes the TxD pin to be forced
low for as \ong as the TBRK bit in Command Register
3 is set. While TranSmit Break is active, data transfers
from the Transmit Buffer to the Transmit register will
be inhibited.
If both the Transmit Buffer and the Transmit Register
are full, and a Transmit Break cominand is issued
(command register 3, TBRK= I), the entire character
in the Transmit register is sent including the stop bits.
TxD is then driven low and the character in the
Transmit Buffer remains there until Transmit Break is
disabled (command register 3, TBRK';' 0). At this time
TxD will go high for one bit time and then send the
character in the Transmit Buffer.
Single Character Break - This causes TxD to be set
low for one character including start bit, data bits,
parity bit, and stop bits. The user can send a specific
number of Break characters using this feature.
If both the Transmit Buffer and the Transmit Register
are full and a Send Break command is,.issued (command register 3, SBRK = 1) the entire character in the
Transmit Register is sent including the stop bits. TxD
is driven low for one complete character time followed
by a high for two bit times after which the character in
the'Transmit Buffer is sent.
Modification Register
The modification register is used to alter two standard
functions of the receiver (start bit check, and sampling
time) and to enable a special indicator flag for halfduplex operation (transmitter status). Disabling start
bit check means that the receiver will not return to the
start bit search mode if RxD has returned to the Mark
state in the center of the start bit. It will simply proceed to assemble a character from the RxDpin
regardless of whether it received a false start bit or
not. The modification register also allows the user to
define where within the receive data bits the MUART
will sample.
Parallel I/O
The MUART contains 16 parallel 1/0 pins which are
divided into two 8-bit ports. These two parallel I/O
ports (Port 1
Port 2) can be used for basic digital
I/O such as setting a bit high or low, or for byte
transfers using a two-wire handshake. Port 1 is bit
programmable for input or output, so any combination of the eight bits in Port 1 can be selected as either
an input or an output. Port 2 is nibble programmable,
which means that all four bits in the upper or lower
nibble have to be selected as either inputs or outputs.
For byte transfers using the two- wire handshake,
Port 2 can either input or output the byte while two
bits in Port 1 are used for the handshaking signals.
and
All of the bits in Port 1 have alternate functions other
than 1/0 ports. As mentioned above, when using the
byte handshake mode, two bits on Port 1 are used for
the handshaking signals. As a result, these two bits
cannot be used for general purpose 1/0. The other six
bits in Port 1 also have alternate functions if they are
nbt used as 1/0 ports. Table 1 lists each bit from Port
1 and its corresponding alternate function.
The bits in the Port 1 Control Register select whether
the pins on Port 1 are inputs or outputs. The pins on
Port 1 are selected as control pins through the other
programming registers which are relevan~ to the control signal. Configuring a bit in Port 1 as a control
function overrides its definition in the Port 1 Control
Register. If the pins on Port 1 are redefined as control
signals, the definition of whether the pin is an input or
an output in the Port 1 Control Register remains unchanged. If the pins on Port 1 are converted back to
I/O pins, they assume the state which was defined in
the Port 1 Control Register.
Each parallel 1/0 port has a latch and drivers. When
the port is in the output mode, the data written to the
port is latched and driven on the pins. The data which
is latched in the 1/0 ports remains unchange4 unless
the port is written to again. Reading the ports,
whether the port is an input or output, gates the state
at the pins onto the data bus. Writing to an input port
has.no effect on the pin, butthe data is stored in the
latch and will be QutP\1t if the direction on the pin is
changed later. Writing to a control pin on Port 1 has
the same effect as writing to an input pin. If pins 2, 3,
S, and 6 iri Port 1 are used for control signals, the contents of the respective output latches will be read, not
the state of the control signals. If pins 0, I, and 7 on
6-253
210907'()()1
,I"n+_I®
•• ~
AP·153
Table 1. Port 1 ContmJ Signals
..
Pin
Symbol
Pin
Number
PH
39
38
PIO
Pll
, ,PIO:
PI2
,
, PI3
Control Function
Condition
A.CK
OBF
Contro}' signals for P?rt 2
8-bit h~dshake output '
' Mode register
P2C2.,. P2CO= 101
39
,38
STB
Control signals for Port 2
8-bit handshake input
Mode register
' PlC2": P2CO = 100
37
lIvent couriter ,2
clock input
36
Event counter 3
clock input
IBF
Mode register
CT2=1
;
'.
' 35
I,nternal baud rate
generator clock output
PI5
34
Timer 5 trigger input
1:>16
33
Break-In detection input
PI7
32
External edge sensitive
interrupt input
PI4 '
Port I are used for control signals, the state of the
control signals will be read. If pin 4 on Port I is used
as a test output for. the internat baud rate, th~s clock
signal will be output ~ough the output latch, thus the
information in the output latch will be lost.
The Two.Wlre Byte Handshake
The 8256 can be programmed, via the Mode Register;
to implement ~ input or output two-wire byte handshake. When the Mode Register is programmed' for
the byte handshake, Port 2 is used to transmit or
receive the byte; and pins PIO and PII are
for the
two 'handshake control signals. Figures 4 and 5 on
pages 7 through 10 show a block 'di~ram and timing
signals for the two-wire handshake input and output.
used
To set up the two-w4i'handshake output using inter" '
rupts one must flrst program the Mode Register, and
then enable"the interrupt via the interrupt 'mask
register. An interrupt will not oC'Cur immediatelya(ter
the two-wire handshake'int!m1lpt is enabled.' nie "interrupt is triggered by the rising edge of ACK. ,There
are two ways to generate the first interrupt. Either the
Mode register
CT3=1
,
M!>deword
P2CO - P2C2 = III
Port I control word P14= I
Command Register 2
B3 - BO > 3H
Mode register
, T5C=1
Command Register I'
BRKI=I
"
Command Register I
BITI=I
first data byte must be written to Port 2 and completely transferred before an interrupt will occur, or the
two-wire handshake interrupt is enabled while A.CK is
low, and then ACK goes high.
Event CountersITlmers
'I;h~ MllART's, five 8-bit 'programmab~ counters/
timers' are binary presettable down couitters.· The
distim;tion between timer ~d counter is determined
by the clock source. A timer measw:es, an absolute
time interval, and its input clock frequency is d~ved
from the MUART's system clQck. A counter's mput
clock frequency is derived from a pulse applied to an
, external pin. The counter is decremented qn the rising
edge of-this pulse.
When the
cOunter~/timers are conflgured' as timers
their clOck source passes through two diViders: the
systeM,' Clock 'prescaler, and the' timer prescaler. As
mentioned before, the system clock prescalet normalizeS the internal system clack 1.024 MHz. The timer
prescaler receives this normalized syStem clock and
devides it down;to either 1 kHz ot i6 kHZ, depending'
'6-254
to
210907-001
Ap·153
INT
OBF
iNTA
AcK
iii)
Processor
Equipment
8258
WR
P2IJ.P27
Databus
Figure 4. Block Diagram of Handshake Output
on how Command Register I is programmed. If more
timing resolution is needed the clock frequency can be
input externally through the 110 ports.
By programming the Mode Register, four of the 8-bit
counters/timers can be cascaded to form two 16·bit
counters. Counters/timers 3 and 5 can be cascaded
together, and counters/timers 2 and 4 can be cascaded
together. Counters/timers 2 and 3 are the lower bytes,
while counters/timers 4 and 5 are the upper bytes in
the cascaded mode.
bit in the interrupt mask register is automatically
reset, preventing further interrupt requests from occuring.
The event counters/timers can be used in the following modes of operation:
Timer I
- Serves as an 8-bit timer.
Each counter can be loaded with an arbitrary initial
value. Timer S is the only timer which has a special
save register which holds its initial value. Whenever
Timers is loaded with an initial value the special save
register is also loaded with this value. Timer 5 can be
reloaded to its initial value from the detection of a
high-to-Iow transition on Port PIS.
The counters are decremented on the first rising edge
of the clock after the initial value has been loaded.
The setup time for loading the counter when using an
external clock is specified in the data sheet. When us·
ing internal clocks, the user has no way of knowing
the phase relationship of the clock to the write pulse;
therefore the timing accuracy is one clock period.
The timers are counting continuously, and an interrupt request is issued any time a single counter or pair
of cascaded counters reaches zero. If the timers are
geing to be used with interrupts, then the programmer
should first load the timer with the initial value, then
enable the interrupt. If the programmer enables the interrupt first, it is possible that the interrupt will occur
before the initial value is loaded. When an interrupt
from anyone of the timers occurs, the corresponding
Event Counter/Timer 2
- Serves as an 8-bit timer or event counter, or
cascaded with Timer 4 as a 16-bit timer or event
counter.
Event Counter/Timer 3
- Serves as an 8-bit timer or event counter, or
cascaded with Timer 5 as a 16-bit timer or event
counter, with the additional modes of operation
selectable for Timer 5.
Timer 4
- Serves as an 8-bit timer, or cascaded with Event
Counter/Timer 2 as a 16-bit' timer or event
counter.
Timer 5
I) Non-retriggerable 8-bit timer
2) Retriggerable 8-bit timer whose initial value is
loaded from a save register which starts following
the negative transition of an external signal. Subsequent transitions of this signal after the counting
has started, reloads the il1itiai value and restarts the
counting.
.
3) Cascaded with Event Counter/Timer 3, nonretriggerable 16l bit timer, which can be loaded
with an initial value by two write operations.
6-255
210907-001
Ap·153
INT
...........
iNTA
or
iiD
.........
®............ . . , ,
.....----------------~~\
A~AD4
DB5-0B7
-----'
Data
PZo.PZ7
Figure 48. Timing of Handshake Output
CD The 8256 signals with INT that the equipment has accepted the last character and that the output latches are empty again.
eD Ther~upon, the microprocessor transfers the next data to the 8256.
@The rish~g edge of WR
new byte is available.
latch~ the data into port 2 (P20 ... P27) and
"Output Buffer Full" (OBF) IS set which indicates that a
.
@The.equipment acknowledges with the f8Iling edge ofA'CK that it recognized OBF.
0Thereupon, the 8256 releases OBF.
@The equipment acknowl~ges the data transfer with a rising edge of ACK which causes the 8256 to.set INT.
6-256
210907-001
Ap·153
INT
S'fi
iNTA
IBF
Ro
Processor
8256
EquIpment
P20·P27
Databus
Figure 5. Block Diagram of Handshake Input
4) Cascaded with event counter/timer 3, non·
retriggerable 16·bit event counter, which can
. be loaded with an initial value by two write
operations.
5) Cascaded with Event Counter/Timer 3, retrig·
gerable 16·bit .timer. The most significant byte
(Timer 5) will be loaded with its initial value from
the save register, while the least significant byte
(Event Counter/Timer 3) will be set to OFFH
automatically, Loading, starting, and retriggering
operation~ follow the same. pattern as in 2).
6) Cascaded with Event Counter/Timer 3, retrig·
gerable 16·bit event counter. The most significant
byte (Timer 5) will be loaded with its initial value
from the save register, while the least significant
byte (Event Counter/Timer 3) will be set to OFFH
automatically. Loading, starting, and retriggering
operations follow the same pattern as in 2).
be met when the CPU must execute a main program as
well as subroutines. Usually each peripheral has its
own request to response time requirements; therefore
the user must establish a priority scheme.
The interrupt method provides certain advantages
over the polling method. When a peripheral device
needs service it signals the CPU through hardware
asynchronously, thus reducing the overhead of polling
a device which does not need service. The CPU would
typically finish the instruction it is executing, save the
important registers, and acknowledge the peripheral's
interrupt request. During the acknowledgment, the
CPU reads a vector which directs the CPU to the start·
ing location of the appropriate interrupt service
routine. If several interrupt requests occur at the same
time, special logic can prioritize the requests so that
when the CPU acknowledges the interrupt, the highest
priority request is vectored to the CPU.
An interrupt dri~en system requires additional hard·
Interrupt Controller
In a micrOl;omputer system there are several ways for
the CPU to recognize that a peripheral device needs
service. Two of the most common ways are the polling
method and the interrupt service method.
In the polling method the CPU reads the status of
each peripheral to determine whether it needs service.
If the peripheral does not need service, the time the
CPU spends polling is wasted; therefore this overhead
results in increasing the execution time. Some systems
must meet a specific request to response time such as a
real time' signal. In this case the programmer must
guarantee that the peripheral is polled at a certain fre·
quency. This polling frequency cannot always easily
ware to control the interrupt request signal, priority,
and vectoring. The 8256 integrates this additional
hardware onto the chip. The interrupt controller on
the MUART is directly compatible with the MCS·85,
iAPX·86, iAPX·88, iAPX·186, iAPX·188 family of
microcomputer systems, and it can also be used with
other microprocessors as well. It contains eight priori·
ty levels, however, there are a total of 12 interruptable
sources: 10 internal and 2 external. Since there are
eight priority levels, only eight interrupts can be used
at one time. The assi~ent of the interrupts used is
selected by Command Register 1 and by the mode
register. The MUART's interrupt sources have a fixed
priority. Table 2 displays how the 12 interrupt sources
are mapped into the 8 priority levels.
6-257
210907-001
Ap·153
. P2D-P27
-v
Data
yi
l~
!~ Data
.J\'----~'l~i------il~1------i10---
INT
~~~g;--------~-------;~~:~--------Figure Sa. Timing for Handshake Input
CD The equipmc;nt indicates with the falling ~of STB (Strobe) that a new character is available at port 2. The 8256
acknowledges the indication bYilctivating IBF (Input Buffer Full).
.
.
CD Thereupon, the equipment releases STB and the 8256 latches the character.
CD The 8256 informs the microprocessor through INT that a new c/laracter is ready for transfer.
@the microprocessor reads the character.
CD The rising edge'of signal RD resets signal iBF.
@Thi,s action signals to the equipment that the input latches of the 8256 are empty and the next char~cter can be transferred.
6-258
210907·001
inter
Ap·153
Table 2. Mapping of Interrupt Source. to
Priority Level.
'
MEMORY ADDRESS
\
Priority
Highest
Source
LO
LI
L2
L3
L4
Lowest
L5
L6
L7
Timer 1
Timer 2 or Port Interrupt
~ternal Interrupt (EXTINT)
Timer 3 or Timers. 3 & 5
Receiver Interrupt
Transmitter Interrupt
Timer 4 or Timers 2 & 4
Timer 5 or Port 2 Handshaking
r - - - - - - , OOH
TRAP
j - - - - - - i 08H
.1-_ _ _ _-1 10H
RST 7.5
RST 6.5
RST 5.5
- ; - -_ _ _--I 18H
. ; / - - - - - - i 20H
~~
________
~24H
.....+-------1 28H
.............- - - - - I 2CH
MCS~·85/8256 Interrupt Operation
The 8256 is compatible with the 8085 interrupt vectoring method when the 8086 bit in Command Register 1
of the MUART is. set to O. This is th~ default condition
after a hardware reset. The 8085 has five hardware interrupt pins: INTR, RST 7.5, RST 6.5, RST 5.5, and
TRAP. When the MUART's interrupt acknowledge
feature is enabled (lAB bit 5 Command Register 3 = I)
the MUART's INT Pin IS should be tied to the 8085's
INTR, and both the 8085 and the MUART's INTA
pins should be tied together. All of the interrupt pins
on the 8085 except INTR automatically vector the program counter to a specified location in memory. When
the INTR pin becomes active (HIGH), assuming the
8085 has interrupts enabled, the 8085 fetches the next
instruction from the data bus where it has been placed
by the 8256 'or some other interrupt controller. This
instruction is usually a Call or an RSTO through
RST7. Figure 6 shows the memory locations where the
8085 will vector to based on which type of interrupt
occurred.
The 8085 can receive an interrupt request any time,
since its INTR input is asynchronous. The 8085,
however, doesn't always acknowledge an interrupt request immediately. It can accept or disregard requests
under software control using the EI (Enable .Interrupt)
or DI (Disable Interrupt) instructions.
At the end of each instruction cycle, the 8085 examines the state of its INTR pin. If an interrupt request is present and interrupts are enabled, the 8085
enters an interrupt machine cycle. During the interrupt machine cycle the 8085 autQmaUcally disables
further interrupts until the EI instruction is executed.
Unlike normal machine cycles, the interrupt machine
·~~----~30H
~---------; 34H
__"':"---l38H
'--......_ _ _--1 3CH
~-----l~!.I-
B08SA
EXECUTING
SOFTWARE
RST INSTRUCTIONS
IN RESPONSE TO INTR
S08SA
SYSTEM
MEMORY
Figure 6. 8085A Hardware and Software RST
Branch Locations
cycle doesn't increment the program counter. This ensures that the 8085 can return to· the pre-interrupt
program location after the interrupt service is completed. The 8085 issues an INTA pulse indicating that
it is honoring the request and is ready to process the
interrupt.
The 8256 can now vector program execution to the
corresponding service routine. This is done during the
first and only INTA pulse. Upon receiving the'lN'i'A
pulse, the 8256 places the opcode RSTn on the data
bus; where n equals 0 through 7 based on the level of
the interrupt requested. The ·RSTn instruction causes
the contents of the program counter to be pushed onto
the stack, then transfers control to the instruction
whose address is eight times n, as shown in Figure 6.
Note that because interrupts are disabled during the
interrupt acknowledge sequence, the EI instruction
must be executed in either the service routine or the
main program before further interrupts can be processed.
For additional information on the 8085 interrupt
operation and the RSTn instruction, refer to the
MCS-85 User's Manual.
210907-001
Ap·153
two INTA pulses which signals the 8256 that the
IAPX·88188 - 8256,lnterrupt Operation
The MUART is compatible with. the 8086/8088
method of interrupt vectoring when the 8086 bit in
Commud Register 1 is set to 1. The MUART's INT
pin is tied to the 8086/8088 INTRJIlt and its INTA
pin. Like the
pin connected to the 8086/88's I
8085, the 8086/8088's INTR pin is also asynchronous
so that' an interrupt request can occur at any time. The
8086/8088 can accept or disregard requests on the
INTR pin under software control instructions. These
instructions set or clear the interr\lpt-enabled flag IF.
When the 8086/8088 is powered· on or reset, the IF
flag is cleared, disabling external interrupts on INTR.
Although there are some basic similarities, the actual
processing of interrupts with an 8086/8088 is different
from the 808,5. When an interrupt request is present
and interrupts are enabled, the 8086/8088 enters its interrupt acknowledge machi.ne cycle. The interrupt
acknowledge machine cycle pushes the flag registers
onto the stack (as in PUSHF ·instruction). It then
clears the IF flag, which disables interrupts. Finally,
the contents of both the code segment register and the
instruction pointer are pushed onto the stack. Thus,
the stack retains the pre-interrupt flag status and program lo~on which are used to return from the sel"
vice routine. The 8086/8088 then issues the first of
8086/8088 has honored its interrupt request.
,
,
The 8256 is now ready to vector program execution to
the appropriate service routine. Unlike the 8085 whe,re
the first INTA pulse is used to place
mstruction on
the data bus, the first INTA pUlse from the' 8086/8088
is used only to signal'the 8256 of the honored request.
The second INTA pulse causes the 8256 to place a
single interrupt vector byte onto the data bus. The
8256 plaCes the interrupt vector bytes 40H through
47H corresponding to the level of the interrupt to be
serviced. Not used as a direct address, this interrupt
vector byte pertains to one of 256 interrupt "types"
supported by the 8086/8088 memory. Program execution is vectored to the corresponding service routine
by the contents of a specified interrupt type.
an
All 25.6 interrupt types are locaied in absolute memory
locations 0 through 3FFH which make up the
8086/8088's interrupt vector table. Each type in the,
interrupt vector table requires 4 bytes of memory and
stores a" code segment address and an instruction
pointer 'address. Figure 7 shows a block diagram of.
the interrupt vector· table. When the 808618088
receives an interrupt,vector byte, it multiplies its value
by four to acquire the address of the int,errupt type.
Cr'
VI"
INTERRUPT
TYPE2SS
(FFH)
3FCH
INTERRUPT
TYPE 254
(FEH)
3F8H
··
·
l::~.,
MUART'S
INTERRUPT
LEVELS
~~
,INTERRUPT
TYPE 71
(47H)
INTERRUPT
TYPE 70
(46H)
l18H
INTERRUPT
TYPE 69
(45H)
l14H
INTERRUPT
tyPE: 68
144H)
110H
INTERRUPT
TYPE 67
(43HI
lOCH
INTERRUPT
TYPE 68
'(42H) ,
10SH
INTERRUPT
TYPE 65
(41 H)
104H
TYPE 64
(40H)
l00H
.
'ItJlTERRUPT
l::~
,
11CH
l::R
.
f
INTERRI/PT
1'Y.PE
~ , '.
(2H)
INTERRUPT
TYPE
1
I1HI. '
INTERRUPT
TYPE
0-
,·iOH)
8H,
4H
OH
Figure 7. 808818088 Interrupt Vector Table
6.-260
210907'()()1
Ap·153
Once the service routine is completed the main program may be reentered by using an IRET (Interrupt
Return) instruction. The IRET instruction will pop the
pre-interrupt instruction pointer, code segment and
flags off the stack. Thus the main program will
resume where it was interrupted with the same flag
status regardless of changes in the service routine.
Note especially that this includes the state of the IF
flag; thus interrupts are re-enabled automatically
when returning from the service routine. For further
information refer to the iAPX 86,88 User's Manual.
Interrupt Registers
Using the 8258's Interrupt Controller
Without INTA
There are several configurations where the 8256 will
not have an INTA signal connected to it. Some examples are when using the 8256 with an 8051 or 8048,
or when connecting the INT pin on the 8,256 to the
8085's RST 7.5, RST 6.5, or RST 5.5 inputs. In these
configurations the lAB bit in Command Register 3 is
set to 0, and the INTA pin on the ,8256 is tied high.
When the interrupt occurs the CPU should branch to
a service routine which reads the interrupt address
register to determine which interrupt request level occured. The interrupt address register contains the level
of the interrupt mUltiplied by four. Reading the interrupt address register is equivalent in effect to the
fNTj\ signal; it clears the INT pin and indicates to the
MUART that the interrupt request has been
acknowledged. After the CPU reads the value in the
interrupt address register, it can add an offset to this
value and branch to an interrupt vector table which
contains jump instructions to the appropriate ihter,rupt service routines. An 8085 program which
demonstrates this routine is given is Figure 8.
Table 3 summarizes the priority levels and the interrupt vectors which the 8256 sends back to the CPU.
Note that when using Timer I there is a conflict pre-
INTA:
IN
MOV
XRA
MOV
LXI
DAD
PCHL
INTADD
L, A
sent between RSTO in the 8085 mode and a hardware
reset, bec~use both expect instructions starting at
address OH. However, there is a way to distinguish
between the two. After a hardware reset, all control
registers are reset to a value of QH; therefore when
using Timer I, Reset and RSTO can be distinguished
by reading one of the control registers of the 8256
which has not been programmed with a value of OH.
The control registers will contain the previously
programmed values if RSTO occurs.
The 8256's interrupt controller has several registers
associated with it: an Interrupt Mask R~gister, an Interrupt Address Register, an Interrupt Request
Register, an Interrupt Service Register, and a Priority
Controller. Only the Interrupt Mask Registers and the
Interrupt Address Register can be accessed by the
user.
Interrupt Mask Registers
The Interrupt Mask Registers consist of two write
registers - the Set Interrupts Register and Reset Interrupts Register, and one read register - the Interrupt
Enable Register. Each one of the eight levels of interrupts may be individually enabled or disabled through
these registers. Writing a one to any of the bits in the
Set Interrupts Register enables the corresponding interrupt level, while writing a one to a bit in the Reset
Interrupts Register disables the corresponding interrupt level. Reading the Interrupt Enable Register
allows the user to determine which interrupt levels are
enabled. The pits which are set to one in the Interrupt
Enable Register correspond to the levels which are
enabled. All of the interrupt levels will remain enabled
until disabled by the Reset Interrupts Register except
the counter/timer interrupts which automatically
disable themselves when they reach zero.
;Read the Interrupt Address Register
;Put the interrupt address in HL
A
H,A
B, TABLE
B
;Load BE with the interrupt table offset
;Add the offset to the interrupt address
;Jump to the interrupt vecor table
Figure 8. Software Interrupt Acknowledge Routine
6-261
210907-(101
Ap·153
Table 3. Assignment of Interrupt Levels to Interrupt Sources
Inter~
Restart
Com·
mand
rupt
Vector
Interrupt
Level
8085
8086
mode
mode
Inter·
rupt
Trigger
Address Mode
Highest
Priority
0
RSTO
40H
OH
1
RSTI
41H
2
RST2
3
RST3
4
RST4
5
RST5
6
7
Lowest
Priority
,
Sources
(Only one s.ource can be
assigned at any time)
Selection
by
edge
Timer 1
-
4H
edge
Event Counter/Timer 2 or
external interrupt request
on Port 1 P17
Command
word 1 BITI
(bit 2)
42H
SH
,level
Input EXTINT
-
43H
CH
edge
Event Counter/Timer 3 or
cascaded event counters/
timers 3 and 5
Mode word
T35 (bit 7)
44H
lOH
edge
Serial receive,r
45H
14H
edge
Serial transmitter
-
,RST6
46H
2SH
edge
Timer 4 or cascaded event
counters/timers 2 and 4
Mode word
T24 (bit 6)
RST7
47H
lCH
edge
Timer 5 or port 2 with
handshaking interrupt
request
.
-Mode word
P2C2 - P2CO
(bits 2 ... 0)
Note:
If no interrupt requests are pending and INTA cycle occurs, interrupt level 2 will be the default value vectored to the CPU.
Interrupt requests occurring when the corresponding
interrupt .level is disabled are lost. An interrupt will
only occur if the .interrupt is enabled before the
interrupt request occurs.
Interrupt Request Register
The Interrupt Request Register latches all pending interrupt requests unless they are masked off. The request is set whenever the associated event occurs.
Interrupt Address Register
The Interrupt Address Register contains an identifier
for the currently requested interrupt level. The
numerical value in this register is equal to the interrupt
level mutliplied by four. It can be used in lieu of an
iNTA signal to vector the CPU to the appropriate interrupt service routine. Reading this register has the
same effect as the INTA pulse: it clears the INT pin
and indicates an interrupt acknowledgement to the
MUART. If the Interrupt Address Register is read
while no interrupts are pending, the external interrupt
EXTINT will be the default value, OSH.
Interrupt Service Register
In the fully nested mode of operation, every interrupt
request which is granted service is entered into this
register. The appropriate bit will be set whenever the
interrupt is acknowledged by iNTA or by reading the
Interrupt Address Register. At the same time., the corresponding bit in the Inten:upt Request Register is
reset. The Interrupt Service Register bit remains set
until the microcomputer transfers the End Of Inter, rupt command (EDI) to the device by writing it into
Command Register 3. In the normal mode the bits in
the Interrupt Service Register are never set.
6-262
210907-001
Ap·153
Priority Controller
The priority controller selects the highest priority
reciuest in the Interrupt Request Register from up to
eight requests pending. If the INTA signal is enabled
and becomes active, the priority controller will cause
the highest priority level in the Interrupt Request
Register to be vectored ba<;.k to the CPU, regardless of
whether the &256 is in the normal mode or the nested
mode. In the normal mode, if any bits are set in the
Interrupt Request Register, the INT pin is activated.
The highest priority level in the Interrupt Request
register will be transferred to the Interrupt Address
Register at the same time the interrupt request occurs.
In the Fully Nested mode, the priorities of all pending
requests are compared to the priorities in the Interrupt
Service Register. If there is a higher priority in the
Interrupt Request Register than in the Interrupt Service Register, the INT signal will be activated and the
new interrupt level will be loaded into the Interrupt
Address Register.
Interrupt Mode.
There are two modes of operation for the interrupt
controller: a normal mode and a Cully nested mode. In
the normal mode the CPU should only be a maximum
of one interrupt level deep; therefore, the CPU can be
interrupted only while in the main program and not
while in an interrupt service routine. In the fully
, nested mode it is possible for the CPU to be nested up
to eight interrupt levels deep. Using the fully nested
mode, the MUART will activate the INT pin only
when a higher priority than the one in service is requested. The fully nested mode is used to protect high
priority interrupt service routines Jrom being
interrupted by equal or lower priority requests.
Normal Mode
In the normal mode of operation the 8256 will activate
the INT pin whenever any of the bits in the Interrupt
Request Register are set. The bits in the Interrupt
Request Register can be set only if the corresponding
interrupts are enabled. If more than one interrupt request bit is set, the MUART will always place the
highest priority level in the Interrupt AddresirfTlister
and vector this level to the CPU during an
cycle. When the CPU acknowledges the interrupt
request, using either, the iN"fA signal or by reading the
Interrupt Address Register, the corresponding interrupt Request Register bit is reset. Since the Interrupt
Service Register bits are never ,set, there is no indication in the MUART that an interrupt service routine is
in progress. Therefore, the priority controller will interrupt the CPU again if any of the interrupt request
bits. are. set, regardless of whether the next request is a
higher, lower, or equal priority.
The implied way to design a program using the normal'
mode is to have the CPU's interrupt flag enabled during portions of the main program, but to leave the interrupt flag disabled while the CPU is executing code
in an interrupt service routine. This way, the CPU can
never be interrupted in an interrupt service routine.
Upon completion of an interrupt service routine the
program can enable the CPU's interrupt flag, then
return to the main program.
Figure 9 shows an-example of how the normal mode
of interrupts may operate. As the CPU begins
executing code in the main program, certain I/O
ports, variables, and arrays need to be initialized.
During this time the CPU's interrupt flag is disabled.
Once the program has completed the initialization
routine and can accept an interrupt, the interrupt flag
is enabled. In the 8085 this is done with the assembly
language instruction EI, and on the 8086 with STI.
A short time later, an interrupt request comes in on
Level 4. Since the CPU's interrupt flag is enabled, the
interrupt acknowlec;tge signal is activated and the CPU.
branches off to Interrupt Service Routine 4. While the
CPU is executing code in Interrupt Service Routine 4,
an interrupt request comes in on Level 6 and then a
short time later on Level 2. The 8256 activates the INT
signal; however, the CPU ignores this because its interrupt flag is disabled~ Upon returning to the main
program the interrupt flag is enabled. When the interrupt acknowledge signal is activated, the MUART
places the highest priority interrupt request on the
data bus regardless of the order in which the requests
came in. Therefore, during the interrupt acknowledge
the MUART vectors the indirect address for InterruDt
Level 2. The INT signal is not cleared after the
acknowledge because there is still a pending interrupt.
The normal mode of operation is advantageous in that
it simplifies programming and lowers code requirements within interrupt routines; however, there
are also several disadvantages. One disadvantage is
that the interrupt response time for higher priority interrupts may'be excessive. For example, if the CPU is
executing code in an interrupt service routine during a
higher priority request, the CPU will not branch off to
the higher priority service routine until the current interrupt service routine is completed. This delay time
may not be acceptable for interrupts such as the serial
receiver or a real time signal. For these cases the
MUART provides the nested mode.
Ne.ted Mode '
In the nested mode of operation, whenever a bit in the
Interrupt Request Re$ister is set, the Priority Con-
6-263
210907·001
Ap·153
MAIN PROGRAM
I
•
t
EI OR STI
t
I
i
INTERRUPT
REQUEST 4
riNTERRUPr-j
..J
SERVICE
ROUTINE 4
I
,
I
I
I
•,
•
• L...:....--
t
t
t
-.I
t
,l.
INTERRUPT
..!.
INTERRUPT
REQUEST 2
I REQUEST 6
I
:
I
RET OR IRET .JI
________
1
r-iNTERRUPT - ,
SERVICE
I
ROUTINE 2
I
I
,
I
I
I
I
I
I
I
I
I
t
I
I
t
I
I
I
RET
R
I... _______
.JI
r-iNTER'RuPi"- ,
,
i
I
-----
-~
l
I
I
SERVICE
ROUTINE 6
I
I
•
I
I
I
,
I I
I________
T R
1I
Figure 9. Normal Interrupt Mode Example
troller compares the Interrupt Request Register to the·
Interrupt Service Register. If the bit set in the Request
Register is of a higher priority,than the highest priority
bit set in the Service Register, the MUART will activate the INT signal and update the Interrupt Address
Register. If the.bit in the Request Register is of equal
or lower priority than the highest priority bit set in the
Service Register, the INT signal. will not be activated.
When an INTA signal is activated or the Interrupt
Address Register is read, the corresponding bit in the
Request Register which caused the INT signal to be
asserted is reset and set in the Service Register. When.
an EO! (End Of Interrupt) command is issued, the
highest priority bit in the Service Register is reset.
Figure 10 shows an example of the program flow using
the nested mode of interrupts. During the main program an interrupt request is generated from Level 4.
Since the interrupt flag is enabled, the interrupt
acknowledge signal is activated, and the
microprocessor is vectored to Service Routine 4.
During Service Routine 4, Level 2 requests an interrupt. Since Level 2 is a higher priority than Level 4,
the 8256 activates its INT signal. An· interrupt
6-264
210907-001
AP·153
MAIN PROGRAM
EIORSTI
r INTERRUPT
E .,
INTERRUPT
REQUEST 41 -
~-~.~~~~ICR~~~EU~~V~I~C~E~4::J
:
I
~~~~~iINTERRUPT
••
REQUEST2
I
EI OR STI
••
•
~~~§
~
EOI
I
r ';"INTERAUPf'" '
I
R~U~y~CEE2
:
EI
I
I ~~~;:
II
I~i_'
~=i=~tINTERRUPT
I
REQUEST 6
41 :E: ~:~ J UU!_~_~_§_~J
E
I
,Mr'
E6
I
I
I
I
I
I
I
I
I
EOI
I
RET OR IRET I
I
I ____ :..JI
Figure 10. Fully Nested Interrupt Mode Example
acknowledge is not generated because the interrupt
flag is disabled. This section of code in Service
Routine 4 is protected and cannot be interrupted. A
protected section ofcade may reinitialize a timer, take
a sample, or update a global variable. When the interrupt flag is enabled the microprocessor acknowledges
the interrupt and vectors into Service Routine 2. Service Routine 2 immediately enables the interrupt flag
because it does not have a protected section of code.
During Service Routine 2, Interrupt Request 6 is
generated. However, the MUART will not interrupt
the microprocessor until service routines 2 and 4 have
issued the EOI command.
Edge Triggering
The MUART has a maximum of two external interrupts-EXTINT and PI7. EXTINT is a dedicated
interrupt pin which is level triggered, where PI7 is
either an 1/0 port or an edge triggered interrupt. If
PI7 is selected as an interrupt through Command
Register I and its interrupt level is enabled, it will
generate an interrupt when the level on this pin
changes from low to high. The edge triggered mode incorporates an edge lockout feature. This means that
after the rising edge of an interrupt request and the
acknowledsment of the request, the positive level on
6-265
210907'()01
"nt_l®
-111'e'
AP·153
P17 won't generate further interrupts. Before another
interrupt ,can be generated P17 must return low.
External devices which generate a pulse for an inter- ,
rupt request can use the edge triggered mode as long as
the minimum high time specified in the data sheet is
met.
Level Triggerin,g
The external interrupt (EXTIN't pin 16) is the only
level triggered interrupt on the MUART. The 8256 will
- recognize any active (high) level on the EXTINT as an
interrupt request. The EXTINT pin must stay high until a short time after the rising edge of the first INTA
pulse. If the voltage level on the EXTINT pin is high
then goes low, the bit in the, interrupt request register
corresponding to EXTINT will be reset.
In the normal mode of operation if EXTINT is still
high after the iNTA pulse has been activated, the INT
signal will remain active. If the microprocessor's interrupt flag is immediately reenabled, another interrupt
will occur. Unless repeated interrupt generation is
desired, the programmer should not reenable the
CPU's interrupt flag until EXTINT has gone low.
In the nested mode of operation, if EXTINT is still
high after the INTA pulse has been activated, the INT
signal will not be reactivated. This is because in the
nested mode only a higher priority interrupt than the
one being serviced can activate the INT signal. The
8085
8088
INTR
EXTINT pin should go inactive (low) before the EOI
command is issued if an immediate interrupt is not
desired"
Depending upon the particular design and application, the EXTINT pin has ~ number of uses. For
example, it can provide repeated interrupt generation
in the normal mode. This is useful in cases when a service routine needs to be continually executed until the
interrupt request goes inactive. Another use of the
EXTINT pin is that a number of external interrupt re, quests can be wire-ORed. This can't be done using
P17, for if a device makes an interrupt request while
P17 is high (from another request), its transition will
be shadoweii. Note that when a wire-OR'ed scheme is
used, the actual requesting device has to be determined by the software in the service routine.
Cascading the MU:4RT's
Interrupt Controller
Cascading the MUART's interrupt controller is
necessary in 'an interrupt driven system which contains
. more than one interrupt controller, such as a system
using more than one MUART, or using a MUART
with another interrupt controller like the 8259A. For a
system which uses several MUART's, one of them is
tied directly to the microprocessor's INT and INTA
pins, while the remaining MUARTs are daisy-chained
'using the EXTINT and INT pins. This is shown in
Figure 11.
-
8256
8256
8256
INT
INTA
Vee
Vee
Figure 11. Cascading- the MUART's Interrupt Controller
6-266
210907-001,
AP-153
Using the configuration in Figure 11, when the
microprocessor receives an interrupt, it generates an
interrupt acknowledge and branches into an interrupt
service routine. For the interrupt service routine of the
external interrupt, EXTINT Level 2, the microprocessor will read the next MUART's interrupt address register and branch to the appropriate service
routine. In effect, this would be a software interrupt
LEVEL 0
INTERRUPT
SERVICE
ROUTINE
acknowledge. An example of this type of interrupt
acknowledge is given in Figure 8. If the last MUART
in the chain indicated an external interrupt, the
microprocessor would simply return to the main program; however, this would be an error condition
caused by a spurious interrupt. A flow chart of the
software to handle cascaded jnterrupts' is given in
Figure 12.
LEVEL 1
INTERRUPT
SERVICE
ROUTINE
• • •
READ
NEXT
INTERRUPT
·ADDRESS
REGISTER.
BRANCH
r----------r::::::::~LT1~~g~~~~~~~I~=EJI~:-:;-------------------,
• • •
. SECOND
MUART
LEVEL 7
INTERRUPT
SERVICE
ROUTINE
READ
NEXT
INTERRUPT
ADDRESS
REGISTER.
BRANCH
TO SERVICE
ROUTINE
•
•
•
Figure 12. Flow Chart to Resolve Interrupt Request When Cascading MUART
Interrupt Controllers
.
6-267
210907·001
Ap,·153
Polling the MUART
Some consideration should be given to the priority of
the mterrupts when cascading MUARTs.If all of the
MUART's Level 0 and Level t interrupts are disabled,
the highest priority interrupt is the EXTINT. In this
case the last MUART in the chain would have the
highest priority; however, it would take the longest
time to propagate back' to the CPU. If, however,
Level 0 or Level 1 interrupts were enabled, the closer
to the microprocessor the MUART is, the higher the
priority these two levels would have.
If intel'fQpts are not used, the only other way to control the MUART is tc;> poll it. It is still possible to use
the priority stnicture of the MUART with polling. In
this mode; of operation the MUA~Ts INT signal (Pin
15) is not used. and the INTA pin is tied high. Since
the INT pin;s level is duplicated in the MSB of the
Status Register, a program can poll this bit. When it
becomes set, the program could read the Interrupt
Address Register to determine the cause. Either the
normal or nested mode of operation can be used. Note
that 'the functions used with this polled method must
have their interrupts enabled.'
When using the 8256 interrupt controller along with
, some othe~ interrupt controller, such as the 8259A,
the MUAR:T's INT signal would simply be tied to one
of the interrupt controller's request inputs. The service routine for the MUART's interrupt request would
initially perform the software interrupt acknowledge
before servicing the MUART's interrupt request.
A block diagram of this cOllfiguration is given 'in
Figure 13.
It is also possible to poll the counters/timers, parallel
I/O, and UART sc;parately. To control the UART,
one could poll the Status Register. Byte handshakes
with the parallel I/O can be controlled by polling Port',
1. Finally, each counter/timer has its own. register
which can be polled.
"
8086A
8088
r
82S9A
INTR ~ INT,
INTA
8258
'.
r--- INTA'
IRm
~
vet""
INT
INTA
, Figure 13. Connecting the 8256 to the 8259A Interrupt Controller
Ap·153
PIN DESCRIPTIONS
Symbol Pin No. Type
A[)()..AD4
1-5
DBS-DB7
6-8
~~~--.--r------~-.
Name and Function
Symbol Pin No. Type
110 Address/Data: Three·
, state address/data lines'
which interface to the
lower 8 bits of the microprocessor's multiplexed
address/data bus. The
S·bit address is latched on
the falling edge of ALE.
In the 8-bit mode, ADO·
AD3 are used to select the
proper register, while
ADI-AD4 are used in the'
16-bit mode. AD4 in the
8-bit mode is ignored as~
an address, while ADO in
the 16-bit mode is used as
a second chip select, active
low.
I
Interrupt Acknowledge:
If the MUART has been
enabled to respond to interrupts, this signal informs the MUART that
its interrupt request is being acknowledged by the
microprocessor. During
this acknowledgement the
MUART puts an RSTn
instruction on the data
bus for the 8-bit mode or
a vector for ,the 16-bit
mode.
INT
15
o
Interrupt Request: A high
signals the microprocessor that the MUART
needs service.
EXTINT
16
I
External Interrupt: An ex-,
ternal device can request
interrupt service through
this input. The 'input is
level sensitive (high),
therefore it must be held
high until an INTA occurs
or the interrupt address
register is read.
CLK
17
I
System Clock: The
reference clock for the
baud rate generator and
the timers.
RxC
18
I
ALE
9
Address Latch Enable:
Latches the 5 address lines
on ADO-AD4 and CS on
the falling edge.
RD
10
Read Control: When this
signal is low, the selected
register is gated onto the
data bus.
WR
11
Write Control: When this
signal is low, the value on
the data bus is written into the selected register.
RESET
12
CS
13
Reset: An active high
pulse on this pin forces
the Ghip into its initial
state. The chip remains in
this state until control information is written.
Chip Select: A low on this
signal - enables the
MUART-: It is latched
with the address on the
falling edge of ALE, and
RD and WR have no effect unless CS was latched
low during the ALE cycle.
6-269
Name and Function
14
110 Receive Clock: If the
baud rate bits in Command Register 2 are ail 0,
this pin is an input which
clocks serial data into the
RxD pin on the rising
edge of RxC. If baud rate
bits in Command Register
2 are programmed from
I-OFH, this pin outputs a
square: wave whose rising
210907·001
inter
Ap·153
PIN DESCR,IPTIONS (CONTINUED)
Symbol Pin No. Type
CTS
Name an~ Functi,on
edge indicates when the
data on RxD is being
sampled. This output remains high during start,
stop, and parity bits.
19
I
Receive Data: Serial data
input.
21
I
Clear To Send: This input
enables the serial ,transmitter. If 1,1.5, or 2 stop
bits are selected, CTS is
level sensitive. As long as
CTS is ~ow, any character
loaded into the transmitter buffer register will be
transmitted serially. A
single negative going
pulse causes the transmission of a single character
previously loaded into the
transmitter
buffer
regis-ter. If a baud rate'
from 1-0FH is selected,
CTS must be low for at
least 1132 of a bit, or it
will be ignored. If the
. transmitter buffer is empty, this pulse will be ignored. If this pulse occurs
during the transmission of
a character up to the time
where 112 of the first (or
only) stop bit is sent out,
it will be ignored. If it occurs afterwards, but
before the end of the stop
bits, the next character
will be transmitted immediately following the
current one. If CTS is still
high when the transmitter
register is sending the last
stop bit, the transmitter
will enter its idle state until tqe next ~-to-low
transition on CTS ,occurs.
6-270
Symbol Pin No. TYPE
Name and Function
If 0.75 stop bits is chosen,
the CTS input is edge sensitive. A negative edge on
CTs results in the immediate transmission of
the next character. The
length of the stop bits is
determined by the time interval between the beginning of the first stop bit
and the next negative edge
on CTS. A high-to-low
transition has no effect if
the transmitter buffer is
empty or if the time interval between the beginning
of the stop bit and next
negative edge is less than
0.75 bits. A high or a low
level or a low-to-high
transition has no effect on
the transmitter for the
0.75 stop bit mode.
TxC
22
I/O Transmit Clock: If the
baud rate bits in command register 2 are all set .
to 0, this input clocks data
out of the transmitter on
the falling edge. If baud
rate bits are programmed
for 1 or 2, this input permits the user to provide a
32x or 64x clock which is
used for the receiver and
transmitter. If the baud
rate bits are programmed
for 3-0FH, the internal
transmitter clock is output., As an output it
delivers ,the transmitter
clock at the selected bit
rate. If 1 Vz or 0.75 stop
bits are selected, the
transmitter divider will be
asynchronously reset at
the beginning of each
210907·001
inter
Ap·153
PIN DESCRIPTIONS (CONTINUED)
Symbol Pin No. Type
DESCRIPTION OF THE REGISTERS
Name and Function
start bit, immediately
causing a high-to-low
transition on TxC. TxC
makes a high-to-low transition at the beginning.-of
each serial bit, and a lowto-high transition at the
center of each bit.
TxD
23
P27-P20
24-31
0
Transmit Data: Serial
data output.
110 Parallel I/O Port 2: Eight
bit general purpose 110
port. Each nibble (4 bits)
of this port can be either
an input or an output.
The outputs are latched
whereas the input signals
are not. Also, this port
can be used as an 8-bit input or output port when
using the two-wire handshake. In the handshake
mode both inputs and
outputs are latchcll.
PI7-PlO
32-39
110 ParaDel I/O Port 1: Each
pin can be programmed as
an input or an output to
perform general purpose
I/O. ,All outputs are
latched whereas inputs are
not. Alternatively these
pins can serve as control
pins which extend the
functional spectrum of
the chip.
,
GND
20
PS Ground: Power supply
,'and
logic
ground
reference.
Vcc
40
PS Power: + SV power supply.
The following section will provide a description of the
registers and define the bits within the registers where
appropriate; Table 4 lists the registers and their
addresses.
Command Register 1
I
L1
1LO 1S1 1SO 1BRKI
(OR)
I
18086 I FRal
BITI
(OW)
FRQ - Timer Frequency Select
This bit selects between two frequencies for the five
timers. If FRQ = 0, the timer input frequency is
16KHz (62.Sus). If FRQ = I, the timer input frequency is 1 KHz (lms). The selected clock frequency is
shared by all the counter/timers enabled for timing;
thus, all·timers must run with the same time base.
8088 - 8088 Mode Enable
This bit selects between 8085 mode and 8086/8088
mode. In 8085 mode (8086 = 0), AO to A3 are' used to
address the internal registers, and an RSTn instruction
is generated in response to the first INTA. 10 8086
mode (8086 = I), Al to A4 are used to address the internal registers, and AO is used as an extra chip select
(AO must equal zero to be enabled). The response to
INTA is {or 8086 interrupts where the first INTA is ignored, and an interrupt vector (40H to 47!1) is placed
on the bus in response to the second iNTA.
BITI - Interrupt on Bit Change
This bit selects between one of two interrupt sources
on Priority Levell, either Counter/Timer 2 or Port 1
PI7 interrupt. When this bit equals 0, Counter/Timer
2 ",ill be mapped into Priority Levell. If BITI equals
oand Level 1 interrupt is enabled, a transition from I
to 0 in Counter/Timer 2 will generate an interrupt request on Levell. When BITI equals I, Port 1 P17 external edge triggered interrupt source is mapped into
Priority Level 1. In this case if Level I is enabled, a
low-to-high transition on PI7 generates an interrupt
request on Level 1.
BRKI - Break-In Detect Enable
lfthis bit equals 0, Port I P16 is a general purpose I/O
port. When BRKI equals I, the Break-In Detect
feature is enabled on Port 1 P16. A ~reak-In condi, tion is present on the transmission line when it is forced to the start bit voltage level by the receiving station.
Port I P16 must be connected externally to ,the
transmission line in order to detect a Break-In. A
6-271
21090Hl01
Ap·153
~
r'[]~
MN/MX !-Vcc
M/m
AD
RESET
8284
...... ClK
CLOCK
READY
GENERATOR RES
WR
INT
iNn
ALE
\
!1!!B
DEN
1---',
I I
I---"n-II L
Il :I
STB
8086
AD o·ADI5
8282
LATCH
2 OR 3
A
Ale·A II ~DRlUATA
-BHE I--
11'1
. II
I III
I III
II
I III
: :II
.
I
ADDR
~
'.::..b-
,.r.-=----'
----"I,
I
:
8286
: I
TRANS I
CEIVER I
~ ~ (2)11
II
L-I - - -
t
II . ~
(16)~
I
'T
.jJl-i-
J
<==>
EXTINT
~
SERIAL 110
t
Figure 16. 8086 Min Mode/8256 Interface
,
I
, MUART....II
SHE
A.
CHARACTERISTICS
0
0
1
1
0
1
0
1
WHOLE WORD
UPPER BYTE FROMrro ODD ADDRESS
LOWER BYTE FROMrro EVEN ADDRESS
NONE
EI -
M/iO
~ E,
!
BHE
E,
0,
ADDRESS
•
A.-A,
8205
00
p r V E N ADDRESS
BYTe PERIPHERALS
110 MAPPED
Figure 16a. Technique for Generating the MUART's Chip Select
6-272
210907-001
Ap·153
Lr~8~~ER
.
f~~~
tacK
8088
CPU
IL STB
8282
A1.A8
Ao,.Ao.
.1ir·R-
OR
.8283
1",",:",-
OE
~
RESETCLK
PORT1
.
"[l=h-
RESET.
C
GEN ERATOR
COMMAND BUS
1'1
~!fEADY
RES
"
n-u It 1
•'MEMORl
OATA
Jl
8288
T OR
~
ERIPHERA
IH>
DATA
11
, UJ
8205
DECODER
8287
DE
1
INT ALE ADo·AD, CSWRRDINTA
0,·0,
8258
PORT2
0 0
TiC RxC TxD
EXTINT
1
Rxb
CTS
~
Serial lID
Figure 17. 8088 Max Mod!,8256 Interface
READING PORT 1 AND PORT 2
Reading the ports gates the state at the pins onto the
data bus if they are defmed as I/O pins. A read operation transfers the contents of 1h,e associated output
latches of pins P12, P13, PIS, and P16, which are defined as control function pins. Reading control pins"
PI0, PH, and P17 delivers the state of these pins.
Operating" the "Event CountersJTimers
The event counters/timers can be loaded with an
initial value at any time. Reading event
counters/timers is possible without interfering with
the counting process.
LOADING EVENT COUNTERSITIMERS
Loading event counters/timers I-S under their respective addresses transfers the data present on the data
bus as an initial value into the addressed event
counter/timer. The event counter/timer counts froin
the new initial value unmediately following the data
transfer (exception: retriggerable mode of Timer S, or
3 and S)
Cascaded counters/timers can be loaded with an
initial value using one of two procedures:
1) Only the event counter/timer representing the most
significant byte will be loaded. The event
counter/timer representing the least significant byte is
set to OFFH automatically. Counting is started immediately after the data transfer.
2) The event counter/timer representing" the most
significant byte will be loaded, causing the least
significant byte to be set to OFFH automatically.
Counting is started immediately following tile data
transfer. Next, the counter representing the least
significant byte will be loaded and counting is started
6-273
210907'()()1
Ap·153
r~
8284 •
CLOCK
GENERATOR
~ClK
-
~
;
,
S.
MWTC
AMYlQ
§",
S,
S.
S,
DEN
I"- DTlii
ALE
,INTR
j'
ClK~
MNIMX i-GND
RESET
READY'
',,"
,
rt
f-i
~
~
AIQY&
' '
' r----'I
8086
ADo·AD"
I
~
..a.-
I
li
8282
lATCH
(2 OR 3)
At.·A,e
J
BHE
,
8286
TRANS·
CEIVERS
L...-
iT
(2)
~IOE
~
II
D
ALE INT INTA WR RD' CS ClK RESET
Abo·AD,
8256
0 5.0,
• PORT1
ID TA
CTS
,
TxD
,
IIxD TxC RxC EXTINT PORT2
~
SERIAL I/O
P
P
Figure 18. 8086 Max Mode:S256 Interface
again, but this time with a complete 16-blt initial
value. The least significant byte of the initial value
must be transfe(red before the counter representing
the least significant 1;>yte exhibits its zero transition tei
prevent ~e most significant byte of the initial value
from being decremented improperly ..
In the case of an 8-bit initial value for Timer 5 or for
cascaded Event Counter/Tjmer 3 and 5" the initial
value for Timer 5 is'loaded from a save register, if it is
operated in retriggerable counting mode. CoUnting is
start~d after an initial' value has been transferred
whenever a high-to-low transition occurs on Port
PIS.
'
Ca&caded Event Counter/Timer 3 and 5 operating in
ret.rigg~rable counting mode can be loaded qirectIy
with an initial value for Timer 5 representing the most
significant byte; Event Counter/Timer 3 wHi be set to,
OFFH automatically.
READING EVENT COUNTERSITIMERS
Reading event counters/time~s .1-5 from their respective addresses gates the counter contents onto the data
bus. The counter contents gated onto the data bus remain stable during the read operation while the
counter just being 'read continues t9 count. The
~inimum time between the two read operations from
the same co~ter is I usee:
The procedure to be followed when reading cascaded
event counters/timers is:
1) The event counter/timer representing the' most
significant byte will be read first. At this time, the
least sigrtificant byte is latched into read latches ..
2) When the event counter/timer representing the
least significant byte is addres~ed, the byte stored in
the read latches will be gateCI onto the. data bus. The
value stored in the read latches remains valid until it is
read, the cascading condition is removed, or a'write
210907-001
inter
Ap·153
18 MHz
VCC
Ji
r~
x,
RESET
X,
iiii
liD
WII
INTO
INTAO
'.
+5V _ SRDY
/
ALE
.f
NMI
.r
HO'D
DT/If
1
1m!
\
80188
ADo·AD
j ·,
~r;=;
8282
LATCH
r- ADDRIDATA
ADDRESS
>
DATA
>
(2)
DE
PCSO
.-C:;8288
TRCVR
(181
~
/
(2)
I~T-
rL
CLOCK RI
GENERATOR
(81
WR
ALE
INTA
ADo·AD,
INT
0,·0,
, ,,
RDRESET
8258
CS
CTS
t
TxD
RxD
TxC
CLK
PORTl
M
PORT2 1 . - .
RxC EXTINT I,....!!L.;
f
'---v-----J
SERIAL 110
t
Figure 19. 8018618256 Interlace
operation affecting one of the two event
counters/timers is execute4.
The time between' reading the most significant byte
and the least significant byte must be at least 1 usec.
Note:
For cascaded event counters/timers the least significant
counter/timer is latched after reading the most significant'
counter/timer. If the lower byte changes from OOH to OFFH
between the readina of the MSB and the latching of the LSB,
the carry from the most significant event counter/timer to the
least significant event counter/timer is lost.
Therefore, it is necessary to repeat the whole reading once if
the value of the least significant event counter/timer is OFFH.
Doing this ~ -avoid. working' with a wrong value (correct
value + 255).
APPLICATION EXAMPLE
This section describes how the 8256 was designed into
a Line Printer Multiplexer (LPM). This application
example waS chosen because it employs a majority of
the MUART's features. The information in this section will be applicable to many other designs since it
describes some cOnUnon software and hardware
aspects of using the MUART.
Description of the Line Printer Multiplexer
(LPM)
The Line Printer Multiplexer allows up to eight
workstations to share one printer" The workstations
transmit serial asynchronous data to the LPM. The
LPM receives the serial data, buffers it, then transmits
(6-275
210907·001
AP·153
Table 4. MUART Registers
Read Registers
Write Registers
8085 Mode:
8086 Mode:
111 LO
AD3
AD4
I S1 I SO IBRKII BITI 180861 FRO I
AD2 AD1
AD3 AD2
ADO
AD1
1 PENI EP I Cl
o
0
0
0
o
0
1 I PEN
0
0
I CT3! CT21 P2C21 P2Cli P2CO! ,'0
0
I I
CO
B31 B2
Command 2
I I I
Bl
BO
I 0 I Rx~IIAE I NIE I
0 ISBRKITS£IiiJ
Command 3
1 T3S1 T241 TSC
1
0
Command 1
o
L1 1 LO! SI 1 SO 1 BRKII BITI 1 80861 FRO I
Command 1
I EP I Cl
1 SET 1 RxE I
I T351
I I I I
1 CO
B3
Command 2
I L6"1
cral CT21 P2C21 P2Cli P2coI
T241 TSC 1
Mode
I
LS 1 L4
LS I L2 ILl
Interrupt Enable
I 07 I 06 I
I
OS I 04 I 03.
02
Interrupt Address
I LO
I
0
0
o
I P171
o
1
lul~I~lul~IL2ll1
PIS I PIS
I
1 DO
I
IWID6ID6I~lool~!~!DOI
6
I 04 103 I 02 I 01 I DO
1 1
o
0
1
o
0
Port 2
IWID6ID6I~lool~I~IDOI
0
o
I
I 07 I 06 I OS I 04
03 I 02 1 01
Port 1
I
I ! 07 I 06 I 05 1 04
03 I 02 1 01
Port 2
o
0
1 07 I .06
I OS I 041
03 I 02
Timer 2
Timer 3
1
I DilDO
1
IwID6ID6I~lool~!~IDO!
o
Timer 4
I
I DO I
Timer 3
IwID6ID6I~lOOI~I~IDOI
liNT I RBF TBE I TRE I BO
Status.
.
Timer 1
! 06 ! OS 1 04 I 03 I 02 101 'I DO 1 I,
Timer 2
! 061 04 I 03
Timer 5
I DO I
IWID6ID6!~loo!~I~IDOI
Time, 1
I 06
~I
Transmillar Buller
1 07 1 06 1 OS 1 04 I 03 I 02 1 01 1 DO I
I 07
I
Reset Interrupts
Port 1
I 07
I
P141 PIS P121 Pll I Pl0
Port 1 Control
o lul~I~IUI~IL2ll1l~1
0
Receiver Buffer
05
.
Set Interrupts
I 01 I DO I
I 07 106 I OS I 04 I D3 I 02 I 01
I 07 I 06 I
BO 1
NIE 1 END ISBR~TBR~ RST!
Command 3
Port 1 Control
L7
Bl
I
IAE
Mode
I Pl?1 P161 PIS 1 P141 PIS I P12 I Pl1 I Pl0 I 0
B2
Tlm~r
I 02
I 01
I PE
I OE I FE
I DO !
I
1
o
I 07 I OS I 05.
1
I 0 I RS4 IRS3 I RS2 IRSI IRSO ITME lose I
.'
6-276
4
I
~
I
03
Timer 5
MOdification
I 02 I 01 I DO ·1
..
210907'()OI
inter
Ap·153
Break-In is polled by the MUART during' the
transmission of the last or only stop bit of a character.
A Break-In Detect is OR-ed with Break Detect In Bit 3
of the Status Register. The distinction can be made
through the interrupt controller. If the transmit and
receive interrupts are enabled, a Break-In Will generate
an interrupt on LevelS, the transmit interrupt, while
Break will generate an interrupt on Level 4, the receive
interrupt. '
SO, S1 -
transmission and reception. In this case, prescaiers are
disabled and the input serial clock frequency must
match the baud rate. The input serial clock frequency
can range from 0 to 1.024 MHz.
BO, B1, B2, B3 -
Stop Bit Length
Stop Bit Length
1
'S1
SO
0
1
1.5
1
1
0
1
2
0.75
o
o
The relationship of the number of stop bits and the
function of input CTS is discussed in the Pin Description section under "CTS".
LO, L1 -
Character Length
L1
LO
o
o
o
1
o
1
1
Character
Length
8
7
6
5
1
Baud Rate Select
These four bits select the bit clock's source, sampling
rate, and serial bit rate for the internal baud rate
generator.
B3
B2
B1
BO
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1'
0
1
0
1
0
1
0
1
Baud
Rate
TxC,RxC
TxC/64
TxC/32
19200
9600
4800
2400
1200
600
300
200
150
110
100
75,
50
Sampling
Rate
1
64
32'
32
64
64
64
64
64
64
64
64
64
64
64
64
The following table gives an overview of the function
of pins TxC and RxC:
'Command Register 2
(PEN
1EP ,I
Cl
(IR)
CO
B3
B2
HI
Bits 3 to
o (Hex.)
BO
(IW) ,
o
Programming bits 0 .. ,'3 with values from 3H to FH
enables the internal baud rate generator as a common
clock source ,"for the transmitter and receiver and
determines its divider ratio.
1,2
Programming bits 0 ... 3 with values of IH or 2H
enables input TxC as a common clock source for the
transmitter and receiver. The external clock must provide a,frequency of either 32x or 64x the baud rate.
The data,'transmission rates range from 0 ... 32
Kbaud.
3 to F
TxC
Input: 1 x baud
rate clock for the
transmitter
Input 32 x or 64 x
baud rate for transmitter and receiver
RxC
input: 1 x baud
rate clock for the
receiver
Output: receiver bit
clock with a low-tohigh transition at
data bit sampling
time. Otherwise:
high level
Output: baud rate Output: as above
clock of the
Itran~mitter
''',
If bits O... 3 are set to 0, separate clocks must be input
to pin Rxe for the receiver and pin TxC for the
transmitter"Thus, different baud rates can be used for
As an output, RxC outputs a low-to-high transition at
sampling time of evary data bit of a character. Thus,
data can be-loaded, e:g., into 'a shift register external-
6-277
210907-091
"nt_l®
111'e' '
Ap·153
Iy. The transition occurs only if data bits of a
character are present. It does not occur for start, parity, and stop bits (RxC = high).
As an output, TxC outputs the internal baud rate
clock of the transmitter. There will be a high-to-Iow
transition at every beginning of a bit.
Bits 4 and 5 define the system clock prescaler divider
ratio. The internal operating frequency of 1.024 MHz
is derived from the system clock.
C1
CO
Divider Ratio
Clock at Pin
ClK
0
0
0
5
3
1
0
1
1
5.12 MHz
3.072 MHz
2.048 MHz
1.024 MHz
EP -
2
1
1) All bits in the Status Register except bits 4 and 5
are cleared, and bits 4 and 5 are set.
2) The Interrupt Enable, Interrupt Request, and Interrupt Service Registers are cleared. Pending requests and indications for interrupts in service will
be cancelled. Interrupt signal INT will go low.
4} If Port 2 is programmed for handshake mode, IBP
and OBP are reset high.
Even ParIty (Bit 6)
RST does not alter ports, data registers or command
registers, but it halts any operation in progress. RST is
automatically cleared.
RST = 0 has no effect. The reset operation triggered
by Command Register 3 is a subset of the hardware
reset.
Parity Enable (Bit 7)
Bit 7 enables parity generation and checking.
'.
PEN =0: No parity bit
PEN = 1: Enable parity bit
TBRK - ,Transmit Break
The parity bit according to Command Register 2 bit 6
(see above) is inserted between the last data bit of a
character and the first or only stop bit. The parity bit
is checked during reception. A false parity bit
generates an error indication in the Status Register
and an Interrupt Request on Level 4:
Command Register 3
The trans,mission data output TxO will be set low as
soon as the transmission of the previous character has
been finished. It stays low until TBRK is cleared. The
state of CTS is of no significance for this operation.
As, long as break is active, data transfer from the
Transmitter Buffer to the Transmitter RegIster will be
inhibited. As soon as TBRK is 'reset, the break condi-,
tion will be deactivated and the transmitter will be reenabled.
SBRK -
, ISET IRxE I IAE INIE I~NO ISBRKfrBRK IRST I
(2R)
Reset
3) The receiver and transmitter are reset. The
transmitter goes idle (TxO is high), and the receiver
enters start bit search mode.
EP = 0: Odd parity
EP = 1: Even parity
PEN -
RST -
If RST is set, the following events occur:
CO, C1 - System Clock Prescaler
(Bits 4, 5)
1
Writing a byte with Bit 7 high sets any bits which were
also high. Writing a byte with Bit 710w resets any bits
which were high. If any bit 0-6 is low, no change occurs to that bit. When Command Register 3 is read,
bits 0, 3, and 7 will always be zero.
(2W)
Command Register 3 is 'different from the first two
registers because it has a bit set/reset capability.
Single Character Break
This causes the transmitter data to be set low for one
character including start bit, data bits, parity bit, and
stop bits. SBRK is automatically cleared when time
for the last data bit has passed. It will start after the
character in progress completes, and will delay the
next data transfer from the Transmitter Buffer to the
Transmitter Register until TxO returns to an idle
6-278
210907·001
Ap·153
(marking) state. If both TBRK and SBRK are set,
break will be set as long as TBRK is set, but SBRK will
be cleared after one character time of break. If SBRK
is set again, it remains set for another character. The
user can send a definite number of break characters in
this manner by clearing TBRK after setting SBRK for
the last character time.
END -
End of Interrupt.
If fully nested interrupt mode is sele<;ted, this bit resets
the currently served interrupt level in the Interrupt
Service Register. This command must occur at the end
P2C2, P2C1, P2CO - Port 2 Control
Direction
P2C2 P2C1 P2CO Mode
Upper Lower
o
0
0
nibble
input
input
o 0 1 nibble
input
output
o
1
0
nibble
output
input
1
1
nibble
output
output
o
1
0
0 byte handshake
input
'1
0
1 byte handshake
output
1
1
0
DO NOT USE
1
1
1
test
of each interrupt service routine during fully nested interrupt mode. END is automatically cleared when the
If test mode is selected, the output from the internal
baud rate generator is placed on bit 4 of Port 1 (pin
35).
Interrupt Service Register (internal) is cleared. END is
ignored if nested interrupts are not enabled.
NIE - Nested Interrupt Enable
When NIE equals I, the interrupt controller will
operate in the nested interrupt mode. When NIE
equals 0, the interrupt controller will operate in the
normal interrupt mode. Refer to the ~'Interrupt controller" section under "Normal Mode" and "Nested
Mode" for a detailed description of these operations.
IAE - Interrupt Acknowledge Enable
Receive Enable
Counterfrlmer Mode
Bit 3 and 4 defines the mode of operation of event
counter/timer~ 2 and 3 regardless of its use as a single
unit or as a cascaded one.
If CT2 or CT3 are high, then counter/timer 2 or 3
This bit enables the serial receiver and its associated
status bits in the status register. If this bit, is reset, the
serial receiver will be disabled and the receive status
bits will not be updated.
Note that the detection of break characters remains
enabled while the receiver is disabled; i.e., Status
Register Bit 3 (BD) will be set while the receiver is
disabled whenever a break character has been
recognized at the receive data input RxD.
SET - Bit SetiReset
If this bit is high during a write to Command Register
3, then any bit marked by a high will set. If this bit is
low, then any bit marked by a high will be cleared.
Mode Register
I T35!
Note:.
If Port 2 is operating in handshake mode, Interrupt Level 7 is
not available for Timer 5. Instead it is assigned to Port 2 handshaking.
CT2, CTa -
This bit enables. an automatic response to INTA. The
particular response is determined by the 8086 bit in
Command Register 1.
RxE -
To achieve this, it is necessary to program bit 4 of Port
. 1 as an output (Port 1 Control Register Bit P14 = 1),
and to program Command Register 2 bits B3 - DO
with a value ~ 3H:
T24! T5C ! CT3! en! P2C2! P2Cl! P2col
(3R)
(3W) .
respectively is configured as an event counter on bit 2
or 3 respectively of Port 1 (pins 37 or 36). The event
counter decrements the count by one on each low-tohigh transition of the external input. If CT2 or CT3 is
low, then the respective counter/timer is configured as
a timer and the Port 1 pins are used for parallel I/O.
T5C - Timer 5 Control
If T5C is set, then Timer 5 can be preset and started by
an external signal. Writing to the Timer 5 register
loads the Timer 5 save register and stops the timer. A
high-to-low transition on bit 5 of Port 1 (pin 34) loads
the timer with the saved value and starts the timer,.
The next high-to-low transition on pin 34 retriggers
the timer by reloading it with the initial value and continues timing.
Following a hardware reset, the save register is reset to
OOH and both clock and trigger inputs are disabled.
Transferring an instruction with T5C = 1 enables the
trigger inpat; the save register can now be loaded with
I
6-279
210907-001
AP·153
an initial value. The first trigger pulse causes the initial
value to be load.ed from the save register and enables
the,coullter to «ount down to zero.
'
When the timer reaches zero it issues an interrupt request, disables its interrupt level and continues counting" A subsequent high-to-low transition on pin 5
resets Timer 5 to its initial value. For another timer interrupt, the Timer 5 interrupt enable bit must be set
again.
T35, T24 -
Cascade Timers
These two bits cascade Timers 3 and 5 or 2 and 4.
Timers 2 and 3 are the lower bytes, while Timers 4 and
5 are the upper bytes. If T5C is set, then both Timers 3
and 5 can be preset and started by an external pulse.
When a high-to-low transition occurs, Timer 5 is
preset to its saved value, But Timer, 3 is always preset
to all ones. If either CT2 or CT3 is set, then the corresponding timer pair is a 16-bit event counter.
A summary of the counter/timer control bits is given
in Table 5.
Note:
Interrupt levels assigned to single counters are partly not oc'
cupied if event counters/timers are cascaded. Level 2 will be
vacated if event counters/timers 2 and 4 are cascaded.
Likewise, Level 7 will be vacated if event counters/timers 3
and 5 are cascaded.
Single event counters/timers generakan interrupt request on
the transition from OlH to OOH, while cascaded ones generate
it on the transition from OOOlH to OOOOH.
Table 5. Event CounterslTlmers Mode of Operation
Event Counterl
Timer
Function
Programming
(Mode Word)
'Clock Source
1
8-bit timer
-
internal clock
2
8-bit timer
T24=0, CT2=0
8-bit event counter
T24=0, CT2=1
internal clock
P12 pin 37
S-bit timer
T35=0, CT3=0
8-bit event counter
T35 =0, CT3 = 1
internlil clock
P13 pin 36
3
4
S-bit timer
T24=0
internal clock
T35=0, T5C=0
internal 910ck
5
S-bit timer,
normal mode
S-bit timer,
retriggerable mode
T35=0, TSC=l
internal clock
16-bit timer
T24=1, CT2=0
16-bit event counter
T24=1, CT2=1
internal clock
P12'pin 37
16-bit timer,
normal mode
T35 = I, T5C=0,
CT3=O
internal clock
16-bit event counter,
normal mode
T35 = I, T5C =0,
CT3=1
P13 pin 36
16-bit timer,
Retriggerable mode
T35 = 1, T5C = I,
CT3=O
internal clock
16-Bit event counter,
Retriggerable mode
T35=1, T5C=I,
CT3=1
PI3 pin 36
2 and 4
cascaded
3 and 5
cascaded
6-280
~
210907-001
inter
Ap·153
Port ,1 Control Register
Port 15 - Timer 5 Trigger
\ PI7 \ P16\ PIS \ P14\ PI3 \ P12\ Pll \ PIO
(4R)
I.
(4W)
Each bit in the Port I Control Register configures the
direction of the corresponding pin. If the bit is high,
thePin is an output. and if it is low the pin is an input.
Every Port 1 pin has another function which is controlled by other registers. If that special function is
disabled, the pin functions as a general 1/0 pin as
specified by this register. The special functions for
each pin are described below.
If T5C is set in the Mode Register enabling a retrig-
gerable timer, then Port IS is the input which starts
and reloads Timer 5.
A high-to-low transition on PIS (Pin 34) loads the
timer with the save register and starts the timer.
Port 16 -
Register I, then this input is used to sense a Break-In.
lf Port 16 is low while the serial transmitter is sending
the last stop bit, then a Break-In,condition is signaled.
Port 17 Port 10, 11 -
Handshake Control
Break·ln Detect
If Break·ln Detect is enabled by BRKI in Command
Port Interrupt Source
If BITI in Command Register I is set, then a low-to-
If byte handshake control is enabled for Port 2 by the
MQsIe Register, then Port lOis programmed as
STBI ACK handshake control input, and Port II is
programmed as IBF/OBF handshake control output.
high transition on Port 17 generates an interrupt request on Priority Level I.
If~ handshake mode is enabled for o~tput on Port
2, OBF indicates that a character has been loaded into
the Port 2 output buffer. When an external device
reads the data, it acknowledges this operation by dri,ving ACK low. OSF is set low by writing to Port 2 and
is reset high byAcK.
Interrupt Enable Register
If byte handshake mode is enabled for input on Port
Interrupts are enabled by writing to the Set Interrupts
Register (5W). Interrupts are disabled by writing to
the Reset Interrupts Register (6W). Each bit set by the
Set Interrupts Register' (SW), will enable that leVel interrupt, and each bit set in the Reset Interrupts
Register (6W) will disable that level interrupt. The
user can determine which interrupts are enabled by
reading the Interrupt Enable Register (5R).
Port 17 is edge triggered.
2, STS is an input. IBF is driven low after STii goes
low. On the rising edge of STB the data from Port 2 is
latched.
'
IBF is reset high when Port 2 is read.
Port 12, n
-
Counter 2, 3 Input
If Timer 2 or Timer 3 is programmed as an event
counter by the Mode Register, then Port 12 or Port 13
is the counter input for Event Counter 2 or 3, respectively.
Port 14 -
Baud Rate 'Generator OutputClotk
If test, mode is enabled by the Mode ,Register and
Command Register 2 baud rate select is greater than 2,
then Port 14 is an output from the internal baud rate
generatQr.
PI4 in Port I control register must be set to I for the
baud rate generator clock to be output. The baud rate
generator clock is 64 x the serial bit rate 'except at
19.2Kbps when it is 32 x the bit rate.
'
L7
I L6 I L5 I'
L4
(5R)
Priority
Highest
LO
Ll
L2
L3
L4
L5'
L6'
Lowest
L7
I L3 I L2
Ll
LO
(5W = enable,
6W = disable)
Source
Timer I
Timer 2 or Port Interrupt
External Interrupt (EXTINT)
Timer 3 or Timers 3 & 5
Receiver Interrupt
Transmitter Interrupt
Timer 4 or Timers 2 & 4
Timer 5 or
Port 2 Handshaking
Interrupt Address Register
o
(6R)
6-281
o
o
D4
L
D3
D2 1 0 1 0 1
21nterrupt Level
Indication
,
210907,001'
AP·153
Reading the interrupt ac;Idress· register transfers an
identifier for the currently requested interrupt level on
the systeM' data bus. This identifier is the number of
the interrupt level multiplied by 4. It can be used by
the CPU as an offset address for interrupt handling.
Reading the interrupt address register has the same effect as a hardware interrupt acknowledge INTA; it
clears the interrupt request pin (lNT) and indicates an
interrupt acknowledgement to the interrupt con. troller.
,(7R)
03
1
D7 I 06' OS 1 D4
(9R)
I 03
02
01
(9W)
'~
DO
Writing to Port 2 sets the data in the :port 2 output
latch. Writing to an input pin does not affect the pin,
but It does store the data in the latch. Reading Port 2 '
puts the input,pins onto the bus or the contents of the
output latch for output pins.
. .
Timer 1·5
Receiver and Transmitter Buner
I 07' 106 I ~5 104 .1
..
Port 2
I 02 I oi I DO
07
I 06 I OS I 04 ,I
03
(7W)
Both the receiver and transmitter in the MUART are
double buffered. This means that the transmitter and
receiver have a shift register and a buffer register. The
buffer registers are directly addressable by reading or
writing to register seven. After the receiver buffer is
full, the RBF bit in the status register is set. Reading
the . receive buffer clears the RBF status bit. The
transmit buffer should be written to 'only if the TBE
bit in the status register is set. Bytes written to the
transmit buffer are held there until the transmit shift
, register is empty, asSuming CTS is low. If the transmit
buffer and shift· r~gister are empty, writing to the
transmit buffer immediately transfers the byte to the
transm~t shift register. If a serial character length is
less than 8 bits, the unused most signlficant,bitsare set
to zero when reading the receive buffer" and are ignored when writing to ~e transmit buffer.
D2
D1
DO
I
(OAI~-OEI6W)
(OAI6-OEI6R)
Reading Timer N puts the cdnterits of'the timer onto
the data bus. If the counter changes while RD is low,
the value on the data bus will not change. If two
timers are cascaded,. reading the high-order byte will
cause the low-order byte to. be latched. Reading the
low-or4er byte will unlatch t~em both. Writing to
either timer or decascading them also clears the latch
condition. Writing to a tinier sets tile starting value of
tnat timer. If two timers are cascad¢d; writing to the
high-order byte presets the low-order byte io all ones.
Loading only the high-order byte with a value of X
leads to a count of X 2S6+2S5. Timers count down
continuously. If the' interrupt is enabled, it 'ocCurs
when the counter 'changes from 1 to O.
.
The timer/counter interrupts are automatically disabled when the interrupt request is generated.
.
Status Register:
I
I
lINT RBF I,TBE TRE·I BO
"
(OF I6R)
Port 1
071061
OS
I 041
(8R)
031 021 D1
IDOl
(8W)
Writing to Port 1 sets tlie data in the Port 1 output
latch. Writing to an input pin,does not affect the pin,
but' the data is stored and win be output 'if the direction of the pin is changed later. If the. Pin is used as Ii
control signal, the pin
not be affected, but the
data is stored. 'Reading Port 1 transfers the data in
Port 1 ~mto the data bus.
will
I PE
I 'DE
I FE I
Reading the status register gates its contents onto the
data bus. It holds the operational status of the serial
iriterface as well as the status of the iriterrupt pin INT.
The status register can be read at any time. The flags
are stable and well defmed at alI'instants'.
FE - Framing Error, Transmission Mode
be used in two modes. Normally, FE infrllIlling error Which can be changed to
transmission mode indication by setting the TME bit
in the modification r\igist,er.
Bit
9 ·.can
~cates
6-282
210907'()()1
Ap·153
If transmission mode is disabled (in Modification
Register), then FE indicates a framing error. A fram·
ing error is detected during the first stop bit. The error
is reset by reading the Status Register or by 'a chip
reset. A framing error does not inhibit the loading of
the Receiver Buffer. If RxD remains low, the receiver
will assemble the next character. The false stop bit is
treated as the next start bit, and no high·to-low transition on RxD is requied to synchronize the receiver.
When the TME bit in the Modification Register is set,
FE is used to indicate that the transmitter was active
during the reception of a character, thus indicating
that the character received was transmitted by its own
transmitter. FE is reset when the transmitter is not active during the reception of character. Reading the
status register will not reset the FE bit in the transmission mode.
OE -
Overrun Error
If the user does not read the character in the Receiver
Buffer before the next character is received and
transferred to this n:gister, then the OE bit is set. The
OE flag is set during the reception of the first stop bit
and is cleared when the Status Register is read or when
a hardware or software~ reset occurs. The first
character received in this case will be lost.
PE -
Parity Error
This bit indicates that a parity error has occurred during the reception of a character. A parity error is present if value of the parity bit in the received character
is different from the one expected according to command word 2 bits 6 EP. The parity bit is expected and
checked only if it is enabled by command word 2 bit 7
PEN.
'
A parity error is set during the first stop bit and is reset
, by reading the Status Register or by a chip reset.
BD -
The break character received will not be loaded into
the receiver buffer register.
, If Break-In Detection is enabled and a Break-In condi-
tion occurs, 'Status Register Bit 3 will be set and in addition an interrupt request on Level 5 is generated.
The BD status bit will be reset on reading the status
register or on a hardware or software reset. For more
information on Break/Break-In, refer to the "Serial
Asynchronous Communication" sectioI), under
"Receive Break Detect"and, "Break-In Detect."
TRE -
TBE -
The BD bit flags whether a break character has been
received, or a Break-In condition exists on the
transmission line. Command Register 1 Bit 3 (BRKI)
enables the Break-In Detect function.
Whenever a break character has been received, Status
Register Bit 3 will be set and in addition an interrupt
request on Level 4 is generated. The receiver will be
idled. It will be started again with the next high-to-low
transition at pin RxD.'
Transmitter Buffer Empty
TBE indicates the Transmitter Buffer is empty and is
ready to accept a character. TBE is set by a chip reset
or the transfer of data to the Transmitter Register,
and is cleared when a character is written to the
transmitter buffer. When TBE is set, an interrupt request is generated on Level 5 if enabled.
RBF -
Break/Break·ln
Transmit Register Empty
When TRE is set the transmit register is empty and an
interrupt request is generated on Level 5 if enabled.
When TRE equals 0 the transmit register is in the process of sending data. TRE is set by a chip reset and
when the last stop bit has left the transmitter. It is
reset when a character is loaded into the Transmitter
Register. If CTS is low, the Transmitter Register will
be loaded during the transmi,ssion of the start bit. If
CTS is high at the end of a character, TRE will remain
high and no character will be loaded ,into the
Transmitter Register until CTS goes low. If t1!e
transmitter was inactive before a character is loaded
into the Transmitter Buffer, the Transmitter Register
will be empty temporarily while the buffer is full.
However, the data in the buffer will be transferred to
the transmitter register immediately and TRE will be
cleared while TBE is set.
Receiver Buffer Full
RBF is set when the Receiver Buffer has been loaded
with a new character during the sampling of the'first
stop bit. RBF is cleared by reading the receiver buffer
or by a chip reset.
INT -
Interrupt Pending
The INT bit reflects the state of the INT Pin (Pin 15)
and indicates an interrupt is pending. It is reset by
INTA or by reading the Interrupt Address Register if ,
only one interrupt is pending and by a chip reset.
6-283
210907·001
Ap·153
FE, OE, PE, RBF, and Break Detect all generate a
Level 4 interrupt when the receiver samples the fmt
stop bit. TRE, TBE, and Break-In Detect generate a
Level 5 interrupt. TRE generates an intCjffUpt when
TBE is set and the Transmitter Regisfer finished
transmitting. The Break-In Detect interrupt is issued
at the same time as TBE or Tlut
~odlflcatlon
RS4 RS3 RS2 RS1 Rs( Point of time between
start of bit and end of
bit measllred In' steps of
1/32 bit .Iength
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I
1
1
1
1
1
I
I
1
1
I
I
I
1
I
1
Register
I 0 I RS41 RS31 RS21 Rsd RSO ITME IDSC I
(OFI6W)
DSC - Disable Start Bit Check
DSC disables the receiver's start bit check. In this state
the teceiver will not be reset if RxD is not low at the
center of the start bit.
TME -Transmission Mode Enable
TME enables transmissiqn mode and disables framing
error detection. For information on transmission
mode,see the description of the framing error bit in the
Status Register.
RsO, RS1, RS2, RS3, RS4 - Receiver sample" .
Time
The ,number in RSn alters when the receiver samples
RxD. The receiver sample time can be modified only if
the receiver is not clocked by RxC.
Note:
The modifiCation register cannot be reacl. Reading from ad·
dress OFH, 8086: lEH gates the contents of the status register
onto the data bus.
- A hardware reset (reset, Pin 12) resets all modification register bits to 0, i.e.:
• The start bit check is enabled.
,. Status Register Bit 0 (FE) indicates framing error.
• The, sampling t~e of the ,serial receiver is the bit
center.·
A software reset (Command Word 3, RST) does not
affect the modifi!=lltion register.
Hardware Reset
,
.
A reset signal on p~ RESET (HIGH level) forces the
device 8256 into a,well-defmed initial state., This state
is characterized as follows:
1
1
1
1
1
I
'I
1
0
0
0
0
0
0
0
0
I
I'
1
1
J
1
I
I
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
I
I
I
1
0
0
0,
0
1
1
1
1
0
0
0
0
1
1
1
I
0
0
0
0
1
1
1
0
0
1
0
0
1
1
I
0
0
1
0
0
I
I
I
0
I
0
0
0
I
1
1
0
0
1
0
0
1
1
1 ,0
0
1
0 0
I
I
1
0
0
I
0
0
I
I
1
0
0
1
0
0
I
I
I
0
0
I
0
0
1 (Start of Bit)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
I~
(Bit center)
17
HI
19
20
21
22
23
24
25
26
27
28
29
30
31
32 (End of Bit)
1) Command registers 1,2 and 3, mode register, Port
1 control 'register, and modification register are
reset. Thus, all bits of the parallel interface are set
to be inputs and event counters/timers are configured as independent 8-bit timers.
2) Status register bits are reset with the ~cepti()n of
bits 4 and 5. Bits 4 and 5 are set indicating that
both transmitter register and transmitter buffer
register are empty.
6-284
210907-001
"
inter
Ap·153
3) The interrupt mask, interrupt request, and interrupt service register bits are reset and disable all requests. As a consequence, interrupt signal INT is
inactive (LOW).
4) The transmit data output is set to the marking state
(HIGH) and the receiver section is disabled until it
Is enabled by Command Register 3 Bit 6.
5) The start bit w~1 be checked at sampling time. The
receiver will return to start bit search mode if input
RxD is not LOW at this time.
6) Status Register Bit 0 implies framing error.
Figure 16 'shows the 8256 interfaced with an 8086 in
the min mode. When the 8256 is in the 16-bit mode,
AO serves as a second chip select. As a result the
MUART's internal registers will all have even addresses since AO must be zero to select the device. Normally the MUART will be placed on the lower data
byte. If the MUART is placed on the upper data byte
the internal registers will be 512 address locations
apart and the chip would occupy an 8 K word address
space. Figure 16A shows a table and a diagram of how
the 8256 may be sel~ted in an 8086 system where the
MUART is I/O mapped and used on the lower byte of
the address/data bus.
PROGRAMMING
Initialization
7) The receiver samples input RxD at bit center.
Reset has no effect on the' contents of receiver buffer
register, transmitter buffer register, the intermediate
latches of parallel ports, and event counters/timers,
respectively.
INTERFACING
This section describes the hardware interface between
the 8256 MUART and the 8085, 8086, 8088, and 80186
microprocesors. Figures 14 through 19 display the
block diagrams for these interfaces. The MUARJ' can
be interfaced to many other microprocessors using
these basic principles.
In all cases the 8256 will be connected directly ~o the
CPU's multiplexed address/data bus. If latches or
data bus buffers are used in a system, the ~UART
should be on the microprocessor side of the addI'ess/data bus. The MUART latches the address internally on $e falling edge of ALE. The address consists of Chip Select (CS) and four address lines. For8-bit microprocessors, ADO-AD3 are the address
lines. For 16-bit microprocessors, ADI-AD4 are the
address lines; ADO is used as a second chip select
which is active low. Since chip select is internally latched along with the 'address, it does not have to re. main active during the entire instruction cycle. As long
as the chip select setup and hold times are, met, it can
" be derived from multiplexed address/data lines or
multiplexed address/status lines.
In Figure 15, the 8088 min mode, the 8205 chip select
decoder is connected to the 8088's address bus lines
A8-AI5. These address lines are stable throughout the
entire instruction cycle. However, the MUAR1"s chip
select signal' could have been derived from AI6/S3'
AI9/S6.
In general the MUART's functions are independent of
each other and only the registers and bits associated
with a particular function need to be initialized, not
the entire chip. The command sequence is arbitrary
since every register is directly addressable; however,
Command Word 1 must be loaded fIrst. To put the
device into a fully operational condition, it is
necessary to write the following commands:
Command byte 1
Command byte 2
Command byte 3
Mode byte
Port 1 control
Set Interrupts
The modification register may be loaded if required
for special applications; normally this operation is not
necessary. It is a good idea to reset the part before initialization. (Either a hardware or a software reset will
do.)
Operating th~ Serial Interface
The microprocessor transfers data to the serial interface by writing bytes to the Transmit Buffer Register.
Receive characters are transferred by reading the
Receiver Buffer Register. The Status Register provides
all of the necessary information to operate'the serial '
I/O, including when to write to the Transmit Buffer,
and when to read the Receive Buffer and error information.
Transmitting
The transmitter and the r~eiver may be operated by
using either pOlling or interrupts. If polling is used
then the software may poll the Status Register and.
write a byte to the Transmit Buffer whenever TBE = 1.
Writing a byte to the Transmit Buffer clears the TBE
6-285
210907-001
AP·153
v
~o~
::::
::::
TRAP
RST 7.5
RST 8.5
RST 5.5
x,
r
v
fS
x,
l
RESET IN
HO~D
H~DA
SOD
SID
SI
So
8085A
:::
;::
::::
II:
Q
~
10
M
~~~~
II:
'~
<
i
Q
Q
I jj
A~E
vm CLK~~~E~NT ffm
IL..~
Q
Q
€
<
irxC
RxD
ClK
rn
iUi
,
'
RESET
TxD
WIi
€
....
Til: : : : } Serla lifO
::::
Port 1 ... (8) .....
ALE
T
ADO·AD4
DBS·DB7
I.....................
DE~~~ER I
L.-
Port 2
CS
EXTINT
~
I~
8282
~TeH
Q
W
€
TO
Vee
GND
t
t
,
'(ar')
v---Y
I-
€
v
NON·MULTIP~EXED
PERIPHERALS
Figure 14. 8085/8256 Interface
status bit. If the CTS pin is low, then the Transmit
Buffer will transfer the data to the Transmit Register
when it becomes empty. When this transfer takes
place the TRE bit is reset, and the TBE bit is set indicating the next byte may be written to the Transmit
Buffer. If ffi is high, disabling the' transmitter, the
data byte will remain in the Transmit Buffer and TBE
will remain low until CTS goes low. The transmitter
can only buffer one byte if it is disabled.
There is no way of knowing that the transmitter is
disabled unless the CTS signal is fed into one of the
I/O ports. Using the transmitter interrupt will free up
the CPU to perform other functions while the
transmitter is disabled or while the Transmit Buffer is
full.
To enable the transmit interrupt feature Bit L5 in the
Set Interrupt Register must be set. An interrupt request will not occur immediately after this bit has been
set. Before any transmit interrupt request will occur a
byte must be written to the, Transmit Buffer. After the
first byte has been written to the Transmit Buffer, a
transmit interrupt request will occur, providing the
transmitter is enabled.
There are three sources of transmitter interrupt requests: TBE= 1, TRE= 1, and .Break-In Detect.
Assuming the Break-In Detect feature is disabled,
after the transmit interrupt is enabled and the first
byte is written, a transmit interrupt request will be
generated by TBE ,going active. The microprocessor
can immediately write a byte to the Transmit Buffer
without reading any status. However if Break-In
Detect is enabled, the Status Register must be read to
determine whether' the transmit interrupt request was
generated by Break-In Detect or TBK'
The TRE interrupt request can be used to indicate
when the transmitter has completely sent all of the
data. For example, using half-duplex conimunica-
210907·001
Ap·153
n;;;lttt
R '".,,~
IIII -r:::-.
'-'",.... 1
-ClK
AD,.AD,
MNlMX
A~
f'---o'
eI
ADDRIDATA'
ADO-ADIoPORT 2
D5-D7
-vcc
-I-
~
R
-
READY
8088
,8284A
ClK
READY
101M
INTR
--"
--.I'
~
iN'i'A
RxD
INTR
IJMET
C'B
SERIAL UO
lID
at~
m
I r - - RESET
RESET f-l
X,
RiC
TxD
8258
iNn
A,,1S3-A,,IS8
P
EXTINT-
x.
'-oJ
Figure 15. 8088 Min Model8256 Interface Multiplexed Bus
tions, all of the data written to the MUART must be
transmitted before the line can be turned around.
After the last byte is written, an iDterrupt request will
be generated by TBE. If this interrupt is acknowledged without writing another byte, then the next
transmitter ipterrupt request, TRE = 1, will iDdicate
that the' transmitter is empty and the line may be
~UrQ.ed around.
RECEIVINQ
Valid data may be read from the Receive Buffer
whenever the RBF bit iD the Status'Register is set.
Reading the Receive Buffer resets the UF status bit.
The RBF bit iD the Status Register can be used for
polling. When the RBF bit is ,set, the 'three receive
status bits, PE, OE, and FE are updated. These three
status bits are reset when they are read. Therefore
when the status register is read with UF set, the three
error status bit should be tested too., .
If iDterrupts are used for serial' rectiV'e: data, the
receiver must be enabled by setting the RxE bit iD
Command Register 3, and Bit lA must be set iD the Set
Interrupt Register. When the receive iDterrupt ,request
occurs the Receive Buffer may be read, but, the status
register should also be read since the receive interrupt
could have been generated by the Break Detect. -Also,
reading the status register will indicate whether there
were any errors in the received character.
Operating the Parallel Interface
Data can be transferred tel or read from Port 1 and
Port 2 by using the appropriafe write and read operations.
LOADING PORT 1 and PORT 2
Writing to the ports transfers the data present on the
data bus into the output latches. This operation is independent of the programmed I/O characteristics of
the individual port pins. Writing to control or input
ports' has. no effect on the state of the pins. Pins defined as outputs immediately assume the state which is
associated with the transferred data. If inputs or control piDs are reprogrammed into outputs, they assume
the states stored iD'their output latches which were
transferred by the most recent port write operation.
6-287
210907'()01
Ap·153
Line Printer
Figure 20. Using the Line Printer Multiplexer to Share a Line Printer
it to the line printer using a two-wire byte handshake
Dataproducts interface. A conceptual diagram of this
,system is shown in Figure 20. Note that only one
workstation can transmit at a time. This workstation
will transmit its entire. file before another workstation
will be allowed to transmit.
The LPM sequentially polls each of the eight RS-232
ports for a Request To Send (RTS). When it finds a
serial port which has asserted RTS, it configures itself
for the appropriate data format and bit rate,
esiablishes the connection and sends back to the serial
port a Clear To Send (CTS) which enables transmission. The LPM receives the' serial asynchronous data,
buffers it in a software FIFO, and transmits the data
to the Ii~e printer. If the LPM detects an error in any
of the serial characters it receives, it transmits an error
message to the serial port and ignores the bad
character. If the LPM does not receive a serial
character after 18 seconds, it assumes that the
transmission is complete. It transmits the final status
to the serial port, and returns to scanning.,
This LPM was designed to be used with single-user'
workstations and a 300 lines per minute line printer.
These workstations are not multitasking; therefore in
the middle of a file transfer when the CPU needs to
reload its buffer from' the disk, no serial data is
transmitted. During this time the LPM is emptying its
FIFO; thus, the line printer never stops printing.
The buffer size on the LPM was chosen to complement the disk access time on the workstations. Figure
21 illustrates the buffer size calculation. The line
printer can print up to 300 lines per minute, or approximately 660 characters per second. This corresponds to a serial transmission rate of 6,600bps
(assuming ASCII character codes and a parity bit) as
shown· in equation 1.
(1) Serial bit rate = (300 Iines/min)*(l32 char/line)*(10 bits/char)
for the line I>rinter
' . (60 sec/min)
The bottleneck in this data transfer is the line printer
since the MUART and the, workstations can both
transmit and receive at 19.2Kbps. To realize the maximum data transfer rate of this system the, LPM mUst
guarantee that the average transfer rate to the line
printer is 660 characters per second. The maximum
amount of dead time that the serial port on· the
workstation is not transmitting, multiplied by 660 is
the number of bytes which the LPM should buffer. It
was cietermined through experimentation that it takes
about 3 seconds to load 40K bytes of data from the
disk into the workstation's RAM. During these 3
seconds no serial data is being sent; therefore the buffer size on the LPM should be 2K bytes. (Note: even
though only a 2K byte FIFO is required, this design
used an 8 Kbyte FIFO.~
To keep the LPM's buffer full the ,serial data rate must
be greater than6.6Kbps. The two bit rates which the·
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LINE
PRINTER
"IODBPS
OR
19,200 BPS
LPM
iii
300 LINES/MIN
Fig.... 21. I,:PM Buffer Size Calculation
UPPER NIBBLE ,
FIRST BYTE
•
L1 LO
o
o
0 ..BIT
1 7
1 0 •
005
LOWER NIBBLE
SECOND BYTE
LoI_x.......ll...-x_ ...
1_x--L1_x--r.1_B.;.3......1...;.B2~...1~B1.......1II...-BO;.;...-,
~
BAUD RATE SELECT
B3 B2 B1 BO BIT RATE
0 0 0 DO NOT USE
000 1 DO NOT USE
001 0 DO NOT USE
001 1 19200
o 1 0 0 9800
o 1 0 1 4800
1 1 0
2400
1 1 1
1200
100 0
IOD
100 1
300
, 200
101 0
o
o
o
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
150
110
100
75
50
Figura 22. Programming Words Format for LPM
workstations use are 9.6Kbps and 19.2Kbps. The crs
signal is used to control the flow of the serial data so
that the LPM buffer will not overflow.
Each serial port on.the LPM can have a different bit
rate, character length, and parity format. These
parameters are programmable through the serial port.
When the LPM powers up, or is reset, it expects a bit
rate of 9600 bps. 7 bit characters,' and odd parity.
When a serial port receives an ASCU ESC character
(lBH), it puts that port in the program mode. The
next two bYtes will program these three "parameters.
Only the lower mobles of these ,two bytes are used,
and the upper nibbles are" discilrded. The format of
these programming words is given in FIgUre 22. If the
word following the ESC is an ASCR NUL (0), the
, LPM will exit from ~e programming mode and not
change any of its parameters.
6-289
210907'()()1
AP·153 "
. Description 'of the 'Hardware
full. Parallel Port 2 and two'bits fr.om Port I are con·
nected to the line printer implementing a two-wire
byte handshake transfer. These signals are passed '
don to the standard' components of most ,through a line .driver so that ttley can reliably drive.a
microp~ocessor systems such as Cpp, RP,.,M, and
i
b'
."
R.OM this particular design reqjlires a UART, timers;,' , :" ong ca Ie.
:f}, .
'
parallel I/O and an interrupt controller': The MUA'R1" ,
1.
.
"
'., ,','
is the ideal choice for this design since it integrates
:there are three timing,funliioq§ needed for the LPM:
t~ese four functions ont~ one, device.
a scan timer, a debounee timer, and a recieve timeout.
. The Scan timer determines the amount of time spent
The eight serial 1/0 ports,use four.signals: Transmit
sampling RTS on each port ·b.efore the next port is ad- '
Data (TxD), Receive Data ~), Request TQ. Send , ' dress~. By usiJl,g one of the MUART's timers to do
(RTS), and Clear To Send (CTS). These four signals,
this function, the' CPU is free to perform other funccontrolled by the MUART, are connected to one port
tions instead of implementing the timer in software. If
~t a time using TTL multiplexers. The TTL ll1ultiplexRTS is recOpized as true, the CPU branches into a
ers are interfaced to RS-232 transceivers to' be -elec- .. debounce procedure. This procedure uses another one
trically compatible with the RS-232 spec. The serial .. of the MUART's diners. to wait 10' msec then sample
Port select address is derived ,from three bits of, the
ag~, ~,~us preventing any glitches from register- ,
MUART's parallel 1/0 port (Port 1). 1:wo more bits
.irig as,a·false ttTS". The receive timeout timer uses two,
from Port 1 control CTS and RTS, and another bit
8-blt' tifqerS ill- the cascaded mode to measure an .
IS-seCond 'int~iV8I. After a validt RTS is recognized,
lights up an LED to indicate when the LPM's buffer is
Figure 23 shows a block dIagram of the LPM. In addi-
.m
r-----;:----
----------l
I
I
I
I
I
I
I
L-.
'=:'1".-:c=.....;='=:--h:c:J=.
::::-t:'"---J;:::~.:1 Be"al
,
VO porls
L.J', ,C......J 'L.J. C).
'1--;
I ,.CJ=.
!
Figure ,23. Functional Block Diagram of the Line Printer Multiplexer
6,..290
, 210907-001
"n+_I®
111'eII·
Ap·153
the LPM sends back a CTS and initializes the receive
timeout timer for 18 seconds. Each time a character is
received by the LPM, this timer is reinitialized. If this
timer times out, the LPM considers the transmission
complete and returns to scanning.
The schematic diagram of the LPM is shown in Figure
24. The CPU is an 8088 used in the min mode. It is in.
terfaced directly to the 8256. An 8282 latch is
employed in the system so that nonmultiplexed bus
memory can be used. A 2716 holds the entire program, and six 2016s (2K x 8 static RAMs) are used to
store the buffer, temporary data, stack area, and interrupt vector table. The 2716 is located in the upper
2K of the 8088 address space (FF8oo- FFFFFH) so that
the reset vectors can be stored starting at location
FFFFOH. The RAM address space spans 0-2FFFH so
that the interrupt vector table can be stored starting at
location O. The MUART is I/O mapped and its
registers occupy even addresses from 0 to lEH. Using
an 8088 CPU the MUART must be placed in the 8086
mode since the INTA signal is used; hence the register
addresses are all even numbers.
The line printer used provides a choice of two stan·
dard parallel interfaces: Centronics or Dataproducts.
The Centronics interface uses a two·wire handshake
pulsed strobe where the transmitter asserts a complete
strobe pulse before .an acknowledge is received. The
Dataproducts interface is an interlocking two-wire
handshake. The Dataproducts interface was chosen
since it is directly compatible with the MUART's
two-wire byte handshake. The MUART could also be
connected to the Centronics interface; however, additional hardware would be necessary to generate the
pulsed strobe for correct interrupt operation. Figure
25 shows the timing of the Dataproducts interface and
Table 6 lists the connector pin configuration.
Table 6. Dataproducts Interface Line Functions
Signal
Description
Connector Pin
Data Request
Sent by printer to synchronize data transmission. When
true, requests a character. Remains true until Data
strobe is received, then goes false within 100 nsec.
Data Strobe
Sent by user system to cause printer to accept
information on data lines. Should remain true until
printer drops Data Request line. Data lines must
stabilize for at least 50 nsec before Data Strobe is sent.;
E(return C)
I
Data
Data
Data
Data
Data
Data
Data
Data
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
1
2
3
4
5
6
7
8
Bit 8 controls optional character set
Refer to Commands and Formats.
j(return m)
B(return D)
F(return J)
L(return N)
R(return T)
V(return X)
Z(return b)
n(return k)
h(return e)
Optional control from user system. Used for VFU
control. Data Request/Strobe timing is same as for data
lines.
p(return s)
Sent to user system:by printer. Title when no Check
condition exists.
Cqreturn EE)
On Line
Sent to user system by piihter. True when Ready
line is true and operator has activated ON LINE
Pushbutton. Enables interface activity.
y(return AA)
Interface
Verify
Jumper in printer connector. Continuity informs user
system that connector is properly seated.
x to v
Supply voltage for Exerciser only.
HH
VFU Control
(PI)
Ready
+5V
6-291
210907'()01
Ap·153
.'
-r
RUIET
.1....
t11
IN
-:...L ' ".
110Q
.,
TvltlCAL
, OF.
T021"'1f)
T021211(E)
•••
.......
$TA11C
0II1111A/
THAU
01111(1'1
T021_
T021111C1
T02121(8)
1
1
1
'I
1
I
1
I
I
I
I
1
I
IL ________
,1
~
___ JI
Figure 24. Sch8matlc of LPM
6-292
21 0907-001
Ap·153
3
.'f!
m·
m
•
T_D :I
.
"
I
--1
~------i
'''0 3
r::I.
:£j:
..0'
r=I.
~~
LED
Figure 24. Schematic oi LPN! (Continued) .
6-293
210907-(lOl
Ap·153
,
~~I------------------------------~n
READ~
ON· LINE
----./1-1 i1t---------:-2~ SEC MIN ------------l~~'1
I
,t-----1I I I
_- 100-NSEC
'
-_ _ _ _ _---,1
DATA REQUEST
DATA LIN,ES _
1 THROUGH 8 & Pl
-+l •~ 50 NSEC MIN
DATA_ST_R_O_B_E_ _ _ _ _ _ _
'
_I-Jlf?'
\'-----
Figure 25. Timing of Dataproducts Interface
Only ten signals are uS,ed to interface the LPM to the
line pri\1ter: Data Request, Data Strobe, and the eight
data lines. The most significant data line is not used
since the character code is 7-bit ASCII. Data Strobe
connects to OBF on the MUART; however, for the
Datapro?ucts interface this signal must be inverted.
Data Request is connected to ACK on the MUART.
When the line printer is ready to accept data, the Data
Request signal goes high. The 8256 will not interrupt
the CPU to transmit parallel data unless this'signal is
high.
The Dataproducts interface is slightly different from
the MUART's two-wire handshake in that it latches
'the data on the leading edge of the strobe signal.
When the MUART receives bytes it latches the data on
the trailing edge. As a result the Dataproducts interface has a,50 nsec setup time for data stable to the'
, leading edge of Data Strobe. In the LPM hardware a
delay line was used to realize this setup time.
Description of the Software
The software is written in PLiM and is broken up into
four separate modules, each containing several procedures. A block diagram of the software structure is
given in Figure 26. The modules are identified by the
dotted boxes, and the procedures are identified by the
solid boxes. Two or more procedures connected by a
solid line means the procedure above calls the procedure below. The procedures without any solid lines
connected above, are interrupt procedures. They are
entered when the MUART interrupts the CPU and
vectors an indirect address to it.
The LPM program uses nested interrupts; the priority
of the interrupt procedures is given in Table 7.
Table 7. Line Printer Multiplexers' Interrupt
Priority
Priority Source
Debounce timer
Highest
0
1
Not Used
2
Not Used
Receive timer
3
RxD Interrupt
4
TxD Interrupt
5
6
Scan timer
7
LP Interrupt
The priority of the interrupts is not,programmable but
they are logically oriented so that for this application
the priority is correct. In the steady state of the LPM's
operation the UART will be receiving data, and the
parallel port will· be' transmitting data. The serial
receiver should be the highest priority since it can have
overrun errors. This is the case because the debounce
timer will be disabled, and the receive timeout interrupt will only occur when serial reception has ended.
Therefore the RxD request can interrupt any other service routine, thus preventing any possibility of an
, overrun error.
6-294
21090HlOl
AP-153
~------------,
MAIN_MOD
SCAN
I
r.;--,PON_MOD
I
I
--...,
I
POWER$ON
I
I
I
I
I
I
I
I
,
L _______ J
I
L ____________ J
i'NLMOD- - -
I
I
SCAN$TIME
---------------
IDEBOUNCE$TlME I I RECEIVE$TIME I
I
---,
LOAD$INT$TABLE
I
I
D!IJ .JI
____________
I
'---
Figure 26. Block Diagram of LPM Software Structure
On power-up the CPU branches from OFFFFOH to
the INITCODE routine which is included in the
machine code by the MDS locater utility. INITCODE
initializes the 8088's segment registers, stack pointer,
and instruction pointer, then it disabled interrupts and
jumps into MAIN_MOD. The first executable instruction in MAIN~OD calls POWER$ON, which
initializes the MUART, flags, variables, and arrays.
The MAIN~OD calls LOAD$INT$TABLE, which
initializes the interrupt vector table. The CPU's interrupt is then enabled and the program enters into a DO
FOREVER loop which scans the eight serial ports for
antrrn.
There ar.e three software functions which employ the ,
MUART's timers and interrupt controller to measure
time intervals: SCAN, debounce, and INIT$RECEIVER. DEBOUNCE and INIT$RECEIVER
procedures, employ the MU~RT's ,timers and interrupt controller to measure time intervals. The CPU remains in a loop for a specific amount of time before it
proceeds with the next section of code. In this loop the
CPU is waiting for a global status flag to change while
servicing any interrupts which may occur. When the
appropriate timer interrupt occurs, the interrupt service routine will set the global flag which causes the
CPU to exit the loop anll proceed to the next section
of code. An example can be seen from the scan flow
chart in Figure 27.
The fir'st thing the program does before entering the
loop is set the flag (in this case SCAN$DELAY)
TRUE. The timer is initiatized and the loop is entered.
As long as SCAN$DELAY is TRUE the CPU will
continue to sample RTS. If RTS remains false Jor
more than 100 msec, the timer interrupts the CPU and
'the interrupt service routine sets SCAN$DELAY
FALSE. This causes the CPU to exit the loop and address the next port. The process is then repeated: If
RTS becomes true while it is being sampled, the DEBOUNCE procedure is called.
DEBOUNCE does n~thing more than wait 10 msec
and sample RTS again using the saJIle technique
discussed above. .If RTS is' still valid INIT$RECEIVER is called, otherwise the CPU returns
to scan.
6-295
. ,210907·001
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CALL ERROR
PROCEDURE
ADDRESS NEXT PORT
Flgu~
FigUre 28. RxD Interrupt Procedure Flow Chart
27. Scan Flow Chart
INIT$RECElVER calls CONFIGURE which programs the MUJ\RT fOf the l1it r:ate, number of bits in a
character" an~parity fprm4t. This information is
stored in an array calle4 SERI~$FORMAT, which
contains . a byte for each pori. The bytes, in tlte
SERIAL$FORMAT array have the same bit def'mition
as the two nibbles in the pr9glamnii~ words j.n, Figure
22. Upon returning to INIT$RECEIVER the receiver
is enabled, the reCeive tiineout timer is initialized. IlIld
the timer and receiver interrupts
enabled. CTS on
the:serial,poit is then set true, and the 'CPU ~iers Ii
loop which does nothing except wait for 18 seconds. If
no characters are received within 18 seconds, the
receive timeout interrupt occurs'arid the loop flag is
set false, which caps,es the CPU to exit the'loop. If a
character is ,tcic"ived, a receive inter:rupt oc'curs, and
the' CPU veCtors into the RiD interrupt 'service
routine.
are
Figure 28 shows a flow chart of the RxD interrupt service routine. This routine begins by reading the receive
buffer and reinitializing the receiv'e timeout timer.
There are two conditions to check for before the
character can be inserted into the FIFO. First, if there
are any errors in the received character, an ERROR
procedure is called which reports back, to the serial
port what the error condition was. The character ,in error is discarded and the routine, returns. The other
condition is that if the received character is an ASCII
ESC, the PROGRAM procedure is called. If neither
one of these conditions occurs, the character is'placed
in the FIFO by the BUFFsIN procedure.
The LP interrupt routine is entered when the byte
handshake interrupt r:eQuest is acknowledged. This
routine simply calls the BllFFSqUT procedure, which
extracts a byte out of the ;FIFO. BUFFSOUT returns
the byte to the LP interrupt proc,~dure, which then
writes it to Port 2. One small problem with getting the
handshake,interrupt going is'that the first byte has to
be written to Port 2 J;!efore the first hlmdshake interrupt will' occur. The problem is that the line printer
may not be ready for the first byte. This would be indicated by DATA REQUEST being low. If the byte
was written to the LP while DATA REQUEST is low,
it would be lost. Note that if the handshake interrupt
is enabled while DATA REQUES~ is low, then DATA
REQUEST goes high, the interrupt will occur without
6-296
21090HlOl
Ap·153
writing the first byte. There are several ways to solve
this problem. Port 1 can be read to find out what ·the
state of the DATA REQUEST line is. If DATA REQUEST is low, the CPU can simply wait for the interrupt without writing the first byte. If DATA REQUEST is high, then the first data byte may ~ written. Another solution would be to write a NUL
character as the first &yte to Port 2. If DATA
REQUEST is low, then a worthless character is lost. If
DATA REQUEST is high, the NUL character would
be sent to the line printer; however, it is not printed
since NUL is a nonprintable character. The LPM program uses the NUL character solution.
BUFFER MANAGEMENT
The FIFO implementation uses an 8K byte array to
store the characters. There are two pointers used as indexes in the array to address the characters:
IN$POINTER and OUT$POINTER. IN$POINTER
points to the location in the array which will store the
next' byte of data inserted. OUTSPOINTER points to
the next byte of data which will be removed from the
array. Both IN$POINTER ~d OUT$POINTER are
declared as words. Figure 29 illustrates the FIFO in a
block diagram.
The BUFFSIN procedure receives a byte from the
RxD interrupt routine and stores it in the array location pointed to by IN$POINTER, then IN$POINTER
is incremented. Similarly, when BUrnOUT is called
(0)
, l+- FIF~ (oUT$POINTERI
t-- FIFO (lN$POINTERI
Figure 29. FI FO Structure and Status
by the LP interrupt routine, the byte in the array
pointed to by OUT$POINTER is read.
OUT$POINTER is incremented, and the byte which
was read is passed back to the LP interrupt routine.
Since IN$POINTER and OUTSPOINTER are always
incremented, they must be able to roll over when they
hit the top of the 8K byte ,address space. This is done
by clearing the upper three bits of each pointer after it
is incremented.
IN$POINTER and OUT$PONTER not only point to
the locations in the FIFO, they also indicate how
many bytes are in the FIFO and whether the FIFO is
full or empty. When a character is placed into the
FIFO and IN$POINTER is incremented, the FIFO is
full if IN$POINTER equals OUTSPOINTER. When
a character is read from the FIFO and OUT$POINTER is incremented, the FIFO is empty if
OUTSPOINTER equals IN$POINTER. If the buffer
is neither full nor empty, then it is in use. A byte called
BUFFER$STATUS is used to indicate one of these
three conditions.
The software uses the buffer status information to
control the flow into and out of the FIFO. When the
FIFO is empty the handshake interrupt must be turned
off. When the FIFO is full, CTS must be sent false so
that no more data will be received. If the buffer status
is in use,
is true and the handshake interrupt is
enabled.
rn
Figure 30 shows the tlow chart of the Burn IN procedure. The BUFFS IN procedure begins by checking
the BUFFER$STATUS. If it is empty and the
character to be inserted into the FIFO is a CR or LF,
Ithe handshake interrupt is enabled, a NUL character
is output, and the BUFFERSSTATUS is set to INUSE. The character passed to BUrnIN from RxD is
put into the FIFO. If the FIFO is now full, the BUFFERSSTATUS is set to FULL, CTS is set false, and
the buffer full LED is turned on.
Figure 31 shows the flow chart of the BUFF$OUT
procedure., After the character is read from the FIFO;
the FIfO is tested to deter~ne if it is empty. If it is·
not-empty, the BUFFER$STATUS,is FULL and there
are 200 bytes available in the fIFO, serial data reception is reenabled, and the FIFO fi~ again~ile data'
is being received from the workstation, CTS toggles
high 'and low, ,mling up and emptying the last 200
bytes in the FIFO. ~eferring to the top of the flow
chart (FIFO empty test) if it's empty, the BUFFER$STATUS is set to EMPTY, and the handshake
interrupt is disabled. During this time all interrupts
6-297
210907'()()1
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, This is known as a critical section of code. Suspicion
should arise for a critical section of code when two or
more ·nested interrupt routilies can affect the same
status. One solution is to disable the interrupt flag at
the CPU while the status and conditional operations
are peing modified.
The flow chart for the TxD interrupt proce9ure is
given in Figure 32. For this program five different
messages can be transmitted;' .and they are stored in
ROM. It is possible to downioad the messages into a
dedIcated RAM Duffer; however, the RAM buffer
would have to be as large .as the largest message. A
'more efficient way to transmit the messages is to read
them from ROM. In this c~~ the address of the first
byte of the message would have be accessible by the
transmit interrupt procedure. Since parameters cannot
be passed to. interrupt., procedures, this message
pointer is declared PUBLIC in one module and EXTERNAL in the'other modules.
to
To get the traqsmit interrupt started, the first byte of
the message must be Written to the transmit buffer.
When a section of code decides to transmit a message
serially, it loads the global message pointer with the
address of the first byte of the message, enables the
transmit interrupt, and calls the TxD interrupt procedure. Calling the TxD interrupt procedure writes the
first byttl to the transmit buffer to initiate transmit interrupts. This 'can be done by calling PL/M's built-in
procedure CAUSE$INTERRUPT.
Figure 30. Flow Chart of the BUFF$IN Procedure
are disabled at the CPU. (Remember that the RxD interrupt routine- can interrupt the LP and BUFF$OUT
proced\H'es since it 'has a higher priority,- and the
MUART'is in the nested mode.)
"
If the CPU interrupt w,as not disabled during this
time, the following' events could occur' which would
cause the LPMto crash. Assume that the RxD inter~'
rupt occured where the asterisk is in the flow 'chart,
after BUFFER$STATUS is set 'to EMPTY. The
BUFF$IN procedure wduld set.BUFFER$STATUS to
INUSE and enable.the handshake interrupt. When the
RxD interrupt routine returned to BUFF$OUT, tl).e
handshake interrupt is disabled, but, the BUFFER$STATUS is'INUSE. Thehandsh8ke interrupt
could never be reertabled,. and the FIFO would' fill up.
.
The transmit interrupt routine checks each byte before
it writes it to the transmit buffer. The last character in
each message is a 0, so if the character fetched is 0, the
transmit interrupt is disabled and the character is
ignored.
USING THE LPM WITH THE INTELLE~
MICROCOMPUTER DEVELOPMENT
SYSTEM, SERIES II OR SERIES III
A special driver program was written for the MDS to
communicate to the LPM. This program, called,
WRITE, reads a specified file from the di$k, expands
any TAB characters, and transmits the data through
Serial Channel 2 to the LPM. Serial Channel 2 was
chosen because CTS and RTS-are brought out ~o the
RS-232 connector. The WRITE program is listed in
appendiX B. It wi!.s also necessary to modify the b~ot
ROM of 'the development 'systeqt so that Serial Channe12 initializes with RTSJalse anll a bit rate of 9600
bps .. , .
-
6-298
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AP·153
Flgl!re 31. Flow Chart of the BUFF$OU,T Procedure
Figure 32. Flow Chart for TxD Interrupt Procedure
6-299
210907·001
Ap·153
APPENDIX A
LISTING OF THE LINE PRINTER
MULTIPLEXER SOFTWARE
Q-300
210907-001
Ap·153
PL/M-B6 COMPILER
MAlj~f'IUn
SERIES-Ill PL/M-86 VI 0 CoMPILAIIUN OF MODULE MAINMoD
OB.!ECT MODULE PLACED IN FI MAIN DB.!
COMPILER INVO~ED BY
PLM86 86 FI MAIN SRC
.
..
/**********~****************************************** ***********************
*
MAIN MODULE FOR THE LINE PRINTER MULTIPLEXER
*
************.***************************************** **********************1
*
$DEBUG
MAIN$MOD DO,
1***************************************************** ***********************
*
*
•
..
PORT I BIT CGNFIGURATION
BUFFER FULL
B7
..
ADDRESS
B5 B4 B3
CTS
B6
RTS
B2
TWO WIRE HANDSHA~E
BI BO
..
..
**~*************************************************** ***********************1
2
LITERALLY
LIT
LIT
LIT
'LITERALLY',
'OFFH',
'0',
'WHILE J ' ,
CMD$I
CMD$2
CMD$3
MODE
PORT$I$CTRL
SET$INT
INT$EN
RST$INT
INT$ADDR
TX$BUFF
RxnUFF
PORT$I
PORT$2
DEBOUNCESTIMER
SCANSTIMER
RECEIVE$TIMER
STATUSSREG
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
'0',
'2',
'4',
LIT
'lAW,
'ICH' ,
'lEW,
SCAN$INT
DEBOUNCESINT
RECEIVERSINT
TIMESOUTSINT
TRANSMITSINT
LIT
LIT
LIT
LIT
LIT
'40H',
'OtH' ,
'lOW,
'OSH',
'20H' ,
EMPTY
INUSE
FULL
LIT
LIT
LIT
'0',
'I',
'2',
LIT
'( INPUT(PORTSI) AND 04H) "
DECLARE LIT
TRUE
FALSE
FOREVER
RTS
1*8256 REGISTERS<-I
'6',
'S',
'OAH',
'OAH',
'OCW,
'OCW,
'OEH',
'OEH',
'IOH' ,
'12W,
'14H' '
./
6-301
210907·001
Ap·153
PL/M-B6 COMPILER
MAINMOO
BEGIN
LABEL
PUBLIC,
TEMP
BYTE
SCANS DELAY
BYTE
OEBOUNCESDE.LAY BYTE
RECEIVESDELAY
BYTE
PORTSPTR
BYTE
SERIALSFORMAT(8)BYTE
MESSAGESPTR
PUBLIC,
PUBLIC,
PUBLIC,
PUBLIC,
PUBLIC,
POINTER
BYTE
BYTE
BYTE
,J
OK( I)
llUFFERSSTATUS
1* PEN EP LI LO 133 B2 Bl BO *1
EXTERNAL,
EXTERNAL.,
EXTERNAL,
EXTERNAL,
1******************************)********************** *****************
*
*
EXTERNAL PROCEDURE DECLARATIONS
*********************************************************************1
3
4
2
5
6
:2
1
1
POWERSON PROCEDURE EXTERNAL;
END POWERSON,
'
LOADSINTSTABLE, PROCEDURE EXTERNAL,
END'LOADSINTSTABLE;
1*********************************************************************
*
SET THE BIT RATE AND DATA FORMAT FOR THE SERIAL PORT
*
*********************************************************************/
7
B
9
10
11
1
2
2
2
2
CONFIGURE:PROCEDURE , I*Initialize b,t rate and data format*1
TEMP=SERIALSFORMATCSHRCPORTSPTR, 3»;
OUTPUTCCMDSI)=«SHLCTEMP,2) AND OCOH) OR 03H),
OUTPUTCCMDS2)=CTEMP OR 30H);
END CONFIGURE,
1*********************************************************************
*
INITIALIZE SERIAL RECEIVER
*
*********************************************************************1
12
13
14
15
16
17
18
1
2
2
2
2
2
2
19
2
20
21
2
3
INITSRECEIVER
PROCEDURE,
CALL CONFIGURE,
I*Initiallze 8256 se~lal port*1
RECEIVESDELAY=TRUE,
OUTPUTCCMDS3)=OGOH,
I*Enable serIal receiver*1 '
OUTPUTCRECEIVESTIMER)=70,
1*18 second TIMESOUT*I
OUTPUTCSETSINT)=18H,
I*Enable RECEIVER and TIMESOUT lnterrupts*1
IF CBUFFER$STATUS~>FULL)
THEN
OUTPUTCPORTSI)=CINPUTCPORTSI) AND OBFH), I*Send CTS TRUE*I
00 WHILE RECEIVE$DELAY=TRUE.
1* After 18 seconds
22
23
24
25
2
2
2
2
1* Walt here wh1le recelvlng
serl~l
data *1
END,
OUTPUT(SETSINT)=TRANSMI1SINT,
-J=O,
o~
not recelvlng a
charar.te~,
proceed *1
1* Send the termlnatlng message *1
'
MESSAGESPTR= @OKCO);
CAUSES INTERRUPT (45H),
6-302
210907·001
inter
Ap·153
PL/M-86 COMPILER
26
27
28
29
2
2
2
2
MA)NMOD
OUTPUT(PORT$I)=(INPU1(PORT$I) DR 40H), I*Send CTS FALSE*I
OUTPUT(RS1$INT)=18H,
I*Clear RECEIVER and TIMER Interrupts*1
OUTPUT(CMD$3)=40H,
I*Dlsabl@ serial recelver*1
E~D INIT$RECEIVER,
1*********************************************************************
*
DEB OUNCE RTS
*
*********************************************************************1
30
31
32
33
34
35
36
38
1
2
2
2
2
3
2
2
DEB OUNCE PROCEDURE,
DEBOUNCE$DELAY=TRUE,
OUTPUT 0
THEN OUTPUT(TXSBUFF)-I.
ELSE OUTPUTCRSTSINT)=TRANSMITSINT.
J=J+l,
OUTPUT(CMDS3l=88H,
END T)(D.
END INTSMOD,
MODULE INFORMATION
CODE AREA SIZE
CONSTANT AREA SIZE
VARIABLE AREA SIZE
MAXIMUM STACK SIZE
181 LINES REAO
o PROGRAM WARNINGS
o PROGRAM ERRORS
E~O
'. 01BDH
= 0078H
= 0003H
= 0022H .
44'50
1200
30
340
OF PL/M-86 COMPILATION
6-306
210907'()()1
Ap·153
PL/M-Sb COMPILER
BUFFMOD
SERIES-III PL/M-Sb VI 0 COMPILATION OF MODULE BUFFMOD
OB')ECT MODULE PLACED IN FI BUFF OB')
COMPILER INVOKED BY
PLMSb Sb 'FI BUFF SRC
,
1*********************************************************************
*
*
*
*
*
BUFFER MODULE'
*
INSERTS AND REMOVES CHARACTERS FROM FIFO
REPORTS SERIAL RECEIVE ERRORS AND
RE-PROGRAMS SERIAL PORTS
*
*
*
*******************************************.*************************1
*
$DEBUG
BUFF$MOD'DO,
$NOLIST
DECLARE
3
MESSAGE$PTR
POINTER
BYTE
,)
OK(I)
BYTE
BREAK(I)
BYTE
PARITY(I)
BYTE
FRAME(I)
BYTE
OVER$RUN(I)
BYTE
SERIAL$FORMAT(I)BYTE
BYTE
PORT$PTR
PUBLIC,
PUBLIC,
EXTERNAL,
EXTERNAL,
EXTERNAL,
EXTERNAL,
EXTERNAL,
EXTERNAL,
EXTERNAL,
FIFO(SI92)
IN$POINTER
OUUPOINTER
BUFFER$STATUS
PUBLIC,
PUBLIC,
PUBLIC,
BYTE,
WORD
WORD
BYTE
1***************************************************** ****************.
*
*
INSERT CHARACTER INTO FIFO
*********************************************************************1
4
5
7
S
9
I
:2
10
:2
3
3
3
11
3
12
13
:2
:2
14
BUFF$IN,PROCEDURE (CHAR) PUBLIC,
DECLARE
CHAR
BYTE,
IF «BUFFER$STATUS=EMPTY) AND «CHAR=LF) OR (CHAR-CR»)
THEN
DO;
OUTPUT(SET$INT)=HANDSHAKE$INT, 1* Enable two-Wlre handshake interrupt *1
BUFFER$STATUS=INUSE,
OUTPUT(PORT$2)=O,
1* Output NULL character to get
the lnterrupt started *1
END,
FIFOCIN$POINTER)=CHAR,'
IN$POINTER~«WPOINTERH)
1* Put CHAR lnto FIFO and
lncrpmpnt pOinter I'
AND IFFFH),'
IF «((IN1iPOINTER+4) AND lFFFH):,.OUT$.,OnJ1ER)
1*
If thi" bttfft-'r'
1'.
fljll.
'itop
l'el.t:'ptlOrl
THEN
15
DO.
1* Send CTS FALSE.
cHld
11qht up buffer-full ltl)
6-307
It,'
210907·001
ft
inter
AP·t53
FL/M-B6 COMPILER
16
17
IB
19
,:3
3
3
0
THEN
GO TO DONE,
29
CALL OPEN( AFTSIN •. FILENAME. 1. O.
30
IF STATUS <> 0
THEN
GO TO DONE;
31
32
FILENAME. 15.
ACTUAL.
STATUS).
STATUS').
34
1* Open up the file *1
REPEAT'
CALL READ(AFTSIN •. BUFFER.32000 •. ACTUAL.
33
1* R""d in f i h and path name *1
STATUS),
IF STATUS <> 0
THEN
GO TO DONE.
r- CHAR_COUNT keeps
35
CHAR$COUNT-O,
36
OUTPUT(USARTSSTATUS)= RTS.OR TXEN.
t~ack
of the tab columns
In
each lIne *1
210907-:'IFH AND BUFFER(I}':: 7FH)
THEN
69
69
70
71
72
2
1* Only lncrement CHARSCOUNT
for printable characters *1
CHARSCOUNT=CHARSCoUNT+!,
IF' ( (BUFFI?R ( j ) =CR} OR (BUFFER ( J) =LF} }
THEN
1* Ro.et CHARSCOUNT for CR or LF *1
CHAR$CoUNT=O,
END,
END,
IF ACTUAL = 32000 1*1 f
th e f 11 e
1
s more than :J2K.
get some more data *1
THEN
GO TO REPEAT,
CALL TXRDY,
1* Termln,ate File With CR,
LF,
and FF *1
OUTPUT(USART$DATA)=CR,
CALL TXRDY,
6-315
210907-001
Ap·153
PL/M-80 COMPILER
73
74
75
OUTPUT (USAR T$DA 1 A) =LF;
CALL TXRDY,
OUTPUT (USART$DATA)=FORM$FEED,
76
OUTPUT(USART$STATUSl=RXE OR TXEN;
77
CALL CLOSE (AFT$IN, STATUS);
78
79
1
2
80
81
82
2
83
1* Shut oFF RTS *1
",*
DO 1=0 TO 'i4;
IF FILENAME(I)=CR
THEN
GO TO SKIP,
BYE(I+S)=FILENAME(I),
END;
2
2
SKIP'
84
CALL WRITE(0"BYE,42,
Output slgn off message *1
STATUS);
GO TO NEXT;
85
DONE:
86
NEXT:
87
END WRITE$MOD;
CALL ERROR (STATUS) ,
CALL EXIT.
MODULE INFORMATION:
CODE AREA SIZE
= 0209H
VARIABLE AREA SIZE
7D44H
MAXIMUM STACK SIZE = 0008H
191 LINES READ
o PROGRAM ERRORS
521D
32068D
80
END OF PL/M-80 COMPILATION
6-316
210007-()01
AP·153
APPENDIX C
MUART REGISTERS
6..;317
21090Hl01
Ap·153
I
8085 Mode: AD3
8086 Mode: AD4
AD2
AD3
AD!
AD2
ADO
Ant
0000
~---
Timer Frequency Select
8086 Mode Enable
Interrupt on Bit Change
Break-in Detect Enable c
Stop Bit Length
Character Bit Length
0001
' - - - - - - Baud Rate Select
' - - - - - - - - - - - - - System Clock Divider
Even Parity
' - - - - - - - - - - - - - - - - - - Parity Enable
0010
I SET .. 1RxE I IAE I NIE IEND ISBRKtrBRK I RST I
I
Command 3
L
I I
0011
Software Reset
Transmit Break
Single Character Break
End of Interrupt
.
Nested Interrupt Enable
Interrupt Acknowledge Enable
Receiver Enable
Bit Set/Reset
I T35 I T24 I T5C I CT3 I CT2 IP2C21p2Cli P2CO I
Mode
f
I
l
i
J
'-1 _ _-
~----------
'-------------'---------------'------------------
6-318
Port 2 Control
Counter/Timer 2
Counter/Timer 3
Timer 5 Retriggerable
Cascade Counter/Timer 2 & 4
Cascade Counter/Timer 3 & 5
210907-001
Ap·153
0100
' - - - - - - - - - - - - Output/Input of Port 1 pins
(Write only)
0101
L7
L6
I L5 I LA I L3 I L2 I Ll I LO I
Enable
Set Interrupts
(Write only)
OlIO
L7
L6
I L5 I LA I L3 I L2
Ll
I LO I
Disable
LI
I LO I
Interrupt Levels Enabled
Reset Interrupts
(Read only)
0101
L7
L6
I L5 I LA I L3 I L21
Interrupt Enable
(Read only)
0110
'---t==-______
Interrupt Level in Service
(Write only)
1111
Disable Start Bit Check
' - - - - - Transmit Mode Enable
Receiver Sampling Point
L....._ _ _ _ _ _ _ _ _ _
6-319
210907·001
,inter
Ap·153
Status Register
1111
(Read only)
I
I
I
lINT RBF TBE TRE
I BD I PE I OE I FE I
I
Framing Error/Transmission Mode
Indication '
Overrun Error
Parity Error
Break Detect or Break-in Detect
Transmitter Register ,Empty
Transmitter Buffer Empty
Receiver Buffer Full
Interrupt Pending
,
Response to INTA
B085-Mode (RST-instruction in response to INTA)
D5
I
D4
I D3,
1..-_ _ _ _ _ _ _ _ _ _
8086-Mode (Interrupt Vector in response to
o
o
o
o
secon~
Interrupt Level
INTA)
021DlIDOI
' - - - - - Interrupt Level
6-320
210907'()()1
8231 A
ARITHMETIC PROCESSING UNIT
Compatible with all Intel and most
• other
Microprocessor Families
Direct
Memory Access or
• Programmed
110 Data Transfers
End
of
Execution
Signal
•
PurposeS·Blt Data Bus
• General
Interface
24 Pin Package
• Standard
+ 12 Volt and + 5 Volt Power
• Supplies
N·Channel Silicon Gate
• Advanced
HMOS Technology
Fixed Point Single and Double .
• Precision
(16/32 Bit)
Floating
Point
Single Precision
• (32 Bit)
Binary Data Formats
• Add,
Subtract, Multiply and Divide
• Trigonometric
Inverse
• Trigonometric and
Functions
Roots, Logarithms,
• Square
Exponentiation
Float to Fixed and Fixed to Float
• Conversions
• Stack Oriented Operand Storage
The Intell!> 8231 A Arithmetic Prpcessing Unit (APU) is a monolithic HMOS LSI device that provides high performance fixed
and floating point arithmetic and floating pOint trigonometric operations. It may be used to enhance the mathematical
capability of a wide variety of processor-oriented systems. Chebyshev polynomials are used in the implementation of the
APU algorithms.
All transfers, including operand, result, status and command information, take place over an 8-bit bidirectional data bus.
Operands are pushed onto an internal stack and commands are issued to perform operations on the data in the stack.
Results are then available to be retrieved from the stack.
Transfers to and from the APU may be handled by the associated processor using conventional programmed 1/0, or may be
handled by a direct memory access controller for improved performance. Upon completion of each command, the APU
issues an end of execution signal that may be used as an interrupt by the.CPU to help coordinate program execution.
Figure 2. Pin Configuration
Figure 1. Block Diagram .
6-321
intJ
8231A
Table 1. Pin Des,crlption
Pin
Symbol No.
I'
Name and Function
~pe
Vee
2
Power: +5 VCllt power supply,
Voo
16
Vss
CLK
1
23
I
Clock: An external,' TTL compatible,
timing source is applied to the CLK pin.
RESET
22
I
Reset: The active high reset signal provides initialization' for the chip, RESET
also tllrminates, any operation in progress.RESET clears the status register
and places the 8231A into the idle state.
Stack contents and command registers
are not affected (5 clock cycles). '
SVREQ
5
0
READY ,1,7
0
DBODB7
I/O
Power: +12 Volt pOIYer supply.
Ground.
CS
18
I
Chip Select: CS is an active low input
signal which selects the 8231A and enables communication with the data bus.
Ao
21
I
Address:' In' conjunction with the m5
and WR signals; the Ari control, line establishes the type of communication
that is to be performed with the 8231 A as
shown below:
Ao
RD
WR
Function
0
0
1
1
1
0
1
0
0
1
0
1
Enter data byte into stack
Read data byte from stack
Enter command ,
Read status
20
I
.
Read: This active low input indicates
that data or status is to be read from the
8231A if CS is low.
WR
19
I
Write: This active low input indicates
that data or a command is to be written
into the 8231A if CS is low.
EACK
3
I
End of Execution: This active low input
clears the end of execution output signal (8iiD). If EACK is tied low, the END
output will be a pulse that is one clock
period wide.
SVACK
4
I
Service Request: This active low input
clears the service request output
(SVREQ).
24
0
End: This active low, open-drain output
indicates that execution of the previously entered command is complete. It
can be used as' an interrupt request and
is cleared by EACK, RESET or any read
or write access to the 8231.
815
Name and Function
Service Req\leat: This acti~e hJ,gh output signal il1d,icates that command
execution is 'complete and that' post
execution service .."as requested in the
previous command byte. It is cleared by
SVACK, the next command output'to the
devic$, or by RESET.
Ready: This active high output Indicates that the 8231A is able to accept
communication with the data bus. When
an attempt is made to read 'data, write
data or to enter a new command while
the 8231A Is' executing a command,
READY goes low until executi,on of the
current command Is complete (See
READY Operation" p. 5).
Data Bus: These eight bidirectional
lines provide for transfer of commands,
status and data between the 8231A and
theCPU.,The '8231A can drive the data
bU~ only when CS and RD are low.
COMMAND STRUCTURE
,
RD
ENE)
Pin
Symbol No. ~pe
Each command entered I nto the 8231 A consists of a 51 ngle
B-bit byte having the format illustrated below:
,
Bits 0·4 select the operation to be performed as shown
in the table. Bits 5·6 select the data format appropriate
to the selected operation. If bit 5 is a 1, a fixed point data
format is specified. If bit 5 is a 0, floating point format is
specified. Bit 6 selects the precision of the data to be
operated upon by fixed pOint commands only (if bit
5 = 0, bit 6 must be 0). If bit 6 is a 1, single'precision
(16·bit) operands are assumed. If bit 6 is a 0, double·
precision (32·bit) operands are indicated. Results are
undefined for all illegal combinations of bits in the com·
mand byte. Bit 7 indicates whether a service request is
to be issued after the command is executed. If bit 7 is a
1, the service request output (SVREQ) will go high at the
conclusion of the command and will remain high until
reset by a low level on the service acknowledge pin
(SVACK) or until completion of execution of the suc·
ceeding command where service request (bit 7) is O.
Each command issued to the 8231A requests post execution service based upon the state of bit 7 in the command
byte. When bit 7 is a 0, SVREQ remains low.
6-322
AFN'()1251B '
inter
8231A
Table 2. 32·81t Floating Point Instructions
Description
Inslrucllon
ACOS
Inverse Cosine of A
ASIN
Inverse Sine of A
ATAN
Slick (:onlenls(2)
After Execullon
A B C D
Hex(1)
Code
Slllus FIIgS(4)
Allecled
6
R U
U
U
S, Z, E
R U
U
U
S, Z, E
Inverse Tangent of A
5
0 7
R
B
U
U
S, Z
CHSF
Sign Change of A
t 5
R
B
C
0
S, Z
COS
Cosine of A (radians)
0
3
R
B
U
U
S, Z
EXP
ell Function
0
A
R
B
U
U
S, Z, E
FADD
Add A and B
t 0
R C
0
U
S, Z, E
0
,0
FDIV
Divide B by A
1 3
R
C
D
U
S, Z, E
FLTD
32·BIt Integer to Floating Point Conversion
1
C
R
B
C
U
S, Z
FLTS
16·Bit Integer to Floating POint Conversion
1
0
R
B
C
U
S, Z
FMUL
Multiply A and B
1
2
R C
0
U
5, Z, E
FSUB
Subtract A from B
1
1
R C
0
U
S, Z, E
LOG
Common Logarithm (base 10) of A
0
8
R
B
U
U
S, Z, E
S, Z, E
LN
Natural Logarithm of A
0
9
R
B
U
U
POPF
Stack Pop
1
B
B
C
0
A
S, Z
PTOF
Stack Push
1
7
A
A
B
C
S,Z
PUPI
Push n onto Stack
1
A
R A
B
C
S, Z
PWR
sA Power Function
0
B
R C
U
U
S, Z, E
SIN
Sine of A (radians)
0
2
R
B
U
U
S, Z
SORT
Square Root of A
0
1
R
B
C
U
S, Z, E
TAN
Tangent of A (radians)
0
4
R
B
U
U
S, Z, E
XCHF
Exchange A and B
1 9
B
A
C
0
S,Z
Table 3. 32·81t Integer Instructions
De.crlpllon
Instruction
Stack Contents(2)
Aller Execullon
A 8 C D
Hex(1)
, Code
Sialus Flags(4)
Allecled
CHSD
SIgn Change of A
3
4
R
B
C
0
S,Z,O
DADO
Add A and B
2 C
R
C
0
A
S, Z, C, E
DDIV
Divide B by A
2
F
R C
0
U
S, Z, E
DMUL
Multiply A and B (R
2
E
R C
0
U
S,Z,O
DMUU
=lower 32·bits)
Multiply A and B (R =upper 32·bits)
3
6
R C
S,Z,O
Subtract A from B
2
0
R C
0
0
U
DSUB
A
S,Z, C, 0
FIXD
Floating Point to Integer Conversion
1
E
R
B
C
U
S,Z,O
,
POPD
Stack Pop
3
8
B
C
0
A
S, Z
PTOD
Stack Push
3
7
A
A
B
C
S, Z
XCHD
Exchange A and B
3
9
B
A
C
0
S,Z
Table 4. 16-8it Integer Instructions
Inslructlon
Descrlpllon
)
Hex(1)
Code
Slack Conlenl.(3)
After Execullon
Au AL Bu BL Cu CL Du DL
Stalus Flags(4)
Allecled
CHSS
Change Sign of Au
7
4
R AL Bu BL Cu CL Du DL
FIXS
Floating Poont to Integer ConversIon
I
F
R Bu BL C u CL U
POPS
Stack Pop
7
S, Z
Stack Push
7
8
7
AL Bu BL Cu CL Du DL Au
PTOS
Au Au AL Bu BL Cu CL Du
S, Z
SADD
Add Au and AL
6
C
R Bu BL Cu CL Du DL Au
S, Z, C, E
501 V
Divide AL by Au
6
F
R Bu BL Cu CL Du DL U
S, Z, E
SMUL
Multiply AL by Au (R
6
E
R Bu BL Cu CL Du DL U
S, Z, E
SMUU
Multiply AL by Au (R - upper 16·bits)
7 6
R Bu BL Cu CL Du DL U
S, Z, E
SSUB
Subtract Au from AL
6
0
R Bu BL Cu CL Du DL Au
S, Z, C, E
XCHS
Exchange Au and AL
7
9
AL Au Bu BL Cu CL· Du DL
S, Z
NOP
No Operation
0
0
Au AL Bu BL Cu CL Du DL
=lower 16'blts)
U
U
S, Z, 0
S,Z,O
Note•• 1. In the hex code column, SVREQ IS a O.
2. The stack initially is composed of four 32·bil numbers (A, B, C, D). A is eqUIvalent to Top Of Staak (TOS) and B IS Next On Stack (NOS). Upon
completion of a command the stack IS composed of: the result (R); undefined (U), or the initial contents (A, B, C, or D).
3. The stack initially Is composed Of eight 16·bit n~mbers (Au, AL, Bu, BL, Cu , C lo Du , DU' Au is the TOS and AL is NOS. Upon completion of a
command the stack is composed of: the result (R); undefined (U); or the initial contents (Au, AL, Bu, BL, ... ).
4. Nomenclature: Sign (S); Zero (Z); Overflow (0); Carry (C); Error Code Field (E).
6-323
AFN~01251B
intJ
8231 A
DATA FORMATS
The 6231 A arithmetic processing unit handles operands
In -both fixed point and floating -point formats. Fixed
point oparands may be represented in either single
(16-bit operands) or double precision (32-blt operands),
and are always represented as binary, two's complement values.
.
SINGLE PRECISION FIXED POINT FORMAT
I
~
I
I
.
VALUE
-I II I I-I I I I I I I I I I
DOUBLE PRECISION FIXED POINT FORMAT
~
The sign (positive or negative) of the operand is located
in the most significant bit (MSB). Positive values are
represented by a sign bit of zero (S 0). Negative values
are represented by the two's complement of the corresponding positive value with a sign bit equal to 1 (S 1).
The range of values that may be accommodated by each
of these formats is - 32,768 to +' 32,767 for single preciSion and -2,147,483,648 to +2,147,483,647 for double
precision.
'
=
=
Floatini;l'point biliary values are represented in a format
'that permit's arithmetic to be performed in a fashion
analogous to operations with decimal values expressed
in scientific notation.
"
. The 8231A is a binary arithmet1c processor and requires
that floating pOint data be represented ·by a fractional
mantissa value between .5 and 1 multiplied by 2 raised
to an appropriate power. This is expressed as follows:
value = mantissa, x
2e~ponent
For example, the value 100.5 expressed in this form Is
0.1100' 1001 x 27. The decimal equl,valent of this value
may be computed by s~mmlng the components (powers
of two) of the mantissa and then multiplying by the exponent as shown below:
value = (2- 1 + 2- 2 + 2- 5 + 2- S)x 27
0.5 + 0,25 + 0:03125 + 0:00290625) x 128
0.78515625 x 128
100.5
=
=
=
I
.
-VALUE
·1 I I I I I I I 1'1 I I I I I I I I I I I I I I I I I I I I I
,
1,1',
FLOATING POINT FORMAT
The format for floating point values in the 8231A is given
below. The mantissa Is expressed as a 24-bit (fractional)
value; the exponent Is expressed as a two's comple,ment
7-blt value having a range of -64 to +163. The most
significant bit Is the "ign of the mantissa (0 = positive,
1 = negative), for a total of 32 bits. The binary point is
assumed to be to the left of the most significant mantissa bit (bit 23). All floating point data values must be
normalized. Bit 23 must be equal to 1, except for the
value zero, ,which is represented by ali zeros.
I
I
EXPONENT
~I~I
MANT'SSA
I I I I I I I I I II I I I I I II I II I I I I I I I
3130
2423
I
0
The range of values that can be represented in this format is ± (2.7 x 10- 20 to 9.2 x lO'S) and zero.
In the decimal system, data may be expressed as values
between 0 and 10 times 10 raised to a power that effectively shifts the Implied decimal pOint right or left the
number of places necessary to express the result in conventional form (e.g., 47,572.8). The value-portion of the
data is called the mantissa The exponent may be either
negative or positive. '
The concept of floating point notation has both a gain
and a loss associated with it. The gair:J is the ability to
represent the significant digits of data with values spanning a large dynamic range limited only by the capacity
. of the exponent field. For example, in decimal notation
if the exponent field is two digits wide, and the mantissa
is five digits, a range of values (positive or negative)
from 1.0000 x 10- 99 to\ 9.9999 x 10+ 99 can be accommodated. The loss is that only the significant digits of
the value can be represented. Thus there is no distinction in this representation between the values 123451
and 123452, for example, since 'each would be expressed as: 1.2345 x 105. The sixth digit' has been
discarded. In most applic/itions where the dynamic
.' range of values to be represented is large, the loss of
significance, and hence accuracy of results, is a minor
consideration. For greater precision a fixed point format
could be chosen, although with a loss of potential
, dynamic range.
.
FUNCTIONAL DESCRIPTION
STACK CONTROL
The user interface to the 8231A in'eludes access to an 8
level 16-bit wide data stack. Since Single precision fixed
'" point operands are 16-bits in length, eight such values
may be maintained In the stack. When using double
precision fixed point or floating point formats four
values may be store'd. The stack in these two cenfigurations can be visualized as shqwn below:
TOS
NOS
--
A2
82
A'
B'
T05-
A4
A3
NOS
B4
as
A2
82
A.
B.
-32-
-18-'
Data are written onto the stack, eight bits at a'time, In
the order shown (A 1, A2, A3, ...). Data are removed from
the stack in reverse byte order (A4, A3, A? ..). 'oata
should be entered onto the stack in multiples of the
number of bytes appropriate to the chosen data format.
"
6-324
. '
A~'()'251B
i.nter
8231 A
\ DATA ENTRY
4. The 8231A is not busy, and a data entry has been requested. READY will be pulled low for the length of
time required to ascertain If the preceding data byte,
if any, has been written to the stack. If so READY will
Immediately go high. If not, READY will remain low
until the Interface latch Is free and will then go high.
5. When a status read has been requested, READY will
be pulled low for the length of time necessary to
transfer the status to the Interface latch, and will
then be raised to permit completion of the status
read. Status may b.e read whether or not the 8231A is
busy.
Data entry is accomplished by bringing the chip select
(CS), the command/data line (Ao), and WR low, as shown
in the timing diagram. The entry of each new data word
"pushes down" the previously entered data and places
the new byte on the top of stack (TOS). Data on the bottom of the stack prior to a stack entry are lost.
DATA REMOVAL
Data are removed' from the stack in the 8231 A by bringing
chip select (CS), command/data (Ao), and An low as
shown in the timing diagram. The removal of each data
word redefines TOS so that the next successive byte to
be removed becomes TOS. Data removed from the stack
rotates to the bottom of the stack.
When READY goes. low, the APU expects the bus control signals present at the time to remain stable until
READY goes high.
COMMAND ENTRY
DEVICE STATUS
After the appropriate number of bytes of data have been
entered onto the stack, a command may be issued to
perform an operation on that data. Commands which require two operands for execution (e.g., add) operate on
the TOS and NOS values. Single operand commands
operate only on the TOS.
Device status Is provided by means of an internal status
register whose format is shown below:
I
BUSY
Commands are issued to the 8231A by bringing the chip
select (CS) line low, command data (Ao)lIne high, and
WR line low as indicated by the timing diagram. After a
command is issued, the CPU can continue execution of
its program concurrently with the 8231A command
execution.
I
SIGN
I
ZERO
tJ
I
ERROR CODE
--I I
-I
CARRY
BUSY: Indicates that 8231A is currently executing a command (1 =Busy)
SIGN: Indicates that i'he value on the top of stack is
negative (1 = Negative)
ZERO: Indicates that· the value on the top of stack Is
zero (1 =Value is zero)
. ERROR CODE: This field contains an indication of the
validity of the result of the last operation. The error codes are:
0000 - No error
1000 - Divide by zero
0100 - Square root or log of negative number
1100 - Argument of inverse sine, cosine, or
eX too large
XX10 - Underflow
XX01 - Overflow
CARRY: Previous operation resulted in carry or borrow
from most significant bit. (1 =Carry/Borrow,
0= NoGarry/No Borrow.)
COMMAND COMPLETION
The 8231 A signals the completion of each command execution by lowering the End Execution line (END).
Simultaneously, the busy bit in the status register Is
cleared and the Service Request bit of the command
register is checked. If it is a "1" the service request output level (SVREQ) is raised. END is cleared on receipt of
an active low End Acknowledge (EACK) pulse. Similarly,
the service request line is cleared by recognition of an
active low Service Acknowledge (SVACK) pulse.
READY OPERATION
An active high ready (READY) is provided. This line is
high in its quiescent state and is pulled low by the 8231A
under the following conditions:
1. A previously initiated operation is in progress (device
busy) and Command Entry has been attempted. In
this case, the READY line will be pulled low and remain low until completion of the current command
execution. It will then go high, permitting entry of the
new command.
2. A previously initiated operation is in progress and
stack access has been attempted. In this case, the
READY line will be pulled low, will remain In that
state until execution is complete, and will then be
raised to permit completion of the stack access.
3. The 8231A is not busy, and data removal has been requested. READY will be pulled low for the length of
time necessary to transfer the byte from the top of
stack to the interface latch, and will then go high,
indicating availability of the data.
If the BUSY bit in the status register is a one, the other
status bits are not defined; if zero, indicating not busy,
the operation is complete and the other status bits are
defined as given above.
READ STATUS
The 8231 A status register can be read by the CPU at any
time (whether an operation is in progress or not) by
bringing the chip select (CS) low, the command/data line
(Ao) high, and lowering RD. The status register is then
gated onto the data bus and may be input by the CPU.
EXECUTION TIMES
Timing for execution of the 8231A command set is contained below. All times are given in terms of clock
cycles. Where substantial variation of execution times
6-325
AFN-01251B
8231A
is possible, the minimum and maximum values are
qljoted; otherwise, typical values are given. Variations
are data dEl pendent.
Total ,execution times may require allowances for
operand transfer into the APU, command exeCution; and
result retrieval from the APU.Except for command exe·
cution, these times will be heavily influenced by the
nature of the data, the control interface used, the speed
of memory, the CPU used, the priority allotted to DMA
and Interrupt operations, the size and number of
operands to be transferred', and the use of chained
calcuiations, etc.
Table 5. Command Execution Times
Command
Mnemonic
SADD
SSUB
SMUL
SMUU
SDIV
DADD
DSUB
DMUL
DMUU
DOIV
• FIXS
FIXD
FLTS
FLTO
Clock
' Cycles
17
30
84·94
80·98
84·94
21
38
194·210
182·218
208
92·216
100·346
98·186
98·378
Command
Mnemonic
Clock
Cycles
Command
Mnemonic
Clock
Cycles
Command
Mnemonic
Clock
Cycles
FADD
FSUB
FMUL
54·368
70·370
146·1fl8
LN
EXP
PWR
4298·6956
3794·4878
8290·12032
POPF
XCHS
XCHD,
12
18
26
FDIV
SORT
SIN
COS
154·184
800
4464
4118
NOP
CHSS
CHSD
CHSF
4
23
27
18
XCHF
PUPI
26
16
TAN
ASIN
ACOS
ATAN
LOG
5754
7668
7734
6006
4474·7132
PTOS
PTOD
PTOF
POPS
PO PO
16
20
20
10
12
DERIVED FUNCTION DISCUSSION
Computer approximations of transcendental functions
are ofterr based on some form of polynomial equation,
such as:
'
In general, the next term in the Chebyshev series can be
re?ursively derived from the previous term as follows:
(1·7)
(1·1)
The primary shortcoming of an approximation in this
form is that it typically exhibits ttery large errors when
the magnitude of IXI is large, although the errors are
small when IXI is small. With polynomials in !hi,s form,
the error distribution is markedly uneven' over any
'
arbitrary interval.
Common I'ogarithms are computed by multiplication
of the natural logarithm by the conversion factor
0.43429448 and the error function is therefore the same
as that for natural logarithm. The power function is
realized by combination of natural log and exponential
functions according to the equation:
A set of approximating functions exists that not only
minimizes the maximum error but also provides an even
distribution of errors within the selected data represen·
tation interval. These are known as Chebyshev Poly·
nomials and are are based upon cosine functions. These
functions are defined as follows:
The error for the power function is a combination of that
for the logarithm and exponential functions.
Tn(Xl = Cos nO; where n = 0,1,2 ...
O=COS-1X
Each of the derived functions is an approximation of the
true function. Thus the result of a derived function will
have an error. The absolute error is the difference be·
tween the function's result and the true result. A more
useful measure of the function's error is relative er'ror
(absolute errorltrue result). This gives a measurement of
the significant digits of algorithm accuracy. For the
derived functions except LN, LOG, and PWR the relative
error is typically 4 x 10 -7. For PWR the relative error is
the summation of'the EXP
TEST POINTS
0.45
Unit
0.8
'.
A.C. TESTING l.OAD CIRCUIT
-x=
<,
DEVICE
UNDER
TEST
0.8
l
lc.-'~PF·
,
A.C. TESTING' INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC "'" AND O.45V FOR A
LOGIC ''O,n TiMING MEASUREMENTS ARE MAoe AT 2.2V FOR A LOGIC "1" AND
OJV FOR A LOGIC O.
• .•
• •
.
c.lNOWOES JIG CAPACIT!,NCE
. 6-340
..
", '
inter
825318253·5
WAVEFORMS
WRITE TIMING
Ao-l,C8_ _,.,.._ _ _ _ _ _ _+..,..,_~_
DATA BUS
----------~~~--+---~~---
.CLOCK AND GATE TIMING
REAOTIMING
:
/,'
','\
.
8254
PROGRAMMABLE INTERVAL TIMER
ill Compatible with Most Mlcr~
• Three Independent 16·blt Counters
processors Including 8080A,' 8085A,
IAPX 88 and IAPX 88
.Bln~ry
• Handles Inputs from DC to 8 MHz
(10 MHz for 8254·2)
or BCD Counting
• Single +5V Supply
• Six Programmable Counter Modes
• Available In EXPRESS
-Standard Temperature Range
• Status Read·Back Command
The Intelill> 8254 is a counter/timer device designed to solve the common timing control problems in microcomputer system design. It pro)/ides three independent 16-bit counters. each capable of handling clock inputs up to,
:10 MHz. All modes are software programmable. The 8254 is a superset of the 8253.
;The 8254 uses HMOS technology and comes in a 24~pin plastic or CERDIP package.
CLK 0
o,·Do
GATEG
OUT 0
CLK 1
D.
GATE 1
OUT 1
CLK2
GATE 2
GATE 1
OUT 1
OUT2
Figure 1. 8254 Block Diagram
Figure 2. Pin Configuration
6-342 '
f
8254
Table 1. Pin Description
PinHo.
Type
H..... and FuncUan
DrDo
HI
UO
01118: BI-dlrectional three state data bus
lines, connected to system data bus.
ClKO
9
I
Clock 0: Clock Input of Counter O.
OUT 0
10
0
Output 0: Output 9f Counter O..
GATE 0
11
I
GND
12
Symbol
G_~
Symbol
WA'
Pin No.
Ty~
23
I
WrIte Control: This Input Is low during, CPU
write operations.
,
RD
22
I
Read Conlrol: This Input Is low during CPU
~ad operallons.
. CS
21
I
Chip Select: A low.on this Input enables the
.8254 ~o respond to Ri5 and WR Signals. AD
and· WR ere Ignored otherwise.
20-19
I
Addre••: Used to select one of the three
Counters or the Control Word Register for
read or write operations. Normally connected to the system address bus.
,
.
0: Gate Input of Counter O.
Ground: Power supply connection.
Name -(III FuncUan
Power: +5V power supply connection.
24
Vcc
A 1,Ao
Ao'
0
0
1
Counter 0
Counter 1
0
Counter 2
1
Control Word Register
0
"
1
I
FUNCTIONAL DESCRIPTION
Selects
A,
ClK2
18
I
Clock 2: Clock Input of Counter 2.
OUT 2
17
0
Oul 2: Output of Counter 2.
GATE 2
16
I
Gale 2: Gate Input of Counter 2.
ClK 1
15
I
Clock 1: Clock Input of Counter 1.
GATEI
14
I
Gale 1: Gate Input of Counter 1.
OUTI
13
0
Oull: Output
01 Counter. 1.
Block Diagram
DATA BUS BUFFER
General
This 3-state, bi-directionai, 8-bit buffer is used to interface the 8254 to the system bus (see Figure 3).
The 8254 is a programmable interval timer/counter designed lor use with Intel microcomputer systems. It is a
general purpose,. multi-timing element that can be treat~d
as an array 01 I/O ports in the system software.
CLKO
GATE 0
The 8254 solves oneol the most common problems in
any microcomputer system, the generation 01 accurate
time delays under software control. Instead 01 setting
up'liming loops In software, the programmer configures
the 8254 to match his requirements and prograrns one of
the counters for the desired OelaY. After. the desired
delay, the 82~ will interrupt the CPU. Software overhead is minimal and variable length delays can easily be
accommodated.
OUT 0
eLK 1
GATE 1
OUT 1
Some of the other counter/timer fUnctions common' to
microcomputers which can be implemented with the
8254 are:
Cl,K2
OUT 2
• Reat time clock
• Event counter
. Dlgit~1 one-shot
• Programmable rate generator
• Square wave generator
• Binary rate' multiplier
• Complex waveform generator
• Complex motor controller
Figure 3. Block Dlagr.am Showing Data Bus Buffer and
ReadlWrlte Logic Functions
6-343
AFN-00217D
READIWRITE LOGIC
,The ReadlWrite Logic accepts inpu~s frol'!J the system
bus and generates control signals for the other functional blocks o'f the 8254. Al and' Ao select one of the
thr~e counters or the Control Word Register to be read
from/written into. A "low" on the RD input tells the 8254
that the CPU is reading one of'the counters. ,A "low" on
the WR input tells the 8254 that the CPU is writing either
a Control Word or an:initialcount. Both' RD and WR are
qualified I:)y CS; AD and WR are ignored unless the 8254
has been selected by holding'CS low.
CONTfJPL WORD REGISTER
The Control Word Register (see Figure 4) is selected by
the ReadlWrite Logic when A1.Ao= 11. If the CPU then
does a write operation to the 8254, the data is stored in
the ContrElI Word Register and is interpreted as a' Control Word used to define the ope~ation of the Counters.
The Control Word Register can only be written to; status
information is available with the Head-Back Command.
Figure 5. Internal Block Diagram of a Counter
The status register, shown in the Figure, when latched,
contains the current contents of the Control Word
Register and status of the output and null count flag.
(See detailed explanation of the Read-Back command.),
The actual counter is labelled CE (for "Counting Eiement"). It is a 16-bit presettable synchronous down
counter.
OLM and OL l are two S-bit latches. OL stands for "Output Latch"; the subscripts M and L stand for "Most significant byte" and "Least significant byte" respectively.
Both are normally referred to as one unit and called just
OL. These latches nOrmally "follOw" the CE, 'but if a
suitable Counter Latch Command'is sent to the"8254,
the latches "latch" the present count until read by the
CPU and then return to "fOllowing" tiie CEo One latch at
a time is enabled by the countl!r's Control Logic to drive
the internal bus. This is how the 16-bit Counter communicates over the .8-bit internal bus. Note'that the ,CE
itself cannqtberead; whenever you read the count, it is
th~ .OL that ,is being read. '
The Counters are fully independent. Each Counter may
operate in a different Mode.
Similarly; there are two 8-b1t registers called CRM and
CRl (for "Count Register"). Both are normally referred to
as one unit and called juS! CR. When a new count is written to the Counter, the count is stored in theCR and
latertransferred tO,the CEo The Control Logic allows one
register at atim,e to ,be ,loaded hom the iniernal bus.
Both bytes are transferred to the CE simultaneously.
CRM and CRl are cleared when the Counter is programmed. In this way, if the Counter has be!'!,n pro;
grammed for one byte counts (either mpst ,~Ignific;;ant
byte only or least Significant byte only) the '!?therbyt!l
will be zero. Note that the CE ,c:;annot be written into;
whenever a count is written, it is, wti'tteninto the CR.
,The Control Word Register is shown, in the figure; it 'is
not part of the Counter itsell,"but its contents determine
how the Counter'operates;
The Control Logic is also shown' In the diagram. CLK n,
GATE n, and OUT n are all connected to the outside
world through the Control Logic,.
Figure 4_ Block Diagram Showing Control Word
Register and Counter Functions
.cOUNTER 0, COUNTER 1, COUNTER,2
Thesethree tunctional blocks are identical in operation,
so only a single Counter will be described. The internal
block diagram of a single counter is ~hown in Figure 5.
6-344
AFN-00217D
intJ
8254
8254 SYSTEM INTERFACE
OPERATIONAL DESCRIPTION
The 8254 is a component of the Intel Microcomputer Systems and interfaces in the same manner as all other peripherals of the family. It Is treated by the systems software
as an array of peripheral 110 ports; three are counters and
the fourth Is a control register for MODE programming.
Basically, the select inputs Ao, A1 connect to the Ao, A1
address bus signals of the CPU. The CS can be derived
directly from the address bus using a linear select method.
Or It can be connected to the output of a decoder, such as
an Intel 8205 for larger systems.
.
General
After power-up, the state of the 8254 Is undefined. The
Mode, count value, and output of all Counters are
undefined.
.
How each Counter operates is determined when It Is
programmed. Each Counter must be programmed
before It can be used. Unused counters need not be programmed.
Programming the 8254
Counters are programmed by writing a Control Word
and then an Initial count.
All Control Words are written Into the Control Word
Register, which Is selected when Al,Ao= 11. The Control Word Itself specifies which Counter Is being pro·
grammed.
By contrast, initial counts are written Into the Counters,
not the Control Word Register. The Al,Ao Inputs are
used to select the Counter to be written Into. The format
of the Initial count is determined by the Control Word
used.
Control Word Format
Figure 6. 8254 System Interface
Al,Ao=11 Cs=o
I SC1 I SCO I RW1 I RWO I M2
sc - Select Counter:
M1
MO
RD=1 'WR=O
I BCD I
M- MODE:
SCl
SCO
M2
Ml
MO
0
0
Select Counter 0
0
0
0
Mode 0
0
1
Select Counter 1
0
0
1
Mode 1
1
0
Select Counter. 2
X
1
0
Mode 2
1
1
Read-Back Command
(See Read. Operations)
X
1
1
Mode 3
1
0
0
Mode 4
1
0
1
ModeS
RW - ReadlWrlle:
. RWl RWO
0
0
Counter Latch Command (see Read
Operations)
0
1
ReadlWrite least significant byte only.
Binary Counter l6-bits
1
0
ReadlWrite most significant byte only.
1
1
ReadlWrite least significant byte first,
then most significant byte.
Binary Coded Decimal (BCD) Counter
(4 Decades)
BCD:
NOTE: DON'·T CARE BITS (Xl SHOULD BE 0 TO INSURE
COMPATJBILIT~ WITH FUTURE INTEL PRODUCTS.
Figure 7. Control Word Format,
..
'6-345
AFN-()()217D
8254
Write Operations
qulred. Any, programming sequence that follows the
conventions above is acceptable.
The programming procedure for the 8254 is very flexible.
Only two conventions need to be remembered:
.
A new initial count may be written to a Counter at any'
time wlthput affecting the Counter's programmed Mode
In any way. Counting will be affected as described in the
Mode definitions. The new count must ,follow the programmed count format.
1) For each, Counter, the Control Word must be written
before the Initial count is written.
2) The Initial count must follow the count format
specified In the Control Word (least significant byte
only, most significant byte only, or least significant
byte and then mOst significant byte).
If a Counter is programmed' to read/write two·bYte
counts, the following precaution applies: A program'
must not transfer control between writing the first and
second byte to another routine which also writes into
that same ,Counter. Otherwise, the Counter will be
loaded with an incorrect count.
Since the Control Word Register and the three Counters
have separate addresses (selected by the AhAO inputs),
and each Control Word specifies the Counter it applies
to (SCO,SC1 bits), no special Instruction sequence is reo
Control Word,...
LSB of countMSB of count Oontrol Word LSB of count MSB of count Control Word LSB of count MSB of count -
Control Word
Control' Word
Oontrol Word
LSB of count
LSB of count
LSB of count
MSB of count
MSB of count
MSB of count
-
Counter 0
Counter 0
Counter 0
Counter 1
Counter 1
Counter 1
Counter 2
Counter 2
Counter 2
Counter 0
Counter 1
Counter 2
Counter 2
Counter 1
Counter 0
Counter 0
Counter 1
Counter 2
A1
Ao
1
0
0
1
0
0
1
1
1
1
0
0
1
1
1
1
Control Word Control Word Control Word LSB of count,...
MSB of count LSB of, count MSB of count LSB of count MSB of count -
I>
0
A1
Ao
1
1
1
1
0
0'
0
0
1
1
1
1
0
1
0
0
1
0
Control Word
Control Word
LSB of count
Control Word
LSB of count
MSB of count
LSB of· count
MSB of count
MSB of count
-
Counter 2
Counter 1
Counter 0
Counter 2
Counter 2
Oounter 1
Counter 1
Counter 0
Counter 0
Counter 1
Counter 0
Counter 1
Counter 2
Counter 0
Counter 1
Counter 2
Counter 0
Counter 2
A1
Ao
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
A1
Ao
1
1
1
1
0
1
1
1
0
0
1
0
1 ,0
0
0
1
0
NOTE: IN ALL FOUR EXAMPLES. ALL COUNTERS ARE PROGRAMMED TO READlWRrrE TWO-BYTE COUNTS.
THESE ARE ONLY FOUR OF MANY POSSIBLE PROGRAMMING SEQUENCES.
Figure 8. A Few Possible Programming Sequences
Read Operations
It is often desirable to read the value of a Counter
without disturbing the count in progress. This is easily
done in the 8254.
There are three possible methods for reading the Counter~. The first is through the Read-Back command. The'
6-346
second is a simple read operation of the Counter, which is
selected with the A1,Ao inputs. The only requirement is
that 1) the CLK input of the selected Counter must be
inhibited by using either the GATE input or external logic;
or 2) the counlmust first be latched. Otherwise, the count
may be in process of changing when it is read, giving an
undefined result.
AFN-OO~17D
inter
8254
COUNTER LATCH COMMAND
The other method Involves a special software command
called the "Counter Latch Command". like a Control
Word, this command III written to the Control Word
Register, whicH Is sele9ted when A1,Ao= 11. Also'like a
Control Word, the SCO,SC1 bits select one of the three
Counters, but two other bits, 05 and 04, distinguish this
command from a Control Vlford.
A"Ao=11; CS=O; RD=1; WR=O
D7
Ds
I I
SCO
SC1
Ds
D4
I I I
0
0
D3
X
D2
D,
Do
I I I xl
X
0
0
1
1
seo
0
1
0
1
1.
2.
3.
4.
Read least significant byte.
,Write new least significant byte.
Read most significant byte.
Write new most significant byte.
If a Counter Is programmed to read/write two-byte
counts, the following precaution applies: A program
must not transfer control between reading the first and
second byte to another routine which also reads from
that same Counter. Otherwise, an Incorrect count will be
read.
X
SC1,SCO - specify counter to be latched
8C1
Another feature of the 8254 Is that reads and writes of
the same Counter may be Interleaved; for example, If the
Counter Is programmed for two byte counts, the fqllowIng sequence Is valid.
Counter
0
1
2
Read·Back Command
READ-BACK COMMAND
The read-back command allows the user to check the
count value, programmed Mode, and current state of the
OUT pin and Null Count flag of the selected counter(s).
The command is written into the Control Word Register
and has the format sho~n in Figure, 10. The command
applies to the counters selected by setting their corresponding bits 03,02,01=1.
'
05,04 - 00 designates Counter Latch Command
X - dOfl't ca~EI
AO,A'."
NOTE: DON'T CARE BITS (XI SHOU~D BE 0 TO INSURE
COMPATIBILITY WITH FUTURE INTEL PRODUCTS.
~
Ci-o liJj=1 vm=o
~
~
~
~
, I ' ICOUNflmml cml
Figure 9. Counter latching Command Format
~
CNT,
~
I
CNT 0
~
I
0
I
DS: 0 = LATCH COUNT OF SELECTED COUNTEII(8)
0 = LATCH STAtUS OF SELECTED COIJNTEIII8I
114:
D:I: , - SELECT COUNTER 2
D:I: 1 - lllLECT COUtIJI!R 1
D,: 1 = SELECT COUNTER 0
The seledted Counter's output latch (Ol) latches the
count at. the time the Counter Latch Command is reo
celved. This count is held In the latch untl! it is read by
the CPU (or until the Counter Is reprogrammed). The
count is then unlatched automatically and the Ol
returns to "following" the counting element (CE). This
allows reading the contents of the Counters "on the fly"
without ,affeqting counting in progress. Multiple
Counter Latch Commands may be used to latch more
than one Counter. Each iatched Counter's Ol holds Its
count until It is read. Counter Latch Commands do not
affect the programmed Mode of the Counter in any way.
If a Counter, Is latched and then, some time later, latChed again before the count is read, the second Counter
Latch Command is ignored. The count read will be'the
count at the time the first Counter Latch Command was
issued.
With either method, the count must be read according
to the programmed format; specifically, if the Counter Is
programmed for two byte counts, two bytes must be
read. The two bytes do not have to be read one right
after the other; read or write or programming operations
of other Counters may !>e inserted between them.
_00:
_lIVED' POR PUlUIIE EXPANSION; ..-r IE 0
Figure 10. Read-Back Command Format
The read-back command may be used to latch multiple
,counter output latches (Ol) by setting the COiJNT bit
05=0 and selecting the desired counter(s). This Single
command is functionally equivalent to several counter
latch commands, one for each counter latched. Each
counter's latched count Is held until it is read (or the
'counter is reprogrammed). That counter is automatically
unlatched when read, but other counters-remain latched
until they are read. If multiple count read-back commands
are issued tothe same counter without reading the count,
all but the first are ignored; i.e., the count which will be
read is the count at the time the first read-back command
was issued.
The read-back command may also be used to latch
status information of sEllected counter(s) by setting
STATUS bit 04=0. Status must be latched to be read;
, status of a counter Is accessed by a read from that
counter.
AfN.OO217D
8254
ThE! counter status format Is shown In Figure 11. ~Its 05
thr~)l.igh.D.o contain the counter's programmed Mode ex·
actly as written In the last MO.de Control Word. OUTPUT
pit 07 contains the current state of the OUT pin. This
allows the user to monitor the counter's output via soft·
ware, possibly eliminating some hardware from a
syotem.
De
Dr
D.
11118 ACTION:
A. WRITE 10 lHE CON1IIOL WORD
I. WRITE 10 lHE·CouNr ......... (CfI)l21
c. .NeW COUNT II LOADID INTO CE (CII-oCE);
CAU. .:
NULL COUNT-'
NIlLL COUNT.'
NULL 'COUNT-O
(11 ONLY 11IE COUNTER SPECIFIED BY 11IE CONTROL WORD WILL HAVE
ITS NULL COUNT SET TO 1, NULL,COUNT BITS OF O11IER COUNTERS
AIlE UNAFFECTED.
121 IF 11IE COUNTER 18 PROGRAMMED FOR TWO-BYTE COUNTS '(LEAST
SlCJNIFICANT BYTE THEN MOST SICJNIFICANT BYTE) NULL COUNT
CJOES TO 1 WHEN THE SECOND BYTE IS WRITTEN.
Do
D.
IIIiCIIIrE!IPI
ICD
Flg~re 12~ Null Count Operetlon
Dr , - OUT PIN IS·'
0lie' =
ISO
0-
Ds-Do
If multiple status latch operations ,of the counter(s), are
performed without reading the status, all but the first
are ignored; I.e., the status that will be read Is the status
of the counter at the time the first status read·back com·
mand was issued.
Flg,ure 11. StatuI Byte
NULL COUNT bit 06 Indicates when the last count writ·
ten to .th,. counter register (CR) has been.loaded Into the'
counting· element (CE). The exact time this happens de·
pends on the Mode of the counter and Is described In
the'Mode Definitions, but until the count Is loeded Into
the Counting element (CE), It can't be read from the
counter. If the count Is latched or read before this time,
the count value will not reflect ,he new count just writ·
ten. The operation of Null Count Is shown In Figure 12.
Command
Description
D7 De Ds D4 D3 D2 'D, Do
'0
1
0
1
1
1
1
1
0
0
0
1
0
1
1
0
0
0
1
1
1
0
"
1
1
0
1
1
0
1
1
1
1
Both count and status of the selected counter(s) may be
latched simultaneously by setting both. COUNT and
STATUS bits 05,04=0. This Is functionally the same as·
Issuing two separatl? read·back commands. at once, and
the above discussions apply here also. Specifically, If multiple count and/or status read-back commands are issued
to the same counter(s) without any intervening reads, all
but the first are.ign~~ed. This Is lIIustraiEld In Figure 13.
Result
0
Read back count and. status of
Counter 0
0
0
Read back status of Counter 1
Status latched for Counter 1
0
0
Read back status of Counters 2, 1
,Status latc~ec! for count~r
2, but notCoul'lte,r 1 .
0
0
0
Read back count of Counter 2
Count latched for Counter 2
1
0
0
Read back count and sta,tus of
Counter 1·
90unt latched for Counter 1,
but not stlitus
0 '0
1
.0
Read b!lck status of Counter 1 .
Command Ignored, status
already latched for Counter1
\
Figure 13. Read·Back Command Example
"
~
,
6-3:48
Count and status latched
. , ' ..
for Counter 0
inter
8254
If both count and status of a counter are latched, the
first read operation of that counter will return latched
status, regardless of which was latched first. The next
one or two reads (depending on whether the counter Is
programmed for one or two type counts) return latched
count. Subsequent reads return unlatched count.
1) Writing the first byte disables counting. OUT Is set
low Immediately (no clock pulse required),
2) Writing the second byte allows the new col,lnt to be
!oeded Qn the ,next ClK pulse.
This allows the counting sequence to be synchronized
by aoftware. Again, OUT does not go high until N + 1
CLK pulses after the new count of N is written •.
CI
1m
VIR
A1
Ao
0
1
0
0
0
Write into Counter 0
0
1
0
0
1
Write 'Into Counter 1
0
1
'0
1
0
Write Into Counter 2
'0
0
1
1
Write Control Word
0
1
'0
1
0
0
Read from Counter 0
0
0
1
0
1
Read from Counter 1
WIi
0
0
1
1
0
Read from Counter 2
CLK
0
0
1
1
1
No-Operation (3-State)
1
X
X
X
X
No-Operation (3-State
0
1
1
X
X
No-Operatlon (3-State)
If an Initial count Is written while GATE=O,ltwlll'stlll be
loaded on the next ClK pulse. When GATE goes high,
OUT will go high N ClK pulses later; no elK 'pulse is
nesCledto load the Counter as this has already been
done.
OW ••O
L88.4r.-_ _ _ _ _ _-:-_ __
l....lL.J
GATE - - - - - - - - - - - - - - OUT
Figure 14. ReadIWrlte Openitlons Summary
~_"'-_ _ _ __ : _ - - - - '
W1iLJUr-------CW.10
LlI.a
CLK
Mode Definitions
The following are defined for use In describing the
operation of the 8254.
GATE
ClK pulse: a rising edge, then a failing edge, in that
.
order, of a Counter's ClK input.
trigger: a rising edge of a Counter's GATE input.
Counter loading: the transfer of a count from the CR
to the CE (refer to the "Functional
Description")
CLK
MODE 0: INTERRUPT ON TERMINAL COUNT
GATE
Mode 0 Is typically used for event counting. After the
Control Word is written, OUT is initially low, and will re'
main IQw until the Counter reaches zero. OUT then goes
'high and remains high until a new count or a new Mode
o Control Word Is written into the Counter.
=
,GATE 1 enables counting; GATE
Ing. GATE has no effect on'OUT.
r--
OUT:::J
1N 1N 1N 1Nil: 1 I: 1~ 1: 1== 1
=0 disables count-
NOTE: THE FOLLOWING CONVENTIONS APPLY TO ALL MODE nMING DIAGRAMS:
•• COUNTERIARE PROGRAMMED FOR BINARY (NOT BCD) COUNTING AND FOR
READINOIWRmNG LEAST SIGNIFICANT BYTE (1.81) ONLY.
2. THE COUNTER IS ALWAYS SELECTED (eJ ALWAYS LOW).
3. ow STANDS FOR "CONTROL WORD"; CW ••0 MEANS A CONYROL WORD OF '0.
HEX IS WRlmN Tq THE COUNTER.
4. LIB STANDS FOR "LEAST SIGNIFICANT BYTE" OF COUNT•
.. NUMIERl8ELOW DIACI~. ARE CQUNT VALUES.
THE LOWER NUMBER IS THE LEAST SIGNIFICANT 8VTE.
After the Control Word and Initial count are written to a
Counter, the initial count will be loaded on the next ClK
pulse. This ClK pulse does not decrement the count, so
for an Initial count of N, OUT does not go high until N + 1
ClK pulses after the Initial couht is written.
r.H=:::~=~~~?N~':::'~~:~=~W::
CANNOT IE READ.
If a new count Is written to the Counter, It will be loaded
on the next ClK pulse and counting will contlnue'from
-the new count. If a two-byte count is written, the following happens:
<,
=E="~ ~~:'A:H:!,::~:;g:!iETWEEN COUNT VALUES.
Figure 16. ModeO
•
6-349
AFIi-G02.7D
inter.'
'·8254
MODE 1: HARDWARE.RETRIGGERABLE ONEooSHOT
MODE 2: RATE GENERATOR
OUT will be initially high.'OUT will go low on the ClK
purse following a trigger to begin the one-shot pulse,
and will remain low untH·the Counter reaches·zero. our
wJJl thel) go. high and,remain high until the Y.lK pulse
after the next trigger.
(
This Mode functions like a divide-by-N counter. 1t ,is
typiclaly used to generate a'Real Time Clock interfupt.
OUT will initially' be high: When the In'itlal count has
'decremented to 1, OUT go~s low for one elK pU,lse:OUT
then goes high again, the Counter 'reloads the Initial
count and the process is repeated. Mode 2 is periodic;
the same -sequence is repeated Indefinitely. For an inItial count o'f N, the sequence repeats every N ClK·
cycles. .
,
After writing ·the Cpntrol Word and Initial oount, the
Counter Is, .armed. A trigger re",ults .In loading the
Counter. and setting OUr IpW O{l the next ClK pulsf/,
thus starting the one-shot pulse. An Initial count of N
will res~lt in a one,sbot pulse NClK, qYC!~1I1 in duration.
The one-shot Is retrlggerable, hence OUT will remain
low for N ClK pulses after any trigger. The one-shot
. pulse can be repeated without rewriting the same count
into the counter. GATE has no effect on OUT.
"
GATE",1 enables counting; GATE=O ·dlsables countIng.lf GATE goes low during an output pulse, OUT is set
high immediately. A trigger reloads the Counter with the
Initial count on the Aexf ClK pulse; OUT goes low N
CLl< pulses after the trigger. Thus the GATE input can
be used to synchronize the Counter.
II a I'Iew cou'nt is iNi"itten to the Counter during a o'neshot pulse, the current one-shot is not affected unless
the Counter Is ,retr!ggered. In that case, tile Counter is
loaded with the new count and the one-shot pulse continues until the new count expires.
CW=12
lS"3~
After writing' a' Control \yord and initial couAt, the
Counter will be 10l\ded on the next ClK pulse. OUT goes
loW N ClK Pulses after the Initial count is written. This
allows the Counter to be synchronized by software aiso.
CW_14
_ _ _ _ _ _ _ _ _ __
LSB.3~
W1iLJU
W1iLJU
ClK
ClK
------, n--------..,,'n-----
GATE
'
,
I"
_ _ _ _ _ _ _ _ __
BAn - - - - - - - - - - - - - - - - -
I
OUT
OUT
1
1 ~ 1 1~ 1 1 ~ 1
CW-14
~
1
I~ I
LSB.3-",_ _ _ _ _- - - - -
W1iLJU
eLK.
LJ
GATE
'--___---Ir-
=:J
OUT
.1
N
1N 1 ~ 1 N 1 N 1 :' 1 U ~
n,
1~ 1 ~ 1
. eLK
QATE -------:----~.".------
GATE
-------'n-;---:--:--' rr-''--
------"".
'.
,.
, .. ,
,I.
-
u
O:UT ,:..:.:)'
•
.
OUT'
.
NOTE: A GATE tie_IOn ohouk! ftOI occur one clock prior to terminal '
count.
Figure 17_ Mode 2
Figure 16. Mode 1
•
6-350
AFN.Q0217D
inter
8254
Writing a new count while counting does not affect the
current counting sequence. If a trigger Is received after
writing a new count but before the end of the current
, period, the Counter will be loaded with the new count on
the next CLK pulse and counting will continue from the
new count. Otherwise, the new count will be loaded at
the end of the current counting cycle. In mode 2, a
COUNT of 1 is illegal.
elK
GAlE - - - - - - - - - - - - - - - - - OUT
CW_11J L88_'~------------1i1!"LJLJ
elK
GATE - - - - - - - - - - - - - - - - - OUT
MODE 3: SQUARE WAVE MODE
Mode 3 is typically used for Baud rate generation. Mode
3 is simil.ar to Mode 2 except for the duty cycle of OUT.
CW",16
elK
GATE
GATE = 1 enables counting; GATE = 0 disables counting. If GATE goes low while OUT is low, OUT is set high
immediately; no CLK pulse is required. A trigger reloa~s
the Counter with the initial count on the next CLK pulse.
Thus the GATE input can be used to synchronize the
Counter.
OUT
I " I " I" I ", I ~ I : I ~ I : I : I : I : I : I ~ I : I
NOTE: A GATE IraneMlon should not occur one clock prior to terminal
count.
After writing a Control Word and initial count, the
Counter will be loaded on the next CLK pulse. This
allows the Counter to be synchronized by software also.
Figure 18_ Mode 3
Writing a new count while counting does not affect the
current counting sequence. If a trigger is received after
writing a new count but before the end of the current
half-cycle of the square wave, the Counter will be loaded
with the new count on the next CLK pulse and counting
will continue from the new count. Otherwise, the new
count will be loaded at the end of the current half-cycle.
M~de
LSB_'4_ _ _ _ _ _ _ _ _ _ _ _ __
1i1!l.JU
OUT will initially be high. When half the initial count has
expired, OUT goes low for the remainder of the count.
Mode 3 is periodic; the sequence above is repeated indefinitely. An initial count of N results In a square wave
with a period of N CLK cycles.
I
MODE 4: SOFTWARE TRIGGERED STROBE
OUT will be initially high. When the initial count expires,
OUT will go low for one eLK pulse and then go high
again. The counting sequence is "triggered" by writing
the initial COunt.
GATE= 1 enables counting; GATE = 0 disables countIng. GATE has no effect on OUT.
3 is Implemented as follows:
Even counts: OUT is initially high. The initial count is'
loaded on one CLK pulse.and then is decremented I)y
two on succeeding CLK pulses. When the count expires
OUT changes value and the Counter is reloaded with the
initial count. The above process is repeated indefinitely.
After writing a Control Word and initial count, the
Counter will be loaded on the next CLK pulse. This CLK
pulse does not decrement the count, so for an initial
count of 'N, OUT does not strobe low until N + 1 CLK
pulses after'the initial count Is written.
Odd counts: OUT is initially high. The initial count
minus one (an even number) is loaded on one CLK pulse
and then is decremented by two 0(1 succeeding CLK
pulses.. One CLK pulse after the count expires, OUT
goes low and the Counter is reloaded with the initial
count minus one. Succeeding CLK pulses decrement
the count by two. When the count expires, OUT goes
high again and the Counter Is reloaded with the initial
count minus one. The above process is repeated indefinitely. So for 'odd counts, OUT will be high for
(N + 1)/2 couritsand low for (N - 1)/2 counts.
If a new count is written during counting, it will be loaded on the nex! eLK pulse and counting will continue
from the new count. If 'a tWO-byte count is written, the
following happens:
1) Writing the first byte has no effect on counting.
2) Writing the second byte allows the new count to be
loaded on the 'next CLK pulse.
This allows the sequence to be "retriggered" by software. 'OUT strobes low N + 1· CLK pulses after the new
count·of N.ls·written.
6-351
AFN-00217D
8254
cw.,.
,
,eLK
---"--'--, rr--------, n:.:::::
GATE"
GATE
::J,
I
N
1N 1N
CW.1.
U
·.1·
I I 1 I· IFFIFFIFFI
N
10
FF
\
FE,FD
LSBI&3r-_ _ _ _ _ _ _ _ __
r-___________
CWc1A
L. . . .
fIIIlJl..J
• eLK
ClK
,OUT
,
OUT
fIIIL....JL.J
GATE
j
LSB.a_.,....._ _ _ _ _ _~_
WIIlJl..J
ClK
OUT
:
CW.1A
LS8=-3
fill L....JL.J~~~-----
GATE
---------1f\:.:l/l~----------7"
------~
=.:J
l,F
• I • I FF I
1
0
OUT
rN
FF
,
GATE
OUT
I I I I I: I~ I~ I~ I~ I~
N
N
N
N
Flg~re
LJ
=.:J,
I
N
1
N,
1~ 1
N
1N 1
f 1:
1: 1: 1
~ 1 ~ ,I ~n
--n----vr--:-------Vc.:.=
u
:=J
I~~ I
Figure 20. Mode 5
19. Mode 4,
MODE 5: HARDWARE TR~GOERED STROBE
(RETRIGGERABL,E)
' O.Oolng
0
Dlsal!les
counting
--
1
I
and
After' wrltin~, the Control Word
Inltla! ~o~nt, the
c9unter will 'not be loaded until the CL,K pulse after a
trlgger. This ClK pul,se does, not decrement the cou,nt,
so for an·lnitial covnt of N, OUT does nOt.strobe low un·
til N + 1 ClK pulses after a trigger. '
,
2
Rlelng
High
--
Enables
counting
,'Low
Mode.
OUT will initially be high. Counting is triggered by a ris·
ing edge of GATE. When the Initial count h'as expired,
OUT will go low for one ClK pulse and then go high
again.
' '
,
Low
SIgnal
SllIIuB
1) Initiates'
counllng
2) Resets output
after nexl clock
, 1) Dlsable~
counllng
: 2) Sets output
--
Iniliaies
counting
' Enables
counllng
Inillates
counting
Enables
, oounllng'
--
Enables
cpuntlng
Irnmedlat~ly
A trigger r~s,ults In'theCount~r being load~9 with the Initial count on the' next ClK pulse. The co:untjng. sequence'is retrlggerable. OUT will not stro~e lo,w' f,or
N + 1 ClK pulses after any trigger. GATE has'no effect
on OUT.
"
high
3
"
the
If a new count is wtltteh 'dvring coulltlng,
curent
counting sequence wili 'n-ot be' affected.: if 8' trigger oc·
curs after the new.count Is written llut before the :current count expires, the Counter will be 'loaded with ,the
new count on the next ClK pulse and counting,wlll ,cwntinue from there.
•4
5
1) Disables
counting
, '2) Sets outpuf
,Immediately
high
Disables,
,
--
cou(l,tl~g
',I
'"
Inltlatee
q()\Intlng ,
,\"1 --
"
v
,
,
Figure 21. Oate Pin Operations Summary
6-352
"
inter
8254
GATE
Min
Count
Max
Count
0
1
0
1
1
0
2
2
0
3
2
0
4
1
0
5
1
0
Mode
The GATE input Is always sampled on the rising edge of
CLK. In Modes 0, 2, 3, and 4 the GATE Input Is level
senllltlve, and the logic level Is sampled on the rising
edge of CLK. In Modes 1, 2, 3, and 5 the GATE Input Is
rlslng·edge sensitive. In these Modes, a rising edge of
GATE (trigger) sets an edge·sensltlve flip·flop In the
Counter, This fllp·flop Is then sampled on the next rising
edge of CLK; the fIIp·flop Is reset Immediately after It Is
sampled. In this way, a trigger will be detected no matter
when It occurs-a high logic level does not have to be
maintained until the next rising edge of CLK. Note that
In Modes 2 and 3, the GATE Input Is both edge· and level·
sensitive. In Modes 2 and 3, If a CLK source other than the
system clock is used, GATE should be pulsed immediately
following iiiiR of a new count value.
NOTE: 018 EQUIVALENT TO 218 FOR BINARY COUNTING AND 104 FOR
BCD COUNTING.
COUNTER
Figure 22. Minimum and Maximum Initial Count.
New counts are loaded and Counters are decremented
on the failing edge of CLK.
The largest possible Initial count Is 0; this Is equivalent
to 218 for binary counting and 104 for BCD counting.
Operation Common to All Modes
The Counter does not stop when it reaches zero. In
Modes 0,1,4, and 5 the Counter "wraps around" to the
highest count, either FFFF hex for binary counting or
9999 for BCD counting, and continues counting. Modes
2 and 3 are periodic; the Counter reloads Itself with the
Initial count and continues counting from there.
PROGRAMMING
When a Control Word Is written to a Counter, all Control
Logic Is Immediately reset and OUT goes to a known
Initial state; no CLK pulses are required for this.
6-353
AFN-002170
.inter
8254
ABSOLUTE MAXIMUM RATINGS·
AmbientTemperalure Under Bias ....•.... O·C 10 70·C
Storage Temperature ... '" ......... .,.~S·C to + 1S0!C
Voltage on Any Pin with
Respect 10 Ground ..........•...... -O.SVto + 7V
Power Dissipation .••...... , ....... ~ ...... , .•. 1 Watt
"NOTICE: Stresses above those listed under "Absolute
Maximum Ratlngs" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above.
t/Jose indicated in the operational sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended per/ods may affect device
reliability.
D.C. CHARAC:rERISTICS (TA=O·C 10WC, Vee = SV:I: 10%)
Symbol
Parameter
. Min.
Max.
Units
-O.S
0.8
V
2.0
Vee+ O.SV
V
0.45
V
IOL=2.0 mA
V
IOH= -400,..A
Test Conditions
VIL
Input Low Voltage.
VIH
Input High Voltage
VOL
Output Low Voltage
VoH '
Output liigh Voltage
.IIL
Inpul Load Current
:1:10
,..A
V1N=Vccto OV
I.OFL
Output Float Leakage
:1:10
,..A
VOUT.= Vee toO.45"
Icc
Vee Supply Current
170
mA
2.4
"
CAPACITANCE (TA=2SoC, Vee=GND=OV)
Symbol
CIN
CliO
Parameter
Min.
Input Capacitance
110 Capacitance
Max.
Units
10
pF
le= 1 MHz
pF
Unmeasured pins
returned to Vss
20
"
,
Test Condltipns
-'A.C. CHARACTERISTICS (TA= O·C to 70·C, Vee = SV:I: 10%, GND=OV)
Bus Parameters (Note 1)
READ
CYCLE
/
8254
Symbol
Parameter
tAR
Address Stable Before RD!
Min.
8254-2
Max.
Min.
Max.
Unit
45
30
ns
tSR
CS Stable Before RD!
0
0
ns
tRA
Address Hold Time After ROt
0
0
ns
tRR
RD Pulse Width
150
9S'
ns
tRO
Data Delay from RD!
120
85
tAD
Data Delay from Addifts
220
185
ns
tOF
ROt to Data Floating
65
ns
IAv
Command RecoveryTime
Note 1:
S
200
90
S
16S
ns
ns
Ae timings measured at VOH =2.0V, VOL =O.BV.
AFN.(J(J2170
8254
A.C. CHARACTERISTICS (Continued)
WRITE CYCLE
8254
Symbol
Parameter
Min.
8254-2
Max.
Min.
Max.
Unit
tAW
Address Stable Before WRJ,
0
0
tsw
CS Stable Before WRJ,
0
0
ns
tWA
Address Hold Time WRt
0
0
ns
tww
WR Pulse Width
150
95
ns
tow
Data Setup Time Before WRt
120
95
ns
two
Deta Hold Time After WJ!$;t
0
0
ns
tRY
Command Recovery Time
200
165
ns
ns
CLOCK AND GATE (TA= O·C to 70·C, Vee = 5V± 10%, GND=OV)
8254
Symbol
Parameter
tClK
8254-2
Min.
Max.
Min.
Max.
Unit
Clock Period
125
DC
100
DC
ns
tpWH
tpWl
High Pulse Width
60[31
30[31
ns
Low Pulse Width
60[31
50[31
ns
tR
Clock Rise Time
25
25
ns
25
ns
tF
Clock Fall Time
lGw
Gate Width High
50
50
ns
tGl
Gate Width Low
50
,50
ns
tQs
Gate Setup Time to ClKt
50
40
ns
tGH
Gate Hold Time After Cl1
TEST POINTS
0.45
0.8
<2.0X=
DEVICE
UNDER
TEST
i J C l = 150pF
0.8
A.C. TESTING' INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC .. , .. AND 0.45V FOR
A LOGIC "0:' TIMING MEASUREMENTS ARE MADE AT 2.0V FOR A LOGIC , ..
AND O.8V FOR A LOGIC' 0 ..
Cl = 150pF
Cl INCLUDES JIG CAPACITANCE
6-356
inter
. 8254
WAVEFORMS
WRITE
110.•
4---tAW---""
cs
DATA BUS·
two--..
READ
110.,
1+---1.\.,----+1
cs
DATA B U S - - -
I~~RY
CLOCK' AND GATE
CLK
GA~
"
O~TPUT
----____
~
________
~~
+ __-'.,...______.;...;.-".___....._____________
0 __..........;__~_______________
'LAST BYTE Of.COUNT BEING WRITTEN
6-357
AFN-OOI!17D
inter·
8255A18255A-5
PROGRAMMABLE PERIPHERAL INTERFACE
• MCS·85™ Compatible 8255A·5
• 24 Programmable 110 Pins
:. Completely TTL Compatible
• Direct Bit SetlReset Capability Easing
Control Application Interface
.
• Reduces System Package Cdunt
.• Improved DC Driving Capability
a Fully Compatible with IntelC!> Microprocessor Families
• Available In EXPRESS
-Standard Temperature Range
-Extended Temp~rature, Range
• Improved Timing Charac~.ristlcs
.The Intel'" 8255A is a ge.neral purpose programmable 110 device designed for use with Intel'" microprocessors, It has
24110 pins which may be Individually programmed in 2 groups of 12 and used In 3 major modes of operation. In the first
mode (MODE 0), each group of 12110 pins may be programmed In s~ts Qf 4 to be input or output. In MODE 1, the secqnd
mode, each group may be programmed to have 8 lines of input or output. Of the remaining 4 pins, 3 are used for hand·
shaking and Interrupt control signals. .The·thlrd mode of operation (MODE 2) Is a bidirectional bus mode which uses 8
lines for a bidirectional bus, and 5 IInes,.borrowing one from the other grQup, for handshaking.
..,...,
vo
,,.,
""....
.....
.
"
.......
.
III
.."
..
..,vo
-----'
Flgure:l. 8255A Bloc~ .Dlagr.",_ .
"INTEL CORPORATION. 1982.
Figure 2. Pin CQnflguratlon
6-358
inter
8255A18255A·5
8255A FUNCTIONAL DESCRIPTION
General
The 8255A is a programmable peripheral Interface (PPI)
device designed for use In Intel microcomputer
systems. Its function Is that of a general purpose I/O
component to interface peripheral equipment to the
microcomputer system bus. The functiQnal configuration of the 8255A is programmed by the system software
so that normally no external logic Is necessary to Interface peripheral devices or structures.
Data Bus Buffer
This 3·state bldlrectlonal8·blt buffer Is used to Interface
the 8255A to the system data bus. Data is transmitted or
received by the buffer upon execution of input or output
instructions by the CPU. Control words and st~tus information are also transferred through the data bus buffer.
(RD)
,Read. A "low" on this input pin enables the 8255A to
send the data or status Information to the CPU on the
data bus. In essence, It allows the CPU to "read from"
~he 8255A.
(WR)
Write. A "low" on this Input pin enables the CPU to write
data or control words into the 8255A.
(Aoand Ad
Port Select 0 and Port Select 1, These Input signals, in
conjunction with the RD and WR inputs, control t!le
selection of one of the three ports or the control word
registers. They are normally connected to the least
significant bits of the address bus (Ao and A l ).
8255A BASIC OPERATION
---=-RD
WR
cs INPUT OPERATION (READ)
A1
AO
ReadlWrlte and Control Logic
The function of this block is to manage all of the internal
and external transfers of both Data and Control or Status
words. It accepts inputs from the CPU Address and cOntrol busses and in turn, issues commands to both of the
Contro I Grou ps.
(CS)
Chip Select. A "low" on this input pin enables the communlction between the 825M and the CPU.
POWER
SUPPLIES
1- · "
0
0
1
0
1
0
0
0
0
1
1
1
0
0
0
PORT A="oATA BUS
PORT B'" DATA BUS
PORT C- DATA BUS
OUTPUT OPERATION
(WRITE)
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
DATA BUS-PORT A
DATA BUS - PORT B
DATA BUS- PORT C
DATA BUS - CONTROL
DISABLE FUNCTION
X
X
X
X
1
1
0
1
1
0
DATA BUS" 3-STATE
ILLEGAL CONDITION
X
X
1
1
0
DATA BUS" 3-STATE
_ _ '"
"0
PA, PAo
'0
PC7P~
"0
PB,PB o
"'----"
Figure 3_ 8255A Block Diagram Showing Data Bus Buffer and Read/Write Control Logic Functions
6-359
AFN-00744C
82SSAI825SA·5 '
(RESET)
Ports A, B,and,C ,,-
R...t.,A "high",on this'il1Put clears tl1e control register
and al~ ports CA, B"O) are setto the,input mode. "
The 8255A contains three 8·blt ports (A, B, an~,_C), ~r,,,
can be configured In a wide variety of functional characteristics by, the !!ystem software but each has,lts:'pwn
speclai feature!! o,r ·,,~personallty" to further enhance.the '
power and flexibility of the 8255A.
, Group A and Group B Controls
The functional configuration 'of each port Is program·
med by the systems software. In essence, the CPU "out·
p'uts" a control word 'to the 8l1SSA. The control word con·
tains information such as "mode", "blt set", "bit reset",
etc., that Initializes the functional configuration of the
8255A.
'
Port A. One 8-bit'data output latchlbuffer and' one 8-bit
data input latch.
'
Port B. One 8-blt data Input/output latch/buffer and 'one
8-bit data input buffer.
Each ,of the Contreil blocks (Group A ~nin:Jroup B) accepts \
"commands" from the Read/Write Control Logic, receives
"con'trol words" trom the inter~al data b~'s and issu~ the
proper commands to its associated ports.
Control Group A - Port A and Port C upper (C7·C4)
Control Group B - ~?ft B and~rt~ lower (C,3·CO)
The _Convol Worq R,egister can Only be written. into. No
Re~d 'Ope~?tion cif the Controi, Word Register is allowed.
Port C. One 8·bit data output latch/buffer and one 8-blt
data input buffer (no latch for Input). This port can be
divided Into two 4-,bit ports under the mode control.
Each 4-bit port ,contains a 4·bit latch and It can be used
for the control signal outputs and status signal Inputs In
conjul)ction ,with ports A and B.,
.,
, ,~,
::
PIN CONFIGURATiON
,
;'
",",,{_+5V
......
, --""
..
PIN NAMES'
D7 Do
ReSET
CS
Rli
WR
AO,A1
PA7-PAO
P87 P90
PC7 PCO
DATA BUS 181 DIRECTIONAL)
RESET INPUT
CHIP SELECT
READ INPUT
WRITE INPUT
PORT ADDRESS
PORT A 181Tl
PORT B f81TI
PORT C fBIT)
Vee
+5VOLlS
GND
'VOLTS
Figure 4. 8225A Block OIagra'" Showing Group A and
Group B Control Functions
,
6-360
.'
AFN.Q0744C
8255A18255A·.6
8255A OPERATIONAL DESCRIPTION
Moda Salactlon
CONTROL WORD
10,10.
There are three basic modes of operation that can be selected by the system software:
Os
I D·I D31 0.1 D, I
Do
I
LJ
Mode 0 - Basic Input/Output
Mode 1 - Strobed Input/Output
Mode 2 - Bi-Directional Bus
When the reset Input goes "high" all ports will be Stt to
the Input mode (I.e., all 24 lines will be In the high impedance state). After the reset is removed the 8255A can
remain in the input mode with no additional initialization
required. During the execution of the systel)'l program
any of the other modes may be selected using a single
output instruction. This allows Ii single 8255A to service
a variety of peripheral devices with a simple software
maintenance routine.
-
/
GROUP a
\
PORT C (LOWERI
'-INPUT
0- OUTPlIT
PORTa
,-INPlIT
L..--.....
O-OUTPUT
MOOE SELECTION
O'MODEO
'-~ODE'
The modes for Port A and Port B can be separately defined,
while Port C is divided into two portions as required by the
Port A and Port B definitions_ All of the output registers, including the status flip-flops, wilt be reset whenever the
mode is changed. Modes may be combined so that their
functional definition can be "tailored" to almost'any I/O
structure. For instance;, Group B can be programmed in
Mode 0 to monitor'simple switch closings or display computational results, Group A could be programmed in Mode 1
to monitor a keyboard or tape reader on an interrupt-driven
basis.
/
GROUP A
\
PORT C (UPPERI
,-INPlTT
O-OUTPUT
PORTA
,-INPUT
0- DUTPlTT
MODE SELECTION
OO-MODEO
O,-MODE,
,X-MOOE2
ADDRESSaUS
MODE SET FLAG
,- ACTIVE
CONTROL BIll
Figure 8. Mode Definition Format
MODE 0
MODE 1
-...r
& t tt t tttt
PB,.f'80
MODE 2
c
B
CONTROL
OR 110
CONTROL
OR 110
c,
,
A
r
~O
PA,.f'Ao
l'
,go tIt 1 IfI f. '~.QlRECTIONAL
--..t
a
Pa,-Pa"
110 ' ,
A
The mode definitions and possible mode combinations
may seem confusing at first but after a cursory review of
the complete device operation a simple, logical I/O approach will surface. The design of the 8255A has taken
Into account things such as efficient PC board layo,ut,
control signal definition vs PC layout and complete
functional flexibility to support almost any peripheral
device with no external logic. Sucll design represents
the maximum use of the available pins. ,
- PA,-PAo
CO..t..OL
Singia 81t Savaa..t Feature
Ar.v of the eight bits of Port C can be Set or Reset using a
single OUTput instruction. This featUre reduces software
'
requirements in Control-based applications.
Figura 5. 'Baalc Mode Deflnltlona
and Bua Interface
6-361
inter
8255A18255A·5
When Port C is being used as status/control for Port A or B.
these bits car:J be, set or reset by using the Bit Set/Reset operation 'Just as'if they were data output ports.
CONTROL WORD
II 0 1 I0 1 I0,1 021 0, I I
o.
7
5
d.
I I I
I X
X
X I
I
Lr
DO
'
Interrupt Control Functions
When the B255A is progrnmmed, to operate in mode 1 or
mode 2, control signals are provided that can be used as
interrupt request Inputs to the CPU. The interrupt reo
quest signals, generated t'rom port C, can be inhibited or
enabled by setting or resettll'!g'the associated INiE flipflop, using the bit set/reset function of port C.
I
BIT SET/RESET
1 =SET
0= RESET
DON'T
CARE
BIT SELECT
01234567
0101010180
This function allows the Programmer to disallow or' allow a
specific ,I/O device to interrupt the CPU without affecting
any other device in the' irlterrupt structure.
0011001181
OPOOl111B21
BIT SET/RESET FLAG
O=ACTIVE
INTE .flip-flop definition:
I
(BIT-SET) '-- INTE'is SET - Interrupt enable'
(BIT-R'ESET) - INTE is RESET - Interrupt disable
Note: All Mask flip-flops are automatically reset during
mode selection and device Reset.
Figure 7. Bit Set/Reset Format
Operating Modes
Mode
MODe 0 (Basic Input/Output). This functional configuration provides simple input and output operations for
each of the three ports. No "handshaking" is required,
data is simply written to or read from a specified ,port.
• ' Two B,bit ports and two 4-bit ports.
• Any port can be input or output.
• Outputs are latched.
• Inputs are not latched.
_
• 16 different Input/Output configurations are possible
in this Mode.
.
OBasi~ Functional
Definitions:
.
't RR
---+-
.co-
- I--tHR-1
t=IRINPUT
-tRA-1
I::==.:ARC$,.Al.AO
---- - - - - ' - - ' tRD
.
,tOF
.
---
MODe 0 (Basic Input)
'wD
I------t~w-----~
1 - - - - - - 'wA------+I
a,Al,AD
OUTPUT
MODE 0 (Basic Outpul)
,6-362
AF"'-OO744C
8255A18255A·5
MODE 0 Port Definition
A
GROUPA
B
04
03
01
DO
PORTA
0
0
0
OUTPUT
0
0
0
0
0
0
0
1
0
1
1
0
0
1
0
1
0
0
1
1
1
0
0
1'
0
1
PORTC
#
PORTB
OUTPUT
0
OUTPUT
OUTPUT
OUTPUT
1
OUTPUT
INPUT
0
1
0
1
OUTPUT
OUTPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
2
3
4
OUTPUT
INPUT.
0
OUTPUT
INPUT
(UPPER)
(LOWER)
OUTPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
OUTPUT
1
OUTPUT
INPUT
5
6
7
INPUT
INPUT
0
1
INPUT
OUTPUT
8
OUTPUT
OUTPUT
INPUT
OUTPUT
INPUT
INPUT
OUTPUT
INPUT
OUTPUT
1
INPUT
OUTPUT
9
10
11
OUTPUT
0
1
INPUT
INPUT
0
1
INPUT
INPUT
12
OUTPUT
OUTPUT
1
0
0
INPUT
INPUT
13
OUTPUT
INPUT
1
1
INPUT
INPUT
14
INPUT
OUTPUT
1
1
0
1
INPUT
INPUT
15
INPUT
INPUT
1
0
0
1
1
1
1
1
1
1
GROUP B
PORTC
0
0
1
MODE 0 Configurations
CONTROL WORD >;0
0,
I, I
0,
0
0,
0,
CONTROL WORD #2
0,
0,
0,
0,
Do
,
I I I I Io I I
o
0
0
0
0,
0,
0,
0,
0,
8
A
0
0
0
0
Do
,I
I
0
8
A
PArPAo
PA,.PA,
8255A
8255A
4
c{
°7-0 0
0,
I I I I I I I
0
0
•
8
B
P~.PC4
c{
°7-0 0
•
PC7 "PC 4
•
pe3 -peO
pel-peO
PB7-PB o
B
,8
I
PB 7 "PBO
\
CONTROL WORD #3
CONTROL WORD #1
0,
0,
0,
0,
0,
0,
0,
0,
Do
I, I I o I I I I o I ' I
0
0
0
1
0
8
A
8255A
°
7-00 •
.
I
c{ .
B
•
,
0,
"
8,
0
0,
0
0,
0
0,
0
0,
Do
, 1,1
PA7-,PAo
8
A
PA,.PA,
82S5A
.
PC 3 -PC O
c{ .
p.,·pSo
B
PC7-PC4
°7-0 0 •
I
0,
I I I I I I
0
6-363
4
I
"
PC7-PC 4
PC 3 -pe O
8
p.,·pSo
AFN·OO744C
·8255A18255A-5
CONTROL WORD #4
0,
D.
Os
04
CONTROL WORD =8
03
02
0,
DO
07
I,
1,1010101,1010101
0,
05
10 1 0
DC
03
I, I
02
0,
DO
I
0 1 0 0'1 0 1\
A1-_+,8,-__ PA,-PAo
82SSA
c ,{
1---+,::'-I---f~-
82SSA
"",.pc.
!'Ca."""
8 - . PB,'PIIo
91-_+::.
91-_+'::.8- - PB,'PIIo
----------------~----~----------+---------------------------------CONTROL WORD #9
CONTROL WORD #6
0,
D6
05
04
03
02
0,
0,.0.
00
Da
DC
03
DZ
0 , 00
1,10101,1010101,1
1,1010101,10101,1
8 __ PA,'PAo
A1-_+::.
A t-_+8~__ PA,·pAo
.'
0,0°0
C
..._ _ _ _.o(
•
{I---F.--
Pc,.PC.
1--+'-- !'Ca."""
9 1-_-f.:.8__
9 t----,~8=---- ""-l'B"
CONTROL WORD #10
CONTROL WORD #6
07
06
Os
DC
PB,.~
03
02
0,
0.,
00
D.
05
04
03
02
0,'00
1,10101,1°101,101
1,1010101,101,101
8 - . PA,.PA,
A 1-_+::.
82SSA
C
o,.D, -o----.J
{I--+::'--
"",.PC,
1---+"--- pc,·pCo
'91--+,,8-_ ""'PIIo
91---f8=-- PB,'PB,
CONTROL WORD #7
0,
08
05
04
CONTROL WORD #11
03
Q1
,0,.
07
DO'
D.
Os
0
0
04
03
02
01
DO
I, I I I, I I 0,1, I, I
I, I0 I0 I0 I ; I0 I, I, I
0"
8 _ _ PA,'pAo
A 1--_-1-.:.
8 - - PA,-PAo
A......-+.:.
D,.D, ....- - - - 1
D,.o.....- - - - - 1
C
•
{I---+"'.--
!'C,'pc.
t--+'--- !'Ca'pc.
B ....._+::.8__
~ .....-+.:.8-- ""'PIIo
""-Plio
' - _ - - ' -_ _.J
6-364
AFN-00744C
8255A18255A·5
CONTROL WORD #14
CONTROL WORD =12
07
DO
I
1 1
1
1
1
1
I
1
A
.
8255A
,,8
,"
c{
.
I
•
8
B
I
06
1
05
1
03
1
02
1
0,
1
03
1
02
1
01
DO
I, I
10
PC 7 ·PC 4
°7-0 0
.
,,8
PA 7 ·PAo
,,
PCr PC 4
.
A
8255A
c{
pel-peO
pel-peO
PB 7,PRo
B
.
,,8
PB7,PSO
DO
1
I
1
8
A
8255A
.
1
04
CONTROL WORD #15
'04
1
1
05
PA 7 PAO
CONTROL WORD #13
07
06
.
c{
B
i
/
.
A
8255A
.
•
8
c{
\
B
8
•
•
8
Mode 1 Basic Functional Definitions:
Operating Modes
•
•
Two Groups (Group A and Group B)
Each group contains one 8·bit data port and one 4-bit
control/data port.
• The 8-bit data port can be either input or output.
Both inputs and outputs are latcl)ed.
• The 4-bit port is used for control and status of the
8-bit data port.
MODE 1 (Strobed Input/Output). This functional con·
figuration provides a means for transferring 110 data to
or from a specified port in conjunction with strobes or
"handshaking" signals. In mode 1, port A and Port B use
the lines on port C to generate or accept these "hand·
shaking" signals.
6-365
Input Control Signal Definition
MODE 1 (PORT AI
STB (Strobe Input). A "low" on this input loads data into
the input latch.
IBF (Input Buffer Full F/F)
A "high" on this output indicates that the data has been
loaded into the input latch; in essence,an acknowledgement
IBF is set by STB input being low and is reset by the rising
edge of the R0 input.
INTR (Interrupt Request)
A "high" on this output can be used to interrupt the CPU
when an input device is requesting service. I NTR is set by
the STB is a "one", IBF is a "one" and INTE is a "one".
It is reset by the falling edge of RD. This procedure allows
an input device to request service from the CPU by simply
strobing its data into the port.
'
MODE 1 (PORT B)
INTE A
Controlled by bit set/reset of PC 4.
INTE B
Controlled by bit set/reset of PC 2.
Figure 8. MODE 1 Input
~--tsT·-~-~
ST.
\
1/
~tSl.Ji
\
IBF
tSIT
-~1
~7
)'
INTR
,'
AD
l~tRI.~)
'
~tpH-:1
I
1/
/
•
---------------------
INPUT FROM _ _ _
PERIPHERAL
j-------tPS~~----
I
Figure 9,. MODE 1 (Strobed Input)
6·366'
AFN.Q0744C
8255A18255A·5
Output Control Signal Definition
MODE 1 (PORT AI
OBF (Output Buffer Full F/F). The OBF output will go
"low" to indicate that·the CPU has written data out to
the specified port. The OBF F/F will be set by the rising
edge of the WR input and reset by ACK Input being low.
I
CONTROL WORD
r- - .,
I INTE t
I __
A JI
ACt< (Acknowledge Input). A "low" on this input informs
the 8255A that the data from port A or port B has been ac·
cepted. In essence, a response from' the peripheral
devi'ce indicating that it has received the data output by
the CPU.
MODE 1 (PORT B)
INTR (Interrupt Request). A "high" on this output can be
used to interrupt the CPU when an output device has ac·
cepted data transmitted by the CPU. INTR is set when
ACK is a "one", OBF is a "one" and INTE is a "one". II is
reset by the falling edge of WR.
CONTROL WORD
07 06 05 04 0 3 02 0, Do
I, k>®012fl
~
oe,
OSF.
PC, - A C KA
CONTROL WORD
INTRA,
PC,
OBFA
pc. - A C K A .
~D.D&D4D3D2D,DO
PC,
ST".
pc.
IBfA
I, I, M>® °I"]°1
,
PC, - S T BA
,
pc..
1 "'INPUT
Pc,
IBFA
1· INPUT
O-OUTPUT
0" OUTPUT
3
3
I/O
PC'4
RD _ _ C
PB,'P"
pc..
I
V
•
RD _ _ C
J
PB,.PBo
WFi----"-<:
-f-
•
I/O
.......
-y
WFi-----;:c
I
;
MODE 2 AND MODE 1 (OUTPUT)
PC,
..
PA-,'PAo
PC,
CONTROL WORD
07 0 6
-Os
MODE 2 AND MODE 1 (INPUT)
PC,
INTRA
~
r--------:
pc,
P~7-PAo
oe,
OBF.
CONTROL WORD
ACKA
PC,
ST"A
PC,
IBF A
PB,·p..
-
RD
K=O
,
OBFA
- A C KA
,0., De Os 04 03 02 0, Do
04 03 02 01 Do
I' I, NXlXJ.loN
Pes
INTRA,
I,I'MXN,I'[>
TEST POINTS
<::
DEVICE
UNDER
TEST
2.0
.
0.8
i
y-----O
Co.
-=
*~XT IS SET AT VARIOUS VOLTAGES DURING TESTING
S ECIFICATION CllNCLUDES JIG CAPACITANCE
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1 AND 0 45V FOR
A LOGIC 0 TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC 1
AND 0 BV FOR A LOGIC a
6-375
VEXT'
= lS0pF
TOGUARANTEE THE
.
AFN.Q0744C
8255A18255.A·5
WAVEFORMS
MODE 0 (BASIC INPUT)
.
RD
too
--c'--
~r
-"'0-1
~IRINPUT
-tRA~\
~tAR-
CS. A1. AO
---------~(
too
.
toF
.
---
MODE·O (BASIC OUTPUT)
'wW----~
~r
7 F-
J+---tow
tAW
'w~
twA
1<..-
~.A1,AO
OUTPUT
.1---'wO--
6-376
AFN-00744C
825.5A18255A·5
WAVEFORMS (Continued)
MODE 1 (STROBED INPUT)
,
- - tST -
-'SlB11
tSlT
INTR
\
-}
i)
1--'.'B~l
'I
/
/
I--'.H-I
INPUT FROM
PERIPHERAL
--'PS
---------------------
.
MODE 1 (STROBED OUTPUT)
'I
1\
INTR
_twIT_
~{
I
OUTPUT
~.'AOB=1·
~/1
L/
-,.d-,."-
H-'wB
{j-377
AFN.()()744C
8255A182$5A·5
WAVEFORMS (Continued)
MODE 2 (BIDIRECTIONAL)
DATA FROM
8080 TO 8255
/
/
/
\
I
INTR-~\\\@-'_\t--~_~/f4r-'-~-tAK-~I-+~.J~-"---
i
ACK
~/
\
r-tST~y'
c
/
i
i,'
t_Sl._I·~-f-,.:I~~.~--+--+-i
.
- -....i-----L1
IBF _ _ _ _ _ _ _ _
~ltAol_
Ir---'-"""""'\I
PERIPHERAL 8~
-
-
-
_
-
-
-
-
-
-
-
-
-
-
-r - - I
~I l..,............t R1B
/
DATA FROM
PERIPHERAL TO 8255
DATA FROM
8255 TO 8080
NOTE:
Any sequence where WR occurs before ACK and STBoccurs before RD
tlNTR = IBF • MASK' STB • RD + OBF • MASK' ACK • WR )
WRITE TIMING
Ao-,.CS=:::>t--:_
DATUU.
IS
permissible.
READ TIMING
~:tw~'-~-.--
tAw----*1
~;
i..
tow
~
---1-
AO_l.CS==x:_ _ _ _ _ _ _
I
x=
two
1'*
tAR
.,
~~\...----
~
l---tRA
----~~
. I-.t.RRRR-*'lj~·--AD
:--L-..;f
~
~t~ot-- -jtOFI..--
WR------.jW~,~-
DATA BUS
/:;/ ~~
HIGH IMPEDANCE
VAllO
;H1GH IMPEDANCE
l---ftww
6-378
AFN-D0744C
intJ
8256AH
MULTIFUNCTION UNIVERSAL
,ASYNCHRONOUS RECEIVER~TRANSMITTER (MUART)
I
'
• Programmable Serial Asynchronous
Communications Interface for 5·,8·,7·,
or 8·Blt Characters, 1, 11f2, or 2 Stop
Bits; and Parity Oeneratlon
• Two 8·Blt Programmable Parallel I/O
Ports; Port 1 Can, Be Programmed for
Port 2 Handshake Controls and Event
Counter Inputs
• On·Board Baud Rate Generator
Programmable for 13 Common Baud
Rates up to 19.2K Bits/second, or an
Exte...,al Baud Clock Maximum of 1M
Bit/second
• Eight-Level Priority Interrupt Controller
Programmable for 8085 or IAPX 86,
IAPX 88 Systems and for Fully Nested
Interrupt Capability
• Five 8-Blt Programmable Timer/
Counters; Four Can Be Cascaded to
Two 18-Blt Timer/Counters
• Programmable System Clock to 1 )( ,
2)( , 3)(, or 5)( 1.024 MHz
The Intel~ 8256AH Multifunction Universal Asynchronous Receiver-Transmitter (MUART) combines five commonly used functions into a single 4O-pin device. It is designed to interface to the 8086188, iAPX 186/188,·
and 8051 to perform serial communications, parallel I/O, timing, event counting, and priority interruptfunctions. All of these functionS are fully programmable through nine inte,rnal, registers. In addition, the five
timer/countEtrs and two parallel I/O ports can be accessed directly by the microprocessor.
AD1
ADO-AD4
ADZ
91-087
P14
DB7
P11
P1.
ALE
P17
iiii
Viii
P20
088
CLK
iii
iiii
WI!
ALE
PM
RESET
RaD
TaD
JIiITl
INT~--,.
_ _......
RiC
CLK
TaC
IiiC
Ciii
RaD
GND
. Figure 1. MUART Block Diagram
, Figura 2. MUART Pin Configuration
Intel Corporation Assumes No ResponSibility for the Use of Any Circuitry Other Than Circuitry Entlodled In an Intel Prodtd. No Other CircUit Patent Licenses are Implied
• INTEL c;oRPORATION. 1983
6~79
ORDER NUM8E~~:~~~S:~
8256AH
Table 1. Pin Description
Symbol
AQO-A:D4
DBS-DB7
Pin
1-5
a.:a
,
Name and Function
Type
110 ADDRESSIDATA: ThreHtate addl'ess/data lines wtlich,interface: to the, lower
.
8 bits of the microprocessor's multiplexed address/data bus. The 5-bit
address is latched on the falling edge of ALE. In the 8-bit mode, ADO-AD3
are used to select the proper register, while AD1-AD4 are used in the 16-bit
mode. AD4 in the &obit mode Is ignored as an address, while ADO in the
1&obit mode is used as a second chip select, .ae,tive low.
,
ALE
9
I
ADDRESS LATCH ENABLE: Latches the 5 address lines on ADQ-A~ and OS:on the
falling edge.
'Air
10
I
READ, CONTROL: When this signal is low, the selected [eglster is gated
'
'onto the data bus.
WR'
11
I
WRITE CONTROL: When this signal is low, the value on the data bus is
written into the selected register.
RES~
12
I
e§
13
I
CHIP, SELECT: A low on this signal enables ,the MUART. It ill latched with
the addrees on the falling edge of ALE. and AD and WR' have no effect
unless CS was latched low during the ALE cycle.
fRTA
14
I
INTERRUPT ACKNOWLEDGE: If the MUART has been enabled to respond
,to interrupts. this signal informs the MUART that its interrupt request is being
acknowledged by the microprocessor. During this acknowledg8rJ1ent the
MUART puts an ASTn instruction on the data bus for the 8-bit mode or
a vector for the HI·bit mode.
INT_
15
0
INTE"RUPT REQU,EST: A high signals the microprocessor that the MUAAT
needs service.
EXTINT
16
I
EXTERNAL INTERRUPT: An external, device. can request interrupt service
through this input. The input is level sensitive' (hilt!), therefore It must be
held high until an iN'fA occurs or'the interrupt address register is read.
elK
17
I
Axe
18
I/O
RxD
19
I
GND
20
PS
I:tI;SET: An active hilt! pulse ,on this pi~ forCes, the chip into its initial' state.
. ,
The chip remains in this state until control information Is written.
SYSTEM CLOCK: The reference clock for the baud rate generator and the timers.
RECEIVE CLOCK: If the baud rate bits in the Command Aegister 2 are all 0,
this pin is an input which Clocks serial data into the AxD pin on the rising
edge of AxC. If baud rate bits in Command Register 2 are programmed from
1-OFH. this pin outputs a square wave whose rising edge indicates when
the data on RxD is being sampled.' This output remairs high during start:
stoP. and parity bits.
'"
RECEIVE DATA: Serial data input.
GROUND: Power supply and logic ground reference.
,.
'/
6~O
23075g.()()1
8256AH
Table 1. Pin Description (continued)
Symbol
CTS
Pin
Type
Name and Function
21
I
CLEAR TO SEND: Thi~ut enables the serial transmitter. If 1, 1.5, or 2
stop bits are selected
is level sensitive. As ,long as CTS is low, any
character loaded, into the trans/TIitter buffer register will be transmitter serially.
A single negative going pulse causes the transmission of a single char~er previously
loaded into the transmitter buffer register., If a 'baud rate from 1"()FH is
selected, C'i'§' must be low for at least .1/32
a bit, or it will be ignored. If
the transmitter buffer is empty, this pulse will be ignored. If this pulse
occurs during the transmission of a character up to the time where V2 the first
(or only) stop bit is sent out, it will be ignored. If it occurs afterwards, but
before the end of the stop bits, the next character will be transmitted
immediately following the current one. If C'i'S is still high when the transmitter
register is sending the last stop bit, the transmitter will enter its idle state
until the next high-to-Iow transition on ~ oCcurs. If 0.75 stop bits is
chosen, the C'i'S input is edge sensitive. A negative edge on C'M results in the
immediate transmission of the next character. The length of the stop bits is
determined by the time interval between the beginning of the first stop bit and
A high-to-low transition has no effect if the
the next negative edge on
transmitter buffer is empty or if the time interval betWeen the beginning of the
stop bit and next negative edge is less than 0.75 bits. A high or a low level
or a low-to-high transition has no effect on the transmitter for the 0.75 stop bit mode.
m
m
TxC
22
I/O
TRANSMIT CLOCK: If the baud rate bits 'in command register 2 are all set
to 0, this input clocks data out of the transmitter on the falling edge. If baud
rate bits are programmed for 1 or 2, this input permits the user to provide a
32x or 64x clock which is used for the reoeiver and transmittei. If the baud rate
bils are programmed for 3-OFH, the internal transmitter clock is output. As an
output it delivers the transmitter clock at the selected bit rate. If 11h or 0.75
stop bits are seleCted, the transmitter divider will be asynchronously reset at
the beginning of each start bit, immediately causing a high-to-Iow transition
on TxC. TxC makes a high-to-Iow transition at the beginning of each serial
bit, and a low-to-high transition at the center of each bit.
23
0
TRANSMIT DATA: Serial data oulput.
P27-P20
24-31
I/O
PARALLEL 110 PORT 2: Eight bit general purpose I/O port. Each nibble (4 bits)
of this port can, be either an input or an output. The outputs are latched whereas
the input signals are not. Also, this port can be used as an 8-bit input or output
port when using the two-wire handshake. In the handshake mode both inputs
,'
and outputs are latched.
P17·P10
32-39
I/O
PARALLEL 110 PORT 1: Each pin can be programm'ed as an input or an output
to "perform general purpose I/O. All .outputs are latched whereas inputs are
not. Alternatively these pins can serve as control pins which extend ,the
functional spectrum of the Chip.
40
PS
POWER: +5V power supply. '
TxD
Vee
230759-001
8256AH
FUNCTIONAL DESCRIPTION
The 8256AH Multi-Function Universal Asynchronous
Receiver-Transmitter (MUART) combines.five commonly used functions into a single 40-pin device. The
MUART per10rms asynchronous serial communications, parallel I/O, timing, event counting, and interrupt control. For detailed application information, see
Intel Ap Note #153, Designing with the 8256.
Serial Communications
The serial communications portion of the MUART
contains a full-duplex asynchronous receivertransmitter' (UART). A programmable baud rate
generator is included on the MUART to permit a varIety of operating speeds without external components.
The UART can be programmed by the CPO for a
variety of character sizes, J)&rity generation and detection, error detection, and start/stop bit handling. The
receiver checks the start and stop bits In the center
of the bit,and a break halts the reception of data. The
transmitter can send breaks and can be controlled
by an external enable pin.
Parallel 1/0
The MUART includes 16 bits of general purpose
parallel I/O. Eight bits (Port 1) can be individually
changed from input to output or used for special I/O
functions. The other eight bits (Port 2) can be used
as nibbles (4 bits) or as bytes. These eight bits also
include a handshaking capability using two pins on
Port 1.,
CounterlTimers
Tbere are five 8-blt counter/timers on the MUART.
The timers can be programmed to use, either a 1 kHz
or 16 kHz clock generated from the system clock.
Four of the 8-blt counter/timers can be cascaded'to
two 16-bit counter/timers, and one of the 8-bit
counter/timers can be reset to its initial value by an
external signal.
Interrupts
An eight-level priority interrupt controller can be configured for fully nested or normal interrupt priority.
Seven of the eight interrupts service functions on the
MUART (counter/timers, UART), and one external interrupt is provided which can be used for a particular
function or for chaining interrupt controllers or more
MUARTs. The MUARTwili support 8085 and 8086/88
systems with direct interrupt vectoring, or the MUART
can be polled to determine the cause of the interrupt.
If additional interrupt control capability is needed, the
MUART's interrupt controller can be cascaded into
another MUART, into an Intel 8259A Programmable
Interrupt Controller, or into the interrupt controller of
the iAPX 186/188 High-Integration Microprocessor:
INITIALIZATION
In general the MUART's functions are independent
of each other' and only the registers and bits
associated with a particular function need to be initialized, not the entire Chip. The command sequence
is arbitrary since every register is directly addressable;
however, Command Byte 1 must be loaded first. To
put the device into a fully operational.condition, it is
necessary to write the following commands:
Command byte 1
Command byte 2
, Command byte 3
Mode byte
Port 1 control
Set Interrupts '
The modification register may be loaded'if required
for special applications; normally this operation is not
necessary. The MUART should be reset before initialization. (Either a hardware or a software reset will
do.)
,
INTERFACING
This section describes the hardware interface between the 8256 MUART and the 80186
microprocessor. Figure 3 displays the block diagram
for this interface. The MUART can be interfaced to
many other microprocessors using these basic
. principles.
'
In all cases the 8256 will be connected directly to the
CPU's multiplexed address/data bus. If latches or
data bus buffers are used in a system, the MUART
should be on the microprocessor side of the address/data bus. The MUART latches the address in- •
ternally on the falling edge of ALE. The address consists of Chip Select (CS) and four address lines. For
8-bit microprocessors, ADO-AD3 are the address lines.
For 16-bit microprocessors, AD1-AD4 are the address
lines; ADO is used as a second chip select which is
active low. Since chip select is internally latched along
with the address, it does not have to remain active
during the entire instruction cycle. As long as the chip
select setup and hold times are met, it can be derived from multiplexed address/data lines or multiplexed address/status lines. When the 8256 is in the 16-bit
mode, AO serves as a second chip select. As a result .
the MUART's internal registers will all have even addresses since AO must be zero to select the device:
Normally the MUART will be placed on the lower data
byte. If the MUART is placed on the upper data byte.
6-382
230759-001
inter
8256AH
Vee
16 MHz
n
r°'"
X X RESET
1 2R6
INTO
INTAO
ALE
J
+-sv-
-r
.f"
WR
RES
SRDY
1/
DT/R IDEN I-
NMI
ADo-15
HOLD
rv
~
r
STB
8282
ADDR/DATA
pcso
ADDRESS
lATCH
(2) OE
v
f
80186
8286
(16)
DATA
TRCVR
~~E(2)
v
.
'""""
(8)
...
ALE INTA INT WR
ADo-4
8256
°5-7
CS
r1
CLOCK II
GENERATOR
RD RESET ClK
PORT 1
(8)
~
(8)
CTS TxD RxD TxC RxC EXTINT
,
-
f
SERIAL 1/0
Figure 3_ 80186/8256 Interface
the internal registers will be 512 address locations
apart and the chip would occupy an 8 K word address
space.
DESCRIPTION OF THE REGISTERS
The following section will provide a description of the
registers and define the bits within the registers where
appropriate. Table 2 lists the registers and their
addresses.
Command Register 1
L1 I LO I 51 I 50 IBRKI! BITI. I 8086 I FRO I
(OR)
(OW)
FRO -
Timer Frequency Select
This bit selects between'two frequencies for the five
timers. If FRO = 0, the timer input frequency is 16
kHz (62.5fLS). If FRO = 1, the timer input frequency
is 1 KHz (1 ms), The selected clock frequency is
, shared by all the counter/timers enabled for timing;
thus, all timers must run with the same time base.
8086 - 8086 Mode Enable
This bit selects between 8085 mode and 8086/8088
mode. In 8085 mode (8086 = 0), AO to A3 are used
to address the internal registers, and an R5Tn instruction is generated in response to the first INTA. In
I." 8086 mode (8086 = 1), A1 to A4 are used to address the internal registers, and AO is used as an extra chip select (AO must equal zero to be enabled).
The response to INTA is for 8086 interrupts where
the first INTA is ignored, and an interrupt vector (40H
to 47H'i!..E!aced on the bus in response to the
second INTA.
BITI -
Interrupt on Bit Change
This bit selects between one of two interrupt sources
on Priority Level 1, either Counter/Timer 2 or Port 1
P17 interrupt. When this bit equals 0, CounterlTimer
2 will be mapped into Priority Level 1. If BITI equals
o and Level 1 interrupt is enabled, a transition from
1 to 0 in CounterlTimer 2 wiU generate an interrupt
request on Level 1. When BITI equals 1, Port 1 P17
external edge triggered interrupt source is mapped
into Priority Level 1. In this case if Level 1 is enabled, a low-to-high transition on P17 generates an
interrupt request on L~vel 1.
6-383
250759·001
intJ
8256AH
Table 2. MUART Registers
Read Registers
8085 Mode: AD3 AD2 AD1 ADO
8086 Mode: AD4 AD3 AD2 AD1
L1 1 LO 1 Sl 1 so 1BRKII BITI1808s1 FROI 0
Command 1
Write Registers
;0
o
0
0 I II I LO I Sl I
IBRKII BITI IS08S1 FROI
Command 1
0
o
0
1
1 0 I RxE 1 IAE I NIE I 0 ISBRKITBRKI 0 I 0
Command 3
o
0 I SET 1 RxE 1 IAE 1 NIE I END ISBR*BR~ RST 1
Command 3
I T351 T241 T5C I CT31 CT21 P2C21 P2C1 IP2coI 0
Mode
,
o
1 I T351 T241 T5C I CT31 CT21 P2C21 P2C11 P2coI
Mode
I PENI EP 1 C1 1 CO 1 B31 B2 1 B1 1 BO
Command 2
I
I P171 P1s1 P151 P141 P131 P121 P111 P10 I
Port 1 Control
I L7 I LS
0
I L3 I L2 III I LO I 0
Interrupt Enable
o
1 I L7 I LS I L5 I L4 I L3 I L2 I II I \,0 I
Set Interrupts
I
I Osl
I 07
I 06 I 05
P1S1 P15 I P14 I P131 P12 I P11 I P10 I
Port 1 Control
o
05 1 04 1 03 02 I 01
Interrupt Address
I 07
I P171
I CO 1 B3 1 B2 1 B1 1 BO 1
Comml!nd2
0
I L5 I L4
I 07 I Osl
I PEN 1 EP I C1
05 1 04 I 03 1 02
Receiver Buffer
I 01
I DO I
o lul~I~IUI~IUlll
0
I 00'1 0
I 04
wi
Reset Interrupts
'107 I OS I 05 I 04 I 03 I 02 I 01 I DO
Transmitter Buffer ,
0
I 07
I 06 I 05 I 04 I 03
Port 1
I 02
I
I 03 I 02 I 01 I 00 I 1
Port 1
0
0
I 01 I 00 I
[ 07 I OS I ,05 I 04 I 03 I 02 I 01 I DO I 1
Port 2
0
0
Iwl06I~I~looloolmlool
Timer 1
o
o Iwl06I~I~looloolmlool
Timer 1
Iwl06I~I~looloo[mlool 1
o
IwIMI~~~looloolmlool
1~1061~1~looloolmlool
Port 2
Timer 2
Timer 2
Iwl06I~I~looloolmlool 1
Timer 3
o
0 I 07 I 06 I- 05 I' b4 I 03 I 02 I 01 I DO I
Timer 3
Iwlool~I~I~I~lm,lool 1
Timer 4
o
I 07 I OS I 05 I 04 I 03 I 02 I 01 I-DO I
Timer 4
I 07 I 06
I' 05 I 04 I 03 I 02 I 01 I DO I 1
Timer 5
,
o I 07 1 06 I 05 I 04 I 03 I 02 I 01 I 00 I
Timer 5
liNT I R,t;!F I TaE l TRE I Bo·1 PE I OE I FE I 1
Status
1 I 0 I~S4IRS3IRS2IRS1 IRSolJME losci
Modification
6.,.384
230759·001
intJ
8256AH
SRKI - Break-In Detect Enable
If this bit equals 0, Port 1 P16 is a general purpose
1/0 port. When BRKI equals 1, the Break-In Detect
feature is enabled on Port 1 P16. A Break-In condition is present on the· transmission line when it is
forced to the start bit voltage level by the receiving
station. Port 1 P16 must be connected externally to
the transmisSion line in order to detect a Break-In.
A Break-In is polled by the MUART during the
transmission of the last or only stop bit of a character.
A Break-In Detect 'is OR-ed with Break Detect in Bit
3 of the Status Register. The distinction can be made
through the interrupt controller. If the transmit and
receive interrupts are enabled, a Break-In will
generate an interrupt on Level 5, the transmit interrupt, while Break will generate an interrupt on Level
4, the receive interrupt.
SO, S1 -
If bits O...3 are set to 0, separate clocks must be
input to pin RxC for the receiver and pin TxC for the
transmitter. Thus, different baud rates can be used
for transmission and reception. In this case,
prescalers are disabled and the input serial clock frequency must match the baud rate. The input serial
clock frequency can range from 0 to 1.024 MHz.
BO, B1, B2, 83 - Baud Rate Select
These four bits select the bit clock's source, ampling rate, and serial bit rate for the internal baud rate
generator.
Stop Bit Length
S1
SO
Stop Bit Length
Q
1
1.5
1
0
1
0
1
1
0
vide a frequency of either 32x or 64x the baud rate.
The data transmission rates range from O. • .32
Kbaud.
B3
0
B2
0
0
0
0
0
0
0
0
2
0.75
0
0
1
1
The relationship of the number of stop bits and the
function of input CTS is discussed in the Pin Description section under "CTS".
L1
LO
Character Length
0
0
1
0
1
8
7
1
1
0
1
6
5
1
I
I B3
1
1
0
1
1
1
0
1
0
0
0
0
0
1
0
1
1
0
1
0
0
1
0
1
1
1
1
0
1
1
0
1
Baud
Rate
TxC, RxC
TxC/64
Sampling
Rate
1
64
TxC/32
19200
9600
4600
2400
1200
600
300
200
150
110
100
75
50
32
32
64
64
64
64
64
64
64
64
64
64
64
64
The following table gives an overview of the function
of pins TxC and RxC:
B1
B2
0
.1
1
Command Register 2
IPEN EP I C1 I CO
(1R)
0
0
1
BO
0
1
0
0
1
1
1
LO, L 1 - Character Length
1
0
1
1
B1
BO
(1W)
...3 with values from 3H to FH
Programming bits O
enables the internal b\iud rate generator as a common clock source for the transmitter and receiver and
determines its divider ratio.
Bits 3 to
o (Hex.)
TxC
Input: 1 x baud
0
rate clock for the
transmitter
1,2, Input: 32 x or 64 'x
baud rate for transmitter and receiver
i
Programming bits O... 3 with values of 1H or 2H
el'lables input TxC as a common clock source for the
transmitter and receiver. The external clock must pro-
6-385
3 to F
Output: baud rate
clock of the
transmitter
RxC
Input: 1 x baud
rate clock for the
receiver
Output: receiver bit
clock with a low-tohigh transition at
data bit sampling
time. Otherwise:
high level
Output: as above
230759-001
inter
8256AH
As an output; RxCoutputs a low-ta-high transition at
sampling time of every-data bit of a character. Thus;
data can be loaded, e.g., into a shift register exter'nally, The ,transition occurs pnly if oata bits of, a
character are present. It does,not occur for start, parity, and stQP bits (Rxe = high).,
"
As an output, TxC outputs the internal baud rate clock
curs to that bit. When 99mmandRegister 3 is read,
bits 0, 3, and 7 will always be zero.
RST -
Reset
If RST is set, the following ev,ents occur:
of the transmitter. There will beahigh-to-Iow transi~
tion at every beginning of a bit.
1. All bits in the Status Register except bits 4 and 5
are cleared, and bits 4 and 5 are set.
CO, C1 :- System, Clock ~rescaler
(Bits 4, 5) ,
2. The Interrupt Enable; Interrupt Request, and)nterrupt Service Registers are cleared. Pending requests and indications for interrupts in service will
be cancelled. Interrupt signal INT will go low.
Bits 4 and 5 define the system clock prescaler.divider
ratio; The internal operating frequency of 1.024 MHz
is derived from the system clock.
C1
CO
0
0
1
0
1
1
EP
~
Divider Ratio ,
,5
0
3
2
1
1
Clock at Pin
CLK
' 5.12 MHz
3.072 MHz
2.048 MHz
' 1.024 MHz
Parity Enable (Bit 7)
= 0: No parity bit
= 1: Enable parity bit
The parity bit according to Command Register 2 bit
'6 (see above) is inserted between the last data bit of
a character and the first or only stop bit. The parity
bit is checked during reception. A false parity bit
generates an error indication in the Status· Register
and an Interrupt Request on Level 4.
Command Register 3
!$ET! RxE IIAE I NIW I END 1SB.RK I TBRK I, RST
(?R)
.'
RST doeS not alter ports, data registers or command
registers, but it halts any operation in progress. RST
is automatically cleared.
TBRK -
Bit 7 enables parity generation and checking.
PEN
PEN
4. If Port 2 is programmed for handshake mode, IBF
and OBF are reset high.
RST '= 0 has not effect. The reset qperation triggered
by Command Register 3 is a subset of Ihe hardware
reset.
Even Parity (Bit 6)
EP = 0: Odd parity
EP = 1: Even parity
PEN -
3. The receiver and transmitter are reset. The
transmitter goes idle (TxD is high), and the receiver
enters start bit search mode.
. (2W)
,
Command Register 3 is different from the first two
registers because it has a bit set/reset capability.
Writing a byte with Bit 7 high sets any bits which were
also high. Writing a byte with Bit 7 low resets any bits
which were high. If any bit 0-6 isjoVv, no change oc~
Transmit Break
The transmission data output TxD will be set low as
soon as the transmission of the previous character
has been finished. It stays low until TBRK is cleared.
The state of CTS i~ of no significance for this
operation. As long as break is active, data transfer
from the Transmitter Buffer to the Transmitter
Register will be inhibited. As soon as TBRK is reset,
the break condition will be deactivated and the
transmitter will be re-enabled.
SBRK -
Single Character Break
\
",
'
{
This causes the transmitter data to be set low for one
character including start bit, data bits, parity bit, and
stop bits. SBRK is automatic~IIY c,leared when time
for the last data bit has passed. It will ,start after the
character in progress completes, and will delay the
next data transfer from the Transmitter Buffer to the
Transmitter Register until TxD refurns to an idle
(marking) state. If both TBRK and'SBRK are set,
break will be set as long as TBRK is set, but SBRK
will be cleared after one character time of break. If
SBRK is set again, it remains set for another
ctlaracter. The user can send a definite number of
break characters in this manner by blearing TBRK
after setting SBRK tor the last charactertir'r1e.
230759·001
intJ
END -
8256AH
End of Interrupt
P2C2, P2C1, P2CO -
If fully nested interrupt mode is selected, this bit reset
the currently served interrupt level in the Interrupt Service Register. This command must occur at the end
of each interrupt service routine during fuily nested
interrupt mode. 'END is automatically cleared when
the Interrupt Service Register (internal) is cleared.
END is ignored if nested interrupts are not enabled.
, .
NIE -
Nested Interrupt Enable
When NIE equals 1, ttie interrupt controller will
opera.te in the nested interrupt mode. When NIE
equals 0, the interrupt controller will op(;lrate in the
normal interrupt mode. Refer to the "Interrupt controller" section of Ap·153 under "Normal Mode"
and "Nested Mode" for a detailed description of
these operations.
IAE -
Interrupt Acknowledge Enable
This bit enables an automatic response to INTA. The
particular. response is determined by the 8086 bit in
Command Register 1.
'
RxE -
Receive Enable
This bit enables the serial rec'eiver and its associated
status bits in the status register. If this bit is reset,
the serial receiver will be disabled and the receive
status bits will not be updated.
Note that the de.tection of break characters remains
enabled while the receiver is disabled; i.e., Status
Register Bit 3 (BD) will be set while the receiver is
disabled whenever a break character has been
recognized at the receive data input RxD.
SET -
P2C2 P2C1 P2CO
Bit Set/Reset
If this bit is high during a write to Command Register
3, then any bit marked by a high will set. If this bit
is low, then any bit marked by a high will be cleared.
Mode Register
IT351 T24! TSC ! CT3! CT2! P2C2! P2C1 ! P2CO !
(3R)
(3W)
If test mode is selected, the output from the internal
baud rate generator is placed on bit 4
Port 1 (pin
35).
of
To achieve this, it is necessary to program bit 4 of .
Port 1 as an Ol,!tput (Port 1 Control Register Bit P14
= 1), and to program Command Register 2 bits B3
- BO with a value ~ 3H.
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
1
1
1
0
1
Port 2 Control
Direction
Upper Lower
Mode
Nibble
Input Input
Nibble
Input Output
Nibble
Output Input
Nibble
Output Output
Byte
Input
Handshake
Output
Han~e
shake
DO NOT USE
Test
NOTE:
If Port 2 is operating in handshake mode, Interrupt Level 7
is not available for Timer 5. Instead it is assigned to Port 2
handshaking.
CT2, CT3 -Counter/Timer Mode
Bit 3 and 4 defines the mode of operation of event
counter/timers 2 and 3 regardless of its use as a single
unit or as a cascaded one.
If CT2 or CT3 are high, then counter/timer 2 or 3
respectively is configured as an event counter on bit
2 or 3 respectively of Port 1 (pins 37 or 36). The event
counter de.crements the count by one on each lowto-high transition of the external input. If CT2 or CT3
is low, then the respective counter/timer is configured
as a timer and the Port 1 pins are used for parallel 110.
T5C - Timer 5 Control
If T5C is set, then Timer 5 can be preset and started
by an external signal. Writing to the Timer 5 register
loads the Timer 5 save register and stops the timer.
A high-ta-Iow transition on bit 5 of Port 1 (pin 34) loads
the timer with the saved value and starts the timer.
The next high-to-Iow transition on pin 34 retriggers
the timer by reloading it with the initial value and continues Vming.
Following a hardware reset, the save register is reset
to OOH and both clock and trigger inputs are disabled. Transferring an instruction with T5C
1
enables the trigger. input; the save register can now
be loaded with an initial value. The first trigger pulse
causes the initial val,ue to be loaded from the save
register and enables the counter to count dowrr'to
zero.
'
=
When the timer reaches zero it issues an interrupt
request, disables its interrupt level and continues
counting. A subsequent high-to-Iow transition on pin
5 resets Timer 5 to its initial value. For another timer
interrupt, the Timer 5 interrupt enable bit must be set
again.
" 6-387
230759-001
inter
8256AH
Regl$t~r
T35, T24 - Cascade Timers
Port 1. Control
These two bits cascade Timers 3 and 5 or 2 and 4.
Timers 2 and 3 are the lower bytes, .While Timers 4
and 5 are the upper bytes. If T5C is set, then both
Timers 3 and 5 can be preset and started by an external pulse.
IP171 P161 P15, IP141 P131.P12 I' P11
(4W)
P10
(4W)
Each bit in the Port 1 Control Register configures the
direction of the corresponding pin. If the bit i!iS high,
the pin is ari output, and if it low the pin is an input.
Every Port 1 pin has another function which is controlled by other registers. Jf that special function: i.
disabled, the pin functions as a general 110 pin ,as
specified by tl)is register. The speeial functions for
each pin are described below. .
When a high-to-Iow transition occurs, limer 5 is preset
to its saved value, Bl,lt Timer 3 is always preset to all
ones. If either CT2 or CT3 is set, then the corresponding timer pair is a 16·bit event counter.
Asummary of the counter/timer control bits is given
in Table 3. ,
Port
NOTE:
Interrupt levels assigned to single counters are partly not occupied if event countersltimers are cascaded. Level 2 will be
vacated if event countersltimers 2 and 4 are cascaded.
Ukewise, Level 7 wUl be vacated if event countersltlmers 3
and 5 are cascaded.
.
Single event countersltimers generate an interrupt request
on the transition from 01H to OOH, while·cascaded ones
generate it on the transition from 0001 H to QOOOH.
to, 11 - Handshake Control
If byte handshake control is enabled for ~rt 2 by
t1!!...Mode Register, then Port 10 is programmed as
STB/ACK handshake.£Qntroi input, and Port 11 is
programmed as IBF/OBF handshake control output.
If ~e:andShake mode is enabled for output on Port
2
iIJdicates that a character has been loaded
Table 3. Event CountersITlmers Mode of Operation
Event Counter/
Timer
1
2
Programming
(Mode Word)
Function
-
8-bit timer
Clock Source
Internal clock
8-bit timer'
T24=O, CT2=O
Intefl;lal clock .
8-bit event counter
T24=O, CT2=1
P12 pin 37
8-bit timer
T35=O, CT3=0
Internal clock
B-bit event counter
T35=O, CT3= 1
P13 pin
4
B-bit timer
T24=O
Internal clock
8-bit timer,
normal mode
T35=O, T5C=0
Internal clock
5-
8-bit timer,
retrigger.able mode
T35=O, T5C=1
Intemal.clock
16-bit timer
T24=1, CT2=0
Internal clock
16-bit event counter
T24=1, CT2=1
P12 pin 37
16-bit timer,
normal. mode
T35=1, T5C=O,
CT3=0
Internal clock
16-bit event counter,
normal mode
T35=1, T5C=O,
CT3=1
16-bit timer,
,retriggerable mode
T35=1, T5C=~,
CT3=0
Internal clock
T35=1, T5C=1, .
CT3=1
P:13 pin 36
2
2 and 4
cascaded
3 and 5
cascaded
16-bit event counter,
retriggerable mode
6-388
.
36
J
P13 pin 36
)
230759-001
inter
8256AH
Interrupt Enable Reglater
into the Port' 2 output buffer. When an external
device reads the data, it acknowledges this operation by driving ACK low. OBF is set low by writing to
Port 2 and is reset by ACK.
1 L7 1 L6 1 LS 1 L4
If b.lillthandshake mode is enabled for input on Port
2, STB is an input. IBF is driven low after STB goes
low. On the rising edge of STB the data from Port 2
is latched.
IBF is reset high when Port 2 is read.
Port 12, 13 - Counter 2, 3 Input
If Timer 2 or Timer 3 is programmed as an event
counter by the Mode Register, then Port 12 or Port
13 is the counter input for Event Counter 2 or 3,
respectively.
'
Port 14 - Baud
Clock
~at(!
L3
I
(SR)
LO
Interrupts are enabled py writing to the Set Interrupts
Register (SW). Interrupts are disabled by writing to
the Reset Interrupts Register (6W). Each bit set by
the Set Interrupts Register (5W) will enable that level
interrupt, and each bit set in the Reset Interrupts
Register (6W) will disable that level interrupt. The user
can determine which interrupts are enabled by
reading the Interrupt enable Register (SR).
Priority
Highest
LO
L1
L2
L3
L4
LS
L6
L7
Generator Output
If test modEl is enabled by the Mode Register and
Command Register 2 baud rate select is greater than
2, then Port 14 is an output from the internal baud
rate generator.
Lowest
P14 in Port 1 control register must be set to 1 for the
baud rate generator clock to be output. The baud rate
generator clock is 64 x the serial bit rate except at
19.2Kbps when it is 32 x the bit rate.
L2
L1
(5W=enable,
(6W = disable)
Source
Timer 1
Timer 2 or Port Interrupt
External Interrupt (EXTINT)
Timer 3 or Timers 3 & S
Receiver Interrupt
Transmitter Interrupt
Timer 4 or Timers 2 & 4
Timer S or Port 2 Handshaking
Interrupt Address Register
o
0
Interrupt Level
Indication
Port 15 -Timer 5 Trigger
(6R)
If TSC is set in the Mode Register enabling a retrigger/ilble timer, then Port 1S is the input which starts
and reloa~s Timer S.
Reading the interrupt address register transfers an
identifier for the currently requested interrupt level
on the system data bus. This identifier is the number
of the interrupt level multiplied by 4. It can be used
by the CPU as an offset address for interrupt handling. Reading the interrupt address register has the
same effect as a hardware interrupt acknowledge
INTA; it clears the interrupt request pin (INT) and
indicates an interrupt acknowledgement to the interrupt controller.
'
A high-to-Iow transition on P1S (Pin 34) loads the timer
with the saye register and starts the timer.
Port 16 -
Break-In Detect
If Break-In Oetect is enabled by BRKI in Command
Register 1, then this input is used to sense a BreakIn. If Port 16,is low while the serial transmitter is sending the last stop bit, then a Break-In condition is
, signaled.,
Port· 17
-
1 07 1 06 1 OS 1 04 1 03 1 02
(7R)
Port Interrupt Source
If BITI in Command Register 1 is set, then a low-tohigh tran$i,tion on Port 17 generates an.interrupt request on PrioTity lElvel 1.
Port 17 is edge triggered.
Receiver and Transmitter Buffer
01
00 ·1
(7W)
Both the receiver and t'ransmitter in the MUART ~re
double buffered. This means that the transmitter and
receiver have a shift register and a buffenegister.
The buffer registers' are ~i~ectly addressable by
reading or writing to register seven. After the. receiver
buffer is full, the RBF bit in the status register is $.et.
6-389
23075~1
8256AH
Reading the receive bl.!ffer clears ·the RBF statl!s bit.
The transmit buffer should be written to only if the
TBE bit in the status register is set. Bytes written to
the transmit buffer are held there until the transmit'
shift registec is empty, assuming eTS is low. If the
transmit buffer and ,shift register are empty, writing
to the transmit buffer immediately transfers the byte
to the transmit shift register. If a serial character
length is less than S btts: the unu$ed most significant
bits are set to zero when reading the receive buffer,
and are ignored when writing to the transmit buffer;
leads to· a count of X. *256 + 255. Timers count
down ·continuously, If the interrupt is enabled, it
occurs when the counter changes._from 1 to. O.
The timer/counter interrupts are automatically disabled when the interrupt request is generated.
Status Register
I I
I
liNT RBF TBE TRE
Port 1
I 07 I 06 I 05 I 04
03
02
01
00
(SW)
(SR)
Writing'to Port) sets the data in the Port 1 output
latch. Writing to an input pin does not affect the pin,
but the data is stored and will be output if the direction of the pin is changed later. If the pin is used as
a control signal, the pin will notbe affected, but the
data is stored. Reading Port 1 transfers the data in
Port 1 onto the data bus.
Port 2
I 07 I 06 I 05 104 ·1
DO
03
(9R)
(9W)
Writing to Port 2 sets the data in th~ Pan 2 output
latCh. Writing to an input p,n does not affect the pin,
but.it does store ~he ~ata in the lat<::h. Reading Port
2 puts the input pins onto the bus or the contents of
the output latch for outP!Jt pins. .
Timer 1·5
I
07 I 06
I ·05 1 04
'.
1 '03 ·1
02
01
001
Reading Timer N puts the contents of the timer onto
the data biJ~. Ifthe counter changes while RO is low,
the value on the data bus will not change. If two timers
are cascaded, reading the high-order byte will cause
the low-orc!er byte to be latched. Reading the loworder byte will unlatch them both. Writing to either
timer or decascading them also clears the latch condition:. Writing ttl a timer !lets the starting value of that
timer: If two timers are cascaded, writing to the highorder byte presets the low-order byte t«;l all o"'es.
, Loading only the high-order byte with a'value of X
I
I
BO
PE
(OF16R)
OE
FE
Reading the statiJs register gates its contents onto
the data bus. It holds the operational status of the
serial interface as well as the status of the interrupt
pin INT. The s~atus register can be read at any time.
The flligs are stable arid well defined at all instants.
FE - Framing Error ,Transmission
Mode'
,
Bit 0 can be used in two modes. Normally, FE indicates framing error which can be changed to
transmission mod,e indication by setting the TME bit
in the modification register.
If transmission mode is disabled (in Modification
Register), then FE indicates a framing error. A framing error is detected during the first stop bit. The error is reset by reading the Status Register or by a' chip
reset. A framing error does not inhibit the loading of
the Receiver Buffer. If RxO remains low, the receiver
will assemble· the next character. The false stop bit
is treated as the next start bit, and no high-to-Iow transition on RxO is required to synchronize the receiver.
When the TME bit in the Modification Registefis set,
FE is used to indicate that the transmitter was active
during the reception of a character, thus indicating
that the character received was transmitted by its own
transmitter. FE Is reset' when the transmitter is not
active during the recepti,on of character. Reading the
status register wiU not reset the FE bit in the transmissian mode.
OE - Overrun Error
If the user does nilt read the character in the Receiver'
Buffer before the next character is received and'
tranSferred to' this register, then the OE bit.is set. The
OE flag is set during the' reception of the,first stop
bit and is cleared when the Status"Register is read
or when a hardware or software reset occurs. The first
character received in this caSe
be lost.
6"390
will
230759-001
intJ
8256AH
PE - Parity Error
TBE' - Transmitter Buffer Empty
This bit indicates that a parity error has occurred during the reception of a character. A parity error is pre~
sent if value of the parity bit in the received character
is different from the one expected according to command word 2 bits 6 EP. The parity bit is expected and
checked only if it is enabled by command word 2 bit
7 PEN.
TBE indicates the Transmitter Buffer is empty and
is ready to accept a character. TBE is set by a chip
reset or the transfer of data to the Transmitter
Register, and is cleared when a character is written
to the transmitter buffer. When TBE is set, an interrupt requ,est is generated on Level 5 if enabled.
A parity error is set during the first stop bit and is reset
by reading the Status Register or by a chip reset.
BD -
Break/Break-In
The BD bit flags whether a break character has been
received, or a Break-In condition exists on the
transmission line. Command Register 1 Bit 3 (BRKI)
enables the Break-In Detect function.
Whenever a break character has been received,
Status Register Bit 3 will be set and in addition an
interrupt request on Level 4 is generated. The receiver
will be idled. It will be started again with the next highto-low transition at pin RxD.
The break character received will not be loaded into
the receiver buffer register.
If Break-In Detection is enabled and a Break-In condition occurs, Status Register Bit 3 will be set and
in addition an interrupt request on Level 5 is
generated.
The BD status bit will be reset on reading the status
register or on a hardware or software reset. For
more information on BreakIBreak"ln, refer to the
"Serial Asynchronous Communication" section of
AP-153 under "Receive Break Detect" and "BreakIn Detect." '
RBF - Receiver Buffer Full
RBF is set when the Receiver Buffer has been loaded with a new character during the sampling of the
first stop bit. RBF is cleared by reading the receiver
buffer or by a chip reset.
INT - Interrupt Pending
The INT bit reflects the state of the INT Pin (Pin 15)
and indicates an interrupt is pending. It is reset by
INTA or by reading the Interrupt Address Register if
only one interrupt is pending and by a chip reset.
FE, OE, PE, RBF, and Break Detect all generate a
Level 4 interrupt when the receiver samples the first
stop bit. TRE, TBE, and Break-In Detect generate a
Level 5 interrupt. TRE generates an interrupt when
TBE is set and the Transmitter Register finished
transmitting. The Break-In Detect interrupt is issued
at the same time as TBE or TRE.
'
Modification Register
o
IRS41 Rssl RS21 ~S1 I RSO I TME I DSC I
(OF1sW)
TRE - Transmit Register Empty
DSC - Disable Start Bit Check
When TRE is set the transmit register is empty and
an interrupt request is generated on Level 5 if enabled. When TRE equals 0 the transmit register is
in the process of sending data. TRE is set by a chip
reset and when the last stop bit has left the transmitter. It is reset when a character is loaded into the
Transmitter Register. if CTS is low, the Transmitter
Register wil!J2e loaded during the transmission of the
start bit. If CTS is high at the end of a character, TRE
will remain high and no character will be loaded into
the Transmitter Register until CTS goes low. If the
transmitter was inactive before a character is loaded into the Transmitter Buffer, the Transmitter
Register will be empty temporarily while the buffer
is full. However, the tlata in the buffer will be transferred to the transmitter register immediately and TRE
will be cleared while TBE is set.
DSC disables the receiver's start bit check. In this
state the receiver will not be reset if R~D is not low
at the center of the start bit. '
TME - Transmission Mode Enable'
TME enables transmissiOn mode and disables framing error detection. For information on transmission
mode see the description of the framing error bit in .
.
the Status Register.
RSO, RS1, RS2, RS3, RS4 Sample Time
Receiver
The number in RSn alters when the receiver samples
RxD. The receiver sample time can be modified only
if the receiver is not clocked by RxC.
6-391
23075&-001
inter
8256AH
\
Reset has no effect on the c,ontents of; receiver bl,l,fer register, transmitter buffer register, the intermediate latches of parallel ports, and event
coun!ers/timers, respectively.
NOTE:
.
The modification reg'ister cannot be read. Reading from address OFH, 8086: 1EH gates the contents of the status
.
,
register onto the data bus.,
Ahardware reset (reset, Pin 12) resets all modificationregister-bits to 0, i.e.:
'
• The start bit check is enabled.
• Status Register Bit 0 (FE) indicates framing error.
~ The sampling time of,the serial receiver is the bit
center.
A software reset (Command Word 3, RST) does not'
affect the modification register.
'
Hardware Reset
A reset signal on pin RESET (HIGH level) forces the
device 8256 into a well-defined initial state. This state
is characterized as follows:
1. Command registers 1, 2 and 3, mode register, Port
, J control register, and modification register are
reset. Thus, all bits of the parallel interface are set
to be inputs and event counters/timers are configured as independent 8-bit timers.
2. Status regist~r bits are reset with the exception of
bits 4 and 5. Bits 4 and 5 are set indic~ting tha,t
both transmitter register and transmitter buffer,
register are empty.
3. The interrupt maSk, interrupt request, and inter, rupt service register bits are reset and disable all
requests. As a consequence, interrupt signallNT
IS INACTIVE (LOW).
4. The transmit data output is set to the marking state
(HIGH) and the receiver section is disabled until
it i~ enabled by Command R~gister 3 Bit 6.
5. The start bit will be checked at sampling time. The
receiver wm'return'to start bit search mode if in~
'pul RxD is not LOW at this time.
-
6. St"tu~ Register ~it 0 implies framing error.
7. The receiver samples input RxD at bit center.
RS4 RS3 RS2 RS1
0
1 ' 1
0
1
1
0
1
1
0
1
1
0
1
0
1
0
0
0
1
0
0
1
0
0
0
1
0' 1
0
'0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
l'
1
1
1
0
,1
1
0
1 '1
0
1
1
0
1 ,0
1
1
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0,
0,
1
1
0
0'
RSO
Point of time between
start of bit and end of
bit measured in steps
of 1J:f2 bit length
1
0,
1
0
1
0
1
0
1
1 (Start of Bit)
2
3
4'
5
6
7
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
'1
0
1
0
1
0
8
9
10
11
12
13
14
15
16 (Bit center)
17
18
19
20
21
22
23
24
25
'
26
27
.
.
28
29
30
31
32 (End
of Bit)
/'
6-392
230759-001
8256AH
ABSO'LUTE MAXIMUM RATINGS *
Ambient Temperature Under Bias
OOC to 70°C
Storage Temperature
-65°C to -150°C
Voltage On Any Pin
With Respect to ground
-0.5V to -7V
Power Dissication
1 Watt
D.C. CHARACTERISTICS
Symbol
(TA-
"NOTICE: Stresses above those listed under. "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and
functional operation of the device at these or any other
conditions abov~ those indicated in the operational
sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect device reliability.
ooe to 70 e. Vee=
VIL
VIH
VOL
VOH
Parameter
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
ilL
Input Leakage
ILO
Output Leakage
lee
Vee SUPJ: y Current
0
Min.
-0.5
2.0
+5.0V
±
10%)
Max.
0.8
Vee+ 0.5
0.45
2.4
10
-10
. 10
-10
160
Units
V
V
V
V
~
~
Test Conditions
IOL= 2.5 mA
IoH= -400 ,IAA
VIN= Vee
VIN= OV
VOUT= Vee
VOUT= O.45V
mA
CAPACITANCE
Symbol
QN
ClIO
Parameter
Input Capacitance
1/0 Capacitance
lin.
Max.
10
20
,6-393
Unite
pF
pF
Teet COndhions
fc= 1 MHz
Unmeasured pins
returned to Vss
230759-001
intJ
825($AH
A.C. CHARACT~RISTICS.
, (TA = oDe to 700C, Vcc ~:
+5.0V:. ± ) 0%,
GND
::=
OV) ,
BUS PARAMETI;RS
8256AH
"
Symbol
tLL
. .Parameter
' ,
Min .
'
..
Units
Max.
tCSL
ALE Pulse Wldtn .
CS to ALE Setup Time
tAL
Address to ALE Setup Time
20
ns
ns
tLA
Address Hold Time After ALE
30
20
ns
tLC
ALE to
tCC
tRD
RD,
70
0
RDJ\Wt
WR, INTA Pulse Width
tPP
,tCR
'.
150
ns
ns
70
ns
200
ns
50
ns
25
..
ns
ns
180
500
ns
500
ns
2.2
lAs
1.1
lAS
1.1
/AS
/AS
2.5
·LOAD Pulse High Time Counter 5
LOAD P41se Low Time Counter "5
Counter 5' Load Before Next' Clock Pulse on P13
· External Count Clockt. to
Reflected in Count
ns
200
Data Valid from RD (1)
, "
Data Float After RD (2)
tDF
tOW
Data Valid to WR
tWO
Data Valid After WR
RD/.WR Control to Latch Enable
tCL
·ALE to Data Valid
tLDR
tRST
Reset Pulse Width
tRV
Recovery Time Between RDIWR
TIMER/COUNTER PARAMETERS
Counter Input Cycle Time (P12, P13)
tCPI
Counter Input Pulse Width High
tCPWH
tCPWL
Counter Input Pulse Width Low
. Counter Inpl,ltt to INn at Terminal Count
tTPI
tTIH
tTIL
ns
RD. to Ensure Clock is
tRC
Frnt to External Count Clockt to Ensure Clock
is not Reflected in Count
tCW
External Count Clockt ro WRt to Ensure Count
Written is Not Decremented
tWC
WAt to External Count Clock to Ensure Count
Written is Decremented
1.1
1.1
lAs:
lAS
1.1
'"2.2
lAs
0
ns
lAS
.
2.2
lAS
ns
0
INTERRUPT PARAMETERS
tDEX
EXTINn to ·INTt
tDPI
Interrupt request on P17t to INn
tPI
Pulse Width of Interrupt Request on P17
tHEA
INTAt or ROt to EXTINTt
tHIA
INTAt or ROt to INn
,
200
ns
2tCY
+500
ns
tCY+
100
ns
ns
30
300
6-394'
ns
23075~·OOl
8256AH
A.C. CHARACTERISTICS (continued)
SERIAL INTERFAcE AND CLOCK,PARAMETERS
8256AH
Symbol
Parameter
"
Min.
Max.
10,000
tCY
tCLKH
Clock Period
Clock High Pulse Width
195
65
Units
ns
65
ns
ns
tCLKL
Clock Low Pulse Width
tR
Clock Rise Time
tF
Clock Fall Time
tSCY
Serial Clock Period (4)
975
ns
tSPD
Serial Clock High (4)
350
ns
tSPW
Serial Clock Low (4)
350
tSTD
Internal Status Update Delay From Center of
Stop Bit (5)
tDTX
tlRBF
30
,j.IS
30
ns
ns
300
ns
TxC to TxD Data Valid
INT Delay From Center of First Stop Bit
300
2tCY
+500
ns
ns
tlTBE
INT Delay From Falling Edge of Transmit Clock at
end of Start Bit
2tCY
+500
ns
tCTS
Pulse Width for Single Character Transmission
0
ns
PARALLEL I/O PORT PARAMETERS
(6)
•
tWP
WR t to P1/P2 Data Valid
tPR
P1/P2 Data Stable, Before RD
tRP
tAK
P1/P2 Data Hold Time
tST
tPS
,
+(7)
300
ns
ns ,
ACK Pulse Width
50
150
Strobe Pulse Width
tSIB
ns
Data Setup to STB t
50
ns
ns
,
S'l'Bt
ns
50
tPH
Data Hold After
tWOB
tAOB
tSIB'
WR t to qBF t
250
ns
+OBF.
STB +to IBF +
250
ns
tRI
RD t to IBF t
250
ns
tSIT
STB t to INT
t
ns
tAil
ACK t to INT
t
2tCY
+500
2tCY
+500
tAED
OBF. to ACK
+Delay
AKC
NOTES:
,
1. CL = pF all outputs.
2. Measured from,logic "one" or "zero"
to 1.5" at CL = 150 pF.
"
,3. P12, P13 are external clock inputs, ,
4. Note that Rxe may be used as an input only
in 1X mode, otherwise it will be an output.
250
0
"
ns
ns
ns
5. The center of the Stop' Bit will be the receiver
sample"time, as programmed by the modification register.
6. 1/16th bit length for 32X, 64X; 100 ns for 1X.
7. To ensure t RO spec is met.
6-395
230759-001
inter
WAVEFORMS
A.C. TESTING INPUT, OUTPUT WAVEFORM
U=>e
A.C: tEsnNG LOAD aRCUIT
INPUT/OUTPUT
,
0.45
2.0'
2.0
TEST POINTS
0.8
0.8
DEVICE
'UNDER
TEST
)C
,
,
NOTES:,
,
A.C. testing: inputs are driven at 2.4V for a logic "1" and
O.45V for a logic "0". timing measurements are made at 2.0V
for a logic "1" and O.BV for a logic "0".
~ ',.'"''
NOTES:
Cl - 150 pF
Cl includes jig capacitance
SYSTEM CLOCK
ClK
. WRITE CYCLE '
READ CYCLE
DATA
6~96
230759001
inter
8256AH
WAVEFORMS (Continued)
PARALLEL PORT HANDSHAKING - INPUT MODE
II
P 20-27
11
.,
P
,
"
(IBF)
INT
:~:7
:::::::::::::::::::::11:X__...Jr.:X ~:~:; >-
PARALLEL PORT HANDSHAKING - OUTPUT MODE
DB~7:X ~m
X
::
Af1.3
::X-__>--
~-------~!----~I.!--------------P"
(OBF)
(ACK)
INT
WOR RD
_ _______.;".'WP~
OUTPUT
II
-
_ _ _ _ _X~ATA VALID
fl
P20-27
6-397
230759·001
8256AH
COUNT PULSE TIMINGS
P12 - P13
(COUNTER INPUT)
INT
LOADING TIMER (OR CASCADED COUNTER/TIMER 3 AND 5)
P13
(COUNTER INPUT)
ZERO COUNT
P15
(COUNTER INPUT)
f 4 - - - - - tT I L - - - - - . . I
INT
TRIGGER PULSE FOR TIMER 5 (CASCADED EVENT COUNTER/TIMER 3 AND 5)
I
P15
(TRIGGER INPUT)
COUNTER TIMER TIMlt-iG
EXTERNAL CLOCK
(P12, P13)
twe
OUTPUT FROM PORT 1 AND PORT 2
DB
A
0-7
0-3
___-~-'x
DATA VALID
•
WR
OUTPUT
P10-17, P20-27
X _________
r~...:..-1
xt_~::::::::::::--------.::
" ....- - - - if
.
·6-398
230759-001
8256AH
\
INPUT FROM .PORT 1 AND PORT 2
>t
-'
INPUT
P10-17, P20-27 _ _ _ _ _ _
_
--:;::,'~q
_____________x
DB
0-7
AD-3
1<
_ _ _ __
}-----\.pDATA VALID
)>-------
INTERRUPT TIMING
EXTINT
INT
INTA OR
DB
Ro
0-7
A
0-3
__________--.Jx
DATA
)>----
CTS FOR SINGLE cHARACTER TRANSMISSION
RESET TIMING
RESET
.EXTERNAL BAUD RATE CLOCK FOR SERIAL INTERFACE
TxC
(64 X AND 32
BAUD RATE INPUT
6-399
230759-001
\
'
inter
8256AH
TRANSMITTER AND RECEIVER CLOCK FROM INTERNAL CLOCK SOURCE
f4--1/2 tCCY
TiC,RiC
I
.;r
"\1.-
(OUTPUT)
,I
1/2 tCCY.........
'\
tCCY= 1/BAUD RATE~
TRANSMISSION OF CHARACTERS ON SERIAL INTERFACE
STATUS
REGISTER
BIT 5 (TBE)
STATUS
REGISTER
BIT 4 (TRE)
INT
(LEVEL 5)
TxD
NOTES:
1.
2.
3.
4.
5.
6.
7.
Load transmitter buffer register.
Transmitter buffer register is empty:
Transmitter register is empty.
.
.
Character format for this example: 7 Data Bits with Parity Bit and 2'Stop Bits.
Loading of transmitter buffer register must be complete before CTS goes low.
Interrupt due to transmitter buffer register empty.
.
Interrupt due to transmitter register empty.
No Status bits are altered when RD is active.
DATA BIT OU1PUT ON SERIAL INTERFACE
TxC
(1 x BAUD RATE INPUT)
TxC
(64 x BAUD RATE INPUT)
TxC
(32 x BAUD RATE INPUT)
TxD
I....- - - - - D A T A BlT----~-.j
6-400
230759-001
8256AH
CONTINUOUS RECEPTION OF CHARACTERS ON SERIAL INTERFACE WITHOUT ERROR CONDITION
CHARACTER
RxD
1)
WR
2)
'CHARACTER
CHARACTER
CHARACTER
CHARACTER
COMMAND
REGISTER
BIT 6 (RxE)
STATUS
REGISTER
BIT 6 (RBF)
INT
(LEVEL 4)
4)
RECEIVER ENABLE
RECEIVER DISABLE
CHARACTER
CHARACTER
CHARACTER
NOTES:
. 1.
2.
3.
4.
Character format for this example: 6 data bits with parity bit and one stop bit
Set or reset bit 6 of command register 3 (enable receiver).
Receiver buffer located.
Read receiver buffer register.
ERROR CONDITIONS DURING RECEPTION OF CHARACTERS ON THE SERIAL INTERFACE
CHARACTER
RxD
CHARACTER
CHARACTER
CHARACTER
CHARACTER
1)
STATUS
REGISTER 2)
BIT 6 (RBF)
INT
(LEVEL 4)
STATUS
REGISTER
BIT 1 (OE)
3)
------++-----'
STATUS
REGISTER
BIT 0 (FE)
NOTES:
1.
2.
3.
4.
5.
6.
7.
FRAMING ERROR
.
Character format for this example: 6 data bits without parity and one stop bit
Receiver buffer register loaded.
Overrun error.
Framing error.
Interrupt from receiver buffer register loading.
Interrupt from overrun errOL
Interrupt from framing error and loading receiver buffer register.
No status bits are altered when AD is active.
6-401
230759-001
,.
·8279/8279·5
. PR,OGRANI.MABLE KEYBOARD/DISPL.AY INTERFACE
,
':'.
~'.
"
,. Simultaneous 'KeYboard Display
Operations
• Slrigle16.Character Display
• Scanned Keyboard Mode
, • Right or Left Entry 16-Byte, Display
.
RAM
• Scanned Sensor Mode
.• 'Mode Programmable from CPU
• Strobed Input Entry Mode
.• Programmable Scan Timing
• a-Character Keyboard FIFO
• Interrupt Output on Key Entry
• 2-Key Lockout or N-Key Rollover with
Contact Debounce
• Dual 8-or 16·Numerlcal Display
• Available in EXPRESS
-Standard Tempera.ure Range
-Extended 'n!mperature Range
'1he Intel" 827g.ls a gene~al purpose programmable keyboard and display I/O interface device designed for use with
Intel" microprocessors. The keyboard portion can provide a scanned Interface to a 64-contact key matrix. The
keyboard portion will also Interface to an array of senso~s or a strobed interface keyboard, such as the hall effect and
ferrite variety. Key depressions can be 2-key lockout or N-key·'rollover. Keyboa'rd entries are debounced and strobed in
an 8-character FIFO. If more than 8 characters are entered, overrun status is :tiel. Key entries set.the interrupt output
line to the CPU.
The display portion provides a scanned display interface for LED, Incandescent, and other popular display
technologies. Both numeric and alphanumeric segment displays may be used as well as simple Indicators. The 8279.
has 16)(8 display RAM which can be organized Into dual 16X4. The RAM can be loaded or interrogated by the CPU. Both
right entry, calculator,and left entry typewriter display formats are possible. ,aQth 'read and write of the display RAM
.can be done. witl1: fu.to-il1crement of the display RAM address,. .
" ,
'
--'---lIRa
SH .. T I - - - - KE~ DATA
- - - ' I RD
CPU
INTERFACE
SL03
t----v"
SCAN
---~IAo
l--
OUT Ao3
RESET
elk
t----v"
OUTB03t--_-V
DISPLAV
DATA
v..." -_ _"""
v..
FIgure 1. logic Symbol
Figure 2. .Pln Co"flguratlc;»n . '
.6-402
inter
827918279·5
HARDWARE DESCRIPTION
The 8279 is packaged in a 40 pin DIP. The following is
a functional description of each pin."
18ble 1. Pin DeicrlpUona
Pin
Symbol
Pin
No.
DBO"D~
8
Bkllrecllonal da.. bus: All data
and commands between the CPU
and the 8279 are transmitted on
these lines.
CLK
1
Clock: Clock from system used to
generate internal timing.
RESET
1
Name and Function
No.
Name and Function
SHIFT
1
Shift: The ,shift Input statlls Is,
stored along with the key poSition
on key closure in the Scanned Keyboard modes. It has an active Internal pullup to keep It high until a
switch closure pulls it low.
CNTUSTB
1-
ControII8trobed Input Mode: For
keybollrd modes this line Is used
as a control input and stored like
atatus on a key closure. The line
is also the strobe line that enters,
the data Into the FIFO in the
Strobed Input mode.
Symbol
Rnet: A high signal on'thls pin resets the 8279, After being reset the
8279 'Is placed in the following
mode:
1) 18 8-bit character display
-left entrY.
2) Encoded scan ke~board-2
key lockout.
Along with this the program clock
prescaler Is sat to 31.
CS
Ao
1
1
(Rising Edge). It has an active Internal puUup to keep it high until
a switch closure puUs It low.
Chip Select: A low on this pin enables the Interface functions to
receive or transmit.
OUTAo-OUT~
OUT Bo-OUT B3
4
4
Output8: These two porta are the
outputs for the 18 x 4 dlspley refresh registers. The data from
these outputs Is synchronized to
the scan lines, (SLo-S~) for multiplexed digit displays. The two 4
bit ports may be blanked independently. These two porta may
also be considered as one 8-bit
port.
BD
1
Blank Display: This output is
used to blank the display during
digit switching or by a display
blanking command.
Buffer Addres.: A high on this
line indicates the signals in or out
are interpreted
a command or
status. A low indicates that they
are data.
as
RD,WR
IRQ
2
1
Input/Output Read and Write:
These signals enable the data
buffers to either send data to the
external bus or receive it from the
external bus.
Interrupt Request: 'In a keyboard mode. the .Interrupt line Is
high when there is data in the
FIFO/Sensor RAM. The Interrupt
line goes low with each FIFO/
Sensor RAM read and returns
high If there Is stili Information in
,the RAM. In a sensor mode, the
Interrupt line goes high whenever
a change in a sensor is datected.
Vss, Vcc
2
Ground and power supply pine.
SLo-S~
4
Scan Unes: Scan lineS which are
used to 'scan the key switch or
lIensor matrix and the display
digits. These lines can be either
encoded (1 of 18) or decoded (1
of 4).
RLo-RL1
8
Return Line: Return line Inputs
which are co'nnected to the scan
lines through the .keys or sensor
,SWitches. They have active internal
pullups to keep them high until a
switch closure pulls one low. They
also serve as an 8-blt input In the
Strobed Input mode.
FUNCTIONAL DESCRIPTION
Since data input and display are an integral part of many
microprocessor deSigns, the system designer needs an
, interface that can contrbl these functions without placing
'a large load on the CPU, The 8279 provides this function
for ,8-bit microprocess~rs.
The 8279 has two sec;'tions: keyboard and display, Th.
Keyboard section can interface to regular' typewriter style
keyboards or random toggle or thumb switches. The
display section drives alphanumenc displays or a bank of
indicator lights. Thus the CPU IS r.elieved from scanning
the keyboard or refreshing the display.
'
The 8279 Is designed to directly' connect to the
microprocessor bus. Tile CPU can program ali operating
modes fo~ the 8279. These modes include:
6-403
inter
8279/8279-5 '
PRINCIPLES OF OPERATION
Input Mode.
• Scanned Keyboard - with encoded (8 x 8 key
keyboard) or decoded (4 x 8 key keyboard) scan lines.
A key depression generates a 6-bit encoding of key
position. Position and shift and control status are
stored in the FIFO. Keys are automatically debounced
with 2-key lockout or N-key rollover.
The following is a descripti.on of the major elements of the
8279 Programmable Keyboard/Display interface device.
'. Refer to the block diagram in Figure 3.
1/0 Control and Data Buffers
• Scanned Sensor Matrix - with encoded (8 x 8 matrix
switches) or decoded (4 x 8 matrix switches) scan nnes.
Key status (open or closed) stored in RAM addressable
by CPU.
The 1/0 control section uses the CS. A.a. RD and WR lines
to control data flow to and from the various internal
registers and buffers. All data flow to and from the 8279 is
enabled by CS. The character of the information. given or
desired by the CPU. is identified by Ao. A logic one
means the information is a command or status. A logiC
zero means the information is data. RD and WR determine
the direction of data flow. through the Data Buffers. The
Data Buffers are bi-directional buffers that connect the
internal bus to the external bus. When the chip is not
'selected (CS = 1). the devices are l!!.. a high impedance
state. The drivers input during ijij'R. CS and output during
RD-CS,
• Strobed Input - Data on return lines during control
line strobe is transferred to' FIFO.
Output Mode.
- 8 or 16 character multiplexed displays that can be organized as dual 4-bit or single 8-bit (Bo Do. A3 07)'
=
=
• Right entry or left entry display formats.
Other features of the 8279 include:
• Mode programming from the CPU,
Control and Timing Regl.ters and Timing Control
• Clock Prescaler
• Interrupt output to signal CPU when there is keyboard
or sensor data av\ailable.
These registers store the keyboard and display modes and
other operating conditions programmed by the CPU. The
modes are programmed by presenting the proper
command on the data lines with Ao = 1 and then sending
a WR, The command is latched on the rising edge of WR.
• An 8 byte FIFO to stor,e keyboard information
• 16 byte internal Display RAM for display refresh. This
RAM can also be read by the CPU
eLK
RESET
DIlO-7
IRQ
KEYBOARD
DEBOUNCE
AND
CONTROL
OUT AO.3
our 80-3
Figure 3_ Internal Blo«k Diagram
6-404
AFN-00742B
inter
8279/8279·5
The command is then decoded and the appropriate
function is set. The timing control contains the basic
timing counter chain. The first counter is a + N prescaler
that can be programmed to yield an, internal frequency,
of 100 kHz which gives a 5.1 ms keyboard scan time and
a 10.3 ms debounce time. The other counters divide
down the basic internal frequency to provide the proper
key scan, row scan, keyboard matrix scan, and display
scan times.
SOFTWARE OPERATION
8279 commands
The following commands program 'the 8279 operating
modes. The commands are sent on the Data Bus with CS
low and Ao high and are loaded to the 8279 on the rising
edge of WR.
Keyboard/Display Mode Set
MSB
Scan Counter
The scan counter has tv:.o modes. In the encoded mode.
the counter provides a binary count that must be
externally decoded to provide the scan lines for the
keyboard and display. In the decoded mode, the scan
counter decodes the least significant 2 bits and provides a
decoded 1 of 4 scan. Note than when the keyboard is In
decoded scan, so is the display. This means that only the
first 4 characters in the Display RAM are displayed.
In the encoded mode: the scan lines are active high
outputs. In the decoded mode, the scan lines are active
low outputs.
Code:
LSB
101010iDIDIK IKIKI
Where DD is the Display Mode and KKK is the Keyboard
Mode.
DO
o
o
0
8 8-bit character display -
1
16 8-bit character display -
o
8 8-bit character display 16 8-bit character display -
Return Buffers and Keyboard Debounce
and Control
The 8 return lines are buffered and latched by the Return
Buffers. In the keyboard mode, these lines are scanned,
looking for key closures in that row If the debounce
circuit detects a closed sWitch, it waits about 10 msec to
check if the switch remains closed. If it does, the address
of the switch in the matrix plus the status of SHIFT and
CONTROL are transferred to the FIFO In the scanned
Sensor Matrix modes, the contents of the return lines is
directly transferred to the correspon1lng row of the
Sensor RAM (FIFO) each key scan time In Strobed Input
mode, the contents of the return lines are transferred to
the FIFO on the rising edge of the CNTUSTB line pulse
Display Address Registers and Display RAM
The Display Address Registers hold the address of the.
. word currently being written. or read by the CPU and the
two 4-bit nibbles being displayed The read/write
addresses are programmed by CPU command. They also
can be set to auto Increment after each read or write. The
Display RAM Cdn be directly read by, the CPU after the
correct mode and Mc!ress IS set. The addresses for the A
and B nibbles are .'lJtomatlcaHy updated by the 8279 to
match data entry by the CPU. The A and B nibbles can be
entered independently or as one word, according to the
mode that is set by the CPU Data entry to the display can
be set to either left or right entry. See Interface
Considerations for details.
Left entry'
Right entry
Right entry
For description of right and left entry, see Interface
Considerations. Note that when decoded scan IS set in
keyboard mode, the display IS reduced to 4 characters
independent of display mode set.·
KKK
0
0
0
Encoded Scan Keyboard -
0
0
1
Decoded Scan Keyboard - 2-Key Lockout
0
Encoded Scan Keyboard - N-Key Rollover
0
Encoded Scan Sensor MatriX
1
Decoded Scan Sensor MatriX
0
Strobed I nput, Encoded Display Scan
0
2 Key Lockout'
Decoded Scan Keyboard - N-Key Rollover
0
0
0
FIFO/Sensor RAM and Status
This block is a dual function 8 x 8 RAM In Keyboard or
Strobed Input modes, It is a FIFO Each new entry IS
written into successive RAM posItions and each IS then
read ,in order of entry. FIFO status keeps track of the
number of characters In the FIFO and whether It IS full or
empty. Too many reads or writes Will be recognized as an
error The status can be read by an RD with CS low and
Ao high. The status logic also provides an IRQ signal
when the FIFO IS not empty. In Scanned Sensor Matrix
mode, the memory IS a Sensor RAM. Each row of the
Sensor RAM IS loaded with the status of the correspond• ing row of sensor in the sensor matrix. In this mode, IRQ is
high if a change In a sensor is detected.
Left entry
Strobed Input, Decoded Display Scan
Program Clock
Code:
I
0I
0 11 I pip I pip I p
I
All timing and multiplexing signals for the 8279 are
generated by an internal prescaler. This prescaler
divides the external clock (pin 3) by a programmable
integer. Bits PPPPP determine the value of this integer
which ranges from 2 to 31. Choosing a divisor that yields
100 kHz will give the specified scan and debounce
times. For instance, if Pin 3 of the 8279 is being clocked
by a 2 MHz Signal, PPPPP should be set to 10100 to
divide the clock by 20. to yield the proper 100 kHz operat·
ing frequency.
Read FIFO/Sensor RAM
Code:
I
0 'f 1
I IAI IX IA IA IA I
0
X = Don't Care
The CPU sets up the 8279 for a read of the FIFO/Sensor
RAM by first writir;.9 this command. In the Scan Key'Default after reset
6-405
AFN.flO742B
8279/8279·5
board Mode, the Auto-Increment flag (AI) and the RAM
address bits (AAA) are irrelevant. The 8279 will automatically drive the data bus for each subsequent read (Ao = 0)
in the same sequence in which the data first entered the
FIFO. All subsequent reads will be from the FIFO until
~nother command is issued.
Clear
r~ '~'
1
Read Display RAM
I 0 11 11 I
AliA
1 A 1A 1A
Write'Dlsplay RAM
11 1 0 1a 1AliA 1 A 1 A IA I
The CPU sets up the 8279 for a write to the Display RAM
by first wJiting this command. After writing the command with Ao = 1, all subsequent writes with Ao = 0 will
be to the Display RAM. The addressing and AutoIncrement functions are identical to those for the Read
Display RAM. However, this command does not affect
the source of subsequent Data Reads; the CPU will read
from whichever RAM (Display or FIFO/Sensor) which
was last specified. If, indeed, the Display RAM was last
specified, the Write Display RAM will, nevertheless,
change the next Read location.
Display Write Inhibit/Blanking
Code:
1
I
The CPU sets up the 8279 for a read of the Display RAM
by first writing this command. The address bits AAAA
select one of the 16 rows of the Display RAM. If the AI
flag is set (AI = 1), this row address will be incremented
after each following read or write to (he Display RAM.
Since the same counter is used for both reading and
writing, this command sets the next read or write
address and the sense of the Auto-Increment mode for
both operations. '
Code:
F
The Co bits are available in this command to clear all
rows of the Display RAM to a selectable blanking code
as follows:
'
In the Sensor Matrix Mode, the RAM address bits AAA
select one of the 8 rows of the Sensor RAM. If the AI flag
is set (AI = 1), each successive read will be from the subsequent row of the sensor RAM.
Code:
11 11 I0 ICo ICD ICol C ICA I
Code:
A B A B
11 10 11 1X IIW Ilw I BL 1BL 1
The IW Bits can be used to mask nibble A and nibble B
in applications requiring separate 4-bit display ports. By
setting the IW flag (IW= 1) for one of the ports, the port
becomes marked so that entries to the Di$'play RAM
from the CPU do not affect that portThus, if each nibble
is input to a BCD decoder, the CPU may write a digit to
the Display RAM without affecting the other digit being
displayed. It is important to note that bit Bo corresponds
to bit Do on the CPU bus, and that bit A3 corresponds 'to
bit 0 7,
If the user wishes to blank the display, the BL flags are
available jor each nibble. The last Clear command issued
determines the code to be used as a "blan'k." This code
defaults to all zeros after a reset. Note that both BL
flags must be set to blank' a display formatted with a
single 8-bit port.
All
"ro, IX • 000''';''''
0
AB = Hex 20 (0010 0000)
1
All Ones
Enable clear display when
= 1 (or by CA = 1)
During the time the Display RAM is being cleared ("'160 /,s),
it may not be written to. The most significant bit of the
FIFO status word is set during this time. When the Display RAM becomes available again, it automatically
resets.
If the C F bit is asserted (C F = 1), the FIFO status is
cleared and the interrupt output line is reset. Also, the
Sensor RAM pointer is set to row O.
C A, the Clear All bit, has the combined effect of CD and
C F ; it uses the CD clearing code on the Display RAM and
also clears FIFO status. Furthermore, it resynchronlzes
the internal timing chain.
End Interrupt/Error Mode Set
Code:
For the sensor matrix modes this command lowers the
IRQ line and enables further writin9 into RAM. (The IRQ
line would have been raised upon the detection of a
change in a sensor value. This would have also inhibited
further writing into the RAM until resetl.
For the N-key rollover mode - If the E bit is programmed
to "1" the chip will operate In the special Error mode (For
further details. see Interface Considerations Section,)
Status Word
The status word contains the FIFO status, error, and
display tJnavailable signals. This word is read by the CPU
when Ao is high and CS and Ri5 are low, See Interface
Considerations for more detail on status word,
Data Read
Data is read when Ao, CS and AD are all low, The source
of the data is specified by the Read FIFO or Read Display
commands, Th~ trailing edge of RD wi,lI cause the address
of the RAM being read to 6e Incremented if·the AutoIncrement flag is set. FIFO reads always increment (if no
error occurs) independent of AI.
Data Write
Data that is written with Ao, CS and WR low is always
written to the Display RAM, The address is specified by the
latest Read Display cir Write Display command. AutoIncrementing on the rising edge of WR occurs if AI set by
the latest display command,
6-406
AFN·OO742B
intJ
8279/8279·5
INTERFACE CONSIDERATIONS
Scanned Keyboard Mode, 2·Key Lockout
Increment flag is set to zero, or by the End Interrupt
command if the Auto-Increment flag is set to one.
There are three possible combinations of conditions
that can occur during debounce scanning. When a key is
depressed, the debounce logic is set. Other depressed
keys are looked for during the next two scans. If none
are encountered, it is a single key depression and the
key "osition is entered into the FIFO along with the
status of CNTL and SHIFT lines. If the FIFO was empty,
IRQ wiil be set to signal the CPU that there is an entry in
the FIFO. If the FIFO was fuil, the key will not be entered
and the error flag wiil be set. If another closed switch is
encountered, no entry to the FIFO can occur. If ail other
keys are released before this one, then it wiil be entered
to the FIFO. If this key is released before any other, it
wiil be entirely ignored. A key is entered to the FIFO
only once per depression, no matter how many keys
were pressed aiong with it or in what order they were
released. If two keys are depressed within the debounce
cycle, it is a simultaneous depression. Neither key wiil
be recognized until one key remains depressed alone.
The last key wiil be treated as a single key depression.
Note: Multiple changes in the matrix Addressed by (SLo-3
= Ol may cause multiple interrupts, (SLo = 0 in the Decoded
Mode). Reset may cause the 8279 to see multiple changes.
Data Format
In. the Scanned Keyboard mode, the character entered
into the FIF.O corresponds to the position of the switch
in the keyboard plus the status of the CNTL and SHIFT
lines (non-inverted). CNTL is the MSB of the character
and SHIFT is tile next most significant bit. The next
three bits are from the scan counter and indicate the
row the key was found in. The last three bits are from the
column counter and indicate to which return ilne the key
was connected.
MSB
LSB
~ETUR~
SCANNED KEYBOARD DATA FORMAT
In Sensor Matrix mode, the data on the return lines is
entered directly in the row of the Sensor RAM that
corresponds to the row in the matrix being scanned.
Therefore, each switch postion maps directly to a Sensor
RAM position. The SHIFT and CNTL inputs are ignored in
this mode. Note that switches are not necessarily the only
thing that can be connected to the return lines in this
mode. Any logic that can be triggered by the scan lines
can enter data to the return line inputs. Eight multiplexed
input ports could be tied to the return lines and scanned by
the 8279.
Scanned Keyboard Mode, N·Key Rollover
With N-key Rollover each key depression is treated
independently from all others. When a key is depressed,
the debounce circuit waits 2 keyboard scans and then
checks to see if the key is still down. If it is, the key IS
entered into the FIFO. Any number of keys can be
depressed ~nd another can be recognized and entered
into the FIFO. If a simultaneous depression occuts, the
keys are recognized and entered according to the order
the keyboard scan found them.
Scanned Keyboard - Special Error Modes
MSB
For N-key rollover mode the user can program a special
error mode. This is done by the "End Interrupt/Error Mode
Set" command. The debounce cycle and key-validity
check are as in normal N-keyo mode If during a single
debounce cycle, two keys are found depressed, thiS is
considered a simultaneous multiple depression, and sets
an error flag. This flag will prevent any further writing Into
the FIFO and will. set interrupt (if not yet set). The errorflag
could be read in this mode by reading the FIFO STATUS
word. (See "FIFO STATUS" for further details.) The error
flag is reset by sending the normal CLEAR command with
CF = 1.
RL7! RL6! RL5! RL4! RL3! RL2! RL, ! RLo
In Strobed Input mode, the data IS also entered to the FIf:O
from the'return lines. The data is entered by the rising
edge of a CNTLlSTB line pulse. Data can come from
another encoded keyboard or simple switch matrix. The
return lines can also be used as a general purpose strobed
input.
Mse
RL7! RL61 RL51 RL41 RL31 RL21 RL,
Sensor Matrix Mode '
In Sensor Matrix mode, the debounce logic is inhibited.
The status of the sensor switch is Inputted directly to the
Sensor RAM. in this way the Sensor RAM keeps an image
of the state of the switches in the sensor matrix. Although
debouncing is not provided, this mode has the advantage
that the CPU knows how long the sensor was closed and
when it was released. A keyboard mode can only indicate
a validated closure. To make the software easier, the
designer should functionally group the sensors by row
since this is the formlit In which the CPU will read them.
The IRQ line goes high if any sensor value change is
detected at the end of II sensor matrix scan, The IRQ line is
cleared by the first data read operation if the Auto-
LSB
. LSB
I
RLo
Display
Left Entry
Left Entry mode is ~he simplest display format in that each
display position directly corresponds to a byte (or nibble)
in the Display RAM. Address 0 in the RAM is the left-mllst
display character and address 15 (or address 7 in 8
character display) is the right most display character.
Entering characters from position zero causes the display
to fill from the left. The 17th (9th) character is entered back
in the left most position and filling again proceeds from
there.
6-407
AFN-00742B
intJ
8279/8279-5
o
1
lst entry
[TI ====OJ =:d~ess
2nd entry
C2:0 -,"' - '- IT]
o
o
16th entry
14 15
===EEJ
~= =
==EEl
~= =
==EEJ
o
,18th entry
1
1
1
1 2. 3 4
II
1st entry
l' I
2nd entry
1'121
14 15
1
5 6
I
7'-Display
I' I
1
=~~es:
01234567,
'
o
~=
o
17th entry
1
o
14 15-_Display
Qlmmand
10010101
14 15
1111I
1 2 3
4 5 6
7
l' 12 1 I I, I I I
Enter, next at Location 5 Auto Increment
o
14 15
1
2' 3
4
5
6
7
3rde\ltry
1'1211113111
4th entry
l' 12 I I
012345,t17
LEFT ENTRY MODE
(AUTO INCREMENT)
1 1 3 14
I
LEFT ENTRY MODE
(AUTO INCREMENT)
Right Entry
'In the Right Entry mode, Auto Incrementing and non
Incrementing have the same effect as in the Left Entry
except if the address sequence is interrupted:
Right ,entry IS the method used by most electronic
calculators, The first entry is placed in the right most
display character, The next entry is also placed in the right
most character after the display is shifted left one
character, The left most character IS shifted off the end
and is lost
1 2 3 4
1st entry
1
1 1
5 6
7 0 -4- DISplay
I II
11 I
=~~ess
23456701
1st entry
II
!
2nd entry
11
121
234 5 6 7 0
2nd entry
Qlmmand
10010101
3
3rdentry
4
0
[1]= ===
1
2
1 11 2 13
1
11 121
Enter next at LocatIon 5 Auto Increment
1
34567012
45670123
02:[ ===
1 2
;7th entry
4th entry
13141
1151161171
2
18th entry
14':15 0
3
~=
===
15 0
I
11 \2\
1
RIGHT ENTRY MODE
(AUTO INCREMENT)
1
Starting at an arbitrary location operates as shown t:'.3low:
1161171'81
o
RIGHT ENTRY MODE
(AUTO INCREMENT)
Command
10010101
1 2 3 4 5 6 7-4-D,splay
II
I 1 -I I
1 1
I =:d~ess
Enter next at Location 5 Autp Increment
Note that now the display position and register address do
not correspond, Consequently, entering a -character to an
arbl,trary position in the Auto Increment mode may have
unexpected results, Entry starting at Display RAM address
o with sequential entry IS recommended,
1
2' 3
6' 7
0
2nd entry
1I
8th entry
14151617181,12131
9111, entry
15' 16171819121, 3 141
2 ' 3, '4
6-408
5
I \ \ \ 11 I
Auto Increment
In the Left Entry mode, Auto Incrementing causes the
address where the CPU will next write to be Incrernented '
by one and the character appears in the next loclltion,
With non~Auto Incrementing the entry is hoth to the same
RAM address and display position, Entry to an arbitrary ,
address iii the Auto Increment mode has no undesirable
side effects and the result is predictable:
4
lst entry
5
6
I'll' 2\
7
I I 1
0
1
1 1
RIGIi:r EN:rRY MODE
(AUTO INCREMENT)
8279/8279·5
Entry appears to be from the initial entry point.
In a Sensor Matrix lJlode, a bit Is set in the FIFO status
word to Indicate that at least one sensor closure Indica·
tion Is contained In the Sensor RAM.
8/16 Character Dllplay Formatl
In SPElcial Error Mode the S/E bit Is showing the error
flag and serves as an Indication to whether a slmultane·
ous multiple closure error has occurred.
If the display mode is set to an 8 character display. the on
duty-cycle is double what it would be for a 16 character
display (e.g .. 5.1 ms scan time for 8 characters'vs. 10.3 ms
for 16 characters with 100 kHz internal frequency).
FIFO STATUS WORD
G. FIFO StatuI
FIFO status is used in the Keyboard and Strobed' Input
modes to indicate the number of characters in the FIFO
and to indicate whether an error has occurred. There are
two types of errors possible: overrun and underrun:
Overrun occurs when the entry of another character into a
full FIFO is attempted. Underrun occurs when the OPU
tries to read an empty FIFO.
Number of
characters in FIFO
L..~_ _
L-_ _ _ _
The FIFO status word also has a bit to indicate that the
Display RAM was unavailable because a Clear Display or
Clear All command had not completed its clearing
operation.
Error-Overrun
Sensor Closure/Error Flag for
Multiple Closures
Display unavailable
KEYBOARD
SHIFT
MATRIX
CONTROL
s/
8 COLUMNS
RETURN
8 ROWS
LINES
HS
5V
INT
SHIFT CNTL
INT
"oD
vssll.
DATA BUS
S·BIT
MICRO-
PROCESSOR
SYSTEM
DATA
BUS
S/
AD
CONTROLS {
ADORESS{
BUS
CLOCK
WR
RESET
cs
Ao
CLK
0 0 _1
iOli
iliW
I
Ro·,U
3 - 8 DECODER
V
ov
So.3
8279
4/
SCAN LINES
3 LSB'
(j4
RESET
H.
4--16 DECODER
CS
AO
ClK80~3
r~~~~~Y
80
4
ADDRESSES
IDECODED) ,
DISPLAY
4
/
CHARACTERS
DATA
DISPLAY
'00 not drive the keyboard decoder wiih the MSB of the scan lines,
Figure 4. System Block Diagram
6-409
AFN-oG7428
inter
~BSOLUrE MAXIMUM ~A~"NGS*.·
"NOTICE: Stresses above those listed under "Abseilute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or a~y other conditio,ns above
those indicated In the operational sections of this specificatIon Is ·not implied. Exposure to absolute maximum
rating ·conditlons for extended periods mayaffectd,evice
reliability.
Ambient Temperatu~ ;..•• ':'•• , ••• :.••' O~Cto 70·C
Storage' Temperatu~e : .' •••••••• :'.•• -65°C to 125"C .
.
.'
Voltage on any Pin with .'
Respect to Ground •••••••••••••• -0.5V to +7V
Power Dissipation •••• .' ••••••••••••••••• 1 Watt
D.C. CHARACTERISTICS {TA '" O"C!O 70"C, Vss =
Ov. (NOTE 3)]*
Symbol
Parameter
·Mln.
Max.
Unit
VIL1
Input Low Voltage for
Return ~ines
-0.5
1.4
V
VIL2
Input Low Voltage for All Others
-0.5
O.B
V
Test ConditionS
I
I
I
Input High Voltage for
Return Lines
2.2
VIH2
Input High Voltage for All Others
2.0
VOL
Output Low Voltage
VOHl
Output High Voltage on Interrupt
Line
3.5
VOH2
Other Outputs
2.4
IILl
Input Current on Shift, Control and
Return Lines
+10
-100
JJA
JJA
VIN
VIN =OV
IIL2
Input Leakage Current on All Others
±10
JJA
VIN = Vcc to OV
IOFL
Output Float Leakage
±10
JJA
VOUT = Vee to 0.45V
Icc
Power Supply Current
120
mA
VIH1
f---- '
V
V
0.45
V
Note 1
V
Note 2
IOH
-4OO,.A 8279-5
8279
= -l00"A
= Vee
--
CAPACITANCE
Symbol
Parameter
CIN
CaUT
Typ.
Max.
Input Capacitance
5
10
pF.
Output Capacitance
10
20
pF
A.C. CHARACTI:RISTiCS [TA =
Unit
Test Conditions
fe. = 1 MHz Unmeasured
pins returned to VSS
O"C to 70"C. VSS = 9V. (Note 3)] "
Bus Paramete,.
READ CYCLE
. ,.8279
Symbol
Parameter
Min.
8279-5
Max.
Min.
Max.
Unit
tAR
Address Stable Before READ
50
0
ns
tRA
Add(ess Hold Time for READ
5
0
ns
tRR
READ Pulse Width'
tRO[4]
Data 'Delay fromR EAD "
tAO [4]
Address to Data Valid
tOF
READ to Data Floating' .
tRCY
Read Cycle Ti me
420
250
300
..
450
.:-
10
1
6-410
.'
"
100
10
1
ns
150
ns
250
' ns
100
ns
JJS
AfN.OO742B
\
intJ
8279/8279·5
A.C. CHARACTERISTICS (Continued)
WRITE CYCLE
8279
Symbol
Parameter
Min.
8279·5
Max.
Min.
Unit
Max.
tAW
Address Stable Before WR IT E
50
0
tWA
Address Hold Time for WRITE
20
0
tww
WR ITE Pulse Width
400
250
tow
Data Set Up Time for WR ITE
300
150
two
Data Hold Time for WR ITE
40
0
ns
tWCY
Write Cycle Time
1
1
J.lS
ns
ns
,
ns
ns
OTHER TIMINGS
8279
Symbol
8279·5
Parameter
Min.
tw
Clock Pulse Width
230
120
tCY
Clock Period
500
320
Keyboard Scan Time ........................ 5.1 msec
Keyboard Debounce Time .................. 10.3 n;Jsec
Key Scan Time .............................. 80 ILsec
Display Scan Time ......................... 10.3 msec
Max.
Min.
Max.
Unit
._---
nsee
nsee
---
Digit-on Time .............................. 480ILsec
Blanking Time ............................. 160 ILsec
Internal Clock Cycle[5] ....................... 10 ILsec
NOTES:
1.
2.
3.
4.
5."
•
8279. IOL = 1.6mA; 8279-5. IOL = 2.2mA.
IOH = -100/LA
8279. Vcc = +5V ±5%; 8279-5. Vcc = +5V ±1()%.
8279. CL = l00pF; 8279-5. CL = 150pF.
The Prescaler should be progr;immed to provide a 10 /LS internal clock cycle.
For Extended Temperature EXPRESS. use M8279A electrical parameters.
A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUT/OUTPUT
~=x >
2:0
TEST POINTS
0.8
<
2.0
0.8
0.45
A.C. TESTING LOAD CIRCUIT
x=
DEVICE
UNDER
TEST
'1CL~I20PF
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1" AND 0 45V FOR
A LOGIC '0" TI~ING MEASUREMENTS ARE MADE AT 2
AND 08V FOR A LOGIC '0"
ov FOR A LOGIC' 1"
Cl =120pF
CL INCLUDES JIG CAPACITANCE
6-411
AFN'()()742B
8279/8279·5
WAVEFORMS
READ OPERATION
,...-------------------"1' "'-_____________
(SYSTEM'S
ADDRESS BUSI
(READ CONTROLI
DATA BUS
(OU~UTl~~~~~~~~~~~~~_______________~~~~~~~~~~~~~
WRITE OPERATION
-JE
Ao, CS
W"
',
""
--tA-W----j-"-
I!f-o-.==~~~--~-'w-w====~~~~----~~~~________________
~
"'""-------t-o-w- - - ~ two
(SYSTEM'S
ADDRESS BUS)
(WRITE CONTROLI
'J --DATAVALID~I\I
DATA
-'p
'-Il\'-_____M_A_Y_C_H_AN_G_E_ _ _ _ __
DATA BUS
DATA
ClNPUTI_ _ _ _ _
M_A_Y_C_HA_N_G_E_ _ _
CLOCK INPUT
6-412
AFN-00742B
8279/8279-5
WAVEFORMS (Continued)
SCAN
L
S,
ENCODED
SCAN
L
L
S,
U
~U
S,
DECODED
SCAN
S,
S,
~
U
U
U
U
U
U
U
U
DISPLAY
640 j.4S
U
U
LI
U
Lr
PRE5CALER PROGRAMMED FOR INTERNAL FREQUENCY: 100 ·kHz SO
tey = 10~s
=84 ICY
S,
Ao-As
ACTive HIGH
A(')
BLANK
CODE·
A(')
BLANK
CODE"
*BLANK CODE IS EITHER ALL
O's OR ALL 1'. OR 20 HEX
BO-83
8(1)
ACTIVE HIGH
490 ... ----~_I_
Ala-RL7
NOTE: SHOWN IS ENCODED SCAN LEFT ENTRY
8a·Sa ARE NOT SHOWN BUT THEY ARE SIMPLY 81 DIVIDED BY 2 ANO 4
AFN-007428
82285,
CLOCK GENERATOR AND
READY INTERFACE FOR 1/0 COPROCESSORS
82285 is an 18 pin bipolar clock generator/driverdesigned to provide clock signals forthe 82730, 82586, or
other master peripherals. It also contains READY multiplexing logic to provide the required RDYO and
READY timing and synchronization for the peripheraf chips. RESETI,ogic with hysteresis and synchronization
is also provided.
.
• Uses crystal or TTL signal for Frequency
Source.
"
• Generates system reset output from
Schmitt nigger Input.
• Provides a 50% duty cycle peripheral
clock output with MOS drive
characteristics.
• Capable of clock synchronization with
other 82285's.
• Provides synchronous READY for peripherals from synchronous and/or
asynchronous sources.
RESET
ff 1+--------..,
i------------+-.RESET
SYNCHRONIZER
x,--+---I
»-.-+---t-- ClK
E F I - - t - - - -......
~c--~------~
CSYNe --1------1
I - - - - - - - - f -.......-+--i.. PClK
~L¥N--~----_----------------~
! - - -......---------+--+---i.. RDYO
!----------------t--.,READY
Figure,,1.
82285 Block Diagram
6-414
NOVEMBER 1983
ORDER NUMBER'230813-QOl
inter
82285
FUNCTIONAL DESCRIPTION
Aiii5Y
SiiDv
SiiiffiN
Vee
Aii6YEN
Clock Generator
CSYNC
PClKIN
RDYO
The ClK and PClK clock outputs may be generated either by an external crystal or by an external
TTL freqL!ency input. If the frequencylcrystal select
input (Fie) is high, the EFI input is used. If Fie is low,
a crystal attached to Xl and X2 pins is used. ClK is a
TTL output at the crystal or EFI frequency. PClK is a
MOS-Ievel output which has a 50% duty cycle,
. operates at 112 the ClK frequenC;y, and can be used
to d rive the clock inputs ofthe 82586, 82730, or other
devices.
READY
ClK
RESET
EFI
Fie
REs
PClK
Figure 2.
1.
2.
3.
4.
82285 Pin Configuration
NOTE
ClK is a TTL level output and has the same
frequency as either the crystal or EFI,
depending on the state of F/C.
PClK is a MOS level output and has half
the frequency of ClK.
ARDY and ARDYEN are interchangeable.
SRDY and SRDYEN are interchangeable.
Reset Logic
The reset logic provides a Schmitt Trigger input
(RES) and two synchronization flip-flops to synchronize the reset timing. The reset signal is synchronized at the falling edge of PClK IN. A simple
RC network can be used to provide power-on reset
of proper duration.
Table 1. Pin Description
Pin
Number
Type
Name and Function
RES
11
I
RESET IN: RES is an active low signal which is used to generate RESET. A Schmitt trigger input is provided so that a RC
connection can be used to establish the power up reset of
proper duration.
RESET
12
0
RESET: RESET is an active high Signal which is the synchron.
ized version of the RES input.
X1, X 2
7,8
I
CRYSTAL INPUT: X 1 and X 2 are attached to a parallel resonant, fundamental mode crystal. If Fie is strapped low to select
the internal oscillator as the clock source, ClK will be the
same frequency as the crystal, PClK will be '12 that frequency.
ClK
13
0
CLOCK: ClK is a TTL output and has the same frequency as
either the crystal or the external frequency input (EFI).
depend~nt upon the state of Fie.
PClK
10
0
PERIPHERAL CLOCK: PCLK is a clock output at h~f the frequency of the crystal input or EFI, depending on F/C input. It
provides MOS levels to drive the system ClK inputs of 82586
or 82730 or other device. PClK has a 50% duty cycle.
PCLKIN
15
I
PERIPHERAL CLOCK IN: PClK IN is a clock input which is
used for clocking the RESET flip-flops and the Al1r5Y' synchronizing flip-flop. It.can be driven by the PClK OiJtput or
some other system clock.
F/C
6
I
FREQUENCY/CRYSTAl SELECT: FIC is a strapping option.
When low, ClK and PCLK are generated from an external
crystal. When high, ClK and PClK are generated from the
EFI input.
Symbol
6-415
230813-001
inter
82285
'DIble 1. 'Pln Descrtptlon (Cont.) .
Pin
Number
Symbol
Type
Name and Function
EFI
5
I
EXTERNAL FREQUENCY IN: When FIC is strapped high,
CLK and PCLK are generated from the EFI input. CLK will be
the same frequency as EFI; PCLK will be half that frequency.
ARDYEN
17
I
ASYNCHRONOUS READY ENABLE: ARDYEN is ari
asynchronous active low input which qualifies A'RDY. Set up
anc;l hold times are given only to guarantee recognition on
that clock edge.
Am5Y
1
I
ASYNCHRONOUS READY: AJ:U)Y is an asynghronous active
low input which will be synchronized to provide the RDYO
output at the falling edge of PCLK IN. Setup and hold times
are given only'to guarantee recognition on that falling edge of
~ IN. The RDYO output will also be a function of the
SRDY input.
SRDYEN
3
I
SYNCHRONOUS READY ENABLE: SROYEN is a synchronous active low input which qualifieli SRi5Y.
SRDY
2
I
SYNCHRONOUS READY: SRDY is a synchronous active low
input. The RDYO outputs will also be a function of the ARDY
input.
4
0
SYNCHRONOUS READY OUT: RDYO is an active high . .
output which is either the SRDY input delayed, or the Am5Y
input synchronized. RDYO will be inactive (low) if the ready'
inputs are inactive (high).
.
READY
14
0
READY: READY is an active high output which is the RDYO
signal synchronized with theJalling edge of .PCLK output.
CSYNC
16
I
CLOCK SYNCHRONIZATION: CSYNC is used to provide
synchronization of PCLK's among multiple 82285's. The
source of CSYNC come from the PCLK output of the reference 82285. When synchronization is not used, CSYNC
should' be connected to Vee.
GND
9
-
Ground.
Vee
18
-.
+5Vsupply.
I
"
RDYO
,
tional ready signal in orderto optimize the operation
of systems using the 82730, 82586, and 8086.
'RDYO and READY Logic
RDYO is determined b~ synchronous ready input
~N or asynchronous ready
input ARDY qualified by ARDYEN. For the asynchronous input ARDY, it will be clocked in at the
falling edge of PCLK IN; and the RDYO output will
become valid at the same fallilb~gE! of PCLK IN,
provided ARDY is stable. The A
flip-flop Is used
as the first step In a two flip-flop synchronization
method for RDYO. For the synchronou~ input SRDY,
the RDYO output will become valid when SRi5Yis
stable.
'
WARNING:
SRDY'qualified by SRD
The RDYO output is not fully synchronized
when the asynchronous mode (Am5V) is used.
Clock Synchronization Logic
The READY output is the ROYO output latched at
the falling edge of·PCLk out. It provides an addi-
The clock synchronization logic allows the PCLK
signal of the device to be synchronized with the
P,CLK from other 82285's. A typical application of this
synchronization logic is shown in Diagram 5. Diagram 3 and 4 illustrates typical functional sequences,
of 82285..
6"-416 .
82285
PClK
RESET
Figure 3.
Reset Sequence
ClK
I
PClK
IN&OUT
AiiiiVEN --i-..,....,
SROVEN ___4-_____~-_r--------------
ROVO
REAOV _______________________
~
Figure 4.
Ready Operation
6-417
230813-001
82285
82285 #1
I
L
EFI
82285 #1
FIe
PClK
CSYNC
x,
PClK,
CRYSTAL
I
82285#2
ClK 1 - - - - 1 EFI
F/C
CSYN'i>ClK
82285 #2
EFI
L....,.
PClK,
PClK2
F/C PClK
CSYNC
Figure 5. TYpical Applictions of Clock Synchronization Among Multiple 82285's
ABSOLUTE MAXIMUM RATINGS·
•
Ambient Temperature Under Bias .......... O"C to 70"C
Storage Temperature .................. - 65"C to 150"C
Voltage on any Pin with Respect
'
, to Ground ............................ -O.5V to +7V
Power Dissipation ............................ 1.5 Watt
"NOTICE: Stresses above those listed under
"Absolute Maximum Ratings" may cause perma·
nent damage to the device. This is a stress rating
only and functional operation of the device at these
or any other conditions above those indicated in
the operational sections of this specification is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Electrical Characteristics and Waveforms
D.C. Characteristics for 82285
Conditions: TA = 0" C to 700 C; Vee = 5V ± 10%
Symbol
IF
Parameter
Forward Input Current
Min.
,
Max.
Units
-0.5
mA
For PCLK IN
-0.6
mA
For SRDYEN. SRDY
-0.85
'mA
IR
Reverse Input Current
50
f..IA
Ve
Input Forward Clamp voltage
-1.0
V
Icc
Power Supply Current
145
mA
V1L
Input "low" voltage
0.8
V
V1H
Input "high" voltage
2.0
V1HR
Reset input "hi9h" voltage
2.6
VOL
Output "low" voltage
VOH
Output "high" voltage PCLK
IOl
V
-1.05 mA
2:4
V
-1.05 mA
I
C1
10'
Input Capacitance
6-418
=5.25 mA
V
4.0
0.25
RES Input HYsteresis
= 0.45V
VF = 0.45V
VF = 0.45V
VR = Vee
Ie = -5 mA
V
0.45
Other outputs
, VIHR-V,LR
Test Conditions
VF
pF
,
230813-001
inter
82285
82285 A.C. Characteristics (Cont.)
Condition: TA = O°C to 70°C; Vee = %V
Symbol
± 10% (Note 1)
Parameter'
Min.
Max.
Units
tR
ClK and PClK rise time
10
ns
Note 2
tF
ClK and PClK fall time
10
ns
Note 2
tL
PClK IN and EFI low time
30
ns
lH
PClK IN and EFI high time
t,
elK low time
30
1/2 b-15
ns
ns
l2
ClK high time
1/2 b-15
ns
b
ClK cycle time '
56
ns
to.
PClK low time @ 0.6V
b-12.5
ns
PClK low time @ 1.5V
b-10
ns
ts
PClK high time @ 3.8V
b-17,5
ns
PClK high time @ 1.5V
b-10
ns
te
PClK cycle time
2b
ns
h
RES setup time to PClK INI
15
ns
Note 3, 4
ta
RES hold time from
10
ns
Note 3, 4
PClK INI
t9
PClK delay from ClK low
0
40
ns
t,o
RESET delay from PClK low
0
50
ns
t"
ARDYEN setup time to ARDY
0
ns
Note 4
t'2
ARDYEN hold time from
0
ns
Note 4
ns
Note 3, 4
ns
Note 3, 4
0
ns
Note 4
0
ns
Note 4
Am5Y
t'3
ARDY setup time to PClK INI
t'4
ARDY hold time from PClK INI
t,~
SRDYEN setup time to SRDY
t'6
SRDYEN hold time from
0
30
SR5Y
t'7
SRDY setup time to PClKI
50
ns
1,8
RDYOI delay from PClK INI
55
ns
ns
ns
t'9
RDYOI delay from AROYl
30
l20
RDYO
30
l2,
READYI delay from PClKI
-20
0
ns
t22
READYI delay from PClKI
-20
8
ns
delay from SRDY
Crystal frequency
17.6
4
MHz
Note 6
EFI frequency
D.C.
17.6
MHz
Note 5
(see notes next page)
\
6-419
230813-001
inter
NOTE
1. All times are measured at the 1.5V level unless specified otherwise ..
2. The rise and faJldimes for 9lK are measured b.etween O.8V and 2.0V (TTL level drive
characteristiCs). The rise and fall times for PClK are measured between 1.0Vand 3.5V (MOS level
drive characteristics).
'3. These are asynchronous inputs.
4. The setup and hold times are measured at the 0.8V and 2.0V levels forthe inputs and at 1.5Vfrom
the PClK signal.
.
5. To assure proper operation, the rise time or fall time of EFI cannotexceed 100 ns.
6. The specified timings are given in accordance with the maximum operating 1re quency of 17.6 MHz.
However, the device will be designed to operate to 24 MHz with a/l timing specs to be determined.
Loading:
For READY OUTPUT:
CL =30 pt, IOL =5.25 mA, IOH
For the ClK output:
CL =75 p1, IOL =5.25 mA, IOH
For the RDYO output:
.
Cl =75.p1, IOL =5.25 mA, IOH =-1.05 mA
For the PClK output:
CL = 175 p1, IOL = 5.25 mA, lo~ =-1.05 mA
All input capacitance will be:
Q = 10.p1
=-1.05 mA
=-1.05 mA
WAVEFO~MS.
eLK
REi
--_../
RESET
ARi5Y ----------,~
SADV
SRDYEN
RDVO
--------_--~
R~DV-----------------~
6:-420
230813-001
APPLICATIONS
. An Intelligent
Data Base System
Using the 8272
Contents
INTRODUCTION
The Floppy Disk
The Floppy Disk Drive
,
SUBSYSTEM OVERVIEW
Controller Electronics
Drive Electronics
COl'!troller/Drlve Interface
Processor/Memory Interface
DISK FORMAT
Data Recording Techniques
Sectors
Tracks
Sector Interleaving
THE 8272 FLEXIBLE DISKETTE CONTROLLER
Floppy Disk Commands
Interface Registers
Command/Result Phases
Execution Phase
Multi-sector and Multi-track Transfers
Drive Status Polling
Command Details
THE DATA SEPARATOR
Single Density
Double Density
Phase-Locked Loop Design
In Itlallzation
Floppy Disk Data
Startup
PLL Synchronization
AN INTELLIGENT DISKETTE DATA BASE SYSTEM
Processor and Memory
Serial 110
DMA
Disk Drive Interface
SPECIAL C~NSIDERATIONS
APPENDIX
Schematics
Power Distribution
6-421
, APPLICATIONS
1. INTRODUCTION
Most microcomputer systems in use today require lowcost, high-density removable magnetic media for information storage. In the area of removable media, a designer's
choice is limited to magnetic tapes and floppy disks
(flexible diskettes), both of which offer non-volatile
data storage. The choice between these t,wo technologies
is relatively straight-forward for a given application.
Since disk drives are designed to permit random access to
stored information, they are significantly faster than
tape units. For example, locating information on a disk
requires less than a second, while tape movement (even at
the fastest rewind or fast-forward speed) often requires several minutes. This random access ability permits the use of floppy disks in on-line storage applications (where information must be located', read, and
modified/updAted in real-time under program or
operator control). Tapes, on the other hand, are ideally
suited to archival or back-up storage due to their large
storage capacities (more than 10 million bytes of data
can be archived on a cartridge tape).
61=====
o
•
INDEX HOLE
I
fL--
WRITE PROTECT NOTCH.-/'
(\
Figure 1~ A Floppy Diskette
A sophisticated cont~oller is required, to capitalize on
the abilities of the disk storage unit. In the past, disk
controller designs have required upwards of 150 ICs.
Today, the single-chip 8272 Floppy Disk Controller
(FDC) plus approximately 30 support devices can handle
up to four million bytes of on-line data storage on four
floppy disk drives.
The Floppy Disk
A floppy disk is a circular piece of thin plastic material
covered with a magnetic coating and enclosed in a protective jacket (Figure 1). The circular piece of plastic,
revolves at a fixed speed (approximately 360 rpm) within
its jacket in much the same manner that a record revolves
at a fixed speed on a stereo turntable. Disks are
manufactured in a variety of configurations for various
storage capacities. Two standard physical disk sizes are
commonly used. The 8-inch disk (8 inches square) is the
larger of the two 'sizes; the smaller' Size (5-114 inches
square) is often referred to as a mini-floppy, Singlesided disks can record information on only one side of the
disk, while double-sided disks increase the storage
capacity by recording on both sides. Iii addition; disks are
classified as single-density or double-density. Doubledensity disks use a modified recording method to store
twice as much information in the same disk area as can be
stored on a single-density disk. Table 1 lists storage
capacities for standard floppy disk media.
A magnetic head assembly (in contact with the disk)
positioned at one of these fixed positions, the head can
read or write information in a circular path as the disk
revolves beneath the head assembly. This method
divides the surface into a fixed number of cylinders (as
shown in Figure 2). There are normally 77 cylinders on a
standard disk. Once the head assembly is positioned at a
given cylinder, data may be read or written on either
side of the disk. The appropriate side of the disk is
selected by the read/write head address (zero or one).
Of course, a single-sided disk can only use head zero.
The combination of cylinder address and head address
uniquely specifies a single circular track on the disk. The
physical beginning of a track is located by means of a
small hole (physical index mark) punched through the
plastic near the center of the,disk. This hole is optically
sensed by the drive on every revolution of the disk.
Table 1. Formatted Disk Capacities
Single-Density
Format
Byte/Sector
Sectors/Track
Tracks/Disk
Bytes/Disk
6-422
256
15
77
256,256
295,680
315,392
315,392
128
52
77
256
30
77
512
16
77
1024
8
77
512,512
591,360
630,784
630,784
512
8
77 (
1024
4
77
Double·Denslty
Format
Bytes/Sector
Sectors/Track
Tracks/Disk
Bytes/Disk
writes information onto the disk surface and subsequently reads the data back. This head assembly can
move from the outside edge of the disk toward the
center in fixed increments. Once the head assembly is
128
26
77
AFN 01795A
APPLICATIONS
Each track is subdivided into a number of sectors (see
detailed discussion in section 3). Sectors are generally
128,256, 512, or 1024 data bytes in length. This track
sectoring Ill1lY be accomplished by one of two techniques: hard sectoring ,or soft sectoring. Hard sectored
disks divide each track into a maximum of 32 sectors.
The beginning of each sector is indicated by a sector
hole punched in the disk plastic. Soft sectoring, the IBM
standard method, allows software selection of sector
sizes. With this technique, each data sector is preceded
by a unique sector identifier that is read/written by the
disk controller.
Finally, the drive provides additional signals to the
system controller regarding the status of the drive and
disk. These signals include:
Drive Ready - Signals the system that the drive door
is closed and that a floppy disk is inserted into the
drive.
Track Zero - Indicates that the head assembly is
located over the outermost track of the disk.
This signal may be used for calibration of the disk
drive at system initialization and after an error condition.
Write Protect - Indicates that the floppy disk loaded
into the drive is write protected.
Dual Sided - Indicates that the floppy disk in the
drive is dual-sided.
Write Fault - Indicates that an error occurred during
a recording operation.
IndeX - Informs the system that the physical index
mark of the floppy disk (signifying the start of a data
track) has been sensed.
A floppy disk may also contain a write protect notch
punched at the edge of the outer jacket of the disk. This
notch is detected by the drive and passed to,the controller as a write protect signal.
The Floppy Disk Drive
The floppy disk drive is an electromechanical device
that records data on, or·reads data from, the surface of
a floppy disk. The disk drive contains head control electronics that move the head assembly one increment
(step) forward (toward the center of the disk) or
backward (toward the edge of the disk). Since the
recording head must be in contact with the, disk m~terial
in order to read or write information, the dis'k drive also
contains head-load electronics. Normally the read/write
head is unloaded until it is rtecessary to read or write information on the floppy disk. Once the head assembly
has been positioned over the correct track on the disk,
the head is loaded (brought into contact with the disk).
This sequence prevents excessive disk wear. A small
time penalty is paid when the head is loaded. Approximately thirty to fifty milliseconds are needed before
data may be reliably read from, or written to, the disk.
This time is known as the head load time. If desired, the
head may be moved from cylinder to cylinder while
loaded. In this manner, ortly a small time interval (head
settling time) is required before data may be read from
the new cylinder. The head settling time is often shorter
than the head load time. Typically, disk drives also contain drive select logic that allows mor'e than one physical
drive to be connected to the same interface cable (from
the controller). By means of a jumper on the drive, the
drive number may be selected by the OEM or end user.
The drive is enabled only when selected; when not
selected, all control signals on the cable are ignored.
CURRENT TRACK
Figure 2. Concentric Cylinders on a Floppy Diskette
6-423
AFN 01795A
APPLICATIONS
2. SUBSYSTEM OVERVIEW
A disk subsystem consists of the following functional
electronic units:
1. Disk Controller Electronics
2. Disk Drive Electronics
3. Controller/Di~k Interface. (cables, drivers, terminators)
.
4. Controller/Microprocessor System Interface
The operation of these functional units is discussed in
the.following paragraphs.
Controller Electronics
The disk controller is responsible for converting highlevel disk commands (normally issued by software executing on the system processor) into disk drive com'mands. This function includes:
1. Disk Drive Selection - Disk controllers typically
manage the operations of multiple floppy disk
drives. This controller function permits the system
processor to specify which drive is to be used in a
particular operation.
2. Track Selection - The controller issues a timed sequence of step pulses to move the head from its current location to the proper disk cylinder from which
data is to be read or to which data is to be written.
The controller stores the current cylinder number
and computes the stepping distance from the current
cylinder to the specified cylinder. The controller also
manages the head select signal to select the correct
side of the floppy disk.
3. Sector Selection - The controller monitors the
data on a track until the requested sector is sensed .. ~
4. Head Loading - The disk controller determines
the times at which the head assembly is to be brought
in contact with the disk surface in order to read or
write data. The controller is also responsible for
waiting until the head has' settled before reading or
writing inf9rmation. Often the controller maintains
the head loaded' condition for up to 16 disk revolutions (approximately 2 seconds) after a read or write
operation has been completed. This feature eliminates the head load time during periods 'of heavy disk
110 activity.
5. Data Separation - The actual signal recorded on a
floppy disk is a combination of timing information
(clock) and dat,a. The serial READ DATA input
(from the disk drive) must be converted into two signal streams: clock and data. '(The READ DATA input operates at 250K bits/second for single-density
disks and 500K bits/second for double-density
disks.) The serial data must also be assembled into
8-bit bytes for transfer to system memory. A byte
must be assembled and transferred every 32
microseconds for' single-density disks and every 16
microseconds for double-density.
6. Error Checking - Information recorded on a floppy disk is subject to both hard and soft errors. Hard
(permanent) errors are caused bY media defects. Soft
errors, on the other hand, are temporary errors
caused by electromagnetic noise or mechanical interference. Disk controllers use a standard error checking technique known as a Cyclic Redundancy Check
(CRC). As data is written to a disk, a 16-bit CRC
character is computed and also stored on the disk.
When the data is subsequently read, the CRC character allows the controller to detect data erro~s. Typically, when CRC errors are detected, the controlling
software retries the failed operation (attempting to
recover from a soft error). If data cannot reliably be
read or written after a number of retries, the system
software normally reports the error to the operiltor.
Multiple CRC errors normally indicate unrecoverable media error on the current disk track. Subsequent recovery attempts must be, defined by the system designers and tailored to meet system interfacing
requirements.
Today, single-chip digital LSI floppy disk controllers
such as the 8272 perform all the above functions with
the exception of data separation. A data separation circuit (a combinatIon of digital and analog electronics)
synchronizes itself to the actual data rate of the disk
drive. This data rate varies from drive to drive (due to
mechanical factors such as motor tolerances) and varies
from disk to disk (due to temperature effects). In ·order
to operate reliably with both single- and double-density
storage, the data separation circuit must be based on
phase-locked loop (PI;.L) technology. The phase-locked
loop data separation logic is described in section 5. The
separation logic, after SYnchronizing with the data
stream, supplies a data window to .the LSI disk controller.. This window. differentiates data information
from clock information within the serial stream. The
controller uses this window to reconstruct the data
previously recorded on the floppy disk.
6.-424
Drive Electronics
Each floppy disk drive contains digital electronic circuits that translate TTL-compatible command signals
into electromechanical operations (such as drive selection and head movement/loading) and that sense and
report disk or drive status to the controller (e.g., drive
ready, write fault, and write protect). In addition, the
drive electronics contain analog components to sense,
amplify, and shape data pulses read from, or written to,
the floppy disk surface by the read/write head.
AFN 01795A
APPLICATIONS
Controller/Drive Interface
Memory Access (DMA) controller. When the disk controller requires the transfer of a data byte, it simply ac~
tivates the DMA request line. The DMA controller interfaces to the processor and, in response to the disk
controller's request, gains. control 'of the memory ini.erface for a short period of time-long enough to transfer
the requested data byte to/from memory. See section 6
for a detailed DMA interface description.
The controller/drive interface consists of high-current
line drivers, Schmitt triggered input gates, and flat or
twisted pair cable(s) to connect the disk drive electronu:s
to the controller electronics. Each interface signal line is
resistively terminated at the end of the cable farthest
from the line drivers. Eight-inch drives may be directly
interfaced by means of SO-conductor flat cable.
Generally, cable lengths should be less than ten feet in
order to maintain noise immunity.
3. DISK FORMAT
New floppy disks must be written with a fixed format by
the controller before these disks may be used to store
data. Formatting is a method of taking raw media and
adding the necessary information to permit the controller to read and write data without error. All formatting is performed by,the disk controller on a track-bytrack basis under the direction of the system processor.
Generally, a track may be formatted at any time.
Ho-.yever, since formatting "initializes" a complete disk
track, all previously written datli is lost (after a format
operation). A format operation is normail~ used only
when initializing,new floppy disks. 'Since soft-sectoring
in such a predominant formatting technique (due to
IBM's influence),' the following discussion will limit
itself to soft-sectored formats.
Normally, provisions are made for up to four disk
drives to share the same interface cable. The controller
may operate as many cable assemblies as practical. LSI
floppy disk controllers typically operate one to four
drives on a single cable.
Processor/Memory Interface
The disk controller must interface to the system processor and memory for two distinct purposes. First, the
processor must specify disk control and command
parameters to the controller. These parameters include
the selection of the recording density and specification
of disk formatting information (discussed in section 3).
In addition to disk parameter specification, the .processor must also send commands (e.g., read, write, seek,
and scan) to the controller. These commands require the
specification of the command code, drive number,
cylinder address, sector address, and head address.
Most LSI controllers receive commands and parameters
by means of processor I/O instructions.
In addition to this I/O interface, the controller must
also be designed for high-speed data transfer between
memory and the disk drive. Two implementation
methods may be used to coordinate this data transfer.
The lowest-cost method requires direct processor intervention in the transfer. With this method, the controller issues an interrupt to the processor for each data
transfer. (An equivalent method allows the processor to
poll an interrupt flag in the controller status word.) In
the case of a disk write operation, the processor writes a
data byte (to be encoded into the serial output stream)
to the disk controller following the receipt'of each controller interrupt. During a disk read operaiion, the processor reads a data byte (previously assembled from the
input data stream) from the controller after each inter'rupt.The processor must transfer a data byte from the
controller to memory or transfer a data byte from
memory to the disk controller within 16 or 32
microseconds after each interrupt (double-densitY/lnd
single-density response times, respectively).
If the system processor must service a variety of other
interrupt sources, this interrupt method may not be
practicat, especially in double-density systems. In this
case, the disk controller may be interfaced to a 'Direct
Data Recording Techniques
Two standard data recording techniques are used to
combine'clock and data information for storage on a
floppy disk. The single-density technique is referred to
asFM encoding. In FM encoding (see Figure 3),a double frequency encoding technique is used that inserts a
data bit between two adjacent clock bits. (The presence
of a data bit represents a binary "one" while the
absence of a data bit represents a binary "zero. ") The
two adjacent clock bits are referred to as a bit cell, and
except for unique field identifiers, all clock bits written
, on the disk ar~ b,inary "ones." In: FM encoding, each
data bit is written at the center of the bit cell and the
clock bits are written at the leading edge of the bit cell.
The encoding used for double-density recording is
termed MFM encoding (for "Modified FM"). In MFM
encoding (Figure 3) the data bits ate again written at the
center of the bit cell. However, a clock bit is written at
the leading edge of the bit cell only if no data bit was
written in the previous bit cell and no data bit will be'
written in the present bit cell.
Sectors
Soft-sectored floppy disks divide each track into a
number of data sectors. Typically, sector sizes of 128,
256, 512, or 1024 data bytes are permitted. The sector
size; is specified'when the track is initially formatted by
the controller. Table 1 lists the single- and double6-425
AFN 01795A
APPLICATIONS
density data storage capliCitiC$ for each of the four· sector sizes. Each sC\;tor within a track is comj)Osed of the
following four fields (illustrated in Figure 4):
the beginning of the data field. When a sector is to be
deleted, (e.g., a hard error on the disk), a deleted
data address mark is written in place of the data address mark. The last two bytes of the data field comprise the eRe character.
1. Sector ID Field- This field, consisting of seven
. ,bYtes, IS Written only wheri the track is formatted.
The ID field provides the sector identification that is
used by the controller when a sector must be read or
written. The first byte of the field is the ID address
mark, a unique coding that speciijes the beginning of
the ID field. The second, third, and fOurth bytes are
the cylinder, head, and sector addresses, respectively, and the fifth byte is the sector length code. The
last two bytes are the 16-bit eRe character for the
ID field. During formatting, the controller supplies
the address mark. The cylinder, head, and sector addtesses and the sector length code are supplied to the
controller by the processor' software. The eRe
character is derived by the controller from the data'in
the first five bytes.
4. Post Data Field Gap - The post data field gap
, (gap 3) is written when the track is formatted and
separates the preceding data field from the next
physiCal ID field on the track. Note that a post data,
field gap is not written following the last physiCal
sector on a track. The,gap itself cOntains a programselectable number of bytes .. Following a sector update (write) operation, the drive's write logic is
disabled during the gap. The actual size of gap- 3 is
determined by the maximum number of data bits
that can be recorded on a track, the number of sectors per track and the total sector size (data plus
overhead information). The gap size must be adjusted so that it is large enough to contain the discontinuity generated on the floppy disk when the write
current is turned on or off (at the start or completion
of a disk write operation) and to contain a synchronization field for the upcoming ID field (of the
next sector). On the other hand, the gaps must be
small enough so that the total number of data bits required on the track (sectors plus gaps) is less than the
maximum number of data bits that can be recorded
on the track. The gap size must be specified for all
read, write, and format operations. The gap size
used during disk reads and writes must be smaller
than the size used to format the disk to avoid the
splice points between contiguous physiCal sectors.
Suggested gap sizes are listed in Table 9.
2. Post ID Field Gap - The post ID field gap (gap 2)
is writteillniti8l1y when the track is formatted. Duririg subsequentwrite operations, the drive's write circuitry is enabled within the gap and the trailing bytes
of the 'gap are rewritten each time the sector is updated (written). During subsequent read operations,
the trailing bytes of the gap are used to synchronize
the data separator logic with the upcoming data
field.
.
3. Data Field':"" The length (number of data bytes) of
the data field is determined by software when the
track is formatted. The first byte· of the data field is
the data address mark, a unique coding that specifi~s
I 1 Ii 11 I
0
I
1
I
0
I
0
I
0
1
I
1
o
I
0
I
0
FM
MFM
NOTE THAT THE FM BIT CELL IS TWICE THE SIZE OF THE MFM BIT CELL. THtiS, THE
FM TIME SCALE IN THIS FIO~RE IS 4 .slBII WHll.E THE MFM TIME SCALE IS 2.slBIT .
Figura 3. FM IiInd MFM Encoding
,6-426
AFN 01795A
~PPLl.CATIONS
Tracks
chronize the data separator logic ,with the data to be
read from the ID field (of the flJ'st sector). The post
index gap is written only when the disk is formatted.
The overall format for a track is Wustratecl in Fisure 4.
Each track consists of the following fieldsl
4. Sectors - The sector information (discussed above)
is repeated o~ for each sector on the track.
1. Pre-'lndex Gap ...:... The pre-index gap (sap S) is written only when the track is forJDattCd.
S. Final Gap -
The fmal gap (sap 4) is written when
the track is formatted' and extends from the last
physical data field on the track to the physical index
mark:' The length of this gap is dependent on the
number of bytes per sector sPecified, the lengths of
the program-selectable gaps specified, and the drive
speed.
2. Index Address Mark - The index address mark
consists of a unique code that indicates the beginning
of a data track. One index mark is written on each
track when the track is formatted.
3. Post Index Gap - The post index gap (sap 1) is
used durina disk read and write o~erations to syn-
----_......n~:
pHYIICAL
f~
SECTOR
DATA
FIELD
PREINDEX
GAP
(GAP I)
FINAL
GAP
(GAP 4)
INDEX
ADDRESS
MARK
I
HEXFF
I
DATA
A=~
POST
INDEX
GAP
(GAP 1)
POIT-ID
FIELD
GAP
(GAP II
SECTOR
1
ID FIELD
SECTOR 1
DATA FIELD
I
SYNC,
(HEXOD)
I I
HEXFF
SYNC
(HEX
00)
,
I
I
I
121. an USER DATA BYTES
I
CRC
BYTE 1
I
CRC
BYTE 2
"
JL
POBT
DATA
FIELD
GAP
(GAPS)
lECTOR
2
POBTID
FIELD
ID FIELD'
GAP
(GAP
POST
lECTOR 2
DATA FIELD
II
DATA
FIELD
GAP
(GAPS)
POSTID
FIELD
SECTOR
, 8
GAP
IDFIELD
(GAP II
I
ID
ADDRESS
MARK
TRACK
ADDRESS
BYTE 1
BYTE 2
I II I
(H~
SYNC
00)
HEX FF
SECTOR
ADDRESS
SECTOR
UlNGTH
SYTE4
BYTES
I I
HEX FF
I
J 1 I
'HEAD
ADDRESS
I
CRe
BYTE 1
BYTEe
J.
J
~,-/
SECTOR
DATA
FIELD
"
"
'
.
(HEX
SYNC
00)
CRe
BYTE 2
BYTE 7
J
Figure 4. Standard Floppy Dlske"e Track Format (From sac 204 Manual)
6-427,
AFN 01795A
APPLICATIONS
Sector Interleaving '.
'
,
The initial formatting of a floppy disk determineS where
sectors are located within track. It is not necessary to
allocate sectors sequentially around the traCk (i.e.,
1,2,3, .. .',26). In fact, is is often advantageous to place
the sectors ,on 'the track in a non-sequential order.Sequential sectQr ordering optimizes sector access times
during multi-sector transfers (e.g., when a program is
loaded) by permitting the number of sectors specified
(up to an entire; track) to be transferred within a single
revolution of the disk. A technique known ~~ector interleaving optimizes access times when, altho. sectors
are accessed sequentially, a small amount of processing
must be performed between sector reads/writes. For example, an editing program performing a text search
reads sectors sequentially, and after each sector is read,
, performs a software search. If a match is not found, the
- software issues a read request for the next sector. Since
the floppy disk continues to rotate during the time that
the software executes, the next physical sector is already
passing under the read/write head when the read request
is issued, and the processor must wait for another complete revolution of the disk (approximately 166
milliseconds), before the data may actually be input.
With interleaving, the sectors are not stored sequentially
on a track; rather, each sector is physically removed
from the previous sector by soine number (known as the
interleave factor) of physical seCtors as shown in Figure
's. This method of sector allocation provides the processor additional execution time between sectors on the
disk. For example, wi~ a 26 sector/track format, an interleave factor of 2 provides 6.4 milliseconds of processing time between sequential 128 byte sector accesses.
a
To calculate the correct interleave factor, the maximum
processor time between sector operations must be divided' by the time required for complete sector to pass
under the disk readlwrite head. After determining the
interleave f~or, the correct sector numbers,are p~sed
to the disk controller (~n the exact order that they are to
physically appear on the track) during the execution of a
format operation.
'
a
4. THE 8272 FLEXIBLE DISKETTE
CONTROLLER
The 8272 is a single-chip LSI Floppy Disk Controller
(FDq that contains the circuitry necessary to implement both single-and double-density floppy disk storage
subsystems (with up to four dual-sided disk drives per
FDq. The 8272 supports the IBM 3740 single-density
recording format (FM) and the IBM System 34 doubledensity recording format (MFM). With the 8272, iess
than 30 ICs are needed to implement a complete disk
subsystem. The 8272 accepts and executes high-level
disk commands such as formai track, seek, read sector,
write sector, and read track. All data synchronization
and error checking is automat,icallY performed by the
FDC to ensure reliable data storage and subsequent
retrieval. External logic is reqUired only for the generation of the FDC master clock and write clock (see Section 6) and for data separation (Section S). The FDC
provides signals that control the startup and base frequency selection of the dat,a separator. These signals
greatly ~e the design of a phase-locked loop data
separator.
In addition to the data separator interface signals, the
8272 also provides the necessary signals to interface to
microprocessor systems with or without Direct Memory
Access (DMA) ~apabilities. In order to interface to a
large number of commercially avllilable floppy disk
drives, the FDC permits software specification of the
track stepping -rate, the head load time, and the head
unload time.
The pin configuration and internal block diagram of the
8272 fs shown in Figure 6. Table 2 contains a description
for each FDC interface pin.
'
Floppy Disk Commands
Figure 5. Interleaved Sector Allocation Within a Track
The 8272 el'ecutes fifteen high-level disk interface
""mmands:
Specify
Write Data
Write Deleted Data
Sense Drive Status
Read Track
Sen~ htterrupt Status
Read ID
Seek
Scan Equal
Recalibrate
Scan High or Equal
Format Track
Scan Low or Equal
Read Data
Read ,Deleted Data
6.r428
AFN 01795A
APPLICATIONS
Each command is initiated by a multi-byte transfer from
the processor to the FOC (the transferred bytes contain
command and parameter information). After complete
command specification, the FOC automatically executes the command. The command result data (after
execution of the command) may require a multi-byte
transfer of status information back to the processor. It
ill QOIIlvenient to consider each FOC command as consisting of the following thre,e phases:
COMMAND PHASE:
RESET
Rii
Viii
Ci
Ao
os.
The executing program
transfers to the FOC all the
information required to perform a particular disk operation. The 8272 automatically
enters the command phase
after RESET and following
the completion of the result
phase (if any) of a previous
command.
Vee
EXECUTION PHASE: The FOC performs the
operation as instructed. The
execution phase is entered
immediately after the last
command parameter is written to the FDC in the
preceding command phase.
The execution phase normally ends when the last data
byte is transferred to/from
the disk (signalled by the TC
input to the FDC) or when an
error occurs.
RESULT PHASE:
After completion of the disk
operation, status and other
housekeeping information
are made available to the
processor. After the processor reads this information,
the FOC reenters the command phase and is ready to
accept another command.
DBo.,
Rw/sEEK
lCT/DIR
FRISTP
HDl
RDY
WPITS
FlTITRKO
PSo
PS,
DB,
WR DATA
DB,
DSo
DB,
DRQ
DAcK
TC
TERMINAL
COUNT
READY
OS,
WRITE-PROTECTITWO SIDE
INDEX
FAULTITRACK 0
HDSEl
MFM
WE
IDX
Vee
INT
RDDATA
ClK
DW
GND
WRClK
DRIVE SELECT 0
DRIVE SELECT 1
MFM MODE
e"S
elK ---.
Vee --..
GND -+-
IIW/sEEK
HEAD lOAD
HEAD SELECT
lOW CURRENT/DIRECTION
FAULT RESETfSTEP
Figure 6. 8272 Pin Configuration and Internal Block Diagram
AFN 01795A
APPLICATIONS
Table 2. 8272 FOe Pin Description
Number
Pin
Symbol
110
To/From
Description
I
RST
I
uP
Reset. Active-high signal that places the FDC in the "idle" state and all
disk drive output signals are forced inactive (low). This input must be
held active during power on reset while the RD and WR inputs are active.
2
RD
I·
uP
Read. Active-low control signal that enables data transfer ftom the FDC
to the data bus.
3
WR
I·
uP
Write. Active-low control signal that enables data transfer from the data
bus into the FDC.
4
CS
I
uP
Chip Select. Active-low control signal that Selects the FDC. No reading or
writing will occur unless the FDC is selected.
S
Ao
I·
uP
Address. Selects the Data Register or Main Status Register for input/output in conjunction with the RD and WR inputs. (See Table 3.)
6-13
IlBo-DB?
I/O·
uP
Data Bus. Bidirectional three"state 8-bit data bus.
14
DRQ
0
DMA
DMA Request. Active-high output that indicates an FDC request for
DMA services.
I
DMA
DMA Acknowledge. Active-low control signal indicating that the requested DMA transfer is in progress.
DACK,
15
I
16
TC
I
DMA
Terminal Count. Active-high signal that causes the termination of a command. Normally, the terminal count input is directly connected to the
TCIEOP output from the DMA controller, signalling that the DMA
transfer has been completed. In a non-DMA environment, the processor
must count data transfers and supply a TC signal to the FDC.
17
lOX
I
Drive
Index. Indicates detection of the physical index mark (the beginning of a
track) on the selected disk drive.
1,8
INT
0
uP
Interrupt Request. Active-high signal indicating an 8272 interrupt service
request.
I
19
CLK
20
GND
Clock. Signal phase 8 MHz clock (50"70 duty cycle).
21
WRCLK
I
22
DW
I
PLL
Data Window. Data sample signal from the phase-locked loop indicating
that the FDC should sample input data from the disk drive.
Ground. DC power return.
Write Clock. SOO kHz (FM) or I MHz (MFM) write clock with a constant
pulse width of 2S0 ns (for both FM and MFM recording). The write clock
must be present at all times.
23
RDDATA
I
Drive
Read Data. FDC input data from the selected disk drive.
24
YCO
0
PLL
YCO Sync. Active-high output that enables the, phase-locked loop to
synchronize witli the input data from the disk drive.
2S
WE
0
Drive
Write Enable. Active:high output that enables the disk drive write gate:
MFM
0
PLL
MFM Mode. Active-high output used by external logic to enable the
MFM double-density recording mode. When the MFM output is low,
single-density FM recording is indicated.
27
HDSEL
0
Drive
Head Select. Selects head 0 or head I on a dual-sided disk.
28,29
DS.. DSo
0
Drive
Drive Select. Selects one of four disk drives.
WRDATA
0
Drive
Write Data. Seriai data stream (combination of clock and'data bits) to be
writtert on the disk.
PSIoPSO
0
Drive
Precompensation (pre-shift) Control. Write precompensation output control d~ring MFM mode. Specifies early, late. and normal timing signals.
See the discussio,n in Section S.
,
26
30
31,32
"
6~430
AFN 01795A
APPLICATIONS
Table 2. 8272 FDC Pin Description (continued)
Number
Pin
Symbol
1/0
ToiFrom
33
FLT/TRKO
I
Drive
Fault/Track O. Senses the disk drive fault condition in the Read/Write
mode and the Track 0 condition in the Seek mode.
34
WP/TS
I
Drive
Write Protect/Two-Sided. Senses the disk write protect status in the
Read/Write mode and the dual-sided media status in the Seek mode.
Description
35
ROY
I
Drive
Ready. Senses the disk drive ready status.
36
HDL
·0
Drive
Head Load. Loads the disk drive read/write head. (The head is placed in
contact with the disk.)
37
FR/STP
0
Drive
Fault Reset/Step. Resets the fault flip-flop in the disk drive when
operating in the Read/Write mode. Provides head step pulses (to move
the head from one cylinder to another cylinder) in the Seek mode.
38
LCT/DIR
0
Drive
Low Current/Direction. Signals that the recording head has been positioned over the inner cylinders (44-77) of the floppy disk in the ReadlWrite
mode. (The write current must be lowered when recording on the physically shorter inner cylinders of the disk. Most drives do not track the actual head position and require that the FDC supply this signal.) Determines the head step direction in the Seek mode. In the Seek mode, a high
level on this pin steps the read/write head toward the spindle (step-in); a
low level steps the head away from the spindle (step-out).
39
RW/SEEK
0
Drive
Read, Write/Seek Mode Selector. A high level selects the Seek mode; a
low level selects the Read/Write mode.
40
"Disabled when
Vee
+ SV DC Power.
es is high.
Interface Registers
To support inf.ormation transfer between the FDC and
the system processor, the 8272 contains two 8-bit
registers: the Main Status Register and the Data
Register. The Main Status Register (read only) contains
FDe status information and may be accessed at any
time. The Main Status Register (Table 4) provides the
system processor with the status of each disk drive, the
status of the FDC, and the status of the processor interface. The Data Register (read/write) stores data, commands, parameters, and disk drive status information.
The Data Register is used to program the FDe during
the command phase and to obtain result information
after completion of FDe operations. Data is read from,
or written to, the FDe registers by the combination of
the AO, RD, WR, and CS signals, as described in
Table 3.
In addition to the Main Status Register, the FDe contains four additional status registers (STO, STl, ST2,
and ST3). These registers are only available during the
result phase of a command.
cs
0
0
0
0
(l
0
1
6-431
Table 3. FDC ReadlWrlte Interface
. Ao
RD
WR
Function
0
0
0
1
1
1
X
0
I
0
0
0
1
X
1
0
0
0
1
0
X
Read Main Status Register
Illegal
Illegal
Illegal
Read from Data Register
Write into Data Register
Data Bus is three-stated
AFN 01795A
APpLICATIONS
Table 4. Main Status Register Bit Definitions
Bit
Symbol
Number
Description
0
DaB
Disk Drive 0 Busy. Imk Drive 0 is
in the Seek mode.
I
DIB
Disk Drive I Busy. Disk Drive I is
in the Seek mode.
2
D2B
Disk Drive 2 Busy. Disk Drive 2 is
in the Seek mode.
3
D3B
Disk Drive 3 Busy. Disk Drive 3 is
in the Seek mode.
4
CB
FDC Busy. A read or write command is in process. '
S
NDM
Non-DMA Mode. The FDe is in
the non-DMA mode when this bit is
high. This bit is set only during the
execution phase of commands in
the non-DMA mode. Transition to
a low leve} indicates that the execution phase has ended.
6
DIO
Data Input/Output. Indicates the
direction of a data transfer between
the FOC and the Data Register.
When DIO is high, data is read
from the Data Register by the processor; when DIO is low, data is
written from the processor to the
Data Register.
7
RQM
Request for Master. Indicates that
the Data Register is ready to send
data to, or receive data from, the
processor.
Command/Result Phases
Table 5 lists the 8272 command set. For each of the fifteen commands, command and result phase data
transfers are listed. A list of abbreviations used in the
table is given in Table 6, and the contents of the result
status registers (STO-ST3) are illustrated in Table 7.
The bytes of data which are sent to the 8272 during the
command phase, and are read out of the 8272 in the
result phase, must occur in the order shown in Table S.
That· is, the command code'must be sent first and .the
other bytes sent in the prescribed sequence. All bytes of
the command and result phases must be read/written as
described. After the last byte of data in' the command
phase is sent to the 8272 the execution phase
automatically starts. In a similar fashion, when the last
byte of data is read from the 8272 in the result phase,
the command is automatically ended and the 8272 is
, ready for a new command. A command may be aborted
by simply raising the terminal count signal (pin 16). This
is a convenient means of ensuring that the processor
may always gain control of the 8272 (even if the disk
system hangs up in an abnormal manner).
It is important to note that during the result phase all
bytes shown in Table 5 must be read. The Read Data
command, for example, has seven bytes of data in the
result'phase. All seven bytes must be read in order to
successfully complete the Read Data command. The
8272 will not accept a new command until all seven
bytes have been reaq. The number of command and
result bytes varies from command-to-command.
In order to read data from, or write data t9, the Data
Register during the command and result phases, the
system processor must examine the Main Status Register
to determine if the Data Register is available. The DIO
. (bit 6) and RQM (bit 7) flags in the Main Status Regis,ter
must be low and high, respectively, before each byte of
the command word may be written into the 8272. Many
of the commands require multiple bytes, and as a result,
the Main Status Register must be read prior to each byte
transfer to the 8272. To read status bytes during the
result phase, DIO and RQM in the Main Status Register
'must both be high. Note, checking the Main Status
Register in this manner before each byte transfer
to/from the 8272 is required only in the command and
result phases, and is NOT required during the execution
phase.
execution Phase
All data transfers to (or from) the floppy drive occur
during the execution phase. The 8272 has two primary
modes of operation for data transfers (selected by
the specify command);
1. DMA mode
2. non-DMA mode
In the DMA mode, DRQ (DMA Request) is activated
for each transfer request. The DMA controller responds
to DRQ with DACK (DMA Acknowledge) and RD (for
read commands) or WR (for write commands). DRQ is
reset by the FDC during the transfer. INT is activated
after the last data transfer, indicating the completion of
the execution phase, and the beginning of the result
phase. In the DMA mode, the terminal count
(TC/EOP) output of the DMA controller should be
connected to the 8272 TC input to properly terminate
disk data transfer commands.
6-432
AFN 01795A
APPUCATIONS
Table 5.
PtfASE
Command
-
-"
W
W
W
W
W
W
W
W
W
DATA_
I
lis
D.t IIa Dz
IDr "AEADDATA
lIT MFM SK
0
0
0
0
0
0
0
I
II,
1101
, ,
0
HOS OS, DSO
-- - -
Command~
GPL
DTL
_... """....,.......
o.ta Imnster
_.heFDD
A
A
A
A
'A
A
A
W
W
W
W
W
W
W
W
W
~
Soclor 10 I n _
prior to Command
_Ian
C
H
A
N
Ear
lIT MFM SK
-.......-
0
0
0
0
"-
lis D.t IIa Dz II, IIa
READATRM:K
0 MFM SK
0
0
0
,
0
0
0
0 HOSOS'DSO
0
0
prior to c:omn..I
~
GPL
-_
DTL
D
_FDD
_ IIIa
...
_the""" _
phyIIcoI-
Resu"
Command coo..
A
A
A
A
A
A.
A
STO
ST'
ST2
C
H
A
N
,
Status information
-~
_tton
_IDln_
_COOnmIInd
_ution
AEADID
prior to Command
IIII DProceosor .
Dmo~DProceosor
Table11 ID Information When Procesior Teimlnates Command
"
MT (
£01
lA
OF
08
lA
OF
0
1
I)
,
.
,
(
Final Sector Transferred
10
Processor
Sector 1 to 25 at Side 0
Sector 1 to 14 at Side 0
. Sector 1 to 7 at Side 0
08
Sector 26 at Side 0
Sector 15 at Side 0
Sector 8 at Side 0
lA
OF
08,
Sector 1 to 25 at Side 1
Sector, 1 to 14 at Side 1
Sector 1 to 7 at Side 1
lA
. OF
08
Sector 26 at Side 1
Sector 15 at Side 1
Sector 8 at Side 1
lA
, OF
08
C
ID Information at Result Pha..
H
R
N
NC
NC
R+l
NC
C+l
NC
R=OI
NC
NC
NC
RH
NC
R=OI
NC
R+l
NC
\
C+l
NC
Sector 1 to 25 at Side 0
Sector 1 to '14 at Side 0
Sector 1 to 7 at Side 0
NC
NC
lA
OF
08
Sector 26 at Side 0
Sector 15 at Side 0
Sector 8 at Side 0
NC
LSD
R=OI
NC
lA
OF
08
Sector 1 to 25 at Side 1
Sector 1 to 14 at Side,l
Sector 1 to 7 at Side 1 ,
NC
NC
R+l
NC
lA
OF
Sector 26 at Side 1
Sector IS at Side 1
Sector '8 at Side 1
C+l
LSD
R=OI
NC
Q8
,
"
'~
Notes: 1. NC (No Chllll8c): The same value as the one at the beglnllllll of command execution:
2. LSi (Least Significant Bit): The least Bisnificant bit of H is complemented.
6-442
AFN 01795A
APPLICATIONS
not satisfied" flags under various scan termination
conditions.
If the FDC encounters a deleted data address mark in
one of the sectors and the skip fl,ag is low, it regards the
sector as· the last sector on the cylinder, sets the" control
mark" flag (bit 6 in Status Register 2) and terminates
the command. If the skip flag is high, the FDC skips the
sector with the deleted address mark, and reads the next
sector. In this case, the FDC also sets the "control
mark" flag (bit 6 inStatus Register 2) in order to show
that a deleted sector had been encountered.
NOTE: During scan command execution, the last sector
on the track must be read for the command to
terminate properly. For example, if the scan
sector increment is set to 2, the end of track
parameter is set to 26, and the scan begins at
sector 21 , sectors 21, 23, and 25 will be
scanned. The next sector, 27 will not be found
on the track and an abnormal command termination will occur. The command would be
completed in a normal manner if either a) the
scan had started at sector 20 or b) the end of
track parameter had been set to 25.
During the Scan command, data is supplied by the processor or DMA controller for comparison against the
data read from the disk. In order to avoid having the
"overrun error" flag set (bit 4 in Status Register 1), it is
necessary to have the data available in less than 27 /Ls
(FM Mode) or 13 /LS (MFM Mode). If an overrun error
occurs, the FDC terminates the command.
Invalid Commands
If an invalid (undefined) command is sent to the FDC,
the FDC will terminate the command. No interrupt is
generated by the 8272 during this condition. Bit 6 and
bit 7 (010 and RQM) in the Main Status Register are
both set indicating to the processor that the 8272 is in
the result phase and the contents of Status Register 0
must be read. When the processor reads Status Register
oit will find an 80H code indicating that an invalid command was received.
A Sense Interrupt Status command must be sent after a
Seek or Recalibrate interrupt; otherwise the FDC will
consider the next command to be an invalid command.
Also, when the last "hidden" interrupt has been serviced, further Sense Interrupt Status commands will
result in invalid command codes.
In some applications the user may wish to use this command as a No-Op command to place the FDC in a
stand-by or no operation state.
5. THE DATA SEPARATOR
As briefly discussed in section 2, LSI disk controllers
such as the 8272 require external circuitry to generate a
data window signal. This signal is used within the FDe
to is,9late the data bits contained within the READ
DATA input signal from the disk cWve. (The disk.
READ DATA signal is a composite signal constructed
from both clock and data information.) After isolating
the data bits from this input signal, the FDC assembles
the data bits into 8-bit bytes for transfer to the system
processor or memory.
Single· Density
In .single-density (FM) recording (Figure 3 ). the bit cell
is 4 microseconds wide. Each bit cell contains a clock bit
at the leading edge of the cell. The data bit (if present) is
always located at the center of the cell. The job of data
separation is relatively straightforward for singledensity; simply generate a data window 2 /LS wide starting 1 /Ls after each clock bit. Since every cell has a clock
bit, a fixed window reference is available for every data
bit and because the window is 2 p.s wide, a slightly
shifted data bit will still remain within the data window.
A single-density data separator with these specifications
may be easily generated using a digital or analog oneshot triggered by the clock bit.
Double·Denslty
Double-density (MFM) bit cells are reduced to 2 /LS (in
order to double the disk data storage capacity). Clock
bits are inserted into the data stream only if data bits are
not present in both the current and preceding bit cells
(Figure 3). The data bit (if present) still occurs at the
center of the bit cell and the clock bit (if present) still occurs at the leading edge of the bit cell.
MFM data separation has two 'problems. First, only
some bit cells contain a clock bit. In this manner, MFM
encoc\ing loses the fixed bit cell reference pl,llse present
in FM encoding. Second, the bit cell for MFM is c;mehalf the size of the bit cell for FM. This shorter bit cell
means that MFM cannot tolerate as large a playback
data-shift (as EM can tolerate) without errors~
Since most playback data-shift is predicta,ble, the FDC
can precompensate the write data stream so that
datal clock pulses will be correctly positioned for subsequent playback. This function is completely controlled
, by the FDC and is oniy required for MFM recording.
During write operations, the FDC specifies an early,
normal, or late bit positioning. This timing information
is specified with respect to the FDe write clock. Early
and late timing is typically 125 ns to 250 ns before or
after the write clock transition (depending on disk drive
requirements).
6-443
AFN 01795A
APPLICATIONS
r
The data separator c:in:uitry for double-deusity recording must continuously analyze the total READ DATA
stream, synchronizing its operation (window generation) with the actual cIockIdata bits of the data stream.
The data separation circuit must track the disk input
data frequency very cIosely-unPrecHctable bit shifts
leave less than SO ns. margin to the window edges.
Phas.Locked Loop
Only an analog phase-locked loop (PLL) can provide
the reliability required for a double-density data separation circuit. (A phase-locked loop is an electronic circuit
that constantly analyzes the frequency of an input signal
and locks another oscillator to that frequency.) Using
analog PLL techniques, a data separator can be designed with ± 1 ns reSolution (this would require a 100
MHz clock in a digital phase-locked loop). The analog
PLL determines the clock and data bit positions by
sampling each bit in the serial data stream. The phase
relationshiP between a data bit and the PLL generated
data window is constantly fed back to adjust the positioil of the data window, enabling the PLL to track input data frequency changes,. and thereby reli~blY read
previously recorded data from a floppy disk.
PLL Design·
A block diagram of the phase-locked loop described in
this application note is shown ~ Figure 7. Basically, the
phase-locked loop operates by comparing the frequency
of the input data (from the disk drive) against the frcquep.cy of a local oscillator. The difference of these frequencies is used to increase or decrease the frequency of
the local oscillator iii. order to bring its frequency closer
to that of the input. The PLL synchronizes the local
oscillator to the frequency of the input during the all
. "zeroes" synchronization field on the floppy disk (immediately preceding both the ID field and the data
field).
The PLL consists of nine ICs and is located on page 3 of
the schematics in the Appendix. The 8272 veo output
essentially turns the PLL circuitry on and off. When the
PLL is off, it "idles" at its center frequency. The veo
output turns the PLL on only when valid data is being
received from the disk drive~ The veo turns the PLL
on after:. the readlwrite head has been loaded and the
head load time has e!.apsed. The PLL is turned off in the
gap between the ID field and the· data fieta and in the
gap after the data field (before the n~ sector ID field).
The GPL parameter in the FDC read and write commands specifies the elapsed time (number of data bytes)
that the PLL is turned off in order to blank out discontinuities that appear in the gaps when the write current is
turned on and off. The PLL operates with either MFM
or FM input data. The MFM output from the FDC controls the PLL operation frequency.
The PLL consists of six functional blocks as follows:
1. Pulse Shaping - A 96LS02 senses a READ DATA
pulse and provides a clean output signal to the FDC .
and to the PLL Phase Comparator and Frequency
Discriminator circuitry.
2. Phase Comparator - The phase difference between the PLL oscillator and the READ DATA input
is compared. Pump up (PU) and pump down (PD)
error signals are derived from this phase difference
and output to the filter. If there is no phase difference between the PLL oscillator and the READ
/DATA input, the PU and PD pulse widths are equal.
If the READ DATA pulse occurs early, the PU dura"
tion is shorter than the PD duration. If the data pulse
occurs late, the PU duration is longer than the PD
duration.
3. F"llter - This analog circuit illters the PU and PD
pulses into an error voltage. This error voltage is buffered by an LM3S8 operational amplifier.
.----_ _ _ _ _ _ _ _ _ _ _ _~--_~.:TA
DATAWlNDOW
~
(TO FDC)
READ DATA
DISKETTE DRIVE)
IDiECLAMP
Vco~FDC) - - - - - - - - -....
_
~FDC) - - - - - - - - -....
Figure 7. Phase-Locked Loop Data Separator
AFN01795A
APPLICATIONS
4. PLL Oscillator - This oscillator is composed of a
74LS393, 74LS74, and 96LS02. The oscillator frequency is controlled by the error voltage output by
the ftlter. This oscillator also generates the data window signal to the 'FOC.
5. Frequency Discriminator - This logic tracks the
READ DATA,' input from the disk drive and
discriminates between the synchronization gap for
FM reCording (250 KHz) and the gap for MFM
recording (500 KHz). Synchronization gaps 'immediately precede address marks.
6. Start Logic - The function of this logic is to clamp
the PLL oscillator to its center frequency (2 MHz)
until the FDe veo signal is enabled and a valid data
pattern is sensed by the frequency discriminator. The
start logic (consisting of a 74LS393 and 74LS74) ensures that the PLL oscillator is started with zero
phase error.
PLL Adjustments
The PLL must be initially adjusted to operate at its
center frequency with the veo output off and the adjustment jumper removed. The 5K trimpot should be
adjusted until the frequency at the test point (Q output
of the 96LS02) is 2 MHz. The jumper should then be
replaced for normal operation.
PLL DeSign Details
The following paragraphs describe the operational and
design details of the phase-locked loop data separator il-
lustrated in the appendix. Note that the analog section is
operated from a separately filtered +sv supply.
Initialization
As long as the 8272 maintains a low veo signal, the
data separator logic is "turned off'. In this state, the
PLL oscillator (96LS02) is not oscillating an4 therefore
the 2XBR signal is constantly low. In addition, the
pump up (PU) and pump down (PD) signals are inactive
(PU low and PD high), the CNT8 signal is inactive
(low), and the filter input voltage is held at 2.5 volts by
two IMohm resistors between ground and +5 volts.
Floppy Disk Data
The data separator frequency discriminator, the input
pulse shaping circuitry, and the start logic are always
enabled and respond to rising edges of the READ DATA
signal. The rising edge of every data bit from the disk
drive triggers two pulse shaping one-shots. The first
pulse shaper generates a stable and well-defined 200 ns
read data pulse for input to the 8272 and other portions
of the. data separator logic. The second one-shot
generates a 2.5 p.s data pulse that is used for input data
frequency discrimination.
The frequency discriminator operates as illustrated in
Figure 8. The 2F output signal is active (high) during
reception of valid MFM (double-density) sync fields on
the disk while the IF signal is active (high) during reception of valid FM (single-density) sync fields. A
multiplexer (controlled by the 8272 MFM signal) selects
the appropriate IF or 2F signal depending on the programmed mode.
, (a) FM OPERATION: ONE-llHOT TIMES OUT BETWEEN CLOCK PULSES
FREQ DISC -..,.... _ _
2F LOW. 1F HIGH DURING SYNC DATA INPUT (FM)
MFM READ DATA
_ ... .. ,.
~ 2F HIGH. 1F LOW DURING SYNC DATA INPUT (MFM)
FREQ
DISC~
•
•
x = FREQUENCY DISCRIMINATOR SAMPLE POINTS TO GENERATE 1F AND 2F SIGNALS
Figure 8. Input Data Frequency Discrimination
6-445
AFN 01795A
APPLICATIONS
Startup
The data separator is designed to require reception of
eight valid sync bits (one sync byte) before enabling the
PLL oscillator and, attempting to synchronize with the
input data stream (see Figure 9). This delay ensures that
the PLL will not erroneously synchronize outside a valid
sync field in the data stream if the VCO signal is enabled
slightly early. The sync bit counter is asynchronously
reset by the CNTEN signal when valid'sync data is not
being received by the drive.
Once the VCO signal is active and eight sync bits have
been counted, the CNT8 signal is enabled, This signal
turns on the PLL oscillator. Note that this oscillator
starts synchtonousli with the rising edge of the disk input data (because CNT8 is synchronous with the data
rising edge) and the oscillator also starts at its center frequency of 2 MHz (because the LM348 filter input is held
at its center voltage of approximately 2.5 volts). This
f~equency is divided by two and four to generate the
2XBR signal (1 MHz for MFM and 500 KHz. for FM).
READ DATA
FREQDISe
2F~L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _
CNTEN~L-________________~____~______________________________
Veo
-
CNn----------------------------______________________
~
nnnnnnnnnnnnnnn
PLCLK ________________________________-.-'-__-:-________......
2XBA ______________________________________________________ ~
PDCLR ______________________________________________________ ~
PUCLR-----------------------------:-----------------------------,LJ
pu
_________--'-_______________________~n~~n~---
PD-----------,U
LJ
--'-_1L.JLf"
DW _ _ _ _ _ _ _ _ _ _ _- - : - -_ _ _
Figure 9. Typical Data Separator Startup Timing Diagram
6-446
AFN 01795A
APPLICATIONS
PLL Synchronization
Processor and Memory
At this point, the PLL is enabled and begins to synchronize with the input data stream. This synchronization is accomplished very simply in the following manner. The pump up (PU) signal is enabled on the rising
edge of the READ DATA from the disk drive. (When
the PLL is synchronized with the data stream, this point
will occur at the same time as the falling edge of the
2XBR signal as shown in Figure 9). The PU signal is
turned off and the PO signal is activated on the next rising edge of the 2XBR clock. With this scheme, the difference between PU active time and the PO active time
is equal to the difference between the input bit rate and
the PLLdock rate. Thus, if PU is turned on longer than
PO is on, the input bit rate is faster than the PLL clock.
A high-performance 8088 eight-bit microprocessor
(operating at 5 MHz with no wait states) controls system
operation. The 8088 was selected because of its memory
addressing capabilities and its sophisticated string
handling instructions. These features improve the speed
of data base search operations. In addition, these
capabilities allow the system to be easily upgraded with
additional memory, disk drives, and if required, a bub.
ble memory or winchester disk unit.
As long as PU and PO'are both inactive, no charge is
transferred to or from the LM358 input holding
capacitor, and the PLL output frequency is maintained
(the LM358 operational amplifier has a very high input
impedance). Whenever PU is turned on, current flows
from the + 5 volt supply through a 20K resistor into the
holding capacitor. When the PO signal is turned, on;
current flows from the bolding capacitor to ground'
through a 20K resistor. In this manner, both the pump
up and pump down charging rates are b8Ianced.
The change in capacitor charge (and therefore voltage)
after a complete PU/PO cycle is proportional to the difference between the PU and PO pulse widths and is also
proportional to the frequency difference between the incoming data stream and the PLL oscillator. As the
capacitor voltage is raised (PU active longer than PO),
the PLL oscillator time constant (RC of the 96LS02) is
modified by the filter output (LM358) to raise the
oscillator frequency. As the capacitor voltage is lowered
(pO active longer than PO), the oscillator frequency is
lowered. If both frequencies are equal, the voltage on
the holding capacitor does not change, and the PLL
oscillator frequency remains constant.
The schematics 'for the basic design provide 8K bytes of ,
2732A high-speed EPROM program storage and 8K
bytes of disk directory and file buffer RAM. This ,
memory can easily be expanded to 1 megabyte for
performance upgrades.
An 8259A Programmable Interrupt Controller (PIC) is
also included in the design to field interrupts from both
the serial port and the' FOC. This interrupt controller
provides a large degree of programming flexibility for
the implementation of data base functions in an asynchronous, demand driven environment. The PIC allows
the system to accumulate asynchronous data base requests from all serial I/O ports while previously
specified data base operations are.currently in' progress.
This feature 'is made possible by the ability of the 8251A
RXROY signal to cause a processor interrupt. After
receiving this interrupt, the processor can temporarBy
halt work on existing requests and enter the incoming
information into a data qase request buffer. Once the
information has been entered into the buffer, the system
can resume its previous processing.
In addition, the PIC permits some portions of data base
requests to be processed in parallel. For example, once a
disk record has been'loaded into a memory buffer, a
memory search can proceed in parallel with the loading ,
of the next record. After the FOC completes the record
transfer, the memory search will be interrupted and the
processor can begin another disk transfer before resuming the memory search.
6. AN INTELLIGENT DISKETTE
DATA BASE SYSTEM
The bus structure of the system is split into three functional buffered units. A 2O-bit address from the processor is latched by three-state transparent 74LS373
devices. When the processor is in control of the address
and data busses, these devices are output enabled to the
system buffered address bus. All I/O devices are placed
directly 011 the local data bus. Finally, the memory data
bus is isolated from the local data bus by an 8286 octal
transceiver. The" direction of this transceiver is determined by the Memory Read signal, while its output
enable is activated by a Memory Read or Memory Write
command..
The system described in this application note is designed
to function as an intelligent data base controller. The
schematics for this data base unit are presented in Appendix A; a block diagram of the unit is illustrated in
Figure 10. As designeQ, the unit can access over four
"million bytes of mass storage on four floppy disk drives
(using a single 8272 FOq; the system can easily be expanded to four FOC devices (and 16 megabytes of online disk storage). Three serial data links are also included. These data links may be used by CRT terminals or
other microprocessor systems to access the data base.
6-447
AFN 01795A
APPLICATIONS
I
CLOCK
G,ENERATOR
(8284)
---.~
~ ADDRESS
I-LATCH
,
~
~
8-11T LOCAL DATA BUS
PROCESSOR
(8088)
~
r-frfrr-
110 AND MEMORY COMMANDS
INTA
INT
.HOLD
t
HLDA
~
DMA
CONTROLLER
(8237'2)
a:: a::
I--. - - I---
t
t
DACK.
FLEXIBLE DISKETTE CONTROLLER
1t,
n
VCo.MFM
(EAD DATA
I.
RECEIVERS
itt
i
f-Jl
DATA BUS
TRANSCEIVER
(8288)
;..
I
. PHASE
LOCKED
LOOP
(PLL)
DATA
SEPA·
~
READY
RD,WR,CS
8-BIT COCAL DATA BUS
-JJ~
PROCIIIAMMABLE
INTERRUPT
CONTROLLER
(82SBA PIC)
DATA
(8272FDC)
~
(2114·3)
I/O AND
CS
MEMORY
ADDRESS f RD,WR,CS
R
DECODE
I
~~~
1Ir'
I--
~
DRO
2732A
~~~
I~ADPRESS~
LATCHI
-BUFFER
~
rl- I
l-
I-
SERIAL 110 PORTS
(8251A USARTs)
l-
I--
I-I--
lAUD
RATE
GENERATOR
I--
(8253 PIll
~~:~
'----RxD
hD
AxD
INDEX
WRITE PROTECT
TWO SIDED
FAULT
TR"ACKO
READ DATA
DRIY.!RS
III
DRIVE SELECT
DIRECTION
STEP
WRITE GATE
FAULT RESET
LOW CURRENT
SIDE SELECT
HEAD LOAD
WAITE DATA
Figure 10. IntelJlgent Date Ba8e Block Diagram
6-448
AFN 01795A
APPLICATIONS
SertalUO
The three RS-232-C compatible saial 110 ports operate
at software-programmable baud rates to 19.2K. Each
110 port is contronedby an 8251A USAllT (Universal
Synchronous/Asynchronous Receiver/Transmitter).
Each USAllT is individually programmable for operation in many synchronous and asynchronous serial data
transmission formats fmcluc:ling mM Bi-sync). In
operation, USART error detection circuits can check
for parity, data oVemQ1, and framing errors. An 8253
Programmable Interval Timer is employed to generate
the baud rates for the serial 110 ports.
The Transmitter Ready and ReCeiver Ready output
signals of the 8151As are routed to the interrupt inputs
of ~e 8159A interrupt controner. These signaI:s interrupt processor execution when a data byte is received by
a USART and also when the USART is ready to accept
another data byte for transmission.
DMA
The 8272 FDC interfaces to system memory by means of
an 8237-2 high-speed DMA controner. Transfers between the disk controner and memory also operate with
no wait states when 2114-3 (ISO ns) or faster static RAM
is used. In operation, the 8272 presents a DMA request
to the 8237 for every byte of data to be transferred. This
request causes the 8273 to present a HOLD request to
the 8088. As soon as the 8088 is able to relinquish
dataladdress bus control, the processOr signaI:s a HOLD
acknowledge to the 8237. The 8237 then assumes control over the data and address busses. After latching the
address for the DMA transfer, the 8237 generates
simultaneous 110 Read and Memory Write commands
(for a disk read)' or simultaneous 110 Write and
Memory Read commands (for a disk write). At the same
time, the 8272 is selected as the 110 device by means of
the DMA acknowledge signal from the 8237. After this
su.sie byte has been transferred between the FDC and
memory, the DMA controner releases the dataladdress
busses to the 8088 by deactivating the HOLD request. In
a short period of time (13 1'5 for double-density and 27
1'5 'for su.sie-density) the FDC requeSts a subsequent
data transfer. This transfer occurs in exactly the same
manner as the previous transfer. After an data transfers
have been completed (specified by the word count pr0grammed into the 8237 before the FDC operation was
initiated), the 8237 signaI:s a terminal count (BOP pin).
This terminal count si&naI informS the' 8272 that the
data transfer is complete. Upon reception of this terminal Count signal, the 8272 halts DMA requests and
initiates an "operation complete" interrupt.
.
sitlce the system is designed for 2O-bit addressing, a
'four-bit DMA-address latch is included as a processor
addressable 110 port. The prqc:essor writes the upper
four DMA address bits before a data transfer. When the
DMA contro8er assumes bus control, the contents of
this latCh are output enabled on the upper four bits of
the address bus. The only restriction in the use of this
address 1atch is that a single disk read or write transfer
cannot cross a 64K memory boundary.
Disk Drive Interface
The 8272 FDC may be interfaced to a lIUIlIimum of four
eight-inch floppy disk drives. Both su.sie- and doubledensity drives are accommodated using the data separation circuit described in section S. In addition, su.sie- or
dual-sided disk drives may be used. The 8272 is driven
by an 8 MHz crystal contro8er clock produced by an,
8224 clock generator.
Drive select signaI:s are decoded by means of a 74LS139
from the 080, OSI outputs of the FDC. The fault reset,
step, low current, and direction outputs to the disk
drives are generated from the FRlSTEP, LCI'/DIR,
and RW/SEEK FDC output signaI:s by means of a
74LS240. The other half of the 74LS240 functions as an
input multiplexer for the disk write protect, two-sided,
fault, and track zero status signals. These signaI:s are
multiplexed into the WPITS and FLTITRKO inputs to
the 8272.
The 8272 write clock (WR eLK) is generated by a ring
counter/multiplexer combination. The write clock frequency is 1 MHz for MFM recording and SOO KHz for
PM recording (selected by the MFM output of the
8272). The pulse width is a constant 150 ns. The write
clock is constantly generated and input to the FDC (during both read and write operations). The FDC write
enable output (WE) is transmitted directly to the write
gate disk drive input.
Write data to the disk drive is preshifted (according to
the PSO, PSI FDC outputs) by the combination of a
74LSI7S four-bit latch and a 74LS1S3 multiplexer. The
amount of preshift is completely controned within the
8272 FDC. Three cases are possible: the data may be
written one clock cycle early, one clock cycle late, or
with no in'eshift. The data preshift circuit is activated by
the FDC only in the double-density mode. The preshift
is required to cancel predictable playback data shifts
when recorded data is 1ater read from 'the floppy disk.
A su.sie SO-conciuctor flat cable connects the board to
the floppy disk drives. FDC outputs are driven by 7438
open conector high-currCnt line-drivers. These drivers
are resistively terminated On the last disk drive by means
ofa ISO ohm resistor to +SV. The line receivers are 7414
Schmitt triggered inverters with ISO ohm puR-up
resistors on board.
6-449
AFN01195A
APPLICATIONS
7. SPECIAL CON,SIDERATIONS
This section contains a quick review of key features and
issues, most of which have been mentioned in .other sections of this application note. Before designing with the
8272 FDC, it is advisable that the information in this
section be completely understood.
1. Multl·Sector Transfers
The 8272 always operates in a multi-sector transfer
mode. The 8272 continues to transfer data until the TC
input is activated. In a DMA configuration, the TC input· of the 8272 must always be connected to the
EOP/TC output of the OMA controller. When mUltiple
DMA channels are used on a single OMA controller,
EOP must be gated with the select signal for the proper
FDC. If the TC signal is not gated, a terminal count on
another channel will abort FDC operation.
In a processor driven configuration with no DMA controller, the system must count the transfers and supply a
TC signal to the FOC. In a DMA environment, ORing a
programmable TC with the TC from the DMA controller is a convenient means of ensuring that the processor may always gain control of the FDC (even ifihe
'diskette system hangs up in an abnormal manner).
2. Processor Command/Result Phase Interface
In the command phase, the processor must write the exact number. of parameters in the exact order shown in
Table 5. During the result phase, the processor must
read the complete result status. For example, the Format Track command requires six command bytes and
presents seven result bytes. The 8272 will not accept a
new command until all result bytes are read. Note that
the number of command. and result bytes varies from
command-to-command. Command and result phases
cannot be shortened.
During both the command an.d result phases, the Main
Status Register must be read by the processor' before
each byte of inform;ltion is read from, or written to, the
FDC Data Register. Before each command byte is written, 010 (bit 6) must be low (indicating a data transfer
from the processor) and RQM (bit 7) must be high (indicating that the FDe is ready for, data). During the
result ,phase,DIO must be high (indicating a data
transfer to the processor) andRQM must also. be high
(indicating that d~ta is ready for the prQcessQr).
NOTE: After the 8272 receives a command byte, the
RQM flag may remain set for 12 microseconds
(with an 8 MHz, dock). Software should not attempt to read the Main Status Register b~ore
this time interval has elapsed; otherwise, the
software will erroneously assume that the FDe
is ready to accept the nel't byte,
3. Sector Sizes
The 8272 does not support 128 byte sectors in the MFM
(double-density) mode.
4; 'Write Clock
The FOC Write Clock input (WR CLK) must be present
at all times.
5. Reset
The FDC Reset input (RST) must be held active during
power-on reset while the RD and WR inputs are active.
If the reset input becomes inactive while RD and WR
are still active, the 8272 enters the test'mode. Once activated, the test mode can only be deactivated by a
power-down condition.
6. Drive S.tatus
The 8272 constantly polls (starting after the power-on
reset) all drives for changes in the drive ready status. At
power-on, the FDC assumes that all drives are not
ready. If a drive application requires that the ready line
be strapped active, the FDC will generate an interrupt
immediately after power is applied.
7. Gap Length
Only the gap 3 size is software programmable. All other
gap sizes are fixed. In. addition, different gap 3 sizes
must be specified in format, read, write, and scan commands .. Refer to Section 3 and Table 9 for gap size
recommendations.,
.,
.
8. Seek Command
The drive busy flag in the Main Status Register remains
set after a Seek command is issued until the Sense Interrupt Status command is issued (following reception of
the seek complete interrupt). '
.
.
' I "
The FDC does not perform implied seeks. Before issuing data read or write commands, the read/write head
must be positi~ed over the correct cylinder. If the head
is not positioned correctly, a cylinder address error is
generl!lted.
After issuing a step pulse, the 8272 resumes drive status
polling. For correct stepper operation in this mode, the
stepper motor must be constantly enabled. (Most drives
provide a jumper to permit the stepper motor to be constantly enabled.)
,
.
9. Step Rate
'The 8272 can emit a step puise that is. one millisecond
faster than the rate progriunmed by the'SRT parameter
in the Specify command., This ,action .may cause subsequent sector' not found errorli. The step rate time should
be programmed to be 1 ms longer than the step rate time
required by the drive.
10. Cable Length
A cable length of less than 10 feet is recolllmended for
drive interfacing.
6-450
AFN 01795A
APPLICATIONS
11. Scan Commands
The current 8272 has several problems when using the
scan commands. These commands should not be used at
this time.
is low), the FDC terminates the command after reading
all the data in the sector.
14. Bad Track Maintenance
The 8272 does not internally maintain bad track information. The maintenance of this information must be
performed by system software. As an example of typical
bad track operation, assume that a media test determines that track 31 and track 66 of a given floppy disk
are bad. When the disk is formatted for use, the system
software formats physical track 0 as logical cylinder 0
(C=O in the command phase parameters), physical
track 1 as logical track 1 (C = I), and so on, until
phy.sical track 30 is formatted as logical cylinder 30
(C = 30). Physical track 31 is bad and should be formatted as logical cylinder FF (indicating a bad track). Next,
physical track 32 is formatted as logical cylinder 31, and
so on, until physical track 67 is formatted as logical
cylinder 64. Next, bad physical track 66 is formatted as
logical cylinder FF (another bail track marker), and
physical track 67 is formatted as logical cylinder 6S.
This formatting continues until the last physical track
(77) is formatted as logical cylinder 75. Normally, after
this formatting is complete, the bad track information is
stored in a prespecified area on the floppy disk (typically in a sector on track 0) so that the system will be able
to· recreate the bad track information when the disk is
removed from the drive and reinserted at some later
time.
12. Interrupts
When the processor receives an interrupt from the FDC,
the FDC may be reporting one of two distinct events:
a) The beginning of the result phase of a previously requested read, write, or scan command.
b) An asynchronous event such as a seek/recalibrate
completion, an 'attention, an abnormal command
termination, or an invalid command.
These two cases are distinguished by the FDC busy flag
(bit 4) in the Main Status Register. If the FDC busy flag
is high, the interrupt is of type (a). If the FDC busy flag
is low, the interrupt was caused by an asynchronous
event (b).
A single interrupt from the FDC may signal more than
one of the above events. After receiving an interrupt,
the processor must continue to issue Sense Interrupt
Status commands (and service the resulting conditions)
until an invalid command code is received. In this manner, all "hidden" interrupts are ferreted out and
serviced.
13. Skip Flag (SK)
The skip flag is used during the execution of Read Data,
Read Deleted Data, Read Track, and various Scan commands. This flag permits the FDC to skip unwanted sec.
tors on a disk track.
To illustrate how the system software performs a
transfer operation disk with bad tracks, assume that the
disk drive head is positioned at track 0 and the disk
described above is loaded into the drive. If a command
to read track 36 is issued by an application program, the
system software translates this read command into a
seek to physical track 37 (since there is one bad track
between 0 and 36, namely 31) followed by a read of
logical cylinder 36. Thus, the cylinder parameter C is set
to 37 for the Seek command and 36 for the Read Sector
command .
When performing a Read Data, Read Track, or Scan
command, a high SK flag indicates that the FDC is to
skip over (not transfer) any sector containing a deleted
data address mark. A low SK flag indicates that the
FOC is to terminate the command (after reading all the
data in the sector) when a deleted data address mark is
encountered.
When performing a Read Deleted Data command, a
high SK flag indicates tbat sectors containing normal
data address marks are to be skipped. Note that this is
just the opposite situation from that described in the last
paragraph. When a data address mark is encountered
during a Read Deleted Data command (and the SK flag
.15. Head Load versus Head Settle Time.
The 8272 does not permit separate specification of the
head load time and the head settle time. When the
Specify command is issued for a given disk drive, the
proper value for the HLT parameter is the maximum of
the head load time and the head settle time.
6-451
AFN 01795A
APPLICATIONS
APPENDIX
6-452
AFN 01795A
APPLICATIONS
Power Distribution
Ref D..1g
Part
8088
8224
8237-2
82S1A
8253-5
A2
GND
40
1,20
8
20
4
12
14
201
9
10
9,16
31
26
8272
8284
8286
16
A6
A9,B9,C9
AI0
BI0
010
Al
B6,F4
2114
2732A
Fl,F2,OI,02,Hl,H2,I1,I2
O1,D2
74LSOO
74LS04
74LS27
74LS32
74LS74
74LS138
74LS139
74LSlS3
74LSlS7
74LSI64
74LS173
74LS17S
74LS240
74LS2S7
74LS367
74LS373
74LS393
El
B2,E6,E8,F8
E2,ES
Bl
A4,OS,H6
F3
EI0
13
F6
FS
03
G4
010
D3
C:3,E9
B4,C4,D4,C6
IS,F7
74S08
74S138
E4
7414
7438
82S9A
+5
24
28
40
18
20
18
24
14
14
14
14
14
16
16
16
16
14
16
16
+12
-12
I
9
12
14
7
7
7
7
7
8
8
8
8
7
8
8
10
8
8
10
7
D6,E3
14
16
7
8
H7
H8,H9,H1O
14
14
7
7
1488
1489
H3
H4
14
7
7
96LS02
96LS02
G7
16
8
G6
16
8
LM3S8
HS
8
4
20
16
16
20
,
6-453
,
14
I
AFN 01795A
APPLICATIONS
REFERENCES
6. Shugart, SA800 Series Diskette Storage Drive
Double ~nsityDesign Guide, Part No. 39000,
Shugart Associates, 1977.
7. Shugart, "Applic,ation Notes for Shugart Dual
VFO," Part No. 39101, Shugart Associates, 1980.
1. Intel, "8272 Single/Double, Density Floppy Disk
Controller Data Sheet," Intel Corporation, 1980.
2. Intel, iSBC 208 Hardware Reference' Manual,
Manual Order No. 143078, Intel Corporation,
1980.
3. Intel, iSBC 204 Flexible Diskette Controller Hardware Reference Manual, Manual Order
No. 9800568A, Intel Corporation, 1978.
4. Shugart, SA800/801 Diskette Storage Drive OEM
Manual, Part No. 50574, Shugart Associates, 1977.
5. Shugart, SA8001801 Diskette Storage Drive Theory
of Operations, Part No. 50664, Shugart Associates,
1977.
8. Pertec, "Soft-sector Formatting for PERTEC Flexible Disk Drives," Pertee Application Note, 1977.
9. Austin Lesea and Rodnay Zaks, "Floppy-disc Controller Design Must Begin With the Basics," EDN,
May 20, 1978.
10. John ,Iioeppner and Larry Wall, "Encoding/
Decoding Techniques Double Floppy Disc Capacity," Computer Design, Feb 1980.
11. John Zarrella, System Architecture, Mirocomputer
Applications, 1980.
6-454
AFN 01795A
Software Design and
Implementation of
Floppy Disk
Subsystems
Contents
1. INTRODUCTION
The Physical Interface Level
The Logical Interface Level
The File System Interface Level
Scope
this Note
0'
2. DISK I/O TECHNIQU~S
FDC Data Transfer Interface
Ove'rlapped Operations
Buffers
3. THE 8272 FLOPPY DISK CONTROLLER
Floppy Disk Commands
Interface Registers
Command/Result Phases
Execution Phase
Multi-sector and Multi-track
Transfers
Drive Status Polling
Command Details
Invalid Commands
4. 8272 PHYSICAL INTERFACE
SOFTWARE
INITIALlZE$DRIVERS
EXECUTE$DOCB
FDCINT
OUTPUT$CONTROLS$TO$DMA
OUTPUT$COMMAND$TO$FDC
INPUT$RESULT$FROM$FDC
OUTPUT$BYTE$TO$FDC
INPUT$BYTE$FROM$FDC
FDC$READY$FOR$COMMAND
FDC$READY$FOR$RESULT
OPERATION$CLEAN$UP
Modifications for
Polling Operation
5. 8272 LOGICAL INTERFACE
SOFTWARE
SPECIFY
RECALIBRATE
SEEK
FORMAT
WRITE
READ
Coping With Errors
6-455
AFN-Q1949A
'Contents (Continued)' .,
6. FILE SYSTE,MS.
File Allocation
The Intel File System
Disk File System FUnctions
7. KEY 8272 SOFTWARE
INTERFACING CONSIDERATIONS
REFERENCES
APPENDIX A-8272 FDC
DEVICE DRIVER SOFTWARE
APPENDIX 8-8272 FDC
EXERCISER PROGRAM
APPENDIX C-8272 DRIVER FLOWCHARTS
6-456
AFN-01949A
APPLICATIONS
1.
Introduction
Disk interface software is a _jor cantributor to the efficient and reliable
operation of a floppy disk subsystea. '!'bis software JlUSt be a well-cJesigned
CCJIIIPrOliise between the needs of the application. software lIodules and the
capabili ties of the floppy disk cantroller (!'DC). In an effort to .eet these
requiraaents. the 1I.pleaentatien of disk interface software is often divided
into several levels of abstraction. ~ purpose of this application note is
to define these software .interface levels and describe the design and illple.entation of a lIodular and flexible software ckiver .for the 8272 lDC. This
note is .. caipaIlion to AP-1l6. -An Intelligent Data Blase System Using the
8272.-
'rile physical. Interface Level
'f'be software interface level closest to the lDC hardware is referred. to as the
physical inteJ;face level. At this le~l. interface lIodules (often called disk
drivers or disk handlers) aa.aunicate directly with the lDC device. Disk drivers
accept floppy disk aa.aands frc:.a other software lIodul_. cantrol and aonitor the
lDC execution of the cc.aands. and finally return operational IiItatus inforaation
(at QCWIand termination) to the requesting lIodules.
In order to perfora
the~e function~.
the dr,ivers aust support the bitjbyte level
lDC interface for status and· data transfers. In addition. the drivers aust field,
classify. and service a variety of me interrupts.
fte Logical. Interface Level
Systelll and application software aodules often specify disk operation paruaeters .
that are not directly ~tible with the lDC device. This software illCClllpatibility is typically caused ~ one of the following:
,1.
'f'be change frc:.a an existing lDC to a funCtionally equivalent
design. Replacing a ftL based controller with an LSI device is
an exa.ple of a change that aay result in sOftware in~ti
bilities.
2.
'f'be upgrade.of an existing lDC subsystem' to a higher capability
design. ~ ~ion frOll a single-sided. single-density system to a dual-sided. double-density system to increase data.
storage capacity is an example of such a system change.
"
' .
3., !be abstraction. of the disk software interface to avoid redundancy. Many PDC paraaeters (,in particular, the density. gap
size. mDbex:, 9f sectors per tr,ack and nQlbeJ: of bytes per
sector) are fixed ,for a floppy disk (atter f~J:IIatting). In
fact. in aany syst_ these paraaeters are never changed during
the life of the system.
-
APPUCATIONS
4.
The requir~ment to support a software interface th~t is independent of the type of disk attached to the system. In this
'case, a system generated ("logical") disk address (driVe, head,
cylinder, and sector',nl:llDbers) must be mapped into a physical
floppy disk address. " For example, to switch between sihgleand dual-sided disks, it'may be easier and more cost-effective
for the software to treat the ,dual-sided disk as'containing
twice as many seotors per track '(52) rather than as'~aving two
sides. with this technique, accesses to sectors 1 through 26
are mapped onto head 0 while accesses to sectors 27 through 52
are mapped onto head 1.
5.
The necessity of supporting a bad track map. Since bad tracks
depend on the disk media, the bad track mapping varies from
disk to disk. In general, the system and application software
should not be concerned with calculating bad track parameters.
Instead, these software modules should refer to cylinders
logioally (0 through 76). The logical interface level procedures must map these cylinders into physical cylinder Positions in order to avoid the bad tracks;'
'
The key to logical interface software design 'is the mapping of the "logical disk
interface" (as seen by the application software) into the "physical disk interface" (as implemented by the flOppy disk drivers). This logical to physical
mapping is tightly coupled to system software design and'the mapping serves to
isolate both applications and system software from the peculiarities of the FCC
device. Typical logical interface procedures are described in Table 1.
~he
File System Interface Level
The file syst~m typically comprises'the highest level of disk interface software
used by application programs. The file system 'is designed to treat the disk as
a collection of named data areas (known as files). These files are cataloged in
the disk directory. " File system interface software permits the creation of new
files and the deletion of existing files under software control. When a file is
created, its name and disk addressat:e entered into the directorYJ when a file is
deleted, its name is removed from the directory. Application software requests
the use of a file by executing an OPEN function. Once opened, a file is
normally reserved for use by the' requesting program or 'task and the file cannot
be reopened by other tasks. When a task no longer needs to use an open file,
the task closes the ,file, releasiogit for use by other: 1:ask~.
Most file systems also support a set of file attributes that can be specified
for each file. File attributes may be used to protect files (e.g. , the WRITE
PROTECT attribute ensures that an eX'isting file cannot aCcidentally be overwritten) and to supply system configuration ihformation (e.g., a' FORMAT attribute may specify that a HIe should automatically be created on a new disk
when the disk is format,ted).
At the file system interface level, application programs need not be explicitly
aware of disk storage allocation techniques, block sizes, or file coding strategies. Only a "file name" must be presented in order to open, read or write,
and subsequently close a file.) Typical file system functions are listed in
Table 2.
6-458
AFN-ol949A
APPLICATIONS
Table 1:
Name
Description
FORMAT DISK
RECALIBRATE
Bxaaples of Logical Interface Procedures
Controls physical disk formatting for all tracks on a disk.
Formatting adds FDC recognized cylinder, head, and sector
addresses as well as address marks and data synchronization
fields (gaps) to the floppy disk media.
I
Moves the disk read/write head to track 0 (at' the outside
edge of the disk) •
Moves the disk read/write head to a specified logical
cylinder. The logical and physical cylinder numbers may
be different if bad track mapping is used.
SEEK
READ
STATUS
Indicates the status of the floppy disk drive and media. One
important use of this procedure is to determine.whether a
floppy disk is dual-sided.
READ
SECTOR
Reads one or more complete sectors starting at a specified
disk address (drive, head, cylinder, and sector).
WRITE SECTOR
Writes one or more complete sectors starting at a specified
disk address (drive, head, cylinder, and sector).
6-459
AFN-G1949A
APPLICATIONS
'I'able 2:
Hame
Disk Pile Systea Punctions
Description
OPEN
Prepare a file for processing. If ~be file is to be opened ·for
input and the file name is not found in the directory, an error
is generated. If the file is opened for output and tbe file name
is not found in the directory,_ tbe file is automatically created.
CLOSE
Terminate processing of an open file.
Transfer data from an open file to memory. The READ function is
often designed to buffer one or more sectors of data from tbe disk
drive and !'lupply tbis data to the requesting program, as required.
WRITE
Transfer data from memory to an open file. The WRITE function is
often designed to buffer dat~ from the application program until
enough data is available to fill a disk sector.
CREATE
Initialize a file and enter its name and attributes into the
file directory.
DELETE
Remove a file from tbe directory and release its storage space.
Change the name of a file in the directory.
ATTRIBO':l'E
Change the attributes of a file.
LOAD
Read a file of executable code into memory_
INI'l'DISK
Initialize a disk by formatting tbe media and establishing the
directory file, tbe bit map file, and otber system files.
_84M
APPLICATIONS
Scope of this Bote
This applicat,ion note directly addresses the logical and physical interface
levels. A complete 8272 driver (including interrupt service software) is
listed in Appendix A. In addition, examples of recalibrate, seek, format,
read, and write logical interface level procedures are included as part of
the exerciser program found in Appendix B. Wherever possible, specific
hardware configuration dependencies are parametized to provide maximum flexibility without requiring major software changes.
6-461
AFN.()1949A
ApPLICATIONS
2.
Disk I/O Techniques
One of the most important software aspects of diSk'interfacing is the fixed sector
size. (Sector sizes are fixed when the disk is formatted.) Individual bytes of
disk storage cannot be read/wrItten, instead, complete sectors must be tr,a,ns.,.
fer red between the floppy disk and system memory.
Selection of the appropriate sector size involves a tradeoff between memory
size, disk storage efficiency, and disk transfer efficiency. Basically, the
/following factors must be weighed:
1.
Memory size. The larger the sector size, the larger the memory
area that must be reserved for use during disk I/O transfers.
For example, a lK byte disk sector size requires that at least
one lK memory block be reserved for disk I/O.
2.
Disk Storage efficiency. Both very large and very small sectors
can waste disk storage space as follows. In disk file systems,
space must be allocated somewhere on the disk to link the sectors
of each file together. If most files are composed of many small
sectors, a large amount of linkage overhead information is required. At the other extreme, when most files are smaller than a
single disk sector, a large amount of space is wasted at the
end of each sector.
3.
Disk transfer efficiency. A file composed of a few large sectors
can be transferred to/from memory more efficiently (faster and
with less overhead) than a file composed of many small sectors.
Balancing these considerations requires knowledge of the intended system applications. Typically, for general purpose systems, sector sizes from 128 bytes
to lK byt~s are used. For compatibility between single~density and doubledensity recording with the 8272 floppy disk controller, 256 byte sectors or 512
byte sectors are most useful.
FDC Data Transfer Interface
Three distinct software interface techniques may 'be used to interface system memory to the FCC device during sector data transfers:
1.
DMA - In a DMA implementation, the software
to set up the DMA controller memory address
and to ihitiate the data transfer. The DMA
handshakes with the processor/system bus in
each data transfer.
2.
Interrupt Driven - The FDe generates an interrupt when a data
byte is ready to be transferred to memory, or when a data byte
is needed from memory. It is the software's responsibility to
perform appropriate memory reads/writes in order to transfer
data,from/to the FCC upon receipt of the interrupt.
3.
polling - Software responsibilities in the polling mode are
, identical to the responsibilities in the interrupt driven mode.
The polling mode, however, is used when interrupt service overhead (context switching) is too large to support the disk data
6-462
is only required
and transfer count,
controller hardware
order to perform
AFN-01949A
APPLICATIONS
rate. In this mode, the software determines when to transfer
data by continually polling a data request status flag in the
FOe status register.
The DNA mode has the advantage of permitting the processor to continue executing
instructions while a disk transfer is in progress. (This capability is especially
useful in multiprogramming environments.when the operating system is designed to
permit other tasks to execute while a program is waiting for I/O.) Modes 2 and
3 are often combined and described as non-DNA operating modes. Non-DNA modes
have the advantage of significantly lower system cost, but are often performance limited fpr double-density systems (where data bytes must be transferred
to/from the FOe every 16 microseconds).
Overlapped Operations
Some FCC devices support simultaneous disk operations on more than one disk
drive. Normally seek and reca1ibrate operations can be overlapped in this
manner. Since seek operations on most floppy drives are extremely slow, this
mode of operation can often be used by the system software to reduce overall
disk access times.
Buffers
The buffer concept is an extremely important element in advanced disk I/O
strategies. A buffer is nothing more than a memory area containing the same
amount of data as a disk sector contains. Generally, when an application program requests data from a disk, the system software allocates a buffer (memory
area) and transfers the data from the appropriate disk sector into the buffer.
The address of the buffer is then returned to the application software. In the
same manner, after the application program has filled a buffer for output,
the buffer address is passed to the system software, which writes data from the
buffer into a disk sector. In multitasking systems, multiple buffers may be
allocated from a buffer pool. In these systems, ·the disk controller is often
requested to read ahead and fill additional data buffers while the application
software is processing a previous buffer •. Using this technique, system software
attempts to fill buffers before they are needed by the application programs,
thereby eliminating program waits during I/O transfers. Figure 1 illustrates
the use of multiple buffers in a ring configuration.
6-463
AFN-Ql949A
APPLICATIONS
BUFFER #4
EMPTY
BUFFER #3
EMPTY
BUFFER #2
EMPTY
BUFFER #1
BEING
FILLED
DATA FLOW FROM DISK
INTO BUFFER
DISK
DRIVE
DISK
SU,SSVSTEM
a) The first disk read request by the application,software causes the disk subsystem to begin filling
the first empty buffer, The application software must wait until the buffer is filled before it may
continue execution.
AFN-01~
Figure 1. USing Multiple Memory Buffers for Disk 1/0
6-464
AFN'()1949A
APPLICATIONS
APPLICATION
SOFTWARE
BUFFER #1
BEING
EMPTIED
BUFFI;.R#4
EMPTY
~
BUFFER #3
EMPTY
.
BUFFER #2
BEING
FILLED
OAT A FLOW FROM DISK
INTO BUFFER
DISK
DISK
SUBSYSTEM
DRIVE
b) After the first buffer is filled, the disk system continues to transfer disk data into the next buffer
while the application software begins operating on the first full buffer.
Figure 1. Using Multiple Memory Buffers for Disk I/O (Continued)
6-465
AFN-01949A
APPUCATIONS
APPLICATION
SOFTWARE
t
BUFFER #1
BEING
EMPTIED
BUFFER #2
FULL
BUFFER #3
FULL
BUFFER #4
FULL
NO DISK TRANSFER
ACTIVE
DISK
SUBSYSTEM
c) When all empty buffers. have been filled, disk activity is stopped until the application software
releases one or more buffers for reuse.
.
AFN.()1949A
Figure 1. Using Multiple Memory Buffers for Disk 1/0 (Continued)
6-466
AFN'()1949A
APPLICATIONS
APPLICATION
SOFTWARE
BUFFER #2
BEING
EMPTIED
BUFFER #3
FULL
BUFFER #4
FULL
BUFF.ER #1
BEING
FILLED
OAT A FLOW fROM
DISK INTO BUFFER
DISK
DRIVE
DISK
SUBSYSTEM
d) When the application software releases a buffer (for reuse), the disk subsystem begins a disk
sector read to refill the buffer. This strategy attempts to anticipate application software needs by
maintaining a sufficient humber of full data buffers in order to minimize data transfer delays. If
disk data is already in memory when the application software requests it, no disk transfer delays
are incurred.
AFN'()1949A
Figure 1. Using Multiple Memory Buffers for Disk 1/0 (Continued)
6-467
AFN'()1949A
APPLICATIONS
3.
'~8272
FLOPPY DISK CONTROLLER
The 8272 is a single-chip LSI Floppy Disk Controller (FDC) that implements both
single- and double-density floppy disk storage subsystems (with up to four
dual-sided disk drives per FDC). The 8272 supports the IBM 3740 single-density
recording format (FM) and the IBM System 34 double-density recording format
(MFM). The 8272 accepts and executes high-level disk commands such as format
track, seek, read sector, and write sector. All data synchronization and error
checking is automatically performed by the FDC to ensure reliable data storage
and subsequent retrieval. The 8272 interfaces to microprocessor systems with
or without Direct Memory Access (DMA) capabilities and also interfaces to a
large number of commercially available floppy disk drives.
Ploppy Disk Co.aands
The 8272 executes fifteen high-level disk interface commands:
Specify
Sense Drive Status
Sense Interrupt Status
Seek
Recalibrate
Format Track
Read Data
Read Deleted Data
Write Data
Write Deleted Data
Read Track
Read ID
Scan Equal
Scan High or Equal
Scan Low or Equal
Each command is initiated by a multi-byte transfer from the driver software
to the FDC (the transferred bytes contain command and parameter information).
After complete command specification, the FDC automatically executes the
command. The command result data (after execution of the command) may require a
multi-byte transfer of status information back to the driver. It is convenient to consider each FDC command as consisting of the following three phases:
Command Phase:
The driver transfers to the FDC all the information
\ required to perform a particular disk operation. The
8272 automatically enters the command phase after
RESET and following the completion of the result
phase (if any) of a previous command.
Execution Phase:
The FDC performs the operation as instructed. The
execution phase is entered immediately after the
last command parameter is written to the FDC in the
preceding command phase. The execution phase
normally ends when the last data byte is transferred
to/from the disk or when an error occurs.
Result Phase:
After completion of the disk operation, status and
other housekeeping information are made available to the' driver software. After this information is
read, the FDC reenters the command phase and is ready
to accept another command.
6-468
AFN-OI949A
APPLICATIONS
Interface Registers
,
To support information transfer between the FDC and the system software, the
8272 contains two 8-bit registers: the Main status Register and the Data '
Register. The Main Status Register (read only) contains FDC status information
and may be accessed at any time. The Main Status Register (Table 3) provides
the system processor with the status of each disk drive, the status of the
FDC, and the status of the processor interface. The Data Register (read/write)
stores data, commands, parameters, and disk drive status information. The Data
Register is used to program the FDC during the command phase and to obtain
result information after completion of FDC operations.
In addition to the Main Status Register, the FDC contains four additional
status registers (STO, STl, ST2, and ST3). These registers are only available
during the result phase of a command.
Ca.aand/Result Phases
Table 4 lists the 8272 command set. For each of the fifteen commands, command
and result phase data transfers are listed. A list of abbreviations used in
the table is given in Table 5', and the contents of the result status registers
(STO-ST3) are illustrated in Table 6'.
>
The bytes of data which are sent to the 8272 by the drivers during the command
phase, and are read out of the 8272 in the result phase, must occur in the order
shown in Table 4. That is" the command code must be sent first and the other
bytes sent in the p~escribed sequence. All bytes of the command and result
phases must be read/written as described. After the last byte of data in the
command phase is sent to the 8272 the execution phase automatically starts. In
~ similar fashion, when the last byte of data is read from,the 8272 in the
result phase, the result phase is automatically ended and the 8272 reenters the
command phase.
'
It is important to note that during the result phase all bytes shown in Table 4
must be read. The Read Data command, ,for example, has seven bytes of data in the
result phase. All seven bytes must be read in order to successfully complete
the Read Data command. The 8272 will not accept a new command until all seven
bytes have been read. The number of command and result bytes varies from
command-to-command.
In order to read data from, or write data to, the Data Register during the
command and result phases, the software driver must examine the Main Status
Register to determine if the Data Register is available. The DIO (bit 6) and
RQM (bit 7) flags in the Main status Register must be low and high, respectively, before each byte of the command word may be written into the 8272. Many of
the commands require multiple bytes, and as a result, the Main Status Register
must be read prior to each byte transfer to the 8272. To read status bytes
during the result phase, DIO and RQM in the Main Status Register must both be
high. Note, checking the Main Status Register in this manner before each byte
transfer to/from the 8272 is required only in the command and result phases,
and is NOT required during the execution phase.
6-469
AFN-OI949A
APPLICATIONS
'l'able 3: Main status Register Bit' Definitions
BIT
DESCRIPTION
SYMBOL
NUMBER
:
o is seeking.
0
DOB
Disk Drive 0 BUSy.
Disk Drive
1
DIB
Disk Drive 1 BUsy.
Disk Drive 1 is
2
D2B
Disk Drive 2 Busy.
Disk Drive 2 is seeking.
3
D3 B
Disk Drive 3 Busy.
Disk Drive 3 is seeking.
4
CB
FOe BUSY.
5
NDM
Non-DNA MOde. The FOe is in the non-DNA mode when this flag is
set (1). This flag is set only during the execution phase of
commands in the non-DNA mode. Transition of this flag to a
zero' (0) indicates that the execution phase has ended. '
6
DIO
Data Input/Output. Indicates the direction of a
between the FOe and the Data Register. When DIO
is read from the Data Register by the processor,
reset ,(0), data is written from the processor to
7
RQM
seeking~
A read or write command is in progress.
data transfer
is set (1), data
when DIO is
the Data Register.
Request for Master. When set '(1,), this flag indicates that
the Data Register is ready to send data ,to, or receive data
, from" the proces~or'.
6-470
APPLICATIONS
~able
4: 8272 Ca.aand Set
DATA IUS
PHASE
AIW
I Dr
De
DS
Da liz
D4
Dol
REMARKS
PHASE
AIW
Dr De
DS
READ DATA
Command
W
W
W
W
W
W
W
W
W
MT MFM SK
0
0
0
0
1
1
0
0 HOS DSI DSO
0
0
Command
N
Data transfer
I
between the FoD
and the
STO
STI
ST2
C
H
A
N
W
W
W
W
W
W
W
W
W
MT MFM SK
0
0
0
0
0
1
1
0
0
0 HDS DSI DSO
C
H
A
N
ECI
GPl
OTl
,Execution
0 MFM SK
0
0
0
STO
ST 1
S12
C
H
R
N
W
W
W
W
W
W
W
W
W
MT MFM 0
0
0
0
0
0
0
1
0
1
0 HDS,OSI DSO
C
H
R
N
EDT
GPl
DTl
Execution
STO
STI
ST2
C
H
R
N
W
W
W
W
W
W
W
W
W
MT MFM 0
0
0
0
0
0
1
0
0
1
0 HOS OSI DSO
C
H
R
N
EDT
GPl
OTl
Execution
Result
Note: 1.
0
0
0
1
0
0
0 HOS DSI DSO
STO
STI
ST2
C
H
A
N
Command Codes
N
EDT
GPl
DTl
Data transfer
between the FDD
and the main-system.
FDC reada the
Status information
complete track
con~ents
execution
physical index
from the
mark to EOT
Sector 10 information
alter command
Result
execution
Command Codes
STO
ST 1
ST2
C
HR
N
R
R
A.
A
A
A
A
Sector 10 Information
prior to Command
execution
W
W
0
0
0 MFM 0
0
0
0
1
1
0
0
0 HOS OSI OSO
Execution
Result
Status Information
after Command
execution
Status Information
after Command
execution
Sector 10 Information
after Command
execution
AEAO 10
Command
Sector 10 Information
after Command
execution
Command ,Codes
The first correct 10
information on the
track Is stored In
Data Register
5TO
STI
ST2
C
H
R
N
A
R
R
R
R
R
R
Status information
after Command
execution
Sector 10 information
during Execution
Phase
FOAMAT A TAACK
Command
Command Codes
Sector 10 Information
pnor to Command
execution
W
W
W
W
W
W
0 MFM 0
0
0
0
0
0
1
0
1
0 HOS OSI 080
'1
Result
Status information
after Command
execution
Sector 10 Information
alter Command
execution
Command Codes
Bytes/Sector
SectorsfTrack
N
SC
GPl
0
Gap 3
Filter Byte
Execution
FOC formats an
enUre track
A
A
A
A
R
R
R
STO
ST 1
ST2
C
H
A
N
Status Information
;;after Command
execution
In this case, the 10
Information has no
meaning
SCAN EQUAL
Command
COmmand 'Codes
Sector 10 Information
prior to Command
execution
W
W
W
W
W
W
W
W
W
MT MFM SK
0
0
0
1
0
C
H
R
N
EDT
GPl
STP
Execution
Data transfer
between the FOD
and the main-system
A
R
A
R
A
R
R
REMARKS
Sector 10 information
prior to Command
execution
Execution
WRITE DELETED DATA
Command
Do
after Command
Data transfer
between the main·
system and the FDD
R
R
R
R
R
A
R
Result
Dl
C
H
R
WAITE DATA
Command
liz
Data transfer
between the FOD
and the main-system
A
R
R
R
R
R
R
Result
D3
maln~.y8tem
READ DELETED DATA
Command
'II
W
W
W
W
W
W
W
W
EDT
GPl
DTl
R
R
R
A
A
R
R
D4
READ A TRACK
Command COdes
Sector 10 Information
prior to Command
execution
C
H
R
Execution
Result
,
DATA 'US
Dl
Result
Status information
after Command
execution
Sector 10 information
after Command
execution
1
0
0
0
0 HOS OSI DSO
COmmand Codes
Sector 10 Information
pnor to Command
execution
Data compared
between the FOO
and the main·system
R
R
R
A
R
A
R
STO
STI
512
C
H
R
N
Status information
after Command
execution
Sector 10 Information
after Command
execution
Ao = 1 for all operations.
6-471
AF~I949A
APPLICATIONS
I
PHASE
RIW
J
DATA BUS
I D7
De
DS
D4
D3
D2
D,
SCAN LOW OR EQUAL
Command
W
W
MT MFM SK
0
0
0
W
W
W
W
W
W
W
, ,
Do
,
0
0
0 HOS OS1 OSO
0
C
H
R
N
EOT
GPL
STP
PHASE
Command Codes
Command
W
W
$ector 10 information
0.
DS
D4
R
R
R
R
R
R
R
STO
ST 1
ST2
C
H
R
N
W
W
W
W
W
W
W
W
W
MT MFM SK
0
0
0
1
0
1
1
0
1
0 HOS OS1 o'SO
C
H
R
N
EOT
GPL
STP
Executlo'n
A
STO
ST 1
ST2
C
H
R
N
02
DO
D,
0
0
0
0
0
0
0
0
, , ,
0
0
0
IREMARKS
Command Codes
OS" DSO
Execution
Head retracted to
Track 0
prior Command
SENSE INTERRUPT STATUS
Command
Result
W
R
R
Status information
after Command
execution
Command
W
0
0
0
,
0
W
W
0
1
0
0
0
0
0
0
_SPT _ _ _... _ H U T
HLT
Sector 10 information
0
CommSind Codes
Status information at
the end of each seek
operatlo'n about the
FOC
1
Command Codes
- NO
II
Command
W
W
0, 0
0
0
0
0
R
0
0
0
1
0
0
0 HOS OS1 OSO
SEEK
Sector 10 information
Command
execution
W
W
W
0
0
0
0
0
0
0
0
1
1
1
1
Command Codes
0 HOS OS1 OSO
C
Execution
Head IS pOSItioned
over proper Cylmder
on Dlskettl:t
INVALID
Command
W
_ _ _ _ Invalid Codes _ _ _ _
Result
R
STO
Status Information
after Command
execution
Sector 10 information
after Command
execution
Command Codes
Status information
about the FOO
ST 3
Command Codes
prior Command
Timer Settings
SENSE DRIVE STATUS
after Command
execution
0
STO
C
SPECIFY
Data compared
bet~een the FOD
and the main-system
R
R
R
R
R
R
D3
execution
Result
Result
DATA BUS
I Dr
RECALIBRATE
SCAN HIGH OR EQUAL
Command
RIW
Data compared
between the FOD
and the main-system
Execution
Result
L
I REMARKS
6-472
Invalid Command
Codes (NoOp - FOG'
goes Into Standby
State)
STO=80
(16)
AFN-ol~A
APPLICATIONS
Table 5:
SYMBOL
Ca.aan4/Result Paraaeter Abbreviations
OESCRIPTION
C
Cylinder Address.
the disk.
D
Data p~ttern.
formatting.
DSO,DSl
Disk Drive Select.
The currently selected cylinder address (0 to 76) on
The pattern to be written in each sector data field during
DSl DSO
0
0
1
1
0
1
0
1
Drive
Drive
Drive
Drive
0
1
2
3
DTL
Special Sector Size. During the execution of disk read/write pommands,
this parameter is used to temporarily alter the effective disk sector
size. By setting N to zero, DTL may be used to specify a sector size
from 1 to 256 bytes in length. If the actual sector (on the'disk)
is larger than DTL specifies, the remainder of the actual sector is not
passed to the system during read commands, during write commands, the
remainder of the actual sector is written with all-zeroes bytes. DTL
should be set to FF hexadecimal when N is not zero.
,EOT
End of Track.
GPL
Gap Length.
H
Head Address. Selected head: 0 or 1 (disk side 0 or 1, respectively)
as encoded in the sector ID field.
HLT
Head Load Time. Defines the time interval that the FDC waits after
loading the head before initiating a read or write operation. programmable from 2 to 254 milliseconds (in increments of 2 ms).
HUT
Head Unload Time. Defines the time interval from the end of the execution phase (of a read or write command) until the head is unloaded.
programmable from 16 to 240 milliseconds (in increments of 16 ms).
MFM
MFM/PM Mode Selector. Selects MFM double-density recording mode when
high, PM single-density mode when low.
MT
Multi-Track Selector. When ~et, this flag selects the multi-track
operating mode. In this mode (used only with dual-sided disks),
the FDC treats a complete cylinder (under both read/write head 0 and
read/write head 1) as a single track. The FDC operates as if this
expanded track started at the first sector under head 0 and ended at the
last sector under head 1. With this flag set (high), a multi-sector
read operation will automatically continue to the first sector under
head 1 when the FDC finishes operating on the last sector under head O.
N
Sector Size Code.
The final sector number of the current track.
The gap 3 size.
(Gap 3 is the space between sectors.)
The number of data bytes within a sector.
6-473
AFN-01949A
APPLICATIONS
NO
Non-DMA Mode Flag. When set (1), this flag indicates th~t the FDC
is to operate in the non-DMA mode. In this mode, the processor
participates in each data transfer (by means of an interrupt or by
polling the RQM flag in the Main status Register). When.reset (0),
the FDC interfaces. to a DMA controller.
R
Sector Address. Specifies the sector number to be read or written. In
multi-sector transfers, this parameter specifies the sector number of
the first sector to be read or written.
se
Number of Sectors per Track. Specifies the number of sectors per track
to be initialized by the Format Track command •.
SK
Skip Flag. When this flag is set, sectors containing deleted data
address marks will automatically be skipped during the execution of
multi-sector Read Data or Scan commands. In the same manner, a sector
containing a data address mark will automatically be skipped during
the execution of a multi-sector Read Deleted Data command.
SRT
Step .. Rate Interval. Defines the time interval between step pulses
issued by the FDC (track-to-track access time). programmable from
1 to 16 milliseconds (in.increments of 1 ms).
STO
STl
ST2
ST3
Status Register 0-3. Registers within the FDC that store status information after a command has been executed. This status information is
available to the proce'ssor during the Result Phase after command execution. These registers may only be read after a command has been
executed (in the exact order, shown in Table 4 for each command).
These registers should not be confused with the Main Status Register.
STP
Scan Sector Increment. During Scan operations, this parameter is
added to the current sector number in order to determine the next
sector to be scanned.
6-474
AFN-OI949A
APPLICATIONS
~able
6:
status Register Definitions
status Register 0
BIT
SYMBOL
DESCRIPTION
NUMBER
7,6
IC
Interrupt Code.
00 - Normal termination of command. The spe~ified command was
properly executed and completed without error.
01 - Abnormal termination of command. Command execution was
started but could not be 'successfully completed.
10 - Invalid command.
The requested command could not be executed.
11 - Abnormal termination.
During command execution, the disk
drive ready signal changed state.
5
SE
Seek End. Th~s flag is set (1) when the FOe has completed the
Seek command and the read/write bead is positioned over the
correct cylinder,.
4
Be
Equipment Check Er'ror. This flag is set (1) if a fault signal
is received from the disk drive or if the track 0 signal is
not received from the disk drive after 77 step pulses
(Re9alibrate command).
3
NR
Not Ready Error. This flag is set if a read or write command is
issued and either the drive is not ready or the command specifies
side 1 (head 1) of a single-sided disk.
2
B
Bead Address.
1,0
DS1,DSO
Drive Select. The number of the drive selected at the time of
the interrupt.
The head address at the time of the interrupt.
Status Register 1
BIT
SYMBOL
DESCRIPTION
NUMBER
7
EN
End of Track Error. This flag is set if the FDC attempts to
access a sectbr beyond th~ fina~ sector of the track.'
Undefined
6
5
DE
Data Error. Set when 'the FOe detects a'CRC'error in either the
the ID field or the data field of a sector. ;
4
OR
Overrun Error. set (during data transfers) i f the FDC does not
receive DMA or'processor service within the 'specified time
interval.
6-475
APPLICATIONS'
Undefined
3
2
ND
Sector Not Found Error.
ing conditions.
'
This flag is set by any of the follow-
a) The FOe cannot locate the sector specified in the Read
Data, Read Deleted Data, or Scan command.
b) The FOe cannot locate the starting sector specified in .
the Read Track command.
c) The FOe cannot read the ID fieid without error during
a Read ID command.
1
NW
Write Protect Error. This flag is set if the FOe detects a
write protect signal from the disk drive during the execution
of a Write Data, Write Delet,ed Data, or Format Track camnand.
o
MA
Missing Address Mark Error.
following conditions:
This flag is set oy either of the
a) The FOe cannot detect the ID address mark on the specified
track (after two rotations of the disk).
b) The FOe cannot dete~t the data address mark or, deleted data
address mark on the specified track. (See also the Me bit
of Status Register 2.)
\
Status Register 2
BIT
DESCRIPTION
SYMBOL
NUMBER
Undefined
7
6
CM
Control Mark. This flag is set when the
the following conditions:
FOe
encounters one of
a) A deleted data address mark during the execution of a Read
Data or Scan command.
b) A data address mark during the execution of a Read Deleted
Data command.
5
DD
Data Error. Set (1) when the FOe detects a CRC error in a
sector data field. This flag is not set when a CRC error is
detected in the ID field.
4
we
Cylinder Address Error. Set when the cylinder address from the
d~sk sector ID field is different from the current cylinder
address maintained within the FOe.
3
SH
Scan Bit. Set during the execution of the Scan camnand
if the scan condi tion is satisfied,.
2
SN
,Scan Not Satisfied. Set during execution of the Scan command
if 'the FDC cannot ,locate a sector on the specified cylinder
that satisfies the scan condition.
6-476
APPLICATIONS
1
BC
Bad Track Error. Set when the cylinder address from the disk
sector ID field is FF hexadecimal and this cylinder address is
different from the current cylinder address maintained within
the FDC. This all "ones" cylinder number indicates a bad track
(one containing hard errors) according to the IBM soft-sectored
format specifications.
o
MD
Missing Data Address Mark Error. Set if the FOe cannot detect
a data address mark or deleted data address mark on the specified track.
Status Register 3
BIT
SYMBOL
DESCRIPTION
NUMBER
7
FT
Fault. This flag indicates the status of the fault signal from
the selected disk drive.
6
WP
Write Protected. This flag indicates the status of the write
protect signal from the selected disk drive.
5
RDY
Ready. This flag indicates the status of the ready signal from
the selected disk drive.
4
TO
Track O. This flag indicates the status of the track 0 signal
from the selected disk drive •.
3
TS
TWo-Sided. This flag'indicates the status of the two-sided
signal from the selected disk drive.
2
H
Head Address. This flag ihdicates the status of 'the side select
signal for the currently selected disk drive.
1,0
DS1,DSO
Drive Select.
number.
Indicates the currently selected disk drive
6-477
\
APPLICATIONS
Bxecution Phase
All data transfers to (or from) the floppy drive occur during .the execution
ph'ase·. The 8272 has two primary modes of operation for data transfers
(selected by the specify command):
1) DMA mode
2) non-DMA mode
In the.DMA mode, execution phase data transfers are handled by the DMA controller hardware (invisible to the driver software). The driver software, however,
must set all appropriate DMA controller registers prior to the beginning of the
.disk operation. An interrupt is generated by the 8272 after the last data
transfer, indicating the completion of the execution phase, and the beginning of
the result phase.
In the non-DMA mode, transfer requests are indicated by generation of an interrupt
and by activation of the RQM flag (bit 7 in the Main Status Register). The
interrupt signal can be used for interrupt-driven systems and RQM can be used for
polled systems. The driver software must respond to the transfer request by
reading data from, or. writing data to, the FDC. After completing the last
transfer, the 8272 generates an interrupt to indicate the beginning of the
result phase. In the non-DMA mode, the processor must activate the "terminal
count" (TC) signal to the FDC (normally by means of an I/O port) after the
transfer request for the last data byte has been received (by the driver) and
before the appropriate data byte has been read from (or written to) the FDC.
In either mode of operation (DMA or non-DMA), the execution phase ends when a
"terminal count" signal is sensed by' the FDC, when the last sector on a track
(the EDT parameter - Table 4) has been read or written, or when an error
occurs.
Multi-sector and Multi-track
~ransfers
. During disk read/write transfers (Read Data, Write Data, Read Deleted Data,
and Write Deleted Data), the FDC will ~ontinue to transfer data from sequential
sectors until the TC input is sensed. In the DMA mode, the TC input is normally
set by the DMA controller. In the non-DMA mode, the processor directly controls
,the FDC TC input as previously described. Once the TC input is received, the FDC
stops requesting data transfers (from.the system software or DMA controller).
The FDC, however, continues to read data from, or write data to, the floppy disk
until the end of the current disk sector. During a disk read operation, the data
read from the disk (after reception of the TC input) is discarded, but the data
CRC is checked for errors: during a disk write operation, the remainder of the
sector is filled with all-zero bytes.
If the TC signal is not received before the last byte of the current sector has
been transferred to/from the system, the FDC increments the sector number by one
and initiates a read or write command for this new disk sector.
6-478
AfN.Ol949A
APPLICATIONS
The FDC is also designed to operate in a multi-track mode for dual-sided
disks. In the mUlti-track mode (specified by means of the MT flag, in the
command byte - Table 4) the Foe will automatically increment the head address
(from 0 to 1) when the last sector (on the track under head 0) has been read or
written. Reading or writing is then continued on the first sector (sector 1)
of head 1.
'
Drive Status polling
After the power-on reset, the 8272 automatically enters a drive status
polling mode. If a change in drive status is detected (all drives are assumed
to be "not ready" at power-on), an interrupt is generated. The 8272 continues
this status polling between command executions (and between step pulses in the
Seek command). In this manner, the,8272 automatically notifies the system
software whenever a floppy disk is inserted, removed, or changed by the operator.
Command Details
During the command phase, the Main Status Register must be polled by the driver
software before each byte is written into the Data Register. The 010 (bit 6) and
RQM (bit 7) flags in the Main Status Register must be low and high, respectively,
before each byte of the command may be written into the 8272. The beginning
of the execution phase for any of these commands will cause 010 to be set high
and RQM to be set low.
Operation of the Foe commands is described in detail in Application Note AP-ll6,
"An Intelligent Data Base system Using the 8272."
Invalid Commands
If an invalid (undefined) command is sent to the FOC, the FDC will terminate
the command. No inteq:upt is generated by the 8272, during this condition.
Bit 6 and bit 7 (010 and RQM) in the Main Status Register are both set indicating to the processor that the 8272 is in the result phase and the contents
of Status Register 0 must be read. When the processor reads Status Register
o it will find an 80H code indicating that an invalid command was received.
The driver software in Appendix B checks each requested command and will not
issue an invalid command to the 8272.
A Sense Interrupt Status command must be sent after '~ Seek or Recalibrate
interrupti otherwise 'the FDC will consider the next command to be an invalid
command. Also, when the last "hidden" interrupt has been 'serviced, further
Sense Interrupt Status commands will xesult in invalid command codes.
6'479
AFN.o1949A
APPLICATIONS
4.'
8272 physical Interface Software
PL/M software driver listings for the 8272 FOe are contained in Appendix A.
These drivers have been designed to operate in a DMA environment (as -described
in Application Note AP-116, "An Intelligent Data Base System U&ing the 8272").
In the following paragraphs, each dri~er procedure is described. (A description
of the driver data base variables is given in Table 7.) In addition, the modifications necessary to reconfigure the drivers for operation in a polled environment are discussed.
IRI'l',IALI ZE$DRIVBRS
This initialization procedure must be called before any FOe operations are
attempted. This module initializes the DRIVE$READY, DRIVE$STATUS$CHANGE,
OPERATION$IN$PROGRESS, and OPERATION$COMPLETE arrays as well as the
GLOBAL$DRIVE$NO variable.
EXBCU'l'E$DOCB
This procedure contains the main 8272 driver control software and_handles the
execution of a complete FOe command. EXECUTE$DOcB is called with two parameters: a) a pointer to a disk operation control block and b) a pointer to a
result status'byte. The format of the disk operation control block is illustrated in Figure 2 and the result status codes are described in Table 8.
Before starting the command phase for the specified disk operation, the command
is checked for ,validity and to determine whether the FDC is busy. (For an overlapped operation, i f the FDC BUSY flag is set - in the Main Status Register the command cannot be started, non-overlapped operations cannot be s~arted if
the FDC BUSY flag, is set, if any drive is in the process of-seeking/recalibrating,
or if an operation is currently in progress on the specified drive.)
After these checks are made" interrupts are disabled in order to set the
OPERATION$IN$PROGRESS flag, reset the OPERATION$COMPLETE flag, load a pointer
to the current operation control block into the OPERATION$DOCB$PTR array and
set GLOBAL$DRIVE$NO (if a non-overlapped operation is to be started).
At this point, parameters from the operation control block are output to the
OMA controller and the FDC command phase 'is ini tiated. After completion of the
command phase, a test is made to detetmine the type of result phase required
for the current operation. If no result phase is needed, control is immediately'returned to the callirlg program. If an immediate result phase is required,
the result bytes are input from the FOe. Otherwise, the CPU waits until the
OPERATION$COMPLETE flag is set (by the interrupt service procedure).
Finally, if an error is detected in the result status code (from the FOe), an
FDC operation error is reported to the calling program.
6-480
AfN.Ol949A
APPLICATIONS
~able
7:
Driver 'Data Base
NAME
DRIVE$READY
DESCRIPTION
A public array containing the current "ready·
status of each drive.
DRIVE$STATUS$CBANGE
A public array containing a flag for' each
drive. ~e appropriate flag i~ set whenever the ready status of a drive changes.
OPERATION$DOCB$P~
An internal array of pointers to the
operation control block currently in
progress for each drive.
OPERATION$IN$PROGRESS
An internal array used by the driver procedures tO'determine if a disk operation
is in progress on a given drive.
OPERATION$COMPLETE
An internal array used by the-driver procedures to determine when the execution
phase of a disk operation is complete.
GLDBAL$DRIVE$NO
A data byte that records the current drive
number for non-overlapped disk operations.
VALID$COMMAND
A constant flag array that indicates
whether a specified FDC cOllUDand code is
,valid.
COMMAND$LENGTH
A constant byte array specifying the number
of cOllUDand/parameter bytes to be transferred to the FDC during the COIlUDand phase.
DRIVE$NO$PRESENT
A constant flag array that indicates whether
a drive number is encoded into an FDC cOllUDand.
OVERLAP$OPERATION
A constant flag array that indicates whether
an FDC cOllUDand can be overlapped with other
cOllUDands.
NO$RESULT
A constant flag array that is used to determine when an FDC operation does not have a
result phase.
IMMED$RESULT
A con~tant flag array that indicates that an
FDC operation has a result phase beginning
immediately after the cOllUDand phase is'
complete.
roSSIBLE$ERROR
A constant flag array that indicates if an
FDC operation should be checked for an
error status indication during the result
phase.
6-481
AfN.{)1949A
APPLICATIONS
Disk Operation
Control Block (DOCB)
Address
Offset
o
,1
DMA$OP
- DMA$ADDR
3
DMA$ADDR$EXT
4
DMA$COUNT
6
DISK$COMMAND(O)
7
DISK$COMMAND(l)
8
DISK$COMMAND(2)
9
DISK$COMMAND (3)
10
DISK$COMMAND(4)
11
DISK$COMMAND(5)
12
DISK$COMMAND(6)
13
DISK$COMMAND(7)
14
'OISK$COMMAND (8)
15
DISK$RESULT(O)
'16
DISK$RESULT(l)
17
DISK$RESULT(2)
18
DISK$RESULT (3)
19
DISK$RESULT(4)
20
, DISK$RESULT(5)
21
DISK$RESULT(6)
22
MISC,
I
1
AFN-Ol949A
Figure 2. Disk Operation Control Siock (OPCS) Format
6-482
AFN-Ol949A
APPLICATIONS
~able
8:
BXBCO~$DOCB
Code
Return Status Codes
Description
o
No errors.
1
FCC busy. The requested operation cannot be started. This error
occurs if an attempt is made to start an operation before the
previous operation is completed.
2
FCC error. An error was detected by the FOe during the execution
phase of a disk operation. Additional error information is contained in the result data portion of the disk operation control
block (DOCB.DISK$RESULT) as described in the 8272 data sheet.
This error occurs whenever the 8272 reports an execution phase
error (e.g., missing address mark).
3
8272 command interface error. An 8272 interfacing error was detected during the command phase. This error occurs when the command
phase of a disk operation cannot be successfully completed (e.g.,
incorrect settittg of the DIO flag, in the Main status Register).
4
8272 result interface error. An 8272 interfacing error was detected
during the result phase. This error occurs when the result phase
of a disk operation cannot be successfully completed (e.g., incorrect
setting of the DIO flag in the Main Status Register).
5
Invalid FOe Command.
The specified operation was completed without error.
6-483
AFN-Ol949A
APPLICATIONS
PDCIR", .
This procedure performs all interrupt processing for the 8272 interface drivers.
Basically, two types of interrupts are generated by the 8272: (a) an interrupt
that signals the end.of a command execution phase and the beginning of the result phase and (b) an interrupt that signals the completion of an overlapped
operation or the occurrence of an unexpected event (e.g., change in the drive
"ready" status).
An interrupt of type (a) is indicated when the FOe BUSY flag is set (in the
Main Status Register). When a type (a) interrupt is sensed, the result bytes
are read from the 8212 and placed in the result·portion of the disk operation
control block, the appropriate OPERATION$COMPLETE flag is set, and the OPERATION$IN$PROGRESS flag is reset.
When an interrupt of type (b) is indicated (FOe not busy), a sense interrupt
status command is issued (to the FOe). The upper two bits of the result status
register (Status Register Zero - STO) are used to determine the cause of the
interrupt.. The following ,four cases are possible:
1) Operation Complete. An overlapped operation is complete. The
drive number is found· in the lower two bits of STO. The STO data
is transferred to the active operation control biock, the OPERATION$COMPLETE flag is set, and theOPERATION$IN$PROGRESS flag is
reset.
2) Abnormal Termination. A disk operation has abnormally terminated.
The drive number is found in the lower two bits of STO. The STO
data is transferred to the active control block, the OPERATION$COMPLETE flag is set, and the OPERATION$IN$PROGRESS flag is reset.
3) Invalid Command. The execution of an invalid command (i.e., a
sense interrupt command with no interrupt pending) has been attempted. This interrupt signals the successful completion of all interrupt
processing.
4) Drive status Change. A change has occurred in the "ready" status
of a disk drive. The drive number is found in the lower two bits
of STO. The DRIVE$READY flag for this disk drive is set to the
new drive "ready" status and the DRIVE$STATUS$CHANGE flag for the
drive is also set. In addition, if a command is currently in
progress, the STO data is transferred to the active control block,
the OPERATION$COMPLETE flag is set, and the OPERATION$IN$PROGRESS
flag is reset.
A~ter processing a type (b) interrupt, additional sense interrupt status commands
must be issued and processed until an "invalid command" result is returned from
the FOe. This actiqn guarantees that all "hidden" interrupts are serviced.
In addition to the major driver procedures described above, a number of support
procedures are required. These support routines are briefly described in the
following paragtaphs.
6-484
AFN-01949A
APPLICATIONS
OUTPUT$COR2ROLS$TO$DMA
This procedure outputs the DNA mode, the DMA address, and the DMA word count
to the 8237 DMA controller. In addition, the upper four bits of the 20-bit
DMA address are output to the address extension latch. Finally, the disk DMA
channel is started.
OU'l'PUT$COIlMARD$"fO$PDC
This software module outputs a complete disk command to the 8272 FDC. The
number of required command/parameter bytes is found in the CO~$LENGTH table.
The appropriate bytes are output one at a time (by calls to OUTPUT$BYTE$TO$FDC)
from the command portion of the disk ope'ration control block.
IRPUT$RBSULT$FRDM$PDC
This procedure is used to read result phase status information from the disk
controller. At most, seven bytes are read. In order to read each byte, a call
is made to INPUT$BYTB$FROM$FDC. When the last byte has been read, a check is
ma 0 then call co(~I~):
If (dir$entry.attribute and systern$flag) <> o then call co(~S~):
If (dir$entry.attribute and protected$flag) <> 0 t;hen call co(~W~):
If (dir$entry.attribure and forrnat$flag) <> o then call co(-F~):
end:
end:
end;
end dir:
AFN-Ol949A
Figure 4. Sample PLJM Directory Procedure
6-494
AFN-Ol949A
APPLICATIONS
7.
Key 8272 Software Interfacing Considerations
This section contains a quick review of Key 8272 Software design features and
issues. (Most items have been mentioned in Qther sections of this application
note.) Before',designing 8272 software drivers, it is advisabl,e that the information in this section be thoroughly understood.
1. Non-DNA Data Transfers
In systems that "operate without a DNA controller (in the polled or
interrupt driven mode), the system software is responsible for counting
data transfers to/from the 8272 and generating a TC signal to the FCC
when the transfer is complete.
2. processor Command/Result phase Interface
In the command' phase, the driver softwar,e must write the exact nUlllber of parameters
in the exact order shown in Table 5. During the result phase, the driver
must read the, complete result status. For example, the Forma,t Track command
requires six,qpmmand bytes and presents ,seven result bytes. The 8272 will not
accept a new CQIIIIIand until all, result by,tes are read. Note that the nUlllber, of
command and result bytes varies from command-to-command. Ca.aand and result
pbases cannot be sbortened.
During both the command and result phases, the Main Status Register must, be read
by the driver before each byte of information is read from, or wr'itten to,
the FCC Data Register., Before each command byte is wri tten. 010 (bit 6)
must be low (indicating a data transfer from the processor) and RQM (bit 7)
must be high ,(indicating that the FCC is ready for data). During the result
phase, 010 must be high (indicating a data transfer to the processor) and RaM
must also be high (indicating that data is ready for the processor).
Rote:
'After the 8272 receives, a command byte, the RQM flag may remain set for
approximately 16 microseconds (with an 8 MHz.'clock). The driver should not
attempt to read the Main Status Register before this time interval has
elapsed, otherwise, the driver may erroneous~y assume that ~he FCC is
ready to accept the_nex~ byte.
3. Sector sizes
The 8272 does not support 128 byte
sector~
,in the MFM (double-density) mode.
4. Drive status Changes,
The 8272 constantly polls all drives for changes in the drive ready status.
This pOlling begins immediately following RESET. An interrupt is generated
every time the FCC senses a change in the drive ready status. After reset,
the FCC assUllles that all drives are Rnot- ready". If a drive is ready
immediately after reset, the 8272 generates a drive status change interrupt.
6-495
APPLlC'ATlQNS,
5. Seek Commands
The 8212 'FCC dOes not petform implied seeks'. Before' issuing 'a data read
.or write command, the'read/~rite'head'must be positioned over' the correct
cylinder by means of an explicit seek command~ 'If the head is not posit~
ioned correctly, a cylinder address error is generated.'
6. Interrupt processing
When the processor 'receives an interrupt from the FCC, the FCC may be reporting one of two distinct events:
a) The beginning of the result phase of a previously requested
read, write, or scan command.
b) An asynchronous event such as a'seek/tecalibrate completlun,
an attention, an abnormal command termination, or an invalid
command. '
These two'cailes are 'distinguished by;the FDC BUSY flag (bit 4) in the Main
status Register. I f ttte FDC BUSY flag is high, the interrupt iso£ type (a).
If the FCC BUSY flag is low, 'the interrupt was caused by an asynchro~ous
event (b).'
'
,
"
,
A single interrupt from the FCC may signal more than one of the above events.
After receiving an interrupt, 'the processor mUst continue to issue Sense
Interrupt Status commands (and service the resulting conditions) until an
invalid command code is received. In this manner, all "hidden- interrupts are
ferreted out and serviced.
' ,
7. Skip Flag (SK)
The skip flag is used during the execution of Rea~ Data, Read Deleted Data,
Read Track, and various Scan commands. This flag 'per~its the FCC to skip
unwanted sectors on a disk track.
When performing a Read fiata~'Read Track, or Scan command, a high SK flag indicates that the FDC is to skip over (not transfer) any sector containing a
deleted data address mark. A low SK flag indicates that the FDC is to terminate the command (after reading all the data in the sector) when a deleted
'data address mark is encountered.
When perforllling a Read Deleted Dflta camiland, a high SK flag 'indicates that
sectors containing normal data address marks are to be skipped. Note that
this is just the opposite situation from that described in the last paragraph.
When a data'address mark is encountered during a Read Deleted Data command (and
the SK flag is lOW), the FDC,terminates the command after reading all the data
in the sector2
'
,,"
,
I'
'1.,'
",Of
APPLICATfONS
8. Bad Track Maintenance
The 8272 does not internally maintain bad track information. The maintenance
of this information must be performed by system software. 'AS an example of
typical bad track operation, assume that a media test determines that track
31 and track 66 of a given floppy disk are ba!!. When the disk· is formatted
for use, the system software formats physical track 0 as logical cylinder, .
o (C-O in the command phase parameters), physical track 1 as logical track 1
(C=l), and so on, until physical track 30·is formatted as logical cylinder
30 (C-30). Physcial track 31 is bad and should be formatted as logical
cylinder FF (indicating a bad track). Next, physical track 32 is formatted
as logical cylinder 31, ~nd so on, until physi~l trac~ 65 is formatted as
logical cylinder 64. Next, bad physical track 66 is formatted as logical
cylinder FF (another bad track marker), and physical track 67 is formatted
as logical cylinder 65. This formatting continues until the last phYsical
track (77) is formatted as logical cylinder 75. Normally, after this formatting
is complete, the bad track information is stored in a prespecified area on the
floppy disk (typically ina sector on ttack 0) so that the system will be able
to recreate the bad track information when the disk is removed from the drive
and reinserted at some later time.
To illustrate how the system software performs a transfer operation ,on a disk
with bad tracks, assume that the disk drive head is positioned at track 0 and
the disk described above is loaded into the drive. If a command to read track
36 is issued by an application program, the system software translates ·this
read command into a seek to physical track 37 (since there is one bad track
between 0 and 36, namely 31) followed by a read of logical cylinder 36.,
Thus, the cylinder parameter C is set to 37 for the Seek command and 36.for
the Read Sector command.
6-497
AfN.Ol949A
ARPt,lE:ATIONS
- 'f'-
'.j',
REPBRBIICBS
,
1. Int.l, ·8272"Single/DOlo1ble'Density':'Fl~pyj,Dlsk Controller Data Sheet,.
Intel' CQrpora,tion, 1980 Ii
"" .. \
\
. A~:
r "
2. Intel, "~An-"Int:elUgent Data'Base System Using the 8272,· Int:el Applioation
Notet' AP-1l6,'-198l:~:
'c, '
,"
"
,
- ,,,",,
,i","
'
'
t,'),'''' ,
..
3. Intel,.-iSse 20a Hardware Reference 'Manual, Manual'Or6er No. 143078,
Intel COl!poration, 1980.
'I:
:"
4. Intel,,,'RMX/80 User's Guide, Milnual Order No. 9800522, Il'Itel'
Corporation" 1978,
." ,
'/,1
5. Brinch Hansen,"' P., Operating System Pr incipI:es, prentice"'Hall, Inc."
,New Jersey~ 1973.
",
6.~Flores,'I.,
Computer'Software: programming Systems for Digital Computers,
prentioe":'Hall, Inc., New Jersl!y, 1965.
'7. Knuth, D. E., Fundamental Algorithms, Addison-Wesley publishing Company,
Massachusetts,' 1975.
;,
I"
'.
",
'
'
~
8. Shaw, A: C'., The Logical Design of Operating Systenis, prentice-Hall, Il'Ic. ,.
New Jersey, 1974.
W.,"
9. Watson" R.
Time -Sharing System Design Concepts~ McGraW-Hi~l, Inc.,
New,.York,' 1970.
10. Zarrella, J., Operating Systems: Concepts and principles, Microcomputer
Applications, California, 1979.
6-498 .
I
APPLICATIONS
,
"
APPENDIX A .
8272 FDC DEVICE DRIVER SOFTWARE
, .
"
,
.'1
"
"j
','
'
,t
T,
,
.,
-,"
::..'"
"
,
"
.
~,
,
--
PL/M-86 COMPILER
8272 FLOPPY DISK CONTROLLER DEVICE DRIVERS
ISIS-II PL/M-S6 Vl.2 COMPILATION OF MODULE DRIVERS
OBJECT MODULE PLACED IN :Fl:driv72.0BJ
COMPILER INVOKED BY: plm86 :Fl:driv72.pS6 DEBUG
$title('S272 floppy disk controller device drivers')
$nointvector
$optimize (2)
$large
drivers! do;
declare
/* floppy disk port def ini tions */
fdc$status$port
literally'30H',
fdc$data$port
literally '31H',
/* 8272 status port */
/* 8272 data port */
declare
/* floppy disk commands */
sense$int$status
lit~rally ~08H;;
declare
/* interrupt definitions "/
fdc$int$level
literally '33',
/* fdc interrupt level */
declare
/* return status and error codes */
e'rror
literally '0',
ok
complete
false
true
error$in
propagate$error
stat$ok
stat$busy
stat$error
stat$command$error
stat$result$error
stat$invalid
1
declare
;* masks */
busy$mask,
DIO$mask
RQM$mask
seek$mask
result$error$mask
result$drive$mask
result$ready$mask
literally
li terally
literally
literally
1i teralJ.y
literally
'1',
'3',
'0',
'1',
;not~,
' 1.t,1t.erally '(d" ,
literally "'1' ,
li terally '"2",
literally "'3"",
literally "'4"",
literally '5',
literally
literally
literally
literally
literally
literally
literally
l'
+1
"'return'
e'rr-or~,
J* fdc opera,tion cO,mpleted without errors */
/* fdc is husy, operation cannot be started */
1*
/*
/*
/"
fde operation error *1
fdc not ready for command phase */
fdc not ready for r~sult phase */
invalid fdc command "/
'lOH',
"'40H",
'SOH',
'OFH',
'aCOH',
'03H',
'08H',
declare
/* drive numbers */
max$no$drives
fdc$general
literally "3"',
literally '4',
rieclare
/* miscellaneous control
8
any$drive$seeking
command$code
DIO$set$for$input
DIO$set$for$output
extract$drive$no
fdc$busy
no$fdc$error
wait$for$op$complete
wait$for$RQM
*1
literally
literally
literally
literally
literally
literally
literally
'«input(fdc$status$port) and seek$mask) <> 0)',
'(docb.disk$command(O) and IFH)',
'«input(fdc$status$port) and DIO$mask)=O)',
'«input(fdc$status$port) and DIO$mask)<>O)',
'(docb.disk$command(l) and 03H)',
'«input(fdc$status$port) and busy$mask) <> 0)',
'possible$error(command$code) and «docb.disk$result(O)
and result$error$mask) ~ 0)',
literally 'do while not operation$complete(drive$no), end',
literally 'do while (input (fdc$status$port) and RQM$mask) = 0, end,',
deolare
9
/* structures */
dpcb$type
literally
/* disk operation control block */
'(dma$op byte,dma$addr word, dma$addr$ext byte,dma$count word,
disk$command(9) byte,disk$result(7) byte,misc byte)',
$eject
10
1
declare
drive$status$change(4) byte publiC,
drive$ready(4) byte public,
/* when set - indicates that drve status changed */
/* current statys of drives */,
AFNoOI949A
APPUCATIONS
II
declare
operation$in$progress(5) byte,
operation$complete(5) byte,
operation$docb$ptr(5) pointer,
interrupt$docb structure docb$type,
global$drive$no byte,
1
1* internal flags for operation with multiple drives *1
1* fdc execution phase completed *1
1* pointers for operations in progress *1
1* tempora~y docb·for interrupt processing *1
I*-drive number of non-overlapped operation
in progress - if any *1
declare
1* internal vectors that contain command operational information *1
nO$result(32) byte
1* no result phase to command *1
data(O,O~O,l,O,O,O,o,o,o,a,o,o,o,O,O,O,O,O,O,O,~,O,O~O,O~O,O,O,O,O,O) ,
immed$reBult(32)· byte
1* immediate result 'phase for command *1
data(O,O,O,O,l,O,O,O,l,O,O,O,O,O,o,O,O,O,O,o,O,O,O,O,O,0,0,0,0,0,0,0),
over lap$operat ion (32) byte
1* command permits overlapped'operation of drvies
12
*1
data(O,O,O,O,O,O,O,l,O,O,O,O,O,O,O,l,O,O,O,O,O,O,O,O,O ,O,O.O,O,O~O~O),
1* drive number present in command information *1
drive$no$present(32) byte
data(O,O,l,O,l,l,l,l,O,l,l,O,l,l,O,l,O,l,O,O,O,O,O,O,O ,1,OrO,~,1,O,O),
1* determi'nes if command can return with an error *1
command$length(32) byte
1* contains number of command bytes for each command *1
data(O,O,9,3,2,9,9,2,1,9,2,O,9,6,O,3,O,9,O,O,O,O,O,O,O,9,0,0,0,9,0,0),
valid$command(32) byte
.
1* flags invalid command codes *1
possible$error (32) byte
data(O,O,l,O,O,l,l,l,l,l,l,O,l,l,O,l,O,l,O,O,O,O,O,O,O,1,0,0,0,1,0,0),
data(O,O,l,l,l,l,l,l,l,l,l,O,l,l,O,l,O,l,O,O,O,O,O,O,O,1,0,0,0,1,0,0),
$eject
1**** initialization for the 8272 fdc driver. software.
.
1
14
2
15
2
3
3
3
3
3
do drv$noaO to max$no$drives,
2
operation$in$progress (fdc$qeneral) =false,
operation$complete(fdc$general)-falseJ
global$drive$no=O,
17
18
19
20
21
22
23
****1
initialize$drivers: procedure public,
1* initialize 8272 drivers *1
declare drv$no byte,
13
16
This procedure must
be called prior to execution of any driver software.
~rive$ready(drv$no).false,
drive$status$change(drv$no)afalse,
operation$in$progress(drv$no)-falseJ
operation$complete (drv$no) afalse,
endJ
2
2
e~d initialize$driversJ
24
1**** wait until the 8272 fdc is ready to receive command/parameter bytes
in the command phase. The 8272 is ready to receive command bytes
when the ROM flag is high and the OIO flag is low.
****1
25
fdc$ready$for$command: procedure byte,
1
I
1* wait for valid flag settings in status reqister *1
call ti .... n;'
26
1* wait for "master request" flag
wait$for$ROM,
27
2
30
2
32
2
else return error,
33
2
end fdc$readv$for$command,
*1
1* check data direction flag *1
if OIO$set$for$input
then return ok,
1**** wait until the 8272 fdc is ready to return data bytes in the result
phase. The 8272 is ready to return a result byte·when the ROM and DIO
flags are,both high. The busy flag in tne main status register will
remain Bet until'the iast'data byte of the result phase has been read
by the prooessor'. ' '****1'
34
1
35
2
36
fdc$ready$for$result: procedure byte,
1* wait for •. valid settings in st'atus. register *1
call time (1) ,
1* result phase has ended when the 8272 busy flag is reset *1
if not fdc$busy
then return complete,
2
,:'
,'" ~
.'
6-501
"
APPLICATIONS
/. wait for "master request" flag ./
wait$for$ROM,;
38
/. check data di'rection flag • /
if PIO$set$£or$output
then return ok:
else return error:
41
43
end fdc$readV$for$:esult;
44
/ •••• output a single command/parameter, ,byte to the" 8272 'fdc.
parameter is the byte to be output to the fdc.
• ••• /
45
46
1
2
output$byte$to$fdc. procedure(data$byte) byte;
declare data$bvte byte;
/. check to see if fdc is ready' for command ./
i f not fdc$ready$for$command
then propagate$error;
47
49
50\
51
The "data$byte"
output(fdc$data$port)=data$byte;
2
2
return ok;
end output$byte$to$fdc,
/ •••• input a single reslIlt byte from the 8272 fdc.
The "data$byte$ptr"
parameter is a pointer to the memory location that is to contain
the input byte.
52
53
54
1
2
2
• ••• /
input$byte$from$fdc. procedure (data$bvte$ptr) byte,
declare data$byte$ptr pointer,
declare
data$byte based data$byte$ptr byte,
status byte;
,
/. check to see if fdc is ready ./
status=fdc$ready$for$result,
if error$in status
then propagate$error,
55
56
/. check for result phase complete ./
58
if status=complete
then return complete:
60
61
62
2
2
2
data$byte=input(fdc$data$port),
return ok;
end input$bvte$from$fdc,
$eject
/ •••• output the dma mode, the dma address, and' the dma word count to the
8237 dma controller. Also output the high order four bits of the
address to the address ~tension latch. Finally, start the disk
dma channel.
The "docb$ptr" parameter is a pointer to the appropriate
disk operation control block.
63
64
1
2
65
2
• ••• ;
output$controls$to$dma: procedure(docb$ptr);
declare docb$ptr painter;
declare docb based docb$ptr structure docbtype;
declare
/. dma port definitions ./
dma$upper$addr$port
literally'lOH',
dma$disk$addr$port
literally'OOH',
dma$disk$word$count
literally'OlH',
dma$command$port
literally'08H',
dma$mode$port
literally'OBH',
dma$mask$sr$port
literally ',OAH',
dma$clear$ff$port
l i terallv' 'DCH' ,
dma$master$clear$port literal:ly 'OPH',
dma$mask$port
literally'OFH',
66
dma$disk$chan$start
dma$extended$write
dma$single$transfer
if docb.dma$op
67
<
literallY,'OOH',
literally'shl(l,s)',
literally 'shl (1,6)'"
1* upper
4 bits of current address */
/. current address'pott,·/'
/. word count port ./
;. command port ./
/* mode port-/
/* ma'sk set/r (the' fde busy flag
is not set when this interrupt is receiVed). "
When interrupt type (a) is received, the result bytes from the operation
are read from the 8272 and the operation complete flag is set.
When an intefrupt of type (b) is received, ,the interrupt result code is
examined to determine which of the f!'llow:in'g four' actions are indicated:
1. An overlapped option, (recalibrate or seek) has been completed'. The
result data is read from the 8272 and placed in the currently active
disk operation control block.
.
2. An abnormal termination of an operation,has.occurred. The result
data is rea05 and placed in the currently active 05isk operation
control block.
.
3. The execution of an in~lid cqmmand has been attempted. This
signals the successful cOl!'pleU!'n 'of all 'in~e,r,J::\.tpt processing.
4. The ready status of a drive haa crhange~,." Ttie, 'dr'ive$u~dy' and
"drive$ready$status' change tables are ~P4~\:ed •. :If an operation
is currel,ltly in progress on the affected dd"e. the result 'data
is placed in the currently, ac't:ive ,~Us~ opera't.i,on 'col\tr,o,l block.
After an interrupt is processe05, additionai sense interrupt status' epmmands
must be issued and processed until an invalid command result is r.turned
from the fdc. This action guarantees that all "hidden" interrupts
are serviced.
• ••• t
6-505
OI'tIQATIONS..
fdcint. procedure public interrupt fdc$int$level,
declare
invalid byte,
dr1ve$no byte,
docb$ptr pointer,
docb based docb$ptr structUTe 4ocb$type,
207
1
208
2
209
2
declare
1* interrupt port definitions *1
ocw2
literally"OB',
nseoi
literally 'shl(l,S)',
210
2
declare
1* miscellaneous flags *1
literally
result$code
result$drive$ready
literally
extract$result$dr,ive$no liter aU:!,
end$of$interrupt
literally
211
2
213
3
215
216
4
4
218
219
220
221
222
223
,4
4
4
4
3
224
225
226
2
3
3
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4
231
4
232
233
234
235
5
6
6
6
236
237
238
239
5
6
6
6
1* if the fdc is busy when .n interrupt is received, then the result
phase of the previous non-overlapped operation has bagun *1
if
fdc$busy
then do,
1* process interrupt if operation in progress *1
if global$drive$no <> 0
then dOl '
, ,
,
'
docb$ptr-operation$docb$ptr(global$drive$no-l),
if error$in input$result$from$fdc(docb$ptr)
then docb.misc-error,
else docb.misc.ok, '
operation$in$progre.s (global$dr ive$no-l) -falsej
operation$complete(global$drive$no-l)-true,
global$drive$no-O,
end,
end,
1* if the'fdc is not busy, tben either an o~erlapped operation has been
coapleted or an unexpected interrupt has occurred (e.g., drive st.tus
chsnge) *1
eUe do,
invalid-false,
do while not invslid,
1* perform a sense interrupt status operation - if errors are detectea,
in the actual fdc interface, interrupt processing is discontinued, '1
if error$in output$byte$to$fdc(sense$int$atatua) then go to ignore,
if error$in input$reault$from$fdc(@interrupt$docb) then go to ignore,
do, case result$code,
'1* case 0, - operation complete *1
do,
'
,
""
dr i ve$no-extract$result$dr i ve$n,:i"
call copy$int$result(drive$no),
end,
' ,
1* caae
240
241
242,
243
244
245
247
5
5
6
6
6
6
do,
1,-'
abnormal termination *1
.
','"
I
I
, ,dr,ive$"o-extract$rllsult~dr.ive$no"
call copy$int$result(drive$no);
en4"
1* case 2 - i~valid command *1
invalid-true;
/* case' 3 .: 'drive ready change */
40",dr ive$no-extr,ac;t$real\lt$dr
,'
"
' i
i v8$nol
call copy$int$te,ult(drive$no),
, drlve$stat'us$ch.iJjge(drive$no)l"true, "
, ,if' res~lt~di'"iv.$r.adf "
"
",'
then drive$ready(drive$no)-'true,
e1 •• dri~.$r.ady(dri~e$no)~false, ,
end,
ena,
ehd,
end;
249
250
251
6
6
5
4
3
252
253
2
2·
ignore, e~d$of$interrupt'
end fdcint,'
254
1
end drivers,
248
'.hr(interrupt$docb.disk$result(O) and'result$error$m•• k,6)',
'((interrupt$docb.di.k$result(O) .nd result$re.dy$••sk) • 0)',
'(interrupt$docb.di8k$result(0) .nd re.ult$drive$••sk)',
'output (ocw2)-n.eoi',
APPLICATIONS
MODULE INPORMATION,
CODE AREA SIZE
~ 0615H
CONSTANT AREA SIZE • OOOOH
VARIABLE AREA SIZE ~ 0050H
MAXIMUM STACK SIZE • 0032H
564 LINES READ
o PROGRAM
ERROR(S)
END OP PL/M-86 COMPILATION
1557D
OD
80D
SOD
APPLICATIONS
APPE~DIX B
8272 FOC EXERCISER PROGRAM
6-508
.
AFN-01949A
APPLICATIONS
PL/M-S~
S272 FLOPPY DISK DRIVER EXERCISE PROGRAM
COMPILER
ISIS-II PL/M-S6 Vl.2-COMPILATION OF MODULE RUN72
OBJECT MODULE PLACED IN :Fl:run72.0BJ
COMPILER INVOKED BY: plmS6 :Fl:run72.pS6 DEBUG
$title ('S272 floppy disk driver exercise program')
$nointvector
$optimi-ze (2)
$large
run72: do;
1
declare
docb$type
literally
/* disk operation control block */
'(dma$op byte,dma$addr word,dma$addr$ext byte,dma$count word,
disk$command(9) byte,disk$result(7) byte,mise byte)'1
1
declare
/* 8272 fdc commands */
literally "0"'"
fm
mfm
j.iterally "'1'" ,
dma$mode
literally "'0'" ,
non$dma$mode
literally "'1'" ,
recalibrate$command
literally '7',
specify$command
literally "'3'" ,
read$command
literally "'6"',
write$command
literally "'5"" ,
format$command
literally 'ODH',
seek$command
literally 'OFH'I
1
declare
dma$verify
dma$read
dma$write
dma$noop
1
li terally
literally
literally
literally
declare
/* disk operation control blocks */
format$docb
seek$docb
recalibrate$docb
specify$docb
read$docb
write$docb
1
structure
structure
structure
structure
structure
structure
declare
step$rate
head$load$time
head$unload$time
f iller$byte
docb$type,
docb$type,
docb$type,
docb$type,
docb$type,
docb$typel
byte,
byte,
byte,
byte,
byte,
operation$,status
interleave
byte,
format$gap
read$write$gap
index
byte,
byte,
byte,
drive
byte,
cylinder
head
tracks$per$disk
sectors$per$track
bytes$per$sector$code
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
bytes$per$sector
wo.rd;
density
multitrack
sector
'
/* disk drive head */
/* number of bytes in a sector on the disk */
1
declare
1* read and write buffers */
fmtblk(104)
byte public,
wrbuf(1024)
byte public,
rdbuf (1024)
byte public I
1
dec;lare
;*
disk format initialization tables */
sec$trk$table(3)
fmt$gap$table(S)
rd$wr$gap$table(S)
byte datal,26,lS,S),
,
byte data(lBH,2~H,3AH,O,O,36H,S4H,74H),
.byte data(07H,OEH,lBH,O,O,OEH,lBH,3SH) I
6-509
AFN'()1849A
" APPUCAT.IONS
9
1
declare
I*texternal pointer tables and interrupt vector *1
rdeptr (2)
word external,
wrbptr (2)
word external,
fbptr (2)
word external,
intptr (2)
word external,
intvec(80H)
word externalJ
10
11
12
1
2
execute$docb, procedure(docb$ptr,status$ptr) external,
declare docb$ptr pcinter, status$ptr pcinter,
end execute$docb,
13
14
1
2
inltialize$driver!l" procetJ~re externl\l,
end initialize$driversl
2
$eject
1**** specify step rate ("srt"), head load time ("hlt"j, head unload time ("hut"),
and dma or non-dma ope~ation ("nd").
****1
15
16
1
2
17
18
2
19
20
21
2
2
2
22
2
2
specify, procedure(srt,hlt,hut,nd),
declare (srt,hlt,hut,nd) byte,
specify$docb.dma$op=dma$nOOPl
specify$docb.disk$command(O)-specify$command,
specify$docb.disk$command(l)-shl«not srt)+l,4) or shr(hut,4) ,
specify$do~b.disk$command(2)D(hlt and OPEH) or (nd and I),
call execute$docb(@specify$docb,@operation$Btatus),
end specify,
1**** recalibrate disk drive
8272 automatically steps out until the track 0 signal is activated
by the disk drive.
****1
23
24
1
2
2
25
26
27
28
2
2
2
29
2
recalibrate, procedure(drv),
declare dry byte,
recalibrate$docb.dma$op-dma$nOoPl
recalibrate$docb.disk$command'(O)=recalibrate$command,
recalibrate$docb.disk$command(l).drv}
call execute$docb(@recalibrate$docb,@operation$status),
end recalibratel
1**** seek drive "drv", head (side) "hd" to cylinder acyl".
30
1
2
31
32
36
2
2
2
2
2
37
2
33
34
35
"**1
seek. procedure(drv,cyl,hd),
declare (drv,cyl,hd) byte,
seek$docb.dma$op=dma$nooPl
seek$docb.disk$command(O)-seek$command,
seek$docb.disk$command(l)=drvor shl(hd,2),
seek$docb.disk$command(2)-cyl,
call execute$docb(@seek$docb,@operation$status)l
end seekp
1**** format a ,complete side ("head") of a single floppY,disk in "drive "dry".
(single or double) is specified by flag "dens~..
t***1
38
1
39
2
U
42
2
2
43'
3
46
3
47
48
3
40
2
4
'",.1
The density,
format, procedure(drv,dens,intlve),
1* format disk *1
declare (drv,dens,intlve) byte I
declare physical$sector byte,
call recalibrate(drv)I
do cylinder=O to tracks$per$disk-l,
1* s~t sector numbers in format block to zero before computing interleave *1
do physical$sector-l to sectors$per'$track, flDtblk «physicai$sector-ll *4+2) -0, end,
1 equals, log10al sector 1 */
physioal$sector-l,
"
,
1* physical seotor
1* assign interleaved seotors *1
do sector=l to sectors$per$track,
index-(physioal$seotor-l) *41
6-510
AFN-ol_
APPLICATIONS
/. change sector and index if sector has already been assigned ./
_
do while fmtb1k(index+2) <> 0: index=index+4, physica1$sector=physica1$sector+1: end,
49
53
54
55
56
1* set cylinder, bead, sector, and size code for current sector into table *1
4
4
4
4
fmtb1k(index)=cy1inder:
fmtb1k(index+1)-head:
fmtb1k(index+2)=sector:
fmtb1k (index+3) =bytes$per$sector$code:
60
4
/. update physical sector number by interieave • /
physica1$sector=physica1$sector+int1ve:
if physica1$sector > sectors$per$track
then physica1$sector=physica1$sector-sectors$per$track:
end;
61
3
/* seek to next cylinder ./
call seek(drv,cy1inder,head):
62
63
64
65
66
67
68
69
70
73
3
3
3
3
3
3
3
3
3
3
3
3
74
2
57
58
71
72
/* set up format control block ./
formrt$docb.dma$op=dma$write:
format$docb'.dma$addr=fbptr (0) +sh1 (fbptr (1) ,4) ;
format$docb.dma$addr$ext=O;
format$docb.dma$count=sectors$per$track*4-1;
format$docb.disk$command(O)=format$command or sh1(dens,6);
format$docb.disk$command(l)=drv or sh1(head,2);
format$docb.diskfocommand(2)=bytes$per$sector$code;
format$docb.disk$command (3) =sectors$per$track;
format$docb.disk$command(4)=format$gap;
format$docb.disk$command(5)=fi11er$byte:
call execute$docb(@format$docb,@operation$status) 7
end;
end format;
/**** write sector "sec" on drive "drv" at head "hd" and cylinder "cy1". The
disk recording density is specified by the "dens" flag. Data is expected to be
in the global write puffer ("wrbuf").
• ••• /
75
76
1
2
77
78
79
80
81
82
83
84
85
86
87
88
89
2
2
2
2
2
2
2
2
2
2
2
2
2
91
92
93
2
write: ptocedure(drv,cyl,hd,sec,dens);
declare (drv,cyl,hd,sec,dens) byte;
write$docb.dma$op=dma$write:
write$docb.dma$addr=wrbptr(0)+sh1(wrbptr(1) ,4);
write$docb.dma$addr$ext=O;
write$docb.dma$count=bytes$per$sector-1:
write$docb.disk$command(O)=write$command or sh1(dens,6) or sh1(mu1titrack,7);
write$docb.disk$command(l)=drvor sh1(hd,2);
write$docb.disk$command(2)=cy1;
wr.te$docb.disk$command(3)=hd;
write$docb.disk$command(4)=sec:
write$docb.disk$command (5) =bytes$per$sector$code:
write$docb.disk$command(6)=sectors$per$track;
write$docb.disk$command (7) =read$write$gap;
if bytes$per$sector$code = 0
then write$docb.disk$command(8)=bytes$per$sector;
else write$docb.disk$command(8)=OFFH;
call execute$docb(@write$docb,@operation$status);
end write;
/****
94
95
1
2
96
97
98
99
100
101
102
103
104
105
106
107
2
2
2
2
2
2
2
2
2
2
2
2
read sector "sec" on drive "drv" at head "hd" and cylinder "'cy1 R. The
disk recording density is defined by the "dens" flag_ Oata is read into
the global read buffer ("rdbuf").
***./
read: procedure (drv,cyl,hd,sec,dens) ;
declare (drv,cyl,hd,sec,dens) byte,
read$docb.dma$op=dma$read;
read$docb.dma$addr=rdbptr (0)+sh1 (rdbptr (1) ,4);
read$docb.dma$addr$ext=O;
r~ad$docb.dma$count=bytes$per$sector-1;
,read$docb.disk$command(O)=read$command or sh1(dens;6) or sh1(multitrack,7);
read$docb.disk$command(l)=drvor sh1(hd,2);
read$docb.disk$command(2)=cy1;
read$docb.disk$command(3)=hd;
read$docb.disk$command(4)=sec;
read$docb.disk$command (5) =bytes$per$sector$codel
read$docb.disk$command(6)=sectors$per$track;
read$docb. disk$command'( 7) =read$wr i te$gap:
6·511
AFN-01949A
A'PLICATIONS
108
if bytes$per$sector$code = 0
then rj!ad$docb.disk$command(8)=bytes$per$sector,
else read$docb.disk$command(8)=OFFH,
call execute$docb(@read$docb,@operation$status),
110
111
end read;
11-2
$eject
1**** initialize system by settiQ,g up 8237 dma controller and 8259A interrupt
controller.
113
114
1
2
****/
initial!ze$system: procedure;
declare
1* 1/0 ports *1
dma$disk$addr$port
dma$disk$word$count$port
dma$command$port
dma$mode$port
dma$mask$sr$port
dma$clear$ff$port
dma$master$clear$port
dma$mask$port
dma$cl$addr$port
dma$cl$word$count$port
dma$c2$addr$port
dma$c2$word$count$port
dma$c3$addr$port
dma$c3$word$count$port
iewl
icw2
icw4
oowl
ocw2
ocw3
1*
1*
1*
1*
1*
1*
1*
1*
"'OOH",
'OlH',
"'08H"",
'OSH',
'OAH',
'OCH' ,
"'ODH",
'OFH',
'02H',
,2
2
'04H',
"OSH",
'06H',
'07H' ,
'70H' ,
'71H'
"71H":'71H' ,
'70H' ,
'70H',
output (dma$master$clear$port) =,0,
output (dma$mode$port) =dma$extended$write,
1* set all dma registers to valid values *1
output (dma$mask$port) =mask$all,
118
119
120
121
122
123
·124
125
126
127
2
2
2
2
2
2
2
2
2
128
129
130
131
132
l3l
134
135
136
,2
2
2
2
2
2
2
2
2
current address port *1
word count port *1
command por t *1
mode port *1
mask set/reset port *1
clear first/last flip-flop port
dma master clear port *1
parallel mask set port*1
"03B"',
declare
1* mise masks and literals *1
cjma$extended$write
literally 'shl,(l,5)',
dma$single$transfer
literally 'shl(l,~)',
dma$disk$mode
literally'40H',
dma$cl$mode
literally'4lH',
ama$c2$mode
literally'42H',
dma$c3$mode
'literally '43H'"
mode$8088
literally '1',
interrupt$base
literally '20H',
single$controller
literally ~shl(l,l)',
level$sensitive
literally 'shl (1,3)';
control$word$4$required literally'l',
base$icwl '
literally'lOH',
mask$all
literally'OFFH',
disk$interrupt$mask
literally '1',
115
116
117
literally
literally
literally
Ii terally
literally
li tera1ly
literally
literally
11 terally
literally
literally
literally
literally
literally
literally
literally
literally
li terally
literally
literally
1* set all addresses to zero *1
1* extended write flag *1
1* single transfer flag *1
1* master reset *1
1* set dma command mode *1
1* mask all channels *1
1* reset first/last flip-flop *1
output (dma$clear$ff$port) =0,
output (dma$disk$addr$port) =0;
output (dma$disk$addr$port) =0,
output (dma$cl$addr$port)=O,
output (dma$cl$addr$port) =0,
output(dma$c2$addr$port)=0,
output (dma$c2$addr$port)=0,
output, (dma$c3$addr$port) =0,
output (dma$c3$addr$port) =0,
1* set all word counts to valid values *1
output (dma$clear$ff$port) =0,
output (dma$disk$word$count$port) =1,
output (dma$disk$word$count$port) =1,
output (dma$cl$word$count$port) =1
output (dma$cl$word$count$port) =1
output (dma$c2$word$count$port) =1
output (dma$c2$word$count$port) =1
output (dma$c3$word$count$port) =1
output (dma$c3$word$count$port) =1
6-51 0
then do, bytes$per$sector$code=index; go to doneho; end,
else bytes$per$sector$code=shr(bytes$per$sector$code,l) ,
doneho:
sectors$per$track=sec$trk$table(bytes$per$sector$code-density);
format$gap=fmt$gap$table (shl (density,2)+bytes$per$sect or$code),
read$write$gap=rd$wr$gap$table(shl(density,2)+bytes$per$sector$code),
1* initialize system and drivers .1
call initialize$system;
call initialize$drivers;
;. reenable interrupts and give 8272 a Chance to report on drive status
before proceeding .1
enable;
call time (10);
I. specify disk drive parameters .1
call specify (step$rate,head$load$time,head$unload$time,dma$mode),
176
177
declare drive$ready(4) byte external,
end:
169
170
Then
I· disable until interrupt vector setup and initialization complete .1
disable,
149
150
151
152
153
154
155
156
157
158
159
main program:
first format disk (all tracks on side (head) O.
r.ead each sector on every track of the disk forever.
i ****/
1
;. run Single disk drive '0 *1
drivecO;
1* wait until drive ready .1
do while 1,
if drive$ready(drive)
then go to start,
start:
call format(drive,4ensity,interleave):
183
184
185
186
1
2
187
4
3
3
do while 1,
do cylinder=O to tracks$per$disk-l,
call seek(drive,cylinder,head);
do sector=l to sectors$per$track;
I· set up write buffer *1
do index=O to byteS$per$sector-l; wrbuf(index)=index+sector+cylinder; end:
6-513
190'
191
call write (drive ,cylinder ,head ,sector ,density) t
call read (drive ,cylinder ,head,seator"idensity) I
4
4
/* check read buffer against write buffer */
if cmpw(@wrbuf,@rdbuf,shr(bytes$per$sector,l)) <> OFFFFH
then haltl
192
194
195
196
4
3
2
197
1
end;
, end;
end;
end runn,
MODULE INFORMATION:
CODE AREA SIZE
- 05708
CONSTANT AREA SIZE = 00008
VARIABLE AREA SIZE = 09078
MAXIMUM STACK SIZE = 00228
412 LINES READ
o PROGRAM ERROR(S)
ENO OF PL/M-86 COMPILATION
13920
'00
23110
340
6-5J4
A~l949A
APPLICATIONS
APPENDIX C
8272 DRIVER FLOWCHARTS
6-515,
AFN-Q1949A
APPLICATIONS
RESET
-DRIVE$READY
-DRIVE$STATUS$CHANGE
-OPERATION$IN$PROGRESS
-OPERATION$COMPLETE
RETURN
-------)
RETURN
ERROR
6-516
RETURN
AFN-Ol949A
APPLICATION$
(
RETURN
COMPLETE
)
RETURN
a·517
AFN'()1949A
APptlCATIONSI
YES
6-518
AFN-01949A
APPLICATIONS
YES
REYURN
ERROR
6-519
APPLICATIONS
RETURN
INVALID STATUS
----
>=C-____C
,
ReTURN
BUSY
STATUS
ENABLE INTERRUPTS
)
•C
---,
RETURN
BUSY
STATUS
)
NO
6-520
A~I_
APPLICATIONS
CALL COPY$INT$RESULT
TO PUT OPERATION
RESULT INFORMATION
INTO THE DOCB
RESET OPERATION$INfPROGRESS
SET OPERATION$COMPLETE
RESET GLOUL$DRIVEtNO
CALL COPY$INT$REBULT
TO PUT OPERATION
RESULT INFORMATION
INTO THE DOCB
,
6-521
AfN.0194BA
APPUeA"FIONS
RESET OPERATlONSlN$PROGRESS FLAG
SET OPERATIOHSPOMPLETE FLAG
(
RETURN
6-522
)
APPLICATIONS
. ~.
NO
YES
RETURN
RESULT ERROR STATUS
NO
AFN-01949A
8271/8271·6
PROGRAMMABLE FLOPPY DISK CONTROLLER
• IBM 3740 Soft s.ctored Format Compatible
and Checking
• Int.mal. CRC Generetlon
,
• Programmable Record Length.
• Programmable Step Rate, Selll.nme, Head
Load Time, tiead Unload Index Count
• Multl·Sector Capability
• Maintain Dual Drive. with Minimum SoftWare
Overhead Expan~•.ble to 4 Drive. '
• Automatic ReadIWrlte Head Po.aitlcml"O and
Verification
.
.• Fully M~TM and MCS-85TM Compatible
• Single
+ 5V Supply
• 4O-Pln Package
The InteP 8271 Programmable Floppy Disk Controller (FOC) Is an LSI component designed to Interface one to 4 floppy
disk drives to an 8-blt microcomputer system. Its powerful control functions minimize both hardware and software
overhead normally associated with floppy disk' controllers.
Vee
FAULi'RESETIOPO
WR DATA
HSYNe
SERIAL
I"TERfA~E
,
CONTROUER
ROCAlA
DATA WINDOW
LOW,CURRENT
4MHzCLK
LOADttEAO
RESET
DIRECTION
READY 1
SEEKfSTEP
SELECT 1
WR ENBLE
DACK
ORO - - - - - - ,
PLOISS
IlACR - - - - - ,
INT
••ADVO
iiVIliY1
TiiACKO
COi,j'iiffIOPI
iNDEX
~
FiiiL'f
HlEeTO
SELECT 1
RESET
WR ENABLE
LOAD HEAD
HEI/STE'
DIRECTION
LOW CURRENT
FAULT RESETIOPO
Ci - - - - - '
INTERNAL
DATA BUS
CPU INTERFACE
SEUClO
INDEX
DRO
WR PROTECT
R5
READY 0
""
COUNT/OPI
TRKO
INT
oeo
WR DATA
OS1
OS2
FAULl
UNSEPDATA
083
D. .
DATA WINDOW
D85
CS
OSO
IHSYNe
PlOISS
DB7
OND
__-r'"
A,
~
DISK INTERFACE
Figure 1. Block Diagram
Figure 2. Pin Configuration
8271/8271·6
Table 1. Pin Description
Pin
No.
Symbol
Type
Nsme and Function
Vcc
40
+5YSuppl,.
GND
20
Ground.
Clock
3
I
Clock: A squllre wave clock.
Reset
4
I
Reaet: A high signal on the
reset Input forces the 8271 to
an idle state. The 8271 remains idle until a command is
Issued by th~ CPU. The output signals of the drive interface are forced inactive
(LOW). Reset must be active
for 10 or more clock cycles.
24
CS
DB7-DBo
WR
I
19-12
I/O
10
I
.
RD
INT
A,-Ao
9
I
Chip Select: The I/O Read
and I/O Write inputs are
enabled by the chip select
signal.
Type
Neme and Function
Fault Reset/
OPO
1
0
Fault R. .et: The optional
fault reset output line Is used
to reset an error condition
which is latched by the drive.
If this line is not used for a
fault reset It can be used as
an optional output line. This
line is set with the write special register command.
Write Enable
35
0
Write' Enable: This Signal
enables the drive write logic.
Seek/Step
36
0
SeeklStep: This multifunction line Is used during
drive seeks.
Direction
37
0
Direction: The direction line
specifies the seek direction.
A high level on this pin steps
the R/W head toward the
spindle (step-in), a low level
steps the head away from the
spindle (step-out).
Load Head
38
0
Load Heed: The load head
line causes the drive to load
the Read/Write head against
the diskette.
Low Currenl
39
0
Low Current: This line
notifies the drive ttiat track 43
or greater is selected.
Ready I,
Ready 0
5
I
32
Read, 1: These two lines indlcatethat the specified drive
is ready.
Fault
28
I
Fault: This line is used by the
drive to specify a file unsafe
condition.
Count/OPI
30
I
Count/OPl: If the optional
seekl,direction/count seek
modll.ts selected, the count
pin receives pulses to step
the R!W head to the desired
track, Other:wise, this line can
be used as ail olltlonal inpu!. '
Write Protect
33
I
Writ. Protect: This signal
specifies that the diskette inserted Is write protected.
TAKO
31
I
Track Zero: This signal indicates when the RlW head is
positioned .over track zero.
34
I
Index:.The Index.slgnal gives
an indication of the relative
position of the diskette.
Deta Bu,; The Data Bus lines
are bidirectional, thrae-state
lines (8080 data bus compatible).
-
Write: The Write signal is
used to signal the control
logic that a transfer of data
from the data bus to the 8271
is required.
Read: The Read Signal is
used to signal the control
. logic that a transfer 0.1 data
from the 8271 to the data bus
is required.
11
0
Interrupt: The interrupt signal indicates that the 8271
requireS service.
22-21
I
Addre . . Line: These two
lines are CPU Interface Register select Jines.
,
Pin
No.
S,mbol
ORO
8
0
Data Reque't: The DMA
request signal is used to request a transfer of data betwaen the 8271 and memory.
DACK
7
I
Data Acknowledge: Ttie
DMA acknowledge signal
notifies the 8271 that a DMA
cycle has baen granted. For
non-DMA transfers, this signal should be driven in the
manner of a "Chip Selec!."
:
Select 1Select 0
6
2
0
Selected Drive: These lines
are used to specify the
selected drive. These lines
are set by the command byte.
iiideX
6-525
AFN.Q0223B
intJ
Table 1. Pin Description (Continued)
Symbol'
pI-oiss
.,.
Pin
No.
Type
N.m••nd Function
?5
'I
"
',.
Pli....Lock.d O.clll/itorl
Singi. Shot: This pin is used
to specify thl' type of data
separator used. ,
29
WrltllDSta
Q
Writ. D.t.: Composite write:
data.
I
Un••par.t.d D.t.: This
Input is the unseparated data
and clocks.
I
Dat. WIndow: This is a data
window established by a
slngle-ahot or phase-locked
, oscillator data separator.
\
LJnseparated
Oa,ta,
27
OataWlndow
2~
':'
,
, ,
INSYNp
23
t,
CPU lriterface Description
"
,0"
,"
Input Synchronization: This
line is high when 8271 has attained Input data synchronization, by detecting 2 bytes of
zeros followed by an expected Address Mark. It will
stay high until the end of the
10 or data field.
This interface minimizes CPU involvement by supporting
a setQf high level COmmands anp both OMA and non-I;>MA
type data transfers and by providing hierarchical status
information regarding the result of comma,nd execution.
The CPU utilizes the,oontrol interface (see the Block
diagram) to specify the FOC commands and to determine
the result of !In executed command. This Interface 'Is
supported by five Registers which are addressed by the
CPU via the A" Ao, 1m and Vim'signals. If al'l8Q8d based
system Is"uaed; 'the Ri5 and WR signals can be driven by
the ,8228'" 'm5R and i/OW Signals. The registers are
defined as fo,lp,ws:
Command'Regl.ter
,The CPU loads ,an, ,appropriate command Into the
Command ,Register which ",as the following format:
At
Act 07 0,
os
Dill 03 02. 0,
Do
1q 10.1 1 1 I. 1 1 .I. 1 1
t'
I
COMMAND OPCOOE
SURFACE/DRIVE
ISELECT 0, 1)
FUNCTIONAL DE$CRIPTION
General
The 8271 Floppy' Disk COntroller (FOC) interfaces, either
two single or one, ,Qual floppy drive to an eight bit
microprocessor and Is fully compatible with Inte/'s
new high performance MCS-85' microcomputer system.,
With minimum external circuitry, thisinnovative controller
:supports most standard, commonly-available flexible disk
drives including the mini-floppy.
:The 8271 FOC supports-'B' comprehensive sothectored
,format which 'Is IBM' 3740 compatible 'and includes
provision for the dell1gnatlng and handling of bad tracks. It
Is a'hlgh level'controllerth"t relieves the CPU (and user) of
'many of th~ control t~s~s, a~ociated with implementing a'
floppy disk interface.:rhe ,FOC suppbrts a variety' of high
/ev~llnstructions which ililow the user to store and retrieve
data on a floppy disk without dealing with the, low le\(el
details 6f disk operlftibh,
','
"
,In addition to tile s~andarQ read/write commands, a scan
command Is supported. The scan command allows the
user"program to specify, a data pattern and instructs the
FOG,to search for tl!\at .pattern on a track. Any application'
that is requlred.to seateh the,disk for,informatlon (such as,
point of sale price lookup;'disk dlrecti>ry search, etc.l, lriay
use the scan'"cbmmahd to'reduce the CPU overhead. Once
the scan operation is initiated, no CPU intervention is
reql,ljred."
'"
:
,
.Parameter Ragllter
Accepts parameters of commands that req/Jire further
description;' 'up to five parametera may be required,
example: '
II.:.''___ _ _ _ _
EXPECTED PARAMETER
RDult Regllter
The'Result Registeris -used to supply the outcome of FOC
commafld exec!Jtlon (su,ch as a good/bad completion) to
the CPU. The stan~ari:t B~sultbyte format is:
.
At
.AO ,0, 06 Os 0403' D2 Of Do
,1011 1 0101 1 ,I 1 1 10 1
i, '
A[~:.:,;:..,
Ir
..•·
-
"
'
COMPLETION TVPE
,
DUETED OAT A. FOUND
!- !>.
~~-.,-------NOTUS~D·OO
AFN-002238 ,
827118271·6
DRQ: OMA Request
The OMA request signal Is used to request a transfer,of
data betwean the 8271 and memory.
1----
WROATA
DACK: OMA Acknowledge:
The DMA acknowledge signal notifies the 8271 that a OMA
cycle has bean granted.
RD. WR: Read, Write
The read and write signals are used to specify the
direction of the data transfer.
S£LECTO
SELECT 1
WA ENABLE
LOAD HEAD
IEEK!STE'
DIRECTION
INTERNAL
LOW CURRENT
DATA SUS
FAULT RESET!
OPO
Figure 3. 8271 Block Dlegram Showing CPU
Interface FuncUons
OMA transfers require the use of a DMA controller such as
the Inte~8257. The function of the OMA controller is to
provide sequential addresses and timing for the transfer
at a starting address determined by the CpU. Counting of
data block lengths is performed by the FOC.
To request a OMA transfer, the FOC raises ORO. OACK
and RO enable OMA data onto the bus (independently of
CHIP SELECT). DACK and WR transfer OMA data to the
FOC. If a data transfer request (read or write) is not
serviced within 31 "sec, the command Is cancelled, a late
OMA status Is set, and an interrupt is generated. In OMA'
mode, an interrupt is generated at the completion of the
data block transfer.
When configured to transfer data in non·OMA mode, the
CPU must pass data to the FOC in response to the n0'l·
OMA data requests Indicated by the status word. The
data is passed to and from the chip by asserting the'
OACK and the RO or WR signals. Chip select should be
inactive (HIGH).
Status Register
Reflects the state of the FOC.
A,
AD 0, 06 D6 Dc D3 02 0, Do
, • ' .• 1 1 1 1 1 1 1.1. ,
IIII
.
,.-~,."~1· INTEARUPT REQUEST
1 .. RESULT REGISTER FULL
REGISTERS
1· PARAMETER REGISTER FULL
L-_ _ _ _ _ _ _ _ ,,, COMMAND REGISTER FUll
' - - - - - - - - - - - - 1 "COMMAND BUSY
oa..,
Reset Register
....
Allows the 8271 to be reset by the program. Reset must
be active for 11 or more chip clocks.
ORO _ _ _- ,
INT
INT (Interrupt Line)
Another element of the control interface is the Interrupt
line (INT). This line is used to signal the CPU that an FOC
operation has been completed. It remains active until the
result register is read.
A,
"
RESET
DMA Operation
aoulNTERFACE
The 8271 can transfer data in either OMA or non OMA
mode. The data transfer rate of a floppy disk drive is high
enough (one byte every 32 Ilsec) to justify OMA transfer.
In OMA mode tl)e elements of ,the OMA interface are:
DllklNTt;RFAC'E
Figure 4. 8271 Block Diagram Showing Disk Interface
Functions
6-527
AFN.Q0223B
intJ
82711-827'1·&
Disk Drive Interface
Data Separation
The 8271 disk"drlve interface supports the h'lgh level
command structure described in the Command Description section. The 8271 maintains the location of bad tracks
and the current track location for two drives. However,
with minor, software support, this interiace,can support
four drives by expanding the two drive select lines (select
0, select 1) with the addition of minimal support hardware.
the 8271 needs only a data window to separate the data • ,
from thl! composite read data as well as to detect missing
clocks in the Address Marks.
The window generatjon logic may be i'mplemented using
either a single-shot separator or a phase-locked oscillator.
The FDC Disk Drive Interlace hlS'the following, major
functions.
Single-Shot Separator
READ FUNCTIONS
The single-shot separator approach is the lowest cost
solution.
Utilize the, user supplied data window to ,obtain the clock
and data patterns from, the un"eparated read data.
Establish' byte synchronization.
Compute and verify the 10 I!nd data field CRCs.
WRITE FI,JNCTIONS
Encode composite write data.
The FDC samples the value of Data Window on the leading
edge of Unseparated Data and determines whether the
delay from the previous pulse was a half or full bit-cell
(high input = full bit-cell, low input = half bit-cell).
PLO/SS should be tied to Ground.
Insync Pin
Compute the 10 and data field CRes and append them'to
their respective fIelds.
"
This pin gives an indication of whether the 8271 is
synchronized with the serial data stream during read
operations. This pin can be used with a phase·locked
oscillator fd~ soft and hard locking.
CONTROL FUNCTIONS
Generate the programmed step rate, head'ioad time, head
settling time, head unload delay, and monitor drive
functKms.
FOUND SYNC aiD MARK
AEAD ID FIELD BUT
TRACK OR SECTOR
INCORRECT
DATA
-}-SEPARATOR
tN SYNC
~
.
'-=..
:..
...
8271
FDC
:-.
..
FOUND
DATA MARK
NOT AN 10 MARK
~
SEEK/STEP
Di1fECfiON
COUNT!OPI
L6ADHEAD
iNDEX
tRACK 0
:-
svl
UNSEPAAATED DATA
WRITE DATA
DUA,
fLOPPY
OISK
DRIVE
,mfCfO '
S~LECT
1
tlIWCliIIlffilf
WRITE PRotEct
WRITE FAUL'f
WfufE FAULT RESETIOPO
RiAOVO'
READY 1
NOTE.
INPUTS TOCHIP MAY REQUIRE RECEIVERS
(AT LEAST PULL UPIOOWN PAIRS).
Figure 5. 8271 Disk Drive Interface
6~528
FOUND SYNC & ID MARK
ID FIELD CORRECT
/
I
FOUND SYNC. DATA MARK
READ DATA SECTOR
8271/8271-8
DATA WINDOW
RETRIGGi:RABLE
SINGLE·SHOT
2.8!ijls WINDOW*
UiliSEPARATED
DATA
8271 FDC
I
}L~/SS
*FOR MINI·FLOPPY DATA WINDOW =5.7j.ISIC
Figure 8, Single-Shot Data Separator Block Diagram
, UNSEPARATED
DATA,
los;;>100ns
Flgur.
7.
Single-Shot DIde Window nmlng
Phe_Locked OSCillator Separator
The FOC samples the value of Data Window on the leading
edge of Unseparated Data and determines whether the
pulse represents a Clock or Data Pulse.
Insync may be used to provide soft and hard locking'
control for the phase· locked oscillator.
PLO/55 should be tied to Vee (+5Vl.
UNSEPARATED
DATA
J
I
_
I·l. .---rt-__-_-__-_: ______f~ ~~:~
PLO
DATAW'NDOW .,
IN SYNC·
+5V
·OPTIONAL
Figure 8. PLO Da.. Separator Block Diagram
6-529
AFN-00223B
·DATA WINDOW MAY BE 180° OUT OF PHASE IN PLO DATA SEPARATION MODE.
)
Dllk Drlv. Conlrollnlerf,ce
Write En,bl.
The disk drive control interface performs the high level
'and programmable flexible disk drive 'operations. It
custom tailors many varied drive performance paraiheters
such as the step rate. settling time. head load time, and
head unload index count. The following is the description
of the control interface.
The Write Enable controls the read and write functions of a
flexible dislc"drive. When ~rlte,Enable Is a logical one, It
enables the drive write electronics to pass,current through
the Read/Write head. When Write Enable is a logical zero,
the drive Write circuitry Is disabled and the ReadlWrite
head detects the magnetic flux transitions recorded on a
diskette. The write current turn-on is as follows.
"
WRliTEDAT!....Jl.....JL ____
--t
WRITE ENABLE
~
~twE-t
I-tWE
•
..._ _ __
Flgur. 10. Writ. En,bl. TIming
6.0530
8271/8271-6
Seek Control
Seek Control is accomplished by Seek/Step, Direction,
and Count pins and can be Implemented two ways to
provide maximum flexibility In the subsystem design. One
instance is when the programmed step rate is not equal to
zero. In this case, the 8271 uses the Seek/Step and
Direction pins (the Seek/Step pin becomes a Step pin).
Programmable Step timing parameters are shown.
The Direction pin is a contro1level indicating the direction
in which the R/W head is stepped. A logic high level on this
line moves the head toward ~he spindle (step-in). A logic
low level moves the he~d away from the spindle (step-out).
Another instance Is when the programmable step rate Is
equal to zero, In which case the 8271 holds the seek line
high until the appropriate number of user-supplied step
pulses have been counted on' the cOUht'input pin.
DIRECTION
~
nL
____
SEEK/ST~ _ _ _ _ _.......
-1
~ ts --l
~tps
tps=tos=tso =1 OilS
STANDARD: 1ms';; ts';; 255ms
MINI-FLOPPY: 2ms.;; ts';; 510ms
Figure 11. Seek Timing
SEEK/ST_E_P_ _ _
~I
-.l
I
----l
i-tsc
COUNT
l-tc
.~ •• 1
!Pc
!-tes
-------1fL--LAST COUNT
tos=tso =tcs=1 OilS
tsc >11ls
tpc",20llS
te> 1ms
Figure 12.
~eek/Step/Count
Timing
AFN-00223B
Htad Saek'SeHII,ng TIme
T,he 8271 allows the head settling time to be programmed
'
from 0 to 255ms, in,increments of lms.
The head settling time is defined as the interval of time
from completion of the last step to the time when reading
or writing on the diskette is possible (A/W Enable). The
AIW head is assumed loaded.
'
~LASTSTEPCOMPLETE
SEEK OR LAST STEP
WRITE/READ E;NABLE
.... I~ r______......,1----
STANDARD: Q.;;;*tsw<;;255ms
, *RIW HEAD IS AS$!JMED LOADED.
MINI·FLOPPY: 0 <;;*tsw'; 510ms
FIgure 13. Head Load SettlIng TImIng
Load Head
When active, load head output pin causes the drive's
read/write head to be loaded on the diskette. When the
head is initially loaded, there is a programmed delay (0 to
60ms in 4ms increments) prior to any read or write
operation. Provision is also made to unload the head
,following an operation within a programmed number of
diskette revolutions.
LOAD HEAD
_.----------_.1.
,"'-----------
tLW-J
EARLIEST WRITE ENABLE
OR INTERNAL READ DATA
r., I
STANDARD: 0<;; tLW <;; Iiams
MINI·FLOPPY: 0<;; tLW <;; 120ms
Figure 14. Head Load to Read/Write TIming
6-532
inter
8271/8271 ••'
Index
The Index input is used to determine "Seqtor no~·found"
status and to Initiate format trac!'
Bit 5:
COMMAND BUSY
COMMAND REG FULL
Deleted Oata Found: This bit is set when deleted data is
encountered during a transaction.
PARAMETER REG FULL
Bit 7: Command Busy
Bits 4 and 3: Completion Type
The command busy bit is set on writing to the command
register. Whenever the FOC is busy processing a
command, the command busy bit is seltoaone. Thisbit is
~et to zero after the command is completed.
The completion type field provides general information
regarding the outcome of an operation.
The completion type field provides general information
regarding the outcome of an operation.
Bit 6: Command Full
Completion
Type
The command full bit is set on writing to the command
buffer and cleared when the FOC begins processing the
command.
'
Bit 5: Parameter Full
00
01
10
This bit indicates the state ofthe.parameterbuffer. This bit
is set when a parameter is written to the FOC and reset
after the FOC has accepted the parameter.
11
6-536
Event
GoOd Completion"": No Error
System Error - recoverable errors;
operator intervention probably required
for recovery.
.
Command/Drive Error - either a program
error or drive hardware failure.
AFN-002238
inter
827118271-8
Blia 2 and 1: Completion Code
It is important to note the hierarchical structure of the
result byte. In very Simple systems where only a GO-NO
GO result Is required, the user may simply branCh on a
zero result (a zero.result is a good completion). The next
level of complexity Is at the completion type Interface. The
completion type supplies enough Information so that the
software may distinguish between fatal and non-fatal
errors. If a completion type 01 occurs, ten retries should
be performed before the error is considered un ....
coverable.
'
The completion code field provides more detailed
information about the completion type (See Tablel.,
Completion
Completion
Type
Code
Event
00
00
00
01
10
,11
00
01
10
11
00
01
10
11
00
01
10
11
00
00
01
01
01
01
10
10
10
10
11
11
11
11
Good Completion/
Scan Not Met
Scan Met Equal
Scan Met Not Equal
Clock Error
Late OMA
10 CRC Error
Data CRC Error
Drive Not Ready
Write Protect
Track 0 Not Found
Write Fault
Sector Not Found
The Completion Type/Completion Code Interface supplies the greatest detail about each type of completion.
This Interface is used when detailed information about the
transaction completion is required.
Bit 0:
Not used (zero returned).
Table 3. Completion Code Interpretation
Interpretetlon
DeIInlUon
Successful Completionl
Scan Not Met
The diskette operation spaclfied was completed without error If scan operation
was specified. the pattern scanned was not foun~ on the track addressed.
Scan Met Equal
The data pallern specified with the scan command WIIS found on the track
'addressed with the speCified comparison. and the equality was mel.
Scan Met Not Equal
The data pattern specified with the scan command was found With the
specified comparison on the track addressed. but the equahty was not met.
Clock Error
-Late DMA
During a diskette read operation. a clock bit was missing (dropped), Note that thiS •
function is disabled when reading any of the 10 address marks (which contaon
,missing clock pulses), If this error occurs. the operation is termonated immedi·
ately and an interrupt is generated.
During either a diskette read or write operation. the data channel did not respond
within the allotted tom" Interval to prevent data from beong overwritten or lost ThiS
error Immediately terminates the operation and generates an interrup\
10 Field CRC Error
The CRC word !tWO bytes) derived from the data read on an 10 field did not match
the CRC word written in the 10 field when the track was formatted If thiS error
occurs. the associated diskette operation IS prevented and no data IS transferred.
Data Field CRC Error
During a diskette read operation. the CRC word derived from the data field read
did not match the data field CRC word preViously written If thiS error occurs, the
data read from the sector should be conSidered invalid
Drive Not Ready
The drive addressed was not ready. ThiS ondlcatoon IS caused by any of the
following conditions:
1. Drove not powered up
2, Diskette not loaded
3, No'n-exlstent drove addressed
4 Drive went not ready dUring an operation
Note that this completion code is cleared only through an FOC read drive
status' command.
Write Prote"t
A diskette write operation was specified on a write protected diskette The
intenoed ",;rote operatlbn IS prevented and no data IS written on the diskette.
Track 00 Not Found
DUring a seek to track 00 operation. the drive failed to provide a track 00
indication after beong stepped 255 times.
Write Fault
ThiS error IS dependent on the drive supported and indicates that the fault input to
the FOC has been activated by the drove
Sector Not Found
Either the sect~r addressed could not be found Within one complete revolution of
, the diskette (two index marks encountered) or the track address specified did not
match the track address contained in the 10 field Note that when the track
address spaclfled and the track address read do not match, the FOCautomaticaliy
increments its track address register (steppong the drive to the next track) and
again compares the track addresses. If thO! track addresses stili do not match, the
track address register is incremented a second time and another comparison Is
made before the sector ~ot found completion ,code Is set.
6-537
inter
827118271-8
,INFrIALiZATION
Loed Bad Tl'lcka
, "1
R.~t Command
Ai
'Ao
::':1 : ,.:"
o~"
0
Ds
,
0
I I
0
0
j-
0
I
0
,
:.J
0
CMD :
I
PAR :
PAR :
Functlor,:. the ~eset comman~" em.ulates the action' of
tl.1e r,ese. pin.)t is issued by 9utputtlng a one follqwed
by a zero to the Reset register.
1. The drive control signals are forced low.
2. An in-progress command is aborted
3 .. The FOC s.tatus register flags are cleared.
4. The FPC enter.s an idle state until the next command
issued.
Reset must be active for 10 or more clock cycles. ,
PAR
PAR
i~
First Parameter
Specify Type
.Initialization
Load bad Tracks Surface '0'
Load bae;! Tracks Surface '1'
The' Specify, commlind is usep prior to performing any
diskette operation (including formatting of a diskette) to
define the drive's inherent operating characteristics and
also is used following a formatting operation or
Installation of another diskette to define the locations of
bad tracks. Since the Specify command only loads
internal registers within the 8271 and does not involve an
actual diskette'operation, command processing is limited
to only Command' Phase. Note .that once the operating
characteristics and bad tracks have been s'pecified for
a given drive and diskette, redefining these values need
pnly be done if a diskette with 'unique bad tracks is to be
used or if the system is powered down,
Initialization:
PAR :
. PAR
, PAR :
0
1
0
0
0
o
o
1o 11 11 1
1o 1010 1
1
STEP RATE"
1
HEAD SET'TLING TIME"
1
INDEX CNT BEFORE
HEAD UNtOAO·
01 oJ 1 L '1 0'1 1 1 o 1 1
,0 1 o 1 o 1 ;1 '10 1 0' 1 o 1 0
1
BAD TRACK,NO 1
,1
.B~·TRACK NO 2
1,
CURR ENT TRACK
It Is recommended to program both bad tracks and current track to FFIi during Initialization.
OOH
10H
.18H
0
0
1
Parameter 1: '
Bad track address number 1 (Physical Address).
Many of the Interface characteristics of the FOC are
specified by the systems software. Prior to Initiating any
drive operation command, the software must execute
the three specify commands. There are two types of
specify commands selectable by the first param~ter
issued.
.
PAR
0
Parameter 0: 1OH = Load Surface zero bad tracks
18H"= Load Surface ,one bad track
SPECIFY COMMAND
.. CMD
0
0
0
0
0
o
I
1
1
1
1
1
1o 11
1o 11
HEAD LOAD TIME"
SEEK COMMAND
The seek command moves the head to the specified trac)<
wit~out load!,n~ the head or verifying the track.
The seelt operation uses the specified bad tracks to
compute the phySical track address. lhis feature insures
that the seek operation positions the head over the correct
track:
.
, When a suk to track zero is specified, the FOC steps
the head until the track 00 signal Is detected.
"
'
'"I
I'
If the track·oo sign'al is not detected within (FF)H steps, a
track 0 not found error status is returned. "
A seek to track zero is used to position the read/write head,
when the current head position is unknown (such as after'
a power up).
Seek, operations are not verified. A subsequ~lnt read or
write operation must be performed to determine if the
correct track is located .
READ DRIVE STATUS COMMAND
This command is 'used to interrogate the drive status.'
Upon completion the result register will ~old the final
.drl~~ statu~.
.
·Note: Mini-floppy .parameters .are .doubled, ,
I
parameter 0 - OOH = Select Specify Initialization.
Parameter 1 - 07-00 = Step Rate (0-255ms in 1ms steps)'
Parameter 2 - 07-00 = Head Settling Time (0-255ms in 1
ms steps). {O- 510ms in 2ms steps}.O= standard,
{}= mini
Parameter 3 - 07-04 = Index Count - Specifies the
number of Revolutions (0-14) which are to occur before
the FOC automatically unloadS the R/W·head. If 15 is
' ' '
'specified, the head remains loaded.
b3-Do = Head 'Load Time (o-'60ms in, steps of 4';'s):
{0-120ms In 8ms steps} () = standard, {}= mini
A1'
CMD
Au
07
06
05
Dot
03
02
0,
Do
lot 0 IS~L I S~L I r ~ I ,1, 10 10 I
1
"Note the two ready bits are zero latching. Therefore, to clear the drive
not ready condition, asSumlng·the d~lve IIr,ready, and todeteet It via soft·
ware, one must Issue this command twice.
6-r538
inter
8271/8271-8
!-"
liP TO
T......
ON DIUYIt
Figure 18. Initialization 01 the 8271 by the U.er
Mode Regl.ler Write 'aram"'r Format
RHcllWrlie Special Regl.te,. .
This command Is used to access special registers within
the 8271.
D
CMD:
PAR:
.0
0, D. Os D. D, D, D, D.
'111 1010 1010 I ~
.
D
COMMAND OPCODE
~~~------------------~
Command code:
3DH Read Special Register
3AH Write Special Register
Table 4. Special Regl"'r.
.
R..I....._
InH..
Scan
Sactor Number
,
'/'
SCln MSB 01 Count
Scan LSB 01 Count
Surface 0 Current Track
06
14
13
12
1 Current Track
lA
Surface
~ode
Register -
17
Drive Control Output Port
23
Drive Control Input Port
22
Surface 0 Bad Track 1
10
11
18,
19
.Surface 0 !lad Track 2
SI/rfac'! 1 Bad Track.l
Sul'fac!, 1 Bad Track 2
Bit. 8.7
Must be one.
Blta 5·2
For boih commands. the first parameter is the register
addreSs; for Write commands a second 'parameter
specifies data to be written. Only tlie Read Special
Registilr command supplies a result. .
D_rl~
... 0 DMA MODE. '" , NON OMA
• Ii DOUBLE. =1 SINGLE ACTUATOR
,...
Commlnt
.See Se!,n !Iescrlption
See Scan Descrol1!19n
See Scan Description
,
See Mode Regisier
Description·
See Drive Output
POl'\, Description
Sae Drive Input
Port Description
(Not used), Must be set to zero.
-Bit 1
Double/Single Actuator: Selects single or double actullt~r
mode. If the single 'actuator mode is selected. the FDC
assumes that the physical track location of both disks is
always the same. This mode facilitates control of a drive
which has' a single actuator mechanism to move two
hes_'
.
-BIIO
Data Transfer Mode. This bit selects the data transfer
mode. If this bit Is a zero. the FDC operates In the DMA
mode (DMA RequestlACK). If this bit is a one. the FCC
operates in non-DMA mode. When the FDC is operating in
DMA mode, 'interrupts are generated at the completion of
commands. If the non~DMA mode is selected. the FDC
generates an inter~upt for every data bYte transferred.
"B1I80 and 1 are Inillalized to zero.
6-539
inter
827118271-6
Non-DMA Transfers In DMA Mode
Track Format
If the user desires, he may retain the use of interrupts
generated upon command completions_ This mode Is
accomplished by selecting the DMA capability, but
using the DMA REQ/ACK pins as effective INT aOO CS
Signals, respectively.
Each Diskette Surface is divided into 77 tracks with each
track divided into fixed length sectors. A sector can hold Ii
whole record or a part of a record. If the record is shortlN'
than the sector length, the unused bytes are filled with
binary zeros. If a record is longer than the sector length,
the' record is written over as many sectors as its length
requires. The sector size that provides tite most efficient
use of diskette space can be chos~m depending upon the
record length.required.
Tracks are numbered from 00 (outer-most) to 76 (innermost> and are used as follows:
TRACK 00 reserved as System Label Track
TRACKS 01 through 74 used for data
TRACKS 75 and 76 used as alternates.
,Drive Control Input Port
Reading this port will glv~ the CPU exactly the data that
the FDC sees at the corresponding pins. Reading this
port will update the drive not ready status, but will not
clear the status. (See Read Drive Status Command for
Bit locations.)
Each sector consists of an 10 field (which holds a unique
address for the sector) and a data field.
Drive Control Output Port Format
I
I I I I I I L I
L=
WRITE ENABLE
SEEK/STEP
DIRECTION
LOAD HEAD
lOW HEAD CURRENT
WAITE FAULT RESET j
OPTIONAL OUTPUT
SELECT 0
SELECT 1
Each of these signals correspond to the chip pin of the
same name. On standard-sized drives with write fault
detection logic, bit 5 is set to generate the write fault
reset signal. This signal Is used to clear a write fault
indication within the drive. On mini-sized drives,Jhis bit
can be used to turn on or off the drive motor prior to initiating a drive operation. A time delay after turn on may be
necessary for the drive to come up to speed. The register must be read prior to writing the register in order to
save the states of the remaining bits. When the register
is subsequently written to modify bit 5,the remaining
bits must be restored to their previous states.
IBM DISKETTE GENERAL FORMAT
INFORMATION
'
The IBM Flexible Diskette used for data storage ,and
retrieval is organized into concentric circular path!l,or
TRACKS. There are 77 tracks on either one or both sides
(surfaces~ of the diskette. On double-sided diskettes, the
corresponding top and bottom tracks are referred to as a
CYLINDER. Each track is further divided into fixed length
sections or SECTORS. The number of sectors petttack ~
26, 15 or 8 - is delermined when a track is form'atted and is
dependent on the sector length -128, '256 or:512 bytes
•
respectively - specified.
All tracks on thedislsette are referenced to a physical
index mark (a small hole in the diskette). Each time the
hole passes a photodetector cell ione revolution of the
diskette), an Index pulse is generated to indicate the
logical beginning of a track. This index pulse is used to
initiate a track formatting operation.
The 10 field is seven bytes long and is writfen for each
sector when the track is formatted. Each 10 field consists
of an ID'field Address Mark, a Cylinder Number byte which
identifies the track number, a Head Number byte which
specifies the head used (top or bottom) to access the
sector, a Record Number byte identifying the sector
number (1 through 26 for 128 byte sectors), an N-byte
specifying the byte length of the sector and two CRC
(Cyclic RedundancyGheck) bytes.
The Gaps separating the index mark'and the 10 and data
fields are written on a track whenjt is formatted. These
gaps provide both an interval for switching the drive electronics frolTlreading or writing and compensation for rotational speed and other diskette-to-diskette and drive-todrive manufacturing tolerances to ensure that data written
on a diskette by one system can be read by another
(diskette'interchangeability).
IBM Format Implementation Summary
Track Format
The disk has 77 tracks, numbered physically from 00 to 76,
with track 00 being the outermost track. There are
logically 75 data tracks and two alternate tracks. Any two
tracks may be initialized as bad tracks. The data tracks are
numbered logically in sequence from 00 to 74, skipping
over bad tracks (alternate tracks replace bad tracks).
Note: In IBM format track 00 cannot be a bad track.
Sector Format
Each track is divided into 26,15, or 8 sectors of 128,256,
or 512 bytes length respectively. The first sector is
numbered 01, and, is physically the firstsectot after the
physical index mark. The logical sequence 'of the
remaining sectors may be nonsequential physically. The
location of these is determined at initialization by CPU
software.
" ,
Each sector consists of an 10 field and a data field. Ail
fields are separated by gaps. The beginning of each field
is indicated by 6 bytes of (OOlH followed by a one byte
address mark.
Address Marks
Address Marks are unique bit patterns one byte in length
which are used to identify the beginning of 10 and Data
other dilfa
fields. Address Mark bytes are unique from
all
6-540
AFN-00223B
inter
8271/8271·6
I
-~-
~-~
L8st Sector
(
II
Go.
Sector 02 :.
I
-Seator 03
Dete F,eld
IDFleId
A
A
128. 258, or 512 Bytes
AM2' Data. hex FB or F.
Fa -dati field
F8 - control field
IThe controlf.1d
.n
beginwlthaOorlnF.
of the Format command specify
record length, the bits are coded the same way as in the
Read Data commands.
2·. The programmable gap sizes (gap 3, gap 5, and gap 1) must
be programmed such that the 6 bytes of zero (sync) are subtracted from the intended gap size i.e., 11 gap 1 Is intended
to be 16 bytes long, programmed length must be 16 - 6 = 10
bytes (of FFH'S),
Data Format
Data Is written (general case) in the following manner:
CLOCK
CLOCK
DATA "0"
MISSING
CLOCK
CLOCK
DATA "1"
DATA "1"
DATA "1"
Mini-Floppy Disk Format
TF == FULL 81T TIME == NOMINALLY 4,1jS*
TH == HALF 81T nME NOMINALLY ~ ..
=
The mini-floppy disk format differs from the standard
disk format in the following ways:
1. Gap 5 and the Index Address mark have been eliminated.
2. There are fewer sectors/tracks.
References
"The IBM Diskette for Standard Data Interchange," IBM
Document GA21-9182-0. "System 32," Chapter 8, IBM
Document GA21-9176-0.
GAPS
The fOllowing is the gap size and description summary:
Bad Track Format
The Bad Track Format is the same as the good track
format except that the bad track 10 field is initialized as
follows:
Gap
Gap
Gap
Gap
Gap
C = H = A ;" N = (FF)H
When formatting, bad track registers should be set to
FFH for the drive during the formatting, thus specifying
no bad tracks. Thus, all tracks are left available for formatting.
Upon completion of the format the bad tracks should be
set up using the write special register command. The
8271 will then generate an extra step pulse to cross the
bad track, locating a new track that now happens to be
an extra track out.
Gap 1:
This gap separates the index adNbytes FF's
dress mark of the index pulse from
6 bytes O's for sync the first 10 mark. It is used to protect the first 10 field from a write on
the last physical sector of the current track.
Format Track
Format Command
0
0
PAR
0
1
PAR
0
PAR
0
PAR.
0
PAR
0
1
,
,
,
S~L
I S~L I ' I
TRACK ADDRESS
o
I
0
I
o
I
Gap 2:
This gap separates the 10 field from
11 bytes FF's
the data mark and field such that
6 bytes O's fOr sync during a write only the data field
will be changed even if the write
gate turns on early, due to drive
speed changes.
'I '
GAP 3 SIZE MINUS 6
RECORD LENGTH
I
Programmable
17 Bytes
Programmable
Variable
Programmable
The last six bytes of gaps 1.2,3,and 5 are (OO)H. all other
bytes in the gaps are (FF)H. The Gap 1,3 and 5 count
specified by the user are the numberof bytes of (FF)H. Gap
4 is written until the leading edge of the index pul"e. If a
Gap 5 size ·of zero is specified, the Index Mark is not
written.
The track following the bad track(s) should be one
higher in number tha,:! track before the bad track(s).
CMO.
1
2
3
4
5
NO-OF SECTORS/TRACK
GAP 5 SIZE MINUS 6
Gap 3:
This gap separates a data area from
N bytes FF's
the next 10 field. It is used so that
6 bytes O's for sync during drive speed changes the
next 10 mark will not be overwritten,
thus causing loss of data..
GAP 1 SIZE MINUS 6
The format command can be used to initialize a disk track
compatible with the IBM 3740 format. A Shugart "IBM
Type" mini-floppy format may also be generated.
The Format command can be used. to initiaUze a diskette, one track at a time. When format command is used,
the program must supply 10 fields for each sector on the
track. During command execution, the supplied 10 fields
(track head sector addresses and the sector length) are
written sequentially on the diskette. The 10 address
marks originate from the 8271 and are written automatically as the first byte of each 10 field. TheCAC character Is· written in the last two bytes of the 10 field and is
derived from the data written in the first five bytes. OurIrig the formatting operation, the data field of each sector Is filled with data pattern (E5)H' The CAC, derived
from the data pattern is also appended to .the last byte.
6-542
Gap 4:
FF's only
This gap fills out the rest of the disk
and is used for slack during formatting. During drive speed variations
this gap will shrink or grow if the
disk is re-formatted.
Gap 5:
This gap separates the last sector
N bytes FF's
from the Index Address mark and
6 bytes O's for sync is used to assure that the index address mark is not destroyed by
writing on the last physical data
sector on the track.
The number of FF bytes is programmable for gaps 1, 3
.
and 5.
AFN.00223B
inter
8271/8271·6
L
INDEX
~ INDEX ADDRESS MARK
GAPS
GAP 1:
POST INDEX GAP
I'
"I
,I
SYNC
GAP 2:
POST 10 FIELD GAP
I'
"I
I
SYNC
L.
WRITE GATE TURN.()N FOR UPDATE OF NEXT
DATA FIELD.
NOTE
THE WRITE GAte TURN·ON SHOULD BE TIMED
TO WITHIN ± "" 1 BIT BV COUNTING THE BYTES
IN THE GAP UNTIL 1 BYTE BEFORE THE
TURN..QN
GAP 3:
POST DATA FIELD GAP
,·1
·1'
I
I
L
WRITE GATE rURN-OfF fROM UPDATE OF PREVIOUS: DATA FIELD
NOTE
GAP 4:
IBM FORMAT REOUIRES AT LEAST 281NARV "1" BiTS AS A DATA FIELD POSTAMBLE.
FINAL GAP
I'
GAP 5:
I
SYNC
"I
INITIAL GAP
I'
I
"I
SYNC
I
Figure 21. Track Format
6-543
AfN-002238
intJ
8271/8271·6
n
PHYSICAL
INDEX
_ _ _ _-'
MAR'
'1'~"I~~~L .:::X
DATA
Fl.LD
(GAP 4)
GAP
CoAl' 5)
I I,:
INDEX ,
ADOliesa
MARk
GAP
(GAP 1)
I
f
HEXF"
ISECTO:I
P:eJ.~D'
I
"
' GAP
SECTOR
~
DATA FIELD
(GA, 2)
10 FIELD,
.~
I(::~ I I
40 IYTES
HEX FF
& BYTES
2e BYTES
(TYPICA~
(TYPICAL)
IA!~tsl
I
IH:;:)
,
~
_ _ _- - '
128" 2" US£FI OTA BYTES
~,,:::~,
I
I
8 BYTES
I B~,1 B~~2
,
'BYTES
IAf.'i~~S81 A~:i~ IA::::OJAs:g:~~L ~:~~=
)
BYTE 1
BYTE 2
BYTE'
BYTE
I, ,:::~ ,
HEX"
l1BYT)5S
BYTE'
B$.r~,
BYTEe
.BYTES
LB~~2 J
BYTE7
NUMBER OF BYTES
GAP 1
NUMBER
OF SECTORS
GAP 2
GAP 3
ID FIELD
'ONES
SYNC
26
26
26
26
26
26
6
6
6
6
6
6
26
15
8
4
2
1
GAP 5
DATA FIELD
ONES
SYNC
11
11
11
11
11
11
6
6
6
6
6
6
7
7
7
7
7
7
GAP 4
131
259
515
1027
2051
4099
,
'ONES
SYNC
27
48
90
224
255
0
6
6
6
6
6
0
275
129
148
236
719
1007
40
40
40
40
40
40
,
'Program Specified
SYNC
'ONES
6
6'
6
6
6
6
5206 Bytes Per Track
Figure 22. Standard Diskette Track Format
~PHYSICAL
INDEX
MARK
DATA
POS'
FIELD
I (Q~r3)
FIELD
I SECTOR
: I POST
2
GAP"1
10 FIELD
(OAP 2)
poe,
1SECTOR
3
GAP
10 FIELD
DATA
FIELD
......
SECTOR 2
OATA FIELD
, BYTES
BYTE 1
IYTI 2
BYTE 3
BYTE 4
BYTE IS
BYTE II
I"ff I
121lC2'!U8ERDATAIYTES
111'' ' :"1
FIELD
GAP
POST'"
SECTOR
DATA
FIELD
(GAP 2)
J
• BYTES
I B~' I 8~~2 I
BYrE7
NUMBER OF BYTES
NUMBER
OF SECTORS
18
10
5
2
1
GAP 1
GAP 2
GAP 3
SYNC
16
16
16
16
16
6
6
6
6
6
7
7
7
7
7
GAP 4
DATA FIELD
ID FIELD
'ONES
ONES
SYNC
11
11
11
11
11
6
6
6
6
6
131
259
515
1027
2051
'ONES
SYNC
11
21
74
255
6
6
6
6
0
q
24
30
86
740
1028
3125 Bytes Per Tra~k
'Program Specified
Figure 23. Mini-Diskette Track Format
6-544
AFN-002238
inter
8271/8271·8
TCSTOP::';{
DMA ENABLE BITS '--_ _...,._ _ _....
'--_ _--,._ _ _- '
}
:~O
LOAD AND
.
DMA ENABLE BITS
Figure 24. U••r DMA Channel Initialization Flowchart
R.ad ID Command
A1
CMD:
PAR:
PAR:
PAR:
°
°
°
°
o
o4
•
•
°
~l
1
TRACK ADDRESS
A
1
1
I S~L I I I
0
1
o1
1
I°I
1
I
1
°1°1°1°1°1°1°10
NUMBER OF 10 FIELOS
The Read 10 command transfers the specified number of
10 fields into memory (beginning with the first 10 field after
Index). The CRC character is checked but not transferred.
These fields are entered into memory In the order In
which they are physically located on the disk, with the
first field being the one starting at the Index pulse.
Full power of the multisector read/write commands can be
realized by doing OMA transfer .using Intel@ 8257 DMA
Controller. For example. in a 128 byte per sector
multisector write command. the .entire data block
(containing 128 bytes times the number of sectors) can be
located in a disk memory buffer. Upon completion of the
command phase. the 8271 begins execution by accessing
the desired track. verifying the 10 field. and locating the
data field of the first record to be written. The 8271 then
OM A-accesses the first sector and starts counting and
writing one byte at a time until all 128 bytes are Written. It
then locates the data field of the next sector and repeats
the procedure until all the specified sectors have beE!n
written. Upon completion of the execution phase the 8271
enters into the result phase and interrupts the CPU for
availability of status and completion results. Note that all
read/write commands. single or multisector are executed
without CPU intervention.
Data Processing Cqmmands
All the routine ReadlWrlte commands examine specific
drive status lines before beginning execution, perform
an implicit seek to the track address anClload the drive's
read/write head. Regardless of the type of command
(I.e., read, write or verify), the 8271 first reads the 10
fleld(s) to verify that the correct track has been located
(see sector not found completion code) and also to
locate the addressed sector. When a trarisfer Is com·
plete (or cannot be completed), the 8271 sets the Inter·
rupt request bit in the status register and provides an In·
dication of the outcome of the operation In the result
register.
Note, execution of multi·sector operations are faster if
the sectors are not interleave&
128 Byte Single Record Format
PAR:
PAR:
0
0
0
j
I
0
S~l
1
TRACK ADDR
1
SECTOR
S~l
COMMAND OPCODE
0·255
0-255
Commands
If a CRC error is detected during a multisector transfer, processing is terminated with the sector in error. The
address of the failing sector number can be determined by
examining the Scan Sector Number register using the
. Read Special Register command.
6-545
READ DATA
READ DATA AND DELETED DATA
WRITE DATA
WRITE DELETED DATA
VERIFY DATA AND DELETED DATA
-
Opcode
12
16
OA
OE
1E
AFN-002238
inter
827t/82,71-8
Scan Commands
Variable length/Multi-Record Format
CMO:
0
0
si I S~L I
PAR-
0
1
TRACK ADOR 0·255
PAR
0
1
SECTOR 0·255
PAR.
0
1
LENGTH
L
COMMAND OPCODE
I
CMD
0
0
S~l
PAR.
0
1
TRACK ADDR 0 255
PAR
0
1
SECTOR 0255
PAR.
0
1
LENGTH,
PAR
0
1
'SC'AN TYPE
0
'I
NO. OF SEFTORS
07-05 of Parameter 2 determine the length of the disk
record.
"
128 Bytes
256 Bytes
512 Bytes
1024 Bytes
2048 Bytes
4096 Bytes
8192 Bytes
16,384 Bytes
000
00 1
010
o1
1
100
10 1
1 1 0
1 1 1
Commands
READ DATA
READ DATA AND DELETED DATA
WRITE DATA
WRITE DELETED DATA
VERiFY DATA AND DELEl'ED DATA
SCAN DATA
SCAN DATA AND DELETED DATA
PAR:
Command
S~ll
I
0.1
o
I
J
0
I~DAT~I
SDELD
0
I
0
NO OF SECTORS
STEP SIZE
FIELD lE.NOiTH (KEY)
O2 = 0
O2 = 1
Scan Data
Scan Data and Deleted Data
Scan Commands, Scan Data and Scan Data and Deleted
Data, are used to search a specific data pattern or "key"
from memory. The 8271 FDC operation during a scan is
unique in that data is read from memory and from the
diskette simultaneously,
Opcode
13
17
OB
OF
1F
00
04
Read Commands
Read Data, Read Data and Deleted Data.
Function'
'r..he reap command transfers data from a specified diSK
record
grou'p 'Of 'records to memory. The operation of
this command is outlined in execution phase table.
or
,
f
During tnescanope,ration, the key is compared
repetitively (using the 8257 DMA Controller in auto load
mode) with the data read from the diskette (e.g., an eight
byte key would be compared with the fi~stl!illht.bytlls(1-8)
read from the diskette, the second eight bytes (9-16): the
third eigh~ bytes, (17-24), etc.>. The scan operation is
concluded when the key is located or when the specified
number of sectors have been searched ~ithout locating
the key. When concluded, the 8271FDC requests an
interrupt. The Program must then read the re$ult register
to determine if the scan was successful (if the key was
locatedl. If successful, several of the FDC's special
r;egisters can be examined (read special registers
comniand) to determine more specific information
relating to the scan (i.e., the sector hUmber il'l which the
key was'located, ,and the nlimber of bytes within the sector
that were not compared when the key was located).
'
Write Commands
'Write Data, Write Deleted Data.
Function
The write command: transfers data from memory to a
specified disk record or group of. records.
The 8271 does not do a sliding scan. ,it does a fixj;ld
block Iinearsearch.'TI1is means the key in memory is
compared to an equal length block in a sector; when
these blocks meet the scan condilio(ls the scan will
stop. Otherwise. the scan continues, until ail the sectors
specified have been searched.
The fOllowing' factots' regarding key: ierygth must be
consider",d when establishing'a key in memory.
Verify Command
Verify Data and Deleted Data.
Function
The verify command is identical to the read data and
deleted data command except that the data is, not
transferred to memory. This command is used to check
that a record or a group of records has been written
correctly by verifying the CRC character.
'6-546
1. When searching m·ul.tiple sectors, the limgth of the key
must be evenly divisible .into tl'iesector length to
prevent the key from be'ingsplit at subsequent sector
boundaries. Since the character FFH is not compared,
the key in memory c~n be paddedto the re,qui'red length
u~ing thischaracte( For example, if the actual' pattern
compared
lhe'dis'ketle is twelve characters in length,
the field ,'ength should be sixteen and four bytes ofFFH
on
AFN-002238
inter
827118271·8
would be appended to the key. Consequently, the last
block of sixteen bytes compared within the first sec·
tor would end at the sector boundary and the first
byte of the next sector would be compared with the
first byte of the key. Splitting data over sector boundarys will not work properly since the FOC expects the
start of key at each sector bounda,ry.
10-LEQ
2. Since the first byte of the key is compared with the first
byte of the sector, w.hen the pattern does not begin with
the first byte of the sector, the key must be offset using
the character FF16. For example, if the first byte of a
nine byte pattern begins on the fifth byte of the sector,
four bytes of FF16 are prefixed to the key (and three
bytes of FF16 are appended to the key to meet the
length requirement) so that the first actual comparison
b!"gins on the fifth byte.
The Scan Commands require five parameters:
Parameter 0, Track
Scan for each character within the disk sector less than or equal to the corresponding
character within the field length (key). The
scan stops after the first less than or equal
condition is met.
Step Size: The Step Size field specifies the
offeet to the next sector in, a multisector
scan. In this case, the next sector address is
generated by adding the Step Size to the
current sector address.
Parameter 4, Field Length
Specifies the number of bytes to be compared (length of
key), While the range of legal values is from 1 to 255, the
field length specified should I:)e evenly divisible into the
s,ector length to prevent the key from being split at sector
boundaries, if the multisector scan commands are used.
Addrel~
specifl~s the tra.ck number containing the sectors to be
scanned. Legal values range from OOH to 4CH (0 to 76) for
a standard diskette and from OOH to 22H (0 to 34) for a
mini-sized diskette.
Scan Command Relults
More detailed information about the completion of Scan
Commands may be obtained by executing Read Special
Register commands,
Parameter 1, Sector Addre.s
Specifies the first' sector' to be scanned. The number of
sectors scanned is specified in parameter 2, and the order
in which sectors are scanned is specified in parameter 3,
Read Special Register
Parameter
The sector length field (bits 7-5) specifies the number of
data bytes allocated to each sector (see parameter 2,
routine read and write commands for field interpretation!.
The number of sectors field (bits 4-0) specifies the number
of sectors to be scanned. The number specified ranges
from one sector to the physical number of sectors on the
track.
Parameter 3
Indicate scan type
Scan for each character within the field
length (key) equal to the corresponding character within the disk sector. The scan stops
after the first equal condition Is met.
01-GEQ
Scan for each character within the disk sector greater than or equal to the c
TEST POINTS
08
045
"x=
<
.'
DEVICE
UNDER
TEST
'1
c,
0.8
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOA A LOGIC 1 AND 0 45V FOR
A LOGIC 0 TIMING MEASUREMENTS ARE MADE AT 2 OV FDA A LOGIC 1
AND 0 8V FDA A lOGIC 0
C, INCLUDES JIG CAPACITANCE
!
6-550
. AFN-00223B
intJ
8271/8271·8 .
WAVEFORMS
READ
DACK
-}
I---ICD-I
X
}
• f"-tcA-1
IRR
1
~
116
DATA.US
---
--
]{
-IDC-
~
IRD
-IAC-
-----------lAD
IKD
I--IDF-}- _ _ _ _ ..:. _ _
WRITE
DACK
~
-
IDC-
I----tcD
J(
tww
I---IAC-,
f"-ICA-l
~
](
)(
DATA BUS
IDW
IWD----=---..J
DMA
DRQ
_~I
=4
r
\~----+-----------------------------tcc
~OR~ ----------------~~L_____________________________________
CHIP CLOCK
AFN.()()223B
inter
, ""
t:: ,
"
''',
8271/8271-6
WAVEFORMS (Continued)
<
READ DATA
WRITE DATA
·tCY -= 250 n8
F
s
H =
• "'tCY
1m
500 n8
PULSE WIDTH PW = ICY'" 30
H (HALF BIT CELL) = S ICY
F (FULL BIT CELL) • IS ICY
IS ICY ",SICY
BICy",4tcy
n.
-tCY =- 250 ns :t:O.4%· .. tey = 500 na ::to.4%
250 ns :t 30 ns
500"1 :t: 30 ns
'STANDARD FLEXIBLE DISK DRIVE TIMING
"MINI·FLOPPY TIMING
2.0JolI:t: 8ns
4.o,,1::I:18nl
4.0". :t: 16 ftl
8.0". :t 32 na
I
SINGLE-SHOT DATA SI;PARATOR
PLO DATA SEPARATOR
UNSEPARATED
IilTA
·DATA WINDOW MAY BE 180- OUT
IN PLO DATA SEPARATION MODE.
6-552
o~
PHASE
inter
8272A
SINGLE/DOUBLE DENSITY
FLOPPY DISK CONTROLLER
Compatible In Both Single and
• IBM,
Double Density Recording Formats
Programmable Data Record Lengths:
• 128,256,512,
or 1024 Bytes/Sector
Multl·Sector and Multi·Track Transfer
• Capability
Up to 4 Floppy or Mlnl·Floppy
• Drives
Disks
Data Transfers In DMA or Non·DMA
• Mode
Parallel Seek Operations on Up to
• Four
Drives
•
Compatible with all Intel and Most
• Other
Mlcrop~essors
Single·
Phase 8 MHz Clock
•
• Single + 5 Volt Power Supply (± 10%)
The 8272A'is an LSI Floppy Olsk Controller (FDC) Chip, which contains the circiJitry and control functions for interfacing a processor to 4 Floppy Disk Drives. It is capable of supporting either IBM 3740 single density format (FM), or
IBM System 34 Double Density format (MFM) including double sided recording. The 8272A provides control signals
which simplify the deSign of an external phase locked loop and write precompensation circuitry. The FDC simplifies
and handles most of the burdens associated with implementing a Floppy Disk Drive Interface. The 8272A is a pincompatible upgrade to the 8272.
DBo.r
FLT/TRKO
!'So
TERMINAL
PS,
COUNT
WR DATA
R~DY
WRITE PROTECTITWO SIDE
INDEX
DSo
DS,
FAULTITRACK 0
DRIVE SELECT 0
DRIVE SELECT 1
MFM MODE
RD DATA
IIWfSEEK
HEAD LOAD
elK - . . .
Vee - . . .
GND - .
HEAD SELECT
LOW CURRENT/OrRECTfON
FAUl-T RESETISTEP
Figure 1. 8272A Internal Block Diagram
Figure 2. Pin Configuration
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodted in an Intel product. No other circuit patent licenses are Implied.
© Intel Corporation, 1982
ORDER NUMBER210606-001
6-553
inter
8272A
Table 1. Pin Description
Symbol
RESET
Pin
No.
Connec~
Type
1
I
lion To
'. "e..I:, Places FDC in
p,P'
'Idle state. Resets' oul·
put lines to FDD to ;'0"
(lOW). Does not clear the
"last specify command.
RD
2
I['J
p,P
Read: Control signal
for transfer of data from
, FDC to Data Bus, when
"Oi, (low).
' ,
WR
3
1[1]
p,P
Wrlle;, Control, signal
for transfer of data to
• FD,C via Data Bus,when
"0" (low), .
CS
4
I
p,P
Chip Selecl: IC selected
(lo!1,allow109 RD and WR to be
enabled,
.'
Ao
DBo-DB7
5
6-13
,111[
110[1]
"p
p,P
RW/SEEK
39
0
lCT/QIR
38
o
FR/STP
37
o
FDD
Fault Reaet/Step: Resets fault FF in FDD in
Read/Write mode, provides step pulses to
move head to another
cyliride'r, it:> Seek mode.
HDl
36
o
,FDD '.
Head Load: Command
which causes read/write
head in FDD
contact
diskette,
FDD
Read Write / SEEK:
When "1" (high) Seek
mode selected' and
when" "0" (low) Read/
Write mode selected.
FDDLow~urre"t/DjI'l!C\llon:
lowers Write current
..
on inner" tracks In
Read/Write mode, determinesdirection head
will step ,in Seek ~ode.
Data DMA Requeat:
DMA Request is being
made by FDC when
ORO "1,"13J
DACK
15
I
DMA
DMA Acknowledge:
DMA cycle is active
when "0" (low) and
Controller is performing DMA transfer.
TC
16
I
DMA
Terminal Counl: Indicates the termination of
a DMA transfer when
"1" (high)[2J.
17
I
INT
18
0
ClK
19
I
20
to
Data Bus: Bidirectional
8-Bit Data Bus.
DMA
FDD
p,P
Index: Indicates the
beginning of a disk
track,
Re..
Interrupt: Interrupt
quest Generated by
FDC.
Name and Function
D.C. Power: +5V
,
0
Note 1. Disabled when
Connec-
'Typ~ tlon To
40
, 0,181 Statlls Reglsler
$eJecl: Selects Data
Reg (Ao = 1) or Status
Reg (Ao = 0) contents
to:be sent to Data Bus.
14
GND
Pin
No.
whe~O"
ORO
lOX
iiSym~ol
Heme and FlinCllon
35
I
FDD
WPiTS
34. I
FDD
Write. Prolect / TwoSide: Senses Write Protect status in Read/
Write mode, and'Two
Side Media in Seek
mode,
FlTiTRKO
33
I
FDD
FaultiTrack 0: Senses
FDD fault condition in
Read/Write mode and
Track 0 condition in
Seek mode.
31,32
'0
FDD
PrecompanBatlon (preahltt): Write precompensation stetus during
MFM mlAmod.
-.
A read or wrh. oommond la In
NDM
Th~ FOC 'la' In the non-DMA'
mode. This bit Ie . .t only dur..
log the _ I o n phoN In
non·OMA mode, TranSItion to
"0" ltat. Indicates execution
phIH haa'endad,
,
De
Data InputlOutp'ut
IndlC81.. direction of d.t~ ~
'010
::~':r,"Ii~~~~t:=
,
..
:
Dr
Request for Master
ROM
;,,'
"
.
"
'
tranlter I. from O.ta Regllter
to the Procaaaor. If 010 ''0'',
~h.n tran.fer 18 from the Proc>
. ~~rt~ Data Reg_,
=
indlcat•• Data ReOlster la
noody to HOd or 1808,," data
to or from the ~lOr. ~Oti
bits 010 and RQM should ,be
uHd to petIonm the hana.
, 'aheklng 'funoflona Of ':Mdy"
and!'dlrectlOn:' to the proe>
0I80f,
"
;:
The 010 and ROM bits in the Status Register Indicate
when Data. il ready and in which direction data will be
:transferred on the Data Elu••
Note: Therela a 1a,.8 or 24,A8 ROM flag delay when
using an 8 or 4, MHt clock respectively,
\ "T.
-=
OUt Of 'DC 'AND INTO PIIIOCaIOIt
OUT OF IIROCI8IOII AND INTO PDC
-
L
I
I
FfHfl
I
.~~ I
•
I
N01'II:
.1.1 1.1.I.ttTIL
iii -DAT• ....,...MADYTOUWIUYTDIINTOM'PIIOCDIOIl
IJ ..: MfA ....... NOT IllUDY '1'0 II 'MInIM lITO IV PRacIDOIl
II III -
--.
OAtA UflIIfIII NADY FOR...-r DATA IY1I TO II .... " ...
DATA .......... NOT READY PO" NIXf DATA.m TO. READ IY
,
Figure 5. Status Register nmlng
the 8272A
Note: Dellgn m~t guaran~
,II ~ subJected to !Ilegal Inputs.
lIT NUMBER
,
The 8272A is capable of executing 15 different commands. Each command Is' initiated by a multi·byte
transfer from the processor, and the result after execu·
tion of the command may also be a multl-byte:transfer
,back to the processor. Because of this multi·byte Inter··
change of Information betwe~n the 8272A and the processor, it is convenient to consider each command as
consisting of three phases: .
Command Phase: The FDC receives all information
required to perform a particular
ope~tlon from the prOcessor.
'
Execution Phese: The FDC performs the operation it
was Il'!structed to do.
Result Phase:
After completion of the operation~
status and other housekeeping in·
formation are made available to
the pr.opessor.
During Command or Result Pheses the Main Status
Register (described In Table 3) must be read' by th8,prooessor ~fore each byte of information Is written into or
readfrPl)'l the Data.f~egi.ter. 8,lts 06, ~nd Dr';n the~ain
S,tatus Regls,er must, be II'! a Q,andJ state, resp'ectively,
befOle each byte of th~ command word may be ~rltten
into the 8272A. Many of the commands r8qljiremultlple
bYt,s, and as a result the Main Status Reglster,must be
re~ p'~lor to eacl'! l;Iyte:,tra~sfer, tQ tl'!e 8272A. !)n tlK!
,onter hand, dl/rlng the Resl,llt,~p~, OS,aodD7 In the
Main status Register musU>oth. be 1'8 (06 '" ·1 and.
07 =' 1) before reading each 'byte from Jh.e Data
,Reglster.,NS)te, this reading !,f the Main Status Register'
.befor~ each byte ,tra!,sfer fo the 8~72A is ..r~uitedln
only the Command and Result Phases, and NOT during
tile Execution Phase.
",',
, ,
',f'
\,,"
,
, .
~
During the Exacutlon Phase, the Main Status Regillter
need not be reae!. If tbe 8272A is In the non-DMA Mode,
then the receipt of each data byte (if 8272A, Is reading I
data from FDD),lslndicated by an Interrupt signal on pin
18 (INT == 1). The gentpratlon of a Read slgn~I,(R.1?
0)
wll! reset the Interrupl as well as output the Data onto
=
AFN·Ol268C
intJ
8272A
the Data Bus. For example, If the processor cannot
handle Interrupts fast enough (every 13 jlS for MFM
mode) then It may poll the Main Status Register and
then bit \)7 (RaM) functions Just like the Interrupt
signal. If ,a Write Command Is In process, then the WR
signal performs the reset to the Interrupt signal.
It Is Important to note that during the Result Phase all
bytes shown In the Command Table must be read. The
Read Data Command, for example, has seven bytes of
data In the Result Phase. All seven bytes must be read
In order to successfully complete the Read Data Command. The 8272A will not accept a new command until
all seven bytes have been read. Other commands may
require fewer bytes to be read during the Result Phase.
The 8272A always operates In a multi-sector transfer
mode. It continues to transfer data until the TC Input Is
active. In Non-DMA Mode, the system must supply the
TC Input.
The 8272A contains five Status Registers. The Main
Status Register mentioned above may be read by t~e
processor at any time. The other four Status Registers
(STO, ST1, ST2, and ST3) are only available during the"
Result Phase, and may be read only after successfully
completing a command. The particular command which
has been executed determines how many of the Status
Registers will be read.
If the 8272A Is In the DMA Mode, no Interrupts are generated during the Execution Phase. The 8272A generates
DRa's (DMA Requests) when each byte of data Is
available. The DMA Controller responds to this request
with bOth a DACR = 0 (DMA Acknowledge) and a AD = 0
(Rea~A!tData F;ields in each sector, ,the
FDC checks the,CRC'bytes. If a read error,is detected
(Inco~rect CRC in ID field), the FDC sets the DE (Data Error) flag in Status Register 1 to a 1 (high), and if a,CRC error occul'l! in the D~ta Field the F.DC also sets the DO
(pata J:rror ,In Data Field) flag in Status Register 2 to ~ ~
(hl,gh), and terminates the R~d,Data Command. (Sta,tus
Register 0 also has bits 7 and 6 set to O'and 1 respec;:lively.)
If, the FDC reads a Deleted Data. Address Markoff the
diskette, and the SK'bit (bit 05 In the ,first Command
Word) IS not set (SK" 0), then the FDC sets the CM (cron~
trol Mark) flag In Status Register 2 to a 1 (hIgh), and terminates·the Read Data Command, after reading all the
data in the 'Sector. If SK = 1, the FDC skips the, sector
with the Deleted Data Address Mark and .reads the 'next
sector.
l~mD"~
.. 2801S1d. 0
I
EOT
FlnoiSectorT..........d to
p-
IA
OF
DB
Sector I to 14 at Side 0
Sector 1 to 7 at Ski. 0
IA
OF
DB
Sector 26 al Sid. 0
Sector 15 al Sid. 0
Seclor 8 at Side 0
IA
OF
08
Sector 1 to 14 at Side I
Sector I to 7 at Side 1
IA
OF
08
Sectot 8 al Sid. 1
lA
OF
08
Sector 1 to 14 at Side 0
Sector 1 to 7 at Side O'
ID l.tomaU. . at R_lt
P_
C
H
R
N
NC
NC
R+l
NC
C+I
NC
R.01
NC
NC
NC
R+l
NC
C+I
NC
R=OI
NC
NC
NC
R+l
NC
NC
LSB
R-OI
NC
NC
NC
R+l
NC
C+I
LSB
R.Ol
NC'
sector 1 to 25 at Side 0
Bector 1 to 25 at Sld. 1
sector 28 at Side 1
Sector 15 at Side 1
Sector 1 10 25 at Side 0
lA
OF
08
Sector 15 al Side 0
IA
OF
08
sector 1 to 25 at Side 1
sector 1 to 14 at Side 1
Sector 1 to 7 at Side 1
IA
OF
08
Sector 15 al Side' I
Sector 26 at Side 0
S84?tor 8 at Side 0
sector 26 at Side 1
Sector 8
at Side 1
,
Notes: 1 NC (No Change): The same 'value as the one at the beginning of command
execution.
2. LSB (Leaat Significant BII). Thel...t Blgnlflcant bit of H II
complemented
WRITE DATA
A set of nine (9) bytes are required to set the FDC into
the Write Data mode. After the Write Data command has
been issued the FDC loads the head (if It is in the
unloaded state), waits the specified h",ad settling time
(defined in the Specify Command), and begins readlhg
ID:Flelds. When the current sector number ("R"), stored
in the 10 Register (lOR) compares wijh the sector
6-560
AFN·OI258C
inter
8272A
number read off the diskette, then the FDC takes data
from the "processor byte·by·byte via the data bus, and
outputs it to the FDD.
After writing data into the current sector, the Sector
Number stored in "R" is incremented by one, and the
next data field Is written Into. The FDC continues this
"Multi·Sector Write Operation" until the issuance of a
Terminal Count signal. If a Terminal Count signal is sent
to the FOC it continues writing into the current sector to
complete the data field. If the Terminal Count signal is
received while a data field Is being written tlien the reo
mainder of the data field is filled with 00 (zeros).
The FDC reads the 10 field of each sector and checks
the CRC bytes. If the FDC detects a read error (incorrect
CRC) in one of the 10 Fields, it sets the DE (Data Error)
flag of Status Register 1 to a 1 (high), andler,minates the
Write Data Command. (Status Register 0 also has bits 7
and 6 set to 0 and 1 respectively.)
The Write Command operates In much the same manner
as the Read Command. The following Items are the
same; refer to the R~d Data Command for details,:
• Transfer Capacity
• EN (End of Cylinder) FI~g
• NO (No Data) Flag
• Head Unload Time Interval
• 10 'Information when the processor terminates com·
, mand (sea Table 2)
• Definition of DTL when N = 0 and when N '" 0
all data fields on the track as continuous blocks of data.
If the,FDC finds an error In the 10 or DATA CRC check
bytes, it continues to read data from the track. The FDC
compares the 10 information read from each sector with
the value etored In the lOR, and sets the NO flag of
Status Register 1 to a 1 (high) If there Is no comparison.
Multi·track or skip operations are not allowed with this
command.
This command terminates when EOT number of sectors
have bean read. If the FDC does not find an 10 Address
Mark on the diskette after It encounters the INDEX
HOLE for the second time, then It sets the MA (missing
address mark) flag in Status Register 1 to a 1 (high), and
terminates the command. (Status Register 0 has bits 7
I
and 6 set to 0 and 1 respectively.)
READID
The READ 10 Command Is usad to give the present posl·
tion of the recording head. The FDC stores the values
from the first 10 Field It Is able to read. If no proper 10
Address Mark Is found on the diskette, before the IN·
DEX HOLE is encountered for the second time then the
MA (Missing Address Mark) flag In Status Register 1 Is
set to a 1 (high), and if no data Is found then the NO (No
Data) flag is aiso set In Status Register 1 to a 1 (high)
and the command Is terminated.
FORMAT A TRACK
The Format.Command allows an entire track to be·for·
matted. After the INDEX HOLE Is detected, Data Is writ·
ten on the Diskette: Gaps, Aqdress Marks, 10 Fields and
Data Fields, all per the IBM System 34 (Double DenSity)
or System 3740 (Single Density) Format a~ recorded.
The particular format which will be written Is controlled
by the values programmed Into N (number of bytes/sec·
tor), SC (sectors/cylinder), GPL (Gap Length), and 0
(Data Pattern) which are supplied by the processor duro
Ing the Command Phase. The Data Field Is filled with
the Byte of data stored in D. The 10 Field for each sector
is supplied by the processor; that Is, four data requests
per sector are made by the FDC for C (Cylinder Number),
H (Head Number), R(Sector Number) and N(Number of
Bytes/Sector). This allows the diskette to be formatted
with nonsequential, sector numbers, if desired.
in the Write Data mode, data transfers between the proc·
essor and FDC must occur every 31 ,..s In the FM mode,
and every 15 ,..s In tlle MFM mode. If the time Interval
between data transfers Is longer than this then ~he FDC
sets·the OR (Over Run) flag in Status Register 1 to a 1
(high), and terminates the Write Data Command.
For minl·floppies, multlpie track writes are usually not
permitted. This Is because of the turn-off time of the
erase head coils-the head switches tracks before the
erase head turns off. Therefore thll system 'should
typically walt 1.3 mS before attempting to step or
c!,!ange sides.
,"
WRITE DELETED DATA
This command is the same as the Write Data Command
except a Deleted Data Address Mark Is written at the
beginning of the Data Field instead of the normal Data
Address Mark.
'
READ DELETED DATA
This ', DProcessor
0FDD ;t.. DProces8or
DFDD
When either the STP (contiguous sectofsSTP=01. or
alternate sectors STP = 02 sectors are read) or the MT
(Multi-Track) are programmed, It Is necessary to
remember that the last sector on the track must be read.
For example. If STP = 02, MT 0, the sectors are
numbered sequentially 1 through 26, and we start the
Scan Command at sector 21; the following will happen.
Sectors 21, 23, and 25 will be read, then the next sector
(26) will be skipped and the Index Hole will be encountered before the EOT value of 26 can be read. This
will result In an abnormal termination of the command.
If the EOT had been set at 25 or the scanning started at
sector 20, then the Scan Command would be completed
in a normal manner.
=
Dyrhlg the Scan Command data Is supplied by either the
processor or DMA Controller for comparison against the
data read from the diskette. In order to avoid haVh'lg the
OR (Over Run) flag set in Status Register 1, It is necessary to have the data availabl~ in less than 27 ,..s (FM
Mode) or 13 ,..s (MFM Mode). If an Overrun occurs the
FDC terminates the command.
SEEK
The read/write head within the FDD Is moved from
cylinder to cylinder under control of the Seek Command.
The FDC compares the PCN (Present Cylinder N\.!mber)
which is t~e current head position with the NCN (New
Cylinder Nu'mber), and performs the following operation
If there Is a difference:
PCN < NCN: Direction signal to FDD set to a 1,(high).
and·Step Pulses are issued. (Step In.)
PCN > NCN: Direction signal to FDD set to a 0 (low).
and Step Pulses are issued. (Step Out.)
+Dprocl8sor
If the FDC encounters a Deleted Data Address Mark on
one of the sectors (and SK 0), then It regards the sector as the last sector on the cylinder. sets CM (Control
=
Mark) flag of Status Register 2 to a 1 (high) and terminates the command. If SK= 1. the FDC skips the sector with the Deleted Address Mark, and reads the next
sector. In the second case (SK= 1), the FDe sets the CM
(Control Mark) flag of Status Register 2 to a 1 (high) in
order to show that a Deleted Sector had been encountered.
The rate at which Step Pulses are Issued is controlle!l.by
SRT (Stepping Rate Time) in the SPECIFY Command.
After each Step P·ulse is Issued' NCN is compared
against PCN. and when NCN = PCN, then the SE(Seek
End) flag.ls set In Status Register 0 to a 1 (high). and the
command is terminated.
6-562
AFN·01259C
8272A
During the Command Phase of the Seek operation the
FDC Is In the FDC BUSY state, but during the Execution
Phase It Is In the NON BUSY state. While the FDC Is In
the NON BUSY state, another Seek Command may be
Issued, and In this manner parallel seek operations may
be done on up to 4 Drives at once.
If an FDD Is In a NOT READY state at the beginning of
the command execution phase or during the seek opera·
tlon, then the NR (NOT READy) flag Is set In Status
Register 0 to a 1 (high), and the command Is terminated.
Note that the 8272A Read and Write Commands do not
have Implied Seeks. Any R/W command should be
preceded by: 1) Seek Command; 2) Sense Interrupt
Status; and 3) Read 10.
RECALIBRATE
This command causes the read/write head within the
FDD to retract to the Track 0 pOSition. The FDC clears
the contents of the PCN counter, and checks the status
of the Track 0 signal from the FDD. As long as the Track
osignal Is low, the Direction signal remains 1 (high) and
Step Pulses are Issued. When the Track 0 signal goes
high, the SE (SEEK END) flag In Status Register 0 Is set
to a 1 (high) and the command Is terminated. If the Track
o Signal Is stili low after 77 Step Pulses have been
Issued, the FDC sets the SE (SEEK END) and EC (EQUIP·
MENT CHECK) flags of Status Register Oto both 1s
(highs), and terminates the command.
The ability to overlap RECALIBRATE Commands to
multiple FDDs, and the loss of the READY signal,. as
described. in the SEEK Command, also applies to the
RECAllBRATE Command.
SENSE INTERRUPT STATUS
An Interrupt signal Is generated by the FDC for one of
the following reasons:
1. Upon entering the Result Phase of:
a. Read Data Command
b. Read a Track Command
c. Read 10 Command
d. Read Deleted Data Command
e. Write Data Command
f. Format a Cylinder Command
g. Write Deleted Data Command
h. ,Scan Commands
2. Ready Line of FDD changes state
3. End of Seek or Recallbrate Command
4. During Execution Phase In the NON·DMA Mode
Interrupts caused by reasons 1 and 4 above occur during
, normal command operations and,. are easily discernible
by the processor. However, Interrupts caused by
reasons 2 and 3 above may be uniquely Identified wl~h
the aid of the Sense Interrupt Status Command. This
command when Issued resets the Interrupt signal and
via bits 5, 8, and 7 of Status Register 0 identifies the
cause of the Interrupt.
'
Neither the Seek or Recallbrate Command haife a Result
Phase. Therefore, It Is mandatory to use the Sense Inter·
rupt Status command after these commands to effec·
tively terminate them and to provide verification of the
head position (PCN).
Tabl.11. S.ek, Interrupt Cod••
SEEK END INTERRUPT CODE
BITS
BITe BIT7
CAUSE
0
1
1
Ready Line changed
state, either polarity
1
0
0
Normal Termination
of Seek or Raeallbrate
Command
1
1
0
Abnormal Termination of
Seek or Reeallbrate
Command
SPECIFY
The Specify Command sets the Initial values for each of
the three Internal timers. The HUT (Head Unload Time)
defines the time from the end of the Execution Phase of
one of the ReadIWrlte Commands to the head unload
state. This timer Is programmable from 16 to 240 ms In
increments of 1~ ms (01 = 16 ms, 02= 32 ms .... OF =
240 ms). The SRT (Step Rate Time) defines the time in·
terval between adjacent step pulses. This timer Is programmable from 1 to 16 ms In increments of 1 ms (F = 1
ms, E = 2 ms, 0 = 3 ms, etc.). The HlT (Head load Time)
defines the time between when the Head load Signal
goes high and when the Read/Write operation starts.
This timer Is programmable from 2 to 254 ms in In·
crements of 2 ms (01 = 2 ms, 02 = 4 ms, 03 = 6 ms .•..
FE=254 ms).
The step rate should be programmed 1 mS longer than
the minimum time required by the drive.
The time Intervals mentioned above are a direct function
of the clock (ClK on pin 19). Times indicated above are
for an 8 MHz clock, If the clock was reduced to 4 MHz
(mini·floppy apPlication) then all 'time intervals ara in·
creased by a factor of 2.
The choice of DMA or NON·DMA operation Is made by
the NO (NON·DMA) bit. When this bit Is high (NO = 1) the
NON·DMA mode Is selected, and when NO = 0 the DMA
mode Is selected.
SENSE DRIVE STATUS
This command may be used by the processor whenever
It wishes to obtain the status of the FDDs. Status
Register 3 contains the Drive Status Information.
INVALID
If an invalid command is sent to the FDC (a command
not defined above), then the FDC will terminate the command. No interrupt Is generated by the 8272A during this
condition. Bit 6' and bit 7 (010 and RQM) in the Main
Status Register are both high ("1") indicating to the,
processor that the 8272A is in the Result Phase ",nd the
contents of Status Register 0 (STO) must be read. When
the processor reads Status Register 0 it will find an 80H
indicating an invalid command was received.
A Sense Interrupt Status Command must be sent after a
Seek or Recallbrate interrupt, otherwise the FDC will
consider the next command to be an Invalid Command.
I n some applications the user may wish to use this com·
mand as a No·Op command, to place the FDC in a stand·
by or no operation state.
AFN·OI258C
intJ
8272A
Table,2. Status Reglate,.
BIT
NO.
NAME
BIT
DEBCRIPTION
SYMBOL
NO.
STATUS REGISTER 0 '
07
Inlerrupl
Code
IC
SYMBOL
01
Not
Writable
NW
During execullon of WRITE DATA,
WRITE DELETED DATA or Formet A
Cylinder Command, If Ihe FDC
detects a wrlle protect signal from
,Ibe FDD, then Ihls flag Is ael.
Do
Missing
Address
Mark
MA
If Ihe FDC cannol detect lhe 10
Address Mark after encounlerlng the
Index hol.lwlce, lhen Ihls Ilag Is set.
If Ihe FDC cannol delecllhe Data
Address Mark or Delated Dala
Address Mark, Ihls nag, Is 1181, Also
allhe same lime, Ihe MD (Missing
Address Mark in Data FIeld) of
Stalus Reglsler 2 Is set.
07= 1 and De=O
Invalid Command Issue, (IC).
(i:ommand which was issued was
never slarted.
07",1 and Ds= 1
Abnormal Termination because
during command execution Ihe
nsady signal from FDD changed
slale.
DalaErrorin
Dala Field
DO
If the FDC delecls a CRC error In
Ihe data field Ihen Ihls flag Is set.
04
Wrong"
Cylinder
WC
This bills relaled wllh 111$ NO bll,
and when Ihe conlsnls of C on the
medium Is dlfferenl from thai stored
In the lOR, this flag Is set.
1;)3
Scan Equal
Hit
SH
During execution, the SCAN
Command, If the conditio!, of
"equal" Is satisfied, this flag Is aet.
O2
Scan Not
Satisfied
SN
During executing the SCAN
Command, If the FDC cannot fond a
Sector on the cylinder which meets
the conditIon, then this flag is set.
01
Bad
Cylinder
Be
This bit Is related with the NO bit,
and when Ihe conlenl of C 00 Ihe
medium Is dlfferenl from Ihai stored
in the lOR and the content of C Is
FF" then this flag Is set.
Do
Missing
Addres.
Mark In Data
Field
MD
When data Is read from the medIum,
If Ihe FDC cannot find a Data
Address Mark or Deleted Data
Address Mark, lhen this flag Is set.
07
Fault
FT
this blt 18 used to Indicate the
status of the Fault signal from the
FDD.
08
Write
Protected
WP
ThiS bit Is used to Indicate the
status of the Write Protected .Ignal
from the FDO.
Os
Reedy
ROY
This bit ;s used to Indicate the status
of the Ready signal from the FDD,
During executing Ihe READ 10 Com·
mand, If Ihe FDC cannol read the
10 field wllhout an, error, Ihen Ihis
flag Is set.
04
Track 0
TO
This bit is uaed to indicate the status
of the track a signal from the FDD,
03
Two Side
TS
This bit Is used to Indicate the status
of the Two Side signel from Ihe FDO.
During Ihe execution of Ihe RE""o" A
Cylinder Command, If the starting
seclor cannot be found, Ihen this
flag Is set.
O2
Head
Address
HD
.0,1
Unit Select 1
USI
This bit Is used to l'1dlcate ihe status
of the Unit Select 1'8lgnal to th, FOD.
,
Do
Unit Select 0
usa
This bit is used to Indicate the status
of the Unit Select 0 signal tothe FOD.
When Ihe FDC compleles Ihe
SEEK Command, Ihls flag Is aello 1
(high). '
04
Equipmenl
Check
eC
If a fault Signel Is received from Ihe
FDD, Dr If Ihe Track 0 Signal falls 10
occut after 77 Slep Pulaes (Recall·
brale Command) then Ihls flag Is set.
Nol Ready
NR
When Ihe FDD Is In Ihe nol·reedy
slale and a read or wrlle cqmmand Is
issued, Ihls flag is set. If a read or
wrlle command is issued 10 Side 1
of a single sIded drive, then this flag
Is aet.
O2
Head
Address
01
Unit Selectl
USI
Do
Unit Select 0
usa
07
End of
Cylinder
This flag is uaed 10 Indlcale Ihe
state of the head IIllnterrupl.
EN
When the FDC tries 'to access a
Sector beyond the final Sector of a
Cylinder, this flag Is 88t.
05
Data Error
DE
When the FDC detects a CRe error
In either the 10 field or the data field,
thIS flag Is set.
04
Over Run
OR
If the FDC Is not serviced by the
main-systems during data transfers,
within a certain time Interval, this
flag Is set.
Nol used This bit Is always 0 (low).
03
STATUS REGISTER 3,
Not uaed. This bit always 0 (low).
No Data
NO
, CM
These flags are uaed to indicate a
Drive Unit Number allnterrupt
STATUS REGISTER 1
O2
Durtng executing Ihe READ ,DATA 6r
SCAN Command, If Ihe FDC
encounlers a Seclor which conlalns
a Deleled Data Address Mark, Ihls
flag Is set.
Os
SE
06
Noi used. This ,bll Is always 0 (Iow~
Conlrol
Mark
Seek End
' HD
STA1'II8 REGISTER 2
07
08
Os
03
DEBCRIPTION
IITATUS REGISTER 1 (CONT.)
"
07=0 and 08=0
Normal Termlnallon of Command,
(N1). Command was compleled and
properly execuled,
07=0 and 08= 1
Abnormal Termlnallon of Com·
mand, (A1). Execullon of Command
was started, but was not
successfully compleled,
08
NAME'
During execution of READ DATA,
WRITE DELETED QATA o~ SCAN
Command, If the'FCC cannot find
the Seclor specified In Ihe lOR
Raglsler, lh1s flag Is aet.
6-564
,
This bit Is used to indicate the status
of Side Select slgnallo'the FDD.
AFN-01259C
inter
8272A
ABSOLUTE MAXIMUM RATINGS*
NOTICE: Stress above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Expo~ure to absolute maximum rating
conditions for extended p~riods may affect device
reliability.
Operating Temperature .................. O°C to + 70°C
Storage Temperature .•........... -40·C to +125·C
All Output Voltages ...•........... -0.5 to + 7 Volts
'All Input Voltages .....•........... -0.5 to + 7 Volts
Supply Voltage Vee ..•............ -0.5 to + 7 Volts
'Power Dissipation .. : .•.................•... 1 Watt
D.C. CHARACTERISTICS
(TA = O°C to + 70·C, Vee = + 5V ± 10%)
Limits
Symbol
Parameter
Min.
Max.
Unit
V
Test
Conditions
VIL
Input Low Voltage
-0.5
0.8
V IH
Input High Voltage
2.0
Vee+ 0.5
V
0.45
V
IOL=2.0 mA
Vee
V
10H = -400 /loA
VOL
Output Low Voltage
VOH
Output High Voltage
Icc
Vee Supply Current
120
mA
IlL
Input Load Current
(All Input Pins)
10
-10
/loA
/loA
VIN = Vee
VIN=OV
ILOH
High Level Output
Leakage Current
10
/loA
VOUT= Vee
±10
/loA
2.4
' Output Float
Leakage Current
IOFL
CAPACITANCE
(TA = 25·C, Ie = 1 MHz, Vec = OV)
,
Limits
Parameter
CIN("')
Clock Input Capacitance
20
pF
C IN
Input Capacitance
10
pF
CliO
Input/Output Capacitance
20
pF
Min.
Max.
A.C. CHARACTERISTICS (TA =O·C to +70·C, Vce= +5.0V
Test
Conditions
Unit
Symbol
CLOCK
O.45V "" VOUT "" Vee
All Pins Except
Pin Under Test
Tied to AC
Ground
± 10 0M
TIMING
Symbol
ICY,
ICH
lAST
Parameter
Clock Period
Clock High Period
Reset Width
Min.
Max.
120
500
40
14
Unit
ns
ns'
tey
Not••
Note 5
Note 4, 5
READ CYCLE
tAR.
IAA
IAA
lAD
IOF
Select Setup t9 RD(
Select Hold from AD!
RD Pulse Width
Data Delay from RDI
Output Float Delay
0
0
250
200
20
6-565
100
ns
ns
ns
ns
ns
AFN·OI259C
intJ
8272A
A.C. CHARACTERISTICS (Continued) (TA=O·C to +70·C, vcc= -+:5.0Y
:1:10%)'
WRITE CYCLE
P!araIIIeIer
Symbol
Typ.1
Select Setup to ~
tAW
twA
Select Hold from ~
tWw
WI!I' Pulse Width
tow
Data'Setup to
two
Data Hold from WAf
WJii,
Min.
Max.
Unit
0
ns
0
ns
250
150
ns
5
ns
NoIH
ns
1m!
Note 6
INT Delay from Wilt
NoteS
INT Delay from
tRQCY
ORO Cycle Period
tAKRQ
~!toDRQI
13
I'J5
200
NoteS
ns
tRQR
ORO! to lifi!
600
ns
NoteS
tRQW
DRat toWII!
250
ns
NoteS
tRQRW
DRat to Alit or WFft
~s
Note 6
I'J5
MFMzO Note 2
MFM=1
12
FDDINTERFACE
WCK ~cle Time
20r4
lor2
tWCH
WCK High Time
250
tcp
Pre·Shlft Delay from WCK!
tco
WDA Delay f~om WCK!
twoo
Write Data Width
tWCY
ns
20
100
ns
20
100
ns
100
"s
ns
60
tWCH-5P
WE! to WCK! or WEI to WCKI Delay
tWE
350
20
twwqv
Window Cycle Time
2
1
twRo
Window Setup to ROOt
15
ns
tROW
WindOW Hold from RDDI
15
ns
tROD
ROD Active Time (HIGH)
40
ns
• _c
~s
MFM=O
MFM=1
FDD SEEKIDIRECTIONISTEP
tus
USo 1 Setup to RWISEEK!
12
~s
• Note S
tso
USo 1 Hold after iiWlSEEKI
15
~s
NoteS
ISO
RWISEEK Setup to LCTIDIR
7
~s
NoteS
tos
RWISEEK Hold from LCTIDIR
30
~s
NoteS
tOST
LCTIDIR Setup to FAlSTEPt
1
~s
NoteS
tSTo
LCT/DIR Hold from FRiSTEPI
24
I'J5
Note 6
5
tSTU
OS:! 1 Hold from FAlStepl
tSTP
STEP Active Time (High)
ISC
STEP Cycle Time
33
tFR
FAULT RESET Active Time (High)
8
tlOX
INDEX Pulse Width
ITC
Terminal Count Width
5
10
10
1
~s
NoteS
I'J5
Note 6
~s
Note 3, S
I'J5
Note 6
tCY
troy
NOTES:
1. Typical valuea for TA _ 25'C and nominal supply voltage•
• 2. The former values are used for standard floppy' and the latter valuea are used for II)lnl.flopples.
9. tsc = 331'J5 min. Is for different driVe units. In the case of same unit, ISC can be ranged from 1 ms to IS ma with 8 MHz clock period, and 2 ms
to 32 ma with 4 MHz clock, ullder software conirol. .
4. From 2.0V to
+ 2.0V •
5. At 4 MHz, the clock duty cycle may range from IS% to 76%. USing an 8 'MHz clock the duty cycle can range from 32% to 52%. Duty cycle Is
defined aa: D.C. = 100 (tCH + tCY) with typical ria. and falltlmea of 5 na.
.
8. The spaclfled values listed are for an 8 MHz clock period. Multiply tlmlngs by 2 when ualng a 4 MHz clock parlod.
6-566
inter ,
8272A
A.C. TESTING INPUT, OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
INPUT/OUTPUT
~TE_N'1lE_:_R_ ~~. ,.~
....1__
A.C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC "1" AND 0 45V FOR
A LOGIC "0 " TIMING MEASUREMENTS ARE MADE /IJ 2.OV FOR A LOGIC "I"
AND 0 IV FOR A LOGIC "0"
...
CL= 100pF
C,INCWDES JIG CAPACITANCE
WAVEFORMS
F
PROCESSOR READ OPERATION
AO'Ci,=>t
DACK
_
-"-R----I--..---------------------,R-R=========~~~-..j-I----,RA
'
~----IRD'----_+I
DATA -
-
-
-
-
-
-
-
-
-
-
-
INT
6-567
AFN·Ol26IIC
inter
8272A
WAVEFORMS (Continued)
''\-''
PROCESSOR WRITE OPERATION
A,. CS. DACK
!+-_ _ _ lwW _ _ _ _
~
DATA
IWI----+l.~ ..
•NT
DMA OPERATION
DAD
!+-------IRQRW-------+!
WI!.r AD
!-----IRQW----!
!+-_--I.Q.---~
6-568
AFN·Ol259C
8272A
WAVEFORMS (Continued)
CLOCK TIMING
CLK
FDD WAITE OPERATION
WRITE ENABLE
(WE)
PRESHIFTO
PRESHIFT 1
NORMAL
0
0
LATE
0
1
EARLY
1
0
INVALID
1
1
6-569'
AFN·01258C
8272A
WAVEFORMS (Continued)
SEEK OPERATION
STABLE
.....-ID8
LeT!
DIRECTION
STEP
1-----------',c-----------1
INDEX
FlT RESET
FAULT RESET
FAIL UNSAFE RESET
I
6-570
AFN-OI259C
inter
8272A
WAVEFORMS (Continued)
FDD READ OPERATION
A A ,o o A 4
RE
tROD
~-------------------------
~,1--'.
___
_
READ DATA
WINDOW
-IWRO-
-----------------------------
1--------tWWCy--------~
•
TERMINAL COUNT
1
RESET
RESET
TC
6-571
AFN·01259C
intJ
.
82062
WINCHESTER DISK CONTROLLER
~
Mult,ple Sector ll'ansfer Capability .
5 MBIt/Sec Transfer Rate
•
Implied Seek With Read/Write Commands
•
128, 256, 512, and 1024 Byte Sector
Lengths
•
7 Byte Sector Length Extension For
External Error Correction Code
•
Six High-Level Commands: Restore, Seek,
Read Sector, Write Sector, Scan ID, and
Write Format
• Single +5 Volt Power Supply
•
Controls ST506/ST412 Interface
WInchester Drives
•
The 82062 Winchester Disk Controller (WDC) device interfaces microprocessor systems to Winchester Disks
that use the Seagate Technology ST506/ST412 interface. Examples include the Seagate ST506 and ST412,
Shugart SA604 and SA606, Tandon 600, al')d Computer Memories CM5206 and CM5412. The device translates
. parallel data from the microprocessor tq a 5 mbiVsec, MFM-encoded serial bit stream. It· provides all of the
drive control logic and, in addition, control signals which simplify the design of an external phase locked loop
and write precompensation circuitry. The 82062 is designed to interface to the host controller through an
external sector buffer.
TASK, STATUS. DATA
REGISTERS
DATA
080-7
BUS
BUFFER
__
WNI'E
CONIROI.
Vee
RDCLOCK
RDGATE
WRDATA
BORO
LATE
"we
iiiiET
RDDATA
EARLY
WRCLOCK
BRD.
WA
Ci
....
INTRO
"EAD
CONIROI.
Rii
AM IlEI'ECT
MOM DECODE
w;;
Ci
AWe
RDDATA
ROGATE
WAFAULT
DRUN
INDEX
RDCLOCK
. .D.
STEP
WRGATE
BROY
Bes
DRUN
8C
BUFFER
'STEP
.,"
CONTROL
BOflO
iCii
DRIYE
VCC----'
INTERFACE
CONTROL
Vss--+-
DRD.
WR FAULT
DB<
I
"'"
WRCLOCK
WAGAr!
EAIii:Y
Wi
WRDATA
TRACK 000
INDEX
Be
. Figure 1. 82062 Block Diagram
Figure 2• Pin Configuration
NOVEM.BER1983
6-572
Order Number: 210446-002
inter
82062
Table 1. Pin Description
Type
Name and Function
1
0
Buffer Chip Select: Output used to enable reading or writing of the external
sector buffer.
BCR
2
0
Buffer Counter Reset: Output that is strobed by the WDC prior to readlwrite
operation. This pin IS strobed whenever B'CS changes state. It can be
optionally used to reset the address counter of the buffer memory.
INTRa
3
0
Interrupt Request: Interrupt generated by the WDC upon command termination. It is reset when the status register is read.
RESET
5
6
I
Reset: Initializes the controller and clears all status flags.
RD
1/0
Read:' As an Input.J~P controls the transfer of status information from the
WDC to the host. RD is an output when the WDC is reading data from the
sector buffer.
WR
7
1/0
Write: As an input, WR controls the transfer of command or task information
into the WDC register file. iNA is an output when theWDC is writing data to
the sector buffer.
Symbol
BCS
Pin No.
~
8
1
9-11
I
,12-19
1/0
I
Ground
WR DATA
20
21
0
LATE
22
a
Write Data: Open drain output that shifts out MFM data at a rate determined
by the Write Clock Input
EARLY
23
0
Early: Open drain output used to derive a delay value for write precompensatlon Valid when the WR GATE output IS high
WR GATE
24
0
Write Gate: High when write data IS ~alld WR GATE goes low If the WF input IS
high. This output is used by the dnve to enable head wnte current
WR CLOCK
25
I
Write Clock: Clock Input used to derive the write data rate Frequency ~ 5MHz
for the ST506 interface, 4.34MHz for the SA 1000 Interface.
DIR
26
0
Direction: High level on thiS output tells the drive to move the head inward
(increasing cylinder number) The signal ,IS determined by the WDC
commands.
STEP
27
0
Step: Provides 8.4 microsecond pulses to move the drive head to another
cylinder
DRDY
28
I
Drive' Ready: If DRDY from the drive goes low, all commands Will be
deactivated
INDEX
29
I
Index: Signal from the drive indicating the beginning of a track. It IS used by
the WDC dUring formatting, and for counting retnes
WR FAULT
30
I
Write Fault: An error Input to the WDC which indicates a fault condition at. the
drive If WR FAULT from the drive goes low,' all commands Will be
deactivated.
TRACK 000
31
I
Track Zero: Used by the Restore command to verify that the head IS at the
outermost cylinder.
SC
32
I
Seek Complete: Signal from the drive indicating that reads or writes can be
made
RWC
33
0
Reduced Write Current: Signal' goes high for all cylinder numbers above the
value programmed to the Write Precomp Cylinder register It is used by the
precompensatlon logic and by the drive
DRUN
34
I
'Data Run: Looks for a string of zeros or ones In the read data, indicating the
beginning of an ID field If the zeros are detected, RD GATE IS brought high
BRDY
35
I
Buffer Ready: Input used by the buffer memory to signal the controller that it
IS ready for reading (full) or writing (empty). BROY,ls checked dUring Read
and Write commands.
BDRa
36
0
Buffer Data Request: Optionally activated during Read or Wnte commands If
BRDY is high. Can be used as a DMA Request line.
CS
Aa-A 2
DBrDBa
GND
Chip Select: Enables RD or WR as inputs
Address: Used to select a register from the task register file
Data Bus: Bidlrecllonal 8-blt Data Bus
Late: Open drain output used to derive a delay value for wnte precompensatlon Valid when the WR GATE output is high.
RD DATA
37
I
Read Data: Single ended input that accepts MFM data from the drive.
RDGATE
38
0
Read Gate: Output that IS high for data and ID fields.
RD CLOCK
39
. I
Vee
40
I
Re.ad Clock: Clock input deriv,ed from the external data recovery circuits.
D.C .. Power: +5V
6-573
210446-002
82062
FUNCTIONAL DESCRIPTION
INTERNAL ARCHITECTURE
The Intel 82062 Winchester Disk Controller (WDC)
integrates much of the logic needed to implement
Winchester Disk cohtroller subsystems. It provides
MFM-encoded data and all the control lines required
by hard disks using the Seagate Technology ST506
or Shugarf Associates SA1000 interface standard.
Currently, most 5'14 inch and many8 inch Winchester
Drives use this interface.
The internal architecture of the 82062 WDC is shown
in more detail in Figure 4. The major functional
blocks are:
PLA Controller
The PLA interprets commands and provides all control functions. It is synchronized with WRCLOCK.
Due to the higher data rates required by these
drives-1 byte every 1:6 usec-the 82062 is designed
to interface with the host CPU or I/O controller
through an external buffer RAM. The 82062 WDC has
four pins that minimize the logic required to design a
buffer interface.
Magnitude Comparator
A 1O-bit magnitude comparator is used forthe calculation of drive step, present and desired cylinder
position.
Figure 3 shows a block diagram of an 82062 subsystem. The WDC is controlled by the host CPU through
six commands:
CRC Logic
Generates and checks the cyclic redundancy check
characters appended to the ID and data fiel9s. The
polynomial used is:
Restore
Seek
Read Sector
Write Sector
ScanlD
Write Format
X 16
x
+ X12 + 5 + 1.
MFM Encode/Decode
These commands use information stored by six task
registers. Command execution starts immediately
after the command register is loaded-'-therefore
commands require only one byte from the CPU after
the WDC has been initialized.
Encodes and decodes MFM data to be written/read
from the drive. The MFM encoder operates from WR
CLOCK. a clock having a frequency equivalentto the
bit rate. The MFM decoder operates from RD CLOCK,
a bit rate clock generated from the external data
separator. RD CLOCK and WR CLOCK need not be
synchronized.
The 82062 adds all the required track formatting to
the data field, including twq bytes of CRC. Optionally,
these two bytes can be replaced by seven bytes of
ECC information for external·error correction.
1 - - - - - - - - - - - - - 1 BORQ
1------------1'NTRQ
~==:::Qj!m~~!llI==~
080-7
~
AD,WR
'""======:;-]
EARi:Y, tffilRwe
82082
woe
WRDATA
10 MHZ
t----~cs
DRIVE CONTROL
Figure 3.
System Block Diagram .
6-574
210446-002
inter
82062
080·7
WRDATA
WR CLOCK
iii)
,
Wii
j
AO·2
INTRQ
.•
I
RDCLOCK
HOST
IFC
R'EsET
Cs
RDDATA
PLA
CONTROLLER
STEP
DIRC
iiCR - - , - ~-l--""'---1..j
BRDY
mIi:Y
....- - - - - -...
WE
BORQ
I
DRDY
iiCi
WR FAULT
TRACK 000
INDEX
se
Rwe
'--____
Figure 4.
DRUN
82062 Detailed Block Diagram
AM Detect
The address mark detector checks the incoming data
stream for a unique missing clock pattern (Data =
A1 H, Clock = OAH) used in each lD and data field.
Host/Buffer Interface Control
The Host/Buffer IFC logic contains all of the necessarycircuitryto communicate with the 8-bit bus from
the host processor.
Drive Interface Control
The Drive IFC logic controls and monitors all lines
from the drive, with the exception of read and write
data.
DRIV~
WRGATE
RO GATE
~
INTERFACE
The buffer/receivers condition the control lines to
be driven down the cable to the drive. The control
lines are typically single-ended, resistor terminated
TTL levels. The data lines to and from the drive also
require buffering, but are differential RS-422 levels.
The interface speCification to the drive can be found
in the manufacturers' OEM manual. The WDC supplies TTL compatible signals, and will interface to
most buffer/driver devices.
The data recovery circuits consist of a phase-lock
loop data separator and associated components.
The 82062 WDC interacts with the data separator
thru the DATA RUN (DRUN) and RD GATE signals.
A block diagram of a typical data separator circuit is
shown in Figure 6. Read data from the drive is presented to the RD DATA inputof the WDC, the reference multiplexor,and a retriggerable one-shot. The
RD GATE (Pin 38) output will be low when the WDC
is not inspecting data. The PLL at this time should'
remain locked to the reference clock.
The drive side of the 82062 WDC requires three sections of external logic. These are buffer/receivers,
data separator, and write precompensation. Figure 5
illustrates a drive side interface.
6-575'
210446-002
82062
2X
DATA RAte
WRITE DATA
EARLY
WRITE
PRECOMP
LATE
WINCHESTER DRIVE 0
Rwe
WRITE DATA
READ DATA
READ DATA
PHASE
LOCK
LOOP
READ CLOCK
DRUN
DRIVE SEL
READ GATE
STEP
TO NEXT
DRIVE
82062
woe
DIRECTION
DATA
WR CLOCK
RATE
READY
osc
WRITE FAULT
sc
, TRACK 000
INDEX
INDEX
TKOOO
seEK COMPLETE
DRDY
Rwe
WFI FAULT
HEAD NUMBER
DIR
WRITE GATE
WR GATE
STEP
DATA BUS
I
DAISY CHAIN TO
Q
ADDRESS
NEXT DRIVE
(HOLDS DRIVE ANI) HEAD
SELECTS)
DATA LATCH
Figure 5.
Drive Interface
RETR)GGERABLE
ONE-SHOT
....-----------.._~ DRUN
~----. .--------------------------------~~RDDATA
82062
....---..-----1'""
RD CLOCK
~~~~---------~----------~RDGATE
~---------------------------.._------------~WRCLOCK
Figure 6.
Data Recovery Circuit
6-57.6
210446-002
82062
When any Read/Write' command is initiated and a
search for address mark begins. the DRUN input is
examined. The DRUN one-shot is set for slightly
greater than one bit time. allowing it to retrigger
constantly on a field of ones and zeros. An internal
counter times out to see that DRUN is high for 16
bits (2 byte times). RDGATE is set by the WDC.
switching the data separator to lock onto the incoming data stream. If DRUN falls priorto,12 bit times,
RD GATE is lowered and. the process is repeated.
RD GATE will remain active high until a non-zero.
non-address mark byte is detected. It will then lower
RD GATE for two byte times (to allow the PLL to
lock back on to the referenc,e clock), and start the
DRUN search again. If an address mark is detected.
RD GATE will be held ,high and the command will
continue searching for the proper 10 field. This
sequence is shown in the flow chart in Figure 7.
The write precompensation logic is controlled by
theRsignals REDUCE WRITE CURRENT (RWC).
EA LY and CA'i'E. The cylinder in which the RWC
line becomes active is controlled by the REDUCE
WRITE CURRENT register in the Task Register File.
It can be used to turn on the precomp Circuitry on a
predetermined cylinder. If the REDUCE WRITE
CURRENT register contents are FFH. then RWC will
always be low.
RESET
RD GATE
The signals EARLY and tATE' are used to tell the
precomp circuitry how much deJay is required on
the WR DATA pulse about to be sent. The amount of
delay is determined externally through a di9it~
delay line or equivalent Circuitry. Since the EARL
signal occurs after the fact. WR DATA should be
delayed byone interval when both EAFi'i:Yand LATE
are low. two~als when CA'fE is high. and no
delay when EARLY is high. An interval is. for exam~2-15 ns. for the ST506 interface. EARLY or
LATE ~ctive Slightly ahead of the WR DATA
pulse. EARLY and LATE will never be high at the
sa":,e time. =egardle~.2!Jhe contents of the RWC
regIster. EA LYand LATE will always be active.
HOST PROCESSOR INTERFACE
The primary interface between the host processor
and the 82062 WDC is through an 8-bit bi-directional
data bus. This bus is used to transmit/receive data to
both the WDC and a sector buffer. The sector buffer
is constructed with either FIFO memory. or static
RAM and a counter. Since the WDC will use the data
bus when accessing the sector buffer. a transceiver
J1I1ust be used to isolate the host during this time.
Figure 8 shows a typical connection to a sector
buffer implemented with RAM memory. Whenever
the WDC is not using the sector buffer. The BUFFER
CHIP SELECT (BCS) is high (disabled). This allows
th:e host to access the WDC's Task RegiSter File. and
Figure 7.
6-577
PLL Control Sequence
210446-002
inter
821)62
. When the woe is done.using the buffer, it disables
B'CS which again allows the host to access the local
bus. Tbe READ SECTOR command oper;atesin a
similar manner, except the buffer is loaded by the'
WOC instead of the host processor.
to set up parameters prior to issuing a command. It
also allows the host to access the RAM buffer. A:
decoder is used to generate a chip selectw~enAo_2.
is '000', an unused address in.Jb.e WQ.g. A bin~ry
counter is enabled whenever ,RD or WR go active
and is incremented on the trailing edge of· the chip.
select. This allows the host to access sequential
bytes within the RAM. The decoder also generates
another chip select when Ao-2 does not equal '000', .
allowing access to the WOC's int~rnal registers
. while keeping the RAM tri-stated.
Another control signal caned BUFFER DATA
REQUES, (BORQ, not used in Figure 8) is a OMA
Signal that can inform a OMA controller when the
82062 WOC is requesting data. For further explanation, refer to the individual command descriptions
and the A.C. Characteristics. In a READ SECTOR
command, interrupts are generated at the termination of the command. An interrupt may be specified
to occur either at the end of the command, or when
BORQ is activated. The INTERRUPT line (INTRQ)
is cleared either by reading the StATU~ register, or
by writing a new command in the COMMAND
register.
During a WRITE SECTOR command, the host processor sets up data in the Task Register File and
then issues the command. The 82062 WOC strobes
the BUFFER COUNTER RESET (BCR) signal to
zero the counter. It then generates a status to inform
the host that it may load the buffer with the data to
be written. When the counter reaches its maximum
count, the BUFFER READY (BROY) signal is made
active (by the "carry" out of the counter), informing
the WOC that the buffer is full. (BROY is a rising
edge triggered signal which wi!!..!2.!Wgnored if activated before the WOC issues BCR). BCS is then·
made active, disconnecting the host through the
transceivers, and the AD andWRlInes become outputs from the WOC to allow it to~ccess the buffer.
iiii
..J
iiii
I
Wil
DATA
Wil
~&J,
I
HOST
CPlt
DATA
8
~+
I
I
I
I
I
I
I
CK
Q
AD
WA
ADOR
,-T~
DATA
CS
j
---
SYSTEM
r-
~---
.rG=l
ADDRESS
, BCii
I
I
I
I
I
I
I
82062
I
BeS
BRDY
Co
.....
3
INTERRUPT
INTRQ
REseT
: RESET
L.::1...----.
. J.L
8.0.'
Figure 8.
........
ST.
.J OJ
DRive HEAD
SELECT
LATCH
CPU Buffer Interface
6-578
210446-002
82062
TASK REGISTER FILE
Bit 3 - Reserved Not used.
The Task Register File is a bank of registers used to
hold parameter information pertaining to each
command. These registers and their addresses are:
Forced to zero.
A2A1
0 0
0 0
0 1
0 1
1 0
1 0
AO
0
1
0
1
0
1
1 1 0
1 1 1
READ
(Bus Tri-Stated)
Error Flags
Sector Count
Sector Number
Cylinder Low
Cylinder High
SOH
Status Register
This bit is set if a command was issued while OROY
(Pin 28) or WR FAULT (Pin 30) is low. The Aborted
Command bit will also be set if an undefined command is written into the COMMAND register, but an
implied seek will be executed.
WRITE
(Bus Tri-Stated)
Reduce Write Curren
Sector Count
Sector Number
Cylinder Low
CyUnder High
SOH
Command Register
NOTE: Registers are not cleared by
Bit 2 • Aborted Command
Bit 1 • TRACK 000
This bit is set only by the RESTORE command. It
indicates that TRACK 000 (Pin 31) has not gone
active after the issuance of 1024 stepping pulses.
RESET.
ERROR REGISTER
Bit 0 - Data Address Mark
This read-only register contains specific error status after the completion of a command. The bits are
defined as follows:
This bit is set during a READ SECTOR command if
the Data Address Ma~k is not found after the proper
Sector 10 is read.
REDUCE WRITE CURRENT REGISTER
7
6
5
4
321
0
This register is used 'to define the cylinder number
where RWC (Pin'33) is asserted:
1BBO 1CRC 1- 1 10
7
6
5
4
3
2
1
o
Bit 7 - Bad Block Detect
This bit is set when an 10 field. has been encountered that contains a bad block mark. It is used for
bad sector'mapping.
Bit 6 - CRC Data Field
This bit is set when a data field CRC error has
ocurred or the Data Address Mark has not been
found. The sector buffer may still be read but will
contain errors.
Bit 5 - Reserved Not used.
The value (0-255) loaded into this register is internally multiplied by 4 to specify the actual cylinder
where RWC is asserted. Thus a value of 01 H will
cause RWC to activate on cylinder 4,02H on
cylinder 8, and so on. RWC switching points are
then 0,4,8, ... 1020. RWC will be asserted when the
present cylinder is greater than or equal to the
cylinder indicated by this register. For example, the
ST506 interface requires precomp on cylinder 128
(80H) and above. Therefore, the REDUCE WRITE
CURRENT register should be loaded with 32 (20H).
A value of FFH will make RWC stay low, regardless
of the actual cylinder number.
Forced to zero.
Bit 4 - 10 Not Found
This bit is set when the desired cylinder, head, sector, or size parameter cannot be found after 8 revolutions of the disk, or if an 10 field CRC error has
occured.
6-579
210446-002
82062:
SECTOR COUNT REGISTER
CYLINDER NUMB,ER LOW REGISTER
This register is used to define the number of sectors
that need to be transfered to the buffer during a
READ MULTIPLE SECTOR or WRITE MULTIPLE
SECTOR command.: '
This register holds the lower ,byte of the desired
cylinder number: '
7
,5'
6
4'
3
7
o
2. 1
4
3
2
1
The SECTOR NUMBER register is also used to program the Gap 1 and Gap 3 lengths to be used when
the WRITE FORMAT comformatting a disk.
mand description for further explanation.
543
S~ZE
.
.
f.
2
7
6
5
4
3
x
x
x
x
xx
2
1
0
(9)
(8)
I
The SDH register contains the desired sector size,
drive number, and head number parameters. The
format is diagramed below.
1
o
DRIVE
,
6
5
SECTOR SIZE
4
3
DRIVE #
0
0
1
1
0
256
512
1024
128
0
0
1
0
1
DSEL1
DSEL2
DSEL3
DSEL4
1
0
1
0
SECTOR/DRIVE/HEAD REGISTER
See
6
1
Internal to the 82062 WDC isanotherpairof registers
that hold the actual position where the RlW heads are
located. The CYLINDER NUMBER HIGH and LOW
registers can be considered the cylinder destination
for seeks and other commands. After these commands are executed, the internal cylinder position
registers' contents are equal to the cylinder high/low
registers. If a drive number change is detected 011 a
new command, the WDC automatically reads an ID
field to update its internal cylinder position registers.
This affects all commands except a RESTORE.
o
For a multiple sector command, it specifies the first
sector to be transferred. It is decremented after each
sector is transferred to/from the sector buffer.'The
SECTOR NUMBER register may contain any value
from 0 to 255.
7
2
This register holds the two most significant bits of the
desired cylinder number;
This register holds the '$ector number of the desired
sector:
5
3
CYLINDER NUMBER HIGH REGISTER
SECTOR NUMBER
6
4
It is used in conjunction with the CYLINDER
NUMBER HIGH register to specify a range of 0 to
1023.
The value contained in the register is decremen.ted
'after each sector is transferred to/from the sector
buffer, A zero represents a 256 sector transfer, a onea
o sector transfer, etc. This register is a "don't care"
when single sector commands are specified.
7
5
6
0
1
1
.
~
2
1
0
0
0
0
0
1
1
0
'0
l'
1
0
1
0
1
0
0
1
1
1
1
0
1
0
1
HEAD# .
HSELO
HSEL1
. HSEL2
HSEL3
HSEL:.4'
HSEL5 '
HSEL6
HSEL7
210446-002
inter
82062
Both head number and sector size are compared
against the disks' 10 field. Head select and drive
select 'lines 'are not available as outputs from the
82062 WDC and must be generated externally.
Figure 9 shows a possible logic implement,ation of
these'select lines.
Bit 7 - Busy
This bit is set whenever the 82062 WDC is accessing
the disk. Commands should not be loaded into the
OBO
081
WIi >------..
AD
A.
>--=----E-.....
==:::::I
L
>--I.~---J
A2
l!I)-_"";'_ _J
OBO l
08. A
OB2 T
DB3C
DB4 H
OSEl'
82062
DSEL2
DSEL3
DSEL4
Figure 9.
Drive/Head Select Logic
Bit 7, the extension bit (EXT), is used to extend the
data field by seven bytes when using ECC codes.
When EXT= 1, theCRC is not appended to the end of
the data field, the data field becomes "sector size + 7"
bytes long. The CRG is checked on the 10 field
regardless of the state of EXT. Note that the sector
size bits (SIZE) are written to the 10 field during a
formatting command. The SOH byte written into the
10 field is different than the SqH Register contents.
The recorded SOH byte does not have the drive
number (DRIVE) written but does have the BAD
BLOCK mark written. The format is:
7
6
3
4
5
2
1
o
Note that use of the extension bit requires the gap
lengths.to be modified as described in the WRITE
FORMAT command description.
STATUS REGISTER
The status register is a read-only register which
informs the host of certain events performed by tile
82062 WDC as well as reporting status from the
drive control lines.. The format is:
'
765
! BUSY! READY ! WF
4
3
SC
1 ORO ·1
1
2
1
CIP
0
I I
ERROR
COMMAND register while Busy is set. Busy is set·
when a command is written into the WDC and is
cleared at the end of all commands except READ
SECTOR. While executing a READ SECTOR command, Busy is cleared after the sector buffer has
been filled. When the Busy bit is set, no other bits in
either the STATUS or any other registers are valid.
Bit 6 - Ready
This bit normally reflects the state of the DRDY (Pin
28) line. When an interrupt is g'enerated by an
'aborted command' error condition, the Ready bit is
latched for later examination by the host. After a
STATUS register read, the Ready bit will resume
reflecting the state of DRDY.
• Bit 5 - Write Fault
This bit reflects the state of the WR FAULT (Pin 30)
line. Whenever WR FAULT goes high, an interrupt
will be generated. The Write Fault bit is latched Uke
the Ready bit (Bit 6).
Bit 4 .. Seek Complete
This ,bit reflects the state of the SC (Pin 32) line.
Certain commands will pause until Seek Complete
is set. The Seek Complete bit is latched like the
Ready bit.
6-581
210446-002
82062
INSTRUCTION SET
Bit 3 - Data Request
The Data request bit (ORO) reflects the'state of the
BDRO (Pin 36) line. It is set when the sector buffer
should be loaded with data or read by the host
processor, depending upon the command. The
DRO bit and the BDRO line remain high until BRDY
·is sensed, indicating the operation is completed.
BDRO can be used in DMA interfacing, while DRO .
can be used for programmed 1/0 transfers.
Bit 2 - Reserved
The 82062 WDC' instruction set contains, six
commands. Prior to .!oading the command register,
the host processor IT)ust first set up the. Task
Register File with the information needed for the
command. Except for the COMMAND register, the
registers may be loaded in any order. If a command
is in progress, a subsequent write to the COMMAND
register will be ignored until execution of the
current cQmmand is completed as indicated by the
command in progress bit in the STATUS register
, being cleared
Not Used. Forced to zero.
Bit 1 - Command in
Progres~
When this bit is set, a command is being executed
and a new command should not be loaded until it is
cleared. Although a commanq may be executing,
the sector buffer is still available for access by the
host processor. Only the STATUS register may ~e
read. If other registers are read, the STATUS register contents will be returned.
t
.
This bit is set whenever any bits' in the ERROR
register are set. It is the logical 'Or' of the bits in the
error register and may be used by the host processor to quickly check for successful completion of a
command. This bit is reset when a new command is
written into the COMMAND register.
COMMAND REGISTER
I
This write-only register is loaded with the qesired
command:
6
7 6 5 4
RESTORE
SEEK
READ SECTOR
WRITE SECTOR
SCANID
WRITE FORMAT
0
0
0
0
0
0
Rw
Bit 0 -Error
7
COMMAND
5
4
3
2
1
o
I
The command begins to execute immediately upon
loading. This register should not be loaded while the
Busy or Command in Progress bits are set in the
STATUS register. The INTRa line (Pin 3), if set, will
be cleared by a write to the COMMAND register.
6-582
=
0
1
0
0
1
1
3
2
1
Q 1 R3
R2
R2
M
M
0
0
R1
R1
0
0
0
0
1
1
1
0
0
1 R3
0 I
1 0
0 0
1 0\
0
RO
RO
T
T
0
0
Rate Field
For 5 M"Iz WR CLO,CK:
R3-C) = 0000 • =35
0001
0.5
0010
1.0
0011
1.5
0100
2.0
0101
2.5
0110
3.0
0111
3.5
1000
4.0
1001
4.5
1010
5.0
1011
5.5
1100
6.0
1101
6.5
1110 \
7.0
1111
7.5
·
·
·
·
··
·
·
·
·
·
·
·
T =
us
ms
ms
ms
ms
ms
ms
ms
ms .
ms
ms
ms
ms
ms
ms
ms
Retry Enable
T= 0
T = 1
Enable Retries
Disable Retries
M=
Multiple Sector Flag
M= 0
M= 1
lhInsfer 1 Sector
11'ansfer MulUple Sectors
,
I =
Interrupt Enable
I
0
I = 1
Interrupt at BDRQ time
Interrupt at end of command
210446-002
inter
82062
RESTORE COMMAND
The RESTORE command is usually used on a
power-up comdition. The actual stepping rate used
for the RESTORE is determined by the Seek Complete time. A step pulse is issued and the 82062
WDC waits for the Seek Complete (SC) line to go
active before issuing the next pulse. If after 1,024
stepping pulses the TRACK 000 line does not go
active, the WDC will set the TRACK 000 bit in the
ERROR register and terminate with an INTRQ. An
Interrupt will also occur if WR FAULT goes active or
DRDY goes inactive at any time during execution.
The rate field specified (R3-O) is stored in an internal
register for future use in commands with implied
seeks.
RESETINTRQ
ERRORS.
SET BUSY. CIP
AESETAWC
SET DIRECTION
OUT
•
STORE STEP-RATe
A flowchart of the RESTORE command is shown in
Figure 10.
PULSE iICJI
SETINTRQ
RESET BUSY.CIP
SEEK COMMAND
Since all commands feature an implied seek, the
SEEK command can be used for overlap seek operations on multiple drives. The actual stepping rate
used is taken from the. Rate Field of the command,
and is stored in an internal register for future use. If
DRDY goes inactive or WR FAULT goes active at
any time during the seek, the command is terminated and an INTRQ is generated.
The direction and number of step pulses needed is
calculated by comparing the contents of the
CYL!NDER NUMBER LOW/HIGH register pair to
the internal cylinder position register. After all steps
have been issued, the internal cylinder position register is updated and the command is terminated.
The Seek Complete (SC) line is not checked at the
beginning or end of the command.
If an implied seek was performed, the 82062 will
search until a rising edge of SC is received.
A flowchart of the SEEK command is shown in Figure 11.
READ SECTOR
The READ SECTOR command is used to transfer
one or more sectors of data from the disk to the
sector buffer. Upon receipt of the READ SECTOR
command, the 82062 WDC checks the CYLINDER
NUMBER LOW/HIGH register pair against the
internal cylinder position register to see if they are
equal. If not, the direction and number of steps
calculation is performed and a: seek takes place. If
an implied seek was performed, the WDC will.
search u·ntl1 a rising edge of SC is reqeived. The WR
FAULT and DRDY lines are monitored throughout
the command.
ISSUE"
STEP PULSE
Figure 10.
Restore Command Flow
210446-002
82062'
When the Seek Complete (SC) line is high (with or
without an implied seek having occured), the search
for an 10 field begins. If T = 0 (retries enabled), the
82062 WOC must fi nd an 10 with the correct cyli nder
number, head, sector size and CRC within 8 revolutions, or an automatic scan 10 wi!! be performed to
obtain cylinder position information, and then a
seek performed (if necessary). The search for the
proper 10 will be retried for up to 8 revolutions. If the
correct sector is still notfound, the appropriate error
bits will be set and the command terminated. Data
CRC errors will also be retried for~p to 8 revolutions
(if M =0).
If T= 1 (retries disabled), the 10 search must find the
correct sector within 2 revolutions or the appropriate error bits will be set and the command
terminated.
'
Both the READ SECTOR and WRITE SECTOR commandsfeaturea "simulated completion" to ease programmingo ORO/BORO will be generated upon detecting'
an error condition. This allows the same program
flow for successful or unsuccessful completion of a '
command.
When the data address mark is found, the WOC is
ready to transfer data to the sector buffer. After the
data has been transferred, the I bit is checked. If I = 0,
INTRO is made active coincident with BORO, indicating that a transfer of data from the buffer to the host
processor is required. If I = 1, INTRQ will occur at the
end of the command, i.e. after the buffer is unloaded,
by the host.
An optional M bit may be set for multiple sector
transfers. When M = 0, one sector is transferred and
the SECTOR COUNT-register is ignored. When M =
1, multiple sectors are transferred. After each sector
is transferred the 82062 decrements the SECTOR
COUNT register and increments the SECTOR NUMBER register. The next logical sector will be transferred regardless of any interleave. Sectors are numbered at format time by a byte inttie 10 field.
Forthe 82062 to make' multiple sector transfers to the
buffer, the BROY line must be toggled low to high for
each se,ctor. Transfers will continue until the SECTOR COUNT register equals zero, or the BROYline
goes active. If th~SEPTOR COUNT register is nonzero (indicating more sectors are to be transferred
but the buffer is full), BORO will be made active and,
the host must unload the buffer. After,thiS occurs, the
buffer,will again be fre~ to accept the remaining sectors from the WOC. ,ThiS scheme enables the user to
transfer more sectors than the buffer memory has
capacity for:
'
In summary then, READ SECTOR operation is as
follows!
"
F.lgure' 1:1.
6-584
,
Seek Command Flow'
210446-002
82062
When M = 0 (READ SECTOR)
(1)
Host
(2)
(3)
82062:
82062:
( 4)
5)
6)
7)
8)
82062:
82062:
82062
Host:
82062:
(9)
(10)
82062:
Host:
(
(
(
(
When M
Sets up parameters; issues
READ SECTOR command.
Strobes Be'R; sets BCS = O.
Finds sector specified; transfers
data to buffer.
_
Strobes BCR; sets BCS = 1,
Sets BORa =1, ORa =1.
If I bit = 1 then go to'(9).
Reads contents of sector buffer.
Waits for BRDY, thEm sets
INTRa = 1; END.
Sets INTRa 1.
Reads out contents of buffer;
END.
=
=1 (READ MULTIPLE SECTOR)
( 1)
Host
( 2)
( 3)
82062:
82062:
( 4)
82062:
( 5)
( 6)
( 7)
82062:
82062:
( 8)
Buffer:
( 9)
82062:
(10)
(11)
82062:
82062:
Host
Sets up parameters; issues
READ SECTOR command.
Strobes BCR; sets BCS O.
Finds sector specified; transfers '
data to buffer.
Decrements SECTOR COUNT
register; increments SECTOR
NUMBER begister.
Strobes B' R; sets BCS 1.
Sets BORa = 1, ORa = 1.
Reads out contents of buffer;
END.
Indicates data has been transferred byactivating'BRDY.
When BRDY 1, if Sector Count
= 0, then go to (11).
Go to (2).
Set INTRa = 1.
=
=
=
A flowchart of the READ SECTOR command is
shown in Figure 12.
WRITE SECTOR
I
The WRITE SECTOR command is used to write one
or more sectors of data to the disk from the sector
buffer. Upon receipt of WRITE'SECTOR command,
the 82062 WDC checks the CYLINDER-NUMBER
LOW/HIGH register pair against the internal cylinder
position register,to see if they are equal. If not, t~e
direction and number of steps calculation is performed and a seek takes place. The WR FAULT and
DRDY lines are checked throughout the command.
When the Seek Complete (SC) line'is found to be
tru'e (with or without an implied seek having occured), the BORa signal is made active and the host
proceeds to unload the buffer. When the 82062
senses BRDY high, the 10 field with the specified
cylinder number, head, and sector size is searched
for. Once found, WR GATE is made active and the
data is written to the disk. If retries are enabled (T =
0), and if the 10 field cannot be found within 8
revolutions, automatic scan 10 and seek commands
are performed. The 10 Not Found error bit is set and
the command is terminated if the correct 10 field is
not found within 8 additional revolutions. If retries
are disabled, (T = 1), and if the 10 field cannot be
found within 2 revolutions, the 10 Not Found error
bit is set and the command is terminated.
During a WRITE MULTIPLE SECTOR command (M
= 1), the SECTOR NUMBER register is decremented
and the SECTOR COUNT register is incremented. If
the BRDY line is low after the first sector is transferred from the buffer, the 82062 will transfer the
next sector. If BRDY is high, the 82062 will set
BORa and wait for the host processor to place more '
data in the buffer. In summary then, the WRITE
SECTOR operation is as follows:
When M = 0,1 (WRITE SECTOR)
( 1)
( 2)
( 3)
( 4)'
( 5)
( 6)
( 7)
( 8)
( 9)
(10)
Host:
Sets up parameters; issues
WRITE SECTOR command.
Strobes !reA; sets BORa = 1,
82062:
DRO= 1.
Loads sector buffer with data.
Host
82062:
Waits for BRDY = 1.
Finds specified 10 field; writes
82062:
• sector to disk.
82062:
If M = 0, then 'set
INTRa = 1; END.
82062
Increment SECTOR NUMBER
register; decrement SECTOR
COUNT register.
11 SECTOR =0, then set INTRa
82062
=1; END.
If BRDY =0, then go to (5).
82062
Goto (2).
82062
A flowchart of the WRITE SECTOR command is
shown in Figure 13.
SCANID
The SCAN 10 command is used to update the SECTOR/DRIVE/HEAD, SECTOR NUMBER, and CYL- .
INDER NUMBER LOW/HIGH registers.
After -the command is loaded, the Seek Complete
(SC) line is sampled until it is valid. The DRDY and
WR FAULT lines are also monitored throughout
execution of the command. When the first 10 field is
,"
'
, 210446-002
inter
82062
RESETINTRQ
ERRORS
SET BUSY, CIP
SEARCH
FOR 10
FIELD
NOTE'
PULSE BCR
SET INTRQ, AC
RESET BUSY, CJP
'N T bit 0 1 _
=llhen _
..... It ..loin _ , 21_. put....
Figure 12A, Read Sector Command Flow
a"586
210446-002
82082
~NO-0
NOTE'
,
Figure 128, 'Read sector Command Flow
:6-587
210446-002
82062
£[Q)W~OO©~ OOOfF@OOIMl~'jjD@OO
."
· I ' _ d l..blecl ..... _ed ..... 1.
laken filla' 2 _ . pur_.
Figure 1a. WrIte Sector Cpmmaoci Flow
6:-588
210446-002.
inter
82062
found, the 10 information is loaded into the SOH,
SECTbR ",UMBER, and CYLINDER NUMBER registers. The internal cylinder pOSition register is also
updated. If a'bad block is detected, the BAD BLOCK
bit will also be set. The CRC is checked and if an error
is found, the 82062 will retry up to 8 revolutions to find
an error-free 10 field. There is no implied seek with
this command and the sector buffer is not disturbed.
A flowch'art of the SCAN 10 command is shown in
Figure 14.
WRITE FORMAT
The WRITE FORMAT command is used to format
one track using the Task Register File and the sector
buffer. During execution of this command, the sector
buffer is used for additional parameter information
instead of sector data. Shown in Figure 15 is the
contents of the sector buffer for a 32 sector track
format with an interleave factor of two. Each sector
requires a two byte sequence. The first byte designates whether a bad block mark is to be recorded in
the sector's 10 field. An OOH is normal; an SOH indicates a bad block mark for that sector. In the example
of Figure 15, sector 04 will get a bad block mark
recorded.
The second byte indicates the logical sector number
to be recorded. This allows sectorS'to be recorded
with any interleave factor desired, The remaining
memory in the sector buffer may be fiHed with any
value; its only purpose is to generate a BROY to tell
the 82062 to begin formatting the track.
An implied seek is in effect on this command. As for
other commands, if the drive number has been
changed, an 10 field will be scanned for cylinder
position information before the implied ,seek is performed. If no 10 field can be read (because the track
had been erased or because an incomplete format
had been been used), an 10 Not FOt,lnd error will
result and the WRITE FORMAT command will be
aborted. This can be avoided by issuing RESTORE
command before formatting.
a
The SECTOR COUNT register is used to hold the
total number of sectors to be formatted (FFH = 255
sectors), while the SECTOR NUMBER register holds
the number of bytes minus three to be used for Gap 1
and Gap 3; for instance, if the SECTOR COUNT'
register value is 02H and the SECTOR NUMBER
register value is OOH, then 2 sectors are written and 3
bytes of 4EH are written for Gap 1 and Gap 3. The
data fields are filled with FFH and the CRC is automatically generated and .appended. The sector extension
bit in the SOH register should not be set. After the last
sector is written the track is filled with 4EH.
Figure 14. Scan 10 C~mmand Flow
&-589
210446-002
inter
82062
FORMAT COMMAND
SECTOR BUFFER CONJ"ENTS
SECTOR
BUFFER
ADDRESS
LOCICAL
SECTOR
NUMBER
BAD
BLOCK?
00
00
02
04
38
3A
3C
3E
40
FF
00
10
01
11
02
12 .
03
13
04
14
05
15
06
16
07
17
08
18
09
19
OA
lA
DB
1B
DC
1C
00
10
DE
lE
OF
IF
FF
00
06
00
08
OA
DC
DE
10
12
14
16
18'
lA
lC
lE
20
22
24
26
28
2A
2C
2E
30
00
00
00
FO
FF
FF
00
00
80
00
00
00
00
00
00
00
00
00
DO
00
00
00
00
00
00
00,
00
00
32
34
36
00
00
00
00
The Gap 3 value is determined by' the drive motor
speed variation, data sector length, and the interleave
factor, The interleave factor is only important when
1:1 interleave is uSed. The formula for determining the
minimum Gap 3 length value is:
Gap 3 = (2 * M * S) + K + E
M = motor speed variation (e.g., 0.03
for±.3%)
S = sector length in bytes
K = 25 for interleave factor of 1
K = 0 for any other interleave factor
E = 7 if the sector is to be extended
Like 1111 commands, a WR FAULT or drive not ready
condition will terminate execution of the WRITE
FORMAT command. Figure 16shows the format that
the 82062 will write on the disk.
A flowchart of the WRITE FORMAT command is
shown in Figure 17.
. Figure 15
DATA FIELD
----::l
USER DATA
'DFI~LD
A1 '" A1H with OAH clock
IDENT " MSB of Cylinder Number
FE '" 0·255 Cylinders
FF = 256-511 Cylinders
Fe" 512-767 Cylinders
FD" 768-1023 Cylinders
SDH BYTE" 81ts 1 1, 2 ~ Head Number
811s3.4=O
Bits 5, 6 '" Sector Size
,
Btl 7 " Bad Block Mark
Sec 1/ = Logical Sector Number
DATA FtELO
Al " A1H with OAH clock
Fa " Data Address Mark. Normal clock
USER" Data Field 128 to 1024 Bytes.
NOTES
1 GAPl and 3 length
formatting
2
Figure 16.
de~rmtned
by sector number register contents dUring
,
If EXT pIt In SOH reg'lster IS set to 1 then an additIOnal 7 data bytes are Written, ,
no CAC bytes are written
'n'ack Format
210446·002
inter
82062
YES
WG_
SET ABORTED
COMMAND BIT
PULSE BCR
SETINTRQ
RESET BUSY, C,IP
Figure 17.
Write FormatComman~ Flow
·6:"591
210446-002
82062·
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS·
.Ambient Temperature Under Bias ..• O°C to 70°C
Storage Temperature .........• -65°C to +150°C
.
Voltage on any pin with
respect to GND ...•............. -0.5V to +7V
Power Dissipation ....•.•..........•....1.5 Watt
• NOTICE: Stresses above those listed under
. "Absolute Maximum Ratings" may cause permanent damage to the device. This.is a stress rating
qnly anp fl.!nction~1 operation of thfJ deviceat these
or any other conditions above those indicated in ,
the operational sections of this specification is
not implied. Exposure to absolute maximum rating
conditions for exten.ded periods may affect device
reliability.
D.C. CHARACTERISTICS,(TA =.O°C to 70°C; VCC = +5V ± 10%; GND = OV)
SYMBOL
PARAMETER
IlL
Input Leakage Current
10
f.lA
IOFL
Output Leakage Current
10
f.lA
VIH
Input High Voltage
VIL
Input Low Voltage
VOH
Output High Voltage
. VOL
Output Low Volta~e
MIN
MAX
2.0
UNIT . TEST CONDITIONS
=Vee
Your =Vee
VIN
V
0.8
2.4
0.45
V
V
IOH
V
IOL
=100uA
=1.6mA
4.8mA P21,22,23
Icc
Supply Current
CIN
Input Capacitance
ClIO
,
250
rnA
All Outputs Open
10
pF
fc
20
pF
'1/0 Capacitance
=1 MHz
. Unmeasured pins returned
to GND
For Pins 25,34,37,39
V1H
Input High Voltage
VIL
Input Low Voltage
0.5
V
TRS
Rise Time
30
ns
4.6
V
10% to 90% points
A.C. CHARACTERISTICS (TA = O°C to 70°C; Vce = +5V ± 10%; GND = OV)
HOST READ TIMING
PARAMETER
MAX
UNIT
. ns
SYMBOL
1
Address Stable Before RDI '
2
Data Delay From RDI
375
ns
3
RD Pulse Width
0.4
10
ns
4
RD to Data Floating
20
200
ns
5
Address. Hold Time after RD!
0
ns
MIN
100
6
Read Recovery Time
300
ns
7
CS Stable before RD
0
ns
6-592
TEST CONDITIONS
--
210446-002
inter \,
82062
HOST WRITE TIMING
MIN
MAX
UNIT
0
10
0
10
0
ps
ps
ps
ps
ns
ns
ns
1.0
us
SYMBOL
PARAMETER
8
Address Stable Before
9
CS Stable Before WRI
10
Data Setup Time Before WRt
0.2
11
WR Pulse Width
0.2
12
Data Hold Time After WAt
10
13
Address Hold Time After WRt
30
14
CsHoid Time AfterWR't
15
Write Recoverv Time
wm
10 "
TEST CONDITIONS
I
BUFFER READ TIMING (WRITE SECTOR COMMAND)
MIN
SYMBOL
PARAMETER
16
AD Float to RD valid
15
17
RD Output Pulse Width
300
18
Data Setup to Rot
140
19
Data Hold from Rot
0
20
R'6' Repetition Rate
AD Float from BeSt
1.2
21
TVP
400
MAX
100
500 .
UNIT
TEST CONDITIONS
=50pF
ns
CL
ns
See Note 3
ns
1.6
2.0
100
ns
ps
ns
See Note 1
CL
=50pF
~~~--~------~,~
JID----"
(OUTPUT)
;xxx
.....----@-----.I
6-593
210446-002
82062
BUFFER WRITE TIMING (READ SECTOR COMMAND)
,
TYP
Wf!i Float to ViiR Valid
MIN
15
23
WR Output Pulse Width
300
400
24
Data Valid from WRI,
SYMBOL
22
PARAMETER'
25
Data Hold from iNAt
60'
26
iit71=i Repetition
1.2
27
WR Float from BCSt
Rate
MAX
100
UNIT
' 'ns'
500
ns
, 110
ns
2.0
100
JJs
ns
nST CONDITIONS
CL
=50pF
See Note:,3
ns
1.6
15
See Note 1
CL
=50pF
':~~=----------~' ~
(OUTPUT)
OBO-7
-------+------+-<
, ....1 ' - - - - -
@
OAT~ VALID
- - - - - , - - I..
~,
MISCELLANEOUS TIMING
SYMBOL
28
PARAMETER
BDRQ Reset from BRDY .
MIN
40
29
BRDY Pulse Width
800
30
BcR Pulse Width
1:4
1.6
1.8
31
STEP Pulse Width
8.3
8.4
8.7
32
, I~DEX Pulse Width
5000
33
REm Pulse Width
24
34
~tto~
1.6
35
REsE'i'i Jo WR, CSI
6.4
36
WR CLOCK Frequency
37
RD CLOCK Frequency
TVP
MAX
200
UNIT
'ns
TEST CONDITIONS
ns
See Note 4
JJS
JJS
See Note 1
:
See Note 1
ns
WRCLK
See Note 2
3.2
6.4
JJS
See Note 1
5.0
5.25
JJS
MHz
See Note 1
0.25
0.25
5.0
5.25
MHz
50% Duty Cycle
See Note 5
50% Duty Cycle
:~
.J
STEP~
WRCLOCK{
INDEX~
RDCLDCK{
I
; '
~
'
.(
210446-002
82062
READ DATA TIMING
MAX
UNIT
95
2000
ns
RD DATA after RD CLOCKI
0
T38/2
ns
RD DATA before RD CLOCK!
20
T38/2
ns
41
RD DATA Pulse Width
40
T38
42
DR UN PUlse Width
30
38
SYMBOL
PARAMETER
RD CLOCK Pulse Width
39
40
AD DATA
J
TYP
TEST CONDITIONS
50"10 Duty Cycle
ns
ns
t
-~~
®=:1
"''---..
AD CLOCK
MIN
t\_________-Jr-
j-----""'''. . -----/
-1=®~
DAUN
WRITE DATA TIMING
SYMBOL
PARAMETER
/
MIN
TYP
MAX
UNIT
43
WR CLOCK Pulse Width
95
2000
ns
44
Propogation Delay
WR Cl.,OCK to WR DATA
10
65
ns
45
WR CLOCK to EARLY/LATEI
10
65
ns
46
WR CLOCK to EARLY/LATE!
10
65
ns
WA DATA
TEST CONDITIONS
_-+-J
WA~LOCK
EAAU--------------------------~
6-595
r:=®
---Jl
F--_ _
219446-002
inter
'82062
:
A.C. TESTING
JN~UT,
OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
INPUT'OUTPUT
DEVICE
UNDER
TEST
1
CL=50pF
-=
AC TESTING: INPUTS ARE DRIVEN AT 24V FOR A LOGIC .1,
AND 0.45V FOR A LOGIC O. TIMING MEASUREMENTS ARE
MADE AT 20V FOR A LOGIC .1, ANDO 8V FOR A LOGIC .0
CL=50pF
CL INCLUDES JIG CAPACITANCE
NOTES:
1.
2,
3.
4.
5.
6.
Based on WR CLOCK = 5.0 MHz.
24 WR CLOCK periods = 4.8 JiS at 5,0 MHz,
2 WR qLOCK periods ± 100 ns.
BRDY must be 4 Jis or a spurious BDRQ pulse may exist for up to 4 JiS after the rising ,edge of BRDY.
WR CLOCK Frequency = RD CLOCK Frequency ± 15%.
2 WR CLOCK periods ± 50 ns.
6-596
, 210446-002
MICROPROCESSOR PERIPHERALS
UPI™ USEFJ'S MANUAL
\
APRIL 1982
6-597
CHAPTER 1
INTRODUCTION
Accompanying the introduction of microprocessors
such as the BOBO, B085, B088, and B086 there has been
a rapid proliferation of intelligent peripheral de'vic~s; '1hese special purpose peripherals extend
C~U performance and flexibility in a number of important ways.
Table 1·1. Intelligent Peripheral Devlcea
8255,(GPIO)
designed for comtnuI:1ication disciplines, parallel
I/O, keyboard encoding, interval timing, CRT control, etc. Yet, in spite of the large number of devices
available and the increased \flexibility built into
these chips, there is still a large number of microcomputer peripheral control tasks which are not
satisfIed.
Programmable Peripheral
Interface
Programmable
Communication Interface
Programmable Interval Timer
Programmable DMA Controller
With the introduction of the, Universal Peripheral
Interface (UPI) microcomputer, ~ntel has taken the
8251A (USART)
intelligent peripheral concept a step further by
providing an'intelligent controller that is fully user
programmable. It is a complete single-chip micro8253 (TIMER)
computer which can connect directly to a master
8257 (DMA)
processor data bus. It has the s~me advantages of inProgrammable Interrupt
8259
telligllnce and flexibility which previous peripheral
Controller
chips offered. In addition, the UPI is user8211;.(SQFDC), ", PrOir~mable Floppy l)~k', ' '~.:: '. " 'programmable: it has 1K bytes of ROM or EPROM
8272 (DDFDC)
ControlleJ,'S ,
,
_
memory for program storage plus 64 bytes of RAM
memory for data storage or initialization from the
8273 (SDLO)
Progr_able Synchronous
Data Link Controller
master processor. The UPI device allows a designer
to fully sPecify his control algorithm in the periphProgrammable Multiprotocol8274 '
Serial Communications
eral chip without relying on the master processor.
Controller
Devices like printer controllers and keyboard scanners can be completely self-contained, relying on the
8275/8276 (CRT)
Programmable CRT
Controllers
master processor only for data transfer.
8279 (PKD)
Progr8lI\lDabie
KeyboardlDisplay Controller
The UPI family currently consists offive components:
8291A, 8292, 8293 Programmable GPIB System
• 8741A microcomputer with 1K EPROM
Talker, Listener, Controller
memory
Intelligent. devices like the 8272 floppy disk control• B041AH microcpmputer with 1K ROM memler and 8273 synchronous data link controller (see
ory
Table 1-1) can preprocess serial data and perform
• B042 microcomputer with 2K ROM memory
control tasks which off-load the main system proces• 8243 I/O expander device
sor. Higher overall system throughout is achieved
• 8742 microcomputer with 2K EPROM
and'l\oftware complexity is greatly reduced. The inmemory
telligent peripheral chips simplify master processor
control tasks by performing many functions exterThe 8741A, 8041AH, 8742 and 8042 single chip
nally in peripheral hardware rather than internally
microcomputers are functionally equivalent except
in main processor software.
for the type and amount of program memory availIntelligent peripherals also provide system flexibility. They contain on-chip mode registers which are
programmed by the master processor during system
initialization. These control registers allow the peripheral to be confIgured into many different operation modes. The user-defined program for the,
peripheral is stored in main system memory and is
transferred to the peripheral's registers whenever a
mode change is required. Of course, this type of
fl6xibility requires software overhead in the master
systell!. which tends to limit the benefIt derived from
the peripheral chip.
In the past, intelligent peripherals were designed to
handle very specialized tasks. Separate chips were
able with each. These devices have the following
main features:
•
•
•
•
•
•
•
•
8-bit CPU
8-bit data bus interface registers
1K by 8 bit ROM or EPROl\,ll memory (2K for
8042/8742)
64 by 8 bit RAM memory (128 bytes for
8042/8742)
Interval timer/eveJlt counter
Two 8-bit TTL compatible I/O ports
Resident clock oscillator
12 MHZ operation, 1.25 p.88C instruction cycle
for B041AH, 8742, B042
INTRODUCTION
HOST
PROCESSOR
KEYBOARD
UPI-41AH,42
OAT A
BUS
~
PRINTER
CONTROL
BUS
ADDRESS
BUS
Figure 1-1.
Interfacing Peripheral. To Microcomputer Systems
HMOS processing has been applied to the UPI family to allow for additional penormance and memory
capability while reducing costs. The 8041AH, 8741A,
8042, 8742 are all pin and software compatible. This
allows growth in present designs to incorporate new
features and add additional performance. For new
designs, the additional memory and performance of
the 8042/8742 extends the UPI 'grow your own solution' concept to more complex motor control tasks,
SO-column printers and process control applications
as examples.
at any time. An interrupt to the UPI processor is
automatically generated (if enabled) when DBBIN
is loaded.
Because the UPI contains a complete microcomputer with program memory, data mem,ory, and
CPU it can function as a "Universal" controller. A
designer can program the UPI to control printers,
tape transports, or multiple serial communication
channels. The UPI can also handle off-line arithmetic processing, or any nlflIlber of other low speed control tasks.·
The 8243 device is an I/O multiplexer which allows
expansion of I/O to over 100 lines (if seven devices
are used). All three parts are fabricated with Nchannel MOS technology and require a single, 5V
supply for operation.
INTERFACE REGISTERS FOR MULTIPROCESSOR CONFIGURATIONS.
In the normal configuration, the 8041AH/8741A,
8042/8742 interfaces to the system bus, just like any
intelligent peripheral device (see Figure 1-1). The
host processor and the 8041AH/8741A, 8042/8742
form a loosely coupled mUiti~processor system, that
is, communications between the two processors are
direct. Common resources are three addressabl~ registers located physically on the 8041AH/87UA,
8042/8742. These registers are the Data.Bus' Buffer
Input (DBBIN), Data Bus Buffer Output
(DBBOUT), and Status (STATUS) registers. The
host processor may read data from DBBOUT or
write commands and data into DBBIN. The status
of DB BOUT and DBBINplus user-d-efined status is
supplied in STATUS. Tile hbiit may read STATUS
6-599
8041AH. 8042
MASK
PROGRAMMED
ROM
8141A,8742
ELECTRICALLY
PROGRAMMABLE
LIGHT ERASABLE
EPROM
FI~ure 1-2': Pin ComPatible ROM/EPROM Versions
INTRODUCT.ION
POWERFUl- 8-BIT PROCESSOR
Features for'Peripheral Control
The UPI 8-bit interval timer/event counter can be
used to generate complex timing sequences for control application!! or it can count external events such
as switch closures and position encoder pulses. Software timing loops can be simplified or eliminated by
the interval timer. If enabled, an interrupt to the
CPU will occur when the timer overflows.
The UPI contains a powerful, 8-bit CPU with as fast
as 1.25 ~sec cycle time and two single-level interrupts. Its instruction set includes, over 90 instructions for 'easy software development. ~ost
instructions are single byte and single cycle and
none are more than two bytes long. The instruction
set is optimized for bit manipulation and I/O operations. Special instructions are inCluded to allow binary or BCD arithmetic Operations, table lookup
routines, loop counters, and N -way branch routines.
The UPI I/O complement contains two TTL-compatible 8-bit bidirectionalI/O ports and two generalpurpose test inputs. Each of the 16 port lines can
.individually function as either input or output under.
softwale,control. Four of the port lines can also function as an interface for the 8243 I/O expander which
provides four additional4-bit ports that are directly,
addressable by UPI software. The 8243 expander al- lows low cost I/O expansion for large control applications while maintaining easy and efficient software
port addressing.
SPECIAL INSTRUCTION SET ,
FEATURES
• For Loop Counters:
Decrement Register and Jump if no~
zero.
• For Bit Manipulation:
AND to A (immediate data or Register)
OR to A (immediate data or Register)
XOR to A (immediate data or Register)
AND to Output Ports (Accumulator)
OR to Output Ports (Accumulator),
Jump Conditionally on any bit in A
•
•
P~3,/,-_ _",
8243
For BDC Arith~etic:
Decimal Adjust A
Swap 4-bit.Nibbles of A
Exchange lower nibbles. of A and Register .
' Rotate A left or right with or without
..
Carry
For Lookup Tables: •
Load A from Page of ROM (Address in A)
Load A from Current Page of ROM
(Address in A)
8041AH/8741A,
8042/8742
PROG ~-----I
12110 LINES'
Figure 1-4. 82431/0 Expander Interface
, PERIPHERAL
CONTROL
OFF-UNE
ARIT~METIC
PROCESSING' "
"';
Fllliure1-3. Inte!1ac..
161/0 LINES
P20
And Protocol.. 'ForMultlpr~"sor Syst.J11,8 "
6-600
INTRODUCTION
8042s can be used in an 8041AH/8741 socket. This
feature allows extensive testing with the EPROM
part, even into initial shipments to customers. Yet,
the transition to low-cost ROM is simplified to the
point of being merely a package substitution.
On-Chip Memory
The UPI's 64 (128) bytes of data memory include
dual working register banks and an 8-level program
counter stack. Switching between the reg~ster banks
allows fast response to interrupts. The stack is used
to store return addresses .and processor status upon
entering a subroutine.
PREPROGRAMMED UPI'.
The 8292, 8294, and 8295 are 8041A's that are programmed by Intel and sold as standard peripherals.
The 8292 is a GPIB controller, part of a three chip
GPIB system. The 8294 is a Data Encryption Unit
that implements the National Bureau of Standards
data encryption algorithm. The 8295 is a dot matrix
printer controller designed especially for the LRC
7040 series dot matrix impact printers. These parts
illustrate the great flexibility offered by the UPI
family.
The UPI program memory is available in· two types
to allow flexibility in moving from design to prototype to production with the same PC layout. The
8741A, 8742 device with EPROM memory is very
economical for initial system design and development. Its program memory can be electrically programmed using the Intel Universal PROM
Programmer. When changes are needed, tlie entire
program can be erased using UV lamp and
reprogrammed in about 20 minutes. This means the
8741A/8742 can be used as a single chip
"breadboard" for very complex interface and control
problems. After the 8741A/8742 is programmed it
can be tested in the actual production level PC
board and the actual functional environment.
Changes required during system debugging can be
made in the 87 41A/87 42 program much more easily
than they could be made in 11 random logic design.
The system configuration and PC layout can remain
fixed during the development process and the turn
around time between changes can be reduced to a
.
minimum.
DEVELOPMENT SUPPORT
The UPI microcomputer is fully supported by Intel
with development tools like the UPP PROM programmer already mentioned. An ICE-41A in-circuit
emulator is also available to allow UPI software and
hardware to be developed easily and quickly. The
combination of device features and Intel development support make the UPI an ideal component for
low-speed peripheral control applications.
UPI DEVELOPMENT SUPPORT
•
•
•
•
•
•
•
At any point during the development cycle, the
8741A/8742 EPROM part can be replaced with the
low cost 8041AH, 8042 respectively with factory
mask programmed memory. The transition from
system development to mass production is made
smoothly because the 8741A and 8041AH, 8742 and
8042 parts are completely pin compatible. 8742s or
6-601
8048/8041AH/8042 Assembler
Universal PROM Programmer UPP Series
ICE-41A Module
MULTI-ICE
Insite User's Library
Application Engineers
Training Courses
CHAPTER 2
FUNCTIONAL DESCRIPTION
The UPI-41AH, 4/! microco~puter is ~'intelligent
peripheral controller designed to operate. in iAPX86, 88, MCS-85, MCS-80, MCS-51 and MCS-48 systems. The UPI'S architecture, illustrated in Figure
2-1, is based on a low cost, single-chip microcom".
puter with progr~m memory, data memory, CPU,
I/O, event timer and clock oscillator in a single 40pin package. Special interface registers are included
which enable the UPI to function as a peripheral to
an 8-bit master processor.
This chapter provides a basic description of the UPI
microcomputer and its system interface registers.
Unless otherwise noted the descriptions in this sec-
I
tion apply to both the 8741A, 8742 (with UVerasable program memory) and the 8041AH, 8042 (with
factory mask programmed memory); These two devices are so similar that they can be considered identical under most circumstances. All functions
described in this chapter apply to the 8041AH; 8042,
and 8741A, 8742.
.
PIN DESCRIPTION
The 8041AH/8741A, 8042/8742 are packaged in 40pin Dual In-Line (DIP) packages. The pin configuration for both devices is shown in Figure 2-2. Figure
2-3 illustrates the UPI Logic Symbol.
,
CLOCK
1
1 1
1024 X 1;1\'2048 X 8
8-BIT CPU
PROGRAM
64 X 8,128 X 8
DATA MEMORY
MEMORY
(ROM/EPROM)
I
jI
Jl
J
11
II
8-BIT
DATA BUS
INPUT REGISTER
l'
8·81T
8-BIT
DATA BUS
STATUS
OUTPUT REGISTER
REGISTER
II
8-BIT
TIMER/ COUNTER
18
I/O LINES
II
'v
SYSTEM
INTERFACE
PERIPHERAL INTERFACE
AND
1/0 EXPANSION
Figure 2·1. UPI-41AH, 42 Single Chip Microcomputer
6-602
FUNCTIONAL DESCRIPTION
TEST 0
Vcc
XTAl1
TEST1
XTAL2
P27/0ACK
ReSeT
55
Cs
P26 /0RQ
PROGRAM
PROM
+sv GND ...........
P25 / iiiF
P24!OBF
EA
P17
iii)
P16
AO
P15
jWR
P,.
SYNC
ponT #1
PORT #2
DATA
P'3
DO
P12
Dl
P11
D2
PlO
D3
VDD
D.
PRoo
D5
P23
06
P22
D7
P21
VS5
P20
{
BUS BUFFER
INTERFACE
COf'lTROL
INTERFACE
,,~
WRITE
CONTROLI
DATA
CHIP SELECT
Figure 2-2. Pin Configuration
Figure 2-3. Logic Symbol
The following section summarizes the functions of
each UPI-41A pin. NOTE that several pins have two
or more functions which are described· in separate
paragraphs.
.
Table 2-1. Pin Description
Symbol
Pin No. Type
DO-D7
(BUS)
12-19
I/O
PlO-P I7
P20-P 27
27-34
21-24
35-38
I/O
I/O
WR
10
I
.RD
8
I
CS
6
I
AO
9
I
TEST 0,
TEST 1
1
39
I
Name and Function
Data·Bus: Three-state, bidirectional DATA BUS BUFFER lines used to interface the
UPI-41AH, 42 microcomputer to an 8-bit master system data bus.
Port 1: 8-bit, PORT 1 quasi-bidirectional I/O lines.
Port 2: 8-bit, PORT 2 quasi-bidirectional I/O lines. The lower 4 bits (P20-P23) interface directly to the 8243 I/O expander device and contain address and data information
during PORT 4-7 access. The upper 4 bits (P24-P27) can be programmed to provide
interrupt Request and DMA Handshake capability. Software control can configure P24
as Output Buffer Full (OBF) interrupt, P25 as Input Buffer Full (IBF) interrupt, P26
as DMA Request (DRQ), and P27 as DMA ACKnowledge (DACK).
Write: I/O write input which enables the master CPU to write data and command
words to the UPI-41A INPUT DATA BUS BUFFER.
Read: I/O read input which enables the master CPU to read data and status words
from the OUTPUT DATA BUS BUFFER or status register.
Chip Select: Chip select input used to select one UPI-41AH, 42 microcomputer out of
several connected to a common data bus.
Command/Data Select: Address input used by the master processor to indicate
whether byte transfer is data (AO=O) or command (AO=I).
Test Inputs: Input pins which can be directly tested using conditional branch instructions.
Frequency Reference: TEST 1 (Tl) also functions as the el(ent timer input (under
software control). TEST 0 (TO) is used during PROM programming and verification in.
the 8741A, 8742.
FUNCTioNAL DESCAIPnON'
Table 2-1. Pin Description (Continued)
Pin No. Type
Symbol
XTAL1,
,XTAL2
SYNC
Inputs: Inputs for a crystal, LC or an external timing signal to determine the internal
oscillator frequency.
Output Clock: Output signal which occurs once per UPI-41A instruction cYLie. SYNC
can be used as a strobe for external circuitry; it is also used to synchronize single step
operation.
'
External Access: External access input which allows emulation, testing and PROM/
ROM verification.
,Program: Multifunction pin used as the program pulse input during PROM programming.
I
2
3
11
0
EA
7
I
PROG
25
I/O
RESET
4
I
SS
5
I
VCC.
VnD
40
26
VSS
20
Name and Function
During I/O expander acc;:ess the PROG pin acts as an address/data strobe to the 8243.
Reset: Input,used to reset status flip-flops and to set the program counter to zero.
I
RESET is also used during PROM programming and verification.
Single Step: Single step input used in conjunction with the SYNC output to step the
program through each instruction.
Power: +5V main power supply pin.
Power: +5V during normal operation. +25V during programming operation, +21 V for
programming 8742. Low power standby pin in ROM version.
, Ground: Circuit ground potential.
The following sections provide a detailed functional
description of the UPI microcomputer. Figure 2-4 il-
lustrates the functional blocks within the UPI device.
-,
I/o
-
...TA
......
""'"'ACE
-
..
I .....
P10-
'"
-
......-
l EG 1Afl(1
AESIDIi!NT
64xa"aaX8
STA'"
ACCESS
lIeGBANkO
iii
Ci,
Ao
'/0
""".
-
'20..,
...
PORte-,
_ACE
1KX8.2Klf8
PROM AOM
'
"
PROGRAM
MeMOA,'
CRYSTAL,
lie::
POWE.
{
...sro
T"-"
..... ,
XTAU
{= ==:-':
.
VSS_GAOI.WD
SlMlY
...,.
•
• .->1
E...............
Figure 2-4. UPI-41AH, 42TM Block Diagram
6-604
-.........
FUNCTIONAL DESCRIPTION
CPU SECTION
The CPU section of the UPI-41AH, 42 microcomputer performs basic data manipulations and
controls data flow thtoughout the single chip computer via the internal8-bit data bus. The CPU section includes the following functional blocks shown
in Figure 2-4:
• Arithmetic Logic Unit (ALU)
• Instruction Decoder
• Accumulator
• Flags
Arithmetic Logic Units (ALU)
The ALU is capable of performing the following operations:
•
•
•
•
•
•
•
ADD with or without carry
AND, OR, and EXCLUSIVE OR
Increment, Decrement
Bit complement
Rotate left or right
Swap
BCD decimal adjust
storage. Each of these memory locations is directly
addressable by a 10-bit program counter. Depending
on the type of application and the number.of program changes anticipated, two types of program
memory are available:
.
•
•
8041AH, 8042 with mask programmed RO~
Memory
.
8741A, 8742 wit~ electrically programmable
EPROM Memory
/
The 8041AH and 8741A, 8042 and 8742 are iuhctionally identical parts and are completely pin compatible. The 8742 and 8042 can be used in 8041AH,
8741A sockets. The 8041AH, 8042 has ROM memory
which is mask programmed to user specification
during ·fabrication. The 8741A/8742 are electrically
programmed by the user using the Universal PROM
Programmer (UPP series) with a UPP-848 or UPP549 Personality Card. It can be erased using
ultraviolet light and reprogrammed at any time.
A program memory map is illustrated in Figure 2-5.
Memory is divided into 256 location 'pages" and
three locations are reserved. for special use:
In a typical operation data from the accumulator is
combined in the ALU with data from some other
source on the UPI-41AH, 42 internal bus (such as a
register or an I/O port). The result of an ALU operation can be transferred to the internal bus or back
to the accumulator.
PAGE?
{
.,...,
.DO7
17
{ '7
PA~E • .
'536
,.eo
{ ",.
••
PAGE. {
If an operation such as an ADD or ROTATE requires more than 8 bits, the CARRY flag is used as
an indicator. Likewise, during decimal adjust and
other BCD operations the AUXILIARY CARRY
flag can be set and acted upon. These flags are P8rt
of the Program Status Word (PSW).'
79
PAOE4
PAGE 3
{
f
.
'023
004'
8742
,8041AH,
8741A
7
87
PAOEI {
:
PAGE1 {
:
,.
11
Instruction Decoder
56
55
•
During an instruction fetch, the operation code (opcode) PQrtion of each program instruction is stored
and decOded by the instruction decoder. The decoder genera~s ou.tputs used along 'Yith various timing signals to control the functions performed in the
·ALU. Also, the instruction decoder controls the
source and destination of ALU data.
8
PAOlO
PROGRAM MEMORY
VECTORS
PROGRAM HEAE
8
•
••
•,
•
AcculRulator
The accumulator is the single most important register in the processor. It is the primary source of data
to the.ALU and is often the destination for results as
well. Data to and from the I/O ports and memory
.
normally passes through the· accumulator. .
~7-_
:!.
"
LOCATION 3-1BF
=:r~:-roRS
7
8
5
•••, •
ADDRESS'
LOCATION 0 VECTORS
RESET
_ A U HERE
PROGftAM MEYORY MAP
Figure 2-5. PrOgram Memory Map
'I,
INlERRUPT VECTQRS
Location 0
1)
The UPI-41AH, 42 microcomputer has 1024, ~048 8bit words of resident, read-only memory for program
1).605'
;
,
, Following a'RESET input to the proce&sor,.tl,l.e
next instruction is. automatically fetcjled from
location O.
.
FUNCnONAL'DE8eRIPTION
2) , ,Location 3
,An interrupt generated by an !nlNt Buffer Full
, :·(IBF) condition (when the IBF'interrupt is enabled)'Causes the next instruction ,to be fetched
from location 3.
'27
8042
USER RAM
64X'S
84
83
3)
Location 7'
A timer overflow interrupt (when enabled) will
cause the next instruction to be fetched from location 7.
Following a system RESET, program execution begins at location O. Instructions in program memory
are normally executed'sequentially. Program control
can be transferred out of the main line of code by an
input buffer full (IBF) interrupt or a timer interrupt, or when a jump or call instruction is encountered. An IBF interrupt (if enabled) will
'automatically transfer control to location 3 while a
timer intetrupt will transfer control to location 7.
All conditional JUMP instructions and the indirect
JUMP instructi~~ are limited in rang!! to the current
256-location page (that is, they alter PC bits.O-7
only). If a conditional JUMP or indirect JUMP begins in location 255 of a page, it must reference a destination on the following ·page.
Program memory can be used to' store constants as
'well as program instructions. The UPI-41AH, 42 in- ,
struction set contains an instruction (MOVP3) designed specifically, for efficient transfer of look-up
table information from page 3 of memory.
DATA MEMORY'
The UPI-41AH, 42 universal peripheral interface
has 64, 128 8-bit words of random access data memorY. This memory contains two working register
banks, an 8-level program counter stack and a
scratch pad memorY, as shown' in Figure 2.-6. The
'amount of scratch pad memory available is variable
depending on the number of addresses nested in the
stack and ,the n~ber of working registers being
used.
Addressing Data M~morY
The first e~ht locations in ~ are designated as
.working registers Ro-R7; These locations (or registers) ~an,be addressed directly by specifying a register number in the instruction.' Since these locations
are easilya~dre~d! they ~~ generally used to store
frequently accessed intermediate results. Other locations in data memory are ad~ressed indi,rectly by
using Ro or Rl to specify the desired address. Since
all RAM locations (including the eight working reg"
isters) can be adaressedby 6:bits, the tw6 most significant'bits'(6 and 7)ofthe addressing registers are
ignored.
'
USER RAM
32X8
32
3'
BANK 1
WORKING
REGISTERS
axs
-------RV--------
24
23
-------Rtr--------
I
DIRECTLY
ADDRESSABLE
WHEN BANK 1
IS SELECTED
~
'/
ADDRESSED
INDIRECTLY
8 LEVEL STACK
DR
USER RAM
THROUGH
R,CARD
IRQ' DR R,')
16 xs
s
7
BANKO
WORKING
REGISTERS
axa
-------R1--------
-------RO--------
Flgur.
~
DlREcnv
ADDRESSABLE
WHEN BANK 0
IS SELECTED
I
2·6. Data Memory Map
Working Registers
Dual banks of eight working registers are included in
the UPI-41AH, 42 data memory. Locations 0-7
make up register b~and locations 24-31 form
register bank 1. A RESE'r signal, automatically se- .
lects register bank O. When bank 0 is selecte'4"
references to Ro-R7 in UPI-41AH, 42 instructions
operate on locations 0-7 in data memory. A "select
register bank" instruction is used to select between
the banks during program execution. If the instruction SEL RBI (Select Register Bank 1) is ~xecuted,
then program references to Ro-R7 will operate' on
locations 24-31. As stated previously, registers'O and
1 in the active register bank are used as indirect addre,ss re~isters for all locations in data me~ory.
Register bank 1 is normally reserved for handling illterrupt service routines, thereby preserving the contents of the main program registers. The SEL RBI
instruction can be issued at the beginning of an interrupt service, routine. Then, ~pon return to the
main: program, lan ,RETR (return & restore status)
instructioB will automatically restore the previously
selected bank. Dunng :interrupt processing, registers
in bank 0 can be accessed indirectly using Ro' and
R~
,"
It register bank 1 is not used, re~sters 24-31, «&n still
serve as additional scratch pad memory.
FUNCTIONAL DESCRIPTION
Program Counter Stack
DATA
. RAM locations 8-23 are used as an 8-level program
counter stack. When program control is temporarily
passed from the main program to a subroutine or interrupt service routine, the lO-bit program counter
and bits 4-7 of the program status word (PSW) are
stored in two stack locations. When control is 'returned to the main program via an RETR instruction, the program counter and PSW bits 4-7 are
restored. Returning via an RET instruction does not
restore the PSW bits, however. The program counter
stack is addressed by three stack pointer bits in the
PSW (bits 0-2). Operation of the program counter
stack and the program status word is explained in
detail in the following sections.
MEMORY
LOCATION
STACK
POINTER
11 1
110
10 1
100
01 1
010
The stack allows up to eight levels of subroutin~
'nesting'; that is, a subroutine may call a second subroutine, which may call a third, etc., up to eight levels. Unused stack locations can be used as scratch
pad memory. Each unused level of subroutine nesting provides two additional RAM locations for genI
eral use.
00 1
When control is temporarily passed from the main
program to a subroutine or an interrupt routine,
however, the PC contents must be altered· to point to
the address of the desired routine. The stack is used
_ to save the current PC contents so that, at the end of
the routine, main program execution can continue.
The program counter is initialized to zero by a
RESET signal.
PROGRAM COUNTER STACK
The Program Counter Stack is composed of 16 locations in Data Memory as illustrated in Figure 2-7.
These RAM locations (8 through 23) aI'e used td
store the 10-bit program counter and 4 bits of the.
program status word.
An interrupt or CALL to a subroutine cause~ the
contents of the program counter to be stored in one
of the 8 register pairs of the program counter s,tack.
22
I
21
I
20
I
19
I
18
I
17
I
16
I
15
I
14
I
13
I
12
I
11
I
10
I
Pe(s·g)
PC(4-7)
I
PC(<>3)
LSB
Figure 2-7. Program Counter Stack
The following sections provide a detailed description of the Program Counter Stack and the Program
Status Word.
PROGRAM COUNTER
The UPI-4lAH, 42 microco!Dputer has a 10-bit program counter (PC) which can directly address any of
the 1024 locations in program memory. The program
counter always contains the address of the next instruction to be executed and is normally incremented sequentially for each instruction to be
executed when each instruction fetches occurs.
23
I
PSW(407)
000
MSS
I
A 3-bit Stack Pointer which is part of the Program
Status Word (PSW) determines the stack pair to be
used at a given time. The stack pointer is initialized·
by a RESET signal to OOH which corresponds to
RAM locations 8 and 9.
The first call or interrupt results in the program
counter and PSW contents being transferred to
RAM locations 8 and 9 in the format shown in Figure
2-7. The stack pointer is automatically incremented
by 1 to point to locations 10 and 11 in anticipation of
another CALL.
Nesting of subroutines within subroutines can continue up to 8 levels without overflowing the stack. If
overflow does occur the deepest address stored (locations 8 and 9) will be overwritten and lost since the
stack pointer overflows from 07H to OOH. Likewise,
the stack pointer will underflow from OOH to 07H.
The end ot a subroutine is signaled by a return instruction, either RET or RETR. Each instruction
will automatically decrement the Stack Pointer and
transfer the contents of the prdper RAM register
pair to the Program Counter.
PROGRAM STATUS WORD
The 8-bit program status word illustrated in Figure
2-8 is used to store general information about program execution. In addition to the 3~bit Stack
S..e07
FUNCTlO~
SAVED IN STACK
STACK POINTER
I
I
I I
cv
AC
MSB
FO
BS
S.
S,
PESCRIPTlQN
I I
So
•
Bit6
LSB
an
Figure 2-8. Program Status Word
Pointer discussed previously, the PSW includes the
following flags:
• Cy - Carry
• AC - Auxiliary Carry
• FO - Flag 0
• BS - Registet Bank Select
The Program Status Word '(PSW) is actually a collection of flip-flops lOcated throughout the machine
which are read or written as a whole. The PSW can
be loaded to or froni the accumulator by the MOV A,
PSW or MOV PSW,A instructions. The ability to
write directly to the PSW allows easy restoration of
machine status after a power-down ~uence.
The upper 4 bits of the PSW (bits 4, 5, 6, and 7) are
stored in the PC Stack With ~very subroutine CALL
or interrupt vector. Restoring the bits on a return is
optional. The bits are restored if an RETR instruction is executed, but not if an RET is executed.
PSW
•
•
•
•
as
bit .definitions are follows:
Bits 0-2 Stack Pointer Bits So, S1, S2
Bit 3
Not Used
Bit 4
Working Register Bank
0= BankO
1 = Bank 1
Bit 5
Flag 0 bit (FO)
This is a general purpose flag
which can be cleared or compleTable 2-2.
Device
Accumulator bit
Carry flag
User flag
.'
Timer flag
Test Input 0
Test Input 1
Input Buffer flag
Buffer flag
Ou~put
•
Bit 7
CONDITIONAL BRANCH LOGIC
Conditional Branch Logic in the UPI-41AH, 42 allows the status of various processor flags, inputs, and
other hardware functions to directly affect program
execution. The status is sampled in state. 3 of the
first cycle. ,
Table 2-2 lists the internal conditions which are testable and indicates the condition which will cause a
jump. In all cases, the destination ¢dress must be
within the page of program memory (256 locations)'
in which the jump instruction occurs.
OSCILLATOR AND T!MING CIRCUITS
The 8041A's internal timing generation is controlled
by a self-contained oscillator and timing circuit. A
choice of ~stal, L-C or external clock can be used to
derive the basic QScillator frequency.
The resident timing circuit consists of an oscillator,
a state counter and a cycle counter as illustrated in
Figure 2-9. Figure 2-10 shows instruction cycle
timing.
Conditional aranch instructions
Jump condlilo,n
Jump If:
Instruction Mnamonlc
Accumulator
JZ
JNZ
JBb
JC
JNC
JFO
JFl
JTF
JTO
JNTO
JTl
JNTl
JNmF
JOBF
mented an.d tested with condi~
tional jump instnictions. It may
, be useq, I
lnCI'ement' .
-
lIMA Enabled
OlIO Cleared
-
0UIpuI Enabled
EN lIMA
EN fLAGS
InsIrucIIon
ProgremCounler
Felch
InSIIUcIion
Progrem Cotmr
Felch
IncremenI
InsIrucIIon
Program COUIIIeI
,
CYCLE 2
S3
InIem!>I
DBF, iii'
0UIpuI Dell
ToP2l.ow«
0UIpuI
Dell
0UIpuI
Dell
Upd8Ie
SIeIuIRegieIer
0UIpuI
To PorI
S1ar1
Cotmr
Slop
Counlel
6-609
52
S3
S4
55
-
-
-
-
-
-
-
""'-'
Progrem Cotmr
0UIpuI
To PorI
-
Felch
_Dell
-
ProgramCOIIII8!
To Pori
-
-
Read
-
-
-
-
-
-
-
Felch
_Dell
_PorI'
P2 Lower
-
-
-
Update
Program COUIIIeI
0uIpuI
FUNOTI0NAL'DESCRIPTION
'"
r
'3
,±"~'25P~
20 pF
~ J
!
XTAL 1
a041A,H
8741A
8042
8742
-
XTAL 1
'
8041AK
1
~OpF
'"
,
8741A
8042
L
xtAL.2
Figure 2-11.
2
"
8742
3 XTAL,2,
Recommended Crystal and L-C Connections
, Cycle Counter
The output of the state counter is divided by 5 in the
cycle counter to generate It signal which defines a
machine cycle. This signal is call SYNC and is available continously on the SYNC output pin. It can be
used to synchronize external circuitry or as a general
purpose clock output.Jt is also used for synchronizing single-step.
An' external clock signal can also be used as a frequency reference to the 8741AH, 8741A, 8142 or
8042; however, the levels are not TTL compatible.
The signalIJlust be.in the 1-1~ MHz ,frequency range
and must be copne<;ted to pins XTAL 1 and XTAL,2
by bUf(e;J;'s with a suitable pull~~p resistor to gullrantee, that.a logic "1" is above 3.8 volts. Therecommended connection i~ sho~1) in Figure 2-12:
Frequency Reference
The external crystal provides high speed and accurate timing generation. A crystal frequency of 5.9904
MHz is useful for generation of standard communication frequencies by the 8041AH/8741, 8042/8742.
However, if an accurate frequency reference and
maximum processor speed are not required, an inductor and capacitor may be used in place afthe crystal as shown in Figure 2cll.
INTERVAL TIMER/EVENT COUNTER .
The 8041AH, 8042 has a resident 8-bit timer/
counter which has several software selectable modes
of operation. As an interval timer, it can generate accurate delays from 80 microseconds to 20.48 milliseconds without placing· undue burden on the,
processor. In the counter mode, external events such,
as switch closures ortacholIleter pulses can be
counted and used to direct program flow.
A recommended ral)ge of inductance and capacitance combinations is given below:
• L '" 130 ~H corresponds to 3 MHz
• L "" 45 ~H c~rresponds to 5 MHz
\ Timer Configuration
Figure 2-13 illustrates the basic timer/counter configuration. An 8~bit register is used to count pulses
from either the internal clock and prescaler or from
an'exte,rnal source. The' counter is presettable and
readable with two MOV instructions which transfer
the c6ntents, of ,the accumulator to the,co"\1nter and
vice-versa (Le. MOV.T, A and MOV A, T). The'
_counter is stopped by a RESET or STOP TCNT instruction and remains stopped until rest~ed either
as a timer (START T instruction) or as a counter
(START CNT instruction). Once started, the
counter will increme,llt to its maiimum ,count (FFH)
and overflow to zero con:tinuing its, count until
stopped by a STOPTCNT, instruction or RESET.
+5V
+5V
L-~<>-+--I XTAL 2
STANDARD TTL OR
OPEN COLLECTOR
Figure 2-12.
Recommended Connection
For External Clock Signal
The increment from maximum count to zero (overflow) results in setting the Timer Flag '(TF) and generating .an interrupt request. The state of the
overflow flag .is testable. with the conditi6nal jump
6-610
FUNCTIONAL DESCRIPTION
XTAL 1
PRESCALER
(+ 32)
XTAL2
OSCILLATOR
TIMER
EXTERNAL
INPUT
n
--l
TEST 1
I..-
a-8IT
COUNTER
COUNTER
o
STOP
Figure 2·13.
Timer Counter
instruction, JTF. The flag is reset by executing a
JTF or by a RESET signal.
input clock is derived from the SYNC signal of the
internal oscillator and the divide-by-32 prescaler.
The configuration is illustrated in Figure 2-13. Note
this instruction does not clear the timer register.
VariOl,ls delays and timing sequences between 40
ILsec and 10.24 msec can easily be generated with a
minimum of software timing loops (at 12 MHz).
The timer interrupt request is stored in a latch and
ORed with the input buffer full interrupt request.
The timer interrupt can be enabled or disabled independent of the IBF interrupt by the EN TCNTI and
DIS TCTNI instructions. If enabled, the counter
overflow will cause a subroutine call to location 7
where the timer service routine is stored. If the timer
and Input Buffer Full interrupts occur simultaneously, the IBF source will be recognized and the
call will be to location 3. Since the timer interrupt is
latched, it will remain pending until the DBBIN register has been serviced and will immediately be recognized upon return from the service routine. A
pending timer interrupt is reset by the initiation of a
timer interrupt service routine.
Times longer than 10.24 msec can be accurately
measured by accumulating multiple overflows in a
register under sQftware control. For time resolution
less than 40 ILsec, an external clock can be applied to
the TEST 1 counter input (see Event Counter
Mode). T~e minimum time resolution with an external clock is 3.75 ILsec (267 kHz at 12 MHz).
TEST 1 Event Counter Input
The TEST 1 pin is multifunctional. It is automatically initialized as a test input by a RESET signal
and can be tested using UPI-41A conditional branch
instructions.
Event Counter Mode
The STRT CNT instruction connects the TEST 1
input pin to the counter input and enables the
counter. Note this instruction does not clear the
counter. The counter is incremented on high to low
transitions of the TEST 1 input. The TEST 1 input
must remain high for a minimum of one state in order to be registered (250 ns at 12 MHz). The maximum count frequency is one count per three
instruction cycles (267 kHz at 12 MHz). There is no
'
minimum frequency limit.
In the second mode of operation, illustrated in Figure 2-13, the TEST 1 pin is used as an input to the
internal 8-bit event counter. The Start Counter
(STRT CNT) instruction controls an internal switch
which connects TEST 1 through an edge detector to
the 8-bit internal counter. Note that this instruction
does not inhibit the testing of TEST 1 via conditiona~ Jump instructions.
Timer Mode
The STRT T instruction connects the internal clock
to the c(;mnter input and enables the counter. The
In the counter Illode the TEST 1 input is sampled
once per instruction cycle.' After a high level is detected, the next occurence of a low level at TEST 1
6-611
FUNCTIONAL DESCRIPTIOM
• Input Buffer Full (IBF) interrupt
• Timer Overflow interrupt·
The IBF interrupt forces a CALL to location 3 in
program memory; a timer-overflow interrupt forces
a CALL to location 7. The IBF interrupt is enabled
by the EN I instruction and disabled by the DIS I
instruction. The timer-overflow interrupt is enabled
and disabled by the EN TNCTI and DIS TCNTI
instructions, respectively.
Figure 2-14 illustrates the internal interrupt l~
An IBF interrupt request is generated whenever WR
and CS are both low, regardless of whether inter-.
rupts are enabled. The interrupt request is cleared
upon entering the IBF service routine only. That is,
the DIS I instruction does not clear a pending IBF
interrupt.
will cause the counter to increment by one.
The event counter functions can be stopped by the
Stop Timer/Counter (STOP TCNT) instruction.
When this instruction is executed the TEST 1 pin
becomes a test input and functions as previously described.
TESTINPUTS
There are two multifunction pins designated as Test
Inputs, TEST 0 and TEST 1. In the normal mode of
operation, status of each of these lines can be directly tested using the following cQnditional Jump
instructions:
• JTO
Jump if TEST 0 = 1
• JNTO
Jump if TEST 0 = 0
• JTl
Jump if TEST 1 = 1 •
Jump if TEST 1 = 0
.
• JNTI
The test inputs are TTL compatible. An ext~rnal
logic signal connected to one of the test inputs will
be sampled at the time the appropriate conditional
jump instruction is executed. The path of program
execution will be altered depending on the state of
the external signal when sampled.
INTERRUPTS
The 8041AH/8741A, 8042/8742 has the following internal'interrupts:
;WR
Q
cs
Interrupt Timing Latency'
When the IBF interrupt is enabled and an IBF interrupt request occurs, an interrupt sequence is initiated as soon as the currently executing instruction is
compieted. The following sequence occurs:
• A CALL to location 3 is forced.
• The program counter and bits 4-7 of the Program Status Word are stored in the stack.
• The stack pointer is incremented.
IBF
INTERRUPT
REQUEST
IBF
IBF
INTERRUPT
RECOGNIZED
INTERRUPT
REQUEST
RESET
ENI
IBF
-----Is
Q
INTERRUPT
ENABLE
IBF
INTERRUPT
ENABLE
0151
REseT
TIMER
OVERFLOW
Q
=J"L=-==---ir\--___-l
TIMER
INTERRUPT
REQUEST
TIMER
INTERRUPT
RECOGNIZED
RETR EXECUTED
Q
RESET
TIMER
INTE-RRUPT
I:NABLE
DIS TeNTI
EXECUTED
RESET
Figure 2~14.
Interrupt Logic
6-612
INTERRUPT
IN PROGRESS
FUNCTIONAL DESCRIPTION
Location 3 in program memory should contain an
unconditional jump to the beginning of the IBF interrupt service routine elsewhere in program memory. At the end of the service routine, an RETR
(Return and Restore Status) instruction is used to
return control to the main program. This instruction
will restore the program counter and PSW bits 4-7,
providing automatic restoration of the previously
active register bank as well. RETR also re-enables
interrupts.
Host Interrupts And DMA
If needed"two external interrupts to the host system
can be created using the EN FLAGS instruction.
This instruction allocates two I/O lines on PORT 2
(P24 and P25)· P24 is the Output Buffer Full inter.
rupt request line to the host system; P25 is the Input
Buffer empty interrupt request line. These interrupt
outputs reflect the internal status of the OBF flag
and the IBF inverted flag. Note, these outputs may
be inhibited by writing a "0" to these pins. Reenabling interrupts is done by writing a "I" to these port
pins. Interrupts are typically enabled after power on
since the I/O ports 'are set in a "1" condition. The EN
F~AG's effect is only cancelled by a device RESET.
A timer-overflow interrupt is enabled by the EN
TCNTI instruction and disabled by the DIS TCNTI
instruction. If enabled, this interrupt occurs when
the timer/counter register overflows. A CALL to location 7 is forced and the interrupt routine proceeds
as described above.
DMA handshaking controls are available from two
pins on PORT 2 of the UPI-41A microcomputer.
These lines (P26 and P27) are enabled by the EN
DMA instruction. P26 becomes DMA request
(DRQ) and P27 becomes DMA acknowledge
(DACK). The UPI program initiates a DMA request
by writing ,a "I" toP26. The DMA controller transfers the data into the DBBIN data register using
DACK which act,s as a, chip select. The EN DMA instruction ~an only be 'cancelled b~ a chip RESET.
The interrupt service latency is the sum of current
instruction time, interrupt recognition time, and the
internal call to the interrupt vector address. The
worst case latency time for servicing an interrupt is 7
clOck cycles. Best case latency is 4 clock cycles.
Interrupt Timing .
Interrupt inputs may be enabled or disabled under
program control using EN I, DIS I, EN TCNTI and
DIS 'rCNTI instructions. Also, a RESET, input will
disable interrupts. An interrupt request must be removed before the RETR instruction is executed to
return from the service routine, otherwise the processor will re-enter the service routine immediately.
Thus, the WR and CS inputs shO\lI9. not be held low
longer than the duration of the interrupt service
routine.
The interrupt sysiem is single level. Oo<;e an interrupt is detected, all further interrupt requests are
latched but are not acted upon until execution of an
RETR instruction re-enables the interrupt input
10gic:This occurs at the beginning of the second cycle ofthe RETR instruction. If an IBF interrupt,and
a timer-overflow interrupt occur simultaneously, the
IBF interrupt will be recognized first and the timeroverflow interrupt will remain pending until the end
of the interrupt service'routine.
Ex~ernal Interrupts
An external interrupt cal). be created using the UPI41AlL 42 timer/counter in the event counter mode
The counter is first preset to ,FFH and the EN
TCNTI instruction is executed. A timer-overflow in
terrupt is generated by the first high to low transi·
tion of the TEST 1 input pin. Also, if an IBF
interrupt occurs during servicing of the
iimer/counter interrupt, it will remain pending until
the end of the service routine.
RESET
The RESET input provides a means for 'internal
initialization of the processor.' An automatic
initialization pulse can be generated at power-on by
simply connecting a 1 !Lfd capacitor between the
RESET input and ground as shown in Figure 2-15. It
has an internal pull-up resistor to charge the capacitor and a Schmitt-trigger circuit to generate a clean
trmsition. A2~stlige sychronizer has been added to
support'reliabie operation up to 12 MHz.
If automatic initialization is used, RESET should be
held low for at least 10 milliseconds to allow the
power supply to stabilize. If an external RESET signal is used, RESET may be held low for a minimum
of 8 instruction cycles. Figure 2-15 illustrates a con-
figuration using an external TTL gate to generate
the RESET input. This configuratiQn can be used to
derive the RESET signal from the 8224 clock generator in an 8080 system.
The RESET input performs the following functions:
• Disables Interr,upts
• Clears Program Counter to Zero
• Clears Stack P~inter: '
• Clears Status Register and Flags
• Clears Timer and Timer Flag
• Stops Timer
• Selects Register Bank ,0
• ':SMs PORTS 1 and. 2 to Input Mode
6-613
FUNCTIONAL DESCRIPTION
I,
8041AH
8741A
EXTERNAL
8042
8742
RESET
SIGNAL
OPEN COLLECTOR
Figure 2-15.
External Reaet Configuration
DATA BUS BUFFER
Two 8-bit data bus ~iIffer reg~sters, DBBIN and
DBBOUT, setve as temporary buffEirs for commands
and data flowing between it and the mast~r processor. Externally, data is transmit,ted or received by
the Dim registers upon ~xecution of an INput or
OUTput instruction by the master processor. Four
control signals are used:
• AO
•
CS
•
'.
RD
WR
tween the DBB and the UPI accumulator is under
software control and is completely asynchronous to
the external processor timing. This allows the UPI
software to handle peripheral control tasks independent of the main processor while still maintaining. a
data interface with the master system.
Configuration
Figure 2-16 illustrates the internal configuration of
the DBB registers. Data is stored in two 8-bit buffer
registers, DBBIN and DBBOUT. DBBIN and
DBBOUT may be accesse~ the external processor
using the WR line and the RD line, respectively. The
data bus is a bidirectional, three-state bus which can
be connected directly to an 8-bit microprocessor system. Four control lines (WR, RD, CS, Ao) are used
by the external proce!!sor to transfer data to and
from the DBBIN and DBBOUT registers.
Address input signifYIng control or
'
data
~hip Select
Read strobe
Write strobe
Transfer can i>e implemented with or,without UPI
program interference by enabling or disabling an internal UPI interrupt. Internally, data transfer be-
Wi!
CONTROL'
BUS
iii)
cs
Ao
SYSTEM
INTERFACE
UPI-41AH,42
BUS CONTENTS DURING
ST7
ST6
07
06
I
DATA
~TATUS RE'AD
STs
51-4
F1
05
D4
D3
I
F/l
02
r
,1BF
ri1
I
BUS
QIIF
DO
2,16. '~ta Bus Buffer Configuration
6-614
(e)
FUNCTIONAL DESCRIPTION
SYSTEM,INTERFACE
An, 8-bit register containing status flags is used to
indicate the status of the DBB registers. The eight
status flags are defined as follows:
•
•
OBF Output Buffer Full This flag is automatically set when the UPI-Microcomputer
loads the DBBOUT register and is cleared when
the master processor reads the data register.
IBF Input Buffer Full This flag is set when
the ,master processor writes a character to the
DBBIN register andJs cleared when the UPI INputs the data register contents to its accumulatOI:'.
•
•
•
Figure 2-17 illustrates how an UPI-Microcomputer
can be connected to a standard 8OSO-type bus sysc
tem. Data lines DO-D7 form a three-state
bidirectio~al port which can be connected directly t~
the system data bus. The UPI bus interface has sufficient drive capability (400 pA) for small systems,
however, a larger system may require buffers. ",
Four control signals are required to handle the data
and status information transfer:
• WR I/O WRITE signal used to transfer data
from the system bus to the UPI DBBIN
register and set the Fl flag in the status
register.,
'
• RD I/O READ signal used to transfer data
from the DBBOUT'register or status
register to the system data bus.
• CS CHIP, SELECT signal used to enable
one 8041A out of several connected to a
common bus.
• Ao Address input used to select either the
8-bit status register or DBBOUT register during an I/O READ.
Also; 'the signal is used to set the Fl flag
in the status register during an I/O
WRITE.
'
'
FO This is a general purpose flag which can be
cleared or toggled under UPLsoftware control.
The flag is used to transfer UPI status'information to the master processor.
Fl CommandlD~ta This flag is'set to the condition of the Ao input line when the master processor writes a character to the1iata register. The
F1 flag can also be cleared or toggled under UPIMicrocomputer program control.
ST4 Thro1J,ghST7 These bits are user defined
status bits. They are defmed by the MOY' STS A
'
,
instruction.
All flags in the status register are automatically
cleared by a RESET input.
~
~
AODRESS BUS "
AO
a·BIT
SYSTEM
BUS
A1
-~
I
iOR
lOw
RESET
CONTROL BUS
c..
DATA BUS
~
2
).
~.,
Do-D7
470
V
8
AO
CS
WR
AD
RESET
t
XTAL 1
XTAt 2
TEST,1
TEST 0
+5V
470
+5V
8041A/8741A
,-
PORT 1
PORT 2
l"'
•
8
'v
'v
I
PERIPHERAL INTERFACE
Figure 2·17. Inter1ace to 8080 System Bus
6-615
"
FUNC'li'KM'Al DESCWlPTION
t
The WR and RD signals are8ctiviiilow aDcfare stand,ard MCS,~ periphefal contr~1 signals used to SYn'clvo~ize datil transferbetweliln ,the ,!lystem bqs lind
peripheral devices.
The CS and Ao,~i~als are !J,ecoded f~9~ the address
bvs,of the master syste~., In a system with.few I/O
'devices a linear addressing confIguration can be used.
where AO' and Al lines are connected directly to AO
and es inputs (see Figure '2.1;7).
Data Read
Table 2-'4 illustrates the relative'timing of a
DBBOUT Read. When es, Ao,"and RD are low, the
contents of the DBBOUT register is placed on the
three-state'Data lines DO~D1 and the OBF flag is
cleared.
The master processor uses es, 'A.o, WR, and RD to
control data transfer between the DBBOUT register
and the master system. The following operations are
'under master processo~ control:' '
,
, .,Table 2-4.
cs
RD WR
0
0
0
0
0
0
1
x
1 ,
1
1
1
0
0
x
Ao
0
1
0
1
x
D~ta
,
Tr.,..fer Control.
Read DBBOUT register
Read STATUS register
Write DBBIN.data register
Write DBBIN comm!lnd register
DisableDBB
Status Read
Table 2-4 shows the logic sequence re
.N"
can individually function as either inputs otlmtputs
Under software conttoL In addition, the lowei" lines
of PORT 2 can be used to interface to an' 8243 I/O
expander device to inc~ase I/O capacity to 28- Qr
m!)re lines. The adeJitionallines' are grouped,as '4-bit
.poiis:
. PORTS 4, 5, 6, ,and 7.
"
PORTS 1 and 2,
POltTS 1 and 2 are' each 8 bits wide and have the
sSme I/O characteristics. Data written to these ports
by an OUTL Pp,A'instruction is latched and remains unchanged until it is rewritten. Input data is
sampled at the 'time the IN, A,Pp instruction is exe()uted. Therefore, input data must be present ilt the
PORT until read by an iNput instruction: PORT 1
and 2 inputs are fully TTL compatible and outputs
wilf drive one standard TTL load.
' ,
Circuit Configuration
The PORT 1 and 2 lines b,ave a special 'output structure (shpwn in Figure 2-1~) that IilIC;>wS'each line to
serve as an input, an output, or both, even though
outputs are statically latched.
"
Each iine has a permanent high impedance pull-up
(50KO) which is sufficient to provide source current
for a TTL high level, yet c~ be pulled low by a st,andard TTL gate drive. Whenever a "1" is written to a
line, a low impedance pull-up (5K) is switched in
momentarily (500 ris) to provide a fast transition
from 0 to 1. When a "0" is written to the line, a low
impedance pull-down (300n) is active to provide
TTL current sinking capability. '
To use a particular PORT pin as an input, a logic "1"
must fir~t be written to that pin.
NOTE: A RESET intializes all PORT pins to the
high impedance logic "1" state.
An external TTL device connected to the pin has
sufficient current sinking capability to pull-down
the pin to the low state. An IN A,Pp instruction will
.. sample the status ,of PORT pin and will input the
proper logic level. With no external input connected,
the IN A,Pp instruction inpu~s the previous output
status.
This structure $llows input and output information
on the same pin and also allows any mix of input and
output lines on the same port. However, when inputs
and outputs are'mixed on one PORT, a PORT write
will cause the stro~ internal pull-ups to turn on at
all inputs. If a switch or other low impedance device
is connected to an input, 'aPORT write ("1" to' an
input) could caliise current limits on internal lines to
6-616
FUNCTIONAL DESCRIPTION
-
INTERNAL
Figure 2-18.
be exceeded. Figure 2-19 illustrates the recommended connection when inputs and outputs are
mixed on one PORT.
The bidirectional port structure in combination with
the UPI-41AH, 42 logical AND and OR instructions
provides an efficient means for handling single line
inputs and outputs within an 8-bit processor.
The lower half of PORT 2 provides an interface to'
the 8243 as illustrated in Figure 2-20. The PROG pin
is used as a.strobe to clock address and data information via the PORT 2 interface. The extra 16 I/O lines
are referred to in UPI software as PORTS 4, 5, 6, and
7. Each PORT can be directly addressed and can be
ANDed and ORed with an immediate data mask.
Data can be moved directly to the accumulator from
the expander PORTS (or vice-versa).
PORTS 4, 5, 6, and 7
By using an 8243 I/O expander, 16 additional I/O
lines can be connected to the UPI-41AH, 42 and directly addressed as 4-bit I/O ports using UPI.41AH,
42 instructions. This feature saves program space
and design time, and improves the bit handling ca·
pability of the UPI-41AH, 42.
.
PORT 1,2
The 8243 I/O ports,. PORTS 4, 5, 6, and 7, p~vi4e
more drive capability than the UPI-41AH, 42
bidirectional ports. The 8243 output ·is capable of
driving about 5 standard TTL loads.
. ".
~'--1'
8041AH
8741A
.
1K
PORT 1,21-JW_-o
.=
8041AH
8741,\
.
8042
8742
':'
'
RECOIIIIEIIDED
WHEN
_
AND OUTPUTS
INCORRECT UNLESS
ALL UIES ON 1ME
PORTARE_
Figure 2-19.
---,'':'
ME MIXED ON A PORT
.R~,PORT
~7
Input Connecti0n8
FUNcnONAL DESCRIPTION
~,CHIP SELECT CONNeCTION IF MORE
":"
CS
1/0
12
,THAN ONE EXPANDER IS USED
P4- PORT 4
TEST
INPUTS
2
8041AH
8042
8742
4
> 1/0
P6'-PORT6
4
1/0
P7- PORT 7
4
> 1/0
OO~D3
PROG
PROO
\
/
-<
4
8243
P20-P23
P20"P23
1/0
P5- PORT 5
8741A
PROG
4
,
81T80,1
,
oo}
01
10
X
BITS 2,3
PORT
'ADDRESS
11
DATA (4-81T8)
ADDRESS (4-8IT8)
Figure 2~20.
~
01
10
READ
WRITE
OR
11
AND
>
8243 Expander Interface
Multiple 8243's can be connected to the PORT 2 interface. In normal operation, only one of the 8243's
would be active at the time an Input or Output command is executed. The upper half of PORT 2 is used
to provide chip select signals to the 8243's. Figure 221 shows how four 8243's could be connected. Soft- '
ware is needed to select and set the proper PORT 2
pin before an INPUT or OUTPUT command to
PORTS 4-7 is executed. In general, the software
overhead required is very minor compared to the
added flexibility of having a large number of I/O
pins available.
8041AH
°tJ: "_--"-_/I DBa 8:~~A
8742
CO:~~OL
<:3:=)1 CONTRO~ORT ,I(:::::i:::::>
p~~
-+____________
__________
~
____________
FIgUre 2-21. ' Multiple 8243 Expansion
~
__________- - J
CHAPTER 3
INSTRUCTION SET
chine status accordingly and provide a means of restoring status after an interrupt or of altering the
stack pointer if necessary.
The UPI-41AH, 42 Instruction Set is opcode-compatible with the MCS-48 set except for the elimination of external program and data memory
instructions and the addition of the data bus buffer
instructions. It is very straightforward and efficient
in its use of program memory. All instructions are
either 1 or 2 bytes in length (over 70% are only 1
byte long) and over half of the instructions execute
in one machine cycle. The remainder require only
two cycles and include Branch, Immediate, and I/O
operations.
Accumulator Operations
Immediate data, data memory, or the working registers can be added (with or without carry) to the accumulator. These sources can also be ANDed, ORed,
or exclusive ORed to the accumulator. Data may be
moved to or from the accumulator and working registers or data memory. The two values can also be
exchanged in a single operatiQn.
The UPI-41AH, 42 Instruction Set efficiently handles the single-bit operations required in control applications. Special instructions allow port bits to be
set or cleared individually. Also, any accumulator bit
can be directly tested via conditional branch instructions. Additional instructions are included to
simplify loop counters, table look-up routines and
N-way branch routines.
The lower 4 bits of the accumulator can ,be exchanged with the lower 4 bits of any of the internal
RAM locations. This operation, along with an instruction which swaps the upper and lower 4-bit
halves of the accumulator, provides easy handling of
BCD numbers and other 4-bit quantities. To facilitate BCD arithmetic a Decimal Adjust instruction is
also included. This instruction is used to correct the
result of the binary addition of two 2-digit BCD
numbers. Performing a decimal adju~t on ~he result
in the accumulator produces the desired BCD result.
The UPI-41AH, 42 Microcomputer handles
arithmetic operations in both binary and BCD for
efficient interface to peripherals such as keyboards
and displays.
The accumulator can be incremented, decremented,
cleared, or complemented and can be rotated left or
right 1 bit at a time with or without carry.
The instruction set can be divided into the following
groups:
• Data Moves
• Accumulator Operations
.' Flags
• Register Operations
• Branch Instructions
• Control
• Timer Operations
• Subroutines
• Input/Output Instructions
Data Moves
(See Instruction Summary)
The 8-bit accumulator is the control point for all
data transfers within the UPI-41AH, 42. Data can be
transferred between the 8 registers of each yvorking
register bank and the accumulator directly (Le., with
a source or destination register specified by 3'bits in
the instruction). The remaining locations, i'n the
RAM array are addressed either by'Ro or Rl of the
active register bank. Transfers to and from RAM require one cycle.
Constants stored in Program Memory can be loaded
directly into the accumulator or the ,eight working
registers. Data can also be transferred directly· between the accum:l~lator and the. o.n-bo~rd timer/
counter, the Status Register (STS), or the Program
Status Word {PSW). Transfers to the STS register
alter bits 4-7 only. Transfers to the PSW alter ma-
A .subtract operation can be easily implemented in
UPI-41AH, 42 software using three single-byte,
single-cycle instructions. A value can be subtracted
from the accumulator by using the following instructions:
.
• Complement the accumulator
• Add the value to the accumulatpr
• Complement the accumulator
Flags.
There are four user accessible flags:
~. Carry
• Auxiliary Carry
• FO
.• Fl
The Carry flag indicates overfl~w ol the accumulator, while the Auxiliary Carry flag indicates overflow
between BCD digits and is used during decimal adjust operations~ Both Carry and Auxiliary Carry are
part of the Program. Status Word (PSW) and are
stored in the stack during subroutine calls. The FO
.and F~ flags are general-purpose flags which can be
<:leared or c<;>mplemented by UP!. instructions. FO is
accessible via the Program Status Word and is
~tor~d in the stack with the Ca,rry.fl,ags. Fl reflects
the condition of the AD line, and caution must be
used when setting or clearing it.
6-619
INSTRUCOON SET
, , ~
Register Operations'
The working registers can be,accessed via the accumulatGr as explained ~bove, or they can be loaded
, with immediate data constants from program memory. In addition, they can be incremented or
decremented directly, or they can be used as loop
counters as explained in the section on branch
instructions.
Additional Data Memory lOOatio~ can be accessed
with indirect instructions via Ro and Rl.
\ Branch Instructions
The UPI-41~, 42 Instruction Set includes 17 jump
instructioas. The unconditional jump instruction allows ju~ps anywhere in the lK words of program
memory. All otlllllr jump instructions are limited to
the ~nt page (256 words) of program memory.
Conditional jump instructions' can test the following
inputs and machine flags:
" '
• 'TEST 0 input pin
• TEST 1 input pin
• Input Buffer Full flag
• Output Buffer Full flag
• Timer flag
• Accumulator zero
• Accuinulator bit
• Carry flag'
• FO flag
• ;I"1 flag
The conditions tested by these instructions are the
instantaneous values at the time the conditional
jump instruction is executed. For instance, the jump
on accumulator zero instruction 'tests the accumulator itself, not an intermediate flag.
•
The decrement register and jump if not zero (DJNZ)
instruction combines decrement and broch operations in a single instruction which is useful in implementing a loop counter. This instruction can
designate any of the 8 working registers as acounter
and can effect a branch to any address within the
current page of executio~.
A special indirect jump instruction (JMPP @A)'allows the 'program to be vectored to any one of several
different locations based on the contents of the accumulator. The contents of the accumulator point to a
location in progriun' memory which 'contains the
jump address. As an exampli!, this instruction coUld
be used to vector 1X> 'anyone of several routines based
on an ASCII clWacter which has been loaded into
the accumulator. In this Yiay, ASCII inputs can be
..
used to initiate various routines. .
Control
The UPI-41o'\H, 42 Instruction Set has six instructions,for control of the DMA, interrupts, and selec- '
tion of working register banlm.
TheUPI-41AH, 4!z, provides two i~struciions for
control of the external microcomputer system. IBF
and OBF flags can be'routed to PORT 2 allowmg interrupts of the external processor. DMA
h8ndshaking 's~ can ~ be enabled uSing lines
fromPORT~.
The IBf interrupt can be enabled and disabled
using two instructions. Also, the interrupt is automatically disabled following a RESET input or during an interrupt service routine.
The working register bank switch instruptions 8.llow
the programmer to immediately substitute a second
8 register hank for the one in use. This effectively
provides either 16 working registers or the means for
quickly saving the contents of the first 8 registers in
response to an interrupt. The user has the option of
switching register .bapks when an interrupt occurs.
However, if the banks are switched" the original
bank will automatically be restored upop execution
of a return and restore status (RETRj instruction at
the end of the interrupt service routine.
Timer
The 8-bit on-board timer/counter can be loaded or .
read via the accumulator while the counter is
stopped or while counting.
The counter can be started as a timer with an internal clock source or as an event counter or,timer with
an external clock applied to the TEST 1 pin. The
instruction executed determines which clock source
is used. A single instruction stops the counter
whether it is operating with an internal or an external clock source. In addition, two instllUctions allOw
the timer interrupt.tobe ,enabled or disabled.
Subroutines
,
,
,
Subroutines are. entered by executing a call instruction. ,Calls can be made to any address in the lK
word program memory. Two separate return
instructions determine whether pr not ~tatus' (i.e.,
the upper 4 bits of the PSW) is restored upon return
from a subroutine.
'
Input/OUtput Instructions
Two 8-bit data bu's blifferregisters (DBBIN and
DBBOuT) and an 8-bit status register (STS) enable
the UPI-4lA UDive~ peripheraI interface to communicate with ,the ~xtemaI microcomputer system.
'Data can be INputted from the DBBIN register to
INSTRUCTION SET
the accumulator. Data can be OUTputted from the
accumulator to the DBBOUT register.
The STS register con~ four user-definable bits
(ST4-ST7) plus four reserved status bits (IBF, OBF,
FO, and Fl). The user-defmable bits are set from the
accumulator.
The UPI-41AH, 42 peripheral interface has two Sbit static I/O ports which can be loaded to and from
the accumulator. Outputs are statically latched but
inputs to the ports are sampled at the time an IN
instruction is executed. In addition, immediate data
from program memory can be ANDed and ORed directly to PORTS 1 and 2 with the result remaining
on the port. This allows "masks" stored in program
memory to be used to set or reset individual bits on
the I/O ports. PORTS 1 and 2 are configured to allow input on a given pin by fll'Bt writing a "1" to the'
pin.
INSTRUCTION SET DESCRIPTION
The following section provides a detailed description of each UPI instruction and illustrates how the
instructions are used.
For further information about programming the
UPI, consult the 8048/8041A' Assembly Language
Manual.
Table 3-1.
Mnemonic
Accumulator
A,Rr
ADD
ADD
A,@Rr
ADD
A,#data
A,Rr
ADDC
A,@Rr
ADDC
A,#data
ADDC
A,Rr
ANL
A,@Rr
ANL
A,#data
ANL
ORL
A,Rr
A,@Rr
ORL
ORL
A,#data
XRL
A,Rr
A,@Rr
XRL
XRL
A,#data
INC
A
, DEC
A
CLR
A
CPL
A
DA
A
SWAP
A
RL
A
RLC
A
RR
A
RRC
A
Symbols end AbbrevIatIona UMcI
Symbol
DeflnHlon
Accumulator
Carry
Data Bus Buffer Input
Data Bus Buffer OutyDt
FLAG 0, FLAG 1 (C flag)
Interrupt
Mnemonic for "in-page" operation
Program Counter
Port designator (p ... 1,2, or 4-7)
Program Status Word
Register designator (r = 0-7)
A
C
DBBIN
DBBOUT
FO,FI
I
P
PC
Pp
PSW
Four additional4-bit ports are available through the
82431/0 expander device. The 8243 interfaces to the
UPI-41AH, 42 peripheral interface via four PORT 2
lines which form an expander bus. The 8243 ports
have their own AND and OR instructions like the
on-board ports, as well as move instructions to transfer data in or out. The expander AND or OR instructions, however, combine the contents of the
accumulator with th~ selected port rather than with
immediate data as is done with the on-board ports.
Table 3-2.
'
Rr
\
StackPoin~
SP·
STS
T
TF
TO,TI
#
@
,
,
Status register
':rimer
Timer Flag
TEST 0, TEST 1
Immediate data prefix
Indirect address prefIX
Double parentheses show the effect of@,
thatis, @ROis shown as «RO».
Contents of
«)
()
Instruction Set Summ.-y
Byt..
Operation Description
Add register to A
Add data memory to A
Add immediate to A
Add register to A with carry
Add data memory to A with carry
Add immediate to A with carry
And register to A
And data memory to A
' And immediate to A
Or register to A
Or data memory to A
Or immediate to A
Exclusive Or register to A
Exclusive Or data memory to A
Exclusive Or immediate to A
IncrementA
Decrement A
Clear A
Complement A
Decimal Adjust A
Swap nibbles of A
Rotate A left
Rotate A left through carry
Rotate A right
Rotate A right through carry
·6-621
1
I
I
1
2
1
2
1
1
1
2
2
1
1
1
2
1
1
2
,1
1
2
1
1
1
1
1
1
1
1
1
1
1
2
1
1
2
1
1
2
1
1
1
1
1
,
1
1
,
,
eycl..
1
1
1
INSTRUCOON SET
Tabl. 3-2.'1netructIon Set Summary (Con't.) .
M~emonle
INPUT/OUTPUT
A,Pp
IN
Pp,A
OUTL
' Pp,#data
ANL
ORL
Pp,#data
A,DBB
IN
OUT
DBB,A
MOV ,
STS,A
A,Pp
MOVD
Pp,A
MOVD
Pp,A
ANLD
ORLD
Pp,A
.
OpfttIOn De8crlptlon
Input port to A
Output A to port
And immediate to port
Or immediate to port
Input DBB to 'A, clear mF
Output A to DBB, Set OBF
A4-A7 to bits 4-7 ofstatus
Input Expander port to A
Output A to Expander port
And A to Expander port
Or A,to Expander port
Bytee
Cyel..
1
1
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
2
DATA MOVES
Move register to A '
MOV
A,Rr
MOV
A,@Rr
Move data m,emory to A
MOV
A,#data
Move immediate to A
MOV
Rr,A
Move A to register
MOV
@Rr,A
Move ~ to data memory
MOV
Rr,#data
Move immediate to register
MOV
@Rr,#data
Move immediate to data memory
MOV
A,PSW
MovePSWtoA
MOV
PSW,A
MoveAtoPSW
, , Exchange A and registers
A,Rr
XCH
XCH
A,@Rr
Exchange A and data memory
XCHD
A,@Rr
Exchange digit of A and register
A,@A
Move to A from current page
MOVP
MOVP3
A;@A
Move to A from Page 3
TIMER/COUNTER
"
A,T
Read ,Timer/Counter
MOV
T,A
MOV
LOad Timer/Counter
STRT
T
Start Timer
STRT
CNT
Start Counter
STOP
TeNT
Stop Timer/Counter
EN
TeNT!
Enable Timer/Counter Interrupt
DIS
TeNTI
Disable Timer/Counter Interrupt
CONTROL
EN
DMA
Enable DMA Handshake Lines
'I
EN
Enable mF interrupt
DIS
I
Disable mF interrupt
EN
FLAGS
Enable Master Interrupts
Select
register bank ()' ,
SEL
RBO
SEL
RBI
Select register bank 1
No Operation
NOP
REGISTERS
INC
Increment register
Rr
@Rr
Increment data memory
INC
DEC
Decrement register
Rr
SUBROUTINE
addr
Jump to subroutine
CALL
RET
Return
RETR
Return and restore status
FLAGS
Clear Carry
CLRC
CPLC
Complement Carry
CLRFO
Clear Flag 0
CPLFO
Complement Flag 0
CLRFI
Clear Fl Flag
CPLFI
' Complement Fl Flag
1
1
2
1
1
2
-
1
1
2
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1 '
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
-
1
2
'
,
1
1
1
1
1
1
1
.
1
"
2'
2
2
1
1
I'
1
1
1
INSTRUCTION SET
Instruction Set SUmmary (Con't.)
Table 3·2.
Operation Description
Mnemonic
Bytes
Cycles
2
2
2'
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BRANCH
JMP
JMPP
DJNZ
JC
JNC
JZ
JNZ
JTO
JNTO
JTl
JNTl
JFO
JFl
JTF
JNIBF
JOBF
JBb
addr
@A
Rr,addr
addr
addr
addr
addr
addr
addr
addr
addr
addr
addr
addr
addr
addr
addr
Jump unconditional
Jump indirect
Decrement register and jump on non-zero
Jump on Carry=1
Jump on Carry-O
Jump on A Zero
Jump on A not Zero
Jump on TO=l
Jump on TO=O
Jump on Tl=l
Jump on Tl=O
Jump on FO Flag... l
Jump on Fl Flag"'l
Jump on Timer Flag=l
Jump on IBF Flag=O
Jump on OBF Flag=l
Jump on Accum.ulator Bit
1
2
2
2
2
2
2
2
2
2
2
2
2
21
2
2
i
ALPHABETIC LISTING
ADD A,Rr Add Register Contents to Accumulator
Opcode:
1.. .10____°..J.1_1_r2_r_1_r--'0I
The contents of register 'r' are added to the accumulator. Carry is affected.
(A) - (A) + (Rr)
r=0-7
Example:
ADDREG: ADD A,RS
ADD A,@Rr
Add Data Memory Contents to Accumulator
Opcode:
;ADD REG S CONTENTS
;TOACC
1.. .10_ _ _0~1o_o_o_r--ll
The contents of the standard data memory location addressed by register 'r' bits 0-5 are added to the
accumulator. Carry is affected.
(A) - (A) + «Rr»
. r=0-1
Example:
ADDM: MOV RO,#47
ADDA,@RO
;MOVE 47 DECIMAL TO REG
;ADD VALUE OF LOCATION
;47 TOACC
°
ADD A,#data Add Immediate Data to Accumulator
Opcode:
10 ° ~ 010 °
This is a 2-cycle instruction. The specified data is added to the. accumulator. Carry is affected.
(A) - (A) + data
Example:
ADOID: ADD A,#ADDER
;ADD VALUE OF SYMBOL
;'ADDER' TO ACC
6-623
INSTR,",CTI()N SET
ADDC A,Ar
Opcode:
Example:
Add c.ry end Regia. pontenta to Accumulator
I 0 ,1
1
1
'1
1 r2 r1
ro I
The content of the carry bit Is added to accumulator location O. The contents of register 'r' are then added to
the accumulator. Carry Ia affected.
'
W - W + (Rr) + (C)
r=0-7
ADDRGC: ADDC A,R4
;ADDCAARY AND REG 4
;CONTENTS TO Ace
ADDC A,,,,, Add Carry and Data Memory Contents to AcCumulator
Opcode:
101111000
rl
The content of the carry bit is added to accumulator location O. Then the contents of the standard data
memory location addressed by register 'r' bits o-S are added to the accumulator. Carry is affected.
Example:
«Ar»
W,- W +
+ (C)
ADDMC: MOV R1,#4O
ADDC A,@R1
ADDC A,#data
Opcode:
10
r=0-1
;MOV '40' DEC TO REG 1
;ADD CARRY AND LOCATION 40
;CONTENTS TO Ace
Add Carry and Immediate Data to Accumulator
0
0
1 10
0
1
1 I . Id7
de
dS d41 d3 d2 d1 dO I
~
Example:
ANL A,Ar
Opcode:
Example:
A!"Il A.@Rr
a~ to accumulator location O. Then til8:
This is a 2-cycle instruction. The
of the 'carry bit is
specified data Is added to the accumulator. Carry Is affected.
W - W + data + (C)
ADDC A,#255
;ADD CARRY AND '22S' DEC
;TOAce
Logical AND Accumulator WHh Reglater Mask
I0
1
0
1 11
r2 r1
rO I
Data In the accumulator Is logically ANDed with the mask contained in working register 'r'.
W - WAND (Rr)
r=0-7'
,
ANDREG: ANL A,R3
;'AND' Ace CONTENTS WITH MASK
;MASK IN REG 3
logical AND Accumulator WHh Memory Mask
Opcode:
Data in the aecumui8tor is logically ANDed with the mask contained in the data memory location referenced
by register 'r', bits O-S.
'
..... W - (A) AND
r=,0-1
(
Example:
ANDDM: MOV RO,#OFFH
;MOVE 'FF' HEX TO REG 0
ANL A,#OAFH
;'AND' Ace CONTENTS WITH
;MA~K IN LOCATION 63
«Rr»
6-624
INSTRUC'nON
ser
ThleI8 a 2-cycIe 1naIructIon. Data In the accumutator Is IogIcaIy AtCIed with an ImmadIately-epeclflad muk.
(A) AND data
AI\IDI): AN.. A.#OAFH .
;'~D' ACC CONTENTS
(A) -
Example:
:WITH MASK 10101111
AN.. A.#3+X/Y
;'AND' Ace CONTENTS
;~ VALlE OF EXP
;'3+X/Y'
ANL Pp,#cIata LogIcal AND Port 1-2 WIth immediate Maek,
ThI8 18 a 2-cycIe Instruction. Data on port 'p' is IogicaIy ANDed with an invnedIataly-apeclfled mask.
(Pp) - (Pp) AND data
p= 1-2
\
Note:
Bits 0-1 of the opcode are used to represent PORT 1 and PORT 2. If you are coding in binary rather than
aaaembly language, the mapping is as follOws:
BIts
p1
pO
Port
o
o
0
1
X
1
1 0 2
1
Example:
1
ANDP2: ANt. P2,#OFOH
X.
' ;'AND' PORT 2 CONTENTS
;WJTH MASK 'FO' HEX
;(CLEAR P20-23)
ANLD Pp,A
Opcode:
LogIcal AND Port 4-7 With Accumulator Maek
11
0
0
1 11
1 P1 PO 1
This is a 2-cycle instruction. Data on port 'p' on the 8243 expander is logically ANDed with the digit mask
contained in accumulator bits 0-3.
(Pp) - (Pp) AND (AO-3)
p=4-7
Note:
The mapping of Port/'p' to opcode bits P1,PO is as follows:
o
o
Example:
0
1
1
6
1
1
ANDP4: ANlD P4,A
Port
4
5
6
7
;'AND' PORT 4-CONTENTS
;WITH ACC BITS 0-3
6-625
INSTRU0110tUET
"
Opcode:
10 a9
as
1 10
1
0, 0,1- 'la7
as
86 84183 a2 a1
r'
so 'I
, Th\8,. a 2-cyc1e~. The Program counter and PSW bite 4-7. are,aaved in the stack. The stack
pointer (psW bite 0-2) Is updated. Program controIla then PJ888d to the location apecIfted by 'addreaa'.
execution contInuea at the InstrUctIOn foIowIng the CALl upon return from the subroutine.
«SP» - (PC), (PSW4-7)
,
, '
(SP) - (SP) + 1
(PCS-g) - (addrs-g)
(PCo-7) - (addrO-7)
Add tflrea groupe of two numbers. Put subtotals in locations 50,51 and total in location 52.
Example:
MOV RO,#50
;MOVE '50' DEC TO ADDRESS ,
;REGO
;MOVE CONTENTS OF REG 1
;TOAce
'
;ADD REG 2 TO Ace
;CALL SUBRQUTlNE 'SUBTOT'
;ADD REG 3 TO Ace
;ADD REG,4 TO Ace
;CALL SUBROUTINE '$UBTOT'
;ADD REG 5 TO Ace
;ADD REG 6 TO ACe
;qALL SUBROUTINE 'SUBTOT'
BEGADD: MeV A,R1
ADD A,R2
CALL SUBTOT
ADD A,R3
ADD A,R4
CALL~BTOT
ADD A,R5
ADD A,R6
CALL SUBTOT
;MOVE CONTENTS OF Ace TO
;LOCATION ADDRESSED BY
;REGO
'
;INCREMENT REG 0 ,
;RETURN TO MAIN PROGRAM
SUBTOT: MOV @RO,A
INeRO
RET
CLR A
Clear Accumuletol'
100101011,11
()pcocle:
The contents of the accumulator are cleared to zero.
(A)-OOH
CLR C
Cia. carry BIt
Opcode:
1
1
1
I
I
During normal program execution, the carry bit can be set to one by th8 ADD, ADDC, ALC, CPLC, RAP, and
DM Instructions. ThIs Instruction resets the carry bit to zero.
(C)-O
CLR F1
Clear Flag 1
The F 1 flag Is cleared to zero.
(F1) -
0
INSTRUCTION SET
CLR FO aear Flag 0
Opcode:
1100010
0
Flag 0 Ie cleared to zero.
(Fo)-O
CPL A Complement Accumulator
Opcocle:
I0
0
1
I0
The contents of the accumulator are complemented. This is strictly a one's complement. Each one is
changed to zero and vice-versa.
(A)- NOT (A)
Assume accumulator contains 011010l0.
CPLA: CPL A
;ACC CONTENTS ARE COMPLE·
;MENTED TO 10010101
Example:
CPL C Complement carry Bit
Opcocle:
11
0
0
I
0
The setting of the carry bit is complemented; one is changed to zero, and zero is changed to one.
(C)- NOT (C)
Set C to one; current setting is unknown.
CT01: CLR C
;C IS CLEARED TO ZERO
CPL C
;C IS SET TO ONE
Example:
CPL FO Complement Flag 0
Opcode:
1100110
0
The setting of Flag 0 is complemented; one is changed to zero, and zero is changed to one.
FO- NOT (FO)
CPL F1
Complement Flag 1
Opcode:
L...11_0_ _1--l......10_ _0_--,
The setting of the F 1 Flag is complemented; one is changed to zero, and zero is changed to one.
(F1) - NOT (F1)
6·627
It4STRUC'FfON SET
DA A
DecImal Adjust Accumulator
Opcode:
10
1
0
1 10
The 8-bit accumulator value is adjusted to form two 4-bit Binary Coded Decimal (BCD) digits following the
binary addition of BCD numbers. The carry bit C is affected. If the contents of bits ()-3 are greater than nine,
or if AC is one, the accumulator is incremented by six.
The four high-order bits are then checked. If bits 4-7 exceed nine, or if Cis one, these bits are inCreased by
six. If an overflow occurs, C is set to one; otherwise, it is claared to zero.
Assuma accumulator contains 9AH.
DA A
;Ace ADJUSTED TO 01H with C set
Example:
C
o
AC
0
Ace
9AH
06H
INITIAL CONTENTS
ADD SIX TO LOW DIGIT
o
0
A1H
60H
01H
ADD SIX TO HIGH DIGIT
RESULT
o
DEC A
Decrement Accumulator
Opcode:
0
0 1
°
°
Decrement R~lster
Opcode:
Example:
0'
The cOntents of the accumulator are decremented by one.
(A)-(A)-1
Decrsment contents of data memory location f),3.
MOV RO,#3FH
;MOVE '3F' H~ TO REG
MOV A,@RO
;MOVE CONTENTS OF LOCATION 63
;TOACC
;DECREMENT Ace
DEC A
MOV @RO,A
;MOVE CONTENTS OF Ace TO
;LOCATION 63
Example:
DEC Rr
10
11
100 1 1
r2 f1
rol
The contents of working register 'r' are decremented by one.
(Rr) - (Rr) - 1
r=0-7
DECR1: DEC R1
;DECREMENT ADDRESS REG 1
DIS I DIsable IBF Interrupt
OPCode:1'-0_0_0_--<-10_1_0_--,
Note:
The input Buffer Full interrupt is disabled. The interrupt sequence is not initiated by WR and CS, however,
an IBF interrupt request is latched and remains pending until an EN I (enable IBF interrupt) instruction is
executed.
The IBF flag is set and cleared independent of the IBF interrupt request so that handshaking protocol can
cOntinue normally.
6-628
INSTRUCTION SET
DIS TeNT!
DIHbIe Timer lCounter Interrupt
Opcode:
1,-0_o_ _1-,-10_ _0_1---,1
The timer I counter interrupt is disabled. Any pending timer interrupt request is cleared. The interrupt
quence is not inltisted by an overflow, but the timer flag is set and time accumulation continues.
DJNZ Rr, address
Opcode:
se-
Decrement Register and Test
11
This is a 2-cycle instruction. Register 'r' is decremented and tested for zero. If the register contains all zeros,
program control falls through to the next instruction. If the register contents are not zero, control jumps to the
specified address within the current psge.
(Rr) ... (Rr) - 1
If R ¢ 0, then;
(PCo-7) - addr
A 1Q-bit address specification does not cause an error if the DJNZ instruction and the jump target are on the
same page. If the DJNZ instruction begins in location 255 of a page, it will jump to a target address on the
following page. Otherwise, it is limited to a jump within the current page.
Increment values in data memory locations 50-54.
MOV RO,#50
;MOVE '50' DEC TO ADDRESS
;REGO
;MOVE '5' DEC TO COUNTER
MOV R3,#05
;REG3
INCRT: INC @RO
;INCREMENT CONTENTS OF
;LOCATION ADDRESSED BY
;REGO
INC RO
;INCREMENT ADDRESS IN REG
DJNZ R3,INCRT
;DECREMENT REG ~--JUMP TO
;'INCRT' IF REG 3 NONZERO
NEXT- ;'NEXT' ROUTINE EXECUTED
;IF R3 IS ZERO
Note:
Example:
°
EN DMA
Enable DMA Handshake Lines
Opcode:
_1_ _ _
OJ'1_0_ _0_---'
LI
DMA handshaking is enabled using P26 as DMA request (ORO) and P27 as DMA acknowledge (DACK). The
DACK line forces CS and Ao low internally and clears ORO.
EN FLAGS
Opcode:
Enable Master Interrupts
1L-1_ _ _1-L-10_ _0_--'
The Output Buffer Full (OBF) and the Input Buffer Full OBF) flags OBF is inverted) are routed to P24 and P25.
For proper operation, a "1" should be written to P25 and P24 before the EN FLAGS instruction. A "0" written
to P24 or P25 disables the p i n . '
6-629
INSTRUCTION seT
EN I
Enable IBF Interrupt
Opcode:
10
°
0010
°
The Input Buffer Full interrupt is enabled. A low signal on WR and CS initiates the interrupt sequence.
EN TCNTI
Opcode:
Enable Timer/Counter Interrupt
1,-0_0_ _
0....L.I_o_ _o_1--,1
The timer I counter interrupt is enabled. An overflow of this register initiates the interrupt sequence.
IN A,DBB
Opcode:
Example:
Input Data Bus Buffer Contents to Accumulator
1...-10_0_ _
0.......1_0_0_ _0--,1
Data in the DBBIN register is transferred to the accumulator and the Input Buffer Full (IBF) flag is set to zero.
(A) - (DBB)
(IBF)INDBB: IN A,DBB
;INPUT DBBIN CONTENTS TO
;ACCUMULATOR
°
IN A,Pp Input Port 1-2 Data to Accumulator
Opcode:
Example:
1
°°°° °
11
P1 PO 1
This is a 2-cycle instruction. Data present on port 'p' is transferred (read) to the accumulator.
(A) - (Pp)
p= 1-2 (see ANL instruction)
INP12: IN A,P1
;INPUT PORT 1 CONTENTS
;TOACC
MOV R6,A
;MOVE ACC CONTENTS TO
;REG6
IN A,P2
;INPUT PORT 2 CONTENTS
;TOACC
MOV R7,A
;MOVE ACC CONTENTS TO REG 7
INC A Increment AccumUlator
Opcode:
1
° ° °
0
1 1
1
The contents of the accumulator are incremented by one.
(A)-(A) + 1
Example:
Increment contents of location 10 in data memory.
INCA: MOV RO,#10
;MOV '10' DEC TO ADDRESS
;REGO
MOV A,@RO
;MOVE CONTENTS OF LOCATION
;10 TO ACC
INC A
;INCREMENT ACC
MOV @RO,A
;MOVE ACC CONTENTS TO
;LOCATION 10
6-630
INSTRUCTION SET
INC Rr Increment Register
1
Opcode:
1 11
r2 r1
rO 1
The contents of working register 'r' are incremented by one.
(Rr) - (Ar) + 1
r=0-7
INCRO: INC RO
;INCREMENT' ADDRESS REG
Example:
INC ORr
°°°
°
Increment Data Memory Location
Opcocle:
Example:
10
°
0110
°°
rl
The contents of the resident data memory location addre~ by registar 'r' bits 0-5 are incremented by
one.
r=0-1
«Rr» +1
INcOM: MaV R1,#OFFH
;MaVE ONES TO REG 1
INC @R1
;INCREMENT LOCATION 63
«Ar»
J8b addr... Jump If Accumulator Bit Is Set
Opcode:
Example:
JC addre..
Ib2 b1
bo
1 1
°°
This is a 2-cycle instruction. Control passes to the spacified address if accumulator bit 'b' is set to one.
(PCQ-7) - addr
if b=1
(PC) - (PC) + 2
if b=O
JB41S1: JB4 NEXT
;JUMP Te 'NEXT' ROUTINE
;IF ACC. BIT 4= 1
Jump If Carry Is Set
Opcocle:1L...1_ _ _ _1,-LI_o_ _ _o--'l- la7 a6 a5 84l a3 a2 a1 SO 1
Example:
This is a 2-cycle instruction. Control passes to the spacified address if the carry bit is set to one.
(PCo-7) - addr
if C=1
(PC) - (PC) + 2
if C=O
JC1: JC OVERFLOW
;JUMP TO 'OVFLOW' ROUTINE
;IFC=1
JFO addr... Jump If Flag 0 I. Set
Opcocle:
Example:
LI1_0
_ _ _1--LI_o_ _ _o--,l- la7 86 85 a41 83 a2 a1 aol
This is 8 2-cycle instruction. Control passes to the spacified address if flag
- PI)
p=4-7
p=4-7
Move data in accumulator to porta 4 and 6.
0UTP45: MOVD P4,A
SWAP A
MOVD P6,A
;MOVE ACC BITS 0-3 TO PORT 4
;EXCHANGE ACC BITS 0-3 AND 4-7
;MOVE Ace BITS 0-3 TO PORT 6
6-637
INSTRU<;TION SET
Move Current Page
MOVP A.oA
Opcode:
Note:
Example:
Date to Accumulator.
11010100111
This Is a 2-eycle Instruction. The contents of the program memory location addressed by the accumulator
are moved to the accurnulstor._ Only bits 0-7 of the program counter are a~, Hrnlting the program
niemory reference to the current page. The program counter Is restor~ following this operation. .
(A)- «A»
.
This Is a 1-byte, 2-eycle InatrucJlon. If It apP8&r8 in location 266. of a program memory page, @Aaddresses
a location In the following page.
MOV128: MOV A,#128
;MOVE '128' DEC TO Ace'
MOVP A,@A
;CONTENTS OF 129TH LOCATION
;IN CURRENT PAGE ARE MOVED TO
;Ace
MOVP3 A,OA
Opcode:
Example:
Move Page 3
.
,
Date to Accumulator
'1-1_ _1_0...1...1_0_0_1_1...../1
This Is a 2-eycle instruction. The contents of the program memory location within pags 3, addressed by the
accumulator, are moved to the accumulator. The program counter Is restored following this operation.
, (A) - «A» within pags 3
Look up ASCII eqUivalent of hexadecimal code In table contained at the beginning of pags 3. Nota that ASCII
characters are designated by a 7-bit code; the eighth bit is alwaYs reset.
I
TABSCH: MOV A,#0B8H
;MOVE '88' HEX TO Ace (10111000) .
ANL A,#7FH
;LOGICAL AND Ace TO MASK BIT
;7 (00111000)
MOVP3, A,@A
;MOVE CONTENTS OF LOCATION
. ;'38' HEX IN PAGE 3 TO Ace
;(ASCII '8')
Access contents of location in page 3 labelled TAB 1. Assume currant program location Is not in page 3.
TABSCH: MOV A,#TAB1
;ISOLATE BITS 0-7
;OFLABEL
;AODRESS VALUE
MOVP3 A,@A
;MOVE CONTENT OF PAGE 3
;LOCAirON LABELED 'TAB l' (
;TOAce
NOP The HOP Instruction
Opcode:
10000100001
No operation Is performed. Execution continues with the following instruction.
ORL A,Rr
Opcocle:
Example:
Logical OR Accumulator With Register Mask
I0
1
0
0 11
r2 r1 ro
I
Data in the accumulator is logically ORed.witt! the ",-sk contained in wprl
p=4-7 (See MOVD instruction)
ORP7: ORLD P7,A
;'OR' PORT 7 CONTENTS
;WITH Ace BITS 0-3
Output Accumulator Contents to Oats Bus Buffer
10000100101
Contents of the accumulator are transferred to the Data Bus Buffer Output register and the Output Buffer FuH
(OBF) flag is set to one.
'
(DBB)-CA)
OBF-1
OUTDBB: OUT DBB,A
;OUTPUT THE CONTENTS OF
;THE Ace TO DBBOUT
6-639
•
INSTRUCTION SET
OUTL Pp,A
Opcode:
OUtput Accumulator Data to Port 1 and 2
0_0_ _1--l-11_0_p_1_PO---li
L..I
This is a 2-cycle instruction. Data residing in the accumulator is transferred (written) to port 'p' and latched.
P=1-2
(Pp) - (A)
Bits 0-1, of the ,opcode are used to represent PORT 1 and PORT 2. If you are coding in binary rather than
assembly language, the mapping is as follows:
Note:
Bits
Example:
RET
Port
p1
pO
1f
1f
°11
1
1
1
2
X
OUTLP: MOV A,R7
OUlL P2,A
MOVA,R6
OUR P1,A
X
°
;MOVE REG 7 CONTENTS TO Ace
;OUTPUT Ace CONTENTS TO PORT2
;MOVE REG 6 CONTENTS TO Ace
;OU~T Ace CONTENTS TO PORT 1
Return Without PSW Restore
Opcode:
110
°
010
0
This is a 2-cycle instruction. The stack pointer (PSW bits 0-2) Is decremented. The program counter is then
restored from the stack. PSW bits 4-7 are not restored.
(SP) - (SP) - 1
(PC) - «SP»
RETR
Return With PSW Restore
Opcode:
110
0110
°
This is a 2-cycle instruction. The stack pointer is decremented. The program counter and bits 4-7 of the
PSW are then restored from the stack. Note that RETR should be used to return from an interrupt, but should
not be used within the interrupt service routine as it signals the end of an interrupt routine.
(SP) - (SP) - 1
(PC) - «SP»
(PSW4-7) - «SP})
RL A
Rotate Left Without Carry
Opcode:
Example:
1-11_ _1_0--,-10_ _ _--'
The contents of the accumulator are rotated left one bit. Bit 7 is rotated into the bit
n=0-6
(An+ 1) - (An)
(Ao) - (A7)
Assume accumulator conteins 10110001.
RLNC: RL A
;NEW Ace CONTENTS ARE 01100011
6-640
°
position.
INSTRucnON SET
RLC A RotAde Left Through c.ry
()pcQde:
11.1
1
1101111
The contents of the accumulator are rotated left one bit. Bit 7 replacee the carry bit; the carry bit Ia rotated
into the bit 0 poaItIon.
CAn+1) -
n-(}.8
.. (Ao)-(C)
Example:
(C)- (A7)
As8ume accumulator contalna a '8Igned' number; isolate sign without changing Value.
ALTC: a.R C
;a.EAR CARRY TO ZERO
ALC A
;ROTATE ACe lEFT, SIGN
;B/T (7) IS PLACED IN CARRY
RR A
;ROTATE Ace RIGHT - VALUE
;(BITS 0-6) IS RESTORED,
;CARRY UNCHANGED, BIT 7
;ISZERO
RA A Rotate RIght Without c.ry
Opcode:
Example:
1011110111
The contents of the accumulator. are rotated right one I:!it. Bit 0 is rotated into the bit 7 position.
(An> - (An+ 1)
n=0-6
(A7)-(Ao)
Assume accumulator contains 10110001.
RRNC: RRA
;NEW Ace CONTENTS ARE 11011000
RAC A Rotate RIght Through Carry
0pc:0cIe:
10110101111
The contents of the accumuiator are rotated right one bit. Bit 0 replaces the carry bit; the carry bit is rotated
into the bit 7 position.
- (An+1)
n=0-6
(A7)- (C)
(C)-(Ao)
Exalnple:
As8ume carry Ia not set and accumulator contains 10110001.
RATC: RRCA
;CARRY IS SET AND Ace
;CONTAINS 01011000
SEL RBO SeleCt Register Bank 0
Opcode:
11
100101011
PSW BIT 4 is set to zero. References to working reglaters 0-7 address data memory locations 0-7. This is
the recommended setting for normal program execution.
(8$)-0
6-641
INSTRUCnON SET
SEL RB1
Select Register Bank 1
Opcode:
Example:
11
Opcode:
Example:
,~
10110101
PSW bit 4i8 set to one. References to working registers ()-.,7'addreas data memory Jocations 24-31. Thiels
the recommended setting for Interrupt service routines, since locations 0-7 are IefHntact. The setting of
PSW bit 4 in effect at the time of an Interrupt Is restored by ttwRETR instruction when the, Interrupt service
routine is completed.
(BS)-1
Assume an ISF interrupt has occllrred. control has passed to program memory location 3, and PSWblt 4
was zero before the interrupt.
LOC3: JMP INIT
;JUMPTO ,ROUTINE 'INIT'
SEL RB1
MOV R7,#OFAH
;MOV ACe CONTENTS TO
;LOCATION 7
;SELECT REG BANK 1
;MOVE 'FA' HEX Tq LOCATION 31,
SEL RBO
MOVA,R7
RETR
;SELECT REG BANK 0
;RESTORE, ACC FROM LOCATION 7
;RETURN--RESTORE PC AND PSW
INIT: MOV R7,A
STOP TCNT
,
Stop Timer IEvent Counter
10110101011
This instruction is used to stop both time accumulation and event counting.
",'
Disable interrupt, but jump to interrupt routine after eight overflows and stop timer. Count overflows in
reglst,r 7.
'
;DISABLE TIMER INTERRUPT
START: DIS TCNTI
CLR A
;CLEAR ACC TO, ZERO
MOV T,A
:MOV ZERO'TO TIMER
MOV R7,A
:MOVE ZERO TO REG 7
STRT T
;START TIMER
MAIN: JTF COUNT
;JUMP TO ROUTINE 'COUNT'
;1f,)f,F=1 ANOCLEAR TIMER FLAG
;CLOSE LOOP
JMP MAIN
COUNT: INC R7
;INCREMENT REG 7
MOV A,R7
;MOVE REG 7 CONTENTS TO ACe
JB3 INT
;JUMP TO ROUTINE 'INT' IF ACC
;BIT 31S SET (REG 7=8)
,
JMP MAIN
;OTHERWISE RETURN TO ROUTINE
;MAIN
INT: STOP TCNT
JMP7H
;STOP TIMER
;JUMP TO LOCATION 7 (TIMER
;INTERRUPT ROUTINE)
6..642
INSTRUCTION SET
STRT CNT Start Event Counter
1010010101
0pc0cIe:
The lJ;ST 1 (T 1) pin is enabled as the event-counter input and the counter is started. The event-counter
register is Incremented with each high to low transition on the T 1 pin.
Initialize and start event counter. Assume overflow Is desired with first T 1 input.
STARTC: EN TCNTI
;ENABLE COUNTER INTERRUPT
.
MOV A,#OFFH
;MOVE 'FF' HEX (ONES) TO
;Ace
MOV T,A
;MOVE ONES TO COUNTER.
STAT CNT
;INPUT AND START
Example:
STRT T
Start Timer
Opcode:
Example:
1,-0_ _
1 _0_....L.1_0_1_0_1--,
Timer accumulation Is initiated In the timer register. The register is incremented every 32 instruction cycles.
The preecaler which counts the 32 cycles is cleared ~t the timer register is not.
Initislize and start timer.
STARTT: EN TCNTI;ENABLE TIMER INTERRUPT
CLR A
;CLEAR ACC TO ZEROS
MOV T,A
;MOVE ZEROS TO TIMER
STRT T
;START TIMER
SWAP A Swap Nibble. Within Accumulator.
Opcode:
Example:
10100101
11
Bits 0-3 of the accumulator are swapped with bits 4-7 of the accumulator.
(A4-7) (Ao-a>
Pack bits 0-3 of locations 50-51 into location 50.
PCKDIG: MOV RO,#50
;MOVE '50' DEC TO REG 0 .
MOV R1,#51
;MOVE '51' DEC TO REG 1
XCHD A,@RO
;EXCHANGE BIT 0-3 OF Ace
;AND LOCATION 50
SWAP A
;SWAP BITS 0-3 AND 4-7 OF ACC
XCHD A,@R1
;EXCHANGE BITS 0-3 OF Ace AND
;LOCATION 51
MOV @RO,A
;MOVE CONTENTS OF Ace TO
;LOCATION 51
XCH A,Rr Exchange Accumulator-Register Contents
Opcode:
Example:
I0
0 '1
0 11
[2 r1
rO
I
The COJ:Itents of the accumulator and the contents of working register 'r' are exchanged.
CA) (Rr)
r=0-7
Move PSW contents to Reg 7 without losing accumulator contents.
XCHAR7: XCH A,R7
;EXCHANGE CONTENTS OF REG 7
;AND Ace
MOV A,PSW
;MOVE PSW CONTENTS TO ACC .
XCH A,R7
;EXCHANGE CONTENTS OF REG 7
;AND Ace AGAIN
6-643
I,NSTRUCTION SET
XCH A,@Rr
Exchange Accumulator and Data Memory Contents
Opcode:
100101000
The contents of the accumulator and the contents'of the data memory locatiOn addressed by bits 0-5 of
register 'r' are exchanged. Register 'r' contents are unaffected.
(A) «Rr»
r=0-1'
Decrement contents of location 52.
DEC52: MOV RO,#52
;MOVE '52' DEC TO ADDRESS
;REGO
XCH A,@RO
;EXCHANGE CONTENTS OF Ace
;AND LOCATION 52
DEC A
;DECREMENT ACC CONTENTS
XCH A,@RO
;EXCHANGE CONTENTS OF Ace
;AND LOCATION 52 AGAIN
Example:
XCHD A,@Rr
Opcode:
Example:
XRL A,Rr
rl
Exchange Accumulator and Data Memory 4-blt Data
0_0
_ _ _1...J.1_0_0_0_--,rI
,-I
This instruction exchanges bits 0-3 of the accumulator with bits 0-3 of the data memory location addressed
by bits 0-5 of register 'r'. Bits 4-7 of the accumulator, bits 4-7 of the data memory location, and the
contents of register 'r' are unaffected.
(AO-3) «RrO-3»
r=0-1
Assume program counter contents have been stacked in locations 22-23.
XCHNIB: MOV RO,#23
;MOVE '23' DEC TO REG 0
CLR A
;CLEAR Ace TO ZEROS
XCHD A,@RO
;EXCHANGE BITS 0-3 OF Ace
;AND LOCATION 23 (BITS 8-11
;OF PC ARE ZEROED, ADDRESS
;REFERS TO PAGE 0)
Logical XOR Accumulator With Register Mask
I
opcode:lL _1_ _
0_1...J.1_1_r2_r_1_r--,O
Example:
XRL A,@Rr
Opcode:
Example:
Data in the accumulator is EXCI.,USIVE ORed with the mask contained in working register 'r'.
r=0-7
(A) - (A) XOR (Rr)
XORREG: XRL A,R5
;'XOR' Ace CONTENTS WITH
JMASK IN REG 5
Logical XOR Accumulator With Memory Mask
11
Data in the accumulator is EXCLUSIVE ORed with the mask contained in the data memory location addressed by register 'r'; bits 0-5. '
r=0-1
(A) - (A) XOR «(Rr»
XORDM: MOV R1,#20H
;MOVE'20' HEX TO REG 1
XRL A;@R1
;'XOR' ACC CONTENTS WITH MASK
;IN LOCATION 32
6-644
INSTRUCTION SET
XRL A,#data
Opcode:
Logical XOR Accumu..tor With immediate Mok
11 1
0
1 10
0
1 1 1• 1d7 de ds d41 d3 d2 d1 do 1
This is a 2-cycia instruction. Data in the accumulator is EXCLUSIVE ORad with an immediately-specified
mask.
Example:
(A) - (A) XOR data
XORID: XOR A,#HEXTEN
;XOR CONTENTS OF ACC WITH
;MASK EQUAL VALUE OF SYMBOL
.;'HEXTEN'
6-645
. CHAPTER 4
SINGLE-STEP, PROGRAMMING,
AND POWER..DOWN MODES
SINGLE-STEP
Figure 4-1 illustrates a recommended circuit for single-step operation, while Figure 4-2 shows the tim!!!grelationship between the SYNC output and the
SS input. During single-step operation, PORT 1 and
part of PORT 2 are used to output address information. In order to retain the normal I/O functions of
PORTS 1 and 2, a separate latch can be used as
shown in Figure 4-3.
The UPI (amilyhas a single-step mode which allows
the user to manually step through his program one
instruction at a time. While stopped, the address of
the next instruction to be fetched is available on
PORT 1 and the lower 2 bits of PORT 2. The singlestep feature simplifies program debugging byallowing the user to easily follow program execution.
+sv
+sv
10k
r
PRESET
fj}
MOMENTARY
PUSH TO STEP
+sv
PRESET
+sv
Q
D
10k
HALT
Q
D
TOSS
INPUT
ON 8741A
+sv
CLOCK
10k
CLEAR
CLEAR
FROM
% 7414
% 7474
Figure 4-1.
SYNC
-.J
~
ss
P10·17
Single-Step Circuit
I
P20-P21
SS BUrTON
Pca-7
>C
PCB-9
>C
STOP CYCle
ACTIVE CYCLE
Figure 4-2.
:~
::
::
X
X
PORT DATA
8741A
SYNC
OUTPUT
Single-Step TIming
6-646
ACTIVE CYCLE
SlNGLE-STEP,PAOGAAMMING, & POWEA;'OOWN MODES
SYNC
P10
D10
P10
DATA IN
P11
D11
D12
P12
8041AH
8042
87·&1A
87.2
P13
D13
P14
D1.
P15
D15
P18
D18
D17
P17
"-
""
"::"
:-,
+5v
SYNC
"
+5V
ADDllE55
DISPLAY
(LED)
1011
P17
OC
LS
D17
=
OPEN COLLECTOR Tn.
= LOW POWER SCHOTTKLY TTL
Figure 4-3.
latching Port Data
Timing
The sequence of single-step operation is as follows:
1) The processor is requested to stop by applying a
low level on SS. The SS input should not be
brought low while SYNC is high. (The UPI
samples the SS pin in the middle of the SYNC
pulse).
T~e
2)
processor responds to the request by stopping during the instruction fetch portion of the
next instruction. If a double cycle instruction is
in progress when the single-step command is received; both cycles will be completed before
stopping.
3)
The processor acknowledges it has entered the
stopped state by raising SYNC high. In this
state, which can be maintained indefinitely, the
10-bit address of the 'next instruction to be
fetched is ,present on PORT 1 and the lower 2
bits of PORT 2.
4)
P171NPUT DATA
SS is then raised high to bring the processor out
of the stopped mode allowing it to fetch the
next instruction. The exit from stop is indicated
by the processor bringing SYNC low.
5)
To stop the processor at the next instruction SS
must be brought low again before the next
SYNC pulse-the circuit in Figure 4-1 uses the
trailing edge of the previous pulse. If SS is left
high, the processor remains in the "RUN"
mode.
Figure 4-1 shows a schematic for implementing single-step. A single D-type flip-flop with preset and
clear is used to generate SS. In the RUN mode SS is
held high by keeping the flip-flop preset (preset has
precedence over the clear input). To enter singlestep, preset is removed allowing SYNC to bring SS
low via the clear input. Note that SYNC must be
buffered since the SN7474 is equivalent to 3 TTL
loads.
The processor is now in the stopped state. The next
instruction is initiated by clockinL'~" into the flipflop. This "1" will not appear on SS unless SYNC is
high (i.e., clear must be removed from the flip-flop).
In response to SS going high, the processor begins an
instruction fetch which brings SYNC low. SS is then'
reset through the clear input and the processor again
enters the stopped state.
, 6-647
,INGLE-STEp,. PI(oGRAMNlI~G~:&POWER..DOWN, MODES
PROGRAMMING, VERIFYING AND ERASING
EPROM (8741A, 8742 EPROM ONLY)
The internal Program Memory of the 8741A and
8742 may be erased and reprogrammed by the user
as explained in the following sections. See the data
sheet for more detail.
•
P20, P21 .Address Input
•
VDD
Programming Power Supply
•
PROG'
Program Pulse Input
NOTE: All set-up and hold times are 4 cycles.
Th~ detailed Programming sequence (for one byte)
Programming
is as follows:
The programming procedure consists of the following: activating the program mode, applying an
address, latching the address, applying data, and
applying a programming pulse. Each word is programmed completely before moving on to the next
and is followed by a verification step. Figure 4-4
illustrates the programming and verifying sequence.
The following is a list of the pins used for programming and a description of their functions:
• XTAL I, Clock Input
XTAL2
I)
Initial Conditions: Ycc =; VDD = 5V; Clock
Running; AO = OV, CS = 5V; EA = 5V; DO-D7
and PROG Floating.
2)
RESET = oV, TEST 0 'i= OV (Select Programming Mode).
3)
EA'= 23V for 8741A
EA = 18V for 8742
•
RESET Initialization and Address Latching
4)
Address applied to DO-D7 and PORTS 20-22.
•
TEST 0 Selection of Program or Verify
Mode
5)
RESET = 5V (Latch Address).
•
EA
Activation of Program/Verify
Modes
6)
Data applied to Do-D7.
•
DO-D7
Address and Data Input
Data Output During Verify
7)
VDD = 25V for 8741A
.
VDD = 21V for 8742 tProgramming Power).
+5V
RESET
BUS
·1
A~D PROG CAN BE DRIVEN ONLY DURING THIS TIME
+5V
TEST 0
+23Y/+18V
EA
.
+5V
PO·P7
(
ADDRESS 0-7
P20'·21
(
ADDRESS AO-Ag
>-<
. DATA
)
)
+25vl+21V
Voo
+5V
+5V
PROG
+OV
,
+23VI+21V
I
. Figure 4-4. . Programming Sequence
6-648
L.,
~
OUT
SINGLE-STEP, PROGRAMMING, a ,POWER-DOWN MODES
8)
PROG =OV followed by one 50 msec pulse of
23V for 8741A
PROG = OV followed by one 50 msec pulse of
18V for 8742.
9)
VOO
=5V.
= 5V (Select Verify Mode).
10)
TEST 0
11)
Read data on 00-07 and verify EPROM cell
contents.
WARNING
An attempt to prOgram a mis-socketed 8741A
or 8742 will result in severe damage to the part.
An indication of a properly socketed part is the
appearance of the SYNC clock output. The
lack of this clock, may be used 'to disable the
programmer.
Verification
Verification is accomplished by latchj.ng in an address as in the Programming Mode and then applying "1" to the TEST 0 input. The word stored at the
selected address then appears on the Do-D7 lines.
Note that verification can be applied to both ROM's
and EPROM's independently of the programming
procedure. See the data sheet.
The detailed Verifying sequence (for one byte) is as
follows:
1)
Initial Conditions: VCC = VOO = 5V; Clock
Running; Ao = OV, CS = 5V; EA ~ 5V; 00-07
and PROG Floating.
2) RESET
3)
= OV, TEST 0 = 5V (Verify Mode).
EA = 23V for 8741A
EA = 18V for 8742
,4) . Address applied to 00-07 and PORTS 20-22.
= 5V (Latch Address)
5)
RESET
6)
Read data on 00-07 and verify EPROM cell
contents.
Erasing
The program memory of the 8741A or 8742 may be
erased to zeros by exposing' its translucent lid to
shortwave ultraviolet light.
EPROM Light Sensitivity
The erasure characteristics of the 8741A or 8742
EPROM are such that erasure begins to occur when
exposed to light wit/l wavelengths shorter than approximately 4000 Angstroms. It should be noted
that sunlight and certain types of fluorescent lamps
have wavelengtlls in the 3<>00-4000 Angstrom range.
Oata shows that constant exposure to room level fluorescent lighting could erase the typiclil8741A in approximately 3 years while it wO\1ld take
approximately 1 week to cause erasure when exposed to direct sunlight. If the 8741A or 8742 is to be
exposed to these types of lighting conditions for extended periods or' time, opaque labels (available
from Intel) should be placed over the 8741A or 8742
window to prevent unintentional erasure.
The recommended erasure procedure for the 8741A
or 8742 is exposure to shortwave ultraviolet light
which has a wavelength of 2537 Angstroms. The integrated dose (i.e., UV intensity X exposure time)
for erasure should be a minimum of 15W-sec/cm2
pOwer rating. The erasure time with this dosage is
approximately 15 minutes using an ultraviolet lamp
with,a 12;OOO,I'W/cm2 power rating ..The 8741A or
8742 should be placed within 1 inch of the lamp
tubes during eras~re. Some lamps have a fllter on
their tubes which should be removed before erasure.
EXTERNAL ACCESS
The UPI family has an External Access mode (EA)
which puts the processor into a test mode. This
mode allows the user to disable the internal program
memory and execute from external memory. Exter-·
na1 Access mode is useful in testing because it allows'
the user to test the processor's functions directly.-It
is only useful for testing since this mode uses 00-07,
PORTS 10-17 and PORTS 20-22.
This mode is invoked by connecting the EA pin to
5V. The ll-bit current program counter contents
then come out on PORTS 10-17 and PORTS 20-22
after the SYNC output gOes high. (PORT 10 is the
least significant bit.). The desired instruction opcode
is placed on 00-07 before the start of state Sl. Ouring state SI, the opcode is sampled from 00-07 and
subsequently executed in place of the internal program memory contents.
The program counter contents are multiplexed with
the I/O .port data: on PORTS 10-17 and PORTS 2022. The I/O port data may be demultiplexed using
an external latch on the rising edge of SYNC. The
program counter contents may be demultiplex.ed
similarly using the trailing edge of SYNC.
Reading and/or writing the Oata Bus Buffer registers is still allowed although only when 00-07 are
not being sampled for opcode data. In practice, since
this sampling time is not known externally, reads or
9-649
SINGLE-STEP, PROGRAMMING, &.POWER-DOWN MODES
writes on the system bus are done during SYNC high
time. Approximately 600ns are available for each
read or write cycle.
early enough to guarantee the 8041AH or 8042
can save all necessary data before· VCC falls
outside normal operating t\>lerance.
POWER DOWN MODE
(S041AH/S042 ROM ONLY)
Extra circuitry is included in the ROM version to allow low-power, standby operation. Power is removed
from all system elements except the internal data
RAM in the iow-power mode. Thus the contents of'
RAM can be maintained and the device draws only
10 to 15% of its normal power.
The VCC pin serves as the 5V power supply pin for
all of the ROM version's circuitry except the data
RAM array. The VDD pin supplies only the RAM
array. In normal operation, both VCC and VDD are
connected to the same 5V power supply.
To enter the Power-Down ~ode, the RESET signal
to the UPI is asserted. This ensures the memory will
. not be inadvertently altered by the UPI during
power-down. The VCC pin is then grounded while
VDD is maintained at 5V. Figure 4-5 illustrates a
recommended Power-Down sequence. The sequence
typically occurs as follows:
1)
2)
A "Power Failure" signal is used to interrupt
the processor (via a timer overflow interrupt,
for instance) and call a Power Failure service
routine.
3)
The Power Fltilure routine saves all important
data and machine status in the RAM array. The
routine may also initiate transfer of a backup
supply to the VOO pin and indicate to external
circuitry that the Power Failure routine is complete.
4)
A RESET signal is applied by external hardware to guarantee data will not be altered as the
power supply falls out of limits. RESET must
be low until VCC reaches ground potential.
Recovery from the Power-Down mode «an occur as
any other power-on sequence. An external 1 I'fd capacitor on the RESET input will provide the necessary initialization pulse.
Imminent power supply failure is detected by
user defined circuitry. The signal must occur
:'\
1 '"1----
POWER SUPPLY
:;'~~~~~~D
/
PO':i~ ~~:~r
1
1
I
I
NORMAL
1
FOLLOWS
1
-----1--------:~;fU":Ng~
r
- - - " " " , ''"I-----1:1
1
1
1
_____+,1 ____--;1,
ReSET
11
LJI
1i
1________ _
I.
II
PATA SAVE
ROUTINE
EXECUTeD
Figure 4-5,
ACCESS TO
DATA RAM
INHIBITED
Power-Down Sequence
6-650
CHAPTER 5
SYSTEM OPERATION
BUS INTERFACE
The UPI-41AH, 42 Microoomputer functions as a
peripheral to a master processor by using the data
bus buffer registers to handle data transfers. The
,DBB confIgUration is illustrated in Figure 5·1. The
UPI-41AH, 42 Microcomputer's 8 three-state data
lines (D7-DO) connect directly to the master processor's data bus. Data transfer to the master is controlled by 4 external inputs to the UPI:
• Ao Address Input signifying command
or data '
• CS Chip Select
Read strobe
• RD Write strobe
• WR
the system Data Bus. The OBF flag is cleared automatically.
Reading STATUS '
The sequence for reading the UPI-41AH, 42
Microcomputer's 8 STATUS bits is shown in Figure
.5-3. This operation causes the 8-bit STATUS register contents to be placed on the system Data Bus as
shown.
;'
Write Data to DBBIN·
The sequence for writing data to the DBBIN register
is shown in Figure 5-4. This operation causes the system Data Bus contents to be transferred to the
DBBIN register and the mF flag is set. Also, the F1
flag is cleared (F1 = 0) and an interrupt request is
generated. When the IBF interrupt is ~nabled, a
jump to location 3 will occur. The interrupt request
is cleared upon entering the mF service routine or
by a system RESET input..
Wii
CONTROL
BUS
AD
Ao
Ci
cs'
..Jr
----«\-,._ _
DATA
Figure 5-1. 'Data .... Reg'"
~atlon
Figure 5-2.
The master processor addresses the UPI:41AH, 42
Microcomputer as a standard peripheral device. Table 5-1 shows the conditions for datil transfer: "
cs
Table 5-1'. 'Data Transfer Controls
CI
,
Ao·RD WR·
0
0
0
, '0
0
1 " 0
0
1
1
1
0
0
1
x
x'
0
x
Condition
"
~,,---_--,I
AoJ
\"--------\''-_...11
ae.dD~BOUT
1
1
DBBOUT Reed'
~
Read STATUS
Write DBBIN data, set Fl =0.'
Write DBBIN command se~,
Fl 1
Diliabl~DBB
=
-------~
-----.""1(....._ _ _' .~.~
. ' DATA ..
ails CONTENTS _
.1
aeadl",i the DBBOUT.R.gI.ter,
The sequence for reading the DBBOUT register is
'shown'in Figure 5-2. This operation causes the'8.:bit
contents of the DBBOUT register to be placed on
ST/IST6: 1
~
STS
1 ST4 1
~'.~'~
STATUS READ
Fl
'00
I.
Fo
1 .BF 1 OBF 1
~
·FIgure 5-3. Statua Read,
6:.e51
~
00
SYSTEM OPERATION
, 'os
>
I
Ao
--.JI
Wii
Wii - -.....,\,.'_ _
DATA
--<
)--
Writing Data to DB8IN
FIgwe 5-5.
Writing, ¢ommands to D~BIN
Operations of Data Bus Registers
The UPI-41AH, 42 Microcomputer controls the
of DBB data to its accumulator by executing INput and OUTput instructions. An IN A,DBB
instruction causes the ,contents to be transferred to
the UPI accumulator and the mF flag is cleared.
~ransfer
The OUT DBB,A instruction causes the contents of
the accumulator to be transferred to the DBBOUT
register. The OBFtlag ~ set.
..
8 * Interface
, Figure 5·7 illustrates a UPI-41AH, 42 interface to an
8088 minimum mode system; Two 8-bit latches are
used to demultiplex the address and data bus. The '
address bus is 2O-lines wide. for I/O only, the lower
16 alidress lines are used, providing an addressing
range of 64K. UPI address selection is accomplished
using an 8205 decoder. The Ao address line of ihe
bus is connected to the corresponding UPI input for
register selection. SiD,~ tJte UPI-~UA is polled by the
B088, neither DMA nor master interrupt caPabilities
of the, UPI-41AH, 42,4U'8 used in the fIgUJ'e.
The UPI's data ,bus buffer interface is applicable to a
variety of microprocessors including the B086, 8088,
8085AH, B08O; and 8048.
"
,cessors follows.
WrItIng CornmaIIda to DB8IN
using the two DMA handshaking lines of PORT 2.
The 8237 performs the actual bus transfer operation.
Using the UPI-41AH, 42's ()BF master interrupt,
the UPI-41A notifies the 8085AH upon transfer
completion using the RST 5.5 interrupt input. The
IBF master interrupt is not used in this example.
The sequence for writing, commands to the DBBIN
register is shown in Figure 5-5. This seqlclence is
identical to a data write except that the Ao input is
latched in the Fl flag (Fl = 1). The IBF flag is set
and an interrupt request is generated, when the master writes a command to DBB.
fA description of the interface to each of these
,-----
DATA
\,....._ _--J
,FIgwe 504.
"_'_..........,1
~--~
pro~
.
DESIGN EXAMPLES
8085AH Interface
Figure 5-6 i~h~strates>an 8085AH system using a
:UPI-41AH, 42. The 8085AH system uses a multiplexed address and data bus. During I/O the 8 upper
address lines =
..... .
~..
.. ...
~ .. ~
!>=.
MOTOR
:0
0
iil
0
Q
~
DRIVERS
1I1
0
I
SOLENOID
DRIVERS
70R9
PQRT2
PORT 2
PORT l/PORT 2
8041A/8741A
INTERFACE
TO 8-BIT
MASTER
PROCeSSOR
\
DATA BUS
't
CQNTROLBUS
DBB
CONTROL
~
4
Figure 6-2.
\
j
Matrix Printer Controller
6-658
APPLICATIONS
DATA
EDT/BOT
10--01
I
DATA
OUT
I~
DATA ENCODE/DECODE
AND COMMAND
DATA
IN
Cl..OCK
STATUS
2
.~
MOTOR
DRIVE
FWD
SPEED
REV
4
I
PORT 1
,
I
POAT2
8041A/8741A
CONTROL
DBB
INTERFACE
TO 8·81T
MASTER
PROCESSOR
~
DATA BUS
\
CONTROl BUS
Figure 6-3.
Tape Transport Controller
PORT 1 is used strictly for I/O in this example while
PORT 2 lines provide five functions:
• P23-P20 I/O lines (bidirectional)
• P24
Request to send (RTS)
Clear to Send (CTS)
• P25
Interrupt to master
• P26
• P27
Serial data out
The parallel I/O lines make use of the bidirectional
port structure of the UPI. Any line can function as
an input or output. All port lines are automatically
initialized to 1 by a system RESET pulse and remain
inserted, busy, and write permit. All control signals
can be handled by the UPl's two I/O ports.
Universal 1/0 Interface
Figure 6-4 shows an I/O interface design based on
the UPI. This configuration includes 12 parallel I/O
lines and a serial (RS232C) interface for full duplex
data transfer up to 1200 baud. This type of design .
can be used to interface a master processor to a
broad spectrum of peripheral devices as well as to a
.
serial communication channel.
PARALLEL
RS232C
I/O
SERIAL INTERFACE
,-L-,
I
I
ers
RTS
OUTPUT
TO
'"
MASTER :
12
PRocr
SOR
I
,
J. ~AO
TRANSMIT
DATA
,
.......,....
~A1
INTERRUPT
I
I
RECEIVE
DATA
TEST 0
PORT 2
PORT 1 AND 2
8041A/8741.
CONTROl
DBB
INTERFACE
\
1
DATA
TO 8-BIT
MASTER
PROCESSOR
\
CONTROL
Figure. 6-4.
J
I I
Universal 1/0 Interface
6-659
\
APPLICATIONS
latched. An external TTL signal connected to a port
line will override the UPI's 5OK-ohm internal pullup so that an INPUT instruction will c:orrect1y sample the TTL signal.
P25.
can'be preset to generate an interrupt at the proper
time·for sampling the serial bit stream. This eliminates the need for software timing loops and allows
the proceBBOr to proceed to other tasks (i.e., parallel
I/O operations) between serial bit samples. Software
flags are used so the main program can determine
when the interrupt driven receive program has a
character assembled for it.
,
This type of conflgUl'atlon allows system designers
flexibility in designing custom I/O interfaces for specific serial and parallel I/O applications. For instance, a second or third serial channel could be
substituted in p~ of the parallel I/O if required.
The UPI's data memory can buffer data and commands for up to 4 low-speed channels (110 baud teletypewriter, etc.)
The RS232C interface is implemented using the
TEST 0 pin as a receive input and a PORT 2 pin as a
transmit output. External packages (Ao, AI) are
used to provide RS232C drive requirtlments. The
serial receive software is interrupt driven and uses
the on-chip timer to perform time critical serial control. After a start bit is detected the interval timer
Application Not..
The following application notes illustrate the various applications of the UPI family. Other related
publications including the 8048 Family Application.
Handbook are available through the Intel Literature
:pepartment.
Four PORT 2 lines function as general I/O similar to
PORT 1. Also, the RTS signal is generated on PORT
2 under software control when the UPI b8s serial
data to send. The CTS signal is monitored via PORT
2 as an enable to the UPI to send serial data. A
PORT 2 line is also used as it software generated interrupt to the master proce880r. The interrupt functions as a service request when the UPI bas a byte of
data to transfer or when it is ready to receive. Alter- .
natively, the EN FLAGS instruction could be used
to create the OBF and IBF interrupts on P24 and .
6-e60
APPLICATIONS
requirements allow them to either stand alone or be
incorporated as just one task ip a "multi-tasking"
UPI, and applications which are complete UPI applications in themselves. Applications in the fmt
group are a simple LED display and sensor matrix
controllers. A combination serial/parallel! I/O device is an application in the second group. Each application illustrates different UPI configurations
and features. However, before the application details are p1eBented, a section on the UPI/master protocol requirements is included. These protocol
requirements are key to UPI software development.
For convenience, the UPI block diagl:am is reproduced in Figure 1 and the instruction set summary
in Table 1.
INTRODUCTION TO THE UPI-41ATIII
Introduction
Since the introduction in 1974 of the second generation of microprocessors, such as the 8080, a wide
range of peripheral interface devices have appeared.
At fmt, these devices solved application problems of
a general nature; i.e., parallel interface (8255), seriai
interface (8251), timing (8253), interrupt control
(8259). However, as the speed and density of LSI
technology increased, more and more intelligence
was incorporated into the peripheral devices. This
allowed more specific application problems to be
solved, such flS floppy disk control (8271), CRT control (8275), and data link control (8273). The advantage to the system designer of this increased
peripheral device intelligence is that many of the peripheral control tasks are now handled externally to
the main processor in the peripheral hardware
rather than internally in the main processor software. This reduced main processor overhead results
in increased system throughput and reduced software complexity.
UPI-41 VB. UPI-41A
The UPI-41A is an enhanced verSion of the UPI-41.
It incorporates several architectural features not
found on the "non-A" device:
• Separate Data In and Data Out data bus buffer registers
• User-definable STATUS register bits
• ~mable master interrupts for the OBF
andIBFtlags
• Programmable DMA interface to external
DMA controller.I
In spite of the number of peripheral devices available, the pervasiveness of the microprocessor has
been such that there is still a l&rge number of periph- '
eral control applications not yet satisfied by dedicated LSI. Complicating this problem is the fact that
new applications are emerging faster than the manufacturers can react in developing new, dedicated peripheral controllers. To address this ptoblem, a new
microcomputer-based Universal Peripheral Interface (UPI-41A) device was developed.
, In essence, the UPI-41A acts as a slave processor to
the main system CPU. The UPI contains its own
processor;memory, and I/O, and is completely user
programmable; that is, the entire peripheral control
algorithm can be programmed locally in the UPI, instead of taxing the master processor's main memory.
This distributed processing concept allows the UPI
to handle the real-time tasks such as encoding' keyboar4s, controlling printers, or -multiplexing displays, while the main processor is handling non-realtime dependent tasks such as buffer management or
arithmetic. The UPI relies on the master only for
initialization, elementary commands, and data
transfers. ThiS, technique results in an overall increase in system efficiency since both processorsthe master CPU and the slave UPI-are working in
parallel.
The separate Data In (DBBIN) and Data Out
(DBBOUT) registers greatly simplify the master/
UPI protocol compated to the UPI-41. The master
need only check IBF before writing to DBBIN and
OBF befc;>re reading DBBOUT. No data bus buffer
lock-out is required.
The most significant nibble of the STATUS register,
undefmed in the UPI-41, is user-definable in UPI41A. It may be loaded dir8ctly from the most signifi·
cant nibble of the Accumulator (MOV STS,A).
These extra four STATUS bits are useful for transferring additional status information to the master.
This application note uses this feature extensively.
A new instruction, EN FLAGS, allows OiJF and IBF
to be reflected on PORT 2 BIT 4 and PORT 2 BIT 5
. respect~vely. nis feature enables interrupt-driven
data transfers when these pins are interrupt- sources
to the master.
By executing an EN DMA instruction PORT 2 BIT
6 becomes a DRQ (DMA Request) output and
PORT 2 BIT 7 becomes DACK (DMA Acknowledge). Setting DRQ requests a DMA cycle to an external DMA controller. When the cy;ele is gran~
the pMA. controller returns DACK plus either RD
(Read) or WR (Write). DACK automatically forces
This application note-presents three UPI-41A applications which are roughly divided into two groups:
applications whose complexity -and UPI code space
AFN-Ol538A
6-661
APPLICATIONS
·~r'
·~r
.3,---------,
USER RAM
32 X 8
7681-_ _ _ _ _.....
~~ 1 - - - - - - - - - - 4
BANK 1
5121-_ _ _ _ _.....
WORKING
-'r
I
DIRECTLY
REGISTERS
ADDRESSABLE
axa
WHEN BANK 1
IS SELECTED
~.
:;: 1 - - - - - -.....
ADDRESSED
8 LEVEL STACK
OR
INDfFlECTLV
THROUGH
USER RAM
16X8
(RO' OR R1')
R1 OR RO
LOCATION 7 - TIMER
~-::':6'~~~:rH~TORS
1-_ _ _ _ _..
PAGf!O
LOCATION 3 -
BANKO
WORKING
ISF
REGISTERS
I---:'_ _ _ _~.-g'~~:~ ~~HTORS
axa
DIRECTLY
ADDRESSABLE
WHEN BANK 0
ISSELECrD
Figure 1A.
Program Memory Map
Figure 1B.
CS and Ao low internally and clears DRQ. This selects the appro~te data buffer register (DBBOUT
for DACK and RD, DBBIN for DACK and WR) for
the DMA transfer. .
Data Mamory Map
Looking into. the UPI from the 8085A, the 8085A
sees only the three registers mentioned above. If the
8085A wishes to issue a command to the UPI, it does
so by writing the command to the DBBIN register
according to the decoding of Table 2. Data for the
UPI is also passed via the DBBIN register. (The UPI
differentiates commands and data by examining the
Ao pin. Just how this is done is covered shortly.)
Data from the UPIfor the 8085A is passed in the
DBBOUT register. The 8085A may interrogate the
UPI's status by reading the UPl's STATUS register.
Four bits of the STATUS register act as flags and
are used to handshake data and commands into and
out of theUPI. The STATUS register format is
sho~ in Figure 3.
Like the "non-A", the UPI-41A is available in both
RQM (8041A) and EPROM (8741A) Program Memory versions. This application note deals exclusively
with the UPI-41A since the applications use the "A"s
enhanced features.
UPI/MASTER PROTOCOL
As in most' closely coupled multiprocessor systems,
the various processors communicate via a shared resource. This shared resource is typically specific locations in RAM or in registers through which status
and data are passed. In the case of a master processor and a UPI-41A, the shared resource is 3 separate,
master-addressable, registers internal to the UPI.
These registers are the status register (STATUS),
the Data Bus Buffer Input register (DBBIN), and
the Data Bus Output register (DBBOUT). [Data
Bus Buffer direction is relative to the UPI]. To illustrate this registllr interface, consider the 8085A/UPI
system in Figure 2.
BIT 0 is OBF (Output Buffer Full). This flag indicates to the master when the UPI has placed data in
theDBBOUT register. OBF is set when the UPI
writes to DBBOUT and is reset when the master
reads DBBOUT. The master finds meaningful data
in the ~BBOUT register only when OBF is set.
The Input Buffer Full (IBF) flag is BIT 1. TheUPI
uses this flag as an indicator that the master has
written to the DBBIN register. The master usesIBF
6-662
APPLICATIONS
..
........
ST. . . .
~
MAS...
s,m..
INTERFACE
l
Wii
iii
Ci
..
,,""
is
CRYSTAl
Le," . {TAL'
CLOCK
POWER
"".U
{.... _
_
..... ..........,
Vss _ _ _
VCC_+5SUPPLV
figure 1C.
UPl-41A Block Diagram
to indicate when the UPI has accepted a particular
command or data byte. The master should examine
IBF before outputting anything to the UPI. IBF is
set when the master writes to DBBIN and is reset
when the UPI reads DBBIN. The master must wait
untilIBF=O before writing new data or coDunands
to DBBIN. Conversely, the UPI must ensure IBF=l
before reading DBBIN.
'
~t'"""~t'"""
~ ~
8085
FLAG 1 (Fl) is the final dedicated STATUS bit.
Like FO the UPI can set, reset, and test this flag.
However, in addition, Fl reflects the state of the Ao
pin whenever the master writes to the DBBIN register. The UPI uses this flag to delineate between master command and data writes to DBBIN.
The remaining four STATUS register bits are user
defmable. Typical uses of these bits are as.status in-
~~~~
gr- ~
t-t--
r- r
'-
The third STATUS register bit is FO (FLAG 0). This
is a general purpose flag that the UPI can set, reset,
and test. It is typically used to indicate a UPI error
or busy condition to the master.
Figure 2.
'
i=
......
r-
i'
.
.... 1
lUI
cs
lID
WR
1
STATUS
I
DIIBIN
I
I DB80UT I
Reg'" Interfece
dicators for individual tasks in a multitasking UPI
or as UPI generated interrupt status. These bits fmd
a wide variety of uses in the upcoming applications.
Looking into the 808SA from. the UPI, the UPI sees
the two DBB registers plus the IBF, OBF, and Fl
flags. The UPI can write from its accumulator to
DBBOUT or read DBBIN into the accumulator.
The UPI cannot read OBF, IBF, or Fl directly, but
these flags may be tested usmg conditional jump
~538A
APPLICATIONS
Table 1.
MDemoDlc
DescrlptioD
Instruction Set Summary
Byte. Cycle.
DescriptioD
Mnemonic
'Accumulator
Add register to A
Add date memory to A
Add immediate to A
Add register to A with carry
Add data memory to A with carry
Add immed. to A with carry
AND register to A
AND data memory to A
AND immediate to A
OR register to A
OR data memory to A
OR immediate to A
E%clusive OR register to A
Exclusive OR data memory to A
Exclusive OR immediate to A
IncrementA
Decrement A
Clear'A
Complement A
Decimal Adjust A
Swap digits of A
Rotate A left
Rotate A left through carry
Rotate A right
Rotate A right through carry
ADDA.R"
ADDA,@R"
ADDA,#date
ADDCA,Rr
ADDCA@R"
ADDC A,#data
ANLa,R"
ANLA,@R"
ANLA,#data
ORLA,R"
ORLA@Rr
ORLA,#data
XRLA.R"
XRLA.@R"
XRLA,#data
INCA
DEC A
CLRA
CPLA
DAA
SWAP A
RLA
RLCA
RRA
RRCA
1
1
2
1
1
2
1
1
2
1
1
2
1
1
2
1
1
1
1
1
1
1
I
I
I
1
1
2
1
1
2
1
1
2
1
1
2
1
1
INA,D B
OUTDBB,A
MOVSTS.A
MOVDA,P
MOVDP p•
ANLDPp.A
ORLDPp.A
Input port to A
Output A to port
AND immediate to port
OR immediate to port
Input DBB to A, clear IBF
Output A to DBB, set OBF
~ -A7 to Bits 4-7 of Status
Input Expander port to A
Output A to E%pander port
AND A to E%pander port
OR A to E%pander port
MOV A,R"
MOVA.@R"
MOVA,#data
MOVR",A
MOV@R".A
MOV R",#data
MOV @R".#data
MOVA,PSW
. MOVPSW.A
XCHA,R"
XCHA,@R"
XCHDA@R"
MOVPA.@A
MOVP3,A,@A
Move register to A
Move data memory to A
Move immediate to A
Move A to register
Move A to data memory
Move immediate to register
Move immediate to data memory
MovePSWtoA
MoveAtoPSW
E%change A and register
Exchange A and data memory
Exchange digit of A and register
Move to A from current page
Move to A from pege 3
OUTL~p.A
2
1
1
1
1
1
1
I
I
I
I
ANL Pp,#data
ORLP~#data
X
I
I
2
2
I
I
I
1
I
I
I
2
2
I
I
2
I
I
2
2
I
I
I
I
I
I
I
I
I
2
1
I
2
2
I
I
I
I
I
2
2
cs
0
0
ENDMA
ENI
DIS I
EN FLAGS
SELRBO
SELRBI
NOP
Enable DMA Handshake Lines
Enable IBF Interrupt
Disable IBF Interrupt
Enable Master Interrupts
Select register bank 0
Select register bank I
No Operation
INCR"
INC@R"
DECR"
Increment register
Increment data melllory
Decrement register
CALLaddr
RET
RETR
Jump to subroutine
Return
Return and restore status
CLRC
CPLC
CLRFO
CPLFO
CLRFI
CPLFI
Clear Carry
Complement Carry
Clear FlegO
Complement Flag 0
Clear Fl Fleg
Complement FI Fleg
JMPADDR
JMPP@k
DJNZ R,addr
JC addr
JNC addr
JZaddr
JNZaddr
JTOaddr
JNTOaddr
JTI addr
JNTI addr
JFOaddr
JFI addr
JTF addr
JNIBF addr
JOBF addr
JBbaddr
Jump unconditional
Jump indirect
Decrement register and skip
Jump on Carry-I
Jump.on Carry-O
Jump ob'A Zero
Jump on A not Zero
Jump onTO-I
I
1
I
I
1
1
I
I
I
I
I
1
I
I
I
I
1
I
I
I
I
I
I
1
I
I
I
I
I
I
1
1
I
2
I
2
1
Subroutine
1
2
2
I
I
1
I
I
1
I
I
1
1
I
I
2
I
2'
2
. 2
2
2
2
2
2
2
2
2
2
2
:I
2
2
2
2
2
2
2
2
Flags
2
2
I
I
I
2
2
BraDch
2
2
JumponTO~O
JumponTI=1
Jump on TI=O
Jump on FO Flag-I
Jump on FI Flag=l
Jump on Timer Flag-l;Clear Flag
Jump on IBF FIeg=O
Jump on OBF FIeg-1
Jump on Accumulator Bit
2
2
2
2
2
2
2
2
2
2
Reglater Decoding
AO 1m VIR
0
0
1
0
0
1
0
1
1
1
0
0
1
X
X
X
Q
Read Timer/Counter
Loed Timer/Counter
Start Timer
Start CQunter
Stop Timer/Counter
Enable Timer/Counter Interrupt
Disable Timer/Counter Interrupt
Reglstera
Data Moves
. Table 2.
MOVA,T
MOVT,A
STRTT
STRTCNT
STOPTCNT
ENTCNTI
DISTCNTI
CODtrol
IDput/Output
IN A;P
Bytes Cycles
Tim"r/CouDter
1
REGISTER
511411
211~1)
...
I
i
READDBBOUT
READ STATUS
WRITE DBBIN (DATA)
WRITE DBBIN (COMMAND)
NO ACTION
.
OBF ISF -
DSSOUT FULL
[)BstN FULL
' - - r - - FO - FLAG 0
' - - - ' - - - - Fl - FLAG 1
' - - - - - - - - - USER DEFINED
STATUS REGISTER
Figure 3.
Statue Reglater Format
AFN-Ol536A
6-664
APPLICATIONS
instructions. The UPI should make sure that OBF is
reset before writiDg new data into DBBOUT to ensure that the master baa read previous ,DBBOUT
data. IBF should also be tested before reading
DBBIN since DBBIN data is valid only when IBF is
set. As was mentioned earlier, the UPI uaea Fl to differentiate between command and data contents in
DBBIN when IBF is set. The UPI may also write the
upper 4-bits of its accumulator to the upper 4-mts of
the STATUS register. These bits are thus user
definable.
The UPI can teat the flags at any time during its·internal program execution. It eaaentially "polla" the
STATUS regiater for changes. If faster response is
needed to master commands and data, the l)'Pl's internal interrupt structure can be used. If IBF interrupts are enabled, a master write to DBBIN (either
command or data) sets IBF whjch generates an internal CALL to location 03H in program memory. At
this point, working register contents can be saved
using bank switching, the accumulator saved in a
spare working register, and the DBBIN register read
and serviced. The interrupt logic for the IBF interrupt is shown in Figure 4. A few observations concerning this logic are appropriate. Note that if the
master writes to DBBIN while the UP! is still servicing the last IBF interrupt (a RETR instruction baa
not been executed), the IBF Interrupt Pending line
is made high which cauaea a new 'CALL to 03H as
soon as the lint RETR is executed. No EN I (Enable
Interrupt) instruction is needed to rearm the interrupt logic as is needed in an 8080 or 808SA system;
the RETR performs this function. Also note that executiDg a DIS I to disable further IBF interrupts
does not ~lear a pending interrupt. Only a CALL to
location 03H or RESET clears a pending IBF interrupt.
Keeping in mind that the actual masterlUPl protocol is dependent on the application, probably the
best way to illustrate correct protocol is by example.
Let's consider using the UPI as a simple parallel I/O
device. (This is a trivial application but it embodies
all of the important protocol considerations.) Since
the UPf may be either interrupt or non-interrupt
driven internally, both cases are considered.
Let's take the easiest configuration lint; using the
UPI PORT 1 as an 8-bit o.utput port. From the UPI's
point-of-view, this is an input-only application since
all that is required is that the UPI input data from
the master. Once the master writes elata to the UPI,
the UPI reads the DBBIN register and transfers the
data to PORT 1. No testing for commands versus
data is needed since the UPI "knows" it only performs one task-no commands are needed.
FORCE
INTERRUPT
CALL
RESET
DISTCNTI
EXECIITED
-
nlER
ENABLE
Wii
cs
RESET
IBF INTEIIIM'T
CALL EXECU'TED
RESET
DIS I
EXECUTED
IBF INTERRUPT
ENABLE
Figure 4.
UPJ.41A Interrupt Structure
APPLICATIONS
Non-interrupt driven UPI software ill shown in Figure 5A while Figure 5B shows interrupt based softW8xe. For Figure 5A, the UPI simply waits until it
, sees IBF go high indicating the master has written a
data byte to DBBIN. The UPlthen reads DBBIN,
transfers it to PORT 1, and returns to waiting for the
next data. For the interrupt-driven UPI, Figure 5B,
once the EN I instruction is executed', the UPI simply waits for the IBF interrupt before handling the
data. The UPI could handle other tasks during this
waiting time. When the master writes the data to
DBBIN, an IBF interrupt is generated which performs a CALL to location 03H. At this point the UPI
reads DBBIN (no testing of IBF is needed since an
IBF interrupt implies that IBF is set), transfers the
data to PORT 1, and executes an RETR which returns program flow to the main program.
Software for the master 80SSA is included in Figure '
5C. The only requirement for the master to output
data to the UPI is that it check the UPI to be sure
the previous data had been taken before writing new
data. To accomplish this the master simply reads the
STAtUS register looking for IBF=O before writing
the next data.
Figure 6A illustrates the case where UPI PORT 2 is
used as an 8-bit input port. This COnfiguration is
termed UPI output-only as the master does not
write (input) to the UPI but simply reads either the
STATUS or the DBBOUT registers. In this example
only the OBFflag is used. OBF signals the master
that the UPI has placed new port data in DBBOUT.
The UPI loops testing OBF. When OBF is clear, the
master has read the previous data and' UPI then
reads its input port (PORT 2) and places this data in
DBBOUT. It then waits on OBF until the master
reads DBBOUT before reading the input port again.
When the master wishes to read the input port data,
Figure 6B, it simply checks for OBF being set in the
STATUS register before reading DBBOUT~ While
this technique illustrates proper protocol, it should
be noted that it is not meant to be a good method of
using the UPI as an input port since the master
would never get the newest status of the port.
: UPI OUTPUT ONLY EXAMPLE-PORT 2 USED AS INPUT PORT
PORT DATA IS AVAILABLE IN DBBOUT
RESET:
JOBF
IN
OUT
JMP
; LOOP IF OBF=1 (DATA NOT READ)
; DBBOUT CLEAR. READ PORT
; TRANSFER PORT DATA'TO DBBOUT
,; WAIT FOR MASTER TO READ DATA
RESET
A.P2
DElB.A
RESET
Figure 6A.
Single 'nput Port Example
; UPIINPUT ONLY EXAMPLE-PORT 1 USED AS OUTPUT PORT
UPI POLLS IBF FOR DATA
RESET'
JNIBF
IN
OUTL
JMP
RESET
A.DBB
P1.A
RESET
; WAIT ON IBF FOR INPUT
; INPUT THERE. SO READ IT
; TRANSFER DATA TO PORT 1
; GO WAIT FOR NEXT DATA
.8085 SOFTWARE FOR UPI OUTPUT-ONLY EXAMPLE
INPUT DATA RETURNED IN'REG, A
UPIIN:
Figure 5A.
Single Output Port Example-Polling
IN
ANI
JZ
IN
RET
STATUS
OBF
UPIIN
DBBOUT
, Figure 6B.
; READ UPI STATUS
; LOOK AT OBF
; WAIT UNTIL OBF= 1
; READ DBBOUT
; RETURN WITH DATA IN A
8OS5A Single Input Port Code
; UPIINPUT ONLY EXAMPLE-PORT 1 USED AS OUTPUT PORT
DATA INPUT IS INTERRUPT·DRIVEN ON IBF
RESET:
IBFINT:
EN
I
JMP
RESEH1
IN
A.DBB
OUTL P1.A
RETR
Figure 5B.
; ENABLE IBF INTERRUPTS
; LOOP WAITING FOR INPUT
; READ DATA FROM DBBIN
; TRANSFER DATA TO pORT 1
; RETURN WITH RESTORE
Single Output Port 'Example-Interrupt
; 8085 SOFTWARE FOR UPIINPUT·ONL Y EXAMPLE
DATA FOR OUTPUT IS PASSED IN REG. C
UPIOUT: IN
ANI
JNZ
MOV
OUT
RET
Figure 5C.
STATUS
IBF
UPIOUT
A.C
DBBIN
; READ UPI STATUS
; LOOK AT IBF
; WAIT FOR IBF =0
; GET DATA FROM C
; OUTPUT DATA TO DBBIN
; DONE. RETURN
8085A Code for Single Output Port Example 1
.
The above examples can easily be combined. Figure
7 shows UPI software to use PORT 1 as an output
port simultaneously with PORT 2 as an input port.
The program starts with the UPI checking IBF to
see if the master has written data destined for the
output port into DBBIN. If IBF is set, the UPI reads
DBBIN and transfers the data to the output port
(PORT 1). If IBF is not set or once the data is transferred ,to the output port if it was, OBF is tested. If
OBF is reset (indicating the master has read
DBBOUT), the inp\lt port (PORT 2) is read and
transferred to DBBOUT. If OBF is set, the master
has yet to read DBBOUT so the program just loops
back to test IBF.
The master software is identical to the separate
input/output examples; the master must test IBF
AF~I536A
6-666
APPLICATIONS
; UPIINPUT I OUTPUT EXAMPLE-PORT 10UTPUT, PORT 2 INPUT
RESET:
oun:
JNIBF
IN
OUlL
JOBF
IN
OUT
JMP
Figur. 7.
OUT 1
A, DBB
P1, A
RESET
A, P2
DBB,A
RESET
; IF IBF .. O, DO OUTPUT
; IF IBF-1, READ DBBIN
; TRANSFER DATA TO PORT 1
; IF OBF-1, GO TEST IBF
; IF OBF-O, READ PORT 2
; TRANSFER PORT DATA TO DBBOUT
; GO CHECK FOR INPUT
Combination Output/Input Port Example
and OBF before writing output port data into
DBBIN or before reading input port from DBBOUT
respectively.
In all of the three examples above, the UPI treats
information from the master solely as data. There
has been no need to check ifDBBIN information is a
command rather than data since the applications do
not require commands. B~t what if both PORTs 1
and 2 were used as output ports? The UPI needs to
know into which port to put .the data. Let's use a
command to select which port.
Recall that both commands and data pass through
DBBIN. The state of the Ao pin at the time of the
write to DBBIN· is used to distinguish commands
from data. By convention, DBBIN writes with Ao=O
are for data, and those with Ao=1 are commands.
When DBBIN is written into" F1 (FLAG 1) is set to
the state of Ao. The UPI tests F1 to determine if the
information in the DB BIN register is data or
command.
: UPI DUAL OUTPUT PORT EXAMPLE-BOTH PORT 1 AND 2 OUTPUTS
COMMAND SELECTS DESIRED PORT
WRITE PORT 1-0000 0010 (02H)
WRITE PORT 2-0000 0100 (04H)
FLAG 0 USED TO REMEMBER WHICI'I PORT WAS SELECTED
. BY LAST COMMAND.
RESET:
JNIBF
IN
JF1
JFO
OUTL
JMP
PORT2: OUTL
JMP
CMD:
JB1
JB2
JMP
PT1:
CLR
JMP
PT2:
CLR
CPL
JMP
RESET
A,DBB
CMD
PORT2
P1,A
RESET
P2,A
RESET
PT1
PT2
RESET
FO
RESET
FO
FO
RESET
Figura SA.
; WAIT FOR MASTER INPUT
; READ INPUT
; IF F1-1, COMMAND INPUT
; INPUT IS DATA, TEST FO
; FO-O, SO OUTPUT TO PORT 1
; WAIT FOR NEXT INPUT
; FO"1, SO OUTPUT TO PORT 2
; WAIT FOR NEXT INPUT
; TEST COMMAND BITS (BIT 1)
; TEST BIT 2
; NEITHER BIT SET, WAIT FOR INPUT
; PORT 1 SELECTED, CLEAR FO
; WAIT FOR INPUT
; PORT 2 SELECTED, SET FO
; WAIT FOR INPUT
Dual Output Port Ex~mpl.
Initially, the UPI simply waits until IBF is set indicating the master has written into DBBIN. Once
IBF is set, DBBIN is read and F1 is tested for a command. If F1 =1, the DBBIN byte is a command. Assuming a' command, BIT 1 is tested to see if the
command selected PORT 1. If so, FO is cleared and
the program returns to wait for the data. If BIT 1=0,
BIT 2 is tested. If BIT 2 is set, PORT 2 is selected so
FO is set. The program then loops back waiting for
the next master input. This input is the desired .port
data. If BIT 2 was not set, FO is not changed and no
action ill taken.
For the case of two output ports, let's assume that
the master selects the desired port with a command
prior to writing the data. (We could just use F1 as a
port select but that would not illustrate the subtle
differences between commands and data). Let's define the port select commands such that BIT 1=1 if
the next data is for PORT 1 (Write PORT 1=0000
0010) and BIT 2=1 if the next data is for PORT 2
(Write PORT 2=0000 0100). (The number of the set
bit selects the port.) Any other bits are ignored..This
assignment is completely arbitrary; we could use any
command structure, but this one has the advantage
of being simple.
When IBF=1 is again detected, the input is again
tested for command or data. Since it is necessarily
data, DBBIN is read and FO is tested to determine
which port was previously selected. The data is then
output to that port, following which the program
waits for the next input. Note that since FO still selects the previous port, the next input could be more
data for that port. The port selection command
could be thought ohs a port select flip-flop control;
once a selection is made, data may be repeatedly
written to that port until the other port is selected.
Master software, Figure SB, simply must check IBF
before writing either a command or data to DBBIN.
Otherwise, the master software is straightforward.
Note that the'UPI must "remember" from·DBBIN
write to write which port has been selected. Let's use
FO (FLAG 0) for this purpose. If a Write PORT 1
command is received, FO is reset. If the command is
Write PORT 2, FO is set. When the UPI finds data in
DBBIN, FO is intel.Togated and the data is loaded
into the previously selected port. The UPI software
is shown in Figure SA.
For the sake of completeness, UPI software for implementing two input ports is given in Figure 9. This
case is simpler than the dual output case since the
UPI can assume that all writes to DBBIN are port
selection commands so no command/data testing is
required. Once the Port Read command is input, the
selected port is read and the port data is placed in /
DBBOUT. Note that in this case FO is used as a UPI
AFN.o1536A
6-667
APPLICATIONS
error indicator. If the master happened to issue an
invalid command (a coDlmand without either BIT 1
or 2 set), FO is set to notify the master that the UPI
did not know how to interpret the command. FO is
also set if the master commanded a port read before
it had read DBBOUT from the previous command.
The UPI simply tests OBF just prior to loading
DBBOUT and if OBF=I, FO is set to indicate the
error.
All of the above examples are, in themselves, rather
trivial applications of the UPI although they could
easily be incorporated as one of several tasks in a
UPI handling multiple small tasks. We have covered
them primarily to introduce the UPI concept and to
illustrate some master/UPI protocol. Before moving
on to more rea1iatic UPI applications, let~s discuss
two UPI features that do not directly relate to the'
master/UPI protocol but greatly enhance the UPfs
transfer capability.
In addition to the OBF and IBF bits in the STATUS
register, these flags can also be made available directly on two port pins. These port pins can then be
used as interrupt sources to the master. ByexecutiJ)g an EN FLAGS instruction, PORT 2 pin 4 reflects the condition of OBF and PORT 2 pin 5
reflects the inverted condition of IBF (IBF). These
dedicated outputs can then be enabled or disabled
via their respective port bit values; i.e., P24 reflects
OBF ~ l~ng as an instruction is executed which sets
P24 (i.e. ORL P2,#10H). The same action applies to
the IBF output except P25 is used. Thus P24 may
serve as a DATA AVAILABLE interrupt output.
Likewise for P25 as a READY-TO-ACCEPT-DATA
interrupt. This greatly simplifies interrupt-driven,
master-slave data transfers,
; IlO85 SOFTWARE FOR DUAL OUTPUT PORT EXAMPLE
lltS ROUTINE WRITES DATA IN REG, C TO PORT I
(SAME ROUTINE F9R ~ORT 2-JUST C~E COMMAND)
PORTI: IN
ANI
JNZ
MVI
PI'
OUT
IN
ANI
JNZ
MaV
OUT
RET
figure 88.
S:rATUS
IEIF
PORTI
A,OOOOOOI08
UPICMD
STATUS
IBF
PI'
A, C
DBBIN
; READ'UPI STATUS
; LOOKATlBF
; WAIT UNTIL IBF*O
; LOAD'WRITE PORTI CMD
; OUTPUT TO UPI COMMAND PORT
; READ UPI STATUS AGAIN
;"LOOK AT> IBF
,
, WAIT UNTIL COMMAND ACCEP;TED
; GET DATA FROM C
; OUTPUT TO DBBIN
; DONE, Rf"JRN
8085A Dual OUtput Port Example Code
TheUPI also supports a DMA transfer interface. If
an EN DMA'instruction is executed, PORT 2 pin 6
becomes a DMA: Request (DRQ) output ana P27 becomeB' a high impedanee, DMA Acknowledge
; UP! DUAL INPUT PORT EXAMfi(E-SOTH PORT l' AND 2 INPUTS
COMMAND SELECTB WHICH PORT IB TO BE READ
FLAG 0 UBED AS ERROII'FLAG
RESET: JNlBF RESET
CLR FO
IN
JBl
JB2
A,DBB
PTI
PT2
ERROR:' CPa.
JMP
PTl,
IN
JOBF
OUT
JMP
,
PT2:
FO
RESET
A, PI
ERROR
DBB,A
RESET
IN
A. P2
JOBF ERROR
OUT DBB. A
JMP RESET
; WAIT FOR INPUT
, ; CLEAR ERROR FLAG
; READ INPUT (COMMAND)
; 'feST BIT 1 (PORT 1)
; TEST err 2 (PORT 2) ,
; ERROR-COMPLEMENT FO
; WAIT FOR INPUT
; READ PORT I
; TEST OBF BEFORE LOADING DBSOUT
; LOAD PORT 1 DATA INTO DBBOUT
; WAIT FOR INPUT
; READ PORT 2
; TEST OSF BEFORE LOADING DBSOUT
; LOAD PORT 2 DATA INTO DBSOUT
; WAIT FOR INPUT
Figure 9. Dual Input Port Example
(DJ\CK) input. Any instruction which would normally set P26 now sets Drul: DR~ cleared when
DACK is low and either RD or WR is low. When
DACK is low, CS and AO are forced low internally
which allows data bus transfers between OaBOUT
or DBBIN to occur, depending upon whether WR or
RD is true. Of course, the function requires the use
of an external DMA controller.
Now that we have discussed the aspects of the UPI
protocol and data transfer interfaces, let's move on
to the actua1 applications.
EXAMPLE APPLICAnONS
Each of the following three sections presents the
hardware and software details of a UPI application.
Each application utilizes one of the protocols mentioned in the last section. The rll'St example is a sim.pie 8-digit LlID display controller. This application
requires only that the UPI pe~orm input operations
from the DBBIN; DBBOUT is not qsed. The reverse
is true for the second application: a sensor matrix
controller. The final application involves both
DBBOUT ,and DBBIN operations: a combination
seria1/parallell/O device.
.'
,
The core master processor system with which these
applicati~nswere developed is ~e iSBC SO/30 single
board computer. nis board provides an especially
convenient UPI environment since it contains a
dedicated socket specifically interfaced for the UPI41A. The SO/30 uses the 8085A as the master processor. The I/O and peripheral complement on the
SO/30 include 12 vectored priority interrupts (8 on
lin 8259 Programmable Interrupt Controller and 4
on the 8085A itself), an 8253 Programmable Interval
Timer supplying three I6-bit programmable timers
(one is dedicated as a programmable baud rate generator), 'a high speed serial, channel provided by a
8251 Programmable USART, and 24 parallel I/O
APPLICATIONS
lines implemented with an 8255A Programmable
Parallel Interface. The memory complement contains 16K bytes of RAM using 211716K bit Dynamic
RAMs and the 8202 Dynamic RAM Controller, and
up to 8K bytes of ROM/EPROM with sockets compatible with 2716, 2758, or 2332 devices. The SO/30's
RAM uses a dual port architecture. That is, the
memory can be considered a global system resource,
accessible from the on-board S085A as well as from
remote CPUs and other devices via the
MULTIBUS. The SO/30 contains MULTIBUS controllogic which allows up to 16 SO/30s or other bus
masters to share the same system bus. (More detailed information on the iSBC 80/30 and other
iSBC products may be found in the latest Intel
Systems Data Catalog.)
A block diagram of the iSBC SO/30 is shown in Figurel0. Details of the UPI interface are shown in Figure 11. This interface decodes the UPI registers in
the following format:
Register
Operations
Read STATUS
Write DBBIN (command)
Read DBBOUT (data)
Write DBBIN (data)
INE5H
OUTE5H
INE4H
OUTE4H
processing, go update the display, and then return to
its normal flow. This extra burden is ideally handled
by a UPI. The master CPU could simply give characters to the UPI and let the UPI do the actual segment decoding, display multiplexing, and
refreshing.
As an example of this technique, Figure 13 shows the
UPI controlling an 8-digit LED display. All digit
segments are connected in parallel and are driven
through segment drivers by the UPI PORT 1. The
lower 3 bits of PORT 2 are inputs to a 3-to-8 decoder
which selects an individual digit through a digit
driver. A fourth PORT 2 line is used as a decoder
enable input. The remaining PORT 2 lines plus the
TEST 0 and TEST 1 inputs are available for other
tasks.
Internally, the UPI uses the counter/timer in the interval timer mode to define the interval between display refreshes. Once the timer is loaded with the
desired interval and started, the UPI is free to handle other tasks. It is only when a timer overflow interrupt occurs that the UPI handles the short
display multiplexing routine. The display multiplexing can be considered a background task which is entirely interrupt-driven. The amount of time spent
multiplexing is such that there is ample time to handle a non-timer task in the UPI foreground. (We'll
discuss this timing shortly.)
8-Digit Multiplexed LED Display
The traditional method of interfacing an LED display with a microprocessor is to use a data latch
along with a BDC-to-7-segment decoder for each
digit of the display. Thus two ICs, seven current
limiting resistors, and about 45 connections are required for each digit. These requirements are, of
course, multiplied by the total number of digits desired. The obvious disadvantages of this method are
high parts count and high power dissipation since
each digit is "ON" continuously. Instead, a scheme
of time multiplexing the display can be used to decrease both parts count and power dissipation.
When a timer interrupt occurs, the UPI turns off all
digits via the decoder enable. The next digit's segment contents are retrieved from the internal data
memory and output via PORT 1 to the segment
drivers. Finally, the next digit's location is placed on
PORT 2 (P20-P22) and the decoder enabled. This
displays the digit's segment information until the
next interrupt. The timer is then restarted for the
next interval. This process continues repeatedly for
each digit in sequence.
Display multiplexing basically involves connecting
the same segment (a, b, c, d, e, f, or g) of each digit in
parallel and driving the common digit element (an~
ode or cathode) of each digit separately. This is
shown schematically in Figure 12". The'various digits
of the display are not all'on at once; rather, only one
digit at a time is energized. As each digit is energized, the appropriate segments for that digit are
turned on. Each digit is enabled in this way, in sequence, at a rate fast enough to ensure that each
digit appears to be "ON" continuously. This implies
that the display must be "refreshed" at periodic intervals to keep the digits flicker-free. If the CPU had'
to handle this task, it would have to suspend normal
As. a prelude to discussing the UPI software, let's examine the internal data memory structure used in
this application, Figure 14. This application requires
only 14 of the 64 total data memory locations. The
top eight locations are dedicated to the Display
Map; one location for each digit. These locations
contain the segment and decimal point information
for each character. Just how characters are loaded
into this section of memory is covered shortly. Register R7 of Register Bank 1 is used as the temporary
Accumulator store during the interrupt service
routines. Register Ra stores the digit number of the
next digit to be displayed. R2 is a temporary storage
register for characters during input routine. Ro is
6-669
APPLICATIONS
USER DESIGNATED
PEIIIPHERALS
42 PROGRAMMABLE
PARALLEL J/O LINES
"S232C
COMPATIBLE
DEVICE
POWEAFAIL
INTE.......
41NTE.....T
REQUEST UNES
.INTE.......
REQUESTUt-ES
8 INTERRUPT
REQUEST LINES
16K X 8
RAM
2117
MULTlBUSno
Figure ~O.
ISBC 80/30 Block Diagram
the offset pointer pointing to the Display Map location of the next digit. That makes 12 locations so far.
The remaining two locations are the two stack locations required to store the return address plus status
during the timer and input interrupt service
routines. The remaining unused locations, all of
. Register Bank 0, 14 bytes of stack, 4 in Register
Bank 1, and 24 general purpose RAM locations, are
all available for use by any foreground task.
The UPI software consi~t~ of only three sl).ort
routines. One, .INIT, is' used ,strictly duri~g
initialization. DISPLA is the mqltiplexing routine
called at ,a timer interrupt. INPUT is the character
input handler called at an IBF interrupt. The flow
6-670
charts for these routines are shown in Figures 14A
through 14C.
INIT initializes the UPI by simply turning off all,
segment and digit drivers, filling the Display Map
with blank characters, loadi~g and starting the
timer, and enabling both til!ler and IBF interrupts.
Although the flow. chart shows the program loopiIlg
at this point, it is here that the code for any foreground task is inserted. The only restrictions on this
foreground task are that it not use I/O lines dedicated to the display and that it not require dedicated
,use of the timer. It could share the timer' if precautions are taken to ensure that the,display will still be ,
refreshed at the required interval.
i
'
APPLICATIONS
+sv
VDO
;ow
P10
WR
P11
iOA
"D
RESET
P1a
"'SET
..••
Aa
AO
PlO
CO
01
POIIT 1
A1
P1'
Aa
P1S
.20S
M As
E1
P1.
iiA'i
Ai As
E'
P17
E.
TO
10 PORT
TESTO
CONTROL,
EO
DATA
E.
TEST 1
+SV
55
8041A
8741A
EA
"
T1
32
0
••
0
....
EVENT CLOCK (8253)
~l~a.a
~CHANNEL
80851NTR
pa.
D0-
D7
08'
'"
P2'
+SV
• ao
P"
...
+SV
PORT 2
pa•
P2S
-
5.5296
pa.
XTAL 1
XTAL2
Figure 11.
P27
vss \
UPllnterface on iSBC 80/30
+5V
Figure 12.
LED Multiplexing
AFN-01536A
6-671
~PPUCATIONS
+ 5V
E3
E2
3
PORT 2/
,.c
00
01
02
8205 03
.,
E1
.2
O'
05
06
AO
07
~
~
~
"'"'
DIGIT
DRIVERS
8041A1
8741A
PORT 1
SEGMENT
DRIVERS
Figure 13.
UPI Controlled a-Digit LED Display
63
INIT
DISPLAY MAP
8x8
INITIALIZE
REGISTERS
USER RAM
24 X 8
(NOT USED)
31
ACCUMULATOR STORE
NOT useD
2.
R6
NOT USED
R5
NOT USED
R'
DIGIT COUNTER
R3
TEMPORARY STORE
R2
NOT USED
R1
DISPlAY MAP POINTER
TURN OFF ALL
DRIVERS
R7
FILL DISPLAY MAP WITH
BLANK CHARACTERS
REGISTER
BANk 1
CLEAR DIGIT COUNTER
LOAD AND START
TIMER
RO
23
STACK
16 x 8
UNUSED
8x8
ENABLE TIMER AND
ISF INTERRUPTS
REGISTER
BANK 0
WAIT LOOP OR
FOREGROUND TASK CODe
Figure 14.
Figure. 14A.
LED Display Controller Data Memory
Allocation
INIT Routine Flow
AFN.o1536A
6-672
APPLICATIONS
oiSPLA
SWITCH TO A81
SAVE ACCUMULATOR
IWnCHTOM1
IA.. - . . . _
MADAJID . . . _
TURH OFF AU DIGIT
DRIVERS
UPDATE DiSPLAY
MAP POINTER
GET SEGMENT INFO
FROM DISPLAY MAP
OUTPUT TO SEGMENT
DR1VERS
TURN ON DIGIT
ORtVER
Figure 148.
INPUT RoutIne Flow
LOAD AND START TIMER
The INPUT routine handles the character input. It
is called when an IBF interrupt occurs. After the
usual swapping· of register banks and saving of the
accumulator, DBBIN is read and stored in register
R2. DBBIN contains the Display Data Word. The
format for this word, Figure 15, has two fields: Digit
Select and Character Select. The Digit Select field
selects the digit number into which the character
from the Character Select field is placed. Notice that
the character set is not limited strictly to numerics,
some alphanumeric capability is provided. Once
DBBIN is read, the offset for the selected digit is
computed and· placed in the Display Map Pointer
Ro. Next the segment information for the selected
character is found through a look~up table starting
in page 3 of the program memory. This segment information is then stored at the location pointed at by
the Display Map Pointer. If the Character Select
field specified a decimal pOint, the segment corresponding to the decimal point is ANDedinto the
present segment information for that digit. After the
accumulator is restored, execution is returned to the
main program.
The DISPLA routine simply implements the
multiplexing actions described earlier. It is called
whenever a timer interrupt occurs. After saving pre-
RESTORE ACCUMUlATOR
RETURH
Figure 14C.
DISPLA Routine Flow
interrupt status by switching register banks and
storing the Accumulator, all digit drivers are turned
off. The Display Map Pointer is then updated using
the Current Digit Register to point at that digit's
segment information in the Display Map. This information is output to. PORT 1; the segment drivers.
The number of the current digit, R3" is then sent to
the digit select dkoder and the decoder is enabled.
This turns on the current digit. The digit counter is
incremented and tested to see if all eight digits have
been refreshed. If so, the digit counter is reset to
zero. If not, nothing is done. Finally, the timer is
10aded and restarted, the Accumulator is restored,
and the routine returns execution to the main program. Thus DISPLA refreshes one digit each,time it
is CALLed by the timer interrupt. The digit remains
on until the next time DISPLA is executed.
The UPI software listing is included as Appendix
AI. Appendix A2 shows the 8085A test routine used
AfN.Ol536A
6-673
APPLICATIONS
DISPLAY OATA WORD
716151413121'101
-~
DIGIT SElECT
7
5
0
0
,0
0
0
0
6
DIGIT
,
,, ,,
0
2
3
4
5
6
7
0
,
, ,
,, , ,
0
0
0
)
0
With the UPI ~niling at 5.5296 MHz, the instruction cycle time is 2.713 I's. The DISPLA routine requires 2S instruction cycles, therefore, the routine
executes in 76 1'8. Since DISPLA is CALLed 400
times/sec, the tota:l time spent refreshing the display
during one second is then 30 ms or 3 % of the tota:l
UPf time. This leaves 97.0% for any foreground
tasks that could be added.
8
1
CHARACTER SELECT
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
,
,,
,
,,
,
,,
,
,
,,
,,
,
,,
,
,
,
0
0
0
0
0
0
0
0
,
,,
,
,, ,,,
,,
Figure 15.
,
0
, ,
,
, ,
,, , ,
, , ,
,
,
,
,
,,, , ,
, ,
,
,
,
,, ,,
,, ,, ,
,
,
, ,
,, ,
,, ,, ,
0
0
0
0
L1
0
i?
0
0
0
0,
0
0
0
0
0
0
I
i
,
)
0
8
q
0
R
0
0
0
0
0
0
0
0
While the basic UPI software is useful' just as it
stands, there are several enhancements that could be
incorporated depending on the application. Auto-incrementing of the digit location could be added to
the input routine to alleviate the need for the master
to keep track of digit numbers. This could be (optionally) either right-handed or left-handed entry a
la TI or HP ca:lculators. The character set could be
easily modified by simply changing the lookup table.
The display could be expanded to 16 digits a:t .the
expense of one additiona:l PORT 2 digit select line,
the replacement of the 3-to-S decoder with a 4-to-16
decoder, and 8 more Display Map locations.
,
•
0
0
0
0
0
0
0
0
CHAR
0
b
[
d
0
E
1
F
0
0
"
0
J
H
I
L
0
n
0
p
0
t
0
0
If we assume a 50 Hz refresh rate and an 8-digit display, this means the DISPLA routine must be
CALLed 50X8 or 400 times/sec. This transfers, using
the timer interva:l of 87 p,$ at 5.5296 MHz, to a timer
count of 227. (Reca:ll from the UPI-41A User's Manual that the timer is an'"8-bit up-counter".) Hence
the TIME equate of 227D in the UPI listing. Obviously, different frequency sources or display lengths
would require that this equate be modified.
0
Now let's mov~ on to a slightly more cfJmplex application that is UPI output-only-a sensor matrix
controller.
. .",
"
LI
"
0
,
Sensor Matrix Controller
blank
LED Display Controller Display Data
Word Format
'
to display the contents of a displa:y buffer on the display. The S085A software takes care of· the display
digit numbering. Since the application is input-only
for the UPI, the .only protocol required is that the
master must test IBF before writing a Display Data
Word int.o DBBIN.
'
On the iSBC SO/30, the UPI frequency is at 5.5296
MHz. To obtain-a flicker-free display, the whole display must be refrl'shed at a rate of 50 Hz.or greater.
Quite often a microprocessor systllm is ca:l~d UP.on
to read the status .of aJarge number of simple SPST
switches .or .sens.or,s. This is especially true in a pr.ocess or industria:l control ,environment. Alarm sy.stems are als.og.o.od el'amples .of systems,with a ~arge
senSfJr populati.on. Ift\le number of sensors is sma:ll,
it ,might be reas.o~ble ~Q dedicate a !1ingle input port
pin f.or each sensor. Ho~ever, as the number .of sensqrs increase, thie technique bec.omes, very wasteful.
A. better arrangement.is to c.onfigure the sensors in a
matrix .organizati.on like that sh.own in Figure 16.
This arrangement .of 16 sensors requires only 4 input
and 4 output lines; half the number needed if dedicated inputs were,ul\ed. The line saving bec.omes
even m.ore substantial as the number of sens.ors
increases."
AFN-O'538A
6-674
APPLICATIONS
In Figure 16, the basic operation of the matrix involves scanning individual row select lines in sequence while reading the column return lines. The
state of any particular sensor can then be determined by decoding the row and column information.
The typical confIguration pulls up the column return lines and the selected row is held low. Deselected rows are held high. Thus a return line remains high for an open sensor on the selected row
and is pulled low for a closed sensor. Diode isolation
is used to prevent a phantom closure which would
occur when a sensor is closed on a selected row and
there are two or more closures on a deselected row.
Germanium diodes are used to provide greater noise
margin at the return line input.
3+ V
2 +v
'+v
If the main processor was required to control such a
matrix it would periodically have to output at the
row port and then read the column return port. The
proceBBor would need to maintain in memory a map
of the previous state of the matrix. A comparison of
the new return information to the old information
would then be made to determine whether a sensor
change had occurred. Any changes would be processed as needed. A row counter and matrix map
pointer also require maintenance each scan. Since in
most applications sensors change very slowly compared to most processing actions, the processor
probably would scan the rows only periodically with
other tasks being proceBBed between scans.
Rather than require the processor to handle the
rather mundane tasks of scanning, comparing, and
decoding the matrix, why not use a dedicated proceBBor? The UPI is perfect.
O+v
Figure 17 shows a UPI cOnIlgUration for controlling
up to 128 sensors arranged in a 16X8 matrix. The 4to-16 line decoder is used as the row selector to save
port pins and provides the expansion to 128 sensors
over the maximum of 64 sensors if the port had been
used directly. It also helps increase the port drive capability. The column return lines go directly into
PORT 1. Features of this design include complete
matrix management. As the UPI scans the matrix it
compares its present status to the previous scan. If
any change is detected, the location of the change is
decoded and loaded, along with the sensor's present
state, into DBBOUT. This byte is called a Change
Word. The Master processor has only to read one
byte to determine the status and coordinate of a
changed sensor. If the master had not read a previous Change Word in DBBOUT (OBF=l) before a
new sensor change is detected, the new Change
ROW
SELECT
LINES
Figure 16.
4X4 Sensor Matrix
/I-
DO-
V"
"V
07
Cs
AD
a RETURN LINES
PORT 1
804,AI
8741A
74154
WR
AO
FIFO NOT
EMPTY
oaF
P23
P22
P2'
P2S
r- 0
r- c
I-- a
P20 I-- A
P2'
G'
lS
.~
~ ~
Figure 17.
Rv
\'
16 x 8
SENSOR
MATRIX
SELECT LINES
128 Sensor Matrix Controller
AFN-ol538A
6-675
APPLICATIONS
I
Word is loaded·into an internal FIFO. This FIFO
buffers up to 40 changes before it fills. The status of
the FIFO and OBF is made available to the mas.ter
either by polling the UPI STATUS register, Figure
18A, or as interrupt sources on port pins. P24 and
P25 respectively, Figure 17. The FIFO NOT EMP-.
TY pin ~d bit are true as long as there are changes
not yet read in the FIFO. As long as the FIFO is not
empty, the UPI m~>nitors OBF and loads new
Change Words from the FIFO into DBBOUT. Thus,
the UPI provides complete FIFO management.
and updates of the sensor l!tatus.Rl is a general
FIFO pointer. The FIFO is implemented as a circularbuffer with In and Out. pointer registers which
are stored in R4 and Rs respectively. These registers
are moved into FIFO pointer Rl for actual transfers
into or out of the FIFO. ij2 is the Row Select
Counter. It stores the number of the row being
scanned.
63
MATRIX MAP
16x 8
4B
.7
7
6
5
L -.J
4
3
2
1
0
~
1
OSF IBF
F1
FO
CHANGE WORD READY (P25)
FIFO
40 x 8
FIFO NOT EMPTY (P24)
NOT~SEO
COMPARE
Figure 18A. Sensor Matrix Status Register Format
RES~ T
R7
CHANGE WORD STORE
R6
FIFOQUT
R5
FIFO IN
R.
COLUMN COUNTER
R3
SCAN ROW SELECT
R2
OBBOUT REGISTER:...... CHANGE WORD,
T
716151·13121,101
I O II I I=tl
. ~II ~I SENSOR COORDINATE
o
' - - - - - - - - - - - SENSOR STATE
o =CLOSED
1 =OPEN
Figure 188. Sensor Matrix Change Word Format
Internally, the matrix scanning software is programmed to run as a foregrourid task. This allows
the timer/counter to be used by any background task
although the hardware configuration leaves only 2
inputs (TEST 0 and TEST 1) plus 2 I/O port pins
available. Also, to add a background task, the FIFO
would have to be made smaller to accommodate the
needed register and data memory space. (It would be
possible however to turn the table here and make the
scanning software timer/counter interrupt-driven
where the timer times the scan interval.)
The data memory organization for this application is
shown in Figure 19. The upper 16 bytes form the
Matrix Map and store the sensor states from the
previous scan; one bit for each sensor. The Change
Word FIFO occupies the next 40 loc!ltions. (The top
and bottom addresses of this FIFO are treated as
equate variables in the program S9 that the FIFO
size may easily be changed to accommodate the register needs of other tasks.) Register Ro serves as a
pointer into the matrix map area for comparil!lons
FIFO POINTER
R1
MATRIX MAP POINTER
RO
Figure 19. Sensor Matrix Data Memory Map
Register Ra is the Column Counter. This counter is
normally set to OOH; however, when a change is detected somewhere in a particular row, it is used to
inspect each sensor status. bit individually for a
change. When a changed counter sensor bit is found,
the Row Select Counter and Column Counter are
combined to give the sensor's matrix coordinate.
This coordinate is temporarily stored in the Change
Word Store, register Rs. Register R7 is the Compare
Result. As each, row is scanned, the return information is Exclusive-OR'd with the return information
from the previous scan of that row. The result of this
operation is .stored in R7. If R7 is zero, there have
been no changes on that row. A non-zero result indicates at least one changed sensor.
The basic program operation is shown in the flow
chart of Figure 20. At RESET, the software initializes the working registers, the ports, and clears
the STATUS register. To get a starting point from
which to perform the sensor comparisons, the current status of the matrix is read and stored in the
Matrix Map. At this point, the UPI begins looking
for changed sensors starting with the first row.
6-676
APPLICATIONS
Before delving further into the flow, let's pause to
describe the general format of the operation. The
UPI scans the matrix one row at a time. If no
changes are detected on a particular row, the UPI
simply moves to the nett row after checking the status of DBBOUT and the FIFO. If a change is detected, the UPI must check each bit (sensor) within
the row to determine the actual sensor location.
(More than one sensor on the scanned row could
have changed.) Rather thaD test aUs bits of the row
before checking the DBBOUT and FIFO status
again, the UPI performs the status check in between
each of the bit tests. This ensures the fastest re~
sponse to the master reading previous Change
Words from DBBOUT and the FIFO.
I
INITIALIZATION
SCAN AND
COMPARE
With this general overview in mind, let's go fll8t
thru the flow chart assuming we are scanning a row
where no changes have occurred. Starting at the
Scan-and-Compare section, the UPI first checks if
the entire matrix has been scanned. If it has, the various pointers are reset. If not, the address of the
next row is placed on PORTs 20 thru 23. This selects
the desired row. The state of the row is then' read
on PORT 1; the column return lines. This presellt
state is compared to the previous state by retrieving the previous state from the matrix map imd
performing an Exclusive-OR with the present state~
Since we are assuming that no change has ~d,
the result is zero. No coordinate decodiDg is needed
and the flow branches to the FIFO-DBBOUT Manageinent ~ion.
CHANGE WORD
ENCODING
The FIFO-DBBOUT Management section simply
maintains the FIFO and loads DBBOUT whenever
Change Words are present in the FIFO and
DBBOUT is clear (OBF-O). The section first tests if
the FIFO is fulL (If we assume our "no-change" row
is the first row scanned, the FIFO obviously would
not be full.) If it·is, the UPI waits until OBF=O, at
which point the next Change Word is retrieved from
the FIFO and placed in DBBOUT. This "unfills" the
FIFO making room for more Change Words. At this
point, the Column Counter,'R3, is checked. For rows
with no changes, the Column Counter is always zero
so the test sUpply falls through. (We cover the case
for changes shortly.) Now the FIFO is tested for being empty. If it is, there is no sense in' any further
tests so the flow simply goes back up to scim the next
row. If the FIFO. is nOt empty. DBSOUT is tested
a,gain through OBF. If a Change Word is in
DBBOU~ wai~ing for the master to read it, nothing
can be done and the flQw ijkewlse branches up for
the next row. ,However, if the, PBBOUT is free and
remembering that the previouS test showed that the
FIFO was not empty, DBBOUT is loaded with the
next Change WQrd and the last two conditional tests
repeat.
'
FIFOoBBOUT
MANAGEMENT
Figur. 20. Sensor MatrIx Control.... Flow Chart
. 6-677
APPLICATIONS
Now let's assume the next row contains several
changed sensors. Like before, the row is selected, the
return lines read, and the sensor status compared to
the previous scan. Sin<;~ changes have occUrred, the
Exclusive-pR result is now non-zero. Any I's in the
result reflect the position!! of the changed sensors.
This non-zero result is stored in the Compare Re.sult
register, R7. At this point, the Column Counter is
preset to S. To determ,ine the changed sensors' locations, the Compare Result register is shifted bit-bybit to the left while decrllmentin~ the Column
Counter. After each shift, BIT 7 of the result is tested: If it is a one, a changed sensor has been found.
The Column Counter then reflected the sensor's matrix column position while the Scan Row Select register holds it row position. These registers are then
combined in Rs, the Change Word Store, to form the
sensor's matrix coordinate section ·of the Change
Word. The Sth bit of the Change Word Store is coded with the sensor's present state (Figure IS). This
byte forms the complete Change Word. It is loaded
into the next available FIFO position. If BIT 7 of the
Compare Result had been zero, that particular sensor had not changed and the coordinate decoding is
not performed.
master reads DBBOU'l'. Figures 21D and 2IE show
two more Change Wolds loaded into the FIFO. In
Figure 2IF the first Cl1imge Word is fmally read by
the master resetting OBF. This allows the next
Change Word to be loaded into DBBOUT. Note that
each time the FIFO is loaded, the FIFO-IN pointer
increments. Each time DBBOUT is read the FIFOOUT pointer increments unless there are no more
Change Words in the FIFO. Both pointers wraparound to the .bottom once they reach the FIFO top.
rhe remaining figures show more Change Words being loaded into the FIFO. When the entire FIFO fills
and DBBOUTcan not be loaded (OBF=I), scanning
stops until the master reads DBBOUT making room
for more Change Words.
In between each shift, test, and coorle for UPI use in serial I/O applications. Sockets are also provided for termination
of the parallel port.
either the receiver or the parallel input port, the FO
and Fl flags (BITs 2 and 3) code the source. Thus,
when the master fmds OBF set, it must decode FO
and Fl. to determine the source.
.
, STATUS FORMAT
171615141312 I' 10J
~,I~,
OBF-DATA AVAILABLE
BF-BUSY
FO
F'
NOT USED
Tx INTERRUPT
FRAMING ERROR
OVERRUN ERROR
PARALLEL PORT
FO
F1
OPERATION (SF
= 1)
NO OPERATION
PARALLElliO DATA
SERIAL 1/0 DATA
COMMAND ERROR
R,D
TICK SAMPLE
EXT CLOCK(76
FROM 8253
Figure 22.
a KHz)
Combination 1/0 Device
, There are three commands for this application.
Their format is shown in Figure 23. The CONFIGURE command specifies the serial baud rate
and the parallel I/O direction. Normally this command is issued once during system initialization.
The I/O command causes a parallel I/O operation to
be performed. If the parallel port direction is out,
the UPI expects the data byte immediately following
an I/O command to be data for the output port. If
the port is in the input direction, an I/O command
causes the port to be read and the datil placed in
DBBOUT. The RESET ERROR command resets
the serial receiver error bits in the STATUS register.
COMMAND FORMAT
716151 13121,10 I
4
CONFIGURE COMMAND
A
COP
A-1200 BAUD SELECT
8- 600 BUAO SELECT
c-
300 BAUD SELECT
0- 110 BAUD SEI,.ECT
P-PARALLEL 1/0 DIRECTION
O-INPUT
1-QUTPUT
o
o
Figure 23.
I/O COMMAND
RESET ERROR COMMAND
Figure 24.
STATUS Register Format
BIT 1 (IBF) functions as a busy bit. When IBF is set,
no writes to DBBIN are allowed. BIT 5 is the TxINT
(Transmitter Interrupt) bit. It is asserted whenever
the transmitter buffer register is empty. The master
uses this bit to determine when the transmitter is
ready to accept a data character.
BITS 6 and 7 are receiver error flags. The framing
error flag, BIT 6, is set whenever a character is received with an invalid stop bit. BIT 7, overrun error,
is set if a character is received before the master has
read a previous character. Jf an overrun occurs, the
previous character is overwritten "and lost. Once an
error occurs, the error flag remains set until reset by
a RESET ERROR command. A set error flag does
not inhibit receiver operation however.
Figure 25 shows the port pin definition for this application. PORT 1 is the parallel I/O port. The
UARTuses PORT 2 and the Test inputs. P20 is the
transmitter data out pin. It is set for a mark and reset for a space. P23 is a transmitter interrupt output.
This pin has the same timi~ as the TxINT bit in the
STATUS register. It is normally used in interruptdriven systems to interrupt the master processor
when the transmitter is ready to accept a new data
character.
Combination 1/0 Command Format
The OBF flag is brought out on P24 as a master interrupt when data is available in DBBOUT. P26 is a
diagnostic pin which pulses at four times the selected baud rate. (More about this pin later.) The receiver data input uses the TEST 0 input. One of the
PORT 2 pins could have been used, however, the
The STATUS register format is shown in Figure 24.
Looking at each bit, BIT 0 (OBF) is the DATA
AVAILABLE flag. It is set whenever the UPI places
data into DBBOUT. Since the data may come from
AFNoO'538A
6-680
APPLICATIONS
63
PORT ... DEF1NIT1ON
~
!!I
11-7
0
4
"
6
PARALLEL I/O
31
AC TEMP. STORE
30
COMMAND STORE
R8
29
Ta STATUS -
AS
28
Tx_
R4
27
Tx SEIIWJZEII
A3
26
Ta TICK COUNTER
R2
2"
BAUD RATE CONSTANT
Rl
NOT USED
AO
TxDalll
NOT USED
NOTUSEO
Tx IN1EIIRUPT
OBF IN1EIIRUPT
NOT USED
NOT USEO (TICK SA-.E)
NOT USED
TO
RxDATA
Tl
EXTEIINAL CLOCK (76.8 _ )
Figure 25.
USERIWI
(NOT USED)
!!!!£!!!!
32
24
23
R7
TxSTS
REGISTER
BAN< 1
STACK
(ONE LEVEL USEO)
CombInation 1/0 Port DefInItIon
software can test the TEST 0 in one instruction
without fl1'llt reading a port.
The TEST 1 input is the baud rate external source.
The UART divides this input to determine the timing needed for the selected baud rate. The input is a
non-synchronous 76.8 kHz source.
Internally, when the CONFIGURE command is received and the selected baud rate is determined, the
internal timer/counter is loaded with a baud rate
constant and started in the event counter mode.
Timer/counter interrupts are then enabled. The
baud rate constant is selected to provide a counter
interrupt at four times the desired baud rate. At
each interrupt, both the transmitter and receiver are
handled. Between interrupts, any new commands
and data are recognized and executed.
o
STATUS STORE
A7
Rx DESEIIWJZEII
R6
Rx TICK COUNTER
RS
RxHOLDING
A4
Ax STATUS-AxSTS
R3
NOTUSEO
R2
NOTUSEO
Rl
NOT USED
RO
Figure 26.
REGISTER
BANKO
Comblnetlon 1/0 Register Map
RlIISTS FORMAT
171615 14T3 121,10 I
I I, LL:
Rx FLAG-POSSIBLE START BIT
START FLAG-GOOD START BIT
BYTE F1NISHEO FLAG
DATA READY FLAG
FRAMING EAROR
OVERRAUN ERROR
I /ODIRECnON
I /0 FLAG
Flgur. 27. ' RxSTS Register
As a prelude to discussing the flow charts, Figure 26
shows the register defmition. Register Bank 0 serves
the UART receiver and parallel I/O while Register
Bank 1 handles the UART transmitter and commands. Looking at RBOfirst, Ra is the receiver status register, RxSTS. Reflected in the bits of this
register is the current receiver status in sequential
order. Figure 27 shows this bit defmition. BIT 0 is
the Rx flag. It is set whenever a possible start bit is
received. BIT 1 signifies that the start bit is good
and character construction should begin with the
next received bit. BIT 1 is the Good Start flag. BIT 2
is the Byte Finished flag. When all data bits of Ii
character are received, this flag is set. When all the
bits, data and stop bits are received, the assembled
character is loaded into the holding register I
7 I
S I THIS PRODR..... USES THE UPI-4IA /IS A LED DISPLAY CONTRClLLER
9 I WHICH SCANS AND REFRESHES EigHT SEIIEN-SEOMENT LED DISPLAYS.
10 I THE CHllftACTERS liRE DEFINED IY INPUT FROM II MIISTER CPU IN THE
II I FDAM OF ONE EigHT BIT WORD PER DIIIIT-CHMACTER SELECTION.
12 I
13 I
14 I
l'
J ***********************************.*.*.**.* ..******* ...************.
II> I
17
IS
19
20
21
22
23
24
2'
I REIlISTER DEFINITIONS.
I
REOISTER
I
RO
RI
R2
R3
R4
I
'"
I
I
I
21>
27
RI>
R7
R81
RBO .
DISPLAY MAP POINTER
NDT USED
NOT -USED
NOT USED
DATA WORD AND CHARACTER STORIIOE NOT USED
DIOIT COUNTER
NOT USED
NOT USED
NDT USED
NDT USED
NDT USED
NOT USED
NDT USED
ACCUMULATOR STORME
NDT USED
as
J **.********* ••• ******** ....*******.**•• ******** ......*************.***
29 I
30 I PORT PIN DEFINITIONS
31 I
PIN
32 J
PORT I FUNCTlDN
PORT 2 FUNCTION
-------------
--------------
33 •
SEGMENT DRIllER CONTROL
DigIT DRIVER CONTRCIL
PO-7
:14 I
35 SE"ECT
6-691
AP,..uc~nONS,
""
,;
PAGE
LOC
DB'"
LIIIE
:2
SOURCE STATEI1ENT
36 ; *******•••••******** ...**********..***** ....*****.***...****....**......
37 ,DISPL.AY DATA WORD BIT DEFINITIDN:
3B
BIT
WUNCTION
39 •
40
CHARACTER SELECT
DII/IT SELECT
0-4
41 •
5-7
42 •
43 • CHARACTER SELECT:
44
D4
45
0
46.
0
47
0
48.
0
49 J
:10 ;
51 J
:S2 I
:53;
:54 J
0
0'
0
0
0
0
:Sf) ;
i56 ,
0
D3
0
0
0
0
0'
0
0
0
1
1'
1
1
1
1
1
1
0
0
57 •
0
0
58,
0
59,
60 ,
61 ,
62 I
0
0
1
1
1
0
64
1
0
1
0
1
0
0
63 ,
65
I
J
66
67
1
6B
69;
70 J
71
72
73
74
1
1
1
75
76
1
1
-I
1
0
1
1
1
I
1
i
1
D2
0
0
0
0
,1
1
1
1
0
0
0
0
1
1
1
1
'0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Dl
0
0
1
1
0
0
1
1
0
0
1
1
Or
0
1
1
0
0
1
1
0
DO
0
1
1
5
6
7
0
8
1
0
1
0
1
B
0
0
1
0
1
1
C
D
E
F
1
0
1
0
1
0
1
1
0
1
1
9
A
0
I
0
2
3·
4
0
1
'0
1
0
0
CHARACTER
0
1
0
H
I
J
L
N
D
P
R
T
0
I
0
1
0
I
0
I
U
y
I
"BLAMI-
77 ,
7B ,DIQIT SELECT'
79 ,
D7
D6
D5
80,
81 ,
0
0
0
0
0
1
82.
0
1
0
3
B3 •
0
1
1
84.
1
0
0
4
:5
6
7
8
DIOIT ....... ER
1
2
85,
1
0
1
86.
1
1
0
87,
1
1
~
88 J . . . . . . .***.*********••****.***.**********************••***......*******
B9 .E,JECT
6'-692
APPLICATIONS
lele-II rtCS-48/UPI-41 MACRO ASSEMBLER.
LOC
DB'"
LINE
90
91
PME
Y3.0
3
SOURCE STATEI1ENT
* .......**.......**.....**.......................................
I ................
J
EGUATES
92 • THE FDLLQWING CODE DESI_TES "TJI'E" AS A YARIABLE. THIS
"3 • AD.JUBTS THE APlllUNT OF CYCLES THE TlIIER COUNTS BEFORE
94 .'" TU.ER INTERRUPT OCCURS lIND REFRESHEB:THE. DISPL"'V. APPROlClMATELY
'" • ~ TlMES PER SECDNJ).
"6 Tll'E
ECiU
-oFH' • TlI'ER Y/llLUE 2 . _ C
FFFI
0000
0000
0002
0003
000'
0006
0409
00
0436
00
00
0007 041D
*********.***.
97
J *it •••••••••••••••• _ . . . . . . . . . . . . . . . . . . _ ••• _ . . . . . . . . . . . . . . . . .
98
.,.,
100
101
102
103
104
10'
106
•
INTERRUPT BRANCHING
• THIS PORTlON OF I1EI1OIIV IS DEDIC"'TED FOIl USE OF RESET /lIND
• INTERRUPT BRANCHING. WHEN THE INTERRUPTS ARE ENABLED THE
• CODE AT THE FOLLOWING DESIGNATED SPDTS ARE .EXECUTED WHEN A
• RESET DR A INTERRUPT OCCURS
ORQ
0
•
.JMP
START
• RESET
NaP
•
. "'""
INPUT
• IBF INTERRUPT
NaP
107
loa
NIIP
1~
~
110 ;
;
•
DI8PLA
J Tlt1I!ft
INTERRUPT
.*.*.*.*****.*•••*••••* ••**...******.** ... **.*.***..........*****.*.*******
111 •
INITl/IILUATlON
112 • THE FOLLOWING CODE SlETS UP THE UPI-41 lIND DISPLAY HARDWARE
113 • INTO OPERATlON/llL FOII""T. THE DISPLAV IS TURNED OFF, THE DISPLAY
114
J MAP
IS FILLED WITH "BLANK." CHARACTERS,
THE TII£R ,SET AND THE
11' • INTERRUPTS ARE ENABLED
116
0009
OOOA
OOOC
OOOE
0010
0011
0012
0013
0015
0017
001"
OOIA
OOIB
OOIC
D'
aAoa
B83a
23FF
AO
la
Fa
B20E
BBOO
23FI
62
"
2'
0'
J
117 START'
SEL
118
OftL.
119
" i'IOV
120
121
122
123
124
12'
126
127
128
129
130
131
132
133
134
13'
136
137
RBI
•
J TURN DIOIT DR IVERS_ OFF
,DISPLAY MAP POINTER, BOTTatt OF DISPLAY HAP
BLK"'AP MOY
A, .OFFH
J FF."BLANK"
MOY
eRO, A
• BLANK TO DISPLAY MAP
INC
RO
,INCREMENT DISPLAY MAP POINTER
MOY •
A, RO
• DISPLAV MAP POINTER TO ACCUMULATOR
"'B'
BLKMAP
• BLANK DISPLAV MAP TILL FILLED
MOY
R3, .OOH
• SET DIgIT COUNTER TO 0
MOY
A, .rIME
• TlME~ Y/llLUE
MOV
T. A
• LOAD TIMER
STRT
T
• START TIMER
EN
TCNTI
, ENABLE TIMER INTERRUPT
EN
1
,ENABLE IBF INTERRUPT
; ****************************************.*******************************
,
USER PROQRAM
J A USERS PROGRAM WOULD INITIALIZE AT THIS POINT. THE FOLLOWING
• CODE IS UND CONCLUDED WITH
,SYNC CHARACTERS (OMHI.
A CHECKSUI'I BVTE IMMEDIATELV PRECEEDS THE
• FINAL SYNC
WHEN READINQ, THE CONTROLLE***-_*** ••************_._***_*___"'*.*
.E"'ECT
pa, _OSH
RO,.3BH
AfN.01536A
6-693
APPLICATIONS
IBIS-II MCS-48/UPJ-41 MeRD ASSEMBLER,
LOC
OB.J
LINE
138
00ID
ODIE
001F
0021
0022
0024
002'
0026
0027
0028
0029
002A
002C
002E
0030
0032
0033
0034
003'
DlI
AF
BAoa
1'1
433B
AB
1'0
3'
Fa
3A
la
D307
'630
aBOO
23Fl
62
"
1'1'
'3
139
140
141
142
143
144
1411
146
147
148
14'
150
151
152
153
154
155
156
1:t7
V3 0
PAGE
4
SOURCE STATEI'IENT
********.**************************************************************
•
DISPLAY ROUTINE'
J
, THIS PORTION OF THIS pROIlAAI'! IS AN INTERRUPT ROUTINE WHICH IS
,ACTED UPON WHEN THE TII1ER COUNT IS CDl'lPLETED. THE ROUTINE UPDATES
,ONE DISPLAY DIGIT FRor! THE DISPLAY !'lAP PER INTERRUp:r SEQUENTIALLY,
,THUS EIGHT TII'IER INTERRUPTS WILL HAVE REFRESHED TI'IE ENTIRE DISPLAY.
,REGISTER BA~ 1 IS SELECTED AND THE ACCUl'lULATOR IS SAVED UPON
,ENTERING THE ROUTINE ONCE THE DISPLAY HAS BEEN REFRESHED THE TIllER
,IS RESET AND THE ACCUIIULATDR AND PRE-INTERRUPT REgISTER BANK IS RESTDRED.
J
DISpLA
BEL
MOY
ORL
!'IOV
ORL
I'IOV
I'IOV
OUTL
!'IOV
RBI
R7, A
1'2, .OSH
A, R3
A••3BH
RO. A
A, eRO
Pl. A
A. R3
',REIlISTER _ _ 1
,BAVE ACCUI'IULATOR
,fURN DIgIT' DRIVERB OFF
,DIgIT COUNTER TO ACCUl'lULATOR
,'OR" TO gET DISPLAY I1AP ADDRESS
,DISPLAY MAP POINTER
,(lET CHARACTER FRDM DISPLAY I1AP
,OUTPUT CHARACTER TO SEIlMENT DRIVERS
,DIIIIT COUNTER VALUE TO ACCUMULATOR
DUTL
P2. A
J OUTPUT
TO DIGIT DRIYI!RS
15B
INC
R3
• INCREMENT DIIIIT COUNTER
15'
XRL
A••07H
,CHECK IF AT LAST DIIlIT
160
.JNZ
SETIHE
,RESET TlI'IER IN', NOT LAST DIIIIT
161
MOY
R3dIOOH'
,RESET DigIT COUNTER
162 SETIME: I'IOV
A••TII1E
'TlI'IER VALUE
163
MOV
T. A
,LOAD TlI'IER
164
STRT
T
,START TlI'IER
16'
!'IOV
A. R7
,RESTORE ACCUMULATDR
166
RETR
, RETURN
167 J ************.*.*****.*.*.-.*'... *.***********--****.*****.....******.****
168 .E.lECT
!
6-694
:
APPLICATIONS
ISIS-II MCS-48/Uf'I-41 J'lACRO IIISSEI1BLER,
LOC
OB.J
t..INE
169
0036
0037
0038
0039
003A
003B
003C
003E
0040
0041
0042
0044
0045
0046
00419
004A
004B
05
AF
22
AA
47
77
5307
433B
AB
FA
531F
E3
AA
D37F
Cb4E
FA
AO
004C 04:51
004E FA
004F :50
00:50 AO
0051 FF
0052 93
170
171
172
173
174
175
176
177
178
179
ISO
IBI
182
183
IB4
185
IB6
IB7
IBB
IB9
190
191
192
193
194
195
196
197
19B
199
200
201
202
V3.0
PAGE
SOURCE STATEJ'IENT
i
; **********************************.****.* ...*******.*********** ••*******
,
INPUT CHARACTER AND DIgIT ROUTINE
, THIS PORTION OF THE PROQRA!'I IS AN INTERRUPT ROUTINE WHICH
, IS ACTED UPON WHEN THE IBF BIT IS SET. THE ROUTINE gETS THE
,DISPLAY DATA WORD FROM THE DBB AND DEFINES BOTH THE DIgIT 'AND
,THE CHARACTER TO BE DISPLAYED. THIS IS DONE BY MEANS OF A
J CHARACTER l.OOP-UP TABLE AND It DISPL.AY MAP FOR DIGIT AND CHARACTER
,LOCATION. SPECIAL CONSIDERATION IS TAKEN FOR A DECII'IAL POINT WHICH 18
,SIMPLY ADDED TO THE EXISTING CHARACTER IN THE DISPLAY f'tAP. REGISTER
,BANK 1 IS SELECTED AND THE ACCUMULATOR IS SAIlED UPON ENTERINQ
,THE ROUTINE. ONCE THE D"'TA WORD HAS BEEN FULLY DEFINED THE ACCU!'IULATOR
,AND THE PRE-INTERRUPT REGISTER BANK IS RESTORED.
J
INPUT:
DPOINT
203
SEL
!'IOV
IN
!'IOV
SWAP
RR
ANL
ORL
MOV
!'IOV
ANL
!'IOVP3
!'IOV
XRL
.JZ
!'IOV
!'IOV
.J!'IP
!'IOV
ANL
f10V
204 RETURN. !'IOV
205
RETR
206 I
RBI
R7.A
A,D88
R2.A
A
A
A.I07H
A.13BH
RO.A
A.R:!
A.4nFH
AdlA
R2.A
A.17FH
DPOINT
A.R2
eRO.A
RETURN
A. R2
A.eRO
80. A
A. R7
,REQISTER BANK 1
i SAVE ACCU!'IULATOR
I GET DATA
,SAVE DATA WORD
,DEFINE DIGIT LOCATION
,
I DIGIT LOCATION IN DIGIT POINTER
i SAIlED DATA WORD TO ACCU!'IULATOR
,DEFINE CHARACTER LOOK-UP-TABLE LOC.
I GET CHARACTER
J SAVE CHARACTER
• IS CHARACTER DECIMAL POINT
,
; SAVED CHARACTER' TO ACCUMULATOR
TO DISPLAY MAP
,; CHARACTER
,SAVED CHARACTER TO ACCUMULATOR
• "AND" WITH OLD CHARACTER
• BACK TO DISPLAY MAP
• RESTORE ACCUMULATOR
**********************************************************************
207 _E.JECT
AFN-OI536A
6-695
APPLICATIONS
ISIS-II MCS-4B/UPI-41 MACRO ASSEMBLER.
LOC
LINE
OB"
V30
' 'PAGE
6
SOURCE STATEMENT
20B
; *********************************************************************
209
L[J(M-UP TABLE'
210
THIS LOOK-UP TABLE ORIGINATES IN PAGE 3 01' THE UPI-41 PROGRAM
211 J MEMORY. I T IS USED TO DEFINE THE CORRECT LEVEL .0F EACH SEGMENT
212 I AND DECIMAL POINT FOR A SEL.ECTED CHARACTER FROM THE INPUT ROUTINE.
213 ,INVERSE LOGIC IS, USED BECAUSE 'OF THE, SPECIFIC DRIVER CIRCUITRY; THUS
214 • A I ON A GIVEN SEGMENT MEANS IT IS OFF AND A 0 MEANS IT IS ON
215
0300
0300
0301
0302
0303
0304
0305
0306
0307
030B
0309
oaOA
030B
030e
0300
OSOE
030F
0310
0311
0312
0313
0314
216
217
21B
219
220
221
222
223
224
223
226
227
228
229
230
231
232
J
*******SeGMENTS********
g
ORG
300H
.DP
F E ·0 C B A
, DB
O' 0
0
0
eeOH'
.1'
I
0
0
,I
DB
OF'PH
I
I
I
I
0
0
I
DB
OA4H
0' I
0
.1
0
I
0
0
DB
oaOH
.1
0
I
I
0
0
0
0
DB
99H
.1
0
0
I
I
0
0
I
i1,
CH~'
DB
92H
0
0
I
0
0
I
0
, I
CHo:
DB
B2H
0
I
0
0
0
0
0
CH7
,I
DB
OFBH
I
I
I
I
0
0
0
CHB:
DB
BOH
.1
0
0
0
0
0
0
0
, 1
eH9DB
9BH
0
0
1
I
0
0
0
CHADB
BBH
.1
0
0
0
I
0
0
0
CHB
DB
B3H
,I
0
0
0
0
0
I
I
CHe
,I
DB
OC6H
I
0
0
0
I, I
0
,DB
CHD
OAlH
I I
0
I
0
0 (\ '0
I
CHE
e6H
DB
0
0
0
0
I
I
0
233 CHF
,I
DB
BEH
0
0
0
I
I
I
0
,,0
234 CHDP
7FH'
DB
I
I
I
I
I
I
I
235 CHG
,I
DB
OC2H
I
0
0
0
0
I
0
236 CHH
DB
B9H
.1
0
0
0
I
0
0
237 CHI
OFBH
DB
I
I
I
I
0
I
"
239 CH.J
DB
OE1H
.1
I
0
0
0
0
239 CHL
DB
OC7H
0
0
0
I
1
I
"
240 CHN
I
DB
CASH
.1
0
I
1 0
0
1
241 CHO
DB
OA3H
.1
0
I
0
0
0
I
I
242 CHP
DB
SCH
0
0
0
0
0
1
"
243 CHR.
DB
OAFH
.1
0
I
0
I
1
1
244 CHT
DB
B7H
.1
0
0
0
0
I
24~ CHU
0
DB
OCIH
1 0
0
0
0
246 CHY
DB
91H
•1
0
0
0
0
0
247 CHDASH
DB
OBFH
•1
0
1
I
24B CHAPOS
DB
OFDH
.1
I
I
0
249 BLANK
DB
OFFH
.1
1
I
1
250
; ************************************************************************
251
END
CO
F9
A4
BO
99
92
B2
FB
SO
9B
BS
83
C6
AI
86
8E
7F
C2
B9
FB
El
031:' C7
0316 AS
0317 A3
0318 ae
0319 AF
031A S7
031B CI
031C 91
031D BF
031E FD
031F FF
USER SYMBOLS
BLANK
031F
CH6
0306
CHD
080D
CHJ
0314
CHY
031C
J
CHO'
CHICH2.
CH3
CH4
,"
...
BLKMAP
CH7
CHDASH
CHL
DI$PLA
ASSEMBLY COMPLETE,
OOOE
0307
0810
031~
0010
CHO
CHe
CHDP
CHN
DPOINT
0300
0308
0310
0316
004E
CHI
CH9
CHE
CHO
INPUT
0301
0309
030E
0317
0036
CH2
CHA
CHF
CHP
RETURN
0302
030A
030F
0318
0051
CH3
CHAPOS
CHG
CHR
SETINE
0303
031E
0311
0319
0030
CH4
CHB
CHH
CHT
START
0304
03013
0312
031A
0009
CH5
CHC
CHI
CHU
TIME
0305
030C
0313
031E
FFF1
NO ERRORS
AFN.o1536A
6-696
APPLICATIONS
FI "'S"4S
F3 SENSOR NDOB.JECT PRINT! LP I
PAGE
ISIS-II "CS-4S/UPI-41 "AeRO "'SSE"BLER. 113 0
LOC
DB'"
LINE
SDUftCIE STATEl'lENT
I etIOO4I ...
2
3
4
••••••••••••••••••••••••••••••••••••••••••••••
•
UPI-41'" SENSOR ""'TRIX CONTROLLER
•
••••••••••••••••••••••••••••••••••••••••• *** ••
5
"
.,
7
I
S
I
10
11
12
I
I
I
THIS PROQRM USE. THE UPI-41'" "'S ... SENSQR ·"... TRIX CONTROLLER
IT HAB "DNITOIIINQ CAP...BlLITIES OF UP TO 128 BENBORS
THE COORDIN...TE
AND SENSOR ST...TUS OF E...CH DETECTED C _ IS ...II... IL.... LE TO THE MSTER
HICRDPROCES_ IN ... SINeLE BYTE.
... 40XS FIFO ClUEUE "IS PROIiIDED FOR
DAT ... IUFFERINQ
10TH HAIIOW""'E 011 POLLED INTERRUPT ~THODS CAN .IE USED
TO NOTIFY THE H...STER OF ... DETECTED SENSOR CHANeE
.
13
J •••••
14
15
I"
17
IS
I
I
I
*................................** •••••••••••••••••••••••••••••••••
REQISTER DEFINITIONS.
IIEQISTER
RIC!
RBI
I
RO
RI
24
R6
" ...TR IX "AP POINTER
FIFO POINTER
SC"'N ROW SELECT
COLunN COUNTER
FIFO-IN
FIFO-DUT
CH_E WORD
25
R7
C~Me:
19 I
20 I
21
22
j'
23
I
R2
R3
R4
R5
~I
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
USED
USED
USED
USED
USED
USED
USED
USED
•
'.
27 J • • • •**** ••• ** •••** ...................**•••* ••••••• ** •••••••••••••••••**
28 I
29 • PORT PIN DEFINITIONS'
30 I
PORT 2 FUNCTION
31 J PIN
PORT I, FUNCTION
PIN
3l!
33 IPO-7
PO-3
ROW SELECT OUTPUTS
COLUNN LINE INPUTS
FIFO NOT EI1PTY INTERRUPT
P4
34 I
P5
OIF INTERRUPT
35
NOT USED
3ft I
P"-7
37
38 J • • • • • • • • • • • • • • • • • • • • • • • •**•••••••••••••••••••••••••** ••••• * •• * ..........
39
40 SE.JECT
6-697
APPLICATIONS
ISIS-II MCS-4S/UPI-41 MACRO ASSEMBLER.
LOC
OBJ
LINE
41
V3 0
PAGE
SOURCE STATEMENT
I
************************************************.****.**.******.*****
42
43 • CHANGE WORD BIT DEFINITION
44
4~ ,
BIT
46
FUNCTION
SENSOR COORDINATE
47
SENSOR STATUS
48
49
2
~*******.*.*********.*****************.**** •• ********* *************.*.*
,
!!to •
~1
52 • STATUS REGISTER BIT DEFINITION'
~3
BIT
FUNCTION
~8
DO
01-3
04
~9
05-7
OBF
IBF. FO. Fl (NOT USED)
FIFO !\lOT EMPTY
USED DEF I NED (NOT USED)
~4
~~
56
~7
60,
61 .*************************************.*.***********************.*******
62
63
E(lUATES
1.4
6~
66
67
6B
69
70
71
72
• THE FOLLOWING CODE DESIGNATES THREE VARIABLES. SCANTM. FIFOBA
• AND FIFOTA
SCANTM ADJUSTS THE LENGTH OF A DELAY BETWEEN
• SCANNING SWITCH
THIS SIMULATES DEBOUNCE FUNCTIONS
FIFOBA
• IS THE BOTTOM ADDRESS OF THE FIFO
FIFOTA IS THE TOP ADDRESS
• OF THE FIFO THIS MAKES IT POSSIBLE TO HAVE A FIFO :3 TO 40
• BYTES IN LENGTH
.**** ••• *.**.**.*.***************.****.*.****************.**** ••••••••
73
OOOF
0008
002F
74 SCANTM
FIFOBA
76 FIFOTA
77
7~
I
EQU
E(lV
E(lU
OFH
OBH
2FH
• SCAN. TIME ADJUST
.FIFO BOTTOM ADDRESS
• FIFO TOP ADDRESS
79 $EJECT
AFN-Ol536A
6-698
APPLICATIONS
ISIS-II I'1CS-4B/UPI-41 MAeRO ASSEMBLER.
LOC
0000
0000
0002
0004
0006
OOOB
OOOA
OOOC
0000
OOOE
OOOF
0010
OB')
SB3F
BAOF
BCOB
BD2F
B9FF
2300
90
FA
3A
09
AO
0011 FA
0012
0014
001'
OOlb
0016
OOIA
0018
OOIC
Cbl6
C6
CA
0400
BAIO
FA
3A
F'
LINE
V3 0
PAGE
SOURCE STATEMENT
79 • ** ..................** ..............................** ••••••••••••••••••
BO
SI
INITIALIZATION
S2
83 • THE PROGRAM STARTS AT THE FOLLOWINII CODE UPON RESET
WITHIN
,B4 • THIS INITIALIZATION SECTION THE REIIISTERS THAT MAINTAIN THE MATRIX
S' • MAP. FIFD AND ROW SCANNING ARE SET UP
PORT I IS SET HIGH FOR USE
B6 • AS AN INPUT PORT FOR THE COLUI1N STATUS
BIT 4 OF STATUS REIlISTER IS
B7 • WRITTEN TO CONVEY A FIFO EJlPTY CONDITION
THE INITIAL COLUMN BTATUS
BS ,OF ALL THE ROWS IN THE SENSOR MATRIX IS THEN READ INTO THE MATRIX
B9 ,MAP
ONCE THE MATRIX MAP IS FILLED THE DBF INTERRUPT (PORT 2-4) IS
90.ENABLED
91' •
92 I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .*** ••••••••••••••••
93
94
ORIl
o
,MATRIX MAP POINTER REQIBTER. TOP ADDRESS
95 INITMX MOV
RO •• 3FH
96
,BCAN ROW SELECT REGIISTER. TOP ROW
MOV
R2 •• 0FH
MOV
<17
R4 ••FIFOBA
• FIFO INPUT ADDRESS REGISTER. DOT1'OI1 OF FIFO
9B
R~, .FIFOTA
MOV
• FIFO OUTPUT 'ADDRESS REGISTER. TOP OF FIFO
99
ORL
PI ••OFFH
• INITIALIZE PORT I HIGH FOR INPUTS
100,
A••OOH
MOV
• INITIALI ZE STATUS REGISTER'. FIFO EMPTY
101
I10V
STS.A
• WRITE TO STATUS REGISTER. BITS 4-7,
102 FILLMX MOV
A.R2
• SCAN ROW SELECT TO ACCUMULATOR
103
OUTL
P2.A
• OUTPUT SCAN ROW SELECT TO PORT O!
104
IN
A.PI
• INPUT COLUMN STATUS PORT I
MOV
eRO. A
• LOAD MATR IX MAP WITH COLUMN STATUS
10'
106
A.R2
MOV
• CHECK SCAN ROW SELECT REG I STER VALUE FOR 0
107
JZ
OBFINT
• IF 0 ENABLE OBF INTERRUPT
lOS
DEC
RO
• DECREMENT TO NEXT MATR I X MAP ADDRESS
109
DEC
• DECREMENT TO SCAN NEXT ROW
R2
110
.IMP
FILLMX
• FILL NEXT MATRIX MAP 'ADDRESS
III DBFINT MOV
RO! •• IOH
• BIT 4 HIGH IN ROW SCAN SELECT REGISTER
112
MOV
A.RO!
• ROW 'SCAN SELECT VALUE TO ACCUMULATOR
113
OUTL
P2. A
• INITIALIZE PORT 2. 81T 4 FOR "EN FLAGS"
FLAQS
114
• ENABLE OBF I NTERRUPT PORT 2. 8 IT 4
EN
115
lib .EJECT
AFN.Ql536A
6"699
APPLICATIONS
ISIS-II MCS-4B/UPI-41 MACRO ASSEMBLER.
LOC
OBJ
LINE
IlB
0010 FA
001E
~30F
0020
0022
0023
0024
0026
C626
CB
CA
042C
SB3F
0026 FA
0029 430F
0028 AA
002C
0020
002E
0030
0032
0033
FA
3A
SSOF
EB30
09
20
0034 DO
0035 AF
0036 C669
4
***************.***********************.**************.***************
SCAN AND COI'IPARE
• THE FOLLOWING CODE IS THE SC",N ...ND COMpAIIE SECTION OF THE pROQRAI'I.
.• UPON ENTERING THIS SECTION ... CHECK IS M"'DE TO SEE IF THE ENTIRE !'lATRIX
• HAS BEEN SCANNED.
IF SO THE RECnSTERS THAT !'IAINTAIN THE MATRIX MAP AND ROW
• SCANNINQ ARE RESET TO THE BECHNNING OF THE SENSOR MATRIX.
IF THE ENTIRE
.M... TRIX HASNT. BEEN SC"'NNED THE REGISTERS INCREMENT TO SCAN THE NEXT ROW.
• FRDI'! THIS POINT ON THE ROW SCAN BELECT REGISTER IS USED FOR TWO FUNCTIONS.
• BITS 0-3 FOR SCANNINGI ...ND BITS 4 AND , FDR THE EXTERNAL INTERRUPTS.
THUSLY
....LL USAGIE OF THE REGISTERS IS DONE BY LOGICALLY I'IASKING IT SO AS TO ONLY
• AFFECT THE FUNCTION DESIRED
ONCE THE REGISTERS ARE RESET. ONE ROW OF THE
• SENSOR M"'TRIX IS SC"'NNED.
... DELAY IS EXECUTED TO ...D.JUST FOR SCAN TIME
• (DEBOUNCEI.
A BYTE OF COLUMN STATUS IS THEN RE ...D INTO THE I'IATRIX 1'1"'1'
.... T THE TIME THE NEW COLUI'IN ST"'TUS IS CO""''''RED TO THE OLD.
THE RESULT IS
• STORED IN THE CDI'!p ...RE REGISTER.
THE pROGIR ...M IS THEN ROUTED ACCORDING TO
• WHETHER OR NOT ... CHANGIE WAS DETECTED.
. ********* •• **********************************************************
AD,JREQ
MOV
",NL
JZ
R$ETRQ.
148 5CANltX
149
150
1"1 DEL ...Y2.
152
153
1"4
155
1 " ..
"",GE
SOURCE STATEI'IIi:NT
117 •
119
120
121
122
123
124
12'
126
12?
128
129
130
131
132
133
134
13'
136
137
13B
139
140
141
142
143
144
14"
146
147
V3 0
DEC
DEC
.IMP
MOV
MOV
ORL
"OV
"OV
OUTL
"OV
DJNZ
IN
XCH'
XRL
MOV
JZ
.... R2
A, .OFH
RSETRGI
RO
R2
SC ...HM •
RO ••3FH
A,R2
A ••OFH
R2 ....
A.R2
1'2....
R3 ••SC ...NTM
R3.DELAY2
A. PI
.... !tRO
A.@RO
R7.A
CHFFUL
• SC"'N ROW SELECT TO "'CCUMULATOR
• CHECK FOR 0 SC ...N V...LUE ONLY.NOT INTERRUPT
,IF 0 RESET REGISTERS
,DECREMENT M... TRIX .....P POINTER
• DECREMENT SCAN ROW SELECT
• SC ...N MATRIX
• RESET ..... TRIX "AP POINTER REGIISTER. TOP ADDRESS
.SCAN ROW SELECT TO ACCUMULATOR
,RESET SCAN ROW SELECT. NO INTERRUPT CHANGE
.SCAN ROW SELECT REGIISTER
• SCAN ROW SELECT TO ACCUMULATOR
• OUTPUT SCAN ROW SELECT TO PORT 2
• SET OELAY FOR OUTPUT SCAN TIME
.OEL"'Y
• INPUT COLUMN ST... TUS FROM PORT I TO ACCUMULATOR
.STORE NEW COLUMN STATUS S"'VE OLD IN ACCU..UL ... TOR
• COMPARE OLD WITH NEW COLUMN STATUS
• SAVE CO..PARE RESULT IN COMP ...RE REGISTER
• IF THE SA"E. CHECK IF FIFO 16 FULL
1"7
15B .EJECT
AFN-01536A
6-700
APPliCATIONS
ISIS-II t\CS-4S/UPI-41 "ACRO ASSE"BLER.
LaC
OBJ
LINE
PAgE
V3 a
SOURCE STATE"ENT
1 ~9 , ••••**.** •••** ••••• ****•••• **..** ••••••••• ** •••• *** ••••* ........** •••• **
160
161
162
163
164
16'
166
167
16S
169
170
171
172
173
174
17~
003S
003A
0038
003C
003D
003E
0031"
0040
0041
0043
BBDB
CB
1"0
77
AO
1"1"
77
AI"
F24~
0469
004~ FA
0046 ~30F
004S E7
0049 E7
004A E7
004B 4B
004C AE
004D FO
004E ~3S0
OO~O 4E
OO~I
AE
CHANGE WORD ENCODINII
THIS
• THE;! POLLOWINII CODE IS THE C _ E WORD ENCODING! SECTION.
• SECTION ·IS ONLY EXECInED IF A CH_E WAS DETECTED
THE COLUI'IN COUNTER
, IS sn AND DECREI1ENTED TO DESlgN"'TE E"'CH OF. THE S COLU"NS.
THE COI'IPARE
• REgiSTER IS LOIMED ... T ONE BIT "'T ... TlI1E TO FIND THE EX ...CT LDCATIDtil OF
• THE CHANgEIS)
WHEN ... · CHANQE IS FOUND IT IS ENCODED BY GlIVINg IT A
THIS IS DONE BY CO"BINING!·THE PRESENT VALUE
• COORDINATE FOR ITS LOCATION
.IN THE ROW SC ...N SELECT REgiSTER AND THE COLUI'IN COUNTER.
THE ...CTUAL STATUS
• OF THAT SENSOR IS EST ...BLISHED BY LOOKIIIIII ",T THE CORRESPONDINg· BYTE IN
• THE "ATRIX"",P
THIS STATUS IS CO"BINED WITH THE COORDINATE TO ESTABLISH
• THE CHANgE WORD
THE CHANIIE WORD IS THEN STORED IN THE CHANgE WORD REgiSTER
,.**•••• *** •••••• ***.****** ••• ***••••• ***..................* ••••••••••••
176
177 RRLOOK
17S
179
ISO
lSI
IS2
IS3
IS4
P10V
DEC
"OV
RR
"OY
"OY
RR
I'IOY
JB7
IS~
J"P
IS6 E;!NCODE;! I'IOV
...NL
IS7
ISS
'RL
IS9
RL
190
RL
191
ORL
192
193
"OV
194
"OY
ANL
19'
196
ORL
197
I'IOV
19S
199 .EJECT
R3 •• 0SH
R3
A,eRO
A
IIRO.A
A,R7
A
R7d~
ENCODE
CHFFUL
A. R2
A. _OFH
.A
A
A
A. R3
R6d"
A.IIRO
A. _SOH
A. Rb
R6. A
• SET COLUI'IN COUNTER REgiSTER TO S
• DECRE"ENT COLU"N COUNTER
,COLUt1N STATUS TO ACC.U"UL"'TOR
• ROTATE COLU"N. STATUS RIGlHT
• ROTATED COLU"N STATUS BACK TO "ATRIX "AP
• CO"PARE REGIISTER YALUE TO ACCUI1ULATOR
• ROTATE COMPARE VALUE RIGHT
• ROTATED CO"PARE YALUE TO CO"PARE REGISTER
• TEST BIT 7 IF CHANGE DETECTED ENCODE CHANGE WORD
• IF NO CHANgE IS DETECTED CHECK FOR FIFO FULL
• SCAN ROW SELECT TO ACCU"ULATOR
OOOOXXXX
• ROTATE ONLY SCAN VALUE
OOOXXXXO
• ROTATE LEFT
• ROTATE LEFT
OOXXXXOO
• ROTATE LEFT
OXXXXOOO
• ESTABLISH "ATRIX.COORDINANT
OXXXXXXX
• lOR) COLUI'IN COUNTER VALUE WITH 'ACCU"ULATOR
• SAVE CQORDIN"'NT IN CH"'NGE WORD REGISTER
• COLU"N STATUS FROI'I "ATRIX MAP TO ACCUMULATOR
.0 ALL BITS BUT BIT 7
I
(OR) SENSOR STATUS WITH COORDINATE FOR COMPLETED CHANGE WORD
• SAVE CHANGE WORD
XXXXXXXX
~1538A
6-701
APPLICATIONS
ISIS-II MCS-46/UPI-4I MACRO ASSEMBLER.
LOC
OBJ
LINE
V3 0
PAGE
6
SOURCE STATEMENT
200 ; *********************************************************************
201
202
FIFO-DBBOUT MANAGEMENT
203
204 ,THE FOLLOWING CODE IS' THE FIFO~D8BOUT MANAGEMENT SECTION OF tHE'
205 'PROQRAM
THIS SECTION TAKES AN ENCODED CHANGE WORD AND LOADS IT INTO
206 • THE FIFO
THE FIFO NOT EMPTY INTERRUPT' IS THEN SET AND THE FIFO-IN
207 l POINTER GETS UPDATED A FIFO FULL CONDITION IS THEN CHECKED FOR AND
20B • ROUTED ACCORDI'NIlLY
IF BOTH THE FIFO AND OBF HAVE CHANGE WORDS THE
IF THE FIFO ISNT FULL COLUMN
209 ,PROGRAM LOCKS UP UNTIL THIS,HAS CHANGE~
210 ,COUNTER,.O. FIFO EMPTY AND OBF CONDITIONS ,ARE CHECKED
THE FIFO-OUT
211 • POINTER IS' SET AND' DBBOUT IS LOADED IF THE FIFO ISNT EMPTV AND OBF ISNT
ot12 ,SET.
IF THIS ISNT THE SITUATION. PROGRAM FLOW IS ROUTED BACK TO THE
213 rTHE SCAN AND COMPARE SECTION TO SCAN THE NEXT ROW
214
0052 FC
0053 A9
00'4 FE
0055 AI
0056 23)0
0056
0059
00'8
005C
005E
005F
0061
0062
0064
90
8A20
FA
4320'
AA
232F
DC
Cb67
IC
0065 0469
0067
0069
006A
006B
0060
006F
0071
0072
BCOB
FC
DO'
9670
B660
232F
DO
C677
0074 10
0075
0077
0079
007A
007B
007C
0479
BDOB
FO
A9
FI
02
0070 Fa
007E 963A
0080 2308
21 5 i *********************** *********************~**.***************** **_*
216
A. R4
,FIFO INPUT ADDRESS TO ACCUMULATOR
217 LOADFF' Mev
21B
Mev
RI. AI
• FIFO POINTER USED FOR INPUT
219
MOV
A. R6
• CHANGE WORD TO ACCUMULATOR
220
MOV
ItR!. A
• LOAD FIFO AT FIFO INPUT ADDRESS
221 STATNE' MOV
A •• IOH
• BIT 4 FOR FIFO NOT EMPTY
222
MOV
STS,A
I WRITE ,TO STATUS
REGISTER. FIFO NOT EMPTY
.FIFO NOT EMPTV INTERRUPT PORT 2-5 HIGH
223 INTRHI: ORL
P2.4I20H
224
MOV
A.R2
• ROW SCAN SELECT TO ACCUMULATOR
225.
ORL
A •• 20H
• SAVE INTERRUPT. NO CHANGE TO SCAN VALUE
226
MOV
R2. A
,ROW SCAN SELECT REGISTER
227 ADJF I N MOV
A •• FIFOTA
• FIFO TOP ADDRESS TO ACCUMULATOR
226
XRL
A. R4
• COMPARE WITH CURRENT FIFO INPUT ADDRESS
• IF THE S~ME RESET FIFO INPUT REGISTER
229
JZ
RSFFIN
230
INC
R4
• NEXT FIFO INPUT ADDRESS
JMP
231
CHFFUL
• CHECK FIFO FULL
232 RSFFIN MOV
R4 •• FIFOBA
• RESET FIFO INPUT REGISTER. BOTTOM OF FIFO
233 CHFFUL
A. R4
• FIFO INPUT ADDRESS TO ACCUMULATOR
MOV'
234
A. R5,
,COMPARE INPUT WITH OUTPUT FIFO ADDRESS
XRL
235
JNZ
CHCNTR
• IF NOT SAME CHECK COLUMN COUNTER VALUE
236 CHOBFI
JOBF
CHOBFI
• IF OBF IS I THEN CHECK ODF
, FIFO TOP ADDRESS TO ACCUMULATOR
237 ADJFQT
MOV
A. ttFIFOTA
23B
A. R:5
XRL
• COMPARE TOP TO OUTPUT FIFO ADDRESS
RSFFOT
239
JZ
• IF THE SAME RESET FIFO OUTPUT REGISTER
,NEXT FIFO OUTPUT ADDRESS
240
INC
R5
241
JMP
LOADDB
• LOAD DBBOUT
242 RSFFOT
R5,ttFIFOBA
,RESET F I Fa OUTPUT ADDRESS TO BOTTOM OF FIFO
MOV
A, R:5
243 LOADDB
• OUTP,UT FIFO ADDRESS TO ACCUMULATOR
MOV
244
MOV
RI. A
• FIFO POI NTER USED FOR OUTPUT
245
A. (tRI
MOV
• CHANGE WORD TO ACCUMULATOR
,CHANGE WORD TO DBBOUT
246
OUT
DBB. A
247' CHCNTR
MOV
A. R3
• COLUMN COUNTER TO ACCUMULATOR
248
JNZ
RRLOOK
• IF NOT 0 FINISH CHANGE WORD ENCODING
249 CHFFEM MOV
J FIFO
BOTTOM ADDRESS TO ACCUMULATOR
A. ttFIFOBA
250
251 .EJECT
AFN-Ol536A
6-702
APPLICATIONS
1515-1 J MCS-4B/UPI-41 MACRO ASSE.MBLER.
LOC
OBJ
0082
008::!
0085
008b
0087
00B8
OOBA
008C
008E
OOBF
00"1
0093
0094
0090
0097
0099
OIl"A
009C
009E
DC
Cb8C
FC
07
00
Cb91
049C
232F
DO
9b9C
2300
90
9ADF
FA
LINE
USER SYMBOLS
AD.JFEM OOBC
CHOBF2 009C
INTRLO 0094
SCANMX 002C
XRL
2~3
J~
2~4
2~9 ADJFEM
2bO
21.1
262 STATMT
21.3
'01604 INTRLO:
MOV
DEC
XRL
JZ
.!I'IP
MOV
XRL
JNZ
MOV
MOV
ANL
2b~
MOV
21.1.
2b7
2bB
21.9 Cl-fOBF2'
270
271
272
ANL
MOV
..IMP
.JOBF'
.JMP
2~5
2~b
257
258
AA
041D
BblD
04bF
AD.JFIN OO~F
DELAY2 0030
LOADDD 0079
SCANTM OOOF
ASSEMBLY COI'IPLETE,
'PAGE"
7
SOURCE STATEMENT
252
~3DF
V3 0
A, R4
AP.JFEM
A. R4
A
A, R~
STATMT
Cl-fOBF,~
A, ,FIFOTA
A, R5
Cl-fOBF2
A,.OOH
STS, A
PC ••ODFH
A,R2
A, .ODFH
R2,A
ADJREG
AP.JREG
AOJFOl
,COMPARE FIFO IN~UT .ADDRESS WITH FIFO BOTTOM.ADD
,IF THE SAME.
ADJUST TO CHECK FOR FIFO EMPTY
,FIFO INPUT ADDRESS TO ACCUMULATOR
,DECREMENT FIFO INPUT ADDRESS IN ACCUMULATOR
,COMPARE INPUT TO OUTPUT FIFO ADDRESSES
,IF SAME, WRITE STATUS REGISTER FOR FIFO EMPTY
,CHECK OBF
,FIFO TOP ADDRESS TO ACCUMULATO~
,COMPARE TOP TO OUTPUT FIFO ADDRESS
• IF NOT SAME THEN FIFO IS NOT EMPTY. CHECK OBF
,CLEAR BIT 0 FOR FIFO EMPTY
,WRITE TO STATUS REGISTER
,FIFO EMPTY, INTERRUPT 'PORT 2-5 LOW
; SCAN ROW SELECT TO AC~UI'1ULATOR
,SAVE INTERRUPT, NO CHANGE TO SCAN VALUE
,SCAN ROW SELECT REGISTER
iADJUST REGISTERS
, IF OBF-I THEN AD.JUST REGISTERS
• ADJUST FIFO OUT ADDRESS TO LOAD D8BOVT
END
AD.JFOT OObF
ENCODE 004~
LOADFF 00~2
STATMT 0091
ADJREG 0010
FIFOSA oooe
OBFINT 0018
STATNE 0051.
CHCNTR 0070
FIFOTA 002F
RRLOOK 003A
CHFFEM ooeo'
FILLMX 0000
RSETRQ 0021.
CHFFut 0010"1
INITMX 0000
R5FFIN 0067
CHOBFl OObD
INTRHl 0059
RSFFOT 0077
NO ERRORS
AFN-01536A
APPUCATI(:)NS
PROGRAMMABLE KEYBOARD INTERFACE
• SlmuHaneous Keyboard and Display
Operations
"
".
• N-Key Rollover with Programmable
Error Mode on Multiple New Closures
• Interface Signals for Contact and
capacitive Coupled Keyboards
• Sixteen or Eight Character SevenSegment Display Interface
• 128-Key Scanning Logic
• Right or Left E,ntryDlspiay RAM
• 10.7msec Matrix Scan Time for 128 Keys
and 6MHz Clock
• Depress/Release Mode Programmable
• Interrupt Output on Key Entry
• Eight Charflcter Keyboard FIFO
This application is a general purpose programmable
keyboard and display interface device designed for
use with 8-bit microprocessors like the MCS-SO and
MCS-8S. The keyboard portion can provide a
scanned interface to 128-key contact or capacitivecoupled keyboards. The keys are fully debounced
with N -key rollover and programmable error generation on multiple new key closures. Keyboard entries
are stored in an 8-character FIFO with overrun sta-
RL
x,
x.
RESET
B.
MS
DATA
BUS
BO
MO
KeL
MS
AO
M5
WR
M.
SYNC
M,
DO
M.
D,
M,
D.
Mo
0,
D.
Ne
INTERRUPT
REQUEST
AD
WR
cs
Ao
Voo
D5
ERROR
Dt;
IRQ
D7
........
B,
B,
GND
SCAN
OUTPUTS
CLR
cs
AD
The display portion of the UPI-41A provides a
scanned display interface for LED, incandescent
and other popular display technologies. Both numeric displays and simple indicators may be used.
The UPI-41A has a 16X4 display RAM which can be
Vee
Ne
GND
tus indication when more than 8 characters are entered. Key entries set an interrupt request output to
the master CPU.
TO
DISPLAY,
DIGITS
HYS
BP
+5_
PWR --..
GND ____
Figure 1.
Pin Configuration
INTERNAL
BUS
Figure 2.
Block Diagram
APPLICATlqNS
loaded or interrogated by the CPU. Both right entry
calculator and left entry typewriter display formats
are possible. Both read an4 write of the display
RAM can be done with auto increment oithe display
RAM address.
ORDERING INFORMATION:
This part may be ordered 88 an 8041A with ROM
code number 8278. The source code is 'available
through Insite.
Throughout this application of the UPI·41A, it will
be referred to by its ROM code number, 8278. The
8278 is packaged in a 4O.pin DIP. The following is a
brief functional description of each pin.
PRINCIPLES OF OPERATION
The following is a description of the major elements
of the Programmable Keyboard/Display inteqace
device. Refer to the block diagram in Figure 1.
1/0 Control and Data Buffer.
The I/O control section uses the CS, Ao, RD, and
WR lines to control data flow to and from. the var·
ious internal registers and buffers (see Table 2). All
data flow to and from the 8278 is enabled by CS. The
8·bits of information being transferred by the CPU
is identified by Ao. A logic one means information is
command or status. ~c zero means the informa·
tion is data. RD and WR determine the direction of
data flow through the Data Bus Buffer (DBB). The
Table 1. Pin Description
SIgnal
12·19
110
WR
10
I
RD
8
I
CS
Xlo X 2
6
9.
4
2,3
I
I
I
I
mQ
23
0
27-33
0
RL
1
I
HYS
22
0
KCL
34
0
SYNC
11
0
Bo-B 3
35-38
0
ERROR
24
0
CLR
BP
39
21
0
DO·D7
Ao
RESET
Mo-Ms
VCC,VDD
GND
Name and Function
Pin. No. Type
40,26
20,7
I
I
I
Data Bus: Three-state, bi·directional data b~ lines used to transfer data and commands between the CPU and the 8278.
Write: Write strobe which enables the master CPU to write data and commands between the CPU and the 8278.
Read: Read strobe which enables the master CPU to read data and status from the
.8278 intem81 registers.
Chip Select: Chip select input used to enable reading and writing to the 8278.
ControllData: Address input used by the CPU to indicate control or datil. .
. Reset: A low signal on this pin resets the 8278.
Freq. Reference Inputs: Inputs for crystal, L-C or external timing signal to determine internal oscillator frequency.
Interrupt Request: Interrupt Request OUtput to the master Cpu. In the keyboard
mode the mQ line goes low with each FIFO read and returns high if there is still information in the FIFO or an ERROR has occurred.
Matrix Sean Lines: Matrix scan outputs. These outputs control a decoder which
scans the key matrix columns and the 16 display digits. Also, the Matrix scan outputs
~e used to multiplex the return lines from the key matrix.
Keyboard Return Line: Input from the multiplexer which indicates whether the key
currently being scanned is closed:
Hysteresis: Hysteresis output to the analog detector. (Capacitive keyboard COnIIguration). A ·0· means the key currently being scanned has already been recorded.
Key Clock: Key Clock output to the analog detector (capacitive keyboard configuration) used to resst the detector before scanning a key.
Output Clock: High frequency (400kHz) output signal used in the key scan to detect
a closed key (capacitive keyboard conIIguration).
Display Outputs: Thess four lines contaiD binary coded decimal display information
synchronized to the keyboard column SC$ll. The outputs are for multiplexed digital
displays.
Error Signal: This line is high whenever two new key closures are detected during a
entered into the keyboard FIFO. It is resst
single sean or when too many characte~
by a system RESET pulss or by a ~1· input on the CLR pin or by the CLEAR ERROR
command.
Clear Error:. Input used to cl~ an ERROR condition in the 8278.
Tone .Enable: Tone enl!ble output. This line is high for lOms following a valid key
closure; it is set high and remains high during an ERROR condition.
Powet: +5 volt power input: +5V ± 10%.
Ground: Signal ground.
are
6-705
APPLICATlONS.
are niuItiplexed' by the .8278.' When akey closure is
detected, the debourice logic waits about 12msec
check if the key remains clOsed. If it does, the ,address ofthe key in the matrix is transferred into,a
FIFO buffer.
DBB register is a bi-directional8-bit buffer register
which connects the internal 8278 bus buffer register
to the external, bus. When the chip is not selected
(CS = 1) the DBB is in the highimE!!an.£! state.
The DBB acts as an input when (RDJYR, CS) = (1,'
0,0) and an output when (iID,WR, OS) = (0, 1,0).
to
FIFO and
FIFO Status
,',
"
The 827,8 contains an 8X8 FIFO character buffer.
Each new entry is written into a successive FIFO,location and each is then read out in the order of entry.
A FIFO status register keeps track of the number of
characters in the FIFO and whether it is full or empty. Too many reads or key entries will be recognized
as an error. The status can b!l read bya RD with CS
low and Ao high. The status logic also provides a
IRQ signal to the master processor whenever the
FIFO is not empty.
Table 2. 1/0 Control and Data Buffera
cs
0
0
0
0
1
Ao WR RO,
'0
1
0
1
1
1
0
0
0
0
1
1
X
X
X
Condition
Read DBBData
Read STATUS
Write Data to DBB
Write Command to DBB
Disable 8278 Bus,
High Impedance
Scan Counter
The scan counte,r provides, the timing to scan the
keyboard and display. Th'e four MSB's (M3-M6)
scan the display digits and provide column filcan to
the keyboard via a 4 to 16 decod!lr. The three LSB's
(MO-M2) are used to multiplex; the row return lines
into the 8278.
Display Address Registers and Display RAM
The Display Address registers hold the address of
thl1 word currently being written 8r read by the CPU
and the two 4-bit nibbles being displayed. The
read/write addresses are programmed by CPU command. They al~o Clll/. be set to auto increment after
each read or:'\vtite. The display RAM can be directly
read by the CPU after th8- correct mode and address
is set. Data entry to the display can be set to either
let'( or rIght entry.
Keyboard Debounce and, Control
The 8278 system configuration is shown in Figure 3,
The rows of the matrix are ,scanned anchhe outputs
TO TONE GENERATOR
ANALOG
DETECTOR
BP
ERF,tOR
(lLR
,
RLHYS~
"!2 ,
MULTIPLEXER
8041A/
~ASTER
PROCESSOR
8741A
00-07'
WR
Ro
SYNC
"!6
AO
RESET
";0
83' • '. ~ -BO
.
:,'
---'
Cs
4TO 16
DECODE
---
--8-
'
~
"
1",1,~
~
I
I
CAPACITIVE
KEYBOARD
MATRIX
a OR,~6,DlGIT DIsPLAY
Figure 3.
I
ANALOG
M:i
IRO
8
TO
8060, 8085 OR 8048
I
KCL
,
" "
'~TSCAN
Syatem Conflguratlon"for Capacltlve-C:oupled KeYboard
I
APPLICATIONS
TO TONE GENERATOR'
I,
9P
r
I
RL
ERROR
CLR
~2
IRQ
MO
_·'AI
J
8741A
8
--8--
00,07
TO
8080, 8085 OR 8048
,
MASTER
PROCESSOR
,
r---
WRD
AO
CS
I
DIGITAL
MULTIPLEXER
"!6
RESET
M3
93··· •• 90
4 TO 16
DECOOE
I r-
4TO 16
DECODE
16
--I
I
~
I
16
i
'---
1
I
I
I
CONTACT
KEYBOARD
MATRIX
16 DIGIT SCAN
8 OR 16 DIGIT DISPLAY
,
Figure 4.
System Configuration for Contact Keyboard
COMMANDS
The 8278 operating mode is programmed by the
master CPU using the AO, WR and DO-D7 inputs as
shown below:
AO.
os
3'--___v_AL_D
__....--'X~_'N_VA_Ll_D_
\
INVALID
/
X
VALID
X
INVALID
The master CPU presents the proper command on
the DO-D7 data lines with Ao =1 and then sends a
WR pulse. The command is latched by the 8278 on
the rising edge of the WR and is decoded internally
to .set the proper ppera~ing mo.de. See the
8041A/8741A data sheet for timing details.
Where the mode set bits are defined as follows:
K-the keyboard mode select bit
O-normal key entry mode
I-special function mode: Entry on key closure
and on key release
D-the display entry mode select bit
O-left display entry
I-right display entry
I-the interrupt request (IRQ) output enable bit.
O-enable IRQ output
I-disable IRQ output
E-the error mode select bit
O-error on multiple key depression
.. I-no error on multiple key depression
N-the number of display digits select
0-16 display digits
1-8 display digits
NOTE:
The default mode following a RESET input is all bits zero:
READ FIFO COMMAND
CODE
Command Summary
I 0 I 1 I 0 10 I 0 I 0 I 0 I 0
KEYBOARD/DISPLAY MODE SET
READ DISPLAY COMMAND
CODE
CODE
101010iNIEIIIDIK
6-707
I 0I '
I ' I AI IA31 A2 I A, IAO I
APPLICATIONS
Where AI indicates Auto Increment and A3-AO is
the address of the next display character to be read
out.
AI = 1 AUTO increment
AI = 0 no AUTO increment
The S3-So status bits indicate the number of entries
(0 to 8) in the 8-level FIFO. A FIFO overrun will lock
status at 1111. The overrun ,condition will prevent
further key entries until cleared.
WRITE DISPLAY COMMAND
l\ multiple key closure error will set the KE flag and
CODE
prevent further key entries until cleared.
I 1 I 0 I 0 I AI IA31 A2 IAl IAo I
Where AI indicates Auto Increment and Aa-Ao is
the address of the next display character to be
written.
CLEAR/BLANK COMMAND
CODE
11 1011 IUDIBDICDICFICEI
Where the comm~d bits are defined as follows:
CE = Clear ERROR
CF = Clear FIFO
CD = Clear Display to all High
BD = Blank Display to all High
UD = Unblank Display
The display is cleared and blanke4 following a
Reset.
Status Read
The status register in the 8278 can be read by the
master CPU using the Ao, RD, and DO-D7 inputs as
shown below:
AO,Cs
==x
AD
\'---_/
The 8278 places 8-bits of status information on the
Do-D7lines following (AO, CS, RD) = 1,0,0 inputs
from the master.
'
Status Format
07
06
05
ISo I B' IKE IIBF IOBF I
04
03
02
The IBF and OBF flags signify the status of the 8278
data buffer registers used to transfer information
(data, status or commands) to and from the master
CPU.
'
The IBF flag is set when the master CPU writes
Data or Commands to the 8278. The IBF flag is
cleared by the 8278 during its response to the Data
or Command.
The OBF flag is set when the 8278 has output data
ready for the master CPU. This flag is cleared by a
master CPU 'Data READ.
The Busy flag in the status register is used as a
, LOCKOUT signal to the master processor during response to any command or data write from the
master.
The master must test the Busy flag before each read
(during a sequence) to be sure that the 8278 is ready
with valid DATA.,
The ERROR and TONE outputs from the 8278 are
set high for either type of error. Both types of error
are cleared by the CLR input, by the CLEAR ERROR command, or by a reset. The FIFO and Display
buffers are cleared independently of the Errors.
,VALID
I s31 s21 81
STATUS DESCRIPTION
01
Do
Where the status bits are defined as follows:
IBF = Input Buffer Full Flag
OBF = Output Buffer Full Flag
KE = Keyboard Error Flag (multiple depression) ,
B = BUSY Flag
S3-S0 = FIFO Status
FIFO status is used to indicate the number of characters in the FIFO and to indiate whether an error
has occurred. Overrun occurs when the entry of another character into a full FIFO is attempted. Underrun occurs when the CPU tries to read an empty
FIFO. The character read will be the last one entered. FIFO status will remain at 0000 and the error
condition will not be set.
Data Read
The master CPU can read DATA from the 8278
fIFO or Display buffers by using the Ao, RD, and
DO-D7 inputs. "
'
The master sends a RD pulSe with Ao = 0 andCS = 0
and the 8278 responds by outputting data on lines
!!!tD7. The data is strobed by the trailing edge of
RD.
. '
6-708
APPLICATIONS
DATA READ SEQUENCE
Before reading data, the master CPU must send a
command to select FIFO or Display data. Following
the command, the master must read STATUS and
test the BUSY flag and the OBF flag to verify that
the 8278 baS respOnded to the previous command. A
typical DATA READ sequence is III follows:
BUSY
L
J
IIF
WRITE DISPlAY
COMMAND
8278
IIASTER
8278
READY
DATA WRITE
READY
FOR
FIRST BYTE
COIIIIIAND
OR DATA
l
BUSyJ
'---_----If
OBF
READ DlSP\.AY
FIRST
OR FIFO COMMAND
DATA BYTE
FROIlIiASTER
READY
t
IIASTER
NEXT
READS DATA
BYTE READY
8278
PROCESSING
NEXT BYTE
After the first read following a Read Display or Read
FIFO command, succeBBive reads may occur as soon
as OBF rises.
Data Write
The master CPU
Write DATA to the 8278 Display buffers by using the Ao, WR and DO-D7 inputs
as follows:
em
3 . . .___
AO,Cs
-'X
VAI._ID_ _ _
8.78
READY
IIASTER WRITES
NEXT BYTE
INTERFACE CONSIDERATIONS
Scanned Keyboard Mode
With N-key rollover each key depreBBion is treated
independently from all others. When a key is depressed the debounce logic waits for a full scan of
128 keys and then checks to see if the key is still
down. H it is, the key is entered into the FIFO.
H two key closures occur during the same scan the
,ERROR output is set, the,KE flag is set in the Status
word, the TONE output is activated and IRQ is set,
and no further inputs are accepted. This condition is
cleared ~h signal on the CLEAR input or by a
system RESET input or by the CLEAR ERROR
command.
In the special function mode. both the key closure
and the key release cause an entry to the FIFO. The
release is entered with the MSB=1.
Any key entry triggers the TONE output for 10ms.
INVAUD
\'--------11
The master CPU presents the Data on the DO-D7
lines with Ao=O and then sends a WR pu18e. The
data is latched by'the 8278 on the rising edge of WR.
The HYS and KCL outputs e~ble the 8nalog multiplexer and detector to be synchronized for interface
to capacitive coupled keyboards.
Data Format
In the scanned keyboard mode, the code entered
into the FIFO corresponds to the position or address
of the switch in the keyboard. The MSB is relevant·
only for special function keys in which code "0" signifies closure and "1" signifies release. The next four
bits are the column count which indicates which column the key was found in. The last three bits are
.
from the row counter.
BIT
7
e
5
432
o
DATA WRITE SEQUENCE
Before writing data to the 8278, the' master CPU
must first send a command to select the desired display entry mode and to specify the address of the
next data byte. Following th~ commands, the master
must read STATUS and test the BUSY flag (8) and
IBF flag to verify that the 8278 has responded, A
typical sequence is shown below.
1 FOR SPECIAL FUNCTION'
MODE AND KEY RELEASED
o FOR KEY DEPRESSED
Display'
Display data is IIntered into a 16X4 display register.
aJid may be en~ from the left, from the right or
,6-709
'APPUCATIONS
,
"
s
COUNT
'I
'I
110
I
II,
'I
1
I
X
X
n
n
t
X
X
t
n
n
~lgur. 5, Keybqard Timing
,
SCAN CYCLE
IRQ
,:
BP
----------------~
~~----------------~------~I
t ' t
~D
KEV,1
ENTERED
Figure 6.
"
.i.
DISPlAY
~
lis
KEY 3
DEPRESSED
Key Entry and Error Timing
/
i
5
I
I'
" I
I
I
;..
'
,
I
I'
r
liS
"
_s"
KEY 2
DEPRESSED
,,'
0
,I,
KEY 1
READ BY MASTER
r\
7 '\
7\
7\
"
Figure 7.
Dl8p1ay Timing ,
6-71Q
I
:I'
~"
'J
I
l' \
1'\
'8
, I
APPLICATIONS
into specific locations in the display register. A new
data character is put out on Bo-Ba each time the
M6-Malines change (i.e., once every O.75ms with a 6
MHz crystal). Data is blanked during the time the
column select lines change by raising the display
outputs. Output data is positive true.
LEFT ENTRY
The left entry mode is the simplest display format in
that each display position in the display corresponds
to a byte (or nibble) in the Display RAM. ADDRESS
oin the RAM is the left-most display character and
ADDRESS 15 is the right-most display character.
Entering characters from position zero causes the
display to rill from the left. The 17th character is entered back in the left-most position and filling again
proceeds from there.
AUTO INCREMENT
In the Left Entry mode, Auto Incrementing causes
the address where the CPU will next write to be incremented by one and the character appears in the
next location. With non-Auto Incrementing the entry is both to the same RAM address and display position. Entry to an arbitrary address in the Left
Entry-Auto Increment mode has no undesirable
side effects and the result is predictable:
-1
0
1ST ENTRY
2
14
1ST ENTRY
2
3
15
2ND ENTRY
3
4
t
0
13
11 I 2 I
2
I 2 I 3 I
2
18TH ENTRY
8
7
2
3
4
6
8
7
DISPLAY
RAM
I ADDRESS
234
687
ENTER NEXT AT LOCATION 5 AUTO INCREMENT '
o
234
687
3RDENTRY
11 I 2 I
41H ENTRY
1
...._1...L1_2....11_L-...L........I1_3--,--1_4...LI--I
o
I 3 I
234
5
8
In the Right Entry mode, Auto Incrementing and
non-Incrementing have the same effect as in the Left
Entry except that the address sequence is interrupted.
11 1,2 I 3 I
0
171H ENTRY
6
0
11 I 2
SRDENTRY
181HENTRY
DISPLAY
16
0
RAM
I ADDRESS
11
4
11 I 2 I
o
RIGHT ENTRY
Right entry is the method used by most electronic
calculators. The rmt entry is placed in the rightmost display character. The next entry is also placed
in the right-most character after the display is
shifted left one character. The left-most character is
shifted off the end and is lost.
3
11 I
0
2ND ENTRY
2
3
I 3 I 4 I
14
16
1141151181
14
16
16
0
3
4
5
8
7
2
3
4
6
8
7
0
2ND ENTRY
I
Note that now the display posftion and 'register address do not correspond. Consequently, entering a
character to an arbitrary position in the Auto Increment mode may have unex'pec.ted resUlts. Entry
starting at Display RAM ADDRESS 0 with sequential entry is recommended. A Clear Display command should be given before display data is entered
if the number of data characters is not equal to 16 (or
8) in $is mode.
0
11 I 2
2
1
118117118
2
1ST ENTRY
0
1161181171
'I
3
4
6
8
I
I
0
COMMAND
10010101
ENTER NEXT AT LOCATION 5 AUTO INCREMENT
3
4
3RDENTRY
6-71'1
8
7
6
8
I 3 I 4 I
0
2
11 I 2 I
I 3 I
4
41HENTRY
6
7
0
11 I 2 I
2
3
DISPLAY
RAM
AODRESS
APPLICATIONS
Starting at an arbitrary location operates as shown
below.
'
O'
2
3
4
5
e
7
DISPLAY
RAM
r---T"""II--r-I"""--"1Ir--T"""I-'--I~I1
COMMAND
10010101
ADDRESS
ENTER NEXT AT LOCATION 5 AUTO 'INCREMENT
2
3
4
5
e
0
I I
1ST ENTRY
1
3
4
5
e
0
I I I
2ND ENTRY
1
2
8TH ENTRY
I l Ie I I I I I I
9TH ENTRY
I Ie I Ie I I I I I
4
5
5
7
7
8
9
1
2
2
3
3
4
Entry appears to be from the initial entry point.
APPLICATION
NOTE
AP-161
" ;
September 1983
@
INTEL CORPORATION, 1983
NOVEMBER 1983
ORDER NUMBER- 230795..(J01
6-713
,I"~
';;'
,'.
',,\,
,i ~\\
I
',',' ',.: 7
• ,,''''
COMPLEX PERIPHERAL
CONTROL WITH THE
UPI-42
,
:
I
I
,.r\
1
",'~,
~
,J.
TABLE OF CONTENTS·
INTRODUCTION ......•..........•.•..
DOT MATRIX PRINTING ..........••••..
THE PRINTER MECHANISM ..•••.....•.
HARDWARE INTERFACE ...•....•..•...
TECHNICAL BACKGROUND ....•......
SOFTWARE .•.......••...•.....•.•..•.
Introduction ....•.......•........•...
Functional Overview ................•.
Memory and Register Allocation .•.....
Description of Functional
Blocks and Flowcharts .. : ...••....
CONCLUSION' ........................ ~
APPENDICES
~ppendix A. Software Listing .•......
Appendix B. Printer Enhancements .•.
Appendix C. Printer Mechanism
Drive Circuit Schematics .•.......•
FIGURES
1. UPI-42 Pin Configuration ....•.....•
2. UPI-42 Block Diagram .......•.....•
3. UPI-41A,42 Functional
Block Diagram ......... '.......•.•••
4. Character E In 5 x 7 Dot
Matrix Format •..•.............•....
5. Carriage Stepper Motor Assembly '"
6. Print Head Solenoid Assembly ...•.•.
" .l Hardware Interface Block Diagram .. .
8. Hardware Interface Schematic ...... .
~.' UPI-42 and 8243 I/O Port Map .•.•...
10. S~epper Motor Step
Se~uence Waveforms ..•.•.......•..
11. carD" Stepper Motor
Step Seq."ence ................... " .
12. Paper F~· Stepper M,otor
Step Sequence ................... ..
13. Carriage Stepper Motor
Drive Timing .. '......••.......•...••
14. Carriage Stepper Motor
Predetermined Tlme:Constants ..... .
15. Paper Feed Stepper Motor
Predetermined Time Constants •.••.•
16. PTS Lags PT Timing .': .. ,,'~ .........
11 PTS Leads PT Timing •.............
18. Components of PrInt Head ASsembly
Line Motion and Printing. • . . . • . . • • .. \
19. Data Memory Allocation Map .•....••
20. Register Bank 0
Register Assignment •......•••....•
'21. Register Bank 0 Sta.us
'
Byte Flag Assignments ............ .
6-714
230795-001
inter
AP-181.
22. Register Bank 1
.
Register Assignment .••..•••..•...•
23. Register Bank 1 Status
.
Byte Flag Assignments ............. ;
24. Program Memory Allocation Map ... .
25. ASCII Character Code TEST
O.utput and .I'rh'lt', Example •..•.•..•..
26.
~~=rs'::8= ~~~~~
............ ;
FLOW CHARTS,
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
Main Program Body ............... ..
Power-On/Reset Initialization .•.••••.
Home Print Head Assembly .•••.•...
Extemal Status Switch Check .•.•..•
Character Buffer Fill .............. ..
Carriage Stepper Motor Drive
and Line Printing ~ .•...•. .' .•.•...•..
Carriage Stepper Motor
,
Acceleration Time Storage .......... .
Proce.. Characters for Printing ....•.
'ThIn"'te Character-to-Dots ...••....
Decelerate Carriage
Stepper Motor ................. '.. ..
Paper E:eed Stepper Motor Drive .,.•..
Addtional sources of information on Intel's UPI
devices;
"UPI User's Manual"
Includes the following Application Notes;
Programmable Keyboard Interface
Using the 8295 Dot Matrix Printer Controller
An 8741 Al8041 A Digital Cassette Controller
"8048 Family Applications Handbook"
"1983 Microprocessor and Peripheral Handbook"
"MCS-48 and UPI:41A/42 Assembly Language
Manual"
'\SpeCifications, for Impact., Dot Matrix Printer
Model-3210~·. Epson, Jan'8, 1981
6-715
230795-001
AP-161 ,
INTRODUCTION
The UPI-42 is the newest meritb~rof.Intel's Universal
Peripheral Interface (UPI) ;niqocom'puter family. It
represents a significant growth in UPI ca.pabilities"
resulting in a broader spectrilm of applications. The
Up,I-42 incorporates twice the EPROM/ ROM of the
UPI-41 A, 2048 vs 1024 bytes, tW,ice the RAM, .128 vs 64
bytes, and operates at a maximum speed twic~ that of
the UPI-4IA, i.e. 12 MHz vs 6 MHz. The ROM based
8042 and the EPROM based 8742 provide more highly
integrated solutions for complex stepping motor and
dot matrix printer applications. Those applications
previously requiring a microprocessor plus a UPI chip
can now be implemented entirely with the UPI-4;!.
The software features of the UPI-42, such as indirect
Data and Program Memory addressing, two independent and selectable 8 byte register banks, and
directIysoftware testable I/O pins, greatly simplify the
external interface and software flow. The software and
hardware design of the UPI-42 allows a complex
peripheral to becontrolled·with a minimum of external
hardware.
.
TEST 0
XTAL1
Until recently, the dedicated control processor approach
was usually not cost effective due to the large number of .
components needed; CPU, RAM, ROM, I/O, \ and
Timer/ Counters. To help make the approach more cost
effective, in 1977 Intel introduced the UPI-4l family of
Universal Peripheral Interface controllers consisting ·of
an 8041 (ROM) device and an 8741 (EPROM) device.
These devices integrated the common microprocessor
system functions into One 40 pin package. The UPI-42
family, consisting of the 8042 and 8742, further extends
the UPl's cost effectiveness through more memory and
higher speed.
Another member of the UPI family is the Intel 8243
Input/Output Expander chip. This chip provides the
UPI-4lA and UPI-42 with up to 16 additional independently programmable I/O lines, and interfaces
directly to the UPI-4IA/42. Up to seven 8243s can be
cascaded to provide over 100 I/O lines.
The UPI is a single chip microcomputer with a standard
microprocessor interface. The UPI's architecture, illustrated in Figure 3, features on-chip program memory,
ROM (804lA/8042) or EPROM (874lA/8742), data
memory (RAM), CPU, timer/counter, and I/O. Special interface registers are provided which enable the
UPI to function as a peripheral to an 8-bit central
processor.
Vee
TEST 1
XTAL2
RESET
Using one of the UPI devices, the designer simply codes
his proprietary peripheral control algorithm into the
UPI device itself, rather than into the main system
software. The UPI device then performs the peripheral
control task while the host processor simply issues
commands and transfers data. With the proliferation of
microcomputer systems, the use of UPls or slave
J1licroprocessors to off load the main system microprocessor has become quite common.
P26 ORO
55
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P"
Ro
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WR
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02
p,.
03
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PIIOG
Os
P23
D6
P22
07
P2'
V55
P20
This Application Note describes how the UPI-42 can be
used to control dot matrix printing and the printer
mechanism, using stepper motors for carriage/print
head assembly and paper feed motion. Previous Intel
Application Notes AP-27, AP-54, and AP-91 describe
using intelligent processors and peripherals to control
single solenoid ~riven printer mechanisms with 80
character line buffering and bidirectional printing. This
Application Note expands on these previous themes
and extends the concept of complex device control by
incorporating full 80 character line buffering, bidirectional printing, as well as drive and feedback control of
two four phase stepper motors.
,Figure 1. UPI-42 Pin Configuration·
Many microcomputer systems need real time control of
peripheral devices such as a pTinter, keyboatd, complex
motor control or process control. These medium speed
but still time consuming tasks require a fair amount of
system software overhead. This processing burden can
be reduced by using a dedicated peripheral control
processor
The Application Note assumes that the reader is familiar with the 8042/8742 and 8243 Data Sheets, and
UPI-4lA/42 Assembly Language. Although some background information is included, it also assumes a basic
understanding of stepper motors and dot matrix printer "
mechanisms. A complete software listing is included in
Appendix A.
6-716
230795-001
inter
AP-161
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l
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POWER
{
Vee - - _ +5'iUPPU
'ss - - _
GROUND
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E.... ENT COUNTER
Figure
2. UPI-42 Block Diagram
DOT MATRIX PRINTING
A dot matrix printer print head typically consistS of
seven to nine solenoids, each of which drives a stiff wire,
or hammer, to impact the paper through an inked ribbon. Characters are formed by firing the solenoids to
form a matrix of "dots" (impacts of the wires). Figure.4
shows how the character "E" is formed using a 5 x 7
matrix. The columns are labeled CI through C5, and
the rows RI throl,lgh R7. The print head moves left-toright across the paper, so that at time Tl the head is over
column Cl. The character is formed by activating the
proper solenoids as the print head sweeps across the
character position.
Dot matrix printers are a cost effective way of providing good quality hard copy output for microcomputer
systems. There is an ever increasillg demand for the
moderately priced printer to provide more functionality with improved cost and performance. Using stepper
motors to control the paper .feed ,and carriage/ print
head assembly motion is one way of enabling the dot
matrix printer to provide more capal!ilities, such as
expanded or cOl),tracted characters, dot or line graphics, variable line and character spacing, and subscript
or superscript ~rinting.
However, stepper motors require fairly complex contol
algorithms. Previous solutions involved the use pf a
main CPU, UPI, RAM, ROM, and I/O onboard the
peripheral The ,CPU ,:acted as ,supervisor and ·used
parallel .processing to achieve accU1'ate stl~pper motor
control via a" UPI, character buffering via' the I/O
device, RAM, 'and ROM. The CPU performed realtime decoding of each character into a dofmatl:ix pattern. This Application Note demonstrates that the
increased memory and performance of the UPI -42 facilitates integrating these control functions to reduce the
cost and component count.
TH~>PAINTERMECHANftnill '
The printer mechanism. used in this application is the
Epson Model 321Q. It consists of four basic subassemblies; the chassis or frame, the pa per'feCd, mechanism a.nd stepper motor, the carriage motion mechanism and stepper motor, and the print head assembly.
The paper feed mech~nism is a tractor !f~ed' type. It
accomodates up to 8.S' inch wide paper (not including'
traelorJeed portion) .. There iSll@ 'piaten as~uch; the
paptiris moved W(!)Ugh tl\epaper guide bytW6sprocketed wheels fflourited on a' center sprocket:shaft. The
sprocket shaft is driven by a four phase stepper motor.
Th'e roiation 'of the stepper motor is transmitted to the
sprocket shaft through a series of four red uction gears.
6-717
230795-001
-"i" ''J, (
AP·fln
I
CLOCK
1
:
I
t,
"
'"
i
.
1024 x 8, 2048 x 8
PROGRAM I
8-BITCPU
M~MORY
(ROM/EPROM)
.
8-BIT
,TIMER/COUNTER
II
II
' It
II
I
I
8-BIT
DATA BUS
OUTPUT REGISTER
8-BIT
STATUS
REGISTER
18
I/O LINES
r
I
8-BIT
DATA BUS
II\IPUT REGISTER
64x8,128x8
DATA MEMORY
1
. II
II
v
SYSTEM
INTERFACE
PERIPHERAL INTERFACE
AND
I/O EXPANSION
Flgunt 3. UPI·41A, ~2 Functlonl!ll BloCk Diagram
C1
C2
The carriage motion mechanism consists of another
four phase stepper motor,'whioh controls the left-toright or right-to-Ieft print head assembly motion. The
print speed is 80 CPS maximum. Both the speed of the
stepper motor and the movement of the print head
a~sembly are independently controllable in either direction. The rotation of the stepper motor is converted to
the linear motion of the print head assembly'via a series
of reduction gears and a topthed drive belt. The drive
belt also controls a second set of reduction gears which
advances the print ribbon as the print head assembly
moves.
'
C5
C4'
C3 '
Rl
DO D,D
RZ
,
0 0
R3
,
,
DO
R4
0 0 DD
,0,0 D'D
R5
,
R6
.
,~
,
"
',
! ~
..
R1,
\;' :i
'19..1'84. Character E In 5 x 7 Dot Matrix Form••
Two optical sensors ' provide feedback information, on
the carriage assembly position and speed. The fir~t of
these optical sensors, called the 'HOME RESET' or
HR, is mounted near the left-most physical position'to
which the print head assembly can move. As the print
head assembly approaches the' left-most position, a
flange on the print' head assembly interferes with the
light source and sensor, causing the output of the sehsor
to shift, from a logic level one to zero. The right-most
printer position is monitored in software rather than by
another optical sensor: The right-most print position is
a function of the number of.characters printed and the
distance'required to ,print them. '
The second optical sens9r, called the 'PRINT TIMING
SIGNAL" ,or PTS, provides feedback on carriage
stepper ' motor velocity and relative position within a
6~718
230795-001
PRINT HEAD ASSEMBLY
TOOTHED DRIVE BELT
REDUCTION GEARS
Figure 5. carriage Stepper ~tor ~mbly
given step of the motor. The feedback is generated by
the optical sensor as an "encoder disk" moves across it.
Figure 5 illustrates the carriage stepper motor, optical
, sensor, encoder disk and reduction gears, and dt:ive belt
assembly. The optical sensor outputs a pulse train with
the same period as the phase shift signal used to drive
the stepper, but slightly out of phase with it when the
motor is at a constant speed (see Software Functional
Block: Phase Shift Data for additional details). The
disk acts as a timing wheel, providing feedback to the
UPI software ofthe carriage speed, position, and optimum position for energizing the print head solenoids.
The two optical sensors are monitored under software
and provide the critical feedback needed to control the
print head assembly and paper feed motion accurately.
The process of stepper motor drive and control via
feedback signals is called ,"closed loop" stepper mo~or
control, and is covered in more detail in the software
discussion.
'
, contracted characters, as well as line or block graphics
(see Appendix B, Printer Enhancements). It also facilitates printing lower case ASCn characters 'with "lower
case; descenders." That is to say, certain lower case
letters (e:g. y, p, etc.) will print below the bottom part of
all upper case letters.
I
The print head assembly consists of nine solenoids and
nine wires or hammers. Figure 6 illustrates a print head
assembly. The available dot matrix measures 9 x'9. This
large matrix enables the J;lpson 3210 print mechanism to
Print a variety of character fonts, such as expanded or
DOT WIRE
MAGNETIC POLE
Figure 6. Print Head Solenoid Aeaembly
6-719
230795-001
~
STEPPER MOTOR
CONTROL
'? '5V
....
__--O~
P40-43
ON LINEISELECT
PRINT
MECHANISM
DRIVE
CIRCUIT
...
CONTROL: P50-53
(CURRENT LIMITING)
~
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it
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Figure 8. Hardware Interface Schematic
Port
No of
lines
1
8
2
2
1
1
2
2
4
5
5
'6
6
7
4
3
1
3
5
Bits
I/O
0-7
6
7
4.5
0-3
1-3
0
o
o
o
o
o
o
1
'0,2,3
0-3
o
DeSCription
Character dot column data to print head solenoids
(same)
Print head solenoid trigger
Host system data transfer handshaking (ACK/BUSY)
Carriage & paper feed stepper motors
Stepper motor select and current limiting
Paper End sense
Print head trigger reset
(unused)
External status switches; (LF, FF, TEST,
ON/OFF Line)
I
Figure 9. UPI-42 and 8243 I/O Port Map
Note: The notation used in the balance of this Application Note, when referring to a port number and a particular pin or bit, is Port 23 rather than Port 2 bit 3.
6-721
The two printer mechanism optical sensors, discussed
in the Printer Mechanism discription, are tied to the
two "Test Input" pins, TO and n, of the UPI-42
through a buffet circuit for noise supression. These
inputs are directly testable in software.
230795-001
AP-161
Host System Interface
The host system interfaces to the printer through a
parallel port to the UPI-42 Data Bus. Four handshaking signals are used to control data transfer; Data
Strobe (STB!), Acknowledge (ACK), Busy(BUSY),
and Online or Select. The Data Strobe line of the host
parallel port is tied directly to the UPI-42 WRI pin.
This provides a low going pulse on the UPI-42 WRI pin
whenever a data byte is written to the UPI-42. The ACK
and BUSY handshake s'ignals are tied to two UPI-42
110 port lines for software control of data transfer. The
"On Line" handshake signal is tied to a single-pole
single-throw fixed position switch, which externally
enables or disables character transfer from the host
system. Characters transmitted to the UPI-42 by the
host are loaded into the UPI-42 Data Bus Buffer In
(DBBIN) register, and the Input Buffer Full (IBF) interrupt and UPI-42 status flag are set (see Figure 9. UPI-42
and 8243 I 10 Ports).
CARRIAGE STEPPER MOTOR DRIVE SIGNALS (FORWARD)
L
Stepper Motor Interface
Port 4 (41-43) of the 8243, provides both carriage and
paper feed stepper motor phase shift signals to the
printer mechanism drive circuit. Each of the two
stepper motors is driven by 2 two phase excitation
signals (4 phases). Figure 10 shows the wave form for
each stepper motor. Each signal consists oftwo components (Sig. I AlB & Sig. 2 C/D) 180 degrees out of
phase with the other. Each of these signal pairs (AI B &
eli) is 90 degrees out of phase with the other pair. For
each signal pair, one port line supplies both halves by
using an inverter.
Each of the resulting eight stepper motor drive signals is
interfaced to a discrete drive transistor through an
inverter. The emitter of the drive transistor is tied to the
open collector of the inverter to provide high current
sinking capability for the drive transistor. Each half of
the motor winding is tied to the collector of the drive
transistor (see Appendix C, Printer Mechanism Drive
Circuit Schematic).
Each stepper motor requires two current levels for
operation. These levels are' called "Rush" current and
.. Hold" current. Rush current refers to the high current
required to cause the rotor to rotate within its windings
as the polarity of the power applied to the windings is
'changing. Each chll;nge in the polarity of the power
applied to the motor windings is called a step or phase
shift. Hold current refers to the low level of current
required to stabilize and maintain the rotor. in a fixed
position when the the polarity applied to the windings is
not changing. Hold current is simply Rush current with
a current limiting transistor switched in. Switching
from Hold to Rush current "selects" or enables that
stepper motor to move with the next step signal output.
In the balance of this Application Note, the term
"select" will be used to refer to turning on Rush current,
and "deselect" will refer to switching to HoM currrent.
PAPER FEED STepPER MOTOR DRIVE SIGNALS
Figure 10. Stepper Motor Step Sequence
Waveforms
Three 8243 port lines are dedicated to the select! deselect control of the two stepper motors. One line is for
the paper feed stepper motor, and two lines are for the
carriage motion stepper motor (80 and 132 column).
These lines are labeled SLF, 80Col, and 132Col, and are
8243 PORT 53, 52, and 51, respectively.
By varying the voltage applied to the stepper motor
biasing circuit and the current, it is possible to vary the
distance the motor moves the print head assembly with
each step. Enabling one of two different voltage biasing
levels, and changing the timing rate at which the motor
is stepped, facilitates either 80 or 132 character column
printing. Only 80 character column printing is implemented in the software design. Appendix B, Printer
Enhancements, details the software algorithm for han'
dling 132 character printing.
Print Head Interface
A total of eleven II 0 lines are used to control the print
head solenoids and solenoid firing (see Figure 9 above).
Nine are used for character dot data, one for the Print
Head Trigger, and one for Reset of the Print Head
Trigger circuit. Each of the nine character dot data lines
'is buffered by an open collector hex inverter.
6-722
230795-001
inter
AP·18t
The Print Head Trigger output is tied to the Trigger
input of a 555 Monostable Multivibrator. The output
pulse generated by the 555 triggers the print head solenoids to fire. The 555 Output pulse width is independent of the input trigger waveform. The pulse width is
determined by an RC network across the 555 inputs and
the voltage level applied to the Control Voltage 555
input. The 555 Output is tied to the base of a PNP
transistor through an inverter, biased in a normally off
configuration. The PNP transistor supplies enough
drive to pull up the open collector inverter on each print
head solenoid line, Port 10-17 and 26. The 555 output
pulse momentarily enables the print head solenoid line
open collector inverter output, turning on the solenoid
drive transistor, and firing the print head hammer. The
555 Ouput pulse width is approximately 400 us. Further
details of the print head firing operation can be found in
the software description below.
Miscellaneous Interface Signals
The 8243 Port 5 pin 0 is tied to the Paper End Detector,
a ree4 switch located on the printer paper guide. This
sensor detects when the paper is nearly exhausted.
Three LED status lights complete the hardware interface design. One status light is used for each of the
following: Power ON/OFF, On/Ofr Line, and Out of
Paper.
Open loop is simply continuous pulses to drive the
motor at a predetermined rate based on the voltage,
current, and the timing of the step pulses applied.
Closed loop control is characterized by continuous
monitoring of the stepper motor, through feedback
signals, and adjusting the motor's operation based upon
the feedback received.
C. Stepper Motor Drive Pha.. ShIft
or Step Sequence
Each change in the polarity of the power applied to the
motor windings is called a step or phase shift. The
sequence of the steps or phase shifts, and the pattern of
polarity changes output to the stepper motor, determines
the directiOn of rotation.
Figure 10 shows the waveforms for each of the two
stepper motors. Figure II lists the step sequence for
carriage motor clockwise rotation, which moves the
print head assembly Left-to-Right. Figure II also lists
the step sequence for counterclockwise rotations; the
print head assembly moves, Right-to-Left. Figure 12
lists the step sequence for the paper feed stepper motor
clockwise drive. The phase sequence, for either stepper
motor, may begin at any point within the sequence list,
but must then continue in order.
SteP No.
A-Step
B-Step
C-Step
D-Step
1
On
On
Off
Off
Off
Off
On
On
Off
On
On
Off
On
Off
Off
On
BACKGROUND
Before a detailed discussion of the software begins, a
few terms and software functions referenced throughout the software need introduction.
2
3
4
A. What Is a Stepper Motor?
A stepper motor has the ability to rotate in either
direction as well. as start and stop at predetermined
angular positions. The stepper motor's shaft (rotor)
moves in precise angular increments for each input step.
The displacement is repeated for each input step command, accurately positioning the rotor for a given
number and sequence of steps.
Carriage stepper motor rotates clockwise
Print head assembly moves from left to ~ight
Step No.
A-Step
B-Step
C-Step
O-Step
1
On
On
Off
Off
Off
On
Off
Off
On
Off
On
On
Off
The stepper '!l0tor controls position, velocity, and ,
direction. The accuracy of stepper motors i,s generally 5
percent of one step. The number of steps in each revolution of the shaft varies, depending on the intended
application.
2
,3
4
Off
On
On
,B. Open/Closed Loop Stepper Motor Drive and
Control
The carriage stepper motor is closed loop driven. The
paper feed stepper motor is open loop driven.
Carriage stepper motor rotates counter clockwise
Print head assembly \lloves from right to left
There are two major types of stepper motor control
known by the broad headings of open and closed loop.
FIgure 11. Carriage Stepper Motor Step
Sequence
6-723:
230795-001
inter
AP-161
Step No.
A-Step
B-Step
C-Step
D-Step
1
On
On
Off
Off
Off
Off
On
On
On
Off
Off
On
Off
On
On
Off
2
3
4
placement is required to accelerate a stepper motor to
its full speed. Conversely, deceleration must begin some
time before the final angular position. The time interval
and angular displacement of the carriage stepper motor
translates into the distance the print head assembly
travels before it reaches a constant speed. The distance
traveled during acceleration is constant. The distance
the print head assembly travels during deceleration
must be the same as the distance traveled during acceleration in order to accurately align the £.haracter dot
columns from one line to the next.
Figure 12. Paper Feed Stepper Motor Step
Sequence
E. Stepper Motor Predetermined
Time Constant
C. Acceleration and Deceleration
of Stepper Motors
The carriage stepper motor starts from a fixed position,
accelerates to a constant speed, maintains constant
speed, and then decelerates to a fixed position. Printing
llJIlY occur from the time and position the print head
assembly reaches constant speed, until the time and
position the print head assembly begins to decelerate
from constant speed. Whether printing occurs during
any carriage stepper motor drive sequence is controlled
by software. Figure 18, below, illustrates these components of print head assembly line motion.
Due to inertia, a finite time interval and angular dis-
Whenever the stepper motor is stepped, or energized,
the angular velocity of the rotor is greater than the
constant speed which is ultimately required. This is
called "overshoot." The frictional load of the carriage
assembly (motor rotor, reduction gears, drive belt and
print head assembly, or paper feed sprocket shaft and
wheels) provides damping or frictional load. Damping
slows the motor to less than the required constant speed
and is called "undershoot" (see Figure 13, Carriage
Stepper Motor Drive Timing). A constant rate of speed
is achieved through the averaging of the overshoot and
undersffoot within each step.
HRSIGNAL
PT.
DOT COLUMN
PRINT
Tx
Tx
Tx
TX
STEP
SIGNAL
OUTPUT
.1
LCONSTANT SPEED
UNDERSHOOT
7
EQUATIONS:
PTe = PREDETERMINED TIME CONSTANT
PT.' T,- TN
T, •.. Te TIME:::. PTe + Tx
T, TIME = PTe
Ta. ';' T11 Time =PTe
Figure 13. Carriage Stepper Motor Drive
Timing
6-724
230795-001
inter
Ap·181
The Predetermined Time (PT) Constant is the time
required to average the overshoot and undershoot of
the particula~ stepper motor for a desired constant ra~e
of speed. The PT also is the time required to move the
print head assembly .a specific distance, acounting for
both overshoot. and undershoot of the stepper motor.
Changing the Predetermined Time Constant changes
the angular displacement of the stepper motor rotor,
this in turn changes the output. Figure 14 lists the Time
Constants for both standard and condensed character
printing. Figure IS lists the paper feed stepper motor
Time Constants used for various line spacing formats.
This Application Note implements standard character
p.rint and paper feed (6 lines per inch) Time Constants.
See Appendix B, Printer Enhancements, for details on
implementing non-standard Time Constants.
Character mode
Predetermined time
Standard or Enlarged
Character
2.08ms
+10%
-4%
Condensed Character 4.16ms
+10%
-4%
PTlIIG_
~:::
D ......
II
---.J
Figure 16. PTS Lags PT Timing
-~
SOLENOID
DRfYEPULSE
I
.PHASE
Paper feed tIme
150msl423mm
113msl318mm
100msl2.82mm
D.... PULO.
~
~=""I
--:-1
c ......
D ......
o12mm(1/216") 11 pulse
4 23mm(1/6") 136 pulses
3.18mm(1/8") 127' pulses
2 82mm(1I9") 124 pulses
RMlNI!DTlME
,I
MOTOR A PHASE
Paper feed pitch
I!!iL~1
IL--.-H;!r--.
(PRE
PT8 SKJNAL
Figure 14. Carriage Stepper Motor
Predetermined Time Constants
:t. . . .
IDL!NOID
I
]
-
11
(PRED~II:".INED
r'liaoLENolD DRIVE
I
TIME)
~LSE (0 4ms MY)
I
II
I
.1
I
I,
Figure 17. PTS Leads PT Tfmlng
Approx 6.6 IInes/s (continuous feed)
Approx 88 Ilnes/s (contInuous feed)
Appro~. 10 IInes/s (continuous feed)
Figure 15. Paper Feed Stepper Motor
Predetermined nme Constants
D. Relationship Between PTS and PT
Figure 13 illustrates ho'Y PTS lags PT at the start of
acceleration, and .moves to lead PT as the motor
achieves constant speed. Figure 13 also illustrates the
relationship between HR, PTS, PT, acceleration, constant speed, and printing. Figure 16 and 17 illustrate the
relationship between PTS and PT during acceleration
;
and at constant speed.
PTS is the point of peek angular velocity within a step
of the motor. PTS is a function of the slot spacing on
the encoder disk, shown in Figure 5. The spacing is
determined by the mechanics of the printer m\chanism.
When the carriage stepper motor is acceillrated from a
fixed position, the effects of damping slows the angular
velocity of engergizing the stepper motor. This causes
PTS to occur after the PT, or PTS lags PT. When PTS
lags PT, the next step signal is output at PTS rather
than at PT. If the step signal is outputted at PTS, the
rotor could be midway through a rotation. Energizing
the motor at PT could cause it to bind or shift in the
wrong direction. When the carriage stepper m.Qtor is at
a constant rate of speed, PTS leads PT and the step
signal is:out'pl1l' at PT (see Figure 13).0. Stored Time
Constants.
230795-001
inter
A~161
The time between each step, for a constant number of
steps, required for the motor to reach a constant speed,
is calculated and stored in Data Memory during acceleration. The values stored are used, in reverse order,
during deceleration as the Predetermined Time (PT)
Constants. This ensures that the acceleration and deceleration distance traveled by the print head assembly is
the same, and that it accurately aligns character dot
columns from one line to the next during printing. The
time values stored are called "Stored Time. Constants."
Steps Tl through T 11 in Figure 13, representthe Stored
Time Constants.
H. Print Head Assembly "Home'~ Position
The "logical" Home position for the print head assem~
bly is the left~niost position at which printing begins
(for L-to-R motion) or ends (for R-to-L motion). The
"physical" Home position is the logical HOME posi-,
tion, plus the distance required by the carriage stepper
motor to fully accelerate the print head assembly to a
constantspeed. Printing can only occur when the print
head is moving at a constant speed. The printer mechanism manual stipulates eleven step time periods are
required to ensure the the print head assembly is at a
constant speed. These eleven step time periods are the
Stored Time Constants described above. Fig:ure 18
illustrates the components of print head assembly line
motion and character printing.
The equations for the Stored Time Constants are given
at the bottom of Figure 13, Carriage Stepper Motor
Drive Timing.
.'
Left-to-Right Printing:
Deceleration
Begins
Acceleration
Begins
Constant
Speed, Printing
Can Begin
I
..
I
(direction of printing)
I
Output
Stored
Time Constants
Store Tiine
Constants
I
Physical
Left-most
Position.
Space Available For Printing
Home
(HR)
Right-most Physical
Print
Right-most
Position
Position
Right-to-Left Printing:
ISto,. Tlm~i
;
I
Output
Stored
Constants
Constants
'4
(direction of/printing)
I
I
Constant
Speed, Printing
Can Begin
Deceleration
Begins
I
Acceleration
Begins
Figure 1.8. Components of Prlllt Head
Assembly Line Motion and Printing
230795-001
inter
AP-161
SOFTWARE
Introduction
The five principal parts are incorporated into ten software blocks, listed below.
The software description is presented in three sections.
First, a brief overview of the software to familiarize the
reader with the interdependencies and overall program
flow. Second, data and program memory allocation and
status registerflllg definitions. And third, each of the ten
software blocks is presented with its own flowchart.
I.
2.
Power On/ Reset Initialization
Home Print Head Assembly
3. External Status Switch Check
4. Character Buffer Fill
5. Carriage Stepper Motor Drive and
Line Printing
6. Accelerate Stepper Motor Time Storage
7. Process Characters for Printing
8. Translate Character-to-Dots
9. Decelerate Carriage Stepper Motor
10. Paperfeed Stepper Motor Drive
Software Overview
The softwate·is written in Intel UPI-4IA/42 Assembly
Language. A block structure approach is used for ease
of development, maintance, and comprehension. The
software is divided into five principal parts.
I.
2.
3.
4.
5.
Initialization
Character Buffering or Input
St~pper Motor Drive anI;! Control
Character Processing
Character Printing or Output
Flow Chart No. I illustrates the overall software algorithm. Below, is a description of the algorithm.
MAIN PROGRAM BODY
CARRIAGE $TEPPER MOTOR DRIVE a LINE PAINTING
tFl.OW<>OAAT ..,
Flow Chart No.1. Main Program Body
6-72~
230795-001
"n+_r
.111'e'
Ap·161
Upon power-on.or reset, a software' and hardware
initialization is performed. This stablizes and sets inactive the printer hardware and electronics. The print
head assembly is then moved to establish its HOME
position. The default status registers are set for character buffering, carriage, and paper feed stepper motor
drive. The External Stattis switches art; checked;
FORM FEED, LINEFEED, ON/OFF LINE, and
Character Print TEST. If the printer is ON LINE, the
software will loop on filling the Data Memory Character Buffer.
Memory and Register Allocation
Data Memory Allocation (RAM)
The UPI-42 has 128 bytes of Data Memory. Sixteen
bytes are used by the two 8 byte r~gister banks(RBO and
RBI). Sixteen additional byteS' are used for the Program Stack. The Stored Time Constants utilize IJ
bytes, while the stepper motor phase storage requires 4
bytes. Below is a detailed descFiption of Data and Program Memory
Hex Address
Description
Character or data input to the UPI-42 is interrupt
driven. Characters sent by the host system set the Input
Buffer Full (IBF) interrupt and the IBF Program Status
flag. Character ,input servicing (completed during the
paper feed and carriage stepper motor drive end Delay
subroutine) tests for various ASCII character codes,
loads characters into the Character Buffer (CB), and
repeats until one of several conditions sets the CB Full
status flag. Once the CB Full flag is set, further character transmission by the host system is inhibited and
printing can begin.
The carriage stepper motor is initialized, and drive
begins for the direction indicated. The motor isaccelerated to constant speed, printable character codes are
translated to dot patterns and printed (if printing is
enabled), and the motor is decelerated to a stop. Two
timing loops guarantee both constant speed and protection (Failsafe Time) against stepper motor burn out due
to high current overload. The two optical sensors, described in the Printer Mechanism section above, are
constantly monitored to maintain constant speed, and
trigger print head solenoid firing.
Once the line is printed and the carriage stepper motor
drive routine has been completed, a Linefeed is forced.
The paper feed stepper motor drive subroutine tests the
number of lines to move, and energizes the paper feed
stepper motor for the required distance. The lines per
page default is 66; if 66 lines have bel;n received, a
Formfeed to Top-of-Next-Page is performed. The Tol'Of-Page is set at Power On/ Reset.
' ,
."
When the EOF code is received, the EOF status flag is
set. When the last line has been printed, the EOF check
will force the print head assembly to the HOME position. The EOF flag is tested following each Paper Feed
stepper motor drive. The next entry to the External
Status Check subroutine begins a loop which waits for
input from either the external status switches or the
hoM~mm.
'
The software character dot matrix used in this application is 5 x 7 of the available 9 x 9 print head solenoid
matrix. Although lower case descenders and block/line
graphics characters are not implemented, Appendix B,
Printer Enhancements, discusses how and where these
enhancemerits could be added. The software Implements the full 95 ASCII printable charac.ters set.
2F-7FH
80 Characte, Line Butler (80 Byt. .)
Stored Time Conalanb Bufler (11 Bytes)
24H
Unused
23H
Charlet" Print T".I ASCII Code
22H
Pseudo Regialfr' Paperf•• d Stepper
Motor Lall Ph .... lnd.rect Address
Slart Temporary Storage
21H
Pseudo Reg'lter Cii'.... ge Stepper
'OH
Pseudo Reg'lter' 'Last Ph ••• of
Stepper Motor Not Being Dnven
18-1FH
Register Bank 1 Character ProceSSIng
Motor ForwardfReverse L.at Phas.
8 Level Slack
0-01H
Register Bank 0 Stepper Motor
Forward/Reverse Acceleralion/Drlve
Figure 19. Data Memory Allocation Map
Register Bank 0 is used for stepper motor drive functions.
Register Bank I is used for character processing. Each
register bank's register assignments is listed in Figure 20 •
and 22, respectively. Each register bank has one register
allocated as a Status Register. Figure 21 and 23 detail the
Status Register flag assignments. Note that bit 7 of each
Status Byte is used as a print head assembly motion
direction flag. This saves coding of the Select Register
Bank (SEL RBn) instruction at each point the flag is
checked.
Register Bank 0
Register
Program Description
Label
RO
TmpROO
TStrRO
GStR20
PhzR30
CntR40
TConRO
LnCtRO
OpnR70
R1
R2
R3
R4
RS
R6
R7
RBO Temporary Register
Store Time Register
General Status Register
Stepper Motor Step Register
Count Register
Time Constant Register
Line Count Register
Available. Scratctl
Figure 20. Register Bank 0 Register Assignment
230795-001
inter
AP-161
Bit
illustrates the Program Memory allocation map by
page.
Dellnltlon
Accel/Decelerate Drive
Page
Ready"'/NotRdy"O
1-Do Not PMI/O" Pront
1 Form Feed/O'Line Feed
...._ - - , FallSafe/OcConstant
Hex Addre..
Description
Time Window
AccellOeceleratlon Irltttalizatlon,
, Done/O' Not Done
Stepper Motor at Speed and
PMt Head Not Left of Home
, Sync/O=Not Sync'd, Pront
Page 7
1182-2Q47
Character to Dot Pattern
Lookup Tibl.; Page 2:
ASCII 50H·7EH
Page 6
1536-1791
Character to Dot Pallern
Lookup Table; Page 1:
ASCII,20H.4FH (sp·M)
Page 5
1280-1535
Miscellaneous Subroutines:
InltAI/AIiOIf
Clear Data Memory
Home Print Head Assembly
Character Print Test
Initialize Carriage Stepper
Motor
Delay
Stepper Motor Deselect
Page 4
1024-1279
Paper Feed Stepper
, Motor Drive
Page 3
768-1023
Stepper Motor Slep LookUp
Table(lndexed)
Character Processing and
Translaloon
Print Head Firing
Page 2
51-767
Carroage Stepper Motor
Acceleration
Time Calculation and
Storagp
Stepper Motor Deceleraloon
Head Inltl811ze and Fire
Stepper Motor Direction
L-to-R-', R-to-LoO
Figure 21. Register Bank 0 Status Byte
Flag Assignments
Reglater
Program
Label
Deacrlptloll'
AO
Al
TmpAl0
CAdrAl
A2
ChStAl
A3
A4
CDtCAl
CDotAl
A5
CCntAl
A6
R7
StrCRl
OpnR71
ABO Temporary Aeglster
Character Data Memory
Address Aeglster
Character Processing
Status Byte Aeglster
Character Dot Count Aeglster
Character Dot Temporary
Storage Aeglster
Character Count Temporary
Register
Store Character Aeglster
'Available/Scratch
Figure 22. Register Bank 1 Register A..lgnment
Bit
Dellnltion
CB Registers 1=lnltlsloze
/0=00 Not lnobaloze,
I=CR/(LF)/O=Not CR/(LF)
Character Buffer
Full=1INot Full=O,
I=EOF/O=Not EOF
(uhused)
...._ _ _ _ _ _ Character Lookup Table Page
Page 1
256-511
Carroage Stepper Motor Drove
Page 0
0-255
Inltlahzatlon - Jump-on-Reset
Main Program Body
External Slatus SWitch
Check
Character Buffer Fill
l=Pg, " O=Pg 2
Character Initialized.
Figure 24. Program Memory Allocation Map
1= Done/O= Not Done
Carnage Stepper Motor Direction
L-to-R.t, R-to-LcO
Software Functional Blocks
Below is a decription and flow chart for ea~h of the ten
software blocks iisted above.
Figure 23. Register Bank 1 Status Byte
Flag Assignments'
Program Memory Allocation (EPROM/ROM)
1. Power-On/Reset Initialization
The UPI-42 has 2048 bytes of Program Memory
divided int~ eight pages, each 256 bytes. Figure 24
The"first operational part in Flow Chart No. I is the
Power-On or Reset Initialization. Flowchart No. 2
illustrates the Initialization sequence in detail.
6-729
230795-001
inter
(
AP-161
START
The Data Memory locations OOH through I FH are not
cleared. These locations are Register Bank 0 (OOH07H), Program Stack (OSH-17H), and Register Bank I
(JSH-IFH) (see Figure 19). Clearing the Program Registers or Stack would cause the initialization subroutine
to become lost. The registers are used from the beginning of the program. Care is tliken to initialize' the
registers and stack accurately prior to each program
subroutine as required.
)
1"
DISABLE INTERRUPTS
J
J
Upon power-on, it is necessary to initialize the two
stepper motors, verify their operation, and locate the
print head assembly in the left-most 'HOME' position.
This sequence serves as a system checkout. If a failure
occurs, the motors are deselected and the external status
light is turned on. Each stepper motor is selected and
energized for a sequence of four steps. This serves to
align and stabilize each stepper motor's rotor position,
preventing the rotor from skipping or binding when-the
first drive sequence begins.
RESET PRINT HEAD TRIGGER
TURN OFF ALL PRINT HEAD SOLENOIDS
SET PRINT HEAD TRIGGER INACTIVE
SET HOST SVS",M HANDSHAKE ACTIVE
CLEAR RBO/RB1 STATUS REGISTERS
I
CLEAR DATA MEMORY (2OH·7FH)
I
+
I INITIALIZE CARRIAGE AND PAPER FEED STEPPER MOTORS .1
L
I
I
+
HOME PRINT HEAD ASSEMBLY
(FLOWCHART #4)
~
~ET DEFAULT REGISTERS AND FLAGS
1
RETUIlN
/
At the end of each stepper motor's initialization, the last
step data add res; is stored in one of the Data Memory
pseudo registers. The last step data address is recalled at·
the beginning of the next corresponding stepper motor
drive sequence, and used as the basis of the next step
sequence. This ensures that the stepper motor always
receives the exact next step data, in sequence, to garantee smooth stepper motor motion. This also garantees
the motor never skips or jerks, which would misalign
the start, stop, and character dot column positions. A
stepper motor not being driven has its last phase data
output held constant to stabilize it.
.
I
I
Following any stepper motor drive sequence of either
motor, a delay of 30-60 ms occurs by switching the
curr.ent to Hold Current, stabilizing the motor before it
is deselected.
Flow Chart No.2. Power-On/Reset Initialization
Initialization first disables both interrupts. This is done
. as a precaution to prevent the system software from
hanging-up should an interrupt occur before the proper
registers and Data Memory values are initialized.
Initialization then deactivates the system electronics. This is also a precauti0l) to protect the printer
mechanism and includes the print head solenoid (trigger
and data) lines and the stepper motor select lines. The
host system handshake signals are activated to inhibit
data transfer from the host until the printer is r~ady to
accept data.
Next, Data Memory is cleared from 20R to 7FH. This
includes; the SO byte Character Buffer, the 11 byte
Stored Time Constants buffer, and the 4 bytes used as
pseudo registers. The pseudo registers are Data Memory
locations used as if they were registers. They serve .as
storage loacations for step data used in accurately
reversing the direction of the carriage stepper motor,
and stablizing either of the stepper motors not being
driven.
2. Home Print Head Assembly
At the end of the carriage stepper motor four step
initialization, the output of the HR optical sensor is
tested. The level of the HR.sigrial indicates which drive
'sequence will be required to 'HOME' the print head
assembly. If the print head assembly is to the right of
HR, HR is high, the print head assembly need only be
moved to from .Right-to-Left until HR is low,. then
decelerated to locate the physical home position. If HR
is low, the print head assembly must be moved first
Left-to-Right until HR is high, then Right-to~Left to
locate both the logical and physical 'HOME' positions.
In each case, the software accelerates the carriage
stepper motor, generating the Stored Time Constants
then decelerates the stepper motor using the Stored
Time Constants (see Background section above). Flow
Chart No.3 details the HOME print head assembly
subroutine. Figures 13 and IS illustrate the components
of acceleration and print head assembly line motion.
6-730
230795-001
AP-161
C?
I
lIT DO NOT PRINT STATUS 'LAO
1
+
<
HR"
+"
/
CAAAI:l~~=:(~==';J~.TO-R1
I
CARRa:t~:e~,::(~=~.T().Ll
I
HOM'E position, the software enters a loop which continually monitors the four external status switches, and
exits if anyone is active. Flow Chart No.4 details the
External Status Switch Check subroutine.
+
+
Flow Chart No.4. External Status Switch Check
7
If the LINEFEED or FORM FEED switch is set, the
Paper Feed subroutine is called. The Paper Feed subroutine is discussed in detail below. If the ONLINE
switch is set, the Character Buffer (CB) Fill subroutine
is called.
/
CLIAR DO NOT PRINT FLAG
I
~
"ETURN
I
If the Character Print TEST switch is set, the Data
Flow Chart No.3. HOME Print Head Assembly
The carriage stepper motor drive subroutines used to
HOME the print head assembly and to print, are the
same. A status flag, called Do-Not-Print, determines
whether the Character Processing subroutine is called.
The flag is ,set by the subroutine which calls the Carriage
Stepper Motor Drive subroutine. Details of the carri~ge and paper feed stepper motor drive and character
processing subroutines are covered separately below.
3. External Status Switch Check
Once the system is initialized and the print head is at the
Memory Character Buffer(CB) is automatically loaded
with the ASCII code sequence, beginning at 20H (a
Space character), the first ASCII printable character
code. The software then proceeds as if the CB had been
filled by characters received from the host system. The
External Status Switch Check subroutine is exited and
character printing begins. When the line has finished
printing, a linefeed occurs (as shown in the main program Flow Chart No.1) and the program returns to the
External Status Switch Check subroutine. If the TEST
switch remains active, .the ASCII character code is
incremented and program continues as before. This will
eventually print all 95 ASCII printable characters. An
example of the TEST printer output, the complete
ASCII character code printed, is shown in Figure 25.
CHARACTER BUfFER FIl.L
(FLOWCHART #5)
Flow Chart No.4. ExtelT!al Status Switch Check
6-731
230795-001
inter
AP-161
4. Caracter Buffer Fill
The Character Buffer (CB) Fill subroutine is called
from three points within the main program; External
Status Switch subroutine, and the Delay subroutine
fo~lowing the. carriage and paper feed stepper motor
dnve subroutmes. Flowchart No.5 details the Character Buffer Fill subroutine operation.
C?
<""
"'ult"
Character input is interrupt driven. When the IBF
interrupt is enabled, a transmitted character sets the
IBF interrupt and IBF Program Status flag. Three
instructions make up the IBF interrupt service routine ..
This short routine disables further interrupts, sets the
BUSY handshake line active, inhibiting further transmission by the host, and returns. The subroutine can be
executed at virtually any point in the software flow
without effecting the printer mechanism operation.
Processing of the received character takes place during
one of the three program segments mentioned above.
The BUSY line remains active until the character is
processed by the CB Fill subroutine.
'
RETURN
v
U "".
t
--v'"
I
.?'
,
N+
I
ENABLE INTERRUPTS
<
INPUT BUFFER FULL
"-
CHARACTER BUFFER
INITIALIZATION DONE
I
RETURN
N
~v
BUFFER FILL
I
DECREMENT CHARACTER
BUFFER SIZE
*
<
END OF CHARACTER BUFFER
<
I
INITIALIze CHARACTER
/N
v
"
t
CHARACTER BUFFER PAD
v
seT EXIT FLAGS
v
LOAD C8 WITH 20H
,
t"
ACKNOWLEDGE A READ CHARACTER
<
I
ASCII PRINTABLE CHARACTER
V
<
L.OAD CHARACTER INTO
CHARACTER BUFFER
~
->l
eFt OR LF
N
I
LOAD CB WiTH eFt
SET C8 PAD FLAG
ENABLE INTERRUPTS
READ NEXT CHARACTER
ASSUME IT'S Lf & IGNORE
<
EOF
N
>v--t
SET EOF " CB FUll FLAGS
CL.EAR CB PAD FLAG
J
RETURN
<
FORMFEEO
N
:>v-t
seT FF " CB FULL FLAGS
CLEAR CB PAD FI.AG
t
RETURN
.
I
LOAD CB WITH 20H
I.
I
DECREMENT CB ADDRESS
+
CB FULL OR
CBPAD
RETURN
/v
I
+
N
I
ENABLE INTERRUPTS
RETURN
Flow Chart No.5. Character Buffer Fill
The approximate 80 ms total pre-deselect delay at the
end of each stepper motor drive sequeQ.ce, 40 ms c.. r,riage and 40 ms paper feed stepper motor pre-deselect
delay, is sufficient to load an entire 80 character line.
Half the CB is filled at the end of printing the current
line, and the second half is filled at the end of a paper
feed. There is no time lost in printing throughput due to
filling the character buffer.
.
I
l-
The CB is 80 bytes from the top of Data Memory
(30H-7FH). It is a FIFO for forward, left-to-right printing, and a LIFO for reverse, right-to-Ieft, printing.
Loading the CB'always begins at the top, 7FH. One
character may be loaded into the buffer each time the
CB Fill subroutine is called.
The CB is always filled with 80 bytes of data prior to
printing. If the total number of characters input up to a
Carriage Return (CR)/ Linefeed (LF), does not c.ompletely fill the CB, the CR code is loaded into the CB
and the balance of the CB is padded with 20H (Space
Character) until the CB is full. A Linefeed (LF) character following a Carriage Return is ignored. A LF is
always forced at the end of a printed line. When the CB
is full, the CB FUll status byte flag is set and printing can
begin.
A LF character alone is treated as a CR/ LF at the end
of a full 80 character line. This is a special case of a
printed line and is handled during character processing
for printing (see No.7, Processing Characters for Printing, below). A Formfeed (FF) character sets the FF
status byte flag. The flag is tested at each paper feed
stepper motor drive subroutine entry.
When the software is available to load the CB with a
character, entry to the CD Fill subroutine checks three
status flags; CB Full, CB Pad, and IBF flag. If the CB
Full flag is set, the program returns without entering the:
body of the CD Fill subroutine. The CB Pad flag will
cause another Space character to be loaded. If the IBF'
flag is not set, the program returns. If the IBF flag is set,
the character is read from the Data Bus Buffer registe'r,
tested for printable or nonprintable ASCII code, and, if
printable, loaded into the CB. If the character is a
non-printable ASCII code and not an acceptable
ASCII control code (CR, LF, FF, EOF), a 20H (Space
Character) is loaded into the CB.
Exiting the CB Full subroutine with the CB Full or CD
6-732
230795-001
inter
,<
Ap..181
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IJrIITJAUZIi!TtMlCONITAffTREGlST'M
IliUCTCAAflIAQIIST1iflNftMOrOll
r-----+
LOAD TtMER WlTHPT
M.UtCMPEfI=~&l1:.CAARIAGE
OUTPUT S1V OATA
I
"'."....
<
I
........
I
.
CAMIAGE&'JPfIERMOTOfI
ATC0Nl'fANT8PeI!D
J'
ro< -...
,
Figure 26 illustrates the carriage stepper motor-step
sequence verses the actual step data output for clockwise rotation, Left-to-Right motion, and counterclockwise rotation, Right-to-Left print head assembly
motion. An eight step sequence is depicted in the figure .
Note that the sequence for Right-to-Left motion is the
reverse of the sequence for Left-to-Right motion. Note
also, that for the L-to-R sequence step 4 is the same as
step <1, step 5 the same as step I, etc., through step 7
matching step 3. The four step sequence simply repeats
itself until the motor is stopped via the Deceleration
subroutine.
SlTA.1tJ.4,1'LAO
SE'TL·TOofIFUG
-,..
' I
lCM_~--1
>
1~*7)
I
Ii'f,IOCES8 CHMAC1l!RS
I'OfIPAIHTtM(I
(Fl.OWQtMT iii)
Next, the carriage and paper feed stepper motor step
data is-initialized. The last step data output to the paper
feed stepper motor is loaded into the Last Phl;lse pseudo
register. This data is masked with each step data output
to the carriage stepper motor. Masking the step data in
this manner guarantees the pa per feed motor signals do
not change as the carriage stepper motor is being
.
driven.
I
SETUP NEXT STEP DIII'A
<
+
.
,
STEP stQUENCE DOfo«.
R£8TART8liQUI!NCE
I
L-to-R
Motion
Sequence
Phase/Step
Data
(3210)
R-to-L
Motion
Sequence
(32 1 0)
BCD
0
1
2
3
1001
1010
01 10
0101
7
6
5
4
0000
0001
0010
00 11
4
5
6
7
1001
1010
0110
0101
3
2
1
0
0100
0101
0110
0111
LOAD NOT $TlP DATA
r-l
1<
.
,
"11MEOUT
"""
Figure 26. Carriage Stepper Motor
Phase/Step Data
SETI'AILSAfEsrATUSI'LAQ
· ...""""",
·
·
.... I
~TIMEfI WITH FAILSAfe
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READYTOPAINT
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I
MOTOR I
DEiLAY Dt:Si6LECT CARRIAGE STEPPER
~
'low Chart No. 6.
ca;'rlag~ Ste;',
Moto, Drive/Line Printing
When the carriage stepper motor is driven for a specific
direction of print head assembly motion, the step
sequence must be consistant for the motion to be
smooth and accurate. The same holds true for the transition from one direction of motion to the other. Since
the sequence for one direction is the opposite for the
other direction, incrementing the sequence for L-to-R
and decrementing for R-to-L provides the needed step
data flow. For example, referring to Figure 26, if the
print head assembly moved L,to-R and the last step
output was #1, the first step for R-to-L motion would be
#7. Thus, when the carriage stepper motor is initialized
for a clockwise (L-to-R) or counterclockwise (R-to-L)
rotation, the last step sequence number is incremented
or decremented to obtain the proper next step. In this
way, the smooth' motion of the stepper motors is
assured.
The step data' is referenced indirectly via the step
sequence number. The ste'p data is stored in a Program
Memory-look-up table whose addresses correspond to
the step sequence numbers. For example, as shown in
6..734
230795-001
inter
AP·161
Figure 26, at location 0 the step data "1001" is stored.
This me,thod is particularly well suited to the UPI-42
software. The UPI-42 features a number of instructions
which perform an indirect move or data handling op.eration. One of these instructions, M OVP3 A,@A, unlike
the others, allows data to be moved from Page 3 of
Program Memory to any other page of Program
Memory. This instruction allows the step data to be
centrally located on Page 3 of Program Memory and
accessed by various subroutines.
Each time the carriage stepper motor step data is output, the step data lookup table address is incremented
or decremented, depending upon the direction of rotation, and tested for restart ofthe sequence. The address
is tested because the actual step data, Figure 26, is not a
linear sequence and thus is not an easily testable condition for restarting the sequence. The sequence number
is tested for rollQver of the sequence count from 03H to
04H and clockwise motor rotation via the Jump on
Accumulator Bit instruction (JBn), withOOH loaded to
restart the sequence. The same bit is tested when decrementing the sequence count for counterclockwise motor
rotation, R-to-L motion, because the count rolls over
from OOH to OFFH, with 03H loaded to restart the
sequence.
At this point the UPI-42 Timer/ Counter is loaded, the
step signal is output, and the timer started. The next
step data to be output h~s been determined and the
At-Speed flag is tested for entry to one of two subroutines; Stepper Motor Acceleration Time Storage or
Character Processing.
The first entry to the Acceleration Time Storage subroutine initializes the subroutine and returns. All other
entries to one of the two subroutines perform the necessary operations, detailed below (Blocks 6 and 7), and
returns. The program loops until the PT times out or the
PTS level change is detected. PTS is tied to TO of the
UPI-42. The level present on TO is directly tested via
conditional jump instrunctions. The software loops on
polling the timer Time Out Program Status flag and the
TO input level.
As described in the Backgroun'd section above (shown
in Figure 13), ifPT times out before PTS is detected, the
software waits for PTS before outputing the next step
signal. If PT times out before PTS, a second timer
count value is loaded 'into the UPI-42 timer. The timer
value is called "Failsafe."This is the maximum time the
stepper motor can be selected, with no rotor motion,
and not damage the motor. If PTS is not detected,
either the carriage stepper motor is not rotatIng or the
optical sensor is defective. In either case, program excution halts, the motor is deselected; and the external
status light is turned on to indicate a malfunction. A
system reset is required to recover from this condition.
The Failsafe time, is approximately 20 milliseConds,
including PT.
The Failsafe time. loop also serves as a means of tracking the elapsed fime between PT time out and PTS.
6-735
Entry to the Failsafe time loop sets the Failsafe/ Constant Time Window status flag. This flag is tested by the
Acceleration Time Storage subroutine for branching to
the proper time storage calculation to be perform (see
Figure 13 and Block 6 below for further description).
During the Failsafe timer loop, if PT8. is detected and
verified as true, the Failsafe timer value .is read and
stored in the Time Storage register. This value is used
during the next Acceleration Time Storage subroutine
call to calculate the Stored Time Constant (see Block 6
below). If PTS is invalid, the flow returns to the timer
loop just exited, again waiting for PTS or Failsafe time
out.
During the PT time loop, if PTS i~ detected and verified, the Sync flag is tested for entry to the print head
solenoid firing subroutine. This flag is set by the first
entry to the Character Processing subroutine. The flag
synchronizes the solenoid firing with charact~r ~roces.s
ing. Only if characters are processed for prmtmg Will
the' solenoids be enabled, via the Snyc flag, for firing.
This prevents the solenoids from being fired without
valid character dot data present.
As described in the Background section "Relationship
Between PTS and PT," PTS is the point of peek angular
velocity within a step of the motor. After PTS. is
detected the motor speed ramps down, compensatmg
for the overshoot ofthe rotor motion. PTS is the optimUQl time for print head solenoid firing, as shown in
Figure 13. This is the most stable point of motor rotation and, thus, the print 'head assembly motion. If PTS
is detected during PT, printing is enabled, the Sync flag
is set, and the solenoid trigger is fired.
The firing of the solenoid trigger, following PT~, is ,v~ry
time critical. The time between PTS and solenOid fmng
must be consistant for accurate dot column alignment
throughout the printed line. The software is designed to
meet this requirement by placing all character proces,sing and motor control overhead before t~e solen?ld
firing subroutine is called, The actual ,mst:uctlO,n
sequence which fires the print head solenOid trigger IS
plus or minus one instruction for any call to the
subroutine.
Once the timer loop is complete, the software tests for
Exit conditiops. If the Exit conditions fail, the software
loops to \lutput the next step signal, starts the PT timer,
and continues to accelerate the carriage stepper motor,
or process, and print characters. If the Exit test is t.rue,
the carriage stepper motor is decelerated to a fixed
position; and the program returns to the main program
flow (see Flowchart I).
The exit conditions are different for the two directions
of print head assembly motion. For L-to-R printing, if a
Carriage Return (CR) character code is read from CB,
the carriage stepper motor drive terminates and the
motor is decelerated to a fixed position. There are two
conditions forterminating carriage stepper motor drive
upon detectipga CR during L-to-R motion; Ifles~ than
half a character line (40 characters) has been pnnted,
r
230795-001
,
Ap..161
the,print head assembly returns t,o the HOME position
to start the next printed line. Otherwise, the print head
assembly continues to the, right-most ,position for a full
80 character line, and then begins printing the next line
from R-to-L. R-to-L printing always returns the print
head assembly to the HOME position before the next
line is printC
I,
.1
-+
r;;<
TIME STORAGE DONE
l'
I
<
">
INITIALIZE CHARACTER PROCESSING
REGISTERS
,
J
~'
FAILSAFE TIME WINDOW ENTERED
,I
P
'CALCULATE! TIME TO STORE
(PT + TX) RESET FAILSAFE FLAG
I
I.
1
DeCREMENT OATA MEMORV ADORESS
DECREMENT STEPS TO $OlRE COUNT
~
RETURN
STOREPT
I
r
I
I
The Character Processing subroutine is entered only if
the Home Reset (HR) optical sensor signal is high and
printing is enabled. Otherwise, the software simply
returns to the Carriage Stepper Motor Drive subroutine. There are two cases when printing is n,ot enabled;
during,the HOME subroutine operation, and when the
print head assembly returns to the HOME position
after printing less than half an 80 character line. If
printing is enabled, the Sync status flag is set.
START')
-r
ry<
I',"
",
I
I
Flow Chart No.7. carriage Stepper Motor
Acceleration Time Storage
J
All character processing operations use the second UP.J42 Data Memory Register'Bank, RBI. Register Bank 1
is independent of Data Memory Register Bank 0, used
for stepper motor control. The use of two independent, '
register banks greatly silI)plfies the software flow, and
helps' to ensure the accuracy of event sequences that
must be h.andled in parallel. Each register bank must be
initialized only once for any ,entry to either the Carril!-ge
StepPer Motor Drive or Character Processing subroutilles. A single UPI42 Assembly Laqguage instruction
selects the I!-ppropriate register bank. Initializing the
character processing registers includes loading the maximum character count (SO), dot matri'x'size count (6),
and CS 'start address. The CB start address is print
direction dependant, as described in Block 4, above.
a
Character ,proce'ssing reads character from the CB,
tests for control codes, translates the character to dots,
and conditionally exits, returning to the Carriage
Stepper ~oto~'Drive subrql,ii,ine. Fio:W ~hart 8 det~iIs,
the character processing subroutine.
230795.()()1
inter
AP-161
act~r dot column (blank column) had
been entered. The
next character, in this case the first character in the line,
is translated and printing can begin. This method of
intiializing the Character Processing subroutine utilizes
the same software for both start-upanq normal character flow. Once a character code has been translated to a
dot matrix pattern starting address in the look-up table,
aU subsequent en,tries to the Character Processing subroutine simply advance the dot column data address
and outputs the data.
The decision to translate the character to dots during
the blank column time was an arbitary one. As was the
choice of the blank column following rather than
preceding the actual character dot matrix printing.
4. Translate Character-to-Dots
Character-to-dot pattern translation involves converting the ASCII code into a look-up table address, where
the first of the five bytes of charcter dot column data is
stored. The address is then incremented for the next
column of dot pattern data until the full character has
been printed.
The doLpattern look-up table occupies two pages, or
approximately 512 bytes of Program Memory. A printable ASCII character is tested for its dot pattern location page and the offset address, from zero, on that
page. Both the page test and page offset calculations use
two's complement arithmetic, with a jump on carry or
not carry causing the appropriate branching. Once the
pattern page and address are determined the indirect
addressing and data move instructions are used to read
and output the data to the print head solenoids. Flowchart 9 details the Character-to-Dots Translation subroutine.
In the case ~f R-to-L printing, although the translation
operation is the same, the character is printed in
reverse. This requires that the character dot pattern
address be incremented by five, before printing begins,
so that the first dot column data output is the last dot
column data of the character. The dot pattern look-up
table address is then decremented rather that incremented, as in L-to-R printing, for the balance of the
character. Translation still takes place during the last
character dot column, the blank column, and the blank
column follows the character matrix.
RETURN
Flow Chart No.8. Process Characters for Printing
Each character requires si'X steps of the carriage stepper
motor to print; five for the 5 character dot columns and
I Jor ,the blank dot column between each character.
Reading a character from the CB and character-to-dot
pattern translation takes place during the last character
dot column, or blank column, time.
The first character line entry to the Character Processing subroutine appears to the software as if a last char-
Only one control code, a Carriage Return (CR), is
encountered by the, character translation subroutine.
Linefeed (LF) characters are stripped off by the CB Fill
subroutine. If a CR code is detected the software :tests
for a mid~line exit condition; less than half the line
printed exits the stepper motor drive subroutine and
HOMEs the print head assembly before printing the
next line. If the test fails, more than half the line has
been printed, the CR is replaced by a 20H (Space character) and printing continues for the balance of the line;
the space characters padding the CB are printed.
6-737
230795-001
inter
AP~161,
INITIALIZE DECELERATION REGISTERS
OUTPUT NEXT STEP SIGNAL
LOAO .. START TIMER
DECREMENT STORED TIME CONSTANT
DATA MEMORV ADDRESS
SETUP NEXT STEP
<
REPLACE CR WITH 20H
STEP
SE~UENCE
DONE
RESTART SEQUENCE
I~
I
LOAO NEXT STEP
<
L-;;<
1,
PT TIME OUT
~
~
DECELERATION DONE
~
,
>
STORE LAST STEP' ADDRESS
1
RETURN
Flow Chart No. 10. Decelerate'Carrlage
Stepper Motor
Flow Chart No.9. Translate Character-to-Dots
As mentioned above, the character dots are printed and
the print head trigger is fired when the PTS signal is
detected and verified and the carriage stepper motor is
At Speed.
When the character to print test fails the CB Buffer size
count equals zero, the Carriage Stepper Motor Drive
subroutine exit flags are set, and the flow passes to the
Deceleration and Delay subroutines and programs
returns to the main program flow.
9. Decelerate Carriage Stepper Motor
The transition from the Carriage Stepper Motor Drive
subroutine to the Deceleration subroutine outputs the
next step signal in sequence, and then initializes the
Decereration subroutine registers; Stored Time Constants Data Memory buffer end address and size. The
Sfored Time Constant Buffer is a LIFO for deceleration
of the carriage stepper motor. The buffer,size is used as
the step count. When the step count decrements to zero,
the step signal output is terminated, and the last step
sequence number is stored in the carriage stepper motor
Next Step pseudo register. The last step sequence
number is recalled, during initialization of the next
carriage stepper motor drive, as the basis of the next
step data signal to be output. See Flow Chart 10.
When the carriage stepper motor is decelerated, Failsafe protection and PTS monitoring are not necessary.
The Deceleration subroutine acts as its own failsafe
mechanism. Should the stepper motor hang-up, the
subroutine would exit and deselect the motor in sufficient time to protect the motor from burnout. Since
neither, Failsafe nor print head solenoid firing take
place during deceleration, PTS is not needed. PT is
replaced by the Stored Time Constant values in Data
Memory. The Deceleration subroutine determines the,
next step signal to output, loads the Timer with the
Stored Time Constant, starts the UPI-42 Timer, and
loops until time out. The subroutine loops to outputthe
next step until all of the Stored Time Constants have
been used. The program returns to the, Carriage
Stepper Motor Drive subroutine and the motor is deselected foliowing the Delay subroutine execution. The
Delay subroutine is called to stablize the stepper,motor
before it is deselected. During the DELAY subroutine,
the IBF interrupt is enabled and characters are processed.A paper feed is forced following "the carriage
stepper motor being desele~ted.
10. Paper Feed Stepper Motor Drive,
The paper feed stepper motor subroutine Ojltputs a
predefined number of step sjgnitls to advance the paper,
in one li\leihcrements, for the required number oflines.
The number of step signals per line increment is a function of the defined number of lines per inch, given the
distance the paper moves in one step., Figure 16 lists
three step (or pulse) count and line spacing configJlra-
6-738
230795-001
inter
AP·161
tions, as well as the distance the paper moves in one
step. Standard 6 lines per inch spacing has been implemented in this Application Note (Appendix B details
how variable line spacing could be implemented).
Flowchart 11 illustrates the Paper Feed subroutine.
If the Formfeed flag has been set in tjle Character Buffer
Fill subroutine, the software calculates the number of
lines needed for a top of. next page paper feed> The
resulting line count is loaded in the Line Count Register. The Paper Feed subroutine loops on the line count
until done and then returns to the main program body.
Once the Paper Feed subroutine is complete, the software loops to test the End of File (EOF) Flag (see
Flow Chart I). If EOF is set, the print head assembly is
moved to the HOME position, the program again
enters the External Status Switch Test subroutine, and
begins polling the external status switches. If EOF is not
set, the program directly calls the External Status
Switch Check subroutine; and the prClgram repeats for
the next line.
CONCLUSION
Although the full speed, 12 MHz, of the UPI-42 was
used, the actual speed required is approximately 8-9
MHz. 1400 bytes of the available 2K bytes of Program
Memory were used; 500 bytes for the 95 character
ASCII code dot pattern look-up table, 900 bytes for
operational software. This means that the UPI-42 has
excess processing power and memory space for implementing the additional functions such as those listed
below and discussed in Appendix B. ,
Special Characters or Symbols
Lower Case Descenders
Ipline Control Codes
Oifferent Character Formats
Variable Line Spacing
Flow Chart No. 11. Paper Feed Stepper Motor
Drive
The number of lines the paper is to be moved is called
the "Line Count." The Line Count defaults to one
unless the Formfeed flag is set, or the total number of
lines previously moved equals a full page. The default
total lines per page for this application is 66. When the
total number of lines moved equals 66, the paper is
moved to the top of the next page.' The Top-of-Page is
set at power-on or reset.
'
The software developed for this Application Note was
not fully optimized and could be further packed by
combining functions. This would require creating
another status register, which could also serve to
implement some of the features listed above. Since the
full 16 byte stack is not used for subroutine nesting,
there are 6-8 bytes of Program Stack Data Memory that
could be used for this purpose. In several places, extra
code was added for clarity ofthe Application Note. For
example, each status byte flag is set with a separate
instruction, using a equate label, rather than setting
several flags simultaneously at the same point in the
code.
This Ap'plication Note has demonstrated that the UPI42 is easily capable of independently controlling a complex peripheral device requiring real time event monitoring, ,The moderate size of the program required to
implement this application attests to the effectiveness of
the- UPI-42for peripheral control. _
6-739
230795-001
inter
AP-161
APPENDIXA.
SOFTWARE LISTING
1 S~OD42 TITLE('UPI 42 APP NOTE'I;
~
$HACROFILE NOSYHBOLS NOQEN DEBUQ
3
=
4 $INCLUDE(:Fl:ANECD.OV1)
5
6
7
= 8
PG
** ** * ****** ******** * *** * ** * ********* **
Complex Peripheral Control With the UPI-42
9
= 10
Intel Corporation
=
11
= 12
3065 Bowers Avenue
Santa Clara, Ca. 95051
= 15
Written By
13
14
16
17
18
19
=
20
•
22
23
24
25
..
=
* * * * ** **** * *
Christopher Scott
~
**** **** ***
~
* ********* ** *
Notes and Comments
~1
Three A••• mbl~ Language fil.s comprise the full Application·
Note sdu?ce co~ ••
1.
ANECD. OVI
App Note
2.
4~ANC.SRC
UPI-4~
3.
CHRTBL.OVI
E~uate ••
Constants, Declarations. Overlav
~6
27
28
29 •
30
31
32
App Not. Code Source
33
= 34;
* * * *
37
38
* * * * * * * * ** * * ** * * * * * * * * * * * * * * ** * * * * * * * *
= 36
= 39
40
= 41
4~
=
=
=
=
=
PG
35
43
44 •
45
46
*4*
* * * * * * * * * * * * * * * * * * * * * * * * * * *_* * * * *
Equates, Constants and System Definitions
Data &Program Memory Allocations
Program Memory
Page No.
He. Addr
Page 7
179~-~047
Page 6
1536-1791
Page 5
1280-1535
Page 4
Page 3
10~4-1279
768-10~3
47;
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Page 2
'Page
Page 0
512-767
256-511
0-255
Description
Char to Dot pattern lookup table
Page~:
ABCII 50H-7FH SN-~)
Char to Dot pattern iookup tabl.
Page 1:
ASCII ~OH-4FH (sp-H)
Mise called routines:
InitAl/AllOH
Clear Data H.mor~
CR Hom"
Char Print Test load Ascii char codes
Initialize CR Stpr Htr
nelaV' short/long/verv long
Stpr Htr d •• elect
Pap,erF •• d Stpr Htr Ini t end Drive
Stpr Htr Phase LookUp Table - Inde.ed
Charact.r Translation and proc •• sing
PrintH.ad firing
Stpr Htr Accel. Time calc. and memorization
Stpr Htr Deceleratian
SHDriv (FAccal/RAccen - For ..ard Ie Reverse
Stpr Htr acceleration Ie drive
Initiaization ~mp-on-R.s.t
Program Body - .11 calls
Character Input test and Char Buffer fill loop
Interrupt •• rvice rout in ••
6-740
230795-001
inter
AP-161
=
71
pg
72 ,
= 73
---------------------------------------------------------------------------
Data "elDrg
74
75 , --------------------------------------------------------------------------Hex
D..... iption
76
77,
TOP
78 ,
79,
48-127
2F-7FH
80 Ch ..... t ... Lin. Buff ...
80 ,
37-47
25-2EH
Stp .. Mt .. 011••• 1/0••• 1 ti~ •• ~.mo .. il.tion
81 ,
36
24H
Unu •• d
,
35
82
23H
Ch ... p .. int t •• t ASCII .od • • t ... t tmp .to...
83
34
LF
SI'I
I
••
,
PhI
Ind
.....
,
Add
.. p.u.do ... g
22H
84 ,
21H
CR 8M Fo ..w... d/R.v ..... la.t PhI p.u.do ... g
33
811 ,
32
20H
P.u.do R•• : La.t Pha •• of .tp .. ~t.. not
b.in. d.. iv.n
86"
87
24-31
18-1FH
R•• S.t ... Bank 1: Cha .. a.t.,. Handlin.
88
8-17H
8-23
8 L.val Stack
89
0-7
R•• S.t ... Bank 0: Stp .. Mt .. FIR A.c.I/D.. iv.
0-07H
90,
91 ,
BOTTOM
92
---------------------------------------------
93 ,
94
, --------------------------------------------------------------------------911
96 CH8FSZ ECiU
lIOH
,.ha.. buff .... il. 0-79 • 80
97 HUCpl Eq,u
OD9H
,Cpl(1/2 CbBfSI> .> cpl of 27H - OD9H
oollO
001)9
98
007F
0080
002F
0051
oo2F
0008
OOOA
002F
0025
007F
0050
0020
0021
0022
0023
•
•
•
•
•
•
•
-
99
100
101
102
103
104
105
106
107
108
FCBfSt
FClflS
RCBUS
ChBfIS
Eq,u
Eq,u
Eq,u
Eq,u
7fH
80H
2FH
81
,.ta.. t of .ha.. buff ...
,init ci .t.. t-allow. It .. a D•• b~ 1
, init CB' .t.. t-.11o". It .. a In. by 1
,Io.d .ha ... nt .... w/.ha .. bu', .. Ini t She
ENDBUF
ASBfSI
DBBfSI
SI'IBFST
SI1BEnd
DMSi ..
ECiU
ECiU
Eq,u
EIiU
Eq,u
Eq,u
Eq,u
2FH
OSH
OAH
2FH
25H
7FH
93
,END OF CHAR BUFFER,
,A••• l ... at • • tp .. mt .. bu' .ount
,D ••• I ... at• • tp . . . t .. buf .ount
,STPR MTR BUFFER START
,Stp" Mt .. Data M•• o.. y Add ......nd
,Data M••o.. y Top
,Data M.mo .. y Sil. (1 ••• t.o .o.. kin ....... >
LutPh
CPSAd ..
LPSAd ..
PTA •• S
Eq,u'
ECIU
Eq,u
Eq,u
20H
21H
22M
23H
,Ia.t phI p.u.do .... add ..
,CR phI p.u.do ... .
,LF phI p.u.do ... .
,Ch ... p .. int T•• t .od',.ta.. t tmp .to...
•
109 DMTop
•
•
•
•
•
•
110
111
112
113
114
115
116
=117
pg
•
118 »
* * * * * • * * * * * • * * * * * • * * * * * * * * * * * •• * * * * * * *
= 119
• 120 ,
• 121
122
- 123
• 124
- 125 ,
• 126
= 127
0000
0001
0002
0003
0004
0005
0006
0007
Register allocatiDn
* **** ** * ** * ** • *** *** ** ** ** ** * ***** ** • *
All Indi ... ct Data M.mo .. y Add ..... in. vi. eRn In.t mu.t u.e
only ... gi.t .... 0 • 1 of .ith ....... ist ... bank. Anu oth .... ill
b. ".J •• t.d b'l the A. . .mbl... .
La.t cha .. a.t ... in labl. indicat •• R.gi.t ... Bank ... f ....nc.d
Register Bank 0
• 128 J - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RO
,'RBO T.mpo .. a .. y R.gist ...
- 129 T~pROO Eq,u
Rl
,Sto... Tim. R.gSste .. RBO
• 130 TSt .. RO ECiU
131 QStR20 ECIU
R2
,Q.n ... al Status R.gist ... RBO
R3
,Stp" Mt .. Ph ••• R•• i.t ... RBO
• 132 PhlR30 EIiU
R4
,Count R••. Ph ••• count-St, .. Mt .. loop.
• 133 CntR40 Eq,u
, A••• I/Dec.1 Count
• 134
R5
,Tim• • on.tant .... RBO
• 135 TConRP Eq,u
; Line count
• 136,LnCtRO Eq,u
R6
• 137
,'avail.b 1.
R7
- 138 OpnR70 ECiU
• 139
R•• ist ... Bank 0 Data M.mo .. y Add .....
• 140 ,
- 141 , ----------------------------------------------------------.----------------
6-741
230795-001
AP-161.
0000
0001
0002
0003
0004
0005
0006
0007
=
=
=
=
142 TmpAOO
TStrAO
144 QStRAd
145 PhzA20
146 CntRAO
147
148 TConAO
149 LnCtAO
150
151 OpnA70
152
153
=
155
R
= 143
=
=
=
=
=
=154
PG .
;TempOTBTV Register OM addres$
;Time Store Register DM addre.s
I RBO Cllar Statu,s Reg DM address
IStpr Mtr Phase Registor DM addre.s
; Count Reg', Phase count-6tpT' Mtl" loops
i
Accel/Decel Count OM address
EIlU
EGU
EIlU
EGU
Equ
OOH
01H
Equ
Equ
05H
06H
; Time. constant ,reg OM add,...ss
EGU
07H
; available
Oi?H
03H
04H
;Lin_ Count Register DM .ddress
,
'
---------------------------------------------------------------------RBO Status Byte Bit Definition
- 156
= 157 I
= 1:58
.. 159
- 160
.. 161
= 162
= 163
.. 164
.. 165
- 166
.. 167
= 168
.. 169
.. 170
.. 171
.. 172
.. 173
.. 174
= 175
.. 176 LRPrnt
.. 177 RLPT'nt
= 178 SnkSet
... 179 ClrSnk
180 AtSpdF
.. 181 NAtSpd
= 182 ADIntD
183 ADIntN
• 184
= 185 FsCTm
= 186 ClrFsC
.. 187 FT'mFd
.. 188 LineFd
.. 189 DoNatI'
190 OkPrnt
R
191 Readv
.. 192 NatRdv
.. 193
.. 194
Bit
Definition
7
6
5
4
Stpr Mtr Direction: L-ta-R - 1. R-,ta-L = 0
1 = Sink / 0 • Not Sinked, Print H•• d Init and Fire
Stpr Mtr at speed and CR not left of Home
Ace.I/O.cel Init, 1 = Done I 0 - Not Done
3
2
1
1 • FailSafe I 0 - Constant, Time Window
1 - Form Feed ( 0 - Line Feed
1 = Do Nat Print / 0 - Print
FAccel/DAccel drive Readv = l/NotRdv = 0 (exit
drive & deeel ,.tpr mtr)
o
B,it Mask.:
Stepper, Motor
RBO
c~ntral
bit masks function an QStRl0
EIlU
Ellu
Equ
Equ
Equ
Equ
Equ
EIlU
80H
7FH
40H
OBFH
20H
ODFH
10H
OEFH
I Left .to Right Printing the Ch ... St'.tu. Regiah .. RBl
'Jump to CR BI'I Hom. if EDF bit •• t
,loop to Cha .. Buffe.. Input t.~t
451
453
454
455
0029 15
002A 35
002B 83
" C.ll Fo ....... d Stp .. !'It..· D..
,C.ll lin.fJed stp .. !'It .. D1'iv.
450
452
0025 8A20
0027 15
0028 83
i".
8!'1Driv'
I-FDU'"
RBl .
A. 'Ch8tRl
Home
CBInpt
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
.505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
Switc~·ChfckIChar.
guff.r Fill
* * * * * * * * * * * * * * , *,P...
* *p *'0..* no
* ...
* el
* ••
* * * * * * * * * * * *
ch., ... ct... handling/input
ESCB'F:
SEl
!'Iov
ANl
!'Iov
SEl
RBl
A.ChStRl
A••N.. mP .. n
ChStRl. A
RBO
'get the .ch .... ct.r .t.t ... g bvt.
, •• t no .. m.l ch .... ct ... input
,sto ... the .t.t bvte
,
Test Exh .. n.l St.tus Port
!'IovD
A. P7
'get the .t.t switch po .. t bit.
Fo .. mFd
..IBO
•• rvice F01'm' •• d
..181
linFd
•• rvice Lin.f.ed
vB2
Ch .. Tst
.... vic. Ch .... ct ... TEST
..IB3
OnLine
, .... vic. Ch.T" Buff ... Che.ck/Fill
, loop
..Imp
ESCBfF
------------------------------------------~~-~-------------------------Fo .. mFd: !'Iov
A.GStR20
'get the .t.tu. b~t.
ORl
A.4IF.. mFd
••• t the 'D1'm' •• d .tat .l.g
Mov
GStR20.A
, .to...· t .. h• • tatu. b~te
Call
lfD.. iv
'do a fD1'mhed
..Imp
ESCBfF
linFd:
C.ll
,do. line d1'lv.
LfD1'1v
..Imp
ESCBfF
, -----------------------------------------------------------------------ChrTst·
BEL
RBl
Mov
A.ChStRl
'get the ch ....eter st.t ... g b,te
ORl
A••T.tPrn
••• t ch .... ct ... ,t.st flag
!'Iov
ChStRl. A
,.to"•.til • • t.t ·b~t.
TmpRl0 •• PTA.cS 'load the p.u.do A.cil. code ·tmp ".9 .dd ..
Mov
Mov
A.ITmpR·10
,g.t ~h. inc'd •• cil cod.
A,••LA.End
ADD
,t •• t fo .. code .nd
..INZ
AscCld
,i' not cod • • nd Jmp to lo.d
, i f .ri~, .... t.rt .scu .t b.g.inl.ng
Mov
ITmpR 10••Asc 11 ,.to~. the .scii,cod • • t ... t
AscCld: !'Iov
A.ITmpRl0
,ge~ the •• cli cod • • g.in
Mov
OpnR71. A
.pl.c. in the emptv ... gi.t ...
Inc
ITmpRl0
,Inc st ... t ASCII ch ... in d.t. m.mo .. ~
C.ll
P.. nT.t
,c.ll the DI'I lo.d p .. oc.du...
8El
RBO
' ..... l.ct ".9 bank 0
Ret
, ------------------------------------------------------------------------
6.-746
230795-001
inter
005£ D5
005F 05
0060 FA
0061 3267
0063 146D
00650460
0067 C5
0068 83
AP·161
520
521
522
523
524
525
526
527
528
529
OnLin.: BEL
EN
ca'Ckl: Kov
Jal
II.Ck: Call
.lap
caCkEx: BEL
Rlt
RII
,a.l.ct cha~ bu",~ ~.giat.~a
,"nabl. intl~~upta
,g.t the Cha~ 8tat a~tl
, i ' Ch~ au' haa full lin • • xit
,~.a. a cha~ into Cha~ lu".~
'loop to Cha~ lu' Ful t.at
,1
A.Ch8tRl
CICkEx
CaFi11
CaFCkl
RaO
PG
530 , ------------------------------------------------------------------------
531
006"
006A
0061
006D
D5
FA
32EC
527C
006F 05
0070 D6EC
0072 FA
0073 127C
0075
0077
0078
007A
4301
AA
1"7F
ID50
007C
007E
007F
0081
0083
0085
0086
0087
EDl6
FA
4302
53FI
53FE
AA
FA
'2El
008" "AEF
0081'22
ooec 537F
008E A8
008F 8AI0
00"1
00"3
00'J5
00'J7
00"8
03EO
F6"7
04"C
"7
F8
OO'J" Al
OO"A 04E3
OO"C F8
0~D03F3
OO"F
OOAI
00A2
00A4
00A6
OOA7
00A8
OOAA
OOAB
C6C3
F8
031B
"6AA
F8
Al
041"
F8
03F4
OOAD "hEl
OOAF
0010
OOBI
0013
0014
0015
00B6
C5
FA
4304
AA
D5
FA
4304
0018 AA
OOB" FA
Character Input
532 , -----------------------------------------------------------------------533,
Input luf'"~ Full al~vicI ~outinl:
t •• t 'o~ Cha~ bu".~ 'ull-Ixit
534 ,
.lal load cha~ into cha~ bu""~
535 IaF8~v:' BEL
Rli
536
Kov
A.Ch8tRl
'glt the RIO atat b~t.
537
JB1
CaFuli
.i. Do Not P~int lit S.t - EXIT
538 CaF111: .112
CIPad
.t.at fo~ CI padding 'lag
,
i. not pad Inabll cha~ input
53"
540
t.ll thl hoat to •• nd cha~'s
541
EN
I
542
JNIBF
CIF1Ex
543 ,, -----------------------------------------------------------------------544
Ackno~l.dg. Cha~ input and •• t Hold/au.~ Activ.
545
Hov
A.ChS~Rl
,g.t thl Rll Cha~ Stat I~tl
546
.110.
SkpInt
.t •• t 'o~ CB ha. b •• n Inltlalizld
547 •, -----------------------------------------------------------------------548
Init o. all Cha~ handling ~Igiatl~.
ORL
A•• IntCaR
•• et CI R.g .kip Initlallzation stat bit
54"
Kov
ChStRI.A
•• av. the altl~.d atat b~tl
'50
551
Hov
CAd~Rl ••FCB'St
• load cha~ ~.g ~/cha~ bu'~ at~t
552
Kov
CCntRl ••Chl.Sz • load cha~ cnt ~eg ~/cha~ bu'~ size
553 caPad:
554 Skplnt: DJNZ
CCntRI.LdCha~
.DECREKENT IUFFER SIZE
Hov
A.ChStRl
'get thl status b~te
556
ORL
A••CaFLn
•• et Cha~ au"e~ Full Linl atat bit
557
ANL
A••Cl~C~
.clea~ the CR/ILF) stat bit
558
ANL
A••CnCIR
,~.a.t CB Init bit:
init CB ~eg on ent~~
Kov
ChStRI. A
,ato~1 thl atatu. b~ta
560 LdCha~: Kov
A.ChStRI
'glt thl atatua b~tl
561
Ja2
CBPadl
.CI not full but CR/LF p~eviou.l~
562
, ~Iclivld ao pad CI
563
ANL
P2 •• Ack
,output DIB Ack lo~
564
.In
A.Dla
.~aad thl Cha~
565
ANL
A••AscStp
'.t~ip
KSB
566
Kov
TmpRIO.A
.tlmp ..va cha~
567
ORL
P2 ••RISAck
.output DBI ACK High
568
--------------------------------------------------------------~--------56"
tnt .o~ A8CII p~intable cha~act.~
570
ADD
A••ASCCpl
,t.at 'o~ Ca~~iag. R.tu~n
571
JC
A.ciiC
'Jmp to .I~vice
572
.Imp
Ch~Chk
573 AscHC: Cl~
C
,cl.a~ c.~~v ' I ••
574
Hov
A.TmpRI0
'glt thl c~~ back
575
Hov
lICAd~RI.A
'load data m.mo~v ./Ch.~
576
.Imp
IBFS~E
577
578
t •• t 'o~ CR/LF:
i f CR/LF St~ip off LF and .xit setting
Cha~ lu".~ Init Stat bit
57" •
580 Ch~Chk: Hov
A. TmpRI0
.'glt thl cha~ back
581
ADD
A••CRCpl
,t •• t .o~ Ca~~i.g. Retu~n
582
JZ
CRCh~
• i. CR go a.~vice it
583
Hov
A/TmpRIO
1.lt thl cha~ back
584
ADD
A••EOFCpl
.t.at 'o~ End O' File
585
JNZ
Ch~Ckl
, i ' not EOF Jap to CI Pad
Hov
A.TmpRIO
.i. EOF. plac. it in CB
586
587
Hov
.CAd~Rl.A
'load data m.mo~v ~/CR Cha~
5ee
.Imp
ExtS.t
.E~it
A.TmpRIO
'glt the atatus byte
58" Ch~Ckl: Hov
ADD
A••FFCpl
.t •• t ,'o~ Fo~mF •• d
JNZ
CIPadl'
,if not FF Pad the CI
BEL
RIO5"2
Kov
A.OStR20
'get
the .tatu. byte
5"3
ORL
A••F~mFd
, •• t the 'o~m' •• d 'lag
5"4
Kov
OStR20.A
~
,.to~e the .t.~us b~t.
5"5
SEL
RB1
5"6
Kov
A.ChStRl
'get thl .tatu. byte
5"7
ORL
A••CRLF
,s.t CRLF stat bit:
pad balenc.
CB
, ~lth Space. unt.l 'ill
600
Hov
ChStRl;1\
'.tD~' the atatu. b~t.
601 ExtSlt: Hov
A.ChStRI
'glt the statua byte
"5
""
0"
'''0
'''I
0'
'''II
5""
6-747
230795-001
inter
OODA
OOBC
OOBE
OOCO
OOCI
4302
53FD
53FE
AA
04EC
00C3
00C4
OOC5
OoC6
00C7
OOCB
FB
Al
C5
IE
FE
03C4
OOCA
OOCC
OOCD
OOCF
DODO
OODI
00D2
00D4
00D6
OODB
E6DO
FA
AP-161
DRL
ANL
ANL
Moy.
Jmp
A• .cBFLn
A••ClrCr
A••CIICBR
ChStR1. A
CBF1Ex
, •• t Ch.r Buff.+ Full Line st.t bit
,cle.r the CR/(LF) stat bit
,re •• t CB In1t bit: init CB reg on entry
...to... the .tatu. b,te
,Exit
Moy
Moy
SEL
INC
Moy
Add
A.TmpRl0
IICAdrRl. A
RBO
LnCtRO
A.LnCtRO
A••PgLCpl
,g.t the ch.r hack
'load d.t ......0 ... ' fIl/CR Char
JNC
Moy
ORL
Moy
SEL
En
ANL.
JNIBF
ANL
In
NoFmFd
A.GStR20
A••FrmFd
GStR20.A
RBI
I
00D9 FA
OODA 4304
Moy
ORL
A.ChStRl
A••CRLF
OODe AA
OODD BA10
OODF 04E3
Moy
ORL
Jmp
ChStRI.A
P2 ••R.SAck
IBfSrE
------------~-------------------------~----------------------~---------Store eR ,ch.", 'read in LF ch.r (.s.ume its .1 ...·'. th .... ) and ignor it
4304
AA
D5
05
9ADF
DbD4
9AEF
22
line the lin. count
,g.t the line count
,t.st for p.ge f.ed In cnt·
, if LnCt -> PgLnCt set for.fe.d fl.g
'if not ~t .nd af page .kip
-, get the status bUte
'.et the form feed st.tus flag
's.v~ the st.tus b,te
P2.~otB·V
LFTe.t
P2.41Ack
A.DBB
0DE1 8120
.00E3
00E4
00E5
00E7
C9
FA
32EC
52EC
00E905
OOEA 9ADF
OOEC B3
PG
653 ,
654
655
10100
* * * * * * * * * * * * * * • * ••.• * * * * * * * * * * * * * * * * * *
L-to-R/R-to-L Carriage Stepper Motor Drive
and Line Printing
ORG
100H
R•• to".
Moy
Mov
Moy
the ph ••• r.gister index .ddr •••••
T.. pIt00.4ICPSAdr 'get Ph. Stor.g. Addr psuedo reg
A.IITmpROO
, g . t stored CR la.t ph ••• inde. addr
PhzR3O. A
'place last LF pha •• index .ddr in Ph.
0100 3622
0102
0103
010'
0107
0109
010B
0100
010E
010F
0110
0112
FA
53BF
53DF
43BO
4301
53EF
AA
D'
FA
43BO
AA
0113 C5
0114 BB21
0116 FO
0117 AB
.
6-748
'.
230795~01
inter
0118
0119
011A
011C
011E
0120
lB
FB
521E
2440
BBOO
2440
0122
0123
0125
0127
0129
012B
012D
012E
012F
0130
0132
0133
FA
53BF
53DF
537F
4301
53EF
AA
D5
FA
537F
AA
C5
AP-161
0134 B821
0136 FO
0137 AB
0138
0139
013A
013C
013E
CI
FI
523E
2440
BI03
0140
0142
0143
0144
0146
1822
FO
E3
1820
AO
0147 BDBA
0149 2308
014B 3D
014C
014D
014E
014F
FD
62
FI
E3
0150 B820
015240
0153 3C
0154 55
0155 740C
0157 FA
0158 F264
015A
015a
015C
015E
0160
0162
CI
FB
5260
2462
1103
246C
6-749
230795-001
AP-161
707
0164
0165
0166
0168
016A
IB
FB
526A
246C
BBOO
016e
016E
0170
-0172
0173
0175
1682
5672
246C
00
5677
246C
0177
0178
017A
017C
FA
D27C
247E
74CA
017E 1698
0180 247E
0182 2300
0184 62
0185 55
0186
0187
0189
018A
018C
018E
0190
0191
0193
0195
0196
0197
FA
4308
AA
5690
16AC
248A
00
5695
248A
65
42
Al
0198 FA
0199 F2A7
0193 20AC
019D FA
019E 124C
01AO
0lA2
0lA4
OIAS
4302
53BF
AA
244C
0lA7 FA
0lA8 124C
OIAA 24AC
OIAe 5437
01AE FA
OlAF F2B3
768
769
770
771
772
773
774
776
775
;
fot'w.T'd:·
Set up fol" next phase bit outp~t before entering ti~ing loops
,STEP PHASE DB ADDRESS
INC
PhzR30
,CHECK THE PHASE COUNT REG
MOV
A.PhzR30
, ,CHK FOR COUNT B IT ROLLOVER
AFZroP
.JB2
i.kip adr index t'eset
.JMP
ANxtPh
AFZroP: MOV
PhzR30.8FStCRP ,ZERO CR SM PHASE REGISTER
, _____________________________ w ____ ___________________ - - - - - - - - A,NxtPh:
Ac IF2:
~
777
stage one time-r loop - T occurs befol"e Std timeout
wait for time out
778
779 TLOOP2: .JTF
FAILSF'
,;;MP ON TIME OUT-t DOES NOT OCCUR 1ST
780
VTI
tCHKI
,IS T,HIGH-VMP TO tCHK
781
,LOOP FOR VTl OR VTF
.JMP
TLOOP2
782 tCHlu:
NOP
j delalA'
then double check T signal
78:3
,.JUMP T TEST TRUE-WAIT FOR VTF
.JTI
tTruWI
784
.JMP
TLOOP2
785 tTruWI:
786
tnt for Print R,eady bit - was Print Head Fire Setup Done?
787
insert acceloration time/store time count done/notdone flag bit
788
Mov
A.GStR20
'get the status byte - prep for prnt
789
JB6
_RdyPr2
'if Re.dy Print bit set call PHFire
790
.Jmp
SkpPHF
,
else skip Print Head Fire
791 Rd~Pr2: Call
PHFire
iprint head solenoid fjre routine
792 PNRdy2:
793 SkpPHF:
NXTPHZ
,.JUMP TO SM ERROR
794 tTruW2: VTF
tTruW2'
, LOOP
TO TLOOP3
795
.IMP :... _____________________
_ ... _________
'-J.. ___________________________ _
796
797
Step into failsafe/startup ti~.r .etup - T does not
occurs before Std Time timeout, load 'ail •• f. 8M protection
798 "
799
ti'me and wait for failsafe timeout or T.
I f T occurs
800
801 FAILSF: Mo~utPutA~~~::~i:medi.t~:~o:~t~Ii1~RV~~!a:omS
802
MOV
' T. A
SM PROTECTION TIMEOUT
803
STRT
T
,START TIMER
804 • --------------------------------------------------------------805
set the Status bit for Store time te.t
806
Mov
A.GStR20
'get the .tatu. b~te
807
;s.t Fail.afe/constant time flag
ORL
A.8FSCTm
,store the status byte
808
Mov
GStR20.A
,IS THIGH
809 TLOOP3: JTl
tCHK2
810
,IF TIME OUT QO SM ERROR
JTF
DSLECT
811
TLOOP3
,LOOP UNTIL T HIQH OR T-OUT
JMP
,WAIT
812 tCHK2:
NOP
StrTml
I Jump out and stD~& elapsed time
813
.JTl
JMP TO FAILSF LOOP
814
TLOOP3
JMP
TCnt
;stop the f.ilSa~. Timer
815 StrTml: Stop
. Mov
816
A.T
; 1'1Uld' the timer
817
MOV
@TStrRO.A
,Store the time Te.d in indexed addT'
818
, - next entrv to A/D Memorize Time
819
; routine will add time constant to it
820
821
822
823 NXTPHZ:
824
test for"orward I reverse phase start indirect index to load
825
Mov
A.GStR20
,store stat ~vte
826
.JB7
FDriv.
827
Reverse
test for Reverse Stpr Mtr Dl'ive procedul'e exit
828 ,
ALWAYS drive the CR to the left most HOME position
829
JNTO
EOLn
,test i f hom. po.itio·n Jmp stop
8:30
Mov'
A. GStR20
,get the status bVte
831
.JBO
StrtT
,test R.adv stat bit:
,
,
if bit 0 =1 then Print More
832
A.8DoNotP
,set the do not print flag
833
ORL
'834
A.8ClrSnk
,clear Pri,nt Ready bit
ANL
835
Mov
GStR20.A
,save the status byte
836 '
StrtT'
,continue CR SM d~ive
Jmp
837
, - only exit is HR
838
Forward
test for Forward Stp,. Mtr Drive pToeedura exit
839 FDrive:
840
Mov
A.GStR20
'get the statuI byte
841
.JBO
StrtT
,te.t Read~ stat bit:
842
if bit 0 = 1 then Print More
843
.Jmp
EOLn
el.e Jmp to End Of Line exit
844
; Jump to start timeT' again
845 DSLECT,'
846 EOLn:
Call
DeelSM
,~all Sptr Mtr, Deceleration
847
848
Tavel'se ph.SF stal't indirect index to load'
test foT' forward
849
,sto~e stat bvt.,
Mov
A.Q~tR20
850
.JB7
FDrvFS
; Jmp to f d-rive flag set I
6~750
230795-001
AP·181
0181 53FD
'
,I,. •••
ani,
A••OkP .. nt
851
ANL
852
853
854
upd.t. the .t.tu. b,t.
855 FD.. vF8: ANL
A••Cl .. 8n'
p.. int 'l.g --01 p .. int
if p.. inting R-to-L
,
0113 53IF
'cl .... p.. int R•• d, bit
, •• t the Bt.tu. bit fo .. Sto...
'Ch... · At p.. int Sp •• d IU'
, •• v. the .t.tu. b,t.
856
0115 53DF
0117 ItA
0118 83
857
B58
B59
860
ANL
"ov
RET
861
A••NAtSpd
QStR20.A
u.,.
t •• t
pg
*****••***********• *************
863 * * * Stepper
"otor Ateel. Ti.e Storeage
B62
864
0200
0200920C
0202
0204
0206
0207
0209
892F
ICOI
FA
4310
AA
020A 4436
865
866
867
020E FA
020F 4320
0211 AA
0212 3226
0214
0215
0216
0218
0219
D5
FA
4340
AA
F21F
ORQ
869
870,
B?l
B?2
8?3
8?4
B?5
B?6
B?7
8?B
880
881
8B2
B83
884
8S5
SS6
887
SBB
SS9
S90
S91
S92
S93
021F 19S0
0221 ID51
0223 1101
0225 C5
0226 722C
0228 FD
0229 Al
022A 4435
022C Fl
022D OXB
022F 6D
0230 Al
, Ent .. , h•• g.n St.t I,t.·in A
,i. AID 1nit don. - th.n Jmp
DADInt
1.t Ent .. , in1t1.1i ••• the AID Tim • • to .....0 .. k1n ..... i.t ....
TSt .. RO ••~lfSt ,Lo.d the Stp .. "t.. luff ... St... t Add ..
"ov
CntR40••ASI'S. ,Lo.d the luff ... Si..
I
"ov
A.QStR20
, •• t the .t.tu. b,t.
"ov
A••ADIntD
, •• t not 1.t Acc.l Ent .. , Fl.g
DRL
QStR20.A
,.to .... th • • t.tus b,t.
"ov
.Jmp
ADE.it
, •• it - 1.t .nt.. , h.s not •• n .... t.d
• clo •• d t1m... indo ..
Init1ali •• Ch ... p .. int R•• i.t .... : if , .. inting an.bl.d
.JBl
Sto.. Ct
.if Do Not p .. int st.t bit •• t
" Skip the Ch ...... gi.t ... in~t
,
,
Initi.liz • • 11 Ch ... R.g'.
T•• t fa .. L-to-R (fo ....... d) 0 .. R-to-L ( ... v ..... ) p.. inting
Rll
, •• t the .t.tus bVt.
"ov
A.ChStRl
, •• t Ch.,. Init Dona fl •• - b,p •••
DRL
A.~HIntD
the .t.tu. b,te
Mov
ChStRl.A
.J17
LdCIRl
,t •• t Ch,. St.t I,t. R.tu,.n.d
if b1t 7 - 1 th.n p .. 1nt L-to-R
"ov
CAd,.Rl ••RCI'IS .lo.d ch.,. ,..g .. /ch.,. bu'" .t.. t R-to-L
.J.,p
LdCIR2
SEL
894
S95
B96
S97
,•.v.
S99 LdCIR:
900
901
CAd,.Rl ••FCBfIS
902 LdCIR1: "ov
903
904 LdCIR2: "ov
CCntRl •• ChBnS
905
Mov
CDtCR1 ••01
906
8EL
RIO
907
90S ,
T.st fo.. t > Te 0.. t <
:~~ Sto .. Ct: . .J13
F.UST
911
912
913
914
915
916
917
9'lS
919
920
921
922
923
924
925
926
927
929
930
931
932
n.g
,
,
t
< Tc
Mov
"ov
.Jm,
,
,lo.d ch.,. ...... /eh ... buf ... t .. t L-to-R
,lo.d ch ... cnt ...... /ch ... bu'" si ••
, •• t the ch .. dot column cnt
Tc
,t ••'t , .... '.U •• ~. tim.... itch
- sto,.. Tim. Con.t.nt 1n u••
A.TConRO
,g.t tim. con.t.nt cu.....ntl' in us.
ITSt,.RO.A
,".mo.. iz./Sto,.. the tim. - i~di ... ct .dd ..
ADPR.t
> Te - .to,.. Tim. Con.t.nt
+ F.iIS••• Tim. EI.p •• d
Aeeal/Cn.t 8p.ed/Dec.I.W.vaFo.. mJ
.,u.tion 1.:
T.. d - F.ilSaf. Ti.,. - T.
-> T.. d + C,pllF.pS.f. Tim.) - T.
T. + Ten.t • T
Sto... I"• .,o,.i •• T
t
t •••
,
,
,
,g.t the sto... d tille
la's epl .dd
.Add: Tim• • to ... d +
• cu?,..n'lv in u••
Mov
ITSt .. RO,A
,"• .,o.. i •• /Sto ... the tim.
R••• t the St.tu. bit 'a.. Sto ... ·t1.,. t •• t
F.ilST: "ov
Add
Add
928 ,
0231 FA
0232 53F7
200H
8t.p the AID Sto... count
DADlnt: D.JNZ
CntR40.8torCt
,dec Tim •• to star. count
'if not 0 .to... the count
,.1 ••• t .nd-•• t don. fl ••
A.QStR20
.g.t the .t.tu. b,t.
"ov
, •• t .t .p •• d/no mo .. e to sto .. a
A••AtSpdF
ORL
gStR20.A
,.to ... the .t~tu. bIt.
"ov
89S
0218 192F
021D 4421
* * * * * * • * ** * * * * * * * • * * * * * * * * * * * * ** • * *
868 _T8: .J14
B~9
020C EC26
J
Mov
ANL
A.ITSt .. RO
A,.FTCpl
A.TConRO
A.gStRaO
A••Cl .. FSC
•• et the .t.tu. b,t.
...... t F.il •• f./const.nt ti.,. flag
•• wum •• ent,., via constant tim.
6-751
230795-001
II
inter
0234 AA
023' C9
0236 B3
..
, '~
AP·'l61
\
9313
Mov
934 ADPRott:,. Dec
93' ADExit: R.t
936
937
938
~
0231 FI
023C E3
023D 1820
023F 40
0240 3C
0241 Fl
0242 62
0243 55
0244 19
024' FA
0246 F252
0248 CI
0249 FI
024A
024C
024E
0250
524E
44!5A
IB03
44'A
02'2 18
02'3
02'4
0256
02'B
FB
'2'B
44!5A
BBOO
02'A F8
02'8 E3
02'C
02'E
02'F
0261
0263
0264
8B20
40
1663
44'F
0266
026B
0269
026A
026C
026E
8821
FI
AO
8478
8490
B3
3C
EC41
J
*
.1'. Carriage
* * * ... ... .' * * * ... * * * * ... ,* '* * ... * * * * * * * * * *
Stepper Motor Deceleration
* * * * * * * * * * ... * * ... ... * ... * * * * * * ... * * * * * * * *
941
942 D.clBM:
943 "
8.tUp tha D.c.l .. atian ,.egist.,..
944
Mav
TStI'R,O ••8M,BEnd ,L.aad the 8tp" 1'110. Buff.,. End Add,.
Ma~
CntR40••OSBfSz 'Load the Buffe,. Si.e
94'
946 '
MOV
A. PhzR30
", g.t ph ••• indu .dd,. •••
947
MovP3
A.IA
'get ph •• e ,,.om indexed .dd ••••
948
patch togathe,. the CR la.t and LF next pha.e bits
Mav
TmpROO ••L•• tPh 'load La.t Ph. p.u_da ,.ag to T.mp Reg
949
CRL
A.ITmpROO
'patch togeth.,. CR exi.ting • new LF
950
MCYD
P4.A
,OUTPUT BITS
9'1
A.ITStrRO
,g.t tim_ '.am ind.xed data m.mo.y
9'2 Stl'tTD: May
MCY
T.A
'load timer
9'3
STRT
T
,START TIMER
9'4
Inc
TSt,.RO
,stap the M.mo.ized time addr ind.x .eg
955
te.t '0,. farwa.d
,..ve,. •• 'pha.e ota,.t indi •• ct index to load
9'6 ,
JMov
A.OStR20
lotore' .10.10 byte
9'7
.JB7
DclF2
9'8
9'9
960 , .eve.se:
961
Set up for next ph ••• bit output be'o". entering timing loops
962
Dec
PhzR30
idecrement the ph ••• addT"
,Oet the ph. data addr
A.PhzR30
963
MOV
DRZ,.oP
,CH,K FCR CCUNT BIT RCLLCVER'
964
.JB2
DNxtPh
96'
.IMP
Ph',R30.'.RStCRP ,'ZERO CR SM PHASE REOISTER
966 DRZ.oP: MCY
967
.Imp'
DclR2
968
969, 'fo,.wa,.d:
970 ,
S.t up for nut phase bit output befar. ent.,.ing timing loop.
,increment the pha .. add,. ,
PhzR30
971 OclF2: Inc'
972
MCY
A. PhzR30
,Oet the phz data addr
973
.JB2
DZ,.oPh
',CHK FCR COUNT BIT RCLLOVER
974
.IMP
DNxtPh
,skip .d. index reoet
Ph zR30 ••FStCRP ,ZERO CR SM PHASE REOISTER
97' DZ,.oPh: MCY
976 DNxtPh:
,set up for nex't pha.e shift
977 DclR2:
A. PhzR30
,g.t p'ha .. index .ddress
'
MCY
978
,g.t pha.e from indexed addr'aas
A.IA
MovP3
979,
p.tch tog.th.r the CR la.t .nd LF next ph •• e bits
980
Mov
TmpROO •• L•• tPh 'load Last Ph. psueda ,.ag to Temp Reg
981
ORL
A.IT~pROO
'patch together CR exi.ting • new LF
NxtPD2
,.IMP CN TIME OUT TC NEXT PH
982 TLaopD: .JTF
TLoopD
,LCCP UNTIL TIME CUT
983
.JMP
984 NxtPDi2: MOYD
P4. A ' '
,CUTPtlT BITS
CntR40.StrtTD
,Exit Te.t
D.JNZ
98'
'986
987 ,
Set
988 ,
next ph ••• is •• ~u.nc. correct for stpr mtr drive direction
~t~r
989 S.tRN:
990
991
992
993
994
99'
Mav
MCY
Mav
DI'IE xit: C.ll
C.ll
RET
996
997
998
•• g. of next pha •• data in psueda add,., This insu,.a.
TmpROO •• CPSAdr
A.PhzR30'
ITmpROO.A
DlyLng
D.Sl8M
,get Phz Store.ge ~ddr psuada reg
,g.t Ph. data
CR N.xt pha •• index add,.
'0100".
PG
J
* * * * * * .'. * * * .. * * * * ... '.,. * * * * * * * * * * * * ... * * * * *
Stepper Motor
All
999,
0300
'.100 •• the .tatu. byte
,stap the AID time data .100 •• add.
PG
940 ;
0237 B92'
0239 ICOA
OBtR20. A,
TBt.-RO
1000
1001
1002
1003
1004
'tOO,
1006
1007 ,
1008
1009 "
1010
1011
p"ogra~
* * ** ****
CRQ
P.~ase
Sb ift DefinitionS'
pracadura. call this data,
* * * * '* * * * * * * * * * * * * * * * *'* * * * * * * *
300H
,
DEFINE PHASE ADDRESSES:
THE PHASE DATA IS ENCCDED TC THE ADDRESS CALLED DURINQ THE
STPR MTR ENEROIZE SEQUENCE CCRRESPCNDING TC THE NEXT PHASE
'C~ ~HE SEQUENCE REQUIRED,
CARRAOE MCTCR, ENCCDINO
6-752
FORWARD
REYERSE
-
LEFT-ta-RIOHT"
RIOHT-to-LEFT' '
230795-001 '
0300
0301
0302
0303
01
03
02
00
0308
0308
0309
030A
030B
04
OC
08
00
1012 ,
1013 ,
1014
1015
1016
1017
10lB
1019
1020
1021
1022
1023
1024 ,
1025
1026
1027
102B
1029
1030
1031
1032
1033
030F 4400
direction ENCODING is the •• me
r.v.~ ••
DB
DB
DB
DB
b~t • • • cc •••• d
in
direction
CRMFPI
CRMFP2
CRMFP3
CRMFP4
** ** *** * • ******** *** * * * ** ** ** **
LF MOTOR PHASE ENCODE. DECODE: FORWARD (CLOCKWISE)
For~ard direction ENCODINQ:
ORQ
30BH
DB
DB
DB
DB
LFMFPl
LFMFP2
LFMFP3
LFMFP4
1034
PG
103~
* * * ~ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * *
1036
030C FA
030D B211
R.v.~.e
Accel/Decel I Character Handling Test
1037
** *>
* * Is* CR
* *Stpr
* * Mtr
* * *A.*Speed
* * *??* * * * * * * * * * * * * * * * * *
103B , * * * TEST
1039 I
Ve. - SetUp do Character Proc •• sing
1040
No - Calculat. I Store the Acceleration Ph.se Shift Time (11)
1041 , ----r---------------------------~-----------------------------------------~
1042
1043 ADPTst: Mov
A.QStR20
'get the st.tus b~te
1044
.JB5
,test if Stpr Mtr At Speed
PHFSet
1045
Jmp to Prnt Head Fire Setup
1046
..Imp
ADMmTS
i . l •• Call Ace.I/Deeel Memory Time Store
1047
1048
1049
J
* * ** *** ** ** ** *** * ** *** * * ** ** * *** *** * * *
Process Characters for Printing
1050
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
1051
1052
Character dot matrix ~ normal char
1053
Dot Column
1054
b =- Blank Column
1055
1056
b d d d d d
(Ch.'r Mat,.i x)
1057
105B
o 0 0 0 b
1059
000 1 d
1060
o0 I 0 d
1061
o 0 lid
1062
o 100 d
1063 I
o 1 Old
1064
1065
1066 PHFSet: ..INTO
Ret,."
;if R-O not r.ad~ to print-exit
1067
.JBl
NPRet
'if Do Not Print stat bit set - EXIT
106B
.JB6
SinkSt
iif blt p~eviousl~ set-skip setting it
May
1069
A.QStR20
'get the status bute
1070
ORL
A.IISnkS.t
'set Prnt R.ad~ Sink bit
1071
May
QStR20.A
isave the status b~te
1072 SinkSt: SEL
RBI
May
1073
A.ChStRI
;get char status register addr
1074
.JB6
PageCk
itest Char Init Done. 1
Print Dot
1075
o Qet ChaT'
1076
*
*
** **
=
0311
0313
0315
0317
031B
031A
031B
031C
031D
266B
326A
D21B
FA
4340
AA
D5
FA
D23A
=
1077
031F
0320
0322
0324
0326
0327
FI
03F3
C626
6437
FA
F22B
0329 6432
107B
1079
lOBO
lOBI
10B2
IOB3
1084
10B5
10B6
10B7
10BB
1089
1090
1091
=
PG
Call for Individual
cha~acter
processing:
mid line test if CR/(LF)
QetChr:
test for CRI (LF,) i f it is the test position ~ the line
CRChCk, Mov
A.@CAdrRl
; get charecte-r
ADD
A.IICRCpl
itest for Carriage Return
.JZ
CrLnCk
if CR go service it
..Imp
Aniel
'if not CR Insert Space Char
CRLnCk: Moy
A.ChStRI
;get cha~ status register addr
.JB7
HlfLn
,test Chr Stat B~te Returned
if bit 7 - 1 then Print L-to-R
..Imp
SpFi 11
; if R-to-L p~int skip exit upon CR detect
, -----------------------------------------------------------------------
6-753
230795-001
AP-161
0328 FD
032C 03D9
032E F632
0330 648A
, 0332 97
0333 2320
0335 6438
0337 Fl
0338 7498
033A
0338
033D
033F
0341
FA
8241
F4EB
6443
D4FO
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
HlfLn:
Jmp
SpFill.
LnPad:
Clr
Mov
Jmp
;
0343 EB61
0345
0346
0348
0349
0348
034D
034F
FA
538F
AA
ED58
53FD
53FE
AA
0350
0351
0352
0354
0355
0356
C5
FA
53FE
AA
D5
6468
0358 FA
0359 F25E
035819
035C 6468
035E C9
035F 6468
0361 FA
0362 F267
0364 CC
0365 6468
0367 IC
~xit
MdLnEx
the line if less'than 1/2 line printed
load ch.~ cnt reg w/cher bufr lize
,add the 2'. cpl of 1/2 chr buf size
, if CB>1/2 full set CR/LF stat bit for
, If CB<1/2 •• t buffer full stat bit
; rni'd-line exit
J
A,ISpaee
Ch Isrt
Jclear c.rr~ 91ag
; insert a space char
;char inserted Jmp over get chaT
GCharl
,call the char lookup/trns table
C
p~d
---------------------------------------------------------------------A•• CAdrRI
'get character
AsclCl: Mov
ChIsrt: Call
, ---------------------------------------------------------------fetch the char dot column data
;
PageCk.
Mov
J85
FxJmp I:
Call
Jmp
Call
A.ChStRI
F.Jmpl
ChrPg2
MtxTst
ChrPgl
ipage test for balance of char
'get the status byte
if1x Jmp over page boundries
,Ascii char 50 - 7F He.
I Jump to Matrix Test
,Ascii char 20 - 4F He.
fall thru to print matrix
and CD count tests
PG
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
·1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
if L-to-R printing
Mov
A,CCntRI
ADD
A•• HlfCpl
JC
LnPad
, -------------------------------------------------------------------------test the Chi." dot column print matri x count and Char buffer count
MtxTst: DJNZ
CDtCRI. PrntDt
Mov
ANL
Mov
DJNZ
ANL
ANL
Mov
A.ChStRI
A•• ClntND
ChStRl.A
CCntRI.NotLCh
A•• NCBFln
A•• CnCBR
ChStRI. A
SEL
Mov
ANL
Mov
SEL
Jmp
RBO
A.GStR20
A•• NotRdy
GStR20.A
RBI
RetT'n
,
itest foT' dot color blank
jstatus b~te i~ A upon entr~ heT'.
'get the status byte
,.et Char Init NotDone stat Flag
,store the status byte
Idec char cnt-Jmp if Not Last Char
'if 0 reset stat bit Not CB Full Line
,reset CB Reg Init Flag - do Init
isave the status b~te
'get GIn Status register addr
ic1.ar the read~ bit
J sto,.'. the GeneT'sl Status B~te
, EXit
Test for L-to-R (forward) or R-to-L (reverse) printing
(see GChaT'l ASCII chaT' code translation procedure)
NotLCh:
Mov
JB7
StpCh I'
Inc
Jmp
StpCh2: Dec
Jmp
A. ChStRI
StpCh2
CAdrRI
Retrn
CAdrRI
Retrn
,A contains LR/RL bit properly set
igat char status T'egister addT'
,test Chr Stat 8yte Returned
if bit 7 = 1 then Print L-to-R
i Increment char data memQr~ addT'o
iDecrement char data memor~ addr,
fall thru to Get Char
, -------------------------------------------------------------------------Re-Entry Exit point faT' same char:
(befDT'. retuT'ning step the matrix)
, -----------------~-------------------~-----------------------------------Test faT' L-to-R (fDr~ard) OT' R-to-L (reveT'se) printing
,
(.~e GCharl ASCII char cod. translation procedure)
1156 , -------------------------------------------------------------------------1157
1158 PrntDt:
1159 PrnDi r: Mov
A.ChStRI
iget chaT' status byte
1160
J87
StpCD2
,test Chr Stat Byte Returned
1161
,
if bit 7 = 1 then Print L-to-R
1162 StpCDI: Dec
.revers. step chaT' dot ,c~l ihdex
CDotRI
1163
addr if R-to-L print
1164
Jmp
Retrn
,skip over L-to-R print addr inc
1165 StpCD2: INC
; 'foT''waT'd step chaT' dot col in'dex
CDotRI
1166
I'
addr i f L-to-R print
, E'XI'r
1167
1168
1169
PG
230795-001
inter
0368 C5
0369 83
036A 05
036B FA
036C F27C
03bE
036F
0370
0372
C5
FA
53BF
83
0373 027C
0375
0377
0378
037A
037C
037E
037F
0381
0382
0383
0384
0386
0387
0388
0389
038A
0388
0380
038F
0390
0391
0392
0394
0396
0397
4340
AA
B807
6488
E888
FA
53BF
AA
C5
FA
53FE
AA
83
C5
83
FA
53FO
53FE
AA
C5
FA
4302
53BF
AA
83
AP-161
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
0398 AE
0399
0398
0390
039F
03AO
03EO
F69F
64C9
97
FE
03AI 03BO
03A3 F6AE
03A5
03A6
03A8
03A9
03AA
03AC
FA
4320
AA
FE
03EO
64B8
, -------------------------------------------------------------------,
Cha~acta~ P~Int SatUp Exit P~ocadu~as
, -------------------------------------------------------------------,
Clean Shnda~d Exit
, -------------------------------------------------------------------Ret~n:
SEL
RBO
Rat
,EXIT - ~etu~n wI Rag lank 0 Reset
,
NPRat:
00 Not
SEL
, Rev.,. ••
BEL
Mov
ANL
Ret
, Forw.rd
exit:
RBI
A.ChStRI
SkpNPI
P~int
set Stpr
RIO
A.QStR20
A••Cl~Snk
Mt~
d~Ive
~outine
count loop
'gat tha .tatus b~ta
,te.t p~int di~action
,get the .tatus b~te
,~a.at the print ~ead~ bit- skips
PHFi~a
call
SkpNPI
,test fo~ fl~st PHFSet ent~~ ~eg Init
Initialize ~egiste~ va~iables upon fl~st ent~~
and of count clea~s cha~ to p~Int bit In status b~t.
ORL
A••ChlntD
,set Cha~ Reg Inlt Done stat bit
Mov
ChStRl.A
,sav. the .tatus b~te
Mov
TmpRI0 ••07H
.load CR stp~ mt~ count du~lng NoPrnt
~mp
NPEx i t
SkpNPI: D~NZ
TmpRI0.NPExit
.gat tha status byte
Mov
A.ChStRI
Jr ••• t - ch.r init not don_
ANL
A••ClntND
Mev
ChStRl.A
i'.V. the statuI b~t.
SEL
RBO
Mov
A.QStR20
.get Qen Status ~egl.te~ .dd~
ANL
A•• NotRdy
;cl •• ,. the r •• d~ bit
Mev
QStR20.A
.sto~a tha Qana~al Status I~te
NSetEx: Ret
NPEx I t: SEL
RBO
Ret
~B6
Mld-LIna Exit
, -------------------------------------------------------------------EXIT - i f CR and not > 1/2 lina dona du~ing L-to-R p~int
.gat tha status byta
MdLnEx: Mov
A.ChStRI
, if 0 ~esot stat bit Not CI Full Line
ANL
A••NCBFln
'~eset CI Reg Init Flag - do Init
ANL
A•• CIICIR
ChStRI, A
il.V. the statuI b~t.
Mov
RBO
SEL
A.QStR20
'get the RBO status byte
Mov
,set the 00 Not Print Flag(fo~ RAccel)
A•• DoNotP
ORL
.~o.at the p~int ~ •• dy bit-exit FAccol
A•• Cl~Snk
ANL
QStR20.A
Mov
i'.V. the statuI b~t.
Ret
PG
1222
1223 ,.
Charact.,. Dot gener.tor Math
1224
Look-up Table Page Vacto~lng
1225 ,
Print H.ad Firing
~226 , ---------------------------------------------------------------1227
St~CRI. A
,STORE THE CHAR
1228 QCHAR1: MOV
1229
1230
scr.en for printable
1231
A•• OEOH
ADO
1232
PrntCh
~C
1233
Jmp
CntlCh
'Jmp to cont~ol cha~ lookup tabl.
lei •• ,. c.,.,.~ flag
1234 P~ntCh: Clr
C
1235
A.St~CRI
;get the char again
1236
1237
le" •• n foT' cha~ pago Cch.~ +(cpl 50 Hex + 1 • 10 Hex)]
1238 ,
i f cnry cha~ on pa.e 2 01.0 page 1
1239
ADO
A/.OBOH
1.40
~C
Page2
1241
1242
Page
Cha~.cter -- ASCII 20 Hex thru 4F Hex
1243
Correct offset for lookup table page
1244
{(char + EO Hox)*5 • Page 1 indox addr)
1245 I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1246 Pagel: Mov
A.ChStRI
'get the status byte
1247
OrL
A•• ChOnPI
.s.t tho pago ~ont~y flag bit
1248
Mov
ChStRI.A
.sto~e the status byte
1249
Mov
A.St~CRI
,got the cha~ aglan
1250
ADO
A•• OEOH
•• et page I ~.lative 00 offset
1251
~mp
Multi5
'Jump to add~o •• math function
1252
6-755
230795-001
AP-161
03AE
03AF
0300
0302
0303
0384
03B6
97
FA
530F
AA
FE
03BO
64B8
0388
03B9
03BA
03BB
03BC
AE
E7
E7
6E
AC
0380 FA
03BE F2C4
03CO FC
03Cl 0304
03C3 AC
03C4
03C5
03C7
03CB
FA
4340
AA
83
03C9 B3
03CA 05
03CB FO
03CC 9602
03CE
0300
0302
0304
0305
0307
0308
0309
OB06
6408
2340
3A
23CO
3A
C5
B3
1253
1254
1255
1256
1257
125B
1259
1260
1261'
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
12B8
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
0400
0402
0404
0406
OC04
BB22
2308
AO
0407 BEOI
0409 841B
Page2:
Clr
Mov
AnL
Mov
Mov
AOO
Jmp
Compute
MUL TIS: Moy
RL
RL
AOO
MOV
carry flag
Jgst the status bVte
'set the page rentry flag bit
; store ~h. statu_ bvte
jgst the char agian
,set page 2 relative 00 offset
ifal1 thru to address math function
Jclea~
C
A,ChStRI
A,IIChOnP2
ChStR1.A
A,StrCRI
A.II0BOH
Multi5
character page offset dot pattern index address
StrCR1,A
Jstare the zero offset char
,MULTIPLY CHR BY 5 TO
A
FINO THE ADORESS
A
A,StrCRI
,ADD 1 TO COMPLETE 5X
CDotR1, A
,SAVE THE ADDRESS
Test for L-to-R (forward) or R-to-L (reverse I printing
(see Gehert ASCII char code translation procedure)
Moy
JB7
A,ChStRI
LRPrn
MOV
AOO
A,CDotRI
A,IIRLPShf
'get char statu. byte
,test Chr Stat Byte Returned
if bit 7 = 1 then Print L-toR
jget the char index addr
,add char offset - start at .nd
MOV
CDotR1, A.
• SAVE THE ADDRESS
j
of chaf.#
print i t R-to-L
Set the status bvte for Character SetUp done
i
----------------------------------------------------------------
LRPrn:
Moy
A,ChStRI
ORL
A,IIChlntD
Mov
ChStR1,A
Ret
1
test for non printable
CntlCh: Ret
.get the status byte
• set 1st char c'ol test .. it - 0
isto~e the status byte'
ireturn wlstatus byte in A
cha~acters goes here
* * * *Print
* * Head
* * *Fire
* * * * * * * * * * ,* * * * * * * * * * * * * * * * *
* * * * * * * * ~ * * * * * * * * * * * * * * * * * * * * * * * * * * *
Ent~y point for print head solenoid firing
- test for status byte for dot/blank column position
PHFire: SEL
RBI
Moy
A.COtCRI
iset the ch~ dot column cnt
Fire
JNZ
iif char cnt nat 0 - Fire Head Sol.
.if Chr Dot Cnt 0, res.t the
SetCnt: Mov
CDtCRl,IINDtCCt
char dot column count
Jmp
Retrn1
; skip PH Fire
A,IIPTrgLo
Fire:
MOV
'get the Prnt Head Trigger byte
P2,A
OUTL
,FIRE PRINT HEAD
MOV
A,IIPTrgHi
.get the Prnt Head Trigger byte
P2,A
OUTL
.FIRE PRINT HEAD
Retrnl: SEL
RBO
Ret
iEXIT - ~eturn wI Reg Sank 0 Reset
1312
PG
1313
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
1314
0400
Page 2 Character -- ASCII 20 Hex thru 4F Hex
Co~~ect offset fD~ lookup table page two's complement
of ASCII chr code LookUp Table page bas. char of 50H plus
char * 5 {(char + BO Hex)*5 a Page 2 index addr),
PaperFeed Stpr Mtr Drive
1315
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
1316
1317
ORG
400H
1318
1319
Inlt psuedo regIster with LF inderect addr start - subs.~uent
exchanges of the psuedo register will yi~ld correct value,
1320
CntR40.IIILFCNT .INIT PHASE COUNT ~EG
1321 InitLF: MOV
Mav
TmpR00J ttLPSAdr ; get Phz Inderect Addr psue,do· reg
1322
1323
MOV
A,IIStL"'"
• get LF star)ting addr
Mav
@TmpROO,
,store LF phase index addr start
1324
in psueda register
1325
Mov
LnCtRO,#LlneCt isat line count reg fo~ 1 In
1326
1327
; enables exit fol10"'ing LF S.M init
4mP
LfDrv1
Jump OV~T' ~~_
I'Pen"!'1 ~eed amd variable
1328
1329
lIne ~pacing tests & setups
1330
1331
LineFeed I FormFeed Drive
*
I
6-756
230795-001
AP-161
0401 BCl1
040D
040E
0410
0412
0414
0415
0416
0418
FA
5214
BEOI
8.41B
FE
37
0301
0342
041A AE
1332 , ----------------------------------------------------------------------1333
1334 ,
1335 , --------------------------------------~-------------------------------1336
t.st 'or v.~iou. line/inch spacing would go h.~.
1337
520
0521
C5
230F
3E
23FF
39
23CO
3 ...
8 ...03
B... OO
D5
B... OO
C5
83
F...
.get the ph.,e Index address
• store LF Next pha.e Ind •• addr
or
Check if Char Buffer >ontaln. full line (SO char
nChar • CR)
exit oth.r~j •• continue to read in char.cters
Mov
.... GStR20
.get the .tat byte
~Bl
BVPa.l
.If DO Not Print Bit Set - EXIT
Call
CBFck
Ret
1428
PG
1429 •
* ** * * **** * ** ** * * ** * ** ** * * ** *** * *****
1430
0500
.... Ph.R30
.TmpROO ....
Dl~Lng ,
D.S1SM
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
Minor Software Subroutines
*** ****** * * * ***** ****** **** *** * *****
ORG
J
•
500H
----------------------~----------------------------------------
Sv.tem initlall'ation subroutine.
--------------------------------------------------------------Ddalt:
• --------------------------------------------------------------•
re.et/set EOF Itatu. flag bit. 0
SEL
RBI
Mov
.... ChStRI
.get the char .tatul byte
...NL
.....C1 rEOF'
.clear the EOF flag bit
Mov
ChStRl ....
..tore the char statu. byte
Mov
TmpRI0 •• PT .... cS .get the .... cii code tmp .tore addr
Mov
,.TmpRI0.,..... cii • load the tmp s·tor reg .. / •• cii .tart
SEL
RBO
--------------------------------------------------------------reset/.et Ok~tO-Prlnt .tatus flag b i t . 0
M,ov
.... GStR20
" getth • • tatus byte
...NL
..... OkPrnt
.reset print flag - Ok Print
Mov
GStR20....
..ave ·the statu. byte
RET
Ini t"'l:
"'llOH:
--------------------------------------------------------------CLE... R all output.
SEL
RBO
MOV
.....OFH
• FORCE PORT HI - RI OF 555
MOVD
P6 ....
MOV
..... OFFH
• TURN ALL PRNT SOL'. OFF
OUTL
P1,A
MOV
A,.PTRGHI
.prlnt h.ad fir. tirgger Inactive
OUTL
P2.A
ORL
P2 ••03
•• et comm hd.k to ACK hi/Busy hi
Mov
GStR20 •• 00H
.clear the statu. registers
SEL
RBI
Mov
ChStRl •• 00H
SEL
RBO
RET
• RETURN TO INIT ROUTINE
1472 r PG
0522
0523
0525
0526
F...
4302
......
362...
052S 3402
052... 3422
052C B474
052E 83
052F B87F
0531 B95D
0533 8000
1473 • * * *
1474 •
1475 •
* **
1476
. 1477 CRHome:
1478
1479
1480
1481
1482
1483 RtoL:
1484
1485
1486
1487
1488
** *
1489
1490
1491· * * *
1492
1493 1
1494 ClrDM:
1495
1496 ClrDM1:
*Home
* *Carriage
*'* * * *I *Print
* * *H.ad
* *.*
* ****** ** ** *** *** *
A•• emblv
* * * * * * * * * * * * * * * * * * * * * * * * * '. * * * * * * *
Mov
ORL
Mov
~TO
A.GStR20
A••OoNotP
GStR20.A
RtoL
Call
Call
FAcc_l
RAccel
Call
RU
DIVVLg
.get the .tatu. byte
.set the do not print flag
•• ava the .tatu. byte
,t.st for po.ltlon of PH •••• mbly
drive accordingly
• dr I ve CR' St"" Mtr
.find the logical left ho~. CR position
idel_, a lang time b.fo~. continuing
*Clear
* * Data
* * *Memorv
*"* * * * * * * *'*.* * * * * * * * * * * * * * * * *
* * * * *'* * * * * * * * * * *,* * * * * * * * * * * * * * * * *
At Po .. erUp or R.a.t. follo~tng CR • LF Stpr Mtr Init. this
procedure clears data memory above RBO. Stack and RBI.
MOV
RO ••OMTop
.QET BUFFER ST...RT LOCATION [HEX]
MOV
Rl ••0MSIZE
• ZERO ,MEMORY LOCATION
MOV
.RO•• OOH
6-75a
230795-001
AP·161
0535 C8
0536 E933
0538 83
0539 197F
053B ID50
053D
053E
053F
0540
0541
0543
0545
0547
0549
054A
FF
AI
C9
IF
0382
9647
BF20
ED3D
C5
83
0541 IC04
054D 2308
054F 3D
0550 IDCO
0552 1100
0554 FI
0555 E3
0556 3C
0557 FD
055862
0559 55
055A IB
,0558 FB
055C 5260
OS5E A462
0560 BBOO
0562
0563
0564
0566
0568
0569
FB
E3
1669
A464
3C
EC57
0561
056D
056E
056F
0571
0573
B821
FB
AO
B478
B490
83
1497
1498
1499
1500
0578 B880
057A A47E
RO
RI.
•?
.e
.A
.B
.C
ID
IE
•.Q
F
.H
•I
.,J
.K
.1.
.11
.t.et
J
te.t
.N
.D,
--------------------------------------------------------------------Ch.~ •• t.~ Dot P.tt.~n Fetch
End P.g'. 1
--------------------------------------------------------------------Character Dot Pattern Fetch
=1735
06FO FC
06Fl A3
DB
DB
-DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
-1736 • ---------------------------------------------------------------------1737
Jget char index .dd~.s. offset"
-1738 Ch~Pgl: I1DV
A.CDotRI
;get column dot patern byte
AdlA
-1739
I1DVP
-1740
06F2 4380
06F4 39
06F5 83
this bit fix n.c.ssar~ to not underline each. character
this saves fixing each bit in the look up table
-1741
-1742 •
-1743
=1744
-174:5
=1746
-1747
=1748
-1749
-1750
-1751
-1752
ORI.
Dutl.
RET
Patte~n
G~nerator
Fetch
Look-Up Table
50H' ---------------------------~--------------> 7EH
.. NOPORSTUVWXYZ(\] .... _(?)abcdefghiJklmnopq,rstuvwxvz
--------------------------------------------------------------------SNol.IST
Sl.ist,
•
Listing below 15 for reference only, actual code is not listed
at aS5embl~ time,
I
«<
--------------------------------------------------------------------OOH. 76H, 76H. 76H. 79H
IP
asc50
DB
,Q
DB
41H. 3EH. 2EH. 5EH. 21H
.R
DB
OOH. 76H. 66H. 56H. 39H
IS
59H. 36H. 36H. 36H. 4DH
a.c53
DB
asc54
DB
7EH. 7EH. OOH. 7EH. 7EH
•IU
T
asc'55
40H. 3FH. 3FH. 3FH. 40H
DB
IV
60H. 5FH. 3FH. 5FH. 60H
• asc56
DB
IW
OOH. 5FH. 67H. 5FH. OOH
-1830 • ascS7
DB
I X
-1831
ascS8
DB
lCH. 6BH. 77H. 6BH. lCH
IY
7CH. 7BH. 07H. 7BH. 7CH
-1832 • asc59
DB
, asc51
asc52
6-761
230795-001
/
inter
AP-161
-1833 I .sc5A:
-1834
a5e5B:
-1835 I ... e5C:
=183b
.se5D:
-1837 I .se5E:
-1838
•• c5F:
-IB39
a .. bO:
-1840 I •• e61:
=1841
... eb2:
-1842
.... eb3:
-1843 I •• e64:
=1844
.. se65:
=1845
•• ebb:
... e67:
=1846
=1847
... e68:
-184B
... eb9:
=1849
•• e6A:
-1850
•• ebB:
=IB51
asc6C:
-1852
ase6D:
=1853 , ase6E:
-1854
asc6F:
-1855 I ••. e70:
=IB56
•• e71:
=1857
a •• 72:
,".e73:
=lB58
=1859
.. s.74~
=lS60
••• 75:
=18bl
•• e76:
.... 77:
=1862
=1863 I •• e7B:
=1864
•• e79:
.... 7A:
-1865
-1866 i ASC7B:
-1867 I ASC7C:
-1861;1 , ASC7D:
-1869
ASC7E:
=1870
=1871 I
=1872
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
,I Z
,\
IEH. 2EH. 3bH. 3AH. 3CH
OOH. 3EH. 3EH. 3EH. 7FH
7DH. 7BH. 77H. bFH. 5FH
7FH. 3EH. 3EH. ;iEH. OOH
bFH. 77H. 7BH. 77H. bFH
3FH. 3FH. 3FH. 3FH. 3FH
7DH. 7BH. 77H. OFFH. OFFH
ODFH. OABH. OABH. OABH. OB7H
080H. OB7H. OB7/'1. OB7H. OCFH
OC7H. OBBH. OBBH. OBBH. OBBH
OCFH. OB7H. OB7H. OB7H. OBOH
OC7H. OABH. OABH. OABH. OB7H
OF7H. 081H. OFbH. OFEH. OFDH
OF7H. OABH. OABH. OABH. OC3H
080H. OF7H. OFBH. OFBH. 087H
OFFH. OBFH. 08BH. OBFH. OFFH
ODFH. OBFH. OBBH. OC2H. OFFH
OFFH. 080H. OEFH. OD7H. OBBH
OFFH. OBEH. 080H. OBFH. OFFH
087H. OFBH. OE7H. OFBH. 087H
OB3H. OF7H. OFBH. OFBH. OB7H
OC7H. OBBH. OBBH. OBBH. OC7H
084H. OEBH. OEBH. OEBH. OF7H
OF7H. OEBH. OEBH. OEBH'. OB4H
OFFH. OB3H. OF7H. OFBH. OFBH
OB7H. OABH. OABH. OABH. ODBH
OFBH. OCIH. OBBH. ODFH. OFFH
OC3H. OBFH. OBFH. OBFH. OC3H
OE3H. ODFH. OBFH. ODFH. OE3H
OC3H. OBFH'. OCFH. OBFH. OC3H
OBBH. OC7H. OEFH. OC7H. OBBH
OFFH. OB3H. OAFH. OAFH. OC3H
OBBH. 09BH. OABH. OB3H. OBBH
07FH. 077H. 049H. 03EH. 03EH
OFFH. OFFH. 088H. OFFH. OFFH
03EH. 03EH. 009H. 077H. 07FH
067H. 07BH. 067H. 05FH. 067H
[
I ]
,A
1\
I.
Ib
Ie
Id
I.
If
I g.
Ih
, i
I J
I k
I I
1m
In
,a
IP
''I
'"
"I t
IU
,v
I ..
I x
, U
I •
I(
I I
I)
,~
-------------------------------------------------------------Character Dot Pattern Fetch
--------------------------------------------------------------
07EB FC
07EC A3
07ED 4380
07EF 39
07FO 83
-IB73
-1874
-1875 Ch"Pg2:
-IB76
-IB77
-1878
=1879
=IBBO
-18Bl
=1882
=1883
1884
1885
MOV
MOVP
. A. CDotRl
AdlA
'get eh .. " index add" ••• off.et
,g.t column dot p.te"n bute
this bit fix n.c.s •• r~ to not
und.~lin.
each
ch.~.ct.r
this sav •• fi.ing .a.h bit in the look up table
ORL
OutL
RET
A.1I80H
Pl. A
,eh." bit fix
,output the dot patt."n
;Ixit with
b~t.
in ace
188b
1887 J
1888
1889
1890
1891
ASSEMBLY COMPLETE.
** * * * *** ** ** ** ** *** * * * *** ***
Program End
** * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
END
NO ERRORS
6-762
230795-001
AP-181
APPENDIX B.'
SOFTWARE PRINTER
ENHANCEMENTS
This section describes several software enhancements
which could be implemented as additions to the software developed for this Application Note. Space is
available for most of the items described. Approximately 5 bytes of Data Memory would be required to
implement most of the features. Two bytes would be'
used for status flags, and two bytes for temporary data
or count storage. It is possible to use less than five bytes,
but this would require the duplicate use of some flags,
or other Data Memory storage, which will significantly
complicate the software coding and debug tasks.
Special Characters or Symbols
Dot matrix printing lends itself well to the creation of
custom characters and symbols. There are two aspects
to implementing special characters. First, a character
look-up table, and second, additional software for dec
oding and processing the special characters or symbols.
Special characters might be scientific notation, mathematical symbols, unique language characters, or block
and line graphics characters.
The character look-up table could be an additional
page of Program Memory dedicated to the special
characters, or replace part, or ali, of the existing lookup tables. If an additional look-up ta~le is used, a third
page test would be needed at the beginning of the Character translation subroutine. There is fundamentally
no differ:ence between the processing of special characters and standard ASCII printable characters. If the
characters require the same 5 x 7 dot matrix, the balance of the software would remain the same. If, however, the special characters require a different matrix, or
the manipUlation of the matrix, the software becomes
more complex.
In general, the major software modification required to
implement special characters is the size of the dot
matrix printed or the dot matrix configuration used. In
the case of scientific characters, it would often be
necessary to shift the 5 x 7 matrix pattern within the
available 9 x 9 matrix. Block or line graphics characters,
on-the-other-hand, would require using the entire 9 x 9
print head matrix and printing during normally blank
dot columns. This would require suspending the blank
column blanking mechanism implemented in this Application Note. This would be the most complex aspect of
implementing special ~haracters. It would possibly
change the number of required instructions, and thus
the timing between ,PTS detection .and print head
solenoid trigger firing. This could cause the dot columns
to be misaligned within a printed line and between lines.
In the case of a matrix change, two approaches are
possible: dynamically changing the matrix, in line, as
standard ASCII characters are being printed, or
isolating the special characters to a separate processing
flow where special characters are handled ,as a unique
and complete line of characters only. A discussion of in
line matrix changes for special characters is beyond the
scope of this Appendix. It is sufficient to say that the
changes would require the conditions setting the EO LN
flag, character count, and dot column count software be
modified during character processing and printing:
Lower Case Descenders
The general principle of implementing lower case des- •
cenders is to shift the 5 x 7 character dot matrix within
the available 9 x 9 print head solenoid matrix. Implementing lower case descenders requires two software
modifications and the creation of status flag for the
purpose. First, the detection of characters needing descenders and setting a dedicated status f).ag during the
character code to dot pattern translation subroutine.
Second, the character dot column pata output to the
print head solenoids must be shifted for each dot
column of the character. At the end of the character, the
flag would be reset.
'
Inllne Control Codes
Inline control codes are two to three character sequences, which indicate special hardware conditions or
software flow control and branching. The first character indicates that the control code sequence is beginning
and is typically an ASCII Escape character (ESC),
I BR. Termination of the inline code sequence would be
indicated by a default number of code sequence characters. This would decrease the buffer size available for
characters. Full SO' character line buffering would
require loading the Chilracter Buffer with a received
character as a character is removed from it and
processed. ,
The Inline Control Code test would be performed in
, two places: in the Character Buffer Fill subroutine and
in the Character Processing (trallslation) subroutine.
The test would be performed in the same manner that a
Carrnage Return (CR) character code test is implemented. Examples are horizontal tabs and expanded or
• condensed character fonts. In the case of horizontal
tabs, 20R (Space Character) would have to be placed in
the Character Buffer for inline proc;essing during character processing and printing. Unless fixed position
tabs are used, a minimum of a nibble of Data Memory
would be required to maintain a "spaces-to-tab" count.
Fixed tab positions could be set via another inline
control code, by default of the printer software, or
through the use,of external hardware switch settings.
The control code method of setting the tab positions is
the most desireable, but the most complex to implement.
Different Character Formats
Figure BI illustrates three different character fonts;
standard, condensed, and enlarged or expanded characters. As the the figure illustrates, condensed and
6-763
230795~01
inter
AP-161
enlarged characters are variations in either the number
of dots and/ or the space used to print them. Thus, each
character is a variation of the stepper motor and/ or
print head· solenoid trigger timings. Figure B2 illustrates the "timings required to implement the additional
.
character printing. .
• In addition to the three character fonts sbown, it is
possible to print each in bold face by printing each dot
twice per dot column position. This would require little
software modification, but would require a status flag.
Again, care must be used to ensure that the delay in
. retriggering the solenoids is precisely the same for each
type of event. Without this precise timing the dot
column alignment will not be accurate. The software
modifications needed to implement enlarged or condensed characters is essentially the same. The carriage
and print head solenoid firing software flow is the same,
but the timing for each changes. For condensed characters, the step Time Constant is doubled to approximately 4.08 ms, and the solenoids are fired four times
within each step time. The step rate actually becomes a
multiple' of the solenoid firing time, and a counter
incrementing once for each solenoid firing would be
needed. At the count offour, the carriage stepper motor
is stepped and the counter reset.
In the case of condensed characters, PTS does not play
the same roll as in standard or enlarged character printing. PTS is not used to indicate the optimum print head
solenoid firing time. Solenoid firing is purely a time
function for condensed characters. PTS would only be
used for Failsafe protection.
Enlarged characters would require the solenoids be
fired twice per dot column data, in two sequel)tial dot
columns, at the same rate as standard characters. The
character dot column data and dot column count would
not be incremented at each output but at every other
.output. A flag could be used for this purpose.
When printing either condensed or enlarged characters,
the maximum character count would have to compensate for the increased or decreased characters per line
count. When printing enlarged characters, the maxi-
mum characters per line would btl 40. The Character
Buffer could hold two complete lines of characters. But,
condensed characters presents a quite different situation. The available character per line increases to 132,
.well beyond the 80 character Character Buffer size. the
solution is to re-initialize the Character Buffer Size
Count register count during condensed character processing. This will effectively inhibit the carriage stepper
motor drive EOLN detection.
Two status flags would be required; one for standard or
enlarged characters, and the second for condensed
characters. A third status flag would be required to
implement bold face printing. Activating one of the
alternate character fonts could be either through the use
of external status switches or through inline control
code sequences, as detailed above. Note, that if the
alternate character fonts are implemented in such a way
that format changing is to occur dynamically during
any single line being printed, the same. control code
problems described above also apply. In addition, the
effect on the timing and dot column alignment must
also be investigated.
Var~able
Line Spacing
Variable line spacing is another feature which could be
implemented either through the use of external status
switches or inline control codes. The line spacing is a
function of the number of steps the stepper motor
rotates for a given line. Figure 15, Paper Feed Stepper
Motor Predetermined Time Constants, in the Background section above, lists the Time Constants required
for three different line spacings; 6, 8, and JO lines per
inch. At the beginning of the Paper Feed Stepper
Motor Drive subroutine, the default line step count is
loaded. The software required is a conditional load for
the line spacing, indicated by a status flag set in the
External Status Switch Check subroutine or the Character Buffer Fill subroutine. Implementing the three
different line spacings would require two additional
status flags.
6-764
230795"()()1
AP-161
APPENDIX C.
PRINTER MECHANISM
DRIVE CIRCUIT
~~C':':l-___~Q,,1~--""'''''i4)-.......,smo1LENOID 1
PRINT PULSE 1
5OO± 201'1
PRINT PULSE 9
I
SOLENOID 9
'--,-;::=t:::;"";';;';';"'"1:=:::;--,r-V8041A Interface Register
Decoding
The flow charts of figure 9 show the flow of sample
host software assuming a polling software interface
between the host and the controller. The WRITE
command requires two additional count bytes which
form the I6-bit byte count. These extra bytes are
"handshaked" into the controller using the IBF flag
in the STATUS register. Once these bytes are
written, the host writes data in response to IBF
being cleared. This continues until the host finds
OBF set indicating that the operation is complete
and reads the result code from DBBOUT. No
testing of BUSY is needed since only the result code
appears in the DBBOUT register.
STATUS
OBF-OUTPUT BUfFER FULL
ISF-INPUT BUFFER FULL
FO-FLAG 0
l1~g~~~F1_FLAG
DRIVE ACTIVE
1
FILE PROTECT
CASSETTE PRESENCE
BUSY
The READ command does require that BUSY be
tested. Once the READ command is written into the
Figure 8. Status Register Bit Definition
6-775
AFN.()l342A
APPLICATIONS
controller, the host must test BUSY whenever OBF
is set to determine whether the contents of DBBOUT
is data from the tape or the result code.
THE CONTROLLER SOFTWARE.
The UPI-41A software to control the cassette can be
divided up into various commands such as WRITE,
READ and ABORT. In a previous version of this application note (May 1980), software was described that
implemented these commands. This code however did
not adequately compensate for speed variations of the
motor during record and playback nor for data distortion caused by ,the magnetic media. Since then, new
code has been written to include these effects. This
revised software is now available through the INTEL
User's Library, INSITE. For more information on this
software or INSITE, contact your local INTEL Sales
Office.
6-776
AFN.ol342A
8041~8641~8741A
UNIVERSAL PERIPHERAL INTERFACE
8·BIT MICROCOMPUTER
• 8·Blt CPU plus ROM, RAM, I/O, Timer
and Clock In a Single Package
• One 8·Blt Status and Two Data Regis·
ters for Asynchronous Slave·to·Master
Interface
• Fully Compatible with All
Microprocessor Families
Ii Interchangeable ROM and EPROM
Versions
.3.6 MHz 8141A·8 Available
• Expandable I/O
• DMA, Interrupt, or Polled Operation
Supported
• RAM Power. Down Capability
• 1024 x 8 ROM/EP~OM, 64 x 8 RAM,
8·Bit Timer/Counter, 18 Programmable
I/O Pins
• Available in EXPRESS
-Standard Temperature Range
-Extended Temperature Range
• Over 90 Instructions: 10% Single Byte
The Intel'" 8041A18741A is a general purpose, programmable interface device designed for use with a variety of 8-bit
microprocessor systems. It contains a low cost microcomputer with program memory, data memory, 8·bit CPU, I/O
ports, timer/counter, and clock in a single 40-pin package. Interface registers are included to enable the UPI device to
function as a peripheral controller in MCS-48™, MCS-80™, MCS-85™, MCS-86™, and other 8·bit systems.
The UPI.41A TM has 1K words of program memory and 64 words of data memory on-chip. To allow full user flexibility the
program memory is available as ROM In the 8041 A version or as UV-erasable EPROM in the 8741A version. The 8741A
and the 8041 A are fully pin compatible for easy transition from prototype to prOduction level deSigns. The 864M is a
one-time programmable (at the factory) 8741A which can be ordered as the first 25 pieces of a new 8041A order. The
substitution of 8641A's for 8041A'$ allows for very fast turnaround for initial code verification and evaluation results.
The device has two 8-bit, TTL compatible I/O ports and two test inputs.llndividual port lines can function as either in·
puts or outputs under software control. I/O can be expanded with the 8243 device which is directly compatible and has
16 I/O lines. An 8-bit programmable timer/counter Is included in the UPI device for generating timing sequences or
counting external inputs. Additional UPI features include: single 5V supply, low power standby mode (in the 8041A),
single-s~ep mode for debug (in the 8741A), and dual working register banks.
'
Because it's a complete microcomputer, the UPI provides more flexibility for the designer than conventional LSI inter·
face devices. It is designed to be an efficient controller as well as an arithmetic processor. Applications include keyboard scanning, printer control, display multiplexing and similar functions which involve interfacing peripheral
devices to microprocessor systems.
PIN CONFIGURATION
BLOCK DIAGRAM
Vee
l ..,,. --
:;'~,=*--k=::::===::::
....
...MfEll
InnM
,,~
.-
INTERFACE
,...
.....
--
V. . -......_ _:J"
__
{ '~-_I'IIOIIPIIDGtIMI
~
I~ .."._
..-I
'"
. ."",Y
' " _ _ +SIUI'PL'f
'.--0_'
Intel Corporation Assumes No Responaibilty for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses Bfa Implied.
@INTElCORPORATION, 1982
6-'177
I
MARCH 1982
intJ
8041 AJ8641 AJ8741 A
", Table
Signal
00-0 7
(BUS)
,
"
"
.
1. -Pin Description
Signal
Description
P10-P17 8"bit. PORT 1 quasi-bidirectional I/O lines.
SYNC
Output signal wllich occur" once per ~UPI41 A instruction cycle. SYNC can be used as a,
strobe for external circuitry; it is also used to
synchronize sirigle step operation.
EA
External access input which allows emulation. testing and PROM/ROM verification.
PROG
Multifunction pin used as the program pllise
input during PROM programming.
During I/O expander access the PROG pin
acts as an address/data strobe to thl' 824,3.
RESET
Inp'ut used to reset IStatus flip-flops and to set
the program counter to zero.
I/O write inp,ut which enables the master CPU
to write data and command words to the UPI41A INPUT DATA BUS BUFFER.
iID
I/O read Input which enables the master CPU
to read data- and status words from the OUTPUT DATA BUS BUFFER or status register.
CS
Chip select input used to select one UPI-41 A
,out of several connected to a common data
bus.
Ao
Address input used by the master processor
to indicate whether byte transfer is data or
command. During a write operation flag F1 is
set to the status of the Ao input.
Description
XTAL1 •. Inputs for a,. crystal; L,C 9r a':l external timing,
XTAL2
sillnal ~o, llet\'lr(l1ine the ,internal oscillator
frequency.' "
,
'
Three-state. bidirectional D.ATA BUS BUFFER lines used to interface the UPI-41 A to an
8-bit master system data bus.
P20-P27 8-bit. PORT' 2 quasi-bidirectional VO lines.
The lower 4 bits (P20-P23) interface directly
to the 8243 I/O expander device and contain
address and data information during PORT
4-7 access. The upper 4 bits (P24-P27) can
be programmed to provide Interrupt Request
and DMA Handshake capability. Software
control can configure P24 as OBF (Output
Buffer'Full). P25 as iBF (Input Buffer FU~
as ORO (DMA Request). and P27 as
,
(DMA ACKnowledge):
WR
,
RESET is also used during PROM programming and verification.
RESETshouid beheld lowforaminimumof8
i'nstruction cycles after power-up.
TEST O. Input pins which can be directly tested using
TEST 1 conditional, branch instructions.
T 1 also functions as the event timer input
(under software control). To is used during
PROM programming and verification in the
8741A.
SS
Single stl'lP input used in the 8741 A in con-,
junction with the SYNC output to step the
program through each instruction.
Vee
+SV main power supply \lin.
Voo
+5V during normal operation. +25V during
programming operation. Low power standby
pin In ROM version.
VSS
Clrpult ground potential. '
"
6-778
, AFN-OOl88B
8041 AJ8641AJ8741 A
PROGRAMMING, VERIFYING, AND
ERASING THE 8741A EPROM
6.
Data appl ied to BUS
S.
V DD ~ 25v (programm ing power)
9.
PROG = Ov followed by one 50ms pulse to 23V
10.
V DD =5v
Programming Verification
In brief, the programming process consists of: activating
the program mode, applying an' address, latching the
address, applying data, and applying a programming pulse.
Each word is programmed completely before moving on to
the next and is followed by a verification step. The follow·
ing is a list of the pins used for programming and a descrip·
tion of their functions:
Pin
Function
XTAL 1
Clbck Input (1 to 6MHz)
Reset
Test 0
EA
Initialization and Address Latching
BUS
P20-1
VDD
PROG
Selection of Program or Verify Mode
Activation of Program/Verify Modes
Address and Data Input
Data Output During Verify
Address Input
Programming Power Supply
Program Pulse Input
WARNING:
An attempt to program a mlssocketed 8741 A will result In severe
damage 10 the part. An indication of a property socketed pan is t~e
appearance of the SYNC clock output. The lack of thIS clock may
RESET = 5v (latch addressl
7.
a = 5v (verify model
11.
TEST
12.
Read and verify data on SUS
13.
TEST
14.
RESET
15.
Programmer should be at conditions of step 1 when
8741A IS removed ,from socket.
a = Ov
= Ov and repeat from step 5
8741A Erasure Characteristics
The erasure characteristics of the 8741A are such that
erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Ang·
stroms (A). It should be noted that sunlight and certain
types of fluorescent lamps have wavelengths in, the
3000-4000A range. Data show that constant exposure to
room level fluorescent lighting could erase the typical
8741A in approximately 3 years while it would take approximately one week to cause erasure when exposed
to direct sunlight. If the 8741A is to be exposed to these
types of lighting conditions for extended periods of
time, opaque labels are available from Intel which
should be placed over the 8741A window to prevent
unintentional erasure.
be used to disable the programmer.
The recommended erasure procedure for the 8741 A is
exposure to shortwave ultraviolet light which has a
wavelength of 2537 A. The integrated dose (i.e., UV intensity x exposure time) for erasure should be a minimum
of 15 w·seclcm 2. The erasure time with this dosage is
approximately 15 to 20 minutes using an ultraviolet
lamp with a 12,000 ,..Wlcm 2 power rating. The 8741A
should be placed within one inch of the lamp tubes during erasure. Some lamps have a filter on their tubes
which should be removed before erasure.
The Program/Verify sequence is:
1.
AO= OV. CS = 5V. EA = 5V, RESET = OV, TESTa = 5V,
Voo = 5V , clock applied or Internal oscillator operating,
BUS and PROG floatln9.
2.
Insert 8741A In programming socket
3.
TEST 0 = Ov (select program
4.
EA = 23V (activate program model
5.
Address appl ied to BUS and P20-1
mo~el
6-779
AFN-00188B
inter
8041~8841~8741A
UPI·41ATII FEATURES AND
ENHANCEMENTS
1. Two Data Bus Buffers, one for Input and one for out·
-put. This allows a much cleaner Master!Slave pro\
tocol.
INTERNAL
DATA BUS
Do-Dr
<=If
'
If "EN FLAGS" has been executed, P2!I becomes the
i'B'f!' (Input Buffer Full) pin. A "1" written to P25
ena~les the i'B'f!' pin (the pin outputs the Inverse of the
IBF Status Bit). A "0" written to P25 disables the IIi'F
pin (the pin remalnslow).lThls:pin can 'be used to
indDcate that the UPI-41A Is ready for data.
•
INPUT
DATA
BUS
BUFFER
(8)
L.-..--..-I
08F PNTERRUPT REQUEST)
OUTPUT
DATA
BUS
BUFFER
ill' (INTERRUPT REQUES1l,
(8)
DATA BUS BUFFER INTERRUPT CAPABILITY
2. 8 Bits of Status
EN FLAGS
Op Codo: OFIM
01
ST• .,ST7 are user definable status bits. These bits are
defined by the "MOV STS, A" single byte, single
cycle instruction. Bits 4-7 of the accumulator are
moved to bits 4-7 of the status register. Bits 0-3 of
the status register are not affected.
MOV STS. A Op Cod.: 90H
3. RD and WR are edge triggered. IBF, OBF, Fl and INT
change internally after the trailing,edge of AD or WR.
FLAGS AFFECTED
lID or WR
4. P24 and P25 are port pins or Buffer Flag pins which
can be used to interrupt a master proces~or. These
pins default to port pins On Reset.
If the "EN FLAGS" Instruction has been executed,
P24 becomes the OBF (Output Buffer Full) pin. A "1"
written to P24 enables the OBF pin (the pin outputs
the OBF Status Bit). A "0" written to P24 disables the
OBF pin (the pin remains low). This pin can be used
to indicate that valid data is available from the UPI·
41A (in Output Data Bus Buffer).
6-780
5. P26 and P27 are port pins or DMA handshake pins for
use with a DMA controller. These pins default to port
pins on Reset.
If the "EN DMA" instruction has been executed, P26
becomes the DRQ (DMA ReQuest) pin. A "1" written
to P26 causes a DMA request (DRQ is activated). DRQ
Is deactivated by DACK . RD, DACK :WR, or execution
of the "EN DMA" Instruction.
If "EN DMA" has been executed, P27 becomes the
DACK (DMA ACKnowledge) pin. This pin acts as a
chip select Input for the Data Bus Buffer registers
during DMA transfers.
8041A1
8741A
DROI!!!:
DROn
DACKr!!!:
DACK
8257
DMA HANDSHAKE CAPABIUTY
EN DMA
Op CoM: OES"
_1888
8041 AJ8641 AJ8741 A
APPLICATIONS
DATA
D
~
m
8OI5A
ADDR
-TO
CONTROL
.
8041A1
CS 87.1A
~
~
Ao
I-To
DBB
-T1
RD
AD
WR
Wli
....
0
8048
-T1
PORT
CONTROL
2
BUS
DATA BUS
8
a
Figure 2. 8048-8041A Int.rface
Figure 1. 808SA-8041A Interface
KEYBOARD
MATRIX
8243
EXPANDER
8041A18741A
DATA BUS
DATA BUS
CONTROL BUS
CONTROL BUS
Figure 4. 8041A Matrix Printer Interface
Figure 3. 8041A-8243 Keyboad Scanner
6-781
AFN-00188B
8041 Al8641 Al8741 A
ABSOLUTE MAXIMUM RATINGS·
'COMMENT: Stresses above those listed under "Absolute Maximum
Ratings" may causs permanent damage to the devloe:This Is a stress
rating only and functional operation of the device at these or any other
pondltlons above, those Indicated i~ ,the operational sections of this
specification Is not Implied. Exposure to absolute maximum rating con·
,dltion. for extended periods may affect device reliability,
Ambient Temperature Under Bias ......... O·C to 70·C
Storage Temperature ............. - 65'·Cto + 150·C
Voltage on Any Pin With Respect
to Ground .......................... 0.5V to + 7V
Power Dissipation ..... , ................... 1.5 Waft
D.C. AND OPERATING, CHARACTERISTICS
TA=O°C to 70°C, VSS=OV, VCC=Voo=+5V ±10%'
Symbol
Parameter
Min.
Max.
Unit
-0.5
VILt
V IH
Input Low Voltage (Except XTAL 1, XTAL2, RESET)
Input Low Voltage (XTAL1, XTAL2, RESET)
Input High Voltage (Except XTAL 1, XTAL2, RESEn
-0.5
0.8
0.6
V
V
2.2
Vce
V IH1
Input High Voltage (XTAL1, XTAL2, RESET)
3.8
VOL
Output Low Voltage (0 0-0 7)
Vce
0.45
VOlt
VOL2
VOH
Output Low Voltage (Pl0PH' P20 P27 , Sync)
Output Low Voltage (Prog)
Output High Voltage (0 0-0 7)
Output High Voltage (All Other Outputs)
VIL
VOH1
0.45
0.45
loz
III
ILil
IDD
Ice+ 100
V
V
V
IOL=2.0 mA
10L= 1.6 mA
V
10L= 1.0 mA
2.4
V
10H = - ,400 p.A
2.4
V
IOH= -50p.A
± 10
I'A
± 10
Vss s VIN s Vee
Vss + 0.45 s VIN s Vee
VIL = 0.8V
VIL =0.8V
Input Leakage Current (To, T 1, RD, WR, CS, A o, EA)
Output Leakage Current (0 0-0 7, High Z State) ,
IlL
Test Conditions
Low Input Load Current (Pl0PH, P20 P27 )
Low Input Load Current (RESET, SS)
0.2
I'A
rnA
mA
Voo Supply Current
Total Supply Current
15
mA
Typical = 5 mA
125
mA
Typical = 60 mA
0.5
A.C. CHARACTERISTICS
TA=O°C to 70°C, VSS=OV, VCC=Voo=+5V ±10%'
DBB ijEAD
Symbol
tAR
tRA
tRR
tAO
t RO
Max.
0
0
RD Pulse Width
' CS, Ao to Data Out Delay
RDI to Data Out Delay
Frn f
tCY
Cycle Time (Except 8741A·8)
Cycle Time (8741A·8)
2.5
4.17
Test Conditions
ns
225
225
to Data Float Delay
Unit
ns
ns
250
tOF
tCY
Min.
Parameter
CS, Ao Setup to RDI
CS, Ao Hold After JIDf
ns,
ns
100
ns
15
15
I'S
I's
Max.
Unit
C L =150pF
C L=150pF
6.0 MHz XTAL
3.6 MHz XTAL
DBB WRITE
Symbol
Min.
0;
Parameter
0
ns
ns
WFi Pulse Width
250
ns
tow
Data Setup to WAf
150
ns
two
Data Hold AfterWAf
0
ns
tAW
tWA
, tww
CS, Ao Setup to WRI
CS, Ao Hold AfterWFif
6-782
Test Conditions
AFN-OOI88B
inter
8041 AJ8841 AJ8741 A
A.C. TIMING SPECIFICATION FOR PROGRAMMING
TA=O·Ctb 7'O·C. VCC=+5V :1:10%·
Symbol
Min.
Parameter
tAW
Address Setup Time to RESET 1
4tcy
tWA
Address Hold Time After RESET 1
4tcy
tow
Data
two
Data in Hold Time After PROG I
4tcy
tpH
RESET Hold Time to Verify'
Voo Setup Time to PROG I
.
4tcy
tvoow
tv DOH
tpw
Voo Hold Time After PROG I
0
Program PU'lse Width
50
tTW
Test 0 Setup Time for Program Mode
4tcy
4tcy
1ft
Setup Time to PROG 1
Unit
60
mS
Telt Cl)ndltlonl
4tcy
4icy
twT
Test 0 Hold Time After Program Mode
too
Test 0 to Dala Out Delay
tww
RE"SET Pulse Width to Latch Address
tr. If
Ma••
4tcy
4tcy
. Voo and PROG Rise and Fall Times
05
ICY
CPU Operation Cycle Time
5.0
tRE
RESET SetuR Jlme Before EA I.
4tcy
20
"s
"s
NOI.: If TEST 0 Is high. too can be triggered by REsET I .
• For Extended Temperature EXPRESS; use M8741A electrical parametars.
D.C. SPECIFICATION FOR PROGRAMMING
TA = 25·C :!:: 5·C, Vcc = 5V :!:: 5%, Voo = 25V :!::
Symbol
tv
Parameter
Min.
Max.
Unit
24.0
260
V
Voo Voltage Low Level
4.75
5.25
V
PROG Program Voltage High Level
21.5
24.5
V
0.2
V
21.5
24.5
V
VOOH
Voo Program Voltage High
VOOl
VPH
Leve~
VPl
PROG VOltage Low Level
VEAH
EA Program or Verify Voltage High Level
VEAL
EA Voltage Low Level
5.25
V
100
Voo High Voltage Supply Current
30.0
rnA
IpROG
PROG High Voltage Supply Current
16.0
mA
lEA
EA High Voltage Supply Current
.
,
,
mA
1.0
,
Te.t Condition.
'"
A.C. CHARACTERISTICS-PORT 2
TA=O·C to 70·C,: Vcc= +5V :!:: 10%"
Symbol
..
Min.
Parameter
tcp
Port Control Setup Before Falling
Edge of PROG
110
tpc
Port Control Hold After Falling
Edge of PI'IOG·
100
tpR
PROG to Time P2 Input Must Be Valid
tpF
top
Input Data Hold Time
tpo
Output Data Setup Time
Output Data Hold Time
tpp
PROG Pulse Width
0
6-783
MM.
Unit
TestCondltlonl
' ns
ns
810
ns
150
n~
250
65
ns
ns
12Dq
ns
..
AfN.OO1888
inter
8041A18~:1~8741A
A C CHARACTERISTICS-DMA
Symbol
',"
,
Min.
Parameter
Max.
Unit
ns
tAce
' P!,\CK to WR or RD
0
tCAC
A!l or ~ to r5AOR
0
tACO
DACK to Data Valid
22~
ns
tCRa
RD or WR to ORO Cleared
200
ns
SOCKET, STRAy)
r-r:1
I
ns
C L =,150 pF
DRIVING FROM EXTERNAL SOURCE
CRYSTAL OSCILLATOR MODE
".""~;;:~
Test Conditions
+5V
4700
m"
»--t------''''1XTAL1
+5V
I
L_____
3
XTAL2
470Q
I
15-25 pF
(INCLUDES SOCKET,
STRAY)
'---+-----=-iXTAL2
-:;-
CRYSTAL SERIES RESISTANCE SHOULD B~
<752 AT 6 MHz; <180Q AT 3.-6 MHz.
BOTH XTAL1 AND XTAL2 SHOULD BE DRIVEN
RESISTORS TO Vee ARE NEEDED TO ENSURE VIH
= 3.8V
IF TTL CIRCUITRY IS USED,
LC OSCILLATOR MODE
l
45",H
120",H
..Q..
20pF
20pF
NOMINAL I
t '" 2nJLC'
5.2 MHz
3,2 MHz
Jc ~L
"':" T
2
XTAL1
C'= C+3Cpp
2
C
3
XTAL2
Cpp ~ 5 -10 pF PIN,TO,PIN
CAPACITANCE
E,ACH C SHOU~D BE APPROXIMATELY 20 pF, INCLUDING STRAY CAPACITANCE,
TYPICAL 8041/8741 A CURRENT
A;C TESTING LOAD,CIRCUIT
80 rnA
60mA
DEVICE
UNDER
40mA
TEST
n , C L : 1 5 0 PF
,1
20 rnA
-=
'TEMP (I'e)
6-784
AFN-00188B
/
intJ
8041AJ8841AJ8741 A
WAVEFORMS
READ OPERATION-DATA BUS BUFFER REGISTER.
ISYSTEM'S
BOR Aa
~-------
ADDRESS BUS)
1----'00----1
fREAD CONTROLI
-'00-1
~OF
----1"0-
?:UTT~~~~-----------C< -
DATAVALlD)'>-----------
WRITE OPERATION-DATA BUS BUFFER REGISTER.
eJOR ~
A_
=>1_______
----'1r~
_
__
-:--ISVSTE
...SBUS)
ADDRESS
-'AW-J"------r-fw_W-~4--'WA~_ _
L_
-'ow--
DATA
aus
DATA
,
~
flNPUTI_ _ _ _ _
MA_V_C_H_AN_G_'_ _ _.:J/'
-fwo
_OATAVAlID_'"
1c!\~
PORT 2 TIMING
SYNC
EXPANDER
PORT
OUTPUT
PORT 20~3 DATA
EXPANDER
PORT
INPUT
PCAT 20_3 DATA
-PAoe
6-785
DATA
_____MA_V_C.;.HA....;NG.;.,;....
_ _ __
IWRITECONTROLI
inter
8041 AJ8641AJ8741 A
WAVEFORMS FOR PROGRAMMING
COMBINATION PROGRAMNERIFY MODE (EPROM'S ONLY}
.A
'23Y
5V
/
_ _ _ _ _J
1 - - - - - - - - - - PROGRAM
~---------t-~-
'_'+I'~--_ PROGRAM - - - -
VERIFY
,-------"
TESTO
OBo-OB,
==>---
DATA TO BE
PROGRAMMED VALID
--
-<
NEXT AODR
VAllO
NEXT
LAST
ADDRESS
_
C
ADDRESS
",'.~_~W_T
+23------- --_=fY-UDW
':
.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
two
PROG
,
:~-----------
___ J
r- .....--------'"'\..._______
VERIFY MODE (ROM/EPROM}
'ww
V
RESET
DBO-DB7
P20-P ,
=>---
II
~
tWA
J--'"
ADDRESS
(0-7) VALID
--
DATA OUT
VALID
ADDRESS (8-9) VALID
NEXT
ADDRESS
NEXT DATA
OUT VALID
NEXT ADDRESS VALID
------\
NOTES:
1. PROG MUST FLOAT IF EA IS LOW (I•••• *23V), OR IF ro_5V FOR THE 8741A. FOR THE
8041A PROG MUST ALWAYS FLOAT.
2. XTAL 1 AND XTAL 2 DRIVEN BY 3.8 MHz CLOCK WILL GIVE 4.17 's.c ICY. THIS IS ACCEPT·
ABLE FOR 8741A·8 PARTS AS WELL AS STANDARD PARTS.
3. AO MUST BE HELD LOW (I••••• OV) DURING PROGRAMIVERIFY MODES.
The 8741A EPROM can be programmed by either of two
Intel products:
1. PROMPT-48 Microcomputer Design Aid, or
2. Universal PROM Programmer (UPP series) peripheral
of the Intellec'" Development System with a UPP-848
Personality Card.
6-786
AFN.ool88B
8041 AJ8841 AJ8741 A
WAVEFORMS-DMA
i!ACK
AD
- 'AI:~CAC-
WII
-tAce
,.=---:CAC-
DATA IUS
VALID
VALID
I---'ACD-
DRO
-------- -
-,cJ-
-tcJ-
INPUT AND OUTPUT WAVEFORMS FOR A.C. TESTS
2.4
----""\X2.2
....... TEST POINTS
......2
.2V
0.8. --...0.8"",,_____
0.45 _ _ _ _oJ_ _
Cl=l50pF
Table 2. UPI™ Instruction Set
Mnemonic
Accumulator
ADD A,Rr
ADD A,@Rr
ADD A,#data
AD DC A,Rr
AD DC A,@Rr
ADDCA,
#data
ANL A,Rr
ANL A,@Rr
ANL A,#data
ORL A,Rr
ORL A,@Rr
ORL A,#data
XRL A,Rr
,
Description
Add register to A
Add data memory to A
Add immediate to A
Add register to A with
carry
Add data memory to A
with carry
Add immed. to A with
carry
AND register to A
AND data memory to A
AND immediate to A
OR register to A
OR data memory to A
OR immediate to A
Exclusive OR register
to A
Mnemonic
Bytes Cycles
XRL A,@Rr
1
1
2
1
1
1
2
1
1
1
2
2
1
1
2
1
1
2
1
1
1
2
1
1
2
1
XRL A,#data
INCA
DEC A
CLR A
CPLA
DAA
SWAP A
RL A
RCL A
RRA
RRCA
6-787
Description
Exclusive OR data
memory to A
Exclusive OR immediate to A
Increment A
Decrement A
Clear A
Complement A
Decimal Adjust A
Swap nibbles of A
Rotate A left
Rotate A left through
carry
Rotate A right
Rotate A right through
carry
Bytes Cycles
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
AFN-OOl88B
8041AJ8641AJ8741 A
Table 2., UPI™ Instruction Set (Cont'd.)
Mnemonic
Description
Input/Output
In A,Pp
OUTL Pp,A
ANL Pp,#data
ORL Pp,#data
In A,DBB
OUTDBB,A
.MOV STS,A
MOVD A,Pp
MOVD Pp,A
ANLD Pp,A
ORLD Pp,A
Data Moves
MOVA,Rr
MOVA,@Rr
,
MOVA,#data
MOV Rr,A
MOV@Rr,A
MOV Rr,#data
MOV@Rr,
#data
MOVA,PSW
MOV PSW.A
XCH A,Rr
XCH A,@Rr
XCHD A,@Rr
MOVPA,@A
MOVP3, A,@A
Timer/Counter
MOVA,T
MOV T,A
STRT T
STRT CNT
STOP TCNT
EN TCNTI
DIS TCNTI
Input port to A
Output A to port
AND immediate to port
OR immediate to port
Input DBB to A,
clear IBF
Output A to DBB,
set OBF
A4-A7 to Bits 4-7
of Status
Input Expander port
to A
Output A to Expander
port
AND A to Expander
OR A to Expander
port
Move register to A
Move data memory
to A
Move'immediate to A
Move A to register
Move A to data
memory
Move immediate to
register
Move immediate to
data memory
Move PSW to A
Move A to PSW
Exchange A and
register
Exchange A and data
memory
Exchange digit of A
and register
Move to A from
current page
Move to A from
page 3
Read Timer/Counter
Load Timer/Counter
Start Timer
Start Counter
Stop Timer/Counter
Enable Timer/Counter
Disable Timerl
Counter Interrupt
Bytes ICycles
1
1
Mnemonic
Control
ENDMA
2
2
2
2
1
EN I
DIS I
EN FLAGS
1
1
SEL RBO
1
1
SEL RB1
1
2
NOP
1
2
1
1
2
2
Registers
INCRr
INC@Rr
2
2
1
1
1
1
1
2
2
1
1
1
1
2
2
2
2
l'
1
1
1
DEC Rr
Subroutine
CALLaddr
RET
!;IETR
Flags
CLRC
CPLC
CLR FO
CPL FO
CLR F1
CPL F1
Branch
JMP addr
JMPP@A
DJNZ Rr,addr
1
1
1
1
1
1
1
·2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
JC addr
JNC addr
JZ addr
JNZ addr
JTO addr
JNTO addr
JT1 addr
JNT1 addr
JFO addr
JF1 addr
JTF addr
1
JN1BF addr
JOBF addr
JBb addr
,6-788
Description
Enable DMA Handshake Lines
Enable IBF Interrupt
Disable IBF Interrupt
Enable Master
Interrupts
Select register
bank 0
Select register
bank 1
No Operation
Bytes Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Jump to subroutine
Return
Return and restore
status
2
1
1
2
2
2
Clear Carry
Complement Carry
Clear Flag 0
Complement Flag 0
Clear F1 Flag
Complement F1 Flag
1
1
1
1
1
1
1
1
1
1
'1
1
Jump unconditional
Jump indirect
Decrement register
and jump
Jump on Carry=1
Jump on Carry=O
Jump on A Zero
Jump on A not Zero
Jump on TO=1
Jump on TO=O.
Jump on T1=1
Jump on T1=0
Jump on FO Flag=1
Jump on F1 Flag",,1
Jump on Timer
Flag=1, Clear Flag
Jump on IBF Flag=O
Jump on OBF Flag.=1
Jump on Accumulator
Bit
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Increment register
Increment data
memory
Decrement register
1
,
inter
8042/8742
UNIVERSAL PERIPHERAL INTERFACE
8·BIT MICROCOM'PUTER
• 8042/8742: 12 MHz
• Pin, Software and Architecturally
Compatible with 8041A18741A
• 8·Blt CPU plus ROM, RAM, 1/0, Timer
and Clock In. a Single Package
• 2048 x 8 ROMIEPROM, 128 x 8 RAM,
8·Blt TlmerlCounter, 18 Programmable
110 Pins
• One 8·Blt Status and Two Data
Registers for Asynchronous
Slave·to·Master Interface
• DMA, Interrupt, or Polled Operation
Supported
• Fully Compatible with all Intel and
Most Other Microprocessor
Families
• Interchangeable ROM and EPROM
Versions
• Expandable 110
• RAM Power· Down Capability
• Over 90 Instructions: 70% Single Byte
• Available in EXPRESS
-Standard Temperature Range
The Intel 804218742 is a general-purpose Universal Peripheral Interface that allows the designer to grow his own
customized solution for peripheral device control. It contains a low·cost microcomputer with 2K of program memory,
128 bytes of data memory, 8·blt CPU, 110 ports, 8-bit timer/couJlter, and clock generator in a single 40-pin package.
Interface registers are included to enable the UPI device to function as a peripheral controller in the MCS-48™,
MCS·51™, MCS-80™, MCS-85™, iAPX-88, iAPX-86 and other 8-, 1S·bit systems.
The 804218742 is software, pin, and architecturally compatible wit-h the 8041 A, 8741 A. The 804218742 doubles the on-chip
mernory space to allow for additional features and performance to be incorporated in upgraded8041 N8741 A designs. For
new designs, the additional memory and performance of the 8042/8742 extends the UPI concept to more complex motor
control tasks, 80-column printe~s and process control applications as examples.
To allow full user flexibility, the program memory is available as ROM in the 8042 version or as UV·erasable EPROM in
the 8742 verSion. The 8742 and the 8042 are fully pin compatible for easy transition from prototype to production level
designs.
PfIIl'HIIIIIL
IHlEllf'ACE
'1 _ _
{
_1I"'ce
__
HlOQMIIIIU",L~
+f~l'
Figure 2. Pin Configuration
• • _ _ OIlOUND
Figure 1. Block Diagram
Intel Corporation Assumes No Responslbtlty for the Use at Any Circuitry Other Than Circuitry Embod/ed In an Intel Product No Otther Circuit Patent Licenses .,. ImPlied,'
©INTEL CO~PORATION, 1983
-
6-789
FEBRUARY 1883
ORDER NUMBER: 210393-001
804218742
Symbol
Pin
No.
TESTO.
TEST 1
1
39
'TYpe
Name and FuncUon
I
Test inputs: Input plfls which can be
directly tested using conditional
branch instructions.
Frequency Reference: TEST 1 (T 1)
alSO functiona as the 'event timer input (under software control). TEST 0
(To) Is used during PROM programming and verification in the 8742.
XTAL 1.
XTAL2
2
3
I
Inputs: Inputs for a crystal. LC or an
external timing signal to determine
the internal' oscillator frequency.
RESET
4
I
Reset: Input used to reset status flipflops and to set the program counter
to zero.
Symbol
Pin
No.
Type
SYNC
11
0
Output 'Clock: Output signal which
occurs once per UPI-42 Instru,ction
cycle. SYNC can be used as ~ strobe
for external circuitry; it Is also used to
,synchronize single step operation.
00-07
12-19
I/O
Data Bua:, Thr\l&state. bidirectional
DATA BUS BUt=FER lines used to In·
terlace the UPI-42 microcomputer to
an 8-blt ,master system, data bus.
P1o-P17
27-34
I/O
Pori 1: 8-bit. PORT 1 quasi-bidirectional I/O lines.
P2O -P27
21-24
35-38
I/O
Pori 2: 8-bit. PORT 2 quasl-bidirectional I/O lines. The lower 4 bits (P20P23) interface directly to the 8243,j/0
expander device and contain' address
and data information during PORT 4-7
access. The upper 4 /:;Iits (P2.-P27 ) ,can
be programmed to provide interrupt
Request and DMA Handshake capability, Software control can configure
P2• as Output Buffer Full (OBF) interrupt •. P2• as Input Buffer Full (IBF)
interrupt. P26 as DMA Request
(ORO). and P27 as DMA ACKnowledge
(DACK).
PROG
25
I/O
Program: Multifunction pin used as
the program pulse input during
PROM programming.
(BUS)
RESET is also used during PROM programming and verification.
SS
5
I
Single Step: Single step input used
in conjunction with the SYNC out·
put to step the program through
each instruction. (8742 only)
CS
6
I
Chip SlIIect: Chip select input used to
select one UPI microcomputer out of
several connected to a common data
bus.
EA
7
I
External Acces.: External access
input which allows emulation. testing
and PROM/ROM verification. This
pin should be tied low if unused.
RD
8
I
Read: I/O fead inpllt which enables
the master CPU to read data and
status words from the OUTPUT DATA
BUS BUFFER or status register.
Ao
9
I
Command/Data Select: Address Input
used by the master processor to in·
dicate whether byte transfer is data
(Ao=O. F1 is reset) or command
(Ao= 1. F1 is· set).
WR
10
I
Write: 110 write Input which enables
the master CPU to write data and
command' words to the UPI INPUT
DATA BUS BUFFER.
Name and Function
During I/O expander access the PROG
pin acts as an address/data strobe to
the 8243. This pin should be tied high
if unused.
Vcc
40
Power: +5V main power supply pin.
Voo
26
Power: + 5V during normal opera·
tion. + 21V during programming
operation. Low power standby pin in
ROM version.
Vss
20
Ground: Circuit ground potential.
6-790
AFfoI.Ol832A
.
'
inter
804218742
UPI·42 FEATURES
pin (the pin remains low). This pin can be used to
Indicate that the UPI-42 Is ready for data.
1. Two Data Bus Buffers, one for input and one for out·
put This allows a much cleaner Master/Slave pro·
tocol.
00-07
dF
OBF (INTERRUPT REOUEsn
INTERNAL
DATA BUS
INPUT
DATA
BUS
BUFFER
(8)
I"Bf (INTERRUPT
dJ
REQUEST)
DATA BUS BUFFER INTERRUPT CAPABILITY
1..---.
OUTPUT
DATA
BUS
BUFFER
EN FLAGS
Op Cod.: OFSH
I ' I ' I ' I '. I I ' I I ' I
(8)
0
0
2. 8 Bits of Status
I~I~I~I~
~
~
~
~
~
~
~ ~I
~
~
~
5. P26 and P27 are port pins or DMA handshake pins for
use with a DMA controller. These pins default to port
pins on Reset.
~
If the "EN DMA" instruction has been executed, P26
becomes the ORO (DMA ReOuest) pin. A "1" written
to P26 causes a DMA request (ORO is activated). ORO
is deactivated by DACK· RD, DACK 'WR, or execution
of the "EN OM A" instruction.
ST 4-ST 7 are user definable status bits. These bits are
defined by the "MOV STS, A" single byte, single
cycle instruction. Bits 4-7 of the accumulator are
moved to bits 4-7 of the status register. Bits 0-3 of
the status register are not affected.
MOV STS, A
If "EN DMA" has been executed, P27 becomes the
DACK (DMA ACKnowledge) pin. This pin acts as a
chip select input for the Data Bus Buffer registers
during DMA transfers.
Op Code 90H
I ' I I ,0 1-,
0
DO
3. RD and WR are edge triggered. IBF, OBF, F, and INT
change internally after the trailing edge of RD or WR.
ORO
P~6
1 - - - - - - , DROn
DACK
P21
IO----Q
8041AHi
8741A
8257
DACK
AD orWR
DMA HANDSHAKE CAPABILITY
During the time that the host CPU is reading the
status register, the 804218742 is prevented from up·
dating this regillter or is 'locked out.'
EN DMA
Op Code: OE5H
I I I I ' I Ii]
1
0
0
0
DO
4. P24 and P25 are port pins or Buffer Flag pins which
can be used to interrupt a master processor. These
pins default to port pins on Reset.
6. The RESET Input en the 804218742.lncludes a2-stage
If the "EN FLAGS" instruction has been executed,
P24 becomes the OBF (Output Buffer Full) pin. A "1"
written to P24 enables the OBF pin (the pin outputs
the OBF Status Bit). A'''O'' written to P24 disables the
OBF pin (the pin remains low). This- pin.can be used
to indicate that valid data is available from the UPI41 A (in Output Data Bus Buffer).
synchronize~
to support reliable reset operation for
12 MHz operation.
7. When .EA is enabled on the 8042/8742, the program
counter is placed on Port 1 and the lower three bits of.
Port 2 (MSB= P22, LSB= P,al. On the 8042/8742 this
information is multiplexed with PORT DATA (see port
timing diagrams at end of this data sheet}.
!!...:EN FLAGS" has been executed, P25 becomes the
ISF (Input Buffer Full) pin. A "1" written to P25
enables the IBF pin (the pin outputs the inverse of the
IBF Status Bit). A "0" written to P25 disables the iBF
6-791
AFN'()1832A
8042/8742
APPLICATIONS
,
8
I
\=!=>ADDR~~~;llj
-TO
CONTROLI-_ _--,n'1
Rlll-"---------- Rll
8048H W R I - - - - - - - - - I W R 8042
TO
PERIPHERAL
BUS K::==:::::::;D1:!Ai!TA~BU!ilSc:==3)81 Daa
--T1
Figure 3. 8088-8042/8742 Interface
P4
PORT 2
P.~~
KEYBOARD
MATRIX
z
P7 ,~
.ij
Figure 4. 8048H·804218742 Interface
~~
P5~~
8243
EXPANDER
TO
PEAIPHERAL
DEVICES
PORT ~==~~~~====(>ICS87U
lCONTROL
AO
DEVICES
~
iii
~l il .-~l ~IH
1
PRQG
~
0:
0-
0
Z
PORT 1
PQRT2
,. z~
~ ~
. lil
..
.."' g ..~J
8 ROWS
w
8042
B742
DBB
DATA BUS
B
CONTROL
M
J
:
l
CONTROL BUS
C - CONTROL BUS
Figure 5. 804218742·8243 Keyboard Scanner
Figure 6. 804218742 80·Column Matrix Printer Interface
PROGRAMMING, VERIFYING, AND
ERASING THE 8742 EPROM
WARNING
An attempt to program a missocketed 8742 will result
In bri~f, the programming pro$'ess consists of: activating
the program mode, applying an address, latching the
address, applying data, and applying a programming pulse.
Each word IS programmed completely before moving on to
the next and IS followed by a venfication step. The follow·
Ing IS a list of the PinS used for programming and a descrip·
tion of their functions:
In
severe
da~age
to the part. An indication of a properly socketed part is the appearance
Programming Verification
of the SYNC clock output. The lack of this clock may be used to disable
the programmer.
The ProgramlVerify sequence is:
1.
=
Ao = OV,. CS = SV.EA SV. RESET =OV. TESTO = SV,
Voo = Sv, clock applied or internal oscillator operating. BUS
floating. PROG = SV.
2.
Insert 8742 in programming socket
Pin
Function
3.
TEST 0 = Ov (select program model
XTAL 1
Clock Input
4.
EA= 18V (active program mode)"
Reset
Initialization and Address Latching
5.
Address applied to BUS andP20-22
Test 0
Selectlpn of Program or Verify Mode
6.
REsET = 5v
EA
Activation of ProgramlVerify Modes
7,
Data applied to BUS"
BUS
Address and Data Input
Data Output Durin.g Verify
8.
Voo = 21V (programming power)"'
9.
PROG
P20-12
Ad.dress Input
10.
VOO
Voo
PROG
Programming Power Supply
11.
TEST 0
(latch addressl
= Vee followed by one SO ms pulse to 18V"
= 5v ..
= 5v (verify model
Program Pulse Input
6-792
AFN-D1832A
804218742
12.
Read and verify data on BUS
13.
TEST 0 nOv
14.
RESET
15.
Programmer should be at conditions of step 1 when
= Ov and
proximately one week to cause erasure when exposed
to direct sunlight. If the 8742 is to be exposed to these
types of lighting conditions for extended periods of
time, opaque labels are available from Intel which
should be placed over the 8742 window to prevent unintentional erasure.
repeat from step 5
8742 i8 removed from socket
'When verifying ROM, EA= l2V.
"Not uled in verifying ROM procedure.
8742 Erasura Characteristics
The erasure characteristics of the 8742 are such that
erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Ang·
stroms (A). It should be noted that sunlight and certain
types of fluorescent lamps have wavelengths in the
30oo-4oooA range. Data show that constant exposure to
room level fluorescent lighting cOl:lld erase the typical
8742 In approximately 3 years while it would take ap-
6-793
The recommended erasure procedure for the 8742 is
exposure to shortwave ultraviolet light which has a
wavelength of 2537 A. The integrated dose (i.e., UV Intensity x exposure time) for erasure should be a minimum
of 15 w-sec/cm 2. The erasure time with this dosage is
approximately 15 to 20 minutes using an ultraviolet
lamp with a 12,000 /lW/cm 2 ,power rating. The 8742
should be placed within one inch of the lamp tubes during erasure. Some lamps have a filter on their tubes
which should be removed before erasure.
AFN-Ol832A
!
804218742
'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage tQ the
devide. This is a stress rating only and funCtional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maxImum
rating conditions for extended periods may affect devIce
reliability.
ABSOLUTE MAXIMUM RATINGS*
\
Ambient Temperature Under Bias ... ' ...... O·C to 70'C
Storage Temperature ............. - 6S'C to + 1S0'C
Voltage on Any Pin With Respect
to Ground ................... . .. -O.SV to + 7V
Power Dissipation ......................... 1.S Watt
D.C. CHARACTERISTICS
(TA
=0
to +700 e: Vee
0
=VDD =+SV ± 10%)
804218742.
Symbol
Parameter
Mln_
Max.
Units Notes
VIL
Input Low Voltage (Except XTAL 1. XTAL2. RESET)
-0.5
0.8
V.
VILl
Input Low,Voltage (XTALl. XTAL2. RESET)
-0.5
0.6
V
VIH
Input High Voltage (Except XTAL 1. XTAL2. RESET)
2.0
VCC
V
3.5
VCC
V
2.2
VCC
V
VIH1
Input High Voltage (XTAL 1. RESET)
VIH2
Input High Voltage (XTAL2)
/
VOL
Output Low Voltage (00-07)
0.45
V
Vall
Output Low Voltage (P1OP17. P20P27. Sync)
0.45
V
10L = 16 mA
VOL2
Output Low Voltage (PROG)
0.45
V
10L = 1.0 mA
V
10H = -400iJ.A
VOH
Output High Voltage (00-07)
2.4
VOH1
Output High Voltage (All Other Outputs)
2.4
IlL
Input Leakage Current (TO. T1. RD. WR. CS. AO. EA)
10FL
Output Leakage Current (00-07, High Z State)
III
Low Input Load Current (P1OP17. 'P20P27)
ILl1
Low Input Load Current
(RESE~
10H = - 50 iJ.A
± 10
SS)
10L = 2.0mA
iJ. A
VSS <:;; VIN <:;; VCC
. VSS + 0.45
<:;; VOUT<:;; VCC
± 10
iJ. A
03
mA
VIL = oav
0.2
mA
VIL = oav
100
VOO Supply Current
20
mA
Typical = 5 mA
ICC+ 100
Total Supply Current
135
mA
TYPical = 60 mA
VIN = VCC
IIH
Input Leakage Current (P1O-P17. P20-P27)
100
iJ. A
CIN
Input Capacitance
10
pF
Cia
1/0 Capacitance
20
pF
D.C. CHARACTERISTICS-PROGRAMMING'(TA=2S'C
Symbol
Parameter
±S'C, Vcc=SV ±S%, Voo=21V ±0.5V
Min.
Max.
Units
VOOH
Voo Program Voltage High Level
20.5
21.S
V
VOOL
VOO Voltage Low Level
4.75
. 5.25
V
VPH
PRO.G Program Voltage High Level
VPL
PROG Voltage Low Level
VEAH
EA Program or Verify Voltage High Level
VEAL
EA Voltage Low Level
100
VOO High Voltage Supply Current
IpROG
PROG High Voltage. Supply Current
lEA
EA High Voltage Supply Current
.
6-794
17.5
18.5
V
Vee-O.S
Vee
V
17.5
18.5
V
5.25
V
30.0
mA
1.0
mA
1.0
mA
Test CO.ndltlons
AFN-Ol832A
804218742
A.C. CHARACTERISTICS
DBBREAD
(TA=O·Oto +70·0, VSS=Ov, VCC=VOO=+5V± 10%)
8042
Symbol
Parameter
tRA
Ao Setup to RD~
OS, Ao Hold After ROt
tRR
RD Pulse Width
tA.O
OS,
tRO
RD~ to Data Out Delay
tOF
Rot to Data Float Delay
tAR
OS,
Min.
8742
Max.
Min.
Max.
Units
0
0
ns
0
0
ns
160
160
Ao to Data Out Delay
ns
130
130
130
130
ns
ns
85
85
ns
Max.
Units
DBBWRITE
Symbol
Parameter
Min.
Max.
Min.
tWA
Ao
OS, Ao
tww
WR Pulse Width
160
160
tow
Data Setup to WRt
130
130
ns
two
Data Hold After WRt
0
0
ns
tAW
OS,
Setup to WR~
0
0
ns
Hold After WRf
0
0
ns
ns
CLOCK
8042
Symbol
Parameter
8742
Min.
Max.
Min.
Max.
Units
tcv
Cycle Time
125
9.20
1.25
9.20
I's[']
tcvc
Clock Period
833
613
83.3
613
ns
tpWH
Clock High Time
33
tpWL
Clock Low Time
33
tR
Clock Rise Ti(lle
10
10
ns
JF
Clock Fall Tim!!
10
10
ns
38
ns
38
ns
NOTE:
1.
tcv = 15/f(XTAL)
6-795
AFN.(]1832A
804218742
A.C. CHARACTERISTICS
(TA=2S·C±S·c. vcc=sv±S%. Voo=21V ±O.SV)
PROGRAMMING
Symbol
Parameter
Min.
Max.
Unit
tAW
Address Setup Time to RESET!
4tCY
tWA
Address Hold Time After RESETt
4tCV
tow
Data in Setup Time to PROGt
4tCY
two
Data in Hold Time After PROG~
4tCY
!PH
RESET Hold Time to Verify
4tCY
tvoow
Voo Setup Time to PROGt
0
1.0
mS
tvOOH
Voo Hold Time After PROGt
0
1.0
mS
tpw
Program Pulse Width
50
60
mS
tTW
Test 0 Setup Time for Program Mode
4tCY
tWT
Test 0 Hold Time After Program Mode
4tCY
too
Test 0 to Data Out Delay
tww
RESET Pulse Width to Latch Address
tr • tf
Voo and PROG Rise and Fall Times
0.5
tCY
CPU Operation Cycle Time
4.0
tRE
RESET Setup Time Before EAt
Test Conditions
4tCY
4tCY
100
/LS
/loS
4tCY
NOTE:
If TEST 0 is high, too can be triggered by RESETt.
A.C. CHARACTERISTICS
DMA
8042
Symbol
Parameter
Min.
8742
Max.
Min.
tACC
DACK 10 WR or RD
0
0
ICAC
RD or WR to DACK
0
0
tACO
DACK to Data Valid
130
tCAQ
RD or WR to ORO Cleared
110
Max.
Units
ns
ns
130
130
ns
nJl1
NOTE:
1. CL 150 pF.
=
A.C. CHARACTERISTICS
PORT 2 (TA=O'Cto +70·C. Vcc= +SV ±10%)
8042/8742 [31
Symbol
Parameter
tcp
Port Control Setup Before Falling Edge of PROG
tpc
Port Control Hold After Falling Edge of PROG
tpR
PROG to Time P2 Input Must Be Valid
tpF
Input Data Hold Time
top,
Output Data Setup Time
tpo
.Output Data Hold Time
tpp
PROG Pulse Width
f(tCY)
Min.
1/15 tCy-28
55
1/10 tCY
125
48/15 tCy-16
0
Max.
Units
ns[l]
650
ns[l]
ns[2]
150
ns[2]
2/10 TCY
250
ns[l]
1/10 tCY-SO
45
ns[2]
6/10 tCY
750
ns
NOTES:
1. CL=80pF.
2. CL=20 pF.
3.
ICY = 1.25 /LS.
6-796
AFN-01832A
8042/8742
A.C. TESTING INPUT, OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
INPUT/OUTPUT
24
-v:: >
TEST POINTS
.~~
DEVICE
UNDER
TEST
< 2.V-
~CL=I50PF
~~
DRIVING FROM EXTERNAL SOURCE-TWO OPTIONS
+5V
>6 MHz
470Q
XTALI
»--+---~-=1 XTAL 1
470Q
XTAL2
'----'--"-1
XTAL'
RISE AND FALL TIMES SHOULD NOT EXCEEO
I. NS. RESISTORS TO VCC ARE NEEDED TO
ENSURE V,H = 3.5V IF TTL CIRCUITRY IS USED.
LC OSCILLATOR MODE
-'-
45.,H
120"H
~
20pF
20 pF
CRYSTAL OSCILLATOR MODE
~~
ricfC ~,
C'
I
I
XTAl1
I :.~3-I:
~ ::----r--::=T
1.;;0 2',)lC'
52 MHz
32 MHz
,
C'= ~+ 3Cpp
XTAU
~HZ
C2
=
I
f--'---'---;:i
XTAL2
C3
-=-
XTAl2
Cpp ;:: 5 - 10 pF PIN TO PIN
CAPAC IT ANCE
EACH C SHOULD BE APPROXIMATEl Y 20 pF INCLUOING STRAY CAPACITANCE
6-797
g~ -m~~~::::t! ~TSfA~) ~
8pF
C3 -. 2o-3OpF INCLUDING STRAY
CRYSTAL SERIES RESISTANCE SHOULD BE LES6 THAN
30Cl AT 12 MHz; LESS THAN 7S0 AT 6 MHZ; LESS THAM
1800 AT 3.1 MHz.
804218742
WAVEFORMS
READ OPERATION-DATA BUS BUFFER REGISTER
tl OR
AO
:=)
K
!SVST£M'S
AD()RESS BUSI
-1011.1'1-
'"
~
\
.0
-'11011.IRUO CONTROLI
--'0'
-"0_--1011.[1--_
WRITE OPERATION-DATA BUS BUFFER REGISTER
~
c,O • •,
=>1
.
r
--------------1 '--________ (SVSTEM'~
; - ... - )
~
t
'i
w.
AOD.ESSBUSI
~_'WA~
,.....------------~fWRITE CONTROLI
-'DW--+ - fWD
DATA
aus
DATA
\.f - O A T A V A l I D _ 1~'\!
DATA
_ _ _........M.,;.;V....;C>i;,;,.,;.;N;;;:G'
;...._ _ __
IINPUTl.....;_ _ _ _
M._y_C_H._NG_'_ _ _.Jf\
CLOCK TIMING
2.4V
XTAL2
1.6V
.45V
---------'-f'-t-"+_
~YC
•
6-798
AFt«Jl1132A
WAVEFORMS (Continued)
COMBINATION PROGRAM/VERIFY MODE (EPROM'S ONLY)
.
EA
/ - - - - - - ; - - - - PROG~AM
trw_
----------1--- VERIFV ------II•.----PROGRAM - - - -
,..------..
TESTO
tww ______
==:>---
tAW
DSO-DS,
+---1-+
twA
DATATOSE
PROGRAMMED VALID
--
-<
NEXT ADDR
VALID
C
LAST
NEXT
ADDRESS
ADDRESS
~------- -- - .~Jjk-~-~- - - - - - "- - - - - - - - ~- - - - - - - - - - - -
.:
VERIFY MOQE (ROM/EPROM)
18V
EA 5V--./
\~_---J/
ADDRESS
10-7) VALID
- - -<,-__A_D_N~_~_:S_s_-.JX'l._~_E_;T_'VD_AA_L~_~-,)-
-
-
-
-
~
-
•
~____J)(,-_____A_D_DR_ES_S_(~_l~_VA_L_ID_ _ _ _-J)('-__~___N_EX_T_A_D_D_RE_SS_V_AL_ID_ _ _ _ _ _ ___
NOTES:
1. PROG MUST FLOAT IF EA IS LOW OR IFTESTO=5V FOR THE 8742, FOR THE 8042
2. Au MUST BE HELD LOW (I •••• OV) DURING PROGMMIVERIFY MODES,
3. TEST 0 MUST BE HELD HIGH.
The 8742 EPROM can be programmed by the following.
Intel product!!:
1. Universal PROM Programmer (UPP 103) peripheral
of the Intellec Development System with a UPP-549
Personality Card.
~ROG
MUST ALWAYS FLOAT.
2. IUp·200/iUP·20l PROM' Programmer with the iUP·
F87/44 Personality Module.
80421874~
WAVEFORMS (Continued)
DMA
.
'-----'
- -
-tcAe
tAce
-
_IACC~CAC,..------,.
,I~
DATA BUS
jK
-
VALID
-IAco~1
I
JJ-
ORO
VALID
-
feR
-
PORT 2
SYNC
EXPANQER
PORT
PORT 20~3 DATA
OUTPUT
EXPANDER
PORT
INPUT
peRT 20.3 DA TA
PAOG
PORT TIMING DUR,ING EA
.sYNC
P1Cl-17
P20-22
I
PORT
DATA
I
\
X
PC
X
PORT
DATA
\
X
PC
ON THE ~ISING EDGE OF,SYNC AND EA IS ENABLED,. PORT. DAyA IS VALID AND CAN I3E.
STROI3ED ON THE TRAILING EDGE OF SYNC THE PROGRAM COUNTER CONTENTS ARE
AVAILABLE
6-800
AFN-Ol832A
intel'
804218742
Table 2. UPI™ InstructIon Set
Mnemonic
Description
ACCUMULATOR
ADD A, Rr
ADD A, @Rr
ADD A, #data
ADDC A, Rr
ADDCA,@Rr
ADDC A, #data
ANL A, Rr
ANL A, @Rr
ANL A, #data
ORLA, Rr
ORLA,@Rr
ORL A, #data
XRL A, Rr
XRLA, @Rr
XRL A, #data
INCA
DECA
CLR A
CPLA
DAA
SWAP A
RLA
RLCA
RRA
RRCA
ORL Pp, #data
INA,DBB
OUTDBB, A
MOV STS, A
MOVDA, Pp
MOVD Pp, A
ANLD Pp, A
ORLD Pp, A
Bytes Cycles
DATA MOVES
Add register to A
Add data memory
to A
Add immediate to A
Add reg ister to A
with carry
Add data memory
to A with carry
Add immediate
to A with carry
AND register to A
AND data memory
to A
AND immediate to A
OR register to A
OR data memory
to A
OR immediate to A
Exclusive OR register to A
Exclusive OR data
memory to A_
Exclusive OR immediate to A
Increment A
Decrement A
Clear A
Complement A
Decimal Adjust A
Swap nibbles of A
Rotate A left
Rotate A left through
carry
Rotate A right
Rotate A right
through carry
1
1
1
1
MOVA, Rr
MOVA,@Rr
2
1
2
1
MOV A, #data
1
1
2
2
1
1
1
1
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
2
1
2
Read Timer/Counter
Load Timer/Counter
Start Timer
start Counter
Stop Timer/Counter
Enable Timer/
Counter Interrupt
Disable Timer/
Counter Interrupt
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Enable DMA Handshake Lines
Enable IBF Interrupt
Disable IBF Interrupt
Enable Master
Interrupts
Select register
bank 0
Select register
bank 1 '
No Operation
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Increment register
I ncrement data
memory
Decrement register
1
1
1
1
1
1
Jump to subroutine
Return
Return and restore
status
2
1
1
2
2
2
1
1
2
2
MOV Rr, #data
1
1
1
1
2
1
1
2
1
1
MOV@Rr,
#data
MOVA, PSW
MOV PSW, A
XCH A, Rr
2
1
2
1
XCHD A, @Rr
1
1
MOVPA,@A
2
2
MOVP3, A, @A
1
1
1
1
1
1
ITIMER/COUNTER
1
1
1
1
1
1
1
1
1
1
1
1
1
XCHA,@Rr'
i
MOVA, T
MOVT,A
STRTT
STRTCNT
STOP TCNT
EN TCNTI
DIS TCNTI
CONTROL
ENDMA
Input port toA
Output A to port
AND immediate to
port
OR immediate to
port
Input DBB to A,
clear IBF
Output A to DBB,
set OBF
A4-A7 to Bits 4-7 of
Status
Input Expander
port to A
Output A to
Expander port
AND A to Expander
port
OR A to Expander
port
1
1
Move register to A
Move data memory
to A
Move immediate
TOA
Move A to register
Move A to data
memory
Move immediate to
register
Move immediate to
data memory
Move PSWto A
Move A to PSW
Exchange A and
register
Exchange A and
data memory
Exchange digit of A
and register
Move to A from
current page
Move to A from
page 3
MOV Rr, A
MOV@Rr,A
INPUT/OUTPUT
IN A, Pp
OUTL Pp, A
ANL Pp, #data
Description
Mnemonic
Bytes Cycles
1
1
2
2
2
2
ENI
DIS I
2
2
EN FLAGS
1
1
SEL RBO
1
1
SEL RB1
1
1
1
2
1
2
1
2
NOP
REGISTERS
INC Rr
INC@Rr
DEC Rr
SUBROUTINE
1
2
CALL addr
RET
RETR
6-801
AFN-01832A
intel'
804218742'
Table 2. UPI™ Instruction Set (Continued)
Mnemonic
Description
Bytes Cycles
FLAGS
CLRC
CPL C
CLR FO
CPL FO
CLR F1
CPL F1
Clear Carry
Complement Carry
Clear Flag 0
Complement Flag 0
Clear F1 Flag
Complement F1 Flag
1
1
1
1
1
1
,1
1
1
1
1
1
Jump unconditional
Jump indirect
Decrement register
and jump
Jump on Carry= 1
Jump on Carry=O
Jump on A Zero
Jump on A not Zero
Jump on TO=1
Jump on TO=O
Jump on T1 =1
Jump on T1=0
Jump on FO Flag=l
Jump on Fl Flag=l
Jump on Timer Flag
= 1, Clear Flag
Jump on IBF Flag
=0
Jump on OBF Flag
=1
Jump on Accumulator Bit
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BRANCH
JMP addr
JMPP@A
DJNZ,Rr, addr
JC addr
JNC addr
JZ addr
JNZ addr
JTO addr
JNTO addr
JT1 addr
JNT1 addr
JFO addr
JF1 addr
JTF addr
JNIBF addr
JOBF addr
JBb addr
1
2
2
2
2
2
2
6-802
AFN·Ol832A
8243
MCS-48® INPUT/OUTPUT EXPANDER
• Low Cost
• Simple Interface to MCS-48@
Microcomputers
• Four 4-81t I/O Ports
• AND and OR Directly to Ports
•
•
•
•
24-Pln DIP
Single 5V Supply
High Output Drive
Direct Extension of Resident 8048 I/O
Ports
The Intel® 8243 is an input/output expander designed specifically to provide a low cost means of I/O
expansion for the MCS-48® family of single chip microcomputers. Fabricated in 5 volts NMOS, the 8243
combines low cost: single supply voltage and high drive current capability.
The 8243 consists of four 4-bit bidirectional static I/O ports and one 4-bit port which serves as an interfaceto
the MCS-48 microcomputers. The 4-bit interface requires that only 4 I/O lines of the 8048 be .used for I/O
expansion, and also allows multiple 8243's to be added to the same bus.
The I/O ports of the 8243 serve as a direct extension of the resident I/O facilities of the MCS-48 microcomputers
and are accessed by their own MOV, ANL, and ORL ins.tructions.
PORT 4
PORT 5
PORT 6
P50
Vee
P40
PSI
1'41
P52
F42
P53
F43
PeO
cs
P61
PROG
P62
P23
Pe3
P22
P73
P21
P72
P20
P71
GND
P70
PORT 7 .
Figure 2. 8243
Pin Configuration
Figure 1. 8243
Block Diagram
Intel CorporatIOn Assumes No Responslbllty for the Use of Any Circuitry Other Than Circuitry Embodied
INTEL CORPORATION. ,980
6-803'
In
an Inlet Product No Other CirCUIt Patent Licenses are Implied
AFN-00214A.Q,
8243
Table 1. Pin Description
Symbol Pin No.
PROG
7
Clock Input. A high to low transition on PROG signifies that address and control are available on
P20-P23, and a low to high transition signifies that data is available
on P20-P23.
CS
6
Chip Select Input. A high on CS
inhibits any change of output or
internal status.
P20-P23
GND
11-8
12
P40-P43
2-5
P50-P53 1, 23-21
P60-P63 20-17
P70-P73 13-16
I
VCC
24
Power On InHlalization
Initial application of power to the device forces
i!1Put/output ports 4, 5, 6, and 7 to the tri-state and
port 2 to the input mode. The PROG pin may be
either high or low when power is applied, The first
high to low transition of PROG causes device to
exit power on mode. The power on sequence is
initiated if vee drops below lV.
.
. Function
P21 P20
Four (4) bit bi-directional port contains the~ddress and control bits
on a high to low transition of
PROG. During a low to high transition contains the data for a selected output port if a write operation, or the data from a selected
port before the low to high transition if a read operation.
0
0
Address
Code
0
1
0
1
Port
Port
Port
Port
4
5
6
7
P23 P22
0
0
1
l'
0
1
0
1
Instruction
Code
Read,
Write
ORlD
ANlD
Write Modes
o volt supply.
The device has three write modes. MOVD Pi, A directly writes new data into the selected port and old
data is lost. ORlD Pi, A takes new data, OR's it with
the old data and then writes it to the port. ANlD Pi, A
takes new data, AND's it with the old data and then
writes it to the port. Operation code and port address are latched from the input port 2 on the high
to low transition of the PROG pin. On the low to high
transition of PROG data on port 2 is transferred to
the logic block of the specified output port.
.
After the logic manipulation is performed, the data
is latched and outputed. The old data remains
latched until new valid outputs are entered.
Four (4) bit bl-directionall/O ports.
May be programm,ed to be input
(during read), low impedance
latched output (after write), or a tristate (after read). Datl\ on pins
P2o-P23 may be directly written,
ANDed or ORed with previous
data,
+5 volt supply.
FUNCTIONAL DESCRIPTION
~eneral Operation
The 8243 contains four 4-bit 1/0 ports which serve
as an extension of the on-chip I/O and are addressed as ports 4-7. The following operations may
be performed on these ports:
Read Mode
All communication between the 8048 and the 8243
occurs over Port 2 (P20-P23) with timing provided
by an output pulse on the PROG pin of the processor. Each transfer consists of two 4-bit nibbles:
The'
ns
ns
ns
80 pF Load
TEST POINTS
0 . 4 5 - - -......
6:805
AFN-Q0214A-03
8243
WAVEFORMS
PROG
~
PORT 2
_______________ 'K ______________
~
FLOAT
FLOAT
PORT 2
/
IpO
OUTPUT
VALID
PREVIOUS OUTPUT VALID
INPUT VALID
les
'es
6-806
AFN-II0214A-tl4
inter
8243
125
100
C
!
:;
~
....
<.!
75
z
II:
II:
:>
GUARANTEED WORST CASE
CURRENT SINKING CAPABILItiES
"iiiz
OF ANY 1/0 PORT PIN vs. TOTAL
U
...
50
SINK CURRENT OF ALL PINS
.
I!0
25
I
9
10
11
'2
'3
MAXIMUM SINK CURRENT ON ANY PIN@ .45V
MAXIMUM IOL WORST CASE PIN (mA)
Figure 3
Sink Capability
The 8243 can sink 5 mA@ .45Von each of its 161/0
lines simultaneously. If, however, all lines are not
sinking simultaneously or all lines are not fully
loaded, the drive capability of any individual line
increases as is shown by the accompanying curve.
Example: This example shows how the use of the 20 mA
sink capability of Port 7 affects the sinking
capability of the other 1/0 lines.
An 8243 will drive the following loads simultaneously.
For example, if only 5 of the 16 lines are to sink
2 loads-20 mA @ 1V (port 7 only)
8 loads-4 mA @ .45V
6 loads-3.2 mA@ .45V
Is this within the specified limits?
curr~nt at one time, the curve shows that each of
those 5 lines is capable of sinking 9 mA @ .45V (if
any lines are to sink 9 mA the total 10l must not
exceed 45 mA or five 9 mA loads).
Example: How many pins can drive 5 TTL loads (1.6 mAl
assuming remaining pins are unloaded?
10l =5 x 1.6 mA =8 mA
,10l = 60 mA from curve
# pins =60 mA + 8 mAlpin
,10l = (2 x 20) + (8 x 4) + (6 x 3.2) = 91.2 mA.
From the curve: for 10l = 4 mA, ,10l = 93 mA.
since 91.2 mA < 93 mA the loads are within
specified limits.
=7.5 =7
Although the 20 mA @ IV loads are used in
calculating ,10l, it is the largest current required @ .45V which determines the maxim'um
allowable ,IOL.
In this case, 7 lines can sink 8 mA for a total of
56mA. This leaves 4 mA sink current capability
whit;h can be divided in any way among the
remaining 8 1/0 lines of the 8243.
NOTE: A 10 to 50K 0 pullup resistor to +5V should be added to 8243 outputs When driVing to 5V CMOS directly.
6-807
AFN-Q0214A-05
';:
8243
fl
~1I0
CS
~TEST
3
8048
P20·P23
P4
4
P5
4
P6
4
P7
4
)110
PROG
PROG
INPUTS
4
8243
v
"-
I/O
)110
DATA IN
P2
)110
Figure 4. Expander Interface
BITS 3,2
P20-e23
--('-_-.JX'-___..J)~-. ADDRESS f4-BITSI
BITS 1,0
~!1 ~:~~E
00,
11
11
I AND
01
10
PORT
J
ADORfSS
OATA fiBITS)
Figure 5. Output Expander Timing
PORT 1
8048
PORr2
PROG~--------------~----------------~----------------~--~----~------~
Figure 6. Using Multiple 8243's
6-808
AFN-Q0214A-06
8295
DOT MATRIX PRINTER CONTROLLER
• Programmable Print Intensity
• Interfaces Dot Matrix Printers to
MCSo48T11 , MCs-&oI86T11 , MCSoaeTIi
Systems
• Single or Double Width Printing
• 40 Character Buffer On Chip
• Serial or Parallel Communication with
Host
• Programmable Multiple Line Feeds
• DMA Transfer CapabilitY
• 3 Tabulations
• Programmable Character Density (10 or
12 Chararctersllnch)
• 2 General Purpose Outputs
The Intel- 8295 Dot Matrix Printer Controller provides an Interface for microprocessors to the LRC 7040 Serl~s dot
matrix Impact printers. It may also be used as an Interface to other similar printers.
The chip may be used In a serial or parallel communication mode with the host processor. In parallel mode, data
transfers ara based on pOlling, Interrupts, or DMA. Furthermore, It provides Internal buffering of up to 40 characters
and contains a 7 x 7 matrix character generator accommodating 64 ASCII characters.
INTERNAL
aus
TW
STa
MOT
mr
HOME
PFEED
G"
G..
Figure 1. Block Diagram
Figure 2. Pin Configuration
6·809
·inter
8295
Table 1. Pin Description
Symbol
Pin
No. ~pe
"
Neme and Function
"'FEED
1
I
Pepar Feed: Paper feed InRut
switch.
XTALI
XTAL2
2
3
I
Cryatel: Inputs for a crystal to set Internal oscillator frequency. For
proper operation USe 6 MHz crystal.
RESET
4
I
NC
5
CS
6
GND
7
RD
8
Vcc
9
WR
10
SYNC
Do
D,
D2
D3
D.
D.
D6
D7
,
Pin
sYmbol
No.
~pa
Name and Function
39
I
Homa: Home input switch, used by
the 8295 to detect that the print head
Is in the home position.
HOME
\
Re.at: Reset input, active low: After
reset the 8295 will be set for 12 char·
acters/lnch singlll width printing,
solenoid strobe at 320 msec.
DACK/SIN
38
I
DMA Acknowladga/Serlallnput: In
the p,rallel mode used as D~A acknoWledgment; II) the serial mode,
used as Input for data.
DRQ/CTS
37
0
DMA Raque8tlClaar to Sand: In the
parallel mode used as DMA request
Ol,ltput pin to Indlcete to the 8257 that
a DMA transfer Is requested; in the
serial mode 'lsed as clear-to-send
signal.
IRQ/~
36
0
Intarrupt Raque.tlSerlal Mode: In
parallel mode it is an interrupt request Input to'the master CPU; in
Sjlrial mode it should .be strapped to
Vss·
MOT
35
STB
34
0
0
S;
33
32
31
No Connection: No connection or
tied high.
I
Chip Select: Chip select input used
to enable the RD and WR inputs except during DMA.
Ground: This pin must be tied to
ground.
I
Read: Read input which enabl., the
master CPU to read data and status.
In the serial mode this pin must be
tied to Vcc.
Power: +5 volt power input: +5V ±
10%.
I
WrHe: Write input which enables the
master CPU to write data and commands to the 8295. In the serial mode
this pin must be tied to Vss.
'Sa
S,
50
~,
11
0
Sync: 2.5 /LS clock output. Can be
used as a strobe for external circuitry.
/12
13
14
15
16
17
18
19
VO
Data Bus: Three-state bidirectional
data bus buffer lines used to interface
the 8295 to the host processor in the
parallel mode. In the serial mode
Do-D2 sets up the baud rate.
~ND
20
Ground: This pin must be tied to
ground.
Vcc
40
Power: +5 volt power input: +5 ±
10%.
So
6-819
0
Motor~
Main motor drive, active low.
Solenoid Strobe: Solenoid'strobe
output. Used to determine duration of
solenoids activation.
Solenoid: Solenoid drive outputs;
active low.
30
'S1
29
28
27
Voo
26
Vcc
25
GPI
GP2
24
fOF
PFM
Power: +5V power input (+5V ±
10%). Low power standby pin. ,
Power: Tied high.
23
0
0
Genarsl Purpose: General purpose
output pins.
22
I
Top of Form: Top ofform input, used
to sense top of form signal for type T
printer.
21
0
Paper Faed Motor Drive: Paper
feed motor drive, active low.
AFN-00231C
•
8295
Communication between the 8295 and the host processor can 'be implemented in either a serial or parallel
mode. The parallel mode allows for character transfers
Into the buffer via DMA cycles. The serial mode features
selectable data rates from 110 to 4800 baud.
FUNCTIONAL DESCRIPTION
The 8295 Interfaces microcomputers to the LRC 7040
Series dot matrix impact printers, and to other similar
printers. It provides internal buffering of up to 40 characters. Printing begins automatically when the buffer Is
full or when a carriage return charscter is received. It
provides a modified 7x7 matrix character generator. The
character set Includes 64 ASCII characters.
The 8295 also offers two general purpose output pins
which can be set or cleared by the host processor. They
can be used with various printers to implement such
functions as ribbon color selection, enabling form
release solenOid, and reverse document feed.
COMMAND SUMMARY
Hex Code
Description
Hex Code
00
Set G1;'1. This command brings the GP1 pin
to a logic high state. After power on It Is
automatically set high.
09
Description
Tab character.
OA
LI ne feed.
Multiple Line Feed; must be followed by i
byte specifying the number of line feeds.
01
Set GP2. Same as the above but for GP2.
OB
02
Clear GP1. Sets GP1 pin to logic low state,
Inverse of command 00. ,
oc
03
Clear GP2. Same as above but for GP2. Inverse command 01.
Top of Form. Enables the line feed output
until the Top of Form input is activated.
00
04
Software Reset. This is a pacify command.
This command Is not effective Immediately
after commands requiring a parameter, as
the Reset command will be Interpreted as a
parameter.
Carriage Return. Signifies end of a line and
enables the printer to start printing.
OE
Set Tab #1, followed by tab pOSition byte.
OF
Set Tab #2, followed by tab position byte.
Should be greater than Tab #1.
10
Set Tab #3, followed by tab position byte.
Should be greater than Tab #2.
05
Print 10 characters/in. density.
08
Print 12 characters/In. density.
07
Print double width characters. This command prints characters at twice the normal
width, that is, at either 17 or 20 characters
per line.
11
Print Head Home on Right. On some )
printers the print head home position is on
the right. This command would enable normalleft to right printing with such printers.
08
Enable DMA mode; must be followed by
two bytes specifying the number of data
characters to be fetched. Least significant
byte accepted first.
12
Set Strobe Width; must be followed by
strobe width selection byte. This command
adjusts the duration of the strobe activation.
Table 2. Solenoid On-Time
PROGRAMMABLE PRINTING OPTIONS
CHARACTER DENSITY
The character density Is programmable at 10 or 12 characters/inch (32 or 40 characterslline). The 8295 is automatically set to 12 characters/Inch at power-up. Invoking
the Print Double-Width command halves the character
density (5 or 6 characters/Inch). The 10 charlln or 12
charlln command must be re-issued to cancel the
Double-Width mode. Different character density modes
may not be mixed within a single line of p~lnting.
PRINT INTENSITY
The IntenSity of the printed characters Is determined by
the amount of time during which the solenoid Is on. This
on-time Is.programmable via the Set Strobe-Width command. A byte following this command sets the solenoid
on-time according to Table 2. Note that only the three
least significant bits of this byte are Important.
6-811
D7-D3
D2
D1
DO
SolenpldOn
(mlcro.ec)
x
x
x
x
x
x
x
x
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
200
240
280
320
,360
400
440
480
TABULATIONS
Up to three tabulation pOSitions may be specified with
the 8295. The column pOSitiOn of each tabulation is
selected by issuing the Set Tab commands, each folAfN.OO231C
intJ
8295
lowed by'a byte 'speclfying the column. The tab posl.
tlons will then remain valid until new Set Tab commands
are Issued.
the 8257 DMA controller without further CPU interven·
tion. Figure 4 shows a block diagram of the 8295 in DMA
mode.
Sen~Ii'ng a tab character (09H) will automatically fill the
character buffer with blanks up to the next tab position.
The character sent immediately after the tab character
•
will thus be stored and printed at that position.
CPU TO 8295 INTERFACE
Communication between the CPU and the 8295 may
take place In either a serial or parallel mode. However,
the selection of modes is Inherent in tlie system hard·
ware; it is not software programmable. Thus, the two
modes cannot be mixed in a 'single 8295 application.
PARALLEL INTERFACE
Two internal registers on the 8295 are addressable by
the CPU: on"e for input, one for output. The following
table describes how these registers are accessed.
DONE
Register
1
o
o
o
o
Input Data Register
Output Status Register
Figure 3. Host to 8295 Protocol Flowchart
8257
Input Data Register-Data written to this register is
interpreted in one of two ways, depending on how the
data is coded.
( ' - - -.... \1
DMA
CONTROLLER
IlACKx
DRQx
1. A command to be executed (OXH or lXH).
2. A character to be stored in the character buffer for
printing (2XH, aXH, 4XH, or 5XH). See the character
set, Table 2.
Output Status Reglster-8295 status Is available in this
register at ali times.
STATUS BIT:
FUNcnON:
I~
If-----I
4
PA
DE
l!lf-----I
"'f------!
IIF
PA-Parameter Required; PA = 1 Indicates that a com·
mand requiring a parameter has been received. A tter the
necessary parameters have been received by the 8295,
the PA flag is cleared.
DE-DMA Enabled; DE = 1 whenever the 8295 is in DMA
mode. Upon completion of the required DMA transfers,
the DE flag ,i!1 cleared.
·IBF-Input Buffer Full; IBF = 1 whenever data is written
to the Input Data Register. No data should be written to
, the 8295 when rSF= 1.
A flow chart describing communication with the 8295 is
shown in Figure 3.
'
The interrupt request output (IRQ, Pin 36) is available on
the 8295 for interrupt driven systems. This output is
asserted true whenever the 8295 is ready to receive data.
To Improve bus efficiency and CPU overhead, data may
be transferred from main memory to the 8295 via DMA
cycles. Sending the Enable DMA command (08HUlCti· .
vates the DMA Ghannel of the 8295. This command must
be followed by two bytes specifying the length of the
data string to be transferred (least signlficaht byte first).
The 8295 wlH'then assert the required DMA requests to
"PFEED 1 - - - - - - - - 1
HOME 1 - - - - - - - - 1
Figure 4. ParaJlel System Interface
Data:transferred in ,he DMA mode may be either com·
mands or characters or a mixture of both. The procedure
Is as follows:
1. Set up the 8257 DMA controller channel by sending a
starting address ,and a block length.
2. Set up the 8295 by issuing the "Enable DMA" com·
mand (08H) followed by two bytes specifying the
block length (least significant byte first).
The DMA enabled flag (DE)' will be true until the'
assigned dafa transfer is completed. Upon completion
of the transfer, the flag is cleared and the' interrupt request (IRQ) signal is asserted. The 8295 then returns to
the non·DMA mode of operation.
AfN.OO231C
8295
+II
SERIAL INTERFACE
. The 8295 may be hardware pr,ogrammed to operate In
a serial· mode of communication. By connecting the
IRQ/SER pin (pin 36) to logic zero, the serial mode Is
enabled Immediately upon power-up. The serial Baud
rate Is also hardware programmable; by strapping pins
14, 13, and 12 according to Table 3, the rate Is selected.
CS, RD, andViiR must be strapped as shown in Figure 5.
STB
Sf
ii
iii
Table 3. Serial Baud Aate
Pin 14
Pin 13
0
0
0
0
0
0
1
0
0
1
1
1
1
1
1
1
Pin 12
0
1
0
1
0
1
0
1
TO
SO~ENOID
§4
Baud Rate
DRIVERS
8285
53
110
150
300
600
1200
2400
4800
4800
52
51
MOi'
}
PFii
The serial data format is shown in Figure 5. The CPU
should wait for a clear to send signal (CTS) from the
8295 before sending data.
TO MOTOR
DRIVERS
Figure 6: 8295 To Printer So.lenold Interface
OSCILLATOR AND TIMING CIRCUITS
The 8295's Internal timing generation Is controlled by/a
self-contained oscillator and timing circuit. A 6 MHz
crystal Is used to derive the basic oscillator frequency.
The ri!sident timing circuit consists of an OSCillator, a
state counter and a cycle counter as Illustrated In Figure
7. The recommended crystal connection is shown in
Figure 8.
SYNC
OUTPUT
(2.5jAsec)
SERIA~
INPUT
STOP
BIT
Figure 7. Oscillator Configuration
Figure 5. Serial Interface to UAAT (8251A)
8295 TO PRINTER INTERFACE
1-8 MHz
The strobe output signal of the 8295 determines the
duration of the solenoid outputs, which hold the data to
the printer. These solenoid outputs cannot drive the
printer solenoids directly. They should be buffered
through solenoid driverS as shown in Figure 6. Recommended solenoid and motor driver circuits may be found
in the printer manufacturer's interface guide.
20 PFi
r
XTA~l
f!1tiI .
13
8285
XTAL2
Figure 8_ Aecommended Crystal Connection
6-813
AFN-00231C
intJ
.
.,
",
8295
,
8295 CH,ARACTER SET
Hex Code
20
21
22
23
24
25
26
27
28
29
2A
28
2C
20
2E
2F
Prinl Char. ,
Hex Code
PrinlChar.
Hex Code
30
31
32
0
1
2
3
4
5
6
7
8
9
40
space
!
,n
#
33
$,
34
35
36
37
38
39
,3A
38
3C
%
& ..
+.
3~'
.
>
?
ABSOLUTE MAXIMUM RATINGS*
, D.C'. AND OPERATING CHARACTERISTICS
VIL
V IL1
,
Input Low Voltage (All
Except X" X2. RESET)
Inpm Low Voltage (X" X2.
AESET)
A
8
C
0
E
F
,
MIn.
-0.5
~ex'Code
PrlnlChar.
,'
50
51
52
Q'
·53,
S
54
55
T
U
V
W
X
P,
R
56
G
57
H
I
58
K
L
M
N
0
(TA = O'C to 70'C, Vee
Typ.
Max.
0.8
= Voo = +5V ±
Unit
0.6
V
2.2
Vee
V
VIH1
~PUH:i9h Voltage (X1. X2.
3.S
Vcc
V
0.45
,0.45
V
V
IOL=2.0mA
IOL=1.6mA
V
V
IOH= -400jjA
IOH= -50jjA
IlL
,) 10FL
100
,100+ Icc
lu
ILI1
IIH
.cIN
CliO
)
t
Teel Condilions
Input High VOIWge ~I
Except X" X2. ES
VOH
VOH1
\
10%, Vss = OV)
VIH
VOL
VOL1
Z
[
V
'':'0.5
ES
Output Low Voltage (DO-07)
Output Low Voltage (All
Other Outputs)
Output High Voltage (00-07)
Qutput High Voltage (All
, Other Outpuis)
y
59
5A
58
5C
50
5E
5F'
J
Limite
Parameler
@
'NOTICE: Stresses abcive those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operatlon.,1 sections of this specification is not Implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
,AmbIent Tempe;~ture Under 8ias ......... 0 'C to 70'C
Storage Temperature ................ - 65' to + 160'C
Voltage on Any Pin With
Respect to Ground ...... .' .......... ,-0.5V,to +7VPower Dissipation ......................... 1.5 Watt
Symbol
"
41
,42
43 ,
44
45
46
47
48
49
5A
48
4C
40
4E
4F
<
·3E
3F
Prinl C~ar. '
,~
2.4
2.4
Input Leakage Current
:1:10
jjA
Vss'" VIN'" Vee
Output Leakage Current
(0 0-07. High Z State)
Voo Supply Current
Total Supply Current
Low Input Load Current
(Pins 24,27-38) .
Low Input Load Current
:1:10
jjA
Vss+0.45" VOUT" Vce
15
125
0.5
mA
mA'
, mA
VIL=O.S~
0.2
mA
VIL=O.QV
100
p.A
VIN = Vcc
(RD. WR. CS. ~
(~:
5
60
-
,
Input High Leakagll Current
(Pins 22, 38)
' I"p~t Capacitance
I/O Capacitance
'
"
,
10
20
, 6-St4
" pF
DF
AFI'l-00231C
inter
8295
A.C. CHARACTERISTICS
(TA
= o·c to 70·C, VCC = Voo = +5V ±
10%, Vss
= OV)
DBB READ
Symbol
tAR
tRA
Parameter
Min.
OS, Ao Setup to AD ~
OS, Ao Hold After RO t
Fro Pulse Width
tRR
tAD
CS,
tRo
RD ~ to Data Out Delay
ns
0
ns
250
Ao to Data Out Delay
toF
RD t to Data Float Delay
tCY
Cycle Time
Unit
MIX.
0
T..t Conditione
ns
225
ns
CL= 150 pF
225
ns
CL= 150 pF
ns
100
2.5
15
.,,5
Min.
MIX.
Unit
DBB WRITE
. Parameter
Symbol
tAW
~, Ao Setup to WF! ~
es,
0
ns
0
ns
ns
tww
Ao Hold After WR t
WR Pulse Width
250
tow
Data Setup to WR t
150
ns
two
Data Hold to WR t
0
ns
tWA
Test Conditions
DMA AND INTERRUPT TIMING
Symbol
Parameter
Min.
MIX.
Unit
DACK Setup to Control
0
tCAC
~ Hold After Control
0
tCRQ
WR to ORO Cleared
200
ns
tACO
DACK to Data Valid
225
ns
tAcc
A.C. TESTING INPUT, OUTPUT WAVEFORM
Test Conditions
ns
ns
CL = 150 pF
A.C. TESTING LOAD CIRCUIT
INPUT/OUTPUT
u=x > < x=
2.0
2.0
DEVICE
UNDER
TEST
TEST POINTS
O.B
0 .•
~C'=150PF
0.45
6-815
AF~1C
inter
8295
WAVEFORMS
READ OPERATION-OUTPUT BUFFER REGISTER
ei OR Ao
kf
'\
~1··11----"'R----.j
R5
(SYSTEM'S
----/:T1.----:'--------""":"---{~.'------------- ADDRESS BUS)
----~~~~
"
- I....
~~------~
(READ CONTROL)
._I__:-- I_R·C
_ M'''':-?~-----------<.i==:::::j)-
DATA BUS _ _ _ _ _ _
II,_ _ _
(OUTPUT)
WRITE OPERATION-INPUT BUFFER REGISTER
...
CSOR"
.J\/L______________~ L___-:._________ (SYSTEM'S
ADDRESS BUS)
____
fir-
_
r:.
I---,----iww - - - - I
W
(WRITE CONTROL)
DATA BUS
(INPUT)
DATA
MAY CHANGE
DATA
MAY CHANGE
--------------~
DMA AND INTERRUPT TIMING
..
--lAce....
I
1cAc--
\
~
DRQ
O:~:
,
'eRa
lAc.
~
\
X
----------~--------------------~.~.--------VALID
6-816
AFN-D0231C
inter
8295
WAVEFORMS (Continued)
PRINTER INTERFACE TIMING
MOTOR DRIVE
HOME
SOLENOID DATA
\
.
I{
)
K
- S Ds
~
. SOLENOID STROBE
i-- p ... -
Sym~ol
J
'--;~>:LJ
-
MH.
-
Typical
Parameter
Poti
Print delay from
home inactive
1.8ms
Sos
. Solenoid data
setup time before
strobe active
25,..s
SHS
Solenoid data
hold ,after strobe
inactive,
>1 ms
-
MHA
" Motor hold time
. after home active
3.2ms
PSP
. " PFEED setup time
after PFM active
58ms
PHP
PFM hold time
after PFEED active
6-817
9.75 ms
AFN-00231C
ICE™ -42
8042 IN-CIRCUIT EMULATOR
•
Precise, full-speed, real-time emulation
Load, drive, timing characteristics
Full-speed program RAM
Parallel ports
Data Bus
•
User-specified breakpoints
•
Execution trace
User-specified qualifier registers
Conditional trigger
Symbolic groupings and display
Instruction and frame modes
•
•
Full symbolic debugging
•
Single-line assembly and disassembly
for program instruction changes
• , Macro commands and conditional
block constructs for automated
debugging sessions .
•
HELP facility: ICETM-42 command
syntax reference at the console
•
User.confidence test of ICETM-42
hardware
Emulation timer
The ICETM_42 module resides in the Intellec Microcomputer Development System ami interfaces to
any user-designed 8042 or 8041 A system through a cable terminating in an 8042 emulator microprocessor, and a pin-compatible plug. The emulator processor, together with 2K bytes of user program
RAM located in the ICE-42 buffer box, replaces the 8042 device in the user system while maintaining
the 8042 electrical and timing characteristics. Powerfullntellec debugging functions are thus extended
into the user system. Using the ICE-42 module, the designer can emUlate the system's 8042 chip in
real-time or single-step mode. Breakpoints allow the user to stop emulation on user-specified
conditions, and a trace qualifier feature allows the conditional collection of 1000 frames of trace data.
Using the single-line 8042 assembler the user may alter program memory using the 8042 assembler
mnemonics and symbolic references, without leaving the emulator environment. Frequently used command sequences can be combined )nto compound commands and identified as macros with userdefined names.
©INTEL CORPORATION, 1983
6-818
MAY 1983
Order Number: 210818-001
infel~
ICETM_42 IN-CIRCUIT EMULATOR
8042 microcomputer. Thus, the ICE-42 module
provides the ability to debug a prototype or production system at any stage in its development
without introducing extraneous hardware or software test tools.
FUNCTIONAL DESCRIPTION
Integrated Hardware and Software
Development
Symbolic Debugging
The ICE-42 emulator allows hardware and software development to proceed interactively. This
approach is more effective than the traditi.onal
method of independent hardware and software
development followed by system integration.
With the ICE-42 module, prototype hardware
can be added to the system as it is designed.
Software and hardware integration occurs while
the product is being developed.
The ICE-42 emulator assists four stages of
development:
SOFTWARE DEBUGGING
This emulator operates without being connected
to the user's system before any of the user's
'hardware is available. In this stage ICE-42 debugging capabilities can be used in conjunction
with the Intellec text editor and 8042 macroassembler to facilitate program development.
T,he ICE-42 emulator permits the user to define
and to use symbolic, rather than absolute, references to program and data memory addresses.
Thus, there is no need to recall or look up the addresses of key locations in the program, or to
become involved with machine code.
When a symbol is used for memory reference in
an ICE-42 emulator command, the emulator supplies the corresponding location as stored in the
ICE-42 emulator symbol table. This table can be
loaded with the symbol table produced by the assembler during application program assembly.
The user obtains the symbol table during software preparation simply by using the "DEBUG"
switch in the 8042 macroassembler. Furthermore, the user interactively modifies the emulator symbol table by adding new symbols or
changing or deleting old ones. This feature provides gre'at flexibility in debugging and minimizes
the need to work with hexadecimal values.
Through symbolic references in combination
with other features of the emulator, the user can
easily:
HARDWARE DEVELOPMENT
The ICE-42 module's precise emulation characteristics and full-speed program RAM make it a
valuable ~ool for debugging hardware.
SYSTEM INTEGRATION
Integration of software and hardware begins
when any functional element of the user system
hardware is connected to the 8042 socket. As
each section of the user's hardware is
completed, it is added to the prototype. Thus,
each section of the hardware and software is
"system" tested. in real-time operation as it becomes available.
SYSTEM TEST .
When the user's prototype is complete, it is
tested with the final version of the user system
software. The ICE,42 module is then used for
real-time emulation of the 8042 chip to debug
the system as a completed unit.
The' final' product verification test may be performed using the 8742 EPROM version of the
• Interpret the results of emulation activity collected during trace.
• Disassemble
program
memory
to
mnemonics, or assemble mnemonic instructions to executable code.
• Reference labels or addresses defined in a
user program.
Automated Debugging and Testing
MACRO COMMAND
A macro is a set of commands given a name. A
group of commands executed frequently can be
defined as a macro. The user executes the
group of comma'nds by typing a colon followed
by the macro name. Up to ten parameters may
be passed to 1he macro.
Macro commands can ·be defined at the beginning of a debug session and then used throughout the whole session. One or more macro defini"
tions can be saved on diskette for later use. The
Intellec text editor may be used to edit the macro
file. The macro definitions are easy to include in
any later emulation session.
6-819
AFN-OOl4BB
inter
ICE™ -42IN·CIRCUIT EMULATOR'
"
T~ble 1 Major Emulation Commands
The power of the development system can 'be
applied to manufacturing testing as well' as
development by writing test sequences as'
macros. The macros are stored on diskettes fof
use during system test.
Command
GO
"
COMPOUND COMMAND
Compound commands provide conditional execution of commands (IF command) !lnd execution of commands repeatedly until certain conditions are met (COUNT, REPEAT commands).'
BRO, BR1, BR
\
Compound commands may be nested any
number of times, and may be used in macro
commands.
Example:
"DEFINE .1=0
"COUNT l00H
:IF .I AND 1 THEN
..*CBYTE.I =.1
..*END
,*.1-.1 + 1
.·END
; Define symbol.! to 0
; Repeat the following
commands 100H times.
; Check if .I is odd
; Fill the memory at
location.! to value .I
EMULATION
The ICE-42 module can emulate the operation of
prototype 8042 system, at real-time speed (up tv
12M Hz) or in single steps. Emulation commands
to the ICE-42 module control the process of setting up, running, and halting an emulation of the
user's 8042-basedsystem. Breakpoints and tracepoints enable the ICE-42 emulator to halt emulation and provide a detailed trace of execution
in any part of the user's program. A summary of
the emulation commands is shown in Tabte 1. '
Sets or, displays either or
both Breakpoint Registers
used for stopping
real-time emulation.
Performs single-step
emulation.
QRO,QRl
Specifies match
conditions for qualified
trace.
TR
Specifies or displays
trace-data collection
conditions and optionally
sets Qualifier Register
(QR~! QR1).
.
Synchronization
Line Commands
Sets and displays status
of synchronization line
outputs or latched inputs.
Used to allow real-time
emulation or trace to start
and stop synchronously
with external events,
Operating Modes
The ICE-42 software is an Intellec RAM-based
program that provides easy-to-use commands
for initiating emulation, defining ,breakpoints,
controlling trace data collection, and displaying
and controlling system parameters. ICE-42 commands are configured with a broad range of
modifiers that provide maximum flexibility in describing the operation to be performed.
Begins real-time
emulation and optionally
specifies break
conditions.
STEP
; Increment .1 by 1.
; Command executes
upon carriage-return
after END
(The Asterisks are system prompts; the dots
indicate the nesting levei of compound
commands.)
Description
Breakpoints
The ICE-42 hardware includes two breakpOint
registers that allow halting of emulation when
speCified conditions are met. The emulator continuously compares the, values stored in the
breakpoint registers with the status of specified
address, opcode, operand, or port values, and
halts emulation when this comparison is
satisfied. When an instruction initiates a break,
that instruction is executed completely before
the break takes place. The ICE-42 emulator then
regains control of the console and enters the interrogation mode. With 'the breakpoint featore,
the user can request an emulation break when
the program:
6-820
• Executes an instruction at a specific address
Or within a range of addresses.
AFN-OOl48B
inter
ICE™.42IN.CIRCUIT EMULATOR
tionally or unconditionally. Two unique trace
qualifier registers, specified in the same way as
breakpoint registers, govern conditional trace
activity. The qualifiers can be used to condition
trace data collection to take place as follows:
• Executes a particular opcode.
• Receives a specific signal on a port pin.
• Fetches a particular operand from the user
program memory.
• Fetches an operand from a specific address
in program memory.
'
• Under all conditions (forever). '
• Only while the trace qualifier is satisfied.
• For the frames or instructions preceding the
time when a trace qualifier is first satisfied
(pre-trigger trace).
Trace and Tracepolnts
Tracing is used with real-time and single-step
emulation to record diagnostic information in the
trace buffer as a program is executed. Theinfor"
mation collected includes opcodes executed,
port values, and memory addresses. The ICE-42
emulator collects 1000 frames of trace data.
• For the frames or instructions after a trace
qualifier is first satisfied (post-triggered
trace).
Table 2 shows an example of trace display.
If desired this information can be displayed as
assembler instruction mnemonics for analysis
during interrogation or single-step mode. The
trace-collection facility may be set to run condi-
INTERROGATION AND UTILITY
Interrogation and utility commands give convenient access to detailed information about the
Table 2 Trace Display (Instruction Mode)
Pl,
P2
TO
n
])BYIN
A, # 55H
Pl,A
P2,A
A,])BB
A
])BB,A
R2,#03H
RO,#.TApLEO
Rl,#.TABLEl
FFH
FFH
55H
55H
55H
55H
55H
55H
55H
FFH
FFH
FFH
55H
55H
55H
55H
55H
55H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
bbH
bbH
bbH
bbH
111
1'1
EAO])
MOV
MOV
INt
INC
])JNZ
A,@RO
@Rl,A
RO
Rl
R2, .LOOP
55H
55H
55ft
55H
55H
55H
.!iSH
55H
55H
55H
0
0
0
0
0
0
0
0
'0
0
10])H
10EH
10FH
llOH
lllH
FO
Al
111
1'1
EAO])
MOV
MOV
INC
INC
])JNZ
A,@RO
@Rl,A
RO
Rl
R2,.LOOP
55H
55H
55H
55H
55H
55H
55H
55H
55H
55H
0
0
0
0
0
0
0
0
0
0
10])H
10EH
10FH
llOH
lllH
ll3H
FO
Al
111
1'1
EAO])
DO
MOV
MOV
INC
INC
])JNZ
NOP
A,@RO
@Rl,A
RO
Rl
R2,.LOOP
55H
55H
55H
55H
55H
5SH
55H
55H
55H
'55H
55H
55H
EI
0
0
0
0
0
0
FRAME
LOC
OBJ
INSTRUCTION
DODD:
00011:
00011:
0012:
0014:
DOlI.:
00111:
0022:
00210:
.LOOP
0030:
00:32:
00311:
00310:
00311:
.LOOP
00"2:
DOli":
001110:
00"11:
0050:
.LOOP
DDS":
00510:
00511:
00100:
00102:
001010:
100H
102H
103H
10llH
105H
10bH
107H
10'11:1
10BH
2355
3'1
3A
22
37
02
BA03
BIIIIO
B'IbO
MOV
OUTL
OUTL
IN
CPL
OUT
MOV
MOV
MOV
10])H
10EH
10FH
UOH
lllH
FO
Al
6-821
0
0
0
0
0
YOUT YSTS TOVF
])FH
])FH
])FH
])FH
bbH
bbH
bbH
bbH
'1'1H
'1'1H
'1'1H
,
bbH
bbH
bbH
'1'1H
,
'1'1H
'1'1H
'1'1H
bbH
'1'1H
bbH
bbH
'1'1H
'1'1H
,
bbH
'1'1H
bbH
bbH
'1'1H
'1'1H
02H 0
02H 0
02H 0
02H 0
02H 0
DOH 0
DOH 0
OlH '0
OlH 0
OlH
OlH
OlH
OlH
OlH
0
0
0
0
0
OlH
OlH
OlH
OlH
OlH
0
0
0
0
0
OlH
OlH
OlH
OlH
OlH
OlH
0
0
0
0
0
0
AFN-OOl48B
intel"·
user program and the state of the 8042 that is
useful in debugging hardware and software ..
Changes can be made in memory and .in .the
8042 registers, flags, and port values.Commands are also provided for various utility 9'perations such as loading and 'saving program files,
defining symbols, displaying trace data, controlling system synchronization and returning control
to ISIS-II. A summary of the basic interrogation
and utility commands is shown in Table 3. Two
add'itic;>nal time-saving emulator features are discussed below.
Single-Line Assembler/Disassembler
The single-line assembler/disassembler (ASM
and DASM commands) pe~mits the designer to
examine and alter program memory using assembly language mnemor;lics, without leaving
the emulator environment 01' requiring timeconsuming program reassembly. When assembling new mnemonic instructions into program
memory,previously defined symbolic references
(from the original program assembly, or subsequently defined during the emulation session)
Table 3 Major Interrogation and Utility Commands
Command
Description
HELP
Displays help messages for ICE-42 emulator command-entry assistance ..
LOAD
Loads user object program (8042 code) into user-program memory, and
user symbols into ICE-42 emulator symbol table.
SAVE
Saves ICE-42 emulator symbol table and/or user object program in ISIS-II
hexadecimal file.
LIST
Copies all emulator console input and output to ISIS-II file.
EXIT
Terminates ICE-42 emulator operation.
DEFINE
Defines ICE-42 emulator symbol or macro.
REMOVE
Removes ICE-42 emulator symbol or macro.
ASM
,
. Assembles mnemonic instructions into user-program memory.
DASM
Disassembles and displays user-program memory contents.
Change/Display
Commands
Change or display value of symbolic reference in ICE-42 emulator symbol
table, contents of key-word references (including registers, I/O ports, and
status flags), ~r memory references.
EVALUATE"
Evaluates expression and displays resulting value.
MACRO
Displays ICE-42 macro
INTERRUPT
Displays contents for. the Data Bus and timer interrupt registers.
SECONDS
Displays contents of em\l'ation timer, in microseconds.
Trace Commands
Position trace buffer pOinter and select format for trace display.
PRINT
Displays trace data pOinted to by trace buffer pOinter.
MODE
Sets or displays the emulati,on mode, 8041 A or 8042.
,
or macros.
"
6-822
AFN-001488
ICETM_42 IN-CIRCUIT EMULATOR
Table 4 HELP Command
*HELP
Help is available for the following items. Type HELP followed by the item name·
The hl11p items cannot be abbreviated. (For more information, type HELP HELP or
HELP INFO.)
Emulation!
Trace Collection:
Misc:
Tft
Qft
QftO Qftlo SYlo BASE
GO Gft SYO
Bft BftOBftlo
DISABLE
STEP
Trace Display:
ENABLE
TftACE
MOVE
PftINT
EftftOft
< identifier>
OLDEST NEWEST
EVALUATE
HELP
< masked#cons tant >
Change I
Displayl Definel ftemove: INFO
ftEMOVE
CBYTE
< numer i c .cons tant >
DBYTE
DASM
LIST
SYr,lB.OL
ftEGISTEft
ftESET
ASM
LOAD
MODE
SECONDS
Wft I1':E
SAVE
< s tr i ng .constant >
DEFINE
STACK
SY
SUFFIX
SYMBOLIC
Macro:
Comp.ound
< trace.reference >
Commands:
. DI~
DEl'"iNE
< unl im i ted.match$cond >
DISABLE
ENABLE COU.tlT.
INCLUDE
PUT
IF
ftEPEAT
*
*
*HELP IF
IF - Thl;! conditional command allows conditional execution of one or more commands
based on the values of boolean conditions.
IF 'THEN
::=' @
;;=' @
'OftIF
:: =An ICE-4C! command.
@
'ELSE;
END
The s are evaluated in order as lob-bit unsigned integers. If one is
reached whose value has low-order bit lo (TftUE), all commands in the
following that are then executed and all commands in the other s and in the are skipped. I f all s have value with loworder bit 0 (FALSE), then all commands in all s are skipped and, if
ELSE is present, all commands in the are executed.
(EX: IF .LOOP=5 THEN
STEP
ELSE
GO
END)
*
*
*
*
*EXIT
6-823
AFN-00148B
IC'E™ .. 42IN .. CIRcurr EMULATOR
may be used in the instruction operand field.
The emulator supplies the absolute address or
data values as stoted in the emulator symbol
table. These features eliminate user time spent
translating to and from machine code and
searching for absolute addresses, with a corresponding reduction in transcription errors.
HELP
Additional emulator processor pins provide signals such as internal address, data, clock, and
control lines to the emulator buffer box. These
signals let static RAM in the buffer box substitute
for on-chip program ROM or EPROM. The emulator chip also gives the IC~ module "back-door"
access to internal chip operation, allowing the
emulator to break and trace execution without in'terfering with the values on the user-system
pins.
The HELP file allows display of ICE-42 command
syntax information at the Intellec console. By
typing "HELP", a listing of all items for which
help messages are available is displayed.
Typing "HELP - " then displays relevant
information about the item requested, including
typical usage examples. Table 4 shows some
sample HELP messages.
EMULATION ACCURACY
The speed and interface demands of a highp~rformance single-chip microcomputer require
extremely accurate emulation, including fullspeed, real-time operation with the full function
of the microcomputer. The ICE-42 module
achieves accurate emulation with an 8042
emulator chip, a special configuration of the
8042 microcomputer family, as its emulation
processor.
Each of the 40 pins on the user plug is connected
directly to the corresponding 8042 pin on the
emulator chip. Thus the user system sees the
emulator as an'8042 microcomputer at the 8042
socket. The resulting characteristics provide extremely accurate emulation of the 8042 including
speed, timing characteristics, load and drive
values, and crystal operation. However, the
emulator may draw more power from the user
system than a standard 8042 family device.
SPECIFICATIONS
Figure 1 A Typical 8042 Development
Configuration. The host system is
an Intellec Model 225, plus 1
megabyte dual double-density
flexible disk storage. The ICE-42
module is connected to a user r,rototype system.
• Emulation buffer box, 'Intellec interface
cables, and user-interface cable with 8042
emulation processor
ICETM-42 Operating Requirements
• Crystal power accessory
Intellec Microcomputer Development System
(64K RAM required)
System console
Intellec' Diskette Operating System (single or
double'density) ISIS-II (Version 3.4 or later).
• Operating inst~uctions manuals
• Diskette-based ICE-42 software (single and
double density)
Emulation Clock
Equipment Supplied
User's system clock (up to 12MHz) or ICE-42
crystal power accessory (12 MHz)
• Printed circuit boards (2)
6-824
AFN·OO148B
inter
ICETM_42 IN-CIRCUIT EMULATOR
Environmental Characteristics
Electrical Characteristics
Operating Temperature - 0° to 40°C
DC Power Requirements
(from Intellec® system)
Operating Humidity - Up to 95% relative humidity without condensation.
Vee ;= +5V, ± 5%
Icc = 1i3.2A max; 11.0A typical
Voo = +12V, ±5%
100 = 0.1 A max; 0.05A typical
VBB = -10V, ±5%
IBB ~ 0.05A max; 0.01 A typical
Physical Characteristics
Printed Circuit Boards
Width: 12.00 in. (30.48 cm)
Height: 6.75 in. (17.15 cm)
Depth: 0.50 in. (1.27 em)
Buffer Box
User plug characteristics at 8042 socket Same as 8Q42 or 8742 except that the user
system sees an added load of 25 pF capaCitance
and 50ILA leakage from the ICE-42 emulator
user plug at ports 1, 2, TO, and T1.
Width: 8.00 in. (20.32 cm)
length: 12.00 in. (30.48 em)
Depth: 1.75 in. (4.44 cm)
Weight: 4.0 lb. (1.81 kg)
ORDERING INFORMATION
Part Number Description
ICE-42
,
8042 Microcontroller In-Circuit
Emulator, cable assembly and in-, "
teractive diskette softw~re,
".
AFN-OOl48B
6-825
MCS~-48
DISKETTE-BASED SOFTWARE
SUPPORT PACKAGE
• Extends Intellec microcomputer
development system to support MCS-48
development
• MCS-48 assembler provides conditional
assembly and macro capability
• Takes advantage of powerfullSIS·n file
handling and storage capabilities
• Provides assembler output in standard
Intel hex format
The MCS-48 assembler translates symbolic 8048 assembly language instructions into the appropriate machine
operation codes, and provides both cO'nditional and macroassembler programming. Output may' be 10'aded
either to an ICE-49 module for debugging or into the iUP Universal PROM Programmer for 8748 PROM
programming. The MCS-48 assembler operates under the ISIS-II operating system on Intel Development
systems.
©INTEL CORPORATION, 1983
MAY 1983
6-826
inter
MCS@·48
'r
Table 1. Sample MC5-48 Dlskett.Based
FUNCTIONAL DESCRIPTION
The MCS-48 assembler translates symbolic 8048
assembly language instructions into the appropriate
machine operation codes. The ability to refer to program
addresses with symbolic names eliminates the errors of
hand translation and makes it easier to modify programs
when adding or deleting instructions. Conditional
assembly permits the programmer to specify which portions of the master source document should be Included or deleted In variations on a basic system design,
such as the code required to handle optional external
devices. Macro capability allows the programmer use of
a single label to define a routine. The MCS-48 assembler
will assemble the code required by the reserved routine
whenever the macro label is inserted in the text. Output
from the assembler is in standard fntel hex format. It
may be either loaded directly to an In-circuit emulator
(lCe-49) module for integrated hardware/software
debugging, or loaded into the iUP Universal PROM
Programmer for 874~ PROM prog~amming. A
sample assembly listing is shown in Table 1.
PAGEL
ISIS 1180lIl MACROASSEM!LEA VI 0
LOC
SOURCE STATEMENT
SEQ
OBJ·
,DECIMAL ADDITION ROUTINE ADO ICO NUMIER
AT LOCATION BETA TO ICD NUM8£A AT ALPHA WITH
,RESULT IN 'ALPHA' LENOTHQIi NUMHR tS COUNT, DIGIT
..
!I
..,.
"'''
"'"
.•
"
0107
0108
0108
ODD)
1
INIT
"
""
13
ALPHA
U
BETA
15 COUNT
16
11
18+
19+LI
0032
0100
0102
Olel'
0108
PAIAS (ASSUME BOTH BETAANO ALPHA ARE SAME LENGTH
AND HAVE EVEN NUMBER OF DIGITS 01'1 MSO IS 0 IF
6
BII1E
BI28
em
20.
..".""
."
97
22
FO
71
!l1
010A Al
0108 18
010C 1\1
0100 EM1
USER SYMBOLS
ALPHA OOOIE
LI
0102
BETA 0028
MACAO
MOV
AUGND,ADDNO.CNT
MO'
At .ADDNO
R2 .ONT
EOU
EOU
",
"""
ENCM
.fOU
OfIG
lNIT
MOV
MOV
MO'
CLA
LP
COuNT 0lI06
Mev
AOot::
0'
MO'
INC
INC
OJNZ
ENO
AD .AUQND
30
"""
ALPHA BETA COUNT
AD .ALPHA
Rl.BeTA
R2.coUNT
.
C
A @RO
A .,Rl
.'" A
"'"An'
LP 0107
ASSEMBLY COMPLETE NO ERRORS
ISIS II ASSEMBLER SYMBOL CROSS REFERENCE VI 0
SYMBOL CRQS& REFERENCE
ALPHA'3t
8ETA
14'
17
17
COU~T
1!t11
11
INIT
11
191
22t
28
Ll
LP
17
SPECIFICATIONS
Operating Environment
Documentation Package
(All)
Titles
Intel, Microcomputer Development Systems
(Series II, Series III/Intel equivalent)
Intel P13 rsonaL Development System
of:U~r
Guides
Operating Instructions
Reference ~anuals
I
Ordering
Informatio~
Part Number
Description
MDS-D4B
MCS-48 Disk Based Assembler
Requires Software License
SUPPORT:
Hotline Telephone SUPP9rt, Software Performance
Reports (SPR), Software Updates, Technical
Reports, Monthly Newsletters are available.
6-827
AfN-00618C
inter
iUP·2001 iUP·201
UNIVERSAL PROM PROGRAMMERS
MAJOR IUP·200/iUP·201 FEATURES:
ADDITIONAL IUP·201, FEATURES:
• Serial interface to aIIINTELLEC® •
Development Systems
• 24-character alpha·numerlc display
• Full hexadecimal plus 11·functlon
keypads
'
• Powerful PROM Programming Software
utility (IPPS)
• Off·line editing and, device duplication
•. Support for all ,Intel PROM families
through multiple device Personality
Modules
• 16K bytes RAM expandable to 32K bytes
• iUP system self·tests plus device integrity
checks
The iUP-200 and iUP-201 Universal Prom Programmers provide programming and verification of. data in all the
Intel programmable ROMs (PROMs). They can also be used for programming the PROM memory portions of
Intel's single-chip microcomputer and peripheral devices. When used with any INTELLEC Development System,
the iUP-200 and il.!P-201 provide on-line, programming and verification with the aid of the Intel PJ:!OM
Programming Software utility (iPPS). In addition, the iUP-201 supports off-line, stand-alone, program editing and
PROM duplication. The iUP·200 is completely expandable to the iUP-20t
The follOWing are trademarks of Intel Corporation and may,be used only to descnbe Intel products Intel, Intellee. MeS and ICE, and the combmatlon of MCS or ICE and a numerIcal sufflx_ Intel Corporation assumes no responsibility for the use of any CircUitry other than CirCUitry embodied In an Intel product. No other CirCUit patent licenses are Implied
, ,INTEL CORPORATION 1981
AFN-02138A
6-828
December 1981
210319
iU P·200/iU P·201
FUNCTIONAL DESCRIPTION
On·Line System
Hardware Components-The basic iUP-200 and iUP201 consist of a free-standing unit that, when interfaced directly to any Intel Development System
equipped with at least 64K bytes of user memory,
provides "on-line" PROM programming and verification of Intel programmable devices. In addition, the
units can read the contents of the ROM versions of
these devices. Communication with the host is accomplished through a standard RS232C serial data
link. A serial converter is needed when using the
MD5-SOO as a host system. These converters are
available from other manufacturers. Each unit contains an 8085 CPU, selectable power supply, 2.3K
bytes of static RAM, 8K bytes of pre-programmed
EPROM, a programmable timer, and circuitry for
interfacing to a Personality Module, keyboard,
display, and host system. The pre-programmed
EPROM contains the firmware needed for all iUP edit
and control functions.
The interface between the iUP and the target PROM
is accomplished using a family or single-device
Personality Module. No additional sockets or
adaptors are necessary. These Personality Modules
are iUP front panel inserted units containing all the
hardware and firmware necessary for programming
either a family of Intel PROMs or a single Intel device.
Figure 1 diagrams the on-line system data flow.
The iUP-201 will also accept Intel hexadecimal programs developed on a non-Intel Development System. Only a few keystrokes are required to download
the program into ,iUP RAM for editing and loading
into a PROM.
Loading programs into a PROM from INTELLEC
system memory or directly from a disk. file is
accomplished under iPPS control. Access to the
disk allows the user to create and manipulate data
in a virtual buffer with an address range up to 16M.
This large block of data can be formatted into different PROM word sizes for program storage into
several different PROM tYPes. In addition, a program from any of the three logical devices can be
"interleaved" with a second program and entered
into a specific target PROM or PROMs.
iPPS supports data manipulation in any Intel format:
8080 hexadecimal ASCII, 8080 absolute object, 8086
hexadecimal ASCII, 8086 absolute object, and 286
absolute object. Addresses and data can be displayed in one of several number bases including
binary, octal, decimal, and hexadecimal. The user
can easily change defaulted data formats as well as
number bases.
iPPS requires that version 3.4 or later of Intel's ISIS-II
Operating System be resident in INTELLEC Development System memory at the time of execution. The
software is designed to run under control of ISIS
"Submit Files" thereby freeing the user from repeti-·
tious command entry.
System Expansion-The iUP-200 can be easily expanded, by the user, for off-line operation. The Keyboard/Expansion Kit (iUP-PAK) is available from Intel
or your local Intel Distributor.
Software Components-The Intel PROM Programming Software utility (iPPS) is included with both the
iUP-200 and iUP-201. Created to run on aflY INTELLEC
Development System, iPPS provides user control of
all reading, programming, and verification functions
through an easy to use language driven interface. All
iPPS commands, as well as program address and
data information, are entered through. the development system ASCII keyboard and displayed on the
system CRT. These plain Engli.sh commands allow
the user to read and write data to 9r frpm any of three
logical devices: the target PROM, theANTELLEC system memory, or a disk file system. Additional commjinds control iPPS program execution, display information and status, allow rearrangement of data
from any of the three logical devices, and provide
user assistance information in the form of a HELP
command. Figure 2 summarizes these commands.
6-829
HOST DEVELOPMENT SYSTEM
AS-232INTEAFACE
""------,
-..I
_~
~:A:1
1
:
'- ______ ..J
Figure 1. On· Line System Data Flow
AFN·02138A
inter
iUP·2OOI.IUP·201
Program Control Group-Controls the program execution of IPPS.
EXIT
Exits iPPS and returns control to ISIS·II
< ESC>
Terminates current command
REPEAT
Repeats full execution of previous command
. ALTER
Allows edit and re-execution of previous command
Utility Group-Displays user Infonnatlon, status, and sets default values.
DISPLAY .
Displays PROM, Buffer, or File data on the console
PRINT
Prints PROM,Buffer or File data on a printer
HELP
Selectively displays user assistance information
MAP
Displays Buffer structure and status
BLANKCHECK
Checks for unprogrammed PROM
OVERLAY
Checks if non·blank PROM can be, programmed
TYPE .
Selects PROM type
INIT
Initializes the default number base and file type
WORKFILES
Specifies drive device for temporary work files
Buffer Group-Edits, modifies, and verifies data in the Buffer.
SUBSTiTUTE
Examines and modifies Buffer data
LOADDATA
Loads a section of the buffer with a constant
VERIFY
Verifies data in PROM with Buffer data
Formatting Group-Permits rearrangement of data from PROM, Buffer, or File.
FORMAT
Interactively formats the Buffer, PROM, or File data
and places the result in a workfile
Copy Group-Provides for variations of the general purpose COPY command.
COPY (File to PROM)
Programs PROM with data in a file on disk
COPY (PROM to File)
Saves PROM data in file on disk
COPY (Buffer to PROM)
Programs PROM device from Buffer
COpy (PROM to Buffer)
Loads Buffer with data in PROM
COpy (Buffer to File)
Saves Buffer in file on disk
COPY (File to Buffer)
Loads Buffer from file on disk
COPY (File to URAM)
Loads file data into iUP URAM
(iUP·201 only)
COpy (URAM to File)
Save iUP URAM data in a file
(iUP·201 only)
COpy (Buffer to URAM)
Loads Buffer into iUP URAM
(iUP·201 only)
COpy (URAM to Buffer.)
Loads iUP URAM data into the Buffer(iUP·201 only)
Figure 2. iPPS Command Summary·
. IUP·200 On-Line System Configuration
AFN-02138A
inter
iUP·20OJiUP·201
Off· Line System
While capable of performing all the on-line functions,
the iUP-201 allows program editing, PROM duplication, and program verification independent of the
host system_ In addition to the hardware components
included as part 'of the iUP-200, the iUP-201 contains
a 24-character alphanumeric display, full HEX ancf11function keypads, and 16K bytes of user RAM (URAM)
expandable to 32K bytes. This expansion provides
memory needed to store data for PROMs exceeding
16K bytes (128K bits) in size. Figure 3 illustrates the
iUP-201 keyboard and display.
rup
aaoa
RER]Y
I
B
The two logical devices accessible during off-line
operation are the PROM device and iUP-201 RAM.
. Typical operation would entail copying the data from
a PROM (or ROM) into iUP RAM, modifying this data
in RAM, and programming the modified data back
into a PROM device. The address range of the needed
RAM is automatically determined by the iUP when
PROM type selection is made.
OJ
ADOfIfSS
55
I
E
F
A
B
6
7
"i
LjD
L
o
POWER
Figure 3_iUP·201 Keyboard and Display
Figure 4 summarizes the off-line commands.
Selects either the on·line or the off line operation. When on-line, all other function keys are
disabled.
Selects the PROM type when a Personality Module capable of programming multiple devices is
used. The selected device is indicated by an adjacent LED on the installed module.
Verifies the contents of the installed PROM device with that of the iUP RAM. The iUP display indicates address and the 2's complement of any expected vs. actual mismatch.
Performs a device Biank Check and then programs the target PROM with data from iUP RAM. If
Blank Check fails, pressing PROG again will perform a stuck bit check to further verify PROM I
Program compatibility.
Loads the iUP RAM with the data from the PROM device installed in the Personality Module.
Terminates the current off-line function, clears a user entry, or restores the display after an error
condition.
Pressing the ENTER key transfers information from the iUP display (addresses or data) into
URAM.
Pressing the s'hift key and ADDRIO key selects the address field for keypad entry.
Pressing the shift key and DATAl1 key selects the data field for keypad editing and entry.
Pressing the shift key and FILU2 key selects the fill function, which allows a contiguous section
of RAM locations to be loaded with a constant.
Pressing the shift key and LOAD/3 initiates a download of Intel hexadecimal data from any development system with an R5-232C port.
Figure 4. Off·Line Command Summary
6-831
AFN·02138A
iUP·2001iOP·201
SYSTEM DIAGNOSTICS
Interfa~s
Both tlie iUP-200 and iUP-201 include self-contained
system diagnostics that provide verification of system operation and aid the user in fault isolation.
Diagnostics are performed on the power supply, CPU,
internal firmware ROM y internal RAM, timer, and on
the iUP-201 keyboard and URAM. In addition, tests
are made on any -Personality Module installed in the
programmer the first time the module is accessed.
They include tests on the power select circuitry and
the 2K of module firmware. Easy to read status messages are provided on the development system display in the on-line mode and the iUP-201 display in
the off-line mode.
Each personality module, an example is shown in
Figure 6, interfaces with the programmer through a
41·pin connector. Module firmware is uploaded into
i.uP RAM and executed by the onboard 8085A processor. This firmware contains routines needed to
Read arid Program a number of PROMs. In addition,
the personality module sends specific information
regarding the selected PROM to the iUP to aid in per·
forming PROM device integrity checks.
PERSONALITY MODULES
Operational status is indicated through individual
LEOs on each module. A column of device selection
LEOs indicate which PROM device type the user has
selected. After device selection, an LED below each
sqcket (on modules containing more than one socket)
indicates the socket to be used. A red indicator light
(Hot Socket) wa~ns the user when power is being
supplied to the selected device.
.
The iUP-200 a'pd iUP-201 interface with a selected
PROM (or ROM) through an associated Personality
Module. These modules contain all of the hardware
and firmware needed to read and program a family of
Intel devices. Each module is a single molded unit,
front panel inserted on either programmer. No additional adapters or sockets are needed, Figure 5 lists
the available modules.
iUP-F271128 ·E2IEPROM Personality Module capable
of reading and programming the 2716,
2732, 2732A, 2764, 27128, 2815, and 2816.
iUP-F87/51 . MICROCONTROLLER Personality Mod·
ule capable of reading and programming
the 8748, 8748H, 8048, 8749, 8049, 8750,
8050,8751, and 8051.
iUP·F87/44· PERIPHERAL Personality Module capa·
ble of reading and programming the
8741A,8041A,8742,8042,8744,8044,and
8755A.
Figure 6. iUp·F271128
Device Integrity Checks
iUP·F36132· BIPOLAR Personality Module capable
of reading and programming the 3628,
3632, 3632A, 3636, 3636B, and 3624.
In addition to the iUP system self·tests, each Person·
ality Module contains diagnostics in firmware that
perform selected PROM tests and indicate status:
These tests are performed in both the on-line and off·
line modes. A PROM installation test is performed to
insure the device is installed In the module correctly
and the ZIF socket is closed. A PROM Blank Check is
Figure 5. iUP Pel'$onality Modules
6-832
AFN·02138A
IUp·2OOIiUp·201
performed to determine whether a· device is in its
erased state. The iUP automatically determines
whether this erased state is all· zeros or all ones. A
stuck bit check Is performed when a PROM is found
to be not blank. This test determines which bits are
pre-programmed, compares those bits against the
program to be loaded, and allows programming to
continue if they match. As with the system self-tests,
easy to read status messages are provided. All of the
PROM device integrity checks, with the exception of
the installation test which occurs automatically any
time an operation is selected, can be invoked by the
user.
Figure 7 illustrates a typical on-line and off-line programming sequence.
No
No
Figure 7. iUP' Programming Sequence
6
6-833
AFN-02138A
inter
/
IUP·2OOI.IUp·201
iUP·2OOI201 SPECIFICATIONS
Environmental Characterislics
Operating Temperature-10°C to 40°C
Operating Humidity-O% to 95% Relative
Humidity
,
Control Processor
Intel 8085A Microprocessor
6.144 MHz Clock Rate
Reference Material
Memory
IUP·200/201 Universal Programmer User's Guide
iUP·200/201 Pocket Reference Card
R",VI-2.3K bytes Static
ROM-SK bytes EPROM
Interfaces
Keyboard-16 character Hexadecimal and 11·
function keypad (iUP·201 only)
Display-24 Character Alphanumeric (iUP·201
only)
PERSONALITY MODULE SPECIFICATIONS
Memory
EPROM - 2K bytes
Physical Characteristics
Software
Width Height Depth Weight -
Monitor-System Controller in pre·programmed
EPROM
iPPS-lntel PROM Programming Software utility
on supplied diskel'te
5.5 inches (14.0 cm)
1.6 inches (4.1 cm)
7.0 inches (17.S cm)
1 lb. (.45 kg)
Electrical Characteristics
Maximum power consumption (module)-5 watts
Maximum power consumption (device)-2.5 watts
Maximum power consumption (total from iUP)7.5 watts
Physical Characteristics
Depth-15 inches (38.1 cm)
Width-15 inches (38.1 cm)
Height-6 inches (15.2 cm)
Weight-15Ibs. (6.S kg)
Environmental Characteristics
Operating Temperature-10°C to 40°C
Operating Humidity-O% to 95% relative humidity
Electrical Characteristics
Selectable 100,120,200, or 240 Vac ± 10%;
50·60 Hz
Maximum power consumption-SO watts
Reference Material
Selected Personality Module User's Guide
ORDERING INFORMATION
Part Number
iUP-200
iUP-201
iUP-F27/128
iUP-F87/51
iUP-F87/44
iUP-F36/32
Description
Intel On-Line Universal
Programmer
Intel On-Line/Off-Llne Universal
Programmer
E2EPROM Personality Module
MICROCONTROLLER
Personality Module
PERIPHERAL Personality
Module
BIPOLAR Personality Module
6-834
AFN·Q2138A
Data Conununications
Peripherals
Section
7
\
inter
INTEL DATA COMMUNICATIONS
FAMILY OVERVIEW
Data Communications has become an increasingly
important factor in computer system design with the
evolution of distributed processing and remote, networked peripherals. Intel's data communications product line provides a range of components to satisfy the
broad spectrum of speed, protocol support and protocol
flexibility needs (Figure I).
.
four more common peripheral functions of a microprocessor based system as well as a full-duplex, double buffered serial asynchronous receiver/ transmitter with an
on-chip baud rate generator.
The 8273 is a dedicated high level peripheral controller
for SDLCj HDLC protocol support. It provides an high
level of Data Link Control support for IBM-SNA or
CCITT X.25 compatible microcomputer systems. This
·device minimizes CPU overhead by supporting a comprehensive frame level operation. The 8273 is compatible
with every telephone network-based communication system due to its speed (up to 64 Kbps) and flexible modem
interface.
GLOBAL DATA COMMUNICATIONS:·
ASVCHRONOUSAND SYNCHRONOUS PRomoCOLS
Dedicated data communications controllers
For low-to-medium speed (up to 19.2 Kbps), the 8251A
USART (U niversal Synchronous Asynchronous Receiver/
Transmitter) is the industry standard for asynchronous
communications. It can be ,used in such applications as
personal computers, workstations, word processors, CRT
terminals point-of-sale terminals, banking terminals,
printers, communications processors, data concentrators, industrial control networks, etc.
Multlprotocol controllers
Multi-protpcol controllers bridge the gap between byte
oriented and bit oriented protocols (HDLCj SDLC).
They provide an easy migration path for the user through
a single software reconfiguration. Design of high-level
protocols like X.25 are considerably simplified when they
are coupled with the power of high performance processors such as the iAPX 86/88/186, or 188. They are also
used to implement custom high-level protocols on top of
standard bit-synchronous protocols.
The 8256 MUART (Multi-function Universal Asynchronous Receiver/Transmitter) IS an highly competent
asynchronous communications controller. It considerably minimizes the number of LSI required in a system
with an asynchronous interface. The 8256 integrates the
The dual-channel 8274 MPSC (Multi-Protocol Serial
SPEED
10Mbps
1 Mbps
e
64 Kpbs
19.2 Kbps
8
ASYNC
8'
SOLC/HOLC
MULTI PROTOCOLS;
ASYNC, BYTE SYNC,
BIT SYNC •
CSMAICO
FIGURE 1: A Spectrum of Data Communications Solutions
7-1
PROTOCOL
SUPPORT
Controller) provide a solution for Asy~chronous, Byte
Synchronous (IBM Bisync) imd Bit 'Synchronous
(HDLe; SDLC) protocols support. It' is optimized' for
high-speed applications requiring the flexibility of the
protocol support and the integration of multiple communications channels.
The 8291 A'implements the Talker/ Listener functions of
the GPIB.
The 82530 SCC (Serial Communications Controller) is
another dual channel multiprotocol controller. It cOntains new functions including on-chip baud rate generators, digital phase locked loops, various data encoding/decoding schemes and extensive diagnostic capabilities.
All these added features reduce the need for external logic
and greatly improve the reliallility and maintainability of
the system.
The 8293 is a low-power, high-current, HMOS 8-line
transceiver. It provides the electrical interface to the
GPIB.
The 8292 provides the controller functions. Operating in
tandem with the 8291 A, it complements its interface functions to provi<\e a full-capability GPIB interface.
Local Area Networks
Intel has developed the first complete VLSI solution for
Local Area Networks (LAN s) and Ethernet in particular:
the 82586 Local Area Network Coporcessor and the
82501 ESI (Ethernet Serial Interface).
Distributed Intelligence Systems
The 8044/8744 is a microcontroller with an on chip serial
communication processor. It simplifies control of remote
subsystems (subsystems that are physically separated
from the host CPU and communicate over a serial link).
Four on chip DMA channels alIow the 82586 to operate
as a bus master. The 82586 manages the entire process of
transmitting and receiving frames, thereby relieving the
host processor of the tasks of managing the communication interface to the network.
The 8044 and 8051CPUs are identical. The serial communication is handled by an additional processor calIed
the SerialInterface Unit(SIU). The SIU operates concurrently with the CPU and offers a high level of,intelligence
and performance for HDLe;SDLC based communications. The SIU can' handle 2.4 Mbps in Half-Duplex
mode.
An extensive set of diagnostic capabilities, implemented.
in silicon, simplifies the design of more reliable local
networks and facilitates their maintenance. In order to
take full advantage of the LAN concept and CSMA/ CD
access method, the 82586 architecture is software configurable. This alIows the 82586 to be "customized" for
other applications including serial backplanes (serial
'peripheral interconnection), low cost short distance
LANs, broadband networks and medium speed (1-2
Mbps) LANs.
In addition to controlIing commllnications with the host
CPU, the 8044 provides significant peripheral control.
Examplesinclude .Iocal keyboard, CRT and printer control as welI as design of network for Distributed IntelIigence Systems (Medical instrumentation, CATV, PABX,
etc.... )
The 82501 is designed to work directly wit\!. the 82586 in
Ethernet applications. The major functions of the ESI are
to generate the JO MHz transmit clock for the 82586, to
perform Manchester encoding/ decoding of transmitted/received frames, and to provide the electrical interface to
the Ethernet transceiver cable
Detailed 8044/8744 information is contained in the Intel
MicrocontrolIer Handbook.
Instrumentation
The Intel Data Communications product family provides
a wide range of solutions for the needs of data communications systems.
The 8291 A, 8292, and 8293 family of components provide
complete, high-performance support for IEEE-488
(GPIBj standard interface. GPIB is used in instrumenta. tion applications.
7-2
APPLICATION
NOTE
'
© I"tel Corporation. 1976
7-3
AP-16
PRICE $1.00
APPLICATIONS
INTRODUCTION
The Intel 8251 is a Universal Synchronous/Asynchronous Receiver/Transmitter (USART) which is
capable of operating with a wide variety of serial
communication formats. Since many· peripheral
devices are available with serial interfaces, the 8251
can be used to interface a microcomputer to a
broad spectrum of peripherals, as well as to a serial
cemmunications channel. The 8251 is part of the
MCS-80™ Micreprocesser Family, and as such it is
capable of interfacing to the 8080 system with a
minimum of external hardware.
This application note describes the 8251 as a component and then explains its use in sample applicatiens via several examples. A specific use of the
8251 to facilitate communicatien between two
MCS-80 systems is discussed in detail from both
the hardware and software viewpoints. The first
two sections of this applicatien note describe the
8251 first from a functional standpoint and then
on a detailed level. The function of each input and
output pin is fully defined. The next section describes the various eperating modes and how they
can be seiected, and finally, a sample design is discussed using the 8251 as a data link between the
MCS-80 systems.
has to last fer the duration of the character (the
next character will contain a new START bit), this
method works quite well assuming a properly
designed receiver. One or mere STOP bits are
added to the end of the character to ensure that
the START bit of the next character will cause a
transition on the communicatien line and to give
the receiver time to "catch up" with the transmitter if its basic clock happens to be running slightly
slower than that of the transmitter. If, on the other
hand, the receiver clock happens to be running
slightly faster than tne transmitter clock, the receiver will perceive gaps between characters but
will still cerrectly doecode the data. Because of this
tolerance to minor frequency deviations, it is not
necessary that the transmitter and receiver clocks
be locked to the identical frequency for successful
asynchronous communication.
0
The synchroneus format, instead of adding bits to
each character, groups characters into records and
adds framing characters to the record. The framing
characters are generally known as SYN characters
and are used by the receiver to determine where
the character boundaries are in a string of bits.
Since synchronization must be held over a fairly
lon'g stream of data, bit synchronization is normally either extracted from the communication
channel by the modem or supplied from an external source.
COMMUNICATION FORMATS
Serial communications, either en a data link or
with a local peripheral, eccurs in one of two basic
formats;. asynchronous or synchronous. These formats are ,similar in that they both require framing
information to be added to. the data to enable
proper detectio~, ef the' cnaracter at the receiving
end. The major difference between the two formats is that the asynchronous format requires
framing information to be added to each character,
while the synchronous fOfI11at adds framing information to blocb of data, er messages. Since the
synchronous format is mo.re efficient than the
asynchronous format but requires mere complex
decoding, it is typically found on high-speed data
links, while the asynchrenous fermat is used on
lower speed lines.
The asynchronous format starts with the basic data
bits to. be transmitted and adds a "START" bit to
the front of them and one or more "STOP" bits
behind them as they are transmitted. The START
bit is a logical -zero, or SPACE, and is d\!fined as
the pesitive vohage level by RS-232-C. The. STOP
bit is a logical one, or MARK, and is defined as the.
negative voltage level by RS-232-C. In current loop
applications .current flow normally indicates a
MARK and lack of current a SPACE. The START
bit tells the receiver to start assembling a character
and allows the receiver to synchronize.itself with
the transmitter. Since this synchrenization only
An example of the synchronous and asynchronous
formats is shown in Figure 1. The synchronous
format shown is fairly typical in that it requires
two SYN characters at the start of the message.
The asynchronous format, also typical, requires a
START bit preceding each character and a single
STOP bit fellowing it. In both cases, two 8-bit
characters are to be transmitted. In the asynchronous mode 1O*n bits are used to transmit n characters and in the synchronous mode 8N + 16 bits are
used. For the example shown the asynchronous
mode is actually more efficient, using 20 bits
versus 32. To transmit a thousand characters in the
asynchronous mode, however, takes 10,000 bits
versus 8,016 for the synchroneus format mode.
For long messages the synchronous format becomes much more efficient than the asynchronous
format; the crossover point for the examples
shown in Figure 1 is eight characters, for which
both formats require 80 bits.
oIn, additien to the differences in format between
synchronous and asynchronous cemmunication,
there are differences with regards to the type of
modems that can be used. Asynchronous modems
. typically employ FSK (Frequency Shift Keying)
techniques which Simply generate one audio tene
for a MARK and another for a SPACE. The receiving modem detects these tones on the telephone
0
7-4
AFN-ooeooA
APPLICATIOMS
I I I
I I I
I I I
Ie
START BIT
DATA
,
START all
\
DATA
STOP BIT
AlvNCHRONOUS
DATA
SYN
CIIAR#2
SYN
CIIAR#'
Figure 1. Transmission Forlllllu
line, converts them to logical signals, and pre~nts
them to the receiving terminal. Since the modem
itself is not concerned with the transmission speed,
it can handle baud rates from zero to its maximum
speed. Synchronous modems, in contrast to asynchronous modems, supply timing information to
the terminal and require data to be presented to
them in synchronism with this timing information.
Synchronous modems, because of this extra clocking, are only capable Qf operating at certain preset
baud rates. The receiving modem, which has·~
oscillator running at the same frequency as the
transmitting modem, phase locks its clock to that
of the transmitter and interprets changes of phase
as data.
In some cases it is desirable to operate in a hybrid
mode which involves transmitting data with the
asynchronous format using a synchronous m04em.
This occurs. when an inCrease in operating speed is
required without a change in the basic protocol of
the system. This hybrid technique is known as
isosynchronous and involves the generation of the
start and stop bits associated with the asyn~hro
nous format, while still using the modem clock for
bit synchronizatiop.
.
The 8251 USART has been deSigned to meet a
broad spectrum of requirements in the synchronous, asynchronous, and isosynchronouS modes. In
the synchronous mode the 8251 operates with 5,
6, 7, or 8-bit characters. Eve)l Or odd parity can be
optionally appended and checked. Synchronization
can be achieved either externally via added hardware or internally via SYN character detection.
SYN detection can' be· based on one or two 'characters which mayor may not be the same. The single
or double SYN ,characters are inserted into the
data stream automatically if the software fails to
supply data in time. The automatic generatjon of
SYN characters is required to prevent the loss of
synchronization.' In the asynchronous mode the
8251 operates with the same data and parity structures as it does in the synchronous triode. In addition to appending a START bit to this data, the
825 I appends 1, I~, or 2 STOP bits. Proper framing is checked by the receiver and a status flag set
if an error occurs. In the asynchronous mode the
USART can be programmed to accept clock rates
of 16 or 64 times the required baud rate. Isosynchronous operation is a special case of asynchronous with the multiplier rate programmed as one
instead of 16 or 64. Note that XI operation is only
valid if the clocks of the receiver and transmitter
are synchronized.
The 8251 USART can transmit the three formats
in half or full duplex mode and is double-buffered
internally (i.e., the software has a complete character time to respond to a service request). Although
the 8251 supporj:s basic' data set control signals
(e.g., DTR and RTS), it does not fully support the
signaling described in EIA-RS-232-C. Examples of
unsupported signals are Carrier petect (CF), Ring
Indicator (CE), and the secondary channel signals.
In some cases an additional. port will be required to
implement these siin,als. The 8251 also does not
interface to the voltage levels reqUired by EIARS-232-C; drivers and receivers must be added to
accomplish this interface.
BLOCK DIAGRAM
A blo<;k diagram of the 8251 is shown in Figure 2.
As can be seen in the ngure, the 8251 consists of
nve major sections which communicate with each
other on an internal data bus. The five sections are
the receiver, transmitter, modem control, read/
write control, and I/O Buffer. In order to facilitate
discussion, the' I/O Buffer has been shown broken
down into' its three' major subsections: the status
buffer, the transmit data/command buffer, and the
receive data buffer. '
Receiver
The receiver accepts serial data on the RxD pin and .
converts it'to parallel data according to the appropriate format. When the 8251 is in the asynchronous mode and, it is ready to accept a character
7-5
EXTERNAL DATA BUS
1--_
TxD
RESET_
CLK_
1 - - - RxRDY
1 - - - - SYNDET
1----fbC
'-_~-L
RECEIVER
' -_ _ RxD
__~IS:~~I__~r,
Figure 2",8251 Block'Diagram
(Le., it is not in the process of receiving a character), it looks for a low level on the RxD line, Whe,n
it sees the low level, it assumes that it isa START
bit and' enables an' intern'al counter,' At a courtt
equivalent to one-half of a bit time, ,the Rxb line is
sampled again, If the' line is still low, a valid
START bit has probably been received and the
8251 proceeds to assemble the chiracter~ If the
"' RxD line is high when it is sampled, then either a
noise pulse' has occurred on the lirie or thtl receiver
has become enabled in the middle 'of the transmission of a character. In either case the receiver
, aborts its operation and prepares itself to accept a
new character. After the successful reception of a
START bit the 8251 clocks in the data, parity, and
STOP 'bits, and 'then transfers the data on 'the
internal data bus to the receive data register: When
operating with less' than' 8 bits, the characters are
right-justified. The RxRDY signal isasseited to
'
indicate that a character is availa1:>le.
In the synchronous mode, t'he receiver, s~mply
clocks in the specified number of data;,pits and
transfers" them to the, receiver buffe,r register,
setting RxRDY. Since the receiver blin"ly groups
data bits into characters, there must be a means of
synchronizing the receiver to the transmitter so
that the proper character boundaries are maintained in, the serial data strellm. This synchronization is achieved in the HUNT'mode,. ' , " ,
In thtl HUNT mode the 8451 shifts in "ata on ;the
Rxi> line one bit at a time. After each bit is received, the receiver register is compared to a register holding the SYN character (program loaded).
If the two registers are not equal, the 8251 shifts in
another bit and repeats the comparison: When the
registers compare as equal, 'the 8,251 ends, the
HUNT mode and raises the SYNDET line to indicate that it has achieved synchronization. If the
USART has been programmed to operate with two
SYN 'characters the process is as described above,
except that two contiguous characters from tlie
line must compare to,the two stored SYN characters before synchronization is declared. Parity is
not checked. If the USART has been programmed
to, ;llccept external synchronization, the SYNDET
pin is,llsed as an input to synchronize the receiver.
The timing necessary to do this is discussed in the
SIGNALS section of this note. The USART enters
the HUNT mode when it is initialized into the
synchronous mode or when it is commanded to do
so by the command instruction. Before the receiver
is operated, it must be enabled by the RxE bit (D2)
of the command instructionsAf this bit is not set
the receiver will not assert the RxRDY bit.
Transmitter '
The transmjtter accepts parallel ;data fro~ the
processol, !ldds the appropriate framing ill formatiol)., serializes it, lIlld ~ran,~mits it 0)1 the TxD pin.
In the asynchronous mode the traIJsmitteralways
7-6
AFN.ooeooA
APPLICATIONS
adds a START bit; depending on how the unit is
programmed, it also adds an optional even or odd
parity bit, and either I, 1*. or 2 STOP bits. In the
synchronous mode no extra bits (other than parity,
if enable) are generated by the transmitter unless
the computer failt to send a character to the
USART. If the USART is ready to'transmit acharacter and a new character has not been supplied by
the computer, the USART will transmit a SYN
character. This is necessary since synchronous
communications, unlike asynchronous communications, does not allow gaps between characters. If'
the USART is operating in the dual SYN mode,
both SYN characters will be transmitted before the
message, can be resumed. The USART will not
generate SYN characters until the software has supplied at Ijlast one character; i.e., the USART will
,fill 'holes' in the transmission but will not initiate
transmission itself. The SYN characters which are
to be transmitted by the USART are specified by
the software during the initialization procedure. In
either the synchronous or asynch'ronous modes,
transmission is inhibited until TxEnable and the
C'i'S input are asserted.
An additional feature of the transmitter is the ability to transmit a BREAK. A BREAK is a period of
continuous SPACE on the communication line and
is used in full duplex communication to interrupt
the transmitting terminal. The 8251 USART will
transmit a BREAK condition as long as bit 3
(SBRK) of the command register is set.
CE
c/o
READ
WRITE
0
0
0
1
CPU Reads Data from
USART
0
1
0
1
CPU Reads Status from
USART
0
0
1
0
CPU Writes Data to
USART
0
1
1
0
CPU Writes Command to
USART
1
X
X
X
USART Bus Floating
(NO-OP)
Function
and WRITE being a zero at the same time is an
illegal state with undefined results. The Read/
Write Control Logic contains s~ltTEnization circuits so that the READ and
I
pulses can
occur at any time with respect to the clock inputs
to the USART.
The I/O buffer contains the STATUS buffer, the
RECEIVE DATA buffer and the XMIT DATA/
CMD buffer as shown in Figure 2. Note that although there are two registers which store data for
transfer to the CPU (STATUS and RECEIVE
DATA), there is only one register which stores data
being transferred to the USART. The sharing of
the input register for both transmit data and commands makes it important to ensure that the
USART does not have data stored in this register
before sending a command to the device. The
TxRDY signal can be monitored to accomplish
this. Neither data nor commands should be transferred to the USART if TxRDY is low. Failure to
perform this check can result in erroneous data
being transmitted.
Modem Control
The modem control section provides for the generation of RTS and the reception of
In addition, a general purpose output and a general purpose input are provided. The output is labeled
DTR and the input is' labeled DSR. DTR can be
asserted by setting bit 2 of the command instruction; DSR can be sensed as bit 7 of the status
register. Although the USART itself attaches no
special significance to these signals, DTR (Data
Terminal Ready) is normally assigned to the
modem, indicating that the terminal is ready to
communicate and DSR (Data Set Ready) is a signal
from the modem indicating that it is ready for
communications.
rn.
INTERFACE SIGNALS
The interface signals of the 8251 USART can be
broken down into two groups - a CPU-related
group and a device-related group. The CPU-related
signals have been designed to optimize the attachment of the 8251 to a MCS-80™ system. The
device-related signals' are intended 'to interface a
modem or like device. Since many peripherals
(TTY, CRT, etc.) can be obtained with a modemlike interface, the USART has a broad range of
applications which do not include a modem. Note
that although the USART provides a logical,interface to an EIA-RS-232 device, it does not provide
EIA compatible drive, and this must be added via
circuitry external to the 8251. As an example of a
peripheral interface application and to aid in
understanding the signal descriptions which 'follow,
Figure 3 shows a system configured to interface
with a TTY or CRT.
I/O Control
The Read/Write Control Logic decodes control
,signals on the' 8080 control bus into signals which
gate data on 'and off the USART's internal bus and
controls the external I/O bus (DBo-DB7). The
truth table for these operations is as follows:
If neith~r READ or WRITE is a zero, then the
USART will not perform an I/O function. READ
7-7
APPLICATIONS
~~~~~~~~-.
.---------------------~
~
.. I
~
~
:>
•
~~
"',
~
;~
~_;;T__;;i'_;:;i__;;i'__---'~ ~I
!
~~
,-;; ~~L~
""-KII--'--'-L-<¥~~
_:;_1'"'
III
~
7-8
APPLICATIONS
CPU-Related Signals
+5 Volt Supply
Vee (26)
I
GND(4) ,
I
+5 Volt Common
The CLK input generates inCLK(20)
ternal device timing. No external inputs or outputs are
referenced to CLK, but the
frequency of CLK must be
greater than 30 times the
Receiver or Transmitter
clock inputs for synchronous
mode or 4.5 times the clock
inputs for an asynchronous
mode. An additional constraint is imposed by the
electrical specifications (ref.
Appendix B) which require
the period of CLK be between 0.42 Ilsec and 1.35
Ilsec. The CLK input can
generally be connected to the
Phase 2 (TTL) output of the
8224 clock generator.
A
high on this input perRESET (21)
forms a master reset on the
8251. The device returns to
the idle mode and will remain there until reinitialized
with the appropriate control
words.
I/O The DB signals form a threeDB7-DBo
state bus which can be con(8,7,6,5,2,1,
28,27)
nected to the CPU data bus.
Control, status, and data are
transferred on this bus. Note
that the CPU always remains
in control of the bus and all
transfers are initiated by it.
CS(lI)
I
Chip Select. A low on this
input enables communication between the USART
and the CPU. Chip Select
should go low when the
USART is being addressed by
'
the CPU.
cti5 (12)
Control/Data. 'During a read
operation this pin selects
either status or data to be input to the CPU (high=status,
low=data). During a write
operation this pin causes the
USART to interpret the data
on the bus as a command if it
is high or as data if it is low.
1m (13)
I
A low on this input causes'
the USART to' gate either
WR (10)
TxRDY (IS)
TxE (18)
RxRDY(14)
7-9
status or data onto the data
bus.
I
A low on this input causes
the USART to accept data
on the data bus as either a
command or as a data char:acter.
0, Transmitter Ready. This output signals the CPU that' the
USART is ready to accept a .
data character or command.
It can be used as an interrupt
to the system or, for polleo
operation, the CPU can
check TxRDY using the
status read operation. Note,
however, that while the
TxRDY status bit will be asserted whenever the XMIT
DATA/CMD buffer is empty,
the TxRDY output will be
asserted only if the buffer is
empty and the USART is enabled to transmit (Le., CTS is
low and TxEN is high).
TxRDY will be reset when
the USART receives a charac-'
ter from the program.
o Transmitter Empty. A high
output on this line indicates
that the parallel to serial
converter, in the transmitter
is empty. In 'the synchronous
mode, if the CPU has failed
to load a new character in
time, TxE will go high momentarily as SYN characters
are loaded into the transmitter to fill the gap in transmission.
o Transmitter Ready. This output goes high to indicate that
the 8251 has received a character on its serial input and is
ready, to. transfer it to the
CPU. Although the receiver
runs continuously, RxRDY
will only be asserted if the
RxE (Receive Enable) bit in
the command register has
been set. RxRDY can be COIlnected to the interrupt stru~
ture or, for polled operation,
the CPU can check the condition of RxRDY using a status
read operation. RxRDY will
,be reset when the character is
read by the CPU.
APPLICATIONS
SYNDET (16) I/O Synch Detect. This line is used
in the,synchronous mode only.
It can be either an input or
output, depending on whether
the initialization program sets
the USART for external or internal synchronization. SYNDET is reset to a zero by RESET. When in the internal
synchronization mode, the
USART uses SYNDET as an
output to indicate that the
device has detected the required SYN character(s}. A
high output indicates synchronization has been achieved. If the USART is programmed to operate with
double SYN characters, SYNDET will go high in the middle of the last bit of the
second SYN character. SYNDET will be reset by a status
read operation. When in the
external synchronization mode
a positive-going input on the
SYNDET line will cause the
8251 to start assembling
characters on the next falling
edge of RxC. The high input
should be maintained at least
for one RxC cycle following
this edge.
CTS (17)
RxC (25)
RxD (3)
TxC (9)
Device-Related Signals
DTR (24)
.0
Data Terminal Ready. This is a
general purpose output signal
which can be set low by programming a ' I' in command
instruction bit I. This signal
allows additional device control.
Data Set Ready. This is a genDSR (22)
eraJpurpose input signal. The
status of this signal can be
tested by the CPU through a
status read. This pin can be
used to test device status and
is read as bjt 7 of the status
register.
RTS (23)
o Request to Send. This is a general purpose output signal
equivalent to DTR. RTS is
normally used to request that
the modem prepare itself to
transmit (i.e., establish carrier). RTS can be asserted
TxD (19)
o
(brought low) by setting bit 5
in the command instruction.
Clear to Send. A low on this
input enables the USART to
transmit data. CTS is normally
generated by the modem in response to a RTS.
Receiver Clock. This clock
controls the data rate of characters to be received by the
USART. In the synchronous
mode RxC is equivalent to the
baud rate, and is supplied by
the modem. In asynchronous
mode RxC is 1, 16, or 64
times the baud rate. The clock
division is preselected by the
mode control instruction.
Data is sampled by tl1e USART
on the rising edge of RxC.
Receiver Data. Characters are
received serially on this pin
and assembled into parallel
characters. RxD is .high .true
(Le., High = MARK or ONE).
Transmitter Clock. This clock
controls the rate at which
characters are transmitted by
the USART. The relationship
- between clock rate and baud
rate is the same as for RxC.
Data is shifted out of the
USART on the falling edge of
TxC.
Transmit Data. Parallel characters sent by the CPU are transmitted serially by the USART
on this line. TxD is high true
(Le., High = MARK or ONE).
MODE SELECTION
The 8251 USART is capable of operating in a number of modes (e.g., synchronous or asynchronous).
In order to keep the hardware as flexible as possible (both at the chip and end product level), these
operating modes are selected via a series of control
outputs to the USART. These mode control outputs must occur between the time the USART is
reset and the time it is utilized for data transfer.
Since the USART needs this information to structure its internal logic it is essential to complete the
initialization before any attempts are made at data
transfer (including reading status).
A flow.chart of the initialization process appears in
Figure 4. The first operation which must occur
following a reset is the loading of the mode control
7-10
APPLICATIONS
SYSTEM RESET
INITIALIZATION
-~--L ~
. .,-
00 "SVN MODE
•
01-ASYNXl
10-ASVNX16
11.ASYNX64
CHARACTER LENGTH
00 -S8ITS
01·6BITS
10 ... 7811S
11 -8 BITS
PARITY CONTROL
X 0 .. NO PARITY
01 ... 000 PARITY
1 1 ... EVEN PARITY
FRAMING CONTROL
SVN
NO - ASVN (0, 00'*00)
00 "NOTVALID
01·1STOPBIT
?
1 D .1~ STOP BITS
11 "2STOPBITS
VES
(0100"'01
SVNCONTROL
x0
INTERNAL SVN
EXTERNAL SYN
DOUBLE SVN CHAR
, X SINGLE SVN CHAR
X,
oX
\ Figure 5. Mode Instruction Format
The last field, 07-D6, has two meanings, depending on whether operation is to be in the synchronous or asynchronous mode. For the asynchronous
mode (i.e., OJ Do 00), it controls the. number of
STOP bits to be transmitted with the character.
Since the receiver will always operate with only
one STOP"bit, 07 and 06 only control the transmitter. In the .synchronous mode (OJ Do = 00),
this field controls the synchronizing process. Note
that the choice of single or double SYN characters
is independent of the choice of internal or external
synchronization. This is because even though the
receiver may operate with external synchronization
logic, the transmitter must still know whether to
send one or two SYN characters should the CPU
fail to supply a character in time.
Following the loading of the mode instruction the
appropriate SYN character (or characters) must be
loaded if synchronous mode has been specified.
The SYN character(s) are loaded by the same control output instruction used to load the mode instruction. The USART determines from the. mode
instruction whether no, one, or two SYN characters are required and uses the control output to
load SYN characters until the required number are
loaded.
At completion of the load of SYN characters (or
after the mode instruction in the asynchronous
mode), a command character is issued to the
USART. The command instruction controls the
operation of the USART within the basic framework established by the mode instruction. The
format of the command instruction is shown in
'*
Figure 4. Initialization Flowchart
register. The mode control register is loaded by the
first control output (<;/D=l, lID=l, WR=O, C:S=(}f
following a reset. The format of the mode control
instruction is shown in Figure 5. The instruction
can be considered as four 2-bit fields. The first
2-bit field (DI 00) determines whether the USART
is to operate in the synchronous (00) or asynchronous mode. In the asynchronous mode this field
also controls the clock scaling factor. As. an example, if 01 and 00 are both ones, the RxC and TxC
will be divided by 64 to establish the baud rate.
The second field, 03-D2, determines the number
of data bits in the character and the third, 05-D4,
controls parity generation. Note that the parity bit
(if enabled) is added to the data bits and is not
considered as part of them when setting up the
character length. As an example, standard ASCII
transmission, which is seven data bits plus even
parity, would be specified as:
XXIIIOXX
7-11
APPLICATIONS
Figure 6. Note that if, as an eXllll1ple, the USART
is waiting for a SYN character load and instead is
issued an internal reset command, it will accept thll
command as a SYN character instead of resetting.
This situation, which should only occur if two
independent programs control the USART, can be
avoided by outputting three all zero characters as
commands before issuing the internal reset command. The USART indicates its state in a status
regist,er which can be read under program control.
The format of the status register read is shown in
Figure 7.
When operating the receiver it is important to realize that RxE (bit 2 of the command instruction)
only inhibits the assertion of RxRDY; it does not
inhibit the actual reception of characters. Because
the receiver is constantly running, it is possible for
it to contain extraneous data when it is enabled.
To avoid problems this data should be read from
the USART and discarded. The read should be
done immediately following the setting of Receive
Enable in the asynchronous mode, and following
the setting of ,Enter Hunt in the synchronous
mode. It is not necessary to wait for RxRDY before executing the dummy read.
TRANSMIT ENABLE
'-ENABLE
O-DISABLE
DATA TERMINAL
READY
"HIGH"WILL FORCE
DTR OUTPUT TO ZERO
SEND BREAK
L . - - - - - - I CHf!:g~~:STXD "LOW"
0 ... NORMAL OPERATION
L.-------J
L._ _ _ _ _ _ _ _·I
ERROR RESET
1" RESET ALL ERROR
FLAGS (PE. DE, FE)
REQUEST TO SEND
~~~,;~f~~~~o
INTERNAL FlESET
"HIGH" RETURNS 8261
TO MODE INSTRUCTION
FORMAT
'------------_1
ENTER HUNT MODE
1" ENABLE SEARCH FOR
SYN CHARACTERS
Figure 6. Command Instruction
0,
D.
I
OSR
I
I
SYNDE;
j
I
FE
For~t
I
DE
PE
I
I
TxE
j
I
RxRDV
I
j
TxRDV
j
j
PARITY ERROR
THE PE FLAT IS SET WHEN
I
SAME DEFINITIONS
AS I/O PINS EXCEPT
THAT TxRDY IS NOT
CONDITIONED BY
TxENOR eTI'
A PARITY ERROR IS DE·
TECTED. IT IS RESET BY
THE EA BIT OF THE COM·
MAND INSTRUCTION. PE
DOES NOT INHIBIT OPERA
ATION OF THE 8251.
OV,ERRUN ERROR
THE OE FLAG IS SET WHEN
THE CPU DOES NOT READ A
-
~~~~~~~E;E~~E~EA~~~L.
ABLE. IT IS RESET BY THE
ER BIT OF THE COMMAND
INSTRUCTION OE DOES
NOT INHIBIT OPERATION OF
THE 8251, HOWEVER, THE
PREVIOUSLY OVERRUN
CHARACTER IS LOST'
FRAMING ERROR (:'SYNC
ONLY)
THE FE FLAG 1$ SET WHEN
A VALID STOP BIT IS NOT
DEtECTED AT THE END OF
EVERY CHARACTER. IT IS
,RESET BY THE EA BIT OF
THE COMMAND INSTRUC'nON. FE DOES NOT INHIBIT
THE OPERATION OF THE 8251.
'Figure 7. Status Register Format
AFN.ooeooA
APPLICATIONS
Received
Data
PROCESSOR DATA UNK
The ability to change the operating mode of the
USART by software makes the 8251 an ideal
device to use to implement a serial communication
link. A terminal initially configured with a simple
asynchronous protocol can be upgraded to a synchronous protocol such as IBM Binary Synchronous Communication by a software only upgrade.
In order to demonstrate the use of the 8251
USART, the remainder of this document will
describe the implementation of an interrupt-driven,
full duplex communication link on the Intel
MDSTM system. With minor modifications, the
program developed could be used on the Intel
SBC-80110™ OEM card, thus implementing a data
link between the two systems. Such a facility can
be used to down-load programs, run diagnostics,
and maintain common data bases in multiprocessor
systems.
.
The factors which must be considered in the design
of such a link include the desired transmission rate
and format, the error checking requirements, the
desirability of full duplex operation, and the physical implementation of the link. The basic requirement of the system described here is that it allow
an Intel SBC-80/10 OEM card to be loaded from
an MDS development system, either locally or on
the switc4ed telephone network. An additional
constraint is that the modem used on the switched
network be readily available and inexpensive.
These requirements led to the choice of a modem
such as the Bell 103A to implement the link. These
modems, which support full duplex communication at up to 300 baud, are readily available from a
number of sources at reasonable cost. These
modems are also available in acoustically coupled
versions which do not require permanent installation on the telephone network. Interface to the
103A modem is accomplished with nine wires:
Protective Ground, Signal Ground, Transmitted
Data, Received Data, Clear to Send, Data Set
Ready, Data Terminal Ready, Carrier Detector,
and Ringing Indicator.
The utilization of the interface signals to the
modem is as follows:
Protective
Protective Ground is used to bond
Ground
the chassis ground of the modem to
that of the terminal.
Clear to
Send
Data Set
Ready
Data
Terminal
Ready
Carrier
Detector
Ringing
Indicator
A block diagram showing the connections between
the MDS and the SBC-80/10 through the modems
is shown in Figure 8. Figure 9-shows the portion of
the MDS monitor board devoted to the USARTs
and Figure 10 shows the equiv~ent section of the
SBC-sO/IO board. Note that several signals on the
MDS to not have the proper EIA deimed voltage
levels, . and for this reason the adapter shown in
Figure 11 was added to the MDS. The 390 pF
capacitor was added to the 1488 driver to bring the
rise time within EIA imposed limits of 30 voltsl
It8ec. In Figure 7 the signal labels within the MDS
and SBC-80/10 blocks correspond to the labels on
the schematics, the signal labels within the modem .
blocks correspond to EIA conventions, and the
signal labels on the wires between the bl9Cks are
abbreviations for the English language names of the
signals.
As an example of how the USART clocks can be
generated, circuits· A27, Al6, and A15 of Figure 9
form divider of the OSC signal. The OSC Signal
hils -Ii frequency of 18.432 MHz and is generated by
the 8224 which generates system timing for the
8080A. The 18.432 MHz signal results in a state
time of 488 ns versus the normal 500 ns for the
8080A. (This does not violate 8080A specifications.) The 18.432 MHz signal can be divided by
a
Signal
Ground
Signal. Ground provides a common
ground reference between the modem and the terminal. -
Transmitted
Data
Transmitted Data is used to transfer
serial data from the terminal to the .
modem.
7-13
Received Data is used to transfer
serial data from the modem to the
terminal.
Oear to Send indicates that the
modem has established a connection with a remote modem and is
ready to transmit data.
Data Set Ready indicates that the
modem is connected to the telephone line and is in the data mode.
Data Terminal Ready is a signal
from the terminal which permits
the modem to enter the data mode.
Carrier Detector is identical to
Oear to Send in the 103 modem
and will not be used in this interface.
Ringffig Indicator indicates that the
modem is receiving a ringing signal
from the telephone -system. This
signal will not be used in the interface, since it is possible for the
terminal to assert Data Terminal
Ready whenever it is ready for the
modem to "answer the telephone".
The modem uses Data Set Ready to
indicate that it has answered the
call.
APPLICATIONS
--------l
,
r------,--
I
I
CB'
CRT USART RTSI
CT8
CRTTxDATA
'
REQTOSEND
RECEIVE DATA
"
TRANSMITTED DATA
CRTRxDATA/
CRTDTR/
DATASET ROY
: CRT DSRI
DATA TERM'L ROY
CRTSIGGND
OND
'CRr INTERFACE
_____ ~
I
_ _ ...J
IL _
, ______ _
SBC ••
Figure 8. System Block Diagram
Before the software design of the system could be
undertaken, it was necessary to decide whether
service requests from the USART would be handled on a polled. or i,nterrupt driven mode. Polled
operation normally results in more compact code
but it requires that whatever programs are running
concurrently with a transmission or reception must
periodically either check the status of the USART
or call a routine tliat does. Since it was not possible
to determine what program might be running during a receive or transmit operation, it was decided
to operate in an interrupt driven mode.
The' program which operates the 8251 must be
instructed as to what data it should. transmit or
receive from some other program resident in the
8080 system. To facilitate the discussion of the
operation of the software, the following definitions
will be made:
'
USRUN is the program which controls the
operation of the 8251.
, USER is a program which utilizes USRUN in
order to effect a data transmission.
USER passes commands and parameters' to
USRUN by means of the control block shown in
Figure 12. The first byte of the block contains the
command' which USER wants USRUN to execute.
Valid contents of this byte are "C" which causes
USRUN to initialize itself and the 8251, "R"
which causes the execution of the data input (or
READ) operation, and "W" which causes a data
output (WRITE) operation. The second byte of the
control. block is used by USRUN to inform USER
of the status of the requested operation. The third
and fourth bytes specify the' starting address of a
buffer set up by USER which contains the data for
a transmit operation or which will be used by
USRUN to store received data. The fifth and sixth
bytes are concatenated to form a positive binary
Figure 9. EIA Adapter
30 and then 64 to give a 9600 baud communication standard. The 9600 baud signal can be further
divided to give 4800, 2400, 1200, 600, and 300
baud signals. The 1200 baud signal can be divided
by 11 to give a 109.1 baud signal which is within
1% of the 110 baud standard signal rate. Note that
because of constraints on the CLK iriput 9600
baud operation is not possible in th<:; X64 mode.
The divide by 64 can be accompiished by dividing
by 4 with a counter and then 16 within the
USART.
In order to keep the system as general purpose as
possible, it was decided to transmit 8-bit data characters with an appended odd parity bit. Having a
full 8-bit byte available for data enables the transmission of codes such as ASCII (which is ,7-level
with an additional parity bit) to be transmitted'
and received transparently in the system. Also, of
course, it allows 8-bit bytes from the 8080A memory to be transferred in pne transmission character.
If error checking beyond the parity check is required, it could be added to the data record to be
transmitted in the form of redundant check characters.
7-14
i"tSOO
'4$QO
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Lpn~TV:: ~~,
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-
Figure 11. MDS Monitor Module
~
""
1"Zta .........
ST"..
""I 1"Z>ll ....... ,,""""""
TTY OUT IUT/!Z:rdl
~ ~"'''''CKT'
,f'HI .............~....
~ecM1tD!'TPfI{fI
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(5
Z
tn
APPLICATIONS
number which specifies how many bytes of data
USER wants transferred. The seventh and eighth
bytes are concatenated and used by USRUN to
count the number of bytes that have been transferred. When the required number of characters
have been transferred, or if USRUN terminates a
READ or WRITE due to an abnormal condition,
then USRUN calls a subroutine at an address defined by the ninth and tenth bytes of the command block. This subroutine, which is provided by
USER, must determine the state of the process and
then take appropriate action.
COMMAND
STATUS
BAD LOl'
8ADHIGH
RCTLOW
RCTHIGH
CCTLOW
CCTHIGH
eRA LOW
CRAHIGH
)
THESE TWO BYTES FORM
THE BUFFER ADDRESS
THESE TWO BYTES INDICATE
) THE NUMBER OF BYTES TO
BE TRANSFERRED
THESE TWO BYTES INDtCATE
THE NUMBER OF BYTES THAT
!
HAVE BEEN TRANSFERRED
THESE TWO BVTES FORM
THE ADDRESS OF A SUBROUTINE TO BE CAllED
. WHEN THE OPERATION
IS TERr.1I'NATED
Figure 12. Control Block
Since USRUN must be capable of operation in a
full duplex mode (i.e., be able to receive and transmit simultaneously), it keeps the address of two
control blocks; one for a READ operation and one
for a WRITE. The address of the controlling command block is kept in RAM locations labeled
RCBA for the READ operation and TCBA for the
WRITE operation. If RCBA (Receive Control
Block Address) or TCBA (Transmit Control Block
Address) is zero, it indicates that the correspon,ding
operation is in an idle status.
Flowcharts of USRUN appear in Figure 13 and the
listings' appear in Figure 14. The first section of the
flowcharts (Figures 13.1 and 13.2) consists of two
subroutines which are used as convenient tools for,
operating on the control blocks. These routines are
labeled LOADA and CLEAN. LOADA is entered
with the address of a control block in registers H
and L. Upon return registers D and E have been set
equal to the address in the buffer which is the
target of the next data transfer (i.e., D,E = BAD+
CCT); and CCT (transferred byte count) has then
been incremented. In addition, the B register is set
to zero if the number of bytes that have been
transferred is equal to the number requested (i.e., '
CCT = RCT). CLEAN, the second routine, is also
entered with the address of a command block in
the :tI and L registers. In addition, the Accumulator
holds the status which will be placed in the
STATUS byte of the command block. On exit the
STATUS byte has been updated and the address of
the completion routine has been placed in H and L.
'Figure 13.1. LOADA Subroutine
Upon interrupt, control of the MCS-80 system is
transferred to VECTOR (Figure 13.3). Vector is a
program which saves the state of the system, gets
the status of the USART and jumps to the RISR
(Receive Interrupt Service Routine) or the TISR
(Transmit Interrupt Service Routine), depending
on which of the two ready flags is active. If neither
ready flag is active, VECTOR restores the status of
• the run,ning program, enables interrupts, and returns. (Interrupts are automatically disabled by the
hardware upon an interrupt.) This exit from VECTOR, which is labeled VOUT, is used from other
Figure 13.2. CLEAN Subroutine
7-17
APPLICATIONS
portions of US RUN if return from the interrupt
mode is required .
tn addition to handling normal data transfers,
TISR (Figure 13.4) checks a location in memory
named TCMD in order to dete1ll,line if the receive
program wishes to send a command to 'the USART.
Since the transmit data and command must share a
buffer within the USART, any command output
must occur when TxRDY is asserted. If TCMD is
zero, TISR proceeds with the data transfer. If
TCMD is non-zero, TISR calls TUTE (Transmit
Utility, Figure 13.5) which, depending on the value
•NT
Figure 13.3. Interrupt Entry
Figure 13.4.. Transmitfnterrupt Service ReIItin.
Figura 13.5. Trans",it Utility Routine
7-18
AFN-006OOA
APPLICATIONS
in TCMD, turns off the receiver, turns on the receiver, or clears error conditions. Note that the
error flags (parity, framing, and overrun) are always cleared by the software when the receiver is
first enabled.
The flowchart of the RISR is shown in Figure
13.6. Note that in addition to terminating whenever the required number of characters have been
received, the RISR also terminates if one of the
error flags becomes set or if the received character
matches a character found in a table pointed to by
the label ETAB. This table, which starts at ETAB
and continues until an all "ones" entry is found,
can be used by USER to define special characters,
such as EOT (End Of Transmission), which will ter- .
minate a READ operation. The remainder of Figure 13 (13.7) shows the decoding of the commands
to USRUN. The listings also include a test USER
which exercises USRUN. This program sets up a
256-byte transmit buffer and transfers it to a similar input buffer by means of a local loop. When
both the READ and WRITE operations are complete, the test USER checks to )insure that the two
buffers are identical. If the bufters differ, the MDS
monitor is called; if the data is correct, the test is
repeated.
CONCLUSION
The 8251 USART has been described both as a
device and as a component in a system. Since not
only modems but also many peripheral devices
have a serial interface, the 8251 is an extremely
useful component in a microcomputer system. A
particular advantage of the device is thafit is capable of operating in various modes without requiring hardware modifications to the system of which
it is a part. As with any complex subsystem, however, the 8251 USART must be carefully applied
so that it can be utilized to full advantage in the
overall system. It is hoped that this application'
note will aid in the designer in the application of
the 8251 USART. As a further aid to the application of the 8251, the appendix of this document
includes a list of design hints based on past experience with the 8251.
Figure 13.6. Receive Interrupt Service Routine
7-19
APPLICATIONS
NO
Figure 13.7. URUN Command Decode
7-20
AFN-ooeooA
APPLICATIONS
Figure 14. Program Listing
,••••••
j
SYSTEM ORIGIN STATEMENT
j •••••
4000
ORG
4000H
,••••••
DATA STORAGE FOR TEST USER
j
,••••••
4000
4100
4200
4202
4204
4206
4208
420A
420C
420E
4210
4212
4214
4216
5200
0040
FFOO
0000
1742
5700
0041
FFOO
0000
2742
4300
00
BUFIN:
BUFOUT:
RBLOCK:
RBAD:
RRCT:
RCCT:
RCRA:
TBLOCK:
TBAD:
TRCT:
TCCT:
TCRA:
GBLOCK:
FLAG:
DS
DS
DB
DW
DW
DW
DW
DB
DW
DW
DW
DW
DB
DB
100H
100H
'R' ,OOH
BUFIN
OFFH
OOH
RCR
'w' ,OOH
BUFOUT
OFFH
OOH
TCR
'c' ,OOH
OOH
jINPUT BUFFER
jOUTPUT BUFFER
jftECEIVE CONTROL BLOCK
jTRANSMIT CONTROL BLOCK
;*****
COMPLETION ROUTINES
j
.•••
,
**
4217
4218
421B
421E
4221
4223
4226
4227
4'228
422B
422E
4231
4233
4236
AF
323B42
323C42
3A1642
E60F
321642
C9
AF
323942
323A42
3A1642
E6FO
321642
C9
RCR:
TCR:
XRA
STA
STA
LDA
ANI
STA
RET
XRA
STA
STA
LDA
ANI
STA
RET
A
RCBA
RCBA+1
FLAG
OFH
FLAG
A
TCBA
TCBA+1
FLAG
OFOH
FLAG
jCLEAR A
jTURN OFF RECEIVE
jGET FLAG
jCLEAR UPPER FOUR BITS
jRESTORE FLAG
;CLEAR A
jTURN OFF TRANSMIT
jGET FLAG
jCLEAR LOWER FOUR BITS
jRESTORE FLAG
jTHEN RETURN
7-21
APPLICATIONS
.
.*****
SYSTEM EQUATES
;
;*****
00F5
00F5
00F4
00F4
0000
DOFF
0001
USTAT
USCMD
USDAI
USDAO
GSTAT
BSTAT
CEND
EQU
EQU
EQU
EQU
EQU
EQU
EQU
OF5H
OF5H
OF4H
OF4H
DOH
OFFH
01H
;USART STATUS ADDRESS
;USART CMD ADDRESS
;USART DATA INPUT ADDRESS
;USART DATA OUTPUT ADDRESS
;GOOD STATUS
;BAD STATUS
;*****
.
SYSTEM DATA TABLE
;
.*****
4237
4238
4239
423B
·423D
00
00
0000
0000
FF
LCMD
TCMD
TCBA
ReBA
MTAB
DB
DB
DW
DW
DB
OOH
DOH
OOH
OOH
OFFH
;CURRENT OPERATING COMMAND
;IF NON ZERO A COMMAND TO BE SENT
;ADDRESS OF XMIT CBLOCK
;ADDRESS OF RECEIVE CBLOCK
;END CHARACTER TABLE
7-22
AFN-ooeooA
APPLICATIONS
j • • **.
LOAD ADDRESS ROUTINE
LOADA IS ENTERED WITH THE ADDRESS OF A CONTROL
BLOCK ~N H,L. ON EXIT D,E CONTAINS THE ADDRESS
WHICH IS THE TARGET OF THE NEXT DATA TRANSFER (BAD+CCNT)
AND B HAS BEEN SET TO ZERO IF THE REQUESTED NUMBER OF
TRANSFERS HAS BEEN ACCOMPLISHED. CCNT IS INCREMENTED
AFTER THE TARGET ADDRESS HAS BEEN CALCULATED.
j
j**.*.
423E
423F
lj240
4241
4242
4243
4244
4245
4246
4247
4248
4249
424A
424B
424C
424D
424E
424F
4250
4251
4252
4253
4254
4255
4256
4257
4258
4259
425A
23
23
5E
23
56
23
23
23
4E
23
46
EB
09
EB
03
70
2B
71
OB
2B
7E
go
47
CO
2B
7E
91
47
C9
LOADA:
INX
INX
MOV
INX
MOV
INX
INX
INX
MOV
INX
MOV
XCHG
DAD
XCHG
INX
MOV
DCX
MOV
DCX
DCX
MOV
SUB
MOV
RNZ
DCX
MOV
SUB
MOV
RET
H
H
E,M
H
D,M
H
H
H
C,M
H
B,M
jD,E GETS
BUFF~R
ADDRESS
jDONE
jB,C GETS COMPLETED COUNT (CCNT)
jDONE
jD,E GETS BAD+CCNT
B
B
M,B
H
M,C
B
H
A,M
B
B,A
jDONE
jCCNT GETS INCREMENTED
jDONE
JDOES OLD CCNT=RCNT?
JNO-RETURN WITH B NOT ZERO
H
A,M
C
B,A
jRETURN WITH B=O IF RCNT=CCNT
7-23
APPLICATIONS
,.*****
CLEAN-UP ROUTINE.
CLEAN IS ENTERED WITH THE ADDRESS OF A CONTROL
BLOCK IN H,L AND A NEW STATUS TO BE
ENTERED INTO IT IN A. ON EXIT THE ADDRESS OF THE
CONTROL JLOCK IS IN D,E; THE STATUS OF THE BLOCK
HAS BEEN UPDATED; AND THE ADDRESS OF THE COMPLETION
ROUTlNE IS IN H,L.
;
;*****
425B
425C
425D
425E
425F
4262
4263
4264
4265
4266
4267
5D
54
23
77
010700
09
7E
23
66
6F
C9
CLEAN:
HOV
MOV
INX
MOV
LXI
DAD
MOV
INX
MOV
MOV
RET
E,L
D,H
H
M,A
B,7
B
A,M
H
H,M
L,A
jSAVE THE ADRESS OF THE COMMAND BLOCK
jPOINT AT STATUS
jSET STATUS EQUAL TO A
iSET INDEX TO SEVEN
;POINT AT COMPLETION ADDRESS
jGET LOWER ADDRESS
jPOINT AT UPPER ADDRESS
jH GETS HIGH ADDRESS BYTE
jL GETS LOW ADDRESS BYTE
,.**.*.
,
INTERUPT VECTOR ROUTINE
VECTOR SAVES THE STATUS OF THE RUNNING PROGRAM
THEN READS THE STATUS OF THE USART TO DETERMINE
IF A RECEIVE OR TRANSMIT INTERUPT OCCURRED.
VECTOR THEN CALLS THE APPROPRIATE SERVICE ROUTINE.
IF NEITHER INTERUPTS OCCURRED THEN VECTOR RESTORES
THE STATUS OF THE RUNNING PROGAM. THE SERVICE
ROUTINES USE THE EXIT CODE"LABLED VOUT, TO EFFECT
THEIR EXIT FROM INTERUPT MODE.
;*****
4268
4269
426A
426B
426C
. 426E
4270
4271
4272
4275
4276
4277
427A
427C
427E
427F
4280
4281
4283
4286
4287
F5
C5
D5
E5
DBF5
DBFA
OF
OF
DA8842
07
07
DAD442
3EFC
D3F3
El
D1
C1
3E20
D3FD
FB
C9
VECTOR: PUSH
PUSH
PUSH
PUSH
IN
IN
RRC
RRC
JC
RLC
RLC
JC
MVI
OUT
VOUT:
POP
,POP
POP
MVI
OUT
EI
RET
PSW
B
D
H
USTAT
OFAH
RISR
TISR
A,OFCH
OF3H
H
D
B
A,20H
OFDH
jPUSH STATUS INTO THE STACK
jGET USART ADDRESS
jMDS-GET MONITOR CARD INT. STAtUS
JROTATE TWO PLACES
JSO THAT CARRY=RXRDY
;IF RXRDY GO TO SERVICE ROUTINE
jIF NOT ROTATE BACK
jLEAVING TXRDY IN CARRY
jIF TXRDY THEN GO TO SERVICE ROUTINE
jMDS-CLEAR OTHER LEVEL THREE INTERUPTS
;MDS
jELSE EXIT FROM INTERUPT MODE
jMDS-RESTORE CURRENT LEVEL
jMDS
jENABLE INTERUPTS
7-24
APPLICATIONS
,••••••
j
,
••••••
4288
428B
428D
428F
4290
4291
4294
4295
4296
4299
429C
429E
429F
42AO
42A2
42A4
42A7
42A8
42A9
42AC
42AE
42B1
42B2
42B5
42B8
2A3B42
3E82
D3F3
2C,
2D
C29942
24
25
CA7E42
CD3E42
DBF4
12
4F
DBF5
E638
C2B942
04
05
C2BE42
3EOO
217E42
E5
2A3B42
CD5B42
E9
RISR:
42B9
42BB
42BE
42C1
42C2
42C4
42C7
42C8
42CB
42CC
42CF
42D1
3EFF
C3AE42
213D42
7E
FEFF
CA7E42
B9
CACF42
23
C3C142
3E01
C3AE42
RISRE:
RISRB:
RISRA:
RECEIVE INTERUPT SERVICE ROUTINEj
RISR PROCESSES A RECEIVE INTERUPT
AT THE END OF RECEIVE THE USER SUPPLIED
COMPLETION ROUTINE IS CALLED AND THEN AN
EXIT IS TAKEN THROUGH VOUT OF THE
VECTOR
LHLD
MVI
OUT
INR
DCR
JNZ
INR
DCR
JZCALL
IN
STAX
MOV
IN
ANI
JNZ
INR
DCR
JNZ
MVI
LXI
PUSH
LHLD
CALL
PCHL
MVI
JMP
EXCHAR: LXI
EXA:
MOV
CPI
JZ
CMP
JZ
INX
JMP
PEND:
MVI
JMP
RCBA
A,82H
OF3H
L
L
RISRB
H
H
VOUT
LOADA
USDAI
D
C,A
USTAT
38H
RISRE
B
B
EXCHAR
A,GSTAT
H,VOUT
H
RCBA
CLEAN
jMDS-CLEAR RECEIVE INTERUPT
jMDS
jREADY-SET UP ADDRESS
jGET INPUT DATA
jAND PUT IN THE BUFFER
jSAVE INPUT DATA IN C
jGET STATUS AGAIN
jMASK FOR ERROR FIELD
JNOT ZERO-TAKE ERROR EXIT
jB WAS 00 IF DONE
JNOT DONE-EXIT
jA GETS GOOD STATUS
jGET RETURN ADDRESS
jAND PUSH IT INTO THE STACK
jPOIN~ H,L AT THE CMD BLOCK
jCALL CLEANUP ROUTINE
jEFFECTIVELY CALLS COMPLETION ROUTINE
jRETURN IS TO VOU~ BECAUSE OF PUSH H
A,BSTAT jA GETS BAD STATUS
jOTHERWISE EXIT IS NORMAL
RISRA
H,MTAB _ JTEST CHARACTER AGAINST EXIT TABLE
A,M
OFFH
jEND OF TABLE
VOUT
C
PEND
jMATCH-TERMINATE READ
H
EXA
A,CEND
RISRA
7-25
AFN-00600A
APPLICATIONS
,.****11
TRANSMIT INTERUPT SERVICE ROUTINE
TISR PROCCESSES TRANSMITTER INTERUPTS
WHEN THE END OF A TRANSMISSION IS
DETECTED THE USER SUPPLIED COMPLETION
ROUTINE IS CALLED AND THEN AN EXIT IS
TAKEN THROUGH VOUT OF VECTOR
j
j****11
42D4
42D7
42D8
42DB
42DD
42DF
42E2
42E3
42E4
42E7
42E8
42E9
42EC
42EF
42FO
42F2
42F3
42F4
42F7
42FA
42FB
42FD
4300
4303
3A3842
B7
C40443
3E81
D3F3
2A3942
2C
2D
C2EC42
24
25
CA7E42
CD3E42
lA
D3F4
04
05
C27E42
217E42
E5
3EOO
2A3942
CD5B42
E9
TISR:
4304
4306
4309
430B
430E
4310
4313
4314
4317
4319
431C
431F
4321
4323
4324
4327
4329
432C
FEO 1
CA2443
FE02
CA1443
FE03
CA1C43
C9
3A3742
F604
323742
3A3742
F610
D3F5
C9
3A3742
E6FB
323742
C32143
TUTE:
TISRA:
TUTE2:
TUTE3:
TUTE4:
TUTEl :
LDA
ORA
CNZ
MVI
OUT
LHLD
INR
DCR
JNZ
INR.
Dq
JZ
CALL
LDAX
OUT
INR
DCR
JNZ
LXI
PUSH
MVI
LHLD
CALL
PCHL
TCMD
A
TUTE
A,081H
OF3H
TCBA
L
L
TISRA
H
H
VOUT
LOADA
D
USDAO
B
B
VOUT
H,VOUT
H
A,GSTAT
TCBA
CLEAN
CPI
JZ
CPI
JZ
CPI
JZ
RET
LDA
ORI
STA
LDA
ORI
OUT
RET
LDA
ANI
STA
JMP
01
TUTEl
02
TUTE2
03
TUTE3
jGET POTENTIAL COMMAND
jDESIGNATE ON IT
JDO UTILITY COMMAND
jMDS-CLEAR XMIT INTERUPTS
jMDS
jMAKE SURE HAVE VALID CONTROL BLOCK
jGOOD
JNON VALID BLOCK (H,L=O)
jSET UP ADDRESS
jGET DATA FROM BUFFER
jAND OUTPUT IT
jB WAS 00 IF DONE
JNOT DONE-EXIT FROM SERVICE ROUTINE
jSET UP RETURN ADDRESS
jAND PUSH IT INTO THE STACK.
jA GETS GOOD STATUS
jPOINT H,LAT COMMAND BLOCK
jCALL CLEANUP ROUTINE
jCALL COMPLETION ROUTINE
jRETURN WILL BE TO VOUT
jRECEIVER OFF
jRECEIVER ON
jCLEAR ERRORS
LCMD
04
LCMD
LCMD
10H
USCMD
LCMD
OFBH
LCMD
TUTE4
7-26
APPLICATIONS
,.*****
USART COMMAND BLOCK INTERPRETER
USRUN IS CALLED BY USER WITH THE ADDRESS
OF THE COMMAND BLOCK IN H,L. USRUN EXAMINES
THE BLOCK AND INTIALIZES THE REQUESTED OPERATION
j
j*****
432F
4330
4332
4335
4337
433A
433C
433 F
4340
4341
4342
4344
4346
4348
434A
434C
1A
FE43
CA4043
FE52
CA5D43
FE57
CA9D43
F3
AF
D3F5
D3F5
D3F5
3E40
D3F5
3E5E
434E
4350
4351
4354
4355
4356
4357
4358
4359
435A
4356
435C
D3F5
AF
213942
77
23
77
23
77
23
77
F6
C9
435D
4360
4361
4362
4365
4366
4367
4368
4366
436D
4370
4311
4372
4375
4376
213642
7E
67
C26B43
23
7E
67
CA7743
3EFE
217643
E5
EB
CD5B42
E9
C9
4317
4318
437B
437E
4380
4383
EB
223B42
3A3742
F616
323142
OF
cg
USRUN:
LDAX
CPI
JZ
CPI
JZ
9 PI
JZ
RET
UCLEAR: DI
XRA
OUT
OUT
OUT
MVI
OUT
MVI
OUT
XRA
LXI
MOV
INX
MOV
INX
MOV
INX
MOV
EI
RET
UREAD:
UROUT:
URDB:
URDA:
LXI
MOV
ORA
JNZ
INX
MOV
ORA
JZ
MVI
LXI
PUSH
XCHG
CALL
PCHL
RET
XCHG
SHLD
LDA
ORI
STA
RRC
D
'c'
UCLEAR
'R'
UREAD
'w'
UWRITE
A
USCMD
USCMD
USCMD
A,40H
USCMD
A,05EH
USCMD
A
H, TCBA
M,A
JGET THE CMD FROM THE BLOCK
JIS IT A CLEAR COMMAND?
jYES GO TO CLEAR ROUTINE
JIS IT A READ COMMAND?
jYES-GO TO READ ROUTINE
JIS IT A WRITE COMMAND?
JGO TO WRITE ROUTINE
JNOT A GOOD COMM~ND-RETURN
jDISABLE INTERUPTS
jCLEAR A
jOUTPUT THREE TIMES TO ENSURE
jTHAT THE USART IS IN A KNOWN STATE
jCODE TO RESET USART
jOUTPUT ON CMU CHANNEL
JCE IMPLIES ASYN MODE (X16)
8 DATA BITS
ODD PARITY
1 STOP BIT
jOUTPUT ON CMD CHANNEL
jCLEAR A, SET ZERO
;CLEAR TCBA AND RCBA
H
M,A
H
M,A
H
M,A
jENABLE INTERUPTS
jAND RETURN TO USER
H,RCBA
A.M
jCHECK READ IDLE
A
UROUT
H
A, M •
A
URDA
-A,OFEH
H', URDB
H
CLEAN
RCBA
LCMD
16H
L'CMD
;READ IS IDLE-PROCEDE
jALREADY RUNNING-ERROR STATUS
jSET UP RETURN ADDRESS
jPUSH IT INTO STACK
jH GETS COMMAND BLOCK ADDRESS
jCALL CLEANUP ROUTINE
jEFFECTIVELY CALLS END ROUTINE ..
jRETURN TO USER
;H GETS COMMAND BLOCK ADDRESS
jRCBA GETS COMMAND BLOCK ADDRESS
JGET LAST COMMAND
jSET RXE AND DTR AND RESET ERRORS
jAND RETURN TO MEMORY
jSET CARRY EQUAL TO TXE
7-27
AFN-006OOA
APPLICATIONS
4384
4387
4389
438C
438D
438F
4391
4393
4395
4397
4399
439B
439C
D28C43
3E02
323842
07
D3F5
DBF4
DBF4
3E82
D3F3
3EF6
D3FC
FB
C9
439D
43AO
43A1
43A2
43A5
43A6
43A7
43AA
43AB
43AE
43B1
43B3
43B6
43B8
43BA
43BC
43BD
213942
7E
B7
C26B43
23
7E
C26B43
EB
223942
3A3742
F623
323742
D3F5
3EF6
D3FC
FB
C9
URDC:
JNC
MVI
STA
RLC
OUT
IN
IN
MVI
OUT
MVI
OUT
EI
RET
UViRITE: LXI
MOV
ORA
JNZ
INX
MOV
JNZ
XCHG
SHLD
LDA
ORI
STA
OUT
MVI
OUT
EI
RET
URDC
A,2
TCMD
USCMD
USDAI
USDAI
A,82H
OF3H
A,OF6H
OFCH
' H,TCBA
A,M
A
UROUT
H
A,M
UROUT
TCBA
LCMD
023H
LCMD
USCMD
A,OF6H
OFCH
jOUTPUT CMD
jCLEAR USART OF LEFT OVER CHARACTERS
jMDS-CLEAR RECEIVE INTERUPT
jMDS
jMDS-ENABLE LEVEL THREE
jMDS
jENABLE INTERUPTS
jRETURN TO USER
jCIlECK WRITE IDLE
jBUSY-EXIT
jBUSY-EXIT
jOK-H GETS COMMAND BLOCK ADDRESS
jTCBA GETS COMMAND'BLOCK ADDRESS
JGET LAST COMMAND
jSET RTS,DTR, AND TXEN
MDS-ENABLE LEVEL THREE INTERUPTS
MDS
ENABLE SYSTEM INTERUPTS
~ND RETURN
7-28
APPLICATIONS
*****
USER IS A TEST PROGRAM WHICH EXERCISES USRUN
*****
43BE
43CO
43C3
43C6
43C9
43CB
43CE
43CF
43D2
43D5
43D6
43D7
43D8
43DB
43DE
43DF
43EO
43E3
43E4
43E6
43E9
43EB
43EE
43EF
43F2
.43F5
43FB
43FB
43FE
4401
4403
4406
4409
440A
440D
4410
4411
4412
4413
4416
4417
4418
441B
441E
0000
3EC3
321800
216842
221900
3E43
111442
12
CD2F43
210040
AF
77
2C
C2D643
210041
75
2C
C2DE43
65
2E52
220042
2E57
220A42
6C
220642
221042
110042
CD2F43
110A42
CD2F43
3EFF
321642
3A"1642
B7
c20644
210040
7E
24
BE
C21E44
25
2C
C21044
C3BE43
C7
USER:
COMLP:
COMER:
MVI
STA
LXI
SHLD
MVI
LXI
STAX
CALL
LXI
XRA
MOV
INR
JNZ
LXI
MOV
INR
JNZ
MOV
MVI
SHLD
MVI
SHLD
MOV
SHLD
SHLD
LXI
CALL
LXI
CALL
MVI
STA
LDA
ORA
JNZ
LXI
MOV
INR
CMP
JNZ
DCR
INR
JNZ
JMP
RST
•
A,OC3H ;MDS-SET INTERUPT VECTOR
018H
H,VECTOR
019H
A, 'c'
;SET ~ENERAL BLOCK TO A 'c'
D,GBLOCK
D
USRUN
H,BUFIN ;CLEAR INPUT BUFFER
A
M,A
L
$-2
H,BUFOUT ;INITIALIZE OUTPUT BUFFER
M,L
L
$-2
;REINTIALIZE CONTROL BLOCKS
H,L
L, 'R'
RBLOCK
L, 'w'
TBLOCK
L,H
RCCT
TCCT
D,RBLOCK ;START READ
USRUN
D,TBLOCK ;START WRITE
USRUN
A,OFFH ;LOOP WAITING COMPLIITION
FLAG
; FLAG WILL BE SET BY COMPLETION ROUTINES
FLAG
A
$-4
H,BUFIN ;TEST INPUT BUFFER=OUTPUT BUFFER
A,M
H
M
COMER
H
L
COMLP
;GOOD COMPARE-REPEAT TEST
USER
;ERROR-RETURN TO MONITOR
0
END
7-29
AFN-006OOA
APPLICATIONS
BSTAT
CLEAN
EXCHA
LCMD
READ
RCR
RISRB
TELOC
TCR
TRCT
TUTE3
URDB
USCMD
USRUN
VOUT
DOFF
4"25B
42BE
4237
4202
4217
4299
420A
4227
420E
431C
4376
00F5
432F
427E
BUFIN
COMER
FLAG
LOADA
RBLOC
RCRA
RISRE
TCBA
TCRA
TUTE
TUTE4
URDC
USDAI
USTAT
4000
441E
4216
423E
4200
4208
42B9
4239
4212
4304
4321
438C
00F4
00F5
BUFOU
COMLP
GBLOC
MTAB
RCBA .
,RISR
RRCT
TCCT
T'ISR
TUTEl
UCLEA
UREAD
USDAO
UWRIT
4100
4410
4214
423D
423B
4288
42'04
4210
42D4
4324
4340
435D
00F4
439D
7-30
CEND
EXA
GSTAT
PEND
RCC T
RISRA
TBAD
TCMD
TISRA
TUTE2
URDA
UROUT
USER
VECTO
0001
42Cl
0000
42CF
4206
42AE
420C
4238
42EC
4314
4377
436B
lJ3BE
4268
AFN.()()6()OA
APPLICATIONS
APPENDIX A
8251 DESIGN HINTS
1. Output of a command to the USART destroys
the integrity of a transmission in progress if
timed incorrectly.
Sending a command into the USART will overwrite any character which is stored in the buffer
waiting for, transfer to the paraUel-to-serial converter in the device. This can be avoided by
waiting for, TxRDY tQ be asserted before sending a command if transmission is taking place.
Due to the internal structure of the USART, it is
also possible to disturb the transmission if a
command is sent while a SYN character is being
generated by the device. (The USART generates
a SYN if the software fails to respond to
TxRDY.) If this occurrence is possible in a system, commands should be transferred only when
a positive-going edge is detected on the TxRDY
line.
'
characters have been detected and the next character has been assembled and is ready to be read.
3. Loss of crs or dropping TxEnable will immediately clamp the serial output line.
TxEnable and RTS should remain asserted until
the transmission is .complete. Note that this implies that not only has the USART completed
the transfer of an bits of the last character, but
also thaHhey have cleared the modem. A delay
of I msec (onowing a proper occurrence of
TxEmpty is usuany sufficient (see item 4). An
additional problem can occur in the synchronous mode because the loss of TxEnable clamps
the data in at a SPACE instead of the normal
MARK. This problem, which do'es not occur in
the asynchronous mode, can be corrected by an
external gate combining RTS and the serial output data.
2. RxE only acts as a mask to RxRDY; it does not
control the operation of the receiver.
When the receiver is enabled, it is possible for it
'to already contain one or hyo characters. These '
characters should be read and discarded when
the RxE bit is first set. Because of these extrane.ous characters the p~bper sequence for gaining
synchronization is as follows:
I. Disable interrupts
2. Issue a command to enter hunt mode, clear
errors, and enable the receiver (EH,ER,RxE=
I)
4, Extraneous transitions can occur on TxEmpty
while data (including USART generated SYNs)
is transferred to the parallel-to-serial convrrter.
This situation can be avoided by eh~uring that
TxEmpty occurs during several consecutive
status reads before assuming that the transmitter
is truly in the empty state.
S. A BREAK (Le., lonll space) detected by the
receiver results in a string of characters which
have framing errors.
, If reception is to be continued after a BREAK,
care must be taken to ensure that valid data is
being received; special care must be taken with
the last Character perceived during a BREAK,
since its value, including any framing error associated with it, is indetermInate.
.
3. Read USART data (it is not necessary to
check status)
4. Enable interrupts
The first RxRDY that occurs after the above
sequence will indicate that the SYN character or
7-31
AFN-00600A
·
.
8251 PROGRAMMABLE COMMUNICATION INTERFACE
7-32
/
APPLICATION
NOTE
AP·36
.
© Intel Corporation, 1978
7-33
March 1978
APPLICATIONS
INTRODIJCTION
The Intel 8273 is a Oata Communications Protocol Con·
troller designed for use in systems utilizing either SOLC
or HOLC (Synchronous or High-Level Oata Link Control)
protocols. In addition to the usual features such as full
duplex operation, automatic Frame Check Sequence
generation and checking, automatic zero bit insertion
and deletion, and TIL compatibility found on other
single component SOLC controllers; the 8273 features a
frame level command structure, a digital phase locked
loop, SOLC loop operation, and diagnostics.
The frame level command structure Is made possible by
the 8273's unique internal dual processor architecture.
A high-speed bit processor handles the serial data
manipulations and character recognition. A byte processor implements the frame level commands. These
dual processors allow the 8273 to control the necessary
byte-by-byte operation of the data channel with a
minimum of CPU (Central Processing Unit) intervention.
For the user this means the CPU has time to take on
additional tasks. The digital phase locked loop (OPLL) ,
provides a means of clock recovery from the received
data stream on-chip. This feature, along with the frame
level commands, makes SOLC loop operation extremely
simple and Ilexible. Oiagnostics in the form of both data
and clock loopback are available to simplify board
debug and link testing. The 8273 is a dedicated function
peripheral in the MCS-80/85 Microcomputer family and
as such, it interfaces to the 8080/8085 system with a
minimum of external hardware.
This application note explains the 8273 as a component
,and shows, its use in a generalized loop configuration
and a typical 8085 system. The 8085 systefj1 was used to
verify the SOLC operation of the 8273 on an actual IBM
SOLC data communications link.
The first section of this application note presents an
overview of the SOLC/HOLC protocols. It is fairly tutorial
in 'nature and may be skipped by the more knowledgeable reader. The second section describes the 8273 from
a functional standpoint with explanation of the block
diagram. The software aspects of the 8273, including
command examples, are discussed in the third section.
The fourth and fifth sections discuss a loop SOLC configuration and the 8085 system respectively.
Aside from supporting a large number of configurations,
SOlC offers the potential of a 2 x increase In throughput over the presently most prevalent protocol: Bi·Sync.
This performance increase is primarllyduetotwocharacteristics of SOLC: full duplex operation and the implied
acknowledgement of transferred information. The per·
formance Increase due to full duplex operation is fairly
obvious since, in SOLC, both stations can communicate
simultaneously. Bi·Sync supports only half·duplex (twow,ay alternate) communication~ The Increase from implied acknowledgement arises from the fact that a station using SOLC may acknowledge previously received
intormation while transmitting different information. Up
to 7 messages may be outstanding before an acknowl·
edgement is required. These messages may be acknowledged as a block rather than singly. In Bi-Sync, acknowledgements are unique messages that may not be
Included "Wlith messages containing information and
each information message requires a separate acknowl·
edgement. Thus the line efficiency of SOLC is superior
to Bi-Sync. On a higher level, the potential of a 2x
increase in performance means lower cost per unit of
information transferred. Notice that the increase is not
due to higher data link speeds (SOLC Is actually speed
independent), but simply through better line utilization.
Getting down to the more salient characteristics of
SOLC; the basic unit of information on an SOLC link is
that of the frame. The frame format is shown in Figure 1.
Five fields comprise each frame: flag, address, control,
information, and frame check sequence. The flag fields
(F) form the boundary of the frame and all other fields
are positionally related to one of the two flags. All
frames start with an opening flag and end with a clOSing
flag. Flags are used for frame synchronization. They
also may serve as time·fill characters between frames.
(There are no intraframe time·fill characters in SOLC as
there are in Bi·Sync.) The opening flag serves as a refer·
ence point for the address (A) and control (C) fields. The
frame check sequence (FCS) is referenced from the
clOSing flag. All flags have the binary configuration
01111110 (7EH).
SOLC is a bit-oriented protocol, that is, the receiving
station must be able to recognize a flag (or any other
special character) at any time, not just on an 8-bit '
boundary. This, of course, implies that a frame may be
N-bits in length. (The vast majority of applications tend
to use frames which are multiples of 8 bits long,
however.)
SDLC/HDLC OVERVIEW
SOLC is a protocol for managing the flow of information
on a data communications link. In other words, SOLC
can be thought of as an envelope - addressed,
stamped, and containing an s.a.s.e. - in which information is transferred from location to location on a data
communications link. (Please note that while SOLC is
discussed specifically, all comments also apply to
HOLC except where noted.) The link may be either pointto'point or multi-point, with the point-to-point configura·
tion being either switched or nonswitched. The informa·
tion flow may use either full or half duplex exchanges.
With this many configurations supported, it i,s difficult
to find a synchronous data communications application
where SOLC would not be appropriate.
FRAME
CHECK
OPENING
FLAG
ADORESS
FIELD (AJ
CONTROL
FIELD (e)
INFORMATION SEQUENCE
FIELD (I)
(FCSI
CLOSING
FLAG
Figure 1. SDLe Frame Format
7-34
AFK-00611A
APPLICATIONS
The fact that the flag has a unique binary pattern would
seem to limit the contents of the frame since a flag pattern might inadvertently occur within the frame. This
would cause the receiver to think the closing flag was
received, invalidating the frame. SOLe handles this
situation through a technique called zero bit insertion.
This techniques specifies that within a frame a binary 0
be insprted by the transmitter after any succession of
five contiguous binary 1s. Thus, no pattern of 01111110
is ever transmitted by chance. On the receiving end,
after the opening flag is detected, the receiver removes
any 0 following 5 consecutive 1s. The inserted and
deleted Os are not counted for error determination.
Before discussing the address field, an explanation of
the roles of an SOLC station is in order. SOLe specifies
two types of stations: primary and secondary. The
primary is the control station for the data link and thus
has responsibility of the overall network. There is only
one predetermined primary station, all other stations on
the link assume the secondary station role. In general, a
secondary station speaks only when spoken to. In other
words, the primary polls the secondaries for responses.
In order to specify a specific secondary, each secondary
is assigned a unique 8-bit address. It is this address that
Is used in the frame's address field.
When the prim~ry transmits a frame to a specific secondary, the address field contains the secondary's ad·
dress. When responding, the secondary uses its own
address in the address field. The primary is never iden·
tified. This ensures that the primary knows which of
many secondaries is responding Since the primary may
have many messages outstanding at various secondary
stations. In addition to the specific secondary address,
an address common to all secondaries may be used for
various purposes. (An all 1s address field is usually used
for this "All Parties" address.) Even though the primary
may use this common address, the secondaries are ex·
pected to respond with their unique address. The
address field is always the first 8 bits following the
opening flag.
The 8 bits following the address field form the control
field. The control field embodies the link-level control of
SOLe. A detailed explanation of the· commands and
responses contained in this field is beyond the scope of
this application note. Su1/ice it to say that it is in the
control field that the implied acknowledgement is carried out through the use of frame sequence numbers.
None of the currently available SOLe single chip controllers utilize the control field. They simply pass it to
the processor for analysis. Readers wishing a more
detailed explanation of the control field, or of SOLe in
general, should consult the IBM documents referenced
on the front page overleaf.
In some types of frames, an information field follows
the control field. Frames used strictly for link management mayor may not contain one. When an information
field is used, it is unrestricted in both content and
length. This code transparency is made possible
because of the zero bit insertion mentioned earlier and
the bit-oriented nature of SOLC. Even main memory core
dumps may be transmitted because of this capability.
This feature is unique to bit·oriented protocols. Like the
7-35
control field, the information field is not interpreted by
the SOLC device; it is merely transferred to and from
memory to be operated on and interpreted by thE.'
processor.
The final field is the frame check sequence (FCS). The
FCS is the 16 bits immediatelY'preceding the closing
flag. This 16·bit field is used for error detection through
a Cyclic Redundancy Checkword (CRC). The 16-blt
transmitted CRC is the complement of the remainder
obtained when the A, C, and I fields are "divided" by a
generating polynomial. The receiver accumulates ,the A,
C, and I fields and also the FCS into Its internal CRC
register. At the closing flag, this register contains one
particular number for an error-free reception. If this
number is not obtained, the frame was received in error
and should be discarded. Discarding the frame causes
the station to not update its frame sequence numbering.
This results in a retransmission after the station sends
an acknowledgement from previous f,rames. [Unlike all
other fields, the FCS is transmitted MSB (Most Significant Bit) first. The A, C, and I fields are transmitted LSB
(Least Significant Bit) first.) The details of how the FCS
is generated and checked is beyond the scope of this
application note and since all single component SOLC
controllers handle this function automatically, it is
usually sufficient to know only that an error has or has
not occurred. The IBM documents confain more detailed
information for those readers desiring it.
The clOSing flag terminates the frame. When the closing
flag is received, the receiver knows that the preceding
16 bits constitute the FCS and that any bits between the
control field and the FCS constitute the information
field.
SOLC does not support an interframe time-fill character
such'as the SYN character in Bi-Sync. If an unusual condition occurs while transmitting, such as data is not
available in time from memory or CTS (Clear-to-Send) is
lost from the modem, the transmitter aborts the frame
by sending an Abort character to notify the receiver to
invalidate. the frame. The Abort character consists of
eight contiguous 1s sent without zero bit insertion. Intraframe time-fill consists of either flags, Abort characters, or any combination of the two.
While the Abort character protects the receiver from
transmitted errors, errors introduced by the transmission medium are discovered at the receiver through the
FCS check and a check for invalid frames. Invalid
frames are those which are not bounded by flags or are
too short, that is, less than 32 bits between flags_ All invalid frames are ignored by the receiver.
Although SOLC is a synchronous protocol, it provides
an optional feature that allows its use on basically asynchronous data links NRZI (Non-Return-to-ZeroInverted) coding, NRZI coding specifies that the signal
condition does not change for transmitting a binary 1,
while a binary 0 causes a change of state. Figure 2 illustrates NRZI coding compared to the normal NRZ. NRZI
coding guarantees that an active line will have a transition at least every 5-bit times; long strings of zeroes
cause a transition every bit time, while long strings of 1s
are broken up by zero bit insertion. Since asynchronous
AFN.()0611A
APPLICATIONS
Loop operation defines a new special character: the
EOP (End-of-PolI) character which conSists of a 0 followed by 7 contiguous, non·zero bit inserted, ones. After
the loop controller transmits a message, It Idles the line
(sends all 1s). The final zero of the closing flag plus the
first 7 1s of the idle form an EOP character. While
repeating, the secondaries monitor their incoming line
for an EOP character. When an EOP is detected, the
secondary checks to see if it has a message to transmit.
If it does, it changes the seventh 1 to a 0 (the one bit
delay allows time for this) and repeats the modified EOP
(now alias flag). After this flag is transmitted, the secondary terminates its repeater function and inserts its
message (with multiple preceding flags if necessary).
After the closing flag, the secondary resumes its one bit
delay repeater function. Notice that the final zero of the
secondary's closing flag plus the repeated 1s from the
controller form an EOP for the next down-loop secondary, allowing it to insert a message if it desires.
operation requires that the receiver sampling clock be
derived from the received data, NRZI encoding plus zero
bit insertion make the design of clock recovery circuitry
easier.
All of the previous discussion has applied to SOLC on
either point-to-point or multi-point data networks, SOLC
(but not HOLC) also includes specification for a loop
configuration. Figure 3 compares these three configurations. IBM uses this loop configuration in its 3650 Retail
Store System. It consists of a single loop controller station with one or more down-loop secondary stations.
Communications on a loop rely on the secondary stations repeating a received message down loop with a
delay of one bit time. The reason for the one bit delay
will be evident shortly.
DATA
1
BIT SAMPLE
"I
l 11
I·
o
0
111
lIt
0
One might wonder if the secondary missed any messages from the controller while it was inserting its own
message. It does not. Loop operation is basically halfduplex. The controller waits until it receives an EOP
before it transmits its next message. The controller's
reception of the EOP signifies that the original message
has propagated around the loop followed by any messages inserted by the secondaries. Notice that secondaries cannot communicate with one another directly, all
secondary-to-secondary communication takes place by
way of the controller.
NRZ
NRZI
,Figure 2. NRZI v. NRZ Encoding
POINT·TO·POINT
LOOP
MULTI·POINT
Figure 3 Network Configuration.
7-36
AFN-00611A
APPLICATIONS
BASIC 8273 OPERATION
Loop protocol does not utilize the normal Abort charac·
ter. Instead, an abort is accomplished by simply trans·
mitting a flag character. Down loop, the receiver sees
the abort as a frame which is either too short (if the
abort occurred early in the frame) or one with an FCS
error. Either results in a discarded frame. For more
detailli on loop operation, please refer to the IBM
documents referenced earlier.
It will be helpful for the following discussions to have
some idea of the basic operation of the 8273. Each
operation, whether it is a frame transmission, reception
or port read, etc., is comprised of three phases: the
Command, Execution, and Result phases. Figure 5
shows the sequence of these phases. As an illustration
of this sequence, let us look at the transmit operation.
Another protocol very similar to SOLC which the 8273
supports is HOLC (High· Level Data Link Control). There
are only three basic differences between the two: HOLC
offers extended address and control fields, and the
HLOC Abort character Is 7 contiguous 1s as opposed to
SOLC's 8 contiguous 1s. •
Extended addressing, beyond the 256 unique addresses
possible with SOLC, is provided by using the address
field's least significant bit as the extended address
modifier. The receiver examines this bit to determine if
the octet should be interpreted as the final address
octet. As long as the bit is 0, the octet that contains it is
considered an extended address. The first time the bit is
a 1, the receiver interprets that octet as the final address
octet. Thus the address field may be extended to any
number of octets. Extended addressing is illustrated in
Figure 4a.
A similar technique is used to extend the control field
although the extension is limited to only one extra con·
trol octet. Figure 4b illustrates control field extension.
Figure 5. 8273 Operational Pha•••
Those readers not yet asleep may have noticed the simi·
larity between the SDLC loop EOP character (a 0 follow·
ed by 7 1s) and the HOLC Abort (7 1s). This possible in·
compatibility is neatly handled by the HOLC protocol
not specifying a loop configuration.
This completes our brief discussion of the SOLC/HOLe
protocols. Now let us turn to the 8273 in particular and
discuss its hardware aspects through an explanation of
the block diagram and generalized system schematics.
FIRST BIT TRANSMITTED (LSB FIRst)
A HDLe ADDRESS FIELD eXTENSION
Flgure4a
/
F~G
EXTENSION BIT (1 MAX)
I It C11
A
When the CPU decides it is time to transmit a frame, the
Command phase is entered by the CPU issuing a Trans·
mit Frame command to the 8273. It is not sufficient to
just instruct the 82"3 to transmit. The frame level com·
mand structure sometimes requires more information
such as frame length and address and control field con·
tent. Once this additional information is supplied, the
Command phase is complete and the Execution phase
is entered. It is during the Execution phase that the
actual operation, in this case a frame transmission,
takes place. The 8273 transmits the opening flag, A and
C fields, the specified number of I field bytes, inserts
the FCS; and closes with the closing flag. Once the clos·
ing flag is transmitted, the 8273 leaves the Execution
phase and begins the Result phase. During the Result
phase the 8273 notifies the CPU of the outcome of the
command by supplying interrupt results. In this case,
the results would be either that the frame is complete or
that some error condition causes the transmission to be
aborted. Once the CPU reads all of the results (there is
only one for the Transmit Frame command), the Result
phase and consequently the operation, is complete.
Now that we have a general feeling forthe operation of
the 8273, let us discuss the 8273 in detail.
C2 )11
112
I
Fes,)
FCS21
FLAG
HARDWARE ASPECTS OF THE 8273
B HOLe CONTROL FIELD EXTENSION
The 8273 block diagram is shown in Figure 6. 'It consists
of two major interfaces: the CPU module interface and
the modem interface. Let's discuss each interface
separately.
Figure4b
7-37
AF~11A
APPLICATIONS
~---------F~GDETE~
~---'----Cii
REGISTERS
, . - - - - - - - CTii
,.-----RTS
TxUR
CO~MA"D
RxUR
PARAMETER
TEST MODE
STATUS
RESULT
DBO_7
p..----TxC
TxDRO----I
DATA
TIMING
LOGIC
TiDACK:-,- - - 0 1
RxDRO----!
RxDACK
---.oj
1-----TxD
P.----RxC
1-----RxD
'-------iim
Rii---·CJI
' - - - - - - - - 32XCLK
WA_
CS---.oj
Ao----I
A1-----I
INTERNAL
DATA BUS
RESET _ _ _ _oJ
OCLK-------'
TxlNT _ _ _ _ _- - '
RxlNT _ -_ _ _ _---'
CPU MODULE INTERFACE
MODEM INTERFACE
Fig .... 8. 8273 Block Diagram
CPU Interface
Command - 8273 operations are initiated by writing
the appropriate command byte Into this register.
The CPU Interface consists of four major blocks: Control/ReadlWrlte logic (C/RlW), internal registers, data
transfer logic, and data bus buffers.
The CPU module utilizes the C/RIW logic to issue commands to the 8273. Once the 8273 receives a command
and executes it, It returns the results (good/bad completion) of the command by way of the C/RIW logic, The
C/RlW logic Is supported by seven registers which are
address~ via the Ao, A" RD, and iiiiRslgnals, I,n addi·
tlon to CS. The Ao and A, signals are generally derived
from the two low order bits of the CPU module address
bus while Fro and iiiiR are the normal 110 Read and Write
signals found on the system control bus. Figure 7
shows the address of each register using the C/RIW
logic. The function of each register Is defined as
follows:
'
ADDRESS INPUTS
Ao
CS.RD
CS.WR
0
0
1
1
0
1
0
1
STATUS
RESULT
Txl/R
RxllR
COMMAND
PARAMETER
TEST MOPE
Immediate Result (Result) - The completion infor, mation (results) for commands which execute immediately are provided in this register.
Transmit Interrupt Result (TxIlR) - Results of
transmit operations are passed to the CPU In this
register.
Receiver Interrupt Result (RxIlR) - Receive operation results are passed to the CPU via this register.
Status - The general status of the 8273 is provided
in this register. The Status register supplies the
handshaking necessary during various phases of the
8273 operation.
Test Mode - This register provides a software reset
function for the 8273.
CONTROL INPUfS
A1
Parameter - Many commands require more information than found In the command Itself, This additional information Is provided by way of the parameter register.
The commands, parameters, and bit definition of these
registers are discussed in the following software section. Notice that there are not specific transmit or
receive data registers. This feature is explained in the
data transfer, logic discussion.
-
FIgure 7. 8273 Register Selection
7-38
AfN.CXi8'1A
APPLICATIONS
The final elements of the ClR/W logic are the Interrupt
lines (RxINT and TxlNn. These lines notify the CPU
module that either the transmitter or the receiver reo
quires service; I.e., results should be read from the
appropriate Interrupt result register or a data transfer is
required. The Interrupt request remains active until all
the associated interrupt results have been read or the
data transfer is performed. Though using the Interrupt
lines relieves the CPU module of the task of polling the
8273 to check if service is needed, the state of each
Interrupt line Is reflected by a bit In the Status register
and non-Interrupt driven operation Is possible by examing the contents of these bits periodically.
The 8273 supports two independent data Interfaces
through the data transfer logic; receive data and transmit data. These interfaces are programmable for either
DMA or non· OM A data transfers. While the choice of the
configuration is up to the system designer, it is based
on the Intended maximum data rate of the communica·
tions channel. Figure 8 Illustrates the transfer rate of
data bytes that are acqulred'by the 8273 based on link
data rate. Full-duplex data rates above 9600 baud usually require DMA. Slower speeds mayor may not require
DMA depending on the task load and interrupt response
time of the processor.
Figure 9 shows the 8273 In a typical DMA environment.
Notice that a separate DMA controller, in this case the
Intel 8257, is required. The DMA controller supplies the
timing and addresses for the data transfers while the
8273 manages the requesting of transfers and the actual
counting of the data block lengths. In this case,
elements of the data transfer Interface are:
TxDRQ: Transmit DMA Request - Asserted by the
8273, this line requests a DMA transfer from memory
to the 8273 for transmit.
TxDACK: Transmit DMA Acknowledge - Returned
by the 8257 in response to TxDRQ, this line notifies
the 8273 that a r.equest has been granted, and pro·
vides access to the transmitter data register.
the receiver alleviates the need for the normal transmit
and receive data registers addressed by a combination
of address lines, CS, and WR or RD. Competitive
devices that do not have this "hard select" feature require the use of an external multiplexer to supply the
correct Inputs for register selection during DMA. (Do not
forget that the SDLC controller sees both the addresses
and control signals supplied by the DMA controller duro
ing DMA cycles.) Let us look at typical frame transmit
and frame receive sequences to better see how the 8273
truly manages the DMA data transfer.
Before a frame can be transmitted, the DMA controller is
supplied, by the CPU, the starting address for the
desired Information field. The 8273 is then commanded
to transmit a frame. (Just how this is done is covered
later during our software discusllion.) After the com·
mand. but before transmission begins, the 8273 needs a
little more Information (parameters). Four parameters
are required for the transmit frame command: the address field byte, the control field byte, and two bytes
which are the least significant and most significant
bytes of the information field byte length. Once all four
parameters are loaded, the 8273 makes RTS (Request·to·
Send)'active and waits for CTS (Clear-to-Send) to go ac·
tive. Once CTS Is active, the 8273 starts the frame trans·
mission. While the 8273 is transmitting the opening flag,
address field, and control field; it starts making trans·
mitter DMA requests. These requests continue at char·
acter (byte) boundaries until the pre·loaded number ot
bytes of information field /lave been transmitted. At this
pOint the requests stop, the FCS and closing flag are
transmitted, and the TxlNT line is raised, Signaling the
CPU that· the frame transmission is complete. Notice
that after the initial command and parameter loading,
absolutely no CPU intervention was required (since
DMA is used for data transfers) until the entire frame
was transmitted. Now let's look at a frame reception.
BOms
8m,
RxDRQ:. Receiver OMA Request - Asserted by the
8273, it requests a DMA transfer from the 8273 to
memory for a receive operation.
sec/byle
TxDACK: Receiver DMA Acknowledge - Returned by
the 8257, it notifies the 8273 that a receive DMA cycle
has been granted, and provides access to the
receiver data register.
801'$
'00
BAUD RATE (bps)
RD: Read - Supplied by the 8257 to indicate data Is
to be read from the 8273 and placed in memory.
Figure 8. Byte Transler Rate .. Baud Rale .
WR: Write - Supplied by the 8257 to indicate data is
to be written to the 8273 from memory.
To request a DMA transfer the 8273 raises the appropri·
ate DMA request line; let us assume it iii a transmitter
request (TxDRQ). Once the 8257 obtains control of the
system bus by way of its HOLD and HLDA (hold
acknowledge) lines, it notifies the 8273 that TxDRQ has
been granted by returning TxDACK and WR. The
TxDACK and WR signals transfer data to the 8273 for a
transmit, independent of the 8273 chip select pin (CS). A
similar sequence of events occurs for receiver requests.
This "hard select" of data into the transmitter or out of
7-39
DRQ1
8257
OACK1
OMA
CONTROLLER
ORCO
r
·OONTROL
'BUS
~OATA.US
Figure 9. DMA. Interrupt·Drlven System
AFN-00611A
APPLICATIONS
The receiver operation is very similar. Like the initial
transrnlt sequence, the DMA controller Is loaded with a
starting address for a receiver data buffer and the 8273
is commanded to receive. Unlike the transmitter, there
are two different receive commands: General Receive,
where all received frames are transferred to memory,
and Selective Receive, where onlY'frames having an address field matching one of two preprogrammed 8273
address fields are transferred to memory. Let's assume
fpr now that we want to general receive. After the
receive command, two parameters are required before
the receiver becomes. active: the least significant and
most significant bytes of the receiver buffer length.
Once these bytes are loaded, the receiver is active and
Ihe CPU may return to other tasks. The next frame
appearing at the receiver input is transferred to memory
using receiver DMA requests. When the closing flag is
received, the 8273 checks the FCS and raises its RxlNT
line. The CPU can then read the results which indicate if
the frame was error-free or not. (If the received frame
had been longer than the pre-loaded buffer length, the
CPU wOljld have been notified of that occurrence earlier
with a receiver error interrupt. The command description
section contains a complete list of error conditions.)
Like the transmit example, after the initial command,
the CPU is free for other tasks until a frame Is com·
pletely received. These examples have illustrated the
8273's management of both the receiver and transmitter
DMA channels.
the Status register. Thus, In response to an interrupt,
the CPU reads the Status register and branches to either
a result or a data transfer routine based on the status of
one bit. As before, data transfers are made via using the
DACK lines as chip selects to the transmitter and
receiver data registers.
r
COHTAOL
BUS
0213
WR
07-00
~ ~~T'BUS
Figure 10. Interrupt·aased DMA System
It is possible to use the DMA data transfer interface in a
non·DMA interrupt-driven environment. In this case, 4 interrupt levels are used: one each for TxlNT and RxINT,
and one each for TxDRO and RxDRO. This configuration
is shown in Figure 10. This configuration offers the
advantages that no DMA controller is required and data
requests are still separated from result (completion) reo
quests. The disadvantages of the configuration are that
4 interrupt levels are required and that the CPU must ac·
tually supply the data transfers. This, of course, reduces
the maximum data rate compared to the configuration
based strictly on DMA. This system could use an Intel
8259 8-level Priority Interrupt Controller to supply a vectored CALL (subroutine) address based on requests on
its inputs. The 8273 transmitter and receiver make data
requests by raising the respective ORO line. The CPU is
interrupted by the 8259 and vectored to a data transfer
routine. This routine either writes (for transmit) or reads
(for receive) the 8273 using the respective TxDACK or
RxDACK line. As In the case above, the DACK lines
serve as "hard" chip selects Into and out of the 8273.
(Tx{)ACK + iiVJ!t writes data Into the 8273 for transmit.
RxDACK + RD reads data from the 8273 for receive.)
The CPU Is notified of operation completion and results
by way of TxlNT and RxlNT lines. Using the 8273, andthe 8259, In this way, provides a very effective, yet simple, Interrupt-driven Interface.
Figure 11 illustrates a system very similar to that
described above. This system.utilizes the 8273 in a nonDMA data transfer mode as opposed to the two DMA ap·
proaches shown in Figures 9 and 10. In the non-DMA
case, data transfer requests are made on the TxlNT and
RxlNT lines. The ORO lines are riot used. Data 'transfer
requests are separated from result requests by a bit in
7-40
lOR
RD
8273
lOW
WR
07-00
rBUS
~ ~DATA.US
Figure 11. Non·DMA Interrupt·Drlven System
Figure 12 illustrates the simplest system of all. This
system utilizes polling for all data transfers and results.
Since the Interrupt pins are reflected in bits. in the
Status register, the software can read the Status
register periodically looking for one of these to be set. If
it finds an INT bit set, the appropriate Result Available
bit is examined to determine if the "Interrupt" Is a data
transfer or completion result. If a data transfer Is called
for, the DACK line Is used to enter or read the data from
the 8273. If the Interrupt Is a completion result, the-appropriate result register Is read to determine the goodl
bad completion of the operation.
The actual selection of either DMA or non-DMA modes
is controlled by a command Issued during Initialization.
This command is covered In detail during the software
discussion.
AFN.00611A
APPLICATIONS
reset. (All commands mentioned In this section are
covered In detail later.).
The final block of the CPU module Interface Is the Data
Bus Buffer. This block supplies the trl-state, bidirectional data bus Interface to allow communication to and
from the 8273.
The final block to be covered is the serial data timing
block. This block contains two sections: the serial data
logic and the digital phase locked loop (OPLL).
Elements of the serial data logic section are the data
pins, TxD (transmit data output) and RxD (receive data
input), and·the respective data clocks, TxC and RxC. The
transmit and receive data is synchronized by the TxC
and RiC clocks. Figure 15 shows the timing for these
signals. The leading edge (negative tranSition) of TxC
generates new transmit data and the trailing edge
(positive transition) of RxC is used to capture the
receive data.'
Modem Interface
As the name implies, the modem interface is the modem
side of the 8273. It consists of two major blocks: the
modem control block and the serial data timing block.
The modem control block provides both dedicated and
user·defined modem control functions. All signals supported by this interface are active low so that EIA
inverting drivers (MC1488) and inverting receivers
(MC1489) may be used to interface to standard modems.
It is possible to reconfigure this section under program
control to perform diagnostiC functions; both data and
clock loopback are available. In data loopback mode, the
TxD pin is internally routed to the RxO pin. This allows
simple board checkout since the CPU can send an SOLC
message to itself. (Note that transmitted data will still
appear on the TxO pin.)
Port A is a modem control input port. Its representation
on the data bus is shown in Figure 13. Bits Do and D1
have dedicated functions. Do reflects the logical state of
the CTS (Clear-to-Send) pin. [If CTS is active (low), Do is a
1.] This signal is used to condition the start of a trans·
mission. The' 8273 waits until CTS is active before it
starts transmitting a frame. While transmitting, if CTS
goes inactive, the frame is aborted and the CPU is inter·
rupted. When the CPU reads the interrupt result, a CTS
failure is indicated.
D1 reflects the logical state of the CD (Carrier Detect)
pin. CD is used to condition the start of a frame reception. CD must be active in time for 'a frame's address
field. If CD is lost (goes inactive) while receiving a frame,
an interrupt is generated with a CD failure result. CD
may go inactive between frames.
Ne
Ne
Ne
He
_CONTROL
'OA
8273
BUS
,ow
WA
Bits D2 thru D4 reflect the logical state of the PA 2 thru
PA 4 pins respectively. These inputs are user defined.
The 8273 does not interrogate or manipulate these bits.
Bits D5, D6,and D7 are not used and each is read as a 1
for a Read Port A command.
D7~OO
~ ~DA'ABUS
Port B is a modem control output port. Its data bus
representation is shown in Figure 14. As in Port A, the
bit values represent the logical condition of the pins. Do
and D5 are dedicated function outputs. Do represents
the FITS (Request-to·Send) pin. FITS is normally used to
notify the modem that the 8273 wishes to transmit. This
function is handled automatically by the 8273. If FiTS is
inactive (pin is high) when the 8273 is commanded to
transmit, the 8273 makes it active and then waits for
CTS before transmitting the frame. One byte time after
the end of the frame, the 8273 returns RTS to its inactive
state. However, if RfS was active when a transmit com·
mand is issued, the 8273 leaves it active when the frame
is complete.
Figure 12. Polled System
Figure 13. Port A (Input) BII D.llnltlon
Bit D5 reflects the state of the Flag Detect pin. This pin
is activated whenever an active receiver sees a flag
character. This function is useful to activate a timer for
line activity timeout purposes.
I
Bits D1 thru D4 provide four user-defined outputs. Pins
PB 1 thru PB 4 reflect the logical state of these bits. The
8273 does not interrogate or manipulate these bits. 0 6
and D7 are not used. In addition to being able to output
to Port B, Port B may be read using a Read Port B com·
mand. All Modem control output pins are forced high on
I·I IIII
.
-~--mI"E::::'.::,:::·ou,pu,.
LI_I
FLAG DETECT
Figure 14. Port B (Output) Bit Dellnltlon
7-41
AFN.()()611A
APPLICATIONS
When data loopback is utilized, the receiver may be
presented incorrect sample timing (RxC) by the external
circuitry. 'Clock loopback overcomes this problem by
allowing the internal routing of 'i'Xe and Axe. Thus the
same clock used to Iran,sm!t the data is used to receive
it. Examination of Figure 15 shows that this method ensures bit synchronism. The final element of the serial
data logic is the Digital Phase locked loop.
DJ5[[ pulse 8. The distance from 8 to the next pulse C Is
influenced according to which quadrant (AI' 81, 8 2, or
A2) the data edge falls in. (Each quadrant represents 8
32 x ClK times.) For example, if the edge is detected In
quadrant AI, It is apparent that pulse 8 was too close to
the data edge and the time to the next pulse must be
shortened. The adjustment for quadrant Al Is specified
as - 2. Thus, the next DPll pulse, pulse C, is positioned 32 - 2 or 30 32 x ClK pulses following i5J5[[
pulse 8. This adjustment moves pulse C closer to the
nominal bit center of the next received data cell. A data
edge occurring in quadrant 82 would have caused the
adjustment to be small, namely 32 + 1 or 33 32 x ClK
pulses. Using this technique, the i5'PiI pulse converges
to the norninal bit center within 12 'data transitions,
worse case - 4-bit times adjusting through quadrant A1
or A2 and 8-bil-times adjusting through 8 1 or 82'
The DPll provides a means of clock recovery from the
received data stream. This feature allows the 8273 to interface without external synchronizing logic to low cost
asynchronous modems (modems which do not supply
clocks). It also makes the problem of clock timing In
loop configurations trivial.
To use the DPll, a clock at 32 times the required baud
rate must be supplied to the 32 x ClK pin. This clock
provides the interval that the DPll samples the received
'data. The DPll uses the 32 x clock and the received
data to generate a pulse at the DPll outPl,lt pin. This
DPll pl,llse is positioned at the nominal center of the
received data bit cell. Thl,ls the DPll Ol,ltPl,lt may be
wired to RxC and/or TxC to sl,lpply the data timing. The
exact pOf?ition of the pl,llse is varied depending on the
line noise and bit distortion of the received data. The adjustment of the DPll position is determined according
to the rules outlined in Figure 16.
J
Adjustments to the sample phase of DPLt with respect
to the received data is made in discrete increments.
Referring to Figure 16,/following the occurrence of
DPll pullje A, the DPll counts 32 x ClK pulses and examines the received data for a data edge. Should no
edge be detected in 32 pulses, the DPll positions the
next DPll pulse (8) at 32 clock pulses from pulse A.
Since no new phase information is contained in the data
stream, the sample phase is assumed to be at nominal
1 x baud rate. Now assume a data edge occurs after
Figura 15. TransmlllRecelve Timing
, BIT TIME
RxD
mctK
.u-..
NO TRANSITION
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32
1------32 CLOCKS - - - - - 1
A
1--~--30 ~LOCKS -~-=:::--I
8
I
I
I
I
I•
33 CLOCKS
,
I
,
I
_-+-_ _-..,-_.
:---+--32 ~LOCKS--t-----.1u~'.vm'~'
r:::-AL
,
'
I
,
QUADRANT'
ADJUSTMENT'
I
I
I
AI
-2
I
I
8,
-,
I
I
I
I
82
+1
A2
+2
I
I
Flgure\16. DPLL Phase Adjustments
7-42
AFN-00611A
APPLICATIONS
to the CPU. Due to the Internal processor architecture of .
the 8273, this CPU-8273 communication is basically a
form of Interprocessor communication. Such communication usually requires a form of protocol of its own.
This protocol is implemented through use of handshaking suppl1ed In the 8273 Status register. The bit definition of this register is shown in Figure 18.
When the receive data stream goes Idle after 15 ones,
DPll pulses ~re generated at 32 pulse Intervals of the
32x ClK. This feature allows the DPll pulses to be
used as both transmitter and receiver clocks.
In order to guarantee sufficient transitions of the received data to enable the i515lI. to lock, NAZI encoding
of the data is recommended. This ensures that, within a
frame, data transitions occur at least every five bit times
- the longest sequence of 1s which may be transmitted
with zero bit insertion. It is also recommended that
frames following a line idle be transmitted with preframe sync cha~acters which provide a minimum of 12
transitions. This ensures that the !)IS([ Is generating
iSPIT pulses at the nominal bit centers in time for the
opening flag. (Two OOH characters meet this requirement by supplying 16 transitions with NRZI encoding.
The 8273 contains a mode which supplies such a preframe sync.)
,
. '
CBSY: Command Busy - CBSY indicates when the
8273 is in the command phase. CBSY is set when the
CPU writes a command into the Command register,
'starting the Command phase. It is reset when the last
parameter Is deposited In the Parameter register and
accepted by the 8273, completing the Command
phase.
CBF: Command Buffer Full - When set, this bit indicates that a byte is present in the Command
register. This bit is normally not used.
CPBF: Command Parameter Buffer Full- This bit indicates that the Parameter register contains a
parameter. It is set when the CPU deposits a
parameter in the Parameter register. It Is reset when
the 8273 accepts the parameter.
Figure 17 illustrates 8273 clock configurations using
either synchronous or asynchronous modems. Notice
how the DPll output is used for both ~ and RXC in
the asynchronous case. This feature eliminates the
need for external clock generation logic where low cost)
asynchronous modems are used and also allows direct
connection of 8273s for the ultimate In low cost data
links. The configuration for loop applications is discussed in a following section.
CRBF: Command Result Buffer Full - This bit is set
when the 8273 places a result from an immediate
type command in the Result register. It is reset when
the CPU reads the result from the Result register.
RxINT: Receiver Interrupt - The state of the RxlNT
pin is reflected by this bit. RxlNT is set by the 8273
whenever the receiver needs servicing. RxlNT is reset
when the CPU reads the results or performs the data
transfer.
TxINT: Transmitter Interrupt - This bit is identical to
RxlNT except action is initiated based on transmitter
interrupt sources.
This completes our discussion of the hardware aspects
of the 8273. Its software aspects are now discussed.
SOFTWARE ASPECTS OF THE 8273
The software aspects of the 8273 Involve the communication of bO,th commands from the CPU to the 8273 and
the return of results of those co~mands from the 8273
TXc
TxD
8273
-=
RxC
SYNC
MODEM
Ne
SYNCHRONOUS MODEM INTERFACE
32X
CLOCK
ASYNCHRONOUS MODEM INTERFACE
Figure 17. Serial Data Tim/rig _C-"nfiuuratl.?",
7-43
AFN-00611A
APPLICATIONS
RxIRA: Receiver Interrupt Result Available - RxlRA
Is set when the 8273 places an interrupt result byte
into the Rxl/R register. RxlRA is reset when the CPU
reads t~e RxllR register;
phase: A detailed description of the commands and
their parameters is presented'in a following 'section.
TxIRA: Transmitter Interrupt Result Available TxlRA is the corresponding Result Available bit for
the transmitter. It is set when the 8273 places an In·
terrupt result byte in the Txl/Rregisfer and' reset
when the CPU reads the register. '
The significance of each of these bits will be evident
shortly. Since the software requirements of each
8273 phase are essentially independent, each phase
' .
is covered separately.
-':====
L
TdRA ...... TxlNT RESULT AVAILABLE
RxlRA - RdNT AESUL T AVAILABLE
TxlNT -
Tx INTERRUpt
RxlNT - Rll INTERRUPT
' - - - - - - - CR&F ~ COMMAND RESULT
- BUFI=ER FULL
' - - - - - - - - CPBF -
~~~F~tNF~rtRAMETER
- COMMAND'8UFFER FULL
L~=========CBF
eBSY - COMMAND BUSY
• Figure 18. StatuI Realste, Format
Command Phase Software
Recalling the Command phase description il1 an earlier
section, the CPU starts the Command phase by writing a
command byte into the 8273 Command.register. If further information about th.e command is required by the
8273, the CPU writes this information into the Parameter
register. Figure 19 is a flowchart of the Command
phase. Notice that the CBSY and CPBF bits of the
Status register are used to handshake the command
and parameter bytes. Also note that the, chart shows
that a command may not be issued if the Status register
indicates the 8273 is busy (CBSY = 1). If a command is
issued while CBSY = 1, the original command Is over·
written and lost. (Remember that CBSY signifies the
command phase is in progress and not the actual execution of the command.) The flowchart also Includes a
Parameter buffer full check. The CPU must wait until
CPBF = 0 before writing a parameter to the Parameter
register. If a parameter Is issued while CPBF= 1, the
previous parameter Is overwritten and lost. An example
of command output assembly language software Is provided in,Figure 20a. This software assumes that a com·
mand buffer exists in memory. The buffer is pOinted at
by the HL register. Figure 20b shows the command buf.
fer structure.
The 8273 is a full duplex device, i.e., both the transmitter
and receiver may be executing commands or passing interrupt results at any given time. (Separate Rx and Tx interrupt pins and result registers are provided for this
reason.) However, there is only one Command register.
Thus, the Command register must be. used for only one
command sequence 'at a time and the transmitter and
receiver may never' be simultaneously in a' command
;FUNCTION: COMMAND DISPATCHER
; INPUTS: HL - COMMAND aUF F ER ADDRESS
; OUTPUTS: NONE
JCALLS: NONE
; DESTROYS :
_A,~,H,L,F/F· S
,DESCRIPTION: CMDOUT ISSUES THE COMMAND + PARAMETERS
; IN THE COMMAND BUFFER POINTED AT BY HL
,
CKOOUT; LXI
MOV
INX
eKDI:
IN
RLC
JC
CMo2:
MOV
OUT
MOV
ANA
RZ
INX
OCR
CMD3:
IN
ANI
JNZ
MOV
OUT
JM~
H,CMDBUFIPOINT HL AT BUFFER
B,M
; 1ST ENTRY IS PAR. COUNT
H
; POINT AT COMMAND BYTE
STAT73
;READ 8273 STATUS
;ROTATE CBSY INTO CARRY
eMDI
;WAIT UNTIL CBSY-"
A,M
:MOVE COMMAND BYTE TO A
COMM73
: PUT COMMAND IN COMMAND REG
A, B
; GET PARAMETER COUNT
iTEST IF ZERO
A
; IF " THEN DONE
H
B
STAT? 3
CPBF
CMD3
A,M
PARM73
CMD2
;NOT DONE, so POINT AT NEXT PAR
; DEC PARAMETER COUNT
;READ 8-273 STATUS
;'l'EST CPSF BIT
;WAIT UNTIL CPBE IS "
;GET PARAMETER FROM SUFFER
;OUTPUT PAR TO PARAMETER BEG
;CHECK IF MORE PARAMETERS
Figure 2OA. Com....nd P..... Sollwera
AFN.()Q611A
APPLICATIONS
+4
PARAMETER 3
+3
+2
PARAMETER 2
PARAMETER 1
+1
COMMAND
CMDBUF:
PARAMETER COUNT
Result register to obtain the immediate result. The
Result register provides only the results from immediate commands.
Example software for handling immediate results Is
shown in Figure 21. The routine returns with the result
in the accumulator. The CPU then uses the result as is
appropriate.
-HL
All non·immediate commands deal with either the transmitter or receiver. Results from these commands are
provided in the Txl/R (Transmit Interrupt Result) and
Rxl/R (Receive Interrupt Result) registers respectively.
Results in these registers are conveyed to the CPU by
the TxlRA and RxlRA bits of the Status register. Results
of non-immediate commands consist"f one byte result
interrupt code indicating the condition for the Interrupt
and, if required, one or more bytes supplying additional
information. The interrupt codes and the meaning of the
additional results are covered following the detailed
command description.
Execution Phase Software
During the'ExeCution phase, the operation specified by
the Command phase Is performed. If the system utilizes
DMA for data transfers, there Is no CPU Involvement
during this phase, so no software Is required. If non·
DMA data transfers are used, either interrupts or polling
is used to signal a data transfer request.
For interrupt·driven transfers the 8273 raises the appro·
priate INT pin. When responding to the interrupt, the
CPU must determine whether it is a data transfer request or an Interrupt signaling that an operation is com·
plete and results are available. The CPU determines the
cause by reading the Status register and interrogating
the associated IRA (Interrupt Result Available) bit (Tx·
IRA forTxlNTand RxlRA for RxINT).lf the IRA= 0 the in·
terrupt is a data transfer request. If the IRA:' 1, an
operation is complete and the associated Interrupt
Result register must be read to determine the comple·
tion status (good/bad/etc.). A software interrupt handler
implementing the above sequence is presented as part
of the Result phase software.
When polling is used to determine when data transfers
are required, the polling routine reads the 'Status
register looking for one of the INT bits to be set. When a
set INT bit is found, the corresponding IRA bit is ex·
amined. Like in the interrupt·driven case, if the IRA = 0, a
data transfer is required. If IRA = 1, an operation is complete and the Interrupt Result register needs to be read.
Again, example polling software is presented in the next
section.
Non-immediate results are passed to the CPU in
,response to either interrupts or polling of the Status
register. Figure 22 illustrates an interrupt-driven result
handler. (Please note that all of the software presented
in this application note is not optimized for either speed
or code efficiency. They are provided atl a guide and to
illustrate concepts.) This handler provides for interruptdriven data transfers as was promised in the last section. Users employing DMA-based transfers do not need
t.he lines where the IRA bit is tested for zero. (These
hnes are denoted by an asterisk in the comments column.) Note that the INT bit is used to determine when all
results have been read. All results must be read. Otherwise, the INT bit (and pin) will remain high and further interrupts may be missed. These routines place the
results in a result buffer pOinted at by RCRBUF and
TxRBUF.
A typical result handler for systems utilizing polling is
shown in Figure 23. Data transfers are also handled by
this routine. This routine utilizes the routines of Figure
22 to handlE! the results.
At this point, the reader should have a good conceptual
feel about how the 8273 operates. It is now time for the
particulars of each command to be discussed.
Result Phase Software
During the Result phase the 8273 notifies the CPU of the
outcome of a command. The Result pha,se is initiated by
either a successful completion of an operation or an error detected during execution. Some cpmmands such
as reading or writing the I/O ports provide irtimediate
results, that is, there is essentially no delay from the
issuing of the command and when the result is available. Other commands such as frame transmit, take
time to complete so their result is not available im·
mediately. Separate result registers are provided to
distinguish these twO types of commands and to avoid
interrupt handling for simple results.
FUNCTION: IMDRLT
INPUTS: NONE
OU'l'PUTS: RESULT REGISTER IN A
CALLS: .{\,lONE
DES'l'ROYS: A, F IF I 5
Of:;5CI<.IpTION: IMDRLT IS CALLED AF'l'£R A CMDOUT FOR AN
IMMl:.£lIATE COMMA~D TO READ THE. RESULT RBGISTER
MDRL'l': IN
ANI
JZ
IN
Immediate results are provided in the Result register.
Validity of information in this register is indicated to the
CPU by way of the CRBF bit in the Status register. When
the CPU completes the Command phase of an im·
mediate command, it polls the Status register waiting
until CRBF = 1. When this occurs, the CPU may read the
kCT
STAT71
iRbAD 8271 STATUS
CkeF
_TEST IF RESULT REG Rt.AOY
;WAIT IF CRBF=0
IMDRLT
RESL 7 '1
1 RE-AD RESllLT REGISTER
;RE.'l'URN
Figure 21. Immediate Ruult Handle,
7-45
AfN.OO811A
APPLICATIONS
:
~~=~~~ ~C:~F: i~~::UPT
J CALLS I
NOltE
,
,FUNCTION: POLOP
,INPUTS. NONE
iOUT~UTS. C-. (NO STATUS)., -I '(RX COMPLETION),
,
-2 (TX COMPLETION), -1 (BOTH)
,CALLS. TXI, RXl
,DESTROYS: B,C
,DESCRIPTION. POLOP IS CALLED TO POLL THE 8273 FOR
,DATA TRANSFERS AND COMPLETION RESULTS.
THE
,ROUTINES TXI AND RXI ARB USED FOR THE ACTUAL
,TRANSFE)rmation should be Invalidated. Thill applies to all receiver
error conditions.) Note that the FCS, either transmitted or
'
received, is 'never available to the CPU.
The Abort Detect result occurs whenever the receiver
sees either anSDLC (81s) or an HDLC (71s), depending
on the Operating Mode register. However, the intervenIng Abort character between a closing flag and an Idle
does not generate an interrupt. If an' Abort character
(seen by an active receiver within a frame) is not, preceded bY a flag and Is followed by an Idle, an interrupt
will be generated for the Abort, followed by an Idle Inter
The DMA Overrun result.results from the DMA controller
being too slow in extracting data from the 8273, I.e., the
~ signal Is not returned before the next received
byte Is ready for transfer. The receiver Is disabled if this
error condition occurs. ,
The Memory Buffer Overflow result occurs when the
number of received bytes exceeds the receiver buffer
length supplied by the Bo and B, parameters In the
receive command. The receiver Is disabled.
The Carrier Detect Failure result occurs when the CD
pin goes high (inactive) during reception of a frame. The '
cr> pin Is used to qualify reception and must be active
by the time the address field starts to be received. If ~
Is lost during the frame, a CI5 Failure Interrupt is
generated and the receiver is disabled. No Interrupt is
generated If CD goes inactive between frames.
If a condition occurs requiring an interrupt be generated
before the CPU has finished reading the previous interrupt results, the second interrupt is generated after the
current Result phase'is complete (the RxlNT pin and
status bit go low then high). However, the interrupt
result for this second interrupt will be a Receive Interrupt Overrun. The actual cause of the second Interrupt Is
lost. One case where this may occur Is at the'end of a
received frame where the line goes Idle. The 8273
generates a received frame Interrupt after the Closing
flag and then 15-blt times later, generates an Idle Detect
interrupt. If the l!1terrupt service routine is slow in
reading the first Interrupt's results, the Internal Rxl/R
register stili contains result information when the Idle
Detect Interrupt occurs. Rather than wiping out the
, prev,lous results, the 8273 adds a Receive Interrupt Overrun result as an extra result. If the system's Interrupt
structure Is such that the second,lntElrrupt is not
acknowledged (interrupts are stili, disabled from the first
Interrupt), the Receive Interrupt Overrun result Is read as
an extra result, after those from the first Interrupt. If the
second interrupt Is serviced, the Receive Interrupt Overrun Is returned as a single result. (Not~, th~t the INT pins
supply the necessary transitions to support a Program-
. 7-49
AfN.OO811A
APPLICATIONS
mabie Interrupt Controller such as the Intel 8259. Each
interrupt generates a positive-going edge on the appropriate INT pin and the high level is held until the Interrupt is completely serviced.) In general, it Is possible to
have interrupts occurring at one character time intervals. Thus the interrupt handling software must have at
least that much response and service time.
At the end of the frame, the transmitter interrupts the
CPU (the interrupt results are discussed shortly) and
returns to either Idle or Flag Stream, depending on the
Flag Stream bit of the Operating Mode register. If RTS
was active before the transmit command, the 8273 does
not change It. If it was inactive, the 8273 will deactivate
it within one charactE!r time.
The occurrence of Receive Interrupt Overruns Is an Indication of marginal software design; the system's Interrupt response and servicing time is not sufficient for the
data rates being attempted. It is advisable to configure
the interrupt handling software to simply read the interrupt results, place them Into a buffer, and clear the Interrupt as quickly as possible. The software can then examine the buffer for new results at its leisure, and taKe
appropriate action. This can easily be accomplished by
using a result buffer flag that indicates when new
results are available. The Interrupt handler sets the flag
and the main program resets it once the results are
retrieved.
Loop TransmIt
Both SDLC and HDLC allow frames which are of arbitrary length (>32 bits). The 8273 handles this N-bit
reception through the high order bits (D 7-D51 of the
.result code. These bits code the number of valid received bits In the last received information field byte.
This coding is shown In Figure 30. The high order bits of
the received partial btye are indeterminate. [The address, control, and information fields are transmitted
least significant bit (Ao) first. The FCS is complemented
and transmitted mos,t Significant bit first.]
TransmIt Commands
The 8273 transmitter is supported by three Transmit
commands and three corresponding Abort commands.
TransmIt Frame
The Transmit Frame command simply transmits a
frame. Four parameters are required when Buffered
mode Is selected and two when It is not. In either case,
the first two parameters are the least and the most'
significant bytes of the desired frame length (Lo, L,). In
Buffered mode, Lo and L, equal the length in bytes of
the desired Information field, while in the non-Buffered
mode, Lo and L, must be specified as the infqrmation
field length plus two. (Lo and L, specify the number of
data transfers to be performed.) In Buffered mode, the
address and control fields are presented to the transmitter as the third and fourth parameters respectively. In
non-Buffered mode, the A and C fields must be passed
as the first two data transfers.
When the Transmit Frame command is· Issued, the 8273
makes RTS (Request-to-Send) active (pin low) If it was
not already. It then YIIalts until CTS (Clear-to-Send) goes
active (pin low) before starting the frame. If the Prefraple
Sync bit in the Operting Mode register is set, the transmitter prefaces two characters (16 transitions) before
the opening flag, If the Flag Stream bit is set in the
Operating Mode register, the frame (including Preframe
Sync if selected) is started on a flag boundary. Otherwise the fram.e starts on a character boundary.
7-50
Loop Transmit Is similar to Frame Transmit (the parameter definition Is the same). But since it deals with loop
configurations, One Bit Delay mode must be selected.
If the transmitter is not In Flag Stream mode when this
command is issued, the transmitter walts until after a
received EOP character has been converted to a flag
(this is done automatically) before transmitting. (The
one 'bit delay is, of course, suspended during transmit.)
If the transmitter is already in Flag Stream mode as a
result of a selectively received frame during a Selective
Loop Receive command, transmission will begin at the
next flag boundary for Buffered mode or at the third flag
boundary for non-Buffered mode. This discrepancy is to
allow time for enough data transfers to occur to fill up
the internal transmit buffer. At the end of a Loop Transmit, the One Bit Delay mode is re-entered and the flag
stream mode is, reset. More detailed loop operation Is
covered later.
Transmit Transparant
The Transmit Transparent command enables the 8273 to
transmit a block of raw data. This data Is without SDLC
protocol, i.e., no zero bit Insertion, flags, or FCS. Thus j(
is possible to construct and transmit a Bi-Sync message
for front-end processor switching or to construct and
transmit an SDLC message with incorrect FCS for diagnostic purposes. Only the Lo and L, parameters are used
since there are not fie ids in this mode. (the 8273 does
not support a, Receive Transparent command.)
Abort Commands
Each of the above transmit commands has an associated Abort command. The Abort Frame Transmit command causes the transmitter to send eight contiguous
ones (no zero bit insertion) immediately and then revert
to either idle or flag streaming baSed on the Flag Stream
bit. (The 8 1s as an Abort character Is compatible with
both SDLC and HDLC.)
For'Loop Transmit, the Abort Loop Transmit 'command
causes the transmitter to send one flag and then revert
to one bit delay. Loop protocol depends upon FCS
errors to detect aborted frames.
The Abort Transmit Transparent simply causes the
transmitter to revert to either idles or flags as a function
of the Flag Stream mode speCified.
The Abort commands require no parameters, however,
they do generate an interrupt and return a result When
complete.
A summary of the Transmit commands is shown in
Figure 31. Figure 32 shows the various transmit interrupt result codes. As in the receiver operation, the
transmitter generates interrupts, based on either good
AF~llA
APPLICATIONS
completion of an operation or an error condition to start
the Result phan.
writing of the 01 and the 00. The action taken Is the
same as If a hardware reset Is performed, namely:
The Early Transmit Interrupt result occurs after the Idst
data transfer to the 8273 If the Early Transmit Interrupt
bit Is set In the Operating Mode register. If the 8273 Is
commanded to transmit again within two character
times, a single flag will separate the frames. (Buffered
mode must be used for a Single flag to separate the
frames. If non·Buffered mode Is selected, three flags
will separate the frames.) If this time constraint Is not
met, another Interrupt Is generated and multiple flags or
Idles will separate the frames. The second Interrupt Is
the normal Frame Transmit Complete Interrupt. The
Frame Transmit Complete result occurs at the closing
flag to signify a good completion.
1. The modem control outputs are forced high
Inactive).
2. The 8273 Status register Is cleared.
3. Any commands In progress cease.
4. The 8273 enters an Idle state until the next command Is Issued.
Modem Control Commends
The modem control ports were discussed earlier In the
Hardware section. The commands used to manipulate
these ports are shown In Figure 33. The Read Port A and
Read Port B commands are Immediate. The bit definition for the returned byte Is shown In Figures 13 and 14.
Do not forget that the returned value represents the
logical condition of the pin, I.e., pin active (low) = bit
set.
The OMA Underru'n result Is analogous to the OMA Overrun result In the receive,. Since SDLC does not support
Intraframe time fill, if the OMA controller or CPU does
not supply the dllta In time, the frame must be aborted.
The action taken by the transmitter on this error Is automatic. It aborts the frame just 'as If an Abort command
had been Issued.
PORT
C.lear-to-Send Error result Is generated If CTS goes Inac·
tlve during a frame transmission. The frame Is aborted
I
as above.
A INPUT
BOUTPUT
The Abort Complete result Is self-explanatory. 'Please
note however that no Abort Complete Interrupt Is
generated when an automatic abort occurs. The next
command type consists of only one command.
COMMAND
TRANSMIT FRAME
ABORT
LOOP TRANSMIT
ABORT
TRANSMIT TRANSPARENT
ABORT
HEX
CODE
C8
CC
CA
CE
co
CD
PARAMETERS'
~.Ll.A.C
NONE
~.Ll.A.C
NONE
~.Ll
NONE
COMMAND
READ
READ
SET
RESET
HEX
CODE
22
23
A2
83
PARAMETER
REG
RESULT
PORT VALUE
NONE
NONE
PORTYALUE
SET MASK
NONE
RESET MASK
NONE
Figure 33. Modem Control Commend SUm_ry
The Set and Reset Port B commands are similar to the
Initialization commands In that they use a mask parameter which defines the bits to be changed. Set Port B
utilizes a logical OR mask and Reset Port B uses a
logical ANO mask. Setting a bit makes the pin active
(low). Resetting the bit deactiVates the pin (high).
RESULTS
TxUR
TIC
TIC
TIC
TIC
TIC
TIC
To help clarify the numerous timing relationships that
occur and their consequences, Figures 34 and 35 are
provided as an illustration of several typical sequences.
It Is suggested that the reader go over these diagrams
and re-read the appropriate part of the previous sections
If necessary.
'A AND C ARE PASSED AS PARAMETERS IN BUFFERED. MODE ONLY.
Figure 31. Transmitter Commend SUmmery
HLDC CONSIDERATIONS
TIC
Dr-Do
TRANSMITTER INTERRUPT RESULT CODE
01100 EARLY Tx INTERRUPT
01101 FRAME Tx COMPLETE
01110 DMA UNDERRUN
01111 CLEAR TO SEND ERROR
.000 10000 ABORT COMPLETE
000
000
000
000
TxSTATUS
AFTER INT
The 8273 supports HOLC as well as SOLC. Let's discuss
how the 8273 handles the three basic HOLC/SOLC dif. ferences: extended addressing, extended control, arid
the 7 1s Abort charjlcter.
ACTIVE
IDLE OR FLAGS
ABORT
ABORT
IDLE OR FLAGS
Recalling Figure 4A, HOLC supports an address field of
indefinite length. The actual amount of extension used
Is determined by ,he least significant bit of the characters immediately following the opening flag. If the LSB
is 0, more address field bytes follow. If the LSB is 1, this
byte Is the final address field byte. Software must be
used to determine this extension.
Figure 32. Trensmllter InterTupt ....ult Codes
Reset Command
The Reset command provides a software reset function
for the 8273. It Is a special case and does not utilize the
normal command Interface. The reset facility is provided
In the Test Mode register. The 8273 Is reset by simply
'outputting a 01H followed by a OOH to the Test Mode
register. Writing the 01 followed by the 00 mlmlcks the
action required by the hardware reset. Since the 8273 requires time to process the reset internally, at lflast 10
cycles of the r2lCLK clock must occur between the
If non-Buffered mode Is used, the A, C, and I fields are In _
memory. The software must examine the initial characters to find the el(tent of the address field. If Buffered
mode Is used, the characters corresponding to the
SOLC A and C fields are transferred to the CPU as Interrupt results. Buffered mode assumes the two characters
following the opening flag are to be transferred as interrupt results regardless of content or meaning, (The 8273
7-51
AfN.OO811A
APPLICATIONS
does not know whether it is being used in an SOLe or an
HOLC environment.) In SOLC, these characters are
necessarily the A and C field bytes, however in HOLC,
their meaning may change depending on the amount of
extension used. The software must recognize this and
examine the transferred results as possible address
,
field extensions.
Frames may still be selectively received as Is needed for
secondary stations. Th,e Selective Receive command is
still used. This command qualifies a frame reception on
the first byte following the opening flag 'matching either
of the A1 or A2 match byte parameters. WhUe this does
not allow qualification over the complete range of H OLC
addresses, it does perform ,a qualification on the first
address byte. The remaining address field bytes, if any,
are then examined via software to completely qualify
the frame.
Once the extent of the address field is found, the following bytes form the control field. The same LSB test used
for the address field is applied to these bytes to determine the control field extension, up to two bytes maximum. The remaining frame bytes in memory represent
the iilformatlon field.
The Abort character difference is handled in tHe
Operating Mode register. If the HOLC Abort Enable bit is
set, the reception of seven contiguous ones by an active
receiver will generate an Abort Detect Interrupt rather
than eight ones. (Note that both the HOLC Abort Enable
bit and t~e EOP Interrupt bit must not be set simultaneously.)
Now let's move on to the SOLC loop configuration
discussion.
CARRIER DETECT
LOOP CONFIGURATION
Aside from use in the normal data link applications, the
8273 is extremely attractive in lOOp configuration due to
the special frame-level loop commands and the Digital
Phase Locked Loop. Toward this end, this section
details the hardware and software considerations when
using the 8273 In a loop application.
The loop configuration offers a simple, low-cost solution for systems with multiple stations within a small
physical location, I.e., retail stores and banks. There are
two primary reasons to consider a loop configuration.
The interconnect cost is lower for a loop over a multipoint configuration since only one twisted pair or fiber
optic cable is used. (The loop configuration does not
support the passing of distinct clock signals from station to station.) In addition, loop statiOns do not need
the intelligence of a multi-point station since the loop
protocal is simpler. The most difficult aspects of loop
station design are clock recovery and implementation of
one bit delay (both are handled neatly by the 8273).
Figure 36 illustrates a typical loop configuration with
one controller and two down-loop secondaries. Each
station must derive its own data timing from the
received data stream. Recalling our earlier discussion of
the OPLL notice that TxC and RxC clocks are provided
by the
output. The only clock required in the
secondaries is a simple, non-synchronized clock at 32
times fhe desire'd baud rate. The controller requires bofh
32x and 1 x clocks. (The 1 x is usually implemented by
dividing the 32 x clock with a 5-bit divider. However,
there is no synchronism requirement between these
clocks so any convenient implementation may be used.)
DPtt
~
\'---
RxD
Rx COMMAND
t I l
A
OR
C
t
I,
~~~:~N~~~~~~i~""'''''''------------~'--I-7,--.:..---------NON·BUFFERED
.MO~E
1
FRAME
COMPLETE
1
POSSIBLE
IDLE INT
IN~~::~~~~-------'-:'---------------------A: ERROR, FREE FRAME RECEPTION
CARRIER DETECT
~
Rx COMMAND
\\\\\\\\\\\\
!
CD
CD
FAILURE
IN~~~:~~~~_-,--_ _~_ _..!...::F::AI:::LU::.::R:::E....:......:_.:-..:-...:......:.I-"...:......:.-,--_..:..._ _ _ __
B. CARRIER DETECT FAILURE DURING FRAME RECEPTION
Figure 34. $ample Recel..~ Timing Dlagrems
AfN.00811A
APPLl9ATIONS
Tx COMMAND
I
TxD
L
L
RTS~
cTS------'
IA
Ic
1'11'2
OR~~~:~~~~~~=~~------------,---i---i----------------------------------------------------NON·BUFFERED
1
IN~~::~~~~--------------M-O-D-E----------------------_-------------------F-R-A-M-E_C_O_M_P_L__
ETE
A. ERROR·FREE FRAME TRANSMiSSION
1ST FRAME
TxCOMMAND
2ND FRAME
I I I I I
I
I I I I I
TxD
RTS~
OR~~~:~N~~~~~:;;-~~-------------~I-II----------------------------------I-'-1
____1_'2
___________
tEARLY Tx
IN~~::~----------------------------~----------------------------------------B. DIAGRAM SHOWING Tx COMMAND QUEiNG AND EARLY Tx INTERRUPT
(SINGLE FLAG BETWEEN FRAMES) BUFFERED MODE IS ASSUMED.
TxCOMMAND
I
I
'--------
CTS----......J
OR~~~:~N;~~~~----------~t-A----~t-C----~t-'l-----t-12----~I-'3----------
__________________
1 CTS
IN~~::~~~~--------------------------------~--------O=R~A~~R~yR~O~R~-------------C. CTS FAILURE (OR OTHER ERROR) DURING TRANSMISSION
ERROR
INTERRUPT
. Figure 35. Sample !~n8mIH.r TIming Diagrams
7-53
AfN.OO811A
APPLICATioNS
the secondary terminates Its rapeater function and Inserts Its response frame (with multiple preceding flags
If necessary). After the closing flag of the response, the
secondary re-enters Its repeater function, repeating the
up-loop controller 1s. Notice that the final zero of the
response's closing fiag,plus the repeated 1s from the
controller form a new, EOP\ for the next down-loop
secondary. This new EOP allows the next secondary to
insert a response If It desires. This gives each secondary'a chance to respond.
'
hLOOP
OSCILI,ATOR
OR
DIVIDER
ToC
RoD
ToD
1273
LOOP
ToD I---If--f--I RxD
TERIlINAL
Back at the controller, after the polling frame has been
transmitted and the continuous 1s started, the controller walt's until It receives an EOP. Receiving an EOP
signifies to the controller that the original frame has
propagated around the loop followed by any responses
Inserted by ~he ~condarles. At this point, the controller
may either send flags to Idle the loop or transmit the
next frame. Let's assume that the, loop Is Implemented
completely with the 8273s and describe the command
flows for a typical controller and secondary.
1273
LOOP
T~RIIINAL
The loop controJler Is Inltlallz8d with commands which
specify that the NAZI, Preframe Sync, Flag Stream, and
EOP Interrupt modes are set. Thus, the controller encodes and decodes all data using NRZI format. Preframe
Sync mode specifies that all transmitted frames be
prefaced with 16 line transitions. This ensures that the
minimum of 12 transitions needed by the DPLLs to lock
after an all 1s line have occurred by the time the secondary sees a frame's opening flag. Setting the Flag Stream
mode starts the transmitter sending fiags which Idles
the loop. AM the EOP Interrupt mode specifies that the
controller processor will be Inter~upted whenever the
active receiver sees an EOP, Indicating the completion
of a poll cycle.
Figure 31. SDLC Loop AppIICIIUon
A quick review of loop protocol Is appropriate. All communication on the loop Is controlled by the loop controller. When the controller wishes to allow the secondaries to transmit, It sends a polling frame (the control field contains a poll code) followed by an EOP (Endof-Poll) character. The secondaries use the EOP
character to capture the loop and Insert a rasponse
frame as will be discussed shortly.
When the controller wishes to transmit a non-polling
frame, It simply executes a Frame Transmit command.
Since the Flag Stream mode Is set, no EOP Is formed
after the closing flag. When a polling frame Is to be
transmitted, a General Receive command Is executed
first. This enables the receiver aM allows reception of
all Incoming frames; namely, the original polling frame
plus any ,response frames Inserted by the secondaries.
After the General Receive command, the frame is transmitted with a Frame Transmit command. When the
frame Is complete, a transmitter interrupt Is generated.
The loop controller processor uses this Interrupt to
reset Flag Stream mode. This causes the transmitter to
start sending all1s. An EOP Is formed by the last flag
and the first 7 1s. This completes the loop controller
transmit sequence.
The secondaries normally operate In the rapeater mode,
retransmitting received data with one bit time of delay.
All received frames ara repeated. The secondary uses
the one bit time of delay to capture the loop.
When the loop Is Idle (no frames), the' controller transmits continuous flag characters. This keeps transitions
on the loop for the sake of down-loop phase locked
loops. When the controller has a non-polling frame to
transmit, It simply transmits the frame and continues to
send flags. The non-polling frame Is then repeated
around the loop and the controller receives It to signify a
complete traversal of the loop. At the particular sec;ondary addressed by the frame, the data Is transferred to
• memory while being repeated. Other secondaries simply
repeat It.
At any time following the start of the polling frame
transmission the loop controller receiver will start
receiving frames. (The exact time difference depends, of
course, on the number of down-loop secondaries due to
each Inserting one bit time of delay.) The first received
frame Is simply the original polling frame. However, any
additional frames are those Inserted by the secondaries.
The loop controller processor knows all frames have
been received when it sees an EOP Interrupt. This interrupt Is generated by the 8273 since the EOP Interrupt
mo~e was set during initialization. At this pOint, the
transmitter may be commandeq either to enter Flag
If the controller wants to poil the secondaries, It
transmits a polling frame followed by all1s (no zero bit
insertion). The final zero of the closing frame plus the
first seven 1s form an EOP. While repeating, the secondaries monitor their incoming line fqr an EOP. Whe,n IiIn
EOP Is received, the secondary checks if It has any
response for the controller. If not, It simply continues
repeating. If the secondary has a response, It changes
the seventh EOP one Into a zero (the one bit time of
delay allows time for this) and repeats it, f~rmlng a fiag
for the down-loop stations. After this flag Is transmitted,
7-54
~l1A
APPLICATIONS
Strea~ mode, Idling the loop, or to transmit the next
frame. A flowchart of the above sequence is shown In
Figure 37.
The secondaries are initialized with the NRZI and. One
Bit Delay modes' set. This puts the 8273 into the repeater '
mode with the transmitter repeating the received data
with one-tiit time of delay. Since a loop station cannot
transmit until it sees and EOP character, any transmit
command is queued until an EOP is received. Thus
whenever the secondary wishes to transmit a response,
a Loop Transmit command is issued. The 8273 then
walts until it receives an EOP. At this pOint, the receiver
changes the EOP into a flag, repeats It, resets One Bit
Delay mode stopping the repeater function, and sets the
transmitter into Flag Stream mode. This captures the
loop. The transmitter now Inserts its message. At the
closing flag, Flag Stream mode is reset, and One Bit
Delay mode is set, returning the 8273 to repeater func·
tion and forming an EOP for the next down·loop station.
These actions happen automatically after a Loop
Transmit command is issued.
When the secondary wants its receiver enabled, a Selective Loop Receive command is issued. The receiver t.hen
looks for a frame having a match In the Address field.
Once such a frame Is received, repeated, and trans·
ferred to memory, the secondary's processor Is Interrupted with the appropriate Match interrupt result and
the 8273 continues with the repeater function until an
EOP is received, at which point the loop is cap~ured as
above. The processor should use the interrupt to determine If It has a message for the controller. If It does, It
simply issues a Loop Transmit command and things
progress as above. If the processor has no message, the
software must reset the Flag St~eam mode bit In the
Operating Mode register. This will inhibit the 8273 from
capturing the loop at the EOP. (The matCh frame and the
EOP may be separated In time by several frames de·
pending on how many up-loop stations 100~erted messages of their own.) If the timing Is such that the
receiver has already captured the loop when the Flag
Stream mode bit is reset, the mode is exited on a flag
boundary and the frame just appears to have extra clos·
ing flags before the EOP. Notice that the 8273 handles
the queuing of the transmit commands and the setting
and resetting of the mode bits automatically. Figure 38
illustrates the major points of the secondary command
sequence.
INITIALlZE'SET NAZI. ONE
BIT DELAY MODES
RECEIVER
INTERRUPT READ'RxIR
o
o
DENOTES COMMAND'
DENOTES COMMANDS
~ DENOTES INTERRUPT CODes
c:::) DENOTES INTERRUPT CODE
figure 38. Loop Sacondary Flowchart.
Figure 37. Loop Controller Flowchart
7·55
AFN-OIl611A
APPliCAtiONS
When an off·line secondary wishes to come· on-line, 'It
must'do so In a manner which does not disturb data'on
the loop. Figure '39 shows a typical hardware Interface.
The line 1$led Port could be one of the 8273 Port Bout·
pufsand Is"assumed to be high (1) Initially: Thus up-loop
data Is simply passed down·loop with no delay; how·
ever, the receiver may stili monitor data on the loop. To
come on·llne, the secondary Is Initialized with only the
EOP Interrupt mode liet. The up-loop data Is then monl·
tored until an EOP occurs. At this point, the secondary's
CPU is Interrupted with an EOP Interrupt. This signals
the CPU to set One Bit Delay mode In the 8273 and then
to set Port low (active). These actions switch the sec·
ondary's one bit delay into the loop. Since after the EOP
only 1s are traveralng the loop, no loop disturbance occurs. The secondary now walts for the next" EOP, captures the loop, and inserts a "new on-line" message.
This signals the controller that a new secondary exists
and must be acknowledged. After the seCondary receives its acknowledgement, the normal command flow
Is used.
I
I
FlOUr. 40. Raytheon Slock DlllJllllm.
An SDK-85 '(System Design Kit) was used as the core
6085 sys,tem. This system provides up to 4K bytes of
ROM/EPROM,. 512 bytes of RAM, 76 I/O pins, plus two
timers as provided in two 8755 Combination EPROM/I/O
devices and two 8155 Combination RAM/I/OlTlmer
devices. In add.ltlon, 5 interrupt Inputs are supplied on
the 8085. The address, data, and control buses are buffered by the 8212 and 8216 latches and bidirectional bus
drivers. Although it was not used In this application, an
8279 Display Driver/Keyboard Encoder Is included to Interface the on-board display and keyboard. A block
diagram of the SDK-85 Is shown In Figure 41. The 8273,
and associated circuitry was constructed on the ample
wire-wrap area provided for the user.
It is hopefully evident 'from the above, ,discussion that,
the 8273 oJfers a very simple and easy to Implement
solution for designing. loop stations whether they are
controllers or down-loop secondaries.
The example 827318085 system is interrupt-driven and
uses DMA for all data transfers supervised by an 8257
DMA Controller. A 2400 baud asynchronous line, Implemented with an 8251A USART, provides communication
between the software and the user. 8253 Programmable
Interval Timer is used to supply the baud rate clocks for
the 8251A and 8273. (The 8273 baud rate clocks were
used only during initial system debug. In actual operation, the modem supplied these clocks via the RS-232 interface.) Two 2142 1Kx4 RAMs provided 512 bytes of
transmitter and 512 bytes of receiver buffer memory.
(Command and result buffers, plus miscellaneous
variables are stored in the 8155S,) The RS-232 interface
utilized MC1488 and MC1489 RS-232 drivers and
receivers. The schematic of the system is shown in
Figure 42.
F1gU18 38. Loop In'-'-
APPLICATION EXAMPLE
This section describes the hardware and software of the
827318085 system used to verify the 8273 Implementation of SDLC on an actual IBM SDLC Link. This IBM link
was gratefully VOlunteered by Raytheon Data Systems in
Norwood, Mass. and I wish to thank them for their
generous cooperation. The IBM system consisted of a
370 Mainframe, a 3705 Communications Processor, and
a 3271 Terminal Controller. A Comlink II Modem supplied the modem interface and all communications took
place at 4800 baud. In addition to observing correct
responses, a Spectron 0601 B Datascope was used to
verify the data exchanges. A block diagram of ttle
s\,stem Is shown In Figure 40. The actual verification
was accomplished by the 8273 system receiving and
responding to polls ,from the 3705. This method was
'-Ised on both point-ta-point and multi-pOint configurations. No attempt was made to Implement. any higher
protocol software over that of the poll and poll responses Since such software would not affect the verification of the 8273 implementation. As testimony to the
ease of use of the 8273, the system worked on the first
try.
'
One detail to note is the DMA and interrupt structure of
the transmit and receive channels. In both cases, the
receiver is always given the higher priority (8257 DMA
channel 0 has priority over the remaining channels and
the 8085 RST 7.5 Interrupt Input has priority over the
RST 6.5 Input.) Although the choice is arbitrary, this
technique minimizes the chance that received data
could be lost due to other processor or DMA commitments.
'
Also note that only one 8205 Decoder Is used for both
the peripherals' and the inemorys' Chip Selects. This
was done to eliminate separate memory and I/O
decoders sincl! it was known beforehand that neither
address space would be completely filled.
The 4 MHz cry!ltal and 8224 Clock Generator were us8d
only to verify that the 8273 operates correctly at that
maximum spec. speed. In a normal system, the 3.072
MHz clock from the 8085 w,ould be sufficient. (This fact'
was verified du~lng Initial checkout.)
7-56
AfN.OO811A
APPLICATIONS
L __ .J
r~:-')
.
~~~
r---,
INTERRUPT
1118
L __ .J
!NPUTS
~::JJ
f.=r---'
1212 I '
ADDAit~C==~=:=t:=--'=::::t==~~=:==t====~=:t=====~~~===t==Y.L __ ..J
r---,
1
L3~1211
__ .J~CONTROL
CONTROLC===:=+====t====:==~=====t==========\==~
BUS
8US
r - - -,
L ___ J
I
I
I
OPTIONAL A PLACE HAS BEEN PROVIOED ON TIfE PC BOARD fOR THE DEViC& aul' THE
Il£VICEIS NOT INCLUDED
LFigure 41.
,
,"
,"
"
""
'"
" ""
"
. ."
..
101M
"
I
SDK.a5
FunctlonaTBIOCkDlaU1MIl
. ....
iOR
MEMW
.'" ..
SDKes
'"'
Figure 42.
82731SDK-IIS System
7-57
AFN-00611A
AP·PLlCATIONS
The software consists of the normal monitor program
supplied with the SDK-85 and a program to input commands to the 8273 and to display results. The SDK-85
monitor allows the user to read and write on-board RAM,
start execution at any memory location, to single-step
through a program, and to examine any of the 8085's internal registers. The monitor drives either the on-board
keyboard/LED display or a serial TTY interface. This
monitor was modified slightly in order to use the 8251A
with a 2400 baud CRT as opposed to the 110 baud normally used. The 8273 program Implements monitor-like
user interface. 8273 commands are entered by a twocharacter code followed by any parameters required by
that command. When 8273 Interrupts occur, the source
of the interrupt Is displayed along with any results
associated with It. To gain a flavor of how the user/program Interface operates, a sample output is shown in
Figure 43. The 8273 program prompt character is a "- "
and user Inputs are underlined.
Figures 44 through 51 show the flowcharts used for the
8273 program development. The actual program listing
Is included as Appendix A. Figure 44 Is the main status
poll loop. After all devices are initialized and a prompt
character displayed, a loop is entered at LOOPIT. This
loop checks for a change of status in the result buffer or
if a keyboard character has been received by the 8251 or
if a poll frame has been received. If any of these conditions are met, the program branches to the appropriate
routine. Otherwise, the ioop.ls traversed again.
The result buffer is implemented as a 255-byte circular
buffer with two pointers: CNADR and LDADR. CNADR is
the console pOinter. It pOints to the next result to be
displayed LDADR is the load pOinter. It points to the
next empty position in the buffer into which the interrupt handler places the next result. The same buffer is
used for both transmitter and receiver results. LOOPIT
examines these pOinters to detect when CNADR is not
equal to LDADR indicating that the buffer contains
results which have not been displayed. When this occurs, the program branches to the DISPLY routine,
The "SO 05" implements the Set Operating Mode command with a parameter of 05H. This sets the Buffer and
Flag Stream modes. "SS 01" sets the 8273 in NAZI mode
using the 'Set Serial 110 Mode command. The next command specifies General Receiver with a receiver buffer
size of 0100H bytes (Bo 00, Bl 01). The "TF" command causes the 8273 to transmit a frame containing an
address field of C2H and control field of 11H. The information field Is 001122. The "TF" command has a speCial
format. The Lo and Ll parameters are computed from the
number of information field bytes entered.
=
DISPLY determines the source of the undlsplayed
results by testing the first result. This first result is
necessarily the interrupt result code. If this result is
OCH or greater, the result is from a transmitter interrupt.
Otherwise It is from a receiver source. The source of the
result code Is then displayed on the console aiong with
the next four results from the buffer. If the source was a
transmitter interrupt, the routine m.erely repoints the
pOinter CNADR and returns to LOOPIT. For a receiver
source, the receiver data buffer is dispiayed in addition
to the receiver interrupt results before returning to
LOOPIT.
=
After the TF command is entered, the 8273 transmits the
frame (assuming that the modem protocol is observed).
After the closing flag, the 8273 interrupts the 8085. The
8085 reads the interrupt results and places them in a
buffer. The software examines this buffer for new
results and if new results exist, the source of the interrupt is dispiayed along with the results.
START
In this example, the ODH result indica.tes a Frame Complete interrupt. There is only one resuit for a transmitter
interrupt, the interrupt's trailing zero results were included to simplify programming.
CMDREC
LOOPIT
The next event is a frame reception. The interrupt
results are displayed in the order read from the 8273.
The EOH indicates a General Receive interrupt with the
last byte of the information field received on an 8-bit
boundary. The 03 00 (R o, R1) results show that there are
,3H bytes of information field received. The remaining
,·two resuits indicate that the received frame had a C2H
address field and a 34H control field. The 3 bytes of information field are displayed on the next line.
8273 MONITOR Vl.2
i!Ui
-
-
H..J!l.
.!!!L!!2..IU
TFC211OQl122
TxlNT
-
RxlNT FF EE 00
00 00 00 00 00
EO 03 00 C2 34
'--_ _ _..oN
Figure 43. Sample 8273 Monitor ItO
Figure 44. Main StatUI Poll Loop
7-58
AfN.OO611A
APPLICATIONS
Rx
Tx
DISPLAY
RxlNT
MESSAGE
DISPLAY
TxlNT
MESSAGE
Figure 47. TF Subroutlno
ReAD AND DISPLAY
REMAINING
RESULTS
READ AND DISPLAY
REMAINING
RESULTS
Figure 45. DISPLY Subrou~ti_n.;.e_ _ _ _ _ __
Figure 46. TxPOL Subroutine
PARAMETER #2
PARAMETER #1
COMMAND
B
~I
-# OF PARAMETERS
I
Figure 49. COMM Subroutine with Command Bull.r For"",t
Figure 46. GETCMD Subroutl~e.
7-59
AFN.00611A
APPLICATIONS
EXIT TO
MONITOR
the PolI·Response mode is selected, the prompt
character is changed to a '+'. If a frame is received
which contains a prearranged poll control field, the
memory location POLIN is rt;lade nonzero by the receiver
interrupt handler. LOOPITexamines this location and if
it is nonzero, causes a branch to the TxPOL routine. The
TxPOL routine clears POLIN, sets a pointer to a special
command buffer at CMDBUF1, and issues the command
by way of the COMM2 entry in'the COMM routine. The
'special command buffer' contains the appropriate
response frame for the poll frame received. These ac·
tions only occur when the Z command has changed the
prompt to a '+'. If the prompt is normal' -', polling
frames are displayed as normal frames and no response
is transmitted. The PolI·Response mode was used duro
ing the IBM tests.
Figure SO. Txl (Transmitter Interrupt) Routine
If the result buffer pOinters indicate an empty buffer, the
8251 A is polled for a keyboard character. If the 8251 has
a character, GETCMD is called. There the character is
read and checked if legal. Illegal characters simply
cause a reprompt. Legal characters indicate the start of
a command input. Most commands are organized as two
characters signifying the command action; Le., GR General Receive. The software recognizes the two char·
acter command code and takes the appropriate action.
For non·Transmit type commands, the hex equivalent of
the command is placed in the C register and the numbeJ
of parameters associated with that command is placed
in the B register. The program then branches to the
COMM routine.
~EXITTO
~-~MONITOR
READ RESULTS AND
PLACE IN RESULT
BUFFER
The COMM routine builds the command buffer by
reading the required number of parameters from the
keyboard and placing them at the buffer pOinted at by
CMDBUF. The routine at COMM2 then issues this com·
mand buffer to the 8273.
If a Transmit type command i.s specified, the command
buffer is set up similarly to the the COMM routine;
however, since the information field data is entered
from the keyboard, an' intermediate routine, TF, is
called. TF loads the transmit data buffer pOinted at by
TxBUF. It coulltS the number of data bytes entered and
loads this number into the command buffer as Lo,
L l . The command is then issued to the 8273 by jumping
to CMDOUT.
One command does not directly result in a command be·
ing issued to the 8273. This command, Z, operates a
software flip· flop which selects whether the software
wiU respond automatically to received polling frames. If
Figure 51., Rxl (Recevler tnterrupt) Routine
7-60
AFN-006llA
APPLICATIONS
The final two software routines are the transmitter and
receiver Interrupt handlers. The transmit Interrupt
handler, Txl, simply saves the registers on the stack and
checks if loading the result buffer will fill It. If the result
buffer will overfill, the program is exited and control Is
passed to the SDK-85 monitor. If not, the results are
read from the Txl/R register and placed In the result buffer at LDADR. The DMA pointers are then reset, the
registers restored, and Interrupts enabled. Execution
then returns to the pre-Interrupt location.
The receiver Interrupt handler, Rxl, Is only slightly more
complex. As In Txl, the registers are saved and the
possibility of overfilling the result buffer Is examined. If
the result buffer Is not full, the results are read from
RxllR and placed In the buffer. At this point the prompt
character Is examined to see if the Poll-Response mode
Is selected. If so, the control field is compared with two
possible polling control fields. If there Is a match, the
special command buffer is loaded and the poll Indicator,
POLIN, is made nonzero. If no match occurred, no action
Is taken. Finally, the receiver DMA buffer pointers are
reset, the processor status restored, and Interrupts are
enabled. The RET Instruction returns execution to the
pre-Interrupt location.
This completes the discussion of the 827318085 system
design.
CON~LUSION
This application note has covered the 8273 In some
detail. The simple and low cost loop configuration was
explored. And an 8273/8085 system was presented as a
sample design Illustrating the DMAllnterrupt-driven Interface. It is hoped that the major features of the 8273,
, namely the frame-level command structure and the
Digital Phase Locked Loop, have been shown to be a
valuable asset In an SOLe system design.
AFN-00611A
APPLICATIONS
APPENDIX A
7-62
AFN-00611A
APPLICATIONS
APPENDIX A
ASII88 :F1: RAVT73. SRC
ISI5-II 8889,8885 I1ACRO ASSEI'EILER, X18S
LOC
(lIJ
IIODULE
PAGE
1
SOURCE STAmENT
SEQ
1 $NOPAGING IlOO85 1I0C0ND
2 TRUE
EQU'
80H
;ee FOF RAYTHEON
EOO
80H
EQU
09H
; 00 FOR NORMAL RESPONSE
; FF FOR LOOP RESPONSE
· 90 FOF NO Doo
J;
4 TRUE1
· FF FOP. SELF-TEST
5.
6 DEM
7.
· FF FOP. DE~1O
8;
9;
19 •GENERAL 82;'1 MONITOR WITH RflYTHEOIl POLL MODE ADDED
11;
17
18
19
20
21
22
21
24
;
;
,COttIAND 51JPPOFTED' ARE'
;
•
;
,
;
,
RS
55
PO
50
PO
!lP
-
25 ,
SF -
26 ,
27 ,
TF AF -
28 ;
SP -
29 ;
J0 ;
RP ~ -
:>1 ,
58 -
12 "
n;
SL TL -
74 ;
Z -
RESET SERIAL 1/0 I100E
SET SERIAL It'O MODE
RESET OPERATI NGI100E
SET OPERATING MODE
PECEIYER r'ISABLE
GENERAL RECEIVE
SELECTIVE RECEIVE
TRANSMIT FRAI1E
ABORT FilM
SET PORT B
RESET POPT B
RESET 8NE BIT DELAY (PAR = 7F)
SET ONE BIT DELAY (PAP = 89',
SELECTIVE LOOP RECEIVE
TRANSMIT LOOP
CHANGE MODES FLIP/FLOP
38 ;
.940,.: -too<*"""*~*********""""**"*_'i<*****_"'''''''*''''''***_*___*_**
41 ; NOTE,
42 ,
'SET' COI'1Mf1lOS IMPLEMENT LOGICAL OR' FlH:TIONS
'RESET' COMMANDS IMPLEMENT LOGI CAL 'AND' FUNCTIONS
4] •
44 • ~'I"''''''*"'**'''''*~;'''*'''*'''''''''*''*'''**-******-''''''***''''''**''''''''''''**--*****45.:
46 "BUFFERED MODE t1UST BE SELECTED WHEN SELECTIVE ~ECEII/E IS USE&.
4;' ;
,
48 . COlt1AND- FORMAT IS "COHI'IAND ',2 LTRS,,' "PAR.Ii' ,'PAR. 12' ETC,
49.:
'5.a ; THE TRANSt1IT FP.fII'IE CIltR{I FORMAT IS: 'TF' 'A' 'C' 'BUFFER CONTENTS'.
51 ;
NO LENGTH COUNT 15 NEEDED, BlfFER CONTENTS IS ENDED WITH A CR,
52 ;
51 ; .*'I<.".*"''',,*-***''******~'''--'''''''*-*****-*******---***
54;
55 ,POLLEro MOOE
WHEN POLLE[' MODE IS SELECm (DENOTED BY A "+' PROMPT), IF
7-63
APPLICATIONS
56;
A SNRM-P OR RR(8)-P IS RECEII/ED, A RESPONSE FRAtIE OF NSA-F
OR 1<.R(8H IS TAANS/'IITTED. OTHER CIlIt1ANDS OPERATE NORl1AU.Y.
57 ;
62 ;
64;
0099
0090
8891
0091
8Il92
'9893
8892
8820
8884
8808
0001
8802
0!39B
889C
889[\
009E
088C
0036
0086
2017
2018
65 ; 8273 EQUATES
66 ;
67 STAm EOO
68 cOM/'In EQU
69 PARMn EQU
70 RESL73 EOO
71 TXIR73 EQU
72 RXIR73 EQU
73 TEST73 EOO
74 CPBF
EOO
75 TXINT EOO
76 RXINT EQI)
77 TXIRA EQU
78 R'l.iRA EQU
79 ;
80 ; 8253 EQUATES
81 ;
82, MODES: EQU
S3 CNT053 EQlJ
84 CNT153 EQU
85 CNT253 EQU
86 COBP.
~QU
87 MOCNT0 EQU
88 MDCNT2 EQU
89 LKBRl EQIJ
ge LKBi<2 EQlJ
; STATUS REGISTER
; COt1/'lAND REGISTER
; PARAMETER REGISTER
; RESULT REGISTER
; TX rNTERRUPT RESULT REGISTER
; Ril INTERRUPT RESULT REGISTER
; TEST MODE REGISTER
; PARAMmR BUFFER FULL BIT
.' Til INTERRUPT BIT IN STATUS REGISTER
.' RX INTERRUPT aIT IN STATUS REGISTER
,f'-: I NT RESULT MAILABLE BIT
; RX INT RESULT AVAILABLE BIT
90H
90H
91H
91H
92H
93H
92H
2ElH
04H
0SH
81H
02H
,8253 MODE WORD REG! STER
; COUNTER 9 REGISTER
; COUNTER 1 REGISTER
; COUNTER 2 REGI?TER
; CONSOLE BAUD RATE (2400 j
; MODE FOR COUNTER il
; MODE FOR COliNTER 2
.' 8273 BAUD RFlTE LS8 ADR
,827J BfIllC' I<.ATE 1'158 ADR
9BH
9CH
9DH
9EH
e0eCH'
36H
!3B6H
2017H
201BH
91;
92 ; BAUD RATE TABLE.
BAUD RATE
LKBRl
93 ;
94;
*********
9690
*****
*****
2E
09
95 ;
96 .;
97 ;
4800
2400
1200
5C
B9
98 ;
99 ;
100 ,
600
JOO
E5
72
C9
LKBR2
00
00
01
02
05
101,
1e2 ,8257 EflllATE5
103 ;
etlAS
00A!3
0\iAl
OOA2
80ft3
B0AS
8200
8880
0962
4iFF
e06J
il061
81FF
1';;4
11)5
106
107
108
109
WI
111
112
in
114
115
116
MotiS7
CHeADR
CH0Te
CHlADR
CHHC
5TAT57
Rt:BUF
EQU
EQU
EOO
EOi.!
EOU
EOIJ
r:~BljF
EQU
EQU
DRDMA
RXTC
ENNlil
NDMA
TilTC
Eili
EG!lI
EQt!
mu
EOli
\iASH
\iA0H
eAlH
\iA2H
iffGH
BASH
8200H
8000H
62H
41FFH
63H
61H
B1FFH
; 13257 MODE PORT
j CH0 (lW ADR REGISTER
i CH0 TER!'lINAL COUNT REGISTER
; CH1 (TXi ADR REGISTER
. CHi TER!'lINAL COUNT REGISTER
; STfiTUS REGISTER
.; RX BUFFER STFlRT ADDRESS
; Tii BUFFER START ADDRESS
; DiSABLE Rl\ DI'IA CHANNEL TX STILL ON
i TERMINAL COUNT AND MODE FOR RX CHANNEL
.' ENABLE BOTH TX AND Rii CHANNELS-OO. WR.. TX STOP
, DI SABLE TX DMA CHANNEL Ri\ STILL ON
; TERMINAL COUNT AND MODE FOR iX CHANNEL
117 .
7-64
~l1A
APPLICATIONS
9989
9989
!IIl88
IIIl88
IlIlCE
1!Il27
IlIlIl2
1l61F
1l5F8
1l75E
Il5BB
95EB
Il6C7
118 ; 8251A EQUATES
119 ;
121l CNTL51 EQU
89H
121 STAT51 EQU
89H
122 0051 EQU
88H
123 10051 EQU
8SH
124 1'l\E51 EQlI _ IlCEH
125 0051 EQU
27H
126 ROY
EQU
82H
127 ;
128 ; IIlNITOI! SUBROUTINE EQUATES
129 ;
131l GETCH EQU
Il61FH
EQU
131 ECHO
95FSH
132 YALDG EQU
875EH
133 CNYSN EQU
85B8H
134 CRI.F
EQU
Il5EBH
135 NPIOUT EQU
96C7H
; CONTROL IIORI) REGISTER
; STAM REGISTER
; TX DATR REGISTER
; RX DATR REGISTER
; !lODE 16>:, 2 STOP, I«) PARITY
; COMIIfINI), ENABI.E TX&RX
; RXRDY BIT
i GET CHR FROPI KEYBffiRD,
i ECHO CHR TO DISPLAY
ASCI I IN CH
; CHECK IF YALID DIGIT, CARRY SET IF YALID
ASCII TO HEX
; DISPLAY CR, HENCE LF TOO
; WMRT BYTE TO 2 ASCII CHR AND DISPLAY
i CONYERTS
136 ;
137 ; IUSC EQUATES
28C1l
9tlIl3
9988
2eIl0
2821l
Il00D
9tlIlA
2004
20CE
2018
2813
2898
8993
8811
oon
8811
2015
2016
2827
138
139
148
141
142
;
STKSRT EQIJ
CNTLC EQIJ
IOlTOl! EQIJ
C/1DBlIF EQU
143 Cl'IDBFl EQIJ
144 CR
EQIJ
145 LF
EQU
146P.ST75 EQU
147 RST~ EQU
148 LOOM
149 CNADR
158 RESBlf EQU
151 SNRMP EQIJ
EQIJ
152 RR0P
153 NSft!:
EQU
154 RR8F
EQU
155 PRMPT EQIJ
15f POLIN EOO
..157 DEMODE EOO
161 ;
~
162
29C0H
; STACK START
; CNTL-C EQUIVALENT
; I1ONITOR
i START OF COMl'IfINI) BlIFFER
; POLL MODE SPECIAL TX COlttflNl) BlIFFER
; ASCII CR
83H
8IlIl8H
2il90II
20291i
OOH
0AIi
21lD4H
21lCEH
2019H
2813H
2899H
9JH
1lH
nH
l1H
; ASCII LF
; PST7. 5 JUMP ADDRESS
; RST6. 5 JUMP ADDRESS
.: RESlILT BUFFER LOAD POINTER STORAGE
; RESULT BUFFER CONSOLE POINTER STORAGE
i RESlILT BlIFFER START - 255 BYTES
,SNRI'I-P CONTROL CODE
; RR(Il:'-P CONTROL CODE
; NSA-F CONTROL cortE
; RR\9)-F CONTIWL CODE
; PRPlPT STORAGE
•POLL IIODE SELECTION INDICATOR
; DEMO "ODE IND ICATOR
2815H
2816H
2827H
.****************************_*_ _****_*********_*******
163 ;
164 : RAI'I STORAGE DEFINITIONS:
165 :
LOC
DEF
166 ;
167 :
168 ;
16~ ,
179,
171,
172 ;
173 ;
177 j
179 ,
188 j
181
2000-291lF
2018-2911
2813-2814
2015
2816
2817
2818
2819
2820-'2026
2888-28FF
COI1I'IAND BUFFER
RESlILT BUFFER LOAD POINTER
RESlIL T BUFFER CONSOLE POINTER
PROMPT CHARACTER STORAGE
POLL IIODE INDICATOR
BAlJI) RATE lSB FtP. SELF-TEST
BAlID RATE I'I5B FOR SELF-TEST
SPARE
RESPONSE COI'IIIAND BlIFFER FOR POLL MODE
RESlIL T BUFFER
i
7-65
~11A
APPLICATIONS
183
184
185
186
187
188
199
0800
0899
9803
0895
0897
080A
esac
a80F
0811
0814
9817
0819
081B
0810
0SlF
0821
13824
9826
9829
882C
9B2F
31C920
3E36
0398
JA172S
D39C
3A1820
D39C
CDiA8S
CD358B
:lE01
0392
3Eee
D392
:;E20
321520
3E09
321620
322729
21AJOC
CD920C
13832
0835
08:>8
083A
083B
083C
9BlD
083E
0841
0S44
0846
0847
0848
9849
004A
084C
0840
210420
e1000C
360
23
71
21
7O
21CE20
01CEOC
36('3
23
71
23
713
JE1S
38
FB
B84E 219028
0851221:>20
8854 221020
;
: PROGRAM START
,
; INITIALIZE 8~53, 8257, 8251A, AND RESET 8273.
,ALSO SET NOR/'IAL MODE, ANI) PRINT SHlNON MESSAGE
;
ORG
808H
198
sp, STKSRT
191 START: LXI
; INITIALIZE SP
192
MVI
A, !'IOCHT0
,8253 MOOE SET
193
OUT
/'IODE53
,8253 MODE PORT
194
LOA
LKBRl
.: GET S273 BAllO RATE L58
OUT
CNTes]
195
; USING COUNTER 9 AS fJAUI) RATE GEN
196
LOA
LKBR2
; GET 8273 BUfI) RATE M5B
197
OUT
CNTB53
iCOUNTER 0
198
CAlL
RXDMA
; lNITIAl~ZE 8257 RX OMA CHANNEL
199
CAlL
j INITIALIZE 6257 Tl( DMA CHffINEI.
TXDMA
A,8iH
200
MVI
; OUTPUT. 1 FOLLOWED BY A 9
2131
OUT
TESTn
.' TO TEST I10DE REGISTER
MYl
2132
A,08H
; TO RESET THE 8273
203
OUT
TESm
AJ
204
Mill
; NORI1AL MODE f'RmIT CHR
205
SiA
PRMPT
.: PUT IN STORAGE
296
Mill
A,90H
; Tl( POLL RESPONSE IN1) lCATOR
287
STA
POLIN
; 0 MEANS NO SPECIAl TX
STA
DEMODE .
; CLEAR DEI'IO MOOE
208
212
LXI
H.• SIGNON
; SI GNON MESSAGE AOR
21]
CALL
TYMSG
; DISPLAY SIGNON
214,
215 ; I'IONlTOR USES .JUMPS IN RAM TOOlRECT INTERRUPTS
216 :
217
LXI
H..R5T75
; RST7. :5 JUMP LOCATION USED BY MONITOR
218
LAI
B,RXI
; IllDRESS OF RX INT ROUTINE
MVI
; LOAD 'JMP I OPCooE
219
M.. !lC3H
INX
229
H
; INC POINTER
M,C
221
/'10\1
; LOAD RXI L58
222
INX
H
; INC POINTER
223
MOV
I'I. B
; LOAD RXI "58
224
LXI
H. R5T65
; RST6. 5 JUI'IP LOCATION USED BY MONITOR
B, TXl
225
LXI
; ADDRESS OF TX INT ROUTINE
226
HVI
M,0GH
; LOAD 'JMP" OPCODE
227
INX
H
; INC PO INTER
M,e
228
f'IOV
; LOAD r":I L58
229
INX
H
; INC POINTER
/'I,B
238
/'101/
; LOAD TXI I1SB
A,1SH
231
MvI
; GET SET TO RESET INTERRUPTS
SIt;
232
; RESET INTERRUPTS
2J3
EI
; ENABLE INTERRUPTS
2:>4,
235 I INITIAlIZE BUFFER POINTER
236 .
2j7 i
L"·
; SET RESULT BUFFER POINTERS
218
H.. RESBUF
239
; RESULT CONSOLE POINTER
CNADR
240
SHLD
LOADR
; RESULT LOAD POINTER
241,
242 ; MAIN PROGRAI'l LOOP - CHECKS FOR CHANGE IN RESULT POiNTERS, USART STATUS,
243;
OR POLL STATUS
J_J
SiD
7-66
AfN,()0811A
APPLICATIONS
9857 CDEB85
885A 3A1520
985D 4F
985E CDFS85
08612A1329
08647D
11865 2111829
8868 8l'l
0869
886C
986E
0878
8873
C2190A
DB89
E682
C27D08
3A1629
es7~ A7
8877 C24C1l9
0B7A C36110
244 ,
245 CI'I>REC:
246
247
248
249 LOOP IT :
259
251
252
253
259
2b0
261
262
263
264
265
CALL
CRLF
LOA
I!OY
mIPT
CALL
LHLD
C,A
ECHO
CNfI)R
HOY
A.L
LHL.D
ClIP
JNZ
IN
ANI
JNZ
LDA
ANA
JHZ
JI1P
LDADR
L
DISPY
STATS1
lID','
GETOO
POLIN
A
TXPOL
LOOPIT
,DISPLAY CR
,GET CURRENT PRCIIPT CHI!
; MOVE TO C
,: DISPLfIY IT
; GET CONSOLE POINTER
,5AYE POINTER LSB
,lET LOll) POINTER
;SfIIE L58?
,NO, RESlLTS NEED DISPLAYING
,YES. c/£CK KEYBOARD
; CHR RECEIVED?
; I1UST BE CHR SO GO GET IT
: GET POLL I100E STATUS
;IS IT Il? '
i NO, nEN POLL OCCURRED
i YES, TRY AGAIN
266
267
i
i
268 ,COItfIN[l RECOGNIZER ROUTINE
107D CD1F86
88S9 CDF8Il5
1l88! 79
0084 FE52
8886 CAAFOO
8889 FE53
ease CAD7Il8
08SE FE.!7
1l891l CAms
0893 FE54
Il895 CAIlE0!I
Il89S
889A
889D
1l89F
!!8A2
FE41
CA2289
FE5A
CA1109
FE03
Il8f!4 CAIlSOO
1ilS1I7 !!ElF
1l8A9 roF8Il5
BSAC C357IlS
269,
278 :
271 GETOO, CALL
CALL
272
2t3
HOIf
cpr
274
275
JZ
276
CPI
277
JZ
278
CPI
]Z
279
CPI
280
281
JZ
CPI
2S2
28Z
JZ
CPI
284
285
12
CPI
299
291
' 292 ILLEG MYI
293
CALL
294
JMP
rz
GETCH
ECHO
A.C
,'R'
RDWN
'5"
SDIIN
'G"
GD/oIN
'T'
TDWN
'A'
FW4
'z'
Ct100E
CNTLC
MONTOR
C, ",,,
ECHO
CI1DP.EC
,GET CHR
;ECHO IT
,SETUP FOR C!I1PARE
iR?
i GET
i S1
!'lORE
,GET !'lORE
iG?
; GET !'lORE
; T?
,lET I'IORE
iA?
i GET
11OF.E
iZ?
; YES, GO CHANGE MODE
,; CNTL-l"
,EXIT TO MONITOR
,: PRINT ?
;DISPLAY IT
,LooP FOR CMlAND
295
!!8fIF
Il882
!!SB5
1l8B6
8B88
Il8B8
esero
CD1FB6
CDF8Il5
79
FE4F
CA5D09
FE'):::
CA6799
FE44
CA71B!1
FE'50
CADSIl3
FES"
CflOO08
esc!!
08(2
Bses
08C7
il13CA
98CC
98CF FE4~
88rt1 CA7809
2% RDWN,
297
298.
299
::;ee
J81
3!!2
393'
394
CALL
IETCH
CALL
ECHO
I!OY
A,C
CPI
JZ
CPI
JZ
CPI
'0'
ROC/Il)
'5'
RSC1'ID
'D'
J2
RDCII)
385
CPI
J96
J2
'P'
P.POO
'R'
STAPT
307
388
309
310
cpr
],
CPI
JZ
's,'
RBC11D
7-67
i lET NEXT CIf1
,ECHO IT
,SETUP FOR CilMPARE
,O?
i RO COI1I1ANI)
is?
iRS COMMAND
iD?
; lID COMI'IAND
,P? .
: RP COIV1AND
,R?
,5TART OYER
:S?
; RB COIt1ANV
AfN.GllA
APPLlCATJONS
0804 'C3A798
0807 CDIF06
080A CDF80S
98OC- 78
08DE FE4F
9BE0 CAA609
98E3 FE53
08ES CAB089
0BE8 FE52
0BEA CABAe9
0BEDFE'50
98EF CAE209
98F2 FE42
tlBF4 CA8509
0BF7 FE4(
98F9 CASFB9
98FC C3A798
tlBFF
0902
9905
0906
090S
090B
WIF06
CDF895
78
FE52
(.RC499
CA70S'
09BE
0911
0'?14
0915
B917
09111
09iC
091F
CDIFB6
C[)FS05
78
FE46
CAEce'?
FE4C
CA9909
GAieS
0922
0925
13928
0929
09213
092E
C[liF06
CDF8es
78
FE46
CACEf.l9
CiA70e
;39~1
F1
3A1520
FE2['
C243e9
3E2B
121520
FB
CS70e
3E2D
32152i1
FB
C35708
0912
0935
0937
893ft
093C
B9~F
0940
0941
@945
.\l948
13949
311
312
313 SDWN:
314
31S
316
317
318
319
320
ILLEGfL TRY AGAIN
JMP
ILLEG
i
CALL
CALL
I'IOV
CPI
GETCH
ECHO
i GET
JZ
50(./11)
NEXT CHR
ECHO IT,
; SETUP FOR COI'IPARE
;O?
,; SO COItIfIN[)
CPI
'5'
;S?
J2
SSOO
'R'
5RC./1I)
A~B
'0'
i
321
JZ
322
323
324
325
326
'327
328
129
]30 GOWN.
1;;1
CPI
'P'
J2
SPCMD
'B'
SBCMD
'L'
SLCM{J
ILLEG
i S5 COI'IIIANI)
iR?
; 5R COItIfIN[)
;P?
;SPCOHI1AND
;B?
;5BCOIt1AND
;L?
;5L COMMAND
; ILtEGAL TRY AGAIN
GETCH
ECHO
A,B
'R'
ORCMI)
ILLEG
; GET NEXT CHR
;ECHO IT
.; SETUP FOR COMPARE
; R?
;OR COMMAND
; ILLEGAL.. TRY AGAIN
. GETCH
ECHO
A,B
.; GET NEXT' CHR
; ECHO IT
; SETUP FOR COMPARE
1>2
Z33
334
CPI
CPI
JZ
CPI
JZ
JIiP
CALL
CALL
MOV
CPI
JZ
335
JMP
336
337 TDWN.
338
CALL
CALL
~39
~10V
340
CPI
J2
C.PI
JZ
341
34~
34:;
344
345
:;46 Af COfIIffIN) INTO BlfFER
i POINT AT ADR AN> CNTL. POSITIONS
; FINISH OFF COIIlIAND IN TF RWTlt£
i
i
446 i so - SET OPERATING IIlDE mIIM)
-447 ;
B,81H
448 SOCI1O: !WI
i' OF PfRAI'IETERS
i COIII'fAN)
C,91H
449
/'IVI
; GET ~ fH) -ISSUE COItfAN)
458
CALL
COlI'!
i GET NEXT COIIfH)
451
JIIP
CItDREC
452 i
453 i SS - SET SERIAL 110 COPttIANI)
454 i
;. oF PARAI1ETERS
a,81H
455 SSCIID: l'1li1
; COI'IIIfINI)
111/1
C,8A8H
456
; GET PfI1AI'IETER AN> ISSUE COItIfIN)
457
CALL
COI1I1
,.GET NEXT COI1IIAN)
458
JI1P
CllDREC
459 ;
~ ,SR - SElECTIVE RECEIVE COII'IfH)
461 ;
;. OF PfIRAIETERS
a,84H
462 SRCI1D: l'1li1
;COI'IIIfINI)
C,8C1H
46l
MIll
464
COI!I1
,GET PARfII'IE~5 fIN) ISSUE COltIH)
; GET NEXT COItfAN)
465
JI1P
CI1DREC
466 ;
467 ; GR - GENERAL RECEIVE COI1HAI{l
au
468
469
478
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
. 486
487
488
489
499
491
492
493
494
495
496
;
GRCI1O: 11111
"'.'1
CALL
JI1P
a,8211
C,9C8H
COlt!
Ct1DREC
; t() PARAI1ETERS
;COPIIIfH)
, ; ISSUE COHIIfH)
; GET NEXT COIt1AND
i
; AF - ABORT FRAME COt1/1AND
;
a, II8H
AFOO: 11111
C,8CCH
I'IYI
-CALL
CO"'"
CHDREC
JI1P
j
NO PARAMETERS
;CtM1I)
; ISSUE COIII'IfN) .
; GET NEXT COItfINI)
i
,RP - RESET PORT CMIfINI)
:
11PC11O- I'll/I
a,81H
C,63/i
11111
COlt!
CALL
JI1P
CI1DREC
;
,5P - SET PORT cotII'IANI)
,
5PC/1I)- 11111
a,81H
1'1111
C,9AlH
.CALL
COi'Ii'I
JIIP
Ct1DREC I
;
, TF - TRANSI1IT FRAIIE COItIAN)
,
7-70.
" .OF PARAI'ETERS
; CortlAND
; GET PARAI1ETER AND ISSUE COItftNI)
; GET NEXT COI1I1AND
; I OF PARAI1rnRS
; COI1I'IAND
; GET PARAI'IETER AND ISSUE COItIANI)
;GET HEX COI1i'IfIND
AfN.Ooel1A
APPLICATIONS
89fC 210020
09EF 0682
89Fl 36C8
99F3 218220
99F6 78
0!lF7 A7
99F8CAtJ7eA
99FB CDAD0A
89FE DAA798
0A91 2l
9A02 95
0A93 77
0A94 ClF699
8A!l7 219088
9A!lA !l10909
9A!lD C5
!lA!lE CDAD0A
eA11 DA1B0A
0A14 77
!!A1S 23
eA16 C1
eA1? 1.33
8A18 C3000A
!!AlB FE0D
eA1D CA240A
!!A2!l Cl
0A21 GA7es
!lA24 C1
0A25 210120
0A2871
0A29 2Z
tlA2A 70
'3A2B 0604
!lA2D 2E60A
9A30 ('5
811:1 E3
!lA32 C5
!lAn ClFB0A
!lA36 C35798 .
497 TFCIID: LXI
498
I'IVI
499
I'IYI
500
LXI
581 TFCI'ID1: PlOY
582
ANA
59l
JZ
594
CALL
505
JC
506
INX
597
OCR
598
MOV
.JI'IP
599
518
511 TBUFL: LXI
'512
LXI
513 TBUFL1: PUSH
514
CALL
515
JC
MOil
516
51;'
INX
518
POP
519
INX
S29
JMP
521 ENOCH!<.: CPI
522
JZ
523
POP
524
Ji'IP
5.<"5 TBliFFL. POP
526
m
527
MOI/
528
!Nil
529
1'101/
530
MIiI
531
L:A2
78
D3A2
01FF81
79
FsA3
78
v5il::;
3m
D?.AS
C9
712 TXDMA:
713
?14
715
A, DTftl1A
MODES?
B, TXBUF
716
CHiADR
A,B
CH1ADR
B, mc
A,C
CH1lc
A. B
CHiTC
A, ENDMA
MODES?
717
718
719
720
721
722
723
724
725
Mill
OUT
LXI
MOIJ
OUT
' MOIJ
OUT
TXDHA1: LXI
MOIl
OUT
726
727 •
728 ;
MOY
OUT
MYI
OUT
RET
A)C
7-74
; DISABLE TX DMA CHANNEL
; 8257 tomE PORT
; TX BUFFER START ADDRESS
, TX BUFFER LSB
; CH1 ADR PORT
i TX BUFFER HSB
i CH1 ADR PORT
; TX CH TERMINAL COUNT
.; TX TERMINAL COUNT LSB
; CHi TC PORT
; TX TERMINAL COUNT MSB
; CHi TC PORT
; ENABLE DMA WORD
; 8257 MODE PORT
.,RETLIRN
AFN.(J0811A
. APPLICATIONS
ecee
729 ; II£RRtPT PROCESSING SECTION
739 i
731
IICII9II
~
732
i
mi
BCIl8 E5
9C91 F5
9C82 C5
9C8305
9C84 3E62
IIC86 D3A8
8C88 3E18
IIC8R 38
9C8B 1604
9C8D 2A1028
BC10 E5
8C11 E5
9C12 4'5
BCD 2R1328
8C1684
8Cl; 78
9C1S BD
9C19 CRE40R
8C1C 15
8C1D C2168C
8C28 1685
tq2a
8C23 DB90
8C25 E60B
8C27Cf1398C
BC2A DB98
8C2C E602
8C2E CA238C
8C3l D893
8C3J 77
0C34 2C
8C3'5 15
0C36 C3238C
8Cl9 7ft
8C3A A7
8C3B CA458C
OC3E 3680
0':'40 2C
8C4115
9C42 C3398C
8C45221828
0C48 3A1528.
8C48 FE2D
9C4D CAB58C
0C50 E1 •
8C51 7E
734 i RECEfYER INTERRIPT - RST 7. 5 (LOC lCH)
735 i
736 RXI:
H
iSAVE HL
PUSH
737
PUSH
PSW
i,SAVE PSW
73S
PUSH
B
iSAYE BC
739
D
PUSH
iSAYE DE
A, DRDIII
748
PlYI
i DISABLE RX DI1A
741
OUT
IIlDE57
i 8257 /'KIDE PORT
R,18H
742
PlYI
i RESET R5T7. 5 FIF
743
SIll
D,84H
744
i D IS RESULT COUNTER
PlYI
745
LHLD
LDRDR
i GET LORD POINTER
746
iSAYE IT
PUSH H
747
PUSH
H
; SAVE IT RGfIIN
748
iSRYE LSB
!lOY ' B,L
749
; GET CONSOLE POINTER
LHLD
CIf!DR
i BIIIP LeA) POINTER LSB
758 RXI1: INR
B
A,B
751
PlOY
.' GET SET TO TE$T
; LORD=CONSOLE?
752
C/'F
L
i YES, BUFFER FULL
JZ
' 753
BUFF\I..
754
D
i DEC CtUlTER
OCR
i NOT DONE, TRY AGAIN
755
JNZ
RXI1
756
PlYI
D.85H
i RESET COUNTER
; RESTORE LeA) POINTER
757
POP
H
i READ STATUS .
75B RliI2: IN
STAm
759
; TEST RX INT BIT
ANI
RXINT
i DONE, 00 FINISH tP
768
JZ
RXB
761
IN
STAm
i READ STATUS AGAIN
762
ANI . RXIRA
i IS RESULT READY?
. RXI2
76J
i NO, TEST RGfIIN
JZ
,YES, READ RESULT
764
IN
RXIR73
M,A
765
IIOY
; STORE IN BUFFER
766
INR
L
; INC BUFFER POINTER
767
OCR
D
; DEC COUNTER
768
.JI'P
RXI2
i GET mlRE RESULTS
A,D
769 RXB: I10V
i GET SET TO TEST
; ALL RESULTS?
i7!l
ANA
A
771
RXI4
; YES, SO FINISH UP
JZ
IU8H
; NO, LOfI) 8 UL DONE
772
PlYI
; BUI'IP POINTER
m
INR
L
774
OCR
D
i DEC COUNTER
775
JMP
RXIJ
iGO fGlIN
776 RXI4: SHLD. LDADR
; UP,I)ATE LOAD POINTER
; GET I10DE III) ICATOR
m
LDA
PRI'IPT
77B
CPI
i NORIIAl !'lODE?
'-'
; YES, CLEAN UP BEFORE RETURN f
m
RXI6
JZ
788 ;
781 i
POLL I'1OOE SO CHECK CONTROL BYTE
782 ;
IF coNTRoL IS A POLL, SET UP SPECIIL TX COI'1IIfN) BUFFER
78~ i
AND RETURN WITH POLL III)ICATOR NOT 8
e
784 ;
H
; GET PREVIOUS LOAD ADR POINTER
785
POP
A,II
,GET IC BYTE FRO/'! BtfFER
786
IIOY
7-75
. AfN.OD811A
APPLICATIONS
9CS2 E61E
0C54 C2898C
9CS7 2C
OC58 2C
OC592C
0C5A 56
0C5B 2C
OCSC 7E
OC5[) FE93
OCSF CA6C9C
OC62 FEll
OC64 C2890C
OC67 1E11
OC69 Cl6EOC
0C6C 1E73
OC6E 212029
OC71 36GB
OC73 23
OC743600
OC76 23
8en l600
OC79 23
OC7A 72
OC7B 23
OC7C 73
OC71) JE81
OC7F 321620
OC82 C3890C
OC85 E1
OCB6 CJ890C
OC.B9
OC.BC
OC80
OC8E
OC8F
. OC98
OC91
OC92
OC93
OC94
OC95
OC97
0C9A
OC9B
OC9E
OCA1
OCA2
CD1Ae8
D-l
C1
F1
E1
FE
C9
C5 .
7E
23
FEFF
CAA10C
4F
CDFB05 .
C3930C
C1
C9
787
788
789
798
791
792
ANI
JNZ
INR
INR
INR
79J
INR
I'IO't'
794
t10Y
795
CPI
JZ .
CPI
JHZ
ItYI
JItP
796
797
798
799
BOO
881 n:
1'1\11
802 TXRET: LXI
HVI
i306
808
INX
HilI
809
819
INX
811
ItYl
812
INX
813 .
HOY
814
INX
815
MOil
816
MVI
B17
STA
818
JItP
819
828 RXI6: POP
821
JItP
822
823.RXI5: • CALL
824
POP
825
POP
826
POP
827
POP
828
EI
RET
829
830 •
831 ;
832. MESSAGE TYPER
833 ;
834 ;
835 TYI'ISG: PUSH
836 TYI'ISG2: HOV
837
INX
83B
CPI
839
J2
1'1011
B40
841
CALL
JItP
842
843 TYMSG1: POP
844
RET
845
lEH
i LOOK ATGOOO. FRflI1E BITS
i IF NOT 8, INTERRUPT WASN'T
i B\'PASS. R8 AND R1 IN BUFFER
RXI5
L
L
L
[),II
L
A,II
i GET
FROI'I A GOOD FRflI1E
ADR BYTE AND SAVE IT IN [)
i GET
CNTL BYTE FROI'I BUFFER
WAS IT SNRIt-P?
i YES, GO SET RESPONSE
; WAS n· RR(8l-P?
i YES, GO SET RESPONSE, OTHERWISE RETURN
; RRHI)-P SO SET RESPONSE TO RR(8)-F
; GO FINISH LOADING SPECIAL BUFFER
.' SNRIt-P SO SET RESPONSE TO NSA-F
; SPECIAL BUFFER ADR
; LOAD TX FRAItE COllMAN[)
; INC POINTER
iL9=9
; INC POTHTER
;L1=8
; INC POINTER
. ; LOAD RCIJD ADR BYTE
; INC POINTER
; LOAD RESPONSE CNTL BYTE
; SET POLL INDICATOR NOT 0
; LOAD POLL INDICATOR
!RETlIRN
SNR~1P
j
n
RReF'
RXI5
E..RR8F
TXRET
E,NSAF
H,Clt[)8F1
• It !lCSH
H
H,89H
H
H,89H
H
I'I,[)
H
I'LE
A,81H
POPN
RXI5
H
RXI5
; CLEAN UP STACK IF NORMAL MODE
!RffilRN
RXDMA
•RESET DMA CHANNEL
.' RESTORE REGISTERS
0
B
PSW
H
•ENABLE I NTERRlIPTS
•RETURN
- ASSUMES HESSAGE STARTS AT HL
[;
;SflVE Be
; GET fISC II CfIR
; INC POINTER
; STOP?
; YES, GET SET FOR EXIT
; SET UP FOR [) ISPLAY
; DISPLAY CHR
j GET NEXT CfIR
,RESTORE BC
.• RETUP.N
A, M
H
BFFH
T'r'I'ISG1
C,A
ECHO
WI'ISG2
B
j
B46 ;
847. ,SIGNON I'IESSAGE
848 ;
7-76
AFN.Q0611A
APPLICATIONS
9CR]
IlCA4
9CA8
9CAC
9CB0
9C84
9CB6
0CB7
9CB8
9CB9
9C13I)
9CC1
0ce2
90
J8323733
294D4F4E
49544FS2
202Il56J1
2E31
90
FF
91)
525821149
4E54292D
20
FF
849 SIGIOI: .DB
Yi 1', CIt IlFFH
CR, '8273 I'IONITOR
858 .:
851.:
852 .:
853 .: RECEIVER INTERRUPT PlESSflGES
854 .:
855 ;
856 RXII'ISG: DB
CR, 'RX INT - ',0FFH
857 ;
OCC391)
OCC4 54582049
OCC8 4E54202D
0Cce 20
0CC~ FF
858 .' TRANSIIITTER INTERRUPT PlESSAGES
859.:
CR., 'TX INT - ',0FFH
860 TX1115G: OB
861;
S62 .:
9CCE E5
0CCF F5
0C00 C5·
0CD1 05
9C023E61
0CD4 D3A8
9CD61604
0COS 2A1020
0CDB E5
0COC 45
9COO 2A1320
0CEfJ 04
0CE1 78
OCE2131)
0CE3 CRE4l!A
0CE6 15
0CE7 C2E00C
0CEA E1
9CEB DB92
0CED 77
0CEE 2C
0CEF 3600
0CF1 2C
OCF23600
9CF4 2C
9CF5 3600
9CF7 2C
863 ; TRAN5I'lITTER INTERRUPT ROUTINE
864 ;
S65 TXI:
PUSH
H
PSW •
866
PUSH
867
PUSH
B
86S
0
PUSH
A,OTDl1A
869
MYI
870
OliT
i'lIDE57
0,04H
871
MYI
872
lHlD . LDADR
PliSH
873
H
!'lOy
874
B,l
875
lHlD
CNAOR
876 TXI1:
B
IN!!
A,B
877
!'lOY
878
CMP
L
879
JZ
BUFFUl
880
OCR
D
TX11
8S1
JNZ
H
8S2
POP
883
IN
TXIR73
I'I,A
8S4
11011
885
IN!!
L
S86
887
8BS
889
890
891
I1YI
INR
M,00t!
; SfIYE Hl
.:SAYE P5W
iSAYE Be
; SAVE .DE
; DISABLE TX DI1A
; 8257 I'IOOE PORT
.: SET COUNTER
; GET lOAD POINTER
i
SAVE IT
SfIYE LSB IN B
: GET CONSOLE POINTER
; INC POINTER
; GET SET TO TEST
: lOfll)=CONSOLE?
; YES, BUFFER FULL
i NO, TEST NEXT LOCATION
; TRY AGAIN
; RESTORE LOAD POINT~
i REAl) RE.."l1LT .
; STORE IN BUFFER
; IN!! POINTER
; EXTRA RESUlT SPOTS 0
i
l
MY!
M,OOt!
IN!!
tiVI
l
IN!!
L
M,OOH
7-n
AfN.OO611A
APPLICATIO"S
IlCF8
IICFA
9CFB
IlCFE
3688
2C
221029
CD35IIB
8DII1 D1
892
893
894
""'I
IN!
899
CFU
POP
POP
POP
POP
EI
RET
SHLI)
9811
9111
982
9IIJ
984
905
9Il6 ;
9117;
952 ;
95J ;
Il002 C1
, 0DIIJF1
11D114E1 0DII5 FB
9DII6 C9
II.IIIIH
L
I.DADR
TXDI1A
0
B
PSII
H
i tFofITE LOAD POINTER
i RESET' DI'III CHfINIEI..
;RESTORE DE
iRESTORE Be
i RESTORE PSW
iRESTDR£ HL
i EtRIl.E INTERRUPTS
; !£TURN
END
954
PUBLIC SYI'IBOlS
ElITERNAL 5VItlOI.S
USER S'r'I'IBOlS
A 8922
CII>51 A 8927
CNT853 A !III9C
COl!! . A 8AE5
DEI1
A 9I11III
ECHO A 85F8
ILLEG A 88ft7
~2 A IIIIB6
PARi A IIBII8
POLIN A 21116
IIDY
A I11III2
RSC/1D A 0967
RXI1 A 1IC16
RXINT A 0098
RXTC A41FF
SPCI'JI) A 99E2
STKSRT A 29C1I
TEST7J A 91192
TXBUF A 89l1li
TXINT A I11III4
T\'I1SG A 1IC92
Af)WN
AFOO
Cl'lDBF1
00153
COI'II11
DEIIOOE
ENDCHK
LOADR
!tOES1
PAR2
PRltPT
RESBUF
RST65
RXI2
RXIR7J
SBCI'fI)
SRCI'ID
SW
TFCI'I):
0051
TXIR7J
TYIISG1
ASSEIIBLY COMPLETE,
"
\t ""
A 99C£
BUFFLl A 1lfE4
A 2l12li
00Blf' A 2l1li8
A II1I9I)
CNT25J A IIII9E
A lIfER
C!III12 A 9AFF
8 21127 .OISPY A 8AJ9
A WB
ENDIIA A ~
iI 211111 LF
A II0IIA
A IIIICE' I'IOOE5J A IIII9B
PARIN A IIAAf)
A eBeD
A 21115
RePT A 9AA2
A 28l1li
RESl.7J A l1li91
A 20CE
RST75 A 2IID4
A 1IC23
RXB A 1IC39
A l1li93
RXIRA A I11III2
A 11985
SOWN A 118D7
A II9BA ' SSCI'1D A liB
A 11943
T1
A IIC6C
A I19EC
TFCllD1 'A 119F6
A 11988
TXDIIA A 9835
A l1li92 . TXIRA A I11III1
A 9CA1, TYItSG2 A 9C93
'CHIIfI)R
CIIOOUT
.CNTL51
Cl»II7J
OISPY1
GOWN
,LKBR1
1IODE57
PAR1N1
RiPT
A Il8A8
A IIAFB
A IlII89
A Il99II
A 9A4E
A 88FF
A21117
A 89A8
A HII
A lIRA?
A II95D
RXBUF ,A 82l1li
ROCfI)
RXI4
RXS1
SIGMON
STflRT
TBlfFL
TFRET
TXDI'IA1
TXPOL
YAI.OO
A 1IC45
A IIA69
A IICAJ
A 118l1li
A 9A24
A 9A36
A 9842
A II94C
A 975E
CHeTC
OOREC
CNTLC
CPBF
OISPY2
GETCH
LKBR2
I'KlNTOR
PARIN2
RBOO
A IIIIA1
A 0857
A II89J
A 8929
A IIA40
A 861F
A 21118
A,eaes
A 9ff)C
A 11978
RPCPID A II9D8
RXD51
RXIS
RXS2
51.00
STATS1
TBUFL
TLCIID
TXI
TXRET
A 0Il88
A 1IC89
A 1Ifl7F
A II98F
A IlII89
A 1lA97
A em
A IICCE
A IIC6E
CH1fI>R A 99fI2
CHiTC
CIIOOE A 89J1
ctR>R
CNYBN A' II5BB , COBR
CR
A IIIlIID
CRL.F
DRDIfA A l1li62
OmtA
GRell)
GETCIID A 1l87D
LOOPIT A 8861
II>CHTII
ItWT A 116C7 N5AF
PARI'I7J
PARINJ A IlABC
RJ)Cft) A11971
RDIoIi
RRIIF A IlII11
RRIIP
RXDI1A A Il81A
RXI
RXI6 A IIC85
RXIIISG
RXS3 A 8A8D
RXSORC
50()1)
5IRIP A l1li93
STArn
STAT57 A IIIIA8
TBlFl1 A 9AIID
TDIIl
TRlE A IIIIIIII
TRl£1
TXI1 A 8cEII
TXIIISG
TXSa!C A9fl47
mc
A IIIIfIJ
A 2II1J
A IlIlIIC
A II5EB
A l1li61
A 09C4
A IIIIJ6
A 11117J
A l1li91
A II8AF
A l1li11
A IICIIII
A IICBB
AIIA62
A 99f16
A Il99II
A 99IIE
A IIIIIIII
A IICCJ
A 81FF
NO ERRORS
7-78
AfN.OO811A
intJ
APPLICATION
NOTE
AP-134
October 1981 '
© INTEL CORPORATION. 1981
7-79
Order number: 210311-001
AP-134
:; ~
INTRODUCTION
4. WAIT Mode. The MPSC'ready signal is used to
synchronize processor data transfers by forcing the
processor to enter wait states until the 8274 is ready
for another data byte. This feature enables the 8274
to interface directly to an 8086 or 8088 processor by
means of string 1/0 instructions for very high-speed
data links.
The 8274 Multiprotocol 'serial ~ontroller (MPSC) is a
sophisticated dual-channel communications controller
that interfaces microprOcessor systems to high-speed
serial data links (at speeds to 880K bits per second)
using synchronous or asynchronous protocols. The
8274 interfaces easily to most common microprocessors (e.g., 8048, 8051, 8085, 8086, and 8088), to DMA
controllers such as the 8237 and 8257, and to the 8089
110 processor. Both MPSC communication channels
are completely independent and can operate in a fullduplex communication mode (simultaneous data transmission and reception).
Scope
This application note describes the use of the 8274 in
asynchronous communication modes. Asynchronous
communication is typically used to transfer data
to/from video display terminals, modems, printers, and
other low-to-medium-speed peripheral devices. Use of
the 8274 in both interrupt-driven and polled system
environments is described. Use of the DMA and WAIT
modes ,are not described since these modes are
employed mainly in synchronous communication systems where extremely high data rates are common.
Programming examples are written in PL/M-86
(Appendix B and Appendix C). PL/M-86 is executed by
the iAPX-86 and iAPX-88 processor families. In addition, PL/M-86 is very similar to PL/M-80 (executed by
the MCS-80 and MCS-85 processor families). In addition, Appendix D describes a simple application example using an SDK-86 in an iAPX-86/88 environment.
Communication Funct!ons
The 8274 performs
functions, including:
many" communications-oriented
'
-Converting data bytes from "Illllicroprocessor system
into a serial bit stream for tratismission over the data
link to a receiving system.
.
-Receiving serial bit streams and ,reconverting the
data into parallel data bytes that can easily be processed by the microprocessor system.
-Performing error checking during data trati~ers. Error checking functions include computingl
transmitting error codes (such as.parj.ty:bitl! or CRC
bytes) and using these code~ to check thj:,v~dity
received data.
. ,'.'
~, ,
SERIAL-ASYNCHRONOUS DATA LINKS
of .,
-Operating independently of the system processo("ina
manner designed to reduce the system overhead in- ,
volved in data transfers.
"
System Interface
The MPSC system interface is extrem:ely flexible,
supporting the following data transfer ~odes:
"
1. Polled Mode. The system processor periodically
reads (polls) an 8274' status register to determine
when a character has been received, when a chw- '
ter is needed for transmission, and when transmission errors are detected.
A serial asynchronous interface is a method of data
transmission in which the receiving and transmitting
I/ystems need not be synchronized. Instead of transmitting clocking information with the data, locally
generated clocks (16, 32 or 64 times as fast as the data
transmissioq rate) are used by the transmitting and
receiving systems. When a character of information is
sent by the transmitting system, the character data is
framed (preceded, and followed) by special START and
STOP. bits. This framing information permits the receiving system' to temporaruy synchronize with the data
tI'l\nsmission. (Refer to Figure 1 during the following
d~~c'.lssion of asynchronous ~ata transmission.)
TIME--+-
I
2. Interrupt Mode. The MPSC interrupts the system
, processor when a character has been received, wh,,;}
a character is needed for transmission, and when
transmission errors.are detected.
.
I
I
I
I
--1_
I
0
I
1~
I
1
I
0
I
0
DA:A~:I~~~lE '>~~T ~
3. DMA Mode. The MPSC automatically requests data
transfers from system memory for both transmit and
receive functions by means. of two DMA request
signals per serial channel. These DMA request signals may,be directly interfaced to an 8237 or 8257
DMA controller or to an 8089 1/0 processor.
"
1
I
0
,I,
1
I
0
•
I
I
I
I
1--,-
iPARITYS:PDA:A~:I~::LE
PARITY
o
CHARACTER (UPPER CASE &53H)
1 0 1
0 0 1 t
Figure 1. Transmission'of a 7·BltASCIl Character
with Even Parity
7-80
Ap·134
Normally the data link is in an idle or marking state,
continuously transmitting a "mark" (binary 1). When a
character is to be sent, the character data bits are immediately preceded by a "space" (binary 0 START bit).
The mark-to-space transition informs,.the receiving system that a character of information will immediately
follow the start bit. Figure I illustrates the transmission
of a 7-bit ASCII character (upper case S) with even
parity. Note that the character is transmitted immediately following the start bit. Data bits within the character are transmitted from least-significant to
most-significant. The parity bit is transmitted immediately following the character data bits and the STOP
framing bit (binary 1) signifies the end of the character.
Asynchronous interfaces are often use'd with human
interface devices such as CRT/keyboard units where
the time between data transmissions is extremely
variable.
Framing
Character framing is accomplished by the START and
STOP bits described previously. When the START bit
transition (mark-to-space) is detected, the -receiving
system assumes that a character of data will follow. In
order to test this assumption (and isolate noise pulses
on the data link), the receiving system waits one-half bit
time and samples the data link again. If the link has
returned to the marking state, noise is assumed, and the
receiver waits for another START bit transition.
When a valid START bit is detected, the receiver
samples the data link for each bit of the following character. Character data bits and the parity bit (if required)
are sampled at their nominal centers until all required
characters are received. Immediately following the
data bits, the receiver samples the data link for the
STOP bit, indicating the end of the character. Most
systems permit specification of 1, 1h, or 2 stop bits.
Characters
Timing
In asynchronous mode, characters may vary in length
from five to eight bits. The character length depends on
the coding method used. For example, five-bit characters are used when transmitting Baudot Code, seven-bit
characters are required for ASCII data, ,and eight-bit
characters are needed for EBCDIC and binary data, To
transmit messages composed of multiple characters,
each c~aracter is framed and transmitted separately
(Figure 2).
The transmitter and receiver in an asynchronous data
link arrangement are clocked independently. Normally,
each clock is generated locally and the clocks are not
synchronized. In fact, each clock'may be a slightly
different frequency. (In practice, the frequency difference should not exceed a few percent. If the transmitter
and receiver clock rates vary substantially, errors will
occur because data bits may be incorrectly identified as
START or STOP framing bits.) These clocks are designed to operate at 16, 32, or 64. times the com~unica
tions data rate. These clock speeds allow the receiving .
device to correctly sample the incoming bit stream.
This framing method ensures that the receiving system
can easily synchronize with the start and stop bits of
each character, preventing receiver synchronization errors. In addition, this synchronization method 'makes
both transmitting and receiving systems insensitive to
possible time delays between character transmissions.
VARIABLE DELAY BETWEEN
CHARACTERS
;
; ;
:;
c
t;
~!::
;om
e~
'"
~
.,
.
CHARACTER
~
0'"
Iii~
.~.
~,. §
1------1
'"
Ii Ii
I
I
CHARACTER CHARACTER
•3
.,
Ii
CHARACTER
••
;
Ii
:;
~
~
.----.
CHARACTER
OS
Figure 2. Multiple Character Transmission
Serial-interface data rates are measured in bitsi second.
The term "baud" is used to specify the' number oftimes
per second that the transmitted signalleye! can change
states. In general, the baud is not equal to the bit rate.
Orily when the transmi,tted signal has two states
(electrical levels) is the baud rate equal to the bit rate.
Most point-to-pointserial data links use RS-232:C, RS422, or RS-423 electrical interfaces. These specifications call for two electrical signal levels (the baud is
equal to the bit rate). Modem interfaces, however, may
often have differing bit and baud r:ates. .'
While there are generally no limitations on the data
transmission rates used in an asynchronous data link, a
limited set of rates .has been standardized to promote
equipment interconnection ..These rates vary from 75,
bits per second to 38,400 bits per second. Table 1 illustrates typical asynchronous data rates and the asso'dated clock frequencies required for the transmitter
and receiver circuits.
AFN-<)2076B
Table 1. Communication Data Rates and .
Associated Transmitter/Receiver .
CloCk Rate.
75
150
300
600
1200
2400
4800
9600
19200
38400
MPSC SYSTEM INTERFACE
Clock Rate (kHz)
Data Rate (liits/second)
X16
X32
X64
1.2
2.4
4.8
9.6
19.2
38.4
76.8
153.6
307.2
614.4
2.4
4.8
9.6
19.2
38.4
76.8
153.6
307.2
614.4
4.8
9.6
19.2
38.4
76.8
153.6
307.2
614.2
-
software ~on~ol, the 8274 can initiate a break se'luence
when trans~ittin'g data and, detect a break sequen!!e
when receiving da~. ,
--
Parity'
In order to detect transmission errors, a parity bit may
be added to the character data as it is transferred over
the data link. The parity bit is set or cleared to make the
total number of "one" bits in the character even (even
parity) or odd (odd parity). For example, the letter "A"
is represented by the seven-bit ASCII code' 1000001
(41H). The transmitted data code (with parity),for this
character contains eight bits; 01000001 (41H) for even
parity and 11000001 (OCIH) for odd parity. Note that a
single bit error changes the parity of the received character and is therefore easily detected.. The 8274 support~' both odd and even parity checking as well as a
parity disable mode to support binary data 'transfers.
Hardware Environment,
The 8274 MPSC interfaces to the system processor over
an 8-bit data bus. Each serial I/O channel responds to
two I/O or memory addresses as shown in Table 2. In
addition, the MPSC supports vectored and daisychained interrupts.
The 8274 may be configured for memory-mapped or
I/O-mapped operlltion.
Table 2. 8274 Addressing
cs
A,
AI
Read Operation
Write Operation
0
0
0
1
0
1
01
o~
1 I
1 .
X
X
Ch A Data Read
Ch A Status Read
Ch B Data Read
Ch B Status Read
High Impedance
Ch A Data Wnte
Ch A Command/Parlmeter
Ch B Data Write
Ch. B Command/Parameter
High Impedance
0
0
1
The 8274-processor hardware interface can be configured in a flexible manner, depending on the operating
mode selected-polled, interrupt-driven, DMA, or
WAIT. Figure 3 illustrates typical MPSC configurations
for use with an 8088 microprocessor in the polled and
interrupt-driven modes.
Communication Modes
Serial data transmission between two devices can occur in one ofthree modes. In the simplex transmission
mode, a data link can transmit data in one direction
only. In the half-duplex mode, the data link can transmit
data ih both directions, but not sllnultaneously. In the
full-duplex mode (the most common), the data link ~an
transmit data in both directions simultaneously. The
8274 directly supports the full-duplex mode and will
interface to simplex and half-dupiex conimunication
data links with appropriate, software' controls.
BREAK Condition
Asynchronous data links often include a special'sequence known as a break condition. A break condition
is initiated when the transmitting device forces the data
link to a spacing state (binary 0) for ari extended lenSili
of time (typically 150 milliseconds).' Many terminals
contain keys to initiate a break sequence. Under
All serial-to-parallel conversion, parallel-ta-serial conversion, . and parity checking required during
asynchronous serial I/O operation is automatically performed by.the MPSC.
Operational Interface
Command, parameter, and status information is stored
in 22 registers withjn-the MPSC;: (8 writable registers
and 3 readable registers for each channel). These registers are all accessed by means of'the command/status
ports for. each channel. An jntefnaI. pointer r~gister
selects ,which of the command or status re~sters will be
written or read during a command/status access of an
MPSC channel. Figure 4 diagrams the command/ status
register. architecture for each ~~rial channel. In the
following discussion, the writable registers will be
referred to as WRO through WR7 and the readable registers will be referred to as RRO through RR2.
7-82
AP-134
a) Polled Configuration
~. ADDRESS BUS
...
-"
~
I
I
~DATA BUS
1l
im
WR
.....
"-
8205,
~
~
I--
DBO-7
INTA
Ao
~
~
.
,.
A,
Vee
~
MPSC
CS
RD
WR
b) Dalsy-chalned IJlterrupt Configuration
Vee
INT~{
INTA
CPU
INT
~
IPI
~
INTA
IPO
6
INT
IPI
MPSC
HIGHEST PRIORITY
},
INT
INTA
IPO
MPSC
INTA
IPI
IPO
MPSC
LOWEST PRIORITY
,
Figure 3_ 8274 Hardware Interface for Polled and Interrupt-driven Environments
The least-significant three bits of WRO are automatically loaded into the pointer register every time WRO is
written. After reset, WRO is set tei zero so that the first
write to a command register causes the data to be
loaded into WRO (thereby setting the pointer register).
After WRO is written, the following read or write accesses the register selected by the pointer. The pointer is
reset after the read or write 'operation is completed. In
this manner, reading or writing an arbitrary MPSC
channel register requires two 110 accesses. The first
access is always a write command. This write command
is used to set the pointer register. The second access is
either a read or a write command; the pointer regis~r
(previously set) will 'ensure that the correct internal
register is read or written. After this second access, the
pointer register is automatically reset. Note that writI ing WRO and reading RRO does not require presetting of
'/ the pointer register.'
"
During initialization and normal MPSC operation,
various registers are read and/ or written by the system
processor. These actions are discussed in detail in the
following paragraphs. Note that WR6 and WR7 are not
used in the asynchronous communication modes.
RESET
When the 8274 RESET line is activated, both MPSC
channels enter the idle state. The serial output lines are
forced to the marking state (high) and the modem interface signals (iTS, DTR) are forced high. In addition,
the pointer register is set to zero.
.
7-83
AP-134.
COMMAND/STATUS
POINTER
:::I :
r
D2
D1
DO
0
0
0
~I'
W :
R
~I
W
R
~I
W
R
0
'"'
II
1 1
II
2
;
R
R
R
R
R
R
0
2
0
0
. 1
~I
0
0
0
Read Regllte'"
w
R
·1
W
R
~I
W
R
~I
W
R
6
W
,R
7
~I
I
..sa
Msa
4
,MSa
Lsa
Write Regllte ..
Figure 4. Command/Status Register Architecture (Each Serial Channel)
External/Status Latches
The MPSC continuously monitors the state of four external/status conditions:
I
1. CTS-clear-to-st(nd input pin.
'. "
2. CD-carrier-detect input pin.
3: SYNDET~sync~detect input pin. This pifl may be
used as ageneral-purpo,se input in t~e, asynchron~us
communication mode.
'
,
4. BREAK..,...a break condition (series of space bits on
the receiver input pin).
A change of state in 'any of these monitored conditions
will cause the associated status bitin RRO '(Appendi-xA)
to be latched (and optionally cause an interrupt).
Error 'Reporting
Three error.cqnditi~qs may be encountered dwing data;
reception in the asynchronous mode:
AP-134
1. Parity. If parity bits are computed and transmitted
with each character and the MPSC is set to ·check
parity (bit 0 in WR4 is set), a parity error will occur
whenever the number of "1" bits within the character (including the parity bit) does not match the
odd/even setting of the parity check flag (bit 1 in
WR4).
all remaining bits must be set to 1. The following
table illustrates the data formats for transmission of
1 to 5 bits of data:
D7 D6 D5
2. Fiaming. A friUning errol' will occur if a stop bit is
not detected immediately following the parity bit (if
parity checking is enabled) 'or'immediately following
the most-significant data bit (if parity checking is not
enabled).
an
3. Overrun. If input character has been assembled
but the receiver buffers are full (becaus.e the. previously received characters have not been read by the
system processor), an overrun error will occur.
When an overrun error occurs, the input character
that has just been received will overwrite the iIIlinediately preceding character.
Transmltter/R,cel~er Initialization
In order to operat~ in the asynch~onous mode,.each
MPSC channel must be initialized with the following
information:
1. Clock Rate. This parameter'is specified by bits 6 and
7 ofWR4. The clock rate may be set to 16, 32, or 64
time,s the data-link bit rate. (See Appendix A for WR4
detajls.)
2. Number of Stop Bits. This parameter is specified by
bits 2 and 3 of WR4. The llumher of stop. hits may be
setto 1, 1~, or2. (See Appendix A forWR4 details.)
3. Parity Selection. Parity may be set for odd, even, or
no parity by bits 0 and 1 of WR4.· (See Appendix A
for WR4 details.)
.
4. Receiver Character Length. This parameter sets the
length of received characters to 5, 6, 7, or 8.bits. This
parameter is specified by bits 6 and 7 ofWR3. (See
Appendix A for WR3 details.)'
.
5. Receiver Enable. The serial-channel recei~er operation may be enabled or disabled by setting or clearing bit 0 of WR3. (See Appendix A for WR3 details.)
1
,1
·0
0
0
0
0
0
Number of
Blti Transmitted <
,04 D3 D2 D1 DO (Character Length)
0 0 0 c.
1
0 0 0 c c
2
0 0 c c c
3
0 c C c c.
4
C ,.
.C
C
C
C
S
,
7. 'Transmitter Enable. The serial channel' transmitter
operation may be enabled or disabled by setting or
clearing bit 3 of WRS. (See Appendix A for WRS
details.)
For data transmissions via a modem or RS-232-C interface, the following information must also be specified:
1. Request-to-Send/Data-Terminal-Ready. Must be
set to indicate status of data· terminal equipment.
Request-to-send is controlled by bit 1 of WR5 and
data terminal ready is controlled.by bit 7. (See Appendix A for WRS details.)
2. Auto Enable. May be set to allow the MPSC to
automatically enable the channel transmitter when
·the clear-to-send signal is active and· to automati- .
cally enable the receiver when the carrier-detect
signal is active. Auto Enable is controlled by bit 5 of
·WR3. (See Appendix A for WR3 details.)
During initialization, it is desirable to guaflllltee that the
extern\ll/ status latches reflect the latest interface informatiqn. Since up to two state changes are internally
stored by the MPSC, at least two Res~t External/Status _
I~terrupt cOimnanlis rilUst be issued. This procedure is
most easily accomplished by simply issuing this reset
command whenever the pointer register is set during
initialization.
An MPSC initialiZation procedure (MPSC$RX$INIT)
for asynchrc;mOlis communication is listed ill Appendix'
B. figure. 5 illustrates typical MPSC initialization
parameters for use with this procedure.
6. Transmitter Character Length. This parameter Sets
the length of transmitted characters to 5, 6, 7, or 8
bits. This parameter is specified by bits 5 and 6 of
WR5. (See Appendix A for WRS details.) Characters
of less than 5 bits in length"may be transmitted by
setting the transmitted length to five bits (set bits 5
and 6 of WR5 to 1).
The MPSC then determines the actual number of
bits to be transmitted from the character data byte.
The bits to be transmitted must be right justified in
the data byte. the next' three bits must be' set to 0 and
call MPSC$RX$INIT(41,
1,1,0,1,
3,1,1,
3,1,1,0,1);
initializes the 8274 at address 41 as follows:
X16 clock rate
1 stop bit
.Odd parity .
fl.bit characters (Tx and Rx)
Enable tra~sinittRxS>TxA>
TxS >eXTA'
> EXTS"
>
0= PRIORITY RxA >TKA >RxB
then the fixed vector, programmed in
WR2, is returned from an interrupt acknowledge sequence. If the bit is set, then
the vector returned from an interrupt acknowledge is variable as shown in the
Interrupt Vector Table.
D4,D3
TxS >EXTA" >EXTB'
~
0
0
8085 MODE 1
0
1
8085 MODE 2
1
0
8066188 MODE
1
1
ILLEGAL
Receive Interrupt Mode.
1;:: VECTORED INTERRUPT
0= NON VECTORED INTERRUPT
00
Receive Interrupts/DMA Disabled.
01
Receive Interrupt on First Character
Only or Special Condition.
10
Interrupt on All Receive Characters of
Special Condition (Parity Error is a Special Receive .Condition).
-
I I
Interrupt on All Receive Characters or
Special Condition (Parity Error is not a
Special Receive Condition).
D5
Wait on Receive/Transmit-when the
following conditions are met, the RDY pin
is activated, otherwise it is held in the
MUST BE ZERO
1
PIN 10::::: SYNDET 8
o
PIN 10
= Rr~8
*EXTERN'AL STATUS INTERRU'PTONLY IF EXT INTERRUPT ENA!:JLE (WR1. DO) IS
7-91
seT
DI,DO
System Configuration-These specify
the data transfer from MPSC channels to
the CPU, either interrupt or DMA based.
00
Channel A and Channel B both use
interrupts.
AFNe done elC:ternally.
-
-
'IX ENABLE
5ENO BREAK
0
TX 5 BITS OR LESS/CHAR
0
I
TX 7 BITS/CHAR
I
0
TX 6 BITs/CHAR
I
I
TX 8 BITS/CHAR
0
DTR
01 '
Request to Send-a one in this bit forces
the RTS pin active (low) and zero in this
bit .forces the RTS pin inactive (high).
03
Transmitter Enable-a zero in this bit
forces a marking state on the transmitter
output. If this bit is set to zero during data
or sync character transmission, the marking state is entered after the' character has
been sent. If this bit is set to zero during
transmission of a CRC character, sync or
flag bits are substituted for the remainder
of the CRC bits.
D4
Send Break-a one in this bit forces the
transmit data low. A zero in this bit allows
norma. transmitter operation.
06,D5
Transmit Character length.
00
Transmit'S or less bits/character.
01
Transmit 7 bits/character.
10
. Transmit 6 bItS!character.
AFN-02076B
AP·134
Transmit 8 bits/character.
I I
D4
SYNDET-In asynchronous modes, the
operation of this bit is similar to the CD
status bit, except that it shows the state of
the SYNDET input. Any High-to-Low
trabsition on the SYNDET pin sets this
bit, and causes an External/Status interrupt (if enabled). The Reset External/Status Interrupt command is issued
to clear the interrupt. A Low-to-High
transition clears this bit and sets the External/Status interrupt. When the External/ Status interrupt is set by the change
in state of any other input or condition,
this bit shows the inverted state of the
SYNDET pin at time of the change. This
bit must be read immediately following a
Reset External/ Status Interrupt command to read the current state of the
SYNDET input.
D5
Clear to Send-this bit contains the inverted state of the CTS pin at the time of
the last change of any of the External/Status bits (CD, CTS, Sync/Hunt,
Break/ Abort, or Tx Underrun/EOM).
Any change of state of the CTS pin causes
the CTS bit to be latched and causes an
External/Status interrupt. This bit indicates the inverse of the current state of
the CTS pin immediately following a
Reset External! Stahls Interrupt
command.
D7
Bits to be sent must be right justified, least-significant
'
bit fir~t, e.g.:
D7 D6 D5 D4 D3 D2 Dl DO
B5 B4 B3 B2 BI BO
o 0
Read Register 0 (RRO):
I I I I I I I I~°l
07
06
05
04
03
02
01
L~'.".
CHAR AVAILABLE
PENDING, (CHA ONl Yl
-'"
c
s
C
N
A
8
DO
Receive Character Available-this bit is
set when the receive FIFO contains data
and is reset when the FIFO is empty.
Di
Interrupt Pending-This InterruptPending bit is reset when an EOl command is issued and there is no other
interrupt request pending at that time. In
vector mode, this bit is set at the falling
edge of the second INTA in an INTA
cycle for an internal interrupt request. In
non-vector mode, this bit is set at the
falling edge of RD input after pointer 2 is
specified. This bit is. always zero in
.Channel B.
D2
Transmit Buffer Empty-This bit is set
whenever the transmit buffer is empty
except when CRC characters are being
sent in a synchronous mode. This bit is
reset when the transmit buffer is loaded.
This bit is set after an MPSC reset.
Break-in the Asynchronous Receive
mode, this bit is set when a Break sequence (null character plus framing error)
is detected in the data stream. The External/Status interrupt; if enabled, is set
when break is detected. The interrupt service routine must issue the Reset External/Status Interrupt command (WRO,
Command 2) to the break detection logic
so the Break sequence termination can be
recognized.
D3
Carrier Detect-This bit contains the
state of the CD pin at the time of the last
change of any of the External/ Status bits
(CD, CTS, Sync/Hunt, Break/Abort, or
Tx Underrun/EOM). Any change of state
of the CD pin causes the CD bit to be
latched and causes an External/ Status interrupt: This bit indicates current state of
the CD pin immediately following a Reset
External/ Status' Interrupt .command.
The Break bit is reset when the termination of the Break
sequence is detected in the incoming data stream. The
termination of the Break sequence also causes the External/Status interrupt to be set. The' Reset External/Status Interrupt command must be issued to enable
the break detection logic to look for the next Break
sequence. A single, extraneous null character is present
in the receiver after the termination ofa break; it should
be read and discarded.
7-94
AFN-020768
AP·134
ged with this error. Once the overwritten
character, is read, this, error condition is
latched uritil reset by the Error Reset
command. If the MPSC is in the "status
affects vector" mode, the overrun causes
a special Receive Error Vector.
Read Register 1 (RR1)
Msa
L.SI
1.'1 D61 D'I"I,
11
CALLS.
03 : D2 : 0'
00
NT
NOTUSED IN ASYNCHRONOUS MODES
PARITY ERROR
D6
Ax OVERRUN ERROR
CAe/FRAMING ERROFf
Framing Error~in async modes, a one in
this bit indicates a receive framing error.
It can be reset by issuing an Error Reset
command.
END OF FRAME (SDLe/HDLe MODE)
Read Register 2 (RR2):
DO
All sent-this bit is set when all characters have been sent, in asynchronous
modes. It is reset when characters are in
the transmitter, in asynchronous modes.
In synchronous modes, this bit is always
set.
D4
Parity Error-ifparity is enabled, this bit
is set for received characters whose
parity does not match the programmed
sense (Even/Odd). This bit is latched.
Once an error occurs, it remains set until
the Errot Reset command is written.
D5
RR2
Channel B
D7-DO
Interrupt vector-contains the interrupt
vector programmed into WR2. If the
"status affects vector" mode is selected,
it contains the modified vector. (See
WR2.) RR2 contains the modified vector
for the highest priority interrupt pending.
If no interrupts are pending, the variable
bits in the vector are set to one.
Receive Overrun Error-this bit indicates that the receive FIFO has been
overloaded by the receiver. The last character in the FIFO is overwritten and fiag-
7-95
AFN-02076B
AIM 34
APPENDIX B
MPSC-POLLED TRANSMIT/RECEIVE CHARACTER ROUTINES
MPSC$RX$INIT: procedure (cmd$port,
clock$rate,stop$bits,parity$type,parity$enable,
rx$char$length,rx$enable,auto$enable,
tx$char $leng th, tx$enable, dtr, brk, rts) ,
declare cmd$port
clockS rate
stop$bits
parity$type
parity$enable
rx$char$length
rx$enable
auto$enable
tx$char$length
tx$enable
dtr
brk
rts
output(cmd$port):30H!
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
/* channel r~set *1
output(cmd$port):14H,
/* point to WR4 */
/* set clock rate, stop bits, and parity information */
output(cmd$port)=shl(clock$rate,6) or shl(stop$bits,2) or shl(parity$type,l)
or parity$enable;
output(cmd$port)=13H,
/* point to WR3 */
/* set up receiver parameters */
'
output(cmd$port)=shl(rx$char$length,6) or rx$enable ot shl(auto$enable,5):
output(cmd$port)=15H,
/* point to WR5 */
/* set up transmitter parameters */
output(cmd$port)=shl(tx$char$length,5) or shl(tx$enable,3) or shl(dtr,7)
or shl(brk,4) or shl(rts,l);
end MPSC$RX$INIT;
('-96
AF~76B
AP-134
MPSC$POLL$RCV$CHARACTER: procedure(data$port,cmd$port,character$ptr) byte;
declare data$port
cmd$port
character$ptr
character
status
byte,
byte,
pointer,
based character$ptr byte,
byte;
declare char$avail
rcv$error
literally '1',
li ter ally '70H';
/* wait for input character ready */
while (input(cmd$portl and char$avail) <> 0 do; end;
/* check for errors in received character
output(cmd$port) =1;
if (status:=input(cmd$portl and rcv$error)
then do,
character=input(data$portl;
call RECEIVE$ERROR(cmd$port,statusl,
return 0;
end;
else do;
character=input(d'ata$portl,
return OFFH,
end;
*/
/* point to RRl */
/* read character to clear MPSC */
/* clear receiver errors */
/* error return - no character avail */
/* good return - character avail */
end MPSC$POLL$RCV$CHARACTER,
MPSC$POLL$TRAN$CHARACTER: procedure(data$port,cmd$port,character),
declare data$port
cmd$port
character
byte,
byte,
byte,
declare tx$buffer$empty literally '4',
/* wait for transmitter buffer empty */
wh'ile not (input(cmd$port) and tx$buffer$emptyl do, end,
/* output character */
output(data$portl=character,
end MPSC$POLL$TRAN$CHARACTER:
RECEIVE$ERROR: procedure (cmd$port,statusl :
declare cmd$port
status
output(cmd$portl=30H,
byte,
byte,'
/* error reset */
/* *** other application dependent
error processing should be placed here
*** */
end RECEIVE$ERROR,
AFN-02076B
AP-134
TRANSMIT$BUFFER: procedure(buf$ptr,buf$length)
declare
buf$ptr _
buf$length
poin ter ,
byte,
/* set up transmit buffer pointer and buffer length in global variables for
interrupt service */
tx$buffer$ptr=buf$ptr,
transmit$length=buf$length,
/* setup status for not complete */
/* transmit first character */
/* first character transmitted */
transmit$status=not$complete,
output(data$port)=transmit$buffer(O) ,
transmit$index=l,
/* wait until transmission complete or error detected */
while transmit$status = not$complete ~o, end,
if transmit$'status <> complete
then return false,
else return true;
end TRANSMIT$BUFFER,
RECElVE$BUFFER: procedure (buf$ptr,buf$length$ptr);
declare
pointer,
buf$ptr
buf$length$ptr pointer,
based buf$length$ptr byte,
buf$length
/* set up receive buffer pointer in global variable for interrupt service */
rX$buffer$ptr=buf$ptr,
receive$index=O,
receive$status=not$complete,
/* set status to not complete */
/* wait until buffer received */
while receive$status= not$complete do, end;
buf$length=receive$length,
if receive$status = complete
then return true;
else return false,
end RECElVE$BUFFER,
7-98
AFN-Q2076B
AP-134
MPSC$RECEIVE$CHARACTER$INT: procedure interrupt 22H:
/* ig;ore input if no open buffer */'
if receive$status <> not$complete then return:
/* check for receive buffer overrun */
if receive$index = 128
then receive$status=overrun:
else do:
/* read character from MPSC and place in buffer - note that the
parity of the character must be masked off during this step if
the character is less than 8 bits (e.g., ASCII) */
receive$buffer(receive$index) ,character=input(data$port) and 7FE:
receive$index=receive$index+l:
/* update receive buffer index */
/* check for line feed to end line */
i f character = line$feed
then do: receive$length=receive$index: receive$status=complete:
end:,
~nd:
end MPSC$RECEIVE$CHARACTER$INT:
MPSC$TRANSMIT$CHARACTER$INT: procedure interrupt 20H:
/* check for more characters to transfer */
if transmit$index < transmit$length
then do:
/* write next character from buffer to MPSC */
ou tpu t (da ta$port) =transmi t$buffe.r (transmi t$ index) :
transmit$index=transmit$index+l:
/* update transmit buffer index */
end:
else transmit$status=complete:
end MPSC$TRANSMIT$CHARACTER$INT:
RECElVE$ERROR$INT: procedure interrupt 23H:
declare
temp
byte:
output(cmd$port)=l:
receive$status=input(cmd$port) :
temp=input(data$port) :
output(cmd$port)=error$reset:
/* temporary character storage */
/* point to RRl */
/* discard character */
/* send error reset */
/* *** other application dependent
error processing should be placed here
*** */
end RECElVE$ERROR$INT:
EXTERNAL$STATUS$CHANGE$INT: procedure interrupt 2lH:
transmit$status=input(cmd$port)
output (cmd$port) =reset$ext$status:
/* input status change information */
•
/* *** other application dependent
error processing should be placed here
*** */
end EXTERNAL$STATUS$CHANGE$INT:
7-99
AFN-02076B
APPENDIXC
INTERRUPT-DRIVEN TRANSMIT/RECEIVE SOFTWARE
declare
/* global variables for buffer manipulation */
rx$buffer$ptr
pointer,
/* pointer to receive buffer */
receive$buffer based rx$buffer$ptr(128) byte,
/* indiciates receive buffer status */
receive$statu:,
byte initial (OJ ,
receive$index
byte,
/* curren~ index into receive"buffer */
receive$length
byte,
1* length of final receive buffer */
tx$buffer$ptr
pointer,
1* pointer to transmit buffer *1
transmit$buffer based tx$buffer$ptr (12B» byte,
transmit$status
byte initial{O),
1* indicates transmit-buffer status */
byte-,
transmit$index
/* current index into transmit buffer *1
transmit$length
byte,
1* length of buffer to be trans~itted *1
cmd$port
data$port
a$cmd$port
b$cmd$port
line$feed
not$complete
complete
overrun
literally
literally
literally
literally
literally
literally
literally
literally
'43H',
'41H',
'42H',
'43H',
'OAH',
'0'
'OFF-H'; '.
'1',
channel$reset
error$reset
reset$ext$s ta t.us
literally 'ISH',
literally '30H'~
literally 'lOH';
7-100
AFN·02076B
MPSC$INT$INIT: procedure (clock$ra·t,e, s.\:bp$bits, par i tY$type, par i ty$enable,
rx$char$length,rX$enable,autD$enable,
tx$char$length,tx$enable,dtr,brk,rts,
ext$en,tx$en,rx$en,stat$affects$vector,
config,priority,vector$int$mode,int$vector) ;
declare
clock$rate
stop$bits
parity$type
pa.r i ty$enable
rx$char$,length
rx$enable
auto$enable
tx$char$length
tx$enable
dtr
brk
rts
ext$en
tx$en
rx$en
stat$aff$vector
config
priority
vector$int$mode
int$vector
/*
/*
/*
/*
/*
/*
'/*
/*
/*
byte,
byte,
byte,
bY,te,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte;
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
output(b$cmd$port)=channel$reset;
2-bit
2-bit
l-bit
I-bit
2-bit
l-bit
l-bit
2-bit
l-bit
l-bit
l-bit
l-bit
l-bit
I-bit
2-bit
l.,.bit
2-bit
l-bit
3-bit
a-bit
code for clock rate divisor */
code for number of stop bits */
parity type */
parity enable */
receive character length */
receiver enable */
auto enable fli?g */
transmit character length */
transmitter enable */
status of DTR pin */
data link break enable */
status of RTS pin */
external/status enable */
Tx interrupt enable */
Rx interrupt enable/mode */
status affects vector flag */
system config - int/DMA */
priority flag */
interrupt mode code */
interrupt type code */
/* channel reset */
output(b$cmd$port)=l4H;
/* point to WR4 */
/* set clock rate, stop bits, and parity information */
output(b$cmd$port)=shl(clock$rate,6) or shl(stop$bits,2) or shl(parity$type,l)
or parity$enable;
output(b$cmd$pott)=l3H;
/* point to WR3 */
/* set up receiver parameters */
output(b$cmd$port)=shl(rx$char$length,6) or rx$enable or shl(auto$enable,5);
outp~t(b$cmd$port)=l5H;
/* point to WR5 */
/* set up transmitter parameters */
output (b$cmd$port) =shl(tx$char$lenqth, 5) or shl (tx$enable,3) or, shl(dtr, 7)
or shl(brk,4) or.shl(rts,l);
output (b$cmd$port) =l2H;
/* set up inter~upt vector */
output(b$cmd$port)=int$vector)
/* point to WR2 */
output(a$cmd$port)=12H;
/* point to WR2, channel A */
/* set up interrupt modes */
output{a$cmd$port)=shl(vector$int$mode,3) or shl(priority,2) or config;.
output{b$cmd$port)=lIH;
/* set up interrupt"enables */
output(b$cmd$port~=shl(rx$en,3)
/* point to WRl */
or shl(stat$aff$vector,2) or shl(tx$en,l)
or ext$en;
end MPSC$INT$INIT;
7-101
AFN-Q2076B
AP.13,~t
APPENDIXD
APPLICATION EXAMPLEUSINGSDK-86
This application example shows the 8274 in a simple
iAPX-86/88 system. The 8274 controls two separate
asynchronous channels using its internal interrupt controller to request all data transfers. The 8274 driver
software is described w.hich transmits and receives data
buffers provided by the CPU. Also, status registers are
maintained in system memory to allow the CPU to
monitor progress of the buffers and error conditions.
THE HARDWARE .INTERFACE
Nothing could be easier than the hardware design of an
interrupt-driven 8274 system. Simply connect the data
bus lines, a few bus control lines , supply a timing clock
for baud rate and, voila, it's done! For this example, the
ubiquitous SDK-86 is used as the host CPU system. The
8274 interface is constructed on the wire-wrap area
provided. While discussing the hardware interface,
please refer to Diagram 1.
Placing the 8274 on the lower 8 bits of the 8086 data bus
allows byte-wide data transfers at even I/O,addresses.
For simplicity, the 8274's CS/ input is generated by
combining the M-IO/ select line with address lineA7 via
a 7432. This places the 8274 address range in multiple
spots within the 8086 I/O address space. (While fine for
this example, a more complete address decoding is
recommended for actual prototype systems.) The
8086's Al and A2 address lines are connected to the AO
and Al 8274 register select inputs respectively. Although other port assignments are possible because of
the overlapping address spaces, the following I/O port
assignments are used in this example:
Port Function
I/O Address
Data channel A
Command/status A
Data channel B
Command/status B
0002H
0004H
0006H
OOOolf
To connect the 8274's interrupt controller into the system an inverter and pull-up resistor are needed to convert the 8274's active-low, interrupt-request output,
IRQ, into the correct polarity for the. 8086's INTR
interrupt input. The 8274 recognizes interruptacknowledge bus cycles by connecting the INTA
(INTerrupt Acknowledge) lines of the 8274 and 8086
together.
The 8274 ReaD and WRite lines directly connect to the
respective 8086 lines. The RESET line requires an inverter. The system clock for the 8274 is provided by the
PCLK (peripheral clock) output. of the 8284A clock
generator.
On the 8274's serial side, traditional 1488 and 1489
RS-232 drivers and receivers are used for the serial
interface. The onboard baud rate generator supp1ies the
channel baud rate timing. I~ this example, both sides of
both channels operate at the same baud rate although
'this certainly is not'a requirement. (On the SDK-86, the
baud rate selection is hard-wired thrujumpers. A more
flexible approach would be to incorporate an 8253 Programmable Interval Timer to allow software. configurable baud rate selection.)
That's all there is to it. This hardware interface is
completely general-purpose and supports all of the 8274
features except the DMA data transfer mode which
requires an external DMA controller. Now let's look at
the software interface.
SOFTWARE INTERFACE
In this example, it is assumed that the 8086 has better
things to do rather than continuously run a serial channel. Presenting the software as a group of callable procedures lets the designer include them in the main body
of another program. The interrupt-driven data transfers
give the effect that the serial channels are handled in the
background while the main program is executing in the
foreground. There are five basic procedures: a serial
channel initialization routine and buffer handling
routines for the transmit and receive data buffers of
each channel. Appendix D-l shows the entire software
listing. Listing line numbers are referenced as each
major routing is discussed.
The channel initialization routine (INITIAL 8274),
starting with line #203, simply sets each channel into a
particular operating mode by loading the command registers of the 8274. In normal operation, once these
registers are loaded, they are rarely changed. (Although
this example assumes a simple asynchronous operating
mode, the concept is easily extended for the byte- and
bit-synchronous' modes.)
7-102
AFN·02076B
AP-134
CONTROL
LINES
CONNECTOR
ADDRESS
BUS EXPANSION
CONNECTOR
(FOR DETAILED DESCRIPTION ON SDK-86, REFER TO SDK-86 MCS-86 SYSTEM DESIGN KIT
ASSEMBLY MANUAL)
SOK·88
EXPANSION
BUS
INTR
AD
..
'8
Wi!
'8
im'A
5.
pelK
36
RST
D7
D6
DS
D.
5V
751488
40
TxDA
28
iNT
22
AD
RlSA
21
Wi!
RxDA
27
A
elSA
CLK
,.••
CDA
RESET
12
,.
12
1.'
D.
,.
,.
,.
15,
17
D2
,.
18
Dl
DO
DB7
DTRA
DB.
751489
8274
DB5
TxOS
DB.
RTSB
DB.
DB2
RxDB
DBl
CTSB
CHANNEL
B
DB.
'COB
cs
MilO
CHANNEL
INTA
D'i'RB
A7
25
Al
2"
A2
A.
fiCA
Al
RiCA
TxCB
Rxes
WI
28
OND
2.
A2'
PIN 9
Figure 0-1. 8274/SDK-86 Hardware Interface
7-103
AFN-02076B
AP-1~~
The channel operating modes are contained in two
tables starting with line #163. As the 8274 has only one
command register per channel, the remaining seven
registers are loaded indirectly through the WRO (Write
Register 0) register. The first byte of each table entry is
the register pointer value which is loaded into WRO and
the second byte is the value for that particular register.
The indi~ated modes set the 8274 for a~yncllfonous
operation with data characters 8 bits long, no parity,
and 2 stop bits. An X 16 baud rate clock is assumed. Also
selected is the "interrupt on all RX character" mode
with a variable ittterrupt vector compatible witll the
8086/8088. The. transmitters are enabled and all model'
control lines are put in. their active state.
In .tddition to initializing the 8274. this routine also sets
up the appropriate interrupt vectors. The 8086 assumes
the first lK bytes of memory contain up to 256 separate
interrupt vectors. On the SDK-86 the initial2K bytes of
memory is RAM and therefore must be initialized with
the appropriate vectors. (In a prototype system, this
initial memory is probably ROM, thus the vector set-up
is not needed.) The 8274 supplies up to eight different
interrupt vectors. These vectors are developed from
internal conditions such as data requests, status
changes, or error conditions for each channel. The initialization routine arbitrarily assumes that the initial
8274 vector corresponds to 8086 vector location 80H
(memory location 200H). This choice is arbitrary since
the 8274 initial vector location is programmable.
After returning to the main program, all transmitter
data transfers are handled via. the transmitter-interrupt
service routines starting at lines #360 and #443. These
routines start by issuing an End-Of-Interrupt command
to the 8274. (This command resets the internalinterrupt controller logic of the 8274 for this particular
vector and opens the logic for other internal interrupt
requests. The routines next check the length count. If
the buffer is completely transmitted, the transmitter
empty flag; T)<-EMPTY_CHx, is set and a command is
issued to the 8274 to reset its interrupt line. Assuming
that the buffer is not completely transmitted, the next
character is output to the transmitter. In either case, an
interrupt return is executed to return to the main CPU
program.
The receiver commands start at line #314. Like the
transmit commands, it is assumed that the CPU has
initialized the receive-buffer-pointer public variable,
RX_POINTER_CHx. This variable points to the first
location in an empty receive buffer. The command
routines clear. the .receiver ready flag, RX_READY_CHx, and then set the receiver enable bit in the 8274
WR3 register. With the receiver now enabled, any
received characters are ·placed in the receive buffer
using interrupt-driven data transfers.
The received data service routines, starting at lines
#402 and #485, siinply place the received character in
the buffer after first issuing the EOI command. The
character is then compared to an ASCII CR. An ASCII
CR causes the routine to set the receiver ready flag,
RX_READY _CHx, and to disable the receiver. The
CPU can interrogate this flag to determine when the
buffer contains a new line of data. The receive buffer
pointer, RX_POINTER_CHx, points to the last
received character and the receive counter, RX_COUNTElLCHx, contains the length.
Finally, the initialization routine sets up the status and
flag in RAM. The meaning and use of these locations are
discussed later.
Following the initialization routine are those for the
transmit commands (starting with line #268). These
commands assume that the host CPU has initialized the
publically declared variables for the transmit buffer
pointer, TX_POINTER_CHx, and the buffer length,
TX_LENGTH_CHx. The transmit command routines
simply clear the transmitter empty flag, TX EMPTY
CHx, and load the first character of the buffer into the
transmitter. It is necessary to load the first character in
this manner since transmitter interrupts are generated
only when the 8274's transmit data buffer becomes
empty. It is the act of becoming empty which generates
the interrupt not simply the buffer being empty, thus the
transmitter needs one character to start.
That completes our discussion ofthe command routines
and their associated interrupt service routines. Although not used by the commands, two additional service routines are included for completeness. These
routines handle the error and status-change interrupt
vectors.
The error service routines, starting at lines #427 and
#510, are· vectored to if a special receive condition is
detected by the 8274. These special receive conditions
include parity, receiver overrun, and framing errors.
When this vector is generated, the error condition is
indicated in RRI (Read .Register I). The error service
routine issues an EOI command, reads RRI and places,
it in the ERROlLMSG_CHx variable, and then issues
The host CPU can monitor the transmitter empty flag,
TX_EMPTY_CHx, in order to determine when transmission ofthe buffer is complete. Obviously, the CPU
should only call the command routine after first checking that the empty flag is set.
7-104
AFN-02076B
intJ
AP-134
a reset error command to the 8274. The CPU can monitor the error message location to detect error conditions. The designer, of COUTl!e, can supply his own error
service TOutine.
read RRO, place its contents in the STATUS_MSG_CHx variable and then issue a reset external status
command. Read Register 0 contains the state of the
modem inputs at the point of the last change.
Similarily, the status-change TOutines (starting linel\
#386 and #469) are initiated by a change in the modemcontrol status lines CTS/, CDI, or SYNDET/. (Note
that WR2 bit 0 controls whether the 8274 generates
interrupts based upon changes in these lines. Our WR2
parameter is such that the 8274 is progrl;Ullmed to ignore
changes for these inputs.) The service'TOutines simply
Well, thafs it. This application example has presented
useful, albeit very simple, routines showing how the
8274 might be used to transmit and receive butTers using
an asynchronous serial format. Extensions for byte- or
bit-synchronous formats would require no hardware
cha.n,es due to the highly programmable nature of the
8274's serial formats.
8274 APPLICATION BRIEF PROGRAM
ISIS-II It:S-86 IR:RO AS5EIIlI.ER Y2. 1 R5SEIIlI.Ya: IQlllE ASYIQ
0lJECT IQlllE PUaD IN :Fl:ASYI«:B.1RI
fISSEIIllfR INYOkED ~. A5II86. Fl. ASYIQ. SRC
LOC IRI
LII£
SW/CE
1
; ......... 111111' ..... ,1111111111111111111111111111111111111111"
2
9
18
11
i*
8274 RPPLlCATIQI BRIEF PR!MRIII
i*
i*
i*
i*
,* TI£ 8274 15 INITIIU2EO FIR SIIfILE RSYIDI!(HJJS SERlfI.
i * FOMIT fit) YECTm I~-oRI~ DATR lJ/.fWSFERS.
i' TI£ INITIRLIZRTIQI ROOTII£ II.SO LOfI>S TI£ 88$6'5 INTERRIPT
i * 'lECTIR TfIlI.E FR(JI 11£ COOE SEGI£NT INTO Lilol RAIl QI TI£
i* SDK-86. TIE TRfffSIIITTER fit) RECEIVER ARE LEFT ENfRED.
12
it
3
4
5
6
7
8
13
14
15
16
17
18
19
28
21
22
23
24
,25
26
27
28
29
38
i * FII! TRfffSIIIT, TI£ CPU PASSES IN IIEIO!Y TI£ POINTER a: A '
i * BlFFER TO TRfffSIIIT AN) TI£ BYTE l.OOTH a: TI£ BlFFER.
i * 11£ DATR TRANSFER PROCEED USIIIl INTERRlPT-oRI'IEN TRIIISFERS.
i' R STRTUS BIT IN IIEIO!Y IS SET IoI£H IF IU'FERS IS EIf'TY.
i*
>
*
*
*
*
*
•*
•
•*
*
•
,.•*
•
•
i * FIR RECEIVE, TI£ CPU PASSES TI£ POINTER a: ABUFFER TO FILL
i * TI£ BlFFER IS FIlJ.EI) IMTIL A 'CR..at!' CIBACTER IS RECEI'tS,
i * ASTRTUS BIT IS SET fit) TI£ CPU lIlY REfI) TI£ RX POINTER TO
i' DETERIIII£ TI£ LOCATIQI a: TI£ LAST CII1RIUER.
i*
i * RLL ROOTII£S 1ft RSSIIED TO EXIST IN TI£ SIItE COOE SElJENT. *
i * CRLL'S TO TI£ SERVICE ROOTI~ fIlE ASSI.JEI) TO BE .StQT. II! **
i * INTRfISEliIENT (IH.Y TI£ RE'1'WI fIlIlRESS IP IS· QI TI£ STACK).
•*
•
,t
i*
i*
i*
*
,•
i 1111111111111, •• 111111111111111111111" .... "11111 .... 1111111111
7-105
AFf'l-()2076B
AP-134 ,
11:5-86, IR:RO fISSEIELER
fISVI«:8
LOCIilJ
WE
31
,32
n
34
.',
'
:l5
36
17
·38
19
48
41
42
41
44
45
46
47
48
49
,59
51
52
53
54
55
56
57
58
59
68
61
62
61
64
65
66
67
68
II8Il8
8882
8882
69
79
71
72
n
9994
8896
1!996
74
75
76
't
"
SW!CE
NII£
fISVI«:8 ; HOOll£ NII£ .
; PIIllIC DEClARATIIIIS FIR COItIN) ROOTII£S
PtaIC
PIIllIC
PlaIC
PIIllIC
PlaIC
INITIFL8274
; INITIflIZATtIW ROOTINE
l'X:.CtJIVN)..CIiI' , TX BlFFER COItIN) CIRI£L B
TlLCOItIN)_CIfI ; TX BlfFER 'mtIfIII) CtRI£L A '
RlLCOItIN)_CII! ; RlC BlfFER COItIN) CHfH£I. B
RlLCOItIN)_CIfI ; RlC BlFFER CCIIIN> CIRf£L A
; PIIllIC DEClARATIONS FIJI STATUS VARIABLES
PIIllIC
PIIllIC
PIIllIC
PIIllIC
PIIllIC
PIIllIC
PIIllIC
PIIllIC
PIIllIC
PIIllIC
RlLREfI)Y_CIIl
RllREfI)Y..CIfI
TX_£II'T'U:te
TX..EIf>TV_CIfI
RlLCWIT..cHB
RlLCWIT-CHfI
ERROIJ1SG..CIIl
ERRIILIISG-CIfI
STATUSJ!SG..CIfl
STATUSJlSG..CIfI
"RlC REfI)Y FLRG CIfl
,RlC REfI)Y FL"; CIfI
, TX EIf'TY FL"; CHB
; TX Elf>TY FLRG CHA
,RlC Blf~ ClUiTER CIII
; RX BlfFER ClUiTER CIfI
,ERROl Ft,.; CHB
; ERRtl! FL"; CIfI
; STATUS FLRG CHB
; STATUS FL"; CIfI
; PIIllIC DECUlRATIIIIS FOR VARIABLES PASSED TO ,T/£ TRftNSIIIT
,IN) RECEIVE 00tRI)S.
PIIllIC
PIIllIC
PI8.IC
PIIll'IC
PIIllIC
PIIllIC
TlLPOINTER-CHl
TlLLENGTlLCHB
Tll.POINTER_CHA
TX-LOOTlLCIfl
Rll.POINTE\lCKl
RX..PqINTER_CHA
; TX BlFFER POINTER FOR CHB
; TX LENGTH OF BlfFER FOR CIIl
, TX BlFFER POINTER FOR CHA
, TX LOOTH OF BlFFER FOR CIfI
,RlC BUFFER POINTER FIll CHB
,RlC BlfFER POINTER FOR CIfI
,110 PORT ASSIIHENTS
; CIRf£L A PORT ASSIGNl£NTS
DflTA_PORLCIfI
EQU
8
COItIN)..PORT..CIfI
EW
2
COItIN).PORLCIfI
STATUS..PORLCIfI
EQU
,DfITA ilO PORT
,(!WIRNI) POIIT
,STATUS PORT
,CHAIf£L BfoRT ASSI!H£NTS '
n
DflTA..PORT_CHB
mtIfIII)..PORLCHB
STATIJSJ'(I?T:.tHB
78
79
,"15(. SYSTEIt EQUATES
EQU
EQU
Eilu
4
6
COltlAIiLPORLCHB
; DflTA 110 PORT
,cat1AND PORT
,STATUS PORT
,:,.
99
999f)
81
9299
9599
82
EQU
CII-CHR
INT_TABLE.BASE EQU
COOE_START
EQlI
OOH
299H
599H
, ASC Il CF CIflRAC TER COPE
,INT VECTIlII BASE flOI1[SS
,STAAT LOCATION FOR (OOE
83
84
85+1 SEJECT
86
87
,~ ASSSIGMNTS FOR DflTA SEGI£NT
88
89
DATA
SEGI1ENT
99
7-106
"FN~076B
AP-134
1tS-86 IflCRO RSSEIIllER
ASYI«:8
LOC
LItE
(8J
8288 1!888
!Ii
92
93
94
95
96
97
98
99
198
1111
182
183
184
828A'!B811
185
8288
8288 8I11III
9282 8I11III
8284 8I11III
11296 8I11III
82IlC 8I11III
828E 8I11III
82188I11III
8212 8I11III
82148I11III
11216 8I11III
8218 8I11III
821A 1!888
SW!CE
; YECTlf! INTERRlfT TFIBlE - flSstI£ INlTlfI.. 8274 INTERRlf'T
,YECrn! IS NlJf!ER ae (f28IlH), F~ EfDi YECTOR, THE TAIlI..£
; ClllTAINS START LOCRTltw fH) COOE SEMNT J!EGISTER YPUf,
,TIE TIIIlE IS LIlOO) FRa1 PROI1
~
TlLYECTOR..CII!
TlLCUIII
INT_TABlE..IIfISE
ON
ON
9
8
,TX INTEI1I1IJ'T YECTIII FOR CII!
STS_YEtl'lLCIi ON
STS_CS..ell!
ON
8
8
,STATUS INTERRUPT
I!X-YECT~
ON
ON
8
8
,RX INTERRlf'T
ERR..YECTOR..cIII ON
ERR..c5..CIII
ON
8
8
,ERRtl! INTERI!IJ>T YECTIll Fill CH8
TlLYECTIR..CIIl
TlLCS..CIf!
ON
ON
8
9
,TX INTERRlf'T VECT{J! Fill elf!
STS_YECTOR..CIfI. ON
STS-CUIII
ON
8
8
,STATUS INTERRlf'T YECTIll Fill CHR
RX..YECTIR..CHR
RX..CS..CHR
ON
ON
8
8
; RX lNTERRlf'T YECTlf! FIll CHA
119
1211
121
122
123
ERR_YECTlR..CHR ON
ERR..CS..afI
ON
8
8
,ERRtl! INTERRlf'T YECTlf! Fill CIIl
124
,CIWf£l. B POINTERS
186
197
1ae
189
119
111
112
113
114
115
116
117
RlLCS_CIII
YECT~ F~
CII!
YE~
, FOR CII!
119
821C 8I11III.
&21E 8I11III
822Il 8I11III
11222 8I11III
&224 8I11III
e226 8I11III
822Il ae
8229 ae
822fI ae
822Il ae
822C
822E
8238
1!232
8I11III
8I11III
8I11III
8I11III
8234 ae
8235 ae
8236 ae
8Wae
125
126
127
128
129
138
131
132
133
134
135
136
137
138
139
148
141
142
; "ISC RAN LOCRTIIWS FOR CIfN£L STATUS
TlU'OINTER..CIfl
TX...l.ENlTH..C
RlU'OINTER..CIfl
RX..CIUIT_CIII
Tl<-EIf'TY..ell!
1!X..R£mY..eII!
STATUS..IISG..CIII
ERROI..MSG.CIII
IN)
ON
ON
ON
ON
08
08
08
08
; CIWf£l. A POINTERS
8
8
8
8
8
8
8
fH)
143
144
145 .
146
DATA
147
$EJECT
148 +1
POINTERS
STATUS
8
TlU'OINTER..CIIl ON
TlU.ENGTILCHR ON
RlU'OINTER..CIfI ON
RX..CIUIT..CIII
ON
Tl<-EIf'TY..CIII
08
I!X..R£mY_CIIl
08
STATUS..IISG..CIIl 08
ERRaUISILCHR 08
fH)
; TX BlFfER POINTER Fill CIII
; TX BlFfER l.EIIlTlI FOR CIII
;Rl( BlFfER POINm! Fill CIII
,RX L.OOTH CIUITER FOR CIII,
,TX 1)(1£ FlAG
,~ fI.Rl (1 IF CR-DI! RECElYED. ELSE 8)
,STATUS C!fIIGE'!IESSRlE
; ERROl STATUS LOCRTI!II (8 IF NO ERRIl!)
STATUS
e
8
8
8
8
8
8
II
) TX BlFfER POINTER Fill CIIl
,TX BtfFER LEfImI FOR CIIl
;RX BlFfER POINTER FOR CIIl
,RX L.OOTH CIUITER FOR CHR
,TX D!IIE FlAG
; ~ FlAG (1 IF CR..CII! RECEIVED, ELSE 9)
; STATUS CHIME I£SSfllE
,ERROR STATUS LOCRTI!II (9 IF ND ERRIl!)
ENDS
7-107
AFN-02076B
AP~134
MCS-86 IR:RO ASSEI1BlER
ASYt«:8
LOC ooJ
LINE
SOURCE
149
~
159
151
152
SEGI'IEIIT
ASSM CS.ABC,DS DATA,5S.DATA
~
CODE-START
153
154
155
156
157
158
159
8SIl0 91
058116
05e2 92
0583 88
8594 83
05e5
ce
I
***,"*************************~****************ic************~*
PARAltETERS FOR .CHANNEL INITIALIZATION
*
*
;*****************************************************..fI*******:t**
168
161
162
, CHfH£L B PflRM:TERS
163
CMDSTRB DB
, WRl - INTERRIPT ON filL RX C/fR, YflIIIABLE INT VECTOR, TX INT ENABLE
," L 16H
164
165
, IIR2 - INTERRIPT VECTOR
DB
2, ROOTII£S
,.,.
,.,.
,.,.
, -_ _ u* _ _ _ _*
INlTIfUZRTlal COlIN> F!R TIE 8274 - TIE 8274
IS SETlP fUmlllll TIl'TIE PARfl£TERS STt1!ED IN
PRIll fIlOYE STRRTIIil AT CII5TRB F(R CIM£l B IN)
CI!iTRA F!R CIM£l A.
•
•
•
•
•
, ..... IIIIIIIIIIJlIIIIIIIIII****III ............ IIIIIIIIII ........
INITIfL8274
,CIJ'Y IHTERRIJ'T YECTIR IP IN) CS YfI.t£S
lIlY
llLYECT!R..CIII, OFFSET XlfTIHB
lIlY
TX..CS...CI& CS
lIlY
STS_YECT!R.Cfm. OFFSET STAIHB
lIlY
STS..C5..CI& CS
lIlY
RlLYECT(IUIIl, OFFSET RCYIHB
RlLCS_CIII, CS
lIlY
lIlY
ERR_YECT!R..CNB, OFFSET ERRIHB
RlLCS_CNB, CS
lIlY
lIlY
llLYECTIR.£IIt (FFSET XlfTINrt
lIlY
TX..CS..CIfI, CS
lIlY
STS_YECT!R..CIfI, IlFFSET STAlHA
lIlY
STS_CS..att CS
lIlY
RlLYECT!R..CIfI, IlFFSET RCYIHA
lIlY
RX..CS..att CS
lIlY
ERR..YECT!R..CIfI, IlFFSET ERRIHA
lIlY
ERR..CS..att CS
FRIll PRIll TO RIll
,TX DATR YECllR CIII
,STATUS YECT!R CIII
; RX DATR YECT!R CHB
; ERR(R
YECT!R CIII
, TX DATR YECT!R CIfI
,STATUS YECT!R CIfI
; RX DATR YECT!R CIfI
• ERR(R
YEC1lR CIfI
,CIJ'Y SETlP TABLE PARfI'IElERS INTO 8274
lIlY
lIlY
CALL
lIlY
lIlY
CALL
01, OFFSET ctrISTRB
ox, -ctlfRt)..PIRT-till
SETlP
01, OFFSET CII>STRA
ox, COIIN>..PIRT-tIII
SETlP
; INITIALIZE STATUS BYTES
lIlY
lIlY
lIlY
lIlY
lIlY
lIlY
lIlY
lIlY
lIlY
lIlY
lIlY
lIlY
JE
; CIJ'Y CIII PARfl£TERS
,INITIALIZE CIfI
; CIJ'Y CIfI PARfI'IElERS
IN) FUWlS
11)(,8
ERRIlU\SG..CNB, AL
ERRIlU\SG..CIfI AL
STATUSJISG-Il& AL
STfITUS..IISG.. AL
AX
AX
1Ill.CWfl'-tIII,
IIll.CWfl'_CIfI,
ILl
RX..REfI)Y_CNB,
RX..REfI)Y_CIfI,
TlLEII'TY-till,
TlLEII'TY.£IIt
AL
AL
AL
AL
STI
RET
SETlP: lIlY
CIt' >
,INITIALIZE CIII
AL, [Oil
IL8
DII£
; ClEfR ERR(R FUll CIII
,ClEfR ERR(R FUll OIl
,ClEfR STATUS FUll CHB
; ClEfR STATUS FUll OIl
,ClEfR RX CWITER CHB
; ClEfR RX crufTER OIl
DII£ FLBi CHB
DII£ FUll OIl
DII£ FUll till
DII£ FUll OIl
IHTERRlJ'TS
; RETIRH - DII£ 1I1TH SETIJ'
; SET fIX
,SET RX
; SET TX
; SET TX
; ENfIlE
; PARfI£TER ClJ'Y111l ROOTII£
7-109
AfI\HI2078B
Ap·134
LOC OBJ
95ft5 EE
95fI6 47
85A7EBF6
85A9 C3
LINE
SOURCE
251
OUT
It«:
252
253
254
JIf'
DOI£:
DX, "'DI
SElU'
,OUTPUT PARAItETER
,POINT AT NEXT PARAI1ETER
;60 LOA) IT
,DOI£ - SO RETml
RET
255
256 f1 $EJECT
257
258
259
268
261
262
263
264
26.5
266
267
85AA
268
85M 58
95AB 57
269
278
271
272
85AC 52
85AD C686288289
9582 BA9480
9585 883£2992
95B9 8A95
9588
958C
9500
958E
EE
SA
51'
58
958F C3
274
275
276
277
278
279
2S9
281
282
284
285
286
287
288
289
299
291
95C1 57
95C2 52
85C3 C686349200
85Ca BAII8!l9
85Ca 883E2C92
95CF 8A95
95D1 EE
9502 SA
9503 51'
95D4 58
95D5 C3
;****************************************************************
TX_CMfflD_CIIl.
'273
283
85Ca
85Ca 59
,.
,.
,.
;--**--***---**-*--****-***
,*
IX CHfN£I. B COI1I1fII{> ROUTINE - ROUTINE IS CALLED TO
,* TRflNS/tlT A BlfFER. Tf£ BlfFER STARTING AOORESS,
,* TXJ>OINTER_CIIl, ANI) Tf£ BlfFER LENGTH, TX-LEI«lTH_CHB,
ItlIST BE INITIALIZED BY THE CALLING PROORAI1.
BOTH ITEI1S ARE WORD IlARIABLES.
•*
"
*
292
293
294
AX
PUSH
PUSH
DI
IllY
t10Y
t10Y
t10Y
ruT
TX_EII'TUHB, 9 ,CLEAR EI1f'TY FLAG
DX, DATAYORT_CIIl
; SETIA' PORT PO INTER
01, TX..POINTE~_CIIl
,GET TX BUFFER POINTER CHB
",-, [DIl
; GET FIRST CHARACTER TO TX
DX, AL
,OUTPUT IT TO 8274 TO GET IT STARTED
OX
DI
POP
,.;'
POP
POP
RET
; SRYE REGISTERS
OX
AX
,RE1UOINTERJ:lifl. ANI) THE BlfFER LENGTH, TX_LEI«lTHJJiFl.
,* I1UST BE INlTI"'-IZED BY THE CALLING PROGRfIIl
,* BOTH ITEMS ARE WORO IlARIABLES.
*
"
,***._*-*-****----*******-*-*.**-*
IX_comfH)_CHA:
AX
PUSH
PUSH
01
PUSH
295
296
t10Y
IllY
t10Y
297
298
'299
399
381
392
393
394
395
396
397
399
399
318
PUSH
I10V
OUT
POP
POP
POP
RET
I
i
SAYE REGISTERS
OX
TX..EMPTY_CHA, 9 ,ClERR EI'1PTY FLAG
Ox, DATAYORLCHA
,SElU' PORT POINTER
01, TXJ>OINTER-CHA
..; Gff TX BlfFER POINTER CHA
AL [Of)
,GET FIRST CHARACTER TO TX
DX, "',OUTPUT IT TO 8274 TO GET IT STARTED
DX
DI
AX
,RETURN
****************************************************************
,.,"
"
"
RX CM1fH) FOR C/fNoEL B - THE CALLING ROUTINE t1UST
INITIALIZE RX_POINTER_CHl TO POINT AT THE RECEllIE
BUFFER BEFORE CALLING THIS ROUTINE.
H10
•
*
•
*
AFN-020768
AP·134
I'ICS-86 PR:RO ASSEIllI.ER
ASI'NCB
LOC OBJ
LINE
85D6
85D6 58
851)7 52
851)8 C606298289
0500 C706269211989
m BA06!l9
1l5E6 8993
1l5E8 EE
1l5E~ B8Cl
Il5EB EE
Il5EC 51!
05EJ) 58
85EE C3
311
312
313
314
315
316
317
318
319
328
321
322
323
324
325
326
327
328
329
338
331
m
m
334
335
05EF
05EF 58
85F852
85Fl C686358289
85F6 C78632828988
85FC BA8288
95FF 8803
8681 EE
8682
8684
9695
8696
8687
B8Cl
EE
51!
58
C3
336
J
*.**.*lMc***********.........**************..********************
RlLCCMM>-CIII.
PUSH
PUSH
lIlY
I10Y
lIlY
lIlY
AX
,SAVE REGISTERS
DX
OUT
~VJIl, e; CLEAR RX REff)Y FLAG
RlLCOtNLCIIl. 0 ,CLEIR RX COUNTER
DX, COIt1fWJ_~LCte
,POINT AT COftIANI) PORT
fl., 3
,SET UP FOR WR3
DX, AL
,WR3 - 8 8ITSlCfI1, ENABLE I1X
AL OC1H
OX· AL
PCP
PCP
OX
AX
OOT
lIlY
, RETlRN
RET
;******************************************************...,*******
*
RX rotfII(l FOR CIRHL A- THE CALlING ROUTINE MUST
INITIAlIZE RX..POINTER_CHA TO POINT AT THE RECEIVE
BUFFER BEFORE aUING THIS ROUTINE
*
RlLCOI1I1I1I1>-Clfi :
AX
OX
341
342
PUSH
lIlY
lIlY
MOV
lIlY
343
344
345
lIlY
OUT
RlLREADUHfI, 9, CLEAR RX READY FLAG
RX_COUNT _CIfl, 8, CLEAR RX COUNTER
Ox, crMffJ_PORT_CHR
. POINT AT COI1PIANO PORT
fl., 3
,SET UP FOR 1oiR3
DX, AI..
,1.13 - 8 BIT5.II:ffi, ENA8LE RX
fL OC1H
DX, AL
346
347
PCP
PCP
OX
AX
348
•
,***************************************************************.
PIJSH
337
338
339
-*
OUT
,SAYE REGISTEIIS
, RET/JRN
RET
348
349
358 +1 $EJECT
351
352
,j ********"******************************************************
353
i*
*
354
START OF INTERRlIPT SERVICE ROUTINES
355
;*
356
i ******************************************.*********************
357
358
359
,CIftf£l B TRANSIIIT DATA SERVICE ROUTINE
8688 52
868~ 57
868A 58
368
XllTlte: PUSH
361
PUSH
362
8689 E88291
06eE FF862892
363
PUSH
CALL
364
INC
8612
8616
8618
8618
861F
365
369
DEC
JE
lIlY
lIlY
lIlY
378
OUT
FF8E2282
748E
BA8498
8B3E2892
8A85
8621 EE
366
367
368
DX
01
,SIIYE REGISTERS
AX
EOI
'SEND EOI COIt1ANI) TO 8274
TlLPOINTEILCIIl ,POINT TO NEXT CHARACTER
TlUENGTILCIIl ,DEC LENGTH CO/JNTER
XIB
; TEST IF DONE
Ox, DIITfL~T _CJIl
,NOT DONE - GET NEXT CHARACTER
01, TlLP01NTER_CIIl
fl., [ o i l , PUT CHARACTER IN AL
OX, AL
,OUTPUT IT TO 8274.
7-111
AFN-()2()16B
AP-134
ItS-86 IIOCRO IISSEIIllER
fISYI«:B
LOC m.J
Ut£
8622 58
862l5F
8624 51!
8625 CF
11626 BIIII6'88
371
Il629 B828
862B EE
377
862C C686288281
:m
8631 58
379
388
381
864952
864A 57
tl64S 58
864C EBC188
I!64F 883£2482
965l IlAt!488
8656 EC
8657 8885
9659 FF862482
965& FF862682
8661 3CllI)
8663 758E
8665 C686298291
866A BA8698
866D 8893
866F EE
&'78 B8C9
9672 EE
8671 58
8674 51'
9675 5A
9676 CF
9677 52
86;'8 59
8679 E~~
~
.
XIS:
386
387
388
389
3!le
391
m
393
394
395
396
397
398
4IlJ
484
485
486
STRINB: PUSH
PUSH
PUSH
Cfl.L
IIOY
IN
IIOY
IIOY
ruT
PO'
POP
PO'
lRET
RCYINB. PUSH
PUSH
PUSH
CIl.L
,SAVE REGISTERS
OX
01
fIX
,SEND EOI COI9fAIf) TO 8274
EOI
DX, COllfNU'(J!T..CItl
,READ RR8
RL OX
STRTUS..J!S(LCHB, fl.
; PUT RR8 IN STATUS IESSRGE
fl., 1ai
; SE/I) RESET STATUS INT COIIIftI) TO 8274
Dx.fl.
,RESTORE REGISTERS
AX
III
DX
,SAVE REGISTERS
fIX
POP
POP
I)X
4B
JNE
414
415
416
417
418
419
IIOY
IIOY
IN
INC
INC
CI1P
IIOY
IIOY
OOT
..w
RIB.
()X
DI
EOI
•SEND EOI COItIRND TO 8274
01, R)LPOINTER_CHB
; GET RX CHB BlFFER POINTER
DX. DATILPORLCHB
RL f)X
; READ CHARACTER
rDl1 AL
; STORE IN BlFFEI1
RX_POINTER_CHB ,BIJI1P TI£ BUFFER POlNTE~
RX..COtRfLCHB
•BtW THE C(l1NTEl1
fl., CR_~
,TEST IF lAST CHRIIACTER TO BE RECElYEO?
RIB
RX..RERDY.CIIl, 1 ; YES, SET READY FLAG
Ox, COIt1fIND.PORLCHB
,POINT AT COI1tfANI) PORT
fl., 7
· POINT AT Wfl3
OX, AL
,OISRBLE RX .
fl.. 9Cai
!lX. fl.
AX
· E!THEII WAY, RESTORE REGISTERS
DI
ItOY
f10II
421
422
423
424
425
426
427
428
429
430
; RETmI TO F!REGRIXN)
Ox, tnlfHU'(J!T..CHB
,fl.L CIiIIIlCTERS Ifl'fE BEEN SEND
fL28H
; RESET ~ITTER INTERRtPT PE/t)INl
Ox, fl.
TX..£II'TV_CIIl, 1, D!H: - SO SET TX EltPTV Am CHB
,RESTORE REGISTERS
fIX
01
DX
; RETmI TO FOREGRtlJIt)
,CIRf£L B RECElYEO DATA SERVICE RWTlt£
497
48B
489
419
411
412
428
,RESTORE REGISTERS
fIX
01
OX
,CIRf£L B STRTUS CIIHlE SERVICE RruTIt£
m
488
481
402
..w
IIOY
ruT
IIOY
PO'
PO'
PO'
IRET
382
383
384
385
8635 52
86J6 57
863758
Iil638 E8D589
Iil638 BIIII6'88
863£ EC
86JF A22fI82
8642 B818
8644 EE
8645 58
8646 51'
864751!
tl64S CF
PO'
PO'
PO'
IRET
m
ill
374
375
376
8632 51'
8633 51!
8634 CF
5(Jm
OOT
POP
lRET
,RETUIIN TO FOREGPOUND
. CHANNEL B ERROII SEIIVKE
~IJUTINE
~
ERRIHB PUSH
PUSH
CALL
I10V
PX
,SAVE REGISTERS
AX
EO!
,SEN£> EO! COMHfiNl) TO B274
f)x, C\lI9f\N[).PORUHB .
/-'
7-112
AFN.020768
AP-134
.,;s-86 Ift:RO ASSEI'IIllER
A5YNJl
LOC reJ
LItE
867F BiJ81
431
432
433
434
435
436
437
8681
8682
8683
9686
9688
8689
068fI
968B
EE
EC
A22II82
B83Il
EE
58
5A
CF
SQ.RC£
IllY
fL, 1
I)X,fL
; POINT AT RR1
(J.JT
; RBI)
til
!LOX
IllY
IllY
~,fL
!L 3llH
; SEll)
(J.JT
Ox, fL
AX
I)X
438
p(f
p(f
439
lRET
RR1
; SAYE IT IN ERRa! FLffi
RESET ~ COItIfIlI) TO 8274
,RESTlI!E REGISTERS
; RETlRN TO FlI!EGRWID
448
868C 52
9680 57
968E 58
868F E87E80
9692 FF962C82
9696 FF9E2E92
96911 74eE
969C BAeeIl8
969F 883E2C82
96A3 8A95
96A5 EE
86A6 58
96A7 5F
96A8 5A
96A9 CF
96AA BA9280
86AD B928
96AF EE
86B9 C69634l1201
06B5 58
06B6 SF
9687 SA
06B8 CF
441
442
443
,C/ftf£\. A TRANSltIT DATA SERVICE ROUTII£
XlfTINR. PUSH
OX
PUSH
PUSH
01
444
445
446
CfLL
It«:
DEC
JE
IllY
IllY
447
448
449
458
451
452
453
454
455
456
457
458
459
469
461
462
463
464
465
466
467
~y
OUT
p(f
XIA
AX
EOI
; SEND EOI COItIAtf) TO 8274
TX.POINTER.CHA ,POINT TO NEXT CHARACTER
TX.J.ENGTH..CHA ,DEC LOOTH CWNTER
XIA
,TEST IF DONE
OX, DATA.PORLCHA
,NOT 001£ - 6fT NEXT CHARACTER
I) I, TX.POINTER..CHA
AL,[DIJ
; PUT CHARACTER IN fL
Ox, fL
; OUTPUT IT TO 8274
AX
; RESTORE REGISTERS
POP
DI
POP
JRET
I)X
IllY
IllY
OUT
HOI!
POP
POP
POP
IRET
,SAVE REGISTERS
· RETURN TO FlI!EGROIJND
DX, cot1ItfN).PORLCHA
,ALL CHARACTERS HAVE BEEN SEN!)
AL 28H
,RESET TRANSMITTER IIITERRUPT PENI!ING
Ox.. AL
TX_EMPTY _CIf!, 1 ,DONE - SO SET TX EMPTY FLAG CHB
AX
; RESTlI!E REGISTERS
DI
OX
,RETURN TO FOREGROIJNI!
,CHANNEL A STAnJS CHAmE SEIIVICE ROUTINE
468
068952
96BA 57
968B 58
068C E85100_
068F 8A0280
06C2 EC
e6C3 A23682
96C6 8018
06C8 EE
e6C958
86CA SF
96CB SA
9o'..cC CF
06CD 52
06CE 5i'
06CF ~.e
06£>0 E8?f)9a
06D3 883E3802
06Di' BA0099
469
470
471
472
473
474
475
476
4f7
478
479
4B0
481
482
483
484
485
486
48i'
488
489
499
STAlNA
PUSH
PUSH
PUSH
CALL
MaV
IN
IllY
I10V
OUT
POP
POP
POP
lRET
OX
,SAllE REGISTERS
DI
AX
EOI
· SENO EOI ('OttIflND TO 8274
DX, COMlI-ID_PORUHA
AL DX
,READ RRB
STATUS_MSG_CHA, AL
. PUT ~R0 IN STAWS t1ESSAGE
AL, 1SH
· SEND RESET STATUS lIlT COMlI-ID TO 82i"
DX, AL
AX
· RESTORE REGISTERS
DI
DX
. CHANNEL A RECEIIlED DATA
~('JlNA
PUSH
PUSH
PUSH
CALL
MeV
MeV
vii
vi
SE~YI(E
ROUTINE
· SAVE PEGISTEP5
AX
EOI
· SEN[> EOI (OMMAN!' TO 8274
DJ, PLPOIIITER_CHA
•GET PX CHA BUFFEP POIIITER
DX. DATA_PO~'U HA
7-113
AFN-020766
AP-134
11C5-B6 I1ACRO ASSEIIBLER
AS'r'NCB
LOC OBJ
LINE
IlbDA EC
49-1
492
493
494
495
496
497
498
060B 88e5
8600 FF963892
86Ei FF963282
96E5 3C8I)
86£7 75eE
86E9 C686358281
96EE BA82ee
86F1 8803
B6F3 EE
86F4 B8C8
86F6 EE
B6F7
86F8
86F9
86FA
58
5F
SA
CF
86FB 52
86FC 58
86FD E81880
8789 BfI82ge
0783 ee81
8785 EE
8786 EC
8m A23782
878R 8830
978C EE
9700 58
079E SA
878F CF
0711 52
0712 BA8200
0715 8038
'9717 EE
8718 SA
8719 58
ellA C3
IN
I'IOV
INC
INC
581
582
583
5e4
5e5
RIA.
587
588
5e9
518
511
512
513
514
515
516
517
518
519
529
526
527
S28
529
538
531
532
533
534
535
536
537
53B
539
flL, CR_~
RIA
RX..REAO'UIIA, 1 ; YES, SET READY FLAG
DX, COItIIfN)..PORLCHA
; POINT AT COIt\AI() PORT
fl., 3
; POINT AT WR3
ox, fl.
fl., 0C8H
; OISfIBLE RX
DX, AI..
AX
,EITHER NAY, RESTORE REGISTERS
01
POP
POP
DX
,RETURN TO FOREGIlOUI«>
; CIftINEL A ERro< SERVICE ROUTINE
ERRINA: PUSH
PUSH
CALL
ItlV
IllY
OUT
IN
I10V
lIllY
OUT
POP
POP
lRET
521'
522
523
524
; READ CHARACTER
,STORE IN BUFFER
; EIlW TIE BUFFER POINTER
; Bl.!'IP TI£ COUNTER
; TEST IF LAST CHARACTER TO BE RECEIYED?
mE
POP
IRET
586
fl., OX
[On fl.
RX..POINTER..CIfI
RX_COUNUHA
CHI'
ItlV
ItlV
I10V
OUT
I10V
OUT
499
588
525
9719 58
SOURCE
ox
,SAllE REGISTERS
AX
EOI
; SEND EOI COItIfH) TO 8274
ox, COItfKl..PORLCIfI
fl., 1
; POINT AT RR1
OX, fI.
,READ RR1
/L DX
ERRftUISILCIfI, fI.
; SAllE IT IN ERROR FLAG
fl., 3IlH
; SEND RESET ERro< COIt\AI() TO 8274
ox, fl.
AX
,RESTORE REGISTERS
ox
,RETlRN TO FOREilROlN)
,EIIHf"-INTERRlfT RruTiNE - SENDS EOI mtfIII) TO 8274.
; THIS CIJltlflll) I'lJST fl.IoIAYS TO ISSU:D ON CIfH£L A.
EOI:
PUSH
PUSH
ItlV
I'IlV
OUT
POP
POP
AX
,SAllE REGISTERS
OX
ox, CO/'II'IAND..PORLCHA
fl., 3IlH
DX, fl.
; ALIoIAYS FOR C1fU£L A !"
ox
AX
RET
,END OF CODE ROUTINE
ABC
ENDS
END
ASSEIIBLYCOIflETE, NO ERRORS FIJ.H)
7-114
AFN'()2076B
intJ
AP-134
REFERENCES
3. Telecommunications and the Computer, J. Martin,
Prentice-Hall, New Jersey, 1976.
1. 8274 Multiprotocol Serial Controller (MPSC) Data
Sheet, Intel Corporation, California, 1980.
4. Technical Aspects of Data Communications, J.
McNamara, DEC Press, Massachusetts, 1977.
2. Basics of Data Communication, Electronics Book
Series, McGraw-Hill, New York, 1976.
5. Miscellaneous Data Communications Standards
-EIA RS-232-C, EIA RS-422, EIA RS-423, EIA
Standard Sales, Washington, D.C.
7-115
AFN·02076B
,
APPLICATION
NOTE,
'
AP-145
June 1982
@ INTEL CORPORATION, 1982
7-116
ORDER NUMBER: 210403-001
AP·145
INTRODUCTION:
The INTEL 8274 is a Multi-Protocol Serial Controller,
capable of handling both asynchronous and synchronous
communication protocols. Its programmable features allow it to be configured in various operating modes, providing optimization to given data communication
application.
This application note describes the features of the MPSC
in Synchronous Communication applications only. It is
strongly recommended that the reader read the 8274 Oata
Sheet and Application Note AP134 "Asynchronous Communication with the 8274 Multi-Protocol Serial Control-,
ler" before reading this Application Note. This
Application note assumes that the reader is familiar with
the basic structure of the MPSC, in terms of pin descripOPENING
FLAG
BYTE
ADDRESS·
FIELD(A)
tion, Read/Write registers and asynchronous communication with the 8274. Appendix A contains the software
listings of the Application Example and Appendix B
shows the MPSC Read/Write Registers for quick
reference.
The first section of this application note presents an overview of the various sysnchronous protocols. The second
section discusses the block diagram description of the
MPSC. This is followed by the description of MPSC interrupt structure and mode of operation in the third and
fourth sections. The fifth section describes a hardware/
software example, using the INTEL single board computer iSBC88/45 as the hardware vehicle. The sixth section
consists of some specialized applications of the MPSC. Finally, in section seven, some useful programming hints are
summarized.
CONTROL··
FlELD(C)
DATA
FIELD
FRAME
CHECK
' SEQUENCE
CLOSING
FLAG
BYTE
Figure 1. HDLC/SDLC Frame Format
• Extendable to 2 or More Bytes
•• Extendable to 2 Bytes
SYNCHRONOUS PROTOCOL OVERVIEW
ZERO BIT INSERTION
This section presents an overview of various synchronous
protocols. The cOntents of this section are fairly tutorial
and may be skipped by the more knowledgeable reader.
The flag has a unique binary bit pattern: 7E HEX. To
eliminate the possibility of the data field containing a 7E
HEX pattern, 'a bit stuffmg technique called Zero Bit insertion is used. This technique specifies that during transmission, a binary 0 be inserted by the transmitter after any
succession of five contiguous binary 1'so This will ensure
that no pattern of 0 1 I 1 I 1 lOis ever transmitted between flags. On the receiving side, after receiving the flag,
the receiver hardware automatically deletes any 0 following fIVe consecutive 1's.The 8274 performs zero bit insertion and deletion automatically in the SOLC/HOLC
mode. The zero-bit stutTmg ensures periodic transitions in
the data stream. These transitions are necessary for a
phase lock circuit, which may be used at the receiver end
to generate a receive clock which is in phase to the received data. The inserted and deleted O's are not included
in the CRC checking. The address field is used to address
a given secondary station. The control field contains the
link-level control information which includes implied acknowledgement, supervisory commands and' responses,
etc. A more detailed discussion of higher level protocol
functions is beyond the scope of this application note. Interested readers may refer to the references at the end of
'this application note.
Bit Oriented Protocols OVerview
Bit oriented protocols have been defmed to manage the
flow of information on data communication links. One of
the most widely known 'protocol is the one defined by the
International Standards Organization: HOLC (High
Level Oata Link Control). The American Standard Ass0ciations' protocol, ADCCP is similar to HOLC. CCITT
Recommendation X.25 layer 2 is also an acceptable version of HOLC. Finally, IBM's SOLC (Synchoronous
Data Link Control) is also a subset of the HOLC.
In this section, we will concentrate most of our discussion
on HOLC. Figure I shows a basic HOLC frame format.
A frame consists of five basic fields: Flag, Address, Control, Oata and Error Oetection. A frame is bounded by
flags - opening and closing flags. An address field is 8 bits
wide, extendable to 2 or more bytes. The control field is
also 8 bits wide, extendable to two ~ytes. The data field or
information field may be any number of bits. The data
. field may or may not be on an 8 bit boundary. A powerful
error detection code called Frame Check Sequence contains the calculated CRC (Cycle Redundancy Code) for
a!l the bits between the flags.
The data field may be of any length and content in
HOLC. Note that SOLC specifies that data field be a
multiple of bytes only. In data communications, it is gen7-117
Ap-145
erally desirable to tra\lsmit data which may be of any content. This requires that data field should· not contain
characters which are defined to assist the transmission
protocol (like opening flag 7EH in HOLC/SOLC communications). This property is referred to as "data transparency". In HOLC/SOLC, this code transparency is
made possible by Zero Bit Insertion discussed earlier and
the bit orientated nature of the protocol.
The last field is the FCS (Frame Check Sequence). The
FCS uses the error detecting techniques called Cyclic Redundancy Check. In SOLC/HOLC, the CCITT-CRC
must be used.
NON·RETURN TO ZERO INVERTED (NRZI)
NRZI is a method of clock and data encoding that is well
suited to the HOLC protocol. It allows HOLC protocols to
be· used with low cost asynchronous modems. NRZI coding is done at the transmitter to enable clock recovery
from the data at the receiver terminal by using standard
digital phase locked loop techniques. NRZI coding specifies that the signal condition does not change for transmitting ai, while a causes a change of state. NRZi coding
ensures that an active data line will have transition at least
every 5-bit times (recall Zero Bit Insertion), while contiguous O's will cause a change of state. Thus, ZBI and NRZI
encoding makes it possible for a phase lock circuit at the
receiver end to derive a receive clock (from received data)
which is synchronized to the received data and at the same
time ensure data transparency.
°
Byte Synchronous Communication
As the name implies, Byte Synchronous Communication
is a synchronous communication protocol which means
that the transmitting station is synchronized to the receiving station through the recognition of a special sync character or characters. Two examples of Byte Synchronous
protocol are the IBM Bisync and Monosync. Bisync has
two starting sync characters per message while monosync
has only one sync character. For the sake of abrevity, we
HEADER
Figure 2.
will only discuss Bisync here. All the discussiQn is valiMOI;
Monosync also. Any exceptions will be noted. Figure 2
shows a typical Bisync message format.
The Bisync protocQl is defined for half duplex communication between two or more stations over point to point or
multipoint communication lines. ,Special characters controllink access, transmission of data and termination of
transmission operations for the system. A'detailed discussion of these special control characters !SYN, ENQ,
STX, ITB, ETa, ETX, OLE, SOH, ACKO, ACKI,
WACK, NAK and EaT, etc) is beyond the scope of this
Application Note. Readers interested in more detailed
discussion are directed to the references listed at the end of
I
this Application Note.
As shown in Figure 2, each message is preceded by two
sync characters. Since the sync characters are defined at
the beginning of the message only, the transmitter must
insert fill characters (sync) in order to maintain synchronization with the receiver when no data is being
transmitted.
TRANSPARENT TRANSMISSION .
Bisync protocol requires special control characters to
maintain the communication link over the line. If the data
is EBCOIC encoded, then transparency is ensured by the
fact that the data field will not contain any of the bisync
control characters. However, if datatloes not conform to
standard character encoding techniques, transparency in
bisync is achieved by inserting a special character OLE
(Oata Link Escape) before and after a string of characters
which are to be transmitted transparently. This en~ures
that any data charaters which match any of the special
characters are not confused for special characters. An example of a transparent block is shown in Figure 3.
In a transparent mode, it is required thact theCRC(BCC)
is not performed on special characters. Later on, we will
show how the 8274 can be used to achieve transparent
transmission in Bisync mode.
STXTEXT
ETXOR ETB
Bisync Message Format
TRANSPARENT TRANSMISSION
return to normal mode
Enter transparent mode
Figure 3.
Bisync Transparent Format
7-118 .
AFN-02213A
inter
AP-145
BLOCK DIAGRAM
CPU Interface
This section discusses the block diagram view of the 8274.
The CPU interface and serial interface is discussed separately. This will be followed by a hardware example in the
fifth section, which will s.\1ow how to interface the 8274
with the Intel CPU 8088. The 8274 block diagram is
shown in Figure 4.
The CPU interface to the system interface logic block utilizes the AO, AI, CS, RD and WR inputs to communicate
with the internal registers of the 8274. Figure 5 shows the
address of the internal registers. The DMA interface is
achieved by utilizing DMA request lines for each channel:
TxDRQA> TxDRQB' RxDRQA> RxDRQB' Note that
r -CHANNEL
--------,
A
TxDA
CHANNEL A
TRANSMITTER
DBo-7'
___- ' - - " I
TxCA
CH~~~ A
REGISTERS
DCDA
CLK
RESET
RDYB/TxDRQA
I
!1
eTSA
CHANNEL A
CONTROL
LOGIC
RTSA
SYNDETA
RDYA/RxDRQA
!lID 1/'-....L---1
i!
i!i
IPO/TxDRQa
IP1/RxDRQB
INT
I. .
SYSTEM
INTERFACE
CONTROL
LOGIC
DTRA
CHANNEL A
READ
REGISTERS
F'~~======~
I
CHANNELA
RECEIVER
INTA
AO
Al
TxDB
•f
I
TxCB
DCDB
CTSB
CHANNELB
{ SYNDETB
RTSB
SYSTEM INTERFACE
ImtB
RxCB
RxDB
NETWORK INTERFACE '
Figure 4.
cs
A1 AO
0
0
0
1
°
0
0
1
8274 Block Diagram
Read Op~ration
Write Operation
0
0
CHA DATA READ
CHA STATUS REGISTER
(RRO,RRl)
CHA DATA WRITE
CHA COMMAND/PARAMETER
(WRO--WR7)
I
I
I
CHB DATA READ
CHB STATUS REGISTER
(RRO,RRl,RR2)
CHB DATA WRITE
CHB COMMAND/PARAMETER
(WRO--WR7)
x
X
HIGHZ
HIGHZ
Figure 5. Bus Interface
7-119
AFN.02213A
intJ
AP-145
TxDRQBand RxDRQBbecomes IPO and IPI respectively in non-DMA mode. IPI is the Interrupt Priority Input
and IPO is the Interrrupt Priority Output. These two pins
can be used for connecting mUltiple MPSCs in a daisy
chain. If the Wait Mode is programmed, then TxRDQA
and RxDRQ A pins become RDYBand RDY A pins. These
pins can be wire-or'ed and are usually hooked up _to the
CPU RDY line to synchronize the CPU for block transfers. The INT pin is activated whenever the MPSC requires CPU attention. The INTA may be used to utilize
the powerful vectored mode feature of the 8274. Detailed
discussion on these subjects will be done later in this Application Note. The Reset pin may be used for hardware
reset while the clock is required to click the internal logic
on the MPSC.
Serial Interface
On the serial side, there are,two completely independent
channels: Channel A and Channel B. Each channel consists of a transmitter block, receiver block and a set of
read/write registers which are used to initialize the device. In addition, a control logic block provides the modem
interface pins. Channel B serial interface logic is a mirror
image of Channel A serial interface logic, except for one
exception: there is only one pin for RTS Band SYNDETB'
At a given time, this pin is either R1;SB or SYND~TB'
This mode is programmable through one of the internal
registers on the MPSC:
, Transmit And Receive Data Path
Figure 6 shows a block diagram for transmit and receive
data path. Without describing each block on the diagram,
a brief discussion of the block diagram will be presented
here.
TRANSMIT DATA PATH
The transmit data is transferred to the twenty-bit serial
shift register. The twenty-bits are needed to store two
bytes of sync characters in bisync mode. The last three bits
of the shift register are used to indicate to the internal controllogic that the current data byte has been shifted out of
the shift register. The transmit data in the transmit shift
register is shifted out through a two bit delay onto the
TxData line. This two bit delay is used to synchronize the
internal shift clock with the external transmit clock. The
data in the shift register is also presented to zero bit insertion logic which inserts a zero after sensing five contiguous
ones in the data stream. In pa~allel to all this activity, the
CRC-generator is computing CRC on the transmitted
data and appends the frame with CRC bytes at the end of
the data transmission.
CPU I/O
TxDA
TxCA
1
Figure 6.
Transmit and Receive Data Path
7-120
AFN-02213A
inter
AP-145
RECEIVE DATA PATH
top of the FIFO at the chip clock rate (not the receiver
clock). It takes three chip clock/periods to transfer data
from the serial shift register to the top of the FIFO. The
three bit deep Receive Error FIFO shifts any error condition which may have occured during a frame reception.
While all this is happening, the eRe checker is checking
the eRe on the incoming data. The computed eRe is
checked with the eRe bytes attached to the incoming
frame and an error .generated under a no-check condition.
Note that the bisync data is presented to the eRe checker
with an 8-bit delay. This is necessary to achieve transparency in bisync mode as will be shown later in this Application Note.
The received data is passed through a one-bit delay before
it is presented for flag/sync comparison. In bisync mode,
after the synchronization is achieved, the incoming data
bypasses the sync register and enters directly into the
three bit buffer on its way to receive shift register. In
SDLe mode, the incoming data always passes through the
sync register where data pattern is continously monitored
for contiguous ones for zero deletion logic. The data then
enters the three bit buffer and the receive shift register.
From the receive shift register, the data is transferred to
the three byte deep FIFO. The data is transferred to the
FIRST DATA CHARACTER
FIRST NON·SYNC
CHARACTER (SYNC MODES)
INTERRUPT
ON FIRST RECEIVE
CHARACTER
VALID ADDRESS
BYTE (SDLC)
INTERRUPT ON
ALL RECEIVE
CHARACTERS
PARITY ERROR
RX OVER-RUN ERROR
FRAMING ERROR
SPECIAL
RECEIVE
CONDITION
INTERRUPT
END OF FRAME
(SOLCONLY)
DCD TRANSITION
MPSC
INTERRUPTS
CTS TRANSITION
EXTERNAL
STATUS
INTERRUPT
SYNC TRANSITION
TX UNDER-RUN/EOM
BREAK/ABORT DETECT
TRANSMIT
INTERRUPT
TX BUFFER EMPTY
Figure 7.
MP$C Interrupt Structure
7-121
AFN·02213A
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AP-14S
MULTI-PROTOCOL SERIAL CONTROLLER
(MPSC) INTERRUPT STRUCTURE
The MPSC offers a very powerful interrupt structure,
which helps in responding to an interrupt condition very
quickly. There are multiple sources of interrupts within
the MPSC. However, the MPSC resolves the priority between various interrupting sources and interrupts the
CPU for service through the interrupt line. This section
presents a comprehensive discussion on all the 8274 interrupts and the priority resolution between these interrupts.
All the sources of interrupts on the 8274 can be grouped
into three distinct catagories. (See Figure 7)
I. Receive Interrupts
2. Transmit Interrupts
3. External/Status Interrupts.
An internal interrupt priority structure sets the priority
between the interrupts. There are two programmable options available on the MPSC. The priority is set by
WR2A, 02. (Figure 8)
PRIORITY
.
~R2A:02 Highest
Lowest
0
RxA
TxA RxB
TxB EXTA EXTB
I
RxA
TxA RxB
TxB EXTA EXTB
Figure 8.
Interrupt Priority
Receive Interrupt
All receive interrupts may be catagorized into two distinct
groups: Receive Interrupt on Receive Character and Special Receive Condition Interrupts.
RECEIVE INTERRUPT ON RECEIVE CHARACTER
A receive interrupt is generated when a character is received by the MPSC. However, as will be discussed later,
this is a programmable feature on the MPSC . A Rx character available interrupt is generated by the MPSC after
the receive character has been assembled by the MPSC. It
may be noted that in OMA transfer mode too, a receive
interrupt on the first receive character should be programmed. In SOLC mode, if address search mode has
been programmed, this interrupt will be generated only
after a valid address match has occured. In bisync mode,
this interrupt is generated on receipt of a character after
at least two valid sync characters. In inonosync mode, a
character followed by at least a single valid sync character
will generate this interrupt. An interrupt on first receive
character signifies the beginning of a valid frame. An end
of the frame is characterized by an "End of Frame" Interrupt (RRI: 07).* This bit (RRl:07) is set in
SOLC/HOLC mode only and signifies that a valid ending
flag (7EH) hlis been received. This bit· gets reset· either by
an "Error Reset" command (WRO: 050403 = 110) or
upon reception of the first character of the next frame. In
multiframe reception, on receiving the interrupt at the
"End of Frame" the CPU may issue an Error Resllt command which will reset the interrupt. In OMA mode, the
interrupt on first receive character is accompanied by a
RxORQ (Receiver OMA request) on the appropriate
channel. At the end of the frame, an End of Frame interrupt is generated. The CPU may use this interrupt to jump
into a routine which may redefine the receive buffer for
the next incoming frame.
*RRI:07 is bit 07 in Read Register 1.
SPECIAL RECEIVE CONDITION INTERRUPTS
So far, we have assumed that the reception is error free. ,
But this is not a 'typical' case in most real life applications.
Any error condition during a frame reception generates
yet another interrupt - special receive condition interrupt. There are four different error conditions which can
generate this interrupt.
(i) Parity error
(ii) Receive Overrun error
(iii) Framing error
(iv) End of Frame
(i) Parity error: Parity error is encountered in asynchronous (start-stop bits) and in bisync/monosync protocols.
Both odd or even parity can be programmed. A parity error in a received byte will generate a special receive condition interrupt and sets bit 4 in RRI.
(ii) Receive Overrun error: If the CPU or the DMA controller (in OMA mode) fails to read a received character
within three byte times after the received character interrupt (or OMA request) was generated, the receiver buffer
will overflow and this wi:ll generate a special receive condition interrupt and sets bit 5 in RRI.
(iii) Framing error: In asynchronous mode, a framing error will generate a special receive interrupt and set bit 06
in RRI. This bit is not latched and is updated on the next
received character.
(iv) End of frame: This interrupt is enj:ountered in
SOLC/HOLC mode only. When the MPSC receives the
closing flag, it generates the special receive condition interrupt and sets bit 07 in RRI.
All the special receive condition interrupts may be reset by
issuing an Error Reset Command.
CRC Error: In SOLC/HOLC and synchronous modes, a
CRC error is indicated by bit 06 in RRI. When used to
check CRC error, this bit is' normally set until a correct
CRC match is obtained which resets this bit. After receiving a frame, the CPU must read this bit (RRI :0.6) to determine if a valid CRC check had occured. It may be
noted that a CRC error does not generate an interrupt.
7-122
AFNo02213A
inter
AP-145
It may be also be pointed out that in SDLC/HDLC mode,
receive DMA requests are disabled by a special receive
condition and can only be re-enabled by issuing an Error
Reset Command.
Transmit Interrupt
A transmit buffer empty generates a transmit interrupt.
This has been discussed earlier under "Transmit in Interrupt Mode" and it would be sufficient to note here that a
transmit buffer empty interrupt is generated only when
the transmit bJlffer gets empty - assuming it had a data
character loaded into it earlier. This is why on starting a
frame transmission, the first data character is loaded by
the CPU without a transmit empty interrupt (or DMA request in DMA mode). After this character is loaded into
the serial shift register, the buffer becomes empty, and an
interrupt (or DMA request) is generated. This interrupt is
reset by a "Reset Tx Interrupt/DMA Pending" command
(WRO: D5 D4 D3 = 101).
External/Status Interrupt
Continuing our discussion on transmit interrupt, if the
transmit buffer is empty and the transmit serial shift register also becomes empty (due to the data character shifted out of the MPSC), a transmit under-run interrupt will
be generated. This interrupt may be reset by "Reset/External Status Interrupt" command (WRO: D5 D4 D3 =
101).
SDLC Mode
In SDLC mode, the SYNDET pin is an output. Status
register RRl, D4 contains the state of the SYNDET pin.
The Enter Hunt Mode initially sets this bit in RO. An
opening flag in a received SDLC frame resets this bit and
generates an external status interrupt. Every time the receiver is enabled or the Enter Hunt Code Command is issued, an external statl.\s interrupt will be generated on
receiving a valid flag followed by a valid address/data
character. This interrupt may be reset by the "Reset External Status Interrupt" command.
External SYNC Mode
The MPSC can be programmed into External Sync Mode
by setting WR4, D5 D4 = 11. The SYNDET pin is an input in this case and must be held high until an external
character synchronization is established. However, the
External Sync mode is enabled by the Enter Hunt Mode
control bit (WR3: D4). A high at the SYNDET pin holds
the sync/Hunt bit (RRO,D4) in the reset state. When external synchronization is established, SYNDET must be
driven low on second rising edge of RxC after the rising
edge of RxC on which the last bit of sync character was
received. This high to low transition sets the Sync/Hunt
bit and generates an external status interrupt, which must
be reset by the Reset External/Status command. If the
SYNDET input goes high again, another External Status
Interrupt is generated, which may be cleared by Reset External Status command.
The External Status Interrupt can be caused by five different conditions:
(i) DCD Transition
(ii) CTS Transition
(iii) Sync/Hunt Transition
(iv) Tx under-run/EOM condition
(v) Break/ Abort Detection.
Mono-Sync/Bisync Mode
SYNDET pin acts as an output in this case. The Enter
Hunt Mode sets the Sync/Hunt bit in RO. Sync/Hunt bit
is reset when the MPSC achieves character sysnchronization. This high to low transition will generate an external
status interrupt. The SYNDET pin goes active every time
a sync pattern is detected in the data stream. Once again,
the external status interrupt may be reset by the Reset External Status command.
DCD,CTS TRANSITION
Any transition on these inputs on the serial interface will
generate an External/Status interrupt and set the corresponding bits in status register RRO. This interrupt will
also be generated in DMA as well as in Wait Mode. In order to find out the state of the CTS or DCD pins before the
transition had occurred, RRO must be read before issuing
a Reset External/Status Command through WRO. A read
of RRO after the Reset External/Status Command will
give the condition of CTS or DCD pins after the transition
had occurred. Note that bit D5 in RRO gives the complement of the state of CTS pin while D3 in RRO reflects the
actual state of the DCD pin.
SYNC HUNT TRANSITION
Any transition on the SYNDET input generates an interrupt. However, sync input has different functions in different modes and we shall discuss them individually.
Tx UNDER-RUN/END OF MESSAGE (EOM)
The transmitter logic includes a transmit buffer and a
transmit serial shift register. The CPU loads the character
into the transmit buffer which is transferred into the
transmit shift register to be shifted out of the MPSC. If
the transmit buffer gets empty, a transmit buffer empty
interrupt is generated (as discussed earlier). However, if
the transmit buffer gets empty and the serial shift register
gets empty, a transmit under-run condition will be created. This generates an External Status Interrupt and the
interrupt can be cleared by the Res.et External Status
command. The status register RRO, D6 bit is set when the
transmitter under-runs. This bit plays an important role in
controlling a transmit operation, as will be discussed later
in this application note.
7-123
AFN-02213A
AP-145
BREAK! ABORT DETECTION,
In asynchronous mode, bit 07 in RRO is set when a break
condition is detected on the receive data line. This also
generates an External/Status interrupt which may be reset by issuing a Reset External/Status Interrupt command to the MPSC. Bit 07 in RRO is reset when the break
condition is terminated on the receive data line and this
causes another External/Status interrupt to be generated.
Again, a Reset External/Status Interrupt command will
reset this interrupt and will enable the break detection logic to look for the next break sequence.
In SOLC Receive Mode, an Abort sequence (seven or
more I's) detection on the receive data line will generate
an External/Status interrupt and set RRO,07. A Reset
External/Status command will clear this interrupt. However, a termination of the Abort sequence will generate
another interrupt and set RRO, 07 again. Once again, it
may be cleared by issuing Reset External/Status
Command.
'
This concludes our discussion on External Status
Interrupts.
Interrupt Priority Resolution
The internal.interrupt priority between various interrupt
sources is resolved by an internal prority logic circuit, a€cording to the priority set in WR2A. We will now discuss
the interrupt timings during the priority resolution. Figures 9 and 10 show the timing diagrams for veCtored and
non-vectored modes.
VECTORED MODE
We shall assume that the MPSC accepted an internalrequest for an interrupt by activating the internal INT signal. This leads to generating an external interrupt signal
on the INT pin. The CPU responds with an interrupt acknowledge (INTA) sequence. The leading edge of the first
INTA pulse sets an internal interrupt acknowledge signal
(we will call it Internal INTA). Internal INTA is reset by
the high going edge of the third INTA pulse. The MPSC
will not accept any internal requests for an interrupt during the period when Internal INTA is active (high). The
MPSC resolves the priority d\lring various existing internal interrupt requests during the Interrupt Request Priority Resolve Time, which is defined as the time between the
leading edge of the first INTA and the leading edge of the
second INTA from the CPU. Once the internal priorities
have been resolved, an internal Interrupt-in-service Latch
is set. The external INT is also deactivated when the Interrupt-in-Service Latch is set.
The lower priority interrupt requests are not accepted internally until an EO! (WRO: 05 04 03 = III) command
is issued by the CPU. The EO! command enables the lower priority interrupts. However, a higher priority interrupt
'N0
INTERNAL
ACCEPTED
EXTERNAL
INT
IPI
--I~
\ ' - -_ _ _ _ _ _
\
1
\
INTA
INTERNAL
INTA
I
=::-_________N_O_IN_TE_\...JN:r.L{INTERRUPTS ACCEPTED
-:
INT·IN·SERVICE
..y
(INTERNAL LATCH)
EOI COMMAND
------------~~--------------------------~
Figure'9.
8274 in 8085 Vectored Mode Priority Resolution Time
7-124
AFN·02213A
AP-145
INTERNAL INT
ACCEPTED,
EXTERNAL INT - - - . . . . ,
\
\
\
\
POINTER 2
SPECIFIED
INT-IN-SERVICE._ _ _ _ _ _ _ _ _ _ _ _.....
(INTERNAL LATCH)
E~COMMAND---------------------~T--~
Figure 10. 8274 NC)n Vectored Mode Priority Resolve Time
request will still be accepted (except during the period
when internal INTA is active) even though the Internalin-Service Latch is set. This higher priority request will
generate another external INT and will have to be handled by the CPU according to how the CPU is set up. If the
CPU is set up to respond to this interrupt, a new INTA
cycle will be repeated as discussed earlier. It may also be
noted that a transmitter buffer empty and receive character available interrupts are cleared by loading a character
into the MPSC and by reading the' character received by
the MPSC respectively_
must read status register RR2 to find out the cause of the
interrupt_ In order to do sO, first a pointer to status register
RR2 is specified and then the status read from RR2. It
may be noted here that after specifying the pointer, the
CPU must read status register RR2 otherwise, no new interrupt requests will be accepted internally.
Figure 10 shows the timing of interrupt sequence in nonvectored mode. The explanation for non-vectored ill similar to the vector mode, except for the following exceptions.
Just like the vectored mode, no lower internal priority requests are accepted until an EOI command is issued by the
CPU. A higher priority request can still i~terrupt the
CPU (except during the priority request inhibit time)_ It is
important to note here that if the CPU does not perform a
read operation after specifying the pointer 2 for Channel
B, the interrupt request accepted before the pointer 2 was
activated will remain valid and no other request (high or
low priority) will be accepted internally. In order to complete a correct priority resolution, it is advised that a read
operation be done after specifying the pointer 2B.
- No internal priority requests are accepted during the
time when pointer 2 for Channel B is specified.
IPI and IPO
NON-VECTORED MODE
- The interrupt request priority resolution time is ·the
time between the leading edge of pointer 2 and leading
edge of RQ active. It may be pointed out that in non-vectored mode, it is assumed that the status affects vector
mode is used.to expedite interrupt response.
On getting an interrupt in non-vectored mode, the CPU
So far, we have ignored the IPI and IPO signals shown in
Figures 9 and 10. We may recall that IPI is the InterruptPriority-Input to the MPSC. In conjunction with the lPO
(Interrupt Priority Output), it is used to daisy chain multiple MPSC's. MPSC daisy chaining will be discussed in
detail later in this application note_
7-125
AFN-02213A
AP-145
EOI Command
The EOI command as explained earlier, enables the lower
priority interrupts by resetting the internal In-ServiceLatch, which consequently resets the IPO output to a low
state. See Figures 9 and 10 for details. Note that before
issuing any EOI co~mand, the internal interrupting
source must be satisfied otherwise, same source will interrupt again. The Internal Interrupt i~ the signal which gets
reset when the internal interrupting source is satisfied (see
Figure 9).
This concludes our discussion on the MPSC Interrupt
Structure.
MULTI-PROTOCOL SERIAL CONTROLLER
(MPSC) MODES OF OPERATION
The MPSC provides two fully independent channels that
may be configured in various modes of operations. Each
channel can be configured into full duplex mode and may
operate in a mode or protocol different from the other
channel. This feature will be very efficient in an application which requires two data link channels operating in
different protocols and possibly at different data rates.
This section presents a detailed discussion on all the 8274
modes and shows how to configure it into these modes.
Interrupt Driven Mode
In the interrupt mode, all the transmitter and receiver operations are reported to the processor through interrupts.
Interrupts are generated by the. MPSC whenever it requires service. In the following discusson, we will discuss
how to transmit and receive in interrupt driven mode.
TRANSMIT IN INTERRUPT MODE
The MPSC can be configured into interrupt mode by appropriately setting the bits in WR2 A (Write Register 2,
Channel A). Figure 11 shows the modes of operation.
WR2A
D1
DO
0
0
0
I
1
1
0
Figure 11.
1
MODE
CH A and CH B in Int,errupt Mode
CH A in DMA and CH B in Interrupt
Mode
CH A and CH B in DMA Mode
Illegal
MPSC Mode Selection for Channel A
and Channel B.
first data character must be loaded from the CPU; in all
cases. (DMA Mode too, as you wiil notice later in this application note). Note that in SDLC mode, this first data
character may be the address of the station addressed by
the MPSC. The transmit buffer consists of a transmit
buffer and a serial shift register. When the character is
transferred from the buffer into the serial shift register, an
interrupt due to transmit buffer empty is generated. The
CPU has one byte time to service this interrupt and load
another character into the transmitter buffer. The MPSC
will generate an intei'rupt due to transmit buffer underrun condition if the CPU does not service the Transmit
Buffer Empty Interrupt within one byte time.
This process will continue until the CPU is out of any more
. data characters to be sent. At this point, the CPU does not
respond to the interrupt with a character but simply issues a
Reset Tx INT /DMA pending command (WRO: D5 D4 D3
== 10 I). The MPSC will ultimately under-run, which simply means that both the transmit buffer and transmit shift
registers are empty. At this point, flag character (7EH) or
CRC byte is loaded into the transmit shift register. This sets
the transmit under-run bit in RRO and generates "Transmit
Under-runjEOM" interrupt (RRO:D6= 1).
You will recall that an SDLC frame has two CRC bytes
after the data field. 8274 generates the CRC on all the
data that is loaded from the CPU. During initialization,
'there is a choice of selecting a CRC-16 or CCITT-CRC
(WR5: D2). In SDLCjHDLC operation, CCITT-CRC
must be selected. We will now see how the CRC gets inserted at the end of the data field. Here we have a choice of
having the CRC attached to the data field or sending the
frame without the CRC bytes. During transmission, a
"Reset Tx Under-runjEOM Latch" cQmmand (WRO:
D7 D6 '7' 11) will ensure that at the end of the frame when
the transmitter underruns, CRC bytes will be automatically inserted at the end of the data field. If the "Reset Tx
Un.der-run/EOM Latch" command was not issued during
the transmission of data characters, no CRC would be inserted and the MP,SC will transmit flags (7EH) instead.
However, in case of CRC transmission, the CRC transmission sets the Tx Under-run/EOM bit and generates a
Transmitter Under-run/EOM Interrupt as discussed earlier. This will have to be reset il) the next frame to ensure
CRC insertion in the next frame. It ,is recommended that
Tx Under-run/EOM latch be reset very early in the transmission mode, preferably after loading the first character.
It may be noted here that Tx Under-runjEOM latch cannot be reset if there is no data in the transmit buffer. This
means that atleast one character has to be loaded into the
MPSC before a "Reset Transmit Under-run/EOM
Latch" command will be accepted by the MPSC.
When the transmitter is under-run, an interrupt is generated. This interrupt is .generated at the beginning of the
CRC transmission, thus giving the user enough time
(minimum 22 transmit clock cycles) to issue an Abort
We will limit our discussion to SDLC transmit and receive
only. However, exceptions for pther synchronous protocols
will be pointed out. To initiate a frame transmission, the
7-126
AFN·02213A
inter
AP-145
command .(WRO: D5 D4 D3 = 0 0 1) in case if the transmitted data had an error. The Abort Command will ensure that the MPSC transmits at least eight l's but less
than fourteen 1's before the line reverts to continuous
flags. The receiver will scratch this frame because of bad
CRC.
Transmitter Disabled during
1. Data Transmission
2. eRe Transmission
However, assuming the transmission was good (no Abort
Command issued), after the CRC bytes have been transmitted; closing flag (7EH) is loaded into the transmit
buffer. When the flag (7EH) byte is transferred to the serial shift register, a transmit buffer empty interrupt is generated. If another frame has to be transmitted, a new data
character has to be loaded into the transmit buffer and the
complete transmit sequence repeated. If no more ftames
are to be transmitted, a "Reset Transmit INT /DMA
Pending" command (WRO: D5 D4 D3 = 101) will reset
the transmit buffer empty interrrupt.
3. Immediately after issuing
ABORT command.
Figure 12.
Tx Data will send idle
characters· which will
be zero inserted.
16 bit transmission,
corresponding to 16
bits of eRe will be
completed. However,
flag bits will be
substituted in the
eRe field.
Abort will still be
transmitted - output
will be in the mark
state.
Transmitter Disabled During
Transmission
-Idle characters are defined as a string of 15 or more contiguous ones.
For character oriented protocols (Bisync, Monosync), the
same discussion is valid, except that during transmit under-run condition and transmit under-run/EOM bit in set
state, instead of flags, filler sync characters are transmitted. ,
"
mode bit (WR3: D2). In general receive mode ( WR3:
D2=0), all frames will be received.
Since the MPSC only recognizes single byte address fiel9,
extended address recognition will have to be done by the
CPU on the data passed on by the MPSC. If the first address byte is checked by.the MPSC, and the CPU determines that the second address byte does not have the
correct address field, it must set the Hunt Mode (WR3:
D2 = 1) and the MPSC will start searching for a new address byte preceded by a flag.
CRC Generation:
The'transmit CRC enable bit (WR5: DO) must be set before loading any data into the MPSC. The CRC generator
must be reset to all 1's at the beginning of each frame before CRC computation has begun. The CRC computation
starts on the first data character loaded from the CPU and
contillues until the last data character. The CRC generated is inverted before it is sent on the Tx Data line.
Programmable Interrupts: The receiver may be programmed into anyone of the four modes. See Figure 13
for details.
Transmit Termination:
A successful transmission can be terminated by issuing a
"Reset Transmit Interrupt/DMA Pending" command, as
discussed earlier. However, the transmitter may be disabled any time during the transmission and the results will
be as shown in Figure 12.
WR1,CHA
D4
D3
RECEIVE IN INTERRUPT MODE
0
0
0
The receiver has to be initialized into the appropriate receive mode (see sample program later in this application
note). The receiver must be, programmed into Hunt Mode
(WR3: D4) before it is enabled (WR3: DO). The receiver
will remain in the Hunt Mode until a flag (or sync character) is received. While in the SDLC/Bisync/Monosync
mode, the receiver does not enter the Hunt Mode unless
the Hunt bit (WR3, D4) is set again or the receiver is enabled again.
"
1
0
1
1
SDLC Address byte is stored in WR6. A global address
(FFH) has been hardwired on the MPSC. In address
search mode (WR3: D2 = 1), any frame with address
matching with the address in WR6 will be received by the
MPSC. Frames with global address (FFH) will also be received, irrespective of the condition of address search
Result
1
Figure 13.
Rx Interrupt Mode
Rx INT/DMA disable
Rx INT on first character
INT on all Rx characters
(Parity affects vector)
INT on all Rx characters
(Parity does not affect vector)
Receiver Interrupt Modes
All receiver interrupts can be disabled by WRl: D4 D3 =
oo. Receiver interrupt on first character is normally used
to start a DMA transfer or a block transfer sequence using
WAIT to synchronize the data transfer to received or
transmitted data.
External Status Interrupts:
Any change in DCD input or Abort detection in the received data, will generate' an interrupt if External Status
Interrupt was enabled (WRl: DO).
7-127
AFN-02213A
inter
AP-145
Special Receive Con'OFFH,
OUTPUT (COMMAND.B_74 I - TABLE_74~(CII
C=C+l,
OUTPUT'(COMMAND.B_74I - TABLE_74~(CI'
C=C+l,'
'
ENDI
c=o;
DO WHILE
<> OFFH,
.. TABLE_74~(CII
TABLE_74~(C)'
OUTPUT(COMMAND~_74)
C-C+l1
OUTPUT(COMMAND_A_74) ..
C-C+l1
TABLE_74~(C)1
END,
RETURN,
END INlTIA~IZE_82741
Figure 18. Typical MPSC SOLe Initialization Sequenca
7-131
AF~13A
AP·145
For this application, the CPU is run at 8 MHz. The board"
is configured to operate the 8274 in SDLC operation with
the data transfer in DMA mode using the 8237 A. 8274 is
configured first in non-vectored mode in which case the
INTEL Priority Interrupt Controller 8259A is used to resolve priority b.etweeen various interrupting sources on the
board and subsequently interrupt the CPU. However, the
vectored mode of the 8274 is also verified by disabling the
8259A and reading the vectors from the 8274. Software
examples for each case will be shown later.
·
.
The application example is interrupt driven and uses
DMA for all data transfers under 8237A control. The
·8254 provides the transmit and receive clocks for the
8274. The 8274 was run at 40,0,K baud with a local.loopback Uumper wire) on Channel A data.The board was
also run at 80,0,K baud by modifying the software as wlll be
discussed later in the Special Applications section. One
detail to note is that the Rx Channel DMA request line
from the 8274 has higher priority than the Tx Channel
DMA request line. The 8274 master clock was 4.0. MHz.
The on-board RAM is used to define transmit and receive
data buffers. In this application, the data is read from
memory location 80,0,H through 810,H and transferred to
memory location 90,0,H to 910,H through the 8274 Serial
Link. The operation is full duplex. 8274 modem control
pins, CTS and CD have been tied low (active).
Interrupt Routines
The 8274 interrupt routines will be discussed here. On an
8274 interrupt, program branches off to the "Main Inter. rupt Routine". In main interrupt routine, status register
RR2 is read. RR2 contains the modified vector. The cause
of the interrupt is determined by reading the modified bits
of the vector. Note that the 8274 has been programmed in
the non-vectored mode and status affects vector bit has
been set. Depending on the value of the modified bits, the
appropriate interrupt routine is called. See Figure 19 for
the flow diagram and Figure 20. for the source code. Note
that an End of Interrupt Command is issued after servicing the interrupt. This is necessary to enable the lower priority interrupts.
Figure 21 shows all the interrupt routines called by the
Main Interrupt Routine. "Ignore. Interrupt" as the name
implies, ignores any interrupts and sets the FAIL flag.
This is done because this program is for Channel A only
and we are ignoring any Channel B interrupts. The important thing to note is the Channel A Receiver Character
available routine. This routine is called. after receiving the
first character in the SDLC frame. Since the transfer
mode is DMA, we have a maximum of three character
times to service this interrupt by enabling the DMA
controller.
Software
The software consists of a monitor program and a program to exercise the 8274 in ~he SDLC mode. Appendix A
contains the entire program listing. For the sake of clarity,
each source module has been rewritten in a simple language and will be discussed here individually. Note that
some labels in the actual listings in the Appendix will not
match with the labels here. Also the Hsting in the f\.ppendix sets up some flags to communicate with the monitor.
Some of these flags are not explained in detail for the reason that they are not pertinent to this discussion. The monitor takes the command from a keyboard and executes this
program, logging any error condition which might occur.
IF V2V1V0
IF V2V1V0
IF V2V1V0
IF V2V1V0
IF V2V1V0
IF V2V1V0
~
~
0, CALL IGNORE - INTERRUPT
1, CALL IGNORE - INTERRUPT
2, CALL CHB Rx CHAR
~
CALL IGNORE - INTERRUPT
~ 4, CALL IGNORE - INTERRUPT
~ 5, CALL CHA - EXTERNAL CHANGE
INTERRUPT
IF V2V1V0 ~ 6, CALL CHA Rx CHAR
IF V2V1V0 ~ 7, CALL CHA Rx SPECIAL
8274 Initialization
The MPSC is initialized in the SDLC mode for Channel
A. Channel B is disabled. See Figure 18 for the initialization routine. Note that WR4 is initialized before setting
· up the transmitter and receive parameters. However, it
may also be pointed out that other than WR4, all the other
n,gisters may be programmed in any order. Also SDLCCRC has been programmed for correct operation. An incorrect CRC selection will result in incorrect operation.
· Also note· that receive interrupt on first receive character
has been programmed although Channel A is in the DMA
mode.
.
.
Figure 19.
7-132
~
a,
Interrupt Response Flow Diagram
AFN.()2213A
intJ
AP-145
1**************************1
1* MAIN INTERRUPT ROUTINE *1
1**************************1
OUTPUT (COMMAND_B_74 I .. 2.
TEMP .. INPUT (STATUS_B_74 I AND 07H.
1* SET POINTER TO 2*1
1* READ INTERRUPT VECTOR *1
1* CHECK FOR CHA INT ONLY*I
1* FOR THIS APPLICATION CH B INTERRUPTS ARE IONORED*I
DO CASE TEMP.
CALL
IONORE_INT.
1* V2VIVO .. 000*1
CALL
IONORE_INT.
1* V2VIVO ., 001*1
CALL
CHB_RX_CHAR'
010*1
1* V2VIVO
CALL
IONORE_INT.
1* V2VIVO ., 011*1
CALL I I ONORE_I NT.
1* V2VIVO .. 100*1
CALL
CHA_EXTERNAL_CHANOE,
1* V2VIVO = 101*1
CALL
CHA_RX_CHAR'
1* V2VIVO ., 110*1
CALL
CHA_RX_SPECIAL,
1* V2VIVO ., 111*1
END,
OUTPUT (COMMAND_A_74 I =38H.
1* END OF INTERRUPT FOR 8274 *1
RETURN,
END INTERRUPT_8274,
Figure 20. Typical Main Interrupt Routine
1******************************************************1
1* CHANNEL A EXTERNAL/STATUS CHANOE INTERRUPT HANDLER *1
1******************************************************1
CHA_EXTERNAL_CHANOE: PROCEDURE,
TEMP" INPUT(STATUS_A_741,
1* STATUS REO 1*1
IF (TEMP AND END_OF_TX_MESSAOEI = END_OF_TX_MESSAOE THEN
TXDONE_S=DONE,
ELSE DO.
TXDONE_S=DONE,
RESULTS_S=FAILI
END.
OUTPUT (COMMAND_A_74I = 10H,
1* RESET EXT/STATUS INTERRUPTS *1
RETURN,
END CHA_EXTERNAL_CHANOE'
1**********************************************************1
1* CHANNEL A SPECIAL RECEIVE CONDITIONS INTERRUPT HANDLER *1
1**********************************************************1
CHA_RX_SPECIAL: PROCEDURE,
OUTPUT (COMMAND_A_74 I ., 1,
TEMP" INPUT(STATUS_A_741,
IF (TEMP AND END_OF_FRAMEI ., END_OFJFRAME THEN
DO,
IF(TEMP AND 040Hl = 040H THEN
RESULTS S = FAIL,
1* CRC ERROR *1
RXDONE_S ;;; DONE,
OUTPUT (COMMAND_A_74 I .. 30H, I*ERROR RESET*I
END,
ELSE DO,
IF (TEMP AND 20Hl = 20H THEN DO,
RESULTS_S ., FAIL,
1* RX OVERRUN ERROR*I
RXDONE_S ., DONE.
OUTPUT (COMMAND_A_74 I = 30H. I*ERROR RESET*I
END,
END,
RETURN,
END CHA_RX_SPECIAL,
1.*****************************************1
1* CHANNEL A RECEIVE CHARACTER AVAILABLE *1
/*****************************************1
CHA_RX_CHAR: PROCEDURE,
OUTPUT (SINOLE_MASKI .. CHO_SEL,
RETURN,
END CHA_RX_CHAR'
I*ENABLE RX DMA CHANNEL*I
Figure 21. 8274 Typical Interrupt Handling Routines
7-133
AFN.0221aA
inter
AP-145
It may be recalled that the receiver buffer is three bytes
deep in addition to the receiver shift register. At very high
data rates, it may not be possible to have enough time to
read RR2, enable the DMA controller without overrunning the receiver. In a case like this, the DMA controller
may be left enabled before receiving the Receive Character Interrupt. Remember, the Rx DMA request and interrupt for the receive character appears at the same time. If
the DMA controller is enabled, it would service the DMA
request by reading the received character. This will make
the 8274 interrupt line go inactive. However, the 8259A
has latched the interrupt and a regular interrupt acknowledge sequence still occurs after the DMA controller has
completed the transfer and given up the bus. The 8259A
will return Level 7 interrupt since the 8274 interrupt has
gone away. The user software must take this into account,
otherwise the CPU will hang up.
The procedure shown for the Special Receive:Condition
Interrupt checks if the interrupt is due to the End of
Frame. If this is not TRUE, the FAIL flag is set and the
program aborted. For a real life system, this must be followed up by errot'recovery proCedures which obviously are
beyond the scope ofthis Application Note.
The transmission is terminated when the End of Message
(RRO, D6) interrupt is generated. This interrupt is serviced in the Channel A External/Status Change interrupt
procedure. For any other change in external status conditions, the program is aborted and a FAIL flag set.
Main Program
Finally, we wiil briefly discuss the main program. Figure
22 shows the source program. It may be noted that the
Transmit Under-run latch is reset after loading the first
character into the 8274. This is done to ensure CRC transmission at the end of the frame. Also, the first character is
loaded from the CPU to start DMA transfer of subsequent data. This concludes our discussion on hardware
and software example. Appendix A. also includes the software written to exercise the 8274 in the vectored mode by
disabling.the 8259A.
CHA_SDLC_TEST' PROCEDURE BYTE PUBLIC.
CALL
ENABLE_INTERRUPTS_S.
CALL
INIT_8274_SDLC_S.
ENABLEI
OUTPUT (COMMAND_A_74) • 28H. 1* RESET TX INT/DMA
*1
OUTPUT(COMMAND-P_74) = 28H. 1* BEFORE INITIALIZING 8237*1.
CALL
INIT_8237_S.
OUTPUT (DATA_A_74) .OOH •.
I*LOAD FIRST CHARACTER FROM *1
I*CPU *1
1* TO ENSURE CRC TRANSMISSION. RESET TX UNDERRUN, LATCH
OUTPUT(COMMAND_A_74) • OCOH.
RXDONE_S.TXDONE_S=NOT_DONE. 1* CLEAR ALL FLAGS
RESUL TS_S-PASS.
1* FLAG SET FOR MONITOR
DO WHILE TXDONE_S-NOT_DONE. 1* DO UNTIL TERMINAL COUNT
END.
DO WHILE(INPUT(STATUS-A_74) AND 04H) <> 04H.
1* WAIT FOR CRC TO GET TRANSMITTED *1
1* TEST FOR TX BUFFFER EMPTY TO VERIFY THIS*I
END.
DO WHILE RXDONE_S=NOT_DONE. 1* DO UNTIL TERMINAL COUNT
END.
CALL
STOP 8237 S.
END CHA_SDLC_TESTI
Figure 22.
*1
*1
Typical 8274 Transmit/Receive Set-Up in SOLe Mode
7-134
AFN-02213A
inter
AP-145
Vee
CPU
INT~o(}-~--------r---------------~--------------__
INTA p---------~---t_----------_--__t----------------
8085 CPU
8085 INTERRUPT
MODE 1
IAPX·88/86
CPU
8088/86
INTERRUPT MODE
Figure 23.
8085 INTERRUPT
MODE 3
8088/86
INTERRUPT MODE
1088/86
INTERRUPT MODE
8274 Daisy Chain Vectored Mode
SPECIAL APPLICATIONS
In this section, some special application issues will be discussed. This will be useful to a user who may be using Ii
mode which is possible with the 8274 but not explicitly explained in the data sheet.
MPSC Daisy Chain Operation
Multiple MPSt can be connected in a daisy-chain configuration (see Figure 23). This feature may be useful in an
application where multiple communication channels may
be required and because of high data rates, converttional
interrupt controller is not used,to avoid long interrupt response times. To configure the MPSCs for the daisy chain
operation, the interrupt priority input pins (IPI) and interrupt priority output pins (IPO) of the MPSC should be
connected as shown. The highest priority device has its IPI
pin connected to ground. Each MPSC'is programmed in a
vectored mode with status affects vector bit set. In the
8085 basic systems, only one MPSC should be programmed in the 8085 Mode 1. This is the MPSC which
will put the call vector (CD Hex) on the data bus in response to the first INTA pulse (See Figure 15). It may be
pointed out that the MPSC in 8085 Mode 1 will provide
the call 'vector irrespective of the state of IPI pin. Once a
higher priority MPSC generates an interrupt, its IPO pin
goes inactive thus preventing lower priority MPSCs from
interrupting the CPU. Preferably the highest priority
MPSC should be programmed in 8085 Mode 1. It may be
recalled that the Priority Resolve Time on a given MPSC
extends from th falling edge of the first INTA pulse to the
falling edge of the second INTA pulse. During this period,
no new internal interrupt requests are accepted. The
maximum number of the MPSCs that can be connected in
a daisy chain is limited by the Priority Resolution Time.
Figure 24 shows a maximum number of MPSCs that can
be connected in various CPU systems. It may be pointed
out that IP() to IPI delay time specification is lOOns.
B.isync Transparent Communication
Bisync applications generally require that data transparency be established during communication. This requires
that the special control characters may not be included in
the CRC accumulation. Refer to the Synchronous Protoc~1 Overview section- for a more detailed discussion on
data transparency. The 8274 can be used for transparent
communication in Bisync communications. This is made
System
Configuration
Pribrity Resolution Time
Min (ns)
Number of 8274s Daisy Chained
(Max)
8086-1
8086-2
8086
8088
8085-2
8085A
400
500
800
800
1200
1920
'4
5
8
8
12
19
Note: Zero wait states have been assumed.
Figure 24. 8274 Daisy Chain Operation
7-135
AFN.Q2213A
inter
AP-145
possible by the capability of the MPSC to selectively turnon/turnoff the CRC accumulation 'while transmitting or
receiving. In bisync transparent transmit mode, the special characters (OLE, OLE SYN etc) are excluded from
CRC calculation. This can be easily accomplished by
turning off the transmit CRC calculation (WR5: 05=0)
before loading the special character into the transmit
buffer. If the next character is to be included in the CRC
accumulation, then the CRC can be enabled (WR5:
05 = I). See Figure 25 for a typical flow diagram.
Figure 26.
Figure 25.
(WR3:01) must be set in order to use the auto enable
mode. In non-auto mode, the transmitter or receiver is enabled if the corresponding bits are set in WR5 and WR3,
irrespective of the state CTS or OCO pins. It may be recalled that any transition on CTS or OCO pin will generate External/Status Interrupt with the corresponding bits
set in RRI. This interrupt can be cleared by issuing a Reset External/Status interrupt command as discussed earlier.
Transmit in Bisync transparent Mode
Note that in auto enable mode, the character to be transmitted must be loaded into the transmit buffer after the
CTS becomes active,. not before. Any character loaded
into the transmIt buffer before the CTS became active will
not be transmitted.
During reception, it is possible to exclude received character from CRC calculation by turning off the Receive CRC
after reading the special character. This is made possible
by the fact that the received data is presented to receive
CRC checker 8 bit times after the character has been received. During this 8 bit times, the CPU must read the
character and decide if it wants it to be included in the
CRC calculation. Figure 26 shows the typrcal flow diagram to achieve this.
!
Receive in Bisync Transparent Mode
High Speed DMA Operation
h should be noted that the CRC generator must be enabled during CRC reception. Also, after reading the CRt:
bytes, two more characters (SYNC) must be read before
checking for CRC check result in RRI.
Auto Enable Mode
In some data communication applications, it may be required to enable the transmitter or the receiver when the
CTS or the OCO lines respectively, are activated by the
modems. This may be done very easily by programming
the 8274 into the Auto Enable Mode.The auto enable
mode is set by writing a 'I' to WR3,05. The function of
this mode is to enable the transmitter automatically when
CTS goes active. The receiver is enabled when OCO goes
active. An in-active state of CTS or OCO pin wili disable
the transmitter or the receiver respectively. However, the
Transmit Enable bit (WR5:03) and Receive Enable bit
7-136
In the section titled Application Example, the MPSC has
been programmed to operate in OMA mode and receiver
is programmed to generate an interrupt on the first receive
character. You may recall that the receive FIFO is three
bytes deep. On receiving the interrupt on the first receive
character, the CPU must enable the OMA controller
within three received byte times to avoid receiver over-run
condition. In the application example, at 400K baud, the
CPU had approximately 60 JlS to enable the OMA controller to avoid receiver buffer overflow. However, at higher baud rates, tbe CPU may not have enough time to
enable the OMA controller in time. For example, at 1M
baud, the CPU should enable the OMA controller within
approximately 24 JlS to avoid receiver buffer overrun. In
most applications, this is not sufficient time. To solve this
problem, the OMA controller should be left enabled before getting the interrupt on the first receive character
(which is accompanied by the Rx OMA request for the
appropriate channel). This will allow the OMA controller
to start OMA transfer as soon as the Rx OMA request becomes active without giving the CPU enough time to reAFN-02213A
inter
AP-145
, spond to the interrupt on the first receive character. The
CPU will respond to the interrupt after the OMA transfer
has been completed and will find the 8259A (See Application Example) responding with interrupt level 7, the lowest priority level. Note that the 8274 interrupt request was
satisfied by the OMA controller, hence the interrupt on
the first receive character was cleared and the 8259A had
no pending interrupt. Because of no pending interrupt, the
8259 A returned interrupt level 7 in response to the INT A
sequence from the CPU. The user software should take
care of this interrupt.
Initialization Sequence
The MPSC initialization routine must issue a channel Reset Command at the beginning. WR4 should be defined
before other registers. At the end of the initialization sequence, Reset External/Status and Error Reset commands should be issued to clear any spurious interrupts
which may have been caused at power up.
Transmit Under-run/EOM Latch
At the end of transmission, the CPU must issue "Reset
Transmit Interrupt/OMA Pending" command in WRO to
reset the last transmit empty request which was not satisfied. Failing to do so will result in the MPSC locking up in
a transmit empty state forever.
In SOLC/HOLC, bisync and monosync mode, the transmit underrun/EOM must be reset to enable the CRC
check bytes to be appended to the transmit frame or transmit message. The transmit under-run/EOM latch can be
reset only after the first character is loaded into the transmit buffer. When the transmitter under-runs at the end of
the frame, CRC check bytes are appended to the frame/message. The transmit under-run/EOM latch can be
reset at any time during the transmission after the first
character. However, it should be reset before the transmitter !lnder-runs otherwise, both bytes of the CRC may not
be appended to the frame/message. In the receive mode in
bisync operation, the CPU must read the CRC bytes and
two more SYNC characters before checking for valid
CRC result in RRI.
Non-Vectored Mode
Sync Character Load Inhibit
In non-vectored mode, the Interrupt Acknowledge pin
(INTA) on the MPSC must be tied high through a pull-up
resistor. Failing to do so will result in unpredictable response from the 8274.
In.bisync/monosync mode only, it is possible to prevent
loading sync characters into the receive buffers by setting
the sync character load inhibit bit (WR3:01 = I). Caution must be exercised in using this option. It may be possible to get a CRC character in the received message which
may match the sync character and not get transferred to
the receive buffer. However, sync character load inhibit
should be enabled during all pre-frame sync characters so
the software routine does not have to read them from the
MPSC.
PROGRAMMING HINTS
This section will describe some useful programming hints
which may be useful in program development.
Asynchronous Operation
HOLC/SOLC Mode
When receiving data in SOLC mode, the CRC bytes must
be read by the CPU (or OMA controller) just like any other data field. Failing to do so will result in receiver buffer
overflow. Also, the End of Frame Interrupt indicates that
the entire frame has been received. At this point, the CRC
result (RRI:06) and residue code (RRI:03, 02, 01)
may be checked.
In SOLC/HOLC mode, sync character load inhibit bit
must be reset to zero for proper operation.
EOI Command
EOI Command can only be issued through channel A irrespective of which channel had generated the interrupt.
Status Register RR2
RR2 contains the vector which gets modified to indicate
the source of interrupt (See the section titled MPSC
Modes of Operation). Howe\ler, the state of the vector
does not change if no new interrupts are generated. The
contents of RR2 are only changed when a new interrupt is
generated. In order to get the correct information, RR2
must be read only after an interrupt is generated, otherwise it will indicate the previous state.
Priority in OMA Mode
There is no priority in OMA mode between the following
four
signals:
TxORQ(CHA),
RxORQ(CHA),
TxORQ(CHB), RxORQ(CHB): The priority between
these four signals must be resolved by the OMA controller. At any given time, all four OMA channels from the
8274 are capable of going active.
7-137
AFN.(J2213A
AP-145
APPENDIX A
APPLICATION EXAMPLE: SOFTWARE LISTINGS
7-138
AFN-02213A .
AP-145
PL/M-B6, COMPILER
tBBC
ee/4~
B274 CHANNEL A BDLC TEST
SERIES-III PL/M-86 V2.0 COMPILATION,OF MODULE INIT~274_S
OI~ECT MODULE PLACED IN :Fl:SINI74.0B~
COMPILER INVOKED BY: PLMB6.B6 :Fl:SINI74.PLM TITLE(tSBC SB/4~ S274 CHANNEL
A SDLC TEST) COMPACT NOINTVECTOR ROM
,····**·*****·**······**·***····***·····•..*****••*11
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
INITIALIZE THE B274 FOR SDLC MODE
1. RESET CHANNEL.
2. EXTERNAL INTERRUPTS ENABLED
3. NO'WAIT
4. PIN 10 - RTS
5. NON-VECTORED INTERRUPT-BOB6 MODE
6. CHANNEL ADM, CH B INT
7. tx AND RX • B BITSICHAR
9. ADDREee SEARCH MODE
10. CD AND CTS AUTO ENABLE
tl. Xl CLOCK
12. NO PARITY
13.IDLC/HDLC MODE
14.RTS AND DTR
U. CCITT - CRC
'
,
16. TRANSMITTER AND RECEIVER ENABLED
17.7EH • 'FLAO
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
'***···*····*********·.·********·.********•••*.***1
INIT_S274J1: DO,
.INCLUDE (:Fl:PORTS.PLM)
,
'···*··.*******••******•••••****•••***********1
1*
*1
1*
IIBC ee/4~ PORT ASSIGNMENTS
*1
1*
*1
1**********************************************1
DECLARE LIT LITERALLY 'LITERALLY',
1* B237A-5 PORTS *1
3
DECLARE CHOJIDDR
CHO_COUNT
CHIJ1DDR
CHI_COUNT
CHlU..DDR
CHi_CDUNT
CH3..ADDR .
CH3_COUNT
STATUS_37
COMMAND_37
REGUEST~EO_37
SINOLEjMASK
MODE~EO_37
PL/M-86 COMPILER
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
'080H',
'081H',
'OB2H',
'083H',
'084H',
'OB5H',
'OS6H',
'o8m',
'OBBH',
'088H',
'OS9H',
'OSAH',
'OSBH',
tSIC B8/45 8274 CHANNEL A SOLC TEST
CLR....BYTEJ'TR_37
TE.... ~EO_37
MASTER_CLEAR_37
ALLjMASK_37
LIT
LIT
LIT
LIT
'OSFH',
LIT
LIT
LIT
'092H',
'OSCH',
'OSDH',
'OBDH',
1* 8254-2 PORTS *1
4
DECLARE CTR_OO
CTR_Ol
CTR_02
7-139
'090H',
'091H',
,
AP-145
CONTROL.O_54
STATUSO_54
CTR_l0
CTR_ll
CTR12
CONTROL.l_54
STATUS1_54
L.IT
L.IT
LIT
L.IT
L.IT
LIT
L.IT
'093H',
'093H',
'098H',
'099H',
'09AH',
'09BH',
'09BH';
1* B255 PORTS *1
5
DECLARE PORTA_55
PORTB_55
PORTC_55
CONTROL._55
LIT
L.IT
L.IT
LIT'
'OAtH',
'OA2H',
LIT
LIT
LIT
LIT
LIT
LIT
'OO1H',
'OD2H',
'OD2H',
'OD3H',
'OAOH',
'OA3H';
1* B274 PORTS */'
6
DECLARE DATA_A_74
DATA_B_74
STATUSJI_74
COMMAND_A_74
STATUS_B_74
COMMAND_B_74
'ODOH',
'OD3H',
1* B259A PORTS *1
7
DECLARE STATUS_POLL_59
ICW1_59
OCW2_59
OCW3_59
OCWl 59
ICW2:59
ICW3_59
ICW4_59
LIT
LIT
LIT
LIT
LIT
LIT
LlT
LIT
'OEOH',
'OEOH',
'OEOH',
'OEOH',
'OE1H',
'OE1H',
'OE1H',
'OE1H',
1* B274 REGISTER BIT ABSIGNMENTS *1
1* READ REGISTER o *1
B
DECLARE RX_AVAIL
INT]ENDING
TX_EMPTY
CARR IER_DETECT
SYNC HUNT
CLEAR_TO_SEND
PL/M-86 COMPILER
LIT
LIT
LIT
LIT
LIT
LIT
'01H',
'02H',
'04H',
'OSH',
'10H',
'20H',
iSBC 8B/45 8274 CHANNEL A SDLC TEST
END_OF _TX_MESSAGE LIT
BREAK_ABORT
LIT
'40H',
'BOH';
1* READ REGISTER 1 *1
9
DECLARE ALL_SENT
PARITY_ERROR
RX_OVERRUN
CRC ERROR
END:OF _FRAME
LIT
LIT
LIT
LIT
LIT
'01H',
'10H',
'20H',
'40H',
'BOH';
1* ,READ REGI,STER 2 *1
10
DECLARE TX_B_EMPTY
EXT_B_CHANGE
RX_B_AVAIL
RX_B_SPEC IAL
TX_A_EMPTY
EXT~A3HANGE
RX_A_AVAI\..
RX_A_SPEC IAL
7-140
LIT
LIT
LIT
LIT
LIT
,LIT
LIT
LIT
'OOH',
'01H',
'02H',
'03H',
'04H',
'05H',
'06H',
'07H"
AFN-02213A
intJ
AP-145
1* 8237 BIT ASSIGNMENTS *1
DECLARE CHO_SEL
CH1_SEL
CH2_SEL
CH3_SEL
WRITE_XFER
READ_XFER
DEMANDJ10DE
SINGLE_MODE
BLOCK_MODE
SET_MASK
11
12
13
14
15
16
17
18
1
2
2
2
3
3
2
DELAY_S: PROCEDURE
DECLARE D WORD,
D-O,
DO WHILE D<800H,
D-D+l.
END.
END DELAY _S,
'OOH',
'OIH',
'OiiZH',
'03H',
'04H',
'OSH',
'OOH',
'40H',
'BOH',
'04H',
P~BLIC,
PROCEDURE PUBLIC,
19
20
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
2
DECLARE C
BYTE,
$E.JECT
PL/M-86 COMPILER
lSBC 88/45 8274 CHANNEL A SDLC TEST
1* TABLE TO INITIALIZE THE 8274 CHANNEL A AND B *1
1*
1*
21
2
22
2
FORMAT IS: WRITE REGISTER. REGISTER DATA
INITIALIZE CHANNEL ONLY
*1
*1
DECLARE TABLE_74_A(~' BYTE DATA
1* CHANNEL RESET *1
(00H.18H.
1* RESET TX CRC *1
OOH.80H.
1* PIN 10-RTSB. A DMA. B INT *1
02H.llH.
1* SDLC/HDLC MODE. NO PARITY *1
04H.2OH.
1* SDLC FLAG *1
07H.07EH.
1* RX DMA ENABLE *1
0IH.OBH.
1* DTR. RTS. 8 TX BITS. TX ENABLE. TX CRC ENABLE *1
05H.OEBH.
1* DEFAULT ADDRESS *1
OhH. ~5H.
1* 8 RX BITS. AUTO ENABLES. HUNT MODE. *1
03H.OD9H.
1* RX CRC ENABLE *1
1* END OF INITIALIZATION TABLE *1
OFFHI,
DECLARE TABLE_74_B(*1 BYTE DATA
1* INTERRUPT YECTOR .1
(02H.OOH.
1* STATUS AFFECTS YECTDR *1
0IH.1CH.
OFFHI,
1* END *1
1* INITIALIZE THE 8254 *1
23
24
25
2
2
2
OUTPUT (CONTROLO_54 1-36H,
OUTPU~(CTR~OOI • LOW(201,
OUTPUT (CTR_OO I • HIGH(201,
1* BAUD RATE • 400K BAUD.I
1* BAUD RATE • 400K:BAUD*1
1* INITIALIZE THE 8274 *1
26
27
28
2
2
3
29
3
30
3
31
3
32
3
C-O,
DO WHILE TABLE]4_B(CI <> OFFH.
OUTPUT (COMMAND_B_74 I • TABLE_74_B(CI'
C-C+l,
OUTPUT (COMMAND_B_74) ."TABLE_74_B(C)'
C=C:+-l,
END.
7-141
AFN-02213/\
. . inter
33
34
2 .
3'
3
2
36'
37
3B
39
40
3
3
41
42
43
2
3
3
2
2
1
CaOI
DO WHILE TABLE_74~(C) <> OFFHI
OUTPUT(COI1MAND_A_74) a TABLE":'74~(C)1
CaC+ll
OUTPUT 04H,
1* WAIT FO~ CRC TO QET TRANSMITTED *1
1* TEST FOR TX BUFFFER EMPTY TO VERIFY THIS*I
END,
DO WHILE RXDONE_S-NOT-P0NE,
1* DO UNTIL TERMINAL COUNT*I
END,
47
2
CALL
STOP_8237_S,
48
2
CALL
DISABLE_INTERRUPTS_S.
49
:I
CALL
VERIFY_TRANSFER_S,
'0
2
RETURN RESULTS_S,
51
'2
2
1
OUTPUTCCOMMAND~_74)
2
1* DO UNTIL TERMINAL COUNT*I
END,
END CHA_SDLC_TEST,
END STEST.
MODULE INFORMATION:
CODE AREA SIZE
0063H
CONSTANT AREA SIZE • OOOOH
VARIABLE AREA SIZE = 0OO3H
MAXIMUM STACK SIZE • 0004H
198 LINES READ
o PROgRAM WARNINQS
o PROgRAM ERRORS
99D
OD
3D
4D
END OF PL/M-B6 COMPILATION
PL/M-86 COMPILER
iSIC B8/4' 8274 CHANNEL A SDLC TEST
SERIE8-III PL/M-86 VOl. 0 COMPILATION OF MODULE VECTOR~ODE
OB~ECT MODULE PLACED IN :Fl:VECTOR.OB~
COMPILER INVOKED BY: PLM86.B6 : F1:VECTOR. PLH TITLEC1SIC 88/4' B274 CHANNEL A SDLC TEST)
1*****•••**** •• *****.******* ••*******.****· ••·.··***** *****.********,
1*
*1
1*
8274 INTERRUPT HANDLINg ROUTINE FOR
*1
1*
8274 VECTOR MODE
*1.
1*
STATUS AFFECTS VECTOR
*1
1*
*1
1.*.*.*********•••*.* ••" ••• **•••••**********.·.·*******************1
7-147
AfN-G2213A
AP-145
/* THIS IS AN EXAMPLE OF HOW 8274 CAN BE USED IN VECTORED MODE.
1* THE iSBC88/45 BOARD WAS REWIRED TO DISABLE THE PIT 8259A AND
/* ENABLE THE 8274 TO PLACE ITS VECTOR ON THE DATABUS IN RESPONSE
/* TO THE INTA SE~UENCE FROM THE 8088. OTHER MODIFICATIONS INCLUDED
/* CHANGES TO 8274 INITIALIZATION PROGRAM (SINI74) TO PROGRAM 8274
/* INTO VECTORED MODE (WRITE REGISTER 2A D5-1).
*1
*1
*1
*1
*1
*/
VECTORjMODE: DO,
.NOLIST
12
DECLARE TEMP BYTE,
DECLARE (RESULTS_S.TXDONE.RXDONE) BYTE EXTERNAL,
DECLARE DONE LITERALLY 'OFFH',
NOT_DONE LITERALLY 'OOH'.
PASS
LITERALLY 'OFFH'.
LITERALLY 'OOH',
FAIL
13
14
1***********************************************************************1
1*
TRANSMIT INTERRUPT CHANNEL A INTERRUPT WILL NOT BE SEEN IN THE *1
/*
DMA OPERATION.
*1
1****************************************************************~******I
15
16
17
18
TX_INTERRUPT_CHA:PROCEDURE INTERRUPT 84,
OUTPUT(COMMAND_A_74) = 00101000B,
/*RESET TXINT PENDING*/
OUTPUT(COMMAND A 74) • 00111000B,
/*EOI*I
END TX_INTERRUPT:CHA,
1
2
2
2
1***********************************************************************1
EXTERNAL/STATUS INTERRUPT PROCEDURE: CHECKS FOR END OF MESSAGE */
/*
ONLY. IF THIS IS NOT TRUE THEN THE FAIL FLAG IS SET. HOWEVER, *1
/*
A USER PROGRAM SHOULD CHECK FOR OTHER EXT/STATUS CONDITIONS
*/
/*
ALSO IN RRI AND THEN TAKE APPROPRIATE ACTION BASED ON THE
*/
/*
APPLICATION.·
*/
1***********************************************************************1
1*
19
20
21
22
23
1
2
2
2
2
24
3
EXT _STAT _CHANGE_CHA: PROCEDURE INTERRUPT 85,
TEMP = INPUT (STATUS_A_74),
IF (TEMP AND END OF TX MESSAGE) = END_OF_TX_MESSAGE THEN
TXDONE = DONE~ - ELSE DO,
TXDONE = DONE,
PL/M-86 COMPILER
25
26
3
3
27
28
29
2
30
2
2
2
iSBC 88/45 8274 CHANNEL A SDLC TEST
FAIL,
OUTPUT (COMMAND_A_74) = 00010000B,
OUTPUT (COMMAND_A_74) = 00111000B,
RETURN,
END EXT_STAT _CHANGE_CHA"
I*RESET EXT STAT INT*/
I*EOI*/
1***********************************************************************1
RECEIVER CHARACTER AVAILABLE INTERRUPT WILL APPEAR ONLY ON FIRST*I
RECEIVE CHARACTER. SINCE DMA CONTROLLER HAS Be:EN ENABLED BEFORE *1
1*
THE FIRST CHARACTER IS RECEIVED. THE RECEIVER REOUEST IS
*1
1*
SERVICED BY THE DMA CONTROLLER.
*/
1*
1*
I******************************.***~************************************1
31
32
33
34
1
2
2
2
RX_CHAR_AVAILABLE_CHA:PROCEDURE INTERRUPT R6i
OUTPUT (COMMAND_A_74) = 00111000B,
/*EOI*/
RETURN,
END RX_CHAR_AVAILABLE_CHA'
$EJECT
7-148
AFN-02213A
inter
AP-145
PL/M-86 COMPILER
iSBC
88/45
B274 CHANNEL A SDLC TEST
1***********************************************************************1
SPECIAL RECEIVE CONDITION INTERRUPT SERVICE ROUTINE CHECKS FOR *1
END OF FRAME BIT ONLY. SEE SPECIAL SERVICE ROUTINE FOR NON*1
VECTORED MODE FOR'CRC CHECK AND OVERRUN ERROR CHECK.
*1
1***********************************************************************1
1*
1*
1*
35
,
SPECIAL_RX_CONDITION_CHA:PROCEDURE INTERRUPT B7.
36
37
3B
39
40
41
42
43
44
45
46
47
2
2
2
2
2
3
3
3
2
2
2
2
OUTPUT(COMMAND~_741 - I.
I*POINTER 1*1
TEMP - INPUT(STATUS~_741.
IF (TEMP AND END_OF_FRAMEI = END_OF_FRAME THEN
RXDONE • DONE.
ELSE DO.
RXDONE
DONE.
RESULTS_S = FAIL.
END.
OUTPUT (COMMAND_A_74 I • 00110000B.
I*ERROR RESET*I
OUTPUT (COMMAND_A_74 I • 00111000Bl
I*EOI*I
RETURN.
END SPEC IAL_RX_CONDITI DN_CHAI
4B
49
50
51
52
53
54
1
2
2
2
2
2
2
2
ENABLE_INTERRUPTS: PROCEDURE PUBLIC.
DISABLE.
CALL SETS I NTERRUPT (B4. TX_INTERRUPT_CHAI.
CALL SETSINTERRUPT(B5.EXT_STAT_CHANGE_CHAI.
CALL SETSINTERRUPT(B6.RX_CHAR_AVAILABLE_CHAII
CALL SETSINTERRUPT(B7.SPECIALJRX_CDNDITIDN_CHAI.
RETURN.
END ENABLE_INTERRUPTS.
55
56
END VECTOR_MODEl
1***************************************************************************1
1***************************************************************************1
MODULE INFORMATION:
CODE AREA SIZE
CONSTANT AREA SIZE
VARIABLE AREA SIZE
MAXIMUM STACK SIZE
226 LINES READ
o PROQRAM WARNINGS
o PROGRAM ERRORS
• 012EH
= OOOOH
- 0001H
• 001EH
302D
OD
ID
30D
END OF PL/M-B6 COMPILATION
7-149
AFN.()2213A
AP·145
APPENDIXB
MPSC READ/WRITE REGISTER DESCRIPTIONS
7-150
AFN-02213A
AP-145
WRITE REGISTER 0 (WRO):
MSI
um
'D7ID8II",,,,·t~:c!~"A~~
REGISTER POINTER
o
o
o
o
1
1
1
1
o
o
1
1
0
0
1
1
0
0
1
1
NULL CODE
SEND ABORT (IDLe)
REseT EXT S1ATUSINTERRUPTS
CHANNEL REBET
ENABLE INTERRUPT ON NEXT RX CHARACTER
REBET TXIfiIT OMA PENDING
'ERROR ResET
END OF INTERRUPT
0
1
0
1
0
1
0
1
0 NULLCODE
1 RESET RX CRC CHECKER
0 RESET TX CRD GENERATOR
1 RESET TX UNDERRUN EOM LATCH
WRITE REGISTER 1 (WR1):
~I
I
~I
ID7ID8ID5ID1D~D~D1D~
o
o
1
~
I ~I=:~RUPT
L
0...-
,
OMAENABLE
STATUS AFFECTS VECTOR
(CHIONLV)
(NULL CODE
A)
~ ~~~~-:J~CTOR
fH
0 RxiNTIOMA DISABLE
1 RxlNT ON FIRST CHAR OR SPECIAL CONDmON
0 IN)' ON ALL Rx CHAR (PARITY AFFECTS VECTOR) OR
SPECIAL CONDmON
1 INT ON ALL Rx CHAR (PARITY DOES NOT AFFECT
VECTOR) OR SPECIAL CONDITION
1 WAIT ON Ax. 0 WAIT ON Tx
- - MUST IE ZERO
' - - WAIT ENABLE. 1 ENABLE. 0 DISABLE
7-151
AfN.02213A
inter
AP-145
WRITE REGISTER 2 (WR2): CHANNEL A
MSB
I
LSB
ID710ID5ID4ID3ID2JD1JD~
o
o
1
1
0
1
0
1
~~o01 ADMABINT
80TH INTERRUPT
o
80THDMA
1 ILLEGAL
L . - 1 PRIORITY RxA>RxB> TxA> TxB>EXTA'>EXTB'
o
PRIORITY RxA>TxA>RxB>TxB>EXTA'>EXTB'
8085 MODE 1
8085 MODE 2
8086/88 MODE
ILLEGAL
~ 1 VECTORED iNTERRUPT
o NON VECTORED INTERRUPT
' - - MUST BE ZERO
L.-
J ~:= 19 ~~l:'r6
• EXTERNAL STATUS INTERRUPT ONLY IF EXT
INTERRUPT ENJ\8LE (WR1:00) IS SET
WRITE REGISTER 3 (WR3):
WRITE REGISTER 2 (WR2): CHANNEL B
MSB
LSB
I"I~I~I~I~I~I~IWI
Rx ENABLE
SYNC CHAR LOAD INHIBIT
ADDR SRCH MODE (SDLC)
_
Rx CRC ENABLE
'NTERRUPT
VECTOR
ENTER HUNT MODE
AUTO ENABLES
o
o
0 Rx5 BITS/CHAR
Rx7 BITS/CHAR
o Rx6 BITS/CHAR
1 Rx8 BITS/CHAR
7-152
AFN-02213A
inter
AP-145
WRITE REGISTER 4 (WR4):
1 ENABLE PARITY
o OISABLE PARITY
Tx CRC ENABLE
EVEN PARITY
000 PARITY
o
o
1
1
o
o
1
1
o
o
1
1
0
1
0
1
RTS
'----- ~8i8~S8E;6
ENABLE SYNC MOOES
1 STOP BIT
1.5 STOP BITS
2 STOP BITS
' - - - - - - Tx ENABLE
o
8 BIT SYNC CHAR
1 18 BIT SYNC CHAR
SOLC/HOLC(01111110)FLAG
1 1 EXTERNAL SYNC MOOE
' - - - - - - - SENO BREAK
o
o
X1 CLOCK
1 X16 CLOCK
o X32 CLOCK
1 X64 CLOCK
o
o
1
0
1
0
1
1
Tx5 BITS OR LESS/CHAR
Tx7 BITS/CHAR
Tx8 BITS/CHAR
Tx8 BITS/CHAR
OTR
WRITE REGISTER 6 (WR6):
MSB
LSB
1071061051041031021011001
"
L
LEAST SI:NIFICANT
SYNC BYTE (AOORESS
IN SOLC/HOLC MOOE)
WRITE REGISTER 7 (WR7):
MSB
LSB
107108105104103102101103
"
L MQlHJII~IFIC~NT
SYNC BYTE (MUST
BE 01111110 IN
SOLe/HOLC MOOE)
7-153
AFN·Q2213A
inter
AP-145
READ REGISTER 0 (RRO):
MSB
LSB
ID71D1DstD1D1D~D l DoJ
L
Rx CHAR AVAILABLE
INT PENDING (CHA ONLY)
Tx BUFFER EMPTY
CARRIER DETECT
SYNC/HUNT
=
}
EXTERNAL
TxUNDERRUN/EOM
~fATUS
INTERRUPT MODE
BREAK/ABORT
\ '
READ REGISTER' (RR'):
(SPECIAL RECEIVE CONDITION MODE)
MSB
:c
LSB
LD7IDSIDSID4ID3ID2ID'IDOI
LALLSENT
I FIELD BYTE
PREVIOUS BYTE
o 0
o 0
o ,
0
,
0
o , ,
,
,
0 0
0 ,
,
~}
3
7
0
,,,
,
I FIELD BYTE
2ND PREVIOUS BYTE
2
0
0
0
0
,
0
0
RESIDUE DATA
BITS CHAR
MODE
5
8
' - - PARITY ERROR
' - - Rx OVERRUN ERROR
' - - CRC/FRAMING ERROR
END OF FRAME (SDLC HDLC MODE)
READ REGISTER 2 (RR2):
MSB
LSB
I V71 val VslwIV3-IV2-IVl'IVO-1
,
;
T
INTERRUPT
VECTOR
7-154
-VARIABLES IN
STATUS AFFECTS
VECTOR MODE
AFN-02213A
8251 A
PROGRAMMABLE COMMUNICATION INTERFACE
• Synchronous and Asynchronous
Operation
• Synchronous 5-8 Bit Characters;
Internal or External Character
Synchronization; Automatic Sync
Insertion
• Asynchronous 5-8 Bit Characters;
Clock Rate-1, 16 or 64 Times Baud
Rate; Break Character Generation;
1, 11f2, or 2 Stop Bits; False Start Bit
Detection; Automatic Break Detect
and Handling
• Synchronous Baud Rate-DC to
64K Baud
• Asynchronous Baud Rate-DC to
19.2K Baud
• Full-Duplex, Double-Buffered
Transmitter and Receiver
• Error Detection-Parity, Overrun and
Framing
• Compatible with an Extended Range
of Intel Microprocessors
• 28-Pin DIP Package
• All Inputs and Outputs are TTL
Compatible
• Available in EXPRESS
-Standard Temperature Range
-Extended Temperature Range
The Intel® 8251A is the enhanced version of the industry standard. Intel 8251 Universal Synchronous/
Asynchronous Receiver/Transmitter (USART). designed fordata communications with Intel's microprocessor
families such as MCS-48. 80. 85. and iAPX-86. 88. The 8251 A is used as a peripheral device and is programmed
by the CPU to operate using virtually any serial data transmission technique presently in use (including IBM
Ubi-sync"). The USARTaccepts data characters from the CPU in parallel format and then converts them into a
continuous serial data stream for transmission. Simultaneously. it can receive serial data streams and convert
them into parallel data characters for the CPU. The USARTwill signal the CPU whenever it can accept a new
character for transmission or whenever it has received a character for the CPU. The CPU can read the
complete status of the USARTat any time. These include data transmission errors and control signals such as
SYNDET. TxEMPTY. The chip is fabricated using N-channel silicon gate technology.
TxO
°
7 ,00
0,
03
TxADY
TxE
DO
RxD
Vee
GND
Rxe
0,
OTR
05
RTS
06
OSR
0,
RESET
he
WR
os
RxD
0,
c/o
elK
TxD
hEMPTY
eTS
SYNDET/BD
R:.RDY
TI(RDY
RxROY
fW;
Figure 2. Pin Configuration
Figure 1. Block Diagram
AFN-Q15730
OINTEI. CORPORATION, 1983
7-155
intJ
8251A
FUNCTIONAL
FEATURES AND I:NHANCEMENTS
The 8251A is an advanced design of the industrY
standard USART, tbe Intel$ 8251. The 8251A
operates with an 'extended range of, Intel
microprocessors lind maintains compatibili~y with
the 8251. Familiarization time is minimal because of
compatibility and involves only knowing the additional features and enhancements, and reviewing
the AC and DC specifiqations of the 8251A.
The 8251A incorporates all the key features of the
8251 and has ~he following additional featur~s and
enhancements:
DESCR~PTION'
General
The 8251A. is a .lJn!versal SynchronouslAsynQhronous Receiver/Transmitter desig,ned for a wide
range of Intel microcomputers sucll as 8048, 8080,
8085, 8086 and 8088. Like other I/O devices in a
microcomputer system~ its functional configuration
is programmed by the system's software for maximum flexibility. ~he 8251A can support most serial
data teChniques in ulje, including IBM "bi-sync."
• In asynchronous operations, the Receiver detects
and handles "break" automatically, relieving the
CPU of 'this task.
'
In a communication environment an interface
device must convert parallel format system data into
serial format for transmission and convert incoming
serial format data into parallel system data for reception. The interface device must also delete or insert
bits or characters that are functionally unique to the
comm.unication technique. In essence, the interface
should appear "transparent" to the CPU, a simple
input or output of byte-oriented system data.
• A refined Rx initialization prevents th,e Receiver
fr~m starting when in "break" state, preventing
unwanted interrupts from a disconnected USART.
Data Bus Buffer
• 8251A has double-buffered data paths ~ith separate I/O registers for control, status, Data In, and
Data Out, which considerably simplifies control
programming and minimizes CPU overhead.
• At the conclusion of a transmission, TxD line will
always return to the marking state unless SBRK is
programmed.
• Tx Enable logic enhancement p.revents a Tx Disable command from halting transmission until all
data previously written has been transmitted. The
logic also prevents the transmitter from turning
off in the middle of a word.
• When External Sync Detect is programmed, Internal Sync Detect is disabled, and an External Sync
Detect status is provided via a flip-flop which
clears itself upon a status read.
• Possibility of false sync detect is minimized by
ensuring that if double character sync is program· med, the characters be contiguously detected and
,also by clearing the Rx register to all ones
whenever Enter Hunt command is issued in Sync
mode.
• As long as the 8251A is not selected, the RD and
WR do not affect the internal operation of the
device.
• The 8251A Status can be read at any time but the
status update will be inhibited during status read.
• The 8251A is free from extraneous glitches and
has enhanced AC and DC characteristics, providing higher speed and better operating margins.
• Synchronous Baud rate from DC to 64K.
7-156
This 3-state, bidirectional, 8-bit buffer is used to interface the 8251A to the system Data Bus. Data is
transmitted or received by the buffer upon execution
of INput or OUTput instructions of the CPU. Control
words, Command words and Status information are
also transferred through the Data Bus Buffer. The
Command Status, Data-In and Data-Out registers
are separate, 8-bit registers communicating with the
system bus through the Data Bus Buffer.
This functional block accepts inputs from the system
Control bus and generates control signals for overall
device operation. It contains the Control Word Register and Command Word Register that store the
variou,s control formats for the device functional
definition.
RESET
(~eset)
A "high" on this input forces the 8251A into an "Idle"
mode. The device will remain at "Idle" until a new set
of control words is written into the 8251A to program
its functional definition. Minimum RESET pulse
width is 6 tCY (clock must be running).
A command reset operation also puts the device into
the "Idle" state.
AfN.01573D
8251A
ClK (Clock)
C/O (Control/Data)
The ClK input is used to generate internal device
timing and is normally connected to the Phase 2
(TTL) output of the Clock Generator. No external
inputs or outputs are referenced to ClK but the
frequency of ClK must be greater than 30 times the
Receiver or Transmitter data bit rates.
This input, in conjunction with the WR and RD inputs, informs the 8251A that the word on the Data
Bus is either a data character, control word or status
information.
1
= CONTROUSTATUS; 0 = DATA.
CS (Chip Select)
WR (Write)
A "Iow"on this input informs the 8251A that the CPU
is writing data or control words to the 8251A.
A "low" on this input selects the 8251A. No reading or
writing will occur unless the device is selected.
When CS is high, the Data Bus is in the float state and
RD and WR have no effect on the chip.
RD (Read)
Modem Control
A "low" on this input informs the 8251A that the CPU
is reading data or status information from the 8251 A.
The 8251A has a set of control inputs and outputs
that can be used to simplify the interface to almost
any modem. The mo~em control signals are general
purpose in nature and can be used for functions
other than modem control, if necessary.
DSR (Data Set Ready)
The DSR input signal is a general-purpose, 1-bit inverting input port. Its condition can be tested by the
CPU using a Status Read operation. The OOR input
is normally used to test modem conditions such as
Data Set Ready.
.
DTR (Data Terminal Ready)
The DTR output signal is a general-purpose, 1-bit
inverting output port. It can be set "low" by programming the appropriate bit in the Command Instruction word. The DTR output signal is normally
used for modem control such as Data Terminal
Ready.
/
INTERNAL
DATA BUS
RTS (Request to Send)
The FITS output signal is a general-purpose, 1-bit
inverting output port. It can be set" "low" by programminQ the appropriate bit in the Command Instruction word. The RTS output signal is normally
used for modem control such as Request to Send.
Figure 3. 8251A Block Diagram Showing Data
Bus Buffer and Read/Wrlte Logic
Functions
CTS (Clear to Send)
c/o
RD
WR
cs
0
0
0
1
0
0
0
1
X
X
0
1
X
X
0
0"
0
0
A "low" on this input enables the 8251A to transmit
serial data if the Tx Enable bit in the Command byte
is set to a "one." If either a Tx Enable off or CTS off
condition occurs while the Tx is' in operation, the Tx
will transmit all the data in the USART, written prior
to Tx Disable command before shutting down.
8251A DATA = DATA 8US
DATA 8US .. 8251A DATA
STATUS .. DATA BUS
DATA BUS-CONTROL
DATA"BUS= 3-STATE
DATA BUS- 3-STATE
7-157."
AFN-01573D
'.
inter
Transmitter
8251A
B~ffer
The Transmitter Buffer accepts parallel data from the
Data Bus Buffer, converts it to a serial bit stream,
inserts the appropriate'characters or'bits (based on
the communication t,echnique) and outputs a cOmposite serial stream of data on the TxD output pin 011
the falling edge of fiC. The transmitter will begin
= O. The
transmission upon being enabled if
TxD line will be held in the marking state immediately upon a master Reset or when Tx Enable or C'fS
is off or the transmitter is ,mpty.
rn
Transmitter Control
The Transmitter Control manages all activities associated with the transmission of serial data. It accepts
and issues signals both externally and internally to
accomplish this function.
TxRDY (Transmitter Ready)
This output signals the CPU that the transmitter is
ready tc? accept a data character. The TxRDY output
pin can be used as an interrupt to the system, since it
is masked by TxEnable; or, for Polled operation, the
CPU can check TxRDY using a Status Read operation. TxRDY is automatically reset by the leading
edge of WR when a data character is loaded from
the CPU.
Note that when using the Polled operation, the
TxRDY status bit is not masked by TxEnable, but will
only indicate the Empty/Full Status of the Tx Data
Input Register.
Figure 4. 8251A Block Diagram Showing Modem
and Transmitter Buffer and Control
Functions
Tie (Transmitter Clock)
The Transmitter Clock controls the rate at which the
character is to be transmitted. In the Synchronous
transmission mode, the Baud Rate (1x) is equal to
the TxC frequency, In Asynchronous transmission
mode, the baud rate is a,fraction of the actual TxC
frequency. A portion of the modEl instruction selects
this factor; it can be 1, 1/16 or 1/64 the TxC.
For Example:
TxE (Transmitter Empty)
When the 8251 A has no characters to send. the
TXEMPTYoutputwili go "high." It resets upon receiving a character from CPU if the transmitter is enabled. TxEMPTY remains high when the transmitter
is disabled. TxEMPTY can be used to indicate the
end of a transmission mode, so that the CPU "knoWs"
when to "turn the line around" In the half-duplex
operational mode.
',' '
In the Synchronous, mode, a "high" on this ootput
indicates that a character has not been loaded and
the SYNC character or characters are about to be or
are being transmitted automatioally as "fillers."
TxEMPTY does not go low when the SYNC characters are being shifted ,out.
7-158
If Baud Rate equals 110 Baud, '
TxC equals 110 Hz' in the 1'x mode.
TxC equals 1.72 kHz in the 16x mode.
, TxC equals 7.04 kHz in the 64x mode.
The falling edge o(f'XC'shifts the serial data out of
the 8251A.
' ','
,
Receiver Buffer
T~e Re~eiver accepts serial
data, converts this serial
input to parallel format, checks for bits or characters
that are unique to the communication technique
and sends an "assembled" character to'the CPU.
Serial data is, input..!2BxD pin, and is clQcked in on
'
the rising edge of RxC.
Af'N.01573D
inter
8251 A
RiC (Receiver Clock)
, Receiver Control
This functional block manages all receiver-related
activities which consists of the following features.
The RxD initialization circuit prevents, the 8251A
from. mistaking an unused input line for ~n active
low (iata line in the "break condition." Before
starting to receive serial characters on the RxD
line, a valid "1" must first be detected after a chip
master Reset. Once this ,has been determined, a
search for a valid low (Start bit) is enabled. This
feature is only active in the asynchronous mode,
and is only done once for each master Reset. ,
The False Start bit detection ,circuit prevents false
starts due to a transient noise spike by first detecting the falling edge and then strobing the nominal
center of the Start bit (RxD = lOW).
Parity error detection sets the' correspon~ing
status bit.
The F~aming Error status bit is set if the Stop bit is
absent !It the end of the data byte (asynchronous
mode).
The Receiver Clock controls the rate at which the
character is to be received. In Synchronous Mode,
the Baud Rate (1 x) is equal to the actual frequency of
RiC. In Asynchronous Mode, the Baud Rate is a
fraction of the actual ~ frequency. A portion of
. the mode instruction selects this factor: 1, 1/16 or
1/64 the 'Axe.
'
For example:
Baud Rate equals 300 Baud, if
Rie equals 300 Hz in the 1x mode;
FrxC equals 4800 Hz in the 16x mode;
AXe equals 19.2 kHz in the 64x mode.,
Baud Rate equals 2400 Baud, if
AXe equals 2400 Hz in the 1x mode;
RxC equals 38.4 kHz in the 16x mode;
~ equals 153.6 kHz in the 64x mode.
Data is sampled into the 8251A on the rising edge of
Axe.
NOTE: In most communications systems, the 8251A
will be handling both the transmission and reception
operations of a single link. Consequently, the
Receive and Transmit Baud Rates will be the same.
Both TxC and RxC will require identical frequencies
for this operation and can be tied togeth~r and connected to a single frequency source (Baud Rate
Generator) to simplify the interface.
RxRDY (Receiver Ready)
This output indicates that the 8251A contains a character that is ready to be input to the CPU. RxRDY can
be connected to the interrupt structurE! of the CPU
or, for polled operation, the CPU can check the condition of RxRDY using a Status Read operation.
RxEnable, when off, holds RxRDY in the Reset Con~
dition. For Asynchronous mode, to set RxRDY, the
Receiver must be enabled to sense a Start Bit and a
complete character must be assembled and transferred to the Data Output Register. For Synchronous
'mode, to set RxRDY, the Receiver must be enabled
and a character must finish assembly and be transferred to the Data Output Register.
Failure to read the received character from the Rx
Data Output Register prior to the ass,mbly of the
next 'RxData character will set overrun condition
error and the'previous character will be written over
and lost. If the Rx Data is being read by the CPU
when the internal transfer is occurring, overrun error will be set and the old character will be lost.
7-159
Figure 5. 8251A Block Diagram Showing
Receiver Buffer and Control Functions
AfN.01573D
inter
8251, A
SYNDET (SYNC Detect!
BRKDET Break Detect)
DETAILED OPERATION DESCRIPTION
General
This pin is used in Synchronous Mode for SYNDET and may be used as either input or output,
programmable through the Control Word. It is reset
to output mode low upon RESET. When used as an
output (internal Sync mode), the SYNDET pin will go
"high" to indicate that the 8251A has located the
SYNC character in the Receive mode. If the 8251A is
programmed to use double Sync characters (bisync), then SYNDETwill go "high" in the middle of
the last bit of the second Sync character. SYNDET is'
automatically reset upon a Status Read Qperation.
When used as an input (external SYNC detect mode),
a positive going signal will cause the 8251A to start
assembling data characters on the rising edge of the
next RxC. Once in SY,NC, the "high" input signal can
be removed. When External SYNC Detect is programmed, Internal SYNC Detect is disabled.
BREAK (Async Mode Only)
This output will go high whenever the receiver
remains low through two consecutive stop bit sequences (including the start bits, data bits, and
parity bits). Break Detect may also be read as- a
Status bit. It is reset only upon a master chip Reset or
Rx Data returning to a "one" state.
I
The complete functional definition of the 8251A is
programmed by the system's software. A set of control words must be sent out by the CPU to initialize
'the 8251A to support the desired communications
format. These control words will program the: BAUD
RATE, CHARACTER LENGTH, NUMBER OF STOP
BITS, SYNCHRONOUS or ASYNCHRONOUS OPERATION, EVEN/ODD/OFF PARITY, etc. In the
Synchronous Mode, options are also provided to
select either internal or external character
synchronization.
Once programmed, the 8251A is ready to perform its
communication functions; The TxRDY output is
raised "high" to signal the CPU that the 8251A is
ready to receive a data character from the CPU. This
output (TxRDY) is reset automatically when the CPU
writes a character into the 8251 A. On the other hand,
, the 8251A receives serial data from the MODEM or
I/O device. Upon receiving an entire character, the
RxRDYoutput is raised "high" to signal the CPU th/it
the 8251A has a complete character ready for the
CPU to fetch. RxRDY is reset automatically upon the
CPU data read operation.
~
The 8251A cannot begin transmission until the Tx
Enable (Transmitter Enable) bit is set in the Command Instruction and it has received a ClearTo Send
(CTS) input. The TxD output will be held in the marking state upon Reset.
\
ADDRESS BUS
A.
J
CONTROL BUS,
I/O R
'L
'i7i5"W
RESET
°2
(TTL)
DATA BUS
8
c/o
os
°1-0 0
RI)
WR
RESET
ciD"
1
MODE INSTRUCTION
ciD =
1
SYNC CHARACTER 1
cio",
1
SYNC CHARACTER 2
' } SYNC MODE
C/D= 1
COMMAND INSTRUCTION
CID '" 0
DATA
ONLY·
COMMAND'INSTRUCTION
ClK
8251A
ciD.,
0
DATA
ciD:
1
COMMAND INSTRUCTION
·TH£" SECOND SYNC ClfARACTER IS SKIPPED IF MODE INSTRucnON HAS PAGo
GRAMMEO THE U51A TO SINGLE CHARACTER SYNC MODE. BOTH SYNC
CHARACTERS ARE SkIPPED IFMOOE INSTRUCTION HAS PROGIJAMMED THE
8251A TO ASVNC MODE.'
Figure 6. 8251A Interface to 8080 Standard
System Bus
Figure 7_ lYpical Data, Block
7-160
AFN-01573D
8251A
the same package. The format definition can be
changed only after a master chip ReSet. For explanation purposes the two formats will be isolated.
Programming the 8251A
Prior to starting data transmission or reception, the
8251A must be loaded with a set of control words
generated by the CPU. These contr'ol signals define
the complete functional definition of the 8251 A and
must immediately follow a Reset operation (internal
or external).
NOTE: When parity is, enabled it is not considered
as one Qf the data bits for the purpose of programmi[1g the 'l\(ord,length.;r,l')e actual parity bit received
on the Rx Data line cannot be read on the Data Bus.
In the case of a programmed character length of less
than 8 bits, the least 'significant Data Bus bits will
hold the dat~; unused bits are "don't care" when
writing data to the 8251 A, and will be "zeros" when
reading the data from the 8251A.
The control words are split into two formats:
1. Mode Instruction
2. Command Instruction
Mode Instruction
Asynchronous Mode (Transmission)
This instruction defines the general operational
characteristics of the 8251 A. It must follow a Reset
operation (internal or external). Once the Mode Instruction has been written into the 8251A by the
CPU, SYNC characters or Command Instructions
may be written.
Whenever a data character is sent by,the CPU the
8251A automatically adds a Start bit (lOW level) followed by the data bits (least significant bit first), and
the programmed number of Stop bits to each character. Also, an even or odd Parity bit is inserted prior '
to the Stop bit(s), as defined by the Mode Instruction. The' character is then transmitted as a serial
data stream on the TxD output. The serial data is
shifted out on the falling edge ofTxC at a rate equal
to 1, 1/16, or 1/64 that of the "'iXC. as defined by the
Mode Instruction. BREAK characters can be continuously sent to the TxD if commanded to do so.
Command Instruction
This instruction defines a word that is used to control
the actual operation of the 8251A.
Both the Mode and Command Instructions must
conform to a specified sequence for proper device
operation (see Figure 7). The Mode Instruction must
be written immediately following a Reset
operation, prior to using the 8251 A for data
communication.
When no data characters have been loaded into the
8251 A theTxD output reamins "high" (marking) unless a Break (continuously low) has been
programmed.
, 0 , 0,
o
.
0
0'3
0
, ,
0
00
I ',1 " 1EP IPEN I L,I L, I B,I B, I
All control words written into 'the 8251A after the
Mode Instruction will load the Command Instruction. Command Instructions can be written into the
8251 Aat any time in the data block during the operation of the 8251A. To return to the Mode Instruction
format, the master ReSet bit in the Command Instruction word can be set to initiate an internal Reset
operation which automatically places the 8251A
back into the Mode Instruction format. Command
Instructions must follow the Mode Instructions or
Sync characters.
~
BAUD RATE FACTOR
1
I
o I
0
0
SYNC
I
'1X)
MODE
I
I
0
1
(16X)
1
1
I
(64X)
I
I
I
CHARACTER LENGTH
o I
o I
BI~S
I
I
1
0
I B:;'S
I
I
0
1
1
1
I
I
1 BI~S--I
BI~S
PARITY ENABLE
1" ENARLE
0= DISABLE
EVEN PARITY GENERATION/CHE CK
0=000
1 = EVEN
NUMBER OF STOP BITS
Mode Instructi'on Definition
o I
1
0
o
1. 0 I
1
1
1
I
I
I
I
I,NVAL,DI BiT I B1~s I BI~' I
The 8251 A can ,be used for either AsynchronQus or
Synchronous data communication. To understand
how the Modelnstructibn defines the functional
operation of the 8251 A, the designer can best v.iew
the device as two separate components" one
Asynchronous and the other Synchronous. sharing
Figure 8. Mode Instruction Format,
Asynchronous Mode '
7-161
AFN.()1573D
intJ
8251A
Asynchronous Mode (Receive)'
Synchronous Mode (Transmission)
The RxD line is normally high. A falling edge on this
line triggers the beginning of a START bit. The
validity of this START bit is checked by again strobing this bit at its nominal center (16X or64X mode
only). If a low is detected again, it is a valid START bit,
and the bit couhter will start counting. The bit coun-·
tar thus locates the center of the data bits, the parity
bit (if it exists) and the stop bits. If parity error occurs, the parity error flag is set. Data and parity bits
are sampled on the RxD pin with the rising edge of
RxC. If a low level is detected as the STOP bit, the
Framing Error flag will be set. The STOP bit signals
the end of a character. Note that the receiver requires only one stop bit, regardless of the number of
stop bits programmed. This c!:Jaracter is then loaded
into the parallel I/O buffer of the 8251 A. The RxRDY
pin is raised to signal the CPLf that a character is
ready to be fetched. If a previous character has not
been fetched by the CPU. the present character
replaces it in the I/O buffer, and the OVERRUN Error
flag is raised (thus.the previous character is lost). All
of the error. flags Ican be reset by an Error Reset
Instruction. The occurrence of any of these errors
will not affect the operation of the 8251A.
The TICD output is continuously high until the CPU
sends its first ch.aracter to the 8251Awhich usually is
a SYNC character. When the CiS line goes low, the
first character is serially transmitted out. All characters are shifted out on the falling edge ofTxC. Data is
shifted out at the same rate as the TxC.
Once transmission has started, the data stream at
the TxD output must continue at the TxC rate. If the
CPU does not provide the 8251A with a data character before the 8251A T~ansmitter Buffers become
empty, the SYNC characters (or character if in single
SYNC character mode) will be automatically inserted in the TxD data stream. In this case, the
TxEMPTY pin is raised high to signal that the 8251A
is empty and SYNC Characters are being sent out.
TxEMPry does not go low when the SYNC is being
shifted out (see figure below). The TxEMPTY pin is
internally reset by a data character being written
into the 8251A.
AUTOMATICAllY INSERTED BY USART
TxD
I
DATA
I
DATA
TxEMPTY _ _ _~/
GENERATED
BrTS
RxD
..IG
__
1L.._8T.;;.:';;..~T:.
t
t
PROGRAMMED
CHARACTER
LENGTH
TRANSMISSION FORMAT
CPU BYTE {5·S BITS/CHARI
~
DATA CHARACTER
I
'--_ _-II ....._ _ _:...-J
ASSEMBLED SERIAL DATA OUTPUT (TxOI
~_~_D_AT_A~CHI-A"_A_CT_ER_~____,--ST~",~
RECEIVE FORMAT
SERIAL DATA INPUT
L-~
____
--I~
__
mxo)
~
__
STOO·
BITS
~~
CPU BYTE (5-8 BITS/CHAR)·
DATA
I
DATA
\..
1-- - --
FALLS UPON CPU WRITING A
/CHARACTER TO THE USART
In this mode, character synchronization can be internally or externally achieved. If the SYNC mode has
been programmed, ENTER HUNT command should
be included in the first command instruction word
written. Data. on the RxO pin is then sampled .on
the rising edge of RxC. The content of the Rx buffer
is compared at every bit boundary with the first
SYNC character un.til a match occurs. If the 8251A
has been programmed for two SYNC characters, the
subsequent received character is also compared;
when both SYNC characters have been detected,'
the USARTends the HUNT mode and is in character
synchronization. The SYNDET pin is then set high,
and is reset autqmatically by a STATUS READ. If
parity is programmed, SYNDETwili not be set until
the middle of the parity bit instead of the middle of
the last data bit.
ST6;i
afrs L
A ")-'T_8:...
DA_Tooi
. ..J-'-:;';:...-J
DATA CHARACTER
SYNC 2
Synchronous Mode (Receive)
L
DOES NOT APPeAR
DO 01---;-0)( ON THE DATA BUS
tt
I
\'\\\\\\\
NOMINAL gENTER OF LAST BIT
STt;i
RECEIVER INPUT
SYNC'
""
'BY8251A
000'---- Ox
I \
I
In the external SYNC mode, synchronization is
achieved by applying a high level on the SYNDET
pin, thus forcing the 8251A out of the HUNT mode.
The high level can be removed after one RxC cycle.
An ENTER HUNT command has no effect in the
asynchronous mode of operation.
C~A~ACTER
"NOTE IF CHARACTER LENGTH IS DEFINED AS 5, 6 OR 7
BITS THE UNUSED BITS ARE SET TO "ZERO"
Figure 9. Asynchronous Mode
7-162
AFN-01573D
inter
8251A
Parity error and overrun error are both checked in
the same way as in the Asynchronous Rx mode.
Parity is Checked when not in Hunt, regardless of
whether the Receiver is enabled or not.
CPU BYTES 16·8 BllS/CHARI
OATA
C~~RACTERS
ASSEMBLED SERIAL DATA OUTPUT IT"OI
0,
0,
0,
0,
0,
0,
IlseslEsol E' '.ENI L,I L, ,
I
I
0,
D.
0 , 0
DATA
I
RECEIVE FORMAT
CHARACTER LENGTH
0
,
0
1
0
0
1
1
5
BITS
•
1
BITS
•
BITS
CHAR"'~AC-T-ER-S---'
SERIAL DATA INPUT IRxO)
BITS
SYNC
SYNC
CHAR 1
CHAR 2
I
OATACH~R:
...CT_ER_S_......J
CPU BYTES 15-8 BITS/CHAR)
;'
DATA CHARACTERS
PARITY ENABLE
11" ENABLE)
(0" DISABLE)
EVEN PARITY GENERATION/CHECK
1 .. eVEN
O~ODD
EXTERNAL SYNC DETECT
1 .. SYNDET IS AN INPUT
Figure 11. Data Format, Synchronous Mode
o= SV",",OET IS AN OUTPUT
SINGLE CHARACTER SYNC
COMMAND INSTRUCTION DEFINITION
1 • SINGLE SYNC CHARACTER
o = DOUBLE SYNC CHARACTER
NOTE' IN eXTERNAL SYNC MODE. PROGRAMMING DOUBLE CHARACTER
SYNC WILL AFFECT ONLY THE Tx.
Once the functional definition of the 8251 A has been
programmed by the Mode Instruction and the sync
characters are loaded (if in Sync Mode) then the
device is ready to be used for data communication.
The Command Instruction controls the actual operation of. the selected format. Functions such as:
Enable Transmit/Receive, Error Reset and Modem
Controls are provid~d by tl')e Command Instruction.
Figure 10. Mode Instruction Format,
Synchronous Mode
The CPU can command the receiver to enter the
HUNT mode if synchronization is lost. This will also
set all the used character bits in the buffer to a
"one," thus preventing a possible false SYNDET
caused by data that happens to be in the Rx Buffer at
ENTER HUNT time. Note that the SYNDET F/F is
reset at. each Status Read, regardless of whether
internal or external SYNC has been· p·rogrammed.
This does not cause the 8251 A to return to the HUNT
mode. When in SYNC mode, but not in HUNT,.Sync
Detection is still functional, but only occurs at the
"known" word boundaries. Thus, if one Status Read
indicates SYNDET and a second Status Read also
indicates SYNDET, then the programmed SYNDET
characters have been received since the previous
Status Read. (If double character sync h!$ been
programmed, then bath sync characters have been
contiguously received to gate a SYNDETJndication.j
When external SYNDET mode is selected, internal
Sync Detect is disabled, and the SYf',IDET F/F may be
set at any bit boundary.
7-163
Once the Mode Instruction has been written into the
8251A and Sync characters inserted, if necessary,
then all further "control writes" (C/O = 1) wiU load a
Command Instruction. A Reset Operation (internal
or external) will return the 8251A to the Mode Instruction format.
Note: Internal Reset on Power-up
When power is first applied, the 8251A may come up
in the Mode, Sync character or Command format. To
guara.ntee that the device is in the Command Instruction format ·before the Reset command is issued, it is safest to execute the worst-case
initialization sequence (sync mode with two sync,
characters). Loading three OOHs consecutively into
the device with C/O = 1 configures sync operation
and writes two dummy OOH sync ch!i1racters. An.lnternal Reset command (40H) may then be issued to
return the device to the "Idle" state.
AfN.01573D
8251A
II
0,
0,
EH
I'A
0,
0,
0,
0,
RTS
ER
ISBRK)
AxE
I I
,,"
0,
0,
OTR
IT.IIENI
I
"Lr
TRANSMIT ENABLE
1 ~ enable
"
0 = disable
LI
DATA TERM'NAL
READY
'high" will force OTR
output to lero
J
I
I
I
dlsd~hle
_I SEND BREAK
CHARACTER
I ~ : ~~rC:IT:~r~~~:
.1l '
ERROR RESET
~ reset error lIags
PE,OE FE
Il.
'I
I
,,'
"
II
,
REQUEST TO
Note:
SE~
INfERNAL RESET
"high' returns 8251 A to
Mode Instruction Format
~oD"
ENTER HUNT
1 = enable search for Sync
Characters
'
D.
D,
FE
OE
PE
I
D,
0,
T'EMPTyl R,RDY
I
D,
T,RDY
~
1 I
SAME DEFINITIONS AS "0 PINS
PARITY ERROR
The PE flag II set when a parity
error IS detected It IS reset by
the ER bit of the Command
Instruction PE does not Inhlbn
operation of the &251A
OVERRUN ERROR
The DE flag IS set when the CPU
C-
does not read a character before
the oelCt one becomes available
It IS reset by the ER blt-of the
Command Instruction oe does
not IOhlblt oper~tton of the 8251 A
however. the previously oytlrrun
character IS lost
FRAMING ERROR (Async only)
The FE flag IS set when a valid
Stop bit IS not detected at the
end of every charact.r It IS reset
by the ER bit of the Command
I
I
I
Instruction FE does not mhlbl1
the operation of the 8251A
DATA SET READV Indicates
that the eSR 'S8t 8 lero level
Note 1
(HAS NO eFFeCT
AS~NC
0,
I
"high" will force RTS
output to lero
IN
D,
SYNDETI
BRKOET
I
I
RECEIVE ENABLE
1 enable
0
0,
DSR
I I I I I I
\
MODE)
TxRDY status bit has different meanings from the
TxRDY output pm· The former IS not conditioned
Ern and TxEN. the latter IS conditioned by both
Ern and TxEN
'
by
~rror Reset must be performed whenev~r RxEnable
and Enter Hunt are programmed.
I.e TxADV status bit
Figl,lre 12. Command .nstruction Format
= DB Buffer Empty
TxRDY Pin out - DB Buffer Empty ·leTS
ITxEN-ll
STATUS READ DEFINITION
01·
Figure 13. Status Read Format
In data communication systems it is often necessary
tb examine the "status" of the active device to ascertain if errors have occ!Jrred or other coriditions that
require the proces~or's attention. The 825"1A has
facilities that allow the programmer to "read" the
status of the device at any time during the functional operation. (Status llpdate is inhibited during
status read.)
APPLICATIONS OF THE 8251A
A I!,..ormal ~'read'! ~ommand is issued by the CPt.! with
C/O = 1 to accol)1plish this function,,'
Some of the bUs in th'e Status Read Format have
identical mea·nings to external output pins·
that
the 8251A can be used "in a' completely polled or
interrupt~driven envi"ronment. TxROY" is an
so
ex~ption.
Note that status "update can have a maximum delay
of 28 clock periods from the actual event affecting
the status.
7-164 '
Figure 14. Asynchronous Serial Interface to CRT
Terminal, DC-960'o B~ud
AFN-015730
inter
8251A
ADDRESS BUS
-'!
CONTROL BUS
_\
DATA BUS
~
1
1
I
1
~~~~~
SYNCHRONOUS
TERMINAL
OR PERIPHERAL
DEVICE
RxD
8251A
SYNDETi----oj
TxD
I--
I----CTS P-
SYNDET
Figure 15. Synchronous Interface to Terminal or
Peripheral Device
1-
f----
IIxll I TxC I -
RTS
p--o
DSR
P-
i5TlI t>----
PHONE
LINE
INTERSYNC
MODEM
t--
I-
fACE
t
TELEPHONE
LINE
ADDRESS BUS
11
\
1
1
Figure 17. Synchronous Interface to Telephone
Unes
i
CONTROL BUS
DATA BUS
~JB~
RxD
TxD
I--
PHONE
DSR 1'-
ASVNC
LINE
I'--
MODEM
INTER·
FACE
DfR
8251A
r--
~
t--
CTS ~
FiTS I'--
RiC
fie
R
BAUD
RATE
GENERATOR
t
TELEPHONE
LINE
Figure 16. Asynchronous Interface to Telephone
Lines
7-165.
intJ
8251A
ABSOLUTE MAXIMUM RATINGS"
Ambient Temperature Under Bias .......... O"C to 70·C
Storage Temperature r ••••••••••••••• -65·C to +150~C
Voltage On Any Pin
With RespectTo Ground ............. -0.5V to + 7V
Power DisSipation ............................. 1 Watt
,D.C. CHARACTERISTICS
Symbol,
(TA
'NOTICE: Stresses above those listed under "Absolute
Maximum RatIngs" may cause permanent damage to the
device. This Is a stress rating only and functional operation
of the device at these or any other COnditions above those
Indicated In the operational sections of this specification
Is not Implied. Exposure to absolute maximum rating con·
ditions for extended periods may affect device reliability.
=O·C to 70·C, Vee =5.0V ± 5%, GND =OV)'
Parameter
Min.
Max.
0.8,
VIL
Input Low Volta.ge
-0.5
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
Unit
V
Vee
V
0.45
V
2.4
V
IOFL
Output Float Leakage
±10
IlL
Input Leakage
±10
,...A
Icc
Power Supply Current
100
mA
CAPACITANCE
(TA
Test ,Conditions
,...A
= 2.2mA
= -400,...A
voiJT = Vee TO 0.45V
VIN = Vee TO 0.45V
All Outputs = High
IOL
IOL
= 25·C, Vee = GND = OV)
Symbol
Max.
Unit
CIN
Input Capacitance
Parameter
10
pF
fc = 1MHz
Glib
1/0 Capacitance
20
pF
Unmeasured pins returned
to GND
A.C. CHARACTERISTICS
Bus Parameters (Note 1)
(TA
Min.
Test Conditions
= o·c to 70·C, Vee = 5.0V ±100/0, GND = OV) ,
READ CYCLE
Symbol
Parameter
Min.
tAR
Address Stable Before READ (CS, C/D)
tRA
Address Hold Time for READ (CS, C/D)
tRR
READ Pulse Width
tRO
Data Delay from READ
tOF
READ to Data Floating
Max.
Unit
Test Conditions
0
ns
Note 2
0
ns
Note 2
250
ns
200
ns
10
100
ns
Min.
Max.
Unit
3, CL
= 150pF
WRITE CYCLE
Symbol
Parameter
tAW
Address Stable Before WRITE
,
0
ns
tWA
Address Hold Time for WRITE
0
ns
tww
WRITE Pulse Width
250
ns
tow
Data Set·Up Time for WRITE
150
ns
two
Data Hold Time for WRITE
20
ns
tRY
Recovery Time Between WRITES
6
tey
, 7·166
Test Condtions
.
Note 4
AFN-01573D
8251A
A.C: CHARACTERISTICS (Continued)
OTHER TIMINGS
Symbol
Parameter
Min.
Max.
Unit
tCY'
Clock Period
320
1350
ns
tp
Clock High Pulse Width
120
tCy-90
ns
t.U
Clock Low Pulse Width
90
tR, tF
Clock Rise and Fall Time
tOTx
TxD Delay from Falling Edge of TxC
fTx
Transmitter Input Clock Frequency
lx Bau(l Rate
16x Baud Rate
64x Baud Rate
DC
DC
DC
Transmitter Input C,lock Pulse Width
1x Baud Rate ,
l6x and 64x Baud Rate
12
1
tCY
tCY
Transmitter Input Cldck Pulse Delay
lx Baud Rate
16x and 64x Baud Rate
15
3
tCY
tCY
Receiver Input Clock Frequency
lx Baud Rate
16x Baud Rate
64x Baud Rate
DC
DC
DC
Receiver Input Clock Pulse Width
lx Baud Rate
16x and 64x Baud Rate
12
1
Receiver Input Clock Pulse Delay
1x Baud Rate·
l6x and 64x Baud Rate
15
3
tTPW
tTPO
f Rx
tRPw
tRPO
tTxROY
TxRDY Pin Delay from Center of Last Bit
tTxROY CLEAR
TxRDY ~ from Leading Edge of WR
tRxROY
tRxROY CLEAR
Test Conditions
Notes 5, 6
ns
20
ns
1
",s
64
310
615
kHz
kHz
kHz
64
310
615
kHz
kHz
kHz
tCY
tCY
tCY
tCY
8
tCY
Note 7
400
ns
Note 7
RxRDY Pin Delay from Center of Last Bit
26
tCY
Note 7
RxRDY ~ from Leading Edge of RD
400
ns
Note 7
tiS
Internal SYNDET Delay from Rising
Edge of RxC
26
tCY
Note 7
tES
External SYNDETSet-Up Time After
Rising Edge of RxC
18
tCY
Note 7
tTxEMPTY
TxEMPTY Delay from Center of Last Bit
20
tCY
Note 7
twc
Control Delay from Ris1!:!.2. Edge of
WRITE (TxEn, DTR, RTS)
8
tCY
Note 7
tCR
Control to READ Set-Up Time (DSR, CTS)
20
tCY
Note 7
'NOTE:
1. For Extended Temperature EXPRESS, use M8251 A electrical parameters.
7-167
AFN.()1573D
8251 A
A.C. CHARACTERISTICS (Continued)
NOTES:
1. AC timings measured VOH = 2.0 VOl = 2.0, VOL = 0.8, and with load circuit of Figure 1.
2. Chip Select (CS) and COmmand/Data (C/O) are considered as Addreases.
3. Assumes that Address is valid before RD~.
4. This recovery time is for. Mode Initialization only. Write Data is allowed only when TxROY = 1. Recovery Time between
Writes for Asynchronous Mode Is 8 tCY and for Synchronous Mode is 16 tCY. .
5. The TxC and RxC frequencies have the following limitations with respect to ClK: For 1x Baud Rate, fTx or fRx ..; 1/(30
tCY):
For 16x and 64x Baud Rate, fTx or fRx ..;1/(4.5 tCY).
6. Reset Pulse Width = 6 tCY minimum; System Clock must be running during Reset.
7. Status update can have a maximum delay of 28 clock periods from the event affecting the status.
"
TYPICAL A OUTPUT DELAY VS. A CAPACITANCE (PF)
+20
/
+10
!
>
Sw
0
I-
~::>
.,
0
-10
-20
-100
/
/
/
/
"'-SPEC.
0,
+50
+100
.1 CAPACITANCE (.F)
A.C. TESTING INPUT, OUTPUT WAVEFORM,
A.C. TESTING LOAD CIRCUIT
INPUT/OUTPUT
o
--:--~
~
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC ,'AND 0 45V FOR
A LOGIC 0" TIMING MEASUREMENTS ARE MADE AT 2 OV FOR II LOGIC "
AND 0 8V FOR A LOGIC 0"
7-168
A_5730
intJ
8251A
WAVEFORMS
SYSTEM CLOCK INPUT
CLOCK
¢l
TRANSMITTER CLOCK AND DATA
'T)i(!!1x MODE)
~(1exMODEl
Tx DATA
RECEIVER CLOCK AND DATA
IRx BAUD COUNTER STARTS HEREl
Rx DATA
Rxe (lx
MODE~
Rxe (16 MODE)
INT SAMPLING
PULSE
WRITE DATA CYCLE (CPU
~
USART)
'Ww,1
Wi
DON'T CARE
DATA IN (0 B)
CIO
Clr
READ DATA CYCLE (CPU
~
'l.
I~ tTKROY CLEAR
I
TxRDY
1--+~:j'WD
DATA STABLE
~
~
F
~
DON'T CARE
USART)
R,RDY _ _ _ _~/
~
----------{
I}-----"I
DATA OUT (0 B I _ _ _ _D!!!A!.!T~A!;FL~O~A!.T_ _~H~~~~~D~~~~
em -------~~4_-----4_~~--
7-169
AFN-01573D
8251A
WAVEFORMS (Continued)
WRITE CONTROL OR OUTPUT PORT CYCLE (CPU ~ USART)
m,rn
INOTE =11
l
ww
=--x
_1 t'wc::.!
1-1---1
'ow - ::I'WO'
Wi
. DATA IN {OBI
I~
CID
It
os
'I,
I--i 'WA
'AW
"'
1-- 'AW HtWA
1
READ CONTROL OR INPUT PORT (CPU - USART)
DSR,CTS
/NOTE::-2)
Ad
1- tc"-==J ~ 'RR-1
~
~ I-'RO
OAT'A OUT
(o.B)
-I'AR
-
- 'RAr--
~
~
JI
CID
~'AR-
os
'OF
-'RAk=--
,X
NOTE..,.1 Twc INCLUDES THE RESPONSE TIMING OF A CONTROL BYTE.
NOTE :2 TCR INCLUDES THE EFFECT OF eTS ON THE TxENBL CIRCUITRY,
I
TRANSMITTER CONTROL AND FLAG TIMING (ASYNC MODE)
•
tTKEMPTV
TIC EMPTY
TxDATA
------,....----------t---:----i
-------~tcODoaJl~tLOCoaoaJOJJ)l]XT~OOoa1Xxi~-----~J)Jl~_~DATA CHAR 1
DATA CHAR 2
DATA CHAR 3
'Oo.-NM'IIt.tHD
=:
I- DATA CHAR 4
0:,..
E)(AMPLE FORMAT" 7 BIT CHARACTER WITH PARITY & 2 STOP BITS
7-170
~;§
~
I!;
t;
AFN-015730
inter
8251A
WAVEFORMS (Continued)
RECEIVER CONTROL AND FLAG TIMING (ASYNC MODE)
'''~',:~:;::~ ------~----r-t_I-___,--
" ---;!''''''
_~=======~--:--=--=-:-=--=--_---hlttll~v+__f--I ,---+-_+--____~'-i+-_--"'!.I~
w,
~~~~.p."~,,~,,~"t---1-~~~l-~~~~---'----------,,-,,-lt,,,-,,-,--------
U"'''hn
i;
TRANSMITTER CONTROL AND FLAG TIMING (SYNC MODE)
m~~-----------r--------~'~
r.
READY
,.-
r'--',- t~
------I---~~
ISTATUSSITI
TxREAOY
lPINI_
~,---~
'---
T'---~
1,.-
In
r\......Jl-
W'i~:KMAIllO
A
~~'i~T: ~H~~~t:
~
~~r;.~T:
~
~~~:Tt
W'~::~AND
'7,w;;;~:;!;.,:,,,,:Cft-----+--------
;T~'~,!~I':~--f--DA-'-A-t'sr"',\~~~~~~~~f-I'"\HIA"I':~,\-+--DA-'+A,,--1-M-A'5·'~~~'NGJtji~,·tl'::,~*----+--'------
w.
l
\8-1
MARKING STAlE
c~:
I
CHAR 2
CHAR 1
SYNC CHAR 2
CHAR 4 ""
s:~l s::;~ IM~~i'
EXAMPLE FORMAT· ft81T CHARACTER WITH PARITY 2 SYNC CHARACTERS
RECEIVER CONTROL AND FLAG TIMING (SYNC MODE)
SYNDET
IPININOH
1
'15 _ _
~~OTE3.....J
-
tES_
''----
OVERRUN
ERROR ISB)
r-
t-'
''----
,--
~
LOST
\
Jr~'"' J~
" ~::i:
RdDATA
CHAR 1
--V
CHAR J
SYNC
SYNC
DATA
CARE
CHAR I
CHAR 2
CHAR 1
b t -1-
[1••
•
•
~
U
1
?
J
• .:
U
1
•
)
•
DATA
CHAR 2
c . ' l l ' c.' 13'
}!-llJASsr;;UsT
TfTlllTTTTITT
JlJ1fU1J
RxCLOCK
L
r-roTE
Non
CHARl
u,., •
TTTTT
CHAR 1
.
\...
r-
Rd DATA
nlJ
SYNC CHAR 2
c., l l . c_'
EXIT HUNT MODE
SET SYNC DET
Rd:,T::~S
-- r-<
RdSTATUS
CHAR 1
>---
DONT
r ---
I,.
DATA
CHAR 1
DON T CA'U
•
~
•
x
~
••
x.'"
-DATA \..
CHAR 2
Irno
• cO, 1 ) ' c
ru- 'H"~
8EGINS
J1J
EXIT HUNT MODE
SET SYN Del ISTATUS Bm
I
1 INTERNAL SYNC 2 SYNC CHARACTERS S81TS WITH PARITV
2 [XHRNAL SYNC 5 BITS WITH PARITV
AFN-01573D
7-171
8273, ,8273-4
PROGRAMMABLE HDLC/SDLC PROTOCOL
CONTROLLER
• CCITT X.25 Compatible
• Programmable NRZI Encode/Decode
Two User Programmable Modem
• Control
Ports
Digital Phase Locked Loop Clock
• Recovery
• Minimum CPU Overhead
Compatible with, 804$/808Q/80851
• FUllY
8088/8086/80188/80186 CPUs
• HDLC/SDLC Compatible
Full Duplex, Half Duplex, or Loop
• SDLC
Operation
Up to 64K Baud Synchronous
• Thmsfers
(56K Baud with 8273-4)
Automatic FCS (CRC) Generation and
• Checking
to 9.6K Baud with On· Board Phase
• Up
Locked Loop
• Single +5V Supply
The Intel@ 8273 Programmable HOLC/SOLC Protocol Controller is a dedicated device designed to support the 1501
CCITTs HOLC and IBM's SOLC communication line protocols. It is fully compatible with Intel's new hiQh performance
microcomputer systems such as the MCS1 88/186'·. A frame level command set is achieved by a unique microprogrammed
dual processor chip architecture. The processing capability supported by the 8273 relieves the sYl>tem CPU of the low
level real·time tasks normally associated with-controllers.
Fi:A'G'1iEf
08 0- 7
T.D
r;c
DPLL
Vee
Tx tNT
~
elK
PB3
RESET
PII2
TxDACK
;;a;
TxORQ
m
RxDACK
PA,
RxORO
PA,
AD
PA2
w-
CD
Rx INT
rn
RTs
DBO
T,O
PB,-4
OBI
TiC
ffi
£ci
DB2
RiC
DBl
R,D
PA 2_ 4
DB'
32iC[j(
DBS
Cs
32X elK
DPlL
R,D
DB7
A,
GND
An
R;c
F'l.AGDET
Figure 2. Pin Configuration
Figure 1. Block Diagram
Intel Corporation Assumes No Responsibilty for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product No Other CirCUit Patent Licenses a..,e Implied
© INTEL CORPORATION, 1982
\
7-172
NOVEMBER 1983
ORDER NUMB.R 211)479-002
intJ
8273, 8273·4.
types of frames; an Information Frame is used to transfer
data, a Supervisory Frame is used for control purposes,
and a Non-sequenced Frame is used for initialization and
control of the secondary stations.
A BRIEF OESCRIPnON OF HOLC/SOLC
PROTOCOLS
General
The High Level Data Link Control (HOLCl is a standard
communication link protocol established by International
Standards Organization (ISOl. HOLC is the 'discipline
used to implement ISO X.25 packet switching systems.
The Synchronous Data Link Control (sOLCl is an IBM
communication link protocol used to implement the
System Network Architecture (SNAl. Both the protocols
are bit oriented, code independent, and ideal for full
duplex communication. Some common applications
include terminal to terminal, terminal to CPU, CPU to
CPU, satellite communication, packet switching and other
high speed data links. In systems which require expensive
cabling and interconnect hardware, any of the two
protocols could be used to simplify interfacing (by going
seriall, thereby reducing interconnect hardware costs.
Since both the protocols are speed independent, reducing
interconnect hardware could become an important
application.
Network
Il'tboth tf'Ie HOLC and SOLC line protocols, according to a
pre-assigned hierarchy, a PRIMARY (Controll STATION
controls the overall network (data linkl and issues
commands to the SECONDARY (Slavel STATIONS. The
latter comply with instructions and respond by sending
appropriate RESPONSES. Whenever a transmitting
station must end transmission prematurely it sends an
ABORT character. Upon detecting an abort character, a
receiving station ignores the transmission block called a
FRAME. Time fill between frames can be accomplished by
transmitting either continuous frame preambles called
FLAGS or an abort character. A time fill within a frame is
not permitted. Whenever a station receives a string of
more that fifteen consecutive ones, the station goes into
an IDLE state.
Frame Characteristics
An important 'characteristic of 'a frame is that its contents are made code transparent by use of a zero bit
insertion and deletion technique. Thus, the user can adopt
any format or code suitable for his system - it may even
be a computer word length or II "memory dump". The
frame is bit oriented that is, bits, not characters in each
field, have specific meanings. The Frame Check
Sequence (FCS) is an error detection scheme similar to
the Cyclic Redundancy Checkword (CRCl widely used in
magnetic disk storage devices. The Command and
Response information frames contain sequence numbers
in the control fields identifying the sent and received
frames. The sequence numbers are used in Error
Recovery Procedures (ERP) and as implicit acknowledgement of frame communication, enhancing the true fUIIduplex nature of the HOLC/SOLC protocols.
In contrast, BISYNC is basically half-duplex (two way
'alternate) because of necessity to transmit immediate
acknowledgement frames. HOLC/SOLC therefore saves
propagation delay times and have a potential of twice the
throughput rate of BISYNC.
It is possible to use HOLC or SOLC over half duplex lines
but there is a corresponding loss in throughput because
both are primarily designed, for full-duplex communication. As in any synchronous system, the bit rate is
determined by the clock bits supplied by the modem,
protocols themselves are speed independent.
A byproduct of the use of zero-bit insertion-deletion
technique is the non-return-to-zero invert (NRZI) data
transmission/reception compatibility. The latter allows
HOLC/SOLC protocols to be used with asynchronous
data communication hardware .in which the clocks are
derived from the NRZI encoded data.
References
Frames
IBM Synchronous DatB Lmk. Control General Information, IBM.
A single communication element is called a FRAME which
can be used for both Link ContrQI and data transfer
purposes. The elements of a frame are the beginning eight
bit FLAG (Fl consisting of one zero, six onjilS, and a zero,
an eight bit ADDRESS FIELD (Al, an eight bit CONTROL
FIELD (cl, a variable (N-bitlINFORMATION FIELD (Il, a
sixteen bit FRAME CHECK SEQUENCE (FCSl, and an
eight bit end FLAG (Fl, having the same bit pattern as the
beginning flag. In HOLC the Address (Al and Control (Cl
bytes are extendable. The HOLC and the SOLC use three
OPENING
FLAG (FI
01111110
ADDRESS
FIELD (A)
BBITS
CONTROL
FIELD (C)
SBITS
GA27~
3093-1.
Standard Network Access Protocol Specification, OATAPAC, TransCanada Telephone System CCG111
Recommendation X.25. ISOICCITT March 2. 1976.
IBM 3650 Retail Store System Loop Interface OEM Information, IBM. GA
27-3098-0
GUidebook to Data Communications, Training Manual, Hewlett-Packard
5955-1715
IBM Introduction to Teleprocessing, IBM, GC 20-.8095-02
System Network Architecture, Techmcal OverView, IBM. GA 27-3102
System Network Architecture Format and Protoco', IBM GA 27-3112
INFORMATION
FIELD (I) .
FRAME CHECK
SEOUENCE (FCS)
CLOSING
FLAG (F)
VARIABLE lENGTH
(ONLY IN I FRAMES)
16 BITS
01111110
Figure 3. Frame Format
7-173
AFN-00743C
inter
8273, 8273-4
Table 1. Pin Description
Symbol
Pin
No. Type
Vcc
40
GND
20
RESET
Name and Function
Symbol
Pin
No. Type
Power Supply: +5V Supply.
32X ClK
25
I
32)( Clock: The 32X clock is used to
provide clock recovery when an
asynchronous modem is used. In
loop configuration the loop station
can run without an accurate 1X clock
by using the 32X ClK in conjunction
with the DPll output. (This pin must
be grounded when not used.)
DPll
23
0
Digital Phase Locked Loop: Digital
Phase locked loop output can be
tied to RxC and/or TxC when 1X clock
is not available. DPLL is used with
32X ClK.
1
0
Flag Detect: Flag Detect signals that
a flag (01111110) has been received
by an active receiver.
Ground: Ground.
Name and Function
4
I
Reaet: A high signal on this pin will
force the 8273 to an idlit state. The
8273 will remain idle until a command
is issued by the CPU. Th'e modem
interface output signals are forced
high. Reset must be true for a
minimum of 10 TCY.
CS
24
I
Chip Select: The RD and WR inputs
are enabled by the chip select input.
DB7-DBo
1912
I/O
Data Bus: The Data Bus lines are bidirectional three-state lines which interface with the system Data Bus.
FLAGDET
10
I
Write Input: The Write signal is used
to control the transfer of either a
command or data from CPU to the
8273.
RTS
35
0
Request to Send: Request to Send
Signals that the 8273 is ready t~ transmit data.
CTS
30
I
Clear to Send: Clear to Send Signals
that the modem is ready to accept
data from the 8273,
CD
31
I
Carrier Detect: Carrier Detect signals that the line transmission has
started and the 8273 may begin to
sample data on RxD line,
PA'-4
,3234
I
General purpose Input ports: The
logic levels on, these lines can be
Read by the CPU through the Data
Bus Buffer.
PB'-4
3639
0
General Pl!rpose output ports: The
CPU can 'write these output lines
through Data Bus Buffer.
ClK
3
I
Clock: A ,square wave TTL clock.
WR
RD
9
I
Read Input: The Read signal is used
to control the transfer of either a data
byte or a status word from the 8273
to the CPU.
TxlNT
2
0
Transmitter Interrupt: The Transmitter interrupt signal indicates that
the transmitter logic requires service.
RxlNT
11
0
Receiver Interrupt: The Receiver
interrupt signal indicates that the Receiver logic requires service.
6
0
Transmitter Data Request: Requests a transfer of data between
memory and the 8273 for a transmit
operation.
TxDRQ
RxRDQ
8
0
Receiver DMA Request: Requests a
transfer of data between the 8273 and
memory for a receive operation.
TxOACK
5
I
Transmitter DMA Acknowledge:
The Transmitter DMA acknowledge
signal notifies the 8273 that the
TxDMA cycle has been granted.
7
I
Receiver DMA Acknowledge: The
Receiver DMA acknowledge sigl)al
notifies the 8273 that the RxDMA
cycle has been granted.
A,-An
2221
I
Address: These two lines are CPU
Interface Register Select lines.
TxD
29
0
Transmitter Data: This line transmits the serial data to the communication channel.
TxC
28
I
Transmitter Clock: The transmitter
clocl< is used to synchronize the
transmit data.
RxDACK
,-
.
RxD
26
I
Receiver Data: This line receives
serial data from the communication
channel.
RxC
27
I
Receiver Clock: The Receiver Clo,ck
is used to synchronize the receive
data,
FUNCTIONAL DESCRIPTION
General
The Intel@ 8273 HOlC/SOLC controller is a microcomputer peripheral device which supports the International
Standards Organization (ISO) High Level Oata Link
Control (HOLC). and IBM Synchronous Data Link Control
(SOLC) communications protocols. This controller
minimizes CPU software by supporting a comprehensive
frame-level inst~uction set and by hardware implementation of the low level tasks associated with frame
assembly/disassembly and data integrity. The 8273 can be
used in either synchronous or asynchronous applications.
In asynchronous applications the data can be programmed to be encoded/decoded in NRZI code. The clock is
derived from the NRZI data using a digital phase locked
loop. The 'data transparency is achieved by using a zerobit insertion/deletion technique. The frames are automatically,checked for errors during reception by verifying the
Frame Check Sequence (FCS); the FCS is automatically
generated and appended before the final flag in transmit.
7-174
AFN-00743C
8273, 8273·4
The 8273 recognizes and can generate flags (01111110'
Abort, Idle, and GA (EOP) characters.
The 8273 can assume either a primary (control) or a
secondary (slave) role. It can therefore be readily
implemented in an SOLe loop configuration as typified by
the laM 3650 Retail Store System by programming the
8273 into a one-bit delay mode. In such a configuration, a
two wire pair can be effectively used for data transfer
. between controllers and loop stations. The digital phase
locked loop output pin can be used by the loop station
without the presence of an accurate Tx clock.
A1
Ao Ti6ACR iIiilim eI Iili
0
0
0
0
1
1
1
1
X
X
0
0
1
1
1
1
0
0
1
1
1
1
1
1
1
X
X
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
~
Register
0
1
0
1
0
Command
Status
Parameter
Result
Reset
TxlNT Result
l'
1
1
0
1
0
1
0
1
0
-
RxlNT Result
Transmit Data
Receive Data
Register Description
CPU Interface
The CPU interface is optimized for the MCS-80/85'· bus
with an 8257 DMA controller. However, the interface is
flexible, and allows either DMA or non-DMA data
transfers, interrupt or non-interrupt driven. It further
allows . maximum line utilization by providing early
interrupt mechanism for buffered (only the information
field can be transferred to memory) Tx command overlapping. It also provides separate Rx and Tx interrupt
output channels for efficient operation. The 8273 keeps
the interrupt request active until all the associateq
interrupt results have been read.
The CPU utilizes the CPU interface to specify commands
and transfer data. It consists of seven registers addressed
via CS, A1, Ao, RD and WR signals and two independent
data registers for receive data and transmit data. A1, Ao are
generally derived from two low order bits of the address
bus. If an 8080 based CPU is utilized, the AD and WR
signals may be driven by the 8228 1I0R and I/OW. The
table shows the seven register select decoding:
REGISTERS
Command
Operations are initiated by writing an appropriate •
command in the Command Register.
Parameter
Parameters of commands that require additional information are written to this register.
Result
Contains an immediate result describing an outcome of an
executed command.
Transmit Interrupt Result
Contains the outcome of 8273 transmit operation
(good/bad completion!.
Receive Interrupt Result
Contains the outcome of 8273 receive operation (good/
bad completion), followed by additional results which detail the reason for interrupt.
Status
The status register reflects the state of the 8273 CPU
Interface.
DMA Data Transfers
The 8273 'CPU interface supports two independent data
interfaces: receive data and transmit data. At high data
transmission speeds the data transfer rate of the 8273 is
great enough to justify the use of direct memory a.ccess
(DMA) for the data transfers. When the 8273 IS configured
in DMA mode, the elements of the DMA Interfaces are:
TxDRQ: Transmit DMA Request
Requests a transfer of data between memory and the
8273 for a transmit operation
TxDACK: Transmit DMA Acknowledge
The TxDACK signal notifies the 8273 that a transmit DMA
cycle has been granted. It is also used with \'VR to transfer
data to the 8273 in non-DMA mode. Note: RD must not be
asserted while TxDACK is active.
INTERNAL DATA BUS -
CPU INTERFACE
MODEM INTERFACE
Figure 4. 8273 Block Diagram Showing CPU
Interface Functions
RxDRQ: Receive DMA Request
Requests a transfer of data between the 8273 and memory for a receive operation.
7-175
AFN-l10743C
inter
8273, 8273-4,
RxDACK: Receive DMA Acknowledge
The RxDACK signal notifies the 8273 that a receive DMA
cycle has been granted. It is also used with RD'to read
data fro,m the 827al!!..n2!:!::PMA mode. Note: WR must not
be asserted while RxDACK is active.
REGISTERS
RD, WR: R~d, Write
The AD and WR signals are used to specify the direction of
the data transfer.
DMA transfers require the use of a DMA controller such as
the Intel 8257. The function of the DMA controller is to
provide sequential addresses and timing for the transfer,
at a starting address determined by the CPU. Counting of
data block le('gths is performed by the 8273.
080-7
TxD
iXc
To request a DMA transfer the 8273 raises the appropriate.
DMA REQUEST. DMA ACKNOWLEDGE and READ enab,!es DMA data onto the bus (independently of CHIP
SELECT). DMA ACKNOWLEDGE and WRITE transfers
DMA data to the 8273 (independent of CHIP .SELECT).
Pa,-.
ill
It is also possible to configure the 8273 in the non-DMA
data transfer mode. In this mode the CPU module must
pass data to the 8273 in response to non-DMA data requests indicated by the status word.
ilA 2_ 4
. . . - - - . . _ - R,D
Modem Interface
R;c
The 8273 Modem interface provides both dedicated and
user defined modem control functions. All the control
signals are active low so that EIA RS-232C inverting
drivers (MC 1488) and inverting receivers (MC 1489) may
be used to interface to standard modems. For asynchronous operation, this Interface supports programmable
NRZI data encode/decode, a digital phase locked loop
for efficient clock extraction from NRZI data, an~
modem control ports with automatic C'fS, CD monitoring and RTS generation. This interface also allows the
8273 to operate in PRE-FRAME SYNC mode in which the
8273 prefixes 16 transitions to a frame to synchronize
idle lines before transmission of the first flag.
CPU INTERFACE
Figure 5. 8273 Block Diagram ShowIng Control
LogIc Functions
It should be noted that all tfie 8273 port operations deal
with logical values, for instance, bit DO of Port A will be a
one when CTS (Pin 30) is a physical zero (logical one).
Port A - Input Port
Port B - Output Port
During normal operation, if the CPU sets RTS active, the
8273 will not change this pin; however, iflhe CPU setsRi'S
inactive, the 8273 will activate it before each transmission
and deactivate it one byte time after transmission. While
the receiver is active the flag detect pin is pulsed each time
a flag sequence is detected in the receive data stream.
Following an 8273 reset, all pins of Port Bare setto a high,
inactive level.
During operation, the 8273 interrogates input pins CTS
(Clear to Send) and CD (Carrier Detect). CTS is used to
condition the start of a transmission. If during transmission eTS is lost the 8273 generates an interrupt. During
reception, if CD is lost, the 8273 generates an interrupt.
~
11
~
~
1 11
,~
~
~
I
~
~
I
I ,I
~
---..l
MODEM INTERFACE
CTS -
IATS -
C,=,!~R TO SEND
REQUEST TO SEND
USER DEFINED OUTPUT PB.t, P83.
CD - CARRIER DETECT
U~E~~EF~~_E~ ~;~T-P~~~---- --
pBz. PB,
I FLAG DETECT
The user defined input bIts correspond. to the 8273 PA.,
PA. and PA,. pins. The 8273 does not interrogate or manipulate these bits.
7-176
The user defined output bits correspond to the state of
PB4-PB, pins. The 8273 does not interrogate or manipulate these bits.
intJ
" 8273, 8273·4.
Serial Data Logic
The Serial data is synchronized by the user transmit (TxC)
and receive (RxC) clocks. The leading edge of TxC
generates new transmit data and the trailing edge of RXC
is used to capture receive data. The NRZI encoding/
decoding of the receive and transmit data is programmable.
circuitry in place of the Rxp pin. thus allowing a CPU to
send a message to itself to verify operation of the 8273.
In the selectable clock diagnostic feature. when the data is
looped back. the receiver may be presented incorrect
sample timing by the external circuitry. The user may
select to substitute the TxC pin for the RxC input on-chip
so that the clock used to generate the loop back data is
used to sample it. Since TxO is generated off the leading
edge of TxC and RxO is sampled on the trailing edge. the
selected clock allows bit synchronism.
The diagnostic features included in the Serial Data logic
are programmable loop back of data and selectable clock
for"the receiver. I n the loop-back mode. the data presented
to the TxO pin is internally routed to the receive data input
TxC
TxD
RxC
RxD
I
/
r-
X
\
X
\
\
)
\
)
\
)
X
I
X
I
X
I
\
X
Figure 6. Transmit/Receive Timing
Asynchronous Mode Interface
Although the 8273 is fully compatible with the HOLC/
SOLC communication line protocols. which are primarily
designed for synchronous communication. the 8273 can
also be used In asynchronous applications by using this
interface. The interface employs a digital phase locked
loop (oPLLl for clock recovery from a receive data stream
and programmable NRZI encoding and decoding data.
The use of NRZI coding with SOLC transmission
of
7-177
guarantees that within a frame. data transitions will occur
at least every five bit times -the longest sequence of ones
which may be transmitted without zero-bit insertion. The
OPLL should be used only when NRZI coding is used
since the NRZI coding will transmit zero sequence as line
transitions. The digital phase locked loop also facilitates
full-duplex and half-duplex asynchronous implementation with. or without modems.
AFN-Q0743C
inter
,'.."
,
8273,8273-4
'~,
,\
Digital Phale Locked Loop
In asynchronous applications, the clock is derived from
the ~eceiver data stream by the use of the digital phase
locked loop (DPLL), The DPLL requires a clock Inputat32
times the required baud rate. The receive data (RxD) is
sampled with this 32X eLK and'the 8273 DPLL supplies a
sample pulse nominally centered on the RxD bit cells. The
DPLL has a built-in "stiffness" which reduces sensitivity to
line noise and bit distortion. This is accomplished by
making phase error' adjustments In discrete increments.
Since the nominal pulse is made to occur at 32 counts of
the 32X CLK, these counts are subtracted or added to the
nominal, depending upon which quadrant ofthefour error
qoadrants the data edge occurs In. For example if an RxD
edge Is detected in quadrant A 1, it is apparent that the
DPLL sample "A" was placed too close to the trailing edge
of the data cell; sample "B" will then be placed at T =
(T nominal - 2 counts), = 30 counts of the 32X'C[j( to move
the sample pulse "B" toward the nominal center of the next
bit cell. A data edge occuring In quadrant B1 would cause
a smaller adjustment of phase with T = 31 counts of the
32X CLK. Using this technique the DPLL pulse will
converge to nominal bit center within 12 data bit times,
worst case, with constant inco!l1ing RxD edges.
A method of attaining bit synchronism following a line idle
is,to use PRE-FRAME SYNC mode of transmission,
RXD_--IX~
DPLL
SAMPLES
___---JX~___~X~__
Ij
~~ I: " ·1· • .j. " ·1· ~ :1
ADJUSTMENT
-2
-1
+1
+2
Figure 7. DPLL Sample Timing
7-178
AFN-00743C
8273, 8273·4
Synchronous Modem - Duplex or Half Duplex Operation
8273
AxC
AxD
TxC
TxD
32xCLK
f
GND
MODEM
,
V'
~
./
RxC
RxD
MODEM
fXc'
8273
TxD
llI'IT
32xCLK
iiPiI
1 l
l
N.C.
GND
N.C.
Asynchronous Modems - Duplex or Half Duplex Operation
8273
MODEM
MODEM
t----+----... AxD
32iCiJ(
DPLL
.' Asynchronous - No Modems - Duplex or Half Duplex
8273
8273
7-179
AFN.()()743C
8273; 8273~4
SOLe Loop
The OPLL simplifies the SOLe loop station implementation. In this application, each secondary station on a loop
data link is a 'repeater s~t in one-~it delay mode. The
.signals sent out on the loop by the loop controller (primary
station) are reiayed from station to station then, back to
the controller. Any secondary station finding its address in
the A field captures the frame for action at that station, All
received frames are relayed to the next station on the loop,
Loop stations are required to derive bit timing from the
incoming NRZI data stream. The OPLL generates sample
Rx clock timing for reception and uses the same clock to
implement Tx ciock timing.
8273
LOOP
CONTROLLER
,...------ITxD
RxDt-----.,
TxC
RxD Rxe
8273
TxD
8273
LOOP
LOOP
TERMINAL
TERMINAL
TxD~-~-------~~--~RxD
FigUN 8. SOLe Loop Application
7-180
AF~43C
intJ
8273, 8273·4
PRINCIPLES OF OPERATION
The 8273 is an intelligent peripheral controller which
relieves the CPU of many of the rote tasks associated with
constructing and receiving frames. It is fully compatible
with the MCS-80/85'" system bus. As a peripheral device,
it accepts commands from a CPU, executes these
commands and provides an Interrupt and Result back to
the CPU at the end of the execution. The communication
with the CPU is done by activation of CS, RD, WR pins,
while the A1, Ao select the appropr~ate registers on the
chip as described in the Hardware Description Section.
YES
The 8273 operation is composed of the following
sequence of events:
CPU WRITES COMMAND AND PARAMETERS INTO THE
8273 COMMAND AND PARAMETER REGISTERS.
NO
T'HE 8273 IS ON ITS OWN TO CARRY OUT THE COMMAND.
THE 8273 SIGNALS THE CPU THAT THE EXECUTION
HAS fIN.lSHED. THE CPU MUST PERFORM A READ
OPERATI,ON OF ONE OR MORE OF THE REGISTERS.
END OF COMMAND PHASE
The Command Phase
During the command phase, the software writes a command to the command register. The command bytes provide a general description of the type of operation requested. Many commands require more detailed information about the command. In such a case up to four
parameters are written into the parameter register. The
flowchart of the command phase indicates that a command may not be issued if the Status Register indicates
that the device is busy. Simi\arly if a parameter is issued
when the Parameter Buffer shows full, incorrect operation
will occur.
The 8273 is a duplex device and both transmitter and
receiver may each be executing a command or passing
results at any given time. For this reason separate
interrupt pins are provided. However, the command register must be used for one command sequence at a time.
Status Register
The status register contains the status of the 8273 activity.
The description is as follows.
0,
0.
I\;
D.
0,
0,
0,
YES
FJgure 9. Command Phase Flowchart
Bit 6 CBF (Command Buffer Full)
Indicates that the command register is full, it is reset when
the 8273 accepts the command byte but does not imply
that execution has begun.
Bit 5 CPBF (C!)mmand Parameter Buffer Full)
CPBF is set when the parameter buffer is full, and is reset
by the 8273 when it accepts the parameter. The CPU may
poll CPBF to determine when additional parameters may
be written.
"0
@SYTCBf Ie"SF leRsF IR.INT ITxINT IR.IRA IT.IRA I
Bit 7 CBSY (Command Busy)
Indicates in-progress command, set for CPU poll when
Command Register is full, reset upon command phase
completion. It is improper to write a command when CBSY
is set; it results in' incorrect operation.
7-181
Bit 4 CRBF (Command Result Buffer Full)
fndicate.s that an executed command immediate result is
present in the Result Register. It is set by 8273 and reset
when CPU reads the result.
AFN-Q0743C
inter
8273, 8273-4
• Bit 3 RxlNT (Receiver Interrupt)
Th. Execution Pha••
RxlNT Indicates that the receiver requires CPU attention.
It is identical to RxlNT (pin 11) and Isset by the 8273 either '
upon good/bad completion of a specified command or by
Non-DMA data transfer. It is reset only after the CPU has
read the result byte or has received a data byte from the
8273 in a Non-DMA data transfer.
Upon accepting the lallt,parameter, the 8273 er;lters Into
the Execution Phase. The ex!!cution phase may consist
of a DMA or other activity, and mayor may not require
CPU Intervention. The CPU Intervention is eliminated In
this phase if. the system utilizes DMA for the data trans·
fers, otherwise, for non-DMA data transfers, the CPU is
Interrupted by the 8273 via TxlNT and AxlNT pins, for
each data byte request.
Bit 2 TxlNT (Transmitter Interrupt)
The TxlNT indicates that the transmitter requires CPU
attention. It ,is identical to TxlNT (pin 2). It is set by 8273
either upon good/bad completion of a specified command
or by Non-DMA data transfer. It is reset only after the CPU
has read the result byte or has transferred transmit data
byte to the 8273 in a Non-DMA transfer.
Tha R••ult Pha••
During the result phase, th' 8273 notifies the CPU of the
execution outcome of a command. This phase is initiated
by:
Bit 1 RxlRA (Receiver Interrupt Result Avelleble)
The RxlRA Is set by the 8273 when an interrupt result
byte is placed in the RxlNT register. It is reset after the
CPU has read the RxlNT register.
1. The successful completion of an operation
2. An error detected during an oP!lration.
Bit 0 TxlRA (Transmitter Int~rruPt Result Available)
To facilitate quick network software decisions, two types
of execution results are provided: ,
The TxlRA is set by the 8273 when an Interrupt result
byte Is placed in the TxlNT register. It is reset when the
CPU has read the TxlNT register.
{
.
Y
Dr lit
All 8 bits recelved
00 recalved
o
0,-00 received
DrOo recolved
~-Oo received
D4-00 received,
05-00 received
1. An Immediate Result
2. A Non-Immediate Result
DS D4
•
_
De-Oo received
0
0
'0
Da liz
D,
0
0
0
0
0
Do _ .... Interrupt RUIIII Code
0
0
0
Active
CRe error
Activo
Activo
Disobled
Abert detected
Idle detect
0
EOP detected
0
0
Frame lesa than 32 bits
DMA
o
overrun detected
Memory buffer overflow
o
'0
carrier de.act failure
• Partial Byte Received
Rx SU"', Allor INT
A1 match or general reoelve
A2 match
Receive Interrupt overrun
Active
Dloobled
Active
DI••bled
Dloabled
Dloabled
Dllobled
Figure 10. Rx Interrupt Re.ult Byte Format
06
o
0,
02
Os
DO
o
D4
D3
02
01
Do
a
Early transmlt,lnterrupt
Frame tnnsmrt complete
OMA underrun
Clear to Send leTS) error
Abort complete
Figure 11. 'IX Interrupt Result Byte Format
7-182
AFN-00743C
intJ
8273, 8273-4
Immediate result is provided by the 8273 for commands
such as Read Port A and Read Port B which have
information (CTS, CO, RTS, etc.) that the network
software needs to make quick operational decisions.
condition for the interrupt and, if required, one or more
bytes which detail the condition.
Tx and Rx Intarrupt Result Registers
The Result Registers have a result code, the three high
order bits 07-05 of which are set to zero for all but the
receive command. This command result contains a count
that indicates the numberof bits received in the last byte. If
a partial byte is received, the high order bits of the last data
byte are indeterminate.
A command which cannot provide an immediate result will
generate an interrupt to signal the beginning of the Result
phase. The immediate results are provided in the Result
Register; all non-immediate results are available upon
device interrupt, through Tx I nterrupt Result Register
Txl/R or Rx Interrupt Result Register Rxl/R. The result
may consist of a one-byte interrupt code indicating the
All results indicated in the command summary must be
read during the result phase.
r----
N~~g~A
I
I DMA
I MODE
I
READ STATUS
I
REGISTER
I
I
I
NO
I
I
READ STATUS
REGISTER
DATA REOUEST
NON·DMA MODE
USE DACK + AD OR
WR TO READ OR
WRITE DATA
(
END)
Figure 12. Result Phase Flowchart-Interrupt Results
7-183
AFN.oo743C
8273, 8273·4
IMMEDIATE RESULTS
---
AFTER COMMAND PHASE COMPLETION (READ PORT A. PORT B)
.....
READ RESULT
REGISTER
FIgure 13. (Rx Interrupt Service)
7-184
8273, 8273-4
DETAILED COMMAND DESCRIPTION
Initialization Set/Reset Commands
General
These commands are used to manipulate data within the
8273 registers. The Set commands have a single parameter which is a mask that corresponds to the bits to be set.
(They perform a logical-OR of the specified register with
the mask provided as a parameter!. The Register
commands have a single parameter which is a mask that
has a zero in the bit positions that are to be reset. (They
perform a logical-AND of the specified register with the
mask),
The 8273 HOLC/SOLC controller supports a comprehensive set of high level commands which allows the 8273 to
be readily used In full-duplex, half-duplex, synchronous,
asynchronous and SOLC loop configuration, with or
without modems. These frame-level commands minimize
CPU and software overhead. The 8273 has address and
control byte buffers which allow the receive and transmit
commands to be used in buffered or non-buffered modes.
Set
In buffered transmit mode, the 8273 transmits a flag
automatically, reads the Address and Control buffer
registers and transmits the fields, then via OMA, it fetches
the information field. The 8273, having transmitted the
information field, automatically appends the Frame Check
Sequence (FCS) and the end flag. Correspondingly, in
buffered read mode, the Address and Control fields are
stored in their respective buffer registers and only
Information Field is transferred to memory.
One~BIt
Delay (CMD Code A4)
~
~
~
~
~
~
~
~
~
~
:::'1 :I: I:' I: I:I: I:I:I: I: I
In non-buffered transmit mode, the 8273 transmits the
beginnin.g flag automatically, then fetches and transmits
the Address, Control and Information fields from the
memory, appends the FCS character and an end flag. In
the non-buffered receive mc1de the entire contents of a
frame are sent to memory with the exception of the flags
and FCS.
When one bit delay is set, 8273 retransmits the receivea
data stream one bit delayed, This mode is entered at a
receiver character boundary, and should only be used by
Loop Stations,
Re..t One-Bit Delay (CMD Code 64)
~
~
~
~
~
~
~
~
~
~
::::1: I~ J: I: I:I~ I: I: I:I'~ I
HDLC Implemenatlon
The 8273 stops the one bit delayed retransmission mode,
HOLC Address and Control field are extendable. The
extension is selected by setting the low order bit of the
field to be extended to a one, a zero in the low order bit
indicates the last byte of the respective field.
Set Data Transfer Mode (CMD Code 97)
Since Address/Control field extension is normally done
with software to maximize extension flexibility, the 8273
does not create or operate upon contents of the extended
HOLe Address/Control fields. Extended fields are
transparently passed by the 8273 to user as either
interrupt results or data tr~nsfer requests. Software must
assemble the fields for transmission and interrogate them
upon reception.
However, the user can take advantage of the powerful
8273 commands to minimize CPU/Software overhead and
simplify buffer management in handling extended fields.
For instance buffered mode can be used to separate the
first two bytes, then interrogate the others from buffer.
Buffered 'mode' is perfect for a two byte address field.
~
~
~
~
~
~
~
~
~
~
::: I: I: I:I:I:I: I: I:I:I' I
When the data transfer mode is set, the 8273 will interrupt
when data bytes are required for transmission or are
available from a receive. If a transmit interrupt occurs and
the status indicates that there is no Transmit Result
(TxIRA = 0), the interrupt is a transmit data request. If a
receive interrupt occurs and the status indicates that there
is no receive result (RxIRA = 0), the interrupt is a receive
,
data request. '
Re..t Data Transfer Mode (CMD Code 57)
The 8273 when programmed, recognizes protocol
characters unique to HOLC such as Abort, which is a
string of seven or more ones ,(01111111l. Since Abort
character is the same as the GA (EOP) character used in
SOLC Loop applicati'ons, Loop Transmit and Receive
commands are not recommended to be used in HOL:C.
HOLC does not support Loop mode.
7-185
~
~
~
~
~
~
~
~
~
~
::: I: I~ I:I:I: t : I: I:I:I:"
If the Data Transfer Mode is reset, the 8273 data transfers '
are performed through the OMA requests without interrupt·
ing the CPU.
inter
8273.827~
Set Operating Mode (CMO Code 91)
TRANSMIT COMPLETION
IODH)
INTERRUPT
OTHER
I I, .
1
IIC
FLAG STREAM MODE
PREFRAME SYNC MODE
1 .. BUFFERED MODE
1 = EARLY INTERRUPT MODE
1 = EOP INTERRUPT MODE
1::c HDLCMODE
Reset Operating Mode (CMO Code 51)
CMD:
PAR
NO
Any mode switches set in eMO code 91 can be reset using
this command by 'placing zeros i.n the appropriate
positions.
(OS) HOLC Mode
In HOLe mode, a bit sequence of seven ones (01111111) is
interpreted as an abort character, Otherwise, eight ones
(011111111) signal an abort.
OTHER PROCESSING
(04) EOP Interrupt Mode
Figure 14.
In EOP interrupt mode, an interrupt is generated ,
whenever an EOP character (01111111) is detected by an
active receiver, This mode is useful forthe implementation
of an SOLe loop controller in detecting the end of a
message stream after a loop poll.
(03) Transmitter Early Interrupt Mode (Tx)
The early interrupt mode is specified to indicate when the
8273 should generate an end of frame interrupt. When set,
an early interrupt is generated when the last data
character has been passed to the 8273. If the user software
responds with another transmit command before the final
flag is sent, the final flag interrupt will not be generated
and a new frame will immediately begin when the current
frame is complete. This permits frames to be separated by
a single flag. If no additional Tx commands are provided, a
final interrupt will follow.
If this bit is zero, the interrupt will be generated only after
the final flag has been transmitted.
(02) Buffered Mode
If the buffered mode bit is set to a one, the first'two bytes
(normally the address (A) and control (e) fields) of a frame
are buffered by the 8273.11 this bit is a zero the address and
control fields are passed to and from memory.
(01) Preframe Sync Mode,
If this bit is set to a one the 8273 will transmit two characters before the first flag of a frame.
To guarantee sixteen line transitions, the 8273 ~ends two
bytes of data (OO)H if NRZI is set or data (55)H if NRZI is not
set.
(DO) Flag Stream Mode
If this ,bit is set to II one, the following table outlines the
operation of the transmitter.
Note: In buffered mode, if a supervisory frame (no Information) Transmit command is sent in response to an early
Transmit Interrupt, the 8273 will repeatedly transmit the
same supervisory frame with one flag in between, until a
non-supervisory transmit is issued.
TRANSMITTER STATE
Idle
Transmit or Transmit}
Transparent Active
Loop Transmit Active
1 Bit Delay Active
Early transmitter interrupt can be used in buffered mode
by waiting for a transmit complete interrupt instead of
early Transmit Interrupt before issuing a transmit frame
command for a supervisory frame. See Figure 14.
7-186
ACTION
Send Flags immedIately.
Send F lags after the
transmission complete
Ignore command.
Ignore command.
AFN,00743C
inter
8273, 8273·4
If this bit is reset to zero the following table outlines the
operation of the transmitter ..
TRANSMITTER STATE
IDLE
Transmit or Transmit·
Transparent Active
Loop Transmit Active
1 Bit Delay Active
}
ACTION
Send Idles on next character
boundary.
Send Idles after the transmission
is complete.
Ignore command.
Ignore commend.
The reset command emulates the action of the reset pin.
1. The modem control signals are forced high (inactive
level).
2. The 8273 status register flags are cleared.
3. Any commands in progress are terminated immediately.
4. The 8273 enters an idle state until the next command is
issued.
5. The Serial I/O and Operating Mode registers are set
to zero and OMA data register transfer mode is
selected.
6. The device assumes a non-loop SOLC terminal role.
Set Serial 1/0 Mode (CMD Code AO)
~
~
~
~
~
~
~
~
~
Receive Commands
~
:::' I 0 10 I' 10 I' 10 I 0 10 10 10 1
\ , :=
,
'=
The 8273 supports three receive commands: General
Receive, Selective Receive, and Splective Loop Receive.
NRZl MODE
General Receive (CMO Code CO)
TxC-Rxe
1 = lOOP BACK TxO _
General receive is a receive mode in which frames are
received regardless of the contents of the address field.
RxD
Reset Serial 1/0 Mode (CMD Code 60)
This command allows bits set in CMO code AO to be reset
by placing zeros in the appropriate positions.
(02) Loop Back
If this bit is set to a one, the transmit data is internally routed
to the receive data circuitry.
(01) TxC:+- RxC
If this bit is set to a one, the transmit clock is internally
routed to the receive clock circuitry. It is normally used
with the loop back bit (02).
(~O)
NRZI Mode
If this bit is set to a one, NRZI encoding and decoding of
transmit and receive data is provided. If this bit is a zero, the
transmit and receive data is treated as a normal positive logic
bit stream.
NRZI el)coding specifies that a zero causes a change in the
polarity of the transmitted signal and a one causes no polarity
change. NRZI is used in all asynchronous o!,erati'ons.
Referto IBM document GA27-3093 for details.
PAR-
0 0 '\'\0\0\0\0\01 0
0 , LEAST SIGNIFICANT BYTE OF THE
PAR
0
CMD:
,
RECEIVE BUFFER LENGTH (BO)
MOST SIGNIFICANT BYTE OF RECEIVE
BUFFER LENGTH (Bl)
NOTES:
1. If buffered mode IS specified. the RO; R1 receive frame len'gth
iresult) is the number of data bytes received.
2. If non-buffered mode IS specified, the RO, R 1 receive frame
length (result) IS the number of data bytes rec~ived plus two
(the count Includes the address and control bytes).
3. The frame check sequence (FCS) IS not transferred to
memory.
4. Frames with less than 32 bits between flags are Ignored (no
interrupt generated) If the buffered mode IS specified
5. In the non-buffered mode an Interrupt IS generated when a
less than 32 bit frame is received, since data transfer requests'
have occurred.
6. The 8273 receiver IS always disabled when an Idle IS received
after a valid frame. The CPU module must Issue a receive
command to re-enable the receiver.
7. The mtervemng ABORT character between a final flag and an
IDLE does not generate an mterrupt.
8. If an ABORT Character is not preceded by a flag and IS followed by an IDLE, an interrupt will be generated for the ABORT
followed by an IDLE interrupt one character time later. The
reception of an ABORT will disable the receiver.
Selective Receive (CMD Code C1)
Reset Device Command
CMO
PAR
PAR
An 8273 reset command is executed by outputing a (01)H
followed by (OO)H to the reset register (TMR). See 8273
AC timing characteristics for Reset pulse specifica·
tions.
7-187
PAR
PAR
,
°
°
°
°
°
°,
,
,
,
'\'\0\0\0\0\0.\'
LEAST SIGNIFICANT BYTE OF THE
RECEIVE BUFFER LENGTH (BO)
MOST SIGNIFICANT BVTE OF RECEIVE
BUFFER LENGTH (81)
RECEIVE FRAME ADDRESS MATCH
FIELD ONE (A1)
RECEIVE FRAME ADDRESS MATCH
FIELD TWO (AZ)
AFN.(J()743C
inter
8273, 8273·4.
Selective receive is a'receive mode in which frames are
ignored unless the address fie.ld matChes anyone of two
address fields given to the 8273 as parameters.
When selective receive is used in HDLC the 8273 looks at
the first character, if extended, software must then decide
if the message is for this unit.
Loop Transmi~ (CMD Code CAl
PAR
PAR
, 0
, 0
PAR
0
PAR
° '1'101011\01'10
°0
CMO
1
,
LEAST SIGNIFICANT BYTE OF
FRAME LENGTH (LO)
MQST SIG~IFICANT BYTE OF
FRAME LENGTH (l11
1
ADDRESS FIELD OF TRANSMIT FRAME (A)
1
CONTROL FIELD OF TRANSMIT FRAME (C)
Selective Loop Receive (CMD Code C2)
CMO
PAR
PAR
PAR
PAR
Transmits one frame in the same manner as the transmit
frame command except:
1. If the flag stream mode is not active transmission will
begin after a received EOP has been converted to a
flag.
2. If the flag stream mode is active transmission will
begin at the next flag boundary for buffered mode or at
the third flag boundary for non-buffered mode.
3, At the end of a loop transmit the one-bit delay mode is
entered and the flag stream mode is reset.
° ° '1'1°1°1°1°1'1°
LEAST SIGNIFICANT BYTE OF THE
° ° RECEIVE
BUFFER LENGTH
,
,
°
°
,
°
~BO)
MOST SIGNIFICANT BYTe OF RECEIVE
BUFFER LENGTH (81)
RECEIVE FRAME ADDRESS MATCH,
FIELD ONE (All
RECEIVE FRAME ADDRESS MATCH
FIELD TWO (A21
Selective loop receive operates like selective receive except that the transmitter IS placed in flag stream mode
automatically after detecting an EOP (01111111) following
a valid received frame. The one bit delay mode is also
reset at the end of a selective loop receive.
Transmit Transparent (CMD Coded C9)
CMO
PAR
, 0 0
, 0 1
PAR
Receive Disable (CMD Code C5)
Al
PAR
Ao
07
D6
05
04
03
02
01
1
I 1 I 0 I 0I 1 I
0
I 0I
1
MOST SIGNIFICANT BYTE OF
FRAME LENGTH (L1)
The 8273 will transmit a block of raw data without
protocol, i.e., no zero bit insertion, flags, or frame check
sequences.
Terminates an active receive command Immediately.
CMO
0
1
LEAST SIGNIFICANT BYTE OF
FRAME LENGTH ILO)
Do
I ° I ° I ' I 'I 0 I ° I ° I ' , ° ,
Abort Transmit Commands
NONE
Transmit Commands
An ,abort command is supported for each type of transmit
command. The abort commands are ignored if a transmit
command is not in progress.
The 8273 supports three transmit commands: Transmit
Frame, Loop Transmit, Transmit Transparent.
Abort T1'ansmit Frame (CMD Code CC)
A1
CMO.'
Transmit Frame (CMD Code C8)
CMD
PAR
PAR
PAR
PAR
PAR,
1
07
06
Ds
1 ,
04
03
0 , 0 l'
02
01
Do
, ' I 0 '0
NONE
After an abort character (eight contiguous ones) is transmitted, the transmitter reverts to sending flags or idles as a
function of the flag stream mode specified.
° °, '1'10101'101010
°
,
°
° ,
°
Ao
0 , 0' ' ,
LEAST SIGNIFICANT BYTe OF
FRAME LENGTH (LO)
MOST SIGNIFICANT BYTE OF
FRAME LENGTH (l1)
Abort Loop Transmit (CMD Code CE)
ADDRESS FIELD OF TI;tANSMIT FRAME IA)
~
CONTROL FIELD OF TRANSMIT F.RAME (e)
CMo'l
PAR
. Transmits one frame including: initial flag, frame check
sequence, and the final flag.
If the buffered mode is specified, the LO, L1, frame length
provided as a parameter is the length of the information
field and the address and control fields must be input.
In unbuffered mode the frame length provi
0.8
x=
< .
2.0
TEST POINTS
A.C. TESTING LOAD CIRCUIT
0.8
0.45
DEVICE
~Cl~150PF
UNDER
TEST
,
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1 AND 0 45V FOR
A LOGIC 0 TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC 1
AND 0 BV FOR A LOGIC 0
CL
=
150pF
C L INCWDES JIG CAPACITANCE
WAVEFORMS
lREAD
DACK
Ao.
---.J
'oe
X
I--tCA-I
'RR
J
No
DATA BUS
X
CD
A,. CS
.- -
I---tAC~
~
tRO
~-------tAD
"D
I :--tOF~
):--------
WRITE
DACK
=:x:::::=
'0-
I
X·
--~tAC
DATA BUS
)(
L
J(
tww
~
r-tCA-l
X
tow
7-197
:-.---- two----l
AFN-00743C
inter
8273, 8273-4
WAVEFORMS (Continued)
( (.
ORO ___.J/
DMA
'CQ~
r
______
I
\~----r-----------------------------
XL_______________________________
~OR~
tLtCL=rLtCHJ~---J/
~
=l
CHtPCLOCK
32XCLOCK
TRANSMIT
,
-j
+----tDCL
.!
\
~-tDCH - - - - - - .
tOCY
TxO
.
~
--tTD-
RECEIVE
~,-~lt-,~--~~
--if
RXO------.t=J [~J-~I--------IDCV
\1+---.
7-198
AF~43C
inter
8273,8273-4
WAVEFORMS (Continued)
DPLLOUTPUT
FLAG DETECT OUTPUT
7-199
AFN.()()743C
8274
MULti-PROTOCOL SERIAL
CONTROLLER (MPSC)
• Byte Synchronous:
- Character Synchronization, Int. or Ext.
- One or Two Sync Characters
- Automatic CRC Generation and
Checking (CRC-16)
-IBM Bisync Compatible
• Bit Synchronous:
- SDLC/HDLC Flag Generation and
Recognition
- 8 Bit Address Recognition
- Automatic Zero Bit Insertion and
'Deletion
- Automatic CRC Generation and
Checking (CCITT-16)
- CCITT X.25 Compatible
• Asynchronous, Byte Synchronous and
Bit Synchronous Operation
• Two Independent Full Duplex
Transmitters and Receivers
• Fully Compatible with 8048, 8051, 8085,
8088, 8c)s6, 80188 and 80186 CPU's; 8257
and 8237 DMA Controllers; and 8089 I/O
Proc.
• 4 Independent DMA Channels
• Baud Rate: DC to 880K Baud
• Asynchronous:
-5-8 Bit Character; Odd, Even, or No
Parity; 1, 1.5 or 2 Stop Bits
-Error Detection: Framing, Overrun,
and Parity
• Available in EXPRESS
-Standard Temperature Range
The Intele 8274 Multi-Protocol Series Controller (M PSC) is designed to interface High Speed Communications
Lines using Asynchronous, IBM Bisync, and SOLC/HOLC protocol to Intel microcomputer systems. It can be
interfaced with Intel's MC5-48, -85, -51; iAPX-86, -88, -186 and -188 familieS, the 8237 OMA Controller, or the 8089
110 Processor-in polled, interrupt driven, or OMA driven modes of operation.
'
The MPSC is a 40 pin device fabricated using Intel's High Performance HMOS Technology.
D80 _7
~A
CLJ----....I
WII _ _ _ _- - '
DTRa
RiC.
L.-_ _-'--_ _~- .....
NETWORK INTERFACE
Figure 1. Block
Fig~re
Dlag~am
2. Pin Configuration
Inlel CorporatIon Assumes No ResponSibility for the USB of Any Circuitry Other Than Circuitry Embodied In an Intel Product No Other C,rcuit Patent LICeOHS are Implied
©INTEL CORPORATION, 1981
7-200
8274
Table 1. Pin Description
Pin
No.
~pe
ClK
1
I
~
2
I
~
3
I
Symbol
RxC.
4
I
Carrier Detect (Channel AI: This
interface signal is supplied by the
modem to indicate that a data carrier
signal has been detected and that a
valid data signal is present on the
RxDA line If the auto enable control
is' set the 8274 will not enable the
serial receiver until w signal on this pin will
force the MPSC to an idle state TxD.
and TxD. are forced high. The
modem interface output signals are
forced high. The MPSC will remam
idle until the control registers are
initialized. Reset must be true for one
complete ClK cycle.
li'ansmit Clock (Channel BI: The
serial data are shifted out from the
Transmit Data output (TxDe) on the
falling edge of the Transmit Clock
Ground.
Power: +5V Supply
TxDe
8
a
li'ansmlt Data (Channel BI: This pin
transmits serial data to the communications channel (Channel B)
RxD.
34
I
RxDe
9
I
Receive Data (Channel BI: This pin
receives serial data from the communications channel (Channel B)
Receive Data (Channel AI: T~ls pin
receives senal data from the commUnications channel (Channel A)
SYNDETA
33
I/O
~
IRTS.
10
1/0
Synchronous Detection (Channel BI:
Thispm IS used in byte synchronous
mode as either an internal sync
detect (output) or as a means to
force' external synchronization (input) In SDlC mode, this pin IS an
output indicating Flag detection In
asynchronous mode it is a general
purpose input (Channel B)
,synchronous Detection (Channel A):
This pin is used in byte synchronous
mode as either an Internal sync
detect (output) or as a means to
force external synchronization (input) In SDlC mode, thiS pin IS an
output indicating flag detection In
asynchronous mode it is a general
purpose Input (Channel A)
RDY.I
RxDRQA
32
a
Ready: In mode 0 this pin is RDYA
and is used to synchronize data'
transfers between the processor
and the MPSC (Channel A). In
modes 1 and 2 this pin is RxDRQA
and is used by the channel A receiver
to request a DMA transfer
DTR.
31
a
Data Terminal Ready (Channel A):
General.purpose output
Request to Send (Channel BI: General purpose output, gene~ally used
to signal that Channel B is ready to
send data
SYrii'5E"f. or RTS. selection is done
by WR2, D7 (Channel A)
AFN-01701B
7-201
intJ
8274
Table 1. Pin Description
Symbol
iP5i
Pin
No.
30
"TYpe
0
TxDRQ.
WI!
29
I/O
RxDRQ.
iNi
28
0
Name and Function
Interrupt Priority Out/Transmitter
DMA Request (Channel 8): In modes
a and 1, this pin is Interrupt Priority
Out. It is used to establish a: hardware
interrupt priorit~ scheme with iPl. It
is low only if iPl is low and the
controlling processor is not servicing
an interruptfrom this MPSC. In mode
2 it is TxDRQ. and is used to request
a DMA cycle for a transmit operation
(Channel 8)
Interrupt Priority In!Recelver DMA
Reques~(Channel 8): In ,modes 0
and 1, IPl,ls Interrupt PrlOrity In A
low on IPI means that no higher
priority device is being serviced by
the controlling processor's interrupt
service routine. In mode 2 this pin is
RxDROo and is used to request a
DMA cycle for a receive operation
(Channel 8). In Interrupt mode, this
pin must be tied low.
Interrupt: The interrupt signal indicates thatthe highest prioriI\' internal
interrupt requires service (open collector) Priority can be resolved via
an external Interrupt controHer or a
daisy-chain scheme.
"TYpe
.~
Pin
No.
27
DiRs
26
0
A,
25
I
A,
24
I
~
23
I
RD
22
I
WR
21
I
Symbol
I
Name and Function
Interrupt Acknowledge: This Interrupt Ackowledge signal allows the
highest priority interrupting device
to generate an interrupt vector. This
pin must be pulled high (inactive) in
non-vector mode.
Data Terminal Ready (Channel 8):
This is a general purpose output
Addras" This line selects Channel A
or 8 during data or command transfers. A low selects Channel A.
Address: This line selects between
data or command information transfer A low means data.
Chip Select: This signal selects the
MSPC and enables reading from or
writing into its registers
Read: Rea', controls a data byte or
status byte transfer from the MPSC
to the CPU.
Write: Write controls transfer of data
or commands to the MPSC.
RESET
FUNCTIONAL DESCRIPTION
When the 8274 RESET line is activated, both MPSC
channels enter the idle state. The serial output lines are
forced to the marking state (high) and the modem
interface signals (Fi'rn, OTR) are forced high. In addition, the pointers registers arlil set to zero.
Additional information on Asynchronous and Synchronous Communications with the 8274 is available
respectively in thEil Applications Notes AP 134 and AP
145.
GENERAL DESCRIPTION
The Intel 8274 Multi-Protocol Serial Controller is a
microcomputer peripheral device which supports
Asynchronous, Byte Synchronous (Monosync, IBM
Bisync), and Bit Synchronous (ISO's HOLC, IBM's
SOLC) protocols. This controller'S flexible architecture
allows easy implementation of many variations of these
three protocols with low software and hardware
overhead.
The Multi-Protocol Serial controller (MPSC) implements two independent serial receiver/transmitter
channels.
Command, parameter, and status information is stored
in 21 registers within the MPSC (8 writable registers for
each channel, 2 readable registers for Channel A and 3
readable registEilrs for Channel B).
In the following discussion, the writable registers will
be referred to as WRO through WR7 and the readable
registers will be referred to as RRO'through RR2.
This section of the data sheet describes how the
Asynchronous and Synchronous protocols are implemented in the MPSC. It describes general considerations, transmit operation, and receive operation for
Asynchronous, Byte Synchronous, and Bit Synchronous protocols.
The MPSC supports several microprocessor interface
options: Polled, Wait, Interrupt driven and OMAdriven.
The MPSC is designed to support INTEL'S MCS-85
and iAPX 86, 88, 186, 188 families.
7-202
AFN-01701B
intJ
8274
ASYNCHRONOUS OPERATIONS
7. Transmitter Enable. The serial channel transmitter
operation may be enabled or disabled by setting or
clearing bit 3 of WRS
TRANSMITTER/RECEIVER INITIALIZATION
(See Oetailed Command Oescription Section for complete information)
In order to operate in asynchronous mode, each MPSC
channel must be initialized with the following informatio'l:
1. TransmiVReceive Clock Rate. This parameter is
specified by bits 6 and 7 of WR4. The clock rate may
besetto 1, 16, 32, or64 times the data-link bit rate. If
the X1 clock mode is selected, the bit synchroniza\
tion must be accomplished externally.
2. Number of Stop Bits. This parameter is specified by
bits 2and 30fWR4. The number of stop bits may be
set to 1, 1 1/2, or 2.
3. Parity Selection. Parity may be set for odd, even, or
no parity by bits 0 and 1 of WR4.
4. Receiver Character Length. This parameter sets the
length of received characters to S, 6, 7, or 8 bits. This
parameter is specified by bits 6 and 7 of WR3.
S. Receiver Enable. The serial-channel receiver operation may be enabled or disabled by setting or
clearing bit 0 of WR3.
6. Transmitter Character Length. This parameter sets
the length of transmitted characters to S, 6, 7, or 8
bits. This parameter is specified by bits Sand 6 of
WRS. Characters of less thanS bits in length may be
iransmitted by setting the transmitted length to five
. bits (set bits Sand 6 of WRS to 0).
The MPSC then determines the actual number of
bits to be transmitted from the character data byte.
The bits to be transmitted must be right justified in
the data byte, the next three bits must be set to 0 and
all remaining bits must be set to 1. The following
table illustrates the data formats for transmission of
1 to S bits of data:
07
1
1
1
1
0
06
1
1
1
0
0
OS
1
1
0
0
0
04
1
0
0
0
c
03
0
0
0
c
c
02 01 00
0 0 c
a c c
c c c
c c c
c c c
Number of
Bits Transmitted
(Character Length)
1
2
3
4
S
7-203
8. Interrupt Mode.
For data transmission via a modem or RS-232-C
interface, the folloWing information must also be
specified:
1. The Request To Send (RTS) (WRS; 01) and Oata
Terminal Ready (OTR) (WRS; 07) bits must be set
along with the Transmit Enable bit (WRS; 03).
2. Auto Enable may be set to allow the MPSC to
automatically enable the channel transmitter when
the clear-ta-send signal is active and to automatically
enable the receiver when the carrier-detect signal is
active. However, the Transmit Enable bit (WR3; 03)
and Receive Enable bit (WR3; 01) must be set in
order to use the Auto Enable mode. Auto Enable is
controlled by bit S of WR3.
When loading Initialization parameters into the MPSC,
WR4 information must be written before the WR1, WR3,
WRS parameters commands.
Ouring initialization, it is desirable to guarantee that the
external/status latches reflect the latest interface
information. Since up to two state changes are
internally stored by the MPSC, at least two Reset
External/Status Interrupt.commands must be issued.
This procedure is most easily accomplished by simply
issuing this reset command whenever the pOinter
register is set during initialization.
An MPSC initialization procedure (MPSC$RX$INIT)
for asynchronous communication is listed in Intel
Application Note AP 134.
TRANSMIT
The transmitfunction begins when the Transmit Enable
bit (WRS; 03) is set. The MPSC automatically adds the
start bit, the programmed parity bit (odd, even or no
parity) and the programmed number of stop bits (1, 1.S
or 2 bits) to the data character being transmitted. 1.S
stop bits option must be used with X16, X32 or X64
clock options only.
AFN-01701B
inter.
8274>
The serial data are shifted out from the Transmit Data
(IXO) output on the falling edge of tlJe Transmit Clock
(TxC) input at a rate programmable to 1, 1/16th, 1/32nd,
or 1/64th the clock rate supplied to the TxC input.
ff
The TxO o~tPut is held high when the transmitter has
no data to send, unless, under program control, the
Send Break (WRS; 04) commandis issued to hold the
TxO low.
.
.
If the External/Status Interrupt bit (WR1; ~O) is set, the
and SYNDET are monitored and, if
status of CIT,
any changes occur for a period oftime greater than the
minimum specified pulse width, an interrupt is generated. CTS is usually monitored using this interrupt
feature. (e.g. Auto Enable option).
rn
The Transmit Buffer Empty bit (RRO; 02) is set by the
MPSC when the data byte from the buffer is loaded ir
the transmit shift register. Data should be written to the
MPSC onfy when the Tx buffer becomes empty te.
prevent overwriting.
2. Framing. A framing error will occur·if a stop!;>i! is not
detected immediately following the parity bit (if
parity checking is enabled) or immediately following
the most-sig nificant data bit (if parity checki ng is not
enabled). When a Framing Error is detected, the
Fram·ing Error bit (RR1; 06) is set. The detection of a
Framing Error adds an additional 1/2 bit time to the
character time so the Framing E~ror is not interpreted
as a new start bit.
3. Overrun. If the CPU fails to read a data character
while morethan three characters have been received,
the Receive Overrun bit (RR1; 05) is set. When this
occurs, the fourth character assembled replaces the
third character in the receive buffers. Only the
overwritten character is flagged with the Receive
Overrun bit. The Receive Overrun bit (RR1, 05) is
reset by the Error Reset command (WRO; OS, 04, 03).
External/Status Latches
The MPSC continuously monitors the state of five
externallstatus conditions: \
Receive
\
The receive function begins when the Receive Enable
(WR3; ~O) bit is set. If the Auto Enable (WR3: 05)
option is selected, then Carrier Detect (a:5) must also
be low. A val id start bit is detected if a low persists for at
least 112 bit time on the Receive Data (RxO) input.
The data is sampled at mid-bit time, on the rising edge
of RxC, until the entire character is assembled. The
receiver inserts 1 when a character is less than 8 bits.
If parity (WR4·; ~O) is enabled and the character is less
than 8 bits the parity bit is not stripped from the
character.
's
1. CTS - clear-to-send input pin.
2. CD - carrier-detect input pin.
3. SYNOET - synC-detect input pin. This pin may be
used as a general-purpose input in the asynchronous
communication mode.
.
'
4. BREAK - a break condition (series of space bits on
the receiver input pin).
5. T,x UNOERRUN/EOM - Transmitter Underrun/End
of Message.
Error Reporting
The receiver also stores error status for each of thEi 3
data characters in the data buffer. Three error conditions may be encountered during data reception in tl:le
asynchronous mode:
1. Parity. If parity bits are computed and transmitted
with each character and the MPSC is set to check
parity (bit 0 in WR4 is set), a parity error will occur
whenever the number of "1" bits Within the character
(including the parity bit) does not match the
odd/even setting of the parity check flag (bit 1 in
WR4). When a parity error is detected, the parity
error flag (RR1; 04) is set and remains set until it is
reset by the Error Reset command (WRO; OS, 04,
03).
7-204
A change of state in any ofthese monitored conditions
will cause the associated status bit in RRO to be latched
(and optionally cause an interrupt).
If the External/Status Interrupt bit (WR1; ~O) is enabled,
Break Detect (RRO; 07) and Carrier Detect (RRO; 03)
will cause an interrupt. Reset External/Status interrupts
(WRO; OS, 04, 03) will clear Break Detect and Carrier
Detect bits if they are set.
AFN·01701C
8274
Asynchronous Mode Register Setup
07
00
01
10
11
WR3
06
05
Rx 5 b/char
Rx 7 b/char
Rx 6 blchar
Rx B b/char
04
AUTO
ENABLE
03
0
0
02
01
00
0
0
Rx
ENABLE
00 X1 Clock
WR4
01 X16 Clock
10 X32 Clock
11 X64 Clock
,WR5
00
01
10
1,1
DTR
0
01 1 STOP BIT
10 1V2 STOP BITS
11 2 STOP BITS
0
Tx:55 b/char
Tx 7 b/char
Tx 6 b/char
Tx B b/char
SEND
BREAK
Tx
ENABLE
0
EVENI
ODD
PARITY
PARITY
ENABLE
RTS
0
SYNCHRONOUS OPERATIONMONOSYNC, BISYNC
General
Transmit Set-Up-Monosync, Bisync
The MPSC must be initialized with the following parameters: odd or even parity (WR4; 01,00), X1 clock
mode (WR4; 07, 06), 8- or 16-bit sync character
(WfII4; OS, 04), CRC polynomial (WRS; 02), Transmitter Enable (WRS; 03), interrupt modes (WR1,
WR2), transmit character length (WRS; 06, 05) and
receive character length (WR3; 07,'06). WR4 pa~
rameters must be written before WR1, WR3, WRS,
WR6 and WR7.
Transmit data is held high after channel reset, or if
the transmitter is not enabled. A break may .be programmed to generate a spacing line that begins as
soon as the Send-Break (WRS; 04) bit is set. With the
transmitter fully initialized and enabled, the default
condition is continuous transmission of the 8- or
16-bit sync character.
'
The data is transl1)itted on the falling edge of the
Transmit Clock, (TxC) and is received on the rising
edge of Receive Clock (RxC). The X1 clock is used
for both transm it and receive operations for all three
sync modes: Mono, Bi and External.
Using interrupts for data transfer requires that the
Transmit InterrupVOMA Enable bit (WR1; 01) be set.
An interrupt is generated each time the transmit buffer becbmes empty. The interrupt can be satisfied
Synchronous Mode Register Setup-MonosYJlc, Bisync
07
WR3
00
01
10
11
Rx
Rx
Rx
Rx
WR4
0
WR5
DTR
06
5 b/char
7 b/char
6 b/char
B b/char
0
00
01
10
11
05
AUTO
ENABLE
02
01
00
Rx CRe
ENABLE
0
SYNC
CHAR
LOAD
INHIBIT
Rx
ENABLE
0
0
EVENI
ODD
PARITY
PARITY
ENABLE
Tx
eNABLE
1
(SELECTS
CRC-16)
RTS
Tx CRC
ENABLE
04
\.
ENTER
HUNT
MODE
03
00 B bit Sync
01 16, bit Sync
11 Ext Sync
Tx:55 b/char
Tx 7 b/char
Tx 6 b/char
Tx'B b/char
SEND
BREAK
7-205
AFN-01701C
intJ
,
8274
either by writing another character into the transmitter or by resetting the Transmitter Interrupt/OMA
Pending latch with a Reset Transmitter Interrupt/
OMA Pending Command (WRO; OS, 04, 03). If noth- '
ing more is written into the transmitter, there can be
no further Transmit Buffer Empty interrupt, but this
situation does cause a Tr?lnsmit Underrun condition
(RRO; 06).
,
'"
the MPSC. Although the MPSC automatically
transmits up to two synd characters (16 bit sync), it is
wise to send a few more sync characters ahead of
the message (before enabling Transmit CRC) to
ensure sY,nchronization at the receiving end.
Data Transfers using the ROY signal are for software
controlled data transfers such as block moves. ROY
tells the CPU that the MPSC is not ready to accept!
provide data and that the CPU must extend the
output/input cycle. OMA data transfers, use the
TxORQ AlB signals which indicate that the transmit
buffer is empty, and that the MPSC is ready to accept
the next data character. If the data character is not
loaded into the MPSC by the time the transmit shift
register is empty, the MPSC enters the Transmit
Underrun condition.
The Transm it CRC Enable bit can be changed on the
fly any time in the message to include or exclude a
particular data character from CRC accumulation.
The Transmit CRC Enable bit should be in the de- '
sired state when the data character is loaded into
the transmit shift register. To ensure this bit in the
proper state, the Transmit CRC Enable bit must be
issued before sending the data character to the
MPSC.
Transmit Transparent Mode. Transparent mode
(Bisync protocol) operation is made possible by the
ability to change Transm it CRC Enable on the fly and
by the additional capability of inserting 16 bit sync
characters. Exclusion of OLE characters from CRC
calculation can be achieved by disabling CRC calculation immediately preceding the OLE character
transfer to the MPSC.
'
The MPSC has two fJrogrammable options for solving the transmit underrun condition: it can insert
sync characters, or it can send the CRC characters
generated so far, followed by sync characters. Following a 'chip or channel reset, the Transmit
Un~errun/EOM status bit (RRO; 06) Is In a set condition allowing the insertion of sync characters when
there is no data to send. The CRC is not calculated
on these automatically inserted sync characters.
When the CPU detects the end of'message, a Reset
Transmit Underrun/EOM command can be issued.
This allows CRe to be sent when the transmi'tter has
no data to send.
In the transmit mode, the transmitter always sends
the pr,ogrammed n umber of sync bits (8 or 16) (WR4;
OS, 04). When in the Monosync mode, the transmitter sends from WR6 and the receiver compares
against WR7. One of two CRC polynomials, CRC 16
or SOLe, m?lY be used with synchronous mqdes. In
the transmit initialization process, the CRC
generator is initialized by setting the Reset Transmit
CRC Generato~ command (WRO; 07,06).
In the case of sync insertion, an interrupt is generated only after the first ,automatically inserted sync
character has been lOaded in the Transmit Sh'iftRegister. The status register indicates the Transmit Underrunl
EOM bit and the-Transmit Buffer Empty bit are set.
In the case of CRC insertion, the Transmit
Underrun/EOM bit is set and the Transmit Buffer
Empty bit is reset whileCRC is being sent. When
CRC has been completely sent, the Transmit Buffer
Empty status bit is set and an interrupt is generated
to indicate to the CPU that another message can
begin (this interrupt occurs because CRC has been
sent and sync has been loaded into the Tx Shift Register). If no more messaQes are to be $ent, the program can terminate transmission by resetting RTS,
and disabling the transmitter (WRS; 03).
Bisync CRC Generation. Setting the Transmit CRe;
enable bit (WRS; ~O) inoicates CRC accumulation
when the program sends the first data character to
7-206
The External/Status interrupt (WR1; ~O) mode can
be used to monitor the status of the CTS input as
well as the Ti'ansmit Underrun/EOM latch. Optionally, the Auto Enable (WR3; 05) feature can be used
to enable the trapsmitter when CTS is active. The
first data transfer to the MPSC can begin when the
External/Status interrupt occurs (CTS (RRO; 05)
status bit set) following the Transmit Enable command (WRS; 03).
Receive
After a channel reset, the receiver is in the Hunt
phase, during which the MPSC looks f9r character
synchronization. The Hunt begins only when the receiver is enabled and data transfer begins only when
character synchronization has been achieved. If
character synchronization is lost, the hunt phase
can be re-entered by writing the Enter Hunt Phase
(WR3; 04) bit. The l/-ssernbly of received data continues until the MPSC is reset or until the receiver is
AFN-0170,C
8274
disabled (by command or by rn! while in the Auto
Enables mode) or until the CPU sets the Enter Hunt
Phase bit. Under program control, all th-e leading
sync characters of the message can be inhibited
from loaqing the receive buffers by setting the Sync
Character Load Inhibit (WR3; 01) bit. After character
synchronization is achieved the assembled characters are transferred to the receive data FIFO. After
receiving the first data character, the Sync Character
Load Inhibit bit should be reset to zero so that all
characters are received, including the sync characters. This is important because the received CRC
may look like a sync character and not get received.
buffer. Errors and Special Receive Conditions generate a special vector if the Status Affects Vector
(WR1 8; 02) is selected. Also the Parity Error may be
programmed (WR1; 04, 03) not to generate the special vector while in the Interrupt On Every Character
mode.
The Special Receive Condition interrupt can only
occur while in the Receive Interrupt On First Character'Only or the Interrupt On Every Receive Character
modes. The Special Receive Condition interrupt is
caused by the Receive Overrun (RR1; 05) error condition. The error status reflects an error in the current word in the receive buffer, in addition to any
parity or Overrun errors since the last Error Reset
(WRO; 05, 04, 03). The Receive Overrun and Parity,
error status bits are latched and can only be reset by
the Error Reset (WRO; 05, 04, 03) command.
Data may be transfl!rred with or without interrupts.
Transferring data without interrupts is used for a
purely polled operation or for off-line conditions.
There are three interrupt modes available for data
transfer: Interrupt on First Character Only, Interrupt
on Every Character, and Special Receive Conditions
Interrupt.
Interrupt on First Character Only mode is normally
used to start a polling loop, a block transfer sequence using ROY to synchronize the CPU to the incoming data rate, or a OMA transfer using the RxORQ
signal. The MPSC interrupts on the first character
and th,ereafter only interrupts after a Special Receive Condition is detected. This mode can be
reinitialized using the Enable Interrupt On Next'Receive Character (WRO; 05, 04, 03) command which
allows the next character received to generate an
interrupt. Parity Errors do not cause interrupts, but
End of Frame (SOLC operation) and Receive Overrun do cause interrupts in this mode. If the external
status interrupts (WR1; ~O) are enabled an interrupt
may be generated any time the rn5 changes state.
The CRC check result may be obtained by checking
for CRC bit (RR1; 06). This bit gives the valid CRC
result 16 bit times after the second CRC byte has
been read from the MPSC. After reading the second
CRe byte, the user software must read two more
characters (may be sync characters) before checking for CRC result in RR1. Also for proper CRC computation by the receiver, the user software must reset
the Receive CRC Checker (WRO; 07, 06) after receiving the first valid data character. The receive CRC
Enable bit (WR3; 03) may also be enabled at this
tima
.
SYNCHRONOUS OPERATION-SOLC
General
Inter/upt On Every Character mode generates an
interrupt whenever a character enters the receive
Like the other synchronous operations the SOLC
mode must be initialized with the following parameters: SOLC mode (WR4; 05, 04), SOLC polynomial
(WR5; 02), Request to Send, Data Terminal Ready,
Synchronous Mode Register Setup-SOLC/HOLC
07
00
01
10
11
WR3
0
WR4
I
WR5
06
Rx 5b/char
Rx 7b/char
Rx 6b/char
Rx 8b/char
OTR
0
05
04
03
02
01
DO
AUTO
ENABLES
ENTER
HUNT
MODE
Rx
CRC
ENABLE
ADDRESS
SEARCH
MODE
0
Rx
ENABLE
0
0
0
0
RTS
Tx
CRC
ENABLE
1
0
(SELECTS SOLCI
HOLC MODE)
00 Tx .. 5b/char
01 Tx 7b/char
10 Tx 6b/char
11 Tx 8b/char
SEND
BREAK
7-207
Tx
ENABLE
-
0
(SELECTS
SOLCI
HOLC
CRC)
AFN·01701C
8274,
)
COMMAND/STATUS
POINTER
D2
D1
o
0
o
0
o
DO
~I w :
O----t
·1
~I
0--_-1
R
W
R
W
,R
: : : I
0
""
:JI
2
1
1
1
I
R
R
R
R
R
R
0
I
MSS
o
LSS
Read Registers
~I
W
R
-I
W
R
~I
W
R
0----.
~I
W
R
-I
W
R
6
MSS
LSS
Write Registers
Figure 3. Command/Status Register Architecture,(each serial channel)
Command, parameter, and status information is stored
in 21 registers within the MPSC (8 wrItable registers for
each channel, 2 readable registers for Channel A and 3
readable registers for Channel B), They are all accessed via the command ports.
After reset, the contents of the pointer registers are
zero. The first write to a' command register causes
the data to be loaded into Write Register 0 (WRO) ..
The three least significant bits of WRO are loaded
into t.he Command/Status Pointer. The next read or
write operation accesses the read or write register
seiected by the pointer. The pointer is reset after the
read or write operation is completed.
An internal pointer register selects which of the
command or status registers will be read or written
during a command/status access of an MPSC
channeL
7-208
AFN·01701C
intJ
8274.
transmit character length (WR5; OS, 05), interrupt
modes (WR1; WR2), Transmit Enable (WR5; 03),
Receive Enable (WR3; ~O), Auto Enable (WR3; 05)
and External/Status Interrupt (WR1; 00).WR4
parameters must be written before WR1, WR3,
WR5, WRS and WR7.
The Interrupt modes for SOLC operation are similar
to those discussed previously in the synchronous
operations section.
Transmit
After a channel reset, the MPSC begins sending
SOLC flags.
Receive
After initialization, the MPSC enters the Hunt phase,
and remains in the Hunt phase until the first Flag is
received. The MPSC never ag~in enters the Hunt
phase unless the microprocessor writes the Enter
Hunt command. The MPSC. will also detect flags
separated by a single zero. For example, the bit pattern 011111101111110 will be detected as two flags.
The MPSC can be programmed to receive all frames
or it can be programmed to the Address Search
Mode. In the Address Search Mode, only frames with
addresses that match the value in WRS or the global
address (OFFH) are received by the MPSC. Extended
address recognition must be done by the microprocessor software.
Following the flags in an SOLC operation the a-bit
address field, control field and information field may
be sent to the MPSC by the microprocessor. The
MPSC tranllmits the Frame Check Sequence using
the Transmit Underrun feature. The MPSC automatically inserts a zero after every sequence of 5 consecutive 1 's except when transmitting Flags or
Aborts.
.
The control and information fields are received as
data.
SOLC/HOLC CRC calculation does not have an 8-bit
delay, since all characters are included in the calculation, unlike Byte Synchronous Protocols.
Reception of an abort sequence (7 or more 1's) will
cause the Break/Abort bit (RRO; 07)to be set and will
cause an External/Status interrupt, if enabled. After
the Reset External/Status Interrupts Command has
been issued, a second interrupt will occur atthe end
of the abort sequence.
SOLC-like protocols do not have provision for 'fill
characters within a message. The MPSC therefore
automatically terminates an SOLC frame when the \
transmit data buffer and output shift register have
no more bits to send. It does this by sending the two,
bytes of CRC and then one or more flags. This allows
very high-speed transmissions under OMA or CPU
control without requiring the CPU to respond
quickly 'to the end-of-message situation.
After a reset, the Transmit Underrun/EOM status bit
is in the set state and prevents the insertion of CRC
characters during the time there is no data to send.
Flag characters are sent. The MPSC begins to send
the frame when data is written into the transmit buffer. Between the time the first data byte is written,
/ and the end of the message, the Reset Transmit
Underrun/EOM (WRO; 07, OS) command must be
issued. The Transmit Underrun/EOM status bit (RRO;
06) is in the reset state at the end of the message
which auto~atically sends the CRC characters.
The MPSC may be programmed to issue a send
Abort command (WRO; OS, 04, 03). ThiS command
causes' at least eight 1's butless than fourteen 1's to
be sent before the line reverts to continuous flags.
MPSC
Detailed Command/Status Description
GENERAL
The MPSC supports an extremely flexible set of se"
rial and system interface modes.
The system interface to the CPU consists of a ports
or buffers:
cs
A,
A.
Read Operation
Write Operation
0
0
0
0
1
0
1
0
1
X
0
0
1
1
X
Ch A Data Read
Ch A Status Read
Ch B Data Read
Ch A Data Write
Ch A Command/Parameter
Ch B Data Write
Ch 8 Command/Parameter
High Impedance
Ch B Statu's R'ead
High Impedance
Data buffers are addressed by A1
po'rts are addressed by Al = 1.
7-209,
=
0, and Command
,
AFN·01701 C
8274:
COMMAND/STATUS DESCRIPTION
The following command and status bytes are used
during i'nitialization and execution phases of operation. All Command/Status operations on the two
channels are identical, and independent, except
where noted.
Command 0
Null-has no effect.
Command 1
Send Abort-causes the generation of eight to thirteen 1's when
in the SDLC mode.
COl\lmand 2
Reset External/Status Interruptsresets the latched status bits of
RRO and re-enables them, allowing
interrupts to occur again.
Command 3
Channel Reset-resets the Latched Status bits of RRO, the
interrupt prioritization logic and
all control registers for the
channel. Four extra system
clock cycles should be allowed
for MPSC reset time before any
additional commands or controls
are written into the channel.
Command 4
Enable Interrupt on Next Receive
Character-if the Interrupt on
First Receive Character mode is
selected, this command reactivates that mode after each complete message is received to
prepare the MPSC for the next
message.
Detailed Register Oescription
Write Register 0 (WRO):
COMMANDISTATUS POINTER
REGISTER POINTER
(0
NULL CODe
SEND ABORT (SDLC)
RESET EXTISTATUS INTERRUPTS
CHANNEL RESET
ENABLE INTERRUPT ON NEXT Rx
CHARACTER
Command 5
Reset Transmitter Interrupt/DMA
Pending-if
The
Transmit
Interrupt/OMA Enable mode is
selected, the MPSCautomatically
interrupts or requests OMA data
transfer when the transm it buffer
becomes empty, When there are no
more characters to be sent,
issuing this command prevents
further transmitter interrupts or
DMA requests until the next
character has been completely
sent.
. Command 6
Error Reset-error latches, Parity and Overrun errors in RR1 are
reset.
Command 7
End of Interrupt-resets the
interrupt-in-service latch of the
highest-priority internal device
under service.
07,06
CRC Reset Code
00
Null-has no effect.
RESET TxlNT/DMA PENDING
ERROR RESET
END OF INTERRUPT
roo 1
NULL CODE
RESEr Ax CRe CHECKER
RESET Tx CRC GENERATOR
RESET Tx UNDERRUN/EOM LATCH
WRO
02,01, DO-Command/Status Register Pointer bits
determine which write-register the next byte is to be
written into, or which read-register the next byte is to
be read from. After reset, the first byte written into
either channel goes into WRO. Following a read or
write to any register (except WRO) the pointer will
point to WRO.
05,04, D3-"-Command bits deter'mine which of the
basic seven commands are to be performed,
7-2·10
01
. Reset Receive CRC Checkerresets the CRC checker to D's. If in
SOLC mode the CRC checker is
initialized to all 1's.
AFN-01701C
<
intJ
8274
10
Reset Transmit CRC Generator
-resets the CRC generator to
O's. If in SOLC mode the CRC
generator's initialized to all 1'so
01
Transmitter Interrupt/OMA Enable
-allows the MPSC to interrupt or
request a OMA transfer when the
transmitter buffer becomes empty.
11
Reset Tx Underrun/End of Message
Latch.
02
Status Affects vector-(WR1, 02
active in channel B only.) If this
bit is not set, then the fixed vector,
programmed in WR2, is returned
from an interrupt acknowledge
sequence. If the bit is set then the
vector returned from an interrupt
. acknowledge is variable as shown
in the Interrupt Vector Table.
Write Register 1 (WR1):
MSB
I
LSB
D71 D6
I
Dsl D4 : D31 D21 D1
'--...,--J
I I
I
DO
EXT INTERRUPT
ENABLE
TxINTERRUPT/
04,03
Receive Interrupt Mode
o
o
Receive Interrupts/OMA Disabled
0
"Receive Interrupt on First Character Only or Special Condition
DMAENABLE
o
STATUSAFFECTS
VECTOR (CH B ONLY)
(NULLCODECH AI
1'" VARIABLE
VECTOR
0 FIXED
VECTOR
,....----....
0
0
RxlNT/OMA DISABLE
0
1
RxiNT ON FIRST CHAR OR SPECIAL
CONOITldN
1
0
INT ON ALL Rx CHAR (PARITY AfFECTS
VECTOR) OR SPECIAL CONDITION
1
1
Interrupt on All Receive Characters or Special Condition (Parity
Error is not a Special Receive
Condition).
INT ON ALL Rx CHAR (PARITY DOES
NOT AFFECT VECTOR) OR SPECIAL
05
Wait on ReceivelTransmit-when
the following conditions are met
the ROY pin is activated, otherwise
it is held in the High-Z state.
(Conditions: Interrupt Enabled
Mode, Wait Enabled, CS = 0,
AO = 0/1, and A1 = 0). The ROY
pin is pulled low when the transmitter buffer is full or the receiver
buffer is empty and it is driven
I-'Iigh when the transmitter buffer is
empty or the receiver buffer is full.
The ROYA .and ROY e may be
wired OR connected since ,only
one signal is active at anyone time
while the other is in the High Z
state.
06
Must be Zero
07
Wait Enable-enables the wait
function.
CONDITION
1 == WAIT ON Rx, 0 '" WAIT ON Tx
MU$T BE ZERO
WAIT ENABLE 1 == ENABLE, 0 == DISABLE
WR1
DO
Intern.lpt on All Receive Characters or Special Condition (Parity
Error is a Special Receive Condition)
External/Status Interrupt Enable
-allows interru!'>t to occur as the
result of transitions on the CO,
CTS or SYNOET inputs. Also
allows interrupts as the result of a
Break/Abort detection and termination, or at the beginning ofCRC,
or sync character transmission
when the Transmit Underrun/EOM
latch becomes set.
7-211
AFN·01701C
inter
WR2
8~7~.
""'J'
, 05,04,03
C!1annelA
01, DO
System Configuration-These
specify the data transfer from
MPSC channels to the CPU, either.
interrupt or OMA based.
o
0
Channel A and Channel B both use
interrupts
o
1
Channel A uses OMA, Channel B
uses interrupt
0' X X
0
8085 Vector Mode 1-intended for
use as the primary MPSC in a daisy
,chained priority structure. (See
System Interface secti,on)
o
1
8085 Vector Mode 2-intended for
use as any secondary MPSC in a
daisy chained priority structure.
(See System Interface section)
o
8086/88 Vector Mode-intended
lIIe'lal Code
Priority-this bit specifies the
relative priorities of the internal
MPSC interruptlOMA sources.
o
(Highest) RxA, TxA, RxB, TxB
ExTA, ExTB (Lowest)
for use as eitlier a 'primary or
secondary in a daisy chained
priority structure. (See System
Interface 'section)'
(Highest) RxA, RxB, TxA, TxB,
ExTA, ExTB (Lowest)
06
07
Write Register 2 (WR2): Channel A
07
Must be zero.
zero
one
MSB
I
Non-vectored interrupts-intended' for use with-external OMA
CONTROLLER. The Data Bus remains in a high impedence state
during INTA sequences.
1 0
Channel A and Channel B both
use OMA.
02
In.terrupt Code-specifies the
behavior of the MPSC when it receives an interrupt acknowledge
sequence from the CPU. (See Interrupt Vector Mode Table).
Pin 10 =RTSB I
Pin 10 = SYNOETB
LSB
: De
I I
05
I 1 I
02
04 : 03
01 : DO
'----..----'
'----..----'
0
0
BOTH INTERRUPT
0
1
A DMA. B INT
1
0
BOTHoMA
1
1
ILLEGAL
I
1
PRIORITY AxA
RxB
TxA
TxB
EXTA'
EXTB'
0
PRIORITY RxA
TxA
RxB
TxB
eXTA*
EXTS"
~
0
0
8085 MODE 1
0
1
8085 MODE 2
1
0
8086/88 MODE
1
1
ILLEGAL
r
1
VECl'oREO INTERRUPT
0' NON VECTORED INTERRUPT
MUSTSE ZERO
1
i'Y'N'iiEf B
PIN 10
o
PIN 10
I
ATS e
'EXTERNAL STATUS INTERRUPT·
ONLY IF EXT INTERRUPT ENABLE (WR1; DO)IS SET
7-212
AfN.01701C
intJ
8274
The following table describes the MPSC's response to aninterrupt acknowledge sequence:
Data
Bus
ft'IODE
INTA
X
Non-vectored
Any INTA
0
85 Mode 1
1st INTA
2nd INTA
3rd INTA
0
0
0
0
0
1
0
1
D5
D4
D3
IPI
0
X
X
1
0
0
DO
07
High Impedance,
0 1
1
1
1 1 0 0
V7 V6 V5 V4' V3' V2' V1 VO
0 0
0
1
0
0
1
85 Mode 1
1st INTA
2nd INTA
3rd INTA
1
1 1 0 0
High Impedance
High Impedance
1
1
0
0
86 Mode
1st INTA
2nd INTA
High Impedance
V7 V6 V5 V4 V3
1
0
1
0
85 Mode 2
1st INTA
2nd INTA
3rd INTA
High Impedance
V7 V6 V5 V~' V3' V2' V1 VO
0 0 0 0
0 0
0 0
1
0
1
1
85 Mode 2
1st INTA
2ndiNTA
3rd INTA
High Impedance
High Impedance
High Impedance
1
1
O'
1
86 Mode
'1st INTA
2nd INTA
High Impedance
High Impedance
V2' V1'VO'
'These bits are vanable /I the "status affects vector" mode has been programmed, (WR1 B, D2).
Interrupt/DMA Mode, Pin Functions, and Priority
Ch.A WR2
Int/DMA
Mode
D2
D1
Do
CH,A
CH.B
0
0
0
INT
INT
1
0
0
INT
INT
0
0
1
OMA
--INT
1---
1
0
1
-OMA
- - - -INT
0
1
0
OMA
OMA
1
1
0
OMA
OMA
RDYAI
RxDRQ A
Pin 32
ROYA
Pin Functions
IPII
RDYel
TxDRQ A
RxDRQ e
Pin 11
Pin 29
iPi
ROY e
Priority
IPOI
TxDRQ e
Pi~.30
Highest
Lowest
RxA, TxA. RxB. TxB. EXTA> EXTe
IPO
RxA. RxB. TxA. TxB, EXTA> EXTe
RxA. TxA (OMA)
RxORO A
iPi
TxOROA
'-------------RxA 1, RxB. TxB. EXT , EXTe(INT)
A
IPO
RxA, TxA (OMA)
~A\RxB,TxB, EX~ EXTe(INT)- RxA TxA. RxB, TxB (OMA)
RxA \ RxB 1, ·EXTA> EXTe (INT)
RxOROA
TxOROA
RxORO e
TxORO e
RxA, RxB, lxA. TxB. (OMA)
RxA 1, RxB ,EXTA> EXT e (INT)
1Special Receive C':!ndition
7-213
AfM.01701C
intJ
8274
Interrupt Vector Mode Table
I
8085 Modes
V4
8086/88 Mode
V2
Note 1: Special
Receive Condition=
Parity Error,
Rx Overrun Error.
Framing Error,
End of Frame (SOLC)
V3
V1
V2
""
Vo
Channel
'0
0
0
0
0
0
1
1
0
1
0
.1
B
Tx Buffer Empty
ExtlStatus Change
Rx Char. Available
Special Rx Condition
(Note 1)
1
1
1
1
0
0
1
1
0
1
0
1
A
Tx Buffer Empty
Ext/Status Change.
Rx Char. Available
Special Rx Condition
(Note 1)
Write Register 2 (WR2): Channel B
Condition
WR2 CHANNEL B
07-00
Interrupt vector-This register contains
the value of the interrupt vector placed
on the data bus during interrupt acknowledge sequences.
Write Register 3 (WR3):
• MSB
Rx ENABLE
SYNC CHAR LOAD INHIBIT
L -_ _ _ AOOR SRCH MODE (SOLC)
' - - - - - - - R x CRC ENABLE
' - - - - - - - - E N T E R HUNT MODE
L - - - - - - - - - A U T O ENABLES
Rx 5 BITS/CHAR
Ax 7 BITS/CHAR
Rx 6 BITS/CHAR
Rx 8 BITS/CHAR
7-214
AFN-01701C
intJ
WR3
DO
01
8274
Write Register 4 (WR4):
Receiver Enable-A one enables the reo
ceiver to begin. This bit should be set only
after the receiver has been initialized.
Sync Character Load Inhibit-A one prevents the receiver from loading sync
characters into the receive buffers. In
SOLC. this bit must be zero.
02
1 • ENA'LE PARITY
o • DISA'LE PARITY
1 :: EVEN PARITY
o • ODD PARITY
Address Search Mode-If the SOLC mode
has 'been selected. the MPSC will receive all frames unless this bit is a 1. If this
bit is a 1. the MPSC will receive only frames
with address bytes that match the global
address (OFFH) or the value loaded into
WR6. This bit must be zero in non-SOLC
modes.
03
Receive CRC Enable-A one in this bit
enables (or re-enables) CRC calculation.
CRC calculation starts with the last character placed in the Receiver FIFO. A zero in
this bit disables. but does not reset. the
Receiver CRC generator.
04
o
Enter Hunt Phase--After initialization. the
MPSC automatically enters the Hunt mode.
If synchronization is lost. the Hunt phase
can be re-entered by writing a one to this
bit.
'
07. 06
Receive Character length
o
o
Receive 5 Data bits/character
0
o
Receive 8 Data bits/character
7-215
1.5 STOP lilTS
1
1
2 STOP lilTS
"IT SYNC CHAR
1
0
SDLClHDLCMODEI0111,1110IF~G
1
1
EXTERNAL SYNC MODE
X1 CLOCK
X18CLOCK
1
1
X84CLOCK
03. 02
1 STOP
0
11111T SYNC CHAR
X32CLOCK
Receive 6 Data bits/character
1
1
1
, 01
,IT
o
1
0
0
Receive 7 Data bits/character
ENA'LE SYNC MODES
o
o
ao
0
o
1
WR4
DO
Auto Enable-A one written to this bit causes
CD to be automatic enable signal for the
receiver and CTS to be an automatic enable
signal for the transmitter. A zero written to
and CTS signals
this bit limits the effect of
to setting/resetting their corresponding bits
in the status register (RRO).
05
0
o
Parity-a one in this bit causes a parity
bit to be added to the programmed number
of data bits per character for both the
transmitted and received ,character. If the
MPSC is programmed ,to receive 8 bits per
character, the parity bit is not transferred
to the microprocessor. With other receiver
character lengths. the parity bit is transferred to the microprocessor.
Even/Odd Parity-if parity is enabled. a
one in this bit causes the MPSC to transmit
and expect even parity, and a zero causes
it to send and expect odd parity.
Stop bits/sync mode
AFNo01701C
inter
o
0
8274.
Selects synchronous modes.
o
Transmit CRC Enable-a one in this bit
enables the transmitter CRC generator.
The CRC calculation I is done when a
character is moved from the transmit
buffer into the shift register. A zero in this
bit disables CRC calculations. If this bit is
not set when a transmitter underrun
occurs, the CRG will not be sent.
Async mode, 1 stop bit/character
o
Async mode, 1-V2 stop 'bits/character
Async mode, 2 stop bits/character
1
OS, 04
Sync mode select
o
8 bit sync character
0
o
01
Re~t t.o Send-a one in this bit forces
the RTS pin active (low) and zero in this bit
forces the RfS pin inactive (high).
External sync mode
02
Clock mode-selects the clock/data rate
multiplier for both the receiver and the
transmitter. 1x mode must be selected for
synchronous modes. If the 1 x mode is
selected, bit synchronization must be done
externally.
CRC Select-a one in this bit selects the
CRC -16 polynomial (X 16 + X15 + X2 + 1)
and a zero fn this bit selects the CCITT-CRC
polynomial (X 16 + X12 + X 5 + 1). In SOLC
mode, CCITT-CRC must be selected.
03
.Transmitter Enable-a zero in this bit
forces a marking. state on the transm itter
output. If this bit is set to zero during data
or sync character transmission, the marking state is entered after the character has
been sent. If this bit is set to zero during
transmission of a CRC character, sync or
flag bits are substituted for the remainder
of the CRC bits.
04
Send Break-a one in this bit forces ~he
transmit data low. A zero in this bit allows
normal transmitter operation.
06, 05
Transmit Character length
o 0
Transmit 1 - 5 bits/character
o
Transmit 7 bits/character
16 bit sync character
o
SOLC mode (Flag sync)
07, 06
o
WRS
DO
Clock rate = Data rate x
0
o
Clock rate = Data rate x 16
o
Clock rate = Data rate x 32
Clock rate = Data rate x 64
Write Register 5 (WRS):
RTS
, - -_ _ SDLClCRC·16 (CRC MODE)
o
' - - - - - T l c ENABLE
Transmit 6 bits/character
' - -_ _ _ _ _ SENiiBiteAK
Transmit·8 bits/character
o
Tlc 5 BITS OR LESs/CHAR
Bits to be sent must be right justified least significant
bit first, eg:
Tx 7 BITS/CHAR
Tx 6 BITS/CHAR
Tlc 8 BITS/CHAR
L..-_ _ _ _ _ _ _ _ _ _ DTR
7-216
07
06
05
04
03
D2
D1
DO
o
0
B5
B4
B3
B2 .B1
BO
AFN'()1701C
inlef
8274
Five or less mode allows transmission of one to five bits per
character. The microprocessor must format the data in
the following way:
07
0
07
03
02
01
DO
0
0
0
BO
Sends one data bit
0
0
0
,B1
BO
Sends two data bits
0
0
0
B2
B1
BO
Sends three data bits
0
0
0
B3
B2
B1
BO
Sends four data bits
0
0
B4
B3
B2
B1
BO
Sends five data bits
06
05
04
Data Terminal Ready-when set, this bit
forces the OTR pin active (low). When
reset, this bit forces the OTR pin inactive
(high).
Write Register 7 (WR7):
Write Register 6 (WR6):
LSB
MSB
MSB
LSB
I~:~:~:~:oo:oo:~:ool
Least significant
1M.5t Significant
Sync byte (Address
In SOLe/HOLe Mode)
Sync byte (must
be 01111110 In
SOLe/HOLe Mode)
WR7
07-00
WR6
07-00
Sync/Address-this register contains the
transmit sync character in Monosync
mode, the low order 8 sync bits in Bisync
mode, or the Address byte in SOLC mode.
7-217
Sync/Flag-this register contains the receive sync charaCter in Monosync mode,
the high order 8 sync bits in Bisync mode,
or the Flag character (01111110) in SOLC
mode. WR7 is not used in External Sync
mode.
AFN-01701C
8274 ·
Read Register 0 (RRO):
MS.
LS.
I~I~I~I~I~I~I~I~I
I
, Ax CHAR AVAILABLE
Int PENDING (CHA ONLY)
TIC BUFI!ER EMPTY
CARRIER DETECT
SYNC/HUNT
EXTERNAL STATUS
INTERRUPT MODE
CTS
/
TIC UNDERRUNlEOM
BREAK/ABORT
RRO
DO
Receive Character Available-this bit is
set when the receive FIFO contains data
and is reset when the FIFO is empty.
01
Interrupt Pending*-This Interrupt-Pending bit is reset when an EOI command is
issued and there is no other" interrupt request pending at that time.
02
Transmit Buffer Empty-This bit is set
whenever the transmit buffer is empty
except when CRC characters are being
sent in a synchronous mode. This bit is
reset when the transmit buffer is loaded.
This bit is set after an MPSC reset.
03
Carrier Detect-This bit contains the state
of the CO pin at the time of the last change
of any of the External/Status bits (CD.
CTS. Sync/Hunt. Break/Abort. or Tx
Underrun/EOM). Any change of state of the
CD pin 'causes the CD bit to be latched and
causes an External/Status interrupt. This bit
indicates current state of the CD pin immediately following a Reset External/Status
Interrupt command.
04
Sync/Hunt-In asynchronous modes, the
operation of this bft is similar to the CD
status bit, except that Sync/Hunt shows the
state of the SYNDET....!!!.e.!!.L.Any High-toLow transition on the SYNDET pin sets this
bit, and causes 'an External/Status interrupt (if enabled). The Reset External/Status
Interrupt command is issued to clear the
interrupt. A Low-to-High transition clears
this bit and sets the External/Status interrupt. When the External/Status interrupt is
set by the change In state of any other input
or condition. this bit shows the inverted
state of the SYNDET pin at time of the
change. This bit must be read immediately
following a Reset External/Status Interrupt
command to read the current state of the
SYNDET input.
I~the
External Sync mode, the Sync/Hunt
bit operates in a fashion similar to the
Asynchronous mode, except the Enter
Hunt Mode control bit enables the external
sync detection logic. When the External
Sync Mode and Enter Hunt Mode bits are
set (for example, when the receiver is
enabled follo..,ing a reset). the SYNDET
input must be held High by the external
logic until external character synchronization is achieved. A High at the SYNDET
input holds the Sync/Hunt status in the
reset condition.
*In vector mode this bit is set at the falling edge of
the second i'iii'fA in an INTA cycle for an internal
interrupt request. In non-vector mode. this bit is
set at the falling edge of AD input after pointer 2
is specified. This bit is. always zero in Channel B.
7-218
AfN.Ol701C
intJ
8274
When external synchronization is
achieved, SYNOET must be driven Low on
the second rising edge of RxC after the
rising edge of RxC on which the last bit of
the sync character was received. In other
words, after the sync pattern is detected,
the external logic must wait for two full
Rec~ive Clock cycles to activate the SYNOET inp~t. Once SYNOET is forced Low, it
is good practice to keep it Low until the
CPU informs the external sync logic that
synchronization has been lost or a new
message is about to start. The High-to-Low
transition of the SYNOET output sets the
Sync/Hunt bit, which sets the External/
Status interrupt. The CPU must clear the
interrupt by issuing the Reset External/
Status Interrupt Command.
When the SYNOET input goes High again,
another External/Status interrupt is generated that must also be cleared. The Enter
Hunt Mode control bit isset whenever
character synchronization is lost or the end
of message is detected. In this case, the
MPSC again looks for a High-to-Low transition on the SYNOET input and the operation repeats as explained previously. This
implies the CPU should also inform the externallogic that character synchronization
has been lost and that the MPSC is waiting
for SYNOET to become active.
In the SOLC mode, the Sync/Hunt bit is
initially set by the Enter Hunt mode bit, or
when the receiver is disabled. In any case, it
is reset to D when the opening flag of the
first frame is detected by the MPSC. The
External/Status interrupt is also generated,
and should be handled as discussed
previously.
Unlike the Monosyn~ and Bisync modes,
once the Sync/Hunt bit is reset in the SOLC
mode, it does not need to be set when the
end of message is detected. The MPSC automatically maintains synchronization.
The only way the Sync/Hunt bit can be set
again is by the Enter Hunt Mode bit, or by
disabling the receiver.
05
Clear to Send-this bit contains the inverted state ofthe CTS pin at the time of the
last change of any of the External/Status
bits (CD, CTS, Sync/Hunt, Break/Abort, or
Tx Underrun/EOM). Any change of state o.f
the CTS pin causes the CTS bit to be
latched and causes an External/Status
interru·pt. This bit indicates the inverse of
the current state of the CTS pin immediately following a Reset External/
Status Interrupt command.
In the Monosync and Bisync Receive
modes, the Sync/Hunt status bit is initially
set to 1 by the Enter Hunt Mode bit. The
Sync/Hunt bit is reset when the MPSC establishes character synchronization. The
High-to-Low transition of the Sync/Hunt bit
causes an External/Status interrupt that
must be cleared by the CPU issuing the
Reset External/Status Interupt command.
This enables the MPSC to detect the next
transition of other External/Status bits.
06
Transmitter Underrun/End of Messagethis bit is in aset condition following a reset
(internal or external). The only command
that can reset this bit is the Reset Transm it
Underrun/EOM Latch command (WRD, 0 6
and D7). When the Transmit Underrun condition occurs, this bit is set, which causes
the External/Status Interrupt which must
be reset by issuing a Reset External/Status
command (WRD; command 2).
When the CPU detects the end of message
or that character synchronization is lost, it
sets the Enter Hunt Mode control bit, which
sets the Sync/Hunt bit to 1. The Low-toHigh transition of the Sync/Hunt bit sets the
External/Status Interrupt, which must also
be cleared by the Reset External/Status
Interrupt Command. Note that the SYNOET
pin acts as an output in this mode, and
goes low every time a sync pattern is detected in the data stream.
..D7
Break/Abort-in the Asynchronous Receive mode, this bit is set when a Break
sequence (null character plus framing
error) is detected in the data stream. The
External/Status interrupt, if enabled, is set
when break is detected. The interrupt service routine must issue the Reset
External/Status Interrupt command (WRD,
Command 2) to the break detection logic
SO the Break sequence termination can be
recognized.
AFN-01701C
8274
SOLC Residue Code Table (I Field Bits in 2 Previous Bytes) ,
8 bits/char
RR1
Previous
Byte
03,02,01
7 bits/char
2nd Prevo
Byte
Previous
Byte
.5 bits/char
6 bits/char
2nd Prevo
Byte
Previous
Byte
2nd Prevo
Byte
Previous
Byte
2nd Prevo
Byte
5
1
0
0
0
3
0
2
0
1
0
0
1
0
0
4
0
3
0
2
0
1
1
1
0
0
5
0
4
0
3
0
2
0
0
1
0
6
0
5
0
4
0
3
1
0
1
0
7
0
6
0
5
-
0
1
1
0
8
0
-
-
-
-
1
1
1
1
8
-
-
-
-
-
0
0
0
2
8
1
7
0
6
0
The Break/Abort bit is reset when the term ination of the Break sequence is detected
in the incoming data stream. The termination of the Break sequence also causes the
External/Status interrupt to be set. The
Reset External/Status Interrupt command
must be issued to enable the break detection logic to look for the next Break sequence. A single extraneous null character
is present in the receiver after the termination of a break; it should be read and
discarded.
00
In the SOLC Receive mode, this status bit is
set by the detection of an Abort sequence
(seven or more 1's). The External/Status
interrupt is handled the same way as in the
case of a Break. The Break/Abort bit is not
used in the Synchronous Receive mode.
04
4
All sent-this bit is set when all characters have been sent, in asynchronous
modes. It is reset when characters are in
the transmitter, in asynchronous modes.
In synchronous modes, this bit is always
set.
03, 02, 01 Residue Codes-bit synchronous protocols allow I-fields that are not an integral number of characters. Since transfers from the MPSC to the CPU are character. oriented, the residue codes
provide the capability of receiving
leftover bits. Residue bits are right justified in the last two data bytes received.
7-220
Parity Error-If parity is enabled, this bit
is set for received characters whose parity does not .match the. programmed
sense (Even/Odd). This bit is latched.
Once an error occurs, it remains set until
the Error Reset command is written.
AFN-01701C
8274\
Read Reglater 1 (RR1): (Special Receive Condition Mode)
MSB
I 1I
07
01
OIl D4
I
,
LSB
03 : 02 : 01
I I
DO
I
I
,
I
\
LALLSE NT
I FIELD BITS
PREVIDUS8VTE
000
2
o 0 1
0
o 1 0
0
o 1 1
0
1 0 0
0
1 0 1
0
1 1 0
0
1 1 1
1
RESIDUE DATA
8 BITS/CHAR. MODE
PARITY ERROR
Rx OVER~UN ERROR
CRC/FRAMING ERROR
END OF FRAME (SDLClHDLC MODE)
05
06
Receive Overrun Error-this bit indicates that the receive FI FO has been
'overloaded by the receiver. The last
character in the FIFO is overwritten 'and
flagged with this error. Once the overwritten character is read, this error condition is latched until reset by the Error
Reset command. If the MPSCis in the
status affects vector mode, the overrun
causes a special Receive Condition
Vector.
ing error. In synchronous modes, a one
in this bit indicates that the' calculated
CRC value does not match the last two
bytes received. It can be reset by issuing
an Error Reset command.
07
CRC/Framing Error-In async modes, a
one in this bit indicates a receive fram-
7-221
End of Frame-this bit is valid only in
SOLC mode. A one indicates that a valid
ending flag has been received. This bit is
reset either by an Error Reset command
or upon reception of the first character
of the next frame.
AFN-01701C
inter·'
8274
Read Register 2 (RR2):
Msa
LSB
DMA operation is accomplished viii an external DMA
controller. When the MPSC needs a data transfer, it
request a DMA cycle from the DMA controller. The
DMA controller then takes control of the bus and
simultaneously does a read from the MPSC and
write'to memory or vice-'ilersa.
a
* variable In
,,:lni:".="~UP~1_ _ _ _ StatuI Affecta
Vector
Vector Mode (WR1 j 02)
RR2
07-00
Channel B
Interrupt vector-contains the interrupt
vec~or programmed into WR2. If the status
affects vector mode is selected (WR1; D2), it
contains the modified vector (See WR2). RR2
contains the modified vector for the highest
priority interrupt pending. If no interrupts are
pendi ng, the variable bits in the vector are set
to one.
SYSTEM INTERFACE
·General
The MPSC to Microprocessor System interface can
be configured in many flexible ways. The basiq interface types are polled, wait, interrupt driven, or direct
memory access driven.
Polled operation is accomplished by repetitively
reading the status of the MPSC, and making decisions based on that status. The MPSC can be polled
at any time.
The following section describes the many configurations of these basiC types of system interface
techniques for botn serial channels.
POLLED OPERATION:
In the polled mode, the CPU must monitor the desired conditions within the MPSC by reading the appropriate bits in the read registers. All data available,
status, and error conditions are represented by the
appropriate bits in read registers 0 and 1 for channels A and B.
There are two ways in which the software task of
monitoring the status of the MPSC has been reduced. One is the "DRing" of all conditions into the
Interrupt Pending bit. (RRO; D1 channel A only). This
bit is set when the MPSC requires service, allowing
the CPU to monitor one bit instead of four status registers. The other is available when the "statusaffects-vector" mode is selected. By reading RR2
Channel B, the CPU can read a vector who's value
will indicate that one or more of group of conditions
has occurred, narrowing the field of possible conditions. See WR2 and RR2 in the Detailed Command
Description section.
Software.Flow, Polled Operation
Wait operation allows slightly faster data throughput
forthe MPSC by manipulating the Ready inputtothe
microprocessor. Block Read or Write Operations to
the MPSC are started at will by the microprocessor
and the MPSC del;lctivates its ROY signal if it is not
yet ready to transmitthe new byte, or if reception of
.new byte is not completed.
Interrupt driven operation is accomplished via an
internal or external interrupt controller. When the
MPSC requ ires service, it sends an interrupt request
signal to the microprocessor, which responds with
an interrupt acknowledge signal. When the internal
or external interrupt controller receives the acknowledge, it vectors the microprocessor to a servide routine, in which the transaction occurs.
REC,EIVE
ARO, DO IS
TRANSMIT
reset automatICally when the data IS' read
AAO. 02 IS reset automatically when the data IS written
7-222
AFN'()1701C
inter
8274
Hardware Configuration, Polled Operation
l
....
ADDRESS BUS
&
II
A DATA BUS
iii!
WII
...-8205
'--
~
p""':=:=
Ao
A,
U
VCC
DBG-7
C-
'iNii
MPSC
CS
RD
WR
instruction (8085 mode) and interrupt vector (8085
and 8088/86 mode) on the data bus.
WAIT OPERATION:
Wait Operation is intended to facilitate data transmission or reception using block move operations. If
a block of data is to be transmitted, for example, the
CPU can execute a String I/O instruction to the
MPSC. After writing the first byte, the CPU will attempt to write a second byte immediately as is the
case of block move. The MPSC forces the ROY
signal low which inserts wait states in the CPU's
write cycle until the transmit buffer is ready to accept a new byte. At that time, the ROY signal is high
allowing the CPU to finish the write cycle. The CPU
then attempts the third write and the process is
repeated.
The MPSC can be programmed to cause an interrupt
due to up to 14 conditions in each channel. The
status of these interrupt conditions is contained in
Read Registers 0 and 1. These 14 conditions are all
directed to cause 3 different types of internal interrupt request for each channel: receive/interrupts,
transmit interrupts and external/status interrupts (if
enabled).
This results in up to 6 internal interrupt request
signals ..The priority of those signals can be programmed to one of two fixed modes:
Similar operation can be programmed for the receiver. During initialization, wait on transmit (WR1;
05 = 0) or wait on receive (WR1; 05 = 1) can be
selected.The wait operation can be enabled/
disabled by setting/resetting the Wait Enable Bit
(WR1; 07).
Highest Priority
Lowest Priority
RxA RxB TxA TxB ExTA
RxA TxA RxB TxB ExTA
ExTB
ExTB
The interrupt priority resolution Works dif(erently for
vectored and non-vectored modes.
CAUTION: ANY CONDITION THAT CAN CAUSE THE
TRANSMITTER TO STOP (EG, CTS GOES INACTIVE) OR THE RECEIVER TO STOP (EG, RX DATA
STOPS) WILL CAUSE THE MPSC TO HANG THE
CPU UP IN WAIT STATES UNTIL RESET. EXTREME
CARE SHOULD BE TAKEN WHEN USING THIS FEATURE.
PRIORITY RESOLUTION: VECTORED MODE
Any .Interrupt condition can be accepted internally
to the MPSC at any time, unless the MPSC's internal
INTA signal is active, unless a higher priority interrupt is currently accepted, or if i15i' is inactive (high).
The MPSC's iriternallNTA is set on the leading (failing) edge of the first External INTA pulse and reset
on the trailing (rising) edge of the second External
INTA pulse. After an interrupt is accepted internally,
an External INT request is generated and the jj5Q
goes inactive. iPO and iPi are used for daisychaining MPSC's together.
INTERRUPT DRIVEN OPERATION:
The MPSC can be programmed into several interrupt modes: Non-Vectored, 8085 vectored, and
8088/86 vectored. In both vectored modes, multiple
MPSC's can be daisy-chained.
In the vectored mode, the MPSC responds to an
interrupt acknowledge sequence by placing a call
7-223
AFN'()1701C
8274
Interrupt Condition Grouping
MODE
CONDITION
RECEIVE CHARACTER - - - - - - - - - - - - 1 ! > 1
INTERNAL INTERRUPT
REQUEST
R~~~~::g~~:C~~~S
PARITY ERROR===",...--.rsP'Ec:iAiC"l
RECEIVE OVERRUN ERROR - - +
FRAMING ERROR
•
END OF FRAME (SDLC ONLY)_u.cl>---- CS'
Ao-----~
A1---;::-----;
cs
DMATiming
DRQ,~
\'-------
>C
A"A"CS---""'X'--_ _ _ _ _-'-_ _ _
....J/
iiD, Wii - - - - - -...\ ..._ _ _ _ _ _
DMA OPERATION
Each MPSC can be programmed to utilize up to four
DMA channels: Transmit Channel A, Receive Channel A, Transmit Channel B, Receive Chal1nel B. Each
DMA Channel has an associated DMA Request line,
Acknowledgement of a DMA cycle is done via normal data read or write cycles. This is accomplished
by encoding the DACK signals to generate A o, A"
and CS signals, and multiplexing them with the
normal Ao. A,. and CS signals.
permutations of interrupt. wait. and DMA modes for
channels A and B. Bits D" Do of WR2 Ch. A determine these permutations.
Permutation
WR2 <;h. A
0,
Do
Channel A
ChannelB
00
Walt
Interrupt
Polled
Wait
Interrupt
Polled
Interrupt
Polled
o1
DMA
Polled
PERMUTATIONS
Chanllels A and B can be used with different system
interface modes. In all cases it is impossible to poll
the MPSC. The following table shows the possible
1 0
DMA
DMA
-Polled
Polled
D1, DO = 1. 1 is illegal.
7-229
AFN-01701C
inter
8274
....
DE
A18-A18
01
ALE
~
'11-A11
00
ST8
"--
~
828"
....
jjjj
READY
Wi!
-
'-
~
"'I-A15
A8-.415
~VCC
K~
A~=Ot~
~B'''O'~
:~ ~O,~
A,
84
eLK
.-f-
O,~
01
DO
Bra
8212
T-
OE'
I
RESET
I,- ,
r--r--
I
.....
HLOA
,..-~
@1
CLR
0.-0
HLOA
0
HRO
7"LS74
eLK
AEN
1m!
...
00,-00,
I
~
08,
DB.
DO-0 7
~
I
H
I
8282 ITI
OE 01,D1 1
....
ADO-AD7
HOLD
1274
flOW
READY
eLK
RESET
ADSTI
1237 A.-A
RxDR 0,
DROI)
am. I-ORO,
am,
DRQ
am,
2
ii
"'000
-
1bo.
"
f
, .......
r
AIDA 0,
MULTIPLEXER
r-
01'
A.
I
A,
-yo
.....
T~DR 0,
I
I
I ..
-t>-~
I
(FROMI20S)
--------1
i-..
:V
eB
I
It--I:::''------J
V
lIIi
~
7-230
PROGRAMMING HINTS
li'ansmlt Under-run/EOM Latch
This section will describe some useful programming
hints which may be useful in program development.
In SOLC/HOLC. bisync and monosync mode. the
transmit under-run/EOM must be reset to enable the
CRC check bytes to be appended to the transmit frame
or transmit message. The transmit under-run/EOM .
latch can be reset only after the first character is loaded
into the transmit buffer. When the transmitter underruns at the end of the frame. CRC check bytes are
appended to the frame/message. The transmit underrun/EOM latch can be reset at any time during the
transmission after the first character. However. it should
be reset before the transmitter under-runs otherwise.
both bytes of the CRe may not be appended to the
frame/message. In the receive mode in bisync operation. the CPU must read the CRC bytes and two more
SYNC characters before checking for valid CRC result
in RR1.
Asynchronous Operation
At the end of transmission. the CPU must issue "Reset
Transmit InterrupVOMA Pending"command in WROto
reset the last transmit empty request which was not
satisfied. Failing to do so will result in the MPSC
locking up in a transmit emptY. state forever.
Non-Vectored Mode
In non"vectored mode. the Interrupt Acknowledge pin
(INTA) on the MP$C must be tied high through a
pull-up resistor. Failing to do so will result in unpre:dictable response from the 8274.
HOLC/SOLC Mode
When receiving data in SOLC mode. the CRC bytes
. must be read by the CPU (or OMA controller) just like
any other data field. Failing to do so will result in
receiver buffer overflow. Also. the End of Frame Interrupt indicates that the entire frame has been received.
At this pOint. the CRC result (RR1:06) and residue code
(RR1;03. 02. 01) may be checked.
Status Register RR2
RR2 contains the vector which gets modified to indicate
the source of interrupt (See the section titled MPSC
Modes of Operation). However. the state of the. vector
does not change if no new interrupts are generated.
The contents of RR2 are only changed when a new
interrupt is generated. In order to get the correct
information. RR2 must be read only after an interrupt is
generated. otherwise it will indicate the previous state.
Sync Character Load Inhibit
In bisync/monosync mode only. it is possible to prevent
sync characters into the receive buffers by
setting the sync character load inhibit bit (WR3;01=1).
Caution must be exercised in using this option. It may
be possible to get a CRC character in the received
message which may match the sync character and not
get transferred to the receive buffer. However. sync
character load inhibit should be enabled during all
pre-frame sync characters so the software routine does
not have to read them from the MPSC.
lo~ding
In SOLC/HOLC mode. sync character load inhibitpit
must be reset to zero for proper operation.
EOI Command
EOI command can only be issued through channel A
irrespective of which channel had generated the
interrupt.
Priority in OMA Mode
Initialization Sequence
The MPSC initialization routine must issue a channel
Reset Command at the beginning. WR4 should be
defined before other registers. At the end of the
initialization sequence. Reset External/Status and Error
Reset commands should be issued to clear any
spurious interrupts which may have been caused at "
power up.
There is no priority in OMA mode between the following four signals: TxORQ(CHA). ·RxORQ(CHA).
TxORQ(CHB). RxORQ(CHB). The priority between
these four signals must be resolved by the OMA
controller. At any given time. all four OMA channels
from the 8274 are capable of going active.
7-231
AFN-01io1C
8274
ABSOLUTE MAXIMUM RATING.S*
Ambient Temperature
ynder.Bias ............... , ........ O°C to +70°C
Storage Temperature
(Ceramic Package) ............. -65°C to +150°C
(Plastic Package) .............. -40°C to +125°C
Voltage On Any Pin With
Respect to Ground .............. -O.5V to +7.0V
D.C. CHARACTERISTICS
Symbol
'NOTlCE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sedtions of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
(T. = O"C to 70"C; Vee = +5V ±10%)
Min.
Input Low Voltage
-0.5
+0.8
+2.0
Vee +0.5
V
+0.45
V
IOL = 2.0mA
V
IOH = -200pA
V,H
Input HlghVoltage
VOL
Output Low Voltage
VOH
Output High Voltage
I,L
Input Leakage Current
Max.
+2.4
Units
Test Conditions
Para metter
V,L
V
±10
pA
V,N = Vee to OV
IOL
Output Leakage Current
±10
pA
VOUT=VeetoOV
lee
Vee Supply Current
180
mA
CAPACITANCE (T.
= 25°C; Vee = GND = OV)
Test Conditions
Max.
Units
C'N
Input Capacitance
10
pF
fc = 1 MHz;
COUT
Output Capacitance
15
pF
Unmeasured
CliO
Input/Output Capacitance
20
pF
Symbol
Min.
Parameter
,
pins returned
toGND
7-232
. AFN-01701C
8274
A.C. CHARACTERISTICS.
Symbol
(T.
= O°C to
70°C; Vcc
=
+5V ±10%)
Min.
Max.
Units
tCY
CLK Period
250
4000
ns
tCL
ClK low Time
105
2000
ns
tCH
ClK High Time
105
2000
ns
tr
ClK Rise Time
0
30
ns
tf
ClK Fall Time
0
30
ns
tAR
AO, AI Setup to RD)
0
tAD
AO, Alto Data Output Dlay
200
ns
tRA
AO. AI Hold After RD!
tRO
RD) to Data Output Delay
tRR
AD
Parameter
Pulse Width
Test Conditions
ns
CL~150
pi
CL~150
pi
ns
0
200
ns
ns
250
120
ns
tOF
Output Float Delay
tAW
CS, AO, AI Setup to WR)
0
ns
tWA
CS, AO, AI Hold after WR!
0
ns
tww
WR Pulse Width
tow
Data Setup to WR!
tWD
Data Hold Alter WR!
tpi
tiP
ns
250
150
ns
0
ns
iPi Setup to INTA)
0
ns
IPI Hold after INTA!
10
ns
til
INTA Pulse Width
250
tplPO
IPI) to IPO Delay
100
ns
tiD
INTA) to Data Output Deay
200
ns
tca
AD or WR to ORO)
150
ns
ns
ns
tRY
Recovery Time Between Controls
tcw
CS, AO, Alto ROYA or ROY B Delay
300
t oCY
Data Clock Cycle
4.5
tcy
tDn
Data Clock low Time
180
ns
tDCH
Data Clock High Time
180
tTD
TxC to TxD Delay
,
140
ns
;
ns
300
ns
.
ns
0
tDS
RxD Setup to RxC!
tDH
RxD Hold after RxC!
t'TD
TxC to INT Delay
4
6
tcy
tlRD
RxC to INT Delay
7
10
tcy
t pi
CTS, CD, SYNDET low Time
200
tpH
CTS, CD, SYNDET High Time
200
tlPD
ExternallNT Irom CTS, CD, SYNDET
ns
140
ns
ns
500
7-233
\
ns
AFN-01701C
intJ
8274',
A.C. TESTING INPUT, OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
INPUT/OUTPUT
24=>\2,0 >
TEST POINTS
0,8
045
<2'OIC
DeVICE
UNDER
TEST
'1Cl~.'50PF
08
-------------------
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1 AND 0 45V FOR
A LOGIC 0 TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC 1
AND 0 8V FOA A LOGIC 0
CL "",l50pF
Cl INCWOES JIG CAPACITANCE
\
WAVEFORMS
CLOCK CYCLE
READ CYCLE
CS, AO. A1
DBo-DB7
1---------- 1'0 ----------;~I
7-234
HIGH IMPEDANce
AFN-01701C
inter
8274
WAVEFORMS (Continued)
V
. ../ I=...~_._
WRITE CYCLE
v
d<
.••
INTA CYCLE
DMA CYCLE
ORa
/
---J
eB.AO,A1
RDORliR
NOTES:
1."iNTA signal acts as RD IIlgnal.
2.lPi Signal acts as CS signal.
7-235
AFN'()1701C
inter
8274
WAVEFORMS (Continued)
READ/WRITE CYCLE (SOFTWARE POLLED MODE)
a,AO,41
iiDORWR
t--------I"--:-,-------t
"'------)
i-------tOCy------i
TRANSMIT DATA CYCLE
Ic-----
I.o----~-.j
. . .---
OTHER T!,:!~ ":.-----"lp"-,----0----,'"----<~
1
'''D--IQ~___
7-236
AFN·01701C
82530/82530-6
SERIAL COMMUNICATIONS CONTROLLER (SCC)
• Two independent full duplex serial
channels
•
On chip crystal oscillator, Baud-Rate
Generator and Digital Phase Locked Loop
for each channel
•
Programmable for NRZ, NRZI or FM data
encoding/decoding
•
Diagnostic localloopback and automatic
echo for fault detection and isolation
•
System Clock Rates:
-4 Mhz for 82530
-6 Mhz for 82530-6
•
Max Bit Rate (4 Mhz)
..... Externally clocked: 1Mbps
•
Asynchronous Modes
- 5-8 bit character; odd, even or no
parity; 1, 1.5 or 2 stop bits
- Independent transmit and receive
clocks. 1X, 16X, 32X or 64X
programmaple sampling rate
- Error Detection: Framing, Overrun and
,
Parity
- Break detection and generation
•
Bit synchronous Modes
- SDLC/HDLC flag generation and
recognition
- Automatic zero bit insertion and
deletion
- Automatic CRC generation and
detection (CRC 16 or CCITT)
- Abort generation and detection
- I-field residue handling
- SDLC loop mode operation
- CCITT X.25 compatible
•
Byte synchronous Modes
- Internal or external character
synchronization (1 or 2 characters)
- Automatic CRC generation and
checking (CRC 16 or CCITT)
- IBM Bisync compatible
- Self clocked:
250 Kbps FM coding
125 Kbps NRZI coding
• Interfaces easily with any INTEL CPU,
DMA or I/O processor
7-237.
NOVEMBER 1983
ORDER NUMBER: 2~0834-001
82530/82530-6
DATA
IUS
D10·7
BUFFERS
CHANNEL A
TXD..,
,;~~
GENERATOR
AaDA
TRANSMITTERI
RECEIVER
1ITiC,
TIiiC,
READ
REGISTERS
elK
CONTROL
SYNC"
LOGIC
11ft,
Ci'i,
WRITE
REGISTERS
Co,
lEO
,.,
OPERATION
CONTROL
Ai5Y,vQti"
RDl'alREOa
tmiAlJiEO...
m ....Am.
CHANNELl
SYSTEM INTERFACE
SERIAL COMMUNICATION
INTERFACE
Figure 1.
82530 Internal Block Diagram
The INTEL 82530 Serial Communications Controller
(SCC) is a dual-channel, multi-protocol data
communications peripheral. It is aesigned to interface
high speed communications lines using Asynchronous.
Byte synchronous and Bit synchronous protocols
to INTEL's microprocessQrs based systems. It can
be interfaced with Intel's MCS51, iAPX86/88/186
and 188 in polled, interrupt driven or DMA driven
modes of operation.
D81
D80
083
082
08.
08.
087
08'
jjj'f
Rl)
lEO
\VA
lEI
cs
Vee
o/E
FWYA~A
The SCC is a 40 pin device manufactured using
INTEL's high-performance HMOS II technology.
SYNC.
ONO
ROYBIREQe
RTxC.
SYNCs
RXOA
ATxCe
fRiC",
... 0.
DTRAfREQ"
fITS ...
CTSA
RxDs
fRiC a
TxDe
me/REOs
RTSe
ell.
CTSB
elK
CDB
Figure 2.
7-238
AlB
iNfA
Pin configuration
230834-001
inter
82530/82530-6
The following section describes the pin functions
of the SCC. Figure 2 details the pin assignments
'nIble 1. Pin Description
Symbol
Pin No. ~pe
DBa
DB,
DB2
DB3
DB4
DBs
DBe
DB7
INT
40
1
39
2
38
3
37
4
1/0
5
0
lEO
6
0
lEI
7
I
INTA
8
I
Vee
RD?/REQ A
RD e1Rme
9
10
30
0
0
SYNC A
SYNCe
11
29
1/0
I/O
1/0
, Name and Function
Data Bus: The Data Bus lines are bi-directional three-state lines which
interface with the system's Data Bus. These lines carry data and
commands to and from the SCC.
I/O
I/O
I/O
I/O
I/O
I/O
Interrupt Request: The interrupt signal is activated when the SCC
requests an interrupt. It is an open drain output.
Interrupt Enable Out: lEO is High only if lEI is High and the CPU is not
servicing an SCC interrupt or the SCC is not requesting an interrupt
(Interrupt Acknowledge cycle only). lEO is connected to the next lower
priority device's lEI input and thus inhibits interrupts from lower priority
devices.
Interrupt Enable In: lEI is used with lEO to form an interrupt daisy chain
when there is more than one interrupt-driven device. A High lEI indicates that no other higher priority device has an interrupt under service
or is requesting an interrupt.
Interrupt Acknowledge: This signal ind icates an active Interrupt Acknowledge c~le. During this cycle, the SCC interrupt daisy chain settles.
When D becomes active, the SCC places an interrupt vector on the
data bus (if 'IEI is High)'. INTA is latched by the rising edge of ClK.
Power: +5V Power supply
Ready/Request (output, open-drain when programmed for a Ready
function, driven High or low when programmed for a Requestfunction).
These dual-purpose outputs may be programmed as Request lines fora
DMA controller or as Ready lines to synchronize thelCPU to the SCC
data rate. The reset state is Ready.
'
Synchronization: These pins can act either as inputs. outputs or part of
the crystal oscillator circuit. In the Asynchronous Receive mode (crystal
oscillator option not selected). these pins are inputs similar to ~ and
CD. In this mode, transitions on these lines affect the state of the
Synchronous/Hunt status bits in Read Register 0 (Fig ure 9) but have no
other function.
.
In External Synchronization mode with the crystal oscillator not
selected, these lines also act as inputs. In this mode, SYNC must be
driven lbw.two receive clock cycles after the last bit in the synchronous
character is received. Character assembly begins on the r~ingcdge of
.
the receive clock immediately preceding the activation of YN.
.
In the Internal Synchronization mode (Monosync and Bisync) with the
crystal oscillator not selected, these pins act as outputs and are active
only during the part of the receive clock cycle in which synchrono\Js
characters are recognized. The synchronous condition is not latched, so
these ,outputs are active each time a synchronization' pattern is
recognized (regardless of characters boundaries). In SOlC mode, these
pins act as outputs and are valid on receipt of a flag .
.
7-239
230834-001
82530/82530·6
Table 1. PIn Description (Cont.)
Symbol
PIn No.
,~pe
Name and Function
RTxC A
RTxC B
12
28
I
I
Recelve/nansmlt clocks: These pins can be prRfrCmmed in several
different modes of operation. In each channel,
x may supply the
receive clock, the transmit clock, the clock for the baud rate generator,
or the clock for the Digital Phase lbcked LOop. These pins can be
programmed for use with the respective SYNC pins as a crystal
oscillator. The receive clock may be 1, 16,32, or 64 times the data rate in
Asynchronous modes.
RxDA
RxDB
13
27
I
I
Receive Data: These lines receive serial data at standard TTL levels.
TRxC A
~B
14
26
I/O
I/O
Transmit/Receive clocks: These pins can be programmed in several
different modes of operation. TRXC may supply the receive clock'or the
transmit clock in the input mode or supply the output of the Digital
Phase locked loop, the crystal oscillator, the baud rate generator, orthe
transmit clock in the output mode.
TxDA
TxDA
15
25
0
0
Transmit Data: These output signals transmit serial data at standard TTL
levels
DTRAREQ A
DTRBREQ B
16
24
0
0
Data Terminal Ready/Request: These outputs follow the state programmed into the DTR bit. They can also be used as general purpose
outputs or as Request lines for a DMA controller.
RTSA
RTS B
17
23
0
0
Request To Send: When the Request to Send (RTS) bit in Write Register 5
is set (figure 10), the RTS signal goes low. When the RTS bit is reset in
the Asynchrqnous mode ano Auto Enable is on, the signal goes High
after the transmitter is empty. In ~hronous mode or in Asynchronous
mode with Auto Enable off, the RTS pin strictly follows the state of the
RTS bit. Both pin.s can be used as general-purpose outputs.
CTSA'
CTS B
18
22
I
I
Clear To Send: If·these pins are programmed as Auto Enables, a lowon
the inputs enables the respective transmitters. If not programmed as
Auto Enables, they may be used as general-purpose inputs. Both inputs
are Schmitt-trigger buffered to accommodate slow rise-time inputs.
The SCC detects pulses on these inputs and can interrupt the CPU on
both logic level transitions:
CD A
CD B
19
21
I
I
Carrier Detect: These pins function as receiver enables if they: are
programmed for Auto Enables; otherwise they may be used as generalpurpose input pins. Both pins are Schmitt-trigger buffered to accommodate slow rise time signals. The SCC detects pulses on these pins and
can interrupt the' CPU on both logic level transitions.
ClK
20
I
Clock: This is the system SCC clock usee to synchronize internal
signals. ClK is a TTL level signal.
GND
31
D/C
32
I
Data/Command Select: This signal defines the type of information
transferred to or from the SCC A High means data IS transferred: a low
Indicates a command
es
33
1
Chip Select:This signal selects, th.e
A/B
34
I
Channel AIChannel B Select: This signal selects the channel in which
the read or write operation occurs
WR
35
I
RD
36
I
\
Ground
sec for a read or write operation.
Write: When the see l."._selecte.Qlhls signal indicates a write operation.
The ·colncldence of RD and WR IS interpreted as a reset.
Read: This signal indicates a read operation and when the SCC is
selected, enables the.SCC's bus dnvers. During the Interrupt Acknowledge cycle, this signal gates the interrupt vector onto the bus if the SCC
IS the highest priOrity device requesting an interrupt.
7-240
230834-001
inter
82530/82530-6
GENERAL DESCRIPTION
The register set for each channel includes ten control (write) registers, two synchronous character
(write) registers, and four status (read) registers. In
addition, each baud rate generator has two (read/write) registers for holding the time constant that
determines the baud rate. Finally, associated with
the interrupt logic isa write registerforthe interrupt
vector accessible through either channel, a writeonly Master Interrupt Control register and three
read registers: one containing the vector with status
information (Channel,B only), one containing the
vector without status (A only), and one containing
the Interrupt Pending bit~,(A on!y).
The INTEL 82530 Serial Communications Controller (SCC) is a dual-channel, multi-protocol data
communications peripheral. The SCC functions as
a serial-to-parallel, parallel-to-serial converter/controller. The SCC can be software-configured to
satisfy a wide range of serial communications applications. The device contains new, sophisticated
internal functions including on-chip baud rate generators, digital phase locked loops, various data
encoding and decoding schemes, and crystal oscillators that dramatically reduce the need for external
logic.
The registers for each channel are designated as
follows:
In addition, diagnostic capabilities - automatic echo
and local loopback - allow the user to detect and
isolate a failure in the networK. They greatly improve
the reliability and maintainability of the system.
WRO-WR15 - Write Registers 0 through 15.
RRO-RR3, RR10, RR12, RR13, RR15 - Read Registers
o through 3, 10, 12,.13, 15
The SCC handles Asynchronous formats, Synchronous byte-oriented protocols such as IBM Bisync,
and Synchronous bit-oriented protocols such as
HDLC and IBM SDLC. This versatile device supports virtually any serial data transfer application
(Terminal, Personal Computer, Peripherals, Industrial Controller, Telecommunication system, etc.):
Table 21ists the functions assigned to each read or
write register. The SCC contains only one WR2
and WR9, but they can be accessed by either
channel. All ,other registers are paired (one for
each channel).
The 82530 can generate and check CRC codes in
any Synchronous mode and can be programmed to
check data integrity in various modes. The SCC also
has facilities for modem controls in both channels.
In applications where these controls are not needed,
the modem controls can be used for generalpurpose I/O.
DATA PATH
The transmit and receive data path illustrated in
Figure 3 is identical for both channels. The receiver
has thrre 8-bit buffer registers in a FIFO arrangement, in addition to the 8-bit receive shift register.
This scheme creates additional time for the CPU to
service an interrupt at the beginning of a block of
high-speed data. Incoming data is routed through
one of severai' paths (data or CRC) depending on
the selected mode (the character length in asynchronous modes also determines the data path).
The INTEL 82530 is designed to support INTEL's
MCS51, iAPX86/88 and iAPX186/188 families.
ARCHITECTURE
The 82530 internal structure includes two fullduplex channels, two baud rate generators, internalcontrol and interrupt logic, and a bus interface to a
non-multiplexed CPU bus. Associated with each
channel are a number of read and write registers for
mode control and status information, as well as
logic necessary to interface to modems or other
external devices.
The transmitter has an 8-bit transmit data buffer
reg,ister loaded from the internal data bus and a
20-bit transmit shift register that can be loaded
either from the synC-Character registers or from the
transmit data register. Depending on the operational mode, outgoing data is routed through one of
four main paths before it is transmitted from the
Transmit Data output (TxD).
The logic for both channels. provides formats, synchronization, and validation for data transferred to
and from the channel interface. The modem control
inputs are monitored by the control logic under
program control. All of the modem control signals
are general-purpose in nature and can optionally be
used for functions other than modem control.
7-241
230834-001
82530/82530-6
Table 2. Read and Write Register Functions
READ REGISTER FUNCTIONS
WRITE REGISTER FUNCTIONS
RRO
Transmit/Receive buffer status and
External status
WRO
RR1
Special Receive Condition status
CRC initialize, initialization commands for
the various modes, shift right/shift left
command
RR2
Modified interrupt vector
(Channel B only)
Unmodified interrupt
(Channel A only)
WR1
Transmit/Receive interrupt and data
transfer mode definition
WR2
Interrupt vector (accessed through either
channel)
RR3
Interrupt Pending bits
(Channel A only)
RR8
Receive buffer
WR3
Receive parameters and control
WR4
Transmit/Receive miscellaneous parameters and modes
RR10
Miscellaneous status
WR5
Transmit parameters and controls
RR12
Lower byte of baud rate generator time
constant
WR6
Sync characters or SOLC address field
WR7
Sync character or SOLC flag
RR13
Upper byte of baud rate generator time'
constant
WR8
Transmit buffer
RR15
External/Status interrupt information
WR9
Master interrupt control and reset
(accessed through either channel)
WR10
Miscellaneous transmitter/receiver control
bits
WR11
Clock mode control
WR12
Lower Byte of baud rate generator time
constant
WR13
Upper byte of baud rate generator time
constant
WR14
Miscellaneous control bits
WR15
External/Status interrupt control
7-242
230834-001
l
CPU "a
8A GENERATOR
INPUT
GIl
l
1"
N
.,..
Co>
II)
(1'1
Co)
!i
~
GIl
W
II)
(1'1
Ii
Co)
iii'
_J _____
l
u
__
!f
DPLL
---..1._ _ _ _.....
8R GENERATOR OUTPUT
DPLLOUTPUT
TfiiC
ii!iiC
~
RECEIVE CLOCK
CLOCK
MUX
TRANSMIT CLOCK
DPllCLOCK
8A GENERATOR CLOCK
i'iNC
(OSCILLATOR I
!
l
TRANSMIT
CLOCK
•
0
82530/82530;':6
FUNCTIONAL DESCRIPTION
The functional capabilities of the SCC can be described from two different points of view: as a data
communications device, it transmits and receives
data in a wide variety of data communications protocols; as a microprocessor peripheral, it interacts
with the CPU and provides vectored interrupts and
handshaking signals. .
end of a received break. Reception.is protected from
spikes by a transient spike-rejection mechanism
that checks the signal one-half a bit ti me after a Low
level is detected on the receive data input (RxD A or
RxDB).lfthe Low does not persist (as in the case of a
transient), the character assembly process does not
start.
DATA COMMUNICATIONS
CAPABILITIES
Framing errors and overrun errors are detected and
buffered together with the partial character on
which they occur. Vectored interrupts allow fast servicing or error conditions using dedicated routines.
Furthermore, a built-in checking process avoids the
interpretation of framing error as a new start bit: a
framing error results in the addition of one-half a bit
time to the point at which the search for the next
start bit begins.
The SCC provides two independent full-duplex
channels programmable for use in any'common
asynchronous or synchronous data-comm unications
protocol. Figure 4 and the following description
briefly detail these protocols.
Asynchronous Modes
TransmiSSIon and reception can be accomplished
independently on each channel with five to eight
bits per character, plus optional even or odd parity.
The transmitter can supply one, one-and-a-half or
two stop bits per character and can provide a break
output at any time. The receiver break-detection
logic interrupts the CPU both at the start and at the
The SCC does not require symmetric transmit and
receive clock signals - a feature allowing use of the
wide var.iety of clock sources. The transmitter and
receiver can handle data at a rate of 1, 1116; 1/32, or
1/64 of the clock rate supplied to the receive and
transmit clock inputs. In asynchronous modes, the
SYNC pin may be programmed as an input used for
functions such as monitoring a ring indicator.
MARKING LINE
MARKING LINE
SYNC
DATA
:;
::
DATA
CRC1
CRC2
DATA
CRC1
CRC2
DATA
CRC1
CRC2
CRC1
CRC2
MONOSYNC
,
DATA
SYNC
SIGNAL
I
DATA
:;.
BISYNC
EXTERNAL SYNC
FLAG
ADDRESS
I
INFO;~ATION
FLAG
SDLC/HDLC/X.25
Figu~
4.
see Protocols
7-244
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Synchronous Modes
If a transmit underrun occurs in the middle of a
message, IiIn external status interrupt warns the
CPU of this status change so that an abort may be
issued. The SCC may also be programmed to send
an abort itself in case of an underrun, relieving the
CPU of this task. One to eight bits per character can
be sent allowing reception of a message with no
prior information about the character structure in
the information field of a frame.
The SCC supports both byte-oriented and bitoriented synchronous communication. Synchronousbyte-oriented protocols can be handled in several
modes allowing character synchronization with a
6-bit or 8-bit synchronous character (Monosync),
any 12-bit synchronous pattern (Bisync), or with an
external synchronous signal. Leading synchronous
characters can be removed without interrupting the
cpu.
Five- or 7-bit synchronous characters are detected
with 8- or 16-bit patterns in the SCC by overlapping
the larger pattern acfoss multiple incoming synchronous characters as shown in Figure 5.
CRC checking for Synchronous byte-oriented
mode is delayed by one character time so that the
CPU may disable CRC checking on specific characters. this permits the implementation of protocols
such as IBM Bisync.
Both CRC-16 (X16 + X15 + X2 + 1) and CCITT (X16 + X 12
+ X5 + 1) error checking polynomials are supported.
Either polynomial may be selected in all synchronous modes. Users may preset the CRC generator
and checker to all 15 or all Os. The SCC also provides a feature that automatically transmits CRC
data when no other data Is available for transmission.
This allows ·for high-speed transmissions under
OMA control, with no need for CPU intervention at
the end of a message. When there is no data or CRC
to send in synchronous modes, the transmitter
inserts 6-, 8-, or 16-bit synchronous characters,
regardless of the programmed character ,length.
.
The SCC supports synchronous bit-oriented protocols, such as SOLC and HOLC, by performing
automatic flag sending, zero Insertion, and CRC
generation. A special command" can be used to
abort a frame in transmission. At the end of a message, the SCC automatically transmits the CRC
and trailing flag when the transmitter underruns.
The transmitter may also be programmed to send an
idle line consisting of continuous flag characters or
a steady marking condition.
The receiver automatically acquires synchronization on the leading flag of a frame in SOLC or!:!Q.bQ
and provides a synchroniZation signal on the SYNC
pin (an interrupt can also be programmed). The
receiver can be programmed to search for frames
addressed by a single byte (or four bits within a
byte) of a user-selected address or to a global
broadcast address. In this mode, frames not matching either the user-selected or broadcast address
are ignored. The number of address bytes can be
extended under software control. For receiving
data, an interrupt on the first received character, or
an interrupt on every character, or on special condition only (end-of-frame) can be selected. The
receiver automatically deletes all Os inserted by the
transmitter during character assembly. CRC is also
calculated and is automatically checked to validate
frame transmission. At the end of transmission, the
status of a received frame is available in the status
registers. In SOLC mode, the SCC must be programmed to use the SOLC CRC polynomial, but the
generator and checker may be be preset to all 1s or
al,1 Os. The CRC is inverted before transmission and
the receiver checks against the bit pattern
0001110100001111.
NRZ, NRZ I or FM coding may be used in any 1X
mode. The parity options available in asynchronous
modes are available in synchronous modes.
The SCC can be conveniently used under OMA
control to provide high-speed reception or transmission. In reception,for example, the SCC can
interrupt the CPU when the first character of a message is received. The CPU then enables the OMA to
transfer the message to memory. The SCC then
issues an end-of-frame interrupt and the CPU can '
SBITS
:SYNC
SYN~
SYNC
DATA
OATA
DATA
DI'TA
----------- ---------16
Figure 5. Detecting 5- or 7- Bit Synchronous Characters
7-245
230834-001
82530/82530-6
check the status of the received message. Th us, the
CPU is freed for other service while the message is
being received. The CPU may also enable the OMA
first and have the SCC interrupt only on end-offrame. This procedure allows all data to be transferred via OMA.
SOLe LOOf) MODE
The SCC supports SOLC Loop mode in addition to
normal SOLC. In an SOLC Loop, there is a primary
controller station that manages the message traffic
flow and any number of secondary. stations. In
SOLC Loop mode, the SCC performs the functions
of a secondary station while an SCC operating in
regularSOLCmode can act asa controller (Figure 6).
further down the loop with messages to transmit
can then append their mellsages to the message of
the first secondary station by the same process. Any
secondary stations without messages to send merely
echo the incoming messages and are prohibited
from placing messages on the loop (except upon
recognizing an EOP).
SOLC Loop mOde is a programmable option in the
SCC. NRZ, NRZI, and FM coding may all be used in
SOLC Loop mode.
BAUD RATE GENERATOR
sec
Each channel in the
contains a programmable
Baud rate generator. Each generator consists of two
S-bit time constant registers that form a 16-bit time
constant, a 16-bit down counter, and a flip-flop on
the output prod ucing a square wave. On startup, the
flip-flop on the output is set in a High state, the value
in the time constant register is loaded into the counter, and the counter starts counting down. The output of the baud rate generator toggles upon reaching zero, the value in the time constant register is
loaded into the counter, and the process is repeated.
The time constant may be changed at any time, but
the new value does not take effect until the next load
of the counter.
The output of the baud rate generator may be used
as either the transmit clock, the receive clock, or
both. It can also drive the digital phase-locked loop
(see next section).
If the receive clock or transmit clock is not programmed to come from the i'RXC pin, the output of
the, baud rate generator may be echoed out via the
TRxC pin.
Figure 6. An SOLe Loop
A secondary station in an SOLC Loop is always
listening to the messages being sent around the
loop, and in fact must pass these messages to the
rest of the loop by retransmitting them with a onebit-time delay. The secondary station can place its
own message on the loop only at specific times. The
controller signals that secondary stations may
transmit messages by sending a special character,
called an EOP (End of Poll), around the loop. The
EOP character is the bit pattern 11111110. Because
of zero insertion during messages, this bit pattern is
unique and easily recognized.
The following formula relates the time constant to
the baud rate. (The baud rate is in bits/second and
the BR clock period is in seconds.)
baud rate -
1
. .
.
2 (time constant + 2) x (BR clock penod)
When a secondary station has a message to transmit and recognizes an EOP on the line, it changes
the last binary one of the EOP to a zero before
transmission. This has the effect of turning the EOP
into a flag sequence. The secondary station now
places its message on the loop and terminates the
message with., an EOP. Any secondary stations
7-246
230834-001
82530/82530-6
encoding. as 1 is represented by no change in level
and a 0 is represented by a change in level. In FM1
(more properly, bi-phase mark) a transition occurs
at the beginning of every bit cell. A 1 is represented
by an additional transition at the center of the bit cell
and a 0 is repr-esented by 110 additional transition at
the center of the bit cell. In FMo (bi-phase space), a
transition occurs at the beginning of every bit cell. A
o is represented by an additional transition at the
center of the bit cell, and a 1 is represented by no
additional transition at the center of the bit cell. In
addition to these four methods, the SCC can be
used to decode Manchester (bi-phase level) data by
using the OPLL in the FM mode and programming
the receiver for NRZ data. Manchester encoding
always produces a transition at the center of the bit
cell. If the transition is 0/1 the bit is a O. If the transition is 1/0 the bit is a 1.
Time Constant Values
for Standard Baud Rates at BR Clock,= 3.9936MHz
Rate
Time Constant
(Baud)
(decimal notation)
Error
19200
9600
7200
4800
3600
2400
2000
1800
1200
600
300
150
134.5
110
75
50
102
206
275
414
553
830
996
1107
1662
3326
,6654
13310
14844
18151
26622
39934
0.12%
-
0.06%
0.04%
0.03%
-
-
-
0.0007%
0.0015%
-
AUTO ECHO AND LOCAL LOOPBACK
DIGITAL PHASE LOCKED LOOP
The SCC contains a digital phase locked-loop
(OPLL) to recover clock information from a datastream with NRZI or FM encoding. The OPLL is
driven by a clock that is nominally 32 (NRZI) or 16
(FM) times the data rate. The OPLL uses this clock,
along with the datastream, to construct a clock for
the data. This clock may then be used as the SCC
receive clock, the transmit clock, or both.
For NRZI coding, the OPLL counts the 32X clock to
create nominal bit ti'mes. As the 32X clock is
counted, the OPLL is searching the incoming datastream for edges (either 1/0 or 0/1). Whenever an
edge is detected, the OPLL makes a count adjustment (during the next counting cycle), producing a
terminal count closer to the center of the bit cell.
For FM encoding, the OPLLstili Counts from 1 to 31,
but with ,a cycle corresponding to two bit times.
When the OPLL is locked, the clock edges in the
datastream should occur between counts 15 and 16
and between counts 31 and O. The OPLL looks for
edges only during a time centered on the 15/16
counting transition.
'
The 32X clock for the OPLL can be programmed to
come from either the RTxC input orthe output of the
baud rate generator. The OPLL output may bTRrc
grammed to be echoed out of the SCC via the
x
pin (if this pin is not being used as an input).
DATA ENCODING
The SCC may be programmed to encode and
decode the serial data in four different ways (Figure
7). In NRZ encoding, a 1 is represented by a High
level and a 0 is represented by a Low level. In NRZI
The SCC is capable of automatically echoi ng everything it receives. This feature is useful mainly in
asynchronous modes, but works in synchronous
and SOLC modes as well. In Auto Echo mode TxO
is RxO. Auto Echo mode can be used with NRZI or
FM encoding with no additional delay, because the
datastream is not decoded before retransmission. In
Auto Echo mode, the eTS input is ignored as a
transmitter enable (although transitions on this
input can still cause interrupts if programmed to do
so). In this mode, the transmitter is actually bypassed
and the programmer is res~Esbbie for disabling
transmitter interrupts and
A 7REaUEST on
transmit.
The SCC is also capable of local loopback. In this
mode, TxO is RxO just as in Auto Echo mode. However, in Local Loopback mode, the internal transmit
data is tied to the internal receive data and RxO is
( ignored (except to be echoed out via TxO).' eTS
and CD inputs ,are also ignored as transmit and
receive enables. However, transitions on these inputs
can still cause interrupts. Local Loopback works in
asynchronous, synchronous and SOLC modes with
NRZ, NRZI or FM coding of the data stream.
SERIAL BIT RATE
To run the 82530 (4Mhz) at 1Mbps the receive a,nd
transmit clocks must be externally generated and
synchronized to thTRsysjem clock. If the serial
xC and the system clock
clocks (RTxC and
(CLK) are asynchronous, the maximum bit rate is
880 Kbps. For self-clocked operation, i.e using the
on chip OPLL, the maximum bit rate is 125 Kbps if
NRZI coding is used and 250 Kbps if FM coding is
•
used.
7-247
230834-001
82530/82530-6
DATAl
'1
:....---+----i
NRZ
NRZI
o
o
I
I
BIT CELL LEVEL:
t---~ HIGH = 1
LOW=O
I
i----.;,-----;
I
!-- - - - i
NO CHANGE = 1
CHANGE = 0
BIT CENTER TRANSITION:
FM1
(BIPHASE MARK)
TRANSITION = 1
!----~I NO TRANSITION = 0
NO TRANSITION = 1
FMo
(BIPHASE SPACE) ~_ _~
TRANSITION = 0
II
HIGH _LOW = 1
LOW _HIGH = 0
Figure 7. Data Encoding Methods
Mode
Serial clocks
generated
externally
System
clock
System' clock!
Serial clock
Serial bit rate
Conditions
Serial clocks synchronized with
system clock. Refer to parameter #3
and #10 in general timings.
4Mhz
4
1 Mbps
6 Mhz
4
1.5 Mbps
, 4 Mhz
4.5
880 Kbps
6 Mhz
4.5
1.3 Mbps
NAZI
4 Mhz
6 Mhz
32
32
125 Kbps
187 Kbps
FM
4 Mhz
6Mhz
16
16
250 Kbps
375 kbps
Serial cloCks synchronized with
. system clock. Refer to parameter #3 and
#10 in general timings.
Serial clocks and system
clock asynchronous.
Serial clocks and system
clock asynchronous
Self-clocked
operation
7-248
230834"()Ol
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82530/82530·6
1/0 INTERFACE CAPABILITIES
The S,CC offers the choice of Polling, Interrupt (vectored or nonvectored) and Block Transfer moces to
transfer data, status, and control information to and
from the CPU. The Block Transfer mode can be
implemented under CPU or DMA control.
POLLING
All interrupts are disabled. Three status registe,rs in
the SCC are automatically updated whenever any
function is performed. Forexample, end-of-frame in
SDL~ mode sets a bit in one of these status registers.
The Idea' behind p,olling is for the CPU to periodically read a statu~ register until the register contents
indicate the need for data to be transferred. Only
one register needs to be read; depending on its
contents, the CPU either writes data reads data or
continues. Two bits in the register indicate the n~ed
for data transfer. An alternative is a poll of the Interrupt Pending register to determine the source of an
interrupt. The status for both channels resides in
one register.
INTERRUPTS
"Yhen a SCC responds to an Interrupt Acknowledge
signal (TlilTAj from the CPU, an interrupt vector may
be placed on the data bus. This vector is written in
WR2 and may be read in RR2A or RR2B (Figures 9
and 10).
'
To speed interrupt response time, the SCC can modify three bits in this vector to indicate status. If the
vector is read in Channel A, status is never included'
if it i,s read in Channel B, status is always included:
Each of the six sources of interrupts in the SCC
(Transmit, Receive and ExternaliStatus interrupts in
both channels) has three bits associated with the
interrupt source: Interrupt Pending (IP), Interrupt
Under Service (IUS), and Interrupt Enable (IE).
Operation ofthe IE bit is straightforward. If the IE bit'
is set for a given interrupt source, then that source
can request interrupts. The exception is when the
MIE (Master Interrupt Enable) bit in WR9 is reset
and no interrupts may be requested. The IE bits are
write-only.
The other two bits are related to'the interrupt priority chain (F!gure 8). As a peripheral, the SCC may
request an mterrupt only when no higher-pr.Jority
device is requesting one, e.g., when lEI is High. If the
deviceJ!!. question requests an ihterrup,t, it pulls
down INT. The CPU then responds with iNTA, and
the interrupting device places the vector on the data
bus.
In the SCC, the IP bit signals a need for interrupt
servicing. When an IP bit is 1 and the lEI input is
~igh, the INT output is pulled Low, requesting an
mterrupt. In the SCC, if the IE bit is not set by
enabling interrupts, then the IP for that source can
never be set. The IP bits are readable in RR3A.
The IUS bi,ts signal that an int,errupt request is being
'serviced. If, an IUS is set, all interrupt sources of
lower priority in the ,sCC and external to the SCC
are prevented from requesting interrupts. The internal interrupt sources are inhibited by the state of the
internal daisy chain, while lower priority devices are
inhibited by the lEO output of the
being pulled
sec
sec
scc
HIGHEST PRIORITY
SCC
LOWEST PRIORITY
+5V
DBO-DB7
INT
~ '---~--~-------4--~--------------~------------------~
+5V
FIgure 8. Daisy Chaining SCC's
7-249
23083~'
82530/825~O-6
Low and propagated to subsequent peripherals. An
~US bit is set during an Interrupt Acknowledge cycle
~f there are no higher-priority devices requesting
Interrupts.
.
. '
There are three types of interrupts: Transmit, Receive
External/Status interrupts. Each interrupt type
IS enabled under program control with Channel A
having higher priority than Channel B, and with
Receiver, Transmit and External/Status interrupts,
prioritized in that order within each channel. When
the Transmit interrupt is enabled, the CPU is interrup~ed wh~n the transmit buffer becomes empty.
(This Implies that the transmitter must have had a
data character written into it so that it can become
empty.) When enabled, the receiver can interrupt
the CPU in one of three ways:
.
~nd
•
Interrupt on First Receive Character or Special
Receive condition.
.
•
Interrupt on/all Receive Characters or Special
Receive condition.
•
Interrupt on Special Receive condition only.
Interrupt on First Character or Special Condition
and Interrupt on Special Condition Only are typically used with the Block Transfer mode. A Special
Receive Condition is one of the following: receiver
overrun, framing error in Asynchronous mode, Endof-Frame In SDLC mode and, optionally, a parity
error. The Special Receive Condition interrupt is
different from an ordinary receive character available interrupt only in the status placed in the vector
during the Interrupt-Acknowledge cycle. In Interrupt on First Receive Character, an interrupt can
occur from Special Receive conditions any time
after the first receive character interrupt.
The main function of the External/Status interrupt is
§o mCni~or the signal transitions of the CTs, Co, and
YN pinS; however, an External/Status interrupt is
also caused by a Transmit Underrun condition, or a
zero count in the baud rate generator, or by the
detection of a Break (asynchronous mode), Abort
(SDLC mode) or EOP (SDLC Loop mode) sequence
in the data stream. The interrupt caused by the Abort
or EOP has a special feature allowing the sec to
interrupt when the Abort or EOP sequence is
detected or terminated. This feature facilitates the
proper termination of the current message, correct
initialization of the next message, and the accurate
timing of the Abort condition in external logic in
SDLC mode. In SDLe Loop mode this feature
allows secondary stations to recognize the wishes
of the primary station to regain control of the loop
during a poll sequence.
CPU/DMABLOCKTRANSFER
TheSCC provides a Block Transfer mode to accommodate CPU block transfer functions and DMA
controllers. The Bl.ock Transfer mode uses the
READY/REQUEST output in conjunction withfhe
READY/REQUEST bits in WR1. The READY/REO"O'EST output can be defined under software control as a REAI:5? line in the CPU Block Transfer
mode (WR1; D6=0) orasa request line in the DMA
Block Transfer mode (WR1; D6=1). To a DMA con~
troller, the SCC REQUEST output indicates .that
the SCC is ready to transfer data to or from
memory. To the CPU, the READY line indicates that
the SC~ is not ready to transfer data, thereby
requesting that the CPU extend the I/O cycle. The
DTR/REQUEST line allows full-duplex operation
under DMA control.
PROGRAMMING
Each channel has fifteen Write registers that are
individually programmed from the system bus to
configure the functional personality of each channel. Each channel also has eight Read registers from
which ime system can r.ead Status, Baud rate, or
Interrupt information.
.
Only the four data registers (Read, Write for channels
A and B) are directly selected by a High on the D/G
inl2ut and the appropriate levels on the RD, WR and
Alt3 pins. All other registers are addressed indirectly
by the content of Write Register 0 in conjunction
with a Low ~the D/G inp.!:.!,t and the appropriate
levels on the RD, WR and AlB pins. If bit 4 in WWO is
1 and bits 5 and 6 are 0 then bits 0, 1,2 address the
higher registers 8 through 15. If bits 4, 5, 6 contain a
different code, bits 0, 1,2 address the lower registers
o through 7 as shown on Table 3.
Writing to or reading from any register except RRO,
WRO and the Data Registers thus involves two
operations:
First write the appropriate code into WRO,then follow this bya write or read operation on the register
thus specified. BitsOthrough 4 in WWOareautomatically cleared after this operation, so that WWO then
points to WRO or RRO again. '
Channel AlChannel B selection is made by the AlB
input (High = A, Low = B)
The system program first issues a series of commands to initialize the basic mode of operation. This
is followed by other commands to qualify condi-
,
230834-001
inter
82530/82530-6
TABLE 3. REGISTER ADDRESSING
I
DIC "Point High"
Code In WRO
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Either Way
Not True
Not True
Not True
Not True
Not True
Not True
Not True
Not True
True
True
True
True
True
True
True
True
D2
D1
Do
Write
Reg'lster
Read
Register
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Data
0
1
2
3
4
5
6
Data
0
1
2
3
(0)
(1 )
(2)
(3)
Data
InWRO
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
tions within the selected mode. For example, the
asynchronous mode, character length, clock rate,
number of stop bits, even or odd parity might be set
first. 'Then the interrupt mode would be set, and
finally, re~eiver or transmitter enable.
7
Data
9
10
11
12
13
14
15
-
10
(15)
12
13
(10)
15
The status bits of RRO.and RR1 are carefully grouped
to simplify status monitoring: e.g. when the interrupt vector indicates a Special Receive Condition
interrupt, all the appropriate error bits can be read
from a Single register (RR1).
READ REGISTERS
WRITE REGISTERS
The SCC contains eight read registers (actually
nine, counting the receive 'buffer (RR8) in each
channel). Four of these may be read to obtain status
information (RRO, RR1, RR10, and RR15). Two registers (RR12 and RR13) may be read to earn the baud
rate generator time constant. RR2 contains either
the unmodified interrupt vector (Channel A) or the
vector modified by status information (Channel B).
RR3 contains the Interrupt Pending (IP) bits (Channel A). Figure 9 shows the formats for each read
register.
The SCC contains 15 write registers (16 counting
WR8, the transmit buffer) in each,. channel. These
write registers are programmed separately to configure the functional "personality" of the channels.
In addition, there are two registers (WR2 and WR9)
shared by the two channels that may be accessed
through either of them. WR2 contains the interrupt
vector for both channels, while WR9 contains the
interrupt control bits. Figure 10 shows the format of
each write register.
7-251
230834-001 I
82530182530-6,
I,"
Rx CHARACTER AVAILABLE
ALL SENT
ZERO COUNT
' -_ _ _ _ TIl BUFFER EMPTY
L -_ _....._ _ CO
' -_ _ _ _ _ _ _
RESIDUE CODE 2
1-_ _ _ _ RESIDUE CODE 1
L.._ _ _ _ _ _ RESIDUE COOEO
~NCJHUNT
'-_
-_
-_
-_
-_
-_
- PilAITV
ERROR
L..._ _
_
_
Ax OVERRUN
ERROR
~---------bs
1-_ _ _ _ _ _...._ _ _ _ _ CACIFRAMING ERROR
....- - - - - - - - - - - - TIl UNDERRUNJEOM
L.._ _ _ _ _ _ _ _ _ _ _ _ _ END OF FRAME (SDLC)
....- - - - - - - - - - - - - BREAK/ABORT
. .----~I_~n_
'-------- ~ \
CHANNEL B EXT/STAT II>"
CHANNEL B TIIIP"
....----CHANNELB R,IP'
'-------'CHANNEL A EXT/STAT II'"
L...--------CHANNEL A TIIP'
L . . - - - - - - - - - - c : H A N N E L A "xlp·
'-ALWAYs 0 IN 8 CHANNEL
"MODIFIED IN B CHANNEL
~~ )
ON LOOP
TC.~
L-__
..-.:_-_-_-_-_-_-_-_-_-_
....- - - - - - - - LOOP SENDING
~'j
LOWER BYTE OF
TIME CONSTANT
....- - - - - - - - - - - - TWO CLOCKS M_NG'
TC,
....- - - - - - - - - - - - - - ONE CLOCK MISSIHG
:~: I
....- - - - T C lO
....- - - - - - TC11
l
ZERO COUNT IE
L . . . - -.....- - - C D I E
UPPER BYTE OF
TC12 \ ) TIME CONSTANT
L-_ _ _ _ _ _ _ _ _ TC13
' - - - - - - - - - SYNC/HUNT IE
-_
-_
-_
-_
-_
-_
-_
-_
-_
- TIl
CTSIE
L..._'_
UNDERRUNJEOM IE
1-_ _ _ _ _ _ _ _ _ _ _ _ _ BREAK/ABORT IE
1-_....
_-_
-_
-_-_
-_
- ._
..
_
._
, ._
-_-_
- TC14
TC15
Figure 9. Read Register Bit FuncUons
7-252
230834-001
inter
82530/82530-6
WRITE REGISTER 0
I
0,
081
05
D.
031
001
02
0,
0
0
0
0
,
0
1
0
0
1
1
0
1
20'
3",
0
40'
AEGISnA
0
1
0
1
5o,
1
1
0
60,
1
1
,
0
0
0
1
1
POINT HIGH AEGIS
0
FRElIT EX'118TATUS
NULLCDDE
1
SEND ABORT
0
ENABLE INT ON NEXT Ax CHARACTER
,
0
1
AEBET Til INT PENDI NG
1
EARORAESET
1
1
0
1
1
L-._ _ _ _ _ _ _ ENTER HUNT MODE
L-._ _ _ _ _ _ _ _ _ AUTO ENAILES
70'
0
1
0
SYNC CHARACTER LOAD INHIBIT
L-._ _ _ _ ADDRESS SEARCH MODE (SOLe)
L-._ _ _ _ _ Ax CRC ENABLE
1o,
0
0
0
1
RJt ENABLE
00<
o
Rx S 8'TSICHARACTEA
1
Ax7 BITS/CHARACTER
o
Ax' BITs/CHARACTER
1
Ax 8 BITSfCHARACTI!A
PARITY ENABLE
PAAITY EVEN/ODD
RESET HIGHEST IUS
SYNC MODES ENABLE
o rO
1 STOP BIT/CHARACTER
NULL CODE
Or,- RESET Ax eRe CHECKER
-;-'0 RESET Tx CRe GENERATOR
-;-r,- REseT
Tx UNOEARUN/EOM LATCH
11ft STOP BITS/CHARACTER
2 STOP BIT$'CHARACTEA
-"'--
WRITE REGISTER 1
EXT. INT ENABLE
Tx INT ENABLE
'-----PARITY IS SPECIAL CONDITION
o
Ax INT DISABLE
1
AxlNT ON FIRST CHARACTER OR SPECIAL CONDITION
OINT ON ALL Rx CHARACTERS OR SPECIAL CONDITION
1
Ax INT ON SPECIAL CONDITION ONLY
'------"EADYlDMAREQUESTONRECEIYElTRANSMIT
L-.------_tlEADyIDMA REQUEST FUNCTION
L-_ _ _ _ _-'-_ _ READy/DMA REQUEST ENABLE
TxCRCENABI-E
RTS
' - -_ _ _ II5LC/CRC-1.
L-_ _. - _
' - - - - - - - T. ENABLE
~y,!I
L-_ _ _ _ _ _ _ _ SEND BREAK
Tx 5 BITS (OR LESS)/CHARACTER
L-._ _ _ _ _ _ .,
~\
L.,-------------- .,
Tx 7 BITS/CHARACTER
INTERRUPT VECTOR
Tx 6 BITS/CHARACTER
Tx 8 BITS/CHARACTER
' -_ _ _ _ _ _ _ _ _ _ _ _ _ DTR
~------------~
SYNC7
SYNC1
SYNC7
SYNC3
ADR,
AOA,
SYNC.
SYNc"
SYNC.
SYNC,
ADR,
ADA,
S"(NCs
SYNC,
SYNCs
SYNC,
ADRs
ADAs
\SYNC4
SYNC.
SYNC.
SYNc"
ADR4
ADA<
SYNC3
SYNC3
SYNC3
1
AOR3
1
SYNC,
SYNc..
SYNC2
1
ADR,
1
SYNC1
SYNC1
SYNC1
1
ADR1
1
SYNCo
SYNCo
SYNc"
1
ADRo
1
MONOSYNC 8 BITS
MONOSYNC 8 BITS
BISYNC 18 BITS
BISYNC 12 BITS
SOLC
SDLC (ADDIIESS 0)
Figure 10. Write ~eglster Bit Functions
7-253
230834-001
inter
82530/82530-6
$VNCr
SYNCs
SYNCs
SY~Cl'
SYNCs
SYNC4
SYNC)
SYNC2
.sVNC,2
SYNC,
SVNC13
,
SYNC,
,
SYNC3
SYNC,
SYNC"
SYNC2
SYNC,
,
SYNCo
SYNC,o
SYNC,
SYNCs
SYNC,
SYNC..
SYNCo
,
,
SYNC,
SYNC1
,
,
•
a
MONOSYNC BITS
MONOSYNC 8 BITS
S(SVNC 1& BITS
BISYNC 12 BITS
SOle
V,S
TC,
TC,
NV
'----OLC
' - - - - TC,
'------M'E
' - - - - - - Tel
'--------STATUSHIGH/~
I'
LOWER BYTE OF
TC, \ TIME CONSTANT
' - - - - - - - - - TC,
' - - - - - - - - - - - TC,
'-------------TC,
CHANNEL RESET 8
FORCE HARDWARE RESET
:~: \
' - - - - TC,O
lOOP MODE
' - - - - - - Te"
' -_ _ _ ABORTJFL;AO' ON uNDERRUN
L-_ _ _ _ _ _ _ _
L-_ _ _ _ _ _ _ _ _ _
~----- MARK/FLAG,IDLE
' - - - - - - - - GO ACTIVE ON ROLL
~------------
NRZ
TC;2
TCu \
UPPER BYTE OF
T. tME
CONSTANT
TCH
TCn
NRll
FMl (TRANSMISSION
I)
FMO (TRANSMISSION
0)
' - - - - - - - -_ _ _ _ _ ORC PRESET 1115
BR GENERATOR ENABLE
BR GENERATOR SOURCE
rn REQUEST FUNCTION
' -_ _ _ _ AUTO ECHO
' - - - - - - - - - LOCAL LOOP8ACK
o fiiiC OUT = XlAL OUTPUT
1
'i'iiiC OUT: TRANSMIT CLOCK
o 'fliic OUT: 8A GENERATOR OUTPUT
1 lJiie OUT; DPLL OUTPUT
~0I1
TRANSMIT CLOCK - ~ PIN
o
TR~NS"'IT CLOCK: 8A GtNEAATOR OUTPUT,
TRANSMIT CLOCK
0
ENTER SEARCH MODE
RESET MtSSING CLOCK
1
1
t
0
1
0
NULL COMMAND
DISABLE DPLL
SET SOURCE: SR GENERATOR
,
SET SOURCE:
SET FM MODE
JW'i'l!
= OPlL OUTPUT
~
x
~
~
u
x
ZERO COUNT IE
~
~
-
TRANSMIT CLOCK - ~ PIN
L
0
0
SET NRZI MODE
1
___________
o
o
o
o
'---_a
' -_ _ _ _ _ COIE
' -_ _ _ _ _ _ _ _ SYNC/HUNT IE
L-....._ _ _ _ _ _ _ _ CT$"
' -_ _ _ _ _ _ _ _ _ _ _ _ _ TI UNDERRUNlEOM IE
' - - - - - - - - - - - - - - BREAK/ABOATIE
Figure 10. Write Register Bit FUnctions (Cont.)
7-254
230834-001
inter
82530/82530-6
82530 TIMING
Write Cycle Timing
The SC~enerates internal control signals from
i}ffi and 'RU that are related to ClK. Since ClK has
no phase relationship with WR and~, the circuitry
generating these internal control signals must provide time for metastable conditions to disappear.
This gives rise to a recovery time related to ClK. The
recovery time applies only between bus transactions involving the SCC. The recovery time required
for..E!...oper QE..eraton is specified from the rising edge
of WR or 'RU in the first transaction involving the
SCC to the falling edge of WR or'Rl5 in the second
transaction involving the SCC. This time must be at
least 6 ClK cycles plus 200ns.
Figure 12 illustrates Write cycle timing. Addresses
on AlB' and Om-and the status on iN'fA must remain
stable throughout th~cle. If~ falls after WR falls
or if it rises before WR rises, the effective WJ!!i is
shortened.
Read Cycle Timing
I
Figure 11 illus.!!'ates Read cycle timing. Addresses
on AlB and O/C and the status on I NTA must remain
stable throughoutthe cycle. If C'S falls after rID falls
or if Jt rises before R!) rises, the effective Rn is
shortened.
AlB. DIG
X
Interrupt Acknowledge Cycle Timing
Figure 13 illustrates Interr~Acknowledge cycle
timing. Between the time INTA goes low and the
falling edge of1!ID, the internal and externallEI/IEO
daisy chains settle. If there is an interrupt pending in
the SCC and I EI is High when 1m falls, the Acknowledge cycle is intended for the SCC. In this case, the
SCC may be programmed to respond to AD low by
placing its interrupt vector on 0 0 -0 7 and it then sets
the appropriate Interrupt-Under-Service internally.
X
ADDRESS VALID
\
INTAJ
C;
AD
DBO-DB7
\
/
\
/
X
(
DATA VALID
)
Figure 11. Read Cycle Timing
7-25$
230834-001
82530/82530-6
Alii. Die
'
X
X
ADDRESS VALID
iNfA.-J
c.
\
\
/
DBO-DB7
/
\
\iii
(
>"
DATA VALID
Figure 12. Write Cycle Timing
MA\
RD
DBO-DB7
/
IS
II
II
/
\
(
X
VECTOR
>
Figure 13. Interrupt Acknowledge Cycle Timing
7-256
230834-001
inter
82530/82530-6
ABSOLUTE MAXIMUM RATINGS· .
Case Temperature
Under Bias ........................ O°C to + 70°C
Storage Temperature
(Ceramic Package) ............. -65°C to + 150°C
(Plastic Package) .............. - 40°C to + 125°C
Voltage On Any Pin With
Respect to Ground ............... - O.5V to +7 .OV
D.C. CHARACTERISTics
Symbol.
"NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may·cause permanent damage t9 the
device. This is a stress. rating only and functional operation of the device at these or any other conditigns above
those indicated in the operatiqnal sections of this specification is ncit implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
(:T'c=O° C to 70° C; Vcc=+5V±5%)
Parameter
Min.
V IL
Input Low Volta9,e
-03
V IH
Input High Voltage
+2.0
VOL
Output Low Voltage
VO H
Output High Voltage
IlL
Input Leakage Current
IOL
Output Leakage Current
lee
Vee Supply Current
250
mA
CAPACITANCE
Symbol
CIN
Units
Max.
+0.8
V
Vee +0.3
V
Test Conditions
V
IOL = 20mA
V
.'OH = -250p.A
±10
p.A
OA to 2AV
:t 1O
p.A
04 to 2 4V
+0.40
+2.4
(Tc=25°; Vcc=GNO=OV)
Parameter
Min.
Max.
10
Input Capacitance
,
Units
Test Conditions
pF
fc = 1 MHz,
Unmeasured
pms returned
COUT
Output Capacitance
15
pF
CliO
Input/Output Capacitance·
20
pF
toGND
7-257
230834-001
inter
82530/82530-6 .•
/ ,!
A.C CHARACTERISTICS (Tc=O°C to 70°C; Vcc=+SV±S%\
READ AND- WRITE TIMING
82530 (4MHz)
Number Symbol . Parameter
82530-6 (6 MHz)
Units
MIn
Max
1
tCl
ClK low Time
105
2000
70
1000-
ns
2
tCH
elK High Time
105
2000
70
1000
ns
3
tf
ClK Fall Time
20
10
ns
4
tr
ClK Rise Time
20
15
ns
5
tCY
ClK Cycle Time
2000
ns
6
tAW
Address to WRj Setup Time
7
tWA
8
tAR
9
tRA
10
tiC
11
12
tlW
tWI'
WRt Hold Time
Address to m5T Setup Time
Address to Fmi Hold Time
i'JiiW. to ClKI Setup Time
Tm'A to WRT Setup Time (Note"1)
(
Min
Max
250
Address to
II'ITA to wm Hold Time·
4000
165
80
80
ns
0
0
ns
80
80
ns
0
0
ns
0
0
ns
200
200
ns
0
0
ns
200
200
ns
0
0
ns
100
100
ns
13
tlR
IlilTA to Fmj
14
tRI
fiiiiTA10
15
tCI
m1t Hold Time
INTA to mt Hold Time
16
tClW
~ low to \7mj Setup Time
0
0
ns
17
tWCS
0
0
ns
18
tCHW
~ to WR"t Hold Time
~ High to 'WRj Setup Time
100
70
ns
19
tClR
~ low to Rl)j Setup Time (Note 1)
0
0
ns
20
tRCS
C"S to RDt
0
0
ns
21
tCHR
100
70
ns
22
tRR
CS High to J!fI5j Setup Time (Note 1)
RO low Time (Note 1)
390
250
ns
23
tRDA
Fm'j to Data Active Delay
0
0
ns
24
tRDI
ROt to Data Not Valid Delay
0
25
tRDV
RDj to Data Valid Delay
26
tDF
Rot to Output Float Delay (Note 2)
Setup Time (Note 1)
Hold Time (Note 1)
0
250
180
nl!
ns
70
45
ns
NOTES:
1. Parameter does not apply to Interrupt Acknowledge transactions.
2. Float delay is defined as the time required for a + O.5V change
in the output with a maximum D.C load and minimum A.C lOad.
'Timings are preliminary and subject to change.
7-258
230834-001
inter
82530/82530-6
A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUT OUTPUT
24
2.0
>
TEST POINTS
08
<
2.0
08
045---J
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC , AND 045V
FOR A LOGIC "0 ,. TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A
LOGIC " AND 0
FOR A LOGIC 0
ev
A.C. TESTING LOAD CIRCUIT
±
DEVICE
UNDER
TEST
CL=150pF
CL=150pF
CL INCLUDES JIG CAPACITANCE
OPEN DRAIN TEST LOAD
+5V
2.2K
7-259
230834-001
inter
82530/82530-6
eLK
--
~~~--:
_0
~.
o
0-
s
AlB, DIe
:-.J1---(1)----0®
- V~
1--0-~
x.
---:"I®
I-@- fi
INTA
~
1=-= ::'-
r-:-@
0,.--.
-
@r--®-
'-
-¥o
@-
-l
®
@
'-I
I--@-
~®~ ~
b-®-
®
](
- @,..:-
L.J
f-- @-
DBD-DB7
Read
-
1--0-
I-" -@
®
~
JLr-"
@
DBD-DB7
WRITE
READY/REQ
READY
X
J(
H-®
@-I- - ® :--\~
®
READY/REQ
REQUEST
6'i'Ri'REQ
REQUEST
-:-@
®
,
-
1
.-®--
j
J
@-
\.
,
®
Figure 14. Read and Write Timing
7-260
230834-001
82530/82530-6
INTERRUPT ACKNOWLEDGE TIMING, RESET TIMING, CYCLE TIMING
82530 (4MHz)
Number Symbol
27
tAD
Min
Parameter
Address Required Valid to Read Data
Max
82530-6 (6 MHz)
Min·
590
Max
Units
420
ns
Valid Delay
28
TWW
W'RLowTime
390
250
29
tOW
Data to \Wrl Setup Time
0
0
ns
ns
30
tWD
Data to WA! Hold Time
0
0
ns
31
tWRV
WRlto Ready Valtd Delay (Note 4)
240
200
ns
32
tRRV
Ri5'1 to Ready Valid Delay (Note 4)
240
200
ns
33
34
tWRI.
\VAl to READY/REO Not Valid .Delay
240
200
ns
tRRI
ADI to
J!fEAI5V/REQ' Not Valid
240
200
ns
35
tDWR
WR! to DTR/REQ Not Valid Delay
5tCY
+300
5tCY
+ 250
ns
36
tDRD
RD! to DTR/REa Not Valid Delay
5tCY
+ 300
5tCY
+ 250
ns
37
tCIV
CLKI to INT Valid Delay (Note 4)
500
500
ns
38
tllD
INTA to JfDI (Acknowledge) Delay
(Note 5)
39
til
lID (Acknowledge) Low Time
40
tlDV
mJl (Acknowledge) to Read Data
Valid Delay
41
tEl
IEfta
42
tiE
lEI to m5!,(Acknowledge) Hold Time
43
tEIEO
lEI to lEO Delay Time
120
100
ns
44
tCEO
CLK! to lEO Delay
250
250
ns
45
tRIl
ADI to iNT Inactive Delay (Note 4)
500
ns
46
tRW
RD! to WRI Delay for No Reset
30
15
ns
47
tWR
WRf to RDI Delay for No' Reset
30
30
ns
48
tRES
WR and RD COincident Low
for Reset
250
250
ns
49
tREC
Valid Access Recovery Time
(Note 3)
6tCY
+ 200
6tCY
+ 130
ns
Ani
Delay
ns
190
(Acknowledge) Setup Time
\
ns
250
285
180
120
100
0
0
500
ns
ns
ns
NOTES:
3, Param'eter applies only between transactions involving the see,
4, Open-drain output, measured with open-drain test load,
5, Parameter is system dependent. For any see in the daisy chain, tllO,must be greater than the sum of teEO forthe highest
priority device in the daisy chain, tEl for the see and tEIEO for each device separating them in the daisy Chain,
'Timings are preliminary and subject to change,
7-261
230834-001
inter
.,'
82530/82530-6
eLK
1tii'A _ _ _ _ _ _"'
@)
i----@--.j
~-------------~~----~----~
DBD-DB7 _--------------_+-------~_++_.,;£'
lEI,
lEO
I----@--~.j
I~~I______________________________________~~Jfr:-------
Figure 15. Interrupt Acknowledge Timing
Figure 16: Reset Timing
CS
RDORWR
11
/
}
@1
\
i'
\
\
Figure 17. Cycle Timing
2308~-oOl
82530182530-6
GENERAL TIMING
82530 4MHz)
'I
Number Symbol
Parameter
Min
1
tCRV
ClKI to READY/REGI Valid Delay
Max
82530-6 (6 MHz)
Min
TBD
Max
Units
TBD
ns
350
ns
2
tCRI
ClKI to Aeady Inactive Delay
3
4
tRCC
tARC
RxC! to ClK! Setup Time (Notes 1.4)
RxD to RxC(Setup Time (X1 Mode)'
(Note 1)
5
tACA
AxD to AxC! Hold Time (X1 Mode)
(Note ,1)
6
tOAC
RxD to RxCI Setup Time (X1 Mode)
(Notes 1,5)
7
tACO
RxD to RxCI Hold Time (X1 Mode)
(Notes 1,5)
8
tSRC
SYNC to AxC! Setup Time (Note 1)
9
tRCS
SYNC to RxC! Hold Time (Note 1)
3tCY
+ 200
10
tTCC
TxCI to ClK! Setup Time (Notes 2.4)
11
tTCT
TxCI to TxD Delay (X1 Mode)
(Note 2)
300
300
ns
12
tTCD
TxC! to TxD Delay (X1 Mode)
(Notes 2,5)
300
300
ns
13
tTDT
TxD to TRxC Delay (Send Clock
Echo)
14
tOCH
RTxC High Time
350
50
50
ns
0
0
ns
150
150
ns
0
0
ns
150
150
ns
-200
-200
ns
3tCY
+ 200
ns
ns
0
0
ns
180
ns
180
15
tOCl
RTxC low Time
180
180
ns
16
tOCY
RTXC Cycle Time
400
400
ns
17
tClCL
Crystal Oscillator Period
(Note 3)
250
18
tRCH
TRxC High Time
180
80
ns
19
tRCl
TAxC low Time
180
180
ns
20
tRCY
TRxC Cycle Time
400
400
ns
21
tCC
CD or CTS Pulse Width
200
200
ns
22
tSS
SYNC Pulse Width
200
200
ns
1000
250
1000
ns
NOTES:
1. AXe is RTxC or TRxC, whichever is supplYing the receive clock.
2. 'iX'C is TRxC or RTxC, whichever is supplying the transmit clock.
3. Both RTxC and SYNC have 30pF capacitors to ground connected to them.
4. Paramete.!.!.eplies only if the data rate is one-fourth the system clock (ClK) rate. In all other cases, no phase relationship
between RxC and ClK or TxC and ClK is required.
5. Parameter applies only to FM encoding/decoding.
'Timings are preliminary and subject to change.
7-263
230834-001
82530/82530-6
CLK
READY/REO
REOUEST
READY/REO
READY
Ri'iC, i'Rxi:
RECEIVE
RxD
SYNC
EXTERNAL
TRxC, iii'iC
TRANSMIT
TxD
'f'RxC
~'
~~--~---t==@~
----------'~~~-@-,3-----------~~~--~
--~~------
~-------------------------------------------------
OUTPUT
SYNC
iNPiJ'I'
Figure 18. General Timing
7-264
230834-001
82530/82530-6
SYSTEM TIMING
8~0(4MHz}
Number Symbol
Parameter
Axe t
READY/REO Valid
1
tRRV
2
tRW I
RxC t to Ready Inactive Delay
(Notes 1,2)
3
tRSC
4
5
fRIV
AXe
AXe
tTRV
TxC
6
tTWI
TxC
7
tTDV
TxC
8
9
tTIV
TxC I to INT Valid Delay (Notes 1,3)
tSIV
SYNC Transition to INT Valid Delay
10
tCTI
CD or C'i'S Transition to INT
Valid Delay
to
(Note 2)
t to
SYNC Valid Delay (Note 2)
REA5WRE'Q Valid
i5i'R/RE'Q Valid
TBD
TBD
TBD
TBD
tCY
TBD
TBD
TBD
TBD
tCY
4
7
4
7
tCY
TBD
TBD
TBD
TBD
tCY
TBD
TBD
TBD
TBD
tCY
TBD
TBD
TBD
TBD
tCY
TBD
TBD
TBD
TBD
tCY
TBD
TBD
TBD
TBD
tCY
TBD
TBD
TBD
TBD
tCY
2
6
2
6
tCY
Delay
I to Ready Inactive Delay
(Notes 1.3)
I to
(Note 3)
Units
Max
Delay
t to jji;j'j' Valid Delay (Notes 1,2)
I to
(Note 3)
82530-6 (6 MHz)
Min
Max
Min
,
Delay
(Note 1)
NOTES'
1 QE!n-d!!!!!2utput. measured wIth open-drain test load
2 fu!Q IS !lIxQ or TRXC. whichever IS suppling the receIve clock
3 TxC IS TRxC or RTxC. whIchever IS supplying the transmIt clock
"TImings are preliminary and subject to change
~~
--------------_r----___
R!~--------------_r--~--J
CD
~--------------_r--~
"""'"
....
........
---------------+--------.
'"
7-265
230834-<)01
ARTICLE
REPRINT
.
AR~186·
November 1981
Reprinted -wIth permission from ElectrOniCS August 25,1981 A McGraw HIli PublicatIon All rights reserved
7-266
Order Number ~ 210262..Q01
~ocalnebNcrk
architecture proposed
for work stations
General-purpose standard compatible with Ethernet will serve
many applications at a wide range of perfqrmance levels
by Robert Ryan, George Marshall, Robert Beach,
and Steve Kerman, Intel Corp" Sants Clsrs. Csllf.
o Computer-based communicating work stations and
microprocessor development systems, which promise to
usher in an era of electronic offices and workplaces, will
need to be attached to local networks through a standardized architecture in order to be cost-effective. In
response to the lack of'such a standard, Intel has come
up with a local network architecture that is currently
geared to work stations and development systems based
on Intel microprocessors. Called iLNA, the proposed
network takes advantage of the work already done in
association with Digital Equipment Corp. and Xerox
Corp. by using the EthC(rnet local network design as the
'basis for its own data-carrying scheme.
.
What has been proposed is a six-layer architecture
combining software and hardware that will expedite all
local network functions. Its goal is simply efficient,
flexible communication between users and application
programs, application programs and resources, and any
other combination of users, programs, and resources
within the local network.
The concept of a layered architecture is not new.
Indeed, IBM'S well-known Systems Network Architecture is layered, as is the forthcoming International Standards Oganization and American National Institute
Reference Model of Open Systems Interconnection.
,What is new is the fact that a network architecture has
been. specifically designed for Intel- and Ethernet-based
equipment (see "Specifying the network," p. 122). If
eventually accepted as an industry standard, the proposal will become the basis for future network architectures,
and manufacturers of equipment that hooks up to local
networks will want their equipment to be compatible.
In developing a local network architecture, the primary goal has to be achieving cost-competitiveness with
any general-purpose network design, while at the same
time equaling the efficiency and performance of a network designed for a specific application. Likewise, the
network has to facilitate communication through commonly used interfaces but not be bound by anyone
topology or internal communication mechanism. In addition, it has to function independently of any particular
computer's operating system or hardware.
The network also has to act as an error-free message-
delivery medium between communication processes
(programs resident in equipment attached to the network) and permit an operator or program to monitor,
maintain, and modify network operations. While performing all these chores, the network must also be able
to serve low-cost, low-performance equipment and incorporate future technology. In addition, the failure of any
device at a work station should have minimal effect on
the operation of other work stations.
To perform all these tasks, the Intel network architecture defines a set of interfaces, algorithms, and protocols
by which application programs on various kinds of Intel
microprocessor-based work stations can communicate. It
also establishes a process-to-process communication
m~chanism whereby a process (any application, function, or peripheral using the network) is defined as the
active element in a communicating node and the ultimate source or destination for data. Thus, for example,
terminals, files, and input/output devices can communicate with one another through the use of processes.
Messages are sent and received by the designated processes th.rough what is termed a communications socket,
which is a hierarchical address composed of three unique
identifiers-one each for the local network, the host, and
the port to a process.
Each node in the network, which may consist of one or
more pieces of equipment, has a unique host identifier
that distinguishes it from all other nodes installed anywhere, to ensure eventual communications between
equipment on various local networks. Within each node,
each process is given a local address, or port identifier.
The binding of ports to processes is the responsibility of
the node, and the ports remain unique within each node.
Certain ports, however, may be assigned numbers in
accordance with a globally consistent scheme.
Each installed local network will be given a unique
identifier, its network identifier, that identifies it in
multiple-network applications. In a single-network application, the network identifier is not used, but its assignment assures that an orderly progression to an internetworking environment is possible.
In designing its architecture, Intel examined applications needs of its users and chose a suitable set of
7-267
Electronici/ August 25, 1981
interconnect functions to serve them. These functions
were then defined in a series of layers that permit the
network to achieve high performance across a wide
applications base. The architecture is divided into six
layers (Fig. I). The ones of interesLhereare the physical-link, data-link. transport. session. and network-management layers. The network layer is used when one
local network must be connectedJo another.
The lowest-level means of sending data from one node
to another, the physical-link layer, is responsible for
delivering the smallest unit of data (the bit) the network
handles. This layer is the one directly concerned with the
transmission medium. signal type, data rate, and
mechanical interconnect specifications of the network. It
can be implemented using two modems, two telephone
sets, and a telephone line or using coaxial cable, a
baseband line driver, receiver chips, and a universal
synchronous-asynchronous receiver-transmitter (Usart).
ered, but all those that are, arrive unmodified. With
error-free packet !ielivery all packets are delivered (no
lost packets), all paekets are delivered just once (no
duplicate packets), and all packets are received in the
order sent (no nonsequential packets). However, when
error-free packet delivery is required, data-link error
control is necessary to perform packet sequencing and
retransmission. In addition, besides having the higherlevel error-coding alternatives previously noted, datalink error control also is expensive and, given the physical-link error rates, not cost-effective.
Data-link error control might provide a reliable node1. La,.rs. In the Intel local-network architecture. there are six levels
of hardware. and software. with the network layer omitted in strictly
local (non-store-and-forward) configurations. The physical link and
data link contain hardware; the others only software.
Moving from node. to node
While the physical link moves data bits from one node
to another, it cannot guarantee successful transmission.
Electrical noise in the environment causes errors,
although some transmission media are less susceptible
than others. For example, the error rates generally run
between 1 bit-error per 10,000 bits and 1 bit-error per
100,000 bits for transmissions over a modem-telephone
network, but can be less than I bit in 10 million for local
coaxial-cable-based networks.
Error rates can be kept quite low at the physical link
level if the network designer is willing to properly locate
and shield the network cabling from rf interference by
other electrical utilities in, say, a building. However, the
higher-level layers are a better place to reduce errors
because they can exploit such multiple-bit schemes as
redundancy codes and automatic repeat requests that are
not available at the physical link level.
In the Ethernet physical link, data is transmitted on a
50-ohm coaxial cable that is up to 500 meters long per
segment. The Manchester-encoded, baseband signal carri~s data at a rate of 10 megabits per second. At the start
of a transmission. a 64-bit preamble is used to stabilize
and synchronize the communication channel circuitry.
, After reception, the preamble is removed and only the
Ethernet header and data are passed on.
USER INTERFACE
Packet-delivery service
The data-link layer makes possible a node-to-node
packet delivery service. As such, it is the first step
toward a process.!o-process packet deliv!lry system. The
data link supplies some of the services missing from the
physical link. Among others, it is responsible for framing, or the determination of where a message begins and
ends; addressing, or the determination of Which station
should receive a message; error detection, or the determination of bit errors in the packet; and link, management,
which controls the access of multiple transmitters and
receivers to the physical link.
. A data link may deliver all the packets error-free by
using various error-correcting protocols. Or it may provide, as the Ethernet data-link architecture does, a besteffort delivery. service in which not all packets are delivElectronics/ August
25. 1981
7-268
FULL LOCAL NETWORK
ARCHITECTURE
S~eclfylng
The Digital Equipment-Intel-Xerox specification for the
Ethernet network is the first portion of Intel's forthcoming
local network architecture. and the first hardware produced for this architecture will be the Ethernet intelligent
controller. The two-board set. which plugs into an Intel
Multibus chassis. supplies many of the functions of the
physical- and data-link layers of the network architecture.
The data-link functions performed are framing (including
packet-boundary delineation and address recognition).
link management (including transmission scheduling and
retries in case of a collision between packets). and error
detection. The physical-link functions performed are preamble generation and removal and bit encoding and
decoding. The set also handles a number of systemoriented functions. such as interfacing with the system
parallel bus. communicating with the central processing
unit. handling data movement to and from the buffers. and
to-node delivery service, but it does not ensure a reliable
end-process-to-end-process delivery service. That is particularly true in any internetworking environment where
two or more local networks are connected and there are
multiple gateways (the physical and software connections) acting as packet forwarders. The risk of packet
nondelivery then is moderate to high. In addition, endto-end delivery retransmission (error control) would still
have to be performed at the transport layer, making
error control at the data-link layer redundant.
Collilion inlurlnce
The data-link software supports a large address
space- up to a 48-bit destination identifier and a 48-bit
source identifier - to permit flexibility in managing
internetwork gateways. In operation, data-link users
must supply both transmit requests and standby receivebuffers to the network. The transmit requests contain the
address of the destination nodes and the data to be sent.
The data iink combines both into a packet that is transmitted when the line becomes idle.
Should multiple nodes transmit concurrently, they aU
abort their transmissions, generate a jam signal that
reinforces the initial collision signal, wait a random
interval before retransmission to avoid repeated collisions, and then try again. The average retransmission
interval increases as a function of channel load in order
to achieve channel stability under overload conditions.
On the receiving side, the intended packets are recognized by the data link, which performs a 32-bit cyclic
redundancy check. If the packet is good, it is placed in
an empty receive buffer. A packet that has collided is
recognized as such and dropped.
As noted earlier, the data link supports framing,
addressing, error detection, and link management. hi the
IAtel Ethernet approach to framing, a carrier-sense func-.
tion determines the end of a packet. When the carrier is
lost, the packet is finished. The two-bit beginning-ofpacket indicator at the end of the preamble actuates
carrier sensing.
The address scheme permits a received packet to be
accepted by any number of nodes. The data link recog-
the network
interfacing with the transmitter-receiver units.
The board hardware consists of an Intel 8086
5-megahertz microprocessor with local random-accessand read-only memory. direct-memory-access channels
for sending. and receiving data at the required 10 megabits
per second. bit-serial send-and-receive logic. packet
address-recognition logic. error detection logic. and interval timers. One board contains the microprocessor. memory. timers and DMA control; the other contains the serial
send-and-receive and error-detection logic.
The boards implement part of the data-link layer and
also contain seven major software functions. These
include the executive (or scheduler). the rest of the datalink software. transport control. session control. network
management. the bootstrap. and diagnostics. Typically
these software functions are implemented with programs
that occupy small amounts of memory space.
nizes single-host, broadcast, and multicast addresses.
The first bit within the destination address distinguishes
between single-host and multicast delivery, and the next
47 bits determine the multicast group identifier. Broadcast addressing is simply a special case of multicast in .
which the next 47 bits are aU logical Is.
The link management function controls line access
when two or more nodes attemp~ to transmit data simultaneously .through an arbitration policy called carriersense multiple access with collision detection. With this
system, when a packet is to be sent, the link management
facility determines if another carrieris present. If this is
so, or if the interpacket gap time has not expired, the
waiting packet is not released onto the line. When the
data packet is finally transmitted, the link management
function monitors the line to determine whether a collision has occurred. If a collision is detected, the random
waiting period for retransmitting the packet is chosen by
executing what is known as a truncated binary exponential back-off algorithm.
Reliable tranlport
The transport layer software (there is no hardware in
this layer) makes possible location-independent, reliable
packet transmission. Users of this layer can establish,
maintain, and terminate virtual circuits, which represent
full-duplex data paths between sockets.
A virtual circuit is defined by its basic properties.
First, it permits mUltiple virtual connections to exist
between processes. Second, it can be dynamically managed by the communicating processes. Third, it can
accommodate message lengths that are independent of
transport communication. Finally, it transmits data in a
full-duplex error-controlled and flow-controlled format.
While the data-link layer makes a best-effort attempt
to move individual packets from one physiCal node to
another, the transport layer is reSponsible for reliably
moving a user's variable-length message, such as a file
transfer, ftom one process to another, even though the
underlying packet delivery service will occasionally drop
packets, duplicat~ packets, or deliver them out of order.
A secondary responsiblity of the transport layer is to
Electronics I August 25. 1981
7-269
2. EJCtMelone. The six-layer local network
architecture can be extended to include
remote network configurations by s!mply
adding the network layer and the new data
links. These new configurations can be colocated or geographically dispersed.
prevent fast transmitters from swamping slow receivers.
It also must ensure that the network's communication
subsystem resources (primarily media bandwidth, communications processor usage, and communications buffer memory) not be wasted in frequently retransmitting
packets when there is a speed mismatch. Both are
accomplished by a flow control function that throttles
fast transmitters when the rCFeiver cannot keep pace.
The transport software serves several other functions
as well. Since the transport layer should insulate user
software from the limiting characteristics of the underlying physical network, it performs fragmentation and
reassembly services that let the user software send arbitrarily long messages over the network. To accomplish
this, the transmitting transport software breaks messages
into packet-sized chunks and the receiving software then
reassembles them.
information exchange, the transport software uses a
combined error- and flow-control algorithm that permits
both functions to work at the same time. For processto-process addressing, the transport software adheres to
the standard network-address structure, which consists
of the network, host, and port identifiers.
The session control software layer identifies and
locates process names within the network. In order to
communicate, a process using the transport layer in one
node must know the socket of other processes. Since, it is
unlikely that the naming convention for processes under
a given computer's operating system conforms with that
used in another, the session layer resolves this problem
through a location-independent scheme known as a binding function, which provides users with standard-format,
location-independent names for remote processes they
must access.
Acknowledge and over
Tie. that bind
In order to provide its services, the transport software
carefully manages the user's service requests and the
packets exchanged on the data link. For example, the
transport software associates a unique sequence number
with every packet it sends. Likewise, the receiving transport software sends back acknowledgment packets, indicating with the sequence number which packets have
been correctly received and accepted. Packets not
acknowledged within a specified time are automati<;ally
retransmitted by the sender.
The transPort software controls the data flow by
exchanging information on the amount o..f receive-buffer
memory that each claims to have available. The amount
of buffer memory available is called a window, and a
receiver that has indicated it has a large amount of
receive buffer space is said to have its window wide <1pen.
The binding function is composed of two operationsmapping and updating. Mapping is the function that, on
demand from the user software, translates between process names and sockets. Updating distributes the mapping information throughout the network so that it is
available when needed at each node.
The session software also supplies network status
information to the. application software. In turn, the
transport software gives the session layer status information on its best estimate of the quality of the underlying
network layers. However, the decision to abort a connection is left to the'user for all but the most extreme cases,
such as evidence of total equipment failure.
Openwindow
If the transmitter has several data packets, they will
be delivered much faster if the receiver has sufficient
buffer space and has opened its window than if the
window is' small and requires an exchange of window
information after each packet is sent. To expedite the
Network management
The netw9rk-management software layer provides the
'user with all those functions not required for normal
operation. In addition, it includes diagnostic utilities for
accessing the network components when any portion of
the network fails. It also 'has maintenance tools that
gauge the performance of various network components
so users can plan for changing network demand.
Network management functions fall into one of three
Electronics/ August 25. 1981
7-270
3. HncI.r•. If two processes on two different local network nodes
want to communicate, the session layer software establishes a virtual
circuit between them. The transport- and data-link layers add headers for identification. addressing, and control.
APPLICATION LAYER
APPLICATION
LAYER DATA
without interfering with network operations. The network management layer in a node desiring information
from a remote node first sends a request to the network
management layer in the remote node. The management
layer in that remote node then performs the desired
function and transmits a response to the requesting node.
TRANSPORT LAYER AND DATA
APPLICATION
LAYER DATA
'Iolating errorl
DATA LINK LAYER
AND DATA
categories: operation, maintenance, or planning. The
operation category includes all functions that are performed on a day-to-day basis as part of normal network
operation. A major goal of the Intel network architecture has been eliminating the full-time network operator,
and thus only the network bootstrap and the manual
operations needed to add a new node to the network are
included in the management layer.
The network bootstrap is the, operational function used
by a booting node to load its operating system from
another network node. The bootstrap sequence begins
when the booting node transmits a multicast packet
addressed to any node that has a copy of the operating
system and is willing to send it. If such a node exists on
the local Ethernet data link, it will respond.
Should more than one node reply, the booting node
will accept the first reply and ignore all others. If no
reply is received, as would happen if either the request or
reply is lost in the network because of line noise, the
booting node will retransmit the request. If a reply still is
not received after several retries, the bootstrap attempt
will be aborted.
Preventive maintenance
The maintenance category detects failures in the network, even though it may be uncertain of exactly what
the problem may be. Problem detection proceeds
through three mechanisms. The first is a set of error
counters made possible by the management layer; the
second is an error-reporting and -logging mechanism;
and the third is user observation.
The first problem detection mechanisms, the error
counters, are maintained by the individual layers and
record occurrences of recoverable errors. The presence of
errors does not necessarily indicate a failure in that the
layers are designed to operate normally in the face of a
large number of errors. An excessive number of errors,
however, may indicate that a problem is developing.
Since this set of counters is maintained at each node in
the network, and since the nodes can be spread over a
large area, the network management layer includes a
remote examination function for interrogating nodes
The error-counting mechanism is supplemented by an'
error-reporting mechanism that logs problems detected
by the communication system to an error-logging file.
Once a problem has been detected, it is isolated to some
serviceable component through two mechanisms. First,
the same error counters are used to isolate the error.
Second, the management layer generates test traffic,
including a loopback function within each layer, and
observes the behavior of the system.
Generally, correcting the problem involves repairing
or replacing hardware. Some problems, however, can be
corrected simply by reinitializing a system component.
In that case, the management layer can stop and rein itialize each layer.
In its planning function, the management layer supplies the network administrator with statistical information about the use of the network to help in planning
network growth.
By way of example
To illustrate the operation of the software and hardware layers with a practical example, consider a case in
which there are two processes, A and B, that reside on
two different nodes (Fig 2). Application process A's
request to communicate with process B on some remote
node requires the cooperation of the communication
layers of each node.
The source node's session layer first determines that
process B resides at socket n, thus pinpointing process B
to a specific port residing in a specific node on a specific
network through the port identifier. By means of the
transport interface, the session layer then attempts to
create a virtual circuit between the source port and the
destination port. Assuming there are no conflicts on the
network, the virtual circuit is established after the two,
transport-layer sites exchange connection information.
The two processes can now send or receive over the
virtual circuit so that data can be delivered in order,
unmodified, and withe reactivated.
The common mode voltage and external termination
are identical to the RCV/ReV input. (See Figure 4.)
The CLSN/CLSN input also has a 15-volt maximum
protection and additional clamping against lowenergy, high-voltage noise signals.
A valid collision-presence signal will assert the 82501
COT output which can be directly tied to the
When a valid collision-presence signal is present the
CRS signal is asserted (along with COT). However, if
this collision-presence signal arrives within 6.0 ± 1.0
IJ.S from the time CRS was deasserted, only COT is
generated.
Internal Loopback
When asserted, LPBK causes the 82501 to route
serial data from its TXD input, through its transmit
logic (retiming and Manchester encoding), returning
it through the receive logic (Manchester decoding
and receive clock generation) to RXD output. The
internal routing prevents the data from passing
through the output drivers and onto the transmit
output pair, TRMT/TRMT. When in loopback mode,
all of the transmit and receive circuits, including the
noise filter, are tested except for the transceiver
cable output driver and input receivers. Also, at the
end of each frame transmitted in loopback mode, the
82501 generates a 1-lJ.sec COT signal within 1 IJ.sec
after the end of the frame. Thus, the collision circuits,
including the noise filter, are also tested in loop back
mode.
The watchdog timer remains enabled in loopback
mode, terminating test frames that exceed its time-out·
period. The watchdog can be inhibited by placing the
LPBK to a resistor connected to 12V ± 3V. The loop back
feature can still be used to testthe integrity of the 82501
by using the circuit shown in Figure 5.
In the normal mode (LP8K not asserted), the 82501
operates as a full duplex device, being able to transmit and receive simultaneously. This is similar to the
externalloopback mode of the 82586. Combining the
internal and external loopback modes of the 82586
and the internal loopback and normal modes of the
82501, incremental testing of an 82586/82501-based
interface can be performed under program control
for systematic f~ult detection and fault isolation.
~
input of the 82586 controller.
During the time that valid colliSion-presence transitions are present on the CLSN/CLSN input, invalid
data transitions will be present on the receive data
pair due to the superposition of signals from two or
more stations transmitting simultaneously. It is possible for RCV/RCV to lose transitions for a few bit
times due to perfect cancellation of the signals. In
any case, the invalid data will not cause any discontinuity of RXC.
Interface Example
The 82501 is designed to work directly with the 82586
controller in Ethernet as well as non-Ethernet 10
Mbps LAN applications. The control and data signals
oonnect directly between the two devices without
the need for additional external logic. The complete
82586/82501/Ethernet Transceiver cable interface' is
shown in FIGURE 4. The 82501 provides the driver
and receivers needed to directly connect to the
transceiver cable, requiring only terminating re.sistors on each input signal pair.
7-279
AFN-OOB64A
82501
20 MHz INTERNAL CLOCK
Figure 3. Start of Transmission and Manchester Encoding
5V
20
26
16
26
15
27
17
TXC
RTS
TXD
CTS
TO CPU
BUS
82586
CONTROLLER
iiXC
CRS
29 C1
GND
CDT
TXC Vee
TXD
TRMT
C1
2
62501
ESI
C2
8 RXC,
31
6
25
9
30
,
......
10
GND
TRMT
TEN
23
RXD
,.--_._-
eTHERNET TRANSCEIVER
CABLE
OV
CRS
CLSN
12
7en
RXD
CLSN
11
LOOPSACK
INPUT FROM PROCESSOR
NOTE:
C1 = 0.022 "F ± 10%
C2 = C3 = 30-35pF
Figure 4. 82586/82501/Transcelver Cable Interface
7-280
AFN-00864A
intJ
82501
ELECTRICAL CHARACTERISTICS
Please Note: The following specifications are preliminary values and are subject to ch~nge without notice.
Contact your local Intel Sales Office for the latest specifications.
D.C. CHARACTERISTICS
(TA = 0-70· C, Vcc = 5V ± 10"10)
Vee + 0.5
'±15OO
Vcc- 1.O
0.45
4.5
Units
V
V
mV
V
V
V
1.1
V
V
V
C~UT
Input Leakage Current (TIL)
Input Capacitance
Output Capacitance
Icc
IF
±200
10
20
200
/loA
pF
pF
mA
Input Forward Current (TIL)
-500
/loA
Symbol
VIL
VIH
VI OF
VCM
VOL
VOCM
VOH
VOOF
ILl
CIN
Parameter
Input Low Voltage (TIL)
Input High Voltage (TIL)
Input Differential Voltage
Input Common Mode Voltage
Output Low Voltage TIL or MOS
Common Mode Output
Min.
-0.5
2.0
±300
Vcc -2.5
Output High Voltage
TIL
MOS
Differential Output Swing
1.0
2.4
3.9
.6
A.C. CHARACTERISTICS
Max.
+0.8
Conditions
RCVandCLSN
RCVand CLSN
10L = 4mA
RL = 78 Ohms Differential
Termination and 1200
pulldown
10H =-1.0mA
10H =-400/loA
RL = 78 Ohms Differential
Termination and 1200
pulldown (TRMT)
0< VIN < Vcc VL = Vcc
,
f = 1 MHz
f = 1 MHz
VF= .45V
c) Differential inputs and outputs:
The 50% points of the total swing are used for
delay measurements. The rise and fall times of
outputs are measured at the 20 to 80% points.
The differential voltage swing at the inputs is
at least ± 300mV with rise and fall times of
3-15 ns measured at ±.2 volts. Once the
squelch 'threshold has been exceeded the
inputs will detect less than ±160 mV signals.
A.C. Measurement Conditions
I) TA = O· to 70°C, Vee = 5V ± 10%
II) The AC measurements are done at the following
voltage levels for the various kinds of inputs and
outputs
III) The AC loads for the various kind of outputs are
as follows:
a) TTL inputs and oututs: 0.8V and 2.0V
The input voltage swing is 0.4 to 2.4Vat least
with 3-10 ns rise and fall times.
a) TTL and,MOS: A 15-pF Capacitor to GND
b) Differential: A 10-pF Capacitor from each terminal to GND and a termination load resis.tor of 78 ohms in parallel with a 27 microhenries inductor between the two terminals.
b) MOS outputs: The rise and fall times are measured between 0.6Vand 3.6V points. The high
time is measured between 3.6V points and the
low time is measured between 0.6V points.
7-281
AFN-Q0864A
82501
TRANSMIT TIMING
Symbol
Parameter
Min.
Max.
Unit
99.99
100.01
ns
TXC Fall Time
5
ns
t3
TXC Rise Time
5
ns
'"
TXC Low Time
40
ns
ts
TXC High Time
40
ns
16
Transmit Enable/Disable to TXC Low
50
ns
t7
TXD Stable to TXC Low
50
Is
Bit Cell Center to Bit Cell Center of Transmit Pair Data
t9
t1
TXC Cycle Time
t2
ns
99.5
100.5
ns
Transmit Pair Data Fall Time[1J
1.0
5.0
ns
t10
Transmit Pair Data Rise Time [1J
1.0
5.0
ns
t11
Bit Cell Center to Bit Cell Boundary of Transmit Pair Data
49.5
50.5
ns
t12
TRMT starts approaching its high level from Last Positive Transition of
Transmit Pair Data during idle.
200
8000
ns
(
TRANSMIT TIMING
~~----+-~.r-----------+------JI
"
\
TXD
LAST BIT!
o
1/0
+
'8
IBML
TRMT (LAST BIT ~ 1)
TRMT,TJlMT(LASTBIT~l) ~
[+
+
1
Note:
1. Measured per 802.3 Para 6.5.1.1
7-282
AFN-lJ0864A
82501
RECEIVE TIMING
Symbol
t13
Parameter
Receive Pair Signal Pulse Width (at -.30V differential signal) of First
Negative Pulse for a) Signal Rejection by Noise Filter,
b) Noise Filter Turn-on in order to Begin Reception
t14
Duration which the RXC is held at low state
t15
t16[1]
Receive Pair Signal Rise/Fall Time at ±.2 volt
t 17 [1]
t18
Min.
Max.
Unit
30
15
ns
ns
1400
ns
20
ns
±20
±20
ns
ns
±20
±20
ns
ns
8
!LS
Receive Pair Bit Cell Center from crossover timing distortion:
In preamble
In data
Receive Pair Bit Cell Boundary allowing for timing distortion:
In preamble
In data
Receive Idle Time Before the Next Reception
the deassertion of CRS)
can~Begin
(as measured from
t19
Receive Pair 'Signal Return to Zero Level from Last valid Positive Transition
t20
CRS Assertion delay from the First received valid Negative Transition of
Receive Pair Signal
SyMbol
0.20
Min.
Parameter
!LS
100
ns
Max.
Unit
CRS Deassertion delay from the Last valid positive transition received
(when no Collision-Presence signal exists on the transceiver cable)
300[2]
ns
t24
RXC Jitter
±5.0
ns
t25
RXC Rise/Fall time
t26
RXC High/Low time
40
ns
t27
Receive Data Stable before the Negative Edge of RXC
30
ns
t28
Receive Data Held valid past the Negative Edge of RXC
30
t29
Carrier Sense deasserted before the Negative Edge of RXC
10
t30
Receive data Rise/Fall time
t31
From .the time CRS is deasserted until the time it can be asserted again
t21
,
ns
ns
30
ns
10
ns
7
!L S
5
NOTES:
1. ± 5 ns' of bias distortion-the remainder is random distortion.
2. CRS is deasserted synchronously with the RXC:This condition is not specified in the IEEE 802.3 specification.
12V
82501
LPBK
LPBK/WOTO
'~WDTD
1
0
WOTO
0
X
0
'1
Function
LPBK mode
Norma~mode
Normal mode with
watchdog timer disabled
• = Open Collector
Figure 5.
Watchdog Timer Disable
7-283
AFN-00864A
..
inter
82501
RECEIVE TIMING: START OF FRAME
I
I
I
I
I
0
0
I
l
I
:g-Bge? :J(,,,~
1 - - - - - - . 1, •.
- - - - -..... 1
RXD
'THIS CLOCK PULSE MAY NO,. BE A VALID CLOCK PULSE
, RECEIVE TIMING: END OF FRAME
I
+
0
-
I+
0
-
I
---1
+
:g~(LASTBIT = 0) :;:>QOQ<-----?;~~
I
:g~ (LAST BIT = 1)"
I
=x::=:::x
I'
J-t:9_ _ _ 118
:~ I },--
~"9~
r'21~
~-----~~~~--~-----
--------~--~/~I---'~----.
I'31----.~1
~ r-"9
RXD
-o --" /
'NOTE: CRS CAN BE TRIGGERED ON AGAIN BY THE COLLISION·PRESENCE SIGNAL.
7-224
AFN-00864A
intJ
82501
COLLISION TIMING
Symbol
Min.
Parameter
CLSN/CLSN Signal Pulse Width (at -.30V differential signal) of first
Negative Pulse for Noise Filter TlIrn-on
30
l33
CLSN/CLSN Cycle Time
86
t34
CLSN/CLSN Rise/Fall Time at ±.2 volts
t35
CLSN/~ Transition Time
l32
35
Max.
Unit
ns
118
ns
15
ns
70
ns
l36
~ Assertion from the First Valid Negative Edge of Collision Pair Signal
75
ns
t37
~ Deassertion from the Last Positive Edge of CLSN/~ Signal
200
ns
tae
CRS Deassertion from the Last Positive Edge of CLSN/CLSN signal (If no
post-collision signal remains on the receive pair.)
350
ns
t39
~ stable before the negative edge of
10
60
ns
Min.
Max.
Unit
P.S
RXC at deassertation
COLLISION TIMING
~----<
~--)c----------\\\'0
I
NOTE 1
RXC
NOTES:
1.
CAS WILL BE DEASSERTED FOR A PERIOD UP TO 7 !,SEC MAXIMUM
WHEN RCV/m;i7 OR CLSN/CLSN TERMINATES, WHICHEVER OCCURS
LATER.
2 CRS WILL REMAIN ASSERTED AFTER THE CLSN/CLSN SIGNAL
TERMINATES IF RCV/RCV SIGNALS CONTINUE.
LOOPBACK TIMING
Symbol
Parameter
l.4o
LPBK asserted before the first attempted transmission
500
1.41
Simulated collision test delay from the end of each attempted transmisssion
.5
1.5
ns
1.42
Simulated collision test duration
.5
1.0
1.43
LPBK deasserted after the last attempted transmission
5
p.s
p'S
NOTE:
In Loopback mode, AXC, 'RXD and CRS function in the same manner as a normal Receive.
7-285
AFN-00864A
82501
LOOPBACK TIMING
1 "'"
TXD
I
"0"
I
"'"
1
"0"
I
"0"
I
"'"
1
.~
1 -!----1 --J
41
CDT------------------------------------------~~I
\~
42
~
__________~&~,---------JI
1 "'"
·1
"0"
1 "'"
1
1 "'"
RXD ------------..:.--~~I----..:...-NOTE:
1. DURING LOOPBACK. THE 82501 RECEIVE CIRCUITRY USES 12 BIT TIMES
WHILE THE PLL LOCKS ON THE DATA AS A RESULT, THE FIRST 12 BITS
ARE LOST.
TESTABILITY
NOTES:
1. All AC parameters become valid after the PLL has stabilized: 1001's after the application of power.
2. TXC can be synchronized to tester clock by applying reset
signal (12V) to the TEN pin.
7-286
AFN-00864A
82586
LOCAL AREA NETWORK COPROCESSOR
•
Fully Implements the IEEE 802.31Ethemet
Data Link specifications without CPU
overhead.
•
Bus Interface optimized
188 microprocessors.
•
On-chlp DMA channels provide automatic
memory management.
•
Independent parallel bus and serial line
clocks.
........
•
Network diagnostics:
Frame CRC errors
Frame alignment errors
location of cable opens/shorts
Collision tallies
•
Self test diagnostiCS
Loop back
Register Dump
Backoff timer check
•
Efficient use of memory via buffer
chaln,lng.
•
User conflgurable to realize broadband,
short topology and 1 Mbps networks•
to IAPX 186 and
-
...
Vee
A..
A22(1ilii
• 11181
A..
A"
A..
A23(iiII)
iiiii!
ADlI
HOLD
HLDA
11 (OTill)
iii iIIIR)
READY
.NT
CAL~
ARDYlIRDY
Vee
CA
AD?
ADa
AESl!T
MN/iD
eLI(
AIlS
A..
A..
A..
Iliii
eDT
C'II
m
AD1
ADO
TXD
lie
1'lm
Vss '1.:..:._..:;r AX"
NOTE THE SYMItOLS IN PARENTHESES
CORRESPOND TO MINIMUM MODE-
figure 1. 82586 Functional Block Diagram
7-287
Figure 2. 82586 Pinout
November 1983
Order Number: 21078,3..003
inter
82586
The 82586 is an intelligent, high performance Local
Area Network coprocessor, implementing the
CSMAlCD link access method. (Carrier Sense Multiple Access with Collision Detection).
programmable, enabling the user to optiJTIize bus
overhead for a given worst case bus latency.
The 82586 performs.a large range of link management and channel interface functions including:
CSMAlCD link access, framing, preamble generation and stripping, source address generation, destination address checking, CRC generation and
checking. Any data rate up to 10 Mb/s can be used:
The 82586 provides a rich set of diagnostic and
network management fUnction!! including: internal
and externalloopbacks, exception condition tallies,
channel activity indicators, optimal capture of all
frames regardless of destination address, optional
capture of errored or collided frames, and time
domain reflectometry for locating fault points in the
cable.
The 82586 features a powerful host system interface. It automatically manages memory structures
with command chaining and bidirectional data
chaining. An on-chip DMA controller manages 4
. channels transparently to the user. Buffers containing errored or collided frames can be automatically
recovered. The 82586 can be configured for 8-bit or
16-bit data path, with maximum burst transfer rate of
2 or 4 Mbyte/sec, respectively. Memory address
space is 16 Mbyte maximum.
The 82586 can be used in conjunction with either
baseband or broadband networks. The controller
can be configured for maximum network efficiency
(minimum contention overhead) for any length
network operating at any data rate within the
82586's range. The controller supports address field
lengths of 1, 2, 3, 4, 5, or6 bytes.ltcan be configured
foreitherthe IEEE802.3/ Ethernet or HDLC method
of frame delineation. Both 16-bit and 32-bit CRC are
supported.
• The 82586 provides two independent 16 byte FIFO's,
one for receiving and one for transmitting. The
threshold for block transfer to/from melnory is
The 82586 is packaged in a 48 pin DIP and fabrjcated in Intel's reliable HMOS II 5 volt technology.
Table 1. 82586 Pin Description
Symbol
VCC,VCC
VSS,VSS
RESET
Pin No.
48,36
12,24
34
~pe
TxD
27
0
TxC
26
I
RxD
RxC
25
23
I
I
28
0
I
,
Ri'S
Name and Function
System Power: +5 volt power supply.
System Ground.
RESET is an active HIGH internally synchronized signal, causing the
82586 to terminate present activity immediately. The signal must be
HIGH for at least four clock cycles. The 82586 will execute RESET within
ten system clock cycles starting from RESET. HIGH. When RESET
returns LOW, the 82586 waits for the first CA to begin the initialization
sequence.
Transmitted Serial Data output signal. This signal is HIGH when not
transmitting.
Transmit Data Clock. This signal provides timing information to the
internal serial logic, depending upon the mode of data transfer. For NRZ
mode of operation, data is transferred to the TxD pin on the HIGH to
LOW clock transition.
Received Data input signal.
Received Data Clock. This signal provides timing information to the
internal shifting logic depending upon the mode of data transfer. For
NRZ data, the state of the .RxD pin is sampled on the HIGH to LOW clock
transition.
Request To Send signal. When LOW, notifies an external interface that
the 82586 has data to 1ransmit. It is forced HIGH after a Reset and while
the Transmit Serial Unit is not sending data.
7-288
210783-003
82586
Table 1. 82586 Pin Description (Cont'd.)
Symbol
rn
Pin No.
29
~pe
CAs
31
I
C'i5T
30
I
INT
CLK
38
32
0
I
MN/MX
33
I
ADO-AD15
6-11,
13-22
liD
A16-A18,
A20-A23
1,3-5,
45-47
\0
A19/S6
2
0
HOLD.
43
0
HLDA
42
I
I
,
i
Name and Function
Active LOW Clear To Send ,input enables the 82586 transmitt~o
actually si'lnd data. It is normally used as an interface handshake to RTS.
This Sig~Oing inactive stops transmission. It is internally synchronized. If TS goes inactive, meeting the setup time to TxC negative edge,
transmission is stopped and RTS goes inactive within, at most, two
TxC cycles.
Active LOW Carrier Sense input used to notify the 82586 that there is
traffic on the serial link. It is used only if the 82586 is configured for
external Carrier Sense. When so configured, external circuitry is
required for detecting serial link traffic. It is internally synchronized. To
' be accepted, the signal must stay active for at least two serial clock
cycles.
Active LOW Collision Detect input is used to notify the 82586 that a
collision has occurred. It is used only if the 82586 is confi'gured for
external Collision Detect. External circuitry is required for detecting the
collisiqn. It is internally synchronized. To be accepted, the signal must
stay active for at least two serial clock cycles. During transmission, the
82586 is able to recognize a collision one bit time after preamble
transmisSion has begun.
Active HIGH Interrupt request signal.
The system clock input from the 80186 or another symmetric clock
generator,
When HIGH, MN/MX selects RD, WR, ALE, DEN, DT/R (Minimum
Mode). When LOW, MN/MXselectsA22,A23, READY, 80,81 (Maximum
Mode). Note: This pin should be static during 82586 operation.
These lines form the time multiplexed memory address (t1) and
data (t2, t3, tW, t4) bus. When operating with an 8-bit bus, the high byte
will output the address during the entire cycle. ADO-AD15 are floated
after a RESET or when the bus is not acquired.
Used maximum mode only. These lines constitute 7 out of 8 most
significant address bits for memory operation. They switch during t1
and stay valid during the entire memory cycle, The lines are floated after
RESET or when the bus is not acquired.
During t1 it forms line 19 of the memory address. During t2 through t4 it
is used as a status indicating that this isa Master peripheral cycle, and is
HIGH, Its timing is identical to that of ADO - AD15during write operation.
HOLD is an active HIGH signal used by the 82586 to request local bus
mastership atthe end of the current CPU bus transfer cycle, or at the end
of the currer'lt DMA burst transfer cycle. In normal operation, HOLD
goes inactive before HLDA. The 82586 can be forced off the bus by
HLDA 'going inactive, In this case, HOLD goes inactive, at most, three
bus cycles after HLDAgoes inactive.
HLDA is an active HIGH Hold Acknowledge signal indicating that the
CPU has received the HOLD request and that bus control has been
relinquished to.the 82586. It is internally synchronized. After HOLD is
detected as LOW, the,processordrives HLDA LOW. Note, CONNECTING
VCC TOHLDA IS NOT ALLOWED because it will cause a deadlock.
Users wanting to give permanent bus access to the 82586 should
connect HLDA with HOLQ. If HLDA goes inactive before HOLD, th!,!
82586 will release the ,bus (by HOLD going inactive), within three bus
cycles at .most.
7-289
210783-003
8258~
Table 1. 82586 Pin Descrtption (Confd.)
Pin No.
Type
CA
35
I
BHE
44
0
READY
39
.I
SRDY/AADv
37
I
40,41
0
RD
46
0
"tim
45
ALE
39
0
DEN
40
0
Symbol
50,81
,.
0
Name and Function
The CA pin is a Channel Attention input used by the CPU to initiate the
82586 execution of memory resident Command Blocks. The CA signal is .
synchronized internally. The signal must be HIGH for at least one system
clo~k period. It.is latched internally on HIGH to LOW edge and then
detected by the 82586.
The Bus High Enable signai (§HE) is used to enable data onto the most
significant half of the data bus. Its timing is id.entical to that of A 16-A23.
With a 16-bit bus it is LOW and with an 8-bit bus it is HIGH. Note: after
RESET, the 82586 is configured to 8-bit bus.
. This active HIGH signal is the acknowledgement from the addressed
memory that the transfer cycle can be completed. While LOW, it causes
wait states to be inserted. This signal must be externally synchronized
with the system clock. The Ready s~RgY.ternal to the 82586 is a logical
OR between READY .and SRDY;~
.
This active HIGH signal performs the same function as READY. If it is
programmed at AR~~ure time to SRDY. it is identical to READY. If it is
programmed to
, the positive edge of the Ready signal is internally
synchronized. Note, the negative edge must still~setup and hold
time specifications, when in ARI5V mode. The ARDY signal must be
active for at least one system clock HIGH period for proper strObing. The
Ready signal internal to the 82586 is a logical OR between READY (in
Maximum Mode only) and SRDY/ARi5'Y. Note that following RESET, this
pin assumes ARDY mode:
Maximum mode only. These status pins define the type of DMA transfer
orted
STATUS word (written by 82586):
COMMAND word:
EL
S
(Bit 15)
(Bit 14)
- End of command list
- Suspend after
completion
(Bit 13)
- Interrupt after
completion
(Bits 0-2) - lA-SETUP" 1
I
CMD
C
B
(Bit 1-5)
(Bit 14)
OK
A
(Bit 13)
(Bit 12)
. - Command completed
- Busy executing
command
- Error free completion
- Command aborted
COMMAND word:
EL
S
(Bit 15)
(Bit 14)
- End of command list
- Suspend after
completion
(Bit 13)
- Interrupt after
completion
(Bits 0-2) - Configure" 2
I
LINK OFFSET: Address of next Command Block
CMD
INDIVIDUAL ADDRESS: Individual Address
parameter
The least significant bit of the Individual Address
parameter must be zero for IEEE 802.3/Ethernet
However, no enforcement of 0 is provided by the
82586. Thus, an Individual Address with least
significant bit 1, is possible.
CONFIGURE
The CONFIGURE command is used to update the
82586 operating parameters.
LINK OFFSET: Address of next Command Block
Byte 6-7:
BYTE CN' (Bits 0-3) - Byte Count, Number of
bytes including this one,
holding the parameters
to be configured. A
number smaller than 4
is interpreted as 4. A
number greater than 12
is interpreted as 12.
EVEN BYTE
ODD BYTE
15
C
B
OK
EL
S
I
ZEROS
A
I
.
I.
LINK OFFSET
FIFO LIM
EXT
LP
BCK
INT
LP
BCK
"REAM
LEN
AC
LOC
ADDRLEN
SAV
BF
SRD~I
ARDY
BOf,
MET
INTERFRAME SPACING
,
I I
ACR
I
RETRYNUM
SLTTM(H)
CDTF
CRS
SRC
CRSF
00
.
CMD-2
I
PAQ
BT
STF
I
,<
I
CRC INCRCITONOI
16
INS CRS
MIN
FRM
LEN·
02
~
04
BYTE CNT
06
08
LIN PRIO
SLOT TIME (L)
I
COT
SRC
0
OA
OC
~~~
iiBiZ I
BC lPRM
DIS
OE
10
Figure 13. The CONFIGURE COmmand Block
7-·300
210783-003
82586
ACR
(Bits 4-6) - Accelerated Contention
Resolution (Exponential
Priority)
Byte 8-9:
SRDWARD~(Bit 6)
o
SAV-BF
BOF-MEl (Bit 7)
- SRDY/A"Ri5Y pin
operates as ARDY
(internal
synchr2!l!!!tion ).
- SRDY/ARDY pin
operates as SRDY
(external
synchronization).
o-
INTER1Bits8-15) - Number indicating the
FRAME
Interframe Spacing in
SPACING
TxC period units
.
Byte 12-13:
(Bit 7)
o
- Received bad frames are
not saved in memory.
- Received bad frames are
saved in memory. ,
SLOTTIME (L)
(Bit 11)
o
(Bits
12-13)
(Bits
12-15)
- Maximum number of
transmission retries on
collisions
PRM
(Bit 0)
- Promiscuous Mode
BC-DIS
MANCHI
NRZ
(Bit 1)
(Bit 2)
- Broadcast Disable
- Manchester or NRZ
encoding/decoding
- NRZ
- Manchester
- Address and Type
Fields separated from
data and associated
with Transmit Command Block or Receive
Frame Descriptor. For
transmitted Frame,
Source Address is
inserted by the 82586.
- Address and Type Fields
are part of the Transmit!
Receive data buffers,
including Source
Addr.ess (which is not
inserted by the 82586).
PREAMLEN
(Bits 0-7) - Slot Time number, low
byte
SLT-TM (H)(Bits 8-10) - Slot Time number, high
bits
RETRYNUM
AT-LOC
- Exponential Backoff
Method
IEEE 802.3/Ethernet
1 - Alternate method
Byte 14-15·
0
1
TONO-CRS(Bit 3)
0
INT-LPBCK(Bit 14)
- Internal Loopback
EXT-LPBC'\(Bit 15)
- External Loopback.
NOTE: Bits 14 and 15
configured to 1, cause
Internal Loopback.
am
1
- Preamble Length
including Beginning of
Frame indicator:
00- 2 bytes
01 - 4 bytes
10- 8 bytes
11 - 16 bytes
NCRC-IN ~ (Bit 4)
CRC-16
(Bit 5)
0
,
1
BT-STF
- Transmit on No Carrier
Sense
- Cease transmission if
goes inactive during frame transmission
- Continue transmission
even if no Carrier Sense
(Bit 6)
0
1
- No CRC Insertion
- CRCType:
- 32 bit Autodin II CRC
polynomial
- 16 bit CCITT CRC
polynomial
Bitstuffing:
- End of Carrier mode
(Ethernet)
- HDLC like Bitstuffing
mode
Byte 10-11:
I
PAD
LIN-PRlol (Bits 0-2)1- Li\'lear Priority
7-301
(Bit 7)
0
- Padding
- No Padding
210783-003
82586
Table 2. 82586 Default Values.
- Perform padding by
transmitting flags for
remainder of Slot Time
1
Preamble Length
Length
Broadcast Disable
CRC-16/CRC-32
No CRC Insertion
Bitstuffing/EOC
Padding
Min-Frame-Lengtti
Interframe Spacing
Slot Tirne
Number of Retries'
Linear Priority
Accelerated Contention Resolution
Exponential Backoff Method
Manchester/NRZ
InternalCRS
CRS Filter
Internal CDT
COT Filter
Transmit On No CRS
FIFO THRESHOLD
SRDY/ARDY
Save Bad Frame
Address/Type Location
INT Loopback
EXT Loopback
Promiscuous Mode
(Bits 8-9) - Carrier Sense Filter in
bit times
CRSF
CRS-SRC (Bit 11)
0
1
Carrier Sense Source
- External
- Internal
CDTF
- Col!.ision Detect Filter in
bit times
- Collision Detect Source
- External
- Internal
(Bits
12-14)
CDT-SRC (Bit 15)
0
1
Byte 16:
MIN-FRM- (Bits 0-7)
LEN.
2
6
Addre~s
- Minimum number of
bytes in a frame
o
o
o
o
o
64
96
512
= • 15
o
o
o
o
o
o
o
o
o
8
o
o
o
o
o
o
CONFIGURATION DEFAULTS
MC-SETUP
The default values of the configuration parameters
are compatible with the IEEE 802.3/Ethernet Standards. RESET configures the 82586 according to
the defaults shown in Table 2.
This command sets up the 82586 with a set of
Multicast Addresses. Subsequently, incoming
frames with Destination Addresses from this set are
accepted.
15
ODD BYTE
C
B
EL
s
EVEN BYTE
0
o
OK
(STATUS)
2
(COMMAND)
LINK OFFSET
6
MC-CNT
MCLIST
2ND BYTE
1ST BYTE
I
MC~D
. NTH BYTE
ADDITIONAL MC-ID'S
'
Figure 14. The MC-SETUP Command Block
7-302
210783-{)03
82586
An incoming frame is accepted if it hasa Destination
Address whose least significant bit is a one, and
after hashing points to a bit in the HASH table
whose value is one. The hash function is selecting
bits 2 to 7 of the CRC register. RESET causes the
HASH table to become all zeros.
The MC-SETUP command includes the following
fields:
STATUS word (written by 82586):
C.
B
(Bit 15)
(Bit 14)
OK
A
(Bit 13)
(Bit 12)
- Command completed
- Busy executing
command
- Error free completion
- Command aborted
After the Transmit-Byte-Machine reads a MCSETUP command from TX-FIFO, it clears the HASH
table and reads the bytes in groups whose length is
determined by the ADDRESS length. Each group is
hashed l!sing CRC logic and the bit in the HASH
table to which bits 2-7 of the CRC register pOint is set
to one. A group that is not complete has no effect on
the HASH table. Transmit-Byte-Machine notifies
CU after completion.
COMMAND word:
(Bit 15)
(Bit 14)
EL
S
- End of command list
- Suspend after
completion
(Bit 13)
- Interrupt after
completion
(Bits 0-2) - MC-SETUP = 3
I
CMD
TRANSMIT
,
The TRANSMIT command causes transmission
(and if necessary retransmission) of a frame.
LINK OFFSET: Address of next Command Block
TRANSMIT CB includes the following fields:
MC-CNT: A 14-bit field indicating the number of
STATUS word (written by 82586):
byt~s
in the MC-LlST field. MC-CNT is truncated to
the nearest multiple of Address Length (in bytes).
Issuing a MC-SETUP command with MC-CNT=O
disables reception of any incoming frame with a
Multicast Address.
MC-LlST: A list of Multicast Addresses to be
accepted by the 82586. Note that the most significant
byte of an address is followed immediately by the
least significant byte of the next address. Note also
. that the least significant bit of each Multicast
Address in the set must be a one.
C
B
(Bit 15)
(Bit 14)
OK
A
S10
(Bit 13)
(Bit 12)
(Bit 10)
S9
(Bit 9)
- Command completed
- Busy executing
command
- Error free completion
- Command aborted
- No Carrier SeQse signal
during transmission
(between beginning of
Destination Address
and end of Frame
Check Sequence).
- Transmission
unsuccessful (stopped)
due to loss of Clear-toSend signal.
The Transmit-Byte-Machine maintains a 64-bit
HASH table used for checking Multicast Addresses
during reception.
15
ODD BYTE
C
B
OK
EL
S
I
A
I I I I I I I I I
0
S10
S9
S8
S6
57
S5
0
, EVEN BYTE..-
.
MAXCOLL
0
(STATUS)
CMD=4
LINK OFFSET
,
0
2
(COMMAND)
4
NEXT BD OFFSET
2ND BYTE
I
NTH BYTE
DESTINATION ADDRESS
I
I
1ST BYTE
I
6
\
E8
A
C
TYPE FIELD
.E
Figure 15. The Transmit Command Block
7-303
210783-003
inter
S8
82586
(Bit 8)
S7
56
S5
MAXCOll
~
Transmission
unsuccessful (stopped,
due to DMA underrun,
, (Le. data not supplied'
from the system for
transmiSSion).
(Bit 7)
- Transmission had to
Defer to traffic on the
link.
(Bit 6)
- Heart Beat, indicates
that during Interframe
Spaoing period after thE
previous transmission, ~
pulse was detected on
the Collision Detect pin
(Bit 5)
- Transmission attempt
stopped due to number
of collisions exceeding
the maximum number
of retries.
(Bits 3-0) - Number of Collisions
experienced by this
frame. 85 = 1 and MAXCOll = 0 indicates that
there wer:e 16 collisions.
(Bit 15)
(Bit 14)
I
CMD
TYPE FIELD: Type Field of the frame.
STATUS word:
EOF
ACTCOUNT
- Indicates that this is the
Buffer De~riptor of the
last buffer of this
frame's Informati(;I1'~ ,
Field.
(Bits 0-13) - Actual number of data
bytes in buffer (can be
even or odd).
NEXT BD OFFSET: points to next Buffer Descriptor
in list. If EOF is set, this field is meaningless.
BUFFER ADDRESS: 24-bit absolute address of
buffer.
.'.
TIME DOMAIN REFLECTOMETER - TOR
'
This command performs a Time Domain Reflectometer test on the serial link. By performing the
command, the user is able to identify shorts or opens
and their location. Along with transmission of ~II
Ones: the 82586 triggers an internal timer. The timer
measures the time elapsed from transmission start
until 'echo' is obtained. 'Echo' is indicated by
Collision Detect going active or Carrier Sense
signal drop.
COMMAND word:
El
S
DESTINATION ADDRESS: Destination Address of
the frame.
- End of command list
- Suspend after
completion
(Bit 13)
- Interrupt after
completion
(Bits 0-2) - TRANSMIT = 4 •
TOR comlTland includes the following fields:
STATUS word (written by 82586):
LINK OFFSET: Address of next Command Block
TBD OFFSET: Address of list of buffers holding the
Information field. TBD-OFFSET =,OFFFFH indicates
'that there is no Information field.
C.
B
(Bit 15)
(Bit 14)
'~
OK
(Bit 13)
- Command completed
- Busy executing
command
- Error free completion
EVEN BYTE
0
ACrCOUNT
~
NEXT BD OFFSET
________________________________________________
--;2
BUFFER ADDRESS
Figure 16. The lhInamlt Buffer Descriptor
7-304
210783~03
inter
15
82586
ODD BYTE
C
B
EVEN BYTE
0
OK
LINK OFFSET
r--r--r--r--r77r--------------------------------~4
LNK
OK
~~---L
__
~~~£L
TIME
____________________________________
~6
Figure 17. The TOR Command Block
COMMAND word:
ET-SRT
(Bit 15)
(Bit 14)
- End of command list
- Suspend after
completion
(Bit 13)
- Interrupt after
completion
(Bits 0-2) - TOR - 5
EL
S
I
CMO
TIME
- -S-hort on the link
identified (valid only in
the case of a
Transceiver that returns
Carrier Sense during
transmission).
(Bits 0-10) - Specifying the distance
to a problem on the·link
(if one exists) in
transmit clock cycles.
(Bit 12)
LINK OFFSET: Address of next Command Block
DUMP
RESULT word:
LNK-OK
I
(Bit 15)
XCVR-PRB(Bit 14)
ET-OPN
(Bit 13)
- No link problem
identified
- Transceiver Cable
Problem identified (valid
only in the case of .a
Transceiver that does
not return Carrier Sense
during transmission).
_. Open on the link
identified (valid only in
the case of a
Transceiver that returns
Carrier Sense during
transmission).
This command causes the contents of over a
hundred bytes of internal registers to be placed in
memory. It is supplied as a self diagnostic tool, as
well as to supply registers of interest to the user.
OUMPcommand includes the following fields:
STATUS word (written by 82586):
C
B
(Bit 15)
(Bit 14)
OK
(Bit 13)
- Command completed
- Busy executing
command
- Error free completion
o
15
o
C
B
OK
~--~~--_4~~~~~~~~~~~~~~~~~~~~--_r--,_~(STATUS)
EL
CMD=6
S
2
~--L-~--~~~~~~~~~~~~~~~~~~~~~---L--~~(COMMAND)
LINK OFFSET
~------------__-------------------------------------------44
BUFFER OFFSET
~----------------------------.-~---.-------------'
Figure 18. The DUMP Command Block
/-305
2·,0783-003
82586
COMMAND word:
EL
S
I
CMD
After RESET - 'All Ones.'
I
(Bit 15)
(Bit 14)
- End of command list
- Suspend after
completion
(Bit 13)
- Interrupt after
completion
(Bits 0-2) - DUMP = 6
After good frame reception 1.' For CRC-CCITT - OD1 FOH.
2. For CRC-Autodin-I/ - 7C40DD7BH.
After Bad Frame reception - corresponds to the
received information.
LINK OFFSET: Address of next Command Block
BUFFER OFFSET: This word specifies the offset
portion of the memory address which points to the
top of the buffer allocated for the dumped registers
contents. The length of the buffer is 170 bytes.
After reception attempt, I.e. unsuccessful check
for address match, corresponds to the CRC
performed on the frame address.
10
NOTE
Any frame on the serial link modifies this
register contents.
15 14
DUMP AREA FORMAT
AI~
Figure 18 shows the format of the DUMP area. The
fields are as follows:
Bytes OOH to OAH: These bytes correspond to the
82586 CONFIGURE command field (except bit 6 of
the first word).
Bytes OCH to 11H: The Individual Address Register
content. IARO is the Individual Address least significant byte.
." ~'1!1\
13
12
11
7
6
5
4
3
2
1
0
FIFO liM
0
.,~
0
0
0
0
0
0
00
L~t ADOR LEN
SAV
1
1
1
1
1
1
02
1
liN
XIXI
PREAM
LEN
10
9
8
~~~l
COTF
1 11
".
NUM
0
1
"
OK
Bytes 121:1 to 13H: Status word of last command
block (only bits 0-13):
Bytes 14H to 17H: Content of the Transmit CRC
generator. .TXCRCRO is the least significant byte.
The contents are dependent on the activity before
the DUMP command:
SlT TM [H]
CRS
SRC
CRSF
1
1
1
ACR
NET
1
1
II%\'
E90F
INTER FRAME SPACING
RETRY
OP
I
MIN
1
1
0
"
OK
After successful transmission - 'A.l1 Zeros.'
After MC-SETUP command - Generated CRC
~KK
After unsuccessful transmission, depends on
where it stopped.
NOTE
For 16-bit CRC only TXCRCRO. and
TXCRCR1 are valid.
Bytes 18H to 1BH: Contents of Receive CRC
Checker. RXCRCRO is the least significant byte.
The contents are dependent on the activity performed before the DUMP command:
,~,
ET
08
OA
IAR1
IARO
OC
IAR3
IAR2
OE
lARS
IAR4
01
0
LST
LST
CRS CTS
URN
TX HRT MAX
DEF BT COL
10
COll NUM
0
12
TXCRCR 1
TXCRCR 0
14
TXCRCR 3
TXCRCR 2
16
RXCRCR 1
RXCRCR 0
18
RXCRCR 3
RXCRCR2
lA
TEMPR 1
TEMPR 0
lC
TEMPR 3
TEMPR 2
IE
CRC
'RR
1
TEMPR4
ALN
'RR
0
OVAN
HRT NO
PKT EOP
1
1
1
20
1
1
1
22
HASHR 1
HASHR 0
HASHR 3
HASHR2
26
HASHRS
HASHR4
28
HASHR 7
value of the last MC address,'on MC-LlST.
gl~ PRM
lEN
PAC
04
06
i
:~F IC1~C MI~:C WA~O
TEMPRS
After RESET - 'All Ones.'
ILl
SLOT TIME
PAD
PRIO
ET
0 .... SRT
lJ'.
2'
HASHR 6
)1C..
A
2A
X IX IX X X X ,X- iX A
IX X r)(' X
IX
)1C..
~
2C
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
O.
0
32
0
0
0
0
0
0
0
0
.0
0
0
0
0
0
0
O· 34
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
36
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
38
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3A
IX IX IX' IX IX lX IX IX
0
0
Ell><
0
0
0
0
0
0
)1C.. .)1C..
X X IX
0
0
0
X' IX' IX lX lX
0
0
NXT RB SIZE
AOR lEN
2E·
3C
3E
40
Figure 19. The DUMP Area
7-306
. 210783-003
inter
82586
1514131211109876543210
ELIX)
CUR RB SIZE
46
LA RBDADR
48
NXTR8DADR
4A
CURRBDADR
4C
CUR RB EBC
4E
NXT PO ADR
50
CUR
PO ADR
RBD
,.
""'IX)
NXTRBADR L
24
PRY
EL
S
I
56
58
Bytes 2CH to 2DH: Status bits of the last time TDR
command that was performed.
NXTTB AD L
5A
LATBD ADR
5C
ADR
5E
I...\.\.'\.\.\.\.\.'\.'\.'\.'\.'\.'\.'\.'\.1 gg~: ~~~
NXTCBADR
60
64
CURCBADR
SCBADR
66
68
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
lic
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6E
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X X X X X X
X .x X X X X
.x IX IX ~
x
X
><
x IX
70
72
0
X
0
0
0
0
0
0
76
0
0
0
0
0
0
0
0
0
0
0
0
0
0
78
0, 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7A
X X
X
X
X X
X IX X
7C
X
SAY
.~
X
X
FIFO
0
0
0,X 0
0
."
LIM
..
.oe
SP
~
IX I:X"
L~ 0
X X X
..
0
0
X
O~ "M
'"
M'
~,
~,
CX PR
CHR RNR
0
1
0
RU RU
IDL RDY
X X
X X
X
X
X
X
X IX X
0
0
0
0
0
0
.x
.x .x
.x .x
X
0
x:
0
0
><
0
X
X
X )( X
0
0
0
0
0
0
~
.""'
~
'"""
RU
sus
0
0
0
0
7E
0
0
0
0
80
0
0
0
0
82
X X
84
X X X
0
0
86
XX X X
I)<
.x
88
X X
X X
X IX
I)<
X
X
8A
0
0
0
0
0
X
.x 8C
X 8E
BUFADR PTR H
0
BUF ADR
PTR
90
L
92
RCVDMABC
0
0
0
0
0
0
94
ADR_H
BR+BUF
0
0
96
98
RCVDMAADRH
9A
RCVDMAADRL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0)
0
9C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
9E
0
0
0'
0
Ci
0
0
0
0
0
0
0
0
0
0
0
AO
CUR-RB-SIZE: The, number of bytes in the last
buffer of the last received frame. EL - The EL bit of
the last buffer in the last received frame.
0
A2
NXT-RBD-ADR: Next Receive Buffer Descriptor
Address. Similar to LA-RBD-ADR but points to N+'1
Receive Bu'ffer Descriptor.
CUR-RBD-ADR: Current Receive Buffer Descriptor
Address. Similar to LA-RBD-ADR, but points to Nth
Receive Buffer Descriptor.
CUR-RB-EBC: Current Receive Buffer Empty Byte
Count. Let N be the currently used Receive Buffer.
Then CUR-RB-EBC indicates the Empty part of the
buffer, Le. the ACT-COUNT of buffer N is given by
the difference between its SIZE and the CURRB-EBC.
NXT-FD-ADR: Next Frame Descriptor Address.
Define N as the last Receive Frame Descriptor with
bits C=1 and B=O, then NXT-FD-ADR is the address
of N+2 Receive Frame Descriptor (with B=C=O) and
is equal to the LINK-ADDRESS field in N+1 Receive
Frame Descriptor.
CUR-FD-ADR: Current Frame Descriptor Address.
Similar to next NXT-FD-ADR but refers to N+1
,Rece'ive Frame Descriptqr (with B=1, C=O).
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
Q
...,
.RD,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A8
,
NXT-RB-ADR: Let N be the last Receive Buffer used,
then NXT-RB-ADR is the BUFFER-ADDRESS field
in the N+1 Receive-Buffer Descriptor, Le. the pointer
to the N+1 Receive Buffer.
LA-RBD-ADR: Look Ahead Buffer'Descriptor, Le .
the pointer to N+2 Receive Buffer Descriptor.
74
0
0
NXT-RB-SIZE: Let N be the last buffer of the last
received frame, then NXT-RB-sIZE is the number of
bytes of available in the N+1 buffer. EL - The EL bit of
the Receive Buffer Descriptor.
62
xxxxlxXIXXXXXXxxxx
IX :X"
Bytes 22H to 23H: Receive Status Register. Bits
6,7,8,10,11 and 13 assume the same meaning as
corresponding bits in the Receive Frame Descriptor
Status field.
Bytes 24H to 2BH: HASH TABLE.
54
NXTTB CNT
TBD
Byte.1CH to 21H: Temporary Registers.
52
ADR
BUFADR
NXT
Figure 1$. DUMP Area (con't)
42
NXTRB ADRH
'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\.'\1
A4
Byte. 54H to 55H: Temporary register.
7-307
210783-003
82586
NXT-TB-CNT: Next Transmit Buffer Count. Let N be
the last transmitted buffer of the TRANSMIT command executed recently, the NXT-TB-CNT is the
ACT-CQUNT field in the Nth Transmit Buffer
Descriptor. EOF - Corresponds to the EOF bit of the
Nth Transmit Buffer" Descriptor. EOF=1 indicates
that the last buffer accessed by the 82586 during
Transmit was the last Transmit Buffer in the data
buffer chain associated with the Transmit Command.
Frame Desc~iptor used recently, then RU-SUS,FD is equivalent to the S bit of N+1 Receive
Frame Descriptor.
Bytes 82H, 83H:
RU-SUS (Bit 4) - Receive Unit in SUSPENDED
state.
I
RU-NRSRC (Bit 5) - Receive Unit in NO
RESOURCES state.
BUF-ADR: Buffer Address. The BUF-PTR field in
the DUMP-STATUS Command Block.
RU-RDY (Bit 6) - Receive Unit in READY state.
RU-IOL (Bit 7) - Receive Unit in IDLE state.
NXT-TB-AD-L: Next Transmit Buffer Address Low.
Let N be the last Transmit Buffer in the transmit
buffer chain of the TRANSMIT Command performed
recently, then NXT-TB-AD-L are the two least significant bytes of the Nth buffer address.
LA-TBD-ADR: Look Ahead Transmit Buffer Descriptor Address. Let N be the last Transmit Buffer in the
transmit buffer chain of the TRANSMIT Command
pe'rformed recently, then LA-TBD-ADR is the NEXTBD-ADDRESS field of the Nth Buffer Descriptor.
NXT-TBD-ADR: .Next Transmit Buffer, Descriptor
Address. Similar in function to LA-TBD-ADR but
related to Transmit Buffer Descriptor N-l Actually, it
is the address of Transmit Buffer Descriptor N.
RNR (Bit 12) - RNR Interrupt In Service bit.
CNR (Bit 13) - CNR Interrupt In Service bit.
FR (Bit 14) - FR Interrupt In Service bit.
CX (Bit 15) - CX Interrupt In Service bit.
Bytes 90H to 93H:
BUF-ADR-PTR - Buffer pointer is the absolute
address of the bytes following the DUMP
Command block.
Bytes 94H to 95H:
Bytes 60H,61H: This isa copyof the 2nd word in the
DUMP-STATUS command presently executing.
RCV-DMA-BC - Receive DMA Byte Count. This
field contains number of bytes to be transferred
during the n~xt Receive DMA operation. The
value depends on AT-LOCation configuration
bit.
NXT-CB-ADR: Next Command Block Address. The
LINK-ADDRESS field in the DUMP Command Block
presently executing. Points to the next command.
1. If AT-LOCation = 0 then RCV-OMA-BC =
(2 times ADDR-LEN plus 2) if the next
Receive Frame Descriptor has already
been fetched.
CUR-CB-ADR: Current Command Block Address.
The address of the DUMP Command Blockcurrently
executing.
2. If AT-LOCation = 1 then it contains the size
of the next Receive Buffer.
BR+BUF-PTR+96H - Sum of Base Address plus
BUF-PTR field and 96H.
SCB-ADR: Offset of tile System Control Block
(SCB).
RCV-DMA-ADR - Receive DMA absolute Address. This is the next RCV-DMA start address.
The value depen9s on AT-LOCation configuration bit.
Bytes 7EH, 7FH:
'RU-SUS-RQ (Bit 4) - Receive Unit Suspend
Request.
l
Bytes 80H,81H:
CU-SUS-RQ (Bit 4) - Command Unit Suspend
Request
'
END-OF-CBL (Bit 5) - End of Command Block
List. If '1' indicates that DUMP-STATUS is the
last command in the command chain.
If AT-LOCation = 0, then RCV-DMA-ADR
is the Destination Address field located in
the next Receive Frame Descriptor.
2. If AT-LOCation = 1, then Rcv-bMA-ADR
is the next Receive Data Buffer Address.
ABRT-IN-PROG (Bit 6) - Command Unit Abort/
Request.
RU-SUS-FD (Bit 12)- Receive Unit Suspend
Frame Descriptor Bit. Assume N is the Receive
7-308
210783-{)03
82586
o
15
C
B
EL
S
OK
CMD=7
2
~_'~__-L__~~~~~~~~~~~~~~~~~~~~L-~L-~L-~(COMMAND)
L-____________
~
__________________________________
__J4
LINK OFFSET
Figure 20. The DIAGNOSE Command Block
The Receive Frame Area, RFA, is prepared by the
host CPU. data is olaced into the RFA hv the 82586
as frames are received. RFA consists of a list of
Receive Frame Descriptors (FD), each of which is
associated with a frame. RFA-OFFSET field of SCB
points to the first FD of the chain; the last FD is
identified by the End-of-Ust flag (ELl. See Figure 21.
The following nomenclature has been used in the
DUMP table:
o
-
The 82586 writes zero in this location.
- The 82586 writes one. in this location.
x
- The 82586 writes zero or one in this
location.
III
- The 82586 copies this location from
the corresponding position in the
memory structure.
FRAME DESCRIPTOR (FO) FORMAT
The FD includes the following fields:
STATUS word (set by the 82586):
DIAGNOSE
The DIAGNOSE Command triggers an internal selt,
test procedure of backoff related registers and
counters.
C
(bit 15)
B
(bit 14)
OK
(bit 13)
S11
(bit 11)
S10
(bit 10)
S9
(bit 9)
S8
S7
(bit 8)
(bit 7)
S6
(bit 6)
The DIAGNOSE command includes the following:
STATUS word (wriHen by 82586):
C
B
(bit 15)
(bit 14)
OK
(bit 13)
FAIL
(bit 11)
- Command completed
- Busy executing
command
- Error free
completion
- Indicates thet the self
test proced~'e failed
COMMAND word:
EL
S
I
CMD
- End of command list
- Suspend after
completion
- Interrupt after
(bit 13)
completion
(bits 0-2) - DIAGNOSE =7
(bit 15)
(bit 14)
- Completed storing
frame.
- FD was consumed by
RU.
- Frame received
successfully. If this bit is
set, then all others will
be reset; if it is reset,
then the other bits will
indicate the nature of
the error.
- Received frame
experienced CRC error.
- Received frl;lme
experienced an
alignment error.
- RU ran out of resources
during reception of this
frame.
- RCV-DMA overrun.
- Received frame had
fewer bits than
configured Minimum
Frame Length.
- No EOF flag detected
(only when configured
to Bitstuffing).
COMMAND word:
LINK OFFSET: Address of next Command Block
EL
S
RECEIVE FRAME AREA (RFA)
7-309
(bit 15)
(bit 14)
- Last FD in the list.
- RU should be
suspended after
receiving this frame.
210783'()OO
inter
82586
LINK OFFSET: Address of next FD in list.
\
DESTINATION ADDRESS (written by 82586): Contains Destination Address of received frame. The
length in bytes. it· is determined by the Address
Length configuration parameter.
RBD-OFFSET (initially prepared by the CPU and
later may be updated by 82586): Address of the first
ABO that represents the Information Field. ABDOFFSET = OFFFFH means there is no Information
Field.
L
SCB
r-:-~FAPOINTEF fSTATISTICS
TO
COMMAND
BLOCK·
LIST
I.
'-----:+
RECEIVE
FRAME
DESCRIPTORS
.
RECEIVE FRAME AREA
RFD1
I
-l
L
STATUS
J
VALID
PARAMETERS
RBD1,
o IACT:
RECEIVE
BUFFER
DESCRIPTORS
STATOS
,
--
I
r-
STATUS
-~
EMPTY
EMPTY
r
L
RBD2
1
RBD4
RBD3
ACT~jS o
-r
ACT-cnt
Ir
0
ACT-cnl
~
-r
STATUS
EMPTY
RBDS
r. -
o I ACT-cnt
~
I
RECEIVE
BUFFERS
r--"---
-'--
VALID
DATA
VALID
DATA
"--BUFFER 1
1-
I
-
BUFFER 2
RECEIVE FRAME LIST
,..-'---
r--'--
'--BUFFER 3
BUFFER 4
- 1••_ _ __
I
----
r--'--
-----
BUFFERS
FREE FRAME LIST
Figure .21. The Receive Frame Area
7-310
210783-003
inter
82586
EVEN BYTE
C
B
EL
S
0
, LINK OFFSET
4
RBD-OFFSET
6
2ND BYTE
1ST BYTE
DESTINATION ADDRESS
10
NTH BYTE
12
1ST BYTE
2ND BYTE
14
SOURCE ADDRESS
18
NTH BYTE
18
2ND BYTE
1ST BYTE
TYPE FIELD
20
Figure 22. The Frame DeSCriptor (FD) Format
SOURCE ADDRESS (written by 82586): Contains
Source Address of received frame. Its length is the
same as DESTINATION ADDRESS
TYPE FIELD (written by 82586): Contai ns the 2 byte
Type Field of received frame.
RECEIVE BUFFER
DESCRIPTOR FORMAT
The Receive Buffer Descriptor (RBD) holds information abouta buffer; size and location, and the means
for forming a chain of RBDs, (forward pOinter and
end-of-frame indication).
STATUS word (written by the 82586):
(bit 15)
F
(bit 14)
ACT
COUNT
ELISIZEEL
SIZE.
(bit 15)
- Last BD in list.
(bits 0-13) - number of bytes the
buffer is capable of
holding.
ELECTRICAL AND TIMING
CHARACTERISTICS
PLEASE NOTE:
The following specifications are preliminary
values and are subject to change without
notice. Contact your local Intel Sales Office
for the latest specifications.
The Buffer Descriptor contains the following fields:
EOF
BUFFER ADDRESS: 24-bit absolute address of
buffer.
- Last buffer in received
frame.
- ACT COUNT field is
valid.
SYSTEM INTERFACE
A.C. TIMING' CHARACTERISTICS
(bits 0-1~) - Number of bytes in the
buffer that are actually
occupied.
TA=0-70° C, Vcc=5V±10%
NEXT RBD OFFSET: Address of next BD in list of
BD's.
Figure 24 and Figure 25 define how the measurements should be done:
7-311
210783-003
82586
15
o
ACT COUNT
EOF
~__~__~__~__~__~__- L__~__~__~__~~~L-~L-__L -__L -__L--1(STATUSI
NEXT BD OFFSET
~--------~----------------------------------~
2.
4
BUFFER ADDRESS
6
A23
8
SIZE
Figure 23. The Receive Buffer Descriptor (RBO) Format
INPUT AND OUTPUT WAVEFORMS FOR AC TESTS
2 . 4 - V1:5 --·-TEST POINTS - - 1 . 5
.
D.45~
V--
7"...--
AC TESTING INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC 1 AND
0.45 FOR A LOGIC O. TRIMMING MEASUREMENTS ARE MADE
AT 1.5V FOR BOTH A LOGIC 1 AND 0
Figure 24. TTL Input/Output Voltage Levels For Timing Measurements
T&
T7
HIGH LEVEL MAY
VARY WITH VCC
T4
T1
MOS I/O MEASUREMENTS ARE TAKEN AT
Q1 AND 09 OF THE VOLTAGE SWING
Figure 25. System Clock MOS Input Voltage Levels for Timing Measurements
7-312
210783-003
82586
D.C. CHARACTERISTICS
TA = 0-70°C, Vee = 5V ± 10% CLK, TxD, TxC, RxD,
Signals have TTL levels (see Vll , VIH :' VOL, VOI;i)'
Axe have MOS levels (see VMll , VMIH , VMOl ' VMOH )' All other
Symbol
Parameter
Min.
Max.
Units
Vil
Input Low Voltage (TTL)
-0.5
+0.8
V
VIH
Input high Voltage (TTL)
2.0
Vee+0.5
V
VOL
Output Low Voltage (TTL)
0.45
V
IOl=2.5rnA
VOH
Output High Voltage (TTL)
.2.4
V
IOH=-400uA
VMil
VMIH
Input Low Voltage (MOS)
-0.5
0.6
Input High Voltage (MOS)
3.9
Vee+0.5
V
VMOl
Output Low Voltage (MOS)
0.45
V
IOl=2.5rnA
VMOH
Output High Voltage
V
IOH=-400uA
III
Input Leakage Current
±10
uA
o:;:,V'N-:;VCC
ILO
Output Leakage Current
±10
uA
0.45-:;Vour-:;Vcc
FC=1MHz
Vee-0.5
Test Conditions
V
CIN
Capacitance of Input Buffer
10
pF
COUT
Capacitance of Output Buffer
20
pF
FC=1 MHz
lee
Power Supply
450
rnA
TA = 0 deg. C
Figure 26. INT Output Timing
Figure 27. CA Input Timing
elK
T18 _
RESET
RD. WR. DEN. DT/R.
_
_
T47f"
------------_+,.___
w.Si
Figure 28. RESET Timing
7-313
210783-003
inter
82586
READY SIGNAL
PClK
'/
-
V
ARDY
T3
T2
L~
C
80186 OR
82285 OUTPUT
~
k
r;;-
-
82586
INPUT
"'--
V
""
Tn
--
/
f- T12
T13
SREADY
OR
-
READY
82586 INPUTS
VALID
T14
-
Figure 29. ARDY and SRDY Timings Relative to ClK
HOLDA
BHE ADO-AI2~
A16-A~3
SO.£!
DT/R RD WR
CPU MASTER
1~~~82~58~6~-M~A~ST~E!RPr:=~----
T30
Figure 30. HOlD/HlDA Timing Relative to ClK
7-314
210763-003
inter
82586
T2
T1
v--
veL
T4
1
.!!. r--.- ~
T1
~
ggL
T3
>--1\
~
~
T4
T4
§1)~
1 /
T33
1-+\T34
!!!
T29_
A16·A18 A20·A23
A 19/56
T3S-
T32-
~
T29 ....
1+ T38 i"'-T36
I-l
I
'AD
t:::::f,
r-'--
,,- --
~
AO·A15
ADO·AD15
T39
-- -
~
T9
T8
-{
lie
I;--
DATA IN
I
T41-
1-T43
T23
I-
-
T42
T40
.....:..
i'--
T44
I
DEN
I
1;1-
ALE
DT/R
I
S6
A19
~
'-1/
T22
I
.o-T24
I
Figure 31. Read Cycle Timing
7":315
210783-003
82586
T1
~
vel
~
1-
-
T6 -
I- -
T4
-
.m.
IJRE A16-A18 A20-A23
A19/58
;-L
'r-----"
'U'I
T33
f-17
Ijf--j\
ALE
T35-
Y-
-
r- ~
ADO-AD15
/
T29-
l-
~ T2!..j
)(~
~
~
-T31
~
T32-
I
-T36
....
I
~
-r39
~
T29-
56
T32 _
_T31
AO-A15
WA
T4
T34
A19
-
~
-
DATA OUT
~
-T30
-
T45
T23
T24-
,-
--
---
~
-
i-
-
T24
Flgure,32. Write Cycle Timing
INPUT TIMING REQUIREMENTS (8MHz)*
Symbol
T1
T2
T3
T4
T5
TB
T7
T8
T9
T10
T11
T12
T13
T14
T15
T1El
T17
T18
T19
T20
T21
Parameter
ClK cycle period
ClK low time at 1.5V
ClK low time at O.BV
ClK high time at 1.5V
ClK high time at 3.8V
ClK rise time
ClK fall time
Data in setup time
Data in hold time
Async ROY active setup time
Async ROY inactive setup time
Async ROY hold time
Synchronous ready/active setup
Synchronous ready hold time
HlOA setup time
HlOA hold time
Reset setup time
Reset hold time
CA pulse width
Min.
Max.
125
53
42.5
53
42.5
2000
1000
1000
15
15
20
10
20
35 '
15
35
0
20
10
20
10
1 T1
20
10
CA setup time
CA hold time
7-316
Comments
Note 1
Note 2
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
15
Note 3
Note 3
210783-003
inter
82586
OUTPUT TIMINGS (8 MHz)~
Symbol
Parameter
T22
DT/A valid delay
WA. DEN active delay
WA. DEN inactive delay
Int. active delay
T23
T24
T25
T26
T27
Int. inactive delay
Hold active delay
Hold inactive delay
Address valid delay
Address float delay
Data valid delay
Data hold Time
T28
T29
T30
T31
T32
T33
Min.
0
0
0
0
0
0
0
0
0
0
0
Max.
60
0
0
60
70
T35
T36
T37
0
0
T2-10
T38
Address valid to ALE low
T2-30
T39
Address hold to ALE inactive
T7-10
T40
T41
T42
0
0
2T1-50
T44
T45
T46
AD active delay
rID inactive delay
RDwidth
Address float to AD active
Ri5 inactive to Address active
WRwidth
Data hold after WR
T47
Control inactive after reset
T43
0
T1-40
2T1-40
T2-25
0,
• All units are in ns.
"CL on all outputs is 2G-200 pF unless otherwise specified.
65
85
Note 4
85
85
85
Note. 4
Note 4
Note 4
60
50
60
Status active delay
Status inactive delay
ALE active delay
ALE inactive delay
ALE width
T34
Comments
70
45
45
Note 5
Note 5
Note 5
95
70.
60
Note 6
SERIAL INTERFACE
A.C. TIMING CHARACTERISTICS
NOTE LIST:
1
2
3
4
5
6
1.0Vto 3.5V
3.5Vto 1.0V
to guarantee recognition at next clock
CL= 50pF
CL= 100 pF
Affects:
MIN MODE: RD, iNA, DT/R. DEN
MAX MODE: SO, S1 .
CLOCK SPECIFICATION
Applies for TxC. AxC
f min = 100KHz 10 MHz ±100 ppm
f max = 10 MHz ±1oo ppm
for Manchester. symmetry is needed:
,
T51. ;-52 =
7-317
~
±5%
210783'{)03
8258.6
A.C. CHARACTERISTICS
TRANSMIT AND RECEIVE TIMING PARAMETER SPECIFICATION' ..
Symbol
Parameter
Min.
Max.
1000
Comments
I
TRANSMIT CLOCK PARAMETERS
T48
fXc Cycle
100
T48
TxC Cycle
100
Notes 1, 2
Notes 1, 3
T49
TxC Rise Time
5
T50
TxC Fall Time
5
Note 1
T51
TxC High Time
44
1000
Note 1
T52
TxC Low Time
40
Note 1
Notes 1, 4
TRANSMIT DATA PARAMETERS
T53
TxD Rise Time
10
T54
TxD Fall Time
10
T55
TxD Transition - Transition
T56
T57
TxC Low to TxD Valid
40
Notes 1,3,5
'fxC Low.to TxD Transition
40
Notes 1, 2, 5
T58
TxC High to TxD Transition
40
Notes 1, 2, 5
T59
TxC Low to TxD High at the Transmission end
40
Notes 1, 5
45
Note 6
Notes 1, 5
Notes 1, 5
Notes 1,2,5
35
REQUEST TO SEND/CLEAR TO SEND PARAMETERS
T60
TxC Low to RTS Low. Time to Activate RTS
T61
CTS Valid to TxC Low. CTS Set-Up Time
45
Note 6
T62
TxC Low to CTS Inyalid. CTS Hold Time
20
Notes 6,7
T63
TxC.Low to RTS High. time to deactivate
FITS
45
Note 6
RECEIVE CLOCK PARAMETERS
T64
RxC Clock Cycle
T65
RxC Rise Time
5
Note 1
T66
T67
RxC Fall Time
RxC High Time
40
5
1000
T68
RxC Low Time
44
Note 1
Note 1.
Note 1
Notes 1, 3
100
RECEIVE DATA PARAMETERS
T69
RxD Setup Time
T70
T71
RxD Hold Time'
RxD Rise Time
T72
RxD Fall Time
Note 1
Note.1
30
"
30
10
Note 1
10
Note 1
• All units are in ns.
7-318
210783-003
inter.
82586
TRANSMIT AND RECEIVE TIMING PARAMETER SPECIFICATION* (cont'd.)
(symbol
Min.
Parameter
Mex.
Comments
I
CARRIER SENSE/COLLISION,DETECT PARAMETERS
T73
COT Valid to TxC Low Ext. Collision
T74
TXCLow to CDT Inactive. CDT Hold Time
T75
T76
Ci5T Low to Jamming Start
T77
T78
T79
TxC Low to CRS Inactive.CRS Hold Time
Qetect Setup Time
CRS Valid to
m
'i"XC Low Ext. Carrier Sense Setup time
30
Note 12
20
Note 12
30
Note 8
Note 12
20
Low to Jamming Start
Note 12
Note 9
Note 10
Jamming Period
R'ie==-.r---
(~~)
T76
_ J-r--T7-7 - - - . ; , t-
~,----'"'"
\
/
=~
T55
'5bOc=:J~~.r---~ =~~
TXD
(MANCHESTER)
Figure 35. Transmit and Control and Data Timing (cont.)
f - - - - - T64 - - - - - - - i
1 - - - T 6 8 -"--~
RoD'
Figure 36. RxD Timing Relative to RxC
~
___________
~_r-~----J
T80,
Figure 37.
eRS Timing Relative toRxC
7-321
210783:003
APPLICATION
NOTE
AP-66
January 1980
@INTELCORPORATION, 1980
7-322
APpLlCATIONS
IN)'RODUCTION
The Intel@ 8292 is a preprogrammed UPI™-4IA that
implements the Controller function of the IEEE Std
488-1978 (GPIB, HP-IB, IEC Bus, etc.). In order to
function the 8292 must be used with the 8291
Talker/Listener and suitable interface and transceiver logic such as a pair of Intel 8293s. In this
configuration the system has the potential to be a
complete GPIB Controller when driven by the
appropriate software. It has the following capabilities: System Controller, send IFC and Take.
Charge, send REN, Respond to SRQ, send Interface
messages, Receive Control, Pass Control, Parallel
Poll and Take Control Synchronously.
This application note will explain the 8292 only in
the system context of an 8292, 8291, two 8293s and
the driver software. If the reader wishes to learn
more about the UPI-4IA aspects of the 8292, Intel's
Application Note AP-41 describes the hardware
features and programming characteristics of the
device. Additional information on the 8291 may be
obtained in the data sheet. The 8293 is detailed in its
data sheet. Both chips will be covered here in the
details that relate to the GPIB controller.
The next section of this application note presents an
overview of the GPIB in a tutorial, but comprehensive nature. The knowledgable reader may wish
to skip this section; however, certain basic semantic
concepts introduced there will be used throughout
this note.
Additional sections cover the view of the 8292 from
the CPU's data bus, the' interaction of the 3 chip
types (8291, 8292, 8293), the 8292's software
protocol and the system level hardware/software
protocol. A brief description of interrupts and
DMA will be followed by an application example.
Appendix A contains the source code for the system
driver software.
Based on this experience, Hewlett-Packard began to
define a new interconnection scheme. They went
further than that, however, for they wanted to
specify the typical communication protocol for
systems of instruments. So in 1972, HewlettPackard came out with the first version of the bus
which since has been modified and standardized by a
committee of several manufacturers, coordinated
through the IEEE, to perfect what is now known as
the IEEE 488 Interface Bus (also known as the HPIB, the GPIB and the IEC bus). While this bus
specification may not be perfect, it is a good
compromise of the various desires and goals of
instrumentation and computer peripheral manufacturers to produce a common interconnection
mechanism. It fits most instrumentation systems in
use today and also fits very well the microcomputer
I/O bus requirements. The basic design objectives
for the GPIB were to:
1. Specify a system that is easy to use, but has all of
the terminology and the definitions related to
that system precisely spelled out so that everyone uses the same language when discussing the
GPIB.
2. Define all of the mechanical, electrical, and functional interface requirements of a ~ystem, yet not
define any of the device aspects (they are left up
to the instrument designer).
3. Permit a wide range of capabilities of instruments
and computer peripherals to use a system simultaneously and not degrade each other's performance. '
4. Allow different manufacturers' equipment to be
connected together and work together on the
same bus.
5. Defme a system that is good for limited distance interconnections.
6. Define a system with minimum restrictions on
performance of the devices.
7. Define a bus that allows asynchronous communication with a wide range of data rates.
8. Defme a low cost system that does not require
extensive and elaborate interface logic for the
.low cost instruments, yet provides higher capability for the higher cost instruments if desired.
9. Allow systems to exist that do not need a central
controller; that is, communication 'directly from
. one instrument to another is possible.
GPIB/IEEE 488 OVERVIEW
DESIGN OBJECTIVES
What is the IEEE 488 (GPIB)?
The experience of designing systems for a variety of
applications in the early 1970's caused HewlettPackard to define a standard intercommunication
mechanism which would allow them to easily assemble
instrumentation systems of varying degrees of complexity. 1n a typical situation each instrument designer designed his / her own interface from scratch.
Each one was inconsistent in ~erms of electrical
levels, pin-outs on a connector, and types of connectors. Every time they built a system they had to
invent. new cables and new documentation just to
specify the cabling and interconnection procedures.
Although the GPIB was originally designed for
instrumentation systems, it became obvious that
most of these systems would be controlled by a
calculator or computer. With this in mind several
modifications were made to the original proposal
before its final adoption as an international standard. Figure 1 lists the salient characteristics of the
7-323
APPLICATIONS
GPIB as both an instrumentation bus and as' a
computer I/O bus.
Data Rate
,
1 IV! bytes/s, max
250k DyteS/S, tvP
Multiple Devices
15 d~vices,max (electrical limit)
8 devices, tvP (interrupi: flexibility)
Bus Length
20'm', max
2 m/device, typ
Byte Oriented
a·bitcommands
a·bit data
Block Multiplexed
Optimum strategy on GPIB due to
setup overhead for commands
Interrupt Driven
Serial poll (slower devices)
Parallel poll (faster devices)
Direct Memory Access
One DMA facility at controller
serves all devices on bus
Asynchronous
One talker
}
.
Multiple listeners,
3-wlrehandshake
formance and allow utilization of m'ore of the bus
bandwidth.
Multiple Devices - Many microcomputer syStems
used as computers (not as components) service from
three to seven peripherals. With the GPIB, up to 8
devices can be handled easily by 1 controller; with
some slowdown in interrupt handling, up to 15
devices can work together. The limit of 8 is imposed
by the number of unique parallel poll responses
available; the limit of 15,1s set by the electrical drive
,characteristics of the bus. Logically, the IEEE 488
Standard is capable of accommodating more device
addresses (31 primary, each potentially with 31
secondaries).
Bus Length - Physically, the majority of microcomputer systems fit easily on a desk top or in a
standard 19" (48-cm) rack, eliminating the need for
extra long cables. The GPIB is designed typically to
have 2 m of length per device, which accommodates
most systems. A line printer might require greater
cable lengths, but this can be handled at the lower
speeds involved by using extra dummy terminations.
Byte Oriented - The 8-bit byte is almost universal
in I/O applications; even 16-bit anq 32-bit computers use byte transfers for most peripherals. The 8bit byte matcl).es the ASCII code for characters and
is an integral submultiple of most c~mputer word
sizes. The GPIB has an 8-bit wide data path that may
be used to transfer ASCII or binary data, as well as
the necessary status and control bytes.
I/O to I/O Transfers
Talker and listeners need not
include microcomputer/controller
Block Multiplexed - Many peripherals are block
oriented or are used in a block mode. Bytes are
transferred in a fixed or variable length group; then
then; is a wait before another group is sent to that
device, e.g., one sector ,of a floppy disc, one line on a
printer or tape punch, etc. The GPIB is, by nature, a
block multiplexed bus due to the overhead involved
in addressing various devices to talk and listen. This
overhead is less bothersome if it only occurs once for
a large number of data bytes (once per block). This
mode of operation matches the needs of microcomputers and most of their peripherals. Because of
block mUltiplexing, the bus works best with buffered
memory devices.
Figure 1. Major Characteristics of
~PIB as Microcompllter 110, Bus
The bus can be best unders100d by examining each
of these characteristics fI:om the viewpoint of a
general microcomputer I/O bus.
Data Rate - Most microcomputer systems utilize
peripherals of differing operational rates, such as
floppy discs at 31k or 62k bytes/s (single or double
density), ,tape' cassettes at 5k to 10k bytes / s, and
cartridge tapes at40k to 80k bytes / s. In general, the
only devices that nee~ high speed I/O are 0.5"(1.3cm) magnetic tapes and hard discs, operational at
30k to 781k ,bytes/s, respj::ctively, Certainly, the
250k-bytes / s datarate that can be easily achieved by
the IEEE 488 bus is sufficient for microcomputers
and their peripherals,' and is more than needed for
typical analog instruments that take only a few readings per second. The IM-bytefs maximum data rate
is not easily achieved on the GPIB and requires
speciaf attention to considerations beyond the scope
of this note. Although not required, data buffering
,in each device will improve the overall bus per-
Interrupt Driven - Many types ofinterrupt systems
exist, ranging from complex, fast, vectored/priority
networks to simple polling schemes. The main
tradeoff is usually cost versus speed of response. The
GPIB has two interrupt protocols to help span the
range df applications. The first is a single service
request (SRQ) line that' may be asserted by all
interrupting devices. The controller ,then polls all ,
devices to find out which wants service. The polling
mechanism is well defined and' can be easily
7-324
AFN-0138OA
APPLICATIONS
automated. For higher performance, the parallel
poll capability in the IEEE 488 allows up to eight
devices to be polled at once - each device is
assigned to .one bit of the data bus. This mechanism
provides fast recognition of an interrupting device.
A drawback is the frequent need for the controller to
explicitly conduct a parallel poll, since there is no
, equivalent of the SRQ line for this mode.
Direct Memory Access (DMA)- In many applications, no imediate processing of I/O data on a byteby-byte basis is needed or wanted. In fact,
programmed transfers slow down the data transfer'
rate unnecessarily in these cases, and higher speed
can be obtained using DMA. With the G,PIB, one
DMA facility at the controller serves all devices.
There is no need to incorporate complex logic in
each device.
Asynchronous Transfers - An asynchronous bus is
desirable so that each device can transfer at its own
rate. However, there is still a strong motivation to
buffer the data at each device when used in large
systems in order to speed up the aggregate data rate
on the bus by allowing each device to transfer at top
speed. The GPIB is asynchronous and uses a special
III"~
DEVICE A
ABLE TO
TALk, LISTEN.
AND
CONTROL
(e g. computer)
==
"'f
ABLE TO
DATA BUS
LISTEN
DAYA BYTE
TRANSFER
CONTROL
DEVICE C
ONLY ABLE
YO LISTEN
1=
SRQ - Service Request
This line is. like an
interrupt: it may be asserted by any device to request
the Controller to take ,some action. The Controller
must determine which device is asserting SRQ by
conducting a Serial Poll at its earliest convenience.
The device deasserts SRQ when polled.
[Fe - Interface Clear This signal is asserted only
by the System Controller in order to initialize all
device interfaces to a known state. After deasserting
IFC, the System Controller is the active controller of
the system.
REN - Remote Enable This signal is asserted
only by the System Controller. Its assertion does not
place devices into Remote Control mode; REN only
enables a device to go remote when addressed to
listen. When in Remote, a device should ignore its
front panel controls.
(e 9. signal
generator)
(
GENERAl.
INTERFACE
MANAGEMENT
DEVICE 0
ONLY ABLE
TO TALK
t==
leg counter)
--==} 0101
L---
The lines DlOl through DlO8 are used to transfer
addresses, control information and data. The
formats for addresses and control bytes are defined
by the IEEE 488 standard (see Appendix C). Data
formats are undefined and may be ASCII (with or
without parity) or binary. 0101' is the Least Significant Bit (note that this will correspond to bit 0
on most computers).
EOI- End or Identify This signal has two uses as
its name implies. A talker may assert EOI simultaneously with the last byte of data to indicate end of
data. The Controller may assert EOI along with
ATN to initiate a Parallel Poll. Although many
devices do not use Parallel Poll, all devices should
use EOI to end transfers (many currently available
ones do not).
t==
muttimeter)
GPIB SIGNAL LINES
Data Bus
A TN - Attention This signal is asserted by the
Controller to indicate that it is placing an address or
control byte on the Data Bus. ATN is de-asserted to
allow the assigned Talker to place status or data on
the Data Bus. The Controller regains control by reasserting ATN; this is normlj.lly done synchronously
with the handshake to avoid confusion between
control and data bytes.
-
(e g. digital
I/O To I/O Transfers - In practice, I/O to 110
transfers are seldom done due to the need for
processing data and changing formats or due to
mismatched data rates. However, the GPIB can
support this mode of operation where the microcomputer is neither the talker nor one of the
listeners.
Management Bus·
DEVICE B
TAlK AND
3-wire handshake that allows data transfers from
one talker to many listeners.
DATA
NPUT/OUTPUT)
"
OA.\!' (DATA VALID)
NAFD {NOT READY FOR DATA)
NDAC (NO T DATA ACCEPTED)
IFe (INTER FACE CLEAR)
ATN (ATTENTlON)
SRQ (SERVICE REQUEST)
REN (REM aTE ENABLE)
EOI (END- OR-IDENTIFY)
Figure 2. Interface Capabilities and Bus Structure
AF1W138OA
7-325
APPLICATIONS
bytes. The latter is called an extended Talker.
4. L - Listener (section 2.6) This function allows
a device to receive data when addressed to listen.
There can be extended Listeners (analogous to
extended Talkers above).
5. SR - Service Request (section 2.7) This function allows a device to request service (interrupt) the Controller. The SRQ line maybe
asserted asynchronously.
Transfer Bus
Not Ready For Data This handshake
line is asserted by a listener to indicate it is not yet
ready for the next data or control byte. Note that the
Controller will not see NRFD deasserted (Le., ready
for data) until all devices have deasserted NRFD.
NRFD -
N DA C - Not Data Accepted. This handshake
line is asserted by a Listener to indicate it has not yet
accepted the data or control byte on the DIO lines.
Note that the Controller will not see NDAC
deasserted (i.e., data accepted) until all devices have
deasserted NDAC.
6. RL ~ Remote Local (section 2.8) This function
allows a device to be operated in two modes:
Remote via the GPIB or Local via the manual
froht panel controls.
7. PP - Parallel Poll (section 2.9) This function
allows a device to present one bit of status to the
Controller-in-charge. The device need not be
addressed to talk and no handshake is required.
DA V - Data Valid
This handshake line is
asserted by the Talker to indicate that a data or
control byte has been placed on the DIO lines and
has had the minimum specified settling time.
I
-f..._ _ _---I~---(..._ _ _ _...I~-
010
HDAV
L-
H-,-,
_--I ,""'.______.Jn L._ _ __
NRFO L
H NDAC L _
"-'~_ _
' ..,
I
L.
I
L
Figure 3. GPIB Handshake Sequence
GPIB INTERFACE FUNCTIONS
There are ten (l0) interface functions specified by
the IEEE 488 standard. Not all devices will have all
functions and some may only have partial subsets.
The ten functions are summarized below with the
relevant section number from the IEEE document
given at the beginning of each paragraph. For
further information please see the IEEE standard.
1. SH - Source Handshake (section 2.3) This
function provides a device with the ability to
properly transfer data from a Talker to one or
more Listeners using the three handshake lines.
2. AH - Acceptor Handshake (section 2.4) This
function provides a device with the ability to
properly receive data from the Talker using the
three handshake lines. The AH function may
also delay the beginning (NRFD) or end
(NDAC) of any transfer.
3. T - Talker (section 2.5) This function allows a
device to send status and data bytes when addressed to talk. An address consists of one
(Primary) or two (Primary and Secondary)
8. DC - Device Clear (section 2.10) This function
allows a device to be cleared (initialized) by the
Controller. Note that there is a difference
between DC (device clear) and the IFC line
(interface clear).
9. DT - Device Trigger (section 2.11) This function allows a device to have its basic operation
started either individually or as part of a group.
This capability is often used to synchronize
several instruments.
10. C - Controller (section 2.12) This function
allows a device to send addresses" as well as
universal and addressed commands to other
devices. There may be more than one controller
on a system, but only one may be the controllerin-charge at anyone time.
At power-on time the controller that is handwired to
be the System Controller becomes the active
controller-in-charge. The System Controller has
several unique capabilities including the ability to
send Interface Clear (IFC -- clears all device
interfaces and returns control to the System
Controller) and to send Remote Enable (RENallows devices to respond to bus data once they are
addressed to listen). The System Controller may
optionally Pass Control to another controller, if the
system software has the capability to do so.
GPIBCONNECTOR
The GPIB connector is a standard 24-pin industrial
connector such as Cinch or Amphenol series 57
Micro-Ribbon. The IEEE standard specifies this
connector, as well as the signal connections and the
mounting hardware.
The cable has 16 signal lines and 8 ground lines. The
maximum length is 20 meters with no more than two
meters per device.
AF~13BOA
7-326
APPLICATIONS
i
GNO
~
DA TA - Transfer a block of data from device A to
devices B, C ...
I. Device A Primary (Talk) Address
Device A Secondary Address (if any)
2. Universal Unlisten
3. Device B Primary (Listen) Address
Device B Secondary Address (if any)
Device C Primary (Listen) Address
etc.
4. First Data Byte
Second Data Byte
SHIELD
ATN
SRQ
IFC
NOAC
NRFD
o'Av
REN
EOI
0108
0107
0106
0105
0104
0103
0102
0101
Last Data Byte (EO!)
5. Null
TRIGR - Trigger devices A, B, ... to take action
I. Un,iversal Unlisten
2. Device
Device
Device
Device
etc.
3. Group
4. Null
Figure 4. GPIB Connector
GPIB SIGNAL LEVELS
The GPIB signals are all TTL compatible, low true
signals. A signal is asserted (true) when its electrical
volotage is less than 0.5 volts and is deasserted (false)
when it is greater than 2.4 volts. Be careful not to
become confused with the two handshake signals,
NRFD and NDAC which are also low true (i.e.
> 0.5 volts implies the device is Not Ready For
Data).
A Primary (Listen) Address
A Secondary Address (if any)
B Primary (Listen) Address
B Secondary Address (if any)
Execute Trigger
PSCTL - Pass control to device A
I. Device A Primary (Talk) Address
Device A Secondary Address (if any)
2. Take Control
3. Null
CLEAR - Clear all devices
I. Device Clear
2. Null
The Intel 8293 G PIB transceiver chips ensure that all
relevant bus driver I receiver specifications are met.
Detailed bus electrical specifications may be found
in Section 3 of the IEEE Std 488-1978. The Standar~
is the ultimate reference for all GPIB questions.
REMAL - Remote Enable
I. Assert REN continuously
GOREM - Put devices A, B, ... into Remote
I. Assert REN continuously
2. Device A Primary (Listen) Address
Device A Secondary Address (if any)
Device B Primary (Listen) Address
Device B Secondary Address (if any)
etc.
3. Null
GPIB MESSAGE PROTOCOLS
The GPIB is a very flexible communications
medium and as such has many possible variations of
protocols. To bring some order to the situation, this
section will discuss a protocol similar to the one used
by Ziatech's ZT80 GPIB controller for Intel's
MUL TIBUS™ computers. The ZT80 is a complete
high-level interface processor that executes a set of
high level instructions that map directly into GPIB
actions. The sequences of commands, addresses and
data for these instructions provide a good exaIIlple
of how to use the GPIB (additional information is
available in the ZT80 Instruction Manual). The
'null' at the end of each instruction is for cosmetic
use to remove previous informatIon from the DIO
lines.
GQLOC - Put devices A, B,. ;. into Local
I. Device A Primary (Listen) Address
Device A Secondary Address (if any)
Device B Primary (Listen) Address
Device B Secondary Address (if any)
etc.
2. Go To Local
3. Null
LOCA~L
-
Reset all devices to Local
I. Stop asserting REN
7-327
AFN-01380A
APPLICATIONS
LLKA L ~ Prevent all devices from returning to
Local
I. Local Lock Out
2. Null
SPOLL - Conduct a serial poll of devices A, B, ...
I. Serial Poll Enable
2. Universal Unlisten
3. ZT 80 Primary (Listen) Address
ZT 80 Secondary Address
4. Device Primary (Talk) Address
Device Secondary Address (if any)
,5. Status byte from device
(). Go to Step 4 until all devices on list have been polled
7. Serial Poll Disable
8. Null
PPUAL - Unconfigure and disable Parallel Poll
response from all devices
I. Parallel Poll Unconfigure
2. Null
-Service Request, Parallel Poll, Device Clear, Device Trigger, Remote / Local functions
-Programmable data transfer rate
- Maskable interrupts
-On-chip primary and secondary addressrecognition
-1-8 MHz clock range
-16 registers (8 read, 8 write) for CPU interface
-DMA handshake provision
- Trigger output pin
'-On-chip EOS (End of Sequence) recognition
The pinouts and block diagram are shown in Fig. 5.
One of eight read registers is for data transfer to the
CPU; the other seven allow the microprocessor to
monitor the GPIB states and various bus and device
conditions. One of the eight write registers is for data
transfer from the CPU; the other seven control
various features of the 8291.
The 8291 interface functions will be software
configured in this application example to the
following subsets for use with the 8292 as a
controller that does not pass control. The 8291 is
used only to provide the handshake logic and to send
and receive data bytes. It is not acting as a normal
device in this mode, as it never sees A TN asserted.
ENAPP - Enable Parallel Poll response in devices
A, B, ...
I. Universal Unlisten
2. Device Primary (Listen) Address
Device Secondary Address (if any)
3. Parallel Poll Configure
4. Parallel PolI.Enable
~
5. Go to Step 2 until all devices on list have been
.configured.
6. Null
SHI
AH I
T3
LI
SRO
RLO
PPO
DCO
DTO
DISPP - Disable Parallel Poll response from devices A, B, ...
I. Universal Unlisten
2. Device A Primary (Listen) Address
Device A Secondary Address (if any)
Device B Primary (Listen) Address
Device B Secondary Address (if any)
etc.
3. Disable Parallel Poll
4. Null
Source Handshake
Acceptor. Handshake
Basic Talk-only
Basic Listen-only
No Service Requests
No Remote/Local
No Parallel Poll response
No Device Clear
No Device Trigger
If control is passed to another controller, the 8291
must be reconfigured to· act as a talker/listener with
the following subsets:
SHI
AHI
T5
L3
SRI
RL I
PP2
DC I
DTI '
CO
This Ap Note will detail how to implement a useful
subset of these controller instructions.
HARDWARE ASPECTS OF THE SYSTEM
8291 GPIB TALKER/LISTENER
The 8291 is a custom designed chip that implements
many of the non-controller GPIB functions. It provides hooks so the user's software can implement
additional features to complete the set. This chip is
discussed in detail in its data sheet. The major features are summarized here:
Source Handshake
Acceptor Handshake
Basic Talker and Serial Poll
Basic Listener
Service Requests
Remote / Local with Lockout
Preconfigured Parallel Poll
Device Clear
Device Trigger
Not a Controller
Most applications do not pass control and the controller is always' the system controller (see 8292
commands below).
-Designed to interface microprocessors to the GPIB
-Complete Source and Acceptor Handshake
-Complete Talker and Listener Functions with extended addressing
8292 GPIB CONTROLLER
The 8292 is a preprogrammed Intel® 8041A that
provides the additional functions necessary. to
7-328
AfN.0138OA
APPLICATIONS
PIN CONFIGURATION
Eoi
TRIG
DREQ
6Av'
0i0i
BLOCK DIAGRAM
18291
I
I
GPIB DATA
INTERFACE
I
FUNCTIONS
1/'-___..,...",--"'
SH
aPls CONTROL
TO NON-INVERTING
BUS TRANSCEIVERS
I
T/RCONTROL
i5i02
01
02
05
06
07
Vss
Flgur,e 5. 8291 Pin Configuration and Block Diagram
Interrupt Mask, Error· Mask, Event Counter or
Time Out.
implement a GPIB controller when used with an
8291 Talker/Listener. The 8041A is documented in
both a user's manual and in AP-41. The following
description will serve only as an outline to guide the
later discussion.
The 8292 acts as an intelligent slave processor to the
main system CPU. It contains a processor, memory,
I/O and is programmed to perform a variety of tasks
associated with GPIB controller operation. The onchip RAM is used to store information about the
state of the Controller function, as well as a variety
of local variables, the stack and certain user status
information. The timer/counter may be optionally
used for several time-out functions or for counting
data bytes transferred. The I/O ports provide the
GPIB control signals, as well as the ancillary lines
necessary to make the 8291, 2, 3 work together.
The 8292 is closely coupled to the main CPU
through three on-chip registers that may be
independently accessed by both the master and the
8292 (UPI-41 A). Figure 6 shows this Register
Interface. Also refer to Figure 12.
The status register is used to pass Interrupt Status
information to the master CPU (AO =1 on a read).
The DBBOUT register is used to pass one of five
other status words to the master based on the.last
command written into DBBIN. DBBO{)T is accessed
when AO =0 .on a Read. The five sta~us words are
Error Flag, Controller Status, GP.IB Status, Event
Counter Status or Time Out Status.
DBBIN receives either commands (AO = I on a
Write) or command related data (AO =(} on a write)
from the m;lster. These command related data are
CPU
CS
REGISTER
AD
RO
WR
0
0
0
0
0
1
1
0
0
1
1
READ OBaOUT
READ STATUS
1
1
X
0
0
WRITE CBBIN (DATA)
X
NO ACTION
0
1
x
WRITE DBBIN (COMMAND)
Figure 6. UPI-41A Registers
8293 GPIB TRANSCEIVERS
The 8293 is a multi-use HMOS chip that implements
the IEEE 488 bus transceivers and contains the
additional logic required to make the 8291 and 8292
work together. The two. option strapping pins are
used to internally configure the chip to perform the
specialized gating required for use with 8291 as a
device or with 8291/92 as a controller.
In this application example the two configurations
used are shown in Fig. 7a and 7b. The drivers are set
to open collector or three state mode as required and
the special logiC is' enabled as required in the two
modes.
7-329
AFN-Q1380A
A,PPL1CATIONS '
8291/2/3 CHIP SET
Figure 8 shows the four chips, interconnec~ed with
the special logic explicitly shown.
The 8291 acts only as the mechanism' to put
commands and ,addresses on the bus while the 8292
is asserting ATN. Tl).e 8291 is tricked into believing
that the ATN line is not asserted by the ATN2
output of the ATN transceiver lilnd is placed in Talkonly mode by the CPU. The 8291 then acts as though
it is sending data, when in reality it is sending
addresses and/ or commands. When the 8292
deasserts ATN, the CPU software must place the
8291 in Talk-only, Listen-only or Idle based on the
implicit knowledge of how the controller is going to
participate in the data transfer. In other words, the
8291 does not respond directly to addresses or
commands that it sends on the bus on behalf of the
Controller. The user software, through the use of
Listen-only or Talk-only, makes the 8291 behave as
, though it were ad,dressed.
..
Although it is not a common occurrence, the GPIB
specification allows the Controller to set up a, data
transfer. between two devices and not directly
participate in the exchange. The controller must
know when to go' active again and regain control.
The chip set accomplishes this through use of the
"Continuous Acceptor Handshake cycling mode"
and the ability to detect EO! or EOS at the end of the
transfer. See XFER in the Software Driver Outline
below.
Figure 78. 8293 Mode 2
.-----~~------~
.,
If the 8292 is not the .System Controller as
determined by the signal on its SYC pin, then it must
be able to respond to an IFC within 100 usec. This is
accomplished by the cross-coupled NORs in Fig. 7a
which deassert the 8293's internal version' of crc
(Not Controller-in-Charge). This condition is latched
until the 8292's firmware has received the IFCL
(interface' clear received latch) signal 'by testing the
IFCL input. The firmware then sets its signals to reflect the inactive condition and clears the 8293's latch.
In order for the 8292 to conduct a Parallel Poll the
8291 must be able to capture the PP response on the
DIO lines. The only way to d-xc--
8281
~
D
OPTA
V
~
ItA
\
i
TIC
TIC
, fi:
OPTA
OPTB
NDAC*
NRFD*
IFC*
REN*
IRQ*
.IRT~ ATN*
~R~
..
::J..Y>
EOI*
-
'81R
TIC
~
Figure 8. Talker/Lhltener/Cqntroller
7-331
AFN.()138OA
A9Pl1CATIONS
, ZT7488/18 GPIB CONTROLLER'
Ziatech's GPIB Controller, the ZT7488/ 18 will be
used as the controller hardware in this Application
Note. The controller consistS of an 8291, 8292, an 8
bit input port and TTL logic equivalent to that
shown in Figure 8. Figure 9 shows the card's block
diagram. The ZT7488/ 18 plugs into the STD bus, a
56 pin 8 bit microprocessor, oriented bus. An 8085
CPU card is also available on the STD bus and will
be used to execute the driver software.
The 8291 uses I/O Ports 60H to 67H and the 8292
uses I/O P.orts 68H and 69H:Thefive interrupt lines
are connected to a three-state buffer at I/O Port
, 6FH to facilitate polling operation. This is required
for the TCI, as it cannot be read internally in ~he
8292. The other three 8292 lines (SPI, IBF, OBF)
and the 8291 's INT line are also connected to
minimize the number of 1/ () reads necessary to poll
the devices.
NDAC is connected to COUNT on the 8292 to allow
byte counting on data transfers. The 'example driver
software will not use this feature, as the software is
simpler and faster if an internal 8085 register is used
for counting in software.
.....
ADDRESS
CI.OCK"
AD"
S"RESeT" ~---i._-.J!------'-t-+H
IOElCP*
IORQ-
. ..,
ADDREIS
......
ADDRES •
°IHDICATlI ACT!YE LOW LOGIC
Figure 9. ZT7488/18 GPIB Controller
PORT #
READ REGISTERS
I DI7 I DI. I pl. I DI. I DI3 I DI' I DI1 I DIO
"H
WRITE REGISTERS
I DO' I DD. t DDS I DO. I D03 I DO' I DO' I DOD I
OATA IN
DATA OUT
I CPT I APT I GET I END I DEC I ERR I eo 1., I,
61H
I CPT I APT I GET I END I DEC I ERR I 80 I 81
INTERRUPT fTATUS 1
INTERRUPT MASK 1
INTERRUPT STATUS 2
INTERRUPT MASK 2
I S8 I .A'I"I.o 1.5 I~' 1.3 I S2 I.; I
63H
I.s I,~ I S. I s. I 54 I S3 I S2 I51
SERIAL POLL MODE
SERIAL POLL STATUS
ADDRESS STATUS
ADDRESS MODE
I cml CPTOI Cp.,1 CPJ.I CPT31 CPT' I CPT, I CPTO I
85H
I CN..I CNT' I CNTOI COM.I COM31 COM,I COM,I COMol
COMMAND PASS THROUGH
I X I,QTO I DLO I AD53 A04"IAO~ol AD,.0IAD'·3
AUX MODE
... I ARS I DT I DL I AD51 AD. IAD31 AD'I AD' I
ADDRESS 0/1
ADDRESS 0
I x I Dn I DLI I AD511 AI)4.,I AD3-' I AD211 AD,·,I
87H
I EC' I EC. I EC. I EC. I EC3 I EC' I EC' I ECO
ADDRESS 1
EOS
, Figure 10: 8291 Regllters
7-332
AJ'N.4138OA
APPLICATIONS
.1
RD
r-~
~~
____
~unm==~
At..
________________________________________________-,
mil
~a~~----~----~------------~------~-----------'
rt: ::~o.
WR~~
o.~~
-
__-=mw~____+-~__________~____________________-+-,
.~
IO/I!,---' T.
REsET'-----l---+t++++--------,....-+-+---i
I~A:~====$!~~======:$:$~~=~~======~~----------------_L_L_!----_,
•
I~.::
D7-DO_
b]IJ~~
l
~ SROllt~~~~~~~~~~~;SRO
f=::
tq r I )'
I
RIT RD WR
J
......... D7.1)O
INTi-----II
':t'
'~~AO
DACKO I>----< DACK
HOLDHLDACLK-
DRDO I-;-
8257-5
-HRO
THLDA
"1:. RDY
CLK
z ..
I
~
11211
DREO
~ f--- RS2
CLK~
~
~~~
2142
~
~
~~N
;g~
COU~
ATN
EOI
DAY
8212
D7-DO'rCIC
EOl2
DAY
ATNI
ATNO
r---<
IFCL
r - CLTH
AO .- SYC CS
~
~=~ ,,+~~~ I-'r-HI-+f-Hf-t-I-H.,
I
2142
~
(
I
GPla
M5-M~
R~
RST RD WR
18FI
~H~
825f.5"
...
CC
__________________________________________________________________________
~
Figure 11. DMAllnterrupt GPIB Controller Block Diagram
The application example will not use, DMA or
interrupts; however, the Figure II block diagram
includes these features for completeness.
The 8257-5 DMA chip can be used to transfer data
between the RAM and the 8291 Talker/Listener. ,
This mode allows a faster data rate on the GPIB
and typically will depend on the 8291's EOS or EO!
detection to terminate the transfer. The 8259-5
interrupt controller is used to vector the five possible
interrupts for rapid software handling of the vario~s
conditions. .
8292 COMMAND DESCRIPTION
of each register. Note the two letter mnemonics to be
used in later discussions. The CPU must. not write
into the 8292 while IBF (Input Buffer Full) is a one,
as information will be lost.
DiRECT COMMANDS
Both the Interrupt. Mask (1M) and the Error Mask
(EM) register may be directly written with the LSB
of the address bus (AO) a "0". The firmware uses the
MSB of the data written to differentiate between 1M
and EM.
Load Interrupt Mask
This _command loads the Interrupt ~ask with .
D7-DO. Note that D7 must be a "I" and that
interrupts are enabled by a corresponding "I" bit in
this register. IFC interrupt cannot be masked off;
however, when the 8292 is, the. System Controller,
sending an ABORT command will not cause an IFC
interrupt.
This section discusses each command in detail and
relates them to a particular GPIB activity. Recall
that although the 8041A has only two read registers
and one write register, through the magic of on-chip
firmware the 8292 appears to have six read'registers
and five write registers. These are listed in Figure 12.
Please see the 8292 data sheet for detailed definitions
7-333
APPLICATIONS
READ FROM 8292
WRITE TO 8292
PORT #
INTERRUPT STATUS
I SYC I ERR I SRQI
07
X
EV
I
X
COMMAND FIELD
IIFCR I
IBF
X
I USER I
X
I
X
69H
X
GA
I
X
I TOUT31 TOUT21TOUT,I
SPI
6SH
I
I SYCSI
REN
I EOI I
X
I SYC I
SRO
6SH
0
I
0
IlJSERI
I
0
!
0
I
0
I
0
I
C
I
C
I
C
I
1m
0
I SRO I
DO
0
I
0
I TOUT41TOUT31TOUT,I
EVENT COUNTER'
IFC
I ANTI I SRO I
6SH
0
I
0
I
0
I
EVENT CqUNTER STATUS'
0
I
ERROR MASK
GPIB (BUS, STATUS'
REN I OAV
C
TCI I SYC I OBFI I
07
IFC
I
INTERRUPT MASK
CONTROLLER STATUS'
I CSBSI
OP
I
Do
ERROR FLAG'
I
OBF I '
0
0
I
0
I
0
I
'0
I
0
I
0
I
TIMEOUT'
I
0
0
0
0
I
6SH
0
I
0
I
0
I
D
I
D
I
0
D
1
I
TIME OUT STATUS'
I
DI
0
0
0
D
D
6SH
'Note' These registers are accessed by a speCial utPity command,
Figure 12, 8292 Registers
counter is incremented on a high to low transition of
the COUNT (Tl) input. In this application example
NDAC is connected to count. The counter is an 8 bit
register and therefore can count up to 256 bytes
(writing 0 to the EC implies a count of 256). Iflonger
blocks are desired, the main CPU must handle the
interrupts every 256 counts and carefully observe the
timing constraints.
Because the counter has a frequency range from 0 to
133 kHz when using a 6 MHz crystal, this feature
may not be usable with all devices on the GPIB. The
8291 can easily transfer data at rates up to 250 kHz
and even faster with some tuning of the system.
There is also a 500 ns minimum high time
r~quirement for COUNT Which can potentially be
violated by the 8291 in continuous acceptor
handshake mode (Le., TNDDVI + TDVND2-C =
350 + 350= 700 max). When cable delays are taken
into consideration, this problem will probably never
occur.
When the 8292 has completed the command, IBF
will become a "0" and will cause an interrupt if
masked on.
WTOUT -:- ,Write to Time Out Register
(Command = OEIH),
Tile byte written following this command will be
used to determine the number of increments used for
the time out functions. Because the register is 8 bits,
the max'imumtime olit is 256 time increments. This
Load Error Mask
This command loads the Error Mask with D7 - DO,
Note that D7 must be a zero and that interrupts are
enabled by a corresponding" I" bit in this register.
UTILITY COMMANDS
These commands are used to read or write the 8292
registers that are not directly accessible. All utility
commands are written with AO = I, D7 = D6 = D5 = I,
D4 = O. D3-DO specify the patticularcommand. For
writing into registers the general sequence is:
I. wait for IBF =0 in Interrupt Status R!!gister
2. write the appropriate command to the 8292,
3. write the desired register v~lue to the 8292 with
AO = 1 with no other writes intervening,
4. wait for indication 'of completion from 8292
(lBF =0).
For reading a register the general sequence is:
I. wait for IBF' ~ 0 in Interrupt Status Register
2. write the appropriate command to the 8292
3. wait for a TCI (Task Complete Interrupt)
4. Read the value of the accessed register from the
8292 with AO = O.
WEVC - Write to Event,Counter
(Command = OE2H)
The byte written following this command will be
loaded into the event counter register and event
counter status for byte counting. The internal
7-334
AFNO()138OA
APPLICATIONS
is probably enough for most instruments on the
GPIB but is not enough for a manually stepped
operation using a GPIB logic analyzer like Ziatech's
ZT488. Also, the 488 Standard does not set a lower
limit on how long a device may take to do each
action. Therefore, any use of a time out must be able
to be overridden (this is a good general design rule
for service and debugging considerations).
The time out function is implemented in the 8292'8
firmware and will not be an accurate time. The
counter counts backwards to zero from its initial
value. The function 1l)IlY be enabled/disabled by a
bit in the Error mask register. When the command is
complete IBF will be set to a "0" and will cause an
interrupt if masked on.
RBST - Read Bus Status Register
(Command = OE7H)
This command causes the firmware to read the
GPIB management lines, DA Vand the SYC pin and
place a copy in DBBOUT. TCI is set to "I" and will
cause an interrupt if masked on. The CPU may read
the value.
RERF - Read Error Flag Register
,(Command = OE4H)
This command transfers the content of the Error
Flag register to the DBBOUT register. The firmware
sets TCI = 1 and will cause an interrupt if masked on.
The CPU may then read the value.
This register is also placed in DB BOUT by an lACK
command if ERR remains set. TCI is set to "I" in
this case also.
lACK - Interrupt Acknowledge
(Command = Al A2 A3 A4 1 A5 1 1)
This command is used to acknowledge any combinations of the five' SPI interrupts (AI-A5): SYC,
ERR, SRQ, EV, and IFCR. Each bit AI-A5 is an
individual acnowledgement to the corresponding bit
in the Interrupt Status Register. The command
clears SPI but it will be set again if all of the pending
interrupts were not acknowledged.
If A2 (ERR) is "I", the Error Flag register is placed
inDBBOUT and TCI is set. The CPU may then read
the Error Flag without issuing an RERF command.
REVC - Read Event Counter Status
(Command =OE3H)
This command transfers the content of the Event
Counter to the DBBOUT register. The firmware
then sets TCI = I and will cause an interrupt if
masked on. The CPU may then read the value from
the 8292 with AO = O.
RINM - Read Interrupt Mask Register
(Command = OE5H)
This command transfers the content ofthe Interrupt
Mask register to the DBBOUT register. The
firmware sets TCI =1 and will cause an interrupt if
masked on. The CPU may then read the value.
RERM - Read Error Mask Register
(Command = OEAH)
This command transfers the content of the Error
Mask register to ,the DBBOUT register. The
firmware sets TCI = 1 and will cause an interrupt if
masked on. The CPU may then read the value.
OPERATION COMMANDS
The following diagram (Fig. 13) is an attempt to
show the interrelationships among the various 8292
Operation Commands. It is not meant to replace the
complete controller state diagram in the IEEE
Standard.
RCST - Read Controller Status Register
(Command =OE6H)
This command transfers the content of the Controller Status register to the DBBOUT registllr. Th~
firmware sets Tel = 1 and will cause an interrupt if
masked on. Tb.e CPU may then read the value.
RST - Reset (Command:: {)F2H)
This command has the same effect as an external
reset applied to the chip's pin #4. The 8292's actions
,
are:
1. All outputs go to their electrical high state. This
means that SPl, TCl, OBFI,' IBFI, CLTH will be
TRUE and 'all other GPIB signals will be FALSE.
2. The 8292's firmware will cause the above mentioned five signals to go FALSE after approximately 17.5 usec. (at 6 MHz).
3. These register~ wjll be cleare~: Interrupt Status,
Interrupt Mask, Error Mask, Time Out, Event
Counter, E,rror Flag.
'
4. If the 8292, is the, System Controller (SYC i~
TRUE), then lFC will be sent,TRUEforapproximately 100 usec and the Controller function will
end up in charge of the bus. If the 8292 is not the
RTOUT - Read Time Out Status Register
(Command = OE9H)
This command transfers the content of the Time Out
Status register to the DBBOUT register. The
firmware sets TCI = 1 and will cause an interrupt if
masked on. "Qte CPU may then read the value.
If this register is read while a time-out function is in
process, the value will be the time remaining before
time-out occurs. If it is read after a time-out, it will
~e zero. If it is read when no time-out is in process, it
will be the last value reached when the previous
timing occurred.
7-335
AFN-Ol38OA
APPLICATIONS
,-----------,
(RST + ABORT) • SYC
RST.
fie
I
I
I
SPCNI
I
IDLE
STANDBY
II
I
I
I
I
POLl.
~ ~.!!!:.L~N-CH~G!._
_
J
r - - -,- - - - - - - - - - - ,
I
RST.
--~OC
REMOTE
ABORT.SYC-~
I
II
I
L _ _ _ _ ..!Y!!!,~O.!!!R~~ _ _ _ _ --1
Figure 13. 8292 Command Flowchart
System Controller then it will end up in an Idle
state.
5. TCI will not be set.
RSTI.:..... Reset Interrupts (Command = OF3)
This command clears all pending interrupts and
error flags. The 8292 will stop waiting for actions to
occur (e.g., waiting for ATN to go FALSE in a
TCNTR command or waiting for the proper
handshake state in a TCSY command). TCI will not
be set.
ABORT - Abort all operations and Clear Interface
(Command = OF9H)
If the 8292 is not the System Controller this
command acts like a NOP and flags a USER
ERROR in the Error Flag Register. No TCI will
occur.
If the 8292 is the System Controller then IFC is set
. TRUE for approximately 100 j.Lsec and the 8292
becomes the Controller-in-Charge and asserts ATN.
TCI will be set, only if the 8292 was NOT the CIC.
STCNI - Start Counter Interrupts
(Command = OFEH)
Enables the EV Counter Interrupt. TCI will not be '
set Note that the counter must be enabled by a GSEC
command.
SPCNI - Stop Counter Interrupts
(Command = OFOH)
The 8292 will not generate an EV interrupt when the
counter reaches O. Note that the counter will
continue counting. TCI will not be set.
SREM - Set, Interface to Remote Control
(Command = OF8H)
If the 8292 is the System Controller, it will set REN
.
7-336
and ;rCI TRUK Otherwise it only sets the User
Error Flag.
SLOC - Set Interface to Local Mode
(Command = OF7H)
If the 8292 is the System Controller, it will set REN
FALSE and TCI TRUE. Otherwise, it only sets the
User Error Flag.
EXPP - Execute Parallel Poll
(Command = OF5H)
If not Controller-in-Charge, the 8292 will treat this
as a NOP and does not set TCI. If it is the Control-'
ler-in-Charge then it sets IDY (EOI & ATN) TRUE
and generates a local DA V pulse (that never reaches
the GPIB because of gates in the 8293). If the 8291 is
configured as a listener, it will capture the Parallel
Poll Response byte in its data register. TCI is not
generated, the CPU must detect the BI (Byte In)
from the 8291. The 8292 will be ready to accept
another command before the BI occurs; therefore
the 8291's BI serves as a task complete indication.
GTSB -
Go To Standby (Command = OF6H)
If the 8292 is not the Controller-in-Charge, it will
treat this command as a NOP and does not set TCI
TRUE. Otherwise, it goes to Controller Standby
State (CSBS), sets ATN FALSE and TCI TRUE.
This command is used as part of the Send, Receive,
Transfer and Serial Poll System commands (see
next section) to allow the addressed talker to send
datal status .
If the data transfer does not start within the specified
Time-Out, the 8292 sets TO UT2 TRUE in the Error
Flag Register and sets SPI (if enabled). The
controller continues waiting for a new command.
The CPU must decide to wait longer or to regain
control and take corrective action.
GSEC - Go to Standby and Enable Counting
(Command = OF4H)
This command does the same things as GTSB but
also initializes the event counter to the value previously stored in the Event Counter Register (default
value is 256) and enables the counter. One may wire
the count input to NDAC to count bytes. When the
counter reaches zero, it sets EV (and SPI if enabled)
in Interrupt Status and will set EV every 256 bytes
thereafter. Note that there' is a potential loss of
count information if the CPU does not respond to
the EV/SPIbefore another 256 bytes have been
transferred.' TCI will be set at the end of the
command. "
TCSY - Take Control Synchronously
(Command = OFDH)
If the 8292 is not in Standby, it treats this command
as a NOP and does not set TCI. Otherwise, it waits
APPLICATIONS
for the proper handshake state and sets ATN
TRUE. The 8292 will set TOUT3 if the handshake
never assumes the correct state and will remain in
this command until the handshake is proper or a
RSTI command is issued. If the 8292 successfully
takes control, it sets TCI TRUE.
This is the normal way to regain control at the end of
a Send, Receive, Transfer or Serial Poll System
Command. If TCSY is not successful, then the
controller must try TCAS (see warning below).
TCAS - Take Control Asynchronously
(Command = OFCH)
If the 8292 is not in Standby, it treats this command
as a NOP and does not set TCI. Otherwise, it
arbitrarily sets ATN TRUE and TCI TRUE. Note
that this action may cause devices on the bus to lose
a data byte or cause them to interpret a data byte as a
command byte. Both Actions can result in anomalous behavior. TCAS should be used only in
emergencies. If TCAS fails, then the System
Controller will have to issue an ABORT to clean
things up.
GIDL - Go to Idle (Command =OflH)
If the 8292 is not the Controller in Charge and
Active, then it treats this command as a NOP and
does not set TCI. Otherwise, it se.ts ATN FALSE,
becqmes Not Controller in Charge, and sets TCI
TRUE. This command is used as part of the Pass
Control System Command.
TCNTR - Take (Receive) Control
(Command = OFAH)
If the 8292 is not Idle,-then it treats this command as
a NOP and does not set TCI. Otherwise, it waits for
the current Controller-in-Charge to set ATN
FALSE. If this does not occur within the specified
Time Out, the 8292 sets TOUTl in the Error Flag
Register and sets SPI (if enabled). it will not proceed
until ATN goes false or it receives an RSTI
command. Note that the Controller in Charge must
previously have sent this controller (via the 8291's
command -'pass through register) a Pass Control
message. When ATN goes FALSE, the 8292 sets
CIC, ATN and TCI TRUE and becomes Active.
should not be changed after Power-on in any system
- it adds unnecessary complexity io the CPU's
software.
In order to use polling with the 8292 one must enable
TCI but not connect the pin to the CPU's interrupt
pin. TCI must be readable by some means. In this
application example it is connected to bit I port 6fH
on the ZT7488/ 18. In addition, the other three 8292
interrupt lines and the 8291 interrupt are also on that
port (SPI-Bit 2, ilWi'-Bit 4; OBFI-Bit 3, 8291 INTBit 0).
These drivers assume that only primary addresses
will be used on the GPIB. To use secondary
addresses, one must modify the test for valid
talk/listen addresses (range macro) to include
secondaries.
SOFTW ARE DRIVER OUTLINE
INITIALIZATION
8292 - Comes up in Controller Active State when
SYC is TRUE. The only initialization needed is to
enable the TCI, interrupt mas\<:. This is done by
writing OAOH to Port 68H.
8291 - Disable both the major and minor addresses
because the 8291 will never see lhe 8292's commands/addresses (refer to earlier hardware discussion). This is done by writing 60H and OEOR to
Port 66H.
INIT
INITIALIZATION
Talker/Listener
SEND
RECV
XFER
SEND DATA
RECEIVE DATA
TRANSFER DATA
Controller
TRIG
DCLR
SPOL
PPEN
PPDS
PPUN
PPOL
PCTL
RCTL
SRQD
GROUP EXECUTE TRIGGER
DEVICE CLEAR
SERIAL POLL
PARALLEL POLL ENABLE
PARALLEL POLL DISABLE
PARALLI:L ,POLL UNCONFIGURE
PARALLEL POLL
PASS CONTROL
RECEIVE CONTROL
SERVICE REQUESTED
System Controller
REME
LOCL
IFCL
REMOTE ENABLE
LOCAL
ABORT/INTERFACE CLEAR
Figure 14. Software Driver Routines
The set of system commands discussed below is
shown in Figure 14. These commands are implemented in software routines executed by the main
CPU.
The following section assumes that the Controller is
the System Controller and will not Pass Control.
This is a valid assumption. for 99+% of all
controllers. It also assumes that no DMA or
Interrupts will be used. SYC (System Control Input) ,
7-337
AFN-G138OA
APPLICATIONS
Set Address Mode to Talk-only by writing 80H to
Port MH.
Set internal counter to 3 M~z to match the clock
input coming from the 8085 by writing 23H to Port
65H. High speed mode for the handshakes will not
be used here even though the hardware uses tlireestate drivers.
No interrupts will be enabled now. Each routine will
enable the ones it needs for ease of polling operation.
THe INT bit may be read through Port 6FH. Clear
both interrupt mask registers.
Release the chip~ initialization state by writing 0 to
Port 65H.
INIT:
Enable-8292
Enable TCI
Enable-829I
Disable major address
Disable minor address
ton
Clock frequency
All interrupts off
Immediate execute pon
;Set up Int. pins for Port 6FH
;Task complete must be on
;In controller usage, the 8291
;Is set to talk only and/ or listen only
;Talk only. is our rest state
;3 MHz in this ap note example
;Releases 8291 from init. state
TALKER/LISTENER ROUTINES
Send Data
SENp <~OS>
always sends Universal Uhli~ten. If it is desired to
send data to the listeners previously addressed, one
could add a check for a null list and not send UNL.
Count must be 255 or less due to l1-n 8 bit register.
This .routine also ~lways uses an. EOS chara~tj:r to
te~~Inate the strIng output; thiS coul~ eaSily be
ehmInate~ and rely 0!1 the cou.nt. Items. In brackets
( ) are. optional a!1 d wIll not be Included In the actual
code In AppendiX A.
This routine assumes a non-null listener list in that it
SEND:
Output-to-829l MTA, UNL
Put EOS into 8291
While 20H :S listener :S 3EH
output-to-8291 listener
Increment listen Ust pointer .
Output-to-8292 GTSB
Enable-8291
Output EOI on EOS sent
If count < > 0 then
While not (end or count = 0)
(could check tout 2 hc;re)
Output-to-8291 data
Increment data buffer pointer
Decrement count
Output-to-8292 TCSY
(If tout3 then take control async)
Enable 8291
No output EOI on EOS sent
Return
;We will talk,lnobody listen
;End of string compare character
;GPIB listen addresses are
;"space" thru " >" ASCII
;Address all listeners
;8292 stops asserting ATN, go to standby
;Send EOI along with EOS character
;Wait for EOS or end of count
;Optionally check for stuck bus-tout 2
;Output all data, one byte at a'time
;8085 CREG will count for us
;8292 asserts ATN, take control sync.
;If unable to take control sync.
;Restore 8291 to standard condition
7-338
AfN.0138OA •
APPLICATIONS
CONTROLLER
•
LSTN
"I"
8291,8292
CTLR
'"
"
'
• -('>: •
'.~
,
".
;~
DEVICE
'; :',:
~
TALK
"Q"
,;
'"
~
.:
~
... .'"-
,..
DEVICE
Ef::l
TALK
,', ,"2" ,
"R"
DEVICE
LSTN
TALK
"."
"" ,',
...
"K"
DEVICE
ffi
TALK
"""
Figure 16. SEND to "1", ''2'', ">"; "ABeD"; EOS = "0"
Figure 15. Flowchart For Receive Ending CondlUonl
Receive Data
RECV
facilitate analysis by a GPIB logic analyzer like the
Ziatech ZT488. Otherwise, the bus would appear to
have no listener even though the 8291 will be
listening.
This system command is used to input data from a,
device. The data is typically a string of ASCII
characters.
This routine is the dual of SEND. It assumes a new
talker will be specified, a count of less than 257, and
an ,EOS character to terminate the input. EOI
received will also terminate the input. Figure 15
shows the flow chart for the RECV ending
conditions. My Listen Address (MLA) is sent to
keep the GPIB transactions totally regular to
Note that although the count may go to zero before
the transmi~sion ends, the talker will probably'be
left in a strange state and may have to be cleared by
the controller. The count ending of RECV is
therefore used as an error condition in most
situations.
.
I
7-339
AFN-l)l38OA
APPLfCATIO'N~
RECV:
(
Put EOS.into 8291
If 40H :5 ta~ker :5 5EH then
Output-to-8291 talker '
Increment talker pointer
Output-to-8291 UNL, MLA
Enable-829I
Holdoff on end
End on EOS received
lon, reset ton
Immediate execute pon
Output-to-8292 GTSB
While not (end or count =0 (or tout2»
Input-from-8291 data
Increment data buffer pointer
Decrement count
(If count = 0 then error)
Output-to-8292 TCSY
(If Tout3 then take control async.)
Enable-829I
No holdoff on end
No end on EOS received
ton, reset Ion
Finish handshake
Immediate execute pon
Return error-indicator
;End of string compare character
;GPIB talk addresses are
;"@" thru "~' ASCII
;Do this for consistency's sake
;Everyone except us stop listening
;Stop when EOS character is
;Detected by 829i
;Listen only (no talk)
;8292 stops asserting ATN, go to standby
;wait for EOS or EOI or end of count
;optionally check for stuck,bus-tout2
;input data, one byte at a time
;Use 8085 C register as counter
;Count should not occur before end
;8292 asserts ATN take control
;If unable to take control sync.
;Put 8291 back as needed for
;Controller activity and
;Clear hold off due to end
;Complete hold off due to end, if any
;Needed to reset)on .
CONTROLLER
COIITROLLER
Us1,82S2
8291,8292
ffi
"I"
eTlR
LSTN
TALK
"A"
"I"
TALK
•
"'A"
CTLR
~
,
"
OEVICE
"
lSTN
"1"
,>
"
TALK
"Q"
.
."
~
,', ,"',:,,:-
:"'.,
....
,<
LSTN
"2"
·'f'
~
"R"
.
V
OEVICE
~.:
y;'"
"
f ... )
:'~'
..
DEVICe
~
TALK
"0"
DEVICE
-:.' A.,
v
LsTNTI
:'2". >
TALK
"R"
OEVICE
LSTN
TALK
"K"
"."
DEVICE
LSTN
">"
TALK
"A"
Figure 18. XFER from "" ~ to "1", ''2?, ''+''; EOS
Figure 17. RECV from "R"; EOS = ODH,
M40
=ODH
AfN.013IIIA
APPLICATIONS
Transfer Data
XFER
This routine assumes a device list that has the ASCII
talker address as the first byte and the string (one or
more) of ASCII listener addresses following. The
EOS character or an EOI will cause the controller to
take control synchronously and thereby terminate
the transfer,
This system command is used to transfer data from a
talker to one or more listeners where the controller
does' not participate in the transfer of the ASCII
data. This is accomplished through the use of the
8291's continuous acceptor handshake mode while
in listen-only.
XFER:
;Send talk address and unlisten
Output-to-8291: Talker, UNL
While 20H :5 listen :5 3EH
Output-to-829I : Listener
Increment listen list pointer
Enable-829I
lon, no ton
Continuous AH mode
End on EOS received
Immediate execute PON
Put EOS into 8291
Output-to-8292: GTSB
;Send listen address
;Controller is pseudo listener
;Handshake but don't capture data
;Capture EOS as well as EOI
.
;Initialize the 8291
;Set up EOS character
;Go to standby
;8292 waits for EOS or EOI and then
Upon end (or tout2) then
Take control synchronously
Enable-8291
Finish handshake
Not continuous AH mode
Not END on EOS received
ton
,
Immediate execute pon
Return
;Regains control
;Go to Ready for Data
CONTROLLER
Group Execute Trigger
TRIG < Listener list>
This system command causes a 'group execute
trigger (GET) to be sent to all devices on the listener
TRIG:
Output-to-8291 UNL
While 20H :5 listener :5 3EH
Output-to-8291 Listener
Increment listen list. pointer
Output-to-8291 GET
Return
.
list. The intended use is to synchronize a number of.
instruments.
.;Everybody stop listening
;Check for valid listen address
;Address each listener
;Terminate on any non-valid character
;Issue group execute trigger
7-341
APPLICATIONS
, CONTROLLER
CONTROLLER
8291,8292
L~0N
~
8291,8292
TALK
"A"
LSTN
"I"
lEi
TALK
"An
DEVICE
, :.'P
"
"
DEVICE
r..
TALK
"A"
LSTN
"2"
@
TALK
"0"
DEVICE
!L~:,N
,I
TALK
"A"
DEVICE
TALK
"K"
LSTN
"+"
DEVICE
DEVICE
LSTN
TALK
">"
"/I"
)
Figure 19. TRIG "1", "+"
LSTN
">"
TALK
"II"
Figure 20. DCLR "1", "2"
Device Clear
DCLR < Listener list>
This system command causes a device clear (SDC)
to be sent to all devices on the listener list. Note
that this is not intended to clear the GPIB interface
of the device, but should clear the device-specific
logic.
DCLR:
Output-to-8291 UNL
While 20H :S Listener :S 3EH
Output-to-829l listener
Increment listen list pointer
Output-to-8291 SDC
Return
;Everybody stop listening
;Check for valid listen address
;Address each listener
;Terminate on !lny non-valid character
;Selective device clear
Serial Poll
SPOL < Talker list> < status buffer pointer>
This system command sequentially addresses the
designated devices' and ,receives one byte of status
from each. The bytes are stored in the buffer in the
same order as the devices appear on the talker list.
MLA is output for completeness.
7-342
APPLICATIONS
SPOL:
Output-to-8291 UNL, MLA, SPE
While 40H Stalker S SEH
Output~to-8291 talker
Increment talker list pointer
Enable-8291
lon, reset ton
Immediate execute' pon
Output-to-8292 GTSB
Wait for data in (BI)
Output-to-8292 TCSY
Input-from-8291 data
Increment! buffer pointer
Enable 8291
ton, reset Ion
Immediate execute pon
Output-to-8291 SPD
Return
;Unlisten, we listen, serial poll enable
;Only one byte of serial poll
;Status wanted from each talker
;Check for valid transfer
;Address each device to talk
;One at a' time
;Listen only to get status
;This resets ton
;Go to standby
;Serial poll status byte into 8291
;Take control synchronously
;Actually get data from 8291
;Resets Ion
;Send serial poll disable after all devices polled
CONTROLLER
CONTROLLER
829'_
TALK
"A"
LSTH
"r
121'_
~
TAUC
"A"
"
:
"
DEVICE
LaTN
, .... "
DEVICE
t-
v
T
"0"
LSTN
'TALK
"0"
","
DEVICE
DEVICE
.
LSTH
"2"
ffi
''2"
.'
DEVICE
tLSTN
LSTH
"."
DEVICE
LSTN
">"
Figure 21. SPOL "Q", "R", uK"," A"
Parallel Pol,l Enable
PPEN
This system command configures one or more
de¥ices to respond to Parallel Poll, assuming they
implement subset PPI. The configuration information is stored in a buffer with ilne byte per device'
in the same order as devices appear 'on the listener
TALK
"+"
:
"K"
DEVICE
t-
v
TAUC
"R")
LST"
">"
TALK
""..
FI9llre 22. PPEN ''2"; IPoP .... = 01118
list. The configuration byte has the format
XXXXIP3P2Pl as defmed by the IEEE Std. P3P2PI
indicates the bit # to be used for a response and I
indicates the assertion value. ~ee Sec. 2.9.3,3 of the
Std, for more details.
Af~'38OA
APPlJCATIONS
PPEN:
Output-to-8291 UNL
While 20H $ Listener $ 3EH
Output-to-8291 listener
Output-to-8291 fPC, (PPE or data)
Increment listener list pointer
Increment buffer pointer
Return
;Univenal unlisten
;Check for valid listener
;Stop old listener, address new
;SendparalleJ poll info
";Point to next listener
;One configuration byte per listener
Parallel Poll Disable
P P DS < listener list>
This system command disables one or more devices
from responding to a Parallel Poll by issuing a
Parallel Poll Disable (PPD). It does not deconfigure the devices.
PPDS:
;Universal Un listen
;Check for valid listener
;Address listener
Output-to-8291 UNL
While 20H $ Listener $ 3EH
Output-to-8291 listener
Increment listener list pointer
Output-to-8291 PPC, PPD
Return
;Disable PP on all listeners
CONTROLLER
CONTROLLER
8291.8292
8291.8292
TALK
"A"
LSTN
u,"
V:'.'
8
~'1" ..... ;..
DEVICE
"0"
<
y:
DEVICE
LSTN
"2"
v
\
TALK
~. , .
~~
TALK
"RIO
DEVICE
~
'. -;'9
'e'"
LSTN
TALK
"1"
"0"
DEVICE
~
'..-=-,.,
'.
"
..,...:.;
v
LSTN
TALK
"2"
"R"
~
>-,;
TALK
"K"
DEVICE
~
.'
;
(;,."
',''lI
...
LSTN
TALK
"+"
"K"
DEVICE
V
TALK
"""
LSTN
">"
FIgure 23. PPDS "1", "+", ">"
TALK
. "''
FIgure 24. PPUN
7-344
AF~I38OA
APPLICATIONS
Parallel Poll Unconfigure
PPUN
This system command deconfigures the Parallel Poll
response of all devices by issuing a Parallel Poll
Unconfigure message.
PPUN:
Outpui-to-8291 PPU
Return
;Unconfigure all parallel poll
Conduct a Parallel Poll
PPOL
This system command causes the controller to conduct a Parallel Poll on the GPIB for approximately
12.5 usec (at 6 MHz). Note that a parallel poll does
not use the handshake; therefore, to ensure that the
device knows whether or not its positive response
was observed by the controller, the CPU should
explicitly acknowledge each device by a devicedependent data string. Otherwise, the response bit
will still be set when the next Parallel Poll occurs.
This command returns one byte of status.
PPOL:
Enable-829I
Ion
, Immediate execute pon
Output-to-8292 EXPP
Upon BI
Input-from-8291 data
Enable-829I
ton
Immediate execute pon
Return Data (status byte)
;Listen only
;This resets ton
;Execute parallel poll
;When byte is input
;Read it
;Talk only
;This resets Ion
Pass Control
PCTL
This system command allows the controller to
relinquish active contlpl of the GPIB to another
controller. Normally some software protocol should
already have informed the controller to expect this,
and under what conditions to return controL The
8291 must be set up to become a normal device
and the CPU must handle all commands passed
through, otherwise control cannot be returned (see
Receive Control below). The controller will go idle.
PCTL:
If 40H ::; talker ::; 5EH then
if talker < > MTA then
output-to-8291 talker, TCT
Emible·829I
not ton, not Ion
Immediate execute pon
My device address, mode I
Undefined command pass through
(Parallel Poll Configuration)
Output-to-8292 GIDL
Return
;Cannot pass control to myself
;Take control message to talker
;Set up 8291 as normal device
;Reset ton and Ion
;Put device number in Register 6
;Required to receive control .
;Optional use of PP
;Put controller in idle
7-345
AFN'()138OA
APPLICATIONS
CONTROLLER
CONTROLLER
82~1,8292
8291.8292
~~
"'"
CTL
....i:
6
LSTN
"'"
"A"
Dro,
..
'"
,CT~R,
... ~~,.'t,"
TALK
"A"
DEVICE
DEVICE
LSTN
,:;'
TALK
"Q"
"I"
,
LSTN
TALK
"'"
~
(...
"Q"
\
DEVICE
DEVICE
0102
::..~
LSTN
TALK
"2"
"R"
0,103
LSTN
"2"
f
,~
DEVICE
LSTH
"R"
DEVICE
LITN
TALK
"K"
"+"
TALK
TALK
"K"
"+"
DEVICE
DEVICE
LSTN
TALK
">"
"f,."
LSTN
"#"
Figure 25. PPOL
LSTN
TALK
">"
"1\"
Figure 26. PCTL "C"
Receive Control
RCTL
This system command is used to get control back
from the current controller-in-charge if it has passed
control to this inactive controller. . Most GPIB
systems do not use more than one controller and
therefore would not need this routine.
To make passing and receiving control a· manageable event, the system designer should specify a
RCTL:
Upon CPT
If (command=TCT) then
If TA then
Enable-829I
Disable major device number
ton
Mask off interrupts
Immediate execute pon
eTLA
protocol whereby the controller-in-charge sends a
data message to the soon-to-be-active controller.
This message should give the current state of the
system, why control is being passed, what to do,
and when to pass control back. Most of these issues
are beyond the scope of this Ap Note.
;Wait for command pass through bit in 8291
;If command is take control and
;We are talker addressed
;Controller will use ton and Ion
;Talk only mode
7-346
AF~1311011
APPLICATIONS
Output-to-8292 TCNTR
Enable-829I
Valid command
Return valid
Else
Enable-829I
Invalid command
Else
Enable-829I
Invalid command
Return invalid
;Take (receive) control
;Release handshake
;Not talker addr. so TCT not for us
;Not TCT, so we don't care
SYSTEM
CONTROLLER
CONTROLLER
8291.8292
8291.8292
LSTN
"I"
ff
eTlR
,~
lSTN
"I"
DEVICE
LSTN
"1"
TALK
"0"
=)
TALK
"'"
"0"
DI'VICE
TALK
"R"
LSTN
TALK
"2"
UR"
TALK
UK"
LSTN
"+"
\ LSTN
TALK
,
"A"
LSTN
LSTN
"2"
.
l8TN
DEVICE
~
\'
TALK
"A"
ill0:
DI'VICE
t'<
~
DEVICE
DI'VICE
lSTN
"+"
TALK
"K"
"
DEVICE
~
v
'J
LSTN
"#"
rn
~CTLR:
."
TALK
"C"
"'
DEVICE
">"
TALK
"".
CONTROLLER
Figure 27. RCTL
Figure 28. REME
Service Request
SRQD
This system command is used to detect the occurrence of a Service Request on the GPIB. One or
more devices may assert SRQ simultaneously, and
the CPU would normally conduct a Serial Poll
after calling this routine to determine which devices
are SRQing.
7-347
AFN-0138OA
APPtlCATIONS
SRQD:
If SRQ then
Output-to-8292 IACK.SRQ
Return SRQ
Else return no SRQ
;Test 92 status bit
;Acknowledge it
SYSTEM CONTROLLER
Remote Enable
REME
This system command asserts the Remote Enable
line (REN) on the GPIB. The devices will not go
REME:
Output-to-8292 SREM
Return
remote until they are later addressed to listen by
some other system command.
;8292 asserts remote enable line
Local
LOCL
This system command deasserts the REN line on the
GPIB. The devices will go local immediately.
LOCL:
Output-to-8292 SLOC
Return
;8292 stops asserting remote enable
SYSTEM
CONTROLLER
SYSTEM
CONTROLLER
8291,8292
LSTH
,~
LC:.~J
LSTH
"I"
TALK
"A"
I~
Iii
TALK
NAt.
U
!!o
DEVICE
DEVICE
LSTN
"1"
,
"a"
LSTH
"1"
TALK
"A"
LSTH
"2"
TALK
DEVICE
LSTH
,
TALK
"K"
,,>"
TALK
"R"
DEVICE
LSTN
"+"
DEVICE
DEVICE
LSTH
"Q"
DEVICE
DEVICE
LSTN
"2"
TALK
TALK
"""
Figure 29. LOCL
LSTH
TALK
">"
"/I."
Figure 30. IFCL
7-348
AfN.0138OA
-
APPLICATIONS
Interface Clear/Abort
IFCL
This system command asserts the GPIB's Interface
Cle~r (IFC) line for at least 100 microseconds.
This causes all interface logic in all devices to go to
a known state. Note that the device itself mayor
IFCL:
Output-to-8292 ABORT
Return
may not be reset, too. Most instruments do totally
reset upon IFC. Some devices may require a DCLR
as well as an IFCL to be completely reset. The
(system) controller becomes Controller-in-Charge.
;8292 asserts Interface Clear
;For 100 microseconds
INTERRUPTS AND
DMA CONSIDERATIONS
In, etc. The only difficulty lies in integrating these
various interrupt sources and their matching
routines into the overall syst~m's interrupt structure.
This is highly situation-specific and is beyond the
scope of this Ap Npte.
The previous sections have discussed in detail how
to use the 8291, 8292, 8293 chip set as a GPIB
controller with the software operating in a polling
mode and using programmed transfer of the data.
This is the simplest mode of use, but it ties up the
microprocessor for the duration of a GPIB transaction. If system design constraints do not allow this,
then either Interrupts and/ or DMA may be used to
free up processor cycles.
The 8291 and 8292 provide sufficient interrupts that
one may return to do other work ~hile waiting for
such things as 8292 Task Completion, 8291 Next
Byte In, 8291 Last Byte Out, 8292 Service Request
MAIN CODE
The strategy to. follow is to replace each of the WAlT
routines (see Appendix A) with a return to the main
code and provide for the corresponding interrupt to
bring the control back to the next section of GPIB
code. For example WAITO (Wait for Byte Out of
8291) would be replaced by having the BO interrupt
enabled and storing the (return) address of the next
instruction in a known place. This co-routine
structure will then be activated by a BO interrupt.
Fig. 31 ·shows an example of the flow of control.
INTERRUPT CODE
GPIB SUBROUTINE
USER:
SEND:
ACTIVATE
SEND •
(WAIT 0)
=
'~INT:
___________
-~
GNaO?·
.
_
=
GPIBBO?-
-...
(WAITot
__
~INT:==
~
_=
===
(WAIT 0)
____INT:-
~
GPIBBO?---------------~
•
(WAIT T)
= ~INT:GPIB.BO~
=
•
. GPIB TCI?
=
ETC.
Figure 31. OPIB Interrupt & Co-Routine Flow of Control
7-349.
AfN.0138OA
'APPLICATI'ONS
tude. It will then tell the counter to measure the
frequency and Request Service (SRQ) when complete. The program will then read in the data. The
assembled source code will be found at the end of
Appendix A.
DMA is also usef).!l in relieving the processor if the
average length of a data buffer is long enough to
overcome the extra time used to set up a D MA chip.
This decision will also bea function of the data rate
of the instrument. The best strategy is to use the
DMA to handle only the data buffer transfers on
SEND and RECV and to do all the addressing and
control just as shown in the driver descriptions.
Another major reason for using a DMA chip is to
increase the data rate and therefore increase the
overall transaction rate. In this case the limiting
factor becomes the time used to do the addressing
and control of the G PIB using software like that in
Appendix A. The data transmission time becomes
, insignificant at DMA speeds unless extremely long
buffers are used.
Refer to Figure 11 for a typical D MA and interrupt
based design using the 8291, 8292, 8293. A system
like this can achieve a 250K byte 'transfer rate while
under DMA control. '
ZT7488/18
CONTROLLER
LSTN
"I"
CTLR
TALK
"A"
HP 5328A
COUNTER
LSTN
TALK
.""
APPLICATION EXAMPLE
"Q"
HP 3325A
FUNCTION
GENERATOR
This section will present the code required to operate
a typical GPIB instrument set up as shown in Fig.
32. The HP5328A universal counter' and the
HP3325 function ,generator are typic~l of many
GPIB devices; however, there are a wide 'variety of
software protocols to be found on the GPIB. The
Ziatech ZT488 GPIB analyzer is used to single step
the bus to facilitate debugging the system. It also
serves as a training/familiarization aid fpr newcomers to the bus.
LSTN
TALK
"R"
''2"
ZT488
GPIB ANALYZER
This example will set up the function generator to
output a specific waveform, frequency and ampli-
Figure 32. GPIB Example Configuration
SEND
LSTN: "2", COUNT: 15, EOS: ODH, DATA: "FUlFR37KHAM2VO (CRr'
;SETS UP FUNCTION GEN. TO 37 KHZ SINE, 2 VOLTS PP
;COUNT EQUAL TO # CHAR IN BUFFER
;EOS CHARACTER IS (CR) = ODH ::; CARRIAGE RETURN
SEND
LSTN: "1", COUNT: 6, EOS: "T"DATA: "RR4G7T'
;SETS UP COUNTER FOR P:INITIALIZE,F4: RREQ CflAN A
G7:0.I ' HZ RESOLUTION, T:TRIGGER AND SRQ
;COUNT IS EQUAL TO # CHAR
WAIT FOR SRQ
SPOL TALK: "Q", DATA: STATUS 1
;CLEARS THE SRO-IN THIS EXAMPLE ONLY FREQ CTR ASSERTS SRQ
RECV TALK: "Q", COUNT: 17, EOS: OAH,
DATA: "+
37000.0E+O" (CR) (LF)
;GETS 17 BYTES OF DATA FROM COUNTER
;COUNT IS EXACT BUFFE'R LENGTH
;DATA SHOWN IS TYPICAL HP5328A READING THAT WOULD BE RECEIVED
7-350
AFN-Ol38OA
APPLICATION.S
CONCLUSION
The ultimate reference for GPIB questions is the
IEEE Std 488, -1978 which is available from IEEE,
345 East 47th St., New York, NY, 10017. The ultimate reference for the 8292 is the source listing for it
(remember it's.a pre-programmed UPI-4IA) which
is available from INSITE, Intel Corp., 3065 Bowers
Ave., Santa Clara, CA 95051.
This Application Note has shown a structured way
to view the IEEE 488 bus.and has given typical code
sequences to make the InteI82~1, 8292, and 8293's
behave as a controller o£the GPIB. There are other
ways to use the chip set, but whatever solution is
chosen, it must be integrated into the overall system
.
software. \
APPENDIX A
ISIS-II 80aO/8085 MACKO ASSEMBLER, V3.0
GPIB CONTROLLER SUBROUTINES
LOC
OBJ
LINE
SOURCE STATEMEN'r
1 $TITLE('GPIB CONTROLLER SUBROUTINES')
2
3
GPIB CONTROLLER SUBROUTINES
4
5
6
7 ;
8
9
for Intel 8291, 8292 on ZT 7488/18
Bert Forbes, ziatech Corporation
2410 Broad Street
San Luis Obispo, CA, USA 93461
lI!J
11/
12
13
1000
oIiJ/i 0
01il63
011611
0061
0061
oorn
oOln
00111
0080
0062
01il64
""811
1104-0
110CO
0001
14
15
16
17
18
19
211
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
41'1
01'l1'Jl
01165
1'11123
42
.43
44
45
46
47
48
49
&
Equates
ORG
1001lJH
; For ZT7488/1B w/B085
;
PRT91
EQU
60H
;B291 Base Port'
;
DIN
DOUT
Reg to Data in & Data out
EQU
PRT91+0 ;91 Data in reg
EQU
PRT91+9 ;91 Data out req
,
INTI
INTM1
BO'"
BI'"
ENDMK
CPT
Req , 1 Interrupt 1 Constants
EQU
PRT91+1 ;INT Reg 1
EQU
PRT91+1 ;INT "'ask Reg. 1
EQU
02
;91 BO INTRP Mask
EQU
01
;91 BI INTRP Mask
l0H
;91 END INTRP Mask
EQU
BgH
;91 command pass thru int hit
EQU
;
INT2
Reg .2 Interrupt 2
EQU
PRT9l+2
;
Reg 14
EOU
EQU
EQU
EQU
EQU
ADRMD
TON
LON
TLON
MODEl
Add~ess
PRT91+4
BOH
41'1H
·9CIlH
91
Mode Constants
; 91 adilress mode reg ister t
)
;91 talk only mode & not listen only
/91 listen only & not ton
;91 talk & listen only
;mode 1 addressing for device
ADRST
EOIST
TA
LA
Reg '4
EQU
EQU
EQU
EQU
(ReadY Addre·ss Status Reqister
·PRT91+4 ; reg i4
21!H
;
AUXMD
CLKRT
Reg .5
EQU
EQU
(Write) Auxil1ary Mode Register
PRT91+5 ;91 auxilIary mode reqister •
23H
;91 3 Mhz clock input
41 ;
01164
111120
0111'12
General Defi·nitions
8291 Control Values
2
1
; 11 stener active
7-351
--
APPLICATIONS
0003
0006
\l1l81l
11001
01102
1111103
1I1l04
1l1l1l8
01111F
011117
110AII
50
51
52
53
54
55
56
57
58
59
611
FNHSK
SDEOI
AXRA
HOHSK
HOEND
CAHCY
EDEOS
EOIS
VSCMD
NVCMD
AXRB
CPTEN
EQU
EQU
EQU
EQU
. EQU
EQU
EQU
EQU·
EQU
EQU
EOU
EQU
113
;91 fininsh handshake command
;91 send EOI with next byte
;91 aux. reg A pattern
; 91 hold off hannshake on all bytes
;91 hold off handshake on end
;91 continuous AH cycling
;91 end .on EOS received
; 91 output EOI on EOS sent
;91 valid command pass through
;91 invalid command pass through
;Aux. reg. B pattern
;command pass thru enable
IiJI'i
83H
1.
2
3
4
8
IIFH
117H
0AI!JH
0lH
00!!!
~l
11065
63 ;
'i4 CPTRG
65
Reg .5
EQU
(Read)
PRT91+S
66
Reg 'I'i
EQU
EQU
EQU
Address 11/1 reg. constants
PRT91+1i
60H
;Disable major talker & listener
IIEIlH
;Disable minor talker & listener
Reg t7
EQU
EOS
Character Register
PRT91+7
8292
CONTROL VALUES
EQU
PRT91+8 ;8292 Base Port. (CS7)
EQU
EQU
PRT92+1!J ;92 INTRP Mask
0AI!JH
;TCI
EQU
EQU
EQU
EOU
EQU
EQU
PRT92+1!J
I!Jl
02
1!J4
PRT92 +1'1
PRT92+0
EQU
PRT92+1 ;92 Command Register
INTST
EVBIT
IBFBT
SRQBT
EQU
EOU
E:QU
EQU
PRT92+1
10H
112
211H
;92 Interrupt Status Reg
;Event Counter Bit
;Input Buffer Full Bit
;Seq bit
ERFLG
CLRST
BUSST
EVCST
TOST
EQU
EQU
EQU
EQU
EQU
PRT92+0
PRT92+11
PRT92+0
PRT92+0
PRT92+1!J
;92
;92
;92
;92
;92
8292
OPERATION COMMANDS
EOU
EOU
EOU
EOU
EOU
EQU
EOU
EOU
EQU
EQU
EQU
EQU
EQU
EQU
I!JFfilH
I!JFIH
IIF2H
IIF3H
IIF4H
filFSH
IIF6H'
IIF7H
0F8H.
IIF9H
0FAH
0:FCH
0FDH
IIFEH
~2
0066
90611
110E0
0067
,
67 ADRIH
68 D'rDLl
69 DTDL2
70
71;
72 EOSR
73
74
75
76
77
0068
11068
1101'.0
11068
0301
01i"12
11094
1I1l68
0068
11069
0069
110111
II I!J 92
91121l
11068
11068
11068
0068
01168
00FIl
IIIIF!
IlI!JF2
09F3
III!JF4
IIIIF5
00F6
IIBn
00F8
IHIF9
00FA
00FC
0liJFD
oliFE
78
79
80
81
82
83
84
85
86
87
88
89
911
91
92
93
94
95
96
97
98
99
Hl0
Hll
1112
1113
104
105
106
Hl7
108
1119
119
III
112
113
114
115
116
117
118
119
1211
121
122
;
PRT92
;
INTMR
INTM
;
ERRM
TOUT 1
TOUT2
TOUT3
EVREG
TOREG
,
CMD92
,
,
;
SPCNI
GIDL
RSET
RSTI
GSEC
EXPP
GTSB
SLOC
SREM
ABORT
TCN'rR
TCASY
TCSY
STCNI
;92
;92
; 92
;92
;92
;92
R~g
Error Mask Reg
Time Out for Pass Control
Time Out. fo r Standby
Time Out for Take Control Sync
Event Counter Pseurlo Reg
Time Out Pseudo Reg
Error Flag Pseurlo Reg
Controller Status Pseudo Reg
GPIB (Bus) Status Pseudo Reg
Event Counter Status Pseudo Reg
Time Out &tatus Pseudo Reg
;Stop Counter Interrupts
;Go to idle
;Reset
;Reset Interrupts
;Goto standby, enable counting
;Execute parallel poll
;Goto standby
;Set local mode
;Set interface to remote
;Abort all operation, clear interface
;Take control (Receive control)
;Take control asyncronously
;Take control syncronously
;Start counter interrupts
7-352
AFN-Ol38OA
APPLICATIONS
IHIE 1
1l1lli!2
II1lE3
1l0E4
IlllE5
IlllE6
II11E7
IlllE9
Il0EA
III III liB
123
124
125
126
127
128
129
1311
131
132
133
8292
UTILITY COMMANDS
EQU
0ElH
IilE2H
0E3H
I!JE4H
IlESH
IilE6H
IlE7H
IlE9H
IIlEAH
IIlBH
;
WOUT
WEVC
REVC
RERF
RINM
RCST
RBST
RTOUT
134 RERM
135 lACK
136
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
;Wr!te to timeout reg
;Write to event counter
;Read event counter status
;Read error flag reg
;Read 'interrupt mask reg
;Read controller status reg
;Read GPIB Bus status reg
;Read timeout status reg
;Read error mask reg
;Interrupt Acknowledge
137
006F
0002
1l1"'4
IHI1l8
1l011l
1l01iJ1
01101
0041
1l1l21
1l1l3F
31108
00114
1l1l18
0019
11005
0070
0060
0015
0009
138
139
140
141 ;
142 PRTF
143 TCIF
144 SPIF
145 OBFF
146 IBFF
147 BOF
148
149
150 ,
151 MDA
152 MTA
153 MLA
154 UNL
155 GET
156 SDC
157 SPE
158 SPD
159 PPC
160 PPD
161 PPE
162 PPU
163 'rCT
161
PORT F BIT ASSIGNMENTS
EQU
EQU
EQU
EQU
EQU
EQU
GPIB
PRT91+IlFH
;ZT748R port 6F for interrupts
;Task complete interrupt
1l4H
;Special interrupt
088
;92 Output (to CPU) Buffer full
11lH
,;92 Input (from CPU) Buffer empty
01H
;91 Int line (BO in this case)
III 28
~ESSAG~S
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
(COMMANDS)
;My device address is 1
;My talk address is 1 ("A")
;My listen address is 1 ("!")
;Universa1 unlisten
;Group Execute Trigqer
;Device Clear'
)Serial poll enable
;Serial poll 'disable
;Parallel poll configure
;Paral1el poll disable
;Paral1el poll disable
;Parallel poll unconfigured
;Take,contro1 (pass control)
1
MDA+408
MDA+20H
3FH
08
048
18H
198
05
708
60H
158
139
MACRO DEFINI'rIONS
lfiS
166
167
168 ,
169 SETF
170
171
172 ;
173 WAITO
174
175 WAITL:
176
177
178
179
180
185
189
. ;Sets flags on A reqister
A
END~
I~ACRO
LOCAL
IN
ANI
JZ
ENDM
WAITL
I I'lT 1
BOM
WAITL
MACRO
LOCAL
IN
MOV
ANI
JZ
EN,DM
WAITL
INTI
B,A
BIM
WAITL
MACRO
LOCAL
IN
ANI
JNZ
ENDM
WAITL
PRTF
TCIF
WAITL
;Wait for last 91 byte to be done
;Get Inti status
;Check for byte out
;If not, try again
;until it is
,
181 WAITI
182
183 WAITL:
184
186
187
188
MACRO
ORA
~AITX
190
191 WAITL:
192
193
194
195
7-353
;Wait for 91 byte to be input
;Get II'lTl status
;Save status in B
;Check for byte in
;If no~, just try again
;unt;il it is
;Wait for 92's TCI to go false
AFN.Q138OA
APPL~CATIONS
196
197
198
199
21'11l
2111
2"2
2113
2114
2115
2116
2117
2118
2119
218
211
212
213
214
215
216
217
218
219
221l
221
222
223
224
225
226
227
228
229
231l
231
232
233
234
235
236
WAITT
WAITL:
.lZ
3EAI'I
0368
3E611
0366
111 iii 8 lEU
l"IiIA
lllllC
lIIIlE
HUll
11112
0361)
3E80
0364
3E23
03155
11114 AF
lll15
11117
lll19
101B
0361
0362
0355
C9
WAITL
PRTF
TCIF
WAITL
,Get task complete int,etc.
;Mask it
;Wait for task to be complete
ENDM
RANGE
MACRO
MOV
CPI
.lM
CPI
.lP
!
LOWER,UPPER,LABEL
;Checks for value in range
;branches to label if not
;in range. Falls through if
flower <= ( (M) (L) ) <= upper.
;Get next byte.
'
A,M
LOWER
LABEL
UPPER+l
LABEL
ENDM
;
CLRA
MACRO
XRA
ENDM
A
;A XOR A -Il
All of the following routines have these common
assumptions about the state of the 8291 & 8292 upon entry
to the routine a.nd will exit the routine in an identical state.
,
8291:
BO is or has been set,
All interrupts are masked off
TON mode, not LA
No holdoffs in effect or enabled
No holdoffs waiting for finish command
8292:
ATN asserted (active controller)
not'e: Rc'rL is an exception--- i·t expects
to not be active controller
Any previous task is complete & 92 is
ready to receive next command.
Pointer registers (DE,HL) end one
beyond last legal entry
;
8"85:
,•• _._._._---_._ ••• _._ •• _._------.-._ •. -_.-.-_ ••• _--.-**
237 ;
l001i1
1002
1004
l01i16
"'ACRO
LOCAL
IN
ANI
238
239
241l
241
INITIALIZATioN ROUTINE
242 ,
243 ; INPu'rs:
None
244 ; ou'rpUTS:
None
245 ;CALLS:
None
246 ; DESTROYS,:
A,F
247 ;
MVI
A,INTM IEnable TCI
248 INIT:
249
ou'r
INT\'IR
,Output to 92's intr. mask reg
MVI
A,DTDLl ;Disable major talker/listener
250
251
OUT
ADRlll
252
A,DTDL2 ,Disable minor talker/listener
MVI
253
ou'r
ADRlll
254
..VI
A,TON
;T~lk only mode
255
ou'r
ADRMD
25<;
MVI
A,CLKRT ;3 MHZ for delay timer
257
ou'r
AUX"ID
258
CLRA
259+
XRA
A
;A XOR A =fiI
261l
IN,Tl
ou'r
261
INT2
;Disable ali 91 mask bits
ou'r
262
OUT
;Immediate,execute PON
AUX"'D
263
RET
264
265 *****.****************.******************************
266
267
SEND ROU'UNE
268
269
7-354
AFJPLlCATIONS
270
271
272
273
274
275
276
277
10lC 3E4l
10lE DJli0
1020
1922
1024
1027
1029
1"128
102C
Hl2E
102F
1031
1034
1036
1039
10313
1030
1040
1041
1043
1~44
0861
E602
CA211l0
3E3F
0360
78
0357
7E
FE20
FA4710
FE3F
F24711l
01361
E6C!J2
CA39Ul
7E
0360
23
C32EHl
11147 DBlil
1049 E602
10413 CA4710
H!4E
1050
U52
1'154
3EF6
0369
3E88
0365
H15'i DB6F
1058 E602
IIl5A C25'il!l
1050 DB6F
105~' E602
U6l CA5Dll!
278
279
280
281 ;
282 SEND:
283
284
285+??00U:
286+
287+
288
289
290
291
292
293 -SE>lOl:
294+
295+
296+
297+
298+
299+
300+
301+
302+
303+
1065 B7
lI'J65 CA8810
HI69 1/\
lIiJ5A D3lie
106C 138
MVI
OU'f
WAITO
IN
ANI
A,MTA
OOUT
JZ
n00(oll
MVI
OU'f
MOV
ou'r
RANGE
MOV
CPI
JM
CPI
JP
'~AITO
305+??0\102:
306+
307+
308
309
310
IN
ANI
311
312
313 SEND2:
314+??IHH!3 :
315+
316+
317
318
319
320
321
322
323
324+??0004 :
325+
326+
327
328+??0005:
329+
330+
331
333 ;
334
335
336+
337
338 SEND3:
339
340
341
342
HL listener list pointer
DE data buffer pointer
C count-- C!J will ca~e no ~ata to be sent
bEDS character-- software detected
none
OUTPUTS:
CALLS:
DESTROYS:
304
332 ;
lI'J64 79
INPU'fS:
JZ
MOV
ou'r
INX
J"IP
WAITO
IN
ANI
JZ
MVI
OUT
MVI
OUT
WAITX
IN
ANI
JNZ
WAITT
IN
ANI
JZ
none
A, C, DE, HL, F
; Send M'fA to turn
;previous talker
0
ff any
INTI
BOM
;Get IntI status
;Check for byte out
;If not, try again
A,UNL
;Sen~ universal unlisten
Ito stop previous listeners
OOUT
;Get EOS character
A,B
EOSR
;Output it to 8291
;while listener •••••
20H,3EH,SEND2
;Check next listen address
;Checks for value in ranqe
;branches to label if not
lin range. Falls through if
; lower <= ( (H) (L) ) <= upper.
;Get next byte.
A,M
20H.
SEND2
3EH+l
SEND2
;Wait for previous listener sent
INTI
;Get IntI status
BOM
;Check for byte out
7100112 ;If not, try again
A,M
;Get this listener
DOU'f
;Output to GPIB
H
;Incre~ent listener list pointer
SENDI
;Loop till non-valid listener
;Enable 91 en~inq conditions
;Wait for Istn addr accepted
;Get IntI status
INTI
;Check for byte out
BOM
1711003 ;If not, try again
;WAITO required for early versions
;of 8292 to avoid GTSB before DAC
A,GTSB ;Goto stan~by
CMD92
;
A, AXRA+EOIS
;Sen~ EOI with EOS character
AUXMD
;Wait for TCI to go false
PRTF
TCIF
??1I~(l4
PRTF
TCIF
niHlll5
;Wait for TCI on Giss
;Get task complete int,etc.
;Mask it
;wait for task to be complete
delete next 3 instructions to make count of 0=25fi
MOV
SETF
ORA.
A,C
;Get count
; Set flaqs
A
JZ
SENDI;
LDAX
OUT
C"1P
D
DOU'f
B
;If count=0, send no data
;Get data byte
;Output to GPIB
;Test EOS ••• this is faster
;arid ~ses less code than usinq
;9l's END or EOI bits
7-355
~138OA
11'11;0 CA7F10
U70 DB61
11172 E6tl2
U74 CA7010
1Il77 13
1Il78 00
1079
107C
U7F
11l8"
C26911l
C388l0
13
00
1081 0861
U83 E602
1085 CA8111'1
1088 3E~'D
U8A 031;9
1Il8C 3E81'1
108B D365
1,1l91l DB6F
1092 EI;02
1094 C29~10
11197
1099
Hl9B
109E
DB6F
E602
CA971fil
C9
343
344 SEND4:
345+110IHl6:
34/;+
3-4 7+
,~
348
349
351l
351
352 SEND5:
353
354
355+11110417:
356+
357+
35H
359 SEND';:
36"
361
31';2
3!;3
3';4+??0008:
'3<;5+
31;<;+
31;7
3'68+??0009:
369+
370+'
'371
372
11l9F 78
10M' 0367
101'.2 7E
, 101'.3 FE41l
10A5 FA3911
IM8 F E5F
10M F239il
IliAD 03611
l0AF 23
lllB0
HJB2
1"B4
l0B7
l0B9
DB!;l
E'i02
CABIlH!
3E3F
031;0
10B8 DB!;l
l08D E6"2 \
IIlBF CABBlIl
JZ
WAlTa
IN
ANI
JZ
INX
OCR
JNZ
JMP
INX
DCR
WAlTa
~
SENDS
;If char
INTI
;Get IntI status
;C~eck for byte out,
;If n~t, try again
;Increment buffer pointer
;Decrement count
;If count ( > 0, go send
;Else go finiSh
; fa r consi stency
'so.,
??091'l1i
D
C
SEND3
SEND6
D
C
;
.
EOS , go finish
.
';'fhis ensures' that the stahliard entry
;Get Int! status
;Check for byte out
;If not, try a1ain
;assumptions for the next subroutine are met
MVI
A,TCSY ;Take control syncronously
CMD92
ou'r
, A,AXRA ;Reset send EOI on EOS
MVI
OUT
AUXMD
WAITX
;Wait for TCI false,
IN
PRTF
1'.1111
TCIF·
JNZ
110tl1'l8
'WAIT'r
;Wait for TCI
IN
PRTF
;Get task complete int,etc.
ANI
;Mask it
TCIF
JZ
110009 ;Wait for task to ~e complete
RET
IN
ANI
JZ
INTI
SaM
??11"'07
;**************.** •• ***.***** ••• **.***.~.**.******~*** **.*************
373
RECEIVE ROU'rINE
374
375
376 ,
377 ;INPU'f:
HL talker pointer
,DE data buffer pointer
378
C count (ma'x' bllffer size) 0 implies 251;
379
380 ;
B EOS ch II go back' wait
451
MVI
B,4I1H
,Else set error indicator
452
3MP
RECV5
,And go take control
453
454 RECV2: MOV
A,B'
,Retreive status
455 RECV3: ANI
BIM
,Check for BI
456
3HZ
,If Bl then qo input data
RECV4
457
IN
INTI
,Else wait for last BI
458
3MP
RECV3
,In loop
459 RECV4: IN
DIN
,Get data byte
4611
STAX
,Store it in buffer
D
461
INX
,Incr data pointer
o
462
OCR
,Decrement count, but ignore it
C
463
MVI
B,1l
,Set normal completion indicators
464 ,
465 RECV5: MVI
A,TCSY ,Take control synchronously
466
OUT
CM092
467
WAITX
,Wait for Tel:1l (7 tcy)
468+??1I1115: IN
PRTF
469+
ANI
TCIF
4711+
3NZ
??II!IJl5
471
WAITT
,Wait for TeI=l
472+??1I1116: IN
PRTF
,Get task complete int,etc.
473+
ANI
TCIF
,Mask it
474+
3Z
??1I1I16 ,Wait for task to be complete
,
475
476 ,if timeout 3 is to be checked, the above WAITT should
477 ,be o~itted , the appropriate code to look for TCI or
478 ,TOU'r3 inser·ted here.
479
481l
MVI
A,AXRA ,Pattern to clear 91 END conditions
481
AUXMD
ou'r
482
A,TON
,This bit pattern already in "A"
""VI
483
OUT
ADRMD
,Output TON
484
MVI
l'\,FNHSK ,Finish handshake
OUT
485
AUXMO
486
CLRA
XRA
487+
A
,A,XOR A "Il
488
AUXMD
,I~mediate execute PON-Reset LON
ou'r
489
MOV
A,B
,Get completion character
4911 RECV6: RET
,
,
,
APPLICATIONS
491 ;
492 ;******~***.******~**.**.************************** •• * ********
493
494
495
'496
497
498
499
5111l
Sill
5112
5'13
51il4
51'15
5116
51il7
5118
5119
51'1
11311.
11 JB
1130
114111
1142
1145
1147
FE40
FABBll
FE5F
F28Bll
0351l
23
1148
11411.
114C
114F
1151
OB61
E61il2
CA4811
3E3F
0360
1153
1154
1156
1159
115B
7E
FE20
FA6Cll
FE·3F
F26Cll
115E
1160
1162
1165
1166
1168
1169
0861
E602
CA5Ell
78
0361l
23
C353U
116C
1168
1170
1173
1175
1177
1179
OB61
8602
CA6C11
3887
0365
3840
0364
1176
117C
1178
117F
1181
1183
AF
7E
0365
78
0367
38F6
0369
XFER ROUTINE
;
; INPU'rS:
;
;OU'rpUTS:
;CALLS:
;OESTROYS:
; RETURNS:
HL ~evi~e'list pointer
B 80S character
None
None
A, HL, F
A=I!J normal, A < > I!I barl talker
;
,;NOTE:
,
511 XFER:
512+
513+
514+
515+
516+
517+
518+
519+
5211+
521+
522
523
524
525+??1I1il17:
526+
527+
528
529
531!l XF8Rl:
531+
532+
533+'
534+
535+
536+
537+
538+
539+
540+
541
542+??01118:
543+
544+
545
546
547
5'48
549 XFER2:
550+??01119:
551+
552+
553
554
555
556
557
558+
559
561!1
551
562
563
RANGE
MOV
CPI
JM
CPI
JP
OUT
INX
WAITO
IN
ANI
JZ
'IVI
OUT
RANGE
MOV
CPI
JM
CPI
JP
WAITO
IN
ANI
JZ
!\IOV
ou'r
INX
JMP
WAITO
IN
' ANI
J? '
MVI
OUT
MVI
OUT
CLRA
XRA
OUT
!\IOV
ou'r
,MVI
OUT
XFER will not work if the talker
uses EOI to terminate the transfer.
Intel will be making hardware
morlifications to the 8291 that will
correct this problem. Until that time,
only 80S may be used without possible
loss of the last rlata byte t,ransfered.
4I11H,5EH,XFER4
;Check for valid talker
;Checks for value in range
;branches to label if not
lin ranqe. Falls through if
; lower <" ( (H) (L) ) <- upper.
;Get next byte.
A,M
40H
XFER4
5BHH,
XFER4
DOUT
;Send it to GPIB
H
;Incr pointer
INTI
;Get IntI status
BOM
;Check for byte 'out
??1II1'I17 ;If not, try again
A,UNL
;Universa1 unlisten
OOUT
211H,3EH,XFER2
;Check for valid listener
;Checks, for value in range
;branches to label if not
;in range. ,Falls through i f
;lower <" ( (H) (L) ) <'" upper.
;Get next byte.
11.,101
211H
XFER2
3BH+l
XF8R2
INTI
BOM
??1!J1ll8
11.,,101
DOUT
;Get IntI status
;Check for byte out
,If not, try again
;Get 1 iS,tener
H
;Incr pointer
;Loop until non-valid listener
XFERI
INTI
;Get IntI status
BOM
;Check for byte out
??0019 ;If not, try again
A, AXRA+CAHCY+EOE,OS
; Invi sible 'handshake
AUXIIIO
;Continuous AH mode
A, LON
;Listen only
AOR"IO
'A
AUXIIIO
A,B ,
'1:0SR
,'A,GTSB
CM092
;11. XOR A =Ii!
; Immed. XEQ PO"!
;Get EOS
;Output it to 91
;Go to standby
7~358
APPLIOATIONS
1185 DB6F
1187 E602
1189 C28511
118C
118E
1190
1193
1195
1197
119.0.
119C
DB6F
E602
CA8Cll
DB61
Efi10
CA9311
3e:FD
D369
119E DB5F
11.0.0 E602
11 ... 2 C29E11
11 ... 5
11.0. 7
11 ... 9
11 ... C
11AE
11B0
llB2
11B4
11B6
OB6F
E602
C...... 511
3E80
D365
3E03
D365
3E80
D364
IlB8 AF
llB9 D355
llBB C9
W... ITX
IN
... NI
J'NZ
W... ITT
IN
... NI
JZ
IN
... NI
JZ
MVI
OU'f
WAITX
IN
ANI
581H
JNZ
581
WAITT
582+171l023: IN
583+
... NI
584+
JZ
."IVI
585
586
OU'f
587
MVI
588
OU'f
.,VI
589
590
OU'f
CLRA
591
" 592+
XR ...
593
OUT
594 XFn4: RET
595
564
565+170020:
566+
567+
568
559+110021 :
570+
571+
572 XFER3:
573
574
575
576
577
578+??1l022:
579+
PRTF
TCIF
110020
PRTF
TCIF
110021
INTI
ENDMK
XFER3
A.TCSY
CM092
,Wait for TCS
,Get task complete int.etc.
;Mask it
;Wait for task to be complete
,Get END status hit
,Mask it
,Take control syncronously
PRTF
TCIF
??0n2
PRTF
TCIF
170323
....... XRA
AUX."ID
.... FNHSK
AUX!'IO
"',TON
ADRMD
;Wa i t fo r
,Get task
,Mask it
,Wait for
,Not cont
Tel
complete int.etc.
task to'be complete
AM or END on EOS
,Finish handshake
,Tal,k only
;Normal return .0.=0
,A )(OR A =0
,Immediate XEQ PON
A
AUX'IO
596 ;***************************************************
597
598
599
6~0
,
TRIGGER
6U
602 ,INPU'fS:
603 ,0UTPu'rs:
1)04 fC ... LLS:
605 ,DESTROYS:
1;06
~OUTINE
HL listener list pointer
None
None
A. HL. F
1507 ,
UBC 3E3F
UBE D3'i1l
llC0
lICl
llC3
11C6
11C8
11ce
llCO
11CF
1102
1103
1105
11D6
1109
110B
UOO
llE;0
11E2
7E
~'E20
FAD911
FE3F
F20911
OB61
e602
C...CB11
7.;
03613
23
C 3C~11
OBOl
E~02
CAD911
3EflJ8
03<;0
11E4 OB61
UEn Eh02
608 TRIG:
609
610 TRIGl:
<;11+
612+
1)13+
614+
615+
6l1i+
617'1618+
619"\"
MVI
OU'f
R... NGE
621'H'
JP
621
622+??0024:
'i23+
624+
625
1;26
627
<;28
629 TRIG2:
630+171l025:
631+
632+,
633
WAITO
IN
MOV
CPI
JM
CPI
"'1'11
JZ
"'9V
OU'f
INX
JMP
A.UNL
,
OOUT
,Send universal unllsten
20H,3EH.TRIG2
,Check for valid listen
;Checks for value in range
,branches to label if not
,in range. Falls through if
,lower <= ( (H) (L) ) <= upper.
,Get next byte.
A.M
2~H
TRIG2
3EH+l
TRIG2
IN'r!
BOM
110024
A.M
DO,UT
H
TRIGI
WAlTO
IN
ANI
JZ
,WI
OUT
1534
\'iAI'rO
635
636+??0026:
637+
,Wait for UNL to finish
;Get IntI status
,Check for byte out
,If not, try a1ain
,Get, 1 istener
~Send Listener to GPIB
,Incr. pointer
;Loop until non-valid char
,Wait for last listen to finish
IN'll
BOM
170025
A,GET
OOUT
iGet, IntI st'3tus
INTI
,Get IntI status
,Check for byte out
BOM
,Check for byte out
,If,not. try a1ain
,Selvl group ex.ecute tr i'l'ler
,to 'all addressed listeners
1-359
AFN-0138OA
APPLICATIONS
llE8 CAE4ll
llEB C9
638+
639
640 ;
·641
llEC 3E3F
llEE 03611
llFil
llFI
llF3
UF6
llF8
7E
FE211
FAII9l2
FE3F
F211912
UFB
UFO
llFF
12112
12113
12115
12116
OB61
E6112
CAFBll
7E
03611
23
C3FIIll
12119
1211B
12110
12111
1212
OB61
E602
CAII912
3EII4
0360
1214
1216
1218
121B
OB61
E602
CAI412
C9
121C 3E3F
l21E 03611
12211
1222
1224
1227
1229
OB61
E6112
CA21112
3E21
03611
122B
1220
122F
1232
1234
OB61
E6112
CA2B12
3E18
03611
1236 OB61
.JZ
RET
110026
IIf not, try again
;*.** •• *.*******~****.*** •• * •• *******.**.**
642 ;
643 ,DEVICE CLEAR ROUTINE
64'4
645 ,
646 ;
647 ,INPUTS:
HL listener pointer
648 ;OUTPUT:
None
649 ;CALLS:
None
.6511 ; DESTROYS:
A, HL,. F
651 ,
652 OCLRI'
MVI
A,UNL
653
OUT
OOUT
654 OCLRl: RANGE
211H,3EH,DCLR2
655+
;Checks for value in range
656+
;branches to label if not
657+
lin range. Falls through if
658+
; lower <= ( (HI (LI I <= upper.
659+
;Get next byte.
6611+
MOV
A,M
661+
CPI
208
662+
.JM
DCLR2
663+
CPI
3EH+!
664+
.JP
DCLR2
665
WAITO
666+1101127: IN
INTI
;Get IntI status
667+
ANI
BOM
;Check for byte out
668+
JZ
11111127 ;If not, try again
669
MOV
A,M
6711
OUT
OOUT
;Send listener to GPIB
671
INK
H
672
.JMP
OCLRI
673 OCLR2: WAITO
674+110028: IN
INTI
;Get IntI status
675+
ANI
BOM
;Check for byte out
676+
.JZ
??01128 IIf not, try again
677
MVI
A,SOC
;Send device clear
678
OUT
OOUT
;To all addressed listeners
WAITO
679
6811+??1I029: IN
INTI
;Get IntI status
681+
ANI
BOM
;Check for byte out
682+
JZ
??1I029 ;If not, try again
683
RET
684 ;
685 ;***************************************************
686
687
SERIAL POLL ROUTINE
688 •
689 IINPUTS:
HL talker list pointer
690 •
DE status buffer pointer
691 ;OUTPUTS:
Fills buffer pointed to by DE
692 ,CALLS:
None
693 ; DESTROYS:
A, BC, DE, HL, F
694 ;
695 SPOL:
MVI
A,UNL
;Universal unlisten
696
OUT
DOUT
697
WAITO
698+??IIII311:
INTI
IGet IntI status
699+
A:tr
BOM
;Check for byte out
71111+
.JZ
??1I0311 ,If not, try again
701
MVI
A,MLA
IMy listen address
7112
OUT
OOUT
7113
WAITO
7114+??II031 : IN
INTI
;Get IntI status
705+
ANI
BOM
,Check for byte out
7116+
JZ
110031 IIf not, try again
707
MVI
A,SPE
ISerial poll enable
708
OUT
DOUT
ITo be formal about it
709
WAITO
710+??0032 : IN
INTI
IGet IntI status
7-360
~138OA
APPLICATIONS
1238 E632
123A CA3~12
1230
123E
1240
1243
1245
1248
1249
124B
124C
124E
7E
FE40
FA9412
FE5F
F29412
7E
D36~
23
3E40
D364
1250 OB61
1252 E602
1254 CA5012
1257
1258
125."
125C
AF
0365
3EF6
0369
125E DB6F
1260 E602
1262 C25E12
1265 OB6F
12~7 E602
1269 CM512
126C
126E
126F
1271
1274
1276
OB61
47
E601
CAOC12
3EFD
D359
1278 OB6F
127A E602
127C C27812
127F
1281
1283
1286
1288
1289
128A
128C
OB6F
E602
CA7F12
DB60
12
13
3EB0.
03~4
128E AF
128F 0365
711+
712+
713 SPOL1:
714+
715+
716+
717+
718+
719+
72"'+
721+
722+
723+
724
725
726
727
728
729
73"'+??0~33:
731+
732+
733
734+
735
736
737
738
739+??0034:
740+
741+
742
74H??0CB5:
744+
745+
746
74 7+??0036:
748+
749+
750+
751
752
753
754+??0~37:
755+
756+
757
758+??0038:
759+
76C1J+
761
762
763
764
765
761;
767+
768
ANI
JZ
RANGE
MOV
CPI
JfIf
CPI
JP
MOV
OU'f
INX
"'VI
OUT
WAITO
IN
ANI
JZ
CLRA
XRA
OU'f
"'VI
OUT
WAITX
IN
ANI
JNZ
WAITT
IN
ANI
JZ
WAITI
IN
MOV
ANI
JZ
MVI
OU'f
WAITX
IN
ANI
JNZ
WAITT
IN
ANI
JZ
IN
STAX
INX
MVI
OUT
CLRA
XRA
OU'f
BOM
;Check for byte oJt
??0032 ;If not, try again.
40H,5EH,SPOL2
;Check for valid talker
;Checks for value in range
;branches to 1a~e1 if not
lin range. Falls through if
;lower <= ( (Hl (Ll l <= upper.
;Get next byte.
A,M
411H
SPOL2
5EH+l
SPOL2
A,M
;Get talker
;Send to GPI.B
DOU'f
;Incr t~lker list pointer
H
A,LO'll
;Listen only
ADRMO
;Wait for talk a~dress to complete
INT!
;Get IntI status
BOM
;Check for byte out
7111"'33 ;If not, try again
;Pattern for immediate XEQ paN
A
;A XOR A
AUXMD
A,GTSB ;Goto standby
CM092
;Wait for TCl false
PRTF
TCIF
71C1lC1l34
;Wait for TCI
PRTF
;Get task complete int,etc.
;Mask it
TCIF
710035. ;Wait for task to be complete
;Waitfor status byte input
IN'rl
;Get INTI status
B,A
;Save status in B
BIM
;Check for byte in
;If not, just try again
??0~36
A,TCSY ;Take control sync
CMD92
;Wait for TCI false
PRTF
TCIF
??"'037
;Wait for TCI
;Get task complete int,etc.
PRTF
;Mask it
TCIF
71IHB8 ;Wait for task to be complete
;Get
serial poll status byte
DIN
;Store it in buffer
o
;Incr pointer
D
A,TON
;Talk only for controller
ADRMD
='"
JMP
SPaLl
;A XOR A =1')
;Immeditate XEQ PON
; CLR LA
;Go on to next device on list
MVI
OUT
'wAITO
IN
ANI
JZ
CLRA
XRA
OUT
RET
A,SPO
DOU'r
;Seria1 poll disable
;We know BO was set (WAITO above)
IN'rl
BaM
710039
;Get IntI status
;Check for byte out
;If not, trY again
A
;A' XOR A =1'1
;Immediate XEQ PON to clear LA
A
AUXMD
7~9
1291 C33012
1294 3El9
1296 0360
1298 OB61
129A E602
129C CA9812
129F AF
12Ml 0365
12A2 C9
770
771 ,
772 SPOL2:
773
774
775+??2039:
776+
777+
778
779+
780
781
782
783
784
AUXMO
****** ••• *.**.*** ••••• ** ••••• ***.***** ••••••••••• *.**
7-361
AFN-ol380A
APPLICATIONS
12A3 3E3F
12A5 036('1
12A7
12M
12M
12AD
12AF
7E
FE2('1
FA0812
FE3F
F2D812
12B2
1284
12B6
12B9
12BA
OB61
£602
CAB212
7E
0359
12BC
12BE
12CIl
12C3
12CS
DB61
£602
CA8C12
3E:"S
036"
12C7
12C9
12CB
12CE:
12CF
1201
1203
1204
12DS
OB61
E6"'2
CAC712
1A
F661l
0361!l
23
13
C3A712
1208 DB61
12DA E:6~2
12DC CADB12
12DF C9
12EI!l 3E3F
12E2 0360
12E4
12E5
12E7
12EA
12EC
7E
FE21il
FAFD12
FE3F
F2FD12
12EF DB61
12F1 E602
12F3 CAEF12
785
PARALLEL POLL E:NABLE ROUTINE
786,
,
787 I INPUTS:,
HL listener list pointer
788 ;
'DE configuration byte pointer
None
789 ;OUTPUTS:
None
790 ;CALLS:
A, DE:, HL, F
791 ; DESTROYS:
792
793 ;
794 PPEN:
MVI
A,UIIIL
;Universal un1isten
DOU'r
795
OUT
796 PPEN1: RANGE
20H,3EH,PPEN2
;Check for valid listener
797+
;Checks for value in range
798+
;branches to label if not
799+
lin range. Falls through if
890+
;lower <= ( (H) (L) ) <= upper.
;Get next byte.
801+
8912+
MOV
A,M
803+
20H
CPI
PPE:N2
81!l4+
J"I '
3EH+l
80S+
CPI
8116+
PPEN2
JP
8117
WAITO
;Valid wa i t 91 data out reg
&08+??II04('1: IN
INTI
;Get IntI status
Alii I
809+
BOM
;Check for byte out
??('IPl4A ;If not, try again
810+
JZ
811
MOV
A,M
;Get listener
812
OUT
DOUT
813
'/IAITO
814+??IIP141: IN
IN'rl
;Get IntI status
815+
Alii I
80M
;Check for byte ~ut
816+
JZ
??"9141 ;16 not, try again
817
MVI
A,PPC
;Para1le1 poll configure
OU'f
DOUT
818
,WAITO
819
82IH??Pl042. IN
INTI
,Get IntI status
821+
Alii I
80t'1
;Check for byte out
822+
JZ
??!ll9l42 ;If not, try again
LDAX
,Get matching configuration byte
823
o
824
ORI
;Merge with parallel poll enable
PPE:
OU'f
825
DOUT
INX
826
H
;Incr pointers
INX
o
827
PPE:N1
JMP
;Loop until invalid listener char
828
829 PPE:N2: \~AITO
830+(11'1043: IN
INTI
;Get Inti status
ANI
BOM
;Check for byte out
831+
832+
JZ
??1!343 ;If not, try again
RET
833
834 ;
835 ;PARALLEL POL,L DISABLE ROU'fIIIIE
836 ;
837 ;INPUTS:
HL listener list pointer
None
838 ;OUTPUTS:
839 ,CALLS:
None
840 ;DE:STROYS:
A, HL, F
841 •
A,UIIIL
842 PPDS:
,'WI
;Universal unlisten
OU'f
DOUT
843
844 PPOS1: RANGE
20H,3EH,PPDS2
;Check for valid listener
;Checks for value in range
84S+
841;+
;branches to label if not
lin range. Falls through if
847+
;lower <= ( (H)(L) ) <= upper.
848+
;Get next byte.
849+
8SA+
MOV
A,M
8S1+
CPI
20H
852+
JM
PPDS2
CPI
aS3+
3EH+l
854+
3P
PPDS2
WAITO
855
IN
856+110044 :
IN'rl
;Get IntI status
ANI'
BOM
;Check for byte out
857+
JZ
??0A44 ;If not, try again
8S8+
APPLICATIONS
12F6
12F7
12F9
12FA
7E
D360
23
C3E412
12FD D861
12~'F E'51l2
1301 CAFD12
1304 3E05
130<; D360
1308
13M
130C
130F
1311
DB61
E602
CA0813
3E70
D360
1313
1315
1317
131A
DB61
E602
CA1313
C9
131B 3E15
DID D360
131F
1321
1323
1326
DB61
E602
CAIF13
C9
1327 3E40
1329 D364
1328
132C
P2E
1330
AF
D365
3EF5
D369
1332
1334
1335
1337
133A
133C
D861
47
g6"1
CA3213
3EB"
D364
133E
133F
1341
1343
AF
D355
D8'i0
C9
"lOV
A,M
;Get listener
OUT
OOUT
81;1
INX
H
;Incr pointer
PPDSI
862
JMP
;Loop until invalid listener
8li3 PPDS2: WAlTa
81;4+??01l45:
IN
IN'rl
;Get IntI status
865+
ANI
BaM
;Check for byte out
861i+
.JZ
?10045 ;IE not, try again
81;7
'~VI
;Parallel poll configure
A,PPC
OUT
8G8
DOUT
WAlTa
869
IN
870+??0046:
INTI
;Get IntI status
ANI
BOI~
871+
;Check Eor byte out
872+
JZ
??01l46 ;If not, try again
MVI
A;PPD
;Paral1el poll disable
873
OOUT
OUT
874
WAITO
875
INTI
IN
;Get IntI status
876+??0047 :
BaM
877+
ANI
;Check for byte out
878+
??0047 ;If not, try again
JZ
RET
879
880
881
PARALLEL POLL UNCONFIGURE ALL ,ROU'rINE
882
883 ,
884 ; INPu'rs:
None
885 ;OUTPUTS:
None
886 ;CALLS:
None
887 ;DESTHOYS:
A, F
888
889 PPUN:
MVI
A,PPU
;Parallel poll unconfigure
ou'r
OOUT
890
891
WAITO
892+??1l048:
IN
INTI
;Get Intl status
ANI
893+
BaM
;Check for byte out
894+
JZ
??0048
;If not, try again
RET
895
89e; ,
897 ;**************************************************
898 ,
899 ;CONDUCT A PARALLEL POLL
900
901 ,
902 ;INPUTS:
None
903 ;OUTPUTS:
None
904 ;CALLS:
None
905 ;DESTROYS:
A, S, 10'
906 ;RETURNS:
A= parallel poll status byte
907 ,
MVI
908 PPOL:
A,LON;Listen only
Al)RMD
909
oU'r
910
CLRA
;Immediate XEO paN
911+
XRA
A
;A XOR A =0
912
OUT
AUXMD
;Reset TO'"
913
"lVI
A,EXPP ;Execute parallel poll
914
ou'r
CMD92
915
WAI'rI
;Wait for completion= BI on 91
916+??0049: IN
INTl
;Get INTI status
917+
MOV
8,A
;Save status in B
918+
ANI
BIM
;Check Eor byte in
919+
JZ
??0049 ;IE not, ;ust try again
920
I~VI
A,TON
;Talk only
OUT
ADRMD
921
922
CLRA
;Immediate XEQ PON
923+
XRA
A
;A XOR A =0
924
ou'r
AUXMD
;Reset LOlli
IN,
925
DIN
;Get PP byte
926
RET
927 ,
928 ;**********************************************
929 ; PASS CON'rROL Rou'rINE '
930 ,
931 ;INPUTS:
HL pointer to talker
932 ;OUTPu'rs:
None
859
8~0
7-363
AFN-{)138OA
APPLICATIONS
1344
1345
1347
134,11
134C
134F
1351
1354
7E
FE40
FA8A13
FE5F
F28A13
FE41
CA8Al3
031';0
1356 OB61
1358 E6e 2
135A CA5613
1350 3E09
135F 03':;"
1361
1363
131;5
1368
.136,11
OB61
E602
CMU3
3E01
0364
13r,C AF
1360 0365
136F 3E01
1371 0366
1373 3EA1
1375 031;5
1377 3EFl
1379 0369
137B DB6F
1370 E602
137F C27B13
1382
1384
1385
1389
138,11
DB6F
E602
CA8213
23
C9
138B
1380
138F
1392
1394
DB51
E680
CACF13
OB65
FE09
None
933 ;CALLS:
934 ; DESTROYS:
A, HL, F'
935 PCTL:
RANGE
40H,5EH,PCTL1
;Is it a valid talker?
936+
;Checks for value in range
937+
;branches to label if not
938+
lin range. Falls through if
939+
; lower <= ( (H) (L) ) <= upper.
941H
;Get n·ext byte.
941+
MOV
A,M
942+
CPI
4flH
J,>\
943+
PCTL1
944+
5EH+I
CPI
945+
PCTL1
JP
;Is it my talker address
946
CPI
MTA
;Yes, just return
.
947
JZ
PCTL1
948
OUT
DOUT
;Send on GPIB
949
WAlTa
IN
950+??0050:
INT1
;Get IntI status
ANI
951+
BOM
;Check for byte out
952+
JZ
;IE not, try again
??005~
953
I>1VI
A,TCT
;Take control messaqe
ou'r
954
DOUT
WAITO
955
IN
IN'fl
956+??0051 :
;Get IntI status
ANI
BOM
;Check for byte out
957+
958+
JZ
??0~51
;If not, try again
A,MODE1 ;Not talk only or listen only
959
MVI
OUT
ADRMD
;Enab1e 91 address mode 1
960
961
CLRA
9<;2+
XRA
A
;,11 XOR A =0
903
OUT
AUX.,O
;Immediate XEQ PON
%4
·~VI
A,MDA
;My device address
965
OUT
ADR~1
;enabled to talk and listen
96<)
MVI
A,AXRB+CPTE"I
;Command pass tbru enable
OUT
AUXMD
967
968 ;*******optional PP configuration goes here********
9119
MVI
A,GIDL
;92 go idle command
ou'r
CMD92
970
971
WAITX
PRTF
972+??0052 : IN
973+
TCIF
ANI
974+
??01il52
JNZ
;Wait for TCI
975
WAITT
976+??0053: IN
;Get task complete int,etc.
PRTF
ANI
977+
;Mask it
TCIF
978+
JZ
??0053 ;Wait for task to be complete
INX
979
H
980 PCTL1:
RET
981
982 ;
983 ;*****************************************
984 ;
985 ;RECEIVE CONTROL ROUTINE
986 ,
None
987 ; INPUTS:
None
988 ;OUTPUTS:
None
989 ;CALLS:
990 ;DP-STROYS:
A, F
0= invalid (not take control to us or CPT bit not on)
991 ;RETlJRNS:
< > 0 = valid take contro1-- 92 will now be in control
992 ,
THIS CODE MUST BE TIG9TLY INTEGRATED INTO ANY USE~
993 ;NOTE:
SOFTWARE THA'r FUNCTIONS \-.JITH THE 8291 AS A DIWICE.
994
NORMALLY SOI'1E ADVA"ICE WARNING OF IMPENDI"IG PASS
995
CO"lTROL SHOULD BE GIVE"I TO US BY rHE CONTROLLER
990
t.ITH OTHER USEFUL INFO. THIS PRO'rOCOL IS SITUATION
997
SPECIFIC AND WILL NOT BE COVERED HERE.
998
999
1000 ,
;Get INTI reg (i.e. CPT etc.)
1001 RCTL:
IN
IN'rl
;Is command pass thru on ?
ANI
1002
CPT
;No, invalid-- go return
1003
RC 'rL 2
JZ
1004
IN
CP'rRG
;Get command
;Is it take control?
1005
CPI
TCT
7-364
AFN-0138OA
APPLICATIONS
1396
1399
139B
139D
13 ... 0
13.0.2
C2C ... 13
OBI;4
E602
C...C... 13
3E60
D356
13M 3E8~
13 ... 6 0354
13M AF
13.0.9 031;1
13 ... B 03'i2
13... 0 0365
13 ... F 3EFA
13Bl'D3';9
13B3 3E0F
13B5 03<;5
13B7 OB<;F
13B9 E61l2
l3dB C2B7l3
13dE
l3e0
l3C2
13C5
13C7
13CA
13CC
DB6F
EI;~2
CABEl3
3E09
C3CF13
3E0F
0365
13CE AF
13CF C9
1006
1007
lI!08
1009
HlU
lin 1
1012
11'113
1014
1015+
1016
1017
1303 DB59
E620
CAE213
~'50B
D369
OB69
E602
CAOB13
C9
ou'r
MVI
ou'r
CLRA
XRA
OUT
OUT
OUT
MVI
RCTLI
ADR'lT
TA
RCTLI
A.OTOLI
AORIn
A.TON
AORMD
;No. go return invalid
;Get address status
;Is T... on ?
;No -- go return invalid
;Oisable talker listener
;Ta1k only
;A XOR A =0
INTI
;Mask.off INT bits
INT2
UI18
AUXMO
A.TCN'rR ;T.ake (receive) control 92 command
1019
CM092
1020
ou'r
A.VSCMO ;Va1id command pattern for 91
11321
MVI
AUXI'10
1022
OUT
1023 ; •••••••• optional TOUT1 check could be put here ••••••••
'.-JAITX
1024
1025+71111154 : IN
PRTF
ANI
1026+
TCIF
JNZ
1027+
??0054
;Wait for TCI
Hl28
'IIAITT
PRTF
;Get task complete int.etc.
1029+710055: IN
1030+
... NI
;Mask it
TCIF
;Wait for task to be complete
1031+
JZ
??0~55
1032
MVI
;Valid return pattern
A.TCT
;Only one return per routine
RC'rL2
1033
J'lP
lI!34 RCTL1: MVI
.... VSOolD ;Acknow1edqe CPT
AUXMD
1035
ou'r
CLRA
1035
;Error return pattern
XRA
,; ... XOR ... =0
1037+
...
1038 RCTL2: RET
Hl39 •
104~
1302
1304
1307
13D9
130B
130D
13DF
13E2
JNZ
IN
ANI
JZ
MVI
1041
1042
1(l43
1044
1045
1046
1047
1048
1049
1"50
1051
1052
1053
1054
Hl55
1056
11157
1058
1059
A
~********************************.******.*********
.
SRO ROUT I"'!:
; INPU'rS:
;OU'rpUTS:
;CALLS:
;RE'rURNS:
SRQD:
IN
ANI
JZ
ORI
ou'r
SRQDl:
SRQD2:
IN .
ANI
JZ
RET
None
None
None
.0.= 0 no
.0.<> 0
SRQ
SRQ occured
INTST
SRQBT
SRQD2
lACK
CMD92
INTST
IBFBT
SRQOl
;Get 92's INTRQ status
;Mask off SRQ
;Not set--- go return
;Set--- must clear it with I ... CK
;Get IBF
;Mask it
;Wait if not set
Hl51'J •
1061 ~*.***************.****************.**.******
1"~2
13E3 3EF8
13E5 0369
13E7 DBhF
13E9 E<;02
13EB C2E7l3
13EE DB6F
13F0 g<;02
13F2 CAEg13
•
;REMOTE ENABLE ROUTINE
;
; INPUTS:
None
; ou'rpUTS:
None
;CALLS:
NONE
.... F
;DESTROYS:
;
MVI
.... SREM
REME:
OUT
CMD92
\'iAI'rX
HI 72
PRTF
1Il73+??1l~5<):
IN
ANI
TCIF
1074+
JNZ
1Il75+
??005<;
WAITT
1071;
1077+??0057: IN
PRTF
1078+
ANI
TCIF
1079+ ??(l057
JZ
1063
1064
11'155
1066
11157
1068
1069
1070
1071
;92 asserts remote enable
;Wait for TCI = 0
;Wa i t fo r TCI
;Get task complete int.etc.
;Mask it
;Wait for task to be complete
7-365
AF~l38OA
APPLICATIONS
131'5 C9
131'6 3EF7
131'8 0369
13FA D86F
13Fe E602
131'E C2I'A13
1401
1403
1405
1408
D86F
E602
CA0114
C9
1409 3EF9
1UIIl D3119
140D DBfiF
1401' E'i1/J2
1411 C20D14
1414 DB6F
1416 E602
1418 CA1414
141B C9
1080
RET
U81 ;
lAR2 ;******************.*.*********************
lIl83 ,
U84 ; LOCAL ROUTI'IIE
1085 ,
Hl86 ;
1I'l87 ;INPU'l'S:
None
None
U88 ,OUTPUTS:
None
1089 ;CALLS:
A, I'
1Pl9I'J ; DESTROYS:
1091 ;
.,VI
A,SLOC
11'192 LOCL:
CMD92
OUT
;92 stops asserting remote enable
1093
WAITX
;Wait for TCI =IiJ
1094
PRTF
1Pl9S+??1l0 58: IN
ANI
TCIF
1096+
JNZ
1I'l~7+
??"I'I5R
;Wait for TCI
1098
WAIT'r
;Get task complete int,etc.
PRTF
1I!99+??tH'159 : IN
;Mask it
1101'1+
TCIF
ANI
ll1ll+
JZ
??I"1J59 ;Wait for task to be complete
1102
RE'r
1103 ;
1194 ;********************************\*************
1105 ;
lUI; ; I"ITERFACE CLEAR / ABORT ROU'rINE
1Hl7
11"S ;
None
1109 ; INPu'rs:
None
1111'1 ;ou'rpUTS:
None
1111 ;CALLS:
A, l'
1112 ;DESTROYS:
1113
1114 ,
1115 IFCL:
MVI
A,ABORT
1116
OUT
C..,D92
;Send IFC
1117
WAITX
;Wait for TCI =A
1118+??"~60: IN
PRTF
1119+
ANI
TCIF
1120+
JNZ
??006~
1121
WAITT
;"a i t fo r TCI
1122+??0061: IN
PRTF
;Get task complete int,etc.
1123+
AliI
TCIF
;Mask it
1124+
JZ
??~0"1
;Wait for tas~ to be complete
1125 ; Delete bott) WAI'rX & WAITT i f thi s rout ine
1126 lis to be called while the 9292 is
11'7 ;Contro11er-in-Charqe. If not C.I.C. then
l12S';TCI is set, else nothing is $et (IFC is sent)
1129 land the WAIT'S will hanq forever
113e
RET
1132
7-366
AF~t38OA
APPLICATIONS
01132
0031
0051
000D
0001'.
00fo'F
0040
141C
1421l
1424
1428
1421'.
000F
142B
142F
0006
1431
1432
1433
1434
1435
143<;
31
FF
32
FF
51
FF
1437
1439
143B
143E
1441
Ilfi0D
0E0F
ll1C14
213314
CD1C10
1444
1446
1448
144B
144E
46553146
5233374B
48414032
564F
0D
50463447
3754
0'i54
0E06
112a14
213114
CD1C10
1451 CDD0l3
1454 CA5114
1457
1451'.
145D
1460
1461
1462
1464
1467
1469
146B
146E
1471
1474
11003C
213514
CD1C12
IB
11'.
E640
(;1'.7714
0601'.
0E11
213514
11013C
CD9F10
C27714
1477 00
3C00
3C00
0011
1133
1134
1135
1136
'1137
1138
1139
1140
1141
1142
1143
;APPLICATION EXAMPL8 CODE FOR
8~85
;
FGDNL
~'CDNL
FCDNT
CR
LF
LEND
SRQM
EQU
EQU
EQU
EQU
EQU
EQU
EQU
;Func gen device num "2" ASCII,lstn
;Freq ctr device num "I" ASCII,lstn
;Freq ctr talk address
;ASCI! carriage return
;ASCII line feed
;Llst end for Talk/Listen lists
;Blt indicating device sent SRO
'2 '
'I'
'Q'
(lDt!
0AH
0FFH
40H
;
'FUIFR37KHAM2VO',CR
;Data to set up func. gen
1144 LIr-ll
EQU
1145 FCDATA: DB
15
'PF4G7T'
;Buffer length
;Data to set up freq ctr
1146 LIM2
1147 LL1:
EQU
DB
I;
FCDNL, LEND
;Buffer length
;Listen list for freq ctr
1148 LL2:
DB
FGDNL,L8ND
;Listen list for func. gen
1149 TL1:
DB
FCDNT,LE:ND
;Talk list for freq ctr
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
111;1
1162
1163
111';4
111i5
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
117R
1179
1180
1181
1182
1183
1184
1185
1181;
1187
1188
1189
1190
1191
1192
1193
1194
1195
1195
1197
FGDATA: DB
;SETUP FUNCTION
MVI
MVI
LXI
LXI
CALL
,
GENERATOR
B,CR
;E:OS
C,LI.,1 ;Count
D,FGDATA
;Data pointer
H,LL2
;Listen list pointer
SEND
;SETUP FREO COUNTER
.,VI
MVI
LXI
LX!
CALL
B,'T'
;EOS
C, LI.,2 ;Count
D,FCDATA
;Data pointer
H,LL1
;Listen list pointer
SEND
;WAIT FOR SHQ FROM FREO CTR
,
LOOP:
,
CALL
JZ
SRQD
LOOP
;Has SHQ occurred ?
;No, wait for it
;SERIAL POLL TO CLEAR SRQ
LXI
LXI
CALL
DCX
LDAX
ANI
JZ
D,SPBYTE:
H,TLI
SPOL
D
D
SRQM
ERROR
;Buffer pointer
;Ta1k list pointer
;Backup buffer pointer to ctr byte
;Get status byte
;Did ctr assert SRQ ?
;Ctr should have said yes
;RECEIVE READING FROM COUNTER
MVI
.,VI
LXI
LXI
CALL
JNZ
B,LF
;EOS
C,LI.,3 ;Count
H,TL1
;Ta1k list pointer
D,FCDATI
;Data in buffer pointer
RECV
ERROR
;
;******* rest of user processing goes here *****
;
ERROR:
;
NOP
ETC.
ORG
3C~0f1
SPBYTE: OS
LI.,3
EOU
;User dependant error handling
1
17
;Location for serial poll byte
;r-lax freq counter input
7-367
AFN-Ol38OA
APPLICATIONS
3CflJl
1198 FCOATI : OS
EIliO
1199
;Freq ctr input buffer
LIM3
PUBLIC SYMBOLS
EXTERNAL
SYI~BOLS
US EH SW180LS
ABOHT
A 00F9
8IM
A 0001
CLHS'F A 0068
OCLR
A !lEC
Eoeos
A 0004
ERROR
A 1477
,'CDNL A 0031
GS~C
A 00F4
IFCL
A 1409
IN'FST A 0069
LL1
A 1431
~ODE1
A 03~1
PPD
A 0070
PPEN2
A 12D8
RANGE
+ 0005
RECVl
A 10EA
RER,'
A 00E4
SDEOI
A 0006
SEN06
A 1088
SPIF
A 0004
SRQD1
A 13DB
'FCNTR
A 00FA
TOST
A 0068
UNL
A AB3F
WOU'f
A 00E1
ASSEI~BLY
ADHOI
HOF
CMD92
DCLR1
END"1K
EVBIT
FCDN'F
G1'SB
INIT
LA
LL2
MTA
PPDS
PPOL
RaST
REcn
RERM.
SEND
SE'FF
SPOL
SRQD2
TCSY
TOU'Fl
VSCMD
XFER
CQI4PLETE,
A
A
A
A
A
A
A
A
A
A
A,
A
A
A
A
A
A
A
+
A
A
A
A
A
A
09~<
ADIl"1.D
0001
0369
llF0
0010
0010
0051
00F6
1000
0001
1433
BOM
CPT
DCLR2
EOIS
EVCST
FGDATA
HOEND
INTI
LEND
LOCL
0~41
~VC~D
12E0
1327
00E7
11A5
03EA
lAIC
0000
121C
13£2
00FD
0001
BeeF
113A
PPDSl
PPU
ReST
RECV3
REVC
SEND1
SLOC
SPOL1
SROM
'FCT
TOUT2
WAITI
XFERl
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
.~
00~4
0~02
A0RA
1209
0038
0068
1d1C
0002
00<1
00FF
13F'
0007
12E4
A01S
0"EI}'
11O'
A 00E3
A 102E
A B0F7
A 123D
A 0040
A 0009
A 00~2
+ 00A2
A 1153
ADRST
BUSST
CPT~N
DI~
EOIST
EVREG
A
A
A
A
A
A
A
0~'4
AUX'1D
QJ~~FI:
CAHCY
Ao.I~l
CPTRG
0"11~
DOUT
EOSq
EXPP
FNHSK
lACK
INTM
LIM 1
LOOP
PCTL
PPE
PRT91
RC1'Ll
HECVS
RSET
SEND3
SPCNI
SREM
TA
TL01\l
'fRIG
WAITT
XFER 1
002"
0068
FG~NL
0032
HO~S~
A 0001
INT2
A 00'2
LF
A 000A
LON
A A~4A
OBFF
A A~~8
PPDS2 A 12FD
PPUN
A 131B
RCTL
A 139B
RECV4
A 111A
RIN:"I
A 00ES
SEND2
A 1047
SPBY'FE A 3C00
SPOL2
A l?94
STCNI
A 0AFE
'FLl
A 1435
TOUT3
A 0AA4
WAITO
+ AA01
XFER2
A 116C
A
A
A
A
A
A'
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
00'0;
0031
011Jhlj
0O'.
00')7
00FS
0001
0 •• B
00A0
000F
14'1
1344
.l\XRA.
CLKRT
CR
DTO!:l
ERFLG
FCDATA
GET
IBFBT
1'ITMl
Llt"t2
MDA
PCTL1
0~'A
PPE~
00~0
PR'fn
RCTL2
RECV"
RSTI
SEND4
SPD
llCA
1117
00F2
10'9
BAF0
0AF8
0002
"ACA
!lBC
+ 0004
A 1193
S~OBT
TCASY
'ro~
TRIG1
WAITX
XFER4
A
A
A
A
A
A
A
A
A
A
A
,A
A
A
A
A
A
A
A
A
A
A
A
0060
0023
~~(1)
00'0
~0t;8
1428
0008
00"2
0.'H
000'
A~~l
138A
12A3
00~~
13CF
1139
00F3
1070
0019
00?0
00FC
A"qA
11C0
+ 0AA3
A 11BB
AXRB
CLRA
OCL
DTOL2
A 00AO
+ 0007
A
A
,eRR'~
A
FCDATI A
GIDL
A
A
IBFF
INTMR
A
LIM3
A
MLA
A
PPC
A
PPEN1
A
PRTF
A
RECV
A
REME
A
RTOU'F
A
SENDS
A
spe
A
A
SROD
'feIF
A
TQREG
A
A
,!,RIG2
'.EVC
A
0914
00e0
0068
3C01
00F1
0010
0068
0011
AA21
00AS
12A7
006F
109F
13E3
00E9
107F
0018
1300
00A2
00l'iS
1109
A0E2
NO ERRORS
7-368
AfN.0138OA
APPLICATIONS
APPENDIXB
TEST CASES FOR THE SOFTWARE DRIVERS
The following test cases were used to exercise the
software routines and to check their action. To
provide another device/controller on the GPIB a
ZT488. GPIB Analyzer was used. This analyzer
acted as a talker, listener or another controller as
needed to execute the tests. The sequence of outputs are shown with each test. All numbers are
hexadecimal.
SEND TEST CASES
B =44
C = 30
DE = 3E80
HL = 3E70
3E70: 20 30 3E 3F
3E80: 11 44
GPIB output: 41 ATN
3FATN
20ATN
30ATN
3EATN
11
44EOI
Ending
Ending
Ending
Ending
B
C
DE
HL
=44
= 2E
= 3E82
= 3E73
44
2
3E80
3E70
44
0
3E80
3E70
41ATN
3FATN
20ATN
30ATN
3EATN
11
44 EOI
41ATN
3FATN
20ATN
30ATN
3EATN
44
0
3E82
3E73
44
0
3E80
3E73
RECEIVE TEST CASES
B
C
DE
HL
3E70:
GPIB output:
ZT488 Data
In
Ending A
Ending B
Endi~g C
Ending DE
Ending HL
=44.
= 30
= 3E80
= 3E70
40
40ATN
3F ATN
21 ATN
1
2
3
4
44
=0
=0
= 2B
=3E85
=3E71
44
30
3E80
3E70
50
50ATN
3F ATN
21 ATN
1
2
3
4
5,EOI
0
0
2B
3E85
3E71
44
30
3E80
3E70
5E
5EATN
3FATN
21 ATN
1
2
3
44,EOI
44
30
3E80
3E70
5F
44
4
3E80
3E70
40
40ATN
3FATN
21 ATN
1
2
3
4
44
4
3E80
3E70
40
40ATN
3FATN
21 ATN
11
22
33
44
44
0=256
3E80
3E70
40
40ATN
3F ATN
21 ATN
1
2
3
44
0
0
2C
3E84
3E7l
5F
44
30
3E80
3E70
40
40
0
3E84
3E71
0
0
0
3E84
3E7l
0
0
FC
3E84
3E71
SERIAL POLL TEST CASES
C = 30
DE = 3E80
HL =3E70
3E70: 40
50
5E
5F
C = 30
DE = 3E80
HL = 3E70
3E70: 5F
GPIB output: 3F ATN
21 ATN
18ATN
7-369
AFN-Ol38OA
APPLICATIONS
GPIB output: 3F ATN
19ATN
output: ,21 ATN
EndingC = 30
output: 18 ATN
Ending DE = 3E80
output: 40 ATN
Ending HL = 3E70
input*: '00
output: 50 ATN
input*: ' 41
output: SE ATN
input*: 7F
output: 19 ATN
*NOTE: leave ZT488 in single step mode even on input
Ending C = 30
Ending DE = 3E83
Ending HL = 3E73
Ending 3E80: 00 41 7F
PASS CONTROL TEST CASES
HL = 3E70
3E70: 40
GPIB output: ,40 ATN
09ATN
-ATN
Ending HL = 3E71
Ending A = 02
3E70
41(MTA)
3E70
SF
3E70
41(MTA)
3E70
SF
RECEIVE CONTROL TEST CASES
GPIB input
10 ATN '
A'i"N
Run Receive Control
GPIB Input
Ending A =
0
40ATN
09ATN
41 ATN
09ATN
Am
ATN
0
09
PARALLEL POLL ENABLE TEST CASES
DE = 3E80
HL = 3E70 ,
3E70: 20 30 3E 3F
3E80: 01 02 03
GPIB output:
3F ATN
20ATN
OSATN
61 ATN
30ATN
OSATN
62ATN
3EATN
OSATN
63ATN
Ending DE =3E83
Ending HL = 3E73
3E80
3E70
3F
3FATN
3E80
3E70
PARALLEL' POLL DISABLE TEST CASES
HL = 3E70
3E70: 20 30 3E 3F
3E70
3F
7-370
APPLICATIONS
GPIB output:
3F ATN
20ATN
30ATN
3EATN
05ATN
70ATN
Ending HL = 3E73
3FATN
05ATN
70ATN
3E70
PARALLEL POLL UNCONFIGURE TEST CASE
GPI~
output:
15 ATN
PARALLEL POLL TEST CASES
Set DID #
EndingA
1 2 3 4 5 6 7 8 None
1 2 4 8 10 20 40 80 0
SRQ TEST
Ending A
Set SRQ momentarily
= 02
Reset SRQ
00
TRIGGER TEST
HL = 3E70
DE = 3E80
BC = 4430
3E70: 20 30 3E 3F
GPIB output: 3F ATN
20ATN
30ATN
3EATN
08ATN
Ending HL = 3E73
DE = 3E80
BC = 4430
DEVICE CLEAR TEST
HL = 3E70
DE = 3E80
BC = 4430
3E70: 20 30 3E 3F
GPIB output: 3F ATN
20ATN
30ATN
3EATN
14ATN
Ending HL = 3E73 .
DE = 3E80
RC =4430
7-371
AFN.(J138OA
··APPLICATIONS
XFER TEST
B
HL
3E70:
GPIB output:
GPIB input:
Ending A
B
HL
=44
=3E70
40 20 30 3E 3F
40ATN
3FATN
20ATN
30ATN
3EATN
0
11
2
3
44
=0
=44
=3E74
APPLICATION EXAMPLE
GPIB OUTPUT/INPUT
GPIB output:
GPIB input:
GPIB output:
GPIB input:
GPIB output:
41 ATN
3FATN
32ATN
46
55
31
46
52
33
37
4B
48
41
4D
32
56
4F
OD EOI
41 ATN
3F ATN
31 ATN
50
46
34
47
37
54EOI
SRQ
3FATN
21 ATN
18 ATN
51 ATN
40 S1fQ
19ATN
51 ATN
7-37.2
~138OA.
APPLICATIONS
GPIB input:
3F ATN
21 ATN
20
2B
20
20
20
33
37
30
30
30
2E
30
45
2B
30
OD
OA
GPIB output:
XX ATN
APPENDIX C
REMOTE MESSAGE CODING
T
y
C
I
()
p
Message Name
Mnemonic
H 7
e
ACG
addressed command group
M
At:
ATN
attention
U
lIC
DAB
data byte
M
DD
DAC
DAV
data accepted
data valid
device clear
U
HS
U
M
HS
(Notes 1.9)
D
a ,I
UC
ST
X X X
y
0
X X X
E E E
8 7 6
y 0 0
y 0 It
o
end
EOS.
end. of string
GET
GTL
lOY
group execute trigger
go to local
identify
interface clear
M
M
listen address group
local lock out
my listen address
M
(Note 3)
M
AC
AC
UC
UC
AD
UC
AD
MTA
my talk address
:Note 4)
M
AD
Y
MSA
my secondary address
(Note 5)
M
SE
y
lFC
LAG
LLO
MLA
(Notes 2. 9)
U
U
M
7-373
DD
o
0 0 X X X X
X X X X X X X X
ODD D D DOD
t\ 7 (j 5 4 3 2 1
X X X X X X X X
Y
DCL
EN I:>
U
M
(j
Bu. Sl~nal LII1"(') and
CodlllJ,:: That AhM'rU, the
Truf.' Valu(' 01 th,' Mpssage
NN
D
I DIWA E S I R
0 AFA T OR F E
5 4 3 2 J VDC N I Q C N
XXX J X X X X
XXX 1 X X X X
XXX '» X X X X
XX0 X X X X X
X X X X X lXX X X X X X
1 0 1 It 0 XXX 1 X X X X
X X X X X XXX II 1 X X X
E E E E E XXX II X ~ X X
5 4 3 2 1
It 1 It It It XXX 1 X X X X
o 0 0 It XXX 1 X X X X
XXXXXXXX XXX X 1 X X
X X X X XXX X XXX X X X 1
y 0
XXX X X XXX 1 X X X
y
X X X
0 1
0 .0 1 XXX
o
Y 0
o
L L L
5 4 3
0 T T T
5 4 3
S S S
5 4 3
L
2
T
2
S
2
X
X
X
X
LXXX 1 X X X X
1
T XXX 1 X X X X
1
S XXX 1 X X X X
1
APPLICATIONS
T
y
C
I
a
p
Mnemonic
Message Name
NUL
OSA
OTA
PCG
PPC
PPE
null byte
other secondary address
other talk address
primary command group
parallel poll configure
parallel poll enable
PPD
parallel poll disable
PPRI
PPR2
PPR3
PPR4
PPR5
parallel
parallel
parallel
parallel
parallel
PPR6
PPR7
PPR8
PPU
REN
RFD
RQS
SCG
SDC
SPD
SPE
SRQ
STB
parallel poll response 61
parallel poll response 7
parallel poll response 8
parallel poll unconfigure
remote enable
ready for data
request service
secondary command group
selected device clear
serial poll disa ble
serial poll enable
service request
status byte
TCT
TAG
UCG
UNL
UNT
take control
talk address group
universal command group
unlisten
untalk
poll
poll
poll
poll
poll
response
response
response
response
response
1
2
3
4
5
e
Bus Signal Line( s) and
Codmg That Asserts the
True Value of the Message
D
D
NN
I
I DRD A E S I R
o
0 AFA TOR F E
8 7 6 5 4 3 2 1 VDC N I Q C N
xxx
M
DD
M
M
M
SE
(OSA = SCG " MSA)
AD (OTA = TAG" MTA)
(PCG = ACG V UCG V LAG V TAG)
-
(Note 6)
M
M
(Note 7)
M
AC Y 0 0 0 0
0 I
SEY
0SPPP
321
SEY
DDDD
4 3 2 1
U
U
(Note 10)
U.
U
U
V
M
U
U
(Note 9)
U
M
M
M
M
U
M
(Notes 8, 9)
M
M
M
M
M
(Note 11)
XXXIXXXX
STXXXXXXXI
STXXXXXX1X
STXXXXXIXX
STXXXX1XXX
STXXXIXXXX
AC Y 0 0 0 0 I 0 0
UC Y 0 0
0 0 1
UC Y 0 0 1 I 0 0 0
ST XXXXXXXX
STSXSSSSSS
8
654 3 2 I
AC Y 0 0 0 I 0 0 1
AD Y 1 0 X X X X X
UC Y 0 0
X X X X
AD Y 0
AD Y
o
X X X X X
XXX 1 X X X X
XXXIXXXX
STXXIXXXXX
STX
XXXXXX
ST 1 X X X X X X X
UC Y 0 0 1 0 1 0 I
UC X X X X X X X X
HS X X X X X X X X
ST X
XXXXXX
SEYIIXXXXX
U
U
(Note 10)
0 0 0 0 0 0 0 0
XXX 1
XXX 1
X X X
XXX
X X X
X X X
XXX
XXX
XXX 1
XXX
XXX
XXX
XXX
XXX
X0X
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
1
1
X
X
fI
X
0
I
X X X
X X X
X X X
1 X X X
X X X X
X X X 1
X X X X
X X X X
X X X X
XXXX
X X X X
X X X X
X 1 X X
X X X X
X
X
X
X
X
X
X
X
X X
X
X
X
X
X
X
X
X
X
X
The 1/0 coding on ATN when sent concurrent with multiline messages has been added to this revision for interpretive convenience.
NOTES:
(I) DI-D8 specify the device dependent data bits.
(2) EI-E8 speCIfy the device dependent code used to
indicate the EOS message.
(3) LI-L5 specify the device dependent bits of the
device's listen address.
(4) TI-T5 specify the device dependent bits of the
device's tal k address.
(5) SI-S5 specify the device dependent bits of the device's secondary address.
(6) S specifies the sense of the PPR,
8
Hesponse
II
1
P1-P3 specify the PPR message to be sent when a parallel poll is executed.
7-374
P3
P2
PI
8
PPR Message
PPRI
PPR8
(7) DI-D4 specify don't-care bits that shall not be
decoded by the receiving device. It.is recommended
that all zeroes be sent.
. (8) SI-86, 88 specify the device dependent status.
(0107 is used for the RQS message.)
(9) The source of the message on the ATN line is
always the C function, whereas the messages on the
DID and EO! lines are enabled by the T function
(10) The source of the messages on the ATN and EO!
lines is always the C' function, whereas the SOurce of
the mt'ssages on the DIO lines is always the PP function.
(11) This code is provided for system use, see 6.3.
AFN-0138OA
inter '
APPLICATION
NOTE
AP-166
October 1983
cI> INTEL CORPORATION, 1983
ORDER NUMBER:
7-375
2~32-o01
"
AP-166
INTRODUCTION
The first section of this note presents an overview of IEEE
488 (GPIB). The second section introduces the Intel~
GPIB component family. A detailed explanation of the
8291 A follows. Finally, some application examples using
the component family are presented.
This application note explains the Intel~ 829lA GPIB
(General Purpose Interface Bus) Talker/ Listener as a
component, and shows its use in GPIB interface design
tasks.
DEVICE A
ABLE TO
TALK, LISTEN,
AND
CONTROL
f
~
DATA BUS
(-
(e.g. calculator)
DEVICE B
ABLE TO
TALK AND
LISTEN
--.:.....-
(e.g. digital
multimeter)
DATA BYTE
TRANSFER
CONTROL
(10- t-DEVICEC
ONlY ABLE
TO LISTEN
-'-
(e.g. signal
generator)
DEVICED
ONLY ABLE
TO TALK
( ... --, -...V
GENERAL
INTERFACE
MANAGEMENT
-
(e.g. counter)
} DIO 1 ... 8
Data Input/Output
DAV
Data Available
NRFD
NDAC
Nol Ready lor Data
Not Data Accepted
IFC
ATN
SRC
REN
Inte rlace Clear
AilenHon
Servlce Request
EOI
End or Identify
R'\mote Enable
Figure 1. Interface Capa'1l11tles and Bus Structure
7-376
230832-001
AP-166
ATN (attention) is used.by the Controller to indicate that
it (the controller) has access to the GPIB and that its
output on the data lines is to be interpreted as a
command. ATN is also used by the controller along with
EOI to indicate a parallel poll.
OVERVIEW OF IEEE 488/GPIB
The GPIB is a parallel interface bus with an asynchronous interlocking data exchange handshake mechanism. It is designed to provide a common communication
interface among devices over a maximium distance of 20
meters at a maximum speed of I Mbps. Up to 15 devices
may be connected together. The asynchronous interlocking handshake dispenses with a common synchronization
clock, and allows intercommunication among devices
capable of running at different speeds. During any
transaction, the data transfer occurs at the speed of the
slowest device involved.
REN (remote enable) is used by the controller to specify
the command source of a device. A device can be issued
commands either locally through its front panel or by the
controller.
The GPIB finds use in a diversity of applications
requiring communication among digital devices over
short distances. Common examples are: programmable
instrumentation systems, computer to peripherals, etc.
EOI (end or identify) may be used by the controller as
well as a talker. A controller uses EOI along with ATN to
demand a parallel poll. Used by a talker, EOI indicates
the last byte of a data block.
The interface is completely defined in the IEEE
Std.-488-1978.
IFC, (interface clear) forces a complete GPIB interface to
the idle state. This could be considered the GPIB's
"interface reset." GPIB architecture allows for more than
one controller to be connected to the bus simultaneously.
Only one of these controllers may be in command at any
given time. This device is known as the controller-incharge. Control can be passed from one controller to
another. Only one among all the controllers present on a
bus can be the system controller. The system controller is
the only device allowed to drive IFC.
SRQ (service request) is used by a device to request
service from the controller.
A typical implementation consists of logical devices
which talk (talker), listen (listeners), and control GPIB
activity (controllers).
Interface Functions
The interface between any device and the bus may have a
combination of several different capabilities (called
'functions,). Among a total of ten functions defined, the
Talker, Listener, Source Handshake, Acceptor Handshake and Controller are the more common examples.
The Talker function allows a device to transmit data. The
Listener function allows reception. The Source and
Acceptor Handshakes, synchronized with the Talker and
Listener functions respectively, exchange the handshake
signals that coordinate data transfer. The Controller
function allows a device to activate the interface functions
of the various devices through commands. Other interface
functions are: Service request, 'Remote local, Parallel
poll, Device clear and Device trigger. Each interface may
not contain all these functions. Further, most of these
functions may be implemented to various levels (called
'subsets,) of capability. Thus, the overall capability of an
interface may be tailored to the needs of the communicating device.
Electrical Signal Lines
As shown in Figure I, the G PIB is composed of eight data
lines (D08-DOI), five interface management lines
(lFC, ATN, SRQ, REN, EOI), and three transfer control
lines (DAV, NRFD, NDAC).
The eight data lines are used to transfer data and
commands from one device to another with the help of
the management and, control lines. Each of the five
interface management lines has a specific function.
lhlnsfer Control Lines
The transfer control lines conduct the asynchronous
interlocking three-wire handshake.
DAV (data valid) is driven by a talker and indicates that
valid data is on the bus.
NRFD (not ready for data) is driven by the listeners and
indicates that not all listeners are ready for more data.
,
NDAC (not data accepted) is used by the listeners to
indicate that not all listeners have read the GPIB data
lines yet.
The asynchronous 3-wire hand~hake flowchart is shown
in Figure 2. This is a concept fundamental to the
asynchronous nature of the GPIB and is reviewed in the
following paragraphs.
Assume that a talker is ready to start a data'transfer. At
the beginning of the handshake, NRFD is false indicating
that the listener(s) is ready for data. NDAC is true
indicating that the listener(s) has not accepted the data,
. since no data has been sent yet. The talker places data on
the data lines, waits for the required settling time, and
then indicates valid data by driving DAV true. All active
listeners drive NRFD true indicating that they are not
7-377
230832-001
inter
AP-166
SOURCE
NRFD SIGNAL LINES GOES HIGH
YES
r---...l-----, ONLY WHEN ALL ACCEPTORS ARE READY
DATA IS VALID AND MAY
NOW BE ACCEPTED
DATA IS NOT TO BE CONSIDERED
VALID AFTER THIS TIME
NO
FLOWDIAQRAM OUTLINES SEQUENCE OF EVENTS DURING TRANSFER
, OF DATA BYTE. MOR.E THAN ONE LISTENER AT A TIME CAN ACCEPT
DATA BECAUSE OF LOGICAL CONNECTION OF NRFD AND NDAC
LINES.
"
Figure 2.
Handshake Flowchart
7-378
230832-001
inter
ready for more data. They then read the data and drive
NDAC false to indicate acceptance. The talker responds
by deasserting DAY and readies itself to transfer the next
byte. The listeners respond to DAY false by driving
NDAC true. The talker can now drive the data lines with
a new data byte and wait for NRFD to be false to startthe
next handshake cycle.
Bus Commands
When ATN and DAY are true data patterns which have
been placed by the controller on the GPIB, they are
interpreted as commands by the other devices on the
interface. The GPIB standard contains a repertory of
commands'such as MTA (My Talk Address), MSA (My
Secondary Address), SPE (Serial Poll Enable), etc. All
other patterns in conjunction with ATN and DAY are
classified as undefined commands and their meaning is
user-dependent.
INTEL'S® GPIB COMPONENTS
The logic designer implementing a GPIB interface has, in
the past, been faced with a difficult and complex discrete
logic design. Advances in LSI technology have produced
sophisticated microprocessor and peripheral devices
which combine to red uce this once complex interface task
to a system consisting of a small set of integrated circuits
and some software drivers. A microprocessor hardware/
software solution and a high-level language source code
provide an additional benefit in end-product maintenance. Product changes ~re a simple matter of revising
the product software. Field changes are as easy as
exchanging EPROMS.
Intel® has provided an LSI solution to GPIB interfacing
with a talkerflistener device (829IA), a controller device
(8292), and a transceiver (8293). An interface with all
capabilities except for the controller function can be built
with an 829lA and a pair of 8293's. The addition of the
8292 produces a complete interface. Since most devices in
a GPIB system will not have the controller function
capability, this modular approach provides the least cost
to the majority of interface designs.
Addressing Techniques
To allow the controller to issue commands selectively to
specific devices, three types of addressing exist on the
GPIB: talk only/listen only (ton/Ion), primary, and
secondary.
Overview of the 8291 A
GPIB Talker/Listener
Ton/Ion is a method where the ability of the GPIB
interface to talk or listen is determined. by the device and
not by the GPIB controller. With this method, fixed roles
can be easily designated in simple. systems where reassignment is not necessary. This is appropriate and convenient
for certain applications. For example, a logic analyzer
might be interfaced via the GPIB to a line printer in order
to document some type of failure. In this case, the line
printer simply listens to the logic analyzer, which is a
talker.
The Intel® 8291A GPIB Talker/Listener operates over a
clock range of I to 8 MHz and is compatible'with the
M CS-85, iAPX-86, and 8051 families of microprocessors.
A detailed description of the 829lA is given in the data
sheet.
The 8291A implements the following functions: Source
Handshake (SH), Acceptor Handshake (AH), Talker
Extended (TE), Service Request (SRQ), Listener Extended (LE)., Remote/Local (RL), Parallel Poll (PP2),
Device Clear (DC), and Device Trigger (DTj.
The controller addresses devices through three commands, MTA (my talk address),MLA (my listen address),
and MSA (my secondary address). The device address is
imbedded in the command bit pattern. The device whose
address matches the imbedded pattern is enabled. Some
devices may have the same logical talk and listen
addresses. This is allowable since the talker and listener
are separate functions. However, two of the same functions cannot have the same address.
Current states of the 8291A can' be determined by
examining the device's status read registers. In addition,
the 8291A s;ontains 8 write registers. These registers are
shown in Figure 3. The three register select pins RS3RSO are used to select the desired register.
In primary addressing, a device is enabled to talk (listen)
by receiving the MTA (MLA) message.
Secondary addressing extends the address field from 5 to
10 bits by allowing an additional byte. This '!'ing kit 'and thus shares the same I/O and memory
addresses. This system uses the same downlo~d software
to transfer object files from Intel development systems.
1\vo Software Drivers
Two software drivers were developed to demonstrate a
ton/Ion e,nviromnent. These two programs (BOARD I
and BOARD 2) are contained in Appendix 2.
In this example, one of the systems (BOARD I) initially is
programmed in talk-only mode and synchronization is
achieved by waiting for the 'listening board to become
active. This is sensed by the lack of a GPIB error since a
condition of no active listener produces an ERR status
condition. Board 1 upon detecting the presence of an
active listener transmitts a block of 100 bytes from a'
PROM memory across the bus. The second system
(BOARD 2) receives this data and stores it in a buffer,
EOI is sent true by the talker (BOARD I) with the last
byte of data. Upon detection of Eo!, BOARD 2 switches
to the talk only mode while BOARD 1 upon terminal
count switches to the listen only mode. BOARD 2 then
detects'the presence of an active listener and transmitts
the contents of its buffer back to BOARD 1 which stores
this data in the buffer. EOI again is sent with the last byte
and BOARD 2 switches back to liste~-only. BOARD 1
upon detecting EOI then compares the contents of its
buffer with the contents of its PROM to ensure that no
data transmission errors occured. The process then
repeats itself.
8291A with HP 9835A
An example of the 8291 A used in conjunction with a bus
controller is also included in this application note. In this
example, the 8291 A system used in previo'us experiments
was connected via the GPIB to a Hewlett-Packard 9835A
desktop computer. This computer contains, in additioh
to a GPIB interface, a black and white CRT, keyboard,
tape drive for high quality data cassettes, an<\ a calculator
type printer: The software for the HP 9835A is shown in
Appendix 3. The 'user should refer to the operation manuals for the HP 9835A for information on the features
and programming methods for the HP 9835A.
In this example, the 8292 was removed from its socket
and the OPTA and OPTB pins of the 'two 8293, transceiver reconfigured to modes 0 and 1. Optionally, the
mode pins could have been left wired for modes 21\nd 3
and the 8292 left in its socket with its SYC pin wired to
grolJnd. This would have produced the same effect.
The first action performed is sending IFC. Generally, this
is done when a controller first comes'on line. This pulse is
at least 100 us in duration as specified by the IEEE-488
~tandard.
The software checks to see if active listene~ are on, line.
For dem.onstratiori purposes, the, HP 9835A will flag the
operator to indicate that listeners are on line.
The HP 9835A then configures and performs a Parallel
poll (PPOL). The parallel poll indicates 1 bit'of statl,JS of
each device in a group of up to 8 devices. Such information cOl,Jld be used by an application program' to determine whether optioilal devices are part of a sYstem configuration. Such optional devices might include mass
storage devices, printers, etc. where the application software for the controller might need to format data to
match each type of device. Once the PPOL sequence is
finished, the HP ?835A offers the user the opportunity to
execute user commands from the keyboa~d. At this time
the HP 9835A sits in a loop waiting for an SRQ condition. When the operator !pts a key on the keyboard, the
HP 9835A processor is interrupted and vectors to a
service routine where the key is read and the appropriate
routine is executed. The HP 9835A will then return to the
loop checking for SRQ tr~e. For this application, the
valid keys are G,D,R,H,and X. Pressing the "G" key
causes the GET command to be sent across the bus. A
message to this effect is printed in the CRT and the HP
9835A returns. The "D" key causes the SDC message to
be ~ent with the 8291 A being the addressed device. Again,
an appropriate message is output on th HP 9835A CRT.
The "R" key causes the GTL message to be sent. The CRT
displays "REMOTE MESSAGE SENT." The "H" key
causes a menu to be displayed on the HP 9835A CRT
screen. This menu lists the allowed commands and their
functions. NO GPIB commands are sent. The "X" key
allows the operator to send one line of data across the
bus. The line of data is terminated by a carriage \'Cturn
Ilnd line feed produced. by pressing the "CONTINUE"
key on the HP 9835A.
The characters are stored in the sequence entered into a
bJlffer whose maximum size is 80 characters. Pressing the
"CONTINUE" key terminates stori~ characters in the
array and all characters including the carriage return and
line feed are sent. EOI is then sent true with a false byte of
OOH. This false byte is ,due to the 1975 standard which
allows asyncronous sendi/lg and reception of EOI. (The
8291 A supports t~e later 1978 standard which eliminates
this false byte).
After any key command is serviced control returns to the
loop which ,checks for SRQ I\ctive. Shquld SRQ be
active, then the keyboard ,interrupt is ,disabled and a
me~sage printed to i~dicate that SRQ has b~en .t:eceived
true. '
The controller .t~en petforms a parallel poll.
This is an example of how parallel poll may be used to
23083~-OO1
AP-166
quickly check which group of devices contains a device
sending SRQ. The eight devices in a group would, of
course, have software drivers which allow a true response
to a PPOL if that device is currently driving SRQ true.
This would be a valuable method of isolation of the SRQ
source in a system with a large number of devices. In this
application program, only the response from the 8291A
is of concern and only the 8291 A's response is considered.
It does, however, demonstrate the technique employed. If
a true response from the 8291A is detecte~, then a message to this effect is printed on the HP .9835A CRT
screen. From this process, the controller has identified the
device requesting service and will use a serial poll(SPOL)
to determine the reason for the service request. This
method of using PPOL is not specifically defined by the
IEEE-488 standard but is a use of the resources provided.
The controller software then prints a message to indicate
that it is about to perform a serial poll. This serial poll will
return to the controller the current status of the 8291A
and clear the service request. The status byte received is
then printed on the CRT screen of the HP 9835A. One of
the 8291A status bits indicates that the 8291A system has
a field (on line or less) of data to transfer to the HP
9835A. If this bit is set, then the HP 9835A addresses the
8291A system to talk. The data is sent by the 8291A
system is then printed on the CRT screen of the HP
9835A. The HP 9835 then enables the keyboard interrupts
and goes into its SRQ checking loop.
Appendix 4 contains the software for the 8291A system
which is connected to the HP 9835A via the GPIB. This
software throws away the first byte of data it receives
since this transfer was used by the HP 9835A to test when
the 8291A system came on line.
Next, both status registers are read and stored in the two
variable STAT I and STAT 2. It is necessary to store the
status since reading the status registers clears the status
bits.
Initially, six status bits are evaluated (END, GET, CPT,
DEC, REM C, ADSC). Some of these conditions require
that additional status bits be evaluated.
if END is true, . then the 8291A system has received a
block from the HP 9835A and the contents of a buffer is
printed on the CRT screen. Next, the CPT bit is checked.
PPC and PPE are the only valid undefined commands in
this example.
Address Status Change (ADSC) is checked to see if the
8291A has been addressed or unaddressed by the controller. If ADSC is false, then the software checks the
keyboard at the CRT terminal. If ADSC is se\, then the
TA and LA bits are read and evaluated to determine
whether the 8291 A has been addressed to talk or listen.
The DMA controller is set to start transfers at the start of
the character buffer and the type of transfer is determined
by whether the 8291A is in TADS or LADS. We only
need to set up the D MA controller since the transfers will
be transparent to the system processor. The keyboard
from the CRT terminal is then checked. If a key as been
hit, then this character is stored in the character buffer
and the buffer printer set to the next character location.
This process repeats until the received character is a line
feed. The line feed is echoed to the CRT, the serial poll
status byte updated and the SRQ line driven true. This
allows the 8291A system to store up to one line of characters before requesting a transfer to the controller. Recall
that upon receiving an SRQ, the controller will perform a
serial poll and subsequently address the 8291A to talk.
The 8291 A system then goes back to reading the status
register thus repeating the process.
CONCLUSION
This application note has shown a basic method to view
the IEEE 488 bus, when used in conjunction with Intel's®
8291 A.
The main reference for GPIB questions is the IEEE
Standard 488 - 1978. Reference 8291 A's data sheet for
detailed information on it.
Additional Intel® GPIB products include iSBX-488,
which is a multimode board consisting of the 8291A,
8292, and 8293.
REFERENCES
8291A Data Sheet
8292 Data Sheet
8293 Data Sheet
Application Note #66 "Using the 8292 GPIB Controller"
PLM-86 User Manual
HP 9835A User's Manual
IEEE-488-1978 Standard
Next, the GET bit is examined and if true, the CRT
screen connected to the serial channel on the 8291 A
system prints a message to indicate that the trigger command has been received. A similar process occurs with
the DEC and REMC status bits.
7-387
230832-001
inter
AP-166
APPENDIX 1
SYSTEM BLOCK DIAGRAM
WITH 8088
7-388
230832-001
AP-166
APPENDIX 2
SOFTWARE DRIVERS FOR BLOCK DATA TRANSFER
PLlM-86 Cot1PILER
BOARD 1
ISIS-II PLlt1-86 ',11. 1 COMPILAT10N OF MODULE BOARD I
OBJECT MODULE PLACED W
Fl
BRDt
DBw'
COMP ILER INVOKED BY.
PLMEl6.
Fl'
BRD1.
SRC SYMBOLS MEDIUM
1*
1*
/*
1*
III1*
1*
1*
1*
I"
1*
1*
1*
1*
1*
1*
. BOARD 1 TPT PROGRAt1
*1
THIS BOARD TAL"S TO THE OTHER BOARD BY *1
TRANSFERRING A BLOC\<. OF DATA VIA THE 8237 ""I
COUPLED IJI1H THE. 8291A
THE 8291A IS PROGRAM- *1
MED TO SEND EOI 14HEN RECOGNIZING THE LAST
*1
DATA ByTE'S BIT PATTERN
WHILE DATA IS BEING *1
TRANSFERRED. THE PROCESSOR PERFORMS
I/O READS *1
OF THE 8237 CC'Jtn REGIS1ERS TO SIMULATE. BUS
*1
ACTIVITy, AND TO DE.l~RMINE WHEN TO TURN THE
*1
LINE AROUND. AFTER THE 8237 HAS REACHED
11-1
rERMINAL COUNT. THE 8291A IS PROGRAMMED TO
*1
THE LtSTENER STATE AND WAITS FOR THE SLOCK
*1
TO BE TRANSMITTED ~ACK FROM THE SECOND BOARD. *1
THIS Ii"'TA IS PLACED IN A SECOND BIJFFER AND
*1
ITS CONTENTS cor1PARED WITH THE ORIGINAL DATA *1
TO CHECK FOR INTERFACE INTEGRITY.
*1
BOARD1:
DO.
1* PROCEDURES *1
2
:3
1
2
4
5
6
7
..:
:3
2
2
CO:
PROCEDURE (XXX)
DECLARE XXX BYTE.
SER$STAT LITERALLY
'OFFF2H'.
SER$DATA LITERALLY
'OFFFOH'.
TXRDi
LITERALLY
'OlH'.
DO IJHILE (INPUT
(SER$STATl AND TXRDY)
END;
= XXX;
OUTPUT (SER$DATA)
END CO;
, •
8
9
<:>
T? 100 XFERS
*1
DE.CLARE
DMA$WRD$TALM (2' WORD
DMA$WRO$LSTN(2) WORD
AT
AT
(I@DMA$ADR$TALK).
(@DMA$ADR$LSTN) ;
i* 8291A PORT ADDRESSES *1
16
DECLARE
PORT$OUT
PORT$IN
STATUS$l.
STATUS$2
ADDR$STATUS
COMMAND$t10D
ADDR$O
EOS$REG
L1TERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
7-390
'OFFCOH' ,
'OFFCOH'
'OFFC1H',
'OFFC2H' •
'OFFC4H' ,
'OFFC5H' ,
'OFFC6H' ,
'OFFC7H' ,
1* DATA OUT*I
I*INTR STAT 2*1
1* INTR STAT 2 *1
I~CMD
1*
PASS THRU *1
EOS REGISTER *1
230832-001
inter
AP-166
I. 8291A COMMAND
PL/M-B6 COMPILER
- DATA BYTES *1
BOARDl
DECL.ARE,
17
'BSH'.
END$EOI
LITERALLY
'lOH'.
ONE LITERALLV
paN LITERALLV
'OOH'.
'02H'.
RESET
LITERALLV
'OOH'.
CLEAR
L TTERALL V
'lOH',
DMA$REG.L LITERALLY
L1t1A$REQ$ T L I TERALL V
'20H',
'BOH',
MOD1$TO
LITERALLV
'40H'.
MOD1$LO
LITERALLV
'OOH'.
EOS L ITER ALL V
'23Hi,
PRESCALER LITERALLY
'OA4H'.
HIGH$SPEED LITERALLY
'OFFFFH' •
O~A'y
LITERALLY
XYZ BYTE,
MATCH
I~ORD.
'02H'.
BO
LITERALLY
BI
L [ rr.:RALL 'y
'OlH'
'04H',
ERR LITERALLY
J
1* CODE BEGINS *1
lS
START91,
OUTPUT
(STATUS$2)
=CLEAR.
'* SHUT-OFF OMA REO BITS TO *1
1* PREVENT EXTRA OMA REOS*I
I*FROM S291A
*/
1* MANIPlJ ... ATE OMA pOORESS VARIABLES *1
OMA$AOR $ r AL K
= (@BUFF1) ;
DMA$AOR$LSTN
=(@BUFF2).
DMA$WRO$TALK(l)=SHL (DMA$WRD$TALK(l). 4);
Ot1A$WRD$TALK(0)=DMASI4RDSTALK (0) + OMASWRDSTALK (1)1
OMASI~RO$LSTN ( 1 ) =SHL (DMASWRO$LSTN (1),
4) I
Dt1A$WRD$LSTN(O)=DMASWRDSLSTN (0) +DMA$WRDSLSTN' (1)1
19
20
21
22
23
24
[NrT371
25
1* IIHT 8237 FOR TALKER FUNCTIONS *1
26
27
2B
1
1
'1
29
30
31
32
33
PL/M-86 COMPILER
OUTPUT
(CLEAR$FF)
OUTPUT
(CMO$37)
OUTPUT
(SET$ti0DE )
OUTPUT
(SET$MASK)
OUTPUT
(START$O.LO)
OMA$14RO$TALK (0)
bUTPUT
(START$O$HI)
OUTPUT
\O$COUNT~LO)
OUTPUT
(O$COUNT$HI)
1* INIT 82qlA FOR TALKER
=CLEARI/* TOGGLE MASTER CLEAR *1
=NORM$TIMEI
=RO$TRANSFER;
=CLEARI
=OMA$WRD$TALK (OIl
=SHR (DriA$WAD$TALK (0). BII
=DMA$WRD$TALK (OIl
=TC$L021
=TC$HI2;
FUNCTIONS *1
BOARDS,
. 7-391
230832-001
AP-166
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
34
35
36
37
38
39
40
41
42
43
44
45
46
47
1
DO ~~HILE (INPUT (STATUS$l) AND BO)
ENOl
1* WAIT FOR BO INTR *1
OUTPUT (PORTSOUT> = OAAH,
1
DO
1
2
=0,
(INPUT
(STATUS$1) AND ERR) = ERR,
DO WHILE (INPUT (STATUS$l) AND BO) = ~;
END,
1* WAIT FOR BO INTR *1
OUTPUT (PORT$OUT) =OAAH,
END,
2
3
2
2
~~HILE
OUTPUT
48
( :, TATUSS2)
=D~lA$REGI$T,
DO WHILE ( It~PUT (Ct1D$:J7)
1* WAIT FOR TC =
*1
END;
49
50
(EOS$REG)
=EOS,
=END$EOI, 1* EOI ON EOS SENT *1
(COt1MANDSMOD)
(ADDR$STATUS)
=MODl STO, 1* TALK ONLY *1
(COt1MAt~D$MOD )
=PRESCALER,
=HIGH$SPEED,
( COt1MAND$t10D )
(COMMANO$MOD)
=PON,
°
2
.'...
ENABLE Dt1A REGS *1
<>
AND TC)
TC,
INIT37L,
51
OUTPUT
(STATUS$2)
=CLEAR,
1*
DISABLE DMA REGS *1
1* INIT 8237 FOR L1STENER FUNCTIONS *1
52
53
54
55
56
57
58
OUTPUT (CLEAR$FF) O=CLEAR; I;> TOGGLE MASTER RESET *1
OUTPUT (Ct1D$37)
=NORM$TIME,
OUTPUT (SET$MODEl =WR$TRANSFER,
OUTPUT (SET$MASK) '=CLEAR;
=DMASWRDSLSl N (0);
O'JTPUT (Si ARTSOSLO I
DMASWRDSLSTN (0)
=SHR (DMASWRD1>LSTN (0), 8);
1
2
1
1
1
1
1
OUTPUT
59
60
(START $OSHI)
=DMASWROSLSTN (0);
OUTPUT W,*COUNHiLO)
=TC$L01,
OUTPUT (O$COUNTSHI )
=TCSHll;
1* INIT 82qlA FOR LISTENER FUNCTIONS
OUTPUT
OUTPUT
OUTPUT
61
62
63
64
65
66
2
(COMMAND$MOD)
(AODRSSTATUS)
(COMMAND$t10D)
=RESET,
=t10Dl$LO;
=PON,
/*
DO WHILE (INPUT (STATUS$1) .. AND B1)
END;
1* I~AIT FOR BI INTR .,./
XYZ
INPUT (PORT$IN);
*1
LISTEN ONLY *1
=0,
67
OUTPUT
68
DO WHILE (INPUT (STATUS$l) AND DNE)<::'1* WAIT FOR EDT RECEIVED *1
(STATUS$2)
=DMA$REQ$L,
7-392
1*
ENABLE DMA REGS
*1
DNE;
230832"()01
AP-166
PL/M-86 COMPILER
BCJARL'
CMPBLI'.S
70
'*
rC"1PARE THE nlo BIJFFERS CONTENTS *1
t1ATCH=CMPB
IF t1ATCH
71
:i'
73
74
75
(@BUFFL
SE~m
@BUFF2,
100»)
OKAY THEN GOTO START91)
ERROR MESSAGE IN BUFFER 3
*1
DO 1=0 TO 16)
I
2
2
CALL CO
(BUFF 3
(1)
»)
END.
GOTO START91,
76
77
MODULE INFORMATIONCODE AREA SIZE
CONSTANT AREA SIZE
VARIABLE AREA SIZE
MAXIMUM STACK SIZE
243 LINES READ
o PROGRAM ERROR (8)
END OF PLtr1-86
=OlDBH
..0075H
=0070H
=0006H
4750
1170
1120
6D
COMPILATION
7-393
230832-001
inter
AP-166'
PL/M-86 Cot1P ILER
BOARD2
IS1S-1 I PL1r1-86 VI. 1 COf1P ILATION OF MODULE BOARD2
OBJECT t10DULE PLACED IN : F 1: BRD2, OB')
PLM86
:F1:
BRD2, SRC
COMPILER INVOKED BY:
I~ BOARD 2 TPT PROGRAM
*1
1*
*1
1* THIS BOARD LISTENS TO THE OTHER BOARD (1)
*1
1* AND Dt1A'S DATA INTO A BUFFER, ,,,HILE WAITING *1
1* FOR THE Et,m ltHERRUPT BIT TO BECOt1E ACTIVE *1
;<> UPON END ACTIVE. THE DATA IN THE BUFFER IS *1
1* SENT ~ACK TO THE FIRST BOARD VIA THE GPID
*1
1* ,~HEN THE BLOCK IS FINISHED THE 8291A IS *1
1* PROGRAt1MED BACK INTO THE LISTENER MODE
*1
BOARD2
DO.
1* 8237 PORT ADDRESSES *1
2
DECLARE
CLEAR$FF
START$O$Lo
START$O$HI
O$COUNT$LO
O$COUNT$HI
SET$MODE
Cf10$37
SEHMASK
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
l. ITER ALl. Y
1* 8237 CUMMAND
3
-
DATA BYTES
,I*MASTER CLEAR *1
*1
DECLARE,
RD$TRANSFER
LITERALLY
WR$TRANSFER
LITERALLY
ADDR$lA
LITERALl.Y
ADDR$!B
LITERALLY
NORI'1$TIME
LITERALLY
TC$UH
LITERALLY
TC$HI!
LITERALL.Y
TC$L02
LITERALLY
TC$HI2
LITERALLY
TC
l.lTERALLY
I~
4
'OFFDDH'.
'OFFDOH' ,
'OFFDOH' ,
'OFFD1H' ,
'OFFDIH' ,
'OFFDBH' ,
'OFFD8H' •
'OFFDFH' ,
8291A
'48H',
'44H',
'DOH',
'OIH',
'20H'
~
'OFFH' ,
'OOH',
'99D',
'OOH',
'01H' ,
PORT ADDRESSES *1
DECLARE
PORT$OUT
PORHIt.!
STATUS$!
STA1US$2
ADDR$STATUS
Cot1t1AND$t10D
LITERALl.Y
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
7-394
'OFFCOH' ,
'OFFCOH',I* DATA IN *1
'OFFCIH'. 1* INTR STAT 1 *1
'OFFC2H', 1* INTR STAT 2 *1
'OFFC4H', 1* ADDR STAT
*1
'OFFC5H', 1* Ct1D PASS THRU 'I
ONE;
230832-001
,~
AP-166
PUM--8t>
COMPILER
BOARD2
END;
23
24
INIT37Ti
1* I~IT 8237 FOR TALKER FUNCTION
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
25
26
~!7
28
29
30
31
32
1*
']7
38
*1
(STATUS$2) =CLEAR;
1* CLEAR 8291A DRQ *1
(CLEAR$FF) "'CLEAR;
(CMD$37)
=NORM$TIt1E;
(SET$MODE) "'RD$TRANSFER,
1* BLOCK XFER MODE *1
(SET$MASK)
=CLEAR;
(STAR1-$O$LO)
=ADDR$1A;
(START$O$HI)
=ADDR$lB;
(O$COUNT$LO)
=TC$L02;
(O$COUNT$HI)
=TC$HI2;
INIT 8291A
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
33
34
35
36
FOR TALKER FUNCTION
*1
(EOS$REG)
"'EOS; ,
(COMMANO$MOD)
=END$EOI;I* EOI ON EOS SENT
(ADDR$STATUS)
=t10Dl$TO . 1* TALK ONLY *1
=PRESCALER .
\ COMMAt~D$MOD )
(COMt1AND$t10D)
"'HIGH$SPEED;
(COMMAND$MOD)
=PON .
1
2
DO WHILE (INPUT (STATUS$1)
AND BO)
END;
1* ~~AIT FOR BO INTR
*1
OUTPUT (PORT$OUT)
=OAAH,
42
1
DO
43
2
3
39
40
41
44
45
40
2,.,
~
=0;
OUTPUl
(8TATUS$2)
=DMA$REG$T;
1* WAIT FOR TC=O *1
DO ~~HTLE
END;
1
2
( INPUT
(Ct1D$37)
AND TC)
<>
TC;
GOTO START91;
50
51
*1
~,HILE
(INPUT
(STATUS$!) AND ERR)
=ERR;
DO ~~HILE
(INPUT (STATUS$1)
AND BO)
=0;
END;
1* ~.AIT FOR BO INTR *1
OUTPUT (PORT$OUT)
=OAAH .
END;
47
48
49
I.
END .
MODULE INr=ORMATION
CODE ARE:A SHE
CONSTANT AREA SIZE
VARIABLE AREA SIZE
MAXIMUM STACK SIZE
152 LI NES READ
o PROGRAM ERROR (S)
=0122H
=OOOOH
=0001H
"'OOOOH
2900
00
10
00
7-396
230832-001
inter
AP-166
APPENDIX 3
SOFTWARE FOR HP 9835A
::;Er'iIi IN
CLEAF.:
20
ABORTIO 7
30
F.:Et1 FOF.:CE E
RROF.:S IJt-nIL LIST
ENERS ACTIVE
40 Freer-r-:
OUT
PUT 704 lISING "#
,K";"B'"
50 Chks1,st:
ST
ATlIS 7~S1,o_1,l,Sta
1,2, St-a1,3, St,0.1,4
60
Err=S~at2 A
tHI 1
7(1
IF Er-r-=1 TH
EN GOTO Fr-':-Eor-r'
80
PF.: HH CH~:$ (
12) , .. L I STEt-~EF.:S A
10
~:Et'i
S t. 0_ t. 4
TE~:FACE
17(1
Sr-':::t=I: I t-~At-m (
("-~ t 0_ t 1 ' ....
t9'-0::.1
1 :::(1
IF Sr-q=(1 TH
EN G[I T CI k Eo:' .;. n
200
D"
21~3
PRINT "SEND
I NG PAF.:ALLEL POL
L RESPONSE MESSA
GE"
220
RE~l E::-~ECUT I
NG PARALLEL POLL
230 Ppo11bY1,e=P
POLL(7)
24(1 PRINT "PARA
LLEL POLL E\'TE =
.. ; p p If1 1 b -i t. Eo .
25(1 FtF.~ I t.iT
RE ON LINE ..
'3(1
REt,! COt-~F I GU
RE PF'OLL
100 PPOLL COt-F- =
GURE 704;" (1 (1 (HE :
~:"0
PF.: Hn CHF.:~ (
F.:EC:EI1·.·'E
12).~ USF.:G~
II
___ _
---------------"
..
2E,e Ppcll 1 b-it e=B
I NAt·HI '( p pol 1 ~:n-' 1, Eo ,
1 1(1
I
r-eSF:'c't"1::-e
Dr,
270
b 1t
4
12~3
PRIt-n CHE",,;.
12),"PARALLEL PO
LL COt~F I GURErl"
1 :;:{1 F.: Et'! ENAE: L E
KE\'BOAF.:II I t'iTEF.:F.:U
PT
14(1 PR an .. COt'1t'1
AND = ?
(HIT
---H'-' FOR LIST)"
115(1 Ke-ien:
ON K
ED GOSUE: 610
160 STATlIS 7;S1,
at 1, St-o..1,2, Stat;::,
e=(1
IF PF='O 1 1 b-:d.
THEH GOTD ;:'::'
2'31
2:::0
PR Hn .. SR ,-.
NOT FF.:Ot'l 82'31"
2::: 1 P F.: an ." C(1 ~-1 r'~
AND =?
(HIT
"H'- FOF.: LIST)"
,290
GOTO Ke~"-en
30(1 P8291:
PF.: H~
T " SF.:O IS FF.:ON N
(:C: E:2'~1 ••• THE
ENTERPF.: lSE"
;:: 10 PF.: Hn .. PEF.:F
7-397
230832-001
inter
AP-166
F.: 7(14
.690 PF.:INT CHF.:$(
12) , "GF.:OUP E::-::ECU
TE TF.: I GGEF SEt·n"
7f1(1
PF.: I NT
710
PF.: lNT "COt'1t'l
At·m = 0:;'
(HIT
"H'" FOP LIST)"
72(1
F.:ETUFt'i
73(1 Ilec.:
F~ESET
704
740 PRINT CHR$(
12) , "SELECT I VE II
EV I CE CLEAF SEt·n
OF.:t'l HH; SEF: I AL PO
LL TO GET' STATI.:.IS
"
:32f1
STATU::; 7f14;
.St.Cl,t,
330 PRINT CHR$(
12)., "St-o.t-us
S t. (I, t.
= ";
52~:1
IF D}::fer'\~3
THE t·~ I:; C1 T Cr F.~ (~. !.) tOO,
530 GOTO Ke';o'en
531 ·Rcvr·:
F~Et'l R
EADY TO Re··.'· CHAF.:
S FROM GPIB
54(1
DHl G$ [80J
550 ENTER 704 U
SING "/;,T";G$
560
PF.: I NT CHR$ (
12) , G$
570
PfU t~T "COMN
At·m = r;
(HIT
"H" FDF~ LIST)"
58(1
GOTO Keyen
590
REM INTERRlI
PT SERVICE ROUTI
NES
6~3(1
F.: Et'l GET KEY
BOAFD DATR
610 ~,lh(l.t.ke';o':
DI
t'l K$ [8(1]
f20
K$=KE:D$
6:;:(1
IF K$="G" T
HEN GOTD G.:.t.
64(1
IF K$="D" ~
HEt·~ GOTO Dec.
E.5(1
IF K$="R" ;
HEt·4 GOTO F.: e r'l
E,Et~~1
IF ~:::$=UHII HEHGOTO Help
67(1
IF K$=":~::" T
HEN Gala Xrtl i t
E.8~3 Get.:
TR I ::<:;E
"
750
7E.(1
F'F.: I t·~T".~· ..
PF.: an "COt'H"
At~D = r:J
(HIT
"H'" FCfF.: LI~:;T',
770
EETUfd'i
780 Rer'!:
LOCAL
704
790
PRINT CHF$(
12),"REMOTE MESS
AGE SENT"
800 PRINT·"
810
PRINT "CO~l~l
AND = r;.
(HIT
"H'" FOR LIST)"
82(1
RETURN
830 Help:
PRINT
CHF.:$1:12)
840
PRINT" @@@
@ OPERATOR ALLO~,J
ABLE COt'lMAt'HlS @(~
II
II
@@ "
850 PRINT" hit.
r·es.ult.··
ke')"
PRINT "
860
G
Send GET r(1
es,$o.se."
870
7-398
F'F.: I NT"
It
230832-001
inter
880
-..
AP-166
PRINT"
P
Se r. d ~: E t'1.· "L
940 :x:I"'!i t:
II Hl A
$[80J
950 PR It~T CHF.:$ (
12:1, "Erlter' dO.tll
t CI s.er..::1 o.nd hit
CONTINUE"
9':,0 .INPUT A$
970 OUTF'UT 704;
AS
971 EOI 1;0
9:::0 PRINT "COt1t'l
AtHI
?
(HIT
"H'" FOR LIST)"
9'30
RETUF.:t·.j
.
1000 EtHI
OC l")e::.so.ge"
89(1
(I
PF.: I NT"
>::
Xfill ts. key!::
o. r' d ; n r.' u t t
(I
:::
:2
91 "
9(1(1
PRIt~T"
H
Pr·ints. thi
s· table"
910 PRINT" "
920 PRINT" •••
gel Ilheo.d, TF.:Y IT
=
I "
9:30
RETUF.:N
7-399
230832-001
inter
APPENDIX 4
SOFTWARE FOR HP 8088/HP 9835A VIA GPIB
PL/M-86 COMPILER
HPIB
ISIS-II PL/M-86 V!. 1 COMPILATION OF MODULE HPIB
MODULE PLACED IN :F1:HPIB.OBJ
COMPILER INVOKED BY: PLMS6 :F1:HPIB.SRC LARGE
OB~ECT
1
HPIB:
1*
PARAMETER DECLARATIONS
*1
DOl
2
DECLARE
ADDR$HI
LITERALLY
'01H',
ADDR$LO
LITERALLY
'OOH',
ADSC
LITERALLY
'01H',
BI
LITERALLY
'01H',
BO
LITERALLY
'02H',
CHAR$COUNT BYTE,
CHAR
BYTE,
CHARS(SO)
BYTE,
CLEAR
LITERALLY
'90H',
CPT
LITERALLY
'SOH',
CRLF
LITERALLY
'OAH',
DEC
LITERALLY
'OSH',
DMA$ADR$LSTN
POINTER.
DMA$ADR$TALK
POINTER,
DMA$WRD$LSTN(2) WORD AT
(eDMA$ADR$LSTN),
DMA$WRDSTALK(2) WORD AT
(iDMA$ADR$TALK),
DMA$REO$L
LITERALLY
'tOH',
DMA$REO$T
LITERALLY
'20H',
DNE
LITERALLY
'lOH',
END$EOI
LITERALLY
'SSH',
EOS
LITERALLY
'O.DH"
ERR
LITERALLY
'04H',
GET
LITERALLY
'20H',
I
BYTE,
LISTEN
LITERALLY
'04H',
MLA
LITERALLY
'04H',
MODE$1
LITERALLY
'01H',
NO$DMA
LITERALLY
'OOH',
NO$RSV
LITERALLY
'OOH',
NORM$TIME
LITERALLY
'20H',
PON
LITERALLY
'OOH',
PPC
LITERALLY
'05H',
PPE$MASK
LITERALLY
'60H',
PPOLL$CNFG$FLAG LITERALLY
'OiH',
PPOLL$EN$BYTE
BYTE,
PRI$BUF(SO) BYTE AT
(@CHARS),
RD$XFER
LITERALLY
'4SH',
RESET
LITERALLY
'02H',
REMC
LITERALLY
'02H',
RSV
LITERALLY
'40H',
RXRDY
LITERALLY
'02H',
.400
230B32-001
inter
AP-166
PL/M-B6 COMPILER
HPIB
SRGS
LITERALLY
'40H',
BYTE,
STAT 1
BYTE,
STAT2
TALK
LITERALLY
'02H' ,
BYTE,
TA.OR.LA
'41H' ,
TRG
LITERALLY
TC
LITERALLY
'01H',
TC.HI
LITERALLY
'OOH' ,
TC.LO
'OFFH',
LITERALLY
TXRDY
LITERALLY
'01H' ,
BYTE,
UDC
WRSXFER
'44H',
LITERALLY
BYTE;
XYZ
1*
PORT DE<;LARATIONS
.
*1
3
DECLARE
ADDRSO
ADDRSSTATUS
CLEARSFF
CMDS37
COMMANDSMOD
COUNTSHI
COUNT.LO
CPTSREG
EOS.REG
PORTtIN
PORTSOUT
SERSDATA
SER$STAT
SET.MASK
SETSMODE
SPOLLSSTAT
STARTSHI
STAR TSLO
STATUSS1
STATUS.2
4
:5
6
7
B
1
1
1
1
1
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
'OFFC6H' ,
'OFFC4H' ,
'OFFDDH',
'OFFDBH' ,
'OFFC5H',
'OFFD1H',
'OFFD1H',
'OFFC5H',
'OFFC7H' ,
'OFFCOH' ,
'OFFCOH' ,
'OFFFOH' ,
'OFFF2H',
'OFFDFH' ,
'OFFDBH' ,
'OFFC3H' ,
'OFFDOH',
'OFFDOH',
'OFFC1H' ,
'OFFC2H';
1* crt
mellllagell l i lit *1
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
GET.MSG(l1) BYTE DATA (ODH,OAH, 'TRIGGER',OAH.ODH);
DEC.MSG(16) BYTE DATA (ODH,OAH. 'DEVICE CLEAR',OAH,ODH);
REMCSMSG(lO) BYTE DATA (ODH,OAH, 'REMOTE',ODH,OAH);
CPTSMSG(22) BYTE DATA (ODH,OAH,"UNDEF CMD RECEIVED',OAH,ODH);
HUHSMSG(l1) BYTE DATA (ODH,OAH, 'HUH ???',ODH.OAH);
1* called procedures *1
1
REGSER:
PROCEDURE;
7-401
230832-001
I
inter
AP-166
PL/M-86 COMPILER
HPIB
10
2
OUTPUT (SPOLL.STAT)-TRO;
11
12
2
3
DO WHILE (INPUT (SPOLL.STAT) AND SROS)-SROS;
END;
13
2
OUTPUT (SPOLLSSTAT)=NOSRSV;
14
2
END REOSER;
15
16
1•
2
17
18
19
20
21
22
23
24
25
2
3
2
2
1
2
3
3
2
DO WHILE (INPUT (SERSSTAT) AND TXRDY)<>TXRDYI
END;
OUTPUT (SERSDATA)=XXX;
END CO;
HUH:
PROCEDURE;
DO 1=0 TO 10;
CALL CO (HUH.MSS(I»;
END;
END HUH;
26
1
CI:
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
2
2
3
3
3
3
3
3
3
3
3
4
5
4
4
3
3
2
IF (INPUT (SER$STAT) AND RXRDY)=RXRDY THEN
DO;
1=0;
CHAR$COUNT-Ol
STORE$CHAR:
CHAR-(INPUT (SER$DATA) AND 7FH);
45
46
CO: PROCEDURE(XXX);
DECLARE
XXX
BYTEI
PROCEDURE;
CHAR$COUNT-CHAR$COUNT~ll
CALL CO CCHAR);
CHARS C1 ) -CHAR;
1=1+1 ;
IF CHAR <> CRLF THEN
DO;
DO WHILE (INPUT .CSER.STAT) AND RXRDY) <>RXRDY;
END;
SOTO STORE$CHAR;
END;
CALL REOSER;
END;
END CI;
TALK$EXEC:
2
PROCEDURE;
OUTPUT CSTATUS$2)=CLEARI
1*
manipulate address'bits for DMA controller'
*1
47
48
49
50
2
2
2
DMA$ADR$TALK=C@CHARS);
DMASWRD$TALK(1)=SHLCDMA$WRD$TALKC1).4l1
DMA$WRD.TALKCOl-DMA$WRD$TALKCO)+DMA$WRD$TALK(l);
OUTPUT (CLEAR$FF)=CLEAR;
7-402
230832-001
inter
PL/M-86 COMPILER
51
2
52
.2
:2
2
53
54
55
56
57
58
HPIS
OUTPUT
OUTPUT
OUTPUT
OUTPUT
(CMD37)-NORM.TIME.
(SET.MODE)-RD.XFER,
(SET.MASK)-CLEAR,
(START.LO)-DMA.WRD.TALK(O).
-/
DMA.WRD.TALK(0)·SHR(DMA.~RD$TALKCO),8)1
:2
2
2
2
OUTPUT (START.HI)-DMA.WRD.TALK(O)I
OUTPUT·(COUNT.LO)-CHAR.COUNTI
OUTPUT (COUNT$HI)-Ol
59
60
2
:2
OUTPUT (EOS$REQ)-EOS,
OUTPUT (COMMAND$MOD)-END.EOII
61
62
63
2
3
2
DO WHILE (INPUT (STATUS.1) AND SO)-O,
ENDI
OUTPUT (PORT.OUT)-OAAHI
64
65
66_
67
68
69
2
3
4
3
3
2
DO WHILE (INPUT (STATUS.1) AND ERR)-ERRI
DO WHILE (INPUT (STATUS.1) AND SO)-Ol
END;
OUTPUT (PORT.OUT)-OAAH.
ENDI
OUTPUT (STATUS.2)-DMA.REG.T;
70
:2
END TALK.EXEC.
71
1
72
73
74
75
76
77
78
79
:2
:2
81
82
83
84
85
:2
:2
:2
:2
:2
OUTPUT (STATUS.2)-CLEAR.
OUTPUT (CLEAR.FF)-CLEAR.
OUTPUT (CMD.37)-NORM.TIME;
OUTPUT (SET.MODE)-WR.XFER.
OUTPUT (SET.MASK)-CLEAR.
DMA.ADRSLSTN-(etHARS);
DMA.WRD$LSTN(1)-SHL(DMA$WRD.LSTN(1),4).
DMA.WRD.LSTN(0)sDMA.WRD.LSTN(0)+DMA.WRD$LSTNC1);
OUTPUT (START.LO)-DMA.WRD$(STN(O).
DMA.WRDSLSTN(0)-SHR(DMA.WRD.LSTNCO),8);
OUTPUT (START$HI)-DMA.WRD.LSTN(O).
OUTPUT (COUNT.LO)-TC.LO.
OUTPUT (COUNT.HI)-TC.HI,
OUTPUT (STATUS.:2)-DMA.REG.L;
86
2
END LISTEN.EXECI·
87
1
BB
:2
89
90
91
92
93
:2
3
3
3
:2
DO WHILE PRI$SUF(I) <>CRLFI
CALL CD (PRI.SUFr control, and in (b), for da~a.
then the entire interface can be built with a single
8291A and a pair of 8293s. (See Fig 5.) In this configura"
tion, one 8293 handles the eight data lines DIOI to DI08
and the other handles the data-byte transfer handshake
lines and general interface management lines. Both
transceivers are connected to the 8291A's ATN, and EOi,
and TIRI lines.
Talkar/li,taRar/coRtrollar
For an IEEE 488 controlJer (like the HP 85 or Tektronix
4051), the system must be able to take control of the bus,
or delegate it to another' controlJer. Such an interface
scheme can be implemented using an 8291A, an 8292, and
a pair 6f 8293s. (See Fig 6.) The arrangement is similar to
that of a talker/listener interface; One 8293 handles the
DIOI through DI08 bus data lines and the other handles
the data byte transfer handshake and general interface
management lines. The difference is that pins 26 and 27
have I:!een selected for modes 2 and 3 and several .addi-
tiona! control functions have been added. The attention
in (ATNI) lines arid attention out (ATNO) lines permit the
8292 to monitor the GPIB'S ATN line and take control of
the bus. In conjunction with the ATN line, the E0I2line is
used by the 8292 to initiate a polling sequence.
The chip is divided into nine, distinct
transceivers and each one's
characteristics are determined by
internal logic.
Lastly, the system controller line (SYC) enables the
control function. If it is low, the 8292 is prevented from
acting as a comrolJer. If.it is switched high, the 8292 can
act as a controller. In essence, the SYC controls the
direction of the interface clear (IFC) and remote enable
(REN) signals.
7-411
25
23
10
9
-!l
00
0101
~ 01
0102
-.!!
-.!l
02
0103
03
0104
~ 04
TO
MICROPROCESSOR
INTERFACE
0105
.JL
...!!
05
06
0107
-1!
07
0108
0106
,2 CS
-1. Rii
5iiV
TliiI
-1! \Vii
.Jl INT
GPIB TRIGGER OUTPUT
8
8291A
ATN
fiii
-1.
CLOCK
TlR2
--!
2
RESET
NOAC
OREQ
-2
....J.
NRFD
OACK
SRQ
imi
ifc
TRIG
28
7
29
6
30
5
31
24
32 '
I
33
4
34
3
8293
0101
0101'
0102
0102'
0103'
0103
elL
flZ-.
r!£0106' elL
0107' r!10108' r!L
0104'
0104
0105
Dl05'
iilii6
0107
0108
5iiV
DAV'
OPTA
TlRI
ATN
fiii
35
rRr!L
TO
IEEE 488
BUS
~
r1!-
Vee
OPTB
r1L GND
MODE I
36
I
26
8293
39
3
fiii
EOI'
,.!.L
2
4
ATN*
Ji..
38
I
AfN
NOAC
NOAC'
,l!-
NRFD
NRFO'
37
2
I
27
25
24
10
9
8
6
5
'GPIB TRANSCEIVER
TlRI
TlR2
flZ-.
SRQ
SRQ'
,l!-
imi
ifc
REN'
elL
IFC'
OPTA
OPTB
TO
IEEE 488
BUS
r£r1L- GNO
elL GNO
MODE 0
Fig 5 Talker/listener o,nly implementation can be built using just tbree cbips-single 8l9IA and a
pair of 1293S. First (upper) transceivercbip is used for bidirectional data now on DIOlto DIOII data
lines. Lower 8293 bandies some of data byte transfer control lines and general interface management
lines.
8293 MODE SELECTION PIN MAPPING
• IEEE IMPLEMENTATION NAME
PIN NAME
OPTA
OPTB
DATAl
BUSI
DATA2
BUS2
DATA3
BUS3
DATM
BUS.
DATAS
BUSS
DATA6
BUSS
DATAl
DATA8
BUSI
DATA9
BUS8
DATAIO
BUS9
TlRI
Tlft2
Wi
ATN
Vee
PIN NO
McioE 0
MODE I
MODE 2
MODE 3
27
26
0
0
I
0
0
I
I
I
5
12
S
13
7
IS
S
IS
9
II
10
18
11
23
19
24
21
25
22
I
2
3
4
ifC
Ife·
m
0108
0108'
IiIO'I
REN·
NC
EOI'
iilii6
mro
NRFD'
iii7i4
SilQ
NliAC
NDAC'
TlRIOI'
TlRI02
ATN'
0107'" ,
DIOS'
0105
0105'
ifC
IFC'
m
,~6~;
EOI*
SRQ
mro
NRFO'
Nm
iii03
0103'
NC
NDAC'
ATNI ,
Dl03'
,ATNO
iii03
Iii02
0104*
Iii02
~'
DXV
DID2'
ATN~
GIOI'
GID2
GI02'
TlRI
TlR2
DAV'
0101
0101'
TlRI
NC
CLTH
Wi
ATN
iii7i4
ATIW
iiA\1
~
0107'
DIOS
OIOS'
0105
Dl05'
0104'
GWi
AIN
0108
OIOS'
IiIO'I
iffi
SYC
TlRI
TlR2
Wi
i.i'N
0102"
TlR2
Wi
OPTB
i.i'N
DATAIO
DATAl
ilATA9
OATA2
DATAS
DATA3
DATM
0101'
TlRI
iffi
Wi
ATN
*These pms are the IEEE 488 bus Jionmvedmg drlverf.recelwers. They IOclude aU tile bus termmatlOns
reqUired, by the standard. and connect dlrect!y to the GPIS connector
7-412
I
8293
TRANSCEII'ER
BUS9
BUS8
DATA5
GND
DATAS
BUSI
DATAl
BUS6
DAV·
Diiii
'OPTA
BUSI
BUSS
BUS2
BUS4
GND
BUS3 '
TO MICROPROCESSOR
~
f-#
~
c#
~
16
DO
01
02
03
04
05
06
07
RSO
RSI
RS2
17
18
19
8291A
21
22
23
9
Rii
10
Wii
4
RESET
6
OREQ
7
OACK
8
CS
3
CLOCK
11
INT
TO
MICROPROCESSOR
GPIB
TRIGGER
OUTPUT
5 TRIG
25
23
10
9
8
7
0101 28
0102 29
30
0103
31
0104
32
0105
33
0106
34
0107
0108 35
Tiiil 1
IiAV 36
EQj 39
26
AfN
27
SiiQ
24
38
NOAC
NRfD 37
2
T/R2
DlOI
0102
0103
0104
Dl05
0106
6 0107
5 0108
1
TiRI
24 MY
3EQj
4AfN
0101·
Dl02'
r#-
rli-
0103' ~
Dl04'
0105'
0106'
0107'
Dl08'
rU-
elielirllrR
8293
TO
IEEE 488
BUS
OAV' ~
m
~
REN ~
,!
ATNO
ifc[
OPTA
OPTB
~ Vee
t1§- Vee
NOAC
NRfD
.!L
.!L-
MOOE 3
-400
01
02
o.-..J.l-
r-l4
IiAV lL
'-------#
10
9
2
8
6
~03
16
17
18
19
9
1~
--{)
:
04
05
06
07
AD
@
WR
~SET
~~I
32
33 SPI
35 OBFf
36 iBfi
MICROPROCESSOR
TO{
21
38
23
8292
29
ATNO
39
COUNT
34
EOI2
22
ATNI
SilQ
REN
5
m
J
T/RI
AfN
NOAC
NFRO
T/R2
SRQ
REN
m
I
SRQ' lL
lL
IFC' lL
ATN· !L
EOI' lL
REN*
8293
23 ATNO
3EOi
TO
IEEE 488
BUS
7 E0I2
11 ATNI
1: SYNC
OSCILLATOR
OUTPUT
Vee~
r
~Xl
~
15TOI 5 PFj:
3' X2
ifCi
~
1
31
25 ifc[
24 CiC
21
CLTH
22
SYC
27
ClTH
24
SYC
SYSTEM
CONTROLLER
0FF . SWITCH
U eON
·OPTA
OPTB
&- GNO
pL Vee
MOOE 2
.t
'GPIB TRANSCEIVER
Fig 6 FuDy fUDctioDai talker/lIsteDerI cODtroUer iDterface eaD be built witb oDly four LSI cbips; tbe
am, and a pair of 8293S. Like simpler talkerllistener oDly case, one 8193 bandIes data
transceiver functioDs wbUe otber bandies data byte traDsfer cODtrol aDd geDeral iDterface •
managemeDt. Tbere are additioDai cODtrol IiDes eDabled wbicb support tbe cODtroller (8191) activity.
miA,
Summary
..
Before the advent of integrated solutions for IEEE 488
implementation, it usually took forty to fifty SSI and
MSI chips to build this interface. A large portion of
those were eliminated by controllers and interface chips
like the 8291A and 8292. Now, with the last part of the
interface available in LSI, a fully functional interface
can be built using only four LSI chips. The cost of the
original design was typically $400 to $500. A set of the
three chips, the 8291A, and two 8293s (for a
talker/listener function) allows a IS-fold reduction in
cost. The power dissipation of a 4O-chip interface was in
the vicinity of 10 W. The power dissipation of the 4-chip
approach is a mere 1.5 W. The size of the PC board is
considerably smaller, too, and that lowers the manufacturing costs and improves reliability.
Please rate the value of this article to you by circling
the appropriate number in the "Editorial·Score Box"
on the Inquiry. Card.
High 704
7-413
Average 705
Low 706
ARTICLE
REPRINT
AR·113
January 1980
©INTEl CORPORATION, 1980
Reprinted with permission of Computer Design Magazine,
October 1979 issue.
7-414
LSI CHIPS EASE STANDARD 488
BUS INTERFACING
Time and cost disadvantages of interfacing to the IEEE Std 488
bus are overcome with a dedicated LSI chip set that incorporates
most of its functional and electrical specifications
Ronald M. Williams
Intel Corporation, Santa Clara, California
Historically, interface techniques proliferated as
designers evolved customized links among instruments,
controllers, and processors for realtime test measure·
ments or data communications, resulting in excessive
and expensive codes, formats, signal levels, and timing
factors. Obviously, interface standardization was manda·
tory to save design costs for engineers, development
costs for manufacturers, and system integration costs
for users. Thus, IEEE Standard 488·1978 (a revision of
ANSI/IEEE Std 488.1975) offers a universal instrumenta·
tion system approach to automatic operating measure·
ment configurations that provides compatibility, versa·
tility, and flexibility. This system approach establishes
a suitable standard bus for interfacing programmable.
devices from different manufacturers. Outstanding ad·
vantages of the standard bus include byte serial, bit
parallel digital data handling, synchronized communi·
cation among devices at varying data rates, and hard·
ware interchangeability and interconnection in daisy·
chained fashion. However, some restrictive disadvantages
that have hindered implementation are highly com·
plex logic protocol" time consuming design analysis,
and lack of low cost components to perform the intri·
cate logic control functions. To overcome these draw·
backs, a large scale integrated (LSI) chip set has been
designed with built·in IEEE Std 488 logic controls. Thus,
7-415
interfacing has been significantly simplified for properly connecting processor buses and programming system
protocols_
ment. Bus functions encompass 16 active signal lines,
10 interface functions, the protocol by which inter'face functions send and receive messages, and logical
and timiJIg relationships between signal states,.
Functional requirements of the standard can be incorporated in either hardware, software, or a combination of both. Some designers have chosen the hardware approach to 'incorporate all the interface func'tions, using ,about 200 medium scale integrated (M~I)
and small scale integrated (881) packages. This technique costs about $1000 for a complete interface
board. As a result, many cost sensitive implementations of the bus interface use only a subset of its
functions custom tailored to the requirements of the
devices involved, thereby reducing 'package count and
expense by curtailing the interchangeability advantages.
Other designers have selected the software approach
to implement the bus interface. One disadvantage of
this approach' is that programming is an expensive and
extended project; another is that a subroutine has to
be executed with each transferred byte. This overhead
not only burdens the microprocessor within a device,
but also reduces the overall speed of the bus. This
approach costs about $200 for the interfacing functions.
Interface Overview
The IEEE Standard 488-1978 bus interface inoludes
'electrical, mechanical, and functional specifications *
for interconnecting both programmable and nonprogrammable electronic measuring apparatus with other
apparatus and accessories necessary to assemble instrumentation systems. The functional specifications
occupy about 80% of the document and involve a
proportional amount of system 'design time to ,imple'This article deals with the functional aspects (interface signals
that exist on the physical bus) of IEEE Std 488-1978, and is not
intended as a complete dissertation on the major elements of the
standard. For detailed definitions of the mechanical (physical
cable connections), electrical (timing, voltages, and currents)"
and operational (application software routines) technicalities,
interested readers should consult the IEEE Standard Digital
Inter/ace lor Prosrammable Instrumentation, IEEE Std 488-1978,
Institute of Electrical and Electronics Engineers, IDe, New York,
NY 10017, Nov 30, 1978--Ed.
,
Vss
ii'C
AfN1
SAd
FIll S GPI8 contl'Olltf chip. 8182 chip worka In conjunction with 8It1 to ptI'fonn GPlB oontI'OIler Inlelface
funotlona. It Implementa local control commancla fnlm ml~ accordInG to IEEE Std ... protocol.
Additionally. It p _ .uch Inputa ftom bue .. SRQ and EOI. FurtMmlore, It can Hnd the full repertoire
of GPIB oontI'OI maauvaa. IncludlllQ REN. lI'O, ATN. and EOI
7-421
GPIB
~~~~----~~~+----r----~~----t-------;aIlIiNDAC
~~~------f;~~----------------~t------i~IIIINRFD
~illIlIlIlI"~~IIIIIIIIIIIIII"~~IIII"~III1DIO
NOTES'
1 CONNECT TO NDAC FOR
BYTE COUNT OR TO EOI
FOR BLOCK COUNT
2 GATE ENSURES OPEN
COLLECTOR OPERATION
DURING PARAL.lEL PULL.
~ THE TRANSCEIVER AND
GATING FUNCTIONS WILL.
BE INCORPORATED IN A
FUTUR~ CHIP FROM INTEL.
Fig 6 System configuration' using chip set. I'n conjunction with 8291, 8292 performs complete controller function.
Together with shared bus transceivers, chip set forms',a cpmplete reee Std 488 Interface. In addition, DMA interface may be implemented through 8291 with 8237 DMA controller' '1
7-422
service requests (SRQS), configures other devi<:es on the
bus for remote control by sending Remote Enable
(HEN), and sends Interface Clear (IFC), allowing for
control .seizure to reinitialize the bus. More important.
ly, the SPAS if APRS:STRS:SPAS was true
r-
Device Clear Active State has occurred.
-
These are status only. They Will D,Q! generate
interrupts, nor do they have corresponding
mask bits.
REM
-
SPC
Serial Poll Complete interrupt.
Local lock out change Interrupt.
LLCNO LLO'
LLOC
RemotQ.ocal
REMC
Remote/Local change intemtPt.
AddresseUnaddressed
ADSC
Address status change interr'upt.'
".OTE;: 'In ton (talk·only) and Ion (listen-only) motles, no ADSC interrupt is generated.
7-433
AFN-00229B
8291 A
The APT interrupt bit indicates to the processor that
a secondary address is available in the CPT register
for validation. This interrupt will only occur if
Mode 3 addressing is in etrect. (Refer to the section
on addressing.) In Mode 2, secondary addresses will
be recognized automatically· on the 8291 A. They will
be ignored in Mode 1.
Status 1 Register. However, if it is so desired, data
transfer cycles may be performed without reading
the Interr.upt Status 1 Register if all interrupts except
, for BO or BI are disabled;' BO and BI will automatically reset after each byte is transferred.
If the 8291A is used in the interrupt mode, the
INT and DREO pins can be dedicated to data input
arid output interrupts respectively by enabling BI
and DMAO, provided that no other interrupts are
enabled. This eliminates the need to read the interrupt status registers if a byte is received or
transmitted.
The CPT interrupt bit flags the occurrence of an
undefined' command and of all secondary commands following an undefined command. The Command Pass Through feature is enabled by the BO bit
of Auxiliary Register B.Any message not decoded by
the 8291A (not included in the state diagrams/ in
Appendix B) becomes an undefined command. Note
that any addressed command is automatically ignoree;! when the 8291 A is not addressed.
The ERR bit is set to indicate the bus error condition
when the 8291 A is an active tal ker and tries to send a
byte to the GPIB, but there are no active listeners
(e.g., all devices on the GPIB are in AIDS). The logical equivalent of (nba . TACS . DAC . RFD) will set
this bit.
The DEC bit is set whenever DCAS has occurred.
The user must define a known state to which all
device functions will return in DtAS. Typically this
state will be a power-on state. However, the state of
the device functions at DCAS is at the designer's
discretion. It should be noted that DCAS has no
, effect on the interface functions which are returned
to a known state by the IFC (interface clear) message
or the pon local message.
Undefined commands are read by the CPU from the
Comm\lnd Pass Through register of the 8291A. This
register reflects the logic levels present on the data
lines at the time it is read. If the CPT feature is
enabled, the 8291A will hold off the handshal
4
6
32
TO
MICROPROCESSOR
0103
33
35
1
36
11
OSClllATO R
OUTPU T
Vee
--.-!.
~
$1
15.25 PF
J
~
TRIG
REN
DO
DAV
28
25
29
23
30
10
31
9
32
8
33
7
34
6
35
5
1
1
36
2'
39
3
26
4
2
---.!.!.
WR
RESET1t
IFC
ATNO
COUNT
Cs
EOl2
TCI
ATNt
0105"
Di06
0106"
0107
0108
8293
TlR1
DAV
~
~
~
~
0107" ~
.
0108"
f1L
DAV"
~
TO
IEEE·488
BUS
EOI
ATN
~
r-'-4
riRl
21
8
38
6
23
5
29
23
39
3
3'
7
22
11
OPTA
ATNO
IFCl
2
8292
0105
~
9
AD
0104"
~ I-
D'
05
RD
0104
f-1!..
37
03
SRQ
0103"
24
10
REN
0102"
Di03
38
02
07
0102
27
01
06
0101" ~
0101
OPTS
~Ve
~Ve
MODE3
ATN
NDAC
NDAG
NFRD
NRFD
T/R2
SRO
SRO"
R~N
REN"
8293
IFC
ATNO
IFC"
ATN"
EOI·
EOI
~
CLI
jtj
TO
EEE 488
BUS
r£r'1-
~
EOl2
ATNI
SPI
,
OBFI
IBFt
SYNC
SS
x,t
IFCL
CIC
x,t
EA
ClTH
SYC
1
25
31
24
27
21
2.
22
LJ
ON
iFCL
CIC
CLTH
OPTA
SYC
OPTB
~Vs
~Ve
MODE2
SYSTEM
CONTROllER
SWITCH
• = GPIB BUS TRANSCEIVER
t =SEE 8041 A DATA SHEeT FOR ALTERNATE
CRYSTAL CONFIGURATIONS
tt = CAN CONNECT TO SYSTEM RESET SWITCH,
SEE 8041A DATA SHEET
Figure 7. 8291 A, 8292, and 8293 System Configuration
7-443
AF~229B
inter
8291A
TheADSC bit in the Interrupt Status 2 Register indicates that the 8291A has been addressed or
unaddressed. The TA and LA bits in the Address
Status Register indicate whether the 8291A is talker
(TA=1), listener (LA=1), both (TA=LA=1) or unaddressed (TA=LA=O).
Start-Up Procedures
The following section describes the steps needed to
initialize a typical 8291A system implementing a
talker/listener interface and an 8291N8292 system
implementing a talker/listener/controller interface.
If the 8291A is addressed to listen, the local CPU can
read the Data-In Register whenever the BI (Byte In)
interrupt occurs in the Interrupt Status 1 Register. If
the END bit in the same register is also set, either EOI
'or a data byte matching the pattern in the EOS register has been received.
TALKER/LISTENER SYSTEM
Assume a general system conf,iguration with the
following features: (i) Polled system interface; (ii)
Mode 1 addressing; (iii) same address for talker and
listener; (iv) ASCII carriage return as the end-ofsequence (EOS) character; (v) EOI sent true with the
last byte; and, (vi) 8 MHz clock.
In the talker mode. the CPU writes data into the
Byte-Out Register on BO (Byte Out) true.
Initialization. Initialization is accomplished with
the following steps:
TALKER/LISTENER/CONTROLLER SYSTEM
Combined with the Intel 8292, the 8291A executes a
complete IEEE-488-1978 controller function, The
8291A talks and listens via the data and handshake
Ii nes, (iiiR'J!'Ij , N15AC and OAV). The 8292 controls four
of the five bus management lines (IFC. SRQ,ATN and
R'EN).
the fifth line, is shared. The 8291A drives
and receives
when 8jf is used as an end-ofblock indicator. The 8292 drives Ern along with AiN
during a parallel poll command.
1. Pulse the RESET input or write 02H to the Auxiliary Mode Register.
2. Write OOH to the Interrupt Enable Registers 1 and
2. This disables interrupt and DMA.
3. Write 01 H to the Address Mode Register to select
Mode 1 addressing.
ro,
4. Write 28H to the Auxiliary Mode Register. This,
loads 8H to the Auxiliary Register A matching the
8 MHz clock input to the internal T1 delay counter
to generate the delay meeting the IEEE spec.
5. Write the talker/listener address to the Address
0/1 register. The three most significant bits are
zero.
6. Write an ASCII carriage return (ODH) to the EOS
register.
7. Write 88H to the Auxiliary Mode Register to allow
EOI to be sent true when the EOS character is
sent.
8. Write OOH to the Auxiliary Mode Register. This
writes the "Immediate Execute pon" message
and takes the 8291A from the initialization state
into the idle state.,The 8291Awill remain idle until
the controller initiates some activity by driving
ATN true.
Communication. The local CPU now polls the
8291A to determine which controller command has
been received.
The controller addresses the 8291A by driving A"i'N.
placing MLA (My Listen Address) on the bus and
driving DAV.lf the lowerfive bits of the MLA message
match the address programmed into the Add ress 0/1
register, the 8291A is addressed to listen. It would ,be
addressed to talk if the controller sent the MTA message instead of MLA.
I
ro
Once again, assume a general system configuration
with the following features: (i) Polled system interface; (ii) 8292 as the system controller and
controller-in-charge; (iii)ASCIi carriage return (ODH)
as the EOS identifier; (iv) EOI sent with the last
character; and, (v) an external buffer (8282) used to
monitor the TCI line.
Initialization. In order to send a command across
the GPIB, the 8292 has to drive A"i'N, and the 8291 A
has to drive the data lines. Both devices therefore
need initialization.
To initialize the 8292:
1. Pulse the RESET input. The 8292 will initiallydrive
all outputs high. TCI. SPI. OBFI, IBFI and CLTH
will then go low. The Interrupt Status, Interrupt
Mask, Error Flag, Error Mask and Timeout registers will be cleared. The interrupt counter will be
disabled and loaded with 255. The 8292 will then
monitor the status oLthe SYC pin. If h.igh. the
8292 will pulse IFC true for at le,ast 100J-ts in compliance with the IEEE-488-1978 standard. It will
then take control by asserting ATN.
To initialize the 8291A, the following is necessary:
1. Write OOH to Interrupt Enable registers :1 and 2.
This,disables interrupt and DMA.
-:7-444
AFN-00229B
8291A
2. With the 8292 as the controller-in-charge, it is
impossible to address the 8292 via the GPIB.
Therefore, the ton or Ion modes of the 8291 A must
be used. To send comands, set the 8291A in the
ton mode by writing 80H to. the Address Mode
Register.
3. Write 26H to the Auxiliary Mode Register to match
the T1 data settling time to the 6 MHz clock input.
4. Write an ASCII carriage return (ODH) to the EOS
Register.
5. Write 84H to the Auxiliary Mode Register in order
to enable "Output EOI on EOS sent" and thus
send EOI with the last character.
6. Write OOH-Immediate Execute pon-to theAuxiliary Mode Register to put the 8291A in the idle
state.
Communication. Since the 8291A is in the ton
mode, a BO interrupt is generated as soon as the
immediate Execute pon command is written. The
CPU writes the command into the Data Out Register,
and repeats it on BO becoming true for as many
commands as necessary. ATN remains continuously
true unless theGTSB (Go To Standby) command is
sent to the 8292.
ATIiI has to be false in order to send data rather than
commands from the controller. To do this, the following steps are needed:
1. Enable the TCI interrupt if not already enabled.
2. Wait for IBF (Input Buffer Full) in the 8292 Interru pt Status Reg ister to be reset.
3. Write the GTSB (F6H) command to the 8292 Command Field Register.
4. Read the 8282 and wait for TCI to be true.
5. Write the ton (80H) and pon (OOH) command to
the 8291A Address Mode Registe(and Auxiliary
Mode Registers respectively.
6. Wait for the BO interrupt to be set in the 8291A.
7. Write the data to the 8291 A Data-Out Register.
Identically, the user could command ~he controller
to listen rather than talk. To do that, write Ion (40H)
instead of ton into the Address Mode Register. Then
wait for BI rather than BO to go true. Read the data
Register.
7-445
AFN·OO2298
intJ"
8291A
ABSOLUTE MAXIMUM RATINGS
'NOTlCE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This Is a stress rating only and functional operation of the
device at these or any other condItions above those indicated
in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditIons for extended
periods may affect device reliability.
Ambient Temperature Under Bias .......... O"C to 70°C
Storage Temperature ................ -6SoC to + 1S0°C
Voltage' on Any Pin
With Respect to Ground ................ -O.SV to +7V
Power Dissipation ......................... 0.6S Watts
D.C. CHARACTERISTICS [Vee =
SV ±10%, TA = O°C to 700
e (Commercial)]
Mln_
Max.
Unit
Input Low Voltage
-O.S
0.8
V
VIH
Input High Voltage
2
Vee+O.S
V
VOL
Output Low Voltage
0.4S
V
VOH
Output High Voltage
2.4
V
IOH = -400!,A (-1S0!'A for SRO pinl
VOH-INT
Interrupt Output High Voltage
2.4
V
IOH=-400!,A
IlL
Input Leakage
IIOFL
Output Leakage Current
Icc
Vee Supply Current
Symbol
VIL
Parameter
10
Symbol
[Vee =
IOL=2rl:lA (4mA for TR1 pinl
V
3.S
A.C. CHARACTERISTICS
Test Conditions
IOH=-SO!,A
!,A
VIN=OV to Vee
±10
!,A
VOUT=O.4SV, VCC
120
mA
TA=O°C
--
sv ±10%, TA = O"C to 70"C (Commercial)]
Parameter
tAR
Address Stable Before READ
tRA
Address Hold After READ
tRR
READ Width
tAD
Address Stable to Data Valid
tRO
READ to Data Valid
tROF
Data Float After
tAW
Address Stable Before WRITE
Min.
Max.
nsec
0
nsec
140
READ
Unit
0
Test Conditions
nsec
0
2S0
nsee
100
nsee
60
nsee
nsee
0
tWA
Addres,s Hold After WRITE
tww
WRITE Width
170
nsee
tow
Data Set Up Time to the Trailing
Edge of WRITE
130
nsee
two
Data Hold Time AfterWRTTl:
tOKOR4
RQl, or WRl, to DREOl,
130
nsee
tOKOA6
RDj, to Valid Data
(00 -07)
200
nsee
0
0
nsee
7-446
DACKj, to ROj, 0 ,,;;t ";;SOnsee
AFN.()()229B
inter
8291 A
WAVEFORMS
READ
~/RS,
=:>!
K
I'
'AD
'RR
I-,·RA .....
.
V
READ:
-
~'RD--
!--'AR-
./
DATA BUS
IDATA OUT)
"'"
~
:'-'RDF
VALID DATA
/'
WRITE
CS/RS,
=:)
l(
.
'ww
-twA-!
-tow-
~
Ii
i--'AW-+
DATA BUS
IDATA INI
DATA MAY CHANGE
~
--
'WD~
VALID DATA
K
DATA MAY CHANGE
DMA
•
OREQ _ _
---.II"
DACK----------------~
RoorWR -------------------______"',
- rt-'-_ _ _ _ _ _ __
7-447
8291 A
A.C. TIMING MEASUREMENT POINTS AND LOAD CONDlnONS
INPUT/OUTPUT
u~u >
TEST POINTS
Q.8
0.45
<"X=
Q.8
.
A.C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC "1" AND 045V FOR
~~8g';v"~~JI,t1~~E.~UREMENTS ARE MADe AT 2.oy FOR A LOGIC "1"
GPIB TIMINGS'
Symbol
Max.
Units
EOi~ toTR1t
Parameter
135
nsec
PPSS, ATN=O.45V
TEOD16
Em~ to DiriVaiid
155
nsec
PPSS, ATN=0.45V
TEOT12
EOittoTRH
155
nsec
TATND4
Ai'N~ to NDAC~
155
nsec
PPSS, ATN=O.45V
TACS, AIDS
TATT14
ATN~toTRH
155
nsec
TACS, AIDS
TATI24
Ai'N~ to TR2~
DAV~to~t
155
nsec
TACS, AIDS
650
nsec
AH,CACS
TNDDV1
NDACt to DAVt
350
nsec
SH,STRS
TNRDR1
NRFDt to DREQt
nsec
SH
TDVDR3
DAV~ to DREQt
nsec
AH, LACS, ATN=2.4V
TEOT132
TDVND3-C
\
Test Conditione
,
\
TDVND2-C
DAVtto~~
400·
600
350
nsec
AH, LACS
TDVNR1-C
DAiit to Fmmt
350
nsec
AH, LACS, rdy=ll"ue
TRDNR3
Rlnto NRFDt
500
nsec
AH,LACS
TWRD15
WRf to DiriVaiid
nsec
SH, TACS, RS=O.4V
TWRE05
WRt to EmVaiid
280
350
nsec
SH,TACS
TWRDV2
WRttoDAV~
830 + t SYNC
nsec
High Speed ll"ansfers Enabled,
NF = fc, tsVNC = 1/2-fc
NOTES:
1. All GPIB timings are at the pins of the 8291A.
2. The lest number in the symbol for any GPIB timing parameter is chosen according to the transition directions of the reference
signals. The following table describes the numbering scheme.
fto
fto
~to
t
~
t
ho !
ttoVALID
J,toVALID
1
2
'3
4
5
6
7-448
inter
8291 A
APPENDIX A
MODIFIED STATE DIAGRAMS
Figure A-1 presents the interface function state
diagrams. It is derived from IEEE Std. state dIagrams: with the following changes:
Level
Logic
0
T
F
T
F
T
F
1
0
1
0
A. The 8291A supports the complete set of IEEE-488
interface functions except for the controller. These
include: SH1, AH1, T5, TE5, L3, LE3, SR1, RL 1, PP1,
DC1, DT1, and CO.
B. Addressing modes included in T,L state
diagrams.
1
Convention
IEEE-488
Intel
DAV
DAV
NDAC
NDAC
NRFD
NRFD
DAV
DAV
NDAC
NDAC
NRFD
NRFD
Consider the condition when the Not-Ready-ForData Signal (pin 37) is active. Intel indicates this
active low signal with the symbol NRFD (VOUT",VOL for
AH; VIN",VIL for SH). The IEEE-488-1978 Standard, in
its state diagrams, indicates the active state of this
Signal (True condition) with NRFD.
D. All remote multiline messages decoded are conditioned by ACDS. The multiplication by ACDS is not
drawn to simplify the diagrams.
Note that in Mode 3, MSA, OSA are generated only
after secondary address validity check by the microprocessor (APT interrupt).
E. The symbol
indicates:
C. In these modified state diagrams, the IEEE-4881978 convention of negative (low true) logic is
followed. This should not be confused with the Intel
pin- and signal-naming convention based on positive logic. Thus, while the state diagrams below carry low true logic, the signals described elsew~ere in
this data sheet are consistent with Intel notation and
are based on positive logic.
1. When event X occurs, the function returns to
state S.
2. X overrides any other transition condition in
the function.
Statement 2 simplifies the~diagram, avoiding the
explicit use of X to condition all transitions from S to
other states.
r----'
I
I
I
SH
I
IL ____ J I
pon
ATN + F1
(WITHIN.,)
DAV
F'-TACS+SPAS
F{gure, A-1. ,828:1 A, State Dlagfama (Continued next page)
7-449
AfN.OO229B
8291A
r-----,
I
I
I
AH
I
I
I
L ____ J
*THIS TRANSITION WILL NEVER
OCCUR UNDER NORMAL OPERATION.
pon _ _ _
tTOELAY ISABOUT300NS
~
FOR DEBOUNCING DAV.
F2 = ATN + LACS
+ LADS
F3::: ATN + rdy
T3'=T3·CPT·m
}-----o. END IF (EDI + EOB) RECEIVED
r-----.
I
I
I
TE
I
I
I
L ____ J
STB AND ROS AVAILABLE
TOSH
pon---~
IFe
(WITHIN 141
F4= OTA+ (OSA' TPAS+ MSA • LPAS)'
MODE 1 + MLA. MODE 1
EOI IF DAB
~
EOB
r--~--'
RQS IN STB
I
I
I
SRQ
L ____
I
I
I
J
pon---~
pon
----I
Ras IN STB
Figure A-1. 8291A State DIagrams (ContInued next 'page)
7-450
AFN-()()229B
8291 A
r-----,
I
1
I
LEI
I
I
r----l
1
1
1
RL
1
1
I'
L... _ _ _ _ J
L.. _ _ _ _ J
pon _ _ _-.(
pon---'"
IFe (WITHIN t4!
pon----.(
F5'" (MlA· MODE 1 + LPAS· MSA • MODE 1)
r----,
I
I
I
PP2
L ____
I
I
JI
pon---.-t
*tDY '" ATN: EOI
r----'
1
1
r----'
1
DC
1
1
1
1L _ _ _ _ J1
1
DT
1
1
L ____ ...J1
F6 = OCL + SOC· LADS
Figure A-1. '8291A State Diagrams
7-451
AFN-002298
8291 A
APPENDIX B
Table B-1. IEEE 488 Time Value.
Time Yalue
Identifier'
Function (Applies to)
T1
SH
t2
LC,iC,SH,AH,T,L
T3
AH
t4
,
T,TE,L,LE,C,CE
Description
Value
Settling Time for Multiline Messages
.. 2/ls'
Response to A TN
:S
Interface Message Accept Time"
>0'
Response to IFC or REN False
<
100/lS
Respons~ to ATN+EOI
:S
200ns
200ns
ts
PP
T6
C
Parallel Poll Execution Time
T7
C
Controller Delay to Allow Current Talker
to see A TN Message
Ta
C
Length of IFC or REN False
> 100,,5
T9
C
Delay for EOls
." 1.5/ls·
,
." 2/ls
." 500 ns
NOTES:
'Time values specified by a lower case t indicate the maximum time allowed to make a state transition. Time values specified by an
upper case T indicate the minimum time that a function must remain in a state before exiting.
'If three-state drivers are used on'the 010, OAV, and EOllines, T, may be:
1. '" 1100 ns.
.
2. Or '" 700 ns if it is known that within the controller ATN is driven by a three-state driver.
3. Or." 500ns for all subsequent bytes following the first sent after each false transition of ATN (the first byte must be sent in accord·
ance with (1) or (2).
4. Or." 350ns for all subsequent bytes following the first sent after each false transition of ATN under conditions specified in Section
5.2.3 and warning note. See IEEE Standard 488.
'Time required for interface functions to accept, not necessarily respond to interface messages.
'Implementation dependent.
'Delay required for EOI, NOAC, and NRFO signal lines to indicate valid states.
'''' 600 ns for three-state drivers.
8291 A
APPENDIXC
THE THREE-WIRE HANDSHAKE
TWRDl5
It-n ...
I
VALID
NOT VALID
r=4
I
VALID
f4-;;;J
I+-TNDDV1_~TDVNR1-
I+-TWRDV2
I"!'""-TRDNR3_
..,Il
9
_TDVND3_
f-
-\
I~NRD}
DREQ(SH)
_TDVDR3
DREQ(AH)
..,f-
'"'Ir"
-~
Figure C-1. 3-Wlre Handshake TIming at 8291A
7-453
AFN-00229B
inter
8~2
.
GPIB .CONTROLLER
• Complete IEEE Standard 488 Controller
Function
• Complete Implementation of Transfer
Confrol Protocol
• Interface Clear (IFC) Sending Capability
Allows Seizure of Bus Control and/or
Initialization of the Bus
• Responds to Service Requests (SRQ)
• Sends Remote Enable (REN), Allowing
Instruments to Switch to Remote
Control
• Synchronous Control Seizure Prevents·
the Destruction of Any Data
Transmission in Progress
• Connects with the 8291 to Form a
C6mplete IEEE Standard 488 Interface
Talker/Listener/Controller
The 8292 GPIB Controller is a microprocessor·controlled chip designed to function with the 8291 GPIB Talker/Listener
to implement the full IEEE Standard 488 controller function, including transfer control protocol. The 8292 is a pre·
programmed Intel@ 8041A.
IFCL
X1
8292
REN
RESET
DAV
Cs
riR1
COUNT
X2
VCC
GPIB
CONTROLLER
Vcc
IBFI
OBFI
GND
EOI
Jil.i
SPI
AO
TCI
WR
CIC
SYNC
NC
Do
ATNO
D1
Ne
02
CLTH
03
Vec
b4
NC
DS
SYC
De
IFC
D7
iifN)
VSS
SRQ
GENERAL PURPOSE INTERFACE BUS
Figure 1. 8291, 8292 Block Diagram
Figure 2. Pin Configuration
7-454
inter
8292
Table 1. Pin Description
Pin
No.
~pe
Name and Function
IFCL
1
I
IFe Received (Latched): The 8292
monitors the IFC Line (when not
system controller) through this pin.
X1,X2
2...3
/
I
C..,...llnputs: Inputs for a crystal,
LC or an external timing signal to
determine the internal oscillator
frequency.
RESET
4
I
Relet: Used to initialize the chip to
a known statl! during power on.
es
6
I
Chip Select Input: Used to select
the 8292 from other devices on the
common data bus.
RD
8
I
Read Enable: Allows the master
CPU to read from the 8292.
9
I
Addre.. Une: Used to select batween the data bus and the status
register during read operations and
to distinguish between data and
commands written into the 8292
during write operations.
Symbol
Ao
\
Pin
WR
10
I
Write Enable: Allows the master
CPU to write to the 8292.
SYNC
11
0
Sync: 8041A inslruction cycle syn·
chronizalion signal; It Is an output
clock with a frequency of XTAL ~
15.
Do-Dr
12·19
I/O
Data: 8 bidirectional lines used for
communication between the central processor and the 1I292's data
bus buffers and status register.
Vss
SRO
7,20
A'i'Ni
IFC
21
22
23
Symbol
No.
~pe
REN
38
0
Remote Enable: The Remote Enable bus signal selects remote or
local control of the device on the
bus. A GPIB pus management line,
as defined by IEEE Std. 488-1978.
DAV
37
I/O
Data Valid: Used during parallei
poll to force the 8291 to accept the
parallel poll status bits. It is also
used during the tcs procedure.
IBFI
36
0
Input Buffer Not Full: Used to
interrupt the central processor
while the input buffer of the 8292 is
empty. This feature is enabled and
disabled by the interrupt mask
register.
OBFI
35
0
Output Buffer Full: Used as an
interrupt to the central processor
while the output buffer of the 8292 is
full. The feature can be enabled and
disabled by the Interrupt mask
register.
E012
34
1/0
End Or Identify: One of the GPIB
management lines, as defined by
IEEE Std. 488-1978. Used with ATN
as Identify Message during parallel
poll.
SPI
33
0
Special Interrupt: Used as an interrupt on events not initiated by the
central processor.
TCI
32
0
Taek Comptete Interrupt: 'Interrupt
to the control processor used to indicate that the task requested was
completed by the 8292 and the Information requested is ready in the
data bus buffer.
CIC
31.
0
Controller In Charge: Controls the
SIR input of the SRO bus transceiver. It can also be used to indicate that the 8292 is in charge of the
GPIB bus.
P.S. Ground: Circuit ground potential.
I
I
I/O
Service, Reque8t: One of the IEEE
control lines. Sampled by the 8292
when it is controlier in charge. If
true, SPI interrupt to the master will
be generated.
Attention In: Used by the 8292 to
monitor the GPIB ATN control line. It
is used during the transfer control
procedure.
interface Clear: One of the GPIB'
management lines, as defined by
IEEE Std. 488-1978, places all devices in a known quiescent state.
SYC
24
I
S,8tem Conroller: Monitors 'the
system controller switch.
CLTH
27
0
Clear Latch: Used to claar the IFCR
latch after bemg recognized by the
8292. Usually'low (except after
hardware R~, it will be pulsed
high when IFCR Is recognized by
the 8292.
ATNO
29
0
Attention Out: Controls 'the ATN
control line of the bus through external logic for tcs and tca procedures. (ATN is a GPIB control line, as
defined by IEEE Std. 488-1978.)
Name and function
5,26,40 P.S. Voltage: +5V supply input ±10%.
Vee
EV'!ntCount: When enabled by,the
COUNT
39
I
proper command the internal
counter will count external events
through this pin.' High to low trensition will increment the internal
counter by one. The pin Is sampled
once per three Internal instruction
cycles (7.5",sec sample period
when using 5 MHz XTAL). It can be
used for byte counting when connected to NDAC, or for block counting when connected to the EOI.
7-455
,
AFN-00741 0
·8292
Interrllpt Status Register
FUNCTIONAL DESCRIPTION
The 8292 is an Intel 8041A which has been programmed
as a GPIB Controller interface element. It "is used with
the 8291 GPIB Talker/Listener and two 8293 GPIB 'Transceivers to form a complete IEEE-488 Bus Interface for a
microprocessor. Ttle electrical interface is performed by
the transceivers, data transfer is done by the talker/
listener, and control of the bus is done by the 8292.
Figure 3 is a typical controller interface using Intel's
GPIB peripherals.
GPIB
I
I
svc
ERR
ISRQ
I
x
EV
IFCR
IBF
OBF
The 8292 can be configured to interrupt the microprocessor on one of several conditiOns. Upon receipt of the
Interrupt the microprocessor must read the 8292
interrupt status register to determine which event
caused the interrupt, and then the appropriate subroutine can be performed. The interrupt status register is
read with Ao high. With the exception of OBF and IBF,
these Interrupts are enabled or disabled by the SPI
interrupt mask. OBF and IBF have their own bits in the
interrupt mask (OeFI and IBFI).
OBF
TO
PROCESSOR
BUS
TO
PROCESSOR
BUS
GPIB
Figure 3. Talker/Listener/Controller Configuration
The internal RAM in the 8041A is used as a speCial
purpose register bank for the 8292. Most of these
registers (except for the interrupt flag) can be accessed
through commands to the 8292. Table 2 identifies the
registers used by the 8292 and how they are accessed.
Output Buffer FUll. A byte is waiting to be read by
the microprocessor. This flag is cleared when the
output data bus buffer is read.
Input Buffer Full. The byte previously written by
IBF
the microprocessor has not been read yet by the
8292. If another byte is written to the 8292 before
this flag clears, data will be lost. IBF is cleared
when the 8292 reads the data byte.
IFCR Interface Clear Received. The GPIB system
controller has set IFC. The 8292 has become idle
and is no longer in charge of the bus. The flag is
cleared when the lACK command is Issued.
Event Counter Interrupt. The requested number
EV
of blocks or data bytes has been transferred. The
EV interrupt flag is cleared by the lACK
command.
SRQ Service Request. Notifies the 8292 that a service
request (SRO) message has been received. It is
cleared by the lACK command.
ERR Error occurred. The type of error can be determined by reading the error status register. This
interrupt flag is cleared by the lACK command.
SYC System Controller Switch Change. Notifies the
processor that the state of the system controller
switch has changed. The actual state is contained irvthe GPIB Status Register. This flag is
cleared by the lACK command.
Table 2_ 8292 Registers
WRITE TO 8282
READ FROM 8282
INTERRUPT STATUS
svc
ERR I SRO
07
EV
I
X
I
IBF
IIFCR I
1
OBF I
ERROR FLAG
I I
I I
I I I
I
I I I
I
1
1
I I I I I I I
x
I USER I
x
X
I
I TOUT3 \;rOUT 21 TOUT 1
CONTROLLER STATUS
x
CSBS
CA
REN
OAV
EOI
0
0
0
x
SVCS
IFC
REN
SRO
GPIB (8US) STATUS
X
SVC
IFC
ANTI
SRO
I
I
0
0
0
0
0
0
0
0
0
Ao
IIBFI
I
I SRO I
I
I
I
01
00
ERROR MASK
o·
I
I I I
I I
I I
I I I
I I I I
0
0
I
o·
1
I
1
1
0
1 TOUT31 TOUT2ITOUT,
1
COMMAND FIELD
USER
0
1
OP
1
C
C
C
C
0
0
0
o·
0
0
o·
I
EVENT COUNTER
o·
0
0
0
0
0
0
0
1 ..0
TIME OUT
I
I
TIM E OUT STATUS
SVC [ OBFI
07
EVENT COUNTER STATUS
0
TCI
SPI
I
DO
X
0
INTERRUPT MASK
AO
o·
I
0
0
I
o·
·1
0
0
I
I I
,0
Note: These registers are accessed by a special utility command;
see page 6.
--------
7-456
AfN-007410
inter
8292
Event Counter Register
Interrupt Maek Register
I
1
BPI
1
TCI
1
BYC
1
OBFI
1
o
IBFI
BAQ
The Interrupt Mask Register is used to enable features
and to mask the SPI and TCI interrupts. The flags in the
Interrupt Status Register will be active even when
masked out. The Interrupt Mask Register is written
when Ao Is low and reset by the RINM command. When
the register Is rl18d, 0 1 a"d 07 are undefined. An Inter·
tupt is enabled by setting the corresponding register bit.
SRQ
Enable interrupts, on SRQ rec,eived.
iiFi
Enable interrupts on input buffer empty.
The Event Counter Register contains the initial value for
the event counter. The counter can count pulses on pin
'39 of the 8292 (COUNT): It can be connected to EOI or
NDAC to count blocks or bytes respectively during
standby state. A count of zero equals 256. This register
cannot be read, and Is written using the WEVC
command.
OBFI Enable Interrupts on output buffer full.
SYC' Enable interrupts on a change in the system
controller switch.
TCI
Enable Interrupts on the task completed.
SPI
Enable interrupts on special events.
NOTE: The 'event counter is enabled by the GSEC
command, the error Interrupt Is enabled by the error
mask register, and IFC cannot be masked (It will always
cause an interrupt).
Controller Status Register
ICSBSI
CA
1
x I
X
IsvcsllFC
REN
SRQ
The Controller Status Register is used to determine the
status of the controller function. This register Is
accessed by the RCST command.
SRQ
Service Request line active (CSRS).
REN
Sending Remote Enable.
IFC
Sending or receiving interface clear.
SYCS System Controller Switch Status (SACS).
CA
Controller Active (CACS + CAWS + CSWS).
=
CSBS Controller Stand·by State (CSBS, CAl (0,0) Controller Idle
E,.nt Counter Status Register
This register contains the current value in the event
counter. The event counter counts back from the initial
value stored in the Event Counter Register to zero and
then generates an Event Counter Interrupt. This register
cannot be written and can be read using a REVC
command.
Time Out Register
The Time Out Register is used to store the time used for
the time out error function. See the individual timeouts
(TOUT1, 2, 3) to determine the units of this counter. This
Time Out Register cannot be read, and it is written ,with
the WTOUT command.
Time Out Status Register
This register contains the current value in the time out
counter. The time out counter decrements from the .
original value stored in the Time Out Register. When
zero is reached, the appropriate error interrupt is gen·
erated. If the register is read while none of the time out
functions are active, the register will contain the 'last
value re,ached the last time a function was active. The
Time Out Status Register cannot be written, and it is
read with the RTOUT command.
Error Flag Register
BPIB Bus Status Register
I
REN
1
DAV
1
EOI
1 x 1
1
SYC
IFC
ATNI
~
'ThiS register contains GPIB bus status information. It
can be used by the microprocessor to monitor and
manage the bus. The GPIB Bus Register can be rl18d
using the RBST command.
Each of these status bits reflect the current status of
the corresponding pin on the 8292.
SRQ
Service Request
ATNI Attention In
IFC
Interface Clear
SYC
System Controller Switch
EOI
End or Identify
DAV
Data Valid
REN
Remote Enable
x
1
X
1 USER 1
x,
I'
X
ITOUT3 I TOUT2 1TOUT,
SRQ
7-457
~
Four errors are flagged by the 8292 with a bit in the Err!)r
Flag Register. Each of these errorS can be masked by
the Error Mask Register. The Error Flag Register cannot
be written, and it is read by the lACK command when the
error flag in the Interrupt Status Register is set.
TOUT1 Time Out Error 1 bccurs when the current con·
troller has not stopped sending ATN after
receiving the TCT message for the time period
specified by the Time Out Register., Each count
in the 11me Out Register is at least 18,00 tCY'
After flagging the error"the 8292 will remain in a
loop trying to take control until the current
controller stops sending ATN or a new com·
mand is written by the microprocessor. If a neVi
command is written, the 8292 will return to the
loop after executing It.
AFN-0074'D
8292
TOUT2 Time Out Error 2 occurs When the transmission
between the addressed talker and listener has
not started for the time period specified by the
Time Out Register. E.ach count in the Time Out
Register is at least 45 tCY' This feature is only
enabled when the controller is in the CSBS
state.
TOUT3 Time Out Error 3 occurs when the handshake
signals are stuck and the 8292 Is not succeed·
ing in taking control synchronously for the time
period specified by the Time Out Register. Each
count in the Time Out Register is at least 1800
tCY' The 8292 will continue chec!5ing ATNI until
it becomes true or a new command is received.
After performing the new command, the 8292
will return to the ATNI checking loop.
.
USER
User error occurs when request to assert IFC or
REN was received and the 8292 was not the
system controller.
Error Mask Register
DO
The Error Mask Register is used to mask the interrupt
from a particular type of error. Each type of error inter·
rupt is enabled by setting the corresponding bit in the
Error Mask Register. This register can be read with the
RERM command and written with Ao low.
Command' Register
F2 -
c
c
c
DO.
Commands are performed by the 8292 whenever a byte
is written with Ao high. There are two categories of
commands distinguished by the OP bit (bit 4). The first
category is the operation command (OP= 1). These
commands initiate some action on the interface bus.
The second category is the utility commands (OP=O).
These commands are used to aid the communication
between the processor and the 8292.
RST -
Reset
This command has the same .effect as asserting the
external reset on the 8292. For details, Jefer to the reset
procedure described later.
F3 -
RSTI -
Reset Interrupts
This command resets any pending Interrupts and clears
the error flags. The 8292 will not return to any loop it was
, in (such as from the time out interrupts).
F4 -
GSEC - Go To Standby, Enable Counting
The function causes ATNO to go high and the counter.
will be enabled. If the 8292 was not the active controller,
this command will exit immediately. If the 8292 Is the
active controller,the counter will be loaded with the
value stored in the Event Counter Register, and the
internal interrupt will be enabled so that when the
counter reaches zero, the SPI interrupt will be gener·
ated. SPI will be generated every 256 counts thereafter
until the controller exits the standby state or the SPCNI
command is written. An initial count of 256 (zero in the
Event Counter Register) will be used if the WEVC
command is not executed. If the data transmission does
not start, a TOUT2 error will be generated.
F5 -
op
EXPP - Execute Parallel Poll
This command initiates a parallel poll by asserting EOI
when ATN is already active. TCI will beset at the end of the
command. The 8291 should be previously configured as a
listener. Upon detection of DAV true, the 8291 enters
ACDS and latches the parallel poll response (PPR) byte
into its data in register. The master will be interrupted by
the 8291 BI interrupt when the PPR byte is available. No
interrupts except the IBFI will be generated by the 8292.
The 8292 will respond to this command only when it is the
active controller.
F6 -
GTSB - Go To Standby
If the 8292 is the active controller, ATNO will go high
then TCI will be generated. If the data transmission does
not start, a TOUT2 error will be generated.
OPERATION COMMANDS
Operation commands initiate some action on the GPIB
interface bus: It is using these commands that the
control functions such as polling, taking and passing
control, arid system controiler· functions are performed.
FO - SPCNI - Stop Counter Interrupts
This command disables the internal counter interrupt so
that the 8292 will sto'p interrupting the master on event
counter underflows. However, the counter will continue
counting and its contents can stili be used.
F1 - GmL -
procedure while transferring control to another, con;
troller. The 8292 will respond to this command only If it
is in the active state. ATNO will go high, and CIC will be
high so that this 8292 will no longer be driving the ATN
line ,on the GPIB interface bus. TCI will be set upon
completion.'
.
F7 - SLOC - Set Local Mode
If the 8292 is the system controller, then REN will be asserted false and TCI will ,be set true. If if is not the system
controller, the User Error bi,t will be set in the Error Flag
Register.
F8 - SREM - Set Interface To Remote Control
This command will set REN true and TCI true if this 8292 is
the system controller, If not, the User Error bit wi II be set in
the Error Flag Register.
Go To Idle
This command is used d\Jring the transfer of control
7-458
AFN·OO741D
inter
8292
Fe - ABORT - Abort All Operation, Clear Interface
This command will cause IFC to be asserted true for at
least 100 "sec If this 8292 Is the system controller. If It Is
In CIDS, It will take control over the bus (see the TCNTR
command).
FA - TCNTR - Take Control
The transfer of control procedure Is coordinated by the
master with the 8291 and 8292. When the master
receives a TCT message from the 8291, It should Isslle
the TCNTR command to the 8292. The following events
occur to take control:
1. The 8292 checks to see If It Is In CIDS, and If not, It
exits.
2. Then ATNI Is checked until It becomes high. If the
current controller does not release ATN for the time
specified by the Time Out Register, then a TOUT1
error is generated. The 8292 will return to this loop
after an error or any command except the RST and
RSTI commands.
3. After the current controller releases ATN, the 8292
will assert ATNO and CiC low.
4. Finally, the TCI interrupt is generated to inform the
master that it Is in control of the bus.
FC - TCASY - Take Control Alynchronoully
TCAS transfers the 8292 from CSBS to CACS Independent of the handshake lines. If a bus hang up Is detected
(by an error flag), this command will force the 8292 to
take controi (ass.ting ATN) even if the AH function is
not in ANRS (Acclptor Not Ready State). This command
should be used very carefully since It may cause the
loss of a data byte. Normally, control should be taken
synchronously. Atter checking the controller function
for being in the CSBS (else It will exit immediately),
~ will go low, and a TCI interrupt will be generated.
walt for at least 1.5I'8ec. (T10) and then ATNO will go
low. If DAV does notllo low, a TOUT3 error will be
generated. If the 8292 successfully takes control, it sets
TCI true.
FE - STCNI - Start Counter Interrupti
This command enables the internal counter interrupt.
The counter Is enabled by the GSEC co",!mand.
UTILITY COMMANDS All these commands are either Read or Write to registers
in the 8292. Note that writing to the Error Mask Register
and the Interrupt Mask Register are done directly.
E1 - WTOUT - Write To Time Out Regllter
The byte written to the data bus buffer (with Ao= 0)
following this command will determine the time used
for the time out function. Since this function Is implemented in software, this will not be an accurate time
measurement. This feature is enable or disable by the
Error Mask Register. No Interrupts except for the IBFI
will be 'lenerated upon completion.
E2 - WEVC - Write To Event Counter
The byte written to the data bus buffer (with Ao=O)
following this command will be loaded into the Event
Counter Register and the Event Counter Status for byte
counting or EOI counting. Only IBFl will indicate
completion of this command.
E3 - REVC - Read Event Counter StatUI
This command transfers the contents of the Event
Counter Into the data bus buffer. A TCI is generated
when the data is available in the data bus buffer.
FD - TCSY - Take Control Synchronoully
-There are two different procedures usad to transfer the
8292 from CSBS to CACS depending on the state of the
8291 In the system. If the 8291 is in "continuous AH
cycling" mode (Aux. Reg. AO = A1 = 1), then the
following procedure should be followed:
1. The master microprocessor stops the continuous AH
cycling mode in the 8291;
2. The master reads the 8291 Interrupt Status 1
Register;
3. If the END bit is set, the master sends the TCSV'
command to the 8292;
4. If the END bit was not set, the muter reads the 8291
Data In Register and then waits for another BI
Interrupt from the 8291. When It occurs, the master
sends the 8292 the TCSY command.
If the 8291 Is not In AH cycling mode, then the master
lust waits for a BI interrupt and then sends the TCSY
command. After the TCSY command has been issued,
the 8292 checks for CSBS. If CSBS, then it -exits the
routine. Otherwise, it then checks the DAV bit in the
GPIB status. When DAV becomes false, the 8292 will
7-459
E4 - RERF - Read Error Flag Regllter
This command transfers the contents of the Error Flag
Register into the data bus buffer. A TCI Is generated
when the data is available.
E5 - RINM - Read Interrupt Malk Reglater
This command transfers the contents of the Interrupt
Mask Register into the data bus buffer. This register is
available to the processor so that it does not need to
store this information elsewhere. A TCI Is generated
when the data Is available In the data bus buffer.
E8 - RCST - Read Controller StatUI Regllter
This command transfers the contents of the Controller
Status Register Into the data bus buffer and a TCI interrupt Is generated. '
E7 - RBST - Reed GPIB BUI StatUI Regllter
This command transfers the contents of the GPIB Bus
Status Register into the data bus buffer, and a TCI
interrupt is generated when the data is available.
'
AFN-00741D
inter
8292
E8 .... RTOUT - Read Time Out Status Regllter
This COlTlm~nd transfers the contents of the Tlm'e Out
Status Register Into the data bus buffer, and a TCI
Interrupt Is generated when the data Is available.
EA - RERM - Rud Error Malk Register
This command transfers the contents of the Error Mask
Register to the data bus buffer so that the processor
does not need to store this Information elsewhere. A TCI
Interrupt Is generated when the data is available.
Interrupt Acknowledge
.SYC
'I
ERR
SAO
EV
IFCR
I
1
Each named bit In an Interrupt Acknowledge (lACK)
corresponds to a flag in the Interrupt Status Register.
When the 8292 receives this command, it will clear the
SPI and the corresponding bits In the Interrupt Status
Register. If not all the bits were cleared, then the SPI will
be set true again. If the error flag is not acknowledged
by the lACK command, then the Ij:rror Flag Register will
be transferred to the data bus buffer, and a TCI will be
generated.
NOTE: XXXX1X11 Is an undefined operation or utility
command, so no conflict exists between' the lACK
operation and utility commands.
With' tlieflrst group, the TCI Interrupt will be used to
,ndicat,e that the required respol)se Is ready In the data
bus 'buffer and the master may continue and read it.
With the second group. the Interrupt will be used to
Indicate completion of the required taSk, so that the
master may send new commands.
The SPI should be used when immediate information or
special events Is required (s" the Interrupt Status
Register).
"Polling Status" Baaed Communication
When interrupt based communication is not desired, aH
Interrupts can be masked by the interrupt mask regIster.
The communication with the 8292 is based upon
sequential poll of the interrupt status register. By
testing the OBF and IBF flags, the data bus buffer
status is determined while special events are deter·
mined by testing the other bits.
Receiving IFe
The IFC pulse defined by the IEEE-488 standard is at
least 100 ,..sec. In this time, all operation on the bus
should be aborted. Most important, the current control·
ler (the one that is in charge at that time) should stop
sending ATN or EOI. Thus, IFC must externally gate CIC
'(controller in charg~) and ATNO to ensure that this
occurs.
Reset and Power Up Procedura
After the 8292 has been reset either by the external reset
pin, the device bei(1g .powered on, ot a RST command,
the following sequential events will take. place:
. SYSTEM OPERATION
8292 To Master Processor Interface
Communication between the' 8292 and the Master
Processor can be either Interrupt based communication
or based upon polling the interrupt status register in
predetermined intervals.
Interrupt Based Communication
Four different interrupts are available from the 8292:
OBFI
IBFI
TCI
SPI
Output Buffer Full Interrupt
Input Bll1fer Not Full Interrupt
Task Completed Interrupt
Special Interrupt
Each of the Interrupts Is enabled or dl.sabled 'by a bit in
the Interrupt mask register. Since OBFI and iBFi are
directly connected to the OBF and IBF flags, the master
can write a new command to the. Input data bus buffer
as soon as the previc;>us command has been read.
The TCI Interrupt Is useful when the master is:sendlng
commands to the 8292. The pending TCI will be cleared
with each new command written to the 8292. eommands
sent to the 8292 can be divided into two major'groups:
1. Commands that require response back'from the 8292
to the master, e.g., reading register.
2. Commands that Initiate some action or enable
features but do not require response back from the
8292, e.g., enable data b4s buffer Il)terrupts.
1. All outputs to the GPIB interface will go high (S'Im',
ATm, TI=c, SYC, CLTH, ATm5, CIC, TCI, SPI, EOi,
OBFI, mFT, DAV, l1EV).
.
2. The four interrupt outputs (TCI, 8PI, OBFI, IBFI) and
CLTH output will go low.
3. The following registers will be cleared:
Interrupt Status
Interrupt Mask
Error Flag
Error Mask
Time Out
Event Counter (= 256), Counter is disabled.
4. If the 8292 is the system controller, an ABORT
command will be executed, the 8292 will become the
controller In charge, and it will ent~r the CACS state.
If it is not the system controller, it will remain in
cms.
System Configuration
The 8291 and 8292 must be interfaced to an IEEE-488
bus meeting a variety of specifications Including drive
capability and loading characteristics. To interface the
8291 and th~ 8292 without the 8293's, several external
gates are .req",ired, ~sing a configuration similar to that
used in Figure 5.
7-460
AFN-00141 0
intJ
8292
GPI8
TRANSCEIVERS
NOTE 1
31
EOI
3b
ATN
30
NDAC
3d
NIIFD
f4.7K
PROCESSOR
INTERRUPT
BUS
Viii Ii6 RST CLK ADD DATA
...
1\
! Rio
I-I-- I-----<~I RS,
I-- /----o..IRS,
I-- 1----0..1CLOCK
'--
r--- r-
')1
1----1'"1 RESET
":7
r-
t----IWR
/----iINT
I·f-
Ci
IDiO
.~
f9TDAV
I - I-----<'"Iiiii
I-
45
ATN
I-I--
CLTH
j.
L:==~DATA
rU
-
1 . j - - - - - - I..IAo
.r-----ICi
iiii
L--+--------IIVWRWR
SPI
~--------I~RESET
~--~
1d
EOI
,.
IFC
.-----1 X,
6T
SYC
t
NOTES:
1. CONNECT TO NDAC FOR
BYTE COUNT OR TO EOI
FOR 8LOCK COUNT.
2. GATE ENSURES OPEN
COLLECTOR OPERATION
DURING PARALLEL POLL.
tw;
.----tEA
~
,.
T'--_-lii
SRQ
T, ....;CO:U=N:..:.T_ _ _ _---'
_T.I_!!:IF~C!:.L--------J
....
'--_
UK
SYSTEM. ON
CONTROLLER
-....,.
",,---'
SWITCH
OFFi
Figure 4. 8291 and 8292 System Configuration
7-461
AfN.OO741D
8292
TO MICROPROCESSOR
.1!
..!!
~
~
18
17
18
19
21
22
23
9
lD
4
TO
MICROPROCESSOR
6
28
25
29
23
Di03
Di04
30
10
31
9
8
D5
DiOs
32
D6
DI06
33
7
34
6
35
5
1
1
DO
,Di01
Dl
DI02
D2
D3
D4
D7
RSO
DI07
8291
RSI
TlRI
RS2
RD
DAY
WR
EOI
ill
RESET
DREO
7
DACK
8
3
11
DiOa
SRO
IFC
CS
NDAC
CLOCK
NiiFD
INT
TlR2
GPI B
TRIGGE R
OUTPU T
5
TRIG
REN
36
24
39
3
26
4
DO
DAV
17
18
19
9
8
10
".....
TO
MICROPROCESSOR
4
8
~
~
.E.
r-
32
I
33
35
36
11
OSCILLATO R
OUTPU T
Vee
--.!.
15,25 pF
±r
9
D7
liEN
8292
IFC
lIi'NO
COUNT
CS
EOl2
TCI
ATNI
6293
DI08'
.!!..
DAY'
1!...
T/RI
DAY
EOI
ATN
E-ycc
~TNO
OPTA
IFCL
OPTB l ! . v ec
MODE 3'
ATN
21
8
38
6
23
5
29
23
39
3
34
7
22
11
~I
NDAC
NDAC
Jmili
NRFD
.lL
SRO
SRO'
.1!..
REN
REN'
2
SRO
TO
IEEE'488
BUS
DI07' E-
DI07
4
D6
TlR2
IFC
8293 ,
ATNO
TO
E - I EEE·488
BUS
.!!..
.1!..
EOI' .!i.
IFC'
ATN'
EOI
EOl2
ATNI
SPI
OBFI
IBFI
SYNC
SS
x,,
¥, x,,
~
DI06
t---!' TiR1
10
D5
WR
ReSEr"
DI05
37
2
D4
AO
DI03
Di04
DI08
~
.!!.
DI03' .!!.
DI04' .lL
DI05' .1!..
DI06' .!i.
36
Dl
RD
DI02'
24
~ D2
~ D3
16
DI01'
DI02
27
,
Jl.
-1!
Di01
EA
iffi
CIC
CLTH
SYC
1
25
31
24
27
21
24
22
IFCL
CIC
E...vs
CLTH
OPTA
SYC
OPTB l!.ve
MODE 2
U eON
SYSTEM
CONTROLLER
SWITCH
0FF
.i
'= GPIB BUS TRANSCEIVER
,= SEE 8041A DATASHEET FOR ALTERNATE
CRYSTAL CONFIGURATIONS
"=CAN CONNECT TO SYSTEM RESET SWITCH,
SEE 8041 A DATA SHEET
Figure 5, ,8291, 8292, and 8293 System Configuration
7-462
AFN·OO741D
inter
8282
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ...•..... O·C to 70·C
Storage Temperature ............. -65·C to +150·C
Voltage on Any Pin With Respect
to Ground ...................•....... 0.5V to + 7V
Power Dissipation ......................... 1.5 Watt
D.C. CHARACTERISTICS
(TA
'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification Is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
= O"C to 70"C, Vss = OV: 8292, Vee = :l:5V :1:10%)
Paramater
Symbol
Min.
Max.
Unit
-0.5
0.8
V
-0.5
Teat Conditions
VIL'
Input Low Voltage (All Except X" X2, ~
VIU
Input Low Voltage (X" X2t
0.6
V
VIHl
Input High Voltage (All Except X" X2, ~
2.2
Vee
V
VIH2
Input High Vol,tage (Xl, X2, mET)
3.8
,Vee
V
VO L1 '
Output Low Voltage (00-07)
0.45
V
IOL=2.0 mA
VOU
Output Low VOltage (All Other Outputs)
0.45
V
IOL=1.6mA
VOH'
V OH2
Output High Voltage (00-07)
2.4
V
10H= -400,.A
Output High Voltage (All Other'Outputs)
2.4
V
IlL
Input Leakage Current (COUNT, TFCl, RD, WR, CS, Aol
:1:10
,.A
Vss CO;; VIN
loz
Output Leakage Current (0 0-07, High Z State)
:t:10
,.A
Vss+ 0.45< "IN CO;; Vee
ILll
Low Input Load Current (Pins 21-24, 27-3S)
0.5
mA
VIL=0.8V
ILI2
Low Input Load Current (RESEn
0.2
mA
VIL=0.8V
lee
Total Supply Current
125
mA
Typical = 65 mA
IIH
Input High Leakage Current (Pins 21-24, 27-38)
100
/LA
~N = Vee
CIN
Input Capacitance
.10
pF
CI/O
I/O Capacitance
20
pF
mET)
10H= -50,.A
CO;;
Vee
/ A.C. CHARACTERISTICS (TA = O"C to 70"C, Vss = OV: 8292, Vee = +5V :1:10%)
DBBREAD
Symbol
tAR
' Parimeter
CS,
Min.
Ao Setup to ROt
Max:
Unit
0
ns
0
ns
Tes' Co"dltlons
tRA
CS, AD Hold After Rot
tRR
RD Pulse Width
tAD
CS, AD to Data Ouf Delay
225
ns
CL= 150 pF
tRO
RO~ to Data Out Delay
'225
ns
CL= 150 pF
tOF
ROt to Data Float Delay
100
ns
tey
Cycle Time
2.5
15
,.s'
Min.
Max.
Unit
ns
250
DBBWRITE
Symbol
Parameter
tAW
CS, AD Setup to WR~
tWA
CS, AD Hold After WRt
tww
WR Pulse' Width
tow
Data Setup to WRt
.two
,
Data Hold After WR~
7-463
0
ns
0
ns
250
ns
150
ns
0
ns
Test Conditions
AFN-00741D
inter
8282
,
e-lion
CCIdtt
E1'
'E2
E3
E4
E5
E8
E7
N8h
TIme
imt
WTOUT
WEVC
53
53
Z4
Z4
REVC
RERF
71
87
24
'24
TCP!
&PI
:ue
~
In'
AIR
mi
1iAV
,
C-.nII
51
47
RINM
69
Z4
49
RCST
RBST
97
24
77
92
24
72
RTooT
REAM
Z4
49
49
E8
FO
SPeNI
F1
GIOL
F2
RST
69
89
53
88
94
F,2
RST
214
19
EA
24
Z4
Count ~After 39
24
70
24
24
24
192
107
181
, 181
152
152
1174
.179
Not System Controller
System Controller
1101
F3
RSTI
81
F4
GSEC
125
24
F5
EXPP
75
24
Fe
F7
Fe
F9
GTSB
118
24
100
SLOC
73
24
55
Me
SREM
91
24
73
184
ABORT
155
24
133
FA
TCNTR
108
24
88
1120
171
FC
TCAS
92
24
87
155
FO
TCSY
115
24
91
~
FE
STCNI
24
PIN
RESET
59
29
X
lACK
118
198
~
155
t59
187
191
1115
••
142
Sterta Count After 43
17
17
Not~tem Controller
173
If Interrupt Pending
t88
Notel:
1, All times are multlpl•• of tov lrom the 8041A commend Interrupt,
2, TCI claara .Iter 7 tov on all commands.
3. t Indlcat.. a level tranlltlon lrom low to high. I Indlcat.. a high to low transition.
A.C. TE~TING INPUT, OUTPUT WAVEFO~M
A.C. TESTING LOAD CIRC~IT
,
INPUT/OUTPUT
u
~2'0
0.8
0.45
>
TESTPOINTB< 2.0
)C
DEVICE
UNDER
TEST
0.8
,
A C TESTING INPUTS ARE DRIVEN AT 2,4V FOR A lOGIC I AND 0 45V FOR
A lOGIC 0 TIMING MEASUREMENTS ARE MADE AT 2 OV fOR A lOGIC I
AND 0 BV FOR A lOGIC 0
11"
~lINClUDES JIG CAPACITANCE
,
7-464
AfN.OO741D
inter
8292
CLOCK DRIVER CIRCUITS
CRYSTAL OSCILLATOR MODE
DRIVING FROM EXTERNAL SOURCE
+5V
r-----
< 15 pF
(INCLUDES XTAL,
SOCKET, STRAY)
XTAL1
I
I
I
4702
.J...
1>--+----....::..tXTAL1
"'T"
I
+ 5V
I
I
L ____ _
15-25pF
(INCLUDES SOCKET,
STRAY)
47D2
I
'----+---'-1 XTAL2
':'
BOTH XTAL 1 AND XTAL2 SHOULD BE DRIVEN
RESISTORS TO Vee ARE NEEDEO TO ENSURE V,H = 3,BV
IF TTL GlRCUITRY IS USED
CRYSTAL SERIES RESISTANCE SHOULD BE
<75Q AT 6 MHz; <18OQ AT 3.8 MHz
LC OSCILLATOR MODE
..b...
.£.
45 ..H
20pF
120 .. H
20pF
~::~td'
C,_£+3Cpp
3 XTAL2
Cpp ~ 5 - 10 pF PIN TO PIN
CAPACITANCE
rIC L
':'
XTAL1
2
-
2
C
EACH C SHOULD BE APPROXIMATELY 20 pF. INCLUDING STRAY CAPACITANCE
WAVEFORMS
READ OPERATION-DATA BUS BUFFER REGISTER
Ao
Cs OR
(SYSTEM'S
ADDRESS BUS)
1_ _ _ _
.00 _ _ _ _ 1
I----.ov-----I
iiii
(READ CONTROL)
_"D~~
_'DF_~
~~1~~~~------------------~,r-------D-A-TA-V-A-L-,D------~.--------------------~------------------~
r
-Ul t. .~~~~~~~_-_~~~~~~~~.-..
WRITE OPERATION - DATA BUS BUFFER REGISTER
--A
CSORAo~E
(SYSTEM'S
~.- ':
(WRITE CONTROL)
'i-
_
1..-----------------------
twD
-'ow-I--;=\j
DATA VALlO
V
OATA
-'I'l.,...____________~{\'-------.;;M,;;;A;,,;.Y.;C,;,,;HA;,,;.N;;,;G;;;E;,,-.--______
OATA BUS
DATA
(INPUT) ____..;,.',;;;M,;,,;AY,;,.C,;;;H,;;A;;.N;;;G,;;E_____
7-465
AFN-D07410
inter
8~2
APPENDIX
The following tables and state diagrams were taken
from the IEEE Standard Digital Interface for, Program,
mabie Instrumentati~n, I,EEE Std. 488-1978. This doclI'
ment Is the official standard for the GPIB tills and can be
'purchased from IEEE, 345 East 47th St., New York, NY
10017.
C MNEMONICS
Messages
=
=
pon power on
rsc
request system control
rpp = request parallel poll
gts
go to standby
tca
take control asynchronously
tcs = take control synchronously
sic = send Interface clear
sre = send remote enable
=
=
IFC = interface clear
ATN = attention
TCT = take control
Interface States
CIDS
CADS
CTRS
CACS
CPWS
CPPS
CSBS
CSHS
CAWS
CSWS
CSRS
CSNS
SNAS
SACS
SRIS
SRNS
SRAS
SIIS
SINS
SIAS
=controller idle state
=controller addressed state
=controller transfer state
=controller active state
=controller parallel poll walt state
=controller parall,,1 poll state
= controller standby state
= controller standby hold state
=controller active walt state
= controller synchronous wait state
= controller service requested state
=controller service not requested state
= system control not active state
= system control active state
= system control remote enable Idle IItate
=system control remote enable not active state
= system control remote enable active state
=system control interface clear Idle state
=system control interface clear not active state
=system control Interface clear active state
=
~ accept data state (AH function)
CAID@ = acceptor not ready state (AH funptlon)
~ = source delay state (SH function)
(§!BID = source transfer state (SH function)
C!N2ID = talker addressed ,state (T function)
SRQ
~Q
O~
...
• T'0 > 1.614et
, THE MICROPROCESSOR MUST WAIT FOR THE 80
INTERRUPT BEFORE WRITINQ THE arsB OR GSEC
COMMAHDa TO ENSURE THAT ,IITIII A 111ft)
IS TRUE,
Figure A.1. C State Diagram
7-466
AFN-007410
inter
8292
REMOTE MESSAGE CODING
Mnemonic
T
Y
P
E
Message Name
ACG
ATN
DAB
Addressed Command Group
Attention
Data Byte
DAC
DAV
DCl
END
EOS
Data Accepted
pata Valid
Device Clear
End
End of String
GET
GTL
lOY
IFC
LAG
LLO
MLA
Group Execute Trigger
Go to Local
Identify
Interface Clear
Listen Address Group
Local lock Out
My Listen Address
(Note 3)
MTA
My Talk Address
(Note 4)
MSA
My Secondary Address
NUL
OSA
OTA
PCG
PPC
PPE
(Notes 1, 9)
c'
L
A
S
S
DONN
I
lORD
o
0 AFA
8 7 8 5 4 3 2 1 VOC
M AC
Y 0 0 0 X X X X
U
X X X X X X X X
ODD 0 D D D D
8765432 1
X X X X X X X X
XXXXXXXX
Y 0 0 1 0 1 0 0
X X X X X X X X
E E E E E E E E
M
UC
DO
U
HS
U HS
M UC
U
(Notes 2, 9)
'Bus Signal llne(s) and Coding That
Assertl! the True Value of the Message
ST
M DO
M
M
U
U
M
M
M
Y 0 0 0
X X X X
X X X X
Y 0 1 X
Y 0 0 1
Y 0 1 L
M
AD
Y
SE
Y
M DO
o
M
Null Byte
Other Secondary Address
Other Talk Address
Primary Command Group
Parallel Poll Configure
Parallel Poll Enable
SE
AD
(Note 6)
M
M
M
M
M
AC
SE
Y
PPD
Parallel Poll Disable
(Note 7)
M
SE
Y
PPR1
PPR2
PPR3
PPR4
PPR5
PPR6
PPR7
PPR8
PPU
flEN
RFD
ROS
SCG
SOC
SPD
SPE
SRO
STB
Parallel Poll Response 1
Parallel Poll Response 2
Parallel Poll Response 3
Parallel Poll Response 4
Parallel Poll Response 5
Parallel Poll Response 6
Parallel Poll Response 7
Parallel Poll Response 8
Parallel Poll Unconfigure
Remote Enable
Ready for Data
Request Service
Secondary Command Group
Selected Device Clear
Serial Poll Disable
Serial Poll Enable
Service Request
Status Byte
U
ST
ST
ST
ST
ST
ST
ST
ST
UC
UC
HS
ST
SE
AC
UC
UC
ST
ST
X
X
X
X
X
X
X
1
Y
X
X
X
Y
TCT
TAG
UCG
UNL
UNT
Take Control
Talk Address Group
Universal Command Group
'
Unlisten
Untalk
(Note 10)
U
U
U
U
U
M
U
(Note 9)
U
U
M
M
M
M
U
(Notes 8, 9)
M.
M
M
M
(Note 11)
M
M
1 X X X X
oXX XX
XXO
1XX
XXX
XXX
XXX
X X X X
X X X X
1 X X X
o 1 X X
oX X X
X
X
X
X
X
0
X
X
X
0
L
0
X
X
X
0
L
X X
X'X
1 X
X X
X X
X X
X X
X
X
X
X
X
X
X
XXX
1 XXX
X XXX
X XXX
X XXX
1 XXX
LXXX
5 4 3 2 1
(Note 5)
U
U
0
X
X
X
0
L
0 T T T T T
5 4 3 2 1
S S S S S
Y
Y
Y
X
S
8
AC' Y
AD Y
UC Y
AD Y
Y
AD
XXX
1
X
X
1
1
1
X
X
X
1
X
X
X
xX X X
XXX
X X
54321
0 0 0 0 0 0 0 XXX X X X
(OSA = SCG A MSA)
(OTA TAG AMTA)
(PCG ACG v UCG v LAG v TAG)
0 0 0 0 1 0 1 XXX 1 X X
1 lOS P P P XXX 1 X X
321
1
1 DOD D XXX
X X
432 1
X
X X X X X X 1 XXX
X X X X X 1 X XXX
X
X X X X 1 X X XXX
X
X X X 1 X X X XXX
X
X X 1 X X X X XXX
X
X 1 X X X X X XXX
X
1 X X X X X X XXX
X
X X X X X X X XXX
1 X
0 0 1 0 1 0 1 XXX 1 X X
X X X X X X X XXX X XX
X X X X X X X XOX X X X
1 X X X X X X XXX o X X
1 1 X X X X X XXX 1 X X
0 0 0 0 1 0 0 XXX 1 X X
0 0 1 1 0 0 1 XXX 1 X X
0 0 1 1 0 0 0 XXX 1 X X
X X X X X X X XXX X X 1
X S S S S S S XXX o X X
654 3 2 1
0 0 0 1 0 0 1 XXX
X X
X X
lOX X X X X XXX
0 0 1 X X X X XXX
X X
0 1 1 1 1 1 1 XXX
X X
1 0 1 1 1 1 1 XXX
X X
=
Y
xXXX
XXX
XXX
XXX
8 7 6 5 4 3 2 1
Y 0 0 0 1 0 0 0
AC
AC
UC
UC
AD
UC
AD
A E SIR
TOR F E
N I Q C N
X X
X X
=
X X
X X
X X
X X
XX
XX
X
X
X
X
X
X
X
X
X
X
XX
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X X
X X
X X
X X
X X
The 1/0 coding 'on ATN when sent concurrent with multiline messages has been added to this revision for interpre·
tive convenience.
7-467
AFN-00741 0
8292
NOTE8:
1.
2,
3.
4.
5.
6:
01-08 specify the device dependent data bits.
E1-E8 specify the device dependent code used to indicate the E08 message.
L1-L5 specify the device dependent bits of the device's listen address.
T1-T5 specify the device dependent bits of the device's talk address.
81-85 specify the device dependent bits of the device's secondary address.
8 spec.ifies the sense of the PPR.
Response
=8 EEl ist
/
P1-P3 specify the PPR message to be sent when a parallel poll is executed.
P3
o
P2
0
P1
0
PPR Message
PPR1
PPR8
7.
01-04 specify don't-care bits that shall not be decoded by the receiving device. It is recommended that all zeroes
be sent.
8. 81-86, 88 specify the device dependent status. (0107 is used for the RQ8 message.)
9. The source of the message on the ATN line is always the C function, whereas the messages on the 010 and EOI
lines are enabled by the T f u n c t i o n . '
' .
10. The source of the messages on the ATN and EOI lines is always the C function, whereas the source of the
messages on the 010 lines is always the PP function,
11. This code is provided for system use, see 6.3.
7-468
AFN-00741D
intJ
8293
GPIB TRANSCEIVER
• Nln. Open-coll.ctor or Th .....stat.
Lin. Drlv.,.
• On-chip D.cod.r for Mod.
Configuration
• 48 mA Sink Current Capability on
Each Lin. Drlv.r
• Pow.r Up/PoW.r Down Protection to
Prev.nt Disrupting the IEEE Bus
• Nln. Schmitt-type Lin. R.c.lv.,.
• Conn.cts with the 8291A and 8292 to
Form an IEEE Standard 488 Int.rfac.
Talk.r/L1st.n.r/Controll.r with no
Additional Compon.nts
• High Capacitance Load Drlv.
Capability
• Singi' 5V Pow.r Supply
• Only Two 8293's R.qulred per GPIB
Int.rface
• 28-Pli'I Packag.
• On-Chip IEEE-488 Bus T.rmlnatlons
• Low Pow.r HMOS D.slgn
The Intel8 8293 GPIB Transceiver is a high-current, non-inverting buffer chip designed to interface the 8291A GPIB
Talker/Listener, or the 8291A/8292 GPIBTalker/Listener/Controller combination, to the IEEE Standard 488-1978Instrumentation Interface Bus. Each GPIB Interface would contain two 8293 Bus Transceivers. In addition, the 8293 can also be used
as a general-purposa bus driver.
r--
II
DMA
CONTROLLER
(OPTIONAL)
I
IL _____II
DREQ
I2IIIA
GPl8
TALICER/
LI8TENIR
II2fI2
Gpta
CONTROLLER
Tllll
TIR2
!Oi
mi
DATAl
DATA2
DATAl
3
7
ausa
T/Ill
GND
BUSI
BUSS
BUS2
GENERAL PURPOSE INTERFACE BUS
Figure 1. 8291A, 8292, 8293 Block Diagram
Figure 2. Pin' ConflgUraUon
7-489
i~
8293
t,
Table 1. Pin Description
~I Pin No.
1ftIe
Name and function
BUS1BUS9
12,13,
15-19,
21,22
VO
OATA1DATA10
5-11,
23-25
I/O,
1
I
lI'anamlt Racelva 1: This pin C9ntrols'the direction for NDAC, NRFD,
DAV, and DI01-DlqB. Input III ,TTL
compatible.
2
I
"",!,.m.1t R.cel~" 2: This pin controIS 'the direction for EO!. Input Is
Tlftl
'
1
TIft!
GPIB U.s, GPIB SIde: These arl! '
the IEEE-488. bus Int!lrface,
driver/receivers" or 'Tl\..comp"tlbJ" .
Inputs on the 8291A/8292 side,
depending on the mode used. Their
use 18 programmed by the two mode
~Iect pins, OPTA and OPTB.
,
GPIB Un.." a!!1A,192SIdIl: T~eset
are th'e pins to be connects
TO
PROCESSOR
BUS
GPIB
Figure 4, Talker/Listener/Controller Configuration
7-471
Neme and Function
T/Rl
AFN.()0825C
inter
8293
Table 3. Mode 0 Pin Description (Continued)
Pin
Symbol No, lYpe
NRFO-
T/R2
17
VO
I
2
Neme end Funcllqn
Not Reedy For D~te: IEEE GPIB bus
handshake control line, When an Input,
It is a TTL compatible Schmitt-trigger.
When an output, it is an open-collector
driver with a 48 mA current sinking
capability.
'1l'enamlt ReeelVe 2: Direction control
.for EOI. If T/R2 is high, EOI- is sending.
Input is TTL compatible.
EQI
3
VO
End Or Identify: Processor GPIB bus
control line; is used by a talker to indicate the end of a multiple byte ·transfer.
This pin is TTL compatible.
EOI-
15
I/O
End Or Identify: IEEE GPIB bus control
line; Is used by a talker to indicate the
end of a multiple byte transfer. This pin Is
a three-state (push-pull) driver capable
of sinking 48 mA and a TTL compatible
receiver with hysteresis.
:
SRO
SRO-
REN
8
16
6
I
0
0
Service Request: Processor GPIB bus
control line; used by a device to indicate
the need for service and to request an
interruption of the current sequence of
events on the GPIB. It IS a TTL compatible input.
Service Request: IEEE GPIB bus control line; it is an open collector driver
capable of sinking 48 mAo
Remote Enable: Processor GPIB bus
control line; used by a controller(in conjunction with other messages) to select
between two alternate sources of device
programming dllta (remote or local control). This output is TTL compatible.
REN-
13
I
Remote Enable: IEEE GPIB bus control
line. This input is a TTL compatible
Schmitt-trigger.
ATN
4
0
AHl!lntlon: Processor GPIB bus control
line; used by the 8291 to determineho\y
data on the 010 signal lines are to be
interpreted. This is a TTL compatible
output.
ATW
19
I
Attention: IEEE GPIB bus control line;
this input is a TTL compatible Schmitttrigger.
IFC
5
0
Interface Clear: Processor GPIB bus
control line; used by a controller to
place the interface system into a known
quiescent state. It is a TTL compatible
output.
Pin
Symbol No, lYpe
Neme and Function
IFC-
12
L
I"terfeee Cleer: IEEE GPIB bus control
line. This input is a TTL compatible
Schmitt-trigger.
T/i!iIOl
T/RI02'
11
23
I
I
transmit Receive General 10: Oiraction control for the two spare transceivers. These pins are TTL compatible.
G101'
Gi02
24
25
VO
General 10: This is the TTL side of the
two spare transceivers. These pins are
TTL compatible.
G101GI02-
21
22
I/o' Generel 10: These are spare threeI/O state (push-pull) drivers/Schmitt-trigger
receivers. The drivers can sink 48 mAo
I/O
MODEl
OPTA
OPTB
IDIii
24
TIAI
lii01
1i'io,
IDll3
I!m4
fiiOs
fiiOs
liiQ,
mlJo
2S
22
23
I.
10
18
17
18
15
13
12
0101'
0102'
0103'
0104-
0105'
0108'
0107'
0108'
EOi
Figure 6, Talker/LIstener Data Configuration
AFN·0082SC.
inter
8293
Table 4. Mode 1 Pin Description
MOOE2
Symbol
T/Rl
EOI
ATN
DAY
DAY"
0101-
i5i08
0101"0108"
Pin
No.
Type
Name and Function
1
I
Tran.mlt Receive 1: Controls the di·
rection for DAY and the 010 lines. If
T/FI1 is high, then all these lines are
sending information to the IEEE GPIB
lines. This Input is TTL compatible.
3
4
24
21
I
I
I/O
I/O
25,23,
10, 9,
8, 7,
6, 5
I/O
22,19,
18,17,
16,15,
13,12
1/0
27
OPTA
28
OPTB
18
17 NRFO'
RIII'II
End Of Sequance And Attantlon:
Processor GPIB control lines. These
two control signals are ANOed to·
gether to determine whether all the
transceivers in the 8293 are three·
state (push·pull) or open-collector.
When both signals are low (true),
then the controller is performing a
parallel poll and the transceivers are
all open-collector. These inputs are
TTL compatible.
NOAC'
T/RI
12
I1'll
IFC·
SYC
13 REN'
mi
18
SliQ
1iTRI
19 ATN'
l\TFI
Data Valid: Processor GPIB bus
handshake control line; used to indicate the condition (availability and
validity) of information on the 010
lines. It is TTL compatible.
SRO'
15 EOI'
!OIl
mm
Data valid: IEEE GPIB bus handshake control line. When an input, it
is a TTL compatible Schmitt-trigger.
When DAY" is an output, itcansink48
mA.
Em
T/1I2
Data Input/Output: Processor GPIB
bus data lines; used to carry message
and data bytes in a bit-parallel byteserial form controlled by the ·three
handshake signals. These lines are
TTL compatible.
NOTE: FUNCTION OF ATN TRANSCEIVER
SIR = LOW
1iTRI=ATW
l'm=ATN'
ATN'=INPUT
A'I'iiIl5=INPUT
Data Input/Output: IEEE GPIB bus
data lines. They are TTL compatible
Schmitt-triggers when used for input and can si~48 mA when used for
output. See ATN and EOI description for output mode.
SIR = HIGH
1iTRI = JrnIlj
l'm=HIGH
ATN'=AfI'IO
AfI'IO = INPUT
Figure 7. Talker/Listener/Controller Control
Configuration
7-473
AFN·00825C
8293
Table 5. Mode 2 Pin Description
Pin
Symbol No.
T/Rl
NOAC
"i'Ype
Name and Function
1
I
'Tfansmlt Receive 1: Direction control
for NOACand NRFO.lfT/Rl is high, then
NOAC and NRFO are receiving. Input is
TTL compatible.
10
I/O
Not Data' Accepted: Processor GPIB
bus handshake control line; used to indicate the condition of acceptance of
data by device(s). This pin is TTL compatible.
Pin
Symbol No.
CLTH 1 21
-Type
Name and Function
I
Clear Latch: Used to clear the I,FC Received latch after it has been recognized
by the 8292. Normally low (except after a
hardware reset). It will be pulsed high
when IFC Received is recognized by the
8292. This input is TTL compatible.
IFCL
25
0
IFC Received Latch: The 8292 monitors the IFC line when it is not the active
control/er through this pin.
NOAC'
18
I/O
Not Data Accepted: IEEE GPIB bus
handshake control line. It is a TTL compatible Schmitt-trigger when used for
input and an open-co lIector driven with a
48 rnA current sink capability when used
for output.
SRO
8
I/O
Service Requ~st: Processor GPIB controlline; indicates the need for attention
and requests the active controller
to interrupt the current sequence of
events on the GPIB bus. This pin is TTL
compatible.
mI"rn
9
I/O
Nol Ready For Data: Processor GPIB
bus handshake control line; used to indicate the condition of readiness of device(s) to accept data. This pin is TTL
compatible.
SRO'
16
I/O
NRFO'
17
I/O
Not Ready For Data: IEEE GPIB bus
handshake control line. It is a TTL compatible Schmitt-trigger when used for
input and an open-collector driver with a
48 mA current sink capability when used
for output.
Service Request: IEEE GPIB bus controlline. When used as an input, this pin
is a TTL compatible Schmitt-trigger.
When used as an output, it is an opencollector driver with a 48 rnA current
sinking capability.
T/R2
2
I
'TfansmM Receive 2: Controls the direction for EOI. This input is TTL compatible.
ATNO
23
I
Attention Out: Processor GPIB bus
control line; used by the 8292 for ATN
control of the IEEE bus during "'take
control synchronously" operations. A
Iowan this input causes ATN to be asserted if CIC indicates that this 8292 is in
charge. ATNO is a TTL compatible input.
ATNI
11
0
Attention In: Processor GPIB bus controlline; used by the 8292 to monitor the
ATN line. This output is TTL compatible.
ATN
4
0
Attention: Processor GPIB bus control
line; used by the 8292 to monitorthe ATN
line. This output is TTL compatible.
ATN'
19
I/O
Attention: IEEE GPIB bus control line;
used by a controller to specify how data
on the 010 signal lines are to be interpreted and which devices must respond
to data. When used as an output, this pin
is a three-state driver capable of sinking
48 rnA current. As an input, it is a TTL
compatible Schmitt-trigger.
SYC 1
22
I
System Controller: Used to monitor the
system controller switch and control the
direction for IFC and REN. This pin is a
TTL compatible input.
REN
6
I/O
Remote Enable: Processor GPIB control line; used by the active control/er
(in conjunction with other messages)
to select between two alternate sources
of device programming data (remote or
local control). This pin is TTL compatible.
REN'
IFC
IFC'
CIC
13
5
12
24
I/O
I/O
I/O
I
Remote Enable; lESE GPIB bus control
line. When used al;an input, thisisa TTL
compatible Schmitt-trigger. When an
output, it is a three-state driver with a 48
rnA current sinking capability.
.
Interface Clear: Processor GPIB bus
control line; used by the active controller to place the interface system into
a known quiescent state. This pin is TTL
compatible.
Interface Clear: IEEE GPIB control
line. This is a TTL compatible Schmitttrigger when used for input and a threestate driver capable of sinking 48 rnA
current when used for output.
Controller In Charge: Used to control
the direction of the SRO and to indicate
that the 8292 is in charge of the bus. CIC
is a TTL compatible input.
EOl2
7
I/O
End Or Identify 2: Processor GPIB bus
control line; used in conjunction with
ATN by the active controller (the 8292) to
execute a polling sequence. This pin is
TTL compatible.
EOI
3
I/O
End Or Identify: Processor GPIB bus
control line; used by a talker to indicate
the end of a multiple byte transfer sequence. This pin is TTL compatible.
NOTES:
1. VIL3 is guaranteed at 1.1 Von these inputs to accommodate the
high current-sourcing capability of these pins during a low
Input in Mode 2.
• 7-474
AFN·00825C
inter
8293
Table 6. Mode 3 Pin Description
Table S. Mode 2 Pin Description (Continued)
Pin
Symbol No. ~
Name and function
EOI'
15
1/0 End Or Identify: IEEE GPIB bus control
line; used by a talker to Indicate the end
of a multiple byte transfer sequence or,
by a controller in conjunction with ATN,
to execute a polling sequence. When an
output, this pin cen sink 48 mA currant.
When an input, It is a TTL compatible
Schmitt-trigger.
mm
Pin
No.
~e
Name and Function
TiR1
1
I
Transmit Receive 1: Controls the direction for OAV and the 010 lines. If
T/R1 is high, then all these lines are
sending information to the IEEE GPIB
lines. This input is TTL compatible.
Eoi
3
4
I
I
End Of Sequence and Attention:
Processor GPIB control lines. These
two control lines are ANOed together
to determine whether all the transceivers In the 8293 are push-pull or
open-collector. When both signals
are low (true), then the controller IS
performing a parallel poll and the
transceivers are all open-collector.
These inp,uts are TTL compatible.
11
I
Attention Out: Processor GPIB control line; used by the 8292 during
"take control synchronously" operations. This pin is TTL compatible.
IFCL
2
I
Interfec!I Clear Latched: Used to
make OAV received after the system
controller asserts IFC. This input IS
TTL compatible
OAV
24
1/0
Data Valid: Processor GPIB handshake control line; used to indicate
the condition (availability and
validity) of information on the 010
signals. This pin is TTL compatible.
OAV*
21
I/O
Data Valid: IEEE GPIB handshake
control line. When an input, this pin is
a TTL compatible Schmitt-trigger.
When OAV' is an output, it can Sink 48
mAo
0101-
25,23,
10, 9,
8, 7,
6, 5
1/0
Data Input/Output: Processor GPIB
bus data lines; used to carry message
and data bytes in a bit-parallel byteserial from controlled by the three
handshake Signals. These lines are
TTL compatible.
22,19.
18.17.
16.15.
13,12
1/0
Data Input/Outpu\: IEEE GPIB bus
data lines. They are TTL compatible
Schmitt-triggers when used for Input
and can sink 48 mA when used for
output.
Symbol
A'i'N
OPTA
OPTa
m:t
Z1
DAY
OAV'
A'i"fm
TIII1
iiiO;
010,
010.
211
21
13
I'
0102'
10
l'
0103'
17
010,
iiiOs
010.
•
11
7
15
13
010,
12
010.
D101·
0104'
0105'
0108'
010"
OIOB
0108'
0101'
0108'
Figure 8. Talker/Listener/Controller Data
Conflguratlo~,
7-475
AFN-00825C
inter
8~3
25
2~
10
9
8
. ..2!
-.!!
....!i
.J.!
IZI1A
DO
i!ml
01
Di02
02
0103
iii04
Di05
6i06
Di07
03
.~ 04
....!!.
05
~ 06
....!!
.2!
TO
MICROPROCESSOR ..B.
INTERFACE 2!
2
2
.J!
...!!
-2.
07
RSO
DAY
RSl
T/lil
RS2
ATN
cs
EOI
iffi
TiR2
INT
CLOCK
OREa
r2L
6
r1!30
.
31
5
24
1
32
34
0102"
i!i03
0103"
iii04
0104"
0105
0105"
35
E..
2!....
2!..
2!-
0106
0106"
0107
0107"
~
~
~
E-
0108
0106"
DAY
DAY"
TIRl
OPTA
OPTB
TO
IEEE·488
BUS
~
a
Vee
~ GNO
MODEl
36
1
28
39
3
2
L.....--.!.
1
NRFi5
37
2
iRQ
27
10
l!!N
25
9
24
8
IFC
010l"
iii02
~ ATN
~ EO!
33
38
NiiAC
WR
~ RESET
-..!
-1.
0108
7
8293
0101
6
OACK
5
GPIB TRIGGER OUTPU T.2 TRIG
I
8293
r!!..
EO!
EOI"
ATN
ATN"
r!!..
NiiAC
NOAC"
r!!-
NRFO
NRFO"
TlRl
T/R2
SRa
SRa"
REN
REN"
IFC
IFC"
r!!-
TO
IEEE·488
BUS
l!..
...!!.
E....
OPTA
..E.. GND
OPTB
.!!...
GND
MOOED
" = GPIB BUS TRANSCEIVER
Figure 9. 8291A and 8293 System Configuration
7-476
AFN·00825C
inter
8293
TO MICROPROCESSOR
~
~
,.!!
~
18
17
DO
iii01
01
0102
02
0104
04
05
18
08
19
07
21
RSO
22
RS1
23
RS2
9
Ro
10
1I2t1.
DiOs
DiOs
iii07
DiOs
TiR1
oAV
WR
EOI
RESET
6
oREo
7
AfN
4
TO
MICROPROCESSOR
0103
03
8
3
11
SRo
om
IFC
Cs
NDAC
CLOCK
NRFD
INT
TlR2
GP 18
TRIGGE R
OUTPUT
5
...!!
~
---1!
28
25
iii01
0101"
29
23
iii02
0102"
30
10
31
9
32
8
33
7
34
6
35
5
1
1
24
38
39
3
26
4
16
r£-
10
19
9
8
10
-
-I>
4
6
32
TO
MICROPROCESSOR
33
35
1
36
11
OSCILLATO R
OUTPU T
VCC~
~
.Ef!.1
15-25 PF
J
~
9
04
2
SAo
07
REN
AD
8292
Rii
WR
RESETtt
IFC
lffiIlj
COUNT
Cs
EOl2
TCI
ATNI
r!!-
0108"
~
oAV"
~
TIR1
iiAv
EOI
ATN
-2! AffiO
~ iFC[
2
r!-4
05
06
8293
TO
IEEE-488
BUS
--
~ 03
16
17
0107"
0107
~
~
37
01
oAV
0108"
24
38
02
DO
0105"
27
REN ~
TRIG
0103
lli04
DiOs
DiOs
0108
~
r-!!0103" r-!!0104" r!L
21
8
36
6
23
5
29
23
39
3
34
7
22
11
OPTA
~V cc
OPT8
f3!-v cc
MODE 3
TlR1
AfN
NoAC
NoAC
Jil'iiii
NRFo
r!!.r!L
SAo
SRo"
r!!-
REN
REN"
TIR2
iFc
8293
ATNO
IFC"
ATN"
Eoi
EOI"
~
r!L
TO
IEEE-488
BUS
~
~
EOI2
AfNj
SPI
OBFI
IBFI
SYNC
SS
x,t
IFCL
CIC
x,t
EA
CLTH
SYC
1
25
31
24
27
21
24
22
LJ
ON
IFCL
CIC
ClTH
OPTA
SYC
OPTB
E-vss
2!-vcc
MODE 2
SYSTEM
CONTROLLER
SWITCH
" = GPIB BUS TRANSCEIVER
t = SEE 8041A DATA SHEET FOR ALTERNATE
CRYSTAL CONFIGURATIONS
tt = CAN CONNECT TO SYSTEM RESET SWITCH,
SEE 8041 A DATA SHEET
Figure 10" 8291A, 8292, and 8293 System Configuration
7-477
AFN-00825C
intJ
8293
ABSOLUTE MAXIMUM RATINGS·
o·c
Ambient Temperature Under Bias'........•
to 70·C
Storage Temperature •...••....... - 65·C to + 150·C
Voltage on any Pin with
Respectto Ground ................. - 1.0V to + 7V
Power Dissipation .............•............ 1 Watt
'NOTICE:
1. Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
D.C. CHARACTERISTICS
(TA =
o·c to 70·C, vee = 5.0V :±:10%, GND = OV)
Parameter
Symbol
This is a stress rating only and functional operation of the
device at these or anJo{ other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. All devices are guaranteed to operate within the
min/mum and maximum parameter limits specified below.
Typical parameters however are not tested and are not
guaranteed. Established statistically, they indicate the
, performance level expected in a typical device at room
temperature (TA = 25°C) and Vee = 511.
VIL1
Input Low Voltage (GPIB Bus Pins)
VIL2
1
VIL3
Input Low Voltage (Option Pins)
Min.
Limits
Typ.
-0.1
Input Low Voltage (All Others)
Max.
Units
0.8
V
0.1
V
0.8
V
Test Conditions
,
VIH1
Input High Voltage (GPIB Bus Pins)
2.0
Vee
V
VIH2
Input High Voltage (Option Pins)
4.5
Vee
V
VIH3
Input High voltage (All Others)
2.0
Vee
VIH4
Receiver I nput Hysteresis
400
VOL1
Output Low Voltage (GPIB Bus Pins)
0.5
V
IOL = 48 mA
VOL2
Output Low Voltage (All Others)
0.5
V
IOL = 16 mA
VOH1
Output High Voltage (GPIB Bus Pins)
2.4
V
IOH
VOH2
Output High Voltage (All Others)
2.4
V
IOH = -800 pA
0.8
VIT
.
High to Low
Receiver Input Threshold Low to High
ILe
Input Load Curre.nt (GPIB Pins)
IlL
Input Leakage Current (All Others)
IpO
Bus Power Qown Leakage Current
Ice
Power Supply Current
V
mV
V
2.0
See Bus Load Line Diagram
10
= -5.2 mA
Vee = 5.0V :±: 5%
/LA
0.45 ,;;VIN ,;;Vee
0.45V ,;; VB US ,;; 2.7V
40
/LA
110
175
mA
lYP·
Max.
Units
NOTES:
1. VIL3
= 1.1V max on pins 21 and 22 in Mode 2 for the 8293-10.
CAPACITANCE
Symbol
Parameter
Min.
Test Conditions
CI01
1/0 Capacitance (GPIB Side)
50
80
pF
VIN =Vee
CI02
1/0 Capacitance (System Side)
35
50
pF
VIN =Vee
CITR
Input Capacitance (T/R1, T/R2)
7
10
pF
VIN ;"Vee
7-478
inter
8293
A.C. CHARACTERISTICS (TA = O"Cto 70"C, vee
Symbol
=
5.0V ±10%, GND = OV)
Parameter
Max.
Unite
tp1
Transmitter Propagation Delay (All Lines)
30
ns
tp2
Receiver Propagation Delay (EOI, ATN and Handshake Lines)
50
ns
tP3
Receiver Propagation Delay (All Other Lines)
tpHZ1
Transmitter Disable Delay (High to 3-State)
60
40
ns
40
40
ns
tpZH1
Transmitter Enable Delay (3-state to High)
tpU1
Transmitter Disable Delay (Low to 3-State)
tpZL1
Transmitter Enable Delay (3-State to Low)
tpHZ2
Receiver Disable Delay (High to 3-State)
tpZH2
Receiver Enable Delay (3-State to High)
tpU2
Receiver Disable Delay (Low to 3-State)
tpZL2
Receiver Enable Delay (3-State to Low)
tMS
Mode Switch Delay
ns
ns
40
40
40
ns
40
40
10
ns
ns
ns
ns
ILs
TYPICAL OUTPUT LOADING CIRCUITS
TO SCOPE
(OUTPUT)
TO SCOPE
(OUTPUT)
4J'.'
+2 IV
+5OY'
24011
DATA
~9
"'- lOO.' '
"'-r"" ~
.,..
Ct. INCWDES JIG AND PROlE CAPACITANCE
:"111!'OUIV.
Ct. INCWDES JIG ANO PROSE CAPACITANCE
Bus Input to Data Output (Receiver)
Data Input to Bus Output (Driver)
TOSCON
(OUTPUT)
SOY
~
. . 1'... f
"'I!'
DATA
(tfou2,1pZL2)
ltPH",Ip'",'
SKI!
~
c.. INCWDES JIG AND PROB! CAPACITANCE
, Cl INCWDES JIG AND PROBE CAPACITANCE
Send/Re~h'l!
':"
Input to Bus Output (Driver)
,Sand/!IeceIVe h1put to Data Output (Receiver)
A.C. TESTING INPUT, OUTPUT WAVEFORM
u=x >
INPUT/OUTPUT
2.0
0.8
0.45
< )C'
2.0,
TEST POINTS
.
0.8
~
A C TESnNG INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1 AND 0 45V FOR
A lOGIC 0 TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC 1
AND 08V FOR A lOGIC 0'
'1479
AfN-00825C
8293
WAVEFORMS
3.0V:,.._ _ _ _ _ _ _ _ _ _ _ _ _ _....
tRISE = "'ALL" 5 na
DUTYCYCLE = 10%
INPUT
OV----J
OUTPUT
(TRANSMITTER i!ROP. DELAY)
FIGURE 11 LOAD
OUTPUT
(RECEIVER PROP. DELAY!
FIGURE 11 LOAD
VOH
OUTPUT
(TRANSMITTER ENABLE DELAY
WITH INPUT HIGH!
FIGURE 12 LOAD
Vz -1.0V
Vz -1.13V
OUTPUT
(TRANSMITTER ENABLE DELAY
WITH INPUT LOWI
FIGURE 12 LOAD
VOL
VOH
OUTPUT
(RECEIVER ENABLE DELAY
WITH INPUT HIGH!
FIGURE 13 LOAD
OV
5V
OUTPUT
(RECEIVER ENABLE DELAY
WITH INPUT LOW)
FIGURE 13 LOAD
1.5V
VOL
'OELAYS ARE REFERENCED AGAINST PERCENTAGE OF FINAL OUTPUT WHEREVER 3-STATE OUTPUTS ARE INVOLVED BECAUSE THE RISE AND FALL TIMES OEPEND
ON THE EXTERNAL PULL·UPAND PULL·DOWN LOADS,
BUS LOAD LINE
TYPICAL RECEIVER HYSTERESIS
CHARACTERISTICS
8.0
4.0
2.0
'l...
...a:z
-2.0
a: -4.0
::>
<.> -8.0
II)
::>
III
-8.0
j
-10
-12
-14
0.&
Vau.. BUS VOLTAGE (VOLTS!
1.0
1.5
2.0
V.INPUT VOLTAGE (VOLTS!
7-480
AFN.Q0825C
intJ
8294A
DATA·ENCRYPTION UNIT
• Certified by National Bureau of
Standards
• 7·Bit User Output Port
• Single 5V ± 10% Power Supply
• 400 Byte/Sec Data Conversion Rate
• 64·Bit Data Encryption Using 56·Bit
Key
• Fully Compatible with IAPX-86,88,
MCS-85T11 , MCS-80TII , MCS-51 TM, and
MCS-48™ Processors
• Implements Federal Information
Processing Data Encryption Standard
• DMA Interface
• 3 Interrupt Outputs to Aid in Loading
and Unloading Data
• Encrypt and Decrypt Modes Available
The Intel15 8294A Data Encryption Unit (OEU) is a micrpprocessor peripheral device designed to encrypt and decrypt 64·bit
blocks of data using the algorithm specified in the Federal Information Processing Data Encryption Standard. The OEU
operates on 64·bit text words using a 56·bit user·specified key to produce 64-bit cipher words. The operation is reversible:
If the cipher word is operated upon, the original text word is produced. The algorithm itself is permanently contained in the
8294A; however, the 56·bit key is user·defined and may be changed at any time.
The 56-bit key and 64·bit message data are transferred to and from the 8294A in 8·bit bytes by way.of the system data bus. A
OMA interface and three interrupt outputs are available to minimize software overhead associated with data transfer. Also,
~y using the OMA interface two or more DEUs may be operated illl parallel to achieve effective system conversion rates
which are virtually any multiple of 400 bytes/second. The 8294A also has a 7·bit TTL compatible output port for
user·specified functions.
Because the 8294A implements the NBS encryption algorithm it can be used in a variety of Electronic Funds Transfer
applications as well as other electronic banking and data handling applications where data must be encrypted.
NC
Xl
DATA
aUS
RESET
Vee
CS
GNO
RJj
SRQ
DAV
ceMP
POP6
REsET
SYNC
x,
x,
+5V-POWER-_
GND-_
.
WA
SYNC
DO
01
02
03
04
05
06
07
GNO
INTERNAL
8US
Figure 1. Block Diagram
4
VCC
NC
OACK
ORO
SRO
OAV
NC
P6
P5
P4
P3
P2
Pl
PO
VOO
Vec
CCMP
NC
NC
NC
Figure 2. Pin Configuration
Intel Corporation A..umea No Reaponaibilty for the UM of Any Circuitry Other Than Circuitry Embodied In an Intel Product No Other CirCUit Patent llcenae. are Implied.
OINTEL CORPORATION. 1983
7-481
SEPT 1983
ORDER NUMBER: 210415-003
inter
8294A
Table 1. Pin Description.
Pin
Symbol No. Type
NC
1
Xl
X2
2
3
RESET
4
Vee
5
CS
6
GNO
7
RO
8
I
Read: An actIve low read strobe at this
pin enables the CPU to read data and
status from the internal OEU registers.
AD
9
I
Address: Address input used by the
CPU to select OEU registers during read
and write operations.
NC
39
I
Crystal: Inputs for crystal, L-C or external timing Signal to determine internal
oscillator frequency,
OACK
38
I
I
Reaet: A low signal to this pin resets the
8294A,
DMA Acknowledge: Input sIgnal from
the 8257 OMA Controller acknowledging that the requested OMA cycle has
been granted.
ORO
37
0
DMA Request: Output sIgnal to the
8257 OMA Controller requesting a OMA
cycle.
SRO
36
0
Service Request: Interrupt to the CPU
indicating that the 8294A is awaiting
data or commands at the input buffer.
SRO=l implies IBF=O.
OAV
35
0
Output Available: Interrupt to the CPU
indicating that the 8294A has data or
status available in its output buffer.
OAV=l implies OBF=l.
0
Output POr:!: User output port Irnes
Output lines available to the user via a
CPU command which can assert selected port lines. These lines have (10thing to do with the encryption functIon.
At power-on, each line is in a 1 state.
I
Chip Select: A low signal to this pin
enables reading and writing to the 8294A.
Ground: This pin must be tied to
ground.
10
I
SYNC
11
0
Sync: High frequency (Clock ~ 15) output. Can be used as a strobe for'external
circuitry.
Do
0,
D,
1/0
Data Bus: Three-state, bi-dlrectional
data bus lines used to transfer data between the CPU and the 8294A.
07
12
13
14
15
16
17
18
19
GNO
20
Vce
40
No Connection.
Power: Tied high.
WR
D.
Name,and Function
No Connection.
Write: An active low write strobe at this
pin enables the CPU to send data and
commands to the OEU.
03
D.
0,
Pin
Symbol No. Type
Name and Function
Ground: This pin must be tied to
ground.
Power: +5 volt power input: +5V ±
10%.
NC
34
P6
P5
P4
P3
P2
P1
PO
33'
32
31
30
29
28
27
Voo
26
Vee
25
CCMP
24
No Connection.
Power: +5V power input. (+5V ±10%)
Low power standby pin
Power: Tied high.
0
Conversion Complete: Interrupt to the
CPU indIcating that the encryptlonl
decryption of an 8-byte block is complete,
NC
23
No Connection.
NC
22
No Connection.
NC
21
No Connection.
7-482
AFN-0023OD
8294A
FUNCTIONAL DESCRIPTION
IBF
Input Buffer Full; A write to the Data Input Buffer
or to the Command Input Buffer sets IBF = 1 The
DEU resets this flag when it has accepted the
input byte. Nothing should be wntten when
IBF= 1.
DEC
Decrypt; indicates whether the DEU IS in an en·
crypt or a decrypt mode. DEC = 1 implies the
decrypt mode. DEC = 0 implies the encrypt
mode.
OPERATION
The data conversion sequence is as follows:
1. A Set Mode command is given, enabling the desired
interrupt outputs.
2. An Enter New Key command is issued, followed by 8
data inputs which are retained by the DEU for encryption/decryption. Each byte must have odd parity.
3. An Encrypt Data or Decrypt Data command sets the
DEU in the desired mode.
After this, data conversions are made by writing 8 data
bytes and then reading back 8 converted data bytes. Any
of the above commands may be issued between data
conversions to change the basic operation of the DEU;
e.g., a Decrypt Data command could be issued to
change the DEU from enc;rypt mode to decrypt mode
without changing either the key or the interrupt outputs
enabled.
After 8294A has accepted a 'Decrypt Data' or
'Encrypt Data' command, 11 cycles are required to
update the DEC bit.
Completion Flag; This flag may be used to indio
cate any or all of three events in the data transfer
protocol.
CF
1. It may be used in lieu of a counter in the
processor routine to flag the end of an 8·
byte transfer.
2. It must be used to indicate the validity of
the KPE flag.
3. It may be used in lieu of the CCMP interrupt
to indicate the completion of a DMA operation.
INTERNAL DEU REGISTERS
Four internal registers are addressable by the master
processor: 2 for input, and 2 for output. The following
table describes how these registers are accessed.
RD
WR
CS
Ao
1
0
1
0
1
X
0
0
0
0
0
0
o
1
o
X
1
X
Key Parity Error.; After a new key has been
entered, the DEU uses this flag in conjunction
with the CF flag to indicate correct or incorrect
parity.
KPE
Register
Data input buffer
Data output buffer
Command input buffer
Status output buffer
Don't care
COMMAND SUMMARY
1-
Enter New Key
~~~~~~~~
The functions of each of these registers are described
below.
Data Input Buffer - Data written to this register is inter·
preted in one of three ways, depending on the preceding
command sequence.
.
1. Part of a key.
2. Data to be encrypted or decrypted.
3. A DMA block count.
OP CODE
10 11 1010101010101
MSB
2-
Encrypt Data
OP CODE'
~I0"T"10~1~1"T"1~1l~o"T"l-o1~0"T"1~o1
MSB
Data Output Butler - Data fead from this register is the
output of the encryption/decryption operation.
LSB
This command puts the 8294A inta th~ encrypt mode.
3-
Command Input Buffer - Commands to the DEU are
written into this register. (See command summary
below.)
.
LSB
This command is followed by 8 data byte inputs which
are retained in the key buffer (RAM) to be used in
encrypting and decrypting data. These data bytes must
have odd parity represented by the LSB.
Decrypt Data
OP CODE
~,0""10-'1-1'-10-',-0' "0'' '10-',-'01
MSB
LSB
This command puts the 8294A into the decrypt mode.
Status Output Buffer - DEU status is available in this
register at all times. It is used by the processor for poll·
driven command and data transfer operations.
4-
OP CODE
FUNCTION:
10 1010101AlB 1C 1OJ
MSB
STATUS BIT:
OBF
.
Set Mode
x
X
KPE
CF
DEC
IBF
LSB
where:
Output Buffer Full; OBF = 1 indicates that output
from the encryption/decryption function is
available in the Data Output Buffer. It is reset
when the data is read.
A is the OAV (Output Available) interrupt enable
B is the SRQ (Service Request) interrupt enable
C is the DMA (Direct Memory Access) transfer enable
D is the CCMP (Conversion Complete) interrupt enable
7-483
AFN.--_I~
~_=-i3
XTAL2
FOR THE 8294A XTAL2 MUST BE HIGH
35-85% OF THE PERIOD
RilE AND FALL TIMES MUST
NOT EXCEED 10 nl
RESISTOR TO Vee IS NEEDED
TO ENSUAE VIH = 3.0v IF Tn
CIRCUITRY IS USED
Figure 18. Recommended Connection for Extemal Clock Signal
ABSOLUTE MAXIMUM RATINGS·
'NOTlCE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this speoification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Ambient Temperature Under Bias ........ O'C to 70'e
Storage Temperature ............ - 65'e to
Voltage on Any Pin With
Respect to' Ground. . . . . . . . . . . . . . ..
+ 150'e
-0.5V to + 7V
Power DIssipation •........................ '. . 1.5 Watt
D.C. AND OPERATING CHARACTERISTICS
Min.
(TA = O'C to 70°C, Vee = +5V
Umlts
Typ.
:!:
10%, Vss =
oY)
Max.
Unit
VIL
Input Low Voltage (All
Except X1• X2. RESET)
-0.5
0.8
V
VIL1
Input Low Voltage (X 1• X2.
RESET
-0.5
0.6
V
VIH
Input High Voltage (All
Except X1• X2. RESET)
2.2
Vee
V·
VIH1
Input High Voltage (X 1• X2•
RESET)
3.0
Vee
V
V IH2
Input High Voltage (X2)
2.2
Vee
V
VOL
VOLl
Output Low Voltage (D(),,07)
0.45
V
IOL = 2.0mA
Output Low Voltage (All
Other Outputs)
0.45
V
IOL = 1.6 mA
Symbol
Parameter
1ftt Conditions
VOH
Output High Voltage (0(),,07)
2.4
V
IOH = -400 p.A
VOH1
Output High voltage (All
Other Outputs)
2.4
V
IOH= -50p.A
IlL
Input Leakage Current
(RD. WR. es. Ao)
± 10
p.A
Vss:;;;; VIN:;;;; Vee
IOFL
Output Leakage Current
(00-0 7• High Z State)
± 10
p.A
Vss + 0.45:;;;; VOUT:;;;; Vee
100
100
+ Icc
Voo Supply Current
5
20
mA
Total Supply Current
60
135
mA
III
Low Input Load Current
(Pins 24. 27-38)
0.3
mA
V IL = 0.8V
ILI1
Low Input Load Current
(RESET)
0.2
mA'
V IL = 0.8V
IIH
Input High Leakage Current
(Pins 24. 27-38)
100
p.A
VIN = Vee
C IN
Input Capacitance
10
pF
CliO
I/O Capacitance
20
pF
7-489
AFN.00:!30D
inter
8284A
A.C. ·CHARACTERISTICS
(TA = O'C to 70'C, Vce = Voo ,= +5V ±1 0°/9, Vss = OV)
DBB READ
Symbol
tAR
tRA
tRR
tAD
tOF
1m • to
1m t to
tCY
Cycle Time
tRO
Min. '
Parameter
CS, Ao Setup to R15 •
CS, Ao Hold After 1m t
1m Pulse Width
CS, Ao to Data Out Delay
Max.
Unit
0
ns
0
ns
Test Conditions
ns
160
Data Out Delay
Data Float Delay
130
ns
130
ns
85
ns
1.25
15
,..s
Min.
Max.
Unit
Ct. Ct. =
100 pF
100 pF
1-12 MHz Crystal
DBB WRITE
Symbol
Parameter
tAW
CS, Ao Setup to iiiiR •
tWA
tww
CS, Ao Hold After WR t
WR Pulse Width
tow
Data Setup to WR t
two
Data Hold to WR
0
ns
0
ns
160
130
ns
0
ns
t
Test Conditions
ns
DMA AND INTERRUPT TIMING
Symbol
Parameter
Min.
tAcc
~ Setup to Control
0
0
Unit
Max.
Test Conditions
ns
tCAC
l5AeR Hold After Control
tACO
DACK to Data Valid
130
ns
tCRQ
Control L.E. to DRO T.E.
100
ns
tCI
Control T.E. to Interrupt T.E.
400
ns
ns
CL =100 pF
CLOCK
8742
8042
9.20
Min.
1.25
613
83.3
Max.
Max.
Units
9.20
~S[11
613
ns
tCY
Parameter
Cycle Time
Min.
1.25
tCYC
Clock Period
83.3
tPWH
Clock High Time
tPWL
Clock Low Time
tR
Clock Rise Time
10
10
ns
tF
Clock Fall Time
10
10
ns
Symbol
38
33
33
ns
ns
38
NOTES:
1 ICY = 1S/f(XTAL)
A.C. TESTING INPUT, OUTPUT WAVEFORM
7-490
inter
8294A
WAVEFORMS
READ OPERATION-OUTPUT BUFFER AEGISTER
CSDR
Ao
JJ
- 1 .0
K
-1 .
(SYSTEM'S
ADDRESS BUS)
-IIIA_
100
Y
'\
(R EAD CONTROL)
. .-----------
~~~~P~------------
'" ::..
7
7
825~-5
COUNTERI
TIMER
.., ,.
"1 ".
8261
USART
-ntroller and vectored interrupts
greatly redu~e the overall part count consider~bly.
Decision 2 is fairly obvious; if a circuit can be
designed so that loading on the data and address
lines is kept to a minimum, both the data and address
buffers can be eliminated. This easily saves three to
eight packages and reduces the power consumption
of the design. Both decisions 3 and 4 require a basic
understanding of current CRT design concepts.
In any CR.T design, extreme time conflicts are created
because all essential elements require access to the
bus. The CPU needs to access the memory to control
the system and to handle the incoming characters,
but, at the same time. the CRT controller needs to
access the memory to keep the raster scan display
refreshed. To resolve this conflict two common
techniques are employed, page buffering and line
buffering.
In the page buffering approach the entii-e screen
memory is isolated from the rest of the system. This
isolation is usually accomplished with three-state
buffers or two line to one line multiplexers. Of
course, whenever a character needs to be manipulated the "CPU must gain access to the buffered
memory and, again, possible contention between the
CPU and the CRT controller results. This contention
is usually -resolved in one of two ways, (I) the CPU is
always given priority, or; (2) the CPU is allowed to
access the buffered memory only during horizontal
and vertical retrace times.
Approach I is the easiest to implement from a hardware point of view, but if the CPU always has
priority the display may temporarily blink or
"flicker" while the CPU accesses the display memory.
This, of course, occurs because when the CPU
accesses the display memory the CRT controller is
not able to retrieve a character, so the display must
be blanked 'during this time. Aesethically, this
"flickering" is not desirable, so..approach 2 is often
used.
The second approach eliminates the display flickering encountered in the previously mentioned technique, but additional hardware is required. Usually
the vertical and horizontal blank signals are gated
with the buffered memory select lines and this line is
used to control the CPU's ready line. So, if the CPU
wants to use·the buffered memory, its ready line is
asserted until horizontal or vertical retrace times.
This, of course, will impact the CPU's' overall
through put. .
Both page buffered approaches require a significant
amoun,t of additional hardware and for the most
part are not well suited for a minimum parts count
type of terminal. This guides us to the line buffered
approach. This approach eliminates the separate
buffered memory for the display, but, at the same
time, introduces '8 few ·new .problems that must be
solved.
AfN.01304A
·APPLICATIONS
VIDEO OUT
MOEIlUl'l'l!RINQ
TECHNIQUE
1--_'11010 OUT
UN! IUfFlRlNO
TECHNIQUE
Figure 4·1. Line Buffering Technique
a.OCK CYClES
18
10
18
10
18
4
-16
6
7
4
480
4
4
18
18
4
6
18
4
4
4
7116
4
4
7110
I.
1~
7
4
18
18
18
4
18
SEO
sa~
STAlElalT
1
2
3
4
5
6
7
8
MIl
MIl
I'USII
LX!
H
0
(lfI!>
SP
9
III
11
nvl
LfLI)
fIAI)
16
17
18
1!1
29
XOO
21
SP"rlL
LXI
lICIIG
lIlY
OIP
22
2l
II(J'I
25
26
27
p(Ip
15
)Hz
CItP
JIIZ
LXI
SHLO
IIVI
5/"
-
SP
.·IJIST
~,o
H
H roll L
,,'LiT sr.. .'):
. PQUHER IN H fIfl') L
,HJT SlAI.f. II' t) H!lI E
.GET FOWTER
,PUT C!.Yi£N) LIIc uno SP
,SET rlf;.;J~ F~ ~ll'l
H,~_
SPHL
12
13
14
24
P;U
EI
RrT
,SIW( " fIf(l
"A::!(
,1'\lT
IN H "lD L
.rESltJI..: Slf£j,
,M EOTlOM DIm.flY W H,P..!> L
, SJ.:i1P R:G:ST(P~
,f1JT HIGH !f:C
WIlli R (; 144 ItIZ CRVSTRL TOTAL T11£ TO FILL
m. UfER ON ,8275 '* fSO •. 325 • 21125 ftlCRQSEW[)S
Figure 4-2. Routine To Load 8275's Row Buffe,.
8-10
AFJ+01304A
APPLICATIONS
transfer bit and executing a string of POP instruc~ions. The string of POP instructions is used to
rapidly move the data from the memory into the
8275. Figure 4.2 shows the basic software structure.
In this design the 8085's SOD line was used as the
special transfer bit. In order to perform the transfer
properly this special bit must do two things: (1) turn
processor reads into ~ plus WR. for the 8275
and (2) mask processor fetch cycles from the 8275, so
that a fetch cycle does not write into the 8275.
Conventional logic could have been used to implement this special function, but in this design a small
bipolar programmable read only memory was used.
Figure 4.3 shows a basic version of the hardware..
lid
r.
D-
TRANSFER
BIT
Ci!
speed of the 8080 used in AP-32, we find that at 3
MHz we can transfer one byte every 1.67 microseconds using the 8085 and POP technique vs. 2
microseconds per byte for the 2 MHz 8080 using
DMA.
5. CIRCUIT DESCRIPTION
5.1 SCOPE OF THE PROJECT
A fully functional, microprocessor-based CRT
terminal was designed and constructed using the
8275 CRT controller and the 8085 as the controlling
element. The terminal had many of the functions
found in existing commerciallow-cost terminals and
more sophisticated features could easily be added
with a modest amount of additional software. In
order to minimize component count LSI devices
were used whenever possible and software was used
'
to replace hardware.
BIPOLAR
PROM
S.2 SYSTEM TARGET SPECIFICAnONS
The design specifications for the CRT terminal were
as follows:
Display Format
• 80 characters per display row
• 25 display rows
Character Format
• 5 X 7 dot matrix character contained within a
7 X 10 matrix
• First and seventh columns blanked
• Ninth line cursor position
• Blinking underline cursor
Special Characters Recognized
• Control characters
• Line feed
• Carriage Return
• Backspace
• Form feed
Escape Sequences Recognized
• ESC, A, Cursor up
• ESC, B, Cursor down
• ESC, C, Cursor right
• ESC, D, Cursor left
• ESC, E, Clear screen
• ESC, H, Home cursor
•. ESC, J, Erase to the end of th~ screen
• ESC, K, Erase the current line
Characters Displayed
• 96 ASCII alphanumeric characters
• Special control characters
lid
Ao
8271
A,
827Swr
1.2
8275Cs
1.3
1.4
)
Figure 4-3. Simplified Version of Hardware Decoder
At first, it may seem strange that we are supplying a
I5AO{ when no DMA controller exist in the
system. But the reader should be aware that all Intel
nXt:¥{ral devices that have DMA lines actually use
as a chip select for the data. So, when you
want to write a command or read status you assert
<::S and WR or RU, but when you want to read or
write data you assert DACK and RD or WR. The
peripheral device doesn't "know~ if a D MA controller is in the circuit or not. In passing, it ,should be
mentioned that DACK and CS should not be
asserted on the same device at the same time, since
this combination yields an undefined result.
This POP 'technique actually compares quite
,favorably in terms of time to the DMA technique.
One POP instruction transfers two bytes of data to
the 8275 and takes 10 CPU clock cycles to execute,
for a net transfer rate of one byte every five clock
cycles. The DMA controller takes four clock cycles
to transfer one byte but, some time is, lost in
synchronization. So the difference between the two
techniques is one clock cycle per byte maximum. If
we compare the overall speed of the 8085 to the
8-11
~1304A
APPLICATIONS
CHARACTER
GENERATOR RO,!,
SYSTEM BUS
CRT TERMINAL
SERIAL INPUT LINE
Figure 5-1. CRT Terminal Block Diagram
/
Characters Transmitted
• 96 ASCII alphanumeric characters
• ASCII control characters
Program Memory
• 2K bytes of 2716 EPROM
Display / Buffer/ Stack Memory
• 2K bytes 2114 static memory (4 packages)
Data Rate
.; 9600 BAUD using 3MHz 8085
Worst case bus loading:
CRT Monitor
• Ball Bros TV-12, 12MHz B.W.
Keyboard
• Any standard un-encoded ASCII keyboard
Screen Refresh Rate
Only As ; A15 are important since Ao - A7 are
latched by the 8212 .
Data Bus:
8275
8255A-5
8253-5
8253-5
8251A
2x 2114
2716
8212
20pf
20pf
20pf
20pf
20pf
10pf
12pf
12pf
114pf max
Address Bus: 4x 2114
2716
20pf
6pf
26pf max
This loading assures that all components will be
compatible with a 3MHz 8085 and that no wait
states will be required
• 60 Hz
5.3 HARDWARE DISCRIPTION
.A block diagram of the CRT terminal is shown in
Figure 5.1. Th.e diagram shows only the essential
system features. A detailed schematic of the CRT is
contained in the Appendix. The terminal was
constructed on a simple 6" by 6" wire wrap board.
Because of the minimum bus loading no buffering of
any kind was needed (see Figure 5.2).
Figure 5-2. Bus Loading
mitted, decodes the incoming characters and determines where the character is to be placed on the
screen. Clearly, the processor is quite busy.
A standard list of LSI peripheral devices surround
the 8085. The 825lA is used as the serial communication link, the 8255A-5 is used to scan the keyboard
and read the system variables through a' set of
The "heart" of the CRT terminal is the 8085
microprocessor. The 8085 initializes all devices in
the system, loads the CRT controller, scans the
keyboard, assembles the characters to' be trans&12
AFN'()l304A.
APPLICATIONS
switches, and the 8253 is used as a baud rate
generator and as a "horizontal pulse extender" for
the 8275.
process continues until the last line of the row is
transferred to the dot timing logic.
The dot timing logic latches the output of the
character generator RoM into a parallel in, serial
out synchronous shift register. This shift register is
clocked at the dot clock rate (11.34 MHz) and its
output constitutes the video input to the CRT.
The 8275 is used as the CRT controller in the system,
and a 2716 is used as the character generator. To
handle the high speed portion of the terminal the
8275 is surrounded by a small handful of TTL. The
program memory is contajned in.one 2716 EPROM
and the data and screen memory use four 2114-type
RAMs.
CHARCl.OCK
r~
All devices in this system are memory mapped. A
bipolar PROM is used to decode all ofthe addresses
for the RAM, ROM, 8275, and 8253. As mentioned
earlier, the bipolar prom also tnrns READs into
i'5ACK's and WIt's for the 8275. The 8255 and 8253
are decoded by a simple address line chip select
method. The total package count for the system is
20, not including the serial line drivers. If this same
terminal were designed using the MCS-85 family of
integrated circuits, additional part savings could
have been realized. The four 2114's could have been
replaced by two 8185's and the 8255 and the 2716
program PROM could have been replaced by one
8755. Additionally, since both the 8185 and the
2716 have address latches no 8212 would be needed,
so the total parts count could be reduced by three
or four packages.
LCO-lC2
----AO -A2
--~--
t:::t~=::j
-~
VIDeo
LtNE COUNt
I
2708
CHARACTER
I
8275
HORIZ DR
GENERATOR
ROM
I
CCo-CC51=~~=::j
A3 -A8
VERT DR
___________ J
I
I
Figure 5-3 Character Generator/Dot Timing Logic
Block Diagram
r'
Table 5-1
PARAMETER
VertiGal Blanking Time
RANGE
900 J.Lsec nominal
(VRTC)
Vertical Drive Pulsewidth
5.4 SYSTEM OPERATION
Horizontal Blanking Time
(HRTC)
The 8085 CPU initializes each peripheral to the
appropiate mode of operation following system
reset. After initialization, the 8085 continually polls
the 8251A to see if a character has been sent to the
terminal. When a character has been received, the
8085 decodes the character and takes appropriate
action. While the 8085 is executing the above "foreground" programs, it is being interrupted once every
617 microseconds by the 8~75. This "background"
program is used to load the row buffers on the 8275.
The 8085 is also interrupted once every frame time,
or 16.67 ms, to read the keyboard and the status of
the 8275.
As discussed earlier, a special POP technique was
used to rapidly move the contents of the display
RAM into the 8275's row buffers. The characters are
then synchronously transferred t6 the character code
outputs CCO-CC6, connected to the character
generator address lines A3-A9 (Figure 5.3). Line
count outputs LCO-LC2 from the 8275 are applied
tp the character generator address Ilnes.,AO-A2. The
8275 displays character rows one'line at a time. The
line count outputs are used to determine which line
of the character selected by A3-A8 will be displayed.
Following the transfer of the first line to the dot
timing logic, the line count is incremented and the .
second line of the character row is selected. This
Horizontal Drive Pulsewidth
Horizontal Repetition Rate
300 J.Lsec ~ PW ~ 1.4 ms
11 J.Lsec nO\11inal
25 J.Lsec ~ PW ~ 30 J.Lsec
15,750 ±500 pps
5.5 SYSTEM TIMING
Before any specific timing can be calculated it is
necessary to determine what constraints the chosen
CRT places on the overall timing. The requirements
for the Ball Bros. TV-12 monitor are shown in Table
5.1. The data from Table 5.1, the 8275 specifications,
and the system target specifications are all that is
needed to calculate the system's timing.
~7DOTS_l
LINE1_ •••••••••••••••••••••
eooooo •• ooooo • • ooooo.
.00000 •• 00000 •• 00000.
eooooo • • ooooo • • ooooo.
___
.00000 •• 00000 •• 00000 •
• 00000 • • 00000 • • 00000.
.00000 •• 00000 •• 00000.
UNDERLINE
• 0 a 0 0 0 •• 0 0 0 0 0 •• 0 0 0 " 0 •
POSITION _ _ • 0 0 0 0 0 • • 0 0 0 0 0 • • 0 0 C O O .
LINE 10 _ " • • • • • • • • • • • • • • • • • • • • •
--.-.. --.-.. --.-..
CHARACTER 1 CHARACTER 2 CHARACTER 3
Figure 5-4. Row Format
8-13
AFN-01304A
APPLICATIONS
First, let's select and "match'~ a few numbers. From
our target specificatiOns, we see that each character
is displayed on a 7 X I 0 field, and is formed by a 5 X
7 dot matrix (Figure 5.4). The 8275 allows the
vertical retrace time to be only an integer multiple of
CHARACTER
the horizontal character line: This means that the
total number of horizontal lines in a frame equals 10
times the number of character lines plus the vertical
retrace time, which is programmed to be either 1, 2,
3, or 4 character lines. Twenty-five display lines
1'!1i9:9n;:-:----- 617.0 ~-----I
~
COUNTER
STATE
DOT
CLOCK
44.9n.
OA
CH::~~
CLOCK
I
I
r-----ill
1
1
74S163
OCl:
I·
OD
CHARACTER
CLOCKeJ7~
....;----,-,--J-+--I
11I
I ----:1
1
L-i-.
----+'
rl :
. II
15:r.d1lfAX
1TilL.-_____
.;. ;Ii"__-'
;-
L--_~
I
I
........I
I
---;....:!I'
L..-I
827'
CHARACTER
SECOND CHARACTER
FIRST CHARACTER
OUTPUT
THIRD CHARACTER
(CCO·CC6)
SHI"
REGISTER
OUTPUT
(74166)
11.34 MHz
~
FIRST CHARACTER VIDEO OUT
I
.1
'
T~~
7404
3300
.001
SECOND CHARACTER VIOEO OUT
+V
7404
:>o-+-~_--i
3300
LCO-LC2
CCO-CC6
DOT
CLOCK
VIDEO OUT ...---.....,
VSP
(8275)
LTEN
(6275)
HRTC
(6275)
VRTC
(8275)
CAT
HORIZONTAL
DRIVE
MONITOR
VERTICAL
DRIVE
Figure 5-5. Dot Timing Logic
&14
AFNoOt304A
APPLICATIONS
be allowed for horizontal retrace. Unfortunately,
this number depends almost entirely on the monitor
used. Usually, this number lies somewhere between
15 and 30 percent of the total horizontal line time,
which in this case is 1/16,200 Hz or 61.73
microseconds. Since in most designs a fixed number
of characters can be displayed on a horizontal line, it
is often useful to express retrace as a given number
of character times. In this design, 80 characters can
be displayed on a horizontal line and it was
empirically found that allowing 20 horizontal
character times for retrace gave the best results. So,
in reality, there are 100 character times in every
given horizontal line, 80 are used to display
characters and 20 are used to allow for retrace. It
should be noted that if too many character times are
used for retrace, less time will be left to display the
characters and the display will not "fill out" the
scteen. Conversely, if not enough character times
are allowed for retrace, the display may "run off' the
screen.
One hundred character times per complete horizontal
line means that each character requires
61.73 microseconds /100 character times = 617.3
nanoseconds.
If we mUltiply the 20, horizontal retrace times by the
require 250 horizontal lines. So, if we wish to have
a horizontal frequency in the neighborhood of
15,750 Hz we must choose either one or two
character lines for vertical retrace. To allow for a
little more margin at the top and bottom of the
screen, two character lines were chosen for vertical
retrace. This choice yields a net 250 + 20 = 270
horizontal lines per frame. So, assuming a 60 Hz
frame:
60 Hz * 270 = 16,200 Hz (horizontal frequency)
This value falls within our target specification of
15,750 Hz with a 500 Hz variation and also assures
timing compatibility with the Ball monitor since, 20
horizontal sync times yield a vertical retract time of:
61.7 microseconds X 20 horizontal sync times =
1.2345 milliseconds
This number meets the nominal VRTC and vertical
drive pulse width time for the Ball monitor. A
horizontal frequency of 16,200 Hz implies a
1/ 16,200 = 61. 73 microsecond period.
It is now· known that the terminal is using 250
horizontal lines to display data and 20 horizontal
lines to allow for vertical retrace and that the
horizontal frequency is 16,200 Hz. The next thing
that needs to be determined is how much time must
CHARACTER
CLOCK
HRTC
1...... 1 " 1 ""," 1 "'," 1······1 ":';'
~:
I
(8275)
CHAR CODE
(8275)
LINE COUNT
(82751
SHIFT--t-+-t-t--t-+-t-+-+---t-t-+-±-+-1-'--j-\
REGISTER
LOAOING
VIDEO
OUTPUT
Figure 5-6. CRT System TIming
8-15
AFN-{)I304A
APPLICATIONS
617.3 nanoseconds needed for each character, we frod
617.3 nanoseconds * 20 retrace times = 12.345
microseconds
This value falls short of the 25 to 30 microseconds
required by the horizontal drive of the Ball monitor.
To correct for this, an 8253 was programmed in the
one.-shot mode and was used to extend the horizontal
.
drive pulsewidth.
Now that the 617.3 nanosecond character clock
period is known, the dot clock is easy to calculate.
Since each character is formed by placing 7 dots
.
along the horizontal.
DOT CLOCK PERIOD = 617.3 ns
(CijARACTER CLK PERIOD)/ 7 DOTS
DOT CLOCK PERIOD:;: 88.183 nanoseconds
DOT CLOCK FREQUENCY = I/PERIOD =
1l.34 MHz
Figures 5.5 and 5.6 illustrate the basic dot timing
and the CRT system timing, respectively.
6. SYSTEM SOFTWARE
6.1 SOFTWARE OVERVIEW
As mentioned earlier the software is structured on a
"foreground-background" basis. Two interruptdriven routines, FRAME and POPDAT (Fig. 6.1)
request service every 16.67 milliseconds and 617
microseconds respectively, frame is used to check
the baud rate switches, update the system pointers
and decode and assemble the keyboard characters.
POPDA T is used to move data from the. memory
into the 8275's row buffer rapidly.
The foreground routine first examines the line-local
switch to see whether to accept data from the
USAR T or the keyboard. If the terminal is in the
local mode, action will be taken on any data that is
entered through the keyboard and the USART will
be ignored on both output and input. If the terminal
is in the line mode data entered through the
keyboard will be transmitted by the USAR T and
action will be taken on any data read out of the
USART.·
.
EXIT
When data has been entered in the terminal the
software first determines if the character received
was an ~scape, line feed, form feed, carriage return,
back space, or simply a printaole character. If an
escape was received the terminal assumes the next
received character will be a recognizable escape
sequence character. If it isn't no operation is
performed.
After the character is decoded, the processor jumps
to the routine to perform the required task. Figure
6.2 is a flow chart of the basic software operations;
the program is listed in Appendix 6.8.
EXIT
. Figure 6-1. Frame and Popdat Interrupt RoutInes
8-16
AFN-Ol304A
APPLICATIONS
ROW 1
ROW2
ROW 3
ROW 4
ROW 5
ROW 6
ROW 7
ROW 8
ROW 9
ROW 10
ROW11
ROW 12
ROW 13
ROW 14
ROW 15
ROW 16
ROW 17
ROW 18
ROW 19
ROW 20
ROW 21
ROW 22
ROW 23
ROW 24
ROW 25
LINE
Figure 6-2. Basic Terminal Software
6.2 SY;STEM MEMORY ORGANIZATION
The display memory organization is shown in
Figure 6.3. The display begins at location 0800H in
memory and ends at location OFCFH. The 48 bytes
of RAM from location OFDOH to OFFFH are
used as system stack and temporary system storage.
2K bytes of PROM located at O(JOOH through
07FFH contain the systems program.
1st Column
2nd Column
.••••••••• 80th Column
oBOOH
0850H
08AOH
08FOH
0940H
0990H
09EOH
OA30H
OA80H
OADOH
OB20H
OB70H
OBCOH
OC10H
OC60H
OCBOH
ODOOH
OD50H
ODAOH
ODFOH
OE40H
OE90H
OEEOH
OF30H
OF80H
0801 H ............. 084FH
0851H ............. 089FH
08A 1 H ............08EFH
08F1H ... : ......... 093FH
0941H ............. 098FH '
0991H ............. 090FH
09E1 H ............ OA2FH
OA31 H ........... OA7FH
OA81H ., ......... OACFH
OAD1H .' ......... OB1FH
OB21 H ;, ......... OB6FH
OB71 H ., ......... OBBFH
OBC1 H ........... OCOFH
OC11 H ,........... OC5FH
OC61 H ........... OCAFH
OCB1 H ........... OCFFH
OD01 H ........... OD4FH
OD51 H ........... OD9FH
ODA1H ., ......... ODEFH
ODF1 H ............OE3FH
OE41 H .... : ........OE8FH
OE91 H . , . ~ ........ OEDFH
OEE1 H ............ OF2FH
OF31 H ............. OF7FH '
OF81 H ............ OFCFH
Figure 6-3. Screen Display After Initialization
Subroutines CALCU (Calculate) and ADX (ADd X
axis) use these three variables to calculate al;
absolute memory addr.ess. The subroutine CALCU
, is used whenever a location in the screen memory
m\lst be altered.
6.4 SOFTWARE TIMING
One important question that must be asked about
the terminal software is, "How fast does it run". This
is important because if the terminal is running at
9600 baud, it must be able to handle each received
character in 1.04 milliseconds. Figure 6.5 is 'a
flowchart of the subroutine execution times. It
should be pointed out that all of the times listed are
"worst case" execution times. 'Fhis means that a:Il
routines assume they must do the maximum amount
of data manipulation. For instance, the PUT-routine
assumes that, the character is being placed in the last
column and that a line feed must follow the placing
of the character on the s c r e e n . ,
6.3 MEMORY POINTERS AND SCROLLING
To calculate the location of a character on the
screen, three variables must be defined. Two of these
variables are the X and Y position of the cursor
(CURSX, CURSY). In addition, the memory
address defining the top line of tne display must be
known, since scrolling on the 8275 is accomplished
simply by changing the pointer that Ipads the 8275's
row buffers from memory. ~o, if it is desired to
scroll the display up or down all that must be
changeri js one 16-bit memory poil\ter. T:his pointer
is entered into the system by the variable TOP AD
(TOP Address) and always defines the top line ofthe
display. Figure 6.4 details screen operation dUring
scrolling.
How fast do the routin~s need to execute in ord'et: t,o"
assure operation at ,9600 baud,? Since POPDAT
interrupts occur every 617 microseconds, it is
possible to receive two complete interrupt requests
in every character time (1042 microseconds) at 9600
8-17
AF~'304A
APPLICATIONS
ROW 1
AOW2
ROW 3
ROW 4
,ROWS
'ROWS
ROW 7
ROW 8
ROW9
ROW 10
ROW 11
ROW 12
ROW 13
ROW 14
ROW 15
ROW1S
ROW 17
ROW 18
ROW 19
ROW 20
ROW 21
ROW 22
ROW 23
ROW 24
ROW 25
0800H
0850H
08AOH
08FOH
0940H
0990H
09EOH
OA30H
OA80H
OAoOH
OB20H
OB70H
OBCOH
OC10H
0C60H
OCBOH
OOOOH
OoSOH
OoAOH
OoFOH
OE40H
OE90H
OEEOH
OF30H
OF80H
0801 H ............. 084FH
0851 H .•........... 089FH
08A1H ............08EFH
08F1H ............. 093FH
0941H ..... , ....... 098FH
0991 H ......•...... 090FH
09E1 H ............ OA2FH
OA31H ........... OA7FH
OA81 H ........... OACFH
OA01 H " .......... OB1 FH
OB21 H ........... OBSFH
OB71 H ........... OBBFH
OBC1 H ........... OCOFH
OC11 H ............ OCSFH
OCS1 H ........... OCAFH
OCB1 H ........... OCFFH
0OO1H ........... 004FH
0051 H ........... 009FH
OoA 1 H ........... OoEFH
00F1H .... : .......OE3FH
OE41H .............OE8FH
OE91 H ............ OEoFH
OEE1H ............ OF2FH
OF31H. , ........... 0F7FH
OF81 H ....•....... OFCFH
ROW2
ROW 3
ROW 4
ROWS
ROW6
ROW 7
ROW 8
ROW9
ROW 10
ROW 11
ROW 12
ROW 13
ROW 14
ROW 15
ROW16
.ROW 1'7
ROW 18
ROW 19
ROW 20
ROW 21
ROW 22
ROW 23
ROW 24
ROW 25
ROW 1
0850H
08AOH
08FOH
0940H
0990H
09EOH
OA30H
OA80H
OAoOH
OB20H
OB70H
OBCOH
OC10H
oe60H
oeBOH
OoOOH
OoSOH
OoAOH
OoFOH
eE~OH
OE90H
OEEOH
OF30H
OF80H
0800H
After Initialization
ROW 3
ROW 4
ROWS
ROWS
ROW 7
ROW 8
ROW 9
ROW 10
ROW 11
ROW 12
ROW 13
ROW 14
ROW 15
ROW1€)
ROW 17
ROW 18
ROW 19
ROW 20
ROW 21
ROW 22
ROW 23
ROW 24
ROW 25
ROW 1
ROW 2
08AOH
08FOH
0940H
0990H
09EOH
OA30H
OA80H
OAOOH
OB20H
OB70H
OBCOH
OC10H
OCSOH
OCBOH
OOOOH
OoSOH
OoAOH
OoFOH
OE40H
OE90H
OEEOH
OF30H
OF80H
0800H
0850H
08S1H ............. 089FH
08A1 H ............08EFH
08F1.H ............. 093FH
0941H .............. 098FH
0991H ............. 090FH
09E1 H '; ........... OA2FH I
OA31 H : .......... OA7FH i
OA81 H ........... OACFH:
OA01 H ........... OB1 FH
OB21 H ........... OB6FH
OB71 H ...... ; .... OBBFH
OBC1H ........... OCOFH
OC11 H ........... OCSFH
OC61H ........... OCAFH
OCB1 H ........... OCFFH
0001H ......... .'. 004FH
0051 H ........... 009FH
OoA 1H ........... OoEFH
00F1 H ............ OE3FH
OE41 H ...... : ...... OE8FH
OE91 H ............ OEoFH
OEE1 H ............ OF2FH
OF31 H ............. 0F7FH
OF81 H ............ OFCFH
0801 H ............. 084FH
After 1 Scroll
08A1 H ............08EFH
08F1 H ...... , ...... 093FH
0941H ............. 098FH
0991H ............. 090FH
09E1H .........' ... OA2FH
OA31 H ........... OA7FH
OA81 H ........... OACFH
OA01H ........... OB1FH
OB21 H ..........'. OBSFH
OB71 H ,........... OBBFH
OBC1 H ........... OCOFH
OC11 H ........... OCSFH
OCS1 H ........... OCAFH
OCB1H ........... OCFFH
0001 H ........... 004FH
0051 H ........... 009FH
00A1H ..... 1. . . . . . OoEFH
00F1 H .....' .......OE3FH
OE41 H .............OE8FH
OE91H ............ OEoFH
OEE1H ............ OF2FH
OF31H ............. 0F7FH
OF81 H ............ OFCFH
0801 H ............. 084FH
08S1H ............. 089FH
ROW4
ROWS
ROW6
ROW 7
ROW 8
ROW 9
ROW 10
ROW 11
ROW12
ROW 13
ROW 14
ROW 15
ROW 16
ROW 17
ROW 1B
ROW 19
ROW 20
ROW 21
ROW 22
ROW 23
ROW 24
ROW 25
ROW 1
ROW 2
RO'W3
08FOH OSF1 H ............. 093FH
0940H
0941H ............. 098FH
0990H
0991H ............. 090FH
09EOH 09E1 H ............ OA,2FH
OA30H OA31 H ........... OA7FH
OABOH OAB1 H ........... OACFH
OAoOH OA01 H ........... OB1 FH
OB20H OB21 H ........... OB6FH
OB70H OB7,1H ......,.,.... OBBFH
OBCOH QBC1 H ........... OCOFH
OC10H OC11 H ........... OCSFH
Oe60H. OC61 H ........... OCAFH
OCBOH OCBi H ........... OCFFH
OOOOH 0001 H ........... 004FH
0050H, 0051 H ....... ; ... 009FH
OOAOH .OOA1H ........... OOEFH
OOFOH QOF1 H ............OE3FH
OE40H OE41 H .............OEBFH
OE90H OE91 H ............ OEDFH
OEEOH 'OEE1H ............ OF2FH
OF30H. OF31 H ............. 0F7FH
OFBOH 0,FB1 H ., ~ ......... OFCFH
OBOOH OB01 H ............. 084FH
OB50H OB51 H ..... : ....... OB9FH
OBA 1 H ............OBEFH
OB~H
After 2 Scrolls
After 3 Scrolls
Figure 6-4. Screen MemoryPUring SC,rolllng
ApPLICATIONS
baud. Each POPDAT interrupt executes in 211
microseconds maximum. This means that each
routine must execute in:
By adding up the times for any loop, it is clear that
all routines meet this speed requirement, with the
exception of ESC J. This means that if the terminal
is operating at 9600 baud, at least one character time
must be inserted after an ESC J sequence.
1042 - 2 • 211 = 620 microseconds
(
START)
I
INITIALIZE
211.25~
P011
53~1
I
CHREC
43~
r r r r r
t
r r
esc A esc B elc C esc D esc E esc H esc J esc K
78.7~ 324~ 10r~ 119~ 316~. 105~. 862~1
1 r r
LF
CR
310",1 306~. 42",1
OUT
'456
Figure 6-5. Timing Flowchart
AfN.01304A
00 1
00
Z
111Ia
004
ODs
8212
-
IC2
'8
4
;--
-
6
a
10
15
MO
11 STa
7~ A A A Al Ie, A A DIDo 01 Oz 03 04 05 06 o-,CE
1 Z 3 4 5 6 F18 23 22 1
9 1011 13 1415161 8
:to
O~ 22
2D
30 ALE
6.1:iA~~ '1
!
~
eLK
ADo lZ
ADI h3
ADf 14
A03 15
16
A04
ADs 17
'2
37 eLK OUT
ICC~
~
7474
A0719
Aa 21
IC1
A9 22
23
AID
All 24
+5
LIN~5
LOCAL
AI2 25
SIO
~~:~~--.!
I
AD6 16
8085
36 RESET
*5MF
-=
irr
DlJ
13 oSz
~
A7'
1
017
o~ 18
18
015
9
01 4
o13t-LOIZP-- •
TO
Kcs
2718
ODe 17
19
007
oOa ZI
ClR
-
IC5
A13 25
27
A14
A15 28
32
RO
RESET OUT
ORO 8275.-.! RST65
lR08275.....J! R8T 55
80S1
,
~. ~~
7404
7400
IC4 7400
7400
lC4
-~
ADDRESS
DECODE
PROM
Ie
A4
CS
Al
'2
A3
628123
DO
• 01
IC3
.
02
lis
•
8275 iiACK
05
07
3h8 PROM
47.
e§ ~114 HIGH
.7•
CS 2114 LOW
47'
8275 WR
04
06
Ce 2716
T
.~
47.
4.7K
J
,
, 8275
Cii
8275
iiii
+5
l;;47.
471C '
+5
Appendix 7.1
CRT TERMINAL -SCHEMATJCS
~1304A
APPLICATIONS
IC6
CS
IC7
-C CS
2114
A7 AS A5 A4 Aa A2 Al
171
2 3
'I' ,
Au
2114
'010,'02'0 IO,WE
A,I\; As ~ A:t A2 AIAg
171 2 3
1815 14 1312 II 0
4 1'16 l'
A8 Ag IOIlOziOalO4WE
5 16 1514 13 121 0
I
1
IC8
4J CS
2114
2114
A,I\; AS A, A3 A2AI AO AS A910110210a'O,WE
1712 a , I' 1'1' 1615 14 13 12, 0
A, I\; AS A, A3 A AI '0 I\; Ag 101102'Da I°4 WE
111 2 3 4 , 1
1514 13 12 1 0
6
5 "
11
1
~
IC9
Lc CS
1
I1
1
'-----
,
.,I
,
ICl
6 ,
,,
00 0,
--1.!
----1l!
47"
~
47"
+5
7404
7404
(4
4 3 2 1
27 28 1 2 5 6 1 8
~1l:t04050 I) III 21
A, lSI
DO 0,02 DaD4 05 06 07
..--l1 c/o
CS
AO [91
8253
IC20
H
GATE 2
GATE 0 fU.------PG 2 IC 14
8251 A
IC19
~J
TXD
~ SERIAL OUT
RXD
.!.-- SERIAL IN
OUT 0 r---PG 2 IC 11
CLKO _ P G 2 I C l 0
22
iiii
TO RESET
8085
OUT~
23
~
CS
~RO
10
WR
Viii
9
OUT 2 17
U
elK 2
RESET
ill
ill
+'8
t
TO IC 10
8085 elK ~ 2
TO CLK OUT
ON 8085
8-21
--
APPLICATIONS
Ao SHEET 1
A1 SHEET 1
DO SHEET 1
01 SHEET 1
02 SHEET 1
0 3 SHEET 1
o4 SHEET 1
o5 SHEET 1
o6 SHEET 1
o7 SHEET 1
Ro SHEET 1
'if"R SHEET 1
"
27 28 29 30 31 32 33 34
07 06 05 04 03 02 °1 °0
Viii 36 .
VCC
iiii 5
CS
~O
14 PCo
:::~
16 PC2
IC17
17 PC3
8255A-5
AO
15 PCI
~~
Al
6
9
T0051C3
8
35
PBo
TO RESET OUT 80B5
IB
RlO
19
13 PC4
PBI
~C
12 PC5
P82 20
Rl2
~()
11 PC6
PB3 21
Rl3
10 PC7
P84
22
Rl4
23
Rl5
24
Rl6
25
Rl7
~(,
-:.::-
BAUD RATE SENSE
SWITCHES AND
LINE-LOCAL
SWITCH
P85
vcc--1!
PB6
~
P87
PAO PAl PA2 PA3 PA4 PA5 PA6 PA7
4~
3. 2. I.
40+
Rli
10K"
39. 3+ 37.
Vcc
, Slo Sll Sl2 Sl3 Sl4 Sl5 Sl6 Sl7
KEYBOARD
RETURN LINES
KEYBOARD
SCAN LINES
Appendix 7.1
CRT TERMINAL SCHEMATICS
AFN-{)l304A
APPLICATIONS
11.34 MHz
XTAl
10pF
I
DI
3300
+5
330n
(4)
7404
-=-
7404
.9
DOTOSC
7410
DOT CLOCK
IC 10 7474
10
II ClK
PRESET
_IZ
TO IC3 07
TO IC3 03
TO IC3 06
TO IC3 04
2Z Ag
Z3Aa
00 9
01 10
14 H
CCs Z8
CC4 Z7
26
CC3
I A7
02 II
II
Z A6
10
CCz ZS
3 AS
CCI Z4
4 A4
03 13
14
04
Os IS
CCo Z3
S A3
06 16
3 B
lZ Z
6 AZ
07 17
Z A
LI 3
7 AI
lO 4
8 AO
Ro
WR
ZZ CS
8275
IC 13
6 oACK
TO ICI RST 6.S
S ORO
TO ICI RST 5.S
31 IRO
TO IlIO PIN S
IC15
19 18 17 16 15 14 13 IZ
ZI 07 06 Os 04 03 oz 01 DO
Z9
AO
'
CC6
2716
7 IC 16
ClK
IS
IZ G
lOAD
74166
TOCClK
8275
TO ClK 0
8253 PG l'
OH13
TO GATE 0
8253 PG 1
HRTC 7
VRTC 8
+5
lTEN 37
30 CClK .
1K
VSP 35
VERTICAL DRIVE
IC13
+5
1K
VIDEO OUT
+5
7410
OUTO
8253PG 1
74175
IC14
1K
7404
CRT TERMINAL
(6)
(5)
IC 11
HORIZONTAL
DRIVE
APPLICATIONS
action is taken. By operating the keyboard scan in
this manner an automatic debounce time of 16.67
millisecond~ is, provided.
Figure 7.2A shows the actual physical layout ofthe
keyboard and Figure 7.2B shows how the individual
keys were encoded. On Figure 7.2B the sca,n lines are
the numbers on the bottom of each key position and
the return lines' are the numbers at the top of each
key position. The shift, control, and caps lock key
were brought in through separate lines of port C of
the 8255. Figure 7.3 shows the basic keyboard
matrix.
In order to guarantee that two scan lines could not
be shorted together if two or more keys are pushed
simultaneously, isolation diodes could be added as
shown in Figure 7.4.
'
Appendix 7.2
KEYBOARD INTERFACE
The keyboard used in this design was a simple
unencoded ASCII keyboard. In order to keep the
cost to a minimum a simple scan matrix technique
was implemented by using two ports of an 8255
parallel I/O device.
'
When the system is initialized the contents of the
eight keyboard. RAM locations are set to zero., Once
every frame, which is 16.67 milliseconds the contents
of the keyboard ram is read and then rewritten with
the contents of the current switch matrix. If a non~ero value of one of the keyboard RAM locations is
found to be the same as the corresponding current
switch matrix, a valid key push is registered and
SPACE BAR
Figure 7-2A.' Keyboard Layout
"
'
TOP, NUMBER
= RETURN
LINE
BOTTOM"NUMBER = SCAN LINE.
Figure 7-2B. Keyboard Encoding
8-24.
~1304A
APPLICATIONS
Appendix 7.3
ESCAPE/CONTROL/DISPLAY CHARACTER SUMMARY
000
BIT
NUL
0001
SOH
~DCI
B
OC3
T
EOT
OC4
E
ENO
0110
ACK
NAK
F
0111
,d: :
1000
:/: i
SYN
i':,:,:~~: ,: CAN
. : "
I
1010
:;;:;;;:\~¥.:tt\
K
1101
1110
1111
VT
NOTE
L
FF
:::::,:
:
':
u
v
I
A
0
A
0
"
2
B
R
B
R
#
3
C
S
C
S
$
4
0
T
D
T
5
E
U
E
U
6
F
V
F
V
7
G
W
G
W
X
%
&
:
x
Y
EM
SUB
z
"ii:~~{,,:,:J
~S
8
H
X
H
)
9
I
Y
I
Y
*
J
Z
J
Z
+
K
[
K
<
L
\
L
-
M
1
M
>
N
i\
N
?
0
-
0
/
0
10 1
100
110
111
i
~
--
A
B
C
0
CLR
E
HOME
H
EOS
I
EL
J
A
RS
SO
0 11
P
(
GS
N
Sl
P
,ETB
HT
1100
@
W
1001
1011
!
S
C
0
0101
0 10
Q
OC2
ETX
0100
SP
R
STX
0011
100 10 1 '11 0 111
p
OLE
A
0010
010 0 1
001
@
0000
ESCAPE'
SEQUENCE
DI$PLA Y ABLE
CHARACTER
CONTROL
CHARACTERS
us
-
Shaded blocks
~
/
functions term mal will react to Others can be generated but are Ignored up on rec€.ltpt
8-25
AFN-lJl304A
APPLICAnONS'
SCAN LINES
0
1
2
3
4
5
6
7
+5
10K
0
10K
10K
rB
2
10K
'z
:::i'
'Z
a:
::;)
Iiia:
3
10K
4
10K
~
10K
6
10K
7
Figure 7-3. Keyboard Matrix
Appendix 7.4
PROM DECODING
SCAN LINES
As stated earlier, all of the logic necessary to convert
the 8275,into a non-DMA type of device was
performed by a single small bipolar prom. Besides
turning certain processor READS into DACKS and
WRITES for the 8275, this 32 by,8 prom decoded
addresses for the system ram, rom, as well as for the
8255 parallel 110 port.
Any bipolar prom that has aby eight configuration
could function in this application. This particular
device was chosen simply because it is the only "by
eight" prom available in a 16 pin package. The
connection of the prom is shown in detail in Figure
7.5 and its truth table is shown in FigUre 7.6. Note
lhat when a fetch cycle (M 1) is not being performed,
the state of the SOD line is the only thitig that
determines if memory reads will be written into the
8275's row buffers. This is done by pulling both
DACK and WRITE low on the 8275.
Also note' that all of the outputs of the bipolar prom
MUST BE PULLED HIGH by a resistor. This
prevents any unwanted assertions when the prom is
disabled.
10k
--------~---L------r_~------~~w
RETURN LINES
10k
--------~---L------r_~------~~5V
Figure 7-4. Isolating Scan Lines With Diodes
APPLICATIONS
(Ad' Wr) .
Ala
Appendix 7.5
CHARACTER GENERATOR
ENABLE
SOD
(8015)
A'0
DO
CE271.
At
D,
CE 2114
OIOOH.()BFFH
At
~
Ci 2114
(8015)
~
A11
OCOOH'()FFFH
Wi
'0,
(8085)
1271
A'2
~
D4
DACK
8275
~
DS
Ci
(8015)
M,
(8015)
8255
M, =SO'S,
Ci
DB
8~75
Vec
Vee
GND
GND
Dr
iiii
8275
Figure 7-5. Bipolar Prom (825123) Connection
'-
i '":c
0
:c :c
"0
0
IJ)
I~... I~... I~ l~
a:
;:
:I:
....
.,'"'" .,'"'" .,~ .,~ ~.,
C\i
~
:! '"
;::
(\j
",.
A4 A3 A2 A1 AO 07 06 05 04 03 02 01 00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
O·
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
l'
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
'1
0
1
0
1
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
As previously mentioned, the character generator
used in this terminal is a 2716 or 2758 EPROM. A
lK by 8 device is sufficient since a 128 character 5 by
7 dot matrix only requires 8K of memory. Any
"standard" or custom character generator could
have been used.
The three low-order line count outputs (LCO-LC2)
from the 8275 are connected to the three low-order
address lines of the character generator and the
seven character generator outputs (CCO-CC6) are
connected to A3-A9 of the character generator. The
output from the character generator is loaded into a
shift register and the serial output from the shift
register is the video output of the terminal.
Now, let's assume that the letter "E" is to be
displayed. The ASCU code for "E" is 45H. So, 45H
is presented to address lines A2-A9 ofthe character
generator. The scan ·lines will now count each line
from zero to seven to "form" the character as shown
in Fig. 7.7. This same procedure is used to form all
128 possible characters.
It should be obvious that "custom" character fonts
could be made just by changing the bit patterns in
the character generator PROM. For reference,
Appendix 7.6 contains a' flEX dump of the
character generator used in this terminal.
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
45H = 01000101
Address to Prom = 01000101 SL2 SL 1 SLO
= 228H - 22FH
Depending on state of Scan
lines.
Character generator output
Rom Address
228H
229H
22AH
22BH
22CH
22DH
22EH
22Ft-!
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
Rom Hex Output Bit Output'
01234567
3E
02
02
OE
02
02
3E
00
Bits 0, 6 and 7 are not used.
* note bit output is backward from conventipn.
Figure 7·6. Truth Table Bipolar Prom
Figure 7-7. Character Generation
8-27
AfN.01304A
APPLICAtiONS
Appendix 7.6
'HEX DUMP OF CHARACT.ER GENERATOR
:1000000001000000000000000000000000000000E~
:r000103~00000000000000000000000000000000E0
: 1000200000000000000000000000000000000000D0
: 1000303000000000000000000000000000000000C0
:100040000000000000000000000000000000000080
: 1000500000000003000000000000000000003000A0
:100060000300000000000000000000000000000090
:100070000000000000000000000000000000000080
:100080030030000000000000000000000000000070
: 10009000000000000000082A1C081C2A080000008C
: 1003A0000000000000000000000000000000000050
:100080030000300000000000000000003000300040
: 1000C0000000330000000000030000000000000030
: 1000D0000000000000000000000000000000000020
: 1000E0000000000000000000000000000000000010
:1000~0000000000000000000000000000000000000
: 1001000300000000000000000808080808000800BF
: 10011000141414000000000014143E143E141400C3
:10011000083C0A1C281E08000~2610080432300~r,D
i10013000040A0A042A122C0~080808000030~00023
:100140000804020202040800081020202010080~01
: 100150000B2A1C081C2A08003038083E080800009D
:1001n00300000000000808040000003C000000003~
:100170000000000000001800002010080402000029
;i~gi~~~gig~~~~rc~~~~1~~~~~~g~~r~~&~~ig~g§~
: 100lA000101814123E10100038021E2020221C00C7
:1001B0003804021E22221C003E2010~80404040001
: 1001C0001C22221C22221C001C22223C20100EIIJ079
: 1001D00000000800030830000000080300080904F3
:1001E00~1008040204081~000003E033E00030059
: 1001f000040810211J100804001C222010080S'300821
: 100200001C222A3A1A023C00081422223E22220012
: 100210001E24241C24241EIIJ01C22020202221C0074
: 10-322000182424242 42t11E033 E02020E:02023E1IJ04C
:100230003E02020E:1IJ20202003C02023A22223C00~E
: 100240002222223E222222001C08080808081C0044
:103250a0702020202~21C0022120A0h0A122200EE
:1002~000020202~202023EIIJ0223h2A2A2222220032
: 10027000222~2A32222222001C22222222221C0-392
: 100280031E22221E020202001C2222222A122C00FE
:100290001E22221E0A1222003C02021C211J201E00E~
: 1002A0003E080808080808002222222222221C00F8
: 1002B0002222222222140900222222222A3S2200fiE
:1002C0~022221408142222032222221408080900E4
: 1002DIIJ003E20100804023E001C04040404041C011J18
: 1002E00000020408102000003820202020203800C0
:1002~000081C2A0808080800000000000000007E12
:1~030000099011000000000000003C203C223C004E
: 1003100002021A2fi22221E0000003804840438003B
:1003200020202C3222223C00000038248C84B8005B
: 100330003824040E040404000000BC22223C203CAB
: 1003400002021A262222220008000808080890004B
:100350002000202020A42418020222120A1~2200C3
: 10036000880808080828900000003G2A2A2222007F
: 1003700000001A2n2222220000001824242418003B
: 1003800000001E 22221 E0202000-31C22223C20200D
: 1003900000001A260202020000003R0418201C0087
. : 1003A00008081C0808089000fM00222222324C0095
: 1003B0000000222222140800000022222A3E1400fB
: 1003C000020022140814220000032222223C2038dF
: 1003D00000003E1008043E0018888903888919002F
: 1003E00008080 80808080 8080C90912190910D0051
:1003F00000008C2B80010000000000000000000095
8-28
\
AFN-ol304A
APPLICATIONS
Appendix 7;7
COMPOSITE VIDEO
In this design, it' was assumed that the monitor
required a separate horizontal drive, vertical drive,
and video input. However, many monitors require a
composite video signal. The schematic shown in
Figure 7.8 illustrates how to generate a composite
video signal from the output of the 8275.
The dual one-shots are used to provide a small delay
and the proper horizqntal and vertical pulse to the
composite video momtor. The delay introduced in
the vertical and horizontal timing is used to "center"
the display. VRI and VR2 control the amount of
delay. IC3 is used to mix the vertical and horizontal
retrace and QI along with the R I, R2, and R3 mix
the video and the retrace signal and provide the
proper DC levels.
'
HRTC
VRTC
UK
7....
VIDEO }------IM--'
1500
COMPOSITE
VIDEO
OUT
Figure 7-8. Composite Video
Appendix 7.8
SOFTWARE LISTINGS
ISIS-II 811180/811185 MACRO ASSfMBlER, X111J8
LOC
CBJ
SEQ
SOURCE S'l'ATIi'J4ENl'
~3
$/IIIOIl85
4
; SYSTEM
1811111
18111
18112
18113
Atll1
AllIIII
6111111
611111
61111112
611113
1111111
1111111
14111
11811111
!W80
PORTA
PORTS
POR~
CNWD55
USTF
ISm
CNTII
CNT1
Q/T2
CNTM
CRTS
CRTM
INT75
TPDIS
~~
n
110011
1111111
1111114
110111
III11I11A
1111110
0011F
11012
11111115
1111118
1111118
F3
3lEIIIIF
21111108
22E3111F
22E80F
38110
32E1!W
32E2IIF
32EB!W
32E7111F
32EA8F
r.:=u ~ !~~U,
,8275
;8255 READ
IT!
,8253 ENAB 0 BY
1251 ENABLED BY
1811I11H
1801H
.
1811J2H
1811J3H
1lAlJ11I1H
"'"I11"H
6r/JI1II1IH
601111H
6r/J11I2H
60113H
11111111H
11111110H
14111H
0880H
=~=
26 CIRBOl'
27 LNGTH
28 STPTR
IIFE0
SOF'lWARE ALL I/O IS I41MRY MAPPED
11I01111H TO 07FFH
READ~"11H TO
11FFH
1811111H TO
~~ ~S'
1m
00511J
R()oI
i~~~~
~7
8
9
111
11
12
13
14
15
16
11
18
19
211
21
22
23
~tt215
33
34
35
36
37
339
8
4111
41
42'
43
18H
11I0511JH
IIFEIIH
Al4
A15
1FFF
,
'
·8255 PORT A ~ESS
;8255 PORT B ADDRESS
;8255 PORT C ADDRESS
;8255 CONl'ROL PORT ADmESS
·8251 FlAG)
;8251 Do\TA
·8253 COlNl'ER II
;8253 COUN'l'ER 1
;8253 COUN'l'ER 2
,8253 MODE wam
;8275 CONrROL ADDRESS
,8275 MODE ADDRESS
;8215 INTERRUPT CLEAR
;TOP OF DIS~Y RAM
;~B~I!!~\rs~LAY
,B0M'Q4 Y ClRseR
•LENGTH Of! eN: UNE
;LOCATION OF STACK pOINTER
: START PROOIWI
'
;ALL ~IA8LES ARE INITIAUZED BI!!FCRE ANYTHING ELSE
bI
LXI
SP&'TPTR
LXI
!!..~IS
SHLD
·N......,
SHLD
ClJW)
1IH
IMSTA
t.,.@ lsy
CUI(
STA
CURSXSTA
lfJ000H
;~VE A AND FlAGS'
-~VE HAND L
,SAVE D AND E
;ZERO H AND L
; PUT S'n\CK POIN'l'ER IN H AND L
;PUT S'D\CK IN D AND E
;GET POINTER
;PUT CURREN'l' LINE INTO SP
;SET MASK FOIt SIM
CURAD
t4VI
A,1iJC0H
SIM
REP!' CLNfIfl2)
pop
ENIl'4
pop
H
POP
H
POP
H
POP
H
POP
H
POP
H
POP
H
POP
H
\
POP
H
POP
H
POP
H
POP
H
Pop
H
POP
H
Pop
H
Pop
H
Pop
H
Pop
H
POP
H
Pop
H
POP
H
Pop
H
POP
H
POP
H
Pop
H
POP.
H
POP
H
POP
H
POP
H
POP
H
POP
H
POP
H
'H
POP
POP
H
'H
POP
'Pop
H'
1IOP
'H
H
POP
PoP
H
pop
H
RRC
,SII'I
LXI
MoD
;SET UP A
;GO, SACK TO ~ MODi:
;ZERO HL
• ADD S'D\CK,
hVrS'D\CK IN H AND L
;RIlSTtRE S'D\CK
;PUT BOM'QIt DISPIAY IN H AND L
-SWAP RroISTERS
;PUT HIGH ORDER IN A
;SEE IF ~'AS H
-IF ~LEAVE
~ PUT
OODER IN A
;SEE IF ~E AS L
;111' NOT LEAVE
;LOAD H AND L WITH 'l'OP OF SCREEN "'EMCRY
~ C,tRREN'r ADmE!)S
"
..
~f>"1'I99H
~
SPtiL
~lt;,
MfN,
CMP
JNZ
' MCN
CMP
JNZ'
'LXI'
SlIID
t4VI
SIM
H,LAST
'A 0.
H' ,
KPTK
A,E
L
KP1'K
'~f.R~IS
;M
A,ll:!H
;OUTPUT MASK
,~
AfN.Ol304A
.'
APPLICATIONS
00aA
008B
00ac
0080
008E
m
E1
F1
FB
C9
008F 3E18
0091 3IIJ
011J92 C1
=I~
~l
011J95 F1
0096 FB
0097 C9
0098 32EFIIJF
011J9B32F011JF
011J9E 32F10F
rg;
pop
H~
134
135
136
137
138
U3 8YPASS: im
SIM
U~
~
146
EI
LPl<8D:
l~
158
0M9 23
011JAA 7C
0MB B8
0MC C2A700
0MF 70
00S089
00B1 C2A7"0
0084 3E88
00S6 320318
B~
173
211UA0
368"
36""
3648
80
36EA
361f5
011lC7
"1IlC9
011lCC
811JCE
3E32
320360
3E32
320068
3E00
328060
CDOC00
C3F9"0
0aDl
"003
00D6
0009
80DC
811JDF
08E1
80E4
00E5
00E8
80EA
0088
00EC
00EF
08F1
00F2
3A0218
E60F
32EC0F
07
21C505
1600
SF
19
110360
3EB6
12
18
Sl~ i~
::~~ ~~
00F7 12
00F8 C9
l~a
lj~
176
177
178
179
18B
181
182
183
184
lR~
187
188
189
190
191
1
93
2
19
194
l~
197
198
1211J99
.....:
0 ,.,....a
. .unuu
201
202
203
204
205
206 '
207
208
209
210
211
212
213
214
215
216
217
'218
·SET MASK
;~PUT THE MASK
;gEDB~~
,GET H AND L
,GET A AND FLAG3
,ENABLE INTERRUPl'S
,GO BACK
,
,THIS CLEARS 'ftIE AREA CR RAM 'nIAT IS \SED
, fOR KEYBCP.RD JEBOUNCE.
159
16"
161 LOOP!!':
162
163
164
165
166
167
168
"1IJB9
008C
00SE
011lC0
011lC2
011lC3
011lC5
g
RET
147
148
149
150
157
III
~~U
0M7 3620
A,18H
8
pop'
pop
psw
144
145
l~~
!ggR=~
iGET A AND FlAGS
,TURN ON INTERRUPl'S
,GO BJlCK
EI
RET
•
;THIS ,IS 'ftIE EXIT ROUTINE FCR THE FRAME INTERRUPl'
141
153
154
R
psw,
irrA
som
STA
~THIS
SIInI
RETLIN
SCNLIN
,ZERO SHIFT CCNl'ROL
,ZERO RETURN LINE
,ZERO SCAN LINE
ROl1rINE CLEARS 'ftIE ENl'IRE SCREEN BY PUTTING
,SPACE CODES (21tH) IN EVERY LOCATION ON THE SCREEN.
LxI
LXI
MVI
INX
MCN
C".p
H,'D'DIS
B lAST
M:20H
H
A, H
B
LOOP!!'
A L
CMP
C'
JNZ 'LOOP!!'
JNZ
MeN
,;
,PU'f TOP OIl' SCREEN IN KL
·PU'f BOr'l'CM IN BC
;PUT SPACE IN ..
,INCREMEN'f POINTER
:GET H
;SEE IF SAME AS B
,IF NOr LOOP AGAIt.I
:GET L
.
;SEE IF SAME AS C
,IF Nar LOOP AGAIN
8255 INITIALIZATION
im
som
~.8!l!
~uo5
·MOVE 8255 CONrROL W
'LooK AT RXRDY
;IF HAVE CHARACTER 00 TO WooK
;GET KE'lBOI\RO CHARACTER
;IS IT THERE
;IF KEY IS PUSHED LEAVE
;ZERO ,A
'
;CLEAR KE'iOK
'LOOP AGAIN
; WAS KEY 0Cl'lN
·SAVE A IN C
!GET KE'lBOI\RO CHARACTER
; IS IT THE SAME AS KE'iOK
;IF SAME LOOP AGAIII/
; IF Nor SAVE IT
'SAW: IT
;GET LINE LOCAL
;WHICH WAY
'LEAVE IF LINE
ITIME.TO DO SCl'IE WCRK
'GET USART FLAG>
I REAlYi TO TRANSMIT?
;LOOP IF Nor REAlYi
;GET CHARACTER
;pu'r IN USART
• LEAVE
';READ USART
'S'mIP MSB
; pu'r IT IN MF>tooy
; LEAVE
KE'iOK
USCHR
RIM
ANI
80H·
JZ
'lRANS
JMP
CHRe::
LIl/\
\STIi'
ANI
01H
JZ
TRANS
LIl/\
USCHR
STA
lSTD
JMP
SETUP
LIlI\
USTD
ANI
07FH
STA
USCHR
JMP
CHRe::
;
;THIS ROUTINE CHECKS THE BAUD RATE SWITCHES, RESE'ffi THE
;SCREEN POINTERS AND READS AND LOOKS UP THE KE'lBOI\RO.
FRAME: • f.usH
PUSH
PUSH
PUSH
LIl/\
~SET
LaLD
SHLD
~SET
LM
ANI
PSW
H
D
B
INT75
A AND FLAG>
H AND L
D AND E
B AND C
8275 TO CLEAR INTERRUPT
UP THE POIN'mRS
TOPAD
ClRAD
;LOAD TOP IN, H AND L
; STORE TOP IN CURRENT AOCRESS
UP BAUD RATE
roRTC
0FH
~
~Afto
em
STBAUD
CMP
;SAVE
;SAVE
;SAVE
'SAVE
; READ
B
; READ BAUD RATE SWITCHES
;S'mIP OFF 4 MSB'S
;SAVE IN B'
;GET BAUD RATE
;SEE IF SAME AS B
; IF Nor SAME DO SCl'IETHING
: READ KEYSO\RO
LM
ANI
JNZ
CALL
JMP
KE~
40H
K'lOOWN
RIl
;IF DIFFERENT KEY HAS CHANGED
'GET KEY ~
;HAS
BEEN IX)NE BUmE?
'LEAVE! IF IT ~
;GET RE'ruRN LINE
;GET 'READY TO ZERO B
'ZERO B
;ROfA'lE A
'00 IT AGAIN
;pOINT H AT SCAN LINES
;GET SCAN LINES
'G ET READY TO LOOP
,START .C COON'rING
;ROl'A'lE A
;JUMP '1'0 LOOP
;GET RETURN LINES
A
SIWKEY
A,B
LOOPK
~
II
M,A
H
M,B
At 4SH
K YI:WN
~~
BYPASS
H,9:NLIN
~TA
H
PORTB
M
A
KYCHlI(;
KEYI:WN
01H
BYPASS
PORTS
B,0FFH
B
'nus
UP
II
AM
C:0FFH
C
UP1
A,B
!~~~~~E
;MOVE OVER THREE TIMES
;OR SCAN AND RETURN LINES
'SAVE A IN B
;GET SHIFT COO'l'ROL
; IS CONl'ROL SET
;SAVE A IN C
;GET SHIFT CQ\lI'ROL
;SAVE A IN 0
;S'lRIP CONTROL
;SET BIT
;IF SET LEAVE
; READ IT AGAIN,
;S'lRIP SHIFT
'SAVE A
;GET SHIFT COO'l'ROL
;S'lRIP CONl'ROL
• ARE. THEY 'rIlE SAME?
: If' SET LEAVE
;pu'r TARGET IN E
-ZERO 0
;GET LOOKUP TABLE
;GET OFFSET
;GET CHARACTER
; pu'r CHARACTER IN B
;GET PORTe .
;S'lRIP' BIT .
-
C
ro~TC
40H
C~
S 00
~~ft
'.
C
CN'l'JlolN
PORTe
20H
C,A
A~O
2 H
C
. SHrwN
E,B
o 0011
II:KYLKUP
0
A,M
SA
roRTC
1011
CAPLOC
;CAPS LOCK
~
~~
-GET A BPCK'
; SAVE CHARACTER
'SET A
;SAVE KEY ~
; LEAVE
STA
JMP
BYPASS
; ,
.
" .
; IF·TIIE CAP LOCK BUI'TON IS PUSHED THIS ROl1l'INE SEES IF
;TIIE CHARACTER IS B~EN 61H AND 7AH AND IF IT IS THIS
8-33
AfN-01304A
APPLICATIONS
flJ22£
flJ22F
flJ231
flJ234
flJ236
flJ239
8238
78
FE6fIJ
D\23f1J2
FE7B
0223f1J2
D62fIJ
C32382
395
. ,ROUl'INE .ASSll'IES THAT THE C~ ISL4P
:B~
!g~ ~T~REEN
;GO CLEAR THE RfST OF THE SCREEN
·CLEAR LINE C~
jGo CLEAR A LINE
,CIRSOR UP CHARACTER
,MOVE CURSOR UP
·CURSCR RI='" CHARACTER
;MOVE CURsOO~TO THE RIGHT
;CURS L TO ClEAR LINE
,CLEAR THE LINE
,00 aACK
RourINE MOVES THE CURSOR UP ONE LINE.
LoA
CURSY
CPI
80H
JZ
SETUP
OCR
A
STA
CtRSY
CALL
LOCtR
JMP
SETUP
.,
;THIS ROt1rINE MOVES THE
541
542 UPCtR:
543
544
545
54
6
54 7
548
549
558
551
CALCU
LOe88
CLUNE
SETUP ,
~SX
Nl'OVER
CURSY
ClItSOl'
0018
A
CURBY
A,j"H
CI..I(SX
LOCtR
SETUP
A
CURSX
WCtR
SETUP
,GET Y CURSCR
-IS IT ZERO
IF IT IS LEAVE
-MOW CURSOR UP
:SAVE ~ CURSOR
THE CURSOR
,LEAVE
i
;LQAD
CURSOR ONE UlCATION TO '1'IIE RIGttl'
~~~TI~ X~~
,
WAY OVER?
,IF Nor JUMP AROUND
-GET Y CURSCR
;SEE IF ON BarroM
, IF WE ARE JUMP
,INCRDoIENT Y CURSOR
,SAVE rr
,ZERO A
'
;ZERO X CURSCR
,LOAD THE CURSOR
-LEAVE '
;rNCRDoIEN'r X CURSOR
-SAVE rr
j t.Qr\D THE CURSOR
,LEAVE
,
ROtlrINE MOVES THE CUR:;oR LEFl' ONE CHARACm;t POSITION
AfN.01304A
APPLICATIONS
036E
9371
9373
9376
9379
037B
937E
937F
0382
9384
9387
938A
0380
938E
9391
0394
3AE29F
FE99
C28D03
F
0397
rII'399
939C
039F
r113A2
3E99
"32 E29F
32E1r11F
CDB8r113
C39F91
1
3D
32E19F
3E4F
32E20F
CD3803
C30F01
3D
32E20F
CD3893
C30F01
93A5 3E8r11
93A7 32EE0F
93M C3rllF91
03AD 3Efilrll
fil~ 32E2rIIF
fil 2 CD38r113
03B5 C3r11F91
fil3B8
03BA
r113BD
03Cfil
03C3
03C6
03C9
3ES9
32fil11fil
3AE29F
329fil1fil
3AE1filF
32r1101fil
C9
03CA
03CD
93Dfil
r113D3
fil3D6
9308
fil3DB
fil3DE
fil3E 1
ClE403
2
98
2
0F
C
4
03E4
93E6
93E8
fil3E9
r113EC
fil3EF
r113Ffil
r113F1
fil3F2
93F5
F
F
3
COB r113
C3rllFfill
3EFfil
r11618
04
21fil9r11S
l1Sfil00
77
19
fil5
C2EFfil3
C9
fil3F6 CDFC93
fil3F9 C39Ffili
fil3FC
r113FF
fil4fill
fil4fil4
94fil5
3AElfilF
FE18
CA5394
3C
32E1filF
579
571 LEFT:
572
573
574
575
576
577
578
579
580
581
582
583 HOVER:
584
585
586
587
588
589
59r11 H,
STA
L~
STA
RET
;Z!;:RO
; ZERO
;LOAD
;POLL
~uRrx
WAIE THE CURSOR
;PU'r 80H INTO A
; LOAD CURSOR INfO S275
;GET CURSOR X
; pu'r IT IN 8275
;GET CURSOR Y
;pu'r IT IN 8275
CURSX
CR'lM
CURS'{
CR'lM
~THIS RO~rINE
DOES A
bALL
CLSCR
SHLD
CALL
MVI
STA
STA
CALL
JMP
89
CLUNE
A~rIIH
C SX
CURS'{
LOCUR
SE'NP
LXI
A
' CURSOR X
CURSOR INrO S275
USART AGAIN
~M
FEED
;CALL CLEAR OCREEN
;pu'r TOP DISPLAY IN tiL
; PUT IT IN !.OC8r11
;CLEAR TOP LINE
;ZERO A
;ZERO CURSOR X
.;ZERO CURSOR Y
; LOAD THE CURSOR
; BACK TO USART
~'l'PDIS
hHIS RoorINE CLEARS THE SCREEN BY WRITING END OF RCl>I
;CHARACTERS INTO 'raE FIRST WCATION OF ALL LINES GI
;THE SCREEN.
~
MVI
INR
LXI
LXI
MOV
DAD
OCR
JNZ
RET
iTHIS
~ALL
JMP
A',filF9H
B,CURSOr
B
H,'1PDIS
D,UlIGTH
~,A
B
LOADX
RO~rINE
;PU'r EOO CHARJ\CTER IN A
; LOAD B WITH MAX Y
;00 TO MAX
ONE
; LOAD H AND L ITH TOP OF RAM
;MOVE 5r11H
SfilD INTO 0 AND E
;MOVE EOR IN'fO MEMCNY
;CHAN3E POINTER BY SrIID
;COlJ'fl' THE WOPS
;CON'rINUE IF Nor ZERO
;GO BACK
PLua
=
DOES A LINE FEED
LNFD1
SETUP
;CALL ROUTINE
;POLL FLAGS
;LINE FEED
Lor..
CPI
JZ
INR
STA
CURSY
CURSor
ONBor
A
CURSY
;GEt Y LOCATION OF CURSOR
;SEE IF AT BCJM'OM OF SCREEN
;IF WE ARE LEAVE
; INCREMENT' A
;SAVE r£W CURSOR
8-36
AFN.(Jl304A
APPLICATIONS
8488
8408
848E
8411
8414
8415
841,6
0419
841C
041D
841E
8421
0422
0423
0424
0427
0428
0429
842A
042B
842C
842D
842E
842F
8430
0431
0432
0433
0434
0435
0436
0437
0438
0439
043A
0438
043C
043D
043E
043F
0440
0441
0442
0443
0444
-0445
0446
0447
0448
0449
044A
0448
044C
044D
044E
044F
0450
0451
0452
CIY\S84
22ES8F
CD1S84
c00883
C9
F3
2AES8F
115080
19
EB
210080
39
EB
F9
212820
ES
ES
ES
ES
ES
ES
ES
ES
ES
ES
ES
ES
ES
ES
ES
ES
ES
ES
ES
ES
ES
ES
ES
ES
ES
ES
ES
ES
ES
ES
E5
ES
ES
ES
ES
E5
ES
ES
ES
ES
ffi
F9
FB
C9
0453 2AE30F
0456 22ES0F
0459 115800
045C 19
0450 01D00F
04,13 7('.
0461, 88
0462 C26D04
0465 7D
0466 B9
0467 C26D04
046A 210008
046D 22E30F
658
659
660
661
~~~
CALL·
SHLD
CALL
CALL
RET
;CALCUlATE AD~ESS
;SAVE TO CLEAR LINE
;CLEAR THE LINE
;LOAD THE CURSOR
;LEAVE
CALCU
LOe80
CLLINE
LOClR
664
hHIS RoofINE CLEARS THE LINE WHOSE FIRST ~ESS
665
; IS IN LOe80. PUSH INSTRUCTIONS ARE tSED TO RAPIDLY
666
;CLEAR THE LINE
667
668 CLUNE: hI
;NO
HERE
669
LHLD
~ ~
-GET LOe80
670
LXI
0, UlGTH
iGET IENT CURSOR X
764
CPI
LNG'rH
;HAS IT OONE TOO FAR?
765
JNZ
OK1
; IF NOT 0000
766
CALL
LNFOl
; 00 A UNE FEED
767
JMP
CGRT
;00 A CR
768 OK1:
STA
ClRSX
;SAVE ClRSOR
769
CALL
LOCUR
;LOAD THE CURSOR
77"
JMP
SETUP
; LEAVE
771
•
,
772
; THIS ROt1rINE TAKES THE TOP ADrRESS AND THE Y CURsal
773
• LOCATION AND CALCULATES THE ADOO&SS OF THE UNE
774
;THAT THE CURSOR IS ON. THE RESULT IS RETURNED IN H "
775 ,
;AND L AND ALL REGISTERS ARE USED.
2lDSl!J4
JAE19F
117
1161111
4F
119
7E
4F
23
7E
47
211lllF8
119
E8
2AE31lF
19
EB
2139FIl
19
mCSll4
E8
C9 ,
2139F8
19
C9
H~ CALCU:
778
779
789
781
782
783
784
785
786
787
788
789
7911
791
792
793
794
795
796
797
798
799 FIX:
81111
8111
MOV
DAD
MCN
MCN
INX
MeN
,MQV
LXI
0\0
XCHG
LHW
DAD
XCHG
LXI
mD
JC
XC!K;
RE:!'
LXI
DAD
RE:!'
JAE21!JF
1161111
4F
119
C9
8114
8115
806
807 ADX:
81lS
8119
8111
811
hHIS ROtrrINE ADOS '!'HE X ClRSOR LOCATION TO 'fHE ADDRESS
; THAT IS IN THE H AND L RmISTERS AND RETURI'l:) THE RESULT
iIN HAND L
•
fD.
CURSX
;GET C.URSOR
MVI
B,90H
;ZERO ~
MOV
CB,A
·pu'rcURSOR X'IN C
DAD
;ADD ClJlSOR X TO H AND L
RE:!' .
; LEAVE
g~~
gg
814
"405 """8
"""l
94075""8
9"02
"409 AIl1il8
"0113
04DB Fl!JIl8
"""4
9400 49119
"1il05
94DF 911"9
RLC
MVI
B,99H
C A
B'
A,M
C,A
H
A,M
B,A
H,IlF8""H
6
TOPAD
D
H,IlFIl3IlH
0
FIX
H,IIF83IlH
0
;GET LINE TABLE INTO H AND L
;G ET CURSOR INTO A
.
;SE:!' UP A FOR tool SiJNUIGT LINNll'J)
LINNtJII SET IL
ll'I+tJ,
rkl
TPD S+~UIGT LINNIM)
LINNlM SET ILl lM+tJ,
~
Tl'D S+JUIGT LINNU'4)
LlNNlM SET (LI NIM+1)
.
rkl
I J;
=
!KEY8Q\RO LOOI
925
DB
00H,99H
;BlANK AND NOTHING
926
DB
09H,99H
;NOTHING AND NOTHING
927
DB
99H,41H
;NOTHING AND A
928
DB
SAH,58H
;Z AND X
929
DB
43H,56H
;C AND V
NO CIfARACTER
<
AND ?
939
DB
42H,4EH
;B AND N
931
DB
59H,99H
; 'l AND NOTHING
932
DB
09H,20H
;NO CIfARACTER AND SPACE
933
DB
44H,46H
;0 AND F
934
DB
47H,48H
935
DB
09H,51H
;TAB AND Q
~
:G AND H
936
DB"
57H,53H
;W AND S
937
DB
45H,52H
;E ANDR
938
DB
54H,09H
;T AND NO CONNECTION
939
DB
1BII,21H
;ESCAPE AND' I
949
DB
40H r 23H
:@ AND •
941
" DB
24H,25H
:$ AND ,
942
DB
SEH,99H
;
A
AND NO COONECTION
AFN.()1304A
APPLICATIONS"
0586 0B
0587 00
0ra8 00
SW
SS
058B 011l
058C IIlIil
1Il58D 00
0SSE 1Il0
IIl58F 15
0590 09
0591 IIlF
0592 10
1Il593 0B
0594 IIlC
0595 fJA
1Il596 7F
1Il597 0A
0533 0B
059 ec
0~9A 00
o 9B 00
059C 00
0590 00
059E 00
059F 00
05.\1Il 00
05.\1 00
05.\2 00
05A300
05.\4 00
05.\5 00
05.\6 01'1
05.\7 lA
1'15.\8 18
05.\9,03
0!W. 16
05AB 02
0SAC 0E
0SAD 19
05.\E 00
0SAP 1'10
0580 20
05B1 04
1'1582 06
05B3 07
0ra4 08
o B5 00
0586 11
0587 17
0588 13
0589 06
058A 12
I'J58B 14
I'J58C 1'10
05BO IB
058E 10
058F IE
05C0 Ie
'05Cl 14
05C2 IF
05C3 00
05C4 00
05C500
:~~ ~~
05C8 03
0SC980
05CA 02
05Ca 40
0sec 01
05CD A0
05CE 00
0SCF 50
0500 00
0501 28
0502 00
0503 14
0504 00
05D50A
0506 00
943
944
945
946
be
0eH,098
,NOTHING
947
DB
00H,0eH
,NOl'HING
948
DB
011lH,00H
,NarHING
949
DB
00H,098
,NOTHING
950
DB
15H,09H
,CONTROL U AND I
951
DB
0FH,10H
;CONTROL 0 AND P
952
DB
esH,ecH
,CONTROL [ AND \
953
DB
fJAH,7FH
,LF AND DELETE
; THIS IS WHERE TIE CONTROL CfIARACTERS ARE LOOKED UP
954
DB
fJAH,0BH
,CONTROL J AND K
955
DB
IIlCH,00H
;CONTROL L AND NOTHING
956
DB
0eH,0eH
;NOTHING '
957
DB
0DH,0eH
;CR AND NOTHING
958
DB
0DH,00H
;CONTROL
959
DB
00H,l'JeH
;NOl'HING
960
DB
00H,1'J0H
;NOTHING
961
DB
0eH,I'JI'JH :
;NOTHING AND NOTHING
962
DB
lAH,18H
;CONTROL Z AND ){
963
DB
03H,16H
;CONl'ROL C AND V
964
DB
02H,0EH
;CONTROL B AND N
965
DB
19H,01'JH
;CONl'ROL Y AND NarHING
966
DB
00H,2eH
;MarHING AND SPACE
967
DB
04H,06H
;CONTROL 0 AND F
968
DB
07H,1'J8H
;CONTROL G AND H
969
DB
0eH,llH
970
DB
,17H,13H
,CONTROL WANDS
;CONTROL E AND R
root
AND CCXo!MA
;NarHING AND CON'mOL Q
971
DB
06H,12H
972
DB
14H,l'JeH
;CONl'ROL W AND NOTHING
973
DB
1BH,lDH
;ESCAPE AND HOME (CREDIT)
974
DB
lEH,lCH
;CtRSCR UP AND JnolN (CREDIT)
975
DB
14H,lFH
;CtRSCR RIGHT AND LEFT (CReDIT)
976
DB
00H,00H
;NarHING
977
978
979
980 BDLK:
be
00H,05H,69H,03H ;75 AND.110 BAUD
981
DB
80H,02H,40H,01H ;150 AND 300 BAUD
; LOOK UP TABLE Fm 8253 BAuo RATE GENERA'lm
982
DB
fJA0H,0eH
;600 BAUD
983
DB
50H,00H
;1200 BAUD
984
DB
28H,00H
,2400 BAUD
985
DB
14H,00H
;4800 BAUD
986
DB
fJAH,00H
;91)00 BAUD
8-41
AFN-01304A
APPLICATIONS·
ra~
;DATA AREA
bRG
989
rIlFEl
rIlrllrill
rIl0r1l1
rIl002
§~
CtRS'!': a;
CtRSX: a;
TOPAD: a;
Lae8r1l: a;
USCIR: a;
CURAD: a;
KE'ill'IN: OS
998 KSCllh a;
999 BAUD:
a;
1r1l00 KE'iOK: a;
1r1lrlll ESCP:
a;
1"02 SIC>N: a;
1r1lrll3 RETUN: a;
l01!J4 SCNUN: a;
1"05
END
992
993
994
995
996
997
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rIl""l
rIl"0l
"0"1
rIl00l
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1
2
2
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1
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PUBLIC Sl!MBOtS
EXTERNAL SYMBOtS
USERSYMBOtS
A "4CD
A "22E
A rIl327
A 60r1l3
A rIlFE2
FMFD A rIl3CA
ADX
CAPLOC
CLRLIN
CNlM
CURSX
~ArIlFEA
KYLKUP
LNFD
LPImor~'
access (DMA) controller. The design interfaces
directly with standard CRT monitors, contactclosure keyboards, and RS-232C serial-comnlunication links (asynchronous or bisynchronous), to provide a complete stand-alone operator ·interface.
Although the primary design goal-implementing
a low-cost CRT terminal-has excluded some useful
CRT features, these are easily made available
through additional external hardware. For exampl'e.
composite video is added with two TTL packages, ~
transistor, and some resistors and capacitors. Another simple option involves the two general-purpose
attribute output's on the 8276 and lets users select
anyone of four colors on a color. monitor.
Basic system configuration and architecture
Central to the 22-chip CRT controller design is an
iAPX 88/10 8-bit microprocessor operating at 5 MHz
and supported by two 8185 l-kbit x 8 static RAMs
and a 2716 control software PROM (Fig. 1). An 8251A
programmable communication interface provides
synchronous or asynchronous serial communica-
,
tions. Threp manual switches on the PC board select
the baud rate, and one of the 8253's three independent
programmablp interval timers generates the 8251A's
baud-rate clock under software control.
The three PC -board s\\'itehes an' monitored by the
iAPX 88/10 to determine the desired baud rate .
When the CPU detects a change in the switch
positions, the 8253 is loaded with the appropriate
count for the new baud rate.
An 8255A provides three 8-bit parallel I/O ports.
Two I/O ports ('on tribute ke~'board scanning, and the
vertoc}a
sync
Video
To'
CRT
HOrizontal.
_sync
(from 8253)
1. Intelligent terminals: b\liltwith Intel's iAPX 88/10 (8088)
microprocessor and new 8'276 small-system CRT controller,
take this basic configuration to reduce parts count and
minimize overhead on the system CPU.
Thomas ROSII, Applications Mgr. Peripheral Components
Intel Corp.
3065 Bowers Ave., Sant!! Clara, CA 95051
Electronic Design. April 30, 1981
Low-cost CRT
third port senses option-switch settings and tne
vertical-retrace signal ftom the 8276 (for CRT synchronization upon reset).
'The CRT dot and character timing is generated
by an 8284A clock generator. Another 8253 timer
provides the appropriate horizontal-retrace timing
for the CRT monitor. In its programmable one~shot
mode. this timer generates a 32-l's horizontal-retrace
pulse for the CRT monitor (Ball Brothers TV-12)., A
simple user-initiated change in the software will
modify this delay time to suit different CRT
monitors. The third and last timer in the 8253 is
available for any user-defined need.
A 2716 EPROM on the controller board serves as
a user-programmable character generator. A shift
register transforms the data from the character
EPROM into a serial-bit stream to il~uminate dots
on the CRT screen. The 2716 character generator
helps to create special symbols and characters for
word processing, industrial-control applications, or
foreign-language displays,
The controller hardware is divided into processor
and support, serial and parallel 110, and CRT-(!ontrol
sections. The processor and ,support section ronsists
of an iAPX 88/10 microprocessor, which is supported
by two 8185 1-kbit X 8 static-RAM devices, and
another 2716 EPROM (containing 2 kbytes of'control
firmware). The iAPX 88/10 uses a 15-MHzcrystal
(with an 8284A) 'to operate at a 5-MHz clock rate.
The 8185 memories attach directly to the iAPX 88/10
multiplexed bus. An 8282 latches eight address Unes
(Ao-A1) from the multiplexed bus for 2716-prograrri
memory access (Fig. 2).
The serial and parallel 110 section of the terminal
includes the 8255A programmable peripheral interface, and the CRT section'contains the 8276 CRT
controller and support circuits. Ali of the co~t~oller's
I/O operations are memory mapped (see tablel. '
.....
Memory map of contrOller I/O opefatIons
......
, Addreaa"
00000 - 00003
00004 • 00029
00030 • 007FF
01000 • 01001
01900
12000 • 12001
14000 • 14003
18000 • 18003
FF800 • FFFFF
Selected ,
RAM
RAM
RAM
eom.......
,':
Interlupt v.ector
".~
Stack, local vlrilbla' "
8276iJ
6276
8251 A
8253
8255A
2715
"
~Iay II"""
comm~.
8276 row buff.,
",
" >', "
Serial ch8nnel
Bauck... timer
Keyboard, .Itc""f~
:f,
Program storage
:;,;,,~
2., The processor and support section of the intelligent
terminal's hardware contains two 8185 RAMs attached '
directly to the ,APX 88/1 0 multiplexed bus, An 828211,tches
eight ilddress lin'es (Ao·A,) from the multiplexeo bus for 2716. ,
program memory access.
090-1'
How the ,controller board communicates
The CRT-controller board communicates. to computer systems and other CRT units through a serial
interface. Both RS-232C and TTIrcompatible interfaces are available at the J 1 connector. The unit's
standard software supports eight data-transmission
rates: 9600. 4800, 2400, 1200. 600, 300, 150, and 110
baud. These rates are switch-selectable on the PC
board. Since the baud-rate clock is generated by an
8253, baud rates may be easily modified in software.
Keyboard scanning is supported through the A and
B ports of a 8255A programmable perlphetal interface. Therefore, low-cost unencoded keyboards
can be used. The eight scan lines (port B) and eight
return line!> (port A) support a 64-contact c1osurekey matrix. The three switches attached to port C
permit baud-rate selection. Four general-purpose
Electronic D••lgn • April 30. 1981
CPU
control
,3.,~Here are the major lunctl~nal blocks 01 th~ 8276
prpgraf\lrYIable CRT controller. ThiSl!evlce'permlts software
, ~pecllicatlon of rYlost CRT ·screen format charactlnl'tlc,
(cursor position, characters/row, rowslframe).
inputs on port C permit the software to sense
depression of the ~aps-loCk ke~. the control key. and
the shift key. as well as the position of the line/local
switch. The ~st input on port C senses the status
of the vertical retrace (VRTC) output of the 8276. so
that, the controller can synchronize with the CRT
display on power up Qr ~fter a hardware reset.
All keybOard I/O connects to the te~minal board
by means' of a 40-pin header on its edge. All seven
option-switch inputs are also brought to the connector. so that option switches may be installed on the
key.board if desired.
Soft~are, specifies the screen format
The CRT display is controlled by the 8276 programmable CRT controller (Fig. 3). With this,device, most
CRT screen-format characteristics-such as the
cursor position, the number of characters per row,
and the numher of rows per frame~can he specified
through softwarp. Th(' 8276 handle~ all display timing including retrace time delays.
In" the current design, 2000 characters are displayed on 'the CRT screen (25 rows of 80 characters).
Each character is formed as a5 x 7-dot matrix within
a)arger 7 x 10 matrix (Fig. 4). Other screen formats
(e.g.• 16 rows of 64 characters) can be easily implemented with a few software changes and no
hardware changes.
The 8276 contains two 80-character row buffers
(see "Row l3uffers Reduce System Overhead"). While
one buffer displays the current character line on the
screen, the 8276 fills the other row buffer from
memory. This data transfer begins when the 8276
issues a data request (by means of the ,BRDY pin).
causing an interrupt to the CPU. In response to this
interrupt. the CPU activates the RAM's cs and RD
inputs. while simultaneously activating the 8276 BS
and WR inputs (Fig. 5). Through this technique. a
single bus cycle suffices to transfer each -byte from
the RAM into the CRT row buffer. After the row
buffer is filled, the CPU ex.its the in'terrupt-service
routine.
But the 8276 can do more than simply paint
characters on a CRT screen. Its end-of-row-stop
buffer-loading code allows the control software to
blank individual displa~' lines. Also, the end-of~the
screen-stop buffer-loading code initiates an erase to
the end of the screen.
The 8276 supports software selection of visiblefield "attributes" that can blink. underline. or highlight (intensify) characters on the screen and can
reverse the video-character fi~lds (black letters on
a white background). Two general-purpose attribute
outputs are provided to control the user-defined
display capabilities.
Hardware provides three support functions .
The 8276 is supported by three hardware functions: a dot/character-clock oscillator. an EPROM
character generator. and a character-shift register
(Fig. 6). The dot/character-clock oscillator consists
of an 8284A operating at 11.34 MHz and providing
an 88.2-ns dot clock. A 74LS163 divi(,('s this clock
by 7 to generate a 1.62-MHz (617-ns) character clock.
Line
number
o 0
o 0
o 0
o •
0
,0
0
•
0
0
o
0
0
0
0
o
0
[J
[J
• •o •
o
o
o
••
o
•• • •o •
• o o
0
[J
0
[J
0
0
000
0
0
0 0 [J
0
0
'0
0
0
•
•
0
'0
•
0
00
0
11088
AD
WA
8276
4. The dot',matrlx character font used
In the low-cost CRT controller creaies
85 X 7 chllracter In a 7 X 10 matrix,
(example shown hi an upper-case A).
Top and bottom lines are blanked for
character separation. and the
'
remalnlngllne Is r.servecnor
cur,or/underllne display;
CS AD
8185
5. Row-buffer loading for tha 8276 begins when a single 8088 string Instruction
moves'data bytes from the 8185 RAM to the 8276 row buffer. The 8088 CPU "thinks"
It Is loading the AXreglstl!r.
"
EI.ct~onlc D.olgn • April
30. 1981
Low-cost CRT
The 8276 is programmed to display one raster line
every 61.7 /ts-a complete character line every 617
ItS (ten raster lines). The 8276 is also programmed
to refresh the screen every 16.7 ms (60 Hz).
Each character row consists of ten raster lines.
Seven lines display the 5 X 7-character matrix, two
lines are blanked for row spacing, and one line
displays the cursor and underline.
The 8276 uses the line count (LOo-LC 3) outputs to
indicate the current raster line during the displa~'
of each character. These outputs, combined with the
character-code outputs (CCo-CCs), are sent to ,the
2716, which generates the dot pattern for displa~·.
This dot pattern is loaded into the shift register and
is serially clocked for display by the 11.34-MHz dot
clock.
During the vertical-retrace interval, the row buffer for the first line of the next frame is loaded by
the iAPX 88/10. When the frame starts, the 8276
outputs the first character on its CCo-CCs pins; the
LC outputs are all zero. Exactly 617 ns later, the next
character code is emitted by the 8276. This process
continues every 617 ns \ijltil all 80 characters have
been output. Then the 8276 generates a horizontalretrace pulse, which is converted to the appropriate
pulse width for the CRT monitor by the 8253.
At the end of the first raster line,' the 8276
increments the LC outputs. The next nine raster lines
are similar to the first-the 8276 outputs the same
80 character codes on the CCo-CCs pins for each of
the raster lines, and the LC outputs are incremented
after each raster line.
While the ten raster lines are being displayed, the
8276 is also filling the next row buffer. After the
tenth raster line is completed, the 8276 resets the
LC count and outputs character codes'for the second
row on the CCo-CCs pins. As this row is displayed,
the first row buffer is filled with information for
the third row. The 8276 alternates row buffers until
all 25 rows are displayed. At this time, the verticalretrace signal is activated, and the scanning process
is repeated for the next frame.
During display, the 8276 automatically activates
the video-suppress pin (VSP) andlor light-enable
outputs (LTE~', as appropriate. to control rl'trace
hlanking, genl'rate the cursor, or underline characters.
Software is split between two priorities
The software for the CRT controller is divided into
high and low-priority sections. The high-priority
"foreground" software is activated each time the
8276 requests (through the iAPX 88/10 NMI interrupt) that an 80-character row buffer be filled. The
8276 row buffer is filled by performing 80 sequential
memory reads. As each read is performed, the
~_~oHortzonJal
I--_L-/
out
·f-+===-..,--......------L.J
YERT
_r---
>:::::
'
UNE
SHIFT
REGISTER
J---
~
~
0,
LA,
:::.
.....)-
...:.-.t.J
0,
-
-
>-::">-
.........
~
~
0,
~
-
r--U
J-----
:::.')-V
~
-
~~1£
}"HOR'Z LEFT HALF
OUT
I ....~
-
I .....
....
~
-I
-I NIZATION
SYNCHRO·
;=L)"-VIDEO
,
L TEN
HIGHLIGHT
L--
Figure 22. Typical Character Attribute Logic
AFN·00224B,
intJ
8215
Table 2. Character AHrlbutes
Character attributes were designed to produce th'e following graphics:
DESCRIPTION
0000
Top Left Corner
0001
Top Right Corner
, 0010
Bottom Left Corner
0011
Bottom Right Corner
, 0100
Top Intersect
0101
Right Intersect
0110
Left Intersect
0111
Bottom Intersect
1000
Horizontal Line
1001
Vertical Line
1010
Crossed Li nes
1011
Not Recommended'
1100
Special Codes
1101
Illegal'
1110
Illegal
1111
Illegal
'Character Attribute Code 1011 is not recommended for
"normal operation. Since none of the attribute outputs are
active, the character Generator will not be disabled, and
an indeterminate 'character will be generated.
~
Character Attribute Codes 1101, 1110, and 1111 are iilegal.
Blinking is active when B = 1.
Highlight is active when H = 1.
AFN-00224B
inter
8275
Special Code.
Four special codes are available to help reduce memory,
software, or DMA overhead.
character follOWing the code up to, and including, the
character which precedes the next field attribute code, or
up tei the end of the frame. The field attributes ,are reset
during the vertical retrace interval.
Special Control Character
MSB
1 1 1 1
There are six ,field attributes:
LSB
0 0 S S
~SPECIAL CONTROL CODE
S S
FUNCTION
.
1.
Blink - Characters following the code are caused
to blink by activating the Video Suppressio'n out·
put (VSP). The bl ink frequency is equal to the
screen refresh frequency divided by 32.
2.
Highlight - Characters following the code are
caused to be highlighted by activating the Highlight output (HGLT) .
3.
Reverse Video - Characters following the code are
caused to appear with reverse video by activating
the Reverse Video output (RVV).
The End of Row Code (00) activates VSP and holds it to
the end of the line.
4.
Underline -
The End of Row·Stop DMA Code (01) causes the DMA
Control Logic to stop DMA for the rest of the row when it
is written into the Row Buffer. It affects the display in the
S8JT1e way as the End of Row Code (00).
5,6.
0 0
0 1
0
End of Row
End of Row-Slop DMA
.End of Screen
End of Screen·Stop DMA
The End of Screen Code (10) activates VSP and holds it to
the end of the frame.
The End of Screen·Stop DMA Code (11) causes the DMA
Control Logic to stop DMA for the rest of the frame when
it is written into the Row Buffer. It affects the display in
the same way as the End of Screen Code (10).
If the Stop DMA feature is not used, all characters after an
End of Row character are ignored, except for the End of
Screen character, which operates normally. All characters
after an End of Screen character are ignored.
Note: If a Stop DMA character is not the last character in a burst or
row, DMA is not stopped until after the next character is
read. In this Situation, a dummy"character must be placed in
memory after the Stop DMA character.
Field Attribute.
The field attributes are control .codes which affect the
visual characteristics for a field of characters, starting at the
Characters following the code are
caused to be underlined by activating the Light
Enable output (LTEN).
General Purpose - There are two additional 8275
outputs which act as general purpose, independ·
ently p.~o~rammable field attributes. GPA0-1 are
active high OlJtputs.
Field Attribute Code
MSB
LSB
10URGGBH
II T IL--
HIGHLIGHT
L·---BLINK
GENERAL PURPOSE
L..- - - - -_ _ REVERSE VIDEO
' - - - - - - - - - UNDERLINE
L._ _ _ _ _
H =1 FOR HIGHLIGHTING
B = 1 FOR BLINKiNG
R = 1 FOR REVERSE VIDEO
U = 1 FOR UNDERLINE
GG = GPA1, GP.AO
*More than one attribute can be enabled at the same time.
If the blinking and reverse video attributes are enabled
simultaneously, only the reversed characters will blink.
A~22'B
8215
The 8275 .C$n be programmed to.provid!! visible or invisible
field attribute characters.
Each row buffer has a corresponding FIFO. T!1ese FIFOs
are 16. characters by 7 bits in size.
If the 8275 is programmed in the visible field attribute
mode, all field attributes will occupy a position on the
screen. They will appear as blanks caused by activation of
the Video Suppression output (VSP). The chosen visual
attributes are activated after thi.s blanked character.
When a field attribute is placed in the row buffer during
DMA, the buffer input controller re.cognizes it and places
the next character in the proper FIFO.
When a field attribute is placed in the Buffer Output Con·
troller during display, it causes the controlier to immedi·
ately put a character from the FIFO on the Character Code
outputs (CCo-e). The chosen Visual Attributes are also
activated.
Since the FOtFO is 16 characters long, no more than 16 field
attribute characters may be used per Une in this mode.
If more are used, a bit in the status word is set and the first
characters in the FIFO are written over and lost.
ABC 0 E
F G H I J K L M
N 0 P 0 R S T.U V
Note: Since the FIFO is 7 bits wide, the MSB of any characters put
in it are stripped off. Therefore, a Visual Attribute or Special
Code must not immediately follow a field attribute code. If
1 2 3 4 5
this situation does occur, the Visual Attribute or Special
Code will be treated·as a normal display character.
6 7 8 9
Figure 23. Example of the Visible Field Attribute
Mode (Underline Attribute)
If the 8275 is programmed in the invisible field attribute
mode, the 8275 FIFO is activated.
ABCDEFGHI J KLM
NOPORSTUV
CCLK
1 234 5 6 7 8 9
CC0-6
Figure 25. Example of the Invisible Field Attribute
Mode (Underline Attribute)
LCO_3
LAo-,
HRTC
VATe
HlGT
RVV
LTEN
VSf'
"r-----.,..~
GPAo-1
LPEN
Figure 24. Block Diagram Showing FIFO
Activation
Field and Character Attribute Interaction
Character Attribute SymbolS are affected by the Reverse
Video (RVV) and General Purpose (GPAO_l) field attri· .
butes. They are ,not affected by Underline, Blink or High·
light field attributes; however, these characteristics can be
programmed individually for Character Attribute Symbols.
'.. 8~
AFN-00224B
8275
Cursor Timing
Device Programming
The cursor location is determined by a cursor row register
and a character position register which are loaded by com·
mand to the controller. The cursor can be programmed to
appear on the display as:
The 8275 has two programming registerS, the Command
Register (CREG) and the Par;lmeter Register (PREG). It
also has a Status Register .(SREG). The Command Register
can only be written into and the Status Registers can only
be read from. They are addressed as follows:
1.
2.
3.
4.
a
a
a
a
blinking underline
blinking reverse video block
non-blinking underline
non·bl inking reverse video block
The cursor blinking frequency iS,aqual to the screen refresh
frequency divided by 16.
If a non·blinking reverse video cursor appears in a non·
blinking reverse video field, the cursor will appear as a
normal video block.
If a non·blinking underline cursor appears in a non·blinking
underline field, the cursor will not be visible.
Light Pen Detection
A iight pen consists of a micro switch and a tiny light
sensor. When the light pen is pressed against the CRT screen,
the micro switch enables the light sensor. When the raster
sweep reaches the light sensor, it triggers the light pen
output.
If the output of the light pen is presented to the 8275
LPEN input, the row and character position coordinates are
stored in a pair of registers. These registers can be read on
command. A bit in the status word is set, indicating that
the light pen signal was detected. The LPEN input must be
a 0 to 1 transition for proper operation.
Note: Due to internal and external delays, the character position
coordinate will be off 'by at 'least three character positions.
This has to be corrected in software.
AO
OPERATION
REGISTER
0
Read
0
Write
PREG
1
Raad,
SREG
1
Write
CREG
PREG
The 8275 expects to receive a command and a sequence
of 0 to 4 parameters, depending on the command. If the
proper number of parameter bytes are not received before
another command is given, a status flag is set, indicating an
improper command.
INSTRUCTION SET
The 8275 instruction set consists of 8 commands.
COMMAND
Reset
Start Display
Stop Display
Read Light Pen
Load Cursor
Enable Interrupt
Disable Interrupt
Preset Counters
NO. OF PARAMETER BYTES
4
o
o
2
2
o
o
0
In addition, the status of the 8275 (SREG) can be read by
the CPU at any time.
1\FN-00224B
-inter
8276'
1. Reset Command:
Parameter - UUUU Underline Placement
DATA BUS
OPERATIDII\
Command
Write
Ao Dl!St;RIPTION MSB
0
0
Sc....n ComP
Byte2 "
V V R R R R R R
0
Scree.Comp
Byte 3
U U U U L L L L
0
Write "
Write
Write
-- After
I
-
0, Screen ComP
__ By.t~4 ._.
--
U U U ,U
0 "0 0 0' 0 0 0
Rtiset Command
Se
'2.0
TEST POINTS
<
.8
/
x=
DEVICE
UNDER
•
•
TEST
,
~C:
\
A C TESTING INPIJTS'ARE DRIVEN AT 2 4V FOR A LOGIC "1" AND 0 4SV
FOR A LOGIC "0 "TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A
LOGIC" 1" AND 0 8V FOR A LOGIC "0 "
Co. INCWDES JIG CAPACITANCE
8-73
"
8276
SMALL SYSTEM CRT CONTROLLER
• Dual Row Buffers
• Programmable Scree.n and Character
Format
• Single +5V Supply
• 6 Independent Visual Field Attributes
• 40-Pln Package
• Cursor Control (4 :rypes)
• MCS-51®, MCS-85®, iAPX 86, and
iAPX 88 Compatible
• 3 MHz Clock with 8276-2
The Intel 8276 Small System CRT Controller is a single chip device intended to interface CRT raster scan
displays with Intel microcomputers in minimum device-count systems. Its ptimary function is to refresh the
display by buffering character information from main memory and keeping track of the display position of the
screen. The flexibility designed 1nto the 8276 will allow Simple interface tq almost any raster scan CRT display.
.
It can be used with the 8051 Single Chip Microcomputer for a minimum IC count design.
CCLI(
Vee
LC.
LC,
NC
.NC
LTEN
RVV
DIIo-7
CCO-
VSP
6
GPA,
Q';Ao
BRDY
LCo-,
lIS
RD
HLGT
NC
INT
DIIo
CCo·
CCs
DB,
RD
DB.
WR
C/f'
RASTER TIMING
AND
VIDEO CONTROL
ca
HRTC
VRTC
HLGT
RVV
LTEN
VSP
GPAo-l
DB3
DB.
DBs
Des
~.
GND
Figure 1. Block Diagram
2'
CC3
CC.
CC,
CCo
Ci
CiP
Figure 2. Pin Configuration
8-74
8276
'Table 1. Pin Descriptions
PIn
Symbol ,No. Type
LC3
LC2
LC,
LCo
,1
2
3
4
0
BRDY
5
0
as
6
I
PIn
Symbol No. Type'
, N~me and FunCtIon
Vee
+5V flOWer aupply.
NC
39
No connection.
NC
38
LTEN
37
RW
38
0
Reve,.. video. Output signal used to
activate the CRT circuitry to reverse the
video signal. This output is active at the
cursor position if a reverse video block
cursor is programmed or at the positions specified by the fielll attribute
codes.
VSP
35
0
Video auppresslon. Output signal
IIsed to blank the video signal to the
CRT. This output is active:
- during the horizontal and vertical retrace intervals.
- at the top and bottom lines of rows if
underline is programmed to be number 8 or greater.
- when an lind of row or end of ~reen
code is detected.
- when a Row Buffer under run occurs.
- at regular intervals (1/16 frame frequency, for cursor, 1132. (rame. frequency for a.ttributesl~to create
blinking displays as specified by
cursoror.field attribute programming.
GPA,
GPAo
34
33
0
General purpose attribute codes.Outputs which are enabled by the general purpose field attribute codes.
HLGT
32
0
Hlgbllght. Output signal used to intensify the display at particular positions
on the screen as specified by the field
attribute codes.
No connection.
0
Buffer ready, Output signal indicating
that a Row Buffer Is ready for loading of
character data.
Buffer . .Iect. Input signal enabling
WR for character data into the Row
Buffers.
HRTC
0'
Horizontal retrace. Output signal
which is active during the programmed
horizontal retrace interval. During this
period the VSP output is high and the
LTEN output is low.
,8
0
Vertical retrace. Output'signal which
. is active dllring the programmed vertical retrl!'ce interval, During this period
the VSP output is high and the LTEN
oui'put is low.
RD
9
I
Read Input. A control signal to read
registers. ,
WR
10
I
Write Input. A control signal to write
commands into the control registers or
write data onto ,the row buffers.
NC
11
DBo
DB,
DB2
DB3
DB4
DBs
DB6
DB7
12
13
14
15
16
VRTC
I
7
No connection,
I/O
Bidirectional data bile. Three-state
lines. The outputs are enabled during a
read of the C or P ports.
17
18
19
Ground 20'
I
Nam_itdFunction
40
Une count. Output from the line count·
er which ill used to acjdress the character generator for the line positions on
the screen.
Ground.
Light enable. Output signal used to
enable the video signal to the CRT. This
output, Is active at the programmed
underline cursor position, and at positions specified by attribute codes.
.
INT
31
0
Interrupt output.
CCLK
30
I
Character clock (from 'dot/timing
logic).'
COs
CCs
CC4
CC3
CC2
CC,
CCo
29
28
27
26
25
24
23
0
Character code •• O~tput from the
row buffers used for character selection in the character genllrator.
cs
22
I
of status or
Chip select. Enables
WR of command or parameters.
CI P
21
AD
{
I
Port addre... A high input on this pin
selects the "c" port or command registersand a low Inputselecte the "P" port
or parameter ~Isters.
I
8~75
.
AFN·OO22"!'
8276
FUNCTIONAL DESCRiPtiON
Character C.ounter
Data Bus Buffer,
The Character Counter is a programmi:lble counter
that is used to. determine the number of characters
to be displayed per row and the length of the horizontal retrace interval. It is driven by the CCLK
(Character Clock) input. which should be derived
from the external dot clock. '
This 3-state. bidirectional. 8-bit.buffer is used to
interface the 8276 to the system Data Bus.
This functional block accepts inputs from the Sys~
tem Control Bus and generates control signals for
overall device operation. It contains the Command.
Parameter. and Status Registers that store the various control formats for the device functional
definition.
C/P
OPERATION
0
Read
REGISTER
RESERVED
0
Write
PARAMETER
1
Read
STATUS
1
Write
COMMAND
Line Counter
The Line Counter is a programmable counter that is
used to determine the number of horizontal lines
(Raster Scans) per character row. Its outputs are
.used to address the external character generator.
Row Counter
The Row Counter is a programmable counter that is
used to determine the number of.character rows to
be displayed per frame.and length of the vertical retrace interval.
RD (READ)
A "low:,' on this input informs the 8276 that the CPU
is reading status information from the 8276.
WR (WRITE)
A "low" on this input informs the 8276 that the CPU
is writing data or control words to the 8276.
CS (CHIP SELECT)
A "low" on this input selects the 8276.for RD or WR
of Commands. Status. and Parameters.
Raster Timing and Video Controls
The Raster Timing cirCUitry controls the timing of
. the HRTC (Horizontal Retrace) and VRTC (Vertical
Retrace) outputs. The Video Control circuitry controls the generation of HGLT (Highlight). RVV (Reverse Video). LTEN (Light Enable). VSP (Video Suppress). and GPAO-l (General Purpose Attribute)
outputs.
BRDY (BUFFER READY)
A "high" on this output indicates. that the 8276 is
ready to receive character data.
Row Buffers
BS (BUFFER SELECT)
A "low" on this input enables WR of character data
to the 8276. row buffers.
The Row Buffers are two 80-character buffers. They
are filled from the microcomputer system memory
with the character codes to be displayed. While one
row buffer is displaying a row of characters. the
other is being filled with the next row of characters.
INT (INTERRUPT)
A "high" on this output informs the CPU that the
. 8276 needs interrupt service.
C/P
RD
WR
CS
0
0
0
1
1
0
0
0
1
1
X
X
.X
0
1
1
0
0
1
X
1
1
X
o'
0
l'
X
1
Buffer Input/Output Controllers
as
Reserved
Write 8276 Parameter
1 Read 8276 Status
1 Write 8276 Command
0 Write 8276 Row Buffer
X. High Impedance
1 High Impedance
The Buffer Input/Output Controllers decode the
characters being placed in the row buffers. If the
character is a field attribute or special code. they
control the appropriate action. (Example: A "Highlight" field attribute will cause the Buffer Output
Controller to activate the HGLT output.)
1
1
8-76
AFN-0022AB
inter
8276
The 8276 uses BRDY to request 'character data to fill
the row buffer that is not being used for display.
SYSTEM OPERATION
The 8276 is programmable to a large number of different displllY formats .. It provides raster timing, display row buffering, visual attribute decoding and
'cursor timing.
.
The 8276 d,isplays character rows one scan line at a
time. The number of scan lines per character row,
the underline position, and blanking of top and bottom. lines are programmable. (See Programming
Section.)
It is designed to interface with standard character
generators for dot mat~ix decoding. Dot level timing
.
must be provided by external Circuitry.
The 8276 p.rovides special Control Codes which can
be used to minimize overhead. It also provides Visual Attribute Codes to cause special action on the
screen without the use of the character generator.
(See Visual Attributes Section.)
General Systems Operational Description
Display characters are retrieved from memory and
displayed on a row-by-row basis. The 8276 has two
row buffers. While one row buffer is being used for
display, the other is being filled with the next row of
characters to be displayed. The number of display
characters per row and the number of character
rows perframe are software programmable, providing easy interface to most CRT displays. (See Pro'gramming Section.)
INT
The 8276 can generate a cursor. Cursor location and
format are programmable. (See Programming
Section.)
LC o :3
BROY
8088
MICRO-
The 8276 also controls raster timing. This is done by
generating Horizontal Retrace (HRTC) and Vertical
Retrace (VRTC) signals. The timing of these signals
is also programmable.
ceo
os
PROCESSOR
6
8276
cs
I
CClK
..,
8253-5
COUNTER!
TIMER
. AND
INTERFACE
TO CRT
VERTICAL SYNC
INTENSITY
1t
"
HORIZONTAL SYNC
DOT
VIDEO CONTROLS
~t
::..
HIGH
SPEED
TIMING
LOGIC
CONTROLLER
...,
...
(ROM OR
RAM)
CRT
I DE&'~R I
'" "
VIDEO SIGNAL
CHARACTf:.R
GENERATOR
SYSTEM BUS
"..
"'"
"..
... ,..
'"
...
8251A
USART
..,
i'-
-
CCLl
T""POINTS
<0..2.0~
'K'
FOR A.C TESTING. INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC "1"
AND 0 45V FOR A LOGIC "0 " TIMING MEASUREMENTS FOR INPUT
AND OUTPUT SIGNALS ARE MADE AT 2.0V FOR A LOGIC "1" AND
8V FOR A LOGIC "0 "
o
AFN.Q0224B
ARTICLE
REPRINT
AR-255
By managing tasks like graphics generation and CRT refreshing, a
dedicated VLSI display controller simplifies the design of intelligent
graphics work stations.
.
Dedic~.ted
VLSI chip lightens
graphics display design load
printed-circuit board. This type of system requires
The role of graphics is becoming increasingly ima resolution of about 512 by 512 pixels and is
'portant for unscrambling the communications traffrequently called on to display three-dimensional
fic between people and computers. Thanks to microobjects in various perspectives. To minimize the
processors and dedicated control ICs, designing
distortion of rotating objects, horizontal and vertihigh-reliability graphics work stations is now eascal pixels should be equally spaced.
'ier and less expensive than in the days of smallA' typical display (500 vertices) must be drawn on
scale integration and expensive discrete-circuit
CRT technology. Microprocessors simplify workthe screen in less than 1 second to provide satisstation design by transferring some graphics confactory interaction with the operator. The display
may consist of lines, arcs, filled areas, and colorstrol tasks from hardware to software. However, a
dedicated VLSI controller such as the 82720-with
seven colors are acceptable (see "A Look into
Graphics Fundamentals").
an on-board graphics processor-can push another
step forward toward fast and economical design of
Seri!!1 link interfaces station
high-quality intelligent graphics systems.
A typical ~pplication for the controller is a • An intelligent work station usually interfaces
with a mainframe host via a serial communications
graphics work station aimed at high-end business
link, a keyboard, and a serial link with an optional
and low-end engineering systems. Since such a
graphics tablet. This type of graphics input/output
station usually fits on the top of a desk, all of the
subsystem is -diagrammed in Fig. 1. Two 51/4-in.
electronics must be contained within a single
floppy disks can satisfy the mass-storage needs of
the system. Disk formatting must be compatible
Gary DePalma, Field Applications Engineer
with the requirements of an IBM personal computMark Olson, Product Marketing Engineer
er. Moreover, general-purpose software written for
Roger Jollis, Design Engineer
Intel Corp.
2625 Walsh Ave., Santa Clara, Calif. 95051
from ELECTRONIC DESIGN- January 20, 1983
,
\,
<
controller
Computer Graphics: Graphics display
" "" 'I
~ ~,'
\
1-;
'
this computer must~lso be ~ble to'run 'on the work- 'descl'ibedby a transformed display list ate reduced
station,
to a series of dnts and placed in the image I1lemory.
,Two of the most basic functions of a graphics
The selection of the dots that will be activated is
achieved through a scanning conversion algorithm,
system are generating and refreshing images on
which must create lines that appear very smooth;
the CRT screen. Information pertaining to the
images is stored in the bit-map memory, where
start and end as expected, and look symmetrical no
monochrome pixels are represented by single bits
matter in which direction they are drawn. The
algorithm is repeated thousands of times to draw a
and color pixels by groups of bits. Ljljes and arcs
defined in ,nQrmalized screencoordinates must be
single picture and thus must operate as quickly as
converted into images of the'physical object.
, possible. At the sam~ time, the image iri memory
In a bit-mapped raster 'graphics system,' lines
must be repainted on the- screen 30 times/s for
,
.
,""
,
.
1. A graphics 110 subsystem for an intelligent work ~jation consists of input peripherals
(a keyboard andJablet), a serial communications link, and,mass storage (floppy disks).
Intelligence is pro)llded,by the mlcroproces8or'aildthe peripheral and memory controllers
(a). The three bllisic -tasks Performed-I/O, transformation processing. and CRT control-all
require data ,in t~e form of display lists stored in Ii d,!ta base (b).
8-92
interlaced frames and 60 times/s for noninterlaced
frames. Simple tasks, they nevertheless demand a
high memory bandwidth.
Unlike other system control tasks, gen,erating
graphics figures requires both bit-manipulation
and mathematics capabilities. Integer addition and
multiplication operations calculate the coordinates
of points on a line or a circle. But since pixels
generally are neither complete words nor bytes,
logical operations must be performed on the bits
within the word that contains the selected pixel.
The irtner loop of a so-called Bresenham linedrawing algorithm requires two or three addition
operations, two comparisons or tests, and the masking of tile correct value into the word for each pixel.
Algorithms for drawing circles or filling areas are
even more complex. In the inner loop of a filling
algorithm, for example, the old word must be read
from the bit map to determine whether some, all,
or none of the pixels are within the area to be filled.
If they are, the 'algorithm tests whether the pixels
must be modified and then returns the word to the
2. The 82720 graphics display controller separat.. the t.ska of graphics generation and CRT
refruhing from other .ystem tasks. That parmlts much greater aystem bandWidth, leading to
graphics work ..tatlons that not only draw sharp pictures, but a180 offer color.
3. ,Three m,niory plline••re implamentect in the II:!~ between the bit map ,and the gra""ICII' di....ay , '
controller. Three primary colOra-red, green, and blue-are provided, with tha cOiltroiler'. upper add,... bits
rupon.ible for .eJectlng the memory plane. during reed/Todlry/wrlle cyclee,.
'"
'
8-93
computer Graphics: Graphics display controller
bit map. Because such algorithms are heavily exercised, they must execute at extremely high speeds
to avoid an adverse impact on the system's overall
efficiency.
Memory bandwidth is the most precious commodity in a graphics system. In this application,
screen refreshing requires that 750,000 bits be read
60 times/s, equating to a bandwidth of almost 6
Mbytes/s. The picture refreshing, therefore, has
the highest.-priority access to memory because any
missed readings show up as noise in the picture, a
situation th,at sometimes occurs with simple systems possessing a single-microprocessor, singlememory scheme.
In the latter type of design, one processor handles
all functions except refreshing, which is imple-
8-94
men ted by a discrete counter arrangement or a
simple CRT controller chip. Nevertheless, the re- ,
fresh memory bandwidth always slows down the
microprocessor. That loss of speed can be eliminated simply by separating the processor's memory
system from the bit map, a process that effectively
doubles system memory bandwidth.
The 82720 graphics display controller can provide
the means of separating graphics generation and
CRT refreshing from the other tasks and also
perform the two tasks quickly and concurrently
with the others. Residing between the microprocessor and the bit-map memory and video logic,
the controller refreshes the CRT ljke other CRT
controllers, converts high-level commands into images by placing the proper data into the correct bit
map, and interfaces easily ana simply with proprietary microprocessors.
The 82720 accepts high-level commands (such as
DRAW LINE, DRAW ARC, and FILL RECTANGLE) and
executes them at much faster speeds than generalpurpose microprocessors, primarily because it is a
dedicated graphics hardware processor. Burst
drawing rates as high as 1 pixel every 800 ns can be
achieved. Screen refreshing is handled directly by
the controller. The displayed portion of the bit-map
memory can be configured to allow the display to be
scrolled through memory in any direction. The horizontal and sync periods both are fully programmable, as is the position of the sync pulse in
the blanking interval. Furthermore, the controller
can be programmed to refresh low-cost dynamic
RAMs. In the design 'being considered, the 82720
offloads the microprocessor from low-level graphics
tasks, as shown,in Fig. 2.
For the bit-map interface, the memory is implemented as three planes, each 16 kwords by 16 bits,
with each plane driving red, green, or blue (Fig. 3).
The upper address bits-A16 and A17 -select the
memory planes during read/modify/write cycles
but are ignored during screen refreshing cycles.
The graphics display controller generates the
Row Address Strobe (RAS) signal for the dynamic
RAMs, but the remaining timing signals must be
supplied by external devices. These signals are
produced by a state-machine timing generator consisting of a 4-bit counter and two flip-flops. The
state machine synchronizes itself with RAS after
8~,95
/
Computer Graphics: Graphics display controller
the 8272Q has been initialized. Figure 4 shows thll
com(?lete'schematic for eachpla~e, of'the bit-map
,
..
interface.
'
The remainder of the hardware design interfaces
the graphics ·display processor, the processor
memory, and the other peripherals with the 80186
microprocessor. The task is simplified by the processor's on-bo&",d chip-selection logic and wait." state generatol7s~ Furthermore, because of the processor's highly integrated architecture, the size of
the overall hardware is quite small.
Joining proceslOr and controller
Copnecting the graphics display controller'to the
microprocessor is a simple task, as the processor's
Data, Read, and Write 'signals are completely compatible with those of the 82720. However, because
the controller has no chip-selection input, the Read
or Write signals must be qualified through external
hardware.
'
A number of chip-selection lines on the micro-
processor can be programmed to place peripherals ,
either in memory or ln the processor's I/O space.
Two gates are added to qualify the Read an4 Write
sigrials. The DMA channel on the 80186 uses a
second chip-select input as the Acknowledge signal,
anq data buffers are used to prevent bus contention
at the end of a processor read cYl;le (Fig. 5).
WithQut buffers, the display controller must remove its data from the multiplexed address and
data lines before the processor puts out the 'next
addres~.. At an 8-MHz clock ",ate, the processor
requires that peripherals and memory vacate the
bus in less, tha/1 85 ns; however, the stand.ard speed
of the controller is 100 ns. A faster version, the
82720-1, can be used, but it requires faster memory
chips. A more cost-effective solution is simply adding buffers, if board space permits.
Serial communications to both the host and the
optional tablet are handled by a multipro~ocol
serial controller (the 8274), which takes care of the
host's synchronous and the tablet's asynchronous
..: '!'he bll-mep'lnemory·lntert_ conlalnllhn..·llCldreel plenaa(one of which II lhown h_) 10 complele
the grilphiCI IYltam.. The RA,8 Ililnal for Ihe RAMIII'II.n.~eled by Ihe·llrephlcldl.P"y controller.
Computer Graphics: Graphics display controller
requirements. Interfacing is accomplished simply
by connecting the buffered data bus, the latched
lower-address lines, the Read !lnd Write signals,
and the chip-select. A final link brings the microprocessor's counter-timer, output into the multiprotocol seril!-l c;ontroller as a baud-rate clock. No
buffering of the TTL,supportcircuitry, is necessary.
Univers.1 chip inlert.ces keyboerd
80186 '
mlcroproceasor
82720
grophlcll dleplay
,contrQlIar
5. The interlace between the 82720 and the system
microprocessor is simple to implement because all 01 the
processor's signals are compatible with the controller. It is
necessary, however, to use external gates to qualify the RD
or wFi signals.
A universal peripheral interface chip (the UPI42) serves as the keyboard interface and is programmed to scan the keyboard and interrupt the
processor only on detection of a valid debounced
keystroke. Mass-storage subsystems are managed
by the 8272A floppy-disk controller. An external
phase-locked' loop circuit generates all of the timing
signals reequired to connect !I 51/4-in. drive to the
system. On the microprocessor side, a DMA channel
provides the link to the floppy-disk controller. Thus
6. Ac0!1'plete graphics control system is center,d around an 80188 microprocessor and the 82720 controller.
Local storage is provided by 32 kbytea 01 EPROM and 16 kbytes 01 RAM. The system comprises 85 chips and
is housed on a single 12-by-12-in. printed-circuit board.
8-97
the processor has a high-speed disk interface,
which loads it lightly.
.. .
To 'complete the graphics system illustrated in
Fig. 6, 32 kbytes of EPROM and 16 kbytes of RAM
support the microprocessor's program and display
lists. The two EPROMs (27128s)'come in 28-pin
packages, thereby saving board space~
.
Hooking up the RAM chips is almost as straightforward. Since the microprocessor is. a fuBy byteaddressable device,it can write bytes as well as
words to the RAM. The chip-select input for the low
(even) address RAM must be qualified with address
Ao at a logic zero, and the high (odd) address RAM
must be qualified by the processor's Byte High
Enable signal (BHE). The RAMs, designated 2186,
have built-in controllers.
.
Since dynamic RAMs latch addresses on the
leading edge of the chip-select signal, they must be
qualified with the processor's Address Latch' Enable signal to ensure that selection is made only
after the address is valid. Then, a RAM latches the
data to be written on the leading edge of the write
pulse. The mjcroprocessor's.write signal must be
delayed· by one-half of a clock cycle to guarantee
that data is valid at the correct time;
At this point, the design meets all of its performance goals. The system draws lines and circles
T-1408/5K/0383IHP RM
at about 120,000 bits/so That is approximately
82,000 . pixels for a display consisting of even
amounts. of the three primary colors, as well as
three secondary colors, (and white. The 500 vectors
of 25 pixels each can be drawn in about 0.15 s, six
times faster than the 1-s requirement. The worst
~ase-drawing all lines in white-can be accomplished in about onecthird of a second. These specifications are satisfied when the graphics display
controller is running from a 2,5-Ml:Iz clock. Drawing is performed only during retracing and the
82720 is programmed to use three memory cycles of
each horizontal retrace for memory refreshing.
All of the components fit on a board measuring
12 by 12 in., so that the desktop size requirements
are satisfied. The electronic components occupy
about 100 in. 2 of the low-cost, double-sided printedcircuit board. 0
Bibliography:
Bresenham, J.E., "Algorithm for Computer Control of a Digital
Plotter," IBM System Journal, 1965,4(1) pp. 25-30.
8-98
ARTICLE
REPRINT
·AR~298
Graphics Chip Makes
Low-Cost, High Resolution
Color Displays Possible'
by Mark Olson and Brad May
The making of displays that are
both high-resolution and low-cost is
the key to producing equipment for
both the automated office and the
engineering workstation. Through
the introduction of 16-bit IJoPs such
as Intel's iAPX 8088, 80186 and
80286, the processing power' has
been made available to perform
very sophisticated functions for the
user while making the human interface very simple.
That processing power can be
unnecessarily drained, however, if
the IJoP is Burdened with the entire
task of graphics display. Such a
burden can fill up a significant part
of the processor's 110 bandwidth,
slow down the refresh rate of the
display, and decrease the computational power of'the CPU.
mented in hardware at the device
level.
Such a chip is Intel's 82720
Graphics Display Controller (GDC).
It has features that give systems a
fast drawing speed while reducing
graphics display costs by 60% or
more. It achieves these. results by
taking over the drawing and refresh
functions from the CPU, by allowing the use of dynamic RAM's instead of static RAM's, and by reducing the overall parts count
needed to create a complete graphics system.
The implementation of the drawing task is a major feature of the
GDC. Other graphics chips perform only the 'display refresh function, leaving the more complicated
drawing function entirely to the
CPU. Since the CPU is doing every
pixel of the drawing function on
these systems, they also require fas-
ter bit map RAM than with the
GDC. The GDC, on the other
hand, is capable of handling the
drawing function itself, drawing
such objects as characters, slanted
characters, points, lines, arcs, rectangles, and slanted rectangles
based only upon lengths, slopes,
and arc centers supplied by the
CPU. The GDC's processing,
moreover, takes place concurrently
with the processing of the, CPU.
2048 X 2048 Resolution
With its 4 Megapixel addressability,
one GDC can handle a monochrome display with resolution as
high as 2048 x 2048, and multiple
GDC's can be linked to provide
even higher resolution, such as color displays at 2048 x 2048. The
chances are, however, that the
GDC's full power will not be used
in most applications. The typical
Intelligent
peripheral rcs
offload processing
tasks from the CPU.
The logical way to avoid such
limitations is to dedicate a specialized processor to the handling of
display function. It should be capable of accepting high-level commands to minimize the burden on
the CPu,·, as well as optimizing
the execution of such commands
thro).lgh. raster operations imple-
Operating System
D
From Independent
0
.From Intel
Softwar~ V~ndor
Mark Olson and Brad' May are
Product Marketing Engineers for
Peripheral Components Operation,
Intel Corp., Santa Clara, CA 95051.
Figure 1: General graphics commands are translated mto the VDI mterface level
and then into driver device commands.
Reprinted from DIGITAL DESIGN © April 1983, Morgan-Grampian Publishing Company, Boston, MA 02215
Digital Design _ April 1983
8-99
.;'
82120 BIT MAP INTERFACE
I
in
I
j~
ADO·
AD'S
,
82720
'4 INTO 7
MUX
2 " 74L~157
I
7,
·
I
GREEN ""lEMORY
aWE MEMORY
BLUE
RED MEMORY
'r-LJ
AD-A6
,~'j
o---v
f
-RAS
LS
32
2XCLK
,4..-.u
VIDEO
OUT
GREEN
RED
...
""
-.
-,
,
CAS
TIMING
LOGIC
-DBIN
DOT CLOCK
~SHIFT BANK
WRITE'
l
-
I
I'
'I
DO·D'6
ALE
SYNC
H V
"
~
~
f
,
YO
LS
,39
-
BLANK
DBIN
1<:)10
SELECT
~Y'
'"' Y2
(5 Y3
-
""
SYNC
-BLANK
~
,-
SYNC
LS
32
""
Figure 2: The memory is broken up into three planes. with each plane feeding one of the primary color guns of the CRT:
.
product considered high resolution
for office automation applications
is a 512 x 512 pixel monochrome
or color display.
These latter restrictions are not
imposed by the GDC. but rather
have more to do with' the cost of
display monitors. the' amount of
RAM memory needed to support
such displays. and the adequacy of
such displays for most applications.
It is possible to build "super graphics" boards with a GDC. such as
the lK by lK pixel by 8 color plane
graphics display designed by Phoenix Computer Gra~hics (Lafayette,
LA). Such a display is capable of
rendering 256 different colors on a
high resolution screen.
Even higher performance can be
achieved through the use of multiple GDC's to support multiple display windows, increased drawing
speed, or increased bits per pixel.
For multiple display windows, each
GDC can be used to control one
window of the display. For inO,I911al Desl9n - April 1983
creased drawing speed, multiple
GDC's can be operated in parallel.
For increased bits/pixel, each GDC
can contribute a portion of the,
number of bits necessary for a
pixel.
Although the GDC is intended
primarily for raster-scan graphics, it
can also be used as a' character display controller. It is capable of supporting up to four screens of data
containing 25 rows by 80 columns,
or one screen containing up to 100
rows by 256 characters.
Office Automation Display
, High performance applications can
stretch the usage of the GDC froQl
low-end to high-end engineering
displays, but research has shown
that for office automation proqucts, a 512 x 512 pixel display is
quite acceptable, and that color is
often a requirement. These requirements mes~ with a :major factor ,in
display-the co~t of the CRT. In
OEM quantities, for example, one
could expect to find a 512 x 512
monochrome display for under
$100, a 256 x 256 color display
(TV quality) for about $150, a 512
x 512 color CRT in the $300 range,
and a lK x lK color display in the
$800-$1000 category.
To give an example of the type of
display that can be built for new office products using the 'GDC, consider a 512 x 512 pixel by3 color
plane combination CPU and graphics display on a single q" by ,12':
boarq. Such a display is capable of
ge~erating 8 colors.
"
'
The list of parts (Table'Z) comes
to about $175 for 85 Ie's taking up'
104 square inches of boa~d space.
Even, t\:lat parts count could be redu~ed by replacing the 48 16K
DRAMs with 12 64K DRAMs-if
a 4K x 16 bit DRAM were available. A v~ry importa~ note about
the Pllrts list is thjlt the design is
implemented with inexpensive ~118
dynamic RAMs. The design does
not require the faster, more expensive, and less dense static RAMs.
The parts .count is low enough so
that the processor and graphics
controller can be placed together in
a single 12" by 12" board. This is
important because small overall
size and footpad are selling points
for desktop workstations. System
speed is also enhanced when the
graphics controller and CPU are on
the same board, because their communication need not take up bus,
inter-board bandwidth or experience any additional delays.
PipeliI,1ing 'ftansformations
More important than putting the
graphics display on the same board
as the CPU is the level of communication between the CPU and
graphics controller. If the burden of
transformation processing is left
entirely to the CPU while the
graphics chip is used only as a CRT
controller, then the CPU must com,municate one bit per pixel to upi date a display. With the GDC, the
CPU input takes higher level forms
such as the slope and length of a
line, the length and center point of
an arc, or the key coordinates of a
rectangle. Since the average line on
a screen is about 25 pixels, that
means that 25 times fewer CPU bus
cycles are required to draw a
graphical object with the GDC.
These CPU cycles (an average of
50 ,....S each to calculate the graphical object and communicate it to
the GDC), are the determining factor in drawing rate.
Viewed from a larger perspective, there are four tasks that must
be performed by a CPU-graphics
chip combination:
(1.) The CPU must calculate the
higher-level graphics operations.
This is done by the CPU and it involves the processing of macro-operations such as the CORE, GKS,
PMIG or other graphics protocols.
These general graphics commands
are translated into an intermediate
level, the VDI interface level (Figure 1) and then into device driver
commands by software in the CPU.
(2.) Then, these lower-level
graphical objects such as the key
parameters for lines, arcs, characters, and rect~ngles, must be trans-
VLSI Takes Aim At Text ProcessiIig
The concept of co-processing is not a new one. Intended
as a way of offloading computationally intensive tasks from
a host CPU, 'it has been around at Intel since the introduction of the 8087 numerics processor and the 8089 110 machine, A more recently ,developed product, the 82720
Graphics Display Contrcller is designed to bolster system
performance' by offloading graphics control chores from
the CPU. The chip accepts high level commands from the
CPU and, using its own drawing processor, accesses the
required positions in' the bit-map and handles the processing and display control functions,
Building on the success of these parts come two new
co-processors designed to partition system intelligence
even further. The 82586 is a communications coprocessor designed .to bridge the characteristics of CPU
and network data rates. Its FIFO buffer and DMA facilities
make it possible for a CPU to operate at the full Ethernet
10 Mbits/s ,transfer rate even in the face of continuous
.
bursts of network data traffic.
Intel's most recent introduction is the 82730 text co-processor. Printers'and other hard copy peripherals have supported additional text processing features such as proportional spacing and Simultaneous superscript and subscript
for some time. Implementing these features on the display
screen has traditionally been a costly procedure. Thus, it is
typically not done and screen displays often are not identi, cal to their hard-copy printouts. Aimed to solve this designers headache, the 82730 has its own DMA capability and
communicates asynchronously with the CPU via shared
memory messages: It supports the generation of high
quality text displays through features like proportional
spacing, simultaneous superscript/subscript, dynamically
reloadable fonts and user programmable field and character attributes. In .addition, when coupled with the 82720
Graphics Display Controller (Figure 1) the 82730 provides
flexibl,e, mixing of text and graphics simu ltaneously on the
same display.
.,--Wilson
8-101
,--------,I
8C~~6
I
I
I
Coprocessor
L _______
Data
Communications
Block
~
,--------
I
I
DIsplay
, Processmg
I
I '---.-_---j
Block
82730
Text
I
L
_______ _
Coprocessor
Data
Processing
Block
'- _ _ _ _ _ _ _ ---J
Figure J: Offloading system tasks is simplified by new V LSI
devices.
'Digital Desig" _ April 1983
DRAWING SPEED '
-so .,.sec
Sel up Draw 1
-50.,.sec
Sel up Draw 2
,
" S e l up Draw 3
<..................................................... ) ( ......................................................................................................___ .......... )c ...................................................... )
80186
(25 pixels)
Sel up draw '4
,
( ................. __ .... - .............. - ......... )
(100 pixels)
,
Drawl Drawl
c ............... >( .................. >
BI12
Bil3
GDC (2.5MHz)
Calculate
Nax1 bit
•••••• ~ ••••••4O
GDC
RIMIW
Drawl
Draw2
BI125
Bill
c .... _____.... )c ................. )
Draw2
(------....
)
Bil2
fLseC·············:················,
Drl
Drl
Bill
BI12
Drt
Drl
Dr2
BI124
Bi125
Bill
cOo .......... __ .)c ........... _.... >
012
cOo ....... __ .... )
Blll00
.············40 fLsec········..·····················,
-50 fLsec
Sel up draw 1
other
CPU
Calculate
R/MIW Bill
Calc
<.. ---.......... --_ ........ -............,. ...... >(--_ ...... _............. --> ( ....... -................... _-) ( ... ---_.. _---_..:_--->
,
Bill
R/M/W
-so fLsec
Sel up draw 2
BII25
.·······.,·······.··375-500
fLsec···············································,
Table 1: The 80186 and the GDC work together to accomplish the t;lrawmg /un(:tioll,
,
formed into changes in the actual
bits. This function is performed in
h~rdware in the GDC concurrently
with any level one processing done
by the CPU. Other graphics controllers leave this 'task to the CPU
to execute in software. The contrast is that, in such systems, the
CPU must resolve the graphical object down to every point on a line,
while with the GDC it need only
designate the endpoints.
(3.) With the actual bits for the
bit map calculated, they must be
placed in the bit map memory. This
involves a read-modify-write operation that requires three' CPU cycles using other methods. With the
GDC these operations are not the
responsibility of the' CPU. The
GDC pipelines its execution so that
it is calculating the next' bit to
change while it is executing the
read-modify-write cycles.
(4.) Finally, the bit map memory
must be dumped into the CRT. 'This
is the refresh function performed
by other graphics chips as well as
the GOC.
The summation is' that other systems require the CPU to process
steps one to three serially, leaving
only step four for the graphics controller. Systems with the GOC require the'CPUto process onry step
one, with the ,GOC ,conc~rr~ntly
Digital Design ,. April 1983 .
processing steps two through four.
upon the overall' system efficiency.
The GDC has another advantage in
If they must be executed by a fLP,
the instruction fetching process
that during the transformation process in' step three; the GDC exslows down the calculations' to a
drawing rate of 15-20 fLS per pixel.
eCl1tes t~e algorithms in liardwilre
With a hardware implementation 'of
while a CPU must exec;ute th~ ~l
these algorithms in' the' GDC, the
gorithms in software. The algo,calculations' can be speeded up to·
rithms are exactly the same in both
achi<;ve a di-awing rate of 16(JO ns
cases, They are the Bresenam algo.
rithms from IBM, in which the next
(2.5 M,Hz version) or 800 ns (5
pixel to be drawn becomes a binary
MHz version) per pixel.
decision. between two pixels.
Methods Of Refresh
The execution of these algoIn the fourth step-, the dumping of
rithms is a crucial drawing time facbit map memory intCJ the CRT,
tor, because they are invoked many
there are some differences between
times for each updated screen.
graphiCs controller chips. Motoro,Consider that, in the inner loop of
Bresenam's "line drawing algohi's MC6845 CRT controller, for ex-'
ample, uses., a split,-cYcliF refresh
rithm," there are two or threl! addi-,
method in which each refresh .cycle,
tions, two comparisons or tests,
and the maskin~ of the proper val- . is alt!!rnated with a drawing cycle
in, which the fLP updates, the bit
ue into the word for each pixel.
The algorithms for drawing circles , . map. This gives the MC6845 'a 50% ,I
or filling areas are even more com" ' . draw,ing ,bandwidth. '
, Witli the GDC there are two,
plex. In the inner loop of a fill algo'rithm, the old word inust be read'
drawing modl!s. The first is a "draw:
anytiim;" mode whi'ch ·replaces.
from the bit map, then tested'to see
if all, some, or, none of tbe pilfel~.
CRT n:fresh cycJe~ with drawi~g
are within the area to be filled.
cycll;s. T~is is the fastes~ mode", but
, Next, it tests whether some or,all of
it dOe~ result, in on-screen disr!JPthe pixels must- be modified. Finaltions. The second 'mode, which
ly, the word must be returned to'the
does not disrupt the on-screen disbit map.
" play, ,draws only during the vertical.
and· horizontal retracing' periods.
These, algorithms are heavily'
. This gives the GDC about:a 25%
used and the 'speed with~hicli they
can be executed has a 'direct effect
8-102
(" dphl(
S (
IIII'
1
1
2
1
1
80186
62720
74LS157
74LS139
74LS161
74LS11
1 74LSOO
SUMMARY:
""
,
1
1
9
8
3
2
1'
74LS04
74LS73
74LS244
74LS166
74LS32
8286
8 MHz Crys1~1
1
2'
2
1
1
3
1
20 MHz 910ck
27128
2186
8274
8042
Connectors
12 x 12 2 Layer PC
4 VLSI Controllers
80186
82720
8274
8042
Processor
Graphics
Serial Link
Keyboard
4 VLSI Memory
27128
2186
EPROM
IRAM
4816K DRAMs
2118
DRAM
2s
Buffers/Glue
MSIISSI
,TOTAL: 85 IC'S ....... 104 Sq, Inches
Parts Cost ....... About $175
Table 2: Parts list for 512 x512 x 4 Color DIsplay,
16 MHz
To Dot Clock
(25MHz)
-"~D~
, X.
• X,
2XCCLK
WR
r
RD
CS1
A1'
-v
1
80186
WR
ADO·7
RD
I I
Data
Buffer
[DEN
DT/Ri
r
1
PCS1
AO
r-1
J
DRao
82720
DBO-7
I
DACK
DREa
,
• Asynchronous Processors
• DMA Access to Brt Map
• 4 Buffers, 1 Glue IC
1
ber ,9f pixels is not a power of two,
it will be necessary to round up to
the next power of two and waste
the extra bits.
'
The pixel arrang~ment Which
best meets this requirement is one
with, a 432 x 576 pixel format. It
also meets the requirement that the
number of pixels horizontally be an
even number of 16-bit words. With
three color bits per piJlel (red,
blue, and green), the total display
memory is then about 500 x 500 x 3,
oi- 750k bits.
' ,
It makes the most sense to break
the memo,ry up into three planes,
with each plane feeding one of the
primary color guns of the CRT
(Figure 2), This leads to a memory
arrangement of 16K x 16 x J,
using 16K' dynamic RAMs with a
lK x 16 architecture. When drawing graphics figures, the memory
can be treated as one large plane,
split into the three primary colors.
Drawing in low-order memory
could represent red, middle-order
could be used foi green, and high,
order for blue,
One advantage of' this 3D memory is that drawing with' a primary
color requires setting only one bit
per pixel. Drawing with a secondary color such as cyan, yellow, or
magenta would take two ODC cycles,' and creating, white frq~ all
three colors would take three ODC
cycles. If this were an issue', additional hardware could be used to
draw more than one plane at a
time. As the results will show, however, the drawing speed requirements can be exceeded without any'
added hardware.
Figure 3: The two chIp selects are OR'd together to qualify the RIW slgna/s.
Calculate The Drawing Rate
drawing bandwidth, At first glance
that gives the ODC a disadvantage
in drawing rate, but the fact is,
with its pipelining and hardware
execution of transformations, the
ODC makes much more efficient
use of its bandwidth. The critical
timing factor is the amount of CPU
participation in the drawing process, not the refresh bandwidth of
the graphics controller, Another
tradeoff is that, with its split-cycle
architecture, the MC6845 requires
RAM memory that is twice as fast
a~ that reQuired by the ODC in the
same application.
Inexpensive RAM Is Fast
Enough
Applying this perspective, one can
begin to build the display with parts
listed in Table 2, First one notes
that 'a square display, as indicated
by the 512 x 512 pixel initial specification, is not pleasing to the eye. It
'is much more appealing to have an
aspect ratio of about 4:3, in which
the number of pixels horizontally is
4/3 the number verticallJli If the resolution is such that the tot~1 rum8-100
To see if the proposed design is
practical, one should first calculate
the drawing rate to see what' the
, \lser interface will be like. Then
one should check the refresh rate'
to make sure the design is uninterrupted and without flicker.
The proof of the assumption that
CPU participation ·is the dominat- '
ing factor lies in the 50 IJ.S average :
time that it takes the CPU to calcu- '
late a graphical object and communicate its key' parameters' to the'
ODC. Assume that. the 'graphical
object is an average line containing
25 pb~els, and that there are about
500 vectors on the average screen
display.
The GDC's normal' clock rate is
2.5 MHz, giving it a 400 ns period
(the maximum clock rate is 5 MHz,
with a 200 ns period.) It takes four
GDCcycles to execl,lte a readmodify-~rite on a bit (because, two
read cycles are required), so that
the GDC's normal drawing rate is
one pixel per 1600 ns. To draw the
25 pixels 'involved in the average
line, then, would take 25 x 1600 ns,
or 40 I!,s. Since this operation is
done concurrently with CPU processing, the GDC will be waiting
for the ':Iext, graphical object by the
time the CPU is ready.
If the screen were filled with
nothing but 25-pixel vectors, then
the drawing rllte would be determined by the 50 I!,S average CPU
calculation and transfer cycle, averaging about 2 I!,S per pixel. If all
the vectors were white (worst
case), then it would take 1.5 secs of
drawing time to update the white
screen. Since, in the tindisturbedscreen mode" drawing is only done
during the 25% ofthe time that the'
. screen is undergoing I;!orizontal or
'vertical blanking, ,this would mean
6 secs between updates,
In reality, however, the screen
will not be filled with vectors. It
will have an average of 500 vectors,
'and the color distribution could be
presumed to be evenly distributed
as one-third primary colors" onethird secondary colors, and onethird white. The 500 vectors will require the drawing' of 12.5K pixels
in monochrome, or 25K pixels with
di~tributed colors, At a drawing
rate of 2 I!,S per pixel, this takes 50
ms to draw, Drawing only during
blanking, the screen would be updated in 200 ms.
Under these conditions, it would
not help to use the maximum clock
rate GDC (5 MHz), but if in some'
applications the average vector
length is 100 pixels, then the CPU
calculation-and-bus cycle (50 I!,s)
would remain the same and the
GDC's drawing cycle (1600 ns x
100 = 160 foLS) would become a
limiting factor. Using the 5 MHz
GDC would cut that drawing time
qown to 800 lls/pixel, or 80 foLs/vector. The 500 vector average screen,
would then contain lOOK pixels
with distributed colors' and could
be drawn in 80 ms. Multiplying by
four b~cause the drawing is done
during blanking (25% of the time),
that is 320 ms. That is a screen u~
date in less than one-third second
for a "busy" screen.
Calculate The Refresh Rate
These calculations are of little importance if the display flickers due
to lack of refresh. This exercise is
actually a demonstration of how
the basic GDC clock rate was derived. Assume a non-interlaced display that must be refreshed 60
times per second. That gives a
screen refresh rate of 16.67 ms, but
on typical CRT some 4.27 ms Of
that is blanked, leaving 12.4 ms of
active display time. The dot sweep
period is the 12.4 ms divided by the
number of pixels (432 x 576 =
248.8K), or 49.8 ns. The inverse
gives a 20.07 MHz dot clock.
Since the GDC dumps 16 bits
from the bit map memory into the
a
, DRQD
DAEQ
pcso
DACK
OR01
TMR OUT 01
WR
RD
ALE I - - r -
r-
,--
ADR
-
"!f<
RD
82720
,.--- PCS2
l IJ
GDC
~
r - - ARDY
VIDEO
REFRESH
LOGIC
80186,
eP
-
r - LCS
r - VCS
MONITOR
ADDRESS BUS
LATCH
PCS3
(
11
r-AD
BUS'
DATA
DEN I - - BUFFER
DATA BUS
DTR~,,--;-
I
J£l
'27128
IQl
-
LOW 8K
8 -
HIGH 8K
8. -
CE
TCE
1'--
~M
r-
'EdJM
27128
2186
TcsT
8279
KEY-
2186
LOW
8K
8
WE
080-7
r-
~
HIGH
8K
8
READY}CS
r-
RXC
TXC
BOARD
CON,
}rLER
READY CS
MEMORY BUS
.
r-
'8274
SERIAL
10
ROVB TXORQA
ri
U
BiT MAP MEMORY
CS
16K· 16
3 PLANES
,
-
'.
Fig ure
4: Comp Ie'led graphies sy stem uses the 8()J86 and 82720 GDe
Digital DeSign - April 1983
DMA
'TO
MONITOR
KEYBOARD
8-104
SERIAL PORT
TO HOST
TO
OPTIONAL
TABLET
"
,
'\.
0,
0,
DINO-DIN15
0.
0"
I
~.
I
.'
....
A.-A.
2118
D,N
A,·A.
'r:::
VIDEO
2118
liAs
~
liAs
CAS
..
CAs
WRiTE
BsEL
DBIN
~
::J
2118
I--
WE
DOUT
32
DOT ClK
2118
t
,
I
r--
-
I--
-
IN 15
t--
2X
74166
2X74LS244
0,
0,
•
IN,
IN,
IN,
,CLOCK
..
J
•••
•
SoUTPUT
SINPU'r
Sl
•
0,
0"
900173
SH1FT LOAD
Figure 5: Since the 186 is a fully byte addressable machine. it i,1 possible
16-bit shift register' during each
read, and since the shift register
then feeds these bits out serially to
the CRT, it makes sense that the
GDC's read period should be 16
times the dot sweep period. That
gives a GDC read period of about
800 ns. With each GDC read taking
two cycles, the' basic GDC clock
period is then,4oo ps, or 2.5 MHz.
This gives a rock-solid display, and
one would only want to go to the 5
MHz GDC to improve drawing
rate.
For those who want to examine
the blanking intervals to see if the
ClU is indeed '<'typical," the blanking can be further broken dbwn.
The vertical blanking interval is
1.25 ms, leaving 15.42 ms to scan
the 432 lines on the active' portion
ofthe display. Dividing 15.42 ms by
432 lines gives a 35.7 f.LS period per
line, or a horizontal sweep rate of
28 KHz. Time is also needed for
horizontal retrace, in this case, 7
f.Ls of horizontal blanking per line.
This lea~es 28.7 f.Ls to scan the 576
~
to
write bytes as well as words into the RAMs;
pixels on each line, resulting in the
dot sweep period of 49.8 ns. Using
a 20 MHz CRT helps keep the costs
down, but the GDC can use CRT
displays as fast as 80 MHz when
higher resolution is required.
Mixed Mode
While it is possible to generate
8 x 8 characters and slanted characters in the graphics mode. the GDC
also offCfrs a mixed mode memory
organization to display both characters and graphics drawn from separate windows in the display memory. The advantage of this mode is
that it allows characters to be manipulated as 8-bit entities instead of
the 64 bits that each would require
in graphics mode. Of necessity, the
graphics window dis'J>lay memory is
reduced in this mode (64K 16-bit
words instead of 256K)" ,but even
the reduced maximum graphics
memory is still Ii megapixel and
quite sufficient for both office automation and engineering display
purposes.
In the character window; the
GDC operates as it does in the
pure character mode, with the exception that the line counter must
be implemented externally. In addition to the two windows used for
graphics and characters in the
mixed ,mode, two other windows
can be supported. These can be
designated as either character or
graphics windows by a selection' on
the A17 line.
Panning, Zooming, Light Pen
As special features, the ~DC allows both panning and zooming in
either graphics, character, or mixed
modes. --<---<-.,.---
A-17
DBIN
.
'
HSYNC
"IEXT SYNC
BLANK
iiAS(ALE)
DRa
DACK
lffi
3
.
AI).1S
AI).14
AD·13
,
AI).12
•
9
A().,
COMMAND
PRO£.~"SO~
AD~
A()'7
CONTROL ROM
1Ux1.
, ..,0-13
PARAMETER
RAM
D...
Ao.ola12
,
+5'1
0-;--
GND
2xwct.K
0---
i.
A,D-6
27
AO·S
""
"
AI>4
Ao.,
AD·2
De·7
"E.
<>---- ,
Figure 2. Pin Configuration
Figure 1. Block Diagram
Intel Corporation Assumed No Responsibility for the Use of Any Clrcurtry Other Th'an CircUitry Embodied in an Intel Product No pther CircUit Patent licenses are ,Implied Information
contamed h~rem supersedes previously pubfished speCifications on these devices from Intel
'
,
©INTEL CORPORATION 1983
&-106
ORDER NUMBER:
;:~5~~~:
82720
Table 1. Pin Description
Symbol
2XWCLK
Pin No.
Type
1
I
Name and Description
Clock Input
DBIN
2
HSYNC
3
0
0
VlEXT
SYNC
4
I/O
Vertical Sync: Output used to initiate the vertical retrace of the CRT display. In slave
mode, this pin is an input used to synchronize the GDC with the master raster timing
device.
BLANK
5
6
0
0
Blank: Output used to suppress the video signal.
RAS (ALE)
DRO
7
0
DMA Request: Output used to request a DMA transfer from a DMA controller (8237) or
I/O processor (8089).
mR
8
I
DMA Acknowledge: Input used to acknowledge a DMA transfer from a DMA controller
or I/O processor.
Display Bus Input: Read strobe output used to read display memory data into the GDC.
Horizontal Sync: Output used to initiate the horizontal retrace of the CRT display.
Row Address Strobe (Address Latch Enable): Output used to start the control timing
chain when used with dynamic RAMs. When used with static RAMs, this signal is used
to demultiplex. the display 'address/data bus.
RD
9
I
Read: Input used to strobe GDC .Data into the microprocessor.
y;:m
10
I
Write: Input used to strobe microprocessor data into the GDC.
M)
11
I
Register Address: 'Input used to select between commands and data read or written.
DBO
12
I/O
Bidirectional Microprocessor Data Bus Line: Input enabled by WR. Output enabled
by RD.
DB1
DB2
DB3
DB4
DB5
DB6
DB7
13
14
15
16
17
18
19
GND
20
Vee
40
Al?
39
0
Graphics Mode: Display Address Bit 17 Output
Character Mode: Cursor and Line Counter Bit 4 Output
Mixed Mode: Cursor and Image Mode Flag
A16,
38
0
Graphics Mode: Display Address Bit 16 Output
Character Mode: Line Counter Bit 3 Output
Mixed Mode: Attribute Blink and Line Counter Reset
AD 15
AD14
AD 13
AD12
ADll
AD 10
AD g
ADa
AD?
AD6
AD5
AD4
AD3
AD2
ADl
ADo
37
36
35
I/O
Graphics Mode: Display Address/Data Bits 13-15
Character Mode:' Line Counter Bits 0-2 Output
Mixed Mode: Display Address/Data Bits 13-15
34
33
32
31
30
29
28
27
26
25
24
23
22
I/O
Display Address/Data Bits 0-12
LPEN
21
I
..
Ground.
:f 5V Power Supply
'.
Light Pen Detect Input
8-107
210655-002
82720
FUNCTIONAL DESCRIPTION (Continued)
Microprocessor Bus Interface
Control of the GDC by the system microprocessor is
achieved through an 8-bit bidirectional interface.
The status register is readable at anytime. Access to
the FIFO buffer is coordinated through flags in the
status register.
Command Processor
The contents of the FIFO are interpreted 'by the command processor. The command bytes are decoded, and
the succeeding parameters are, distributed to their
proper destinations within the GDC. The bus interface
has priority over the command processor when both
access the FIFO simultaneously.
Zoom and Pan Controller
Based on the programmable zoom display factor and
the display area parameters in the parameter RAM,
the zoom and pan controlle'r determines when to
advance to the next memory address for display
refresh and when to go on to the next display area. A
horizontal zoom is produced by slowing down the
display refresh rate while maintaining the video sync
rates. Vertical zoom is accomplished by repeatedly
accessing each line a number o,f times equal to the
horizontal repeat. Once the line count for a display
. area is eXhausted, the controller accesses the starting address and line count of the next display area
from the parameter RAM. The system microprocessor, by modifying a display area starting address,
allows par.ming in any direction, independent of the
other display areas.
DMA Control
Drawing Processor
The DMA Control circuitry in the GDC coordinates data
transfers when using an external DMA controller. The
DMA Request and Acknowledge handshake lines interface with an 8257 or 8237 DMA controller or 8089 110
processor, so that display data can be moved between
the microprocessor memory and the display memory.
The drawing processor contains the logic necessary
to calculate the addresses and positions of the pixels
of the various graphics figures. Given a starting point
and the appropriate drawing parameters, the drawing processor needs no further assistance to complete the figure drawing.
Parameter RAM
Display Memory Co~troller
The 16-byte RAM stores parameters that are used
repetitively during the display and drawing processes.
In character mode, the RAM holds the partitioned display area parameters. In graphics mode, the RAM also
holds the drawing pattern and graphics character.
The display memory controller's tasks are numerous.
Its primary purpose is to multiplex the address and
data information in and out of the display memory. It
also contains the 16-bit logic units used to modify the
display memory contents during RMW cycles, the
character mode line counter, and the refresh counter
for dynamic RAMs. The memory controller apportions the video field time between the various types
of cycles.
Video Sync Generator
Based on the clock input, the sync logic generates
the raster timing signals for almost any interlaced,
non-interlaced, or "repeat field" interlaced video format. The generator is programmed during the idle
period following a reset. In video sync slave' mode, it
coordinates timing between the GDC and another
video source.
Memory Timing Generator '
The memory timing circuitry provides two memory
cycle types: a two-clock period refresh cycle and the
read-modify-write (RMW) cycle which takes four
clock periods. The memory control signals needed to
drive the display memory devices are easily
generated from the GDC's RAS(AlE) and DBIN
outputs.
Light Pen Debouncer
Only if two rising edges on the light pen-input occur
at the same point during successive video fields are
the pulses accepted as a valid light pen detection. A
status bit indicates to the system microprocessor
that the light pen register contains a valid address.
System Operation
The GDC is designed to work with Intel microproces'sors to implement high-performance computer
graphics systems. System efficiency is maximized
through partitioning and a pipelined architecture. At
the lowest level, the GDC generates the basic video
8-108
210655-002
inter
82720
many cost/performance tradeoffs for both display and
drawing are realizable.
raster timing, including sync and blanking signals.
Partitioned areas on the screen and zooming are
also accomplished at this level. At the next level,
video display memory is modified during the figure
drawing ope'rations and data moves. Third, display
memory address are calculated pixel by pixel as
drawing progresses. Outside the GDC at the next
level, preliminary calculations are done to prepare
drawing parameters. At the fifth level, the picture
must be represented as a tist of graphics figures
drawable' by the GDC. Fina"y, this representation
must be manipulated, stored and communicated.
The GDC takes care of the high-speed and repetitive
tasks required to implement graphics systems.
The video memory can be partitioned into 4 banks,
each 1024 x 1024 bits. By selecting a" 4 memory
banks during display, 4 bits/pixel can be provided by
a single 82720. Each bank of video memory contributes 1 bit to each pixel. This configuration can
support color monitors, again with a maximum dot shift
rate of 44 or 88 MHz.
Higher performance may be achieved by using multiple 82720s. Mu,ltiple 82720s can be used to support
mutliple display windows, increased drawing speed,
or increased bits per pixel. For display windows,
each 82720 controls one window of the display. For
increased drawing speed, multipl.e 82720s are
operated in para"el. For'increased bits/pixel, each
82720 contributes a portion of the number of bits
necessary for a pixel.
GENERAL OVERVIEW
In order to minimize system bus loading, the 82720 uses
a private video memory for storage of the video image.
Up to 512K bytes of video memory can be directly supported. For example, this is sufficient capacity to store
a 2048' x 2048 pixel x 1 bit image. Images can be
generated on the screen by:
"
CHARACTER DISPLAY CONFIGURATION
Although the 82720 is intended primarily for rasterscan graphics, it can be used as a character display
controller. The 82720 can support up to 8K by 13 bits
of private video memory in this configuration (1 character = 13 bits). This is sufficient memory to store 4
screens of data containing 25rows by 80 characters.
The 82720 can display up to 256 characters per row.
Smooth vertical scrolling of each of 4 independent
display partitions is also supported.
-Drawing Commands
-Program-Controlled Transfers
-DMA Transfers from System Memory
The 82720 can be configured to support a wide variety of graphics applications. It can support:
"":Hlgh Dot Rates
-Color Planes
-Hor.izontal Split Screen
-Character-oriented Displays
-Multiplexed Graphic and Character Display
GRAPHIC DISPLAY CONFIGURATIONS
The 82720 provides the flexibility to handle a wide
variety of graphic applications. This flexibility results
from having its own private video memory for storage
of the graphics image. The organization of this
memory determines the performance, the number of
bUs/pixel and the size of the display. Several different
video memory organizations are examined in the following paragraphs.
In the simplest 82720 system, the memory can store up·
to a 2048 x 2048 x 1 bit image. It can display a 1024
x 1024 x 1 bit section of the image at a maximum dot
rate of 44 MHz, or 88 MHz in wide mode. In this configuration, only 1 bit/pixel is used.
MIXED DISPLAY CONFIGURATION
The GDC can support a mixed display system for
both graphic and character information. This capability allows the display screen to be partitioned between graphic and character data. It is possible to
switch between one graphic display window and one
character display window with raster line resolution.
A maximum of 256K bytes of video memory is supported in this mode: half is for graphic data, half is for
character data. In graphic mode, a OlJe megapixel
image can be stored and displayed. In character mode,
64K, 16-bit characters can be stored.
DETAILED OPERATIONAL DESCRIPTIO.N
The, GDC can be used in one 01 three basic modes
-Graphics Mode, Character Mode and Mixed Mode.
This section of the data sheet describes the following
.
for each mode: .
1.
2.
3.
4.
By partitioning the memory into multiple banks, color,
gray scale and higher bandwidth displays can be supported. By adding various amounts of'external logic,
8-109
Memory organization
Display timing
Special Display functions
Drawing and'writing
210655-002
inter
82720
~unctlons:.
Graphics Mode Memory Organization
Graphics Mode Special Display
The Display Memory is organized into 16-bit words
(32-bit words in wide mode). Since the display memory
can be larger than the CRT display itself, two width
parameters must be specified: display memory width
and display width. The Display width (in words) is
selected by a parameter of the Reset command. The
Display memory width (in words) is selected by a parameter of the Pitch command. The height of the Display
memory can be larger than the display itself. The height
of the Display is selected by a parameter of the Reset
command. The GDC can directly address up to 4Mbits
(O.SMbytes) of display RAM in graphics mode.
WINDOWING
The GDG's Graphics Mode Display car.! be divided
into two windows on the screen, upper and lower.
The windows are defined by parameters written into
the GDC's parameter RAM. Each window is specified
by a starting address and a window length in lines. If
the second window is not used, the first window
parameters should be specified to be the same as the
active display length.
Graphics Mode Display Timing
All raster blanking and display timings of the GDC arl:1
a function of the input clock frequency. Sixteen or
32 bits of data are read from the RAM and loaded into
a shift register in each two clock period display cycle.
The Address and Data busses of the GDC are mUltiplexed. In the fir'st part of the cycle, the address of the
word to be read is latched into an external demultiplexer.
In the second part of the cycle the data is read from
the RAM and loaded into the shift register. Since all 16
(32) bits of data are to be displayed, the dot clock is
8 x (16 x) the GDC clock or 16 x (32 x) the Read cycle
rate.
ZOOMING
A parameter of the GDC's zoom command allows
zooming by effectively increasing the size 6f the dots
on the screen. This is accomplished vertically by
repeating the same display line. The number of times
it is repeated is determined by the display zoom factor parameter. Horizontally, zoom is accomplished by
extending each display word cycle and displaying
fewer words per line, according to the zoom factor. It
is the responsibility of the microprocessor controlling the GDC to provide the shift register clock circuitry with the zoom factor required to slow down the
shift registers to the appropriate speed. The frequency of the 2XWCLK should not be changed. The
zoom factor must be set to a known state upon
initialization.
PANNING
Panning is accomplished by changing the starting
address of the display window. In this way, panning is
possible in any direction, vertically on a lin~ by line
basis and horizontally on a word by word basis.
Parameters of the Reset or Sync command determine
the horizontal and vertical front porch, sync pulse, and
back porch timings. Horizontal parameters are specified
as multiples of the display cycle time, and vertical parameters as a multiple of the line time.
Graphics Mode Drawing and Writing
Another Reset command parameter selects interlaced
or non-interlaced mode. A bit in the parameter RAM can
define Wide Display Mode. In this mode, while data is
being sent to the screen, the display address counter
is incremented by two rather than one. This allows the
display memory to be configured to deliver 32 bits from
each display read ·cycle.
The GDC can draw solid or patterned lines, arcs, Circles,
rectangles, slanted rectangles, characters, slanted characters, filled rectangles. Direct access to the bit map
is also provided via the DMA Commands and the Read
or Write data commands.
MEMORY MODIFICATION
All drawing and writing functions take place at the
location in the display RAM specified by the cursor.
The cursor is not displayed in Graphics Mode. The
cursor location is modified by the execution of dra.wing, reading or writing commands. The cursor will
move to the bit following the last bit accessed.
The V Sync command specifies whether the V Sync
. Pin is an input or an output. If the V Sync Pin is an
output, the GDC generates the raster timing for the
display and other CRT controllers can be synchronized to it. If the V Sync pin is an input, the GDC can
be synchronized to any external verticalSync signal.
8-110
210655-002
82720
READING AND DRAWING COMMANDS
,After the modification mode has been set and tile
parameter RAM has been loaded, the final drawing
parameters are loaded via the figure specify (FIGS)
command. The first parameter specifies the dlrec·
tion in which drawing will occur and the figure type to
be drawn. Thill parameter Is followed by one to five
more parameters depending on the type of character
to be drawn.
Each bit is draw,n by executing a Read-Modify-Write
cycle on the display RAM. These RlMfW cycles normally
require four 2XWCLK cycles to execute. If the display
zoom factor is greater than two, each R/MIW ciCle will
be extended to the width of a display cycle. Write Data
(WDAT), Read Data (RDAT), DMA write (DMAW) and
DMA read (DMAR) commands can be used to exam·
Ine or modify one to 16 bits in each word during each
RlM/W cycle. All other graphics drawing commands
modify one bit per RlM/W cycle.
The direction parameter specifies one of eight octants in which the drawing or reading will occur. The
effect of drawing direction on the various figure
types is shown in Figure 9.
An internal 16·bit Mask register determines which bit(s)
in th~ accessed word are to be modified. A one in the
Mask register allows the corresponding bit in the display
RAM to be modified by the R/MfW .cycle..A zero in the
Mask register prevents the GDC from modifying the corresponding bit in the display RAM.
RDAT, WDAT, DMAR, and DMAW Operations move
through the Display memory as shown in the '.'DMA"
Column.
The mask must be set by the Mask Command prior to
issuing the WDAT or DMAW command. The Mask register is automatically set by the CURS command and
manipulated by the graphics commands.
The other parameters required to set up figure reading
or drawing are shown in Figure 3.
The display RAM bits can be modified in one of four
ways, They can be set to 1, reset to 0, complemented
or replaced by a pattern.
DRMINGTYPE
DC
INITIAL YAWE'
0
RECTANGLE
-.1
AREA FILL
LINE
When replace by a pattern mode is selected, lines,
arcs and rectangles will be drawn using the 16-bit
pattern in parameter RAM bytes 8 and 9.
ARC""
In set, reset, or complement mode, parameter RAM
bytes 8 and 9 act as another level of masking for line
arc and rectangle drawing. As each 16-bit segment'
of the line or arc is drawn, it is checked against the
pattern in the parameter RAM. If the pattern RAM bit
is a one, the display RAM bit will be set, reset, or
complemented per the proper modes. If the pattern
RAM bit is a zero, the display RAM bit won't be
modified.
When replace .by pattern mode is seleccted, the
graphics character and fill commands will cause the
8 x 8 pattern in parameter RAM bytes 8 to' 15 to be
written directly into the display RAM in the appropriate locations.
,
1"11
D
21"DI-I"1I
D2
Dt'
DM
•
-1
-1
2(I"DI-I"II) 21401
'-1
2(.-1)
-1
rsln 81
A-1
B-1
-1
A-1
B-1
A
A
GRAPHIC
CHARACTER'"
B~1
A
A
WRITE DATA
W-1
DMM
D-1
C-1
DMAR
D-1
C-Z'
READ DATA
(C-2)/2t
W
'INITIAL YAWES FOR THE VARIOUS PARAMETERS ARE LOADED
WHEN THE FIGS COMMAND BYTE IS PROCESSEI).
"
"CIRCLES ARE DRJIINN WITH 8 ARCS, EACH OF WHICH SPAN 45°,
SO THAT SIN. = 1/./2 AND SIN 8 = 0.
• .... GRAPHIC CHARACTERS ARE A SPECIAL CASE OF BlT-MAP
AREA FILLING IN WHICH B AND A ,,8. IF A = 8 THERE IS NO
NEED TO LOAD D AND,D2.
WHERE:
-1 = ALL ONES VAWE.
ALL NUMBERS ARE SHOWN IN BASE 10 FOR CONVENIENCE. THE GDC
ACCEPTS BASE 2 NUMBERS (2. COMPLEMENT NOTATION WHERE
APPROPRIATE).
- = NO PARAMETER BYTES SE/(I" TO GDC FOR THIS PARAMETER.al = THE LARGER OF AX OR Ay.
aD THE SMALL:ER OF AX OR ay.
=
r = RADIUS OF CURVATURE, IN PIXELS.,
'
• = ANGLE FROM MAJOR AXIS TO END OF THE ARC. • ,,45°•
• = ANGLE FROM MAJOR AXIS TO START OF THE ARC. • ,,45°.
I = ROUND UP TO THE NEXT HIGHER INTEGER.
I = ROUND DOWN TO THE NEXT LOWER INTEGER.
A = NUMBER OF PIXELS IN THE INITIALLY SPECIFIED DIRECTION.
B = NUMBER OF PIXELS IN TflE DlRECT10N AT RIGHT ANGLES TO
In set, reset, or complement mode, the 8 x 8 patte~n in
parameter RAM bytes 8 to 15 act as a mask pattern
for graphics character or fill commands. If the appropriate parameter RAM bit is set, the display RAM bit
will be modified. If the parameter RAM bit is zero, the
display RAM bit will not be modified. These modes
are selected by issuing a WDAT command without
parameters before issuing graphics commands. The
pattern in the parameter RAM has 'no effect on WIilAT,
RDAT, DMA\N. or DMAR operations.
THE INITI"LLY SPECIFIED DIReCTION.
W = NUMBER OF WOI'IDS TO BE ACCESSED.
C. NUMBER OF IIYTES TO BE TRANSFERRED IN THE INITIALLY
.
SPECIFIED DIRECTION. (TWO BYTES PER WORD IF WORD
TRANSFER 'MODE IS SELEC;TED.)
D = NUMBER OF WORDS TO BE ACCESSED IN THE DIRECTION AT
RIGHT ANGLES TO THE IIITIALLY SPECIFIED DIRECTION.
DC.'DRAWING COUNT PARAMETER WHICH IS ONE LESS THAN
THE NUMBeR OF RMW CYCLES TO BE EXECUTED.
OM = DOTS MASKED FROM DRAWING DURINII ARC _NO.
t = NEEDED ONLY FOR WORD READS.
Figure 3, Drawing' Parameter Details
8-111 .
210855-002
82720
After the parameters have been set; line, arc, circle, rectangle or slanted rectangl.e drawing operations are
.initiated by the Figure Draw (FIGD) command.
Gharacter, slanted character, area fill and slanted area
fill drawing operations are initiated by the Graphic;s
Character Draw (GCHRD) command. DMA transfers are
initiated by the DMA Read or Write (DMAR or DMAW)
commands. Data Read Operations are initiated by the
Read Data (RDAT) Command. Data Write Operations
are initiated by writing a parameter after the WDAT
command.
The area fill operation steps and repeats the 8 x 8
graphics character pattern draw operation to fill a
rectangular area. If the size of the rectangle is not an
jntegral number of 8 x 8 pixels, the GDC will automatically truncate the pattern at Jhe edges furthest
from the starting point.
The Graphics Character Drawing capability can be
modified by the Graphics Character Write Zoom Factor (GCHR) parameter of the zoom command. The
zoom write factor may be set from 1 to 16 (by using
~ from 0 to 15 in the parameter). Each dot will be
repeated in memory horizontally and vertically
(adjusted for drawing direction) the number of times
specified by the zoom factor.
The WDAT command can Qe used to rapidly fill large
areas in memory with the same value. The mask. is set
to all 1's, and the least significant bit of the WDAT
parameter replaces all bits of each word written.
Character Mode Memory Organization
In character mode, the Display memory is organized
into up to. 8K characters of up to 13 bits each. Wide
.mode is also available for characters of up to 26 bits.
"
'. The display memory can"be Jarger than the display
itself. The display width (in characters) is a parameter
of the reset command. The display memory width (in
characters) is a parameter of the, Pitch Command.
The height of the display (in lines) is a parameter of
the Reset Command. The display memory height is
determined by diliiding the number of display
memory words by the pitch.
Character Mode Display Timing
In cha~cter mode, the display timing works as it does
in graphics mode. In addition, the Address 17 output
becomes. cursor output. The characteristics of the cursor are defined by parameters of the. cursor arid
Character Characteristics (CCHAR) command. One bit
allows the cursor output to be enabled or disabled. The
height of the cursor is programmable by selecting the
top and bottom line between which the cursor will
appear. The blink. rate is also programmable. The
parameter selects the number of frame times that the
cursor will be inactive and active, resulting in a 50%
duty cyCle cursor blinking at 2 x the period specified
by the paramet~r.
The cursor output pin also provides the line counter bit
4 signal, which is valid 10 clocks after the trailing edge
of HSyi\lC.
Character Mode Special Display Functions
WINDOWING
The GDC's Character Mode display can be partitioned into one to four windows on the screen. The
windows are defined by parameters written into the
GDC's Parameter RAM. Each window is specified by
a starting address and a window length in lines.
If windowing is not required, the first window length
should be specified to be the same as the active
display length.
ZOOMING AND PANNING
'In character mode, zooming and pan handling commands function the same way as in Graphics Mode.
Character Mode Drawing and Writing
The GOC can read or write characters of up to 13
bits into or out of the Display RAM.,
All reading and writing functions take place at the
display RAM location specified by the cursor. The cursor location can be read by issuing the CURD command. The cursor can be moved anywhere within the
display memory by the CURS command. The cursor
location is also modified by the execution of character
read or write commands.
In character mode, the display works almost, exactly as
it does in graphics mode. The differences lie in the fact
that data read from the display RAM is used to drive
a character generator as well' ~s attribute logic if
desired. In Character mode, address bits 13-16 become
line counter outputs used to select the proper line of
the character generator, and the address 17 output
becomes the cursor and line counter MSB.output.
Each character is written or' read via a
Read/Modify/Write cycle. The mask register contents
determine which bit(s) in the character are modified.
The mask register can be' used to change character .
codes without modifying attribute bits or vice-versa. The
Replace with pattern, Set, Reset and Complement
8-112
210655-002
intJ
82720
modes work exactly as they do in graphics mode, with'
the exception that the parameter RAM Pattern is not
'used. The pattern used is a parameter of the WOAT
command.
The Figure Specify (FIGS) command must be set to
Character Display mode, as well as specify the direction the cursor will be moved by read or write d~ta
commands.
.
In character mode, the FIGO and GCHRO commands
are not used.
active high line counter reset signal which is valid
10 clockS after the tr'liling edge of HSYNC. During the
active display line time, A16 provides blink timing fOr
external attribute circuitry. This signal blinks at 112 the
blink rate of the cursor with a 75% on, 25% off duty
cycle. A17 provides a signal which selects b~en
graphics or character display, which is also valid
10 clocks after the trailing edge of HSYNC. During the
active display time, A17 provides the cursor signal. The
cursor timing and characteristics are defined in exactly
the same way as in pure character mode.
, Mixed Mode Special Displ,y F~nctions
Mixed Mode Memory Organization
In mixed mode, the display memory is organized into,
two banks of up to 64K words of 16 bits each (32 bits
in wide mode).
The display height and width are, programmable by'the
same Reset or Sync command parameters as in the
graphics and character modes. The display memory
width (in words)'is a parameter of,the Pitch Command
and the height of the display memory is determined by'
dividing the number of display memory words by the
pitch.
WINDOWING
The GOC supports two'display windows: in mixed mode.
They can independently be programmed into either
graphics dr character mode determined by the state of
two bits in the parameter RAM. The window location
in display memory and size are alSo determined by
parameters in the parameter RAM.
ZOOMING AND PANNING
In mixed mode, zooming and panning commands
function the same as in graphics and character
,mode.
An image mode Signal is used to switch the external
Circuitry between graphics and character modes in
two display windows.
Mixed Mode Drawing and Writing
In a graphics window, the GOC works as it does in
pure graphics'mode, but on a smaller total memory
space (64K words vs Q12K words).
In mixed mode, the GOC can write or draw in exactly
the same ways as in both graphics and character
modes. In addition, the FIGS command has a parameter GO' (Graphics Drawing Flag) which sets the
image mode signal to select the proper RAM bank.
In a character window, the GOC works as it does in
pure character mode, but the, line counter must be
implemented externally. The counter is cli:>cked by
the h,or,iZ~)ntal sync pulse and reset by a Signal supplied by the GOC.
DEVICE PROGRAMMING
The GOC occupies two addresses on the system microprocessor bus through which the GOC's status regiSter,
and FIFO are accessed. Commands and parameters
are written into the GOC FIFO and are differentiated by
address bit NJ. The status register or the FIFO can be
read as selected by the' address line.
In mixed ~ode, the GOC p~ovides both a cursor and
an attribute blln,k timing signal.
Mixed
Mo~e
Display Timing
AO
In mixed mode, each word 'in a graphic area is accessed
twice iii succession. TheAW paramete~ of the Reset
or Sync command should, be set to twice its normal
value, ~nd the video shift reglste~ load'signal must be
's~ppressed during the extra accel1S cycle.
,
,t
fJ
,I
READ
STATUS REGISTER
I
I
I
I
I
I
I
WRrrE
PARAMETER INTO FIFO
1 1I
FIFO READ
1
,
In addition, A16 becomes a Multiplexed Attribute and
Clear Une Counter signal and A17 becomes a multiplexed c~r and image mode signal. A16 provid~s an
I
I
1'1
I
I
I
I
I
I
;
I
1
,COMMAND INTO FIFO
I
I
I
II I I
I I I I
I,
,
Figure 4. GDC Mlcroproc:essor BU8j~tertace
Registers
8-113
82720
Commands to the GOC take the form of a command
byte followed by a series of parameter bytes as
needed for specifying the details of the command.
The command processor' decodes the commands"
unpacks the parameters, loads them into the appropriate registers wit bin the GOC and initiates the required oiJerations.
'
The cQmmands available in the GOC can be organized into five categories as described in figure 5.
SR-6: Horizontal BI.anklng Active: A 1 value for
this flag signifies that horizontal retrace blanking is
currently underway.
, SR-5: Vertical Sync: Vertical retrace sync occurs
while this flag is a 1. The vertical sync flag coordinates display format modifying commands to the
blanked interval surrounding vertical sync. This
eliminates display disturbances.
SR-4: DMA Execute: This bit is a 1 during OMA data
transfers.
.
VIDEO CONTROL'COMMANDS
1. RESET: RESETS THE GOC TO ITS IDLE STATE.
SYNc:
SPECIFIES THE VIDEO DISPLAY FORMAT.
3. VSYNC: SELECTS MASTER OR SLAVE VIDEO
SYNCHRONIZATION MODE
4. CCHAR: SPECIFIES THE CURSOR AND CHARACTER ROW
HEIGHTS.
DISPLAY CONTROL COMMANDS
1. START:
ENDS IDLE MODE AND UN BLANKS THE DISPLAY.
2. BCTRL: CONTROLS THE BLANKING AND UNBLANKING OF
a.
, 3. ZOOM:
SR-3: Drawing In Progress: While the GOC is drawing a graphics figure, this status bit is a 1.
SR-2: FIFO Empty: This bit and the FIFO Full flag
coordinate system microprocessor accesses with
the GOC FIFO. When it is 1, the Empty flag ensures
that all the commands and parameters previously
sent to the GOC have been processed.
~~~Jl~~:~~OOM FACTORS FOR THE DISPLAY AND
GRAPHICS CHARACTERS WRITING.
•
SETS THE POSITION OF THE CURSOR IN DISPLAY
MEMORY,
5. PRAM:
DEFINES STARTING ADDRESSES AND LENGTHS OF .
THE DISPLAY AREAS AND SPECIFIES THE EIGHT
BYTES FOR THE GRAPHICS CHARACTER.
8. prrCH:
SPECIFIES THE WIDTH OF THE X DIMENSION OF
DISPLAY MEMORY.
DRAWING CONTROL COMMANDS
1. WDAT:
WRITES DATA WORDS OR BYTES INTO DISPLAY
MEMORY.
2. MASK:
SETS THE MASK REGISTER CONTENTS.
3. FIGS:
SPECIFIES THE PARAMETERS FOR THE DRAWING
PROCESSOR.
4. FIGD:
DRAWS THE FIGURE AS SPECIFIED ABOVE.
5. GCHRD: DRAWS THE GRAPHICS CHARACTER INTO DISPLAY
4. CURS:
SR-1: FIFO Full: A 1 at this flag indicates a full FIFO
in the GOC. A 0 ensures that there is room for at least
one byte. This flag needs to be checked before each
write into the GOC.
SR-O: Data Ready: When this flag is a 1, it indicates
that a byte is available to be read by the system
microprocessor. This bit must be tested before each
read operation. It drops to a 0 while the data is transferred from the FIFO into the microprocessor interface data reg ister.
.
ME~~~~frA R~:~D~O~~:~~~DS'OR BYTES FROM DISPLAY
Mr;MORy.
2. CURD:
READS THE CURSOR POSITION.
3. LPRD:
READS THE LIGHT PEN ADDRESS.
DMA CONTROL COMMANDS
1. DMAR:
REQUESTS A DMA READ TRANSFER.
2. DMAW:
REQUESTS A DMA WRITE TRANSFER.
Figure 5: GDC Command Summary
FIFO Operation "& Command Protocol
The first-in, first-out bufte,r (FIFO) in the GOC
handles the command dialogue with the system microprocessor. Thisflpw of information uses halfduplex technique, 'in which the single 16-location
FIFO is used for both directions of data movement,
one direction at a time. The FIFO'sdirectlon is controlled by the system microprocessor through the GOC's
command set. The microprocessor coordinates these
transfers by checking the appropriate status register
bits.
r
'1 Ti, ~5i7
,
"j
a
L_~-~~======vr;RTlCALSYNC
AC7IVE
HORIZONTAL BLANK AC7IVE
' - - - - - - - - - - - - L l G K r I1ENDETEC7
Figure 6. Status Register (SR)
The' command protocol used by the GOC requires
the differentiation of the first byte of a command
sequence from the succeeding bytes. This first byte
contains the operation code and the remaining bytes
carry parameters. Writing into the GOC causes the
FIFO to store a flag value alongside the data byte to
signify whether the byte was written rnto the command or the parameter address. The command pro~
cessor in the GDC tests this bit as it interprets the
..
'
entries in the FIFO.
Status Register Flags
SR-7: Ught Pen Detect: When this bit is set to 1, the
light pen address (LAO) register contains a deglitched value that the system microprocessor may
read. This flag is reset after the 3-byte LAD is moved
into the FIFO in response to the light pen read
command.
6-114
210655-002
82720
The receipt of a command byte by the command
processor marks the end of any previous operation.
The number of parameter bytes supplied with a command is cut short by the receipt of the next command
byte. A read operation from the GDC to the'microprocessor can be terminated at anytime by the next
command.
The FIFO changes direction under' the control of the
system microprocessor. Commands written into the
GDC always put the FIFO into write mode if it wasn't
in it already. If it was in read mode, any read dat'a in
the FIFO at the time of the turnaround is lost. Com-.
mands which req uire a GDC response, such as RDAT,
CURD and LPRD, put the FIFO into read mode after
the command is interpreted by the GDC's command
processor. Any commands and parameters behind
the read-evoking command are discarded when the
FIFO direction is reversed.
Read-Modify-Write Cycle
Data transfers between the GDC and the display
memory are accomplished using a read-modify-write
(RMW) memory cycle. The four dock period timing of
the RMW cycle is used to: 1) output the address, 2)
read data from the memory, 3) modify the data, and 4)
write the modified data back into the initially selected memory address. This type of memory cycle is
used for all interactions with display memory including DMA transfers, except for the two clock period
display and RAM refresh cycles.
moved to identify the pixel's location within the word.
The Execution word address pointer register, EAD, is
also adjusted as required to address the word containing the next pixel.
In character mode, all of the bits in the Pattern register are used in parallel to form the respective bits of
the modify data word. Since the bits of the character
code word are used in parallel, unlike the one-bit-ata-time graphics drawing process, this facility allows
any or all of the bits in a memory word to be modified
in one RMW memory cycle. The Mask register must
be loaded with 1s in the positions where modification
is to be permitted.
The Mask register can be loaded in either of two
ways. In graphics mode, the CURS command contains a four-bit dAD field to specify the dot address.
The command processor converts this parameter
into the one-of-16 format used in the Mask register
for figure drawing. A full 16 bits can be loaded into
the Mask register using the MASK command. In addition to the character mode use mentioned above, the
16-bit MASK load is convenient in graphics mode
when all of the pixels of a word are to be set to the
same value.
The Logic unit combines the d'ata read from display
memory, the Pattern register, and the Mask register
to generate the data to be written back into display
memory. Anyone of four operations can be selected:
REPLACE, COMPL£MENT, CLEAR or SET. In each
case, if the respective Mask bit is 0, that particular bit
of the read data is returned to memory unmodified. If
the Mask bit is 1, the modification is enabled. With
the REPLACE operation, the modify data simply
takes the place of the read data for modification
enabled bits. For the other three operations, a 0 in
the modify data allows the read data bit to be returned to memory. A 1 value causes the specified
operation to be performed in the bit positions with
set Mask bits.
The operations performed during the modify portion
of the RMW cycle merit additional explanation. The
circuitry in the GDC uses three main elements: the
Pattern register, the Mask register, and the 16-bit
Logic unit. The Pattern register holds the data pattern to be moved into memor'y. It is roaded by the
WDATcommand or, during drawing, from the parameter RAM. The Mask register contents determine
which bits of the read data will be modified. Based on
the contents of these registers, the Logic unit performs the selected operations of REPLACE, COMPLEMENT, SET, or CLEAR on the data read from
display memory.
Figure Drawing
The GDC draws graphics figures at the rate of one
pixel per read-modify-write (RMW) display memory
cycle.' These cycles take four clock periods to complete. At a clock frequency of 5 MHz, this is equal to
800 ns. During the RMW cycle the GDC simultaneously calculates the address and position of the
next pixel to be drawn.
The Pattern register contents are ANDed with the
Mask register contents to enable the actual modification of the memory read data, on a bit-by-bit basis.
For graphics drawing, one bit at a time from the
Pattern register is combined with the Mask. When
ANDed with the bit set to a 1 in the Mask register, the
proper single pixel is modified by the Logic Unit. For
the next pixel in the figure, the next bit in the Pattern
register is selected and the Mask register bit is
The graphics figure drawing process depends on the
display memory addressing structure. Groups of 16
horizontally adjacent pixels form the 16-bit words
6-115
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82720
which are handled by the GDC. Display memory is
organized as a linearly addressed space of these
words. Addressing of individual pixels is handled by
the GDC's internal RMW logic.
During the drawing process, the GDC finds the next
pixel of the figure "'!hich is one of the eight nearest
neighbors of the last pixel drawn. The GDC assigns
each of these eight directions a number from 0 to'7,
starting with straight down and proceeding
counterclockwise.
Figure 8 summarizes these operations for each
direction.
, Whole word drawing is useful for filling areas in
memory with a Single value., By setting the Mask
register to all1s with the MASK command, both the
LSB and MSB of the dAD will always be 1, so that the
EAD value will be incremented or decremented for
each cycle regardless of direction. One RMW cycle will
be able to affect all 16 bits (;)f the word for any drawing
type. One bit in the Pattern register is used per RMW
cycle to write ail the bits of the word to the same value.
The next Pattern bit is-used,for, the word, etc.
DIR
o
ADDRESS OPERATION(S)
EAD
= EAD + P'
EAD=EAD+P
If dAD.MSB .. 1 then EAD
dAD
LR(dAD)
=
Figure 7. Drawing Directions
Figure drawing requires the proper manipulation of
the,address and the pixel bit position according to
the drawing direction to determine the next pixel of
the figure. To move to the word above or below the
current one, it is necessary to subtract or add the
number of words per line in display memory, This
parameter is called the pitch. To move to ~he word to
either side, the Execute word address cursor, EAD,
must be incremented or decremented as the dot ad·
dress pointer bit reaches the LSB or the MSB of t~e
Mask register. To move to a pixel within the same
word, it is necessary to rotate the dot address pointer
register to the right or left.
2
If dAD.MSB " 1 then EAD
dAD .. LR(dAD)
3
EAD" EAD -P
If dAD.MSB .. 1 then EAD
dAD = LR(dAD)
= EAD
+ 1
= EAD
+ 1
= EAD
+ 1
4
EAD .. EAD-P
5
EAD=EAIJ-P
If dAD.LSB
'1 1hen EAD .. EAD - 1
dAD .. RR(dAD)
6
_ If d!lD.LSB
1 then !!AD .. EAD - 1
'
dAD " RR(dAD) "
7
EAD ,,'EAD + P
If dAD.LSB .. 1 then EAD " EAD - 1
dAD
RR(dAD)
=
=
=
WHERE
P =
CAD ..
dAD =
LSB =
MSB ..
PITCH, LR .. LEFT ROTATE, RR
CURSOR ADDRESS
DOT ADDRESS
LEAST SIGNIFICANT BIT
MOST SIGNIFICANT BIT
= RIGHT ROTATE
Flglire 8. Address Calculation Details
,,'
8-116
210656.()()2
•
inter
82720
arc as drawing proceeds. An arc may be up to 45
degrees in length. DMA transfers are done on word
boundaries only, and follow the arrows indicated in
the table to find successive word addresses. The
slanted paths for DMA transfers indicate the GDC
changing both the and Y components of the word
address when moving to the next word. It does not
follow a 45 degree diagonal path by pixels.
For the various figures, the effect of the initial direction
upon the resulting drawing is shown in figure 9.
Note that during line drawing, the angle of the line
may be anywhere within the shaded octant defined
by the DIR value. Arc drawing starts in the direction
initially specified by the DIR value and veers into an
Dir
000
001
x
,
0
•
.. ~ <>
.. r' .I / 0
~ 1 <>
,
0
•
Line
.~
Arc
Character Slant Char Rectangle
~---;~~
~
,'~
,,
~
I'
f!f
...
010
.
011
100
1,01
110
111
I'
I "
,
,
~
~
--:~'--
~
v~ -'~~~~)
A-
r
A
'
"
.'
I
I
~
r:
,
..
I
.. I
~
-:. ~]
~
~
0
I .; 0
~
-
<>
DMA
i'N
~
~
~
m
~
-~--
-#
Figure 9. Effect of the Direction Parameter
8-117
210655·002
82720
Drawing Parameters
memory as many times as desired without ,eloadlng
tbe parameter, RAM:
In preparation for graphics figure drawing, the GDC's
,Drawing Processor needs the figure type, direction
and drawing parameters, the starting pixel address,
and the pattern from the microprocessor. Once these
are in place within the' GDC, the Figure Draw command, FIGD, initiates the drawing operation. From
that pOint on, the system microprocessor is not involved in the drawing process. The GDC Drawing
Processor coordinates the RMW circuitry and address registers to draw the specified figure pixel by
pixel.
Once the parameter RAM has been loaded with up to
eight 'graphics character bytes by the ,approp~iate
PRAM command, the GCHRD command can be used
to draw the bytes into display memory starting at the
cursor. The zoom magni,fication factor for writing,
set by the zoom command, controls the size of the
character written into the display memory in Integer
multiples of 1 through 16. The bit values in the PRAM
are repeated horizontally and vertically the number
of times specified by the ;zoom factor.
The movement of these PRAM bytes to the display
memory is controlled by the parameters of the FIGS
,command. Based on the specified height and width
of the area to be drawn, the parameter RAM is
sca'nned to fill the required area.'
The algorithms used by the processor for figure
drawing are designed to optimize its drawing speed.
To this end, the specific details about the figure to be
drawn are reduced by the'mic::roprocessor to a form
conducive to high-speed address calculations within
the GDC. In this way the repetitive, pixel-by-pixel
calculations can be done quickly, thereby minimizing
the overall figure drawing time. Figur,e 3 summarizes
the parameters.
For an 8-by-8 graphics character" the first pixel drawn
uses the LSB of RA-15, the second pixel uses bit 1 of
RA-15, ,and so on" until the MSB of RA-15 is re,ached.
The GDC jumps to the corresponding bit in RA-,14 to
co~tinue the drawing. The progression then advances
toward the LSB of RA-14. This snakih'g sequence is continued for the other 6 PRAM bytes. This progression
matches the seq~ence of display rnemory addresses
calculated by the drawing processor as shown in
figure 9. If the area is mmower than 8 pixels wide, the
snaking will advance to the next PRAM byte before the
MSBis reached. If the area is less than 8 lines high,
fewer bytes in the parameter RAM will be scanned. If
the area is larger than 8 by 8, the GDC will repeat the
contents of the parameter RAM in two dimensions.
Graphics Character Drawing
Graphics characters can be drawn into display
memory pixel-by-pixel. The up to 8-by-8 character is
loaded into the GDC's parameter RAM by the system
microprocessor. Consequently, there are no
limitations on the character set used. By varying the'
drawing parameters and drawing direction,
numerous drawing options ~re available. In area fill
applications; a 'character can be written into display
,
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Parameter RAM Contents
The parameters stored in the parameter RAM,
PRAM, are available for the GDC to refer to
repeatedly during figure drawing and rasterscanning. In each mode of operation the values in the
PRAM are interpreted by the GDC in a predetermined fashion. The host microprocessor must load
the appropriate parameters into the proper PRAM
locations. PRAM loading command allows the host
to write into any location of the PRAM and transfer as
many bytes as desired. In this way any stored parameter byte or bytes may be changed without influencing the other bytes.
The PRAM stores two types of information. For
specifying the details of the display area partitions,
blocks of four bytes are used. The four parameters
stored in each block include the starting address in
display memory of each display area, and its length.
8-119
In addition, there are two mode bits for each area
which specify whether the area is a bit-mapped
graphics area or a coded character area, and
whether a normal or wide display cycle is to be used
for that area.
The other use for the PRAM contents is to supply the
pattern for figure drawing when in a bit-mapped
graphics area or mode. In these situations, PRAM
bytes 8 through 16 are reserved for this patterning
information. For line, arc, and rectangle drawing
(linear figures) locations 8 and 9 are loaded into the
Pattern register to allow the GDC to draw dotted,
dashed, etc. lines. For area filling and graphics bitmapped character drawing locations 8 through 15
are referenced for the pattern or character to be
drawn.
Details of the bit assignments are shown on .the following pages for the various modes of operation.
~
210655-002
"nt_I"
lu~···
82720
:_.,___
S
RAo0'
S_AI_Dl'_ _ _
1
SADl H
~
,.1
L......I._..........I.........I._.l.I_..II_...I........
DISPLAY PARTITION AREA 1 STARTING
ADDRESS WITH LOW AND HIGH
~~:~::fS~~CE FIELDS (WORD
LENGTH OF DISPLAY PARTITION 1
(LINE COUNT) WITH LOW AND HIGH
SI,GNIFICANCE FIELDS.
THE IMAGE BIT AFFECTS THE·
OPERATION OF THE DISPLAY ADDRESS
COUNTER IN CHARACTER MODE. IF
'--------------
~E~~Ac?:E~J~~ ~~~ON~\FTER
EACH READ CYCLE. IF THE IMAGE
:VJ~~~TF~~~~iEI~.f~~ENT
READ CYCLES.
A WIDE DISPLAY CYCLE WIDTH
OF TWO WORDS PER MEMORY CYCLE
IS SELECTED FOR THIS DISPLAY
'--------------- ~~~~I~pI'l~:J1~~~~6~:TliR IS
THEN INCREMENTED BY 2 FOR EACH
DISPLAY SCAN CYCLE. OTHER MEMORY
CYCLE TYPES ARE NOT INFLUENCED.
DISPLAY PARTITION 2 STARTING
- - ADDRESS AND LENGTH
SAD2,
RAo4
a
6
DISPLAY PARTITION 3 STARTING
ADDRESS AND LENGTH
RA-8
o
10
11
RA-12
DISPLAY PARTITION 4 STARTING
ADDRESS AND LENGTH
13
14
15
Figure 10. Parameter RAM Contents-Character Mode
•
8-120
210655-002
82720
DISPLAY PARTITION AREA 1
STARTING ADDRESS WITH LO\'I!
MIDDLE, AND HIGH SIGNIFICANCE
FIELDS (WORD ADDRESS~
LENGTH OF DISPLAY PARTITION
AREA 1 WITH LOW AND HIGH
SIGNIFICANCE FIELDS (LINE CDUNT)
IN MIXED MODE, A 1 INDICATES AN
IMAGE OR GRAPHICS AREA, AND A 0
INDICATES A CHARACTER AREA. IN
GRAPHICS MODE THIS BIT MUST BE O.
WIDE DISPLAY CYCLE MODE BIT
DISPLAY PARTITION AREA 2
STARTING ADDRESS AND LENGTH WITH
IMAGE IDENTIFY BIT AS IN AREA 1.
5
}
RA-10
ClCHR 6
11
GCHR5
12
GCHR4
13
GCHR3
14
GCHR2
PATTERN OF 16 BITS USED FOR
FIGURE DRAWING TO PERFORM
DOTTED, DASHED, ~TC. LINES
GRAPHICS'CHARACTER BYTES
TO BE MOVED INTO DISPLAY
MEMORY WITH GRAPHICS
CHARACTER DRAWING
15
Figure 11. Parameter RAM Contents-Graphics and Mixed Graphics and Character Modes
8-121
210655-002
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~OOl!o..orMInOO£m
82720
I
"-
RESET:
0 1 0
o
1 0'
SYNC:
0
0
, \/SYNC:
0
CCHAR:
0
0
START:
0
1
iCTRL:
0
I
0
11
0
o
10
WDAT:
0
0
1
I
DE
MASK:
0
0
1 1M
FIGS:
o
1
0
I
'0
0
0
0
0
0
0
o
1
0
FIGD:
0
0
GCHRD:
0
0
CURS:
o1
PRAM:
oI
PITCH:
0
I
1
1
1 TYPE 10 1 MOD
I
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
I'
o
1
ZOOM:
0
1DE
RDAT:
0
0
SA
I
0
0
0
TYPE
1 1
I
CURD:
0
10
LPRD:
0
10
0
0
1'1
1 1 TYPE
I
DMAW:
0
1
TYPE
I
o.
DMAR:
1
MOD
1"0 1
0
0
I
111
MOD
I
MOD
Figure 12. Command Bytes su~marY
VIDEO CONTROL COMMANDS
'RESET: 10
,
0
!
0
,
0
,
0! 0 0
0
1
!
!
BLANK THE DISPLAY, ENTER IDLE MODE,
AND INITIALIZE WITHIN THE GDC:
~FIFO
~COMMAND
~INTERNAL
PROCESSOR
COUNTERS
Figure 13. Reset Command
RESET COMMAND
This command can be executed at any time and does
not modify any of the parameters already loaded into
the GDC.
If followed by parameter bytes, this command also
sets the sync gen~rator parameters as described
below. Idle mOde is exited with the STARTcommand.
8-122
82720
P1
o
OjCjFjljDjGjS
AW
P2
VS l
P3
I
!
P5
0
P6
0
!
HFP
!
1\
I
I
I '1" I--
HORIZONTAL FRONT PORCH WIDTH -1.
oj
~ HORIZONTAL BACK PORCH WIDTH -1.
oj
VFP
~ VERTICAL FRONT PORCH WIDTH
~ ACTive DISPLAY LINES PER VIDEO FIELD,
LOW BITS
VBP
I
VERTICAL SYNC WIDTH, HIGH BITS
HBP
ALL
I
HORIZONTAL SYNC WIDTH -1
VERTICAL SYNC WIDTH, LOW BITS
'"
P7
P8
MODE CONTROL BITS.
SEE FIGURE 15.
___ ACTIVE DISPLAY WORDS PER LINE -2. MUST .
BE EVEN NUMBER WITH BIT 0 = O.
HS
j
\
P4
___
I
~
I
I
I
AL
I"
I--
ACTIVE DISPLAY LINES PER VIDEO FIELD,
HIGH BITS
VERTICAL B4CK PORCH WIDTH
Figure 14. Optional Reset Parameters
In graphics mode, a word is a group of 16 pixels. In
character mode, a word is one character code and its
attributes, if any.
HORIZONTAL BACK PORCH CONSTRAINTS
1. In general:
HBP ~3 words
2. If interlaced display mode is used, or the IMAGE or
WIDE mode bits change within one video field:
HBP;:::: 5 words
The number of active words per line must be an even
number from 2 to 256.
MODE CONTROL BITS (FIGURE 15)
An all-zero parameter value selects a count equal to
2n where n = number of bits in the parameter field for
vertical parameters.
Repeat Field Framing:
All horizontal widths are counted in display words.
All vertical intervals are counted in lines.
.
Interlaced Framing:
Sync Parameter Constraints
HORIZONTAL FRONT PORCH CONSTRAINTS
1. In general:
HFP ~2 words
2. If DMA is used, or the display zoom factor is greater
than one in interlaced display mode:
HFP ~3 words
3. If the GDC is used in slave mode:
HFP ~4 words
4. If the light pen input is used:
HFP ~6 words
'
HO.RIZONTAL Sync CONSTRAINTS
1. If dynamic RAM refresh is used:
HS ~2 words
2: If interlaced display mode is used:
HS ~5 words
Noninterlaced Framing:
2 Field Sequence with V2
line offset between otherwise identical fields.
2 Field Sequence with V2
line offset. Each field displays alternate lines.
1 field brings all of the information to the screen.
Total scanned lines in interlace mode is odd. The
sum of VFP + VS + VBP + AL should equal one less
than the desired odd number of lines.
.
.
Dynamic RAM refresh is important when high display
zoom factors or DMA are used in such a way that not
all of. the rows in the RAMs are regularly accessed
during display raster generation and for otherwise
inactive display memory.
Acqess to display memory can be limited to retrace
blah king intervals only, so that no disruptions of the
.
image are seen on the screen.
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210655·002
82720
DISPLAY MODE
CG
0 0
MIXED GRAPHICS & CHARACTER
0 1
GRAPHICS MODE
1 0
CHARACTER MODE
1 1
INVALID
VIDEO fRAMING
IS
NONINTERLACED
0 0
0 1
INVALID
1 0
INTERLACED REPEAT FIELD
FOR CHARACTER DISPLAYS
1 1
INTERLACED
--
-.-~-
-----~~-----.---
..
D
DYNAMIC RAM REFRESH CYCLES ENABLE
0
NO REFRESH-STATIC RAM
1
REFRESH-DYNAMIC RAM
DRAWING TIME WINDOW
F
0
DRAWING DURING ACTIVE DISPLAY TIME
AND RETRACE BLANKING
1
DRAWING ONLY DURING RETRACE BLANKING
Figure 15. Mode Control Bits
SYNC:
1
0 1 0 I 0 1 0 1'1'1'
tDL
P1
~~~~~~~L1
P3
THE DISP.LA Y IS ENABLEO BY
A " AND BLANKED BY A O.
MODE CONTROL BITS.
SEE FIGURE 15.
ACTIVE DISPLAY WORDS PER LINE -2. MUST
BE EVEN NUMBER WITH BIT 0 = o.
'-'"T'-................J,..;...........L.....I
.J...-'--'-_~L...H...JI---
'-'-J..........
VERTICAL SYNC WIDTH, HIGH BITS
' - - - - - - - HORIZONTAL FRONT PORCH WIDTH -1.
HORIZONTAL BACK PORCH WIDTH -1.
VERTICAL FRONT PORCH WIDTH
'-J....J....J.....J...-'--'--'-...J- ~g~~"O':SPLAY LINES PER VIDEO FIELD,
'-'-J........J--'-.Jt_A_~L...H...Jr---
~~T~Virf~SPLA Y LINE,S PER VIDEO FIELD,
VERTICAL BACK PORCH WIDTH
Figure 16. Sync Command
8-124
inter
82720
SYNC Format Specify Command
must be 4 or more display cycles wide. This is equivalent to eight or more clock cycles. This gives the slave
GOCs time to initialize their internal video sync
generators to the proper point in the video field to
match the incoming vertical sync pulse (VSYNC).
This resetting of the generator occurs just after the
end of the incoming VSYNC pul$e, during the HFP
interval. Enough time during HFP is required to allow
the slave GDC to complete the operation before the
start of the HSYNC interval.
This command loads parameters Into the sync
generator. The various parameter fields and bits are
identical to those at the RESETcqmmand. The GOC
is not reset nor does it enter idle mode.
Vertical Sync Mode Command
When using two or more GOCs' to contribute to one
image, one GOC is defined as the master sync
generator, and the others operate as its slaves. The
VSYNC pins of all GOCs are connected together.
Once the GOCs are initialized and set up as Master
and Slaves, they must be given time to synchronize. It
is a good idea to watch the VSYNC status bit of the
Master GDC and wait until after one or more VSYNC
pulses have been generated before the display process is started. The START command will begin the
active display of data and will end the video
synchronization process, so be sure there has been
at least one VSYNC pulse generated for the Slaves to •
synchronize to.
Slave Mode Operation
A few considerations should be observed when
synchronizing two or more GOCs to generate overlayed video via the VSYNC INPUT/OUTPUT pin. As
mentioned above, the Horizontal Front Porch (HFP)
VSYNc:lo"
,
,
,
0"
I
I!
'I~
O-ACCEPT EXTERNAL VERTICAL
,~~iiiiWEA~~~~ VERTiCAL
SYNC-MASTER MODE
Figure 17. Vertical Sync Mode Command
CCHAR: 10
1
•
!
,
0
,
0
,
,
,
0
I Iscl
P3
I 9Bo;r
BRL
1
,
,
I
•
,
r--
o/0f
I-
,LR
P2
,
LINES PER CHARACTER ROW-,
DISPLAY CURSOR IF ,
=SOR TOP LINE NUMBER IN THE
...~t::::;;:l"-;==_=-;.-=-;-=-=-=,--;--_-_ ~=~:~~~.f=R
BLINK RATE. LOWER Brrs
iL
~Rui
r--
_______
BLINK RATE, UPPER Brrs
~~:~BOTTOM LINE NUMBER IN
Figure 18. Cursor & Character Characteristics Command
8-125
210655-002
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82720
Cursor and Character Characteristics
Command
Parameter RAM Load Command
From the 'starting address, SA, any number of bytes
may be loaded into the parameter RAM at incrementing addresses, up to location 15. The sequence of
parameter bytes is terminated by the next command
byte entered into the FIFO. The parameter RAM
stores 16 bytes of information in predefined locations which differ for graphics and character modes.
See the parameter RAM discussion for bit
assignments.
In graphics mode, LR should be set to O. For interlaced
displays in graphics mode, SR should be set to 3. The
blink rate parameter controls both the cursor and attribute blin.k rates. The·cursor blink-on-time = blink-olf-time
= 2 x. SR (video frames). The attribute blink rate is
always 1/2 the curspr rate but with a 3/4 on-1/4 off duty
cycle.
DISPLAY CONTROL COMMANDS
.Zoom Factors Specify Command
Pitch Specification Command
Zoom magnification factors of 1 through 16 are available using codes 0 through 15, respectively.
This value is used during drawing by the drawing
processor to find the word directly above or below
the current word, and during display to find the start
of the next line.
Cursor Position Specify Command
The Pitch parameter (width of display memory) is set
by two different commands. In addition to the PITCH
command, the RESET (or SYNC) command also sets
the pitch value. The "active words per line" parameter, which specifies the width of the raster-scan display, also sets the Pitch of the display memory. In
situations in which these two values are equal there
is no need to execute a PITCH command.
In character mode, the third parameter byte is not
needed. The cursor is displayed for the word time in
which the display scan address (DAD) equals the
cursor address. In graphics mode, the cursor word
address specifies the word containing the starting
pixel of the drawing; the dot address value speoifies
the pixel within that word.
START DISPLAY & END IDLE MODE
START:
I0
.
!
1
!
1
I
0
!
1
!
°
!
1
,
1
I
.
DISPLAY BLANKING CONTROL
BCTRl:
I0
!
0
I
0
!
0
!
1
1
!
!
0
loel
L - ~~~ ~~S:~~YBI~A~~~~L:~
AD.
ZOOM FACTORS SPECIFY
ZOOM:
I
P1
I
0, 1
!
0
I
*'
0 SP
I
0
!
0
I
1 ,1
!
,
t
GCHR
I '
0
I
I-- ZOOM
FACTOR FOR GRAPHICS
CHARACTER WRITING MINUS 1
L_- - - - - - -
DISPLAY ZOOM FACTOR MINUS 1
CURSOR POSITION SPECIFY
CURS: 10,1 'DID' 1,0,0111
P1
P2
P3
EAD
I-- EXECUTE WORD ADDRESS, LOW BYTE
EAD
I--
~::;''~':::::::::.
:=::::~'='~.
dAtD,
I °,°I E~D1 .. -
~
EXECUTE WORD ADDRESS, MIDDLE BYTE
(GRAPHICS MODE ONLY)
WORD ADDRESS, TOP BITS
DOT ADDRESS WITHIN THE WORD
Figure 19. Display Control Commands
8-126
210655·002
inter
82720
SA
it...---STARTING ADDRESS IN
PARAMETER RAM
P,
..
I
1
1-,
TO'8 BYTES TO BE LOADED
INTO THE PARAMETER RAM
STARTING AT THE RAM ADDRESS
SPECIFIED BY SA
====:::==~.
I'"
Pn
Figure 20. Param,terRAM Load Command
PITCH:
I0 , 1 , 0 , 0
P11
I
I
0
!
r
I
1
!
I
!
I
1
1
!
I
!.-
I
NUMBER OF WORD ADDRESSES
IN DISPLAY MEMORY IN THE
HORIZONTAL DIRECTION
Figure 21. Pitch Specification Command
WRITE DATA INTO DISPLAY MEMORY
WDAT:
I
0
0
,
I
TYPE
I I
0
M?D
I
t'--___ RMW MEMORY CYCLE LOGICA~
OPERATION:
o
0
,
,
0
,
o
_
REPLACE WITH PATTERN
COMPLEMENT
RESET TO ZERO
_ S E T TO'
, _
1.-_ _ _ _ _. , - - _ DATA TRANSFER TYPE
,o
0 =::=====WORD,
LOWOF
THEN
BYTE
O
.
LOW BYTE
THE HIGH
WORD
,
,..
o
P1
,
HIGH BYTE OF THE WORD
INVALID
•
1
11-0.0----
WORDL OR BYTE
&..--'_........
1 _1.......1.......1.....""---'
WORD LOW DATA BYTE OR
SINGLE BYTE DATA VALUE
....I_~I----- ~~DDl~~~~R
P2 &..I--'............._WO_I&..R_DH..,..........
ONLY:
Figure 22. Write Data Command
DRAWING CONTROL COMMANDS
Write Data Command
Upon receiving a set of parameters (two bytes for a
word transfer, one for a byte transfer), Cine'RMW
cycle into Video Memory is done at the address
pointed to by the cursor EAD. The EAD pointer is
advanced to the next word, according to the previously specified direction. More parameters can then
be accepted.
For byte writes, the unspecified byte is treated as all
zeros during the RMW memory cycle.
In graphics bit-map situations, only the LSB of the
WDAT parameter bytes is used as the pattern in the
RMWoperations. Therefore it is possibleto have only
an all ones or all zeros pattern. In coded character
applications all the bits of the WDAT parameters are
used to establish the drawing p~ttern.
The WDAT command operates differently from the
other commands which initiate RMW cycle activity. It
requires parameters to set up the Pattern register
while the other commands use the stored values in
the parameter RAM. Like all of these commands, the
8-127
210655-002
inter
MASK:
82720
WDAT command must be preceded by a FIGS command and its parameters. Only the first three parameters need be, given follOwing the FIGS opcode, to set
up the type of drawing, the DIR direction, and the DC
value. :rhe DC pa~ameter + 1 will be the number of
RMW cycles done by the GDC with the first set of WDAT
parameters. ,Additional sets of WDAT parameters will
see a DC value of 0 which will cause only one RMW
cycle to be executed.
IO! 1 ! 0 ! 0 ! 1 ! O! 1 ! 0 I
P11
IfL
!-LOW,SIGNIFICANCE BYTE
:::::::=~===~
P21
11"
I-HIGH SIGNIFICANCE BYTE
Figure 23. Mask Register Load Command
, FIGS:
10
1
I
0
I
0
I
I!! I
P1ISLI R
1
I
I A loci
:10~~
;
:10;01
I
1
L I
I
0 10 1
DIR
1-D~ING
I
~M ;
L
DC DRAWING PARAMETER
GRAPHICS DRAWING 'FLAG FOR USE IN
MIXED'GRAPHICS AND CHARACTER MODE
P,-D DAAWlNG PARAMETER
:L~M: ;
;
p,-D1 DRAWING PARAMETER
; D;lLD1M:
::10; 0i D~LD~M;
;
~ DM DRAWING P,ARAMETER
;
:10';01
,
'
;
p , - D2 DRAWING PARAMETER
=10 ;01
DIREcnON BASE
FIGURE TYPE SELECT BITS:
LINE (VECTOR)
GRAPHICS CHARACTER
ARC/CIRCLE
RECTANGLE
SLANTED GRAPHICS CHARACTER
I
~L~"; ;
; :L
I
;
.
VALID FIGURE TYPE SELECT COMBINATIONS
.Il..
.B.
A
&
~
J..
0 0 0 0 0
CHARACTER DISPLAY MODE
DRAWING, INDIVIDUAL DOT
DRAWING, DMA, WOAl, AND
RDAT ';
0 0 0 1
0 0 0
0
SlRAIGHT LINE DRAWING
0 0
0
ARC AND CIRCLE DRAWING
I"
1
1
1
0
1
0
0
0
0 0
0
1
0
GRAPHICS CHARACTER
~~:'~~=I~:~~~~~
PATTERN
r-Mj
COMIlINATIONS
"
ASSURE
•
CORRECT DRAWING '
OPERATION
RECTANGLE DRAWING
SLANTED GRAPHICS
CHARACTER DRAWING AND
SLANTED AREA FILLING
"
Figure 24. Figure·Drawing Parameters Specify Command
. 8-128
210655-002
inter
82720
FIGD:
10
!
1
I
1
!
0
I
1 ! 1 ,0
1
0
pixel pointed to by the cursor, EAD, and the dot
address, dAD.
I
I
Graphics Char. Draw and Area Fill Start
Command
Figure 25. Figure Draw Start Command
GCHRD:
I0
I
1
!
1 (0
I
1
!
0 , 0 , 0
Based on parameters loaded with the FIGS command, this command initiates the drawing of the
graphics character or area filling pattern stored in
Parameter RAM. Drawing begins at the address in
display memory pointed to by the EAD and dAD
values.
I
Figure 26. Graphics Character Draw
and Area Filling Start Command
DATA READ COMMANDS
Mask Register Load Command
Read Data Command
This command sets the value of the 16-bit Mask register of the figure drawing processor. The Mask register controls which bits can be modified in the display
memory during a read-modify-write cycle.
Using the DIR and DC parameters of the FIGS command to establish direction and transfer count,
multiple RMW cycles can be executed without
specification of the cursor address after the initial
load (DC = number of words or bytes).
The Mask register is loaded both by the MASK command and the third parameter byte of the CURS
command. The MASK command accepts two parameter bytes to load a 16-bit value into the MASK
register. All 16 bits can be individually one or zero,
under program control. The CURS command on the
other hand, puts a "1 of 16" pattern into the Mask
register based on the value of the Dot Address value,
dAD. If normal single-pixel-at-a-time graphics figure
drawing is desired, there is no need to do a MASK command at all since the CURS command will set up
the proper pattern to address the proper pixels as
drawing progresses. For coded character DMA, and
screen setting and clearing operations using the
WDAT command, the MASK command should be
used after the CURS command if its third parameter
byte has been output. The Mask register should be set
to all ones for any "word·at-a-time" operation.
As this instruction begins to execute, the FIFO buffer
direction is reversed so that the data read from display memory can pass to the microprocessor. Any
commands or parameters in the FIFO at this time will
be lost. A command byte sent to the GDC will immediately reverse the buffer direction back to write
mode, and all RDAT information not yet read from the
FIFO will be lost. MOD should be set to 00.
Cursor Address Read Command
The Execute Address, EAD, points to the display
memory word containing the pixel to be addressed.
The Dot Address, dAD, witl'fin the word is represented
as a 1-01-16 code.
Figure Draw Start Command
Light Pen Address Read Command
On execution of this instruction, the GDC loads the
parameters from the parameter RAM into the drawing processor and starts the drawing process at the
The light pen address, LAD, corresponds to the display word address, DAD, at which the light pen input
Signal is detected and deglitched.
RDAT:ll ,0,1
ITYpE I0 IM9D I
L
DATA TRANSFER TYPE
o__
WORD, LOW THEN HIGH BYTE
LOW BYTE OF THE WORD ONLY
1 _ _ HIGH BYTE OF THE WORD ONLY
l-INVALID
o __
Figure 27. Read Data from Display Memory Command
8-129
210655-002
82720
LPRD,
EXECUTE ADDRESS (EAD), HIGH BITS
J4-
x
I
I •
JA7,
EXECUTE ADDRESS (EAD), MIDDLE BYTE
l'-
11 1
I •
, •
I •
, •
,01
THE FOLLOWING BYTES ARE RETURNED BY THE GDe:
EXECUTE ADDRESS (fAD), LOW BYTE
!
LA,DL!
,Aol...- LIGHT PEN ADDRESS, LOW BYTe
~IA:':,:~::::::':LA~,D:M:,~::,:A8~J.-- LIGHT PEN ADDRE~. MIDOLE BYTE
I X I X I X I X I X I X I LAPH 1....-- LIGHT PEN ADDRESS, HIGH BITS
<
DOT ADDRESS (dAD). lOW BYTE
x
DOT ADDRESS (dAD), HIGH BYTE
= Undefmed
= Undefined
Figure 28. Cursor Address Read Command
Figure 29. light Pen Address Read Command
DMA READ REOUEST
DMAR, I '
0
, I TYPE!' ! MOD I
-Lf+----- DATA TRANSFER TYPE:
o
0----- WORD, LOW THEN HIGH BYTE
0 ...
0----- LOW BYTE OF THE WORD
0 ....
, ...0----- HIGH BYTE OF THE WORD
0' , ...0 - - - - - - INVALID
DMA WRITE REOUEST
DMAW:IO
0
'!TYPE!'! MODI
~
RMW MEMORY LOGICAL OPERATION:
D 0 _ REPLACE WITH PATTERN
o , _ COMPLEMENT
'I
0 _ RESET TO ZERO
I - S E T TO ONE
-- 1------
1 - - - - - - DATA TRANSFER TYPE:
0 ...
WORD, LOW THEN HIGH BYTE
0----- LOW BYTE OF THE WORD
, ...1------- HIGH BYTE OF THE WORD
0 ....
o , ....o-----INVALID
Figure 30. DMA Control Commands
8-130
210655-002
inter
82720
ABSOLUTE MAXIMUM RATINGS·
·COMMENT: Exposing the device to stresses above
those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be
operated under conditions outside the limits described in
the operational sections of this specification. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Ambient Temperature Under Bias .......... (fC to 7(fC
Storage Temperature .................. -65"C to 15(fC
Voltage on any Pin with Respect
to Ground ............................ -0.5V to +7V
Power Dissipation ............................ 1.5 Watt
DC CHARACTERISTICS
TA = (fC to 7(f C; Vee = 5V ± 10%; GND =OV
Symbol
Limits
Parameter
Min.
Max.
Conditions
Unit
Vil
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
O.S
V
Vee + 0.5
V
VOL
Output Low Voltage
VOH
Output High Voltage
0.45
V
IOZ
Output Leakage Current
±10
/LA,
Vss+0.45,;;VI .;;
Vee
III
Input Leakage Current
±10
/LA
VSS ,;;VI .;;Vee
Vel
Clock Input Low Voltage
-0.5
0.6
V
VeH
Clock Input High Voltage
3.5
lee
Vee Supply Current
2.4
V
VCC + 0.5
V
270
mA
IOl = 2.2 mA
IOH = -400/LA
Typical = 150 mA
CAPACITANCE
TA = 25°C; Vee = GND = OV
Symbol
Limits
Parameter
Unit
Min.
Conditions
Max.
Input Capacitance
10
pF
CIO
1/0 Capacitance
20
pF
tc = 1 MHz
COUT
Output Capacitance
20
pF
V
Co
Clock Input Capacitance
20
pF
CIN
=0
210655-002
inter
82720
A.C. CHARACTERISTICS
erA = OOC to + 70°C, Vss = OV, Vee = + 5V ± to%)
DATA BUS READ CYCLE
82720
Symbol
82720-1
82720·2
Parameter
Units
Min.
Max.
Min.
Max.
Min.
Max.
TAR
Ao setup to RD I
0
0
0
ns
TRA
Ao hold after RD 1
0
0
0
ns
TAA
RD Pulse Width,
TAD
RD I to Data Out Delay
TOF
RD I to Data Float Delay
TRV
RD Recovery Time
TAO+20
TAO+20
120
0
4 TCY
ns
TAO+20
120
80
100
0
4 TCY
J
Test
Conditions
70
ns
90
ns
CL=50pF
ns
4 TCY
DATA BUS WRITE CYCLE
82720
Symbol
82720·1
82720·2
Parameter
Units
\
Min.
Max.
Min.
Max.
Min.
Max.
TAW
Ao Setup to WR I
0
0
0
ns
TWA
Ao Hold after WR I
0
0
10
ns
Tww
WR Pulse Width
120
100
90
ns
Tow
Data Setup to w.R 1
100
80
70
ns
Two
Data Hold after WR I
TRV
WR Recovery Time
Test
Conditions
'0
0
10
ns
4 TCY
4 TCY
4 TCY
ns
DISPLAY MEMORY TIMING
82720
Symbol
82720·1
82720·2
Parameter
Units
Test
Conditions
Min.
Max.
Min.
Min.
Ma6t.
TCA
Address/Data Delay from 2XWCLK I
30
160
30
130·
30
110
ns
CL=50pF
TAC
Address/Data Hold Time
30
160
30
130
30
110
ns
CL=50pF
Toc
Data Setup to 2XWCLKI
0
Teo
Data Hold Time,
T'E
2XWCLKI to DBIN
30
120
30
90
30
80
ns
CL=50pF
TCAH
2XWCLKI to ALEI
30
125
30
100
30,
90
ns
CL=50pF
TCAL
2XWCLKI to ALE I
30
100
30
80
30
70
ns
CL=50pF
TAL
ALE Low Time
TCy+30
TAH
ALE High Time
TCH -20
TcO
Video Sighal Delay from 2XWCLK I
Max.
0
T'E+20
0
T'E+20
ns
TCy+30
TCH-20
TCH-20
8-132
ns
T'E+20
TCy+30
150
lis
120
ns
100
ns
210655-002
inter
82720
A.C. CHARACTERISTICS (Continued)
OTHER TIMING
82720
Symbol
82720·1
82720·2
Parameter
Units
Min.
Tpc
LPEN or VSYNC Input Setup to 2XWCLKI
Tpp
LPEN or VSYNC Input Pulse Width
Max.
Min.
Max.
Min.
Test
Conditions
Max.
30
20
15
ns
Tev
TCY
'TCY
ns
CLOCK TIMING
82720
Symbol
82720·1
82720·2
Parameter
Units
Min.
Max.
Min.
Max.
Min.
Max.
TCY
Clock Period
250
2000
200
2000
180
2000
TCH
Clock High Time
105
TCl
Clock Low Time
105
TR
Rise Time
20
20
20
ns
TF
Fall Time
20
20
20
ns
80
70
80
Test
Conditions
ns
ns
70
ns
DMA TIMING
82720
Symbol
82720·1
82720·2
Parameter
Units
Min.
TACC
D~CK
TCAC
DACK Hold from RD I or WR I
TRR1
RD Pulse Width
TRD1
RD I to Data Out Delay
Setup to RD I or WR I
TKO
2XWCLK 1 to DREO Delay
TRQAK
DREO Setup to DACK I
Max.
Min.
Max.
Min.
Max.
0
0
0
ns
0
0
0
ns
TRD1 +20
TRD1 +20
TRD1 +20
15 TCY
+120
150
0
TAKRO
DACKI to DREOI Delay
TAKH
DACK High Time
TAK1
DACK Cycle Time, Word Mode
4 TCY
TAK2
DACK Cycle Time, Byte Mode
S TCY
15 TCY
+80
+70
120
TCY
8-133
100
0
TCy+120
TCY+ 150
TCY
ns
15 TCY
0
Test
Conditions
ns
CL=50pF
ns
CL=50pF
ns
TCy+100
ns
TCY
ns
4 TCY
4Tev
ns
5 TCY
5 TCY
ns
CL=50pF
210655-002
82720
A.C. TEST CONDITIONS
Input Pulse Levels (except 2XWCLK) ........................................................... 0.45Vto
Input Pulse Levels (2XWCLK) ............................................................... ; ... 0.3V to
Timing Measurement Reference Levels (except 2XWCLK) ............................................ 0.8V to
Timing Measurement Reference Levels (2XWCLK) ................................................ . 0.fN to
2.4V
3.9V
2.0V
3.5V
WAVEFORMS
DATA BUS TIMING
READ CYCLE
.'=>tr----------"]-----TAR11.
TRR
. ' ~TRA
)
"\
...-TRo--'"
DATA BUS
• (OUTPUT)
\
V
"'<
I - T oF DATAVAUD_
TRV
WRITE CYCLE
----IJDATA BUS
DATA
DATA
(INPUT) _ _.......:M:::;/II::.If.::;CH:.:::A~N:=G=-E _ _- J ~_ _ _ _ _ _..,. '-_ _ _....;;;;M;.;;Ay'-'C;.;.;H""AN;.;.;G;;:E;......_ __
8-134
210655-002
82720
WAVEFORMS (Continued)
DISPLAY MEMORY TIMING
READ/MODiFY/WRITE CYCLE
81
S3
82
S4
2xWCLK
ADCl-15 - - ! - - - ( I
VALID
8-135
210655-002
inter
82720
WAVEFORMS (Continued)
DISPLAY MEMORY TIMING (Continued)
READ CYCLE
51
S2
2xWCLK
ADo-AD" ---!---------T,K.Q-----~------~-
------------+_-.L
I-----T••,----+I
_--4-----1--
D~7-------------+_--------~
1+--------T'K1, T...
---------t
WRITE
2xWCLK
TKQlDREQ
_____J ~T.QAK
8-137
.
)
82720·
WAVEFORMS (Continued)
DISPLAY AND RMW CYCLES (1X ZOOM)
RMW
DJepiayor AMW
Cycle
Cycle
2xWCLK:
DBIN:
ADO'HI
A1S, 17:
~~:~: ----~~r_------------~~r_------------------------------~_V-----
WEXT SYNC:
8-138
210655-002
intJ
82720
WAVEFORMS (Continued)
DISPLAY AND RMW CYCLES (2X ZOOM)
Zoomed Dlsplav
Cycle
Zoomed Display
Cycle
RMW
Cycle
Display or RMW
Cycle
51
2xWCLK:
i5iiiii:
ADO-15:
-~:2:o':li"::!"!:A'!l:"="D'---------~~o::'i"':!":!"~"~"::::'~--------t-<@o::!O"1::":!A~":::"':!:'>_-C!'!!1""::!,:!!o'~"J.-<:!:o'~"'::!':!!"$"~oo::!!"!:::":!"~":!!"!!l'f-
A16,17:
::~::::::::::::::::::::::::~)C::::::::::::::::::::::::t>c:::::::::::::::::::::::=+)C:::::::
Blank:
ZOOMED DISPLAY OPERATION WITH RMW CYCLE (3X ZOOM)
Display or RMW
Cycle
51
2xWCLK:
DBIN:
-+-----_____________________________+-________
..
~
..:>_
ADO·1S: -t-_-----------------------+_@o~o"1::":!A~"!:::".~.>_-C~:§~-<~!!!!!:!!)----------Ko§!o~"o:::,~,,~''':::
A16,17:~:x::::::::::::::::::::::::::::::::::::::4:c:::::::::::::::::::::::::::::::::::::=+x::::::::
Blank:
~~--------------------------------.(..r--------------------------------t'C::::=
"
210655-002
8-139
inter
82720
WAVEFORMS (Continued)
VIDEO SYNC SIGNALS TIMING
I'
'I
1H
2xWCLD:
.J"\.I"\./"\.r\ ____ ./\./'V\../V'-. __ J\..I'\f ___ J\../\.. __ f\.
HBLANK:
J
----'--- __ J
___________________J!
\~--------------------
HSYNC:
AOO-15:
LCO-4:
ADO-1S:
...A....._.r.----I'---_.....A.-_.A.....-_"-::::x:::::::::x::::: :x:=::::x:
:::::x
!\
f-~:=J- __ :: ______ =~:_-_-_-_-_~=~=:~:_-_-_~~==~~_-_-~
-----_~ -- J
:X:XXX:: __ :XX:
~ __ ~ __ )()()(JC ___________________________
--'.'-~
Row:
---v----:x:
___
___
,__________________ _ J \ _ __ _
----u------v-- _______
------------------------~
~
~
r
II-------------------------------------------------------------~
__________________1
____________________________ _
I
Row.
=*==±=x:::::::x=::x-----::::
1
VBLANK:
VSYNC:
'--- __ ________oJ!
f
==:::x::
-------'-
-r--------~-----------------------------------J!
:
1.---------------1V
..
(Fleld)-----------------i
INTERLACED VIDEO TIMING
HBLANK'
VBLANK:
VSYNC:
(Interlace)
.1L __ -1L.JL __ .JLn... __ .1LR. __ ..JL __ JL __ .JLJL __ JLJL_
I
I
I
1
I
I
I
I
I
I
I
I
I
I
I
"L __ ~---I------,----'_ __ ~---,--I----.-I-1--:
I
I
I
I
1
I
1
1
I
II
I
I
L...
1
-I·
O~d Field
Even F l e l d - - -I- - _
I
I
VSYNC:
(No Interlace)
8-140
210655-002
82720
WAVEFORMS (Continued)
VIDEO HORIZONTAL SYNC GENERATOR PARAMETERS
1~'---------------------lHI--------------------~
I
I
I
--,r
HBLANK:~
~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
I
I
I
:
HSYNC: __...;I~_....I!lL._____-+-__________________...iIL...I
I
I
-1
I
I
I
I
I
I
=-t
~HBP~_ _ A W " " " - - - - - - - I ' I
VIDEO VERTICAL SYNC GENERATOR PARAMETERS
~
__________________ 1V __________________
~
I
I
VBLANK: _ _---;_ _ _..,
I
I
I
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8-141
210655..()()2
inter
82720
VIDEO FIELD TIMING
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BLANK Output
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Vertical SYNC Lines
Vertical Back Porch Blanked Linea
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Front PorchBlanking
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DRAWING INTERVALS
~ Drawing Interval
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III Dynamic RAM Refresh If Enabled, Otherwise
III AddHional Drawing Interval
DMA REQUEST INTERVALS
!=;=:==:=::::=====t-
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8-142
InterVai,
210655-002
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'COMPONENTS SPEdAL '. :.'.;.
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• Capacitors • Precision reSIstors • $1:11....119
• Selecting electrolytlcs • Power MOSi=ET. ~r 8WltChers
ma.erlalS '
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The first chip dedic.ated to ..text. manipulation, the 82730 operates
as a coprocessor to .a host CPU anq exec(jtE?s many high-level
commands .that reduce th~ software ne~deq for processing text.
'
Tex:I"'~o;proce880r brlng~
. qualily 'toCRT displays
The quality qf text in
other chip, the 82720
raster-scanning CRT
graphics display controller, the device can
displays has' always'
been a tradeoff a,gainst
display high;~resolution
the complexity, perfor~raphi~s and. text lltthe
mance,and cost of the
sam~ tup,e:
;a$sociated video sysHoused in a 68-pin
,tern. By allocating
package;.the82730 text
maiw. of the complex
coprocessor coml;lines a
·.,display functions to'
direct memory access
. firmware; a e; . ICha;HJiJelAttentibnsigna:l,whichis implemented in
, '..• ,'e!\~~J1~ed. considetllbly Iwh~n:·.wot:ki.ng. with ,,~'he'. ' .hardw~r.!l.lrlreturn, the coprocessor setsa'fiag in
. 8~i'3lvideo .in~!!rfacecontroUer.4~ogefher theyprlF- .' I the shat~ltni~mory that notifies the hoshvhen it
'*ia~. pl;oportib'fi~l.$ea~ing', siin~1t~~eo.us sub~~dpt hasexec'uteJ:l.:the'comman,ret~l\da,ble ch.aracter fO,nts; and uS'er+progra~mllble" bre:;fk .dO\\;J'lJl'lto two grOups: .channel colhmands,
f~~d~)\Ild ~h~racter att:ibutes.},JY adding still a.nwhich wod~lJ.t the systenrlevel to start a_ndsto~ the
~I'ld to'c()rtlmunicate status and similar
,display
, ",'. ;:'~II8~. Bill_rail!, .~Qd\Jct. ~arketi"g en:grne6r
. i~fo~m!ition;and' da:fa~~tteaffi, cQmilll1.114s,: ~hich
"/:Al'Idr~"1' .voj~,.~r~lec* Man~erc, ' .
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'Intel Corp, . ..:.
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.3065 Bowers Ave:,:Santi.~lara, C(!i~,95051";
,.string~FP'goyernth<~ DMA;,proeess and'contt(lf ro~
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Text coprocessor
characteristics, character attributes, and so on.
The 82730 resides on a local system bus with the
host microprocessor, such as the 80186 CPU, and
therefore provides the' same address, data, and
control signals as the main processor. By handling
several of the tasks typically done by the host
processor-like DMA control and display
formatting-it leaves the host free for other tasks.
For example, when the coprocessor is configured
to share the CPU bus, a portion of the host microprocessor bus bandwidth" must be devoted to' the
DMA process that refreshes the CRT. However, the
82730's high-speed intelligent DMA controller
(operating at a maximum data rate of 4 Mbytes/s)
helps minimize the time spent executing the refresh operation, while simultaneously handling the
formatting of the display data. A different approach involves a dual-ported memory architecture, which places the memory between the CPU
and the coprocessor. That completely frees the
processor bus Qf the refresh activity, allowing the
host more time to execute other tasks. It has become
a more cost-effective method, as some dynamic
memory controllers now contain dual-ported arbitration logic on chip.
Inside the chip
The basic architecture of the coprocessor is divided into two main parts: a memory interface and
a display generator section (Fig. 1). The memory
interface lets the coprocessor and the system pro-
cessor communicate via the shared memory. The
display generator, in turn, responds to the data
provided by the memory interface and carries out
the display operations.
The memory interface actually comprises two
smaller subsectio~s, a bus -interface unit and a
microcontrollet url.it. The bus interface provides an
intelligent connection from the 82730 to the host
processor bus and also buffers the data transfer
requests from the microcontroller. Upon initialization, the bus interface can be programmed for 8or 16-bit data and 16- or 32-bit addresses. Furthermore, the host interface can be configured for 8- or
16-bit-wide data buses, making the coprocessor
compatible with 8- or 16-bit host processors, like
the 8088/80188 and the 8086/80186. Running at 8
MHz maximum in 16-bit systems, the 82730 handles
the maximum DMA rate of 4 Mbytes/s.
The microcontroller unit stores the microinstructions for the 82730's high-level operations.
The microcontroller's internal processor manages
the memory transfers, interprets the commands
embedded in the data stream, and executes those
commands by sending data to the appropriate control registers or display data buffers. To optimize
the transfer of data between the system and the
CRT interface, the coprocessor uses three clocksone for the host interface, the other two for video
data. The memory interface section runs from the
bus clock, the CRT interface operates from a reference and a character clock.
, Mlcrocontroller
uriit
1. Di~idedinto two main sections-a memory interface unit and adlspl.y g.iI.r.tor:....th.
82730 lext coprocessor can operate at optimum speed since each section can function
.
ind.pend.ntly at a different clock speed,
iH45
Although the coprocessor packs a consjderable
amount of processing power on a singl!! NMOS chip,
it cannot handle the high video dot rate needed to
deliver high character counts to the CRT display.
For that, it needs the 82731 video interface controller"which gains its high speed and drive capability
from bipolar technology. In addition, the combination of the 82730 and 82731 succeeds in reducing the
video interface to just a few latches ,and 'a software
character generator residing in RAM or ROM
(Fig. 2).
Inside the 82731 are the reference- and characterclock generators, a video shift register, and all
attribute logic (Fig. 3). Housed in a 40-pin package,
the circuit offers TTL-compatible inputs and outputs except far the video output, which is ECLcompatible and provides a dot-shift clock rate of 50
MHz ma,ximum on characters up to 16 dots wide.
The circuit proportionally spaces characters by
accepting the width sent from the character generator and sending an appropriate ,character-clock
output whose period determines the variable width
of the character to be displayed.
The video interface controller can employ an
inexpensive, low-frequency crystal and internally
multiply that frequency to generate the highfrequency dot clock. It also ,supports control functions such as screen reverse ~ideo, synchronized
character field, and tabbing operations. The dot
clock drives the internal video shift register, the
character clock controls the unloading of data from
the row buffers in the 82730;and the reference clock
establishes the raster and screen formats.' The
reference clock also supplies the basic timing for
the horizontal sync, blanking, border, and active
display time. The corresponding vertical
attributes-;-except border-are driven by the horizontal line time. All seven of these screen parame.:'
ters are programmable by the system designer with
the 82730.,
S,stem interfaces are aimple
As a coprocessor, the 82730 has the same buscontrol signals as an 80186 host processor and thus
can share the system-bus controllers, drivers, and
latches. The host processor and the 82730 arbitrate
for control of the local bus through the Hold and
Hold Acknowledge lines (HLD/HLDA). The Channel Attention (CA) and System Interrupt (~INT)
contr,ol lines complete the wired interface. With
this configuration, the 82730 has access to all the
memory that the 80186 CPU has available.
Anytime the CPU wants to send a message to the
82730, it writes the command and busy flag into the
82730 command block and then pulses the coprocessor's CA input to inform it that a message is
waiting. The 82730 then raises the HOLD output
and waits for access to the bus. When the C~U
relinquishes the bus, it raises the HLDA input of
the 82730.
'
, Once the 82730 becomes active, it transmits the
command block address that was stored in its
2. II. typical .,...m 'built eround the 82730 end the 82731 video Interface controller requires .,." few
additional IC, to mete with. holt ~r like the 80188. Onl, the ",tam but drlYere, lOme latchel, end
e cllerecter Pll,l"'etor _
needed.
,8-146
Text coprocessor
registers during initialization. That address, in
conjunction with the appropriate memory control
signals-including read or write strobes, lower or
upper address latch enables, upper address output,
or data enable output-will either read the command block or write to it. All these signals are
coordinated by the bus clock.
Whenever the 82730 must send status information to the host CPU, it gains control of the bus and
places the data into the status location in the
command block. The bus is then released and the
coprocessor notifies the CPU through the SINT
signal. When the coprocessor is using a dual-ported
memory to communicate with the 82730, the HOLD
and HLDA signals are not employed. Instead, the
82730 accesses the dual-ported memory directly
rather than acquiring the bus from the CPU.
When the dillplay process is activated, the coprocessor uses its built-in DMA capability to fetch
display data from the memory. The data consists of
character data mixed with data-stream commands;
embedded data-stream commands provide the flexibility to manipulate data on the fly.
SoH font. loaded
The 82730 also permits soft fonts to be automatically loaded into RAM-based character generators. Addresses and data stored in the system
memory are then loaded into the row buffers of the
coprocessor. During blanked rows (generally during
the vertical retrace), address irtformation is loaded
into a latch and data is written to the character
generator.
The 82730's dual row buffers help reduce the
bandwidth and access time requirements for the
system memory. The data stored in one buffer is
being t1sed to display a row on the screen while the
second buffer is being loaded, by the microcontroller, with the next display row from the
system memory. Up to 200 characters can be stored
and di~played by each row buffer. Furthermore,
since the display generator section operates asynchronously with the microcontroller unit, each can
operate at optimal speed. Processing is synchronized by internal flags and shared internal
storage, and .data that will be displayed is exchanged through the row buffers.
The coprocessor's display generator handles the
data that defines the timing and the operation of
the CRT interface. That qata, which is stored in the
display characteristics registers of the chip, controls every aspect of the display-from the screen's
format to the blink rates of the characters and
cursors. All the parameters that define the initial
display characteristics can be set by one
command-MODEST - thus reducing the time, and
3. The 82731 video interlllce controller is manufactured with
bipolar technology, enabling it to handle video dot rates of
50 MHz and higher, which are needed by high-charactereount displays. The controller serializes the parallel
character outputs from the. coprocessor and adds the
desired attributes to each character.
effort required to establish a screen format.
Beneath the simplicity of the hardware shown in
Fig. 2 are the high-level instructions-channel
commands-and the data-stream (!ommands. When
combined ~ith a table-driven linked-list data structure, they ease software development.
Central to the software is the command block,
through which all channel commands are transferred between the coprocessor and the host. This
block is located within the shared memory, and its
exact position is set during the 82730's initialization
routine (Fig. 3a). Once established, ,it contains all
the information needed to start the display-data
fetch; to communicate status, interrupt, and cursor
position information; and to give the location of the
mode block, which contains all the parameters for
setting up the display. The START DISPLAY channel
command begins the sequence (Fig. 3b). ,
Since the display data is set up within linked
lists, the'coprocessor can rapidly change any of the
lists without shifting huge amounts of data. The,
display fetch lltarts with the value of the list-switch
bit which selects one of two list-base pointers in the
command block. The pointer points to its string
pointer list; the pointers in that list direct the
on-chip DMA to the data strings containing the
!1esired display data R1.1d data-stream commands.
The programmer can modify one pointer list while
8-147
displaying from the other, and can also switch
screens merely by changing the list-switch bit, thus
eliminating time-critical data manipulations,
Two data-stream commands-End of String
(EOS) and End of Row (EOR)-are key to the linked
list and DMA activities, Strings are a logical concept: th,ey contain blocks of contiguous data stored
anywhere in memory. In contrast, rows are a physical concept and represent a block of characters
that make up a physical row on the screen. Many
strings can exist in a display row, or many rows in
a string. (Only the extra DMA overhead of fetching
the new string pointer sets a practical limit on the
number of strings in each row.)
The actions of the two commands are independent. 'End of String tells the 82730 to get the next
string pointer from the list, and from there, the
next data string. End of Row suspends the DMA .
until the row buffers are swapped at the end of the
current row. The DMA then takes over, into the
new row buffer.
String manipulation fosters high speed
Strings are commonly the next level of text
organization above single characters. With the
82730, a string can be as small 'as a character or it
can be a word, row, sentence, paragraph, or a page
of characters. These high-level entities can be
moved merely by manipulating a small string
pointer table (Fig. 5). The heart of the algorithm
for word wraparound, a common feature in text
processors, can easily be accommodated by a single
command such as the String Compare command of
the 80186. Word wraparound is then achieved by
scanning the data (not moving it) and manipulating
a few pointers. Earlier system designs would have
required a multiple-instruction software loop that
scanned and moved every individual character.
An extension of the linked list allows programmers to set up several independent data windows on the CRT screen in a virtual screen mode.
That feature is especially helpful if a user wants
both a menu window and one or more work-space
windows. Such a scheme saves a lot of time for the
end user-eliminating the back-and-forth movement between menus and working text. To set this
up, several data structures, each with its own
command block, can be accessed in a table-driven
sequence to put data in a given window on the
screen (Fig. 6).
, The string list and data strings are the same for
regular or virtual modes; only the structure of their'
command blocks differs. Thus, each virtual window
can be an independent software entity in the system, and the 82730 can present these independent
data bases simultaneously.
'
4. Both the h08t CPU and the coprocessor go through an
initialization aequence when the computer system. is reset
(a). The coprocessor then looks for a S.TART DISPLAY
command 80 that it can load the variou8 data 8tring8 from
the system memory into the di8play, generator section,
attach attribute., and display the data on the CRT (b).
8-148
Text coprocessor
Multiple 82730s can also be used in a single
system. Up to four devices can be clustered in a
single system, with one serving as a system master
and the others as slaves. The data for this cluster
can be interleaved, permitting the cluster to work
from one data base to get more characters per
screen or more bits per character. Also, in the slave
mode, the 82730's video outputs can be synchronized
to an external video signal, giving the system such
cap;:tbilities as mixed text and graphics, broadcast
subtitling (text overlay), and overlays for video
recording.
Attributes enhance display quality
The designers of the 82730 have given it the
ability to highlight various areas of an on-screen
document through the use of character and field
attributes. In the 16-bit data word, for example,
only the most significant bit is committed; it serves
as the command or data designator. If set to 1, the
word is a data-stream command, with the remaining 15 bits becoming one of the predefined instructions. However, if the MSB is 0, the other bits
are at the discretion of the designer, who may
choose which and how many are needed for charac-
ter codes, attributes, or user-defined functions.
The 82730's six predefined attributes-reverse
video, invisible, blinking character, two underlines,
and a special graphics character-can be programmed to respond to any of the 15 bits, or they
can be completely disabled. In addition, they can be
set character by character or through a fieldattribute mask. All can be attached to any charac.:
ter. The blinking cparacter can be programmed for
a wide range of duty cycles and blink rates. The two
underlines can be independently positioned anywhere in the row height, and the position can be
changed from row to row. Thus the underline can
be doubled or serve as a strike-through line, a
fraction line, or an overbar. One of the underlines
can also be programmed to blink at the same rate
as a blinking character.
The graphics character is relatively important,
since it permits character information to be displayed to the full height of the row. It causes the
chip's line-counter output to count from zero at the
top of the display row continuously through to the
bottom of the row. When used with special characters, this' attribute allows business forms and
• graphs to be easily constructed.
5. If a character or word must be In88rted near the beginning of a screen of text, only the
list pointers must be changed to add the item. In older 'ystam., all the character. fOlloWing
the inaertion or deletion were shifted In the memory to revise the display.
8-149
Text coprocessor
Another capability of th~ 82730 is subscript and
superscript characters, done by manipulating the
line-counter outputs. The SUB SUP N data-stream
command declares which and how many pairs of
characters' will bll displayed simultaneously as subscripts and supers~ripts.
.
Proportionally spaced displays could cause some
subscript and superscript characters to have different widths and thus disrupt the. vertical alignment
of a character pair. A special output of the 827~0
called Width Defeat prevents that misalignment by
causing the 82731 video interface controller to enforce a predefined width-programmed upon system initialization-during the display of subscript
and superscript characters.
The proportional spacing is performed by the
reference and the character clock. Used to shift out
the character and attribute data, the character
clock operates during the display field. Its frequency can vary character by character, up to a rate
of 10 MHz, to set the width of the character
currently being displayed. The video interface controller takes the character ·width information that
has been supplied by the character generator and
pr~duces a variable width character clock that
supports the proportional spacing. This approach
also greatly reduces system complexity and cost
I
compared with previous designs.
Scree,,' and row formate are flexible
The reference clock signal in a system that contains the 82730 and 82731 chips is a constantfrequency clock that forms the time base to generate the horizontal scan lines and vertical frame
periods. One scan line can last for 256 reference
clock periods, and one frame can contain up to 2~48
scan lines. Within these periods, the respective
synchronization pulses and the border and character fields can be set anywhere within that range.
All these timing relationships, including the scan
and frame periods, can be changed on a frame-byframe basis to suit changing applic/ltions.
The screen format is flexible all the way down to
the row level: For instance, the height of a row (up
to 32 scan lines) and the vertical position of the
characters within that row can be changed from
row to row by' a single data-stream command called
FULROWDESCRPT. In addition, the command lets
the programmer set the starting and ending scan
lines within the row for the normal, subscript, and
superscript character fields and the two cursors.
The same data-stream command that defines the
row characteristics can also be used to blank the
row, display it as reverse video, double its height
(for up to 64 scan lines per row), or eliminate the
proportional spacing.
Graphics, too, can be handled by the 82730, although fiex,ibility and resolution are not as high as
with the 82720 graphics display processor. Business
applications typically need graphics that are no
more complex' than two- or three-dimensional
charts or business forms. These formats can be
stored as special characters in a standard font set
for the character generator. Even more complex
graphics can be handled through the use of mosaic
graphic cells, which can be stored in RAM to perf!1it
alterations. Of course, as in most systems usmg
floppy-disk systems for main storage, the desired
fonts or graphics forms can be saved on the disks
and downloaded as needed for the display.
There are many applications that also require a
simple graphic display along with text-signature
.verification on bank~ng terminals and generalI?urpose credit verification, for example.o
8. The virtual window capability of the 82730 leta the UHr
arrange independent areaa in the s,atem memciry thld can
be displayed simultaneously on the CRT monitor.
8-150
intJ
ARTICLE
REPRINT
AR-296
Sepiember 1983
"Reprinted by permission of PC World from Volume 1, Issue 5, published at 555 De Haro Street, San FrancIsco,
CA 94107."
. -
"SubscriptIOn rates $24/yr PC World CirculatIOn Department. PO Box 6700, Bergenfield, NJ 07621
8-151
Order Number 230810-001
Something exciting is going on. But like most significant
events, it is not happening quickly. Spurred on by
developments in integrated circuit technology, a new
generation a/personal computers is taking shape, and the
IBM PC and its clones are at the/ore/rant.
National Semiconductor, and Zilog. Diverse chip dt(signs
mean that the system designs of the IBM PC and its
competitors, such as Apple's Lisa (based on the Motorola
6800 microprocessor), will also be radically different.
As IBM PC users, it's sometimes hard to remember that
the inanimate metal boxes in front of us are susceptible to
evolution. But occasionally·a product is introduced that
forces. the complete redesign of our personal computer~.
THE MICROPROCESSORS
Integrated circuits (I Cs), the devices that bring il!telligence
to our machines, have reached a new level of technological
achievement, and now the computers that use them must
advance as well. Strange as it seems, these small silicon
chips are setting the guidelines for the next generation of
personal computers.
Design of the PC was shaped by IBM's surprising selection
of the 8088. This choice caught 1110st industry observers off
guard since IBM, also the world's largest semiconductor
manufacturer, had traditionally used its own designs for
computer logic. Once Big Blue settled on the 8088, Intel's
design philosophy was firmly implanted in the PC-from
the 8088's segmented memory scheme to its l6-bit registers
and 8-bit bus.
Of the many Intel chips being produced, some will have a
greater impact on the computer industry than others. In
the vanguard will be the new microprocessors.
THE CHIP MAKERS
Like the 8088, each of the four microprocessors Intel is
. now readying for production could dramatically influence
the design and performance of tomorrow's PCs.
Now that personal computers have caught on, the semiconductor manufacturers who make ICs are eyeing the
swelling m,arket for personal computer ICs.
The 80186. The recipe for putting an entire central
processing unit (CPU) board on one chip is easy. Take an;
8086 (the 16-bit bus big brother of the 8088), speed it up,
and then add most ofthe support chips essential to making
the 8086 run in a personal computer. Reduce the size with
the help of computer-aided design until all the chips fit
onto one sliver of silicon, and voila, you have the 80186
(186), an entire motherboard on a chip.
Dozens of newly developed semiconductor chips are being
aimed at the personal computer market. These chips range
from hard disk controllers that speed access time to linear
predictive coding processors for speech recognition. With
these new ICs driving personal computer design, we11
'soon see machines we once only reasoned would exist:
diskless computers running a wide array of software
loaded over telephone lines; computers that display text
exactly as it will be printed, with justified margins,
superscripts and subscripts, and bold and italiC typefaces
on screen; and systems with greater, more accessible
graphics.
While firming up plans for full-scale production of the 186,
Intel is currently providing samples of the chip to computer
manufacturers, including MAD Computer and Durango
Systems. The rewards for using this newest chip are many:
manufacturing costs are cut since a single IC is less
expensive to buy than a boardful of them; physical CPU
size is reduced, opening the way to shrink overall computer
size or to put mare power in the same box; and development time is cut for computer designers, which means
considerable savings for system makers.
As computer design is simplified by these advanced ICs,
product differentiation will become greater. This portends
the death of those PC clones capable only of basic
spreadsheet and word processing operations. Instead, to
survive in the increasingly cost-competitive, standardized
personal computer market, small-system manufacturers
will tailor their products for niche markets.
BIG BLUE
Intel Corporation, located 'in Northern California's renowned Silicon Valley, is one of the largest and most
innovative chip manufacturers in the industry. IBM has
been committed to Intel products for years; the PC is built
around Intel's 8088 microprocessor and, as recently as late
1982, IBM invested $225 million in a minority share of
Intel stock. A commitment this size is a good indicator of
IBM's faith in Intel products. IBM's ,good faith and
multimillion-dollar investment is guaranteed by Intel's
long-standing promise that software writte':'! for the 8088
'will run on all its future processors.
The 80188. If the 186 is too rich for your ta~te, the 80188
(188) may be more suitable. As with the 186; the 188 's core
CPU and support chips are melded on a single IC; like the
8088, however, the 188 has an 8-bit interface to the outside
world (the 186 has a 16-bit interface). The 188 decreases
costs by allowing computer manufacturers to use less
expensive 8-bit peripherals. Although the 186 has received
more publicity so far, the 188, aimed squarely at the
massive 8-bit computer market, is expected to be used in
'
greater numbers, at least in the short term.
By taking a close look at the Intel ICs, we can gain valuable
insight into the capabilities of the IBM PCs that will be
built around them. The design philosophy of Intel's IC
family differs radically from that of competitors Motorola,
8-152
The 80286. Powerful multiuser systems will benefit the
most from the 80286 (286), possibly the most powerful
microprocesor commercially available to date. Squeezing
150,000 transistors on a chip, the 286's designers have
integrated a pair of HMOS-III (Intel's own proprietary
process technology) 8086s and numerous other very large
scale integration (VLSI) components. The resultant chip is
two to three times faster than the Motorola 68000 even
though both chips can address about the same amQunt of
memory. The 286 has very high speed (1.5 million instructions per second, five to six times faster than the 8086),
about 16 megabytes worth of addressable physical memory,
the ability to address a virtual memory of I gigabyte per
task (equal to the capacity of 100 IBM XT Winchester
drives), and the ability. to provide several layers of
muiltiuser security on chip.
Since the 188 is ideal for low-priced portable computers, it
ceates the ironic probability that a PC-compatible portable
may soon by available that will run the IBM PC's full line
of software and run it faster than the full-sized PC.
SOFTWARE ON SILICON
One chip ready to plug into the next generation of personal
computers is the 80150 (ISO) CPt M software-in-silicon
operating system. A complete CPt M-86 operating system
is stored in ROM on this chip, along with drivers for input
and output devices.
The 80386. Not yet built, the 80386 (386) is promised for
1984, but the release date may slide to 1985. If the 286 is
vastly more powerful than the. 8088 or 8086, then the 386 's
potential is staggering. Complementary metallic oxide
semiconductor(CMOS) process technology, which lowers
power consumption, is being used to build this 32-bit chip.
Intel, Motorola, and National Semiconductor are already
jockeying for position in what will be an intense competition for the 32-bit market. Motorola is claiming that its
68020 will be the first widely available 32-bit microprocessor when it is introduced later this year, although
NCR has already scooped the industry with its 32-bit chip.
Hewlett-Packard, not to be outdone, has put 450,000
transistors on a single proprietary 32-bit microprocessor,
which is used in the $20,000 to $30,000 HP 9000 work
station.
Use of alSO CPt M chip will eliminate the traditional
booting up procedure ofloading an operating system disk
and reading its contents into operating RAM. Instead, the
user will simply turn on the computer and press a CPt M86 button. Again and more importantly, this chip lowers
overall computer production costs since a disk drive and
attendant control circuits are replaced by a solitary chip.
Another chip, similar to the ISO, has Intel's proprietary
RMX C!perating system in silicon. This little-known RMX
chip is also suitable for present and future IBM PCs.
Many people question the wisdom of putting software in
silicon. "Software should be soft," says Bill Gates, chairman of the board at Microsoft. He points out that
operating systems are constantly updated; for instance,
Microsoft will soon offer a revised version of MS-DOS
that supports networking. Such updates can't readily be
added to.a hardware production line and certainly won't
help the ROM chips already in users' computers.
How will these processors impact the personal computers
that use them? The most obvious effect will be faster
performance. Even the budget model 188 boasts two to
five times the instruction and execution speed of the 8088
in today's PC. A 286 is about twice again as fast as the 188,
and next year's data-gobbling 386 will have more speed
than anyone can immediately.use.
r
I
I
---- - - - -8088
PROGRAM
MEMORY
Or
8086
CLOCK
OATA
MEMORY
I
I
8384A
CLOCK
DRIVER
ROY
INTEARUPT
STATUS
INTERRUPT
STATUS
I
I
I
I
INT.EARUp,T
80150
CLOCK
REQUESTS
I
ACKNOWLEDGE
_
L..8AUDRATE
TIMER
DELAY
TIMER
SYSTEM
I~
.J
iAPX 86/50. 88/50
TIMER
BLOCK DIAGRAM OF INTEL'S 80150 CP/M O!ll A CHIP WITH THE 8088 OR 8086 MICROPROCESSOR
8-153
V'.
j,
Still, Ii1telargd~ 'tliat its choice of CPt M makes the' ISO,
practical. "We picked' CP/M ,because it is a mature
operating system," Says Intol's prodllct'marketng engineer
for software on silicon, Carl Buck. "We'd have more
difficulty with a less developed product." The many
versions of MS-DOS helped eliminate that operating
system from considOratlon! Yet aecording'to Digital
Research President John Rowley, Intel left some room on
th~ ISO chip ttl, add to' CPI,M in:
the futu~.
,
Also, use oithe 150 CP/M chip doesn't preclude the use of
other operating systems.' PC-DOS could still be loaded
into a system and run, making use of the ISO's input/ output
drivers.
PORTABLES
Having software on silicon opens the way for very
powerful diskless portable computers. The minimum
configuration for a 188-based unit with .the ISO CPlM
operating systerp could include one or two BASIC
applications programs in 'ROM, providing spreadsheet
and word processing power in a unit the size of a: keyboard
with
small' flip-up screen. Intel Product Marketing
Engineer Tony Zingale suggests we may soon see truly
uSlJble portables selling for around $500.
a
More ambitious and expensive portables could accept
applications software over telephone lines, loading them
into a variety of media: ~everal memory technologies will
compete for r,oom in portable computers, including magnetic bubble memories, already being used in the Grid and
Teleram computers. Commercially available bubbles have
4 megabit capacity, while 10- to 16-megabit bubbles are
projected for the near future. Japan's NEC reported a
major breakthrough that within 5 years will allow bubbles
to store I gigabit of data. Of course, 8 of those bits are
needed to store I byte of data.
'
Vying with bubbles in some applications and complementing them in others are electronically programmable
read-only memories, or EPROMs. Like'ROM, EPROMs
are nonvolatile chips. Unlike ROM, EPROMs can be
reprogrammed. Intel now offers 2S6K EPROMs, ilnd it is
anticipated that other companies will offer 256K EPROMs
before the year's end.
GRAPHICS
The space created on tlte motherboard by the 186 and
friends will enable computer designers to add more
graphics capability to their systems., Like the ISO there are
co-processor chips ready for ~he task.
A pair of Intel Ies, the 82720 (720)1 graphics display
controller and the' 82730 (730) text co-processor, are
touted as providing vastly enhanced arid simplified dis, plaY$. With the 730, text can be displayed on the computer
screen as it will be-printed out. Italics can be mixed with
st~i~t ,text, and sup!l~scrip~\IIn,d subscripts ar1;l shown
without the annoying and often misleading arrows
common in today's software.
Editing tan be speeded up by the 730's support for split
sereens, multiple windows;dual cursors, smooth scrolling,
and table-driven linked lists. 'Displays of up to 200
characters per row and 128 lines per 'screen '. ~an be
supported, and unique character ,sets, such as Arabic or
Japanese, can be built.
Even more capability can be added thoiIgh the 720, an IC
that works with or without the 730. Introduced in
- September 1982, the 720, joint effort between Intel and
NEC, is said to be integral to graphics plans for NEC's
, 8086-based Advanced Personal Com'puter.
a
One application in which the 720 and 730 will shine is
opening windows on-screen. Most computer users are
familiar with the ability of Apple's Lisa to link spreadsheets, graphics, and word processing through multiple
displays, or windows, on one SCreen. Lisa uses memoryhungry software and dedicated hardwa,re. Apple's initial
release uses I full megabyte of RAM, and Lisa will soon be
offered with 4M of internal memory in addition to a
mandatory SM hard disk.
For comparison, the IBM PC, limited by the range of the
8088, can address 1M tops. VisiCorp's Visi/ ON promises
Lisa-like' graphics and program-linking capabilities for the
IBM PC, with lower memory demands and no dedicated
hardware other than a mouSe, Although Visa/ ON supposedly runs faster with an 8087 math co-processor,
VisiCorp will not comment on wlrether its software will
make use of the 720 or the 730.
BIT-MAPPED GRAPHICS
Both Lisa and Visa/ ON use bit-mapping, a process that
the 720 and the 730 are said to simplify. In plain words, to
create an image on-screen, the electron gun that illuminates the screen must be positioned and then turned on
and off. Data to do this is stored in RAM as a bit-map
memory corresponding to positions of pixels lit on the,
screen. For one-level monochrome displays, I memory bit
describes each pixel; for color and levels of grey, several
bits must be used to describe each pixel.
Creating images is a lengthy chain of simple operations. In
a system that uses the 8088 alone, the microprocessor is
heavily burdened and the software runs slowly. Using
complementary chips to take up part of the processing
chore will speed up the process considerably. This is where
the 720 and the 730 come in By doing tasks such as looking
up and manipUlating a library of commonly used figures,
quickly accessing the bit-map memory, and rewriting the
bit map, both chips speed text and graphics operations.
FLAT VS. SEGMENTED
, MEMORY
Use of the 720 and the 730 demonstrates Intel's design
philosophy and how this philosophy impacts the IBM PC.
Computers such al,Lisa that are based on the Motorola
68000 have a fiat lfiemory, while computers based on the
8088 or 8086 use segmented memory. According to Intel,
8-154
segmented memory (see "How the PC thinks," PC World.
Vol. I, No. I) works better for text and graphics manipulation than its flat counterpart. Ordinarily in processing
any string of characters, changing a single letter in a string
of text means repositioning every character in a document.
But since segmentation uses pointers io locate data in
memory, only the pointers locating the beginning and the
end of a passage of text have to be changed. Similarly,
pointers in memory can be used to position bit-map data
corresponding to mUltiple windows on-screen, eliminating
the need to recalculate and manipulate the entire bit map.
Segmented vs. flat memory has become somewhat of a
religious issue in the semiconductor industry.
Intel and Motorola also differ on how much burden to put
on the CPU. Motorola's 68000 is faster than the 8088 and
the 8086 and can address more memory than either of
those chips or the 188 or the 186. But the 186 and the 286
are substantially faster than the 68000. Also, the 286's
ability to address 16M opens the way to using large
memory segments, strengthening Intel's case for segmented, memory.
In many 68000-based high-end systems the computer
designers have decided to use a co-processor, either bit
slice, or in one case, an 8086, to do graphics. Many people
are skeptical of Intel's graphics approach, but Intel
maintains that its approach will allow computer designers
greater flexibility. In an ultimate system, mUltiple 720s and
730s could be combined to handle interactive windows
under, the direction of a 286 processor, while more
complex imagery (beyond the practical ability of bitmapping) could be managed by an 80287 math coprocessor, the next generation cousin of the 8087. The
creation of three-dimensional graphics tha t can be rotated
on screen foradvancedcomputer-aided design and manufacturing
systems,'for instance, is ,best handled by Vector Graphics
rather than bit-mapping.
8-155
SOFTWARE DEMANDS
Yet there is more to computer design than hardware.
Software must be written to take advantage of the new
IC's promise. In the case of the 286, no operating system
yet exists that can take full advantage of its operating
capabilities. Plug-ins currently on the market that add the
286 to the IBM PC provide little more than a faster 8086.
Only riew operating software will use the new chips to their
fullest potential.
One SOlution on the horizon is a 286 version of XENIX
due to be introduced mid-1983. XENIX, a multiuser
operating system with a visual shell similar to MS-DOS, is
a takeoff on Bell Labs' UNIX operating system. A
licensing agreement ~mong Intel, Bell Labs, and Microsoft,
the author of XENIX and MS-DOS, is reported being
negotiated. Negotiations between Intel and Digital Research to provide a CPI M variant for the 286 have been
underway for some time but have reportedly stagnated.
For lower-end systems Microsoft is said to be upgrading
MS-DOS to accommodate networking. This advance
comes at the right time, as the 188 and 186 open liP sockets
that could be used for local area network chips such as the
programmable Ethernet chip from 'Intel.
As long as software and hardware keep growing rapidly
together, PC users will be offered a continuing stream of
improved computers and ever more capable plug-in
boards. The variety seems endless and next year's crop
exciting.
'
intJ
ARTICLE
REPRINT
AR-297
\
PROCESSING'
VLSI Coprocessor
Delivers High Quality Displays
Many microprocessor-based systems
today use VLSI technology in processing and memory components.
However, designers of subsystems
have, up until now, not been able to
incorporate this technology into
their products because of the lack of
available ICs. When, in 1981, NEC
introduced the 7220 graphics display
controller, users found that they
could bolster system performance
by off-loading graphics control
chores from the system CPU. Second-sourced by Intel as the 82720,
the chip uses its own drawing
processor to access the required
positions in' the bitmap and handles ·both processing and display
!
functions.
Now, Intel is poised to introduce
a text coprocessor, the 82730, which
is specifically tailored to execute
data manipulation and display tasks.
Lucio Lanza of Intel explains, "In
an intelligent terminal or workstation, the CPU spends a lot of its
time manipulating both graphics
and text. We have identified these
areas in terms of CPU use and we
have distributed these blocks so that
the CPU is not overburdened."
Coprocessors fall into two cate-
gories based on their architecture
and operation. One type expands
the microprocessor's own architecture by adding .additional hardware
and instructions. This type of tightly coupled coprocessor can be
thought of as a transparent expansion of the microprocessor's architecture and works in sychronization
with the CPU. Intel's first such coprocessor, the 8087, was designed
Bus controls
for numerics processing and increased the microprocessor's math
performance as much as 100 times.
The second type of coprocessor
independently fetches its own data
and sends instructions in parallel to
the microprocessor. It therefore allows the microprocessor to process
the tasks it handles best and delegate to the coprocessor the task it is
best equipped to handle. In this cate-
ADO·AD15
Char
data
Video
controls
I
Memory Interface Unit .....--1 ----+- Display generator
Andrew Wilson
Technical Editor
FIGURE 1: Block diagram of the 82730.
Reprinted from ELECTRONIC IMAGING © April 1983, Morgan.Grampian Publishing.Company, Boston, MA 02215
50
8-156
ElectroniC Imaging
0
April 1983
gory are 110 channel coprocessors
and others that deal with communications and text processing tasks.
"The 82720 is not yet at this level," Lanza said, "since it does not
have the capability of going to memory and extracting its own instruction and executing it-it needs
something to spoon feed it."
Coprocessors of the second category do not monitor the CPU instruction stream. Instead, they are
linked to the CPU via messages prepared and stored in shared memory.
The CPU will prepare data and high
level directives and then place them
in memory. Upon completion of this
control block, the CPU will alert the
coprocessor by signaling it through a
common channel attention line.
From that point on, the coprocessor
works on its own, fetching required
data and instructions and then executing those instructions.
Jt is not synchronized with the
CPU but works asynchronously and
independently. When the coprocessor completes its task, it informs the
CPU by signaling on the CPU's interrupt line.
The rationaJe for designing a coprocessor with one or the other architectures depends on the application requirement. Tightly coupling
the coprocessor with the CPU gives
the advantage of a short coprocessor
preparation time but has the drawback of consuming the CPU's bus
\
bandwidth.
In the case of numeric processing, the speed of executing the floating point algorithm is of paramount
importance. Reducing the preparation time of the coprocessor task is
the key because of the number of
microseconds it takes to execute the
task. Rapid algorithmic execution
requires tight coupling. In the application of the lIO related coprocessor,
the task execution time is much
longer and the requirement for bus
time can be much higher. And, for
I/O operations the preparation time
is not critical. A shared memory
52
FIGURE 2: Building block approach.
coupling is preferred for those types
of applications because it provides
greater flexibility in the design of
the bus structure.
Text coprocessing
"In the design of the 82730," said
Lanza, "we have tried to eliminate
all the known differences between
what is. visible on the screen and
what is obtained' on the printed
page. In word processing systems today, even the length of a row on the
CRT is sometimes not the same as
the length seen in print. Clearly,
when you are editing text this. becomes a major problem."
The 82730 supports the generation of text displays through features
which include proportional spacing,
simultaneous superscript/subscript,
dynamically reloadable fonts and
user programmable field and character attributes. Editing c.apabilities
are further enhanced by features
such as split screen, virtual windows, smooth scrolling and tabledriven linked lists.
Figure 1 shows a block diagram
of the 82730. The chip is divided
into two main sections-the memory interface unit and the display
generator. The memory interface
unit provides' the communication
between the 82730 and the system
processor, while the display generator acts on the display data and
ries out the display operation.
Comll1unication between the
82730 and the CPU takes place
through messages placed in communication blocks in shared memory.
The processor issues channel com-
ear-
8-157
mands by preparing these message
blocks and directing the 82730's attention to them by activating a hardware channel attention signal (CA).
The memory interface unit fetches
and executes these commands.
When the display process is activated, the 82730 repeatedly fetches display data and embedded datastream
commands from memory utilizing
its built-in DMA capability, executes any datastream commands as
encountered on the fly,. and loads the
row buffers with the display data.
After executing these commands,
the 82730 clears a busy flag in memory, to inform the host CPU that it
is ready for the next command .
. The memory interface unit is divided into two sections-the bus'
unit and the microcontroller unit.
The bus interface unit provides the
electrical interface to the system
bus and the timing signals required
for the microcontroller unit operations, making these operation~
transparent to the microcontroller
unit. The 82730 can be programmed
during initialization to provide 8 or
16 bit data, and 16 or 32 bit
addressing.
The microcontroller unit contains
the microinstruction store and the
associated circuitry required for the
execution of all channel and datastream commands. It uses the bus
interface unit in carrying out its
memory access tasks such as loading
the row buffers with display data.
The interaction· between the microcontroller unit and 'the display
generator takes place through Shared
internal storage. The microconElectroniC ImagIng
0
April 1 983
"The device provides the ability
to independently maximize the
performance of the CPU."
troller unit fetches data from memory and writes it in the internal storage, while the display generator
reads from the internal storage and
carries out the display operation.
The microcontroller unit and display
generator operate asynchronously
with respect to each other. Synchronization is accomplished through
communication via internal flags
and display timing signals generated
by the display generator. The internal shared storage consists of row
buffers which store the display data
and internal registers which store
display parameters. There are two
row buffers each capable of storing
up to 200 characters. The data in
one row buffer is used by the display generator to display one complete character row on the screen,
while the microcontoller unit is
loading the second row buffer with
display data fetched from memory.
At the end of the row being displayed, the buffers are swapped and
the microcontroller ,unit and display
generator resume their tasks.
The display characteristics registers contain all the information used
to 'control every aspect of display
characteristics from screen size to
blink rates. A major. portion of this
register set is the three content
addressable memory (CAM) arrays
that allow flexible timing control for
row and screen characteristics. The
user has the power to set the parameters for the entire screen by invoking a single high-level command.
By separating the video interface
clocks from the bus interface clock,
the 82730 provides the designer with
the ability to independently maximiz~ the. performance of the CPU
and video sections of the system.
The video interface consists of
two independent clocks: the Reference Clock (RCLK) and the Charac~
ter Clock (CCLK). While the
RCLK controls the raster timing
and defines the screen layout, the
CCLK independently shifts character and attribute information out of
the 82730, which allows proportional spacing to be achieved.
Combining
t~xt
and graphics
A major requirement in the design
of engineering workstations is the simultaneous display of both text and
graphics. In terms of graphics requirements, the designer of such
systems' needs a drawing processor
for fast geometric primitives, a math
processor for' fast transformations
and a general purpose processor for
access to the graphics database.
For text, string processing is
needed for manipulation of text primitives and database processing is
needed for access to the document
files: The solution to this problem
can be solved by using both the 720
graphics coprocessor and the 730
text coprocessor (Figure 2).
Both coprocessors work with Intel's new 82586 communications coprocessor. This works in conjunction with a CPU and the appropriate
software to provide local area network (LAN) control capabilities.
Message data to be placed on the
network by a microprocessor-based
work station is stored in shared
memory in transmit blocks. Pointers
(starting address information) to
these blocks are stored along with
processing instructions in other
shared memory blocks, Status information and overall directives are
stored in system control blocks
which serve as the mailbox between
the CPU and the 82586.
When alerted by a ch,mnel attention signal, the 82586 will perform a
host of tasks involved in accessing
data to be transmitted from its location in memory, framing the message packets containing the data and
seeing to the transmission on the
network medium. In a.ddition, the
112586 receives and buffers incoming
dina which it then stores in shared
memory for the CPU to collect: It is
the CPU's job to allocate the blocks
of memory for the LAN coprocessor
to store the receIved packer-data. IiiI
8-158
ElectronIC Imaging
0
AprIl 1 9as
intJ
82730
TEXT COPROCESSOR
•
•
High Quality Display for Text
Applications
Provides Proportional Spa~ing,
Alphamosalc Graphics, Simultaneous
Superscript/Subscript and Soft Font
Support
•
High Performance Text Manipulation
provided by 4 Mbytes/sec DMA and
on-chlp Dual Row Buffers (up to
200 characters each)
•
Programmable Bus Interface Handles
8 or 16 Bit Data and 16 or 32 Bit
Addressing; iAPX 8618811861188
Compatible
On·Chip Processing Unit Simplifies
Software Design by Executing High
Level Commands and Supporting
Linked List Data Structures
•
•
•
•
•
•
Extremely Flexible; Programmable
Features Include Screen and Row For·
mats, Two Cursors, Character and
Field Attributes and.Smooth Scrolling
Simultaneous Display of Independent
Data B,ases Through Programmable
Virtual Screen Mode
High Resolution Display; Up to 200
Characters per Rowand 2048 Scan
Lines per Frame
Separate Bus and Video Clocks Allow
Optimization of Overall System
Performance
Provides Ii Complete LSI Solution for
Display Control when Used in Conjunc·
tion with the 82731 Video Interface
Controller
The 82730 Text Coprocessor is a high performance VLSI ~olution for raster scan text oriented displays. The
82730 works as a coprocessor and has processing capabiljties specifically tailored to execute data
manipulation and display tasks. It provides the designer the ability to functionally partition his system
thereby offloading the system CPU and achieving maximum performance through concurren't processing.
The 82730 supports the generation of high quality text displays through features'like proportional spacing,
simultaneous superscript/subscript, ~ynamically reloadable fonts and user programmable field and character attributes. An intelligent system interface and efficient software capabilities makes 82730 based
systems easy to design. In addition, when coupled with the 82720 Graphics Display Controller, the 82730
provides flexible mixing of high quality text and graphics simultaneously on the same display.
BUS CONTROLS
AD.D-AD15
CHAR
DATA
MICROCONTROLLER
UNIT
1_-+_••1
DISPLAY
CHARACTERISTICS
REGISTERS
SINT
MEMORY INTERFACE UNIT
DISPLAY
GENERATOR
CONTROL
VIDEO
CONTROLS
_ 1 _ DISPLAY GENERATOR
Figure 1. 82730 Block Diagram
Intel Corporation Assumes No Responsibility for the Use of Any Circuitry O1her Than CircUItry Embodied in an Intel Product, No Other Circuit
Patent Licenses are Implied,
NOVEMBER 1983
©INTELCORPORATION,1983
OROER NUMBER: 2100924-002
8-159
"n+_I®
III-e
. 82730
BOTTOM
CA
SO
51
CRVV
BLANK
CHOLD
LPEN
RRVV
VSYNC
CSYNC
CCLK
VSS
RCLK
SYNCJN
HSYNC
LC4
LC3
LC2
LC1
"
READY
SINT
IRST
RESET
BCLK
Vss
ALE
RD
WR
HLDA
HOLD
DEN
AEN
UALE
..
LCO
PIN NO.1 MARK
Figure 2. 82730 Pinout Diagram
Table 1~ 82730 Pin Description
The 82730 is packaged in a 68 pin JEDEC Type A ceramic package.
Symbol
Pin Number
Type
Name and Function
1-8
10-17
1/0
Address Data Bus; these lines output the time
multiplexed address (TU, T1 states) and data (T2, T3,
T4 and TW) bus. The bus is active HIGH and floats to
3·state OFF when the 82730 is not driving the bus (I.e.
HOLD is not active or when HOLD is active but not
acknowledged, or when RESET is active).
BCLK
59
I
Bus clock; provides the basic timing for the Memory
Interface Unit.
RD
62
0
Read strobe; indicates that the 82730 is performing a
memory read cycle on the bus. RD is active low forT2,
T3 and TW of any read cycle and is guaranteed to reo
main high in T2 until the address is removed froin the
bus. RD is active low and floats to 3·state OFF when
82730 is not driving the bus. RD will return high before
entering the float state and will not glitch low when
entering or leaving float.
AD15-ADO
~
8-160
210921-002
, ,
82730
Tabla 1. 82730 Pin Datcrlptlon (Continued)
Sy.mbol
WR
Pin Number
·63
,
lYpa
Nama and Function
0
Write strobe; indicates that the data on the bus is to
be written in a memory device. WR is active for T2, T3
and TW of any write cycle. It is active LOW and floats
when 82730 is not driving the bus. WR will return high
before entering the float state and will not glitch low
when entering or leaving float.
,
ALE
61
0
Lower Address Latch Enable; provided by the 82730
to latch the address into an external address latch
such as 8282/8283 (active HIGH). Addresses a~e
guaranteed to be valid on the trailing edge of ALE.
UALE
68
0
Upper Address Latch Enable; it is similar to ALE
except that it occurs in upper address output cycle
(TU).
AEN
67
0
Address Enable; AEN is active LOW during the entire
period when 82730 is driving the bus. It can be used to
unfloat the outputs of the Upper and Lower Address
latches.
DEN
66'
0
Data enable; provided as a data bus transceiver out·
put enable for transceivers like the 8286/8287. 15m is
active LOW during each bus cycle and floats when
82730 is n'ot driving the bus. DEN will not glitch when
. entering or leaving the float state.
53,54
0
Status pins; encoded to provide bus·transaction
information:
SO, S1
I
51
SO
Bus Cycle initiated
0
0
1
1
0
1
0
1
- - - (Reserved)
Memory Read
Memory Write
Passive (No bus cycle)
These'pins are directly compatible with iAPX 86,186
status outputs 51 and SO. The status pins are floated
when 82730 is not driving the bus. They will not glitch
when entering or leaving the 3·state condition.
READY
55
I
READY; signal to inform the 82730 that the data
transfer can be completed. Immedi~tely after RESET,
READY is asynchronous (internally synchronized)
but can be programmed during initialization to bus
, synchronous.
8-161
210921'()02
"nt_Ie
'III-e-
8273()
Table 1. 82730 Pin i)eacrtptfon(Contlnued)
Symbol
Pin NWmber
HOLD
65
HLDA
64
'
,
TYpe
Name and ,Function
'
b
, ,
CA
, 52
,;
,.,j
(
HOLD; indicates that the 82730 'wants bus access.
HOLD stays a:ctlve HIGH during the entire period
when 82730 is driving the bus.
I
Hold, Acknowledge; Indicates to 82730 that it is
granted the bus access as requested. HLDA may be
asyn«::hronous to 82730 clock. If HLDA goes inac.uve
(LOW) in the middle of an 82730 bus cycle, the 8~730
will cOmplete the current bus cycle first, then it will
drop HOLD and float address and bus control
outputs.
I
Channel Attention; used to notify 82730 that a com·
mand in the command block is waiting to be proc-,
,essed. CA is latched on Its falling edge.
"
SINT
56
0
Status Interrupt; used to inform the processor that an
unmasked interrupt, has been generated in the 82730
status register.
IRST
' 57
I
Interrupt Reset; SINT is cleared by activating the
IRST pin.
RESET
58
I
Reset; causes 82730 to immediately t'ermlnate its
present activity and enter a dormant state. The signal
must be active HIGH for at least 4 BCLK cycles and is
internally synchronized to the bus clock.
CCLK
27
I
Character dlock; input used to clock row buffer data,
attribute, cursor and line count out of 82730. When
more than one 82730 is connected in cluster mode,
CCLK is, used to synchronize ,output from both
master and slave chips. A character data word will be
output at every rising edge of CCLK.
I
Reference clock; input used to generate timings for
the screen layout and to define screen columns for
data formatting. All raster output signals are
specifi~d relative to the rising edge of RCLK.
0
Video data bus output; the least significant 15 bits of
,the character data words are passed through the
827:30 row buffer and made available on the pins
OATO-DAT14. The user has the flexibility to partition
the data word into character and attribute bits per his
requirements. 1'he bits that are assigned for internally generated attributes may also be available at
pin DATO-D~T14. New character data will be shifted
to·these output pins at every rising edge of the CCLK.
Together with LCO-LC4, they may be used to add,ress
the character generator or as attribute controls.
"
RCLK
25
DATO-DAT14
36-42
~4-51
,
,
,
"
I
8..;162
210921-002
82730
Table 1. 82730 Pin Description (Continued)
Symbol
WDEF
LCO-LC4
Pin Number
Type
Name and Function
35
0
Width Defeat; is used to indicate when the character
is allowed to be a variable width or must be of fixed
width. WDEF is LOW if the character being output is
normal, but is HIGH if it is a superscript/subscript
character or visible attribute (TAB or GPA). Option-'
ally, WDEF can be held high by user command.
18-22
0
Line count outputs; used ,to address the character
for the line positions in a row. The line
number output is a function of the display mode and
character attributes programmed by the user.
g~nerator
CSYNC
28
0
CCLK synchronization output; used to synchronize
external character clock generator to reference clock
timing. This output is active (high) outside the display
field.
CHOLD
32
0
CCLKlnhibit output; used by external logic to inhibit
CCLK generation. This output is active (low) during
the tab and end-of-row fl,lnction.
SYNCIN
24
I
23
o (MASTER)
,
I
HSYNC
I (SLAVE)
Synchronization input; used to synchronize the vertical timing counters to an externally generated
VSYNC signal. Used by slave mode 82730 to synchronize to a master mode 82730 and by the master
82730 to lock the frame to an external source such as
the power li('le frequency.
Horizontal Sync; in master mode, it is used to generate the CRT monitor's horizontal sync signal. It is
active HIGH during the programmed horizontal sync
interval. In interlace slave mode it is used in conjunction with SYNCINto indicate the start of the even
field for timing counter reset. At RESET, ~in is set as
an output in the LOW state .
. VSYNC
29
0
Vertical Sync; active HIGH during the programmed
vertical sync interval[and used to generate the CRT
monitor's vertical sync Signal.
BLANK
33
0
Blanking output; used to suppress the video signal to
the CRT. BLANK is clocked by CCLK.
CRVV
34
0
Character Reverse Video (CCLK output); used to externally invert video data output. CRVV is clocked by
CCLK.
RRVV
30
0
Reference Reverse Video (RCLK output); to externally invert video in the field and border area if so programmed by user. It is LOW outside the border area,
RRVV is clocked by RCLK.
8-163
210921-002
82730
Table 1. 82730 Pin Description (Continued)
Symbol
Pin Number
. Type
Name and Function
31
I
Light Pen Input; used to latch the position of a light
pen. At the rising edge of this inpu~, the column position and the row position of the 82730 will be loaded
into the LPENROW and LPENCOL locations in the
Command block.
LPEN
Vce
9,43
Power; + 5 volts nominal potential.
Vss
26,60
Power; ground potential.
FUNCTIONAL DESCRIPTION
operation to the one in the 8275 CRT controller).
The row buff~rs allow the userto use cheaper and
slower main memory for display needs, provide
on-chip attribute ana display function generation, and avoid the conflict of access to the display memory (that would otherwise take place)
by using an ordinary DMA access mechanism.
Figure' 1 shows a basic block diagram of the
82730 Text Coprocessor. The chip is divided into
two main sections, the Memory Interface Unit and
the Display Generator. The Memory Interface
Unit controls. fetching of the.data and commands
and handles interrupts and status. The Display
Generator takes the data fetched by the Memory
Interface Unit and presents iHo the Video Interface
logic which in turn drives the CRT monitor.
SYSTEM BUS INTERFACE
MemorY Interface Unit
The Memory Interface Unit is divided into two
sections: the Bus Interface Unit and the Microcontroller Unit. The Bus Interface Unit does the
actual interfacing to the memorybus.lt fetches or
writes data under the control of the Microcontroller Unit. The Microcontroller Unit is a microprogrammed controller which is designed to efficiently fetch data from memory (up to 4
Mbytes/sec), and decode and execute various
control and data handling commands. The Bus
Interface Unit may be configured for 8 or 16 bit
bus operation. With 8 bit bus selection, the user
may specify either 8 or 16 bit character data. It
also handles address manipulation automatically
after being loaded from the Microcontrolier Unit.
Display Generator
•
The Display Generator takes the data fetched
from memory plus the modes programmed into it
at initialization and produces alk the video timing
and the data transfers to support/the CRT monitor
at the character level. The 82730 works with an
external character generator and the 82731 Video
Interface Controller,. The data is passed to the
Display Generator from the Memory Interface
Unit through the dual row buffers (Similar in
The Memory Interface Unit provides communication with system processor as well as memory
interactions. Communication between the processor and the 82730 is performed via messages
placed in communication blocks in shared
memory. The processor can issue commands by
preparing message blocks and directing the
82730's attention to them by asserting a hardware
channel attention. The 82730 can cause interrupts on certain conditions, if enabled by tile proce,ssor by activating its System Interrupt output,
with status and error reporting taking place
through the communication block in memory.
BUS INTERFACE UNIT:
The 82730 Bus Interface Unit provides an 8086
compatible bus interface which consists of:
a 16/32 bit multiplexed Address/Data Bus:
ADo - AD15
A complete set of local bus control.§l.gnals
comp~le with 8086 min mode:RD, WR,
ALE, DEN and READY
Two stat!Js signals SO and S1. compatibl.e
with 8086 max mode so that a bus c,ontroller (8288) can be shared for Multibus®
access.
Local bus arbitration through HOLD! HLDA
Two .Ylmer Address Latch controls: UALE
and AEN
8-164
210921-002
inter
82730
The BUS INTERFACE UNIT (BIU) utilizes the same
Bus structure as the 80186 or basically the same
bus structure as the 8086 in both Min. and Max.
mode, (with the-exception of RQ/GT) and it performs a bus cycle only on demand (e.g., to fetch a
command from the command block, or fetch a
character from display data memory). The same
set of T-states (T1, T2, T3, T4and TW) of 8086 are
. used to handle the time multiplexed address/data
bus. However, adaptations are made to handle 32
bit addresses as explained in the following sections where specific details of the BIU opeJation
are described. Those details not mentioned can
be assu med to be the same as those of the 80186.
ADDRESS BUS
during addre~lculation. UALE always stays
inactive, but AEN still goes active to indicate the
82730 has control of the bus.
DATA BUS
The 82730 is capable of operating on either an 8
bit or a 16 bit Data bus, as programmed during
initialization on the SYSBUS byte,
When an 8 bit data bus is specified, the address
present on AD15 to AD8 Address/Data lines is
maintained for the complete bus cycle. Therefore, compatibility with 80188, 8088, 8089 and
8085 multiplexed address peripherals is maintained. Since the internal processing of the 82730
generally operates on 16 bit data quantities, two
Bus fetch cycles are performed for each 16 bit
data item. The first cycle fetches the low order
byte, the second cycle the high order byte. These
2 fetch cycles are always executed back to back.
If HLDA drops during the first cycle, the 82730 will
not respond until the second cycle is completed.
An 8 bit data mode can be selected in an 8 bit bus
system that requires only 8 bit character data be
fetched.
.
The 82730 can be programmed during initialization to operate on either 16 bit or 32 bit (including any length between 17 and 32) physical
addresses. Note that the 82730 does not use
memory segmentation. The programmer must
calculate physical addresses from segment and
offset values to manipulate data structures.
To support 32 bit physical addresses with a 16 bit
physical bus, multiplexing is again used. An
upper address output cycle, TU, is in~erted between T4 and T1 to output the upper 16 bits of
address. The upper address latch enable, UALE,
is used to latch the upper addresses during TU.
Figure 3 shows the configuration of a 32 bit
address bus.
TU occurs only when the 32 bit mode is specified
and the upper address register of BIU is reloaded
by MCU. This may result from:
.
i)
Initialization
ii)
Manipulation of display data or command
pointers, for example, when a new string
pOinter is loaded during the execution of
the END OF STRING command.
iii)
DMA address incrementing across a 64K
byte segment boundary.
iv)
Regaining the bus after losing it to a higher
priority master.
In 16 bit bus system, the 82730 requires all 16 bit
quantities to start on even address boundary.
Word transfer to or from odd boundary is not
allowed since this type of transfer not only doubles the use of bus bandwidth but also can be
easily avoided in application software. All that is
required is to make sure all address pointers be
an even number (AO=O).
ClK
CE
UAlE
AEN
Timing of UALE is identical tothatof ALE. AENis
equivalent to the active period of 82730 driving
the bus.
If 16 bit address mode is programmed, TU will
never occur in any bus cycle since the MIU treats
all display pointers as 16 bit quantities and loading of internal upper address register is bypassed
. Figure 3. Address Extension up to 32 Bits
8-165
210921-<)02
82730
BUS CONTROLS
device can preempt the HLDA from a 82730 whiqh
is the current bus master. The 82730 will complete
its current bus cycle, then fl9at its output drivers
and drop the HOLD request. However, the 82730
may raise the HOLD request again 2 clock cycles
later if it still needs the bus to complete the
interrupted burst DMA activities.
The 82730 BIU provides both the 8086 MIN. Mode
(Local Bus Control) and MAX. mode bus control
signals simultaneously in any bus cycle. By
providing a complete set of Local Bus control
signals, the component count of the Local processing module is minimized.
Because only two types of Bus operations,
Memory Read and Memory Write, are executed in
the 82730 BIU, the 8086's 52 status signal is
omitted from the Max. mode controls. S2 could be
setto "1" during any 82730 Bus cyCle. AEN can
be used to produce S2 since·it stays active
whenever 82730 is driving the bus. The status
signals become valid at the middle of the cycle
before Tl which could be either T4 or TU.
BHE is not provided on the 82730 because, the
82730 only writes words to even address boundaries and bytes to the upper byte position. For
these writes BHE isalways high. A PUIIAE~sistor
or a three-state buffer controlled by
. can
provide this signal.
DMA BURST AND SPACE
Some system configurations using the 82730
. would be adversely affected by the long burst
data transfers which the Memory Interface Unit
(MIU) may occasionally desire, Since the 82730
will normally be configured as one of the higher
priority bus masters, burst lengths must be limited
for these systems. For this reason, the length of a
burst transfer and the number of memory cycles
between burst transfers are both programmable
via the mode registers:
15 14
8 7 6
0
MPTR-':"BRSTLEN
BRSTSPAC
BRSTLEN- Burst Length.Determines the number of contiguous word-fetch cycles which may
be requested. Programmable from 1 to 127.
Note that in an 8 bit bus, 16 bit data system, the
burst counter only increments once for the 2 bus
cycles required to complete a word fetch. (Note:
burst length = 0 is not defined and should not be
programmed with a non-zero burst space)
DT/R is also not provided on the 82730 because
its function can be replaced with ST. latched by
ALE.
After RESET is applied, READY is set to be an
asynchronous input. An on-board synchronization
circuit provides reliable operation for any type of
system. During initialization, READY may be
programmed to be bus synchronous. For those
systems that can meet the set-up time specifications, this mode provides more efficie,nt bus
utilization:
BRSTSPAC - Burst Space. Determines a minimum number of bus clocks to occur between
burst accesses. Programmable from 0-511 in
increments of four. Zero space selects an infinite
burst length.
LOCAL BUS ARBITRATION
A DMA burst could be terminated before the
programmed burst length is reached in the
following circumstances:
The 82,730 BIU is designed to function as a bus
master in a multimaster Local bus environment
using the HOLD/HLDA protocol for Bus arbitration.
In the Self Contained Arbitration scheme, one
processor and one 82730 sQare access to the
local bus. The 82730 raises its HOLD request
whenever it needs bus access. After HLDA is
granted from the processor, the 82730 will not
start driving the bus until2 clock cycles later. This
latency allows sufficient time for the 8086 or
80186 processor to get off the bus. When 82730
completes its bus accesses, it will first float its
output drivers before dropping the hold request.
i)
The MIU does not need any more bus
accesses, for example, when the row
buffer is filled.
ii)
A datastream command is encountered
and the MIU must execute the command
first before it resumes data accessing,
iii)
The bus is taken away by a higher priority
device in multi-master bus configuration,
In these cases, the burst counter iscleared.The
BIU must complete a full burst before it waits
through the SPACE cycles. DMA Burst/Space
will be set to zero space until the completion of
the first MODESET command_
In a Local bus configuration with three or more
bus masters, a higher priority DMA Peripheral
8-166
210921-002
inter
8273~
INITIALIZATION OF BIU
Upon activation of the RESET input, the 82730
BIU will stop all operations in progress and
deactivate all outputs. It will stay ih this quiescent
state until memory acceSs is requested by the
MCU after MCU receives its fl rst channel attention
after RESET. The following table shows the state
of all MIU. outputs during and after reset.
'DIble 2. 82730 Bus During and After R~t
Signals
AD15-0
IRD, tvA, DEN
So,51
ALE,UALE
AEN
HOLD
SINT
Condition
Three-state
Driven to '1' then three-state
Driven to '1' then three-state
Low
High
Low
'Low
Control Bus
The 82730 implements both 8086 minimum and
maximum mode bus control structures. This was
, done to maximize compatibility with the 80186
which has the same structure. This a!lows the
82730 to be run locally (minimum mod$) with a
8085,8086,8088,80188, or 80186. The 80186/188
and 82730, can run together at 8MHz because of
clock duty cycle considerations. The 82730 can
only communicate to.an 80286 via a system bus
(such as MULTI BUS), bus interface, or dual-port
RAM.
INITIALIZATION SEQUENCE
The first CA (Channel Attention) after Reset
causes an Initialization Sequence to be executed.
The system processor must set up the appropriate initialization information in memory and set
the BUSY flag in the I ntermediate Block to a nonzero value prior to issuing this CA.
Initially, 32.!.bit addressing and 8-bit data bus
width, are assumed until the corresponding information is fetched during the initialization. First
the SYSBUS byte is fetched from memory location
FFFF FFF6. (When the add ress bus is less than 32
bits wide, the higher order bits are unused.) The
format for SYSBUS byte is shown in Figure 4 and
is the same as that used for 8089. The data bus
width is specified by the least significant bit w,
with w=Q indicating an 8-bit bus and w=1
signifying a 16-bit bus.
82730 COMPATIBILITY IS~UES ,
82730 Bus Clock Compatibility
The 82730 uses the 50% duty cycle outpuf of the
iAPX-186 at 8 MHz or that generated by a clock
generator such as the 82285. A different duty
cycle clock may be used at lower frequencies, so
the 82730 is also useable with the iAPX-86, 88
family. '
A 32-bit real address pointer is then fetched from
memory locations FFFF FFFC through FFFF FFFF,
with lower bytes of the pointer residing in lower
addresses. This pointer is used as an Intermsdiat~ Block Pointer (IBP).
82730 Bus Interface Compatibility
The bus interface compatibility between the 82730
and another bus master has four main issues:
data bus width, add ressabi lity, control bus structure and local bus mastership arbitration.
The Intermediate Block Pointer (IBP) is incremented by two and is used to locate the Command
Block Pointer (CBP). Four bytes are fetched
irrespective of whether a 16-bit or 32-bit addressing option is used. The System Configuration
byte (SCB) is then fetched from location (IBP+6).
'Data Bus
Data Bus width compatibility with all 85/86 family
processors (8085, 8086, 8088, 80188, 80186, and
80286) is, being supported by the 8/16 data bit
programmability already discussed. This allows
interfaCing to the above processors either directly
or through a Multibus-like interface.
The least significant bit, (U of the SCB) specifies
16 'or 32-bit addressing option, with U=O indicating 16 bit addressing and U=1 specifying 32-bit
addressing. The SCB also contains information
about cluster operation. Since up to four 82730's
can be connected in a cluster with their respective
data interleaved in memory, cluster information is
needed for the data access task. The SCB specifies Cluster Number (CL NO), which is the
number of 82730's connected in a cluster and
Cluster Position (CL POS) which is the position
Address Bus
The 82730 uses real 32-bit addresses. The user's
software must calculate real addresses; this general addressing scheme allows the 82730 to be
used with any microprocessor.
8-167
210921-002
inter
82730
programming of CL NO and CL POS is independent. No checking is done for CL POS greater
than CL NO on the 82730. Note that at least one
82730, in a cluster (even if it is a cluster of one),
must be assigned as cluster position zero (CL
POS = 0) for Virtual Disr;>lay mode to work properly.
of this particular 82730 within the cluster. CL NO =
O,1,20r3indicatesaclustercontaining 1,2,30r4
82730's respectively. Similarly, CL POS= 0, 1, 20r
3 indicate~ 1st, 2nd, 3rd or 4th position respectively. Each 82730 adds an offset equal to 2 *
CLPOS to the SPTR fetched from memory and
increments the pOinter by 2 * (CL NO + 1). The
o
7
0
0
0
o
0
o
o
W
~--------------------------------------------------~
7
6
SRDY
DTW16
_ _ _ _ _ _L -_
_____
~
~
W
Data Bus Width
0
1
8-Bit
16-Bit
5
MIS
______
~
4
CL
__
3
POS
____
~~
o
2
~
CL
SYSBUS Byte
NO
__________
~
U
__
~
SCB Byte
SRDY
READY MODE
DTW16
Display Data Mode
o
Asynch ronovs
Synchronous
0
1
8-bit data
16-bit data
1
"
MIS
Mode
CLPOS
Position in
Cluster
o
1
Slave
Master
00
01
10
11
1st
2nd
3rd
4th
CL NO.
No. of 82730's
In Cluster
U
AD DR BUS WIDTH
1
0
2
1
16-bit
32-bit
00
01
10
11
3
4
. Figure 4.SYSBUS and SCB Encoding
8-168
210921-002
82730
The SCB also contains an MIS bit '!hich specifies
a master or slave mode. The MIS bit is stored
int!rnally for use by the Display Generator.LPG).
MIS = 1 indicates a master mode and MIS = 0
specifies a slave mode. The format for the System
Configuration Byte (SCB) is shown in Figure 4.
Following these actions, the BUSY flag in the
Intermediate Block at address IBP is cleared
and a normal Channel Attention sequence is
then! executed.
The last two bits in the SCB are DTW16 and
SRDY. DTW16 specifies whether the display data
in 8 bit bus mode (W=O) is 8 or 16 bit. If a 16 bit
system is specified (W=1) then DTW16 is ignored
and forced internally to a "one". SRDY specifies
whether the clock synchronization circuit for the
READY pin is internal (SRDY=O) or external
(SRDY=1).
The Initialization Control Blocks in memory are
illustrated in Fig. Sa. How these fit into the control
structure of the 82730 is sho"'Yn in Figure 5b.
Channel AUenllon Sequence
When the processor activates CA, an internal
latch in 82730 is set on the falling edge of CA
input and this latch is sampled by the MCU. The
first CA activation after reset causes the 82730 to
execute an initialization sequence. Any subsequent activation will cause the MCU to start processing,the command block by fetching a channel
command.
If a display is in progress, the MCU will sample CA
at each end of frame, otherwise it will sample CA
every cycle until it is found active. When CA is
found active, the MCU will fetch the command
byte from "COMMAND"location in the command
block, execute the command and clear the BUSY
flag upon completion. The internal CA latch is
also cleared by the MCU. An invalid command
code has the effect of NOP and the BUSY flag is
cleared. It will also cause the Reserved Channel
Command (RCC) status bit to be set.
o
INTERMEDIATE
I 8
7
IBP UPPER
BLOCK POINTER
IBPLOWER
FFFF FFFC .
,(RESERVED) SYSBUS
FFFF FFF6
15
INTERMEDIATE
BLOCK
FFFF FFFE
(RESERVED) SCB
1BP +6
CBP UPPER
1BP+ 4
CBP LOWER
(RESERVED) BUSY
1BP+ 2
COMMAND
·CBP
1BP
COMMAND
BLOCK
BUSY
LOW SYSTEM MEMORY
Figure 5a. Initialization Control Blocks
8-169
21092HI02
l
STRING POINTER
LIST
INITIALIZATION BLOCK
ADDRESs
FFFF6:
,----'\
I
I SYSTEM BUS WIDTH
1-----
.
.
INTERMEDIATE BILOCK POINTER LOW
r
DISPlAY
DATA Sl'RINGS
.....VMMANU DL\AOI\
••
. ...
8
7 6 5
COMMAND
LIST SWITCH
•
.
•
DAU
0
BUSY
END OF ROW
AUTO LINE FEED
MAX DMA COUNT
LIST BASE 0 LOWER
INTERMEDIATE BLOCK POINTER HIGH
LIST BASE 0 UPPER
rt
LIST BASE. LOWER
~
DATA
LIST BASE' UPPER
COMMAND BLOCK POINTER'LOWER
COMMAND BLOCK POINTER HIGHER
INTERMEorATE BLOCK
o
~
....
STATUS
0>
.!.
.....,
CONFIGUIRATION BYTE
OCK POINTER LOW
COMMAND BLOCI
INTERRUPT GENERATION CODE
~
INTERRUPT MASK
COMMAND BLOC
OCK POINTER HIGH
LIGHT PEN ROW
(1
CURSOR' ROW
CURSOR 1 COLUMN
CURSOR 2 ROW
CURSOR 2 COLUMN
DATA
LIGHT PEN COLUMN
ENDOFROW
MODE POINTER LOWER
MODE POINTER UPPER
STATUS ROW POINTER LOWER
STATUS ROW POINTER UPPER
TO MODE BLOCK
'"
~
~
Figure 5b. Control Structure of the 82730
~
inter
82730
82730 CHANNEL COMMANDS
~ble
3. Channel Commands
COMMAND
START DISPLAY
0000
0001
01 H
02 H
2
START VIRTUAL DISPLAY
0000
0010
3
STOP DISPLAY'
0000
0011
03 H
4
5
6
7
8
MODE SET
0000
0100
04H
LOAD CBP
0000
0101
05 H
LOADINTMASK
0000
0110
06H
LPEN ENABLE
0000
0111
07 H
READ STATUS
1000
08 H
9
LD CUR POS
0000
'0000
1001
09H
0000
,0000
1010
OA H
1011
OB H
0000
0000
OOH
From: 0000
To: 1111
1100
1111
OC H
FF H
0
SELF TEST
1
TEST ROW BUFFER
2
NOP
3
(RESERVED)
The system processor issues chaMel commands
to 82730 via the Command Block. The processor
first checks if the BUSY flag in the command
block has been cleared. It should wait for the
BUSY flag to be cleared before proceeding with
the issuing of a command. When the BUSY flag is
cleared, the processor places a commanq byte in
the "COMMAND" location in command block,
sets the BUSY flag to a non-zero value and asserts
Channel Attention (CA), by activating the CA
input to 82730. A,Channel Attention should not be
issued, if the BUSY flag has not been cleared.
START DISPLAY
0000
OPCODE
1
0001
CMD Byte
LlSTSWITCH, Auto Linefeed, Max DMA CQunt
and Cursor Position values are fetched from the
Command Block and stored internally after this
command is received. The BUSY flag is cleared
and the normal, display process is activated.
The MCU fetches strings of data from the memory,
using the parameters LISTSWITCH, LBASEO and
LBASE1. The data fetched is interpreted as data-
stream commands or character dafa to be displayed by the Display Generator. The MCU loads
the data into one of the two Row Buffers in the
CRT controller, while the Display Generator
displays the data from the other buffer, the buffers
being swapped at the end oftherow. Any datastream commands encountered during data fetch
are immediately executed.
The display process is continued until it is deactivated by a STOP DISPLAY command or a Reset.
Other channel commands can be issued while a
display is in progress and they will be executed
when CA is found active at one of the periodic
samplings at each end of frame.
The DIP (Display in Progress) status bit is set and
the VDIP (Virtual Display in Progress) is cleared
upon receiving a START DISPLAY command.
Both bits are reset upon receiving a STOP DISPLAY command or a Beset.
It is necessary to load in proper mode information
through a MODESET command before activating
the display. Following Reset, START DISPLAY
command will not b~ executed, i.e., will result in a
NqP until' a MODESET command has been
issued.
8-171
210921-()02
82730
START VIRTUAL DISPLAY
START VIRTUAL DISPLAY command will not
activate a display and results in a NOP until a
MODESET command is issued after a Reset.
text coprocessor are required to remain unchanged over most of normal operation. No
provision is made to prevent MODESET from
changing these parameters and it is left to the
designer to insure that they are not changed.
The modes provide horizontal and vertical mode
display parameters, interlace information, DMA
burst and spacin'g specifications, cursor characteristics as well as attribute enables and bitselects. Typically, this would be the fi rst com mand
issued after initialization. The Mode Block provides all the parameters needed for a complete
initialization of the 82730 for display. Thus a
single Modeset command can fully initialize the
chip. Note that until the first Modeset command is
sent, certain functions such as VSYNC and
HSYNC are not enabled.
It is necessary to set up proper mode information,
before activating a display, Therefore, a display
activating commands should not be issued unless.
proper mode information has been loaded through
a MODESET command. START DISPLAY and
START VIRTUAL DISPLAY commands will result
in a NOP if a MODESET command has not been
issued sinc~ the most recent Reset.
STOP DISPLAY
LOAD CBP
0000
0010
CMD Byte
LlST,SWITCH, Auto Linefeed, Max DMA Count
and Cursor Positions are fetched from the
Command Block and stored internally upon receiving this command. The BUSY flag is cleared
and the Virtual Screen display process is activated.
Th~ operation of Virtual Screen display process is
similar to that of a regular display process, except
for following a different data access mechanism.
The parameters LlSTSWITCH, LBASEO and
LBASE1 in the colmmand block repres.ent ACCESS SWITCH, ACCESS BASEO and ACCESS
BASE1 respectively, in· virtual screen display.
The VDIP (Virtual Display in Progress) status,bit
IS set and the DIP status bit is cleared upon
receiving a START VIRTUAL DISP command:
Both DIP and VDIP are reset upon receiving a
STOP DISPLAY command or a Reset.
0000
0011
CMDByte
The display process is deactivated upon receiving
this command. The DIP and VDIP,status bit are
reset and the BUSY flag is cleared.
This command blanks the display. HSYNC and
VSYNC are not affected.
MODE,SET
0000
0100
CMD Byte
The Mode Pointer contained in command block
location (CBP + 30) is used to access the Mode
Block and the modes are fetched sequentially
and loaded into the corresponding internal registers in 82730. LlSTSWlTCH, Auto Linefeed, Max
DMA Count and Cursor Positions are fetched
from the Command Block and stored internally
upon completion and the BUSY flag is cleared.
The organization of mode words in the mode
block and the parameters supplied by them are
shown below (See Figure 10). Some of these
parameters which are critical to the operation of a
0000
0101
CMD Byte
The address pointer"NEW CBP" contained in the
command block is fetched and stored in the CBP
register in the text coprocessor, replacing the old
CBP. This effectively moves the command block
in the memory. The Command byte from the new
Command Block is fetched and, the specified
channel command is executed. The BUSY flag in
the new Command Block is cleared upon completion. '
LOAD INTMASK
0000
0110
CMD Byte
The interrupt mask confained in location "I NT
MASK" in the command block is fetched and
stored internally in the CRT controller. When a
particular mask bit is set, the interrupt is disabled
for a status bit in the corresponding bit position.
An interrupt is generated by the text coprocessor
by activating the SINT pin, if a status bit is 1 and
the corresponding bit in the interrupt mask is 0,
The BUSY flag is cleared upon completion.
8-172
21092H)02
inter
82730
Interrupts can be enabled for the following status bits.
7
ROC:
RCC:
FOE:
EOF:
DBOR:
LPU:
OUR:
5
4
3
2
RCC
FOE
EOF
DBOR
I -
1000
CMD Byte
0000
8
VDIP
7
DIP
6
ROC
5
RCC
LPEN ENABLE
0000
BIT
STATUS WORD
OUR
LD CUR POS
The internal status register is written to"STATUS"
location in the command block. The status
register is then cleared, however DIP and VDIP
status bits are not cleared. LlSTSWITCH, Auto
Linefeed, Max DMA Count and Cursor Positions are fetched from the Command Block and
stored in~ernally. The BUSY flag is then cleared.
STATUS WORD
15-9
LPU
Reserved Datastream Command Encountered
Reserved Channel Command Executed
Frame Data Error (Fetching characters past physical End of Frame)
End of "ri" frames (Logical end of nth frame)
Data Buffer Overrun (Row Buffer filled completely without
encountering END OF ROW command)
Light Pen Update
Data Underrun (Buffer swa:p initiated before finishing Row Buf
loading)
READ STATUS
0000
a
6
ROC
0111
CMD Byte
1001
CMD Byte
The display row and column positions of cursors
1 & 2 as set in locations "CUR1 ROW," CUR1
COL," "CUR2 ROW" and "CUR2 COL" in the
command block are loaded into internal regis.
ters in the CRT controller. Also LlSTSWITCH
Auto Linefeed and Max DMA Count are loaded
from the Command Block and the BUSY flag is
432
FOE
EOF DBOR
1
LPU
0
OUR
cleared. This command is used to change the
cursors only. Note that the cursor pOSitions are
also updated with the execution of other channel
commands.
The Light Pen detection process is enabled to
search for a rising edge on the LPEN pin. The
BUSY flag is then cleared.
The cursor characteristics for display are defi ned
by the mode. During the display process, a
cursor will be displayed accordingly at the
position specified above.
If the display process is active and a rising edge
is detected on the LPEN input, the corresponding row and column position on the
screen is stored internally. At the next end of
frame, the LPEN position is written to locations
"LPENROW" and "LPENCOL" in the command
block and the LPU (Light Pen Update) status bit
is set.
NOP
0000
0000
CMD'Byte
LlSTSWITCH, Auto Linefeed, Max DMA Count,
and Cursor Positions are fetched from the command block and stored internally as in all other
channel commands. The Busy flag is then cleared ..
It the display process is not active, this command has no immediate effect. However, the
LPEN detection process remains enabled and
will take effect if a display is activated subsequently.
8-173
210921-002
827~0
bits of the data word in the Row Buffer as
character data. This process is repeated for
each data word fetched.
82730 DATASTREAM COMMANDS
Datastream Commands
Datastream commands can be used for changing
Row Characteristics on a row by row basis, for
carrying out editing functions and for formatting data into rows and frames. These commands are executed by the MCU immediately
after they are encountered. As a convenience'
for the user, the set of all possible command
codes starting with "11" in the two most significant bits has been designated as NOP commands. The user can use these command codes
for any desired purpose. All other command
codes which are not presently defined, are
reserved for future expansion and should not be
used by the user. The currently undefined
codes cause the RDC (Reserved Datastream
Command),status bitto be set and also generate
an interrupt, if enabled. Reserved command
codes should not.be used.
Datastream Commands.are commands embedded in the data fetched from memory by the
data access task. These commands are differentiated from character data by the command
bit. The most significant bit (MSB) of each data
word is designated as the command bit. If the
command bit is "1", the lower 15 bits of the data
word are interpreted as a datastream command,
while if the command bit is "0" the lower 15 bits
(or 7 bits if DTW16=0) are interpreted as character data.
Datastream Command Operation
During the data access task, the Micro Controller
Unit (MCU) examines the command bit of each
data word fetched. If the. command bit is 1, it
executes the datastream command specified in
the data word. Otherwise, it stores the lower 15
Datastream Command List
Table 4. 82730 Datastream Commands
COMMAND CODE
COMMAND
QP CODE
OP CODE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
ENDROW
EOF
END OF STRING & END OF ROW
FULROWDESCRPT
SL SCROLL STRT
SL SCROLL END'
TAB TO n
LD MAX DMA COUNT
ENDSTRG
SKIP n
REPEAT n
SUB SUP n
RPT SUB SUP n
SET GEN PUR ATTRIB
SET FIELD ATTRIB
INIT NEXT PROCESS
(Command process command)
(R.ESERVED)
NOP
PARAMETERS
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011·
1100
1101
1110
1111
XXXX
XXXX
XXX X
XXXX
XXXX
XXX X
- "n"
XXX SCR LINE
XXX END LINE
"n"
COUNT
XXX X
XXX X
"h"
10XX
llXX
XXXX
XXXX
XXXX
XXXX
8-174
un"
"n",j
"n"
, GPA OP
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
80
81
82
83
84
85
86
87
88
89'
8A
8B
8C
8D
8E
8F
.
9O-BF
CO-FF
210921-002
inter
82730
addition, in auto linefeed mode (ALF = 1) other
parameters characterizing the process state are
also saved In the header. The "Process Addr"
register is loaded with the address of the header
of the next process fetched from the Access table.
The "Access Tab Addr" register is post-incremented
by two If a 16-blt addressing option is used and by
four if 32-bit addressing is used. The data access'
task is then resumed for the next process.
"The preceding commands' are 'recognized as
valid datastream commands. The corresponding
command codes are also indicated. It should be
noted that the most significant bit of the command
bit is always 1, in order for the word to be
interpreted as command.
The "Inlt Next Process" command can be issued
only through a command 'process In Virtual
Screen Display. It is included in this list because
its operation is analogous to a datastream command in a virtual screen access environment.
Also, in virtual screen display certain datastream
commands are interpreted differently, depending
upon whether they are encountered in a process
datastream or as command process commands.
When a commandis ignored (becomes a NO-OP)
in a virtual display, any parameters that are associated .with it are also ignored. The command
process command operation is discussed separately: The operation of all other datastream commands is described below.
'
EOF
15
14
000
8
0000
7
xxxx
8
0001
7
xxxx
o
xxxx
This command (End of Frame) signifies that no
more characters will be loaded in the Row Buffers
for this frame. The Micro Controller Unit (MCU)
stops fetching data words and waits for the
physical end of frame. If a virtual display is in
progress, this commandis'lnterpreted as VEOS
(Virtual End of Frame), if encountered in a virtual
process datastream.
ENDROW
15
1
14
000
o
The Display Generator (DG) swaps the row
buffers at the end of the current display row and
starts displaying the row containing the EOF
command. When the character preceding the
EOF command is displayed, the DG blanks the
screen until the physical end of frame. The MCU
fetches the Status Row data then waits until its
display is completed. It then performs the actions
'
described below.
xxxx
This command signifies that no more characters will be lo,aded in the Row Buffer for this row
and an End of Row indicator is stored accordingly. When the row currently being loaded is
displayed, the Display Generator (DG) will blank
the screen from the end of row character position
'
until the,physical end of row.
If LPEN has been enabled and a rising edge on
the LPEN input has been detected, the LPENROW
and LPENCOL positions in the command block
are updated and the LPU status bit is set. If a
Channel Attention has occurred, i.e., if CA has
been activated, the command byte is fetched
from command block and the specified channel
command is executed. If the command issued is a
"Stop Display" command, the MCU will terminate
the display. process and wait for the next channel
attention. Otherwise, the MCUresumes the data
access task by reinitializing pointers for the new
frame and continues to fill the Row Buffers.
The Micro Controller Unit (MCU) stops fetching
data and waits for DG to swap the Row Buffers ..
The data access task is resumed following the
buffer swap. If a physical end of frame is reached
while the MCU is waiting for a buffer swap the
MCU ceases to wait and executes an EOF (End of
Frame) command.
In virtual display, this command is interpreted as a
VEOR (Virtual End of Row) if encountered in a
virtual process datastream.
VEOR
ENDROW command in a virtual process datastream is interpreted as VEOR (Virtual End of
Row) and it terminates a virtual row. The current
LPTR is stored in the process header addressed
by the ,"Process Addr" register. The, Max Count
register is also stored in the Max DMA Count,
location in the process header. Similarly. the Field
Attribute Mask is also stored in the header. In
VEOF
EOF command in a virtual process datastream is
interpreted as VEOF (Virtual End of Frame). It
provides for reinitialization of LPTR using LIST~
SWI1CH, LBASEO and LBASE1 for each process,
analogous to the automatic reinitlalization of
: LPTR at each end of frame in a Normal Display.
8-175
210921-002
$2730
FUlROWDESCRPT
LPTR for the current process is reinitialized using
LlSTSWITCH, LBASEO and lBASE1 contained
in the process header. The End of Display (EOD)
bit in the header is set to 1. The current process is
terminated as in a VEOR and the next process in
Access Table is accessed.
15
14
000
8
0010
7
XXXX
o
XXXX
The EOl (End of Line) command has a combined
effect of NXTROWand NXTSTRG commands. All
the actions performed in a END OF ROW command are carried out. In addition a END OF
STRING command is executed before resuming
the data' access task. Thus, following the end of
row, the data access is continued with the next
data string. In virtual process datastream, this
command has the combined effect of VEOR and
END OF STRING.
Upper Byte
Li nas per row
Normal Start/Stop
Superscript Start/Stop
Subscrip~ Start/Stop
Cursor 1 Start/Stop
Cursor 2 Start/Stop
Underli.ne Line Selects
o
7
0011
n
The next un" words fetched from memory are
loaded into the Row Characteristics holding
registers. un" is specified by the lower order byte
of the command word and should be between 0
and 7.
The patameters loaded by this command will be
used to define the tow characteristics at the time
the row currently being loaded is displayed. The
data words defining these characteristcs which
follow the FUlROWDESCRPT command must
be ordered and organized in memory in a specific
format. The format for FUlROWDESCRPT parameters is shown below in Figure 6 starting with
"Lines Per Row" as the first parameter loaded.
This command will be ignored if encountered in a
virtual process datastream. The MSB of all the
parameters must be zero for proper operation in
virtual display.
EOl
15
8
14
000
15 14 13 1211
10
9
8
RVV BlK DBl
W
ROW ROW HGT DEF
NRMSTRT
SUPSTRT
SUBSTRT
CUR1 STRT
CUR2STRT
Ul2 LINE SEl
lower Byte
765
4' 3
2
1
0
lPR
NRMSTOP
SUPSTOP
SUBSTOP
CUR1STOP
CUR2STOP
Ul1 LINE SEl
RVV ROW, when this bit is set the CRVV pin will be inverted for the next full row.
BlK ROW, when this bit is set the row will be blanked (BLANK high).
DBlHGT, when the double height bit is set, all character are displayed with twice the scan lines per row.
WDEF,when the width defeat bit is set, the WOEF pin is activated for the entire row.
The followi"ng can be programl)1ed from 0 to 31 yielding a range of 1 to 32 lines.
lPR specifies number of lines per row.
NRMSTRT, SUPSTRT, SUBSTRT specify line numbers in a display row which mark the stp.rt of
normal, superscript and subscript characters respectively.
NRMSTOp, SUPSTOp, SUBSTOP specify line numbers in a row where normal, super script and
subscripCchatac'ters end respectively.
CUR1 STRT, CUR2 'STRT specify the starting line numbers in a row for cursor 1 and cursor 2
respectively.
ULlNE1 SEl, ULlNE2 SEl specify the line numbers in a row where underline 2 will appear
respectively.
All FUlROWDESCRPT parameters affect the row in which they are programmed and stay in effect
until changed by another FUlROWD~SCRPT command.
Flgu~e
6. Formal for FULROWDESCRPT
8-176
210921-002
inter
82730
SL SCROLL STRT
15
14
000
8
7
5
xxx
0100
4
0
SCR LINE
The Slow Scan register in 82C3 is loaded with the
scroll line specified by the five least significant
bits of the command word. When the row currently being loaded is displayed, the line count for
that row will start with the value specified by the
Slow Scan register. A "Margin" (MGN) parameter,
loaded by MODESET, specifies the number of
blank lines plus one to be added at the top of the
slow scroll field on the screen. This ensures the
availability of sufficient DMA time for fetching the
next row, when only a small number of scan lines
are displayed in the top row of slow scroll window.
This command is used for starting a slow scroll.
(Note: MGN = 0 results in no margin buffer lines)
This command will be ignored if encountered in a
virtual process datastream or if a SL SCROLL
END command is encountered later on the same
row.
SL SCROLL END
15
14
000
8
0101
7
xxx
5
4
0
END LINE
The scroll location in row characteristics holding
registers is loaded with the number of lines
specified by the five least significant bits of the
command word. This number specifies the number of lines to be displayed when the row currently
being loaded is displayed. This is used instead of
the regular LPR (Lines Per Row) characteristics,
for this particular row. This command is used in
the last row of a slow scroll for terminating a slow
scroll. The Margin (MGN) parameter, loaded by
MODESET, is used in the same way as in slow
scroll start e~cept that the specified number of
blank lines are inserted at the bottom of the slow
scroll in this case. This command will be ignored
if encountered in a virtual process datastream or
if followed by a SL SCROLL STRT on the same
row.
TASTOn
15
14
000
displayed, the screen is blanked, until the RCLK
count specified by the command ("n'.') is reached.
After reaching the specified count, display is
resumed by displaying the character following
the TAB command.
If the RCLK count specified by the Tab command
has already occurred before beginning the
blanking for Tab, the display will be blanked until
• the end of the row.
This command is ignored, if encountered in a
virtual display process datastream.
'
LD MAX DMA COUNT
15
14
000
8
0111
o
7
MAX COUNT
The Max Count register in 82730 is loaded with
the Max DMA Count specified by the lower byte
of the command word. The DMA Counter is also
reinitialized with the Max Count value in the
Command ~Iock after all channel commands.
MAX DMA Count is programmable in the range of
1 to 256 (MAX COUNT value 0 equals 256). However, counts greater than the row buffer capacity
will cause row buffer overruns if the data strings
depend on MAX DMA to terminate the fetching.
\
The DMA·counter is decremented for each data
word as the Row Buffer is being loaded. Datastream commands and words supplying parameters for datastream commands as in FULROWDESCRPT, are not counted. SuperscripVSubscript
characters are counted in pairs, i.e., a pair of
characters causes only' one count.
In virtual screen display, every time a new process
is accessed, the DMA counter is initialized with
the Max DMA Count contained in the process
header. This value is also stored in a Max Counter
register.
At virtual end of row (VEOR) the Max .count
register is written to the process header. The "LD
Max DMA Count" command is ignored if encountered in a virtual process datastream.
ENDSTRG
8
0110
7
o
The lower byte of the command word specifies
the- column (RCLK count) after SYNCSTRT at
which a Tab should occur. At.display time, after
the character preceding the Tab command is
15
14'
000
8
1000
7
XXXX
o
XXX~
,
The 'gpTR register in the 82730 is loaded with a
new String Pointer (SPTR) value fetched from the
memory location indexed by the List Pointer
(LPTR), which is stored in the LPTR register. The
8-177
210921-002
82730
LPTR register is incremented by two if a 16-bit
addressing option is used 'and by four if 32-bit
addressing is used. When more than one 82730 is
connected in a cluster, .each of them adds an
offset, deten'nined by its position in the cluster, to
the pointer fetched from memory, before storing
it in its SPTR register.
linefeed mode (ALF = 0), reacl'ling Max DMA
Count before the n repetitions are completed will
result in a termination of the Repeat n command.
This command will also be terminated if the Row
, Buffer gets filled completely before the n repetitions are completed.
It should be noted that the data word immediately
following the Repeat n command is treated as
This command directs the data access to the next
character data, irrespective of the value of its
data string in the list of strings indexed by LPTR.
The operation of this command is identical for a ,.' command bit.
Virtual or Normal Display. In virtual display, tlie
next data string within the current display process is accessed.
SUP/SUB n
SKIPn
15
1
14
000
15
8
o
7
1001
n
The next "n" data words fetched from memory are
ignored. "n" is s'pecified by the lower byte of the
command word and is programmable from 0 to
255. If n equal to 0 is specified, no words are
skipped. Any datastream commands encountered in the data fetch are not counted towards these
n words~ Also parameters following the datastream command as in FUL~OWDESCRPT are
not counted. All embedded datastream commands are executed. If the data words skipped
include any superscript-subscript characters,
they are skipped in pairs and a pair of characters
is counted as only one count in "n". If another skip
command is encountered its value of "n" is added
to the pr~sent skip count and skipping continues.
If an EOF (End of Frame) datastream command is
encountered, SKIP n is terminated. A ENDROW
command causes termination of a SKIP n com mand in non-auto linefeed mode (ALF=O) in'
either normal or virtual dispaly mode. If ALF=1
the ENDROW is ignored, and not counted.
REPEAT n
15
14
000
8
1010'
o
7
n
The next data word (byte, if DTW16=0) fetched
,from memory is stored in the Row Buffer "n"
times, where un" is specified by the lower byte of
the command word. Un" is programmable from 0
to 255. If n equal to 0 is specified no repetitions
will occur, and the word following the Repeat n
command will Qe ignored. This character will
eventually be displayed n times. The DMA counter
is also made to count n times. In non-auto
14
000
8
o
7
n
1011
The next un" pairs of data words (bytes, if DTW16
= 0) fetched from memory are treated as superscripts or subscript characters. un" is specified by
the lower byte 9f the command word .. These n
pairs are assumed to be. ordered with the superscript preceding the subscript.
No datastream commands are permitted in the 2n
words following this command/All ofthese words
are interpreted as superscript-subscript pairs.
The DMA counter is made to count only once for
each pair of characters. In non-auto linefeed
mode (ALF=O), reaching the Max DMA Count will
result in a termination of this command. If n equal
to zero is specified, no action will result.
RPT SUB/SUP n
15
14
000
8
1100
o
7
·n
The operation of this command is similar to that
of the "Repeat n" command except that the pair of
characters follpwing the "RPT SUB/SUP n" command is repeated n times. "n" is specified by the
lower byte of the command word and is programmable from 0 to 255. If n equal to zero is
specified, no repetitions will occur, and the two
data words following the "RPT Sub/Sup n" command will be ignored. The two data words (bytes,
if DTW16=0) immediately following the command
word are interpreted as a superscript-subscript
pair and are repeated. The DMA counter is made
to count only once for each repetition of the pair.
In .non-auto linefeed mode (ALF=p>, reaching
Max DMA Count prjor to completion of n repetitions wil.1 cause a termination of this,command.
210921-002
inter
82730
SET GEN PUR ATTRIB
15
14
000
8
Datastream Command Conventions
o
7
1101
The reaching of Max DMA Count, encountering
of terminating commands such as ENDROW,
EOF, etc. and occurrences of these while exe- ,
cuting a "skip n" command give rise to various
possible combinations of events. The behaviour
of 82730 underthese circumstances is described
below:
GPAOPERAND
This command provides control over the output
pins assigned to General Purpose Attributes,
GPA1 through GPA4.
7
GPA4
DATA
GPA
OPERAND
5
GPA3
DATA
6
GPA4
EN
ENCODING
4
GPA3
EN
GPAx
DATA
GPAtt
EN
0
1
0
1
0
0
1
1
In Virtual Display, everytime a display process is
accessed, the state of the General Purpose Attributes is loaded from the header. The GPA in the
Process Header is also updated each time a SET
GPA command is executed. Thus the GPA state in
the header is updated to reflect any changes
caused by the "Set Gen Pur Attrib" command.
The encoding of the operand, specifying GPA
operation, is shown below.
14
000
o
8
1110
7
XXXX
14
1XX
8
XXXX
7
XXXX
FUNCTION
ROW BUFFER DATA
ROW BUFFER DATA
GPA DATA = 0
GPA DATA = 1
In non-auto linefeed mode, "Repeat n",
"Sub/Sup n" and Rpt Sub/Sup n" commands are terminated upon reaching a
max DMA count, even if "n" is not reached.
iii)
"Skip n" command is terminated if EOF
command is encountered. It is also terminated upon encountering a ENDROW
command in non-auto linefeed mode
(ALF = 0).
iv)
"Repeat n" "Sub/Sup n" ahd "RPT Sub/
Sup n" commands can be nested wfthin a
"Skip n" command. If superscript-subscript
characters are skipped, each pair'of characters counts as one skipped character. If
the above commands are encountered
during a "skip n" and if the specified
count (n) in these commands is not
reached by the end of execution of the
"skip n" command, the execution of the
nested command is continued beyond
the termination of "skip n" command until
the remaining portion of the count specified in the nested command is completed.
NOP
15
0
GPA1
EN
ii)
FIELD ATTRIBUTE MASK
The word following this command is fetched.
This word is used as a Field Attribute Mask in
storing all subsequ~nt display data words in
row buffer. The bits in the data words fetched
from memory corresponding to the bit-positions
containing a "1" in Field Attribute Mask are all
set to 1 before storing the data word in row
buffer. The Field Attribute Mask is used on all
display data words fetched from memory. The
mask register will contain all O's upon reset and
is cleared at the beginning of each frame.
GPA1
DATA
When Max DMA Count is reached, it has
·the effect of a VEOR command if a Virtual
Display is in progress or a ENDROW command if a Normal Display is in progress. It
also causes an automatic end of string
Le., the effect of a NXTSTRG command in
non-auto linefeed mode (ALF = 0).
o
XXXX
GPA2
EN
i)
SET FIELD ATTRIB
15
1
321
GPA2
DATA
o
XXXX
No action is taken. The data access task is
resumed by fetching the next data word.
8-179
210921-002
inter
82730
VIRTUAL SCREEN,MODE
Command Process Com.mands
In Virtual Screen Display, 82730 accesses display processes and command processes through
the Access table., The command processes
enable the 1/0 Driver process to'direct 82730 to
execute certain data stream commands by inserting an appropriate \command process
address in the Access table. This capabnity enables the preservation of uniformity and consistency of operation between normal and virtual
environments, by assigning different interpretations to the command accordi'ng to the
access environment. It is especially useful for
termination and initialization commands. The
operation of command process commands is
analogous to that of data stream commands
except for a different access environment.
Command Process Command list
The commands allowed in command processes
can be divided in.to two subsets. The first subset
consists of commands that can be issued only'
through a command process, while the second
one consists of normal datastream commandS
that can also be issued through a command
process. The command code for a datastream
command issued through a command process
is the same as that for the normal datastream
command embedded in the data. However,
certain datastream commands are interp~eted
dlffere!1tly when they are issued through a command process as oppolled to embedding in the
datastream of a virtual display process. The
most significant bit (MSB) of the command
word must be a "1". In the datastream, this bit
distinguishes a command word from character
data. In the process environment, this bit distinguishes a command process from a display
process. The commands permitted in command
processes are listed below. No othercommands
will be'recognized if encountered in a command
process and will result in a NOP. All undefined
command codes apart from those designated
'as NOP are reserved and should not be used.
Encountering an illegal command code causes
the ROC (Reserved Datastream Command)
status bit to be set and will generate an interrupt,
if enabled.
Table 5. Command Process Command list
COMMAND
INTERPRETATION
IN VIRTUAL
PROCESS
DATASTREAM
Command Proceas Only Command:
1 INIT NEXT PROCESS
NOP
Command Process or Datastream Commands:
2 ENDROW
. VEOR
3 EOF
VEOR
'4 EOl
VEOR + NXTSTRG
5 FUlROWDESCRPT
NOP
6 SL SCROLL STRT
NOP
7 SL SCROLL EN 0
NOP
8 TAB TO n
f'toIOP
NOP'
9 LD MAX DMA COUNT
, 10 (RESERVEP)
RESERVED
11 NOP
NOP
COMMAND CODE
OPCODE
OPCODE
1000
1111
1000
1000
1000
1000
1000
1000
1000
1000
10XX
11XX
1000
0061
0010
6011
0100
0101
0110
0111
XXXX
XXXX
PARAMETERS
XXXX
XXXX
8F
XXXX
XXXX
XXXX
,XXXX
80
81
82
83
84
85
86
87
90-SF
CO-FF
'xxxx
XXXX
XXX'
XXX
Un" .
"SCR LINE"
"END LINE"
un"
"COUNT"
XXXX
XXXX
XXXX
XXXX
./
, 8-180
210921-002
inter
82730
.INIT NEXT PROCESS
15
14
000
o
7
8
1111
XXXX
XXXX
This command can be used onlY,in a command
process to initiate a virtual display "'Io!indow",
Upon receiving this command, the command
process is terminated and the next process in
Access Table is accessed by fetching the new
process address, However, the LPTR register is
not directly loaded from the LPTR location in the
process header. Instead, LISTSWITCH in the
process header is examined and LPTR is initialized with the value LBASE 0 orLBASE 1 depending upon wheth~r LISTSWITCH is 0 or 1 respectively. Both LBASEO and LBASE1 are contained
in the header.
The process header format is shown in Figure 7.
Also the End of Display Bit (EOD) in the header is
reset.
:rhe data access task for a virtual display is then
resumed, with this value of LPTR.
\
15
0
14
LOCATION
PROCESS ADDR
PROCADDR +2
MAX DMA COUNT PROC ADDR +4
PROCADDR +6
LBASEO LOWER
LBASEO UPPER
PROCADDR + 8
PROC AD DR + 10
LBASE 1 LOWER
LBASE1 UPPER
PROC ADDR + 12
PROC ADDR + 14
GPA
PROC,ADDR + 16
FIELD ATTRIBUTE MASK
PROC ADDR + 18
LPTR
'LOWER
LPTR
UPPER
PROC ADDR + 20
SPTR
LOWER
PROC ADDR + 22
,
UPPER
SPTR
PROC ADDR + 24
13
8
-------
LS: LlSTSWITCH
ALF: AUTO LINE
FEED
---,-
----
1
1
SAVE
AREA
RPT
SIS
1
1
SIS
RPT
7
6
EOD
LS ALF
0
----
--
REPT COUNT
REPT CHAR
REPT CHAR 2
15
14
PROCESS ADDR
8
7
PROC AD DR + 26
PROC ADDR + 28
PROC ADDR + 30
o
COMMAND
C/O
Figure 7. Process Header for Display and Command Process
8-181
210921-002
82730
ENDROW
15
14
000
TAB TO It
8
0000
7
XXXX
o
15
XXXX
The actions performed by a, ENDROW datastream command in a Normal Display are
·carri~d out. The next process in Access Table is
accessed and the data access 'task is 'resumed,
after the next Row Buffer swap
14
000
7
XXXX
8
0001
15
1
The actions performed by an EOF (End of
Frame) data stream command in a Normal
Display are carried out.
EOL
15
1
14
000
7
XXXX
8
0010
o·
XXXX
This command is identical to ENDROW command in Virtual Display in Command Process
environment. ENDSTRG, which is strictly a data
operation within a display process is meaningless in the comma~d process environment.
.
FULROWDESCRPT
1514
000
8
"n"
14
000
8
0111
o
7
MAX COUNT
The Max Count register on 82730 is loaded with
the value specified by the lower byte of the
command word. The DMA counter is also initialized with this Max Count Value.
The next process in the Access Table is accessed.
However, the Max DMA Count value in the'
process header is not used for initializing the
DMA counter. Instead, the DMA counter as
initialized by the LD Max DMA Count command
is used for this process. The virtual display data
access task is then resumed normally. When the
process is terminated, the new Max Count valulil
is written to the process header. Thus the Max
Count value in the header is updated as a result
of this command.
NOP
o
7
0011
o
7
LD MAX DMA COUNT
o
XXXX
8
0110.
The effect of this command process command
is identical to that of the TAB TO n datastream
command. The TAB can be'used to establish the
left edge of a virtual display "window".
EOF
15
14
000
15
"n"
14
1XX
8
XXXX
7
XXXX
o.
XXXX
The actions performed by the FULROWDESCRPT datastrea'm command are carried out.
The data access task is resumed by accessing
the next process, in the Access Table.
No action is taken. Data access task is resumed
by fetching the next process address from
Access Table. '
SL SCROLL STRT
ERROR AND STAT,US HANDLING
15
. 1
14
000
8
0100
7
xxx
5
0
4
"SCR LINE"
Error Conditions
The ~ame actions as the SL SCROLL'STRT
datastream command. ,The data access is
resumed with the next process in Access Table.
SL SCROLL END
15
14
000
8
0101
7
xxx
5
4
0
"END LINE"
The actions performed by a sL SCROLL END
datastream command, in a ""ormal display, are
carried out. The data access task is resumed
with the next process in Access Table.
Since the MCU and DG function asynchronou'sIy with respect to each other, different relative
timings in MCU and DG operatioFl are possible,
some of which result in error conditions. The
lack of appropriate termination commands for
'tow or frame data in the datastream also gives
rise to certain error conditions. These types of
situations occurring in display process operation are described below.,.
,
In normal operation, DG initiates a buffer swap
at the physical end of a display row. If the MCU
has not finished loading its row buffer by that
time, a "Data Underrun" occurs. This results in
8-182
210921-002
inter
82730
blanking of the screen until physical endofframe
by DG and execution·of an EOF (End of Frame)
command by MCU. Data underrun also occurs
when the first row of the frame has not finished
loading by the start of the character field. The
entire frame wilJ be blanked in this case.
Virtual Display In Progress
Display In Progress
Reserved Channel Command
Reserved Datastream Command
Frame Data Error
VDIP:
DIP:
RCC:
ROC:
FOE:
OUR:
If a physical end of frame is reached prior to
encountering an EOF datastream command, a
"Frame Data Error" occurs, which results in the
execution of an EOF command by MCU. (Note
that this does not disrupt the visible display
action, and may not constitute an errorforcertain
data structures. The error indication is included
as a flag where knowledge of this condition is
desired.) Similarly, when the MCU fills up a row
buffer completely, wit.hout encountering a ENDROW command, the "Data Buffer Overrun" flag is
set.
All of the above conditions result in the setting of
an appropriate status bit and generation of an
interrupt ,f the corresponding interrupt has been
enabled.
15
9
(RESERVED)
8
VDIP
7
DIP
6
ROC
Data Under Run
This status bit is set by Display Generator if the
Microcontroller Unit (MOU) has not finished
, loading its Row Buffer when the DG initiates a
buffer swap at the physical end of.a display row.
This conditi.on is defined as data underrun and
causes the MCU to execute an EOF command
and the DG to blank the screen until the
phy~ical end of frame.
LPU:
Light Pen Update
This status bit is set by the MCU after updating
the LPENROW and LPENCOL locations in command block. The detection of LPEN input is
enabled by the LPEN ENABLE channel com-
5
RCC
4
FOE
321
EOF
DBOR
LPU
o
OUR
Status and Interrupt Handling
A status word is maintained in an internal register
by 82730 and it is written to the "STATUS"
location in command block when the "Read
Status" channel command is executed. The processor can thus read status' information by issuing
this command. the processor can also enable
interrupts for certain status bits by specifying an
interrupt mask which is loaded in 82730 as a
result of a "Load Int Mask" channel command.
This establishes a communication mechanism
between, 82730 and the processor for error and
status reporting.
Status Word
Tile format for the status word is shown below.
The function of each ofthe status bits is described
below.
The status bits get set under the conditions
described above. I nterrupts can be enabled for all
status bits except 01 P and VOl P bits. The interrupt
status bits are cleared at the beginning of each
new display field. DIP and VDIP bits are cleared
only after receiving a "STOP DISPLAY" command
or a Reset.
All status bits are cleared by.a Reset.
. 8-183
EOF:
DBOR:
LPU:
OUR:
End of Frame
End 'of Row
Light Pen Update
Data Under Run
mand. The detection of a rising edge on the
LPEN input causes the current row and column
position to be stored internally. The MCU
updates the LPEN ROWand ,LPEN CQL locations in command block at the next end of frame
and sets the LPU status bit. Further updates of
these command block locations are inhibited
until another LPEN ENABLE command is issued.
DBDR:
Data Buffer Over Run
This status bit is set when the MCU tries to fill a
row buffer beyond its capacity. The MCU will
stop fetching characters after this pOint and the
display is blanked following the completion of
the row currently being displayed.
210921-002
inter
·82130
EOF: End of Frame
This bit is set by the DGat the physical end:bf
the nth frame, where 'n' is specified by the
MODESET parameter FRAME INTERAt'JPT
,COUNT. This provides the means for timing
frame related events such as'slow scrolls.
Interruj)t. Processing.
The system processor can enable interrupts on
any of the st8:tus bits, with the exception of 01 P
and VDIP bits, by specifying an interrupt mask.
A "1" in a bit position in the interrupt mask
disables (masks out) interrupts on the status bit
located in the corresponding bit position in the
status word. The ,format for Interrupt Mask is
FOE: Frarpe Data Error
showl1 below. The Int Mask can be loaded into
This status bit is set by the DG at the physical
82730 from the INTMASK location in command
·end ·of frame jf no EOS datastream command . block by a "Load Inf'Mask" channel command.
has been encountered until· then .. T.his also
If the Interrupt is enal;lled for it particular status
results in the execution of the EOS command
bit by programming a "0" in the corresponding
by the MCU.
bit position in INTMASK and if the status bit
gets set during the course of the display, an
RCC: Reserved Channel Command
interrupt will be generated by 82730 at the nelC'!
A.C. TESTING INPUT, OUTPUT WAVEFORM
\
/
/
\
A.C. TESTING LOAD CIRCUIT
INPUT OUTPUT
: .:=x;:: >"" ~'"" <::>e
DEVICE
UNDER
TEST
'lee
-=-
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOA A lOGIC 1 AND 0 4'>V FOR
A lOGIC 0 TIMING MEASUREMENTS ARE MADE AT 20V FDA A LQGJC 1
AND 0 8V FDA A lOGIC 0
C l INCLUDES JIG CAPACITANCE
8-198
210921-002
inter
82731
VIDEO INTERFACE CONTROLLER
•
•
•
•
•
Parallel to Serial Data Conversion
On·Chlp Clock Generator
High Video Dot Rates
SO MHz-S2731-2
50 MHz--S 2,731
Character up to 16 Dots Wide
Proportional Character Spacing
•
•
•
•
•
On· Chip Character Attribute Processing
Control Functions to Provide Screen
Reverse Video, Video Clock,
Synchronization and Tab Function
Single 5V Power Supply
40 Pin DIP
All Inputs and Outputs TTL Compatible
Except Video Output which is ECl
The 82731 is a general purpose video interface which generates a serial video signal output from parallel
character and attribute information coming from the character generator and the 82730 Text Coprocessor.
With a character generator and minimal hardware, the 82731 will comprise a complete video interface
system for the 82730 Text Coprocessor and the CRT monitor.
CBLANK---+-i
..
vee
.
GNO
CRVV---+!
ow---+-i
ATTRIBUTE
REGISTER
HOOT---+!
RRVV---+I
ATTRIBUTE
PROCESSING
00-015
VIDEO
16-BIT
SHIFT
REGISTER
07
Vee
06
08
05
09
04
010
03
011
02
012
01
013
DO
014
PROG
015
VIDEO
T2
RCLK
T1
CCLK
VT
HOOT
X2
CBLANK
WOEF
RCLK
00-07
CCLK
WG-W3 _ _--,1/
PROG---+I
CCLKJ
RCLK
REGISTER &
GENERATOR
CSYN---+i
WOEF---"-+i
DOT
OSCILLATOR
PLL
CLOCK
CRVV
RRVV
OW
CSYN
WO
~
X1
W1
W3
X2
GNO
W2
VT
T1
CHOLO---'--+i
X1
OCLK
T2
Figure 2. 82731 Pin
Configuration
Figure 1. 82731 Block Diagram .
Intel Corporation Assumes No Responsibility for the Use of Any Circuitry Other Than Circuitry Emb<>died in an Intel Product. N<> Other Circuit
•
NOVEMBER 1983
Patent Licenses are Implied.
©INTEL CORPORATION, 1983.
Order Number: 210925-003
8-199
inter
82731
TIIble
1.
82731 Pin Description
Pin Number
"lYpe
00-015
8-1,39-32
'1
Character data parallel inputs.
PROG
9
I
Program contro; input; used to program default width
values of CCLK and RCLK; these are latched into the
82731 via 00-07 at the rising edge of CCLK (PROG is
active high).
10
0
Video output; provides the dot infor.mation olocked by
the internal dot clock
11
0
Reference Clock output; used to generate timings for
the screen columns for data formatting and video signals. The period of RCLK is programmable from 8 to
21 times the period of the internal dot clock.
12
.0
Character clock output; used to clock character and
attribute information out of the CRT controller. The
period of CCLK is programmable from 3 to 18 times
the period of the internal dot clock.
HOOT
13
I
CBLANK
14
I
Character blank attribute Input; the video output is
bl;anked (active high).
WOEF
15
I
Width defeat attribute input; the CCLK period is set to
a preprogrammed default value (active high).
. CRVV
16
I
Character reverse video attribute input; inverts the
character data from 00-015 (active high).
OW
17
I
Double width attribute input; the internal dot clock
frequency and the CCLK frequency are divided by
two (active high); The RCLK frequency rem~ins
unchanged.
WO-W3
18,19,21,22
I
Clock width inputs; they are used for programming
the CCLK clock width on a'character by character
basis.
CHO'LD
23
I
CCLK Inhibit input; thiS signal inhibits CCLK
generation and is used for TAB function (active low).
CSYN
24
I
CCLK synchronization Input; CCLK will be
synchronized to RCLK and the video output sigl)al is
defined by RRVV (active high).
RRVV
25
I
'Field reverse video input; the video signal at the video
.
output will be inverted (active high).
OCLK
26
0
Dot clock output; ECL-Ievel signal; must be canneoted to a 3.3k resistor to ground if used.
Xl-X2
27. 28
I
Inputs for fundamental mode crystal; its frequency
must be 1/8 of the required dot clock frequency.
29
0
Tuning voltage for PLL-VCO; this output is used to
tune the LC-circuit and thus control the oscillator frequency of the internal dot clock.
Symbol
VIDEO
RCLK
CCLK
VT
•
Tl-T2
30, Sl
VCC
40
6NO
20
Name and Function
Half dot shift input; the video sigmil at the);~eo.output will be delayed by half dot clock for character
rounding (active high).
,
I
LC-circuit inputs for PLL-VCO. T1 can be used to
provide the 82731 with an external TTL-level. clock at
" twice the dot clock frequency.
-
. +5V power supply
Ground (OV) .
210925-003
inter
82131
The 16 bit shift register receives parallel inputs
from pins 00-015. This allows a maximum character width of 16 dots. The minimum width is 3
dots. The character width is programmable
through pins WO-W3 for proportional character
spacing. This also determines the character clock
(CCLK) frequency. Prc:>gramming of the default
character width and the reference clock (RCLK)
is done through inputs 00-07 and PROG. Signal
WOEF can be used to switch between the default
character width and the one specified dynamlcally through the lines WO-W3. When using variable
character width, for example, in generating tables
on the screen, it is essential that every entry in a
column starts at the same dot distance (and not
the character distance) from the. start of line. The
82731 supports this requirem~roviding a
tab function using CSYN and CHUrn signals to
synchronize with the reference clock ,
DEFINES THE CCLK
WIDTHAS3
AT (CCLKI), WDEF = 1
DEFINES CCLK WIDTH
AS THE DEFAULT VALUE (5)
IGNORING
AT (CCLKI)
DEFINES WIDTH OF CCLK
when WDEF = 0
The defaulf width of CCLK was previously defined as 5
Figure 10.
Function of WDEF
Tabulator Function
shows the normal case where the display of the
TAB-character is finfshed before deactivation of
CHOLD. The gap between the TAB- and the following character is normally blll:nked. In this sche~e
the TAB-character will be handled by the 82731 lik~
each other character (attributes operate normally).
The 82731 supports tabulator functions by providing the CHOLD (character clock inhibit) input.
CCLK Inhibit (CHOLD)
When the CHOLD signal is activated (low) it inhibits
CCLK and thus freezes the information pipeline
between CRT-controller and 8~tiI the next
tabulator location is reached. CHOLD Has to be
activated simultaneously with the display of the
TAB-character. If the TAB-character doesn't consist
of all zeros, it must be blanked by activating
CBLANK.
The'width of the TAB-character can be determined
by WO-W3 or by activatil"!g WDEF.
.The CHOLb signal is provided by the 82730 and it is
assumed to be triggered with the rising edge of
CCLK lFiqure 12). With the same edQe of CCLK, the
TAB-character will be latched into the 82731. Thus
the TAB-character will be displayed completely and
the CCLK will be inhibited until reaching the specified tabulator location, which is defined by CHOLD
inactive (high) at the rising edge of RCLK.
In case of CROL5 active width less than the TABcharacter width the TAB-character will be also displayed completely. However, we have to distinguish
three different cases:
1) TAB-character IS terminated before reaching
TAB-location. The next character will be displayed as described before. In the gap the video
output is normally blanked.
2) TAB-character is finished exactly at the TABlocation. The next character will be displayed
immediately without delay.
3) TAB-character is not terminated when
reaching the TAB-location (see Figure 13). The
following character -will be displayed subsequently after the display of the TAB-character
(i.e. the start of the following character is not at
the TAB-location).
In the timing diagrams it is assumed that CHOLD is
deactivated by the falling edge of RCLK. Figure 12
8-209
CHi5LD
If the
signal is not deactivated the video
output will be continuously blanked. In the gap
between the end of the TAB-character and th~ TABlocation all character attribute signals will have no
effect on the video output signal. If the RRVV control
s:Jnal is active the video output signal is inverted.
210925-003
(
CSYN
RCLK
:!!
-10
C
...
CiI
CCLK
:-'
W3 « « « « 0
00
~
o
2-
~
~
~
....
~
0"
-W2
«
TEST <~x=
o.a
POINTS
2.
o.s
Figure 19.
TTl-Level-O~tput
Figure 20. ECl-Level-Output load Circuit
load Circuit
TDHDH
TCHDX
Figure 21. Basic Timing
8-216
.210925-003
inter
82731
CCLK
RCLK -+-I....J
CHOLD-+-....oo:E.\.
t 4 - - - - - - - t - - TH L H H - - - - - - - - - + l
END OF TAB CHARACTER
BEGINNING OF TAB CHARACTER
BEGINNING OF NEXT
CHARACTER
Figure 22. Timing on CHOLD
CC
LC
8275
CCLK~---~----OC
8276
RW 1 - - - - - - - - - - - - - + _ - - - - - - + 0 1
uENI-------------+-.-----~
vspl------~---__,
HRCT~~---------~~--~
VRCTI----------~+_---L--'
Figure 23. Example lnterface to 8275
8-217
210925-003
Packaging
9
inter
PACKAGING INFORMATION
All dimensions In Inches and (millimeters)
NOTES:
All packages drawings not to scale
All packages seating plane defined by 0415 to .0430 PCB holes.
3 Type P packages only Package length does not Include end flash burr Burr is .005 nominal. can be 010 max at one end
4 All package drawings ~nd view dimenSions are to outside of leads.
PLASTIC DUAL IN-LINE PACKAGE TYPE P
1lt-LEAD PLASTIC DUAL IN·LlNE
PACKAGE TYPE P
1I1·LEAD PLASTIC DUAL IN·LINE
PACKAGE TYPE P
20·LEAD PLASTIC DUAL IN·LlNE
PACKAGE TYPE P
24-LEAD PLASTIC DUAL IN·LINE
PACKAGE TYPE P
9-1
inter
PLASTIC DUAL IN-LINE PACKAGE TYPE P
28-LEAD PLASTIC DUAL IN-LINE
PACKAGE TYPE P
o
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4O-LEAD PLASTIC DUAL IN-LINE
PACKAGE TYPE P
48-LEAD PLASTIC DUAL IN-LINE
PACKAGE TYPE P
CERAMIC DUAL IN·L1NE PACKAGE TYPE D
l6-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D
790(200661
t== ::'~:"'---P-'N~''''
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REF
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PACKAGING INFORMATION
CERAMIC DUAL IN·LINE PACKAGE TYPE D
18-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D
r---
1_ _ _ _
920 (23.000)
880 (22 352)
All dimensions in inches and (millimeters)
~
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310 (7 874)
265 (6.73',
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(8.128)
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SEATING
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(0254)
125(3175)
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032 TYP
(Oa13)
20-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D
! '1t
........
(10.160)
NOTE 4
990(25146) ~
950(24.130)
PIN 1
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125(3.175)
MIN.
032 TYP
(OS13)
22-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D
24-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D
r=
1096(27813) ~
1 060 (26 924)
PIN 1
1.285 (32.6391 ~
r - , . 2 3 5 (31.3691
1_
___
PIN1
l=-'=~=- - --"";';:"'1-
1
~~I;~g:~1
~
~~~j.lL'
C:::
(15,748)
.090~288)
---;---'T
,175(4,445)
~ .140(3,556)
lO2OMIN
II
,032 TV.
(0813)
9-3
' (.508)
-- .... 020 (0 5081
016 (04061
1:
(15.240)
-J
,
II
._..""
.010 T V P '
(0.2541
I
700
:
-,
~ MAX --.\
(17 780)
NOTE 4
W
REF
-PACKAGING INFORMATION
I
28-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D
-----~_ 1 485 (37719)
1 435 (36449)
All dimensions Ininch$s and"(mililmeters)
--------1
I
PIN
11
--1
600 (15.2401
515
(13:081) ,
__1
~~~t-il ,"
.
(33 020)
r-
PLANE
L F'l
f'"
- - - - - - .175(,4.445)
.140 (3 556)
F\.J.-.l_.---1
t
.-
125 (3 175)
MIN
i
-:
_, :____ 060 TYP
40-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D
'
1; __
~~28~;r
1
::
'I~
_. .
010 TYP
I I ' (0.508) .
r' "*" __
(1 524)
110 (2794)
090 (2286)
020 MIN
.620
~
lJ
MAX
MAX
S~A!!~_G
(15.748)
r
~.08~i2"59)·
1 300 REF
200 (5 (8)
:v fa-
"
I
(0254)
~ (0 508)
700
........
I
REF
i_ (1~~~O) ----I
016 (0 406)
NOTE 4
2080 (52832)
r--2030
(51562)~
1- _ _ _
40-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D
__ ~~I
E-o:~:~~ ~:t:L
515/13.081)
--.225(5.715) ._1900REF
MAX.
(49.548)
I
t '59)
·085M
~,
- II
_C-=-.::L
,, .. '
(15748)
620
~ [--'600,
(0.254)' (15.240)
jTl:::~:: ~L
010 TVP
t.02O MIN
.125 (3175)
MIN
110 (2 794)
I
090 (2 286) -l
032 TYP
(0813)
CERAMIC DUAL IN·LlNE PACKAGE TYPE C
40-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C
SEATING
PLANE
110 (2 794)
0901228£)
9-4
J
-II-
(508)
020 (0.508)
016 (0 406)
"
,
. (0254)
•
10'
-....:
REF
L J
,
700
.
MAX
(17 780)
NOTE 4
inter
PACKAGING INFORMATION
All dimensions in inches and (millimeters)
CERAMIC DUAL IN·LlNE PACKAGE TYPE C
48·LEAD PLASTIC DUAL IN·LlNE
PACKAGE TYPE C
o·
-;00
I
125 MIN
(16891)
I
~'6!~
(5175)
CERAMIC PIN GRID ARRAY PACKAGE TYPE CG
B8·LEAD CERAMIC PIN GRID ARRAY
PACKAGE TYPE CG
9-5
.....
, 1
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2014:07:17 10:53:23-08:00 Modify Date : 2014:07:17 10:50:26-07:00 Metadata Date : 2014:07:17 10:50:26-07:00 Producer : Adobe Acrobat 9.55 Paper Capture Plug-in Format : application/pdf Document ID : uuid:02242be7-22b5-504f-8cfa-68617efb19d3 Instance ID : uuid:9ee2e6c9-843d-3447-a9a9-527bf89e261e Page Layout : SinglePage Page Mode : UseNone Page Count : 1319EXIF Metadata provided by EXIF.tools